From 2b2c57a80d71ffeec182cc520e5a72af7b94778d Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Fri, 28 Feb 2020 09:46:47 +0100 Subject: Release v1.5.0 --- Drivers/BSP/NUCLEO-WB35CE/Release_Notes.html | 58 + Drivers/BSP/NUCLEO-WB35CE/_htmresc/mini-st.css | 1700 +++ Drivers/BSP/NUCLEO-WB35CE/_htmresc/st_logo.png | Bin 0 -> 18616 bytes Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c | 864 ++ Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.h | 301 + .../BSP/P-NUCLEO-WB55.Nucleo/Release_Notes.html | 9 +- .../BSP/P-NUCLEO-WB55.Nucleo/stm32wbxx_nucleo.c | 2 +- .../BSP/P-NUCLEO-WB55.Nucleo/stm32wbxx_nucleo.h | 12 - .../BSP/P-NUCLEO-WB55.USBDongle/Release_Notes.html | 9 +- .../P-NUCLEO-WB55.USBDongle/stm32wbxx_usb_dongle.c | 2 +- .../P-NUCLEO-WB55.USBDongle/stm32wbxx_usb_dongle.h | 4 - .../Device/ST/STM32WBxx/Include/stm32wb30xx.h | 11130 +++++++++++++++ .../Device/ST/STM32WBxx/Include/stm32wb35xx.h | 12767 +++++++++++++++++ .../Device/ST/STM32WBxx/Include/stm32wb50xx.h | 209 +- .../Device/ST/STM32WBxx/Include/stm32wb55xx.h | 135 +- .../Device/ST/STM32WBxx/Include/stm32wb5mxx.h | 13677 +++++++++++++++++++ .../CMSIS/Device/ST/STM32WBxx/Include/stm32wbxx.h | 8 +- .../Device/ST/STM32WBxx/Include/system_stm32wbxx.h | 2 +- .../CMSIS/Device/ST/STM32WBxx/Release_Notes.html | 74 +- .../Templates/arm/linker/stm32wb30xx_flash_cm4.sct | 21 + .../Templates/arm/linker/stm32wb35xx_flash_cm4.sct | 21 + .../Templates/arm/linker/stm32wb5mxx_flash_cm4.sct | 21 + .../Source/Templates/arm/startup_stm32wb30xx_cm4.s | 330 + .../Source/Templates/arm/startup_stm32wb35xx_cm4.s | 364 + .../Source/Templates/arm/startup_stm32wb5mxx_cm4.s | 368 + .../Templates/gcc/linker/stm32wb30xx_flash_cm4.ld | 187 + .../Templates/gcc/linker/stm32wb35xx_flash_cm4.ld | 187 + .../Templates/gcc/linker/stm32wb5mxx_flash_cm4.ld | 187 + .../Source/Templates/gcc/startup_stm32wb30xx_cm4.s | 388 + .../Source/Templates/gcc/startup_stm32wb35xx_cm4.s | 439 + .../Source/Templates/gcc/startup_stm32wb5mxx_cm4.s | 445 + .../Templates/iar/linker/stm32wb30xx_flash_cm4.icf | 40 + .../Templates/iar/linker/stm32wb30xx_sram_cm4.icf | 39 + .../Templates/iar/linker/stm32wb35xx_flash_cm4.icf | 40 + .../Templates/iar/linker/stm32wb35xx_sram_cm4.icf | 39 + .../Templates/iar/linker/stm32wb5mxx_flash_cm4.icf | 40 + .../Templates/iar/linker/stm32wb5mxx_sram_cm4.icf | 39 + .../Source/Templates/iar/startup_stm32wb30xx_cm4.s | 422 + .../Source/Templates/iar/startup_stm32wb35xx_cm4.s | 507 + .../Source/Templates/iar/startup_stm32wb5mxx_cm4.s | 517 + .../STM32WBxx/Source/Templates/system_stm32wbxx.c | 4 +- .../Inc/Legacy/stm32_hal_legacy.h | 66 +- Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h | 27 +- .../STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_adc.h | 4 +- .../STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_exti.h | 27 +- .../STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash.h | 6 +- .../Inc/stm32wbxx_hal_gpio_ex.h | 240 +- .../STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2s.h | 546 + .../STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr.h | 41 +- .../Inc/stm32wbxx_hal_pwr_ex.h | 71 +- .../STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc.h | 25 +- .../Inc/stm32wbxx_hal_rcc_ex.h | 143 +- .../STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h | 85 +- .../STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h | 28 +- .../STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_comp.h | 4 +- .../STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_exti.h | 279 +- .../STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_lptim.h | 51 +- .../STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rcc.h | 173 +- .../STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_spi.h | 866 ++ .../STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_system.h | 33 + .../STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h | 46 +- Drivers/STM32WBxx_HAL_Driver/Release_Notes.html | 74 +- Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c | 43 +- .../STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c | 6 +- .../Src/stm32wbxx_hal_flash_ex.c | 37 +- .../STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c | 54 +- .../STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c | 220 +- .../STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2s.c | 1802 +++ .../STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_irda.c | 56 +- .../STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c | 161 +- .../STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pka.c | 39 - .../STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c | 186 +- .../Src/stm32wbxx_hal_rcc_ex.c | 636 +- .../Src/stm32wbxx_hal_smartcard.c | 80 +- .../STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c | 14 +- .../STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c | 19 +- .../STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c | 21 +- .../STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lptim.c | 38 +- .../STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c | 85 +- .../STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c | 250 + .../STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c | 2 +- .../STM32_TouchSensing_Library/Release_Notes.html | 67 + .../ST/STM32_TouchSensing_Library/inc/tsl.h | 2 - .../ST/STM32_TouchSensing_Library/inc/tsl_acq.h | 2 - .../inc/tsl_acq_stm32l1xx_hw.h | 2 - .../inc/tsl_acq_stm32l1xx_sw.h | 2 - .../STM32_TouchSensing_Library/inc/tsl_acq_tsc.h | 2 - .../inc/tsl_check_config.h | 2 - .../inc/tsl_check_config_stm32l1xx.h | 48 +- .../inc/tsl_check_config_tsc.h | 2 - .../inc/tsl_conf_stm32l1xx_template.h | 2 - .../inc/tsl_conf_tsc_template.h | 2 - .../ST/STM32_TouchSensing_Library/inc/tsl_dxs.h | 2 - .../ST/STM32_TouchSensing_Library/inc/tsl_ecs.h | 2 - .../ST/STM32_TouchSensing_Library/inc/tsl_filter.h | 2 - .../STM32_TouchSensing_Library/inc/tsl_globals.h | 2 - .../ST/STM32_TouchSensing_Library/inc/tsl_linrot.h | 2 - .../ST/STM32_TouchSensing_Library/inc/tsl_object.h | 2 - .../ST/STM32_TouchSensing_Library/inc/tsl_time.h | 2 - .../STM32_TouchSensing_Library/inc/tsl_touchkey.h | 2 - .../ST/STM32_TouchSensing_Library/inc/tsl_types.h | 2 - .../ST/STM32_TouchSensing_Library/src/tsl.c | 2 - .../ST/STM32_TouchSensing_Library/src/tsl_acq.c | 6 +- .../src/tsl_acq_stm32l1xx_hw.c | 4 +- .../src/tsl_acq_stm32l1xx_sw.c | 18 +- .../STM32_TouchSensing_Library/src/tsl_acq_tsc.c | 4 +- .../ST/STM32_TouchSensing_Library/src/tsl_dxs.c | 2 - .../ST/STM32_TouchSensing_Library/src/tsl_ecs.c | 2 - .../ST/STM32_TouchSensing_Library/src/tsl_filter.c | 2 - .../STM32_TouchSensing_Library/src/tsl_globals.c | 2 - .../ST/STM32_TouchSensing_Library/src/tsl_linrot.c | 6 - .../ST/STM32_TouchSensing_Library/src/tsl_object.c | 2 - .../ST/STM32_TouchSensing_Library/src/tsl_time.c | 2 - .../STM32_TouchSensing_Library/src/tsl_touchkey.c | 6 - Middlewares/ST/STM32_WPAN/Release_Notes.html | 57 +- .../ST/STM32_WPAN/ble/core/auto/ble_events.c | 150 +- .../ST/STM32_WPAN/ble/core/auto/ble_events.h | 12 +- .../ST/STM32_WPAN/ble/core/auto/ble_hal_aci.h | 8 +- .../ST/STM32_WPAN/ble/core/auto/ble_hci_le.c | 8 +- .../ST/STM32_WPAN/ble/core/auto/ble_hci_le.h | 6 +- .../ST/STM32_WPAN/ble/core/auto/ble_types.h | 10 +- Middlewares/ST/STM32_WPAN/ble/core/ble_bufsize.h | 36 +- Middlewares/ST/STM32_WPAN/ble/core/ble_legacy.h | 10 + .../core/doc/STM32WB_BLE_Wireless_Interface.html | 18 +- .../ST/STM32_WPAN/ble/mesh/Inc/appli_test.h | 14 +- Middlewares/ST/STM32_WPAN/ble/mesh/Inc/ble_clock.h | 4 +- Middlewares/ST/STM32_WPAN/ble/mesh/Inc/ble_mesh.h | 218 +- Middlewares/ST/STM32_WPAN/ble/mesh/Inc/pal_if.h | 4 +- Middlewares/ST/STM32_WPAN/ble/mesh/Inc/pal_nvm.h | 9 +- .../ST/STM32_WPAN/ble/mesh/Inc/serial_ctrl.h | 8 +- Middlewares/ST/STM32_WPAN/ble/mesh/Inc/serial_if.h | 4 +- .../ST/STM32_WPAN/ble/mesh/Inc/serial_prvn.h | 7 +- Middlewares/ST/STM32_WPAN/ble/mesh/Inc/serial_ut.h | 4 +- Middlewares/ST/STM32_WPAN/ble/mesh/Inc/types.h | 6 +- .../ble/mesh/Library/libBle_Mesh_CM4_GCC.a | Bin 263996 -> 358334 bytes .../ble/mesh/Library/libBle_Mesh_CM4_GCC_DEBUG.a | Bin 0 -> 3713088 bytes .../ble/mesh/Library/libBle_Mesh_CM4_IAR.a | Bin 446102 -> 500654 bytes .../ble/mesh/Library/libBle_Mesh_CM4_IAR_DEBUG.a | Bin 0 -> 2726184 bytes .../mesh/Library/libBle_Mesh_CM4_IAR_DEBUG_NOD.a | Bin 0 -> 2602012 bytes .../mesh/Library/libBle_Mesh_CM4_IAR_DEBUG_PROV.a | Bin 0 -> 2664350 bytes .../ble/mesh/Library/libBle_Mesh_CM4_IAR_NOD.a | Bin 0 -> 485660 bytes .../ble/mesh/Library/libBle_Mesh_CM4_IAR_PROV.a | Bin 0 -> 494878 bytes .../ble/mesh/Library/libBle_Mesh_CM4_Keil.lib | Bin 478558 -> 525496 bytes .../mesh/Library/libBle_Mesh_CM4_Keil_DEBUG.lib | Bin 0 -> 3620812 bytes .../ST/STM32_WPAN/ble/mesh/MeshModel/Inc/blob.h | 4 +- .../ST/STM32_WPAN/ble/mesh/MeshModel/Inc/common.h | 16 +- .../ble/mesh/MeshModel/Inc/config_client.h | 155 +- .../ST/STM32_WPAN/ble/mesh/MeshModel/Inc/generic.h | 24 +- .../ble/mesh/MeshModel/Inc/generic_client.h | 11 +- .../ST/STM32_WPAN/ble/mesh/MeshModel/Inc/light.h | 42 +- .../ble/mesh/MeshModel/Inc/light_client.h | 92 + .../STM32_WPAN/ble/mesh/MeshModel/Inc/light_lc.h | 32 +- .../ble/mesh/MeshModel/Inc/meshdfu_node.h | 4 +- .../ST/STM32_WPAN/ble/mesh/MeshModel/Inc/sensors.h | 24 +- .../STM32_WPAN/ble/mesh/MeshModel/Inc/time_scene.h | 12 +- .../ST/STM32_WPAN/ble/mesh/MeshModel/Inc/vendor.h | 19 +- .../ST/STM32_WPAN/ble/mesh/MeshModel/Src/blob.c | 4 +- .../ST/STM32_WPAN/ble/mesh/MeshModel/Src/common.c | 207 +- .../ble/mesh/MeshModel/Src/config_client.c | 293 +- .../ST/STM32_WPAN/ble/mesh/MeshModel/Src/generic.c | 310 +- .../ble/mesh/MeshModel/Src/generic_client.c | 101 +- .../ST/STM32_WPAN/ble/mesh/MeshModel/Src/light.c | 965 +- .../ble/mesh/MeshModel/Src/light_client.c | 231 + .../STM32_WPAN/ble/mesh/MeshModel/Src/light_lc.c | 116 +- .../ble/mesh/MeshModel/Src/meshdfu_node.c | 4 +- .../ST/STM32_WPAN/ble/mesh/MeshModel/Src/sensors.c | 44 +- .../STM32_WPAN/ble/mesh/MeshModel/Src/time_scene.c | 52 +- .../ST/STM32_WPAN/ble/mesh/MeshModel/Src/vendor.c | 194 +- .../ST/STM32_WPAN/ble/mesh/Src/appli_test.c | 300 +- Middlewares/ST/STM32_WPAN/ble/mesh/Src/mesh_cfg.c | 325 +- .../ST/STM32_WPAN/ble/mesh/Src/serial_ctrl.c | 150 +- Middlewares/ST/STM32_WPAN/ble/mesh/Src/serial_if.c | 38 +- .../ST/STM32_WPAN/ble/mesh/Src/serial_prvn.c | 128 +- .../ST/STM32_WPAN/ble/svc/Src/bvopus_service_stm.c | 1 - Middlewares/ST/STM32_WPAN/ble/svc/Src/mesh.c | 65 +- .../STM32_WPAN/interface/patterns/ble_thread/hw.h | 12 +- .../interface/patterns/ble_thread/shci/shci.c | 22 + .../interface/patterns/ble_thread/shci/shci.h | 45 +- .../interface/patterns/ble_thread/tl/hci_tl.c | 28 + .../interface/patterns/ble_thread/tl/hci_tl.h | 28 +- .../interface/patterns/ble_thread/tl/mbox_def.h | 4 +- .../interface/patterns/ble_thread/tl/shci_tl.c | 29 + .../interface/patterns/ble_thread/tl/shci_tl.h | 19 +- .../interface/patterns/ble_thread/tl/tl.h | 10 +- .../interface/patterns/ble_thread/tl/tl_mbox.c | 50 +- .../patterns/ble_thread/tl/tl_zigbee_hci.c | 2 +- .../patterns/ble_thread/tl/tl_zigbee_hci.h | 2 +- .../mac_802_15_4/core/src/mac_802_15_4_core_wb.c | 3 - .../zigbee/core/inc/stm32wbxx_core_interface_def.h | 10 +- .../ST/STM32_WPAN/zigbee/core/src/zigbee_core_wb.c | 625 +- .../STM32_WPAN/zigbee/lib/stm32wb_zigbee_wb_lib.a | Bin 438816 -> 3011600 bytes .../STM32_WPAN/zigbee/platform/flash_emulation.h | 6 + .../zigbee/stack/include/extras/zigbee.extras.h | 32 + .../zigbee/stack/include/zcl/key/zcl.cbke.h | 4 +- .../zigbee/stack/include/zcl/se/zcl.message.h | 188 + .../stack/include/zcl/security/zcl.ias_ace.h | 414 + .../zigbee/stack/include/zcl/security/zcl.ias_wd.h | 124 + .../stack/include/zcl/security/zcl.ias_zone.h | 241 + .../zigbee/stack/include/zcl/zcl.alarm.h | 118 + .../zigbee/stack/include/zcl/zcl.ballast.config.h | 156 + .../zigbee/stack/include/zcl/zcl.basic.h | 144 + .../zigbee/stack/include/zcl/zcl.device.temp.h | 77 + .../ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.h | 62 +- .../zigbee/stack/include/zcl/zcl.identify.h | 4 +- .../zigbee/stack/include/zcl/zcl.illum.meas.h | 72 + .../zigbee/stack/include/zcl/zcl.meter.id.h | 62 + .../zigbee/stack/include/zcl/zcl.occupancy.h | 63 + .../zigbee/stack/include/zcl/zcl.onoff.h | 14 +- .../zigbee/stack/include/zcl/zcl.power.profile.h | 328 + .../zigbee/stack/include/zcl/zcl.press.meas.h | 44 + .../zigbee/stack/include/zcl/zcl.temp.meas.h | 64 + .../zigbee/stack/include/zcl/zcl.therm.ui.h | 43 + .../STM32_WPAN/zigbee/stack/include/zcl/zcl.time.h | 96 + .../zigbee/stack/include/zcl/zcl.touchlink.h | 91 +- .../zigbee/stack/include/zgp/zgp.proxybasic.h | 268 + .../STM32_WPAN/zigbee/stack/include/zigbee.aps.h | 8 +- .../STM32_WPAN/zigbee/stack/include/zigbee.bdb.h | 19 +- .../ST/STM32_WPAN/zigbee/stack/include/zigbee.h | 192 +- .../STM32_WPAN/zigbee/stack/include/zigbee.nwk.h | 21 +- .../zigbee/stack/include/zigbee.security.h | 50 +- .../zigbee/stack/include/zigbee.startup.h | 48 +- .../STM32_WPAN/zigbee/stack/include/zigbee.zdo.h | 172 +- .../STM32_WPAN/zigbee/stack/include/zigbee.zgp.h | 2 +- .../src/drivers/sd_diskio_dma_rtos_template.c | 484 - .../drivers/sd_diskio_dma_rtos_template_bspv1.c | 656 + .../drivers/sd_diskio_dma_rtos_template_bspv2.c | 655 + .../FatFs/src/drivers/sd_diskio_dma_template.c | 491 - .../src/drivers/sd_diskio_dma_template_bspv1.c | 499 + .../src/drivers/sd_diskio_dma_template_bspv2.c | 493 + .../FatFs/src/drivers/sd_diskio_template.c | 225 - .../FatFs/src/drivers/sd_diskio_template_bspv1.c | 226 + .../FatFs/src/drivers/sd_diskio_template_bspv2.c | 238 + .../FatFs/src/drivers/sdram_diskio_template.c | 181 - .../src/drivers/sdram_diskio_template_bspv1.c | 182 + .../src/drivers/sdram_diskio_template_bspv2.c | 188 + .../FatFs/src/drivers/usbh_diskio_dma_template.c | 4 +- .../Third_Party/FatFs/src/ffconf_template.h | 42 +- Middlewares/Third_Party/FatFs/src/option/syscall.c | 39 + Middlewares/Third_Party/FatFs/src/st_readme.txt | 35 + .../Third_Party/FreeRTOS/License/license.txt | 2 +- .../FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c | 8 +- .../FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h | 281 +- .../FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os1.c | 368 - .../FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c | 159 +- Middlewares/Third_Party/FreeRTOS/Source/croutine.c | 6 +- .../Third_Party/FreeRTOS/Source/event_groups.c | 75 +- .../Third_Party/FreeRTOS/Source/include/FreeRTOS.h | 150 +- .../Source/include/FreeRTOSConfig_template.h | 4 +- .../FreeRTOS/Source/include/StackMacros.h | 4 +- .../Third_Party/FreeRTOS/Source/include/croutine.h | 4 +- .../Source/include/deprecated_definitions.h | 4 +- .../FreeRTOS/Source/include/event_groups.h | 9 +- .../Third_Party/FreeRTOS/Source/include/list.h | 13 +- .../FreeRTOS/Source/include/message_buffer.h | 24 +- .../FreeRTOS/Source/include/mpu_prototypes.h | 210 +- .../FreeRTOS/Source/include/mpu_wrappers.h | 13 +- .../Third_Party/FreeRTOS/Source/include/portable.h | 24 +- .../Third_Party/FreeRTOS/Source/include/projdefs.h | 4 +- .../Third_Party/FreeRTOS/Source/include/queue.h | 20 +- .../Third_Party/FreeRTOS/Source/include/semphr.h | 4 +- .../FreeRTOS/Source/include/stack_macros.h | 12 +- .../FreeRTOS/Source/include/stream_buffer.h | 13 +- .../Third_Party/FreeRTOS/Source/include/task.h | 123 +- .../Third_Party/FreeRTOS/Source/include/timers.h | 24 +- Middlewares/Third_Party/FreeRTOS/Source/list.c | 34 +- .../FreeRTOS/Source/portable/Common/mpu_wrappers.c | 317 +- .../FreeRTOS/Source/portable/GCC/ARM_CM0/port.c | 6 +- .../Source/portable/GCC/ARM_CM0/portmacro.h | 6 +- .../Source/portable/GCC/ARM_CM23/non_secure/port.c | 899 ++ .../portable/GCC/ARM_CM23/non_secure/portasm.c | 468 + .../portable/GCC/ARM_CM23/non_secure/portasm.h | 113 + .../portable/GCC/ARM_CM23/non_secure/portmacro.h | 299 + .../portable/GCC/ARM_CM23/secure/secure_context.c | 204 + .../portable/GCC/ARM_CM23/secure/secure_context.h | 111 + .../GCC/ARM_CM23/secure/secure_context_port.c | 91 + .../portable/GCC/ARM_CM23/secure/secure_heap.c | 450 + .../portable/GCC/ARM_CM23/secure/secure_heap.h | 51 + .../portable/GCC/ARM_CM23/secure/secure_init.c | 105 + .../portable/GCC/ARM_CM23/secure/secure_init.h | 53 + .../GCC/ARM_CM23/secure/secure_port_macros.h | 133 + .../portable/GCC/ARM_CM23_NTZ/non_secure/port.c | 899 ++ .../portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c | 381 + .../portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h | 113 + .../GCC/ARM_CM23_NTZ/non_secure/portmacro.h | 299 + .../FreeRTOS/Source/portable/GCC/ARM_CM3/port.c | 4 +- .../Source/portable/GCC/ARM_CM3/portmacro.h | 5 +- .../Source/portable/GCC/ARM_CM33/non_secure/port.c | 899 ++ .../portable/GCC/ARM_CM33/non_secure/portasm.c | 415 + .../portable/GCC/ARM_CM33/non_secure/portasm.h | 113 + .../portable/GCC/ARM_CM33/non_secure/portmacro.h | 299 + .../portable/GCC/ARM_CM33/secure/secure_context.c | 204 + .../portable/GCC/ARM_CM33/secure/secure_context.h | 111 + .../GCC/ARM_CM33/secure/secure_context_port.c | 88 + .../portable/GCC/ARM_CM33/secure/secure_heap.c | 450 + .../portable/GCC/ARM_CM33/secure/secure_heap.h | 51 + .../portable/GCC/ARM_CM33/secure/secure_init.c | 105 + .../portable/GCC/ARM_CM33/secure/secure_init.h | 53 + .../GCC/ARM_CM33/secure/secure_port_macros.h | 133 + .../portable/GCC/ARM_CM33_NTZ/non_secure/port.c | 899 ++ .../portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c | 321 + .../portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h | 113 + .../GCC/ARM_CM33_NTZ/non_secure/portmacro.h | 299 + .../Source/portable/GCC/ARM_CM3_MPU/port.c | 72 +- .../Source/portable/GCC/ARM_CM3_MPU/portmacro.h | 37 +- .../FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c | 4 +- .../Source/portable/GCC/ARM_CM4F/portmacro.h | 5 +- .../Source/portable/GCC/ARM_CM4_MPU/port.c | 74 +- .../Source/portable/GCC/ARM_CM4_MPU/portmacro.h | 37 +- .../Source/portable/GCC/ARM_CM7/r0p1/port.c | 4 +- .../Source/portable/GCC/ARM_CM7/r0p1/portmacro.h | 5 +- .../Source/portable/GCC/ARM_CM7_MPU/r0p1/port.c | 170 +- .../portable/GCC/ARM_CM7_MPU/r0p1/portmacro.h | 53 +- .../FreeRTOS/Source/portable/IAR/ARM_CM0/port.c | 4 +- .../FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s | 4 +- .../Source/portable/IAR/ARM_CM0/portmacro.h | 4 +- .../Source/portable/IAR/ARM_CM23/non_secure/port.c | 899 ++ .../portable/IAR/ARM_CM23/non_secure/portasm.h | 113 + .../portable/IAR/ARM_CM23/non_secure/portasm.s | 377 + .../portable/IAR/ARM_CM23/non_secure/portmacro.h | 306 + .../portable/IAR/ARM_CM23/secure/secure_context.c | 204 + .../portable/IAR/ARM_CM23/secure/secure_context.h | 111 + .../IAR/ARM_CM23/secure/secure_context_port.c | 48 + .../IAR/ARM_CM23/secure/secure_context_port_asm.s | 76 + .../portable/IAR/ARM_CM23/secure/secure_heap.c | 450 + .../portable/IAR/ARM_CM23/secure/secure_heap.h | 51 + .../portable/IAR/ARM_CM23/secure/secure_init.c | 105 + .../portable/IAR/ARM_CM23/secure/secure_init.h | 53 + .../IAR/ARM_CM23/secure/secure_port_macros.h | 133 + .../portable/IAR/ARM_CM23_NTZ/non_secure/port.c | 899 ++ .../portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h | 113 + .../portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s | 303 + .../IAR/ARM_CM23_NTZ/non_secure/portmacro.h | 306 + .../FreeRTOS/Source/portable/IAR/ARM_CM3/port.c | 4 +- .../FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s | 4 +- .../Source/portable/IAR/ARM_CM3/portmacro.h | 10 +- .../Source/portable/IAR/ARM_CM33/non_secure/port.c | 899 ++ .../portable/IAR/ARM_CM33/non_secure/portasm.h | 113 + .../portable/IAR/ARM_CM33/non_secure/portasm.s | 326 + .../portable/IAR/ARM_CM33/non_secure/portmacro.h | 306 + .../portable/IAR/ARM_CM33/secure/secure_context.c | 204 + .../portable/IAR/ARM_CM33/secure/secure_context.h | 111 + .../IAR/ARM_CM33/secure/secure_context_port.c | 48 + .../IAR/ARM_CM33/secure/secure_context_port_asm.s | 73 + .../portable/IAR/ARM_CM33/secure/secure_heap.c | 450 + .../portable/IAR/ARM_CM33/secure/secure_heap.h | 51 + .../portable/IAR/ARM_CM33/secure/secure_init.c | 105 + .../portable/IAR/ARM_CM33/secure/secure_init.h | 53 + .../IAR/ARM_CM33/secure/secure_port_macros.h | 133 + .../portable/IAR/ARM_CM33_NTZ/non_secure/port.c | 899 ++ .../portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h | 113 + .../portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s | 242 + .../IAR/ARM_CM33_NTZ/non_secure/portmacro.h | 306 + .../FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c | 4 +- .../Source/portable/IAR/ARM_CM4F/portasm.s | 4 +- .../Source/portable/IAR/ARM_CM4F/portmacro.h | 4 +- .../Source/portable/IAR/ARM_CM4_MPU/port.c | 52 +- .../Source/portable/IAR/ARM_CM4_MPU/portasm.s | 43 +- .../Source/portable/IAR/ARM_CM4_MPU/portmacro.h | 28 +- .../Source/portable/IAR/ARM_CM7/r0p1/port.c | 4 +- .../Source/portable/IAR/ARM_CM7/r0p1/portasm.s | 4 +- .../Source/portable/IAR/ARM_CM7/r0p1/portmacro.h | 4 +- .../Source/portable/IAR/ARM_CM7_MPU/r0p1/port.c | 262 +- .../Source/portable/IAR/ARM_CM7_MPU/r0p1/portasm.s | 127 +- .../portable/IAR/ARM_CM7_MPU/r0p1/portmacro.h | 81 +- .../FreeRTOS/Source/portable/MemMang/heap_1.c | 5 +- .../FreeRTOS/Source/portable/MemMang/heap_2.c | 4 +- .../FreeRTOS/Source/portable/MemMang/heap_3.c | 4 +- .../FreeRTOS/Source/portable/MemMang/heap_4.c | 4 +- .../FreeRTOS/Source/portable/MemMang/heap_5.c | 4 +- .../FreeRTOS/Source/portable/RVDS/ARM_CM0/port.c | 6 +- .../Source/portable/RVDS/ARM_CM0/portmacro.h | 4 +- .../FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c | 4 +- .../Source/portable/RVDS/ARM_CM3/portmacro.h | 4 +- .../FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c | 4 +- .../Source/portable/RVDS/ARM_CM4F/portmacro.h | 4 +- .../Source/portable/RVDS/ARM_CM4_MPU/port.c | 68 +- .../Source/portable/RVDS/ARM_CM4_MPU/portmacro.h | 45 +- .../Source/portable/RVDS/ARM_CM7/r0p1/port.c | 4 +- .../Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h | 4 +- .../Source/portable/RVDS/ARM_CM7_MPU/r0p1/port.c | 347 +- .../portable/RVDS/ARM_CM7_MPU/r0p1/portmacro.h | 47 +- .../Source/portable/Tasking/ARM_CM4F/port.c | 4 +- .../Source/portable/Tasking/ARM_CM4F/port_asm.asm | 4 +- .../Source/portable/Tasking/ARM_CM4F/portmacro.h | 4 +- Middlewares/Third_Party/FreeRTOS/Source/queue.c | 281 +- .../Third_Party/FreeRTOS/Source/st_readme.txt | 31 + .../Third_Party/FreeRTOS/Source/stream_buffer.c | 214 +- Middlewares/Third_Party/FreeRTOS/Source/tasks.c | 611 +- Middlewares/Third_Party/FreeRTOS/Source/timers.c | 180 +- .../links_to_doc_pages_for_the_demo_projects.url | 5 - Middlewares/Third_Party/FreeRTOS/readme.txt | 0 .../BLE/BLE_HeartRate/Binary/BLE_HeartRate.hex | 1070 ++ .../BLE/BLE_HeartRate/Core/Inc/app_common.h | 114 + .../BLE/BLE_HeartRate/Core/Inc/app_conf.h | 530 + .../BLE/BLE_HeartRate/Core/Inc/app_debug.h | 45 + .../BLE/BLE_HeartRate/Core/Inc/app_entry.h | 69 + .../BLE/BLE_HeartRate/Core/Inc/hw_conf.h | 196 + .../BLE/BLE_HeartRate/Core/Inc/hw_if.h | 254 + .../Applications/BLE/BLE_HeartRate/Core/Inc/main.h | 75 + .../BLE/BLE_HeartRate/Core/Inc/stm32_lpm_if.h | 81 + .../BLE_HeartRate/Core/Inc/stm32wbxx_hal_conf.h | 354 + .../BLE/BLE_HeartRate/Core/Inc/stm32wbxx_it.h | 79 + .../BLE/BLE_HeartRate/Core/Inc/utilities_conf.h | 68 + .../BLE/BLE_HeartRate/Core/Src/app_debug.c | 361 + .../BLE/BLE_HeartRate/Core/Src/app_entry.c | 301 + .../BLE/BLE_HeartRate/Core/Src/hw_timerserver.c | 893 ++ .../BLE/BLE_HeartRate/Core/Src/hw_uart.c | 318 + .../Applications/BLE/BLE_HeartRate/Core/Src/main.c | 641 + .../BLE/BLE_HeartRate/Core/Src/stm32_lpm_if.c | 297 + .../BLE/BLE_HeartRate/Core/Src/stm32wbxx_hal_msp.c | 329 + .../BLE/BLE_HeartRate/Core/Src/stm32wbxx_it.c | 315 + .../BLE/BLE_HeartRate/Core/Src/system_stm32wbxx.c | 357 + .../BLE/BLE_HeartRate/EWARM/BLE_HeartRate.ewd | 1419 ++ .../BLE/BLE_HeartRate/EWARM/BLE_HeartRate.ewp | 1258 ++ .../BLE/BLE_HeartRate/EWARM/Project.eww | 7 + .../BLE_HeartRate/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../BLE_HeartRate/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../BLE/BLE_HeartRate/STM32_WPAN/App/app_ble.c | 1099 ++ .../BLE/BLE_HeartRate/STM32_WPAN/App/app_ble.h | 88 + .../BLE/BLE_HeartRate/STM32_WPAN/App/ble_conf.h | 104 + .../BLE_HeartRate/STM32_WPAN/App/ble_dbg_conf.h | 199 + .../BLE/BLE_HeartRate/STM32_WPAN/App/dis_app.c | 221 + .../BLE/BLE_HeartRate/STM32_WPAN/App/dis_app.h | 77 + .../BLE/BLE_HeartRate/STM32_WPAN/App/hrs_app.c | 230 + .../BLE/BLE_HeartRate/STM32_WPAN/App/hrs_app.h | 69 + .../BLE/BLE_HeartRate/STM32_WPAN/Target/hw_ipcc.c | 523 + .../Applications/BLE/BLE_HeartRate/readme.txt | 110 + .../Core/Inc/FreeRTOSConfig.h | 151 + .../BLE_HeartRateFreeRTOS/Core/Inc/app_common.h | 114 + .../BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_conf.h | 529 + .../BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_debug.h | 45 + .../BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_entry.h | 69 + .../BLE/BLE_HeartRateFreeRTOS/Core/Inc/hw_conf.h | 198 + .../BLE/BLE_HeartRateFreeRTOS/Core/Inc/hw_if.h | 254 + .../BLE/BLE_HeartRateFreeRTOS/Core/Inc/main.h | 75 + .../BLE_HeartRateFreeRTOS/Core/Inc/stm32_lpm_if.h | 81 + .../Core/Inc/stm32wbxx_hal_conf.h | 354 + .../BLE_HeartRateFreeRTOS/Core/Inc/stm32wbxx_it.h | 77 + .../Core/Inc/utilities_conf.h | 68 + .../BLE/BLE_HeartRateFreeRTOS/Core/Inc/vcp_conf.h | 53 + .../BLE/BLE_HeartRateFreeRTOS/Core/Src/app_debug.c | 360 + .../BLE/BLE_HeartRateFreeRTOS/Core/Src/app_entry.c | 336 + .../BLE_HeartRateFreeRTOS/Core/Src/freertos_port.c | 312 + .../Core/Src/hw_timerserver.c | 893 ++ .../BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_uart.c | 318 + .../BLE/BLE_HeartRateFreeRTOS/Core/Src/main.c | 723 + .../BLE_HeartRateFreeRTOS/Core/Src/stm32_lpm_if.c | 278 + .../Core/Src/stm32wbxx_hal_msp.c | 334 + .../Core/Src/stm32wbxx_hal_timebase_tim.c | 152 + .../BLE_HeartRateFreeRTOS/Core/Src/stm32wbxx_it.c | 296 + .../Core/Src/system_stm32wbxx.c | 357 + .../EWARM/BLE_HeartRateFreeRTOS.ewd | 1419 ++ .../EWARM/BLE_HeartRateFreeRTOS.ewp | 1339 ++ .../BLE/BLE_HeartRateFreeRTOS/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../BLE_HeartRateFreeRTOS/STM32_WPAN/App/app_ble.c | 1141 ++ .../BLE_HeartRateFreeRTOS/STM32_WPAN/App/app_ble.h | 88 + .../STM32_WPAN/App/ble_conf.h | 104 + .../STM32_WPAN/App/ble_dbg_conf.h | 199 + .../BLE_HeartRateFreeRTOS/STM32_WPAN/App/dis_app.c | 221 + .../BLE_HeartRateFreeRTOS/STM32_WPAN/App/dis_app.h | 77 + .../BLE_HeartRateFreeRTOS/STM32_WPAN/App/hrs_app.c | 256 + .../BLE_HeartRateFreeRTOS/STM32_WPAN/App/hrs_app.h | 69 + .../STM32_WPAN/Target/hw_ipcc.c | 523 + .../BLE/BLE_HeartRateFreeRTOS/readme.txt | 108 + .../BLE_HeartRate_ota/Binary/BLE_HeartRate_ota.bin | Bin 0 -> 17200 bytes .../BLE/BLE_HeartRate_ota/Core/Inc/app_common.h | 114 + .../BLE/BLE_HeartRate_ota/Core/Inc/app_conf.h | 530 + .../BLE/BLE_HeartRate_ota/Core/Inc/app_debug.h | 45 + .../BLE/BLE_HeartRate_ota/Core/Inc/app_entry.h | 69 + .../BLE/BLE_HeartRate_ota/Core/Inc/hw_conf.h | 196 + .../BLE/BLE_HeartRate_ota/Core/Inc/hw_if.h | 254 + .../BLE/BLE_HeartRate_ota/Core/Inc/main.h | 75 + .../BLE/BLE_HeartRate_ota/Core/Inc/stm32_lpm_if.h | 81 + .../Core/Inc/stm32wbxx_hal_conf.h | 354 + .../BLE/BLE_HeartRate_ota/Core/Inc/stm32wbxx_it.h | 79 + .../BLE_HeartRate_ota/Core/Inc/utilities_conf.h | 68 + .../BLE/BLE_HeartRate_ota/Core/Src/app_debug.c | 360 + .../BLE/BLE_HeartRate_ota/Core/Src/app_entry.c | 301 + .../BLE_HeartRate_ota/Core/Src/hw_timerserver.c | 893 ++ .../BLE/BLE_HeartRate_ota/Core/Src/hw_uart.c | 318 + .../BLE/BLE_HeartRate_ota/Core/Src/main.c | 641 + .../BLE/BLE_HeartRate_ota/Core/Src/stm32_lpm_if.c | 297 + .../BLE_HeartRate_ota/Core/Src/stm32wbxx_hal_msp.c | 329 + .../BLE/BLE_HeartRate_ota/Core/Src/stm32wbxx_it.c | 315 + .../BLE_HeartRate_ota/Core/Src/system_stm32wbxx.c | 356 + .../BLE_HeartRate_ota/EWARM/BLE_HeartRate_ota.ewd | 1419 ++ .../BLE_HeartRate_ota/EWARM/BLE_HeartRate_ota.ewp | 1257 ++ .../BLE/BLE_HeartRate_ota/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4_ota.icf | 44 + .../BLE/BLE_HeartRate_ota/STM32_WPAN/App/app_ble.c | 1094 ++ .../BLE/BLE_HeartRate_ota/STM32_WPAN/App/app_ble.h | 88 + .../BLE_HeartRate_ota/STM32_WPAN/App/ble_conf.h | 104 + .../STM32_WPAN/App/ble_dbg_conf.h | 199 + .../BLE/BLE_HeartRate_ota/STM32_WPAN/App/dis_app.c | 221 + .../BLE/BLE_HeartRate_ota/STM32_WPAN/App/dis_app.h | 77 + .../BLE/BLE_HeartRate_ota/STM32_WPAN/App/hrs_app.c | 230 + .../BLE/BLE_HeartRate_ota/STM32_WPAN/App/hrs_app.h | 69 + .../BLE_HeartRate_ota/STM32_WPAN/Target/hw_ipcc.c | 523 + .../Applications/BLE/BLE_HeartRate_ota/readme.txt | 124 + .../Applications/BLE/BLE_Ota/Binary/BLE_Ota.hex | 1125 ++ .../Applications/BLE/BLE_Ota/Core/Inc/app_common.h | 114 + .../Applications/BLE/BLE_Ota/Core/Inc/app_conf.h | 560 + .../Applications/BLE/BLE_Ota/Core/Inc/app_debug.h | 45 + .../Applications/BLE/BLE_Ota/Core/Inc/app_entry.h | 44 + .../Applications/BLE/BLE_Ota/Core/Inc/hw_conf.h | 246 + .../Applications/BLE/BLE_Ota/Core/Inc/hw_if.h | 254 + .../Applications/BLE/BLE_Ota/Core/Inc/main.h | 74 + .../BLE/BLE_Ota/Core/Inc/stm32_lpm_if.h | 81 + .../BLE/BLE_Ota/Core/Inc/stm32wbxx_hal_conf.h | 355 + .../BLE/BLE_Ota/Core/Inc/stm32wbxx_it.h | 62 + .../BLE/BLE_Ota/Core/Inc/utilities_conf.h | 68 + .../Applications/BLE/BLE_Ota/Core/Inc/vcp_conf.h | 53 + .../Applications/BLE/BLE_Ota/Core/Src/app_debug.c | 349 + .../Applications/BLE/BLE_Ota/Core/Src/app_entry.c | 456 + .../BLE/BLE_Ota/Core/Src/hw_timerserver.c | 893 ++ .../Applications/BLE/BLE_Ota/Core/Src/hw_uart.c | 471 + .../Applications/BLE/BLE_Ota/Core/Src/main.c | 337 + .../BLE/BLE_Ota/Core/Src/stm32_lpm_if.c | 297 + .../BLE/BLE_Ota/Core/Src/stm32wbxx_it.c | 182 + .../BLE/BLE_Ota/Core/Src/system_stm32wbxx.c | 550 + .../Applications/BLE/BLE_Ota/EWARM/BLE_Ota.ewd | 1419 ++ .../Applications/BLE/BLE_Ota/EWARM/BLE_Ota.ewp | 1273 ++ .../Applications/BLE/BLE_Ota/EWARM/Project.eww | 7 + .../BLE/BLE_Ota/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../BLE/BLE_Ota/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../BLE/BLE_Ota/STM32_WPAN/App/app_ble.c | 555 + .../BLE/BLE_Ota/STM32_WPAN/App/app_ble.h | 52 + .../BLE/BLE_Ota/STM32_WPAN/App/ble_conf.h | 66 + .../BLE/BLE_Ota/STM32_WPAN/App/ble_dbg_conf.h | 207 + .../BLE/BLE_Ota/STM32_WPAN/App/otas_app.c | 212 + .../BLE/BLE_Ota/STM32_WPAN/Target/hw_ipcc.c | 523 + .../Applications/BLE/BLE_Ota/readme.txt | 99 + .../Binary/BLE_TransparentMode.hex | 1173 ++ .../BLE/BLE_TransparentMode/Core/Inc/app_common.h | 114 + .../BLE/BLE_TransparentMode/Core/Inc/app_conf.h | 483 + .../BLE/BLE_TransparentMode/Core/Inc/app_debug.h | 45 + .../BLE/BLE_TransparentMode/Core/Inc/app_entry.h | 69 + .../BLE/BLE_TransparentMode/Core/Inc/hw_conf.h | 196 + .../BLE/BLE_TransparentMode/Core/Inc/hw_if.h | 254 + .../BLE/BLE_TransparentMode/Core/Inc/main.h | 75 + .../BLE_TransparentMode/Core/Inc/stm32_lpm_if.h | 81 + .../Core/Inc/stm32wbxx_hal_conf.h | 354 + .../BLE_TransparentMode/Core/Inc/stm32wbxx_it.h | 78 + .../BLE_TransparentMode/Core/Inc/utilities_conf.h | 68 + .../BLE/BLE_TransparentMode/Core/Src/app_debug.c | 361 + .../BLE/BLE_TransparentMode/Core/Src/app_entry.c | 283 + .../BLE_TransparentMode/Core/Src/hw_timerserver.c | 893 ++ .../BLE/BLE_TransparentMode/Core/Src/hw_uart.c | 318 + .../BLE/BLE_TransparentMode/Core/Src/main.c | 579 + .../BLE_TransparentMode/Core/Src/stm32_lpm_if.c | 297 + .../Core/Src/stm32wbxx_hal_msp.c | 227 + .../BLE_TransparentMode/Core/Src/stm32wbxx_it.c | 274 + .../Core/Src/system_stm32wbxx.c | 357 + .../EWARM/BLE_TransparentMode.ewd | 1419 ++ .../EWARM/BLE_TransparentMode.ewp | 1226 ++ .../BLE/BLE_TransparentMode/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../BLE_TransparentMode/STM32_WPAN/App/ble_conf.h | 92 + .../STM32_WPAN/App/ble_dbg_conf.h | 199 + .../BLE/BLE_TransparentMode/STM32_WPAN/App/tm.c | 538 + .../BLE/BLE_TransparentMode/STM32_WPAN/App/tm.h | 97 + .../STM32_WPAN/Target/hw_ipcc.c | 523 + .../BLE/BLE_TransparentMode/readme.txt | 89 + .../BLE/BLE_p2pClient/Binary/BLE_p2pClient.hex | 2049 +++ .../BLE/BLE_p2pClient/Core/Inc/app_common.h | 114 + .../BLE/BLE_p2pClient/Core/Inc/app_conf.h | 523 + .../BLE/BLE_p2pClient/Core/Inc/app_debug.h | 45 + .../BLE/BLE_p2pClient/Core/Inc/app_entry.h | 69 + .../BLE/BLE_p2pClient/Core/Inc/hw_conf.h | 196 + .../BLE/BLE_p2pClient/Core/Inc/hw_if.h | 254 + .../Applications/BLE/BLE_p2pClient/Core/Inc/main.h | 75 + .../BLE/BLE_p2pClient/Core/Inc/stm32_lpm_if.h | 81 + .../BLE_p2pClient/Core/Inc/stm32wbxx_hal_conf.h | 354 + .../BLE/BLE_p2pClient/Core/Inc/stm32wbxx_it.h | 78 + .../BLE/BLE_p2pClient/Core/Inc/utilities_conf.h | 68 + .../BLE/BLE_p2pClient/Core/Src/app_debug.c | 360 + .../BLE/BLE_p2pClient/Core/Src/app_entry.c | 299 + .../BLE/BLE_p2pClient/Core/Src/hw_timerserver.c | 893 ++ .../BLE/BLE_p2pClient/Core/Src/hw_uart.c | 318 + .../Applications/BLE/BLE_p2pClient/Core/Src/main.c | 641 + .../BLE/BLE_p2pClient/Core/Src/stm32_lpm_if.c | 297 + .../BLE/BLE_p2pClient/Core/Src/stm32wbxx_hal_msp.c | 329 + .../BLE/BLE_p2pClient/Core/Src/stm32wbxx_it.c | 304 + .../BLE/BLE_p2pClient/Core/Src/system_stm32wbxx.c | 357 + .../BLE/BLE_p2pClient/EWARM/BLE_p2pClient.ewd | 1419 ++ .../BLE/BLE_p2pClient/EWARM/BLE_p2pClient.ewp | 1248 ++ .../BLE/BLE_p2pClient/EWARM/Project.eww | 7 + .../BLE_p2pClient/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../BLE_p2pClient/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../BLE/BLE_p2pClient/STM32_WPAN/App/app_ble.c | 1022 ++ .../BLE/BLE_p2pClient/STM32_WPAN/App/app_ble.h | 94 + .../BLE/BLE_p2pClient/STM32_WPAN/App/ble_conf.h | 65 + .../BLE_p2pClient/STM32_WPAN/App/ble_dbg_conf.h | 199 + .../BLE_p2pClient/STM32_WPAN/App/p2p_client_app.c | 750 + .../BLE_p2pClient/STM32_WPAN/App/p2p_client_app.h | 83 + .../BLE/BLE_p2pClient/STM32_WPAN/Target/hw_ipcc.c | 523 + .../Applications/BLE/BLE_p2pClient/readme.txt | 100 + .../BLE/BLE_p2pServer/Binary/BLE_p2pServer.hex | 2124 +++ .../BLE/BLE_p2pServer/Core/Inc/app_common.h | 114 + .../BLE/BLE_p2pServer/Core/Inc/app_conf.h | 562 + .../BLE/BLE_p2pServer/Core/Inc/app_debug.h | 45 + .../BLE/BLE_p2pServer/Core/Inc/app_entry.h | 69 + .../BLE/BLE_p2pServer/Core/Inc/hw_conf.h | 248 + .../BLE/BLE_p2pServer/Core/Inc/hw_if.h | 254 + .../Applications/BLE/BLE_p2pServer/Core/Inc/main.h | 75 + .../BLE/BLE_p2pServer/Core/Inc/stm32_lpm_if.h | 81 + .../BLE_p2pServer/Core/Inc/stm32wbxx_hal_conf.h | 354 + .../BLE/BLE_p2pServer/Core/Inc/stm32wbxx_it.h | 78 + .../BLE/BLE_p2pServer/Core/Inc/utilities_conf.h | 68 + .../BLE/BLE_p2pServer/Core/Src/app_debug.c | 360 + .../BLE/BLE_p2pServer/Core/Src/app_entry.c | 300 + .../BLE/BLE_p2pServer/Core/Src/hw_timerserver.c | 893 ++ .../BLE/BLE_p2pServer/Core/Src/hw_uart.c | 318 + .../Applications/BLE/BLE_p2pServer/Core/Src/main.c | 641 + .../BLE/BLE_p2pServer/Core/Src/stm32_lpm_if.c | 297 + .../BLE/BLE_p2pServer/Core/Src/stm32wbxx_hal_msp.c | 329 + .../BLE/BLE_p2pServer/Core/Src/stm32wbxx_it.c | 304 + .../BLE/BLE_p2pServer/Core/Src/system_stm32wbxx.c | 357 + .../BLE/BLE_p2pServer/EWARM/BLE_p2pServer.ewd | 1419 ++ .../BLE/BLE_p2pServer/EWARM/BLE_p2pServer.ewp | 1251 ++ .../BLE/BLE_p2pServer/EWARM/Project.eww | 7 + .../BLE_p2pServer/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../BLE_p2pServer/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../BLE/BLE_p2pServer/STM32_WPAN/App/app_ble.c | 1238 ++ .../BLE/BLE_p2pServer/STM32_WPAN/App/app_ble.h | 88 + .../BLE/BLE_p2pServer/STM32_WPAN/App/ble_conf.h | 70 + .../BLE_p2pServer/STM32_WPAN/App/ble_dbg_conf.h | 199 + .../BLE_p2pServer/STM32_WPAN/App/p2p_server_app.c | 389 + .../BLE_p2pServer/STM32_WPAN/App/p2p_server_app.h | 81 + .../BLE/BLE_p2pServer/STM32_WPAN/Target/hw_ipcc.c | 523 + .../Applications/BLE/BLE_p2pServer/readme.txt | 124 + .../BLE_p2pServer_ota/Binary/BLE_p2pServer_ota.bin | Bin 0 -> 34200 bytes .../BLE/BLE_p2pServer_ota/Core/Inc/app_common.h | 114 + .../BLE/BLE_p2pServer_ota/Core/Inc/app_conf.h | 559 + .../BLE/BLE_p2pServer_ota/Core/Inc/app_debug.h | 45 + .../BLE/BLE_p2pServer_ota/Core/Inc/app_entry.h | 69 + .../BLE/BLE_p2pServer_ota/Core/Inc/hw_conf.h | 248 + .../BLE/BLE_p2pServer_ota/Core/Inc/hw_if.h | 254 + .../BLE/BLE_p2pServer_ota/Core/Inc/main.h | 75 + .../BLE/BLE_p2pServer_ota/Core/Inc/stm32_lpm_if.h | 81 + .../Core/Inc/stm32wbxx_hal_conf.h | 354 + .../BLE/BLE_p2pServer_ota/Core/Inc/stm32wbxx_it.h | 78 + .../BLE_p2pServer_ota/Core/Inc/utilities_conf.h | 68 + .../BLE/BLE_p2pServer_ota/Core/Src/app_debug.c | 360 + .../BLE/BLE_p2pServer_ota/Core/Src/app_entry.c | 300 + .../BLE_p2pServer_ota/Core/Src/hw_timerserver.c | 893 ++ .../BLE/BLE_p2pServer_ota/Core/Src/hw_uart.c | 318 + .../BLE/BLE_p2pServer_ota/Core/Src/main.c | 641 + .../BLE/BLE_p2pServer_ota/Core/Src/stm32_lpm_if.c | 297 + .../BLE_p2pServer_ota/Core/Src/stm32wbxx_hal_msp.c | 329 + .../BLE/BLE_p2pServer_ota/Core/Src/stm32wbxx_it.c | 304 + .../BLE_p2pServer_ota/Core/Src/system_stm32wbxx.c | 356 + .../BLE_p2pServer_ota/EWARM/BLE_p2pServer_ota.ewd | 1419 ++ .../BLE_p2pServer_ota/EWARM/BLE_p2pServer_ota.ewp | 1251 ++ .../BLE/BLE_p2pServer_ota/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4_ota.icf | 44 + .../BLE/BLE_p2pServer_ota/STM32_WPAN/App/app_ble.c | 1228 ++ .../BLE/BLE_p2pServer_ota/STM32_WPAN/App/app_ble.h | 88 + .../BLE_p2pServer_ota/STM32_WPAN/App/ble_conf.h | 70 + .../STM32_WPAN/App/ble_dbg_conf.h | 199 + .../STM32_WPAN/App/p2p_server_app.c | 389 + .../STM32_WPAN/App/p2p_server_app.h | 81 + .../BLE_p2pServer_ota/STM32_WPAN/Target/hw_ipcc.c | 523 + .../Applications/BLE/BLE_p2pServer_ota/readme.txt | 141 + .../FatFs/FatFs_uSD_Standalone/.extSettings | 12 + .../FatFs/FatFs_uSD_Standalone/Core/Inc/main.h | 76 + .../Core/Inc/stm32wbxx_hal_conf.h | 359 + .../FatFs_uSD_Standalone/Core/Inc/stm32wbxx_it.h | 70 + .../FatFs/FatFs_uSD_Standalone/Core/Src/main.c | 222 + .../Core/Src/stm32wbxx_hal_msp.c | 82 + .../FatFs_uSD_Standalone/Core/Src/stm32wbxx_it.c | 205 + .../Core/Src/system_stm32wbxx.c | 357 + .../EWARM/FatFs_uSD_Standalone.ewd | 1419 ++ .../EWARM/FatFs_uSD_Standalone.ewp | 1183 ++ .../FatFs/FatFs_uSD_Standalone/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../EWARM/stm32wb35xx_sram_cm4.icf | 39 + .../FatFs_uSD_Standalone/FATFS/App/app_fatfs.c | 234 + .../FatFs_uSD_Standalone/FATFS/App/app_fatfs.h | 69 + .../FatFs_uSD_Standalone/FATFS/Target/ffconf.h | 272 + .../FatFs_uSD_Standalone/FATFS/Target/sd_diskio.c | 237 + .../FatFs_uSD_Standalone/FATFS/Target/sd_diskio.h | 69 + .../MDK-ARM/FatFs_uSD_Standalone.uvoptx | 669 + .../MDK-ARM/FatFs_uSD_Standalone.uvprojx | 622 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../FatFs_uSD_Standalone/STM32CubeIDE/.cproject | 183 + .../FatFs_uSD_Standalone/STM32CubeIDE/.project | 201 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 159 + .../STM32CubeIDE/Application/User/sysmem.c | 58 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../FatFs/FatFs_uSD_Standalone/readme.txt | 111 + .../FreeRTOS/FreeRTOS_Mutexes/.extSettings | 9 + .../FreeRTOS_Mutexes/EWARM/FreeRTOS_Mutexes.ewd | 1419 ++ .../FreeRTOS_Mutexes/EWARM/FreeRTOS_Mutexes.ewp | 1167 ++ .../FreeRTOS/FreeRTOS_Mutexes/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../EWARM/stm32wb35xx_sram_cm4.icf | 39 + .../FreeRTOS/FreeRTOS_Mutexes/FreeRTOS_Mutexes.ioc | 162 + .../FreeRTOS/FreeRTOS_Mutexes/Inc/FreeRTOSConfig.h | 143 + .../FreeRTOS/FreeRTOS_Mutexes/Inc/main.h | 72 + .../FreeRTOS_Mutexes/Inc/stm32wbxx_hal_conf.h | 359 + .../FreeRTOS/FreeRTOS_Mutexes/Inc/stm32wbxx_it.h | 68 + .../MDK-ARM/FreeRTOS_Mutexes.uvoptx | 649 + .../MDK-ARM/FreeRTOS_Mutexes.uvprojx | 606 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../FreeRTOS_Mutexes/STM32CubeIDE/.cproject | 175 + .../FreeRTOS_Mutexes/STM32CubeIDE/.project | 205 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../FreeRTOS/FreeRTOS_Mutexes/Src/app_freertos.c | 62 + .../FreeRTOS/FreeRTOS_Mutexes/Src/main.c | 481 + .../FreeRTOS_Mutexes/Src/stm32wbxx_hal_msp.c | 84 + .../Src/stm32wbxx_hal_timebase_tim.c | 136 + .../FreeRTOS/FreeRTOS_Mutexes/Src/stm32wbxx_it.c | 183 + .../FreeRTOS_Mutexes/Src/system_stm32wbxx.c | 357 + .../FreeRTOS/FreeRTOS_Mutexes/readme.txt | 106 + .../FreeRTOS/FreeRTOS_Queues/.extSettings | 9 + .../FreeRTOS_Queues/EWARM/FreeRTOS_Queues.ewd | 1419 ++ .../FreeRTOS_Queues/EWARM/FreeRTOS_Queues.ewp | 1167 ++ .../FreeRTOS/FreeRTOS_Queues/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../FreeRTOS_Queues/EWARM/stm32wb35xx_sram_cm4.icf | 39 + .../FreeRTOS/FreeRTOS_Queues/FreeRTOS_Queues.ioc | 163 + .../FreeRTOS/FreeRTOS_Queues/Inc/FreeRTOSConfig.h | 143 + .../FreeRTOS/FreeRTOS_Queues/Inc/main.h | 72 + .../FreeRTOS_Queues/Inc/stm32wbxx_hal_conf.h | 359 + .../FreeRTOS/FreeRTOS_Queues/Inc/stm32wbxx_it.h | 68 + .../FreeRTOS_Queues/MDK-ARM/FreeRTOS_Queues.uvoptx | 649 + .../MDK-ARM/FreeRTOS_Queues.uvprojx | 606 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../FreeRTOS_Queues/STM32CubeIDE/.cproject | 175 + .../FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/.project | 205 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../FreeRTOS/FreeRTOS_Queues/Src/app_freertos.c | 62 + .../FreeRTOS/FreeRTOS_Queues/Src/main.c | 355 + .../FreeRTOS_Queues/Src/stm32wbxx_hal_msp.c | 84 + .../Src/stm32wbxx_hal_timebase_tim.c | 136 + .../FreeRTOS/FreeRTOS_Queues/Src/stm32wbxx_it.c | 183 + .../FreeRTOS_Queues/Src/system_stm32wbxx.c | 357 + .../FreeRTOS/FreeRTOS_Queues/readme.txt | 90 + .../FreeRTOS/FreeRTOS_Semaphore/.extSettings | 9 + .../EWARM/FreeRTOS_Semaphore.ewd | 1419 ++ .../EWARM/FreeRTOS_Semaphore.ewp | 1167 ++ .../FreeRTOS/FreeRTOS_Semaphore/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../EWARM/stm32wb35xx_sram_cm4.icf | 39 + .../FreeRTOS_Semaphore/FreeRTOS_Semaphore.ioc | 162 + .../FreeRTOS_Semaphore/Inc/FreeRTOSConfig.h | 144 + .../FreeRTOS/FreeRTOS_Semaphore/Inc/main.h | 72 + .../FreeRTOS_Semaphore/Inc/stm32wbxx_hal_conf.h | 359 + .../FreeRTOS/FreeRTOS_Semaphore/Inc/stm32wbxx_it.h | 68 + .../MDK-ARM/FreeRTOS_Semaphore.uvoptx | 649 + .../MDK-ARM/FreeRTOS_Semaphore.uvprojx | 606 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../FreeRTOS_Semaphore/STM32CubeIDE/.cproject | 175 + .../FreeRTOS_Semaphore/STM32CubeIDE/.project | 205 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../FreeRTOS/FreeRTOS_Semaphore/Src/app_freertos.c | 62 + .../FreeRTOS/FreeRTOS_Semaphore/Src/main.c | 370 + .../FreeRTOS_Semaphore/Src/stm32wbxx_hal_msp.c | 84 + .../Src/stm32wbxx_hal_timebase_tim.c | 136 + .../FreeRTOS/FreeRTOS_Semaphore/Src/stm32wbxx_it.c | 183 + .../FreeRTOS_Semaphore/Src/system_stm32wbxx.c | 357 + .../FreeRTOS/FreeRTOS_Semaphore/readme.txt | 87 + .../Thread/Thread_Cli_Cmd/Core/Inc/app_common.h | 119 + .../Thread/Thread_Cli_Cmd/Core/Inc/app_conf.h | 360 + .../Thread/Thread_Cli_Cmd/Core/Inc/app_entry.h | 69 + .../Thread/Thread_Cli_Cmd/Core/Inc/hw_conf.h | 143 + .../Thread/Thread_Cli_Cmd/Core/Inc/hw_if.h | 274 + .../Thread/Thread_Cli_Cmd/Core/Inc/main.h | 71 + .../Thread/Thread_Cli_Cmd/Core/Inc/stm32_lpm_if.h | 81 + .../Thread_Cli_Cmd/Core/Inc/stm32wbxx_hal_conf.h | 353 + .../Thread/Thread_Cli_Cmd/Core/Inc/stm32wbxx_it.h | 89 + .../Thread/Thread_Cli_Cmd/Core/Inc/stm_logging.h | 63 + .../Thread_Cli_Cmd/Core/Inc/utilities_conf.h | 69 + .../Thread/Thread_Cli_Cmd/Core/Src/app_entry.c | 450 + .../Thread_Cli_Cmd/Core/Src/hw_timerserver.c | 893 ++ .../Thread/Thread_Cli_Cmd/Core/Src/hw_uart.c | 484 + .../Thread/Thread_Cli_Cmd/Core/Src/main.c | 520 + .../Thread/Thread_Cli_Cmd/Core/Src/stm32_lpm_if.c | 297 + .../Thread_Cli_Cmd/Core/Src/stm32wbxx_hal_msp.c | 360 + .../Thread/Thread_Cli_Cmd/Core/Src/stm32wbxx_it.c | 431 + .../Thread/Thread_Cli_Cmd/Core/Src/stm_logging.c | 212 + .../Thread_Cli_Cmd/Core/Src/system_stm32wbxx.c | 357 + .../Thread/Thread_Cli_Cmd/EWARM/Project.eww | 7 + .../Thread/Thread_Cli_Cmd/EWARM/Thread_Cli_Cmd.ewd | 1419 ++ .../Thread/Thread_Cli_Cmd/EWARM/Thread_Cli_Cmd.ewp | 1305 ++ .../Thread_Cli_Cmd/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../Thread_Cli_Cmd/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Thread_Cli_Cmd/STM32_WPAN/App/app_thread.c | 747 + .../Thread_Cli_Cmd/STM32_WPAN/App/app_thread.h | 105 + .../Thread_Cli_Cmd/STM32_WPAN/Target/hw_ipcc.c | 523 + .../Applications/Thread/Thread_Cli_Cmd/readme.txt | 176 + .../USB_Device/HID_Standalone/.extSettings | 11 + .../USB_Device/HID_Standalone/Core/Inc/main.h | 72 + .../HID_Standalone/Core/Inc/stm32wbxx_hal_conf.h | 359 + .../HID_Standalone/Core/Inc/stm32wbxx_it.h | 71 + .../USB_Device/HID_Standalone/Core/Src/main.c | 229 + .../HID_Standalone/Core/Src/stm32wbxx_hal_msp.c | 83 + .../HID_Standalone/Core/Src/stm32wbxx_it.c | 229 + .../HID_Standalone/Core/Src/system_stm32wbxx.c | 357 + .../HID_Standalone/EWARM/HID_Standalone.ewd | 1419 ++ .../HID_Standalone/EWARM/HID_Standalone.ewp | 1171 ++ .../USB_Device/HID_Standalone/EWARM/Project.eww | 7 + .../HID_Standalone/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../HID_Standalone/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../HID_Standalone/EWARM/stm32wb35xx_sram_cm4.icf | 39 + .../USB_Device/HID_Standalone/HID_Standalone.ioc | 148 + .../HID_Standalone/MDK-ARM/HID_Standalone.uvoptx | 641 + .../HID_Standalone/MDK-ARM/HID_Standalone.uvprojx | 607 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../HID_Standalone/STM32CubeIDE/.cproject | 178 + .../HID_Standalone/STM32CubeIDE/.project | 196 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../HID_Standalone/USB_Device/App/usb_device.c | 210 + .../HID_Standalone/USB_Device/App/usb_device.h | 105 + .../HID_Standalone/USB_Device/App/usbd_desc.c | 397 + .../HID_Standalone/USB_Device/App/usbd_desc.h | 145 + .../HID_Standalone/USB_Device/Target/usbd_conf.c | 774 ++ .../HID_Standalone/USB_Device/Target/usbd_conf.h | 179 + .../USB_Device/HID_Standalone/readme.txt | 101 + .../USB_Device/MSC_Standalone/.extSettings | 14 + .../USB_Device/MSC_Standalone/Core/Inc/main.h | 76 + .../MSC_Standalone/Core/Inc/stm32wbxx_hal_conf.h | 359 + .../MSC_Standalone/Core/Inc/stm32wbxx_it.h | 71 + .../USB_Device/MSC_Standalone/Core/Src/main.c | 227 + .../MSC_Standalone/Core/Src/stm32wbxx_hal_msp.c | 83 + .../MSC_Standalone/Core/Src/stm32wbxx_it.c | 221 + .../MSC_Standalone/Core/Src/system_stm32wbxx.c | 357 + .../MSC_Standalone/EWARM/MSC_Standalone.ewd | 1419 ++ .../MSC_Standalone/EWARM/MSC_Standalone.ewp | 1208 ++ .../USB_Device/MSC_Standalone/EWARM/Project.eww | 7 + .../MSC_Standalone/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../MSC_Standalone/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../MSC_Standalone/EWARM/stm32wb35xx_sram_cm4.icf | 39 + .../MSC_Standalone/MDK-ARM/MSC_Standalone.uvoptx | 765 ++ .../MSC_Standalone/MDK-ARM/MSC_Standalone.uvprojx | 662 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../USB_Device/MSC_Standalone/MSC_Standalone.ioc | 152 + .../MSC_Standalone/STM32CubeIDE/.cproject | 185 + .../MSC_Standalone/STM32CubeIDE/.project | 241 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../MSC_Standalone/USB_Device/App/usb_device.c | 181 + .../MSC_Standalone/USB_Device/App/usb_device.h | 105 + .../MSC_Standalone/USB_Device/App/usbd_desc.c | 397 + .../MSC_Standalone/USB_Device/App/usbd_desc.h | 145 + .../USB_Device/App/usbd_storage_if.c | 321 + .../USB_Device/App/usbd_storage_if.h | 129 + .../MSC_Standalone/USB_Device/Target/usbd_conf.c | 770 ++ .../MSC_Standalone/USB_Device/Target/usbd_conf.h | 179 + .../USB_Device/MSC_Standalone/readme.txt | 99 + .../Adafruit_LCD_1_8_SD_Joystick/.extSettings | 12 + .../Adafruit_LCD_1_8_SD_Joystick.ioc | 139 + .../Adafruit_LCD_1_8_SD_Joystick/Core/Inc/main.h | 111 + .../Core/Inc/stm32wbxx_hal_conf.h | 359 + .../Core/Inc/stm32wbxx_it.h | 88 + .../Adafruit_LCD_1_8_SD_Joystick/Core/Src/main.c | 676 + .../Core/Src/stm32wbxx_hal_msp.c | 82 + .../Core/Src/stm32wbxx_it.c | 234 + .../Core/Src/system_stm32wbxx.c | 357 + .../EWARM/Adafruit_LCD_1_8_SD_Joystick.ewd | 1419 ++ .../EWARM/Adafruit_LCD_1_8_SD_Joystick.ewp | 1197 ++ .../Adafruit_LCD_1_8_SD_Joystick/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../FATFS/App/app_fatfs.c | 320 + .../FATFS/App/app_fatfs.h | 95 + .../FATFS/Target/ffconf.h | 268 + .../FATFS/Target/sd_diskio.c | 239 + .../FATFS/Target/sd_diskio.h | 69 + .../MDK-ARM/Adafruit_LCD_1_8_SD_Joystick.uvoptx | 717 + .../MDK-ARM/Adafruit_LCD_1_8_SD_Joystick.uvprojx | 642 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../STM32CubeIDE/.cproject | 183 + .../STM32CubeIDE/.project | 221 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Adafruit_LCD_1_8_SD_Joystick/readme.txt | 158 + .../ADC_SingleConversion_TriggerSW_IT/.extSettings | 8 + .../ADC_SingleConversion_TriggerSW_IT.ioc | 106 + .../EWARM/ADC_SingleConversion_TriggerSW_IT.ewd | 1419 ++ .../EWARM/ADC_SingleConversion_TriggerSW_IT.ewp | 1128 ++ .../EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../ADC_SingleConversion_TriggerSW_IT/Inc/main.h | 124 + .../Inc/stm32wbxx_hal_conf.h | 359 + .../Inc/stm32wbxx_it.h | 66 + .../ADC_SingleConversion_TriggerSW_IT.uvoptx | 533 + .../ADC_SingleConversion_TriggerSW_IT.uvprojx | 556 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../STM32CubeIDE/.cproject | 170 + .../STM32CubeIDE/.project | 160 + .../STM32CubeIDE/.settings/language.settings.xml | 27 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../ADC_SingleConversion_TriggerSW_IT/Src/main.c | 490 + .../Src/stm32wbxx_hal_msp.c | 156 + .../Src/stm32wbxx_it.c | 133 + .../Src/system_stm32wbxx.c | 357 + .../ADC_SingleConversion_TriggerSW_IT/readme.txt | 97 + .../.extSettings | 8 + .../ADC_SingleConversion_TriggerTimer_DMA.ioc | 121 + .../ADC_SingleConversion_TriggerTimer_DMA.ewd | 1419 ++ .../ADC_SingleConversion_TriggerTimer_DMA.ewp | 1128 ++ .../EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Inc/main.h | 141 + .../Inc/stm32wbxx_hal_conf.h | 359 + .../Inc/stm32wbxx_it.h | 69 + .../ADC_SingleConversion_TriggerTimer_DMA.uvoptx | 533 + .../ADC_SingleConversion_TriggerTimer_DMA.uvprojx | 556 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../STM32CubeIDE/.cproject | 169 + .../STM32CubeIDE/.project | 160 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Src/main.c | 560 + .../Src/stm32wbxx_hal_msp.c | 238 + .../Src/stm32wbxx_it.c | 156 + .../Src/system_stm32wbxx.c | 357 + .../readme.txt | 103 + .../Examples/BSP/BSP_Example/.extSettings | 8 + .../Examples/BSP/BSP_Example/BSP_Example.ioc | 106 + .../Examples/BSP/BSP_Example/EWARM/BSP_Example.ewd | 1419 ++ .../Examples/BSP/BSP_Example/EWARM/BSP_Example.ewp | 1119 ++ .../Examples/BSP/BSP_Example/EWARM/Project.eww | 7 + .../BSP_Example/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../BSP_Example/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../BSP/BSP_Example/EWARM/stm32wb35xx_sram_cm4.icf | 39 + .../Examples/BSP/BSP_Example/Inc/main.h | 68 + .../BSP/BSP_Example/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/BSP/BSP_Example/Inc/stm32wbxx_it.h | 72 + .../BSP/BSP_Example/MDK-ARM/BSP_Example.uvoptx | 497 + .../BSP/BSP_Example/MDK-ARM/BSP_Example.uvprojx | 541 + .../BSP_Example/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../BSP_Example/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../BSP/BSP_Example/STM32CubeIDE/.cproject | 169 + .../Examples/BSP/BSP_Example/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/BSP/BSP_Example/Src/main.c | 238 + .../BSP/BSP_Example/Src/stm32wbxx_hal_msp.c | 81 + .../Examples/BSP/BSP_Example/Src/stm32wbxx_it.c | 231 + .../BSP/BSP_Example/Src/system_stm32wbxx.c | 357 + .../Examples/BSP/BSP_Example/readme.txt | 69 + .../COMP/COMP_CompareGpioVsVrefInt_IT/.extSettings | 8 + .../COMP_CompareGpioVsVrefInt_IT.ioc | 120 + .../EWARM/COMP_CompareGpioVsVrefInt_IT.ewd | 1419 ++ .../EWARM/COMP_CompareGpioVsVrefInt_IT.ewp | 1125 ++ .../COMP_CompareGpioVsVrefInt_IT/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../EWARM/stm32wb35xx_sram_cm4.icf | 39 + .../COMP/COMP_CompareGpioVsVrefInt_IT/Inc/main.h | 71 + .../Inc/stm32wbxx_hal_conf.h | 359 + .../Inc/stm32wbxx_it.h | 70 + .../MDK-ARM/COMP_CompareGpioVsVrefInt_IT.uvoptx | 509 + .../MDK-ARM/COMP_CompareGpioVsVrefInt_IT.uvprojx | 547 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../STM32CubeIDE/.cproject | 169 + .../STM32CubeIDE/.project | 150 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 159 + .../STM32CubeIDE/Application/User/sysmem.c | 58 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../COMP/COMP_CompareGpioVsVrefInt_IT/Src/main.c | 346 + .../Src/stm32wbxx_hal_msp.c | 143 + .../Src/stm32wbxx_it.c | 208 + .../Src/system_stm32wbxx.c | 357 + .../COMP/COMP_CompareGpioVsVrefInt_IT/readme.txt | 87 + .../Examples/CORTEX/CORTEXM_SysTick/.extSettings | 8 + .../CORTEX/CORTEXM_SysTick/CORTEXM_SysTick.ioc | 106 + .../CORTEXM_SysTick/EWARM/CORTEXM_SysTick.ewd | 1419 ++ .../CORTEXM_SysTick/EWARM/CORTEXM_SysTick.ewp | 1119 ++ .../CORTEX/CORTEXM_SysTick/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/CORTEX/CORTEXM_SysTick/Inc/main.h | 71 + .../CORTEXM_SysTick/Inc/stm32wbxx_hal_conf.h | 359 + .../CORTEX/CORTEXM_SysTick/Inc/stm32wbxx_it.h | 66 + .../CORTEXM_SysTick/MDK-ARM/CORTEXM_SysTick.uvoptx | 497 + .../MDK-ARM/CORTEXM_SysTick.uvprojx | 541 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../CORTEX/CORTEXM_SysTick/STM32CubeIDE/.cproject | 169 + .../CORTEX/CORTEXM_SysTick/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/CORTEX/CORTEXM_SysTick/Src/main.c | 242 + .../CORTEX/CORTEXM_SysTick/Src/stm32wbxx_hal_msp.c | 82 + .../CORTEX/CORTEXM_SysTick/Src/stm32wbxx_it.c | 149 + .../CORTEX/CORTEXM_SysTick/Src/system_stm32wbxx.c | 357 + .../Examples/CORTEX/CORTEXM_SysTick/readme.txt | 66 + .../Examples/CRC/CRC_Example/.extSettings | 8 + .../Examples/CRC/CRC_Example/CRC_Example.ioc | 116 + .../Examples/CRC/CRC_Example/EWARM/CRC_Example.ewd | 1419 ++ .../Examples/CRC/CRC_Example/EWARM/CRC_Example.ewp | 1125 ++ .../Examples/CRC/CRC_Example/EWARM/Project.eww | 7 + .../CRC_Example/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../CRC_Example/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/CRC/CRC_Example/Inc/main.h | 71 + .../CRC/CRC_Example/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/CRC/CRC_Example/Inc/stm32wbxx_it.h | 64 + .../CRC/CRC_Example/MDK-ARM/CRC_Example.uvoptx | 521 + .../CRC/CRC_Example/MDK-ARM/CRC_Example.uvprojx | 551 + .../CRC_Example/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../CRC_Example/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../CRC/CRC_Example/STM32CubeIDE/.cproject | 169 + .../Examples/CRC/CRC_Example/STM32CubeIDE/.project | 155 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/CRC/CRC_Example/Src/main.c | 279 + .../CRC/CRC_Example/Src/stm32wbxx_hal_msp.c | 125 + .../Examples/CRC/CRC_Example/Src/stm32wbxx_it.c | 122 + .../CRC/CRC_Example/Src/system_stm32wbxx.c | 357 + .../Examples/CRC/CRC_Example/readme.txt | 85 + .../Examples/CRYP/CRYP_DMA/.extSettings | 8 + .../Examples/CRYP/CRYP_DMA/CRYP_DMA.ioc | 157 + .../Examples/CRYP/CRYP_DMA/EWARM/CRYP_DMA.ewd | 1419 ++ .../Examples/CRYP/CRYP_DMA/EWARM/CRYP_DMA.ewp | 1138 ++ .../Examples/CRYP/CRYP_DMA/EWARM/Project.eww | 7 + .../CRYP/CRYP_DMA/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../CRYP/CRYP_DMA/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../CRYP/CRYP_DMA/EWARM/stm32wb35xx_sram_cm4.icf | 39 + .../Examples/CRYP/CRYP_DMA/Expected_Results.txt | 31 + .../Examples/CRYP/CRYP_DMA/Inc/main.h | 73 + .../CRYP/CRYP_DMA/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/CRYP/CRYP_DMA/Inc/stm32wbxx_it.h | 71 + .../Examples/CRYP/CRYP_DMA/MDK-ARM/CRYP_DMA.uvoptx | 589 + .../CRYP/CRYP_DMA/MDK-ARM/CRYP_DMA.uvprojx | 572 + .../Examples/CRYP/CRYP_DMA/MDK-ARM/Retarget.c | 52 + .../Examples/CRYP/CRYP_DMA/MDK-ARM/Serial.c | 43 + .../Examples/CRYP/CRYP_DMA/MDK-ARM/Serial.h | 24 + .../CRYP_DMA/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../CRYP_DMA/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../Examples/CRYP/CRYP_DMA/STM32CubeIDE/.cproject | 180 + .../Examples/CRYP/CRYP_DMA/STM32CubeIDE/.project | 170 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../CRYP_DMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/CRYP/CRYP_DMA/Src/main.c | 626 + .../Examples/CRYP/CRYP_DMA/Src/stm32wbxx_hal_msp.c | 168 + .../Examples/CRYP/CRYP_DMA/Src/stm32wbxx_it.c | 234 + .../Examples/CRYP/CRYP_DMA/Src/system_stm32wbxx.c | 357 + .../Examples/CRYP/CRYP_DMA/readme.txt | 94 + .../Examples/DMA/DMA_FLASHToRAM/.extSettings | 8 + .../Examples/DMA/DMA_FLASHToRAM/DMA_FLASHToRAM.ioc | 127 + .../DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewd | 1419 ++ .../DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewp | 1119 ++ .../Examples/DMA/DMA_FLASHToRAM/EWARM/Project.eww | 7 + .../DMA_FLASHToRAM/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../DMA_FLASHToRAM/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/DMA/DMA_FLASHToRAM/Inc/main.h | 71 + .../DMA/DMA_FLASHToRAM/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/DMA/DMA_FLASHToRAM/Inc/stm32wbxx_it.h | 65 + .../DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvoptx | 497 + .../DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvprojx | 541 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../DMA/DMA_FLASHToRAM/STM32CubeIDE/.cproject | 169 + .../DMA/DMA_FLASHToRAM/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/DMA/DMA_FLASHToRAM/Src/main.c | 316 + .../DMA/DMA_FLASHToRAM/Src/stm32wbxx_hal_msp.c | 81 + .../Examples/DMA/DMA_FLASHToRAM/Src/stm32wbxx_it.c | 134 + .../DMA/DMA_FLASHToRAM/Src/system_stm32wbxx.c | 357 + .../Examples/DMA/DMA_FLASHToRAM/readme.txt | 90 + .../Examples/DMA/DMA_MUXSYNC/.extSettings | 8 + .../Examples/DMA/DMA_MUXSYNC/DMA_MUXSYNC.ioc | 177 + .../Examples/DMA/DMA_MUXSYNC/EWARM/DMA_MUXSYNC.ewd | 1419 ++ .../Examples/DMA/DMA_MUXSYNC/EWARM/DMA_MUXSYNC.ewp | 1128 ++ .../Examples/DMA/DMA_MUXSYNC/EWARM/Project.eww | 7 + .../DMA_MUXSYNC/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../DMA_MUXSYNC/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/DMA/DMA_MUXSYNC/Inc/main.h | 106 + .../DMA/DMA_MUXSYNC/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/DMA/DMA_MUXSYNC/Inc/stm32wbxx_it.h | 72 + .../DMA/DMA_MUXSYNC/MDK-ARM/DMA_MUXSYNC.uvoptx | 533 + .../DMA/DMA_MUXSYNC/MDK-ARM/DMA_MUXSYNC.uvprojx | 556 + .../DMA_MUXSYNC/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../DMA_MUXSYNC/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../DMA/DMA_MUXSYNC/STM32CubeIDE/.cproject | 169 + .../Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/.project | 160 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/DMA/DMA_MUXSYNC/Src/main.c | 402 + .../DMA/DMA_MUXSYNC/Src/stm32wbxx_hal_msp.c | 228 + .../Examples/DMA/DMA_MUXSYNC/Src/stm32wbxx_it.c | 249 + .../DMA/DMA_MUXSYNC/Src/system_stm32wbxx.c | 357 + .../Examples/DMA/DMA_MUXSYNC/readme.txt | 143 + .../Examples/DMA/DMA_MUX_RequestGen/.extSettings | 8 + .../DMA/DMA_MUX_RequestGen/DMA_MUX_RequestGen.ioc | 106 + .../EWARM/DMA_MUX_RequestGen.ewd | 1419 ++ .../EWARM/DMA_MUX_RequestGen.ewp | 1119 ++ .../DMA/DMA_MUX_RequestGen/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/DMA/DMA_MUX_RequestGen/Inc/main.h | 72 + .../DMA_MUX_RequestGen/Inc/stm32wbxx_hal_conf.h | 359 + .../DMA/DMA_MUX_RequestGen/Inc/stm32wbxx_it.h | 68 + .../MDK-ARM/DMA_MUX_RequestGen.uvoptx | 497 + .../MDK-ARM/DMA_MUX_RequestGen.uvprojx | 542 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../DMA/DMA_MUX_RequestGen/STM32CubeIDE/.cproject | 169 + .../DMA/DMA_MUX_RequestGen/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/DMA/DMA_MUX_RequestGen/Src/main.c | 262 + .../DMA/DMA_MUX_RequestGen/Src/stm32wbxx_hal_msp.c | 83 + .../DMA/DMA_MUX_RequestGen/Src/stm32wbxx_it.c | 213 + .../DMA/DMA_MUX_RequestGen/Src/system_stm32wbxx.c | 357 + .../Examples/DMA/DMA_MUX_RequestGen/readme.txt | 104 + .../Examples/FLASH/FLASH_EraseProgram/.extSettings | 8 + .../EWARM/FLASH_EraseProgram.ewd | 1419 ++ .../EWARM/FLASH_EraseProgram.ewp | 1119 ++ .../FLASH/FLASH_EraseProgram/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../FLASH_EraseProgram/FLASH_EraseProgram.ioc | 106 + .../Examples/FLASH/FLASH_EraseProgram/Inc/main.h | 329 + .../FLASH_EraseProgram/Inc/stm32wbxx_hal_conf.h | 359 + .../FLASH/FLASH_EraseProgram/Inc/stm32wbxx_it.h | 64 + .../MDK-ARM/FLASH_EraseProgram.uvoptx | 497 + .../MDK-ARM/FLASH_EraseProgram.uvprojx | 541 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../FLASH_EraseProgram/STM32CubeIDE/.cproject | 169 + .../FLASH/FLASH_EraseProgram/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/FLASH/FLASH_EraseProgram/Src/main.c | 331 + .../FLASH_EraseProgram/Src/stm32wbxx_hal_msp.c | 81 + .../FLASH/FLASH_EraseProgram/Src/stm32wbxx_it.c | 119 + .../FLASH_EraseProgram/Src/system_stm32wbxx.c | 357 + .../Examples/FLASH/FLASH_EraseProgram/readme.txt | 88 + .../FLASH/FLASH_WriteProtection/.extSettings | 8 + .../EWARM/FLASH_WriteProtection.ewd | 1419 ++ .../EWARM/FLASH_WriteProtection.ewp | 1119 ++ .../FLASH/FLASH_WriteProtection/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../FLASH_WriteProtection.ioc | 106 + .../FLASH/FLASH_WriteProtection/Inc/main.h | 330 + .../FLASH_WriteProtection/Inc/stm32wbxx_hal_conf.h | 359 + .../FLASH/FLASH_WriteProtection/Inc/stm32wbxx_it.h | 64 + .../MDK-ARM/FLASH_WriteProtection.uvoptx | 497 + .../MDK-ARM/FLASH_WriteProtection.uvprojx | 541 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../FLASH_WriteProtection/STM32CubeIDE/.cproject | 169 + .../FLASH_WriteProtection/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../FLASH/FLASH_WriteProtection/Src/main.c | 600 + .../FLASH_WriteProtection/Src/stm32wbxx_hal_msp.c | 81 + .../FLASH/FLASH_WriteProtection/Src/stm32wbxx_it.c | 119 + .../FLASH_WriteProtection/Src/system_stm32wbxx.c | 357 + .../FLASH/FLASH_WriteProtection/readme.txt | 98 + .../Examples/GPIO/GPIO_EXTI/.extSettings | 8 + .../Examples/GPIO/GPIO_EXTI/EWARM/GPIO_EXTI.ewd | 1419 ++ .../Examples/GPIO/GPIO_EXTI/EWARM/GPIO_EXTI.ewp | 1119 ++ .../Examples/GPIO/GPIO_EXTI/EWARM/Project.eww | 7 + .../GPIO/GPIO_EXTI/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../GPIO/GPIO_EXTI/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/GPIO/GPIO_EXTI/GPIO_EXTI.ioc | 106 + .../Examples/GPIO/GPIO_EXTI/Inc/main.h | 71 + .../GPIO/GPIO_EXTI/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/GPIO/GPIO_EXTI/Inc/stm32wbxx_it.h | 68 + .../GPIO/GPIO_EXTI/MDK-ARM/GPIO_EXTI.uvoptx | 497 + .../GPIO/GPIO_EXTI/MDK-ARM/GPIO_EXTI.uvprojx | 541 + .../GPIO_EXTI/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../GPIO_EXTI/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../Examples/GPIO/GPIO_EXTI/STM32CubeIDE/.cproject | 169 + .../Examples/GPIO/GPIO_EXTI/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../GPIO_EXTI/STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/GPIO/GPIO_EXTI/Src/main.c | 249 + .../GPIO/GPIO_EXTI/Src/stm32wbxx_hal_msp.c | 82 + .../Examples/GPIO/GPIO_EXTI/Src/stm32wbxx_it.c | 187 + .../Examples/GPIO/GPIO_EXTI/Src/system_stm32wbxx.c | 357 + .../Examples/GPIO/GPIO_EXTI/readme.txt | 77 + .../Examples/GPIO/GPIO_IOToggle/.extSettings | 8 + .../GPIO/GPIO_IOToggle/EWARM/GPIO_IOToggle.ewd | 1419 ++ .../GPIO/GPIO_IOToggle/EWARM/GPIO_IOToggle.ewp | 1119 ++ .../Examples/GPIO/GPIO_IOToggle/EWARM/Project.eww | 7 + .../GPIO_IOToggle/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../GPIO_IOToggle/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/GPIO/GPIO_IOToggle/GPIO_IOToggle.ioc | 106 + .../Examples/GPIO/GPIO_IOToggle/Inc/main.h | 71 + .../GPIO/GPIO_IOToggle/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/GPIO/GPIO_IOToggle/Inc/stm32wbxx_it.h | 68 + .../GPIO_IOToggle/MDK-ARM/GPIO_IOToggle.uvoptx | 497 + .../GPIO_IOToggle/MDK-ARM/GPIO_IOToggle.uvprojx | 541 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../GPIO/GPIO_IOToggle/STM32CubeIDE/.cproject | 169 + .../GPIO/GPIO_IOToggle/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/GPIO/GPIO_IOToggle/Src/main.c | 224 + .../GPIO/GPIO_IOToggle/Src/stm32wbxx_hal_msp.c | 82 + .../Examples/GPIO/GPIO_IOToggle/Src/stm32wbxx_it.c | 176 + .../GPIO/GPIO_IOToggle/Src/system_stm32wbxx.c | 357 + .../Examples/GPIO/GPIO_IOToggle/readme.txt | 70 + .../Examples/HAL/HAL_TimeBase/.extSettings | 8 + .../HAL/HAL_TimeBase/EWARM/HAL_TimeBase.ewd | 1419 ++ .../HAL/HAL_TimeBase/EWARM/HAL_TimeBase.ewp | 1119 ++ .../Examples/HAL/HAL_TimeBase/EWARM/Project.eww | 7 + .../HAL_TimeBase/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../HAL_TimeBase/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/HAL/HAL_TimeBase/HAL_TimeBase.ioc | 106 + .../Examples/HAL/HAL_TimeBase/Inc/main.h | 71 + .../HAL/HAL_TimeBase/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/HAL/HAL_TimeBase/Inc/stm32wbxx_it.h | 65 + .../HAL/HAL_TimeBase/MDK-ARM/HAL_TimeBase.uvoptx | 497 + .../HAL/HAL_TimeBase/MDK-ARM/HAL_TimeBase.uvprojx | 541 + .../HAL_TimeBase/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../HAL_TimeBase/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../HAL/HAL_TimeBase/STM32CubeIDE/.cproject | 169 + .../HAL/HAL_TimeBase/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/HAL/HAL_TimeBase/Src/main.c | 357 + .../HAL/HAL_TimeBase/Src/stm32wbxx_hal_msp.c | 81 + .../Examples/HAL/HAL_TimeBase/Src/stm32wbxx_it.c | 157 + .../HAL/HAL_TimeBase/Src/system_stm32wbxx.c | 357 + .../Examples/HAL/HAL_TimeBase/readme.txt | 87 + .../HAL/HAL_TimeBase_RTC_ALARM/.extSettings | 9 + .../EWARM/HAL_TimeBase_RTC_ALARM.ewd | 1419 ++ .../EWARM/HAL_TimeBase_RTC_ALARM.ewp | 1128 ++ .../HAL/HAL_TimeBase_RTC_ALARM/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../HAL_TimeBase_RTC_ALARM.ioc | 106 + .../Examples/HAL/HAL_TimeBase_RTC_ALARM/Inc/main.h | 71 + .../Inc/stm32wbxx_hal_conf.h | 359 + .../HAL/HAL_TimeBase_RTC_ALARM/Inc/stm32wbxx_it.h | 64 + .../MDK-ARM/HAL_TimeBase_RTC_ALARM.uvoptx | 533 + .../MDK-ARM/HAL_TimeBase_RTC_ALARM.uvprojx | 556 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../HAL_TimeBase_RTC_ALARM/STM32CubeIDE/.cproject | 169 + .../HAL_TimeBase_RTC_ALARM/STM32CubeIDE/.project | 160 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/main.c | 227 + .../HAL_TimeBase_RTC_ALARM/Src/stm32wbxx_hal_msp.c | 81 + .../Src/stm32wbxx_hal_timebase_rtc_alarm.c | 301 + .../HAL/HAL_TimeBase_RTC_ALARM/Src/stm32wbxx_it.c | 137 + .../HAL_TimeBase_RTC_ALARM/Src/system_stm32wbxx.c | 357 + .../Examples/HAL/HAL_TimeBase_RTC_ALARM/readme.txt | 92 + .../HAL/HAL_TimeBase_RTC_WKUP/.extSettings | 9 + .../EWARM/HAL_TimeBase_RTC_WKUP.ewd | 1419 ++ .../EWARM/HAL_TimeBase_RTC_WKUP.ewp | 1128 ++ .../HAL/HAL_TimeBase_RTC_WKUP/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../HAL_TimeBase_RTC_WKUP.ioc | 106 + .../Examples/HAL/HAL_TimeBase_RTC_WKUP/Inc/main.h | 71 + .../HAL_TimeBase_RTC_WKUP/Inc/stm32wbxx_hal_conf.h | 359 + .../HAL/HAL_TimeBase_RTC_WKUP/Inc/stm32wbxx_it.h | 64 + .../MDK-ARM/HAL_TimeBase_RTC_WKUP.uvoptx | 533 + .../MDK-ARM/HAL_TimeBase_RTC_WKUP.uvprojx | 556 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../HAL_TimeBase_RTC_WKUP/STM32CubeIDE/.cproject | 169 + .../HAL_TimeBase_RTC_WKUP/STM32CubeIDE/.project | 160 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/main.c | 227 + .../HAL_TimeBase_RTC_WKUP/Src/stm32wbxx_hal_msp.c | 81 + .../Src/stm32wbxx_hal_timebase_rtc_wakeup.c | 279 + .../HAL/HAL_TimeBase_RTC_WKUP/Src/stm32wbxx_it.c | 137 + .../HAL_TimeBase_RTC_WKUP/Src/system_stm32wbxx.c | 357 + .../Examples/HAL/HAL_TimeBase_RTC_WKUP/readme.txt | 93 + .../Examples/HAL/HAL_TimeBase_TIM/.extSettings | 9 + .../HAL_TimeBase_TIM/EWARM/HAL_TimeBase_TIM.ewd | 1419 ++ .../HAL_TimeBase_TIM/EWARM/HAL_TimeBase_TIM.ewp | 1122 ++ .../HAL/HAL_TimeBase_TIM/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../HAL/HAL_TimeBase_TIM/HAL_TimeBase_TIM.ioc | 109 + .../Examples/HAL/HAL_TimeBase_TIM/Inc/main.h | 71 + .../HAL/HAL_TimeBase_TIM/Inc/stm32wbxx_hal_conf.h | 359 + .../HAL/HAL_TimeBase_TIM/Inc/stm32wbxx_it.h | 65 + .../MDK-ARM/HAL_TimeBase_TIM.uvoptx | 133 + .../MDK-ARM/HAL_TimeBase_TIM.uvprojx | 566 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../HAL/HAL_TimeBase_TIM/STM32CubeIDE/.cproject | 169 + .../HAL/HAL_TimeBase_TIM/STM32CubeIDE/.project | 150 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/HAL/HAL_TimeBase_TIM/Src/main.c | 260 + .../HAL/HAL_TimeBase_TIM/Src/stm32wbxx_hal_msp.c | 81 + .../Src/stm32wbxx_hal_timebase_tim.c | 114 + .../HAL/HAL_TimeBase_TIM/Src/stm32wbxx_it.c | 158 + .../HAL/HAL_TimeBase_TIM/Src/system_stm32wbxx.c | 357 + .../Examples/HAL/HAL_TimeBase_TIM/readme.txt | 88 + .../Examples/I2C/I2C_TwoBoards_ComDMA/.extSettings | 8 + .../EWARM/I2C_TwoBoards_ComDMA.ewd | 1419 ++ .../EWARM/I2C_TwoBoards_ComDMA.ewp | 1125 ++ .../I2C/I2C_TwoBoards_ComDMA/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../I2C_TwoBoards_ComDMA/I2C_TwoBoards_ComDMA.ioc | 170 + .../Examples/I2C/I2C_TwoBoards_ComDMA/Inc/main.h | 76 + .../I2C_TwoBoards_ComDMA/Inc/stm32wbxx_hal_conf.h | 359 + .../I2C/I2C_TwoBoards_ComDMA/Inc/stm32wbxx_it.h | 70 + .../MDK-ARM/I2C_TwoBoards_ComDMA.uvoptx | 133 + .../MDK-ARM/I2C_TwoBoards_ComDMA.uvprojx | 571 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../I2C_TwoBoards_ComDMA/STM32CubeIDE/.cproject | 169 + .../I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/.project | 155 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/I2C/I2C_TwoBoards_ComDMA/Src/main.c | 525 + .../I2C_TwoBoards_ComDMA/Src/stm32wbxx_hal_msp.c | 202 + .../I2C/I2C_TwoBoards_ComDMA/Src/stm32wbxx_it.c | 206 + .../I2C_TwoBoards_ComDMA/Src/system_stm32wbxx.c | 357 + .../Examples/I2C/I2C_TwoBoards_ComDMA/readme.txt | 134 + .../Examples/I2C/I2C_TwoBoards_ComIT/.extSettings | 8 + .../EWARM/I2C_TwoBoards_ComIT.ewd | 1419 ++ .../EWARM/I2C_TwoBoards_ComIT.ewp | 1125 ++ .../I2C/I2C_TwoBoards_ComIT/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../I2C_TwoBoards_ComIT/I2C_TwoBoards_ComIT.ioc | 130 + .../Examples/I2C/I2C_TwoBoards_ComIT/Inc/main.h | 76 + .../I2C_TwoBoards_ComIT/Inc/stm32wbxx_hal_conf.h | 359 + .../I2C/I2C_TwoBoards_ComIT/Inc/stm32wbxx_it.h | 68 + .../MDK-ARM/I2C_TwoBoards_ComIT.uvoptx | 133 + .../MDK-ARM/I2C_TwoBoards_ComIT.uvprojx | 571 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/.cproject | 169 + .../I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/.project | 155 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/I2C/I2C_TwoBoards_ComIT/Src/main.c | 502 + .../I2C_TwoBoards_ComIT/Src/stm32wbxx_hal_msp.c | 159 + .../I2C/I2C_TwoBoards_ComIT/Src/stm32wbxx_it.c | 176 + .../I2C/I2C_TwoBoards_ComIT/Src/system_stm32wbxx.c | 357 + .../Examples/I2C/I2C_TwoBoards_ComIT/readme.txt | 134 + .../Examples/I2C/I2C_WakeUpFromStop2/.extSettings | 8 + .../EWARM/I2C_WakeUpFromStop2.ewd | 1419 ++ .../EWARM/I2C_WakeUpFromStop2.ewp | 1125 ++ .../I2C/I2C_WakeUpFromStop2/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../I2C_WakeUpFromStop2/I2C_WakeUpFromStop2.ioc | 127 + .../Examples/I2C/I2C_WakeUpFromStop2/Inc/main.h | 77 + .../I2C_WakeUpFromStop2/Inc/stm32wbxx_hal_conf.h | 359 + .../I2C/I2C_WakeUpFromStop2/Inc/stm32wbxx_it.h | 66 + .../MDK-ARM/I2C_WakeUpFromStop2.uvoptx | 541 + .../MDK-ARM/I2C_WakeUpFromStop2.uvprojx | 552 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../I2C/I2C_WakeUpFromStop2/STM32CubeIDE/.cproject | 170 + .../I2C/I2C_WakeUpFromStop2/STM32CubeIDE/.project | 155 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/I2C/I2C_WakeUpFromStop2/Src/main.c | 533 + .../I2C_WakeUpFromStop2/Src/stm32wbxx_hal_msp.c | 172 + .../I2C/I2C_WakeUpFromStop2/Src/stm32wbxx_it.c | 149 + .../I2C/I2C_WakeUpFromStop2/Src/system_stm32wbxx.c | 357 + .../Examples/I2C/I2C_WakeUpFromStop2/readme.txt | 136 + .../Examples/I2S/I2S_Audio/readme.txt | 49 + .../Examples/IWDG/IWDG_WindowMode/.extSettings | 8 + .../IWDG/IWDG_WindowMode/EWARM/IWDG_WindowMode.ewd | 1419 ++ .../IWDG/IWDG_WindowMode/EWARM/IWDG_WindowMode.ewp | 1122 ++ .../IWDG/IWDG_WindowMode/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../IWDG/IWDG_WindowMode/IWDG_WindowMode.ioc | 115 + .../Examples/IWDG/IWDG_WindowMode/Inc/main.h | 71 + .../IWDG/IWDG_WindowMode/Inc/stm32wbxx_hal_conf.h | 359 + .../IWDG/IWDG_WindowMode/Inc/stm32wbxx_it.h | 70 + .../IWDG_WindowMode/MDK-ARM/IWDG_WindowMode.uvoptx | 509 + .../MDK-ARM/IWDG_WindowMode.uvprojx | 546 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../IWDG/IWDG_WindowMode/STM32CubeIDE/.cproject | 169 + .../IWDG/IWDG_WindowMode/STM32CubeIDE/.project | 150 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/IWDG/IWDG_WindowMode/Src/main.c | 283 + .../IWDG/IWDG_WindowMode/Src/stm32wbxx_hal_msp.c | 81 + .../IWDG/IWDG_WindowMode/Src/stm32wbxx_it.c | 215 + .../IWDG/IWDG_WindowMode/Src/system_stm32wbxx.c | 357 + .../Examples/IWDG/IWDG_WindowMode/readme.txt | 100 + .../LPTIM/LPTIM_PWMExternalClock/.extSettings | 8 + .../EWARM/LPTIM_PWMExternalClock.ewd | 1419 ++ .../EWARM/LPTIM_PWMExternalClock.ewp | 1122 ++ .../LPTIM/LPTIM_PWMExternalClock/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../LPTIM/LPTIM_PWMExternalClock/Inc/main.h | 75 + .../Inc/stm32wbxx_hal_conf.h | 359 + .../LPTIM_PWMExternalClock/Inc/stm32wbxx_it.h | 70 + .../LPTIM_PWMExternalClock.ioc | 123 + .../MDK-ARM/LPTIM_PWMExternalClock.uvoptx | 509 + .../MDK-ARM/LPTIM_PWMExternalClock.uvprojx | 546 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../LPTIM_PWMExternalClock/STM32CubeIDE/.cproject | 169 + .../LPTIM_PWMExternalClock/STM32CubeIDE/.project | 150 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../LPTIM/LPTIM_PWMExternalClock/Src/main.c | 289 + .../LPTIM_PWMExternalClock/Src/stm32wbxx_hal_msp.c | 154 + .../LPTIM_PWMExternalClock/Src/stm32wbxx_it.c | 216 + .../LPTIM_PWMExternalClock/Src/system_stm32wbxx.c | 357 + .../LPTIM/LPTIM_PWMExternalClock/readme.txt | 100 + .../Examples/LPTIM/LPTIM_PulseCounter/.extSettings | 8 + .../EWARM/LPTIM_PulseCounter.ewd | 1419 ++ .../EWARM/LPTIM_PulseCounter.ewp | 1122 ++ .../LPTIM/LPTIM_PulseCounter/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/LPTIM/LPTIM_PulseCounter/Inc/main.h | 71 + .../LPTIM_PulseCounter/Inc/stm32wbxx_hal_conf.h | 359 + .../LPTIM/LPTIM_PulseCounter/Inc/stm32wbxx_it.h | 71 + .../LPTIM_PulseCounter/LPTIM_PulseCounter.ioc | 117 + .../MDK-ARM/LPTIM_PulseCounter.uvoptx | 509 + .../MDK-ARM/LPTIM_PulseCounter.uvprojx | 546 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../LPTIM_PulseCounter/STM32CubeIDE/.cproject | 169 + .../LPTIM/LPTIM_PulseCounter/STM32CubeIDE/.project | 150 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/LPTIM/LPTIM_PulseCounter/Src/main.c | 289 + .../LPTIM_PulseCounter/Src/stm32wbxx_hal_msp.c | 196 + .../LPTIM/LPTIM_PulseCounter/Src/stm32wbxx_it.c | 220 + .../LPTIM_PulseCounter/Src/system_stm32wbxx.c | 357 + .../Examples/LPTIM/LPTIM_PulseCounter/readme.txt | 89 + .../Examples/PKA/PKA_ECDSA_Sign/.extSettings | 9 + .../PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewd | 1419 ++ .../PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewp | 1132 ++ .../Examples/PKA/PKA_ECDSA_Sign/EWARM/Project.eww | 7 + .../PKA_ECDSA_Sign/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../PKA_ECDSA_Sign/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../PKA_ECDSA_Sign/EWARM/stm32wb35xx_sram_cm4.icf | 39 + .../Examples/PKA/PKA_ECDSA_Sign/Inc/SigGen.h | 51 + .../Examples/PKA/PKA_ECDSA_Sign/Inc/main.h | 75 + .../Examples/PKA/PKA_ECDSA_Sign/Inc/prime256v1.h | 54 + .../PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_it.h | 70 + .../PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvoptx | 533 + .../PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvprojx | 556 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../Examples/PKA/PKA_ECDSA_Sign/PKA_ECDSA_Sign.ioc | 110 + .../PKA/PKA_ECDSA_Sign/STM32CubeIDE/.cproject | 169 + .../PKA/PKA_ECDSA_Sign/STM32CubeIDE/.project | 160 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/PKA/PKA_ECDSA_Sign/Src/SigGen.c | 97 + .../Examples/PKA/PKA_ECDSA_Sign/Src/SigGen.txt | 5878 ++++++++ .../Examples/PKA/PKA_ECDSA_Sign/Src/main.c | 290 + .../Examples/PKA/PKA_ECDSA_Sign/Src/prime256v1.c | 96 + .../PKA/PKA_ECDSA_Sign/Src/stm32wbxx_hal_msp.c | 129 + .../Examples/PKA/PKA_ECDSA_Sign/Src/stm32wbxx_it.c | 206 + .../PKA/PKA_ECDSA_Sign/Src/system_stm32wbxx.c | 357 + .../Examples/PKA/PKA_ECDSA_Sign/readme.txt | 86 + .../Examples/PKA/PKA_ECDSA_Verify_IT/.extSettings | 9 + .../EWARM/PKA_ECDSA_Verify_IT.ewd | 1419 ++ .../EWARM/PKA_ECDSA_Verify_IT.ewp | 1131 ++ .../PKA/PKA_ECDSA_Verify_IT/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../EWARM/stm32wb35xx_sram_cm4.icf | 39 + .../Examples/PKA/PKA_ECDSA_Verify_IT/Inc/SigVer.h | 49 + .../Examples/PKA/PKA_ECDSA_Verify_IT/Inc/main.h | 73 + .../PKA/PKA_ECDSA_Verify_IT/Inc/prime256v1.h | 54 + .../PKA_ECDSA_Verify_IT/Inc/stm32wbxx_hal_conf.h | 359 + .../PKA/PKA_ECDSA_Verify_IT/Inc/stm32wbxx_it.h | 70 + .../MDK-ARM/PKA_ECDSA_Verify_IT.uvoptx | 533 + .../MDK-ARM/PKA_ECDSA_Verify_IT.uvprojx | 556 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../PKA_ECDSA_Verify_IT/PKA_ECDSA_Verify_IT.ioc | 110 + .../PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/.cproject | 169 + .../PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/.project | 160 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/PKA/PKA_ECDSA_Verify_IT/Src/SigVer.c | 94 + .../PKA/PKA_ECDSA_Verify_IT/Src/SigVer.rsp | 8032 +++++++++++ .../Examples/PKA/PKA_ECDSA_Verify_IT/Src/main.c | 317 + .../PKA/PKA_ECDSA_Verify_IT/Src/prime256v1.c | 96 + .../PKA_ECDSA_Verify_IT/Src/stm32wbxx_hal_msp.c | 131 + .../PKA/PKA_ECDSA_Verify_IT/Src/stm32wbxx_it.c | 215 + .../PKA/PKA_ECDSA_Verify_IT/Src/system_stm32wbxx.c | 357 + .../Examples/PKA/PKA_ECDSA_Verify_IT/readme.txt | 91 + .../Examples/PWR/PWR_LPRUN/.extSettings | 8 + .../Examples/PWR/PWR_LPRUN/EWARM/PWR_LPRUN.ewd | 1419 ++ .../Examples/PWR/PWR_LPRUN/EWARM/PWR_LPRUN.ewp | 1119 ++ .../Examples/PWR/PWR_LPRUN/EWARM/Project.eww | 7 + .../PWR/PWR_LPRUN/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../PWR/PWR_LPRUN/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/PWR/PWR_LPRUN/Inc/main.h | 71 + .../PWR/PWR_LPRUN/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/PWR/PWR_LPRUN/Inc/stm32wbxx_it.h | 70 + .../PWR/PWR_LPRUN/MDK-ARM/PWR_LPRUN.uvoptx | 497 + .../PWR/PWR_LPRUN/MDK-ARM/PWR_LPRUN.uvprojx | 541 + .../PWR_LPRUN/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../PWR_LPRUN/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../Examples/PWR/PWR_LPRUN/PWR_LPRUN.ioc | 106 + .../Examples/PWR/PWR_LPRUN/STM32CubeIDE/.cproject | 169 + .../Examples/PWR/PWR_LPRUN/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../PWR_LPRUN/STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/PWR/PWR_LPRUN/Src/main.c | 294 + .../Examples/PWR/PWR_LPRUN/Src/stm32wbxx_hal_msp.c | 81 + .../Examples/PWR/PWR_LPRUN/Src/stm32wbxx_it.c | 207 + .../Examples/PWR/PWR_LPRUN/Src/system_stm32wbxx.c | 357 + .../Examples/PWR/PWR_LPRUN/readme.txt | 89 + .../Examples/PWR/PWR_LPSLEEP/.extSettings | 8 + .../Examples/PWR/PWR_LPSLEEP/EWARM/PWR_LPSLEEP.ewd | 1419 ++ .../Examples/PWR/PWR_LPSLEEP/EWARM/PWR_LPSLEEP.ewp | 1119 ++ .../Examples/PWR/PWR_LPSLEEP/EWARM/Project.eww | 7 + .../PWR_LPSLEEP/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../PWR_LPSLEEP/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/PWR/PWR_LPSLEEP/Inc/main.h | 73 + .../PWR/PWR_LPSLEEP/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/PWR/PWR_LPSLEEP/Inc/stm32wbxx_it.h | 70 + .../PWR/PWR_LPSLEEP/MDK-ARM/PWR_LPSLEEP.uvoptx | 497 + .../PWR/PWR_LPSLEEP/MDK-ARM/PWR_LPSLEEP.uvprojx | 541 + .../PWR_LPSLEEP/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../PWR_LPSLEEP/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../Examples/PWR/PWR_LPSLEEP/PWR_LPSLEEP.ioc | 106 + .../PWR/PWR_LPSLEEP/STM32CubeIDE/.cproject | 169 + .../Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/PWR/PWR_LPSLEEP/Src/main.c | 304 + .../PWR/PWR_LPSLEEP/Src/stm32wbxx_hal_msp.c | 83 + .../Examples/PWR/PWR_LPSLEEP/Src/stm32wbxx_it.c | 216 + .../PWR/PWR_LPSLEEP/Src/system_stm32wbxx.c | 357 + .../Examples/PWR/PWR_LPSLEEP/readme.txt | 99 + .../Examples/PWR/PWR_PVD/.extSettings | 8 + .../Examples/PWR/PWR_PVD/EWARM/PWR_PVD.ewd | 1419 ++ .../Examples/PWR/PWR_PVD/EWARM/PWR_PVD.ewp | 1119 ++ .../Examples/PWR/PWR_PVD/EWARM/Project.eww | 7 + .../PWR/PWR_PVD/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../PWR/PWR_PVD/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Inc/main.h | 71 + .../Examples/PWR/PWR_PVD/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/PWR/PWR_PVD/Inc/stm32wbxx_it.h | 70 + .../Examples/PWR/PWR_PVD/MDK-ARM/PWR_PVD.uvoptx | 497 + .../Examples/PWR/PWR_PVD/MDK-ARM/PWR_PVD.uvprojx | 542 + .../PWR/PWR_PVD/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../PWR/PWR_PVD/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../NUCLEO-WB35CE/Examples/PWR/PWR_PVD/PWR_PVD.ioc | 106 + .../Examples/PWR/PWR_PVD/STM32CubeIDE/.cproject | 171 + .../Examples/PWR/PWR_PVD/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../PWR_PVD/STM32CubeIDE/Application/User/sysmem.c | 83 + .../PWR_PVD/STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Src/main.c | 249 + .../Examples/PWR/PWR_PVD/Src/stm32wbxx_hal_msp.c | 81 + .../Examples/PWR/PWR_PVD/Src/stm32wbxx_it.c | 215 + .../Examples/PWR/PWR_PVD/Src/system_stm32wbxx.c | 357 + .../NUCLEO-WB35CE/Examples/PWR/PWR_PVD/readme.txt | 79 + .../Examples/PWR/PWR_STANDBY_RTC/.extSettings | 8 + .../PWR/PWR_STANDBY_RTC/EWARM/PWR_STANDBY_RTC.ewd | 1419 ++ .../PWR/PWR_STANDBY_RTC/EWARM/PWR_STANDBY_RTC.ewp | 1125 ++ .../Examples/PWR/PWR_STANDBY_RTC/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/PWR/PWR_STANDBY_RTC/Inc/main.h | 73 + .../PWR/PWR_STANDBY_RTC/Inc/stm32wbxx_hal_conf.h | 359 + .../PWR/PWR_STANDBY_RTC/Inc/stm32wbxx_it.h | 70 + .../PWR_STANDBY_RTC/MDK-ARM/PWR_STANDBY_RTC.uvoptx | 521 + .../MDK-ARM/PWR_STANDBY_RTC.uvprojx | 551 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../PWR/PWR_STANDBY_RTC/PWR_STANDBY_RTC.ioc | 115 + .../PWR/PWR_STANDBY_RTC/STM32CubeIDE/.cproject | 169 + .../PWR/PWR_STANDBY_RTC/STM32CubeIDE/.project | 155 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/PWR/PWR_STANDBY_RTC/Src/main.c | 343 + .../PWR/PWR_STANDBY_RTC/Src/stm32wbxx_hal_msp.c | 160 + .../PWR/PWR_STANDBY_RTC/Src/stm32wbxx_it.c | 216 + .../PWR/PWR_STANDBY_RTC/Src/system_stm32wbxx.c | 357 + .../Examples/PWR/PWR_STANDBY_RTC/readme.txt | 108 + .../Examples/PWR/PWR_STOP2_RTC/.extSettings | 8 + .../PWR/PWR_STOP2_RTC/EWARM/PWR_STOP2_RTC.ewd | 1419 ++ .../PWR/PWR_STOP2_RTC/EWARM/PWR_STOP2_RTC.ewp | 1125 ++ .../Examples/PWR/PWR_STOP2_RTC/EWARM/Project.eww | 7 + .../PWR_STOP2_RTC/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../PWR_STOP2_RTC/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/PWR/PWR_STOP2_RTC/Inc/main.h | 73 + .../PWR/PWR_STOP2_RTC/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/PWR/PWR_STOP2_RTC/Inc/stm32wbxx_it.h | 64 + .../PWR/PWR_STOP2_RTC/MDK-ARM/PWR_STOP2_RTC.uvoptx | 521 + .../PWR_STOP2_RTC/MDK-ARM/PWR_STOP2_RTC.uvprojx | 551 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../Examples/PWR/PWR_STOP2_RTC/PWR_STOP2_RTC.ioc | 115 + .../PWR/PWR_STOP2_RTC/STM32CubeIDE/.cproject | 169 + .../PWR/PWR_STOP2_RTC/STM32CubeIDE/.project | 155 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/PWR/PWR_STOP2_RTC/Src/main.c | 330 + .../PWR/PWR_STOP2_RTC/Src/stm32wbxx_hal_msp.c | 161 + .../Examples/PWR/PWR_STOP2_RTC/Src/stm32wbxx_it.c | 131 + .../PWR/PWR_STOP2_RTC/Src/system_stm32wbxx.c | 357 + .../Examples/PWR/PWR_STOP2_RTC/readme.txt | 103 + .../Examples/QSPI/QSPI_ReadWrite_DMA/.extSettings | 8 + .../QSPI/QSPI_ReadWrite_DMA/EWARM/Project.eww | 7 + .../EWARM/QSPI_ReadWrite_DMA.ewd | 1419 ++ .../EWARM/QSPI_ReadWrite_DMA.ewp | 1126 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/QSPI/QSPI_ReadWrite_DMA/Inc/main.h | 138 + .../QSPI_ReadWrite_DMA/Inc/stm32wbxx_hal_conf.h | 359 + .../QSPI/QSPI_ReadWrite_DMA/Inc/stm32wbxx_it.h | 72 + .../MDK-ARM/QSPI_ReadWrite_DMA.uvoptx | 526 + .../MDK-ARM/QSPI_ReadWrite_DMA.uvprojx | 547 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../QSPI/QSPI_ReadWrite_DMA/QSPI_ReadWrite_DMA.ioc | 162 + .../QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/.cproject | 170 + .../QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/.project | 150 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/QSPI/QSPI_ReadWrite_DMA/Src/main.c | 602 + .../QSPI_ReadWrite_DMA/Src/stm32wbxx_hal_msp.c | 191 + .../QSPI/QSPI_ReadWrite_DMA/Src/stm32wbxx_it.c | 235 + .../QSPI/QSPI_ReadWrite_DMA/Src/system_stm32wbxx.c | 351 + .../Examples/QSPI/QSPI_ReadWrite_DMA/readme.txt | 82 + .../Examples/RCC/RCC_ClockConfig/.extSettings | 8 + .../Examples/RCC/RCC_ClockConfig/EWARM/Project.eww | 7 + .../RCC/RCC_ClockConfig/EWARM/RCC_ClockConfig.ewd | 1419 ++ .../RCC/RCC_ClockConfig/EWARM/RCC_ClockConfig.ewp | 1119 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/RCC/RCC_ClockConfig/Inc/main.h | 71 + .../RCC/RCC_ClockConfig/Inc/stm32wbxx_hal_conf.h | 359 + .../RCC/RCC_ClockConfig/Inc/stm32wbxx_it.h | 64 + .../RCC_ClockConfig/MDK-ARM/RCC_ClockConfig.uvoptx | 497 + .../MDK-ARM/RCC_ClockConfig.uvprojx | 541 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../RCC/RCC_ClockConfig/RCC_ClockConfig.ioc | 106 + .../RCC/RCC_ClockConfig/STM32CubeIDE/.cproject | 169 + .../RCC/RCC_ClockConfig/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/RCC/RCC_ClockConfig/Src/main.c | 489 + .../RCC/RCC_ClockConfig/Src/stm32wbxx_hal_msp.c | 81 + .../RCC/RCC_ClockConfig/Src/stm32wbxx_it.c | 129 + .../RCC/RCC_ClockConfig/Src/system_stm32wbxx.c | 357 + .../Examples/RCC/RCC_ClockConfig/readme.txt | 98 + .../Examples/RNG/RNG_MultiRNG/.extSettings | 8 + .../Examples/RNG/RNG_MultiRNG/EWARM/Project.eww | 7 + .../RNG/RNG_MultiRNG/EWARM/RNG_MultiRNG.ewd | 1419 ++ .../RNG/RNG_MultiRNG/EWARM/RNG_MultiRNG.ewp | 1122 ++ .../RNG_MultiRNG/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../RNG_MultiRNG/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/RNG/RNG_MultiRNG/Inc/main.h | 72 + .../RNG/RNG_MultiRNG/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/RNG/RNG_MultiRNG/Inc/stm32wbxx_it.h | 66 + .../RNG/RNG_MultiRNG/MDK-ARM/RNG_MultiRNG.uvoptx | 536 + .../RNG/RNG_MultiRNG/MDK-ARM/RNG_MultiRNG.uvprojx | 547 + .../RNG_MultiRNG/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../RNG_MultiRNG/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../Examples/RNG/RNG_MultiRNG/RNG_MultiRNG.ioc | 110 + .../RNG/RNG_MultiRNG/STM32CubeIDE/.cproject | 170 + .../RNG/RNG_MultiRNG/STM32CubeIDE/.project | 150 + .../STM32CubeIDE/.settings/language.settings.xml | 27 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/RNG/RNG_MultiRNG/Src/main.c | 276 + .../RNG/RNG_MultiRNG/Src/stm32wbxx_hal_msp.c | 153 + .../Examples/RNG/RNG_MultiRNG/Src/stm32wbxx_it.c | 129 + .../RNG/RNG_MultiRNG/Src/system_stm32wbxx.c | 357 + .../Examples/RNG/RNG_MultiRNG/readme.txt | 75 + .../Examples/RTC/RTC_Alarm/.extSettings | 8 + .../Examples/RTC/RTC_Alarm/EWARM/Project.eww | 7 + .../Examples/RTC/RTC_Alarm/EWARM/RTC_Alarm.ewd | 1419 ++ .../Examples/RTC/RTC_Alarm/EWARM/RTC_Alarm.ewp | 1125 ++ .../RTC/RTC_Alarm/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../RTC/RTC_Alarm/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/RTC/RTC_Alarm/Inc/main.h | 86 + .../RTC/RTC_Alarm/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/RTC/RTC_Alarm/Inc/stm32wbxx_it.h | 65 + .../RTC/RTC_Alarm/MDK-ARM/RTC_Alarm.uvoptx | 521 + .../RTC/RTC_Alarm/MDK-ARM/RTC_Alarm.uvprojx | 551 + .../RTC_Alarm/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../RTC_Alarm/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../Examples/RTC/RTC_Alarm/RTC_Alarm.ioc | 147 + .../Examples/RTC/RTC_Alarm/STM32CubeIDE/.cproject | 169 + .../Examples/RTC/RTC_Alarm/STM32CubeIDE/.project | 155 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../RTC_Alarm/STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/RTC/RTC_Alarm/Src/main.c | 320 + .../Examples/RTC/RTC_Alarm/Src/stm32wbxx_hal_msp.c | 191 + .../Examples/RTC/RTC_Alarm/Src/stm32wbxx_it.c | 135 + .../Examples/RTC/RTC_Alarm/Src/system_stm32wbxx.c | 357 + .../Examples/RTC/RTC_Alarm/readme.txt | 97 + .../Examples/RTC/RTC_Tamper/.extSettings | 8 + .../Examples/RTC/RTC_Tamper/EWARM/Project.eww | 7 + .../Examples/RTC/RTC_Tamper/EWARM/RTC_Tamper.ewd | 1419 ++ .../Examples/RTC/RTC_Tamper/EWARM/RTC_Tamper.ewp | 1125 ++ .../RTC/RTC_Tamper/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../RTC/RTC_Tamper/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/RTC/RTC_Tamper/Inc/main.h | 86 + .../RTC/RTC_Tamper/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/RTC/RTC_Tamper/Inc/stm32wbxx_it.h | 65 + .../RTC/RTC_Tamper/MDK-ARM/RTC_Tamper.uvoptx | 521 + .../RTC/RTC_Tamper/MDK-ARM/RTC_Tamper.uvprojx | 552 + .../RTC_Tamper/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../RTC_Tamper/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../Examples/RTC/RTC_Tamper/RTC_Tamper.ioc | 125 + .../Examples/RTC/RTC_Tamper/STM32CubeIDE/.cproject | 170 + .../Examples/RTC/RTC_Tamper/STM32CubeIDE/.project | 155 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 159 + .../STM32CubeIDE/Application/User/sysmem.c | 58 + .../RTC_Tamper/STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/RTC/RTC_Tamper/Src/main.c | 355 + .../RTC/RTC_Tamper/Src/stm32wbxx_hal_msp.c | 195 + .../Examples/RTC/RTC_Tamper/Src/stm32wbxx_it.c | 138 + .../Examples/RTC/RTC_Tamper/Src/system_stm32wbxx.c | 357 + .../Examples/RTC/RTC_Tamper/readme.txt | 102 + .../SPI/SPI_FullDuplex_ComDMA_Master/.extSettings | 8 + .../SPI_FullDuplex_ComDMA_Master/EWARM/Project.eww | 7 + .../EWARM/SPI_FullDuplex_ComDMA_Master.ewd | 1419 ++ .../EWARM/SPI_FullDuplex_ComDMA_Master.ewp | 1125 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../SPI/SPI_FullDuplex_ComDMA_Master/Inc/main.h | 72 + .../Inc/stm32wbxx_hal_conf.h | 359 + .../Inc/stm32wbxx_it.h | 68 + .../MDK-ARM/SPI_FullDuplex_ComDMA_Master.uvoptx | 521 + .../MDK-ARM/SPI_FullDuplex_ComDMA_Master.uvprojx | 551 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../SPI_FullDuplex_ComDMA_Master.ioc | 172 + .../STM32CubeIDE/.cproject | 169 + .../STM32CubeIDE/.project | 155 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../SPI/SPI_FullDuplex_ComDMA_Master/Src/main.c | 397 + .../Src/stm32wbxx_hal_msp.c | 199 + .../Src/stm32wbxx_it.c | 177 + .../Src/system_stm32wbxx.c | 357 + .../SPI/SPI_FullDuplex_ComDMA_Master/readme.txt | 136 + .../SPI/SPI_FullDuplex_ComDMA_Slave/.extSettings | 8 + .../SPI_FullDuplex_ComDMA_Slave/EWARM/Project.eww | 7 + .../EWARM/SPI_FullDuplex_ComDMA_Slave.ewd | 1419 ++ .../EWARM/SPI_FullDuplex_ComDMA_Slave.ewp | 1125 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../SPI/SPI_FullDuplex_ComDMA_Slave/Inc/main.h | 72 + .../Inc/stm32wbxx_hal_conf.h | 359 + .../SPI_FullDuplex_ComDMA_Slave/Inc/stm32wbxx_it.h | 68 + .../MDK-ARM/SPI_FullDuplex_ComDMA_Slave.uvoptx | 521 + .../MDK-ARM/SPI_FullDuplex_ComDMA_Slave.uvprojx | 551 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../SPI_FullDuplex_ComDMA_Slave.ioc | 169 + .../STM32CubeIDE/.cproject | 170 + .../STM32CubeIDE/.project | 155 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../SPI/SPI_FullDuplex_ComDMA_Slave/Src/main.c | 386 + .../Src/stm32wbxx_hal_msp.c | 199 + .../SPI_FullDuplex_ComDMA_Slave/Src/stm32wbxx_it.c | 177 + .../Src/system_stm32wbxx.c | 357 + .../SPI/SPI_FullDuplex_ComDMA_Slave/readme.txt | 136 + .../Examples/TIM/TIM_OCActive/.extSettings | 8 + .../Examples/TIM/TIM_OCActive/EWARM/Project.eww | 7 + .../TIM/TIM_OCActive/EWARM/TIM_OCActive.ewd | 1419 ++ .../TIM/TIM_OCActive/EWARM/TIM_OCActive.ewp | 1119 ++ .../TIM_OCActive/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../TIM_OCActive/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/TIM/TIM_OCActive/Inc/main.h | 80 + .../TIM/TIM_OCActive/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/TIM/TIM_OCActive/Inc/stm32wbxx_it.h | 64 + .../TIM/TIM_OCActive/MDK-ARM/TIM_OCActive.uvoptx | 497 + .../TIM/TIM_OCActive/MDK-ARM/TIM_OCActive.uvprojx | 541 + .../TIM_OCActive/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../TIM_OCActive/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../TIM/TIM_OCActive/STM32CubeIDE/.cproject | 169 + .../TIM/TIM_OCActive/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/TIM/TIM_OCActive/Src/main.c | 321 + .../TIM/TIM_OCActive/Src/stm32wbxx_hal_msp.c | 157 + .../Examples/TIM/TIM_OCActive/Src/stm32wbxx_it.c | 120 + .../TIM/TIM_OCActive/Src/system_stm32wbxx.c | 357 + .../Examples/TIM/TIM_OCActive/TIM_OCActive.ioc | 165 + .../Examples/TIM/TIM_OCActive/readme.txt | 128 + .../Examples/TIM/TIM_PWMInput/.extSettings | 8 + .../Examples/TIM/TIM_PWMInput/EWARM/Project.eww | 7 + .../TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewd | 1419 ++ .../TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewp | 1119 ++ .../TIM_PWMInput/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../TIM_PWMInput/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/TIM/TIM_PWMInput/Inc/main.h | 71 + .../TIM/TIM_PWMInput/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/TIM/TIM_PWMInput/Inc/stm32wbxx_it.h | 67 + .../TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvoptx | 529 + .../TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvprojx | 542 + .../TIM_PWMInput/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../TIM_PWMInput/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../TIM/TIM_PWMInput/STM32CubeIDE/.cproject | 169 + .../TIM/TIM_PWMInput/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/TIM/TIM_PWMInput/Src/main.c | 356 + .../TIM/TIM_PWMInput/Src/stm32wbxx_hal_msp.c | 150 + .../Examples/TIM/TIM_PWMInput/Src/stm32wbxx_it.c | 162 + .../TIM/TIM_PWMInput/Src/system_stm32wbxx.c | 357 + .../Examples/TIM/TIM_PWMInput/TIM_PWMInput.ioc | 134 + .../Examples/TIM/TIM_PWMInput/readme.txt | 91 + .../Examples/TIM/TIM_PWMOutput/.extSettings | 8 + .../Examples/TIM/TIM_PWMOutput/EWARM/Project.eww | 7 + .../TIM/TIM_PWMOutput/EWARM/TIM_PWMOutput.ewd | 1419 ++ .../TIM/TIM_PWMOutput/EWARM/TIM_PWMOutput.ewp | 1119 ++ .../TIM_PWMOutput/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../TIM_PWMOutput/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/TIM/TIM_PWMOutput/Inc/main.h | 120 + .../TIM/TIM_PWMOutput/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/TIM/TIM_PWMOutput/Inc/stm32wbxx_it.h | 66 + .../TIM/TIM_PWMOutput/MDK-ARM/TIM_PWMOutput.uvoptx | 497 + .../TIM_PWMOutput/MDK-ARM/TIM_PWMOutput.uvprojx | 541 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../TIM/TIM_PWMOutput/STM32CubeIDE/.cproject | 169 + .../TIM/TIM_PWMOutput/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/TIM/TIM_PWMOutput/Src/main.c | 317 + .../TIM/TIM_PWMOutput/Src/stm32wbxx_hal_msp.c | 157 + .../Examples/TIM/TIM_PWMOutput/Src/stm32wbxx_it.c | 148 + .../TIM/TIM_PWMOutput/Src/system_stm32wbxx.c | 357 + .../Examples/TIM/TIM_PWMOutput/TIM_PWMOutput.ioc | 169 + .../Examples/TIM/TIM_PWMOutput/readme.txt | 109 + .../TSC/TSC_BasicAcquisition_Interrupt/readme.txt | 46 + .../UART/UART_HyperTerminal_DMA/.extSettings | 8 + .../UART/UART_HyperTerminal_DMA/EWARM/Project.eww | 7 + .../EWARM/UART_HyperTerminal_DMA.ewd | 1419 ++ .../EWARM/UART_HyperTerminal_DMA.ewp | 1125 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../UART/UART_HyperTerminal_DMA/Inc/main.h | 77 + .../Inc/stm32wbxx_hal_conf.h | 359 + .../UART/UART_HyperTerminal_DMA/Inc/stm32wbxx_it.h | 69 + .../MDK-ARM/UART_HyperTerminal_DMA.uvoptx | 521 + .../MDK-ARM/UART_HyperTerminal_DMA.uvprojx | 551 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../UART_HyperTerminal_DMA/STM32CubeIDE/.cproject | 169 + .../UART_HyperTerminal_DMA/STM32CubeIDE/.project | 155 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../UART/UART_HyperTerminal_DMA/Src/main.c | 397 + .../UART_HyperTerminal_DMA/Src/stm32wbxx_hal_msp.c | 194 + .../UART/UART_HyperTerminal_DMA/Src/stm32wbxx_it.c | 193 + .../UART_HyperTerminal_DMA/Src/system_stm32wbxx.c | 357 + .../UART_HyperTerminal_DMA.ioc | 175 + .../UART/UART_HyperTerminal_DMA/readme.txt | 141 + .../UART/UART_HyperTerminal_IT/.extSettings | 8 + .../UART/UART_HyperTerminal_IT/EWARM/Project.eww | 7 + .../EWARM/UART_HyperTerminal_IT.ewd | 1419 ++ .../EWARM/UART_HyperTerminal_IT.ewp | 1125 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/UART/UART_HyperTerminal_IT/Inc/main.h | 77 + .../UART_HyperTerminal_IT/Inc/stm32wbxx_hal_conf.h | 359 + .../UART/UART_HyperTerminal_IT/Inc/stm32wbxx_it.h | 65 + .../MDK-ARM/UART_HyperTerminal_IT.uvoptx | 521 + .../MDK-ARM/UART_HyperTerminal_IT.uvprojx | 551 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../UART_HyperTerminal_IT/STM32CubeIDE/.cproject | 169 + .../UART_HyperTerminal_IT/STM32CubeIDE/.project | 155 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/UART/UART_HyperTerminal_IT/Src/main.c | 377 + .../UART_HyperTerminal_IT/Src/stm32wbxx_hal_msp.c | 154 + .../UART/UART_HyperTerminal_IT/Src/stm32wbxx_it.c | 135 + .../UART_HyperTerminal_IT/Src/system_stm32wbxx.c | 357 + .../UART_HyperTerminal_IT.ioc | 135 + .../Examples/UART/UART_HyperTerminal_IT/readme.txt | 141 + .../Examples/UART/UART_Printf/.extSettings | 8 + .../Examples/UART/UART_Printf/EWARM/Project.eww | 7 + .../UART/UART_Printf/EWARM/UART_Printf.ewd | 1419 ++ .../UART/UART_Printf/EWARM/UART_Printf.ewp | 1125 ++ .../UART_Printf/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../UART_Printf/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/UART/UART_Printf/Inc/main.h | 72 + .../UART/UART_Printf/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/UART/UART_Printf/Inc/stm32wbxx_it.h | 66 + .../UART/UART_Printf/MDK-ARM/UART_Printf.uvoptx | 521 + .../UART/UART_Printf/MDK-ARM/UART_Printf.uvprojx | 552 + .../UART_Printf/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../UART_Printf/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../UART/UART_Printf/STM32CubeIDE/.cproject | 169 + .../UART/UART_Printf/STM32CubeIDE/.project | 155 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/UART/UART_Printf/Src/main.c | 292 + .../UART/UART_Printf/Src/stm32wbxx_hal_msp.c | 147 + .../Examples/UART/UART_Printf/Src/stm32wbxx_it.c | 149 + .../UART/UART_Printf/Src/system_stm32wbxx.c | 357 + .../Examples/UART/UART_Printf/UART_Printf.ioc | 136 + .../Examples/UART/UART_Printf/readme.txt | 111 + .../Examples/WWDG/WWDG_Example/.extSettings | 8 + .../Examples/WWDG/WWDG_Example/EWARM/Project.eww | 7 + .../WWDG/WWDG_Example/EWARM/WWDG_Example.ewd | 1419 ++ .../WWDG/WWDG_Example/EWARM/WWDG_Example.ewp | 1122 ++ .../WWDG_Example/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../WWDG_Example/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples/WWDG/WWDG_Example/Inc/main.h | 71 + .../WWDG/WWDG_Example/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples/WWDG/WWDG_Example/Inc/stm32wbxx_it.h | 70 + .../WWDG/WWDG_Example/MDK-ARM/WWDG_Example.uvoptx | 529 + .../WWDG/WWDG_Example/MDK-ARM/WWDG_Example.uvprojx | 547 + .../WWDG_Example/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../WWDG_Example/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../WWDG/WWDG_Example/STM32CubeIDE/.cproject | 170 + .../WWDG/WWDG_Example/STM32CubeIDE/.project | 150 + .../STM32CubeIDE/.settings/language.settings.xml | 27 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples/WWDG/WWDG_Example/Src/main.c | 313 + .../WWDG/WWDG_Example/Src/stm32wbxx_hal_msp.c | 101 + .../Examples/WWDG/WWDG_Example/Src/stm32wbxx_it.c | 222 + .../WWDG/WWDG_Example/Src/system_stm32wbxx.c | 357 + .../Examples/WWDG/WWDG_Example/WWDG_Example.ioc | 116 + .../Examples/WWDG/WWDG_Example/readme.txt | 109 + .../ADC/ADC_AnalogWatchdog_Init/.extSettings | 7 + .../ADC_AnalogWatchdog_Init.ioc | 154 + .../EWARM/ADC_AnalogWatchdog_Init.ewd | 1419 ++ .../EWARM/ADC_AnalogWatchdog_Init.ewp | 1089 ++ .../ADC/ADC_AnalogWatchdog_Init/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../ADC/ADC_AnalogWatchdog_Init/Inc/main.h | 113 + .../ADC/ADC_AnalogWatchdog_Init/Inc/stm32_assert.h | 53 + .../ADC/ADC_AnalogWatchdog_Init/Inc/stm32wbxx_it.h | 74 + .../MDK-ARM/ADC_AnalogWatchdog_Init.uvoptx | 357 + .../MDK-ARM/ADC_AnalogWatchdog_Init.uvprojx | 482 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../ADC_AnalogWatchdog_Init/STM32CubeIDE/.cproject | 187 + .../ADC_AnalogWatchdog_Init/STM32CubeIDE/.project | 90 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 159 + .../STM32CubeIDE/Application/User/sysmem.c | 58 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../ADC/ADC_AnalogWatchdog_Init/Src/main.c | 645 + .../ADC/ADC_AnalogWatchdog_Init/Src/stm32wbxx_it.c | 248 + .../ADC_AnalogWatchdog_Init/Src/system_stm32wbxx.c | 357 + .../ADC/ADC_AnalogWatchdog_Init/readme.txt | 94 + .../ADC/ADC_Oversampling_Init/.extSettings | 7 + .../ADC_Oversampling_Init.ioc | 148 + .../EWARM/ADC_Oversampling_Init.ewd | 1419 ++ .../EWARM/ADC_Oversampling_Init.ewp | 1089 ++ .../ADC/ADC_Oversampling_Init/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../ADC/ADC_Oversampling_Init/Inc/main.h | 112 + .../ADC/ADC_Oversampling_Init/Inc/stm32_assert.h | 53 + .../ADC/ADC_Oversampling_Init/Inc/stm32wbxx_it.h | 74 + .../MDK-ARM/ADC_Oversampling_Init.uvoptx | 357 + .../MDK-ARM/ADC_Oversampling_Init.uvprojx | 482 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../ADC_Oversampling_Init/STM32CubeIDE/.cproject | 187 + .../ADC_Oversampling_Init/STM32CubeIDE/.project | 90 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 159 + .../STM32CubeIDE/Application/User/sysmem.c | 58 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../ADC/ADC_Oversampling_Init/Src/main.c | 813 ++ .../ADC/ADC_Oversampling_Init/Src/stm32wbxx_it.c | 248 + .../ADC_Oversampling_Init/Src/system_stm32wbxx.c | 357 + .../ADC/ADC_Oversampling_Init/readme.txt | 110 + .../.extSettings | 7 + .../ADC_SingleConversion_TriggerSW_Init.ioc | 145 + .../EWARM/ADC_SingleConversion_TriggerSW_Init.ewd | 1419 ++ .../EWARM/ADC_SingleConversion_TriggerSW_Init.ewp | 1089 ++ .../EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../ADC_SingleConversion_TriggerSW_Init/Inc/main.h | 112 + .../Inc/stm32_assert.h | 53 + .../Inc/stm32wbxx_it.h | 74 + .../ADC_SingleConversion_TriggerSW_Init.uvoptx | 357 + .../ADC_SingleConversion_TriggerSW_Init.uvprojx | 482 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../STM32CubeIDE/.cproject | 187 + .../STM32CubeIDE/.project | 90 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 159 + .../STM32CubeIDE/Application/User/sysmem.c | 58 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../ADC_SingleConversion_TriggerSW_Init/Src/main.c | 741 + .../Src/stm32wbxx_it.c | 248 + .../Src/system_stm32wbxx.c | 357 + .../ADC_SingleConversion_TriggerSW_Init/readme.txt | 88 + .../.extSettings | 7 + .../COMP_CompareGpioVsVrefInt_Window_IT_Init.ioc | 136 + .../COMP_CompareGpioVsVrefInt_Window_IT_Init.ewd | 1419 ++ .../COMP_CompareGpioVsVrefInt_Window_IT_Init.ewp | 1089 ++ .../EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../EWARM/stm32wb35xx_sram_cm4.icf | 39 + .../Inc/main.h | 100 + .../Inc/stm32_assert.h | 53 + .../Inc/stm32wbxx_it.h | 71 + ...COMP_CompareGpioVsVrefInt_Window_IT_Init.uvoptx | 357 + ...OMP_CompareGpioVsVrefInt_Window_IT_Init.uvprojx | 481 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../STM32CubeIDE/.cproject | 187 + .../STM32CubeIDE/.project | 90 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Src/main.c | 446 + .../Src/stm32wbxx_it.c | 233 + .../Src/system_stm32wbxx.c | 357 + .../readme.txt | 96 + .../CRC/CRC_CalculateAndCheck/.extSettings | 7 + .../CRC_CalculateAndCheck.ioc | 121 + .../EWARM/CRC_CalculateAndCheck.ewd | 1419 ++ .../EWARM/CRC_CalculateAndCheck.ewp | 1083 ++ .../CRC/CRC_CalculateAndCheck/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../CRC/CRC_CalculateAndCheck/Inc/main.h | 110 + .../CRC/CRC_CalculateAndCheck/Inc/stm32_assert.h | 53 + .../CRC/CRC_CalculateAndCheck/Inc/stm32wbxx_it.h | 70 + .../MDK-ARM/CRC_CalculateAndCheck.uvoptx | 333 + .../MDK-ARM/CRC_CalculateAndCheck.uvprojx | 471 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../CRC_CalculateAndCheck/STM32CubeIDE/.cproject | 187 + .../CRC_CalculateAndCheck/STM32CubeIDE/.project | 80 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../CRC/CRC_CalculateAndCheck/Src/main.c | 371 + .../CRC/CRC_CalculateAndCheck/Src/stm32wbxx_it.c | 207 + .../CRC_CalculateAndCheck/Src/system_stm32wbxx.c | 357 + .../CRC/CRC_CalculateAndCheck/readme.txt | 77 + .../DMA_CopyFromFlashToMemory_Init/.extSettings | 7 + .../DMA_CopyFromFlashToMemory_Init.ioc | 132 + .../EWARM/DMA_CopyFromFlashToMemory_Init.ewd | 1419 ++ .../EWARM/DMA_CopyFromFlashToMemory_Init.ewp | 1086 ++ .../EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../DMA/DMA_CopyFromFlashToMemory_Init/Inc/main.h | 102 + .../Inc/stm32_assert.h | 53 + .../Inc/stm32wbxx_it.h | 71 + .../MDK-ARM/DMA_CopyFromFlashToMemory_Init.uvoptx | 345 + .../MDK-ARM/DMA_CopyFromFlashToMemory_Init.uvprojx | 476 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../STM32CubeIDE/.cproject | 187 + .../STM32CubeIDE/.project | 85 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../DMA/DMA_CopyFromFlashToMemory_Init/Src/main.c | 403 + .../Src/stm32wbxx_it.c | 229 + .../Src/system_stm32wbxx.c | 357 + .../DMA/DMA_CopyFromFlashToMemory_Init/readme.txt | 74 + .../EXTI/EXTI_ToggleLedOnIT_Init/.extSettings | 7 + .../EWARM/EXTI_ToggleLedOnIT_Init.ewd | 1419 ++ .../EWARM/EXTI_ToggleLedOnIT_Init.ewp | 1083 ++ .../EXTI/EXTI_ToggleLedOnIT_Init/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../EXTI_ToggleLedOnIT_Init.ioc | 120 + .../EXTI/EXTI_ToggleLedOnIT_Init/Inc/main.h | 101 + .../EXTI_ToggleLedOnIT_Init/Inc/stm32_assert.h | 53 + .../EXTI_ToggleLedOnIT_Init/Inc/stm32wbxx_it.h | 71 + .../MDK-ARM/EXTI_ToggleLedOnIT_Init.uvoptx | 333 + .../MDK-ARM/EXTI_ToggleLedOnIT_Init.uvprojx | 471 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../EXTI_ToggleLedOnIT_Init/STM32CubeIDE/.cproject | 187 + .../EXTI_ToggleLedOnIT_Init/STM32CubeIDE/.project | 80 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../EXTI/EXTI_ToggleLedOnIT_Init/Src/main.c | 257 + .../EXTI_ToggleLedOnIT_Init/Src/stm32wbxx_it.c | 229 + .../EXTI_ToggleLedOnIT_Init/Src/system_stm32wbxx.c | 357 + .../EXTI/EXTI_ToggleLedOnIT_Init/readme.txt | 70 + .../GPIO_InfiniteLedToggling_Init/.extSettings | 7 + .../EWARM/GPIO_InfiniteLedToggling_Init.ewd | 1419 ++ .../EWARM/GPIO_InfiniteLedToggling_Init.ewp | 1083 ++ .../EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../GPIO_InfiniteLedToggling_Init.ioc | 111 + .../GPIO/GPIO_InfiniteLedToggling_Init/Inc/main.h | 102 + .../Inc/stm32_assert.h | 53 + .../Inc/stm32wbxx_it.h | 70 + .../MDK-ARM/GPIO_InfiniteLedToggling_Init.uvoptx | 333 + .../MDK-ARM/GPIO_InfiniteLedToggling_Init.uvprojx | 471 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../STM32CubeIDE/.cproject | 187 + .../STM32CubeIDE/.project | 80 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../GPIO/GPIO_InfiniteLedToggling_Init/Src/main.c | 232 + .../Src/stm32wbxx_it.c | 207 + .../Src/system_stm32wbxx.c | 357 + .../GPIO/GPIO_InfiniteLedToggling_Init/readme.txt | 59 + .../HSEM/HSEM_DualProcess_IT/.extSettings | 7 + .../EWARM/HSEM_DualProcess_IT.ewd | 1419 ++ .../EWARM/HSEM_DualProcess_IT.ewp | 1083 ++ .../HSEM/HSEM_DualProcess_IT/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../EWARM/stm32wb35xx_sram_cm4.icf | 39 + .../HSEM_DualProcess_IT/HSEM_DualProcess_IT.ioc | 109 + .../HSEM/HSEM_DualProcess_IT/Inc/main.h | 116 + .../HSEM/HSEM_DualProcess_IT/Inc/stm32_assert.h | 53 + .../HSEM/HSEM_DualProcess_IT/Inc/stm32wbxx_it.h | 72 + .../MDK-ARM/HSEM_DualProcess_IT.uvoptx | 333 + .../MDK-ARM/HSEM_DualProcess_IT.uvprojx | 471 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../HSEM_DualProcess_IT/STM32CubeIDE/.cproject | 187 + .../HSEM/HSEM_DualProcess_IT/STM32CubeIDE/.project | 80 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../HSEM/HSEM_DualProcess_IT/Src/main.c | 302 + .../HSEM/HSEM_DualProcess_IT/Src/stm32wbxx_it.c | 221 + .../HSEM_DualProcess_IT/Src/system_stm32wbxx.c | 357 + .../HSEM/HSEM_DualProcess_IT/readme.txt | 81 + .../.extSettings | 7 + .../I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ewd | 1419 ++ .../I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ewp | 1089 ++ .../EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ioc | 137 + .../Inc/main.h | 130 + .../Inc/stm32_assert.h | 53 + .../Inc/stm32wbxx_it.h | 77 + .../I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.uvoptx | 377 + .../I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.uvprojx | 482 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../STM32CubeIDE/.cproject | 187 + .../STM32CubeIDE/.project | 90 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 159 + .../STM32CubeIDE/Application/User/sysmem.c | 58 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Src/main.c | 560 + .../Src/stm32wbxx_it.c | 367 + .../Src/system_stm32wbxx.c | 357 + .../readme.txt | 129 + .../.extSettings | 7 + .../I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ewd | 1419 ++ .../I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ewp | 1089 ++ .../EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ioc | 174 + .../Inc/main.h | 143 + .../Inc/stm32_assert.h | 53 + .../Inc/stm32wbxx_it.h | 80 + .../I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.uvoptx | 377 + ...I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.uvprojx | 482 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../STM32CubeIDE/.cproject | 187 + .../STM32CubeIDE/.project | 90 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Src/main.c | 808 ++ .../Src/stm32wbxx_it.c | 274 + .../Src/system_stm32wbxx.c | 357 + .../readme.txt | 131 + .../IWDG_RefreshUntilUserEvent_Init/.extSettings | 7 + .../EWARM/IWDG_RefreshUntilUserEvent_Init.ewd | 1419 ++ .../EWARM/IWDG_RefreshUntilUserEvent_Init.ewp | 1083 ++ .../EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../IWDG_RefreshUntilUserEvent_Init.ioc | 129 + .../IWDG_RefreshUntilUserEvent_Init/Inc/main.h | 111 + .../Inc/stm32_assert.h | 53 + .../Inc/stm32wbxx_it.h | 71 + .../MDK-ARM/IWDG_RefreshUntilUserEvent_Init.uvoptx | 333 + .../IWDG_RefreshUntilUserEvent_Init.uvprojx | 471 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../STM32CubeIDE/.cproject | 187 + .../STM32CubeIDE/.project | 80 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../IWDG_RefreshUntilUserEvent_Init/Src/main.c | 347 + .../Src/stm32wbxx_it.c | 230 + .../Src/system_stm32wbxx.c | 357 + .../IWDG_RefreshUntilUserEvent_Init/readme.txt | 66 + .../LPTIM/LPTIM_PulseCounter_Init/.extSettings | 8 + .../EWARM/LPTIM_PulseCounter_Init.ewd | 1419 ++ .../EWARM/LPTIM_PulseCounter_Init.ewp | 1089 ++ .../LPTIM_PulseCounter_Init/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../LPTIM/LPTIM_PulseCounter_Init/Inc/main.h | 100 + .../LPTIM_PulseCounter_Init/Inc/stm32_assert.h | 53 + .../LPTIM_PulseCounter_Init/Inc/stm32wbxx_it.h | 71 + .../LPTIM_PulseCounter_Init.ioc | 125 + .../MDK-ARM/LPTIM_PulseCounter_Init.uvoptx | 357 + .../MDK-ARM/LPTIM_PulseCounter_Init.uvprojx | 481 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../LPTIM_PulseCounter_Init/STM32CubeIDE/.cproject | 187 + .../LPTIM_PulseCounter_Init/STM32CubeIDE/.project | 90 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../LPTIM/LPTIM_PulseCounter_Init/Src/main.c | 350 + .../LPTIM_PulseCounter_Init/Src/stm32wbxx_it.c | 230 + .../LPTIM_PulseCounter_Init/Src/system_stm32wbxx.c | 357 + .../LPTIM/LPTIM_PulseCounter_Init/readme.txt | 75 + .../LPUART_WakeUpFromStop2_Init/.extSettings | 7 + .../EWARM/LPUART_WakeUpFromStop2_Init.ewd | 1419 ++ .../EWARM/LPUART_WakeUpFromStop2_Init.ewp | 1092 ++ .../LPUART_WakeUpFromStop2_Init/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../LPUART/LPUART_WakeUpFromStop2_Init/Inc/main.h | 116 + .../LPUART_WakeUpFromStop2_Init/Inc/stm32_assert.h | 53 + .../LPUART_WakeUpFromStop2_Init/Inc/stm32wbxx_it.h | 70 + .../LPUART_WakeUpFromStop2_Init.ioc | 141 + .../MDK-ARM/LPUART_WakeUpFromStop2_Init.uvoptx | 369 + .../MDK-ARM/LPUART_WakeUpFromStop2_Init.uvprojx | 487 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../STM32CubeIDE/.cproject | 187 + .../STM32CubeIDE/.project | 95 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../LPUART/LPUART_WakeUpFromStop2_Init/Src/main.c | 532 + .../LPUART_WakeUpFromStop2_Init/Src/stm32wbxx_it.c | 237 + .../Src/system_stm32wbxx.c | 357 + .../LPUART/LPUART_WakeUpFromStop2_Init/readme.txt | 78 + .../Examples_LL/PKA/PKA_ECDSA_Sign/.extSettings | 8 + .../PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewd | 1419 ++ .../PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewp | 1092 ++ .../PKA/PKA_ECDSA_Sign/EWARM/Project.eww | 7 + .../PKA_ECDSA_Sign/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../PKA_ECDSA_Sign/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../PKA_ECDSA_Sign/EWARM/stm32wb35xx_sram_cm4.icf | 39 + .../Examples_LL/PKA/PKA_ECDSA_Sign/Inc/SigGen.h | 51 + .../Examples_LL/PKA/PKA_ECDSA_Sign/Inc/main.h | 109 + .../PKA/PKA_ECDSA_Sign/Inc/prime256v1.h | 54 + .../PKA/PKA_ECDSA_Sign/Inc/stm32_assert.h | 53 + .../PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_it.h | 73 + .../PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvoptx | 369 + .../PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvprojx | 486 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../PKA/PKA_ECDSA_Sign/PKA_ECDSA_Sign.ioc | 112 + .../PKA/PKA_ECDSA_Sign/STM32CubeIDE/.cproject | 187 + .../PKA/PKA_ECDSA_Sign/STM32CubeIDE/.project | 95 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples_LL/PKA/PKA_ECDSA_Sign/Src/SigGen.c | 97 + .../Examples_LL/PKA/PKA_ECDSA_Sign/Src/SigGen.txt | 5878 ++++++++ .../Examples_LL/PKA/PKA_ECDSA_Sign/Src/main.c | 439 + .../PKA/PKA_ECDSA_Sign/Src/prime256v1.c | 96 + .../PKA/PKA_ECDSA_Sign/Src/stm32wbxx_it.c | 235 + .../PKA/PKA_ECDSA_Sign/Src/system_stm32wbxx.c | 357 + .../Examples_LL/PKA/PKA_ECDSA_Sign/readme.txt | 79 + .../PWR/PWR_EnterStandbyMode/.extSettings | 7 + .../EWARM/PWR_EnterStandbyMode.ewd | 1419 ++ .../EWARM/PWR_EnterStandbyMode.ewp | 1083 ++ .../PWR/PWR_EnterStandbyMode/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../PWR/PWR_EnterStandbyMode/Inc/main.h | 124 + .../PWR/PWR_EnterStandbyMode/Inc/stm32_assert.h | 53 + .../PWR/PWR_EnterStandbyMode/Inc/stm32wbxx_it.h | 70 + .../MDK-ARM/PWR_EnterStandbyMode.uvoptx | 333 + .../MDK-ARM/PWR_EnterStandbyMode.uvprojx | 471 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../PWR_EnterStandbyMode/PWR_EnterStandbyMode.ioc | 111 + .../PWR_EnterStandbyMode/STM32CubeIDE/.cproject | 187 + .../PWR/PWR_EnterStandbyMode/STM32CubeIDE/.project | 80 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../PWR/PWR_EnterStandbyMode/Src/main.c | 437 + .../PWR/PWR_EnterStandbyMode/Src/stm32wbxx_it.c | 222 + .../PWR_EnterStandbyMode/Src/system_stm32wbxx.c | 357 + .../PWR/PWR_EnterStandbyMode/readme.txt | 104 + .../Examples_LL/PWR/PWR_EnterStopMode/.extSettings | 7 + .../PWR_EnterStopMode/EWARM/PWR_EnterStopMode.ewd | 1419 ++ .../PWR_EnterStopMode/EWARM/PWR_EnterStopMode.ewp | 1083 ++ .../PWR/PWR_EnterStopMode/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples_LL/PWR/PWR_EnterStopMode/Inc/main.h | 99 + .../PWR/PWR_EnterStopMode/Inc/stm32_assert.h | 53 + .../PWR/PWR_EnterStopMode/Inc/stm32wbxx_it.h | 72 + .../MDK-ARM/PWR_EnterStopMode.uvoptx | 333 + .../MDK-ARM/PWR_EnterStopMode.uvprojx | 471 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../PWR/PWR_EnterStopMode/PWR_EnterStopMode.ioc | 111 + .../PWR/PWR_EnterStopMode/STM32CubeIDE/.cproject | 187 + .../PWR/PWR_EnterStopMode/STM32CubeIDE/.project | 80 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples_LL/PWR/PWR_EnterStopMode/Src/main.c | 341 + .../PWR/PWR_EnterStopMode/Src/stm32wbxx_it.c | 207 + .../PWR/PWR_EnterStopMode/Src/system_stm32wbxx.c | 357 + .../Examples_LL/PWR/PWR_EnterStopMode/readme.txt | 80 + .../PWR/PWR_OptimizedRunMode/.extSettings | 8 + .../EWARM/PWR_OptimizedRunMode.ewd | 1419 ++ .../EWARM/PWR_OptimizedRunMode.ewp | 1083 ++ .../PWR/PWR_OptimizedRunMode/EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../PWR/PWR_OptimizedRunMode/Inc/main.h | 133 + .../PWR/PWR_OptimizedRunMode/Inc/stm32_assert.h | 53 + .../PWR/PWR_OptimizedRunMode/Inc/stm32wbxx_it.h | 73 + .../MDK-ARM/PWR_OptimizedRunMode.uvoptx | 333 + .../MDK-ARM/PWR_OptimizedRunMode.uvprojx | 472 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../PWR_OptimizedRunMode/PWR_OptimizedRunMode.ioc | 115 + .../PWR_OptimizedRunMode/STM32CubeIDE/.cproject | 189 + .../PWR/PWR_OptimizedRunMode/STM32CubeIDE/.project | 80 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../PWR/PWR_OptimizedRunMode/Src/main.c | 542 + .../PWR/PWR_OptimizedRunMode/Src/stm32wbxx_it.c | 231 + .../PWR_OptimizedRunMode/Src/system_stm32wbxx.c | 357 + .../PWR/PWR_OptimizedRunMode/readme.txt | 105 + .../RCC/RCC_UseHSI_PLLasSystemClock/.extSettings | 7 + .../RCC_UseHSI_PLLasSystemClock/EWARM/Project.eww | 7 + .../EWARM/RCC_UseHSI_PLLasSystemClock.ewd | 1419 ++ .../EWARM/RCC_UseHSI_PLLasSystemClock.ewp | 1083 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../RCC/RCC_UseHSI_PLLasSystemClock/Inc/main.h | 134 + .../RCC_UseHSI_PLLasSystemClock/Inc/stm32_assert.h | 53 + .../RCC_UseHSI_PLLasSystemClock/Inc/stm32wbxx_it.h | 73 + .../MDK-ARM/RCC_UseHSI_PLLasSystemClock.uvoptx | 333 + .../MDK-ARM/RCC_UseHSI_PLLasSystemClock.uvprojx | 471 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../RCC_UseHSI_PLLasSystemClock.ioc | 120 + .../STM32CubeIDE/.cproject | 187 + .../STM32CubeIDE/.project | 80 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../RCC/RCC_UseHSI_PLLasSystemClock/Src/main.c | 567 + .../RCC_UseHSI_PLLasSystemClock/Src/stm32wbxx_it.c | 231 + .../Src/system_stm32wbxx.c | 357 + .../RCC/RCC_UseHSI_PLLasSystemClock/readme.txt | 70 + .../RNG/RNG_GenerateRandomNumbers_IT/.extSettings | 7 + .../RNG_GenerateRandomNumbers_IT/EWARM/Project.eww | 7 + .../EWARM/RNG_GenerateRandomNumbers_IT.ewd | 1419 ++ .../EWARM/RNG_GenerateRandomNumbers_IT.ewp | 1086 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../RNG/RNG_GenerateRandomNumbers_IT/Inc/main.h | 121 + .../Inc/stm32_assert.h | 53 + .../Inc/stm32wbxx_it.h | 72 + .../MDK-ARM/RNG_GenerateRandomNumbers_IT.uvoptx | 345 + .../MDK-ARM/RNG_GenerateRandomNumbers_IT.uvprojx | 477 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../RNG_GenerateRandomNumbers_IT.ioc | 129 + .../STM32CubeIDE/.cproject | 187 + .../STM32CubeIDE/.project | 85 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 159 + .../STM32CubeIDE/Application/User/sysmem.c | 58 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../RNG/RNG_GenerateRandomNumbers_IT/Src/main.c | 465 + .../Src/stm32wbxx_it.c | 257 + .../Src/system_stm32wbxx.c | 357 + .../RNG/RNG_GenerateRandomNumbers_IT/readme.txt | 71 + .../.extSettings | 7 + .../EWARM/Project.eww | 7 + .../EWARM/RTC_ExitStandbyWithWakeUpTimer_Init.ewd | 1419 ++ .../EWARM/RTC_ExitStandbyWithWakeUpTimer_Init.ewp | 1083 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../RTC_ExitStandbyWithWakeUpTimer_Init/Inc/main.h | 111 + .../Inc/stm32_assert.h | 53 + .../Inc/stm32wbxx_it.h | 73 + .../RTC_ExitStandbyWithWakeUpTimer_Init.uvoptx | 333 + .../RTC_ExitStandbyWithWakeUpTimer_Init.uvprojx | 472 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../RTC_ExitStandbyWithWakeUpTimer_Init.ioc | 120 + .../STM32CubeIDE/.cproject | 187 + .../STM32CubeIDE/.project | 80 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../RTC_ExitStandbyWithWakeUpTimer_Init/Src/main.c | 538 + .../Src/stm32wbxx_it.c | 227 + .../Src/system_stm32wbxx.c | 357 + .../RTC_ExitStandbyWithWakeUpTimer_Init/readme.txt | 83 + .../.extSettings | 9 + .../EWARM/Project.eww | 7 + .../SPI_TwoBoards_FullDuplex_DMA_Master_Init.ewd | 1419 ++ .../SPI_TwoBoards_FullDuplex_DMA_Master_Init.ewp | 1092 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Inc/main.h | 129 + .../Inc/stm32_assert.h | 53 + .../Inc/stm32wbxx_it.h | 72 + ...SPI_TwoBoards_FullDuplex_DMA_Master_Init.uvoptx | 369 + ...PI_TwoBoards_FullDuplex_DMA_Master_Init.uvprojx | 487 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../SPI_TwoBoards_FullDuplex_DMA_Master_Init.ioc | 183 + .../STM32CubeIDE/.cproject | 187 + .../STM32CubeIDE/.project | 90 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 159 + .../STM32CubeIDE/Application/User/sysmem.c | 58 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Src/main.c | 634 + .../Src/stm32wbxx_it.c | 263 + .../Src/system_stm32wbxx.c | 357 + .../readme.txt | 108 + .../.extSettings | 9 + .../EWARM/Project.eww | 7 + .../SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ewd | 1419 ++ .../SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ewp | 1092 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Inc/main.h | 115 + .../Inc/stm32_assert.h | 53 + .../Inc/stm32wbxx_it.h | 71 + .../SPI_TwoBoards_FullDuplex_DMA_Slave_Init.uvoptx | 396 + ...SPI_TwoBoards_FullDuplex_DMA_Slave_Init.uvprojx | 487 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ioc | 181 + .../STM32CubeIDE/.cproject | 188 + .../STM32CubeIDE/.project | 90 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 159 + .../STM32CubeIDE/Application/User/sysmem.c | 58 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Src/main.c | 572 + .../Src/stm32wbxx_it.c | 248 + .../Src/system_stm32wbxx.c | 357 + .../readme.txt | 108 + .../Examples_LL/TIM/TIM_TimeBase_Init/.extSettings | 7 + .../TIM/TIM_TimeBase_Init/EWARM/Project.eww | 7 + .../TIM_TimeBase_Init/EWARM/TIM_TimeBase_Init.ewd | 1419 ++ .../TIM_TimeBase_Init/EWARM/TIM_TimeBase_Init.ewp | 1089 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples_LL/TIM/TIM_TimeBase_Init/Inc/main.h | 102 + .../TIM/TIM_TimeBase_Init/Inc/stm32_assert.h | 53 + .../TIM/TIM_TimeBase_Init/Inc/stm32wbxx_it.h | 73 + .../MDK-ARM/TIM_TimeBase_Init.uvoptx | 357 + .../MDK-ARM/TIM_TimeBase_Init.uvprojx | 481 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../TIM/TIM_TimeBase_Init/STM32CubeIDE/.cproject | 187 + .../TIM/TIM_TimeBase_Init/STM32CubeIDE/.project | 90 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples_LL/TIM/TIM_TimeBase_Init/Src/main.c | 351 + .../TIM/TIM_TimeBase_Init/Src/stm32wbxx_it.c | 265 + .../TIM/TIM_TimeBase_Init/Src/system_stm32wbxx.c | 357 + .../TIM/TIM_TimeBase_Init/TIM_TimeBase_Init.ioc | 137 + .../Examples_LL/TIM/TIM_TimeBase_Init/readme.txt | 81 + .../USART_Communication_Rx_IT_Init/.extSettings | 7 + .../EWARM/Project.eww | 7 + .../EWARM/USART_Communication_Rx_IT_Init.ewd | 1419 ++ .../EWARM/USART_Communication_Rx_IT_Init.ewp | 1092 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../USART_Communication_Rx_IT_Init/Inc/main.h | 109 + .../Inc/stm32_assert.h | 53 + .../Inc/stm32wbxx_it.h | 72 + .../MDK-ARM/USART_Communication_Rx_IT_Init.uvoptx | 369 + .../MDK-ARM/USART_Communication_Rx_IT_Init.uvprojx | 486 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../STM32CubeIDE/.cproject | 187 + .../STM32CubeIDE/.project | 95 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../USART_Communication_Rx_IT_Init/Src/main.c | 439 + .../Src/stm32wbxx_it.c | 252 + .../Src/system_stm32wbxx.c | 357 + .../USART_Communication_Rx_IT_Init.ioc | 153 + .../USART_Communication_Rx_IT_Init/readme.txt | 78 + .../USART_Communication_Tx_IT_Init/.extSettings | 7 + .../EWARM/Project.eww | 7 + .../EWARM/USART_Communication_Tx_IT_Init.ewd | 1419 ++ .../EWARM/USART_Communication_Tx_IT_Init.ewp | 1092 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../USART_Communication_Tx_IT_Init/Inc/main.h | 113 + .../Inc/stm32_assert.h | 53 + .../Inc/stm32wbxx_it.h | 72 + .../MDK-ARM/USART_Communication_Tx_IT_Init.uvoptx | 369 + .../MDK-ARM/USART_Communication_Tx_IT_Init.uvprojx | 486 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../STM32CubeIDE/.cproject | 187 + .../STM32CubeIDE/.project | 95 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../USART_Communication_Tx_IT_Init/Src/main.c | 466 + .../Src/stm32wbxx_it.c | 264 + .../Src/system_stm32wbxx.c | 357 + .../USART_Communication_Tx_IT_Init.ioc | 158 + .../USART_Communication_Tx_IT_Init/readme.txt | 83 + .../UTILS/UTILS_ReadDeviceInfo/.extSettings | 7 + .../UTILS/UTILS_ReadDeviceInfo/EWARM/Project.eww | 7 + .../EWARM/UTILS_ReadDeviceInfo.ewd | 1419 ++ .../EWARM/UTILS_ReadDeviceInfo.ewp | 1083 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../UTILS/UTILS_ReadDeviceInfo/Inc/main.h | 97 + .../UTILS/UTILS_ReadDeviceInfo/Inc/stm32_assert.h | 53 + .../UTILS/UTILS_ReadDeviceInfo/Inc/stm32wbxx_it.h | 70 + .../MDK-ARM/UTILS_ReadDeviceInfo.uvoptx | 333 + .../MDK-ARM/UTILS_ReadDeviceInfo.uvprojx | 471 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../UTILS_ReadDeviceInfo/STM32CubeIDE/.cproject | 187 + .../UTILS_ReadDeviceInfo/STM32CubeIDE/.project | 80 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../UTILS/UTILS_ReadDeviceInfo/Src/main.c | 228 + .../UTILS/UTILS_ReadDeviceInfo/Src/stm32wbxx_it.c | 207 + .../UTILS_ReadDeviceInfo/Src/system_stm32wbxx.c | 357 + .../UTILS_ReadDeviceInfo/UTILS_ReadDeviceInfo.ioc | 106 + .../UTILS/UTILS_ReadDeviceInfo/readme.txt | 60 + .../WWDG_RefreshUntilUserEvent_Init/.extSettings | 7 + .../EWARM/Project.eww | 7 + .../EWARM/WWDG_RefreshUntilUserEvent_Init.ewd | 1419 ++ .../EWARM/WWDG_RefreshUntilUserEvent_Init.ewp | 1083 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../WWDG_RefreshUntilUserEvent_Init/Inc/main.h | 111 + .../Inc/stm32_assert.h | 53 + .../Inc/stm32wbxx_it.h | 71 + .../MDK-ARM/WWDG_RefreshUntilUserEvent_Init.uvoptx | 333 + .../WWDG_RefreshUntilUserEvent_Init.uvprojx | 471 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../STM32CubeIDE/.cproject | 187 + .../STM32CubeIDE/.project | 80 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../WWDG_RefreshUntilUserEvent_Init/Src/main.c | 346 + .../Src/stm32wbxx_it.c | 230 + .../Src/system_stm32wbxx.c | 357 + .../WWDG_RefreshUntilUserEvent_Init.ioc | 130 + .../WWDG_RefreshUntilUserEvent_Init/readme.txt | 62 + .../ADC_SingleConversion_TriggerSW_IT/.extSettings | 8 + .../ADC_SingleConversion_TriggerSW_IT.ioc | 116 + .../EWARM/ADC_SingleConversion_TriggerSW_IT.ewd | 1419 ++ .../EWARM/ADC_SingleConversion_TriggerSW_IT.ewp | 1128 ++ .../EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../ADC_SingleConversion_TriggerSW_IT/Inc/main.h | 107 + .../Inc/stm32wbxx_hal_conf.h | 359 + .../Inc/stm32wbxx_it.h | 79 + .../ADC_SingleConversion_TriggerSW_IT.uvoptx | 533 + .../ADC_SingleConversion_TriggerSW_IT.uvprojx | 556 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../STM32CubeIDE/.cproject | 170 + .../STM32CubeIDE/.project | 160 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../ADC_SingleConversion_TriggerSW_IT/Src/main.c | 550 + .../Src/stm32wbxx_hal_msp.c | 181 + .../Src/stm32wbxx_it.c | 272 + .../Src/system_stm32wbxx.c | 357 + .../ADC_SingleConversion_TriggerSW_IT/readme.txt | 86 + .../Examples_MIX/DMA/DMA_FLASHToRAM/.extSettings | 8 + .../DMA/DMA_FLASHToRAM/DMA_FLASHToRAM.ioc | 127 + .../DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewd | 1419 ++ .../DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewp | 1119 ++ .../DMA/DMA_FLASHToRAM/EWARM/Project.eww | 7 + .../DMA_FLASHToRAM/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../DMA_FLASHToRAM/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples_MIX/DMA/DMA_FLASHToRAM/Inc/main.h | 77 + .../DMA/DMA_FLASHToRAM/Inc/stm32wbxx_hal_conf.h | 359 + .../DMA/DMA_FLASHToRAM/Inc/stm32wbxx_it.h | 70 + .../DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvoptx | 497 + .../DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvprojx | 541 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../DMA/DMA_FLASHToRAM/STM32CubeIDE/.cproject | 169 + .../DMA/DMA_FLASHToRAM/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples_MIX/DMA/DMA_FLASHToRAM/Src/main.c | 332 + .../DMA/DMA_FLASHToRAM/Src/stm32wbxx_hal_msp.c | 81 + .../DMA/DMA_FLASHToRAM/Src/stm32wbxx_it.c | 237 + .../DMA/DMA_FLASHToRAM/Src/system_stm32wbxx.c | 357 + .../Examples_MIX/DMA/DMA_FLASHToRAM/readme.txt | 85 + .../I2C_OneBoard_ComSlave7_10bits_IT/.extSettings | 8 + .../EWARM/I2C_OneBoard_ComSlave7_10bits_IT.ewd | 1419 ++ .../EWARM/I2C_OneBoard_ComSlave7_10bits_IT.ewp | 1125 ++ .../EWARM/Project.eww | 7 + .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../I2C_OneBoard_ComSlave7_10bits_IT.ioc | 146 + .../I2C_OneBoard_ComSlave7_10bits_IT/Inc/main.h | 96 + .../Inc/stm32wbxx_hal_conf.h | 359 + .../Inc/stm32wbxx_it.h | 73 + .../I2C_OneBoard_ComSlave7_10bits_IT.uvoptx | 521 + .../I2C_OneBoard_ComSlave7_10bits_IT.uvprojx | 551 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../STM32CubeIDE/.cproject | 169 + .../STM32CubeIDE/.project | 155 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../I2C_OneBoard_ComSlave7_10bits_IT/Src/main.c | 500 + .../Src/stm32wbxx_hal_msp.c | 211 + .../Src/stm32wbxx_it.c | 252 + .../Src/system_stm32wbxx.c | 357 + .../I2C_OneBoard_ComSlave7_10bits_IT/readme.txt | 152 + .../Examples_MIX/PWR/PWR_STOP1/.extSettings | 8 + .../Examples_MIX/PWR/PWR_STOP1/EWARM/PWR_STOP1.ewd | 1419 ++ .../Examples_MIX/PWR/PWR_STOP1/EWARM/PWR_STOP1.ewp | 1119 ++ .../Examples_MIX/PWR/PWR_STOP1/EWARM/Project.eww | 7 + .../PWR/PWR_STOP1/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../PWR/PWR_STOP1/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples_MIX/PWR/PWR_STOP1/Inc/main.h | 85 + .../PWR/PWR_STOP1/Inc/stm32wbxx_hal_conf.h | 359 + .../Examples_MIX/PWR/PWR_STOP1/Inc/stm32wbxx_it.h | 72 + .../PWR/PWR_STOP1/MDK-ARM/PWR_STOP1.uvoptx | 497 + .../PWR/PWR_STOP1/MDK-ARM/PWR_STOP1.uvprojx | 542 + .../PWR_STOP1/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../PWR_STOP1/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../Examples_MIX/PWR/PWR_STOP1/PWR_STOP1.ioc | 106 + .../PWR/PWR_STOP1/STM32CubeIDE/.cproject | 169 + .../PWR/PWR_STOP1/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../PWR_STOP1/STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples_MIX/PWR/PWR_STOP1/Src/main.c | 301 + .../PWR/PWR_STOP1/Src/stm32wbxx_hal_msp.c | 81 + .../Examples_MIX/PWR/PWR_STOP1/Src/stm32wbxx_it.c | 216 + .../PWR/PWR_STOP1/Src/system_stm32wbxx.c | 357 + .../Examples_MIX/PWR/PWR_STOP1/readme.txt | 101 + .../.extSettings | 8 + .../EWARM/Project.eww | 7 + .../EWARM/SPI_HalfDuplex_ComPollingIT_Master.ewd | 1419 ++ .../EWARM/SPI_HalfDuplex_ComPollingIT_Master.ewp | 1125 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../SPI_HalfDuplex_ComPollingIT_Master/Inc/main.h | 73 + .../Inc/stm32wbxx_hal_conf.h | 359 + .../Inc/stm32wbxx_it.h | 70 + .../SPI_HalfDuplex_ComPollingIT_Master.uvoptx | 521 + .../SPI_HalfDuplex_ComPollingIT_Master.uvprojx | 551 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../SPI_HalfDuplex_ComPollingIT_Master.ioc | 135 + .../STM32CubeIDE/.cproject | 169 + .../STM32CubeIDE/.project | 155 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../SPI_HalfDuplex_ComPollingIT_Master/Src/main.c | 317 + .../Src/stm32wbxx_hal_msp.c | 149 + .../Src/stm32wbxx_it.c | 205 + .../Src/system_stm32wbxx.c | 357 + .../SPI_HalfDuplex_ComPollingIT_Master/readme.txt | 120 + .../SPI_HalfDuplex_ComPollingIT_Slave/.extSettings | 8 + .../EWARM/Project.eww | 7 + .../EWARM/SPI_HalfDuplex_ComPollingIT_Slave.ewd | 1419 ++ .../EWARM/SPI_HalfDuplex_ComPollingIT_Slave.ewp | 1125 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../SPI_HalfDuplex_ComPollingIT_Slave/Inc/main.h | 73 + .../Inc/stm32wbxx_hal_conf.h | 359 + .../Inc/stm32wbxx_it.h | 71 + .../SPI_HalfDuplex_ComPollingIT_Slave.uvoptx | 521 + .../SPI_HalfDuplex_ComPollingIT_Slave.uvprojx | 551 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../SPI_HalfDuplex_ComPollingIT_Slave.ioc | 134 + .../STM32CubeIDE/.cproject | 170 + .../STM32CubeIDE/.project | 155 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../SPI_HalfDuplex_ComPollingIT_Slave/Src/main.c | 365 + .../Src/stm32wbxx_hal_msp.c | 154 + .../Src/stm32wbxx_it.c | 219 + .../Src/system_stm32wbxx.c | 357 + .../SPI_HalfDuplex_ComPollingIT_Slave/readme.txt | 120 + .../Examples_MIX/TIM/TIM_PWMInput/.extSettings | 8 + .../TIM/TIM_PWMInput/EWARM/Project.eww | 7 + .../TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewd | 1419 ++ .../TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewp | 1119 ++ .../TIM_PWMInput/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../TIM_PWMInput/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Examples_MIX/TIM/TIM_PWMInput/Inc/main.h | 78 + .../TIM/TIM_PWMInput/Inc/stm32wbxx_hal_conf.h | 359 + .../TIM/TIM_PWMInput/Inc/stm32wbxx_it.h | 69 + .../TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvoptx | 497 + .../TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvprojx | 541 + .../TIM_PWMInput/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../TIM_PWMInput/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../TIM/TIM_PWMInput/STM32CubeIDE/.cproject | 169 + .../TIM/TIM_PWMInput/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../Examples_MIX/TIM/TIM_PWMInput/Src/main.c | 462 + .../TIM/TIM_PWMInput/Src/stm32wbxx_hal_msp.c | 223 + .../TIM/TIM_PWMInput/Src/stm32wbxx_it.c | 215 + .../TIM/TIM_PWMInput/Src/system_stm32wbxx.c | 357 + .../Examples_MIX/TIM/TIM_PWMInput/TIM_PWMInput.ioc | 173 + .../Examples_MIX/TIM/TIM_PWMInput/readme.txt | 92 + .../UART/UART_HyperTerminal_IT/.extSettings | 8 + .../UART/UART_HyperTerminal_IT/EWARM/Project.eww | 7 + .../EWARM/UART_HyperTerminal_IT.ewd | 1419 ++ .../EWARM/UART_HyperTerminal_IT.ewp | 1125 ++ .../EWARM/startup_stm32wb35xx_cm4.s | 507 + .../EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../UART/UART_HyperTerminal_IT/Inc/main.h | 88 + .../UART_HyperTerminal_IT/Inc/stm32wbxx_hal_conf.h | 359 + .../UART/UART_HyperTerminal_IT/Inc/stm32wbxx_it.h | 70 + .../MDK-ARM/UART_HyperTerminal_IT.uvoptx | 521 + .../MDK-ARM/UART_HyperTerminal_IT.uvprojx | 551 + .../MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../UART_HyperTerminal_IT/STM32CubeIDE/.cproject | 169 + .../UART_HyperTerminal_IT/STM32CubeIDE/.project | 155 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + .../UART/UART_HyperTerminal_IT/Src/main.c | 424 + .../UART_HyperTerminal_IT/Src/stm32wbxx_hal_msp.c | 151 + .../UART/UART_HyperTerminal_IT/Src/stm32wbxx_it.c | 253 + .../UART_HyperTerminal_IT/Src/system_stm32wbxx.c | 357 + .../UART_HyperTerminal_IT.ioc | 141 + .../UART/UART_HyperTerminal_IT/readme.txt | 141 + Projects/NUCLEO-WB35CE/Release_Notes.html | 62 + Projects/NUCLEO-WB35CE/Templates/.extSettings | 8 + Projects/NUCLEO-WB35CE/Templates/EWARM/Project.eww | 7 + .../NUCLEO-WB35CE/Templates/EWARM/Templates.ewd | 1419 ++ .../NUCLEO-WB35CE/Templates/EWARM/Templates.ewp | 1119 ++ .../Templates/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../Templates/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Templates/EWARM/stm32wb35xx_sram_cm4.icf | 39 + Projects/NUCLEO-WB35CE/Templates/Inc/main.h | 71 + .../Templates/Inc/stm32wbxx_hal_conf.h | 359 + .../NUCLEO-WB35CE/Templates/Inc/stm32wbxx_it.h | 70 + .../Templates/MDK-ARM/Templates.uvoptx | 497 + .../Templates/MDK-ARM/Templates.uvprojx | 541 + .../Templates/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../Templates/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../NUCLEO-WB35CE/Templates/STM32CubeIDE/.cproject | 169 + .../NUCLEO-WB35CE/Templates/STM32CubeIDE/.project | 145 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../Templates/STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + Projects/NUCLEO-WB35CE/Templates/Src/main.c | 206 + .../Templates/Src/stm32wbxx_hal_msp.c | 82 + .../NUCLEO-WB35CE/Templates/Src/stm32wbxx_it.c | 206 + .../NUCLEO-WB35CE/Templates/Src/system_stm32wbxx.c | 357 + Projects/NUCLEO-WB35CE/Templates/Templates.ioc | 104 + Projects/NUCLEO-WB35CE/Templates/readme.txt | 65 + Projects/NUCLEO-WB35CE/Templates_LL/.extSettings | 7 + .../NUCLEO-WB35CE/Templates_LL/EWARM/Project.eww | 7 + .../Templates_LL/EWARM/Templates_LL.ewd | 1419 ++ .../Templates_LL/EWARM/Templates_LL.ewp | 1083 ++ .../Templates_LL/EWARM/startup_stm32wb35xx_cm4.s | 507 + .../Templates_LL/EWARM/stm32wb35xx_flash_cm4.icf | 40 + .../Templates_LL/EWARM/stm32wb35xx_sram_cm4.icf | 39 + Projects/NUCLEO-WB35CE/Templates_LL/Inc/main.h | 96 + .../NUCLEO-WB35CE/Templates_LL/Inc/stm32_assert.h | 53 + .../NUCLEO-WB35CE/Templates_LL/Inc/stm32wbxx_it.h | 70 + .../Templates_LL/MDK-ARM/Templates_LL.uvoptx | 333 + .../Templates_LL/MDK-ARM/Templates_LL.uvprojx | 471 + .../Templates_LL/MDK-ARM/startup_stm32wb35xx_cm4.s | 364 + .../Templates_LL/MDK-ARM/stm32wb35xx_flash_cm4.sct | 21 + .../Templates_LL/STM32CubeIDE/.cproject | 187 + .../Templates_LL/STM32CubeIDE/.project | 80 + .../Application/Startup/startup_stm32wb35ceux.s | 439 + .../STM32CubeIDE/Application/User/syscalls.c | 184 + .../STM32CubeIDE/Application/User/sysmem.c | 83 + .../STM32CubeIDE/STM32WB35CEUX_FLASH.ld | 187 + Projects/NUCLEO-WB35CE/Templates_LL/Src/main.c | 193 + .../NUCLEO-WB35CE/Templates_LL/Src/stm32wbxx_it.c | 206 + .../Templates_LL/Src/system_stm32wbxx.c | 357 + .../NUCLEO-WB35CE/Templates_LL/Templates_LL.ioc | 102 + Projects/NUCLEO-WB35CE/Templates_LL/readme.txt | 87 + .../Applications/BLE/BLE_Beacon/BLE_Beacon.ioc | 16 +- .../BLE/BLE_Beacon/Core/Inc/app_common.h | 7 +- .../BLE/BLE_Beacon/Core/Inc/app_conf.h | 50 +- .../BLE/BLE_Beacon/Core/Inc/app_debug.h | 69 + .../Applications/BLE/BLE_Beacon/Core/Inc/hw_conf.h | 28 + .../Applications/BLE/BLE_Beacon/Core/Inc/main.h | 1 + .../BLE/BLE_Beacon/Core/Inc/stm32wbxx_hal_conf.h | 6 + .../BLE/BLE_Beacon/Core/Src/app_debug.c | 399 + .../BLE/BLE_Beacon/Core/Src/app_entry.c | 76 +- .../BLE/BLE_Beacon/Core/Src/hw_timerserver.c | 2 +- .../Applications/BLE/BLE_Beacon/Core/Src/hw_uart.c | 2 +- .../Applications/BLE/BLE_Beacon/Core/Src/main.c | 6 +- .../BLE/BLE_Beacon/Core/Src/stm32_lpm_if.c | 22 + .../BLE/BLE_Beacon/Core/Src/stm32wbxx_hal_msp.c | 2 + .../BLE/BLE_Beacon/EWARM/ble_beacon.ewp | 3 + .../BLE/BLE_Beacon/MDK-ARM/BLE_Beacon.uvprojx | 5 + .../BLE/BLE_Beacon/STM32_WPAN/App/ble_conf.h | 2 +- .../BLE/BLE_Beacon/STM32_WPAN/App/ble_dbg_conf.h | 2 +- .../BLE_Beacon/STM32_WPAN/App/eddystone_beacon.h | 2 +- .../STM32_WPAN/App/eddystone_tlm_service.c | 2 +- .../STM32_WPAN/App/eddystone_tlm_service.h | 2 +- .../STM32_WPAN/App/eddystone_uid_service.c | 2 +- .../STM32_WPAN/App/eddystone_uid_service.h | 2 +- .../STM32_WPAN/App/eddystone_url_service.c | 2 +- .../STM32_WPAN/App/eddystone_url_service.h | 2 +- .../BLE/BLE_Beacon/STM32_WPAN/Target/hw_ipcc.c | 2 +- .../BLE/BLE_Beacon/SW4STM32/BLE_Beacon/.project | 5 + .../SW4STM32/BLE_Beacon/stm32wb55xx_flash_cm4.ld | 4 +- .../BLE_Beacon/SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../BLE/BLE_BloodPressure/BLE_BloodPressure.ioc | 12 +- .../BLE/BLE_BloodPressure/Core/Inc/app_common.h | 7 +- .../BLE/BLE_BloodPressure/Core/Inc/app_conf.h | 48 +- .../BLE/BLE_BloodPressure/Core/Inc/app_debug.h | 69 + .../BLE/BLE_BloodPressure/Core/Inc/hw_conf.h | 28 + .../BLE/BLE_BloodPressure/Core/Inc/main.h | 1 + .../Core/Inc/stm32wbxx_hal_conf.h | 6 + .../BLE/BLE_BloodPressure/Core/Src/app_debug.c | 399 + .../BLE/BLE_BloodPressure/Core/Src/app_entry.c | 76 +- .../BLE_BloodPressure/Core/Src/hw_timerserver.c | 2 +- .../BLE/BLE_BloodPressure/Core/Src/hw_uart.c | 2 +- .../BLE/BLE_BloodPressure/Core/Src/main.c | 6 +- .../BLE/BLE_BloodPressure/Core/Src/stm32_lpm_if.c | 22 + .../BLE_BloodPressure/Core/Src/stm32wbxx_hal_msp.c | 2 + .../BLE_BloodPressure/EWARM/BLE_BloodPressure.ewp | 3 + .../MDK-ARM/BLE_BloodPressure.uvprojx | 5 + .../BLE/BLE_BloodPressure/STM32_WPAN/App/app_ble.c | 21 +- .../BLE_BloodPressure/STM32_WPAN/App/ble_conf.h | 2 +- .../STM32_WPAN/App/ble_dbg_conf.h | 2 +- .../BLE_BloodPressure/STM32_WPAN/Target/hw_ipcc.c | 2 +- .../SW4STM32/BLE_BloodPressure/.project | 5 + .../BLE_BloodPressure/stm32wb55xx_flash_cm4.ld | 4 +- .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../BLE/BLE_CableReplacement/Core/Inc/app_debug.h | 45 + .../BLE/BLE_CableReplacement/Core/Inc/hw_conf.h | 34 +- .../BLE/BLE_CableReplacement/Core/Src/app_debug.c | 349 + .../BLE/BLE_CableReplacement/Core/Src/app_entry.c | 67 +- .../BLE_CableReplacement/Core/Src/stm32_lpm_if.c | 22 + .../EWARM/BLE_CableReplacement.ewp | 3 + .../EWARM/startup_stm32wb55xx_cm4.s | 51 +- .../MDK-ARM/BLE_CableReplacement.uvprojx | 5 + .../SW4STM32/BLE_CableReplacement/.project | 5 + .../BLE_CableReplacement/stm32wb55xx_flash_cm4.ld | 4 +- .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../BLE/BLE_DataThroughput/Core/Inc/app_conf.h | 28 +- .../BLE/BLE_DataThroughput/Core/Inc/app_debug.h | 45 + .../BLE/BLE_DataThroughput/Core/Inc/hw_conf.h | 34 +- .../BLE/BLE_DataThroughput/Core/Inc/main.h | 2 +- .../BLE/BLE_DataThroughput/Core/Src/app_debug.c | 363 + .../BLE/BLE_DataThroughput/Core/Src/app_entry.c | 153 +- .../BLE/BLE_DataThroughput/Core/Src/hw_uart.c | 496 +- .../BLE/BLE_DataThroughput/Core/Src/main.c | 618 +- .../BLE/BLE_DataThroughput/Core/Src/stm32_lpm_if.c | 22 + .../Core/Src/stm32wbxx_hal_msp.c | 348 + .../BLE/BLE_DataThroughput/Core/Src/stm32wbxx_it.c | 271 +- .../BLE_DataThroughput/Core/Src/system_stm32wbxx.c | 8 + .../EWARM/BLE_DataThroughput.ewp | 28 +- .../EWARM/startup_stm32wb55xx_cm4.s | 51 +- .../MDK-ARM/BLE_DataThroughput.uvprojx | 10 + .../BLE_DataThroughput/STM32_WPAN/App/app_ble.c | 101 +- .../BLE_DataThroughput/STM32_WPAN/App/app_ble.h | 2 +- .../STM32_WPAN/App/dt_client_app.c | 18 +- .../STM32_WPAN/App/dt_server_app.c | 69 +- .../STM32_WPAN/App/dt_server_app.h | 1 + .../BLE/BLE_DataThroughput/STM32_WPAN/App/dts.c | 113 +- .../BLE/BLE_DataThroughput/STM32_WPAN/App/dts.h | 9 + .../SW4STM32/BLE_DataThroughput/.project | 10 + .../BLE_DataThroughput/stm32wb55xx_flash_cm4.ld | 4 +- .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../Applications/BLE/BLE_DataThroughput/readme.txt | 11 +- .../BLE_HealthThermometer.ioc | 12 +- .../BLE_HealthThermometer/Core/Inc/app_common.h | 7 +- .../BLE/BLE_HealthThermometer/Core/Inc/app_conf.h | 50 +- .../BLE/BLE_HealthThermometer/Core/Inc/app_debug.h | 69 + .../BLE/BLE_HealthThermometer/Core/Inc/hw_conf.h | 28 + .../BLE/BLE_HealthThermometer/Core/Inc/main.h | 1 + .../Core/Inc/stm32wbxx_hal_conf.h | 6 + .../BLE/BLE_HealthThermometer/Core/Src/app_debug.c | 399 + .../BLE/BLE_HealthThermometer/Core/Src/app_entry.c | 76 +- .../Core/Src/hw_timerserver.c | 2 +- .../BLE/BLE_HealthThermometer/Core/Src/hw_uart.c | 2 +- .../BLE/BLE_HealthThermometer/Core/Src/main.c | 6 +- .../BLE_HealthThermometer/Core/Src/stm32_lpm_if.c | 22 + .../Core/Src/stm32wbxx_hal_msp.c | 2 + .../EWARM/BLE_HealthThermometer.ewp | 3 + .../MDK-ARM/BLE_HealthThermometer.uvprojx | 5 + .../BLE_HealthThermometer/STM32_WPAN/App/app_ble.c | 21 +- .../STM32_WPAN/App/ble_conf.h | 2 +- .../STM32_WPAN/App/ble_dbg_conf.h | 2 +- .../STM32_WPAN/Target/hw_ipcc.c | 2 +- .../SW4STM32/BLE_HealthThermometer/.project | 5 + .../BLE_HealthThermometer/stm32wb55xx_flash_cm4.ld | 4 +- .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../BLE/BLE_HeartRate/BLE_HeartRate.ioc | 15 +- .../Binary/BLE_HeartRate_reference.hex | 2136 +-- .../BLE/BLE_HeartRate/Core/Inc/app_common.h | 7 +- .../BLE/BLE_HeartRate/Core/Inc/app_conf.h | 50 +- .../BLE/BLE_HeartRate/Core/Inc/app_debug.h | 69 + .../BLE/BLE_HeartRate/Core/Inc/hw_conf.h | 28 + .../Applications/BLE/BLE_HeartRate/Core/Inc/main.h | 1 + .../BLE_HeartRate/Core/Inc/stm32wbxx_hal_conf.h | 6 + .../BLE/BLE_HeartRate/Core/Src/app_debug.c | 399 + .../BLE/BLE_HeartRate/Core/Src/app_entry.c | 76 +- .../BLE/BLE_HeartRate/Core/Src/hw_timerserver.c | 2 +- .../BLE/BLE_HeartRate/Core/Src/hw_uart.c | 2 +- .../Applications/BLE/BLE_HeartRate/Core/Src/main.c | 6 +- .../BLE/BLE_HeartRate/Core/Src/stm32_lpm_if.c | 22 + .../BLE/BLE_HeartRate/Core/Src/stm32wbxx_hal_msp.c | 2 + .../BLE/BLE_HeartRate/EWARM/BLE_HeartRate.ewp | 3 + .../BLE_HeartRate/EWARM/stm32wb55xx_flash_cm4.icf | 2 +- .../BLE_HeartRate/MDK-ARM/BLE_HeartRate.uvprojx | 5 + .../BLE/BLE_HeartRate/STM32_WPAN/App/app_ble.c | 27 +- .../BLE/BLE_HeartRate/STM32_WPAN/App/ble_conf.h | 2 +- .../BLE_HeartRate/STM32_WPAN/App/ble_dbg_conf.h | 2 +- .../BLE/BLE_HeartRate/STM32_WPAN/Target/hw_ipcc.c | 2 +- .../BLE_HeartRate/SW4STM32/BLE_HeartRate/.project | 5 + .../BLE_HeartRate/stm32wb55xx_flash_cm4.ld | 4 +- .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../BLE_HeartRateFreeRTOS.ioc | 15 +- .../Core/Inc/FreeRTOSConfig.h | 38 +- .../BLE_HeartRateFreeRTOS/Core/Inc/app_common.h | 7 +- .../BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_conf.h | 58 +- .../BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_debug.h | 69 + .../BLE/BLE_HeartRateFreeRTOS/Core/Inc/hw_conf.h | 28 + .../BLE/BLE_HeartRateFreeRTOS/Core/Inc/main.h | 1 + .../Core/Inc/stm32wbxx_hal_conf.h | 6 + .../BLE/BLE_HeartRateFreeRTOS/Core/Src/app_debug.c | 399 + .../BLE/BLE_HeartRateFreeRTOS/Core/Src/app_entry.c | 78 +- .../BLE_HeartRateFreeRTOS/Core/Src/freertos_port.c | 51 +- .../Core/Src/hw_timerserver.c | 2 +- .../BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_uart.c | 2 +- .../BLE/BLE_HeartRateFreeRTOS/Core/Src/main.c | 23 +- .../Core/Src/stm32wbxx_hal_msp.c | 2 + .../EWARM/BLE_HeartRateFreeRTOS.ewp | 3 + .../EWARM/startup_stm32wb55xx_cm4.s | 51 +- .../MDK-ARM/BLE_HeartRateFreeRTOS.uvprojx | 5 + .../BLE_HeartRateFreeRTOS/STM32_WPAN/App/app_ble.c | 31 +- .../STM32_WPAN/App/ble_conf.h | 2 +- .../STM32_WPAN/App/ble_dbg_conf.h | 2 +- .../BLE_HeartRateFreeRTOS/STM32_WPAN/App/hrs_app.c | 2 +- .../STM32_WPAN/Target/hw_ipcc.c | 2 +- .../SW4STM32/BLE_HeartRateFreeRTOS/.project | 5 + .../BLE_HeartRateFreeRTOS/stm32wb55xx_flash_cm4.ld | 4 +- .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../Binary/BLE_HeartRate_ota_reference.bin | Bin 16608 -> 17288 bytes .../BLE/BLE_HeartRate_ota/Core/Inc/app_debug.h | 45 + .../BLE/BLE_HeartRate_ota/Core/Inc/hw_conf.h | 34 +- .../BLE/BLE_HeartRate_ota/Core/Src/app_debug.c | 349 + .../BLE/BLE_HeartRate_ota/Core/Src/app_entry.c | 77 +- .../BLE/BLE_HeartRate_ota/Core/Src/stm32_lpm_if.c | 22 + .../BLE_HeartRate_ota/EWARM/BLE_HeartRate_ota.ewp | 3 + .../MDK-ARM/BLE_HeartRate_ota.uvprojx | 5 + .../MDK-ARM/startup_stm32wb55xx_cm4.s | 16 +- .../SW4STM32/BLE_HeartRate_ota/.project | 5 + .../BLE_HeartRate_ota/stm32wb55xx_flash_cm4.ld | 4 +- .../Applications/BLE/BLE_HeartRate_ota/readme.txt | 2 + .../Applications/BLE/BLE_Hid/Core/Inc/app_debug.h | 45 + .../Applications/BLE/BLE_Hid/Core/Inc/hw_conf.h | 34 +- .../Applications/BLE/BLE_Hid/Core/Src/app_debug.c | 349 + .../Applications/BLE/BLE_Hid/Core/Src/app_entry.c | 67 +- .../BLE/BLE_Hid/Core/Src/stm32_lpm_if.c | 22 + .../Applications/BLE/BLE_Hid/EWARM/BLE_Hid.ewp | 3 + .../BLE/BLE_Hid/EWARM/startup_stm32wb55xx_cm4.s | 51 +- .../BLE/BLE_Hid/MDK-ARM/BLE_Hid.uvprojx | 5 + .../BLE/BLE_Hid/SW4STM32/BLE_Hid/.project | 5 + .../SW4STM32/BLE_Hid/stm32wb55xx_flash_cm4.ld | 4 +- .../BLE/BLE_Hid/SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../BLE/BLE_MeshLightingDemo/Core/Inc/app_conf.h | 21 +- .../BLE/BLE_MeshLightingDemo/Core/Inc/hw_conf.h | 34 +- .../BLE/BLE_MeshLightingDemo/Core/Inc/hw_flash.h | 87 + .../BLE/BLE_MeshLightingDemo/Core/Inc/lp_timer.h | 60 + .../BLE/BLE_MeshLightingDemo/Core/Src/app_debug.c | 109 +- .../BLE/BLE_MeshLightingDemo/Core/Src/app_entry.c | 105 +- .../BLE/BLE_MeshLightingDemo/Core/Src/hw_flash.c | 152 + .../BLE/BLE_MeshLightingDemo/Core/Src/hw_uart.c | 20 +- .../BLE/BLE_MeshLightingDemo/Core/Src/lp_timer.c | 134 + .../BLE/BLE_MeshLightingDemo/Core/Src/main.c | 157 +- .../BLE_MeshLightingDemo/Core/Src/stm32_lpm_if.c | 22 + .../EWARM/BLE_MeshLightingDemo.ewd | 11 +- .../EWARM/BLE_MeshLightingDemo.ewp | 56 +- .../EWARM/startup_stm32wb55xx_cm4.s | 51 +- .../EWARM/stm32wb55xx_flash_cm4.icf | 2 +- .../MDK-ARM/BLE_MeshLightingDemo.uvoptx | 281 +- .../MDK-ARM/BLE_MeshLightingDemo.uvprojx | 369 +- .../STM32_WPAN/app/PWM_config.h | 75 - .../STM32_WPAN/app/PWM_handlers.c | 7 +- .../BLE_MeshLightingDemo/STM32_WPAN/app/app_ble.c | 27 +- .../STM32_WPAN/app/appli_config_client.c | 1773 +++ .../STM32_WPAN/app/appli_config_client.h | 75 + .../STM32_WPAN/app/appli_generic.c | 94 +- .../STM32_WPAN/app/appli_generic.h | 13 +- .../STM32_WPAN/app/appli_generic_client.c | 101 + .../STM32_WPAN/app/appli_generic_client.h | 45 + .../STM32_WPAN/app/appli_light.c | 335 +- .../STM32_WPAN/app/appli_light.h | 37 +- .../STM32_WPAN/app/appli_light_client.c | 102 + .../STM32_WPAN/app/appli_light_client.h | 62 + .../STM32_WPAN/app/appli_light_lc.c | 42 +- .../STM32_WPAN/app/appli_light_lc.h | 11 +- .../STM32_WPAN/app/appli_mesh.c | 736 +- .../STM32_WPAN/app/appli_mesh.h | 17 +- .../STM32_WPAN/app/appli_nvm.c | 449 +- .../STM32_WPAN/app/appli_nvm.h | 23 +- .../STM32_WPAN/app/appli_sensor.c | 293 +- .../STM32_WPAN/app/appli_sensor.h | 1 - .../STM32_WPAN/app/appli_vendor.c | 127 +- .../STM32_WPAN/app/appli_vendor.h | 1 + .../BLE_MeshLightingDemo/STM32_WPAN/app/mesh_cfg.h | 31 +- .../STM32_WPAN/app/mesh_cfg_usr.h | 353 +- .../STM32_WPAN/app/models_if.c | 203 +- .../STM32_WPAN/app/models_if.h | 5 + .../BLE_MeshLightingDemo/STM32_WPAN/app/pal_nvm.c | 102 +- .../BLE_MeshLightingDemo/STM32_WPAN/app/user_if.h | 2 +- .../SW4STM32/BLE_MeshLightingDemo/.cproject | 183 - .../SW4STM32/BLE_MeshLightingDemo/.project | 383 - .../BLE_MeshLightingDemo/stm32wb55xx_flash_cm4.ld | 187 - .../SW4STM32/Lighting_Node/.cproject | 181 + .../SW4STM32/Lighting_Node/.project | 423 + .../Lighting_Node/stm32wb55xx_flash_cm4.ld | 187 + .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../BLE/BLE_MeshLightingDemo/readme.txt | 119 +- .../BLE/BLE_MultiAppAt/Core/Inc/app_debug.h | 45 + .../BLE/BLE_MultiAppAt/Core/Inc/hw_conf.h | 34 +- .../BLE/BLE_MultiAppAt/Core/Src/app_debug.c | 349 + .../BLE/BLE_MultiAppAt/Core/Src/app_entry.c | 49 +- .../BLE/BLE_MultiAppAt/Core/Src/stm32_lpm_if.c | 22 + .../BLE/BLE_MultiAppAt/EWARM/BLE_MultiAppAt.ewp | 3 + .../MDK-ARM/ble_multi_app_at.uvprojx | 5 + .../SW4STM32/BLE_MultiAppAt/.project | 5 + .../BLE_MultiAppAt/stm32wb55xx_flash_cm4.ld | 6 +- .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../Applications/BLE/BLE_MultiAppAt/readme.txt | 3 +- .../BLE/BLE_Ota/Binary/BLE_Ota_reference.hex | 843 +- .../Applications/BLE/BLE_Ota/Core/Inc/hw_conf.h | 34 +- .../Applications/BLE/BLE_Ota/Core/Src/app_debug.c | 36 +- .../BLE/BLE_Ota/Core/Src/stm32_lpm_if.c | 22 + .../BLE/BLE_Ota/EWARM/startup_stm32wb55xx_cm4.s | 51 +- .../BLE/BLE_Ota/MDK-ARM/BLE_Ota.uvprojx | 5 + .../BLE/BLE_Ota/SW4STM32/BLE_Ota/.project | 5 + .../SW4STM32/BLE_Ota/stm32wb55xx_flash_cm4.ld | 4 +- .../BLE/BLE_Ota/SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../EWARM/stm32wb55xx_flash_cm4.icf | 2 +- .../BLE/BLE_Peripheral_Lite/Inc/hw_conf.h | 34 +- .../MDK-ARM/stm32wb55xx_flash_cm4.sct | 7 +- .../BLE_Peripheral_Lite/stm32wb55xx_flash_cm4.ld | 4 +- .../BLE/BLE_Peripheral_Lite/Src/app_debug.c | 56 +- .../BLE/BLE_Peripheral_Lite/Src/main.c | 66 - .../BLE/BLE_Proximity/Core/Inc/app_debug.h | 45 + .../BLE/BLE_Proximity/Core/Inc/hw_conf.h | 34 +- .../BLE/BLE_Proximity/Core/Src/app_debug.c | 349 + .../BLE/BLE_Proximity/Core/Src/app_entry.c | 66 +- .../BLE/BLE_Proximity/Core/Src/stm32_lpm_if.c | 22 + .../BLE/BLE_Proximity/EWARM/BLE_Proximity.ewp | 3 + .../BLE_Proximity/EWARM/startup_stm32wb55xx_cm4.s | 51 +- .../BLE_Proximity/MDK-ARM/BLE_Proximity.uvprojx | 5 + .../BLE_Proximity/SW4STM32/BLE_Proximity/.project | 5 + .../BLE_Proximity/stm32wb55xx_flash_cm4.ld | 4 +- .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../BLE_TransparentMode/BLE_TransparentMode.ioc | 14 +- .../Binary/BLE_TransparentMode_reference.hex | 1833 +-- .../BLE/BLE_TransparentMode/Core/Inc/app_common.h | 7 +- .../BLE/BLE_TransparentMode/Core/Inc/app_conf.h | 48 +- .../BLE/BLE_TransparentMode/Core/Inc/app_debug.h | 69 + .../BLE/BLE_TransparentMode/Core/Inc/hw_conf.h | 28 + .../BLE/BLE_TransparentMode/Core/Inc/main.h | 1 + .../Core/Inc/stm32wbxx_hal_conf.h | 6 + .../BLE/BLE_TransparentMode/Core/Src/app_debug.c | 399 + .../BLE/BLE_TransparentMode/Core/Src/app_entry.c | 76 +- .../BLE_TransparentMode/Core/Src/hw_timerserver.c | 2 +- .../BLE/BLE_TransparentMode/Core/Src/hw_uart.c | 2 +- .../BLE/BLE_TransparentMode/Core/Src/main.c | 6 +- .../BLE_TransparentMode/Core/Src/stm32_lpm_if.c | 22 + .../Core/Src/stm32wbxx_hal_msp.c | 2 + .../EWARM/BLE_TransparentMode.ewp | 3 + .../MDK-ARM/BLE_TransparentMode.uvprojx | 5 + .../BLE_TransparentMode/STM32_WPAN/App/ble_conf.h | 2 +- .../STM32_WPAN/App/ble_dbg_conf.h | 2 +- .../BLE/BLE_TransparentMode/STM32_WPAN/App/tm.c | 1 + .../STM32_WPAN/Target/hw_ipcc.c | 2 +- .../SW4STM32/BLE_TransparentMode/.cproject | 2 +- .../SW4STM32/BLE_TransparentMode/.project | 5 + .../BLE_TransparentMode/stm32wb55xx_flash_cm4.ld | 4 +- .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../BLE/BLE_p2pClient/BLE_p2pClient.ioc | 16 +- .../Binary/BLE_p2pClient_reference.hex | 2700 ++-- .../BLE/BLE_p2pClient/Core/Inc/app_common.h | 7 +- .../BLE/BLE_p2pClient/Core/Inc/app_conf.h | 50 +- .../BLE/BLE_p2pClient/Core/Inc/app_debug.h | 69 + .../BLE/BLE_p2pClient/Core/Inc/hw_conf.h | 28 + .../Applications/BLE/BLE_p2pClient/Core/Inc/main.h | 1 + .../BLE_p2pClient/Core/Inc/stm32wbxx_hal_conf.h | 6 + .../BLE/BLE_p2pClient/Core/Src/app_debug.c | 399 + .../BLE/BLE_p2pClient/Core/Src/app_entry.c | 76 +- .../BLE/BLE_p2pClient/Core/Src/hw_timerserver.c | 2 +- .../BLE/BLE_p2pClient/Core/Src/hw_uart.c | 2 +- .../Applications/BLE/BLE_p2pClient/Core/Src/main.c | 6 +- .../BLE/BLE_p2pClient/Core/Src/stm32_lpm_if.c | 22 + .../BLE/BLE_p2pClient/Core/Src/stm32wbxx_hal_msp.c | 2 + .../BLE/BLE_p2pClient/EWARM/BLE_p2pClient.ewp | 3 + .../BLE_p2pClient/MDK-ARM/BLE_p2pClient.uvprojx | 5 + .../BLE/BLE_p2pClient/STM32_WPAN/App/app_ble.c | 2 +- .../BLE/BLE_p2pClient/STM32_WPAN/App/ble_conf.h | 2 +- .../BLE_p2pClient/STM32_WPAN/App/ble_dbg_conf.h | 2 +- .../BLE/BLE_p2pClient/STM32_WPAN/Target/hw_ipcc.c | 2 +- .../BLE_p2pClient/SW4STM32/BLE_p2pClient/.project | 5 + .../BLE_p2pClient/stm32wb55xx_flash_cm4.ld | 4 +- .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../BLE/BLE_p2pRouteur/BLE_p2pRouteur.ioc | 12 +- .../BLE/BLE_p2pRouteur/Core/Inc/app_common.h | 7 +- .../BLE/BLE_p2pRouteur/Core/Inc/app_conf.h | 51 +- .../BLE/BLE_p2pRouteur/Core/Inc/app_debug.h | 69 + .../BLE/BLE_p2pRouteur/Core/Inc/hw_conf.h | 28 + .../BLE/BLE_p2pRouteur/Core/Inc/main.h | 1 + .../BLE_p2pRouteur/Core/Inc/stm32wbxx_hal_conf.h | 6 + .../BLE/BLE_p2pRouteur/Core/Src/app_debug.c | 399 + .../BLE/BLE_p2pRouteur/Core/Src/app_entry.c | 76 +- .../BLE/BLE_p2pRouteur/Core/Src/hw_timerserver.c | 2 +- .../BLE/BLE_p2pRouteur/Core/Src/hw_uart.c | 2 +- .../BLE/BLE_p2pRouteur/Core/Src/main.c | 6 +- .../BLE/BLE_p2pRouteur/Core/Src/stm32_lpm_if.c | 22 + .../BLE_p2pRouteur/Core/Src/stm32wbxx_hal_msp.c | 2 + .../BLE/BLE_p2pRouteur/EWARM/BLE_p2pRouteur.ewp | 3 + .../BLE_p2pRouteur/MDK-ARM/BLE_p2pRouteur.uvprojx | 5 + .../BLE/BLE_p2pRouteur/STM32_WPAN/App/app_ble.c | 2 +- .../BLE/BLE_p2pRouteur/STM32_WPAN/App/ble_conf.h | 2 +- .../BLE_p2pRouteur/STM32_WPAN/App/ble_dbg_conf.h | 2 +- .../BLE/BLE_p2pRouteur/STM32_WPAN/Target/hw_ipcc.c | 2 +- .../SW4STM32/BLE_p2pRouteur/.project | 5 + .../BLE_p2pRouteur/stm32wb55xx_flash_cm4.ld | 4 +- .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../BLE/BLE_p2pServer/BLE_p2pServer.ioc | 12 +- .../Binary/BLE_p2pServer_reference.hex | 2841 ++-- .../BLE/BLE_p2pServer/Core/Inc/app_common.h | 7 +- .../BLE/BLE_p2pServer/Core/Inc/app_conf.h | 58 +- .../BLE/BLE_p2pServer/Core/Inc/app_debug.h | 69 + .../BLE/BLE_p2pServer/Core/Inc/hw_conf.h | 28 + .../Applications/BLE/BLE_p2pServer/Core/Inc/main.h | 1 + .../BLE_p2pServer/Core/Inc/stm32wbxx_hal_conf.h | 6 + .../BLE/BLE_p2pServer/Core/Src/app_debug.c | 399 + .../BLE/BLE_p2pServer/Core/Src/app_entry.c | 76 +- .../BLE/BLE_p2pServer/Core/Src/hw_timerserver.c | 2 +- .../BLE/BLE_p2pServer/Core/Src/hw_uart.c | 2 +- .../Applications/BLE/BLE_p2pServer/Core/Src/main.c | 6 +- .../BLE/BLE_p2pServer/Core/Src/stm32_lpm_if.c | 22 + .../BLE/BLE_p2pServer/Core/Src/stm32wbxx_hal_msp.c | 2 + .../BLE/BLE_p2pServer/EWARM/BLE_p2pServer.ewp | 3 + .../BLE_p2pServer/MDK-ARM/BLE_p2pServer.uvprojx | 5 + .../BLE/BLE_p2pServer/STM32_WPAN/App/app_ble.c | 47 +- .../BLE/BLE_p2pServer/STM32_WPAN/App/ble_conf.h | 2 +- .../BLE_p2pServer/STM32_WPAN/App/ble_dbg_conf.h | 2 +- .../BLE_p2pServer/STM32_WPAN/App/p2p_server_app.h | 2 +- .../BLE/BLE_p2pServer/STM32_WPAN/Target/hw_ipcc.c | 2 +- .../BLE_p2pServer/SW4STM32/BLE_p2pServer/.project | 5 + .../BLE_p2pServer/stm32wb55xx_flash_cm4.ld | 4 +- .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../Binary/BLE_p2pServer_ota_reference.bin | Bin 33620 -> 34312 bytes .../BLE/BLE_p2pServer_ota/Core/Inc/app_debug.h | 45 + .../BLE/BLE_p2pServer_ota/Core/Inc/hw_conf.h | 34 +- .../BLE/BLE_p2pServer_ota/Core/Src/app_debug.c | 353 + .../BLE/BLE_p2pServer_ota/Core/Src/app_entry.c | 80 +- .../BLE/BLE_p2pServer_ota/Core/Src/stm32_lpm_if.c | 22 + .../BLE_p2pServer_ota/EWARM/BLE_p2pServer_ota.ewp | 3 + .../MDK-ARM/BLE_p2pServer_ota.uvprojx | 5 + .../MDK-ARM/startup_stm32wb55xx_cm4.s | 16 +- .../SW4STM32/BLE_p2pServer_ota/.project | 5 + .../BLE_p2pServer_ota/stm32wb55xx_flash_cm4.ld | 4 +- .../Applications/BLE/BLE_p2pServer_ota/readme.txt | 2 + .../Ble_Thread_Static/Core/Inc/hw_conf.h | 34 +- .../Ble_Thread_Static/Core/Src/stm32_lpm_if.c | 22 + .../BLE_Zigbee_Static/Core/Inc/app_common.h | 120 + .../BLE_Zigbee_Static/Core/Inc/app_conf.h | 586 + .../BLE_Zigbee_Static/Core/Inc/app_entry.h | 53 + .../BLE_Zigbee_Static/Core/Inc/hw_conf.h | 249 + .../BLE_Zigbee/BLE_Zigbee_Static/Core/Inc/hw_if.h | 250 + .../BLE_Zigbee/BLE_Zigbee_Static/Core/Inc/main.h | 38 + .../BLE_Zigbee_Static/Core/Inc/stm32_lpm_if.h | 81 + .../Core/Inc/stm32wbxx_hal_conf.h | 349 + .../BLE_Zigbee_Static/Core/Inc/stm32wbxx_it.h | 62 + .../BLE_Zigbee_Static/Core/Inc/stm_logging.h | 63 + .../BLE_Zigbee_Static/Core/Inc/utilities_conf.h | 68 + .../BLE_Zigbee_Static/Core/Src/app_entry.c | 472 + .../BLE_Zigbee_Static/Core/Src/hw_timerserver.c | 893 ++ .../BLE_Zigbee_Static/Core/Src/hw_uart.c | 465 + .../BLE_Zigbee/BLE_Zigbee_Static/Core/Src/main.c | 320 + .../BLE_Zigbee_Static/Core/Src/stm32_lpm_if.c | 297 + .../BLE_Zigbee_Static/Core/Src/stm32wbxx_it.c | 188 + .../BLE_Zigbee_Static/Core/Src/stm_logging.c | 213 + .../BLE_Zigbee_Static/Core/Src/system_stm32wbxx.c | 343 + .../BLE_Zigbee_Static/EWARM/ble_zigbee_static.ewd | 1419 ++ .../BLE_Zigbee_Static/EWARM/ble_zigbee_static.ewp | 1315 ++ .../BLE_Zigbee_Static/EWARM/ble_zigbee_static.eww | 7 + .../EWARM/startup_stm32wb55xx_cm4.s | 528 + .../EWARM/stm32wb55xx_flash_cm4.icf | 41 + .../BLE_Zigbee_Static/STM32_WPAN/App/app_ble.c | 1136 ++ .../BLE_Zigbee_Static/STM32_WPAN/App/app_ble.h | 88 + .../BLE_Zigbee_Static/STM32_WPAN/App/app_zigbee.c | 810 ++ .../BLE_Zigbee_Static/STM32_WPAN/App/app_zigbee.h | 66 + .../BLE_Zigbee_Static/STM32_WPAN/App/ble_conf.h | 70 + .../STM32_WPAN/App/ble_dbg_conf.h | 199 + .../STM32_WPAN/App/p2p_server_app.c | 398 + .../STM32_WPAN/App/p2p_server_app.h | 81 + .../BLE_Zigbee_Static/STM32_WPAN/Target/hw_ipcc.c | 512 + .../BLE_Zigbee/BLE_Zigbee_Static/readme.txt | 134 + .../FatFs/FatFs_uSD_Standalone/.extSettings | 6 +- .../FatFs/FatFs_uSD_Standalone/Core/Inc/main.h | 11 +- .../Core/Inc/stm32wbxx_hal_conf.h | 6 + .../FatFs_uSD_Standalone/Core/Inc/stm32wbxx_it.h | 12 +- .../FatFs/FatFs_uSD_Standalone/Core/Src/main.c | 27 +- .../Core/Src/stm32wbxx_hal_msp.c | 14 +- .../FatFs_uSD_Standalone/Core/Src/stm32wbxx_it.c | 12 +- .../Core/Src/system_stm32wbxx.c | 6 +- .../EWARM/FatFs_uSD_Standalone.ewp | 23 +- .../EWARM/stm32wb55xx_flash_cm4.icf | 39 +- .../FatFs_uSD_Standalone/FATFS/App/app_fatfs.c | 57 +- .../FatFs_uSD_Standalone/FATFS/App/app_fatfs.h | 12 +- .../FatFs_uSD_Standalone/FATFS/Target/ffconf.h | 2 +- .../FatFs_uSD_Standalone/FATFS/Target/sd_diskio.c | 12 +- .../FatFs_uSD_Standalone/FATFS/Target/sd_diskio.h | 10 +- .../FatFs_uSD_Standalone/FatFs_uSD_Standalone.ioc | 17 +- .../FatFs/FatFs_uSD_Standalone/readme.txt | 32 +- .../FreeRTOS/FreeRTOS_Mail/FreeRTOS_Mail.ioc | 15 +- .../FreeRTOS/FreeRTOS_Mutexes/FreeRTOS_Mutexes.ioc | 15 +- .../FreeRTOS/FreeRTOS_Queues/FreeRTOS_Queues.ioc | 15 +- .../FreeRTOS_Semaphore/FreeRTOS_Semaphore.ioc | 15 +- .../FreeRTOS_SemaphoreFromISR.ioc | 15 +- .../EWARM/stm32wb55xx_flash_cm4.icf | 4 +- .../FreeRTOS/FreeRTOS_Signal/FreeRTOS_Signal.ioc | 15 +- .../FreeRTOS_SignalFromISR.ioc | 15 +- .../FreeRTOS_ThreadCreation.ioc | 15 +- .../FreeRTOS/FreeRTOS_Timers/FreeRTOS_Timers.ioc | 15 +- .../Mac_802_15_4_FFD/Core/Inc/hw_conf.h | 34 +- .../Mac_802_15_4_FFD/Core/Src/stm32_lpm_if.c | 22 + .../.project | 8 +- .../Core/inc/app_common.h | 117 + .../Core/inc/app_conf.h | 128 + .../Core/inc/app_entry.h | 57 + .../Core/inc/hw_conf.h | 195 + .../Core/inc/hw_if.h | 250 + .../Core/inc/main.h | 75 + .../Core/inc/stm32_lpm_if.h | 81 + .../Core/inc/stm32wbxx_hal_conf.h | 351 + .../Core/inc/stm32wbxx_it.h | 62 + .../Core/inc/utilities_conf.h | 68 + .../Core/src/app_entry.c | 383 + .../Core/src/main.c | 475 + .../Core/src/stm32_lpm_if.c | 297 + .../Core/src/stm32wbxx_hal_msp.c | 197 + .../Core/src/stm32wbxx_it.c | 134 + .../Core/src/system_stm32wbxx.c | 402 + .../EWARM/Mac_802_15_4_LPM_Periodic_Transmit.ewd | 1419 ++ .../EWARM/Mac_802_15_4_LPM_Periodic_Transmit.ewp | 1248 ++ .../EWARM/Mac_802_15_4_LPM_Periodic_Transmit.eww | 10 + .../EWARM/startup_stm32wb55xx_cm4.s | 528 + .../EWARM/stm32wb55xx_flash_cm4.icf | 47 + .../STM32_WPAN/app/app_lpm_transmit_mac_802_15_4.c | 398 + .../STM32_WPAN/app/app_lpm_transmit_mac_802_15_4.h | 168 + .../app/app_lpm_transmit_mac_802_15_4_process.c | 206 + .../app/app_lpm_transmit_mac_802_15_4_process.h | 84 + .../STM32_WPAN/target/hw_ipcc.c | 523 + .../Mac_802_15_4_LPM_Periodic_Transmit/readme.txt | 136 + .../Mac_802_15_4_RFD/Core/Inc/hw_conf.h | 34 +- .../Mac_802_15_4_RFD/Core/Src/stm32_lpm_if.c | 22 + .../.project | 8 +- .../Thread/Thread_Cli_Cmd/Core/Inc/app_common.h | 7 +- .../Thread/Thread_Cli_Cmd/Core/Inc/app_conf.h | 11 +- .../Thread/Thread_Cli_Cmd/Core/Inc/hw_conf.h | 28 + .../Thread_Cli_Cmd/Core/Inc/stm32wbxx_hal_conf.h | 6 + .../Thread/Thread_Cli_Cmd/Core/Inc/stm_logging.h | 2 +- .../Thread_Cli_Cmd/Core/Src/hw_timerserver.c | 2 +- .../Thread/Thread_Cli_Cmd/Core/Src/hw_uart.c | 2 +- .../Thread/Thread_Cli_Cmd/Core/Src/main.c | 9 +- .../Thread/Thread_Cli_Cmd/Core/Src/stm32_lpm_if.c | 22 + .../Thread_Cli_Cmd/Core/Src/stm32wbxx_hal_msp.c | 2 + .../Thread/Thread_Cli_Cmd/Core/Src/stm_logging.c | 2 +- .../Thread/Thread_Cli_Cmd/EWARM/Thread_Cli_Cmd.ewp | 89 +- .../Thread_Cli_Cmd/EWARM/stm32wb55xx_flash_cm4.icf | 2 +- .../Thread_Cli_Cmd/STM32_WPAN/Target/hw_ipcc.c | 2 +- .../Thread/Thread_Cli_Cmd/Thread_Cli_Cmd.ioc | 12 +- .../Thread_Coap_DataTransfer/Core/Inc/app_common.h | 114 - .../Thread_Coap_DataTransfer/Core/Inc/app_conf.h | 359 - .../Thread_Coap_DataTransfer/Core/Inc/app_entry.h | 68 - .../Thread_Coap_DataTransfer/Core/Inc/hw_conf.h | 219 - .../Thread_Coap_DataTransfer/Core/Inc/hw_if.h | 250 - .../Thread_Coap_DataTransfer/Core/Inc/main.h | 71 - .../Core/Inc/stm32_lpm_if.h | 81 - .../Core/Inc/stm32wbxx_hal_conf.h | 353 - .../Core/Inc/stm32wbxx_it.h | 83 - .../Core/Inc/stm_logging.h | 59 - .../Core/Inc/utilities_conf.h | 68 - .../Thread_Coap_DataTransfer/Core/Inc/vcp_conf.h | 53 - .../Thread_Coap_DataTransfer/Core/Src/app_entry.c | 430 - .../Core/Src/hw_timerserver.c | 893 -- .../Thread_Coap_DataTransfer/Core/Src/hw_uart.c | 318 - .../Thread_Coap_DataTransfer/Core/Src/main.c | 619 - .../Core/Src/stm32_lpm_if.c | 275 - .../Core/Src/stm32wbxx_hal_msp.c | 334 - .../Core/Src/stm32wbxx_it.c | 383 - .../Core/Src/stm_logging.c | 211 - .../Core/Src/system_stm32wbxx.c | 353 - .../Thread_Coap_DataTransfer/EWARM/Project.eww | 10 - .../EWARM/Thread_Coap_DataTransfer.ewd | 1419 -- .../EWARM/Thread_Coap_DataTransfer.ewp | 1359 -- .../EWARM/startup_stm32wb55xx_cm4.s | 528 - .../EWARM/stm32wb55xx_flash_cm4.icf | 40 - .../MDK-ARM/Thread_Coap_DataTransfer.uvoptx | 133 - .../MDK-ARM/Thread_Coap_DataTransfer.uvprojx | 861 -- .../MDK-ARM/startup_stm32wb55xx_cm4.s | 368 - .../MDK-ARM/stm32wb55xx_flash_cm4.sct | 21 - .../STM32_WPAN/App/app_thread.c | 1301 -- .../STM32_WPAN/App/app_thread.h | 137 - .../STM32_WPAN/App/data_transfer.h | 5033 ------- .../STM32_WPAN/Target/hw_ipcc.c | 523 - .../.cproject | 170 - .../.project | 414 - .../stm32wb55xx_flash_cm4.ld | 187 - .../SW4STM32/startup_stm32wb55xx_cm4.s | 427 - .../Thread_Coap_DataTransfer/SW4STM32/syscalls.c | 204 - .../Thread_Coap_DataTransfer.ioc | 254 - .../Thread/Thread_Coap_DataTransfer/readme.txt | 226 - .../Thread_Coap_Generic/Core/Inc/app_common.h | 7 +- .../Thread/Thread_Coap_Generic/Core/Inc/app_conf.h | 15 +- .../Thread/Thread_Coap_Generic/Core/Inc/hw_conf.h | 28 + .../Core/Inc/stm32wbxx_hal_conf.h | 6 + .../Thread_Coap_Generic/Core/Inc/stm_logging.h | 2 +- .../Thread_Coap_Generic/Core/Src/app_entry.c | 2 +- .../Thread_Coap_Generic/Core/Src/hw_timerserver.c | 2 +- .../Thread/Thread_Coap_Generic/Core/Src/hw_uart.c | 2 +- .../Thread/Thread_Coap_Generic/Core/Src/main.c | 9 +- .../Thread_Coap_Generic/Core/Src/stm32_lpm_if.c | 22 + .../Core/Src/stm32wbxx_hal_msp.c | 2 + .../Thread_Coap_Generic/Core/Src/stm_logging.c | 2 +- .../EWARM/Thread_Coap_Generic.ewp | 89 +- .../EWARM/stm32wb55xx_flash_cm4.icf | 2 +- .../STM32_WPAN/App/app_thread.c | 2 +- .../STM32_WPAN/Target/hw_ipcc.c | 2 +- .../Thread_Coap_Generic/Thread_Coap_Generic.ioc | 16 +- .../Thread_Coap_Generic_Ota/Core/Inc/hw_conf.h | 34 +- .../Thread_Coap_Generic_Ota/Core/Src/app_entry.c | 2 +- .../Core/Src/stm32_lpm_if.c | 22 + .../STM32_WPAN/App/app_thread.c | 2 +- .../Thread_Coap_MultiBoard/Core/Inc/app_common.h | 7 +- .../Thread_Coap_MultiBoard/Core/Inc/app_conf.h | 15 +- .../Thread_Coap_MultiBoard/Core/Inc/hw_conf.h | 28 + .../Core/Inc/stm32wbxx_hal_conf.h | 6 + .../Thread_Coap_MultiBoard/Core/Inc/stm_logging.h | 2 +- .../Thread_Coap_MultiBoard/Core/Src/app_entry.c | 2 +- .../Core/Src/hw_timerserver.c | 2 +- .../Thread_Coap_MultiBoard/Core/Src/hw_uart.c | 2 +- .../Thread/Thread_Coap_MultiBoard/Core/Src/main.c | 9 +- .../Thread_Coap_MultiBoard/Core/Src/stm32_lpm_if.c | 22 + .../Core/Src/stm32wbxx_hal_msp.c | 2 + .../Thread_Coap_MultiBoard/Core/Src/stm_logging.c | 2 +- .../EWARM/Thread_Coap_MultiBoard.ewd | 64 +- .../EWARM/Thread_Coap_MultiBoard.ewp | 2837 ++-- .../EWARM/stm32wb55xx_flash_cm4.icf | 2 +- .../STM32_WPAN/App/app_thread.c | 2 +- .../STM32_WPAN/Target/hw_ipcc.c | 2 +- .../Thread_Coap_Multiboard.ioc | 16 +- .../Thread_Commissioning/Core/Inc/app_common.h | 7 +- .../Thread_Commissioning/Core/Inc/app_conf.h | 15 +- .../Thread/Thread_Commissioning/Core/Inc/hw_conf.h | 28 + .../Core/Inc/stm32wbxx_hal_conf.h | 6 + .../Thread_Commissioning/Core/Inc/stm_logging.h | 2 +- .../Thread_Commissioning/Core/Src/app_entry.c | 2 +- .../Thread_Commissioning/Core/Src/hw_timerserver.c | 2 +- .../Thread/Thread_Commissioning/Core/Src/hw_uart.c | 2 +- .../Thread/Thread_Commissioning/Core/Src/main.c | 9 +- .../Thread_Commissioning/Core/Src/stm32_lpm_if.c | 22 + .../Core/Src/stm32wbxx_hal_msp.c | 2 + .../Thread_Commissioning/Core/Src/stm_logging.c | 2 +- .../EWARM/Thread_Commissioning.ewd | 64 +- .../EWARM/Thread_Commissioning.ewp | 2837 ++-- .../EWARM/stm32wb55xx_flash_cm4.icf | 2 +- .../STM32_WPAN/App/app_thread.c | 2 +- .../STM32_WPAN/Target/hw_ipcc.c | 2 +- .../Thread_Commissioning/Thread_Commissioning.ioc | 16 +- .../Core/Inc/app_common.h | 7 +- .../Thread_FTD_Coap_Multicast/Core/Inc/app_conf.h | 15 +- .../Thread_FTD_Coap_Multicast/Core/Inc/hw_conf.h | 28 + .../Core/Inc/stm32wbxx_hal_conf.h | 6 + .../Core/Inc/stm_logging.h | 2 +- .../Thread_FTD_Coap_Multicast/Core/Src/app_entry.c | 2 +- .../Core/Src/hw_timerserver.c | 2 +- .../Thread_FTD_Coap_Multicast/Core/Src/hw_uart.c | 2 +- .../Thread_FTD_Coap_Multicast/Core/Src/main.c | 9 +- .../Core/Src/stm32_lpm_if.c | 22 + .../Core/Src/stm32wbxx_hal_msp.c | 2 + .../Core/Src/stm_logging.c | 2 +- .../EWARM/Thread_FTD_Coap_Multicast.ewd | 64 +- .../EWARM/Thread_FTD_Coap_Multicast.ewp | 2837 ++-- .../EWARM/stm32wb55xx_flash_cm4.icf | 2 +- .../STM32_WPAN/App/app_thread.c | 36 +- .../STM32_WPAN/Target/hw_ipcc.c | 2 +- .../Thread_FTD_Coap_Multicast.ioc | 16 +- .../Thread/Thread_Ota/Core/Inc/hw_conf.h | 34 +- .../Thread/Thread_Ota/Core/Src/app_entry.c | 2 +- .../Thread/Thread_Ota/Core/Src/stm32_lpm_if.c | 22 + .../Thread/Thread_Ota/Core/Src/system_stm32wbxx.c | 18 +- .../Thread/Thread_Ota/STM32_WPAN/App/app_thread.c | 41 +- .../Thread/Thread_Ota_Server/Core/Inc/hw_conf.h | 34 +- .../Thread/Thread_Ota_Server/Core/Src/app_entry.c | 2 +- .../Thread_Ota_Server/Core/Src/stm32_lpm_if.c | 22 + .../Thread_Ota_Server/STM32_WPAN/App/app_thread.c | 39 +- .../Core/Inc/FreeRTOSConfig.h | 38 +- .../Thread_SED_Coap_FreeRTOS/Core/Inc/app_common.h | 7 +- .../Thread_SED_Coap_FreeRTOS/Core/Inc/app_conf.h | 17 +- .../Thread_SED_Coap_FreeRTOS/Core/Inc/hw_conf.h | 28 + .../Core/Inc/stm32wbxx_hal_conf.h | 6 + .../Core/Inc/stm_logging.h | 2 +- .../Thread_SED_Coap_FreeRTOS/Core/Src/app_entry.c | 4 +- .../Core/Src/app_freertos.c | 70 + .../Core/Src/freertos_port.c | 51 +- .../Core/Src/hw_timerserver.c | 2 +- .../Thread_SED_Coap_FreeRTOS/Core/Src/hw_uart.c | 2 +- .../Thread_SED_Coap_FreeRTOS/Core/Src/main.c | 10 +- .../Core/Src/stm32wbxx_hal_msp.c | 2 + .../Core/Src/stm_logging.c | 2 +- .../EWARM/Thread_SED_Coap_FreeRTOS.ewp | 54 +- .../EWARM/stm32wb55xx_flash_cm4.icf | 2 +- .../STM32_WPAN/App/app_thread.c | 6 +- .../STM32_WPAN/Target/hw_ipcc.c | 2 +- .../Thread_SED_Coap_FreeRTOS.ioc | 16 +- .../Core/Inc/app_common.h | 7 +- .../Thread_SED_Coap_Multicast/Core/Inc/app_conf.h | 15 +- .../Thread_SED_Coap_Multicast/Core/Inc/hw_conf.h | 28 + .../Core/Inc/stm32wbxx_hal_conf.h | 6 + .../Core/Inc/stm_logging.h | 2 +- .../Thread_SED_Coap_Multicast/Core/Src/app_entry.c | 2 +- .../Core/Src/hw_timerserver.c | 2 +- .../Thread_SED_Coap_Multicast/Core/Src/hw_uart.c | 2 +- .../Thread_SED_Coap_Multicast/Core/Src/main.c | 9 +- .../Core/Src/stm32_lpm_if.c | 22 + .../Core/Src/stm32wbxx_hal_msp.c | 2 + .../Core/Src/stm_logging.c | 2 +- .../EWARM/Thread_SED_Coap_Multicast.ewd | 64 +- .../EWARM/Thread_SED_Coap_Multicast.ewp | 2837 ++-- .../EWARM/stm32wb55xx_flash_cm4.icf | 2 +- .../STM32_WPAN/App/app_thread.c | 4 +- .../STM32_WPAN/Target/hw_ipcc.c | 2 +- .../Thread_SED_Coap_Multicast.ioc | 16 +- .../USB_Device/CDC_Standalone/CDC_Standalone.ioc | 20 +- .../CDC_Standalone/Core/Inc/stm32wbxx_hal_conf.h | 6 + .../USB_Device/CDC_Standalone/Core/Src/main.c | 5 + .../DFU_Standalone/Core/Inc/stm32wbxx_hal_conf.h | 6 + .../USB_Device/DFU_Standalone/Core/Src/main.c | 5 + .../USB_Device/DFU_Standalone/DFU_Standalone.ioc | 20 +- .../HID_Standalone/Core/Inc/stm32wbxx_hal_conf.h | 6 + .../USB_Device/HID_Standalone/Core/Src/main.c | 5 + .../USB_Device/HID_Standalone/HID_Standalone.ioc | 20 +- .../MSC_Standalone/Core/Inc/stm32wbxx_hal_conf.h | 6 + .../USB_Device/MSC_Standalone/Core/Src/main.c | 5 + .../USB_Device/MSC_Standalone/MSC_Standalone.ioc | 20 +- .../Core/Inc/app_common.h | 114 + .../Core/Inc/app_conf.h | 351 + .../Core/Inc/app_entry.h | 68 + .../Core/Inc/hw_conf.h | 247 + .../Zigbee_DevTemp_Client_Router/Core/Inc/hw_if.h | 250 + .../Zigbee_DevTemp_Client_Router/Core/Inc/main.h | 71 + .../Core/Inc/stm32_lpm_if.h | 81 + .../Core/Inc/stm32wbxx_hal_conf.h | 353 + .../Core/Inc/stm32wbxx_it.h | 83 + .../Core/Inc/stm_logging.h | 55 + .../Core/Inc/utilities_conf.h | 68 + .../Core/Src/app_entry.c | 503 + .../Core/Src/hw_timerserver.c | 893 ++ .../Core/Src/hw_uart.c | 318 + .../Zigbee_DevTemp_Client_Router/Core/Src/main.c | 521 + .../Core/Src/stm32_lpm_if.c | 297 + .../Core/Src/stm32wbxx_hal_msp.c | 334 + .../Core/Src/stm32wbxx_it.c | 411 + .../Core/Src/stm_logging.c | 205 + .../Core/Src/system_stm32wbxx.c | 353 + .../Zigbee_DevTemp_Client_Router/EWARM/Project.eww | 7 + .../EWARM/Zigbee_DevTemp_Client_Router.ewd | 1419 ++ .../EWARM/Zigbee_DevTemp_Client_Router.ewp | 1261 ++ .../EWARM/startup_stm32wb55xx_cm4.s | 517 + .../EWARM/stm32wb55xx_flash_cm4.icf | 47 + .../STM32_WPAN/App/app_zigbee.c | 637 + .../STM32_WPAN/App/app_zigbee.h | 62 + .../STM32_WPAN/Target/hw_ipcc.c | 513 + .../Zigbee/Zigbee_DevTemp_Client_Router/readme.txt | 137 + .../Core/Inc/app_common.h | 114 + .../Core/Inc/app_conf.h | 355 + .../Core/Inc/app_entry.h | 68 + .../Zigbee_DevTemp_Server_Coord/Core/Inc/hw_conf.h | 247 + .../Zigbee_DevTemp_Server_Coord/Core/Inc/hw_if.h | 250 + .../Zigbee_DevTemp_Server_Coord/Core/Inc/main.h | 71 + .../Core/Inc/stm32_lpm_if.h | 81 + .../Core/Inc/stm32wbxx_hal_conf.h | 353 + .../Core/Inc/stm32wbxx_it.h | 83 + .../Core/Inc/stm_logging.h | 55 + .../Core/Inc/utilities_conf.h | 68 + .../Core/Src/app_entry.c | 504 + .../Core/Src/hw_timerserver.c | 893 ++ .../Zigbee_DevTemp_Server_Coord/Core/Src/hw_uart.c | 318 + .../Zigbee_DevTemp_Server_Coord/Core/Src/main.c | 521 + .../Core/Src/stm32_lpm_if.c | 297 + .../Core/Src/stm32wbxx_hal_msp.c | 334 + .../Core/Src/stm32wbxx_it.c | 411 + .../Core/Src/stm_logging.c | 205 + .../Core/Src/system_stm32wbxx.c | 353 + .../Zigbee_DevTemp_Server_Coord/EWARM/Project.eww | 7 + .../EWARM/Zigbee_DevTemp_Server_Coord.ewd | 1419 ++ .../EWARM/Zigbee_DevTemp_Server_Coord.ewp | 1262 ++ .../EWARM/startup_stm32wb55xx_cm4.s | 517 + .../EWARM/stm32wb55xx_flash_cm4.icf | 47 + .../STM32_WPAN/App/app_zigbee.c | 680 + .../STM32_WPAN/App/app_zigbee.h | 62 + .../STM32_WPAN/Target/hw_ipcc.c | 513 + .../Zigbee/Zigbee_DevTemp_Server_Coord/readme.txt | 141 + .../Core/Inc/app_common.h | 114 + .../Core/Inc/app_conf.h | 353 + .../Core/Inc/app_entry.h | 68 + .../Core/Inc/hw_conf.h | 247 + .../Zigbee_MeterId_Client_Router/Core/Inc/hw_if.h | 250 + .../Zigbee_MeterId_Client_Router/Core/Inc/main.h | 71 + .../Core/Inc/stm32_lpm_if.h | 81 + .../Core/Inc/stm32wbxx_hal_conf.h | 353 + .../Core/Inc/stm32wbxx_it.h | 83 + .../Core/Inc/stm_logging.h | 55 + .../Core/Inc/utilities_conf.h | 68 + .../Core/Src/app_entry.c | 504 + .../Core/Src/hw_timerserver.c | 893 ++ .../Core/Src/hw_uart.c | 318 + .../Zigbee_MeterId_Client_Router/Core/Src/main.c | 521 + .../Core/Src/stm32_lpm_if.c | 297 + .../Core/Src/stm32wbxx_hal_msp.c | 334 + .../Core/Src/stm32wbxx_it.c | 411 + .../Core/Src/stm_logging.c | 205 + .../Core/Src/system_stm32wbxx.c | 353 + .../Zigbee_MeterId_Client_Router/EWARM/Project.eww | 7 + .../EWARM/Zigbee_MeterId_Client_Router.ewd | 1419 ++ .../EWARM/Zigbee_MeterId_Client_Router.ewp | 1261 ++ .../EWARM/startup_stm32wb55xx_cm4.s | 517 + .../EWARM/stm32wb55xx_flash_cm4.icf | 47 + .../STM32_WPAN/App/app_zigbee.c | 691 + .../STM32_WPAN/App/app_zigbee.h | 62 + .../STM32_WPAN/Target/hw_ipcc.c | 513 + .../Zigbee/Zigbee_MeterId_Client_Router/readme.txt | 144 + .../Core/Inc/app_common.h | 114 + .../Core/Inc/app_conf.h | 351 + .../Core/Inc/app_entry.h | 68 + .../Zigbee_MeterId_Server_Coord/Core/Inc/hw_conf.h | 247 + .../Zigbee_MeterId_Server_Coord/Core/Inc/hw_if.h | 250 + .../Zigbee_MeterId_Server_Coord/Core/Inc/main.h | 71 + .../Core/Inc/stm32_lpm_if.h | 81 + .../Core/Inc/stm32wbxx_hal_conf.h | 353 + .../Core/Inc/stm32wbxx_it.h | 83 + .../Core/Inc/stm_logging.h | 55 + .../Core/Inc/utilities_conf.h | 68 + .../Core/Src/app_entry.c | 502 + .../Core/Src/hw_timerserver.c | 893 ++ .../Zigbee_MeterId_Server_Coord/Core/Src/hw_uart.c | 318 + .../Zigbee_MeterId_Server_Coord/Core/Src/main.c | 521 + .../Core/Src/stm32_lpm_if.c | 297 + .../Core/Src/stm32wbxx_hal_msp.c | 334 + .../Core/Src/stm32wbxx_it.c | 411 + .../Core/Src/stm_logging.c | 205 + .../Core/Src/system_stm32wbxx.c | 353 + .../Zigbee_MeterId_Server_Coord/EWARM/Project.eww | 7 + .../EWARM/Zigbee_MeterId_Server_Coord.ewd | 1419 ++ .../EWARM/Zigbee_MeterId_Server_Coord.ewp | 1261 ++ .../EWARM/startup_stm32wb55xx_cm4.s | 517 + .../EWARM/stm32wb55xx_flash_cm4.icf | 47 + .../STM32_WPAN/App/app_zigbee.c | 600 + .../STM32_WPAN/App/app_zigbee.h | 62 + .../STM32_WPAN/Target/hw_ipcc.c | 513 + .../Zigbee/Zigbee_MeterId_Server_Coord/readme.txt | 144 + .../Core/Inc/app_conf.h | 5 +- .../Zigbee_OnOff_Client_Distrib/Core/Inc/hw_conf.h | 34 +- .../Core/Src/app_entry.c | 94 +- .../Core/Src/stm32_lpm_if.c | 22 + .../STM32_WPAN/App/app_zigbee.c | 86 +- .../STM32_WPAN/App/app_zigbee.h | 4 +- .../STM32_WPAN/Target/hw_ipcc.c | 50 +- .../Zigbee_OnOff_Client_Router/Core/Inc/app_conf.h | 5 +- .../Zigbee_OnOff_Client_Router/Core/Inc/hw_conf.h | 34 +- .../Core/Src/app_entry.c | 94 +- .../Core/Src/stm32_lpm_if.c | 22 + .../STM32_WPAN/App/app_zigbee.c | 88 +- .../STM32_WPAN/App/app_zigbee.h | 3 +- .../STM32_WPAN/Target/hw_ipcc.c | 50 +- .../Zigbee/Zigbee_OnOff_Client_Router/readme.txt | 12 - .../Zigbee_OnOff_Server_Coord/Core/Inc/app_conf.h | 5 +- .../Zigbee_OnOff_Server_Coord/Core/Inc/hw_conf.h | 34 +- .../Zigbee_OnOff_Server_Coord/Core/Src/app_entry.c | 104 +- .../Core/Src/stm32_lpm_if.c | 22 + .../STM32_WPAN/App/app_zigbee.c | 185 +- .../STM32_WPAN/App/app_zigbee.h | 3 +- .../STM32_WPAN/Target/hw_ipcc.c | 50 +- .../Zigbee/Zigbee_OnOff_Server_Coord/readme.txt | 13 - .../Core/Inc/app_conf.h | 5 +- .../Zigbee_OnOff_Server_Distrib/Core/Inc/hw_conf.h | 34 +- .../Core/Src/app_entry.c | 104 +- .../Core/Src/stm32_lpm_if.c | 22 + .../STM32_WPAN/App/app_zigbee.c | 185 +- .../STM32_WPAN/App/app_zigbee.h | 3 +- .../STM32_WPAN/Target/hw_ipcc.c | 50 +- .../Core/Inc/app_common.h | 114 + .../Core/Inc/app_conf.h | 351 + .../Core/Inc/app_entry.h | 68 + .../Core/Inc/hw_conf.h | 247 + .../Core/Inc/hw_if.h | 250 + .../Core/Inc/main.h | 71 + .../Core/Inc/stm32_lpm_if.h | 81 + .../Core/Inc/stm32wbxx_hal_conf.h | 353 + .../Core/Inc/stm32wbxx_it.h | 83 + .../Core/Inc/stm_logging.h | 55 + .../Core/Inc/utilities_conf.h | 68 + .../Core/Src/app_entry.c | 502 + .../Core/Src/hw_timerserver.c | 893 ++ .../Core/Src/hw_uart.c | 318 + .../Core/Src/main.c | 521 + .../Core/Src/stm32_lpm_if.c | 297 + .../Core/Src/stm32wbxx_hal_msp.c | 334 + .../Core/Src/stm32wbxx_it.c | 411 + .../Core/Src/stm_logging.c | 205 + .../Core/Src/system_stm32wbxx.c | 353 + .../EWARM/Project.eww | 7 + .../EWARM/Zigbee_PowerProfile_Client_Coord.ewd | 1419 ++ .../EWARM/Zigbee_PowerProfile_Client_Coord.ewp | 1261 ++ .../EWARM/startup_stm32wb55xx_cm4.s | 517 + .../EWARM/stm32wb55xx_flash_cm4.icf | 47 + .../STM32_WPAN/App/app_zigbee.c | 643 + .../STM32_WPAN/App/app_zigbee.h | 62 + .../STM32_WPAN/Target/hw_ipcc.c | 513 + .../Zigbee_PowerProfile_Client_Coord/readme.txt | 223 + .../Core/Inc/app_common.h | 114 + .../Core/Inc/app_conf.h | 359 + .../Core/Inc/app_entry.h | 68 + .../Core/Inc/hw_conf.h | 247 + .../Core/Inc/hw_if.h | 250 + .../Core/Inc/main.h | 71 + .../Core/Inc/stm32_lpm_if.h | 81 + .../Core/Inc/stm32wbxx_hal_conf.h | 353 + .../Core/Inc/stm32wbxx_it.h | 83 + .../Core/Inc/stm_logging.h | 55 + .../Core/Inc/utilities_conf.h | 68 + .../Core/Src/app_entry.c | 503 + .../Core/Src/hw_timerserver.c | 893 ++ .../Core/Src/hw_uart.c | 318 + .../Core/Src/main.c | 521 + .../Core/Src/stm32_lpm_if.c | 297 + .../Core/Src/stm32wbxx_hal_msp.c | 334 + .../Core/Src/stm32wbxx_it.c | 411 + .../Core/Src/stm_logging.c | 205 + .../Core/Src/system_stm32wbxx.c | 353 + .../EWARM/Project.eww | 7 + .../EWARM/Zigbee_PowerProfile_Server_Router.ewd | 1419 ++ .../EWARM/Zigbee_PowerProfile_Server_Router.ewp | 1261 ++ .../EWARM/startup_stm32wb55xx_cm4.s | 517 + .../EWARM/stm32wb55xx_flash_cm4.icf | 47 + .../STM32_WPAN/App/app_zigbee.c | 919 ++ .../STM32_WPAN/App/app_zigbee.h | 62 + .../STM32_WPAN/Target/hw_ipcc.c | 513 + .../Zigbee_PowerProfile_Server_Router/readme.txt | 225 + .../Core/Inc/app_common.h | 114 + .../Core/Inc/app_conf.h | 351 + .../Core/Inc/app_entry.h | 68 + .../Core/Inc/hw_conf.h | 247 + .../Core/Inc/hw_if.h | 250 + .../Zigbee_PressMeas_Client_Router/Core/Inc/main.h | 71 + .../Core/Inc/stm32_lpm_if.h | 81 + .../Core/Inc/stm32wbxx_hal_conf.h | 353 + .../Core/Inc/stm32wbxx_it.h | 83 + .../Core/Inc/stm_logging.h | 55 + .../Core/Inc/utilities_conf.h | 68 + .../Core/Src/app_entry.c | 503 + .../Core/Src/hw_timerserver.c | 893 ++ .../Core/Src/hw_uart.c | 318 + .../Zigbee_PressMeas_Client_Router/Core/Src/main.c | 521 + .../Core/Src/stm32_lpm_if.c | 297 + .../Core/Src/stm32wbxx_hal_msp.c | 334 + .../Core/Src/stm32wbxx_it.c | 411 + .../Core/Src/stm_logging.c | 205 + .../Core/Src/system_stm32wbxx.c | 353 + .../EWARM/Project.eww | 7 + .../EWARM/Zigbee_PressMeas_Client_Router.ewd | 1419 ++ .../EWARM/Zigbee_PressMeas_Client_Router.ewp | 1261 ++ .../EWARM/startup_stm32wb55xx_cm4.s | 517 + .../EWARM/stm32wb55xx_flash_cm4.icf | 47 + .../STM32_WPAN/App/app_zigbee.c | 700 + .../STM32_WPAN/App/app_zigbee.h | 62 + .../STM32_WPAN/Target/hw_ipcc.c | 513 + .../Zigbee_PressMeas_Client_Router/readme.txt | 142 + .../Core/Inc/app_common.h | 114 + .../Core/Inc/app_conf.h | 355 + .../Core/Inc/app_entry.h | 68 + .../Core/Inc/hw_conf.h | 247 + .../Zigbee_PressMeas_Server_Coord/Core/Inc/hw_if.h | 250 + .../Zigbee_PressMeas_Server_Coord/Core/Inc/main.h | 71 + .../Core/Inc/stm32_lpm_if.h | 81 + .../Core/Inc/stm32wbxx_hal_conf.h | 353 + .../Core/Inc/stm32wbxx_it.h | 83 + .../Core/Inc/stm_logging.h | 55 + .../Core/Inc/utilities_conf.h | 68 + .../Core/Src/app_entry.c | 504 + .../Core/Src/hw_timerserver.c | 893 ++ .../Core/Src/hw_uart.c | 318 + .../Zigbee_PressMeas_Server_Coord/Core/Src/main.c | 521 + .../Core/Src/stm32_lpm_if.c | 297 + .../Core/Src/stm32wbxx_hal_msp.c | 334 + .../Core/Src/stm32wbxx_it.c | 411 + .../Core/Src/stm_logging.c | 205 + .../Core/Src/system_stm32wbxx.c | 353 + .../EWARM/Project.eww | 7 + .../EWARM/Zigbee_PressMeas_Server_Coord.ewd | 1419 ++ .../EWARM/Zigbee_PressMeas_Server_Coord.ewp | 1262 ++ .../EWARM/startup_stm32wb55xx_cm4.s | 517 + .../EWARM/stm32wb55xx_flash_cm4.icf | 47 + .../STM32_WPAN/App/app_zigbee.c | 685 + .../STM32_WPAN/App/app_zigbee.h | 62 + .../STM32_WPAN/Target/hw_ipcc.c | 513 + .../Zigbee_PressMeas_Server_Coord/readme.txt | 148 + .../Core/Inc/app_common.h | 114 + .../Zigbee_SE_Msg_Client_Coord/Core/Inc/app_conf.h | 350 + .../Core/Inc/app_entry.h | 68 + .../Zigbee_SE_Msg_Client_Coord/Core/Inc/hw_conf.h | 247 + .../Zigbee_SE_Msg_Client_Coord/Core/Inc/hw_if.h | 250 + .../Zigbee_SE_Msg_Client_Coord/Core/Inc/main.h | 71 + .../Core/Inc/stm32_lpm_if.h | 81 + .../Core/Inc/stm32wbxx_hal_conf.h | 353 + .../Core/Inc/stm32wbxx_it.h | 83 + .../Core/Inc/stm_logging.h | 55 + .../Core/Inc/utilities_conf.h | 68 + .../Core/Src/app_entry.c | 502 + .../Core/Src/hw_timerserver.c | 893 ++ .../Zigbee_SE_Msg_Client_Coord/Core/Src/hw_uart.c | 318 + .../Zigbee_SE_Msg_Client_Coord/Core/Src/main.c | 521 + .../Core/Src/stm32_lpm_if.c | 297 + .../Core/Src/stm32wbxx_hal_msp.c | 334 + .../Core/Src/stm32wbxx_it.c | 411 + .../Core/Src/stm_logging.c | 205 + .../Core/Src/system_stm32wbxx.c | 353 + .../Zigbee_SE_Msg_Client_Coord/EWARM/Project.eww | 7 + .../EWARM/Zigbee_SE_Msg_Client_Coord.ewd | 1419 ++ .../EWARM/Zigbee_SE_Msg_Client_Coord.ewp | 1261 ++ .../EWARM/startup_stm32wb55xx_cm4.s | 517 + .../EWARM/stm32wb55xx_flash_cm4.icf | 47 + .../STM32_WPAN/App/app_zigbee.c | 580 + .../STM32_WPAN/App/app_zigbee.h | 62 + .../STM32_WPAN/Target/hw_ipcc.c | 513 + .../Zigbee/Zigbee_SE_Msg_Client_Coord/readme.txt | 128 + .../Core/Inc/app_common.h | 114 + .../Core/Inc/app_conf.h | 352 + .../Core/Inc/app_entry.h | 68 + .../Zigbee_SE_Msg_Server_Router/Core/Inc/hw_conf.h | 247 + .../Zigbee_SE_Msg_Server_Router/Core/Inc/hw_if.h | 250 + .../Zigbee_SE_Msg_Server_Router/Core/Inc/main.h | 71 + .../Core/Inc/stm32_lpm_if.h | 81 + .../Core/Inc/stm32wbxx_hal_conf.h | 353 + .../Core/Inc/stm32wbxx_it.h | 83 + .../Core/Inc/stm_logging.h | 55 + .../Core/Inc/utilities_conf.h | 68 + .../Core/Src/app_entry.c | 504 + .../Core/Src/hw_timerserver.c | 893 ++ .../Zigbee_SE_Msg_Server_Router/Core/Src/hw_uart.c | 318 + .../Zigbee_SE_Msg_Server_Router/Core/Src/main.c | 521 + .../Core/Src/stm32_lpm_if.c | 297 + .../Core/Src/stm32wbxx_hal_msp.c | 334 + .../Core/Src/stm32wbxx_it.c | 411 + .../Core/Src/stm_logging.c | 205 + .../Core/Src/system_stm32wbxx.c | 353 + .../Zigbee_SE_Msg_Server_Router/EWARM/Project.eww | 7 + .../EWARM/Zigbee_SE_Msg_Server_Router.ewd | 1419 ++ .../EWARM/Zigbee_SE_Msg_Server_Router.ewp | 1261 ++ .../EWARM/startup_stm32wb55xx_cm4.s | 517 + .../EWARM/stm32wb55xx_flash_cm4.icf | 47 + .../STM32_WPAN/App/app_zigbee.c | 632 + .../STM32_WPAN/App/app_zigbee.h | 62 + .../STM32_WPAN/Target/hw_ipcc.c | 513 + .../Zigbee/Zigbee_SE_Msg_Server_Router/readme.txt | 128 + .../Adafruit_LCD_1_8_SD_Joystick.ioc | 18 +- .../Core/Inc/stm32wbxx_hal_conf.h | 6 + .../Adafruit_LCD_1_8_SD_Joystick/Core/Src/main.c | 5 + .../FATFS/Target/ffconf.h | 2 +- .../ADC/ADC_AnalogWatchdog/ADC_AnalogWatchdog.ioc | 20 +- .../EWARM/ADC_AnalogWatchdog.ewp | 3 + .../ADC_AnalogWatchdog/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/ADC/ADC_AnalogWatchdog/Src/main.c | 6 +- .../ADC_MultiChannelSingleConversion.ioc | 20 +- .../EWARM/ADC_MultiChannelSingleConversion.ewp | 15 +- .../ADC_MultiChannelSingleConversion/Inc/main.h | 2 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../ADC_MultiChannelSingleConversion/Src/main.c | 6 +- .../ADC/ADC_Oversampling/ADC_Oversampling.ioc | 20 +- .../ADC_Oversampling/EWARM/ADC_Oversampling.ewp | 3 + .../ADC/ADC_Oversampling/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/ADC/ADC_Oversampling/Src/main.c | 6 +- .../ADC_SingleConversion_TriggerSW_IT.ioc | 20 +- .../EWARM/ADC_SingleConversion_TriggerSW_IT.ewp | 3 + .../Inc/stm32wbxx_hal_conf.h | 6 + .../ADC_SingleConversion_TriggerSW_IT/Src/main.c | 6 +- .../ADC_SingleConversion_TriggerTimer_DMA.ioc | 20 +- .../ADC_SingleConversion_TriggerTimer_DMA.ewp | 3 + .../Inc/stm32wbxx_hal_conf.h | 6 + .../Src/main.c | 6 +- .../Examples/BSP/BSP_Example/BSP_Example.ioc | 18 +- .../Examples/BSP/BSP_Example/EWARM/BSP_Example.ewp | 3 + .../BSP/BSP_Example/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/BSP/BSP_Example/Src/main.c | 5 + .../COMP_CompareGpioVsVrefInt_IT.ioc | 18 +- .../EWARM/COMP_CompareGpioVsVrefInt_IT.ewp | 12 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../COMP/COMP_CompareGpioVsVrefInt_IT/Src/main.c | 5 + .../COMP_CompareGpioVsVrefInt_Window_IT.ioc | 25 +- .../EWARM/COMP_CompareGpioVsVrefInt_Window_IT.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../Inc/stm32wbxx_it.h | 1 + .../COMP_CompareGpioVsVrefInt_Window_IT/Src/main.c | 17 +- .../Src/stm32wbxx_hal_msp.c | 25 + .../Src/stm32wbxx_it.c | 18 +- .../COMP_CompareGpioVsVrefInt_Window_IT/readme.txt | 2 +- .../Examples/CRC/CRC_Example/CRC_Example.ioc | 18 +- .../Examples/CRC/CRC_Example/EWARM/CRC_Example.ewp | 15 +- .../CRC/CRC_Example/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/CRC/CRC_Example/Src/main.c | 5 + .../CRC_UserDefinedPolynomial.ioc | 18 +- .../EWARM/CRC_UserDefinedPolynomial.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../CRC/CRC_UserDefinedPolynomial/Src/main.c | 5 + .../Examples/CRYP/CRYP_AESModes/CRYP_AESModes.ioc | 26 +- .../CRYP/CRYP_AESModes/EWARM/CRYP_AESModes.ewp | 15 +- .../CRYP/CRYP_AESModes/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/CRYP/CRYP_AESModes/Src/main.c | 7 + .../Examples/CRYP/CRYP_DMA/CRYP_DMA.ioc | 26 +- .../Examples/CRYP/CRYP_DMA/EWARM/CRYP_DMA.ewp | 15 +- .../CRYP/CRYP_DMA/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/CRYP/CRYP_DMA/Src/main.c | 7 + .../Examples/Cortex/CORTEXM_MPU/CORTEXM_MPU.ioc | 18 +- .../Cortex/CORTEXM_MPU/EWARM/CORTEXM_MPU.ewp | 3 + .../Cortex/CORTEXM_MPU/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/Cortex/CORTEXM_MPU/Src/main.c | 5 + .../CORTEXM_ModePrivilege.ioc | 18 +- .../EWARM/CORTEXM_ModePrivilege.ewp | 3 + .../CORTEXM_ModePrivilege/Inc/stm32wbxx_hal_conf.h | 6 + .../Cortex/CORTEXM_ModePrivilege/Src/main.c | 5 + .../Cortex/CORTEXM_SysTick/CORTEXM_SysTick.ioc | 18 +- .../CORTEXM_SysTick/EWARM/CORTEXM_SysTick.ewp | 3 + .../CORTEXM_SysTick/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/Cortex/CORTEXM_SysTick/Src/main.c | 5 + .../Examples/DMA/DMA_FLASHToRAM/DMA_FLASHToRAM.ioc | 22 +- .../DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewp | 3 + .../DMA/DMA_FLASHToRAM/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/DMA/DMA_FLASHToRAM/Src/main.c | 6 + .../Examples/DMA/DMA_MUXSYNC/DMA_MUXSYNC.ioc | 25 +- .../Examples/DMA/DMA_MUXSYNC/EWARM/DMA_MUXSYNC.ewp | 27 +- .../DMA/DMA_MUXSYNC/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/DMA/DMA_MUXSYNC/Src/main.c | 6 + .../DMA/DMA_MUX_RequestGen/DMA_MUX_RequestGen.ioc | 18 +- .../EWARM/DMA_MUX_RequestGen.ewp | 3 + .../DMA_MUX_RequestGen/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/DMA/DMA_MUX_RequestGen/Src/main.c | 5 + .../EWARM/FLASH_EraseProgram.ewp | 3 + .../FLASH_EraseProgram/FLASH_EraseProgram.ioc | 18 +- .../FLASH_EraseProgram/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/FLASH/FLASH_EraseProgram/Src/main.c | 5 + .../EWARM/FLASH_WriteProtection.ewp | 3 + .../FLASH_WriteProtection.ioc | 18 +- .../FLASH_WriteProtection/Inc/stm32wbxx_hal_conf.h | 6 + .../FLASH/FLASH_WriteProtection/Src/main.c | 5 + .../Examples/GPIO/GPIO_EXTI/EWARM/GPIO_EXTI.ewp | 3 + .../Examples/GPIO/GPIO_EXTI/GPIO_EXTI.ioc | 18 +- .../GPIO/GPIO_EXTI/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/GPIO/GPIO_EXTI/Src/main.c | 5 + .../GPIO/GPIO_IOToggle/EWARM/GPIO_IOToggle.ewp | 3 + .../Examples/GPIO/GPIO_IOToggle/GPIO_IOToggle.ioc | 18 +- .../GPIO/GPIO_IOToggle/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/GPIO/GPIO_IOToggle/Src/main.c | 5 + .../HAL/HAL_TimeBase/EWARM/HAL_TimeBase.ewp | 3 + .../Examples/HAL/HAL_TimeBase/HAL_TimeBase.ioc | 18 +- .../HAL/HAL_TimeBase/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/HAL/HAL_TimeBase/Src/main.c | 5 + .../EWARM/HAL_TimeBase_RTC_ALARM.ewp | 3 + .../HAL_TimeBase_RTC_ALARM.ioc | 18 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/main.c | 5 + .../EWARM/HAL_TimeBase_RTC_WKUP.ewp | 3 + .../HAL_TimeBase_RTC_WKUP.ioc | 18 +- .../HAL_TimeBase_RTC_WKUP/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/main.c | 5 + .../HAL_TimeBase_TIM/EWARM/HAL_TimeBase_TIM.ewp | 3 + .../HAL/HAL_TimeBase_TIM/HAL_TimeBase_TIM.ioc | 18 +- .../HAL/HAL_TimeBase_TIM/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/HAL/HAL_TimeBase_TIM/Src/main.c | 7 +- .../HSEM_ProcessSync/EWARM/HSEM_ProcessSync.ewp | 3 + .../HSEM/HSEM_ProcessSync/HSEM_ProcessSync.ioc | 18 +- .../HSEM/HSEM_ProcessSync/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/HSEM/HSEM_ProcessSync/Src/main.c | 5 + .../HSEM/HSEM_ReadLock/EWARM/HSEM_ReadLock.ewp | 3 + .../Examples/HSEM/HSEM_ReadLock/HSEM_ReadLock.ioc | 18 +- .../HSEM/HSEM_ReadLock/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/HSEM/HSEM_ReadLock/Src/main.c | 5 + .../EWARM/I2C_TwoBoards_AdvComIT.ewp | 15 +- .../I2C_TwoBoards_AdvComIT.ioc | 18 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/I2C/I2C_TwoBoards_AdvComIT/Src/main.c | 5 + .../EWARM/I2C_TwoBoards_ComDMA.ewp | 15 +- .../I2C_TwoBoards_ComDMA/I2C_TwoBoards_ComDMA.ioc | 26 +- .../I2C_TwoBoards_ComDMA/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/I2C/I2C_TwoBoards_ComDMA/Src/main.c | 6 + .../EWARM/I2C_TwoBoards_ComIT.ewp | 15 +- .../I2C_TwoBoards_ComIT/I2C_TwoBoards_ComIT.ioc | 18 +- .../I2C_TwoBoards_ComIT/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/I2C/I2C_TwoBoards_ComIT/Src/main.c | 5 + .../EWARM/I2C_TwoBoards_ComPolling.ewp | 15 +- .../I2C_TwoBoards_ComPolling.ioc | 18 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../I2C/I2C_TwoBoards_ComPolling/Src/main.c | 5 + .../EWARM/I2C_TwoBoards_RestartAdvComIT.ewp | 15 +- .../I2C_TwoBoards_RestartAdvComIT.ioc | 18 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../I2C/I2C_TwoBoards_RestartAdvComIT/Src/main.c | 5 + .../EWARM/I2C_TwoBoards_RestartComIT.ewp | 15 +- .../I2C_TwoBoards_RestartComIT.ioc | 18 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../I2C/I2C_TwoBoards_RestartComIT/Src/main.c | 5 + .../EWARM/I2C_WakeUpFromStop.ewp | 15 +- .../I2C/I2C_WakeUpFromStop/I2C_WakeUpFromStop.ioc | 18 +- .../I2C_WakeUpFromStop/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/I2C/I2C_WakeUpFromStop/Src/main.c | 6 +- .../EWARM/I2C_WakeUpFromStop2.ewp | 15 +- .../I2C_WakeUpFromStop2/I2C_WakeUpFromStop2.ioc | 18 +- .../I2C_WakeUpFromStop2/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/I2C/I2C_WakeUpFromStop2/Src/main.c | 6 +- .../Examples/IWDG/IWDG_Reset/EWARM/IWDG_Reset.ewp | 3 + .../Examples/IWDG/IWDG_Reset/IWDG_Reset.ioc | 20 +- .../IWDG/IWDG_Reset/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/IWDG/IWDG_Reset/Src/main.c | 5 + .../IWDG/IWDG_WindowMode/EWARM/IWDG_WindowMode.ewp | 3 + .../IWDG/IWDG_WindowMode/IWDG_WindowMode.ioc | 14 +- .../IWDG/IWDG_WindowMode/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/IWDG/IWDG_WindowMode/Src/main.c | 5 + .../LCD_SegmentsDrive/EWARM/LCD_SegmentsDrive.ewp | 12 +- .../LCD/LCD_SegmentsDrive/Inc/stm32wbxx_hal_conf.h | 6 + .../LCD/LCD_SegmentsDrive/LCD_SegmentsDrive.ioc | 23 +- .../Examples/LCD/LCD_SegmentsDrive/Src/main.c | 6 +- .../EWARM/LPTIM_PWMExternalClock.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../LPTIM_PWMExternalClock.ioc | 18 +- .../LPTIM/LPTIM_PWMExternalClock/Src/main.c | 5 + .../LPTIM/LPTIM_PWM_LSE/EWARM/LPTIM_PWM_LSE.ewp | 15 +- .../LPTIM/LPTIM_PWM_LSE/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/LPTIM/LPTIM_PWM_LSE/LPTIM_PWM_LSE.ioc | 18 +- .../Examples/LPTIM/LPTIM_PWM_LSE/Src/main.c | 5 + .../EWARM/LPTIM_PulseCounter.ewp | 15 +- .../LPTIM_PulseCounter/Inc/stm32wbxx_hal_conf.h | 6 + .../LPTIM_PulseCounter/LPTIM_PulseCounter.ioc | 18 +- .../Examples/LPTIM/LPTIM_PulseCounter/Src/main.c | 5 + .../LPTIM/LPTIM_Timeout/EWARM/LPTIM_Timeout.ewp | 15 +- .../LPTIM/LPTIM_Timeout/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/LPTIM/LPTIM_Timeout/LPTIM_Timeout.ioc | 18 +- .../Examples/LPTIM/LPTIM_Timeout/Src/main.c | 5 + .../EWARM/PKA_ECCscalarMultiplication.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../PKA_ECCscalarMultiplication.ioc | 18 +- .../PKA/PKA_ECCscalarMultiplication/Src/main.c | 5 + .../EWARM/PKA_ECCscalarMultiplication_IT.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../PKA_ECCscalarMultiplication_IT.ioc | 18 +- .../PKA/PKA_ECCscalarMultiplication_IT/Src/main.c | 5 + .../PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewp | 15 +- .../PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/PKA/PKA_ECDSA_Sign/PKA_ECDSA_Sign.ioc | 18 +- .../Examples/PKA/PKA_ECDSA_Sign/Src/main.c | 5 + .../PKA_ECDSA_Sign_IT/EWARM/PKA_ECDSA_Sign_IT.ewp | 15 +- .../PKA/PKA_ECDSA_Sign_IT/Inc/stm32wbxx_hal_conf.h | 6 + .../PKA/PKA_ECDSA_Sign_IT/PKA_ECDSA_Sign_IT.ioc | 18 +- .../Examples/PKA/PKA_ECDSA_Sign_IT/Src/main.c | 5 + .../PKA_ECDSA_Verify/EWARM/PKA_ECDSA_Verify.ewp | 15 +- .../PKA/PKA_ECDSA_Verify/Inc/stm32wbxx_hal_conf.h | 6 + .../PKA/PKA_ECDSA_Verify/PKA_ECDSA_Verify.ioc | 18 +- .../Examples/PKA/PKA_ECDSA_Verify/Src/main.c | 5 + .../EWARM/PKA_ECDSA_Verify_IT.ewp | 15 +- .../PKA_ECDSA_Verify_IT/Inc/stm32wbxx_hal_conf.h | 6 + .../PKA_ECDSA_Verify_IT/PKA_ECDSA_Verify_IT.ioc | 18 +- .../Examples/PKA/PKA_ECDSA_Verify_IT/Src/main.c | 5 + .../EWARM/PKA_ModularExponentiation.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../PKA_ModularExponentiation.ioc | 18 +- .../PKA/PKA_ModularExponentiation/Src/main.c | 5 + .../EWARM/PKA_ModularExponentiationCRT.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../PKA_ModularExponentiationCRT.ioc | 18 +- .../PKA/PKA_ModularExponentiationCRT/Src/main.c | 5 + .../EWARM/PKA_ModularExponentiationCRT_IT.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../PKA_ModularExponentiationCRT_IT.ioc | 18 +- .../PKA/PKA_ModularExponentiationCRT_IT/Src/main.c | 5 + .../EWARM/PKA_ModularExponentiation_IT.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../PKA_ModularExponentiation_IT.ioc | 18 +- .../PKA/PKA_ModularExponentiation_IT/Src/main.c | 5 + .../PKA/PKA_PointCheck/EWARM/PKA_PointCheck.ewp | 15 +- .../PKA/PKA_PointCheck/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/PKA/PKA_PointCheck/PKA_PointCheck.ioc | 18 +- .../Examples/PKA/PKA_PointCheck/Src/main.c | 5 + .../PKA_PointCheck_IT/EWARM/PKA_PointCheck_IT.ewp | 15 +- .../PKA/PKA_PointCheck_IT/Inc/stm32wbxx_hal_conf.h | 6 + .../PKA/PKA_PointCheck_IT/PKA_PointCheck_IT.ioc | 18 +- .../Examples/PKA/PKA_PointCheck_IT/Src/main.c | 5 + .../Examples/PWR/PWR_LPRUN/EWARM/PWR_LPRUN.ewp | 3 + .../PWR/PWR_LPRUN/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/PWR/PWR_LPRUN/PWR_LPRUN.ioc | 18 +- .../Examples/PWR/PWR_LPRUN/Src/main.c | 5 + .../Examples/PWR/PWR_LPSLEEP/EWARM/PWR_LPSLEEP.ewp | 3 + .../PWR/PWR_LPSLEEP/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/PWR/PWR_LPSLEEP/PWR_LPSLEEP.ioc | 18 +- .../Examples/PWR/PWR_LPSLEEP/Src/main.c | 5 + .../Examples/PWR/PWR_PVD/EWARM/PWR_PVD.ewp | 3 + .../Examples/PWR/PWR_PVD/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/PWR/PWR_PVD/PWR_PVD.ioc | 18 +- .../Examples/PWR/PWR_PVD/Src/main.c | 5 + .../PWR/PWR_STANDBY_RTC/EWARM/PWR_STANDBY_RTC.ewp | 15 +- .../PWR/PWR_STANDBY_RTC/Inc/stm32wbxx_hal_conf.h | 6 + .../PWR/PWR_STANDBY_RTC/PWR_STANDBY_RTC.ioc | 18 +- .../Examples/PWR/PWR_STANDBY_RTC/Src/main.c | 5 + .../PWR/PWR_STOP2_RTC/EWARM/PWR_STOP2_RTC.ewp | 12 +- .../PWR/PWR_STOP2_RTC/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/PWR/PWR_STOP2_RTC/PWR_STOP2_RTC.ioc | 18 +- .../Examples/PWR/PWR_STOP2_RTC/Src/main.c | 5 + .../EWARM/QSPI_ExecuteInPlace.ewp | 38 +- .../QSPI_ExecuteInPlace/Inc/stm32wbxx_hal_conf.h | 6 + .../QSPI_ExecuteInPlace/QSPI_ExecuteInPlace.ioc | 35 +- .../Examples/QSPI/QSPI_ExecuteInPlace/Src/main.c | 8 +- .../QSPI_MemoryMapped/EWARM/QSPI_MemoryMapped.ewp | 38 +- .../QSPI_MemoryMapped/Inc/stm32wbxx_hal_conf.h | 6 + .../QSPI/QSPI_MemoryMapped/QSPI_MemoryMapped.ioc | 32 +- .../Examples/QSPI/QSPI_MemoryMapped/Src/main.c | 8 +- .../EWARM/QSPI_ReadWrite_DMA.ewp | 38 +- .../QSPI_ReadWrite_DMA/Inc/stm32wbxx_hal_conf.h | 6 + .../QSPI/QSPI_ReadWrite_DMA/QSPI_ReadWrite_DMA.ioc | 32 +- .../Examples/QSPI/QSPI_ReadWrite_DMA/Src/main.c | 8 +- .../QSPI_ReadWrite_IT/EWARM/QSPI_ReadWrite_IT.ewp | 38 +- .../QSPI_ReadWrite_IT/Inc/stm32wbxx_hal_conf.h | 6 + .../QSPI/QSPI_ReadWrite_IT/QSPI_ReadWrite_IT.ioc | 32 +- .../Examples/QSPI/QSPI_ReadWrite_IT/Src/main.c | 7 +- .../EWARM/RCC_CRS_Synchronization_IT.ewp | 3 + .../Inc/stm32wbxx_hal_conf.h | 6 + .../RCC_CRS_Synchronization_IT.ioc | 18 +- .../RCC/RCC_CRS_Synchronization_IT/Src/main.c | 5 + .../EWARM/RCC_CRS_Synchronization_Polling.ewp | 3 + .../Inc/stm32wbxx_hal_conf.h | 6 + .../RCC_CRS_Synchronization_Polling.ioc | 18 +- .../RCC/RCC_CRS_Synchronization_Polling/Src/main.c | 5 + .../RCC/RCC_ClockConfig/EWARM/RCC_ClockConfig.ewp | 3 + .../RCC/RCC_ClockConfig/Inc/stm32wbxx_hal_conf.h | 6 + .../RCC/RCC_ClockConfig/RCC_ClockConfig.ioc | 18 +- .../Examples/RCC/RCC_ClockConfig/Src/main.c | 5 + .../RNG/RNG_MultiRNG/EWARM/RNG_MultiRNG.ewp | 15 +- .../RNG/RNG_MultiRNG/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/RNG/RNG_MultiRNG/RNG_MultiRNG.ioc | 18 +- .../Examples/RNG/RNG_MultiRNG/Src/main.c | 5 + .../RNG/RNG_MultiRNG_IT/EWARM/RNG_MultiRNG_IT.ewp | 15 +- .../RNG/RNG_MultiRNG_IT/Inc/stm32wbxx_hal_conf.h | 16 +- .../RNG/RNG_MultiRNG_IT/RNG_MultiRNG_IT.ioc | 18 +- .../Examples/RNG/RNG_MultiRNG_IT/Src/main.c | 5 + .../Examples/RTC/RTC_Alarm/EWARM/RTC_Alarm.ewp | 12 +- .../RTC/RTC_Alarm/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/RTC/RTC_Alarm/RTC_Alarm.ioc | 25 +- .../Examples/RTC/RTC_Alarm/Src/main.c | 11 +- .../Examples/RTC/RTC_Alarm/Src/stm32wbxx_hal_msp.c | 2 + .../RTC/RTC_Calendar/EWARM/RTC_Calendar.ewp | 15 +- .../RTC/RTC_Calendar/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/RTC/RTC_Calendar/RTC_Calendar.ioc | 16 +- .../Examples/RTC/RTC_Calendar/Src/main.c | 9 +- .../RTC/RTC_Calendar/Src/stm32wbxx_hal_msp.c | 2 + .../Examples/RTC/RTC_LSI/EWARM/RTC_LSI.ewp | 3 + .../Examples/RTC/RTC_LSI/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/RTC/RTC_LSI/RTC_LSI.ioc | 16 +- .../Examples/RTC/RTC_LSI/Src/main.c | 8 +- .../Examples/RTC/RTC_LSI/Src/stm32wbxx_hal_msp.c | 2 + .../Examples/RTC/RTC_Tamper/EWARM/RTC_Tamper.ewp | 15 +- .../RTC/RTC_Tamper/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/RTC/RTC_Tamper/RTC_Tamper.ioc | 16 +- .../Examples/RTC/RTC_Tamper/Src/main.c | 8 +- .../RTC/RTC_Tamper/Src/stm32wbxx_hal_msp.c | 2 + .../RTC/RTC_TimeStamp/EWARM/RTC_TimeStamp.ewp | 15 +- .../RTC/RTC_TimeStamp/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/RTC/RTC_TimeStamp/RTC_TimeStamp.ioc | 16 +- .../Examples/RTC/RTC_TimeStamp/Src/main.c | 10 +- .../RTC/RTC_TimeStamp/Src/stm32wbxx_hal_msp.c | 2 + .../EWARM/SPI_FullDuplex_ComDMA_Master.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../SPI_FullDuplex_ComDMA_Master.ioc | 26 +- .../SPI/SPI_FullDuplex_ComDMA_Master/Src/main.c | 6 + .../EWARM/SPI_FullDuplex_ComDMA_Slave.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../SPI_FullDuplex_ComDMA_Slave.ioc | 26 +- .../SPI/SPI_FullDuplex_ComDMA_Slave/Src/main.c | 6 + .../EWARM/SPI_FullDuplex_ComIT_Master.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../SPI_FullDuplex_ComIT_Master.ioc | 18 +- .../SPI/SPI_FullDuplex_ComIT_Master/Src/main.c | 5 + .../EWARM/SPI_FullDuplex_ComIT_Slave.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../SPI_FullDuplex_ComIT_Slave.ioc | 18 +- .../SPI/SPI_FullDuplex_ComIT_Slave/Src/main.c | 5 + .../EWARM/SPI_FullDuplex_ComPolling_Master.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../SPI_FullDuplex_ComPolling_Master.ioc | 18 +- .../SPI_FullDuplex_ComPolling_Master/Src/main.c | 5 + .../EWARM/SPI_FullDuplex_ComPolling_Slave.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../SPI_FullDuplex_ComPolling_Slave.ioc | 18 +- .../SPI/SPI_FullDuplex_ComPolling_Slave/Src/main.c | 5 + .../Examples/TIM/TIM_DMA/EWARM/TIM_DMA.ewp | 3 + .../Examples/TIM/TIM_DMA/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/TIM/TIM_DMA/Src/main.c | 6 + .../Examples/TIM/TIM_DMA/TIM_DMA.ioc | 22 +- .../TIM/TIM_DMABurst/EWARM/TIM_DMABurst.ewp | 3 + .../TIM/TIM_DMABurst/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/TIM/TIM_DMABurst/Src/main.c | 6 + .../Examples/TIM/TIM_DMABurst/TIM_DMABurst.ioc | 16 +- .../TIM_InputCapture/EWARM/TIM_InputCapture.ewp | 3 + .../TIM/TIM_InputCapture/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/TIM/TIM_InputCapture/Src/main.c | 5 + .../TIM/TIM_InputCapture/TIM_InputCapture.ioc | 18 +- .../TIM/TIM_OCActive/EWARM/TIM_OCActive.ewp | 3 + .../TIM/TIM_OCActive/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/TIM/TIM_OCActive/Src/main.c | 5 + .../Examples/TIM/TIM_OCActive/TIM_OCActive.ioc | 18 +- .../TIM/TIM_OCInactive/EWARM/TIM_OCInactive.ewp | 3 + .../TIM/TIM_OCInactive/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/TIM/TIM_OCInactive/Src/main.c | 5 + .../Examples/TIM/TIM_OCInactive/TIM_OCInactive.ioc | 18 +- .../TIM/TIM_OCToggle/EWARM/TIM_OCToggle.ewp | 3 + .../TIM/TIM_OCToggle/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/TIM/TIM_OCToggle/Src/main.c | 5 + .../Examples/TIM/TIM_OCToggle/TIM_OCToggle.ioc | 18 +- .../TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewp | 3 + .../TIM/TIM_PWMInput/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/TIM/TIM_PWMInput/Src/main.c | 5 + .../Examples/TIM/TIM_PWMInput/TIM_PWMInput.ioc | 18 +- .../TIM/TIM_PWMOutput/EWARM/TIM_PWMOutput.ewp | 3 + .../TIM/TIM_PWMOutput/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/TIM/TIM_PWMOutput/Src/main.c | 5 + .../Examples/TIM/TIM_PWMOutput/TIM_PWMOutput.ioc | 20 +- .../TIM/TIM_TimeBase/EWARM/TIM_TimeBase.ewp | 3 + .../TIM/TIM_TimeBase/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/TIM/TIM_TimeBase/Src/main.c | 5 + .../Examples/TIM/TIM_TimeBase/TIM_TimeBase.ioc | 18 +- .../EWARM/UART_HyperTerminal_DMA.ewp | 3 + .../Inc/stm32wbxx_hal_conf.h | 6 + .../UART/UART_HyperTerminal_DMA/Src/main.c | 6 + .../UART_HyperTerminal_DMA.ioc | 28 +- .../EWARM/UART_HyperTerminal_IT.ewp | 3 + .../UART_HyperTerminal_IT/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/UART/UART_HyperTerminal_IT/Src/main.c | 5 + .../UART_HyperTerminal_IT.ioc | 20 +- .../UART/UART_Printf/EWARM/UART_Printf.ewp | 3 + .../UART/UART_Printf/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/UART/UART_Printf/Src/main.c | 5 + .../Examples/UART/UART_Printf/UART_Printf.ioc | 20 +- .../EWARM/UART_TwoBoards_ComDMA.ewp | 3 + .../UART_TwoBoards_ComDMA/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/UART/UART_TwoBoards_ComDMA/Src/main.c | 6 + .../UART_TwoBoards_ComDMA.ioc | 28 +- .../EWARM/UART_TwoBoards_ComIT.ewp | 3 + .../UART_TwoBoards_ComIT/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/UART/UART_TwoBoards_ComIT/Src/main.c | 5 + .../UART_TwoBoards_ComIT/UART_TwoBoards_ComIT.ioc | 20 +- .../EWARM/UART_TwoBoards_ComPolling.ewp | 3 + .../Inc/stm32wbxx_hal_conf.h | 6 + .../UART/UART_TwoBoards_ComPolling/Src/main.c | 5 + .../UART_TwoBoards_ComPolling.ioc | 20 +- .../WWDG/WWDG_Example/EWARM/WWDG_Example.ewp | 3 + .../WWDG/WWDG_Example/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples/WWDG/WWDG_Example/Src/main.c | 5 + .../Examples/WWDG/WWDG_Example/WWDG_Example.ioc | 20 +- .../ADC_AnalogWatchdog_Init.ioc | 19 +- .../ADC/ADC_AnalogWatchdog_Init/Inc/stm32_assert.h | 2 +- .../ADC/ADC_AnalogWatchdog_Init/Src/main.c | 4 +- .../ADC_ContinuousConversion_TriggerSW_Init.ioc | 19 +- .../Inc/stm32_assert.h | 2 +- .../Src/main.c | 4 +- ...ontinuousConversion_TriggerSW_LowPower_Init.ioc | 19 +- .../Inc/stm32_assert.h | 2 +- .../Src/main.c | 4 +- .../ADC_GroupsRegularInjected_Init.ioc | 21 +- .../Inc/stm32_assert.h | 2 +- .../ADC/ADC_GroupsRegularInjected_Init/Src/main.c | 8 +- .../ADC_Oversampling_Init.ioc | 19 +- .../ADC/ADC_Oversampling_Init/Inc/stm32_assert.h | 2 +- .../ADC/ADC_Oversampling_Init/Src/main.c | 4 +- .../ADC_SingleConversion_TriggerSW_DMA_Init.ioc | 19 +- .../Inc/stm32_assert.h | 2 +- .../Src/main.c | 4 +- .../ADC_SingleConversion_TriggerSW_IT_Init.ioc | 19 +- .../Inc/stm32_assert.h | 2 +- .../Src/main.c | 4 +- .../ADC_SingleConversion_TriggerSW_Init.ioc | 19 +- .../Inc/stm32_assert.h | 2 +- .../ADC_SingleConversion_TriggerSW_Init/Src/main.c | 4 +- .../ADC_SingleConversion_TriggerTimer_DMA_Init.ioc | 19 +- .../Inc/stm32_assert.h | 2 +- .../Src/main.c | 4 +- .../COMP_CompareGpioVsVrefInt_IT_Init.ioc | 16 +- .../Inc/stm32_assert.h | 2 +- .../COMP_CompareGpioVsVrefInt_IT_Init/Src/main.c | 3 + .../COMP_CompareGpioVsVrefInt_OutputGpio_Init.ioc | 16 +- .../Inc/stm32_assert.h | 2 +- .../Src/main.c | 3 + .../COMP_CompareGpioVsVrefInt_Window_IT_Init.ioc | 16 +- .../Inc/stm32_assert.h | 2 +- .../Src/main.c | 3 + .../Examples_LL/CORTEX/CORTEX_MPU/CORTEX_MPU.ioc | 38 +- .../Examples_LL/CORTEX/CORTEX_MPU/Inc/main.h | 4 +- .../CORTEX/CORTEX_MPU/Inc/stm32_assert.h | 43 +- .../Examples_LL/CORTEX/CORTEX_MPU/Src/main.c | 41 +- .../CRC_CalculateAndCheck.ioc | 16 +- .../CRC/CRC_CalculateAndCheck/Inc/stm32_assert.h | 2 +- .../CRC/CRC_CalculateAndCheck/Src/main.c | 3 + .../CRC_UserDefinedPolynomial.ioc | 16 +- .../CRC_UserDefinedPolynomial/Inc/stm32_assert.h | 2 +- .../CRC/CRC_UserDefinedPolynomial/Src/main.c | 3 + .../CRS_Synchronization_IT.ioc | 18 +- .../CRS/CRS_Synchronization_IT/Inc/stm32_assert.h | 2 +- .../CRS/CRS_Synchronization_IT/Src/main.c | 3 + .../CRS_Synchronization_Polling.ioc | 18 +- .../CRS_Synchronization_Polling/Inc/stm32_assert.h | 2 +- .../CRS/CRS_Synchronization_Polling/Src/main.c | 3 + .../DMA_CopyFromFlashToMemory_Init.ioc | 20 +- .../Inc/stm32_assert.h | 2 +- .../DMA/DMA_CopyFromFlashToMemory_Init/Src/main.c | 4 + .../EXTI_ToggleLedOnIT_Init.ioc | 18 +- .../EXTI_ToggleLedOnIT_Init/Inc/stm32_assert.h | 2 +- .../EXTI/EXTI_ToggleLedOnIT_Init/Src/main.c | 3 + .../GPIO_InfiniteLedToggling_Init.ioc | 16 +- .../Inc/stm32_assert.h | 2 +- .../GPIO/GPIO_InfiniteLedToggling_Init/Src/main.c | 3 + .../HSEM/HSEM_DualProcess/HSEM_DualProcess.ioc | 18 +- .../HSEM/HSEM_DualProcess/Inc/stm32_assert.h | 2 +- .../Examples_LL/HSEM/HSEM_DualProcess/Src/main.c | 3 + .../HSEM_DualProcess_IT/HSEM_DualProcess_IT.ioc | 16 +- .../HSEM/HSEM_DualProcess_IT/Inc/stm32_assert.h | 2 +- .../HSEM/HSEM_DualProcess_IT/Src/main.c | 3 + ...I2C_OneBoard_AdvCommunication_DMAAndIT_Init.ioc | 20 +- .../Inc/stm32_assert.h | 2 +- .../Src/main.c | 4 + .../I2C_OneBoard_Communication_DMAAndIT_Init.ioc | 20 +- .../Inc/stm32_assert.h | 2 +- .../Src/main.c | 4 + .../I2C_OneBoard_Communication_IT_Init.ioc | 20 +- .../Inc/stm32_assert.h | 2 +- .../I2C_OneBoard_Communication_IT_Init/Src/main.c | 3 + ...2C_OneBoard_Communication_PollingAndIT_Init.ioc | 18 +- .../Inc/stm32_assert.h | 2 +- .../Src/main.c | 3 + .../I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ioc | 18 +- .../Inc/stm32_assert.h | 2 +- .../Src/main.c | 3 + .../I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ioc | 18 +- .../Inc/stm32_assert.h | 2 +- .../Src/main.c | 4 + .../I2C_TwoBoards_MasterTx_SlaveRx_Init.ioc | 18 +- .../Inc/stm32_assert.h | 2 +- .../I2C_TwoBoards_MasterTx_SlaveRx_Init/Src/main.c | 3 + .../I2C_TwoBoards_WakeUpFromStop2_IT_Init.ioc | 18 +- .../Inc/stm32_assert.h | 2 +- .../Src/main.c | 7 +- .../I2C_TwoBoards_WakeUpFromStop_IT_Init.ioc | 18 +- .../Inc/stm32_assert.h | 2 +- .../Src/main.c | 3 + .../IWDG_RefreshUntilUserEvent_Init.ioc | 18 +- .../Inc/stm32_assert.h | 2 +- .../IWDG_RefreshUntilUserEvent_Init/Src/main.c | 3 + .../EWARM/LPTIM_PulseCounter_Init.ewp | 2163 +-- .../LPTIM_PulseCounter_Init/Inc/stm32_assert.h | 2 +- .../LPTIM_PulseCounter_Init.ioc | 16 +- .../LPTIM/LPTIM_PulseCounter_Init/Src/main.c | 3 + .../LPUART_WakeUpFromStop2_Init/Inc/stm32_assert.h | 2 +- .../LPUART_WakeUpFromStop2_Init.ioc | 16 +- .../LPUART/LPUART_WakeUpFromStop2_Init/Src/main.c | 3 + .../LPUART_WakeUpFromStop_Init/Inc/stm32_assert.h | 2 +- .../LPUART_WakeUpFromStop_Init.ioc | 16 +- .../LPUART/LPUART_WakeUpFromStop_Init/Src/main.c | 3 + .../PKA/PKA_ECDSA_Sign/Inc/stm32_assert.h | 2 +- .../PKA/PKA_ECDSA_Sign/PKA_ECDSA_Sign.ioc | 16 +- .../Examples_LL/PKA/PKA_ECDSA_Sign/Src/main.c | 3 + .../PKA_ModularExponentiation/Inc/stm32_assert.h | 2 +- .../PKA_ModularExponentiation.ioc | 16 +- .../PKA/PKA_ModularExponentiation/Src/main.c | 3 + .../PWR/PWR_EnterStandbyMode/Inc/stm32_assert.h | 2 +- .../PWR_EnterStandbyMode/PWR_EnterStandbyMode.ioc | 16 +- .../PWR/PWR_EnterStandbyMode/Src/main.c | 3 + .../PWR/PWR_EnterStopMode/Inc/stm32_assert.h | 2 +- .../PWR/PWR_EnterStopMode/PWR_EnterStopMode.ioc | 16 +- .../Examples_LL/PWR/PWR_EnterStopMode/Src/main.c | 3 + .../PWR/PWR_OptimizedRunMode/Inc/stm32_assert.h | 2 +- .../PWR_OptimizedRunMode/PWR_OptimizedRunMode.ioc | 18 +- .../PWR/PWR_OptimizedRunMode/Src/main.c | 3 + .../EWARM/PWR_SMPS_16MHZ_HSI.ewp | 2 +- .../PWR/PWR_SMPS_16MHZ_HSI/Inc/stm32_assert.h | 2 +- .../PWR/PWR_SMPS_16MHZ_HSI/PWR_SMPS_16MHZ_HSI.ioc | 16 +- .../Examples_LL/PWR/PWR_SMPS_16MHZ_HSI/Src/main.c | 3 + .../PWR/PWR_SMPS_64MHZ_MSI_PLL/Inc/stm32_assert.h | 2 +- .../PWR_SMPS_64MHZ_MSI_PLL.ioc | 16 +- .../PWR/PWR_SMPS_64MHZ_MSI_PLL/Src/main.c | 3 + .../RCC_HWAutoMSICalibration/Inc/stm32_assert.h | 2 +- .../RCC_HWAutoMSICalibration.ioc | 18 +- .../RCC/RCC_HWAutoMSICalibration/Src/main.c | 3 + .../RCC_OutputSystemClockOnMCO/Inc/stm32_assert.h | 2 +- .../RCC_OutputSystemClockOnMCO.ioc | 18 +- .../RCC/RCC_OutputSystemClockOnMCO/Src/main.c | 3 + .../RCC/RCC_UseHSEasSystemClock/Inc/stm32_assert.h | 2 +- .../RCC_UseHSEasSystemClock.ioc | 16 +- .../RCC/RCC_UseHSEasSystemClock/Src/main.c | 3 + .../RCC_UseHSI_PLLasSystemClock/Inc/stm32_assert.h | 2 +- .../RCC_UseHSI_PLLasSystemClock.ioc | 18 +- .../RCC/RCC_UseHSI_PLLasSystemClock/Src/main.c | 3 + .../RNG_GenerateRandomNumbers/Inc/stm32_assert.h | 2 +- .../RNG_GenerateRandomNumbers.ioc | 20 +- .../RNG/RNG_GenerateRandomNumbers/Src/main.c | 3 + .../Inc/stm32_assert.h | 2 +- .../RNG_GenerateRandomNumbers_IT.ioc | 18 +- .../RNG/RNG_GenerateRandomNumbers_IT/Src/main.c | 3 + .../RTC/RTC_Alarm_Init/Inc/stm32_assert.h | 2 +- .../RTC/RTC_Alarm_Init/RTC_Alarm_Init.ioc | 19 +- .../Examples_LL/RTC/RTC_Alarm_Init/Src/main.c | 5 +- .../RTC/RTC_Calendar_Init/Inc/stm32_assert.h | 2 +- .../RTC/RTC_Calendar_Init/RTC_Calendar_Init.ioc | 16 +- .../Examples_LL/RTC/RTC_Calendar_Init/Src/main.c | 3 + .../Inc/stm32_assert.h | 2 +- .../RTC_ExitStandbyWithWakeUpTimer_Init.ioc | 18 +- .../RTC_ExitStandbyWithWakeUpTimer_Init/Src/main.c | 3 + .../RTC/RTC_Tamper_Init/Inc/stm32_assert.h | 2 +- .../RTC/RTC_Tamper_Init/RTC_Tamper_Init.ioc | 16 +- .../Examples_LL/RTC/RTC_Tamper_Init/Src/main.c | 3 + .../RTC/RTC_TimeStamp_Init/Inc/stm32_assert.h | 2 +- .../RTC/RTC_TimeStamp_Init/RTC_TimeStamp_Init.ioc | 16 +- .../Examples_LL/RTC/RTC_TimeStamp_Init/Src/main.c | 3 + .../Inc/stm32_assert.h | 2 +- .../SPI_OneBoard_HalfDuplex_DMA_Init.ioc | 18 +- .../SPI_OneBoard_HalfDuplex_DMA_Init/Src/main.c | 4 + .../Inc/stm32_assert.h | 2 +- .../SPI_OneBoard_HalfDuplex_IT_Init.ioc | 18 +- .../SPI/SPI_OneBoard_HalfDuplex_IT_Init/Src/main.c | 3 + .../Inc/stm32_assert.h | 2 +- .../SPI_TwoBoards_FullDuplex_DMA_Master_Init.ioc | 18 +- .../Src/main.c | 4 + .../Inc/stm32_assert.h | 2 +- .../SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ioc | 22 +- .../Src/main.c | 14 +- .../Inc/stm32_assert.h | 2 +- .../SPI_TwoBoards_FullDuplex_IT_Master_Init.ioc | 23 +- .../Src/main.c | 13 +- .../Inc/stm32_assert.h | 2 +- .../SPI_TwoBoards_FullDuplex_IT_Slave_Init.ioc | 21 +- .../Src/main.c | 13 +- .../TIM/TIM_DMA_Init/Inc/stm32_assert.h | 2 +- .../Examples_LL/TIM/TIM_DMA_Init/Src/main.c | 4 + .../Examples_LL/TIM/TIM_DMA_Init/TIM_DMA_Init.ioc | 24 +- .../TIM/TIM_InputCapture_Init/Inc/stm32_assert.h | 2 +- .../TIM/TIM_InputCapture_Init/Src/main.c | 3 + .../TIM_InputCapture_Init.ioc | 20 +- .../TIM/TIM_OutputCompare_Init/Inc/stm32_assert.h | 2 +- .../TIM/TIM_OutputCompare_Init/Src/main.c | 3 + .../TIM_OutputCompare_Init.ioc | 18 +- .../TIM/TIM_PWMOutput_Init/Inc/stm32_assert.h | 2 +- .../Examples_LL/TIM/TIM_PWMOutput_Init/Src/main.c | 3 + .../TIM/TIM_PWMOutput_Init/TIM_PWMOutput_Init.ioc | 22 +- .../TIM/TIM_TimeBase_Init/Inc/stm32_assert.h | 2 +- .../Examples_LL/TIM/TIM_TimeBase_Init/Src/main.c | 3 + .../TIM/TIM_TimeBase_Init/TIM_TimeBase_Init.ioc | 18 +- .../Inc/stm32_assert.h | 2 +- .../Src/main.c | 3 + .../USART_Communication_Rx_IT_Continuous_Init.ioc | 10 +- .../Inc/stm32_assert.h | 2 +- .../Src/main.c | 3 + ...ART_Communication_Rx_IT_Continuous_VCP_Init.ioc | 19 +- .../Inc/stm32_assert.h | 2 +- .../USART_Communication_Rx_IT_Init/Src/main.c | 3 + .../USART_Communication_Rx_IT_Init.ioc | 10 +- .../Inc/stm32_assert.h | 2 +- .../USART_Communication_Rx_IT_VCP_Init/Src/main.c | 3 + .../USART_Communication_Rx_IT_VCP_Init.ioc | 10 +- .../Inc/stm32_assert.h | 2 +- .../USART_Communication_TxRx_DMA_Init/Src/main.c | 4 + .../USART_Communication_TxRx_DMA_Init.ioc | 10 +- .../Inc/stm32_assert.h | 2 +- .../USART_Communication_Tx_IT_Init/Src/main.c | 3 + .../USART_Communication_Tx_IT_Init.ioc | 10 +- .../Inc/stm32_assert.h | 2 +- .../USART_Communication_Tx_IT_VCP_Init/Src/main.c | 3 + .../USART_Communication_Tx_IT_VCP_Init.ioc | 10 +- .../USART_Communication_Tx_Init/Inc/stm32_assert.h | 2 +- .../USART/USART_Communication_Tx_Init/Src/main.c | 3 + .../USART_Communication_Tx_Init.ioc | 10 +- .../Inc/stm32_assert.h | 2 +- .../USART_Communication_Tx_VCP_Init/Src/main.c | 3 + .../USART_Communication_Tx_VCP_Init.ioc | 10 +- .../USART_WakeUpFromStop1_Init/Inc/stm32_assert.h | 2 +- .../USART/USART_WakeUpFromStop1_Init/Src/main.c | 3 + .../USART_WakeUpFromStop1_Init.ioc | 10 +- .../USART_WakeUpFromStop_Init/Inc/stm32_assert.h | 2 +- .../USART/USART_WakeUpFromStop_Init/Src/main.c | 3 + .../USART_WakeUpFromStop_Init.ioc | 10 +- .../UTILS_ConfigureSystemClock/Inc/stm32_assert.h | 2 +- .../UTILS/UTILS_ConfigureSystemClock/Src/main.c | 3 + .../UTILS_ConfigureSystemClock.ioc | 16 +- .../UTILS/UTILS_ReadDeviceInfo/Inc/stm32_assert.h | 2 +- .../UTILS/UTILS_ReadDeviceInfo/Src/main.c | 3 + .../UTILS_ReadDeviceInfo/UTILS_ReadDeviceInfo.ioc | 10 +- .../Inc/stm32_assert.h | 2 +- .../WWDG_RefreshUntilUserEvent_Init/Src/main.c | 3 + .../WWDG_RefreshUntilUserEvent_Init.ioc | 18 +- .../ADC_SingleConversion_TriggerSW_IT.ioc | 17 +- .../EWARM/ADC_SingleConversion_TriggerSW_IT.ewp | 3 + .../Inc/stm32wbxx_hal_conf.h | 6 + .../ADC_SingleConversion_TriggerSW_IT/Src/main.c | 7 +- .../CRC_PolynomialUpdate/CRC_PolynomialUpdate.ioc | 18 +- .../EWARM/CRC_PolynomialUpdate.ewp | 15 +- .../CRC_PolynomialUpdate/Inc/stm32wbxx_hal_conf.h | 6 + .../CRC/CRC_PolynomialUpdate/Src/main.c | 5 + .../DMA/DMA_FLASHToRAM/DMA_FLASHToRAM.ioc | 22 +- .../DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewp | 3 + .../DMA/DMA_FLASHToRAM/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples_MIX/DMA/DMA_FLASHToRAM/Src/main.c | 6 + .../EWARM/I2C_OneBoard_ComSlave7_10bits_IT.ewp | 12 +- .../I2C_OneBoard_ComSlave7_10bits_IT.ioc | 18 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../I2C_OneBoard_ComSlave7_10bits_IT/Src/main.c | 5 + .../Examples_MIX/PWR/PWR_STOP1/EWARM/PWR_STOP1.ewp | 3 + .../PWR/PWR_STOP1/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples_MIX/PWR/PWR_STOP1/PWR_STOP1.ioc | 16 +- .../Examples_MIX/PWR/PWR_STOP1/Src/main.c | 5 + .../EWARM/SPI_FullDuplex_ComPolling_Master.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../SPI_FullDuplex_ComPolling_Master.ioc | 18 +- .../SPI_FullDuplex_ComPolling_Master/Src/main.c | 5 + .../EWARM/SPI_FullDuplex_ComPolling_Slave.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../SPI_FullDuplex_ComPolling_Slave.ioc | 18 +- .../SPI/SPI_FullDuplex_ComPolling_Slave/Src/main.c | 5 + .../EWARM/SPI_HalfDuplex_ComPollingIT_Master.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../SPI_HalfDuplex_ComPollingIT_Master.ioc | 18 +- .../SPI_HalfDuplex_ComPollingIT_Master/Src/main.c | 5 + .../EWARM/SPI_HalfDuplex_ComPollingIT_Slave.ewp | 15 +- .../Inc/stm32wbxx_hal_conf.h | 6 + .../SPI_HalfDuplex_ComPollingIT_Slave.ioc | 21 +- .../SPI_HalfDuplex_ComPollingIT_Slave/Src/main.c | 5 + .../Src/stm32wbxx_hal_msp.c | 9 +- .../TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewp | 3 + .../TIM/TIM_PWMInput/Inc/stm32wbxx_hal_conf.h | 6 + .../Examples_MIX/TIM/TIM_PWMInput/Src/main.c | 5 + .../Examples_MIX/TIM/TIM_PWMInput/TIM_PWMInput.ioc | 20 +- .../EWARM/UART_HyperTerminal_IT.ewp | 3 + .../UART_HyperTerminal_IT/Inc/stm32wbxx_hal_conf.h | 6 + .../UART/UART_HyperTerminal_IT/Src/main.c | 5 + .../UART_HyperTerminal_IT.ioc | 20 +- .../EWARM/UART_HyperTerminal_TxPolling_RxIT.ewp | 3 + .../Inc/stm32wbxx_hal_conf.h | 6 + .../UART_HyperTerminal_TxPolling_RxIT/Src/main.c | 5 + .../UART_HyperTerminal_TxPolling_RxIT.ioc | 20 +- Projects/P-NUCLEO-WB55.Nucleo/Release_Notes.html | 45 +- .../Templates/Inc/stm32wbxx_hal_conf.h | 6 + Projects/P-NUCLEO-WB55.Nucleo/Templates/Src/main.c | 5 + .../P-NUCLEO-WB55.Nucleo/Templates/Templates.ioc | 18 +- .../Templates_LL/Inc/stm32_assert.h | 2 +- .../P-NUCLEO-WB55.Nucleo/Templates_LL/Src/main.c | 3 + .../Templates_LL/Templates_LL.ioc | 16 +- .../BLE/BLE_HeartRate/Core/Inc/app_debug.h | 45 + .../BLE/BLE_HeartRate/Core/Inc/hw_conf.h | 34 +- .../BLE/BLE_HeartRate/Core/Src/app_debug.c | 350 + .../BLE/BLE_HeartRate/Core/Src/app_entry.c | 65 +- .../BLE/BLE_HeartRate/Core/Src/stm32_lpm_if.c | 22 + .../BLE/BLE_HeartRate/EWARM/BLE_HeartRate.ewp | 3 + .../BLE_HeartRate/EWARM/startup_stm32wb55xx_cm4.s | 51 +- .../BLE/BLE_HeartRate/MDK-ARM/BLE_HeartRate.uvoptx | 134 +- .../BLE_HeartRate/MDK-ARM/BLE_HeartRate.uvprojx | 15 +- .../BLE_HeartRate/SW4STM32/BLE_HeartRate/.project | 5 + .../BLE_HeartRate/stm32wb55xx_flash_cm4.ld | 4 +- .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../BLE/BLE_MeshLightingDemo/Core/Inc/app_conf.h | 13 +- .../BLE/BLE_MeshLightingDemo/Core/Inc/hw_conf.h | 34 +- .../BLE/BLE_MeshLightingDemo/Core/Inc/hw_flash.h | 87 + .../BLE/BLE_MeshLightingDemo/Core/Inc/lp_timer.h | 60 + .../BLE/BLE_MeshLightingDemo/Core/Src/app_debug.c | 114 +- .../BLE/BLE_MeshLightingDemo/Core/Src/app_entry.c | 84 +- .../BLE/BLE_MeshLightingDemo/Core/Src/hw_flash.c | 152 + .../BLE/BLE_MeshLightingDemo/Core/Src/hw_uart.c | 38 +- .../BLE/BLE_MeshLightingDemo/Core/Src/lp_timer.c | 134 + .../BLE/BLE_MeshLightingDemo/Core/Src/main.c | 157 +- .../BLE_MeshLightingDemo/Core/Src/stm32_lpm_if.c | 22 + .../EWARM/BLE_MeshLightingDemo.ewd | 9 +- .../EWARM/BLE_MeshLightingDemo.ewp | 58 +- .../EWARM/startup_stm32wb55xx_cm4.s | 51 +- .../EWARM/stm32wb55xx_flash_cm4.icf | 2 +- .../MDK-ARM/BLE_MeshLightingDemo.uvoptx | 404 +- .../MDK-ARM/BLE_MeshLightingDemo.uvprojx | 442 +- .../STM32_WPAN/app/PWM_config.h | 75 - .../STM32_WPAN/app/PWM_handlers.c | 7 +- .../BLE_MeshLightingDemo/STM32_WPAN/app/app_ble.c | 27 +- .../STM32_WPAN/app/appli_config_client.c | 1773 +++ .../STM32_WPAN/app/appli_config_client.h | 75 + .../STM32_WPAN/app/appli_generic.c | 96 +- .../STM32_WPAN/app/appli_generic.h | 18 +- .../STM32_WPAN/app/appli_generic_client.c | 101 + .../STM32_WPAN/app/appli_generic_client.h | 45 + .../STM32_WPAN/app/appli_light.c | 337 +- .../STM32_WPAN/app/appli_light.h | 45 +- .../STM32_WPAN/app/appli_light_client.c | 102 + .../STM32_WPAN/app/appli_light_client.h | 62 + .../STM32_WPAN/app/appli_light_lc.c | 42 +- .../STM32_WPAN/app/appli_light_lc.h | 11 +- .../STM32_WPAN/app/appli_mesh.c | 739 +- .../STM32_WPAN/app/appli_mesh.h | 17 +- .../STM32_WPAN/app/appli_nvm.c | 449 +- .../STM32_WPAN/app/appli_nvm.h | 23 +- .../STM32_WPAN/app/appli_sensor.c | 293 +- .../STM32_WPAN/app/appli_sensor.h | 4 +- .../STM32_WPAN/app/appli_vendor.c | 129 +- .../STM32_WPAN/app/appli_vendor.h | 1 + .../BLE_MeshLightingDemo/STM32_WPAN/app/mesh_cfg.h | 31 +- .../STM32_WPAN/app/mesh_cfg_usr.h | 341 +- .../STM32_WPAN/app/models_if.c | 203 +- .../STM32_WPAN/app/models_if.h | 5 + .../BLE_MeshLightingDemo/STM32_WPAN/app/pal_nvm.c | 106 +- .../BLE_MeshLightingDemo/STM32_WPAN/app/user_if.h | 2 +- .../SW4STM32/BLE_Lighting_Demo/.cproject | 185 - .../SW4STM32/BLE_Lighting_Demo/.project | 434 - .../BLE_Lighting_Demo/stm32wb55xx_flash_cm4.ld | 187 - .../SW4STM32/Lighting_Node/.cproject | 185 + .../SW4STM32/Lighting_Node/.project | 473 + .../Lighting_Node/stm32wb55xx_flash_cm4.ld | 187 + .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../BLE/BLE_MeshLightingDemo/readme.txt | 120 +- .../Binary/BLE_TransparentModeVCP_reference.hex | 908 +- .../BLE_TransparentModeVCP/Core/Inc/app_debug.h | 45 + .../BLE/BLE_TransparentModeVCP/Core/Inc/hw_conf.h | 34 +- .../BLE_TransparentModeVCP/Core/Src/app_debug.c | 350 + .../BLE_TransparentModeVCP/Core/Src/app_entry.c | 66 +- .../BLE_TransparentModeVCP/Core/Src/stm32_lpm_if.c | 22 + .../EWARM/BLE_TransparentModeVCP.ewp | 3 + .../EWARM/startup_stm32wb55xx_cm4.s | 51 +- .../MDK-ARM/BLE_TransparentModeVCP.uvprojx | 5 + .../SW4STM32/BLE_TransparentModeVCP/.project | 5 + .../stm32wb55xx_flash_cm4.ld | 4 +- .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../Binary/BLE_p2pClient_reference.hex | 1224 +- .../BLE/BLE_p2pClient/Core/Inc/app_debug.h | 45 + .../BLE/BLE_p2pClient/Core/Inc/hw_conf.h | 34 +- .../BLE/BLE_p2pClient/Core/Src/app_debug.c | 350 + .../BLE/BLE_p2pClient/Core/Src/app_entry.c | 65 +- .../BLE/BLE_p2pClient/Core/Src/stm32_lpm_if.c | 22 + .../BLE/BLE_p2pClient/EWARM/BLE_p2pClient.ewp | 3 + .../BLE_p2pClient/EWARM/startup_stm32wb55xx_cm4.s | 51 +- .../BLE_p2pClient/MDK-ARM/BLE_p2pClient.uvprojx | 5 + .../BLE_p2pClient/SW4STM32/BLE_p2pClient/.project | 5 + .../BLE_p2pClient/stm32wb55xx_flash_cm4.ld | 4 +- .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../BLE/BLE_p2pRouteur/Core/Inc/app_debug.h | 45 + .../BLE/BLE_p2pRouteur/Core/Inc/hw_conf.h | 34 +- .../BLE/BLE_p2pRouteur/Core/Src/app_debug.c | 350 + .../BLE/BLE_p2pRouteur/Core/Src/app_entry.c | 67 +- .../BLE/BLE_p2pRouteur/Core/Src/stm32_lpm_if.c | 22 + .../BLE/BLE_p2pRouteur/EWARM/BLE_p2pRouteur.ewp | 3 + .../BLE_p2pRouteur/EWARM/startup_stm32wb55xx_cm4.s | 51 +- .../BLE_p2pRouteur/MDK-ARM/BLE_p2pRouteur.uvoptx | 132 +- .../BLE_p2pRouteur/MDK-ARM/BLE_p2pRouteur.uvprojx | 15 +- .../SW4STM32/BLE_p2pRouteur/.project | 5 + .../BLE_p2pRouteur/stm32wb55xx_flash_cm4.ld | 4 +- .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../Binary/BLE_p2pServer_reference.hex | 1205 +- .../BLE/BLE_p2pServer/Core/Inc/app_debug.h | 45 + .../BLE/BLE_p2pServer/Core/Inc/hw_conf.h | 34 +- .../BLE/BLE_p2pServer/Core/Src/app_debug.c | 350 + .../BLE/BLE_p2pServer/Core/Src/app_entry.c | 68 +- .../BLE/BLE_p2pServer/Core/Src/stm32_lpm_if.c | 22 + .../BLE/BLE_p2pServer/EWARM/BLE_p2pServer.ewp | 3 + .../BLE_p2pServer/EWARM/startup_stm32wb55xx_cm4.s | 51 +- .../BLE_p2pServer/MDK-ARM/BLE_p2pServer.uvprojx | 5 + .../BLE_p2pServer/SW4STM32/BLE_p2pServer/.project | 5 + .../BLE_p2pServer/stm32wb55xx_flash_cm4.ld | 4 +- .../SW4STM32/startup_stm32wb55xx_cm4.s | 64 +- .../Thread/Thread_Cli_Cmd/Core/Inc/hw_conf.h | 34 +- .../Thread/Thread_Cli_Cmd/Core/Src/stm32_lpm_if.c | 22 + .../Thread_Coap_DataTransfer/Core/Inc/app_common.h | 117 - .../Thread_Coap_DataTransfer/Core/Inc/app_conf.h | 378 - .../Thread_Coap_DataTransfer/Core/Inc/app_entry.h | 45 - .../Thread_Coap_DataTransfer/Core/Inc/hw_conf.h | 222 - .../Thread_Coap_DataTransfer/Core/Inc/hw_if.h | 250 - .../Thread_Coap_DataTransfer/Core/Inc/main.h | 55 - .../Core/Inc/stm32_lpm_if.h | 81 - .../Core/Inc/stm32wbxx_hal_conf.h | 351 - .../Core/Inc/stm32wbxx_it.h | 77 - .../Core/Inc/stm_logging.h | 63 - .../Core/Inc/utilities_conf.h | 68 - .../Thread_Coap_DataTransfer/Core/Inc/vcp_conf.h | 54 - .../Thread_Coap_DataTransfer/Core/Src/app_entry.c | 431 - .../Core/Src/hw_timerserver.c | 893 -- .../Thread_Coap_DataTransfer/Core/Src/hw_uart.c | 471 - .../Thread_Coap_DataTransfer/Core/Src/main.c | 333 - .../Core/Src/stm32_lpm_if.c | 275 - .../Core/Src/stm32wbxx_it.c | 191 - .../Core/Src/stm_logging.c | 211 - .../Core/Src/system_stm32wbxx.c | 343 - .../Thread_Coap_DataTransfer/EWARM/Project.ewd | 1419 -- .../Thread_Coap_DataTransfer/EWARM/Project.ewp | 1383 -- .../Thread_Coap_DataTransfer/EWARM/Project.eww | 10 - .../EWARM/startup_stm32wb55xx_cm4.s | 528 - .../EWARM/stm32wb55xx_flash_cm4.icf | 47 - .../MDK-ARM/Project.uvoptx | 133 - .../MDK-ARM/Project.uvprojx | 891 -- .../MDK-ARM/startup_stm32wb55xx_cm4.s | 368 - .../MDK-ARM/stm32wb55xx_flash_cm4.sct | 21 - .../STM32_WPAN/App/app_thread.c | 1258 -- .../STM32_WPAN/App/app_thread.h | 110 - .../STM32_WPAN/App/data_transfer.h | 5033 ------- .../STM32_WPAN/Target/hw_ipcc.c | 523 - .../.cproject | 170 - .../.project | 429 - .../stm32wb55xx_flash_cm4.ld | 187 - .../SW4STM32/startup_stm32wb55xx_cm4.s | 427 - .../Thread_Coap_DataTransfer/SW4STM32/syscalls.c | 204 - .../Thread/Thread_Coap_DataTransfer/readme.txt | 197 - .../Thread/Thread_Coap_Generic/Core/Inc/hw_conf.h | 34 +- .../Thread_Coap_Generic/Core/Src/stm32_lpm_if.c | 22 + .../Thread_FTD_Coap_Multicast/Core/Inc/hw_conf.h | 34 +- .../Core/Src/stm32_lpm_if.c | 22 + .../Thread_SED_Coap_Multicast/Core/Inc/hw_conf.h | 34 +- .../Core/Src/stm32_lpm_if.c | 22 + .../DFU_Standalone/Core/Inc/stm32wbxx_hal_conf.h | 6 + .../USB_Device/DFU_Standalone/Core/Src/main.c | 5 + .../USB_Device/DFU_Standalone/DFU_Standalone.ioc | 20 +- .../HID_Standalone/Core/Inc/stm32wbxx_hal_conf.h | 6 + .../USB_Device/HID_Standalone/Core/Src/main.c | 5 + .../USB_Device/HID_Standalone/HID_Standalone.ioc | 20 +- .../Core/Inc/app_common.h | 114 + .../Core/Inc/app_conf.h | 352 + .../Core/Inc/app_entry.h | 68 + .../Zigbee_MeterId_Server_Coord/Core/Inc/hw_conf.h | 247 + .../Zigbee_MeterId_Server_Coord/Core/Inc/hw_if.h | 250 + .../Zigbee_MeterId_Server_Coord/Core/Inc/main.h | 71 + .../Core/Inc/stm32_lpm_if.h | 81 + .../Core/Inc/stm32wbxx_hal_conf.h | 353 + .../Core/Inc/stm32wbxx_it.h | 95 + .../Core/Inc/stm_logging.h | 55 + .../Core/Inc/utilities_conf.h | 68 + .../Core/Inc/vcp_conf.h | 54 + .../Core/Src/app_entry.c | 497 + .../Core/Src/hw_timerserver.c | 893 ++ .../Zigbee_MeterId_Server_Coord/Core/Src/hw_uart.c | 318 + .../Zigbee_MeterId_Server_Coord/Core/Src/main.c | 521 + .../Core/Src/stm32_lpm_if.c | 297 + .../Core/Src/stm32wbxx_hal_msp.c | 334 + .../Core/Src/stm32wbxx_it.c | 426 + .../Core/Src/stm_logging.c | 205 + .../Core/Src/system_stm32wbxx.c | 353 + .../Zigbee_MeterId_Server_Coord/EWARM/Project.eww | 7 + .../EWARM/Zigbee_MeterId_Server_Coord.ewd | 1419 ++ .../EWARM/Zigbee_MeterId_Server_Coord.ewp | 1310 ++ .../EWARM/startup_stm32wb55xx_cm4.s | 517 + .../EWARM/stm32wb55xx_flash_cm4.icf | 47 + .../STM32_WPAN/App/app_zigbee.c | 600 + .../STM32_WPAN/App/app_zigbee.h | 62 + .../STM32_WPAN/Target/hw_ipcc.c | 513 + .../Zigbee/Zigbee_MeterId_Server_Coord/readme.txt | 144 + .../Zigbee_OnOff_Client_Router/Core/Inc/app_conf.h | 5 +- .../Zigbee_OnOff_Client_Router/Core/Inc/hw_conf.h | 34 +- .../Core/Src/app_entry.c | 82 +- .../Core/Src/stm32_lpm_if.c | 22 + .../STM32_WPAN/App/app_zigbee.c | 88 +- .../STM32_WPAN/App/app_zigbee.h | 3 +- .../STM32_WPAN/Target/hw_ipcc.c | 50 +- .../Zigbee/Zigbee_OnOff_Client_Router/readme.txt | 13 - .../Zigbee_OnOff_Server_Coord/Core/Inc/app_conf.h | 6 +- .../Zigbee_OnOff_Server_Coord/Core/Inc/hw_conf.h | 34 +- .../Zigbee_OnOff_Server_Coord/Core/Src/app_entry.c | 93 +- .../Core/Src/stm32_lpm_if.c | 22 + .../EWARM/Zigbee_OnOff_Server_Coord.ewp | 10 +- .../STM32_WPAN/App/app_zigbee.c | 185 +- .../STM32_WPAN/App/app_zigbee.h | 3 +- .../STM32_WPAN/Target/hw_ipcc.c | 50 +- .../Zigbee/Zigbee_OnOff_Server_Coord/readme.txt | 13 - .../Core/Inc/app_common.h | 114 + .../Core/Inc/app_conf.h | 359 + .../Core/Inc/app_entry.h | 68 + .../Core/Inc/hw_conf.h | 247 + .../Core/Inc/hw_if.h | 250 + .../Core/Inc/main.h | 71 + .../Core/Inc/stm32_lpm_if.h | 81 + .../Core/Inc/stm32wbxx_hal_conf.h | 353 + .../Core/Inc/stm32wbxx_it.h | 95 + .../Core/Inc/stm_logging.h | 55 + .../Core/Inc/utilities_conf.h | 68 + .../Core/Inc/vcp_conf.h | 54 + .../Core/Src/app_entry.c | 498 + .../Core/Src/hw_timerserver.c | 893 ++ .../Core/Src/hw_uart.c | 318 + .../Core/Src/main.c | 521 + .../Core/Src/stm32_lpm_if.c | 297 + .../Core/Src/stm32wbxx_hal_msp.c | 334 + .../Core/Src/stm32wbxx_it.c | 426 + .../Core/Src/stm_logging.c | 205 + .../Core/Src/system_stm32wbxx.c | 353 + .../EWARM/Project.eww | 7 + .../EWARM/Zigbee_PowerProfile_Server_Router.ewd | 1419 ++ .../EWARM/Zigbee_PowerProfile_Server_Router.ewp | 1310 ++ .../EWARM/startup_stm32wb55xx_cm4.s | 517 + .../EWARM/stm32wb55xx_flash_cm4.icf | 47 + .../STM32_WPAN/App/app_zigbee.c | 919 ++ .../STM32_WPAN/App/app_zigbee.h | 62 + .../STM32_WPAN/Target/hw_ipcc.c | 513 + .../Zigbee_PowerProfile_Server_Router/readme.txt | 225 + .../P-NUCLEO-WB55.USBDongle/Release_Notes.html | 32 +- Projects/STM32CubeProjectsList.html | 432 +- .../Release_Notes.html | 819 -- .../STM32WB3x/Release_Notes.html | 244 + .../STM32WB3x/stm32wb3x_BLE_HCILayer_fw.bin | Bin 0 -> 96720 bytes .../STM32WB3x/stm32wb3x_BLE_Stack_full_fw.bin | Bin 0 -> 164872 bytes .../STM32WB3x/stm32wb3x_BLE_Stack_light_fw.bin | Bin 0 -> 107704 bytes .../STM32WB3x/stm32wb3x_Mac_802_15_4_fw.bin | Bin 0 -> 63300 bytes .../STM32WB3x/stm32wb3x_Thread_FTD_fw.bin | Bin 0 -> 347344 bytes .../STM32WB3x/stm32wb3x_Thread_MTD_fw.bin | Bin 0 -> 258216 bytes .../STM32WB5x/Release_Notes.html | 1095 ++ .../STM32WB5x/stm32wb5x_BLE_HCILayer_fw.bin | Bin 0 -> 96712 bytes .../STM32WB5x/stm32wb5x_BLE_Stack_full_fw.bin | Bin 0 -> 164864 bytes .../STM32WB5x/stm32wb5x_BLE_Stack_light_fw.bin | Bin 0 -> 107696 bytes .../STM32WB5x/stm32wb5x_BLE_Thread_fw.bin | Bin 0 -> 506700 bytes .../stm32wb5x_BLE_Zigbee_FFD_static_fw.bin | Bin 0 -> 490128 bytes .../STM32WB5x/stm32wb5x_FUS_fw.bin | Bin 0 -> 24344 bytes .../STM32WB5x/stm32wb5x_FUS_fw_1_0_2.bin | Bin 0 -> 24492 bytes .../STM32WB5x/stm32wb5x_Mac_802_15_4_fw.bin | Bin 0 -> 63460 bytes .../STM32WB5x/stm32wb5x_Thread_FTD_fw.bin | Bin 0 -> 347320 bytes .../STM32WB5x/stm32wb5x_Thread_MTD_fw.bin | Bin 0 -> 258192 bytes .../STM32WB5x/stm32wb5x_Zigbee_FFD_Full_fw.bin | Bin 0 -> 306580 bytes .../stm32wb5x_rfmonitor_phy802_15_4_fw.bin | Bin 0 -> 30096 bytes .../stm32wb5x_BLE_HCILayer_fw.bin | Bin 97080 -> 0 bytes .../stm32wb5x_BLE_Stack_fw.bin | Bin 165772 -> 0 bytes .../stm32wb5x_BLE_Thread_fw.bin | Bin 506060 -> 0 bytes .../stm32wb5x_FUS_fw.bin | Bin 24492 -> 0 bytes .../stm32wb5x_Mac_802_15_4_fw.bin | Bin 60928 -> 0 bytes .../stm32wb5x_Thread_FTD_fw.bin | Bin 346144 -> 0 bytes .../stm32wb5x_Thread_MTD_fw.bin | Bin 257016 -> 0 bytes .../stm32wb5x_Zigbee_FFD_Full_fw.bin | Bin 330020 -> 0 bytes .../stm32wb5x_rfmonitor_phy802_15_4_fw.bin | Bin 30096 -> 0 bytes README.md | 5 + Release_Notes.html | 583 +- .../EWARMv8_STM32WB5MMG_Support_V0.1.zip | Bin 0 -> 162520 bytes .../PC_Software/Keil.STM32WB5MMG_DFP.0.0.1.zip | Bin 0 -> 1710729 bytes Utilities/conf/Release_Notes.html | 46 +- Utilities/conf/utilities_conf_template.h | 80 +- Utilities/sequencer/Release_Notes.html | 56 +- Utilities/sequencer/stm32_seq.c | 2 + how_to_program_wireless_stacks.txt | 3 +- package.xml | 2 +- 4962 files changed, 1079160 insertions(+), 69459 deletions(-) create mode 100644 Drivers/BSP/NUCLEO-WB35CE/Release_Notes.html create mode 100644 Drivers/BSP/NUCLEO-WB35CE/_htmresc/mini-st.css create mode 100644 Drivers/BSP/NUCLEO-WB35CE/_htmresc/st_logo.png create mode 100644 Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c create mode 100644 Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.h create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb30xx.h create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb35xx.h create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb5mxx.h create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/linker/stm32wb30xx_flash_cm4.sct create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/linker/stm32wb35xx_flash_cm4.sct create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/linker/stm32wb5mxx_flash_cm4.sct create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/startup_stm32wb30xx_cm4.s create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/startup_stm32wb35xx_cm4.s create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/startup_stm32wb5mxx_cm4.s create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb30xx_flash_cm4.ld create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb35xx_flash_cm4.ld create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb5mxx_flash_cm4.ld create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb30xx_cm4.s create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb35xx_cm4.s create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb30xx_flash_cm4.icf create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb30xx_sram_cm4.icf create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb35xx_flash_cm4.icf create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb35xx_sram_cm4.icf create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb5mxx_flash_cm4.icf create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb5mxx_sram_cm4.icf create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/startup_stm32wb30xx_cm4.s create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/startup_stm32wb35xx_cm4.s create mode 100644 Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/startup_stm32wb5mxx_cm4.s create mode 100644 Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2s.h create mode 100644 Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2s.c create mode 100644 Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_GCC_DEBUG.a create mode 100644 Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_DEBUG.a create mode 100644 Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_DEBUG_NOD.a create mode 100644 Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_DEBUG_PROV.a create mode 100644 Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_NOD.a create mode 100644 Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_PROV.a create mode 100644 Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_Keil_DEBUG.lib create mode 100644 Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/light_client.h create mode 100644 Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/light_client.c create mode 100644 Middlewares/ST/STM32_WPAN/zigbee/stack/include/extras/zigbee.extras.h create mode 100644 Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/se/zcl.message.h create mode 100644 Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/security/zcl.ias_ace.h create mode 100644 Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/security/zcl.ias_wd.h create mode 100644 Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/security/zcl.ias_zone.h create mode 100644 Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.alarm.h create mode 100644 Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.ballast.config.h create mode 100644 Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.basic.h create mode 100644 Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.device.temp.h create mode 100644 Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.illum.meas.h create mode 100644 Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.meter.id.h create mode 100644 Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.occupancy.h create mode 100644 Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.power.profile.h create mode 100644 Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.press.meas.h create mode 100644 Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.temp.meas.h create mode 100644 Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.therm.ui.h create mode 100644 Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.time.h create mode 100644 Middlewares/ST/STM32_WPAN/zigbee/stack/include/zgp/zgp.proxybasic.h delete mode 100644 Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_dma_rtos_template.c create mode 100644 Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_dma_rtos_template_bspv1.c create mode 100644 Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_dma_rtos_template_bspv2.c delete mode 100644 Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_dma_template.c create mode 100644 Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_dma_template_bspv1.c create mode 100644 Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_dma_template_bspv2.c delete mode 100644 Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_template.c create mode 100644 Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_template_bspv1.c create mode 100644 Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_template_bspv2.c delete mode 100644 Middlewares/Third_Party/FatFs/src/drivers/sdram_diskio_template.c create mode 100644 Middlewares/Third_Party/FatFs/src/drivers/sdram_diskio_template_bspv1.c create mode 100644 Middlewares/Third_Party/FatFs/src/drivers/sdram_diskio_template_bspv2.c delete mode 100644 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os1.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/port.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/port.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/port.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.s create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/port.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.s create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s create mode 100644 Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h delete mode 100644 Middlewares/Third_Party/FreeRTOS/links_to_doc_pages_for_the_demo_projects.url delete mode 100644 Middlewares/Third_Party/FreeRTOS/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Binary/BLE_HeartRate.hex create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/app_common.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/app_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/app_debug.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/app_entry.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/hw_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/hw_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/utilities_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/app_debug.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/app_entry.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/hw_timerserver.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/hw_uart.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/stm32_lpm_if.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/BLE_HeartRate.ewd create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/BLE_HeartRate.ewp create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/app_ble.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/app_ble.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/ble_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/ble_dbg_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/dis_app.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/dis_app.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/hrs_app.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/hrs_app.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/FreeRTOSConfig.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_common.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_debug.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_entry.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/hw_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/hw_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/utilities_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/vcp_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/app_debug.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/app_entry.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/freertos_port.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_timerserver.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_uart.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32_lpm_if.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32wbxx_hal_timebase_tim.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/BLE_HeartRateFreeRTOS.ewd create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/BLE_HeartRateFreeRTOS.ewp create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/app_ble.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/app_ble.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/ble_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/ble_dbg_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/dis_app.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/dis_app.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/hrs_app.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/hrs_app.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Binary/BLE_HeartRate_ota.bin create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_common.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_debug.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_entry.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/hw_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/hw_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/utilities_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/app_debug.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/app_entry.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/hw_timerserver.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/hw_uart.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/stm32_lpm_if.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/BLE_HeartRate_ota.ewd create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/BLE_HeartRate_ota.ewp create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/stm32wb35xx_flash_cm4_ota.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/app_ble.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/app_ble.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/ble_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/ble_dbg_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/dis_app.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/dis_app.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/hrs_app.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/hrs_app.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Binary/BLE_Ota.hex create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/app_common.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/app_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/app_debug.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/app_entry.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/hw_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/hw_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/utilities_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/vcp_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/app_debug.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/app_entry.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/hw_timerserver.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/hw_uart.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/stm32_lpm_if.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/BLE_Ota.ewd create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/BLE_Ota.ewp create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/app_ble.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/app_ble.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/ble_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/ble_dbg_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/otas_app.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Binary/BLE_TransparentMode.hex create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/app_common.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/app_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/app_debug.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/app_entry.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/hw_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/hw_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/utilities_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/app_debug.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/app_entry.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/hw_timerserver.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/hw_uart.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/stm32_lpm_if.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/BLE_TransparentMode.ewd create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/BLE_TransparentMode.ewp create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/ble_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/ble_dbg_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/tm.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/tm.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Binary/BLE_p2pClient.hex create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/app_common.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/app_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/app_debug.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/app_entry.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/hw_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/hw_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/utilities_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/app_debug.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/app_entry.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/hw_timerserver.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/hw_uart.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/stm32_lpm_if.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/BLE_p2pClient.ewd create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/BLE_p2pClient.ewp create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/app_ble.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/app_ble.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/ble_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/ble_dbg_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/p2p_client_app.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/p2p_client_app.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Binary/BLE_p2pServer.hex create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/app_common.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/app_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/app_debug.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/app_entry.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/hw_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/hw_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/utilities_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/app_debug.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/app_entry.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/hw_timerserver.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/hw_uart.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/stm32_lpm_if.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/BLE_p2pServer.ewd create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/BLE_p2pServer.ewp create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/app_ble.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/app_ble.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/ble_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/ble_dbg_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/p2p_server_app.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/p2p_server_app.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Binary/BLE_p2pServer_ota.bin create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_common.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_debug.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_entry.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/hw_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/hw_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/utilities_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/app_debug.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/app_entry.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/hw_timerserver.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/hw_uart.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/stm32_lpm_if.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/BLE_p2pServer_ota.ewd create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/BLE_p2pServer_ota.ewp create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/stm32wb35xx_flash_cm4_ota.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/app_ble.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/app_ble.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/ble_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/ble_dbg_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/p2p_server_app.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/p2p_server_app.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/FatFs_uSD_Standalone.ewd create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/FatFs_uSD_Standalone.ewp create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/stm32wb35xx_sram_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/App/app_fatfs.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/App/app_fatfs.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/Target/ffconf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/Target/sd_diskio.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/Target/sd_diskio.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/MDK-ARM/FatFs_uSD_Standalone.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/MDK-ARM/FatFs_uSD_Standalone.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/FreeRTOS_Mutexes.ewd create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/FreeRTOS_Mutexes.ewp create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/stm32wb35xx_sram_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/FreeRTOS_Mutexes.ioc create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Inc/FreeRTOSConfig.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/MDK-ARM/FreeRTOS_Mutexes.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/MDK-ARM/FreeRTOS_Mutexes.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/app_freertos.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/stm32wbxx_hal_timebase_tim.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/FreeRTOS_Queues.ewd create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/FreeRTOS_Queues.ewp create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/stm32wb35xx_sram_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/FreeRTOS_Queues.ioc create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Inc/FreeRTOSConfig.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/MDK-ARM/FreeRTOS_Queues.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/MDK-ARM/FreeRTOS_Queues.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/app_freertos.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/stm32wbxx_hal_timebase_tim.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/FreeRTOS_Semaphore.ewd create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/FreeRTOS_Semaphore.ewp create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/stm32wb35xx_sram_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/FreeRTOS_Semaphore.ioc create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Inc/FreeRTOSConfig.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/MDK-ARM/FreeRTOS_Semaphore.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/MDK-ARM/FreeRTOS_Semaphore.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/app_freertos.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/stm32wbxx_hal_timebase_tim.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/app_common.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/app_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/app_entry.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/hw_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/hw_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/stm_logging.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/utilities_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/app_entry.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/hw_timerserver.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/hw_uart.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/stm32_lpm_if.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/stm_logging.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/Thread_Cli_Cmd.ewd create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/Thread_Cli_Cmd.ewp create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/STM32_WPAN/App/app_thread.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/STM32_WPAN/App/app_thread.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/HID_Standalone.ewd create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/HID_Standalone.ewp create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/stm32wb35xx_sram_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/HID_Standalone.ioc create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/MDK-ARM/HID_Standalone.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/MDK-ARM/HID_Standalone.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/App/usb_device.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/App/usb_device.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/App/usbd_desc.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/App/usbd_desc.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/Target/usbd_conf.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/Target/usbd_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/MSC_Standalone.ewd create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/MSC_Standalone.ewp create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/stm32wb35xx_sram_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MDK-ARM/MSC_Standalone.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MDK-ARM/MSC_Standalone.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MSC_Standalone.ioc create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usb_device.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usb_device.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usbd_desc.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usbd_desc.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usbd_storage_if.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usbd_storage_if.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/Target/usbd_conf.c create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/Target/usbd_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Adafruit_LCD_1_8_SD_Joystick.ioc create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/Adafruit_LCD_1_8_SD_Joystick.ewd create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/Adafruit_LCD_1_8_SD_Joystick.ewp create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/App/app_fatfs.c create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/App/app_fatfs.h create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/Target/ffconf.h create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/Target/sd_diskio.c create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/Target/sd_diskio.h create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/MDK-ARM/Adafruit_LCD_1_8_SD_Joystick.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/MDK-ARM/Adafruit_LCD_1_8_SD_Joystick.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/ADC_SingleConversion_TriggerSW_IT.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/ADC_SingleConversion_TriggerSW_IT.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/ADC_SingleConversion_TriggerSW_IT.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/ADC_SingleConversion_TriggerSW_IT.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/ADC_SingleConversion_TriggerSW_IT.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.settings/language.settings.xml create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/ADC_SingleConversion_TriggerTimer_DMA.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/ADC_SingleConversion_TriggerTimer_DMA.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/ADC_SingleConversion_TriggerTimer_DMA.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/MDK-ARM/ADC_SingleConversion_TriggerTimer_DMA.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/MDK-ARM/ADC_SingleConversion_TriggerTimer_DMA.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/BSP_Example.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/BSP_Example.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/BSP_Example.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/stm32wb35xx_sram_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/MDK-ARM/BSP_Example.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/MDK-ARM/BSP_Example.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/COMP_CompareGpioVsVrefInt_IT.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/COMP_CompareGpioVsVrefInt_IT.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/COMP_CompareGpioVsVrefInt_IT.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/stm32wb35xx_sram_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/MDK-ARM/COMP_CompareGpioVsVrefInt_IT.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/MDK-ARM/COMP_CompareGpioVsVrefInt_IT.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/CORTEXM_SysTick.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/CORTEXM_SysTick.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/CORTEXM_SysTick.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/MDK-ARM/CORTEXM_SysTick.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/MDK-ARM/CORTEXM_SysTick.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/CRC_Example.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/CRC_Example.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/CRC_Example.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/MDK-ARM/CRC_Example.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/MDK-ARM/CRC_Example.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/CRYP_DMA.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/CRYP_DMA.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/CRYP_DMA.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/stm32wb35xx_sram_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Expected_Results.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/CRYP_DMA.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/CRYP_DMA.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/Retarget.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/Serial.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/Serial.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/DMA_FLASHToRAM.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/DMA_MUXSYNC.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/DMA_MUXSYNC.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/DMA_MUXSYNC.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/MDK-ARM/DMA_MUXSYNC.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/MDK-ARM/DMA_MUXSYNC.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/DMA_MUX_RequestGen.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/DMA_MUX_RequestGen.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/DMA_MUX_RequestGen.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/MDK-ARM/DMA_MUX_RequestGen.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/MDK-ARM/DMA_MUX_RequestGen.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/FLASH_EraseProgram.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/FLASH_EraseProgram.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/FLASH_EraseProgram.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/MDK-ARM/FLASH_EraseProgram.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/MDK-ARM/FLASH_EraseProgram.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/FLASH_WriteProtection.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/FLASH_WriteProtection.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/FLASH_WriteProtection.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/MDK-ARM/FLASH_WriteProtection.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/MDK-ARM/FLASH_WriteProtection.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/GPIO_EXTI.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/GPIO_EXTI.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/GPIO_EXTI.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/MDK-ARM/GPIO_EXTI.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/MDK-ARM/GPIO_EXTI.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/GPIO_IOToggle.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/GPIO_IOToggle.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/GPIO_IOToggle.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/MDK-ARM/GPIO_IOToggle.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/MDK-ARM/GPIO_IOToggle.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/HAL_TimeBase.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/HAL_TimeBase.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/HAL_TimeBase.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/MDK-ARM/HAL_TimeBase.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/MDK-ARM/HAL_TimeBase.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/HAL_TimeBase_RTC_ALARM.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/HAL_TimeBase_RTC_ALARM.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/HAL_TimeBase_RTC_ALARM.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/MDK-ARM/HAL_TimeBase_RTC_ALARM.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/MDK-ARM/HAL_TimeBase_RTC_ALARM.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/stm32wbxx_hal_timebase_rtc_alarm.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/HAL_TimeBase_RTC_WKUP.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/HAL_TimeBase_RTC_WKUP.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/HAL_TimeBase_RTC_WKUP.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/MDK-ARM/HAL_TimeBase_RTC_WKUP.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/MDK-ARM/HAL_TimeBase_RTC_WKUP.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/stm32wbxx_hal_timebase_rtc_wakeup.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/HAL_TimeBase_TIM.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/HAL_TimeBase_TIM.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/HAL_TimeBase_TIM.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/MDK-ARM/HAL_TimeBase_TIM.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/MDK-ARM/HAL_TimeBase_TIM.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/stm32wbxx_hal_timebase_tim.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/I2C_TwoBoards_ComDMA.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/I2C_TwoBoards_ComDMA.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/I2C_TwoBoards_ComDMA.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/MDK-ARM/I2C_TwoBoards_ComDMA.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/MDK-ARM/I2C_TwoBoards_ComDMA.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/I2C_TwoBoards_ComIT.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/I2C_TwoBoards_ComIT.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/I2C_TwoBoards_ComIT.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/MDK-ARM/I2C_TwoBoards_ComIT.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/MDK-ARM/I2C_TwoBoards_ComIT.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/I2C_WakeUpFromStop2.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/I2C_WakeUpFromStop2.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/I2C_WakeUpFromStop2.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/MDK-ARM/I2C_WakeUpFromStop2.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/MDK-ARM/I2C_WakeUpFromStop2.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/I2S/I2S_Audio/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/IWDG_WindowMode.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/IWDG_WindowMode.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/IWDG_WindowMode.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/MDK-ARM/IWDG_WindowMode.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/MDK-ARM/IWDG_WindowMode.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/LPTIM_PWMExternalClock.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/LPTIM_PWMExternalClock.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/LPTIM_PWMExternalClock.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/MDK-ARM/LPTIM_PWMExternalClock.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/MDK-ARM/LPTIM_PWMExternalClock.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/LPTIM_PulseCounter.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/LPTIM_PulseCounter.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/LPTIM_PulseCounter.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/MDK-ARM/LPTIM_PulseCounter.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/MDK-ARM/LPTIM_PulseCounter.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/stm32wb35xx_sram_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/SigGen.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/prime256v1.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/PKA_ECDSA_Sign.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/SigGen.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/SigGen.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/prime256v1.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/PKA_ECDSA_Verify_IT.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/PKA_ECDSA_Verify_IT.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/stm32wb35xx_sram_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/SigVer.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/prime256v1.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/MDK-ARM/PKA_ECDSA_Verify_IT.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/MDK-ARM/PKA_ECDSA_Verify_IT.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/PKA_ECDSA_Verify_IT.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/SigVer.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/SigVer.rsp create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/prime256v1.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/PWR_LPRUN.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/PWR_LPRUN.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/MDK-ARM/PWR_LPRUN.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/MDK-ARM/PWR_LPRUN.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/PWR_LPRUN.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/PWR_LPSLEEP.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/PWR_LPSLEEP.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/MDK-ARM/PWR_LPSLEEP.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/MDK-ARM/PWR_LPSLEEP.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/PWR_LPSLEEP.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/PWR_PVD.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/PWR_PVD.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/MDK-ARM/PWR_PVD.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/MDK-ARM/PWR_PVD.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/PWR_PVD.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/PWR_STANDBY_RTC.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/PWR_STANDBY_RTC.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/MDK-ARM/PWR_STANDBY_RTC.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/MDK-ARM/PWR_STANDBY_RTC.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/PWR_STANDBY_RTC.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/PWR_STOP2_RTC.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/PWR_STOP2_RTC.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/MDK-ARM/PWR_STOP2_RTC.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/MDK-ARM/PWR_STOP2_RTC.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/PWR_STOP2_RTC.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/QSPI_ReadWrite_DMA.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/QSPI_ReadWrite_DMA.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/MDK-ARM/QSPI_ReadWrite_DMA.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/MDK-ARM/QSPI_ReadWrite_DMA.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/QSPI_ReadWrite_DMA.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/RCC_ClockConfig.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/RCC_ClockConfig.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/MDK-ARM/RCC_ClockConfig.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/MDK-ARM/RCC_ClockConfig.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/RCC_ClockConfig.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/RNG_MultiRNG.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/RNG_MultiRNG.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/MDK-ARM/RNG_MultiRNG.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/MDK-ARM/RNG_MultiRNG.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/RNG_MultiRNG.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/.settings/language.settings.xml create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/RTC_Alarm.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/RTC_Alarm.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/MDK-ARM/RTC_Alarm.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/MDK-ARM/RTC_Alarm.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/RTC_Alarm.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/RTC_Tamper.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/RTC_Tamper.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/MDK-ARM/RTC_Tamper.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/MDK-ARM/RTC_Tamper.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/RTC_Tamper.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/SPI_FullDuplex_ComDMA_Master.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/SPI_FullDuplex_ComDMA_Master.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/MDK-ARM/SPI_FullDuplex_ComDMA_Master.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/MDK-ARM/SPI_FullDuplex_ComDMA_Master.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/SPI_FullDuplex_ComDMA_Master.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/SPI_FullDuplex_ComDMA_Slave.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/SPI_FullDuplex_ComDMA_Slave.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/MDK-ARM/SPI_FullDuplex_ComDMA_Slave.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/MDK-ARM/SPI_FullDuplex_ComDMA_Slave.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/SPI_FullDuplex_ComDMA_Slave.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/TIM_OCActive.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/TIM_OCActive.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/MDK-ARM/TIM_OCActive.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/MDK-ARM/TIM_OCActive.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/TIM_OCActive.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/TIM_PWMInput.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/TIM_PWMOutput.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/TIM_PWMOutput.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/MDK-ARM/TIM_PWMOutput.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/MDK-ARM/TIM_PWMOutput.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/TIM_PWMOutput.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/TSC/TSC_BasicAcquisition_Interrupt/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/UART_HyperTerminal_DMA.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/UART_HyperTerminal_DMA.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/MDK-ARM/UART_HyperTerminal_DMA.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/MDK-ARM/UART_HyperTerminal_DMA.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/UART_HyperTerminal_DMA.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/UART_HyperTerminal_IT.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/UART_HyperTerminal_IT.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/MDK-ARM/UART_HyperTerminal_IT.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/MDK-ARM/UART_HyperTerminal_IT.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/UART_HyperTerminal_IT.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/UART_Printf.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/UART_Printf.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/MDK-ARM/UART_Printf.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/MDK-ARM/UART_Printf.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/UART_Printf.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/WWDG_Example.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/WWDG_Example.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/MDK-ARM/WWDG_Example.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/MDK-ARM/WWDG_Example.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/.settings/language.settings.xml create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/WWDG_Example.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/ADC_AnalogWatchdog_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/ADC_AnalogWatchdog_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/ADC_AnalogWatchdog_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/MDK-ARM/ADC_AnalogWatchdog_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/MDK-ARM/ADC_AnalogWatchdog_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/ADC_Oversampling_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/ADC_Oversampling_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/ADC_Oversampling_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/MDK-ARM/ADC_Oversampling_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/MDK-ARM/ADC_Oversampling_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/ADC_SingleConversion_TriggerSW_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/ADC_SingleConversion_TriggerSW_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/ADC_SingleConversion_TriggerSW_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/MDK-ARM/ADC_SingleConversion_TriggerSW_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/MDK-ARM/ADC_SingleConversion_TriggerSW_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/COMP_CompareGpioVsVrefInt_Window_IT_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/COMP_CompareGpioVsVrefInt_Window_IT_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/COMP_CompareGpioVsVrefInt_Window_IT_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/stm32wb35xx_sram_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/MDK-ARM/COMP_CompareGpioVsVrefInt_Window_IT_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/MDK-ARM/COMP_CompareGpioVsVrefInt_Window_IT_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/CRC_CalculateAndCheck.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/CRC_CalculateAndCheck.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/CRC_CalculateAndCheck.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/MDK-ARM/CRC_CalculateAndCheck.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/MDK-ARM/CRC_CalculateAndCheck.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/DMA_CopyFromFlashToMemory_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/DMA_CopyFromFlashToMemory_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/DMA_CopyFromFlashToMemory_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/MDK-ARM/DMA_CopyFromFlashToMemory_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/MDK-ARM/DMA_CopyFromFlashToMemory_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/EXTI_ToggleLedOnIT_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/EXTI_ToggleLedOnIT_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EXTI_ToggleLedOnIT_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/MDK-ARM/EXTI_ToggleLedOnIT_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/MDK-ARM/EXTI_ToggleLedOnIT_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/GPIO_InfiniteLedToggling_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/GPIO_InfiniteLedToggling_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/GPIO_InfiniteLedToggling_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/MDK-ARM/GPIO_InfiniteLedToggling_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/MDK-ARM/GPIO_InfiniteLedToggling_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/HSEM_DualProcess_IT.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/HSEM_DualProcess_IT.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/stm32wb35xx_sram_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/HSEM_DualProcess_IT.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/MDK-ARM/HSEM_DualProcess_IT.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/MDK-ARM/HSEM_DualProcess_IT.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/MDK-ARM/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/MDK-ARM/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/MDK-ARM/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/MDK-ARM/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/IWDG_RefreshUntilUserEvent_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/IWDG_RefreshUntilUserEvent_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/IWDG_RefreshUntilUserEvent_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/MDK-ARM/IWDG_RefreshUntilUserEvent_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/MDK-ARM/IWDG_RefreshUntilUserEvent_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/LPTIM_PulseCounter_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/LPTIM_PulseCounter_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/LPTIM_PulseCounter_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/MDK-ARM/LPTIM_PulseCounter_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/MDK-ARM/LPTIM_PulseCounter_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/LPUART_WakeUpFromStop2_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/LPUART_WakeUpFromStop2_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/LPUART_WakeUpFromStop2_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/MDK-ARM/LPUART_WakeUpFromStop2_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/MDK-ARM/LPUART_WakeUpFromStop2_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/stm32wb35xx_sram_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/SigGen.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/prime256v1.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/PKA_ECDSA_Sign.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/SigGen.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/SigGen.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/prime256v1.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/PWR_EnterStandbyMode.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/PWR_EnterStandbyMode.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/MDK-ARM/PWR_EnterStandbyMode.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/MDK-ARM/PWR_EnterStandbyMode.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/PWR_EnterStandbyMode.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/PWR_EnterStopMode.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/PWR_EnterStopMode.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/MDK-ARM/PWR_EnterStopMode.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/MDK-ARM/PWR_EnterStopMode.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/PWR_EnterStopMode.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/PWR_OptimizedRunMode.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/PWR_OptimizedRunMode.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/MDK-ARM/PWR_OptimizedRunMode.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/MDK-ARM/PWR_OptimizedRunMode.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/PWR_OptimizedRunMode.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/RCC_UseHSI_PLLasSystemClock.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/RCC_UseHSI_PLLasSystemClock.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/MDK-ARM/RCC_UseHSI_PLLasSystemClock.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/MDK-ARM/RCC_UseHSI_PLLasSystemClock.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/RCC_UseHSI_PLLasSystemClock.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/RNG_GenerateRandomNumbers_IT.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/RNG_GenerateRandomNumbers_IT.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/MDK-ARM/RNG_GenerateRandomNumbers_IT.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/MDK-ARM/RNG_GenerateRandomNumbers_IT.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/RNG_GenerateRandomNumbers_IT.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/RTC_ExitStandbyWithWakeUpTimer_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/RTC_ExitStandbyWithWakeUpTimer_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/MDK-ARM/RTC_ExitStandbyWithWakeUpTimer_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/MDK-ARM/RTC_ExitStandbyWithWakeUpTimer_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/RTC_ExitStandbyWithWakeUpTimer_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/SPI_TwoBoards_FullDuplex_DMA_Master_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/SPI_TwoBoards_FullDuplex_DMA_Master_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/MDK-ARM/SPI_TwoBoards_FullDuplex_DMA_Master_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/MDK-ARM/SPI_TwoBoards_FullDuplex_DMA_Master_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/SPI_TwoBoards_FullDuplex_DMA_Master_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/MDK-ARM/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/MDK-ARM/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/TIM_TimeBase_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/TIM_TimeBase_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/MDK-ARM/TIM_TimeBase_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/MDK-ARM/TIM_TimeBase_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/TIM_TimeBase_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/USART_Communication_Rx_IT_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/USART_Communication_Rx_IT_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/MDK-ARM/USART_Communication_Rx_IT_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/MDK-ARM/USART_Communication_Rx_IT_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/USART_Communication_Rx_IT_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/USART_Communication_Tx_IT_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/USART_Communication_Tx_IT_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/MDK-ARM/USART_Communication_Tx_IT_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/MDK-ARM/USART_Communication_Tx_IT_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/USART_Communication_Tx_IT_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/UTILS_ReadDeviceInfo.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/UTILS_ReadDeviceInfo.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/MDK-ARM/UTILS_ReadDeviceInfo.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/MDK-ARM/UTILS_ReadDeviceInfo.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/UTILS_ReadDeviceInfo.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/WWDG_RefreshUntilUserEvent_Init.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/WWDG_RefreshUntilUserEvent_Init.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/MDK-ARM/WWDG_RefreshUntilUserEvent_Init.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/MDK-ARM/WWDG_RefreshUntilUserEvent_Init.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/WWDG_RefreshUntilUserEvent_Init.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/ADC_SingleConversion_TriggerSW_IT.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/ADC_SingleConversion_TriggerSW_IT.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/ADC_SingleConversion_TriggerSW_IT.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/ADC_SingleConversion_TriggerSW_IT.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/ADC_SingleConversion_TriggerSW_IT.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/DMA_FLASHToRAM.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/I2C_OneBoard_ComSlave7_10bits_IT.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/I2C_OneBoard_ComSlave7_10bits_IT.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/I2C_OneBoard_ComSlave7_10bits_IT.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/MDK-ARM/I2C_OneBoard_ComSlave7_10bits_IT.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/MDK-ARM/I2C_OneBoard_ComSlave7_10bits_IT.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/PWR_STOP1.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/PWR_STOP1.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/MDK-ARM/PWR_STOP1.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/MDK-ARM/PWR_STOP1.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/PWR_STOP1.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/SPI_HalfDuplex_ComPollingIT_Master.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/SPI_HalfDuplex_ComPollingIT_Master.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/MDK-ARM/SPI_HalfDuplex_ComPollingIT_Master.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/MDK-ARM/SPI_HalfDuplex_ComPollingIT_Master.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/SPI_HalfDuplex_ComPollingIT_Master.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/SPI_HalfDuplex_ComPollingIT_Slave.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/SPI_HalfDuplex_ComPollingIT_Slave.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/MDK-ARM/SPI_HalfDuplex_ComPollingIT_Slave.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/MDK-ARM/SPI_HalfDuplex_ComPollingIT_Slave.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/SPI_HalfDuplex_ComPollingIT_Slave.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/TIM_PWMInput.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/UART_HyperTerminal_IT.ewd create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/UART_HyperTerminal_IT.ewp create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/MDK-ARM/UART_HyperTerminal_IT.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/MDK-ARM/UART_HyperTerminal_IT.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/UART_HyperTerminal_IT.ioc create mode 100644 Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Release_Notes.html create mode 100644 Projects/NUCLEO-WB35CE/Templates/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Templates/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Templates/EWARM/Templates.ewd create mode 100644 Projects/NUCLEO-WB35CE/Templates/EWARM/Templates.ewp create mode 100644 Projects/NUCLEO-WB35CE/Templates/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Templates/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Templates/EWARM/stm32wb35xx_sram_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Templates/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Templates/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/NUCLEO-WB35CE/Templates/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Templates/MDK-ARM/Templates.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Templates/MDK-ARM/Templates.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Templates/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Templates/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Templates/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Templates/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/NUCLEO-WB35CE/Templates/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Templates/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Templates/Templates.ioc create mode 100644 Projects/NUCLEO-WB35CE/Templates/readme.txt create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/.extSettings create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/EWARM/Project.eww create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/EWARM/Templates_LL.ewd create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/EWARM/Templates_LL.ewp create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/EWARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/EWARM/stm32wb35xx_flash_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/EWARM/stm32wb35xx_sram_cm4.icf create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/Inc/main.h create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/Inc/stm32_assert.h create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/Inc/stm32wbxx_it.h create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/MDK-ARM/Templates_LL.uvoptx create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/MDK-ARM/Templates_LL.uvprojx create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/MDK-ARM/startup_stm32wb35xx_cm4.s create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/MDK-ARM/stm32wb35xx_flash_cm4.sct create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/.cproject create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/.project create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/Application/User/syscalls.c create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/Application/User/sysmem.c create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/STM32WB35CEUX_FLASH.ld create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/Src/main.c create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/Src/stm32wbxx_it.c create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/Src/system_stm32wbxx.c create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/Templates_LL.ioc create mode 100644 Projects/NUCLEO-WB35CE/Templates_LL/readme.txt create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Inc/hw_flash.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Inc/lp_timer.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/hw_flash.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/lp_timer.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_config_client.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_config_client.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_generic_client.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_generic_client.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light_client.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light_client.h delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/BLE_MeshLightingDemo/.cproject delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/BLE_MeshLightingDemo/.project delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/BLE_MeshLightingDemo/stm32wb55xx_flash_cm4.ld create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/Lighting_Node/.cproject create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/Lighting_Node/.project create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/Lighting_Node/stm32wb55xx_flash_cm4.ld create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pClient/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pClient/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pRouteur/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pRouteur/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pServer/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pServer/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pServer_ota/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Inc/app_common.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Inc/app_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Inc/app_entry.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Inc/hw_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Inc/hw_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Inc/main.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Inc/stm_logging.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Inc/utilities_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Src/app_entry.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Src/hw_timerserver.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Src/hw_uart.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Src/main.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Src/stm32_lpm_if.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Src/stm32wbxx_it.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Src/stm_logging.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/Core/Src/system_stm32wbxx.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/EWARM/ble_zigbee_static.ewd create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/EWARM/ble_zigbee_static.ewp create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/EWARM/ble_zigbee_static.eww create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/EWARM/startup_stm32wb55xx_cm4.s create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/EWARM/stm32wb55xx_flash_cm4.icf create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/STM32_WPAN/App/app_ble.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/STM32_WPAN/App/app_ble.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/STM32_WPAN/App/app_zigbee.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/STM32_WPAN/App/app_zigbee.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/STM32_WPAN/App/ble_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/STM32_WPAN/App/ble_dbg_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/STM32_WPAN/App/p2p_server_app.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/STM32_WPAN/App/p2p_server_app.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Zigbee/BLE_Zigbee_Static/readme.txt create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/Core/inc/app_common.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/Core/inc/app_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/Core/inc/app_entry.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/Core/inc/hw_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/Core/inc/hw_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/Core/inc/main.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/Core/inc/stm32_lpm_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/Core/inc/stm32wbxx_hal_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/Core/inc/stm32wbxx_it.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/Core/inc/utilities_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/Core/src/app_entry.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/Core/src/main.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/Core/src/stm32_lpm_if.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/Core/src/stm32wbxx_hal_msp.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/Core/src/stm32wbxx_it.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/Core/src/system_stm32wbxx.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/EWARM/Mac_802_15_4_LPM_Periodic_Transmit.ewd create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/EWARM/Mac_802_15_4_LPM_Periodic_Transmit.ewp create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/EWARM/Mac_802_15_4_LPM_Periodic_Transmit.eww create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/EWARM/startup_stm32wb55xx_cm4.s create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/EWARM/stm32wb55xx_flash_cm4.icf create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/STM32_WPAN/app/app_lpm_transmit_mac_802_15_4.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/STM32_WPAN/app/app_lpm_transmit_mac_802_15_4.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/STM32_WPAN/app/app_lpm_transmit_mac_802_15_4_process.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/STM32_WPAN/app/app_lpm_transmit_mac_802_15_4_process.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/STM32_WPAN/target/hw_ipcc.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Mac_802_15_4/Mac_802_15_4_LPM_Periodic_Transmit/readme.txt delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/app_common.h delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/app_conf.h delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/app_entry.h delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/hw_conf.h delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/hw_if.h delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/main.h delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/stm32_lpm_if.h delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/stm32wbxx_hal_conf.h delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/stm32wbxx_it.h delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/stm_logging.h delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/utilities_conf.h delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/vcp_conf.h delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Src/app_entry.c delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Src/hw_timerserver.c delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Src/hw_uart.c delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Src/main.c delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Src/stm32_lpm_if.c delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Src/stm32wbxx_hal_msp.c delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Src/stm32wbxx_it.c delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Src/stm_logging.c delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Core/Src/system_stm32wbxx.c delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/EWARM/Project.eww delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/EWARM/Thread_Coap_DataTransfer.ewd delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/EWARM/Thread_Coap_DataTransfer.ewp delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/EWARM/startup_stm32wb55xx_cm4.s delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/EWARM/stm32wb55xx_flash_cm4.icf delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/MDK-ARM/Thread_Coap_DataTransfer.uvoptx delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/MDK-ARM/Thread_Coap_DataTransfer.uvprojx delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/MDK-ARM/startup_stm32wb55xx_cm4.s delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/MDK-ARM/stm32wb55xx_flash_cm4.sct delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/STM32_WPAN/App/app_thread.c delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/STM32_WPAN/App/app_thread.h delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/STM32_WPAN/App/data_transfer.h delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/STM32_WPAN/Target/hw_ipcc.c delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/SW4STM32/P-NUCLEO-WB55.Nucleo_Thread_Coap_DataTransfer/.cproject delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/SW4STM32/P-NUCLEO-WB55.Nucleo_Thread_Coap_DataTransfer/.project delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/SW4STM32/P-NUCLEO-WB55.Nucleo_Thread_Coap_DataTransfer/stm32wb55xx_flash_cm4.ld delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/SW4STM32/startup_stm32wb55xx_cm4.s delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/SW4STM32/syscalls.c delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/Thread_Coap_DataTransfer.ioc delete mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_Coap_DataTransfer/readme.txt create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_SED_Coap_FreeRTOS/Core/Src/app_freertos.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Inc/app_common.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Inc/app_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Inc/app_entry.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Inc/hw_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Inc/hw_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Inc/main.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Inc/stm_logging.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Inc/utilities_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Src/app_entry.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Src/hw_timerserver.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Src/hw_uart.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Src/main.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Src/stm32_lpm_if.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Src/stm32wbxx_it.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Src/stm_logging.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/Core/Src/system_stm32wbxx.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/EWARM/Project.eww create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/EWARM/Zigbee_DevTemp_Client_Router.ewd create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/EWARM/Zigbee_DevTemp_Client_Router.ewp create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/EWARM/startup_stm32wb55xx_cm4.s create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/EWARM/stm32wb55xx_flash_cm4.icf create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/STM32_WPAN/App/app_zigbee.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/STM32_WPAN/App/app_zigbee.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Client_Router/readme.txt create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Inc/app_common.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Inc/app_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Inc/app_entry.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Inc/hw_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Inc/hw_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Inc/main.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Inc/stm_logging.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Inc/utilities_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Src/app_entry.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Src/hw_timerserver.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Src/hw_uart.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Src/main.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Src/stm32_lpm_if.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Src/stm32wbxx_it.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Src/stm_logging.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/Core/Src/system_stm32wbxx.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/EWARM/Project.eww create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/EWARM/Zigbee_DevTemp_Server_Coord.ewd create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/EWARM/Zigbee_DevTemp_Server_Coord.ewp create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/EWARM/startup_stm32wb55xx_cm4.s create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/EWARM/stm32wb55xx_flash_cm4.icf create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/STM32_WPAN/App/app_zigbee.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/STM32_WPAN/App/app_zigbee.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_DevTemp_Server_Coord/readme.txt create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Inc/app_common.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Inc/app_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Inc/app_entry.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Inc/hw_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Inc/hw_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Inc/main.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Inc/stm_logging.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Inc/utilities_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Src/app_entry.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Src/hw_timerserver.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Src/hw_uart.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Src/main.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Src/stm32_lpm_if.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Src/stm32wbxx_it.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Src/stm_logging.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/Core/Src/system_stm32wbxx.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/EWARM/Project.eww create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/EWARM/Zigbee_MeterId_Client_Router.ewd create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/EWARM/Zigbee_MeterId_Client_Router.ewp create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/EWARM/startup_stm32wb55xx_cm4.s create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/EWARM/stm32wb55xx_flash_cm4.icf create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/STM32_WPAN/App/app_zigbee.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/STM32_WPAN/App/app_zigbee.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Client_Router/readme.txt create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/app_common.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/app_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/app_entry.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/hw_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/hw_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/main.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/stm_logging.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/utilities_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Src/app_entry.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Src/hw_timerserver.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Src/hw_uart.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Src/main.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Src/stm32_lpm_if.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Src/stm32wbxx_it.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Src/stm_logging.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Src/system_stm32wbxx.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/EWARM/Project.eww create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/EWARM/Zigbee_MeterId_Server_Coord.ewd create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/EWARM/Zigbee_MeterId_Server_Coord.ewp create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/EWARM/startup_stm32wb55xx_cm4.s create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/EWARM/stm32wb55xx_flash_cm4.icf create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/STM32_WPAN/App/app_zigbee.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/STM32_WPAN/App/app_zigbee.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_MeterId_Server_Coord/readme.txt create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Inc/app_common.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Inc/app_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Inc/app_entry.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Inc/hw_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Inc/hw_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Inc/main.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Inc/stm_logging.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Inc/utilities_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Src/app_entry.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Src/hw_timerserver.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Src/hw_uart.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Src/main.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Src/stm32_lpm_if.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Src/stm32wbxx_it.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Src/stm_logging.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/Core/Src/system_stm32wbxx.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/EWARM/Project.eww create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/EWARM/Zigbee_PowerProfile_Client_Coord.ewd create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/EWARM/Zigbee_PowerProfile_Client_Coord.ewp create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/EWARM/startup_stm32wb55xx_cm4.s create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/EWARM/stm32wb55xx_flash_cm4.icf create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/STM32_WPAN/App/app_zigbee.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/STM32_WPAN/App/app_zigbee.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Client_Coord/readme.txt create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/app_common.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/app_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/app_entry.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/hw_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/hw_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/main.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/stm_logging.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/utilities_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Src/app_entry.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Src/hw_timerserver.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Src/hw_uart.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Src/main.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Src/stm32_lpm_if.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Src/stm32wbxx_it.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Src/stm_logging.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Src/system_stm32wbxx.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/EWARM/Project.eww create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/EWARM/Zigbee_PowerProfile_Server_Router.ewd create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/EWARM/Zigbee_PowerProfile_Server_Router.ewp create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/EWARM/startup_stm32wb55xx_cm4.s create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/EWARM/stm32wb55xx_flash_cm4.icf create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/STM32_WPAN/App/app_zigbee.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/STM32_WPAN/App/app_zigbee.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/readme.txt create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Inc/app_common.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Inc/app_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Inc/app_entry.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Inc/hw_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Inc/hw_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Inc/main.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Inc/stm_logging.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Inc/utilities_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Src/app_entry.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Src/hw_timerserver.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Src/hw_uart.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Src/main.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Src/stm32_lpm_if.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Src/stm32wbxx_it.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Src/stm_logging.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/Core/Src/system_stm32wbxx.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/EWARM/Project.eww create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/EWARM/Zigbee_PressMeas_Client_Router.ewd create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/EWARM/Zigbee_PressMeas_Client_Router.ewp create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/EWARM/startup_stm32wb55xx_cm4.s create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/EWARM/stm32wb55xx_flash_cm4.icf create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/STM32_WPAN/App/app_zigbee.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/STM32_WPAN/App/app_zigbee.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Client_Router/readme.txt create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Inc/app_common.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Inc/app_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Inc/app_entry.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Inc/hw_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Inc/hw_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Inc/main.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Inc/stm_logging.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Inc/utilities_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Src/app_entry.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Src/hw_timerserver.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Src/hw_uart.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Src/main.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Src/stm32_lpm_if.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Src/stm32wbxx_it.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Src/stm_logging.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/Core/Src/system_stm32wbxx.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/EWARM/Project.eww create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/EWARM/Zigbee_PressMeas_Server_Coord.ewd create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/EWARM/Zigbee_PressMeas_Server_Coord.ewp create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/EWARM/startup_stm32wb55xx_cm4.s create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/EWARM/stm32wb55xx_flash_cm4.icf create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/STM32_WPAN/App/app_zigbee.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/STM32_WPAN/App/app_zigbee.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_PressMeas_Server_Coord/readme.txt create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Inc/app_common.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Inc/app_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Inc/app_entry.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Inc/hw_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Inc/hw_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Inc/main.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Inc/stm_logging.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Inc/utilities_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Src/app_entry.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Src/hw_timerserver.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Src/hw_uart.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Src/main.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Src/stm32_lpm_if.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Src/stm32wbxx_it.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Src/stm_logging.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/Core/Src/system_stm32wbxx.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/EWARM/Project.eww create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/EWARM/Zigbee_SE_Msg_Client_Coord.ewd create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/EWARM/Zigbee_SE_Msg_Client_Coord.ewp create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/EWARM/startup_stm32wb55xx_cm4.s create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/EWARM/stm32wb55xx_flash_cm4.icf create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/STM32_WPAN/App/app_zigbee.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/STM32_WPAN/App/app_zigbee.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Client_Coord/readme.txt create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Inc/app_common.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Inc/app_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Inc/app_entry.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Inc/hw_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Inc/hw_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Inc/main.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Inc/stm_logging.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Inc/utilities_conf.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Src/app_entry.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Src/hw_timerserver.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Src/hw_uart.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Src/main.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Src/stm32_lpm_if.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Src/stm32wbxx_it.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Src/stm_logging.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/Core/Src/system_stm32wbxx.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/EWARM/Project.eww create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/EWARM/Zigbee_SE_Msg_Server_Router.ewd create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/EWARM/Zigbee_SE_Msg_Server_Router.ewp create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/EWARM/startup_stm32wb55xx_cm4.s create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/EWARM/stm32wb55xx_flash_cm4.icf create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/STM32_WPAN/App/app_zigbee.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/STM32_WPAN/App/app_zigbee.h create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/P-NUCLEO-WB55.Nucleo/Applications/Zigbee/Zigbee_SE_Msg_Server_Router/readme.txt create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_HeartRate/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_HeartRate/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_MeshLightingDemo/Core/Inc/hw_flash.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_MeshLightingDemo/Core/Inc/lp_timer.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_MeshLightingDemo/Core/Src/hw_flash.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_MeshLightingDemo/Core/Src/lp_timer.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_config_client.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_config_client.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_generic_client.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_generic_client.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light_client.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light_client.h delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/BLE_Lighting_Demo/.cproject delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/BLE_Lighting_Demo/.project delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/BLE_Lighting_Demo/stm32wb55xx_flash_cm4.ld create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/Lighting_Node/.cproject create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/Lighting_Node/.project create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/Lighting_Node/stm32wb55xx_flash_cm4.ld create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_TransparentModeVCP/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_TransparentModeVCP/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_p2pClient/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_p2pClient/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_p2pRouteur/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_p2pRouteur/Core/Src/app_debug.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_p2pServer/Core/Inc/app_debug.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/BLE/BLE_p2pServer/Core/Src/app_debug.c delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/app_common.h delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/app_conf.h delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/app_entry.h delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/hw_conf.h delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/hw_if.h delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/main.h delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/stm32_lpm_if.h delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/stm32wbxx_hal_conf.h delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/stm32wbxx_it.h delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/stm_logging.h delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/utilities_conf.h delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Inc/vcp_conf.h delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Src/app_entry.c delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Src/hw_timerserver.c delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Src/hw_uart.c delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Src/main.c delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Src/stm32_lpm_if.c delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Src/stm32wbxx_it.c delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Src/stm_logging.c delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/Core/Src/system_stm32wbxx.c delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/EWARM/Project.ewd delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/EWARM/Project.ewp delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/EWARM/Project.eww delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/EWARM/startup_stm32wb55xx_cm4.s delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/EWARM/stm32wb55xx_flash_cm4.icf delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/MDK-ARM/Project.uvoptx delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/MDK-ARM/Project.uvprojx delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/MDK-ARM/startup_stm32wb55xx_cm4.s delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/MDK-ARM/stm32wb55xx_flash_cm4.sct delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/STM32_WPAN/App/app_thread.c delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/STM32_WPAN/App/app_thread.h delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/STM32_WPAN/App/data_transfer.h delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/STM32_WPAN/Target/hw_ipcc.c delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/SW4STM32/STM32WBxx_USBD_Thread_Coap_DataTransfer/.cproject delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/SW4STM32/STM32WBxx_USBD_Thread_Coap_DataTransfer/.project delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/SW4STM32/STM32WBxx_USBD_Thread_Coap_DataTransfer/stm32wb55xx_flash_cm4.ld delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/SW4STM32/startup_stm32wb55xx_cm4.s delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/SW4STM32/syscalls.c delete mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_Coap_DataTransfer/readme.txt create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/app_common.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/app_conf.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/app_entry.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/hw_conf.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/hw_if.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/main.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/stm_logging.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/utilities_conf.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Inc/vcp_conf.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Src/app_entry.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Src/hw_timerserver.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Src/hw_uart.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Src/main.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Src/stm32_lpm_if.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Src/stm32wbxx_it.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Src/stm_logging.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/Core/Src/system_stm32wbxx.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/EWARM/Project.eww create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/EWARM/Zigbee_MeterId_Server_Coord.ewd create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/EWARM/Zigbee_MeterId_Server_Coord.ewp create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/EWARM/startup_stm32wb55xx_cm4.s create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/EWARM/stm32wb55xx_flash_cm4.icf create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/STM32_WPAN/App/app_zigbee.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/STM32_WPAN/App/app_zigbee.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_MeterId_Server_Coord/readme.txt create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/app_common.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/app_conf.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/app_entry.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/hw_conf.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/hw_if.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/main.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/stm32_lpm_if.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/stm32wbxx_hal_conf.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/stm32wbxx_it.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/stm_logging.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/utilities_conf.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Inc/vcp_conf.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Src/app_entry.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Src/hw_timerserver.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Src/hw_uart.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Src/main.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Src/stm32_lpm_if.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Src/stm32wbxx_hal_msp.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Src/stm32wbxx_it.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Src/stm_logging.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/Core/Src/system_stm32wbxx.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/EWARM/Project.eww create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/EWARM/Zigbee_PowerProfile_Server_Router.ewd create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/EWARM/Zigbee_PowerProfile_Server_Router.ewp create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/EWARM/startup_stm32wb55xx_cm4.s create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/EWARM/stm32wb55xx_flash_cm4.icf create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/STM32_WPAN/App/app_zigbee.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/STM32_WPAN/App/app_zigbee.h create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/STM32_WPAN/Target/hw_ipcc.c create mode 100644 Projects/P-NUCLEO-WB55.USBDongle/Applications/Zigbee/Zigbee_PowerProfile_Server_Router/readme.txt delete mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/Release_Notes.html create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/Release_Notes.html create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_BLE_HCILayer_fw.bin create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_BLE_Stack_full_fw.bin create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_BLE_Stack_light_fw.bin create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_Mac_802_15_4_fw.bin create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_Thread_FTD_fw.bin create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_Thread_MTD_fw.bin create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/Release_Notes.html create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_HCILayer_fw.bin create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_Stack_full_fw.bin create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_Stack_light_fw.bin create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_Thread_fw.bin create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_Zigbee_FFD_static_fw.bin create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_FUS_fw.bin create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_FUS_fw_1_0_2.bin create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_Mac_802_15_4_fw.bin create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_Thread_FTD_fw.bin create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_Thread_MTD_fw.bin create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_Zigbee_FFD_Full_fw.bin create mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_rfmonitor_phy802_15_4_fw.bin delete mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_BLE_HCILayer_fw.bin delete mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_BLE_Stack_fw.bin delete mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_BLE_Thread_fw.bin delete mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_FUS_fw.bin delete mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_Mac_802_15_4_fw.bin delete mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_Thread_FTD_fw.bin delete mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_Thread_MTD_fw.bin delete mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_Zigbee_FFD_Full_fw.bin delete mode 100644 Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_rfmonitor_phy802_15_4_fw.bin create mode 100644 Utilities/PC_Software/EWARMv8_STM32WB5MMG_Support_V0.1.zip create mode 100644 Utilities/PC_Software/Keil.STM32WB5MMG_DFP.0.0.1.zip diff --git a/Drivers/BSP/NUCLEO-WB35CE/Release_Notes.html b/Drivers/BSP/NUCLEO-WB35CE/Release_Notes.html new file mode 100644 index 000000000..92fc9c4ad --- /dev/null +++ b/Drivers/BSP/NUCLEO-WB35CE/Release_Notes.html @@ -0,0 +1,58 @@ + + + + + + + Release Notes for NUCLEO-WB35CE + + + + + +
+
+
+
+
+

Release Notes for NUCLEO-WB35CE

+

Copyright © 2020 STMicroelectronics
+

+ +
+
+
+

License

+

This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:

+

https://opensource.org/licenses/BSD-3-Clause

+

Purpose

+

This driver provides a set of functions to manage:

+
    +

  • LEDs and push-button available on NUCLEO-WB35CE board from STMicroelectronics

    • +

  • LCD, joystick and microSD available on Adafruit 1.8" TFT LCD shield (reference ID 802)

    • +
+
+
+

Update History

+
+ +
+

Main Changes

+

First release

+
+
+
+
+ + + diff --git a/Drivers/BSP/NUCLEO-WB35CE/_htmresc/mini-st.css b/Drivers/BSP/NUCLEO-WB35CE/_htmresc/mini-st.css new file mode 100644 index 000000000..71fbc14fc --- /dev/null +++ b/Drivers/BSP/NUCLEO-WB35CE/_htmresc/mini-st.css @@ -0,0 +1,1700 @@ +@charset "UTF-8"; +/* + Flavor name: Default (mini-default) + Author: Angelos Chalaris (chalarangelo@gmail.com) + Maintainers: Angelos Chalaris + mini.css version: v3.0.0-alpha.3 +*/ +/* + Browsers resets and base typography. +*/ +/* Core module CSS variable definitions */ +:root { + --fore-color: #111; + --secondary-fore-color: #444; + --back-color: #f8f8f8; + --secondary-back-color: #f0f0f0; + --blockquote-color: #f57c00; + --pre-color: #1565c0; + --border-color: #aaa; + --secondary-border-color: #ddd; + --heading-ratio: 1.19; + --universal-margin: 0.5rem; + --universal-padding: 0.125rem; + --universal-border-radius: 0.125rem; + --a-link-color: #0277bd; + --a-visited-color: #01579b; } + +html { + font-size: 14px; } + +a, b, del, em, i, ins, q, span, strong, u { + font-size: 1em; } + +html, * { + font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif; + line-height: 1.4; + -webkit-text-size-adjust: 100%; } + +* { + font-size: 1rem; } + +body { + margin: 0; + color: var(--fore-color); + background: var(--back-color); } + +details { + display: block; } + +summary { + display: list-item; } + +abbr[title] { + border-bottom: none; + text-decoration: underline dotted; } + +input { + overflow: visible; } + +img { + max-width: 100%; + height: auto; } + +h1, h2, h3, h4, h5, h6 { + line-height: 1.2; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + font-weight: 500; } + h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { + color: var(--secondary-fore-color); + display: block; + margin-top: -0.25rem; } + +h1 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } + +h2 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); ); + background: var(--mark-back-color); + font-weight: 600; + padding: 0.1em 0.5em 0.2em 0.5em; + color: var(--mark-fore-color); } + +h3 { + font-size: calc(1rem * var(--heading-ratio)); + padding-left: calc(2 * var(--universal-margin)); + /* background: var(--border-color); */ + } + +h4 { + font-size: 1rem;); + padding-left: calc(4 * var(--universal-margin)); } + +h5 { + font-size: 1rem; } + +h6 { + font-size: calc(1rem / var(--heading-ratio)); } + +p { + margin: var(--universal-margin); } + +ol, ul { + margin: var(--universal-margin); + padding-left: calc(6 * var(--universal-margin)); } + +b, strong { + font-weight: 700; } + +hr { + box-sizing: content-box; + border: 0; + line-height: 1.25em; + margin: var(--universal-margin); + height: 0.0625rem; + background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } + +blockquote { + display: block; + position: relative; + font-style: italic; + color: var(--secondary-fore-color); + margin: var(--universal-margin); + padding: calc(3 * var(--universal-padding)); + border: 0.0625rem solid var(--secondary-border-color); + border-left: 0.375rem solid var(--blockquote-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + blockquote:before { + position: absolute; + top: calc(0rem - var(--universal-padding)); + left: 0; + font-family: sans-serif; + font-size: 3rem; + font-weight: 700; + content: "\201c"; + color: var(--blockquote-color); } + blockquote[cite]:after { + font-style: normal; + font-size: 0.75em; + font-weight: 700; + content: "\a— " attr(cite); + white-space: pre; } + +code, kbd, pre, samp { + font-family: Menlo, Consolas, monospace; + font-size: 0.85em; } + +code { + background: var(--secondary-back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +kbd { + background: var(--fore-color); + color: var(--back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +pre { + overflow: auto; + background: var(--secondary-back-color); + padding: calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + border: 0.0625rem solid var(--secondary-border-color); + border-left: 0.25rem solid var(--pre-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + +sup, sub, code, kbd { + line-height: 0; + position: relative; + vertical-align: baseline; } + +small, sup, sub, figcaption { + font-size: 0.75em; } + +sup { + top: -0.5em; } + +sub { + bottom: -0.25em; } + +figure { + margin: var(--universal-margin); } + +figcaption { + color: var(--secondary-fore-color); } + +a { + text-decoration: none; } + a:link { + color: var(--a-link-color); } + a:visited { + color: var(--a-visited-color); } + a:hover, a:focus { + text-decoration: underline; } + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #f8f8f8; + --card-fore-color: #111; + --card-border-color: #ddd; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0625rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0625rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { +/* --card-back-color: #ffca28; */ + --card-back-color: #e5b8b7; + --card-border-color: #e8b825; } + +.card.error { + --card-back-color: #b71c1c; + --card-fore-color: #f8f8f8; + --card-border-color: #a71a1a; } + +.card > .sectione.dark { + --card-back-color: #e0e0e0; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #f0f0f0; + --form-fore-color: #111; + --form-border-color: #ddd; + --input-back-color: #f8f8f8; + --input-fore-color: #111; + --input-border-color: #ddd; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0625rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0625rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 700; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0625rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0625rem + var(--universal-padding) / 2); + left: calc(0.0625rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0625rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0625rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0625rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0625rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #f8f8f8; + --header-hover-back-color: #f0f0f0; + --header-fore-color: #444; + --header-border-color: #ddd; + --nav-back-color: #f8f8f8; + --nav-hover-back-color: #f0f0f0; + --nav-fore-color: #444; + --nav-border-color: #ddd; + --nav-link-color: #0277bd; + --footer-fore-color: #444; + --footer-back-color: #f8f8f8; + --footer-border-color: #ddd; + --footer-link-color: #0277bd; + --drawer-back-color: #f8f8f8; + --drawer-hover-back-color: #f0f0f0; + --drawer-border-color: #ddd; + --drawer-close-color: #444; } + +header { + height: 3.1875rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0625rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0625rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0625rem; + content: ''; + height: 100%; + border: 0.0625rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0625rem; + content: ''; + height: 100%; + border: 0.0625rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0625rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0625rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #aaa; + --table-border-separator-color: #666; + --table-head-back-color: #e6e6e6; + --table-head-fore-color: #111; + --table-body-back-color: #f8f8f8; + --table-body-fore-color: #111; + --table-body-alt-back-color: #eee; } + +table { + border-collapse: separate; + border-spacing: 0; + : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); } + table caption { + font-size: 1.25 * rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; + text-align: left;} + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0625rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0625rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0625rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 850px; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: 1 0 0; + margin-left: calc( 4 * var(--universal-margin)); + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: 100%; + border: 0; + border-bottom: 0.0625rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0625rem solid var(--table-border-color); + border-right: 0.0625rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0625rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0625rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0625rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #fafafa; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(2 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +:root { + --table-body-alt-back-color: #eee; } + +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #0277bd; + --mark-fore-color: #fafafa; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.5; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #444; + --modal-close-hover-color: #f0f0f0; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #e8e8e8; + --collapse-label-fore-color: #212121; + --collapse-label-hover-back-color: #f0f0f0; + --collapse-selected-label-back-color: #ececec; + --collapse-border-color: #ddd; + --collapse-content-back-color: #fafafa; + --collapse-selected-label-border-color: #0277bd; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.5rem; + cursor: pointer; + transition: background 0.3s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0625rem solid var(--collapse-border-color); + padding: calc(1.5 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-bottom-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0625rem solid var(--collapse-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 850px; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.secondary { + --mark-back-color: #d32f2f; } + +mark.tertiary { + --mark-back-color: #308732; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progess module CSS variable definitions */ +:root { + --progress-back-color: #ddd; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-location { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-phone { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-rss { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-search { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-settings { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-share { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-cart { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-upload { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-user { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for utilities and helper classes. +*/ +/* Utility module CSS variable definitions */ +:root { + --generic-border-color: rgba(0, 0, 0, 0.3); + --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); } + +.hidden { + display: none !important; } + +.visually-hidden { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } + +.bordered { + border: 0.0625rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# sourceMappingURL=mini-default.css.map */ diff --git a/Drivers/BSP/NUCLEO-WB35CE/_htmresc/st_logo.png b/Drivers/BSP/NUCLEO-WB35CE/_htmresc/st_logo.png new file mode 100644 index 000000000..8b80057fd Binary files /dev/null and b/Drivers/BSP/NUCLEO-WB35CE/_htmresc/st_logo.png differ diff --git a/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c b/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c new file mode 100644 index 000000000..cac119efd --- /dev/null +++ b/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c @@ -0,0 +1,864 @@ +/** + ****************************************************************************** + * @file nucleo_wb35ce.c + * @author MCD Application Team + * @brief This file provides set of firmware functions to manage: + * - LEDs and push-button available on NUCLEO-WB35CE + * from STMicroelectronics + * - LCD, joystick and microSD available on Adafruit 1.8" TFT LCD + * shield (reference ID 802) + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "nucleo_wb35ce.h" + +/** @addtogroup BSP + * @{ + */ + +/** @defgroup NUCLEO-WB35CE NUCLEO-WB35CE + * @brief This file provides set of firmware functions to manage Leds and push-button + * available on NUCLEO-WB35CE board from STMicroelectronics. + * It provides also LCD, joystick and uSD functions to communicate with + * Adafruit 1.8" TFT LCD shield (reference ID 802) + * @{ + */ + +/** @defgroup NUCLEO_WB35CE_Private_Defines Private Defines + * @{ + */ + +/** + * @brief STM32WBxx NUCLEO BSP Driver + */ +#define __NUCLEO_WB35CE_BSP_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __NUCLEO_WB35CE_BSP_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ +#define __NUCLEO_WB35CE_BSP_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __NUCLEO_WB35CE_BSP_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __NUCLEO_WB35CE_BSP_VERSION ((__NUCLEO_WB35CE_BSP_VERSION_MAIN << 24)\ + |(__NUCLEO_WB35CE_BSP_VERSION_SUB1 << 16)\ + |(__NUCLEO_WB35CE_BSP_VERSION_SUB2 << 8 )\ + |(__NUCLEO_WB35CE_BSP_VERSION_RC)) + +/** + * @brief LINK SD Card + */ +#define SD_DUMMY_BYTE 0xFF +#define SD_NO_RESPONSE_EXPECTED 0x80 + +/** + * @} + */ + +/** @defgroup NUCLEO_WB35CE_LOW_LEVEL_Private_Variables Private Variables + * @{ + */ +GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT}; +const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN}; + +GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {BUTTON_SW1_GPIO_PORT, BUTTON_SW2_GPIO_PORT, BUTTON_SW3_GPIO_PORT}; +const uint16_t BUTTON_PIN[BUTTONn] = {BUTTON_SW1_PIN, BUTTON_SW2_PIN, BUTTON_SW3_PIN}; +const uint8_t BUTTON_IRQn[BUTTONn] = {BUTTON_SW1_EXTI_IRQn, BUTTON_SW2_EXTI_IRQn, BUTTON_SW3_EXTI_IRQn}; + +/** + * @brief BUS variables + */ + +#ifdef HAL_SPI_MODULE_ENABLED +uint32_t hnucleo_SpixTimeout = NUCLEO_SPIx_TIMEOUT_MAX; /* success, 1=> fail) + */ +uint8_t BSP_JOY_Init(void) +{ + if (ADCx_Init() != HAL_OK) + { + return (uint8_t) HAL_ERROR; + } + + /* Select Channel 15 to be converted */ + hnucleo_AdcChannelConfig.Channel = ADC_CHANNEL_5; + hnucleo_AdcChannelConfig.SamplingTime = ADC_SAMPLETIME_24CYCLES_5; + hnucleo_AdcChannelConfig.Rank = ADC_REGULAR_RANK_1; + hnucleo_AdcChannelConfig.SingleDiff = ADC_SINGLE_ENDED; + hnucleo_AdcChannelConfig.OffsetNumber = ADC_OFFSET_NONE; + + /* Return Joystick initialization status */ + return (uint8_t) HAL_ADC_ConfigChannel(&hnucleo_Adc, &hnucleo_AdcChannelConfig); +} + +/** + * @brief Returns the Joystick key pressed. + * @note To know which Joystick key is pressed we need to detect the voltage + * level on each key output + * - None : 3.3 V / 4095 + * - SEL : 1.055 V / 1308 + * - DOWN : 0.71 V / 88 + * - LEFT : 3.0 V / 3720 + * - RIGHT : 0.595 V / 737 + * - UP : 1.65 V / 2046 + * @retval JOYState_TypeDef: Code of the Joystick key pressed. + */ +JOYState_TypeDef BSP_JOY_GetState(void) +{ + JOYState_TypeDef state = JOY_NONE; + uint16_t keyconvertedvalue = 0; + + /* Start the conversion process */ + HAL_ADC_Start(&hnucleo_Adc); + + /* Wait for the end of conversion */ + HAL_ADC_PollForConversion(&hnucleo_Adc, 10); + + /* Check if the continous conversion of regular channel is finished */ + if(HAL_ADC_GetState(&hnucleo_Adc) & HAL_ADC_STATE_REG_EOC) + { + /* Get the converted value of regular channel */ + keyconvertedvalue = HAL_ADC_GetValue(&hnucleo_Adc); + } + + if((keyconvertedvalue > 1980) && (keyconvertedvalue < 2120)) + { + state = JOY_UP; + } + else if((keyconvertedvalue > 630) && (keyconvertedvalue < 830)) + { + state = JOY_RIGHT; + } + else if((keyconvertedvalue > 1210) && (keyconvertedvalue < 1410)) + { + state = JOY_SEL; + } + else if((keyconvertedvalue > 20) && (keyconvertedvalue < 160)) + { + state = JOY_DOWN; + } + else if((keyconvertedvalue > 3620) && (keyconvertedvalue < 3820)) + { + state = JOY_LEFT; + } + else + { + state = JOY_NONE; + } + + /* Return the code of the Joystick key pressed*/ + return state; +} + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ + +/** + * @} + */ + +/** @addtogroup NUCLEO_WB35CE_Private_Functions + * @{ + */ + +#ifdef HAL_SPI_MODULE_ENABLED +/****************************************************************************** + BUS OPERATIONS +*******************************************************************************/ +/** + * @brief Initialize SPI MSP. + * @retval None + */ +static void SPIx_MspInit(void) +{ + GPIO_InitTypeDef gpioinitstruct = {0}; + + /*** Configure the GPIOs ***/ + /* Enable GPIO clock */ + NUCLEO_SPIx_SCK_GPIO_CLK_ENABLE(); + NUCLEO_SPIx_MISO_MOSI_GPIO_CLK_ENABLE(); + NUCLEO_SPIx_MOSI_MISO_GPIO_CLK_ENABLE(); + + /* Configure SPI SCK */ + gpioinitstruct.Pin = NUCLEO_SPIx_SCK_PIN; + gpioinitstruct.Mode = GPIO_MODE_AF_PP; + gpioinitstruct.Pull = GPIO_PULLUP; + gpioinitstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + gpioinitstruct.Alternate = NUCLEO_SPIx_SCK_AF; + HAL_GPIO_Init(NUCLEO_SPIx_SCK_GPIO_PORT, &gpioinitstruct); + + /* Configure SPI MISO and MOSI */ + gpioinitstruct.Pin = NUCLEO_SPIx_MOSI_PIN; + gpioinitstruct.Alternate = NUCLEO_SPIx_MOSI_MISO_AF; + gpioinitstruct.Pull = GPIO_PULLDOWN; + HAL_GPIO_Init(NUCLEO_SPIx_MOSI_MISO_GPIO_PORT, &gpioinitstruct); + + gpioinitstruct.Pin = NUCLEO_SPIx_MISO_PIN; + gpioinitstruct.Alternate = NUCLEO_SPIx_MISO_MOSI_AF; + gpioinitstruct.Pull = GPIO_PULLDOWN; + HAL_GPIO_Init(NUCLEO_SPIx_MISO_MOSI_GPIO_PORT, &gpioinitstruct); + + /*** Configure the SPI peripheral ***/ + /* Enable SPI clock */ + NUCLEO_SPIx_CLK_ENABLE(); +} + +/** + * @brief Initialize SPI HAL. + * @retval None + */ +static void SPIx_Init(void) +{ + if(HAL_SPI_GetState(&hnucleo_Spi) == HAL_SPI_STATE_RESET) + { + /* SPI Config */ + hnucleo_Spi.Instance = NUCLEO_SPIx; + /* SPI baudrate is set to 8 MHz maximum (PCLK2/SPI_BaudRatePrescaler = 32/4 = 8 MHz) + to verify these constraints: + - ST7735 LCD SPI interface max baudrate is 15MHz for write and 6.66MHz for read + Since the provided driver doesn't use read capability from LCD, only constraint + on write baudrate is considered. + - SD card SPI interface max baudrate is 25MHz for write/read + - PCLK2 max frequency is 32 MHz + */ + hnucleo_Spi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4; + hnucleo_Spi.Init.Direction = SPI_DIRECTION_2LINES; + hnucleo_Spi.Init.CLKPhase = SPI_PHASE_2EDGE; + hnucleo_Spi.Init.CLKPolarity = SPI_POLARITY_HIGH; + hnucleo_Spi.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hnucleo_Spi.Init.CRCPolynomial = 7; + hnucleo_Spi.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + hnucleo_Spi.Init.DataSize = SPI_DATASIZE_8BIT; + hnucleo_Spi.Init.FirstBit = SPI_FIRSTBIT_MSB; + hnucleo_Spi.Init.NSS = SPI_NSS_SOFT; + hnucleo_Spi.Init.NSSPMode = SPI_NSS_PULSE_DISABLE; + hnucleo_Spi.Init.TIMode = SPI_TIMODE_DISABLE; + hnucleo_Spi.Init.Mode = SPI_MODE_MASTER; + + SPIx_MspInit(); + HAL_SPI_Init(&hnucleo_Spi); + } +} + +/** + * @brief SPI Write byte(s) to device + * @param DataIn: Pointer to data buffer to write + * @param DataOut: Pointer to data buffer for read data + * @param DataLength: number of bytes to write + * @retval None + */ +static void SPIx_WriteReadData(const uint8_t *DataIn, uint8_t *DataOut, uint16_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + status = HAL_SPI_TransmitReceive(&hnucleo_Spi, (uint8_t*) DataIn, DataOut, DataLength, hnucleo_SpixTimeout); + + /* Check the communication status */ + if(status != HAL_OK) + { + /* Execute user timeout callback */ + SPIx_Error(); + } +} + +/** + * @brief SPI Write a byte to device + * @param Value: value to be written + * @retval None + */ +static void SPIx_Write(uint8_t Value) +{ + HAL_StatusTypeDef status = HAL_OK; + uint8_t data; + + status = HAL_SPI_TransmitReceive(&hnucleo_Spi, (uint8_t*) &Value, &data, 1, hnucleo_SpixTimeout); + + /* Check the communication status */ + if(status != HAL_OK) + { + /* Execute user timeout callback */ + SPIx_Error(); + } +} + +/** + * @brief SPI error treatment function + * @retval None + */ +static void SPIx_Error (void) +{ + /* De-initialize the SPI communication BUS */ + HAL_SPI_DeInit(&hnucleo_Spi); + + /* Re-Initiaize the SPI communication BUS */ + SPIx_Init(); +} + +/****************************************************************************** + LINK OPERATIONS +*******************************************************************************/ + +/********************************* LINK SD ************************************/ +/** + * @brief Initialize the SD Card and put it into StandBy State (Ready for + * data transfer). + * @retval None + */ +void SD_IO_Init(void) +{ + GPIO_InitTypeDef gpioinitstruct = {0}; + uint8_t counter = 0; + + /* SD_CS_GPIO Periph clock enable */ + SD_CS_GPIO_CLK_ENABLE(); + + /* Configure SD_CS_PIN pin: SD Card CS pin */ + gpioinitstruct.Pin = SD_CS_PIN; + gpioinitstruct.Mode = GPIO_MODE_OUTPUT_PP; + gpioinitstruct.Pull = GPIO_PULLUP; + gpioinitstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + HAL_GPIO_Init(SD_CS_GPIO_PORT, &gpioinitstruct); + + /* Configure LCD_CS_PIN pin: LCD Card CS pin */ + gpioinitstruct.Pin = LCD_CS_PIN; + gpioinitstruct.Mode = GPIO_MODE_OUTPUT_PP; + gpioinitstruct.Pull = GPIO_NOPULL; + gpioinitstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + HAL_GPIO_Init(LCD_CS_GPIO_PORT, &gpioinitstruct); + LCD_CS_HIGH(); + + /*------------Put SD in SPI mode--------------*/ + /* SD SPI Config */ + SPIx_Init(); + + /* SD chip select high */ + SD_CS_HIGH(); + + /* Send dummy byte 0xFF, 10 times with CS high */ + /* Rise CS and MOSI for 80 clocks cycles */ + for (counter = 0; counter <= 9; counter++) + { + /* Send dummy byte 0xFF */ + SD_IO_WriteByte(SD_DUMMY_BYTE); + } +} + +/** + * @brief Set SD interface Chip Select state + * @param val: 0 (low) or 1 (high) state + * @retval None + */ +void SD_IO_CSState(uint8_t val) +{ + if(val == 1) + { + SD_CS_HIGH(); + } + else + { + SD_CS_LOW(); + } +} + +/** + * @brief Write byte(s) on the SD + * @param DataIn: Pointer to data buffer to write + * @param DataOut: Pointer to data buffer for read data + * @param DataLength: number of bytes to write + * @retval None + */ +void SD_IO_WriteReadData(const uint8_t *DataIn, uint8_t *DataOut, uint16_t DataLength) +{ + /* Send the byte */ + SPIx_WriteReadData(DataIn, DataOut, DataLength); +} + +/** + * @brief Write a byte on the SD. + * @param Data: byte to send. + * @retval Data written + */ +uint8_t SD_IO_WriteByte(uint8_t Data) +{ + uint8_t tmp; + + /* Send the byte */ + SPIx_WriteReadData(&Data,&tmp,1); + return tmp; +} + +/********************************* LINK LCD ***********************************/ +/** + * @brief Initialize the LCD + * @retval None + */ +void LCD_IO_Init(void) +{ + GPIO_InitTypeDef gpioinitstruct = {0}; + + /* LCD_CS_GPIO and LCD_DC_GPIO Periph clock enable */ + LCD_CS_GPIO_CLK_ENABLE(); + LCD_DC_GPIO_CLK_ENABLE(); + + /* Configure LCD_CS_PIN pin: LCD Card CS pin */ + gpioinitstruct.Pin = LCD_CS_PIN; + gpioinitstruct.Mode = GPIO_MODE_OUTPUT_PP; + gpioinitstruct.Pull = GPIO_NOPULL; + gpioinitstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + HAL_GPIO_Init(LCD_CS_GPIO_PORT, &gpioinitstruct); + + /* Configure LCD_DC_PIN pin: LCD Card DC pin */ + gpioinitstruct.Pin = LCD_DC_PIN; + HAL_GPIO_Init(LCD_DC_GPIO_PORT, &gpioinitstruct); + + /* LCD chip select high */ + LCD_CS_HIGH(); + + /* LCD SPI Config */ + SPIx_Init(); +} + +/** + * @brief Write command to select the LCD register. + * @param LCDReg: Address of the selected register. + * @retval None + */ +void LCD_IO_WriteReg(uint8_t LCDReg) +{ + /* Reset LCD control line CS */ + LCD_CS_LOW(); + + /* Set LCD data/command line DC to Low */ + LCD_DC_LOW(); + + /* Send Command */ + SPIx_Write(LCDReg); + + /* Deselect : Chip Select high */ + LCD_CS_HIGH(); +} + +/** +* @brief Write register value. +* @param pData Pointer on the register value +* @param Size Size of byte to transmit to the register +* @retval None +*/ +void LCD_IO_WriteMultipleData(uint8_t *pData, uint32_t Size) +{ + uint32_t counter = 0; + __IO uint32_t data = 0; + + /* Reset LCD control line CS */ + LCD_CS_LOW(); + + /* Set LCD data/command line DC to High */ + LCD_DC_HIGH(); + + if (Size == 1) + { + /* Only 1 byte to be sent to LCD - general interface can be used */ + /* Send Data */ + SPIx_Write(*pData); + } + else + { + /* Several data should be sent in a raw */ + /* Direct SPI accesses for optimization */ + for (counter = Size; counter != 0; counter--) + { + while(((hnucleo_Spi.Instance->SR) & SPI_FLAG_TXE) != SPI_FLAG_TXE) + { + } + /* Need to invert bytes for LCD*/ + *((__IO uint8_t*)&hnucleo_Spi.Instance->DR) = *(pData+1); + + while(((hnucleo_Spi.Instance->SR) & SPI_FLAG_TXE) != SPI_FLAG_TXE) + { + } + *((__IO uint8_t*)&hnucleo_Spi.Instance->DR) = *pData; + counter--; + pData += 2; + } + + /* Wait until the bus is ready before releasing Chip select */ + while(((hnucleo_Spi.Instance->SR) & SPI_FLAG_BSY) != RESET) + { + } + } + + /* Empty the Rx fifo */ + data = *(&hnucleo_Spi.Instance->DR); + UNUSED(data); /* Remove GNU warning */ + + /* Deselect : Chip Select high */ + LCD_CS_HIGH(); +} + +/** + * @brief Wait for loop in ms. + * @param Delay in ms. + * @retval None + */ +void LCD_Delay(uint32_t Delay) +{ + HAL_Delay(Delay); +} + +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +/******************************* LINK JOYSTICK ********************************/ +/** + * @brief Initialize ADC MSP. + * @retval None + */ +static void ADCx_MspInit(ADC_HandleTypeDef *hadc) +{ + GPIO_InitTypeDef gpioinitstruct = {0}; + RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct; + + /*** Configure the GPIOs ***/ + /* Enable GPIO clock */ + NUCLEO_ADCx_GPIO_CLK_ENABLE(); + + /* Configure ADC1 Channel8 as analog input */ + gpioinitstruct.Pin = NUCLEO_ADCx_GPIO_PIN ; + gpioinitstruct.Mode = GPIO_MODE_ANALOG; + gpioinitstruct.Pull = GPIO_NOPULL; + gpioinitstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + HAL_GPIO_Init(NUCLEO_ADCx_GPIO_PORT, &gpioinitstruct); + + /*** Configure the ADC peripheral ***/ + /* Enable ADC clock */ + NUCLEO_ADCx_CLK_ENABLE(); + + /* Configure SYSCLK as source clock for ADC */ + RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC; + RCC_PeriphCLKInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK; + HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct); +} + +/** + * @brief Initializes ADC HAL. + * @retval None + */ +static HAL_StatusTypeDef ADCx_Init(void) +{ + if(HAL_ADC_GetState(&hnucleo_Adc) == HAL_ADC_STATE_RESET) + { + /* ADC Config */ + hnucleo_Adc.Instance = NUCLEO_ADCx; + hnucleo_Adc.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; + hnucleo_Adc.Init.Resolution = ADC_RESOLUTION_12B; + hnucleo_Adc.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hnucleo_Adc.Init.ScanConvMode = DISABLE; + hnucleo_Adc.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + hnucleo_Adc.Init.LowPowerAutoWait = DISABLE; + hnucleo_Adc.Init.ContinuousConvMode = DISABLE; + hnucleo_Adc.Init.NbrOfConversion = 1; + hnucleo_Adc.Init.DiscontinuousConvMode = DISABLE; + hnucleo_Adc.Init.NbrOfDiscConversion = 1; + hnucleo_Adc.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hnucleo_Adc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hnucleo_Adc.Init.DMAContinuousRequests = DISABLE; + hnucleo_Adc.Init.Overrun = ADC_OVR_DATA_PRESERVED; + hnucleo_Adc.Init.OversamplingMode = DISABLE; + + ADCx_MspInit(&hnucleo_Adc); + if (HAL_ADC_Init(&hnucleo_Adc) != HAL_OK) + { + return HAL_ERROR; + } + + if (HAL_ADCEx_Calibration_Start(&hnucleo_Adc,ADC_SINGLE_ENDED) != HAL_OK) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +#endif /* HAL_ADC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.h b/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.h new file mode 100644 index 000000000..37578d26b --- /dev/null +++ b/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.h @@ -0,0 +1,301 @@ +/** + ****************************************************************************** + * @file nucleo_wb35ce.h + * @author MCD Application Team + * @brief This file contains definitions for: + * - LEDs and push-button available on NUCLEO-WB35CE + * from STMicroelectronics + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __NUCLEO_WB35CE_H +#define __NUCLEO_WB35CE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup NUCLEO-WB35CE + * @{ + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbxx_hal.h" + +/** @defgroup NUCLEO-WB35CE_Exported_Types Exported Types + * @{ + */ +typedef enum +{ + LED1 = 0, + LED2 = 1, + LED3 = 2, + /* Color led aliases */ + LED_BLUE = LED1, + LED_GREEN = LED2, + LED_RED = LED3 +}Led_TypeDef; + +typedef enum +{ + BUTTON_SW1 = 0, + BUTTON_SW2 = 1, + BUTTON_SW3 = 2, +}Button_TypeDef; + +typedef enum +{ + BUTTON_MODE_GPIO = 0, + BUTTON_MODE_EXTI = 1 +}ButtonMode_TypeDef; + +typedef enum +{ + JOY_NONE = 0, + JOY_SEL = 1, + JOY_DOWN = 2, + JOY_LEFT = 3, + JOY_RIGHT = 4, + JOY_UP = 5 +} JOYState_TypeDef; + +/** + * @} + */ + +/** @defgroup NUCLEO-WB35CE_Exported_Constants Exported Constants + * @{ + */ + +/** + * @brief Define for NUCLEO-WB35CE board + */ +#if !defined (USE_NUCLEO_WB35CE) + #define USE_NUCLEO_WB35CE +#endif + +/** @defgroup NUCLEO_WB35CE_LED LED Constants + * @{ + */ +#define LEDn 3 + +#define LED1_PIN GPIO_PIN_5 +#define LED1_GPIO_PORT GPIOB +#define LED1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define LED1_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_ENABLE() + +#define LED2_PIN GPIO_PIN_0 +#define LED2_GPIO_PORT GPIOB +#define LED2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define LED2_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_ENABLE() + +#define LED3_PIN GPIO_PIN_1 +#define LED3_GPIO_PORT GPIOB +#define LED3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define LED3_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_ENABLE() + +#define LEDx_GPIO_CLK_ENABLE(__INDEX__) __HAL_RCC_GPIOB_CLK_ENABLE() /* All Led on same port */ +#define LEDx_GPIO_CLK_DISABLE(__INDEX__) __HAL_RCC_GPIOB_CLK_ENABLE() /* All Led on same port */ +/** + * @} + */ + +/** @defgroup NUCLEO_WB35CE_BUTTON BUTTON Constants + * @{ + */ +#define BUTTONn 3 + +/** + * @brief Key push-button + */ +#define BUTTON_SW1_PIN GPIO_PIN_0 +#define BUTTON_SW1_GPIO_PORT GPIOA +#define BUTTON_SW1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define BUTTON_SW1_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#define BUTTON_SW1_EXTI_LINE GPIO_PIN_0 +#define BUTTON_SW1_EXTI_IRQn EXTI0_IRQn + +#define BUTTON_SW2_PIN GPIO_PIN_4 +#define BUTTON_SW2_GPIO_PORT GPIOE +#define BUTTON_SW2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE() +#define BUTTON_SW2_GPIO_CLK_DISABLE() __HAL_RCC_GPIOE_CLK_DISABLE() +#define BUTTON_SW2_EXTI_LINE GPIO_PIN_4 +#define BUTTON_SW2_EXTI_IRQn EXTI4_IRQn + +#define BUTTON_SW3_PIN GPIO_PIN_6 +#define BUTTON_SW3_GPIO_PORT GPIOA +#define BUTTON_SW3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define BUTTON_SW3_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#define BUTTON_SW3_EXTI_LINE GPIO_PIN_6 +#define BUTTON_SW3_EXTI_IRQn EXTI9_5_IRQn + +#define BUTTONx_GPIO_CLK_ENABLE(__INDEX__) do { if ((__INDEX__) == BUTTON_SW1) BUTTON_SW1_GPIO_CLK_ENABLE(); else \ + if ((__INDEX__) == BUTTON_SW2) BUTTON_SW2_GPIO_CLK_ENABLE(); else \ + if ((__INDEX__) == BUTTON_SW3) BUTTON_SW3_GPIO_CLK_ENABLE();} while(0) + +#define BUTTONx_GPIO_CLK_DISABLE(__INDEX__) do { if ((__INDEX__) == BUTTON_SW1) BUTTON_SW1_GPIO_CLK_DISABLE(); else \ + if ((__INDEX__) == BUTTON_SW2) BUTTON_SW2_GPIO_CLK_DISABLE(); else \ + if ((__INDEX__) == BUTTON_SW3) BUTTON_SW3_GPIO_CLK_DISABLE();} while(0) + +/** + * @} + */ + +/** @addtogroup NUCLEO_WB35CE_BUS BUS Constants + * @{ + */ +/*###################### SPI1 ###################################*/ +#define NUCLEO_SPIx SPI1 +#define NUCLEO_SPIx_CLK_ENABLE() __HAL_RCC_SPI1_CLK_ENABLE() + +#define NUCLEO_SPIx_SCK_AF GPIO_AF5_SPI1 +#define NUCLEO_SPIx_SCK_GPIO_PORT GPIOA +#define NUCLEO_SPIx_SCK_PIN GPIO_PIN_5 +#define NUCLEO_SPIx_SCK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define NUCLEO_SPIx_SCK_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() + +#define NUCLEO_SPIx_MISO_MOSI_AF GPIO_AF5_SPI1 +#define NUCLEO_SPIx_MISO_MOSI_GPIO_PORT GPIOB +#define NUCLEO_SPIx_MISO_MOSI_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define NUCLEO_SPIx_MISO_MOSI_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE() +#define NUCLEO_SPIx_MISO_PIN GPIO_PIN_4 + +#define NUCLEO_SPIx_MOSI_MISO_AF GPIO_AF5_SPI1 +#define NUCLEO_SPIx_MOSI_MISO_GPIO_PORT GPIOA +#define NUCLEO_SPIx_MOSI_MISO_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define NUCLEO_SPIx_MOSI_MISO_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#define NUCLEO_SPIx_MOSI_PIN GPIO_PIN_7 +/* Maximum Timeout values for flags waiting loops. These timeouts are not based + on accurate values, they just guarantee that the application will not remain + stuck if the SPI communication is corrupted. + You may modify these timeout values depending on CPU frequency and application + conditions (interrupts routines ...). */ +#define NUCLEO_SPIx_TIMEOUT_MAX 1000 + + +/** + * @brief SD Control Lines management + */ +#define SD_CS_LOW() HAL_GPIO_WritePin(SD_CS_GPIO_PORT, SD_CS_PIN, GPIO_PIN_RESET) +#define SD_CS_HIGH() HAL_GPIO_WritePin(SD_CS_GPIO_PORT, SD_CS_PIN, GPIO_PIN_SET) + +/** + * @brief LCD Control Lines management + */ +#define LCD_CS_LOW() HAL_GPIO_WritePin(LCD_CS_GPIO_PORT, LCD_CS_PIN, GPIO_PIN_RESET) +#define LCD_CS_HIGH() HAL_GPIO_WritePin(LCD_CS_GPIO_PORT, LCD_CS_PIN, GPIO_PIN_SET) +#define LCD_DC_LOW() HAL_GPIO_WritePin(LCD_DC_GPIO_PORT, LCD_DC_PIN, GPIO_PIN_RESET) +#define LCD_DC_HIGH() HAL_GPIO_WritePin(LCD_DC_GPIO_PORT, LCD_DC_PIN, GPIO_PIN_SET) + +/** + * @brief SD Control Interface pins + */ +#define SD_CS_PIN GPIO_PIN_1 +#define SD_CS_GPIO_PORT GPIOB +#define SD_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define SD_CS_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE() + +/** + * @brief LCD Control Interface pins + */ +#define LCD_CS_PIN GPIO_PIN_2 +#define LCD_CS_GPIO_PORT GPIOB +#define LCD_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define LCD_CS_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE() + +/** + * @brief LCD Data/Command Interface pins + */ +#define LCD_DC_PIN GPIO_PIN_5 +#define LCD_DC_GPIO_PORT GPIOB +#define LCD_DC_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define LCD_DC_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE() + +/*##################### ADC1 ###################################*/ +/** + * @brief ADC Interface pins + * used to detect motion of Joystick available on Adafruit 1.8" TFT shield + */ +#define NUCLEO_ADCx ADC1 +#define NUCLEO_ADCx_CLK_ENABLE() __HAL_RCC_ADC_CLK_ENABLE() + +#define NUCLEO_ADCx_GPIO_PORT GPIOA +#define NUCLEO_ADCx_GPIO_PIN GPIO_PIN_0 +#define NUCLEO_ADCx_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define NUCLEO_ADCx_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup NUCLEO_WB35CE_Exported_Functions + * @{ + */ +uint32_t BSP_GetVersion(void); + +/** @addtogroup NUCLEO_WB35CE_LED_Functions + * @{ + */ +void BSP_LED_Init(Led_TypeDef Led); +void BSP_LED_DeInit(Led_TypeDef Led); +void BSP_LED_On(Led_TypeDef Led); +void BSP_LED_Off(Led_TypeDef Led); +void BSP_LED_Toggle(Led_TypeDef Led); +/** + * @} + */ + +/** @addtogroup NUCLEO_WB35CE_BUTTON_Functions + * @{ + */ +void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode); +void BSP_PB_DeInit(Button_TypeDef Button); +uint32_t BSP_PB_GetState(Button_TypeDef Button); +#ifdef HAL_ADC_MODULE_ENABLED +uint8_t BSP_JOY_Init(void); +JOYState_TypeDef BSP_JOY_GetState(void); +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NUCLEO_WB35CE_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Drivers/BSP/P-NUCLEO-WB55.Nucleo/Release_Notes.html b/Drivers/BSP/P-NUCLEO-WB55.Nucleo/Release_Notes.html index 6a8c2a122..c5b8cb6bd 100644 --- a/Drivers/BSP/P-NUCLEO-WB55.Nucleo/Release_Notes.html +++ b/Drivers/BSP/P-NUCLEO-WB55.Nucleo/Release_Notes.html @@ -42,9 +42,16 @@

Update History

- +

Main Changes

+

Clean CORE_CM0PLUS

+
+
+
+ +
+

Main Changes

First release

diff --git a/Drivers/BSP/P-NUCLEO-WB55.Nucleo/stm32wbxx_nucleo.c b/Drivers/BSP/P-NUCLEO-WB55.Nucleo/stm32wbxx_nucleo.c index 2938d3349..ade670ea0 100644 --- a/Drivers/BSP/P-NUCLEO-WB55.Nucleo/stm32wbxx_nucleo.c +++ b/Drivers/BSP/P-NUCLEO-WB55.Nucleo/stm32wbxx_nucleo.c @@ -45,7 +45,7 @@ */ #define __STM32WBxx_NUCLEO_BSP_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32WBxx_NUCLEO_BSP_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ -#define __STM32WBxx_NUCLEO_BSP_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32WBxx_NUCLEO_BSP_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32WBxx_NUCLEO_BSP_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBxx_NUCLEO_BSP_VERSION ((__STM32WBxx_NUCLEO_BSP_VERSION_MAIN << 24)\ |(__STM32WBxx_NUCLEO_BSP_VERSION_SUB1 << 16)\ diff --git a/Drivers/BSP/P-NUCLEO-WB55.Nucleo/stm32wbxx_nucleo.h b/Drivers/BSP/P-NUCLEO-WB55.Nucleo/stm32wbxx_nucleo.h index a916d0616..1ec242304 100644 --- a/Drivers/BSP/P-NUCLEO-WB55.Nucleo/stm32wbxx_nucleo.h +++ b/Drivers/BSP/P-NUCLEO-WB55.Nucleo/stm32wbxx_nucleo.h @@ -129,33 +129,21 @@ typedef enum #define BUTTON_SW1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() #define BUTTON_SW1_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() #define BUTTON_SW1_EXTI_LINE GPIO_PIN_4 -#ifdef CORE_CM0PLUS -#define BUTTON_SW1_EXTI_IRQn EXTI15_4_IRQn -#else #define BUTTON_SW1_EXTI_IRQn EXTI4_IRQn -#endif #define BUTTON_SW2_PIN GPIO_PIN_0 #define BUTTON_SW2_GPIO_PORT GPIOD #define BUTTON_SW2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE() #define BUTTON_SW2_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE() #define BUTTON_SW2_EXTI_LINE GPIO_PIN_0 -#ifdef CORE_CM0PLUS -#define BUTTON_SW2_EXTI_IRQn EXTI1_0_IRQn -#else #define BUTTON_SW2_EXTI_IRQn EXTI0_IRQn -#endif #define BUTTON_SW3_PIN GPIO_PIN_1 #define BUTTON_SW3_GPIO_PORT GPIOD #define BUTTON_SW3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE() #define BUTTON_SW3_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE() #define BUTTON_SW3_EXTI_LINE GPIO_PIN_1 -#ifdef CORE_CM0PLUS -#define BUTTON_SW3_EXTI_IRQn EXTI1_0_IRQn -#else #define BUTTON_SW3_EXTI_IRQn EXTI1_IRQn -#endif #define BUTTONx_GPIO_CLK_ENABLE(__INDEX__) do { if ((__INDEX__) == BUTTON_SW1) BUTTON_SW1_GPIO_CLK_ENABLE(); else \ if ((__INDEX__) == BUTTON_SW2) BUTTON_SW2_GPIO_CLK_ENABLE(); else \ diff --git a/Drivers/BSP/P-NUCLEO-WB55.USBDongle/Release_Notes.html b/Drivers/BSP/P-NUCLEO-WB55.USBDongle/Release_Notes.html index 83120aef9..2926b0f55 100644 --- a/Drivers/BSP/P-NUCLEO-WB55.USBDongle/Release_Notes.html +++ b/Drivers/BSP/P-NUCLEO-WB55.USBDongle/Release_Notes.html @@ -41,9 +41,16 @@

Update History

- +

Main Changes

+

Clean CORE_CM0PLUS

+
+
+
+ +
+

Main Changes

First release

diff --git a/Drivers/BSP/P-NUCLEO-WB55.USBDongle/stm32wbxx_usb_dongle.c b/Drivers/BSP/P-NUCLEO-WB55.USBDongle/stm32wbxx_usb_dongle.c index e76d4279d..1600829d1 100644 --- a/Drivers/BSP/P-NUCLEO-WB55.USBDongle/stm32wbxx_usb_dongle.c +++ b/Drivers/BSP/P-NUCLEO-WB55.USBDongle/stm32wbxx_usb_dongle.c @@ -41,7 +41,7 @@ */ #define __STM32WBxx_USB_DONGLE_BSP_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32WBxx_USB_DONGLE_BSP_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ -#define __STM32WBxx_USB_DONGLE_BSP_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32WBxx_USB_DONGLE_BSP_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32WBxx_USB_DONGLE_BSP_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBxx_USB_DONGLE_BSP_VERSION ((__STM32WBxx_USB_DONGLE_BSP_VERSION_MAIN << 24)\ |(__STM32WBxx_USB_DONGLE_BSP_VERSION_SUB1 << 16)\ diff --git a/Drivers/BSP/P-NUCLEO-WB55.USBDongle/stm32wbxx_usb_dongle.h b/Drivers/BSP/P-NUCLEO-WB55.USBDongle/stm32wbxx_usb_dongle.h index 6d2377648..d1ce42206 100644 --- a/Drivers/BSP/P-NUCLEO-WB55.USBDongle/stm32wbxx_usb_dongle.h +++ b/Drivers/BSP/P-NUCLEO-WB55.USBDongle/stm32wbxx_usb_dongle.h @@ -131,15 +131,11 @@ typedef enum #else #define BUTTON_SW1_EXTI_LINE GPIO_PIN_10 #endif -#ifdef CORE_CM0PLUS -#define BUTTON_SW1_EXTI_IRQn EXTI15_4_IRQn -#else #if defined (USE_STM32WBXX_USB_DONGLE_REVA) #define BUTTON_SW1_EXTI_IRQn EXTI9_5_IRQn #else #define BUTTON_SW1_EXTI_IRQn EXTI15_10_IRQn #endif -#endif #define BUTTONx_GPIO_CLK_ENABLE(__INDEX__) __HAL_RCC_GPIOA_CLK_ENABLE() diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb30xx.h b/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb30xx.h new file mode 100644 index 000000000..f393c9ad4 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb30xx.h @@ -0,0 +1,11130 @@ +/** + ****************************************************************************** + * @file stm32wb30xx.h + * @author MCD Application Team + * @brief CMSIS Cortex Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for stm32wb30xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32wb30xx + * @{ + */ + +#ifndef __STM32WB30xx_H +#define __STM32WB30xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 1U /*!< Core Revision r0p1 */ +#define __MPU_PRESENT 1U /*!< M4 provides an MPU */ +#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 4U /*!< STM32WBxx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32wb30xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +/*!< Interrupt Number Definition for M4 */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< Cortex-M4 System Tick Interrupt */ + +/************* STM32WBxx specific Interrupt Numbers on M4 core ************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD and PVM detector */ + TAMP_STAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Interrupt */ + FLASH_IRQn = 4, /*!< FLASH (CFI) global Interrupt */ + RCC_IRQn = 5, /*!< RCC Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line 0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line 1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line 2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line 3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line 4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 Interrupt */ + C2SEV_PWR_C2H_IRQn = 21, /*!< CPU2 SEV Interrupt */ + EXTI9_5_IRQn = 23, /*!< EXTI Lines [9:5] Interrupt */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 global Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Communication and TIM17 global Interrupts */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 Global Interrupt */ + PKA_IRQn = 29, /*!< PKA Interrupt */ + I2C1_EV_IRQn = 30, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 31, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 34, /*!< SPI1 Interrupt */ + USART1_IRQn = 36, /*!< USART1 Interrupt */ + TSC_IRQn = 39, /*!< TSC Interrupt */ + EXTI15_10_IRQn = 40, /*!< EXTI Lines1[15:10 ]Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarms (A and B) Interrupt */ + PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQn = 43, /*!< PWR switching on the fly interrupt + PWR end of BLE activity interrupt + PWR end of 802.15.4 (Zigbee) activity interrupt + PWR end of critical radio phase interrupt */ + IPCC_C1_RX_IRQn = 44, /*!< IPCC RX Occupied Interrupt */ + IPCC_C1_TX_IRQn = 45, /*!< IPCC TX Free Interrupt */ + HSEM_IRQn = 46, /*!< HSEM Interrupt */ + LPTIM1_IRQn = 47, /*!< LPTIM1 Interrupt */ + LPTIM2_IRQn = 48, /*!< LPTIM2 Interrupt */ + AES2_IRQn = 52, /*!< AES2 Interrupt */ + RNG_IRQn = 53, /*!< RNG Interrupt */ + FPU_IRQn = 54, /*!< FPU Interrupt */ + DMAMUX1_OVR_IRQn = 62 /*!< DMAMUX1 overrun Interrupt */ +} IRQn_Type; +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32wbxx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */ +} ADC_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x08-0x38 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x3C */ + __IO uint32_t C2APB1FZR1; /*!< Debug MCU CPU2 APB1 freeze register, Address offset: 0x40 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x44 */ + __IO uint32_t C2APB1FZR2; /*!< Debug MCU CPU2 APB1 freeze register, Address offset: 0x48 */ + __IO uint32_t APB2FZR; /*!< Debug MCU CPU1 APB2 freeze register, Address offset: 0x4C */ + __IO uint32_t C2APB2FZR; /*!< Debug MCU CPU2 APB2 freeze register, Address offset: 0x50 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register 0x00 */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register 0x04 */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register 0x08 */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register 0x0C */ + uint32_t RESERVED; /*!< Reserved, 0x10 */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access control register, Address offset: 0x00 */ + __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank 1 PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank 1 PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank 1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank 1 WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank 1 PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank 1 PCROP area B End address register, Address offset: 0x38 */ + __IO uint32_t IPCCBR; /*!< FLASH IPCC data buffer address, Address offset: 0x3C */ + uint32_t RESERVED2[7]; /*!< Reserved, Address offset: 0x40-0x58 */ + __IO uint32_t C2ACR; /*!< FLASH Core MO+ Access Control Register , Address offset: 0x5C */ + __IO uint32_t C2SR; /*!< FLASH Core MO+ Status Register, Address offset: 0x60 */ + __IO uint32_t C2CR; /*!< FLASH Core MO+ Control register, Address offset: 0x64 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x68-0x7C */ + __IO uint32_t SFR; /*!< FLASH secure start address, Address offset: 0x80 */ + __IO uint32_t SRRVR; /*!< FlASH secure SRAM2 start addr and CPU2 reset vector Address offset: 0x84 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Reset Register, Address offset: 0x18 */ + __IO uint32_t CR5; /*!< PWR Power Control Register 5, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t PUCRE; /*!< PWR Pull-Up Control Register of port E, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< PWR Pull-Down Control Register of port E, Address offset: 0x44 */ + uint32_t RESERVED0[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t PUCRH; /*!< PWR Pull-Up Control Register of port H, Address offset: 0x58 */ + __IO uint32_t PDCRH; /*!< PWR Pull-Down Control Register of port H, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, Address offset: 0x60-0x7C */ + __IO uint32_t C2CR1; /*!< PWR Power Control Register 1 for CPU2, Address offset: 0x80 */ + __IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset: 0x84 */ + __IO uint32_t EXTSCR; /*!< PWR Power Status Reset Register for CPU2, Address offset: 0x88 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ +uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x10-0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ +uint32_t RESERVED11; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 & AHB4 peripheral reset register, Address offset: 0x30 */ +uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable register, Address offset: 0x50 */ +uint32_t RESERVED2; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ +uint32_t RESERVED3; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ +uint32_t RESERVED4; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ +uint32_t RESERVED5; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Clock Configuration Independent Register, Address offset: 0x88 */ +uint32_t RESERVED6; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC Control and Status Register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x98 */ + __IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */ +uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */ + __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */ +uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ + __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */ + __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */ + __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */ +uint32_t RESERVED9; /*!< Reserved, Address offset: 0x154 */ + __IO uint32_t C2APB1ENR1; /*!< RCC APB1 peripheral CPU2 clocks enable register 1, Address offset: 0x158 */ + __IO uint32_t C2APB1ENR2; /*!< RCC APB1 peripheral CPU2 clocks enable register 2, Address offset: 0x15C */ + __IO uint32_t C2APB2ENR; /*!< RCC APB2 peripheral CPU2 clocks enable register 1, Address offset: 0x160 */ + __IO uint32_t C2APB3ENR; /*!< RCC APB3 peripheral CPU2 clocks enable register 1, Address offset: 0x164 */ + __IO uint32_t C2AHB1SMENR; /*!< RCC AHB1 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x168 */ + __IO uint32_t C2AHB2SMENR; /*!< RCC AHB2 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x16C */ + __IO uint32_t C2AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x170 */ +uint32_t RESERVED10; /*!< Reserved, */ + __IO uint32_t C2APB1SMENR1; /*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 1, Address offset: 0x178 */ + __IO uint32_t C2APB1SMENR2; /*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 2, Address offset: 0x17C */ + __IO uint32_t C2APB2SMENR; /*!< RCC APB2 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x180 */ + __IO uint32_t C2APB3SMENR; /*!< RCC APB3 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x184 */ +} RCC_TypeDef; + + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + + + + +/** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR1; /*!< SYSCFG SRAM2 write protection register part 1, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ + __IO uint32_t SWPR2; /*!< SYSCFG write protection register part 2, Address offset: 0x28 */ + uint32_t RESERVED1[53]; /*!< Reserved, Address offset: 0x2C-0xFC */ + __IO uint32_t IMR1; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 1, Address offset: 0x100 */ + __IO uint32_t IMR2; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 2, Address offset: 0x104 */ + __IO uint32_t C2IMR1; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 1, Address offset: 0x108 */ + __IO uint32_t C2IMR2; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 2, Address offset: 0x10C */ + __IO uint32_t SIPCR; /*!< SYSCFG secure IP control register, Address offset: 0x110 */ + +} SYSCFG_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ +} AES_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief Inter-Processor Communication + */ +typedef struct +{ + __IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, Address offset: 0x000 */ + __IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, Address offset: 0x004 */ + __IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, Address offset: 0x008 */ + __IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status register, Address offset: 0x00C */ + __IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, Address offset: 0x010 */ + __IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, Address offset: 0x014 */ + __IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, Address offset: 0x018 */ + __IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status register, Address offset: 0x01C */ +} IPCC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x000 */ + __IO uint32_t MR; /*!< Mask register, Address offset: 0x004 */ + __IO uint32_t SCR; /*!< Status set clear register, Address offset: 0x008 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x00C */ +} IPCC_CommonTypeDef; + +/** + * @brief Async Interrupts and Events Controller + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI software interrupt event register [31:0], Address offset: 0x08 */ + __IO uint32_t PR1; /*!< EXTI pending register [31:0], Address offset: 0x0C */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x10 - 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI software interrupt event register [31:0], Address offset: 0x28 */ + __IO uint32_t PR2; /*!< EXTI pending register [31:0], Address offset: 0x2C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, Address offset: 0x30 - 0x3C */ + __IO uint32_t RESERVED3[8]; /*!< Reserved, Address offset: 0x40 - 0x5C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, Address offset: 0x60 - 0x7C */ + __IO uint32_t IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED8[10]; /*!< Reserved, Address offset: 0x98 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ +}EXTI_TypeDef; + +/** + * @brief Public Key Accelerator (PKA) + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved1[253]; /*!< Reserved Address offset: 0x000C-0x03FC*/ + __IO uint32_t RAM[894]; /*!< PKA RAM, Address offset: 0x0400-0x11F4 */ +} PKA_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ +typedef struct +{ + __IO uint32_t R[32]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RLR[32]; /*!< HSEM 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IER; /*!< HSEM CPU1 interrupt enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM CPU1 interrupt clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM CPU1 interrupt status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM CPU1 masked interrupt status register , Address offset: 10Ch */ + __IO uint32_t C2IER; /*!< HSEM CPU2 interrupt enable register , Address offset: 110h */ + __IO uint32_t C2ICR; /*!< HSEM CPU2 interrupt clear register , Address offset: 114h */ + __IO uint32_t C2ISR; /*!< HSEM CPU2 interrupt status register , Address offset: 118h */ + __IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 11Ch */ + uint32_t Reserved[8]; /*!< Reserved Address offset: 120h-13Ch*/ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +/*!< Boundary memory map */ +#define FLASH_BASE (0x08000000UL)/*!< FLASH(up to 1 MB) base address */ +#define SRAM_BASE (0x20000000UL)/*!< SRAM(up to 256 KB) base address */ +#define PERIPH_BASE (0x40000000UL)/*!< Peripheral base address */ + +/*!< Memory, OTP and Option bytes */ + +/* Base addresses */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 0x1FFF8FFF) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ + +#define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 32 KB) base address */ +#define SRAM2A_BASE (SRAM_BASE + 0x00008000UL)/*!< SRAM2A(32 KB) base address */ +#define SRAM2B_BASE (SRAM_BASE + 0x00010000UL)/*!< SRAM2B(32 KB) base address */ + +/* Memory Size */ +#define FLASH_SIZE (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x07FFUL)) << 10U) +#define SRAM1_SIZE 0x00008000UL /*!< SRAM1 default size : 32 kB */ +#define SRAM2A_SIZE 0x00008000UL /*!< SRAM2a default size : 32 kB */ +#define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */ + +/* End addresses */ +#define SRAM1_END_ADDR (0x20007FFFUL) /*!< SRAM1 : 32KB (0x20000000 0x20007FFF) */ +#define SRAM2A_END_ADDR (0x2000FFFFUL) /*!< SRAM2a (backup) : 32KB (0x20008000 0x2000FFFF) */ +#define SRAM2B_END_ADDR (0x20017FFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20010000 0x20017FFF) */ + +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) +#define AHB4PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define APB3PERIPH_BASE (PERIPH_BASE + 0x20000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x50000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x00007C00UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x00009400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x00000030UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x00000800UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) + +/*!< AHB2 peripherals */ +#define IOPORT_BASE (AHB2PERIPH_BASE + 0x00000000UL) +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOE_BASE (IOPORT_BASE + 0x00001000UL) +#define GPIOH_BASE (IOPORT_BASE + 0x00001C00UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) + + +/*!< AHB Shared peripherals */ +#define RCC_BASE (AHB4PERIPH_BASE + 0x00000000UL) +#define PWR_BASE (AHB4PERIPH_BASE + 0x00000400UL) +#define EXTI_BASE (AHB4PERIPH_BASE + 0x00000800UL) +#define IPCC_BASE (AHB4PERIPH_BASE + 0x00000C00UL) +#define RNG_BASE (AHB4PERIPH_BASE + 0x00001000UL) +#define HSEM_BASE (AHB4PERIPH_BASE + 0x00001400UL) +#define AES2_BASE (AHB4PERIPH_BASE + 0x00001800UL) +#define PKA_BASE (AHB4PERIPH_BASE + 0x00002000UL) +#define FLASH_REG_BASE (AHB4PERIPH_BASE + 0x00004000UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + + +/*!< AHB3 peripherals */ + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE ((uint32_t)0x1FFF7500UL) /*!< Package data register base address */ +#define UID64_BASE ((uint32_t)0x1FFF7580UL) /*!< 64-bit Unique device Identification */ +#define UID_BASE ((uint32_t)0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0UL) /*!< Flash size data register base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +/* Peripherals available on APB1 bus */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) + +/* Peripherals available on APB2 bus */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) + +/* Peripherals available on AHB1 bus */ +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + +#define CRC ((CRC_TypeDef *) CRC_BASE) + +/* Peripherals available on AHB2 bus */ +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) + + +/* Peripherals available on AHB shared bus */ +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define IPCC ((IPCC_TypeDef *) IPCC_BASE) +#define IPCC_C1 ((IPCC_CommonTypeDef *) IPCC_BASE) +#define IPCC_C2 ((IPCC_CommonTypeDef *) (IPCC_BASE + 0x10U)) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100U)) +#define AES2 ((AES_TypeDef *) AES2_BASE) +#define PKA ((PKA_TypeDef *) PKA_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_REG_BASE) + +/* Peripherals available on AHB3 bus */ + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_ALIGN_Pos (5U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR_EXTSEL_Pos (6U) +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ + +#define ADC_JSQR_JEXTEN_Pos (6U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ + +#define ADC_JSQR_JSQ1_Pos (8U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ + +#define ADC_JSQR_JSQ2_Pos (14U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (20U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ + +#define ADC_JSQR_JSQ4_Pos (26U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ +#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ +#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ +#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ +#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003A0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00000100 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00000200 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00000400 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/* Legacy defines */ +#define ADC_CCR_MULTI (ADC_CCR_DUAL) +#define ADC_CCR_MULTI_0 (ADC_CCR_DUAL_0) +#define ADC_CCR_MULTI_1 (ADC_CCR_DUAL_1) +#define ADC_CCR_MULTI_2 (ADC_CCR_DUAL_2) +#define ADC_CCR_MULTI_3 (ADC_CCR_DUAL_3) +#define ADC_CCR_MULTI_4 (ADC_CCR_DUAL_4) + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1U << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2U << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ + +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1U << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2U << AES_CR_MODE_Pos) /*!< 0x00000010 */ + +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001U << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002U << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800U << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ + +#define AES_CR_CCFC_Pos (7U) +#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */ +#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ +#define AES_CR_ERRC_Pos (8U) +#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */ +#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ +#define AES_CR_CCFIE_Pos (9U) +#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */ +#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */ +#define AES_CR_ERRIE_Pos (10U) +#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ +#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ + +#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1U << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2U << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ + +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ + +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in last payload block */ +#define AES_CR_NPBLB_0 (0x1U << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2U << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4U << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8U << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0U) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0U) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0U) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0U) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0U) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* DMAMUX Controller */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DMAMUX_CxCR register **************/ +#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) +#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */ +#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ +#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ +#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ +#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ +#define DMAMUX_CxCR_SOIE_Pos (8U) +#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ +#define DMAMUX_CxCR_EGE_Pos (9U) +#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ +#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ +#define DMAMUX_CxCR_SE_Pos (16U) +#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ +#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ +#define DMAMUX_CxCR_SPOL_Pos (17U) +#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ +#define DMAMUX_CxCR_SPOL_0 (0x1U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_CxCR_SPOL_1 (0x2U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_CxCR_NBREQ_Pos (19U) +#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ +#define DMAMUX_CxCR_NBREQ_0 (0x01U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_CxCR_NBREQ_1 (0x02U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_CxCR_NBREQ_2 (0x04U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_CxCR_NBREQ_3 (0x08U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_CxCR_NBREQ_4 (0x10U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ +#define DMAMUX_CxCR_SYNC_ID_Pos (24U) +#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ +#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ +#define DMAMUX_CxCR_SYNC_ID_0 (0x01U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ +#define DMAMUX_CxCR_SYNC_ID_1 (0x02U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ +#define DMAMUX_CxCR_SYNC_ID_2 (0x04U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ +#define DMAMUX_CxCR_SYNC_ID_3 (0x08U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ +#define DMAMUX_CxCR_SYNC_ID_4 (0x10U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ + +/******************* Bits definition for DMAMUX_CSR register **************/ +#define DMAMUX_CSR_SOF0_Pos (0U) +#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ +#define DMAMUX_CSR_SOF1_Pos (1U) +#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ +#define DMAMUX_CSR_SOF2_Pos (2U) +#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ +#define DMAMUX_CSR_SOF3_Pos (3U) +#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */ +#define DMAMUX_CSR_SOF4_Pos (4U) +#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */ +#define DMAMUX_CSR_SOF5_Pos (5U) +#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */ +#define DMAMUX_CSR_SOF6_Pos (6U) +#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */ +#define DMAMUX_CSR_SOF7_Pos (7U) +#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */ +#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Synchronization Overrun Flag 7 */ +#define DMAMUX_CSR_SOF8_Pos (8U) +#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */ +#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Synchronization Overrun Flag 8 */ +#define DMAMUX_CSR_SOF9_Pos (9U) +#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */ +#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Synchronization Overrun Flag 9 */ +#define DMAMUX_CSR_SOF10_Pos (10U) +#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */ +#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Synchronization Overrun Flag 10 */ +#define DMAMUX_CSR_SOF11_Pos (11U) +#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */ +#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Synchronization Overrun Flag 11 */ +#define DMAMUX_CSR_SOF12_Pos (12U) +#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */ +#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Synchronization Overrun Flag 12 */ +#define DMAMUX_CSR_SOF13_Pos (13U) +#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */ +#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Synchronization Overrun Flag 13 */ + +/******************** Bits definition for DMAMUX_CFR register **************/ +#define DMAMUX_CFR_CSOF0_Pos (0U) +#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ +#define DMAMUX_CFR_CSOF1_Pos (1U) +#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ +#define DMAMUX_CFR_CSOF2_Pos (2U) +#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ +#define DMAMUX_CFR_CSOF3_Pos (3U) +#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */ +#define DMAMUX_CFR_CSOF4_Pos (4U) +#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */ +#define DMAMUX_CFR_CSOF5_Pos (5U) +#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */ +#define DMAMUX_CFR_CSOF6_Pos (6U) +#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */ +#define DMAMUX_CFR_CSOF7_Pos (7U) +#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */ +#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Clear Overrun Flag 7 */ +#define DMAMUX_CFR_CSOF8_Pos (8U) +#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */ +#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Clear Overrun Flag 8 */ +#define DMAMUX_CFR_CSOF9_Pos (9U) +#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */ +#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Clear Overrun Flag 9 */ +#define DMAMUX_CFR_CSOF10_Pos (10U) +#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */ +#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Clear Overrun Flag 10 */ +#define DMAMUX_CFR_CSOF11_Pos (11U) +#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */ +#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Clear Overrun Flag 11 */ +#define DMAMUX_CFR_CSOF12_Pos (12U) +#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */ +#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Clear Overrun Flag 12 */ +#define DMAMUX_CFR_CSOF13_Pos (13U) +#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */ +#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Clear Overrun Flag 13 */ + +/******************** Bits definition for DMAMUX_RGxCR register ************/ +#define DMAMUX_RGxCR_SIG_ID_Pos (0U) +#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ +#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ +#define DMAMUX_RGxCR_SIG_ID_0 (0x01U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGxCR_SIG_ID_1 (0x02U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGxCR_SIG_ID_2 (0x04U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGxCR_SIG_ID_3 (0x08U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGxCR_SIG_ID_4 (0x10U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_RGxCR_OIE_Pos (8U) +#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ +#define DMAMUX_RGxCR_GE_Pos (16U) +#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ +#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ +#define DMAMUX_RGxCR_GPOL_Pos (17U) +#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ +#define DMAMUX_RGxCR_GPOL_0 (0x1U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_RGxCR_GPOL_1 (0x2U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_RGxCR_GNBREQ_Pos (19U) +#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ +#define DMAMUX_RGxCR_GNBREQ_0 (0x01U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_RGxCR_GNBREQ_1 (0x02U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_RGxCR_GNBREQ_2 (0x04U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_RGxCR_GNBREQ_3 (0x08U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_RGxCR_GNBREQ_4 (0x10U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for DMAMUX_RGSR register **************/ +#define DMAMUX_RGSR_OF0_Pos (0U) +#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ +#define DMAMUX_RGSR_OF1_Pos (1U) +#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ +#define DMAMUX_RGSR_OF2_Pos (2U) +#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ +#define DMAMUX_RGSR_OF3_Pos (3U) +#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ + +/******************** Bits definition for DMAMUX_RGCFR register **************/ +#define DMAMUX_RGCFR_COF0_Pos (0U) +#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ +#define DMAMUX_RGCFR_COF1_Pos (1U) +#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ +#define DMAMUX_RGCFR_COF2_Pos (2U) +#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ +#define DMAMUX_RGCFR_COF3_Pos (3U) +#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT_Pos (0U) +#define EXTI_RTSR1_RT_Msk (0x803FFFFFUL << EXTI_RTSR1_RT_Pos) /*!< 0x803FFFFF */ +#define EXTI_RTSR1_RT EXTI_RTSR1_RT_Msk /*!< Rising trigger event configuration bit */ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR1_RT17_Pos (17U) +#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR1_RT18_Pos (18U) +#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR1_RT19_Pos (19U) +#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */ +#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_RTSR1_RT20_Pos (20U) +#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */ +#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ +#define EXTI_RTSR1_RT21_Pos (21U) +#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */ +#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ +#define EXTI_RTSR1_RT31_Pos (31U) +#define EXTI_RTSR1_RT31_Msk (0x1UL << EXTI_RTSR1_RT31_Pos) /*!< 0x80000000 */ +#define EXTI_RTSR1_RT31 EXTI_RTSR1_RT31_Msk /*!< Rising trigger event configuration bit of line 31 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT_Pos (0U) +#define EXTI_FTSR1_FT_Msk (0x803FFFFFUL << EXTI_FTSR1_FT_Pos) /*!< 0x803FFFFF */ +#define EXTI_FTSR1_FT EXTI_FTSR1_FT_Msk /*!< Falling trigger event configuration bit */ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR1_FT17_Pos (17U) +#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR1_FT18_Pos (18U) +#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR1_FT19_Pos (19U) +#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */ +#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI_Pos (0U) +#define EXTI_SWIER1_SWI_Msk (0x803FFFFFUL << EXTI_SWIER1_SWI_Pos) /*!< 0x803FFFFF */ +#define EXTI_SWIER1_SWI EXTI_SWIER1_SWI_Msk /*!< Software interrupt */ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER1_SWI17_Pos (17U) +#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER1_SWI18_Pos (18U) +#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER1_SWI19_Pos (19U) +#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */ +#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_PR1 register *******************/ +#define EXTI_PR1_PIF_Pos (0U) +#define EXTI_PR1_PIF_Msk (0x803FFFFFUL << EXTI_PR1_PIF_Pos) /*!< 0x803FFFFF */ +#define EXTI_PR1_PIF EXTI_PR1_PIF_Msk /*!< Pending bit */ +#define EXTI_PR1_PIF0_Pos (0U) +#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */ +#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */ +#define EXTI_PR1_PIF1_Pos (1U) +#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */ +#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */ +#define EXTI_PR1_PIF2_Pos (2U) +#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */ +#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */ +#define EXTI_PR1_PIF3_Pos (3U) +#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */ +#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */ +#define EXTI_PR1_PIF4_Pos (4U) +#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */ +#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */ +#define EXTI_PR1_PIF5_Pos (5U) +#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */ +#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */ +#define EXTI_PR1_PIF6_Pos (6U) +#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */ +#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */ +#define EXTI_PR1_PIF7_Pos (7U) +#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */ +#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */ +#define EXTI_PR1_PIF8_Pos (8U) +#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */ +#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */ +#define EXTI_PR1_PIF9_Pos (9U) +#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */ +#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */ +#define EXTI_PR1_PIF10_Pos (10U) +#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */ +#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */ +#define EXTI_PR1_PIF11_Pos (11U) +#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */ +#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */ +#define EXTI_PR1_PIF12_Pos (12U) +#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */ +#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */ +#define EXTI_PR1_PIF13_Pos (13U) +#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */ +#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */ +#define EXTI_PR1_PIF14_Pos (14U) +#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */ +#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */ +#define EXTI_PR1_PIF15_Pos (15U) +#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */ +#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */ +#define EXTI_PR1_PIF16_Pos (16U) +#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */ +#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */ +#define EXTI_PR1_PIF17_Pos (17U) +#define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos) /*!< 0x00020000 */ +#define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk /*!< Pending bit for line 17 */ +#define EXTI_PR1_PIF18_Pos (18U) +#define EXTI_PR1_PIF18_Msk (0x1UL << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */ +#define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */ +#define EXTI_PR1_PIF19_Pos (19U) +#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */ +#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */ + +/****************** Bit definition for EXTI_RTSR2 register ******************/ +#define EXTI_RTSR2_RT_Pos (0U) +#define EXTI_RTSR2_RT_Msk (0x302UL << EXTI_RTSR2_RT_Pos) /*!< 0x00000302 */ +#define EXTI_RTSR2_RT EXTI_RTSR2_RT_Msk /*!< Rising trigger event configuration bit */ +#define EXTI_RTSR2_RT33_Pos (1U) +#define EXTI_RTSR2_RT33_Msk (0x1UL << EXTI_RTSR2_RT33_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR2_RT33 EXTI_RTSR2_RT33_Msk /*!< Rising trigger event configuration bit of line 33 */ +#define EXTI_RTSR2_RT40_Pos (8U) +#define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger event configuration bit of line 40 */ +#define EXTI_RTSR2_RT41_Pos (9U) +#define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger event configuration bit of line 41 */ + +/****************** Bit definition for EXTI_FTSR2 register ******************/ +#define EXTI_FTSR2_FT_Pos (0U) +#define EXTI_FTSR2_FT_Msk (0x302UL << EXTI_FTSR2_FT_Pos) /*!< 0x00000302 */ +#define EXTI_FTSR2_FT EXTI_FTSR2_FT_Msk /*!< Falling trigger event configuration bit */ +#define EXTI_FTSR2_FT33_Pos (1U) +#define EXTI_FTSR2_FT33_Msk (0x1UL << EXTI_FTSR2_FT33_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR2_FT33 EXTI_FTSR2_FT33_Msk /*!< Falling trigger event configuration bit of line 33 */ +#define EXTI_FTSR2_FT40_Pos (8U) +#define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger event configuration bit of line 40 */ +#define EXTI_FTSR2_FT41_Pos (9U) +#define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger event configuration bit of line 41 */ + +/****************** Bit definition for EXTI_SWIER2 register *****************/ +#define EXTI_SWIER2_SWI_Pos (0U) +#define EXTI_SWIER2_SWI_Msk (0x302UL << EXTI_SWIER2_SWI_Pos) /*!< 0x00000302 */ +#define EXTI_SWIER2_SWI EXTI_SWIER2_SWI_Msk /*!< Falling trigger event configuration bit */ +#define EXTI_SWIER2_SWI33_Pos (1U) +#define EXTI_SWIER2_SWI33_Msk (0x1UL << EXTI_SWIER2_SWI33_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWI33_Msk /*!< Software Interrupt on line 33 */ +#define EXTI_SWIER2_SWI40_Pos (8U) +#define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */ +#define EXTI_SWIER2_SWI41_Pos (9U) +#define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */ + +/******************* Bit definition for EXTI_PR2 register *******************/ +#define EXTI_PR2_PIF_Pos (0U) +#define EXTI_PR2_PIF_Msk (0x302UL << EXTI_PR2_PIF_Pos) /*!< 0x00000302 */ +#define EXTI_PR2_PIF EXTI_PR2_PIF_Msk /*!< Pending bit */ +#define EXTI_PR2_PIF33_Pos (1U) +#define EXTI_PR2_PIF33_Msk (0x1UL << EXTI_PR2_PIF33_Pos) /*!< 0x00000002 */ +#define EXTI_PR2_PIF33 EXTI_PR2_PIF33_Msk /*!< Pending bit for line 33 */ +#define EXTI_PR2_PIF40_Pos (8U) +#define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos) /*!< 0x00000100 */ +#define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk /*!< Pending bit for line 40 */ +#define EXTI_PR2_PIF41_Pos (9U) +#define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos) /*!< 0x00000200 */ +#define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk /*!< Pending bit for line 41 */ + +/******************** Bits definition for EXTI_IMR1 register ****************/ +#define EXTI_IMR1_Pos (0U) +#define EXTI_IMR1_Msk (0xFFFFFFFFUL << EXTI_IMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_IMR1_IM EXTI_IMR1_Msk /*!< CPU1 wakeup with interrupt Mask on Event */ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< CPU1 Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< CPU1 Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< CPU1 Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< CPU1 Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< CPU1 Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< CPU1 Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< CPU1 Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< CPU1 Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< CPU1 Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< CPU1 Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< CPU1 Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< CPU1 Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< CPU1 Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< CPU1 Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< CPU1 Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< CPU1 Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< CPU1 Interrupt Mask on line 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< CPU1 Interrupt Mask on line 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< CPU1 Interrupt Mask on line 18 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< CPU1 Interrupt Mask on line 19 */ +#define EXTI_IMR1_IM22_Pos (22U) +#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< CPU1 Interrupt Mask on line 22 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< CPU1 Interrupt Mask on line 24 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< CPU1 Interrupt Mask on line 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< CPU1 Interrupt Mask on line 30 */ + +/******************** Bits definition for EXTI_EMR1 register ****************/ +#define EXTI_EMR1_Pos (0U) +#define EXTI_EMR1_Msk (0x003EFFFFUL << EXTI_EMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_EMR1_EM EXTI_EMR1_Msk /*!< CPU1 Event Mask */ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< CPU1 Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< CPU1 Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< CPU1 Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< CPU1 Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< CPU1 Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< CPU1 Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< CPU1 Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< CPU1 Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< CPU1 Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< CPU1 Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< CPU1 Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< CPU1 Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< CPU1 Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< CPU1 Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< CPU1 Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< CPU1 Event Mask on line 15 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< CPU1 Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< CPU1 Event Mask on line 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< CPU1 Event Mask on line 19 */ + +/******************** Bits definition for EXTI_IMR2 register ****************/ +#define EXTI_IMR2_Pos (0U) +#define EXTI_IMR2_Msk (0x0001FFFFUL << EXTI_IMR2_Pos) /*!< 0x0001FFFF */ +#define EXTI_IMR2_IM EXTI_IMR2_Msk /*!< CPU1 Interrupt Mask */ +#define EXTI_IMR2_IM33_Pos (1U) +#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU1 Interrupt Mask on line 33 */ +#define EXTI_IMR2_IM36_Pos (4U) +#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */ +#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< CPU1 Interrupt Mask on line 36 */ +#define EXTI_IMR2_IM37_Pos (5U) +#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */ +#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< CPU1 Interrupt Mask on line 37 */ +#define EXTI_IMR2_IM38_Pos (6U) +#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */ +#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< CPU1 Interrupt Mask on line 38 */ +#define EXTI_IMR2_IM39_Pos (7U) +#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */ +#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< CPU1 Interrupt Mask on line 39 */ +#define EXTI_IMR2_IM40_Pos (8U) +#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */ +#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< CPU1 Interrupt Mask on line 40 */ +#define EXTI_IMR2_IM41_Pos (9U) +#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */ +#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< CPU1 Interrupt Mask on line 41 */ +#define EXTI_IMR2_IM42_Pos (10U) +#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */ +#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< CPU1 Interrupt Mask on line 42 */ +#define EXTI_IMR2_IM44_Pos (12U) +#define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */ +#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< CPU1 Interrupt Mask on line 44 */ +#define EXTI_IMR2_IM45_Pos (13U) +#define EXTI_IMR2_IM45_Msk (0x1UL << EXTI_IMR2_IM45_Pos) /*!< 0x00002000 */ +#define EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk /*!< CPU1 Interrupt Mask on line 45 */ +#define EXTI_IMR2_IM46_Pos (14U) +#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */ +#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< CPU1 Interrupt Mask on line 46 */ +#define EXTI_IMR2_IM48_Pos (16U) +#define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */ +#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< CPU1 Interrupt Mask on line 48 */ + +/******************** Bits definition for EXTI_EMR2 register ****************/ +#define EXTI_EMR2_Pos (0U) +#define EXTI_EMR2_Msk (0x00000300UL << EXTI_EMR2_Pos) /*!< 0x000003000 */ +#define EXTI_EMR2_EM EXTI_EMR2_Msk /*!< CPU1 Interrupt Mask */ +#define EXTI_EMR2_EM40_Pos (8U) +#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */ +#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< CPU1 Event Mask on line 40 */ +#define EXTI_EMR2_EM41_Pos (9U) +#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */ +#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< CPU1 Event Mask on line 41 */ + +/******************** Bits definition for EXTI_C2IMR1 register **************/ +#define EXTI_C2IMR1_Pos (0U) +#define EXTI_C2IMR1_Msk (0xFFFFFFFFUL << EXTI_C2IMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_C2IMR1_IM EXTI_C2IMR1_Msk /*!< CPU2 wakeup with interrupt Mask on Event */ +#define EXTI_C2IMR1_IM0_Pos (0U) +#define EXTI_C2IMR1_IM0_Msk (0x1UL << EXTI_C2IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_C2IMR1_IM0 EXTI_C2IMR1_IM0_Msk /*!< CPU2 Interrupt Mask on line 0 */ +#define EXTI_C2IMR1_IM1_Pos (1U) +#define EXTI_C2IMR1_IM1_Msk (0x1UL << EXTI_C2IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_C2IMR1_IM1 EXTI_C2IMR1_IM1_Msk /*!< CPU2 Interrupt Mask on line 1 */ +#define EXTI_C2IMR1_IM2_Pos (2U) +#define EXTI_C2IMR1_IM2_Msk (0x1UL << EXTI_C2IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_C2IMR1_IM2 EXTI_C2IMR1_IM2_Msk /*!< CPU2 Interrupt Mask on line 2 */ +#define EXTI_C2IMR1_IM3_Pos (3U) +#define EXTI_C2IMR1_IM3_Msk (0x1UL << EXTI_C2IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_C2IMR1_IM3 EXTI_C2IMR1_IM3_Msk /*!< CPU2 Interrupt Mask on line 3 */ +#define EXTI_C2IMR1_IM4_Pos (4U) +#define EXTI_C2IMR1_IM4_Msk (0x1UL << EXTI_C2IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_C2IMR1_IM4 EXTI_C2IMR1_IM4_Msk /*!< CPU2 Interrupt Mask on line 4 */ +#define EXTI_C2IMR1_IM5_Pos (5U) +#define EXTI_C2IMR1_IM5_Msk (0x1UL << EXTI_C2IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_C2IMR1_IM5 EXTI_C2IMR1_IM5_Msk /*!< CPU2 Interrupt Mask on line 5 */ +#define EXTI_C2IMR1_IM6_Pos (6U) +#define EXTI_C2IMR1_IM6_Msk (0x1UL << EXTI_C2IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_C2IMR1_IM6 EXTI_C2IMR1_IM6_Msk /*!< CPU2 Interrupt Mask on line 6 */ +#define EXTI_C2IMR1_IM7_Pos (7U) +#define EXTI_C2IMR1_IM7_Msk (0x1UL << EXTI_C2IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_C2IMR1_IM7 EXTI_C2IMR1_IM7_Msk /*!< CPU2 Interrupt Mask on line 7 */ +#define EXTI_C2IMR1_IM8_Pos (8U) +#define EXTI_C2IMR1_IM8_Msk (0x1UL << EXTI_C2IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_C2IMR1_IM8 EXTI_C2IMR1_IM8_Msk /*!< CPU2 Interrupt Mask on line 8 */ +#define EXTI_C2IMR1_IM9_Pos (9U) +#define EXTI_C2IMR1_IM9_Msk (0x1UL << EXTI_C2IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_C2IMR1_IM9 EXTI_C2IMR1_IM9_Msk /*!< CPU2 Interrupt Mask on line 9 */ +#define EXTI_C2IMR1_IM10_Pos (10U) +#define EXTI_C2IMR1_IM10_Msk (0x1UL << EXTI_C2IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_C2IMR1_IM10 EXTI_C2IMR1_IM10_Msk /*!< CPU2 Interrupt Mask on line 10 */ +#define EXTI_C2IMR1_IM11_Pos (11U) +#define EXTI_C2IMR1_IM11_Msk (0x1UL << EXTI_C2IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_C2IMR1_IM11 EXTI_C2IMR1_IM11_Msk /*!< CPU2 Interrupt Mask on line 11 */ +#define EXTI_C2IMR1_IM12_Pos (12U) +#define EXTI_C2IMR1_IM12_Msk (0x1UL << EXTI_C2IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_C2IMR1_IM12 EXTI_C2IMR1_IM12_Msk /*!< CPU2 Interrupt Mask on line 12 */ +#define EXTI_C2IMR1_IM13_Pos (13U) +#define EXTI_C2IMR1_IM13_Msk (0x1UL << EXTI_C2IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_C2IMR1_IM13 EXTI_C2IMR1_IM13_Msk /*!< CPU2 Interrupt Mask on line 13 */ +#define EXTI_C2IMR1_IM14_Pos (14U) +#define EXTI_C2IMR1_IM14_Msk (0x1UL << EXTI_C2IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_C2IMR1_IM14 EXTI_C2IMR1_IM14_Msk /*!< CPU2 Interrupt Mask on line 14 */ +#define EXTI_C2IMR1_IM15_Pos (15U) +#define EXTI_C2IMR1_IM15_Msk (0x1UL << EXTI_C2IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_C2IMR1_IM15 EXTI_C2IMR1_IM15_Msk /*!< CPU2 Interrupt Mask on line 15 */ +#define EXTI_C2IMR1_IM16_Pos (16U) +#define EXTI_C2IMR1_IM16_Msk (0x1UL << EXTI_C2IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_C2IMR1_IM16 EXTI_C2IMR1_IM16_Msk /*!< CPU2 Interrupt Mask on line 16 */ +#define EXTI_C2IMR1_IM17_Pos (17U) +#define EXTI_C2IMR1_IM17_Msk (0x1UL << EXTI_C2IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_C2IMR1_IM17 EXTI_C2IMR1_IM17_Msk /*!< CPU2 Interrupt Mask on line 17 */ +#define EXTI_C2IMR1_IM18_Pos (18U) +#define EXTI_C2IMR1_IM18_Msk (0x1UL << EXTI_C2IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_C2IMR1_IM18 EXTI_C2IMR1_IM18_Msk /*!< CPU2 Interrupt Mask on line 18 */ +#define EXTI_C2IMR1_IM19_Pos (19U) +#define EXTI_C2IMR1_IM19_Msk (0x1UL << EXTI_C2IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_C2IMR1_IM19 EXTI_C2IMR1_IM19_Msk /*!< CPU2 Interrupt Mask on line 19 */ +#define EXTI_C2IMR1_IM22_Pos (22U) +#define EXTI_C2IMR1_IM22_Msk (0x1UL << EXTI_C2IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_C2IMR1_IM22 EXTI_C2IMR1_IM22_Msk /*!< CPU2 Interrupt Mask on line 22 */ +#define EXTI_C2IMR1_IM24_Pos (24U) +#define EXTI_C2IMR1_IM24_Msk (0x1UL << EXTI_C2IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_C2IMR1_IM24 EXTI_C2IMR1_IM24_Msk /*!< CPU2 Interrupt Mask on line 24 */ +#define EXTI_C2IMR1_IM29_Pos (29U) +#define EXTI_C2IMR1_IM29_Msk (0x1UL << EXTI_C2IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_C2IMR1_IM29 EXTI_C2IMR1_IM29_Msk /*!< CPU2 Interrupt Mask on line 29 */ +#define EXTI_C2IMR1_IM30_Pos (30U) +#define EXTI_C2IMR1_IM30_Msk (0x1UL << EXTI_C2IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_C2IMR1_IM30 EXTI_C2IMR1_IM30_Msk /*!< CPU2 Interrupt Mask on line 30 */ +/******************** Bits definition for EXTI_C2EMR1 register **************/ +#define EXTI_C2EMR1_Pos (0U) +#define EXTI_C2EMR1_Msk (0x003EFFFFUL << EXTI_C2EMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_C2EMR1_EM EXTI_C2EMR1_Msk /*!< CPU2 Event Mask */ +#define EXTI_C2EMR1_EM0_Pos (0U) +#define EXTI_C2EMR1_EM0_Msk (0x1UL << EXTI_C2EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_C2EMR1_EM0 EXTI_C2EMR1_EM0_Msk /*!< CPU2 Event Mask on line 0 */ +#define EXTI_C2EMR1_EM1_Pos (1U) +#define EXTI_C2EMR1_EM1_Msk (0x1UL << EXTI_C2EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_C2EMR1_EM1 EXTI_C2EMR1_EM1_Msk /*!< CPU2 Event Mask on line 1 */ +#define EXTI_C2EMR1_EM2_Pos (2U) +#define EXTI_C2EMR1_EM2_Msk (0x1UL << EXTI_C2EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_C2EMR1_EM2 EXTI_C2EMR1_EM2_Msk /*!< CPU2 Event Mask on line 2 */ +#define EXTI_C2EMR1_EM3_Pos (3U) +#define EXTI_C2EMR1_EM3_Msk (0x1UL << EXTI_C2EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_C2EMR1_EM3 EXTI_C2EMR1_EM3_Msk /*!< CPU2 Event Mask on line 3 */ +#define EXTI_C2EMR1_EM4_Pos (4U) +#define EXTI_C2EMR1_EM4_Msk (0x1UL << EXTI_C2EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_C2EMR1_EM4 EXTI_C2EMR1_EM4_Msk /*!< CPU2 Event Mask on line 4 */ +#define EXTI_C2EMR1_EM5_Pos (5U) +#define EXTI_C2EMR1_EM5_Msk (0x1UL << EXTI_C2EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_C2EMR1_EM5 EXTI_C2EMR1_EM5_Msk /*!< CPU2 Event Mask on line 5 */ +#define EXTI_C2EMR1_EM6_Pos (6U) +#define EXTI_C2EMR1_EM6_Msk (0x1UL << EXTI_C2EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_C2EMR1_EM6 EXTI_C2EMR1_EM6_Msk /*!< CPU2 Event Mask on line 6 */ +#define EXTI_C2EMR1_EM7_Pos (7U) +#define EXTI_C2EMR1_EM7_Msk (0x1UL << EXTI_C2EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_C2EMR1_EM7 EXTI_C2EMR1_EM7_Msk /*!< CPU2 Event Mask on line 7 */ +#define EXTI_C2EMR1_EM8_Pos (8U) +#define EXTI_C2EMR1_EM8_Msk (0x1UL << EXTI_C2EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_C2EMR1_EM8 EXTI_C2EMR1_EM8_Msk /*!< CPU2 Event Mask on line 8 */ +#define EXTI_C2EMR1_EM9_Pos (9U) +#define EXTI_C2EMR1_EM9_Msk (0x1UL << EXTI_C2EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_C2EMR1_EM9 EXTI_C2EMR1_EM9_Msk /*!< CPU2 Event Mask on line 9 */ +#define EXTI_C2EMR1_EM10_Pos (10U) +#define EXTI_C2EMR1_EM10_Msk (0x1UL << EXTI_C2EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_C2EMR1_EM10 EXTI_C2EMR1_EM10_Msk /*!< CPU2 Event Mask on line 10 */ +#define EXTI_C2EMR1_EM11_Pos (11U) +#define EXTI_C2EMR1_EM11_Msk (0x1UL << EXTI_C2EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_C2EMR1_EM11 EXTI_C2EMR1_EM11_Msk /*!< CPU2 Event Mask on line 11 */ +#define EXTI_C2EMR1_EM12_Pos (12U) +#define EXTI_C2EMR1_EM12_Msk (0x1UL << EXTI_C2EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_C2EMR1_EM12 EXTI_C2EMR1_EM12_Msk /*!< CPU2 Event Mask on line 12 */ +#define EXTI_C2EMR1_EM13_Pos (13U) +#define EXTI_C2EMR1_EM13_Msk (0x1UL << EXTI_C2EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_C2EMR1_EM13 EXTI_C2EMR1_EM13_Msk /*!< CPU2 Event Mask on line 13 */ +#define EXTI_C2EMR1_EM14_Pos (14U) +#define EXTI_C2EMR1_EM14_Msk (0x1UL << EXTI_C2EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_C2EMR1_EM14 EXTI_C2EMR1_EM14_Msk /*!< CPU2 Event Mask on line 14 */ +#define EXTI_C2EMR1_EM15_Pos (15U) +#define EXTI_C2EMR1_EM15_Msk (0x1UL << EXTI_C2EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_C2EMR1_EM15 EXTI_C2EMR1_EM15_Msk /*!< CPU2 Event Mask on line 15 */ +#define EXTI_C2EMR1_EM17_Pos (17U) +#define EXTI_C2EMR1_EM17_Msk (0x1UL << EXTI_C2EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_C2EMR1_EM17 EXTI_C2EMR1_EM17_Msk /*!< CPU2 Event Mask on line 17 */ +#define EXTI_C2EMR1_EM18_Pos (18U) +#define EXTI_C2EMR1_EM18_Msk (0x1UL << EXTI_C2EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_C2EMR1_EM18 EXTI_C2EMR1_EM18_Msk /*!< CPU2 Event Mask on line 18 */ +#define EXTI_C2EMR1_EM19_Pos (19U) +#define EXTI_C2EMR1_EM19_Msk (0x1UL << EXTI_C2EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_C2EMR1_EM19 EXTI_C2EMR1_EM19_Msk /*!< CPU2 Event Mask on line 19 */ + +/******************** Bits definition for EXTI_C2IMR2 register **************/ +#define EXTI_C2IMR2_Pos (0U) +#define EXTI_C2IMR2_Msk (0x0001FFFFUL << EXTI_C2IMR2_Pos) /*!< 0x0001FFFF */ +#define EXTI_C2IMR2_IM EXTI_C2IMR2_Msk /*!< CPU2 Interrupt Mask */ +#define EXTI_C2IMR2_IM33_Pos (1U) +#define EXTI_C2IMR2_IM33_Msk (0x1UL << EXTI_C2IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_C2IMR2_IM33 EXTI_C2IMR2_IM33_Msk /*!< CPU2 Interrupt Mask on line 33 */ +#define EXTI_C2IMR2_IM36_Pos (4U) +#define EXTI_C2IMR2_IM36_Msk (0x1UL << EXTI_C2IMR2_IM36_Pos) /*!< 0x00000010 */ +#define EXTI_C2IMR2_IM36 EXTI_C2IMR2_IM36_Msk /*!< CPU2 Interrupt Mask on line 36 */ +#define EXTI_C2IMR2_IM37_Pos (5U) +#define EXTI_C2IMR2_IM37_Msk (0x1UL << EXTI_C2IMR2_IM37_Pos) /*!< 0x00000020 */ +#define EXTI_C2IMR2_IM37 EXTI_C2IMR2_IM37_Msk /*!< CPU2 Interrupt Mask on line 37 */ +#define EXTI_C2IMR2_IM38_Pos (6U) +#define EXTI_C2IMR2_IM38_Msk (0x1UL << EXTI_C2IMR2_IM38_Pos) /*!< 0x00000040 */ +#define EXTI_C2IMR2_IM38 EXTI_C2IMR2_IM38_Msk /*!< CPU2 Interrupt Mask on line 38 */ +#define EXTI_C2IMR2_IM39_Pos (7U) +#define EXTI_C2IMR2_IM39_Msk (0x1UL << EXTI_C2IMR2_IM39_Pos) /*!< 0x00000080 */ +#define EXTI_C2IMR2_IM39 EXTI_C2IMR2_IM39_Msk /*!< CPU2 Interrupt Mask on line 39 */ +#define EXTI_C2IMR2_IM40_Pos (8U) +#define EXTI_C2IMR2_IM40_Msk (0x1UL << EXTI_C2IMR2_IM40_Pos) /*!< 0x00000100 */ +#define EXTI_C2IMR2_IM40 EXTI_C2IMR2_IM40_Msk /*!< CPU2 Interrupt Mask on line 40 */ +#define EXTI_C2IMR2_IM41_Pos (9U) +#define EXTI_C2IMR2_IM41_Msk (0x1UL << EXTI_C2IMR2_IM41_Pos) /*!< 0x00000200 */ +#define EXTI_C2IMR2_IM41 EXTI_C2IMR2_IM41_Msk /*!< CPU2 Interrupt Mask on line 41 */ +#define EXTI_C2IMR2_IM42_Pos (10U) +#define EXTI_C2IMR2_IM42_Msk (0x1UL << EXTI_C2IMR2_IM42_Pos) /*!< 0x00000400 */ +#define EXTI_C2IMR2_IM42 EXTI_C2IMR2_IM42_Msk /*!< CPU2 Interrupt Mask on line 42 */ +#define EXTI_C2IMR2_IM44_Pos (12U) +#define EXTI_C2IMR2_IM44_Msk (0x1UL << EXTI_C2IMR2_IM44_Pos) /*!< 0x00001000 */ +#define EXTI_C2IMR2_IM44 EXTI_C2IMR2_IM44_Msk /*!< CPU2 Interrupt Mask on line 44 */ +#define EXTI_C2IMR2_IM45_Pos (13U) +#define EXTI_C2IMR2_IM45_Msk (0x1UL << EXTI_C2IMR2_IM45_Pos) /*!< 0x00002000 */ +#define EXTI_C2IMR2_IM45 EXTI_C2IMR2_IM45_Msk /*!< CPU2 Interrupt Mask on line 45 */ +#define EXTI_C2IMR2_IM46_Pos (14U) +#define EXTI_C2IMR2_IM46_Msk (0x1UL << EXTI_C2IMR2_IM46_Pos) /*!< 0x00004000 */ +#define EXTI_C2IMR2_IM46 EXTI_C2IMR2_IM46_Msk /*!< CPU2 Interrupt Mask on line 46 */ +#define EXTI_C2IMR2_IM48_Pos (16U) +#define EXTI_C2IMR2_IM48_Msk (0x1UL << EXTI_C2IMR2_IM48_Pos) /*!< 0x00010000 */ +#define EXTI_C2IMR2_IM48 EXTI_C2IMR2_IM48_Msk /*!< CPU2 Interrupt Mask on line 48 */ + +/******************** Bits definition for EXTI_C2EMR2 register **************/ +#define EXTI_C2EMR2_Pos (8U) +#define EXTI_C2EMR2_Msk (0x00000300UL << EXTI_C2EMR2_Pos) /*!< 0x000003000 */ +#define EXTI_C2EMR2_EM EXTI_C2EMR2_Msk /*!< CPU2 Interrupt Mask */ +#define EXTI_C2EMR2_EM40_Pos (8U) +#define EXTI_C2EMR2_EM40_Msk (0x1UL << EXTI_C2EMR2_EM40_Pos) /*!< 0x00000100 */ +#define EXTI_C2EMR2_EM40 EXTI_C2EMR2_EM40_Msk /*!< CPU2 Event Mask on line 40 */ +#define EXTI_C2EMR2_EM41_Pos (9U) +#define EXTI_C2EMR2_EM41_Msk (0x1UL << EXTI_C2EMR2_EM41_Pos) /*!< 0x00000200 */ +#define EXTI_C2EMR2_EM41 EXTI_C2EMR2_EM41_Msk /*!< CPU2 Event Mask on line 41 */ + +/******************************************************************************/ +/* */ +/* Public Key Accelerator (PKA) */ +/* */ +/******************************************************************************/ + +/******************* Bits definition for PKA_CR register **************/ +#define PKA_CR_EN_Pos (0U) +#define PKA_CR_EN_Msk (0x1UL << PKA_CR_EN_Pos) /*!< 0x00000001 */ +#define PKA_CR_EN PKA_CR_EN_Msk /*!< PKA enable */ +#define PKA_CR_START_Pos (1U) +#define PKA_CR_START_Msk (0x1UL << PKA_CR_START_Pos) /*!< 0x00000002 */ +#define PKA_CR_START PKA_CR_START_Msk /*!< Start operation */ +#define PKA_CR_MODE_Pos (8U) +#define PKA_CR_MODE_Msk (0x3FUL << PKA_CR_MODE_Pos) /*!< 0x00003F00 */ +#define PKA_CR_MODE PKA_CR_MODE_Msk /*!< MODE[5:0] PKA operation code */ +#define PKA_CR_MODE_0 (0x01U << PKA_CR_MODE_Pos) /*!< 0x00000100 */ +#define PKA_CR_MODE_1 (0x02U << PKA_CR_MODE_Pos) /*!< 0x00000200 */ +#define PKA_CR_MODE_2 (0x04U << PKA_CR_MODE_Pos) /*!< 0x00000400 */ +#define PKA_CR_MODE_3 (0x08U << PKA_CR_MODE_Pos) /*!< 0x00000800 */ +#define PKA_CR_MODE_4 (0x10U << PKA_CR_MODE_Pos) /*!< 0x00001000 */ +#define PKA_CR_MODE_5 (0x20U << PKA_CR_MODE_Pos) /*!< 0x00002000 */ +#define PKA_CR_PROCENDIE_Pos (17U) +#define PKA_CR_PROCENDIE_Msk (0x1UL << PKA_CR_PROCENDIE_Pos) /*!< 0x00020000 */ +#define PKA_CR_PROCENDIE PKA_CR_PROCENDIE_Msk /*!< End of operation interrupt enable */ +#define PKA_CR_RAMERRIE_Pos (19U) +#define PKA_CR_RAMERRIE_Msk (0x1UL << PKA_CR_RAMERRIE_Pos) /*!< 0x00080000 */ +#define PKA_CR_RAMERRIE PKA_CR_RAMERRIE_Msk /*!< RAM error interrupt enable */ +#define PKA_CR_ADDRERRIE_Pos (20U) +#define PKA_CR_ADDRERRIE_Msk (0x1UL << PKA_CR_ADDRERRIE_Pos) /*!< 0x00100000 */ +#define PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE_Msk /*!< RAM error interrupt enable */ + +/******************* Bits definition for PKA_SR register **************/ +#define PKA_SR_BUSY_Pos (16U) +#define PKA_SR_BUSY_Msk (0x1UL << PKA_SR_BUSY_Pos) /*!< 0x00010000 */ +#define PKA_SR_BUSY PKA_SR_BUSY_Msk /*!< PKA operation is in progress */ +#define PKA_SR_PROCENDF_Pos (17U) +#define PKA_SR_PROCENDF_Msk (0x1UL << PKA_SR_PROCENDF_Pos) /*!< 0x00020000 */ +#define PKA_SR_PROCENDF PKA_SR_PROCENDF_Msk /*!< PKA end of operation flag */ +#define PKA_SR_RAMERRF_Pos (19U) +#define PKA_SR_RAMERRF_Msk (0x1UL << PKA_SR_RAMERRF_Pos) /*!< 0x00080000 */ +#define PKA_SR_RAMERRF PKA_SR_RAMERRF_Msk /*!< PKA RAM error flag */ +#define PKA_SR_ADDRERRF_Pos (20U) +#define PKA_SR_ADDRERRF_Msk (0x1UL << PKA_SR_ADDRERRF_Pos) /*!< 0x00100000 */ +#define PKA_SR_ADDRERRF PKA_SR_ADDRERRF_Msk /*!< Address error flag */ + +/******************* Bits definition for PKA_CLRFR register **************/ +#define PKA_CLRFR_PROCENDFC_Pos (17U) +#define PKA_CLRFR_PROCENDFC_Msk (0x1UL << PKA_CLRFR_PROCENDFC_Pos) /*!< 0x00020000 */ +#define PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC_Msk /*!< Clear PKA end of operation flag */ +#define PKA_CLRFR_RAMERRFC_Pos (19U) +#define PKA_CLRFR_RAMERRFC_Msk (0x1UL << PKA_CLRFR_RAMERRFC_Pos) /*!< 0x00080000 */ +#define PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC_Msk /*!< Clear PKA RAM error flag */ +#define PKA_CLRFR_ADDRERRFC_Pos (20U) +#define PKA_CLRFR_ADDRERRFC_Msk (0x1UL << PKA_CLRFR_ADDRERRFC_Pos) /*!< 0x00100000 */ +#define PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC_Msk /*!< Clear address error flag */ + +/******************* Bits definition for PKA RAM *************************/ +#define PKA_RAM_OFFSET 0x400U /*!< PKA RAM address offset */ + +/* Compute Montgomery parameter input data */ +#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1 ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 1 */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 2 */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 3 */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1 ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Output last double X1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output last double Y1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1 ((0xE90U - PKA_RAM_OFFSET)>>2) /*!< Output last double Z1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2 ((0xEE4U - PKA_RAM_OFFSET)>>2) /*!< Output check point X2 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2 ((0xF38U - PKA_RAM_OFFSET)>>2) /*!< Output check point Y2 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2 ((0xF8CU - PKA_RAM_OFFSET)>>2) /*!< Output check point Z2 coordinate */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x7FCU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0xE94U - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0xEE8U - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x700U - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x754U - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x103CU - PKA_RAM_OFFSET)>>2) /*!< Output final point kP X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1090U - PKA_RAM_OFFSET)>>2) /*!< Output final point kP Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x45CU - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x4B8U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x5E8U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x63CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0xF40U - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0xF94U - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x1098U - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0xFE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x65CU - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x7ECU - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x97CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0xEECU - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic substraction input data */ +#define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic substraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular substraction input data */ +#define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular substraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_ICEN_Pos (9U) +#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk /*!< Instruction cache enable */ +#define FLASH_ACR_DCEN_Pos (10U) +#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */ +#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk /*!< Data cache enable */ +#define FLASH_ACR_ICRST_Pos (11U) +#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk /*!< Instruction cache reset */ +#define FLASH_ACR_DCRST_Pos (12U) +#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk /*!< Data cache reset */ +#define FLASH_ACR_PES_Pos (15U) +#define FLASH_ACR_PES_Msk (0x1UL << FLASH_ACR_PES_Pos) /*!< 0x00008000 */ +#define FLASH_ACR_PES FLASH_ACR_PES_Msk /*!< Program/erase suspend request */ +#define FLASH_ACR_EMPTY_Pos (16U) +#define FLASH_ACR_EMPTY_Msk (0x1UL << FLASH_ACR_EMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_EMPTY FLASH_ACR_EMPTY_Msk /*!< Flash use area empty */ + +#define FLASH_ACR_LATENCY_0WS (0x0UL << FLASH_ACR_LATENCY_Pos) /*!< FLASH Zero wait state */ +#define FLASH_ACR_LATENCY_1WS (FLASH_ACR_LATENCY_0 << FLASH_ACR_LATENCY_Pos) /*!< FLASH One wait state */ +#define FLASH_ACR_LATENCY_2WS (FLASH_ACR_LATENCY_1 << FLASH_ACR_LATENCY_Pos) /*!< FLASH Two wait states */ +#define FLASH_ACR_LATENCY_3WS ((FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) << FLASH_ACR_LATENCY_Pos) /*!< FLASH Three wait states */ + +/******************* Bits definition for FLASH_SR register ******************/ +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of Operation */ +#define FLASH_SR_OPERR_Pos (1U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Operation error */ +#define FLASH_SR_PROGERR_Pos (3U) +#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk /*!< Programming error */ +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */ +#define FLASH_SR_PGAERR_Pos (5U) +#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming alignment error */ +#define FLASH_SR_SIZERR_Pos (6U) +#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ +#define FLASH_SR_PGSERR_Pos (7U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error */ +#define FLASH_SR_MISERR_Pos (8U) +#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk /*!< Fast programming data miss error */ +#define FLASH_SR_FASTERR_Pos (9U) +#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk /*!< Fast programming error */ +#define FLASH_SR_OPTNV_Pos (13U) +#define FLASH_SR_OPTNV_Msk (0x1UL << FLASH_SR_OPTNV_Pos) /*!< 0x00002000 */ +#define FLASH_SR_OPTNV FLASH_SR_OPTNV_Msk /*!< User option OPTVAL indication */ +#define FLASH_SR_RDERR_Pos (14U) +#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< PCROP read error */ +#define FLASH_SR_OPTVERR_Pos (15U) +#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option validity error */ +#define FLASH_SR_BSY_Pos (16U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Flash Busy */ +#define FLASH_SR_CFGBSY_Pos (18U) +#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk /*!< Programming or erase configuration busy */ +#define FLASH_SR_PESD_Pos (19U) +#define FLASH_SR_PESD_Msk (0x1UL << FLASH_SR_PESD_Pos) /*!< 0x00080000 */ +#define FLASH_SR_PESD FLASH_SR_PESD_Msk /*!< Programming/erase operation suspended */ + +/******************* Bits definition for FLASH_CR register ******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Flash programming */ +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page erase */ +#define FLASH_CR_MER_Pos (2U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ +#define FLASH_CR_PNB_Pos (3U) +#define FLASH_CR_PNB_Msk (0xFFUL << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk /*!< Page number selection mask */ +#define FLASH_CR_STRT_Pos (16U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start an erase operation */ +#define FLASH_CR_OPTSTRT_Pos (17U) +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk /*!< Options modification start */ +#define FLASH_CR_FSTPG_Pos (18U) +#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk /*!< Fast programming */ +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error interrupt enable */ +#define FLASH_CR_RDERRIE_Pos (26U) +#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk /*!< PCROP read error interrupt enable */ +#define FLASH_CR_OBL_LAUNCH_Pos (27U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_CR_OPTLOCK_Pos (30U) +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk /*!< Options lock */ +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Flash control register lock */ + +/******************* Bits definition for FLASH_ECCR register ****************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0001FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< double-word address ECC fail */ +#define FLASH_ECCR_SYSF_ECC_Pos (20U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System flash ECC fail */ +#define FLASH_ECCR_ECCCIE_Pos (24U) +#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_CPUID_Pos (26U) +#define FLASH_ECCR_CPUID_Msk (0x7UL << FLASH_ECCR_CPUID_Pos) /*!< 0x1C000000 */ +#define FLASH_ECCR_CPUID FLASH_ECCR_CPUID_Msk /*!< CPU identification */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPTR register ****************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Read protection level */ +#define FLASH_OPTR_ESE_Pos (8U) +#define FLASH_OPTR_ESE_Msk (0x1UL << FLASH_OPTR_ESE_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_ESE FLASH_OPTR_ESE_Msk /*!< Security enable */ +#define FLASH_OPTR_BOR_LEV_Pos (9U) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000E00 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset level mask */ +#define FLASH_OPTR_BOR_LEV_0 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000800 */ +#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< Reset option in Stop mode */ +#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< Reset option in Standby mode */ +#define FLASH_OPTR_nRST_SHDW_Pos (14U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< Reset option in Shutdown mode */ +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter option in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter option in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_nBOOT1_Pos (23U) +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk /*!< Boot Configuration */ +#define FLASH_OPTR_SRAM2PE_Pos (24U) +#define FLASH_OPTR_SRAM2PE_Msk (0x1UL << FLASH_OPTR_SRAM2PE_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2PE FLASH_OPTR_SRAM2PE_Msk /*!< SRAM2 parity check enable */ +#define FLASH_OPTR_SRAM2RST_Pos (25U) +#define FLASH_OPTR_SRAM2RST_Msk (0x1UL << FLASH_OPTR_SRAM2RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2RST FLASH_OPTR_SRAM2RST_Msk /*!< SRAM2 erase option when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< BOOT0 option bit */ +#define FLASH_OPTR_AGC_TRIM_Pos (29U) +#define FLASH_OPTR_AGC_TRIM_Msk (0x7UL << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0xE0000000 */ +#define FLASH_OPTR_AGC_TRIM FLASH_OPTR_AGC_TRIM_Msk /*!< Automatic Gain Control trimming mask */ +#define FLASH_OPTR_AGC_TRIM_0 (0x1U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_AGC_TRIM_1 (0x2U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_AGC_TRIM_2 (0x4U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for FLASH_PCROP1ASR register ************/ +#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U) +#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x1FFUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x000001FF */ +#define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk /*!< PCROP area A start offset */ + +/****************** Bits definition for FLASH_PCROP1AER register ************/ +#define FLASH_PCROP1AER_PCROP1A_END_Pos (0U) +#define FLASH_PCROP1AER_PCROP1A_END_Msk (0x1FFUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x000001FF */ +#define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk /*!< PCROP area A end offset */ +#define FLASH_PCROP1AER_PCROP_RDP_Pos (31U) +#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */ +#define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk /*!< PCROP area preserved when RDP level decreased */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk /*!< WRP area A start offset */ +#define FLASH_WRP1AR_WRP1A_END_Pos (16U) +#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk /*!< WRP area A end offset */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk /*!< WRP area B start offset */ +#define FLASH_WRP1BR_WRP1B_END_Pos (16U) +#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk /*!< WRP area B end offset */ + +/****************** Bits definition for FLASH_PCROP1BSR register ************/ +#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U) +#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x1FFUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x000001FF */ +#define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk /*!< PCROP area B start offset */ + +/****************** Bits definition for FLASH_PCROP1BER register ************/ +#define FLASH_PCROP1BER_PCROP1B_END_Pos (0U) +#define FLASH_PCROP1BER_PCROP1B_END_Msk (0x1FFUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x000001FF */ +#define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk /*!< PCROP area B end offset */ + +/****************** Bits definition for FLASH_IPCCBR register ************/ +#define FLASH_IPCCBR_IPCCDBA_Pos (0U) +#define FLASH_IPCCBR_IPCCDBA_Msk (0x3FFFUL << FLASH_IPCCBR_IPCCDBA_Pos) /*!< 0x00003FFF */ +#define FLASH_IPCCBR_IPCCDBA FLASH_IPCCBR_IPCCDBA_Msk /*!< IPCC data buffer base address */ + +/****************** Bits definition for FLASH_SFR register ************/ +#define FLASH_SFR_SFSA_Pos (0U) +#define FLASH_SFR_SFSA_Msk (0xFFUL << FLASH_SFR_SFSA_Pos) /*!< 0x000000FF */ +#define FLASH_SFR_SFSA FLASH_SFR_SFSA_Msk /* Secure flash start address */ +#define FLASH_SFR_FSD_Pos (8U) +#define FLASH_SFR_FSD_Msk (0x1UL << FLASH_SFR_FSD_Pos) /*!< 0x00000100 */ +#define FLASH_SFR_FSD FLASH_SFR_FSD_Msk /* Flash mode secure */ +#define FLASH_SFR_DDS_Pos (12U) +#define FLASH_SFR_DDS_Msk (0x1UL << FLASH_SFR_DDS_Pos) /*!< 0x00001000 */ +#define FLASH_SFR_DDS FLASH_SFR_DDS_Msk /* Enabling and disabling CPU2 Debug access */ + +/****************** Bits definition for FLASH_SRRVR register ************/ +#define FLASH_SRRVR_SBRV_Pos (0U) +#define FLASH_SRRVR_SBRV_Msk (0x3FFFFUL << FLASH_SRRVR_SBRV_Pos) /*!< 0x0003FFFF */ +#define FLASH_SRRVR_SBRV FLASH_SRRVR_SBRV_Msk /* SCPU2 boot reset vector memory offset */ + +#define FLASH_SRRVR_SBRSA_Pos (18U) +#define FLASH_SRRVR_SBRSA_Msk (0x1FUL << FLASH_SRRVR_SBRSA_Pos) /*!< 0x007C0000 */ +#define FLASH_SRRVR_SBRSA FLASH_SRRVR_SBRSA_Msk /* Secure backup SRAM2a start address */ +#define FLASH_SRRVR_BRSD_Pos (23U) +#define FLASH_SRRVR_BRSD_Msk (0x1UL << FLASH_SRRVR_BRSD_Pos) /*!< 0x00800000 */ +#define FLASH_SRRVR_BRSD FLASH_SRRVR_BRSD_Msk /* Backup SRAM2A secure mode */ + +#define FLASH_SRRVR_SNBRSA_Pos (25U) +#define FLASH_SRRVR_SNBRSA_Msk (0x1FUL << FLASH_SRRVR_SNBRSA_Pos) /*!< 0x3E000000 */ +#define FLASH_SRRVR_SNBRSA FLASH_SRRVR_SNBRSA_Msk /* Secure non-backup SRAM2b start address */ +#define FLASH_SRRVR_NBRSD_Pos (30U) +#define FLASH_SRRVR_NBRSD_Msk (0x1UL << FLASH_SRRVR_NBRSD_Pos) /*!< 0x40000000 */ +#define FLASH_SRRVR_NBRSD FLASH_SRRVR_NBRSD_Msk /* Non-backup SRAM2B secure mode */ +#define FLASH_SRRVR_C2OPT_Pos (31U) +#define FLASH_SRRVR_C2OPT_Msk (0x1UL << FLASH_SRRVR_C2OPT_Pos) /*!< 0x80000000 */ +#define FLASH_SRRVR_C2OPT FLASH_SRRVR_C2OPT_Msk /* SCPU2 boot reset vector memory selection */ + +/****************** Bits definition for FLASH_C2ACR register ************/ +#define FLASH_C2ACR_PRFTEN_Pos (8U) +#define FLASH_C2ACR_PRFTEN_Msk (0x1UL << FLASH_C2ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_C2ACR_PRFTEN FLASH_C2ACR_PRFTEN_Msk /*!< CPU2 Prefetch enable */ +#define FLASH_C2ACR_ICEN_Pos (9U) +#define FLASH_C2ACR_ICEN_Msk (0x1UL << FLASH_C2ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_C2ACR_ICEN FLASH_C2ACR_ICEN_Msk /*!< CPU2 Instruction cache enable */ +#define FLASH_C2ACR_ICRST_Pos (11U) +#define FLASH_C2ACR_ICRST_Msk (0x1UL << FLASH_C2ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_C2ACR_ICRST FLASH_C2ACR_ICRST_Msk /*!< CPU2 Instruction cache reset */ +#define FLASH_C2ACR_PES_Pos (15U) +#define FLASH_C2ACR_PES_Msk (0x1UL << FLASH_C2ACR_PES_Pos) /*!< 0x00008000 */ +#define FLASH_C2ACR_PES FLASH_C2ACR_PES_Msk /*!< CPU2 Program/erase suspend request */ + +/****************** Bits definition for FLASH_C2SR register ************/ +#define FLASH_C2SR_EOP_Pos (0U) +#define FLASH_C2SR_EOP_Msk (0x1UL << FLASH_C2SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_C2SR_EOP FLASH_C2SR_EOP_Msk /*!< CPU2 End of operation */ +#define FLASH_C2SR_OPERR_Pos (1U) +#define FLASH_C2SR_OPERR_Msk (0x1UL << FLASH_C2SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_C2SR_OPERR FLASH_C2SR_OPERR_Msk /*!< CPU2 Operation error */ +#define FLASH_C2SR_PROGERR_Pos (3U) +#define FLASH_C2SR_PROGERR_Msk (0x1UL << FLASH_C2SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_C2SR_PROGERR FLASH_C2SR_PROGERR_Msk /*!< CPU2 Programming error */ +#define FLASH_C2SR_WRPERR_Pos (4U) +#define FLASH_C2SR_WRPERR_Msk (0x1UL << FLASH_C2SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_C2SR_WRPERR FLASH_C2SR_WRPERR_Msk /*!< CPU2 Write protection error */ +#define FLASH_C2SR_PGAERR_Pos (5U) +#define FLASH_C2SR_PGAERR_Msk (0x1UL << FLASH_C2SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_C2SR_PGAERR FLASH_C2SR_PGAERR_Msk /*!< CPU2 Programming alignment error */ +#define FLASH_C2SR_SIZERR_Pos (6U) +#define FLASH_C2SR_SIZERR_Msk (0x1UL << FLASH_C2SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_C2SR_SIZERR FLASH_C2SR_SIZERR_Msk /*!< CPU2 Size error */ +#define FLASH_C2SR_PGSERR_Pos (7U) +#define FLASH_C2SR_PGSERR_Msk (0x1UL << FLASH_C2SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_C2SR_PGSERR FLASH_C2SR_PGSERR_Msk /*!< CPU2 Programming sequence error */ +#define FLASH_C2SR_MISERR_Pos (8U) +#define FLASH_C2SR_MISERR_Msk (0x1UL << FLASH_C2SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_C2SR_MISERR FLASH_C2SR_MISERR_Msk /*!< CPU2 Fast programming data miss error */ +#define FLASH_C2SR_FASTERR_Pos (9U) +#define FLASH_C2SR_FASTERR_Msk (0x1UL << FLASH_C2SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_C2SR_FASTERR FLASH_C2SR_FASTERR_Msk /*!< CPU2 Fast programming error */ +#define FLASH_C2SR_RDERR_Pos (14U) +#define FLASH_C2SR_RDERR_Msk (0x1UL << FLASH_C2SR_RDERR_Pos) /*!< 0x00004000 */ +#define FLASH_C2SR_RDERR FLASH_C2SR_RDERR_Msk /*!< CPU2 PCROP read error */ +#define FLASH_C2SR_BSY_Pos (16U) +#define FLASH_C2SR_BSY_Msk (0x1UL << FLASH_C2SR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_C2SR_BSY FLASH_C2SR_BSY_Msk /*!< CPU2 Flash busy */ +#define FLASH_C2SR_CFGBSY_Pos (18U) +#define FLASH_C2SR_CFGBSY_Msk (0x1UL << FLASH_C2SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_C2SR_CFGBSY FLASH_C2SR_CFGBSY_Msk /*!< CPU2 Programming or erase configuration busy */ +#define FLASH_C2SR_PESD_Pos (19U) +#define FLASH_C2SR_PESD_Msk (0x1UL << FLASH_C2SR_PESD_Pos) /*!< 0x00080000 */ +#define FLASH_C2SR_PESD FLASH_C2SR_PESD_Msk /*!< CPU2 Programming/erase operation suspended */ + +/****************** Bits definition for FLASH_C2CR register ************/ +#define FLASH_C2CR_PG_Pos (0U) +#define FLASH_C2CR_PG_Msk (0x1UL << FLASH_C2CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_C2CR_PG FLASH_C2CR_PG_Msk /*!< CPU2 Flash programming */ +#define FLASH_C2CR_PER_Pos (1U) +#define FLASH_C2CR_PER_Msk (0x1UL << FLASH_C2CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_C2CR_PER FLASH_C2CR_PER_Msk /*!< CPU2 Page erase */ +#define FLASH_C2CR_MER_Pos (2U) +#define FLASH_C2CR_MER_Msk (0x1UL << FLASH_C2CR_MER_Pos) /*!< 0x00000004 */ +#define FLASH_C2CR_MER FLASH_C2CR_MER_Msk /*!< CPU2 Mass erase */ +#define FLASH_C2CR_PNB_Pos (3U) +#define FLASH_C2CR_PNB_Msk (0xFFUL << FLASH_C2CR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_C2CR_PNB FLASH_C2CR_PNB_Msk /*!< CPU2 Page number selection mask */ +#define FLASH_C2CR_STRT_Pos (16U) +#define FLASH_C2CR_STRT_Msk (0x1UL << FLASH_C2CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_C2CR_STRT FLASH_C2CR_STRT_Msk /*!< CPU2 Start an erase operation */ +#define FLASH_C2CR_FSTPG_Pos (18U) +#define FLASH_C2CR_FSTPG_Msk (0x1UL << FLASH_C2CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_C2CR_FSTPG FLASH_C2CR_FSTPG_Msk /*!< CPU2 Fast programming */ +#define FLASH_C2CR_EOPIE_Pos (24U) +#define FLASH_C2CR_EOPIE_Msk (0x1UL << FLASH_C2CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_C2CR_EOPIE FLASH_C2CR_EOPIE_Msk /*!< CPU2 End of operation interrupt enable */ +#define FLASH_C2CR_ERRIE_Pos (25U) +#define FLASH_C2CR_ERRIE_Msk (0x1UL << FLASH_C2CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_C2CR_ERRIE FLASH_C2CR_ERRIE_Msk /*!< CPU2 Error interrupt enable */ +#define FLASH_C2CR_RDERRIE_Pos (26U) +#define FLASH_C2CR_RDERRIE_Msk (0x1UL << FLASH_C2CR_RDERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_C2CR_RDERRIE FLASH_C2CR_RDERRIE_Msk /*!< CPU2 PCROP read error interrupt enable */ + +/******************************************************************************/ +/* */ +/* General Purpose I/O */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + +/******************************************************************************/ +/* */ +/* HSEM HW Semaphore */ +/* */ +/******************************************************************************/ +/******************** Bit definition for HSEM_R register ********************/ +#define HSEM_R_PROCID_Pos (0U) +#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */ +#define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32wb35xx + * @{ + */ + +#ifndef __STM32WB35xx_H +#define __STM32WB35xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 1U /*!< Core Revision r0p1 */ +#define __MPU_PRESENT 1U /*!< M4 provides an MPU */ +#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 4U /*!< STM32WBxx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32wb35xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +/*!< Interrupt Number Definition for M4 */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< Cortex-M4 System Tick Interrupt */ + +/************* STM32WBxx specific Interrupt Numbers on M4 core ************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD and PVM detector */ + TAMP_STAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Interrupt */ + FLASH_IRQn = 4, /*!< FLASH (CFI) global Interrupt */ + RCC_IRQn = 5, /*!< RCC Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line 0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line 1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line 2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line 3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line 4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 Interrupt */ + USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ + USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt (including USB wakeup) */ + C2SEV_PWR_C2H_IRQn = 21, /*!< CPU2 SEV Interrupt */ + COMP_IRQn = 22, /*!< COMP1 and COMP2 Interrupts */ + EXTI9_5_IRQn = 23, /*!< EXTI Lines [9:5] Interrupt */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 global Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Communication and TIM17 global Interrupts */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 Global Interrupt */ + PKA_IRQn = 29, /*!< PKA Interrupt */ + I2C1_EV_IRQn = 30, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 31, /*!< I2C1 Error Interrupt */ + I2C3_EV_IRQn = 32, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 33, /*!< I2C3 Error Interrupt */ + SPI1_IRQn = 34, /*!< SPI1 Interrupt */ + SPI2_IRQn = 35, /*!< SPI2 Interrupt */ + USART1_IRQn = 36, /*!< USART1 Interrupt */ + LPUART1_IRQn = 37, /*!< LPUART1 Interrupt */ + TSC_IRQn = 39, /*!< TSC Interrupt */ + EXTI15_10_IRQn = 40, /*!< EXTI Lines1[15:10 ]Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarms (A and B) Interrupt */ + CRS_IRQn = 42, /*!< CRS interrupt */ + PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQn = 43, /*!< PWR switching on the fly interrupt + PWR end of BLE activity interrupt + PWR end of 802.15.4 (Zigbee) activity interrupt + PWR end of critical radio phase interrupt */ + IPCC_C1_RX_IRQn = 44, /*!< IPCC RX Occupied Interrupt */ + IPCC_C1_TX_IRQn = 45, /*!< IPCC TX Free Interrupt */ + HSEM_IRQn = 46, /*!< HSEM Interrupt */ + LPTIM1_IRQn = 47, /*!< LPTIM1 Interrupt */ + LPTIM2_IRQn = 48, /*!< LPTIM2 Interrupt */ + QUADSPI_IRQn = 50, /*!< QUADSPI Interrupt */ + AES1_IRQn = 51, /*!< AES1 Interrupt */ + AES2_IRQn = 52, /*!< AES2 Interrupt */ + RNG_IRQn = 53, /*!< RNG Interrupt */ + FPU_IRQn = 54, /*!< FPU Interrupt */ + DMA2_Channel1_IRQn = 55, /*!< DMA2 Channel 1 Interrupt */ + DMA2_Channel2_IRQn = 56, /*!< DMA2 Channel 2 Interrupt */ + DMA2_Channel3_IRQn = 57, /*!< DMA2 Channel 3 Interrupt */ + DMA2_Channel4_IRQn = 58, /*!< DMA2 Channel 4 Interrupt */ + DMA2_Channel5_IRQn = 59, /*!< DMA2 Channel 5 Interrupt */ + DMA2_Channel6_IRQn = 60, /*!< DMA2 Channel 6 Interrupt */ + DMA2_Channel7_IRQn = 61, /*!< DMA2 Channel 7 Interrupt */ + DMAMUX1_OVR_IRQn = 62 /*!< DMAMUX1 overrun Interrupt */ +} IRQn_Type; +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32wbxx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */ +} ADC_Common_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x08-0x38 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x3C */ + __IO uint32_t C2APB1FZR1; /*!< Debug MCU CPU2 APB1 freeze register, Address offset: 0x40 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x44 */ + __IO uint32_t C2APB1FZR2; /*!< Debug MCU CPU2 APB1 freeze register, Address offset: 0x48 */ + __IO uint32_t APB2FZR; /*!< Debug MCU CPU1 APB2 freeze register, Address offset: 0x4C */ + __IO uint32_t C2APB2FZR; /*!< Debug MCU CPU2 APB2 freeze register, Address offset: 0x50 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register 0x00 */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register 0x04 */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register 0x08 */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register 0x0C */ + uint32_t RESERVED; /*!< Reserved, 0x10 */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access control register, Address offset: 0x00 */ + __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank 1 PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank 1 PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank 1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank 1 WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank 1 PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank 1 PCROP area B End address register, Address offset: 0x38 */ + __IO uint32_t IPCCBR; /*!< FLASH IPCC data buffer address, Address offset: 0x3C */ + uint32_t RESERVED2[7]; /*!< Reserved, Address offset: 0x40-0x58 */ + __IO uint32_t C2ACR; /*!< FLASH Core MO+ Access Control Register , Address offset: 0x5C */ + __IO uint32_t C2SR; /*!< FLASH Core MO+ Status Register, Address offset: 0x60 */ + __IO uint32_t C2CR; /*!< FLASH Core MO+ Control register, Address offset: 0x64 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x68-0x7C */ + __IO uint32_t SFR; /*!< FLASH secure start address, Address offset: 0x80 */ + __IO uint32_t SRRVR; /*!< FlASH secure SRAM2 start addr and CPU2 reset vector Address offset: 0x84 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Reset Register, Address offset: 0x18 */ + __IO uint32_t CR5; /*!< PWR Power Control Register 5, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< PWR Pull-Up Control Register of port E, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< PWR Pull-Down Control Register of port E, Address offset: 0x44 */ + uint32_t RESERVED0[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t PUCRH; /*!< PWR Pull-Up Control Register of port H, Address offset: 0x58 */ + __IO uint32_t PDCRH; /*!< PWR Pull-Down Control Register of port H, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, Address offset: 0x60-0x7C */ + __IO uint32_t C2CR1; /*!< PWR Power Control Register 1 for CPU2, Address offset: 0x80 */ + __IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset: 0x84 */ + __IO uint32_t EXTSCR; /*!< PWR Power Status Reset Register for CPU2, Address offset: 0x88 */ +} PWR_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ +uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x10-0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t SMPSCR; /*!< RCC SMPS step-down converter control register, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 & AHB4 peripheral reset register, Address offset: 0x30 */ +uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable register, Address offset: 0x50 */ +uint32_t RESERVED2; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ +uint32_t RESERVED3; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ +uint32_t RESERVED4; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ +uint32_t RESERVED5; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Clock Configuration Independent Register, Address offset: 0x88 */ +uint32_t RESERVED6; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC Control and Status Register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x98 */ + __IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */ +uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */ + __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */ +uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ + __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */ + __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */ + __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */ +uint32_t RESERVED9; /*!< Reserved, Address offset: 0x154 */ + __IO uint32_t C2APB1ENR1; /*!< RCC APB1 peripheral CPU2 clocks enable register 1, Address offset: 0x158 */ + __IO uint32_t C2APB1ENR2; /*!< RCC APB1 peripheral CPU2 clocks enable register 2, Address offset: 0x15C */ + __IO uint32_t C2APB2ENR; /*!< RCC APB2 peripheral CPU2 clocks enable register 1, Address offset: 0x160 */ + __IO uint32_t C2APB3ENR; /*!< RCC APB3 peripheral CPU2 clocks enable register 1, Address offset: 0x164 */ + __IO uint32_t C2AHB1SMENR; /*!< RCC AHB1 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x168 */ + __IO uint32_t C2AHB2SMENR; /*!< RCC AHB2 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x16C */ + __IO uint32_t C2AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x170 */ +uint32_t RESERVED10; /*!< Reserved, */ + __IO uint32_t C2APB1SMENR1; /*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 1, Address offset: 0x178 */ + __IO uint32_t C2APB1SMENR2; /*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 2, Address offset: 0x17C */ + __IO uint32_t C2APB2SMENR; /*!< RCC APB2 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x180 */ + __IO uint32_t C2APB3SMENR; /*!< RCC APB3 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x184 */ +} RCC_TypeDef; + + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + + + + +/** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR1; /*!< SYSCFG SRAM2 write protection register part 1, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ + __IO uint32_t SWPR2; /*!< SYSCFG write protection register part 2, Address offset: 0x28 */ + uint32_t RESERVED1[53]; /*!< Reserved, Address offset: 0x2C-0xFC */ + __IO uint32_t IMR1; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 1, Address offset: 0x100 */ + __IO uint32_t IMR2; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 2, Address offset: 0x104 */ + __IO uint32_t C2IMR1; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 1, Address offset: 0x108 */ + __IO uint32_t C2IMR2; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 2, Address offset: 0x10C */ + __IO uint32_t SIPCR; /*!< SYSCFG secure IP control register, Address offset: 0x110 */ + +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ +} AES_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */ +} TSC_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Inter-Processor Communication + */ +typedef struct +{ + __IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, Address offset: 0x000 */ + __IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, Address offset: 0x004 */ + __IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, Address offset: 0x008 */ + __IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status register, Address offset: 0x00C */ + __IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, Address offset: 0x010 */ + __IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, Address offset: 0x014 */ + __IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, Address offset: 0x018 */ + __IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status register, Address offset: 0x01C */ +} IPCC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x000 */ + __IO uint32_t MR; /*!< Mask register, Address offset: 0x004 */ + __IO uint32_t SCR; /*!< Status set clear register, Address offset: 0x008 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x00C */ +} IPCC_CommonTypeDef; + +/** + * @brief Async Interrupts and Events Controller + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI software interrupt event register [31:0], Address offset: 0x08 */ + __IO uint32_t PR1; /*!< EXTI pending register [31:0], Address offset: 0x0C */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x10 - 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI software interrupt event register [31:0], Address offset: 0x28 */ + __IO uint32_t PR2; /*!< EXTI pending register [31:0], Address offset: 0x2C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, Address offset: 0x30 - 0x3C */ + __IO uint32_t RESERVED3[8]; /*!< Reserved, Address offset: 0x40 - 0x5C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, Address offset: 0x60 - 0x7C */ + __IO uint32_t IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED8[10]; /*!< Reserved, Address offset: 0x98 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ +}EXTI_TypeDef; + +/** + * @brief Public Key Accelerator (PKA) + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved1[253]; /*!< Reserved Address offset: 0x000C-0x03FC*/ + __IO uint32_t RAM[894]; /*!< PKA RAM, Address offset: 0x0400-0x11F4 */ +} PKA_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ +typedef struct +{ + __IO uint32_t R[32]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RLR[32]; /*!< HSEM 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IER; /*!< HSEM CPU1 interrupt enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM CPU1 interrupt clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM CPU1 interrupt status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM CPU1 masked interrupt status register , Address offset: 10Ch */ + __IO uint32_t C2IER; /*!< HSEM CPU2 interrupt enable register , Address offset: 110h */ + __IO uint32_t C2ICR; /*!< HSEM CPU2 interrupt clear register , Address offset: 114h */ + __IO uint32_t C2ISR; /*!< HSEM CPU2 interrupt status register , Address offset: 118h */ + __IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 11Ch */ + uint32_t Reserved[8]; /*!< Reserved Address offset: 120h-13Ch*/ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +/*!< Boundary memory map */ +#define FLASH_BASE (0x08000000UL)/*!< FLASH(up to 1 MB) base address */ +#define SRAM_BASE (0x20000000UL)/*!< SRAM(up to 256 KB) base address */ +#define PERIPH_BASE (0x40000000UL)/*!< Peripheral base address */ + +/*!< Memory, OTP and Option bytes */ + +/* Base addresses */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 0x1FFF8FFF) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ + +#define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 32 KB) base address */ +#define SRAM2A_BASE (SRAM_BASE + 0x00008000UL)/*!< SRAM2A(32 KB) base address */ +#define SRAM2B_BASE (SRAM_BASE + 0x00010000UL)/*!< SRAM2B(32 KB) base address */ + +/* Memory Size */ +#define FLASH_SIZE (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x07FFUL)) << 10U) +#define SRAM1_SIZE 0x00008000UL /*!< SRAM1 default size : 32 kB */ +#define SRAM2A_SIZE 0x00008000UL /*!< SRAM2a default size : 32 kB */ +#define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */ + +/* End addresses */ +#define SRAM1_END_ADDR (0x20007FFFUL) /*!< SRAM1 : 32KB (0x20000000 0x20007FFF) */ +#define SRAM2A_END_ADDR (0x2000FFFFUL) /*!< SRAM2a (backup) : 32KB (0x20008000 0x2000FFFF) */ +#define SRAM2B_END_ADDR (0x20017FFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20010000 0x20017FFF) */ + +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) +#define AHB4PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define APB3PERIPH_BASE (PERIPH_BASE + 0x20000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x50000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x00005C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x00006000UL) +#define USB1_BASE (APB1PERIPH_BASE + 0x00006800UL) +#define USB1_PMAADDR (APB1PERIPH_BASE + 0x00006C00UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x00007C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x00008000UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x00009400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x00000200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x00000204UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x00000800UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL) +#define TSC_BASE (AHB1PERIPH_BASE + 0x00004000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x0000006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x00000080UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x00000020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x00000024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x00000028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0000002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x00000030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x00000034UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) + +/*!< AHB2 peripherals */ +#define IOPORT_BASE (AHB2PERIPH_BASE + 0x00000000UL) +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOE_BASE (IOPORT_BASE + 0x00001000UL) +#define GPIOH_BASE (IOPORT_BASE + 0x00001C00UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) + +#define AES1_BASE (AHB2PERIPH_BASE + 0x08060000UL) + +/*!< AHB Shared peripherals */ +#define RCC_BASE (AHB4PERIPH_BASE + 0x00000000UL) +#define PWR_BASE (AHB4PERIPH_BASE + 0x00000400UL) +#define EXTI_BASE (AHB4PERIPH_BASE + 0x00000800UL) +#define IPCC_BASE (AHB4PERIPH_BASE + 0x00000C00UL) +#define RNG_BASE (AHB4PERIPH_BASE + 0x00001000UL) +#define HSEM_BASE (AHB4PERIPH_BASE + 0x00001400UL) +#define AES2_BASE (AHB4PERIPH_BASE + 0x00001800UL) +#define PKA_BASE (AHB4PERIPH_BASE + 0x00002000UL) +#define FLASH_REG_BASE (AHB4PERIPH_BASE + 0x00004000UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + + +/*!< AHB3 peripherals */ +#define QUADSPI_BASE (AHB3PERIPH_BASE + 0x00000000UL) /*!< QUADSPI memories accessible over AHB base address */ +#define QUADSPI_R_BASE (AHB3PERIPH_BASE + 0x10001000UL) /*!< QUADSPI control registers base address */ + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE ((uint32_t)0x1FFF7500UL) /*!< Package data register base address */ +#define UID64_BASE ((uint32_t)0x1FFF7580UL) /*!< 64-bit Unique device Identification */ +#define UID_BASE ((uint32_t)0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0UL) /*!< Flash size data register base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +/* Peripherals available on APB1 bus */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define USB ((USB_TypeDef *) USB1_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) + +/* Peripherals available on APB2 bus */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) + +/* Peripherals available on AHB1 bus */ +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define TSC ((TSC_TypeDef *) TSC_BASE) + +/* Peripherals available on AHB2 bus */ +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) + +#define AES1 ((AES_TypeDef *) AES1_BASE) + +/* Peripherals available on AHB shared bus */ +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define IPCC ((IPCC_TypeDef *) IPCC_BASE) +#define IPCC_C1 ((IPCC_CommonTypeDef *) IPCC_BASE) +#define IPCC_C2 ((IPCC_CommonTypeDef *) (IPCC_BASE + 0x10U)) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100U)) +#define AES2 ((AES_TypeDef *) AES2_BASE) +#define PKA ((PKA_TypeDef *) PKA_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_REG_BASE) + +/* Peripherals available on AHB3 bus */ +#define QUADSPI ((QUADSPI_TypeDef *) QUADSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_ALIGN_Pos (5U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR_EXTSEL_Pos (6U) +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ + +#define ADC_JSQR_JEXTEN_Pos (6U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ + +#define ADC_JSQR_JSQ1_Pos (8U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ + +#define ADC_JSQR_JSQ2_Pos (14U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (20U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ + +#define ADC_JSQR_JSQ4_Pos (26U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ +#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ +#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ +#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ +#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003A0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00000100 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00000200 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00000400 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/* Legacy defines */ +#define ADC_CCR_MULTI (ADC_CCR_DUAL) +#define ADC_CCR_MULTI_0 (ADC_CCR_DUAL_0) +#define ADC_CCR_MULTI_1 (ADC_CCR_DUAL_1) +#define ADC_CCR_MULTI_2 (ADC_CCR_DUAL_2) +#define ADC_CCR_MULTI_3 (ADC_CCR_DUAL_3) +#define ADC_CCR_MULTI_4 (ADC_CCR_DUAL_4) + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ***************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ +#define COMP_CSR_PWRMODE_Pos (2U) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */ +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0x7UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INPSEL_Pos (7U) +#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000180 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */ +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_WINMODE_Pos (9U) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_BLANKING_Pos (18U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */ +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */ +#define COMP_CSR_INMESEL_Pos (25U) +#define COMP_CSR_INMESEL_Msk (0x3UL << COMP_CSR_INMESEL_Pos) /*!< 0x06000000 */ +#define COMP_CSR_INMESEL COMP_CSR_INMESEL_Msk /*!< Comparator input minus extended selection */ +#define COMP_CSR_INMESEL_0 (0x1UL << COMP_CSR_INMESEL_Pos) /*!< 0x02000000 */ +#define COMP_CSR_INMESEL_1 (0x2UL << COMP_CSR_INMESEL_Pos) /*!< 0x04000000 */ +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1U << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2U << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ + +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1U << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2U << AES_CR_MODE_Pos) /*!< 0x00000010 */ + +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001U << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002U << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800U << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ + +#define AES_CR_CCFC_Pos (7U) +#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */ +#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ +#define AES_CR_ERRC_Pos (8U) +#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */ +#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ +#define AES_CR_CCFIE_Pos (9U) +#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */ +#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */ +#define AES_CR_ERRIE_Pos (10U) +#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ +#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ + +#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1U << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2U << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ + +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ + +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in last payload block */ +#define AES_CR_NPBLB_0 (0x1U << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2U << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4U << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8U << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0U) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0U) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0U) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0U) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0U) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* DMAMUX Controller */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DMAMUX_CxCR register **************/ +#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) +#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */ +#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ +#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ +#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ +#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ +#define DMAMUX_CxCR_SOIE_Pos (8U) +#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ +#define DMAMUX_CxCR_EGE_Pos (9U) +#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ +#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ +#define DMAMUX_CxCR_SE_Pos (16U) +#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ +#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ +#define DMAMUX_CxCR_SPOL_Pos (17U) +#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ +#define DMAMUX_CxCR_SPOL_0 (0x1U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_CxCR_SPOL_1 (0x2U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_CxCR_NBREQ_Pos (19U) +#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ +#define DMAMUX_CxCR_NBREQ_0 (0x01U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_CxCR_NBREQ_1 (0x02U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_CxCR_NBREQ_2 (0x04U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_CxCR_NBREQ_3 (0x08U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_CxCR_NBREQ_4 (0x10U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ +#define DMAMUX_CxCR_SYNC_ID_Pos (24U) +#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ +#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ +#define DMAMUX_CxCR_SYNC_ID_0 (0x01U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ +#define DMAMUX_CxCR_SYNC_ID_1 (0x02U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ +#define DMAMUX_CxCR_SYNC_ID_2 (0x04U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ +#define DMAMUX_CxCR_SYNC_ID_3 (0x08U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ +#define DMAMUX_CxCR_SYNC_ID_4 (0x10U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ + +/******************* Bits definition for DMAMUX_CSR register **************/ +#define DMAMUX_CSR_SOF0_Pos (0U) +#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ +#define DMAMUX_CSR_SOF1_Pos (1U) +#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ +#define DMAMUX_CSR_SOF2_Pos (2U) +#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ +#define DMAMUX_CSR_SOF3_Pos (3U) +#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */ +#define DMAMUX_CSR_SOF4_Pos (4U) +#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */ +#define DMAMUX_CSR_SOF5_Pos (5U) +#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */ +#define DMAMUX_CSR_SOF6_Pos (6U) +#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */ +#define DMAMUX_CSR_SOF7_Pos (7U) +#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */ +#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Synchronization Overrun Flag 7 */ +#define DMAMUX_CSR_SOF8_Pos (8U) +#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */ +#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Synchronization Overrun Flag 8 */ +#define DMAMUX_CSR_SOF9_Pos (9U) +#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */ +#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Synchronization Overrun Flag 9 */ +#define DMAMUX_CSR_SOF10_Pos (10U) +#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */ +#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Synchronization Overrun Flag 10 */ +#define DMAMUX_CSR_SOF11_Pos (11U) +#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */ +#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Synchronization Overrun Flag 11 */ +#define DMAMUX_CSR_SOF12_Pos (12U) +#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */ +#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Synchronization Overrun Flag 12 */ +#define DMAMUX_CSR_SOF13_Pos (13U) +#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */ +#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Synchronization Overrun Flag 13 */ + +/******************** Bits definition for DMAMUX_CFR register **************/ +#define DMAMUX_CFR_CSOF0_Pos (0U) +#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ +#define DMAMUX_CFR_CSOF1_Pos (1U) +#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ +#define DMAMUX_CFR_CSOF2_Pos (2U) +#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ +#define DMAMUX_CFR_CSOF3_Pos (3U) +#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */ +#define DMAMUX_CFR_CSOF4_Pos (4U) +#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */ +#define DMAMUX_CFR_CSOF5_Pos (5U) +#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */ +#define DMAMUX_CFR_CSOF6_Pos (6U) +#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */ +#define DMAMUX_CFR_CSOF7_Pos (7U) +#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */ +#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Clear Overrun Flag 7 */ +#define DMAMUX_CFR_CSOF8_Pos (8U) +#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */ +#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Clear Overrun Flag 8 */ +#define DMAMUX_CFR_CSOF9_Pos (9U) +#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */ +#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Clear Overrun Flag 9 */ +#define DMAMUX_CFR_CSOF10_Pos (10U) +#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */ +#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Clear Overrun Flag 10 */ +#define DMAMUX_CFR_CSOF11_Pos (11U) +#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */ +#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Clear Overrun Flag 11 */ +#define DMAMUX_CFR_CSOF12_Pos (12U) +#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */ +#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Clear Overrun Flag 12 */ +#define DMAMUX_CFR_CSOF13_Pos (13U) +#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */ +#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Clear Overrun Flag 13 */ + +/******************** Bits definition for DMAMUX_RGxCR register ************/ +#define DMAMUX_RGxCR_SIG_ID_Pos (0U) +#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ +#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ +#define DMAMUX_RGxCR_SIG_ID_0 (0x01U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGxCR_SIG_ID_1 (0x02U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGxCR_SIG_ID_2 (0x04U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGxCR_SIG_ID_3 (0x08U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGxCR_SIG_ID_4 (0x10U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_RGxCR_OIE_Pos (8U) +#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ +#define DMAMUX_RGxCR_GE_Pos (16U) +#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ +#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ +#define DMAMUX_RGxCR_GPOL_Pos (17U) +#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ +#define DMAMUX_RGxCR_GPOL_0 (0x1U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_RGxCR_GPOL_1 (0x2U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_RGxCR_GNBREQ_Pos (19U) +#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ +#define DMAMUX_RGxCR_GNBREQ_0 (0x01U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_RGxCR_GNBREQ_1 (0x02U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_RGxCR_GNBREQ_2 (0x04U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_RGxCR_GNBREQ_3 (0x08U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_RGxCR_GNBREQ_4 (0x10U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for DMAMUX_RGSR register **************/ +#define DMAMUX_RGSR_OF0_Pos (0U) +#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ +#define DMAMUX_RGSR_OF1_Pos (1U) +#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ +#define DMAMUX_RGSR_OF2_Pos (2U) +#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ +#define DMAMUX_RGSR_OF3_Pos (3U) +#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ + +/******************** Bits definition for DMAMUX_RGCFR register **************/ +#define DMAMUX_RGCFR_COF0_Pos (0U) +#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ +#define DMAMUX_RGCFR_COF1_Pos (1U) +#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ +#define DMAMUX_RGCFR_COF2_Pos (2U) +#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ +#define DMAMUX_RGCFR_COF3_Pos (3U) +#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT_Pos (0U) +#define EXTI_RTSR1_RT_Msk (0x803FFFFFUL << EXTI_RTSR1_RT_Pos) /*!< 0x803FFFFF */ +#define EXTI_RTSR1_RT EXTI_RTSR1_RT_Msk /*!< Rising trigger event configuration bit */ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR1_RT17_Pos (17U) +#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR1_RT18_Pos (18U) +#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR1_RT19_Pos (19U) +#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */ +#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_RTSR1_RT20_Pos (20U) +#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */ +#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ +#define EXTI_RTSR1_RT21_Pos (21U) +#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */ +#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ +#define EXTI_RTSR1_RT31_Pos (31U) +#define EXTI_RTSR1_RT31_Msk (0x1UL << EXTI_RTSR1_RT31_Pos) /*!< 0x80000000 */ +#define EXTI_RTSR1_RT31 EXTI_RTSR1_RT31_Msk /*!< Rising trigger event configuration bit of line 31 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT_Pos (0U) +#define EXTI_FTSR1_FT_Msk (0x803FFFFFUL << EXTI_FTSR1_FT_Pos) /*!< 0x803FFFFF */ +#define EXTI_FTSR1_FT EXTI_FTSR1_FT_Msk /*!< Falling trigger event configuration bit */ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR1_FT17_Pos (17U) +#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR1_FT18_Pos (18U) +#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR1_FT19_Pos (19U) +#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */ +#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_FTSR1_FT20_Pos (20U) +#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */ +#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ +#define EXTI_FTSR1_FT21_Pos (21U) +#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */ +#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ +#define EXTI_FTSR1_FT31_Pos (31U) +#define EXTI_FTSR1_FT31_Msk (0x1UL << EXTI_FTSR1_FT31_Pos) /*!< 0x80000000 */ +#define EXTI_FTSR1_FT31 EXTI_FTSR1_FT31_Msk /*!< Falling trigger event configuration bit of line 31 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI_Pos (0U) +#define EXTI_SWIER1_SWI_Msk (0x803FFFFFUL << EXTI_SWIER1_SWI_Pos) /*!< 0x803FFFFF */ +#define EXTI_SWIER1_SWI EXTI_SWIER1_SWI_Msk /*!< Software interrupt */ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER1_SWI17_Pos (17U) +#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER1_SWI18_Pos (18U) +#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER1_SWI19_Pos (19U) +#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */ +#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */ +#define EXTI_SWIER1_SWI20_Pos (20U) +#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */ +#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */ +#define EXTI_SWIER1_SWI21_Pos (21U) +#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */ +#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */ +#define EXTI_SWIER1_SWI31_Pos (31U) +#define EXTI_SWIER1_SWI31_Msk (0x1UL << EXTI_SWIER1_SWI31_Pos) /*!< 0x80000000 */ +#define EXTI_SWIER1_SWI31 EXTI_SWIER1_SWI31_Msk /*!< Software Interrupt on line 31 */ + +/******************* Bit definition for EXTI_PR1 register *******************/ +#define EXTI_PR1_PIF_Pos (0U) +#define EXTI_PR1_PIF_Msk (0x803FFFFFUL << EXTI_PR1_PIF_Pos) /*!< 0x803FFFFF */ +#define EXTI_PR1_PIF EXTI_PR1_PIF_Msk /*!< Pending bit */ +#define EXTI_PR1_PIF0_Pos (0U) +#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */ +#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */ +#define EXTI_PR1_PIF1_Pos (1U) +#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */ +#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */ +#define EXTI_PR1_PIF2_Pos (2U) +#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */ +#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */ +#define EXTI_PR1_PIF3_Pos (3U) +#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */ +#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */ +#define EXTI_PR1_PIF4_Pos (4U) +#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */ +#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */ +#define EXTI_PR1_PIF5_Pos (5U) +#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */ +#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */ +#define EXTI_PR1_PIF6_Pos (6U) +#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */ +#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */ +#define EXTI_PR1_PIF7_Pos (7U) +#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */ +#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */ +#define EXTI_PR1_PIF8_Pos (8U) +#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */ +#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */ +#define EXTI_PR1_PIF9_Pos (9U) +#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */ +#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */ +#define EXTI_PR1_PIF10_Pos (10U) +#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */ +#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */ +#define EXTI_PR1_PIF11_Pos (11U) +#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */ +#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */ +#define EXTI_PR1_PIF12_Pos (12U) +#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */ +#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */ +#define EXTI_PR1_PIF13_Pos (13U) +#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */ +#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */ +#define EXTI_PR1_PIF14_Pos (14U) +#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */ +#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */ +#define EXTI_PR1_PIF15_Pos (15U) +#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */ +#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */ +#define EXTI_PR1_PIF16_Pos (16U) +#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */ +#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */ +#define EXTI_PR1_PIF17_Pos (17U) +#define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos) /*!< 0x00020000 */ +#define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk /*!< Pending bit for line 17 */ +#define EXTI_PR1_PIF18_Pos (18U) +#define EXTI_PR1_PIF18_Msk (0x1UL << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */ +#define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */ +#define EXTI_PR1_PIF19_Pos (19U) +#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */ +#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */ +#define EXTI_PR1_PIF20_Pos (20U) +#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */ +#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */ +#define EXTI_PR1_PIF21_Pos (21U) +#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */ +#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */ +#define EXTI_PR1_PIF31_Pos (31U) +#define EXTI_PR1_PIF31_Msk (0x1UL << EXTI_PR1_PIF31_Pos) /*!< 0x80000000 */ +#define EXTI_PR1_PIF31 EXTI_PR1_PIF31_Msk /*!< Pending bit for line 31 */ + +/****************** Bit definition for EXTI_RTSR2 register ******************/ +#define EXTI_RTSR2_RT_Pos (0U) +#define EXTI_RTSR2_RT_Msk (0x302UL << EXTI_RTSR2_RT_Pos) /*!< 0x00000302 */ +#define EXTI_RTSR2_RT EXTI_RTSR2_RT_Msk /*!< Rising trigger event configuration bit */ +#define EXTI_RTSR2_RT33_Pos (1U) +#define EXTI_RTSR2_RT33_Msk (0x1UL << EXTI_RTSR2_RT33_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR2_RT33 EXTI_RTSR2_RT33_Msk /*!< Rising trigger event configuration bit of line 33 */ +#define EXTI_RTSR2_RT40_Pos (8U) +#define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger event configuration bit of line 40 */ +#define EXTI_RTSR2_RT41_Pos (9U) +#define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger event configuration bit of line 41 */ + +/****************** Bit definition for EXTI_FTSR2 register ******************/ +#define EXTI_FTSR2_FT_Pos (0U) +#define EXTI_FTSR2_FT_Msk (0x302UL << EXTI_FTSR2_FT_Pos) /*!< 0x00000302 */ +#define EXTI_FTSR2_FT EXTI_FTSR2_FT_Msk /*!< Falling trigger event configuration bit */ +#define EXTI_FTSR2_FT33_Pos (1U) +#define EXTI_FTSR2_FT33_Msk (0x1UL << EXTI_FTSR2_FT33_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR2_FT33 EXTI_FTSR2_FT33_Msk /*!< Falling trigger event configuration bit of line 33 */ +#define EXTI_FTSR2_FT40_Pos (8U) +#define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger event configuration bit of line 40 */ +#define EXTI_FTSR2_FT41_Pos (9U) +#define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger event configuration bit of line 41 */ + +/****************** Bit definition for EXTI_SWIER2 register *****************/ +#define EXTI_SWIER2_SWI_Pos (0U) +#define EXTI_SWIER2_SWI_Msk (0x302UL << EXTI_SWIER2_SWI_Pos) /*!< 0x00000302 */ +#define EXTI_SWIER2_SWI EXTI_SWIER2_SWI_Msk /*!< Falling trigger event configuration bit */ +#define EXTI_SWIER2_SWI33_Pos (1U) +#define EXTI_SWIER2_SWI33_Msk (0x1UL << EXTI_SWIER2_SWI33_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWI33_Msk /*!< Software Interrupt on line 33 */ +#define EXTI_SWIER2_SWI40_Pos (8U) +#define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */ +#define EXTI_SWIER2_SWI41_Pos (9U) +#define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */ + +/******************* Bit definition for EXTI_PR2 register *******************/ +#define EXTI_PR2_PIF_Pos (0U) +#define EXTI_PR2_PIF_Msk (0x302UL << EXTI_PR2_PIF_Pos) /*!< 0x00000302 */ +#define EXTI_PR2_PIF EXTI_PR2_PIF_Msk /*!< Pending bit */ +#define EXTI_PR2_PIF33_Pos (1U) +#define EXTI_PR2_PIF33_Msk (0x1UL << EXTI_PR2_PIF33_Pos) /*!< 0x00000002 */ +#define EXTI_PR2_PIF33 EXTI_PR2_PIF33_Msk /*!< Pending bit for line 33 */ +#define EXTI_PR2_PIF40_Pos (8U) +#define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos) /*!< 0x00000100 */ +#define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk /*!< Pending bit for line 40 */ +#define EXTI_PR2_PIF41_Pos (9U) +#define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos) /*!< 0x00000200 */ +#define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk /*!< Pending bit for line 41 */ + +/******************** Bits definition for EXTI_IMR1 register ****************/ +#define EXTI_IMR1_Pos (0U) +#define EXTI_IMR1_Msk (0xFFFFFFFFUL << EXTI_IMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_IMR1_IM EXTI_IMR1_Msk /*!< CPU1 wakeup with interrupt Mask on Event */ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< CPU1 Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< CPU1 Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< CPU1 Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< CPU1 Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< CPU1 Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< CPU1 Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< CPU1 Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< CPU1 Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< CPU1 Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< CPU1 Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< CPU1 Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< CPU1 Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< CPU1 Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< CPU1 Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< CPU1 Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< CPU1 Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< CPU1 Interrupt Mask on line 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< CPU1 Interrupt Mask on line 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< CPU1 Interrupt Mask on line 18 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< CPU1 Interrupt Mask on line 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< CPU1 Interrupt Mask on line 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< CPU1 Interrupt Mask on line 21 */ +#define EXTI_IMR1_IM22_Pos (22U) +#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< CPU1 Interrupt Mask on line 22 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< CPU1 Interrupt Mask on line 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< CPU1 Interrupt Mask on line 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU1 Interrupt Mask on line 25 */ +#define EXTI_IMR1_IM28_Pos (28U) +#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU1 Interrupt Mask on line 28 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< CPU1 Interrupt Mask on line 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< CPU1 Interrupt Mask on line 30 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< CPU1 Interrupt Mask on line 31 */ + +/******************** Bits definition for EXTI_EMR1 register ****************/ +#define EXTI_EMR1_Pos (0U) +#define EXTI_EMR1_Msk (0x003EFFFFUL << EXTI_EMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_EMR1_EM EXTI_EMR1_Msk /*!< CPU1 Event Mask */ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< CPU1 Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< CPU1 Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< CPU1 Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< CPU1 Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< CPU1 Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< CPU1 Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< CPU1 Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< CPU1 Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< CPU1 Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< CPU1 Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< CPU1 Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< CPU1 Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< CPU1 Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< CPU1 Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< CPU1 Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< CPU1 Event Mask on line 15 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< CPU1 Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< CPU1 Event Mask on line 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< CPU1 Event Mask on line 19 */ +#define EXTI_EMR1_EM20_Pos (20U) +#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< CPU1 Event Mask on line 20 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< CPU1 Event Mask on line 21 */ + +/******************** Bits definition for EXTI_IMR2 register ****************/ +#define EXTI_IMR2_Pos (0U) +#define EXTI_IMR2_Msk (0x0001FFFFUL << EXTI_IMR2_Pos) /*!< 0x0001FFFF */ +#define EXTI_IMR2_IM EXTI_IMR2_Msk /*!< CPU1 Interrupt Mask */ +#define EXTI_IMR2_IM33_Pos (1U) +#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU1 Interrupt Mask on line 33 */ +#define EXTI_IMR2_IM36_Pos (4U) +#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */ +#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< CPU1 Interrupt Mask on line 36 */ +#define EXTI_IMR2_IM37_Pos (5U) +#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */ +#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< CPU1 Interrupt Mask on line 37 */ +#define EXTI_IMR2_IM38_Pos (6U) +#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */ +#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< CPU1 Interrupt Mask on line 38 */ +#define EXTI_IMR2_IM39_Pos (7U) +#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */ +#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< CPU1 Interrupt Mask on line 39 */ +#define EXTI_IMR2_IM40_Pos (8U) +#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */ +#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< CPU1 Interrupt Mask on line 40 */ +#define EXTI_IMR2_IM41_Pos (9U) +#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */ +#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< CPU1 Interrupt Mask on line 41 */ +#define EXTI_IMR2_IM42_Pos (10U) +#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */ +#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< CPU1 Interrupt Mask on line 42 */ +#define EXTI_IMR2_IM44_Pos (12U) +#define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */ +#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< CPU1 Interrupt Mask on line 44 */ +#define EXTI_IMR2_IM45_Pos (13U) +#define EXTI_IMR2_IM45_Msk (0x1UL << EXTI_IMR2_IM45_Pos) /*!< 0x00002000 */ +#define EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk /*!< CPU1 Interrupt Mask on line 45 */ +#define EXTI_IMR2_IM46_Pos (14U) +#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */ +#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< CPU1 Interrupt Mask on line 46 */ +#define EXTI_IMR2_IM48_Pos (16U) +#define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */ +#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< CPU1 Interrupt Mask on line 48 */ + +/******************** Bits definition for EXTI_EMR2 register ****************/ +#define EXTI_EMR2_Pos (0U) +#define EXTI_EMR2_Msk (0x00000300UL << EXTI_EMR2_Pos) /*!< 0x000003000 */ +#define EXTI_EMR2_EM EXTI_EMR2_Msk /*!< CPU1 Interrupt Mask */ +#define EXTI_EMR2_EM40_Pos (8U) +#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */ +#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< CPU1 Event Mask on line 40 */ +#define EXTI_EMR2_EM41_Pos (9U) +#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */ +#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< CPU1 Event Mask on line 41 */ + +/******************** Bits definition for EXTI_C2IMR1 register **************/ +#define EXTI_C2IMR1_Pos (0U) +#define EXTI_C2IMR1_Msk (0xFFFFFFFFUL << EXTI_C2IMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_C2IMR1_IM EXTI_C2IMR1_Msk /*!< CPU2 wakeup with interrupt Mask on Event */ +#define EXTI_C2IMR1_IM0_Pos (0U) +#define EXTI_C2IMR1_IM0_Msk (0x1UL << EXTI_C2IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_C2IMR1_IM0 EXTI_C2IMR1_IM0_Msk /*!< CPU2 Interrupt Mask on line 0 */ +#define EXTI_C2IMR1_IM1_Pos (1U) +#define EXTI_C2IMR1_IM1_Msk (0x1UL << EXTI_C2IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_C2IMR1_IM1 EXTI_C2IMR1_IM1_Msk /*!< CPU2 Interrupt Mask on line 1 */ +#define EXTI_C2IMR1_IM2_Pos (2U) +#define EXTI_C2IMR1_IM2_Msk (0x1UL << EXTI_C2IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_C2IMR1_IM2 EXTI_C2IMR1_IM2_Msk /*!< CPU2 Interrupt Mask on line 2 */ +#define EXTI_C2IMR1_IM3_Pos (3U) +#define EXTI_C2IMR1_IM3_Msk (0x1UL << EXTI_C2IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_C2IMR1_IM3 EXTI_C2IMR1_IM3_Msk /*!< CPU2 Interrupt Mask on line 3 */ +#define EXTI_C2IMR1_IM4_Pos (4U) +#define EXTI_C2IMR1_IM4_Msk (0x1UL << EXTI_C2IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_C2IMR1_IM4 EXTI_C2IMR1_IM4_Msk /*!< CPU2 Interrupt Mask on line 4 */ +#define EXTI_C2IMR1_IM5_Pos (5U) +#define EXTI_C2IMR1_IM5_Msk (0x1UL << EXTI_C2IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_C2IMR1_IM5 EXTI_C2IMR1_IM5_Msk /*!< CPU2 Interrupt Mask on line 5 */ +#define EXTI_C2IMR1_IM6_Pos (6U) +#define EXTI_C2IMR1_IM6_Msk (0x1UL << EXTI_C2IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_C2IMR1_IM6 EXTI_C2IMR1_IM6_Msk /*!< CPU2 Interrupt Mask on line 6 */ +#define EXTI_C2IMR1_IM7_Pos (7U) +#define EXTI_C2IMR1_IM7_Msk (0x1UL << EXTI_C2IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_C2IMR1_IM7 EXTI_C2IMR1_IM7_Msk /*!< CPU2 Interrupt Mask on line 7 */ +#define EXTI_C2IMR1_IM8_Pos (8U) +#define EXTI_C2IMR1_IM8_Msk (0x1UL << EXTI_C2IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_C2IMR1_IM8 EXTI_C2IMR1_IM8_Msk /*!< CPU2 Interrupt Mask on line 8 */ +#define EXTI_C2IMR1_IM9_Pos (9U) +#define EXTI_C2IMR1_IM9_Msk (0x1UL << EXTI_C2IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_C2IMR1_IM9 EXTI_C2IMR1_IM9_Msk /*!< CPU2 Interrupt Mask on line 9 */ +#define EXTI_C2IMR1_IM10_Pos (10U) +#define EXTI_C2IMR1_IM10_Msk (0x1UL << EXTI_C2IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_C2IMR1_IM10 EXTI_C2IMR1_IM10_Msk /*!< CPU2 Interrupt Mask on line 10 */ +#define EXTI_C2IMR1_IM11_Pos (11U) +#define EXTI_C2IMR1_IM11_Msk (0x1UL << EXTI_C2IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_C2IMR1_IM11 EXTI_C2IMR1_IM11_Msk /*!< CPU2 Interrupt Mask on line 11 */ +#define EXTI_C2IMR1_IM12_Pos (12U) +#define EXTI_C2IMR1_IM12_Msk (0x1UL << EXTI_C2IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_C2IMR1_IM12 EXTI_C2IMR1_IM12_Msk /*!< CPU2 Interrupt Mask on line 12 */ +#define EXTI_C2IMR1_IM13_Pos (13U) +#define EXTI_C2IMR1_IM13_Msk (0x1UL << EXTI_C2IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_C2IMR1_IM13 EXTI_C2IMR1_IM13_Msk /*!< CPU2 Interrupt Mask on line 13 */ +#define EXTI_C2IMR1_IM14_Pos (14U) +#define EXTI_C2IMR1_IM14_Msk (0x1UL << EXTI_C2IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_C2IMR1_IM14 EXTI_C2IMR1_IM14_Msk /*!< CPU2 Interrupt Mask on line 14 */ +#define EXTI_C2IMR1_IM15_Pos (15U) +#define EXTI_C2IMR1_IM15_Msk (0x1UL << EXTI_C2IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_C2IMR1_IM15 EXTI_C2IMR1_IM15_Msk /*!< CPU2 Interrupt Mask on line 15 */ +#define EXTI_C2IMR1_IM16_Pos (16U) +#define EXTI_C2IMR1_IM16_Msk (0x1UL << EXTI_C2IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_C2IMR1_IM16 EXTI_C2IMR1_IM16_Msk /*!< CPU2 Interrupt Mask on line 16 */ +#define EXTI_C2IMR1_IM17_Pos (17U) +#define EXTI_C2IMR1_IM17_Msk (0x1UL << EXTI_C2IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_C2IMR1_IM17 EXTI_C2IMR1_IM17_Msk /*!< CPU2 Interrupt Mask on line 17 */ +#define EXTI_C2IMR1_IM18_Pos (18U) +#define EXTI_C2IMR1_IM18_Msk (0x1UL << EXTI_C2IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_C2IMR1_IM18 EXTI_C2IMR1_IM18_Msk /*!< CPU2 Interrupt Mask on line 18 */ +#define EXTI_C2IMR1_IM19_Pos (19U) +#define EXTI_C2IMR1_IM19_Msk (0x1UL << EXTI_C2IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_C2IMR1_IM19 EXTI_C2IMR1_IM19_Msk /*!< CPU2 Interrupt Mask on line 19 */ +#define EXTI_C2IMR1_IM20_Pos (20U) +#define EXTI_C2IMR1_IM20_Msk (0x1UL << EXTI_C2IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_C2IMR1_IM20 EXTI_C2IMR1_IM20_Msk /*!< CPU2 Interrupt Mask on line 20 */ +#define EXTI_C2IMR1_IM21_Pos (21U) +#define EXTI_C2IMR1_IM21_Msk (0x1UL << EXTI_C2IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_C2IMR1_IM21 EXTI_C2IMR1_IM21_Msk /*!< CPU2 Interrupt Mask on line 21 */ +#define EXTI_C2IMR1_IM22_Pos (22U) +#define EXTI_C2IMR1_IM22_Msk (0x1UL << EXTI_C2IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_C2IMR1_IM22 EXTI_C2IMR1_IM22_Msk /*!< CPU2 Interrupt Mask on line 22 */ +#define EXTI_C2IMR1_IM23_Pos (23U) +#define EXTI_C2IMR1_IM23_Msk (0x1UL << EXTI_C2IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_C2IMR1_IM23 EXTI_C2IMR1_IM23_Msk /*!< CPU2 Interrupt Mask on line 23 */ +#define EXTI_C2IMR1_IM24_Pos (24U) +#define EXTI_C2IMR1_IM24_Msk (0x1UL << EXTI_C2IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_C2IMR1_IM24 EXTI_C2IMR1_IM24_Msk /*!< CPU2 Interrupt Mask on line 24 */ +#define EXTI_C2IMR1_IM25_Pos (25U) +#define EXTI_C2IMR1_IM25_Msk (0x1UL << EXTI_C2IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_C2IMR1_IM25 EXTI_C2IMR1_IM25_Msk /*!< CPU2 Interrupt Mask on line 25 */ +#define EXTI_C2IMR1_IM28_Pos (28U) +#define EXTI_C2IMR1_IM28_Msk (0x1UL << EXTI_C2IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_C2IMR1_IM28 EXTI_C2IMR1_IM28_Msk /*!< CPU2 Interrupt Mask on line 28 */ +#define EXTI_C2IMR1_IM29_Pos (29U) +#define EXTI_C2IMR1_IM29_Msk (0x1UL << EXTI_C2IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_C2IMR1_IM29 EXTI_C2IMR1_IM29_Msk /*!< CPU2 Interrupt Mask on line 29 */ +#define EXTI_C2IMR1_IM30_Pos (30U) +#define EXTI_C2IMR1_IM30_Msk (0x1UL << EXTI_C2IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_C2IMR1_IM30 EXTI_C2IMR1_IM30_Msk /*!< CPU2 Interrupt Mask on line 30 */ +#define EXTI_C2IMR1_IM31_Pos (31U) +#define EXTI_C2IMR1_IM31_Msk (0x1UL << EXTI_C2IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_C2IMR1_IM31 EXTI_C2IMR1_IM31_Msk /*!< CPU2 Interrupt Mask on line 31 */ +/******************** Bits definition for EXTI_C2EMR1 register **************/ +#define EXTI_C2EMR1_Pos (0U) +#define EXTI_C2EMR1_Msk (0x003EFFFFUL << EXTI_C2EMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_C2EMR1_EM EXTI_C2EMR1_Msk /*!< CPU2 Event Mask */ +#define EXTI_C2EMR1_EM0_Pos (0U) +#define EXTI_C2EMR1_EM0_Msk (0x1UL << EXTI_C2EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_C2EMR1_EM0 EXTI_C2EMR1_EM0_Msk /*!< CPU2 Event Mask on line 0 */ +#define EXTI_C2EMR1_EM1_Pos (1U) +#define EXTI_C2EMR1_EM1_Msk (0x1UL << EXTI_C2EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_C2EMR1_EM1 EXTI_C2EMR1_EM1_Msk /*!< CPU2 Event Mask on line 1 */ +#define EXTI_C2EMR1_EM2_Pos (2U) +#define EXTI_C2EMR1_EM2_Msk (0x1UL << EXTI_C2EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_C2EMR1_EM2 EXTI_C2EMR1_EM2_Msk /*!< CPU2 Event Mask on line 2 */ +#define EXTI_C2EMR1_EM3_Pos (3U) +#define EXTI_C2EMR1_EM3_Msk (0x1UL << EXTI_C2EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_C2EMR1_EM3 EXTI_C2EMR1_EM3_Msk /*!< CPU2 Event Mask on line 3 */ +#define EXTI_C2EMR1_EM4_Pos (4U) +#define EXTI_C2EMR1_EM4_Msk (0x1UL << EXTI_C2EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_C2EMR1_EM4 EXTI_C2EMR1_EM4_Msk /*!< CPU2 Event Mask on line 4 */ +#define EXTI_C2EMR1_EM5_Pos (5U) +#define EXTI_C2EMR1_EM5_Msk (0x1UL << EXTI_C2EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_C2EMR1_EM5 EXTI_C2EMR1_EM5_Msk /*!< CPU2 Event Mask on line 5 */ +#define EXTI_C2EMR1_EM6_Pos (6U) +#define EXTI_C2EMR1_EM6_Msk (0x1UL << EXTI_C2EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_C2EMR1_EM6 EXTI_C2EMR1_EM6_Msk /*!< CPU2 Event Mask on line 6 */ +#define EXTI_C2EMR1_EM7_Pos (7U) +#define EXTI_C2EMR1_EM7_Msk (0x1UL << EXTI_C2EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_C2EMR1_EM7 EXTI_C2EMR1_EM7_Msk /*!< CPU2 Event Mask on line 7 */ +#define EXTI_C2EMR1_EM8_Pos (8U) +#define EXTI_C2EMR1_EM8_Msk (0x1UL << EXTI_C2EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_C2EMR1_EM8 EXTI_C2EMR1_EM8_Msk /*!< CPU2 Event Mask on line 8 */ +#define EXTI_C2EMR1_EM9_Pos (9U) +#define EXTI_C2EMR1_EM9_Msk (0x1UL << EXTI_C2EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_C2EMR1_EM9 EXTI_C2EMR1_EM9_Msk /*!< CPU2 Event Mask on line 9 */ +#define EXTI_C2EMR1_EM10_Pos (10U) +#define EXTI_C2EMR1_EM10_Msk (0x1UL << EXTI_C2EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_C2EMR1_EM10 EXTI_C2EMR1_EM10_Msk /*!< CPU2 Event Mask on line 10 */ +#define EXTI_C2EMR1_EM11_Pos (11U) +#define EXTI_C2EMR1_EM11_Msk (0x1UL << EXTI_C2EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_C2EMR1_EM11 EXTI_C2EMR1_EM11_Msk /*!< CPU2 Event Mask on line 11 */ +#define EXTI_C2EMR1_EM12_Pos (12U) +#define EXTI_C2EMR1_EM12_Msk (0x1UL << EXTI_C2EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_C2EMR1_EM12 EXTI_C2EMR1_EM12_Msk /*!< CPU2 Event Mask on line 12 */ +#define EXTI_C2EMR1_EM13_Pos (13U) +#define EXTI_C2EMR1_EM13_Msk (0x1UL << EXTI_C2EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_C2EMR1_EM13 EXTI_C2EMR1_EM13_Msk /*!< CPU2 Event Mask on line 13 */ +#define EXTI_C2EMR1_EM14_Pos (14U) +#define EXTI_C2EMR1_EM14_Msk (0x1UL << EXTI_C2EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_C2EMR1_EM14 EXTI_C2EMR1_EM14_Msk /*!< CPU2 Event Mask on line 14 */ +#define EXTI_C2EMR1_EM15_Pos (15U) +#define EXTI_C2EMR1_EM15_Msk (0x1UL << EXTI_C2EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_C2EMR1_EM15 EXTI_C2EMR1_EM15_Msk /*!< CPU2 Event Mask on line 15 */ +#define EXTI_C2EMR1_EM17_Pos (17U) +#define EXTI_C2EMR1_EM17_Msk (0x1UL << EXTI_C2EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_C2EMR1_EM17 EXTI_C2EMR1_EM17_Msk /*!< CPU2 Event Mask on line 17 */ +#define EXTI_C2EMR1_EM18_Pos (18U) +#define EXTI_C2EMR1_EM18_Msk (0x1UL << EXTI_C2EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_C2EMR1_EM18 EXTI_C2EMR1_EM18_Msk /*!< CPU2 Event Mask on line 18 */ +#define EXTI_C2EMR1_EM19_Pos (19U) +#define EXTI_C2EMR1_EM19_Msk (0x1UL << EXTI_C2EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_C2EMR1_EM19 EXTI_C2EMR1_EM19_Msk /*!< CPU2 Event Mask on line 19 */ +#define EXTI_C2EMR1_EM20_Pos (20U) +#define EXTI_C2EMR1_EM20_Msk (0x1UL << EXTI_C2EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_C2EMR1_EM20 EXTI_C2EMR1_EM20_Msk /*!< CPU2 Event Mask on line 20 */ +#define EXTI_C2EMR1_EM21_Pos (21U) +#define EXTI_C2EMR1_EM21_Msk (0x1UL << EXTI_C2EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_C2EMR1_EM21 EXTI_C2EMR1_EM21_Msk /*!< CPU2 Event Mask on line 21 */ + +/******************** Bits definition for EXTI_C2IMR2 register **************/ +#define EXTI_C2IMR2_Pos (0U) +#define EXTI_C2IMR2_Msk (0x0001FFFFUL << EXTI_C2IMR2_Pos) /*!< 0x0001FFFF */ +#define EXTI_C2IMR2_IM EXTI_C2IMR2_Msk /*!< CPU2 Interrupt Mask */ +#define EXTI_C2IMR2_IM33_Pos (1U) +#define EXTI_C2IMR2_IM33_Msk (0x1UL << EXTI_C2IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_C2IMR2_IM33 EXTI_C2IMR2_IM33_Msk /*!< CPU2 Interrupt Mask on line 33 */ +#define EXTI_C2IMR2_IM36_Pos (4U) +#define EXTI_C2IMR2_IM36_Msk (0x1UL << EXTI_C2IMR2_IM36_Pos) /*!< 0x00000010 */ +#define EXTI_C2IMR2_IM36 EXTI_C2IMR2_IM36_Msk /*!< CPU2 Interrupt Mask on line 36 */ +#define EXTI_C2IMR2_IM37_Pos (5U) +#define EXTI_C2IMR2_IM37_Msk (0x1UL << EXTI_C2IMR2_IM37_Pos) /*!< 0x00000020 */ +#define EXTI_C2IMR2_IM37 EXTI_C2IMR2_IM37_Msk /*!< CPU2 Interrupt Mask on line 37 */ +#define EXTI_C2IMR2_IM38_Pos (6U) +#define EXTI_C2IMR2_IM38_Msk (0x1UL << EXTI_C2IMR2_IM38_Pos) /*!< 0x00000040 */ +#define EXTI_C2IMR2_IM38 EXTI_C2IMR2_IM38_Msk /*!< CPU2 Interrupt Mask on line 38 */ +#define EXTI_C2IMR2_IM39_Pos (7U) +#define EXTI_C2IMR2_IM39_Msk (0x1UL << EXTI_C2IMR2_IM39_Pos) /*!< 0x00000080 */ +#define EXTI_C2IMR2_IM39 EXTI_C2IMR2_IM39_Msk /*!< CPU2 Interrupt Mask on line 39 */ +#define EXTI_C2IMR2_IM40_Pos (8U) +#define EXTI_C2IMR2_IM40_Msk (0x1UL << EXTI_C2IMR2_IM40_Pos) /*!< 0x00000100 */ +#define EXTI_C2IMR2_IM40 EXTI_C2IMR2_IM40_Msk /*!< CPU2 Interrupt Mask on line 40 */ +#define EXTI_C2IMR2_IM41_Pos (9U) +#define EXTI_C2IMR2_IM41_Msk (0x1UL << EXTI_C2IMR2_IM41_Pos) /*!< 0x00000200 */ +#define EXTI_C2IMR2_IM41 EXTI_C2IMR2_IM41_Msk /*!< CPU2 Interrupt Mask on line 41 */ +#define EXTI_C2IMR2_IM42_Pos (10U) +#define EXTI_C2IMR2_IM42_Msk (0x1UL << EXTI_C2IMR2_IM42_Pos) /*!< 0x00000400 */ +#define EXTI_C2IMR2_IM42 EXTI_C2IMR2_IM42_Msk /*!< CPU2 Interrupt Mask on line 42 */ +#define EXTI_C2IMR2_IM44_Pos (12U) +#define EXTI_C2IMR2_IM44_Msk (0x1UL << EXTI_C2IMR2_IM44_Pos) /*!< 0x00001000 */ +#define EXTI_C2IMR2_IM44 EXTI_C2IMR2_IM44_Msk /*!< CPU2 Interrupt Mask on line 44 */ +#define EXTI_C2IMR2_IM45_Pos (13U) +#define EXTI_C2IMR2_IM45_Msk (0x1UL << EXTI_C2IMR2_IM45_Pos) /*!< 0x00002000 */ +#define EXTI_C2IMR2_IM45 EXTI_C2IMR2_IM45_Msk /*!< CPU2 Interrupt Mask on line 45 */ +#define EXTI_C2IMR2_IM46_Pos (14U) +#define EXTI_C2IMR2_IM46_Msk (0x1UL << EXTI_C2IMR2_IM46_Pos) /*!< 0x00004000 */ +#define EXTI_C2IMR2_IM46 EXTI_C2IMR2_IM46_Msk /*!< CPU2 Interrupt Mask on line 46 */ +#define EXTI_C2IMR2_IM48_Pos (16U) +#define EXTI_C2IMR2_IM48_Msk (0x1UL << EXTI_C2IMR2_IM48_Pos) /*!< 0x00010000 */ +#define EXTI_C2IMR2_IM48 EXTI_C2IMR2_IM48_Msk /*!< CPU2 Interrupt Mask on line 48 */ + +/******************** Bits definition for EXTI_C2EMR2 register **************/ +#define EXTI_C2EMR2_Pos (8U) +#define EXTI_C2EMR2_Msk (0x00000300UL << EXTI_C2EMR2_Pos) /*!< 0x000003000 */ +#define EXTI_C2EMR2_EM EXTI_C2EMR2_Msk /*!< CPU2 Interrupt Mask */ +#define EXTI_C2EMR2_EM40_Pos (8U) +#define EXTI_C2EMR2_EM40_Msk (0x1UL << EXTI_C2EMR2_EM40_Pos) /*!< 0x00000100 */ +#define EXTI_C2EMR2_EM40 EXTI_C2EMR2_EM40_Msk /*!< CPU2 Event Mask on line 40 */ +#define EXTI_C2EMR2_EM41_Pos (9U) +#define EXTI_C2EMR2_EM41_Msk (0x1UL << EXTI_C2EMR2_EM41_Pos) /*!< 0x00000200 */ +#define EXTI_C2EMR2_EM41 EXTI_C2EMR2_EM41_Msk /*!< CPU2 Event Mask on line 41 */ + +/******************************************************************************/ +/* */ +/* Public Key Accelerator (PKA) */ +/* */ +/******************************************************************************/ + +/******************* Bits definition for PKA_CR register **************/ +#define PKA_CR_EN_Pos (0U) +#define PKA_CR_EN_Msk (0x1UL << PKA_CR_EN_Pos) /*!< 0x00000001 */ +#define PKA_CR_EN PKA_CR_EN_Msk /*!< PKA enable */ +#define PKA_CR_START_Pos (1U) +#define PKA_CR_START_Msk (0x1UL << PKA_CR_START_Pos) /*!< 0x00000002 */ +#define PKA_CR_START PKA_CR_START_Msk /*!< Start operation */ +#define PKA_CR_MODE_Pos (8U) +#define PKA_CR_MODE_Msk (0x3FUL << PKA_CR_MODE_Pos) /*!< 0x00003F00 */ +#define PKA_CR_MODE PKA_CR_MODE_Msk /*!< MODE[5:0] PKA operation code */ +#define PKA_CR_MODE_0 (0x01U << PKA_CR_MODE_Pos) /*!< 0x00000100 */ +#define PKA_CR_MODE_1 (0x02U << PKA_CR_MODE_Pos) /*!< 0x00000200 */ +#define PKA_CR_MODE_2 (0x04U << PKA_CR_MODE_Pos) /*!< 0x00000400 */ +#define PKA_CR_MODE_3 (0x08U << PKA_CR_MODE_Pos) /*!< 0x00000800 */ +#define PKA_CR_MODE_4 (0x10U << PKA_CR_MODE_Pos) /*!< 0x00001000 */ +#define PKA_CR_MODE_5 (0x20U << PKA_CR_MODE_Pos) /*!< 0x00002000 */ +#define PKA_CR_PROCENDIE_Pos (17U) +#define PKA_CR_PROCENDIE_Msk (0x1UL << PKA_CR_PROCENDIE_Pos) /*!< 0x00020000 */ +#define PKA_CR_PROCENDIE PKA_CR_PROCENDIE_Msk /*!< End of operation interrupt enable */ +#define PKA_CR_RAMERRIE_Pos (19U) +#define PKA_CR_RAMERRIE_Msk (0x1UL << PKA_CR_RAMERRIE_Pos) /*!< 0x00080000 */ +#define PKA_CR_RAMERRIE PKA_CR_RAMERRIE_Msk /*!< RAM error interrupt enable */ +#define PKA_CR_ADDRERRIE_Pos (20U) +#define PKA_CR_ADDRERRIE_Msk (0x1UL << PKA_CR_ADDRERRIE_Pos) /*!< 0x00100000 */ +#define PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE_Msk /*!< RAM error interrupt enable */ + +/******************* Bits definition for PKA_SR register **************/ +#define PKA_SR_BUSY_Pos (16U) +#define PKA_SR_BUSY_Msk (0x1UL << PKA_SR_BUSY_Pos) /*!< 0x00010000 */ +#define PKA_SR_BUSY PKA_SR_BUSY_Msk /*!< PKA operation is in progress */ +#define PKA_SR_PROCENDF_Pos (17U) +#define PKA_SR_PROCENDF_Msk (0x1UL << PKA_SR_PROCENDF_Pos) /*!< 0x00020000 */ +#define PKA_SR_PROCENDF PKA_SR_PROCENDF_Msk /*!< PKA end of operation flag */ +#define PKA_SR_RAMERRF_Pos (19U) +#define PKA_SR_RAMERRF_Msk (0x1UL << PKA_SR_RAMERRF_Pos) /*!< 0x00080000 */ +#define PKA_SR_RAMERRF PKA_SR_RAMERRF_Msk /*!< PKA RAM error flag */ +#define PKA_SR_ADDRERRF_Pos (20U) +#define PKA_SR_ADDRERRF_Msk (0x1UL << PKA_SR_ADDRERRF_Pos) /*!< 0x00100000 */ +#define PKA_SR_ADDRERRF PKA_SR_ADDRERRF_Msk /*!< Address error flag */ + +/******************* Bits definition for PKA_CLRFR register **************/ +#define PKA_CLRFR_PROCENDFC_Pos (17U) +#define PKA_CLRFR_PROCENDFC_Msk (0x1UL << PKA_CLRFR_PROCENDFC_Pos) /*!< 0x00020000 */ +#define PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC_Msk /*!< Clear PKA end of operation flag */ +#define PKA_CLRFR_RAMERRFC_Pos (19U) +#define PKA_CLRFR_RAMERRFC_Msk (0x1UL << PKA_CLRFR_RAMERRFC_Pos) /*!< 0x00080000 */ +#define PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC_Msk /*!< Clear PKA RAM error flag */ +#define PKA_CLRFR_ADDRERRFC_Pos (20U) +#define PKA_CLRFR_ADDRERRFC_Msk (0x1UL << PKA_CLRFR_ADDRERRFC_Pos) /*!< 0x00100000 */ +#define PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC_Msk /*!< Clear address error flag */ + +/******************* Bits definition for PKA RAM *************************/ +#define PKA_RAM_OFFSET 0x400U /*!< PKA RAM address offset */ + +/* Compute Montgomery parameter input data */ +#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1 ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 1 */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 2 */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 3 */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1 ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Output last double X1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output last double Y1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1 ((0xE90U - PKA_RAM_OFFSET)>>2) /*!< Output last double Z1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2 ((0xEE4U - PKA_RAM_OFFSET)>>2) /*!< Output check point X2 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2 ((0xF38U - PKA_RAM_OFFSET)>>2) /*!< Output check point Y2 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2 ((0xF8CU - PKA_RAM_OFFSET)>>2) /*!< Output check point Z2 coordinate */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x7FCU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0xE94U - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0xEE8U - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x700U - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x754U - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x103CU - PKA_RAM_OFFSET)>>2) /*!< Output final point kP X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1090U - PKA_RAM_OFFSET)>>2) /*!< Output final point kP Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x45CU - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x4B8U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x5E8U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x63CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0xF40U - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0xF94U - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x1098U - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0xFE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x65CU - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x7ECU - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x97CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0xEECU - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic substraction input data */ +#define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic substraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular substraction input data */ +#define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular substraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_ICEN_Pos (9U) +#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk /*!< Instruction cache enable */ +#define FLASH_ACR_DCEN_Pos (10U) +#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */ +#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk /*!< Data cache enable */ +#define FLASH_ACR_ICRST_Pos (11U) +#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk /*!< Instruction cache reset */ +#define FLASH_ACR_DCRST_Pos (12U) +#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk /*!< Data cache reset */ +#define FLASH_ACR_PES_Pos (15U) +#define FLASH_ACR_PES_Msk (0x1UL << FLASH_ACR_PES_Pos) /*!< 0x00008000 */ +#define FLASH_ACR_PES FLASH_ACR_PES_Msk /*!< Program/erase suspend request */ +#define FLASH_ACR_EMPTY_Pos (16U) +#define FLASH_ACR_EMPTY_Msk (0x1UL << FLASH_ACR_EMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_EMPTY FLASH_ACR_EMPTY_Msk /*!< Flash use area empty */ + +#define FLASH_ACR_LATENCY_0WS (0x0UL << FLASH_ACR_LATENCY_Pos) /*!< FLASH Zero wait state */ +#define FLASH_ACR_LATENCY_1WS (FLASH_ACR_LATENCY_0 << FLASH_ACR_LATENCY_Pos) /*!< FLASH One wait state */ +#define FLASH_ACR_LATENCY_2WS (FLASH_ACR_LATENCY_1 << FLASH_ACR_LATENCY_Pos) /*!< FLASH Two wait states */ +#define FLASH_ACR_LATENCY_3WS ((FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) << FLASH_ACR_LATENCY_Pos) /*!< FLASH Three wait states */ + +/******************* Bits definition for FLASH_SR register ******************/ +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of Operation */ +#define FLASH_SR_OPERR_Pos (1U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Operation error */ +#define FLASH_SR_PROGERR_Pos (3U) +#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk /*!< Programming error */ +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */ +#define FLASH_SR_PGAERR_Pos (5U) +#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming alignment error */ +#define FLASH_SR_SIZERR_Pos (6U) +#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ +#define FLASH_SR_PGSERR_Pos (7U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error */ +#define FLASH_SR_MISERR_Pos (8U) +#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk /*!< Fast programming data miss error */ +#define FLASH_SR_FASTERR_Pos (9U) +#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk /*!< Fast programming error */ +#define FLASH_SR_OPTNV_Pos (13U) +#define FLASH_SR_OPTNV_Msk (0x1UL << FLASH_SR_OPTNV_Pos) /*!< 0x00002000 */ +#define FLASH_SR_OPTNV FLASH_SR_OPTNV_Msk /*!< User option OPTVAL indication */ +#define FLASH_SR_RDERR_Pos (14U) +#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< PCROP read error */ +#define FLASH_SR_OPTVERR_Pos (15U) +#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option validity error */ +#define FLASH_SR_BSY_Pos (16U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Flash Busy */ +#define FLASH_SR_CFGBSY_Pos (18U) +#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk /*!< Programming or erase configuration busy */ +#define FLASH_SR_PESD_Pos (19U) +#define FLASH_SR_PESD_Msk (0x1UL << FLASH_SR_PESD_Pos) /*!< 0x00080000 */ +#define FLASH_SR_PESD FLASH_SR_PESD_Msk /*!< Programming/erase operation suspended */ + +/******************* Bits definition for FLASH_CR register ******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Flash programming */ +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page erase */ +#define FLASH_CR_MER_Pos (2U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ +#define FLASH_CR_PNB_Pos (3U) +#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk /*!< Page number selection mask */ +#define FLASH_CR_STRT_Pos (16U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start an erase operation */ +#define FLASH_CR_OPTSTRT_Pos (17U) +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk /*!< Options modification start */ +#define FLASH_CR_FSTPG_Pos (18U) +#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk /*!< Fast programming */ +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error interrupt enable */ +#define FLASH_CR_RDERRIE_Pos (26U) +#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk /*!< PCROP read error interrupt enable */ +#define FLASH_CR_OBL_LAUNCH_Pos (27U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_CR_OPTLOCK_Pos (30U) +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk /*!< Options lock */ +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Flash control register lock */ + +/******************* Bits definition for FLASH_ECCR register ****************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0001FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< double-word address ECC fail */ +#define FLASH_ECCR_SYSF_ECC_Pos (20U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System flash ECC fail */ +#define FLASH_ECCR_ECCCIE_Pos (24U) +#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_CPUID_Pos (26U) +#define FLASH_ECCR_CPUID_Msk (0x7UL << FLASH_ECCR_CPUID_Pos) /*!< 0x1C000000 */ +#define FLASH_ECCR_CPUID FLASH_ECCR_CPUID_Msk /*!< CPU identification */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPTR register ****************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Read protection level */ +#define FLASH_OPTR_ESE_Pos (8U) +#define FLASH_OPTR_ESE_Msk (0x1UL << FLASH_OPTR_ESE_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_ESE FLASH_OPTR_ESE_Msk /*!< Security enable */ +#define FLASH_OPTR_BOR_LEV_Pos (9U) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000E00 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset level mask */ +#define FLASH_OPTR_BOR_LEV_0 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000800 */ +#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< Reset option in Stop mode */ +#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< Reset option in Standby mode */ +#define FLASH_OPTR_nRST_SHDW_Pos (14U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< Reset option in Shutdown mode */ +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter option in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter option in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_nBOOT1_Pos (23U) +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk /*!< Boot Configuration */ +#define FLASH_OPTR_SRAM2PE_Pos (24U) +#define FLASH_OPTR_SRAM2PE_Msk (0x1UL << FLASH_OPTR_SRAM2PE_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2PE FLASH_OPTR_SRAM2PE_Msk /*!< SRAM2 parity check enable */ +#define FLASH_OPTR_SRAM2RST_Pos (25U) +#define FLASH_OPTR_SRAM2RST_Msk (0x1UL << FLASH_OPTR_SRAM2RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2RST FLASH_OPTR_SRAM2RST_Msk /*!< SRAM2 erase option when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< BOOT0 option bit */ +#define FLASH_OPTR_AGC_TRIM_Pos (29U) +#define FLASH_OPTR_AGC_TRIM_Msk (0x7UL << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0xE0000000 */ +#define FLASH_OPTR_AGC_TRIM FLASH_OPTR_AGC_TRIM_Msk /*!< Automatic Gain Control trimming mask */ +#define FLASH_OPTR_AGC_TRIM_0 (0x1U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_AGC_TRIM_1 (0x2U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_AGC_TRIM_2 (0x4U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for FLASH_PCROP1ASR register ************/ +#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U) +#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0xFFUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x000000FF */ +#define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk /*!< PCROP area A start offset */ + +/****************** Bits definition for FLASH_PCROP1AER register ************/ +#define FLASH_PCROP1AER_PCROP1A_END_Pos (0U) +#define FLASH_PCROP1AER_PCROP1A_END_Msk (0xFFUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x000000FF */ +#define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk /*!< PCROP area A end offset */ +#define FLASH_PCROP1AER_PCROP_RDP_Pos (31U) +#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */ +#define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk /*!< PCROP area preserved when RDP level decreased */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk /*!< WRP area A start offset */ +#define FLASH_WRP1AR_WRP1A_END_Pos (16U) +#define FLASH_WRP1AR_WRP1A_END_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk /*!< WRP area A end offset */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk /*!< WRP area B start offset */ +#define FLASH_WRP1BR_WRP1B_END_Pos (16U) +#define FLASH_WRP1BR_WRP1B_END_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk /*!< WRP area B end offset */ + +/****************** Bits definition for FLASH_PCROP1BSR register ************/ +#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U) +#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0xFFUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x000000FF */ +#define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk /*!< PCROP area B start offset */ + +/****************** Bits definition for FLASH_PCROP1BER register ************/ +#define FLASH_PCROP1BER_PCROP1B_END_Pos (0U) +#define FLASH_PCROP1BER_PCROP1B_END_Msk (0xFFUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x000000FF */ +#define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk /*!< PCROP area B end offset */ + +/****************** Bits definition for FLASH_IPCCBR register ************/ +#define FLASH_IPCCBR_IPCCDBA_Pos (0U) +#define FLASH_IPCCBR_IPCCDBA_Msk (0x3FFFUL << FLASH_IPCCBR_IPCCDBA_Pos) /*!< 0x00003FFF */ +#define FLASH_IPCCBR_IPCCDBA FLASH_IPCCBR_IPCCDBA_Msk /*!< IPCC data buffer base address */ + +/****************** Bits definition for FLASH_SFR register ************/ +#define FLASH_SFR_SFSA_Pos (0U) +#define FLASH_SFR_SFSA_Msk (0x7FUL << FLASH_SFR_SFSA_Pos) /*!< 0x0000007F */ +#define FLASH_SFR_SFSA FLASH_SFR_SFSA_Msk /* Secure flash start address */ +#define FLASH_SFR_FSD_Pos (7U) +#define FLASH_SFR_FSD_Msk (0x1UL << FLASH_SFR_FSD_Pos) /*!< 0x00000100 */ +#define FLASH_SFR_FSD FLASH_SFR_FSD_Msk /* Flash mode secure */ +#define FLASH_SFR_DDS_Pos (12U) +#define FLASH_SFR_DDS_Msk (0x1UL << FLASH_SFR_DDS_Pos) /*!< 0x00001000 */ +#define FLASH_SFR_DDS FLASH_SFR_DDS_Msk /* Enabling and disabling CPU2 Debug access */ + +/****************** Bits definition for FLASH_SRRVR register ************/ +#define FLASH_SRRVR_SBRV_Pos (0U) +#define FLASH_SRRVR_SBRV_Msk (0x1FFFFUL << FLASH_SRRVR_SBRV_Pos) /*!< 0x0001FFFF */ +#define FLASH_SRRVR_SBRV FLASH_SRRVR_SBRV_Msk /* SCPU2 boot reset vector memory offset */ + +#define FLASH_SRRVR_SBRSA_Pos (18U) +#define FLASH_SRRVR_SBRSA_Msk (0x1FUL << FLASH_SRRVR_SBRSA_Pos) /*!< 0x007C0000 */ +#define FLASH_SRRVR_SBRSA FLASH_SRRVR_SBRSA_Msk /* Secure backup SRAM2a start address */ +#define FLASH_SRRVR_BRSD_Pos (23U) +#define FLASH_SRRVR_BRSD_Msk (0x1UL << FLASH_SRRVR_BRSD_Pos) /*!< 0x00800000 */ +#define FLASH_SRRVR_BRSD FLASH_SRRVR_BRSD_Msk /* Backup SRAM2A secure mode */ + +#define FLASH_SRRVR_SNBRSA_Pos (25U) +#define FLASH_SRRVR_SNBRSA_Msk (0x1FUL << FLASH_SRRVR_SNBRSA_Pos) /*!< 0x3E000000 */ +#define FLASH_SRRVR_SNBRSA FLASH_SRRVR_SNBRSA_Msk /* Secure non-backup SRAM2b start address */ +#define FLASH_SRRVR_NBRSD_Pos (30U) +#define FLASH_SRRVR_NBRSD_Msk (0x1UL << FLASH_SRRVR_NBRSD_Pos) /*!< 0x40000000 */ +#define FLASH_SRRVR_NBRSD FLASH_SRRVR_NBRSD_Msk /* Non-backup SRAM2B secure mode */ +#define FLASH_SRRVR_C2OPT_Pos (31U) +#define FLASH_SRRVR_C2OPT_Msk (0x1UL << FLASH_SRRVR_C2OPT_Pos) /*!< 0x80000000 */ +#define FLASH_SRRVR_C2OPT FLASH_SRRVR_C2OPT_Msk /* SCPU2 boot reset vector memory selection */ + +/****************** Bits definition for FLASH_C2ACR register ************/ +#define FLASH_C2ACR_PRFTEN_Pos (8U) +#define FLASH_C2ACR_PRFTEN_Msk (0x1UL << FLASH_C2ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_C2ACR_PRFTEN FLASH_C2ACR_PRFTEN_Msk /*!< CPU2 Prefetch enable */ +#define FLASH_C2ACR_ICEN_Pos (9U) +#define FLASH_C2ACR_ICEN_Msk (0x1UL << FLASH_C2ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_C2ACR_ICEN FLASH_C2ACR_ICEN_Msk /*!< CPU2 Instruction cache enable */ +#define FLASH_C2ACR_ICRST_Pos (11U) +#define FLASH_C2ACR_ICRST_Msk (0x1UL << FLASH_C2ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_C2ACR_ICRST FLASH_C2ACR_ICRST_Msk /*!< CPU2 Instruction cache reset */ +#define FLASH_C2ACR_PES_Pos (15U) +#define FLASH_C2ACR_PES_Msk (0x1UL << FLASH_C2ACR_PES_Pos) /*!< 0x00008000 */ +#define FLASH_C2ACR_PES FLASH_C2ACR_PES_Msk /*!< CPU2 Program/erase suspend request */ + +/****************** Bits definition for FLASH_C2SR register ************/ +#define FLASH_C2SR_EOP_Pos (0U) +#define FLASH_C2SR_EOP_Msk (0x1UL << FLASH_C2SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_C2SR_EOP FLASH_C2SR_EOP_Msk /*!< CPU2 End of operation */ +#define FLASH_C2SR_OPERR_Pos (1U) +#define FLASH_C2SR_OPERR_Msk (0x1UL << FLASH_C2SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_C2SR_OPERR FLASH_C2SR_OPERR_Msk /*!< CPU2 Operation error */ +#define FLASH_C2SR_PROGERR_Pos (3U) +#define FLASH_C2SR_PROGERR_Msk (0x1UL << FLASH_C2SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_C2SR_PROGERR FLASH_C2SR_PROGERR_Msk /*!< CPU2 Programming error */ +#define FLASH_C2SR_WRPERR_Pos (4U) +#define FLASH_C2SR_WRPERR_Msk (0x1UL << FLASH_C2SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_C2SR_WRPERR FLASH_C2SR_WRPERR_Msk /*!< CPU2 Write protection error */ +#define FLASH_C2SR_PGAERR_Pos (5U) +#define FLASH_C2SR_PGAERR_Msk (0x1UL << FLASH_C2SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_C2SR_PGAERR FLASH_C2SR_PGAERR_Msk /*!< CPU2 Programming alignment error */ +#define FLASH_C2SR_SIZERR_Pos (6U) +#define FLASH_C2SR_SIZERR_Msk (0x1UL << FLASH_C2SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_C2SR_SIZERR FLASH_C2SR_SIZERR_Msk /*!< CPU2 Size error */ +#define FLASH_C2SR_PGSERR_Pos (7U) +#define FLASH_C2SR_PGSERR_Msk (0x1UL << FLASH_C2SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_C2SR_PGSERR FLASH_C2SR_PGSERR_Msk /*!< CPU2 Programming sequence error */ +#define FLASH_C2SR_MISERR_Pos (8U) +#define FLASH_C2SR_MISERR_Msk (0x1UL << FLASH_C2SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_C2SR_MISERR FLASH_C2SR_MISERR_Msk /*!< CPU2 Fast programming data miss error */ +#define FLASH_C2SR_FASTERR_Pos (9U) +#define FLASH_C2SR_FASTERR_Msk (0x1UL << FLASH_C2SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_C2SR_FASTERR FLASH_C2SR_FASTERR_Msk /*!< CPU2 Fast programming error */ +#define FLASH_C2SR_RDERR_Pos (14U) +#define FLASH_C2SR_RDERR_Msk (0x1UL << FLASH_C2SR_RDERR_Pos) /*!< 0x00004000 */ +#define FLASH_C2SR_RDERR FLASH_C2SR_RDERR_Msk /*!< CPU2 PCROP read error */ +#define FLASH_C2SR_BSY_Pos (16U) +#define FLASH_C2SR_BSY_Msk (0x1UL << FLASH_C2SR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_C2SR_BSY FLASH_C2SR_BSY_Msk /*!< CPU2 Flash busy */ +#define FLASH_C2SR_CFGBSY_Pos (18U) +#define FLASH_C2SR_CFGBSY_Msk (0x1UL << FLASH_C2SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_C2SR_CFGBSY FLASH_C2SR_CFGBSY_Msk /*!< CPU2 Programming or erase configuration busy */ +#define FLASH_C2SR_PESD_Pos (19U) +#define FLASH_C2SR_PESD_Msk (0x1UL << FLASH_C2SR_PESD_Pos) /*!< 0x00080000 */ +#define FLASH_C2SR_PESD FLASH_C2SR_PESD_Msk /*!< CPU2 Programming/erase operation suspended */ + +/****************** Bits definition for FLASH_C2CR register ************/ +#define FLASH_C2CR_PG_Pos (0U) +#define FLASH_C2CR_PG_Msk (0x1UL << FLASH_C2CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_C2CR_PG FLASH_C2CR_PG_Msk /*!< CPU2 Flash programming */ +#define FLASH_C2CR_PER_Pos (1U) +#define FLASH_C2CR_PER_Msk (0x1UL << FLASH_C2CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_C2CR_PER FLASH_C2CR_PER_Msk /*!< CPU2 Page erase */ +#define FLASH_C2CR_MER_Pos (2U) +#define FLASH_C2CR_MER_Msk (0x1UL << FLASH_C2CR_MER_Pos) /*!< 0x00000004 */ +#define FLASH_C2CR_MER FLASH_C2CR_MER_Msk /*!< CPU2 Mass erase */ +#define FLASH_C2CR_PNB_Pos (3U) +#define FLASH_C2CR_PNB_Msk (0x7FUL << FLASH_C2CR_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_C2CR_PNB FLASH_C2CR_PNB_Msk /*!< CPU2 Page number selection mask */ +#define FLASH_C2CR_STRT_Pos (16U) +#define FLASH_C2CR_STRT_Msk (0x1UL << FLASH_C2CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_C2CR_STRT FLASH_C2CR_STRT_Msk /*!< CPU2 Start an erase operation */ +#define FLASH_C2CR_FSTPG_Pos (18U) +#define FLASH_C2CR_FSTPG_Msk (0x1UL << FLASH_C2CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_C2CR_FSTPG FLASH_C2CR_FSTPG_Msk /*!< CPU2 Fast programming */ +#define FLASH_C2CR_EOPIE_Pos (24U) +#define FLASH_C2CR_EOPIE_Msk (0x1UL << FLASH_C2CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_C2CR_EOPIE FLASH_C2CR_EOPIE_Msk /*!< CPU2 End of operation interrupt enable */ +#define FLASH_C2CR_ERRIE_Pos (25U) +#define FLASH_C2CR_ERRIE_Msk (0x1UL << FLASH_C2CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_C2CR_ERRIE FLASH_C2CR_ERRIE_Msk /*!< CPU2 Error interrupt enable */ +#define FLASH_C2CR_RDERRIE_Pos (26U) +#define FLASH_C2CR_RDERRIE_Msk (0x1UL << FLASH_C2CR_RDERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_C2CR_RDERRIE FLASH_C2CR_RDERRIE_Msk /*!< CPU2 PCROP read error interrupt enable */ + +/******************************************************************************/ +/* */ +/* General Purpose I/O */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + +/******************************************************************************/ +/* */ +/* HSEM HW Semaphore */ +/* */ +/******************************************************************************/ +/******************** Bit definition for HSEM_R register ********************/ +#define HSEM_R_PROCID_Pos (0U) +#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */ +#define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32wb5mxx + * @{ + */ + +#ifndef __STM32WB5Mxx_H +#define __STM32WB5Mxx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 1U /*!< Core Revision r0p1 */ +#define __MPU_PRESENT 1U /*!< M4 provides an MPU */ +#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 4U /*!< STM32WBxx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32wb5mxx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +/*!< Interrupt Number Definition for M4 */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< Cortex-M4 System Tick Interrupt */ + +/************* STM32WBxx specific Interrupt Numbers on M4 core ************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD and PVM detector */ + TAMP_STAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Interrupt */ + FLASH_IRQn = 4, /*!< FLASH (CFI) global Interrupt */ + RCC_IRQn = 5, /*!< RCC Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line 0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line 1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line 2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line 3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line 4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 Interrupt */ + USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ + USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt (including USB wakeup) */ + C2SEV_PWR_C2H_IRQn = 21, /*!< CPU2 SEV Interrupt */ + COMP_IRQn = 22, /*!< COMP1 and COMP2 Interrupts */ + EXTI9_5_IRQn = 23, /*!< EXTI Lines [9:5] Interrupt */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 global Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Communication and TIM17 global Interrupts */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 Global Interrupt */ + PKA_IRQn = 29, /*!< PKA Interrupt */ + I2C1_EV_IRQn = 30, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 31, /*!< I2C1 Error Interrupt */ + I2C3_EV_IRQn = 32, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 33, /*!< I2C3 Error Interrupt */ + SPI1_IRQn = 34, /*!< SPI1 Interrupt */ + SPI2_IRQn = 35, /*!< SPI2 Interrupt */ + USART1_IRQn = 36, /*!< USART1 Interrupt */ + LPUART1_IRQn = 37, /*!< LPUART1 Interrupt */ + SAI1_IRQn = 38, /*!< SAI1 A and B global interrupt */ + TSC_IRQn = 39, /*!< TSC Interrupt */ + EXTI15_10_IRQn = 40, /*!< EXTI Lines1[15:10 ]Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarms (A and B) Interrupt */ + CRS_IRQn = 42, /*!< CRS interrupt */ + PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQn = 43, /*!< PWR switching on the fly interrupt + PWR end of BLE activity interrupt + PWR end of 802.15.4 (Zigbee) activity interrupt + PWR end of critical radio phase interrupt */ + IPCC_C1_RX_IRQn = 44, /*!< IPCC RX Occupied Interrupt */ + IPCC_C1_TX_IRQn = 45, /*!< IPCC TX Free Interrupt */ + HSEM_IRQn = 46, /*!< HSEM Interrupt */ + LPTIM1_IRQn = 47, /*!< LPTIM1 Interrupt */ + LPTIM2_IRQn = 48, /*!< LPTIM2 Interrupt */ + LCD_IRQn = 49, /*!< LCD Interrupt */ + QUADSPI_IRQn = 50, /*!< QUADSPI Interrupt */ + AES1_IRQn = 51, /*!< AES1 Interrupt */ + AES2_IRQn = 52, /*!< AES2 Interrupt */ + RNG_IRQn = 53, /*!< RNG Interrupt */ + FPU_IRQn = 54, /*!< FPU Interrupt */ + DMA2_Channel1_IRQn = 55, /*!< DMA2 Channel 1 Interrupt */ + DMA2_Channel2_IRQn = 56, /*!< DMA2 Channel 2 Interrupt */ + DMA2_Channel3_IRQn = 57, /*!< DMA2 Channel 3 Interrupt */ + DMA2_Channel4_IRQn = 58, /*!< DMA2 Channel 4 Interrupt */ + DMA2_Channel5_IRQn = 59, /*!< DMA2 Channel 5 Interrupt */ + DMA2_Channel6_IRQn = 60, /*!< DMA2 Channel 6 Interrupt */ + DMA2_Channel7_IRQn = 61, /*!< DMA2 Channel 7 Interrupt */ + DMAMUX1_OVR_IRQn = 62 /*!< DMAMUX1 overrun Interrupt */ +} IRQn_Type; +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32wbxx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */ +} ADC_Common_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x08-0x38 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x3C */ + __IO uint32_t C2APB1FZR1; /*!< Debug MCU CPU2 APB1 freeze register, Address offset: 0x40 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x44 */ + __IO uint32_t C2APB1FZR2; /*!< Debug MCU CPU2 APB1 freeze register, Address offset: 0x48 */ + __IO uint32_t APB2FZR; /*!< Debug MCU CPU1 APB2 freeze register, Address offset: 0x4C */ + __IO uint32_t C2APB2FZR; /*!< Debug MCU CPU2 APB2 freeze register, Address offset: 0x50 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register 0x00 */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register 0x04 */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register 0x08 */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register 0x0C */ + uint32_t RESERVED; /*!< Reserved, 0x10 */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access control register, Address offset: 0x00 */ + __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank 1 PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank 1 PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank 1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank 1 WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank 1 PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank 1 PCROP area B End address register, Address offset: 0x38 */ + __IO uint32_t IPCCBR; /*!< FLASH IPCC data buffer address, Address offset: 0x3C */ + uint32_t RESERVED2[7]; /*!< Reserved, Address offset: 0x40-0x58 */ + __IO uint32_t C2ACR; /*!< FLASH Core MO+ Access Control Register , Address offset: 0x5C */ + __IO uint32_t C2SR; /*!< FLASH Core MO+ Status Register, Address offset: 0x60 */ + __IO uint32_t C2CR; /*!< FLASH Core MO+ Control register, Address offset: 0x64 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x68-0x7C */ + __IO uint32_t SFR; /*!< FLASH secure start address, Address offset: 0x80 */ + __IO uint32_t SRRVR; /*!< FlASH secure SRAM2 start addr and CPU2 reset vector Address offset: 0x84 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Reset Register, Address offset: 0x18 */ + __IO uint32_t CR5; /*!< PWR Power Control Register 5, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< PWR Pull-Up Control Register of port E, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< PWR Pull-Down Control Register of port E, Address offset: 0x44 */ + uint32_t RESERVED0[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t PUCRH; /*!< PWR Pull-Up Control Register of port H, Address offset: 0x58 */ + __IO uint32_t PDCRH; /*!< PWR Pull-Down Control Register of port H, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, Address offset: 0x60-0x7C */ + __IO uint32_t C2CR1; /*!< PWR Power Control Register 1 for CPU2, Address offset: 0x80 */ + __IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset: 0x84 */ + __IO uint32_t EXTSCR; /*!< PWR Power Status Reset Register for CPU2, Address offset: 0x88 */ +} PWR_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ + __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration Register, Address offset: 0x10 */ +uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t SMPSCR; /*!< RCC SMPS step-down converter control register, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 & AHB4 peripheral reset register, Address offset: 0x30 */ +uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable register, Address offset: 0x50 */ +uint32_t RESERVED2; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ +uint32_t RESERVED3; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ +uint32_t RESERVED4; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ +uint32_t RESERVED5; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Clock Configuration Independent Register, Address offset: 0x88 */ +uint32_t RESERVED6; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC Control and Status Register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x98 */ + __IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */ +uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */ + __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */ +uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ + __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */ + __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */ + __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */ +uint32_t RESERVED9; /*!< Reserved, Address offset: 0x154 */ + __IO uint32_t C2APB1ENR1; /*!< RCC APB1 peripheral CPU2 clocks enable register 1, Address offset: 0x158 */ + __IO uint32_t C2APB1ENR2; /*!< RCC APB1 peripheral CPU2 clocks enable register 2, Address offset: 0x15C */ + __IO uint32_t C2APB2ENR; /*!< RCC APB2 peripheral CPU2 clocks enable register 1, Address offset: 0x160 */ + __IO uint32_t C2APB3ENR; /*!< RCC APB3 peripheral CPU2 clocks enable register 1, Address offset: 0x164 */ + __IO uint32_t C2AHB1SMENR; /*!< RCC AHB1 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x168 */ + __IO uint32_t C2AHB2SMENR; /*!< RCC AHB2 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x16C */ + __IO uint32_t C2AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x170 */ +uint32_t RESERVED10; /*!< Reserved, */ + __IO uint32_t C2APB1SMENR1; /*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 1, Address offset: 0x178 */ + __IO uint32_t C2APB1SMENR2; /*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 2, Address offset: 0x17C */ + __IO uint32_t C2APB2SMENR; /*!< RCC APB2 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x180 */ + __IO uint32_t C2APB3SMENR; /*!< RCC APB3 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x184 */ +} RCC_TypeDef; + + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + + + + +/** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR1; /*!< SYSCFG SRAM2 write protection register part 1, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ + __IO uint32_t SWPR2; /*!< SYSCFG write protection register part 2, Address offset: 0x28 */ + uint32_t RESERVED1[53]; /*!< Reserved, Address offset: 0x2C-0xFC */ + __IO uint32_t IMR1; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 1, Address offset: 0x100 */ + __IO uint32_t IMR2; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 2, Address offset: 0x104 */ + __IO uint32_t C2IMR1; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 1, Address offset: 0x108 */ + __IO uint32_t C2IMR2; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 2, Address offset: 0x10C */ + __IO uint32_t SIPCR; /*!< SYSCFG secure IP control register, Address offset: 0x110 */ + +} SYSCFG_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ +} AES_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */ +} TSC_TypeDef; + +/** + * @brief LCD + */ +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Inter-Processor Communication + */ +typedef struct +{ + __IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, Address offset: 0x000 */ + __IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, Address offset: 0x004 */ + __IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, Address offset: 0x008 */ + __IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status register, Address offset: 0x00C */ + __IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, Address offset: 0x010 */ + __IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, Address offset: 0x014 */ + __IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, Address offset: 0x018 */ + __IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status register, Address offset: 0x01C */ +} IPCC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x000 */ + __IO uint32_t MR; /*!< Mask register, Address offset: 0x004 */ + __IO uint32_t SCR; /*!< Status set clear register, Address offset: 0x008 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x00C */ +} IPCC_CommonTypeDef; + +/** + * @brief Async Interrupts and Events Controller + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI software interrupt event register [31:0], Address offset: 0x08 */ + __IO uint32_t PR1; /*!< EXTI pending register [31:0], Address offset: 0x0C */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x10 - 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI software interrupt event register [31:0], Address offset: 0x28 */ + __IO uint32_t PR2; /*!< EXTI pending register [31:0], Address offset: 0x2C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, Address offset: 0x30 - 0x3C */ + __IO uint32_t RESERVED3[8]; /*!< Reserved, Address offset: 0x40 - 0x5C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, Address offset: 0x60 - 0x7C */ + __IO uint32_t IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED8[10]; /*!< Reserved, Address offset: 0x98 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ +}EXTI_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Public Key Accelerator (PKA) + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved1[253]; /*!< Reserved Address offset: 0x000C-0x03FC*/ + __IO uint32_t RAM[894]; /*!< PKA RAM, Address offset: 0x0400-0x11F4 */ +} PKA_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ +typedef struct +{ + __IO uint32_t R[32]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RLR[32]; /*!< HSEM 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IER; /*!< HSEM CPU1 interrupt enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM CPU1 interrupt clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM CPU1 interrupt status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM CPU1 masked interrupt status register , Address offset: 10Ch */ + __IO uint32_t C2IER; /*!< HSEM CPU2 interrupt enable register , Address offset: 110h */ + __IO uint32_t C2ICR; /*!< HSEM CPU2 interrupt clear register , Address offset: 114h */ + __IO uint32_t C2ISR; /*!< HSEM CPU2 interrupt status register , Address offset: 118h */ + __IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 11Ch */ + uint32_t Reserved[8]; /*!< Reserved Address offset: 120h-13Ch*/ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +/*!< Boundary memory map */ +#define FLASH_BASE (0x08000000UL)/*!< FLASH(up to 1 MB) base address */ +#define SRAM_BASE (0x20000000UL)/*!< SRAM(up to 256 KB) base address */ +#define PERIPH_BASE (0x40000000UL)/*!< Peripheral base address */ + +/*!< Memory, OTP and Option bytes */ + +/* Base addresses */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 0x1FFF8FFF) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ + +#define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 192 KB) base address */ +#define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ +#define SRAM2B_BASE (SRAM_BASE + 0x00038000UL)/*!< SRAM2B(32 KB) base address */ + +/* Memory Size */ +#define FLASH_SIZE (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x07FFUL)) << 10U) +#define SRAM1_SIZE 0x00030000UL /*!< SRAM1 default size : 192 kB */ +#define SRAM2A_SIZE 0x00008000UL /*!< SRAM2a default size : 32 kB */ +#define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */ + +/* End addresses */ +#define SRAM1_END_ADDR (0x2002FFFFUL) /*!< SRAM1 : 192KB (0x20000000 0x2002FFFF) */ +#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 0x20037FFF) */ +#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 0x2003FFFF) */ + +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) +#define AHB4PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define APB3PERIPH_BASE (PERIPH_BASE + 0x20000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x50000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) +#define LCD_BASE (APB1PERIPH_BASE + 0x00002400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x00005C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x00006000UL) +#define USB1_BASE (APB1PERIPH_BASE + 0x00006800UL) +#define USB1_PMAADDR (APB1PERIPH_BASE + 0x00006C00UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x00007C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x00008000UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x00009400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x00000030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x00000200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x00000204UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x00005400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0000004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0000024UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x00000800UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL) +#define TSC_BASE (AHB1PERIPH_BASE + 0x00004000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x0000006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x00000080UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x00000020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x00000024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x00000028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0000002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x00000030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x00000034UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) + +/*!< AHB2 peripherals */ +#define IOPORT_BASE (AHB2PERIPH_BASE + 0x00000000UL) +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) +#define GPIOE_BASE (IOPORT_BASE + 0x00001000UL) +#define GPIOH_BASE (IOPORT_BASE + 0x00001C00UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) + +#define AES1_BASE (AHB2PERIPH_BASE + 0x08060000UL) + +/*!< AHB Shared peripherals */ +#define RCC_BASE (AHB4PERIPH_BASE + 0x00000000UL) +#define PWR_BASE (AHB4PERIPH_BASE + 0x00000400UL) +#define EXTI_BASE (AHB4PERIPH_BASE + 0x00000800UL) +#define IPCC_BASE (AHB4PERIPH_BASE + 0x00000C00UL) +#define RNG_BASE (AHB4PERIPH_BASE + 0x00001000UL) +#define HSEM_BASE (AHB4PERIPH_BASE + 0x00001400UL) +#define AES2_BASE (AHB4PERIPH_BASE + 0x00001800UL) +#define PKA_BASE (AHB4PERIPH_BASE + 0x00002000UL) +#define FLASH_REG_BASE (AHB4PERIPH_BASE + 0x00004000UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + + +/*!< AHB3 peripherals */ +#define QUADSPI_BASE (AHB3PERIPH_BASE + 0x00000000UL) /*!< QUADSPI memories accessible over AHB base address */ +#define QUADSPI_R_BASE (AHB3PERIPH_BASE + 0x10001000UL) /*!< QUADSPI control registers base address */ + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE ((uint32_t)0x1FFF7500UL) /*!< Package data register base address */ +#define UID64_BASE ((uint32_t)0x1FFF7580UL) /*!< 64-bit Unique device Identification */ +#define UID_BASE ((uint32_t)0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0UL) /*!< Flash size data register base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +/* Peripherals available on APB1 bus */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define LCD ((LCD_TypeDef *) LCD_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define USB ((USB_TypeDef *) USB1_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) + +/* Peripherals available on APB2 bus */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) + +/* Peripherals available on AHB1 bus */ +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define TSC ((TSC_TypeDef *) TSC_BASE) + +/* Peripherals available on AHB2 bus */ +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) + +#define AES1 ((AES_TypeDef *) AES1_BASE) + +/* Peripherals available on AHB shared bus */ +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define IPCC ((IPCC_TypeDef *) IPCC_BASE) +#define IPCC_C1 ((IPCC_CommonTypeDef *) IPCC_BASE) +#define IPCC_C2 ((IPCC_CommonTypeDef *) (IPCC_BASE + 0x10U)) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100U)) +#define AES2 ((AES_TypeDef *) AES2_BASE) +#define PKA ((PKA_TypeDef *) PKA_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_REG_BASE) + +/* Peripherals available on AHB3 bus */ +#define QUADSPI ((QUADSPI_TypeDef *) QUADSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_ALIGN_Pos (5U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR_EXTSEL_Pos (6U) +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ + +#define ADC_JSQR_JEXTEN_Pos (6U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ + +#define ADC_JSQR_JSQ1_Pos (8U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ + +#define ADC_JSQR_JSQ2_Pos (14U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (20U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ + +#define ADC_JSQR_JSQ4_Pos (26U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ +#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ +#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ +#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ +#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003A0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00000100 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00000200 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00000400 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/* Legacy defines */ +#define ADC_CCR_MULTI (ADC_CCR_DUAL) +#define ADC_CCR_MULTI_0 (ADC_CCR_DUAL_0) +#define ADC_CCR_MULTI_1 (ADC_CCR_DUAL_1) +#define ADC_CCR_MULTI_2 (ADC_CCR_DUAL_2) +#define ADC_CCR_MULTI_3 (ADC_CCR_DUAL_3) +#define ADC_CCR_MULTI_4 (ADC_CCR_DUAL_4) + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ***************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ +#define COMP_CSR_PWRMODE_Pos (2U) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */ +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0x7UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INPSEL_Pos (7U) +#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000180 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */ +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_WINMODE_Pos (9U) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_BLANKING_Pos (18U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */ +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */ +#define COMP_CSR_INMESEL_Pos (25U) +#define COMP_CSR_INMESEL_Msk (0x3UL << COMP_CSR_INMESEL_Pos) /*!< 0x06000000 */ +#define COMP_CSR_INMESEL COMP_CSR_INMESEL_Msk /*!< Comparator input minus extended selection */ +#define COMP_CSR_INMESEL_0 (0x1UL << COMP_CSR_INMESEL_Pos) /*!< 0x02000000 */ +#define COMP_CSR_INMESEL_1 (0x2UL << COMP_CSR_INMESEL_Pos) /*!< 0x04000000 */ +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1U << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2U << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ + +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1U << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2U << AES_CR_MODE_Pos) /*!< 0x00000010 */ + +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001U << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002U << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800U << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ + +#define AES_CR_CCFC_Pos (7U) +#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */ +#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ +#define AES_CR_ERRC_Pos (8U) +#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */ +#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ +#define AES_CR_CCFIE_Pos (9U) +#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */ +#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */ +#define AES_CR_ERRIE_Pos (10U) +#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ +#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ + +#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1U << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2U << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ + +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ + +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in last payload block */ +#define AES_CR_NPBLB_0 (0x1U << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2U << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4U << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8U << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0U) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0U) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0U) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0U) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0U) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* DMAMUX Controller */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DMAMUX_CxCR register **************/ +#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) +#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */ +#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ +#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ +#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ +#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ +#define DMAMUX_CxCR_SOIE_Pos (8U) +#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ +#define DMAMUX_CxCR_EGE_Pos (9U) +#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ +#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ +#define DMAMUX_CxCR_SE_Pos (16U) +#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ +#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ +#define DMAMUX_CxCR_SPOL_Pos (17U) +#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ +#define DMAMUX_CxCR_SPOL_0 (0x1U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_CxCR_SPOL_1 (0x2U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_CxCR_NBREQ_Pos (19U) +#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ +#define DMAMUX_CxCR_NBREQ_0 (0x01U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_CxCR_NBREQ_1 (0x02U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_CxCR_NBREQ_2 (0x04U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_CxCR_NBREQ_3 (0x08U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_CxCR_NBREQ_4 (0x10U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ +#define DMAMUX_CxCR_SYNC_ID_Pos (24U) +#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ +#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ +#define DMAMUX_CxCR_SYNC_ID_0 (0x01U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ +#define DMAMUX_CxCR_SYNC_ID_1 (0x02U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ +#define DMAMUX_CxCR_SYNC_ID_2 (0x04U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ +#define DMAMUX_CxCR_SYNC_ID_3 (0x08U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ +#define DMAMUX_CxCR_SYNC_ID_4 (0x10U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ + +/******************* Bits definition for DMAMUX_CSR register **************/ +#define DMAMUX_CSR_SOF0_Pos (0U) +#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ +#define DMAMUX_CSR_SOF1_Pos (1U) +#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ +#define DMAMUX_CSR_SOF2_Pos (2U) +#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ +#define DMAMUX_CSR_SOF3_Pos (3U) +#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */ +#define DMAMUX_CSR_SOF4_Pos (4U) +#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */ +#define DMAMUX_CSR_SOF5_Pos (5U) +#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */ +#define DMAMUX_CSR_SOF6_Pos (6U) +#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */ +#define DMAMUX_CSR_SOF7_Pos (7U) +#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */ +#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Synchronization Overrun Flag 7 */ +#define DMAMUX_CSR_SOF8_Pos (8U) +#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */ +#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Synchronization Overrun Flag 8 */ +#define DMAMUX_CSR_SOF9_Pos (9U) +#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */ +#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Synchronization Overrun Flag 9 */ +#define DMAMUX_CSR_SOF10_Pos (10U) +#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */ +#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Synchronization Overrun Flag 10 */ +#define DMAMUX_CSR_SOF11_Pos (11U) +#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */ +#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Synchronization Overrun Flag 11 */ +#define DMAMUX_CSR_SOF12_Pos (12U) +#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */ +#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Synchronization Overrun Flag 12 */ +#define DMAMUX_CSR_SOF13_Pos (13U) +#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */ +#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Synchronization Overrun Flag 13 */ + +/******************** Bits definition for DMAMUX_CFR register **************/ +#define DMAMUX_CFR_CSOF0_Pos (0U) +#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ +#define DMAMUX_CFR_CSOF1_Pos (1U) +#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ +#define DMAMUX_CFR_CSOF2_Pos (2U) +#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ +#define DMAMUX_CFR_CSOF3_Pos (3U) +#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */ +#define DMAMUX_CFR_CSOF4_Pos (4U) +#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */ +#define DMAMUX_CFR_CSOF5_Pos (5U) +#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */ +#define DMAMUX_CFR_CSOF6_Pos (6U) +#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */ +#define DMAMUX_CFR_CSOF7_Pos (7U) +#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */ +#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Clear Overrun Flag 7 */ +#define DMAMUX_CFR_CSOF8_Pos (8U) +#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */ +#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Clear Overrun Flag 8 */ +#define DMAMUX_CFR_CSOF9_Pos (9U) +#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */ +#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Clear Overrun Flag 9 */ +#define DMAMUX_CFR_CSOF10_Pos (10U) +#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */ +#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Clear Overrun Flag 10 */ +#define DMAMUX_CFR_CSOF11_Pos (11U) +#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */ +#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Clear Overrun Flag 11 */ +#define DMAMUX_CFR_CSOF12_Pos (12U) +#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */ +#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Clear Overrun Flag 12 */ +#define DMAMUX_CFR_CSOF13_Pos (13U) +#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */ +#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Clear Overrun Flag 13 */ + +/******************** Bits definition for DMAMUX_RGxCR register ************/ +#define DMAMUX_RGxCR_SIG_ID_Pos (0U) +#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ +#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ +#define DMAMUX_RGxCR_SIG_ID_0 (0x01U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGxCR_SIG_ID_1 (0x02U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGxCR_SIG_ID_2 (0x04U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGxCR_SIG_ID_3 (0x08U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGxCR_SIG_ID_4 (0x10U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_RGxCR_OIE_Pos (8U) +#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ +#define DMAMUX_RGxCR_GE_Pos (16U) +#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ +#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ +#define DMAMUX_RGxCR_GPOL_Pos (17U) +#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ +#define DMAMUX_RGxCR_GPOL_0 (0x1U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_RGxCR_GPOL_1 (0x2U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_RGxCR_GNBREQ_Pos (19U) +#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ +#define DMAMUX_RGxCR_GNBREQ_0 (0x01U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_RGxCR_GNBREQ_1 (0x02U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_RGxCR_GNBREQ_2 (0x04U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_RGxCR_GNBREQ_3 (0x08U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_RGxCR_GNBREQ_4 (0x10U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for DMAMUX_RGSR register **************/ +#define DMAMUX_RGSR_OF0_Pos (0U) +#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ +#define DMAMUX_RGSR_OF1_Pos (1U) +#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ +#define DMAMUX_RGSR_OF2_Pos (2U) +#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ +#define DMAMUX_RGSR_OF3_Pos (3U) +#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ + +/******************** Bits definition for DMAMUX_RGCFR register **************/ +#define DMAMUX_RGCFR_COF0_Pos (0U) +#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ +#define DMAMUX_RGCFR_COF1_Pos (1U) +#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ +#define DMAMUX_RGCFR_COF2_Pos (2U) +#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ +#define DMAMUX_RGCFR_COF3_Pos (3U) +#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT_Pos (0U) +#define EXTI_RTSR1_RT_Msk (0x803FFFFFUL << EXTI_RTSR1_RT_Pos) /*!< 0x803FFFFF */ +#define EXTI_RTSR1_RT EXTI_RTSR1_RT_Msk /*!< Rising trigger event configuration bit */ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR1_RT17_Pos (17U) +#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR1_RT18_Pos (18U) +#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR1_RT19_Pos (19U) +#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */ +#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_RTSR1_RT20_Pos (20U) +#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */ +#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ +#define EXTI_RTSR1_RT21_Pos (21U) +#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */ +#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ +#define EXTI_RTSR1_RT31_Pos (31U) +#define EXTI_RTSR1_RT31_Msk (0x1UL << EXTI_RTSR1_RT31_Pos) /*!< 0x80000000 */ +#define EXTI_RTSR1_RT31 EXTI_RTSR1_RT31_Msk /*!< Rising trigger event configuration bit of line 31 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT_Pos (0U) +#define EXTI_FTSR1_FT_Msk (0x803FFFFFUL << EXTI_FTSR1_FT_Pos) /*!< 0x803FFFFF */ +#define EXTI_FTSR1_FT EXTI_FTSR1_FT_Msk /*!< Falling trigger event configuration bit */ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR1_FT17_Pos (17U) +#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR1_FT18_Pos (18U) +#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR1_FT19_Pos (19U) +#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */ +#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_FTSR1_FT20_Pos (20U) +#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */ +#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ +#define EXTI_FTSR1_FT21_Pos (21U) +#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */ +#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ +#define EXTI_FTSR1_FT31_Pos (31U) +#define EXTI_FTSR1_FT31_Msk (0x1UL << EXTI_FTSR1_FT31_Pos) /*!< 0x80000000 */ +#define EXTI_FTSR1_FT31 EXTI_FTSR1_FT31_Msk /*!< Falling trigger event configuration bit of line 31 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI_Pos (0U) +#define EXTI_SWIER1_SWI_Msk (0x803FFFFFUL << EXTI_SWIER1_SWI_Pos) /*!< 0x803FFFFF */ +#define EXTI_SWIER1_SWI EXTI_SWIER1_SWI_Msk /*!< Software interrupt */ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER1_SWI17_Pos (17U) +#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER1_SWI18_Pos (18U) +#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER1_SWI19_Pos (19U) +#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */ +#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */ +#define EXTI_SWIER1_SWI20_Pos (20U) +#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */ +#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */ +#define EXTI_SWIER1_SWI21_Pos (21U) +#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */ +#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */ +#define EXTI_SWIER1_SWI31_Pos (31U) +#define EXTI_SWIER1_SWI31_Msk (0x1UL << EXTI_SWIER1_SWI31_Pos) /*!< 0x80000000 */ +#define EXTI_SWIER1_SWI31 EXTI_SWIER1_SWI31_Msk /*!< Software Interrupt on line 31 */ + +/******************* Bit definition for EXTI_PR1 register *******************/ +#define EXTI_PR1_PIF_Pos (0U) +#define EXTI_PR1_PIF_Msk (0x803FFFFFUL << EXTI_PR1_PIF_Pos) /*!< 0x803FFFFF */ +#define EXTI_PR1_PIF EXTI_PR1_PIF_Msk /*!< Pending bit */ +#define EXTI_PR1_PIF0_Pos (0U) +#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */ +#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */ +#define EXTI_PR1_PIF1_Pos (1U) +#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */ +#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */ +#define EXTI_PR1_PIF2_Pos (2U) +#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */ +#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */ +#define EXTI_PR1_PIF3_Pos (3U) +#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */ +#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */ +#define EXTI_PR1_PIF4_Pos (4U) +#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */ +#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */ +#define EXTI_PR1_PIF5_Pos (5U) +#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */ +#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */ +#define EXTI_PR1_PIF6_Pos (6U) +#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */ +#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */ +#define EXTI_PR1_PIF7_Pos (7U) +#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */ +#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */ +#define EXTI_PR1_PIF8_Pos (8U) +#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */ +#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */ +#define EXTI_PR1_PIF9_Pos (9U) +#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */ +#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */ +#define EXTI_PR1_PIF10_Pos (10U) +#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */ +#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */ +#define EXTI_PR1_PIF11_Pos (11U) +#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */ +#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */ +#define EXTI_PR1_PIF12_Pos (12U) +#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */ +#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */ +#define EXTI_PR1_PIF13_Pos (13U) +#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */ +#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */ +#define EXTI_PR1_PIF14_Pos (14U) +#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */ +#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */ +#define EXTI_PR1_PIF15_Pos (15U) +#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */ +#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */ +#define EXTI_PR1_PIF16_Pos (16U) +#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */ +#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */ +#define EXTI_PR1_PIF17_Pos (17U) +#define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos) /*!< 0x00020000 */ +#define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk /*!< Pending bit for line 17 */ +#define EXTI_PR1_PIF18_Pos (18U) +#define EXTI_PR1_PIF18_Msk (0x1UL << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */ +#define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */ +#define EXTI_PR1_PIF19_Pos (19U) +#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */ +#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */ +#define EXTI_PR1_PIF20_Pos (20U) +#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */ +#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */ +#define EXTI_PR1_PIF21_Pos (21U) +#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */ +#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */ +#define EXTI_PR1_PIF31_Pos (31U) +#define EXTI_PR1_PIF31_Msk (0x1UL << EXTI_PR1_PIF31_Pos) /*!< 0x80000000 */ +#define EXTI_PR1_PIF31 EXTI_PR1_PIF31_Msk /*!< Pending bit for line 31 */ + +/****************** Bit definition for EXTI_RTSR2 register ******************/ +#define EXTI_RTSR2_RT_Pos (0U) +#define EXTI_RTSR2_RT_Msk (0x302UL << EXTI_RTSR2_RT_Pos) /*!< 0x00000302 */ +#define EXTI_RTSR2_RT EXTI_RTSR2_RT_Msk /*!< Rising trigger event configuration bit */ +#define EXTI_RTSR2_RT33_Pos (1U) +#define EXTI_RTSR2_RT33_Msk (0x1UL << EXTI_RTSR2_RT33_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR2_RT33 EXTI_RTSR2_RT33_Msk /*!< Rising trigger event configuration bit of line 33 */ +#define EXTI_RTSR2_RT40_Pos (8U) +#define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger event configuration bit of line 40 */ +#define EXTI_RTSR2_RT41_Pos (9U) +#define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger event configuration bit of line 41 */ + +/****************** Bit definition for EXTI_FTSR2 register ******************/ +#define EXTI_FTSR2_FT_Pos (0U) +#define EXTI_FTSR2_FT_Msk (0x302UL << EXTI_FTSR2_FT_Pos) /*!< 0x00000302 */ +#define EXTI_FTSR2_FT EXTI_FTSR2_FT_Msk /*!< Falling trigger event configuration bit */ +#define EXTI_FTSR2_FT33_Pos (1U) +#define EXTI_FTSR2_FT33_Msk (0x1UL << EXTI_FTSR2_FT33_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR2_FT33 EXTI_FTSR2_FT33_Msk /*!< Falling trigger event configuration bit of line 33 */ +#define EXTI_FTSR2_FT40_Pos (8U) +#define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger event configuration bit of line 40 */ +#define EXTI_FTSR2_FT41_Pos (9U) +#define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger event configuration bit of line 41 */ + +/****************** Bit definition for EXTI_SWIER2 register *****************/ +#define EXTI_SWIER2_SWI_Pos (0U) +#define EXTI_SWIER2_SWI_Msk (0x302UL << EXTI_SWIER2_SWI_Pos) /*!< 0x00000302 */ +#define EXTI_SWIER2_SWI EXTI_SWIER2_SWI_Msk /*!< Falling trigger event configuration bit */ +#define EXTI_SWIER2_SWI33_Pos (1U) +#define EXTI_SWIER2_SWI33_Msk (0x1UL << EXTI_SWIER2_SWI33_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWI33_Msk /*!< Software Interrupt on line 33 */ +#define EXTI_SWIER2_SWI40_Pos (8U) +#define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */ +#define EXTI_SWIER2_SWI41_Pos (9U) +#define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */ + +/******************* Bit definition for EXTI_PR2 register *******************/ +#define EXTI_PR2_PIF_Pos (0U) +#define EXTI_PR2_PIF_Msk (0x302UL << EXTI_PR2_PIF_Pos) /*!< 0x00000302 */ +#define EXTI_PR2_PIF EXTI_PR2_PIF_Msk /*!< Pending bit */ +#define EXTI_PR2_PIF33_Pos (1U) +#define EXTI_PR2_PIF33_Msk (0x1UL << EXTI_PR2_PIF33_Pos) /*!< 0x00000002 */ +#define EXTI_PR2_PIF33 EXTI_PR2_PIF33_Msk /*!< Pending bit for line 33 */ +#define EXTI_PR2_PIF40_Pos (8U) +#define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos) /*!< 0x00000100 */ +#define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk /*!< Pending bit for line 40 */ +#define EXTI_PR2_PIF41_Pos (9U) +#define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos) /*!< 0x00000200 */ +#define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk /*!< Pending bit for line 41 */ + +/******************** Bits definition for EXTI_IMR1 register ****************/ +#define EXTI_IMR1_Pos (0U) +#define EXTI_IMR1_Msk (0xFFFFFFFFUL << EXTI_IMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_IMR1_IM EXTI_IMR1_Msk /*!< CPU1 wakeup with interrupt Mask on Event */ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< CPU1 Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< CPU1 Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< CPU1 Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< CPU1 Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< CPU1 Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< CPU1 Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< CPU1 Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< CPU1 Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< CPU1 Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< CPU1 Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< CPU1 Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< CPU1 Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< CPU1 Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< CPU1 Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< CPU1 Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< CPU1 Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< CPU1 Interrupt Mask on line 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< CPU1 Interrupt Mask on line 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< CPU1 Interrupt Mask on line 18 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< CPU1 Interrupt Mask on line 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< CPU1 Interrupt Mask on line 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< CPU1 Interrupt Mask on line 21 */ +#define EXTI_IMR1_IM22_Pos (22U) +#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< CPU1 Interrupt Mask on line 22 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< CPU1 Interrupt Mask on line 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< CPU1 Interrupt Mask on line 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU1 Interrupt Mask on line 25 */ +#define EXTI_IMR1_IM28_Pos (28U) +#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU1 Interrupt Mask on line 28 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< CPU1 Interrupt Mask on line 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< CPU1 Interrupt Mask on line 30 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< CPU1 Interrupt Mask on line 31 */ + +/******************** Bits definition for EXTI_EMR1 register ****************/ +#define EXTI_EMR1_Pos (0U) +#define EXTI_EMR1_Msk (0x003EFFFFUL << EXTI_EMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_EMR1_EM EXTI_EMR1_Msk /*!< CPU1 Event Mask */ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< CPU1 Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< CPU1 Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< CPU1 Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< CPU1 Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< CPU1 Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< CPU1 Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< CPU1 Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< CPU1 Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< CPU1 Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< CPU1 Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< CPU1 Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< CPU1 Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< CPU1 Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< CPU1 Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< CPU1 Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< CPU1 Event Mask on line 15 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< CPU1 Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< CPU1 Event Mask on line 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< CPU1 Event Mask on line 19 */ +#define EXTI_EMR1_EM20_Pos (20U) +#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< CPU1 Event Mask on line 20 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< CPU1 Event Mask on line 21 */ + +/******************** Bits definition for EXTI_IMR2 register ****************/ +#define EXTI_IMR2_Pos (0U) +#define EXTI_IMR2_Msk (0x0001FFFFUL << EXTI_IMR2_Pos) /*!< 0x0001FFFF */ +#define EXTI_IMR2_IM EXTI_IMR2_Msk /*!< CPU1 Interrupt Mask */ +#define EXTI_IMR2_IM33_Pos (1U) +#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU1 Interrupt Mask on line 33 */ +#define EXTI_IMR2_IM36_Pos (4U) +#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */ +#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< CPU1 Interrupt Mask on line 36 */ +#define EXTI_IMR2_IM37_Pos (5U) +#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */ +#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< CPU1 Interrupt Mask on line 37 */ +#define EXTI_IMR2_IM38_Pos (6U) +#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */ +#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< CPU1 Interrupt Mask on line 38 */ +#define EXTI_IMR2_IM39_Pos (7U) +#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */ +#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< CPU1 Interrupt Mask on line 39 */ +#define EXTI_IMR2_IM40_Pos (8U) +#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */ +#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< CPU1 Interrupt Mask on line 40 */ +#define EXTI_IMR2_IM41_Pos (9U) +#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */ +#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< CPU1 Interrupt Mask on line 41 */ +#define EXTI_IMR2_IM42_Pos (10U) +#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */ +#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< CPU1 Interrupt Mask on line 42 */ +#define EXTI_IMR2_IM43_Pos (11U) +#define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos) /*!< 0x00000800 */ +#define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk /*!< CPU1 Interrupt Mask on line 43 */ +#define EXTI_IMR2_IM44_Pos (12U) +#define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */ +#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< CPU1 Interrupt Mask on line 44 */ +#define EXTI_IMR2_IM45_Pos (13U) +#define EXTI_IMR2_IM45_Msk (0x1UL << EXTI_IMR2_IM45_Pos) /*!< 0x00002000 */ +#define EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk /*!< CPU1 Interrupt Mask on line 45 */ +#define EXTI_IMR2_IM46_Pos (14U) +#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */ +#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< CPU1 Interrupt Mask on line 46 */ +#define EXTI_IMR2_IM48_Pos (16U) +#define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */ +#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< CPU1 Interrupt Mask on line 48 */ + +/******************** Bits definition for EXTI_EMR2 register ****************/ +#define EXTI_EMR2_Pos (0U) +#define EXTI_EMR2_Msk (0x00000300UL << EXTI_EMR2_Pos) /*!< 0x000003000 */ +#define EXTI_EMR2_EM EXTI_EMR2_Msk /*!< CPU1 Interrupt Mask */ +#define EXTI_EMR2_EM40_Pos (8U) +#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */ +#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< CPU1 Event Mask on line 40 */ +#define EXTI_EMR2_EM41_Pos (9U) +#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */ +#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< CPU1 Event Mask on line 41 */ + +/******************** Bits definition for EXTI_C2IMR1 register **************/ +#define EXTI_C2IMR1_Pos (0U) +#define EXTI_C2IMR1_Msk (0xFFFFFFFFUL << EXTI_C2IMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_C2IMR1_IM EXTI_C2IMR1_Msk /*!< CPU2 wakeup with interrupt Mask on Event */ +#define EXTI_C2IMR1_IM0_Pos (0U) +#define EXTI_C2IMR1_IM0_Msk (0x1UL << EXTI_C2IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_C2IMR1_IM0 EXTI_C2IMR1_IM0_Msk /*!< CPU2 Interrupt Mask on line 0 */ +#define EXTI_C2IMR1_IM1_Pos (1U) +#define EXTI_C2IMR1_IM1_Msk (0x1UL << EXTI_C2IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_C2IMR1_IM1 EXTI_C2IMR1_IM1_Msk /*!< CPU2 Interrupt Mask on line 1 */ +#define EXTI_C2IMR1_IM2_Pos (2U) +#define EXTI_C2IMR1_IM2_Msk (0x1UL << EXTI_C2IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_C2IMR1_IM2 EXTI_C2IMR1_IM2_Msk /*!< CPU2 Interrupt Mask on line 2 */ +#define EXTI_C2IMR1_IM3_Pos (3U) +#define EXTI_C2IMR1_IM3_Msk (0x1UL << EXTI_C2IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_C2IMR1_IM3 EXTI_C2IMR1_IM3_Msk /*!< CPU2 Interrupt Mask on line 3 */ +#define EXTI_C2IMR1_IM4_Pos (4U) +#define EXTI_C2IMR1_IM4_Msk (0x1UL << EXTI_C2IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_C2IMR1_IM4 EXTI_C2IMR1_IM4_Msk /*!< CPU2 Interrupt Mask on line 4 */ +#define EXTI_C2IMR1_IM5_Pos (5U) +#define EXTI_C2IMR1_IM5_Msk (0x1UL << EXTI_C2IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_C2IMR1_IM5 EXTI_C2IMR1_IM5_Msk /*!< CPU2 Interrupt Mask on line 5 */ +#define EXTI_C2IMR1_IM6_Pos (6U) +#define EXTI_C2IMR1_IM6_Msk (0x1UL << EXTI_C2IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_C2IMR1_IM6 EXTI_C2IMR1_IM6_Msk /*!< CPU2 Interrupt Mask on line 6 */ +#define EXTI_C2IMR1_IM7_Pos (7U) +#define EXTI_C2IMR1_IM7_Msk (0x1UL << EXTI_C2IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_C2IMR1_IM7 EXTI_C2IMR1_IM7_Msk /*!< CPU2 Interrupt Mask on line 7 */ +#define EXTI_C2IMR1_IM8_Pos (8U) +#define EXTI_C2IMR1_IM8_Msk (0x1UL << EXTI_C2IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_C2IMR1_IM8 EXTI_C2IMR1_IM8_Msk /*!< CPU2 Interrupt Mask on line 8 */ +#define EXTI_C2IMR1_IM9_Pos (9U) +#define EXTI_C2IMR1_IM9_Msk (0x1UL << EXTI_C2IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_C2IMR1_IM9 EXTI_C2IMR1_IM9_Msk /*!< CPU2 Interrupt Mask on line 9 */ +#define EXTI_C2IMR1_IM10_Pos (10U) +#define EXTI_C2IMR1_IM10_Msk (0x1UL << EXTI_C2IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_C2IMR1_IM10 EXTI_C2IMR1_IM10_Msk /*!< CPU2 Interrupt Mask on line 10 */ +#define EXTI_C2IMR1_IM11_Pos (11U) +#define EXTI_C2IMR1_IM11_Msk (0x1UL << EXTI_C2IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_C2IMR1_IM11 EXTI_C2IMR1_IM11_Msk /*!< CPU2 Interrupt Mask on line 11 */ +#define EXTI_C2IMR1_IM12_Pos (12U) +#define EXTI_C2IMR1_IM12_Msk (0x1UL << EXTI_C2IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_C2IMR1_IM12 EXTI_C2IMR1_IM12_Msk /*!< CPU2 Interrupt Mask on line 12 */ +#define EXTI_C2IMR1_IM13_Pos (13U) +#define EXTI_C2IMR1_IM13_Msk (0x1UL << EXTI_C2IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_C2IMR1_IM13 EXTI_C2IMR1_IM13_Msk /*!< CPU2 Interrupt Mask on line 13 */ +#define EXTI_C2IMR1_IM14_Pos (14U) +#define EXTI_C2IMR1_IM14_Msk (0x1UL << EXTI_C2IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_C2IMR1_IM14 EXTI_C2IMR1_IM14_Msk /*!< CPU2 Interrupt Mask on line 14 */ +#define EXTI_C2IMR1_IM15_Pos (15U) +#define EXTI_C2IMR1_IM15_Msk (0x1UL << EXTI_C2IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_C2IMR1_IM15 EXTI_C2IMR1_IM15_Msk /*!< CPU2 Interrupt Mask on line 15 */ +#define EXTI_C2IMR1_IM16_Pos (16U) +#define EXTI_C2IMR1_IM16_Msk (0x1UL << EXTI_C2IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_C2IMR1_IM16 EXTI_C2IMR1_IM16_Msk /*!< CPU2 Interrupt Mask on line 16 */ +#define EXTI_C2IMR1_IM17_Pos (17U) +#define EXTI_C2IMR1_IM17_Msk (0x1UL << EXTI_C2IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_C2IMR1_IM17 EXTI_C2IMR1_IM17_Msk /*!< CPU2 Interrupt Mask on line 17 */ +#define EXTI_C2IMR1_IM18_Pos (18U) +#define EXTI_C2IMR1_IM18_Msk (0x1UL << EXTI_C2IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_C2IMR1_IM18 EXTI_C2IMR1_IM18_Msk /*!< CPU2 Interrupt Mask on line 18 */ +#define EXTI_C2IMR1_IM19_Pos (19U) +#define EXTI_C2IMR1_IM19_Msk (0x1UL << EXTI_C2IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_C2IMR1_IM19 EXTI_C2IMR1_IM19_Msk /*!< CPU2 Interrupt Mask on line 19 */ +#define EXTI_C2IMR1_IM20_Pos (20U) +#define EXTI_C2IMR1_IM20_Msk (0x1UL << EXTI_C2IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_C2IMR1_IM20 EXTI_C2IMR1_IM20_Msk /*!< CPU2 Interrupt Mask on line 20 */ +#define EXTI_C2IMR1_IM21_Pos (21U) +#define EXTI_C2IMR1_IM21_Msk (0x1UL << EXTI_C2IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_C2IMR1_IM21 EXTI_C2IMR1_IM21_Msk /*!< CPU2 Interrupt Mask on line 21 */ +#define EXTI_C2IMR1_IM22_Pos (22U) +#define EXTI_C2IMR1_IM22_Msk (0x1UL << EXTI_C2IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_C2IMR1_IM22 EXTI_C2IMR1_IM22_Msk /*!< CPU2 Interrupt Mask on line 22 */ +#define EXTI_C2IMR1_IM23_Pos (23U) +#define EXTI_C2IMR1_IM23_Msk (0x1UL << EXTI_C2IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_C2IMR1_IM23 EXTI_C2IMR1_IM23_Msk /*!< CPU2 Interrupt Mask on line 23 */ +#define EXTI_C2IMR1_IM24_Pos (24U) +#define EXTI_C2IMR1_IM24_Msk (0x1UL << EXTI_C2IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_C2IMR1_IM24 EXTI_C2IMR1_IM24_Msk /*!< CPU2 Interrupt Mask on line 24 */ +#define EXTI_C2IMR1_IM25_Pos (25U) +#define EXTI_C2IMR1_IM25_Msk (0x1UL << EXTI_C2IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_C2IMR1_IM25 EXTI_C2IMR1_IM25_Msk /*!< CPU2 Interrupt Mask on line 25 */ +#define EXTI_C2IMR1_IM28_Pos (28U) +#define EXTI_C2IMR1_IM28_Msk (0x1UL << EXTI_C2IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_C2IMR1_IM28 EXTI_C2IMR1_IM28_Msk /*!< CPU2 Interrupt Mask on line 28 */ +#define EXTI_C2IMR1_IM29_Pos (29U) +#define EXTI_C2IMR1_IM29_Msk (0x1UL << EXTI_C2IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_C2IMR1_IM29 EXTI_C2IMR1_IM29_Msk /*!< CPU2 Interrupt Mask on line 29 */ +#define EXTI_C2IMR1_IM30_Pos (30U) +#define EXTI_C2IMR1_IM30_Msk (0x1UL << EXTI_C2IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_C2IMR1_IM30 EXTI_C2IMR1_IM30_Msk /*!< CPU2 Interrupt Mask on line 30 */ +#define EXTI_C2IMR1_IM31_Pos (31U) +#define EXTI_C2IMR1_IM31_Msk (0x1UL << EXTI_C2IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_C2IMR1_IM31 EXTI_C2IMR1_IM31_Msk /*!< CPU2 Interrupt Mask on line 31 */ +/******************** Bits definition for EXTI_C2EMR1 register **************/ +#define EXTI_C2EMR1_Pos (0U) +#define EXTI_C2EMR1_Msk (0x003EFFFFUL << EXTI_C2EMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_C2EMR1_EM EXTI_C2EMR1_Msk /*!< CPU2 Event Mask */ +#define EXTI_C2EMR1_EM0_Pos (0U) +#define EXTI_C2EMR1_EM0_Msk (0x1UL << EXTI_C2EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_C2EMR1_EM0 EXTI_C2EMR1_EM0_Msk /*!< CPU2 Event Mask on line 0 */ +#define EXTI_C2EMR1_EM1_Pos (1U) +#define EXTI_C2EMR1_EM1_Msk (0x1UL << EXTI_C2EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_C2EMR1_EM1 EXTI_C2EMR1_EM1_Msk /*!< CPU2 Event Mask on line 1 */ +#define EXTI_C2EMR1_EM2_Pos (2U) +#define EXTI_C2EMR1_EM2_Msk (0x1UL << EXTI_C2EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_C2EMR1_EM2 EXTI_C2EMR1_EM2_Msk /*!< CPU2 Event Mask on line 2 */ +#define EXTI_C2EMR1_EM3_Pos (3U) +#define EXTI_C2EMR1_EM3_Msk (0x1UL << EXTI_C2EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_C2EMR1_EM3 EXTI_C2EMR1_EM3_Msk /*!< CPU2 Event Mask on line 3 */ +#define EXTI_C2EMR1_EM4_Pos (4U) +#define EXTI_C2EMR1_EM4_Msk (0x1UL << EXTI_C2EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_C2EMR1_EM4 EXTI_C2EMR1_EM4_Msk /*!< CPU2 Event Mask on line 4 */ +#define EXTI_C2EMR1_EM5_Pos (5U) +#define EXTI_C2EMR1_EM5_Msk (0x1UL << EXTI_C2EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_C2EMR1_EM5 EXTI_C2EMR1_EM5_Msk /*!< CPU2 Event Mask on line 5 */ +#define EXTI_C2EMR1_EM6_Pos (6U) +#define EXTI_C2EMR1_EM6_Msk (0x1UL << EXTI_C2EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_C2EMR1_EM6 EXTI_C2EMR1_EM6_Msk /*!< CPU2 Event Mask on line 6 */ +#define EXTI_C2EMR1_EM7_Pos (7U) +#define EXTI_C2EMR1_EM7_Msk (0x1UL << EXTI_C2EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_C2EMR1_EM7 EXTI_C2EMR1_EM7_Msk /*!< CPU2 Event Mask on line 7 */ +#define EXTI_C2EMR1_EM8_Pos (8U) +#define EXTI_C2EMR1_EM8_Msk (0x1UL << EXTI_C2EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_C2EMR1_EM8 EXTI_C2EMR1_EM8_Msk /*!< CPU2 Event Mask on line 8 */ +#define EXTI_C2EMR1_EM9_Pos (9U) +#define EXTI_C2EMR1_EM9_Msk (0x1UL << EXTI_C2EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_C2EMR1_EM9 EXTI_C2EMR1_EM9_Msk /*!< CPU2 Event Mask on line 9 */ +#define EXTI_C2EMR1_EM10_Pos (10U) +#define EXTI_C2EMR1_EM10_Msk (0x1UL << EXTI_C2EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_C2EMR1_EM10 EXTI_C2EMR1_EM10_Msk /*!< CPU2 Event Mask on line 10 */ +#define EXTI_C2EMR1_EM11_Pos (11U) +#define EXTI_C2EMR1_EM11_Msk (0x1UL << EXTI_C2EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_C2EMR1_EM11 EXTI_C2EMR1_EM11_Msk /*!< CPU2 Event Mask on line 11 */ +#define EXTI_C2EMR1_EM12_Pos (12U) +#define EXTI_C2EMR1_EM12_Msk (0x1UL << EXTI_C2EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_C2EMR1_EM12 EXTI_C2EMR1_EM12_Msk /*!< CPU2 Event Mask on line 12 */ +#define EXTI_C2EMR1_EM13_Pos (13U) +#define EXTI_C2EMR1_EM13_Msk (0x1UL << EXTI_C2EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_C2EMR1_EM13 EXTI_C2EMR1_EM13_Msk /*!< CPU2 Event Mask on line 13 */ +#define EXTI_C2EMR1_EM14_Pos (14U) +#define EXTI_C2EMR1_EM14_Msk (0x1UL << EXTI_C2EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_C2EMR1_EM14 EXTI_C2EMR1_EM14_Msk /*!< CPU2 Event Mask on line 14 */ +#define EXTI_C2EMR1_EM15_Pos (15U) +#define EXTI_C2EMR1_EM15_Msk (0x1UL << EXTI_C2EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_C2EMR1_EM15 EXTI_C2EMR1_EM15_Msk /*!< CPU2 Event Mask on line 15 */ +#define EXTI_C2EMR1_EM17_Pos (17U) +#define EXTI_C2EMR1_EM17_Msk (0x1UL << EXTI_C2EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_C2EMR1_EM17 EXTI_C2EMR1_EM17_Msk /*!< CPU2 Event Mask on line 17 */ +#define EXTI_C2EMR1_EM18_Pos (18U) +#define EXTI_C2EMR1_EM18_Msk (0x1UL << EXTI_C2EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_C2EMR1_EM18 EXTI_C2EMR1_EM18_Msk /*!< CPU2 Event Mask on line 18 */ +#define EXTI_C2EMR1_EM19_Pos (19U) +#define EXTI_C2EMR1_EM19_Msk (0x1UL << EXTI_C2EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_C2EMR1_EM19 EXTI_C2EMR1_EM19_Msk /*!< CPU2 Event Mask on line 19 */ +#define EXTI_C2EMR1_EM20_Pos (20U) +#define EXTI_C2EMR1_EM20_Msk (0x1UL << EXTI_C2EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_C2EMR1_EM20 EXTI_C2EMR1_EM20_Msk /*!< CPU2 Event Mask on line 20 */ +#define EXTI_C2EMR1_EM21_Pos (21U) +#define EXTI_C2EMR1_EM21_Msk (0x1UL << EXTI_C2EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_C2EMR1_EM21 EXTI_C2EMR1_EM21_Msk /*!< CPU2 Event Mask on line 21 */ + +/******************** Bits definition for EXTI_C2IMR2 register **************/ +#define EXTI_C2IMR2_Pos (0U) +#define EXTI_C2IMR2_Msk (0x0001FFFFUL << EXTI_C2IMR2_Pos) /*!< 0x0001FFFF */ +#define EXTI_C2IMR2_IM EXTI_C2IMR2_Msk /*!< CPU2 Interrupt Mask */ +#define EXTI_C2IMR2_IM33_Pos (1U) +#define EXTI_C2IMR2_IM33_Msk (0x1UL << EXTI_C2IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_C2IMR2_IM33 EXTI_C2IMR2_IM33_Msk /*!< CPU2 Interrupt Mask on line 33 */ +#define EXTI_C2IMR2_IM36_Pos (4U) +#define EXTI_C2IMR2_IM36_Msk (0x1UL << EXTI_C2IMR2_IM36_Pos) /*!< 0x00000010 */ +#define EXTI_C2IMR2_IM36 EXTI_C2IMR2_IM36_Msk /*!< CPU2 Interrupt Mask on line 36 */ +#define EXTI_C2IMR2_IM37_Pos (5U) +#define EXTI_C2IMR2_IM37_Msk (0x1UL << EXTI_C2IMR2_IM37_Pos) /*!< 0x00000020 */ +#define EXTI_C2IMR2_IM37 EXTI_C2IMR2_IM37_Msk /*!< CPU2 Interrupt Mask on line 37 */ +#define EXTI_C2IMR2_IM38_Pos (6U) +#define EXTI_C2IMR2_IM38_Msk (0x1UL << EXTI_C2IMR2_IM38_Pos) /*!< 0x00000040 */ +#define EXTI_C2IMR2_IM38 EXTI_C2IMR2_IM38_Msk /*!< CPU2 Interrupt Mask on line 38 */ +#define EXTI_C2IMR2_IM39_Pos (7U) +#define EXTI_C2IMR2_IM39_Msk (0x1UL << EXTI_C2IMR2_IM39_Pos) /*!< 0x00000080 */ +#define EXTI_C2IMR2_IM39 EXTI_C2IMR2_IM39_Msk /*!< CPU2 Interrupt Mask on line 39 */ +#define EXTI_C2IMR2_IM40_Pos (8U) +#define EXTI_C2IMR2_IM40_Msk (0x1UL << EXTI_C2IMR2_IM40_Pos) /*!< 0x00000100 */ +#define EXTI_C2IMR2_IM40 EXTI_C2IMR2_IM40_Msk /*!< CPU2 Interrupt Mask on line 40 */ +#define EXTI_C2IMR2_IM41_Pos (9U) +#define EXTI_C2IMR2_IM41_Msk (0x1UL << EXTI_C2IMR2_IM41_Pos) /*!< 0x00000200 */ +#define EXTI_C2IMR2_IM41 EXTI_C2IMR2_IM41_Msk /*!< CPU2 Interrupt Mask on line 41 */ +#define EXTI_C2IMR2_IM42_Pos (10U) +#define EXTI_C2IMR2_IM42_Msk (0x1UL << EXTI_C2IMR2_IM42_Pos) /*!< 0x00000400 */ +#define EXTI_C2IMR2_IM42 EXTI_C2IMR2_IM42_Msk /*!< CPU2 Interrupt Mask on line 42 */ +#define EXTI_C2IMR2_IM43_Pos (11U) +#define EXTI_C2IMR2_IM43_Msk (0x1UL << EXTI_C2IMR2_IM43_Pos) /*!< 0x00000800 */ +#define EXTI_C2IMR2_IM43 EXTI_C2IMR2_IM43_Msk /*!< CPU2 Interrupt Mask on line 43 */ +#define EXTI_C2IMR2_IM44_Pos (12U) +#define EXTI_C2IMR2_IM44_Msk (0x1UL << EXTI_C2IMR2_IM44_Pos) /*!< 0x00001000 */ +#define EXTI_C2IMR2_IM44 EXTI_C2IMR2_IM44_Msk /*!< CPU2 Interrupt Mask on line 44 */ +#define EXTI_C2IMR2_IM45_Pos (13U) +#define EXTI_C2IMR2_IM45_Msk (0x1UL << EXTI_C2IMR2_IM45_Pos) /*!< 0x00002000 */ +#define EXTI_C2IMR2_IM45 EXTI_C2IMR2_IM45_Msk /*!< CPU2 Interrupt Mask on line 45 */ +#define EXTI_C2IMR2_IM46_Pos (14U) +#define EXTI_C2IMR2_IM46_Msk (0x1UL << EXTI_C2IMR2_IM46_Pos) /*!< 0x00004000 */ +#define EXTI_C2IMR2_IM46 EXTI_C2IMR2_IM46_Msk /*!< CPU2 Interrupt Mask on line 46 */ +#define EXTI_C2IMR2_IM48_Pos (16U) +#define EXTI_C2IMR2_IM48_Msk (0x1UL << EXTI_C2IMR2_IM48_Pos) /*!< 0x00010000 */ +#define EXTI_C2IMR2_IM48 EXTI_C2IMR2_IM48_Msk /*!< CPU2 Interrupt Mask on line 48 */ + +/******************** Bits definition for EXTI_C2EMR2 register **************/ +#define EXTI_C2EMR2_Pos (8U) +#define EXTI_C2EMR2_Msk (0x00000300UL << EXTI_C2EMR2_Pos) /*!< 0x000003000 */ +#define EXTI_C2EMR2_EM EXTI_C2EMR2_Msk /*!< CPU2 Interrupt Mask */ +#define EXTI_C2EMR2_EM40_Pos (8U) +#define EXTI_C2EMR2_EM40_Msk (0x1UL << EXTI_C2EMR2_EM40_Pos) /*!< 0x00000100 */ +#define EXTI_C2EMR2_EM40 EXTI_C2EMR2_EM40_Msk /*!< CPU2 Event Mask on line 40 */ +#define EXTI_C2EMR2_EM41_Pos (9U) +#define EXTI_C2EMR2_EM41_Msk (0x1UL << EXTI_C2EMR2_EM41_Pos) /*!< 0x00000200 */ +#define EXTI_C2EMR2_EM41 EXTI_C2EMR2_EM41_Msk /*!< CPU2 Event Mask on line 41 */ + +/******************************************************************************/ +/* */ +/* Public Key Accelerator (PKA) */ +/* */ +/******************************************************************************/ + +/******************* Bits definition for PKA_CR register **************/ +#define PKA_CR_EN_Pos (0U) +#define PKA_CR_EN_Msk (0x1UL << PKA_CR_EN_Pos) /*!< 0x00000001 */ +#define PKA_CR_EN PKA_CR_EN_Msk /*!< PKA enable */ +#define PKA_CR_START_Pos (1U) +#define PKA_CR_START_Msk (0x1UL << PKA_CR_START_Pos) /*!< 0x00000002 */ +#define PKA_CR_START PKA_CR_START_Msk /*!< Start operation */ +#define PKA_CR_MODE_Pos (8U) +#define PKA_CR_MODE_Msk (0x3FUL << PKA_CR_MODE_Pos) /*!< 0x00003F00 */ +#define PKA_CR_MODE PKA_CR_MODE_Msk /*!< MODE[5:0] PKA operation code */ +#define PKA_CR_MODE_0 (0x01U << PKA_CR_MODE_Pos) /*!< 0x00000100 */ +#define PKA_CR_MODE_1 (0x02U << PKA_CR_MODE_Pos) /*!< 0x00000200 */ +#define PKA_CR_MODE_2 (0x04U << PKA_CR_MODE_Pos) /*!< 0x00000400 */ +#define PKA_CR_MODE_3 (0x08U << PKA_CR_MODE_Pos) /*!< 0x00000800 */ +#define PKA_CR_MODE_4 (0x10U << PKA_CR_MODE_Pos) /*!< 0x00001000 */ +#define PKA_CR_MODE_5 (0x20U << PKA_CR_MODE_Pos) /*!< 0x00002000 */ +#define PKA_CR_PROCENDIE_Pos (17U) +#define PKA_CR_PROCENDIE_Msk (0x1UL << PKA_CR_PROCENDIE_Pos) /*!< 0x00020000 */ +#define PKA_CR_PROCENDIE PKA_CR_PROCENDIE_Msk /*!< End of operation interrupt enable */ +#define PKA_CR_RAMERRIE_Pos (19U) +#define PKA_CR_RAMERRIE_Msk (0x1UL << PKA_CR_RAMERRIE_Pos) /*!< 0x00080000 */ +#define PKA_CR_RAMERRIE PKA_CR_RAMERRIE_Msk /*!< RAM error interrupt enable */ +#define PKA_CR_ADDRERRIE_Pos (20U) +#define PKA_CR_ADDRERRIE_Msk (0x1UL << PKA_CR_ADDRERRIE_Pos) /*!< 0x00100000 */ +#define PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE_Msk /*!< RAM error interrupt enable */ + +/******************* Bits definition for PKA_SR register **************/ +#define PKA_SR_BUSY_Pos (16U) +#define PKA_SR_BUSY_Msk (0x1UL << PKA_SR_BUSY_Pos) /*!< 0x00010000 */ +#define PKA_SR_BUSY PKA_SR_BUSY_Msk /*!< PKA operation is in progress */ +#define PKA_SR_PROCENDF_Pos (17U) +#define PKA_SR_PROCENDF_Msk (0x1UL << PKA_SR_PROCENDF_Pos) /*!< 0x00020000 */ +#define PKA_SR_PROCENDF PKA_SR_PROCENDF_Msk /*!< PKA end of operation flag */ +#define PKA_SR_RAMERRF_Pos (19U) +#define PKA_SR_RAMERRF_Msk (0x1UL << PKA_SR_RAMERRF_Pos) /*!< 0x00080000 */ +#define PKA_SR_RAMERRF PKA_SR_RAMERRF_Msk /*!< PKA RAM error flag */ +#define PKA_SR_ADDRERRF_Pos (20U) +#define PKA_SR_ADDRERRF_Msk (0x1UL << PKA_SR_ADDRERRF_Pos) /*!< 0x00100000 */ +#define PKA_SR_ADDRERRF PKA_SR_ADDRERRF_Msk /*!< Address error flag */ + +/******************* Bits definition for PKA_CLRFR register **************/ +#define PKA_CLRFR_PROCENDFC_Pos (17U) +#define PKA_CLRFR_PROCENDFC_Msk (0x1UL << PKA_CLRFR_PROCENDFC_Pos) /*!< 0x00020000 */ +#define PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC_Msk /*!< Clear PKA end of operation flag */ +#define PKA_CLRFR_RAMERRFC_Pos (19U) +#define PKA_CLRFR_RAMERRFC_Msk (0x1UL << PKA_CLRFR_RAMERRFC_Pos) /*!< 0x00080000 */ +#define PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC_Msk /*!< Clear PKA RAM error flag */ +#define PKA_CLRFR_ADDRERRFC_Pos (20U) +#define PKA_CLRFR_ADDRERRFC_Msk (0x1UL << PKA_CLRFR_ADDRERRFC_Pos) /*!< 0x00100000 */ +#define PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC_Msk /*!< Clear address error flag */ + +/******************* Bits definition for PKA RAM *************************/ +#define PKA_RAM_OFFSET 0x400U /*!< PKA RAM address offset */ + +/* Compute Montgomery parameter input data */ +#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1 ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 1 */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 2 */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 3 */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1 ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Output last double X1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output last double Y1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1 ((0xE90U - PKA_RAM_OFFSET)>>2) /*!< Output last double Z1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2 ((0xEE4U - PKA_RAM_OFFSET)>>2) /*!< Output check point X2 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2 ((0xF38U - PKA_RAM_OFFSET)>>2) /*!< Output check point Y2 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2 ((0xF8CU - PKA_RAM_OFFSET)>>2) /*!< Output check point Z2 coordinate */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x7FCU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0xE94U - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0xEE8U - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x700U - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x754U - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x103CU - PKA_RAM_OFFSET)>>2) /*!< Output final point kP X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1090U - PKA_RAM_OFFSET)>>2) /*!< Output final point kP Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x45CU - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x4B8U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x5E8U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x63CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0xF40U - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0xF94U - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x1098U - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0xFE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x65CU - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x7ECU - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x97CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0xEECU - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic substraction input data */ +#define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic substraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular substraction input data */ +#define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular substraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_ICEN_Pos (9U) +#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk /*!< Instruction cache enable */ +#define FLASH_ACR_DCEN_Pos (10U) +#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */ +#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk /*!< Data cache enable */ +#define FLASH_ACR_ICRST_Pos (11U) +#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk /*!< Instruction cache reset */ +#define FLASH_ACR_DCRST_Pos (12U) +#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk /*!< Data cache reset */ +#define FLASH_ACR_PES_Pos (15U) +#define FLASH_ACR_PES_Msk (0x1UL << FLASH_ACR_PES_Pos) /*!< 0x00008000 */ +#define FLASH_ACR_PES FLASH_ACR_PES_Msk /*!< Program/erase suspend request */ +#define FLASH_ACR_EMPTY_Pos (16U) +#define FLASH_ACR_EMPTY_Msk (0x1UL << FLASH_ACR_EMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_EMPTY FLASH_ACR_EMPTY_Msk /*!< Flash use area empty */ + +#define FLASH_ACR_LATENCY_0WS (0x0UL << FLASH_ACR_LATENCY_Pos) /*!< FLASH Zero wait state */ +#define FLASH_ACR_LATENCY_1WS (FLASH_ACR_LATENCY_0 << FLASH_ACR_LATENCY_Pos) /*!< FLASH One wait state */ +#define FLASH_ACR_LATENCY_2WS (FLASH_ACR_LATENCY_1 << FLASH_ACR_LATENCY_Pos) /*!< FLASH Two wait states */ +#define FLASH_ACR_LATENCY_3WS ((FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) << FLASH_ACR_LATENCY_Pos) /*!< FLASH Three wait states */ + +/******************* Bits definition for FLASH_SR register ******************/ +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of Operation */ +#define FLASH_SR_OPERR_Pos (1U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Operation error */ +#define FLASH_SR_PROGERR_Pos (3U) +#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk /*!< Programming error */ +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */ +#define FLASH_SR_PGAERR_Pos (5U) +#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming alignment error */ +#define FLASH_SR_SIZERR_Pos (6U) +#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ +#define FLASH_SR_PGSERR_Pos (7U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error */ +#define FLASH_SR_MISERR_Pos (8U) +#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk /*!< Fast programming data miss error */ +#define FLASH_SR_FASTERR_Pos (9U) +#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk /*!< Fast programming error */ +#define FLASH_SR_OPTNV_Pos (13U) +#define FLASH_SR_OPTNV_Msk (0x1UL << FLASH_SR_OPTNV_Pos) /*!< 0x00002000 */ +#define FLASH_SR_OPTNV FLASH_SR_OPTNV_Msk /*!< User option OPTVAL indication */ +#define FLASH_SR_RDERR_Pos (14U) +#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< PCROP read error */ +#define FLASH_SR_OPTVERR_Pos (15U) +#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option validity error */ +#define FLASH_SR_BSY_Pos (16U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Flash Busy */ +#define FLASH_SR_CFGBSY_Pos (18U) +#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk /*!< Programming or erase configuration busy */ +#define FLASH_SR_PESD_Pos (19U) +#define FLASH_SR_PESD_Msk (0x1UL << FLASH_SR_PESD_Pos) /*!< 0x00080000 */ +#define FLASH_SR_PESD FLASH_SR_PESD_Msk /*!< Programming/erase operation suspended */ + +/******************* Bits definition for FLASH_CR register ******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Flash programming */ +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page erase */ +#define FLASH_CR_MER_Pos (2U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ +#define FLASH_CR_PNB_Pos (3U) +#define FLASH_CR_PNB_Msk (0xFFUL << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk /*!< Page number selection mask */ +#define FLASH_CR_STRT_Pos (16U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start an erase operation */ +#define FLASH_CR_OPTSTRT_Pos (17U) +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk /*!< Options modification start */ +#define FLASH_CR_FSTPG_Pos (18U) +#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk /*!< Fast programming */ +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error interrupt enable */ +#define FLASH_CR_RDERRIE_Pos (26U) +#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk /*!< PCROP read error interrupt enable */ +#define FLASH_CR_OBL_LAUNCH_Pos (27U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_CR_OPTLOCK_Pos (30U) +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk /*!< Options lock */ +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Flash control register lock */ + +/******************* Bits definition for FLASH_ECCR register ****************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0001FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< double-word address ECC fail */ +#define FLASH_ECCR_SYSF_ECC_Pos (20U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System flash ECC fail */ +#define FLASH_ECCR_ECCCIE_Pos (24U) +#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_CPUID_Pos (26U) +#define FLASH_ECCR_CPUID_Msk (0x7UL << FLASH_ECCR_CPUID_Pos) /*!< 0x1C000000 */ +#define FLASH_ECCR_CPUID FLASH_ECCR_CPUID_Msk /*!< CPU identification */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPTR register ****************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Read protection level */ +#define FLASH_OPTR_ESE_Pos (8U) +#define FLASH_OPTR_ESE_Msk (0x1UL << FLASH_OPTR_ESE_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_ESE FLASH_OPTR_ESE_Msk /*!< Security enable */ +#define FLASH_OPTR_BOR_LEV_Pos (9U) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000E00 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset level mask */ +#define FLASH_OPTR_BOR_LEV_0 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000800 */ +#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< Reset option in Stop mode */ +#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< Reset option in Standby mode */ +#define FLASH_OPTR_nRST_SHDW_Pos (14U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< Reset option in Shutdown mode */ +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter option in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter option in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_nBOOT1_Pos (23U) +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk /*!< Boot Configuration */ +#define FLASH_OPTR_SRAM2PE_Pos (24U) +#define FLASH_OPTR_SRAM2PE_Msk (0x1UL << FLASH_OPTR_SRAM2PE_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2PE FLASH_OPTR_SRAM2PE_Msk /*!< SRAM2 parity check enable */ +#define FLASH_OPTR_SRAM2RST_Pos (25U) +#define FLASH_OPTR_SRAM2RST_Msk (0x1UL << FLASH_OPTR_SRAM2RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2RST FLASH_OPTR_SRAM2RST_Msk /*!< SRAM2 erase option when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< BOOT0 option bit */ +#define FLASH_OPTR_AGC_TRIM_Pos (29U) +#define FLASH_OPTR_AGC_TRIM_Msk (0x7UL << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0xE0000000 */ +#define FLASH_OPTR_AGC_TRIM FLASH_OPTR_AGC_TRIM_Msk /*!< Automatic Gain Control trimming mask */ +#define FLASH_OPTR_AGC_TRIM_0 (0x1U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_AGC_TRIM_1 (0x2U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_AGC_TRIM_2 (0x4U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for FLASH_PCROP1ASR register ************/ +#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U) +#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x1FFUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x000001FF */ +#define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk /*!< PCROP area A start offset */ + +/****************** Bits definition for FLASH_PCROP1AER register ************/ +#define FLASH_PCROP1AER_PCROP1A_END_Pos (0U) +#define FLASH_PCROP1AER_PCROP1A_END_Msk (0x1FFUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x000001FF */ +#define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk /*!< PCROP area A end offset */ +#define FLASH_PCROP1AER_PCROP_RDP_Pos (31U) +#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */ +#define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk /*!< PCROP area preserved when RDP level decreased */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk /*!< WRP area A start offset */ +#define FLASH_WRP1AR_WRP1A_END_Pos (16U) +#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk /*!< WRP area A end offset */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk /*!< WRP area B start offset */ +#define FLASH_WRP1BR_WRP1B_END_Pos (16U) +#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk /*!< WRP area B end offset */ + +/****************** Bits definition for FLASH_PCROP1BSR register ************/ +#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U) +#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x1FFUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x000001FF */ +#define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk /*!< PCROP area B start offset */ + +/****************** Bits definition for FLASH_PCROP1BER register ************/ +#define FLASH_PCROP1BER_PCROP1B_END_Pos (0U) +#define FLASH_PCROP1BER_PCROP1B_END_Msk (0x1FFUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x000001FF */ +#define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk /*!< PCROP area B end offset */ + +/****************** Bits definition for FLASH_IPCCBR register ************/ +#define FLASH_IPCCBR_IPCCDBA_Pos (0U) +#define FLASH_IPCCBR_IPCCDBA_Msk (0x3FFFUL << FLASH_IPCCBR_IPCCDBA_Pos) /*!< 0x00003FFF */ +#define FLASH_IPCCBR_IPCCDBA FLASH_IPCCBR_IPCCDBA_Msk /*!< IPCC data buffer base address */ + +/****************** Bits definition for FLASH_SFR register ************/ +#define FLASH_SFR_SFSA_Pos (0U) +#define FLASH_SFR_SFSA_Msk (0xFFUL << FLASH_SFR_SFSA_Pos) /*!< 0x000000FF */ +#define FLASH_SFR_SFSA FLASH_SFR_SFSA_Msk /* Secure flash start address */ +#define FLASH_SFR_FSD_Pos (8U) +#define FLASH_SFR_FSD_Msk (0x1UL << FLASH_SFR_FSD_Pos) /*!< 0x00000100 */ +#define FLASH_SFR_FSD FLASH_SFR_FSD_Msk /* Flash mode secure */ +#define FLASH_SFR_DDS_Pos (12U) +#define FLASH_SFR_DDS_Msk (0x1UL << FLASH_SFR_DDS_Pos) /*!< 0x00001000 */ +#define FLASH_SFR_DDS FLASH_SFR_DDS_Msk /* Enabling and disabling CPU2 Debug access */ + +/****************** Bits definition for FLASH_SRRVR register ************/ +#define FLASH_SRRVR_SBRV_Pos (0U) +#define FLASH_SRRVR_SBRV_Msk (0x3FFFFUL << FLASH_SRRVR_SBRV_Pos) /*!< 0x0003FFFF */ +#define FLASH_SRRVR_SBRV FLASH_SRRVR_SBRV_Msk /* SCPU2 boot reset vector memory offset */ + +#define FLASH_SRRVR_SBRSA_Pos (18U) +#define FLASH_SRRVR_SBRSA_Msk (0x1FUL << FLASH_SRRVR_SBRSA_Pos) /*!< 0x007C0000 */ +#define FLASH_SRRVR_SBRSA FLASH_SRRVR_SBRSA_Msk /* Secure backup SRAM2a start address */ +#define FLASH_SRRVR_BRSD_Pos (23U) +#define FLASH_SRRVR_BRSD_Msk (0x1UL << FLASH_SRRVR_BRSD_Pos) /*!< 0x00800000 */ +#define FLASH_SRRVR_BRSD FLASH_SRRVR_BRSD_Msk /* Backup SRAM2A secure mode */ + +#define FLASH_SRRVR_SNBRSA_Pos (25U) +#define FLASH_SRRVR_SNBRSA_Msk (0x1FUL << FLASH_SRRVR_SNBRSA_Pos) /*!< 0x3E000000 */ +#define FLASH_SRRVR_SNBRSA FLASH_SRRVR_SNBRSA_Msk /* Secure non-backup SRAM2b start address */ +#define FLASH_SRRVR_NBRSD_Pos (30U) +#define FLASH_SRRVR_NBRSD_Msk (0x1UL << FLASH_SRRVR_NBRSD_Pos) /*!< 0x40000000 */ +#define FLASH_SRRVR_NBRSD FLASH_SRRVR_NBRSD_Msk /* Non-backup SRAM2B secure mode */ +#define FLASH_SRRVR_C2OPT_Pos (31U) +#define FLASH_SRRVR_C2OPT_Msk (0x1UL << FLASH_SRRVR_C2OPT_Pos) /*!< 0x80000000 */ +#define FLASH_SRRVR_C2OPT FLASH_SRRVR_C2OPT_Msk /* SCPU2 boot reset vector memory selection */ + +/****************** Bits definition for FLASH_C2ACR register ************/ +#define FLASH_C2ACR_PRFTEN_Pos (8U) +#define FLASH_C2ACR_PRFTEN_Msk (0x1UL << FLASH_C2ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_C2ACR_PRFTEN FLASH_C2ACR_PRFTEN_Msk /*!< CPU2 Prefetch enable */ +#define FLASH_C2ACR_ICEN_Pos (9U) +#define FLASH_C2ACR_ICEN_Msk (0x1UL << FLASH_C2ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_C2ACR_ICEN FLASH_C2ACR_ICEN_Msk /*!< CPU2 Instruction cache enable */ +#define FLASH_C2ACR_ICRST_Pos (11U) +#define FLASH_C2ACR_ICRST_Msk (0x1UL << FLASH_C2ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_C2ACR_ICRST FLASH_C2ACR_ICRST_Msk /*!< CPU2 Instruction cache reset */ +#define FLASH_C2ACR_PES_Pos (15U) +#define FLASH_C2ACR_PES_Msk (0x1UL << FLASH_C2ACR_PES_Pos) /*!< 0x00008000 */ +#define FLASH_C2ACR_PES FLASH_C2ACR_PES_Msk /*!< CPU2 Program/erase suspend request */ + +/****************** Bits definition for FLASH_C2SR register ************/ +#define FLASH_C2SR_EOP_Pos (0U) +#define FLASH_C2SR_EOP_Msk (0x1UL << FLASH_C2SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_C2SR_EOP FLASH_C2SR_EOP_Msk /*!< CPU2 End of operation */ +#define FLASH_C2SR_OPERR_Pos (1U) +#define FLASH_C2SR_OPERR_Msk (0x1UL << FLASH_C2SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_C2SR_OPERR FLASH_C2SR_OPERR_Msk /*!< CPU2 Operation error */ +#define FLASH_C2SR_PROGERR_Pos (3U) +#define FLASH_C2SR_PROGERR_Msk (0x1UL << FLASH_C2SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_C2SR_PROGERR FLASH_C2SR_PROGERR_Msk /*!< CPU2 Programming error */ +#define FLASH_C2SR_WRPERR_Pos (4U) +#define FLASH_C2SR_WRPERR_Msk (0x1UL << FLASH_C2SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_C2SR_WRPERR FLASH_C2SR_WRPERR_Msk /*!< CPU2 Write protection error */ +#define FLASH_C2SR_PGAERR_Pos (5U) +#define FLASH_C2SR_PGAERR_Msk (0x1UL << FLASH_C2SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_C2SR_PGAERR FLASH_C2SR_PGAERR_Msk /*!< CPU2 Programming alignment error */ +#define FLASH_C2SR_SIZERR_Pos (6U) +#define FLASH_C2SR_SIZERR_Msk (0x1UL << FLASH_C2SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_C2SR_SIZERR FLASH_C2SR_SIZERR_Msk /*!< CPU2 Size error */ +#define FLASH_C2SR_PGSERR_Pos (7U) +#define FLASH_C2SR_PGSERR_Msk (0x1UL << FLASH_C2SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_C2SR_PGSERR FLASH_C2SR_PGSERR_Msk /*!< CPU2 Programming sequence error */ +#define FLASH_C2SR_MISERR_Pos (8U) +#define FLASH_C2SR_MISERR_Msk (0x1UL << FLASH_C2SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_C2SR_MISERR FLASH_C2SR_MISERR_Msk /*!< CPU2 Fast programming data miss error */ +#define FLASH_C2SR_FASTERR_Pos (9U) +#define FLASH_C2SR_FASTERR_Msk (0x1UL << FLASH_C2SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_C2SR_FASTERR FLASH_C2SR_FASTERR_Msk /*!< CPU2 Fast programming error */ +#define FLASH_C2SR_RDERR_Pos (14U) +#define FLASH_C2SR_RDERR_Msk (0x1UL << FLASH_C2SR_RDERR_Pos) /*!< 0x00004000 */ +#define FLASH_C2SR_RDERR FLASH_C2SR_RDERR_Msk /*!< CPU2 PCROP read error */ +#define FLASH_C2SR_BSY_Pos (16U) +#define FLASH_C2SR_BSY_Msk (0x1UL << FLASH_C2SR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_C2SR_BSY FLASH_C2SR_BSY_Msk /*!< CPU2 Flash busy */ +#define FLASH_C2SR_CFGBSY_Pos (18U) +#define FLASH_C2SR_CFGBSY_Msk (0x1UL << FLASH_C2SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_C2SR_CFGBSY FLASH_C2SR_CFGBSY_Msk /*!< CPU2 Programming or erase configuration busy */ +#define FLASH_C2SR_PESD_Pos (19U) +#define FLASH_C2SR_PESD_Msk (0x1UL << FLASH_C2SR_PESD_Pos) /*!< 0x00080000 */ +#define FLASH_C2SR_PESD FLASH_C2SR_PESD_Msk /*!< CPU2 Programming/erase operation suspended */ + +/****************** Bits definition for FLASH_C2CR register ************/ +#define FLASH_C2CR_PG_Pos (0U) +#define FLASH_C2CR_PG_Msk (0x1UL << FLASH_C2CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_C2CR_PG FLASH_C2CR_PG_Msk /*!< CPU2 Flash programming */ +#define FLASH_C2CR_PER_Pos (1U) +#define FLASH_C2CR_PER_Msk (0x1UL << FLASH_C2CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_C2CR_PER FLASH_C2CR_PER_Msk /*!< CPU2 Page erase */ +#define FLASH_C2CR_MER_Pos (2U) +#define FLASH_C2CR_MER_Msk (0x1UL << FLASH_C2CR_MER_Pos) /*!< 0x00000004 */ +#define FLASH_C2CR_MER FLASH_C2CR_MER_Msk /*!< CPU2 Mass erase */ +#define FLASH_C2CR_PNB_Pos (3U) +#define FLASH_C2CR_PNB_Msk (0xFFUL << FLASH_C2CR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_C2CR_PNB FLASH_C2CR_PNB_Msk /*!< CPU2 Page number selection mask */ +#define FLASH_C2CR_STRT_Pos (16U) +#define FLASH_C2CR_STRT_Msk (0x1UL << FLASH_C2CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_C2CR_STRT FLASH_C2CR_STRT_Msk /*!< CPU2 Start an erase operation */ +#define FLASH_C2CR_FSTPG_Pos (18U) +#define FLASH_C2CR_FSTPG_Msk (0x1UL << FLASH_C2CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_C2CR_FSTPG FLASH_C2CR_FSTPG_Msk /*!< CPU2 Fast programming */ +#define FLASH_C2CR_EOPIE_Pos (24U) +#define FLASH_C2CR_EOPIE_Msk (0x1UL << FLASH_C2CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_C2CR_EOPIE FLASH_C2CR_EOPIE_Msk /*!< CPU2 End of operation interrupt enable */ +#define FLASH_C2CR_ERRIE_Pos (25U) +#define FLASH_C2CR_ERRIE_Msk (0x1UL << FLASH_C2CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_C2CR_ERRIE FLASH_C2CR_ERRIE_Msk /*!< CPU2 Error interrupt enable */ +#define FLASH_C2CR_RDERRIE_Pos (26U) +#define FLASH_C2CR_RDERRIE_Msk (0x1UL << FLASH_C2CR_RDERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_C2CR_RDERRIE FLASH_C2CR_RDERRIE_Msk /*!< CPU2 PCROP read error interrupt enable */ + +/******************************************************************************/ +/* */ +/* General Purpose I/O */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + +/******************************************************************************/ +/* */ +/* HSEM HW Semaphore */ +/* */ +/******************************************************************************/ +/******************** Bit definition for HSEM_R register ********************/ +#define HSEM_R_PROCID_Pos (0U) +#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */ +#define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!This driver provides the CMSIS device for the stm32wbxx products. This covers

  • STM32WB55xx devices
    • +
  • STM32WB5Mxx devices
  • STM32WB50xx devices
    • +
  • STM32WB35xx devices
    • +
  • STM32WB30xx devices

This driver is composed of the descriptions of the registers under “Include” directory.

Various template file are provided to easily build an application. They can be adapted to fit applications requirements.

@@ -45,13 +48,68 @@
  • Startup files are provided as example for IAR©, KEIL© and SW4STM32©.
  • Linker files are provided as example for IAR©, KEIL© and SW4STM32©.
    • +

    Specific consideration for available FLASH size inside linker file

    +

    The available flash size depends on the wireless binary used inside the STM32WB device.

    +

    The linker files templates for IAR, KEIL and GCC provide example of implementation which can be tuned.

    +

    You can refer to the below chapters to optimize the usage of the flash on your device.

    +

    STM32WB55xx, STM32WB50xx and STM32WB5M

    +

    The default linker file provided in “/Drivers/CMSIS/DeviceST/STM32WBxx/Source/Templates” allows the application to use 512KB of flash.

    +

    The maximum flash memory that can be used by the application is up to the Secure Flash Start Address (SFSA) that can be read from the option byte.

    +

    The __ICFEDIT_region_ROM_end__ in the linker can be modified with a value up to : (0x08000000 + (SFSA << 12)) - 1.

    +

    Example:

    +
      +
    • When the SFSA option byte is set to 0xA0, the maximum value to be used for __ICFEDIT_region_ROM_end is 0x0809FFFF which is 640KB of flash.
      • +
    +

    Note:

    +
      +
    • The SFSA option byte can only be set by the CPU2. The user cannot modify that value.
      • +
    +

    STM32WB35xx and STM32WB30xx

    +

    The default linker file provided in "/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates allows the application to use 120KB of flash.

    +

    The maximum flash memory that can be used by the application is up to the Secure Flash Start Address (SFSA) that can be read from the option byte.

    +

    The __ICFEDIT_region_ROM_end__ in the linker can be modified with a value up to : (0x08000000 + (SFSA << 12)) - 1.

    +

    Example:

    +
      +
    • When the SFSA option byte is set to 0x32, the maximum value to be used for __ICFEDIT_region_ROM_end is 0x08031FFF – which is 200KB of flash
      • +
    +

    Note:

    +
      +
    • The SFSA option byte can only be set by the CPU2. The user cannot modify that value.
      • +

    Update History

    - +

    Main Changes

    +

    Introduction of STM32WB35xx, STM32WB30xx and STM32WB5Mxx product

    +

    This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.

    +

    Added features:

    +
      +
    • Templates/system_stm32wbxx.c contains the initialization code referred as SystemInit.
      • +
    • Startup files are provided as example for IAR©, KEIL© and SW4STM32©.
      • +
    • Linker files are provided as example for IAR©, KEIL© and SW4STM32©.
      • +
    • The product STM32WB5Mxx is supported by enabling inside your project the define “STM32WB5Mxx”.
      • +
    • The product STM32WB35xx is supported by enabling inside your project the define “STM32WB35xx”.
      • +
    • The product STM32WB30xx is supported by enabling inside your project the define “STM32WB30xx”.
      • +
    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
    • System Workbench STM32 (SW4STM32) toolchain V2.7
      • +
    +

    Supported Devices and boards

    +
      +
    • STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx and STM32WB30xx devices.
      • +
    +
    +
    +
    + +
    +

    Main Changes

    Maintenance release for STM32WBxx devices (stm32wb55xx and stm32wb50xx devices)

    @@ -74,13 +132,13 @@
    -

    Development Toolchains and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • System Workbench STM32 (SW4STM32) toolchain V2.7
    -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx, STM32WB50xx devices
    @@ -89,18 +147,18 @@
    -

    Main Changes

    +

    Main Changes

    Introduction of STM32WB50xx device

    First release for STM32WBxx CMSIS introducing stm32wb50xx devices.

    Contents

    CMSIS devices files for stm32wb55xx, stm32wb50xx devices.

    -

    Development Toolchains and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • System Workbench STM32 (SW4STM32) toolchain V2.7
    -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx and STM32WB50xx devices
    @@ -109,7 +167,7 @@
    -

    Main Changes

    +

    Main Changes

    Maintenance release

    Maintenance release for STM32WBxx devices (stm32wb55xx devices)

    @@ -133,7 +191,7 @@
    -

    Main Changes

    +

    Main Changes

    First release

    Add support of STM32WB55xx.

    diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/linker/stm32wb30xx_flash_cm4.sct b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/linker/stm32wb30xx_flash_cm4.sct new file mode 100644 index 000000000..8c83058e0 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/linker/stm32wb30xx_flash_cm4.sct @@ -0,0 +1,21 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00080000 { ; load region size_region + ER_IROM1 0x08000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000004 0x7FFC { ; RW data + .ANY (+RW +ZI) + } + RW_RAM_SHARED 0x20008000 0x2800 { ; RW data + *(MAPPING_TABLE) + *(MB_MEM1) + *(MB_MEM2) + } + } + + diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/linker/stm32wb35xx_flash_cm4.sct b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/linker/stm32wb35xx_flash_cm4.sct new file mode 100644 index 000000000..8c83058e0 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/linker/stm32wb35xx_flash_cm4.sct @@ -0,0 +1,21 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00080000 { ; load region size_region + ER_IROM1 0x08000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000004 0x7FFC { ; RW data + .ANY (+RW +ZI) + } + RW_RAM_SHARED 0x20008000 0x2800 { ; RW data + *(MAPPING_TABLE) + *(MB_MEM1) + *(MB_MEM2) + } + } + + diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/linker/stm32wb5mxx_flash_cm4.sct b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/linker/stm32wb5mxx_flash_cm4.sct new file mode 100644 index 000000000..63845c07b --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/linker/stm32wb5mxx_flash_cm4.sct @@ -0,0 +1,21 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00080000 { ; load region size_region + ER_IROM1 0x08000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000004 0x2FFFC { ; RW data + .ANY (+RW +ZI) + } + RW_RAM_SHARED 0x20030000 0x2800 { ; RW data + *(MAPPING_TABLE) + *(MB_MEM1) + *(MB_MEM2) + } + } + + diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/startup_stm32wb30xx_cm4.s b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/startup_stm32wb30xx_cm4.s new file mode 100644 index 000000000..f1d673320 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/startup_stm32wb30xx_cm4.s @@ -0,0 +1,330 @@ +;****************************************************************************** +;* File Name : startup_stm32wb30xx_cm4.s +;* Author : MCD Application Team +;* Description : STM32WB30xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2019 STMicroelectronics. All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD and PVM detector + DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts + DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt + DCD FLASH_IRQHandler ; FLASH global Interrupt + DCD RCC_IRQHandler ; RCC Interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup + DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt + DCD ADC1_IRQHandler ; ADC1 Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt + DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt + DCD TIM2_IRQHandler ; TIM2 Global Interrupt + DCD PKA_IRQHandler ; PKA Interrupt + DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt + DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 Interrupt + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TSC_IRQHandler ; TSC Interrupt + DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts + DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt + DCD 0 ; Reserved + DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR + DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt + DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt + DCD HSEM_IRQHandler ; HSEM0 Interrupt + DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt + DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD AES2_IRQHandler ; AES2 Interrupt + DCD RNG_IRQHandler ; RNG1 Interrupt + DCD FPU_IRQHandler ; FPU Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_LSECSS_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT PKA_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK] + EXPORT IPCC_C1_RX_IRQHandler [WEAK] + EXPORT IPCC_C1_TX_IRQHandler [WEAK] + EXPORT HSEM_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT AES2_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_LSECSS_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +C2SEV_PWR_C2H_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +PKA_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler +TSC_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler +IPCC_C1_RX_IRQHandler +IPCC_C1_TX_IRQHandler +HSEM_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +AES2_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +DMAMUX1_OVR_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/startup_stm32wb35xx_cm4.s b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/startup_stm32wb35xx_cm4.s new file mode 100644 index 000000000..923382927 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/startup_stm32wb35xx_cm4.s @@ -0,0 +1,364 @@ +;****************************************************************************** +;* File Name : startup_stm32wb35xx_cm4.s +;* Author : MCD Application Team +;* Description : STM32WB35xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2019 STMicroelectronics. All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD and PVM detector + DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts + DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt + DCD FLASH_IRQHandler ; FLASH global Interrupt + DCD RCC_IRQHandler ; RCC Interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup + DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt + DCD ADC1_IRQHandler ; ADC1 Interrupt + DCD USB_HP_IRQHandler ; USB High Priority Interrupt + DCD USB_LP_IRQHandler ; USB Low Priority Interrupt + DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt + DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts + DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt + DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt + DCD TIM2_IRQHandler ; TIM2 Global Interrupt + DCD PKA_IRQHandler ; PKA Interrupt + DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt + DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt + DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt + DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt + DCD SPI1_IRQHandler ; SPI1 Interrupt + DCD SPI2_IRQHandler ; SPI2 Interrupt + DCD USART1_IRQHandler ; USART1 Interrupt + DCD LPUART1_IRQHandler ; LPUART1 Interrupt + DCD 0 ; Reserved + DCD TSC_IRQHandler ; TSC Interrupt + DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts + DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt + DCD CRS_IRQHandler ; CRS interrupt + DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR + DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt + DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt + DCD HSEM_IRQHandler ; HSEM0 Interrupt + DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt + DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt + DCD 0 ; Reserved + DCD QUADSPI_IRQHandler ; QUADSPI Interrupt + DCD AES1_IRQHandler ; AES1 Interrupt + DCD AES2_IRQHandler ; AES2 Interrupt + DCD RNG_IRQHandler ; RNG1 Interrupt + DCD FPU_IRQHandler ; FPU Interrupt + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_LSECSS_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT PKA_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK] + EXPORT IPCC_C1_RX_IRQHandler [WEAK] + EXPORT IPCC_C1_TX_IRQHandler [WEAK] + EXPORT HSEM_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT AES1_IRQHandler [WEAK] + EXPORT AES2_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_LSECSS_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +C2SEV_PWR_C2H_IRQHandler +COMP_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +PKA_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +LPUART1_IRQHandler +TSC_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +CRS_IRQHandler +PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler +IPCC_C1_RX_IRQHandler +IPCC_C1_TX_IRQHandler +HSEM_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +QUADSPI_IRQHandler +AES1_IRQHandler +AES2_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +DMAMUX1_OVR_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/startup_stm32wb5mxx_cm4.s b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/startup_stm32wb5mxx_cm4.s new file mode 100644 index 000000000..ced275485 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/arm/startup_stm32wb5mxx_cm4.s @@ -0,0 +1,368 @@ +;****************************************************************************** +;* File Name : startup_stm32wb5mxx_cm4.s +;* Author : MCD Application Team +;* Description : STM32WB5Mxx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2019 STMicroelectronics. All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD and PVM detector + DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts + DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt + DCD FLASH_IRQHandler ; FLASH global Interrupt + DCD RCC_IRQHandler ; RCC Interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup + DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt + DCD ADC1_IRQHandler ; ADC1 Interrupt + DCD USB_HP_IRQHandler ; USB High Priority Interrupt + DCD USB_LP_IRQHandler ; USB Low Priority Interrupt + DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt + DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts + DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt + DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt + DCD TIM2_IRQHandler ; TIM2 Global Interrupt + DCD PKA_IRQHandler ; PKA Interrupt + DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt + DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt + DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt + DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt + DCD SPI1_IRQHandler ; SPI1 Interrupt + DCD SPI2_IRQHandler ; SPI2 Interrupt + DCD USART1_IRQHandler ; USART1 Interrupt + DCD LPUART1_IRQHandler ; LPUART1 Interrupt + DCD SAI1_IRQHandler ; SAI Interrupt + DCD TSC_IRQHandler ; TSC Interrupt + DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts + DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt + DCD CRS_IRQHandler ; CRS interrupt + DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR + DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt + DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt + DCD HSEM_IRQHandler ; HSEM0 Interrupt + DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt + DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt + DCD LCD_IRQHandler ; LCD Interrupt + DCD QUADSPI_IRQHandler ; QUADSPI Interrupt + DCD AES1_IRQHandler ; AES1 Interrupt + DCD AES2_IRQHandler ; AES2 Interrupt + DCD RNG_IRQHandler ; RNG1 Interrupt + DCD FPU_IRQHandler ; FPU Interrupt + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_LSECSS_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT PKA_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK] + EXPORT IPCC_C1_RX_IRQHandler [WEAK] + EXPORT IPCC_C1_TX_IRQHandler [WEAK] + EXPORT HSEM_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT AES1_IRQHandler [WEAK] + EXPORT AES2_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_LSECSS_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +C2SEV_PWR_C2H_IRQHandler +COMP_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +PKA_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +LPUART1_IRQHandler +SAI1_IRQHandler +TSC_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +CRS_IRQHandler +PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler +IPCC_C1_RX_IRQHandler +IPCC_C1_TX_IRQHandler +HSEM_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +LCD_IRQHandler +QUADSPI_IRQHandler +AES1_IRQHandler +AES2_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +DMAMUX1_OVR_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb30xx_flash_cm4.ld b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb30xx_flash_cm4.ld new file mode 100644 index 000000000..552344c6e --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb30xx_flash_cm4.ld @@ -0,0 +1,187 @@ +/** +***************************************************************************** +** +** File : stm32wb30xx_flash_cm4.ld +** +** Abstract : System Workbench Minimal System calls file +** +** For more information about which c-functions +** need which of these lowlevel functions +** please consult the Newlib libc-manual +** +** Environment : System Workbench for MCU +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** +**

    © COPYRIGHT(c) 2019 Ac6

    +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of Ac6 nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20008000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K +RAM1 (xrw) : ORIGIN = 0x20000004, LENGTH = 0x7FFC +RAM_SHARED (xrw) : ORIGIN = 0x20008000, LENGTH = 10K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM1 AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM1 + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM1 + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED + MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED + MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED +} + + diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb35xx_flash_cm4.ld b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb35xx_flash_cm4.ld new file mode 100644 index 000000000..6045c9c3a --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb35xx_flash_cm4.ld @@ -0,0 +1,187 @@ +/** +***************************************************************************** +** +** File : stm32wb35xx_flash_cm4.ld +** +** Abstract : System Workbench Minimal System calls file +** +** For more information about which c-functions +** need which of these lowlevel functions +** please consult the Newlib libc-manual +** +** Environment : System Workbench for MCU +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** +**

    © COPYRIGHT(c) 2019 Ac6

    +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of Ac6 nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20008000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K +RAM1 (xrw) : ORIGIN = 0x20000004, LENGTH = 0x7FFC +RAM_SHARED (xrw) : ORIGIN = 0x20008000, LENGTH = 10K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM1 AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM1 + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM1 + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED + MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED + MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED +} + + diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb5mxx_flash_cm4.ld b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb5mxx_flash_cm4.ld new file mode 100644 index 000000000..96ad40d57 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb5mxx_flash_cm4.ld @@ -0,0 +1,187 @@ +/** +***************************************************************************** +** +** File : stm32wb5mxx_flash_cm4.ld +** +** Abstract : System Workbench Minimal System calls file +** +** For more information about which c-functions +** need which of these lowlevel functions +** please consult the Newlib libc-manual +** +** Environment : System Workbench for MCU +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** +**

    © COPYRIGHT(c) 2019 Ac6

    +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of Ac6 nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20030000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K +RAM1 (xrw) : ORIGIN = 0x20000004, LENGTH = 0x2FFFC +RAM_SHARED (xrw) : ORIGIN = 0x20030000, LENGTH = 10K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM1 AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM1 + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM1 + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED + MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED + MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED +} + + diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb30xx_cm4.s b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb30xx_cm4.s new file mode 100644 index 000000000..69fea6731 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb30xx_cm4.s @@ -0,0 +1,388 @@ +/** + ****************************************************************************** + * @file startup_stm32wb30xx_cm4.s + * @author MCD Application Team + * @brief STM32WB30xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* start address for the .MB_MEM2 section. defined in linker script */ +.word _sMB_MEM2 +/* end address for the .MB_MEM2 section. defined in linker script */ +.word _eMB_MEM2 + +/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */ +.macro INIT_BSS start, end + ldr r0, =\start + ldr r1, =\end + movs r3, #0 + bl LoopFillZerobss +.endm + +/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */ +.macro INIT_DATA start, end, src + ldr r0, =\start + ldr r1, =\end + ldr r2, =\src + movs r3, #0 + bl LoopCopyDataInit +.endm + +.section .text.data_initializers +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + bx lr + +FillZerobss: + str r3, [r0] + adds r0, r0, #4 + +LoopFillZerobss: + cmp r0, r1 + bcc FillZerobss + bx lr + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + INIT_DATA _sdata, _edata, _sidata + +/* Zero fill the bss segments. */ + INIT_BSS _sbss, _ebss + INIT_BSS _sMB_MEM2, _eMB_MEM2 + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application s entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_LSECSS_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word C2SEV_PWR_C2H_IRQHandler + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word PKA_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word 0 + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word 0 + .word 0 + .word TSC_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word 0 + .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + .word IPCC_C1_RX_IRQHandler + .word IPCC_C1_TX_IRQHandler + .word HSEM_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word 0 + .word 0 + .word 0 + .word AES2_IRQHandler + .word RNG_IRQHandler + .word FPU_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word DMAMUX1_OVR_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_LSECSS_IRQHandler + .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak C2SEV_PWR_C2H_IRQHandler + .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler + + .weak IPCC_C1_RX_IRQHandler + .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler + + .weak IPCC_C1_TX_IRQHandler + .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler + + .weak HSEM_IRQHandler + .thumb_set HSEM_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak AES2_IRQHandler + .thumb_set AES2_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb35xx_cm4.s b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb35xx_cm4.s new file mode 100644 index 000000000..eea98ff9c --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb35xx_cm4.s @@ -0,0 +1,439 @@ +/** + ****************************************************************************** + * @file startup_stm32wb35xx_cm4.s + * @author MCD Application Team + * @brief STM32WB35xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* start address for the .MB_MEM2 section. defined in linker script */ +.word _sMB_MEM2 +/* end address for the .MB_MEM2 section. defined in linker script */ +.word _eMB_MEM2 + +/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */ +.macro INIT_BSS start, end + ldr r0, =\start + ldr r1, =\end + movs r3, #0 + bl LoopFillZerobss +.endm + +/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */ +.macro INIT_DATA start, end, src + ldr r0, =\start + ldr r1, =\end + ldr r2, =\src + movs r3, #0 + bl LoopCopyDataInit +.endm + +.section .text.data_initializers +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + bx lr + +FillZerobss: + str r3, [r0] + adds r0, r0, #4 + +LoopFillZerobss: + cmp r0, r1 + bcc FillZerobss + bx lr + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + INIT_DATA _sdata, _edata, _sidata + +/* Zero fill the bss segments. */ + INIT_BSS _sbss, _ebss + INIT_BSS _sMB_MEM2, _eMB_MEM2 + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application s entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_LSECSS_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word C2SEV_PWR_C2H_IRQHandler + .word COMP_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word PKA_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word LPUART1_IRQHandler + .word 0 + .word TSC_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word CRS_IRQHandler + .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + .word IPCC_C1_RX_IRQHandler + .word IPCC_C1_TX_IRQHandler + .word HSEM_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word 0 + .word QUADSPI_IRQHandler + .word AES1_IRQHandler + .word AES2_IRQHandler + .word RNG_IRQHandler + .word FPU_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word DMAMUX1_OVR_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_LSECSS_IRQHandler + .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak C2SEV_PWR_C2H_IRQHandler + .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler + + .weak IPCC_C1_RX_IRQHandler + .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler + + .weak IPCC_C1_TX_IRQHandler + .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler + + .weak HSEM_IRQHandler + .thumb_set HSEM_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak AES1_IRQHandler + .thumb_set AES1_IRQHandler,Default_Handler + + .weak AES2_IRQHandler + .thumb_set AES2_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s new file mode 100644 index 000000000..3dd0441f0 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s @@ -0,0 +1,445 @@ +/** + ****************************************************************************** + * @file startup_stm32wb5mxx_cm4.s + * @author MCD Application Team + * @brief STM32WB5Mxx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* start address for the .MB_MEM2 section. defined in linker script */ +.word _sMB_MEM2 +/* end address for the .MB_MEM2 section. defined in linker script */ +.word _eMB_MEM2 + +/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */ +.macro INIT_BSS start, end + ldr r0, =\start + ldr r1, =\end + movs r3, #0 + bl LoopFillZerobss +.endm + +/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */ +.macro INIT_DATA start, end, src + ldr r0, =\start + ldr r1, =\end + ldr r2, =\src + movs r3, #0 + bl LoopCopyDataInit +.endm + +.section .text.data_initializers +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + bx lr + +FillZerobss: + str r3, [r0] + adds r0, r0, #4 + +LoopFillZerobss: + cmp r0, r1 + bcc FillZerobss + bx lr + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + INIT_DATA _sdata, _edata, _sidata + +/* Zero fill the bss segments. */ + INIT_BSS _sbss, _ebss + INIT_BSS _sMB_MEM2, _eMB_MEM2 + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application s entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_LSECSS_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word C2SEV_PWR_C2H_IRQHandler + .word COMP_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word PKA_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word LPUART1_IRQHandler + .word SAI1_IRQHandler + .word TSC_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word CRS_IRQHandler + .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + .word IPCC_C1_RX_IRQHandler + .word IPCC_C1_TX_IRQHandler + .word HSEM_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word LCD_IRQHandler + .word QUADSPI_IRQHandler + .word AES1_IRQHandler + .word AES2_IRQHandler + .word RNG_IRQHandler + .word FPU_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word DMAMUX1_OVR_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_LSECSS_IRQHandler + .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak C2SEV_PWR_C2H_IRQHandler + .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler + + .weak IPCC_C1_RX_IRQHandler + .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler + + .weak IPCC_C1_TX_IRQHandler + .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler + + .weak HSEM_IRQHandler + .thumb_set HSEM_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak AES1_IRQHandler + .thumb_set AES1_IRQHandler,Default_Handler + + .weak AES2_IRQHandler + .thumb_set AES2_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb30xx_flash_cm4.icf b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb30xx_flash_cm4.icf new file mode 100644 index 000000000..8f3317a41 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb30xx_flash_cm4.icf @@ -0,0 +1,40 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +/***** FLASH Part dedicated to M4 *****/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000004; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000; +define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x2000A7FF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__ to __ICFEDIT_region_RAM_SHARED_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */ +initialize by copy { readwrite }; +do not initialize { section .noinit, + section MAPPING_TABLE, + section MB_MEM1 }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite,block CSTACK, block HEAP }; +place in RAM_SHARED_region { first section MAPPING_TABLE}; +place in RAM_SHARED_region { section MB_MEM1}; +place in RAM_SHARED_region { section MB_MEM2}; diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb30xx_sram_cm4.icf b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb30xx_sram_cm4.icf new file mode 100644 index 000000000..181282b44 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb30xx_sram_cm4.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +/***** RAM dedicated to M4 *****/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x20003FFF; + +define symbol __ICFEDIT_region_RAM_start__ = 0x20004000 ; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF ; + +/***** RAM2a *****/ +define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000 ; +define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x2000A800 ; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb35xx_flash_cm4.icf b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb35xx_flash_cm4.icf new file mode 100644 index 000000000..8f3317a41 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb35xx_flash_cm4.icf @@ -0,0 +1,40 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +/***** FLASH Part dedicated to M4 *****/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000004; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000; +define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x2000A7FF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__ to __ICFEDIT_region_RAM_SHARED_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */ +initialize by copy { readwrite }; +do not initialize { section .noinit, + section MAPPING_TABLE, + section MB_MEM1 }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite,block CSTACK, block HEAP }; +place in RAM_SHARED_region { first section MAPPING_TABLE}; +place in RAM_SHARED_region { section MB_MEM1}; +place in RAM_SHARED_region { section MB_MEM2}; diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb35xx_sram_cm4.icf b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb35xx_sram_cm4.icf new file mode 100644 index 000000000..181282b44 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb35xx_sram_cm4.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +/***** RAM dedicated to M4 *****/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x20003FFF; + +define symbol __ICFEDIT_region_RAM_start__ = 0x20004000 ; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF ; + +/***** RAM2a *****/ +define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000 ; +define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x2000A800 ; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb5mxx_flash_cm4.icf b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb5mxx_flash_cm4.icf new file mode 100644 index 000000000..5f36da686 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb5mxx_flash_cm4.icf @@ -0,0 +1,40 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +/***** FLASH Part dedicated to M4 *****/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000004; +define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000; +define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x200327FF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__ to __ICFEDIT_region_RAM_SHARED_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */ +initialize by copy { readwrite }; +do not initialize { section .noinit, + section MAPPING_TABLE, + section MB_MEM1 }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite,block CSTACK, block HEAP }; +place in RAM_SHARED_region { first section MAPPING_TABLE}; +place in RAM_SHARED_region { section MB_MEM1}; +place in RAM_SHARED_region { section MB_MEM2}; diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb5mxx_sram_cm4.icf b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb5mxx_sram_cm4.icf new file mode 100644 index 000000000..97e3ef2d4 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb5mxx_sram_cm4.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +/***** RAM dedicated to M4 *****/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x20017FFF; + +define symbol __ICFEDIT_region_RAM_start__ = 0x20018000 ; +define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF ; + +/***** RAM2a *****/ +define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000 ; +define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x20037FFF ; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/startup_stm32wb30xx_cm4.s b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/startup_stm32wb30xx_cm4.s new file mode 100644 index 000000000..c24fba36b --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/startup_stm32wb30xx_cm4.s @@ -0,0 +1,422 @@ +;****************************************************************************** +;* File Name : startup_stm32wb30xx_cm4.s +;* Author : MCD Application Team +;* Description : M4 core vector table of the STM32WB30xx devices for the +;* IAR (EWARM) toolchain. +;* +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;****************************************************************************** +;* @attention +;* +;*

    © Copyright (c) 2019 STMicroelectronics. +;* All rights reserved.

    +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt + DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts + DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt + DCD FLASH_IRQHandler ; FLASH global Interrupt + DCD RCC_IRQHandler ; RCC Interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup + DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt + DCD ADC1_IRQHandler ; ADC1 Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt + DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt + DCD TIM2_IRQHandler ; TIM2 Global Interrupt + DCD PKA_IRQHandler ; PKA Interrupt + DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt + DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 Interrupt + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TSC_IRQHandler ; TSC Interrupt + DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts + DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt + DCD 0 ; Reserved + DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR + DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt + DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt + DCD HSEM_IRQHandler ; HSEM0 Interrupt + DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt + DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD AES2_IRQHandler ; AES2 Interrupt + DCD RNG_IRQHandler ; RNG1 Interrupt + DCD FPU_IRQHandler ; FPU Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK TAMP_STAMP_LSECSS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_LSECSS_IRQHandler + B TAMP_STAMP_LSECSS_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK C2SEV_PWR_C2H_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +C2SEV_PWR_C2H_IRQHandler + B C2SEV_PWR_C2H_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK PKA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PKA_IRQHandler + B PKA_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + + PUBWEAK IPCC_C1_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +IPCC_C1_RX_IRQHandler + B IPCC_C1_RX_IRQHandler + + PUBWEAK IPCC_C1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +IPCC_C1_TX_IRQHandler + B IPCC_C1_TX_IRQHandler + + PUBWEAK HSEM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM_IRQHandler + B HSEM_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK AES2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +AES2_IRQHandler + B AES2_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/startup_stm32wb35xx_cm4.s b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/startup_stm32wb35xx_cm4.s new file mode 100644 index 000000000..919503dca --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/startup_stm32wb35xx_cm4.s @@ -0,0 +1,507 @@ +;****************************************************************************** +;* File Name : startup_stm32wb35xx_cm4.s +;* Author : MCD Application Team +;* Description : M4 core vector table of the STM32WB35xx devices for the +;* IAR (EWARM) toolchain. +;* +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;****************************************************************************** +;* @attention +;* +;*

    © Copyright (c) 2019 STMicroelectronics. +;* All rights reserved.

    +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt + DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts + DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt + DCD FLASH_IRQHandler ; FLASH global Interrupt + DCD RCC_IRQHandler ; RCC Interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup + DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt + DCD ADC1_IRQHandler ; ADC1 Interrupt + DCD USB_HP_IRQHandler ; USB High Priority Interrupt + DCD USB_LP_IRQHandler ; USB Low Priority Interrupt + DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt + DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts + DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt + DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt + DCD TIM2_IRQHandler ; TIM2 Global Interrupt + DCD PKA_IRQHandler ; PKA Interrupt + DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt + DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt + DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt + DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt + DCD SPI1_IRQHandler ; SPI1 Interrupt + DCD SPI2_IRQHandler ; SPI2 Interrupt + DCD USART1_IRQHandler ; USART1 Interrupt + DCD LPUART1_IRQHandler ; LPUART1 Interrupt + DCD 0 ; Reserved + DCD TSC_IRQHandler ; TSC Interrupt + DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts + DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt + DCD CRS_IRQHandler ; CRS interrupt + DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR + DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt + DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt + DCD HSEM_IRQHandler ; HSEM0 Interrupt + DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt + DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt + DCD 0 ; Reserved + DCD QUADSPI_IRQHandler ; QUADSPI Interrupt + DCD AES1_IRQHandler ; AES1 Interrupt + DCD AES2_IRQHandler ; AES2 Interrupt + DCD RNG_IRQHandler ; RNG1 Interrupt + DCD FPU_IRQHandler ; FPU Interrupt + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK TAMP_STAMP_LSECSS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_LSECSS_IRQHandler + B TAMP_STAMP_LSECSS_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + PUBWEAK C2SEV_PWR_C2H_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +C2SEV_PWR_C2H_IRQHandler + B C2SEV_PWR_C2H_IRQHandler + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK PKA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PKA_IRQHandler + B PKA_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + + PUBWEAK IPCC_C1_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +IPCC_C1_RX_IRQHandler + B IPCC_C1_RX_IRQHandler + + PUBWEAK IPCC_C1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +IPCC_C1_TX_IRQHandler + B IPCC_C1_TX_IRQHandler + + PUBWEAK HSEM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM_IRQHandler + B HSEM_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK AES1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +AES1_IRQHandler + B AES1_IRQHandler + + PUBWEAK AES2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +AES2_IRQHandler + B AES2_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/startup_stm32wb5mxx_cm4.s b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/startup_stm32wb5mxx_cm4.s new file mode 100644 index 000000000..6d2a51d5a --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/startup_stm32wb5mxx_cm4.s @@ -0,0 +1,517 @@ +;****************************************************************************** +;* File Name : startup_stm32wb5mxx_cm4.s +;* Author : MCD Application Team +;* Description : M4 core vector table of the STM32WB5Mxx devices for the +;* IAR (EWARM) toolchain. +;* +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;****************************************************************************** +;* @attention +;* +;*

    © Copyright (c) 2019 STMicroelectronics. +;* All rights reserved.

    +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt + DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts + DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt + DCD FLASH_IRQHandler ; FLASH global Interrupt + DCD RCC_IRQHandler ; RCC Interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup + DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt + DCD ADC1_IRQHandler ; ADC1 Interrupt + DCD USB_HP_IRQHandler ; USB High Priority Interrupt + DCD USB_LP_IRQHandler ; USB Low Priority Interrupt + DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt + DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts + DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt + DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt + DCD TIM2_IRQHandler ; TIM2 Global Interrupt + DCD PKA_IRQHandler ; PKA Interrupt + DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt + DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt + DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt + DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt + DCD SPI1_IRQHandler ; SPI1 Interrupt + DCD SPI2_IRQHandler ; SPI2 Interrupt + DCD USART1_IRQHandler ; USART1 Interrupt + DCD LPUART1_IRQHandler ; LPUART1 Interrupt + DCD SAI1_IRQHandler ; SAI Interrupt + DCD TSC_IRQHandler ; TSC Interrupt + DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts + DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt + DCD CRS_IRQHandler ; CRS interrupt + DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR + DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt + DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt + DCD HSEM_IRQHandler ; HSEM0 Interrupt + DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt + DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt + DCD LCD_IRQHandler ; LCD Interrupt + DCD QUADSPI_IRQHandler ; QUADSPI Interrupt + DCD AES1_IRQHandler ; AES1 Interrupt + DCD AES2_IRQHandler ; AES2 Interrupt + DCD RNG_IRQHandler ; RNG1 Interrupt + DCD FPU_IRQHandler ; FPU Interrupt + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK TAMP_STAMP_LSECSS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_LSECSS_IRQHandler + B TAMP_STAMP_LSECSS_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + PUBWEAK C2SEV_PWR_C2H_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +C2SEV_PWR_C2H_IRQHandler + B C2SEV_PWR_C2H_IRQHandler + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK PKA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PKA_IRQHandler + B PKA_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + + PUBWEAK IPCC_C1_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +IPCC_C1_RX_IRQHandler + B IPCC_C1_RX_IRQHandler + + PUBWEAK IPCC_C1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +IPCC_C1_TX_IRQHandler + B IPCC_C1_TX_IRQHandler + + PUBWEAK HSEM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM_IRQHandler + B HSEM_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK AES1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +AES1_IRQHandler + B AES1_IRQHandler + + PUBWEAK AES2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +AES2_IRQHandler + B AES2_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/system_stm32wbxx.c b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/system_stm32wbxx.c index 759409368..4cb9e0e42 100644 --- a/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/system_stm32wbxx.c +++ b/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/system_stm32wbxx.c @@ -161,7 +161,7 @@ const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \ 4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */ -#if defined(STM32WB55xx) +#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \ {2UL,6UL,4UL,3UL,2UL,4UL}, \ {4UL,12UL,8UL,6UL,4UL,8UL}, \ @@ -223,7 +223,7 @@ void SystemInit(void) /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x22041000U; -#if defined(STM32WB55xx) +#if defined(STM32WB55xx) || defined(STM32WB5Mxx) /* Reset PLLSAI1CFGR register */ RCC->PLLSAI1CFGR = 0x22041000U; #endif diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index e6635d118..7d29c4f9e 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -241,7 +241,7 @@ #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32H7) || defined(STM32F4) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif @@ -313,8 +313,8 @@ #endif /* STM32L4 */ #if defined(STM32G0) -#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 -#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 #endif #if defined(STM32H7) @@ -579,8 +579,7 @@ #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 -#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) \ - || defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS @@ -955,7 +954,7 @@ #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 -#if defined(STM32L1) || defined(STM32L4) || defined(STM32H7) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif @@ -1014,7 +1013,7 @@ /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ @@ -1449,6 +1448,30 @@ #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */ /** * @} */ @@ -1507,13 +1530,13 @@ #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA @@ -1539,10 +1562,10 @@ */ #if defined(STM32G0) -#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD -#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD -#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD -#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler #endif #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg @@ -3219,9 +3242,8 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -3349,7 +3371,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined STM32G4 +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined STM32WL #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3457,9 +3479,9 @@ #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT -#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS -#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT -#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND /* alias CMSIS for compatibilities */ #define SDIO_IRQn SDMMC1_IRQn #define SDIO_IRQHandler SDMMC1_IRQHandler @@ -3472,7 +3494,7 @@ #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #endif -#if defined(STM32H7) +#if defined(STM32H7) || defined(STM32L5) #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback @@ -3727,9 +3749,9 @@ /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32L4) +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE -#endif +#endif /* STM32L4 || STM32F4 || STM32F7 */ /** * @} */ diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h index b69544f38..4e130d4a5 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h @@ -38,23 +38,26 @@ * @{ */ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup HAL_Exported_Constants HAL Exported Constants - * @{ - */ - /** @defgroup HAL_TICK_FREQ Tick Frequency * @{ */ -#define HAL_TICK_FREQ_10HZ 100U -#define HAL_TICK_FREQ_100HZ 10U -#define HAL_TICK_FREQ_1KHZ 1U -#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; /** * @} */ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants * @{ */ @@ -594,8 +597,8 @@ void HAL_IncTick(void); void HAL_Delay(uint32_t Delay); uint32_t HAL_GetTick(void); uint32_t HAL_GetTickPrio(void); -HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq); -uint32_t HAL_GetTickFreq(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); void HAL_SuspendTick(void); void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); @@ -630,7 +633,7 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void); */ extern __IO uint32_t uwTick; extern uint32_t uwTickPrio; -extern uint32_t uwTickFreq; +extern HAL_TickFreqTypeDef uwTickFreq; /** * @} */ diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_adc.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_adc.h index 51790fca2..0968ba989 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_adc.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_adc.h @@ -125,8 +125,8 @@ typedef struct This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. - Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag - to free the IRQ vector sequencer. + Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). + Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_exti.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_exti.h index e16979617..a122369a1 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_exti.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_exti.h @@ -105,18 +105,39 @@ typedef struct #define EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x11u) #define EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x12u) #define EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x13u) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define EXTI_LINE_20 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x14u) #define EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x15u) +#else +#define EXTI_LINE_20 (EXTI_RESERVED | EXTI_REG1 | 0x14u) +#define EXTI_LINE_21 (EXTI_RESERVED | EXTI_REG1 | 0x15u) +#endif #define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u) +#else +#define EXTI_LINE_23 (EXTI_RESERVED | EXTI_REG1 | 0x17u) +#endif #define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u) +#else +#define EXTI_LINE_25 (EXTI_RESERVED | EXTI_REG1 | 0x19u) +#endif #define EXTI_LINE_26 (EXTI_RESERVED | EXTI_REG1 | 0x1Au) #define EXTI_LINE_27 (EXTI_RESERVED | EXTI_REG1 | 0x1Bu) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu) +#else +#define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu) +#endif #define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du) #define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu) +#else +#define EXTI_LINE_31 (EXTI_RESERVED | EXTI_REG1 | 0x1Fu) +#endif #define EXTI_LINE_32 (EXTI_RESERVED | EXTI_REG2 | 0x00u) #define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u) #define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u) @@ -128,7 +149,7 @@ typedef struct #define EXTI_LINE_40 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x08u) #define EXTI_LINE_41 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x09u) #define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au) -#if defined (STM32WB55xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) #define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu) #else #define EXTI_LINE_43 (EXTI_RESERVED | EXTI_REG2 | 0x0Bu) @@ -170,7 +191,7 @@ typedef struct #define EXTI_GPIOA 0x00000000u #define EXTI_GPIOB 0x00000001u #define EXTI_GPIOC 0x00000002u -#if defined (STM32WB55xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) #define EXTI_GPIOD 0x00000003u #endif #define EXTI_GPIOE 0x00000004u @@ -261,7 +282,7 @@ typedef struct #define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) -#if defined (STM32WB55xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ ((__PORT__) == EXTI_GPIOB) || \ ((__PORT__) == EXTI_GPIOC) || \ diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash.h index 548518ffb..683e0f2a1 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash.h @@ -46,7 +46,7 @@ extern "C" { */ typedef struct { - uint32_t TypeErase; /*!< Mass erase or page erase. + uint32_t TypeErase; /*!< Page erase. This parameter can be a value of @ref FLASH_TYPE_ERASE */ uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled This parameter must be a value between 0 and (FLASH_PAGE_NB - 1) */ @@ -222,7 +222,6 @@ typedef struct * @{ */ #define FLASH_TYPEERASE_PAGES FLASH_CR_PER /*!< Pages erase only*/ -#define FLASH_TYPEERASE_MASSERASE FLASH_CR_MER /*!< Flash mass erase activation*/ /** * @} */ @@ -853,8 +852,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define IS_ADDR_ALIGNED_64BITS(__VALUE__) (((__VALUE__) & 0x7U) == (0x00UL)) -#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES) || \ - ((__VALUE__) == FLASH_TYPEERASE_MASSERASE)) +#define IS_FLASH_TYPEERASE(__VALUE__) ((__VALUE__) == FLASH_TYPEERASE_PAGES) #define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ ((__VALUE__) == FLASH_TYPEPROGRAM_FAST)) diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio_ex.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio_ex.h index fc10f8ebe..3000c6d92 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio_ex.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio_ex.h @@ -53,7 +53,7 @@ * */ -#if defined (STM32WB55xx) || defined (STM32WB50xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB50xx) /* | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 | *_____________________________________________________________________________________________ @@ -355,7 +355,6 @@ /** * @brief AF 15 selection */ - #define GPIO_AF15_EVENTOUT ((uint8_t)0x0f) /*!< EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0f) @@ -363,6 +362,241 @@ #endif +#if defined (STM32WB35xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ +#define GPIO_AF0_LSCO ((uint8_t)0x00) /*!< LSCO Alternate Function mapping */ +#define GPIO_AF0_JTMS_SWDIO ((uint8_t)0x00) /*!< JTMS-SWDIO Alternate Function mapping */ +#define GPIO_AF0_JTCK_SWCLK ((uint8_t)0x00) /*!< JTCK-SWCLK Alternate Function mapping */ +#define GPIO_AF0_JTDI ((uint8_t)0x00) /*!< JTDI Alternate Function mapping */ +#define GPIO_AF0_RTC_OUT ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */ +#define GPIO_AF0_JTD_TRACE ((uint8_t)0x00) /*!< JTDO-TRACESWO Alternate Function mapping */ +#define GPIO_AF0_NJTRST ((uint8_t)0x00) /*!< NJTRST Alternate Function mapping */ +#define GPIO_AF0_TRACED0 ((uint8_t)0x00) /*!< TRACED0 Alternate Function mapping */ +#define GPIO_AF0_TRACED1 ((uint8_t)0x00) /*!< TRACED1 Alternate Function mapping */ +#define GPIO_AF0_TRACED2 ((uint8_t)0x00) /*!< TRACED2 Alternate Function mapping */ +#define GPIO_AF0_TRACED3 ((uint8_t)0x00) /*!< TRACED3 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_SPI1 ((uint8_t)0x03) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF3_SPI2 ((uint8_t)0x03) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF4_SPI1 ((uint8_t)0x04) /*!< SPI1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_MCO ((uint8_t)0x06) /*!< MCO Alternate Function mapping */ +#define GPIO_AF6_RF_DTB0 ((uint8_t)0x06) /*!< RF_DTB0 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB1 ((uint8_t)0x06) /*!< RF_DTB1 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB2 ((uint8_t)0x06) /*!< RF_DTB2 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB3 ((uint8_t)0x06) /*!< RF_DTB3 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB4 ((uint8_t)0x06) /*!< RF_DTB4 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB5 ((uint8_t)0x06) /*!< RF_DTB5 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB6 ((uint8_t)0x06) /*!< RF_DTB6 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB7 ((uint8_t)0x06) /*!< RF_DTB7 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB8 ((uint8_t)0x06) /*!< RF_DTB8 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB9 ((uint8_t)0x06) /*!< RF_DTB9 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB10 ((uint8_t)0x06) /*!< RF_DTB10 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB11 ((uint8_t)0x06) /*!< RF_DTB11 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB12 ((uint8_t)0x06) /*!< RF_DTB12 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB13 ((uint8_t)0x06) /*!< RF_DTB13 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB14 ((uint8_t)0x06) /*!< RF_DTB14 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB15 ((uint8_t)0x06) /*!< RF_DTB15 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB16 ((uint8_t)0x06) /*!< RF_DTB16 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB17 ((uint8_t)0x06) /*!< RF_DTB17 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB18 ((uint8_t)0x06) /*!< RF_DTB18 Alternate Function mapping */ +#define GPIO_AF6_RF_MISO ((uint8_t)0x06) /*!< RF_MISO Alternate Function mapping */ +#define GPIO_AF6_RF_MOSI ((uint8_t)0x06) /*!< RF_MOSI Alternate Function mapping */ +#define GPIO_AF6_RF_SCK ((uint8_t)0x06) /*!< RF_SCK Alternate Function mapping */ +#define GPIO_AF6_RF_NSS ((uint8_t)0x06) /*!< RF_NSS Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */ +#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ + #define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /*!< QUADSPI Alternate Function mapping */ +#define GPIO_AF10_USB ((uint8_t)0x0A) /*!< USB Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /*!< COMP1 Alternate Function mapping */ +#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /*!< COMP2 Alternate Function mapping */ +#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /*!< TIM1 Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0F) && ((AF) != (uint8_t)0x0B) && ((AF) != (uint8_t)0x0D)) + +#endif + +#if defined (STM32WB30xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ +#define GPIO_AF0_LSCO ((uint8_t)0x00) /*!< LSCO Alternate Function mapping */ +#define GPIO_AF0_JTMS_SWDIO ((uint8_t)0x00) /*!< JTMS-SWDIO Alternate Function mapping */ +#define GPIO_AF0_JTCK_SWCLK ((uint8_t)0x00) /*!< JTCK-SWCLK Alternate Function mapping */ +#define GPIO_AF0_JTDI ((uint8_t)0x00) /*!< JTDI Alternate Function mapping */ +#define GPIO_AF0_RTC_OUT ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */ +#define GPIO_AF0_JTD_TRACE ((uint8_t)0x00) /*!< JTDO-TRACESWO Alternate Function mapping */ +#define GPIO_AF0_NJTRST ((uint8_t)0x00) /*!< NJTRST Alternate Function mapping */ +#define GPIO_AF0_TRACED0 ((uint8_t)0x00) /*!< TRACED0 Alternate Function mapping */ +#define GPIO_AF0_TRACED1 ((uint8_t)0x00) /*!< TRACED1 Alternate Function mapping */ +#define GPIO_AF0_TRACED2 ((uint8_t)0x00) /*!< TRACED2 Alternate Function mapping */ +#define GPIO_AF0_TRACED3 ((uint8_t)0x00) /*!< TRACED3 Alternate Function mapping */ + + /** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF4_SPI1 ((uint8_t)0x04) /*!< SPI1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_MCO ((uint8_t)0x06) /*!< MCO Alternate Function mapping */ +#define GPIO_AF6_RF_DTB0 ((uint8_t)0x06) /*!< RF_DTB0 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB1 ((uint8_t)0x06) /*!< RF_DTB1 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB2 ((uint8_t)0x06) /*!< RF_DTB2 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB3 ((uint8_t)0x06) /*!< RF_DTB3 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB4 ((uint8_t)0x06) /*!< RF_DTB4 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB5 ((uint8_t)0x06) /*!< RF_DTB5 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB6 ((uint8_t)0x06) /*!< RF_DTB6 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB7 ((uint8_t)0x06) /*!< RF_DTB7 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB8 ((uint8_t)0x06) /*!< RF_DTB8 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB9 ((uint8_t)0x06) /*!< RF_DTB9 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB10 ((uint8_t)0x06) /*!< RF_DTB10 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB11 ((uint8_t)0x06) /*!< RF_DTB11 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB12 ((uint8_t)0x06) /*!< RF_DTB12 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB13 ((uint8_t)0x06) /*!< RF_DTB13 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB14 ((uint8_t)0x06) /*!< RF_DTB14 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB15 ((uint8_t)0x06) /*!< RF_DTB15 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB16 ((uint8_t)0x06) /*!< RF_DTB16 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB17 ((uint8_t)0x06) /*!< RF_DTB17 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB18 ((uint8_t)0x06) /*!< RF_DTB18 Alternate Function mapping */ +#define GPIO_AF6_RF_MISO ((uint8_t)0x06) /*!< RF_MISO Alternate Function mapping */ +#define GPIO_AF6_RF_MOSI ((uint8_t)0x06) /*!< RF_MOSI Alternate Function mapping */ +#define GPIO_AF6_RF_SCK ((uint8_t)0x06) /*!< RF_SCK Alternate Function mapping */ +#define GPIO_AF6_RF_NSS ((uint8_t)0x06) /*!< RF_NSS Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /*!< TIM1 Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0F) && ((AF) != (uint8_t)0x0A) && ((AF) != (uint8_t)0x0B) && ((AF) != (uint8_t)0x0D)) + +#endif + /** * @} @@ -380,7 +614,7 @@ /** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index * @{ */ -#if defined (STM32WB55xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ ((__GPIOx__) == (GPIOB))? 1uL :\ ((__GPIOx__) == (GPIOC))? 2uL :\ diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2s.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2s.h new file mode 100644 index 000000000..b1fcb0ab4 --- /dev/null +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2s.h @@ -0,0 +1,546 @@ +/** + ****************************************************************************** + * @file stm32wbxx_hal_i2s.h + * @author MCD Application Team + * @brief Header file of I2S HAL module. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBxx_HAL_I2S_H +#define STM32WBxx_HAL_I2S_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbxx_hal_def.h" + +#if defined(SPI_I2S_SUPPORT) +/** @addtogroup STM32WBxx_HAL_Driver + * @{ + */ + +/** @addtogroup I2S + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Types I2S Exported Types + * @{ + */ + +/** + * @brief I2S Init structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint32_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint32_t CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +} I2S_InitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */ + HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */ + HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */ + HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */ + HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */ +} HAL_I2S_StateTypeDef; + +/** + * @brief I2S handle Structure definition + */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1) +typedef struct __I2S_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +{ + SPI_TypeDef *Instance; /*!< I2S registers base address */ + + I2S_InitTypeDef Init; /*!< I2S communication parameters */ + + uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */ + + __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */ + + __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */ + + uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */ + + __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */ + + __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter + (This field is initialized at the + same value as transfer size at the + beginning of the transfer and + decremented when a sample is received + NbSamplesReceived = RxBufferSize-RxBufferCount) */ + DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */ + + __IO HAL_LockTypeDef Lock; /*!< I2S locking object */ + + __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */ + + __IO uint32_t ErrorCode; /*!< I2S Error code + This parameter can be a value of @ref I2S_Error */ + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */ + void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */ + void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */ + void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */ + void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */ + void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */ + void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */ + +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} I2S_HandleTypeDef; + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL I2S Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */ + HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */ + HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */ + HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */ + HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */ + HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */ + HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */ + +} HAL_I2S_CallbackIDTypeDef; + +/** + * @brief HAL I2S Callback pointer definition + */ +typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */ + +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_Exported_Constants I2S Exported Constants + * @{ + */ +/** @defgroup I2S_Error I2S Error + * @{ + */ +#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ +#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */ +#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */ +#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */ +#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) +#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup I2S_Mode I2S Mode + * @{ + */ +#define I2S_MODE_SLAVE_TX (0x00000000U) +#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) +#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) +#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)) +/** + * @} + */ + +/** @defgroup I2S_Standard I2S Standard + * @{ + */ +#define I2S_STANDARD_PHILIPS (0x00000000U) +#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) +#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) +#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)) +#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)) +/** + * @} + */ + +/** @defgroup I2S_Data_Format I2S Data Format + * @{ + */ +#define I2S_DATAFORMAT_16B (0x00000000U) +#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) +#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)) +#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)) +/** + * @} + */ + +/** @defgroup I2S_MCLK_Output I2S MCLK Output + * @{ + */ +#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE) +#define I2S_MCLKOUTPUT_DISABLE (0x00000000U) +/** + * @} + */ + +/** @defgroup I2S_Audio_Frequency I2S Audio Frequency + * @{ + */ +#define I2S_AUDIOFREQ_192K (192000U) +#define I2S_AUDIOFREQ_96K (96000U) +#define I2S_AUDIOFREQ_48K (48000U) +#define I2S_AUDIOFREQ_44K (44100U) +#define I2S_AUDIOFREQ_32K (32000U) +#define I2S_AUDIOFREQ_22K (22050U) +#define I2S_AUDIOFREQ_16K (16000U) +#define I2S_AUDIOFREQ_11K (11025U) +#define I2S_AUDIOFREQ_8K (8000U) +#define I2S_AUDIOFREQ_DEFAULT (2U) +/** + * @} + */ + +/** @defgroup I2S_Clock_Polarity I2S Clock Polarity + * @{ + */ +#define I2S_CPOL_LOW (0x00000000U) +#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL) +/** + * @} + */ + +/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition + * @{ + */ +#define I2S_IT_TXE SPI_CR2_TXEIE +#define I2S_IT_RXNE SPI_CR2_RXNEIE +#define I2S_IT_ERR SPI_CR2_ERRIE +/** + * @} + */ + +/** @defgroup I2S_Flags_Definition I2S Flags Definition + * @{ + */ +#define I2S_FLAG_TXE SPI_SR_TXE +#define I2S_FLAG_RXNE SPI_SR_RXNE + +#define I2S_FLAG_UDR SPI_SR_UDR +#define I2S_FLAG_OVR SPI_SR_OVR +#define I2S_FLAG_FRE SPI_SR_FRE + +#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE +#define I2S_FLAG_BSY SPI_SR_BSY + +#define I2S_FLAG_MASK (SPI_SR_RXNE\ + | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup I2S_Exported_macros I2S Exported Macros + * @{ + */ + +/** @brief Reset I2S handle state + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) +#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2S_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + +/** @brief Enable the specified SPI peripheral (in I2S mode). + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + +/** @brief Disable the specified SPI peripheral (in I2S mode). + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + +/** @brief Enable the specified I2S interrupts. + * @param __HANDLE__ specifies the I2S Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) + +/** @brief Disable the specified I2S interrupts. + * @param __HANDLE__ specifies the I2S Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) + +/** @brief Checks if the specified I2S interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the I2S Handle. + * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. + * @param __INTERRUPT__ specifies the I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks whether the specified I2S flag is set or not. + * @param __HANDLE__ specifies the I2S Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2S_FLAG_RXNE: Receive buffer not empty flag + * @arg I2S_FLAG_TXE: Transmit buffer empty flag + * @arg I2S_FLAG_UDR: Underrun flag + * @arg I2S_FLAG_OVR: Overrun flag + * @arg I2S_FLAG_FRE: Frame error flag + * @arg I2S_FLAG_CHSIDE: Channel Side flag + * @arg I2S_FLAG_BSY: Busy flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clears the I2S OVR pending flag. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \ + __IO uint32_t tmpreg_ovr = 0x00U; \ + tmpreg_ovr = (__HANDLE__)->Instance->DR; \ + tmpreg_ovr = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_ovr); \ + }while(0U) +/** @brief Clears the I2S UDR pending flag. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\ + __IO uint32_t tmpreg_udr = 0x00U;\ + tmpreg_udr = ((__HANDLE__)->Instance->SR);\ + UNUSED(tmpreg_udr); \ + }while(0U) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2S_Exported_Functions + * @{ + */ + +/** @addtogroup I2S_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s); +void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); +void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, + pI2S_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2S_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ***************************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); + +/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ +void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); +/** + * @} + */ + +/** @addtogroup I2S_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control and State functions ************************************/ +HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2S_Private_Macros I2S Private Macros + * @{ + */ + +/** @brief Check whether the specified SPI flag is set or not. + * @param __SR__ copy of I2S SR regsiter. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2S_FLAG_RXNE: Receive buffer not empty flag + * @arg I2S_FLAG_TXE: Transmit buffer empty flag + * @arg I2S_FLAG_UDR: Underrun error flag + * @arg I2S_FLAG_OVR: Overrun flag + * @arg I2S_FLAG_CHSIDE: Channel side flag + * @arg I2S_FLAG_BSY: Busy flag + * @retval SET or RESET. + */ +#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\ + & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) + +/** @brief Check whether the specified SPI Interrupt is set or not. + * @param __CR2__ copy of I2S CR2 regsiter. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval SET or RESET. + */ +#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks if I2S Mode parameter is in allowed range. + * @param __MODE__ specifies the I2S Mode. + * This parameter can be a value of @ref I2S_Mode + * @retval None + */ +#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \ + ((__MODE__) == I2S_MODE_SLAVE_RX) || \ + ((__MODE__) == I2S_MODE_MASTER_TX) || \ + ((__MODE__) == I2S_MODE_MASTER_RX)) + +#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \ + ((__STANDARD__) == I2S_STANDARD_MSB) || \ + ((__STANDARD__) == I2S_STANDARD_LSB) || \ + ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \ + ((__STANDARD__) == I2S_STANDARD_PCM_LONG)) + +#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \ + ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \ + ((__FORMAT__) == I2S_DATAFORMAT_24B) || \ + ((__FORMAT__) == I2S_DATAFORMAT_32B)) + +#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \ + ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE)) + +#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \ + ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \ + ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT)) + +/** @brief Checks if I2S Serial clock steady state parameter is in allowed range. + * @param __CPOL__ specifies the I2S serial clock steady state. + * This parameter can be a value of @ref I2S_Clock_Polarity + * @retval None + */ +#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \ + ((__CPOL__) == I2S_CPOL_HIGH)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SPI_I2S_SUPPORT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBxx_HAL_I2S_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr.h index 58f0bc39b..df07fd2fc 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr.h @@ -235,12 +235,22 @@ typedef struct * * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1U) ?\ - (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\ - ((((((uint8_t)(__FLAG__)) >> 5U) == 2U)) ?\ - (PWR->SR2 & (1U << ((__FLAG__) & 31U))) :\ - (PWR->EXTSCR & (1U << ((__FLAG__) & 31U))) ) ) - +#define __HAL_PWR_GET_FLAG(__FLAG__) ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR1) ? \ + ( \ + PWR->SR1 & (1UL << ((__FLAG__) & 31UL)) \ + ) \ + : \ + ( \ + (((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR2) ? \ + ( \ + PWR->SR2 & (1UL << ((__FLAG__) & 31UL)) \ + ) \ + : \ + ( \ + PWR->EXTSCR & (1UL << ((__FLAG__) & 31UL)) \ + ) \ + ) \ + ) /** @brief Clear a specific PWR flag. * @note Clearing of flags {PWR_FLAG_STOP, PWR_FLAG_SB} @@ -280,13 +290,18 @@ typedef struct * * @retval None */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1U) ?\ - ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\ - (PWR->SCR = (__FLAG__)) : (PWR->SCR = (1U << ((__FLAG__) & 31U))) ) :\ - ( (((uint8_t)(__FLAG__)) == PWR_FLAG_CRITICAL_RF_PHASE) ?\ - SET_BIT (PWR->EXTSCR, PWR_EXTSCR_CCRPF) : ( ((((uint8_t)((__FLAG__)) & 31U) <= PWR_EXTSCR_C1STOPF_Pos) ?\ - SET_BIT (PWR->EXTSCR, PWR_EXTSCR_C1CSSF): SET_BIT (PWR->EXTSCR, PWR_EXTSCR_C2CSSF)) ) )) - +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_EXTSCR) ? \ + ( \ + PWR->EXTSCR = (1UL << (((__FLAG__) & PWR_FLAG_EXTSCR_CLR_MASK) >> PWR_FLAG_EXTSCR_CLR_POS)) \ + ) \ + : \ + ( \ + (((__FLAG__)) == PWR_FLAG_WU) ? \ + (PWR->SCR = PWR_SCR_CWUF) : \ + (PWR->SCR = (1UL << ((__FLAG__) & 31UL))) \ + ) \ + ) + /** * @brief Enable the PVD Extended Interrupt C1 Line. * @retval None diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr_ex.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr_ex.h index b7367f4e6..612cfa28c 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr_ex.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr_ex.h @@ -323,62 +323,62 @@ typedef struct * - XX : Status register (2 bits) * - 01: SR1 register * - 10: SR2 register - * - 11: C2_SCR register + * - 11: EXTSCR register * The only exception is PWR_FLAG_WUF, encompassing all * wake-up flags and set to PWR_SR1_WUF. * @{ */ /*--------------------------------SR1-------------------------------*/ -#define PWR_FLAG_WUF1 (0x0020U) /*!< Wakeup event on wakeup pin 1 */ +#define PWR_FLAG_WUF1 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF1_Pos) /*!< Wakeup event on wakeup pin 1 */ #if defined(PWR_CR3_EWUP2) -#define PWR_FLAG_WUF2 (0x0021U) /*!< Wakeup event on wakeup pin 2 */ +#define PWR_FLAG_WUF2 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF2_Pos) /*!< Wakeup event on wakeup pin 2 */ #endif #if defined(PWR_CR3_EWUP3) -#define PWR_FLAG_WUF3 (0x0022U) /*!< Wakeup event on wakeup pin 3 */ +#define PWR_FLAG_WUF3 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF3_Pos) /*!< Wakeup event on wakeup pin 3 */ #endif -#define PWR_FLAG_WUF4 (0x0023U) /*!< Wakeup event on wakeup pin 4 */ +#define PWR_FLAG_WUF4 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF4_Pos) /*!< Wakeup event on wakeup pin 4 */ #if defined(PWR_CR3_EWUP5) -#define PWR_FLAG_WUF5 (0x0024U) /*!< Wakeup event on wakeup pin 5 */ +#define PWR_FLAG_WUF5 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF5_Pos) /*!< Wakeup event on wakeup pin 5 */ #endif -#define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */ +#define PWR_FLAG_WU (PWR_FLAG_REG_SR1 | PWR_SR1_WUF) /*!< Encompass wakeup event on all wakeup pins */ #if defined(PWR_CR5_SMPSEN) -#define PWR_FLAG_FRCBYPI (0x0027U) /*!< SMPS Forced in Bypass Interrupt Flag */ +#define PWR_FLAG_FRCBYPI (PWR_FLAG_REG_SR1 | PWR_SR1_SMPSFBF_Pos) /*!< SMPS Forced in Bypass Interrupt Flag */ #endif -#define PWR_FLAG_BHWF (0x0029U) /*!< BLE_Host WakeUp Flag */ -#define PWR_FLAG_RFPHASEI (0x002BU) /*!< Radio Phase Interrupt Flag */ -#define PWR_FLAG_BLEACTI (0x002CU) /*!< BLE Activity Interrupt Flag */ -#define PWR_FLAG_802ACTI (0x002DU) /*!< 802.15.4 Activity Interrupt Flag */ -#define PWR_FLAG_HOLDC2I (0x002EU) /*!< CPU2 on-Hold Interrupt Flag */ -#define PWR_FLAG_WUFI (0x002FU) /*!< Wakeup on internal wakeup line */ +#define PWR_FLAG_BHWF (PWR_FLAG_REG_SR1 | PWR_SR1_BLEWUF_Pos) /*!< BLE_Host WakeUp Flag */ +#define PWR_FLAG_RFPHASEI (PWR_FLAG_REG_SR1 | PWR_SR1_CRPEF_Pos) /*!< Radio Phase Interrupt Flag */ +#define PWR_FLAG_BLEACTI (PWR_FLAG_REG_SR1 | PWR_SR1_BLEAF_Pos) /*!< BLE Activity Interrupt Flag */ +#define PWR_FLAG_802ACTI (PWR_FLAG_REG_SR1 | PWR_SR1_802AF_Pos) /*!< 802.15.4 Activity Interrupt Flag */ +#define PWR_FLAG_HOLDC2I (PWR_FLAG_REG_SR1 | PWR_SR1_C2HF_Pos) /*!< CPU2 on-Hold Interrupt Flag */ +#define PWR_FLAG_WUFI (PWR_FLAG_REG_SR1 | PWR_SR1_WUFI_Pos) /*!< Wakeup on internal wakeup line */ /*--------------------------------SR2-------------------------------*/ #if defined(PWR_CR5_SMPSEN) -#define PWR_FLAG_SMPSRDYF (0x0040U) /*!< SMPS Ready Flag */ -#define PWR_FLAG_SMPSBYPF (0x0041U) /*!< SMPS Bypass Flag */ +#define PWR_FLAG_SMPSRDYF (PWR_FLAG_REG_SR2 | PWR_SR2_SMPSBF_Pos) /*!< SMPS Ready Flag */ +#define PWR_FLAG_SMPSBYPF (PWR_FLAG_REG_SR2 | PWR_SR2_SMPSF_Pos) /*!< SMPS Bypass Flag */ #endif -#define PWR_FLAG_REGLPS (0x0048U) /*!< Low-power regulator start flag */ -#define PWR_FLAG_REGLPF (0x0049U) /*!< Low-power regulator flag */ +#define PWR_FLAG_REGLPS (PWR_FLAG_REG_SR2 | PWR_SR2_REGLPS_Pos) /*!< Low-power regulator start flag */ +#define PWR_FLAG_REGLPF (PWR_FLAG_REG_SR2 | PWR_SR2_REGLPF_Pos) /*!< Low-power regulator flag */ #if defined(PWR_CR1_VOS) -#define PWR_FLAG_VOSF (0x004AU) /*!< Voltage scaling flag */ +#define PWR_FLAG_VOSF (PWR_FLAG_REG_SR2 | PWR_SR2_VOSF_Pos) /*!< Voltage scaling flag */ #endif -#define PWR_FLAG_PVDO (0x004BU) /*!< Power Voltage Detector output flag */ +#define PWR_FLAG_PVDO (PWR_FLAG_REG_SR2 | PWR_SR2_PVDO_Pos) /*!< Power Voltage Detector output flag */ -#define PWR_FLAG_PVMO1 (0x004CU) /*!< Power Voltage Monitoring 1 output flag */ -#define PWR_FLAG_PVMO3 (0x004EU) /*!< Power Voltage Monitoring 3 output flag */ +#define PWR_FLAG_PVMO1 (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO1_Pos) /*!< Power Voltage Monitoring 1 output flag */ +#define PWR_FLAG_PVMO3 (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO3_Pos) /*!< Power Voltage Monitoring 3 output flag */ /*------------------------------EXTSCR---------------------------*/ -#define PWR_FLAG_SB (0x0068U) /*!< System Standby flag for CPU1 */ -#define PWR_FLAG_STOP (0x0069U) /*!< System Stop flag for CPU1 */ +#define PWR_FLAG_SB (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1SBF_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Standby flag for CPU1 */ +#define PWR_FLAG_STOP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1STOPF_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop flag for CPU1 */ -#define PWR_FLAG_C2SB (0x006AU) /*!< System Standby flag for CPU2 */ -#define PWR_FLAG_C2STOP (0x006BU) /*!< System Stop flag for CPU2 */ +#define PWR_FLAG_C2SB (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2SBF_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Standby flag for CPU2 */ +#define PWR_FLAG_C2STOP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2STOPF_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop flag for CPU2 */ -#define PWR_FLAG_CRITICAL_RF_PHASE (0x006DU) /*!< Critical radio system phase flag */ -#define PWR_FLAG_C1DEEPSLEEP (0x006EU) /*!< CPU1 DeepSleep Flag */ -#define PWR_FLAG_C2DEEPSLEEP (0x006FU) /*!< CPU2 DeepSleep Flag */ +#define PWR_FLAG_CRITICAL_RF_PHASE (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_CRPF_Pos | (PWR_EXTSCR_CCRPF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< Critical radio system phase flag */ +#define PWR_FLAG_C1DEEPSLEEP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1DS_Pos) /*!< CPU1 DeepSleep Flag */ +#define PWR_FLAG_C2DEEPSLEEP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2DS_Pos) /*!< CPU2 DeepSleep Flag */ /** * @} */ @@ -436,6 +436,19 @@ typedef struct * @} */ +/** @defgroup PWR_FLAG_REG PWR flag register + * @{ + */ +#define PWR_FLAG_REG_SR1 (0x20UL) /* Bitfield to indicate PWR flag located in register PWR_SR1 */ +#define PWR_FLAG_REG_SR2 (0x40UL) /* Bitfield to indicate PWR flag located in register PWR_SR2 */ +#define PWR_FLAG_REG_EXTSCR (0x60UL) /* Bitfield to indicate PWR flag located in register PWR_EXTSCR */ +#define PWR_FLAG_REG_MASK (PWR_FLAG_REG_SR1 | PWR_FLAG_REG_SR2 | PWR_FLAG_REG_EXTSCR) /* Bitfield mask to indicate PWR flag location in PWR register */ +#define PWR_FLAG_EXTSCR_CLR_POS (16UL) /* Bitfield for register PWR_EXTSCR clearable bits positions: position of bitfield in flag literals */ +#define PWR_FLAG_EXTSCR_CLR_MASK ((PWR_EXTSCR_C1CSSF_Pos | PWR_EXTSCR_C2CSSF_Pos | PWR_EXTSCR_CCRPF_Pos) << PWR_FLAG_EXTSCR_CLR_POS) /* Bitfield for register PWR_EXTSCR clearable bits positions: mask of bitfield in flag literals */ +/** + * @} + */ + /** * @} */ diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc.h index 36c647b0d..1643d2ffe 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc.h @@ -120,9 +120,9 @@ extern "C" { #if defined(SAI1) #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_ADCCLK) == RCC_PLLSAI1_ADCCLK) || \ - (((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ - (((__VALUE__) & RCC_PLLSAI1_USBCLK) == RCC_PLLSAI1_USBCLK)) && \ - (((__VALUE__) & ~(RCC_PLLSAI1_ADCCLK|RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_USBCLK)) == 0U)) + (((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ + (((__VALUE__) & RCC_PLLSAI1_USBCLK) == RCC_PLLSAI1_USBCLK)) && \ + (((__VALUE__) & ~(RCC_PLLSAI1_ADCCLK | RCC_PLLSAI1_SAI1CLK | RCC_PLLSAI1_USBCLK)) == 0U)) #endif #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ ((__RANGE__) == RCC_MSIRANGE_1) || \ @@ -164,7 +164,14 @@ extern "C" { ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) -#define IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2) || ((__MCOX__) == RCC_MCO3) ) +#if defined(RCC_MCO3_SUPPORT) +#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1) || \ + ((__MCOX__) == RCC_MCO2) || \ + ((__MCOX__) == RCC_MCO3)) +#else +#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1) || \ + ((__MCOX__) == RCC_MCO2)) +#endif #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ @@ -510,6 +517,9 @@ typedef struct #define RCC_PLL_SAI1CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI1CLK selection from main PLL */ #endif #define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */ +#if defined(SPI_I2S_SUPPORT) +#define RCC_PLL_I2SCLK RCC_PLLCFGR_PLLPEN /*!< PLLI2SCLK selection from main PLL */ +#endif /** * @} */ @@ -629,7 +639,9 @@ typedef struct */ #define RCC_MCO1 0x00000000U /*!< MCO1 index */ #define RCC_MCO2 0x00000001U /*!< MCO2 index */ +#if defined(RCC_MCO3_SUPPORT) #define RCC_MCO3 0x00000002U /*!< MCO3 index */ +#endif #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 1 MCO*/ /** @@ -729,7 +741,9 @@ typedef struct #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ +#if defined(SAI1) #define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ +#endif /* Flags in the BDCR register */ #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ @@ -1216,7 +1230,7 @@ typedef struct #define __HAL_RCC_C2GPIOE_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_C2GPIOH_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) #define __HAL_RCC_C2ADC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_ADC) -#if defined(GPIOD) +#if defined(AES1) #define __HAL_RCC_C2AES1_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_AES1) #endif @@ -2921,6 +2935,7 @@ typedef struct * @arg @ref RCC_PLL_USBCLK This Clock is used to generate the clock for the USB FS (48 MHz) * @arg @ref RCC_PLL_RNGCLK This clock is used to generate the clock for RNG * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 64MHz) + * @arg @ref RCC_PLL_I2SCLK This Clock is used to generate the clock for the I2S * @retval None */ #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc_ex.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc_ex.h index 230929ec6..789a28856 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc_ex.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc_ex.h @@ -59,7 +59,14 @@ extern "C" { /** @addtogroup RCCEx_Private_Macros * @{ */ -#define IS_RCC_LSCO(__LSCOX__) ( ((__LSCOX__) == RCC_LSCO1) || ((__LSCOX__) == RCC_LSCO2) || ((__LSCOX__) == RCC_LSCO3) ) +#if defined(RCC_LSCO3_SUPPORT) +#define IS_RCC_LSCO(__LSCOX__) (((__LSCOX__) == RCC_LSCO1) || \ + ((__LSCOX__) == RCC_LSCO2) || \ + ((__LSCOX__) == RCC_LSCO3)) +#else +#define IS_RCC_LSCO(__LSCOX__) (((__LSCOX__) == RCC_LSCO1) || \ + ((__LSCOX__) == RCC_LSCO2)) +#endif #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) @@ -67,8 +74,8 @@ extern "C" { #if defined(LPUART1) && defined(I2C3) && defined(SAI1) && defined(USB) && defined(RCC_SMPS_SUPPORT) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ @@ -79,10 +86,25 @@ extern "C" { (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ (((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)|| \ (((__SELECTION__) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS)) +#elif defined(LPUART1) && defined(USB) && defined(RCC_SMPS_SUPPORT) && defined(SPI_I2S_SUPPORT) +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)|| \ + (((__SELECTION__) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)) #else #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ @@ -118,9 +140,9 @@ extern "C" { #endif #if defined(SAI1) -#define IS_RCC_SAI1CLK(__SOURCE__) \ +#define IS_RCC_SAI1CLK(__SOURCE__) \ (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) #endif @@ -145,6 +167,7 @@ extern "C" { ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE)) +#if defined(USB) #if defined(SAI1) #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ @@ -157,17 +180,24 @@ extern "C" { ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) #endif +#endif -#if defined(SAI1) +#if defined(STM32WB55xx) || defined (STM32WB5Mxx) #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ + (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) +#elif defined(STM32WB35xx) +#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) #else #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) #endif @@ -190,6 +220,14 @@ extern "C" { ((__SOURCE__) == RCC_SMPSCLKSOURCE_HSE)) #endif +#if defined(SPI_I2S_SUPPORT) +#define IS_RCC_I2SCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2SCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_I2SCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2SCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_I2SCLKSOURCE_PIN)) +#endif + #if defined(SAI1) #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U)) @@ -299,8 +337,10 @@ typedef struct This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ #endif +#if defined(USB) uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for RNG). This parameter can be a value of @ref RCCEx_USB_Clock_Source */ +#endif uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB). This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ @@ -322,6 +362,11 @@ typedef struct uint32_t SmpsDivSelection; /*!< Specifies SMPS clock division factor. This parameter can be a value of @ref RCCEx_SMPS_Clock_Divider */ #endif + +#if defined(SPI_I2S_SUPPORT) + uint32_t I2sClockSelection; /*!< Specifies I2s clock source. + This parameter can be a value of @ref RCCEx_I2s_Clock_Source */ +#endif } RCC_PeriphCLKInitTypeDef; @@ -389,7 +434,9 @@ typedef struct */ #define RCC_LSCO1 0x00000000U /*!< LSCO1 index */ #define RCC_LSCO2 0x00000001U /*!< LSCO2 index */ +#if defined(RCC_LSCO3_SUPPORT) #define RCC_LSCO3 0x00000002U /*!< LSCO3 index */ +#endif /** * @} */ @@ -421,7 +468,9 @@ typedef struct #define RCC_PERIPHCLK_SAI1 0x00000040U /*!< SAI1 Peripheral Clock Selection */ #endif #define RCC_PERIPHCLK_CLK48SEL 0x00000100U /*!< 48 MHz clock source selection */ +#if defined(USB) #define RCC_PERIPHCLK_USB RCC_PERIPHCLK_CLK48SEL /*!< USB Peripheral Clock Selection */ +#endif #define RCC_PERIPHCLK_RNG 0x00000200U /*!< RNG Peripheral Clock Selection */ #define RCC_PERIPHCLK_ADC 0x00000400U /*!< ADC Peripheral Clock Selection */ #define RCC_PERIPHCLK_RTC 0x00000800U /*!< RTC Peripheral Clock Selection */ @@ -429,6 +478,9 @@ typedef struct #if defined(RCC_SMPS_SUPPORT) #define RCC_PERIPHCLK_SMPS 0x00002000U /*!< SMPS Peripheral Clock Selection */ #endif +#if defined(SPI_I2S_SUPPORT) +#define RCC_PERIPHCLK_I2S 0x00004000U /*!< I2S Peripheral Clock Selection */ +#endif /** * @} */ @@ -527,24 +579,30 @@ typedef struct * @} */ +#if defined(USB) /** @defgroup RCCEx_USB_Clock_Source USB Clock Source * @{ */ #define RCC_USBCLKSOURCE_HSI48 LL_RCC_USB_CLKSOURCE_HSI48 /*!< HSI48 clock selected as USB clock */ +#if defined(SAI1) #define RCC_USBCLKSOURCE_PLLSAI1 LL_RCC_USB_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "Q" clock selected as USB clock */ +#endif #define RCC_USBCLKSOURCE_PLL LL_RCC_USB_CLKSOURCE_PLL /*!< PLL "Q" clock selected as USB clock */ #define RCC_USBCLKSOURCE_MSI LL_RCC_USB_CLKSOURCE_MSI /*!< MSI clock selected as USB clock */ /** * @} */ +#endif /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source * @{ */ #define RCC_ADCCLKSOURCE_NONE LL_RCC_ADC_CLKSOURCE_NONE /*!< None clock selected as ADC clock */ -#if defined(SAI1) +#if defined(STM32WB55xx) || defined (STM32WB5Mxx) #define RCC_ADCCLKSOURCE_PLLSAI1 LL_RCC_ADC_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "R" clock selected as ADC clock */ +#elif defined(STM32WB35xx) +#define RCC_ADCCLKSOURCE_HSI LL_RCC_ADC_CLKSOURCE_HSI /*!< HSI clock selected as ADC clock */ #endif #define RCC_ADCCLKSOURCE_PLL LL_RCC_ADC_CLKSOURCE_PLL /*!< PLL "P" clock selected as ADC clock */ #define RCC_ADCCLKSOURCE_SYSCLK LL_RCC_ADC_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as ADC clock */ @@ -611,6 +669,19 @@ typedef struct */ #endif +#if defined(SPI_I2S_SUPPORT) +/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source + * @{ + */ +#define RCC_I2SCLKSOURCE_NONE LL_RCC_I2S_CLKSOURCE_NONE /*!< No clock selected as I2S clock */ +#define RCC_I2SCLKSOURCE_PLL LL_RCC_I2S_CLKSOURCE_PLL /*!< PLL "Q" clock selected as I2S clock source */ +#define RCC_I2SCLKSOURCE_HSI LL_RCC_I2S_CLKSOURCE_HSI /*!< HSI clock selected as I2S clock */ +#define RCC_I2SCLKSOURCE_PIN LL_RCC_I2S_CLKSOURCE_PIN /*!< External clock selected as I2S clock */ +/** + * @} + */ +#endif + /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line * @{ */ @@ -1068,20 +1139,20 @@ typedef struct * @arg @ref RCC_RNGCLKSOURCE_LSE LSE clock selected as RNG clock * @retval None */ -#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ - do { \ - if (((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSI) \ +#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ + do { \ + if (((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSI) \ || ((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSE) \ || ((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_CLK48)) \ - { \ + { \ LL_RCC_SetRNGClockSource((__RNG_CLKSOURCE__)); \ - } \ - else \ - { \ + } \ + else \ + { \ uint32_t tmp = (__RNG_CLKSOURCE__) &(~CLK48_MASK); \ - LL_RCC_SetRNGClockSource(RCC_RNGCLKSOURCE_CLK48); \ + LL_RCC_SetRNGClockSource(RCC_RNGCLKSOURCE_CLK48); \ LL_RCC_SetCLK48ClockSource(tmp); \ - } \ + } \ } while(0U) /** @brief Macro to get the direct RNG clock. @@ -1094,6 +1165,7 @@ typedef struct */ #define __HAL_RCC_GET_RNG_SOURCE() LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE) +#if defined(USB) /** @brief Macro to configure the USB clock (USBCLK). * * @note USB and RNG peripherals share the same 48MHz clock source. @@ -1116,14 +1188,17 @@ typedef struct * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock */ #define __HAL_RCC_GET_USB_SOURCE() LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE) +#endif /** @brief Macro to configure the ADC interface clock. * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. * This parameter can be one of the following values: * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock - * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock (*) * @arg @ref RCC_ADCCLKSOURCE_PLL PLL Clock selected as ADC clock * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock (*) + * @note (*) Value not defined for all devices * @retval None */ #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) LL_RCC_SetADCClockSource(__ADC_CLKSOURCE__) @@ -1131,9 +1206,11 @@ typedef struct /** @brief Macro to get the ADC clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock - * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock (*) * @arg @ref RCC_ADCCLKSOURCE_PLL PLL Clock selected as ADC clock * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock (*) + * @note (*) Value not defined for all devices */ #define __HAL_RCC_GET_ADC_SOURCE() LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE) @@ -1217,6 +1294,28 @@ typedef struct * @{ */ +#if defined(SPI_I2S_SUPPORT) +/** @brief Macro to configure the I2S clock (I2SCLK). + * @param __I2S_CLKSOURCE__ specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2SCLKSOURCE_NONE No clock selected as I2S clock + * @arg @ref RCC_I2SCLKSOURCE_PLL PLL "Q" selected as I2S clock + * @arg @ref RCC_I2SCLKSOURCE_HSI HSI selected as I2S clock + * @arg @ref RCC_I2SCLKSOURCE_PIN External clock selected as I2S clock + * @retval None + */ +#define __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__) LL_RCC_SetI2SClockSource(__I2S_CLKSOURCE__) + +/** @brief Macro to get the I2S clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2SCLKSOURCE_NONE No clock selected as I2S clock + * @arg @ref RCC_I2SCLKSOURCE_PLL PLL "Q" selected as I2S clock + * @arg @ref RCC_I2SCLKSOURCE_HSI HSI selected as I2S clock + * @arg @ref RCC_I2SCLKSOURCE_PIN External clock selected as I2S clock + */ +#define __HAL_RCC_GET_I2S_SOURCE() LL_RCC_GetI2SClockSource(LL_RCC_I2S_CLKSOURCE) +#endif + #if defined(SAI1) /** @brief Enable PLLSAI1RDY interrupt. * @retval None diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h index ce4b09ee4..bf05e3bde 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h @@ -523,6 +523,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap + * @{ + */ +#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ +#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ +/** + * @} + */ + /** @defgroup TIM_ClockDivision TIM Clock Division * @{ */ @@ -1312,6 +1321,31 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to */ #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) + +/** + * @brief Get update interrupt flag (UIF) copy status. + * @param __COUNTER__ Counter value. + * @retval The state of UIFCPY (TRUE or FALSE). +mode. + */ +#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) + /** * @brief Indicates whether or not the TIM Counter is used as downcounter. * @param __HANDLE__ TIM handle. @@ -1331,6 +1365,8 @@ mode. /** * @brief Set the TIM Counter Register value on runtime. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance. + * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. * @param __HANDLE__ TIM handle. * @param __COUNTER__ specifies the Counter register new value. * @retval None @@ -1640,29 +1676,29 @@ mode. ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) -#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ - ((__BASE__) == TIM_DMABASE_CR2) || \ - ((__BASE__) == TIM_DMABASE_SMCR) || \ - ((__BASE__) == TIM_DMABASE_DIER) || \ - ((__BASE__) == TIM_DMABASE_SR) || \ - ((__BASE__) == TIM_DMABASE_EGR) || \ - ((__BASE__) == TIM_DMABASE_CCMR1) || \ - ((__BASE__) == TIM_DMABASE_CCMR2) || \ - ((__BASE__) == TIM_DMABASE_CCER) || \ - ((__BASE__) == TIM_DMABASE_CNT) || \ - ((__BASE__) == TIM_DMABASE_PSC) || \ - ((__BASE__) == TIM_DMABASE_ARR) || \ - ((__BASE__) == TIM_DMABASE_RCR) || \ - ((__BASE__) == TIM_DMABASE_CCR1) || \ - ((__BASE__) == TIM_DMABASE_CCR2) || \ - ((__BASE__) == TIM_DMABASE_CCR3) || \ - ((__BASE__) == TIM_DMABASE_CCR4) || \ - ((__BASE__) == TIM_DMABASE_BDTR) || \ - ((__BASE__) == TIM_DMABASE_OR) || \ - ((__BASE__) == TIM_DMABASE_CCMR3) || \ - ((__BASE__) == TIM_DMABASE_CCR5) || \ - ((__BASE__) == TIM_DMABASE_CCR6) || \ - ((__BASE__) == TIM_DMABASE_AF1) || \ +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_OR) || \ + ((__BASE__) == TIM_DMABASE_CCMR3) || \ + ((__BASE__) == TIM_DMABASE_CCR5) || \ + ((__BASE__) == TIM_DMABASE_CCR6) || \ + ((__BASE__) == TIM_DMABASE_AF1) || \ ((__BASE__) == TIM_DMABASE_AF2)) #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) @@ -1673,6 +1709,9 @@ mode. ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) +#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ + ((__MODE__) == TIM_UIFREMAP_ENALE)) + #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h index e11d35cf8..4fbb1fd39 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h @@ -1272,7 +1272,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT (4) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) * @@ -1466,7 +1466,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT (4) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) * @@ -2340,9 +2340,12 @@ __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) * Moreover, this avoids risk of overrun for low frequency * applications. * How to use this low power mode: - * - Do not use with interruption or DMA since these modes - * have to clear immediately the EOC flag to free the - * IRQ vector sequencer. + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). * - Do use with polling: 1. Start conversion, * 2. Later on, when conversion data is needed: poll for end of * conversion to ensure that conversion is completed and @@ -2393,9 +2396,12 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * Moreover, this avoids risk of overrun for low frequency * applications. * How to use this low power mode: - * - Do not use with interruption or DMA since these modes - * have to clear immediately the EOC flag to free the - * IRQ vector sequencer. + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). * - Do use with polling: 1. Start conversion, * 2. Later on, when conversion data is needed: poll for end of * conversion to ensure that conversion is completed and @@ -2549,7 +2555,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT (4) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) * @@ -3126,7 +3132,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT (4) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) * @@ -3621,7 +3627,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT (4) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) * diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_comp.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_comp.h index 49d720eb8..4348e8c49 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_comp.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_comp.h @@ -293,7 +293,7 @@ typedef struct /** * @brief Set window mode of a pair of comparators instances - * (2 consecutive COMP instances odd and even COMP and COMP). + * (2 consecutive COMP instances COMP and COMP). * @rmtoll CSR WINMODE LL_COMP_SetCommonWindowMode * @param COMPxy_COMMON Comparator common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() ) @@ -311,7 +311,7 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COM /** * @brief Get window mode of a pair of comparators instances - * (2 consecutive COMP instances odd and even COMP and COMP). + * (2 consecutive COMP instances COMP and COMP). * @rmtoll CSR WINMODE LL_COMP_GetCommonWindowMode * @param COMPxy_COMMON Comparator common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() ) diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_exti.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_exti.h index d2ef80424..7f9f59641 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_exti.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_exti.h @@ -107,16 +107,26 @@ typedef struct #define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ #define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ #define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ #define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ +#endif #define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ +#endif #define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ #define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */ +#endif #define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */ #define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */ +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */ +#endif + +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define LL_EXTI_LINE_ALL_0_31 (LL_EXTI_LINE_0 | LL_EXTI_LINE_1 | LL_EXTI_LINE_2 | \ LL_EXTI_LINE_3 | LL_EXTI_LINE_4 | LL_EXTI_LINE_5 | \ LL_EXTI_LINE_6 | LL_EXTI_LINE_7 | LL_EXTI_LINE_8 | \ @@ -127,6 +137,16 @@ typedef struct LL_EXTI_LINE_21 | LL_EXTI_LINE_22 | LL_EXTI_LINE_23 | \ LL_EXTI_LINE_24 | LL_EXTI_LINE_25 | LL_EXTI_LINE_28 | \ LL_EXTI_LINE_29 | LL_EXTI_LINE_30 | LL_EXTI_LINE_31) /*!< All Extended line not reserved*/ +#else +#define LL_EXTI_LINE_ALL_0_31 (LL_EXTI_LINE_0 | LL_EXTI_LINE_1 | LL_EXTI_LINE_2 | \ + LL_EXTI_LINE_3 | LL_EXTI_LINE_4 | LL_EXTI_LINE_5 | \ + LL_EXTI_LINE_6 | LL_EXTI_LINE_7 | LL_EXTI_LINE_8 | \ + LL_EXTI_LINE_9 | LL_EXTI_LINE_10 | LL_EXTI_LINE_11 | \ + LL_EXTI_LINE_12 | LL_EXTI_LINE_13 | LL_EXTI_LINE_14 | \ + LL_EXTI_LINE_15 | LL_EXTI_LINE_16 | LL_EXTI_LINE_17 | \ + LL_EXTI_LINE_18 | LL_EXTI_LINE_19 | LL_EXTI_LINE_22 | \ + LL_EXTI_LINE_24 | LL_EXTI_LINE_29 | LL_EXTI_LINE_30) /*!< All Extended line not reserved*/ +#endif #define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */ #define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ @@ -136,14 +156,14 @@ typedef struct #define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */ #define LL_EXTI_LINE_41 EXTI_IMR2_IM41 /*!< Extended line 41 */ #define LL_EXTI_LINE_42 EXTI_IMR2_IM42 /*!< Extended line 42 */ -#if defined (STM32WB55xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) #define LL_EXTI_LINE_43 EXTI_IMR2_IM43 /*!< Extended line 43 */ #endif #define LL_EXTI_LINE_44 EXTI_IMR2_IM44 /*!< Extended line 44 */ #define LL_EXTI_LINE_45 EXTI_IMR2_IM45 /*!< Extended line 45 */ #define LL_EXTI_LINE_46 EXTI_IMR2_IM46 /*!< Extended line 46 */ #define LL_EXTI_LINE_48 EXTI_IMR2_IM48 /*!< Extended line 48 */ -#if defined (STM32WB55xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) #define LL_EXTI_LINE_ALL_32_63 (LL_EXTI_LINE_33 | LL_EXTI_LINE_36 | LL_EXTI_LINE_37 | \ LL_EXTI_LINE_38 | LL_EXTI_LINE_39 | LL_EXTI_LINE_40 | \ LL_EXTI_LINE_41 | LL_EXTI_LINE_42 | LL_EXTI_LINE_43 | \ @@ -243,7 +263,7 @@ typedef struct /** * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -264,17 +284,18 @@ typedef struct * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_23 (*) * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_28 (*) * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_31 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) @@ -285,7 +306,7 @@ __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) /** * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2 * @rmtoll C2IMR1 IMx LL_C2_EXTI_EnableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -306,17 +327,18 @@ __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_23 (*) * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_28 (*) * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_31 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine) @@ -327,7 +349,7 @@ __STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine) /** * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_33 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 @@ -353,7 +375,7 @@ __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) /** * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2 * @rmtoll C2IMR2 IMx LL_C2_EXTI_EnableIT_32_63 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_33 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 @@ -379,7 +401,7 @@ __STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63(uint32_t ExtiLine) /** * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -400,17 +422,18 @@ __STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_23 (*) * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_28 (*) * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_31 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) @@ -421,7 +444,7 @@ __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) /** * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2 * @rmtoll C2IMR1 IMx LL_C2_EXTI_DisableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -442,17 +465,18 @@ __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_23 (*) * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_28 (*) * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_31 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine) @@ -463,7 +487,7 @@ __STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine) /** * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_33 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 @@ -489,7 +513,7 @@ __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) /** * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2 * @rmtoll C2IMR2 IMx LL_C2_EXTI_DisableIT_32_63 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_33 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 @@ -515,7 +539,7 @@ __STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63(uint32_t ExtiLine) /** * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -536,17 +560,18 @@ __STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_23 (*) * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_28 (*) * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_31 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 + * (*) value not defined in all devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) @@ -557,7 +582,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) /** * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 for cpu2 * @rmtoll C2IMR1 IMx LL_C2_EXTI_IsEnabledIT_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -578,17 +603,18 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_23 (*) * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_28 (*) * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_31 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 + * (*) value not defined in all devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) @@ -599,7 +625,7 @@ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) /** * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_33 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 @@ -625,7 +651,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) /** * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2 * @rmtoll C2IMR2 IMx LL_C2_EXTI_IsEnabledIT_32_63 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_33 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 @@ -659,7 +685,7 @@ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) /** * @brief Enable ExtiLine Event request for Lines in range 0 to 31 * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -679,9 +705,9 @@ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) @@ -692,7 +718,7 @@ __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) /** * @brief Enable ExtiLine Event request for Lines in range 0 to 31 for cpu2 * @rmtoll C2EMR1 EMx LL_C2_EXTI_EnableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -712,9 +738,9 @@ __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31(uint32_t ExtiLine) @@ -728,7 +754,6 @@ __STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 - * @arg @ref LL_EXTI_LINE_ALL_32_63 * @retval None */ __STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) @@ -742,7 +767,6 @@ __STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 - * @arg @ref LL_EXTI_LINE_ALL_32_63 * @retval None */ __STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine) @@ -753,7 +777,7 @@ __STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine) /** * @brief Disable ExtiLine Event request for Lines in range 0 to 31 * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -773,9 +797,8 @@ __STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) * @retval None */ __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) @@ -786,7 +809,7 @@ __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) /** * @brief Disable ExtiLine Event request for Lines in range 0 to 31 for cpu2 * @rmtoll C2EMR1 EMx LL_C2_EXTI_DisableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -806,9 +829,9 @@ __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31(uint32_t ExtiLine) @@ -822,7 +845,7 @@ __STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 - * @arg @ref LL_EXTI_LINE_ALL_32_63 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) @@ -836,7 +859,6 @@ __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 - * @arg @ref LL_EXTI_LINE_ALL_32_63 * @retval None */ __STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine) @@ -847,7 +869,7 @@ __STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine) /** * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -867,9 +889,9 @@ __STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * (*) value not defined in all devices * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -881,7 +903,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) /** * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 for cpu2 * @rmtoll C2EMR1 EMx LL_C2_EXTI_IsEnabledEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -901,9 +923,9 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * (*) value not defined in all devices * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -918,7 +940,6 @@ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 - * @arg @ref LL_EXTI_LINE_ALL_32_63 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) @@ -932,7 +953,6 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 - * @arg @ref LL_EXTI_LINE_ALL_32_63 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) @@ -979,9 +999,10 @@ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) @@ -1000,9 +1021,10 @@ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) * condition. * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) @@ -1041,9 +1063,10 @@ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) @@ -1063,9 +1086,10 @@ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) * condition. * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) @@ -1097,9 +1121,10 @@ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) @@ -1111,9 +1136,10 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63 * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) @@ -1160,9 +1186,10 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1182,9 +1209,10 @@ __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) * condition. * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) @@ -1222,9 +1250,10 @@ __STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1243,9 +1272,10 @@ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) * In this case, both generate a trigger condition. * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) @@ -1277,9 +1307,10 @@ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -1292,7 +1323,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63 * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 * @retval State of bit (1 or 0). @@ -1339,9 +1370,10 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1359,9 +1391,10 @@ __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) * register (by writing a 1 into the bit) * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) @@ -1403,9 +1436,10 @@ __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) @@ -1419,9 +1453,10 @@ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) * line. This bit is cleared by writing a 1 to the bit. * @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) @@ -1455,9 +1490,10 @@ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @retval @note This bit is set when the selected edge event arrives on the interrupt */ __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) @@ -1471,9 +1507,10 @@ __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) * line. This bit is cleared by writing a 1 to the bit. * @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices * @retval @note This bit is set when the selected edge event arrives on the interrupt */ __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine) @@ -1507,9 +1544,10 @@ __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) @@ -1523,9 +1561,10 @@ __STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) * line. This bit is cleared by writing a 1 to the bit. * @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine) diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_lptim.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_lptim.h index 5a0e72384..fdc820bec 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_lptim.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_lptim.h @@ -370,7 +370,7 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); } /** @@ -423,7 +423,7 @@ __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL)); } /** @@ -690,8 +690,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx) /** * @brief Set LPTIM input 1 source (default GPIO). - * @rmtoll OR OR_0 LL_LPTIM_SetInput1Src - * @rmtoll OR OR_1 LL_LPTIM_SetInput1Src + * @rmtoll OR OR LL_LPTIM_SetInput1Src * @param LPTIMx Low-Power Timer instance * @param Src This parameter can be one of the following values: * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO @@ -702,12 +701,12 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) { - WRITE_REG(LPTIMx->OR, Src); + MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src); } /** * @brief Set LPTIM input 2 source (default GPIO). - * @rmtoll OR OR_0 LL_LPTIM_SetInput2Src + * @rmtoll OR OR LL_LPTIM_SetInput2Src * @param LPTIMx Low-Power Timer instance * @param Src This parameter can be one of the following values: * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO @@ -716,7 +715,7 @@ __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) */ __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) { - WRITE_REG(LPTIMx->OR, Src); + MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src); } /** @@ -766,7 +765,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL)); } /** @@ -1035,7 +1034,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL)); } /** @@ -1065,7 +1064,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL)); } /** @@ -1087,7 +1086,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL)); } /** @@ -1109,7 +1108,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL)); } /** @@ -1131,7 +1130,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL)); } /** @@ -1153,7 +1152,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL)); } /** @@ -1175,7 +1174,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL)); } /** @@ -1197,7 +1196,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL)); } /** @@ -1238,7 +1237,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL)); } /** @@ -1271,7 +1270,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL)); } /** @@ -1304,7 +1303,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL)); } /** @@ -1337,7 +1336,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL)); } /** @@ -1366,11 +1365,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). + * @retval State of bit(1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL)); } /** @@ -1399,11 +1398,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). + * @retval State of bit(1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL)); } /** @@ -1432,11 +1431,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). + * @retval State of bit(1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx) { - return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE)? 1UL : 0UL); + return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL); } /** diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rcc.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rcc.h index 37cf24761..e448827aa 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rcc.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rcc.h @@ -124,6 +124,12 @@ typedef struct #if !defined (HSI48_VALUE) #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ #endif /* HSI48_VALUE */ + +#if defined(SPI_I2S_SUPPORT) +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 48000U /*!< Value of the I2S_CKIN external oscillator in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ +#endif /** * @} */ @@ -292,7 +298,6 @@ typedef struct * @} */ - /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler * @{ */ @@ -377,13 +382,13 @@ typedef struct * @} */ +#if defined(RCC_SMPS_SUPPORT) /** @defgroup RCC_LL_EC_SMPS_CLKSOURCE SMPS clock switch * @{ */ #define LL_RCC_SMPS_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as SMPS clock */ #define LL_RCC_SMPS_CLKSOURCE_MSI RCC_SMPSCR_SMPSSEL_0 /*!< MSI selection as SMPS clock */ #define LL_RCC_SMPS_CLKSOURCE_HSE RCC_SMPSCR_SMPSSEL_1 /*!< HSE selection as SMPS clock */ - /** * @} */ @@ -395,7 +400,6 @@ typedef struct #define LL_RCC_SMPS_CLKSOURCE_STATUS_MSI RCC_SMPSCR_SMPSSWS_0 /*!< MSI used as SMPS clock */ #define LL_RCC_SMPS_CLKSOURCE_STATUS_HSE RCC_SMPSCR_SMPSSWS_1 /*!< HSE used as SMPS clock */ #define LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK (RCC_SMPSCR_SMPSSWS_0|RCC_SMPSCR_SMPSSWS_1) /*!< No Clock used as SMPS clock */ - /** * @} */ @@ -407,13 +411,10 @@ typedef struct #define LL_RCC_SMPS_DIV_1 RCC_SMPSCR_SMPSDIV_0 /*!< SMPS clock division 1 */ #define LL_RCC_SMPS_DIV_2 RCC_SMPSCR_SMPSDIV_1 /*!< SMPS clock division 2 */ #define LL_RCC_SMPS_DIV_3 (RCC_SMPSCR_SMPSDIV_0|RCC_SMPSCR_SMPSDIV_1) /*!< SMPS clock division 3 */ - /** * @} */ - - - +#endif #if defined(USE_FULL_LL_DRIVER) /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency @@ -437,6 +438,7 @@ typedef struct * @} */ +#if defined(LPUART1) /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE LPUART1 CLKSOURCE * @{ */ @@ -447,6 +449,7 @@ typedef struct /** * @} */ +#endif /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE I2Cx CLKSOURCE * @{ @@ -478,6 +481,7 @@ typedef struct * @} */ +#if defined(SAI1) /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE SAI1 CLKSOURCE * @{ */ @@ -488,6 +492,7 @@ typedef struct /** * @} */ +#endif /** @defgroup RCC_LL_EC_CLK48_CLKSOURCE CLK48 CLKSOURCE * @{ @@ -519,8 +524,10 @@ typedef struct * @{ */ #define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as ADC clock*/ -#if defined(SAI1) +#if defined(STM32WB55xx) || defined (STM32WB5Mxx) #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 selected as ADC clock*/ +#elif defined(STM32WB35xx) +#define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_0 /*!< HSI selected as ADC clock*/ #endif #define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock*/ #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK selected as ADC clock*/ @@ -538,6 +545,19 @@ typedef struct * @} */ +#if defined(SPI_I2S_SUPPORT) +/** @defgroup RCC_LL_EC_I2SCLKSOURCE Peripheral I2S clock source selection + * @{ + */ +#define LL_RCC_I2S_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as I2S clock*/ +#define LL_RCC_I2S_CLKSOURCE_HSI RCC_CCIPR_I2SSEL_0 /*!< HSI clock used as I2S clock source */ +#define LL_RCC_I2S_CLKSOURCE_PLL RCC_CCIPR_I2SSEL_1 /*!< PLL clock used as I2S clock source */ +#define LL_RCC_I2S_CLKSOURCE_PIN RCC_CCIPR_I2SSEL /*!< External clock used as I2S clock source */ +/** + * @} + */ +#endif + /** @defgroup RCC_LL_EC_USART1 USART1 * @{ */ @@ -587,7 +607,7 @@ typedef struct /** @defgroup RCC_LL_EC_CLK48 CLK48 * @{ */ -#define LL_RCC_CLK48_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< USB clock source selection bits */ +#define LL_RCC_CLK48_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< CLK48 clock source selection bits */ /** * @} */ @@ -616,6 +636,16 @@ typedef struct * @} */ +#if defined(SPI_I2S_SUPPORT) +/** @defgroup RCC_LL_EC_I2S I2S + * @{ + */ +#define LL_RCC_I2S_CLKSOURCE RCC_CCIPR_I2SSEL /*!< I2S clock source selection bits */ +/** + * @} + */ +#endif + /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection * @{ */ @@ -734,6 +764,7 @@ typedef struct */ +#if defined(SAI1) /** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLQ) * @{ */ @@ -799,6 +830,7 @@ typedef struct /** * @} */ +#endif /** * @} @@ -968,6 +1000,60 @@ typedef struct #define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) +#if defined(SPI_I2S_SUPPORT) +/** + * @brief Helper macro to calculate the PLLPCLK frequency used on I2S domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) +#endif + /** * @brief Helper macro to calculate the PLLQCLK frequency used on 48M domain * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), @@ -2580,9 +2666,10 @@ __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) * @rmtoll CCIPR CLK48SEL LL_RCC_SetCLK48ClockSource * @param CLK48xSource This parameter can be one of the following values: * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 - * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL * @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI + * @note (*) Value not defined for all devices * @retval None */ __STATIC_INLINE void LL_RCC_SetCLK48ClockSource(uint32_t CLK48xSource) @@ -2590,6 +2677,7 @@ __STATIC_INLINE void LL_RCC_SetCLK48ClockSource(uint32_t CLK48xSource) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, CLK48xSource); } +#if defined(USB) /** * @brief Configure USB clock source * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource @@ -2604,6 +2692,7 @@ __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) { LL_RCC_SetCLK48ClockSource(USBxSource); } +#endif /** * @brief Configure RNG clock source @@ -2617,10 +2706,10 @@ __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE * @param CLK48xSource This parameter can be one of the following values: * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 - * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL * @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI - + * @note (*) Value not defined for all devices * @retval None */ __STATIC_INLINE void LL_RCC_ConfigRNGClockSource(uint32_t RNGxSource, uint32_t CLK48xSource) @@ -2638,9 +2727,11 @@ __STATIC_INLINE void LL_RCC_ConfigRNGClockSource(uint32_t RNGxSource, uint32_t C * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource * @param ADCxSource This parameter can be one of the following values: * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE - * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI (*) + * @note (*) Value not defined for all devices * @retval None */ __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) @@ -2648,6 +2739,23 @@ __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); } +#if defined(SPI_I2S_SUPPORT) +/** + * @brief Configure I2Sx clock source + * @rmtoll CCIPR I2SSEL LL_RCC_SetI2SClockSource + * @param I2SxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S_CLKSOURCE_NONE + * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL + * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2SSEL, I2SxSource); +} +#endif + /** * @brief Get USARTx clock source * @rmtoll CCIPR USART1SEL LL_RCC_GetUSARTClockSource @@ -2761,16 +2869,18 @@ __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) * @param CLK48x This parameter can be one of the following values: * @arg @ref LL_RCC_CLK48_CLKSOURCE * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 - * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL - * @arg @ref LL_RCC_USB_CLKSOURCE_MSI + * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*) + * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL + * @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI + * @note (*) Value not defined for all devices */ __STATIC_INLINE uint32_t LL_RCC_GetCLK48ClockSource(uint32_t CLK48x) { return (uint32_t)(READ_BIT(RCC->CCIPR, CLK48x)); } +#if defined(USB) /** * @brief Get USBx clock source * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource @@ -2786,6 +2896,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) { return LL_RCC_GetCLK48ClockSource(USBx); } +#endif /** * @brief Get ADCx clock source @@ -2794,15 +2905,34 @@ __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) * @arg @ref LL_RCC_ADC_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE - * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI (*) + * @note (*) Value not defined for all devices */ __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) { return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx)); } +#if defined(SPI_I2S_SUPPORT) +/** + * @brief Get I2Sx clock source + * @rmtoll CCIPR I2SSEL LL_RCC_GetI2SClockSource + * @param I2Sx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2S_CLKSOURCE_NONE + * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL + * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx)); +} +#endif /** * @} */ @@ -4403,7 +4533,9 @@ ErrorStatus LL_RCC_DeInit(void); * @{ */ void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +#if defined(RCC_SMPS_SUPPORT) uint32_t LL_RCC_GetSMPSClockFreq(void); +#endif uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); #if defined(LPUART1) @@ -4415,10 +4547,15 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); #endif uint32_t LL_RCC_GetCLK48ClockFreq(uint32_t CLK48xSource); uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); +#if defined(USB) uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#endif uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); uint32_t LL_RCC_GetRTCClockFreq(void); uint32_t LL_RCC_GetRFWKPClockFreq(void); +#if defined(SPI_I2S_SUPPORT) +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); +#endif /** * @} */ diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_spi.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_spi.h index 65ddb0f04..9230ff78a 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_spi.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_spi.h @@ -1405,6 +1405,872 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); * @} */ +#if defined(SPI_I2S_SUPPORT) +/** @defgroup I2S_LL I2S + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure + * @{ + */ + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + uint32_t Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_LL_EC_MODE + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/ + + uint32_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_STANDARD + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/ + + + uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/ + + + uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT + + This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/ + + + uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ + + Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity + and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/ + + + uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_LL_EC_POLARITY + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/ + +} LL_I2S_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants + * @{ + */ + +/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2S_ReadReg function + * @{ + */ +#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */ +#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */ +#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */ +#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */ +#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */ +#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ +#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ +#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_DATA_FORMAT Data format + * @{ + */ +#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */ +#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */ +#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */ +#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */ +#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_STANDARD I2s Standard + * @{ + */ +#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */ +#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */ +#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */ +#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */ +#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */ +#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */ +#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */ +#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor + * @{ + */ +#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */ +#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output + * @{ + */ +#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */ +#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency + * @{ + */ + +#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */ +#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */ +#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */ +#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */ +#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */ +#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */ +#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */ +#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */ +#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */ +#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros + * @{ + */ + +/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions + * @{ + */ + +/** @defgroup I2S_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Select I2S mode and Enable I2S peripheral + * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n + * I2SCFGR I2SE LL_I2S_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +} + +/** + * @brief Disable I2S peripheral + * @rmtoll I2SCFGR I2SE LL_I2S_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +} + +/** + * @brief Check if I2S peripheral is enabled + * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL); +} + +/** + * @brief Set I2S data frame length + * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n + * I2SCFGR CHLEN LL_I2S_SetDataFormat + * @param SPIx SPI Instance + * @param DataFormat This parameter can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_32B + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat); +} + +/** + * @brief Get I2S data frame length + * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n + * I2SCFGR CHLEN LL_I2S_GetDataFormat + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_32B + */ +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); +} + +/** + * @brief Set I2S clock polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + SET_BIT(SPIx->I2SCFGR, ClockPolarity); +} + +/** + * @brief Get I2S clock polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); +} + +/** + * @brief Set I2S standard protocol + * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n + * I2SCFGR PCMSYNC LL_I2S_SetStandard + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard); +} + +/** + * @brief Get I2S standard protocol + * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n + * I2SCFGR PCMSYNC LL_I2S_GetStandard + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + */ +__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); +} + +/** + * @brief Set I2S transfer mode + * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode); +} + +/** + * @brief Get I2S transfer mode + * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + */ +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); +} + +/** + * @brief Set I2S linear prescaler + * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear + * @param SPIx SPI Instance + * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear); +} + +/** + * @brief Get I2S linear prescaler + * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear + * @param SPIx SPI Instance + * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); +} + +/** + * @brief Set I2S parity prescaler + * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity + * @param SPIx SPI Instance + * @param PrescalerParity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U); +} + +/** + * @brief Get I2S parity prescaler + * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); +} + +/** + * @brief Enable the master clock ouput (Pin MCK) + * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); +} + +/** + * @brief Disable the master clock ouput (Pin MCK) + * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); +} + +/** + * @brief Check if the master clock ouput (Pin MCK) is enabled + * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL); +} + +#if defined(SPI_I2SCFGR_ASTRTEN) +/** + * @brief Enable asynchronous start + * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); +} + +/** + * @brief Disable asynchronous start + * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); +} + +/** + * @brief Check if asynchronous start is enabled + * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL); +} +#endif /* SPI_I2SCFGR_ASTRTEN */ + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_FLAG FLAG Management + * @{ + */ + +/** + * @brief Check if Rx buffer is not empty + * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_RXNE(SPIx); +} + +/** + * @brief Check if Tx buffer is empty + * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_TXE(SPIx); +} + +/** + * @brief Get busy flag + * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_BSY(SPIx); +} + +/** + * @brief Get overrun error flag + * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_OVR(SPIx); +} + +/** + * @brief Get underrun error flag + * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); +} + +/** + * @brief Get frame format error flag + * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_FRE(SPIx); +} + +/** + * @brief Get channel side flag. + * @note 0: Channel Left has to be transmitted or has been received\n + * 1: Channel Right has to be transmitted or has been received\n + * It has no significance in PCM mode. + * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL); +} + +/** + * @brief Clear overrun error flag + * @rmtoll SR OVR LL_I2S_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_OVR(SPIx); +} + +/** + * @brief Clear underrun error flag + * @rmtoll SR UDR LL_I2S_ClearFlag_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->SR; + (void)tmpreg; +} + +/** + * @brief Clear frame format error flag + * @rmtoll SR FRE LL_I2S_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_FRE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_IT Interrupt Management + * @{ + */ + +/** + * @brief Enable error IT + * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). + * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_ERR(SPIx); +} + +/** + * @brief Enable Rx buffer not empty IT + * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_RXNE(SPIx); +} + +/** + * @brief Enable Tx buffer empty IT + * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_TXE(SPIx); +} + +/** + * @brief Disable error IT + * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). + * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_ERR(SPIx); +} + +/** + * @brief Disable Rx buffer not empty IT + * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_RXNE(SPIx); +} + +/** + * @brief Disable Tx buffer empty IT + * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_TXE(SPIx); +} + +/** + * @brief Check if ERR IT is enabled + * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_ERR(SPIx); +} + +/** + * @brief Check if RXNE IT is enabled + * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_RXNE(SPIx); +} + +/** + * @brief Check if TXE IT is enabled + * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_TXE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DMA DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_RX(SPIx); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_RX(SPIx); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_RX(SPIx); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_TX(SPIx); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_TX(SPIx); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_TX(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DATA DATA Management + * @{ + */ + +/** + * @brief Read 16-Bits in data register + * @rmtoll DR DR LL_I2S_ReceiveData16 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) +{ + return LL_SPI_ReceiveData16(SPIx); +} + +/** + * @brief Write 16-Bits in data register + * @rmtoll DR DR LL_I2S_TransmitData16 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ + LL_SPI_TransmitData16(SPIx, TxData); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SPI_I2S_SUPPORT */ + #endif /* defined (SPI1) || defined (SPI2) */ /** diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_system.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_system.h index 89bacd005..fa349bca1 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_system.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_system.h @@ -58,6 +58,16 @@ extern "C" { /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants * @{ */ +/** + * @brief VREFBUF VREF_SC0 & VREF_SC1 calibration values + */ +#define VREFBUF_SC0_CAL_ADDR ((uint8_t*) (0x1FFF75F0UL)) /*!< Address of VREFBUF trimming value for VRS=0, + VREF_SC0 in STM32WB datasheet */ +#define VREFBUF_SC1_CAL_ADDR ((uint8_t*) (0x1FFF7530UL)) /*!< Address of VREFBUF trimming value for VRS=1, + VREF_SC1 in STM32WB datasheet */ +/** + * @} + */ /** * @} @@ -1876,6 +1886,24 @@ __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void) return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS)); } +/** + * @brief Get the VREFBUF trimming value for VRS=0 (VREF_SC0) + * @retval Between 0 and 0x3F + */ +__STATIC_INLINE uint32_t LL_VREFBUF_SC0_GetCalibration(void) +{ + return (uint32_t)(*VREFBUF_SC0_CAL_ADDR); +} + +/** + * @brief Get the VREFBUF trimming value for VRS=1 (VREF_SC1) + * @retval Between 0 and 0x3F + */ +__STATIC_INLINE uint32_t LL_VREFBUF_SC1_GetCalibration(void) +{ + return (uint32_t)(*VREFBUF_SC1_CAL_ADDR); +} + /** * @brief Check if Voltage reference buffer is ready * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady @@ -1898,6 +1926,11 @@ __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void) /** * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage) + * @note Each VrefBuf voltage scale is calibrated in production for each device, + * data stored in flash memory. + * Functions @ref LL_VREFBUF_SC0_GetCalibration and + * @ref LL_VREFBUF_SC0_GetCalibration can be used to retrieve + * these calibration data. * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming * @param Value Between 0 and 0x3F * @retval None diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h index f7d2fc5c4..05256d95b 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h @@ -120,30 +120,9 @@ static const uint8_t SHIFT_TAB_OISx[] = #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) /* Generic bit definitions for TIMx_AF1 register */ -#define TIMx_AF1_BKINE TIM1_AF1_BKINE /*!< BRK BKIN input enable */ -#if defined(COMP1) && defined(COMP2) -#define TIMx_AF1_BKCOMP1E TIM1_AF1_BKCMP1E /*!< BRK COMP1 enable */ -#define TIMx_AF1_BKCOMP2E TIM1_AF1_BKCMP2E /*!< BRK COMP2 enable */ -#endif /* COMP1 && COMP2 */ #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ -#if defined(COMP1) && defined(COMP2) -#define TIMx_AF1_BKCOMP1P TIM1_AF1_BKCMP1P /*!< BRK COMP1 input polarity */ -#define TIMx_AF1_BKCOMP2P TIM1_AF1_BKCMP2P /*!< BRK COMP2 input polarity */ -#endif /* COMP1 && COMP2 */ #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */ -/* Generic bit definitions for TIMx_AF2 register */ -#define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /*!< BRK2 BKIN2 input enable */ -#if defined(COMP1) && defined(COMP2) -#define TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E /*!< BRK2 COMP1 enable */ -#define TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E /*!< BRK2 COMP2 enable */ -#endif /* COMP1 && COMP2 */ -#define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /*!< BRK2 BKIN2 input polarity */ -#if defined(COMP1) && defined(COMP2) -#define TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P /*!< BRK2 COMP1 input polarity */ -#define TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P /*!< BRK2 COMP2 input polarity */ -#endif /* COMP1 && COMP2 */ - /* Remap mask definitions */ #define TIMx_OR_RMP_SHIFT 16U #define TIMx_OR_RMP_MASK 0x0000FFFFU @@ -252,13 +231,14 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ - uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. + GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ } LL_TIM_InitTypeDef; @@ -1141,7 +1121,7 @@ typedef struct /** @defgroup TIM_LL_EC_TIM2_ETR_RMP TIM2 External Trigger Remap * @{ */ -#define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR_RMP_MASK /*!< TIM2_ETR is connected to GPIO */ +#define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR_RMP_MASK /*!< TIM2_ETR is connected to GPIO */ #define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR_ETR_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ETR is connected to LSE */ /** * @} @@ -1681,7 +1661,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) * whether or not a timer instance supports a repetition counter. * @rmtoll RCR REP LL_TIM_SetRepetitionCounter * @param TIMx Timer instance - * @param RepetitionCounter between Min_Data=0 and Max_Data=255 + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. * @retval None */ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) @@ -1725,6 +1705,16 @@ __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); } +/** + * @brief Indicate whether update interrupt flag (UIF) copy is set. + * @param Counter Counter value + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter) +{ + return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); +} + /** * @} */ @@ -3295,8 +3285,8 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @brief Select the external trigger (ETR) input source. * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or * not a timer instance supports ETR source selection. - * @note When this function is called with LL_TIM_ETRSOURCE_GPIO, - * LL_TIM_ETRSOURCE_ADC1_AWD1, LL_TIM_ETRSOURCE_ADC1_AWD2 or + * @note When this function is called with LL_TIM_ETRSOURCE_GPIO, + * LL_TIM_ETRSOURCE_ADC1_AWD1, LL_TIM_ETRSOURCE_ADC1_AWD2 or * LL_TIM_ETRSOURCE_ADC1_AWD3, ETR source relies on TIMx ETR remapping * capability configured through the function @ref LL_TIM_SetRemap(). * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource @@ -3715,7 +3705,7 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB * TIM2_OR TI4_RMP LL_TIM_SetRemap\n * TIM2_OR TI1_RMP LL_TIM_SetRemap\n * TIM16_OR TI1_RMP LL_TIM_SetRemap\n - * TIM17_OR TI1_RMP LL_TIM_SetRemap\n + * TIM17_OR TI1_RMP LL_TIM_SetRemap * @param TIMx Timer instance * @param Remap Remap param depends on the TIMx. Description available only * in CHM version of the User Manual (not in .pdf). diff --git a/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html b/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html index b1fbd9f0c..73eb139a2 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html +++ b/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html @@ -46,9 +46,65 @@

    Update History

    - +

    Main Changes

    +

    Introduction of STM32WB5M, STM32WB35xx and STM32WB30xx product

    +

    This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.

    +

    Added features:

    +
      +
    • Introduction of I2S peripheral support. This only apply to STM32WB35xx.
      • +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    PeripheralHeadline
    HAL/LLVREFBUF trimming calibration must be written by software
    HALHAL_SetTickFreq() should update frequency on Systick_LOAD register and uwTickFreq correctly
    GPIOLL_GPIO_Init() generate undesired pulse
    I2CHardFault in I2C_DMAXferCplt
    I2CIncorrectly enable interrupts in I2C_Enable_IRQ routine when InterruptRequest = I2C_XFER_CPLT_IT
    RCCCannot enable PLL if PLL OFF with identical PLL config
    RCCClock reconfiguration issues once PLLSAI used
    I2SAdd peripheral for STM32WB35xx
    +

    Backward Compatibility

    +

    This release is compatible with the previous versions.

    +
    +
    +
    + +
    +

    Main Changes

    Maitenance release

    @@ -92,7 +148,7 @@
    -

    Backward Compatibility

    +

    Backward Compatibility

    This release is compatible with the previous versions.

    Dependencies

    This software release is compatible with:

    @@ -102,7 +158,7 @@
    -

    Main Changes

    +

    Main Changes

    Maitenance release

    @@ -174,7 +230,7 @@
    -

    Backward Compatibility

    +

    Backward Compatibility

    This release is compatible with the previous versions.

    Dependencies

    This software release is compatible with:

    @@ -184,7 +240,7 @@
    -

    Main Changes

    +

    Main Changes

    STM32WB50xx introduction and maintenance release

    First release for STM32WBxx HAL drivers introducing stm32wb50xx devices.

    @@ -253,7 +309,7 @@
    -

    Backward Compatibility

    +

    Backward Compatibility

    This release is compatible with the previous versions.

    Dependencies

    This software release is compatible with:

    @@ -263,7 +319,7 @@
    -

    Main Changes

    +

    Main Changes

    Maintenance release

    Maintenance release of HAL and Low layers drivers supporting STM32WB55xx devices.

    @@ -317,7 +373,7 @@
    -

    Backward Compatibility

    +

    Backward Compatibility

    This release is compatible with the previous versions.

    Dependencies

    This software release is compatible with:

    @@ -327,7 +383,7 @@
    -

    Main Changes

    +

    Main Changes

    First release

    First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32WB55xx.

    diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c index 4432f0b19..a778bffda 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c @@ -56,7 +56,7 @@ * @brief STM32WBxx HAL Driver version number */ #define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBxx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ +#define __STM32WBxx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ #define __STM32WBxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\ @@ -79,7 +79,7 @@ */ __IO uint32_t uwTick; uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ -uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ /** * @} */ @@ -346,17 +346,29 @@ uint32_t HAL_GetTickPrio(void) * @brief Set new tick Freq. * @retval Status */ -HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq) +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) { HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + assert_param(IS_TICKFREQ(Freq)); if (uwTickFreq != Freq) { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ uwTickFreq = Freq; /* Apply the new tick Freq */ status = HAL_InitTick(uwTickPrio); + + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } } return status; @@ -366,7 +378,7 @@ HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq) * @brief Return tick frequency. * @retval tick period in Hz */ -uint32_t HAL_GetTickFreq(void) +HAL_TickFreqTypeDef HAL_GetTickFreq(void) { return uwTickFreq; } @@ -626,14 +638,31 @@ uint32_t HAL_SYSCFG_IsEnabledSRAMFetch(void) * This requires VDDA equal to or higher than 2.4 V. * @arg @ref SYSCFG_VREFBUF_VOLTAGE_SCALE1 : VREF_OUT1 around 2.5 V. * This requires VDDA equal to or higher than 2.8 V. + * @note Retrieve the TrimmingValue from factory located at + * VREFBUF_SC0_CAL_ADDR or VREFBUF_SC1_CAL_ADDR addresses. * @retval None */ void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) { + uint32_t TrimmingValue; + /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); LL_VREFBUF_SetVoltageScaling(VoltageScaling); + + /* Restrieve Calibration data and store them into trimming field */ + if (VoltageScaling == SYSCFG_VREFBUF_VOLTAGE_SCALE0) + { + TrimmingValue = ((uint32_t) *VREFBUF_SC0_CAL_ADDR) & 0x3FU; + } + else + { + TrimmingValue = ((uint32_t) *VREFBUF_SC1_CAL_ADDR) & 0x3FU; + } + assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); + + HAL_SYSCFG_VREFBUF_TrimmingConfig(TrimmingValue); } /** @@ -655,6 +684,12 @@ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) /** * @brief Tune the Internal Voltage Reference buffer (VREFBUF). + * @note Each VrefBuf voltage scale is calibrated in production for each device, + * data stored in flash memory. + * Function @ref HAL_SYSCFG_VREFBUF_VoltageScalingConfig retrieves and + * applies this calibration data as trimming value at each scale change. + * Therefore, optionally, function @ref HAL_SYSCFG_VREFBUF_TrimmingConfig + * can be used in a second time to fine tune the trimming. * @param TrimmingValue specifies trimming code for VREFBUF calibration * This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x3F * @retval None diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c index ab3de969b..57db37d04 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c @@ -315,9 +315,9 @@ void HAL_FLASH_IRQHandler(void) /* return adress being programmed */ param = pFlash.Address; } - else if ((pFlash.ProcedureOnGoing & (FLASH_TYPEERASE_MASSERASE | FLASH_TYPEERASE_PAGES)) != 0U) + else if ((pFlash.ProcedureOnGoing & (FLASH_TYPEERASE_PAGES)) != 0U) { - /* return page number being erased (0 for mass erase) */ + /* return page number being erased */ param = pFlash.Page; } else @@ -389,7 +389,6 @@ void HAL_FLASH_IRQHandler(void) /** * @brief FLASH end of operation interrupt callback. * @param ReturnValue The value saved in this parameter depends on the ongoing procedure - * Mass Erase: 0 * Page Erase: Page which has been erased * Program: Address which was selected for data program * @retval None @@ -407,7 +406,6 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) /** * @brief FLASH operation error interrupt callback. * @param ReturnValue The value saved in this parameter depends on the ongoing procedure - * Mass Erase: 0 * Page Erase: Page number which returned an error * Program: Address which was selected for data program * @retval None diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c index 14976bbba..ce938822f 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c @@ -98,7 +98,6 @@ /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions * @{ */ -static void FLASH_MassErase(void); static void FLASH_AcknowledgePageErase(void); static void FLASH_FlushCaches(void); static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset); @@ -139,7 +138,7 @@ static HAL_StatusTypeDef FLASH_OB_ProceedWriteOperation(void); * @{ */ /** - * @brief Perform a mass erase or erase the specified FLASH memory pages. + * @brief Perform an erase of the specified FLASH memory pages. * @note Before any operation, it is possible to check there is no operation suspended * by call HAL_FLASHEx_IsOperationSuspended() * @param[in] pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that @@ -168,17 +167,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t if (status == HAL_OK) { - if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /* Mass erase to be done */ - FLASH_MassErase(); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - /* If operation is completed or interrupted, no need to clear the Mass Erase Bit */ - } - else + if (pEraseInit->TypeErase == FLASH_TYPEERASE_PAGES) { /*Initialization of PageError variable*/ *PageError = 0xFFFFFFFFU; @@ -214,7 +203,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t } /** - * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled. + * @brief Perform an erase of the specified FLASH memory pages with interrupt enabled. * @note Before any operation, it is possible to check there is no operation suspended * by call HAL_FLASHEx_IsOperationSuspended() * @param pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that @@ -250,15 +239,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) /* Enable End of Operation and Error interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); - if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /* Set Page to 0 for Interrupt callback managment */ - pFlash.Page = 0; - - /* Proceed to Mass Erase */ - FLASH_MassErase(); - } - else + if (pEraseInit->TypeErase == FLASH_TYPEERASE_PAGES) { /* Erase by page to be done */ pFlash.NbPagesToErase = pEraseInit->NbPages; @@ -513,16 +494,6 @@ uint32_t HAL_FLASHEx_IsOperationSuspended(void) * @{ */ -/** - * @brief Mass erase of FLASH memory. - * @retval None - */ -static void FLASH_MassErase(void) -{ - /* Set the Mass Erase Bit and start bit */ - SET_BIT(FLASH->CR, (FLASH_CR_MER | FLASH_CR_STRT)); -} - /** * @brief Erase the specified FLASH memory page. * @param Page FLASH page to erase diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c index 078809e22..852e018cb 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c @@ -188,26 +188,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) if (iocurrent != 0x00u) { /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Alternate function mode selection */ - if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Alternate function parameters */ - assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - - /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3u]; - temp &= ~(0xFu << ((position & 0x07u) * 4u)); - temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); - GPIOx->AFR[position >> 3u] = temp; - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); - GPIOx->MODER = temp; - /* In case of Output or Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) @@ -233,6 +213,26 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp |= ((GPIO_Init->Pull) << (position * 2u)); GPIOx->PUPDR = temp; + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3u]; + temp &= ~(0xFu << ((position & 0x07u) * 4u)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + GPIOx->AFR[position >> 3u] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + GPIOx->MODER = temp; + /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) @@ -314,9 +314,6 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) tmp &= (0x0FUL << (4u * (position & 0x03u))); if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) { - tmp = 0x0FuL << (4u * (position & 0x03u)); - SYSCFG->EXTICR[position >> 2u] &= ~tmp; - /* Clear EXTI line configuration */ EXTI->IMR1 &= ~(iocurrent); EXTI->EMR1 &= ~(iocurrent); @@ -324,6 +321,9 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /* Clear Rising Falling edge configuration */ EXTI->RTSR1 &= ~(iocurrent); EXTI->FTSR1 &= ~(iocurrent); + + tmp = 0x0FuL << (4u * (position & 0x03u)); + SYSCFG->EXTICR[position >> 2u] &= ~tmp; } /*------------------------- GPIO Mode Configuration --------------------*/ @@ -333,14 +333,14 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /* Configure the default Alternate Function in current IO */ GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ; - /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; - /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); } position++; diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c index 58a01f036..c047cd0c4 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c @@ -351,13 +351,13 @@ /* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (0x00000001U) -#define I2C_XFER_RX_IT (0x00000002U) -#define I2C_XFER_LISTEN_IT (0x00000004U) +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */ -#define I2C_XFER_ERROR_IT (0x00000011U) -#define I2C_XFER_CPLT_IT (0x00000012U) -#define I2C_XFER_RELOAD_IT (0x00000012U) +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */ /* Private define Sequential Transfer Options default/reset value */ #define I2C_NO_OPTION_FRAME (0xFFFF0000U) @@ -410,6 +410,9 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + /* Private function to flush TXDR register */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); @@ -4251,9 +4254,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Process Locked */ __HAL_LOCK(hi2c); - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Set State at HAL_I2C_STATE_ABORT */ hi2c->State = HAL_I2C_STATE_ABORT; @@ -5001,6 +5016,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { uint32_t tmpoptions = hi2c->XferOptions; uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; /* Process locked */ __HAL_LOCK(hi2c); @@ -5079,8 +5095,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); } @@ -5369,9 +5401,27 @@ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) */ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) { + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ @@ -5426,19 +5476,36 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); /* Reset handle parameters */ - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -5447,12 +5514,17 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + /* Flush TX register */ I2C_Flush_TXDR(hi2c); - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); - /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; @@ -5466,6 +5538,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; if (hi2c->Mode == HAL_I2C_MODE_MEM) { @@ -5500,6 +5573,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; if (hi2c->Mode == HAL_I2C_MODE_MEM) { @@ -5546,12 +5620,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -5565,6 +5653,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + if (hi2c->hdmatx != NULL) { hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); @@ -5572,6 +5663,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + if (hi2c->hdmarx != NULL) { hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); @@ -5608,7 +5702,6 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -5631,6 +5724,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5646,6 +5740,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5660,6 +5755,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5733,6 +5829,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { HAL_I2C_StateTypeDef tmpstate = hi2c->State; + uint32_t tmppreviousstate; /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; @@ -5752,7 +5849,6 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* keep HAL_I2C_STATE_LISTEN if set */ hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = I2C_Slave_ISR_IT; } else @@ -5767,16 +5863,19 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; } /* Abort DMA TX transfer if any */ - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + tmppreviousstate = hi2c->PreviousState; + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } - if (hi2c->hdmatx != NULL) + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ @@ -5792,13 +5891,20 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } } + else + { + I2C_TreatErrorCallback(hi2c); + } } /* Abort DMA RX transfer if any */ - else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } - if (hi2c->hdmarx != NULL) + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ @@ -5814,10 +5920,28 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } + else + { + I2C_TreatErrorCallback(hi2c); + } } - else if (hi2c->State == HAL_I2C_STATE_ABORT) + else + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5831,6 +5955,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) } else { + hi2c->PreviousState = I2C_STATE_NONE; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -6041,30 +6167,16 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Reset AbortCpltCallback */ - hi2c->hdmatx->XferAbortCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Check if come from abort from user */ - if (hi2c->State == HAL_I2C_STATE_ABORT) + if (hi2c->hdmatx != NULL) { - hi2c->State = HAL_I2C_STATE_READY; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->AbortCpltCallback(hi2c); -#else - HAL_I2C_AbortCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + hi2c->hdmatx->XferAbortCallback = NULL; } - else + if (hi2c->hdmarx != NULL) { - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->ErrorCallback(hi2c); -#else - HAL_I2C_ErrorCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + hi2c->hdmarx->XferAbortCallback = NULL; } + + I2C_TreatErrorCallback(hi2c); } /** @@ -6341,19 +6453,19 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); } - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; @@ -6379,7 +6491,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; @@ -6433,19 +6545,19 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2s.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2s.c new file mode 100644 index 000000000..22a078255 --- /dev/null +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2s.c @@ -0,0 +1,1802 @@ +/** + ****************************************************************************** + * @file stm32wbxx_hal_i2s.c + * @author MCD Application Team + * @brief I2S HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Integrated Interchip Sound (I2S) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The I2S HAL driver can be used as follow: + + (#) Declare a I2S_HandleTypeDef handle structure. + (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API: + (##) Enable the SPIx interface clock. + (##) I2S pins configuration: + (+++) Enable the clock for the I2S GPIOs. + (+++) Configure these I2S pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT() + and HAL_I2S_Receive_IT() APIs). + (+++) Configure the I2Sx interrupt priority. + (+++) Enable the NVIC I2S IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA() + and HAL_I2S_Receive_DMA() APIs: + (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx Stream/Channel. + (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the + DMA Tx/Rx Stream/Channel. + + (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity + using HAL_I2S_Init() function. + + -@- The specific I2S interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process. + -@- Make sure that either: + (+@) PLLPCLK output is configured or + (+@) HSI is enabled or + (+@) External clock source is configured after setting correctly + the define constant EXTERNAL_CLOCK_VALUE in the stm32wbxx_hal_conf.h file. + + (#) Three mode of operations are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() + (+) Receive an amount of data in blocking mode using HAL_I2S_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() + (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback + (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() + (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback + (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxCpltCallback + (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2S_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() + (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback + (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() + (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback + (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxCpltCallback + (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2S_ErrorCallback + (+) Pause the DMA Transfer using HAL_I2S_DMAPause() + (+) Resume the DMA Transfer using HAL_I2S_DMAResume() + (+) Stop the DMA Transfer using HAL_I2S_DMAStop() + + *** I2S HAL driver macros list *** + =================================== + [..] + Below the list of most used macros in I2S HAL driver. + + (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) + (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) + (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts + (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts + (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not + + [..] + (@) You can refer to the I2S HAL driver header file for more useful macros + + *** I2S HAL driver macros list *** + =================================== + [..] + Callback registration: + + (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback. + + Function HAL_I2S_RegisterCallback() allows to register following callbacks: + (++) TxCpltCallback : I2S Tx Completed callback + (++) RxCpltCallback : I2S Rx Completed callback + (++) TxHalfCpltCallback : I2S Tx Half Completed callback + (++) RxHalfCpltCallback : I2S Rx Half Completed callback + (++) ErrorCallback : I2S Error callback + (++) MspInitCallback : I2S Msp Init callback + (++) MspDeInitCallback : I2S Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + + (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default + weak function. + HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (++) TxCpltCallback : I2S Tx Completed callback + (++) RxCpltCallback : I2S Rx Completed callback + (++) TxHalfCpltCallback : I2S Tx Half Completed callback + (++) RxHalfCpltCallback : I2S Rx Half Completed callback + (++) ErrorCallback : I2S Error callback + (++) MspInitCallback : I2S Msp Init callback + (++) MspDeInitCallback : I2S Msp DeInit callback + + [..] + By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + [..] + Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit() + or HAL_I2S_Init() function. + + [..] + When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbxx_hal.h" + +#ifdef HAL_I2S_MODULE_ENABLED + +#if defined(SPI_I2S_SUPPORT) +/** @addtogroup STM32WBxx_HAL_Driver + * @{ + */ + +/** @defgroup I2S I2S + * @brief I2S HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup I2S_Private_Functions I2S Private Functions + * @{ + */ +static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMAError(DMA_HandleTypeDef *hdma); +static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s); +static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s); +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, + uint32_t Timeout); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup I2S_Exported_Functions I2S Exported Functions + * @{ + */ + +/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the I2Sx peripheral in simplex mode: + + (+) User must Implement HAL_I2S_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2S_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Standard + (++) Data Format + (++) MCLK Output + (++) Audio frequency + (++) Polarity + + (+) Call the function HAL_I2S_DeInit() to restore the default configuration + of the selected I2Sx peripheral. + @endverbatim + * @{ + */ + +/** + * @brief Initializes the I2S according to the specified parameters + * in the I2S_InitTypeDef and create the associated handle. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) +{ + uint32_t i2sdiv; + uint32_t i2sodd; + uint32_t packetlength; + uint32_t tmp; + uint32_t i2sclk = 0U; + + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); + assert_param(IS_I2S_MODE(hi2s->Init.Mode)); + assert_param(IS_I2S_STANDARD(hi2s->Init.Standard)); + assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq)); + assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); + + if (hi2s->State == HAL_I2S_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2s->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + /* Init the I2S Callback settings */ + hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hi2s->MspInitCallback == NULL) + { + hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hi2s->MspInitCallback(hi2s); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2S_MspInit(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + + hi2s->State = HAL_I2S_STATE_BUSY; + + /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ + SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ + SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD)); + hi2s->Instance->I2SPR = 0x0002U; + + /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/ + /* If the requested audio frequency is not the default, compute the prescaler */ + if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT) + { + /* Check the frame length (For the Prescaler computing) ********************/ + if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) + { + /* Packet length is 16 bits */ + packetlength = 16U; + } + else + { + /* Packet length is 32 bits */ + packetlength = 32U; + } + + /* I2S standard */ + if (hi2s->Init.Standard <= I2S_STANDARD_LSB) + { + /* In I2S standard packet lenght is multiplied by 2 */ + packetlength = packetlength * 2U; + } + + /* Get the source clock value: based on System Clock value */ + i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S); + + /* Compute the Real divider depending on the MCLK output state, with a floating point */ + if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) + { + /* MCLK output is enabled */ + if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B) + { + tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U); + } + else + { + tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U); + } + } + else + { + /* MCLK output is disabled */ + tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U); + } + + /* Remove the flatting point */ + tmp = tmp / 10U; + + /* Check the parity of the divider */ + i2sodd = (uint32_t)(tmp & (uint32_t)1U); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint32_t)((tmp - i2sodd) / 2U); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint32_t)(i2sodd << 8U); + } + else + { + /* Set the default values */ + i2sdiv = 2U; + i2sodd = 0U; + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) + { + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER); + return HAL_ERROR; + } + + /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ + + /* Write to SPIx I2SPR register the computed value */ + hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput)); + + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + /* And configure the I2S with the I2S_InitStruct values */ + MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ + SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ + SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ + SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD), \ + (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \ + hi2s->Init.Standard | hi2s->Init.DataFormat | \ + hi2s->Init.CPOL)); + +#if defined(SPI_I2SCFGR_ASTRTEN) + if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG))) + { + /* Write to SPIx I2SCFGR */ + SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN); + } +#endif /* SPI_I2SCFGR_ASTRTEN */ + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the I2S peripheral + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); + + hi2s->State = HAL_I2S_STATE_BUSY; + + /* Disable the I2S Peripheral Clock */ + __HAL_I2S_DISABLE(hi2s); + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + if (hi2s->MspDeInitCallback == NULL) + { + hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + hi2s->MspDeInitCallback(hi2s); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_I2S_MspDeInit(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief I2S MSP Init + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_MspInit could be implemented in the user file + */ +} + +/** + * @brief I2S MSP DeInit + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User I2S Callback + * To be used instead of the weak predefined callback + * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for the specified I2S. + * @param CallbackID ID of the callback to be registered + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, + pI2S_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2s); + + if (HAL_I2S_STATE_READY == hi2s->State) + { + switch (CallbackID) + { + case HAL_I2S_TX_COMPLETE_CB_ID : + hi2s->TxCpltCallback = pCallback; + break; + + case HAL_I2S_RX_COMPLETE_CB_ID : + hi2s->RxCpltCallback = pCallback; + break; + + case HAL_I2S_TX_HALF_COMPLETE_CB_ID : + hi2s->TxHalfCpltCallback = pCallback; + break; + + case HAL_I2S_RX_HALF_COMPLETE_CB_ID : + hi2s->RxHalfCpltCallback = pCallback; + break; + + case HAL_I2S_ERROR_CB_ID : + hi2s->ErrorCallback = pCallback; + break; + + case HAL_I2S_MSPINIT_CB_ID : + hi2s->MspInitCallback = pCallback; + break; + + case HAL_I2S_MSPDEINIT_CB_ID : + hi2s->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2S_STATE_RESET == hi2s->State) + { + switch (CallbackID) + { + case HAL_I2S_MSPINIT_CB_ID : + hi2s->MspInitCallback = pCallback; + break; + + case HAL_I2S_MSPDEINIT_CB_ID : + hi2s->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2s); + return status; +} + +/** + * @brief Unregister an I2S Callback + * I2S callback is redirected to the weak predefined callback + * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for the specified I2S. + * @param CallbackID ID of the callback to be unregistered + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2s); + + if (HAL_I2S_STATE_READY == hi2s->State) + { + switch (CallbackID) + { + case HAL_I2S_TX_COMPLETE_CB_ID : + hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_I2S_RX_COMPLETE_CB_ID : + hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_I2S_TX_HALF_COMPLETE_CB_ID : + hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_I2S_RX_HALF_COMPLETE_CB_ID : + hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_I2S_ERROR_CB_ID : + hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2S_MSPINIT_CB_ID : + hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2S_MSPDEINIT_CB_ID : + hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2S_STATE_RESET == hi2s->State) + { + switch (CallbackID) + { + case HAL_I2S_MSPINIT_CB_ID : + hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2S_MSPDEINIT_CB_ID : + hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2s); + return status; +} +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2S data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2S_Transmit() + (++) HAL_I2S_Receive() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2S_Transmit_IT() + (++) HAL_I2S_Receive_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2S_Transmit_DMA() + (++) HAL_I2S_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2S_TxCpltCallback() + (++) HAL_I2S_RxCpltCallback() + (++) HAL_I2S_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @param Timeout Timeout duration + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tmpreg_cfgr; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pTxBuffPtr = pData; + + tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) + { + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); + } + else + { + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + } + + tmpreg_cfgr = hi2s->Instance->I2SCFGR; + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Wait until TXE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + + while (hi2s->TxXferCount > 0U) + { + hi2s->Instance->DR = (*hi2s->pTxBuffPtr); + hi2s->pTxBuffPtr++; + hi2s->TxXferCount--; + + /* Wait until TXE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + + /* Check if an underrun occurs */ + if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) + { + /* Clear underrun flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + } + } + + /* Check if Slave mode is selected */ + if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) + || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX)) + { + /* Wait until Busy flag is reset */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + } + + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @param Timeout Timeout duration + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate + * in continuous way and as the I2S is not disabled at the end of the I2S transaction. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tmpreg_cfgr; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pRxBuffPtr = pData; + + tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) + { + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); + } + else + { + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + } + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Check if Master Receiver mode is selected */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) + { + /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read + access to the SPI_SR register. */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + } + + /* Receive data */ + while (hi2s->RxXferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + + (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR; + hi2s->pRxBuffPtr++; + hi2s->RxXferCount--; + + /* Check if an overrun occurs */ + if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) + { + /* Clear overrun flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + } + } + + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + uint32_t tmpreg_cfgr; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pTxBuffPtr = pData; + + tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) + { + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); + } + else + { + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + } + + /* Enable TXE and ERR interrupt */ + __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization + * between Master and Slave otherwise the I2S interrupt should be optimized. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + uint32_t tmpreg_cfgr; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pRxBuffPtr = pData; + + tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) + { + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); + } + else + { + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + } + + /* Enable RXNE and ERR interrupt */ + __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to the Transmit data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + uint32_t tmpreg_cfgr; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pTxBuffPtr = pData; + + tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) + { + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); + } + else + { + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + } + + /* Set the I2S Tx DMA Half transfer complete callback */ + hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt; + + /* Set the I2S Tx DMA transfer complete callback */ + hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt; + + /* Set the DMA error callback */ + hi2s->hdmatx->XferErrorCallback = I2S_DMAError; + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, + (uint32_t)hi2s->pTxBuffPtr, + (uint32_t)&hi2s->Instance->DR, + hi2s->TxXferSize)) + { + /* Update SPI error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + hi2s->State = HAL_I2S_STATE_READY; + + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + + /* Check if the I2S is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Check if the I2S Tx request is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Enable Tx DMA Request */ + SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + } + + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + uint32_t tmpreg_cfgr; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pRxBuffPtr = pData; + + tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) + { + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); + } + else + { + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + } + + /* Set the I2S Rx DMA Half transfer complete callback */ + hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt; + + /* Set the I2S Rx DMA transfer complete callback */ + hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt; + + /* Set the DMA error callback */ + hi2s->hdmarx->XferErrorCallback = I2S_DMAError; + + /* Check if Master Receiver mode is selected */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) + { + /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read + access to the SPI_SR register. */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + } + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, + hi2s->RxXferSize)) + { + /* Update SPI error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + hi2s->State = HAL_I2S_STATE_READY; + + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + + /* Check if the I2S is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Check if the I2S Rx request is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Enable Rx DMA Request */ + SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + } + + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Pauses the audio DMA Stream/Channel playing from the Media. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) +{ + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State == HAL_I2S_STATE_BUSY_TX) + { + /* Disable the I2S DMA Tx request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + } + else if (hi2s->State == HAL_I2S_STATE_BUSY_RX) + { + /* Disable the I2S DMA Rx request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + } + else + { + /* nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief Resumes the audio DMA Stream/Channel playing from the Media. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) +{ + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State == HAL_I2S_STATE_BUSY_TX) + { + /* Enable the I2S DMA Tx request */ + SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + } + else if (hi2s->State == HAL_I2S_STATE_BUSY_RX) + { + /* Enable the I2S DMA Rx request */ + SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + } + else + { + /* nothing to do */ + } + + /* If the I2S peripheral is still not enabled, enable it */ + if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief Stops the audio DMA Stream/Channel playing from the Media. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + /* The Lock is not implemented on this API to allow the user application + to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() + when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() + */ + + /* Disable the I2S Tx/Rx DMA requests */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Abort the I2S DMA tx Stream/Channel */ + if (hi2s->hdmatx != NULL) + { + /* Disable the I2S DMA tx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Abort the I2S DMA rx Stream/Channel */ + if (hi2s->hdmarx != NULL) + { + /* Disable the I2S DMA rx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + + hi2s->State = HAL_I2S_STATE_READY; + + return errorcode; +} + +/** + * @brief This function handles I2S interrupt request. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) +{ + uint32_t itsource = hi2s->Instance->CR2; + uint32_t itflag = hi2s->Instance->SR; + + /* I2S in mode Receiver ------------------------------------------------*/ + if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) && + (I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET)) + { + I2S_Receive_IT(hi2s); + return; + } + + /* I2S in mode Tramitter -----------------------------------------------*/ + if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET)) + { + I2S_Transmit_IT(hi2s); + return; + } + + /* I2S interrupt error -------------------------------------------------*/ + if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET) + { + /* I2S Overrun error interrupt occurred ---------------------------------*/ + if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET) + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + } + + /* I2S Underrun error interrupt occurred --------------------------------*/ + if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET) + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + } + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Tx Transfer Half completed callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Transfer completed callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer half completed callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2S error callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2S state + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL state + */ +HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) +{ + return hi2s->State; +} + +/** + * @brief Return the I2S error code + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval I2S Error Code + */ +uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) +{ + return hi2s->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2S_Private_Functions I2S Private Functions + * @{ + */ +/** + * @brief DMA I2S transmit process complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* if DMA is configured in DMA_NORMAL Mode */ + if (hdma->Init.Mode == DMA_NORMAL) + { + /* Disable Tx DMA Request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + + hi2s->TxXferCount = 0U; + hi2s->State = HAL_I2S_STATE_READY; + } + /* Call user Tx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxCpltCallback(hi2s); +#else + HAL_I2S_TxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S transmit process half complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Call user Tx half complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxHalfCpltCallback(hi2s); +#else + HAL_I2S_TxHalfCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S receive process complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* if DMA is configured in DMA_NORMAL Mode */ + if (hdma->Init.Mode == DMA_NORMAL) + { + /* Disable Rx DMA Request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + hi2s->RxXferCount = 0U; + hi2s->State = HAL_I2S_STATE_READY; + } + /* Call user Rx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->RxCpltCallback(hi2s); +#else + HAL_I2S_RxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S receive process half complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Call user Rx half complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->RxHalfCpltCallback(hi2s); +#else + HAL_I2S_RxHalfCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S communication error callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMAError(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Disable Rx and Tx DMA Request */ + CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); + hi2s->TxXferCount = 0U; + hi2s->RxXferCount = 0U; + + hi2s->State = HAL_I2S_STATE_READY; + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) +{ + /* Transmit data */ + hi2s->Instance->DR = (*hi2s->pTxBuffPtr); + hi2s->pTxBuffPtr++; + hi2s->TxXferCount--; + + if (hi2s->TxXferCount == 0U) + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + hi2s->State = HAL_I2S_STATE_READY; + /* Call user Tx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxCpltCallback(hi2s); +#else + HAL_I2S_TxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) +{ + /* Receive data */ + (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR; + hi2s->pRxBuffPtr++; + hi2s->RxXferCount--; + + if (hi2s->RxXferCount == 0U) + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + hi2s->State = HAL_I2S_STATE_READY; + /* Call user Rx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->RxCpltCallback(hi2s); +#else + HAL_I2S_RxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } +} + +/** + * @brief This function handles I2S Communication Timeout. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Timeout Duration of the timeout + * @retval HAL status + */ +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, + uint32_t Timeout) +{ + uint32_t tickstart; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until flag is set to status*/ + while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SPI_I2S_SUPPORT */ + +#endif /* HAL_I2S_MODULE_ENABLED */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_irda.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_irda.c index 6768dcff1..58aee4dc2 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_irda.c +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_irda.c @@ -113,8 +113,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback. - Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks: + Use Function HAL_IRDA_RegisterCallback() to register a user callback. + Function HAL_IRDA_RegisterCallback() allows to register following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. (+) TxCpltCallback : Tx Complete Callback. (+) RxHalfCpltCallback : Rx Half Complete Callback. @@ -129,9 +129,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default + Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. @@ -146,13 +146,13 @@ (+) MspDeInitCallback : IRDA MspDeInit. [..] - By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET + By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback(). + examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init() - and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init() + and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -161,8 +161,8 @@ in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit() - or @ref HAL_IRDA_Init() function. + using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit() + or HAL_IRDA_Init() function. [..] When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or @@ -753,28 +753,28 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD (++) HAL_IRDA_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_IRDA_Abort() - (+) HAL_IRDA_AbortTransmit() - (+) HAL_IRDA_AbortReceive() - (+) HAL_IRDA_Abort_IT() - (+) HAL_IRDA_AbortTransmit_IT() - (+) HAL_IRDA_AbortReceive_IT() + (++) HAL_IRDA_Abort() + (++) HAL_IRDA_AbortTransmit() + (++) HAL_IRDA_AbortReceive() + (++) HAL_IRDA_Abort_IT() + (++) HAL_IRDA_AbortTransmit_IT() + (++) HAL_IRDA_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_IRDA_AbortCpltCallback() - (+) HAL_IRDA_AbortTransmitCpltCallback() - (+) HAL_IRDA_AbortReceiveCpltCallback() + (++) HAL_IRDA_AbortCpltCallback() + (++) HAL_IRDA_AbortTransmitCpltCallback() + (++) HAL_IRDA_AbortReceiveCpltCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. @endverbatim * @{ diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c index 873f9630c..df3c8bf1a 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c @@ -174,7 +174,6 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ /** @addtogroup LPTIM_Private_Constants * @{ */ @@ -183,6 +182,25 @@ * @} */ +/* Private macro -------------------------------------------------------------*/ +/** @addtogroup LPTIM_Private_Macros + * @{ + */ +#if defined(LPTIM2) +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) \ + (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT()) + +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(__INSTANCE__) \ + (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT()) +#else +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() + +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(__INSTANCE__) __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() +#endif /* LPTIM2 */ +/** + * @} + */ + /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) @@ -235,17 +253,20 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); - if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) { assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); - assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); } assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { - assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); } + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) + { + assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); + assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); + } assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource)); @@ -278,13 +299,17 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; - if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL)) + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL)); } - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL)); + } + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) + { + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT)); } /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ @@ -298,18 +323,28 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) hlptim->Init.UpdateMode | hlptim->Init.CounterSource); - if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL)) + /* Glitch filters for internal triggers and external inputs are configured + * only if an internal clock source is provided to the LPTIM + */ + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) { - tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | + tmpcfgr |= (hlptim->Init.Trigger.SampleTime | hlptim->Init.UltraLowPowerClock.SampleTime); } - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + /* Configure the active edge or edges used by the counter only if LPTIM is + * clocked by an external clock source + */ + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + { + tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity); + } + + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable External trigger and set the trigger source */ - tmpcfgr |= (hlptim->Init.Trigger.Source | - hlptim->Init.Trigger.ActiveEdge | - hlptim->Init.Trigger.SampleTime); + tmpcfgr |= (hlptim->Init.Trigger.Source | + hlptim->Init.Trigger.ActiveEdge); } /* Write to LPTIMx CFGR */ @@ -1438,6 +1473,9 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Set the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance); + /* Set TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; @@ -1505,6 +1543,9 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Set the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(hlptim->Instance); + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -1620,6 +1661,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Set the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance); + /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { @@ -1684,6 +1728,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Set the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(hlptim->Instance); + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -2304,17 +2351,17 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t { HAL_StatusTypeDef result = HAL_OK; uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL); - do + do + { + count--; + if (count == 0UL) { - count--; - if (count == 0UL) - { - result = HAL_TIMEOUT; - } + result = HAL_TIMEOUT; } - while((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); + } + while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); - return result; + return result; } /** @@ -2341,16 +2388,16 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) /* Save LPTIM source clock */ switch ((uint32_t)hlptim->Instance) { - case LPTIM1_BASE: - tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE(); - break; + case LPTIM1_BASE: + tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE(); + break; #if defined(LPTIM2) - case LPTIM2_BASE: - tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE(); - break; + case LPTIM2_BASE: + tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE(); + break; #endif /* LPTIM2 */ - default: - break; + default: + break; } /* Save LPTIM configuration registers */ @@ -2363,18 +2410,18 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) /*********** Reset LPTIM ***********/ switch ((uint32_t)hlptim->Instance) { - case LPTIM1_BASE: - __HAL_RCC_LPTIM1_FORCE_RESET(); - __HAL_RCC_LPTIM1_RELEASE_RESET(); - break; + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_FORCE_RESET(); + __HAL_RCC_LPTIM1_RELEASE_RESET(); + break; #if defined(LPTIM2) - case LPTIM2_BASE: - __HAL_RCC_LPTIM2_FORCE_RESET(); - __HAL_RCC_LPTIM2_RELEASE_RESET(); - break; + case LPTIM2_BASE: + __HAL_RCC_LPTIM2_FORCE_RESET(); + __HAL_RCC_LPTIM2_RELEASE_RESET(); + break; #endif /* LPTIM2 */ - default: - break; + default: + break; } /*********** Restore LPTIM Config ***********/ @@ -2383,16 +2430,16 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) /* Force LPTIM source kernel clock from APB */ switch ((uint32_t)hlptim->Instance) { - case LPTIM1_BASE: - __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1); - break; + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1); + break; #if defined(LPTIM2) - case LPTIM2_BASE: - __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_PCLK1); - break; + case LPTIM2_BASE: + __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_PCLK1); + break; #endif /* LPTIM2 */ - default: - break; + default: + break; } if (tmpCMP != 0UL) @@ -2427,16 +2474,16 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) /* Restore LPTIM source kernel clock */ switch ((uint32_t)hlptim->Instance) { - case LPTIM1_BASE: - __HAL_RCC_LPTIM1_CONFIG(tmpclksource); - break; + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_CONFIG(tmpclksource); + break; #if defined(LPTIM2) - case LPTIM2_BASE: - __HAL_RCC_LPTIM2_CONFIG(tmpclksource); - break; + case LPTIM2_BASE: + __HAL_RCC_LPTIM2_CONFIG(tmpclksource); + break; #endif /* LPTIM2 */ - default: - break; + default: + break; } } diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pka.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pka.c index cf93e7ce5..f4ef20712 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pka.c +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pka.c @@ -1770,46 +1770,7 @@ uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb) { uint32_t position; -#if defined(CORE_CM0PLUS) - if (msb > 0x7FU) - { - position = 8UL; - } - else if (msb > 0x3FU) - { - position = 7UL; - } - else if (msb > 0x1FU) - { - position = 6UL; - } - else if (msb > 0x0FU) - { - position = 5UL; - } - else if (msb > 0x07U) - { - position = 4UL; - } - else if (msb > 0x03U) - { - position = 3UL; - } - else if (msb > 0x01U) - { - position = 2UL; - } - else if (msb > 0x00U) - { - position = 1UL; - } - else - { - position = 0UL; - } -#else position = 32UL - __CLZ(msb); -#endif return (((byteNumber - 1UL) * 8UL) + position); } diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c index c6f2c02fd..79a4d417c 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c @@ -76,7 +76,9 @@ #define LSI2_TIMEOUT_VALUE (3U) /* to be adjusted with DS */ #define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ #define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#if defined(SAI1) #define PLLSAI1_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#endif #define PRESCALER_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ #define LATENCY_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ @@ -272,6 +274,9 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) /* Get Start Tick*/ tickstart = HAL_GetTick(); + /* MSI PLL OFF */ + LL_RCC_MSI_DisablePLLMode(); + /* Set MSION bit */ LL_RCC_MSI_Enable(); @@ -378,6 +383,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) * @param RCC_OscInitStruct pointer to a @ref RCC_OscInitTypeDef structure that * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. + * @note The PLL source is not updated when used as PLLSAI1 clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) @@ -860,66 +866,126 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) + if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) { - /* Check if the PLL is used as system clock or not */ - if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + const uint32_t temp_pllconfig = RCC->PLLCFGR; + + /* PLL On ? */ + if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) { - if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + + /* Do nothing if PLL configuration is unchanged */ + if ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) || + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) { - /* Check the parameters */ - assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); - assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); - assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); - assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); - assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); - - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while (LL_RCC_PLL_IsReady() != 0U) + /* Check if the PLL is used as system clock or not */ + if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK) { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) +#if defined(SAI1) + /* Check if main PLL can be updated */ + /* Not possible if the source is shared by other enabled PLLSAIx */ + if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U) + { - return HAL_TIMEOUT; + return HAL_ERROR; + } + else +#endif + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLM, + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } } } + else + { + /* PLL is already used as System core clock */ + return HAL_ERROR; + } + } + else + { + /* PLL configuration is unchanged */ + /* Re-enable PLL if it was disabled (ie. low power mode) */ + if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + { + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); - /* Configure the main PLL clock source, multiplication and division factors. */ - __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - RCC_OscInitStruct->PLL.PLLM, - RCC_OscInitStruct->PLL.PLLN, - RCC_OscInitStruct->PLL.PLLP, - RCC_OscInitStruct->PLL.PLLQ, - RCC_OscInitStruct->PLL.PLLR); - - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); - - /* Enable PLL System Clock output. */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); - /* Get Start Tick*/ - tickstart = HAL_GetTick(); + /* Get Start Tick*/ + tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ - while (LL_RCC_PLL_IsReady() == 0U) - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) { - return HAL_TIMEOUT; + if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } } } } - else + } + else + { + /* Check that PLL is not used as system clock or not */ + if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK) { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); + /* Disable all PLL outputs to save power */ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSOURCE_NONE); @@ -932,9 +998,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait till PLL is disabled */ - while (LL_RCC_PLL_IsReady() != 0U) + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { @@ -942,28 +1008,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } } - } - else - { - /* Check if there is a request to disable the PLL used as System clock source */ - if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) - { - return HAL_ERROR; - } else { - /* Do not return HAL_ERROR if request repeats the current configuration */ - uint32_t pllcfgr = RCC->PLLCFGR; - - if ((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || - ((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) || - (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || - (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || - (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) - { - return HAL_ERROR; - } + /* PLL is already used as System core clock */ + return HAL_ERROR; } } } @@ -1302,7 +1350,8 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); } - else +#if defined(RCC_MCO3_SUPPORT) + else if (RCC_MCOx == RCC_MCO3) { /* MCO3 Clock Enable */ __MCO3_CLK_ENABLE(); @@ -1311,6 +1360,11 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M GPIO_InitStruct.Alternate = GPIO_AF6_MCO; HAL_GPIO_Init(MCO3_GPIO_PORT, &GPIO_InitStruct); } +#endif + else + { + ; + } /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ LL_RCC_ConfigMCO(RCC_MCOSource, RCC_MCODiv); diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c index 968e90f51..49d4943bb 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c @@ -42,7 +42,9 @@ /** @defgroup RCCEx_Private_Constants RCCEx Private Constants * @{ */ +#if defined(SAI1) #define PLLSAI1_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#endif #define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ #define CLOCKSMPS_TIMEOUT_VALUE (5000U) /* 5 s */ @@ -55,9 +57,11 @@ #define LSCO2_GPIO_PORT GPIOH #define LSCO2_PIN GPIO_PIN_3 +#if defined(RCC_LSCO3_SUPPORT) #define __LSCO3_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() #define LSCO3_GPIO_PORT GPIOC #define LSCO3_PIN GPIO_PIN_12 +#endif #define LSI2_TIMEOUT_VALUE (3U) /* to be adjusted with DS */ @@ -128,16 +132,14 @@ static uint32_t RCC_PLLSAI1_GetFreqDomain_Q(void); * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock - * * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock - * * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock - * * @arg @ref RCC_PERIPHCLK_RFWAKEUP RFWKP peripheral clock * @arg @ref RCC_PERIPHCLK_SMPS SMPS peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock * * * @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select @@ -170,12 +172,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* SAI1 clock source config set later after clock selection check */ break; +#if defined(SAI1) case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1 */ /* PLLSAI1 parameters N & P configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_ConfigNP(&(PeriphClkInit->PLLSAI1)); /* SAI1 clock source config set later after clock selection check */ break; - +#endif case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/ /* SAI1 clock source config set later after clock selection check */ @@ -325,6 +328,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } #endif +#if defined(USB) /*-------------------------- USB clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) { @@ -336,21 +340,21 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Enable PLLQ output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_USBCLK); } - #if defined(SAI1) - if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) - { - /* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1)); + if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) + { + /* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */ + ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1)); - if (ret != HAL_OK) - { - /* set overall return value */ - status = ret; - } + if (ret != HAL_OK) + { + /* set overall return value */ + status = ret; } + } #endif } +#endif /*-------------------------- RNG clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) @@ -384,17 +388,17 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } #if defined(SAI1) - if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) - { - /* PLLSAI1 parameters N & R configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_ConfigNR(&(PeriphClkInit->PLLSAI1)); + if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) + { + /* PLLSAI1 parameters N & R configuration and clock output (PLLSAI1ClockOut) */ + ret = RCCEx_PLLSAI1_ConfigNR(&(PeriphClkInit->PLLSAI1)); - if (ret != HAL_OK) - { - /* set overall return value */ - status = ret; - } + if (ret != HAL_OK) + { + /* set overall return value */ + status = ret; } + } #endif } @@ -425,6 +429,24 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } #endif +#if defined(SPI_I2S_SUPPORT) + /*-------------------- I2S clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + + /* Configure the I2S clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + + if (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL) + { + /* Enable RCC_PLL_I2SCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_I2SCLK); + } + } +#endif + return status; } @@ -434,7 +456,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * returns the configuration information for the Extended Peripherals * clocks(SAI1, LPTIM1, LPTIM2, I2C1, I2C3, LPUART1, - * USART1, RTC, ADCx, USB, RNG, RFWKP, SMPS). + * USART1, RTC, ADCx, USB, RNG, RFWKP, SMPS, I2S). * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) @@ -457,12 +479,18 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI1; #endif +#if defined(USB) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; +#endif #if defined(RCC_SMPS_SUPPORT) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SMPS; #endif +#if defined(SPI_I2S_SUPPORT) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S; +#endif + #if defined(SAI1) /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/ PeriphClkInit->PLLSAI1.PLLN = LL_RCC_PLLSAI1_GetN(); @@ -501,8 +529,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the RTC clock source ------------------------------------------------*/ PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); +#if defined(USB) /* Get the USB clock source ------------------------------------------------*/ PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); +#endif /* Get the RNG clock source ------------------------------------------------*/ PeriphClkInit->RngClockSelection = HAL_RCCEx_GetRngCLKSource(); @@ -520,6 +550,11 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the SMPS clock source -----------------------------------------------*/ PeriphClkInit->SmpsClockSelection = __HAL_RCC_GET_SMPS_SOURCE(); #endif + +#if defined(SPI_I2S_SUPPORT) + /* Get the I2S clock source -----------------------------------------------*/ + PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE(); +#endif } /** @@ -538,26 +573,26 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - * * @arg @ref RCC_PERIPHCLK_RFWAKEUP RFWKP peripheral clock * @arg @ref RCC_PERIPHCLK_SMPS SMPS peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock * @retval Frequency in Hz */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { - uint32_t frequency; - + uint32_t frequency = 0U; + #if defined(RCC_SMPS_SUPPORT) uint32_t smps_prescaler_index = ((LL_RCC_GetSMPSPrescaler()) >> RCC_SMPSCR_SMPSDIV_Pos); #endif - + /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); - + if (PeriphClk == RCC_PERIPHCLK_RTC) { uint32_t rtcClockSource = LL_RCC_GetRTCClockSource(); - + if (rtcClockSource == LL_RCC_RTC_CLKSOURCE_LSE) /* LSE clock used as RTC clock source */ { if (LL_RCC_LSE_IsReady() == 1U) @@ -566,7 +601,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (rtcClockSource == LL_RCC_RTC_CLKSOURCE_LSI) /* LSI clock used as RTC clock source */ @@ -579,7 +614,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (rtcClockSource == LL_RCC_RTC_CLKSOURCE_HSE_DIV32) /* HSE clock used as RTC clock source */ @@ -588,7 +623,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else /* No clock used as RTC clock source */ { - frequency = 0; + /* Nothing to do as frequency already initialized to 0U */ } } #if defined(SAI1) @@ -596,49 +631,51 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { switch (LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE)) { - case LL_RCC_SAI1_CLKSOURCE_HSI: /* HSI clock used as SAI1 clock source */ - if (LL_RCC_HSI_IsReady() == 1U) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; - - case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */ - if (LL_RCC_PLLSAI1_IsReady() == 1U) - { - frequency = RCC_PLLSAI1_GetFreqDomain_P(); - } - else - { - frequency = 0U; - } - break; - - case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */ - if (LL_RCC_PLL_IsReady() == 1U) - { - frequency = RCC_PLL_GetFreqDomain_P(); - } - else - { - frequency = 0U; - } - break; - - default: /* External input clock used as SAI1 clock source */ - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - break; + case LL_RCC_SAI1_CLKSOURCE_HSI: /* HSI clock used as SAI1 clock source */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + +#if defined(SAI1) + case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */ + if (LL_RCC_PLLSAI1_IsReady() == 1U) + { + frequency = RCC_PLLSAI1_GetFreqDomain_P(); + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif + + case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */ + if (LL_RCC_PLL_IsReady() == 1U) + { + frequency = RCC_PLL_GetFreqDomain_P(); + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + + default: /* External input clock used as SAI1 clock source */ + frequency = EXTERNAL_SAI1_CLOCK_VALUE; + break; } } #endif else if (PeriphClk == RCC_PERIPHCLK_RNG) { uint32_t rngClockSource = HAL_RCCEx_GetRngCLKSource(); - + if (rngClockSource == RCC_RNGCLKSOURCE_LSI) /* LSI clock used as RNG clock source */ { const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady(); @@ -649,7 +686,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (rngClockSource == RCC_RNGCLKSOURCE_LSE) /* LSE clock used as RNG clock source */ @@ -660,7 +697,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (rngClockSource == RCC_RNGCLKSOURCE_PLL) /* PLL clock divided by 3 used as RNG clock source */ @@ -671,7 +708,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (rngClockSource == RCC_RNGCLKSOURCE_MSI) /* MSI clock divided by 3 used as RNG clock source */ @@ -682,7 +719,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else /* HSI48 clock divided by 3 used as RNG clock source */ @@ -693,95 +730,97 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } } +#if defined(USB) else if (PeriphClk == RCC_PERIPHCLK_USB) { switch (LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE)) { #if defined(SAI1) - case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */ - if (LL_RCC_PLLSAI1_IsReady() == 1U) - { - frequency = RCC_PLLSAI1_GetFreqDomain_Q(); - } - else - { - frequency = 0U; - } - break; + case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */ + if (LL_RCC_PLLSAI1_IsReady() == 1U) + { + frequency = RCC_PLLSAI1_GetFreqDomain_Q(); + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; #endif - case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ - if (LL_RCC_PLL_IsReady() == 1U) - { - frequency = RCC_PLL_GetFreqDomain_Q(); - } - else - { - frequency = 0U; - } - break; - - case LL_RCC_USB_CLKSOURCE_MSI: /* MSI clock used as USB clock source */ - if (LL_RCC_MSI_IsReady() == 1U) - { - frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); - } - else - { - frequency = 0U; - } - break; - - default: /* HSI48 clock used as USB clock source */ - if (LL_RCC_HSI48_IsReady() == 1U) - { - frequency = HSI48_VALUE; - } - else - { - frequency = 0U; - } - break; + + case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ + if (LL_RCC_PLL_IsReady() == 1U) + { + frequency = RCC_PLL_GetFreqDomain_Q(); + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + + case LL_RCC_USB_CLKSOURCE_MSI: /* MSI clock used as USB clock source */ + if (LL_RCC_MSI_IsReady() == 1U) + { + frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + + default: /* HSI48 clock used as USB clock source */ + if (LL_RCC_HSI48_IsReady() == 1U) + { + frequency = HSI48_VALUE; + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; } } - +#endif else if (PeriphClk == RCC_PERIPHCLK_USART1) { switch (LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE)) { - case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ - frequency = HAL_RCC_GetSysClockFreq(); - break; - - case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady() == 1U) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; - - case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady() == 1U) - { - frequency = LSE_VALUE; - } - else - { - frequency = 0U; - } - break; - - default: /* USART1 Clock is PCLK2 */ - frequency = __LL_RCC_CALC_PCLK2_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ - LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB2Prescaler()); - break; + case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + + case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + frequency = LSE_VALUE; + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + + default: /* USART1 Clock is PCLK2 */ + frequency = __LL_RCC_CALC_PCLK2_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ + LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB2Prescaler()); + break; } } #if defined(LPUART1) @@ -789,36 +828,36 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { switch (LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE)) { - case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */ - frequency = HAL_RCC_GetSysClockFreq(); - break; - - case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady() == 1U) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; - - case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady() == 1U) - { - frequency = LSE_VALUE; - } - else - { - frequency = 0U; - } - break; - - default: /* LPUART1 Clock is PCLK1 */ - frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ - LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler()); - break; + case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */ + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + frequency = LSE_VALUE; + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + + default: /* LPUART1 Clock is PCLK1 */ + frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ + LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler()); + break; } } #endif @@ -826,61 +865,71 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { switch (LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE)) { -#if defined(SAI1) - case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */ - if (LL_RCC_PLLSAI1_IsReady() == 1U) - { - frequency = RCC_PLLSAI1_GetFreqDomain_R(); - } - else - { - frequency = 0U; - } - break; +#if defined(STM32WB55xx) || defined (STM32WB5Mxx) + case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */ + if (LL_RCC_PLLSAI1_IsReady() == 1U) + { + frequency = RCC_PLLSAI1_GetFreqDomain_R(); + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#elif defined(STM32WB35xx) + case LL_RCC_ADC_CLKSOURCE_HSI: /* HSI clock used as ADC clock source */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; #endif - case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */ - frequency = HAL_RCC_GetSysClockFreq(); - break; - - case LL_RCC_ADC_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ - if (LL_RCC_PLL_IsReady() == 1U) - { - frequency = RCC_PLL_GetFreqDomain_P(); - } - else - { - frequency = 0U; - } - break; - - default: /* No clock used as ADC clock source */ - frequency = 0; - break; + case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */ + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case LL_RCC_ADC_CLKSOURCE_PLL: /* PLL clock used as ADC clock source */ + if (LL_RCC_PLL_IsReady() == 1U) + { + frequency = RCC_PLL_GetFreqDomain_P(); + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + + default: /* No clock used as ADC clock source */ + break; } } else if (PeriphClk == RCC_PERIPHCLK_I2C1) { switch (LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE)) { - case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ - frequency = HAL_RCC_GetSysClockFreq(); - break; - - case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady() == 1U) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; - - default: /* I2C1 Clock is PCLK1 */ - frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ - LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler()); - break; + case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + + default: /* I2C1 Clock is PCLK1 */ + frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ + LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler()); + break; } } #if defined(I2C3) @@ -888,32 +937,32 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { switch (LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE)) { - case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */ - frequency = HAL_RCC_GetSysClockFreq(); - break; - - case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady() == 1U) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; - - default: /* I2C3 Clock is PCLK1 */ - frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ - LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler()); - break; + case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */ + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + + default: /* I2C3 Clock is PCLK1 */ + frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ + LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler()); + break; } } #endif else if (PeriphClk == RCC_PERIPHCLK_LPTIM1) { uint32_t lptimClockSource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE); - + if (lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_LSI) /* LPTIM1 Clock is LSI Osc. */ { const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady(); @@ -924,7 +973,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_HSI) /* LPTIM1 Clock is HSI Osc. */ @@ -935,7 +984,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_LSE) /* LPTIM1 Clock is LSE Osc. */ @@ -946,7 +995,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else /* LPTIM1 Clock is PCLK1 */ @@ -957,7 +1006,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) else if (PeriphClk == RCC_PERIPHCLK_LPTIM2) { uint32_t lptimClockSource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE); - + if (lptimClockSource == LL_RCC_LPTIM2_CLKSOURCE_LSI) /* LPTIM2 Clock is LSI Osc. */ { const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady(); @@ -968,7 +1017,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (lptimClockSource == LL_RCC_LPTIM2_CLKSOURCE_HSI) /* LPTIM2 Clock is HSI Osc. */ @@ -979,7 +1028,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (lptimClockSource == LL_RCC_LPTIM2_CLKSOURCE_LSE) /* LPTIM2 Clock is LSE Osc. */ @@ -990,7 +1039,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else /* LPTIM2 Clock is PCLK1 */ @@ -1001,7 +1050,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) else if (PeriphClk == RCC_PERIPHCLK_RFWAKEUP) { uint32_t rfwkpClockSource = LL_RCC_GetRFWKPClockSource(); - + if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_LSE) /* LSE clock used as RF Wakeup clock source */ { if (LL_RCC_LSE_IsReady() == 1U) @@ -1010,7 +1059,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_LSI) /* LSI clock used as RF Wakeup clock source */ @@ -1023,7 +1072,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024) /* HSE clock used as RF Wakeup clock source */ @@ -1032,14 +1081,14 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else /* No clock used as RF Wakeup clock source */ { - frequency = 0; + /* Nothing to do as frequency already initialized to 0U */ } } #if defined(RCC_SMPS_SUPPORT) else if (PeriphClk == RCC_PERIPHCLK_SMPS) { uint32_t smpsClockSource = LL_RCC_GetSMPSClockSource(); - + if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSI) /* SMPS Clock source is HSI Osc. */ { if (LL_RCC_HSI_IsReady() == 1U) @@ -1049,7 +1098,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSE) /* SMPS Clock source is HSE Osc. */ @@ -1061,41 +1110,62 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_MSI) /* SMPS Clock source is MSI Osc. */ { switch (LL_RCC_MSI_GetRange()) { - case LL_RCC_MSIRANGE_8: - frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_8) / SmpsPrescalerTable[smps_prescaler_index][4]; - break; - case LL_RCC_MSIRANGE_9: - frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_9) / SmpsPrescalerTable[smps_prescaler_index][3]; - break; - case LL_RCC_MSIRANGE_10: - frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_10) / SmpsPrescalerTable[smps_prescaler_index][2]; - break; - case LL_RCC_MSIRANGE_11: - frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_11) / SmpsPrescalerTable[smps_prescaler_index][1]; - break; - default: - frequency = 0U; - break; + case LL_RCC_MSIRANGE_8: + frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_8) / SmpsPrescalerTable[smps_prescaler_index][4]; + break; + case LL_RCC_MSIRANGE_9: + frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_9) / SmpsPrescalerTable[smps_prescaler_index][3]; + break; + case LL_RCC_MSIRANGE_10: + frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_10) / SmpsPrescalerTable[smps_prescaler_index][2]; + break; + case LL_RCC_MSIRANGE_11: + frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_11) / SmpsPrescalerTable[smps_prescaler_index][1]; + break; + default: + break; } frequency = frequency >> 1U; /* Systematic Div by 2 */ } else /* SMPS has no Clock */ { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } #endif - else +#if defined(SPI_I2S_SUPPORT) + if (PeriphClk == RCC_PERIPHCLK_I2S) { - frequency = 0U; + switch (LL_RCC_GetI2SClockSource(LL_RCC_I2S_CLKSOURCE)) + { + case LL_RCC_I2S_CLKSOURCE_PIN: /* I2S Clock is External clock */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_I2S_CLKSOURCE_HSI: /* I2S Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + break; + + case LL_RCC_I2S_CLKSOURCE_PLL: /* I2S Clock is PLL */ + frequency = RCC_PLL_GetFreqDomain_P(); + break; + + case LL_RCC_I2S_CLKSOURCE_NONE: /* No clock used as I2S clock source */ + default: + break; + } } +#endif return (frequency); } @@ -1334,7 +1404,7 @@ __weak void HAL_RCCEx_LSECSS_Callback(void) * @note PA2, PH3 or PC12 should be configured in alternate function mode. * @param RCC_LSCOx specifies the output direction for the clock source. * @arg @ref RCC_LSCO1 Clock source to output on LSCO1 pin(PA2) - * @arg @ref RCC_LSCO2 Clock source to output on LSCO2 pin(PH13) + * @arg @ref RCC_LSCO2 Clock source to output on LSCO2 pin(PH3) * @arg @ref RCC_LSCO3 Clock source to output on LSCO3 pin(PC12) * @param RCC_LSCOSource specifies the clock source to output. * This parameter can be one of the following values: @@ -1378,7 +1448,8 @@ void HAL_RCCEx_LSCOConfig(uint32_t RCC_LSCOx, uint32_t RCC_LSCOSource) HAL_GPIO_Init(LSCO2_GPIO_PORT, &GPIO_InitStruct); } - else +#if defined(RCC_LSCO3_SUPPORT) + else if (RCC_LSCOx == RCC_LSCO3) { /* LSCO3 Clock Enable */ __LSCO3_CLK_ENABLE(); @@ -1387,6 +1458,11 @@ void HAL_RCCEx_LSCOConfig(uint32_t RCC_LSCOx, uint32_t RCC_LSCOSource) GPIO_InitStruct.Alternate = GPIO_AF6_LSCO; HAL_GPIO_Init(LSCO3_GPIO_PORT, &GPIO_InitStruct); } +#endif + else + { + ; + } /* Update LSCOSEL clock source in Backup Domain control register */ if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smartcard.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smartcard.c index a24a035a0..6f38d0c42 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smartcard.c +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smartcard.c @@ -107,8 +107,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback. - Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: + Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback. + Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: (+) TxCpltCallback : Tx Complete Callback. (+) RxCpltCallback : Rx Complete Callback. (+) ErrorCallback : Error Callback. @@ -123,9 +123,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default + Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxCpltCallback : Tx Complete Callback. @@ -140,13 +140,13 @@ (+) MspDeInitCallback : SMARTCARD MspDeInit. [..] - By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET + By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback(). + examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init() - and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init() + and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -155,8 +155,8 @@ in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit() - or @ref HAL_SMARTCARD_Init() function. + using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit() + or HAL_SMARTCARD_Init() function. [..] When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or @@ -722,59 +722,59 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. [..] - (+) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. + (#) There are two modes of transfer: + (##) Blocking mode: The communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. - (++) Non-Blocking mode: The communication is performed using Interrupts + (##) Non-Blocking mode: The communication is performed using Interrupts or DMA, the relevant API's return the HAL status. The end of the data processing will be indicated through the dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. - (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks + (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks will be executed respectively at the end of the Transmit or Receive process The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected. - (+) Blocking mode APIs are : - (++) HAL_SMARTCARD_Transmit() - (++) HAL_SMARTCARD_Receive() + (#) Blocking mode APIs are : + (##) HAL_SMARTCARD_Transmit() + (##) HAL_SMARTCARD_Receive() - (+) Non Blocking mode APIs with Interrupt are : - (++) HAL_SMARTCARD_Transmit_IT() - (++) HAL_SMARTCARD_Receive_IT() - (++) HAL_SMARTCARD_IRQHandler() + (#) Non Blocking mode APIs with Interrupt are : + (##) HAL_SMARTCARD_Transmit_IT() + (##) HAL_SMARTCARD_Receive_IT() + (##) HAL_SMARTCARD_IRQHandler() - (+) Non Blocking mode functions with DMA are : - (++) HAL_SMARTCARD_Transmit_DMA() - (++) HAL_SMARTCARD_Receive_DMA() + (#) Non Blocking mode functions with DMA are : + (##) HAL_SMARTCARD_Transmit_DMA() + (##) HAL_SMARTCARD_Receive_DMA() - (+) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_SMARTCARD_TxCpltCallback() - (++) HAL_SMARTCARD_RxCpltCallback() - (++) HAL_SMARTCARD_ErrorCallback() + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (##) HAL_SMARTCARD_TxCpltCallback() + (##) HAL_SMARTCARD_RxCpltCallback() + (##) HAL_SMARTCARD_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_SMARTCARD_Abort() - (+) HAL_SMARTCARD_AbortTransmit() - (+) HAL_SMARTCARD_AbortReceive() - (+) HAL_SMARTCARD_Abort_IT() - (+) HAL_SMARTCARD_AbortTransmit_IT() - (+) HAL_SMARTCARD_AbortReceive_IT() + (##) HAL_SMARTCARD_Abort() + (##) HAL_SMARTCARD_AbortTransmit() + (##) HAL_SMARTCARD_AbortReceive() + (##) HAL_SMARTCARD_Abort_IT() + (##) HAL_SMARTCARD_AbortTransmit_IT() + (##) HAL_SMARTCARD_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_SMARTCARD_AbortCpltCallback() - (+) HAL_SMARTCARD_AbortTransmitCpltCallback() - (+) HAL_SMARTCARD_AbortReceiveCpltCallback() + (##) HAL_SMARTCARD_AbortCpltCallback() + (##) HAL_SMARTCARD_AbortTransmitCpltCallback() + (##) HAL_SMARTCARD_AbortReceiveCpltCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted. This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode. Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c index eeec81284..ce7a1e8da 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c @@ -2625,10 +2625,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini } /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); @@ -2791,7 +2791,7 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Enable the encoder interface channels */ switch (Channel) @@ -2835,7 +2835,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -2881,7 +2881,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Enable the encoder interface channels */ /* Enable the capture compare Interrupts 1 and/or 2 */ @@ -2931,7 +2931,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -2986,7 +2986,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch uint32_t *pData2, uint16_t Length) { /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); if (htim->State == HAL_TIM_STATE_BUSY) { @@ -3120,7 +3120,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c index 11954768b..e70227cb9 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c @@ -32,12 +32,11 @@ (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: - (++) Counter min (T[5;0] = 0x00) @64 MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 64s - (++) Counter max (T[5;0] = 0x3F) @64 MHz (PCLK1) with prescaler dividing by 128: + (++) Counter min (T[5;0] = 0x00) at 64 MHz (PCLK1) with zero prescaler: + max timeout before reset: approximately 64us + (++) Counter max (T[5;0] = 0x3F) at 64 MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 524.28ms - ============================================================================== ##### How to use this driver ##### ============================================================================== @@ -67,26 +66,26 @@ [..] The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions - @ref HAL_WWDG_RegisterCallback() to register a user callback. + HAL_WWDG_RegisterCallback() to register a user callback. - (+) Function @ref HAL_WWDG_RegisterCallback() allows to register following + (+) Function HAL_WWDG_RegisterCallback() allows to register following callbacks: (++) EwiCallback : callback for Early WakeUp Interrupt. (++) MspInitCallback : WWDG MspInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - (+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to - the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback() + (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to + the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback() takes as parameters the HAL peripheral handle and the Callback ID. This function allows to reset following callbacks: (++) EwiCallback : callback for Early WakeUp Interrupt. (++) MspInitCallback : WWDG MspInit. [..] - When calling @ref HAL_WWDG_Init function, callbacks are reset to the + When calling HAL_WWDG_Init function, callbacks are reset to the corresponding legacy weak (surcharged) functions: - @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have + HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have not been registered before. [..] diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c index 09853b4d2..daf9f6ae2 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c @@ -190,9 +190,6 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru if (currentpin != 0x00u) { - /* Pin Mode configuration */ - LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) { /* Check Speed mode parameters */ @@ -200,6 +197,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru /* Speed mode configuration */ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType); } /* Pull-up Pull down resistor configuration*/ @@ -220,19 +223,13 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); } } + + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); } pinpos++; } - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) - { - /* Check Output mode parameters */ - assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); - - /* Output mode configuration*/ - LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); - - } return (SUCCESS); } diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lptim.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lptim.c index 16cde97df..ea02936b2 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lptim.c +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lptim.c @@ -207,16 +207,16 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) /* Save LPTIM source clock */ switch ((uint32_t)LPTIMx) { - case LPTIM1_BASE: - tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE); - break; + case LPTIM1_BASE: + tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE); + break; #if defined(LPTIM2) - case LPTIM2_BASE: - tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE); - break; + case LPTIM2_BASE: + tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE); + break; #endif /* LPTIM2 */ - default: - break; + default: + break; } /* Save LPTIM configuration registers */ @@ -237,16 +237,16 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) /* Force LPTIM source kernel clock from APB */ switch ((uint32_t)LPTIMx) { - case LPTIM1_BASE: - LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1); - break; + case LPTIM1_BASE: + LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1); + break; #if defined(LPTIM2) - case LPTIM2_BASE: - LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK1); - break; + case LPTIM2_BASE: + LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK1); + break; #endif /* LPTIM2 */ - default: - break; + default: + break; } if (tmpCMP != 0UL) @@ -259,7 +259,8 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } + while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_CMPOK(LPTIMx); } @@ -274,7 +275,8 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } + while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_ARROK(LPTIMx); } diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c index 1a964c467..23aa838de 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c @@ -72,6 +72,9 @@ #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE)) +#if defined(SPI_I2S_SUPPORT) +#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE) +#endif /** * @} */ @@ -81,7 +84,9 @@ * @{ */ uint32_t RCC_PLL_GetFreqDomain_SYS(void); +#if defined(SAI1) uint32_t RCC_PLL_GetFreqDomain_SAI(void); +#endif uint32_t RCC_PLL_GetFreqDomain_ADC(void); uint32_t RCC_PLL_GetFreqDomain_48M(void); @@ -91,6 +96,10 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void); uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void); #endif +#if defined(SPI_I2S_SUPPORT) +uint32_t RCC_PLL_GetFreqDomain_I2S(void); +#endif + uint32_t RCC_GetSystemClockFreq(void); @@ -349,7 +358,6 @@ uint32_t LL_RCC_GetSMPSClockFreq(void) return smps_frequency; } - #endif /** @@ -616,12 +624,15 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) } break; +#if defined(SAI1) case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */ if (LL_RCC_PLLSAI1_IsReady() == 1U) { sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI(); } break; +#endif + case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */ if (LL_RCC_PLL_IsReady() == 1U) { @@ -775,7 +786,7 @@ uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) adc_frequency = RCC_GetSystemClockFreq(); break; - case LL_RCC_ADC_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ + case LL_RCC_ADC_CLKSOURCE_PLL: /* PLL clock used as ADC clock source */ if (LL_RCC_PLL_IsReady() == 1U) { adc_frequency = RCC_PLL_GetFreqDomain_ADC(); @@ -874,6 +885,46 @@ uint32_t LL_RCC_GetRFWKPClockFreq(void) return rfwkp_frequency; } +#if defined(SPI_I2S_SUPPORT) +/** + * @brief Return I2Sx clock frequency + * @param I2SxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S_CLKSOURCE + * @retval I2S clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) or PLLs (PLL) is not ready + */ +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource) +{ + uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource)); + + /* I2SCLK clock frequency */ + switch (LL_RCC_GetI2SClockSource(I2SxSource)) + { + case LL_RCC_I2S_CLKSOURCE_PLL: /* I2S2 Clock is PLL"P" */ + if (LL_RCC_PLL_IsReady() == 1U) + { + i2s_frequency = RCC_PLL_GetFreqDomain_I2S(); + } + break; + + case LL_RCC_I2S_CLKSOURCE_PIN: /* I2S2 Clock is External clock */ + i2s_frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_I2S_CLKSOURCE_HSI: /* HSI clock used as I2S clock source */ + default: + if (LL_RCC_HSI_IsReady() == 1U) + { + i2s_frequency = HSI_VALUE; + } + break; + } + return i2s_frequency; +} +#endif /** * @} @@ -1312,6 +1363,36 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) } #endif +#if defined(SPI_I2S_SUPPORT) +/** + * @brief Return PLL clock frequency used for I2S domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_I2S(void) +{ + uint32_t pllinputfreq, pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + I2S Domain clock = PLL_VCO / PLLP + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); +} +#endif + /** * @} */ diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c index 8d8c4220a..13017194f 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c @@ -21,6 +21,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32wbxx_ll_spi.h" #include "stm32wbxx_ll_bus.h" +#include "stm32wbxx_ll_rcc.h" #ifdef USE_FULL_ASSERT #include "stm32_assert.h" @@ -232,6 +233,10 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) status = SUCCESS; } +#if defined (SPI_I2S_SUPPORT) + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2S_SUPPORT */ return status; } @@ -268,6 +273,251 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) * @} */ +#if defined(SPI_I2S_SUPPORT) +/** @addtogroup I2S_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2S_LL_Private_Constants I2S Private Constants + * @{ + */ +/* I2S registers Masks */ +#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ + SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ + SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD ) + +#define I2S_I2SPR_CLEAR_MASK 0x0002U +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2S_LL_Private_Macros I2S Private Macros + * @{ + */ + +#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \ + || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \ + || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \ + || ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) + +#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \ + || ((__VALUE__) == LL_I2S_POLARITY_HIGH)) + +#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \ + || ((__VALUE__) == LL_I2S_STANDARD_MSB) \ + || ((__VALUE__) == LL_I2S_STANDARD_LSB) \ + || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \ + || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) + +#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \ + || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \ + || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \ + || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)) + +#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \ + || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) + +#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \ + && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \ + || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) + +#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U) + +#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \ + || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2S_LL_Exported_Functions + * @{ + */ + +/** @addtogroup I2S_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the SPI/I2S registers to their default reset values. + * @param SPIx SPI Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are de-initialized + * - ERROR: SPI registers are not de-initialized + */ +ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) +{ + return LL_SPI_DeInit(SPIx); +} + +/** + * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct. + * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), + * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @param SPIx SPI Instance + * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are Initialized + * - ERROR: SPI registers are not Initialized + */ +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) +{ + uint32_t i2sdiv = 2U; + uint32_t i2sodd = 0U; + uint32_t packetlength = 1U; + uint32_t tmp; + uint32_t sourceclock; + ErrorStatus status = ERROR; + + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(SPIx)); + assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); + assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); + assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); + assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput)); + assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq)); + assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity)); + + if (LL_I2S_IsEnabled(SPIx) == 0x00000000U) + { + /*---------------------------- SPIx I2SCFGR Configuration -------------------- + * Configure SPIx I2SCFGR with parameters: + * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit + * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits + * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits + * - ClockPolarity: SPI_I2SCFGR_CKPOL bit + */ + + /* Write to SPIx I2SCFGR */ + MODIFY_REG(SPIx->I2SCFGR, + I2S_I2SCFGR_CLEAR_MASK, + I2S_InitStruct->Mode | I2S_InitStruct->Standard | + I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | + SPI_I2SCFGR_I2SMOD); + + /*---------------------------- SPIx I2SPR Configuration ---------------------- + * Configure SPIx I2SPR with parameters: + * - MCLKOutput: SPI_I2SPR_MCKOE bit + * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits + */ + + /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv) + * else, default values are used: i2sodd = 0U, i2sdiv = 2U. + */ + if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT) + { + /* Check the frame length (For the Prescaler computing) + * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U). + */ + if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B) + { + /* Packet length is 32 bits */ + packetlength = 2U; + } + + /* If an external I2S clock has to be used, the specific define should be set + in the project configuration or in the stm32wbxx_ll_rcc.h file */ + /* Get the I2S source clock value */ + sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S_CLKSOURCE); + + /* Compute the Real divider depending on the MCLK output state with a floating point */ + if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE) + { + /* MCLK output is enabled */ + tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); + } + else + { + /* MCLK output is disabled */ + tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); + } + + /* Remove the floating point */ + tmp = tmp / 10U; + + /* Check the parity of the divider */ + i2sodd = (tmp & (uint16_t)0x0001U); + + /* Compute the i2sdiv prescaler */ + i2sdiv = ((tmp - i2sodd) / 2U); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (i2sodd << 8U); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) + { + /* Set the default values */ + i2sdiv = 2U; + i2sodd = 0U; + } + + /* Write to SPIx I2SPR register the computed value */ + WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput); + + status = SUCCESS; + } + return status; +} + +/** + * @brief Set each @ref LL_I2S_InitTypeDef field to default value. + * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) +{ + /*--------------- Reset I2S init structure parameters values -----------------*/ + I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX; + I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS; + I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B; + I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE; + I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT; + I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW; +} + +/** + * @brief Set linear and parity prescaler. + * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n + * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). + * @param SPIx SPI Instance + * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF. + * @param PrescalerParity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity) +{ + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(SPIx)); + assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear)); + assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity)); + + /* Write to SPIx I2SPR */ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SPI_I2S_SUPPORT */ + #endif /* defined (SPI1) || defined (SPI2) */ /** diff --git a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c index a3f240a16..ba79b2a2e 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c +++ b/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c @@ -262,7 +262,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; TIM_InitStruct->Autoreload = 0xFFFFFFFFU; TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; - TIM_InitStruct->RepetitionCounter = (uint8_t)0x00; + TIM_InitStruct->RepetitionCounter = 0x00000000U; } /** diff --git a/Middlewares/ST/STM32_TouchSensing_Library/Release_Notes.html b/Middlewares/ST/STM32_TouchSensing_Library/Release_Notes.html index 6804b0e3e..16c15985a 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/Release_Notes.html +++ b/Middlewares/ST/STM32_TouchSensing_Library/Release_Notes.html @@ -44,6 +44,73 @@ style='margin-left:4cm;margin-right:4cm;width:80%;background:rgb(51, 102, 255)'>

    Update History

    + +

      

    + +
    +

    +V2.2.4 / 27-May-2019

    +

     

    +

    +Main Changes +

    + +

    •  +Wrong test on acquisition max value. + + +

      

    + +
    +

    +V2.2.3 / 01-April-2019

    +

     

    +

    +Main Changes +

    + +

    •  +IAR compilation issue. + + + +

      

    + +
    +

    +V2.2.2 / 29-March-2019

    +

     

    +

    +Main Changes +

    + +

    •  +Increase STM32L1 maximum bank number. + +

    •  +Solved STM32L1 system workbench compilation error. +

    + +

      

    + +
    +

    +V2.2.1 / 04-March-2019

    +

     

    +

    +Main Changes +

    + +

    •  +Remove notion of Raisonance. + +

    •  +Minor compilation error when using more than 25 channels with STM32L1 MCUs. +

      

    diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl.h index 67a1731ad..98c1d70e5 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains external declarations of the tsl.c file. ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_acq.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_acq.h index df864f4d6..bcb450f78 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_acq.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_acq.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_acq.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains external declarations of the tsl_acq.c file. ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_acq_stm32l1xx_hw.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_acq_stm32l1xx_hw.h index 89a59b4fb..50fb175a4 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_acq_stm32l1xx_hw.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_acq_stm32l1xx_hw.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_acq_stm32l1xx_hw.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains all functions prototypes that manage the HW acquisition * on STM32L1xx devices. ****************************************************************************** diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_acq_stm32l1xx_sw.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_acq_stm32l1xx_sw.h index 71777ccd0..5e45fbbde 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_acq_stm32l1xx_sw.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_acq_stm32l1xx_sw.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_acq_stm32l1xx_sw.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains all functions prototypes that manage the SW acquisition * on STM32L1xx devices. ****************************************************************************** diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_acq_tsc.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_acq_tsc.h index 23d0b0456..1287bb663 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_acq_tsc.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_acq_tsc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_acq_tsc.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains all functions prototypes that manage the TSC acquisition. ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_check_config.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_check_config.h index 8d8c8db29..5a55c5adf 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_check_config.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_check_config.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_check_config.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains the check of all parameters defined in the * common configuration file. ****************************************************************************** diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_check_config_stm32l1xx.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_check_config_stm32l1xx.h index 008c47ba4..c87a7b9d6 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_check_config_stm32l1xx.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_check_config_stm32l1xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_check_config_stm32l1xx.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains the check of all parameters defined in the * STM32L1XX configuration file. ****************************************************************************** @@ -35,36 +33,50 @@ //------------------------------------------------------------------------------ -#if ((TSLPRM_TOTAL_CHANNELS < 1) || (TSLPRM_TOTAL_CHANNELS > 24)) -#error "TSLPRM_TOTAL_CHANNELS is out of range (1 .. 24)." +/* +Channel number can reach 37 on STM32L1 serie. +On Group 2 and Group 7 all pins are not availlable at the same time. + * Groupe 2 (IO1..IO5): we can use 4 IOs instead of 5 (PG0, PG1) + * Groupe 7 (IO1..IO7): we can use 5 IOs insteag of 7 (PG2, PG3, PG4) +This mean we can get only 37-1-2=34 channels. +On STM32 L0, L4, F0 and F3 we can have from 3 to 24 channels +*/ +#define MAX_CHANNEL 34 + +/* This value is equal to int(MAX_CHANNEL/3) = 11 */ +#define MAX_LINROT 11 + + +#if ((TSLPRM_TOTAL_CHANNELS < 1) || (TSLPRM_TOTAL_CHANNELS > MAX_CHANNEL)) +#error "TSLPRM_TOTAL_CHANNELS is out of range (1 .. MAX_CHANNEL)." #endif -#if ((TSLPRM_TOTAL_BANKS < 1) || (TSLPRM_TOTAL_BANKS > 8)) -#error "TSLPRM_TOTAL_BANKS is out of range (1 .. 8)." +#if ((TSLPRM_TOTAL_BANKS < 1) || (TSLPRM_TOTAL_BANKS > MAX_LINROT)) +#error "TSLPRM_TOTAL_BANKS is out of range (1 .. MAX_LINROT)." #endif -#if ((TSLPRM_TOTAL_TOUCHKEYS < 0) || (TSLPRM_TOTAL_TOUCHKEYS > 24)) -#error "TSLPRM_TOTAL_TOUCHKEYS is out of range (0 .. 24)." +#if ((TSLPRM_TOTAL_TOUCHKEYS < 0) || (TSLPRM_TOTAL_TOUCHKEYS > MAX_CHANNEL)) +#error "TSLPRM_TOTAL_TOUCHKEYS is out of range (0 .. MAX_CHANNEL)." #endif -#if ((TSLPRM_TOTAL_TOUCHKEYS_B < 0) || (TSLPRM_TOTAL_TOUCHKEYS_B > 24)) -#error "TSLPRM_TOTAL_TOUCHKEYS_B is out of range (0 .. 24)." +#if ((TSLPRM_TOTAL_TOUCHKEYS_B < 0) || (TSLPRM_TOTAL_TOUCHKEYS_B > MAX_CHANNEL)) +#error "TSLPRM_TOTAL_TOUCHKEYS_B is out of range (0 .. MAX_CHANNEL)." #endif -#if ((TSLPRM_TOTAL_LINROTS < 0) || (TSLPRM_TOTAL_LINROTS > 24)) -#error "TSLPRM_TOTAL_LINROTS is out of range (0 .. 24)." +#if ((TSLPRM_TOTAL_LINROTS < 0) || (TSLPRM_TOTAL_LINROTS > MAX_LINROT)) +#error "TSLPRM_TOTAL_LINROTS is out of range (0 .. MAX_LINROT)." #endif -#if ((TSLPRM_TOTAL_LINROTS_B < 0) || (TSLPRM_TOTAL_LINROTS_B > 24)) -#error "TSLPRM_TOTAL_LINROTS_B is out of range (0 .. 24)." +#if ((TSLPRM_TOTAL_LINROTS_B < 0) || (TSLPRM_TOTAL_LINROTS_B > MAX_LINROT)) +#error "TSLPRM_TOTAL_LINROTS_B is out of range (0 .. MAX_LINROT)." #endif -#if ((TSLPRM_TOTAL_OBJECTS < 1) || (TSLPRM_TOTAL_OBJECTS > 24)) -#error "TSLPRM_TOTAL_OBJECTS is out of range (1 .. 24)." +#if ((TSLPRM_TOTAL_OBJECTS < 1) || (TSLPRM_TOTAL_OBJECTS > MAX_CHANNEL)) +#error "TSLPRM_TOTAL_OBJECTS is out of range (1 .. MAX_CHANNEL)." #endif -#if ((TSLPRM_TOTAL_TKEYS + TSLPRM_TOTAL_LNRTS) > 24) -#error "The Sum of TouchKeys and Linear/Rotary sensors exceeds 24." +#if ((TSLPRM_TOTAL_TKEYS + TSLPRM_TOTAL_LNRTS) > MAX_CHANNEL) +#error "The Sum of TouchKeys and Linear/Rotary sensors exceeds MAX_CHANNEL." #endif //------------------------------------------------------------------------------ diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_check_config_tsc.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_check_config_tsc.h index ae8d9d054..6e9e7500a 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_check_config_tsc.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_check_config_tsc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_check_config_tsc.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains the check of all parameters defined in the * TSC configuration file. ****************************************************************************** diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_conf_stm32l1xx_template.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_conf_stm32l1xx_template.h index aa7f88b18..3aacb621c 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_conf_stm32l1xx_template.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_conf_stm32l1xx_template.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_conf_stm32l1xx_template.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief STM32L1xx configuration file. * @note This file must be copied in the application folder with the 'tsl_conf.h' name. ****************************************************************************** diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_conf_tsc_template.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_conf_tsc_template.h index d4b06bb01..de93c2d69 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_conf_tsc_template.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_conf_tsc_template.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_conf_tsc_template.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief TSC configuration file. * @note This file must be copied in the application folder with the 'tsl_conf.h' name. ****************************************************************************** diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_dxs.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_dxs.h index a79060aa8..40286cee8 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_dxs.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_dxs.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_dxs.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains external declarations of the tsl_dxs.c file. ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_ecs.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_ecs.h index befe58776..6ee673e59 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_ecs.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_ecs.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_ecs.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains external declarations of the tsl_ecs.c file. ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_filter.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_filter.h index 5909a351e..a1ce351f9 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_filter.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_filter.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_filter.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains external declarations of the tsl_filter.c file. ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_globals.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_globals.h index 7ea68de58..b0c8734e1 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_globals.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_globals.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_globals.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains external declarations of the tsl_globals.c file. ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_linrot.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_linrot.h index dabb8decb..357acb7f4 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_linrot.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_linrot.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_linrot.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains external declarations of the tsl_linrot.c file. ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_object.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_object.h index bb2170f8e..c330395f0 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_object.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_object.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_object.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains external declarations of the tsl_object.c file. ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_time.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_time.h index bb43b032c..cf06b7f18 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_time.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_time.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_time.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains external declarations of the tsl_time.c file. ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_touchkey.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_touchkey.h index cf5310484..6d85261c9 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_touchkey.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_touchkey.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_touchkey.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains external declarations of the tsl_touchkey.c file. ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_types.h b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_types.h index 2eee349e9..9c4ec7ce5 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_types.h +++ b/Middlewares/ST/STM32_TouchSensing_Library/inc/tsl_types.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_types.h * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains all general structures definition. ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl.c b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl.c index 81f5972a7..862052986 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl.c +++ b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl.c * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains the driver main functions. ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_acq.c b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_acq.c index dd7bf7fd3..788d1e56d 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_acq.c +++ b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_acq.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_acq.c * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains all functions to manage the acquisition. ****************************************************************************** * @attention @@ -95,7 +93,7 @@ TSL_Status_enum_T TSL_acq_BankGetResult(TSL_tIndex_T idx_bk, TSL_pFuncMeasFilter } else { - if (new_meas > TSL_Params.AcqMax) + if (new_meas >= TSL_Params.AcqMax) { bank->p_chData[idx_dest].Flags.AcqStatus = TSL_ACQ_STATUS_ERROR_MAX; bank->p_chData[idx_dest].Delta = 0; @@ -237,7 +235,7 @@ TSL_Status_enum_T TSL_acq_BankCalibrate(TSL_tIndex_T idx_bk) new_meas = TSL_acq_GetMeas(pchSrc->IdxSrc); // Check min/max and set status flag - if ((new_meas < TSL_Params.AcqMin) || (new_meas > TSL_Params.AcqMax)) + if ((new_meas < TSL_Params.AcqMin) || (new_meas >= TSL_Params.AcqMax)) { // Stop calibration // Clear data for all channels of the bank diff --git a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_acq_stm32l1xx_hw.c b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_acq_stm32l1xx_hw.c index 34ef7a033..e16f5c374 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_acq_stm32l1xx_hw.c +++ b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_acq_stm32l1xx_hw.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_acq_stm32l1xx_hw.c * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains all functions to manage the acquisition * on STM32l1xx products using the Hardware mode (with Timers). ****************************************************************************** @@ -879,7 +877,7 @@ TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tM #elif defined(__CC_ARM) // Keil/MDK-ARM #pragma O1 #pragma Ospace -#elif defined(__GNUC__) // Atollic/True Studio + Raisonance/RKit +#elif defined(__GNUC__) // Atollic/True Studio + AC6/SW4STM32 #pragma GCC push_options #pragma GCC optimize ("O0") #endif diff --git a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_acq_stm32l1xx_sw.c b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_acq_stm32l1xx_sw.c index 79603b022..eb0c2ac53 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_acq_stm32l1xx_sw.c +++ b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_acq_stm32l1xx_sw.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_acq_stm32l1xx_sw.c * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains all functions to manage the acquisition * on STM32l1xx products using the software mode. ****************************************************************************** @@ -821,7 +819,7 @@ void TSL_acq_BankStartAcq(void) RI->ASCR2 &= (uint32_t)(~(TSL_BankChannelConf[1])); /*it's better to implement this like that because it's much more faster than to put this test in the "while test" below */ - if (MeasurementCounter > TSL_Params.AcqMax) + if (MeasurementCounter >= TSL_Params.AcqMax) { TSL_acq_GroupDone(GroupToCheck); __NOP(); @@ -976,12 +974,14 @@ TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tM #if defined(__IAR_SYSTEMS_ICC__) // IAR/EWARM #pragma optimize=low +void SoftDelay(uint16_t val) #elif defined(__CC_ARM) // Keil/MDK-ARM #pragma O1 #pragma Ospace -#elif defined(__GNUC__) // Atollic/True Studio + Raisonance/RKit +void SoftDelay(uint16_t val) +#elif defined(__GNUC__) // Atollic/True Studio + AC6/SW4STM32 #pragma GCC push_options -#pragma GCC optimize ("O0") +void __attribute__((optimize("O0"))) SoftDelay(uint16_t val) #endif /** * @brief Software delay (private routine) @@ -989,7 +989,6 @@ TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tM * With fHCLK = 32MHz: 1 = ~1s, 50 = ~14s, 100 = ~25s, 200 = ~50s * @retval None */ -void SoftDelay(uint16_t val) { __IO uint16_t idx; for (idx = val; idx > 0; idx--) @@ -1005,10 +1004,9 @@ void SwSpreadSpectrum(void) #pragma O1 #pragma Ospace __INLINE void SwSpreadSpectrum(void) -#elif defined(__GNUC__) // Atollic/True Studio + Raisonance/RKit +#elif defined(__GNUC__) // Atollic/True Studio + AC6/SW4STM32 #pragma GCC push_options -#pragma GCC optimize ("O0") -__INLINE void SwSpreadSpectrum(void) +void __attribute__((optimize("O0"))) SwSpreadSpectrum(void) #endif /** * @brief Spread Spectrum using a variable software delay. @@ -1016,7 +1014,7 @@ __INLINE void SwSpreadSpectrum(void) * @retval None */ { - uint8_t idx; + volatile uint8_t idx; SpreadCounter++; diff --git a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_acq_tsc.c b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_acq_tsc.c index 2df6ba6e0..543171564 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_acq_tsc.c +++ b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_acq_tsc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_acq_tsc.c * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains all functions to manage the TSC acquisition. ****************************************************************************** * @attention @@ -285,7 +283,7 @@ TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tM #elif defined(__CC_ARM) // Keil/MDK-ARM #pragma O1 #pragma Ospace -#elif defined(__GNUC__) // Atollic/True Studio + Raisonance/RKit +#elif defined(__GNUC__) // Atollic/True Studio + AC6/SW4STM32 #pragma GCC push_options #pragma GCC optimize ("O0") #endif diff --git a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_dxs.c b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_dxs.c index 2349c08c4..eee6bbb69 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_dxs.c +++ b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_dxs.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_dxs.c * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains all functions to manage the * Detection Exclusion System (DxS) algorithm. ****************************************************************************** diff --git a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_ecs.c b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_ecs.c index c08f95112..5ddd580c0 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_ecs.c +++ b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_ecs.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_ecs.c * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains all functions to manage the ECS. ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_filter.c b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_filter.c index 5e21d0f57..6759c5511 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_filter.c +++ b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_filter.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_filter.c * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains all functions to manage the signal or delta filters. ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_globals.c b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_globals.c index 901e4bbc2..a8018eff1 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_globals.c +++ b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_globals.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_globals.c * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains global variables. ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_linrot.c b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_linrot.c index 06cd9d459..7ec0948d9 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_linrot.c +++ b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_linrot.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_linrot.c * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains all functions to manage Linear and Rotary sensors. ****************************************************************************** * @attention @@ -1711,11 +1709,7 @@ void TSL_linrot_DebErrorStateProcess(void) // Get state mask mask = TSL_linrot_GetStateMask(); // Mask Error and Debounce bits -#ifdef _RAISONANCE_ - mask &= ~(TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_ERROR_BIT_MASK); -#else mask &= (TSL_StateMask_enum_T)(~(TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_ERROR_BIT_MASK)); -#endif // Go back to the previous state switch (mask) { diff --git a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_object.c b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_object.c index 104ca0a91..167f14f8e 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_object.c +++ b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_object.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_object.c * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains all functions to manage the sensors. ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_time.c b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_time.c index 343c8be2e..be3c1917a 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_time.c +++ b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_time.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_time.c * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains all functions to manage the timings for ECS and DTO. ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_touchkey.c b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_touchkey.c index 53172e174..a2835a538 100644 --- a/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_touchkey.c +++ b/Middlewares/ST/STM32_TouchSensing_Library/src/tsl_touchkey.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file tsl_touchkey.c * @author MCD Application Team - * @version V2.2.0 - * @date 01-february-2016 * @brief This file contains all functions to manage TouchKey sensors. ****************************************************************************** * @attention @@ -1037,11 +1035,7 @@ void TSL_tkey_DebErrorStateProcess(void) // Get state mask mask = TSL_tkey_GetStateMask(); // Mask Error and Debounce bits -#ifdef _RAISONANCE_ - mask &= ~(TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_ERROR_BIT_MASK); -#else mask &= (TSL_StateMask_enum_T)(~(TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_ERROR_BIT_MASK)); -#endif // Go back to the previous state switch (mask) { diff --git a/Middlewares/ST/STM32_WPAN/Release_Notes.html b/Middlewares/ST/STM32_WPAN/Release_Notes.html index b20dbca29..6504ed2d7 100644 --- a/Middlewares/ST/STM32_WPAN/Release_Notes.html +++ b/Middlewares/ST/STM32_WPAN/Release_Notes.html @@ -11,7 +11,7 @@ span.underline{text-decoration: underline;} div.column{display: inline-block; vertical-align: top; width: 50%;} - + @@ -49,11 +49,54 @@

    Update History

    - +

    Main Changes

    Interface:

      +
    • Added new commmand SHCI_C2_SetFlashActivityControl() to configure BLE timing protection
      • +
    +

    Zigbee:

    +
      +
    • Support of the following Zigbee clusters: +
        +
      • Basic
        • +
      • On/Off
        • +
      • Device Temperature Configuration
        • +
      • Identify
        • +
      • Power Profile
        • +
      • Thermostat-UI-Config
        • +
      • Ballast-Configuration
        • +
      • Illuminance-Measurement
        • +
      • Temperature Measurement
        • +
      • Pressure Measurement
        • +
      • Occupancy-Sensing
        • +
      • Messaging
        • +
      • Meter Identification
        • +
      • +
    +

    BLE-Mesh:

    +
      +
    • BLE-Mesh library version 1.12.000 +
        +
      • Embedded Provisioner example added including config-client
        • +
      • Multi Net Key support has been added(limited to 2 Net Keys)
        • +
      • Key Refresh updated for Multiple Keys
        • +
      • Vendor Model updated to add Read and Write messages
        • +
      • TID check added in the firmware
        • +
      • Light_LC sensor property updated
        • +
      • Generic Power OnOff Message updated
        • +
      • Multi elements support limited to 3
        • +
      • +
    +
    +
    +
    + +
    +

    Main Changes

    +

    Interface:

    +
    • Added new commmand SHCI_C2_ExtpaConfig() to support external PA
    • Update System and BLE transport layer so that a user event packet is released by default
    @@ -67,7 +110,7 @@
    -

    Main Changes

    +

    Main Changes

    General:

    • Introducing support of Zigbee
      • @@ -105,7 +148,7 @@
      -

      Main Changes

      +

      Main Changes

      General:

      • Following utilities : Scheduler and Low Power Manager reworked and moved to “Utilities” directory
        • @@ -131,7 +174,7 @@
        -

        Main Changes

        +

        Main Changes

        BLE:

        • Fix race condition in transport layer when an operating system is used.
          • @@ -177,7 +220,7 @@
          -

          Main Changes

          +

          Main Changes

          General:

          • Licenses in utilities and patterns moved from sla0044 to 3-clauses BSD
            • @@ -203,7 +246,7 @@
            -

            Main Changes

            +

            Main Changes

            First release

            diff --git a/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_events.c b/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_events.c index b0ebbd32a..1c73c66c8 100644 --- a/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_events.c +++ b/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_events.c @@ -1,13 +1,13 @@ /****************************************************************************** * @file ble_events.c * @author MCD Application Team - * @date 08 November 2019 + * @date 22 January 2020 * @brief Source file for STM32WB (Event callbacks) * Auto-generated file: do not edit! ****************************************************************************** * @attention * - *

            © Copyright (c) 2019 STMicroelectronics. + *

            © Copyright (c) 2020 STMicroelectronics. * All rights reserved.

            * * This software component is licensed by ST under Ultimate Liberty license @@ -73,7 +73,7 @@ void aci_gatt_notification_ext_event_process(uint8_t *buffer_in); void hci_le_connection_complete_event_process(uint8_t *buffer_in); void hci_le_advertising_report_event_process(uint8_t *buffer_in); void hci_le_connection_update_complete_event_process(uint8_t *buffer_in); -void hci_le_read_remote_used_features_complete_event_process(uint8_t *buffer_in); +void hci_le_read_remote_features_complete_event_process(uint8_t *buffer_in); void hci_le_long_term_key_request_event_process(uint8_t *buffer_in); void hci_le_data_length_change_event_process(uint8_t *buffer_in); void hci_le_read_local_p256_public_key_complete_event_process(uint8_t *buffer_in); @@ -82,138 +82,138 @@ void hci_le_enhanced_connection_complete_event_process(uint8_t *buffer_in); void hci_le_direct_advertising_report_event_process(uint8_t *buffer_in); void hci_le_phy_update_complete_event_process(uint8_t *buffer_in); -const hci_event_table_t hci_event_table[HCI_EVENT_TABLE_SIZE] = +const hci_event_table_t hci_event_table[HCI_EVENT_TABLE_SIZE] = { /* hci_disconnection_complete_event */ - {0x0005, hci_disconnection_complete_event_process}, + { 0x0005, hci_disconnection_complete_event_process }, /* hci_encryption_change_event */ - {0x0008, hci_encryption_change_event_process}, + { 0x0008, hci_encryption_change_event_process }, /* hci_read_remote_version_information_complete_event */ - {0x000c, hci_read_remote_version_information_complete_event_process}, + { 0x000c, hci_read_remote_version_information_complete_event_process }, /* hci_hardware_error_event */ - {0x0010, hci_hardware_error_event_process}, + { 0x0010, hci_hardware_error_event_process }, /* hci_number_of_completed_packets_event */ - {0x0013, hci_number_of_completed_packets_event_process}, + { 0x0013, hci_number_of_completed_packets_event_process }, /* hci_data_buffer_overflow_event */ - {0x001a, hci_data_buffer_overflow_event_process}, + { 0x001a, hci_data_buffer_overflow_event_process }, /* hci_encryption_key_refresh_complete_event */ - {0x0030, hci_encryption_key_refresh_complete_event_process}, + { 0x0030, hci_encryption_key_refresh_complete_event_process }, }; -const hci_event_table_t hci_le_meta_event_table[HCI_LE_META_EVENT_TABLE_SIZE] = +const hci_event_table_t hci_le_meta_event_table[HCI_LE_META_EVENT_TABLE_SIZE] = { /* hci_le_connection_complete_event */ - {0x0001, hci_le_connection_complete_event_process}, + { 0x0001, hci_le_connection_complete_event_process }, /* hci_le_advertising_report_event */ - {0x0002, hci_le_advertising_report_event_process}, + { 0x0002, hci_le_advertising_report_event_process }, /* hci_le_connection_update_complete_event */ - {0x0003, hci_le_connection_update_complete_event_process}, - /* hci_le_read_remote_used_features_complete_event */ - {0x0004, hci_le_read_remote_used_features_complete_event_process}, + { 0x0003, hci_le_connection_update_complete_event_process }, + /* hci_le_read_remote_features_complete_event */ + { 0x0004, hci_le_read_remote_features_complete_event_process }, /* hci_le_long_term_key_request_event */ - {0x0005, hci_le_long_term_key_request_event_process}, + { 0x0005, hci_le_long_term_key_request_event_process }, /* hci_le_data_length_change_event */ - {0x0007, hci_le_data_length_change_event_process}, + { 0x0007, hci_le_data_length_change_event_process }, /* hci_le_read_local_p256_public_key_complete_event */ - {0x0008, hci_le_read_local_p256_public_key_complete_event_process}, + { 0x0008, hci_le_read_local_p256_public_key_complete_event_process }, /* hci_le_generate_dhkey_complete_event */ - {0x0009, hci_le_generate_dhkey_complete_event_process}, + { 0x0009, hci_le_generate_dhkey_complete_event_process }, /* hci_le_enhanced_connection_complete_event */ - {0x000a, hci_le_enhanced_connection_complete_event_process}, + { 0x000a, hci_le_enhanced_connection_complete_event_process }, /* hci_le_direct_advertising_report_event */ - {0x000b, hci_le_direct_advertising_report_event_process}, + { 0x000b, hci_le_direct_advertising_report_event_process }, /* hci_le_phy_update_complete_event */ - {0x000c, hci_le_phy_update_complete_event_process}, + { 0x000c, hci_le_phy_update_complete_event_process }, }; -const hci_event_table_t hci_vendor_specific_event_table[HCI_VENDOR_SPECIFIC_EVENT_TABLE_SIZE] = +const hci_event_table_t hci_vendor_specific_event_table[HCI_VENDOR_SPECIFIC_EVENT_TABLE_SIZE] = { /* aci_hal_end_of_radio_activity_event */ - {0x0004, aci_hal_end_of_radio_activity_event_process}, + { 0x0004, aci_hal_end_of_radio_activity_event_process }, /* aci_hal_scan_req_report_event */ - {0x0005, aci_hal_scan_req_report_event_process}, + { 0x0005, aci_hal_scan_req_report_event_process }, /* aci_hal_fw_error_event */ - {0x0006, aci_hal_fw_error_event_process}, + { 0x0006, aci_hal_fw_error_event_process }, /* aci_gap_limited_discoverable_event */ - {0x0400, aci_gap_limited_discoverable_event_process}, + { 0x0400, aci_gap_limited_discoverable_event_process }, /* aci_gap_pairing_complete_event */ - {0x0401, aci_gap_pairing_complete_event_process}, + { 0x0401, aci_gap_pairing_complete_event_process }, /* aci_gap_pass_key_req_event */ - {0x0402, aci_gap_pass_key_req_event_process}, + { 0x0402, aci_gap_pass_key_req_event_process }, /* aci_gap_authorization_req_event */ - {0x0403, aci_gap_authorization_req_event_process}, + { 0x0403, aci_gap_authorization_req_event_process }, /* aci_gap_slave_security_initiated_event */ - {0x0404, aci_gap_slave_security_initiated_event_process}, + { 0x0404, aci_gap_slave_security_initiated_event_process }, /* aci_gap_bond_lost_event */ - {0x0405, aci_gap_bond_lost_event_process}, + { 0x0405, aci_gap_bond_lost_event_process }, /* aci_gap_proc_complete_event */ - {0x0407, aci_gap_proc_complete_event_process}, + { 0x0407, aci_gap_proc_complete_event_process }, /* aci_gap_addr_not_resolved_event */ - {0x0408, aci_gap_addr_not_resolved_event_process}, + { 0x0408, aci_gap_addr_not_resolved_event_process }, /* aci_gap_numeric_comparison_value_event */ - {0x0409, aci_gap_numeric_comparison_value_event_process}, + { 0x0409, aci_gap_numeric_comparison_value_event_process }, /* aci_gap_keypress_notification_event */ - {0x040a, aci_gap_keypress_notification_event_process}, + { 0x040a, aci_gap_keypress_notification_event_process }, /* aci_l2cap_connection_update_resp_event */ - {0x0800, aci_l2cap_connection_update_resp_event_process}, + { 0x0800, aci_l2cap_connection_update_resp_event_process }, /* aci_l2cap_proc_timeout_event */ - {0x0801, aci_l2cap_proc_timeout_event_process}, + { 0x0801, aci_l2cap_proc_timeout_event_process }, /* aci_l2cap_connection_update_req_event */ - {0x0802, aci_l2cap_connection_update_req_event_process}, + { 0x0802, aci_l2cap_connection_update_req_event_process }, /* aci_l2cap_command_reject_event */ - {0x080a, aci_l2cap_command_reject_event_process}, + { 0x080a, aci_l2cap_command_reject_event_process }, /* aci_gatt_attribute_modified_event */ - {0x0c01, aci_gatt_attribute_modified_event_process}, + { 0x0c01, aci_gatt_attribute_modified_event_process }, /* aci_gatt_proc_timeout_event */ - {0x0c02, aci_gatt_proc_timeout_event_process}, + { 0x0c02, aci_gatt_proc_timeout_event_process }, /* aci_att_exchange_mtu_resp_event */ - {0x0c03, aci_att_exchange_mtu_resp_event_process}, + { 0x0c03, aci_att_exchange_mtu_resp_event_process }, /* aci_att_find_info_resp_event */ - {0x0c04, aci_att_find_info_resp_event_process}, + { 0x0c04, aci_att_find_info_resp_event_process }, /* aci_att_find_by_type_value_resp_event */ - {0x0c05, aci_att_find_by_type_value_resp_event_process}, + { 0x0c05, aci_att_find_by_type_value_resp_event_process }, /* aci_att_read_by_type_resp_event */ - {0x0c06, aci_att_read_by_type_resp_event_process}, + { 0x0c06, aci_att_read_by_type_resp_event_process }, /* aci_att_read_resp_event */ - {0x0c07, aci_att_read_resp_event_process}, + { 0x0c07, aci_att_read_resp_event_process }, /* aci_att_read_blob_resp_event */ - {0x0c08, aci_att_read_blob_resp_event_process}, + { 0x0c08, aci_att_read_blob_resp_event_process }, /* aci_att_read_multiple_resp_event */ - {0x0c09, aci_att_read_multiple_resp_event_process}, + { 0x0c09, aci_att_read_multiple_resp_event_process }, /* aci_att_read_by_group_type_resp_event */ - {0x0c0a, aci_att_read_by_group_type_resp_event_process}, + { 0x0c0a, aci_att_read_by_group_type_resp_event_process }, /* aci_att_prepare_write_resp_event */ - {0x0c0c, aci_att_prepare_write_resp_event_process}, + { 0x0c0c, aci_att_prepare_write_resp_event_process }, /* aci_att_exec_write_resp_event */ - {0x0c0d, aci_att_exec_write_resp_event_process}, + { 0x0c0d, aci_att_exec_write_resp_event_process }, /* aci_gatt_indication_event */ - {0x0c0e, aci_gatt_indication_event_process}, + { 0x0c0e, aci_gatt_indication_event_process }, /* aci_gatt_notification_event */ - {0x0c0f, aci_gatt_notification_event_process}, + { 0x0c0f, aci_gatt_notification_event_process }, /* aci_gatt_proc_complete_event */ - {0x0c10, aci_gatt_proc_complete_event_process}, + { 0x0c10, aci_gatt_proc_complete_event_process }, /* aci_gatt_error_resp_event */ - {0x0c11, aci_gatt_error_resp_event_process}, + { 0x0c11, aci_gatt_error_resp_event_process }, /* aci_gatt_disc_read_char_by_uuid_resp_event */ - {0x0c12, aci_gatt_disc_read_char_by_uuid_resp_event_process}, + { 0x0c12, aci_gatt_disc_read_char_by_uuid_resp_event_process }, /* aci_gatt_write_permit_req_event */ - {0x0c13, aci_gatt_write_permit_req_event_process}, + { 0x0c13, aci_gatt_write_permit_req_event_process }, /* aci_gatt_read_permit_req_event */ - {0x0c14, aci_gatt_read_permit_req_event_process}, + { 0x0c14, aci_gatt_read_permit_req_event_process }, /* aci_gatt_read_multi_permit_req_event */ - {0x0c15, aci_gatt_read_multi_permit_req_event_process}, + { 0x0c15, aci_gatt_read_multi_permit_req_event_process }, /* aci_gatt_tx_pool_available_event */ - {0x0c16, aci_gatt_tx_pool_available_event_process}, + { 0x0c16, aci_gatt_tx_pool_available_event_process }, /* aci_gatt_server_confirmation_event */ - {0x0c17, aci_gatt_server_confirmation_event_process}, + { 0x0c17, aci_gatt_server_confirmation_event_process }, /* aci_gatt_prepare_write_permit_req_event */ - {0x0c18, aci_gatt_prepare_write_permit_req_event_process}, + { 0x0c18, aci_gatt_prepare_write_permit_req_event_process }, /* aci_gatt_read_ext_event */ - {0x0c1d, aci_gatt_read_ext_event_process}, + { 0x0c1d, aci_gatt_read_ext_event_process }, /* aci_gatt_indication_ext_event */ - {0x0c1e, aci_gatt_indication_ext_event_process}, + { 0x0c1e, aci_gatt_indication_ext_event_process }, /* aci_gatt_notification_ext_event */ - {0x0c1f, aci_gatt_notification_ext_event_process}, + { 0x0c1f, aci_gatt_notification_ext_event_process }, }; /* hci_disconnection_complete_event */ @@ -1589,10 +1589,10 @@ void hci_le_connection_update_complete_event_process(uint8_t *buffer_in) rp0->Supervision_Timeout); } -/* hci_le_read_remote_used_features_complete_event */ +/* hci_le_read_remote_features_complete_event */ /* Event len: 1 + 2 + 8 */ /** - * @brief The LE Read Remote Used Features Complete event is used to indicate the + * @brief The LE Read Remote Features Complete event is used to indicate the completion of the process of the Controller obtaining the used features of the remote Bluetooth device specified by the Connection_Handle event parameter.See Bluetooth spec 5.0 vol 2 [part E] 7.7.65.4 * @param Status Status error code. @@ -1603,13 +1603,13 @@ remote Bluetooth device specified by the Connection_Handle event parameter.See B * @retval None */ -void hci_le_read_remote_used_features_complete_event_process(uint8_t *buffer_in) +void hci_le_read_remote_features_complete_event_process(uint8_t *buffer_in) { /* Input params */ - hci_le_read_remote_used_features_complete_event_rp0 *rp0 = (hci_le_read_remote_used_features_complete_event_rp0 *)buffer_in; - hci_le_read_remote_used_features_complete_event(rp0->Status, - rp0->Connection_Handle, - rp0->LE_Features); + hci_le_read_remote_features_complete_event_rp0 *rp0 = (hci_le_read_remote_features_complete_event_rp0 *)buffer_in; + hci_le_read_remote_features_complete_event(rp0->Status, + rp0->Connection_Handle, + rp0->LE_Features); } /* hci_le_long_term_key_request_event */ diff --git a/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_events.h b/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_events.h index a5e9af49f..4aa35e2b0 100644 --- a/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_events.h +++ b/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_events.h @@ -1,13 +1,13 @@ /****************************************************************************** * @file ble_events.h * @author MCD Application Team - * @date 08 November 2019 + * @date 22 January 2020 * @brief Header file for STM32WB (Event callbacks) * Auto-generated file: do not edit! ****************************************************************************** * @attention * - *

            © Copyright (c) 2019 STMicroelectronics. + *

            © Copyright (c) 2020 STMicroelectronics. * All rights reserved.

            * * This software component is licensed by ST under Ultimate Liberty license @@ -297,7 +297,7 @@ WEAK_FUNCTION(void hci_le_connection_update_complete_event(uint8_t Status, uint16_t Conn_Latency, uint16_t Supervision_Timeout)); /** - * @brief The LE Read Remote Used Features Complete event is used to indicate the + * @brief The LE Read Remote Features Complete event is used to indicate the completion of the process of the Controller obtaining the used features of the remote Bluetooth device specified by the Connection_Handle event parameter.See Bluetooth spec 5.0 vol 2 [part E] 7.7.65.4 * @param Status Status error code. @@ -307,9 +307,9 @@ remote Bluetooth device specified by the Connection_Handle event parameter.See B * @param LE_Features Bit Mask List of used LE features. For details see LE Link Layer specification. * @retval None */ -WEAK_FUNCTION(void hci_le_read_remote_used_features_complete_event(uint8_t Status, - uint16_t Connection_Handle, - uint8_t LE_Features[8])); +WEAK_FUNCTION(void hci_le_read_remote_features_complete_event(uint8_t Status, + uint16_t Connection_Handle, + uint8_t LE_Features[8])); /** * @brief The LE Long Term Key Request event indicates that the master device is attempting to encrypt or re-encrypt the link and is requesting the Long Term diff --git a/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_hal_aci.h b/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_hal_aci.h index 4406208a7..135800ab6 100644 --- a/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_hal_aci.h +++ b/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_hal_aci.h @@ -1,13 +1,13 @@ /****************************************************************************** * @file ble_hal_aci.h * @author MCD Application Team - * @date 06 November 2019 + * @date 13 January 2020 * @brief Header file for STM32WB (hal_aci) * Auto-generated file: do not edit! ****************************************************************************** * @attention * - *

            © Copyright (c) 2019 STMicroelectronics. + *

            © Copyright (c) 2020 STMicroelectronics. * All rights reserved.

            * * This software component is licensed by ST under Ultimate Liberty license @@ -38,13 +38,11 @@ directly some low level parameters for the system in the runtime. which has to be written. The valid offsets are: - 0x00: Bluetooth public address, Value length to be written: 6 bytes -- 0x06: DIV used to derive CSRK, Value length to be written: 2 bytes - 0x08: Encryption root key used to derive LTK and CSRK, Value length to be written: 16 bytes - 0x18: Identity root key used to derive LTK and CSRK, Value length to be written: 16 bytes - 0x2E: Static Random Address: 6 bytes * Values: - 0x00: CONFIG_DATA_PUBADDR_OFFSET - - 0x06: CONFIG_DATA_DIV_OFFSET - 0x08: CONFIG_DATA_ER_OFFSET - 0x18: CONFIG_DATA_IR_OFFSET - 0x2E: CONFIG_DATA_RANDOM_ADDRESS_WR @@ -63,13 +61,11 @@ The number of read bytes changes for different Offset. which has to be read. The valid offsets are: * 0x00: Bluetooth public address, Value length returned: 6 bytes -* 0x06: DIV used to derive CSRK, Value length returned: 2 bytes * 0x08: Encryption root key used to derive LTK and CSRK, Value length returned: 16 bytes * 0x18: Identity root key used to derive LTK and CSRK, Value length returned: 16 bytes * 0x80: Static random address. Value length returned: 6 bytes (read-only) * Values: - 0x00: CONFIG_DATA_PUBADDR_OFFSET - - 0x06: CONFIG_DATA_DIV_OFFSET - 0x08: CONFIG_DATA_ER_OFFSET - 0x18: CONFIG_DATA_IR_OFFSET - 0x80: CONFIG_DATA_RANDOM_ADDRESS diff --git a/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_hci_le.c b/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_hci_le.c index 3b3c4277f..fc8fa41da 100644 --- a/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_hci_le.c +++ b/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_hci_le.c @@ -1,13 +1,13 @@ /****************************************************************************** * @file ble_hci_le.c * @author MCD Application Team - * @date 23 May 2019 + * @date 22 January 2020 * @brief Source file for ble api STM32WB (hci_le) * Auto-generated file: do not edit! ****************************************************************************** * @attention * - *

            © Copyright (c) 2019 STMicroelectronics. + *

            © Copyright (c) 2020 STMicroelectronics. * All rights reserved.

            * * This software component is licensed by ST under Ultimate Liberty license @@ -927,11 +927,11 @@ tBleStatus hci_le_read_channel_map(uint16_t Connection_Handle, return BLE_STATUS_SUCCESS; } -tBleStatus hci_le_read_remote_used_features(uint16_t Connection_Handle) +tBleStatus hci_le_read_remote_features(uint16_t Connection_Handle) { struct hci_request rq; uint8_t cmd_buffer[BLE_CMD_MAX_PARAM_LEN]; - hci_le_read_remote_used_features_cp0 *cp0 = (hci_le_read_remote_used_features_cp0*)(cmd_buffer); + hci_le_read_remote_features_cp0 *cp0 = (hci_le_read_remote_features_cp0*)(cmd_buffer); tBleStatus status = 0; int index_input = 0; cp0->Connection_Handle = htob(Connection_Handle, 2); diff --git a/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_hci_le.h b/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_hci_le.h index 5b82551b2..548bc7237 100644 --- a/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_hci_le.h +++ b/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_hci_le.h @@ -1,13 +1,13 @@ /****************************************************************************** * @file ble_hci_le.h * @author MCD Application Team - * @date 23 May 2019 + * @date 22 January 2020 * @brief Header file for STM32WB (hci_le) * Auto-generated file: do not edit! ****************************************************************************** * @attention * - *

            © Copyright (c) 2019 STMicroelectronics. + *

            © Copyright (c) 2020 STMicroelectronics. * All rights reserved.

            * * This software component is licensed by ST under Ultimate Liberty license @@ -988,7 +988,7 @@ This command may be issued on both the master and slave. - 0x0000 ... 0x0EFF * @retval Value indicating success or error code. */ -tBleStatus hci_le_read_remote_used_features(uint16_t Connection_Handle); +tBleStatus hci_le_read_remote_features(uint16_t Connection_Handle); /** * @brief The LE_Encrypt command is used to request the Controller to encrypt the diff --git a/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_types.h b/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_types.h index a1c3db62a..46b8ecc60 100644 --- a/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_types.h +++ b/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_types.h @@ -1,12 +1,12 @@ /****************************************************************************** * @file ble_types.h * @author MCD Application Team - * @date 06 September 2019 + * @date 22 January 2020 * @brief Auto-generated file: do not edit! ****************************************************************************** * @attention * - *

            © Copyright (c) 2019 STMicroelectronics. + *

            © Copyright (c) 2020 STMicroelectronics. * All rights reserved.

            * * This software component is licensed by ST under Ultimate Liberty license @@ -623,12 +623,12 @@ typedef PACKED(struct) typedef PACKED(struct) { uint16_t Connection_Handle; -} hci_le_read_remote_used_features_cp0; +} hci_le_read_remote_features_cp0; typedef PACKED(struct) { uint8_t Status; -} hci_le_read_remote_used_features_rp0; +} hci_le_read_remote_features_rp0; typedef PACKED(struct) { @@ -2628,7 +2628,7 @@ typedef PACKED(struct) uint8_t Status; uint16_t Connection_Handle; uint8_t LE_Features[8]; -} hci_le_read_remote_used_features_complete_event_rp0; +} hci_le_read_remote_features_complete_event_rp0; typedef PACKED(struct) { diff --git a/Middlewares/ST/STM32_WPAN/ble/core/ble_bufsize.h b/Middlewares/ST/STM32_WPAN/ble/core/ble_bufsize.h index 45dfc2a81..53fac68c0 100644 --- a/Middlewares/ST/STM32_WPAN/ble/core/ble_bufsize.h +++ b/Middlewares/ST/STM32_WPAN/ble/core/ble_bufsize.h @@ -102,18 +102,24 @@ * - a part, that may be considered "fixed", i.e. independent from the above * mentioned parameters. */ -#define BLE_FIXED_BUFFER_SIZE_BYTES(llo) ((llo) ? 6104 : 6544) +#if (SLAVE_ONLY == 0) && (LL_ONLY == 0) +#define BLE_FIXED_BUFFER_SIZE_BYTES 6976 /* Full stack */ +#elif SLAVE_ONLY == 0 +#define BLE_FIXED_BUFFER_SIZE_BYTES 6272 /* LL only */ +#else +#define BLE_FIXED_BUFFER_SIZE_BYTES 4628 /* Slave only */ +#endif /* * BLE_PER_LINK_SIZE_BYTES: additional memory size used per link */ -#define BLE_PER_LINK_SIZE_BYTES(llo) ((llo) ? 208 : 376) - -/* - * BLE_DLEN_EXT_SIZE: amount of memory needed to support Data Length - * Extension feature. - */ -#define BLE_DLEN_EXT_SIZE(en) ((en) ? 436 : 0) +#if (SLAVE_ONLY == 0) && (LL_ONLY == 0) +#define BLE_PER_LINK_SIZE_BYTES 376 /* Full stack */ +#elif SLAVE_ONLY == 0 +#define BLE_PER_LINK_SIZE_BYTES 192 /* LL only */ +#else +#define BLE_PER_LINK_SIZE_BYTES 332 /* Slave only */ +#endif /* * BLE_TOTAL_BUFFER_SIZE: this macro returns the amount of memory, in bytes, @@ -124,15 +130,11 @@ * will support. Valid values are from 1 to 8. * * @param mblocks_count: Number of memory blocks allocated for packets. - * - * @param dlen_ext_en: Enable or disable the Extended Packet length feature. - * Valid values are 0 or 1. - */ -#define BLE_TOTAL_BUFFER_SIZE(n_link, mblocks_count, dlen_ext_en) \ - (BLE_FIXED_BUFFER_SIZE_BYTES(LL_ONLY) + \ - (BLE_PER_LINK_SIZE_BYTES(LL_ONLY) * (n_link)) + \ - ((BLE_MEM_BLOCK_SIZE + 12) * (mblocks_count)) + \ - BLE_DLEN_EXT_SIZE(dlen_ext_en)) + */ +#define BLE_TOTAL_BUFFER_SIZE(n_link, mblocks_count) \ + (BLE_FIXED_BUFFER_SIZE_BYTES + \ + (BLE_PER_LINK_SIZE_BYTES * (n_link)) + \ + ((BLE_MEM_BLOCK_SIZE + 12) * (mblocks_count))) /* * BLE_TOTAL_BUFFER_SIZE_GATT: this macro returns the amount of memory, diff --git a/Middlewares/ST/STM32_WPAN/ble/core/ble_legacy.h b/Middlewares/ST/STM32_WPAN/ble/core/ble_legacy.h index 6569de531..b47ec9f04 100644 --- a/Middlewares/ST/STM32_WPAN/ble/core/ble_legacy.h +++ b/Middlewares/ST/STM32_WPAN/ble/core/ble_legacy.h @@ -185,4 +185,14 @@ typedef uint8_t tBDAddr[6]; /* ------------------------------------------------------------------------- */ +/* Deprecative name for LE Read Remote Features command + */ +#define hci_le_read_remote_used_features hci_le_read_remote_features +#define hci_le_read_remote_used_features_complete_event_rp0 \ + hci_le_read_remote_features_complete_event_rp0 + + +/* ------------------------------------------------------------------------- */ + + #endif /* BLE_LEGACY_H__ */ diff --git a/Middlewares/ST/STM32_WPAN/ble/core/doc/STM32WB_BLE_Wireless_Interface.html b/Middlewares/ST/STM32_WPAN/ble/core/doc/STM32WB_BLE_Wireless_Interface.html index 467f5f8d3..c963e584a 100644 --- a/Middlewares/ST/STM32_WPAN/ble/core/doc/STM32WB_BLE_Wireless_Interface.html +++ b/Middlewares/ST/STM32_WPAN/ble/core/doc/STM32WB_BLE_Wireless_Interface.html @@ -636,7 +636,7 @@ padding-right: 0px; } td.gsib_a {padding:0px;padding-top:4px;padding-left:3px;} -

            STM32WB BLE Wireless Interface

            This document describes the STM32WB BLE Application Commands Interface (ACI) and Host Commands Interface (HCI).

            STM32WB Series website

            Revision history

            December 2018 - Rev 1.0 - First release for interface 1.0

            February 2019 - Rev 1.1 - Modified HCI_HARDWARE_ERROR_EVENT comment

            March 2019 - Rev 1.2 - Removed unused event documentation

            March 2019 - Rev 1.3 - Modification ACI_HAL_FW_ERROR_EVENT error code

            March 2019 - Rev 1.4 - Changed default mask of HCI_SET_EVENT_MASK

            May 2019 - Rev 1.5 - ACI_GATT_NOTIFICATION_EXT_EVENT added

            June 2019 - Rev 1.6 - Changed comment on usage of Char Handles in multiple ACI_GATT commands; Added ACI_GATT_INDICATION_EXT_EVENT

            June 2019 - Rev 1.7 - Changed descriptions of ACI_ATT_READ_BY_TYPE_REQ and ACI_GATT_READ_USING_CHAR_UUID

            July 2019 - Rev 1.8 - Reworked error codes section; Added GAP_ prefix to the GAP procedure bitmap definitions

            September 2019 - Rev 1.9 - Added ACI_GATT_READ_EXT_EVENT; Modified ACI_GAP_CONFIGURE_WHITELIST comment

            October 2019 - Rev 1.10 - Changed descriptions of ACI_GATT_WRITE_WITHOUT_RESP and ACI_GATT_SIGNED_WRITE_WITHOUT_RESP; Removed obsolete configuration data elements

            November 2019 - Rev 1.11 - Completed description of ACI_GAP_INIT; Added specific pairing status definitions

            November 2019 - Rev 1.12 - Fixed status error codes

            Contents

            HCI/ACI commands

            HCI/ACI events

            Status error codes

            HCI/ACI commands

            HCI commands

            HCI TESTING commands

            ACI HAL commands

            ACI GAP commands

            ACI GATT/ATT commands

            ACI L2CAP commands

            HCI commands

            HCI commands

    +

    STM32WB BLE Wireless Interface

    This document describes the STM32WB BLE Application Commands Interface (ACI) and Host Commands Interface (HCI).

    STM32WB Series website

    Revision history

    December 2018 - Rev 1.0 - First release for interface 1.0

    February 2019 - Rev 1.1 - Modified HCI_HARDWARE_ERROR_EVENT comment

    March 2019 - Rev 1.2 - Removed unused event documentation

    March 2019 - Rev 1.3 - Modification ACI_HAL_FW_ERROR_EVENT error code

    March 2019 - Rev 1.4 - Changed default mask of HCI_SET_EVENT_MASK

    May 2019 - Rev 1.5 - ACI_GATT_NOTIFICATION_EXT_EVENT added

    June 2019 - Rev 1.6 - Changed comment on usage of Char Handles in multiple ACI_GATT commands; Added ACI_GATT_INDICATION_EXT_EVENT

    June 2019 - Rev 1.7 - Changed descriptions of ACI_ATT_READ_BY_TYPE_REQ and ACI_GATT_READ_USING_CHAR_UUID

    July 2019 - Rev 1.8 - Reworked error codes section; Added GAP_ prefix to the GAP procedure bitmap definitions

    September 2019 - Rev 1.9 - Added ACI_GATT_READ_EXT_EVENT; Modified ACI_GAP_CONFIGURE_WHITELIST comment

    October 2019 - Rev 1.10 - Changed descriptions of ACI_GATT_WRITE_WITHOUT_RESP and ACI_GATT_SIGNED_WRITE_WITHOUT_RESP; Removed obsolete configuration data elements

    November 2019 - Rev 1.11 - Completed description of ACI_GAP_INIT; Added specific pairing status definitions

    November 2019 - Rev 1.12 - Fixed status error codes

    January 2020 - Rev 1.13 - Removed DIV unused configuration data; Fixed naming of HCI_LE_READ_REMOTE_FEATURES command and complete event

    Contents

    HCI/ACI commands

    HCI/ACI events

    Status error codes

    HCI/ACI commands

    HCI commands

    HCI TESTING commands

    ACI HAL commands

    ACI GAP commands

    ACI GATT/ATT commands

    ACI L2CAP commands

    HCI commands

    HCI commands

    @@ -704,7 +704,7 @@ td.gsib_a {padding:0px;padding-top:4px;padding-left:3px;} - @@ -1771,7 +1771,7 @@ Channel n is unused = 0. Channel n is used = 1. The most significant bits are reserved and shall be set to 0.

     -
    CommandOpCode
    HCI_DISCONNECT

    0x0406

    HCI_LE_READ_CHANNEL_MAP

    0x2015

    HCI_LE_READ_REMOTE_USED_FEATURES

    0x2016

    +
    HCI_LE_READ_REMOTE_FEATURES

    0x2016

    HCI_LE_ENCRYPT

    0x2017

    Events generated

  • HCI_COMMAND_COMPLETE_EVENT

    • HCI_LE_READ_REMOTE_USED_FEATURES

    Description

    This command requests a list of the used LE features from the remote device. +

    Events generated

  • HCI_COMMAND_COMPLETE_EVENT

    • HCI_LE_READ_REMOTE_FEATURES

    Description

    This command requests a list of the used LE features from the remote device. This command shall return a list of the used LE features. For details see [Vol 6] Part B, Section 4.6. This command may be issued on both the master and slave. @@ -1787,7 +1787,7 @@ This command may be issued on both the master and slave.

    1

    Status error code.

    -

    Events generated

  • HCI_COMMAND_STATUS_EVENT
  • HCI_LE_READ_REMOTE_USED_FEATURES_COMPLETE_EVENT

    • HCI_LE_ENCRYPT

    Description

    The LE_Encrypt command is used to request the Controller to encrypt the +

    Events generated

  • HCI_COMMAND_STATUS_EVENT
  • HCI_LE_READ_REMOTE_FEATURES_COMPLETE_EVENT

    • HCI_LE_ENCRYPT

    Description

    The LE_Encrypt command is used to request the Controller to encrypt the Plaintext_Data in the command using the Key given in the command and returns the Encrypted_Data to the Host. The AES-128 bit block cypher is defined in NIST Publication FIPS-197 (http://csrc.nist.gov/publications/fips/ @@ -2542,12 +2542,11 @@ directly some low level parameters for the system in the runtime.

    Input p which has to be written. The valid offsets are:

    • 0x00: Bluetooth public address, Value length to be written: 6 bytes
      • -
    • 0x06: DIV used to derive CSRK, Value length to be written: 2 bytes
    • 0x08: Encryption root key used to derive LTK and CSRK, Value length to be written: 16 bytes
    • 0x18: Identity root key used to derive LTK and CSRK, Value length to be written: 16 bytes
    • 0x2E: Static Random Address: 6 bytes
    -
  • 0x00: CONFIG_DATA_PUBADDR_OFFSET
  • 0x06: CONFIG_DATA_DIV_OFFSET
  • 0x08: CONFIG_DATA_ER_OFFSET
  • 0x18: CONFIG_DATA_IR_OFFSET
  • 0x2E: CONFIG_DATA_RANDOM_ADDRESS_WR
    • +
  • 0x00: CONFIG_DATA_PUBADDR_OFFSET
  • 0x08: CONFIG_DATA_ER_OFFSET
  • 0x18: CONFIG_DATA_IR_OFFSET
  • 0x2E: CONFIG_DATA_RANDOM_ADDRESS_WR

    • Length

    1

    Length of data to be written

    @@ -2571,12 +2570,11 @@ The number of read bytes changes for different Offset.

    Input parameters< which has to be read. The valid offsets are:

    • 0x00: Bluetooth public address, Value length returned: 6 bytes
      • -
    • 0x06: DIV used to derive CSRK, Value length returned: 2 bytes
    • 0x08: Encryption root key used to derive LTK and CSRK, Value length returned: 16 bytes
    • 0x18: Identity root key used to derive LTK and CSRK, Value length returned: 16 bytes
    • 0x80: Static random address. Value length returned: 6 bytes (read-only)
    -
  • 0x00: CONFIG_DATA_PUBADDR_OFFSET
  • 0x06: CONFIG_DATA_DIV_OFFSET
  • 0x08: CONFIG_DATA_ER_OFFSET
  • 0x18: CONFIG_DATA_IR_OFFSET
  • 0x80: CONFIG_DATA_RANDOM_ADDRESS
    • +
  • 0x00: CONFIG_DATA_PUBADDR_OFFSET
  • 0x08: CONFIG_DATA_ER_OFFSET
  • 0x18: CONFIG_DATA_IR_OFFSET
  • 0x80: CONFIG_DATA_RANDOM_ADDRESS

    • Output parameters

    - @@ -6127,7 +6125,7 @@ Time = N * 1.25 msec

    It shall be a multiple of 10 ms and larger than (1 + connSlaveLatency) * connInterval * 2. Time = N * 10 msec.

    -
    ParameterSizeDescriptionPossible values

    Status

    @@ -5988,7 +5986,7 @@ Controller from the Host.

    HCI_LE_CONNECTION_UPDATE_COMPLETE_EVENT

    0x03

    HCI_LE_READ_REMOTE_USED_FEATURES_COMPLETE_EVENT

    0x04

    +
    HCI_LE_READ_REMOTE_FEATURES_COMPLETE_EVENT

    0x04

    HCI_LE_LONG_TERM_KEY_REQUEST_EVENT

    0x05

  • 0x000A (100 ms) ... 0x0C80 (32000 ms)

    • HCI_LE_READ_REMOTE_USED_FEATURES_COMPLETE_EVENT

    Description

    The LE Read Remote Used Features Complete event is used to indicate the +

    HCI_LE_READ_REMOTE_FEATURES_COMPLETE_EVENT

    Description

    The LE Read Remote Features Complete event is used to indicate the completion of the process of the Controller obtaining the used features of the remote Bluetooth device specified by the Connection_Handle event parameter.See Bluetooth spec 5.0 vol 2 [part E] 7.7.65.4

    Event parameters

    diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/appli_test.h b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/appli_test.h index 890b79263..86b854534 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/appli_test.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/appli_test.h @@ -1,9 +1,9 @@ /** ****************************************************************************** -* @file response_test.h +* @file appli_test.h * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Header file for the serial interface file ****************************************************************************** * @attention @@ -40,8 +40,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __RESPONSE_TEST_H -#define __RESPONSE_TEST_H +#ifndef __APPLI_TEST_H +#define __APPLI_TEST_H /* Includes ------------------------------------------------------------------*/ #include "types.h" @@ -49,11 +49,11 @@ /* Exported macro ------------------------------------------------------------*/ #define TEST_1_WAIT_PERIOD 2000 #define TEST_2_WAIT_PERIOD 100 -#define TEST_3_WAIT_PERIOD 5000 +#define TEST_3_WAIT_PERIOD 3000 #define TEST_READ_PERIOD 2000 #define CLOCK_FLAG_ENABLE 1 #define CLOCK_FLAG_DISABLE 0 -#define DATA_BYTE_SEND 100 +#define DATA_BYTE_SEND 50 /* Exported variables ------------------------------------------------------- */ /* Exported Functions Prototypes ---------------------------------------------*/ void SerialResponse_Process(char *rcvdStringBuff, uint16_t rcvdStringSize); diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/ble_clock.h b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/ble_clock.h index b22154196..8f92cbcc2 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/ble_clock.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/ble_clock.h @@ -1,8 +1,8 @@ /******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** * File Name : ble_clock.h * Author : AMS - HEA&RF BU -* Version : V1.0.1 -* Date : 19-July-2012 +* @version V1.12.000 +* @date 06-12-2019 * Description : Header file for clock library, that gives a simple time * reference to the BLE Stack. ******************************************************************************** diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/ble_mesh.h b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/ble_mesh.h index f75e1273a..3cb9ed00b 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/ble_mesh.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/ble_mesh.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file ble_mesh.h * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Header file for the BLE-Mesh stack ****************************************************************************** * @attention @@ -45,11 +45,11 @@ #include "types.h" //#include "hal_types.h" -#define BLUENRG_MESH_APPLICATION_VERSION "1.10.004" +#define BLE_MESH_APPLICATION_VERSION "1.12.003" /** * \mainpage ST BLE-Mesh Solutions Bluetooth LE Mesh Library * -* \version 1.10.000 +* \version 1.12.003 * * \subsection contents_sec Contents * @@ -237,7 +237,8 @@ typedef struct { /** \brief Write local data callback. * Called when the device gets a request to modify its data. Such a request is - * made via a call to \a BLEMesh_SetRemoteData on a remote device. + * made via a call to \a BluenrgMesh_SetRemotePublication + * on a remote device. * User is responsible for deserializing the data. * \param[in] peer Source network address. * \param[in] dst_peer Destination address set by peer. @@ -338,6 +339,7 @@ typedef struct **/ typedef struct { + MOBLEUINT32 model_id; MOBLEUINT32 opcode; MOBLEBOOL reliable; MOBLEUINT16 min_payload_size; @@ -461,6 +463,7 @@ typedef struct const uint16_t friend_lp_buff_size; const uint16_t max_appli_pkt_size; const uint16_t neighbor_table_buff_size; + const uint16_t models_buff_size; } DynBufferParam_t; @@ -533,7 +536,8 @@ MOBLE_RESULT BLEMesh_Process(void); */ MOBLE_RESULT BLEMesh_SetVendorCbMap(MOBLE_VENDOR_CB_MAP const * map); -/** \brief Set remote data on the given peer. +/** \brief Set remote data on the given peer. The usage of this API is depracated and replaced with +* BluenrgMesh_SetRemotePublication * User is responsible for serializing data into \a data buffer. Vendor_WriteLocalDataCb * callback will be called on the remote device. * \param[in] peer Destination address. May be set to MOBLE_ADDRESS_ALL_NODES to broadcast data. @@ -549,6 +553,23 @@ MOBLE_RESULT BLEMesh_SetRemoteData(MOBLE_ADDRESS peer, MOBLEUINT8 elementIndex, MOBLEUINT32 length, MOBLEBOOL response, MOBLEUINT8 isVendor); + +/** \brief Set remote publication for the given Model ID & node Address +* User is responsible for serializing data into \a data buffer. Vendor_WriteLocalDataCb +* callback will be called on the remote device. +* \param[in] modelId ID of the model. +* \param[in] srcAddress element Address of the Node +* \param[in] command vendor model commands +* \param[in] data Data buffer. +* \param[in] length Length of data in bytes. +* \param[in] response If 'MOBLE_TRUE', used to get the response. If 'MOBLE_FALSE', no response +* \return MOBLE_RESULT_SUCCESS on success. +*/ +MOBLE_RESULT BLEMesh_SetRemotePublication(MOBLEUINT32 modelId, MOBLE_ADDRESS srcAddress, + MOBLEUINT16 command, MOBLEUINT8 const * data, + MOBLEUINT32 length, MOBLEBOOL response, + MOBLEUINT8 isVendor); + /** \brief Vendor Model Set remote data on the given peer. * User is responsible for serializing data into a data buffer. * \param[in] peer Destination address. May be set to MOBLE_ADDRESS_ALL_NODES to broadcast data. @@ -618,6 +639,60 @@ MOBLE_RESULT VendorModel_SendResponse(MOBLEUINT16 vendorModelId, MOBLE_ADDRESS p MOBLE_RESULT Model_SendResponse(MOBLE_ADDRESS src_peer,MOBLE_ADDRESS dst_peer , MOBLEUINT16 opcode,MOBLEUINT8 const *pData,MOBLEUINT32 length); + +/** \brief Config Model Send message to the remote +* \param[in] peer Destination address. Must be a device address (0b0xxx xxxx xxxx xxxx, but not 0). +* \param[in] data Data buffer. +* \param[in] length Length of data in bytes. Maximum accepted length is 8. +* If length is zero, no associated data is sent with the report. +* \return MOBLE_RESULT_SUCCESS on success. +*/ +MOBLE_RESULT ConfigModel_SendMessage(MOBLE_ADDRESS src_peer, + MOBLE_ADDRESS dst_peer, + MOBLEUINT16 opcode, + MOBLEUINT8 *pData, + MOBLEUINT32 length, + MOBLEUINT8 *pTargetDevKey); + + + +/** \brief Publish Send to the provisioner +* \param[in] peer Destination address is Provisioner address +* \param[in] data Data buffer. +* \param[in] length Length of data in bytes. Maximum accepted length is 8. +* If length is zero, no associated data is sent with the report. +* \return MOBLE_RESULT_SUCCESS on success. +*/ +MOBLE_RESULT ConfigModel_SelfPublishConfig (MOBLE_ADDRESS dst_peer, + MOBLEUINT16 opcode, + MOBLEUINT8 *pData, + MOBLEUINT32 length); + +/** \brief Subscription Send to the provisioner +* \param[in] peer Destination address is Provisioner address +* \param[in] data Data buffer. +* \param[in] length Length of data in bytes. Maximum accepted length is 8. +* If length is zero, no associated data is sent with the report. +* \return MOBLE_RESULT_SUCCESS on success. +*/ +MOBLE_RESULT ConfigModel_SelfSubscriptionConfig (MOBLE_ADDRESS dst_peer, + MOBLEUINT16 opcode, + MOBLEUINT8 *pData, + MOBLEUINT32 length); + +/** \brief App binding Send to the provisioner +* \param[in] peer Destination address is Provisioner address +* \param[in] data Data buffer. +* \param[in] length Length of data in bytes. Maximum accepted length is 8. +* If length is zero, no associated data is sent with the report. +* \return MOBLE_RESULT_SUCCESS on success. +*/ + +MOBLE_RESULT ConfigClient_SelfModelAppBindConfig (MOBLE_ADDRESS dst_peer, + MOBLEUINT16 opcode, + MOBLEUINT8 *pData, + MOBLEUINT32 length); + /** \brief initialize unprovisioned node to be provisioned. * \param None * \return MOBLE_RESULT_SUCCESS on success. @@ -669,7 +744,7 @@ MOBLE_ADDRESS BLEMesh_GetAddress(void); * \return mesh address of a node. * */ -MOBLE_ADDRESS BLEMesh_GetPublishAddress(MOBLEUINT8 elementNumber); +MOBLE_ADDRESS BLEMesh_GetPublishAddress(MOBLEUINT8 elementNumber, MOBLEUINT32 modelId); /** \brief Get Subscription address of a node * @@ -680,7 +755,8 @@ MOBLE_ADDRESS BLEMesh_GetPublishAddress(MOBLEUINT8 elementNumber); */ MOBLE_RESULT BLEMesh_GetSubscriptionAddress(MOBLE_ADDRESS *addressList, MOBLEUINT8 *sizeOfList, - MOBLEUINT8 elementNumber); + MOBLEUINT8 elementNumber, + MOBLEUINT32 modelId); /** \brief Set default TTL value. * When message is sent to mesh network, it contains TTL field. User shall call @@ -790,6 +866,29 @@ void BLEMesh_UnprovisionCallback(MOBLEUINT8 reason); */ void BLEMesh_ProvisionCallback(void); +/** \brief Call back function called when PB-ADV link Opened +* Callback on Provision by provisioner +* +*/ +void BLEMesh_PbAdvLinkOpenCb(void); + +/** \brief Call back function called when PB-ADV link Closed +* Callback on Provision by provisioner +* +*/ +void BLEMesh_PbAdvLinkCloseCb(void); + +/** \brief Provisioning of a node from Provisioner +* \param[in] UUID of the Unprovisioned node +* +*/ +MOBLE_RESULT BLEMesh_ProvisionRemote(MOBLEUINT8 uuid[16]); + +/** \brief Creates credentials for Provisioner +* +*/ +MOBLE_RESULT BLEMesh_CreateNetwork(MOBLEUINT8 *devKey); + /** \brief Set SIG Model callback map. * \param[in] map callback map. If NULL, nothing is done. * \count[in] count of the number of models defined in Application @@ -865,6 +964,12 @@ void BLEMesh_LpnFriendshipEstablishedCallback(MOBLE_ADDRESS fnAddress); */ void BLEMesh_LpnFriendshipClearedCallback(MOBLEUINT8 reason, MOBLE_ADDRESS fnAddress); +/** \brief Disable continuous scan +* Applicable only to provisioned Low Power feature enabled node +* \return MOBLE_RESULT_SUCCESS on success. +*/ +MOBLE_RESULT BLEMesh_LpnDisableScan(void); + /** \brief To synchronize flash erase with sufficient available time w.r.t. next connection event. * \return MOBLE_TRUE if no connection exists or sufficient time is available for flash erase operation. */ @@ -876,6 +981,7 @@ void BLEMesh_StopAdvScan(void); /** \brief Set adv interval of provisioning service, 0 value results in stop. * Default value: 1000 ms +* Actual value -> interval + random(16) * \param[in] adv interval (ms), min interval value is 100 ms * \return MOBLE_RESULT_SUCCESS on success. */ @@ -883,6 +989,7 @@ MOBLE_RESULT BLEMesh_SetProvisioningServAdvInterval(MOBLEUINT16 interval); /** \brief Set interval of unprovisioned device beacon, 0 value results in stop. * Default value: 1000 ms +* Actual value -> interval + random(16) * \param[in] interval (ms) of beacons, min interval value is 100 ms * \return MOBLE_RESULT_SUCCESS on success. */ @@ -890,6 +997,7 @@ MOBLE_RESULT BLEMesh_SetUnprovisionedDevBeaconInterval(MOBLEUINT16 interval); /** \brief Set adv interval of proxy service. * Default value: 1000 ms +* Actual value -> interval + random(128) * \param[in] adv interval (ms), min interval value is 1000 ms * \return MOBLE_RESULT_SUCCESS on success. */ @@ -897,12 +1005,14 @@ MOBLE_RESULT BLEMesh_SetProxyServAdvInterval(MOBLEUINT16 interval); /** \brief Set interval of secure network beacon. * Default value: 10000 ms +* Actual value -> interval + random(128) * \param[in] interval (ms) of beacons, min interval value is 10000 ms * \return MOBLE_RESULT_SUCCESS on success. */ MOBLE_RESULT BLEMesh_SetSecureBeaconInterval(MOBLEUINT16 interval); /** \brief Set interval of custom beacon, 0 value results in stop. +* Actual value -> interval + random(128) * \param[in] interval (ms) of beacons, min interval value is 1000 ms * \return MOBLE_RESULT_SUCCESS on success. */ @@ -910,26 +1020,63 @@ MOBLE_RESULT BLEMesh_SetCustomBeaconInterval(MOBLEUINT16 interval); /** \brief Set custom beacon data. * If size > 31 bytes, beacon is rejected -* \param[out] beacon data buffer -* \param[out] size of beacon data +* \param[out] beacon data buffer. Includes length, adtype, data +* \param[out] size of buffer */ void BLEMesh_CustomBeaconGeneratorCallback(void* buffer, MOBLEUINT8* size); +/** \brief Callback to receive non-mesh beacons +* +* Beacons are received only if received beacon ad type is not Mesh Message, +* Mesh Beacon or PB-ADV +* \param[out] MAC address +* \param[out] data +* \param[out] length +* \param[out] rssi +*/ +void BLEMesh_CustomBeaconReceivedCallback(const MOBLEUINT8* bdAddr, + const MOBLEUINT8* data, + MOBLEUINT8 length, + MOBLEINT8 rssi); + /** * @brief ApplicationGetSigModelList: This function provides the list of the * SIG Models to the calling function * @param pModels_sig_ID: Pointer of the array to be filled with SIG Models list +* @param elementIndex: Index of the element for Model List +* retval Count of the SIG Model Servers enabled in the Application +*/ +MOBLEUINT8 ApplicationGetSigModelList(MOBLEUINT16* pModels_sig_ID, \ + MOBLEUINT8 elementIndex); + +/** +* @brief ApplicationGetCLIENTSigModelList: This function provides the list of the +* SIG Models to the calling function +* @param pModels_sig_ID: Pointer of the array to be filled with SIG Models list +* @param elementIndex: Index of the element for Model List +* retval Count of the SIG Model Servers enabled in the Application +*/ +MOBLEUINT8 ApplicationGetCLIENTSigModelList(MOBLEUINT16* pModels_sig_ID, + MOBLEUINT8 elementIndex); + +/** +* @brief BLEMeshSetSelfModelList: This function provides the list of the +* SIG Models to the calling function +* @param Node: Pointer of the array to be filled with SIG Models list +* @param elementIndex: Index of the element for Model List * retval Count of the SIG Model Servers enabled in the Application */ -MOBLEUINT8 ApplicationGetSigModelList(MOBLEUINT16* pModels_sig_ID); +MOBLEUINT8 BLEMeshSetSelfModelList(MOBLEUINT8 numberOfElements); /** * @brief ApplicationGetVendorModelList: This function provides the list of the * Vendor Models to the calling function * @param pModels_sig_ID: Pointer of the array to be filled with Vendor Models list +* @param elementIndex: Index of the element for Model List * retval Count of the Vendor Model Servers enabled in the Application */ -MOBLEUINT8 ApplicationGetVendorModelList(MOBLEUINT32* pModels_vendor_ID); +MOBLEUINT8 ApplicationGetVendorModelList(MOBLEUINT32* pModels_vendor_ID, \ + MOBLEUINT8 elementIndex); /** * @brief ApplicationChkSigModelActive: This function checks if a specific @@ -947,6 +1094,15 @@ MOBLEBOOL ApplicationChkSigModelActive(MOBLEUINT16 modelID); */ MOBLEBOOL ApplicationChkVendorModelActive(MOBLEUINT32 modelID); +/** +* @brief ApplicationGetConfigServerDeviceKey: This function provides the + device key to the node from Application +* @param modelID: Model Server ID received for the checking function +* retval Bool: True or False, if the Server ID matches with the list +*/ +MOBLE_RESULT ApplicationGetConfigServerDeviceKey(MOBLE_ADDRESS src, + const MOBLEUINT8 **ppkeyTbUse); + /** \brief New neighbor appeared callback in neighbor table. * \param[out] MAC address of neighbor. * \param[out] is neighbor provisioned or unprovisioned device. @@ -1009,6 +1165,44 @@ MOBLE_RESULT BLEMesh_Shutdown(void); * \return MOBLE_RESULT_FAIL if already up and running, MOBLE_RESULT_SUCCESS otherwise. */ MOBLE_RESULT BLEMesh_Resume(void); + +/** \brief Get the Buffer for Mesh Model data Received +* +* This function should be called to Get the buffer from the Mesh Models +* \return MOBLE_RESULT_FAIL if NOT available, MOBLE_RESULT_SUCCESS if available +*/ + +#ifdef STATIC_MEMORY_ALLOCATION_IN_APPLI +void* GetMemoryDataBuffer(MOBLEUINT8 type, MOBLEUINT32 len); +#endif + + + + +#define MESH_MODEL_BUFFER 1 +#define MESH_MODEL_RESPONSE_BUFFER 2 +#define MESH_LOWER_TPT_BUFFER 3 +#define MESH_LOWER_TPT_FN_BUFFER 4 +#define MESH_LOWER_TPT_APP_BUFFER 5 +#define VENDOR_MODEL_WRITE_BUFFER 6 +#define VENDOR_MODEL_WRITE_PUBLISHBUFFER 7 +#define VENDOR_MODEL_RESPONSE_BUFFER 8 +#define GENERIC_MODEL_REPLY_BUFFER 9 +#define GENERIC_MODEL_PUBLISH_BUFFER 10 +#define GENERIC_MODEL_SENDREMOTE_BUFFER 11 +#define GENERIC_MODEL_SENDDATA_BUFFER 12 +#define HEALTH_MODEL_PUBLISH_BUFFER 13 +#define HEALTH_MODEL_NEW_BUFFER 14 +#define CONFIG_MODEL_PUBLISH_BUFFER 15 +#define PROVISIONER_BUFFER 16 +#define PROVISION_NODE_BUFFER 17 +#define ACCESS_APPLI_BUFFER 18 +#define MESH_LOWER_TPT_INSEG 19 +#define MESH_LOWER_TPT_INSEQ0 20 +#define MESH_LOWER_TPT_OUTMSG 21 + + + #endif /* __BLE_MESH_ */ /******************* (C) COPYRIGHT 2019 STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/pal_if.h b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/pal_if.h index c15be2731..9d8e05d19 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/pal_if.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/pal_if.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file pal_if.h * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Header file for platform dependent functions ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/pal_nvm.h b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/pal_nvm.h index 1a179fd25..088fd4c2c 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/pal_nvm.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/pal_nvm.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file pal_nvm.h * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Header file for pal_nvm.c ****************************************************************************** * @attention @@ -51,11 +51,12 @@ /* Includes ------------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -/* Exported variables ------------------------------------------------------- */ +/* Exported variables -------------------------------------------------------*/ extern const void* mobleNvmBase; /* Private define ------------------------------------------------------------*/ -#define NVM_BASE ((unsigned int)mobleNvmBase) +#define NVM_BASE ((unsigned int)mobleNvmBase) +#define NVM_SIZE 8192U typedef enum { diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/serial_ctrl.h b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/serial_ctrl.h index 24a4234bd..72b04a179 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/serial_ctrl.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/serial_ctrl.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file serial_if.h * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Header file for the serial interface file ****************************************************************************** * @attention @@ -50,8 +50,8 @@ /* Exported variables ------------------------------------------------------- */ /* Exported Functions Prototypes ---------------------------------------------*/ void SerialCtrl_Process(char *rcvdStringBuff, uint16_t rcvdStringSize); - - +void SerialCtrlVendorRead_Process(char *rcvdStringBuff, uint16_t rcvdStringSize); +void SerialCtrlVendorWrite_Process(char *rcvdStringBuff, uint16_t rcvdStringSize); #endif /* __SERIAL_CTRL_H */ /******************* (C) COPYRIGHT 2018 STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/serial_if.h b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/serial_if.h index 55fe849cf..87f3a42ae 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/serial_if.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/serial_if.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file serial_if.h * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Header file for the serial interface file ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/serial_prvn.h b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/serial_prvn.h index a33f9bcb4..5cb362a55 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/serial_prvn.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/serial_prvn.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file embd_provision.h * @author BLE Mesh Team -* @version V1.11.000 -* @date 25-07-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Header file for the serial interface file ****************************************************************************** * @attention @@ -51,8 +51,7 @@ /* Exported variables ------------------------------------------------------- */ /* Exported Functions Prototypes ---------------------------------------------*/ void SerialPrvn_Process(char *rcvdStringBuff, uint16_t rcvdStringSize); - - +void SerialPrvn_ProvisioningStatusUpdateCb(uint8_t flagPrvningInProcess, MOBLEUINT16 nodeAddress); #endif /* __EMBD_PROVISION_H */ /******************* (C) COPYRIGHT 2018 STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/serial_ut.h b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/serial_ut.h index f5c4dc814..385e24932 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/serial_ut.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/serial_ut.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file serial_ut.h * @author BLE Mesh Team -* @version V1.07.000 -* @date 15-June-2018 +* @version V1.12.000 +* @date 06-12-2019 * @brief Header file for the upper tester file ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/types.h b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/types.h index 7e2b15f03..0332a6335 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/types.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/Inc/types.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file types.h * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Header file for various type declarations ****************************************************************************** * @attention @@ -47,7 +47,7 @@ * \file types.h * \brief This file defines Motorola Solutions Bluetooth LE Mesh Library types. * -* This file contains data types defined in the ST BlueNRG-Mesh Library . Please refer to the +* This file contains data types defined in the ST BLE-Mesh Library . Please refer to the * desription of each type to get the information on it's purpose. */ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_GCC.a b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_GCC.a index a21405272..14f39578f 100644 Binary files a/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_GCC.a and b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_GCC.a differ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_GCC_DEBUG.a b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_GCC_DEBUG.a new file mode 100644 index 000000000..31ec1fc06 Binary files /dev/null and b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_GCC_DEBUG.a differ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR.a b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR.a index d1d21c137..fe9417e3a 100644 Binary files a/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR.a and b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR.a differ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_DEBUG.a b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_DEBUG.a new file mode 100644 index 000000000..248550e7c Binary files /dev/null and b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_DEBUG.a differ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_DEBUG_NOD.a b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_DEBUG_NOD.a new file mode 100644 index 000000000..b08bfdd39 Binary files /dev/null and b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_DEBUG_NOD.a differ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_DEBUG_PROV.a b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_DEBUG_PROV.a new file mode 100644 index 000000000..fd6ebb510 Binary files /dev/null and b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_DEBUG_PROV.a differ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_NOD.a b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_NOD.a new file mode 100644 index 000000000..8324b4acb Binary files /dev/null and b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_NOD.a differ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_PROV.a b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_PROV.a new file mode 100644 index 000000000..c18a12db8 Binary files /dev/null and b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_IAR_PROV.a differ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_Keil.lib b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_Keil.lib index d499334d3..5fa5f6eb8 100644 Binary files a/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_Keil.lib and b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_Keil.lib differ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_Keil_DEBUG.lib b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_Keil_DEBUG.lib new file mode 100644 index 000000000..1bf35941e Binary files /dev/null and b/Middlewares/ST/STM32_WPAN/ble/mesh/Library/libBle_Mesh_CM4_Keil_DEBUG.lib differ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/blob.h b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/blob.h index 08af6f55e..21981ea28 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/blob.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/blob.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file blob.h * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-May-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief BLE-Mesh Block transfer Server implementation header file ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/common.h b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/common.h index 12527cdd9..3ef929b44 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/common.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/common.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file common.h * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Model middleware file ****************************************************************************** * @attention @@ -57,6 +57,7 @@ #define LIGHT_LIGHTNESS_NVM_OFFSET 1 #define LIGHT_CTL_NVM_OFFSET 3 #define LIGHT_HSL_NVM_OFFSET 7 +#define LIGHT_HSL_DEFAULT_NVM_OFFSET 13 /* Buffer index limit for the generic data */ #define GENERIC_DATA_LIMIT 15 @@ -71,9 +72,15 @@ #define CLK_FLAG_DISABLE 0 #define PWM_ZERO_VALUE 1 +#define INTENSITY_LEVEL_ZERO 0X00 +#define INTENSITY_LEVEL_FULL 31990U +#define MAX_TID_VALUE 0XFF +//#if STM32 +//typedef MOBLE_RESULT (*APPLI_SAVE_MODEL_STATE_CB)(MOBLEUINT8* stateBuff, MOBLEUINT16 size); +//#elif BLUENRG2_DEVICE typedef MOBLE_RESULT (*APPLI_SAVE_MODEL_STATE_CB)(MOBLEUINT8* stateBuff, MOBLEUINT8 size); - +//#endif /** @addtogroup MODEL_GENERIC * @{ */ @@ -116,6 +123,7 @@ MOBLE_RESULT Chk_MultiParamValidityAllUnsigned(MOBLEUINT16 min_param_range1, MO MOBLEINT16 min_param_range3, MOBLEUINT16 max_param_range3, const MOBLEUINT8* param); +MOBLE_RESULT Chk_TidValidity(MOBLE_ADDRESS peer_Addrs,MOBLE_ADDRESS dst_Addrs,MOBLEUINT8 tidValue); MOBLEUINT32 Get_StepResolutionValue(MOBLEUINT8 time_param); MOBLEUINT16 PwmValueMapping(MOBLEUINT16 setValue , MOBLEUINT16 maxRange , MOBLEINT16 minRange); @@ -125,7 +133,9 @@ MOBLEUINT16 PWM_CoolValue(float colourValue ,float brightValue); MOBLEUINT16 PWM_WarmValue(float colourValue ,float brightValue); void floatToInt(float in, displayFloatToInt_t *out_value, MOBLEINT32 dec_prec); void TraceHeader(const char* func_name, int mode); +#ifdef ENABLE_SAVE_MODEL_STATE_NVM MOBLE_RESULT SaveModelsStateNvm(MOBLEUINT8 flag); +#endif MOBLEUINT8 BLE_GetElementNumber(void); void Test_Process(void); diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/config_client.h b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/config_client.h index d5e73b5cd..ffdb5f4fd 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/config_client.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/config_client.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file config_client.h * @author BLE Mesh Team -* @version V1.11.000 -* @date 25-07-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Header file for the Config Model Client ****************************************************************************** * @attention @@ -46,15 +46,16 @@ /* Includes ------------------------------------------------------------------*/ #include "types.h" #include "ble_mesh.h" +#include "mesh_cfg.h" /* Exported macro ------------------------------------------------------------*/ #define CONFIG_CLIENT_UNICAST_ADDR 0x0001 -#define MAX_SIG_MODELS_PER_ELEMENT 12 // Number of SIG Models to support -#define MAX_VENDOR_MODELS_PER_ELEMENT 1 // Number of Vendor Models to support -#define MAX_ELEMENTS_PER_NODE 1 +#define MAX_SIG_MODELS_PER_ELEMENT 12 +#define MAX_VENDOR_MODELS_PER_ELEMENT 1 +#define MAX_ELEMENTS_PER_NODE APPLICATION_NUMBER_OF_ELEMENTS #define CONFIG_COMPOSITION_DATA_GET_PAGE_SIZE 1 #define COMPOSITION_PAGE0 0 @@ -63,9 +64,9 @@ #define APPKEY_SIZE 16 #define CONFIGURATION_START_DELAY 2000 -#define CONFIGCLIENT_RESPONSE_TIMEOUT 10000 /* 10 sec Timeout */ -#define CONFIGCLIENT_MAX_TRIALS 5 /* Attempt 5 times retries */ -#define CONFIGCLIENT_RE_TRIALS 3 +#define CONFIGCLIENT_RESPONSE_TIMEOUT 20000 /* 20 sec Timeout */ +#define CONFIGCLIENT_MAX_TRIALS 3 /* Attempt 3 times retries */ + #define CLIENT_TX_INPROGRESS 0 #define CLIENT_TX_TIMEOUT 1 @@ -77,26 +78,100 @@ #define SIG_MODEL_ID_HEALTH_SERVER 0x0002 #define SIG_MODEL_ID_HEALTH_CLIENT 0x0003 -/* 4.3.4.1 Alphabetical summary of opcodes */ +/* 4.3.4.2 Numerical summary of opcodes */ +#define OPCODE_CONFIG_APPKEY_ADD 0x00 +#define OPCODE_CONFIG_APPKEY_UPDATE 0x01 +#define OPCODE_CONFIG_COMPOSITION_DATA_STATUS 0x02 +#define OPCODE_CONFIG_CONFIG_MODEL_PUBLICATION_SET 0x03 +#define OPCODE_HEALTH_CURRENT_STATUS 0x04 +#define OPCODE_HEALTH_FAULT_STATUS 0x05 +#define OPCODE_CONFIG_HEARTBEAT_PUBLICATION_STATUS 0x06 +#define OPCODE_CONFIG_APPKEY_DELETE 0x8000 +#define OPCODE_CONFIG_APPKEY_GET 0x8001 +#define OPCODE_CONFIG_APPKEY_LIST 0x8002 +#define OPCODE_CONFIG_APPKEY_STATUS 0x8003 +#define OPCODE_HEALTH_ATTENTION_GET 0x8004 +#define OPCODE_HEALTH_ATTENTION_SET 0x8005 +#define OPCODE_HEALTH_ATTENTION_SET_UNACKNOWLEDGED 0x8006 +#define OPCODE_HEALTH_ATTENTION_STATUS 0x8007 #define OPCODE_CONFIG_COMPOSITION_DATA_GET 0x8008 -#define OPCODE_CONFIG_APPKEY_ADD 0x0000 -#define OPCODE_CONFIG_APPKEY_DELETE 0x8000 +#define OPCODE_CONFIG_BEACON_GET 0x8009 +#define OPCODE_CONFIG_BEACON_SET 0x800A +#define OPCODE_CONFIG_BEACON_STATUS 0x800B +#define OPCODE_CONFIG_DEFAULT_TTL_GET 0x800C +#define OPCODE_CONFIG_DEFAULT_TTL_SET 0x800D +#define OPCODE_CONFIG_DEFAULT_TTL_STATUS 0x800E +#define OPCODE_CONFIG_FRIEND_GET 0x800F +#define OPCODE_CONFIG_FRIEND_SET 0x8010 +#define OPCODE_CONFIG_FRIEND_STATUS 0x8011 +#define OPCODE_CONFIG_GATT_PROXY_GET 0x8012 +#define OPCODE_CONFIG_GATT_PROXY_SET 0x8013 +#define OPCODE_CONFIG_GATT_PROXY_STATUS 0x8014 +#define OPCODE_CONFIG_KEY_REFRESH_PHASE_GET 0x8015 +#define OPCODE_CONFIG_KEY_REFRESH_PHASE_SET 0x8016 +#define OPCODE_CONFIG_KEY_REFRESH_PHASE_STATUS 0x8017 +#define OPCODE_CONFIG_MODEL_PUBLICATION_GET 0x8018 +#define OPCODE_CONFIG_MODEL_PUBLICATION_STATUS 0x8019 +#define OPCODE_CONFIG_MODEL_PUBLICATION_VIRTUAL_ADDRESS_SET 0x801A +#define OPCODE_CONFIG_MODEL_SUBSCRIPTION_ADD 0x801B +#define OPCODE_CONFIG_MODEL_SUBSCRIPTION_DELETE 0x801C +#define OPCODE_CONFIG_MODEL_SUBSCRIPTION_DELETE_ALL 0x801D +#define OPCODE_CONFIG_MODEL_SUBSCRIPTION_OVERWRITE 0x801E +#define OPCODE_CONFIG_MODEL_SUBSCRIPTION_STATUS 0x801F +#define OPCODE_CONFIG_MODEL_SUBSCRIPTION_VIRTUAL_ADDRESS_ADD 0x8020 +#define OPCODE_CONFIG_MODEL_SUBSCRIPTION_VIRTUAL_ADDRESS_DELETE 0x8021 +#define OPCODE_CONFIG_MODEL_SUBSCRIPTION_VIRTUAL_ADDRESS_OVERWRITE 0x8022 +#define OPCODE_CONFIG_NETWORK_TRANSMIT_GET 0x8023 +#define OPCODE_CONFIG_NETWORK_TRANSMIT_SET 0x8024 +#define OPCODE_CONFIG_NETWORK_TRANSMIT_STATUS 0x8025 + +#define OPCODE_CONFIG_RELAY_GET 0x8026 +#define OPCODE_CONFIG_RELAY_SET 0x8027 +#define OPCODE_CONFIG_RELAY_STATUS 0x8028 + +#define OPCODE_CONFIG_SIG_MODEL_SUBSCRIPTION_GET 0x8029 +#define OPCODE_CONFIG_SIG_MODEL_SUBSCRIPTION_LIST 0x802A +#define OPCODE_CONFIG_VENDOR_MODEL_SUBSCRIPTION_GET 0x802B +#define OPCODE_CONFIG_VENDOR_MODEL_SUBSCRIPTION_LIST 0x802C +#define OPCODE_CONFIG_LOW_POWER_NODE_POLLTIMEOUT_GET 0x802D +#define OPCODE_CONFIG_LOW_POWER_NODE_POLLTIMEOUT_STATUS 0x802E + +#define OPCODE_HEALTH_FAULT_CLEAR 0x802F +#define OPCODE_HEALTH_FAULT_CLEAR_UNACKNOWLEDGED 0x8030 +#define OPCODE_HEALTH_FAULT_GET 0x8031 +#define OPCODE_HEALTH_FAULT_TEST 0x8032 +#define OPCODE_HEALTH_FAULT_TEST_UNACKNOWLEDGED 0x8033 +#define OPCODE_HEALTH_PERIOD_GET 0x8034 +#define OPCODE_HEALTH_PERIOD_SET 0x8035 +#define OPCODE_HEALTH_PERIOD_SET_UNACKNOWLEDGED 0x8036 +#define OPCODE_HEALTH_PERIOD_STATUS 0x8037 +#define OPCODE_CONFIG_HEARTBEAT_PUBLICATION_GET 0x8038 +#define OPCODE_CONFIG_HEARTBEAT_PUBLICATION_SET 0x8039 +#define OPCODE_CONFIG_HEARTBEAT_SUBSCRIPTION_GET 0x803A +#define OPCODE_CONFIG_HEARTBEAT_SUBSCRIPTION_SET 0x803B +#define OPCODE_CONFIG_HEARTBEAT_SUBSCRIPTION_STATUS 0x803C + #define OPCODE_CONFIG_MODEL_APP_BIND 0x803D +#define OPCODE_CONFIG_MODEL_APP_STATUS 0x803E +#define OPCODE_CONFIG_MODEL_APP_UNBIND 0x803F +#define OPCODE_CONFIG_NETKEY_ADD 0x8040 +#define OPCODE_CONFIG_NETKEY_DELETE 0x8041 +#define OPCODE_CONFIG_NETKEY_GET 0x8042 +#define OPCODE_CONFIG_NETKEY_LIST 0x8043 +#define OPCODE_CONFIG_NETKEY_STATUS 0x8044 +#define OPCODE_CONFIG_NETKEY_UPDATE 0x8045 +#define OPCODE_CONFIG_NODE_IDENTITY_GET 0x8046 +#define OPCODE_CONFIG_NODE_IDENTITY_SET 0x8047 + +#define OPCODE_CONFIG_NODE_IDENTITY_STATUS 0x8048 +#define OPCODE_CONFIG_NODE_RESET 0x8049 +#define OPCODE_CONFIG_NODE_RESET_STATUS 0x804A +#define OPCODE_CONFIG_SIG_MODEL_APP_GET 0x804B +#define OPCODE_CONFIG_SIG_MODEL_APP_LIST 0x804C +#define OPCODE_CONFIG_VENDOR_MODEL_APP_GET 0x804D +#define OPCODE_CONFIG_VENDOR_MODEL_APP_LIST 0x804E + -#define OPCODE_CONFIG_MODEL_APP_UNBIND 0x803F -#define OPCODE_CONFIG_MODEL_PUBLI_GET 0x8018 -#define OPCODE_CONFIG_MODEL_PUBLI_SET 0x03 -#define OPCODE_CONFIG_MODEL_SUBSCR_ADD 0x801B -#define OPCODE_CONFIG_MODEL_SUBSCR_DEL 0x801C -#define OPCODE_CONFIG_MODEL_SUBSCR_DEL_ALL 0x801D -#define OPCODE_CONFIG_MODEL_SUBSCR_OWR 0x801E - -/* Status message list : These are required for Node configuration */ -#define OPCODE_CONFIG_COMPOSITION_DATA_STATUS 0x02 -#define OPCODE_CONFIG_APPKEY_STATUS 0x8003 -#define OPCODE_CONFIG_SUBSCRIPTION_STATUS 0x801F -#define OPCODE_CONFIG_MODEL_PUBLI_STATUS 0x8019 -#define OPCODE_CONFIG_MODEL_APP_STATUS 0x803E /* Macros for usage in models ************************************************/ @@ -144,11 +219,6 @@ typedef struct { } Composition_Header_Page0_t; #pragma pack(4) -/* -#define MAX_SIG_MODELS_PER_ELEMENT 10 // Number of SIG Models to support -#define MAX_VENDOR_MODELS_PER_ELEMENT 1 // Number of Vendor Models to support -#define MAX_ELEMENTS_PER_NODE 1 -*/ #define DEVICE_COMPOSITION_HEADER_SIZE sizeof(Composition_Header_Page0_t) #define DEVICE_COMPOSITION_ELEMENTS_DESC sizeof(Elements_Page0_t) @@ -157,11 +227,11 @@ typedef struct { #pragma pack(1) typedef struct { Composition_Header_Page0_t sheader; - //Elements_Page0_t aNodeElements[MAX_ELEMENTS_PER_NODE]; } _Composition_Data_Page0_t; #pragma pack(4) -//#pragma pack(1) + + typedef union { _Composition_Data_Page0_t sComposition_Data_Page0; MOBLEUINT8 aComposition_Data_Page0[DEVICE_COMPOSITION_MAX_SIZE]; @@ -269,6 +339,7 @@ typedef enum typedef enum { NodeIdle_State, + NodeSendMessage_State, InProgress_State, CompositionRecd_State, CompositionRecdCompleted_State, @@ -280,7 +351,8 @@ typedef enum SubscriptionAckCompleted_State, PublicationStatus_State, PublicationStatusCompleted_State, - NodeNoResponse_State + NodeNoResponse_State, + NodeResetStatus_State }eServerRespRecdState_t; @@ -309,6 +381,18 @@ typedef enum InvalidBindingStatus = 0x11, } ConfigModelStatusCode_t; +typedef struct +{ + MOBLEUINT16 opcode; +// MOBLEBOOL reliable; + MOBLEUINT8 min_payload_size; + MOBLEUINT8 max_payload_size; + const MOBLEUINT8 *pDefaultParam; +// MOBLEUINT16 response_opcode; +// MOBLEUINT16 min_response_size; +// MOBLEUINT16 max_response_size; +} MODEL_CONFIG_CLIENT_OpcodeTableParam_t; + /******************************************************************************/ /********** Following Section defines the Opcodes for the Messages ************/ /******************************************************************************/ @@ -336,6 +420,7 @@ MOBLEUINT8 ConfigClient_GetNodeElements(void); MOBLEUINT16 GetSIGModelFromCompositionData(MOBLEUINT8 elementIdx, MOBLEUINT8 idxSIG); MOBLEUINT32 GetVendorModelFromCompositionData(MOBLEUINT8 elementIdx, MOBLEUINT8 idxVendor); MOBLEUINT16 GetNodeElementAddress(void); +MOBLEUINT16 GetServerElementAddress(MOBLEUINT8 elementIndex); MOBLEUINT8 GetTotalSIGModelsCount(MOBLEUINT8 elementIdx); MOBLEUINT8 GetTotalVendorModelsCount(MOBLEUINT8 elementIdx); MOBLEUINT8 GetNumberofSIGModels(MOBLEUINT8 elementIdx); @@ -343,6 +428,7 @@ MOBLEUINT8 GetNumberofVendorModels(MOBLEUINT8 elementIdx); void SetSIGModelCountToConfigure(MOBLEUINT8 count); void SetVendorModelCountToConfigure(MOBLEUINT8 count); MOBLEUINT8 ConfigClient_ChkRetrialState (eServerRespRecdState_t* eRespRecdState); +MOBLEUINT8 ConfigClient_ChkRetries (void); void ConfigClient_SaveMsgSendingTime (void); void ConfigClient_ResetTrials (void); void ConfigClient_ErrorState (void); @@ -360,7 +446,8 @@ MOBLE_RESULT _ConfigClient_ModelAppBind (configClientModelAppBind_t* modelAppBin MOBLE_RESULT ConfigClient_ModelAppStatus(MOBLEUINT8 const *pSrcModelAppStatus, MOBLEUINT32 length); - +MOBLE_RESULT ConfigClient_NodeReset (MOBLEUINT16 elementAddress); +void Appli_NodeResetStatusCb(void); MOBLE_RESULT ConfigClient_SubscriptionAdd (MOBLEUINT16 elementAddress, MOBLEUINT16 appKeyIndex, MOBLEUINT32 modelIdentifier); diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/generic.h b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/generic.h index 0d7e3c890..d4240f8b7 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/generic.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/generic.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file generic.h * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Header file for the user application file ****************************************************************************** * @attention @@ -222,13 +222,12 @@ #define APPLI_LED_OFF 0X00 #define APPLI_LED_ON 0X01 -#define INTENSITY_LEVEL_ZERO 0X00 -#define INTENSITY_LEVEL_FULL 31990U #define NO_TRANSITION 0X01 #define IN_TRANSITION 0X02 #define DEFAULT_TRANSITION 0X03 +#define No_NVM_FLAG 0XFE #define GENERIC_ON_OFF_NVM_FLAG 0X01 #define GENERIC_LEVEL_NVM_FLAG 0X02 @@ -329,6 +328,13 @@ typedef struct MOBLEUINT8 DefaultTransitionTime; }Generic_DefaultTransitionParam_t; +typedef union +{ + Generic_LevelParam_t sGeneric_LevelParam; + MOBLEUINT8 a_Level_param[sizeof(Generic_LevelParam_t)]; +} _Generic_LevelParam; + +/******************************************************/ typedef struct { /* Pointer to the function Appli_Generic_OnOff_Set used for callback @@ -336,6 +342,7 @@ typedef struct */ MOBLE_RESULT (*OnOff_Set_cb)(Generic_OnOffStatus_t*, uint8_t); + MOBLE_RESULT (*OnOff_Status_cb)(MOBLEUINT8 const *, MOBLEUINT32); /* Pointer to the function Appli_Generic_Level_Set used for callback from the middle layer to Application layer */ @@ -351,16 +358,22 @@ typedef struct */ MOBLE_RESULT (*LevelDeltaMove_Set_cb)(Generic_LevelStatus_t*, MOBLEUINT8); + MOBLE_RESULT (*Level_Status_cb)(MOBLEUINT8 const *, MOBLEUINT32); /* Pointer to the function Appli_Generic_PowerOnOff_Set used for callback from the middle layer to Application layer */ MOBLE_RESULT (*GenericPowerOnOff_cb)(Generic_PowerOnOffParam_t*, MOBLEUINT8); + MOBLE_RESULT (*GenericPowerOnOff_Status_cb)(MOBLEUINT8 const *, MOBLEUINT32); + + void (*GenericRestorePowerOnOff_cb)(MOBLEUINT8); + /* Pointer to the function Generic_DefaultTransitionTime_Set used for callback from the middle layer to Application layer */ MOBLE_RESULT (*GenericDefaultTransition_cb)(Generic_DefaultTransitionParam_t*, MOBLEUINT8); + MOBLE_RESULT (*GenericDefaultTransition_Status_cb)(MOBLEUINT8 const *, MOBLEUINT32); } Appli_Generic_cb_t; typedef struct @@ -418,7 +431,7 @@ MOBLE_RESULT GenericModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, MOBLEUINT32 length, MOBLEBOOL response); void Generic_Process(void); -void Generic_Publish(MOBLE_ADDRESS publishAddr, MOBLEUINT8 elementIndex); +void Generic_Publish(MOBLE_ADDRESS srcAddress); MOBLE_RESULT BLEMesh_AddGenericModels(void); @@ -445,7 +458,6 @@ MOBLE_RESULT Generic_Client_OnOff_Status(MOBLEUINT8 const *pOnOff_status, MOBLEU MOBLE_RESULT Generic_Client_Level_Status(MOBLEUINT8 const *plevel_status, MOBLEUINT32 plength); MOBLE_RESULT Generic_Client_PowerOnOff_Status(MOBLEUINT8 const *powerOnOff_status , MOBLEUINT32 plength); MOBLE_RESULT Generic_Client_DefaultTransitionTime_Status(MOBLEUINT8 const *pTransition_status , MOBLEUINT32 plength); - #endif /* __GENERIC_H */ /******************* (C) COPYRIGHT 2017 STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/generic_client.h b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/generic_client.h index cabad069c..f26cd4227 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/generic_client.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/generic_client.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file generic_client.h * @author BLE Mesh Team -* @version V1.11.000 -* @date 25-07-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Header file for the user application file ****************************************************************************** * @attention @@ -49,6 +49,13 @@ /* Exported macro ------------------------------------------------------------*/ +/* Variable-------------------------------------------------------------------*/ +#pragma pack(1) +typedef union +{ + Generic_OnOffParam_t sGeneric_OnOffParam; + MOBLEUINT8 a_OnOff_param[sizeof(Generic_OnOffParam_t)]; +} _Generic_OnOffParam; /******************************************************************************/ /********** Following Section defines the Opcodes for the Messages ************/ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/light.h b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/light.h index 45377dbe0..ea6a5a330 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/light.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/light.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file light.h * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Header file for the Lighting Model file ****************************************************************************** * @attention @@ -176,7 +176,6 @@ #define TRANSITION_SCALER 1 #define PWM_DEFAULT_VALUE 10000U #define PWM_VALUE_OFF 1 - /******************************************************************************/ /* Macros are used to update the PWM state according to the condition. */ #define RESUME_STATE 1 @@ -184,7 +183,6 @@ #define DEFAULT_STATE 3 #define LOAD_STATE 4 - /* Macros for the Light model transition flag */ #define LIGHT_TRANSITION_STOP 0X00 #define LIGHT_LIGHTNESS_TRANSITION_START 0X01 @@ -321,6 +319,13 @@ typedef struct MOBLEUINT8 RemainingTime; }Light_HslStatus_t; +typedef struct +{ + MOBLEUINT16 HslHueDefault16; + MOBLEUINT16 HslSaturationDefault16; + MOBLEUINT16 HslLightnessDefualt16; +}Light_HslDefault_t; + typedef struct { MOBLEUINT16 HslHueMinRange16; @@ -336,65 +341,92 @@ typedef struct */ MOBLE_RESULT (*Lightness_Set_cb)(Light_LightnessStatus_t*, MOBLEUINT8); + MOBLE_RESULT (*Lightness_Status_cb)(MOBLEUINT8 const *, MOBLEUINT32); + /* Pointer to the function Appli_Light_Lightness_Linear_Set used for callback from the middle layer to Application layer */ MOBLE_RESULT (*Lightness_Linear_Set_cb)(Light_LightnessStatus_t*, MOBLEUINT8); + MOBLE_RESULT (*Lightness_Linear_Status_cb)(MOBLEUINT8 const *, MOBLEUINT32); + + /* Pointer to the function Appli_Light_Lightness_Default_Set used for callback from the middle layer to Application layer */ MOBLE_RESULT (*Lightness_Default_Set_cb)(Light_LightnessDefaultParam_t*, MOBLEUINT8); + MOBLE_RESULT (*Lightness_Default_Status_cb)(MOBLEUINT8 const *, MOBLEUINT32); + /* Pointer to the function Appli_Light_Lightness_Range_Set used for callback from the middle layer to Application layer */ MOBLE_RESULT (*Lightness_Range_Set_cb)(Light_LightnessRangeParam_t*, MOBLEUINT8); + MOBLE_RESULT (*Lightness_Range_Status_cb)(MOBLEUINT8 const *, MOBLEUINT32); + /* Pointer to the function Appli_Light_Ctl_Set used for callback from the middle layer to Application layer */ MOBLE_RESULT (*Light_Ctl_Set_cb)(Light_CtlStatus_t*, MOBLEUINT8); + MOBLE_RESULT (*Light_Ctl_Status_cb)(MOBLEUINT8 const *, MOBLEUINT32); + /* Pointer to the function Appli_Light_CtlTemperature_Set used for callback from the middle layer to Application layer */ MOBLE_RESULT (*Light_CtlTemperature_Set_cb)(Light_CtlStatus_t*, MOBLEUINT8); + MOBLE_RESULT (*Light_CtlTemperature_Status_cb)(MOBLEUINT8 const *, MOBLEUINT32); + /* Pointer to the function Appli_Light_CtlTemperature_Range_Set used for callback from the middle layer to Application layer */ MOBLE_RESULT (*Light_CtlTemperature_Range_Set_cb)(Light_CtlTemperatureRangeParam_t*, MOBLEUINT8); + MOBLE_RESULT (*Light_CtlTemperature_Range_Status_cb)(MOBLEUINT8 const *, MOBLEUINT32); + /* Pointer to the function Appli_Light_CtlDefault_Set used for callback from the middle layer to Application layer */ MOBLE_RESULT (*Light_CtlDefault_Set_cb)(Light_CtlDefaultParam_t*, MOBLEUINT8); + MOBLE_RESULT (*Light_CtlDefault_Status_cb)(MOBLEUINT8 const *, MOBLEUINT32); + /* Pointer to the function Appli_Light_Hsl_Set used for callback from the middle layer to Application layer */ MOBLE_RESULT (*Light_Hsl_Set_cb)(Light_HslStatus_t*, MOBLEUINT8); + MOBLE_RESULT (*Light_Hsl_Status_cb)(MOBLEUINT8 const *, MOBLEUINT32); + /* Pointer to the function Appli_Light_HslHue_Set used for callback from the middle layer to Application layer */ MOBLE_RESULT (*Light_HslHue_Set_cb)(Light_HslStatus_t*, MOBLEUINT8); + MOBLE_RESULT (*Light_HslHue_Status_cb)(MOBLEUINT8 const *, MOBLEUINT32); + /* Pointer to the function Appli_Light_HslSaturation_Set used for callback from the middle layer to Application layer */ MOBLE_RESULT (*Light_HslSaturation_Set_cb)(Light_HslStatus_t*, MOBLEUINT8); + MOBLE_RESULT (*Light_HslSaturation_Status_cb)(MOBLEUINT8 const *, MOBLEUINT32); + /* Pointer to the function Appli_Light_HslDefault_Set used for callback from the middle layer to Application layer */ MOBLE_RESULT (*Light_HslDefault_Set_cb)(Light_HslStatus_t*, MOBLEUINT8); + MOBLE_RESULT (*Light_HslDefault_Status_cb)(MOBLEUINT8 const *, MOBLEUINT32); + /* Pointer to the function Appli_Light_HslRange_Set used for callback from the middle layer to Application layer */ MOBLE_RESULT (*Light_HslRange_Set_cb)(Light_HslRangeParam_t*, MOBLEUINT8); + + MOBLE_RESULT (*Light_HslRange_Status_cb)(MOBLEUINT8 const *, MOBLEUINT32); } Appli_Light_cb_t; typedef struct @@ -413,6 +445,7 @@ typedef struct MOBLE_RESULT (*GetLightHslSaturation_cb)(MOBLEUINT8*); MOBLE_RESULT (*GetLightHslHueRange_cb)(MOBLEUINT8*); MOBLE_RESULT (*GetLightHslSatRange_cb)(MOBLEUINT8*); + MOBLE_RESULT (*GetLightHslDefault_cb)(MOBLEUINT8*); }Appli_Light_GetStatus_cb_t; #pragma pack(4) @@ -529,7 +562,6 @@ MOBLE_RESULT Light_Client_HslTarget_Status(MOBLEUINT8 const *pHslTarget_status, MOBLE_RESULT Light_Client_HslHue_Status(MOBLEUINT8 const *pHslHue_status, MOBLEUINT32 pLength); MOBLE_RESULT Light_Client_HslSaturation_Status(MOBLEUINT8 const *pHslSaturation_status, MOBLEUINT32 pLength); - #endif /* __LIGHT_MODEL_H */ /******************* (C) COPYRIGHT 2017 STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/light_client.h b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/light_client.h new file mode 100644 index 000000000..b51ad5b62 --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/light_client.h @@ -0,0 +1,92 @@ +/** +****************************************************************************** +* @file light_client.h +* @author BLE Mesh Team +* @version V1.12.000 +* @date 06-12-2019 +* @brief Header file for the user application file +****************************************************************************** +* @attention +* +*

    © COPYRIGHT(c) 2017 STMicroelectronics

    +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* Initial BlueNRG-Mesh is built over Motorolas Mesh over Bluetooth Low Energy +* (MoBLE) technology. The present solution is developed and maintained for both +* Mesh library and Applications solely by STMicroelectronics. +* +****************************************************************************** +*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __LIGHT_CLIENT_H +#define __LIGHT_CLIENT_H + +/* Includes ------------------------------------------------------------------*/ +#include "types.h" +#include "ble_mesh.h" + + +/* Exported macro ------------------------------------------------------------*/ +/* Variable ------------------------------------------------------------------*/ +#pragma pack(1) +typedef union { + Light_LightnessParam_t sLight_LightnessParam; + MOBLEUINT8 a_Lightness_param[sizeof(Light_LightnessParam_t)]; +} _Light_LightnessParam; +/******************************************************************************/ +/********** Following Section defines the Opcodes for the Messages ************/ +/******************************************************************************/ + + +/* Exported Functions Prototypes ---------------------------------------------*/ +MOBLE_RESULT LightModelClient_GetOpcodeTableCb(const MODEL_OpcodeTableParam_t **data, + MOBLEUINT16 *length); + +MOBLE_RESULT LightModelClient_GetStatusRequestCb(MOBLE_ADDRESS peer_addr, + MOBLE_ADDRESS dst_peer, + MOBLEUINT16 opcode, + MOBLEUINT8 *pResponsedata, + MOBLEUINT32 *plength, + MOBLEUINT8 const *pRxData, + MOBLEUINT32 dataLength, + MOBLEBOOL response); + +MOBLE_RESULT LightModelClient_ProcessMessageCb(MOBLE_ADDRESS peer_addr, + MOBLE_ADDRESS dst_peer, + MOBLEUINT16 opcode, + MOBLEUINT8 const *pRxData, + MOBLEUINT32 dataLength, + MOBLEBOOL response + ); + +MOBLE_RESULT LightClient_Lightness_Set_Unack(MOBLE_ADDRESS element_number, + _Light_LightnessParam *pLightness_param, + MOBLEUINT32 length); +MOBLE_RESULT Light_Client_Lightness_Status(MOBLEUINT8 const *pLightness_status, MOBLEUINT32 plength); + +#endif /* __LIGHT_CLIENT_H */ + +/******************* (C) COPYRIGHT 2017 STMicroelectronics *****END OF FILE****/ + diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/light_lc.h b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/light_lc.h index 17e82c412..38f176cb6 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/light_lc.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/light_lc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file light_control.h * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Header file for the user application file ****************************************************************************** * @attention @@ -94,25 +94,29 @@ #define LIGHT_CONTROL_TIME_PROLONG_ID 0X003B #define LIGHT_CONTROL_TIME_RUN_ON_ID 0X003C -/* Exported variables ------------------------------------------------------- */ +/* Macros ------------------------------------------------------- */ #define LIGHT_CONTROL_AMBIENT_LUXLEVEL_ON 0XEA60 #define LIGHT_CONTROL_AMBIENT_LUXLEVEL_PROLONG 0XC350 #define LIGHT_CONTROL_AMBIENT_LUXLEVEL_STANDBY 0X0000 #define LIGHT_CONTROL_LIGHTNESS_ON_VALUE 0xFFFF -#define LIGHT_CONTROL_LIGHTNESS_PROLONG_VALUE 0xFFF/*0x7FFF*/ +#define LIGHT_CONTROL_LIGHTNESS_PROLONG_VALUE 0x3A98 #define LIGHT_CONTROL_LIGHTNESS_STANDBY_VALUE 0x01 -#define LIGHT_CONTROL_TIME_FADE_ON_VALUE 0x0a -#define LIGHT_CONTROL_TIME_RUN_ON_VALUE 0x2710 -#define LIGHT_CONTROL_TIME_FADE_VALUE 0x0a -#define LIGHT_CONTROL_TIME_PROLONG_VALUE 0X1388 -#define LIGHT_CONTROL_TIME_FADE_STANDBY_AUTO_VALUE 0x0a -#define LIGHT_CONTROL_TIME_FADE_STANDBY_MANUAL_VALUE 0X0a +#define LIGHT_CONTROL_TIME_FADE_ON_VALUE 0xa /* 20 steps */ +#define LIGHT_CONTROL_TIME_RUN_ON_VALUE 0x1388 /* 5 second */ +#define LIGHT_CONTROL_TIME_FADE_VALUE 0Xa +#define LIGHT_CONTROL_TIME_PROLONG_VALUE 0X0bb8 /* 3 second */ +#define LIGHT_CONTROL_TIME_FADE_STANDBY_AUTO_VALUE 0xa +#define LIGHT_CONTROL_TIME_FADE_STANDBY_MANUAL_VALUE 0Xa #define LIGHT_CONTROL_KID 0X01 #define LIGHT_CONTROL_KIU 0X02 #define LIGHT_CONTROL_KPD 0X03 #define LIGHT_CONTROL_KPU 0X04 #define LIGHT_CONTROL_REGULATOR_ACCURACY_VALUE 0X100 +/* Property IDs by SIG ------------------------------------------------------- */ +#define MOTION_SENSED_PROPERTY 0X0042 +#define PEOPLE_COUNT_PROPERTY 0X004C +#define PRESENCE_DETECTED_PROPERTY 0X004D #define TRANSITION_STEP_VALUE 0X0A #define LC_MODE_ENABLE 0X01 @@ -188,12 +192,6 @@ typedef struct MOBLEUINT32 TotalTime; }Light_LC_TimeParam_t; -/* Transition Flag variables */ -typedef struct -{ - MOBLEUINT8 LightLcTransitionFlag; - MOBLEUINT8 LightLcOptionalParam; -}Light_LC_ModelFlag_t; #pragma pack(4) /* Light LC state machine states */ @@ -241,7 +239,7 @@ typedef struct /* Pointer to the function Appli_LightLC_OnOff_Set used for callback from the middle layer to Application layer */ - MOBLE_RESULT (*LightLC_OnOff_Set_cb)(Light_LC_OnOffState_t*, MOBLEUINT8); + MOBLE_RESULT (*LightLC_OnOff_Set_cb)(Light_LC_Param_t*, MOBLEUINT8); /* Pointer to the function Appli_LightLC_Property_Set used for callback from the middle layer to Application layer diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/meshdfu_node.h b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/meshdfu_node.h index a883ef5dd..5d60d20c7 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/meshdfu_node.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/meshdfu_node.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file meshdfu_node.h * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-May-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief BLE-Mesh Device Firmware Upgrade/ FOTA over the mesh header file ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/sensors.h b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/sensors.h index e65f07ca6..2345ba211 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/sensors.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/sensors.h @@ -1,9 +1,9 @@ /** ****************************************************************************** -* @file sensor.h +* @file sensors.h * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Header file for the user application file ****************************************************************************** * @attention @@ -53,12 +53,23 @@ /********** Following Section defines the Opcodes for the Messages ************/ /******************************************************************************/ /* Sensors Property ID */ -#define TEMPERATURE_PID 0x0071// 0x004F +#define TEMPERATURE_PID 0x0071 #define PRESSURE_PID 0x2A6D #define HUMIDITY_PID 0x2A6F +#define TIME_OF_FLIGHT_PID 0X2A7F #define MAGNETO_METER_PID 0x2AA1 #define ACCELERO_METER_PID 0x2BA1 #define GYROSCOPE_PID 0x2BA2 +#define VOLTAGE_PID 0x0005 +#define CURRENT_PID 0x0004 +#define POWER_FACTOR_PID 0x0072 +#define ACTIVE_POWER_PID 0x0073 +#define REACTIVE_POWER_PID 0x0074 +#define APPARENT_POWER_PID 0x0075 +#define ACTIVE_ENERGY_PID 0x0083 +#define REACTIVE_ENERGY_PID 0x0084 +#define APPARENT_ENERGY_PID 0x0085 + /* 7.1 Messages summary Page 300 */ /* Sensor Server Model Opcode */ @@ -100,7 +111,7 @@ /* structure for the Property id for the sensors Present inside the firmware. */ -#pragma pack(1) +#pragma pack(4) typedef struct { MOBLEUINT16 Property_ID; @@ -131,7 +142,7 @@ typedef struct }Sensor_SettingParam_t; /* Sensor Coloumn Parameters */ - +#pragma pack(1) typedef struct { MOBLEUINT16 Property_ID; @@ -164,6 +175,7 @@ typedef struct } Appli_Sensor_cb_t; + /* function pointer for application to get the value from application to middle layer file */ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/time_scene.h b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/time_scene.h index c602ace81..6cb268aa4 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/time_scene.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/time_scene.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file time_scene.h * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Header file for the user application file ****************************************************************************** * @attention @@ -77,10 +77,10 @@ /******************************************************************************/ /********** Following Section defines the SIG MODEL IDs ************/ /******************************************************************************/ -#define TIME_SERVER 0X1200 -#define TIME_SETUP_SERVER 0X1201 -#define SCENE_SERVER 0X1203 -#define SCENE_SETUP_SERVER 0X1204 +#define TIME_MODEL_SERVER_MODEL_ID 0X1200 +#define TIME_MODEL_SERVER_SETUP_MODEL_ID 0X1201 +#define SCENE_MODEL_SERVER_MODEL_ID 0X1203 +#define SCENE_MODEL_SERVER_SETUP_MODEL_ID 0X1204 /******************************************************************************/ /********** SIG MODEL IDs ends ************/ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/vendor.h b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/vendor.h index b0b4cee7b..651d0df0c 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/vendor.h +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Inc/vendor.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file vendor.h * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Header file for the user application file ****************************************************************************** * @attention @@ -65,8 +65,14 @@ #define APPLI_LED_CONTROL_STATUS_CMD 0x3U #define APPLI_ELEMENT_TYPE_CMD 0x4U #define APPLI_SENSOR_CNTRL_CMD 0X5U +#define APPLI_DATA_CNTRL_CMD 0xEU /******************************************************************************/ +/****************Data Received from Android/iOS. B0 = SubCommand***************/ +/********************* Sub Commands for APPLI_DATA_WRITE*************************/ +#define APPLI_STRING_WRITE 0X01 +#define APPLI_STRING_READ 0X02 + /****************Data Received from Android/iOS. B0 = SubCommand***************/ /********************* Sub Commands for APPLI_TEST_CMD*************************/ #define APPLI_RESET_TEST_PARAMETERS 0x01U @@ -75,6 +81,8 @@ #define APPLI_TEST_COUNTER 0x04U #define APPLI_TEST_INC_COUNTER 0x05U #define APPLI_MODEL_PUBLISH_SELECT 0X06U +#define APPLI_OTA_ENABLE 0x07U +#define APPLI_OTA_ENTER 0x08U /******************************************************************************/ /****************Data Received from Android/IoS. B0 = SubCommand***************/ @@ -113,6 +121,8 @@ #define PRESS_SENSOR 0X2U #define ACCEL_SENSOR 0X3U /******************************************************************************/ +#define VENDOR_DATA_BYTE 50 +#define R_ASCI_CODE 0X52 #define DEFAULT_DELAY_PACKET_FROM 500U #define DEFAULT_DELAY_PACKET_RANDOM_TIME 500U @@ -141,7 +151,7 @@ typedef struct MOBLE_RESULT (*TestCommand_cb)(MOBLEUINT8 const *, MOBLEUINT32); void (*LEDControl_cb)(void); void (*GetTestCount)(MOBLEUINT8*); - + MOBLE_RESULT (*DataControlCommand_cb)(MOBLEUINT8 const *, MOBLEUINT32); } Appli_Vendor_cb_t; #pragma pack(4) @@ -161,7 +171,7 @@ MOBLE_RESULT Vendor_OnResponseDataCb(MOBLE_ADDRESS peer_addr, MOBLE_ADDRESS dst_ MOBLEUINT32 dataLength, MOBLEBOOL response); void Vendor_Process(void); -void Vendor_Publish(MOBLE_ADDRESS publishAddr, MOBLEUINT8 elementIndex); +void Vendor_Publish(MOBLE_ADDRESS srcAddress); void Vendor_TestRemoteData(MOBLE_ADDRESS src,MOBLE_ADDRESS dst,MOBLEUINT8 elementIndex); void Vendor_TestCounterInc(MOBLE_ADDRESS src ,MOBLE_ADDRESS dst ,MOBLEUINT8 elementIndex); @@ -186,7 +196,6 @@ MOBLE_RESULT VendorModel_PID1_ProcessMessageCb(MOBLE_ADDRESS peer_addr, MOBLEBOOL response ); - #endif /* __VENDOR_H */ /******************* (C) COPYRIGHT 2017 STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/blob.c b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/blob.c index 48d0fbd09..3d487aef2 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/blob.c +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/blob.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file blob.c * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-May-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief BLE-Mesh Block transfer Server implementation ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/common.c b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/common.c index 9ac302ba4..7328a65eb 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/common.c +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/common.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file common.c * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Model middleware file ****************************************************************************** * @attention @@ -47,6 +47,8 @@ #include "vendor.h" #include "light_lc.h" #include +#include "appli_nvm.h" +#include "compiler.h" /** @addtogroup MODEL_GENERIC @@ -57,13 +59,23 @@ * @{ */ +WEAK_FUNCTION(MOBLE_RESULT ApplicationGetConfigServerDeviceKey(MOBLE_ADDRESS src, + const MOBLEUINT8**ppkeyTbUse)); +MOBLEUINT8 TimeDelay(MOBLEUINT16 waitPeriod); + /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ +#ifdef ENABLE_SAVE_MODEL_STATE_NVM extern const APPLI_SAVE_MODEL_STATE_CB SaveModelState_cb; +#endif extern MOBLEUINT8 NumberOfElements; MOBLEUINT8 PowerOnOff_flag = FLAG_RESET; -extern MOBLEUINT8 RestoreFlag; +MOBLEUINT8 RestoreFlag; +MOBLE_ADDRESS Peer_Addrs; +MOBLE_ADDRESS Dst_Addrs; +MOBLEUINT8 Tid_Value = 0; +MOBLEUINT8 TidSend = 0; /** * @brief Chk_ParamValidity: This function is to check validity of Parameters * @param param: Parameter @@ -340,6 +352,54 @@ MOBLEUINT16 PwmValueMapping(MOBLEUINT16 setValue , MOBLEUINT16 maxRange , MOBLEI MOBLEUINT16 percentValue; MOBLEUINT16 duty; +#ifdef SMART_PLUG + percentValue = (setValue * 100)/ (maxRange - minRange); + + if(percentValue < 2) + { + duty = 0; + } + else if((percentValue > 2) && (percentValue <= 10)) + { + duty = 1; + } + else if((percentValue > 10) && (percentValue <= 20)) + { + duty = 2; + } + else if((percentValue > 20) && (percentValue <= 30)) + { + duty = 3; + } + else if((percentValue > 30) && (percentValue <= 40)) + { + duty = 4; + } + else if((percentValue > 40) && (percentValue <= 50)) + { + duty = 5; + } + else if((percentValue > 50) && (percentValue <= 60)) + { + duty = 6; + } + else if((percentValue > 60) && (percentValue <= 70)) + { + duty = 7; + } + else if((percentValue > 70) && (percentValue <= 80)) + { + duty = 8; + } + else if((percentValue > 80) && (percentValue <= 90)) + { + duty = 9; + } + else if(percentValue > 90) + { + duty = 10; + } +#else if(minRange > 0x00) { percentValue = (setValue - 800)/ (maxRange - minRange); @@ -360,6 +420,7 @@ MOBLEUINT16 PwmValueMapping(MOBLEUINT16 setValue , MOBLEUINT16 maxRange , MOBLEI { duty = 1; } +#endif return duty; } @@ -441,6 +502,7 @@ void TraceHeader(const char* func_name, int mode) printf("%ld %s - <<>>", Clock_Time(), func_name); } +#ifdef ENABLE_SAVE_MODEL_STATE_NVM /** * @brief Prepare and save buffer of Generic and Light models state in NVM * @param void @@ -448,8 +510,8 @@ void TraceHeader(const char* func_name, int mode) */ MOBLE_RESULT SaveModelsStateNvm(MOBLEUINT8 flag) { - MOBLEUINT8 Model_GetBuff[APP_NVM_MODEL_SIZE];/* 16 bytes for generic model and 16 bytes for light model */ MOBLE_RESULT result = MOBLE_RESULT_FAIL; + MOBLEUINT8 Model_GetBuff[APP_NVM_MODEL_SIZE];/* 16 bytes for generic model and 16 bytes for light model */ memset(Model_GetBuff, 0x00, APP_NVM_MODEL_SIZE); @@ -477,6 +539,8 @@ MOBLE_RESULT SaveModelsStateNvm(MOBLEUINT8 flag) #ifdef ENABLE_LIGHT_MODEL_SERVER_HSL (Appli_Light_GetStatus_cb.GetLightHsl_cb)(Model_GetBuff+GENERIC_DATA_LIMIT+LIGHT_HSL_NVM_OFFSET); + (Appli_Light_GetStatus_cb.GetLightHslDefault_cb)(Model_GetBuff+GENERIC_DATA_LIMIT+LIGHT_HSL_DEFAULT_NVM_OFFSET); + #endif if (SaveModelState_cb != NULL) { @@ -494,7 +558,7 @@ MOBLE_RESULT SaveModelsStateNvm(MOBLEUINT8 flag) return result; } - +#endif /* * @brief function to call light middle layer function for restoration of * saved states. @@ -511,6 +575,34 @@ void Model_RestoreStates(MOBLEUINT8 const *pModelState_Load, MOBLEUINT8 size) #ifdef ENABLE_GENERIC_MODEL_SERVER_ONOFF case GENERIC_ON_OFF_NVM_FLAG: { +//#ifdef STM32 +/* checking the Power on off retrieved value according to the given + in standered and taking decision for Generic on off. + */ + ////////krt + // MOBLEUINT8 pData[2]; + +// if(pModelState_Load[4] == GENERIC_POWER_OFF_STATE) +// { +// pData[0] = APPLI_LED_OFF; +// Generic_OnOff_Set(pData,1); +// } +// else if(pModelState_Load[4] == GENERIC_POWER_ON_STATE) +// { +// pData[0] = APPLI_LED_ON; +// Generic_OnOff_Set(pData,1); +// } +// else if(pModelState_Load[4] == GENERIC_POWER_RESTORE_STATE) +// { + Generic_OnOff_Set(pModelState_Load+GENERIC_ON_OFF_NVM_OFFSET, 1); + // } +// else +// { +// TRACE_M(TF_GENERIC, "Power On Off value invalid %d \r\n", pModelState_Load[0]); +// } +// Generic_PowerOnOff_Set(pModelState_Load+GENERIC_POWER_ON_OFF_NVM_OFFSET, 1); +// break; +//#elif BLUENRG2_DEVICE /* checking the Power on off retrieved value according to the given in standered and taking decision for Generic on off. */ @@ -536,6 +628,7 @@ void Model_RestoreStates(MOBLEUINT8 const *pModelState_Load, MOBLEUINT8 size) } break; +//#endif } #endif @@ -566,16 +659,36 @@ void Model_RestoreStates(MOBLEUINT8 const *pModelState_Load, MOBLEUINT8 size) #ifdef ENABLE_LIGHT_MODEL_SERVER_HSL case LIGHT_HSL_NVM_FLAG: { + + if((pModelState_Load[4] == GENERIC_POWER_OFF_STATE) || (pModelState_Load[4] == GENERIC_POWER_ON_STATE)) + { + Light_Hsl_Set((pModelState_Load+GENERIC_DATA_LIMIT+LIGHT_HSL_DEFAULT_NVM_OFFSET), 6); + } + else if(pModelState_Load[4] == GENERIC_POWER_RESTORE_STATE) + { Light_Hsl_Set((pModelState_Load+GENERIC_DATA_LIMIT+LIGHT_HSL_NVM_OFFSET), 6); + } + else + { + TRACE_M(TF_GENERIC, "Power On Off value invalid %d \r\n", pModelState_Load[0]); + } + break; } #endif + case No_NVM_FLAG: + { + TRACE_M(TF_GENERIC,"Power OnOff value stored = %d \r\n",pModelState_Load[4]); + break; + } default: { - TRACE_M(TF_LIGHT, "data is invalid %d \r\n", pModelState_Load[0]); + TRACE_M(TF_LIGHT, "No Saved Data Found \r\n"); break; } } + (GenericAppli_cb.GenericRestorePowerOnOff_cb)(pModelState_Load[4]); + } } @@ -608,6 +721,7 @@ MOBLEUINT8 BLE_GetElementNumber(void) return elementNumber; } +#ifdef ENABLE_SAVE_MODEL_STATE_NVM /** * @brief Function used to save the states of the node, when power down is detected. * @param void @@ -622,6 +736,7 @@ void ModelSave_Process(void) } } +#endif /** * @brief Function used to calculate the delay. * @param MOBLEUINT16 @@ -649,6 +764,69 @@ MOBLEUINT8 BLE_waitPeriod(MOBLEUINT32 waitPeriod) return 0x00; } +/** +* @brief Function used to calculate the delay. +* @param MOBLEUINT16 +* @retval MOBLEUINT8 +*/ +MOBLEUINT8 TimeDelay(MOBLEUINT16 waitPeriod) +{ + static MOBLEUINT8 Clockflag = 0; + static MOBLEUINT32 Check_time; + + + if(Clockflag == CLK_FLAG_DISABLE) + { + Check_time = Clock_Time(); + Clockflag = CLK_FLAG_ENABLE; + } + /* The function will called untill the testcount will not become zero */ + + if(((Clock_Time()- Check_time) <= waitPeriod)) + { + Clockflag = CLK_FLAG_DISABLE; + return 0x01; + + } + return 0x00; +} + +MOBLE_RESULT Chk_TidValidity(MOBLE_ADDRESS peer_Addrs,MOBLE_ADDRESS dst_Addrs,MOBLEUINT8 tidValue) +{ + static MOBLEUINT32 Check_time; + MOBLE_RESULT status = MOBLE_RESULT_SUCCESS; + + if(((Clock_Time()- Check_time) <= 6000)) + { + if((Peer_Addrs == peer_Addrs)&&(Dst_Addrs == dst_Addrs)&&(Tid_Value == tidValue)) + { + TRACE_M(TF_COMMON,"dst_peer = %.2X , peer_add = %.2X,tid = %.2X \r\n",dst_Addrs,peer_Addrs,tidValue); + TRACE_M(TF_COMMON,"Duplicate Message Parameter within six second \r\n"); + status = MOBLE_RESULT_INVALIDARG; + } + else + { + Check_time = Clock_Time(); + Peer_Addrs = peer_Addrs; + Dst_Addrs = dst_Addrs; + Tid_Value = tidValue; + TRACE_M(TF_COMMON,"dst_peer = %.2X , peer_add = %.2X,tid = %.2X \r\n",dst_Addrs,peer_Addrs,tidValue); + TRACE_M(TF_COMMON,"New Message Parameter within six second \r\n"); + } + } + else + { + Check_time = Clock_Time(); + Peer_Addrs = peer_Addrs; + Dst_Addrs = dst_Addrs; + Tid_Value = tidValue; + TRACE_M(TF_COMMON,"dst_peer = %.2X , peer_add = %.2X,tid = %.2X \r\n",dst_Addrs,peer_Addrs,tidValue); + TRACE_M(TF_COMMON,"New Message Parameter \r\n"); + } + + return status; +} + /** * @brief Function used to convert the time vale in standered Transition time. * @param MOBLEUINT16 @@ -682,10 +860,19 @@ MOBLEUINT8 Time_Conversion(MOBLEUINT32 lc_Time) /* No Comment */ } - totalTime = timeResolution << 6; - totalTime |= TRANSITION_STEP_VALUE; - - return totalTime; + totalTime = timeResolution << 6; + totalTime |= TRANSITION_STEP_VALUE; + + return totalTime; +} + + +WEAK_FUNCTION(MOBLE_RESULT ApplicationGetConfigServerDeviceKey(MOBLE_ADDRESS src, + const MOBLEUINT8**ppkeyTbUse)) +{ + MOBLE_RESULT result = MOBLE_RESULT_SUCCESS; + + return result; } /******************* (C) COPYRIGHT 2017 STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/config_client.c b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/config_client.c index ed074f915..e70cb868f 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/config_client.c +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/config_client.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file config_client.c * @author BLE Mesh Team -* @version V1.11.002 -* @date 27-09-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Config model Client middleware file ****************************************************************************** * @attention @@ -40,7 +40,6 @@ */ /* Includes ------------------------------------------------------------------*/ #include "hal_common.h" -#include "mesh_cfg.h" #include "config_client.h" #include "common.h" #include "models_if.h" @@ -76,11 +75,105 @@ const MODEL_OpcodeTableParam_t Config_Client_Opcodes_Table[] = { MOBLEUINT16 max_payload_size; Here in this array, Handler is not defined; */ #ifdef ENABLE_CONFIG_MODEL_CLIENT - {OPCODE_CONFIG_COMPOSITION_DATA_STATUS, MOBLE_FALSE, 10, 100, 0x8FFF , 0, 0}, - {OPCODE_CONFIG_APPKEY_STATUS, MOBLE_FALSE, 4, 4, 0x8FFF , 0, 0}, - {OPCODE_CONFIG_SUBSCRIPTION_STATUS, MOBLE_FALSE, 7, 9, 0x8FFF , 0, 0}, - {OPCODE_CONFIG_MODEL_PUBLI_STATUS, MOBLE_FALSE, 12, 14, 0x8FFF , 0, 0}, - {OPCODE_CONFIG_MODEL_APP_STATUS, MOBLE_FALSE, 7, 9, 0x8FFF , 0, 0}, + + /* 4.3.2.42 Config AppKey List, Opcode= 0x80 0x02 + The Config AppKey List is an unacknowledged message reporting all AppKeys + that are bound to the NetKey.*/ + {SIG_MODEL_ID_CONFIG_CLIENT, OPCODE_CONFIG_APPKEY_LIST, MOBLE_FALSE, 5, 9, 0x8FFF , 0, 0}, + + /* 4.3.2.40 Config AppKey Status, Opcode= 0x80 0x03 + The Config AppKey Status is an unacknowledged message used to report a status + for the requesting message, based on the NetKey Index identifying the NetKey + on the NetKey List and on the AppKey Index identifying the AppKey on the + AppKey List. */ + {SIG_MODEL_ID_CONFIG_CLIENT, OPCODE_CONFIG_APPKEY_STATUS, MOBLE_FALSE, 4, 4, 0x8FFF , 0, 0}, + + /* 4.3.2.3 Config Beacon Status, Opcode= 0x80 0x0B + The Config Beacon Status is an unacknowledged message used to report the + current Secure Network Beacon state of a node (see Section 4.2.10). + + Beacon : 1B : Secure Network Beacon state */ + {SIG_MODEL_ID_CONFIG_CLIENT, OPCODE_CONFIG_BEACON_STATUS, MOBLE_FALSE, 1, 1, 0x8FFF , 0, 0}, + + /* 4.3.2.5 Config Composition Data Status, Opcode= 0x02 + The Config Composition Data Status is an unacknowledged message used to + report a single page of the Composition Data (see Section 4.2.1). + This message uses a single octet opcode to maximize the size of a payload. + Parameters: + Page : 1B : Page number of the Composition Data + Data : variable : Composition Data for the identified page */ + {SIG_MODEL_ID_CONFIG_CLIENT, OPCODE_CONFIG_COMPOSITION_DATA_STATUS, MOBLE_FALSE, 10, 100, 0x8FFF , 0, 0}, + + /* 4.3.2.8 Config Default TTL Status, Opcode = 0x80 0x0E + The Config Default TTL Status is an unacknowledged message used to report + the current Default TTL state of a node (see Section 4.2.7). + Parameter: + TTL : 1B : Default TTL */ + {SIG_MODEL_ID_CONFIG_CLIENT, OPCODE_CONFIG_DEFAULT_TTL_STATUS,MOBLE_FALSE, 1, 1, 0x8FFF , 0, 0}, + + /* 4.3.2.57 Config Friend Status, Opcode = 0x80 0x11 + The Config Friend Status is an unacknowledged message used to report the + current Friend state of a node (see Section 4.2.13). + Parameter: + Friend : 1B : Friend state */ + {SIG_MODEL_ID_CONFIG_CLIENT, OPCODE_CONFIG_FRIEND_STATUS,MOBLE_FALSE, 1, 1, 0x8FFF , 0, 0}, + + /* 4.3.2.11 Config GATT Proxy Status, Opcode = 0x80 0x14 + The Config GATT Proxy Status is an unacknowledged message used to report the + current GATT Proxy state of a node (see Section 4.2.11). + Parameter: + GATTProxy : 1B : GATT Proxy state */ + {SIG_MODEL_ID_CONFIG_CLIENT, OPCODE_CONFIG_GATT_PROXY_STATUS,MOBLE_FALSE, 1, 1, 0x8FFF , 0, 0}, + + /* 4.3.2.63 Config Heartbeat Publication Status, Opcode = 0x06 + The Config Heartbeat Publication Status is an unacknowledged message used + to report the Heartbeat Publication state of a node (see Section 4.2.17). + Parameter: + Status : 1B : Status Code for the requesting message + Destination : 2B : Destination address for Heartbeat messages + CountLog : 1B : Number of Heartbeat messages remaining to be sent + PeriodLog : 1B : Period for sending Heartbeat messages + TTL : 1B : TTL to be used when sending Heartbeat messages + Features : 2B : Bit field indicating features that trigger Heartbeat messages when changed + NetKeyIndex : 2B : NetKey Index */ + {SIG_MODEL_ID_CONFIG_CLIENT, OPCODE_CONFIG_HEARTBEAT_PUBLICATION_STATUS, MOBLE_FALSE, 10, 10, 0x8FFF , 0, 0}, + + /* 4.3.2.66 Config Heartbeat Subscription Status, Opcode = 0x80 0x3C + The Config Heartbeat Subscription Status is an unacknowledged message used + to report the Heartbeat Subscription state of a node (see Section 4.2.18) + Parameters: + Status : 1B : Status Code for the requesting message + Source : 2B : Source address for Heartbeat messages + Destination : 2B : Destination address for Heartbeat messages + PeriodLog : 1B : Remaining Period for processing Heartbeat messages + CountLog : 1B : Number of Heartbeat messages received + MinHops : 1B : Minimum hops when receiving Heartbeat messages + MaxHops : 1B : Maximum hops when receiving Heartbeat messages */ + {SIG_MODEL_ID_CONFIG_CLIENT, OPCODE_CONFIG_HEARTBEAT_SUBSCRIPTION_STATUS,MOBLE_FALSE, 9, 9, 0x8FFF , 0, 0}, + + /* 4.3.2.60 Config Key Refresh Phase Status, Opcode = 0x80 0x17 + The Config Key Refresh Phase Status is an unacknowledged message used to + report the current Key Refresh Phase state of the identified network key + (see Section 4.2.14). + Parameters: + Status : 1B : Status Code for the requesting message + NetKeyIndex : 2B : NetKey Index + Phase : 1B : Key Refresh Phase State */ + {SIG_MODEL_ID_CONFIG_CLIENT, OPCODE_CONFIG_KEY_REFRESH_PHASE_STATUS,MOBLE_FALSE, 4, 4, 0x8FFF , 0, 0}, + + /* 4.3.2.68 Config Low Power Node PollTimeout Status, Opcode = 0x80 0x2E + The Config Low Power Node PollTimeout Status is an unacknowledged message + used to report the current value of the PollTimeout timer of the Low Power + node within a Friend node. + Parameters: + LPNAddress: 2B : The unicast address of the Low Power node + PollTimeout: 3B : The current value of the PollTimeout timer of the Low Power node */ + {SIG_MODEL_ID_CONFIG_CLIENT, OPCODE_CONFIG_LOW_POWER_NODE_POLLTIMEOUT_STATUS, MOBLE_FALSE, 5, 5, 0x8FFF , 0, 0}, + + {SIG_MODEL_ID_CONFIG_CLIENT, OPCODE_CONFIG_MODEL_SUBSCRIPTION_STATUS,MOBLE_FALSE, 7, 9, 0x8FFF , 0, 0}, + {SIG_MODEL_ID_CONFIG_CLIENT, OPCODE_CONFIG_MODEL_PUBLICATION_STATUS, MOBLE_FALSE, 12, 14, 0x8FFF , 0, 0}, + {SIG_MODEL_ID_CONFIG_CLIENT, OPCODE_CONFIG_MODEL_APP_STATUS, MOBLE_FALSE, 7, 9, 0x8FFF , 0, 0}, + {SIG_MODEL_ID_CONFIG_CLIENT, OPCODE_CONFIG_NODE_RESET_STATUS, MOBLE_FALSE, 0, 0, 0x8FFF , 0, 0}, #endif {0} }; @@ -111,6 +204,8 @@ MOBLE_RESULT ConfigClient_ModelAppUnbind (void); MOBLEUINT16 CopyU8LittleEndienArrayToU16word (MOBLEUINT8* pArray); MOBLEUINT32 CopyU8LittleEndienArrayToU32word (MOBLEUINT8* pArray); WEAK_FUNCTION (MOBLEUINT8* GetNewProvNodeDevKey(void)); +MOBLE_RESULT ConfigClient_NodeResetStatus(MOBLEUINT8 const *pStatus, + MOBLEUINT32 length); /* Private functions ---------------------------------------------------------*/ @@ -282,6 +377,21 @@ MOBLEUINT16 GetNodeElementAddress(void) return NodeInfo.nodePrimaryAddress; } +/** +* @brief GetServerElementAddress: This function gets the element address + from elementIndex +* @param None +* @retval MOBLE_RESULT +*/ +MOBLEUINT16 GetServerElementAddress(MOBLEUINT8 elementIdx) +{ + MOBLEUINT16 elementAddr; + + elementAddr = NodeInfo.nodePrimaryAddress; + elementAddr += elementIdx; + return elementAddr; +} + /** * @brief GetNodeElementAddress: This function gets the element address from last known address saved in the flash @@ -685,9 +795,11 @@ maximize the size of a payload. MOBLEUINT8* pConfigData; MOBLEUINT32 dataLength; MOBLE_ADDRESS dst_peer; + MOBLE_ADDRESS self_addr; MOBLE_RESULT result = MOBLE_RESULT_SUCCESS; configClientModelPublication_t configClientModelPublication; + TRACE_M(TF_CONFIG_CLIENT,"Config Client Publication Add Message \r\n"); dataLength = sizeof(configClientModelPublication_t); @@ -720,26 +832,28 @@ maximize the size of a payload. } - msg_opcode = OPCODE_CONFIG_MODEL_PUBLI_SET; + msg_opcode = OPCODE_CONFIG_CONFIG_MODEL_PUBLICATION_SET; pConfigData = (MOBLEUINT8*) &(configClientModelPublication); dst_peer = NodeInfo.nodePrimaryAddress; TRACE_M(TF_CONFIG_CLIENT,"Config Client Publication Add \r\n"); TRACE_M(TF_CONFIG_CLIENT,"elementAddr = [%04x]\r\n", elementAddress); TRACE_M(TF_CONFIG_CLIENT,"publishAddress = [%04x]\r\n", publishAddress); - TRACE_M(TF_CONFIG_CLIENT,"modelIdentifier = [%08x]\r\n", modelIdentifier); + TRACE_M(TF_CONFIG_CLIENT,"modelIdentifier = [%08lx]\r\n", modelIdentifier); - TRACE_I(TF_CONFIG_CLIENT,"Publication Set buffer "); + TRACE_I(TF_CONFIG_CLIENT,"Publication Set buffer \r\n"); for (MOBLEUINT8 count=0 ; count= CONFIGCLIENT_RE_TRIALS) + else { retry_state = CLIENT_TX_TIMEOUT; *peRespRecdState = NodeIdle_State; /* Run next re-trial cycle again */ @@ -1387,6 +1583,41 @@ MOBLEUINT8 ConfigClient_ChkRetrialState (eServerRespRecdState_t* peRespRecdState return retry_state; } +/** +* @brief ConfigClient_ChkRetries: This function is used by application + to check if there is a timeout of the Config Client Message sending +* @param None +* @retval None +*/ +MOBLEUINT8 ConfigClient_ChkRetries (void) +{ + MOBLEUINT8 retry_state = CLIENT_TX_INPROGRESS; + MOBLEUINT32 nowClockTime; + + nowClockTime = Clock_Time(); + if(( (nowClockTime - NodeInfo.Initial_time) >= CONFIGCLIENT_RESPONSE_TIMEOUT)) + { + /* Timeout occured, Do retry or enter the error state */ + NodeInfo.numberOfAttemptsTx++; + + if (NodeInfo.numberOfAttemptsTx >= CONFIGCLIENT_MAX_TRIALS) + { + NodeInfo.numberOfAttemptsTx = 0; + retry_state = CLIENT_TX_RETRY_ENDS; /* re-trial cycle ends, no response */ + ConfigClient_ErrorState(); + } + else + { + retry_state = CLIENT_TX_TIMEOUT; + TRACE_M(TF_CONFIG_CLIENT,"Retry started \n\r"); + } + + ConfigClient_SaveMsgSendingTime(); /* Save the time again for next loop */ + } + + return retry_state; +} + /** * @brief ConfigClient_ErrorState: This function is used by application to save the Initial time of message issue @@ -1494,7 +1725,7 @@ MOBLE_RESULT ConfigClientModel_ProcessMessageCb(MOBLE_ADDRESS peer_addr, { MOBLE_RESULT result = MOBLE_RESULT_SUCCESS; - tClockTime delay_t = Clock_Time(); +// tClockTime delay_t = Clock_Time(); TRACE_M(TF_CONFIG_CLIENT,"dst_peer = %.2X , peer_add = %.2X, opcode= %.2X ,response= %.2X \r\n ", dst_peer, peer_addr, opcode , response); @@ -1522,14 +1753,14 @@ MOBLE_RESULT ConfigClientModel_ProcessMessageCb(MOBLE_ADDRESS peer_addr, break; } - case OPCODE_CONFIG_SUBSCRIPTION_STATUS: + case OPCODE_CONFIG_MODEL_SUBSCRIPTION_STATUS: { ConfigClient_SubscriptionStatus(pRxData, dataLength); break; } - case OPCODE_CONFIG_MODEL_PUBLI_STATUS: + case OPCODE_CONFIG_MODEL_PUBLICATION_STATUS: { ConfigClient_PublicationStatus(pRxData, dataLength); break; @@ -1541,6 +1772,12 @@ MOBLE_RESULT ConfigClientModel_ProcessMessageCb(MOBLE_ADDRESS peer_addr, break; } + case OPCODE_CONFIG_NODE_RESET_STATUS: + { + ConfigClient_NodeResetStatus(pRxData, dataLength); + break; + } + default: { break; diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/generic.c b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/generic.c index e72ee0558..2075b7a25 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/generic.c +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/generic.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file generic.c * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Generic model middleware file ****************************************************************************** * @attention @@ -74,10 +74,15 @@ Generic_DefaultTransitionParam_t Generic_DefaultTransitionParam = {0x06}; static Generic_ModelFlag_t Generic_ModelFlag; extern MOBLEUINT16 CommandStatus; -MOBLEUINT8 GeneicUpdateFlag = 0; +MOBLEUINT8 GenericUpdateFlag = 0; MOBLEUINT8 Generic_Trnsn_Cmplt = 0; MOBLEUINT16 Generic_Rx_Opcode; MOBLEUINT8 OptionalValid = 0; +MOBLEUINT8 PowerOnOff_Flag = 0; +MOBLEUINT8 TidValue = 0; +MOBLEUINT16 Model_ID = 0; +MOBLE_ADDRESS Dst_Peer; +extern MOBLEUINT8 TidSend; const MODEL_OpcodeTableParam_t Generic_Opcodes_Table[] = { /* Generic OnOff Server */ @@ -85,39 +90,39 @@ const MODEL_OpcodeTableParam_t Generic_Opcodes_Table[] = { MOBLEUINT16 max_payload_size; Here in this array, Handler is not defined; */ #ifdef ENABLE_GENERIC_MODEL_SERVER_ONOFF - {GENERIC_ON_OFF_GET, MOBLE_TRUE, 0, 0, GENERIC_ON_OFF_STATUS , 1, 3}, - {GENERIC_ON_OFF_SET_ACK, MOBLE_TRUE, 2, 4, GENERIC_ON_OFF_STATUS , 1, 3}, - {GENERIC_ON_OFF_SET_UNACK, MOBLE_FALSE, 2, 4, 0 , 1, 3}, - {GENERIC_ON_OFF_STATUS, MOBLE_FALSE, 1, 3, 0 , 1, 3}, + {GENERIC_MODEL_SERVER_ONOFF_MODEL_ID ,GENERIC_ON_OFF_GET, MOBLE_TRUE, 0, 0, GENERIC_ON_OFF_STATUS , 1, 3}, + {GENERIC_MODEL_SERVER_ONOFF_MODEL_ID ,GENERIC_ON_OFF_SET_ACK, MOBLE_TRUE, 2, 4, GENERIC_ON_OFF_STATUS , 1, 3}, + {GENERIC_MODEL_SERVER_ONOFF_MODEL_ID ,GENERIC_ON_OFF_SET_UNACK, MOBLE_FALSE, 2, 4, GENERIC_ON_OFF_STATUS , 1, 3}, // null replaced from GENERIC_ON_OFF_STATUS + {GENERIC_MODEL_SERVER_ONOFF_MODEL_ID ,GENERIC_ON_OFF_STATUS, MOBLE_FALSE, 1, 3, 0 , 1, 3}, #endif #ifdef ENABLE_GENERIC_MODEL_SERVER_LEVEL /* Generic Level Server */ - {GENERIC_LEVEL_GET, MOBLE_TRUE, 0, 0, GENERIC_LEVEL_STATUS , 2 , 5}, - {GENERIC_LEVEL_SET_ACK, MOBLE_TRUE, 3, 5, GENERIC_LEVEL_STATUS , 2 , 5}, - {GENERIC_LEVEL_SET_UNACK, MOBLE_FALSE, 3, 5, 0 , 2 , 5}, - {GENERIC_LEVEL_DELTA_SET, MOBLE_TRUE, 5, 7, GENERIC_LEVEL_STATUS , 2 , 5}, - {GENERIC_LEVEL_DELTA_SET_UNACK, MOBLE_FALSE, 5, 7, 0, 0, 0}, - {GENERIC_LEVEL_DELTA_MOVE_SET, MOBLE_TRUE, 3, 5, GENERIC_LEVEL_STATUS , 2 , 5}, - {GENERIC_LEVEL_DELTA_MOVE_SET_UNACK, MOBLE_FALSE, 3, 5, 0, 0 , 0}, - {GENERIC_LEVEL_STATUS, MOBLE_FALSE, 2, 5, 0 , 2 , 5}, + {GENERIC_MODEL_SERVER_LEVEL_MODEL_ID ,GENERIC_LEVEL_GET, MOBLE_TRUE, 0, 0, GENERIC_LEVEL_STATUS , 2 , 5}, + {GENERIC_MODEL_SERVER_LEVEL_MODEL_ID ,GENERIC_LEVEL_SET_ACK, MOBLE_TRUE, 3, 5, GENERIC_LEVEL_STATUS , 2 , 5}, + {GENERIC_MODEL_SERVER_LEVEL_MODEL_ID ,GENERIC_LEVEL_SET_UNACK, MOBLE_FALSE, 3, 5, GENERIC_LEVEL_STATUS , 2 , 5}, //null is replaced with GENERIC_LEVEL_STATUS + {GENERIC_MODEL_SERVER_LEVEL_MODEL_ID ,GENERIC_LEVEL_DELTA_SET, MOBLE_TRUE, 5, 7, GENERIC_LEVEL_STATUS , 2 , 5}, + {GENERIC_MODEL_SERVER_LEVEL_MODEL_ID ,GENERIC_LEVEL_DELTA_SET_UNACK, MOBLE_FALSE, 5, 7, 0, 0 , 0}, + {GENERIC_MODEL_SERVER_LEVEL_MODEL_ID ,GENERIC_LEVEL_DELTA_MOVE_SET, MOBLE_TRUE, 3, 5, GENERIC_LEVEL_STATUS , 2 , 5}, + {GENERIC_MODEL_SERVER_LEVEL_MODEL_ID ,GENERIC_LEVEL_DELTA_MOVE_SET_UNACK, MOBLE_FALSE, 3, 5, 0, 0 , 0}, + {GENERIC_MODEL_SERVER_LEVEL_MODEL_ID ,GENERIC_LEVEL_STATUS, MOBLE_FALSE, 2, 5, 0 , 2 , 5}, #endif #ifdef ENABLE_GENERIC_MODEL_SERVER_POWER_ONOFF - {GENERIC_POWER_ON_OFF_SET, MOBLE_TRUE, 1, 1, GENERIC_POWER_ON_OFF_STATUS, 1,1}, - {GENERIC_POWER_ON_OFF_SET_UNACK, MOBLE_FALSE, 1, 1, 0, 1,1}, - {GENERIC_POWER_ON_OFF_GET , MOBLE_TRUE, 1, 1, GENERIC_POWER_ON_OFF_STATUS, 1,1}, - {GENERIC_POWER_ON_OFF_STATUS , MOBLE_FALSE, 1, 1, 0, 1,1}, + {GENERIC_MODEL_SERVER_POWER_ONOFF_SETUP_MODEL_ID ,GENERIC_POWER_ON_OFF_SET, MOBLE_TRUE, 1, 1, GENERIC_POWER_ON_OFF_STATUS, 1,1}, + {GENERIC_MODEL_SERVER_POWER_ONOFF_SETUP_MODEL_ID ,GENERIC_POWER_ON_OFF_SET_UNACK, MOBLE_FALSE, 1, 1, 0, 1,1}, + {GENERIC_MODEL_SERVER_POWER_ONOFF_MODEL_ID ,GENERIC_POWER_ON_OFF_GET , MOBLE_TRUE, 0, 0, GENERIC_POWER_ON_OFF_STATUS, 1,1}, + {GENERIC_MODEL_SERVER_POWER_ONOFF_MODEL_ID ,GENERIC_POWER_ON_OFF_STATUS , MOBLE_FALSE, 1, 1, 0, 1,1}, #endif #ifdef ENABLE_GENERIC_MODEL_SERVER_DEFAULT_TRANSITION_TIME /* Generic Default Transition Time Server Model */ - {GENERIC_DEFAULT_TRANSITION_TIME_GET, MOBLE_TRUE, 0, 0, GENERIC_DEFAULT_TRANSITION_TIME_STATUS , 1, 1}, - {GENERIC_DEFAULT_TRANSITION_TIME_SET, MOBLE_TRUE, 1, 1, GENERIC_DEFAULT_TRANSITION_TIME_STATUS , 1, 1}, - {GENERIC_DEFAULT_TRANSITION_TIME_SET_UNACK, MOBLE_FALSE, 1, 1, 0 ,0 ,0}, - {GENERIC_DEFAULT_TRANSITION_TIME_STATUS, MOBLE_FALSE, 1, 1, 0 ,1, 1}, + {GENERIC_MODEL_SERVER_DEFAULT_TRANSITION_TIME_MODEL_ID ,GENERIC_DEFAULT_TRANSITION_TIME_GET, MOBLE_TRUE, 0, 0, GENERIC_DEFAULT_TRANSITION_TIME_STATUS , 1, 1}, + {GENERIC_MODEL_SERVER_DEFAULT_TRANSITION_TIME_MODEL_ID ,GENERIC_DEFAULT_TRANSITION_TIME_SET, MOBLE_TRUE, 1, 1, GENERIC_DEFAULT_TRANSITION_TIME_STATUS , 1, 1}, + {GENERIC_MODEL_SERVER_DEFAULT_TRANSITION_TIME_MODEL_ID ,GENERIC_DEFAULT_TRANSITION_TIME_SET_UNACK, MOBLE_FALSE, 1, 1, GENERIC_DEFAULT_TRANSITION_TIME_STATUS ,0 ,0}, // //null is replaced with GENERIC_DEFAULT_TRANSITION_TIME_STATUS + {GENERIC_MODEL_SERVER_DEFAULT_TRANSITION_TIME_MODEL_ID ,GENERIC_DEFAULT_TRANSITION_TIME_STATUS, MOBLE_FALSE, 1, 1, 0 ,1, 1}, #endif #ifdef ENABLE_GENERIC_MODEL_SERVER_BATTERY /* Generic Battery Server Model */ - {GENERIC_BATTERY_GET, MOBLE_TRUE, 0, 0, GENERIC_BATTERY_STATUS , 8 , 8}, + {GENERIC_MODEL_SERVER_BATTERY_MODEL_ID GENERIC_BATTERY_GET, MOBLE_TRUE, 0, 0, GENERIC_BATTERY_STATUS , 8 , 8}, #endif {0} }; @@ -135,6 +140,17 @@ WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_PowerOnOff_Set(Generic_PowerOnOffParam MOBLEUINT8 OptionalValid)); WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_DefaultTransitionTime_Set(Generic_DefaultTransitionParam_t* pDefaultTimeParam, MOBLEUINT8 OptionalValid)); +WEAK_FUNCTION (void Appli_Generic_Restore_PowerOn_Value(MOBLEUINT8 restoreValue)); +WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_GetOnOffStatus(MOBLEUINT8* pOnOff_Status)); +WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_GetOnOffValue(MOBLEUINT8* pOnOff_Value) ); +WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_GetLevelStatus(MOBLEUINT8* pLevel_Status)); +WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_GetPowerOnOffStatus(MOBLEUINT8* pLevel_Status)); +WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_GetDefaultTransitionStatus(MOBLEUINT8* pTransition_Status)); +WEAK_FUNCTION(MOBLE_RESULT Appli_GenericClient_Level_Set_Unack(void)); +WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_OnOff_Status(MOBLEUINT8 const *pOnOff_status, MOBLEUINT32 plength)); +WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_Level_Status(MOBLEUINT8 const *plevel_status, MOBLEUINT32 plength)); +WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_PowerOnOff_Status(MOBLEUINT8 const *powerOnOff_status , MOBLEUINT32 plength)); +WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_DefaultTransitionTime_Status(MOBLEUINT8 const *pTransition_status , MOBLEUINT32 plength)); /* Private functions ---------------------------------------------------------*/ @@ -154,10 +170,10 @@ MOBLE_RESULT Generic_OnOff_Set(MOBLEUINT8 const *pOnOff_param, MOBLEUINT32 lengt Transition Time: 1B Format as defined in Section 3.1.3. (Optional) Delay: 1B Message execution delay in 5 millisecond steps (C.1) */ - Generic_OnOffParam_t Generic_OnOffParam; TRACE_M(TF_GENERIC,"Generic_OnOff_Set callback received \r\n"); - + + Generic_OnOffParam_t Generic_OnOffParam; Generic_OnOffParam.TargetOnOffState = pOnOff_param[0]; Generic_OnOffParam.Generic_TID = pOnOff_param[1]; CommandStatus = pOnOff_param[0]; @@ -217,11 +233,10 @@ MOBLE_RESULT Generic_OnOff_Set(MOBLEUINT8 const *pOnOff_param, MOBLEUINT32 lengt /* When no optional parameter received, target value will be set as present value in application. */ - Generic_OnOffStatus.Present_OnOff_State = Generic_OnOffParam.TargetOnOffState; OptionalValid = NO_TRANSITION; #endif - } + Generic_OnOffStatus.Present_OnOff_State = Generic_OnOffParam.TargetOnOffState; /* Application Callback */ (GenericAppli_cb.OnOff_Set_cb)(&Generic_OnOffStatus, OptionalValid); #ifdef ENABLE_MODEL_BINDING @@ -250,6 +265,7 @@ MOBLE_RESULT Generic_OnOff_Status(MOBLEUINT8* pOnOff_status, MOBLEUINT32 *plengt MOBLEUINT8 Generic_GetBuff[1] ; TRACE_M(TF_GENERIC,"Generic_OnOff_Status callback received \r\n"); + TRACE_M(TF_SERIAL_CTRL,"#8201! \n\r"); /* Function call back to get the values from application*/ (Appli_GenericState_cb.GetOnOffStatus_cb)(Generic_GetBuff); @@ -277,7 +293,7 @@ MOBLE_RESULT Generic_OnOff_Status(MOBLEUINT8* pOnOff_status, MOBLEUINT32 *plengt /** * @brief Generic_Level_Set: This function is called for both Acknowledged and - unacknowledged message +* unacknowledged message * @param plevel_param: Pointer to the parameters received for message * @param length: Length of the parameters received for message * @retval MOBLE_RESULT @@ -358,7 +374,7 @@ MOBLE_RESULT Generic_Level_Set(const MOBLEUINT8* plevel_param, MOBLEUINT32 lengt /** * @brief Generic_LevelDelta_Set: This function is called for both Acknowledged - and unacknowledged message +* and unacknowledged message * @param plevel_param: Pointer to the parameters received for message * @param length: Length of the parameters received for message * @retval MOBLE_RESULT @@ -429,6 +445,9 @@ MOBLE_RESULT Generic_LevelDelta_Set(const MOBLEUINT8* plevel_param, MOBLEUINT32 } Generic_LevelStatus.Last_Level_TID = Generic_DeltaLevelParam.Generic_TID; + /* EME: need to update the value for next operation */ + Generic_LevelStatus.Last_Present_Level16 = Generic_LevelStatus.Present_Level16; + /* Application Callback */ (GenericAppli_cb.LevelDelta_Set_cb)(&Generic_LevelStatus, 0); @@ -438,7 +457,7 @@ MOBLE_RESULT Generic_LevelDelta_Set(const MOBLEUINT8* plevel_param, MOBLEUINT32 /** * @brief Generic_LevelMove_Set: This function is called for both - Acknowledged and unacknowledged message +* Acknowledged and unacknowledged message * @param plevel_param: Pointer to the parameters received for message * @param length: Length of the parameters received for message * @retval MOBLE_RESULT @@ -519,6 +538,7 @@ MOBLE_RESULT Generic_Level_Status(MOBLEUINT8* plevel_status, MOBLEUINT32 *plengt MOBLEUINT8 Generic_GetBuff[2] ; TRACE_M(TF_GENERIC,"Generic_Level_Status callback received \r\n"); + TRACE_M(TF_SERIAL_CTRL,"#8205! \n\r"); /* Function call back to get the values from application*/ (Appli_GenericState_cb.GetLevelStatus_cb)(Generic_GetBuff); @@ -551,7 +571,7 @@ MOBLE_RESULT Generic_Level_Status(MOBLEUINT8* plevel_status, MOBLEUINT32 *plengt /** * @brief Generic_PowerOnOff_Set: This function is called for both -Acknowledged and unacknowledged message +* Acknowledged and unacknowledged message * @param powerOnOff_param: Pointer to the parameters received for message * @param length: Length of the parameters received for message * @retval MOBLE_RESULT @@ -588,6 +608,8 @@ MOBLE_RESULT Generic_PowerOnOff_Status(MOBLEUINT8 *powerOnOff_status , MOBLEUINT */ MOBLEUINT8 Generic_GetBuff[2] ; TRACE_M(TF_GENERIC,"Generic_PowerOnOff_Status callback received \r\n"); + TRACE_M(TF_SERIAL_CTRL,"#8211! \n\r"); + /* Function call back to get the values from application*/ (Appli_GenericState_cb.GetPowerOnOffStatus_cb)(Generic_GetBuff); @@ -599,7 +621,7 @@ MOBLE_RESULT Generic_PowerOnOff_Status(MOBLEUINT8 *powerOnOff_status , MOBLEUINT /** * @brief Generic_DefaultTransitionTime_Set: This function is called for both -Acknowledged and unacknowledged message +* Acknowledged and unacknowledged message * @param defaultTransition_param: Pointer to the parameters received for message * @param length: Length of the parameters received for message * @retval MOBLE_RESULT @@ -662,7 +684,7 @@ MOBLE_RESULT GenericModelServer_GetOpcodeTableCb(const MODEL_OpcodeTableParam_t /** * @brief GenericModelServer_GetStatusRequestCb : This function is call-back - from the library to send response to the message from peer +* from the library to send response to the message from peer * @param peer_addr: Address of the peer * @param dst_peer: destination send by peer for this node. It can be a * unicast or group address @@ -728,7 +750,7 @@ MOBLE_RESULT GenericModelServer_GetStatusRequestCb(MOBLE_ADDRESS peer_addr, /** * @brief GenericModelServer_ProcessMessageCb: This is a callback function from - the library whenever a Generic Model message is received +* the library whenever a Generic Model message is received * @param peer_addr: Address of the peer * @param dst_peer: destination send by peer for this node. It can be a * unicast or group address @@ -742,17 +764,21 @@ MOBLE_RESULT GenericModelServer_GetStatusRequestCb(MOBLE_ADDRESS peer_addr, * @retval MOBLE_RESULT */ MOBLE_RESULT GenericModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, - MOBLE_ADDRESS dst_peer, - MOBLEUINT16 opcode, + MOBLE_ADDRESS dst_peer, + MOBLEUINT16 opcode, MOBLEUINT8 const *pRxData, MOBLEUINT32 dataLength, - MOBLEBOOL response - ) + MOBLEBOOL response + ) { MOBLE_RESULT result = MOBLE_RESULT_SUCCESS; -/* tClockTime delay_t = Clock_Time(); */ - +// tClockTime delay_t = Clock_Time(); + MOBLE_ADDRESS publishAddress; + MOBLEUINT8 elementNumber; + MOBLEUINT8 modelStateChangeFlag = MOBLE_FALSE; + Generic_Rx_Opcode = opcode; + Dst_Peer = dst_peer; TRACE_M(TF_GENERIC,"dst_peer = %.2X , peer_add = %.2X, opcode= %.2X ,response= %.2X \r\n ", dst_peer, peer_addr, opcode , response); Generic_Rx_Opcode = opcode; @@ -763,7 +789,7 @@ MOBLE_RESULT GenericModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, case GENERIC_ON_OFF_SET_ACK: case GENERIC_ON_OFF_SET_UNACK: { - result = Chk_ParamValidity(pRxData[0], 1); + result = Chk_ParamValidity(pRxData[0], 1); /* 3.1.1 Generic OnOff 0x020xFF Prohibited */ /* 3.2.1.2 Generic OnOff Set If the Transition Time field is present, the Delay field shall also be present; otherwise these fields shall @@ -774,7 +800,7 @@ MOBLE_RESULT GenericModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, If present, Only values of 0x00 through 0x3E shall be used to specify the value of the Transition Number of Steps field. */ - result |= Chk_OptionalParamValidity (dataLength, 2, (pRxData[2]&0x3F), 0x3E ); + result |= Chk_OptionalParamValidity (dataLength, 2, (pRxData[2]&0x3F), 0x3E ); if(result == MOBLE_RESULT_SUCCESS) { @@ -782,12 +808,16 @@ MOBLE_RESULT GenericModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, when device is working as proxy and is a part of node delay will be included in the toggelinf of led. */ - Generic_OnOff_Set(pRxData,dataLength); + if(!MOBLE_FAILED(result = Chk_TidValidity(peer_addr,dst_peer,pRxData[1]))) + { + Generic_OnOff_Set(pRxData,dataLength); + Model_ID = (MOBLEUINT16)GENERIC_MODEL_SERVER_ONOFF_MODEL_ID; + modelStateChangeFlag = MOBLE_TRUE; + } } break; } - case GENERIC_ON_OFF_STATUS: { Generic_Client_OnOff_Status(pRxData,dataLength); @@ -804,8 +834,13 @@ MOBLE_RESULT GenericModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, result = Chk_ParamMinMaxValidity(LEVEL_MIN_VALID_RANGE ,pRxData , LEVEL_MAX_VALID_RANGE ); if(result == MOBLE_RESULT_SUCCESS) { - Generic_Level_Set(pRxData,dataLength); - } + if(!MOBLE_FAILED(result = Chk_TidValidity(peer_addr,dst_peer,pRxData[2]))) + { + Generic_Level_Set(pRxData,dataLength); + Model_ID = (MOBLEUINT16)GENERIC_MODEL_SERVER_LEVEL_MODEL_ID; + modelStateChangeFlag = MOBLE_TRUE; + } + } break; } @@ -819,7 +854,10 @@ MOBLE_RESULT GenericModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, Transition Time 1 Format as defined in Section 3.1.3. (Optional) Delay 1 Message execution delay in 5 milliseconds steps (C.1) */ + if(!MOBLE_FAILED(result = Chk_TidValidity(peer_addr,dst_peer,pRxData[4]))) + { Generic_LevelDelta_Set(pRxData,dataLength); + } break; } @@ -830,8 +868,11 @@ MOBLE_RESULT GenericModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, result = Chk_ParamMinMaxValidity(LEVEL_MIN_VALID_RANGE ,pRxData , LEVEL_MAX_VALID_RANGE ); if(result == MOBLE_RESULT_SUCCESS) { + if(!MOBLE_FAILED(result = Chk_TidValidity(peer_addr,dst_peer,pRxData[2]))) + { Generic_LevelMove_Set(pRxData, dataLength); } + } break; } case GENERIC_LEVEL_STATUS: @@ -896,7 +937,15 @@ MOBLE_RESULT GenericModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, for publication is full filled as per specification then the status will be published. */ + elementNumber = BLE_GetElementNumber(); + publishAddress = BLEMesh_GetPublishAddress(elementNumber,Model_ID); + + if((result == MOBLE_RESULT_SUCCESS) && (publishAddress != 0x0000) && (modelStateChangeFlag == MOBLE_TRUE)) + { + Model_SendResponse(publishAddress,dst_peer,opcode,pRxData,dataLength); + modelStateChangeFlag = MOBLE_FALSE; + } return MOBLE_RESULT_SUCCESS; } @@ -964,14 +1013,14 @@ MOBLE_RESULT Generic_TransitionBehaviourSingle_Param(MOBLEUINT8 *GetValue) Check_time = 0; Clockflag = 0; - GeneicUpdateFlag = VALUE_UPDATE_SET; + GenericUpdateFlag = VALUE_UPDATE_SET; /* when transition is completed, disable the transition by disabling transition flag */ if(Generic_TimeParam.StepValue <= 0) { Generic_ModelFlag.GenericTransitionFlag = GENERIC_TRANSITION_STOP; - Generic_Trnsn_Cmplt = 1; + Generic_Trnsn_Cmplt = MOBLE_TRUE; } TRACE_M(TF_GENERIC,"Inside virtual application at %ld, Current state 0x%.2x, Target state 0x%.2x, Remaining Time 0x%.2x \n\r", Clock_Time(), Generic_TemporaryStatus.PresentValue16,Generic_TemporaryStatus.TargetValue16,Generic_TemporaryStatus.RemainingTime); @@ -1035,14 +1084,14 @@ MOBLE_RESULT Generic_TransitionBehaviourMulti_Param(MOBLEUINT8 *GetValue) Check_time = 0; Clockflag = 0; - GeneicUpdateFlag = VALUE_UPDATE_SET; + GenericUpdateFlag = VALUE_UPDATE_SET; /* when transition is completed, disable the transition by disabling transition flag */ if(Generic_TimeParam.StepValue <= 0) { Generic_ModelFlag.GenericTransitionFlag = GENERIC_TRANSITION_STOP; - Generic_Trnsn_Cmplt = 1; + Generic_Trnsn_Cmplt = MOBLE_TRUE; } TRACE_M(TF_GENERIC,"Inside virtual level application at %ld, Current state 0x%.2x , target state 0x%.2x , Remaining Time 0x%.2x \n\r", Clock_Time(),Generic_TemporaryStatus.PresentValue16,Generic_TemporaryStatus.TargetValue16, @@ -1086,12 +1135,16 @@ void Generic_GetStepValue(MOBLEUINT8 stepParam) /** * @brief Generic_Process: Function to execute the transition state machine for - particular Generic Model +* particular Generic Model * @param void * @retval void */ void Generic_Process(void) { + MOBLE_ADDRESS publishAddress; + MOBLEUINT8 elementNumber; + MOBLEUINT8 const pRxData[8] = {0}; + MOBLEUINT32 dataLength = 0; #if defined ENABLE_GENERIC_MODEL_SERVER_ONOFF || defined ENABLE_GENERIC_MODEL_SERVER_LEVEL MOBLEUINT8 Generic_GetBuff[8]; #endif @@ -1101,11 +1154,11 @@ void Generic_Process(void) { (Appli_GenericState_cb.GetOnOffValue_cb)(Generic_GetBuff); Generic_TransitionBehaviourSingle_Param(Generic_GetBuff); - if(GeneicUpdateFlag == VALUE_UPDATE_SET) + if(GenericUpdateFlag == VALUE_UPDATE_SET) { GenericOnOffStateUpdate_Process(); (GenericAppli_cb.OnOff_Set_cb)(&Generic_OnOffStatus, OptionalValid); - GeneicUpdateFlag = VALUE_UPDATE_RESET; + GenericUpdateFlag = VALUE_UPDATE_RESET; } } #endif @@ -1115,28 +1168,39 @@ void Generic_Process(void) { (Appli_GenericState_cb.GetLevelStatus_cb)(Generic_GetBuff); Generic_TransitionBehaviourMulti_Param(Generic_GetBuff); - if(GeneicUpdateFlag == VALUE_UPDATE_SET) + if(GenericUpdateFlag == VALUE_UPDATE_SET) { GenericLevelStateUpdate_Process(); (GenericAppli_cb.Level_Set_cb)(&Generic_LevelStatus, 0); - GeneicUpdateFlag = VALUE_UPDATE_RESET; + GenericUpdateFlag = VALUE_UPDATE_RESET; } } #endif + + if(Generic_Trnsn_Cmplt == MOBLE_TRUE) + { + elementNumber = BLE_GetElementNumber(); + publishAddress = BLEMesh_GetPublishAddress(elementNumber,Model_ID); + if(publishAddress != 0x00) + { + Model_SendResponse(publishAddress,Dst_Peer,Generic_Rx_Opcode,pRxData,dataLength); + } + Generic_Trnsn_Cmplt = MOBLE_FALSE; + } } /** * @brief Generic_Publish: Publish command for Generic Model used while long prees * button. -* @param publishAddress: Publish Address of the message. -* @param elementIndex: index of the element. +* @param srcAddress: Source Address of the node * @retval void */ -void Generic_Publish(MOBLE_ADDRESS publishAddress, MOBLEUINT8 elementIndex) +void Generic_Publish(MOBLE_ADDRESS srcAddress) { MOBLEUINT8 generic_Buff[2]; + MOBLE_RESULT result = MOBLE_RESULT_SUCCESS; /* changes the LED status on other nodes in the network */ if(CommandStatus == (MOBLEUINT16)APPLI_LED_ON) @@ -1147,17 +1211,27 @@ void Generic_Publish(MOBLE_ADDRESS publishAddress, MOBLEUINT8 elementIndex) { generic_Buff[0] = APPLI_LED_ON; } + generic_Buff[1] = TidSend; - BLEMesh_SetRemoteData(publishAddress, elementIndex, + result = BLEMesh_SetRemotePublication(GENERIC_MODEL_SERVER_ONOFF_MODEL_ID, srcAddress , GENERIC_ON_OFF_SET_UNACK, generic_Buff, 2, MOBLE_FALSE, MOBLE_FALSE); + TidSend++; + if(TidSend >= MAX_TID_VALUE) + { + TidSend = 0; + } + if(result) + { + TRACE_M(TF_GENERIC,"Publication Error \r\n"); + } CommandStatus = generic_Buff[0]; } -/* +/** * @brief GenericOnOffStateUpdate_Process:Function to update the parametes of * Generic On Off model in application file from Temporary parameter in model file. * @param void @@ -1172,7 +1246,7 @@ MOBLE_RESULT GenericOnOffStateUpdate_Process(void) } -/* +/** * @brief GenericLevelStateUpdate_Process:function to update the parametes of Generic * Level model in application file from Temporary parameter in model file. * @param void @@ -1188,8 +1262,8 @@ MOBLE_RESULT GenericLevelStateUpdate_Process(void) } -/* -* @Brief GenericOnOff_LightActualBinding: Data binding b/w Generic On Off and +/** +* @brief GenericOnOff_LightActualBinding: Data binding b/w Generic On Off and * light lightness Actual. this function will set the actual light lightness * value at the time of generic on off set. * @param onOff_param: Pointer to the data which needs to be checked. @@ -1278,7 +1352,7 @@ void GenericLevel_LightActualBinding(Generic_LevelParam_t* gLevel_param) } -/* +/** * @brief GenericLevel_CtlTempBinding: Data binding b/w Generic level and Ctl * Temperature set. * @param bLevelParam: pointer to the structure, which should be set. @@ -1320,7 +1394,7 @@ void GenericLevel_HslHueBinding(Generic_LevelParam_t * bLevelParam) } -/* +/** * @brief GenericLevel_HslSaturationBinding: Data binding b/w Generic level and Hsl * Hue set. * @param bLevelParam: pointer to the structure, which should be set. @@ -1338,7 +1412,7 @@ void GenericLevel_HslSaturationBinding(Generic_LevelParam_t * bLevelParam) (LightAppli_cb.Light_HslSaturation_Set_cb)(&bHslSatstatus, 0); } -/* +/** * @brief function to assign the Pwm value to the target value of the generic on off * saved states. * @param void: @@ -1352,7 +1426,7 @@ void Generic_OnOffDefaultTransitionValue(void) Generic_ModelFlag.GenericOptionalParam = 1; } -/* +/** * @brief function called in generic level when the default transition time is enabled. * @param levelValue: generic level target value * return void. @@ -1366,117 +1440,121 @@ void Generic_LevelDefaultTransitionValue(MOBLEUINT16 levelValue) Generic_ModelFlag.GenericOptionalParam = 1; } -/* +/** * @brief Generic_Client_OnOff_Status: Function called when status of the model - received on the client. +received on the client. * @param pOnOff_status: ointer to the parameters received for message * @param plength: Length of the parameters received for message * return MOBLE_RESULT_SUCCESS. */ MOBLE_RESULT Generic_Client_OnOff_Status(MOBLEUINT8 const *pOnOff_status, MOBLEUINT32 plength) { - MOBLEUINT32 i; - - TRACE_M(TF_SERIAL_CTRL,"Generic_OnOff_Status callback received \r\n"); - for(i = 0; i < plength; i++) - TRACE_M(TF_SERIAL_CTRL,"Generic_OnOff_Status: %d\r\n", - pOnOff_status[i]); + TRACE_M(TF_GENERIC_CLIENT,"Generic_OnOff_Status received \r\n"); + GenericAppli_cb.OnOff_Status_cb(pOnOff_status , plength); return MOBLE_RESULT_SUCCESS; } -/* +/** * @brief Generic_Client_Level_Status: Function called when status of the model - received on the client. +received on the client. * @param plevel_status: ointer to the parameters received for message * @param plength: Length of the parameters received for message * return MOBLE_RESULT_SUCCESS. */ MOBLE_RESULT Generic_Client_Level_Status(MOBLEUINT8 const *plevel_status, MOBLEUINT32 plength) { - MOBLEUINT32 i; - TRACE_M(TF_GENERIC,"Generic_Level_Status callback received \r\n"); - for(i = 0; i < plength; i++) - TRACE_M(TF_SERIAL_CTRL,"Generic_Level_Status: %d\r\n", - plevel_status[i]); + TRACE_M(TF_GENERIC_CLIENT,"Generic_Level_Status received \r\n"); + GenericAppli_cb.Level_Status_cb(plevel_status , plength); return MOBLE_RESULT_SUCCESS; } -/* +/** * @brief Generic_Client_PowerOnOff_Status: Function called when status of the model - received on the client. +received on the client. * @param powerOnOff_status: ointer to the parameters received for message * @param plength: Length of the parameters received for message * return MOBLE_RESULT_SUCCESS. */ MOBLE_RESULT Generic_Client_PowerOnOff_Status(MOBLEUINT8 const *powerOnOff_status , MOBLEUINT32 plength) { - MOBLEUINT32 i; - TRACE_M(TF_GENERIC,"Generic_PowerOnOff_Status callback received \r\n"); - for(i = 0; i < plength; i++) - TRACE_M(TF_SERIAL_CTRL,"Generic_PowerOnOff_Status: %d\r\n", - powerOnOff_status[i]); + TRACE_M(TF_GENERIC_CLIENT,"Generic_PowerOnOff_Status received \r\n"); + GenericAppli_cb.GenericPowerOnOff_Status_cb(powerOnOff_status, plength); return MOBLE_RESULT_SUCCESS; } -/* +/** * @brief Generic_Client_DefaultTransitionTime_Status: Function called when status of the model - received on the client. +received on the client. * @param pTransition_status: ointer to the parameters received for message * @param plength: Length of the parameters received for message * return MOBLE_RESULT_SUCCESS. */ MOBLE_RESULT Generic_Client_DefaultTransitionTime_Status(MOBLEUINT8 const *pTransition_status , MOBLEUINT32 plength) { - MOBLEUINT32 i; - TRACE_M(TF_GENERIC,"Generic_DefaultTransitionTime_Status callback received \r\n"); - for(i = 0; i < plength; i++) - TRACE_M(TF_SERIAL_CTRL,"Generic_DefaultTransitionTime_Status: %d\r\n", - pTransition_status[i]); + TRACE_M(TF_GENERIC_CLIENT,"Generic_DefaultTransitionTime_Status received \r\n"); + GenericAppli_cb.GenericDefaultTransition_Status_cb(pTransition_status, plength); return MOBLE_RESULT_SUCCESS; } -/* Weak function are defined to support the original function if they are not +/** +* Weak function are defined to support the original function if they are not included in firmware. There is no use of this function for application development purpose. */ WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_OnOff_Set(Generic_OnOffStatus_t* pGeneric_OnOffParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_Level_Set(Generic_LevelStatus_t* plevelParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_LevelDelta_Set(Generic_LevelStatus_t* pdeltalevelParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_LevelMove_Set(Generic_LevelStatus_t* pdeltaMoveParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_PowerOnOff_Set(Generic_PowerOnOffParam_t* pPowerOnOffParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION (void Appli_Generic_Restore_PowerOn_Value(MOBLEUINT8 restoreValue)) +{} WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_DefaultTransitionTime_Set(Generic_DefaultTransitionParam_t* pDefaultTimeParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_OnOff_Status(MOBLEUINT8 const *pOnOff_status, MOBLEUINT32 plength)) +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_Level_Status(MOBLEUINT8 const *plevel_status, MOBLEUINT32 plength)) +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_PowerOnOff_Status(MOBLEUINT8 const *powerOnOff_status , MOBLEUINT32 plength)) +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_DefaultTransitionTime_Status(MOBLEUINT8 const *pTransition_status , MOBLEUINT32 plength)) +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_GetOnOffStatus(MOBLEUINT8* pOnOff_Status)) +{return MOBLE_RESULT_SUCCESS;} +WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_GetOnOffValue(MOBLEUINT8* pOnOff_Value) ) +{return MOBLE_RESULT_SUCCESS;} +WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_GetLevelStatus(MOBLEUINT8* pLevel_Status)) +{return MOBLE_RESULT_SUCCESS;} +WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_GetPowerOnOffStatus(MOBLEUINT8* pPower_Status)) +{return MOBLE_RESULT_SUCCESS;} +WEAK_FUNCTION (MOBLE_RESULT Appli_Generic_GetDefaultTransitionStatus(MOBLEUINT8* pTransition_Status)) +{return MOBLE_RESULT_SUCCESS;} +WEAK_FUNCTION(MOBLE_RESULT Appli_GenericClient_Level_Set_Unack(void)) +{return MOBLE_RESULT_SUCCESS;} /** * @} diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/generic_client.c b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/generic_client.c index d87e28582..7a6193bd9 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/generic_client.c +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/generic_client.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file generic_client.c * @author BLE Mesh Team -* @version V1.11.002 -* @date 27-09-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Generic model client middleware file ****************************************************************************** * @attention @@ -43,18 +43,17 @@ #include "mesh_cfg.h" #include "generic.h" #include "generic_client.h" -//#include "light.h" #include "common.h" #include "models_if.h" #include #include "compiler.h" -/** @addtogroup MODEL_GENERIC +/** @addtogroup MODEL_CLIENT_GENERIC * @{ */ -/** @addtogroup Generic_Model_Callbacks +/** @addtogroup Generic_Model_Client_Callbacks * @{ */ @@ -62,17 +61,17 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ - +extern MOBLEUINT8 TidSend; const MODEL_OpcodeTableParam_t Generic_Client_Opcodes_Table[] = { /* Generic OnOff Client */ /* MOBLEUINT32 opcode, MOBLEBOOL reliable, MOBLEUINT16 min_payload_size, MOBLEUINT16 max_payload_size; Here in this array, Handler is not defined; */ #ifdef ENABLE_GENERIC_MODEL_CLIENT_ONOFF - {GENERIC_ON_OFF_STATUS, MOBLE_FALSE, 1, 3, NULL , 1, 3}, + {GENERIC_MODEL_SERVER_ONOFF_MODEL_ID ,GENERIC_ON_OFF_STATUS, MOBLE_FALSE, 1, 3, 0 , 1, 3}, #endif #ifdef ENABLE_GENERIC_MODEL_CLIENT_LEVEL - {GENERIC_LEVEL_STATUS, MOBLE_FALSE, 2, 5, NULL , 2 , 5}, + {GENERIC_MODEL_SERVER_LEVEL_MODEL_ID ,GENERIC_LEVEL_STATUS, MOBLE_FALSE, 2, 5, 0 , 2 , 5}, #endif {0} }; @@ -166,7 +165,7 @@ MOBLE_RESULT GenericClient_OnOff_Set_Unack(MOBLE_ADDRESS element_number, MOBLEBOOL ack_flag; TRACE_M(TF_GENERIC_CLIENT,"Generic_OnOff_Set Client Message \r\n"); - + pOnOff_param->a_OnOff_param[1] = TidSend; msg_buff = pOnOff_param->a_OnOff_param; ack_flag = MOBLE_FALSE; msg_opcode = GENERIC_ON_OFF_SET_UNACK; @@ -181,6 +180,12 @@ MOBLE_RESULT GenericClient_OnOff_Set_Unack(MOBLE_ADDRESS element_number, msg_buff, length, ack_flag, MOBLE_FALSE); + TidSend++; + if(TidSend >= MAX_TID_VALUE) + { + TidSend = 0; + } + if(result) { TRACE_M(TF_GENERIC_CLIENT,"Publication Error \r\n"); @@ -214,7 +219,7 @@ MOBLE_RESULT GenericClient_Level_Set_Unack(MOBLE_ADDRESS element_number, MOBLEBOOL ack_flag; TRACE_M(TF_GENERIC_CLIENT,"Generic_Level_Set Client Message \r\n"); - + plevel_param->a_Level_param[2] = TidSend; msg_buff = plevel_param->a_Level_param; ack_flag = MOBLE_TRUE; msg_opcode = GENERIC_LEVEL_SET_UNACK; @@ -229,6 +234,11 @@ MOBLE_RESULT GenericClient_Level_Set_Unack(MOBLE_ADDRESS element_number, msg_buff, length, ack_flag, MOBLE_FALSE); + TidSend++; + if(TidSend >= MAX_TID_VALUE) + { + TidSend = 0; + } if(result) { TRACE_M(TF_GENERIC_CLIENT,"Publication Error \r\n"); @@ -255,7 +265,7 @@ MOBLE_RESULT GenericModelClient_GetOpcodeTableCb(const MODEL_OpcodeTableParam_t /** * @brief GenericModelClient_GetStatusRequestCb : This function is call-back -from the library to send response to the message from peer +* from the library to send response to the message from peer * @param peer_addr: Address of the peer * @param dst_peer: destination send by peer for this node. It can be a * unicast or group address @@ -277,7 +287,7 @@ MOBLE_RESULT GenericModelClient_GetStatusRequestCb(MOBLE_ADDRESS peer_addr, MOBLEBOOL response) { - TRACE_M(TF_GENERIC,"response status enable \n\r"); + TRACE_M(TF_GENERIC_CLIENT,"response status enable \n\r"); return MOBLE_RESULT_SUCCESS; } @@ -285,7 +295,7 @@ MOBLE_RESULT GenericModelClient_GetStatusRequestCb(MOBLE_ADDRESS peer_addr, /** * @brief GenericModelClient_ProcessMessageCb: This is a callback function from -the library whenever a Generic Model message is received +* the library whenever a Generic Model message is received * @param peer_addr: Address of the peer * @param dst_peer: destination send by peer for this node. It can be a * unicast or group address @@ -308,9 +318,9 @@ MOBLE_RESULT GenericModelClient_ProcessMessageCb(MOBLE_ADDRESS peer_addr, { MOBLE_RESULT result = MOBLE_RESULT_SUCCESS; - tClockTime delay_t = Clock_Time(); + //tClockTime delay_t = Clock_Time(); - TRACE_M(TF_GENERIC,"dst_peer = %.2X , peer_add = %.2X, opcode= %.2X ,response= %.2X \r\n ", + TRACE_M(TF_GENERIC_CLIENT,"dst_peer = %.2X , peer_add = %.2X, opcode= %.2X ,response= %.2X \r\n ", dst_peer, peer_addr, opcode , response); switch(opcode) @@ -339,67 +349,6 @@ MOBLE_RESULT GenericModelClient_ProcessMessageCb(MOBLE_ADDRESS peer_addr, return MOBLE_RESULT_SUCCESS; } -/* -* @brief Generic_Client_OnOff_Status: Function called when status of the model -received on the client. -* @param pOnOff_status: ointer to the parameters received for message -* @param plength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Generic_Client_OnOff_Status(MOBLEUINT8 const *pOnOff_status, MOBLEUINT32 plength) -{ - TRACE_M(TF_GENERIC,"Generic_OnOff_Status callback received \r\n"); - return MOBLE_RESULT_SUCCESS; -} - -/* -* @brief Generic_Client_Level_Status: Function called when status of the model -received on the client. -* @param plevel_status: ointer to the parameters received for message -* @param plength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Generic_Client_Level_Status(MOBLEUINT8 const *plevel_status, MOBLEUINT32 plength) -{ - - TRACE_M(TF_GENERIC,"Generic_Level_Status callback received \r\n"); - return MOBLE_RESULT_SUCCESS; -} - -/* -* @brief Generic_Client_PowerOnOff_Status: Function called when status of the model -received on the client. -* @param powerOnOff_status: ointer to the parameters received for message -* @param plength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Generic_Client_PowerOnOff_Status(MOBLEUINT8 const *powerOnOff_status , MOBLEUINT32 plength) -{ - - TRACE_M(TF_GENERIC,"Generic_PowerOnOff_Status callback received \r\n"); - return MOBLE_RESULT_SUCCESS; -} - -/* -* @brief Generic_Client_DefaultTransitionTime_Status: Function called when status of the model -received on the client. -* @param pTransition_status: ointer to the parameters received for message -* @param plength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Generic_Client_DefaultTransitionTime_Status(MOBLEUINT8 const *pTransition_status , MOBLEUINT32 plength) -{ - - TRACE_M(TF_GENERIC,"Generic_DefaultTransitionTime_Status callback received \r\n"); - return MOBLE_RESULT_SUCCESS; -} - -/** -Weak function are defined to support the original function if they are not -included in firmware. -There is no use of this function for application development purpose. -**/ - /** * @} */ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/light.c b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/light.c index 3dd2265d7..e90bddaf7 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/light.c +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/light.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file light.c * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Light Model middleware implementation ****************************************************************************** * @attention @@ -84,84 +84,84 @@ MOBLEUINT8 LightUpdateFlag = 0; const MODEL_OpcodeTableParam_t Light_Opcodes_Table[] = { #ifdef ENABLE_LIGHT_MODEL_SERVER_LIGHTNESS - {LIGHT_LIGHTNESS_GET, MOBLE_TRUE, 0, 0, LIGHT_LIGHTNESS_STATUS, 2, 5}, - {LIGHT_LIGHTNESS_SET, MOBLE_TRUE, 3, 5, LIGHT_LIGHTNESS_STATUS, 2, 5}, - {LIGHT_LIGHTNESS_SET_UNACK, MOBLE_FALSE, 3, 5, 0, 2, 5}, - {LIGHT_LIGHTNESS_STATUS, MOBLE_FALSE, 2, 5, 0, 2, 5}, - {LIGHT_LIGHTNESS_LINEAR_GET, MOBLE_TRUE, 0, 0, LIGHT_LIGHTNESS_LINEAR_STATUS, 2, 5}, - {LIGHT_LIGHTNESS_LINEAR_SET, MOBLE_TRUE, 3, 5, LIGHT_LIGHTNESS_LINEAR_STATUS, 2, 5}, - {LIGHT_LIGHTNESS_LINEAR_SET_UNACK, MOBLE_FALSE, 3, 5, 0, 2, 5}, - {LIGHT_LIGHTNESS_LINEAR_STATUS, MOBLE_FALSE, 2, 5, 0, 2, 5}, - {LIGHT_LIGHTNESS_DEFAULT_GET, MOBLE_TRUE, 0, 0, LIGHT_LIGHTNESS_DEFAULT_STATUS,2, 2}, - {LIGHT_LIGHTNESS_DEFAULT_STATUS, MOBLE_FALSE, 2, 2, 0,2, 2}, - {LIGHT_LIGHTNESS_RANGE_GET, MOBLE_TRUE, 0, 0, LIGHT_LIGHTNESS_RANGE_STATUS, 5, 5}, - {LIGHT_LIGHTNESS_RANGE_STATUS, MOBLE_FALSE, 5, 5, 0, 5, 5}, + {LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID ,LIGHT_LIGHTNESS_GET, MOBLE_TRUE, 0, 0, LIGHT_LIGHTNESS_STATUS, 2, 5}, + {LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID ,LIGHT_LIGHTNESS_SET, MOBLE_TRUE, 3, 5, LIGHT_LIGHTNESS_STATUS, 2, 5}, + {LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID ,LIGHT_LIGHTNESS_SET_UNACK, MOBLE_FALSE, 3, 5, 0, 2, 5}, + {LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID ,LIGHT_LIGHTNESS_STATUS, MOBLE_FALSE, 2, 5, 0, 2, 5}, + {LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID ,LIGHT_LIGHTNESS_LINEAR_GET, MOBLE_TRUE, 0, 0, LIGHT_LIGHTNESS_LINEAR_STATUS, 2, 5}, + {LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID ,LIGHT_LIGHTNESS_LINEAR_SET, MOBLE_TRUE, 3, 5, LIGHT_LIGHTNESS_LINEAR_STATUS, 2, 5}, + {LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID ,LIGHT_LIGHTNESS_LINEAR_SET_UNACK, MOBLE_FALSE, 3, 5, 0, 2, 5}, + {LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID ,LIGHT_LIGHTNESS_LINEAR_STATUS, MOBLE_FALSE, 2, 5, 0, 2, 5}, + {LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID ,LIGHT_LIGHTNESS_DEFAULT_GET, MOBLE_TRUE, 0, 0, LIGHT_LIGHTNESS_DEFAULT_STATUS,2, 2}, + {LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID ,LIGHT_LIGHTNESS_DEFAULT_STATUS, MOBLE_FALSE, 2, 2, 0,2, 2}, + {LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID ,LIGHT_LIGHTNESS_RANGE_GET, MOBLE_TRUE, 0, 0, LIGHT_LIGHTNESS_RANGE_STATUS, 5, 5}, + {LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID ,LIGHT_LIGHTNESS_RANGE_STATUS, MOBLE_FALSE, 5, 5, 0, 5, 5}, #endif #ifdef ENABLE_LIGHT_MODEL_SERVER_LIGHTNESS_SETUP - {LIGHT_LIGHTNESS_DEFAULT_SET, MOBLE_TRUE, 2, 2, LIGHT_LIGHTNESS_DEFAULT_STATUS, 2, 2}, - {LIGHT_LIGHTNESS_DEFAULT_SET_UNACK, MOBLE_FALSE, 2, 2, 0, 2, 2}, - {LIGHT_LIGHTNESS_RANGE_SET, MOBLE_TRUE, 4, 4, LIGHT_LIGHTNESS_RANGE_STATUS, 5, 5}, - {LIGHT_LIGHTNESS_RANGE_SET_UNACK, MOBLE_FALSE, 4, 4, 0, 5, 5}, + {LIGHT_MODEL_SERVER_LIGHTNESS_SETUP_MODEL_ID ,LIGHT_LIGHTNESS_DEFAULT_SET, MOBLE_TRUE, 2, 2, LIGHT_LIGHTNESS_DEFAULT_STATUS, 2, 2}, + {LIGHT_MODEL_SERVER_LIGHTNESS_SETUP_MODEL_ID ,LIGHT_LIGHTNESS_DEFAULT_SET_UNACK, MOBLE_FALSE, 2, 2, 0, 2, 2}, + {LIGHT_MODEL_SERVER_LIGHTNESS_SETUP_MODEL_ID ,LIGHT_LIGHTNESS_RANGE_SET, MOBLE_TRUE, 4, 4, LIGHT_LIGHTNESS_RANGE_STATUS, 5, 5}, + {LIGHT_MODEL_SERVER_LIGHTNESS_SETUP_MODEL_ID ,LIGHT_LIGHTNESS_RANGE_SET_UNACK, MOBLE_FALSE, 4, 4, 0, 5, 5}, #endif #ifdef ENABLE_LIGHT_MODEL_SERVER_CTL - {LIGHT_CTL_GET, MOBLE_TRUE, 0, 0, LIGHT_CTL_STATUS, 4, 9}, - {LIGHT_CTL_SET, MOBLE_TRUE, 7, 9, LIGHT_CTL_STATUS, 4, 9}, - {LIGHT_CTL_SET_UNACK, MOBLE_FALSE, 7, 9, 0, 4, 9}, - {LIGHT_CTL_STATUS, MOBLE_FALSE, 4, 9, 0, 4, 9}, - {LIGHT_CTL_TEMPERATURE_RANGE_GET, MOBLE_TRUE, 0, 0, LIGHT_CTL_TEMPERATURE_RANGE_STATUS, 5, 5}, - {LIGHT_CTL_TEMPERATURE_RANGE_STATUS, MOBLE_FALSE, 5, 5, 0, 5, 5}, - {LIGHT_CTL_DEFAULT_GET, MOBLE_TRUE, 0, 0, LIGHT_CTL_DEFAULT_STATUS, 6, 6}, - {LIGHT_CTL_DEFAULT_STATUS, MOBLE_TRUE, 6, 6, 0, 6, 6}, + {LIGHT_MODEL_SERVER_CTL_MODEL_ID ,LIGHT_CTL_GET, MOBLE_TRUE, 0, 0, LIGHT_CTL_STATUS, 4, 9}, + {LIGHT_MODEL_SERVER_CTL_MODEL_ID ,LIGHT_CTL_SET, MOBLE_TRUE, 7, 9, LIGHT_CTL_STATUS, 4, 9}, + {LIGHT_MODEL_SERVER_CTL_MODEL_ID ,LIGHT_CTL_SET_UNACK, MOBLE_FALSE, 7, 9, 0, 4, 9}, + {LIGHT_MODEL_SERVER_CTL_MODEL_ID ,LIGHT_CTL_STATUS, MOBLE_FALSE, 4, 9, 0, 4, 9}, + {LIGHT_MODEL_SERVER_CTL_MODEL_ID ,LIGHT_CTL_TEMPERATURE_RANGE_GET, MOBLE_TRUE, 0, 0, LIGHT_CTL_TEMPERATURE_RANGE_STATUS, 5, 5}, + {LIGHT_MODEL_SERVER_CTL_MODEL_ID ,LIGHT_CTL_TEMPERATURE_RANGE_STATUS, MOBLE_FALSE, 5, 5, 0, 5, 5}, + {LIGHT_MODEL_SERVER_CTL_MODEL_ID ,LIGHT_CTL_DEFAULT_GET, MOBLE_TRUE, 0, 0, LIGHT_CTL_DEFAULT_STATUS, 6, 6}, + {LIGHT_MODEL_SERVER_CTL_MODEL_ID ,LIGHT_CTL_DEFAULT_STATUS, MOBLE_TRUE, 6, 6, 0, 6, 6}, #endif #ifdef ENABLE_LIGHT_MODEL_SERVER_CTL_SETUP - {LIGHT_CTL_DEFAULT_SET, MOBLE_TRUE, 6, 6, LIGHT_CTL_DEFAULT_STATUS, 6, 6}, - {LIGHT_CTL_DEFAULT_SET_UNACK, MOBLE_FALSE, 6, 6, 0, 6, 6}, - {LIGHT_CTL_TEMPERATURE_RANGE_SET, MOBLE_TRUE, 4, 4, LIGHT_CTL_TEMPERATURE_RANGE_STATUS, 5, 5}, - {LIGHT_CTL_TEMPERATURE_RANGE_SET_UNACK, MOBLE_FALSE, 4, 4, 0, 5, 5}, + {LIGHT_MODEL_SERVER_CTL_SETUP_MODEL_ID ,LIGHT_CTL_DEFAULT_SET, MOBLE_TRUE, 6, 6, LIGHT_CTL_DEFAULT_STATUS, 6, 6}, + {LIGHT_MODEL_SERVER_CTL_SETUP_MODEL_ID ,LIGHT_CTL_DEFAULT_SET_UNACK, MOBLE_FALSE, 6, 6, 0, 6, 6}, + {LIGHT_MODEL_SERVER_CTL_SETUP_MODEL_ID ,LIGHT_CTL_TEMPERATURE_RANGE_SET, MOBLE_TRUE, 4, 4, LIGHT_CTL_TEMPERATURE_RANGE_STATUS, 5, 5}, + {LIGHT_MODEL_SERVER_CTL_SETUP_MODEL_ID ,LIGHT_CTL_TEMPERATURE_RANGE_SET_UNACK, MOBLE_FALSE, 4, 4, 0, 5, 5}, #endif #ifdef ENABLE_LIGHT_MODEL_SERVER_CTL_TEMPERATURE - {LIGHT_CTL_TEMPERATURE_GET, MOBLE_TRUE, 0, 0, LIGHT_CTL_TEMPERATURE_STATUS, 4, 9}, - {LIGHT_CTL_TEMPERATURE_SET, MOBLE_TRUE, 5, 7, LIGHT_CTL_TEMPERATURE_STATUS, 4, 9}, - {LIGHT_CTL_TEMPERATURE_SET_UNACK, MOBLE_FALSE, 5, 7, 0, 4, 9}, - {LIGHT_CTL_TEMPERATURE_STATUS, MOBLE_FALSE, 4, 9, 0, 4, 9}, + {LIGHT_MODEL_SERVER_CTL_TEMPERATURE_MODEL_ID ,LIGHT_CTL_TEMPERATURE_GET, MOBLE_TRUE, 0, 0, LIGHT_CTL_TEMPERATURE_STATUS, 4, 9}, + {LIGHT_MODEL_SERVER_CTL_TEMPERATURE_MODEL_ID ,LIGHT_CTL_TEMPERATURE_SET, MOBLE_TRUE, 5, 7, LIGHT_CTL_TEMPERATURE_STATUS, 4, 9}, + {LIGHT_MODEL_SERVER_CTL_TEMPERATURE_MODEL_ID ,LIGHT_CTL_TEMPERATURE_SET_UNACK, MOBLE_FALSE, 5, 7, 0, 4, 9}, + {LIGHT_MODEL_SERVER_CTL_TEMPERATURE_MODEL_ID ,LIGHT_CTL_TEMPERATURE_STATUS, MOBLE_FALSE, 4, 9, 0, 4, 9}, #endif #ifdef ENABLE_LIGHT_MODEL_SERVER_HSL - {LIGHT_HSL_GET, MOBLE_TRUE, 0, 0, LIGHT_HSL_STATUS, 6, 7}, - {LIGHT_HSL_SET, MOBLE_TRUE, 7, 9, LIGHT_HSL_STATUS, 6, 7}, - {LIGHT_HSL_SET_UNACK, MOBLE_FALSE, 7, 9, 0, 6, 7}, - {LIGHT_HSL_STATUS, MOBLE_FALSE, 6, 7, 0, 6, 7}, - {LIGHT_HSL_TARGET_GET, MOBLE_TRUE, 0, 0, LIGHT_HSL_TARGET_STATUS, 6, 7}, - {LIGHT_HSL_TARGET_STATUS, MOBLE_FALSE, 6, 7, 0, 6, 7}, - {LIGHT_HSL_DEFAULT_GET, MOBLE_TRUE, 0, 0, LIGHT_HSL_DEFAULT_STATUS, 6, 6}, - {LIGHT_HSL_DEFAULT_STATUS, MOBLE_FALSE, 6, 6, 0, 6, 6}, - {LIGHT_HSL_RANGE_GET, MOBLE_TRUE, 0, 0, LIGHT_HSL_RANGE_STATUS, 9, 9}, - {LIGHT_HSL_RANGE_STATUS, MOBLE_TRUE, 9, 9, 0, 9, 9}, + {LIGHT_MODEL_SERVER_HSL_MODEL_ID ,LIGHT_HSL_GET, MOBLE_TRUE, 0, 0, LIGHT_HSL_STATUS, 6, 7}, + {LIGHT_MODEL_SERVER_HSL_MODEL_ID ,LIGHT_HSL_SET, MOBLE_TRUE, 7, 9, LIGHT_HSL_STATUS, 6, 7}, + {LIGHT_MODEL_SERVER_HSL_MODEL_ID ,LIGHT_HSL_SET_UNACK, MOBLE_FALSE, 7, 9, 0, 6, 7}, + {LIGHT_MODEL_SERVER_HSL_MODEL_ID ,LIGHT_HSL_STATUS, MOBLE_FALSE, 6, 7, 0, 6, 7}, + {LIGHT_MODEL_SERVER_HSL_MODEL_ID ,LIGHT_HSL_TARGET_GET, MOBLE_TRUE, 0, 0, LIGHT_HSL_TARGET_STATUS, 6, 7}, + {LIGHT_MODEL_SERVER_HSL_MODEL_ID ,LIGHT_HSL_TARGET_STATUS, MOBLE_FALSE, 6, 7, 0, 6, 7}, + {LIGHT_MODEL_SERVER_HSL_MODEL_ID ,LIGHT_HSL_DEFAULT_GET, MOBLE_TRUE, 0, 0, LIGHT_HSL_DEFAULT_STATUS, 6, 6}, + {LIGHT_MODEL_SERVER_HSL_MODEL_ID ,LIGHT_HSL_DEFAULT_STATUS, MOBLE_FALSE, 6, 6, 0, 6, 6}, + {LIGHT_MODEL_SERVER_HSL_MODEL_ID ,LIGHT_HSL_RANGE_GET, MOBLE_TRUE, 0, 0, LIGHT_HSL_RANGE_STATUS, 9, 9}, + {LIGHT_MODEL_SERVER_HSL_MODEL_ID ,LIGHT_HSL_RANGE_STATUS, MOBLE_TRUE, 9, 9, 0, 9, 9}, #endif #ifdef ENABLE_LIGHT_MODEL_SERVER_HSL_SETUP - {LIGHT_HSL_RANGE_SET, MOBLE_TRUE, 8, 8, LIGHT_HSL_RANGE_STATUS, 9, 9}, - {LIGHT_HSL_RANGE_SET_UNACK, MOBLE_FALSE, 8, 8, 0, 9, 9}, - {LIGHT_HSL_DEFAULT_SET, MOBLE_TRUE, 6, 6, LIGHT_HSL_DEFAULT_STATUS, 6, 6}, - {LIGHT_HSL_DEFAULT_SET_UNACK, MOBLE_FALSE, 6, 6, 0, 6, 6}, + {LIGHT_MODEL_SERVER_HSL_SETUP_MODEL_ID ,LIGHT_HSL_RANGE_SET, MOBLE_TRUE, 8, 8, LIGHT_HSL_RANGE_STATUS, 9, 9}, + {LIGHT_MODEL_SERVER_HSL_SETUP_MODEL_ID ,LIGHT_HSL_RANGE_SET_UNACK, MOBLE_FALSE, 8, 8, 0, 9, 9}, + {LIGHT_MODEL_SERVER_HSL_SETUP_MODEL_ID ,LIGHT_HSL_DEFAULT_SET, MOBLE_TRUE, 6, 6, LIGHT_HSL_DEFAULT_STATUS, 6, 6}, + {LIGHT_MODEL_SERVER_HSL_SETUP_MODEL_ID ,LIGHT_HSL_DEFAULT_SET_UNACK, MOBLE_FALSE, 6, 6, 0, 6, 6}, #endif #ifdef ENABLE_LIGHT_MODEL_SERVER_HSL_HUE - {LIGHT_HSL_HUE_GET, MOBLE_TRUE, 0, 0, LIGHT_HSL_HUE_STATUS, 2, 5}, - {LIGHT_HSL_HUE_SET, MOBLE_TRUE, 3, 5, LIGHT_HSL_HUE_STATUS, 2, 5}, - {LIGHT_HSL_HUE_SET_UNACK, MOBLE_FALSE, 3, 5, 0, 2, 5}, - {LIGHT_HSL_HUE_STATUS, MOBLE_FALSE, 2, 5, 0, 2, 5}, + {LIGHT_MODEL_SERVER_HSL_HUE_MODEL_ID ,LIGHT_HSL_HUE_GET, MOBLE_TRUE, 0, 0, LIGHT_HSL_HUE_STATUS, 2, 5}, + {LIGHT_MODEL_SERVER_HSL_HUE_MODEL_ID ,LIGHT_HSL_HUE_SET, MOBLE_TRUE, 3, 5, LIGHT_HSL_HUE_STATUS, 2, 5}, + {LIGHT_MODEL_SERVER_HSL_HUE_MODEL_ID ,LIGHT_HSL_HUE_SET_UNACK, MOBLE_FALSE, 3, 5, 0, 2, 5}, + {LIGHT_MODEL_SERVER_HSL_HUE_MODEL_ID ,LIGHT_HSL_HUE_STATUS, MOBLE_FALSE, 2, 5, 0, 2, 5}, #endif #ifdef ENABLE_LIGHT_MODEL_SERVER_HSL_SATURATION - {LIGHT_HSL_SATURATION_GET, MOBLE_TRUE, 0, 0, LIGHT_HSL_SATURATION_STATUS, 2, 5}, - {LIGHT_HSL_SATURATION_SET, MOBLE_TRUE, 3, 5, LIGHT_HSL_SATURATION_STATUS, 2, 5}, - {LIGHT_HSL_SATURATION_SET_UNACK, MOBLE_FALSE, 3, 5, 0, 2, 5}, - {LIGHT_HSL_SATURATION_STATUS, MOBLE_FALSE, 2, 5, 0, 2, 5}, + {LIGHT_MODEL_SERVER_HSL_SATURATION_MODEL_ID ,LIGHT_HSL_SATURATION_GET, MOBLE_TRUE, 0, 0, LIGHT_HSL_SATURATION_STATUS, 2, 5}, + {LIGHT_MODEL_SERVER_HSL_SATURATION_MODEL_ID ,LIGHT_HSL_SATURATION_SET, MOBLE_TRUE, 3, 5, LIGHT_HSL_SATURATION_STATUS, 2, 5}, + {LIGHT_MODEL_SERVER_HSL_SATURATION_MODEL_ID ,LIGHT_HSL_SATURATION_SET_UNACK, MOBLE_FALSE, 3, 5, 0, 2, 5}, + {LIGHT_MODEL_SERVER_HSL_SATURATION_MODEL_ID ,LIGHT_HSL_SATURATION_STATUS, MOBLE_FALSE, 2, 5, 0, 2, 5}, #endif {0} }; @@ -211,6 +211,20 @@ WEAK_FUNCTION(MOBLE_RESULT Appli_Light_GetHslSatRange(MOBLEUINT8* lHslSatRange)) WEAK_FUNCTION(void HSL_RGB_Conversion(void)); WEAK_FUNCTION(void RgbF_Create(MOBLEUINT16 value1, MOBLEUINT16 value2, MOBLEUINT16 value3)); WEAK_FUNCTION(void Light_UpdatePWMValue(MOBLEUINT8 state)); +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_GetHslDefaultStatus(MOBLEUINT8* lHslDefaultState)); +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_Lightness_Status(MOBLEUINT8 const *pLightness_status, MOBLEUINT32 pLength)); +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_Lightness_Linear_Status(MOBLEUINT8 const *pLightnessLinear_status, MOBLEUINT32 pLength)); +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_Lightness_Default_Status(MOBLEUINT8 const *pLightnessDefault_status, MOBLEUINT32 pLength)); +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_Lightness_Range_Status(MOBLEUINT8 const *pLightnessRange_status, MOBLEUINT32 pLength)); +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_Ctl_Status(MOBLEUINT8 const *pLightCtl_status, MOBLEUINT32 pLength)); +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_CtlTemperature_Status(MOBLEUINT8 const *pLightCtlTemp_status, MOBLEUINT32 pLength)); +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_CtlTemperature_Range_Status(MOBLEUINT8 const *pCtlTempRange_status, MOBLEUINT32 pLength)); +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_CtlDefault_Status(MOBLEUINT8 const *pCtlDefault_status, MOBLEUINT32 pLength)); +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_Hsl_Status(MOBLEUINT8 const *pHsl_status, MOBLEUINT32 pLength)); +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_HslHue_Status(MOBLEUINT8 const *pHslHue_status, MOBLEUINT32 pLength)); +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_HslSaturation_Status(MOBLEUINT8 const *pHslSaturation_status, MOBLEUINT32 pLength)); +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_HslDefault_Status(MOBLEUINT8 const *pHslDefault_status, MOBLEUINT32 pLength)); +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_HslRange_Status(MOBLEUINT8 const *pHslRange_status, MOBLEUINT32 pLength)); /* Private functions ---------------------------------------------------------*/ @@ -316,6 +330,7 @@ MOBLE_RESULT Light_Lightness_Status(MOBLEUINT8* pLightness_status, MOBLEUINT32* MOBLEUINT8 Light_GetBuff[2]; TRACE_M(TF_LIGHT,"Light_Lightness_Status callback received \r\n"); + TRACE_M(TF_SERIAL_CTRL,"#824B! \n\r"); /* reading the value from the application by passing Appli_LightParam array parameter @@ -440,6 +455,7 @@ MOBLE_RESULT Light_Lightness_Linear_Status(MOBLEUINT8* pLightnessLinear_status, MOBLEUINT8 Light_GetBuff[2]; TRACE_M(TF_LIGHT,"Light_Lightness_Linear_Status callback received \r\n"); + TRACE_M(TF_SERIAL_CTRL,"#824F! \n\r"); /* reading the value from the application by passing Appli_LightParam array parameter @@ -493,6 +509,7 @@ MOBLE_RESULT Light_Lightness_Last_Status(MOBLEUINT8* pLightnessLast_status, MOBL MOBLEUINT8 Light_GetBuff[4]; TRACE_M(TF_LIGHT,"Light_Lightness_Last_Status callback received \r\n"); + TRACE_M(TF_SERIAL_CTRL,"#8253! \n\r"); /* Function call back to get the values from application*/ (Appli_Light_GetStatus_cb.GetLightLightness_cb)(Light_GetBuff); @@ -546,6 +563,7 @@ MOBLE_RESULT Light_Lightness_Default_Status(MOBLEUINT8* pLightnessDefault_status MOBLEUINT8 Light_GetBuff[2]; TRACE_M(TF_LIGHT,"Light_Lightness_Default_Status callback received \r\n"); + TRACE_M(TF_SERIAL_CTRL,"#8255! \n\r"); /* Function call back to get the values from application*/ (Appli_Light_GetStatus_cb.GetLightLightnessDefault_cb)(Light_GetBuff); @@ -606,6 +624,7 @@ MOBLE_RESULT Light_Lightness_Range_Status(MOBLEUINT8* pLightnessRange_status, MO MOBLEUINT8 Light_GetBuff[5]; TRACE_M(TF_LIGHT,"Light_Lightness_Range_Status callback received \r\n"); + TRACE_M(TF_SERIAL_CTRL,"#8257! \n\r"); /* Function call back to get the values from application*/ (Appli_Light_GetStatus_cb.GetLightLightnessRange_cb)(Light_GetBuff); @@ -654,7 +673,7 @@ MOBLE_RESULT Light_Ctl_Set(const MOBLEUINT8* pLightCtl_param, MOBLEUINT32 length if((Light_CtlParam.Last_Lightness == Light_CtlParam.CTL_Lightness) && (Light_CtlParam.Last_Temperature == Light_CtlParam.CTL_Temperature)) { - return MOBLE_RESULT_INVALIDARG; + TRACE_M(TF_LIGHT,"Received Value is same to last values received \r\n"); } Light_CtlParam.Last_Lightness = Light_CtlParam.CTL_Lightness; @@ -718,6 +737,7 @@ MOBLE_RESULT Light_Ctl_Status(MOBLEUINT8* pLightCtl_status, MOBLEUINT32 *pLength MOBLEUINT8 Light_GetBuff[4]; TRACE_M(TF_LIGHT,"Light_Ctl_Status callback received \r\n"); + TRACE_M(TF_SERIAL_CTRL,"#825D! \n\r"); /* Function call back to get the values from application*/ (Appli_Light_GetStatus_cb.GetLightCtl_cb)(Light_GetBuff); @@ -839,6 +859,7 @@ MOBLE_RESULT Light_CtlTemperature_Status(MOBLEUINT8* pLightCtlTemp_status, MOBLE MOBLEUINT8 Light_GetBuff[4]; TRACE_M(TF_LIGHT,"Light_CtlTemperature_Status callback received \r\n"); + TRACE_M(TF_SERIAL_CTRL,"#8261! \n\r"); /* Function call back to get the values from application*/ (Appli_Light_GetStatus_cb.GetLightCtlTemp_cb)(Light_GetBuff); @@ -941,6 +962,7 @@ MOBLE_RESULT Light_CtlTemperature_Range_Status(MOBLEUINT8* pCtlTempRange_status, MOBLEUINT8 Light_GetBuff[5]; TRACE_M(TF_LIGHT,"Light_CtlTemperature_Range_Status callback received \r\n"); + TRACE_M(TF_SERIAL_CTRL,"#8262! \n\r"); /* Function call back to get the values from application*/ (Appli_Light_GetStatus_cb.GetLightCtlTempRange_cb)(Light_GetBuff); @@ -1010,6 +1032,7 @@ MOBLE_RESULT Light_CtlDefault_Status(MOBLEUINT8* pCtlDefault_status, MOBLEUINT32 MOBLEUINT8 Light_GetBuff[6]; TRACE_M(TF_LIGHT,"Light_Ctl_DefaultStatus callback received \r\n"); + TRACE_M(TF_SERIAL_CTRL,"#8267! \n\r"); /* Function call back to get the values from application*/ (Appli_Light_GetStatus_cb.GetLightCtlDefault_cb)(Light_GetBuff); @@ -1114,6 +1137,7 @@ MOBLE_RESULT Light_Hsl_Status(MOBLEUINT8* pHsl_status, MOBLEUINT32 *pLength) MOBLEUINT8 Light_GetBuff[8]; TRACE_M(TF_LIGHT,"Light_Hsl_Status callback received \r\n"); + TRACE_M(TF_SERIAL_CTRL,"#826D! \n\r"); /* Function call back to get the values from application*/ (Appli_Light_GetStatus_cb.GetLightHsl_cb)(Light_GetBuff); @@ -1225,6 +1249,7 @@ MOBLE_RESULT Light_HslHue_Status(MOBLEUINT8* pHslHue_status, MOBLEUINT32 *pLengt MOBLEUINT8 Light_GetBuff[6]; TRACE_M(TF_LIGHT,"Light_HslHue_Status callback received \r\n"); + TRACE_M(TF_SERIAL_CTRL,"#826E! \n\r"); /* Function call back to get the values from application*/ (Appli_Light_GetStatus_cb.GetLightHslHue_cb)(Light_GetBuff); @@ -1330,6 +1355,7 @@ MOBLE_RESULT Light_HslSaturation_Status(MOBLEUINT8* pHslSaturation_status, MOBLE MOBLEUINT8 Light_GetBuff[6]; TRACE_M(TF_LIGHT,"Light_HslSaturation_Status callback received \r\n"); + TRACE_M(TF_SERIAL_CTRL,"#8272! \n\r"); /* Function call back to get the values from application*/ (Appli_Light_GetStatus_cb.GetLightHslSaturation_cb)(Light_GetBuff); @@ -1407,9 +1433,10 @@ MOBLE_RESULT Light_HslDefault_Status(MOBLEUINT8* pHslDefault_status, MOBLEUINT32 MOBLEUINT8 Light_GetBuff[6]; TRACE_M(TF_LIGHT,"Light_HslDefault_Status callback received \r\n"); + TRACE_M(TF_SERIAL_CTRL,"#827B! \n\r"); /* Function call back to get the values from application*/ - (Appli_Light_GetStatus_cb.GetLightHsl_cb)(Light_GetBuff); + (Appli_Light_GetStatus_cb.GetLightHslDefault_cb)(Light_GetBuff); Light_HslStatus.PresentHslLightness16 = Light_GetBuff[1] << 8; Light_HslStatus.PresentHslLightness16 |= Light_GetBuff[0]; @@ -1478,6 +1505,7 @@ MOBLE_RESULT Light_HslRange_Status(MOBLEUINT8* pHslRange_status, MOBLEUINT32 *pL */ TRACE_M(TF_LIGHT,"Light_HslRange_Status callback received \r\n"); + TRACE_M(TF_SERIAL_CTRL,"#827D! \n\r"); /* Function call back to get the values from application*/ @@ -1500,7 +1528,7 @@ MOBLE_RESULT Light_HslTarget_Status(MOBLEUINT8* pHslTarget_status, MOBLEUINT32 * */ TRACE_M(TF_LIGHT,"Light_HslTarget_Status callback received \r\n"); - + TRACE_M(TF_SERIAL_CTRL,"#8279! \n\r"); /* Function call back to get the values from application*/ *(pHslTarget_status) = Light_HslStatus.TargetHslLightness16 ; @@ -1565,7 +1593,6 @@ MOBLE_RESULT LightModelServer_GetStatusRequestCb(MOBLE_ADDRESS peer_addr, MOBLEUINT32 dataLength, MOBLEBOOL response) { - TRACE_M(TF_LIGHT,"response status enable \n\r"); switch(opcode) { #ifdef ENABLE_LIGHT_MODEL_SERVER_LIGHTNESS @@ -1674,7 +1701,7 @@ MOBLE_RESULT LightModelServer_GetStatusRequestCb(MOBLE_ADDRESS peer_addr, /** * @brief LightModelServer_ProcessMessageCb: This is a callback function from -the library whenever a Light Model message is received +* the library whenever a Light Model message is received * @param peer_addr: Address of the peer * @param dst_peer: destination send by peer for this node. It can be a * unicast or group address @@ -1711,7 +1738,10 @@ MOBLE_RESULT LightModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, if(result == MOBLE_RESULT_SUCCESS) { - Light_Lightness_Set(pRxData, dataLength); + if(!MOBLE_FAILED(result = Chk_TidValidity(peer_addr,dst_peer,pRxData[2]))) + { + Light_Lightness_Set(pRxData, dataLength); + } } break; } @@ -1722,7 +1752,10 @@ MOBLE_RESULT LightModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, if(result == MOBLE_RESULT_SUCCESS) { - Light_Lightness_Linear_Set(pRxData, dataLength); + if(!MOBLE_FAILED(result = Chk_TidValidity(peer_addr,dst_peer,pRxData[2]))) + { + Light_Lightness_Linear_Set(pRxData, dataLength); + } } break; } @@ -1788,7 +1821,10 @@ MOBLE_RESULT LightModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, if(result == MOBLE_RESULT_SUCCESS) { - Light_Ctl_Set(pRxData, dataLength); + if(!MOBLE_FAILED(result = Chk_TidValidity(peer_addr,dst_peer,pRxData[6]))) + { + Light_Ctl_Set(pRxData, dataLength); + } } break; } @@ -1818,7 +1854,10 @@ MOBLE_RESULT LightModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, if(result == MOBLE_RESULT_SUCCESS) { - Light_CtlTemperature_Set(pRxData, dataLength); + if(!MOBLE_FAILED(result = Chk_TidValidity(peer_addr,dst_peer,pRxData[4]))) + { + Light_CtlTemperature_Set(pRxData, dataLength); + } } break; } @@ -1868,7 +1907,10 @@ MOBLE_RESULT LightModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, if(result == MOBLE_RESULT_SUCCESS) { - Light_Hsl_Set(pRxData, dataLength); + if(!MOBLE_FAILED(result = Chk_TidValidity(peer_addr,dst_peer,pRxData[6]))) + { + Light_Hsl_Set(pRxData, dataLength); + } } break; } @@ -1903,7 +1945,10 @@ MOBLE_RESULT LightModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, if(result == MOBLE_RESULT_SUCCESS) { - Light_HslHue_Set(pRxData, dataLength); + if(!MOBLE_FAILED(result = Chk_TidValidity(peer_addr,dst_peer,pRxData[2]))) + { + Light_HslHue_Set(pRxData, dataLength); + } } break; } @@ -1935,7 +1980,10 @@ MOBLE_RESULT LightModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, case LIGHT_HSL_SATURATION_SET: case LIGHT_HSL_SATURATION_SET_UNACK: { - Light_HslSaturation_Set(pRxData, dataLength); + if(!MOBLE_FAILED(result = Chk_TidValidity(peer_addr,dst_peer,pRxData[2]))) + { + Light_HslSaturation_Set(pRxData, dataLength); + } break; } case LIGHT_HSL_SATURATION_STATUS: @@ -1964,12 +2012,294 @@ MOBLE_RESULT LightModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, return MOBLE_RESULT_SUCCESS; } +/** +* @brief Light_Client_Lightness_Status: Function called when status of the model +* received on the client. +* @param pLightness_status: ointer to the parameters received for message +* @param plength: Length of the parameters received for message +* return MOBLE_RESULT_SUCCESS. +*/ +MOBLE_RESULT Light_Client_Lightness_Status(MOBLEUINT8 const *pLightness_status, MOBLEUINT32 plength) +{ + MOBLEUINT32 i; + + TRACE_M(TF_LIGHT_CLIENT,"Light_Client_Lightness_Status received \r\n"); + LightAppli_cb.Lightness_Status_cb(pLightness_status, plength); + for(i = 0; i < plength; i++) + TRACE_M(TF_SERIAL_CTRL,"Light_Lightness_Status: %d\r\n", + pLightness_status[i]); + return MOBLE_RESULT_SUCCESS; +} + +/** +* @brief Light_Client_Lightness_Linear_Status: Function called when status of the model +* received on the client. +* @param pLightnessLinear_status: ointer to the parameters received for message +* @param plength: Length of the parameters received for message +* return MOBLE_RESULT_SUCCESS. +*/ +MOBLE_RESULT Light_Client_Lightness_Linear_Status(MOBLEUINT8 const *pLightnessLinear_status, MOBLEUINT32 pLength) +{ + MOBLEUINT32 i; + + TRACE_M(TF_LIGHT,"Light_Lightness_Linear_Status received \r\n"); + LightAppli_cb.Lightness_Linear_Status_cb(pLightnessLinear_status, pLength); + for(i = 0; i < pLength; i++) + TRACE_M(TF_SERIAL_CTRL,"Light_Lightness_Linear_Status: %d\r\n", + pLightnessLinear_status[i]); + return MOBLE_RESULT_SUCCESS; +} + +/** +* @brief Light_Client_Lightness_Last_Status: Function called when status of the model +* received on the client. +* @param pLightnessLast_status: ointer to the parameters received for message +* @param plength: Length of the parameters received for message +* return MOBLE_RESULT_SUCCESS. +*/ +MOBLE_RESULT Light_Client_Lightness_Last_Status(MOBLEUINT8 const *pLightnessLast_status, MOBLEUINT32 pLength) +{ + MOBLEUINT32 i; + + TRACE_M(TF_LIGHT,"Light_Lightness_Last_Status received \r\n"); + for(i = 0; i < pLength; i++) + TRACE_M(TF_SERIAL_CTRL,"Light_Lightness_Last_Status: %d\r\n", + pLightnessLast_status[i]); + return MOBLE_RESULT_SUCCESS; +} + +/** +* @brief Light_Client_Lightness_Default_Status: Function called when status of the model +* received on the client. +* @param pLightnessDefault_status: ointer to the parameters received for message +* @param plength: Length of the parameters received for message +* return MOBLE_RESULT_SUCCESS. +*/ +MOBLE_RESULT Light_Client_Lightness_Default_Status(MOBLEUINT8 const *pLightnessDefault_status, MOBLEUINT32 pLength) +{ + MOBLEUINT32 i; + + TRACE_M(TF_LIGHT,"Light_Lightness_Default_Status received \r\n"); + LightAppli_cb.Lightness_Default_Status_cb(pLightnessDefault_status, pLength); + for(i = 0; i < pLength; i++) + TRACE_M(TF_SERIAL_CTRL,"Light_Lightness_Default_Status: %d\r\n", + pLightnessDefault_status[i]); + return MOBLE_RESULT_SUCCESS; +} + +/** +* @brief Light_Client_Lightness_Range_Status: Function called when status of the model +* received on the client. +* @param pLightnessRange_status: ointer to the parameters received for message +* @param plength: Length of the parameters received for message +* return MOBLE_RESULT_SUCCESS. +*/ +MOBLE_RESULT Light_Client_Lightness_Range_Status(MOBLEUINT8 const *pLightnessRange_status, MOBLEUINT32 pLength) +{ + MOBLEUINT32 i; + + TRACE_M(TF_LIGHT,"Light_Lightness_Range_Status received \r\n"); + LightAppli_cb.Lightness_Range_Status_cb(pLightnessRange_status, pLength); + for(i = 0; i < pLength; i++) + TRACE_M(TF_SERIAL_CTRL,"Light_Client_Lightness_Range_Status: %d\r\n", + pLightnessRange_status[i]); + return MOBLE_RESULT_SUCCESS; +} + +/** +* @brief Light_Client_Ctl_Status: Function called when status of the model +* received on the client. +* @param pLightCtl_status: ointer to the parameters received for message +* @param plength: Length of the parameters received for message +* return MOBLE_RESULT_SUCCESS. +*/ +MOBLE_RESULT Light_Client_Ctl_Status(MOBLEUINT8 const *pLightCtl_status, MOBLEUINT32 pLength) +{ + MOBLEUINT32 i; + + TRACE_M(TF_LIGHT,"Light_Ctl_Status received \r\n"); + LightAppli_cb.Light_Ctl_Status_cb(pLightCtl_status, pLength); + for(i = 0; i < pLength; i++) + TRACE_M(TF_SERIAL_CTRL,"Light_Ctl_Status: %d\r\n", + pLightCtl_status[i]); + return MOBLE_RESULT_SUCCESS; +} + +/** +* @brief Light_Client_CtlTemperature_Range_Status: Function called when status of the model +* received on the client. +* @param pCtlTempRange_status: ointer to the parameters received for message +* @param plength: Length of the parameters received for message +* return MOBLE_RESULT_SUCCESS. +*/ +MOBLE_RESULT Light_Client_CtlTemperature_Range_Status(MOBLEUINT8 const *pCtlTempRange_status, MOBLEUINT32 pLength) +{ + MOBLEUINT32 i; + + TRACE_M(TF_LIGHT,"Light_CtlTemperature_Range_Status received \r\n"); + LightAppli_cb.Light_CtlTemperature_Range_Status_cb(pCtlTempRange_status, pLength); + for(i = 0; i < pLength; i++) + TRACE_M(TF_SERIAL_CTRL,"Light_CtlTemperature_Range_Status: %d\r\n", + pCtlTempRange_status[i]); + return MOBLE_RESULT_SUCCESS; +} + +/** +* @brief Light_Client_CtlDefault_Status: Function called when status of the model +* received on the client. +* @param pCtlDefault_status: ointer to the parameters received for message +* @param plength: Length of the parameters received for message +* return MOBLE_RESULT_SUCCESS. +*/ +MOBLE_RESULT Light_Client_CtlDefault_Status(MOBLEUINT8 const *pCtlDefault_status, MOBLEUINT32 pLength) +{ + MOBLEUINT32 i; + + TRACE_M(TF_LIGHT,"Light_Ctl_DefaultStatus received \r\n"); + LightAppli_cb.Light_CtlDefault_Status_cb(pCtlDefault_status, pLength); + for(i = 0; i < pLength; i++) + TRACE_M(TF_SERIAL_CTRL,"Light_Ctl_DefaultStatus: %d\r\n", + pCtlDefault_status[i]); + return MOBLE_RESULT_SUCCESS; +} + +/** +* @brief Light_Client_CtlTemperature_Status: Function called when status of the model +* received on the client. +* @param pLightCtlTemp_status: ointer to the parameters received for message +* @param plength: Length of the parameters received for message +* return MOBLE_RESULT_SUCCESS. +*/ +MOBLE_RESULT Light_Client_CtlTemperature_Status(MOBLEUINT8 const *pLightCtlTemp_status, MOBLEUINT32 pLength) +{ + MOBLEUINT32 i; + + TRACE_M(TF_LIGHT,"Light_CtlTemperature_Status received \r\n"); + LightAppli_cb.Light_CtlTemperature_Status_cb(pLightCtlTemp_status, pLength); + for(i = 0; i < pLength; i++) + TRACE_M(TF_SERIAL_CTRL,"Light_CtlTemperature_Status: %d\r\n", + pLightCtlTemp_status[i]); + return MOBLE_RESULT_SUCCESS; +} + +/** +* @brief Light_Client_Hsl_Status: Function called when status of the model +* received on the client. +* @param pHsl_status: ointer to the parameters received for message +* @param plength: Length of the parameters received for message +* return MOBLE_RESULT_SUCCESS. +*/ +MOBLE_RESULT Light_Client_Hsl_Status(MOBLEUINT8 const *pHsl_status, MOBLEUINT32 pLength) +{ + MOBLEUINT32 i; + + TRACE_M(TF_LIGHT,"Light_Hsl_Status received \r\n"); + LightAppli_cb.Light_Hsl_Status_cb(pHsl_status, pLength); + for(i = 0; i < pLength; i++) + TRACE_M(TF_SERIAL_CTRL,"Light_Hsl_Status: %d\r\n", + pHsl_status[i]); + return MOBLE_RESULT_SUCCESS; +} + +/** +* @brief Light_Client_HslDefault_Status: Function called when status of the model +* received on the client. +* @param pHslDefault_status: ointer to the parameters received for message +* @param plength: Length of the parameters received for message +* return MOBLE_RESULT_SUCCESS. +*/ +MOBLE_RESULT Light_Client_HslDefault_Status(MOBLEUINT8 const *pHslDefault_status, MOBLEUINT32 pLength) +{ + MOBLEUINT32 i; + + TRACE_M(TF_LIGHT,"Light_HslDefault_Status received \r\n"); + LightAppli_cb.Light_HslDefault_Status_cb(pHslDefault_status, pLength); + for(i = 0; i < pLength; i++) + TRACE_M(TF_SERIAL_CTRL,"Light_HslDefault_Status: %d\r\n", + pHslDefault_status[i]); + return MOBLE_RESULT_SUCCESS; +} + +/** +* @brief Light_Client_HslRange_Status: Function called when status of the model +* received on the client. +* @param pHslRange_status: ointer to the parameters received for message +* @param plength: Length of the parameters received for message +* return MOBLE_RESULT_SUCCESS. +*/ +MOBLE_RESULT Light_Client_HslRange_Status(MOBLEUINT8 const *pHslRange_status, MOBLEUINT32 pLength) +{ + MOBLEUINT32 i; + + TRACE_M(TF_LIGHT,"Light_HslRange_Status received \r\n"); + LightAppli_cb.Light_HslRange_Status_cb(pHslRange_status, pLength); + for(i = 0; i < pLength; i++) + TRACE_M(TF_SERIAL_CTRL,"Light_HslRange_Status: %d\r\n", + pHslRange_status[i]); + return MOBLE_RESULT_SUCCESS; +} + +/** +* @brief Light_Client_HslTarget_Status: Function called when status of the model +* received on the client. +* @param pHslTarget_status: ointer to the parameters received for message +* @param plength: Length of the parameters received for message +* return MOBLE_RESULT_SUCCESS. +*/ +MOBLE_RESULT Light_Client_HslTarget_Status(MOBLEUINT8 const *pHslTarget_status, MOBLEUINT32 pLength) +{ + MOBLEUINT32 i; + + TRACE_M(TF_LIGHT,"Light_HslTarget_Status received \r\n"); + for(i = 0; i < pLength; i++) + TRACE_M(TF_SERIAL_CTRL,"Light_HslTarget_Status: %d\r\n", + pHslTarget_status[i]); + return MOBLE_RESULT_SUCCESS; +} + +/** +* @brief Light_Client_HslHue_Status: Function called when status of the model +* received on the client. +* @param pHslHue_status: ointer to the parameters received for message +* @param plength: Length of the parameters received for message +* return MOBLE_RESULT_SUCCESS. +*/ +MOBLE_RESULT Light_Client_HslHue_Status(MOBLEUINT8 const *pHslHue_status, MOBLEUINT32 pLength) +{ + MOBLEUINT32 i; + + TRACE_M(TF_LIGHT,"Light_HslHue_Status received \r\n"); + LightAppli_cb.Light_HslHue_Status_cb(pHslHue_status, pLength); + for(i = 0; i < pLength; i++) + TRACE_M(TF_SERIAL_CTRL,"Light_HslHue_Status: %d\r\n", + pHslHue_status[i]); + return MOBLE_RESULT_SUCCESS; +} + +/** +* @brief Light_Client_HslSaturation_Status: Function called when status of the model +* received on the client. +* @param pHslSaturation_status: ointer to the parameters received for message +* @param plength: Length of the parameters received for message +* return MOBLE_RESULT_SUCCESS. +*/ +MOBLE_RESULT Light_Client_HslSaturation_Status(MOBLEUINT8 const *pHslSaturation_status, MOBLEUINT32 pLength) +{ + MOBLEUINT32 i; + + TRACE_M(TF_LIGHT,"Light_HslSaturation_Status received \r\n"); + LightAppli_cb.Light_HslSaturation_Status_cb(pHslSaturation_status, pLength); + for(i = 0; i < pLength; i++) + TRACE_M(TF_SERIAL_CTRL,"Light_HslSaturation_Status: %d\r\n", + pHslSaturation_status[i]); + return MOBLE_RESULT_SUCCESS; +} -/* -* @Brief Light_TransitionBehaviourSingle_Param funtion is used for the Light Lightness model +/** +* @brief Light_TransitionBehaviourSingle_Param funtion is used for the Light Lightness model * when transition time is received in message.This function is used for * single paramter transition. -* @param GetValue Pointer of the array +* @param GetValue: Pointer of the array * @retval MOBLE_RESULT */ MOBLE_RESULT Light_TransitionBehaviourSingle_Param(MOBLEUINT8 *GetValue) @@ -2043,11 +2373,11 @@ MOBLE_RESULT Light_TransitionBehaviourSingle_Param(MOBLEUINT8 *GetValue) } -/* -* @Brief Light_TransitionBehaviourMulti_Param funtion is used for the Light Lightness model +/** +* @brief Light_TransitionBehaviourMulti_Param funtion is used for the Light Lightness model * when transition time is received in message.This function is used for * the multiple parameters in transition. -* @param GetValue Pointer of the array +* @param GetValue: Pointer of the array * @param * @retval MOBLE_RESULT */ @@ -2161,8 +2491,8 @@ MOBLE_RESULT Light_TransitionBehaviourMulti_Param(MOBLEUINT8 *GetValue , MOBLEUI } -/* -* @Brief Light_GetStepValue:Function calculates parameters for transition time +/** +* @brief Light_GetStepValue:Function calculates parameters for transition time * for light model. * @param stepParam is transition time set value. * retval void. @@ -2298,8 +2628,8 @@ void Lighting_Process(void) } -/* -* @Brief LightLightnessStateUpdate_Process:Function to update the parametes of light +/** +* @brief LightLightnessStateUpdate_Process:Function to update the parametes of light * lightness model in application file from Temporary parameter in model file. * @param void * return MOBLE_RESULT. @@ -2313,8 +2643,8 @@ MOBLE_RESULT LightLightnessStateUpdate_Process(void) } -/* -* @Brief LightLinearStateUpdate_Process:function to update the parametes of light +/** +* @brief LightLinearStateUpdate_Process:function to update the parametes of light * lightness linear model in application file from Temporary parameter in model file. * @param void * return MOBLE_RESULT. @@ -2328,8 +2658,8 @@ MOBLE_RESULT LightLinearStateUpdate_Process(void) } -/* -* @Brief LightCtlStateUpdate_Process:Function to update the parametes of light +/** +* @brief LightCtlStateUpdate_Process:Function to update the parametes of light * CTL model in application file from Temporary parameter in model file. * @param void * return MOBLE_RESULT. @@ -2344,8 +2674,8 @@ MOBLE_RESULT LightCtlStateUpdate_Process(void) } -/* -* @Brief LightCtlTemperatureStateUpdate_Process:Function to update the parametes of +/** +* @brief LightCtlTemperatureStateUpdate_Process:Function to update the parametes of * light CTL Temperature model in application file from Temporary parameter in model file. * @param void * return MOBLE_RESULT. @@ -2359,8 +2689,8 @@ MOBLE_RESULT LightCtlTemperatureStateUpdate_Process(void) } -/* -* @Brief LightHslStateUpdate_Process:Function to update the parametes of +/** +* @brief LightHslStateUpdate_Process:Function to update the parametes of * light HSL model in application file from Temporary parameter in model file. * @param void * return MOBLE_RESULT. @@ -2375,8 +2705,8 @@ MOBLE_RESULT LightHslStateUpdate_Process(void) } -/* -* @Brief LightHslHueStateUpdate_Process:Function to update the parametes of +/** +* @brief LightHslHueStateUpdate_Process:Function to update the parametes of * light HSL Hue model in application file from Temporary parameter in model file. * @param void * return MOBLE_RESULT. @@ -2389,8 +2719,8 @@ MOBLE_RESULT LightHslHueStateUpdate_Process(void) } -/* -* @Brief LightHslSaturationStateUpdate_Process:Function to update the parametes of +/** +* @brief LightHslSaturationStateUpdate_Process:Function to update the parametes of * light HSL Saturation model in application file from Temporary parameter in model file. * @param void * return MOBLE_RESULT. @@ -2403,10 +2733,10 @@ MOBLE_RESULT LightHslSaturationStateUpdate_Process(void) } -/* -* @Brief Light_BindingCtlToLightness_Actual:Function for binding the data of actual +/** +* @brief Light_BindingCtlToLightness_Actual:Function for binding the data of actual * lightness and light Ctl set. -* @param bindingFlag +* @param bindingFlag: value pass to function from light lightness * return void */ void Light_BindingCtlToLightness_Actual(MOBLEUINT8 bindingFlag) @@ -2424,11 +2754,11 @@ void Light_BindingCtlToLightness_Actual(MOBLEUINT8 bindingFlag) } -/* -* @Brief LightActual_GenericOnOffBinding: Reverse Data binding b/w Generic On Off and +/** +* @brief LightActual_GenericOnOffBinding: Reverse Data binding b/w Generic On Off and * light lightness Actual. this function will set the On Off status of * Light when the light lightness Actual is set. -* @param lightActual used to select the binding and reverse binding +* @param lightActual: used to select the binding and reverse binding * return void. */ void LightActual_GenericOnOffBinding(Light_LightnessParam_t* lightActual) @@ -2456,11 +2786,11 @@ void LightActual_GenericOnOffBinding(Light_LightnessParam_t* lightActual) } -/* -* @Brief LightActual_GenericLevelBinding: Data binding b/w Generic Level and +/** +* @brief LightActual_GenericLevelBinding: Data binding b/w Generic Level and * light lightness Actual. this function will set the actual light lightness * value at the time of generic Level set. -* @param lightActual Pointer to the data which needs to be checked. +* @param lightActual: Pointer to the data which needs to be checked. * return void. */ void LightActual_GenericLevelBinding(Light_LightnessParam_t* lightActual) @@ -2476,7 +2806,7 @@ void LightActual_GenericLevelBinding(Light_LightnessParam_t* lightActual) Generic_LevelStatus_t bGeneric_LevelParam ; elementNumber = BLE_GetElementNumber(); - publishAddress = BLEMesh_GetPublishAddress(elementNumber); + publishAddress = BLEMesh_GetPublishAddress(elementNumber, GENERIC_MODEL_SERVER_LEVEL_MODEL_ID); bGeneric_LevelParam.Present_Level16 = lightActual->TargetLightnessStatus - 32768; (GenericAppli_cb.Level_Set_cb)(&bGeneric_LevelParam, 0); @@ -2486,10 +2816,11 @@ void LightActual_GenericLevelBinding(Light_LightnessParam_t* lightActual) } -/* -* @Brief Light_Linear_ActualImplicitBinding:Function for binding the data of actual +/** +* @brief Light_Linear_ActualImplicitBinding:Function for binding the data of actual lightness and Linear Lightness is implicit binding with generic on off state. -* @param bindingFlag +* @param bindingFlag: flag value passed in function +* @param length:length of data * return void */ void Light_Linear_ActualImplicitBinding(MOBLEUINT8 bindingFlag ,MOBLEUINT32 length) @@ -2503,7 +2834,7 @@ void Light_Linear_ActualImplicitBinding(MOBLEUINT8 bindingFlag ,MOBLEUINT32 leng Light_LightnessParam_t bLightnessActual; elementNumber = BLE_GetElementNumber(); - publishAddress = BLEMesh_GetPublishAddress(elementNumber); + publishAddress = BLEMesh_GetPublishAddress(elementNumber, LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID); if(bindingFlag == BINDING_LIGHT_LIGHTNESS_LINEAR_SET) @@ -2540,8 +2871,8 @@ void Light_Linear_ActualImplicitBinding(MOBLEUINT8 bindingFlag ,MOBLEUINT32 leng } -/*Light_Actual_LinearBinding -* @Brief Light_Actual_LinearBinding:Light_Actual_LinearBinding:Function used for +/** +* @brief Light_Actual_LinearBinding:Light_Actual_LinearBinding:Function used for * binding the data of actual lightness and lineaer lightness.this function * changes the value of linear lightness as actual lightness value is set. * @param void @@ -2566,11 +2897,11 @@ MOBLEUINT16 Light_Actual_LinearBinding(void) } -/* -* @Brief Light_Linear_ActualBinding:Function used for binding the data of actual +/** +* @brief Light_Linear_ActualBinding:Function used for binding the data of actual * lightness and linear lightness. this function changes the value of Actual * lightness as Linear lightness value is set. -* @param void +* @param length: length of the data * return MOBLEUINT16 */ MOBLEUINT16 Light_Linear_ActualBinding(MOBLEUINT32 length) @@ -2597,8 +2928,8 @@ MOBLEUINT16 Light_Linear_ActualBinding(MOBLEUINT32 length) } -/* -* @Brief Light_Actual_RangeBinding:Function used for binding the data of actual +/** +* @brief Light_Actual_RangeBinding:Function used for binding the data of actual * lightness and lightness range this function set the value of Actual * lightness according to the min range and max range value. * @param lightActual: Pointer which needs to be set. @@ -2636,8 +2967,8 @@ void Light_Actual_RangeBinding(Light_LightnessParam_t* lightActual) } -/*Light_CtlTemperature_TempRangeBinding -* @Brief Light_CtlTemperature_TempRangeBinding: Function used for binding the data of +/** +* @brief Light_CtlTemperature_TempRangeBinding: Function used for binding the data of * Ctl temperature and Ctl temperature range this function changes the value of * Ctl temperature according to the min range and max range value. * @param ctlTempemerature: Pointer which needs to be set. @@ -2673,8 +3004,8 @@ void Light_CtlTemperature_TempRangeBinding(Light_CtlParam_t* ctlTemperature) } -/* -* @Brief Light_CtlTemp_GenericLevelBinding: Data binding b/w Generic Level and +/** +* @brief Light_CtlTemp_GenericLevelBinding: Data binding b/w Generic Level and * light Ctl temperature . this function will set the generic Level * value at the time of Ctl temperature value set. * @param bCtlTempParam: Pointer to the data which needs to be checked. @@ -2697,8 +3028,8 @@ void Light_CtlTemp_GenericLevelBinding(Light_CtlParam_t* bCtlTempParam) } -/* -* @Brief Light_HslHue_GenericLevelBinding: Data binding b/w Generic Level and +/** +* @brief Light_HslHue_GenericLevelBinding: Data binding b/w Generic Level and * light Hsl . this function will set the Generic Level * value at the time of Hsl Hue value set. * @param bHslHueParam: Pointer to the data which needs to be checked. @@ -2716,8 +3047,8 @@ void Light_HslHue_GenericLevelBinding(Light_HslParam_t* bHslHueParam) } -/*Light_HslHue_RangeBinding -* @Brief Light_HslHue_RangeBinding: Function used for binding the data of +/** +* @brief Light_HslHue_RangeBinding: Function used for binding the data of * Hsl Hue value and Hsl Hue range. this function changes the value of * Hsl Hue according to the min range and max range value. * @param bHslHueParam: Pointer which needs to be set. @@ -2752,8 +3083,8 @@ void Light_HslHue_RangeBinding(Light_HslParam_t* bHslHueParam) } -/* -* @Brief Light_HslSaturation_GenericLevelBinding: Data binding b/w Generic Level and +/** +* @brief Light_HslSaturation_GenericLevelBinding: Data binding b/w Generic Level and * light Hsl . this function will set the Generic Level * value at the time of Hsl Saturation value set. * @param bHslSatParam: Pointer to the data which needs to be checked. @@ -2771,8 +3102,8 @@ void Light_HslSaturation_GenericLevelBinding(Light_HslParam_t* bHslSatParam) } -/*Light_HslSaturation_RangeBinding -* @Brief Light_HslSaturation_RangeBinding: Function used for binding the data of +/** +* @brief Light_HslSaturation_RangeBinding: Function used for binding the data of * Hsl saturation value and Hsl saturation range. this function changes the value of * Hsl saturation according to the min range and max range value. * @param bHslSatParam: Pointer which needs to be set. @@ -2807,8 +3138,8 @@ void Light_HslSaturation_RangeBinding(Light_HslParam_t* bHslSatParam) } -/* -* @Brief Light_HslLightness_LightnessActualBinding: Data binding b/w Hsl lightness and +/** +* @brief Light_HslLightness_LightnessActualBinding: Data binding b/w Hsl lightness and * Lightness Atual . this function will set the Lightness Actual * value at the time of Hsl Lightness value set. * @param bHslLightParam: Pointer to the data which needs to be checked. @@ -2827,8 +3158,8 @@ void Light_HslLightness_LightnessActualBinding(Light_HslParam_t* bHslLightParam) } -/* -* @Brief Light_ActualLightness_HslLightnessBinding: Data binding b/w Actual Lightness and +/** +* @brief Light_ActualLightness_HslLightnessBinding: Data binding b/w Actual Lightness and * Hsl lightness . this function will set the Hsl Lightness value * at the time of Lightness Actual value set. * @param bActualLightParam: Pointer to the data which needs to be checked. @@ -2845,9 +3176,9 @@ void Light_ActualLightness_HslLightnessBinding(Light_LightnessParam_t* bActualLi (LightAppli_cb.Light_Hsl_Set_cb)(&bHslLightStatus , 0); } -/* +/** * @brief function called in Light lightness when the default transition time is enabled. -* @param void. +* @param pLightnessValue: pointer to the function * return void. */ void Light_LightnessDefaultTransitionValue(Light_LightnessParam_t* pLightnessValue) @@ -2859,9 +3190,9 @@ void Light_LightnessDefaultTransitionValue(Light_LightnessParam_t* pLightnessVal Light_ModelFlag.LightOptionalParam = 1; } -/* +/** * @brief function called in Light CTL set when the default transition time is enabled. -* @param void. +* @param pCTLValue: pointer to the function * return void. */ void Light_CTLDefaultTransitionValue(Light_CtlParam_t* pCTLValue) @@ -2873,9 +3204,9 @@ void Light_CTLDefaultTransitionValue(Light_CtlParam_t* pCTLValue) Light_ModelFlag.LightOptionalParam = 1; } -/* +/** * @brief function called in Light CTL temperature set when the default transition time is enabled. -* @param void. +* @param pCTLValue:pointer to the function * return void. */ void Light_CTLTemperatureDefaultTransitionValue(Light_CtlParam_t* pCTLValue) @@ -2887,357 +3218,103 @@ void Light_CTLTemperatureDefaultTransitionValue(Light_CtlParam_t* pCTLValue) Light_ModelFlag.LightOptionalParam = 1; } -/* -* @brief Light_Client_Lightness_Status: Function called when status of the model - received on the client. -* @param pLightness_status: ointer to the parameters received for message -* @param plength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Light_Client_Lightness_Status(MOBLEUINT8 const *pLightness_status, MOBLEUINT32 pLength) -{ - MOBLEUINT32 i; - - TRACE_M(TF_LIGHT,"Light_Lightness_Status callback received \r\n"); - for(i = 0; i < pLength; i++) - TRACE_M(TF_SERIAL_CTRL,"Light_Lightness_Status: %d\r\n", - pLightness_status[i]); - return MOBLE_RESULT_SUCCESS; -} - -/* -* @brief Light_Client_Lightness_Linear_Status: Function called when status of the model - received on the client. -* @param pLightnessLinear_status: ointer to the parameters received for message -* @param pLength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Light_Client_Lightness_Linear_Status(MOBLEUINT8 const *pLightnessLinear_status, MOBLEUINT32 pLength) -{ - MOBLEUINT32 i; - - TRACE_M(TF_LIGHT,"Light_Lightness_Linear_Status callback received \r\n"); - for(i = 0; i < pLength; i++) - TRACE_M(TF_SERIAL_CTRL,"Light_Lightness_Linear_Status: %d\r\n", - pLightnessLinear_status[i]); - return MOBLE_RESULT_SUCCESS; -} - -/* -* @brief Light_Client_Lightness_Last_Status: Function called when status of the model - received on the client. -* @param pLightnessLast_status: ointer to the parameters received for message -* @param pLength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Light_Client_Lightness_Last_Status(MOBLEUINT8 const *pLightnessLast_status, MOBLEUINT32 pLength) -{ - MOBLEUINT32 i; - - TRACE_M(TF_LIGHT,"Light_Lightness_Last_Status callback received \r\n"); - for(i = 0; i < pLength; i++) - TRACE_M(TF_SERIAL_CTRL,"Light_Lightness_Last_Status: %d\r\n", - pLightnessLast_status[i]); - return MOBLE_RESULT_SUCCESS; -} - -/* -* @brief Light_Client_Lightness_Default_Status: Function called when status of the model - received on the client. -* @param pLightnessDefault_status: ointer to the parameters received for message -* @param pLength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Light_Client_Lightness_Default_Status(MOBLEUINT8 const *pLightnessDefault_status, MOBLEUINT32 pLength) -{ - MOBLEUINT32 i; - - TRACE_M(TF_LIGHT,"Light_Lightness_Default_Status callback received \r\n"); - for(i = 0; i < pLength; i++) - TRACE_M(TF_SERIAL_CTRL,"Light_Lightness_Default_Status: %d\r\n", - pLightnessDefault_status[i]); - return MOBLE_RESULT_SUCCESS; -} - -/* -* @brief Light_Client_Lightness_Range_Status: Function called when status of the model - received on the client. -* @param pLightnessRange_status: ointer to the parameters received for message -* @param pLength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Light_Client_Lightness_Range_Status(MOBLEUINT8 const *pLightnessRange_status, MOBLEUINT32 pLength) -{ - MOBLEUINT32 i; - - TRACE_M(TF_LIGHT,"Light_Client_Lightness_Range_Status callback received \r\n"); - for(i = 0; i < pLength; i++) - TRACE_M(TF_SERIAL_CTRL,"Light_Client_Lightness_Range_Status: %d\r\n", - pLightnessRange_status[i]); - return MOBLE_RESULT_SUCCESS; -} - -/* -* @brief Light_Client_Ctl_Status: Function called when status of the model - received on the client. -* @param pLightCtl_status: ointer to the parameters received for message -* @param pLength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Light_Client_Ctl_Status(MOBLEUINT8 const *pLightCtl_status, MOBLEUINT32 pLength) -{ - MOBLEUINT32 i; - - TRACE_M(TF_LIGHT,"Light_Ctl_Status callback received \r\n"); - for(i = 0; i < pLength; i++) - TRACE_M(TF_SERIAL_CTRL,"Light_Ctl_Status: %d\r\n", - pLightCtl_status[i]); - return MOBLE_RESULT_SUCCESS; -} - -/* -* @brief Light_Client_CtlTemperature_Range_Status: Function called when status of the model - received on the client. -* @param pCtlTempRange_status: ointer to the parameters received for message -* @param pLength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Light_Client_CtlTemperature_Range_Status(MOBLEUINT8 const *pCtlTempRange_status, MOBLEUINT32 pLength) -{ - MOBLEUINT32 i; - - TRACE_M(TF_LIGHT,"Light_CtlTemperature_Range_Status callback received \r\n"); - for(i = 0; i < pLength; i++) - TRACE_M(TF_SERIAL_CTRL,"Light_CtlTemperature_Range_Status: %d\r\n", - pCtlTempRange_status[i]); - return MOBLE_RESULT_SUCCESS; -} - -/* -* @brief Light_Client_CtlDefault_Status: Function called when status of the model - received on the client. -* @param pCtlDefault_status: ointer to the parameters received for message -* @param pLength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Light_Client_CtlDefault_Status(MOBLEUINT8 const *pCtlDefault_status, MOBLEUINT32 pLength) -{ - MOBLEUINT32 i; - - TRACE_M(TF_LIGHT,"Light_Ctl_DefaultStatus callback received \r\n"); - for(i = 0; i < pLength; i++) - TRACE_M(TF_SERIAL_CTRL,"Light_Ctl_DefaultStatus: %d\r\n", - pCtlDefault_status[i]); - return MOBLE_RESULT_SUCCESS; -} - -/* -* @brief Light_Client_CtlTemperature_Status: Function called when status of the model - received on the client. -* @param pLightCtlTemp_status: ointer to the parameters received for message -* @param pLength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Light_Client_CtlTemperature_Status(MOBLEUINT8 const *pLightCtlTemp_status, MOBLEUINT32 pLength) -{ - MOBLEUINT32 i; - - TRACE_M(TF_LIGHT,"Light_CtlTemperature_Status callback received \r\n"); - for(i = 0; i < pLength; i++) - TRACE_M(TF_SERIAL_CTRL,"Light_CtlTemperature_Status: %d\r\n", - pLightCtlTemp_status[i]); - return MOBLE_RESULT_SUCCESS; -} - -/* -* @brief Light_Client_Hsl_Status: Function called when status of the model - received on the client. -* @param pHsl_status: ointer to the parameters received for message -* @param pLength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Light_Client_Hsl_Status(MOBLEUINT8 const *pHsl_status, MOBLEUINT32 pLength) -{ - MOBLEUINT32 i; - - TRACE_M(TF_LIGHT,"Light_Hsl_Status callback received \r\n"); - for(i = 0; i < pLength; i++) - TRACE_M(TF_SERIAL_CTRL,"Light_Hsl_Status: %d\r\n", - pHsl_status[i]); - return MOBLE_RESULT_SUCCESS; -} - -/* -* @brief Light_Client_HslDefault_Status: Function called when status of the model - received on the client. -* @param pHslDefault_status: ointer to the parameters received for message -* @param pLength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Light_Client_HslDefault_Status(MOBLEUINT8 const *pHslDefault_status, MOBLEUINT32 pLength) -{ - MOBLEUINT32 i; - - TRACE_M(TF_LIGHT,"Light_HslDefault_Status callback received \r\n"); - for(i = 0; i < pLength; i++) - TRACE_M(TF_SERIAL_CTRL,"Light_HslDefault_Status: %d\r\n", - pHslDefault_status[i]); - return MOBLE_RESULT_SUCCESS; -} - -/* -* @brief Light_Client_HslRange_Status: Function called when status of the model - received on the client. -* @param pHslRange_status: ointer to the parameters received for message -* @param pLength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Light_Client_HslRange_Status(MOBLEUINT8 const *pHslRange_status, MOBLEUINT32 pLength) -{ - MOBLEUINT32 i; - - TRACE_M(TF_LIGHT,"Light_HslRange_Status callback received \r\n"); - for(i = 0; i < pLength; i++) - TRACE_M(TF_SERIAL_CTRL,"Light_HslRange_Status: %d\r\n", - pHslRange_status[i]); - return MOBLE_RESULT_SUCCESS; -} - -/* -* @brief Light_Client_HslTarget_Status: Function called when status of the model - received on the client. -* @param pHslTarget_status: ointer to the parameters received for message -* @param pLength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Light_Client_HslTarget_Status(MOBLEUINT8 const *pHslTarget_status, MOBLEUINT32 pLength) -{ - MOBLEUINT32 i; - - TRACE_M(TF_LIGHT,"Light_HslTarget_Status callback received \r\n"); - for(i = 0; i < pLength; i++) - TRACE_M(TF_SERIAL_CTRL,"Light_HslTarget_Status: %d\r\n", - pHslTarget_status[i]); - return MOBLE_RESULT_SUCCESS; -} - -/* -* @brief Light_Client_HslHue_Status: Function called when status of the model - received on the client. -* @param pHslHue_status: ointer to the parameters received for message -* @param pLength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Light_Client_HslHue_Status(MOBLEUINT8 const *pHslHue_status, MOBLEUINT32 pLength) -{ - MOBLEUINT32 i; - - TRACE_M(TF_LIGHT,"Light_HslHue_Status callback received \r\n"); - for(i = 0; i < pLength; i++) - TRACE_M(TF_SERIAL_CTRL,"Light_HslHue_Status: %d\r\n", - pHslHue_status[i]); - return MOBLE_RESULT_SUCCESS; -} - -/* -* @brief Light_Client_HslSaturation_Status: Function called when status of the model - received on the client. -* @param pHslSaturation_status: ointer to the parameters received for message -* @param pLength: Length of the parameters received for message -* return MOBLE_RESULT_SUCCESS. -*/ -MOBLE_RESULT Light_Client_HslSaturation_Status(MOBLEUINT8 const *pHslSaturation_status, MOBLEUINT32 pLength) -{ - MOBLEUINT32 i; - - TRACE_M(TF_LIGHT,"Light_HslSaturation_Status callback received \r\n"); - for(i = 0; i < pLength; i++) - TRACE_M(TF_SERIAL_CTRL,"Light_HslSaturation_Status: %d\r\n", - pHslSaturation_status[i]); - return MOBLE_RESULT_SUCCESS; -} - -/* Weak function are defined to support the original function if they are not +/** +Weak function are defined to support the original function if they are not included in firmware. There is no use of this function for application development purpose. */ WEAK_FUNCTION (MOBLE_RESULT Appli_Light_Lightness_Set(Light_LightnessStatus_t* pLight_LightnessParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} WEAK_FUNCTION(MOBLE_RESULT Appli_Light_Lightness_Linear_Set(Light_LightnessStatus_t* pLight_LightnessLinearParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} WEAK_FUNCTION(MOBLE_RESULT Appli_Light_Lightness_Default_Set(Light_LightnessDefaultParam_t* pLight_LightnessDefaultParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} WEAK_FUNCTION(MOBLE_RESULT Appli_Light_Lightness_Range_Set(Light_LightnessRangeParam_t* pLight_LightnessRangeParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} WEAK_FUNCTION(MOBLE_RESULT Appli_Light_Ctl_Set(Light_CtlStatus_t* pLight_CtlParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} WEAK_FUNCTION(MOBLE_RESULT Appli_Light_CtlTemperature_Set(Light_CtlStatus_t* pLight_CtltempParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} WEAK_FUNCTION(MOBLE_RESULT Appli_Light_CtlTemperature_Range_Set(Light_CtlTemperatureRangeParam_t* pLight_CtlTempRangeParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} WEAK_FUNCTION(MOBLE_RESULT Appli_Light_CtlDefault_Set(Light_CtlDefaultParam_t* pLight_CtlDefaultParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} WEAK_FUNCTION(MOBLE_RESULT Appli_Light_Hsl_Set(Light_HslStatus_t* pLight_HslParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} WEAK_FUNCTION(MOBLE_RESULT Appli_Light_HslHue_Set(Light_HslStatus_t* pLight_HslHueParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} WEAK_FUNCTION(MOBLE_RESULT Appli_Light_HslSaturation_Set(Light_HslStatus_t* pLight_HslSaturationParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} WEAK_FUNCTION(MOBLE_RESULT Appli_Light_HslDefault_Set(Light_HslStatus_t* pLight_HslDefaultParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} WEAK_FUNCTION(MOBLE_RESULT Appli_Light_HslRange_Set(Light_HslRangeParam_t* pLight_HslRangeParam, MOBLEUINT8 OptionalValid)) -{ - return MOBLE_RESULT_SUCCESS; -} +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_Lightness_Status(MOBLEUINT8 const *pLightness_status, MOBLEUINT32 pLength)) +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_Lightness_Linear_Status(MOBLEUINT8 const *pLightnessLinear_status, MOBLEUINT32 pLength)) +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_Lightness_Default_Status(MOBLEUINT8 const *pLightnessDefault_status, MOBLEUINT32 pLength)) +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_Lightness_Range_Status(MOBLEUINT8 const *pLightnessRange_status, MOBLEUINT32 pLength)) +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_Ctl_Status(MOBLEUINT8 const *pLightCtl_status, MOBLEUINT32 pLength)) +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_CtlTemperature_Status(MOBLEUINT8 const *pLightCtlTemp_status, MOBLEUINT32 pLength)) +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_CtlTemperature_Range_Status(MOBLEUINT8 const *pCtlTempRange_status, MOBLEUINT32 pLength)) +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_CtlDefault_Status(MOBLEUINT8 const *pCtlDefault_status, MOBLEUINT32 pLength)) +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_Hsl_Status(MOBLEUINT8 const *pHsl_status, MOBLEUINT32 pLength)) +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_HslHue_Status(MOBLEUINT8 const *pHslHue_status, MOBLEUINT32 pLength)) +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_HslSaturation_Status(MOBLEUINT8 const *pHslSaturation_status, MOBLEUINT32 pLength)) +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_HslDefault_Status(MOBLEUINT8 const *pHslDefault_status, MOBLEUINT32 pLength)) +{ return MOBLE_RESULT_SUCCESS;} + +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_HslRange_Status(MOBLEUINT8 const *pHslRange_status, MOBLEUINT32 pLength)) +{ return MOBLE_RESULT_SUCCESS;} + + WEAK_FUNCTION(MOBLE_RESULT Appli_Light_GetLightnessStatus(MOBLEUINT8* lLightnessState)) { return MOBLE_RESULT_SUCCESS; } @@ -3265,6 +3342,8 @@ WEAK_FUNCTION(MOBLE_RESULT Appli_Light_GetHslHueRange(MOBLEUINT8* lHslHueRange)) { return MOBLE_RESULT_SUCCESS; } WEAK_FUNCTION(MOBLE_RESULT Appli_Light_GetHslSatRange(MOBLEUINT8* lHslSatRange)) { return MOBLE_RESULT_SUCCESS; } +WEAK_FUNCTION(MOBLE_RESULT Appli_Light_GetHslDefaultStatus(MOBLEUINT8* lHslDefaultState)) +{ return MOBLE_RESULT_SUCCESS; } WEAK_FUNCTION(void HSL2RGB_Conversion(void)); WEAK_FUNCTION(void RgbF_Create(MOBLEUINT16 value1, MOBLEUINT16 value2, MOBLEUINT16 value3)); WEAK_FUNCTION(void Light_UpdatePWMValue(MOBLEUINT8 state)); diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/light_client.c b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/light_client.c new file mode 100644 index 000000000..864098ae2 --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/light_client.c @@ -0,0 +1,231 @@ +/** +****************************************************************************** +* @file light_client.c +* @author BLE Mesh Team +* @version V1.12.000 +* @date 06-12-2019 +* @brief Generic model client middleware file +****************************************************************************** +* @attention +* +*

    © COPYRIGHT(c) 2017 STMicroelectronics

    +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* Initial BLE-Mesh is built over Motorolas Mesh over Bluetooth Low Energy +* (MoBLE) technology. The present solution is developed and maintained for both +* Mesh library and Applications solely by STMicroelectronics. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ +#include "hal_common.h" +#include "mesh_cfg.h" +#include "light.h" +#include "light_client.h" +#include "common.h" +#include "models_if.h" +#include +#include "compiler.h" + +/** @addtogroup MODEL_CLIENT_LIGHT +* @{ +*/ + +/** @addtogroup Light_Model_Client_Callbacks +* @{ +*/ + +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ + +/* Private variables ---------------------------------------------------------*/ +extern MOBLEUINT8 TidSend; +const MODEL_OpcodeTableParam_t Light_Client_Opcodes_Table[] = { + /* Light Lightness Client */ + /* MOBLEUINT32 opcode, MOBLEBOOL reliable, MOBLEUINT16 min_payload_size, + MOBLEUINT16 max_payload_size; + Here in this array, Handler is not defined; */ +#ifdef ENABLE_LIGHT_MODEL_CLIENT_LIGHTNESS + {LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID ,LIGHT_LIGHTNESS_STATUS, MOBLE_FALSE, 2, 5, 0, 2, 5}, +#endif + {0} +}; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** +* @brief LightClient_Lightness_Set_Unack: This function is called for Acknowledged message +* @param element_number: number for the element present on the node +* @param pLightness_param: pointer ot the function +* @param length:length of the data received +* @retval MOBLE_RESULT +*/ +MOBLE_RESULT LightClient_Lightness_Set_Unack(MOBLE_ADDRESS element_number, + _Light_LightnessParam *pLightness_param, + MOBLEUINT32 length) + +{ + + MOBLE_RESULT result = MOBLE_RESULT_SUCCESS; + MOBLEUINT8 const *msg_buff; + MOBLEUINT16 msg_opcode; + MOBLEBOOL ack_flag; + + TRACE_M(TF_LIGHT_CLIENT,"Light_Lightness_Set_Unack Client Message \r\n"); + pLightness_param->a_Lightness_param[2] = TidSend; + msg_buff = pLightness_param->a_Lightness_param; + ack_flag = MOBLE_FALSE; + msg_opcode = LIGHT_LIGHTNESS_SET_UNACK; + + /* + Manage the TID Here.... + */ + result = MeshClient_SetRemotePublication((MOBLEUINT32) LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID, + element_number , + msg_opcode , + msg_buff, length, + ack_flag, + MOBLE_FALSE); + TidSend++; + if(TidSend >= MAX_TID_VALUE) + { + TidSend = 0; + } + if(result) + { + TRACE_M(TF_LIGHT_CLIENT,"Publication Error \r\n"); + } + + return result; +} + + +/** +* @brief LightModelClient_GetOpcodeTableCb: This function is call-back +* from the library to send Model Opcode Table info to library +* @param MODEL_OpcodeTableParam_t: Pointer to the Generic Model opcode array +* @param length: Pointer to the Length of Generic Model opcode array +* @retval MOBLE_RESULT +*/ +MOBLE_RESULT LightModelClient_GetOpcodeTableCb(const MODEL_OpcodeTableParam_t **data, + MOBLEUINT16 *length) +{ + *data = Light_Client_Opcodes_Table; + *length = sizeof(Light_Client_Opcodes_Table)/sizeof(Light_Client_Opcodes_Table[0]); + + return MOBLE_RESULT_SUCCESS; +} + +/** +* @brief LightModelClient_GetStatusRequestCb : This function is call-back +* from the library to send response to the message from peer +* @param peer_addr: Address of the peer +* @param dst_peer: destination send by peer for this node. It can be a +* unicast or group address +* @param opcode: Received opcode of the Status message callback +* @param pResponsedata: Pointer to the buffer to be updated with status +* @param plength: Pointer to the Length of the data, to be updated by application +* @param pRxData: Pointer to the data received in packet. +* @param dataLength: length of the data in packet. +* @param response: Value to indicate wheather message is acknowledged meassage or not. +* @retval MOBLE_RESULT +*/ +MOBLE_RESULT LightModelClient_GetStatusRequestCb(MOBLE_ADDRESS peer_addr, + MOBLE_ADDRESS dst_peer, + MOBLEUINT16 opcode, + MOBLEUINT8 *pResponsedata, + MOBLEUINT32 *plength, + MOBLEUINT8 const *pRxData, + MOBLEUINT32 dataLength, + MOBLEBOOL response) + +{ + TRACE_M(TF_LIGHT_CLIENT,"response status enable \n\r"); + + return MOBLE_RESULT_SUCCESS; +} + + +/** +* @brief LightModelClient_ProcessMessageCb: This is a callback function from +* the library whenever a Generic Model message is received +* @param peer_addr: Address of the peer +* @param dst_peer: destination send by peer for this node. It can be a +* unicast or group address +* @param opcode: Received opcode of the Status message callback +* @param pData: Pointer to the buffer to be updated with status +* @param length: Length of the parameters received +* @param response: if TRUE, the message is an acknowledged message +* @param pRxData: Pointer to the data received in packet. +* @param dataLength: length of the data in packet. +* @param response: Value to indicate wheather message is acknowledged meassage or not. +* @retval MOBLE_RESULT +*/ +MOBLE_RESULT LightModelClient_ProcessMessageCb(MOBLE_ADDRESS peer_addr, + MOBLE_ADDRESS dst_peer, + MOBLEUINT16 opcode, + MOBLEUINT8 const *pRxData, + MOBLEUINT32 dataLength, + MOBLEBOOL response + ) +{ + + MOBLE_RESULT result = MOBLE_RESULT_SUCCESS; + //tClockTime delay_t = Clock_Time(); + + TRACE_M(TF_LIGHT_CLIENT,"dst_peer = %.2X , peer_add = %.2X, opcode= %.2X ,response= %.2X \r\n ", + dst_peer, peer_addr, opcode , response); + + switch(opcode) + { + case LIGHT_LIGHTNESS_STATUS: + { + Light_Client_Lightness_Status(pRxData, dataLength); + break; + } + default: + { + break; + } + } + + if((result == MOBLE_RESULT_SUCCESS) && (response == MOBLE_TRUE)) + { + Model_SendResponse(peer_addr,dst_peer,opcode,pRxData,dataLength); + } + + return MOBLE_RESULT_SUCCESS; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/******************* (C) COPYRIGHT 2017 STMicroelectronics *****END OF FILE****/ + diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/light_lc.c b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/light_lc.c index ea620bf0a..daaf7048d 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/light_lc.c +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/light_lc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file light_lc.c * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Light Control model middleware file ****************************************************************************** * @attention @@ -71,35 +71,32 @@ Light_LC_TimeParam_t Light_LC_TimeParam; Light_LC_Param_t Light_LC_Param; -Light_LC_ModelFlag_t Light_LC_ModelFlag; - -Light_LC_OnOffState_t Light_LC_OnOffState; - MOBLEUINT8 Light_LC_UpdateFlag = 0; MOBLEUINT32 Timer_value; +extern MOBLEUINT8 TidSend; #endif MODEL_OpcodeTableParam_t Light_LC_Opcodes_Table[] = { #ifdef ENABLE_LIGHT_MODEL_SERVER_LC - {LIGHT_LC_MODE_GET, MOBLE_TRUE, 0, 0, LIGHT_LC_MODE_STATUS , 1, 1}, - {LIGHT_LC_MODE_SET, MOBLE_TRUE, 1, 1, LIGHT_LC_MODE_STATUS , 1, 1}, - {LIGHT_LC_MODE_SET_UNACK, MOBLE_FALSE, 1, 1, 0 , 1, 1}, - {LIGHT_LC_MODE_STATUS, MOBLE_FALSE, 1, 1, 0 , 1, 1}, - {LIGHT_LC_OM_GET, MOBLE_TRUE, 0, 0, LIGHT_LC_OM_STATUS , 1, 1}, - {LIGHT_LC_OM_SET, MOBLE_TRUE, 1, 1, LIGHT_LC_OM_STATUS , 1, 1}, - {LIGHT_LC_OM_SET_UNACK, MOBLE_FALSE, 1, 1, 0 , 1, 1}, - {LIGHT_LC_OM_STATUS, MOBLE_FALSE, 1, 1, 0 , 1, 1}, - {LIGHT_LC_ON_OFF_GET, MOBLE_TRUE, 0, 0, LIGHT_LC_ON_OFF_STATUS , 1, 3}, - {LIGHT_LC_ON_OFF_SET, MOBLE_TRUE, 2, 4, LIGHT_LC_ON_OFF_STATUS , 1, 3}, - {LIGHT_LC_ON_OFF_SET_UNACK, MOBLE_FALSE, 2, 4, 0 , 1, 3}, - {LIGHT_LC_ON_OFF_STATUS, MOBLE_FALSE, 1, 3, 0 , 1, 3}, + {LIGHT_MODEL_SERVER_LC_MODEL_ID ,LIGHT_LC_MODE_GET, MOBLE_TRUE, 0, 0, LIGHT_LC_MODE_STATUS , 1, 1}, + {LIGHT_MODEL_SERVER_LC_MODEL_ID ,LIGHT_LC_MODE_SET, MOBLE_TRUE, 1, 1, LIGHT_LC_MODE_STATUS , 1, 1}, + {LIGHT_MODEL_SERVER_LC_MODEL_ID ,LIGHT_LC_MODE_SET_UNACK, MOBLE_FALSE, 1, 1, 0 , 1, 1}, + {LIGHT_MODEL_SERVER_LC_MODEL_ID ,LIGHT_LC_MODE_STATUS, MOBLE_FALSE, 1, 1, 0 , 1, 1}, + {LIGHT_MODEL_SERVER_LC_MODEL_ID ,LIGHT_LC_OM_GET, MOBLE_TRUE, 0, 0, LIGHT_LC_OM_STATUS , 1, 1}, + {LIGHT_MODEL_SERVER_LC_MODEL_ID ,LIGHT_LC_OM_SET, MOBLE_TRUE, 1, 1, LIGHT_LC_OM_STATUS , 1, 1}, + {LIGHT_MODEL_SERVER_LC_MODEL_ID ,LIGHT_LC_OM_SET_UNACK, MOBLE_FALSE, 1, 1, 0 , 1, 1}, + {LIGHT_MODEL_SERVER_LC_MODEL_ID ,LIGHT_LC_OM_STATUS, MOBLE_FALSE, 1, 1, 0 , 1, 1}, + {LIGHT_MODEL_SERVER_LC_MODEL_ID ,LIGHT_LC_ON_OFF_GET, MOBLE_TRUE, 0, 0, LIGHT_LC_ON_OFF_STATUS , 1, 3}, + {LIGHT_MODEL_SERVER_LC_MODEL_ID ,LIGHT_LC_ON_OFF_SET, MOBLE_TRUE, 2, 4, LIGHT_LC_ON_OFF_STATUS , 1, 3}, + {LIGHT_MODEL_SERVER_LC_MODEL_ID ,LIGHT_LC_ON_OFF_SET_UNACK, MOBLE_FALSE, 2, 4, 0 , 1, 3}, + {LIGHT_MODEL_SERVER_LC_MODEL_ID ,LIGHT_LC_ON_OFF_STATUS, MOBLE_FALSE, 1, 3, 0 , 1, 3}, #endif #ifdef ENABLE_LIGHT_MODEL_SERVER_LC_SETUP - {LIGHT_LC_PROPERTY_GET, MOBLE_TRUE, 2, 2, LIGHT_LC_PROPERTY_STATUS , 2, 10}, - {LIGHT_LC_PROPERTY_SET, MOBLE_TRUE, 2, 10, LIGHT_LC_PROPERTY_STATUS , 2, 10}, - {LIGHT_LC_PROPERTY_SET_UNACK, MOBLE_FALSE, 2, 10, 0 , 2, 10}, - {LIGHT_LC_PROPERTY_STATUS, MOBLE_FALSE, 2, 10, 0 , 2, 10}, + {LIGHT_MODEL_SERVER_LC_SETUP_MODEL_ID ,LIGHT_LC_PROPERTY_GET, MOBLE_TRUE, 2, 2, LIGHT_LC_PROPERTY_STATUS , 2, 10}, + {LIGHT_MODEL_SERVER_LC_SETUP_MODEL_ID ,LIGHT_LC_PROPERTY_SET, MOBLE_TRUE, 2, 10, LIGHT_LC_PROPERTY_STATUS , 2, 10}, + {LIGHT_MODEL_SERVER_LC_SETUP_MODEL_ID ,LIGHT_LC_PROPERTY_SET_UNACK, MOBLE_FALSE, 2, 10, 0 , 2, 10}, + {LIGHT_MODEL_SERVER_LC_SETUP_MODEL_ID ,LIGHT_LC_PROPERTY_STATUS, MOBLE_FALSE, 2, 10, 0 , 2, 10}, #endif {0} }; @@ -283,7 +280,7 @@ MOBLE_RESULT Light_LC_OnOffSet(MOBLEUINT8 const *lcOnOff_param, MOBLEUINT32 leng } /* Application Callback */ - (LightLCAppli_cb.LightLC_OnOff_Set_cb)(&Light_LC_OnOffState , 0); + (LightLCAppli_cb.LightLC_OnOff_Set_cb)(&Light_LC_Param , 0); return MOBLE_RESULT_SUCCESS; } @@ -299,23 +296,9 @@ MOBLE_RESULT Light_LC_OnOffStatus(MOBLEUINT8* lcOnOff_status, MOBLEUINT32 *pleng TRACE_I(TF_LIGHT_LC,"Light_LC_OnOffStatus callback received \r\n"); Appli_LightLC_GetStatus_cb.GetLightLC_OnOffState_cb(LightLC_GetBuff); - Light_LC_OnOffState.Present_OnOff_State = LightLC_GetBuff[0]; - if((Light_LC_ModelFlag.LightLcOptionalParam == 1) || (Light_LC_TimeParam.StepValue != 0)) - { - *lcOnOff_status = Light_LC_OnOffState.Present_OnOff_State ; - *(lcOnOff_status+1) = Light_LC_OnOffState.Target_OnOff; - *(lcOnOff_status+2) = Light_LC_OnOffState.RemainingTime; - *plength = 3; - Light_LC_ModelFlag.LightLcOptionalParam = 0; - } - else - { /* When no optional parameter received, target value will - be sent in status message. - */ - *lcOnOff_status = Light_LC_OnOffState.Present_OnOff_State ; + *lcOnOff_status = LightLC_GetBuff[0] ; *plength = 1; - } return MOBLE_RESULT_SUCCESS; } @@ -336,8 +319,6 @@ MOBLE_RESULT Light_LC_PropertySet(MOBLEUINT8 const *lcProp_param, MOBLEUINT32 le Light_LC_Value_t Light_LC_Value; - Light_LC_Value.Property_Value = 0; - Light_LC_PropertyID = lcProp_param[1] << 8; Light_LC_PropertyID |= lcProp_param[0]; @@ -440,8 +421,8 @@ MOBLE_RESULT Light_LC_PropertyStatus( MOBLEUINT8* lcData_param, MOBLEUINT32* ple /** * @brief Light_LC_GetPropertyID_value: This function is call-back * from the library to send Model Opcode Table info to library -* @param Light_LC_Property_Table_t: Pointer to the property id table array -* @param pROPERTY_ID: Property id of the parameter. +* @param Prop_Value:value belongs to property id +* @param prop_ID: Property id of the parameter. * @retval MOBLEUINT32 */ MOBLE_RESULT Light_LC_SetPropertyID_value(MOBLEUINT32 Prop_Value, @@ -510,8 +491,7 @@ MOBLE_RESULT Light_LC_SetPropertyID_value(MOBLEUINT32 Prop_Value, /** * @brief Light_LC_GetPropertyID_value: This function is call-back * from the library to send Model Opcode Table info to library -* @param Light_LC_Property_Table_t: Pointer to the property id table array -* @param pROPERTY_ID: Property id of the parameter. +* @param property_ID: Property id of the parameter. * @retval MOBLEUINT32 */ MOBLEUINT32 Light_LC_GetPropertyID_value(MOBLEUINT16 property_ID) @@ -601,7 +581,6 @@ MOBLE_RESULT Light_LC_ModelServer_GetStatusRequestCb(MOBLE_ADDRESS peer_addr, MOBLEBOOL response) { - TRACE_M(TF_LIGHT,"response status enable \n\r"); switch(opcode) { #ifdef ENABLE_LIGHT_MODEL_SERVER_LC @@ -696,7 +675,10 @@ MOBLE_RESULT Light_LC_ModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, case LIGHT_LC_ON_OFF_SET: case LIGHT_LC_ON_OFF_SET_UNACK: { - Light_LC_OnOffSet(pRxData,dataLength); + if(!MOBLE_FAILED(result = Chk_TidValidity(peer_addr,dst_peer,pRxData[6]))) + { + Light_LC_OnOffSet(pRxData,dataLength); + } break; } case LIGHT_LC_ON_OFF_STATUS: @@ -748,14 +730,13 @@ void Light_LC_Fsm(void) MOBLEUINT32 resetTime = Clock_Time(); MOBLEUINT32 delta = resetTime - Timer_value; MOBLEUINT8 data_Buff[6]; - MOBLE_ADDRESS publishAddress; - MOBLEUINT8 elementNumber; - MOBLEUINT8 elementIndex = 0; + MOBLE_RESULT result = MOBLE_RESULT_SUCCESS; + MOBLE_ADDRESS srcAdd; MOBLEUINT16 state_Value = 0; MOBLEUINT16 LightnessValue; MOBLEUINT16 luxLightnessvalue = 0; MOBLEUINT16 opcode; - MOBLEUINT8 transitionTime = 0; + MOBLEUINT8 transitionTime; MOBLEUINT32 length = 5; static MOBLEUINT8 Publish_flag = 0; @@ -1281,27 +1262,35 @@ void Light_LC_Fsm(void) { } - elementNumber = BLE_GetElementNumber(); - - publishAddress = BLEMesh_GetPublishAddress(elementNumber); data_Buff[0] = state_Value; data_Buff[1] = state_Value >> 8; - data_Buff[2] = 0x01; + data_Buff[2] = TidSend; data_Buff[3] = transitionTime; + TidSend++; + if(TidSend >= MAX_TID_VALUE) + { + TidSend = 0; + } + srcAdd = BLEMesh_GetAddress(); - BLEMesh_SetRemoteData(publishAddress, elementIndex, + result = BLEMesh_SetRemotePublication(LIGHT_MODEL_SERVER_LC_MODEL_ID, srcAdd , opcode , data_Buff, length, MOBLE_FALSE, MOBLE_FALSE); + + if(result) + { + TRACE_I(TF_LIGHT_LC,"Publication Error \r\n"); + } Publish_flag = 0; } } /** -* @brief Generic_GetStepValue: This function calculates values for transition time +* @brief Light_LC_GetStepValue: This function calculates values for transition time * @param stepParam: Transition time set value of particular model message. -* retval void +* retval MOBLEUINT32 */ MOBLEUINT32 Light_LC_GetStepValue(MOBLEUINT8 stepParam) { @@ -1328,9 +1317,9 @@ MOBLEUINT32 Light_LC_GetStepValue(MOBLEUINT8 stepParam) } /** -* @brief Generic_GetStepValue: This function calculates values for transition time -* @param stepParam: Transition time set value of particular model message. -* retval void +* @brief Get_TimeToWait: This function calculates the time to wait foe any condition +* @param Proprety_ID: property id of the parameter +* retval MOBLEUINT32 */ MOBLEUINT32 Get_TimeToWait(MOBLEUINT16 Proprety_ID) { @@ -1349,7 +1338,7 @@ MOBLEUINT32 Get_TimeToWait(MOBLEUINT16 Proprety_ID) /** * @brief Light_control_Process: Function to execute the transition state machine for -particular Light LC model and state machine Light LC application +* particular Light LC model and state machine Light LC application * @param void * @retval void */ @@ -1371,7 +1360,7 @@ void Light_control_Process(void) /** * @brief Light_LC_LuxLevelOutputValue: This function will return the lightness value from the lux sensors. -* @param void: +* @param property_ID:property id of the parameter * @retval MOBLEUINT16: **/ MOBLEUINT16 Light_LC_LuxLevelOutputValue(MOBLEUINT16 property_ID) @@ -1392,7 +1381,8 @@ MOBLEUINT16 Light_LC_LuxLevelOutputValue(MOBLEUINT16 property_ID) /** * @brief Light_LC_MaxLightnessValue: This function will return the maximum value after comparision. -* @param void: +* @param Param1:paramter to the function +* @param Param2:paramter to the function * @retval MOBLEUINT16: **/ MOBLEUINT16 Light_LC_MaxLightnessValue(MOBLEUINT16 Param1,MOBLEUINT16 Param2) diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/meshdfu_node.c b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/meshdfu_node.c index 23e49f837..b1d01e64a 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/meshdfu_node.c +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/meshdfu_node.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file meshdfu_node.c * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-May-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief BLE-Mesh Device Firmware Upgrade / FOTA over the mesh implementation ****************************************************************************** * @attention diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/sensors.c b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/sensors.c index 7fb75d75d..dc387b794 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/sensors.c +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/sensors.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file sensors.c * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Sensors model middleware file ****************************************************************************** * @attention @@ -73,28 +73,28 @@ const MODEL_OpcodeTableParam_t Sensor_Opcodes_Table[] = { Here in this array, Handler is not defined; */ #ifdef ENABLE_SENSOR_MODEL_SERVER - {SENSOR_DESCRIPTOR_GET, MOBLE_TRUE, 0, 2, SENSOR_DESCRIPTOR_STATUS , 2, 16}, - {SENSOR_DESCRIPTOR_STATUS, MOBLE_FALSE, 2, 16, SENSOR_DESCRIPTOR_STATUS , 2, 16}, - {SENSOR_GET, MOBLE_TRUE, 0, 2, SENSOR_STATUS , 0,65 }, /* STATUS MESSAGE AS MARSHALLED DATA */ - {SENSOR_STATUS, MOBLE_FALSE, 0, 65, SENSOR_STATUS , 0,65 }, - {SENSOR_COLUMN_GET, MOBLE_TRUE, 3, 3, SENSOR_COLUMN_STATUS , 4, 8}, /* GET VARIABLE TAKEN AS 1 (2+VARIABLE) */ - {SENSOR_COLUMN_STATUS, MOBLE_FALSE, 4, 8, SENSOR_COLUMN_STATUS , 4, 8}, + {SENSOR_SERVER_MODEL_ID ,SENSOR_DESCRIPTOR_GET, MOBLE_TRUE, 0, 2, SENSOR_DESCRIPTOR_STATUS , 2, 75}, + {SENSOR_SERVER_MODEL_ID ,SENSOR_DESCRIPTOR_STATUS, MOBLE_FALSE, 2, 75, SENSOR_DESCRIPTOR_STATUS , 2, 75}, + {SENSOR_SERVER_MODEL_ID ,SENSOR_GET, MOBLE_TRUE, 0, 2, SENSOR_STATUS , 0,65 }, /* STATUS MESSAGE AS MARSHALLED DATA */ + {SENSOR_SERVER_MODEL_ID ,SENSOR_STATUS, MOBLE_FALSE, 0, 65, 0 , 0,65 }, + {SENSOR_SERVER_MODEL_ID ,SENSOR_COLUMN_GET, MOBLE_TRUE, 3, 3, SENSOR_COLUMN_STATUS , 4, 8}, /* GET VARIABLE TAKEN AS 1 (2+VARIABLE) */ + {SENSOR_SERVER_MODEL_ID ,SENSOR_COLUMN_STATUS, MOBLE_FALSE, 4, 8, 0 , 4, 8}, #endif #ifdef ENABLE_SENSOR_MODEL_SERVER_SETUP - {SENSOR_CADENCE_GET, MOBLE_TRUE, 2, 2, SENSOR_CADENCE_STATUS , 2, 8}, - {SENSOR_CADENCE_SET, MOBLE_TRUE, 8, 8, SENSOR_CADENCE_STATUS , 2, 8}, - {SENSOR_CADENCE_SET_UNACK, MOBLE_FALSE, 8, 8, SENSOR_CADENCE_STATUS , 2, 8}, - {SENSOR_CADENCE_STATUS, MOBLE_FALSE, 2, 8, SENSOR_CADENCE_STATUS , 2, 8}, - {SENSOR_SETTING_GET, MOBLE_TRUE, 2, 2, SENSOR_SETTING_STATUS_PID , 4 , 4}, - {SENSOR_SETTING_STATUS_PID, MOBLE_FALSE, 4, 4, SENSOR_SETTING_STATUS_PID , 4 , 4}, - {SENSOR_SETTING_GET_SETTING_ID, MOBLE_TRUE, 4, 4, SENSOR_SETTING_STATUS_SETTING_ID , 5, 5}, /* STATUS VARIABLE TAKEN AS 1 (4 + VARIABLE) */ - {SENSOR_SETTING_SET, MOBLE_TRUE, 5, 5, SENSOR_SETTING_STATUS_SETTING_ID , 5, 5}, /* SET VARIABLE TAKEN AS 1 (4_VARIABLE) */ - {SENSOR_SETTING_SET_UNACK, MOBLE_FALSE, 5, 5, SENSOR_SETTING_STATUS_SETTING_ID , 5, 5}, - {SENSOR_SETTING_STATUS_SETTING_ID, MOBLE_FALSE, 5, 5, SENSOR_SETTING_STATUS_SETTING_ID , 5, 5}, - {SENSOR_SERIES_GET, MOBLE_TRUE, 2, 6, SENSOR_SERIES_STATUS , 8, 8}, /* GET VARIABLE TAKEN AS 4 (2+VARAIBLE) , 2 VARIABLE PARAMTER */ - {SENSOR_SERIES_STATUS, MOBLE_FALSE, 8, 8, SENSOR_SERIES_STATUS , 8, 8}, -#endif + {SENSOR_SETUP_SERVER_MODEL_ID ,SENSOR_CADENCE_GET, MOBLE_TRUE, 2, 2, SENSOR_CADENCE_STATUS , 2, 8}, + {SENSOR_SETUP_SERVER_MODEL_ID ,SENSOR_CADENCE_SET, MOBLE_TRUE, 8, 8, SENSOR_CADENCE_STATUS , 2, 8}, + {SENSOR_SETUP_SERVER_MODEL_ID ,SENSOR_CADENCE_SET_UNACK, MOBLE_FALSE, 8, 8, SENSOR_CADENCE_STATUS , 2, 8}, + {SENSOR_SETUP_SERVER_MODEL_ID ,SENSOR_CADENCE_STATUS, MOBLE_FALSE, 2, 8, 0 , 2, 8}, + {SENSOR_SETUP_SERVER_MODEL_ID ,SENSOR_SETTING_GET, MOBLE_TRUE, 2, 2, SENSOR_SETTING_STATUS_PID , 4 , 4}, + {SENSOR_SETUP_SERVER_MODEL_ID ,SENSOR_SETTING_STATUS_PID, MOBLE_FALSE, 4, 4, 0 , 4 , 4}, + {SENSOR_SETUP_SERVER_MODEL_ID ,SENSOR_SETTING_GET_SETTING_ID, MOBLE_TRUE, 4, 4, SENSOR_SETTING_STATUS_SETTING_ID , 5, 5}, /* STATUS VARIABLE TAKEN AS 1 (4 + VARIABLE) */ + {SENSOR_SETUP_SERVER_MODEL_ID ,SENSOR_SETTING_SET, MOBLE_TRUE, 5, 5, SENSOR_SETTING_STATUS_SETTING_ID , 5, 5}, /* SET VARIABLE TAKEN AS 1 (4_VARIABLE) */ + {SENSOR_SETUP_SERVER_MODEL_ID ,SENSOR_SETTING_SET_UNACK, MOBLE_FALSE, 5, 5, SENSOR_SETTING_STATUS_SETTING_ID , 5, 5}, + {SENSOR_SETUP_SERVER_MODEL_ID ,SENSOR_SETTING_STATUS_SETTING_ID, MOBLE_FALSE, 5, 5, 0 , 5, 5}, + {SENSOR_SETUP_SERVER_MODEL_ID ,SENSOR_SERIES_GET, MOBLE_TRUE, 2, 6, SENSOR_SERIES_STATUS , 8, 8}, /* GET VARIABLE TAKEN AS 4 (2+VARAIBLE) , 2 VARIABLE PARAMTER */ + {SENSOR_SETUP_SERVER_MODEL_ID ,SENSOR_SERIES_STATUS, MOBLE_FALSE, 8, 8, 0 , 8, 8}, +#endif {0} }; @@ -521,7 +521,7 @@ MOBLE_RESULT SensorModelServer_ProcessMessageCb(MOBLE_ADDRESS peer_addr, return MOBLE_RESULT_FALSE; } - if(property_ID == LIGHT_CONTROL_LIGHTNESS_ON_ID) + if(property_ID == PRESENCE_DETECTED_PROPERTY) { #ifdef ENABLE_LIGHT_MODEL_SERVER_LC Light_LC_ModeSet(&pRxData[2],1); diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/time_scene.c b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/time_scene.c index 4b7dd58a7..4b021ee4d 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/time_scene.c +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/time_scene.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file time_scene.c * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Time and Scene model middleware file ****************************************************************************** * @attention @@ -47,8 +47,11 @@ #include "Math.h" #include "time_scene.h" +/** @addtogroup MODEL_TIME_SCENE +* @{ +*/ -/** @addtogroup Model_Callbacks +/** @addtogroup Time_Scene_Model_Callbacks * @{ */ @@ -61,24 +64,35 @@ const MODEL_OpcodeTableParam_t Time_Scene_Opcodes_Table[] = { MOBLEUINT16 max_payload_size; Here in this array, Handler is not defined; */ #ifdef ENABLE_TIME_MODEL_SERVER - {TIME_GET, MOBLE_TRUE, 0, 0, TIME_STATUS , 10, 10}, - {TIME_SET, MOBLE_TRUE, 10, 10, TIME_STATUS , 10, 10}, - {TIME_ROLE_GET, MOBLE_TRUE, 0, 0, TIME_ROLL_STATUS , 1, 1}, - {TIME_ROLL_SET, MOBLE_TRUE, 1, 1, TIME_ROLL_STATUS , 1, 1}, - {TIME_ZONE_GET, MOBLE_TRUE, 0, 0, TIME_ZONE_STATUS , 7, 7}, - {TIME_ZONE_SET, MOBLE_TRUE, 6, 6, TIME_ZONE_STATUS , 7, 7}, - {TAI_UTC_DELTA_GET, MOBLE_TRUE, 0, 0, TAI_UTC_DELTA_STATUS , 9, 9}, - {TAI_UTC_DELTA_SET, MOBLE_TRUE, 7, 7, TAI_UTC_DELTA_STATUS , 9, 9}, + {TIME_MODEL_SERVER_MODEL_ID ,TIME_SET, MOBLE_TRUE, 10, 10, TIME_STATUS , 10, 10}, + {TIME_MODEL_SERVER_MODEL_ID ,TIME_ZONE_SET, MOBLE_TRUE, 6, 6, TIME_ZONE_STATUS , 7, 7}, + {TIME_MODEL_SERVER_MODEL_ID ,TAI_UTC_DELTA_SET, MOBLE_TRUE, 7, 7, TAI_UTC_DELTA_STATUS , 9, 9}, + {TIME_MODEL_SERVER_MODEL_ID ,TIME_ROLE_GET, MOBLE_TRUE, 0, 0, TIME_ROLL_STATUS , 1, 1}, + {TIME_MODEL_SERVER_MODEL_ID ,TIME_ROLL_SET, MOBLE_TRUE, 1, 1, TIME_ROLL_STATUS , 1, 1}, + {TIME_MODEL_SERVER_MODEL_ID ,TIME_ROLL_STATUS, MOBLE_FALSE, 1, 1, NULL , 1, 1}, +#endif +#ifdef ENABLE_TIME_MODEL_SERVER_SETUP + {TIME_MODEL_SERVER_SETUP_MODEL_ID ,TIME_GET, MOBLE_TRUE, 0, 0, TIME_STATUS , 10, 10}, + {TIME_MODEL_SERVER_SETUP_MODEL_ID ,TIME_STATUS, MOBLE_FALSE, 10, 10, NULL , 10, 10}, + {TIME_MODEL_SERVER_SETUP_MODEL_ID ,TIME_ZONE_GET, MOBLE_TRUE, 0, 0, TIME_ZONE_STATUS , 7, 7}, + {TIME_MODEL_SERVER_SETUP_MODEL_ID ,TIME_ZONE_STATUS, MOBLE_FALSE, 7, 7, NULL , 7, 7}, + {TIME_MODEL_SERVER_SETUP_MODEL_ID ,TAI_UTC_DELTA_GET, MOBLE_TRUE, 0, 0, TAI_UTC_DELTA_STATUS , 9, 9}, + {TIME_MODEL_SERVER_SETUP_MODEL_ID ,TAI_UTC_DELTA_STATUS, MOBLE_FALSE, 9, 9, NULL , 9, 9}, + #endif #ifdef ENABLE_SCENE_MODEL_SERVER - {SCENE_GET, MOBLE_TRUE, 0, 0, SCENE_STATUS , 3, 6}, - {SCENE_RECALL, MOBLE_TRUE, 3, 5, SCENE_STATUS , 3, 6}, - {SCENE_RECALL_UNACK, MOBLE_FALSE, 3, 5, SCENE_STATUS , 3, 6}, - {SCENE_REGISTER_GET, MOBLE_TRUE, 0, 0, SCENE_REGISTER_STATUS , 5, 8}, - {SCENE_STORE, MOBLE_TRUE, 2, 2, SCENE_REGISTER_STATUS , 5, 8}, - {SCENE_STORE_UNACK, MOBLE_FALSE, 2, 2, SCENE_REGISTER_STATUS , 5, 8}, - {SCENE_DELETE, MOBLE_TRUE, 2, 2, SCENE_REGISTER_STATUS , 5, 8}, - {SCENE_DELETE_UNACK, MOBLE_FALSE, 2, 2, SCENE_REGISTER_STATUS , 5, 8}, + {SCENE_MODEL_SERVER_MODEL_ID ,SCENE_GET, MOBLE_TRUE, 0, 0, SCENE_STATUS , 3, 6}, + {SCENE_MODEL_SERVER_MODEL_ID ,SCENE_STATUS, MOBLE_FALSE, 3, 6, NULL , 3, 6}, + {SCENE_MODEL_SERVER_MODEL_ID ,SCENE_REGISTER_GET, MOBLE_TRUE, 0, 0, SCENE_REGISTER_STATUS , 5, 8}, + {SCENE_MODEL_SERVER_MODEL_ID ,SCENE_REGISTER_STATUS, MOBLE_FALSE, 5, 8, NULL , 5, 8}, + {SCENE_MODEL_SERVER_MODEL_ID ,SCENE_RECALL, MOBLE_TRUE, 3, 5, SCENE_STATUS , 3, 6}, + {SCENE_MODEL_SERVER_MODEL_ID ,SCENE_RECALL_UNACK, MOBLE_FALSE, 3, 5, SCENE_STATUS , 3, 6}, +#endif +#ifdef ENABLE_SCENE_MODEL_SERVER_SETUP + {SCENE_MODEL_SERVER_SETUP_MODEL_ID ,SCENE_STORE, MOBLE_TRUE, 2, 2, SCENE_REGISTER_STATUS , 5, 8}, + {SCENE_MODEL_SERVER_SETUP_MODEL_ID ,SCENE_STORE_UNACK, MOBLE_FALSE, 2, 2, SCENE_REGISTER_STATUS , 5, 8}, + {SCENE_MODEL_SERVER_SETUP_MODEL_ID ,SCENE_DELETE, MOBLE_TRUE, 2, 2, SCENE_REGISTER_STATUS , 5, 8}, + {SCENE_MODEL_SERVER_SETUP_MODEL_ID ,SCENE_DELETE_UNACK, MOBLE_FALSE, 2, 2, SCENE_REGISTER_STATUS , 5, 8}, #endif {0} }; diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/vendor.c b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/vendor.c index e02c06fdb..ae6f98e01 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/vendor.c +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/vendor.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file vendor.c * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Vendor model middleware file ****************************************************************************** * @attention @@ -48,11 +48,11 @@ #include "models_if.h" #include -/** @addtogroup BLE_Mesh +/** @addtogroup MODEL_VENDOR * @{ */ -/** @addtogroup models_BLE +/** @addtogroup Vendor_Model_Callbacks * @{ */ @@ -66,10 +66,9 @@ MOBLEUINT8 AppliBuffer[DATA_BUFFER_LENGTH] = {0x01,0x00}; MOBLEUINT16 CommandStatus = 0; extern MOBLEUINT8 NumberOfElements; -extern MOBLEUINT8 ResponseBuffer[8]; -extern MOBLEUINT8 BuffLength; +extern MOBLEUINT8 ResponseBuffer[VENDOR_DATA_BYTE]; +extern MOBLEUINT16 BuffLength; extern MOBLEUINT8 Appli_LedState; - /* -------------*******************------------------------- Vendor Model Opcode Table @@ -79,9 +78,16 @@ MOBLEUINT16 Vendor_Opcodes_Table[] = { APPLI_DEVICE_INFO_CMD, APPLI_LED_CONTROL_STATUS_CMD, APPLI_ELEMENT_TYPE_CMD, - APPLI_SENSOR_CNTRL_CMD + APPLI_SENSOR_CNTRL_CMD, + APPLI_DATA_CNTRL_CMD }; +char *Board_Type[] = +{ + "BLUENRG1_BRD_TYPE", + "BLUENRG2_BRD_TYPE", + "BLUENRG_MS_BRD_TYPE" +}; /* Private function prototypes -----------------------------------------------*/ #if ENABLE_APPLI_TEST extern MOBLEUINT8 txDataArray[]; @@ -146,11 +152,17 @@ MOBLE_RESULT Vendor_WriteLocalDataCb(MOBLE_ADDRESS peer_addr, B0 - Sub-Cmd LED B1-B7 - Data Bytes */ - TRACE_M(TF_VENDOR,"st device id %4.x \r\n",VENDORMODEL_STMICRO_ID1); VendorAppli_cb.LEDControlCommand_Cb(data,length,elementNumber,dst_peer); break; } - + case APPLI_DATA_CNTRL_CMD: + { + /*This is callback when ever command is coming for test of response + time,command reached count, data byte sent + */ + VendorAppli_cb.DataControlCommand_cb(data,length); + break; + } /* Default case - Not valid command */ default: { @@ -206,6 +218,14 @@ MOBLE_RESULT Vendor_WriteLocalDataCb(MOBLE_ADDRESS peer_addr, VendorAppli_cb.LEDControlCommand_Cb(data, length, elementNumber,dst_peer); break; } + case APPLI_DATA_CNTRL_CMD: + { + /*This is callback when ever command is coming for test of response + time,command reached count, data byte sent + */ + VendorAppli_cb.DataControlCommand_cb(data,length); + break; + } /* Default case - Not valid command */ default: { @@ -346,8 +366,7 @@ MOBLE_RESULT Vendor_ReadLocalDataCb(MOBLE_ADDRESS peer_addr, */ if(elementNumber == FIRST_ELEMENT) { - ResponseBuffer[0] = data[0]; - ResponseBuffer[1] = Appli_LedState; + ResponseBuffer[0] = Appli_LedState; } else if(elementNumber == SECOND_ELEMENT) @@ -362,6 +381,14 @@ MOBLE_RESULT Vendor_ReadLocalDataCb(MOBLE_ADDRESS peer_addr, break; } + case APPLI_DATA_CNTRL_CMD: + { + /*This is callback when ever command is coming for test of response + time,command reached count, data byte sent + */ + + break; + } default: { @@ -440,12 +467,14 @@ MOBLE_RESULT Vendor_OnResponseDataCb(MOBLE_ADDRESS peer_addr, MOBLEUINT32 timeStampRcv; MOBLEUINT8 subCmd = pRxData[0]; MOBLEUINT16 hitcmdcount = 0; - + MOBLEUINT8 increment = 1; /* Traces for the Data */ - TRACE_I(TF_SERIAL_CTRL,"Peer_addr=[%02x],\n\r", peer_addr); - TRACE_I(TF_SERIAL_CTRL,"DATA_RECEIVED length = %ld\n\r", dataLength); + TRACE_I(TF_VENDOR,"Vendor_OnResponseDataCb: peer_addr=[%02x], dst_peer_addr=[%02x],\ + command=[%02x], Response=[%02x] \n\r", peer_addr, dst_peer, command, response ); + TRACE_I(TF_VENDOR,"DATA_RECEIVED length = %d\n\r", dataLength); + TRACE_M(TF_VENDOR_COMMAND,"#%02hx-%02hx! \n\r",command,pRxData[0]); switch(command) { case APPLI_TEST_CMD: @@ -458,34 +487,6 @@ MOBLE_RESULT Vendor_OnResponseDataCb(MOBLE_ADDRESS peer_addr, receiver node. */ #if ENABLE_APPLI_TEST - MOBLEUINT8 idx; - if(dataLength !=0) - { - MOBLEUINT8 valueCounter = 0; - - for (idx=0; idx= waitPeriod)) - { - Clockflag = CLOCK_FLAG_DISABLE; - return 0x01; - - } - return 0x00; + static MOBLEUINT8 Clockflag = 0; + static MOBLEUINT32 Check_time; + + + if(Clockflag == CLOCK_FLAG_DISABLE) + { + Check_time = Clock_Time(); + Clockflag = CLOCK_FLAG_ENABLE; + } + /* The function will called untill the testcount will not become zero */ + + if(((Clock_Time()- Check_time) >= waitPeriod)) + { + Clockflag = CLOCK_FLAG_DISABLE; + return 0x01; + + } + return 0x00; } /** @@ -365,7 +384,8 @@ MOBLEUINT8 processDelay(MOBLEUINT16 waitPeriod) */ void Test_Process(void) { - if(TestNumber){ + if(TestNumber) + { if(TestNumber == CMD_INDEX_RES_01) { diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Src/mesh_cfg.c b/Middlewares/ST/STM32_WPAN/ble/mesh/Src/mesh_cfg.c index ba5294447..45b0aa5c2 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/Src/mesh_cfg.c +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/Src/mesh_cfg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file mesh_cfg.c * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief User configurable settings for BLE-Mesh ****************************************************************************** * @attention @@ -32,7 +32,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * -* Initial BLE-Mesh is built over Motorolas Mesh over Bluetooth Low Energy +* Initial BLE-Mesh is built over Motorola's Mesh over Bluetooth Low Energy * (MoBLE) technology. The present solution is developed and maintained for both * Mesh library and Applications solely by STMicroelectronics. * @@ -41,6 +41,7 @@ /* Includes ------------------------------------------------------------------*/ #include "mesh_cfg.h" +#include "mesh_cfg_usr.h" #include "types.h" #include "ble_mesh.h" #include "compiler.h" @@ -49,9 +50,11 @@ #include "light.h" #include "sensors.h" #include "vendor.h" +#include "config_client.h" #include "light_lc.h" #include "appli_mesh.h" #include +#include "time_scene.h" /* Note: Please use Full Library configuration in project options to use the full configuration of the C/C++ runtime library for printf and scanf functionality */ @@ -69,6 +72,9 @@ #if ENABLE_APPLI_TEST #include "appli_test.c" #endif + #if ENABLE_SERIAL_PRVN + #include "serial_prvn.c" + #endif #endif #endif @@ -81,24 +87,69 @@ MOBLEUINT8 dyn_buffer_m[DYNAMIC_MEMORY_SIZE + \ MAX_APPLICATION_PACKET_SIZE + \ SAR_BUFFER_SIZE + \ NEIGHBOR_TABLE_DYNAMIC_MEMORY_SIZE] = {0}; + + +#define MODELDATA_SIZE (MAX_APPLICATION_PACKET_SIZE+16) +#define MODELS_BUFFER_SIZE (MODELDATA_SIZE) + +#ifdef STATIC_MEMORY_ALLOCATION_IN_APPLI +ALIGN(4) +MOBLEUINT8 aModelsBuff[MODELS_BUFFER_SIZE]; + +ALIGN(4) +MOBLEUINT8 aModelsBuff_Response[MODELS_BUFFER_SIZE]; + +ALIGN(4) +MOBLEUINT8 aLowerTptBuff[MODELS_BUFFER_SIZE]; + +ALIGN(4) +MOBLEUINT8 aLowerTptFnBuff[16]; + +ALIGN(4) +MOBLEUINT8 aLowerTptAppBuff[MAX_APPLICATION_PACKET_SIZE+16]; + +ALIGN(4) +MOBLEUINT8 aProvisionParamBuff[448]; + +ALIGN(4) +MOBLEUINT8 aAppli_SAR_Buffer[24+MAX_APPLICATION_PACKET_SIZE]; + +ALIGN(4) +MOBLEUINT8 aTrans_SegIn_Buffer[40*TPT_SEGMENT_COUNT]; + +ALIGN(4) +MOBLEUINT8 aTrans_Seq0_Buffer[40*TPT_SEGMENT_COUNT]; + +ALIGN(4) +MOBLEUINT8 aTrans_Out_Buffer[12*TPT_SEGMENT_COUNT]; + +ALIGN(4) +MOBLEUINT8 aElementsCC[0x3b8]; +#endif + extern const MOBLEUINT8 StaticOobBuff[]; extern const MOBLEUINT8 PubKeyBuff[]; extern const MOBLEUINT8 PrivKeyBuff[]; +extern MOBLEUINT8 NumberOfElements; __attribute__((aligned(4)))const DynBufferParam_t DynBufferParam = { dyn_buffer_m, (MOBLEUINT16) (DYNAMIC_MEMORY_SIZE + SAR_BUFFER_SIZE ), (MOBLEUINT16) FRIEND_BUFF_DYNAMIC_MEMORY_SIZE, (MOBLEUINT16) MAX_APPLICATION_PACKET_SIZE, - (MOBLEUINT16) NEIGHBOR_TABLE_DYNAMIC_MEMORY_SIZE + (MOBLEUINT16) NEIGHBOR_TABLE_DYNAMIC_MEMORY_SIZE, + (MOBLEUINT16) MODELS_BUFFER_SIZE }; + + + const tr_params_t TrParams = TRANSMIT_RECEIVE_PARAMS; -#if defined(BLUENRG1_DEVICE) || defined(BLUENRG2_DEVICE) /* BLUENRG1 or BLUENRG2 */ +//#if defined(BLUENRG1_DEVICE) || defined(BLUENRG2_DEVICE) /* BLUENRG1 or BLUENRG2 */ const lpn_params_t LpnParams = LOW_POWER_NODE_PARAMS; -#else -const lpn_params_t LpnParams; -#endif +//#else +//const lpn_params_t LpnParams; +//#endif const fn_params_t FnParams = FRIEND_NODE_PARAMS; const prvn_params_t PrvnParams = UNPROV_NODE_INFO_PARAMS; const neighbor_table_init_params_t NeighborTableParams = NEIGHBOR_TABLE_PARAMS; @@ -107,6 +158,13 @@ const neighbor_table_init_params_t NeighborTableParams = NEIGHBOR_TABLE_PARAMS; __attribute__((aligned(4))) const MOBLEUINT16 Appli_SIG_Models[]= { /*****************************************************************************/ +/** Following Section places Generic MODEL Enabled Client IDs ************/ +/*****************************************************************************/ + +#ifdef ENABLE_CONFIG_MODEL_CLIENT + SIG_MODEL_ID_CONFIG_CLIENT, +#endif + /*****************************************************************************/ /** Following Section places GENERIC MODEL Enabled SERVER IDs ************/ /*****************************************************************************/ @@ -205,7 +263,9 @@ __attribute__((aligned(4))) const MOBLEUINT16 Appli_SIG_Models[]= #ifdef ENABLE_LIGHT_MODEL_SERVER_HSL_SATURATION LIGHT_MODEL_SERVER_HSL_SATURATION_MODEL_ID, #endif - +/*****************************************************************************/ +/** Following Section places Light XYL MODEL Enabled SERVER IDs ************/ +/*****************************************************************************/ #ifdef ENABLE_LIGHT_MODEL_SERVER_XYL LIGHT_MODEL_SERVER_XYL_MODEL_ID, #endif @@ -214,6 +274,9 @@ __attribute__((aligned(4))) const MOBLEUINT16 Appli_SIG_Models[]= LIGHT_MODEL_SERVER_XYL_SETUP_MODEL_ID, #endif +/*****************************************************************************/ +/** Following Section places Light LC MODEL Enabled SERVER IDs ************/ +/*****************************************************************************/ #ifdef ENABLE_LIGHT_MODEL_SERVER_LC LIGHT_MODEL_SERVER_LC_MODEL_ID, #endif @@ -233,7 +296,39 @@ __attribute__((aligned(4))) const MOBLEUINT16 Appli_SIG_Models[]= SENSOR_SETUP_SERVER_MODEL_ID, #endif +/*****************************************************************************/ +/** Following Section places Time and Scene MODEL Enabled SERVER IDs ************/ +/*****************************************************************************/ +#ifdef ENABLE_TIME_MODEL_SERVER +TIME_MODEL_SERVER_MODEL_ID, +#endif +#ifdef ENABLE_TIME_MODEL_SERVER_SETUP +TIME_MODEL_SERVER_SETUP_MODEL_ID, +#endif +#ifdef ENABLE_SCENE_MODEL_SERVER +SCENE_MODEL_SERVER_MODEL_ID, +#endif +#ifdef ENABLE_SCENE_MODEL_SERVER_SETUP +SCENE_MODEL_SERVER_SETUP_MODEL_ID, +#endif + +/*****************************************************************************/ +/** Following Section places Generic MODEL Enabled Client IDs ************/ +/*****************************************************************************/ +#ifdef ENABLE_GENERIC_MODEL_CLIENT_ONOFF + GENERIC_MODEL_CLIENT_ONOFF_MODEL_ID, +#endif + +#ifdef ENABLE_GENERIC_MODEL_CLIENT_LEVEL + GENERIC_MODEL_CLIENT_LEVEL_MODEL_ID, +#endif + +#ifdef ENABLE_LIGHT_MODEL_CLIENT_LIGHTNESS + LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID, +#endif + + /*****************************************************************************/ /** End of the SIG Server Model IDs ************/ /*****************************************************************************/ @@ -252,12 +347,34 @@ const MOBLEUINT32 Appli_Vendor_Models[]= 0 /* Default entry, do NOT remove */ }; + +//ALIGN(4) +__attribute__((aligned(4))) const MOBLEUINT16 Appli_CLIENT_Support_SIG_Models[]= +{ + /* Array to define the Models on which subscription and Publication may work + for the Provisioner itself */ + GENERIC_MODEL_SERVER_ONOFF_MODEL_ID, +// GENERIC_MODEL_SERVER_LEVEL_MODEL_ID, +// GENERIC_MODEL_SERVER_DEFAULT_TRANSITION_TIME_MODEL_ID, +// SENSOR_SERVER_MODEL_ID, +// LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID, +// LIGHT_MODEL_SERVER_LC_MODEL_ID, + 0 +}; + + #define APPLI_SIG_MODELS_COUNT ( (sizeof(Appli_SIG_Models) / sizeof(Appli_SIG_Models[0]) ) -1 ) /* Subtracted 1 because of last default entry of 0, since users can comment all models */ #define APPLI_VENDOR_MODELS_COUNT ( ( sizeof(Appli_Vendor_Models) / sizeof(Appli_Vendor_Models[0]) ) -1 ) /* Subtracted 1 because of last default entry of 0, since users can comment all models */ +#define APPLI_NODE_SIG_MODELS_COUNT ( (sizeof(Appli_CLIENT_Support_SIG_Models) / sizeof(Appli_CLIENT_Support_SIG_Models[0]) ) -1 ) +/* Subtracted 1 because of last default entry of 0, since users can comment all models */ + +#define APPLI_NODE_VENDOR_MODELS_COUNT ( ( sizeof(Appli_Vendor_Models) / sizeof(Appli_Vendor_Models[0]) ) -1 ) +/* Subtracted 1 because of last default entry of 0, since users can comment all models */ + /* Private function prototypes -----------------------------------------------*/ #if (LOW_POWER_FEATURE == 0) MOBLE_RESULT BnrgmFrndLpnProcess(void* param); @@ -270,11 +387,41 @@ MOBLE_RESULT BnrgmFrndLpnTranspSegRecvd(void* param); MOBLE_RESULT BnrgmFrndLpnUpdateKeys(void* param); MOBLE_RESULT BnrgmFrndMgmtLpnInit(void* param); #endif /* #if (LOW_POWER_FEATURE == 0) */ + #if (NEIGHBOR_TABLE_SUPPORTED == 0) MOBLE_RESULT BLEMesh_NeighborTableInit(void* param); void BLEMesh_UpdateNeighbors(void* param); #endif /* #if (NEIGHBOR_TABLE_SUPPORTED == 0) */ +#if (PB_ADV_SUPPORTED == 0) +MOBLE_RESULT MoblePBADVInit(void* param); +MOBLE_RESULT MoblePBADVProcessData(void* param); +MOBLE_RESULT MoblePBADVStartProvisioning(void* param); +MOBLE_RESULT MoblePBADVStopProvisioning(void* param); +#endif + +MOBLEUINT8 ApplicationSetNodeSigModelList(void); + +#if (FRIEND_FEATURE == 0) +void BnrgmFrndFnProcess(void* param); +MOBLE_RESULT BnrgmFrndFnProcessFrndClear(void* param); +MOBLE_RESULT BnrgmFrndFnProcessFrndClearConf(void* param); +MOBLE_RESULT BnrgmFrndFnProcessFrndPoll(void* param); +MOBLE_RESULT BnrgmFrndFnProcessFrndRequest(void* param); +MOBLE_RESULT BnrgmFrndFnProcessFrndSubscrListAdd(void* param); +MOBLE_RESULT BnrgmFrndFnProcessFrndSubscrListRem(void* param); +MOBLE_RESULT BnrgmFrndFnSendFrndClear(void* param); +MOBLE_RESULT BnrgmFrndFnSwitchKeys(void* param); +MOBLE_RESULT BnrgmFrndFnUpdateKeys(void* param); +MOBLE_RESULT BnrgmFrndMgmtFnInit(void* param); +MOBLE_RESULT BnrgmFrndMgmtGetFriendshipStatus(void* param); +MOBLEUINT32 BnrgmFrndMgmtGetLpnPollTimeout(void* param); +MOBLE_RESULT BnrgmFrndMgmtGetSubscrStatus(void* param); +MOBLE_RESULT BnrgmFrndMgmtQueLpnPkt(void* param); +void BnrgmFrndMgmtSendSecurityUpdate(void* param); +#endif /* #if (FRIEND_FEATURE == 0) */ + +void* GetModelsResponseBuffer(void); /* Private functions ---------------------------------------------------------*/ @@ -282,9 +429,10 @@ void BLEMesh_UpdateNeighbors(void* param); * @brief ApplicationGetSigModelList: This function provides the list of the * SIG Models to the calling function * @param pModels_sig_ID: Pointer of the array to be filled with SIG Models list +* @param elementIndex: Index of the element for Model List * retval Count of the SIG Model Servers enabled in the Application */ -MOBLEUINT8 ApplicationGetSigModelList(MOBLEUINT16* pModels_sig_ID) +MOBLEUINT8 ApplicationGetSigModelList(MOBLEUINT16* pModels_sig_ID, MOBLEUINT8 elementIndex) { /* Since the SIG Models are 2 bytes, copy 2*size for memcpy */ if (APPLI_SIG_MODELS_COUNT != 0) @@ -294,14 +442,50 @@ MOBLEUINT8 ApplicationGetSigModelList(MOBLEUINT16* pModels_sig_ID) return APPLI_SIG_MODELS_COUNT; } +/** +* @brief ApplicationGetCLIENTSigModelList: This function provides the list of the +* SIG Models to the calling function +* @param pModels_sig_ID: Pointer of the array to be filled with SIG Models list +* @param elementIndex: Index of the element for Model List +* retval Count of the SIG Model Servers enabled in the Application +*/ +MOBLEUINT8 ApplicationGetCLIENTSigModelList(MOBLEUINT16* pModels_sig_ID, MOBLEUINT8 elementIndex) +{ + /* Since the SIG Models are 2 bytes, copy 2*size for memcpy */ + if (APPLI_NODE_SIG_MODELS_COUNT != 0) + { + memcpy(pModels_sig_ID, Appli_CLIENT_Support_SIG_Models, APPLI_NODE_SIG_MODELS_COUNT*2); + } + return APPLI_SIG_MODELS_COUNT; +} + +#ifdef ENABLE_PROVISIONER_FEATURE +/** +* @brief ApplicationGetCLIENTSigModelList: This function provides the list of the +* SIG Models to the calling function +* @param pModels_sig_ID: Pointer of the array to be filled with SIG Models list +* @param elementIndex: Index of the element for Model List +* retval Count of the SIG Model Servers enabled in the Application +*/ +MOBLEUINT8 ApplicationSetNodeSigModelList(void) +{ + /* Since the SIG Models are 2 bytes, copy 2*size for memcpy */ + if (APPLI_SIG_MODELS_COUNT != 0) + { + BLEMeshSetSelfModelList(NumberOfElements); + } + return APPLI_SIG_MODELS_COUNT; +} +#endif /** * @brief ApplicationGetVendorModelList: This function provides the list of the * Vendor Models to the calling function * @param pModels_sig_ID: Pointer of the array to be filled with Vendor Models list +* @param elementIndex: Index of the element for Model List * retval Count of the Vendor Model Servers enabled in the Application */ -MOBLEUINT8 ApplicationGetVendorModelList(MOBLEUINT32* pModels_vendor_ID) +MOBLEUINT8 ApplicationGetVendorModelList(MOBLEUINT32* pModels_vendor_ID, MOBLEUINT8 elementIndex) { /* Since the Vendor Models are 4 bytes, copy 4*size for memcpy */ if (APPLI_VENDOR_MODELS_COUNT != 0) @@ -320,16 +504,16 @@ MOBLEUINT8 ApplicationGetVendorModelList(MOBLEUINT32* pModels_vendor_ID) */ MOBLEBOOL ApplicationChkSigModelActive(MOBLEUINT16 modelID) { - MOBLEUINT8 index; + MOBLEINT8 index = 0; MOBLEBOOL result = MOBLE_FALSE; for(index = 0; index < APPLI_SIG_MODELS_COUNT; index++) { - if ( modelID == Appli_SIG_Models[index] ) - { - result = MOBLE_TRUE; + if ( modelID == Appli_SIG_Models[index] ) + { + result = MOBLE_TRUE; break; - } + } } return result; @@ -360,6 +544,95 @@ MOBLEBOOL ApplicationChkVendorModelActive(MOBLEUINT32 modelID) return result; } + +/** +* @brief GetModel Data buffer to use by the library +* @param none +* retval void* Pointer to the used buffer +*/ +#ifdef STATIC_MEMORY_ALLOCATION_IN_APPLI + +void* GetMemoryDataBuffer(MOBLEUINT8 buffer_type, MOBLEUINT32 u32length) +{ + void* ptr = NULL; + MOBLEUINT32 allocated_len; + + switch (buffer_type) + { + case MESH_MODEL_BUFFER: + case HEALTH_MODEL_NEW_BUFFER: + case HEALTH_MODEL_PUBLISH_BUFFER: + ptr = &aModelsBuff[0]; + allocated_len = sizeof(aModelsBuff); + break; + + case MESH_MODEL_RESPONSE_BUFFER: + case VENDOR_MODEL_WRITE_BUFFER: + case VENDOR_MODEL_WRITE_PUBLISHBUFFER: + case VENDOR_MODEL_RESPONSE_BUFFER: + case GENERIC_MODEL_REPLY_BUFFER: + case GENERIC_MODEL_SENDREMOTE_BUFFER: + case GENERIC_MODEL_SENDDATA_BUFFER: + case CONFIG_MODEL_PUBLISH_BUFFER: + ptr = &aModelsBuff_Response[0]; + allocated_len = sizeof(aModelsBuff_Response); + break; + + case MESH_LOWER_TPT_BUFFER: + ptr = &aLowerTptBuff[0]; + allocated_len = sizeof(aLowerTptBuff); + break; + + case MESH_LOWER_TPT_FN_BUFFER: + ptr = &aLowerTptFnBuff[0]; + allocated_len = sizeof(aLowerTptFnBuff); + break; + + case MESH_LOWER_TPT_APP_BUFFER: + ptr = &aLowerTptAppBuff[0]; + allocated_len = sizeof(aLowerTptAppBuff); + break; + + case PROVISIONER_BUFFER: + case PROVISION_NODE_BUFFER: + ptr = &aProvisionParamBuff[0]; + allocated_len = sizeof(aProvisionParamBuff); + break; + + case ACCESS_APPLI_BUFFER: + ptr = &aAppli_SAR_Buffer[0]; + allocated_len = sizeof(aAppli_SAR_Buffer); + + case MESH_LOWER_TPT_INSEG: + ptr = &aTrans_SegIn_Buffer[0]; + allocated_len = sizeof(aTrans_SegIn_Buffer); + break; + + case MESH_LOWER_TPT_INSEQ0: + ptr = &aTrans_Seq0_Buffer[0]; + allocated_len = sizeof(aTrans_Seq0_Buffer); + break; + + case MESH_LOWER_TPT_OUTMSG: + ptr = &aTrans_Out_Buffer[0]; + allocated_len = sizeof(aTrans_Out_Buffer); + + default: + break; + } + + TRACE_M(TF_MEMORY, "BuffType= %d, RequiredLength=%d, Allocated= %d \r\n", buffer_type, u32length, allocated_len); + if (u32length > allocated_len) + { + TRACE_M(TF_MEMORY, "***<<>> Short buffer Allocated \r\n"); + } + + return ptr; +} + + +#endif + #if (FRIEND_FEATURE == 0) void BnrgmFrndFnProcess(void* param) { @@ -504,10 +777,22 @@ void BLEMesh_UpdateNeighbors(void* param) /* Empty functions to reduce code size in case of PB-ADV functionality not in use */ #if (PB_ADV_SUPPORTED == 0) -MOBLE_RESULT MoblePBADVInit(void* param){return MOBLE_RESULT_SUCCESS;} -MOBLE_RESULT MoblePBADVProcessData(void* param){return MOBLE_RESULT_SUCCESS;} -MOBLE_RESULT MoblePBADVStartProvisioning(void* param){return MOBLE_RESULT_SUCCESS;} -MOBLE_RESULT MoblePBADVStopProvisioning(void* param){return MOBLE_RESULT_SUCCESS;} +MOBLE_RESULT MoblePBADVInit(void* param) +{ + return MOBLE_RESULT_SUCCESS; +} +MOBLE_RESULT MoblePBADVProcessData(void* param) +{ + return MOBLE_RESULT_SUCCESS; +} +MOBLE_RESULT MoblePBADVStartProvisioning(void* param) +{ + return MOBLE_RESULT_SUCCESS; +} +MOBLE_RESULT MoblePBADVStopProvisioning(void* param) +{ + return MOBLE_RESULT_SUCCESS; +} #endif /* PLEASE REFER TO THE .h file for different settings */ diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Src/serial_ctrl.c b/Middlewares/ST/STM32_WPAN/ble/mesh/Src/serial_ctrl.c index b37c7a51b..55c14035c 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/Src/serial_ctrl.c +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/Src/serial_ctrl.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file serial_ctrl.c * @author BLE Mesh Team -* @version V1.10.000 -* @date 15-Jan-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Serial Control file ****************************************************************************** * @attention @@ -82,18 +82,123 @@ MOBLEUINT8 SerialCtrl_GetData(char *rcvdStringBuff, uint16_t rcvdStringSize, MOB * @param rcvdStringSize: length of the input string * @retval void */ +void SerialCtrlVendorRead_Process(char *rcvdStringBuff, uint16_t rcvdStringSize) +{ + MOBLE_ADDRESS peer = 0; /*node adderess of the destination node*/ + MOBLEUINT16 command = 0; /*Opcode command to be executed by the destination node*/ + MOBLEUINT8 datalength = 0; + MOBLEUINT8 elementIndex = 0; /*default element index*/ + MOBLEUINT8 data [10] = {0}; /*buffer to output property variables */ + MOBLE_RESULT result = MOBLE_RESULT_FAIL; + + sscanf(rcvdStringBuff+5, "%4hx %hx ", &peer,&command); + + for(int i = 0; i < 6 ; i++) + { + if(command == Vendor_Opcodes_Table[i]) + { + result = MOBLE_RESULT_SUCCESS; + break; + } + + } + + datalength = SerialCtrl_GetData(rcvdStringBuff, rcvdStringSize, SERIAL_MODEL_DATA_OFFSET, data); + + + if(result) + { + TRACE_I(TF_SERIAL_CTRL,"Invalid Command\r\n"); + return; + } + + else + { + + result = BLEMesh_ReadRemoteData(peer,elementIndex,command, + data, datalength); + if(result == MOBLE_RESULT_SUCCESS) + { + TRACE_I(TF_SERIAL_CTRL,"Command Executed Successfully\r\n"); + } + else + { + TRACE_I(TF_SERIAL_CTRL,"Invalid Opcode Parameter\r\n"); + } + } + +} +void SerialCtrlVendorWrite_Process(char *rcvdStringBuff, uint16_t rcvdStringSize) +{ + MOBLE_ADDRESS peer = 0; /*node adderess of the destination node*/ + MOBLEUINT16 command = 0; /*Opcode command to be executed by the destination node*/ + MOBLEUINT8 elementIndex = 0; /*default element index*/ + MOBLE_RESULT result = MOBLE_RESULT_FAIL; + MOBLEBOOL response = MOBLE_FALSE; + MOBLEUINT8 data_buff[VENDOR_DATA_BYTE]; + MOBLEUINT16 idx=0; + MOBLEUINT8 length; + MOBLEUINT8 j = 1; + + sscanf(rcvdStringBuff+5, "%4hx %hx %hx", &peer,&command,&idx); + + if(command == 0x000E) + { + data_buff[0] = 0x01; // data write sub command; + length = sizeof(data_buff)-idx; + + for(MOBLEUINT8 i=idx;i = 'A' && addr <= 'F') retVal = addr+10-'A'; + else if (addr == ' ') + retVal = addr+10-' '; else return 0xFF; diff --git a/Middlewares/ST/STM32_WPAN/ble/mesh/Src/serial_prvn.c b/Middlewares/ST/STM32_WPAN/ble/mesh/Src/serial_prvn.c index 894bf8ba3..e98188ed7 100644 --- a/Middlewares/ST/STM32_WPAN/ble/mesh/Src/serial_prvn.c +++ b/Middlewares/ST/STM32_WPAN/ble/mesh/Src/serial_prvn.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file serial_prvn.c * @author BLE Mesh Team -* @version V1.11.000 -* @date 25-07-2019 +* @version V1.12.000 +* @date 06-12-2019 * @brief Embedded provisioner Serial Control file ****************************************************************************** * @attention @@ -47,6 +47,9 @@ #include "serial_ctrl.h" #include "mesh_cfg.h" #include "ble_mesh.h" +#include "appli_config_client.h" +#include "serial_prvn.h" +#include "appli_mesh.h" /** @addtogroup BlueNRG_Mesh * @{ @@ -61,12 +64,35 @@ /* Private variables ---------------------------------------------------------*/ static neighbor_params_t NeighborTable[5]; static MOBLEUINT8 NoOfNeighborPresent; - +static MOBLEUINT8 PrvningInProcess = 0; +static MOBLEUINT16 PrvndNodeAddress = 0; +extern MOBLEUINT16 nodeAddressOffset; /* Private function prototypes -----------------------------------------------*/ static MOBLE_RESULT SerialPrvn_ProvisionDevice(char *text); +static MOBLE_RESULT SerialPrvn_UnProvisionDevice(char *text); static MOBLE_RESULT SerialPrvn_ScanDevices(char *text); /* Private functions ---------------------------------------------------------*/ /** +* @brief This function scans and prints unprovisioned devices +* @param unprovDeviceArray: Pointer of an array for filling unprovisioned device UUIDs +* @param noOfUnprovDevices: Pointer to take total count of nearby unprovisioned devices +* @retval MOBLE_RESULT +*/ +__weak MOBLE_RESULT BLEMesh_ScanDevices(neighbor_params_t *unprovDeviceArray, MOBLEUINT8 *noOfUnprovDevices) +{ + return MOBLE_RESULT_NOTIMPL; +} +/** +* @brief This function returns starts the provisioning of one of the devices +* @param unprovDeviceArray: Pointer of an array having unprovisioned device UUIDs +* @param index: Index of the device to be provisioned +* @retval MOBLE_RESULT +*/ +__weak MOBLE_RESULT BLEMesh_ProvisionDevice(neighbor_params_t *unprovDeviceArray, MOBLEUINT16 index) +{ + return MOBLE_RESULT_NOTIMPL; +} +/** * @brief This funcrion is used to parse the string given by the user * @param rcvdStringBuff: buffer to store input string * @param rcvdStringSize: length of the input string @@ -75,16 +101,58 @@ static MOBLE_RESULT SerialPrvn_ScanDevices(char *text); void SerialPrvn_Process(char *rcvdStringBuff, uint16_t rcvdStringSize) { MOBLE_RESULT result; + MOBLEUINT8 prvsnrDevKey[16]; + /* Command to make a devices as Root node which creates Mesh network credentials */ + if (!strncmp(rcvdStringBuff+COMMAND_OFFSET, "ROOT",4)) + { + /* Initializes Mesh network parameters */ + result = BLEMesh_CreateNetwork(prvsnrDevKey); +#ifdef ENABLE_PROVISIONER_FEATURE + Start_SelfConfiguration(); +#endif + } /* Command to scan the unprovisioned devices */ - if (!strncmp(rcvdStringBuff+COMMAND_OFFSET, "SCAN",4)) + else if (!strncmp(rcvdStringBuff+COMMAND_OFFSET, "SCAN",4)) { result = SerialPrvn_ScanDevices(rcvdStringBuff+COMMAND_OFFSET); } /* Command to start the unprovisioned devices */ else if (!strncmp(rcvdStringBuff+COMMAND_OFFSET, "PRVN-",4)) { - result = SerialPrvn_ProvisionDevice(rcvdStringBuff+COMMAND_OFFSET); + if(!PrvningInProcess) + { + result = SerialPrvn_ProvisionDevice(rcvdStringBuff+COMMAND_OFFSET); + } + else + { + BLEMesh_PrintStringCb("Link opened already. Wait.\r\n"); + result = MOBLE_RESULT_FAIL; + } + } + else if (!strncmp(rcvdStringBuff+COMMAND_OFFSET, "UNPV",4)) + { + + result = SerialPrvn_UnProvisionDevice(rcvdStringBuff+COMMAND_OFFSET); + + } + /* Command to start the unprovisioned devices */ + else if (!strncmp(rcvdStringBuff+COMMAND_OFFSET, "RESET",5)) + { + BLEMesh_PrintStringCb("Reseting Board...\r\n"); + NVIC_SystemReset(); + } + /* Command to scan the unprovisioned devices - Used By node only */ + else if (!strncmp(rcvdStringBuff+COMMAND_OFFSET, "NDSCAN",4)) + { + result = BLEMesh_ScanDevices(NeighborTable, &NoOfNeighborPresent); + } + /* Command to start the unprovisioned devices - Used By node only */ + else if (!strncmp(rcvdStringBuff+COMMAND_OFFSET, "NDPRVN-",4)) + { + MOBLEINT16 index = 0; + sscanf(rcvdStringBuff, "PRVN-%hd", &index); + result = BLEMesh_ProvisionDevice(NeighborTable, index); } else { @@ -113,23 +181,55 @@ void SerialPrvn_Process(char *rcvdStringBuff, uint16_t rcvdStringSize) /** * @brief This function returns starts the provisioning of one of the devices -* @param text: recieved array +* @param text: received array * @retval MOBLE_RESULT */ static MOBLE_RESULT SerialPrvn_ProvisionDevice(char *text) { MOBLEINT16 index = 0; + MOBLEINT16 na = 0; MOBLE_RESULT result = MOBLE_RESULT_SUCCESS; - sscanf(text, "PRVN-%hd", &index); - result = BLEMesh_ProvisionRemote(NeighborTable[index].uuid); + sscanf(text, "PRVN-%hd %hd", &index, &na); + if(na>1) + { + nodeAddressOffset = na - 1; + result = BLEMesh_ProvisionRemote(NeighborTable[index].uuid); + } + else + { + result = MOBLE_RESULT_INVALIDARG; + } return result; } +/** +* @brief This function Un-Provision one of the devices +* @param text: received array +* @retval MOBLE_RESULT +*/ +static MOBLE_RESULT SerialPrvn_UnProvisionDevice(char *text) +{ + MOBLEINT16 na = 0; + MOBLE_RESULT result = MOBLE_RESULT_SUCCESS; + + sscanf(text, "UNPV %hd", &na); + if(na>1) + { + result = ConfigClient_NodeReset(na); + } + else + { + result = MOBLE_RESULT_INVALIDARG; + } + + return result; +} + /** * @brief This function scans and prints unprovisioned devices -* @param text: recieved array +* @param text: received array * @retval MOBLE_RESULT */ static MOBLE_RESULT SerialPrvn_ScanDevices(char *text) @@ -153,7 +253,15 @@ static MOBLE_RESULT SerialPrvn_ScanDevices(char *text) } return result; } - +/** +* @brief This funcrion is used to update the status of the provisioning +* @retval void +*/ +void SerialPrvn_ProvisioningStatusUpdateCb(uint8_t flagPrvningInProcess, MOBLEUINT16 nodeAddress) +{ + PrvningInProcess = flagPrvningInProcess; + PrvndNodeAddress = nodeAddress; +} /** * @} */ diff --git a/Middlewares/ST/STM32_WPAN/ble/svc/Src/bvopus_service_stm.c b/Middlewares/ST/STM32_WPAN/ble/svc/Src/bvopus_service_stm.c index bbb630c9c..1818be471 100644 --- a/Middlewares/ST/STM32_WPAN/ble/svc/Src/bvopus_service_stm.c +++ b/Middlewares/ST/STM32_WPAN/ble/svc/Src/bvopus_service_stm.c @@ -836,5 +836,4 @@ uint32_t BluevoiceOPUS_TP_Encapsulate(uint8_t* buffer_out, uint8_t* buffer_in, u } - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_WPAN/ble/svc/Src/mesh.c b/Middlewares/ST/STM32_WPAN/ble/svc/Src/mesh.c index cf3a5a2d3..62ecc4187 100644 --- a/Middlewares/ST/STM32_WPAN/ble/svc/Src/mesh.c +++ b/Middlewares/ST/STM32_WPAN/ble/svc/Src/mesh.c @@ -49,6 +49,8 @@ #include "appli_mesh.h" #include "models_if.h" #include "mesh_cfg.h" +#include "appli_config_client.h" +#include "appli_nvm.h" /* Private typedef -----------------------------------------------------------*/ @@ -66,6 +68,9 @@ const MOBLE_USER_BLE_CB_MAP user_ble_cb = Appli_BleDisableFilterCb }; +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + /* This structure contains Mesh library Initialisation info data */ const Mesh_Initialization_t BLEMeshlib_Init_params = { @@ -97,6 +102,12 @@ extern MOBLEUINT8 bdaddr[]; */ void MESH_Init(void) { + MOBLEUINT8 uuid[16]; + MOBLEUINT8 PrvnDevKeyFlag = 0; +#if PROVISIONER_FEATURE +// MOBLEUINT8 prvsnrDevKey[16]; +#endif + /* Check for valid Board Address */ if (!Appli_CheckBdMacAddr()) { @@ -114,7 +125,7 @@ void MESH_Init(void) /* Initializes BLE-Mesh Library */ if (MOBLE_FAILED(BLEMesh_Init(&BLEMeshlib_Init_params))) { - TRACE_I(TF_INIT,"Could not initialize BlueNRG-Mesh library!\r\n"); + TRACE_I(TF_INIT,"Could not initialize BLE-Mesh library!\r\n"); /* LED continuously blinks if library fails to initialize */ while (1) { @@ -122,10 +133,30 @@ void MESH_Init(void) } } +/* Check if Node is a Provisioner */ +//#if PROVISIONER_FEATURE +// MOBLEUINT8 prvsnrDevKey[16]; +// /* Initializes Mesh network parameters */ +// BluenrgMesh_CreateNetwork(prvsnrDevKey); +// +// /* Following functions help to Configure the Provisioner to default settings*/ +// ApplicationSetNodeSigModelList(); +// AppliConfigClient_SelfPublicationSetDefault(); +// AppliConfigClient_SelfSubscriptionSetDefault(); +// Appli_ConfigClient_SelfDefaultAppKeyBind(); +// +// TRACE_I(TF_PROVISION,"Provisioner node \r\n"); +// TRACE_I(TF_PROVISION,"Provisioner Dev Key:"); +// for(MOBLEUINT8 i=0;i<16;i++) +// { +// TRACE_I(TF_INIT,"[%02x] ",prvsnrDevKey[i]); +// } +// TRACE_I(TF_INIT,"\r\n"); + +//#else /* Checks if the node is already provisioned or not */ if (BLEMesh_IsUnprovisioned() == MOBLE_TRUE) { -// BluenrgMesh_UnprovisionedNodeInfo(&UnprovNodeInfoParams); BLEMesh_InitUnprovisionedNode(); /* Initalizes Unprovisioned node */ TRACE_I(TF_PROVISION,"Unprovisioned device \r\n"); @@ -138,34 +169,52 @@ void MESH_Init(void) { BLEMesh_InitProvisionedNode(); /* Initalizes Provisioned node */ TRACE_I(TF_PROVISION,"Provisioned node \r\n"); + TRACE_I(TF_INIT,"Provisioned Node Address: [%04x] \n\r", BLEMesh_GetAddress()); } - +//#endif /* Initializes the Application */ - Appli_Init(); + /* This function also checks for Power OnOff Cycles + Define the following Macro "ENABLE_UNPROVISIONING_BY_POWER_ONOFF_CYCLE" + to check the Power-OnOff Cycles + 5 Continous cycles of OnOff with Ontime <2 sec will cause unprovisioning + */ + Appli_Init(&PrvnDevKeyFlag); +#if PROVISIONER_FEATURE +// AppliNvm_saveProvisionerDevKey(&prvsnrDevKey[0], +// sizeof(prvsnrDevKey), +// &PrvnDevKeyFlag); +#endif /* Check to manually unprovision the board */ Appli_CheckForUnprovision(); /* Set attention timer callback */ BLEMesh_SetAttentionTimerCallback(Appli_BleAttentionTimerCb); + /* Set uuid for the board*/ + Appli_BleSetUUIDCb(uuid); + /* Prints the MAC Address of the board */ TRACE_I(TF_INIT,"BLE-Mesh Lighting Demo v%s\n\r", BLE_MESH_APPLICATION_VERSION); TRACE_I(TF_INIT,"BLE-Mesh Library v%s\n\r", BLEMesh_GetLibraryVersion()); TRACE_I(TF_INIT,"BD_MAC Address = [%02x]:[%02x]:[%02x]:[%02x]:[%02x]:[%02x] \n\r", bdaddr[5],bdaddr[4],bdaddr[3],bdaddr[2],bdaddr[1],bdaddr[0]); - + TRACE_I(TF_INIT,"UUID Address = "); + for(MOBLEUINT8 i=0;i<16;i++) + { + TRACE_I(TF_INIT,"[%02x] ",uuid[i]); + } + TRACE_I(TF_INIT,"\r\n"); /* Models intialization */ BLEMesh_ModelsInit(); + /* Turn on Yellow LED */ -#if 0 #if (LOW_POWER_FEATURE == 1) - SdkEvalLedOn(LED1); +// BSP_LED_On(LED_RED); #endif #ifdef CUSTOM_BOARD_PWM_SELECTION Light_UpdatePWMValue((MOBLEUINT8)DEFAULT_STATE); #endif -#endif } /************************ (C) COPYRIGHT 2019 STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/hw.h b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/hw.h index 101029647..591215a38 100644 --- a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/hw.h +++ b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/hw.h @@ -76,13 +76,13 @@ extern "C" { void HW_IPCC_ZIGBEE_Init( void ); - void HW_IPCC_ZIGBEE_SendAppliCmd(void); - void HW_IPCC_ZIGBEE_AppliCmdNotification(void); + void HW_IPCC_ZIGBEE_SendM4RequestToM0(void); /* M4 Request to M0 */ + void HW_IPCC_ZIGBEE_RecvAppliAckFromM0(void); /* Request ACK from M0 */ - void HW_IPCC_ZIGBEE_AppliAsyncEvtNotification(void); - void HW_IPCC_ZIGBEE_SendAppliCmdAck(void); - void HW_IPCC_ZIGBEE_AppliAsyncLoggingNotification( void ); - void HW_IPCC_ZIGBEE_SendLoggingAck(void); + void HW_IPCC_ZIGBEE_RecvM0NotifyToM4(void); /* M0 Notify to M4 */ + void HW_IPCC_ZIGBEE_SendM4AckToM0Notify(void); /* Notify ACK from M4 */ + void HW_IPCC_ZIGBEE_RecvM0RequestToM4(void); /* M0 Request to M4 */ + void HW_IPCC_ZIGBEE_SendM4AckToM0Request(void); /* Request ACK from M4 */ #ifdef __cplusplus diff --git a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/shci/shci.c b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/shci/shci.c index 964109840..2ea82a67f 100644 --- a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/shci/shci.c +++ b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/shci/shci.c @@ -315,6 +315,7 @@ SHCI_CmdStatus_t SHCI_C2_ZIGBEE_Init( void ) return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]); } + SHCI_CmdStatus_t SHCI_C2_DEBUG_Init( SHCI_C2_DEBUG_Init_Cmd_Packet_t *pCmdPacket ) { /** @@ -494,6 +495,27 @@ SHCI_CmdStatus_t SHCI_C2_ExtpaConfig(uint32_t gpio_port, uint16_t gpio_pin_numbe return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]); } +SHCI_CmdStatus_t SHCI_C2_SetFlashActivityControl(SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t Source) +{ + /** + * TL_BLEEVT_CS_BUFFER_SIZE is 15 bytes so it is large enough to hold the 1 byte of command parameter + * Buffer is large enough to hold command complete without payload + */ + uint8_t local_buffer[TL_BLEEVT_CS_BUFFER_SIZE]; + TL_EvtPacket_t * p_rsp; + + p_rsp = (TL_EvtPacket_t *)local_buffer; + + local_buffer[0] = (uint8_t)Source; + + shci_send( SHCI_OPCODE_C2_SET_FLASH_ACTIVITY_CONTROL, + 1, + local_buffer, + p_rsp ); + + return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]); +} + /** * Local System COMMAND * These commands are NOT sent to the CPU2 diff --git a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/shci/shci.h b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/shci/shci.h index 308c1d143..d804057f8 100644 --- a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/shci/shci.h +++ b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/shci/shci.h @@ -137,7 +137,8 @@ extern "C" { SHCI_OCF_C2_REINIT, SHCI_OCF_C2_ZIGBEE_INIT, SHCI_OCF_C2_LLD_TESTS_INIT, - SHCI_OCF_C2_EXTPA_CONFIG + SHCI_OCF_C2_EXTPA_CONFIG, + SHCI_OCF_C2_SET_FLASH_ACTIVITY_CONTROL } SHCI_OCF_t; #define SHCI_OPCODE_C2_FUS_GET_STATE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_GET_STATE) @@ -296,6 +297,20 @@ extern "C" { #define SHCI_OPCODE_C2_DEBUG_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_DEBUG_INIT) /** Command parameters */ + typedef PACKED_STRUCT + { + uint8_t thread_config; + uint8_t ble_config; + uint8_t mac_802_15_4_config; + uint8_t zigbee_config; + } SHCI_C2_DEBUG_TracesConfig_t; + + typedef PACKED_STRUCT + { + uint8_t ble_dtb_cfg; + uint8_t reserved[3]; + } SHCI_C2_DEBUG_GeneralConfig_t; + typedef PACKED_STRUCT{ uint8_t *pGpioConfig; uint8_t *pTracesConfig; @@ -375,6 +390,16 @@ extern "C" { /** No response parameters*/ +#define SHCI_OPCODE_C2_SET_FLASH_ACTIVITY_CONTROL (( SHCI_OGF << 10) + SHCI_OCF_C2_SET_FLASH_ACTIVITY_CONTROL) + /** Command parameters */ + typedef enum + { + FLASH_ACTIVITY_CONTROL_PES, + FLASH_ACTIVITY_CONTROL_SEM7, + }SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t; + + /** No response parameters*/ + /* Exported type --------------------------------------------------------*/ typedef MB_WirelessFwInfoTable_t SHCI_WirelessFwInfoTable_t; @@ -427,8 +452,9 @@ typedef MB_WirelessFwInfoTable_t SHCI_WirelessFwInfoTable_t; #define INFO_STACK_TYPE_MASK 0x000000ff #define INFO_STACK_TYPE_NONE 0 -#define INFO_STACK_TYPE_BLE_STANDARD 0x1 -#define INFO_STACK_TYPE_BLE_HCI 0x2 +#define INFO_STACK_TYPE_BLE_STANDARD 0x01 +#define INFO_STACK_TYPE_BLE_HCI 0x02 +#define INFO_STACK_TYPE_BLE_LIGHT 0x03 #define INFO_STACK_TYPE_THREAD_FTD 0x10 #define INFO_STACK_TYPE_THREAD_MTD 0x11 #define INFO_STACK_TYPE_ZIGBEE 0x30 @@ -437,6 +463,7 @@ typedef MB_WirelessFwInfoTable_t SHCI_WirelessFwInfoTable_t; #define INFO_STACK_TYPE_802154_LLD_TESTS 0x60 #define INFO_STACK_TYPE_802154_PHY_VALID 0x61 #define INFO_STACK_TYPE_BLE_PHY_VALID 0x62 +#define INFO_STACK_TYPE_BLE_LLD_TESTS 0x63 #define INFO_STACK_TYPE_BLE_ZIGBEE_FFD_STATIC 0x70 typedef struct { @@ -706,6 +733,18 @@ typedef struct { */ SHCI_CmdStatus_t SHCI_C2_ExtpaConfig(uint32_t gpio_port, uint16_t gpio_pin_number, uint8_t gpio_polarity, uint8_t gpio_status); + /** + * SHCI_C2_SetFlashActivityControl + * @brief Set the mechanism to be used on CPU2 to prevent the CPU1 to either write or erase in flash + * + * @param Source: It can be one of the following list + * - FLASH_ACTIVITY_CONTROL_PES : The CPU2 set the PES bit to prevent the CPU1 to either read or write in flash + * - FLASH_ACTIVITY_CONTROL_SEM7 : The CPU2 gets the semaphore 7 to prevent the CPU1 to either read or write in flash. + * This requires the CPU1 to first get semaphore 7 before erasing or writing the flash. + * + * @retval Status + */ + SHCI_CmdStatus_t SHCI_C2_SetFlashActivityControl(SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t Source); #ifdef __cplusplus } diff --git a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/hci_tl.c b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/hci_tl.c index 6012bf4d8..1836732e9 100644 --- a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/hci_tl.c +++ b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/hci_tl.c @@ -28,6 +28,12 @@ /* Private typedef -----------------------------------------------------------*/ +typedef enum +{ + HCI_TL_CMD_RESP_RELEASE, + HCI_TL_CMD_RESP_WAIT, +} HCI_TL_CmdRespStatus_t; + /* Private defines -----------------------------------------------------------*/ /** @@ -53,6 +59,8 @@ static tHciContext hciContext; static tListNode HciCmdEventQueue; static void (* StatusNotCallBackFunction) (HCI_TL_CmdStatus_t status); +static volatile HCI_TL_CmdRespStatus_t CmdRspStatusFlag; + /* Private function prototypes -----------------------------------------------*/ static void NotifyCmdStatus(HCI_TL_CmdStatus_t hcicmdstatus); static void SendCmd(uint16_t opcode, uint8_t plen, void *param); @@ -280,3 +288,23 @@ static void TlEvtReceived(TL_EvtPacket_t *hcievt) return; } + +/* Weak implementation ----------------------------------------------------------------*/ +__WEAK void hci_cmd_resp_wait(uint32_t timeout) +{ + (void)timeout; + + CmdRspStatusFlag = HCI_TL_CMD_RESP_WAIT; + while(CmdRspStatusFlag != HCI_TL_CMD_RESP_RELEASE); + + return; +} + +__WEAK void hci_cmd_resp_release(uint32_t flag) +{ + (void)flag; + + CmdRspStatusFlag = HCI_TL_CMD_RESP_RELEASE; + + return; +} diff --git a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/hci_tl.h b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/hci_tl.h index 0783eeea9..7eda1df82 100644 --- a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/hci_tl.h +++ b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/hci_tl.h @@ -87,9 +87,11 @@ typedef struct void hci_register_io_bus(tHciIO* fops); /** - * @brief Interrupt service routine that must be called when the BLE core - * reports a packet received or an event to the host through the - * related IPCC RX interrupt line. + * @brief This callback is called from either + * - IPCC RX interrupt context + * - hci_user_evt_proc() context. + * - hci_resume_flow() context + * It requests hci_user_evt_proc() to be executed. * * @param pdata Packet or event pointer * @retval None @@ -107,12 +109,13 @@ void hci_resume_flow(void); /** - * @brief This function is called when an ACI/HCI command is sent and the response - * is waited from the BLE core. - * The application shall implement a mechanism to not return from this function - * until the waited event is received. - * This is notified to the application with hci_cmd_resp_release(). + * @brief This function is called when an ACI/HCI command is sent to the CPU2 and the response is waited. * It is called from the same context the HCI command has been sent. + * It shall not return until the command response notified by hci_cmd_resp_release() is received. + * A weak implementation is available in hci_tl.c based on polling mechanism + * The user may re-implement this function in the application to improve performance : + * - It may use UTIL_SEQ_WaitEvt() API when using the Sequencer + * - It may use a semaphore when using cmsis_os interface * * @param timeout: Waiting timeout * @retval None @@ -120,8 +123,11 @@ void hci_resume_flow(void); void hci_cmd_resp_wait(uint32_t timeout); /** - * @brief This function is called when an ACI/HCI command is sent and the response is - * received from the BLE core. + * @brief This function is called when an ACI/HCI command response is received from the CPU2. + * A weak implementation is available in hci_tl.c based on polling mechanism + * The user may re-implement this function in the application to improve performance : + * - It may use UTIL_SEQ_SetEvt() API when using the Sequencer + * - It may use a semaphore when using cmsis_os interface * * @param flag: Release flag * @retval None @@ -142,7 +148,7 @@ void hci_cmd_resp_release(uint32_t flag); */ /** - * @brief This process shall be called by the scheduler each time it is requested with TL_BLE_HCI_UserEvtProcReq() + * @brief This process shall be called by the scheduler each time it is requested with hci_notify_asynch_evt() * This process may send an ACI/HCI command when the svc_ctl.c module is used * * @param None diff --git a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/mbox_def.h b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/mbox_def.h index efd22fc08..939d51797 100644 --- a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/mbox_def.h +++ b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/mbox_def.h @@ -104,7 +104,7 @@ extern "C" { { uint8_t *notifM0toM4_buffer; uint8_t *appliCmdM4toM0_buffer; - uint8_t *loggingM0toM4_buffer; + uint8_t *requestM0toM4_buffer; } MB_ZigbeeTable_t; /** * msg @@ -233,7 +233,7 @@ extern "C" { #define HW_IPCC_TRACES_CHANNEL LL_IPCC_CHANNEL_4 #define HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL LL_IPCC_CHANNEL_5 #define HW_IPCC_LLDTESTS_CLI_RSP_CHANNEL LL_IPCC_CHANNEL_5 -#define HW_IPCC_ZIGBEE_APPLI_LOGGING_CHANNEL LL_IPCC_CHANNEL_5 +#define HW_IPCC_ZIGBEE_M0_REQUEST_CHANNEL LL_IPCC_CHANNEL_5 #endif /*__MBOX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/shci_tl.c b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/shci_tl.c index 5c663711d..7e8b55724 100644 --- a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/shci_tl.c +++ b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/shci_tl.c @@ -26,6 +26,12 @@ /* Private typedef -----------------------------------------------------------*/ +typedef enum +{ + SHCI_TL_CMD_RESP_RELEASE, + SHCI_TL_CMD_RESP_WAIT, +} SHCI_TL_CmdRespStatus_t; + /* Private defines -----------------------------------------------------------*/ /** * The default System HCI layer timeout is set to 33s @@ -49,6 +55,8 @@ PLACE_IN_SECTION("SYSTEM_DRIVER_CONTEXT") SHCI_TL_UserEventFlowStatus_t SHCI_TL_ static tSHciContext shciContext; static void (* StatusNotCallBackFunction) (SHCI_TL_CmdStatus_t status); +static volatile SHCI_TL_CmdRespStatus_t CmdRspStatusFlag; + /* Private function prototypes -----------------------------------------------*/ static void Cmd_SetStatus(SHCI_TL_CmdStatus_t shcicmdstatus); static void TlCmdEvtReceived(TL_EvtPacket_t *shcievt); @@ -226,3 +234,24 @@ static void TlUserEvtReceived(TL_EvtPacket_t *shcievt) return; } +/* Weak implementation ----------------------------------------------------------------*/ +__WEAK void shci_cmd_resp_wait(uint32_t timeout) +{ + (void)timeout; + + CmdRspStatusFlag = SHCI_TL_CMD_RESP_WAIT; + while(CmdRspStatusFlag != SHCI_TL_CMD_RESP_RELEASE); + + return; +} + +__WEAK void shci_cmd_resp_release(uint32_t flag) +{ + (void)flag; + + CmdRspStatusFlag = SHCI_TL_CMD_RESP_RELEASE; + + return; +} + + diff --git a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/shci_tl.h b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/shci_tl.h index 3e4b2a271..3fbc492f1 100644 --- a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/shci_tl.h +++ b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/shci_tl.h @@ -120,12 +120,13 @@ void shci_resume_flow(void); /** - * @brief This function is called when an System HCO Command is sent and the response - * is waited from the CPU2. - * The application shall implement a mechanism to not return from this function - * until the waited event is received. - * This is notified to the application with shci_cmd_resp_release(). + * @brief This function is called when an System HCI Command is sent to the CPU2 and the response is waited. * It is called from the same context the System HCI command has been sent. + * It shall not return until the command response notified by shci_cmd_resp_release() is received. + * A weak implementation is available in shci_tl.c based on polling mechanism + * The user may re-implement this function in the application to improve performance : + * - It may use UTIL_SEQ_WaitEvt() API when using the Sequencer + * - It may use a semaphore when using cmsis_os interface * * @param timeout: Waiting timeout * @retval None @@ -133,8 +134,12 @@ void shci_resume_flow(void); void shci_cmd_resp_wait(uint32_t timeout); /** - * @brief This function is called when an System HCI command is sent and the response is - * received from the CPU2. + * @brief This function is called when an System HCI command is received from the CPU2. + * A weak implementation is available in shci_tl.c based on polling mechanism + * The user may re-implement this function in the application to improve performance : + * - It may use UTIL_SEQ_SetEvt() API when using the Sequencer + * - It may use a semaphore when using cmsis_os interface + * * * @param flag: Release flag * @retval None diff --git a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl.h b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl.h index a5a395ac2..b11658914 100644 --- a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl.h +++ b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl.h @@ -202,7 +202,7 @@ typedef struct { uint8_t *p_ZigbeeOtCmdRspBuffer; uint8_t *p_ZigbeeNotAckBuffer; - uint8_t *p_ZigbeeLoggingBuffer; + uint8_t *p_ZigbeeNotifRequestBuffer; } TL_ZIGBEE_Config_t; /** @@ -299,12 +299,12 @@ void TL_MAC_802_15_4_SendAck ( void ); * ZIGBEE ******************************************************************************/ void TL_ZIGBEE_Init( TL_ZIGBEE_Config_t *p_Config ); -void TL_ZIGBEE_SendAppliCmdToM0( void ); -void TL_ZIGBEE_SendAckAfterAppliNotifFromM0 ( void ); +void TL_ZIGBEE_SendM4RequestToM0( void ); +void TL_ZIGBEE_SendM4AckToM0Notify ( void ); void TL_ZIGBEE_NotReceived( TL_EvtPacket_t * Notbuffer ); void TL_ZIGBEE_CmdEvtReceived( TL_EvtPacket_t * Otbuffer ); -void TL_ZIGBEE_LoggingReceived(TL_EvtPacket_t * Otbuffer ); -void TL_ZIGBEE_SendAckAfterAppliLoggingFromM0 ( void ); +void TL_ZIGBEE_M0RequestReceived(TL_EvtPacket_t * Otbuffer ); +void TL_ZIGBEE_SendM4AckToM0Request(void); #ifdef __cplusplus } /* extern "C" */ diff --git a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl_mbox.c b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl_mbox.c index 0b5d1f5dd..8a97b0038 100644 --- a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl_mbox.c +++ b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl_mbox.c @@ -122,7 +122,7 @@ int32_t TL_BLE_SendCmd( uint8_t* buffer, uint16_t size ) { (void)(buffer); (void)(size); - + ((TL_CmdPacket_t*)(TL_RefTable.p_ble_table->pcmd_buffer))->cmdserial.type = TL_BLECMD_PKT_TYPE; HW_IPCC_BLE_SendCmd(); @@ -148,7 +148,7 @@ int32_t TL_BLE_SendAclData( uint8_t* buffer, uint16_t size ) { (void)(buffer); (void)(size); - + ((TL_AclDataPacket_t *)(TL_RefTable.p_ble_table->phci_acl_data_buffer))->AclDataSerial.type = TL_ACL_DATA_PKT_TYPE; HW_IPCC_BLE_SendAclData(); @@ -410,68 +410,68 @@ __WEAK void TL_MAC_802_15_4_NotReceived( TL_EvtPacket_t * Notbuffer ){}; ******************************************************************************/ void TL_ZIGBEE_Init( TL_ZIGBEE_Config_t *p_Config ) { - MB_ZigbeeTable_t * p_zigbee_table; p_zigbee_table = TL_RefTable.p_zigbee_table; p_zigbee_table->appliCmdM4toM0_buffer = p_Config->p_ZigbeeOtCmdRspBuffer; p_zigbee_table->notifM0toM4_buffer = p_Config->p_ZigbeeNotAckBuffer; - p_zigbee_table->loggingM0toM4_buffer = p_Config->p_ZigbeeLoggingBuffer; + p_zigbee_table->requestM0toM4_buffer = p_Config->p_ZigbeeNotifRequestBuffer; HW_IPCC_ZIGBEE_Init(); - return; + return; } -void TL_ZIGBEE_SendAppliCmdToM0( void ) +/* Zigbee M4 to M0 Request */ +void TL_ZIGBEE_SendM4RequestToM0( void ) { ((TL_CmdPacket_t *)(TL_RefTable.p_zigbee_table->appliCmdM4toM0_buffer))->cmdserial.type = TL_OTCMD_PKT_TYPE; - HW_IPCC_ZIGBEE_SendAppliCmd(); + HW_IPCC_ZIGBEE_SendM4RequestToM0(); return; } -/* Send an ACK to the M0 */ -void TL_ZIGBEE_SendAckAfterAppliNotifFromM0 ( void ) +/* Used to receive an ACK from the M0 */ +void HW_IPCC_ZIGBEE_RecvAppliAckFromM0(void) { - ((TL_CmdPacket_t *)(TL_RefTable.p_zigbee_table->notifM0toM4_buffer))->cmdserial.type = TL_OTACK_PKT_TYPE; - - HW_IPCC_ZIGBEE_SendAppliCmdAck(); + TL_ZIGBEE_CmdEvtReceived( (TL_EvtPacket_t*)(TL_RefTable.p_zigbee_table->appliCmdM4toM0_buffer) ); return; } -/* Used to receive an ACK from the M0 */ -void HW_IPCC_ZIGBEE_AppliCmdNotification(void) +/* Zigbee notification from M0 to M4 */ +void HW_IPCC_ZIGBEE_RecvM0NotifyToM4( void ) { - TL_ZIGBEE_CmdEvtReceived( (TL_EvtPacket_t*)(TL_RefTable.p_zigbee_table->appliCmdM4toM0_buffer) ); + TL_ZIGBEE_NotReceived( (TL_EvtPacket_t*)(TL_RefTable.p_zigbee_table->notifM0toM4_buffer) ); return; } -/* Zigbee callback */ -void HW_IPCC_ZIGBEE_AppliAsyncEvtNotification( void ) +/* Send an ACK to the M0 for a Notification */ +void TL_ZIGBEE_SendM4AckToM0Notify ( void ) { - TL_ZIGBEE_NotReceived( (TL_EvtPacket_t*)(TL_RefTable.p_zigbee_table->notifM0toM4_buffer) ); + ((TL_CmdPacket_t *)(TL_RefTable.p_zigbee_table->notifM0toM4_buffer))->cmdserial.type = TL_OTACK_PKT_TYPE; + + HW_IPCC_ZIGBEE_SendM4AckToM0Notify(); return; } -/* Zigbee logging */ -void HW_IPCC_ZIGBEE_AppliAsyncLoggingNotification( void ) +/* Zigbee M0 to M4 Request */ +void HW_IPCC_ZIGBEE_RecvM0RequestToM4( void ) { - TL_ZIGBEE_LoggingReceived( (TL_EvtPacket_t*)(TL_RefTable.p_zigbee_table->loggingM0toM4_buffer) ); + TL_ZIGBEE_M0RequestReceived( (TL_EvtPacket_t*)(TL_RefTable.p_zigbee_table->requestM0toM4_buffer) ); return; } -/* Send a Logging ACK to the M0 */ -void TL_ZIGBEE_SendAckAfterAppliLoggingFromM0 ( void ) +/* Send an ACK to the M0 for a Request */ +void TL_ZIGBEE_SendM4AckToM0Request(void) { - ((TL_CmdPacket_t *)(TL_RefTable.p_zigbee_table->loggingM0toM4_buffer))->cmdserial.type = TL_OTACK_PKT_TYPE; + ((TL_CmdPacket_t *)(TL_RefTable.p_zigbee_table->requestM0toM4_buffer))->cmdserial.type = TL_OTACK_PKT_TYPE; - HW_IPCC_ZIGBEE_SendLoggingAck(); + HW_IPCC_ZIGBEE_SendM4AckToM0Request(); return; } diff --git a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl_zigbee_hci.c b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl_zigbee_hci.c index c5b6572e5..4130b3b97 100644 --- a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl_zigbee_hci.c +++ b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl_zigbee_hci.c @@ -51,4 +51,4 @@ __weak void ZIGBEE_CmdTransfer(void){return;} __weak Zigbee_Cmd_Request_t* ZIGBEE_Get_OTCmdPayloadBuffer(void){return 0;} __weak Zigbee_Cmd_Request_t* ZIGBEE_Get_OTCmdRspPayloadBuffer(void){return 0;} __weak Zigbee_Cmd_Request_t* ZIGBEE_Get_NotificationPayloadBuffer(void){return 0;} -__weak Zigbee_Cmd_Request_t* ZIGBEE_Get_LoggingPayloadBuffer(void){return 0;} +__weak Zigbee_Cmd_Request_t* ZIGBEE_Get_M0RequestPayloadBuffer(void){return 0;} diff --git a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl_zigbee_hci.h b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl_zigbee_hci.h index 9938e5598..6d239a2d4 100644 --- a/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl_zigbee_hci.h +++ b/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl_zigbee_hci.h @@ -34,7 +34,7 @@ void ZIGBEE_CmdTransfer(void); Zigbee_Cmd_Request_t* ZIGBEE_Get_OTCmdPayloadBuffer(void); Zigbee_Cmd_Request_t* ZIGBEE_Get_OTCmdRspPayloadBuffer(void); Zigbee_Cmd_Request_t* ZIGBEE_Get_NotificationPayloadBuffer(void); -Zigbee_Cmd_Request_t * ZIGBEE_Get_LoggingPayloadBuffer(void); +Zigbee_Cmd_Request_t* ZIGBEE_Get_M0RequestPayloadBuffer(void); /* Exported defines -----------------------------------------------------------*/ diff --git a/Middlewares/ST/STM32_WPAN/mac_802_15_4/core/src/mac_802_15_4_core_wb.c b/Middlewares/ST/STM32_WPAN/mac_802_15_4/core/src/mac_802_15_4_core_wb.c index bfcb790e9..47300c38e 100644 --- a/Middlewares/ST/STM32_WPAN/mac_802_15_4/core/src/mac_802_15_4_core_wb.c +++ b/Middlewares/ST/STM32_WPAN/mac_802_15_4/core/src/mac_802_15_4_core_wb.c @@ -27,9 +27,6 @@ #include "802_15_4_mac_sap.h" #include "802_15_4_mac_core.h" -#include "dbg_trace.h" -#include "stm_logging.h" - #include "tl.h" #include "tl_mac_802_15_4.h" diff --git a/Middlewares/ST/STM32_WPAN/zigbee/core/inc/stm32wbxx_core_interface_def.h b/Middlewares/ST/STM32_WPAN/zigbee/core/inc/stm32wbxx_core_interface_def.h index 276ac0107..dae2a14c3 100644 --- a/Middlewares/ST/STM32_WPAN/zigbee/core/inc/stm32wbxx_core_interface_def.h +++ b/Middlewares/ST/STM32_WPAN/zigbee/core/inc/stm32wbxx_core_interface_def.h @@ -51,9 +51,10 @@ typedef enum { MSG_M4TOM0_WPAN_GET_UINT32, /* wpan_get_uint32 */ MSG_M4TOM0_WPAN_GET_UINT64, /* wpan_get_uint64 */ - /* ZbMalloc / ZbFree */ - MSG_M0TOM4_ZB_MALLOC, - MSG_M0TOM4_ZB_FREE, + /* M0 Request (Separate IPCC Channel) */ + MSG_M0TOM4_ZB_LOGGING, /* Zigbee stack logging (configured by ZbSetLogging) */ + MSG_M0TOM4_ZB_MALLOC, /* ZbMalloc */ + MSG_M0TOM4_ZB_FREE, /* ZbFree */ /* Stack Init / Destroy */ MSG_M4TOM0_ZB_INIT, /* ZbInit */ @@ -114,6 +115,7 @@ typedef enum { MSG_M4TOM0_BDB_GET_REQ = 0x0040, /* ZbBdbGetReq */ MSG_M4TOM0_BDB_SET_REQ, /* ZbBdbSetReq */ MSG_M4TOM0_BDB_SET_EP_STATUS, /* ZbBdbSetEndpointStatus */ + MSG_M4TOM0_BDB_GET_EP_STATUS, /* ZbBdbGetEndpointStatus */ /* Reserved to 0x004f for Future Use */ /* ZDO Commands */ @@ -337,7 +339,7 @@ typedef enum { } Error_Interface_Id_Enum_t; HAL_StatusTypeDef Zigbee_CallBackProcessing(void); -HAL_StatusTypeDef Zigbee_LoggingProcessing(void); +HAL_StatusTypeDef Zigbee_M0RequestProcessing(void); #ifdef __cplusplus } /* extern "C" */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/core/src/zigbee_core_wb.c b/Middlewares/ST/STM32_WPAN/zigbee/core/src/zigbee_core_wb.c index 8f0c2be5b..67cffe801 100644 --- a/Middlewares/ST/STM32_WPAN/zigbee/core/src/zigbee_core_wb.c +++ b/Middlewares/ST/STM32_WPAN/zigbee/core/src/zigbee_core_wb.c @@ -45,7 +45,7 @@ #endif /* ZbTimerAlloc() needs ZbHeapAlloc */ -/* FIXME - remove this dependancy? */ +/* EXEGIN - remove this dependancy? */ void * zb_heap_alloc(struct ZigBeeT *zb, size_t sz, const char *funcname, unsigned int linenum); void zb_heap_free(struct ZigBeeT *zb, void *ptr, const char *funcname, unsigned int linenum); #if defined(CONFIG_ZB_MEMORY_DEBUG) || defined(CONFIG_ZB_MEMPOOL_HISTORY) @@ -107,6 +107,7 @@ const struct ZbApsAddrT *ZbApsAddrBinding = &sendToBinding; struct zb_ipc_m4_cb_info { void *callback; void *arg; + bool zcl_recv_multi_rsp; }; /* Single static callback for persistent data notifications */ @@ -140,17 +141,17 @@ zb_ipc_m4_memcpy2(void *dst, void *src, unsigned int len) { unsigned int i; - for (i=0; iarg = arg; } return info; -} /* zb_ipc_m4_cb_info_alloc */ +} static void zb_ipc_m4_cb_info_free(struct zb_ipc_m4_cb_info *info) { free(info); -} /* zb_ipc_m4_cb_info_free */ +} static uint32_t zb_ipc_m4_get_retval(void) @@ -196,7 +197,7 @@ zb_ipc_m4_get_retval(void) assert(ipcc_req->Size == 1); zb_ipc_m4_memcpy2(&retval, &ipcc_req->Data[0], 4); return retval; -} /* zb_ipc_m4_get_retval */ +} bool wpan_set_uint32(struct WpanPublicT *publicPtr, enum mcp_attr_id attrId, uint32_t value, uint16_t index) @@ -213,19 +214,19 @@ wpan_set_uint32(struct WpanPublicT *publicPtr, enum mcp_attr_id attrId, uint32_t ipcc_req->Data[2] = (uint32_t)index; ZIGBEE_CmdTransfer(); return zb_ipc_m4_get_retval() != 0U ? true : false; -} /* wpan_set_uint16 */ +} bool wpan_set_uint16(struct WpanPublicT *publicPtr, enum mcp_attr_id attrId, uint16_t value, uint16_t index) { return wpan_set_uint32(publicPtr, attrId, (uint32_t)value, index); -} /* wpan_set_uint16 */ +} bool wpan_set_uint8(struct WpanPublicT *publicPtr, enum mcp_attr_id attrId, uint8_t value, uint16_t index) { return wpan_set_uint32(publicPtr, attrId, (uint32_t)value, index); -} /* wpan_set_uint8 */ +} bool wpan_get_uint32(struct WpanPublicT *publicPtr, enum mcp_attr_id attrId, uint32_t *value, uint16_t index) @@ -242,7 +243,7 @@ wpan_get_uint32(struct WpanPublicT *publicPtr, enum mcp_attr_id attrId, uint32_t ipcc_req->Data[2] = (uint32_t)index; ZIGBEE_CmdTransfer(); return zb_ipc_m4_get_retval() != 0U ? true : false; -} /* wpan_get_uint32 */ +} bool wpan_get_uint64(struct WpanPublicT *publicPtr, enum mcp_attr_id attrId, uint64_t *value, uint16_t index) @@ -259,13 +260,13 @@ wpan_get_uint64(struct WpanPublicT *publicPtr, enum mcp_attr_id attrId, uint64_t ipcc_req->Data[2] = (uint32_t)index; ZIGBEE_CmdTransfer(); return zb_ipc_m4_get_retval() != 0U ? true : false; -} /* wpan_get_uint64 */ +} unsigned int ZbHeapMaxAlloc(void) { return ZB_HEAP_MAX_ALLOC; -} /* ZbHeapMaxAlloc */ +} struct ZigBeeT * ZbInit(uint64_t extAddr, ZbInitTblSizesT *tblSizes, ZbInitSetLoggingT *setLogging) @@ -289,7 +290,7 @@ ZbInit(uint64_t extAddr, ZbInitTblSizesT *tblSizes, ZbInitSetLoggingT *setLoggin zb_ipc_globals.log_mask = setLogging->mask; } return zb_ipc_globals.zb; -} /* ZbInit */ +} void ZbDestroy(struct ZigBeeT *zb) @@ -305,7 +306,7 @@ ZbDestroy(struct ZigBeeT *zb) ipcc_req->Size = 0; ZIGBEE_CmdTransfer(); zb_ipc_globals.zb = NULL; -} /* ZbDestroy */ +} void ZbSetLogging(struct ZigBeeT *zb, uint32_t mask, @@ -325,7 +326,7 @@ ZbSetLogging(struct ZigBeeT *zb, uint32_t mask, ZIGBEE_CmdTransfer(); /* Save the log mask */ zb_ipc_globals.log_mask = mask; -} /* ZbSetLogging */ +} void ZbGetLogging(struct ZigBeeT *zb, uint32_t *mask, @@ -337,7 +338,7 @@ ZbGetLogging(struct ZigBeeT *zb, uint32_t *mask, if (func != NULL) { *func = NULL; } -} /* ZbGetLogging */ +} uint64_t ZbExtendedAddress(struct ZigBeeT *zb) @@ -354,7 +355,7 @@ ZbExtendedAddress(struct ZigBeeT *zb) assert(ipcc_req->Size == 2); zb_ipc_m4_memcpy2(&ext_addr, &ipcc_req->Data, 8); return ext_addr; -} /* ZbExtendedAddress */ +} uint16_t ZbShortAddress(struct ZigBeeT *zb) @@ -363,7 +364,7 @@ ZbShortAddress(struct ZigBeeT *zb) (void)ZbNwkGet(zb, ZB_NWK_NIB_ID_NetworkAddress, &nwkAddr, sizeof(nwkAddr)); return nwkAddr; -} /* ZbShortAddress */ +} void ZbChangeExtAddr(struct ZigBeeT *zb, uint64_t extAddr) @@ -377,7 +378,7 @@ ZbChangeExtAddr(struct ZigBeeT *zb, uint64_t extAddr) ipcc_req->Size = 2; zb_ipc_m4_memcpy2(&ipcc_req->Data[0], &extAddr, 8); ZIGBEE_CmdTransfer(); -} /* ZbChangeExtAddr */ +} uint8_t WpanGetNumChannelsFromMask(uint32_t mask, uint8_t *first_channel) @@ -394,9 +395,9 @@ WpanGetNumChannelsFromMask(uint32_t mask, uint8_t *first_channel) *first_channel = i; } } - } /* for */ + } return num_channels; -} /* WpanGetNumChannelsFromMask */ +} void ZbStartupConfigGetProDefaults(struct ZbStartupT *configPtr) @@ -409,7 +410,7 @@ ZbStartupConfigGetProDefaults(struct ZbStartupT *configPtr) ipcc_req->Size = 1; ipcc_req->Data[0] = (uint32_t)configPtr; ZIGBEE_CmdTransfer(); -} /* ZbStartupConfigGetProDefaults */ +} void ZbStartupConfigGetProSeDefaults(struct ZbStartupT *configPtr) @@ -419,14 +420,14 @@ ZbStartupConfigGetProSeDefaults(struct ZbStartupT *configPtr) (void)memset(configPtr->security.preconfiguredLinkKey, 0, ZB_SEC_KEYSIZE); /* Remove the distributed link key by clearing it. */ (void)memset(configPtr->security.distributedGlobalKey, 0, ZB_SEC_KEYSIZE); -} /* ZbStartupConfigGetProSeDefaults */ +} enum ZbStatusCodeT ZbStartupCbkeConfig(struct ZigBeeT *zb, struct ZbStartupCbkeT *cbke_config) { /* TODO - may be required for SE certification */ return ZB_APS_STATUS_NOT_SUPPORTED; -} /* ZbStartupCbkeConfig */ +} enum ZbStatusCodeT ZbStartup(struct ZigBeeT *zb, struct ZbStartupT *configPtr, void (*callback)(enum ZbStatusCodeT status, void *cb_arg), void *arg) @@ -447,7 +448,7 @@ ZbStartup(struct ZigBeeT *zb, struct ZbStartupT *configPtr, void (*callback)(enu ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_STARTUP_CB handler */ -} /* ZbStartup */ +} enum ZbStatusCodeT ZbStartupRejoin(struct ZigBeeT *zb, void (*callback)(ZbNlmeJoinConfT *conf, void *arg), void *cbarg) @@ -467,7 +468,7 @@ ZbStartupRejoin(struct ZigBeeT *zb, void (*callback)(ZbNlmeJoinConfT *conf, void ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_STARTUP_REJOIN_CB handler */ -} /* ZbStartupRejoin */ +} enum ZbStatusCodeT ZbStartupPersist(struct ZigBeeT *zb, const void *pdata, unsigned int plen, struct ZbStartupCbkeT *cbke_config) @@ -483,7 +484,7 @@ ZbStartupPersist(struct ZigBeeT *zb, const void *pdata, unsigned int plen, struc ipcc_req->Data[2] = (uint32_t)cbke_config; ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); -} /* ZbStartupPersist */ +} enum ZbStatusCodeT ZbStartupFindBindStart(struct ZigBeeT *zb, void (*callback)(enum ZbStatusCodeT status, void *arg), void *arg) @@ -508,7 +509,7 @@ ZbStartupFindBindStart(struct ZigBeeT *zb, void (*callback)(enum ZbStatusCodeT s } return status; /* Followed up in MSG_M0TOM4_STARTUP_FINDBIND_CB handler */ -} /* ZbStartupFindBindStart */ +} enum ZbStatusCodeT ZbStartupTouchlinkTargetStop(struct ZigBeeT *zb) @@ -521,7 +522,7 @@ ZbStartupTouchlinkTargetStop(struct ZigBeeT *zb) ipcc_req->Size = 0; ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); -} /* ZbStartupTouchlinkTargetStop */ +} bool ZbStartupTcsoStart(struct ZigBeeT *zb, void (*callback)(enum ZbTcsoStatusT status, void *arg), void *arg) @@ -546,7 +547,7 @@ ZbStartupTcsoStart(struct ZigBeeT *zb, void (*callback)(enum ZbTcsoStatusT statu } return retval; /* Followed up in MSG_M0TOM4_STARTUP_TCSO_CB */ -} /* ZbStartupTcsoStart */ +} void ZbStartupTcsoAbort(struct ZigBeeT *zb) @@ -558,7 +559,7 @@ ZbStartupTcsoAbort(struct ZigBeeT *zb) ipcc_req->ID = MSG_M4TOM0_STARTUP_TCSO_ABORT; ipcc_req->Size = 0; ZIGBEE_CmdTransfer(); -} /* ZbStartupTcsoAbort */ +} enum ZbStatusCodeT ZbTrustCenterRejoin(struct ZigBeeT *zb, void (*callback)(enum ZbStatusCodeT status, void *arg), void *cbarg) @@ -578,7 +579,7 @@ ZbTrustCenterRejoin(struct ZigBeeT *zb, void (*callback)(enum ZbStatusCodeT stat ZIGBEE_CmdTransfer(); return zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_STARTUP_TC_REJOIN_CB handler */ -} /* ZbTrustCenterRejoin */ +} bool ZbPersistNotifyRegister(struct ZigBeeT *zb, void (*callback)(struct ZigBeeT *zb, void *cbarg), void *cbarg) @@ -602,7 +603,7 @@ ZbPersistNotifyRegister(struct ZigBeeT *zb, void (*callback)(struct ZigBeeT *zb, } return result; /* Followed up by M0 calls to MSG_M0TOM4_PERSIST_CB */ -} /* ZbPersistNotifyRegister */ +} unsigned int ZbPersistGet(struct ZigBeeT *zb, uint8_t *buf, unsigned int maxlen) @@ -617,7 +618,7 @@ ZbPersistGet(struct ZigBeeT *zb, uint8_t *buf, unsigned int maxlen) ipcc_req->Data[1] = (uint32_t)maxlen; ZIGBEE_CmdTransfer(); return zb_ipc_m4_get_retval(); -} /* ZbPersistGet */ +} enum ZbStatusCodeT ZbLeaveReq(struct ZigBeeT *zb, void (*callback)(struct ZbNlmeLeaveConfT *conf, void *arg), void *cbarg) @@ -637,7 +638,7 @@ ZbLeaveReq(struct ZigBeeT *zb, void (*callback)(struct ZbNlmeLeaveConfT *conf, v ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZB_LEAVE_CB handler */ -} /* ZbLeaveReq */ +} void ZbReset(struct ZigBeeT *zb) @@ -649,7 +650,7 @@ ZbReset(struct ZigBeeT *zb) ipcc_req->ID = MSG_M4TOM0_ZB_RESET_REQ; ipcc_req->Size = 0; ZIGBEE_CmdTransfer(); -} /* ZbReset */ +} /****************************************************************************** * ECDSA Signature @@ -658,7 +659,8 @@ ZbReset(struct ZigBeeT *zb) enum ZbStatusCodeT ZbSecEcdsaValidate(struct ZigBeeT *zb, enum ZbSecEcdsaSigType sig_type, const uint8_t *ca_pub_key_array, unsigned int ca_pub_key_len, - const uint8_t *certificate, const uint8_t *signature, uint8_t *image_digest, uint8_t *cert_digest) + const uint8_t *certificate, const uint8_t *signature, + const uint8_t *image_digest, const uint8_t *cert_digest) { Zigbee_Cmd_Request_t *ipcc_req; @@ -675,7 +677,7 @@ ZbSecEcdsaValidate(struct ZigBeeT *zb, enum ZbSecEcdsaSigType sig_type, ipcc_req->Data[6] = (uint32_t)cert_digest; ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); -} /* ZbSecEcdsaValidate */ +} /****************************************************************************** * BDB @@ -703,7 +705,7 @@ ZbBdbGetIndex(struct ZigBeeT *zb, enum ZbBdbAttrIdT attrId, void *attrPtr, ipcc_req->Data[1] = (uint32_t)&bdbGetConf; ZIGBEE_CmdTransfer(); return bdbGetConf.status; -} /* ZbBdbGetIndex */ +} enum ZbStatusCodeT ZbBdbSetIndex(struct ZigBeeT *zb, enum ZbBdbAttrIdT attrId, const void *attrPtr, @@ -727,9 +729,26 @@ ZbBdbSetIndex(struct ZigBeeT *zb, enum ZbBdbAttrIdT attrId, const void *attrPtr, ipcc_req->Data[1] = (uint32_t)&bdbSetConf; ZIGBEE_CmdTransfer(); return bdbSetConf.status; -} /* ZbBdbSetIndex */ +} + +enum ZbBdbCommissioningStatusT +ZbBdbGetEndpointStatus(struct ZigBeeT *zb, uint8_t endpoint) +{ + Zigbee_Cmd_Request_t *ipcc_req; + uint32_t retval; + + Pre_ZigbeeCmdProcessing(); + ipcc_req = ZIGBEE_Get_OTCmdPayloadBuffer(); + ipcc_req->ID = MSG_M4TOM0_BDB_GET_EP_STATUS; + ipcc_req->Size = 1; + ipcc_req->Data[0] = (uint32_t)endpoint; + ZIGBEE_CmdTransfer(); + /* Get the status code */ + retval = zb_ipc_m4_get_retval(); + return (enum ZbBdbCommissioningStatusT)retval; +} -/* ZbBdbSetEndpointStatus is required for the Identify Server Cluster */ +/* Required for the Identify Server Cluster */ void ZbBdbSetEndpointStatus(struct ZigBeeT *zb, enum ZbBdbCommissioningStatusT status, uint8_t endpoint) { @@ -742,7 +761,7 @@ ZbBdbSetEndpointStatus(struct ZigBeeT *zb, enum ZbBdbCommissioningStatusT status ipcc_req->Data[0] = (uint32_t)status; ipcc_req->Data[1] = (uint32_t)endpoint; ZIGBEE_CmdTransfer(); -} /* ZbBdbSetEndpointStatus */ +} /****************************************************************************** * APS @@ -773,7 +792,7 @@ ZbApsdeDataReqCallback(struct ZigBeeT *zb, ZbApsdeDataReqT *req, void (*callback } return (enum ZbStatusCodeT)retval; /* If success, followed up in MSG_M0TOM4_APSDE_DATA_REQ_CB handler */ -} /* ZbApsdeDataReqCallback */ +} void ZbApsmeAddEndpoint(struct ZigBeeT *zb, ZbApsmeAddEndpointReqT *r, ZbApsmeAddEndpointConfT *c) @@ -787,7 +806,7 @@ ZbApsmeAddEndpoint(struct ZigBeeT *zb, ZbApsmeAddEndpointReqT *r, ZbApsmeAddEndp ipcc_req->Data[0] = (uint32_t)r; ipcc_req->Data[1] = (uint32_t)c; ZIGBEE_CmdTransfer(); -} /* ZbApsmeAddEndpoint */ +} void ZbApsmeRemoveEndpoint(struct ZigBeeT *zb, ZbApsmeRemoveEndpointReqT *r, ZbApsmeRemoveEndpointConfT *c) @@ -801,7 +820,7 @@ ZbApsmeRemoveEndpoint(struct ZigBeeT *zb, ZbApsmeRemoveEndpointReqT *r, ZbApsmeR ipcc_req->Data[0] = (uint32_t)r; ipcc_req->Data[1] = (uint32_t)c; ZIGBEE_CmdTransfer(); -} /* ZbApsmeRemoveEndpoint */ +} struct ZbApsFilterT * ZbApsFilterEndpointAdd(struct ZigBeeT *zb, uint8_t endpoint, uint16_t profileId, @@ -811,7 +830,7 @@ ZbApsFilterEndpointAdd(struct ZigBeeT *zb, uint8_t endpoint, uint16_t profileId, struct aps_filter_cb *aps_filter_cb; struct ZbApsFilterT *filter; - /* FIXME - track these allocations so they can be freed later? */ + /* EXEGIN - track these allocations so they can be freed later? */ aps_filter_cb = malloc(sizeof(struct aps_filter_cb)); if (aps_filter_cb == NULL) { return NULL; @@ -833,7 +852,7 @@ ZbApsFilterEndpointAdd(struct ZigBeeT *zb, uint8_t endpoint, uint16_t profileId, } /* Callbacks go to MSG_M0TOM4_APS_FILTER_ENDPOINT_CB handler */ return filter; -} /* ZbApsFilterEndpointAdd */ +} bool ZbApsmeEndpointConfigNoMatchCallback(struct ZigBeeT *zb, uint8_t endpoint, @@ -843,7 +862,7 @@ ZbApsmeEndpointConfigNoMatchCallback(struct ZigBeeT *zb, uint8_t endpoint, struct aps_filter_cb *aps_filter_cb; bool retval; - /* FIXME - track these allocations so they can be freed later? */ + /* EXEGIN - track these allocations so they can be freed later? */ aps_filter_cb = malloc(sizeof(struct aps_filter_cb)); if (aps_filter_cb == NULL) { return false; @@ -864,7 +883,7 @@ ZbApsmeEndpointConfigNoMatchCallback(struct ZigBeeT *zb, uint8_t endpoint, } /* Callbacks go to MSG_M0TOM4_APS_FILTER_ENDPOINT_CB handler */ return retval; -} /* ZbApsmeEndpointConfigNoMatchCallback */ +} struct ZbApsFilterT * ZbApsFilterClusterAdd(struct ZigBeeT *zb, uint8_t endpoint, uint16_t clusterId, uint16_t profileId, @@ -874,7 +893,7 @@ ZbApsFilterClusterAdd(struct ZigBeeT *zb, uint8_t endpoint, uint16_t clusterId, struct aps_filter_cb *aps_filter_cb; struct ZbApsFilterT *filter; - /* FIXME - track these allocations so they can be freed later. */ + /* EXEGIN - track these allocations so they can be freed later. */ aps_filter_cb = malloc(sizeof(struct aps_filter_cb)); if (aps_filter_cb == NULL) { return NULL; @@ -897,7 +916,7 @@ ZbApsFilterClusterAdd(struct ZigBeeT *zb, uint8_t endpoint, uint16_t clusterId, } /* Callbacks go to MSG_M0TOM4_APS_FILTER_CLUSTER_CB handler */ return filter; -} /* ZbApsFilterClusterAdd */ +} bool ZbApsmeEndpointClusterListAppend(struct ZigBeeT *zb, uint8_t endpoint, uint16_t cluster_id, bool is_input) @@ -913,7 +932,7 @@ ZbApsmeEndpointClusterListAppend(struct ZigBeeT *zb, uint8_t endpoint, uint16_t ipcc_req->Data[2] = (uint32_t)is_input; ZIGBEE_CmdTransfer(); return zb_ipc_m4_get_retval() != 0U ? true : false; -} /* ZbApsmeEndpointClusterListAppend */ +} bool ZbApsEndpointExists(struct ZigBeeT *zb, uint8_t endpoint) @@ -927,7 +946,7 @@ ZbApsEndpointExists(struct ZigBeeT *zb, uint8_t endpoint) ipcc_req->Data[0] = (uint32_t)endpoint; ZIGBEE_CmdTransfer(); return zb_ipc_m4_get_retval() != 0U ? true : false; -} /* ZbApsEndpointExists */ +} uint16_t ZbApsEndpointProfile(struct ZigBeeT *zb, uint8_t endpoint) @@ -941,7 +960,7 @@ ZbApsEndpointProfile(struct ZigBeeT *zb, uint8_t endpoint) ipcc_req->Data[0] = (uint32_t)endpoint; ZIGBEE_CmdTransfer(); return (uint16_t)zb_ipc_m4_get_retval(); -} /* ZbApsEndpointProfile */ +} bool ZbApsAddrIsBcast(struct ZbApsAddrT *addr) @@ -954,7 +973,7 @@ ZbApsAddrIsBcast(struct ZbApsAddrT *addr) return true; } return false; -} /* ZbApsAddrIsBcast */ +} bool ZbApsAddrIsLocal(struct ZigBeeT *zb, struct ZbApsAddrT *addr) @@ -972,7 +991,7 @@ ZbApsAddrIsLocal(struct ZigBeeT *zb, struct ZbApsAddrT *addr) } } return false; -} /* ZbApsAddrIsLocal */ +} enum ZbStatusCodeT ZbApsGetIndex(struct ZigBeeT *zb, enum ZbApsmeIbAttrIdT attrId, void *attrPtr, unsigned int attrSz, unsigned int attrIndex) @@ -995,7 +1014,7 @@ ZbApsGetIndex(struct ZigBeeT *zb, enum ZbApsmeIbAttrIdT attrId, void *attrPtr, u ipcc_req->Data[1] = (uint32_t)&apsmeGetConf; ZIGBEE_CmdTransfer(); return apsmeGetConf.status; -} /* ZbApsGetIndex */ +} enum ZbStatusCodeT ZbApsSetIndex(struct ZigBeeT *zb, enum ZbApsmeIbAttrIdT attrId, const void *attrPtr, unsigned int attrSz, unsigned int attrIndex) @@ -1018,7 +1037,7 @@ ZbApsSetIndex(struct ZigBeeT *zb, enum ZbApsmeIbAttrIdT attrId, const void *attr ipcc_req->Data[1] = (uint32_t)&apsmeSetConf; ZIGBEE_CmdTransfer(); return apsmeSetConf.status; -} /* ZbApsSetIndex */ +} void ZbApsmeAddGroupReq(struct ZigBeeT *zb, ZbApsmeAddGroupReqT *r, ZbApsmeAddGroupConfT *c) @@ -1032,7 +1051,7 @@ ZbApsmeAddGroupReq(struct ZigBeeT *zb, ZbApsmeAddGroupReqT *r, ZbApsmeAddGroupCo ipcc_req->Data[0] = (uint32_t)r; ipcc_req->Data[1] = (uint32_t)c; ZIGBEE_CmdTransfer(); -} /* ZbApsmeAddGroupReq */ +} void ZbApsmeRemoveGroupReq(struct ZigBeeT *zb, ZbApsmeRemoveGroupReqT *r, ZbApsmeRemoveGroupConfT *c) @@ -1046,7 +1065,7 @@ ZbApsmeRemoveGroupReq(struct ZigBeeT *zb, ZbApsmeRemoveGroupReqT *r, ZbApsmeRemo ipcc_req->Data[0] = (uint32_t)r; ipcc_req->Data[1] = (uint32_t)c; ZIGBEE_CmdTransfer(); -} /* ZbApsmeRemoveGroupReq */ +} void ZbApsmeRemoveAllGroupsReq(struct ZigBeeT *zb, ZbApsmeRemoveAllGroupsReqT *r, ZbApsmeRemoveAllGroupsConfT *c) @@ -1060,7 +1079,7 @@ ZbApsmeRemoveAllGroupsReq(struct ZigBeeT *zb, ZbApsmeRemoveAllGroupsReqT *r, ZbA ipcc_req->Data[0] = (uint32_t)r; ipcc_req->Data[1] = (uint32_t)c; ZIGBEE_CmdTransfer(); -} /* ZbApsmeRemoveAllGroupsReq */ +} bool ZbApsGroupIsMember(struct ZigBeeT *zb, uint16_t groupAddr, uint8_t endpoint) @@ -1089,10 +1108,10 @@ ZbApsGroupIsMember(struct ZigBeeT *zb, uint16_t groupAddr, uint8_t endpoint) /* We are a member. */ ZbExitCritical(zb); return true; - } /* for */ + } ZbExitCritical(zb); return false; -} /* ZbApsGroupIsMember */ +} /* Helper to iterate through the Groups table using the APSME-GET interface */ uint8_t @@ -1112,10 +1131,10 @@ ZbApsGroupsGetCapacity(struct ZigBeeT *zb) continue; } num_found++; - } /* for */ + } ZbExitCritical(zb); return (uint8_t)(i - num_found); -} /* ZbApsGroupsGetCapacity */ +} /* Helper to iterate through the Groups table using the APSME-GET interface */ uint8_t @@ -1145,10 +1164,10 @@ ZbApsGroupsGetMembership(struct ZigBeeT *zb, uint8_t endpoint, uint16_t *group_l break; } group_list[len++] = group.groupAddr; - } /* for */ + } ZbExitCritical(zb); return len; -} /* ZbApsGroupsGetMembership */ +} void ZbApsmeBindReq(struct ZigBeeT *zb, ZbApsmeBindReqT *bindReqPtr, ZbApsmeBindConfT *bindConfPtr) @@ -1162,7 +1181,7 @@ ZbApsmeBindReq(struct ZigBeeT *zb, ZbApsmeBindReqT *bindReqPtr, ZbApsmeBindConfT ipcc_req->Data[0] = (uint32_t)bindReqPtr; ipcc_req->Data[1] = (uint32_t)bindConfPtr; ZIGBEE_CmdTransfer(); -} /* ZbApsmeBindReq */ +} void ZbApsmeUnbindReq(struct ZigBeeT *zb, ZbApsmeUnbindReqT *unbindReqPtr, ZbApsmeUnbindConfT *unbindConfPtr) @@ -1176,7 +1195,7 @@ ZbApsmeUnbindReq(struct ZigBeeT *zb, ZbApsmeUnbindReqT *unbindReqPtr, ZbApsmeUnb ipcc_req->Data[0] = (uint32_t)unbindReqPtr; ipcc_req->Data[1] = (uint32_t)unbindConfPtr; ZIGBEE_CmdTransfer(); -} /* ZbApsmeUnbindReq */ +} void ZbApsUnbindAllReq(struct ZigBeeT *zb) @@ -1188,7 +1207,7 @@ ZbApsUnbindAllReq(struct ZigBeeT *zb) ipcc_req->ID = MSG_M4TOM0_APS_UNBIND_ALL; ipcc_req->Size = 0; ZIGBEE_CmdTransfer(); -} /* ZbApsUnbindAllReq */ +} void ZbApsmeTransportKeyReq(struct ZigBeeT *zb, ZbApsmeTransportKeyReqT *req) @@ -1201,7 +1220,7 @@ ZbApsmeTransportKeyReq(struct ZigBeeT *zb, ZbApsmeTransportKeyReqT *req) ipcc_req->Size = 1; ipcc_req->Data[0] = (uint32_t)req; ZIGBEE_CmdTransfer(); -} /* ZbApsmeTransportKeyReq */ +} void ZbApsmeRemoveDeviceReq(struct ZigBeeT *zb, ZbApsmeRemoveDeviceReqT *req) @@ -1214,7 +1233,7 @@ ZbApsmeRemoveDeviceReq(struct ZigBeeT *zb, ZbApsmeRemoveDeviceReqT *req) ipcc_req->Size = 1; ipcc_req->Data[0] = (uint32_t)req; ZIGBEE_CmdTransfer(); -} /* ZbApsmeRemoveDeviceReq */ +} enum ZbStatusCodeT ZbApsmeRequestKeyReq(struct ZigBeeT *zb, ZbApsmeRequestKeyReqT *req) @@ -1228,7 +1247,7 @@ ZbApsmeRequestKeyReq(struct ZigBeeT *zb, ZbApsmeRequestKeyReqT *req) ipcc_req->Data[0] = (uint32_t)req; ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); -} /* ZbApsmeRequestKeyReq */ +} void ZbApsmeSwitchKeyReq(struct ZigBeeT *zb, ZbApsmeSwitchKeyReqT *req) @@ -1241,7 +1260,7 @@ ZbApsmeSwitchKeyReq(struct ZigBeeT *zb, ZbApsmeSwitchKeyReqT *req) ipcc_req->Size = 1; ipcc_req->Data[0] = (uint32_t)req; ZIGBEE_CmdTransfer(); -} /* ZbApsmeSwitchKeyReq */ +} void ZbApsmeAddKeyReq(struct ZigBeeT *zb, ZbApsmeAddKeyReqT *req, ZbApsmeAddKeyConfT *conf) @@ -1255,7 +1274,7 @@ ZbApsmeAddKeyReq(struct ZigBeeT *zb, ZbApsmeAddKeyReqT *req, ZbApsmeAddKeyConfT ipcc_req->Data[0] = (uint32_t)req; ipcc_req->Data[1] = (uint32_t)conf; ZIGBEE_CmdTransfer(); -} /* ZbApsmeAddKeyReq */ +} void ZbApsmeGetKeyReq(struct ZigBeeT *zb, ZbApsmeGetKeyReqT *req, ZbApsmeGetKeyConfT *conf) @@ -1269,7 +1288,7 @@ ZbApsmeGetKeyReq(struct ZigBeeT *zb, ZbApsmeGetKeyReqT *req, ZbApsmeGetKeyConfT ipcc_req->Data[0] = (uint32_t)req; ipcc_req->Data[1] = (uint32_t)conf; ZIGBEE_CmdTransfer(); -} /* ZbApsmeGetKeyReq */ +} void ZbApsmeRemoveKeyReq(struct ZigBeeT *zb, ZbApsmeRemoveKeyReqT *req, ZbApsmeRemoveKeyConfT *conf) @@ -1283,7 +1302,7 @@ ZbApsmeRemoveKeyReq(struct ZigBeeT *zb, ZbApsmeRemoveKeyReqT *req, ZbApsmeRemove ipcc_req->Data[0] = (uint32_t)req; ipcc_req->Data[1] = (uint32_t)conf; ZIGBEE_CmdTransfer(); -} /* ZbApsmeRemoveKeyReq */ +} /****************************************************************************** * Zigbee Message Filters @@ -1291,7 +1310,7 @@ ZbApsmeRemoveKeyReq(struct ZigBeeT *zb, ZbApsmeRemoveKeyReqT *req, ZbApsmeRemove */ struct zb_msg_filter_cb_info { struct ZbMsgFilterT *filter; - int (*callback)(struct ZigBeeT *zb, uint32_t id, void *msg, void *cbarg); + enum zb_msg_filter_rc (*callback)(struct ZigBeeT *zb, uint32_t id, void *msg, void *cbarg); void *arg; }; @@ -1300,7 +1319,7 @@ static struct zb_msg_filter_cb_info zb_msg_filter_cb_list[ZB_IPC_MSG_FILTER_CB_L struct ZbMsgFilterT * ZbMsgFilterRegister(struct ZigBeeT *zb, uint32_t mask, uint8_t prio, - int (*callback)(struct ZigBeeT *zb, uint32_t id, void *msg, void *cbarg), void *arg) + enum zb_msg_filter_rc (*callback)(struct ZigBeeT *zb, uint32_t id, void *msg, void *cbarg), void *arg) { Zigbee_Cmd_Request_t *ipcc_req; struct ZbMsgFilterT *filter; @@ -1333,7 +1352,7 @@ ZbMsgFilterRegister(struct ZigBeeT *zb, uint32_t mask, uint8_t prio, } return filter; /* Followed up by MSG_M0TOM4_FILTER_MSG_CB */ -} /* ZbMsgFilterRegister */ +} void ZbMsgFilterRemove(struct ZigBeeT *zb, struct ZbMsgFilterT *filter) @@ -1362,7 +1381,7 @@ ZbMsgFilterRemove(struct ZigBeeT *zb, struct ZbMsgFilterT *filter) ipcc_req->Data[0] = (uint32_t)filter; ZIGBEE_CmdTransfer(); cb_info->filter = NULL; -} /* ZbMsgFilterRemove */ +} /****************************************************************************** * Zigbee Timer API @@ -1404,7 +1423,7 @@ ZbTimerAlloc(struct ZigBeeT *zb, void (*callback)(struct ZigBeeT *zb, void *cn_a } } return timer; -} /* ZbTimerAlloc */ +} void ZbTimerChangeCallback(struct ZbTimerT *timer, void (*callback)(struct ZigBeeT *zb, void *cb_arg), void *arg) @@ -1412,7 +1431,7 @@ ZbTimerChangeCallback(struct ZbTimerT *timer, void (*callback)(struct ZigBeeT *z ZbTimerStop(timer); timer->callback = callback; timer->arg = arg; -} /* ZbTimerChangeCallback */ +} void ZbTimerFree(struct ZbTimerT *timer) @@ -1429,7 +1448,7 @@ ZbTimerFree(struct ZbTimerT *timer) /* Free the timer struct on the M4 */ ZbHeapFree(NULL, timer); -} /* ZbTimerFree */ +} bool ZbTimerRunning(struct ZbTimerT *timer) @@ -1445,7 +1464,7 @@ ZbTimerRunning(struct ZbTimerT *timer) ZIGBEE_CmdTransfer(); retval = zb_ipc_m4_get_retval(); return retval != 0 ? true : false; -} /* ZbTimerRunning */ +} unsigned int ZbTimerRemaining(struct ZbTimerT *timer) @@ -1459,7 +1478,7 @@ ZbTimerRemaining(struct ZbTimerT *timer) ipcc_req->Data[0] = (uint32_t)timer->m0_timer; ZIGBEE_CmdTransfer(); return (unsigned int)zb_ipc_m4_get_retval(); -} /* ZbTimerRemaining */ +} void ZbTimerStop(struct ZbTimerT *timer) @@ -1472,7 +1491,7 @@ ZbTimerStop(struct ZbTimerT *timer) ipcc_req->Size = 1; ipcc_req->Data[0] = (uint32_t)timer->m0_timer; ZIGBEE_CmdTransfer(); -} /* ZbTimerStop */ +} void ZbTimerReset(struct ZbTimerT *timer, unsigned int timeout) @@ -1486,7 +1505,7 @@ ZbTimerReset(struct ZbTimerT *timer, unsigned int timeout) ipcc_req->Data[0] = (uint32_t)timer->m0_timer; ipcc_req->Data[1] = (uint32_t)timeout; ZIGBEE_CmdTransfer(); -} /* ZbTimerReset */ +} unsigned int ZbTimeoutRemaining(ZbUptimeT now, ZbUptimeT expire_time) @@ -1518,7 +1537,7 @@ ZbTimeoutRemaining(ZbUptimeT now, ZbUptimeT expire_time) u_delta = expire_time - now; return (unsigned int)u_delta; -} /* ZbTimeoutRemaining */ +} /****************************************************************************** * NWK @@ -1546,7 +1565,7 @@ ZbNwkGetIndex(struct ZigBeeT *zb, enum ZbNwkNibAttrIdT attrId, void *attrPtr, ipcc_req->Data[1] = (uint32_t)&nlmeGetConf; ZIGBEE_CmdTransfer(); return nlmeGetConf.status; -} /* ZbNwkGetIndex */ +} enum ZbStatusCodeT ZbNwkSetIndex(struct ZigBeeT *zb, enum ZbNwkNibAttrIdT attrId, void *attrPtr, @@ -1570,19 +1589,19 @@ ZbNwkSetIndex(struct ZigBeeT *zb, enum ZbNwkNibAttrIdT attrId, void *attrPtr, ipcc_req->Data[1] = (uint32_t)&nlmeSetConf; ZIGBEE_CmdTransfer(); return nlmeSetConf.status; -} /* ZbNwkSetIndex */ +} enum ZbStatusCodeT ZbNwkGet(struct ZigBeeT *zb, enum ZbNwkNibAttrIdT attrId, void *attrPtr, unsigned int attrSz) { return ZbNwkGetIndex(zb, attrId, attrPtr, attrSz, 0); -} /* ZbNwkGet */ +} enum ZbStatusCodeT ZbNwkSet(struct ZigBeeT *zb, enum ZbNwkNibAttrIdT attrId, void *attrPtr, unsigned int attrSz) { return ZbNwkSetIndex(zb, attrId, attrPtr, attrSz, 0); -} /* ZbNwkSet */ +} uint64_t ZbNwkGetParentExtAddr(struct ZigBeeT *zb) @@ -1600,7 +1619,7 @@ ZbNwkGetParentExtAddr(struct ZigBeeT *zb) assert(ipcc_req->Size == 2); zb_ipc_m4_memcpy2(&ext_addr, &ipcc_req->Data[0], 8); return ext_addr; -} /* ZbNwkGetParentExtAddr */ +} uint16_t ZbNwkGetParentShortAddr(struct ZigBeeT *zb) @@ -1613,7 +1632,7 @@ ZbNwkGetParentShortAddr(struct ZigBeeT *zb) ipcc_req->Size = 0; ZIGBEE_CmdTransfer(); return (uint16_t)zb_ipc_m4_get_retval(); -} /* ZbNwkGetParentShortAddr */ +} uint64_t ZbNwkAddrLookupExt(struct ZigBeeT *zb, uint16_t nwkAddr) @@ -1632,7 +1651,7 @@ ZbNwkAddrLookupExt(struct ZigBeeT *zb, uint16_t nwkAddr) assert(ipcc_req->Size == 2); zb_ipc_m4_memcpy2(&ext_addr, &ipcc_req->Data[0], 8); return ext_addr; -} /* ZbNwkAddrLookupExt */ +} uint16_t ZbNwkAddrLookupNwk(struct ZigBeeT *zb, uint64_t extAddr) @@ -1647,7 +1666,7 @@ ZbNwkAddrLookupNwk(struct ZigBeeT *zb, uint64_t extAddr) zb_ipc_m4_memcpy2(ipcc_req->Data, &extAddr, 8); ZIGBEE_CmdTransfer(); return (uint16_t)zb_ipc_m4_get_retval(); -} /* ZbNwkAddrLookupNwk */ +} bool ZbNwkAddrIsChildExt(struct ZigBeeT *zb, uint64_t extAddr, uint16_t *nwkAddrPtr) @@ -1663,7 +1682,7 @@ ZbNwkAddrIsChildExt(struct ZigBeeT *zb, uint64_t extAddr, uint16_t *nwkAddrPtr) ipcc_req->Data[2] = (uint32_t)nwkAddrPtr; ZIGBEE_CmdTransfer(); return zb_ipc_m4_get_retval() != 0U ? true : false; -} /* ZbNwkAddrIsChildExt */ +} bool ZbNwkAddrIsChildNwk(struct ZigBeeT *zb, uint16_t nwkAddr, uint64_t *extAddrPtr) @@ -1678,7 +1697,7 @@ ZbNwkAddrIsChildNwk(struct ZigBeeT *zb, uint16_t nwkAddr, uint64_t *extAddrPtr) ipcc_req->Data[1] = (uint32_t)extAddrPtr; ZIGBEE_CmdTransfer(); return zb_ipc_m4_get_retval() != 0U ? true : false; -} /* ZbNwkAddrIsChildNwk */ +} bool ZbNwkGetSecMaterial(struct ZigBeeT *zb, uint8_t keySeqno, ZbNwkSecMaterialT *material) @@ -1693,7 +1712,7 @@ ZbNwkGetSecMaterial(struct ZigBeeT *zb, uint8_t keySeqno, ZbNwkSecMaterialT *mat ipcc_req->Data[1] = (uint32_t)material; ZIGBEE_CmdTransfer(); return zb_ipc_m4_get_retval() != 0U ? true : false; -} /* ZbNwkGetSecMaterial */ +} enum ZbStatusCodeT ZbNlmeNetDiscReq(struct ZigBeeT *zb, ZbNlmeNetDiscReqT *req, @@ -1715,7 +1734,7 @@ ZbNlmeNetDiscReq(struct ZigBeeT *zb, ZbNlmeNetDiscReqT *req, ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_NLME_NET_DISC_CB handler */ -} /* ZbNlmeNetDiscReq */ +} enum ZbStatusCodeT ZbNlmeLeaveReq(struct ZigBeeT *zb, struct ZbNlmeLeaveReqT *req, @@ -1737,7 +1756,7 @@ ZbNlmeLeaveReq(struct ZigBeeT *zb, struct ZbNlmeLeaveReqT *req, ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_NLME_LEAVE_CB handler */ -} /* ZbNlmeLeaveReq */ +} void ZbNlmePermitJoinReq(struct ZigBeeT *zb, ZbNlmePermitJoinReqT *req, ZbNlmePermitJoinConfT *conf) @@ -1751,7 +1770,7 @@ ZbNlmePermitJoinReq(struct ZigBeeT *zb, ZbNlmePermitJoinReqT *req, ZbNlmePermitJ ipcc_req->Data[0] = (uint32_t)req; ipcc_req->Data[1] = (uint32_t)conf; ZIGBEE_CmdTransfer(); -} /* ZbNlmePermitJoinReq */ +} void ZbNlmeResetReq(struct ZigBeeT *zb, ZbNlmeResetReqT *req, ZbNlmeResetConfT *conf) @@ -1765,7 +1784,7 @@ ZbNlmeResetReq(struct ZigBeeT *zb, ZbNlmeResetReqT *req, ZbNlmeResetConfT *conf) ipcc_req->Data[0] = (uint32_t)req; ipcc_req->Data[1] = (uint32_t)conf; ZIGBEE_CmdTransfer(); -} /* ZbNlmeResetReq */ +} enum ZbStatusCodeT ZbNlmeSyncReq(struct ZigBeeT *zb, ZbNlmeSyncReqT *req, @@ -1787,7 +1806,7 @@ ZbNlmeSyncReq(struct ZigBeeT *zb, ZbNlmeSyncReqT *req, ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_NLME_SYNC_CB handler */ -} /* ZbNlmeSyncReq */ +} enum ZbStatusCodeT ZbNlmeRouteDiscReq(struct ZigBeeT *zb, ZbNlmeRouteDiscReqT *req, @@ -1809,14 +1828,14 @@ ZbNlmeRouteDiscReq(struct ZigBeeT *zb, ZbNlmeRouteDiscReqT *req, ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_NLME_ROUTE_DISC_CB handler */ -} /* ZbNlmeRouteDiscReq */ +} enum WpanJoinPolicyT ZbNlmeJoiningPolicyGet(struct ZigBeeT *zb) { /* This is only for zbcli. We don't need this for 2.4 GHz operation. */ return WPAN_JOIN_POLICY_ALL; -} /* ZbNlmeJoiningPolicyGet */ +} void ZbNwkNeighborClearAll(struct ZigBeeT *zb, bool keep_parent, bool keep_children) @@ -1830,7 +1849,7 @@ ZbNwkNeighborClearAll(struct ZigBeeT *zb, bool keep_parent, bool keep_children) ipcc_req->Data[0] = (uint32_t)keep_parent; ipcc_req->Data[1] = (uint32_t)keep_children; ZIGBEE_CmdTransfer(); -} /* ZbNwkNeighborClearAll */ +} void ZbNlmeDirectJoinReq(struct ZigBeeT *zb, ZbNlmeDirectJoinReqT *req, ZbNlmeDirectJoinConfT *conf) @@ -1844,7 +1863,7 @@ ZbNlmeDirectJoinReq(struct ZigBeeT *zb, ZbNlmeDirectJoinReqT *req, ZbNlmeDirectJ ipcc_req->Data[0] = (uint32_t)req; ipcc_req->Data[1] = (uint32_t)conf; ZIGBEE_CmdTransfer(); -} /* ZbNlmeDirectJoinReq */ +} void ZbNlmeSetInterface(struct ZigBeeT *zb, ZbNlmeSetInterfaceReqT *req, ZbNlmeSetInterfaceConfT *conf) @@ -1858,7 +1877,7 @@ ZbNlmeSetInterface(struct ZigBeeT *zb, ZbNlmeSetInterfaceReqT *req, ZbNlmeSetInt ipcc_req->Data[0] = (uint32_t)req; ipcc_req->Data[1] = (uint32_t)conf; ZIGBEE_CmdTransfer(); -} /* ZbNlmeSetInterface */ +} void ZbNlmeGetInterface(struct ZigBeeT *zb, ZbNlmeGetInterfaceReqT *req, ZbNlmeGetInterfaceConfT *conf) @@ -1872,7 +1891,7 @@ ZbNlmeGetInterface(struct ZigBeeT *zb, ZbNlmeGetInterfaceReqT *req, ZbNlmeGetInt ipcc_req->Data[0] = (uint32_t)req; ipcc_req->Data[1] = (uint32_t)conf; ZIGBEE_CmdTransfer(); -} /* ZbNlmeGetInterface */ +} bool ZbNwkIfSetTxPower(struct ZigBeeT *zb, const char *name, int8_t tx_power) @@ -1887,7 +1906,7 @@ ZbNwkIfSetTxPower(struct ZigBeeT *zb, const char *name, int8_t tx_power) ipcc_req->Data[1] = (uint32_t)tx_power; ZIGBEE_CmdTransfer(); return zb_ipc_m4_get_retval() != 0U ? true : false; -} /* ZbNwkIfSetTxPower */ +} bool ZbNwkIfGetTxPower(struct ZigBeeT *zb, const char *name, int8_t *tx_power) @@ -1902,7 +1921,7 @@ ZbNwkIfGetTxPower(struct ZigBeeT *zb, const char *name, int8_t *tx_power) ipcc_req->Data[1] = (uint32_t)tx_power; ZIGBEE_CmdTransfer(); return zb_ipc_m4_get_retval() != 0U ? true : false; -} /* ZbNwkIfGetTxPower */ +} bool ZbNwkIfSetDsn(struct ZigBeeT *zb, const char *name, uint8_t macDsn) @@ -1933,7 +1952,7 @@ ZbNwkSetFrameCounter(struct ZigBeeT *zb, uint8_t keySeqno, uint64_t srcAddr, uin ipcc_req->Data[3] = (uint32_t)newFrameCount; ZIGBEE_CmdTransfer(); return zb_ipc_m4_get_retval() != 0U ? true : false; -} /* ZbNwkSetFrameCounter */ +} bool ZbNwkFastPollRequest(struct ZigBeeT *zb) @@ -1946,7 +1965,7 @@ ZbNwkFastPollRequest(struct ZigBeeT *zb) ipcc_req->Size = 0; ZIGBEE_CmdTransfer(); return zb_ipc_m4_get_retval() != 0U ? true : false; -} /* ZbNwkFastPollRequest */ +} bool ZbNwkFastPollRelease(struct ZigBeeT *zb) @@ -1959,7 +1978,7 @@ ZbNwkFastPollRelease(struct ZigBeeT *zb) ipcc_req->Size = 0; ZIGBEE_CmdTransfer(); return zb_ipc_m4_get_retval() != 0U ? true : false; -} /* ZbNwkFastPollRelease */ +} unsigned int ZbNwkFastPollResourceCount(struct ZigBeeT *zb) @@ -1972,7 +1991,7 @@ ZbNwkFastPollResourceCount(struct ZigBeeT *zb) ipcc_req->Size = 0; ZIGBEE_CmdTransfer(); return zb_ipc_m4_get_retval(); -} /* ZbNwkFastPollResourceCount */ +} /* Only required by zbcli. And only helps with automated verification of test cases. * Do not use for certification. */ @@ -1987,7 +2006,7 @@ ZbNwkAddrSetNextChildAddr(struct ZigBeeT *zb, uint16_t nextChildAddr) ipcc_req->Size = 1; ipcc_req->Data[0] = (uint32_t)nextChildAddr; ZIGBEE_CmdTransfer(); -} /* ZbNwkAddrSetNextChildAddr */ +} /* Required for zigbee certification only. May not be required for a DUT though. */ bool @@ -1996,7 +2015,7 @@ nwk_status_send(struct ZigBeeT *zb, uint16_t dstAddr, enum ZbNwkAddrModeT dstAdd { /* TODO? */ return false; -} /* nwk_status_send */ +} /* Required for zigbee certification only. May not be required for a DUT though. */ bool @@ -2004,7 +2023,7 @@ nwk_rreq_by_route_is_active(struct ZigBeeT *zb, ZbNwkRouteEntryT *route) { /* TODO? */ return false; -} /* nwk_rreq_by_route_is_active */ +} bool ZbNwkSendEdkaReq(struct ZigBeeT *zb) @@ -2060,7 +2079,7 @@ ZbZdoDeviceAnnceFilterRegister(struct ZigBeeT *zb, } return handle; /* Followed up in MSG_M0TOM4_ZDO_DEVICE_ANNCE_FILTER_CB handler */ -} /* ZbZdoDeviceAnnceFilterRegister */ +} void ZbZdoDeviceAnnceFilterRemove(struct ZigBeeT *zb, struct ZbZdoDeviceAnnceFilterT *handle) @@ -2089,7 +2108,7 @@ ZbZdoDeviceAnnceFilterRemove(struct ZigBeeT *zb, struct ZbZdoDeviceAnnceFilterT ipcc_req->Data[0] = (uint32_t)handle; ZIGBEE_CmdTransfer(); cb_info->handle = NULL; -} /* ZbZdoDeviceAnnceFilterRemove */ +} /****************************************************************************** * ZDO @@ -2115,7 +2134,7 @@ ZbZdoNwkAddrReq(struct ZigBeeT *zb, ZbZdoNwkAddrReqT *req, ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZDO_NWK_ADDR_CB handler */ -} /* ZbZdoNwkAddrReq */ +} enum ZbStatusCodeT ZbZdoIeeeAddrReq(struct ZigBeeT *zb, ZbZdoIeeeAddrReqT *req, @@ -2137,7 +2156,7 @@ ZbZdoIeeeAddrReq(struct ZigBeeT *zb, ZbZdoIeeeAddrReqT *req, ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZDO_IEEE_ADDR_CB handler */ -} /* ZbZdoIeeeAddrReq */ +} enum ZbStatusCodeT ZbZdoNodeDescReq(struct ZigBeeT *zb, ZbZdoNodeDescReqT *req, @@ -2159,7 +2178,7 @@ ZbZdoNodeDescReq(struct ZigBeeT *zb, ZbZdoNodeDescReqT *req, ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZDO_NODE_DESC_CB handler */ -} /* ZbZdoNodeDescReq */ +} enum ZbStatusCodeT ZbZdoPowerDescReq(struct ZigBeeT *zb, ZbZdoPowerDescReqT *req, @@ -2181,7 +2200,7 @@ ZbZdoPowerDescReq(struct ZigBeeT *zb, ZbZdoPowerDescReqT *req, ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZDO_POWER_DESC_CB handler */ -} /* ZbZdoPowerDescReq */ +} enum ZbStatusCodeT ZbZdoSimpleDescReq(struct ZigBeeT *zb, ZbZdoSimpleDescReqT *req, @@ -2203,7 +2222,7 @@ ZbZdoSimpleDescReq(struct ZigBeeT *zb, ZbZdoSimpleDescReqT *req, ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZDO_SIMPLE_DESC_CB handler */ -} /* ZbZdoSimpleDescReq */ +} enum ZbStatusCodeT ZbZdoActiveEpReq(struct ZigBeeT *zb, ZbZdoActiveEpReqT *req, @@ -2225,7 +2244,7 @@ ZbZdoActiveEpReq(struct ZigBeeT *zb, ZbZdoActiveEpReqT *req, ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZDO_ACTIVE_EP_CB handler */ -} /* ZbZdoActiveEpReq */ +} enum ZbStatusCodeT ZbZdoMatchDescReq(struct ZigBeeT *zb, ZbZdoMatchDescReqT *req, @@ -2247,28 +2266,38 @@ ZbZdoMatchDescReq(struct ZigBeeT *zb, ZbZdoMatchDescReqT *req, ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZDO_MATCH_DESC_CB handler */ -} /* ZbZdoMatchDescReq */ +} enum ZbStatusCodeT ZbZdoMatchDescMulti(struct ZigBeeT *zb, ZbZdoMatchDescReqT *req, void (*callback)(ZbZdoMatchDescRspT *ind, void *cb_arg), void *arg) { Zigbee_Cmd_Request_t *ipcc_req; + enum ZbStatusCodeT status; /* The callback must be static so we can receive multiple responses. We don't check here if * we're overwriting an existing callback, so application cannot effecticely perform more - * than one of these at a time. There should be no practical need for this though. - * There may even be no practical need for this API. */ + * than one of these at a time. */ + + /* Check if a request is already active */ + if (zdo_match_multi_cb != NULL) { + return ZB_ZDP_STATUS_TABLE_FULL; + } zdo_match_multi_cb = callback; + Pre_ZigbeeCmdProcessing(); ipcc_req = ZIGBEE_Get_OTCmdPayloadBuffer(); ipcc_req->ID = MSG_M4TOM0_ZDO_MATCH_DESC_MULTI; ipcc_req->Size = 1; ipcc_req->Data[0] = (uint32_t)req; ZIGBEE_CmdTransfer(); - return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); + status = (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); + if (status != ZB_STATUS_SUCCESS) { + zdo_match_multi_cb = NULL; + } + return status; /* Followed up in MSG_M0TOM4_ZDO_MATCH_DESC_MULTI_CB handler */ -} /* ZbZdoMatchDescMulti */ +} void ZbZdoDeviceAnnce(struct ZigBeeT *zb, ZbZdoDeviceAnnceT *deviceAnncePtr) @@ -2281,7 +2310,7 @@ ZbZdoDeviceAnnce(struct ZigBeeT *zb, ZbZdoDeviceAnnceT *deviceAnncePtr) ipcc_req->Size = 1; ipcc_req->Data[0] = (uint32_t)deviceAnncePtr; ZIGBEE_CmdTransfer(); -} /* ZbZdoDeviceAnnce */ +} void ZbZdoDeviceAnnceAlias(struct ZigBeeT *zb, ZbZdoDeviceAnnceT *deviceAnncePtr) @@ -2294,7 +2323,7 @@ ZbZdoDeviceAnnceAlias(struct ZigBeeT *zb, ZbZdoDeviceAnnceT *deviceAnncePtr) ipcc_req->Size = 1; ipcc_req->Data[0] = (uint32_t)deviceAnncePtr; ZIGBEE_CmdTransfer(); -} /* ZbZdoDeviceAnnceAlias */ +} enum ZbStatusCodeT ZbZdoBindReq(struct ZigBeeT *zb, ZbZdoBindReqT *req, @@ -2316,7 +2345,7 @@ ZbZdoBindReq(struct ZigBeeT *zb, ZbZdoBindReqT *req, ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZDO_BIND_CB handler */ -} /* ZbZdoBindReq */ +} enum ZbStatusCodeT ZbZdoUnbindReq(struct ZigBeeT *zb, ZbZdoBindReqT *req, @@ -2338,7 +2367,7 @@ ZbZdoUnbindReq(struct ZigBeeT *zb, ZbZdoBindReqT *req, ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZDO_UNBIND_CB handler */ -} /* ZbZdoUnbindReq */ +} enum ZbStatusCodeT ZbZdoLqiReq(struct ZigBeeT *zb, ZbZdoLqiReqT *req, void (*callback)(ZbZdoLqiRspT *rsp, void *cb_arg), void *arg) @@ -2359,7 +2388,7 @@ ZbZdoLqiReq(struct ZigBeeT *zb, ZbZdoLqiReqT *req, void (*callback)(ZbZdoLqiRspT ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZDO_MGMT_LQI_CB handler */ -} /* ZbZdoLqiReq */ +} enum ZbStatusCodeT ZbZdoMgmtBindReq(struct ZigBeeT *zb, ZbZdoMgmtBindReqT *req, @@ -2381,7 +2410,7 @@ ZbZdoMgmtBindReq(struct ZigBeeT *zb, ZbZdoMgmtBindReqT *req, ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZDO_MGMT_BIND_CB handler */ -} /* ZbZdoMgmtBindReq */ +} enum ZbStatusCodeT ZbZdoLeaveReq(struct ZigBeeT *zb, ZbZdoLeaveReqT *req, @@ -2403,7 +2432,7 @@ ZbZdoLeaveReq(struct ZigBeeT *zb, ZbZdoLeaveReqT *req, ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZDO_MGMT_LEAVE_CB handler */ -} /* ZbZdoLeaveReq */ +} enum ZbStatusCodeT ZbZdoPermitJoinReq(struct ZigBeeT *zb, ZbZdoPermitJoinReqT *req, @@ -2425,7 +2454,7 @@ ZbZdoPermitJoinReq(struct ZigBeeT *zb, ZbZdoPermitJoinReqT *req, ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZDO_MGMT_PERMIT_JOIN_CB handler */ -} /* ZbZdoPermitJoinReq */ +} enum ZbStatusCodeT ZbZdoNwkUpdateReq(struct ZigBeeT *zb, ZbZdoNwkUpdateReqT *req, @@ -2447,7 +2476,7 @@ ZbZdoNwkUpdateReq(struct ZigBeeT *zb, ZbZdoNwkUpdateReqT *req, ZIGBEE_CmdTransfer(); return (enum ZbStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZDO_MGMT_NWK_UPDATE_CB handler */ -} /* ZbZdoNwkUpdateReq */ +} /****************************************************************************** * ZCL @@ -2482,7 +2511,7 @@ ZbZclBasicPostAlarm(struct ZigBeeT *zb, uint8_t endpoint, uint8_t alarm_code) ipcc_req->Data[1] = (uint32_t)alarm_code; ZIGBEE_CmdTransfer(); return zb_ipc_m4_get_retval() != 0U ? true : false; -} /* ZbZclBasicPostAlarm */ +} void ZbZclBasicServerResetCmdConfig(struct ZigBeeT *zb, bool allow_reset) @@ -2495,7 +2524,7 @@ ZbZclBasicServerResetCmdConfig(struct ZigBeeT *zb, bool allow_reset) ipcc_req->Size = 1; ipcc_req->Data[0] = (uint32_t)allow_reset; ZIGBEE_CmdTransfer(); -} /* ZbZclBasicServerResetCmdConfig */ +} enum ZclStatusCodeT ZbZclBasicWriteDirect(struct ZigBeeT *zb, uint8_t endpoint, uint16_t attributeId, const void *ptr, unsigned int len) @@ -2512,7 +2541,7 @@ ZbZclBasicWriteDirect(struct ZigBeeT *zb, uint8_t endpoint, uint16_t attributeId ipcc_req->Data[3] = (uint32_t)len; ZIGBEE_CmdTransfer(); return (enum ZclStatusCodeT)zb_ipc_m4_get_retval(); -} /* ZbZclBasicWriteDirect */ +} bool ZbZclDiagnosticsServerAlloc(struct ZigBeeT *zb, uint8_t endpoint, uint16_t profileId, enum ZbStatusCodeT minSecurity) @@ -2542,7 +2571,7 @@ ZbZclAddEndpoint(struct ZigBeeT *zb, ZbApsmeAddEndpointReqT *addReqPtr, ZbApsmeA ipcc_req->Data[0] = (uint32_t)addReqPtr; ipcc_req->Data[1] = (uint32_t)addConfPtr; ZIGBEE_CmdTransfer(); -} /* ZbZclAddEndpoint */ +} void ZbZclRemoveEndpoint(struct ZigBeeT *zb, ZbApsmeRemoveEndpointReqT *req, ZbApsmeRemoveEndpointConfT *conf) @@ -2556,7 +2585,7 @@ ZbZclRemoveEndpoint(struct ZigBeeT *zb, ZbApsmeRemoveEndpointReqT *req, ZbApsmeR ipcc_req->Data[0] = (uint32_t)req; ipcc_req->Data[1] = (uint32_t)conf; ZIGBEE_CmdTransfer(); -} /* ZbZclRemoveEndpoint */ +} enum ZclStatusCodeT ZbZclReadReq(struct ZbZclClusterT *clusterPtr, ZbZclReadReqT *req, @@ -2579,7 +2608,7 @@ ZbZclReadReq(struct ZbZclClusterT *clusterPtr, ZbZclReadReqT *req, ZIGBEE_CmdTransfer(); return (enum ZclStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZCL_READ_CB handler */ -} /* ZbZclReadReq */ +} enum ZclStatusCodeT ZbZclWriteReq(struct ZbZclClusterT *clusterPtr, ZbZclWriteReqT *req, @@ -2602,7 +2631,7 @@ ZbZclWriteReq(struct ZbZclClusterT *clusterPtr, ZbZclWriteReqT *req, ZIGBEE_CmdTransfer(); return (enum ZclStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZCL_WRITE_CB handler */ -} /* ZbZclWriteReq */ +} enum ZclStatusCodeT ZbZclDiscoverAttrReq(struct ZbZclClusterT *clusterPtr, ZbZclDiscoverAttrReqT *req, @@ -2625,7 +2654,7 @@ ZbZclDiscoverAttrReq(struct ZbZclClusterT *clusterPtr, ZbZclDiscoverAttrReqT *re ZIGBEE_CmdTransfer(); return (enum ZclStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZCL_DISCOVER_ATTR_CB handler */ -} /* ZbZclDiscoverAttrReq */ +} uint8_t ZbZclGetNextSeqnum(void) @@ -2638,18 +2667,23 @@ ZbZclGetNextSeqnum(void) ipcc_req->Size = 0; ZIGBEE_CmdTransfer(); return (uint8_t)zb_ipc_m4_get_retval(); -} /* ZbZclGetNextSeqnum */ +} enum ZclStatusCodeT ZbZclCommandReq(struct ZigBeeT *zb, ZbZclCommandReqT *zclReq, void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg) { Zigbee_Cmd_Request_t *ipcc_req; - struct zb_ipc_m4_cb_info *info; + struct zb_ipc_m4_cb_info *info = NULL; - info = zb_ipc_m4_cb_info_alloc((void *)callback, arg); - if (info == NULL) { - return ZB_STATUS_ALLOC_FAIL; + if (callback != NULL) { + info = zb_ipc_m4_cb_info_alloc((void *)callback, arg); + if (info == NULL) { + return ZB_STATUS_ALLOC_FAIL; + } + if (ZbApsAddrIsBcast(&zclReq->dst)) { + info->zcl_recv_multi_rsp = true; /* callback only freed on ZCL_STATUS_TIMEOUT */ + } } Pre_ZigbeeCmdProcessing(); ipcc_req = ZIGBEE_Get_OTCmdPayloadBuffer(); @@ -2659,8 +2693,8 @@ ZbZclCommandReq(struct ZigBeeT *zb, ZbZclCommandReqT *zclReq, ipcc_req->Data[1] = (uint32_t)info; ZIGBEE_CmdTransfer(); return (enum ZclStatusCodeT)zb_ipc_m4_get_retval(); - /* Followed up in MSG_M0TOM4_ZCL_COMMAND_REQ_CB handler */ -} /* ZbZclCommandReq */ + /* Followed up in MSG_M0TOM4_ZCL_COMMAND_REQ_CB handler if callback != NULL */ +} enum ZclStatusCodeT ZbZclCommandNoResp(struct ZigBeeT *zb, ZbZclCommandReqT *req, @@ -2682,7 +2716,7 @@ ZbZclCommandNoResp(struct ZigBeeT *zb, ZbZclCommandReqT *req, ZIGBEE_CmdTransfer(); return (enum ZclStatusCodeT)zb_ipc_m4_get_retval(); /* Followed up in MSG_M0TOM4_ZCL_COMMAND_NO_RSP_CB handler */ -} /* ZbZclCommandNoResp */ +} void ZbZclSendDefaultResponse(struct ZbZclClusterT *clusterPtr, ZbApsdeDataIndT *dataIndPtr, @@ -2699,18 +2733,23 @@ ZbZclSendDefaultResponse(struct ZbZclClusterT *clusterPtr, ZbApsdeDataIndT *data ipcc_req->Data[2] = (uint32_t)zclHdrPtr; ipcc_req->Data[3] = (uint32_t)status; ZIGBEE_CmdTransfer(); -} /* ZbZclSendDefaultResponse */ +} enum ZclStatusCodeT ZbZclClusterCommandReq(struct ZbZclClusterT *clusterPtr, struct ZbZclClusterCommandReqT *req, void (*callback)(struct ZbZclCommandRspT *zcl_rsp, void *arg), void *arg) { Zigbee_Cmd_Request_t *ipcc_req; - struct zb_ipc_m4_cb_info *info; + struct zb_ipc_m4_cb_info *info = NULL; - info = zb_ipc_m4_cb_info_alloc((void *)callback, arg); - if (info == NULL) { - return ZB_STATUS_ALLOC_FAIL; + if (callback != NULL) { + info = zb_ipc_m4_cb_info_alloc((void *)callback, arg); + if (info == NULL) { + return ZB_STATUS_ALLOC_FAIL; + } + if (ZbApsAddrIsBcast(&req->dst)) { + info->zcl_recv_multi_rsp = true; /* callback only freed on ZCL_STATUS_TIMEOUT */ + } } Pre_ZigbeeCmdProcessing(); ipcc_req = ZIGBEE_Get_OTCmdPayloadBuffer(); @@ -2721,8 +2760,8 @@ ZbZclClusterCommandReq(struct ZbZclClusterT *clusterPtr, struct ZbZclClusterComm ipcc_req->Data[2] = (uint32_t)info; ZIGBEE_CmdTransfer(); return (enum ZclStatusCodeT)zb_ipc_m4_get_retval(); - /* Followed up in MSG_M0TOM4_ZCL_CLUSTER_CMD_REQ_CB handler */ -} /* ZbZclClusterCommandReq */ + /* Followed up in MSG_M0TOM4_ZCL_CLUSTER_CMD_REQ_CB handler if callback != NULL */ +} enum ZclStatusCodeT ZbZclClusterCommandRsp(struct ZbZclClusterT *clusterPtr, struct ZbZclAddrInfoT *dstInfo, @@ -2741,7 +2780,7 @@ ZbZclClusterCommandRsp(struct ZbZclClusterT *clusterPtr, struct ZbZclAddrInfoT * ipcc_req->Data[4] = (uint32_t)numPayloads; ZIGBEE_CmdTransfer(); return (enum ZclStatusCodeT)zb_ipc_m4_get_retval(); -} /* ZbZclClusterCommandRsp */ +} enum ZclStatusCodeT ZbZclClusterCommandRspWithCb(struct ZbZclClusterT *clusterPtr, struct ZbZclAddrInfoT *dstInfo, uint8_t cmdId, @@ -2751,11 +2790,12 @@ ZbZclClusterCommandRspWithCb(struct ZbZclClusterT *clusterPtr, struct ZbZclAddrI struct zb_ipc_m4_cb_info *info = NULL; enum ZclStatusCodeT status; - if (callback != NULL) { - info = zb_ipc_m4_cb_info_alloc((void *)callback, arg); - if (info == NULL) { - return ZCL_STATUS_ALLOC_FAIL; - } + if (callback == NULL) { + return ZbZclClusterCommandRsp(clusterPtr, dstInfo, cmdId, payloads, numPayloads); + } + info = zb_ipc_m4_cb_info_alloc((void *)callback, arg); + if (info == NULL) { + return ZCL_STATUS_ALLOC_FAIL; } Pre_ZigbeeCmdProcessing(); ipcc_req = ZIGBEE_Get_OTCmdPayloadBuffer(); @@ -2774,7 +2814,7 @@ ZbZclClusterCommandRspWithCb(struct ZbZclClusterT *clusterPtr, struct ZbZclAddrI } return status; /* Followed up in MSG_M0TOM4_ZCL_CLUSTER_CMD_RSP_CONF_CB handler */ -} /* ZbZclClusterCommandRspWithCb */ +} enum ZclStatusCodeT ZbZclSendClusterStatusResponse(struct ZbZclClusterT *clusterPtr, ZbApsdeDataIndT *dataIndPtr, @@ -2794,7 +2834,7 @@ ZbZclSendClusterStatusResponse(struct ZbZclClusterT *clusterPtr, ZbApsdeDataIndT ipcc_req->Data[5] = (uint32_t)zclPaylen; ZIGBEE_CmdTransfer(); return (enum ZclStatusCodeT)zb_ipc_m4_get_retval(); -} /* ZbZclSendClusterStatusResponse */ +} bool ZbZclClusterEndpointRegister(struct ZbZclClusterT *clusterPtr) @@ -2810,7 +2850,7 @@ ZbZclClusterEndpointRegister(struct ZbZclClusterT *clusterPtr) ZIGBEE_CmdTransfer(); retval = zb_ipc_m4_get_retval(); return retval != 0 ? true : false; -} /* ZbZclClusterEndpointRegister */ +} bool ZbZclClusterEndpointRemove(struct ZbZclClusterT *clusterPtr) @@ -2826,7 +2866,7 @@ ZbZclClusterEndpointRemove(struct ZbZclClusterT *clusterPtr) ZIGBEE_CmdTransfer(); retval = zb_ipc_m4_get_retval(); return retval != 0 ? true : false; -} /* ZbZclClusterEndpointRemove */ +} enum ZclStatusCodeT ZbZclClusterBind(struct ZbZclClusterT *clusterPtr, uint8_t endpoint, uint16_t profileId, enum ZbZclDirectionT direction) @@ -2844,7 +2884,7 @@ ZbZclClusterBind(struct ZbZclClusterT *clusterPtr, uint8_t endpoint, uint16_t pr ZIGBEE_CmdTransfer(); return (enum ZclStatusCodeT)zb_ipc_m4_get_retval(); /* Data indication callbacks go to MSG_M0TOM4_ZCL_CLUSTER_DATA_IND */ -} /* ZbZclClusterBind */ +} void ZbZclClusterUnbind(struct ZbZclClusterT *clusterPtr) @@ -2857,7 +2897,7 @@ ZbZclClusterUnbind(struct ZbZclClusterT *clusterPtr) ipcc_req->Size = 1; ipcc_req->Data[0] = (uint32_t)clusterPtr; ZIGBEE_CmdTransfer(); -} /* ZbZclClusterUnbind */ +} enum ZclStatusCodeT ZbZclClusterLoopbackBind(struct ZbZclClusterT *clusterPtr, struct ZbApsFilterT *filter) @@ -2873,7 +2913,7 @@ ZbZclClusterLoopbackBind(struct ZbZclClusterT *clusterPtr, struct ZbApsFilterT * ZIGBEE_CmdTransfer(); return (enum ZclStatusCodeT)zb_ipc_m4_get_retval(); /* Data indication callbacks go to MSG_M0TOM4_ZCL_CLUSTER_DATA_IND */ -} /* ZbZclClusterLoopbackBind */ +} void ZbZclClusterLoopbackUnbind(struct ZbZclClusterT *clusterPtr, struct ZbApsFilterT *filter) @@ -2887,7 +2927,7 @@ ZbZclClusterLoopbackUnbind(struct ZbZclClusterT *clusterPtr, struct ZbApsFilterT ipcc_req->Data[0] = (uint32_t)clusterPtr; ipcc_req->Data[1] = (uint32_t)filter; ZIGBEE_CmdTransfer(); -} /* ZbZclClusterLoopbackUnbind */ +} enum ZclStatusCodeT ZbZclClusterRegisterAlarmResetHandler(struct ZbZclClusterT *clusterPtr, ZbZclAlarmResetFuncT callback) @@ -2905,7 +2945,7 @@ ZbZclClusterRegisterAlarmResetHandler(struct ZbZclClusterT *clusterPtr, ZbZclAla status = (enum ZclStatusCodeT)zb_ipc_m4_get_retval(); return status; /* Callbacks followed up in MSG_M0TOM4_ZCL_CLUSTER_ALARM_CB handler. */ -} /* ZbZclClusterRegisterAlarmResetHandler */ +} void ZbZclClusterRemoveAlarmResetHandler(struct ZbZclClusterT *clusterPtr) @@ -2933,7 +2973,7 @@ ZbZclClusterSendAlarm(struct ZbZclClusterT *clusterPtr, uint8_t src_endpoint, ui ipcc_req->Data[1] = (uint32_t)src_endpoint; ipcc_req->Data[2] = (uint32_t)alarm_code; ZIGBEE_CmdTransfer(); -} /* ZbZclClusterSendAlarm */ +} /****************************************************************************** * SE Key Exchange @@ -2967,7 +3007,7 @@ ZbZclKeWithDevice(struct ZigBeeT *zb, uint64_t partnerAddr, bool aps_req_key, } return status; /* Followed up in MSG_M0TOM4_ZCL_KE_WITH_DEVICE_CB handler */ -} /* ZbZclKeWithDevice */ +} /****************************************************************************** * Certification Test Hooks @@ -2983,7 +3023,7 @@ ZbTestCaseClear(struct ZigBeeT *zb) ipcc_req->ID = MSG_M4TOM0_TEST_CASE_CLEAR; ipcc_req->Size = 0; ZIGBEE_CmdTransfer(); -} /* ZbTestCaseClear */ +} uint32_t ZbTestCaseCurrent(struct ZigBeeT *zb) @@ -2996,7 +3036,7 @@ ZbTestCaseCurrent(struct ZigBeeT *zb) ipcc_req->Size = 0; ZIGBEE_CmdTransfer(); return zb_ipc_m4_get_retval(); -} /* ZbTestCaseCurrent */ +} void ZbTestCaseDisable(struct ZigBeeT *zb, enum ZbTestcaseT testcase) @@ -3009,7 +3049,7 @@ ZbTestCaseDisable(struct ZigBeeT *zb, enum ZbTestcaseT testcase) ipcc_req->Size = 1; ipcc_req->Data[0] = (uint32_t)testcase; ZIGBEE_CmdTransfer(); -} /* ZbTestCaseDisable */ +} void ZbTestCaseEnable(struct ZigBeeT *zb, enum ZbTestcaseT testcase) @@ -3022,7 +3062,7 @@ ZbTestCaseEnable(struct ZigBeeT *zb, enum ZbTestcaseT testcase) ipcc_req->Size = 1; ipcc_req->Data[0] = (uint32_t)testcase; ZIGBEE_CmdTransfer(); -} /* ZbTestCaseEnable */ +} bool ZbApsFragDropTxAdd(struct ZigBeeT *zb, uint8_t blockNum) @@ -3038,7 +3078,7 @@ ZbApsFragDropTxAdd(struct ZigBeeT *zb, uint8_t blockNum) ZIGBEE_CmdTransfer(); retval = zb_ipc_m4_get_retval(); return retval != 0 ? true : false; -} /* ZbApsFragDropTxAdd */ +} void ZbApsFragDropTxClear(struct ZigBeeT *zb) @@ -3050,7 +3090,7 @@ ZbApsFragDropTxClear(struct ZigBeeT *zb) ipcc_req->ID = MSG_M4TOM0_APS_FRAG_DROP_CLEAR; ipcc_req->Size = 0; ZIGBEE_CmdTransfer(); -} /* ZbApsFragDropTxClear */ +} /****************************************************************************** * AES & Hashing @@ -3064,7 +3104,7 @@ ZbAesMmoHash(uint8_t const *data, const unsigned int length, uint8_t *hash) ZbHashInit(&newHash); ZbHashAdd(&newHash, data, length); ZbHashDigest(&newHash, hash); -} /* ZbAesMmoHash */ +} void ZbHashInit(struct ZbHash *h) @@ -3072,7 +3112,7 @@ ZbHashInit(struct ZbHash *h) (void)memset(h->m, 0, sizeof(h->m)); (void)memset(h->hash, 0, sizeof(h->hash)); h->length = 0; -} /* ZbHashInit */ +} void ZbHashAdd(struct ZbHash *h, const void *data, uint32_t len) @@ -3087,7 +3127,7 @@ ZbHashAdd(struct ZbHash *h, const void *data, uint32_t len) ipcc_req->Data[1] = (uint32_t)data; ipcc_req->Data[2] = (uint32_t)len; ZIGBEE_CmdTransfer(); -} /* ZbHashAdd */ +} void ZbHashByte(struct ZbHash *h, uint8_t byte) @@ -3101,7 +3141,7 @@ ZbHashByte(struct ZbHash *h, uint8_t byte) ipcc_req->Data[0] = (uint32_t)h; ipcc_req->Data[1] = (uint32_t)byte; ZIGBEE_CmdTransfer(); -} /* ZbHashByte */ +} void ZbHashDigest(struct ZbHash *h, void *digest) @@ -3115,7 +3155,7 @@ ZbHashDigest(struct ZbHash *h, void *digest) ipcc_req->Data[0] = (uint32_t)h; ipcc_req->Data[1] = (uint32_t)digest; ZIGBEE_CmdTransfer(); -} /* ZbHashDigest */ +} /****************************************************************************** * Memory Helpers @@ -3200,9 +3240,9 @@ WpanCrc(uint16_t crc, const void *dataPtr, unsigned int dataLen) */ while (dataLen--) { crc = (crc >> 8) ^ wpanCrcTable[(crc & 0xff) ^ *p++]; - } /* while */ + } return crc; -} /* WpanCrc */ +} /** * @brief This function is used to manage all the callbacks used by the @@ -3227,24 +3267,6 @@ Zigbee_CallBackProcessing(void) p_notification = ZIGBEE_Get_NotificationPayloadBuffer(); switch (p_notification->ID) { - case MSG_M0TOM4_ZB_MALLOC: - { - void *ptr; - - assert(p_notification->Size == 1); - ptr = malloc((uint32_t)p_notification->Data[0]); - - /* Return ptr in second argument */ - p_notification->Data[1] = (uint32_t) ptr; - - break; - } - - case MSG_M0TOM4_ZB_FREE: - assert(p_notification->Size == 1); - free((void *)p_notification->Data[0]); - break; - case MSG_M0TOM4_FILTER_MSG_CB: { struct zb_msg_filter_cb_info *cb_info; @@ -3274,7 +3296,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_STARTUP_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(enum ZbStatusCodeT status, void *arg); callback = (void (*)(enum ZbStatusCodeT status, void *arg))info->callback; @@ -3285,7 +3307,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_STARTUP_REJOIN_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbNlmeJoinConfT *conf, void *arg); callback = (void (*)(ZbNlmeJoinConfT *conf, void *arg))info->callback; @@ -3296,7 +3318,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_STARTUP_FINDBIND_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(enum ZbStatusCodeT status, void *arg); callback = (void (*)(enum ZbStatusCodeT status, void *arg))info->callback; @@ -3307,7 +3329,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_STARTUP_TCSO_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(enum ZbTcsoStatusT status, void *arg); callback = (void (*)(enum ZbTcsoStatusT status, void *arg))info->callback; @@ -3318,7 +3340,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_STARTUP_TC_REJOIN_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(enum ZbStatusCodeT status, void *arg); callback = (void (*)(enum ZbStatusCodeT status, void *arg))info->callback; @@ -3335,7 +3357,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZB_LEAVE_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(enum ZbStatusCodeT status, void *arg); callback = (void (*)(enum ZbStatusCodeT status, void *arg))info->callback; @@ -3346,7 +3368,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_APSDE_DATA_REQ_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbApsdeDataConfT *conf, void *arg); callback = (void (*)(ZbApsdeDataConfT *conf, void *arg))info->callback; @@ -3391,7 +3413,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_NLME_NET_DISC_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbNlmeNetDiscConfT *conf, void *arg); callback = (void (*)(ZbNlmeNetDiscConfT *conf, void *arg))info->callback; @@ -3402,7 +3424,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_NLME_LEAVE_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(struct ZbNlmeLeaveConfT *conf, void *arg); callback = (void (*)(struct ZbNlmeLeaveConfT *conf, void *arg))info->callback; @@ -3413,7 +3435,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_NLME_SYNC_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbNlmeSyncConfT *conf, void *arg); callback = (void (*)(ZbNlmeSyncConfT *discConf, void *arg))info->callback; @@ -3424,7 +3446,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_NLME_ROUTE_DISC_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbNlmeRouteDiscConfT *discConf, void *cbarg); callback = (void (*)(ZbNlmeRouteDiscConfT *discConf, void *cbarg))info->callback; @@ -3451,7 +3473,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZDO_NWK_ADDR_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbZdoNwkAddrRspT *rsp, void *cbarg); callback = (void (*)(ZbZdoNwkAddrRspT *rsp, void *cbarg))info->callback; @@ -3462,7 +3484,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZDO_IEEE_ADDR_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbZdoIeeeAddrRspT *rsp, void *cbarg); callback = (void (*)(ZbZdoIeeeAddrRspT *rsp, void *cbarg))info->callback; @@ -3473,7 +3495,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZDO_NODE_DESC_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbZdoNodeDescRspT *rsp, void *cbarg); callback = (void (*)(ZbZdoNodeDescRspT *rsp, void *cbarg))info->callback; @@ -3484,7 +3506,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZDO_POWER_DESC_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbZdoPowerDescRspT *rsp, void *cbarg); callback = (void (*)(ZbZdoPowerDescRspT *rsp, void *cbarg))info->callback; @@ -3495,7 +3517,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZDO_SIMPLE_DESC_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbZdoSimpleDescRspT *rsp, void *cbarg); callback = (void (*)(ZbZdoSimpleDescRspT *rsp, void *cbarg))info->callback; @@ -3506,7 +3528,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZDO_ACTIVE_EP_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbZdoActiveEpRspT *rsp, void *cbarg); callback = (void (*)(ZbZdoActiveEpRspT *rsp, void *cbarg))info->callback; @@ -3517,7 +3539,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZDO_MATCH_DESC_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbZdoMatchDescRspT *rsp, void *cbarg); callback = (void (*)(ZbZdoMatchDescRspT *rsp, void *cbarg))info->callback; @@ -3527,16 +3549,24 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZDO_MATCH_DESC_MULTI_CB: if (zdo_match_multi_cb != NULL) { - assert(p_notification->Size == 2); - zdo_match_multi_cb((ZbZdoMatchDescRspT *)p_notification->Data[0], (void *)p_notification->Data[1]); - /* Don't release zdo_match_multi_cb */ + ZbZdoMatchDescRspT *rsp; + + /* Note, we're not using zb_ipc_m4_cb_info for this API, so we don't need + * the callback argument. */ + assert(p_notification->Size == 1); + rsp = (ZbZdoMatchDescRspT *)p_notification->Data[0]; + zdo_match_multi_cb(rsp, NULL); + if (rsp->status == ZB_ZDP_STATUS_TIMEOUT) { + /* Release the callback */ + zdo_match_multi_cb = NULL; + } } break; case MSG_M0TOM4_ZDO_BIND_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbZdoBindRspT *rsp, void *cbarg); callback = (void (*)(ZbZdoBindRspT *rsp, void *cbarg))info->callback; @@ -3547,7 +3577,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZDO_UNBIND_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbZdoBindRspT *rsp, void *cbarg); callback = (void (*)(ZbZdoBindRspT *rsp, void *cbarg))info->callback; @@ -3558,7 +3588,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZDO_MGMT_LQI_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbZdoLqiRspT *rsp, void *cbarg); callback = (void (*)(ZbZdoLqiRspT *rsp, void *cbarg))info->callback; @@ -3569,7 +3599,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZDO_MGMT_BIND_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbZdoMgmtBindRspT *rsp, void *cbarg); callback = (void (*)(ZbZdoMgmtBindRspT *rsp, void *cbarg))info->callback; @@ -3580,7 +3610,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZDO_MGMT_LEAVE_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbZdoLeaveRspT *rsp, void *cbarg); callback = (void (*)(ZbZdoLeaveRspT *rsp, void *cbarg))info->callback; @@ -3591,7 +3621,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZDO_MGMT_PERMIT_JOIN_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbZdoPermitJoinRspT *rsp, void *cbarg); callback = (void (*)(ZbZdoPermitJoinRspT *rsp, void *cbarg))info->callback; @@ -3602,7 +3632,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZDO_MGMT_NWK_UPDATE_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbZdoNwkUpdateNotifyT *rsp, void *cbarg); callback = (void (*)(ZbZdoNwkUpdateNotifyT *rsp, void *cbarg))info->callback; @@ -3643,18 +3673,28 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZCL_CLUSTER_CMD_REQ_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { - void (*callback)(struct ZbZclCommandRspT *rsp, void *cbarg); + /* Note: shouldn't get here if callback was NULL in request, so info should + * always be non-NULL. */ + if (info != NULL) { + struct ZbZclCommandRspT *zcl_rsp = (struct ZbZclCommandRspT *)p_notification->Data[0]; - callback = (void (*)(struct ZbZclCommandRspT *rsp, void *cbarg))info->callback; - callback((struct ZbZclCommandRspT *)p_notification->Data[0], info->arg); + if (info->callback != NULL) { + void (*callback)(struct ZbZclCommandRspT *rsp, void *cbarg); + + callback = (void (*)(struct ZbZclCommandRspT *rsp, void *cbarg))info->callback; + callback(zcl_rsp, info->arg); + } + if (info->zcl_recv_multi_rsp && (zcl_rsp->status != ZCL_STATUS_TIMEOUT)) { + /* Don't free the callback yet */ + info = NULL; + } } break; case MSG_M0TOM4_ZCL_CLUSTER_CMD_RSP_CONF_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbApsdeDataConfT *conf, void *arg); callback = (void (*)(ZbApsdeDataConfT *conf, void *arg))info->callback; @@ -3668,11 +3708,21 @@ Zigbee_CallBackProcessing(void) assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { - int (*callback)(struct ZbZclCommandRspT *conf, void *arg); + /* Note: shouldn't get here if callback was NULL in request, so info should + * always be non-NULL. */ + if (info != NULL) { + struct ZbZclCommandRspT *zcl_rsp = (struct ZbZclCommandRspT *)p_notification->Data[0]; + + if (info->callback != NULL) { + int (*callback)(struct ZbZclCommandRspT *conf, void *arg); - callback = (int (*)(struct ZbZclCommandRspT *rsp, void *arg))info->callback; - err = callback((struct ZbZclCommandRspT *)p_notification->Data[0], info->arg); + callback = (int (*)(struct ZbZclCommandRspT *rsp, void *arg))info->callback; + err = callback(zcl_rsp, info->arg); + } + if (info->zcl_recv_multi_rsp && (zcl_rsp->status != ZCL_STATUS_TIMEOUT)) { + /* Don't free the callback yet */ + info = NULL; + } } /* Return err in second argument */ p_notification->Data[1] = (uint32_t)err; @@ -3682,7 +3732,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZCL_COMMAND_NO_RSP_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbApsdeDataConfT *conf, void *arg); callback = (void (*)(ZbApsdeDataConfT *conf, void *arg))info->callback; @@ -3693,7 +3743,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZCL_READ_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbZclReadRspT *rsp, void *cbarg); callback = (void (*)(ZbZclReadRspT *rsp, void *cbarg))info->callback; @@ -3704,7 +3754,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZCL_WRITE_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbZclWriteRspT *rsp, void *cbarg); callback = (void (*)(ZbZclWriteRspT *rsp, void *cbarg))info->callback; @@ -3715,7 +3765,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZCL_DISCOVER_ATTR_CB: assert(p_notification->Size == 2); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[1]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(ZbZclDiscoverAttrRspT *rsp, void *cbarg); callback = (void (*)(ZbZclDiscoverAttrRspT *rsp, void *cbarg))info->callback; @@ -3726,7 +3776,7 @@ Zigbee_CallBackProcessing(void) case MSG_M0TOM4_ZCL_KE_WITH_DEVICE_CB: assert(p_notification->Size == 5); info = (struct zb_ipc_m4_cb_info *)p_notification->Data[4]; - if (info->callback != NULL) { + if ((info != NULL) && (info->callback != NULL)) { void (*callback)(uint64_t partnerAddr, uint16_t keSuite, enum ZbZclKeyStatusT key_status, void *arg); uint64_t partnerAddr; @@ -3745,20 +3795,59 @@ Zigbee_CallBackProcessing(void) zb_ipc_m4_cb_info_free(info); } - TL_ZIGBEE_SendAckAfterAppliNotifFromM0(); + TL_ZIGBEE_SendM4AckToM0Notify(); return status; -} /* Zigbee_CallBackProcessing */ +} HAL_StatusTypeDef -Zigbee_LoggingProcessing(void) +Zigbee_M0RequestProcessing(void) { - const char *log_str; - Zigbee_Cmd_Request_t *p_logging = ZIGBEE_Get_LoggingPayloadBuffer(); + HAL_StatusTypeDef status = HAL_OK; + Zigbee_Cmd_Request_t *p_logging = ZIGBEE_Get_M0RequestPayloadBuffer(); + + switch (p_logging->ID) { + case MSG_M0TOM4_ZB_LOGGING: + { + const char *log_str; - assert(p_logging->Size == 1); - log_str = (const char *)p_logging->Data[0]; - cli_port_print_msg(NULL, log_str); + assert(p_logging->Size == 1); + log_str = (const char *)p_logging->Data[0]; + cli_port_print_msg(NULL, log_str); + break; + } + + case MSG_M0TOM4_ZB_MALLOC: + { + void *ptr; + + assert(p_logging->Size == 1); + ptr = malloc((uint32_t)p_logging->Data[0]); + /* Return ptr in second argument */ + p_logging->Data[1] = (uint32_t)ptr; + break; + } - TL_ZIGBEE_SendAckAfterAppliLoggingFromM0(); - return HAL_OK; -} /* Zigbee_LoggingProcessing */ + case MSG_M0TOM4_ZB_FREE: + assert(p_logging->Size == 1); + free((void *)p_logging->Data[0]); + break; + + default: + status = HAL_ERROR; + break; + } + + TL_ZIGBEE_SendM4AckToM0Request(); + return status; +} + + +/* Function which needs to be overloaded for test purpose + * In particular when using the ZbCli interface + */ +__weak void cli_port_print_msg(struct cli_app *cli_p, const char *msg) +{ + UNUSED(cli_p); + UNUSED(msg); + +} diff --git a/Middlewares/ST/STM32_WPAN/zigbee/lib/stm32wb_zigbee_wb_lib.a b/Middlewares/ST/STM32_WPAN/zigbee/lib/stm32wb_zigbee_wb_lib.a index 4524b23de..a0b936fd8 100644 Binary files a/Middlewares/ST/STM32_WPAN/zigbee/lib/stm32wb_zigbee_wb_lib.a and b/Middlewares/ST/STM32_WPAN/zigbee/lib/stm32wb_zigbee_wb_lib.a differ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/platform/flash_emulation.h b/Middlewares/ST/STM32_WPAN/zigbee/platform/flash_emulation.h index 2829b6114..21a7ee9cf 100644 --- a/Middlewares/ST/STM32_WPAN/zigbee/platform/flash_emulation.h +++ b/Middlewares/ST/STM32_WPAN/zigbee/platform/flash_emulation.h @@ -37,8 +37,14 @@ #ifndef __FLASH_EMULATION_H #define __FLASH_EMULATION_H +#ifdef STM32WB35xx +#error TMP_STORAGE_BUF_ADDR will be determined during Zigbee porting on Little Dory +#define TMP_STORAGE_BUF_ADDR xxx /* Should be __ICFEDIT_region_RAM_end__ inside the scatter file*/ +#define TMP_STORAGE_BUF_SIZE (xxx - TMP_STORAGE_BUF_ADDR) +#else #define TMP_STORAGE_BUF_ADDR 0x2002F000 /* Should be __ICFEDIT_region_RAM_end__ inside the scatter file*/ #define TMP_STORAGE_BUF_SIZE (0x2002FFFF - TMP_STORAGE_BUF_ADDR) +#endif uint32_t utilsFlashGetSize(void); uint32_t utilsFlashWrite(uint32_t aAddress, uint8_t *aData, uint32_t aSize); diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/extras/zigbee.extras.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/extras/zigbee.extras.h new file mode 100644 index 000000000..6637f4be4 --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/extras/zigbee.extras.h @@ -0,0 +1,32 @@ +/* Copyright [2009 - 2019] Exegin Technologies Limited. All rights reserved. */ + +#ifndef ZIGBEE_EXTRAS_H +#define ZIGBEE_EXTRAS_H + +#include "zigbee.h" + +const char * ZbStatusToStr(enum ZbStatusCodeT statusCode); +const char * ZbBdbCommissStatusToStr(enum ZbBdbCommissioningStatusT status); +const char * ZbApsDeviceStatusToStr(enum ZbApsmeDeviceStatusT status); + +/* NWK functions required for zigbee testing */ +void ZbNwkAddrSetNextChildAddr(struct ZigBeeT *zb, uint16_t nextChildAddr); +bool ZbNwkTestSendUnknownCommand(struct ZigBeeT *zb, uint16_t nwkDstAddr, + uint8_t nwkProtoVer); + +/* APS functions required for zigbee testing */ +void ZbApsmeRemoveDeviceReq_NoApsSec(struct ZigBeeT *zb, ZbApsmeRemoveDeviceReqT *req); + +/* ZDO functions required for zigbee testing */ +void ZbZdoNwkAddrReq_NoSec(struct ZigBeeT *zb, ZbZdoNwkAddrReqT *req); +void ZbZdoNwkAddrReq_InterPan(struct ZigBeeT *zb, ZbZdoNwkAddrReqT *req, uint16_t panid); +void ZbZdoNodeDescReq_NoSec(struct ZigBeeT *zb, ZbZdoNodeDescReqT *req); +void ZbZdoNodeDescReq_nwk_ext_bit(struct ZigBeeT *zb, ZbZdoNodeDescReqT *req, uint64_t dstExtAddr); +void ZbZdoDiscoveryCacheReq(struct ZigBeeT *zb, uint16_t dstAddr); +void ZbZdoUnsolicitedEnhUpdateNotify(struct ZigBeeT *zb, uint16_t dstAddr); + +/* ZDO string conversion helper functions */ +const char * ZbZdoNodeTypeToStr(const uint8_t type); +void ZbZdoNodeBandsStr(const uint8_t band, char *buf, const unsigned int max_len); + +#endif diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/key/zcl.cbke.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/key/zcl.cbke.h index 84dccc6df..2c15c939a 100644 --- a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/key/zcl.cbke.h +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/key/zcl.cbke.h @@ -79,7 +79,7 @@ typedef struct { uint32_t validTo; uint64_t subject; uint8_t keyUsage; - size_t publicLen; + unsigned int publicLen; uint8_t publicKey[CBKE2_CERT_PUBLIC_KEY_SIZE]; } ZbZclCertificateT; @@ -91,7 +91,7 @@ struct ZbZclKeClusterT; */ enum ZclStatusCodeT ZbZclKeAddCbke(struct ZbZclClusterT *clusterPtr, const struct ZbZclCbkeInfoT *info); enum ZclStatusCodeT ZbZclKeAddCbke2(struct ZbZclClusterT *clusterPtr, const struct ZbZclCbke2InfoT *info); -ZbZclCertificateT * ZbZclParseCertificate(ZbZclCertificateT *dst, const void *src, size_t len); +ZbZclCertificateT * ZbZclParseCertificate(ZbZclCertificateT *dst, const void *src, unsigned int len); enum ZbZclKeyStatusT ZbZclCbke2ReconstPrivateKey(struct ZigBeeT *zb, const uint8_t *icu, const uint8_t *se, const uint8_t *du, uint8_t *wu); /* Helper function to reconstruct a private key. */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/se/zcl.message.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/se/zcl.message.h new file mode 100644 index 000000000..ce9543c44 --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/se/zcl.message.h @@ -0,0 +1,188 @@ +/* Copyright [2009 - 2019] Exegin Technologies Limited. All rights reserved. */ + +/*-------------------------------------------------------------------------- + * DESCRIPTION + * Interface definition for the SE Messaging cluster. + *-------------------------------------------------------------------------- + */ +#ifndef ZCL_MESSAGE_H +# define ZCL_MESSAGE_H + +#include "zcl/zcl.h" + +/* Server Generated Commands */ +enum { + ZCL_MESSAGE_SVR_CMD_DISPLAY_MESSAGE = 0x00, + ZCL_MESSAGE_SVR_CMD_CANCEL_MESSAGE = 0x01, + ZCL_MESSAGE_SVR_CMD_DISPLAY_PROTECTED_MESSAGE = 0x02, + ZCL_MESSAGE_SVR_CMD_CANCEL_ALL_MESSAGES = 0x03 +}; + +/* Client Generated Commands */ +enum { + ZCL_MESSAGE_CLI_CMD_GET_LAST_MESSAGE = 0x00, + ZCL_MESSAGE_CLI_CMD_MESSAGE_CONFIRM = 0x01, + ZCL_MESSAGE_CLI_CMD_GET_MESSAGE_CANCELLATION = 0x02 +}; + +enum { + ZCL_MESSAGE_CTRL_TRANS_NORMAL = 0, + ZCL_MESSAGE_CTRL_TRANS_BOTH = 1, + ZCL_MESSAGE_CTRL_TRANS_INTERPAN = 2 +}; + +enum { + ZCL_MESSAGE_CTRL_IMPTNCE_LOW = 0, + ZCL_MESSAGE_CTRL_IMPTNCE_MEDIUM = 1, + ZCL_MESSAGE_CTRL_IMPTNCE_HIGH = 2, + ZCL_MESSAGE_CTRL_IMPTNCE_CRITICAL = 3 +}; + +#define ZCL_MESSAGE_MAX_LENGTH 59U /* D.5.2.3.1.1.1 */ + +struct ZbZclMsgMessageT { + uint32_t message_id; + uint32_t start_time; /* UTC Seconds */ + uint16_t duration; /* Minutes */ + uint8_t message_control; /* ZbZclMessageControlSet - transmission, importance, confirm required, confirm enhanced */ + char message_str[ZCL_MESSAGE_MAX_LENGTH + 1U]; /* UTF-8 */ + uint8_t extended_control; +}; + +#define ZCL_MESSAGE_CTRL_EXTENDED_CONFIRMED 0x01U // message has been confirmed + +/* Message Control fields. */ +#define ZCL_MESSAGE_CTRL_TRANS_MASK 0x03U +#define ZCL_MESSAGE_CTRL_TRANS_OFFSET 0U +#define ZCL_MESSAGE_CTRL_TRANS_GET(_c_) (((_c_) & ZCL_MESSAGE_CTRL_TRANS_MASK) >> ZCL_MESSAGE_CTRL_TRANS_OFFSET) + +#define ZCL_MESSAGE_CTRL_IMPTNCE_MASK 0x0cU +#define ZCL_MESSAGE_CTRL_IMPTNCE_OFFSET 2U +#define ZCL_MESSAGE_CTRL_IMPTNCE_GET(_c_) (((_c_) & ZCL_MESSAGE_CTRL_IMPTNCE_MASK) >> ZCL_MESSAGE_CTRL_IMPTNCE_OFFSET) + +#define ZCL_MESSAGE_CTRL_ENH_CONF_MASK 0x20U +#define ZCL_MESSAGE_CTRL_ENH_CONF_OFFSET 5U +#define ZCL_MESSAGE_CTRL_ENH_CONF_GET(_c_) (((_c_) & ZCL_MESSAGE_CTRL_ENH_CONF_MASK) >> ZCL_MESSAGE_CTRL_ENH_CONF_OFFSET) + +#define ZCL_MESSAGE_CTRL_CONFIRMATION_MASK 0x80U +#define ZCL_MESSAGE_CTRL_CONFIRMATION_OFFSET 7U +#define ZCL_MESSAGE_CTRL_CONFIRMATION_GET(_c_) (((_c_) & ZCL_MESSAGE_CTRL_CONFIRMATION_MASK) >> ZCL_MESSAGE_CTRL_CONFIRMATION_OFFSET) + +/* Message Control "Set" Helper */ +static inline void +ZbZclMessageControlSet(struct ZbZclMsgMessageT *msg, uint8_t transmission, + uint8_t importance, uint8_t confirm, uint8_t enh_confirm) +{ + msg->message_control = 0; + msg->message_control |= ((transmission << ZCL_MESSAGE_CTRL_TRANS_OFFSET) & ZCL_MESSAGE_CTRL_TRANS_MASK); + msg->message_control |= ((importance << ZCL_MESSAGE_CTRL_IMPTNCE_OFFSET) & ZCL_MESSAGE_CTRL_IMPTNCE_MASK); + msg->message_control |= ((confirm << ZCL_MESSAGE_CTRL_CONFIRMATION_OFFSET) & ZCL_MESSAGE_CTRL_CONFIRMATION_MASK); + msg->message_control |= ((enh_confirm << ZCL_MESSAGE_CTRL_ENH_CONF_OFFSET) & ZCL_MESSAGE_CTRL_ENH_CONF_MASK); +} + +/* Cancel Message Descriptor */ +struct ZbZclMsgMessageCancelT { + uint32_t message_id; + uint8_t control; +}; + +/* Cancel All Messages Descriptor */ +struct ZbZclMsgMessageCancelAllT { + uint32_t implementation_time; +}; + +/* Message Confirmation Descriptor */ +struct ZbZclMsgConfirmT { + uint32_t message_id; + uint32_t confirm_time; +}; + +/* Message Confirmation Extended Optional */ +/* EXEGIN - where in which spec is this message defined? */ +#define ZCL_MESSAGE_CONFIRM_ENH_RSP_MAX_LEN 32U + +struct ZbZclMsgConfirmEnhT { + uint32_t message_id; + uint32_t confirm_time; + uint8_t confirm_control; + char confirm_response[ZCL_MESSAGE_CONFIRM_ENH_RSP_MAX_LEN + 1U]; +}; + +#define ZCL_MESSAGE_CONF_RSP_LEN 21U + +struct ZbZclMsgMessageConfT { + uint32_t message_id; + uint32_t confirm_time; + bool has_confirm_control; + uint8_t confirm_control; + bool has_confirm_response; + uint8_t confirm_response[ZCL_MESSAGE_CONF_RSP_LEN]; +}; + +struct ZbZclMsgGetMsgCancellationT { + uint32_t earliest_impl_time; +}; + +/* + * Server + */ +struct ZbZclMsgServerCallbacksT { + enum ZclStatusCodeT (*get_last_message)(struct ZbZclClusterT *cluster, void *arg, + struct ZbZclAddrInfoT *srcInfo); + + enum ZclStatusCodeT (*message_confirmation)(struct ZbZclClusterT *cluster, void *arg, + struct ZbZclMsgMessageConfT *conf, struct ZbZclAddrInfoT *srcInfo); + + enum ZclStatusCodeT (*get_message_cancellation)(struct ZbZclClusterT *cluster, void *arg, + struct ZbZclMsgGetMsgCancellationT *req, struct ZbZclAddrInfoT *source); +}; + +struct ZbZclClusterT * ZbZclMsgServerAlloc(struct ZigBeeT *zb, uint8_t endpoint, + struct ZbZclMsgServerCallbacksT *callbacks, void *arg); + +enum ZclStatusCodeT ZbZclMsgServerDisplayMessageReq(struct ZbZclClusterT *cluster, const struct ZbApsAddrT *dst, + struct ZbZclMsgMessageT *msg, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +enum ZclStatusCodeT ZbZclMsgServerDisplayProtectedMsgReq(struct ZbZclClusterT *cluster, const struct ZbApsAddrT *dst, + struct ZbZclMsgMessageT *msg, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +enum ZclStatusCodeT ZbZclMsgServerCancelMessageReq(struct ZbZclClusterT *cluster, const struct ZbApsAddrT *dst, + struct ZbZclMsgMessageCancelT *cancel, void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +enum ZclStatusCodeT ZbZclMsgServerCancelAllReq(struct ZbZclClusterT *clusterPtr, const struct ZbApsAddrT *dst, + struct ZbZclMsgMessageCancelAllT *cancel_all, void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +/* + * Client + */ +struct ZbZclMsgClientCallbacksT { + enum ZclStatusCodeT (*display_message)(struct ZbZclClusterT *cluster, void *arg, + struct ZbZclMsgMessageT *msg, struct ZbZclAddrInfoT *srcInfo); + + enum ZclStatusCodeT (*cancel_message)(struct ZbZclClusterT *cluster, void *arg, + struct ZbZclMsgMessageCancelT *cancel, struct ZbZclAddrInfoT *srcInfo); + + enum ZclStatusCodeT (*cancel_all_messages)(struct ZbZclClusterT *cluster, void *arg, + struct ZbZclMsgMessageCancelAllT *cancel_all, struct ZbZclAddrInfoT *srcInfo); + + enum ZclStatusCodeT (*display_protected_message)(struct ZbZclClusterT *cluster, void *arg, + struct ZbZclMsgMessageT *msg, struct ZbZclAddrInfoT *srcInfo); +}; + +struct ZbZclClusterT * ZbZclMsgClientAlloc(struct ZigBeeT *zb, uint8_t endpoint, + struct ZbZclMsgClientCallbacksT *callbacks, void *arg); + +enum ZclStatusCodeT ZbZclMsgClientGetLastReq(struct ZbZclClusterT *cluster, const struct ZbApsAddrT *dst, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +enum ZclStatusCodeT ZbZclMsgClientConfReq(struct ZbZclClusterT *cluster, const struct ZbApsAddrT *dst, + struct ZbZclMsgConfirmT *msg_conf, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +enum ZclStatusCodeT ZbZclMsgClientGetMsgCancelReq(struct ZbZclClusterT *cluster, + const struct ZbApsAddrT *dst, uint32_t earliestTime, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +#endif /* ZCL_MESSAGE_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/security/zcl.ias_ace.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/security/zcl.ias_ace.h new file mode 100644 index 000000000..da3cc5a63 --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/security/zcl.ias_ace.h @@ -0,0 +1,414 @@ +/* Copyright [2009 - 2019] Exegin Technologies Limited. All rights reserved. */ + +/*-------------------------------------------------------------------------- + * DESCRIPTION + * The public header file for the Home Automation + * clusters of the ZCL. + *-------------------------------------------------------------------------- + */ +#ifndef ZCL_IAS_ACE_H +#define ZCL_IAS_ACE_H + +/* PICS.ZCL.IASACE + * + * IASACE.S | True + * IASACE.C | True + * + * IASACE.S.Afffd | True + * IASACE.S.Afffe | False + * IASACE.S.C00.Rsp | True + * IASACE.S.C01.Rsp | True + * IASACE.S.C02.Rsp | True + * IASACE.S.C03.Rsp | True + * IASACE.S.C04.Rsp | True + * IASACE.S.C05.Rsp | True + * IASACE.S.C06.Rsp | True + * IASACE.S.C07.Rsp | True + * IASACE.S.C08.Rsp | True + * IASACE.S.C09.Rsp | True + * IASACE.S.C00.Tx | True + * IASACE.S.C01.Tx | True + * IASACE.S.C02.Tx | True + * IASACE.S.C03.Tx | True + * IASACE.S.C04.Tx | True + * IASACE.S.C05.Tx | True + * IASACE.S.C06.Tx | True + * IASACE.S.C07.Tx | True + * IASACE.S.C08.Tx | True + * + * IASACE.C.Afffd | True + * IASACE.C.Afffe | False + * IASACE.C.C00.Tx | True + * IASACE.C.C01.Tx | True + * IASACE.C.C02.Tx | True + * IASACE.C.C03.Tx | True + * IASACE.C.C04.Tx | True + * IASACE.C.C05.Tx | True + * IASACE.C.C06.Tx | True + * IASACE.C.C07.Tx | True + * IASACE.C.C08.Tx | True + * IASACE.C.C09.Tx | True + * IASACE.C.C00.Rsp | True + * IASACE.C.C01.Rsp | True + * IASACE.C.C02.Rsp | True + * IASACE.C.C03.Rsp | True + * IASACE.C.C04.Rsp | True + * IASACE.C.C05.Rsp | True + * IASACE.C.C06.Rsp | True + * IASACE.C.C07.Rsp | True + * IASACE.C.C08.Rsp | True + */ + +#include "zcl/zcl.h" +#include "zcl/security/zcl.ias_zone.h" + +#define ZCL_IAS_ACE_SVR_MAX_ZONES 256 + +/* IAS ACE has no server or client attributes */ + +/* Server Generated Commands */ +enum ZbZclIasAceServerCommandsT { + ZCL_IAS_ACE_SVR_CMD_ARM_RSP = 0x00, + ZCL_IAS_ACE_SVR_CMD_GET_ZONE_ID_MAP_RSP = 0x01, + ZCL_IAS_ACE_SVR_CMD_GET_ZONE_INFO_RSP = 0x02, + ZCL_IAS_ACE_SVR_CMD_ZONE_STATUS_CHANGED = 0x03, + ZCL_IAS_ACE_SVR_CMD_PANEL_STATUS_CHANGED = 0x04, + ZCL_IAS_ACE_SVR_CMD_GET_PANEL_STATUS_RSP = 0x05, + ZCL_IAS_ACE_SVR_CMD_SET_BYPASSED_ZONE_LIST = 0x06, + ZCL_IAS_ACE_SVR_CMD_BYPASS_RSP = 0x07, + ZCL_IAS_ACE_SVR_CMD_GET_ZONE_STATUS_RSP = 0x08, +}; + +/* Client Generated Commands */ +enum ZbZclIasAceClientCommandsT { + ZCL_IAS_ACE_CLI_CMD_ARM = 0x00, + ZCL_IAS_ACE_CLI_CMD_BYPASS = 0x01, + ZCL_IAS_ACE_CLI_CMD_EMERGENCY = 0x02, + ZCL_IAS_ACE_CLI_CMD_FIRE = 0x03, + ZCL_IAS_ACE_CLI_CMD_PANIC = 0x04, + ZCL_IAS_ACE_CLI_CMD_GET_ZONE_ID_MAP = 0x05, + ZCL_IAS_ACE_CLI_CMD_GET_ZONE_INFO = 0x06, + ZCL_IAS_ACE_CLI_CMD_GET_PANEL_STATUS = 0x07, + ZCL_IAS_ACE_CLI_CMD_GET_BYPASSED_ZONE_LIST = 0x08, + ZCL_IAS_ACE_CLI_CMD_GET_ZONE_STATUS = 0x09, +}; + +enum ZbZclIasAceArmModeT { + ZCL_IAS_ACE_ARM_MODE_DISARM = 0x00, + ZCL_IAS_ACE_ARM_MODE_ARM_DAY_ZONES = 0x01, + ZCL_IAS_ACE_ARM_MODE_ARM_NIGHT_ZONES = 0x02, + ZCL_IAS_ACE_ARM_MODE_ARM_ALL_ZONES = 0x03, +}; + +enum ZbZclIasAceArmNotifyT { + ZCL_IAS_ACE_ARM_NOTIFY_ALL_ZONES_DISARMED = 0x00, + ZCL_IAS_ACE_ARM_NOTIFY_ONLY_DAY_ZONES_ARMED = 0x01, + ZCL_IAS_ACE_ARM_NOTIFY_ONLY_NIGHT_ZONES_ARMED = 0x02, + ZCL_IAS_ACE_ARM_NOTIFY_ALL_ZONES_ARMED = 0x03, + ZCL_IAS_ACE_ARM_NOTIFY_INVALID_ARM_CODE = 0x04, + ZCL_IAS_ACE_ARM_NOTIFY_NOT_READY_TO_ARM = 0x05, + ZCL_IAS_ACE_ARM_NOTIFY_ALREADY_DISARMED = 0x06, +}; + +enum ZbZclIasAcePanelStatusT { + ZCL_IAS_ACE_PANEL_STATUS_PANEL_DISARMED = 0x00, + ZCL_IAS_ACE_PANEL_STATUS_ARMED_STAY = 0x01, + ZCL_IAS_ACE_PANEL_STATUS_ARMED_NIGHT = 0x02, + ZCL_IAS_ACE_PANEL_STATUS_ARMED_AWAY = 0x03, + ZCL_IAS_ACE_PANEL_STATUS_EXIT_DELAY = 0x04, + ZCL_IAS_ACE_PANEL_STATUS_ENTRY_DELAY = 0x05, + ZCL_IAS_ACE_PANEL_STATUS_NOT_READY_TO_ARM = 0x06, + ZCL_IAS_ACE_PANEL_STATUS_IN_ALARM = 0x07, + ZCL_IAS_ACE_PANEL_STATUS_ARMING_STAY = 0x08, + ZCL_IAS_ACE_PANEL_STATUS_ARMING_NIGHT = 0x09, + ZCL_IAS_ACE_PANEL_STATUS_ARMING_AWAY = 0x0a, +}; + +enum ZbZclIasAceAudibleNotifyT { + ZCL_IAS_ACE_AUDIBLE_NOTIFY_MUTE = 0x00, + ZCL_IAS_ACE_AUDIBLE_NOTIFY_DEFAULT_SOUND = 0x01, +}; + +enum ZbZclIasAceAlarmStatusT { + ZCL_IAS_ACE_ALARM_STATUS_NO_ALARM = 0x00, + ZCL_IAS_ACE_ALARM_STATUS_BURGLAR = 0x01, + ZCL_IAS_ACE_ALARM_STATUS_FIRE = 0x02, + ZCL_IAS_ACE_ALARM_STATUS_EMERGENCY = 0x03, + ZCL_IAS_ACE_ALARM_STATUS_POLICE_PANIC = 0x04, + ZCL_IAS_ACE_ALARM_STATUS_FIRE_PANIC = 0x05, + ZCL_IAS_ACE_ALARM_STATUS_EMERGENCY_PANIC = 0x06, +}; + +enum ZbZclIasAceBypassResultT { + ZCL_IAS_ACE_BYPASS_RESULT_ZONE_BYPASSED = 0x00, + ZCL_IAS_ACE_BYPASS_RESULT_ZONE_NOT_BYPASSED = 0x01, + ZCL_IAS_ACE_BYPASS_RESULT_NOT_ALLOWED = 0x02, + ZCL_IAS_ACE_BYPASS_RESULT_INVALID_ZONE_ID = 0x03, + ZCL_IAS_ACE_BYPASS_RESULT_UNKNOWN_ZONE_ID = 0x04, + ZCL_IAS_ACE_BYPASS_RESULT_INVALID_ARM_CODE = 0x05, +}; + +enum ZbZclIasAceBypassPermsT { + ZCL_IAS_ACE_BYPASS_PERMS_ALLOWED = 0x00, + ZCL_IAS_ACE_BYPASS_PERMS_NOT_ALLOWED = 0x01, +}; + +/*--------------------------------------------------------------- + * Client Command Structures + *--------------------------------------------------------------- + */ +/* Arbitrary max. "There is no minimum or maximum length to the + * Arm/Disarm Code; however, the Arm/Disarm Code SHOULD be between + * four and eight alphanumeric characters in length." */ +#define ZCL_IAS_ACE_ARM_CODE_STRING_MAX_LEN 32 + +struct ZbZclIasAceClientCommandArmT { + enum ZbZclIasAceArmModeT arm_mode; + char arm_code[ZCL_IAS_ACE_ARM_CODE_STRING_MAX_LEN + 1U]; + /* EXEGIN - what is the Zone ID used for here? + * We're arming/disarming the entire system or set of zones. + * There's nothing to indicate an individual zone + * is useful here. */ + uint8_t zone_id; +}; + +/* Arbitrary max. May want to convert to a list with a max of 255. */ +#define ZCL_IAS_ACE_BYPASS_MAX_ZONES 32 + +struct ZbZclIasAceClientCommandBypassT { + uint8_t num_zones; + uint8_t zone_id_list[ZCL_IAS_ACE_BYPASS_MAX_ZONES]; + char arm_code[ZCL_IAS_ACE_ARM_CODE_STRING_MAX_LEN + 1U]; +}; + +struct ZbZclIasAceClientCommandGetZoneInfoT { + uint8_t zone_id; +}; + +struct ZbZclIasAceClientCommandGetZoneStatusT { + uint8_t starting_zone_id; + uint8_t max_zone_ids; + uint8_t zone_status_mask_flag; + uint16_t zone_status_mask; +}; + +/*--------------------------------------------------------------- + * Server Command Structures + *--------------------------------------------------------------- + */ + +struct ZbZclIasAceServerCommandArmRspT { + enum ZbZclIasAceArmNotifyT arm_notify; +}; + +#define ZCL_IAS_ACE_ZONE_ID_MAP_NUM_SECTIONS 16 + +struct ZbZclIasAceServerCommandGetZoneIdMapRspT { + uint16_t zond_id_map_list[ZCL_IAS_ACE_ZONE_ID_MAP_NUM_SECTIONS]; +}; + +/* Arbitrary max. "There is no minimum or maximum length to the Zone Label + * field; however, the Zone Label SHOULD be between 16 to 24 alphanumeric + * characters in length." */ +#define ZCL_IAS_ACE_ZONE_LABEL_STRING_MAX_LEN 32 + +struct ZbZclIasAceServerCommandGetZoneInfoRspT { + uint8_t zone_id; + enum ZbZclIasZoneServerZoneTypeT zone_type; + uint64_t zone_addr; + char zone_label[ZCL_IAS_ACE_ZONE_LABEL_STRING_MAX_LEN + 1U]; +}; + +struct ZbZclIasAceServerCommandZoneStatusChangedT { + uint8_t zone_id; + enum ZbZclIasZoneServerZoneStatusT zone_status; + enum ZbZclIasAceAudibleNotifyT audible_notify; + char zone_label[ZCL_IAS_ACE_ZONE_LABEL_STRING_MAX_LEN + 1U]; +}; + +struct ZbZclIasAceServerCommandGetPanelStatusRspT { + enum ZbZclIasAcePanelStatusT panel_status; + uint8_t seconds_remain; + enum ZbZclIasAceAudibleNotifyT audible_notify; + enum ZbZclIasAceAlarmStatusT alarm_status; +}; + +struct ZbZclIasAceServerCommandSetBypassedZoneListT { + uint8_t num_zones; + uint8_t zone_id_list[ZCL_IAS_ACE_BYPASS_MAX_ZONES]; +}; + +struct ZbZclIasAceServerCommandBypassRspT { + uint8_t num_zones; + enum ZbZclIasAceBypassResultT bypass_result_list[ZCL_IAS_ACE_BYPASS_MAX_ZONES]; +}; + +#define ZCL_IAS_ACE_ZONE_STATUS_MAX_ZONES 10 + +struct ZbZclIasAceServerCommandGetZoneStatusRspT { + uint8_t zone_status_complete; + uint8_t num_zones; + struct { + uint8_t zone_id; + enum ZbZclIasZoneServerZoneStatusT zone_status; + } zone_list[ZCL_IAS_ACE_ZONE_STATUS_MAX_ZONES]; +}; + +/*--------------------------------------------------------------- + * Server API + *--------------------------------------------------------------- + */ + +struct ZbZclIasAceServerCallbacksT { + /* The callback for Arming should handle arming the system and + * calling ZbZclIasAceServerPanelStatusConfig when the panel status changes. */ + bool (*arm_req)(struct ZbZclClusterT *clusterPtr, void *arg, + struct ZbZclIasAceClientCommandArmT *arm_req, + struct ZbZclIasAceServerCommandArmRspT *arm_rsp); + + void (*bypass_req)(struct ZbZclClusterT *clusterPtr, void *arg, + struct ZbZclIasAceClientCommandBypassT *bypass_req, + struct ZbZclIasAceServerCommandBypassRspT *bypass_rsp); + + /* Emergency, Fire and Panic callbacks return a ZCL status to + * return in the Default Response (e.g. ZCL_STATUS_SUCCESS). */ + uint8_t (*emerg_req)(struct ZbZclClusterT *clusterPtr, void *arg, struct ZbZclAddrInfoT *srcInfo); + uint8_t (*fire_req)(struct ZbZclClusterT *clusterPtr, void *arg, struct ZbZclAddrInfoT *srcInfo); + uint8_t (*panic_req)(struct ZbZclClusterT *clusterPtr, void *arg, struct ZbZclAddrInfoT *srcInfo); +}; + +/* Allocate the IAS ACE Server cluster. + * + * If 'use_trip_pair' is true, application must call ZbZclIasAceServerEnrollRequest + * to perform the 'trip-to-pair' process, unless the IAS CIE has sent us an + * unsolicited Auto-Enroll-Response. */ +struct ZbZclClusterT * ZbZclIasAceServerAlloc(struct ZigBeeT *zb, uint8_t endpoint, + struct ZbZclIasAceServerCallbacksT *callbacks, void *arg); + +void ZbZclIasAceServerConfigCallbacks(struct ZbZclClusterT *clusterPtr, + struct ZbZclIasAceServerCallbacksT *callbacks); + +/* Change the Panel Arm/Disarm Code */ +bool ZbZclIasAceServerPanelCodeConfig(struct ZbZclClusterT *clusterPtr, + const char *arm_code); + +/* Update the Panel Status */ +bool ZbZclIasAceServerPanelStatusConfig(struct ZbZclClusterT *clusterPtr, + enum ZbZclIasAcePanelStatusT panel_status, uint8_t seconds_remain, + enum ZbZclIasAceAudibleNotifyT audible_notify); + +/* Returns the first free Zone ID not already in the Zone Table. */ +bool ZbZclIasAceServerGetFreeZoneId(struct ZbZclClusterT *clusterPtr, uint8_t *zone_id_ptr); + +/* Adds a new zone. Returns true if successful, and the assigned Zone ID + * is returned via zone_id. */ +struct ZbZclIasAceServerZoneTableAddT { + enum ZbZclIasZoneServerZoneTypeT zone_type; + uint64_t zone_addr; + /* zone_label - optional, may be NULL. + * Max length = ZCL_IAS_ACE_ZONE_LABEL_STRING_MAX_LEN. */ + const char *zone_label; + /* zone_id - can use ZbZclIasAceServerGetFreeZoneId */ + uint8_t zone_id; +}; + +bool ZbZclIasAceServerZoneTableAdd(struct ZbZclClusterT *clusterPtr, + struct ZbZclIasAceServerZoneTableAddT *req); + +/* Delete a zone */ +bool ZbZclIasAceServerZoneTableDeleteById(struct ZbZclClusterT *clusterPtr, uint8_t zone_id); +bool ZbZclIasAceServerZoneTableDeleteByAddr(struct ZbZclClusterT *clusterPtr, uint64_t addr); + +/* Returns address of paired zone, or 0 if not found. */ +uint64_t ZbZclIasAceServerZoneTableAddrLookup(struct ZbZclClusterT *clusterPtr, uint8_t zone_id); + +bool ZbZclIasAceServerZoneTableIdLookup(struct ZbZclClusterT *clusterPtr, + uint64_t zone_addr, uint8_t *zone_id_ptr); + +bool ZbZclIasAceServerZoneStatusConfig(struct ZbZclClusterT *clusterPtr, + uint8_t zone_id, enum ZbZclIasZoneServerZoneStatusT zone_status, + enum ZbZclIasAceAudibleNotifyT audible_notify); + +bool ZbZclIasAceServerZoneBypassPerms(struct ZbZclClusterT *clusterPtr, + uint8_t zone_id, enum ZbZclIasAceBypassPermsT bypass_perms); + +enum ZbZclIasAceBypassResultT ZbZclIasAceServerZoneBypassConfig(struct ZbZclClusterT *clusterPtr, + uint8_t zone_id, bool bypass); + +/*--------------------------------------------------------------- + * Client API + *--------------------------------------------------------------- + */ +struct ZbZclClusterT * ZbZclIasAceClientAlloc(struct ZigBeeT *zb, uint8_t endpoint, void *arg); + +/* ARM */ +uint8_t ZbZclIasAceClientCommandArmReq(struct ZbZclClusterT *clusterPtr, + const struct ZbApsAddrT *dst, struct ZbZclIasAceClientCommandArmT *cmd_req, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +bool ZbZclIasAceClientParseArmRsp(const uint8_t *buf, unsigned int len, + struct ZbZclIasAceServerCommandArmRspT *rsp); + +/* BYPASS */ +uint8_t ZbZclIasAceClientCommandBypassReq(struct ZbZclClusterT *clusterPtr, + const struct ZbApsAddrT *dst, struct ZbZclIasAceClientCommandBypassT *cmd_req, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +bool ZbZclIasAceClientParseBypassRsp(const uint8_t *buf, unsigned int len, + struct ZbZclIasAceServerCommandBypassRspT *rsp); + +/* Emergency / Fire / Panic */ +uint8_t ZbZclIasAceClientCommandEmergencyReq(struct ZbZclClusterT *clusterPtr, + const struct ZbApsAddrT *dst, void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +uint8_t ZbZclIasAceClientCommandFireReq(struct ZbZclClusterT *clusterPtr, + const struct ZbApsAddrT *dst, void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +uint8_t ZbZclIasAceClientCommandPanicReq(struct ZbZclClusterT *clusterPtr, + const struct ZbApsAddrT *dst, void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +/* Get Zone Id Map */ +uint8_t ZbZclIasAceClientCommandGetZoneIdMapReq(struct ZbZclClusterT *clusterPtr, + const struct ZbApsAddrT *dst, void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +bool ZbZclIasAceClientParseGetZoneIdMapRsp(const uint8_t *buf, unsigned int len, + struct ZbZclIasAceServerCommandGetZoneIdMapRspT *rsp); + +/* Get Zone Info */ +uint8_t ZbZclIasAceClientCommandGetZoneInfoReq(struct ZbZclClusterT *clusterPtr, + const struct ZbApsAddrT *dst, struct ZbZclIasAceClientCommandGetZoneInfoT *cmd_req, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +bool ZbZclIasAceClientParseGetZoneInfoRsp(const uint8_t *buf, unsigned int len, + struct ZbZclIasAceServerCommandGetZoneInfoRspT *rsp); + +/* Zone / Panel Status Changed */ +bool ZbZclIasAceClientParseZoneStatusChanged(const uint8_t *buf, unsigned int len, + struct ZbZclIasAceServerCommandZoneStatusChangedT *rsp); + +/* Panel Status Changed command has same payload as Get Panel Status Response. + * Use ZbZclIasAceClientParseGetPanelStatusRsp. */ + +/* Get Panel Status */ +uint8_t ZbZclIasAceClientCommandGetPanelStatusReq(struct ZbZclClusterT *clusterPtr, + const struct ZbApsAddrT *dst, void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +bool ZbZclIasAceClientParseGetPanelStatusRsp(const uint8_t *buf, unsigned int len, + struct ZbZclIasAceServerCommandGetPanelStatusRspT *rsp); + +/* Get Bypassed Zone List */ +uint8_t ZbZclIasAceClientCommandGetBypassedZoneListReq(struct ZbZclClusterT *clusterPtr, + const struct ZbApsAddrT *dst, void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +bool ZbZclIasAceClientParseSetBypassedZoneList(const uint8_t *buf, unsigned int len, + struct ZbZclIasAceServerCommandSetBypassedZoneListT *rsp); + +/* Get Zone Status */ +uint8_t ZbZclIasAceClientCommandGetZoneStatusReq(struct ZbZclClusterT *clusterPtr, + const struct ZbApsAddrT *dst, struct ZbZclIasAceClientCommandGetZoneStatusT *cmd_req, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +bool ZbZclIasAceClientParseGetZoneStatusRsp(const uint8_t *buf, unsigned int len, + struct ZbZclIasAceServerCommandGetZoneStatusRspT *rsp); + +#endif /* __ZCL_IAS_ACE_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/security/zcl.ias_wd.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/security/zcl.ias_wd.h new file mode 100644 index 000000000..9fa5ebc6c --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/security/zcl.ias_wd.h @@ -0,0 +1,124 @@ +/* Copyright [2009 - 2019] Exegin Technologies Limited. All rights reserved. */ + +/*-------------------------------------------------------------------------- + * DESCRIPTION + * The public header file for the Home Automation + * clusters of the ZCL. + *-------------------------------------------------------------------------- + */ +#ifndef ZCL_IAS_WD_H +#define ZCL_IAS_WD_H + +/* PICS.ZCL.IASWD + * + * IASWD.S | True + * IASWD.C | True + * + * IASWD.S.A0000 | True + * IASWD.S.Afffd | True + * IASWD.S.Afffe | False + * IASWD.S.C00.Rsp | True + * IASWD.S.C01.Rsp | True + * + * IASWD.C.Afffd | True + * IASWD.C.Afffe | False + * IASWD.C.C00.Tx | True + * IASWD.C.C01.Tx | True + */ + +#include "zcl/zcl.h" + +enum ZbZclIasWdServerAttrT { + ZCL_IAS_WD_SVR_ATTR_MAX_DURATION = 0x0000, +}; + +/* Client Generated Commands */ +enum ZbZclIasWdClientCommandsT { + ZCL_IAS_WD_CLI_CMD_START_WARNING = 0x00, + ZCL_IAS_WD_CLI_CMD_SQUAWK = 0x01, +}; + +enum ZbZclIasWdWarningModeT { + ZCL_IAS_WD_WARNING_MODE_STOP = 0, + ZCL_IAS_WD_WARNING_MODE_BURGLAR = 1, + ZCL_IAS_WD_WARNING_MODE_FIRE = 2, + ZCL_IAS_WD_WARNING_MODE_EMERGENCY = 3, + ZCL_IAS_WD_WARNING_MODE_POLICE_PANIC = 4, + ZCL_IAS_WD_WARNING_MODE_FIRE_PANIC = 5, + ZCL_IAS_WD_WARNING_MODE_EMERGENCY_PANIC = 6, +}; + +enum ZbZclIasWdStrobeT { + ZCL_IAS_WD_STROBE_OFF = 0, + ZCL_IAS_WD_STROBE_ON = 1, +}; + +enum ZbZclIasWdLevelT { + ZCL_IAS_WD_LEVEL_LOW = 0, + ZCL_IAS_WD_LEVEL_MEDIUM = 1, + ZCL_IAS_WD_LEVEL_HIGH = 2, + ZCL_IAS_WD_LEVEL_VERY_HIGH = 3, +}; + +enum ZbZclIasWdSquawkModeT { + ZCL_IAS_WD_SQUAWK_MODE_ARMED = 0, + ZCL_IAS_WD_SQUAWK_MODE_DISARMED = 1, +}; + +/*--------------------------------------------------------------- + * API Structures + *--------------------------------------------------------------- + */ +struct ZbZclIasWdClientStartWarningReqT { + enum ZbZclIasWdWarningModeT warning_mode; + enum ZbZclIasWdStrobeT strobe; + enum ZbZclIasWdLevelT siren_level; + uint16_t warning_duration; + uint8_t strobe_dutycycle; + enum ZbZclIasWdLevelT strobe_level; +}; + +struct ZbZclIasWdClientSquawkReqT { + enum ZbZclIasWdSquawkModeT squawk_mode; + enum ZbZclIasWdStrobeT strobe; + enum ZbZclIasWdLevelT squawk_level; +}; + +/*--------------------------------------------------------------- + * Server API + *--------------------------------------------------------------- + */ +struct ZbZclIasWdServerCallbacksT { + /* Returns a ZCL Status code to send in the Default Response, or + * ZCL_STATUS_SUCCESS_NO_DEFAULT_RESPONSE if no Default Response + * to be generated. */ + uint8_t (*start_warning)(struct ZbZclClusterT *clusterPtr, void *arg, + struct ZbZclIasWdClientStartWarningReqT *warn_req); + + uint8_t (*squawk)(struct ZbZclClusterT *clusterPtr, void *arg, + struct ZbZclIasWdClientSquawkReqT *squawk_req); +}; + +struct ZbZclClusterT * ZbZclIasWdServerAlloc(struct ZigBeeT *zb, uint8_t endpoint, + struct ZbZclIasWdServerCallbacksT *callbacks, void *arg); + +void ZbZclIasWdServerConfigCallbacks(struct ZbZclClusterT *clusterPtr, + struct ZbZclIasWdServerCallbacksT *callbacks); + +/*--------------------------------------------------------------- + * Client API + *--------------------------------------------------------------- + */ +struct ZbZclClusterT * ZbZclIasWdClientAlloc(struct ZigBeeT *zb, uint8_t endpoint, void *arg); + +uint8_t ZbZclIasWdClientStartWarningReq(struct ZbZclClusterT *clusterPtr, + const struct ZbApsAddrT *dst, + struct ZbZclIasWdClientStartWarningReqT *warning_req, + void (*callback)(struct ZbZclCommandRspT *zcl_rsp, void *arg), void *arg); + +uint8_t ZbZclIasWdClientSquawkReq(struct ZbZclClusterT *clusterPtr, + const struct ZbApsAddrT *dst, + struct ZbZclIasWdClientSquawkReqT *squawk_req, + void (*callback)(struct ZbZclCommandRspT *zcl_rsp, void *arg), void *arg); + +#endif /* __ZCL_IAS_WD_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/security/zcl.ias_zone.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/security/zcl.ias_zone.h new file mode 100644 index 000000000..f97cbbbca --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/security/zcl.ias_zone.h @@ -0,0 +1,241 @@ +/* Copyright [2009 - 2019] Exegin Technologies Limited. All rights reserved. */ + +/*-------------------------------------------------------------------------- + * DESCRIPTION + * The public header file for the Home Automation + * clusters of the ZCL. + *-------------------------------------------------------------------------- + */ +#ifndef ZCL_IAS_ZONE_H +#define ZCL_IAS_ZONE_H + +/* PICS.ZCL.IASZ + * + * IASZ.S | True + * IASZ.C | True + * IASZ.TTP | True + * IASZ.ARSP | True + * IASZ.AREQ | True + * IASZ.PIXIT01 | False (seems like it would require a more complete sensor application) + * IASZ.PIXIT02 | False (seems like it would require a more complete sensor application) + * + * IASZ.S.A0000 | True + * IASZ.S.A0001 | True + * IASZ.S.A0002 | True + * IASZ.S.A0010 | True + * IASZ.S.A0011 | True + * IASZ.S.A0012 | False + * IASZ.S.A0013 | False + * IASZ.S.Afffd | True + * IASZ.S.Afffe | False + * IASZ.S.C00.Rsp | True + * IASZ.S.C01.Rsp | True + * IASZ.S.C02.Rsp | True + * IASZ.S.C00.Tx | True + * IASZ.S.C01.Tx | True + * + * IASZ.C.Afffd | True + * IASZ.C.Afffe | False + * IASZ.C.C00.Rsp | True + * IASZ.C.C01.Rsp | True + * IASZ.C.C00.Tx | True + * IASZ.C.C01.Tx | True + * IASZ.C.C02.Tx | True + */ + +#include "zcl/zcl.h" + +/* Zone Attributes */ +enum ZbZclIasZoneServerAttrT { + /* Zone Information Set */ + ZCL_IAS_ZONE_SVR_ATTR_ZONE_STATE = 0x0000, + ZCL_IAS_ZONE_SVR_ATTR_ZONE_TYPE = 0x0001, + ZCL_IAS_ZONE_SVR_ATTR_ZONE_STATUS = 0x0002, + /* Zone Settings Set */ + ZCL_IAS_ZONE_SVR_ATTR_CIE_ADDR = 0x0010, /* IAS_CIE_ADDR */ + ZCL_IAS_ZONE_SVR_ATTR_ZONE_ID = 0x0011, + ZCL_IAS_ZONE_SVR_ATTR_NUM_ZONE_SENSITIVITY_SUPPORTED = 0x0012, + ZCL_IAS_ZONE_SVR_ATTR_CURRENT_ZONE_SENSITIVITY_LEVEL = 0x0013, + + /* Exegin add-on (internal) to preserve endpoint of CIE */ + ZCL_IAS_ZONE_SVR_ATTR_CIE_ENDPOINT = 0x7fff, +}; + +/* Server Generated Commands */ +enum ZbZclIasZoneServerCommandsT { + ZCL_IAS_ZONE_SVR_CMD_ZONE_STATUS_CHANGE_NOTIFY = 0x00, + ZCL_IAS_ZONE_SVR_CMD_ZONE_ENROLL_REQUEST = 0x01, +}; + +/* Client Generated Commands */ +enum ZbZclIasZoneClientCommandsT { + ZCL_IAS_ZONE_CLI_CMD_ZONE_ENROLL_RESPONSE = 0x00, + ZCL_IAS_ZONE_CLI_CMD_INITIATE_NORMAL_MODE = 0x01, + ZCL_IAS_ZONE_CLI_CMD_INITIATE_TEST_MODE = 0x02, +}; + +/* ZCL_IAS_ZONE_SVR_ATTR_ZONE_STATE */ +enum ZbZclIasZoneServerZoneStateT { + ZCL_IAS_ZONE_SVR_STATE_NOT_ENROLLED = 0x00, + ZCL_IAS_ZONE_SVR_STATE_ENROLLED = 0x01, +}; + +/* ZCL_IAS_ZONE_SVR_ATTR_ZONE_TYPE */ +enum ZbZclIasZoneServerZoneTypeT { + ZCL_IAS_ZONE_SVR_ZONE_TYPE_STANDARD_CIE = 0x0000, + ZCL_IAS_ZONE_SVR_ZONE_TYPE_MOTION_SENSOR = 0x000d, + ZCL_IAS_ZONE_SVR_ZONE_TYPE_CONTACT_SWITCH = 0x0015, + ZCL_IAS_ZONE_SVR_ZONE_TYPE_FIRE_SENSOR = 0x0028, + ZCL_IAS_ZONE_SVR_ZONE_TYPE_WATER_SENSOR = 0x002a, + ZCL_IAS_ZONE_SVR_ZONE_TYPE_CO_SENSOR = 0x002b, + ZCL_IAS_ZONE_SVR_ZONE_TYPE_PERSONAL_EMERG_DEVICE = 0x002c, + ZCL_IAS_ZONE_SVR_ZONE_TYPE_MOVEMENT_SENSOR = 0x002d, + ZCL_IAS_ZONE_SVR_ZONE_TYPE_REMOTE_CONTROL = 0x010f, + ZCL_IAS_ZONE_SVR_ZONE_TYPE_KEY_FOB = 0x0115, + ZCL_IAS_ZONE_SVR_ZONE_TYPE_KEYPAD = 0x021d, + ZCL_IAS_ZONE_SVR_ZONE_TYPE_STANDARD_WARNING_DEVICE = 0x0225, + ZCL_IAS_ZONE_SVR_ZONE_TYPE_GLASS_SENSOR = 0x0226, + ZCL_IAS_ZONE_SVR_ZONE_TYPE_SECURITY_REPEATER = 0x0229, + ZCL_IAS_ZONE_SVR_ZONE_TYPE_INVALID = 0xffff, +}; + +/* ZCL_IAS_ZONE_SVR_ATTR_ZONE_STATUS */ +enum ZbZclIasZoneServerZoneStatusT { + ZCL_IAS_ZONE_SVR_ZONE_STATUS_ALARM1 = 1 << 0, + ZCL_IAS_ZONE_SVR_ZONE_STATUS_ALARM2 = 1 << 1, + ZCL_IAS_ZONE_SVR_ZONE_STATUS_TAMPER = 1 << 2, + ZCL_IAS_ZONE_SVR_ZONE_STATUS_BATTERY = 1 << 3, + ZCL_IAS_ZONE_SVR_ZONE_STATUS_SUPERVISION_REPORTS = 1 << 4, + ZCL_IAS_ZONE_SVR_ZONE_STATUS_RESTORE_REPORTS = 1 << 5, + ZCL_IAS_ZONE_SVR_ZONE_STATUS_TROUBLE = 1 << 6, + ZCL_IAS_ZONE_SVR_ZONE_STATUS_AC_MAINS = 1 << 7, + ZCL_IAS_ZONE_SVR_ZONE_STATUS_TEST = 1 << 8, + ZCL_IAS_ZONE_SVR_ZONE_STATUS_BATTERY_DEFECT = 1 << 9, +}; + +/* Sensor mode: I.e. Zone Status "Test" bit cleared or set */ +enum ZbZclIasZoneServerModeT { + ZCL_IAS_ZONE_SVR_MODE_NORMAL = 0, + ZCL_IAS_ZONE_SVR_MODE_TEST, +}; + +/* ZCL_IAS_ZONE_CLI_CMD_ZONE_ENROLL_RESPONSE */ +enum ZbZclIasZoneClientResponseCodeT { + ZCL_IAS_ZONE_CLI_RESP_SUCCESS = 0x00, + ZCL_IAS_ZONE_CLI_RESP_NOT_SUPPORTED = 0x01, + ZCL_IAS_ZONE_CLI_RESP_NO_ENROLL_PERMIT = 0x02, + ZCL_IAS_ZONE_CLI_RESP_TOO_MANY_ZONES = 0x03, +}; + +/*--------------------------------------------------------------- + * API Structures + *--------------------------------------------------------------- + */ +struct ZbZclIasZoneServerStatusChangeNotifyT { + enum ZbZclIasZoneServerZoneStatusT zone_status; + uint8_t ext_status; /* reserved, set to 0x00 */ + uint8_t zone_id; + uint16_t delay; +}; + +struct ZbZclIasZoneServerEnrollRequestT { + uint16_t zone_type; + uint16_t manuf_code; +}; + +struct ZbZclIasZoneClientEnrollResponseT { + uint8_t zcl_status; + enum ZbZclIasZoneClientResponseCodeT enroll_status; + uint8_t zone_id; +}; + +struct ZbZclIasZoneClientTestModeReqT { + uint8_t test_duration; /* seconds */ + uint8_t current_zone_sensitivity; /* 0x00 means to use the device's default */ +}; + +/*--------------------------------------------------------------- + * Server API + *--------------------------------------------------------------- + */ +struct ZbZclIasZoneServerCallbacksT { + /* Callback so the application is made aware of mode change + * (i.e. Normal vs Test). + * 'req' is only valid if mode == ZCL_IAS_ZONE_SVR_MODE_TEST. + * Return value is a ZCL Status. If status indicates an error, + * it sent in a Default Response back to the originator. */ + uint8_t (*mode_change)(struct ZbZclClusterT *clusterPtr, + void *arg, /* ZbZclClusterSetCallbackArg */ + enum ZbZclIasZoneServerModeT mode, + struct ZbZclIasZoneClientTestModeReqT *req); +}; + +/* If 'use_trip_pair' is true, application must call ZbZclIasZoneServerEnrollRequest + * to perform the 'trip-to-pair' process, unless the IAS CIE has sent us an + * unsolicited Auto-Enroll-Response. */ +struct ZbZclClusterT * ZbZclIasZoneServerAlloc(struct ZigBeeT *zb, uint8_t endpoint, + uint16_t zone_type, uint16_t manuf_code, bool use_trip_pair, + struct ZbZclIasZoneServerCallbacksT *callbacks, void *arg); + +void ZbZclIasZoneServerConfigCallbacks(struct ZbZclClusterT *clusterPtr, + struct ZbZclIasZoneServerCallbacksT *callbacks); + +/* Used with 'trip-to-pair'. Before sending a Zone Enroll Request, the IAS CIE + * must write to the IAS_CIE_Address attribute with its IEEE address. */ +uint8_t ZbZclIasZoneServerEnrollRequest(struct ZbZclClusterT *clusterPtr, + void (*callback)(struct ZbZclIasZoneClientEnrollResponseT *enrl_rsp, void *arg), void *arg); + +/*--------------------------------------------------------------- + * Client API + *--------------------------------------------------------------- + */ +struct ZbZclIasZoneClientCallbacksT { + /* ZCL_IAS_ZONE_SVR_CMD_ZONE_STATUS_CHANGE_NOTIFY callback */ + void (*zone_status_change)( + struct ZbZclClusterT *clusterPtr, + void *arg, /* ZbZclClusterSetCallbackArg */ + struct ZbZclIasZoneServerStatusChangeNotifyT *notify, + struct ZbApsAddrT *src); + + /* ZCL_IAS_ZONE_SVR_CMD_ZONE_ENROLL_REQUEST callback. + * Returns a ZCL Status Code. If not SUCCESS, a Default Response is + * sent with the status code. If ZCL_STATUS_SUCCESS, the + * Zone Enroll Response command is sent.*/ + uint8_t (*zone_enroll_req)( + struct ZbZclClusterT *clusterPtr, + void *arg, /* ZbZclClusterSetCallbackArg */ + struct ZbZclIasZoneServerEnrollRequestT *req, + uint64_t ext_src_addr, + /* OUT: Enroll response code */ + enum ZbZclIasZoneClientResponseCodeT *rsp_code, + /* OUT: Zone ID */ + uint8_t *zone_id); +}; + +struct ZbZclClusterT * ZbZclIasZoneClientAlloc(struct ZigBeeT *zb, uint8_t endpoint, + struct ZbZclIasZoneClientCallbacksT *callbacks, void *arg); + +void ZbZclIasZoneClientConfigCallbacks(struct ZbZclClusterT *clusterPtr, + struct ZbZclIasZoneClientCallbacksT *callbacks); + +uint8_t ZbZclIasZoneClientInitiateAutoEnroll(struct ZbZclClusterT *clusterPtr, + const struct ZbApsAddrT *dst, + void (*callback)(const ZbZclWriteRspT *, void *), void *arg); + +uint8_t ZbZclIasZoneClientSendAutoEnrollResponse(struct ZbZclClusterT *clusterPtr, + const struct ZbApsAddrT *dst, uint8_t zone_id, + void (*callback)(struct ZbZclCommandRspT *zcl_rsp, void *arg), void *arg); + +/* Sends a ZCL_IAS_ZONE_CLI_CMD_INITIATE_NORMAL_MODE to destination */ +uint8_t ZbZclIasZoneClientInitiateNormalMode(struct ZbZclClusterT *clusterPtr, + const struct ZbApsAddrT *dst, + void (*callback)(struct ZbZclCommandRspT *zcl_rsp, void *arg), void *arg); + +/* Sends a ZCL_IAS_ZONE_CLI_CMD_INITIATE_TEST_MODE to destination. + * test_duration is in seconds. + * current_zone_sensitivity of 0x00 means use device's default. */ +uint8_t ZbZclIasZoneClientInitiateTestMode(struct ZbZclClusterT *clusterPtr, + const struct ZbApsAddrT *dst, struct ZbZclIasZoneClientTestModeReqT *req, + void (*callback)(struct ZbZclCommandRspT *zcl_rsp, void *arg), void *arg); + +#endif /* __ZCL_IAS_ZONE_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.alarm.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.alarm.h new file mode 100644 index 000000000..fe4f18c15 --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.alarm.h @@ -0,0 +1,118 @@ +/* Copyright [2009 - 2019] Exegin Technologies Limited. All rights reserved. */ + +#ifndef ZCL_ALARM_H +# define ZCL_ALARM_H + +/*-------------------------------------------------------------------------- + * DESCRIPTION + * Interface definition for the ZCL Alarms cluster. + *-------------------------------------------------------------------------- + */ + +/* PICS.ZCL.Alarm + * ALM.S | True + * ALM.C | True + * + * Server Attributes + * ALM.S.A0000 | True + * + * Commands Received + * ALM.S.C00.Rsp | True + * ALM.S.C01.Rsp | True + * ALM.S.C02.Rsp | True + * ALM.S.C03.Rsp | True + * + * Commands Generated + * ALM.S.C00.Tx | True + * ALM.S.C01.Tx | True + * + * + * Client Side + * + * Commands Received + * ALM.C.C00.Rsp | True + * ALM.C.C01.Rsp | True + * + * Commands Generated + * ALM.C.C00.Tx | True + * ALM.C.C01.Tx | True + * ALM.C.C02.Tx | True + * ALM.C.C03.Tx | True + */ + +#include "zcl/zcl.h" + +/*--------------------------------------------------------------- + * Definitions + *--------------------------------------------------------------- + */ +/* Alarms cluster attribute identifiers. */ +enum { + ZCL_ALARM_ATTR_COUNT = 0x0000 +}; + +/* Alarms cluster client commands. */ +enum { + ZCL_ALARM_COMMAND_RESET = 0x00, + ZCL_ALARM_COMMAND_RESET_ALL, + ZCL_ALARM_COMMAND_GET, + ZCL_ALARM_COMMAND_RESET_LOG +}; + +/* Alarms cluster server commands. */ +enum { + ZCL_ALARM_COMMAND_ALARM = 0x00, + ZCL_ALARM_COMMAND_GET_RESPONSE +}; + +/*--------------------------------------------------------------- + * Structures + *--------------------------------------------------------------- + */ + +/* + * Callback on Alarm Client Cluster when an alarm is received + */ +typedef void (*ZbZclAlarmClientCallbackT) + (void *arg, /* supplied argument */ + uint16_t nwk_addr, /* address where the alarm originates */ + uint8_t endpoint, /* endpoint from which it originates */ + uint8_t alarm_code, /* code of detected alarm condition */ + uint16_t cluster_id); /* cluster where alarm condition occurred */ + +/*--------------------------------------------------------------- + * Function Declarations + *--------------------------------------------------------------- + */ + +/* + * Server Commands + */ +struct ZbZclClusterT * ZbZclAlarmServerAlloc(struct ZigBeeT *zb, uint8_t endpoint, + uint16_t logSize, struct ZbZclClusterT *time_server); + +/* + * Client Commands + */ +struct ZbZclClusterT * ZbZclAlarmClientAlloc(struct ZigBeeT *zb, uint8_t endpoint, ZbZclAlarmClientCallbackT callback, void *arg); +/*uint8_t ZbZclAlarmClientBind(struct ZbZclClusterT *clusterPtr, uint16_t nwkAddr, uint8_t endpoint); +uint8_t ZbZclAlarmClientBindDiscover(struct ZbZclClusterT *clusterPtr); +*/ +enum ZclStatusCodeT ZbZclAlarmClientResetAlarmReq(struct ZbZclClusterT *cluster, const struct ZbApsAddrT *dst, + uint8_t alarm_code, uint16_t cluster_id, void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); +enum ZclStatusCodeT ZbZclAlarmClientResetAlarmWait(struct ZbZclClusterT *cluster, const struct ZbApsAddrT *dst, + uint8_t alarm_code, uint16_t cluster_id); + +enum ZclStatusCodeT ZbZclAlarmClientResetAllAlarmsReq(struct ZbZclClusterT *cluster, const struct ZbApsAddrT *dst, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); +enum ZclStatusCodeT ZbZclAlarmClientResetAllAlarmsWait(struct ZbZclClusterT *cluster, const struct ZbApsAddrT *dst); + +enum ZclStatusCodeT ZbZclAlarmClientGetAlarmReq(struct ZbZclClusterT *cluster, const struct ZbApsAddrT *dst, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); +enum ZclStatusCodeT ZbZclAlarmClientGetAlarmWait(struct ZbZclClusterT *cluster, const struct ZbApsAddrT *dst, struct ZbZclCommandRspT *rsp); + +enum ZclStatusCodeT ZbZclAlarmClientResetAlarmLogReq(struct ZbZclClusterT *cluster, const struct ZbApsAddrT *dst, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); +enum ZclStatusCodeT ZbZclAlarmClientResetAlarmLogWait(struct ZbZclClusterT *cluster, const struct ZbApsAddrT *dst); + +#endif /* __ZCL_ALARM_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.ballast.config.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.ballast.config.h new file mode 100644 index 000000000..3e438f467 --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.ballast.config.h @@ -0,0 +1,156 @@ +/* Copyright [2009 - 2019] Exegin Technologies Limited. All rights reserved. */ + +#ifndef ZCL_BALLAST_CONFIG_H +# define ZCL_BALLAST_CONFIG_H + +/*-------------------------------------------------------------------------- + * DESCRIPTION + * Interface definition for the ZCL Ballast Configuration cluster. + *-------------------------------------------------------------------------- + */ +/* PICS.ZCL.Ballast_Config + * BC.S | True + * BC.C | True + * + * Server Attributes + * BC.S.A0000 | True + * BC.S.A0001 | True + * BC.S.A0002 | False + * BC.S.A0010 | True + * BC.S.A0011 | True + * BC.S.A0014 | False + * BC.S.A0015 | False + * BC.S.A0020 | False + * BC.S.A0030 | False + * BC.S.A0031 | False + * BC.S.A0032 | False + * BC.S.A0033 | False + * BC.S.A0034 | False + * BC.S.A0035 | False + * BC.S.Afffd | True + * BC.S.Afffe | False + * + * + * Client Attributes + * BC.C.Afffd | True + * BC.C.Afffe | False + */ + +#include "zcl/zcl.h" + +/*--------------------------------------------------------------- + * Ballast Configuration Cluster Definitions + *--------------------------------------------------------------- + */ +/* Ballast Configuration Attribute Sets */ +enum { + /* Ballast Information Attribute Set */ + ZCL_BALLAST_CONFIG_ATTR_PHY_MIN_LEVEL = 0x0000, + ZCL_BALLAST_CONFIG_ATTR_PHY_MAX_LEVEL = 0x0001, + ZCL_BALLAST_CONFIG_ATTR_BALLAST_STATUS = 0x0002, + + /* Ballast Settings Attribute Set */ + ZCL_BALLAST_CONFIG_ATTR_MIN_LEVEL = 0x0010, + ZCL_BALLAST_CONFIG_ATTR_MAX_LEVEL = 0x0011, + /* deprecated - PowerOnLevel */ + ZCL_BALLAST_CONFIG_ATTR_POWER_ON_LEVEL = 0x0012, + /* deprecated - PowerOnFadeTime */ + ZCL_BALLAST_CONFIG_ATTR_POWER_ON_FADE_TIME = 0x0013, + ZCL_BALLAST_CONFIG_ATTR_INTRINSIC_BALLAST_FACTOR = 0x0014, + ZCL_BALLAST_CONFIG_ATTR_BALLAST_FACTOR_ADJUSTMENT = 0x0015, + + /* Lamp Information Attribute Set */ + ZCL_BALLAST_CONFIG_ATTR_LAMP_QUANTITY = 0x0020, + + /* Lamp Settings Attribute Set */ + ZCL_BALLAST_CONFIG_ATTR_LAMP_TYPE = 0x0030, + ZCL_BALLAST_CONFIG_ATTR_LAMP_MANUFACTURER = 0x0031, + ZCL_BALLAST_CONFIG_ATTR_LAMP_RATED_HOURS = 0x0032, + ZCL_BALLAST_CONFIG_ATTR_LAMP_BURN_HOURS = 0x0033, + ZCL_BALLAST_CONFIG_ATTR_LAMP_ALARM_MODE = 0x0034, + ZCL_BALLAST_CONFIG_ATTR_LAMP_BURN_HOURS_TRIP_POINT = 0x0035, +}; + +/* Ballast Information attribute set defines*/ +#define ZCL_BALLAST_CONFIG_PHY_MIN_LEVEL_DEFAULT 0x01 +#define ZCL_BALLAST_CONFIG_PHY_MIN_LEVEL_MIN 0x01 +#define ZCL_BALLAST_CONFIG_PHY_MIN_LEVEL_MAX 0xfe + +#define ZCL_BALLAST_CONFIG_PHY_MAX_LEVEL_DEFAULT 0xfe +#define ZCL_BALLAST_CONFIG_PHY_MAX_LEVEL_MIN 0x01 +#define ZCL_BALLAST_CONFIG_PHY_MAX_LEVEL_MAX 0xfe + +#define ZCL_BALLAST_CONFIG_BALLAST_STATUS_DEFAULT 0x00 +#define ZCL_BALLAST_CONFIG_BALLAST_STATUS_MAX 0x03 + +#define ZCL_BALLAST_CONFIG_BALLAST_STATUS_NON_OPERATIONAL_BIT 0x00 +#define ZCL_BALLAST_CONFIG_BALLAST_STATUS_LAMP_FAILURE_BIT 0x01 +#define ZCL_BALLAST_CONFIG_BALLAST_STATUS_BIT_MASK \ + ((1 << ZCL_BALLAST_CONFIG_BALLAST_STATUS_NON_OPERATIONAL_BIT) | \ + (1 << ZCL_BALLAST_CONFIG_BALLAST_STATUS_LAMP_FAILURE_BIT)) + +/* Ballast status - Ballast Non-operational */ +enum ZbZclBallastStatusNonOper { + ZCL_BC_BALLAST_STATUS_OPERATIONAL = 0x00, + ZCL_BC_BALLAST_STATUS_NOT_OPERATIONAL = 0x01, +}; + +/* Ballast status - Lamp Failure */ +enum ZbZclBallastStatusLampFailure { + ZCL_BC_BALLAST_STATUS_LAMP_OPERATIONAL = 0x00, + ZCL_BC_BALLAST_STATUS_LAMP_FAILURE = 0x01, +}; + +/* Ballast Settings attribute set defines*/ +#define ZCL_BALLAST_CONFIG_MIN_LEVEL_MIN 0x01 +#define ZCL_BALLAST_CONFIG_MIN_LEVEL_MAX 0xfe + +#define ZCL_BALLAST_CONFIG_MAX_LEVEL_MIN 0x01 +#define ZCL_BALLAST_CONFIG_MAX_LEVEL_MAX 0xfe + +#define ZCL_BALLAST_CONFIG_INTRINSIC_BALLAST_FACTOR_DEFAULT 0xff +#define ZCL_BALLAST_CONFIG_INTRINSIC_BALLAST_FACTOR_MIN 0x00 +#define ZCL_BALLAST_CONFIG_INTRINSIC_BALLAST_FACTOR_MAX 0xfe + +#define ZCL_BALLAST_CONFIG_BALLAST_FACTOR_ADJ_DEFAULT 0xff +#define ZCL_BALLAST_CONFIG_BALLAST_FACTOR_ADJ_MIN 0x64 +#define ZCL_BALLAST_CONFIG_BALLAST_FACTOR_ADJ_MAX 0xfe + +/* Ballast Settings attribute set defines*/ +#define ZCL_BALLAST_CONFIG_LAMP_QUANTITY_DEFAULT 0x00 +#define ZCL_BALLAST_CONFIG_LAMP_QUANTITY_MIN 0x00 +#define ZCL_BALLAST_CONFIG_LAMP_QUANTITY_MAX 0xfe + +/* Ballast Settings attribute set defines*/ +#define ZCL_BALLAST_CONFIG_LAMP_TYPE_NAME_LENGTH 0x10 +#define ZCL_BALLAST_CONFIG_LAMP_MANUFACTURER_NAME_LENGTH 0x10 + +#define ZCL_BALLAST_CONFIG_LAMP_RATED_HOURS_DEFAULT 0xffffff +#define ZCL_BALLAST_CONFIG_LAMP_RATED_HOURS_MIN 0x000000 +#define ZCL_BALLAST_CONFIG_LAMP_RATED_HOURS_MAX 0xfffffe + +#define ZCL_BALLAST_CONFIG_LAMP_BURN_HOURS_DEFAULT 0x000000 +#define ZCL_BALLAST_CONFIG_LAMP_BURN_HOURS_UNKNOWN 0xffffff +#define ZCL_BALLAST_CONFIG_LAMP_BURN_HOURS_MIN 0x000000 +#define ZCL_BALLAST_CONFIG_LAMP_BURN_HOURS_MAX 0xfffffe + +#define ZCL_BALLAST_CONFIG_LAMP_ALARM_MODE_DEFAULT 0x00 +#define ZCL_BALLAST_CONFIG_LAMP_ALARM_MODE_BIT_MASK 0x01 +#define ZCL_BALLAST_CONFIG_LAMP_ALARM_MODE_BIT_POS 0x00 +#define ZCL_BALLAST_CONFIG_LAMP_BURN_HOUR_ALARM_CODE 0x01 + +#define ZCL_BALLAST_CONFIG_LAMP_BURN_HOURS_TRIP_POINT_DEFAULT 0xffffff +#define ZCL_BALLAST_CONFIG_LAMP_BURN_HOURS_TRIP_POINT_MIN 0x000000 +#define ZCL_BALLAST_CONFIG_LAMP_BURN_HOURS_MAX 0xfffffe + +/*--------------------------------------------------------------- + * Ballast Configuration Cluster Definitions + *--------------------------------------------------------------- + */ +struct ZbZclClusterT * ZbZclBallastConfigServerAlloc(struct ZigBeeT *zb, + uint8_t endpoint, uint8_t phyMin, uint8_t phyMax); + +struct ZbZclClusterT * ZbZclBallastConfigClientAlloc(struct ZigBeeT *zb, + uint8_t endpoint); + +#endif /* __ZCL_BALLAST_CONFIG_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.basic.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.basic.h new file mode 100644 index 000000000..740b0d3b4 --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.basic.h @@ -0,0 +1,144 @@ +/** + * @file zcl.basic.h + * @brief ZCL Basic Cluster + * @author Exegin Technologies + * @copyright Copyright [2009 - 2019] Exegin Technologies Limited. All rights reserved. + * + * Client and Server support for the ZCL Basic Cluster + * + * The Basic cluster is unique amoung the ZCL clusters in ZSDK. There is no + * public API to create a new instance, i.e. ZbZclBasicServerAlloc does not + * exist. The stack automatically allocates a new instance of the Basic + * server cluster on every endpoint ...MORE HERE + */ + +#ifndef ZCL_BASIC_H +# define ZCL_BASIC_H + +/* PICS.ZCL.Basic + * B.S | True + * B.C | True + * + * Server Attributes + * B.S.A0000 | True + * B.S.A0001 | True + * B.S.A0002 | True + * B.S.A0003 | True + * B.S.A0004 | True + * B.S.A0005 | True + * B.S.A0006 | True + * B.S.A0007 | True + * B.S.A0008 | False + * B.S.A0009 | False + * B.S.A000a | False + * B.S.A000b | False + * B.S.A0010 | True + * B.S.A0011 | True + * B.S.A0012 | False (ZSDK-2519) + * B.S.A0013 | True + * B.S.A0014 | True + * B.S.A4000 | True + * B.S.Afffd | True + * B.S.Afffe | False + * + * Commands Received + * B.S.C00.Rsp | True + * + * + * Client Attributes + * B.C.Afffd | True + * B.C.Afffe | False + * + * Commands Generated + * B.C.C00.Tx | True + */ + +#include "zcl/zcl.h" + +/* Basic Cluster Attribute Identifiers */ +enum { + ZCL_BASIC_ATTR_ZCL_VERSION = 0x0000, + ZCL_BASIC_ATTR_APP_VERSION, /* 0x0001 */ + ZCL_BASIC_ATTR_STACK_VERSION, /* 0x0002 */ + ZCL_BASIC_ATTR_HARDWARE_VERSION, /* 0x0003 */ + ZCL_BASIC_ATTR_MFR_NAME, /* 0x0004 */ + ZCL_BASIC_ATTR_MODEL_NAME, /* 0x0005 */ + ZCL_BASIC_ATTR_DATE_CODE, /* 0x0006 */ + ZCL_BASIC_ATTR_POWER_SOURCE, /* 0x0007 */ + + ZCL_BASIC_ATTR_LOCATION = 0x0010, + ZCL_BASIC_ATTR_ENVIRONMENT, /* 0x0011 */ + ZCL_BASIC_ATTR_ENABLED, /* 0x0012 */ + ZCL_BASIC_ATTR_ALARM_MASK, /* 0x0013 */ + ZCL_BASIC_ATTR_DISABLE_LOCAL_CONFIG, /* 0x0014 */ + + ZCL_BASIC_ATTR_SW_BUILD_ID = 0x4000 +}; + +/* Power Source Enumerations */ +#define ZCL_BASIC_POWER_UNKNOWN 0x00 +#define ZCL_BASIC_POWER_SINGLE_PHASE 0x01 +#define ZCL_BASIC_POWER_THREE_PHASE 0x02 +#define ZCL_BASIC_POWER_BATTERY 0x03 +#define ZCL_BASIC_POWER_DC 0x04 +#define ZCL_BASIC_POWER_EMERGENCY_CONSTANT 0x05 +#define ZCL_BASIC_POWER_EMERGENCY_TRANSFER 0x06 +#define ZCL_BASIC_POWER_BATTERY_BACKUP_BIT 0x80 + +/* Physical Environment Enumerations */ +#define ZCL_BASIC_ENVIRONMENT_UNSPECIFIED 0x00 +#define ZCL_BASIC_ENVIRONMENT_MIRROR_SUPPORT 0x01 +#define ZCL_BASIC_ENVIRONMENT_UNKNOWN 0xff + +/* Alarm Codes */ +#define ZCL_BASIC_ALARM_CODE_HARDWARE 0x00 +#define ZCL_BASIC_ALARM_CODE_SOFTWARE 0x01 + +/* Alarm Mask */ +#define ZCL_BASIC_ALARM_MASK_ALL 0x03U +#define ZCL_BASIC_ALARM_MASK_HARDWARE 0x01U +#define ZCL_BASIC_ALARM_MASK_SOFTWARE 0x02U + +/* ZCL Version Identifier. */ +#define ZCL_BASIC_ZCL_VERSION 0x02 + +/* Local Config */ +#define ZCL_BASIC_LOCAL_CONFIG_RESET_DISABLE 0x01U +#define ZCL_BASIC_LOCAL_CONFIG_DEVICE_DISABLE 0x02U + +/* Commands */ +enum { + ZCL_BASIC_RESET_FACTORY = 0x00 +}; + +/*--------------------------------------------------------------- + * Basic Server + *--------------------------------------------------------------- + */ +/* The Basic Server is a special cluster that has global attributes and + * behaviour. The API is found in zigbee.h. */ + +/** + * @brief Instantiate a new instance of the Basic client cluster + * + * Creates a new instance of the Basic client cluster + * + * @param zb the ZSDK stack pointer + * @param endpoint the endpoint on which the new cluster instance will reside + * @return a new Basic client cluster or NULL on error + */ +struct ZbZclClusterT * ZbZclBasicClientAlloc(struct ZigBeeT *zb, uint8_t endpoint); + +/** + * @brief Send Basic Cluster Reset to Factory Defaults command to the server + * + * The reset to factory defaults commands instructs the server to resets all attributes + * to their factory default values. Other functionality is not affected. + * + * @param clusterPtr the client cluster from which to send the command + * @param dst the destination address to the server to which the command is sent + * @return ZCL_STATUS_SUCEESS if successful or other ZclStatusCodeT value on error + */ +enum ZclStatusCodeT ZbZclBasicClientResetReq(struct ZbZclClusterT *clusterPtr, struct ZbApsAddrT *dst); + +#endif /* __ZCL_BASIC_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.device.temp.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.device.temp.h new file mode 100644 index 000000000..fd5c4da24 --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.device.temp.h @@ -0,0 +1,77 @@ +/* Copyright [2017 - 2019] Exegin Technologies Limited. All rights reserved. */ + +#ifndef ZCL_DEVICE_TEMP_H +#define ZCL_DEVICE_TEMP_H + +/*-------------------------------------------------------------------------- + * DESCRIPTION + * ZCL Device Temperature Configuration cluster definitions + *-------------------------------------------------------------------------- + */ + +/* PICS.ZCL.Device_Temo + * DTMP.S | True + * DTMP.C | True + * + * Server Attributes + * DTMP.S.A0000 | True + * DTMP.S.A0001 | True + * DTMP.S.A0002 | True + * DTMP.S.A0003 | False + * DTMP.S.A0010 | True + * DTMP.S.A0011 | True + * DTMP.S.A0012 | True + * DTMP.S.A0013 | True + * DTMP.S.A0014 | True + * DTMP.S.Afffd | True + * DTMP.S.Afffe | False + * + * + * Client Attributes + * DTMP.C.Afffd | True + * DTMP.C.Afffe | False + */ + +#include "zcl/zcl.h" + +/*--------------------------------------------------------------- + * Definitions + *--------------------------------------------------------------- + */ +/* Attribute Identifiers */ +enum { + ZCL_DEV_TEMP_CURRENT = 0x0000, + ZCL_DEV_TEMP_MIN_TEMP = 0x0001, + ZCL_DEV_TEMP_MAX_TEMP = 0x0002, + ZCL_DEV_TEMP_OVER_TEMP_DWELL = 0x0003, /* not currently supported */ + ZCL_DEV_TEMP_ALARM_MASK = 0x0010, + ZCL_DEV_TEMP_LOW_THRESHOLD = 0x0011, + ZCL_DEV_TEMP_HIGH_THRESHOLD = 0x0012, + ZCL_DEV_TEMP_LOW_DWELL_TRIP = 0x0013, + ZCL_DEV_TEMP_HIGH_DWELL_TRIP = 0x0014, +}; + +#define ZCL_DEVICE_TEMP_MIN (-200) +#define ZCL_DEVICE_TEMP_MAX 200 + +/* Indicates an invalid temperature, or if set to a threshold value, + * the alarm for that threshold is disabled. */ +#define ZCL_DEVICE_TEMP_INVALID ((int16_t)0x8000) + +/* Alarm Mask */ +enum { + ZCL_DEV_TEMP_ALARM_MASK_CLEAR = 0x00, + ZCL_DEV_TEMP_ALARM_MASK_LOW = 0x01, + ZCL_DEV_TEMP_ALARM_MASK_HIGH = 0x02, +}; + +/* Alarms */ +enum { + ZCL_DEV_TEMP_ALARM_CODE_LOW = 0x00, + ZCL_DEV_TEMP_ALARM_CODE_HIGH = 0x01, +}; + +struct ZbZclClusterT * ZbZclDevTempClientAlloc(struct ZigBeeT *zb, uint8_t endpoint); +struct ZbZclClusterT * ZbZclDevTempServerAlloc(struct ZigBeeT *zb, uint8_t endpoint); + +#endif /* __ZCL_DEVICE_TEMP_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.h index e2a80eae5..67f1515c4 100644 --- a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.h +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.h @@ -189,14 +189,11 @@ typedef uint16_t ZclAttrFlagT; #define ZCL_ATTR_FLAG_REPORTABLE (ZclAttrFlagT)0x0002U /* attribute is persisted */ #define ZCL_ATTR_FLAG_PERSISTABLE (ZclAttrFlagT)0x0004U -/* attribute is allowed to be reset to a default value */ -#define ZCL_ATTR_FLAG_DEFAULTABLE (ZclAttrFlagT)0x0008U /* Which callbacks does the application support */ #define ZCL_ATTR_FLAG_CB_MASK 0x00f0U #define ZCL_ATTR_FLAG_CB_READ (ZclAttrFlagT)0x0010U /* ZCL_ATTR_CB_TYPE_READ */ #define ZCL_ATTR_FLAG_CB_WRITE (ZclAttrFlagT)0x0020U /* ZCL_ATTR_CB_TYPE_WRITE */ -#define ZCL_ATTR_FLAG_CB_DEFAULT (ZclAttrFlagT)0x0040U /* ZCL_ATTR_CB_TYPE_DEFAULT */ -#define ZCL_ATTR_FLAG_CB_NOTIFY (ZclAttrFlagT)0x0080U /* ZCL_ATTR_CB_TYPE_NOTIFY */ +#define ZCL_ATTR_FLAG_CB_NOTIFY (ZclAttrFlagT)0x0040U /* ZCL_ATTR_CB_TYPE_NOTIFY */ /* This flag means the attribute is for internal use only. Not discoverable. */ #define ZCL_ATTR_FLAG_INTERNAL (ZclAttrFlagT)0x8000U @@ -215,14 +212,14 @@ typedef uint16_t ZclWriteModeT; /* ZCL Data Types */ enum ZclDataTypeT { ZCL_DATATYPE_NULL = 0x00, - ZCL_DATATYPE_GENERIC_8BIT = 0x08, - ZCL_DATATYPE_GENERIC_16BIT = 0x09, - ZCL_DATATYPE_GENERIC_24BIT = 0x0a, - ZCL_DATATYPE_GENERIC_32BIT = 0x0b, - ZCL_DATATYPE_GENERIC_40BIT = 0x0c, - ZCL_DATATYPE_GENERIC_48BIT = 0x0d, - ZCL_DATATYPE_GENERIC_56BIT = 0x0e, - ZCL_DATATYPE_GENERIC_64BIT = 0x0f, + ZCL_DATATYPE_GENERAL_8BIT = 0x08, + ZCL_DATATYPE_GENERAL_16BIT = 0x09, + ZCL_DATATYPE_GENERAL_24BIT = 0x0a, + ZCL_DATATYPE_GENERAL_32BIT = 0x0b, + ZCL_DATATYPE_GENERAL_40BIT = 0x0c, + ZCL_DATATYPE_GENERAL_48BIT = 0x0d, + ZCL_DATATYPE_GENERAL_56BIT = 0x0e, + ZCL_DATATYPE_GENERAL_64BIT = 0x0f, ZCL_DATATYPE_BOOLEAN = 0x10, ZCL_DATATYPE_BITMAP_8BIT = 0x18, ZCL_DATATYPE_BITMAP_16BIT = 0x19, @@ -807,7 +804,6 @@ enum ZclStatusCodeT ZbZclAttrAppendList(struct ZbZclClusterT *clusterPtr, const enum ZbZclAttrCbTypeT { ZCL_ATTR_CB_TYPE_READ, /* Read Attribute */ ZCL_ATTR_CB_TYPE_WRITE, /* Write Attribute */ - ZCL_ATTR_CB_TYPE_DEFAULT, /* Write Default Value */ ZCL_ATTR_CB_TYPE_NOTIFY /* Write Notification */ }; @@ -968,7 +964,7 @@ void ZbZclRemoveEndpoint(struct ZigBeeT *zb, ZbApsmeRemoveEndpointReqT *req, ZbA void * ZbZclClusterAlloc(struct ZigBeeT *zb, unsigned int alloc_sz, enum ZbZclClusterIdT cluster_id, uint8_t endpoint, enum ZbZclDirectionT direction); /* Attach the cluster to the stack (after callbacks have been configured) */ -void ZbZclClusterAttach(struct ZbZclClusterT *clusterPtr); +enum ZclStatusCodeT ZbZclClusterAttach(struct ZbZclClusterT *clusterPtr); /* Free and detach the cluster */ void ZbZclClusterFree(struct ZbZclClusterT *clusterPtr); @@ -998,6 +994,7 @@ int ZbZclAppendHeader(struct ZbZclHeaderT *zclHdrPtr, uint8_t *data, unsigned in */ int ZbZclAttrParseLength(enum ZclDataTypeT type, const uint8_t *ptr, unsigned int max_len, uint8_t recurs_depth); +bool ZbZclAttrIsFloat(enum ZclDataTypeT dataType); bool ZbZclAttrIsAnalog(enum ZclDataTypeT dataType); bool ZbZclAttrIsInteger(enum ZclDataTypeT dataType); @@ -1061,18 +1058,27 @@ extern const uint8_t zcl_attr_str_short_zero[1]; /* i.e. {0x00} */ extern const uint8_t zcl_attr_str_long_zero[2]; /* i.e. {0x00, 0x00} */ /*--------------------------------------------------------------- - * Request Remote reporting of attribute changes. + * Configure Reporting *--------------------------------------------------------------- */ -typedef struct { +struct ZbZclAttrReportConfigT { struct ZbApsAddrT dst; uint16_t min; uint16_t max; - uint16_t attribute; + uint16_t attr_id; uint8_t attr_type; -} ZbZclAttrReportT; + uint64_t change; +}; + +enum ZclStatusCodeT ZbZclAttrReportConfigReq(struct ZbZclClusterT *clusterPtr, struct ZbZclAttrReportConfigT *report, + void (*callback)(struct ZbZclCommandRspT *cmd_rsp, void *arg), void *arg); + +struct ZbZclAttrReportReadT { + struct ZbApsAddrT dst; + uint16_t attr_id; +}; -void ZbZclAttrReportConfigReq(struct ZbZclClusterT *clusterPtr, ZbZclAttrReportT *rp, +enum ZclStatusCodeT ZbZclAttrReportReadReq(struct ZbZclClusterT *clusterPtr, struct ZbZclAttrReportReadT *report, void (*callback)(struct ZbZclCommandRspT *cmd_rsp, void *arg), void *arg); /*--------------------------------------------------------------- @@ -1311,17 +1317,18 @@ bool ZbZclDeviceLogRemove(struct ZigBeeT *zb, uint64_t ext_addr); void ZbZclDeviceLogClear(struct ZigBeeT *zb); /*--------------------------------------------------------------- - * ZCL Command Request/Response Helpers + * ZCL Internal Use Only *--------------------------------------------------------------- */ -#define ZCL_STATE_CONTINUE 0 /* Return zero to continue waiting for responses. */ -#define ZCL_STATE_CLEANUP 1 /* Return one to cleanup the state. */ +enum ZclStateReqReturn { + ZCL_STATE_CONTINUE = 0, /**< Return zero to continue waiting for responses. */ + ZCL_STATE_CLEANUP /**< Return one to cleanup the state. */ +}; -typedef int (*ZbZclHandlerFuncT)(struct ZbZclCommandRspT *cmdRsp, void (*callback)(void *msg, void *arg), void *arg); +typedef enum ZclStateReqReturn (*ZbZclHandlerFuncT)(struct ZbZclCommandRspT *cmdRsp, void *callback, void *arg); enum ZclStatusCodeT ZbZclStateBegin(struct ZigBeeT *zb, ZbApsdeDataReqT *apsReq, struct ZbZclHeaderT *zclHdr, - unsigned int timeout, ZbZclHandlerFuncT handler, - void (*callback)(void *msg, void *arg), void *arg); + unsigned int timeout, ZbZclHandlerFuncT handler, void *callback, void *arg); /*--------------------------------------------------------------- * Helper Functions @@ -1330,9 +1337,6 @@ enum ZclStatusCodeT ZbZclStateBegin(struct ZigBeeT *zb, ZbApsdeDataReqT *apsReq, /* Get the next ZCL sequence number to use in a request/notify message. */ uint8_t ZbZclGetNextSeqnum(void); -/* Tell all of this cluster's attributes to revert to default values */ -void ZbZclClusterAttrWriteDefaults(struct ZbZclClusterT *clusterPtr, bool force); - /* Helper functions to SET cluster parameters */ void ZbZclClusterSetCallbackArg(struct ZbZclClusterT *clusterPtr, void *app_cb_arg); void ZbZclClusterSetMfrCode(struct ZbZclClusterT *clusterPtr, uint16_t mfrCode); @@ -1390,8 +1394,6 @@ enum { /* Exegin's Manufacturer Specific Global Commands * ZCL_FRAMECTRL_MANUFACTURER && ZCL_FRAMETYPE_PROFILE && (Manufacturer Code == ZCL_MANUF_CODE_INTERNAL) */ enum { - ZCL_CMD_MANUF_INTERNAL_ATTR_RESET_DEFAULT, /* attr_reset() */ - /* For Scene Store Command (ZCL_SCENES_COMMAND_STORE_SCENE) * Payload for Request (to Server): None * Payload for Response: [CLUSTER(2) | EXT_LEN(1) | EXT_ATTR_DATA(N)] */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.identify.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.identify.h index 3f6af4a51..77746b9bb 100644 --- a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.identify.h +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.identify.h @@ -85,9 +85,9 @@ void ZbZclIdentifyServerSetTime(struct ZbZclClusterT *clusterPtr, uint16_t secon uint16_t ZbZclIdentifyServerGetTime(struct ZbZclClusterT *clusterPtr); /* Client commands */ -uint8_t zcl_identify_identify_request(struct ZbZclClusterT *cluster, const struct ZbApsAddrT *dst, +enum ZclStatusCodeT zcl_identify_identify_request(struct ZbZclClusterT *cluster, const struct ZbApsAddrT *dst, uint16_t identify_time, void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); -uint8_t zcl_identify_query_request(struct ZbZclClusterT *cluster, const struct ZbApsAddrT *dst, +enum ZclStatusCodeT zcl_identify_query_request(struct ZbZclClusterT *cluster, const struct ZbApsAddrT *dst, void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); #endif /* __ZCL_IDENTIFY_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.illum.meas.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.illum.meas.h new file mode 100644 index 000000000..fd50429dd --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.illum.meas.h @@ -0,0 +1,72 @@ +/* Copyright [2009 - 2019] Exegin Technologies Limited. All rights reserved. */ + +#ifndef ZCL_ILLUM_MEAS_H +# define ZCL_ILLUM_MEAS_H + +/*-------------------------------------------------------------------------- + * DESCRIPTION + * Interface definition for the ZCL Illuminance Measurement cluster. + *-------------------------------------------------------------------------- + */ + +/* PICS.ZCL.Illuminance_Measurement + * IM.S | True + * IM.C | True + * + * Server Attributes + * IM.S.A0000 | True + * IM.S.A0000.Report.Tx | True + * IM.S.A0001 | True + * IM.S.A0002 | True + * IM.S.A0003 | False + * IM.S.A0004 | False + * IM.S.Afffd | True + * IM.S.Afffe | False + * + * + * Client Attributes + * IM.C.A0000.Report.Rsp | False + * IM.C.Afffd | True + * IM.C.Afffe | False + */ + +#include "zcl/zcl.h" + +/*--------------------------------------------------------------- + * Illuminance Measurement Cluster Definitions + *--------------------------------------------------------------- + */ +/* Illuminance Measurement Information Attribute Set */ +enum { + ZCL_ILLUM_MEAS_ATTR_MEAS_VAL = 0x0000, + ZCL_ILLUM_MEAS_ATTR_MIN_MEAS_VAL = 0x0001, + ZCL_ILLUM_MEAS_ATTR_MAX_MEAS_VAL = 0x0002, + ZCL_ILLUM_MEAS_ATTR_TOLERANCE = 0x0003, + ZCL_ILLUM_MEAS_ATTR_LIGHT_SENSOR_TYPE = 0x0004, +}; + +/* Illuminance Measurement Defines */ +#define ZCL_ILLUM_MEAS_MEASURED_DEFAULT 0x0000 +#define ZCL_ILLUM_MEAS_UNKNOWN 0xffff +#define ZCL_ILLUM_MEAS_MIN_MEAS_VAL_MIN 0x0001 +#define ZCL_ILLUM_MEAS_MIN_MEAS_VAL_MAX 0xfffd +#define ZCL_ILLUM_MEAS_MIN_MEAS_VAL_UNKNOWN 0xffff +#define ZCL_ILLUM_MEAS_MAX_MEAS_VAL_MIN 0x0002 +#define ZCL_ILLUM_MEAS_MAX_MEAS_VAL_MAX 0xfffe +#define ZCL_ILLUM_MEAS_MAX_MEAS_VAL_UNKNOWN 0xffff +#define ZCL_ILLUM_MEAS_TOLERANCE_MIN 0x0000 +#define ZCL_ILLUM_MEAS_TOLERANCE_MAX 0x0800 +#define ZCL_ILLUM_MEAS_LIGHT_SENS_TYPE_PHOTODIODE 0x0000 +#define ZCL_ILLUM_MEAS_LIGHT_SENS_TYPE_CMOS 0x0001 +#define ZCL_ILLUM_MEAS_LIGHT_SENS_TYPE_UNKNOWN 0x00ff + +/*--------------------------------------------------------------- + * Illuminance Measurement Cluster Definitions + *--------------------------------------------------------------- + */ +struct ZbZclClusterT * ZbZclIllumMeasServerAlloc(struct ZigBeeT *zb, + uint8_t endpoint, uint16_t min, uint16_t max); + +struct ZbZclClusterT * ZbZclIllumMeasClientAlloc(struct ZigBeeT *zb, uint8_t endpoint); + +#endif /* __ZCL_ILLUM_MEAS_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.meter.id.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.meter.id.h new file mode 100644 index 000000000..153eb8f34 --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.meter.id.h @@ -0,0 +1,62 @@ +/* Copyright [2019 - 2019] Exegin Technologies Limited. All rights reserved. */ + +#ifndef ZCL_METER_ID_H +#define ZCL_METER_ID_H + +#include "zcl/zcl.h" + +/*-------------------------------------------------------------------------- + * DESCRIPTION + * Interface definition for the ZCL Meter Identification cluster. + *-------------------------------------------------------------------------- + */ + +/* PICS.ZCL.Electrical.Measurement + * MTRID.S | True + * MTRID.C | True + * + * Server Attributes + * MTRID.S.A0000 | True + * MTRID.S.A0001 | True + * MTRID.S.A0004 | True + * MTRID.S.A0005 | False + * MTRID.S.A0006 | False + * MTRID.S.A0007 | False + * MTRID.S.A0008 | False + * MTRID.S.A000a | False + * MTRID.S.A000b | False + * MTRID.S.A000c | True + * MTRID.S.A000d | True + * MTRID.S.A000e | True + * MTRID.S.Afffd | True + * MTRID.S.Afffe | False + */ + +/* Attribute Identifiers */ +enum { + ZCL_METER_ID_ATTR_COMPANY_NAME = 0x0000, + ZCL_METER_ID_ATTR_METER_TYPE_ID = 0x0001, + ZCL_METER_ID_ATTR_DATA_QUAL_ID = 0x0004, + ZCL_METER_ID_ATTR_CUSTOMER_NAME = 0x0005, + ZCL_METER_ID_ATTR_MODEL = 0x0006, + ZCL_METER_ID_ATTR_PART_NUMBER = 0x0007, + ZCL_METER_ID_ATTR_PRODUCT_REV = 0x0008, + ZCL_METER_ID_ATTR_SOFTWARE_REV = 0x000A, + ZCL_METER_ID_ATTR_UTILITY_NAME = 0x000B, + ZCL_METER_ID_ATTR_POD = 0x000C, + ZCL_METER_ID_ATTR_AVAILABLE_POWER = 0x000D, + ZCL_METER_ID_ATTR_POWER_THRESH = 0x000E +}; + +/* Level Status values */ +#define ZCL_METER_ID_COMPANY_NAME_LEN 32U +#define ZCL_METER_ID_POD_LEN 32U + +/*--------------------------------------------------------------- + * Meter Identification Cluster Definitions + *--------------------------------------------------------------- + */ +struct ZbZclClusterT * ZbZclMeterIdClientAlloc(struct ZigBeeT *zb, uint8_t endpoint); +struct ZbZclClusterT * ZbZclMeterIdServerAlloc(struct ZigBeeT *zb, uint8_t endpoint); + +#endif /* __ZCL_METER_ID_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.occupancy.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.occupancy.h new file mode 100644 index 000000000..e0ee1abfd --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.occupancy.h @@ -0,0 +1,63 @@ +/* Copyright [2009 - 2019] Exegin Technologies Limited. All rights reserved. */ + +#ifndef ZCL_OCCUP_H +# define ZCL_OCCUP_H + +/* PICS.ZCL.Occupancy + * OS.S | True + * OS.C | True + * + * Occupancy Sensor Type + * OS.S.OST00 | False + * OS.S.OST01 | False + * OS.S.OST02 | False + * + * Server Attributes + * OS.S.A0000 | True + * OS.S.A0000.Report.Tx | True + * OS.S.A0001 | True + * OS.S.A0002 | True + * OS.S.A0010 | True + * OS.S.A0011 | True + * OS.S.A0012 | True + * OS.S.A0020 | True + * OS.S.A0021 | True + * OS.S.A0022 | True + * OS.S.A0030 | False + * OS.S.A0031 | False + * OS.S.A0032 | False + * OS.S.Afffd | True + * OS.S.Afffe | False + * + * Client Attributes + * OS.C.A0000.Report.Rsp | False + * OS.C.Afffd | True + * OS.C.Afffe | False + */ + +#include "zcl/zcl.h" + +/* Power Configuration Cluster Attributes */ +enum { + ZCL_OCC_ATTR_OCCUPANCY = 0x0000, /* R- mandatory! */ + ZCL_OCC_ATTR_SENSORTYPE = 0x0001, /* R- mandatory! */ + ZCL_OCC_ATTR_SENSORTYPE_BITMAP = 0x0002, /* R- mandatory! */ + ZCL_OCC_ATTR_PIR_OU_DELAY = 0x0010, /* RW */ + ZCL_OCC_ATTR_PIR_UO_DELAY = 0x0011, /* RW */ + ZCL_OCC_ATTR_PIR_UO_THRESHOLD = 0x0012, /* RW */ + ZCL_OCC_ATTR_US_OU_DELAY = 0x0020, /* RW */ + ZCL_OCC_ATTR_US_UO_DELAY = 0x0021, /* RW */ + ZCL_OCC_ATTR_US_UO_THRESHOLD = 0x0022, /* RW */ + ZCL_OCC_ATTR_PHY_OU_DELAY = 0x0030, /* RW */ + ZCL_OCC_ATTR_PHY_UO_DELAY = 0x0031, /* RW */ + ZCL_OCC_ATTR_PHY_UO_THRESHOLD = 0x0032, /* RW */ +}; + +#define OCC_SENSOR_PIR 0x00 +#define OCC_SENSOR_ULTRASONIC 0x01 +#define OCC_SENSOR_PIR_ULTRASONIC 0x02 + +struct ZbZclClusterT * ZbZclOccupancyClientAlloc(struct ZigBeeT *zb, uint8_t ept); +struct ZbZclClusterT * ZbZclOccupancyServerAlloc(struct ZigBeeT *zb, uint8_t ept); + +#endif /* ZCL_OCCUP_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.onoff.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.onoff.h index 2e7a0fd64..8c430e6ab 100644 --- a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.onoff.h +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.onoff.h @@ -33,8 +33,7 @@ * OO.S.C41.Rsp | False * OO.S.C42.Rsp | False * - * - * OO.C.A0000.Report.Rsp | False (https://exegin.atlassian.net/browse/ZSDK-2624) + * OO.C.A0000.Report.Rsp | False * * OO.C.Afffd | True * @@ -72,7 +71,16 @@ enum { * OnOff Server Cluster *--------------------------------------------------------------- */ -struct ZbZclClusterT * ZbZclOnOffServerAlloc(struct ZigBeeT *zb, uint8_t endpoint, void *arg); +struct ZbZclOnOffServerCallbacksT { + /* The application is expected to update ZCL_ONOFF_ATTR_ONOFF if these callbacks are + * successfully executed. */ + enum ZclStatusCodeT (*off)(struct ZbZclClusterT *clusterPtr, struct ZbZclAddrInfoT *srcInfo, void *arg); + enum ZclStatusCodeT (*on)(struct ZbZclClusterT *clusterPtr, struct ZbZclAddrInfoT *srcInfo, void *arg); + enum ZclStatusCodeT (*toggle)(struct ZbZclClusterT *clusterPtr, struct ZbZclAddrInfoT *srcInfo, void *arg); +}; + +struct ZbZclClusterT * ZbZclOnOffServerAlloc(struct ZigBeeT *zb, uint8_t endpoint, + struct ZbZclOnOffServerCallbacksT *callbacks, void *arg); /* Allow the Level Control Cluster to be notified of OnOff commands */ typedef void (*ZbZclLevelControlCallbackT)(struct ZbZclClusterT *level_cluster, uint8_t on_off_command); diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.power.profile.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.power.profile.h new file mode 100644 index 000000000..f267528a6 --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.power.profile.h @@ -0,0 +1,328 @@ +/* Copyright [2019 - 2019] Exegin Technologies Limited. All rights reserved. */ + +#ifndef ZCL_PWR_PROF_H +#define ZCL_PWR_PROF_H + +#include "zcl/zcl.h" + +/* Attribute Identifiers */ +enum { + ZCL_POWER_PROF_SVR_ATTR_TOTAL_PROFILENUM = 0x0000, + ZCL_POWER_PROF_SVR_ATTR_MULTIPLE_SCHED = 0x0001, + ZCL_POWER_PROF_SVR_ATTR_ENERGY_FORMAT = 0x0002, + ZCL_POWER_PROF_SVR_ATTR_ENERGY_REMOTE = 0x0003, + ZCL_POWER_PROF_SVR_ATTR_SCHEDULE_MODE = 0x0004 +}; + +/* Client Generated Commands */ +enum { + ZCL_PWR_PROF_CLI_PROFILE_REQ = 0x00, + ZCL_PWR_PROF_CLI_STATE_REQ = 0x01, + ZCL_PWR_PROF_CLI_PRICE_RSP = 0x02, + ZCL_PWR_PROF_CLI_SCHED_PRICE_RSP = 0x03, + ZCL_PWR_PROF_CLI_PHASES_NOTIFY = 0x04, + ZCL_PWR_PROF_CLI_PHASES_RSP = 0x05, + ZCL_PWR_PROF_CLI_SCHED_CONS_REQ = 0x06, + ZCL_PWR_PROF_CLI_PHASES_SCHED_STATE_REQ = 0x07, + ZCL_PWR_PROF_CLI_PRICE_EXT_RSP = 0x08 +}; + +/* Server Generated Commands */ +enum { + ZCL_PWR_PROF_SVR_PROFILE_NOTIFY = 0x00, + ZCL_PWR_PROF_SVR_PROFILE_RSP = 0x01, + ZCL_PWR_PROF_SVR_STATE_RSP = 0x02, + ZCL_PWR_PROF_SVR_GET_PRICE = 0x03, + ZCL_PWR_PROF_SVR_STATE_NOTIFY = 0x04, + ZCL_PWR_PROF_SVR_GET_SCHED_PRICE = 0x05, + ZCL_PWR_PROF_SVR_PHASES_REQ = 0x06, + ZCL_PWR_PROF_SVR_PHASES_RSP = 0x07, + ZCL_PWR_PROF_SVR_PHASES_NOTIFY = 0x08, + ZCL_PWR_PROF_SVR_CONSTRAINTS_NOTIFY = 0x09, + ZCL_PWR_PROF_SVR_CONSTRAINTS_RSP = 0x0a, + ZCL_PWR_PROF_SVR_GET_PRICE_EXT = 0x0b, +}; + +/* Energy Formatting Mask (ZCL_POWER_PROF_SVR_ATTR_ENERGY_FORMAT) */ +#define ZCL_PWR_PROF_ENERGY_FORMAT_DIGITS_TRAIL_MASK 0x07U /* num trailing digits */ +#define ZCL_PWR_PROF_ENERGY_FORMAT_DIGITS_TRAIL_OFFSET 0U +#define ZCL_PWR_PROF_ENERGY_FORMAT_DIGITS_LEAD_MASK 0x78U /* num leading digits */ +#define ZCL_PWR_PROF_ENERGY_FORMAT_DIGITS_LEAD_OFFSET 3U +#define ZCL_PWR_PROF_ENERGY_FORMAT_SUPPRESS_LEADING 0x80U /* suppress leading zeroes */ + +/* ScheduleMode Mask (ZCL_POWER_PROF_SVR_ATTR_SCHEDULE_MODE) */ +#define ZCL_PWR_PROF_SCHED_MODE_CHEAPEST 0x01U +#define ZCL_PWR_PROF_SCHED_MODE_GREENEST 0x02U + +/* BUGBUG - review these values */ +#define ZCL_PWR_PROF_MAX_PROFILES 16U /* theoretical max is 0xfe (254) */ +#define ZCL_PWR_PROF_MAX_ENERGY_PHASES 16U /* theoretical max is 0xfe (254) */ + +enum ZbZclPowerProfState { + ZCL_PWR_PROF_STATE_PROFILE_IDLE = 0x00, + ZCL_PWR_PROF_STATE_PROFILE_PROGRAMMED = 0x01, + ZCL_PWR_PROF_STATE_PHASE_RUNNING = 0x03, + ZCL_PWR_PROF_STATE_PHASE_PAUSED = 0x04, + ZCL_PWR_PROF_STATE_PHASE_WAITING_START = 0x05, + ZCL_PWR_PROF_STATE_PHASE_WAITING_PAUSED = 0x06, + ZCL_PWR_PROF_STATE_PROFILE_ENDED = 0x07 +}; + +struct ZbZclPowerProfPhase { + uint8_t energy_phase_id; + uint8_t macro_phase_id; + uint16_t expect_duration; + uint16_t peak_power; + uint16_t energy; + uint16_t max_activation_delay; +}; + +/* PowerProfileNotification and PowerProfileResponse share the same payload format. */ +struct ZbZclPowerProfSvrProfileRsp { + uint8_t total_profile_num; + uint8_t power_profile_id; + uint8_t num_transferred_phases; + struct ZbZclPowerProfPhase phase_list[ZCL_PWR_PROF_MAX_ENERGY_PHASES]; +}; + +struct ZbZclPowerProfileRecord { + uint8_t power_profile_id; + uint8_t energy_phase_id; + uint8_t remote_control; + enum ZbZclPowerProfState state; +}; + +/* PowerProfileStateResponse */ +struct ZbZclPowerProfSvrStateRsp { + uint8_t profile_count; + struct ZbZclPowerProfileRecord record_list[ZCL_PWR_PROF_MAX_PROFILES]; +}; + +/* PowerProfileRequest */ +struct ZbZclPowerProfCliProfileReq { + uint8_t profile_id; +}; + +struct ZbZclPowerProfSchedPhase { + uint8_t energy_phase_id; + uint16_t sched_time; +}; + +struct ZbZclPowerProfCliPhasesNotify { + uint8_t power_profile_id; + uint8_t num_phases; + struct ZbZclPowerProfSchedPhase sched_list[ZCL_PWR_PROF_MAX_ENERGY_PHASES]; +}; + +struct ZbZclPowerProfCliPriceRsp { + uint8_t power_profile_id; + uint16_t currency; + uint32_t price; + uint8_t trailing_digit; +}; + +struct ZbZclPowerProfCliSchedPriceRsp { + uint16_t currency; + uint32_t price; + uint8_t trailing_digit; +}; + +/* ZCL_PWR_PROF_SVR_PHASES_RSP / ZCL_PWR_PROF_SVR_PHASES_NOTIFY */ +struct ZbZclPowerProfSvrPhasesRsp { + uint8_t power_profile_id; + uint8_t num_sched_energy_phases; +}; + +/* ZCL_PWR_PROF_SVR_CONSTRAINTS_NOTIFY */ +struct ZbZclPowerProfSvrConstraintsNotify { + uint8_t power_profile_id; + uint16_t start_after; + uint16_t stop_before; +}; + +/* GetPowerProfilePriceExtended Command options field */ +#define ZCL_PWR_PROF_PRICE_EXT_OPT_START_TIME_PRESENT 0x01U +#define ZCL_PWR_PROF_PRICE_EXT_OPT_EST_PRICE 0x02U + +/* ZCL_PWR_PROF_SVR_GET_PRICE_EXT */ +struct ZbZclPowerProfSvrGetPriceExtReq { + uint8_t options; /* e.g. ZCL_PWR_PROF_PRICE_EXT_OPT_START_TIME_PRESENT */ + uint8_t power_profile_id; + uint16_t start_time; /* optional (ZCL_PWR_PROF_PRICE_EXT_OPT_START_TIME_PRESENT) */ +}; + +/* Power Profile Client Callbacks + * If application sends a response, the callback return code should be set to + * ZCL_STATUS_SUCCESS_NO_DEFAULT_RESPONSE to prevent a Default Response from also being sent. + */ +struct ZbZclPowerProfClientCallbacks { + /* ZCL_PWR_PROF_SVR_PROFILE_NOTIFY */ + enum ZclStatusCodeT (*profile_notify)(struct ZbZclClusterT *cluster, + struct ZbZclPowerProfSvrProfileRsp *notify, struct ZbZclAddrInfoT *srcInfo, void *arg); + + /* ZCL_PWR_PROF_SVR_GET_PRICE */ + enum ZclStatusCodeT (*get_price)(struct ZbZclClusterT *cluster, + struct ZbZclPowerProfCliProfileReq *req, struct ZbZclAddrInfoT *srcInfo, void *arg); + + /* ZCL_PWR_PROF_SVR_STATE_NOTIFY */ + enum ZclStatusCodeT (*state_notify)(struct ZbZclClusterT *cluster, + struct ZbZclPowerProfSvrStateRsp *notify, struct ZbZclAddrInfoT *srcInfo, void *arg); + + /* ZCL_PWR_PROF_SVR_GET_SCHED_PRICE */ + enum ZclStatusCodeT (*get_sched_price)(struct ZbZclClusterT *cluster, + struct ZbZclAddrInfoT *srcInfo, void *arg); + + /* ZCL_PWR_PROF_SVR_PHASES_REQ */ + enum ZclStatusCodeT (*phases_req)(struct ZbZclClusterT *cluster, + struct ZbZclPowerProfCliProfileReq *req, struct ZbZclAddrInfoT *srcInfo, void *arg); + + /* ZCL_PWR_PROF_SVR_PHASES_NOTIFY */ + enum ZclStatusCodeT (*phases_notify)(struct ZbZclClusterT *cluster, + struct ZbZclPowerProfSvrPhasesRsp *notify, struct ZbZclAddrInfoT *srcInfo, void *arg); + + /* ZCL_PWR_PROF_SVR_CONSTRAINTS_NOTIFY */ + enum ZclStatusCodeT (*constraints_notify)(struct ZbZclClusterT *cluster, + struct ZbZclPowerProfSvrConstraintsNotify *notify, struct ZbZclAddrInfoT *srcInfo, void *arg); + + /* ZCL_PWR_PROF_SVR_GET_PRICE_EXT */ + enum ZclStatusCodeT (*get_price_ext)(struct ZbZclClusterT *cluster, + struct ZbZclPowerProfSvrGetPriceExtReq *req, struct ZbZclAddrInfoT *srcInfo, void *arg); +}; + +struct ZbZclClusterT * ZbZclPowerProfClientAlloc(struct ZigBeeT *zb, uint8_t endpoint, + struct ZbZclPowerProfClientCallbacks *callbacks, void *arg); + +/* ZCL_PWR_PROF_CLI_PROFILE_REQ */ +enum ZclStatusCodeT ZbZclPowerProfClientProfileReq(struct ZbZclClusterT *clusterPtr, + struct ZbZclPowerProfCliProfileReq *req, const struct ZbApsAddrT *dst, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +/* ZCL_PWR_PROF_CLI_STATE_REQ */ +enum ZclStatusCodeT ZbZclPowerProfClientStateReq(struct ZbZclClusterT *clusterPtr, + const struct ZbApsAddrT *dst, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +/* ZCL_PWR_PROF_CLI_PRICE_RSP */ +enum ZclStatusCodeT ZbZclPowerProfClientPriceRsp(struct ZbZclClusterT *clusterPtr, + struct ZbZclAddrInfoT *dst, struct ZbZclPowerProfCliPriceRsp *rsp, + void (*callback)(ZbApsdeDataConfT *conf, void *arg), void *arg); + +/* ZCL_PWR_PROF_CLI_SCHED_PRICE_RSP */ +enum ZclStatusCodeT ZbZclPowerProfClientSchedPriceRsp(struct ZbZclClusterT *clusterPtr, + struct ZbZclAddrInfoT *dst, struct ZbZclPowerProfCliSchedPriceRsp *rsp, + void (*callback)(ZbApsdeDataConfT *conf, void *arg), void *arg); + +/* ZCL_PWR_PROF_CLI_PHASES_NOTIFY */ +enum ZclStatusCodeT ZbZclPowerProfClientPhasesNotify(struct ZbZclClusterT *clusterPtr, + struct ZbZclPowerProfCliPhasesNotify *notify, struct ZbApsAddrT *dst, + void (*callback)(ZbApsdeDataConfT *conf, void *arg), void *arg); + +/* ZCL_PWR_PROF_CLI_PHASES_RSP */ +enum ZclStatusCodeT ZbZclPowerProfClientPhasesResponse(struct ZbZclClusterT *clusterPtr, + struct ZbZclPowerProfCliPhasesNotify *notify, struct ZbZclAddrInfoT *dst, + void (*callback)(ZbApsdeDataConfT *conf, void *arg), void *arg); + +/* ZCL_PWR_PROF_CLI_SCHED_CONS_REQ */ +enum ZclStatusCodeT ZbZclPowerProfClientSchedConsReq(struct ZbZclClusterT *clusterPtr, + struct ZbZclPowerProfCliProfileReq *req, const struct ZbApsAddrT *dst, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +/* ZCL_PWR_PROF_CLI_PHASES_SCHED_STATE_REQ */ +enum ZclStatusCodeT ZbZclPowerProfClientPhasesSchedStateReq(struct ZbZclClusterT *clusterPtr, + struct ZbZclPowerProfCliProfileReq *req, const struct ZbApsAddrT *dst, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +/* ZCL_PWR_PROF_CLI_PRICE_EXT_RSP */ +enum ZclStatusCodeT ZbZclPowerProfClientPriceExtRsp(struct ZbZclClusterT *clusterPtr, + struct ZbZclAddrInfoT *dst, struct ZbZclPowerProfCliPriceRsp *rsp, + void (*callback)(ZbApsdeDataConfT *conf, void *arg), void *arg); + +/* Power Profile Server Callbacks + * If application sends a response, the callback return code should be set to + * ZCL_STATUS_SUCCESS_NO_DEFAULT_RESPONSE to prevent a Default Response from also being sent. + */ +struct ZbZclPowerProfServerCallbacks { + /* ZCL_PWR_PROF_CLI_PROFILE_REQ */ + enum ZclStatusCodeT (*profile_req)(struct ZbZclClusterT *cluster, + struct ZbZclPowerProfCliProfileReq *req, struct ZbZclAddrInfoT *srcInfo, void *arg); + + /* ZCL_PWR_PROF_CLI_STATE_REQ */ + enum ZclStatusCodeT (*state_req)(struct ZbZclClusterT *cluster, + struct ZbZclAddrInfoT *srcInfo, void *arg); + + /* ZCL_PWR_PROF_CLI_PHASES_NOTIFY */ + enum ZclStatusCodeT (*phases_notify)(struct ZbZclClusterT *cluster, + struct ZbZclPowerProfCliPhasesNotify *req, struct ZbZclAddrInfoT *srcInfo, void *arg); + + /* ZCL_PWR_PROF_CLI_SCHED_CONS_REQ */ + enum ZclStatusCodeT (*sched_contraints_req)(struct ZbZclClusterT *cluster, + struct ZbZclPowerProfCliProfileReq *req, struct ZbZclAddrInfoT *srcInfo, void *arg); + + /* ZCL_PWR_PROF_CLI_PHASES_SCHED_STATE_REQ */ + enum ZclStatusCodeT (*phases_sched_state_req)(struct ZbZclClusterT *cluster, + struct ZbZclPowerProfCliProfileReq *req, struct ZbZclAddrInfoT *srcInfo, void *arg); +}; + +struct ZbZclClusterT * ZbZclPowerProfServerAlloc(struct ZigBeeT *zb, uint8_t endpoint, + struct ZbZclPowerProfServerCallbacks *callbacks, void *arg); + +/* ZCL_PWR_PROF_SVR_PROFILE_NOTIFY */ +enum ZclStatusCodeT ZbZclPowerProfServerProfileNotify(struct ZbZclClusterT *clusterPtr, + struct ZbApsAddrT *dst, struct ZbZclPowerProfSvrProfileRsp *notify, + void (*callback)(ZbApsdeDataConfT *conf, void *arg), void *arg); + +/* ZCL_PWR_PROF_SVR_PROFILE_RSP */ +enum ZclStatusCodeT ZbZclPowerProfServerProfileRsp(struct ZbZclClusterT *clusterPtr, + struct ZbZclAddrInfoT *dst, struct ZbZclPowerProfSvrProfileRsp *rsp, + void (*callback)(ZbApsdeDataConfT *conf, void *arg), void *arg); + +/* ZCL_PWR_PROF_SVR_STATE_RSP */ +enum ZclStatusCodeT ZbZclPowerProfServerStateRsp(struct ZbZclClusterT *clusterPtr, + struct ZbZclAddrInfoT *dst, struct ZbZclPowerProfSvrStateRsp *rsp, + void (*callback)(ZbApsdeDataConfT *conf, void *arg), void *arg); + +/* ZCL_PWR_PROF_SVR_GET_PRICE */ +enum ZclStatusCodeT ZbZclPowerProfServerGetPriceReq(struct ZbZclClusterT *clusterPtr, + struct ZbZclPowerProfCliProfileReq *req, const struct ZbApsAddrT *dst, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +/* ZCL_PWR_PROF_SVR_STATE_NOTIFY */ +enum ZclStatusCodeT ZbZclPowerProfServerStateNotify(struct ZbZclClusterT *clusterPtr, + struct ZbApsAddrT *dst, struct ZbZclPowerProfSvrStateRsp *notify, + void (*callback)(ZbApsdeDataConfT *conf, void *arg), void *arg); + +/* ZCL_PWR_PROF_SVR_GET_SCHED_PRICE */ +enum ZclStatusCodeT ZbZclPowerProfServerGetSchedPriceReq(struct ZbZclClusterT *clusterPtr, + const struct ZbApsAddrT *dst, void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +/* ZCL_PWR_PROF_SVR_PHASES_REQ */ +enum ZclStatusCodeT ZbZclPowerProfServerPhasesReq(struct ZbZclClusterT *clusterPtr, + struct ZbZclPowerProfCliProfileReq *req, const struct ZbApsAddrT *dst, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +/* ZCL_PWR_PROF_SVR_PHASES_RSP */ +enum ZclStatusCodeT ZbZclPowerProfServerPhasesRsp(struct ZbZclClusterT *clusterPtr, + struct ZbZclAddrInfoT *dst, struct ZbZclPowerProfSvrPhasesRsp *rsp, + void (*callback)(ZbApsdeDataConfT *conf, void *arg), void *arg); + +/* ZCL_PWR_PROF_SVR_PHASES_NOTIFY */ +enum ZclStatusCodeT ZbZclPowerProfServerPhasesNotify(struct ZbZclClusterT *clusterPtr, + struct ZbApsAddrT *dst, struct ZbZclPowerProfSvrPhasesRsp *notify, + void (*callback)(ZbApsdeDataConfT *conf, void *arg), void *arg); + +/* ZCL_PWR_PROF_SVR_CONSTRAINTS_NOTIFY */ +enum ZclStatusCodeT ZbZclPowerProfServerConstraintsNotify(struct ZbZclClusterT *clusterPtr, + struct ZbApsAddrT *dst, struct ZbZclPowerProfSvrConstraintsNotify *notify, + void (*callback)(ZbApsdeDataConfT *conf, void *arg), void *arg); + +/* ZCL_PWR_PROF_SVR_CONSTRAINTS_RSP */ +enum ZclStatusCodeT ZbZclPowerProfServerConstraintsRsp(struct ZbZclClusterT *clusterPtr, + struct ZbZclAddrInfoT *dst, struct ZbZclPowerProfSvrConstraintsNotify *rsp, + void (*callback)(ZbApsdeDataConfT *conf, void *arg), void *arg); + +/* ZCL_PWR_PROF_SVR_GET_PRICE_EXT */ +enum ZclStatusCodeT ZbZclPowerProfServerGetPriceReqExtReq(struct ZbZclClusterT *clusterPtr, + struct ZbZclPowerProfSvrGetPriceExtReq *req, const struct ZbApsAddrT *dst, + void (*callback)(struct ZbZclCommandRspT *rsp, void *arg), void *arg); + +#endif /* ZCL_PWR_PROF_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.press.meas.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.press.meas.h new file mode 100644 index 000000000..29f3b585c --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.press.meas.h @@ -0,0 +1,44 @@ +/* Copyright [2019 - 2019] Exegin Technologies Limited. All rights reserved. */ + +#ifndef ZCL_PRESS_MEAS_H +#define ZCL_PRESS_MEAS_H + +#include "zcl/zcl.h" + +/*-------------------------------------------------------------------------- + * DESCRIPTION + * Interface definition for the ZCL Pressure Measurement cluster. + *-------------------------------------------------------------------------- + */ + +/* Attribute Identifiers */ +enum { + ZCL_PRESS_MEAS_ATTR_MEAS_VAL = 0x0000, + ZCL_PRESS_MEAS_ATTR_MIN_MEAS_VAL = 0x0001, + ZCL_PRESS_MEAS_ATTR_MAX_MEAS_VAL = 0x0002, + ZCL_PRESS_MEAS_ATTR_TOLERANCE = 0x0003, + ZCL_PRESS_MEAS_ATTR_SCALED_VAL = 0x0010, + ZCL_PRESS_MEAS_ATTR_MIN_SCALED_VAL = 0x0011, + ZCL_PRESS_MEAS_ATTR_MAX_SCALED_VAL = 0x0012, + ZCL_PRESS_MEAS_ATTR_SCALED_TOL = 0x0013, + ZCL_PRESS_MEAS_ATTR_SCALE = 0x0014 +}; + +/* Pressure Measurement Defines */ +#define ZCL_PRESS_MEAS_UNKNOWN (int16_t)0x8000 +#define ZCL_PRESS_MEAS_MEAS_VAL_DEFAULT (int16_t)0xffff +#define ZCL_PRESS_MEAS_MIN_VAL_MIN (int16_t)0x8001 +#define ZCL_PRESS_MEAS_MIN_VAL_MAX (int16_t)0x7ffe +#define ZCL_PRESS_MEAS_MAX_VAL_MIN (int16_t)0x8002 +#define ZCL_PRESS_MEAS_MAX_VAL_MAX (int16_t)0x7fff +#define ZCL_PRESS_MEAS_SCALE_MIN (int8_t)0x81 +#define ZCL_PRESS_MEAS_SCALE_MAX (int8_t)0x7f + +/*--------------------------------------------------------------- + * Pressure Measurement Cluster Definitions + *--------------------------------------------------------------- + */ +struct ZbZclClusterT * ZbZclPressMeasClientAlloc(struct ZigBeeT *zb, uint8_t endpoint); +struct ZbZclClusterT * ZbZclPressMeasServerAlloc(struct ZigBeeT *zb, uint8_t endpoint, int16_t min, int16_t max); + +#endif /* __ZCL_PRESS_MEAS_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.temp.meas.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.temp.meas.h new file mode 100644 index 000000000..ac61eca88 --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.temp.meas.h @@ -0,0 +1,64 @@ +/* Copyright [2009 - 2019] Exegin Technologies Limited. All rights reserved. */ + +#ifndef ZCL_MEASURE_H +# define ZCL_MEASURE_H + +/*-------------------------------------------------------------------------- + * DESCRIPTION + * Interface definition for the ZCL Temperature Measurement cluster. + *-------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------- + * Temperature Measurement Cluster Definitions + *--------------------------------------------------------------- + */ +/* Temperature Measurement Information Attribute Set */ + +/* PICS.ZCL.TemperatureMeasurement + * TM.S | True + * TM.C | True + * + * Server Attributes + * TM.S.A0000 | True + * TM.S.A0000.Report.Tx | True + * TM.S.A0001 | True + * TM.S.A0002 | True + * TM.S.A0003 | True + * TM.S.Afffd | True + * TM.S.Afffe | False + * + * Client Attributes + * TM.C.A0000.Report.Rsp | False + * TM.C.Afffd | True + * TM.C.Afffe | False + */ + +#include "zcl/zcl.h" + +enum { + ZCL_TEMP_MEAS_ATTR_MEAS_VAL = 0x0000, /* ZCL_DATATYPE_SIGNED_16BIT */ + ZCL_TEMP_MEAS_ATTR_MIN_MEAS_VAL = 0x0001, /* ZCL_DATATYPE_SIGNED_16BIT */ + ZCL_TEMP_MEAS_ATTR_MAX_MEAS_VAL = 0x0002, /* ZCL_DATATYPE_SIGNED_16BIT */ + ZCL_TEMP_MEAS_ATTR_TOLERANCE = 0x0003 /* ZCL_DATATYPE_UNSIGNED_16BIT */ +}; + +/* Temperature Measurement Defines */ +#define ZCL_TEMP_MEAS_MEASURED_DEFAULT 0xffff +#define ZCL_TEMP_MEAS_UNKNOWN 0x8000 +#define ZCL_TEMP_MEAS_MIN_MEAS_VAL_MIN (int16_t)0x954d +#define ZCL_TEMP_MEAS_MIN_MEAS_VAL_MAX (int16_t)0x7ffe +#define ZCL_TEMP_MEAS_MAX_MEAS_VAL_MIN (int16_t)0x954e +#define ZCL_TEMP_MEAS_MAX_MEAS_VAL_MAX (int16_t)0x7fff +#define ZCL_TEMP_MEAS_TOLERANCE_MIN 0x0000 +#define ZCL_TEMP_MEAS_TOLERANCE_MAX 0x0800 + +/*--------------------------------------------------------------- + * Temperature Measurement Cluster Definitions + *--------------------------------------------------------------- + */ +struct ZbZclClusterT * ZbZclTempMeasClientAlloc(struct ZigBeeT *zb, uint8_t endpoint); +struct ZbZclClusterT * ZbZclTempMeasServerAlloc(struct ZigBeeT *zb, uint8_t endpoint, + int16_t min, int16_t max, uint16_t tolerance); + +#endif /* __ZCL_MEASURE_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.therm.ui.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.therm.ui.h new file mode 100644 index 000000000..70508cb78 --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.therm.ui.h @@ -0,0 +1,43 @@ +/* Copyright [2019 - 2019] Exegin Technologies Limited. All rights reserved. */ + +#ifndef ZCL_THERM_UI_H +#define ZCL_THERM_UI_H + +#include "zcl/zcl.h" + +/*-------------------------------------------------------------------------- + * DESCRIPTION + * Interface definition for the ZCL Thermostat UI Configuration + * cluster. + *-------------------------------------------------------------------------- + */ + +/* PICS.ZCL.Thermostat_UI_Configuration + * TSUIC.S | True + * TSUIC.C | True + * + * Server Attributes + * TSUIC.S.A0000 | True + * TSUIC.S.A0001 | True + * TSUIC.S.A0002 | False + * TSUIC.S.Afffd | True + * + * Client Attributes + * TSUIC.C.Afffd | True + */ + +/* Attribute Identifiers */ +enum { + ZCL_THERM_UI_ATTR_DISPLAY_MODE = 0x0000, + ZCL_THERM_UI_ATTR_KEYPAD_LOCKOUT = 0x0001, + ZCL_THERM_UI_ATTR_SCHEDULE_PROG_VIS = 0x0010, +}; + +/*--------------------------------------------------------------- + * Thermostat UI Config Cluster Definitions + *--------------------------------------------------------------- + */ +struct ZbZclClusterT * ZbZclThermUiClientAlloc(struct ZigBeeT *zb, uint8_t endpoint); +struct ZbZclClusterT * ZbZclThermUiServerAlloc(struct ZigBeeT *zb, uint8_t endpoint); + +#endif /* __ZCL_THERM_UI_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.time.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.time.h new file mode 100644 index 000000000..dc46cea23 --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.time.h @@ -0,0 +1,96 @@ +/* Copyright [2009 - 2019] Exegin Technologies Limited. All rights reserved. */ + +#ifndef ZCL_TIME_H +# define ZCL_TIME_H + +/*-------------------------------------------------------------------------- + * DESCRIPTION + * Interface definition for the ZCL Time cluster. + *-------------------------------------------------------------------------- + */ +/* PICS.ZCL.Time + * T.S | True + * T.C | True + * + * Server Attributes + * T.S.A0000 | True + * T.S.A0001 | True + * T.S.A0002 | True + * T.S.A0003 | True + * T.S.A0004 | True + * T.S.A0005 | True + * T.S.A0006 | True + * T.S.A0007 | True + * T.S.A0008 | True + * T.S.A0009 | True + * T.S.AFFFD | True + * + * Client Attributes + * T.C.AFFFD | True + */ + +#include "zcl/zcl.h" + +/*--------------------------------------------------------------- + * Definitions + *--------------------------------------------------------------- + */ +/* Time cluster attributes */ +enum { + ZCL_TIME_ATTR_TIME = 0x0000, + ZCL_TIME_ATTR_STATUS = 0x0001, + ZCL_TIME_ATTR_TIME_ZONE = 0x0002, + ZCL_TIME_ATTR_DST_START = 0x0003, + ZCL_TIME_ATTR_DST_END = 0x0004, + ZCL_TIME_ATTR_DST_SHIFT = 0x0005, + ZCL_TIME_ATTR_STANDARD_TIME = 0x0006, + ZCL_TIME_ATTR_LOCAL_TIME = 0x0007, + ZCL_TIME_ATTR_LAST_SET_TIME = 0x0008, + ZCL_TIME_ATTR_VALID_UNTIL_TIME = 0x0009 +}; + +/* Time status bits */ +#define ZCL_TIME_STATUS_MASTER 0x01U +#define ZCL_TIME_STATUS_SYNCHRONIZED 0x02U +#define ZCL_TIME_STATUS_ZONE_MASTER 0x04U +#define ZCL_TIME_STATUS_SUPERSEDING 0x08U + +/* ZigBee Epoch in other time formats. */ +#define ZCL_TIME_EPOCH_NTP 0xBC17C20000000000ULL +#define ZCL_TIME_EPOCH_NTP_SECONDS 0xBC17C200UL + +/* January 1, 2000, which equates to 946,684,800 seconds. */ +#define ZCL_TIME_EPOCH_UNIX 0x386D4380UL + +/*--------------------------------------------------------------- + * Time Server + *--------------------------------------------------------------- + */ +struct ZbZclTimeServerCallbacks { + uint32_t (*get_time)(struct ZbZclClusterT *clusterPtr, void *arg); + void (*set_time)(struct ZbZclClusterT *clusterPtr, uint32_t time_val, void *arg); +}; + +struct ZbZclClusterT * ZbZclTimeServerAlloc(struct ZigBeeT *zb, uint8_t endpoint, + struct ZbZclTimeServerCallbacks *callbacks, void *arg); + +/*--------------------------------------------------------------- + * Time Server Helper Functions + *--------------------------------------------------------------- + */ +/* Wrappers to read/write the server's ZCL_TIME_ATTR_STATUS attribute */ +void ZbZclTimeServerSetSynchronized(struct ZbZclClusterT *clusterPtr, bool isSynchronized); +bool ZbZclTimeServerIsSynchronized(struct ZbZclClusterT *clusterPtr); +void ZbZclTimeServerSetStatusMaster(struct ZbZclClusterT *clusterPtr, bool enable); + +/* Wrapper to get/set the current time. This is only applicable if ZbZclTimeServerAlloc() was called with use_stack_uptime=true. */ +void ZbZclTimeServerSetTime(struct ZbZclClusterT *clusterPtr, uint32_t currentTime); +uint32_t ZbZclTimeServerCurrentTime(struct ZbZclClusterT *clusterPtr); + +/*--------------------------------------------------------------- + * Time Client + *--------------------------------------------------------------- + */ +struct ZbZclClusterT * ZbZclTimeClientAlloc(struct ZigBeeT *zb, uint8_t endpoint); + +#endif /* __ZCL_TIME_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.touchlink.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.touchlink.h index 175623030..15b0005f7 100644 --- a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.touchlink.h +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zcl/zcl.touchlink.h @@ -1,10 +1,15 @@ -/* Copyright [2009 - 2019] Exegin Technologies Limited. All rights reserved. */ - -/*-------------------------------------------------------------------------- - * DESCRIPTION - * Interface definition for the ZCL Touchlink cluster. - *-------------------------------------------------------------------------- +/** + * file zcl.touchlink.h + * brief Deprecated Touchlink API - Excluded from DOxygen documentation + * author Exegin Technologies Limited + * copyright Copyright [2009 - 2019] Exegin Technologies Limited. All rights reserved. + * + * The functions in this header file are deprecated */ + +#ifndef ZCL_TOUCHLINK_H +#define ZCL_TOUCHLINK_H + /* PICS.ZCL.Touchlink * TC.S | True * TC.C | True @@ -61,13 +66,10 @@ * TC.C.C42.Tx | False */ -#ifndef ZCL_TOUCHLINK_H -# define ZCL_TOUCHLINK_H - #include "zcl/zcl.h" /* include TL utility cluster support functions. */ -/* FIXME - disabled while adding Touchlink into stack */ +/* EXEGIN - disabled while adding Touchlink into stack */ /* #define TL_UTILITY */ /* Zigbee Information Field @@ -83,43 +85,82 @@ #define ZCL_TL_ZBINFO_RESERVED 0xf8 /* Internal use flags (don't get sent over-the-air) - * FIXME - These used to be mixed with the ZCL_TL_ZBINFO_ flags, so for backward + * EXEGIN - These used to be mixed with the ZCL_TL_ZBINFO_ flags, so for backward * compatibility make sure they don't conflict. */ #define ZCL_TL_FLAGS_IS_TARGET (uint8_t)0x10 #define ZCL_TL_FLAGS_USE_PERSIST (uint8_t)0x20 #define ZCL_TL_FLAGS_FACTORY_RESET (uint8_t)0x40 -/*-------------------------------------------------------------------------- - * Warning! Deprecated API. Use ZbStartup with BDB_COMMISSION_MODE_TOUCHLINK instead. - *-------------------------------------------------------------------------- - */ -/* Deprecated! Touchlink should be started by setting the BDB_COMMISSION_MODE_TOUCHLINK +/** + * @brief Deprecated API Use ZbStartup instead + * + * Touchlink should be started by setting the BDB_COMMISSION_MODE_TOUCHLINK + * commissioning mode bit in the ZbStartupT configuration struct, filling in the + * touchlink configuration in ZbStartupT, and calling ZbStartup + * + * @deprecated Touchlink should be started by setting the BDB_COMMISSION_MODE_TOUCHLINK * commissioning mode bit in the ZbStartupT configuration struct, filling in the - * touchlink configuration in ZbStartupT, and calling ZbStartup. */ + * touchlink configuration in ZbStartupT, and calling ZbStartup + */ uint8_t ZbZclTouchlinkStart(struct ZbZclClusterT *clusterPtr, struct WpanPublicT *wpan, uint8_t flags, const void *persist_buf, unsigned int persist_len) ZB_F_DEPRECATED; -/* Deprecated! Use ZbStartup instead. */ +/** + * @brief Deprecated API Use ZbStartup instead + * + * Touchlink should be started by setting the BDB_COMMISSION_MODE_TOUCHLINK + * commissioning mode bit in the ZbStartupT configuration struct, filling in the + * touchlink configuration in ZbStartupT, and calling ZbStartup + * + * @deprecated Touchlink should be started by setting the BDB_COMMISSION_MODE_TOUCHLINK + * commissioning mode bit in the ZbStartupT configuration struct, filling in the + * touchlink configuration in ZbStartupT, and calling ZbStartup + */ uint8_t ZbZclTouchlinkScan(struct ZbZclClusterT *clusterPtr, void (*callback)(enum ZbBdbCommissioningStatusT status, void *arg), void *arg) ZB_F_DEPRECATED; -/* Deprecated! Use ZbStartup instead, with touchlink ZCL_TL_FLAGS_FACTORY_RESET flag bit set. */ +/** + * @brief Deprecated API Use ZbStartup instead + * + * Call ZbStartup touchlink ZCL_TL_FLAGS_FACTORY_RESET flag bit set + * + * @deprecated Touchlink should be started by setting the BDB_COMMISSION_MODE_TOUCHLINK + * commissioning mode bit in the ZbStartupT configuration struct, filling in the + * touchlink configuration in ZbStartupT, and calling ZbStartup + */ uint8_t ZbZclTouchlinkFactoryReset(struct ZbZclClusterT *clusterPtr, void (*callback)(enum ZbBdbCommissioningStatusT status, void *arg), void *arg) ZB_F_DEPRECATED; -/* Deprecated! Use ZbStartupTouchlinkTargetStop instead. */ +/** + * @brief Deprecated API Use ZbStartupTouchlinkTargetStop instead + * + * @deprecated After starting Touchlink using ZbStartup, use the new API + * instead of this call + */ uint8_t ZbZclTouchlinkStop(struct ZbZclClusterT *clusterPtr) ZB_F_DEPRECATED; -/* Deprecated! ZbStartup will allocate the Touchlink Server cluster if necessary. */ +/** + * @brief Deprecated do not use this API + * + * @deprecated ZbStartup will allocate the Touchlink Server cluster if necessary + */ struct ZbZclClusterT * ZbZclTouchlinkServerAlloc(struct ZigBeeT *zb, uint8_t endpoint) ZB_F_DEPRECATED; -/* Deprecated! ZbStartup will allocate the Identify Server cluster if not already - * allocated on the endpoint chosen for Touchlink. */ +/** + * @brief Deprecated do not use this API + * + * @deprecated ZbStartup will allocate the Identify Server cluster if not already + * allocated on the endpoint chosen for Touchlink + */ void ZbZclTouchlinkServerConfigIdentify(struct ZbZclClusterT *clusterPtr, struct ZbZclClusterT *identifyCluster) ZB_F_DEPRECATED; -/* Deprecated! ZbStartup will allocate the Touchlink Client cluster if necessary. */ +/** + * @brief Deprecated do not use this API + * + * @deprecated ZbStartup will allocate the Touchlink Client cluster if necessary + */ struct ZbZclClusterT * ZbZclTouchlinkClientAlloc(struct ZigBeeT *zb, uint8_t endpoint) ZB_F_DEPRECATED; -#endif /* ZCL_TOUCHLINK_H */ +#endif diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zgp/zgp.proxybasic.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zgp/zgp.proxybasic.h new file mode 100644 index 000000000..d49278db0 --- /dev/null +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zgp/zgp.proxybasic.h @@ -0,0 +1,268 @@ +/* Copyright [2009 - 2019] Exegin Technologies Limited. All rights reserved. */ + +/*-------------------------------------------------------------------------- + * DESCRIPTION + * Interface definition for the ZCL DRLC cluster. + *-------------------------------------------------------------------------- + */ +#ifndef ZGP_PROXYBASIC_H +# define ZGP_PROXYBASIC_H + +/*--------------------------------------------------------------- + * Dependencies + *--------------------------------------------------------------- + */ +#include "zigbee.h" +#include "zcl/zcl.h" + +/*--------------------------------------------------------------- + * Definitions + *--------------------------------------------------------------- + */ + +/* Maximum ZGP Message size (after fragmentation). */ +#define ZB_ZGP_ASDU_LENGTH_GREEN_POWER ZB_APS_CONST_MAX_PAYLOAD_SIZE + +/* GP Proxy Basic Commands Received */ +#define ZB_ZGP_GP_PAIRING 0x01 +#define ZB_ZGP_GP_PROXY_COMMISSIONING_MODE 0x02 +#define ZB_ZGP_GP_RESPONSE 0x06 +#define ZB_ZGP_GP_SINK_TABLE_REQUEST 0x0a +#define ZB_ZGP_GP_PROXY_TABLE_REQUEST 0x0b + +/* GP Proxy Basic Commands Sent */ +#define ZB_ZGP_GP_NOTIFICATION 0x00 +#define ZB_ZGP_GP_COMMISSIONING_NOTIFICATION 0x04 +#define ZB_ZGP_GP_SINK_TABLE_RESPONSE 0x0a +#define ZB_ZGP_GP_PROXY_TABLE_RESPONSE 0x0b + +/* Proxy Basic Client attribute identifiers */ +enum { + ZCL_PROXYBASIC_CLI_ATTR_GPP_MAX_PROXY_TABLE_ENTRIES = 0x0010, + ZCL_PROXYBASIC_CLI_ATTR_PROXY_TABLE = 0x0011, +#if 0 + ZCL_PROXYBASIC_CLI_ATTR_GPP_NOTIFICATION_RETRY_NUMBER = 0x0012, + ZCL_PROXYBASIC_CLI_ATTR_GPP_NOTIFICATION_RETRY_TIMER = 0x0013, + ZCL_PROXYBASIC_CLI_ATTR_GPP_MAX_SEARCH_COUNTER = 0x0014, + ZCL_PROXYBASIC_CLI_ATTR_GPP_BLOCKED_GPDID = 0x0015, +#endif + ZCL_PROXYBASIC_CLI_ATTR_GPP_FUNCTIONALITY = 0x0016, + ZCL_PROXYBASIC_CLI_ATTR_GPP_ACTIVE_FUNCTIONALITY = 0x0017, +#if 0 + ZCL_PROXYBASIC_CLI_ATTR_GPP_SHARED_SECURITY_KEY_TYPE = 0x0020, + ZCL_PROXYBASIC_CLI_ATTR_GPP_SHARED_SECURITY_KEY = 0x0021, +#endif + ZCL_PROXYBASIC_CLI_ATTR_GPP_LINK_KEY = 0x0022, +#if 0 + ZCL_PROXYBASIC_CLI_ATTR_GPP_CLUSTER_REVISION = 0xFFFD, +#endif +}; + +/* Each proxy SHALL be able to support per Proxy Table entry, i.e. per GPD any of the following mini-mum configurations: +(i) at least 2 entries in the Lightweight sink address list and/or Full unicast sink address list, +(ii) at least 2 entries in the Sink group list and +(iii) at least 1 entry in the Lightweight sink address list or Full unicast sink address list and at least 1 entry in the Sink group list. +*/ + +#if 0 /* EXEGIN - NOT_INCLUDED */ +#define ZB_ZGP_MAX_PROXY_TABLE_ENTRIES 5 +#define ZB_ZGP_LIGHTWEIGHT_SINK_ADDRESS_LIST_ENTRIES 2 +#define ZB_ZGP_SINK_GROUP_ENTRIES 2 +#define ZB_ZGP_FULL_UNICAST_SINK_ADDRESS_LIST_ENTRIES 2 + +typedef struct ZbZgpLightweightSinkAddressT { + uint64_t sink_ieee_addr; + uint16_t sink_nwk_addr; +} ZbZgpLightweightSinkAddressT; + +typedef struct ZbZgpSinkGroupT { + uint16_t sink_group; + uint16_t sink_alias; +} ZbZgpSinkGroupT; + +typedef struct ZbZgpProxyTableEntryT { + uint8_t in_use; + uint16_t options; // 16-bit bitmap + union { + uint32_t GPD_ID_SrcID; + uint64_t GPD_ID_IEEE; + }; /* Anonymous Union */ + /* uint32_t GPD_ID; */ // Unsigned 32-bit integer/IEEE address + uint8_t endpoint; // Unsigned 8-bit integer + uint16_t GPD_assigned_alias; // Unsigned 16-bit integer + uint8_t Security_Options; // 8-bit bitmap + uint32_t GPD_security_frame_counter; // Unsigned 32-bit Integer + uint8_t GPD_key[ZB_SEC_KEYSIZE]; // Security key + uint8_t lightweight_sink_address_list_len; + ZbZgpLightweightSinkAddressT lightweight_sink_address_list[ZB_ZGP_LIGHTWEIGHT_SINK_ADDRESS_LIST_ENTRIES]; // sequence of octets 2 entries A.3.4.2.2.2 + uint8_t sink_group_list_len; + ZbZgpSinkGroupT sink_group_list[ZB_ZGP_SINK_GROUP_ENTRIES]; // list sequence of octets 2 entries A.3.4.2.2.2 + uint8_t groupcast_radius; // Unsigned 8-bit integer + uint8_t search_counter; // Unsigned 8-bit integer + uint16_t extended_options; // 16-bit bitmap + uint8_t full_unicast_sink_address_list_len; + ZbZgpLightweightSinkAddressT full_unicast_sink_address_list[ZB_ZGP_FULL_UNICAST_SINK_ADDRESS_LIST_ENTRIES]; // sequence of octets 2 entries A.3.4.2.2.2 +} ZbZgpProxyTableEntryT; + +#endif + +/* Proxy Table in_use field states */ + +enum { + ZCL_PROXYBASIC_PT_ENTRY_FREE = 0x0000, + ZCL_PROXYBASIC_PT_ENTRY_IN_USE, + ZCL_PROXYBASIC_PT_ENTRY_IN_COMMISSIONING, +}; + +/* Proxy Table Options Bit Masks */ + +#define ZGP_PT_APPLICATIONID 0x0007 +#define ZGP_PT_APPLICATIONID_SRCID 0x0000 +#define ZGP_PT_APPLICATIONID_IEEE 0x0002 +#define ZGP_PT_ENTRYACTIVE 0x0008 +#define ZGP_PT_ENTRYVALID 0x0010 +#define ZGP_PT_SEQUENCE_NUMBER_CAPABILITIES 0x0020 +#define ZGP_PT_LIGHTWEIGHT_UNICAST_GPS 0x0040 +#define ZGP_PT_DERIVED_GROUP_GPS 0x0080 +#define ZGP_PT_COMMISSIONED_GROUP_GPS 0x0100 +#define ZGP_PT_FIRSTTOFORWARD 0x0200 +#define ZGP_PT_INRANGE 0x0400 +#define ZGP_PT_GPD_FIXED 0x0800 +#define ZGP_PT_HASALLUNICASTROUTES 0x1000 +#define ZGP_PT_ASSIGNEDALIAS 0x2000 +#define ZGP_PT_SECURITYUSE 0x4000 +#define ZGP_PT_OPTIONS_EXTENSION 0x8000 + +/* Proxy table Options_Extension Bit Mask */ + +#define ZGP_PT_FULL_UNICAST_GPS 0x0001 + +/* Proxy Table Request Options Bit Mask */ + +#define ZGP_PT_REQUEST_TYPE 0x0018 +#define ZGP_PT_REQUEST_TYPE_GPID 0x0000 +#define ZGP_PT_REQUEST_TYPE_INDEX 0x0008 + +/* Proxy Table Security Options Bit Mask */ + +#define ZGP_PT_SECURITYLEVEL 0x0003 +#define ZGP_PT_NO_SECURITY 0x0000 +#define ZGP_PT_FULL_4B_FRAME_COUNTER_AND_FULL_4B_MIC_ONLY 0x0002 +#define ZGP_PT_ENCRYPTION_AND_FULL_4B_FRAME_COUNTER_AND_FULL_4B_MIC 0x0003 +#define ZGP_PT_SECURITYKEYTYPE 0x001C +#define ZGP_PT_NO_KEY 0x0000 +#define ZGP_PT_ZIGBEE_NWK_KEY 0x0004 +#define ZGP_PT_GPD_GROUP_KEY 0x0008 +#define ZGP_PT_NWK_KEY_DERIVED_GPD_GROUP_KEY 0x000C +#define ZGP_PT_INDIVIDUAL_OUT_OF_THE_BOX_GPD_KEY 0x0010 +#define ZGP_PT_DERIVED_INDIVIDUAL_GPD_KEY 0x001C + +/* Pairing Command Options Bit Mask */ + +#define ZGP_PAIR_APPLICATIONID 0x000007 +#define ZGP_PAIR_APPLICATIONID_SRCID 0x000000 +#define ZGP_PAIR_APPLICATIONID_IEEE 0x000002 +#define ZGP_PAIR_ADD_SINK 0x000008 +#define ZGP_PAIR_REMOVE_GPD 0x000010 +#define ZGP_PAIR_COMMUNICATION_MODE 0x000060 +#define ZGP_PAIR_FULL_UNICAST_FORWARDING_OF_THE_GP_NOTIFICATION 0x000000 +#define ZGP_PAIR_GROUPCAST_FORWARDING_OF_THE_GP_NOTIFICATION_COMMAND_TO_DGROUPID 0x000020 +#define ZGP_PAIR_GROUPCAST_FORWARDING_OF_THE_GP_NOTIFICATION_COMMAND_TO_PRE_COMMISSIONED_GROUPID 0x000040 +#define ZGP_PAIR_UNICAST_FORWARDING_OF_THE_GP_NOTIFICATION_COMMAND_BY_THE_LIGHTWEIGHT_UNICAST_FUNCTIONALITY 0x000060 +#define ZGP_PAIR_GPD_FIXED 0x000080 +#define ZGP_PAIR_GPD_MAC_SEQUENCE_NUMBER_CAPABILITIES 0x000100 +#define ZGP_PAIR_SECURITYLEVEL 0x000600 +#define ZGP_PAIR_NO_SECURITY 0x000000 +#define ZGP_PAIR_DEPRECIATED_SECUIRITY_LEVEL 0x000200 +#define ZGP_PAIR_FULL_4B_FRAME_COUNTER_AND_FULL_4B_MIC_ONLY 0x000400 +#define ZGP_PAIR_ENCRYPTION_AND_FULL_4B_FRAME_COUNTER_AND_FULL_4B_MIC 0x000600 +#define ZGP_PAIR_SECURITYKEYTYPE 0x003800 +#define ZGP_PAIR_NO_KEY 0x000000 +#define ZGP_PAIR_ZIGBEE_NWK_KEY 0x000800 +#define ZGP_PAIR_GPD_GROUP_KEY 0x001000 +#define ZGP_PAIR_NWK_KEY_DERIVED_GPD_GROUP_KEY 0x001800 +#define ZGP_PAIR_INDIVIDUAL_OUT_OF_THE_BOX_GPD_KEY 0x002000 +#define ZGP_PAIR_DERIVED_INDIVIDUAL_GPD_KEY 0x003800 +#define ZGP_PAIR_GPD_SECURITY_FRAME_COUNTER_PRESENT 0x004000 +#define ZGP_PAIR_GPD_SECURITY_KEY_PRESENT 0x008000 +#define ZGP_PAIR_ASSIGNED_ALIAS_PRESENT 0x010000 +#define ZGP_PAIR_FORWARDING_RADIUS_PRESENT 0x020000 +#define ZGP_PAIR_RESERVED 0xFC0000 + +/* Proxy Commissioning Mode Options Bit Masks */ + +#define ZGP_PCOMM_ACTION 0x01 +#define ZGP_PCOMM_EXIT_MODE 0x0E +#define ZGP_PCOMM_EXIT_MODE_ON_COMMISSIONINGWINDOW_EXPIRATION 0x02 +#define ZGP_PCOMM_EXIT_MODE_ON_FIRST_PAIRING_SUCCESS 0x04 +#define ZGP_PCOMM_EXIT_MODE_ON_GP_PROXY_COMMISSIONING_MODE_EXIT 0x08 +#define ZGP_PCOMM_CHANNEL_PRESENT 0x10 +#define ZGP_PCOMM_UNICAST_COMMUNICATION 0x20 +#define ZGP_PCOMM_RESERVED 0xC0 + +/* Response Command Options Bit Masks*/ + +#define ZGP_RESPONSE_APPLICATIONID 0x0007 +#define ZGP_RESPONSE_APPLICATIONID_SRCID 0x0000 +#define ZGP_RESPONSE_APPLICATIONID_IEEE 0x0002 +#define ZGP_RESPONSE_TRANSMIT_ON_ENDPOINT_MATCH 0x0008 +#define ZGP_RESPONSE_RESERVED 0x00F0 + +/* Commissioning Notification Bit Masks */ + +#define ZGP_COMMISSIONING_NOTIFICATION_APPLICATIONID 0x0007 +#define ZGP_COMMISSIONING_NOTIFICATION_APPLICATIONID_SRCID 0x0000 +#define ZGP_COMMISSIONING_NOTIFICATION_APPLICATIONID_IEEE 0x0002 +#define ZGP_COMMISSIONING_NOTIFICATION_RXAFTERTX 0x0008 +#define ZGP_COMMISSIONING_NOTIFICATION_SECURITYLEVEL 0x0030 +#define ZGP_COMMISSIONING_NOTIFICATION_NO_SECURITY 0x0000 +#define ZGP_COMMISSIONING_NOTIFICATION_FULL_4B_FRAME_COUNTER_AND_FULL_4B_MIC_ONLY 0x0020 +#define ZGP_COMMISSIONING_NOTIFICATION_ENCRYPTION_AND_FULL_4B_FRAME_COUNTER_AND_FULL_4B_MIC 0x0030 +#define ZGP_COMMISSIONING_NOTIFICATION_SECURITYKEYTYPE 0x01C0 +#define ZGP_COMMISSIONING_NOTIFICATION_NO_KEY 0x0000 +#define ZGP_COMMISSIONING_NOTIFICATION_ZIGBEE_NWK_KEY 0x0040 +#define ZGP_COMMISSIONING_NOTIFICATION_GPD_GROUP_KEY 0x0080 +#define ZGP_COMMISSIONING_NOTIFICATION_NWK_KEY_DERIVED_GPD_GROUP_KEY 0x00C0 +#define ZGP_COMMISSIONING_NOTIFICATION_INDIVIDUAL_OUT_OF_THE_BOX_GPD_KEY 0x0100 +#define ZGP_COMMISSIONING_NOTIFICATION_DERIVED_INDIVIDUAL_GPD_KEY 0x01C0 +#define ZGP_COMMISSIONING_NOTIFICATION_SECURITY_PROCESSING_FAILED 0x0200 +#define ZGP_COMMISSIONING_NOTIFICATION_BIDIRECTIONAL_CAPABILITY 0x0400 +#define ZGP_COMMISSIONING_NOTIFICATION_PROXY_INFO_PRESENT 0x0800 + +/* Notification Bit Masks */ + +#define ZGP_NOTIFICATION_APPLICATIONID 0x0007 +#define ZGP_NOTIFICATION_APPLICATIONID_SRCID 0x0000 +#define ZGP_NOTIFICATION_APPLICATIONID_IEEE 0x0002 +#define ZGP_NOTIFICATION_ALSO_UNICAST 0x0008 +#define ZGP_NOTIFICATION_ALSO_DERIVED_GROUP 0x0010 +#define ZGP_NOTIFICATION_ALSO_COMMISSIONED_GROUP 0x0020 +#define ZGP_NOTIFICATION_SECURITYLEVEL 0x00C0 +#define ZGP_NOTIFICATION_NO_SECURITY 0x0000 +#define ZGP_NOTIFICATION_FULL_4B_FRAME_COUNTER_AND_FULL_4B_MIC_ONLY 0x0040 +#define ZGP_NOTIFICATION_ENCRYPTION_AND_FULL_4B_FRAME_COUNTER_AND_FULL_4B_MIC 0x00C0 +#define ZGP_NOTIFICATION_SECURITYKEYTYPE 0x0700 +#define ZGP_NOTIFICATION_NO_KEY 0x0000 +#define ZGP_NOTIFICATION_ZIGBEE_NWK_KEY 0x0100 +#define ZGP_NOTIFICATION_GPD_GROUP_KEY 0x0200 +#define ZGP_NOTIFICATION_NWK_KEY_DERIVED_GPD_GROUP_KEY 0x0300 +#define ZGP_NOTIFICATION_INDIVIDUAL_OUT_OF_THE_BOX_GPD_KEY 0x0400 +#define ZGP_NOTIFICATION_DERIVED_INDIVIDUAL_GPD_KEY 0x0700 +#define ZGP_NOTIFICATION_RXAFTERTX 0x0800 +#define ZGP_NOTIFICATION_GPTXQUEUEFULL 0x1000 +#define ZGP_NOTIFICATION_BIDIRECTIONAL_CAPABILITY 0x2000 +#define ZGP_NOTIFICATION_PROXY_INFO_PRESENT 0x4000 + +/* Commissioing States */ + +enum { + ZCL_PROXYBASIC_CLI_OPERATIONAL = 0x0000, + ZCL_PROXYBASIC_CLI_WAIT_FOR_CHANNEL_REQ0, + ZCL_PROXYBASIC_CLI_WAIT_FOR_CHANNEL_REQ1, + ZCL_PROXYBASIC_CLI_WAIT_FOR_COMMISSIONING0, + ZCL_PROXYBASIC_CLI_WAIT_FOR_COMMISSIONING1, + ZCL_PROXYBASIC_CLI_WAIT_FOR_SUCCESS, + ZCL_PROXYBASIC_CLI_WAIT_PAIRING, +}; + +#endif /* __ZGP_PROXYBASIC_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.aps.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.aps.h index 7f75836bd..aa47943e3 100644 --- a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.aps.h +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.aps.h @@ -259,7 +259,7 @@ enum ZbApsmeIbAttrIdT { * networkKeyUpdateMethod = 0xba * allowApplicationKeyRequests = 0xbb * allowRemoteTcPolicyChange = 0xbd */ - ZB_APS_IB_ID_TRUST_CENTER_POLICY, /* 0xad (uint32_t) */ + ZB_APS_IB_ID_TRUST_CENTER_POLICY, /* 0xad (type = uint32_t, enum ZbApsmePolicyT) */ /*** Exegin extensions (0x500 to 0x5ff reserved for custom AIBs) ***/ ZB_APS_IB_ID_SCAN_COUNT = 0x0500, /* (uint8_t) ZDO join parameter. Is not modified by ZbApsReset. */ @@ -484,7 +484,7 @@ enum ZbApsmeDeviceStatusT { ZB_APSME_DEV_HIGH_INSECURE_REJOIN = 0x07 /* HIGHSEC INSECURE REJOIN 0x07 */ }; -/* FIXME 1 - change the these values so the low nibble represents an +/* EXEGIN - change the these values so the low nibble represents an * enumeration, and the high nibble is a mask representing the key type * (e.g. global, unique, unverified, derived, etc) * @@ -879,10 +879,6 @@ bool ZbApsLinkKeyExists(struct ZigBeeT *zb, uint64_t partner); ZbApsmeKeyPairT * ZbApsLookupKey(struct ZigBeeT *zb, ZbApsmeKeyPairT *key, uint64_t addr, unsigned int *idx); -/* Required for ZDP Mgmt_Bind_rsp */ -uint8_t ZbApsBindTblNumEntries(struct ZigBeeT *zb); -unsigned int ZbApsAckWaitDuration(struct ZigBeeT *zb); - bool ZbApsAddrIsBcast(struct ZbApsAddrT *addr); bool ZbApsAddrIsLocal(struct ZigBeeT *zb, struct ZbApsAddrT *addr); diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.bdb.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.bdb.h index 4f36ac38e..53c86c761 100644 --- a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.bdb.h +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.bdb.h @@ -26,7 +26,7 @@ enum ZbBdbCommissioningStatusT { /* Bits for ZB_BDB_CommissioningMode */ #define BDB_COMMISSION_MODE_MASK 0x0FU #define BDB_COMMISSION_MODE_TOUCHLINK 0x01U -#define BDB_COMMISSION_MODE_NET_STEER 0x02U /* currently not used */ +#define BDB_COMMISSION_MODE_NET_STEER 0x02U #define BDB_COMMISSION_MODE_NET_FORM 0x04U /* Whether to form a network. Configured by ZbStartup (e.g. ZbStartTypeForm) */ #define BDB_COMMISSION_MODE_FIND_BIND 0x08U @@ -71,9 +71,14 @@ enum ZbBdbTouchlinkKeyIndexT { TOUCHLINK_KEY_INDEX_CERTIFICATION = 15 }; +/* Touchlink Steal Flags */ +#define TOUCHLINK_STEAL_START 0x01 /* Target is allowed to process a Touchlink Network Start Request */ +#define TOUCHLINK_STEAL_JOIN 0x02 /* Target is allowed to process a Touchlink Join Request */ +/* EXEGIN - Make ZB_BDB_TLDenyFactoryNew one of these flags */ + /* BDB IB attributes */ enum ZbBdbAttrIdT { - /* FIXME ? ZB_BDB_CommissioningGroupID ? = 0x1000 */ + /* EXEGIN ZB_BDB_CommissioningGroupID ? = 0x1000 */ ZB_BDB_CommissioningMode = 0x1001, /* bdbCommissioningMode - e.g. BDB_COMMISSION_MODE_MASK */ ZB_BDB_JoiningNodeEui64 = 0x1002, /* for internal use only */ ZB_BDB_JoiningNodeNewTCLinkKey = 0x1003, /* for internal use only */ @@ -122,6 +127,7 @@ enum ZbBdbAttrIdT { ZB_BDB_JoinAttemptsMax, /* 0x1118 - uint8_t - maximum number attempts to join a network. If an attempt fails, the EPID is added to a blacklist before the next attempt. */ ZB_BDB_MaxConcurrentJoiners, /* 0x1119 - uint8_t - maximum number of concurrent joiners the coordinator supports */ ZB_BDB_DisablePersistRejoin, /* 0x111a - boolean */ + ZB_BDB_ZdoBindCheckCluster, /* boolean */ /* Constants which are accessible through a BDB GET IB request. */ ZB_BDBC_MaxSameNetworkRetryAttempts = 0x1200, @@ -131,7 +137,7 @@ enum ZbBdbAttrIdT { ZB_BDBC_TLInterPANTransIdLifetime, /* seconds */ ZB_BDBC_TLMinStartupDelayTime, /* seconds */ ZB_BDBC_TLRxWindowDuration, /* seconds */ - ZB_BDBC_TLScanTimeBaseDuration /* mS */ + ZB_BDBC_TLScanTimeBaseDuration /* uint8_t - milliseconds */ }; /* BDB-GET.request */ @@ -176,11 +182,14 @@ bool ZbBdbCommissionModeBitSupported(struct ZigBeeT *zb, uint8_t new_mode_bit); enum ZbStatusCodeT ZbBdbCommissionModeBitSet(struct ZigBeeT *zb, uint8_t new_mode_bit); enum ZbStatusCodeT ZbBdbCommissionModeBitClear(struct ZigBeeT *zb, uint8_t new_mode_bit); -int ZbBdbGetEndpointStatus(struct ZigBeeT *zb, uint8_t endpoint); - enum ZbBdbCommissioningStatusT ZbBdbNwkStatusToBdbStatus(enum ZbStatusCodeT status); enum ZbStatusCodeT ZbBdbStatusToNwkStatus(enum ZbBdbCommissioningStatusT status); +/* Returns the commissioning status for the given endpoint (same for all endpoints?). + * If endpoint = ZB_ENDPOINT_BCAST, returns the status for the first endpoint found. */ +enum ZbBdbCommissioningStatusT ZbBdbGetEndpointStatus(struct ZigBeeT *zb, uint8_t endpoint); + +/* Configures the endpoint with the given commissioning status. Mostly for internal use only. */ void ZbBdbSetEndpointStatus(struct ZigBeeT *zb, enum ZbBdbCommissioningStatusT status, uint8_t endpoint); #endif /* ZIGBEE_BDB_H */ diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.h index 28dc4f2d7..fb03e19d3 100644 --- a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.h +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.h @@ -8,7 +8,7 @@ # define ZB_F_DEPRECATED __attribute__((deprecated)) #elif defined(_MSC_VER) && (_MSC_VER >= 1800) # define ZB_WARN_UNUSED -# define ZB_F_DEPRECATED __declspec(deprecated) +# define ZB_F_DEPRECATED #else # define ZB_WARN_UNUSED # define ZB_F_DEPRECATED @@ -55,6 +55,12 @@ /* A subset of WPAN_CHANNELMASK_2400MHZ (HA and SE preferred channels) */ #define ZB_CHANNELMASK_2400MHZ_HA 0x0318C800U /* Channels 11, 14, 15, 19, 20, 24, 25 */ +/* A predefined time to let the stack run in order to send a response, before + * proceeding to the next step. This is used to either prevent potential contention + * on the RF or if a packet must be sent before the stack parameters are modified + * or reset. */ +#define ZB_TIMER_DELAY_FOR_RESPONSE 200U + /* ZigBee Status Codes */ enum ZbStatusCodeT { /* General Status Codes */ @@ -276,99 +282,31 @@ typedef struct { const char *fmt, va_list argptr); } ZbInitSetLoggingT; -/*FUNCTION:------------------------------------------------------ - * NAME - * ZbInit - * - * DESC - * Allocates a new Zigbee stack instance. - * - * PARAMS - * extAddr ; The extended address for this stack instance. - * tblSizes ; defines various table sizes with the stack. - * If NULL, default values are used. - * setLogging ; calls ZbSetLogging with info provided. - * Allows debug output during ZbInit process. - * If NULL, ZbSetLogging is not called. - * - * RETURNS - * Pointer to allocated ZigBee stack instance. Used to reference the stack instance in - * many of the function calls to and from the stack. - */ +/* Allocates a new Zigbee stack instance. */ struct ZigBeeT * ZbInit(uint64_t extAddr, ZbInitTblSizesT *tblSizes, ZbInitSetLoggingT *setLogging); -/*FUNCTION:------------------------------------------------------ - * NAME - * ZbDestroy - * DESC - * Deallocates a Zigbee stack instance. - * PARAMS - * none - * RETURNS - * none - *---------------------------------------------------------------- - */ +/* Deallocates a Zigbee stack instance. */ void ZbDestroy(struct ZigBeeT *zb); -/*FUNCTION:------------------------------------------------------ - * NAME - * ZbSeedRand - * DESC - * Help seed the stack's PRNG. If the data has real entropy, set the has_entropy flag - * to true. - * PARAMS - * none - * RETURNS - * none - *---------------------------------------------------------------- - */ +/* Help seed the stack's PRNG. If the data has real entropy, set the has_entropy flag to true. */ void ZbSeedRand(struct ZigBeeT *zb, uint8_t *randBuf, unsigned int len, bool has_entropy); -/*FUNCTION:------------------------------------------------------ - * NAME - * ZbTimerWork - * DESC - * Non-blocking, must be called periodically to run the stack. Returns the length of - * time (in milliseconds) until the next scheduled timer will elapse, or zero if there - * are no scheduled timers. - * PARAMS - * none - * RETURNS - * none - *---------------------------------------------------------------- - */ +/* Called periodically to run the stack. */ void ZbTimerWork(struct ZigBeeT *zb); + +/* Returns the length of time (in milliseconds) until the next scheduled timer will elapse, + * or UINT_MAX if there are no scheduled timers. */ unsigned int ZbCheckTime(struct ZigBeeT *zb); -/*FUNCTION:------------------------------------------------------ - * NAME - * ZbWakeupCallbackConfig - * DESC - * Configure a callback to wakeup the application if there's a new stack event to - * process. Not all stack ports require this. - * PARAMS - * none - * RETURNS - * none - *---------------------------------------------------------------- - */ +/* Configure a callback to wakeup the application if there's a new stack event to + * process. Not all stack ports require this. */ void ZbWakeupCallbackConfig(struct ZigBeeT *zb, void (*wakeup_cb)(void)); -/*FUNCTION:------------------------------------------------------ - * NAME - * ZbPortStackEventFd - * DESC - * Called to get the file descriptor to be used to wake-up the stack thread that is - * calling ZbTimerWork if something in the stack needs attention. This is only required - * in multi-threaded environments. Without this event, it is possible for a user thread - * to initiate a stack function which* doesn't tickle the MAC layer, which in turn would - * wake up the stack thread. - * PARAMS - * none - * RETURNS - * none - *---------------------------------------------------------------- - */ +/* Called to get the file descriptor to be used to wake-up the stack thread that is + * calling ZbTimerWork if something in the stack needs attention. This is only required + * in multi-threaded environments. Without this event, it is possible for a user thread + * to initiate a stack function which* doesn't tickle the MAC layer, which in turn would + * wake up the stack thread. */ int ZbPortStackEventFd(struct ZigBeeT *zb); void ZbChangeExtAddr(struct ZigBeeT *zb, uint64_t extAddr); @@ -381,45 +319,14 @@ enum ZbStatusCodeT ZbLeaveWait(struct ZigBeeT *zb); /* Helper function to perform an APS and NWK reset */ void ZbReset(struct ZigBeeT *zb); -/*FUNCTION:------------------------------------------------------ - * NAME - * ZbIfAttach - * DESC - * Attaches an IEEE 802.15.4 device driver to the ZigBee stack. Uses the link pointers - * within the device structure for linking. - * PARAMS - * zb ; ZigBee stack instance pointer - * dev ; pointer to driver instance to attach. - * RETURNS - * true (1) or false (0) - */ +/* Attaches an IEEE 802.15.4 device driver to the ZigBee stack. Uses the link pointers + * within the device structure for linking. */ bool ZbIfAttach(struct ZigBeeT *zb, struct WpanPublicT *dev); -/*FUNCTION:------------------------------------------------------ - * NAME - * ZbIfDetach - * DESC - * Detaches an IEEE 802.15.4 device driver from the ZigBee stack. - * PARAMS - * zb ; ZigBee stack instance pointer - * dev ; pointer to driver instance to detach. - * RETURNS - * none - */ +/* Detaches an IEEE 802.15.4 device driver from the ZigBee stack. */ void ZbIfDetach(struct ZigBeeT *zb, struct WpanPublicT *dev); -/*FUNCTION:------------------------------------------------------ - * NAME - * ZbSetLogging - * DESC - * Specifies the level of logging to use, and a callback that outputs the log information. - * PARAMS - * zb ; ZigBee stack instance pointer - * mask ; Log mask of the debug messages you wish to receive. - * RETURNS - * none - *--------------------------------------------------------------- - */ +/* Specifies the level of logging to use, and a callback that outputs the log information. */ void ZbSetLogging(struct ZigBeeT *zb, uint32_t mask, void (*func)(struct ZigBeeT *zb, uint32_t mask, const char *hdr, const char *fmt, va_list argptr)); @@ -430,6 +337,29 @@ void ZbGetLogging(struct ZigBeeT *zb, uint32_t *mask, * ZCL Basic Server API *--------------------------------------------------------------- */ +/* Basic Cluster maximum string lengths. */ +#define ZCL_BASIC_MANUFACTURER_NAME_LENGTH 32U +#define ZCL_BASIC_MODEL_IDENTIFIER_LENGTH 32U +#define ZCL_BASIC_DATE_CODE_LENGTH 16U +#define ZCL_BASIC_LOCATION_DESC_LENGTH 16U +#define ZCL_BASIC_SW_BUILD_ID_LENGTH 16U + +/** + * Basic Server Attribute Defaults (ZCL data format). + */ +struct ZbZclBasicServerDefaults { + uint8_t app_version; /**< ZCL_BASIC_ATTR_APP_VERSION */ + uint8_t stack_version; /**< ZCL_BASIC_ATTR_STACK_VERSION */ + uint8_t hw_version; /**< ZCL_BASIC_ATTR_HARDWARE_VERSION */ + uint8_t mfr_name[ZCL_BASIC_MANUFACTURER_NAME_LENGTH + 1U]; /**< ZCL_BASIC_ATTR_MFR_NAME (First byte length) */ + uint8_t model_name[ZCL_BASIC_MODEL_IDENTIFIER_LENGTH + 1U]; /**< ZCL_BASIC_ATTR_MODEL_NAME (First byte length) */ + uint8_t date_code[ZCL_BASIC_DATE_CODE_LENGTH + 1U]; /**< ZCL_BASIC_ATTR_DATE_CODE (First byte length) */ + uint8_t power_source; /**< ZCL_BASIC_ATTR_POWER_SOURCE (e.g. ZCL_BASIC_POWER_UNKNOWN) */ + uint8_t sw_build_id[ZCL_BASIC_SW_BUILD_ID_LENGTH + 1U]; /**< ZCL_BASIC_ATTR_SW_BUILD_ID (First byte length) */ +}; + +void ZbZclBasicServerConfigDefaults(struct ZigBeeT *zb, const struct ZbZclBasicServerDefaults *defaults); + /* Controls whether the Basic Server is allowed to process the ZCL_BASIC_RESET_FACTORY command. */ void ZbZclBasicServerResetCmdConfig(struct ZigBeeT *zb, bool allow_reset); /* Write to the local attributes (e.g. ZCL_BASIC_ATTR_MFR_NAME) */ @@ -478,7 +408,9 @@ unsigned int ZbTimerRemaining(struct ZbTimerT *timer); #define ZB_MSG_FILTER_APSDE_DATA_IND 0x00001000U /* APSDE-DATA.indication (ZbApsdeDataIndT) */ /* Startup Indications */ #define ZB_MSG_FILTER_STARTUP_IND 0x00002000U /* (struct ZbMsgStartupInd) */ -/* Note, max filter bit we can specify here is 0x00008000U */ +/* Reset to Factory Defaults (e.g. Basic Server ZCL_BASIC_RESET_FACTORY command) */ +#define ZB_MSG_FILTER_FACTORY_RESET 0x00004000U +/* Note, max filter bit we can specify here is 0x00080000U */ /* Groups of messages that are filterable. */ #define ZB_MSG_FILTER_NLME \ @@ -494,12 +426,14 @@ unsigned int ZbTimerRemaining(struct ZbTimerT *timer); #define ZB_MSG_DEFAULT_PRIO 64 /* default application priority */ /* Message filter return values. */ -#define ZB_MSG_CONTINUE 0 /* Continue processing any further filter callbacks. */ -#define ZB_MSG_DISCARD 1 /* Stop processing further filter callbacks. */ +enum zb_msg_filter_rc { + ZB_MSG_CONTINUE = 0, /* Continue processing any further filter callbacks. */ + ZB_MSG_DISCARD /* Stop processing further filter callbacks. */ +}; struct ZbApsFilterT; struct ZbMsgFilterT * ZbMsgFilterRegister(struct ZigBeeT *zb, uint32_t mask, uint8_t prio, - int (*callback)(struct ZigBeeT *zb, uint32_t id, void *msg, void *cbarg), void *arg); + enum zb_msg_filter_rc (*callback)(struct ZigBeeT *zb, uint32_t id, void *msg, void *cbarg), void *arg); void ZbMsgFilterRemove(struct ZigBeeT *zb, struct ZbMsgFilterT *filter); struct ZbMsgStartupInd { @@ -517,19 +451,7 @@ bool ZbPersistNotifyRegister(struct ZigBeeT *zb, void (*callback)(struct ZigBeeT * ZED Shutdown *--------------------------------------------------------- */ -/*FUNCTION:------------------------------------------------------ - * NAME - * ZbShutdown - * DESC - * This API moves the stack to shutdown mode, used in case of - * a sleepy end device to conserve power. - * PARAMS - * zb ; ZigBee stack instance pointer - * mask ; Log mask of the debug messages you wish to receive. - * RETURNS - * none - *--------------------------------------------------------------- - */ +/* This API moves the stack to shutdown mode, used in case of a sleepy end device to conserve power. */ void ZbShutdown(struct ZigBeeT *zb); /*--------------------------------------------------------------- diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.nwk.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.nwk.h index ffe02644f..bface2329 100644 --- a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.nwk.h +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.nwk.h @@ -80,7 +80,7 @@ enum ZbNwkNibAttrIdT { * It is generally a bad idea for an application to modify the NNT directly. * Use ZbNwkNeighborClearAll to clear all entries (or all except parent, e.g. * before end-device rejoin). - * FIXME 1 - This NIB should be made read-only. */ + * EXEGIN - This NIB should be made read-only. */ ZB_NWK_NIB_ID_NeighborTable = 0x87, /* Time duration in seconds (Note, the Spec defines this as OctetDurations) */ ZB_NWK_NIB_ID_NetworkBroadcastDeliveryTime = 0x88, @@ -88,7 +88,7 @@ enum ZbNwkNibAttrIdT { ZB_NWK_NIB_ID_RouteDiscoveryRetriesPermitted = 0x8a, ZB_NWK_NIB_ID_RouteTable = 0x8b, ZB_NWK_NIB_ID_TimeStamp = 0x8c, - ZB_NWK_NIB_ID_TxTotal = 0x8d, /* FIXME - make TxTotal a per interface thing */ + ZB_NWK_NIB_ID_TxTotal = 0x8d, /* EXEGIN - make TxTotal a per interface thing */ ZB_NWK_NIB_ID_SymLink = 0x8e, ZB_NWK_NIB_ID_CapabilityInformation = 0x8f, ZB_NWK_NIB_ID_AddrAlloc = 0x90, @@ -140,7 +140,7 @@ enum ZbNwkNibAttrIdT { ZB_NWK_NIB_ID_PersistCounter, /* Persisted outgoing frame counter. */ /* R21+ attributes */ - /* FIXME 2 - The following NIBs should have IDs from 0xaa to 0xad, but + /* EXEGIN - The following NIBs should have IDs from 0xaa to 0xad, but * these are already being used by APS security. I think the only place * this would be a problem is the Gateway API which has a single generic * GET/SET API, which means attribute IDs must be unique and not overlap. */ @@ -152,8 +152,8 @@ enum ZbNwkNibAttrIdT { ZB_NWK_NIB_ID_DisablePeriodicTimers, /* If set, NWK layer disables edka & link power timers. Default is 0 (enabled). */ /* R22+ attributes */ - /* FIXME 2 - nwkIeeeAddress (should be 0xae, but already being used by APS security) */ - /* FIXME 2 - nwkMacInterfaceTable (should be 0xaf, but already being used by APS security) */ + /* EXEGIN - nwkIeeeAddress (should be 0xae, but already being used by APS security) */ + /* EXEGIN - nwkMacInterfaceTable (should be 0xaf, but already being used by APS security) */ ZB_NWK_NIB_ID_TxPowerMgmtSupported, /* not affected by nwk_reset_nib, keeps value. */ ZB_NWK_NIB_ID_LinkPowerDeltaPeriod, @@ -200,6 +200,7 @@ enum ZbNwkRejoinTypeT { #define ZB_NWK_CONST_MAC_FRAME_OVERHEAD 0x0bU /* See D.4 of 053474r17. */ /* The following are added by Exegin */ #define ZB_NWK_CONST_SECURITY_OVERHEAD (14U + ZB_SEC_MIC_LENGTH_5) +/* 127 - 8 - 11 = 108 bytes */ #define ZB_NWK_CONST_MAX_PAYLOAD_SIZE (WPAN_CONST_MAX_PHY_PACKET_SIZE - ZB_NWK_CONST_MIN_HEADER_OVERHEAD - ZB_NWK_CONST_MAC_FRAME_OVERHEAD) #define ZB_NWK_BCNPAYLOAD_MIN_SIZE 15U @@ -299,6 +300,8 @@ enum ZbNwkNeighborRelT { #define ZB_NWK_PARENT_INFO_POWER_NEGOT 0x0004U /* Power Negotiation Supported (R22: Link Power Delta) */ /* Exegin add-on to track the status of parent info */ #define ZB_NWK_PARENT_INFO_START 0x0100U +/* Exegin add-on to track a manual EDKA request. */ +#define ZB_NWK_PARENT_INFO_MANUAL_EDKA_REQ 0x0200U #define ZB_NWK_NEIGHBOR_TIMEOUT_SECONDS(_x_) ((_x_ != 0U) ? ((ZbUptimeT)60U << (_x_)) : (ZbUptimeT)10U) #define ZB_NWK_NEIGHBOR_TIMEOUT_MAX 14U @@ -311,7 +314,7 @@ typedef struct { uint16_t nwkAddr; /* Set to ZB_NWK_ADDR_UNDEFINED to invalidate entry */ uint8_t capability; enum ZbNwkNeighborTypeT deviceType; - bool rxOnWhenIdle; /* FIXME 1 - why not just use capability? */ + bool rxOnWhenIdle; /* EXEGIN - why not just use capability? */ enum ZbNwkNeighborRelT relationship; uint8_t txFailure; uint8_t lqi; /* Average LQI. */ @@ -362,7 +365,7 @@ typedef struct { uint8_t nsduLength; uint32_t handle; uint8_t radius; - uint8_t discoverRoute; + bool discoverRoute; bool security; /* Alias */ bool useAlias; @@ -641,13 +644,15 @@ typedef struct { struct ZbChannelListT supportedChannels; bool routersAllowed; bool powerNegotSupported; + /* Exegin add-on */ + struct WpanPublicT *mac; } ZbNlmeGetInterfaceConfT; /* Broadcast transaction table entry */ typedef struct { uint16_t srcAddr; uint8_t seqnum; - /* FIXME 1 - replace pAckCount with a list of router neighbors */ + /* EXEGIN - replace pAckCount with a list of router neighbors */ uint8_t pAckCount; /* passive ack count for flood limiting. */ ZbUptimeT expireTime; /* expiration time relative to ZbUptime. */ } ZbNwkBttEntryT; diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.security.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.security.h index 766663d8d..4f746c5dc 100644 --- a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.security.h +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.security.h @@ -74,7 +74,7 @@ extern const uint8_t sec_key_touchlink_cert[ZB_SEC_KEYSIZE]; #define ZB_SEC_LEVEL_ENC_MIC128 (uint8_t)(ZB_SEC_LEVEL_ENC | ZB_SEC_LEVEL_MIC128) /* Macro checks security level if encryption is enabled */ -#define ZB_SEC_ENCRYPTED(level) (level & ZB_SEC_LEVEL_ENC) +#define ZB_SEC_ENCRYPTED(level) ((level & ZB_SEC_LEVEL_ENC) != 0U) /* Macro returns the length of the MIC, can be computed * as 4bytes * Floor((2 ^ (level - 1))), or: @@ -117,7 +117,7 @@ enum ZbSecHdrKeyIdT { }; /* Maximum value for a frame counter. */ -#define ZB_SEC_MAX_FRAME_COUNTER 0xffffffffUL +#define ZB_SEC_MAX_FRAME_COUNTER 0xffffffffU /* Frame Counter Resets are controlled much like a lollipop counter, and require * the 'new' value to be near zero to guard against replay attacks. */ @@ -137,13 +137,15 @@ enum ZbSecKeyTypeT { * Flags to indicate encryption used. Loosely based on enum ZbSecKeyTypeT. *--------------------------------------------------------------- */ +#define ZB_SEC_ENCRYPT_TYPE_LINK_FLAG 0x80U + enum ZbSecEncryptT { /* No encryption used */ ZB_SEC_ENCRYPT_TYPE_NONE = 0x00, /* Encrypted with standard network key */ ZB_SEC_ENCRYPT_TYPE_STANDARD_NWK = 0x01, /* Link keys */ - ZB_SEC_ENCRYPT_TYPE_LINK_FLAG = 0x80, + /* ZB_SEC_ENCRYPT_TYPE_LINK_FLAG = ZB_SEC_ENCRYPT_TYPE_LINK_FLAG, */ /* Application link key */ ZB_SEC_ENCRYPT_TYPE_APP_LINK = 0x83, /* ZB_SEC_ENCRYPT_TYPE_LINK_FLAG | 0x03U */ /* Trust-Center link key */ @@ -260,44 +262,11 @@ void ZbSecMakeNonce(uint8_t *nonce, uint64_t extAddr, uint32_t frameCounter, uin void ZbAesMmoHash(uint8_t const *data, const unsigned int length, uint8_t *hash); void ZbSecKeyTransform(uint8_t *key, uint8_t input, uint8_t *keyOut); -/*FUNCTION:------------------------------------------------------------------- - * NAME - * ZbSecInstallCodeCreate - * DESCRIPTION - * Produces an install code with CRC. - * PARAMETERS - * zb ; ZigBee stack structure. - * inputCode ; Pointer to original code without a CRC, or NULL - * to generate a random code. - * outputCode ; Pointer to buffer to contain install code and CRC - * codeLen ; Length of the output code in bytes, including CRC. - * If an inputCode is provided, codeLen is the length - * of inputCode plus 2 for the CRC. - * Valid lengths: - * 8 (48-bit) - * 10 (64-bit) - * 14 (96-bit) - * 18 (128-bit) - * RETURNS - * true on success, false otherwise. - *---------------------------------------------------------------------------- - */ +/* Produces an install code with CRC. */ bool ZbSecInstallCodeCreate(struct ZigBeeT *zb, const void *inputCode, void *outputCode, unsigned int codeLen); -/*FUNCTION:------------------------------------------------------------------- - * NAME - * ZbSecInstallCodeCheck - * DESCRIPTION - * Performs redundancy checks on a ZSE installation code and - * optionally converts the code into an application link key. - * PARAMETERS - * installCode ; Pointer to installation code (includes CRC) - * codeLen ; Length of the installation code (in bytes). - * keyOut ; Output link key (if NULL will not compute) - * RETURNS - * TRUE if the IC is consistent, FALSE otherwise. - *---------------------------------------------------------------------------- - */ +/* Performs redundancy checks on a ZSE installation code and optionally converts the code + * into an application link key. */ bool ZbSecInstallCodeCheck(const void *installCode, unsigned int codeLen, void *keyOut); /* Computes the 2-byte CRC of the input Install Code */ @@ -321,7 +290,8 @@ enum ZbSecEcdsaSigType { enum ZbStatusCodeT ZbSecEcdsaValidate(struct ZigBeeT *zb, enum ZbSecEcdsaSigType sig_type, const uint8_t *ca_pub_key_array, unsigned int ca_pub_key_len, - const uint8_t *certificate, const uint8_t *signature, uint8_t *image_digest, uint8_t *cert_digest); + const uint8_t *certificate, const uint8_t *signature, + const uint8_t *image_digest, const uint8_t *cert_digest); /*--------------------------------------------------------------- * Misc. Helper Functions diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.startup.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.startup.h index e00e62927..25d38c990 100644 --- a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.startup.h +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.startup.h @@ -11,7 +11,9 @@ enum ZbStartType { ZbStartTypeForm = 0x01, ZbStartTypeRejoin = 0x02, ZbStartTypeJoin = 0x03, - /* Exegin add-on */ + /* Exegin add-ons (Internal use only) */ + ZbStartTypeTouchlink = 0xfd, + ZbStartTypeFindBind = 0xfe, ZbStartTypeNone = 0xff }; @@ -118,39 +120,6 @@ struct ZbStartupT { } touchlink; }; -/*FUNCTION:------------------------------------------------------ - * NAME ZbStartup - * DESC - * PARAMS zb ; ZigBee stack instance. - * config ; If not NULL, the configuration to set to the stack - * before forming or joining the network. - * Warning: if not NULL, any configuration to the stack - * prior to calling this function will be lost. Once this - * function is finished, you may continue configuring the - * stack (e.g. adding application link keys). - * func ; The callback function when startup is finished. - * arg ; Argument to pass to func. - * RETURNS none - * - *FUNCTION:------------------------------------------------------ - * NAME ZbStartupWait - * DESC Blocking version of ZbStartup. Calls ZbStartup. - * PARAMS See ZbStartup. - * RETURNS ZigBee status byte. - * - *FUNCTION:------------------------------------------------------ - * NAME ZbStartupPersist - * DESC Start the stack using persistent settings. - * PARAMS zb ; - * pdata ; Persistent data as returned by ZbPersistGet(). - * This function calls ZbPersistSet() and performs - * NWK-RESET.request with warm-start set. - * plen ; Length of persistent data. - * RETURNS ZigBee status byte. - * - *--------------------------------------------------------------- - */ - /* Non-blocking startup function */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbStartup(struct ZigBeeT *zb, struct ZbStartupT *configPtr, void (*callback)(enum ZbStatusCodeT status, void *cb_arg), void *arg); @@ -160,9 +129,14 @@ enum ZbStatusCodeT ZbStartupWait(struct ZigBeeT *zb, struct ZbStartupT *config); /* If Touchlink Target was started with ZbStartup, this API can be used to stop it. */ enum ZbStatusCodeT ZbStartupTouchlinkTargetStop(struct ZigBeeT *zb); -/* Manually start Finding & Binding. F&B is also started automatically after - * joining the network. */ -enum ZbStatusCodeT ZB_WARN_UNUSED ZbStartupFindBindStart(struct ZigBeeT *zb, void (*callback)(enum ZbStatusCodeT status, void *arg), void *arg); +/* Manually start Finding & Binding. F&B is also started automatically after joining + * the network. */ +enum ZbStatusCodeT ZB_WARN_UNUSED ZbStartupFindBindStart(struct ZigBeeT *zb, + void (*callback)(enum ZbStatusCodeT status, void *arg), void *arg); + +/* Same as ZbStartupFindBindStart, but only for a single endpoint. */ +enum ZbStatusCodeT ZB_WARN_UNUSED ZbStartupFindBindStartEndpoint(struct ZigBeeT *zb, uint8_t endpoint, + void (*callback)(enum ZbStatusCodeT status, void *arg), void *arg); /* ZbStartupRejoin is a wrapper for ZbNlmeJoinReq(ZB_NWK_REJOIN_TYPE_NWKREJOIN). * Use ZbStartupRejoin instead, because the internal startup handler will restart diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.zdo.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.zdo.h index 4eb0c5648..0a5360666 100644 --- a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.zdo.h +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.zdo.h @@ -26,7 +26,7 @@ enum ZbZdoAddrReqTypeT { #define ZB_ZDP_NWK_UPDATE_MANAGER_PARAMETERS 0xffU /* Maximum Response Sizes */ -/* FIXME 1 (sal) was 64, but end up allocating too much on the stack */ +/* EXEGIN (sal) was 64, but end up allocating too much on the stack */ #define ZB_ZDO_CLUSTER_LIST_MAX_SZ 16U #define ZB_ZDO_NETWORK_LIST_MAX_SZ 8U #define ZB_ZDO_NEIGHBOR_LIST_MAX_SZ 4U @@ -281,7 +281,7 @@ typedef struct { /* Routing Descriptor */ typedef struct { uint16_t destAddr; - uint8_t status; /* FIXME - convert to an enum type? */ + uint8_t status; /* EXEGIN - convert to an enum type? */ uint8_t constrained; uint8_t manyToOne; uint8_t recordRequired; @@ -575,86 +575,38 @@ struct ZbZdoNwkIeeeJoinListRspT { * ZDO *--------------------------------------------------------------- */ +/* Get the next ZDO sequence number */ +uint8_t ZbZdoGetNextSeqNum(struct ZigBeeT *zb); -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoNwkAddrWait - * DESC NWK_addr_req - * PARAMS - * RETURNS none - */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoNwkAddrReq(struct ZigBeeT *zb, ZbZdoNwkAddrReqT *req, void (*callback)(ZbZdoNwkAddrRspT *rsp, void *cb_arg), void *arg); void ZbZdoNwkAddrWait(struct ZigBeeT *zb, ZbZdoNwkAddrReqT *req, ZbZdoNwkAddrRspT *rsp); -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoIeeeAddrWait - * DESC IEEE_addr_req - * PARAMS - * RETURNS none - */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoIeeeAddrReq(struct ZigBeeT *zb, ZbZdoIeeeAddrReqT *req, void (*callback)(ZbZdoIeeeAddrRspT *rsp, void *cb_arg), void *arg); void ZbZdoIeeeAddrWait(struct ZigBeeT *zb, ZbZdoIeeeAddrReqT *req, ZbZdoIeeeAddrRspT *rsp); -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoNodeDescWait - * DESC Node_Desc_req - * PARAMS - * RETURNS none - */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoNodeDescReq(struct ZigBeeT *zb, ZbZdoNodeDescReqT *req, void (*callback)(ZbZdoNodeDescRspT *rsp, void *cb_arg), void *arg); void ZbZdoNodeDescWait(struct ZigBeeT *zb, ZbZdoNodeDescReqT *req, ZbZdoNodeDescRspT *rsp); -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoPowerDescWait - * DESC Power_Desc_req - * PARAMS - * RETURNS none - */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoPowerDescReq(struct ZigBeeT *zb, ZbZdoPowerDescReqT *req, void (*callback)(ZbZdoPowerDescRspT *rsp, void *cb_arg), void *arg); void ZbZdoPowerDescWait(struct ZigBeeT *zb, ZbZdoPowerDescReqT *req, ZbZdoPowerDescRspT *rsp); -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoSimpleDescWait - * DESC Simple_Desc_req - * PARAMS - * RETURNS none - */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoSimpleDescReq(struct ZigBeeT *zb, ZbZdoSimpleDescReqT *req, void (*callback)(ZbZdoSimpleDescRspT *rsp, void *cb_arg), void *arg); void ZbZdoSimpleDescWait(struct ZigBeeT *zb, ZbZdoSimpleDescReqT *req, ZbZdoSimpleDescRspT *rsp); -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoActiveEpWait - * DESC Active_EP_req - * PARAMS - * RETURNS none - */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoActiveEpReq(struct ZigBeeT *zb, ZbZdoActiveEpReqT *req, void (*callback)(ZbZdoActiveEpRspT *rsp, void *cb_arg), void *arg); void ZbZdoActiveEpWait(struct ZigBeeT *zb, ZbZdoActiveEpReqT *req, ZbZdoActiveEpRspT *rsp); -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoMatchDescReq - * DESC Active_EP_req - * PARAMS - * RETURNS none - */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoMatchDescReq(struct ZigBeeT *zb, ZbZdoMatchDescReqT *req, void (*callback)(ZbZdoMatchDescRspT *rsp, void *cb_arg), void *arg); void ZbZdoMatchDescWait(struct ZigBeeT *zb, ZbZdoMatchDescReqT *req, ZbZdoMatchDescRspT *rsp); - -/** - * ZbZdoMatchDescMulti: +/* ZbZdoMatchDescMulti: * Returns ZB_ZDP_STATUS_SUCCESS for received responses. * Returns ZB_ZDP_STATUS_TABLE_FULL if there's a problem starting the request. - * Returns ZB_ZDP_STATUS_TIMEOUT when the stack decides to stop receiving responses. - **/ + * Returns ZB_ZDP_STATUS_TIMEOUT when the stack decides to stop receiving responses. */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoMatchDescMulti(struct ZigBeeT *zb, ZbZdoMatchDescReqT *req, void (*callback)(ZbZdoMatchDescRspT *rsp, void *cb_arg), void *arg); -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoDeviceAnnce - * DESC Device_annce - * PARAMS - * RETURNS none - */ void ZbZdoDeviceAnnce(struct ZigBeeT *zb, ZbZdoDeviceAnnceT *deviceAnncePtr); void ZbZdoDeviceAnnceAlias(struct ZigBeeT *zb, ZbZdoDeviceAnnceT *deviceAnncePtr); +int ZbZdoParseDeviceAnnce(ZbZdoDeviceAnnceT *structPtr, const uint8_t *buf, unsigned int len); /* API to register a filter in the ZDO for the application to * receive Device_Annce messages. */ @@ -667,22 +619,9 @@ void ZbZdoDeviceAnnceFilterRemove(struct ZigBeeT *zb, struct ZbZdoDeviceAnnceFil * ZDP Binding Requests *--------------------------------------------------------------- */ - -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoBindWait - * DESC Bind_req - * PARAMS - * RETURNS none - */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoBindReq(struct ZigBeeT *zb, ZbZdoBindReqT *req, void (*callback)(ZbZdoBindRspT *rsp, void *cb_arg), void *arg); void ZbZdoBindWait(struct ZigBeeT *zb, ZbZdoBindReqT *req, ZbZdoBindRspT *rsp); -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoUnbindWait - * DESC Unbind_req - * PARAMS - * RETURNS none - */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoUnbindReq(struct ZigBeeT *zb, ZbZdoBindReqT *req, void (*callback)(ZbZdoBindRspT *rsp, void *cb_arg), void *arg); void ZbZdoUnbindWait(struct ZigBeeT *zb, ZbZdoBindReqT *req, ZbZdoBindRspT *rsp); @@ -690,51 +629,19 @@ void ZbZdoUnbindWait(struct ZigBeeT *zb, ZbZdoBindReqT *req, ZbZdoBindRspT *rsp) * ZDP Management Requests *--------------------------------------------------------------- */ -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoLqiWait - * DESC Mgmt_Lqi_req - * PARAMS - * RETURNS none - */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoLqiReq(struct ZigBeeT *zb, ZbZdoLqiReqT *req, void (*callback)(ZbZdoLqiRspT *rsp, void *cb_arg), void *arg); void ZbZdoLqiWait(struct ZigBeeT *zb, ZbZdoLqiReqT *req, ZbZdoLqiRspT *rsp); -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoRtgWait - * DESC Mgmt_Rtg_req - * PARAMS - * RETURNS none - */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoRtgReq(struct ZigBeeT *zb, ZbZdoRtgReqT *req, void (*callback)(ZbZdoRtgRspT *rsp, void *cb_arg), void *arg); void ZbZdoRtgWait(struct ZigBeeT *zb, ZbZdoRtgReqT *req, ZbZdoRtgRspT *rsp); -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoMgmtBindWait - * DESC Mgmt_Bind_req - * PARAMS - * RETURNS none - */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoMgmtBindReq(struct ZigBeeT *zb, ZbZdoMgmtBindReqT *req, void (*callback)(ZbZdoMgmtBindRspT *rsp, void *cb_arg), void *arg); void ZbZdoMgmtBindWait(struct ZigBeeT *zb, ZbZdoMgmtBindReqT *req, ZbZdoMgmtBindRspT *rsp); -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoPermitJoinWait - * DESC Mgmt_Permit_Join_req - * If sent to broadcast, then doesn't wait for responses, and - * will return the status from the APSDE-DATA.confirm. - * PARAMS - * RETURNS none - */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoPermitJoinReq(struct ZigBeeT *zb, ZbZdoPermitJoinReqT *req, void (*callback)(ZbZdoPermitJoinRspT *rsp, void *cb_arg), void *arg); void ZbZdoPermitJoinWait(struct ZigBeeT *zb, ZbZdoPermitJoinReqT *req, ZbZdoPermitJoinRspT *rsp); -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoNwkUpdateWait - * DESC Mgmt_Nwk_Update_req - * PARAMS - * RETURNS none - */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoNwkUpdateReq(struct ZigBeeT *zb, ZbZdoNwkUpdateReqT *req, void (*callback)(ZbZdoNwkUpdateNotifyT *reqPtr, void *cb_arg), void *arg); void ZbZdoNwkUpdateWait(struct ZigBeeT *zb, ZbZdoNwkUpdateReqT *req, ZbZdoNwkUpdateNotifyT *rsp); @@ -742,20 +649,8 @@ void ZbZdoNwkUpdateWait(struct ZigBeeT *zb, ZbZdoNwkUpdateReqT *req, ZbZdoNwkUpd enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoNwkEnhUpdateReq(struct ZigBeeT *zb, struct ZbZdoNwkEnhUpdateReqT *req, void (*callback)(ZbZdoNwkUpdateNotifyT *reqPtr, void *cb_arg), void *arg); -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoNwkUpdateNotify - * DESC Mgmt_Nwk_Update_notify - * PARAMS - * RETURNS none - */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoNwkUpdateNotify(struct ZigBeeT *zb, ZbZdoNwkUpdateNotifyT *reqPtr); -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoMgmtLeaveWait - * DESC Mgmt_Nwk_Leave_req - * PARAMS - * RETURNS none - */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoLeaveReq(struct ZigBeeT *zb, ZbZdoLeaveReqT *req, void (*callback)(ZbZdoLeaveRspT *rsp, void *cb_arg), void *arg); void ZbZdoLeaveWait(struct ZigBeeT *zb, ZbZdoLeaveReqT *req, ZbZdoLeaveRspT *rsp); @@ -764,50 +659,14 @@ void ZbZdoLeaveWait(struct ZigBeeT *zb, ZbZdoLeaveReqT *req, ZbZdoLeaveRspT *rsp * Receive incoming ZDO messages *--------------------------------------------------------------- */ - -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoSetPreHandler - * DESC Configures the callback to receive incoming ZDO messages - * in your application. - * PARAMS zb ; ZigBee stack instance. - * func ; The callback function. - * RETURNS none - * - *FUNCTION:------------------------------------------------------ - * NAME ZbZdoPreHandlerFuncT func - * DESC The callback that's called for an incoming ZDO message. - * PARAMS zb ; ZigBee stack instance. - * dataIndPtr ; APS-DATA.indication - * seqnum ; ZDO message sequence number - * RETURNS true (1) if the application has handled it and the stack - * should not process the message further. - * FALSE (0) if the application has not handled the message or - * wants to let the stack finish whatever processing it needs - * to do. - * Typically, the callback should return 0 to let the stack - * perform its own processing on the message. - *--------------------------------------------------------------- - */ +/* Configures the callback to receive incoming ZDO messages in your application. */ typedef int (*ZbZdoPreHandlerFuncT)(struct ZigBeeT *zb, ZbApsdeDataIndT *dataIndPtr, uint8_t seqnum); void ZbZdoSetPreHandler(struct ZigBeeT *zb, ZbZdoPreHandlerFuncT func); /*--------------------------------------------------------------- - * Misc. Helper Functions + * Complex Descriptor *--------------------------------------------------------------- */ -uint8_t ZbZdoGetNextSeqNum(struct ZigBeeT *zb); - -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoParseDeviceAnnce - * DESC Parses a Device_annce message. - * PARAMS structPtr ; Pointer to structure to fill in. - * buf ; e.g. dataIndPtr->asdu - * len ; e.g. dataIndPtr->asduLength - * RETURNS # of bytes parsed, or <0 on error. - *--------------------------------------------------------------- - */ -int ZbZdoParseDeviceAnnce(ZbZdoDeviceAnnceT *structPtr, const uint8_t *buf, unsigned int len); - /* Internal complex descriptor format */ typedef struct { char manufacturerName[16]; @@ -815,17 +674,12 @@ typedef struct { char serialNumber[16]; } ZbZdoComplexDescT; -/*FUNCTION:------------------------------------------------------ - * NAME ZbZdoSetComplexDesc - * DESC Configures the local complex descriptor. The information from - * the structPtr parameter is copied to the stack instance. - * PARAMS zb ; ZigBee stack instance. - * structPtr ; Pointer to complex descriptor structure to copy. - * RETURNS ZDP Status Code (success == 0x00) - *--------------------------------------------------------------- - */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoSetComplexDesc(struct ZigBeeT *zb, ZbZdoComplexDescT *structPtr); +/*--------------------------------------------------------------- + * IEEE Joining List + *--------------------------------------------------------------- + */ enum ZbStatusCodeT ZB_WARN_UNUSED ZbZdoNwkIeeeJoinListReq(struct ZigBeeT *zb, struct ZbZdoNwkIeeeJoinListReqT *req, void (*callback)(struct ZbZdoNwkIeeeJoinListRspT *rsp, void *cb_arg), void *arg); unsigned int ZbZdoNwkIeeeJoinListRsp(struct ZigBeeT *zb, uint16_t dstNwkAddr, diff --git a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.zgp.h b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.zgp.h index 05c6675de..e5a01a09c 100644 --- a/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.zgp.h +++ b/Middlewares/ST/STM32_WPAN/zigbee/stack/include/zigbee.zgp.h @@ -228,7 +228,7 @@ int ZbZgpDecryptKey(struct ZigBeeT *zb, uint8_t appId, uint64_t gpdId, void *key uint8_t ZbZgpAddKey(struct ZigBeeT *zb, uint8_t applicationId, uint64_t gpdId, uint8_t endpoint, uint8_t level, uint8_t keytype, const void *key); -#if 0 /* FIXME - NOT_INCLUDED */ +#if 0 /* EXEGIN - NOT_INCLUDED */ void ZbZgpRecvDataInd(ZbApsdeDataIndT *dataIndPtr, void *arg); bool ZbZgpHandleUnsolicited(struct ZbZgpT *zgp, ZbApsdeDataIndT *dataIndPtr, uint8_t seqnum); void ZbZgpHandleUnsupported(struct ZigBeeT *zb, ZbApsdeDataIndT *ind, uint8_t seqnum); diff --git a/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_dma_rtos_template.c b/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_dma_rtos_template.c deleted file mode 100644 index 5628db4f3..000000000 --- a/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_dma_rtos_template.c +++ /dev/null @@ -1,484 +0,0 @@ - /** - ****************************************************************************** - * @file sd_diskio_dma_rtos_template.c - * @author MCD Application Team - * @brief SD Disk I/O DMA with RTOS driver template. This file needs to be - copied at user project alongside the respective header file. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -**/ -/* Includes ------------------------------------------------------------------*/ -#include "ff_gen_drv.h" -#include "sd_diskio_dma_rtos.h" - -#include -#include - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define QUEUE_SIZE (uint32_t) 10 -#define READ_CPLT_MSG (uint32_t) 1 -#define WRITE_CPLT_MSG (uint32_t) 2 -/* -================================================================== -enable the defines below to send custom rtos messages -when an error or an abort occurs. -Notice: depending on the HAL/SD driver the HAL_SD_ErrorCallback() -may not be available. -See BSP_SD_ErrorCallback() and BSP_SD_AbortCallback() below -================================================================== - -#define RW_ERROR_MSG (uint32_t) 3 -#define RW_ABORT_MSG (uint32_t) 4 -*/ -/* -* the following Timeout is useful to give the control back to the applications -* in case of errors in either BSP_SD_ReadCpltCallback() or BSP_SD_WriteCpltCallback() -* the value by default is as defined in the BSP platform driver otherwise 30 secs -* -*/ - -#define SD_TIMEOUT 30 * 1000 - -#define SD_DEFAULT_BLOCK_SIZE 512 - -/* -* Depending on the usecase, the SD card initialization could be done at the -* application level, if it is the case define the flag below to disable -* the BSP_SD_Init() call in the SD_Initialize(). -*/ - -//#define DISABLE_SD_INIT - - -/* -* when using cachable memory region, it may be needed to maintain the cache -* validity. Enable the define below to activate a cache maintenance at each -* read and write operation. -* Notice: This is applicable only for cortex M7 based platform. -*/ - -/* #define ENABLE_SD_DMA_CACHE_MAINTENANCE 1 */ - - -/* -* Some DMA requires 4-Byte aligned address buffer to correctly read/wite data, -* in FatFs some accesses aren't thus we need a 4-byte aligned scratch buffer to correctly -* transfer data -*/ -#define ENABLE_SCRATCH_BUFFER - -/* Private variables ---------------------------------------------------------*/ -#if defined(ENABLE_SCRATCH_BUFFER) -#if defined (ENABLE_SD_DMA_CACHE_MAINTENANCE) -ALIGN_32BYTES(static uint8_t scratch[BLOCKSIZE]); // 32-Byte aligned for cache maintenance -#else -__ALIGN_BEGIN static uint8_t scratch[BLOCKSIZE] __ALIGN_END; -#endif -#endif -/* Disk status */ -static volatile DSTATUS Stat = STA_NOINIT; -static osMessageQId SDQueueID; -/* Private function prototypes -----------------------------------------------*/ -static DSTATUS SD_CheckStatus(BYTE lun); -DSTATUS SD_initialize (BYTE); -DSTATUS SD_status (BYTE); -DRESULT SD_read (BYTE, BYTE*, DWORD, UINT); -#if _USE_WRITE == 1 -DRESULT SD_write (BYTE, const BYTE*, DWORD, UINT); -#endif /* _USE_WRITE == 1 */ -#if _USE_IOCTL == 1 -DRESULT SD_ioctl (BYTE, BYTE, void*); -#endif /* _USE_IOCTL == 1 */ - -const Diskio_drvTypeDef SD_Driver = -{ - SD_initialize, - SD_status, - SD_read, -#if _USE_WRITE == 1 - SD_write, -#endif /* _USE_WRITE == 1 */ - -#if _USE_IOCTL == 1 - SD_ioctl, -#endif /* _USE_IOCTL == 1 */ -}; - -/* Private functions ---------------------------------------------------------*/ - -static int SD_CheckStatusWithTimeout(uint32_t timeout) -{ - uint32_t timer = osKernelSysTick(); - /* block until SDIO peripherial is ready again or a timeout occur */ - while( osKernelSysTick() - timer < timeout) - { - if (BSP_SD_GetCardState() == SD_TRANSFER_OK) - { - return 0; - } - } - - return -1; -} - -static DSTATUS SD_CheckStatus(BYTE lun) -{ - Stat = STA_NOINIT; - - if(BSP_SD_GetCardState() == SD_TRANSFER_OK) - { - Stat &= ~STA_NOINIT; - } - - return Stat; -} - -/** -* @brief Initializes a Drive -* @param lun : not used -* @retval DSTATUS: Operation status -*/ -DSTATUS SD_initialize(BYTE lun) -{ - Stat = STA_NOINIT; - /* - * check that the kernel has been started before continuing - * as the osMessage API will fail otherwise - */ - if(osKernelRunning()) - { -#if !defined(DISABLE_SD_INIT) - - if(BSP_SD_Init() == MSD_OK) - { - Stat = SD_CheckStatus(lun); - } - -#else - Stat = SD_CheckStatus(lun); -#endif - - /* - * if the SD is correctly initialized, create the operation queue - * if not already created - */ - - if ((Stat != STA_NOINIT) && (SDQueueID == NULL)) - { - osMessageQDef(SD_Queue, QUEUE_SIZE, uint16_t); - SDQueueID = osMessageCreate (osMessageQ(SD_Queue), NULL); - } - } - - return Stat; -} - -/** -* @brief Gets Disk Status -* @param lun : not used -* @retval DSTATUS: Operation status -*/ -DSTATUS SD_status(BYTE lun) -{ - return SD_CheckStatus(lun); -} - - -/** -* @brief Reads Sector(s) -* @param lun : not used -* @param *buff: Data buffer to store read data -* @param sector: Sector address (LBA) -* @param count: Number of sectors to read (1..128) -* @retval DRESULT: Operation result -*/ -DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count) -{ - DRESULT res = RES_ERROR; - osEvent event; -#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) - uint32_t alignedAddr; -#endif - /* - * ensure the SDCard is ready for a new operation - */ - - if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0) - { - return res; - } - -#if defined(ENABLE_SCRATCH_BUFFER) - if (!((uint32_t)buff & 0x3)) - { -#endif - /* Fast path cause destination buffer is correctly aligned */ - uint8_t ret = BSP_SD_ReadBlocks_DMA((uint32_t*)buff, (uint32_t)(sector), count); - - if (ret == MSD_OK) { - /* wait for a message from the queue or a timeout */ - event = osMessageGet(SDQueueID, SD_TIMEOUT); - if (event.status == osEventMessage) { - if (event.value.v == READ_CPLT_MSG) { - res = RES_OK; -#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) - /* - * Invalidate the chache before reading into the buffer, to get actual data - */ - alignedAddr = (uint32_t)buff & ~0x1F; - SCB_InvalidateDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr)); -#endif - } - } - } -#if defined(ENABLE_SCRATCH_BUFFER) - } else { - /* Slow path, fetch each sector a part and memcpy to destination buffer */ - int i; - uint8_t ret; - for (i = 0; i < count; i++) { - ret = BSP_SD_ReadBlocks_DMA((uint32_t*)scratch, (uint32_t)sector++, 1); - if (ret == MSD_OK) { - /* wait for a message from the queue or a timeout */ - event = osMessageGet(SDQueueID, SD_TIMEOUT); - - if (event.status == osEventMessage) { - if (event.value.v == READ_CPLT_MSG) { -#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) - /* - * - * invalidate the scratch buffer before the next read to get the actual data instead of the cached one - */ - SCB_InvalidateDCache_by_Addr((uint32_t*)scratch, BLOCKSIZE); -#endif - memcpy(buff, scratch, BLOCKSIZE); - buff += BLOCKSIZE; - } - } - } - else - { - break; - } - } - - if ((i == count) && (ret == MSD_OK)) - res = RES_OK; - } - -#endif - - return res; -} - -/** -* @brief Writes Sector(s) -* @param lun : not used -* @param *buff: Data to be written -* @param sector: Sector address (LBA) -* @param count: Number of sectors to write (1..128) -* @retval DRESULT: Operation result -*/ -#if _USE_WRITE == 1 -DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count) -{ - osEvent event; - DRESULT res = RES_ERROR; - uint32_t timer; - -#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) - uint32_t alignedAddr; -#endif - - if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0) - { - return res; - } - -#if defined(ENABLE_SCRATCH_BUFFER) - if (!((uint32_t)buff & 0x3)) - { -#endif -#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) - /* - * Invalidate the chache before writting into the buffer. - * This is not needed if the memory region is configured as W/T. - */ - alignedAddr = (uint32_t)buff & ~0x1F; - SCB_InvalidateDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr)); -#endif - if(BSP_SD_WriteBlocks_DMA((uint32_t*)buff, - (uint32_t) (sector), - count) == MSD_OK) - { - /* Get the message from the queue */ - event = osMessageGet(SDQueueID, SD_TIMEOUT); - - if (event.status == osEventMessage) - { - if (event.value.v == WRITE_CPLT_MSG) - { - timer = osKernelSysTick() + SD_TIMEOUT; - /* block until SDIO IP is ready or a timeout occur */ - while(timer > osKernelSysTick()) - { - if (BSP_SD_GetCardState() == SD_TRANSFER_OK) - { - res = RES_OK; - break; - } - } - } - } - } -#if defined(ENABLE_SCRATCH_BUFFER) - } else - { - /* Slow path, fetch each sector a part and memcpy to destination buffer */ - int i; - uint8_t ret; -#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) - /* - * invalidate the scratch buffer before the next write to get the actual data instead of the cached one - */ - SCB_InvalidateDCache_by_Addr((uint32_t*)scratch, BLOCKSIZE); -#endif - - for (i = 0; i < count; i++) { - ret = BSP_SD_WriteBlocks_DMA((uint32_t*)scratch, (uint32_t)sector++, 1); - if (ret == MSD_OK) { - /* wait for a message from the queue or a timeout */ - event = osMessageGet(SDQueueID, SD_TIMEOUT); - - if (event.status == osEventMessage) { - if (event.value.v == WRITE_CPLT_MSG) { - memcpy((void *)buff, (void *)scratch, BLOCKSIZE); - buff += BLOCKSIZE; - } - } - } - else - { - break; - } - } - - if ((i == count) && (ret == MSD_OK)) - res = RES_OK; - } -#endif - return res; -} -#endif /* _USE_WRITE == 1 */ - -/** -* @brief I/O control operation -* @param lun : not used -* @param cmd: Control code -* @param *buff: Buffer to send/receive control data -* @retval DRESULT: Operation result -*/ -#if _USE_IOCTL == 1 -DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff) -{ - DRESULT res = RES_ERROR; - BSP_SD_CardInfo CardInfo; - - if (Stat & STA_NOINIT) return RES_NOTRDY; - - switch (cmd) - { - /* Make sure that no pending write process */ - case CTRL_SYNC : - res = RES_OK; - break; - - /* Get number of sectors on the disk (DWORD) */ - case GET_SECTOR_COUNT : - BSP_SD_GetCardInfo(&CardInfo); - *(DWORD*)buff = CardInfo.LogBlockNbr; - res = RES_OK; - break; - - /* Get R/W sector size (WORD) */ - case GET_SECTOR_SIZE : - BSP_SD_GetCardInfo(&CardInfo); - *(WORD*)buff = CardInfo.LogBlockSize; - res = RES_OK; - break; - - /* Get erase block size in unit of sector (DWORD) */ - case GET_BLOCK_SIZE : - BSP_SD_GetCardInfo(&CardInfo); - *(DWORD*)buff = CardInfo.LogBlockSize / SD_DEFAULT_BLOCK_SIZE; - res = RES_OK; - break; - - default: - res = RES_PARERR; - } - - return res; -} -#endif /* _USE_IOCTL == 1 */ - - - -/** -* @brief Tx Transfer completed callbacks -* @param hsd: SD handle -* @retval None -*/ -void BSP_SD_WriteCpltCallback(void) -{ - /* - * No need to add an "osKernelRunning()" check here, as the SD_initialize() - * is always called before any SD_Read()/SD_Write() call - */ - osMessagePut(SDQueueID, WRITE_CPLT_MSG, osWaitForever); -} - -/** -* @brief Rx Transfer completed callbacks -* @param hsd: SD handle -* @retval None -*/ -void BSP_SD_ReadCpltCallback(void) -{ - /* - * No need to add an "osKernelRunning()" check here, as the SD_initialize() - * is always called before any SD_Read()/SD_Write() call - */ - osMessagePut(SDQueueID, READ_CPLT_MSG, osWaitForever); -} - -/* - ====================================================================== - enable the callbacks below to deal with Error/Abort usecases. - Depending on the HAL/SD Drvier version, the HAL_SD_ErrorCallback() may - not be available - ===================================================================== -void BSP_SD_ErrorCallback(void) -{ - BSP_ErrorHandler(); - - osMessagePut(SDQueueID, RW_ERROR_MSG, osWaitForever); -} - -void BSP_SD_AbortCallback(void) -{ - osMessagePut(SDQueueID, RW_ABORT_MSG, osWaitForever); -} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_dma_rtos_template_bspv1.c b/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_dma_rtos_template_bspv1.c new file mode 100644 index 000000000..363157b75 --- /dev/null +++ b/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_dma_rtos_template_bspv1.c @@ -0,0 +1,656 @@ +/** +****************************************************************************** +* @file sd_diskio_dma_rtos_template.c +* @author MCD Application Team +* @brief SD Disk I/O DMA with RTOS driver template. This file needs to be +copied at user project alongside the respective header file. +****************************************************************************** +* @attention +* +* Copyright (c) 2017 STMicroelectronics. All rights reserved. +* +* This software component is licensed by ST under BSD 3-Clause license, +* the "License"; You may not use this file except in compliance with the +* License. You may obtain a copy of the License at: +* opensource.org/licenses/BSD-3-Clause +* +****************************************************************************** +**/ +/* Includes ------------------------------------------------------------------*/ +#include "ff_gen_drv.h" +#include "sd_diskio_dma_rtos.h" + +#include +#include + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define QUEUE_SIZE (uint32_t) 10 +#define READ_CPLT_MSG (uint32_t) 1 +#define WRITE_CPLT_MSG (uint32_t) 2 +/* +================================================================== +enable the defines below to send custom rtos messages +when an error or an abort occurs. +Notice: depending on the HAL/SD driver the HAL_SD_ErrorCallback() +may not be available. +See BSP_SD_ErrorCallback() and BSP_SD_AbortCallback() below +================================================================== + +#define RW_ERROR_MSG (uint32_t) 3 +#define RW_ABORT_MSG (uint32_t) 4 +*/ +/* +* the following Timeout is useful to give the control back to the applications +* in case of errors in either BSP_SD_ReadCpltCallback() or BSP_SD_WriteCpltCallback() +* the value by default is as defined in the BSP platform driver otherwise 30 secs +* +*/ + +#define SD_TIMEOUT 30 * 1000 + +#define SD_DEFAULT_BLOCK_SIZE 512 + +/* +* Depending on the usecase, the SD card initialization could be done at the +* application level, if it is the case define the flag below to disable +* the BSP_SD_Init() call in the SD_Initialize(). +*/ + +#define DISABLE_SD_INIT + + +/* +* when using cachable memory region, it may be needed to maintain the cache +* validity. Enable the define below to activate a cache maintenance at each +* read and write operation. +* Notice: This is applicable only for cortex M7 based platform. +*/ + +/* #define ENABLE_SD_DMA_CACHE_MAINTENANCE 1 */ + +/* +* Some DMA requires 4-Byte aligned address buffer to correctly read/wite data, +* in FatFs some accesses aren't thus we need a 4-byte aligned scratch buffer to correctly +* transfer data +*/ +/* #define ENABLE_SCRATCH_BUFFER */ + +/* Private variables ---------------------------------------------------------*/ +#if defined(ENABLE_SCRATCH_BUFFER) +#if defined (ENABLE_SD_DMA_CACHE_MAINTENANCE) +ALIGN_32BYTES(static uint8_t scratch[BLOCKSIZE]); // 32-Byte aligned for cache maintenance +#else +__ALIGN_BEGIN static uint8_t scratch[BLOCKSIZE] __ALIGN_END; +#endif +#endif +/* Disk status */ +static volatile DSTATUS Stat = STA_NOINIT; +#if (osCMSIS <= 0x20000U) +static osMessageQId SDQueueID = NULL; +#else +static osMessageQueueId_t SDQueueID = NULL; +#endif +/* Private function prototypes -----------------------------------------------*/ +static DSTATUS SD_CheckStatus(BYTE lun); +DSTATUS SD_initialize (BYTE); +DSTATUS SD_status (BYTE); +DRESULT SD_read (BYTE, BYTE*, DWORD, UINT); +#if _USE_WRITE == 1 +DRESULT SD_write (BYTE, const BYTE*, DWORD, UINT); +#endif /* _USE_WRITE == 1 */ +#if _USE_IOCTL == 1 +DRESULT SD_ioctl (BYTE, BYTE, void*); +#endif /* _USE_IOCTL == 1 */ + +const Diskio_drvTypeDef SD_Driver = +{ + SD_initialize, + SD_status, + SD_read, +#if _USE_WRITE == 1 + SD_write, +#endif /* _USE_WRITE == 1 */ + +#if _USE_IOCTL == 1 + SD_ioctl, +#endif /* _USE_IOCTL == 1 */ +}; + +/* Private functions ---------------------------------------------------------*/ + +static int SD_CheckStatusWithTimeout(uint32_t timeout) +{ + uint32_t timer; + /* block until SDIO peripherial is ready again or a timeout occur */ +#if (osCMSIS <= 0x20000U) + timer = osKernelSysTick(); + while( osKernelSysTick() - timer < timeout) +#else + timer = osKernelGetTickCount(); + while( osKernelGetTickCount() - timer < timeout) +#endif + { + if (BSP_SD_GetCardState() == SD_TRANSFER_OK) + { + return 0; + } + } + + return -1; +} + +static DSTATUS SD_CheckStatus(BYTE lun) +{ + Stat = STA_NOINIT; + + if(BSP_SD_GetCardState() == SD_TRANSFER_OK) + { + Stat &= ~STA_NOINIT; + } + + return Stat; +} + +/** +* @brief Initializes a Drive +* @param lun : not used +* @retval DSTATUS: Operation status +*/ +DSTATUS SD_initialize(BYTE lun) +{ + Stat = STA_NOINIT; + /* + * check that the kernel has been started before continuing + * as the osMessage API will fail otherwise + */ +#if (osCMSIS <= 0x20000U) + if(osKernelRunning()) +#else + if(osKernelGetState() == osKernelRunning) +#endif + { +#if !defined(DISABLE_SD_INIT) + + if(BSP_SD_Init() == MSD_OK) + { + Stat = SD_CheckStatus(lun); + } + +#else + Stat = SD_CheckStatus(lun); +#endif + + /* + * if the SD is correctly initialized, create the operation queue + * if not already created + */ + + if (Stat != STA_NOINIT) + { + if (SDQueueID == NULL) + { +#if (osCMSIS <= 0x20000U) + osMessageQDef(SD_Queue, QUEUE_SIZE, uint16_t); + SDQueueID = osMessageCreate (osMessageQ(SD_Queue), NULL); +#else + SDQueueID = osMessageQueueNew(QUEUE_SIZE, 2, NULL); +#endif + } + + if (SDQueueID == NULL) + { + Stat |= STA_NOINIT; + } + } + } + + return Stat; +} + +/** +* @brief Gets Disk Status +* @param lun : not used +* @retval DSTATUS: Operation status +*/ +DSTATUS SD_status(BYTE lun) +{ + return SD_CheckStatus(lun); +} + + +/** +* @brief Reads Sector(s) +* @param lun : not used +* @param *buff: Data buffer to store read data +* @param sector: Sector address (LBA) +* @param count: Number of sectors to read (1..128) +* @retval DRESULT: Operation result +*/ +DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count) +{ + DRESULT res = RES_ERROR; + uint32_t timer; +#if (osCMSIS < 0x20000U) + osEvent event; +#else + uint16_t event; + osStatus_t status; +#endif +#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) + uint32_t alignedAddr; +#endif + /* + * ensure the SDCard is ready for a new operation + */ + + if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0) + { + return res; + } + +#if defined(ENABLE_SCRATCH_BUFFER) + if (!((uint32_t)buff & 0x3)) + { +#endif + /* Fast path cause destination buffer is correctly aligned */ + uint8_t ret = BSP_SD_ReadBlocks_DMA((uint32_t*)buff, (uint32_t)(sector), count); + + if (ret == MSD_OK) { +#if (osCMSIS < 0x20000U) + /* wait for a message from the queue or a timeout */ + event = osMessageGet(SDQueueID, SD_TIMEOUT); + + if (event.status == osEventMessage) + { + if (event.value.v == READ_CPLT_MSG) + { + timer = osKernelSysTick(); + /* block until SDIO IP is ready or a timeout occur */ + while(osKernelSysTick() - timer + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define QUEUE_SIZE (uint32_t) 10 +#define READ_CPLT_MSG (uint32_t) 1 +#define WRITE_CPLT_MSG (uint32_t) 2 +#define RW_ABORT_MSG (uint32_t) 3 +/* + * the following Timeout is useful to give the control back to the applications + * in case of errors in either BSP_SD_ReadCpltCallback() or BSP_SD_WriteCpltCallback() + * the value by default is as defined in the BSP platform driver otherwise 30 secs + * + */ + +#define SD_TIMEOUT 30 * 1000 + +#define SD_DEFAULT_BLOCK_SIZE 512 + +#ifndef BSP_SD_INSTANCE +#define BSP_SD_INSTANCE 0 +#endif + +/* + * Depending on the usecase, the SD card initialization could be done at the + * application level, if it is the case define the flag below to disable + * the BSP_SD_Init() call in the SD_Initialize(). + */ + +#define DISABLE_SD_INIT + + +/* + * when using cachable memory region, it may be needed to maintain the cache + * validity. Enable the define below to activate a cache maintenance at each + * read and write operation. + * Notice: This is applicable only for cortex M7 based platform. + */ + +/* #define ENABLE_SD_DMA_CACHE_MAINTENANCE 1 */ + +/* +* Some DMA requires 4-Byte aligned address buffer to correctly read/wite data, +* in FatFs some accesses aren't thus we need a 4-byte aligned scratch buffer to correctly +* transfer data +*/ +/* #define ENABLE_SCRATCH_BUFFER */ + +/* Private variables ---------------------------------------------------------*/ + +#if defined(ENABLE_SCRATCH_BUFFER) +#if defined (ENABLE_SD_DMA_CACHE_MAINTENANCE) +ALIGN_32BYTES(static uint8_t scratch[BLOCKSIZE]); // 32-Byte aligned for cache maintenance +#else +__ALIGN_BEGIN static uint8_t scratch[BLOCKSIZE] __ALIGN_END; +#endif +#endif + +/* Disk status */ +static volatile DSTATUS Stat = STA_NOINIT; +#if (osCMSIS <= 0x20000U) +static osMessageQId SDQueueID = NULL; +#else +static osMessageQueueId_t SDQueueID = NULL; +#endif +/* Private function prototypes -----------------------------------------------*/ +static DSTATUS SD_CheckStatus(BYTE lun); +DSTATUS SD_initialize (BYTE); +DSTATUS SD_status (BYTE); +DRESULT SD_read (BYTE, BYTE*, DWORD, UINT); +#if _USE_WRITE == 1 + DRESULT SD_write (BYTE, const BYTE*, DWORD, UINT); +#endif /* _USE_WRITE == 1 */ +#if _USE_IOCTL == 1 + DRESULT SD_ioctl (BYTE, BYTE, void*); +#endif /* _USE_IOCTL == 1 */ + +const Diskio_drvTypeDef SD_Driver = +{ + SD_initialize, + SD_status, + SD_read, +#if _USE_WRITE == 1 + SD_write, +#endif /* _USE_WRITE == 1 */ + +#if _USE_IOCTL == 1 + SD_ioctl, +#endif /* _USE_IOCTL == 1 */ +}; + +/* Private functions ---------------------------------------------------------*/ + +/* Private functions ---------------------------------------------------------*/ +static int SD_CheckStatusWithTimeout(uint32_t timeout) +{ + uint32_t timer; +#if (osCMSIS < 0x20000U) + timer = osKernelSysTick(); + /* block until SDIO IP is ready or a timeout occur */ + while(osKernelSysTick() - timer -#include "ff_gen_drv.h" -#include "sd_diskio_dma.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* -* the following Timeout is useful to give the control back to the applications -* in case of errors in either BSP_SD_ReadCpltCallback() or BSP_SD_WriteCpltCallback() -* the value by default is as defined in the BSP platform driver otherwise 30 secs -*/ - -#define SD_TIMEOUT 30 * 1000 - -#define SD_DEFAULT_BLOCK_SIZE 512 - -/* -* Depending on the usecase, the SD card initialization could be done at the -* application level, if it is the case define the flag below to disable -* the BSP_SD_Init() call in the SD_Initialize(). -*/ - -/* #define DISABLE_SD_INIT */ - -/* -* when using cachable memory region, it may be needed to maintain the cache -* validity. Enable the define below to activate a cache maintenance at each -* read and write operation. -* Notice: This is applicable only for cortex M7 based platform. -*/ - -/* #define ENABLE_SD_DMA_CACHE_MAINTENANCE 1 */ - -/* -* Some DMA requires 4-Byte aligned address buffer to correctly read/wite data, -* in FatFs some accesses aren't thus we need a 4-byte aligned scratch buffer to correctly -* transfer data -*/ -#define ENABLE_SCRATCH_BUFFER - - -/* Private variables ---------------------------------------------------------*/ - -#if defined(ENABLE_SCRATCH_BUFFER) -#if defined (ENABLE_SD_DMA_CACHE_MAINTENANCE) -ALIGN_32BYTES(static uint8_t scratch[BLOCKSIZE]); // 32-Byte aligned for cache maintenance -#else -__ALIGN_BEGIN static uint8_t scratch[BLOCKSIZE] __ALIGN_END; -#endif -#endif - -/* Disk status */ -static volatile DSTATUS Stat = STA_NOINIT; -static volatile UINT WriteStatus = 0, ReadStatus = 0; -/* Private function prototypes -----------------------------------------------*/ -static DSTATUS SD_CheckStatus(BYTE lun); -DSTATUS SD_initialize (BYTE); -DSTATUS SD_status (BYTE); -DRESULT SD_read (BYTE, BYTE*, DWORD, UINT); -#if _USE_WRITE == 1 -DRESULT SD_write (BYTE, const BYTE*, DWORD, UINT); -#endif /* _USE_WRITE == 1 */ -#if _USE_IOCTL == 1 -DRESULT SD_ioctl (BYTE, BYTE, void*); -#endif /* _USE_IOCTL == 1 */ - -const Diskio_drvTypeDef SD_Driver = -{ - SD_initialize, - SD_status, - SD_read, -#if _USE_WRITE == 1 - SD_write, -#endif /* _USE_WRITE == 1 */ - -#if _USE_IOCTL == 1 - SD_ioctl, -#endif /* _USE_IOCTL == 1 */ -}; - -/* Private functions ---------------------------------------------------------*/ -static int SD_CheckStatusWithTimeout(uint32_t timeout) -{ - uint32_t timer = HAL_GetTick(); - /* block until SDIO IP is ready again or a timeout occur */ - while(HAL_GetTick() - timer < timeout) - { - if (BSP_SD_GetCardState() == SD_TRANSFER_OK) - { - return 0; - } - } - - return -1; -} - -static DSTATUS SD_CheckStatus(BYTE lun) -{ - Stat = STA_NOINIT; - - if(BSP_SD_GetCardState() == MSD_OK) - { - Stat &= ~STA_NOINIT; - } - - return Stat; -} - -/** -* @brief Initializes a Drive -* @param lun : not used -* @retval DSTATUS: Operation status -*/ -DSTATUS SD_initialize(BYTE lun) -{ -#if !defined(DISABLE_SD_INIT) - - if(BSP_SD_Init() == MSD_OK) - { - Stat = SD_CheckStatus(lun); - } - -#else - Stat = SD_CheckStatus(lun); -#endif - return Stat; -} - -/** -* @brief Gets Disk Status -* @param lun : not used -* @retval DSTATUS: Operation status -*/ -DSTATUS SD_status(BYTE lun) -{ - return SD_CheckStatus(lun); -} - -/** -* @brief Reads Sector(s) -* @param lun : not used -* @param *buff: Data buffer to store read data -* @param sector: Sector address (LBA) -* @param count: Number of sectors to read (1..128) -* @retval DRESULT: Operation result -*/ -DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count) -{ - DRESULT res = RES_ERROR; - uint32_t timeout; - uint8_t ret; -#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) - uint32_t alignedAddr; -#endif - - /* - * ensure the SDCard is ready for a new operation - */ - - if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0) - { - return res; - } - -#if defined(ENABLE_SCRATCH_BUFFER) - if (!((uint32_t)buff & 0x3)) - { -#endif - if(BSP_SD_ReadBlocks_DMA((uint32_t*)buff, - (uint32_t) (sector), - count) == MSD_OK) - { - ReadStatus = 0; - /* Wait that the reading process is completed or a timeout occurs */ - timeout = HAL_GetTick(); - while((ReadStatus == 0) && ((HAL_GetTick() - timeout) < SD_TIMEOUT)) - { - } - /* incase of a timeout return error */ - if (ReadStatus == 0) - { - res = RES_ERROR; - } - else - { - ReadStatus = 0; - timeout = HAL_GetTick(); - - while((HAL_GetTick() - timeout) < SD_TIMEOUT) - { - if (BSP_SD_GetCardState() == SD_TRANSFER_OK) - { - res = RES_OK; -#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) - /* - the SCB_InvalidateDCache_by_Addr() requires a 32-Byte aligned address, - adjust the address and the D-Cache size to invalidate accordingly. - */ - alignedAddr = (uint32_t)buff & ~0x1F; - SCB_InvalidateDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr)); -#endif - break; - } - } - } - } -#if defined(ENABLE_SCRATCH_BUFFER) - else { - /* Slow path, fetch each sector a part and memcpy to destination buffer */ - int i; - - for (i = 0; i < count; i++) { - ret = BSP_SD_ReadBlocks_DMA((uint32_t*)scratch, (uint32_t)sector++, 1); - if (ret == MSD_OK) { - /* wait until the read is successful or a timeout occurs */ - - ReadStatus = 0; - timeout = HAL_GetTick(); - while((ReadStatus == 0) && ((HAL_GetTick() - timeout) < SD_TIMEOUT)) - { - } - if (ReadStatus == 0) - { - break; - } - - -#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) - /* - * - * invalidate the scratch buffer before the next read to get the actual data instead of the cached one - */ - SCB_InvalidateDCache_by_Addr((uint32_t*)scratch, BLOCKSIZE); -#endif - memcpy(buff, scratch, BLOCKSIZE); - buff += BLOCKSIZE; - } - else - { - break; - } - } - - if ((i == count) && (ret == MSD_OK)) - res = RES_OK; - } -#endif - } - - return res; -} -/** -* @brief Writes Sector(s) -* @param lun : not used -* @param *buff: Data to be written -* @param sector: Sector address (LBA) -* @param count: Number of sectors to write (1..128) -* @retval DRESULT: Operation result -*/ -#if _USE_WRITE == 1 -DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count) -{ - DRESULT res = RES_ERROR; - uint32_t timeout; - uint8_t ret; - int i; - - WriteStatus = 0; -#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) - uint32_t alignedAddr; -#endif - - if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0) - { - return res; - } - -#if defined(ENABLE_SCRATCH_BUFFER) - if (!((uint32_t)buff & 0x3)) - { -#endif -#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) - - /* - the SCB_CleanDCache_by_Addr() requires a 32-Byte aligned address - adjust the address and the D-Cache size to clean accordingly. - */ - alignedAddr = (uint32_t)buff & ~0x1F; - SCB_CleanDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr)); -#endif - - - if(BSP_SD_WriteBlocks_DMA((uint32_t*)buff, - (uint32_t)(sector), - count) == MSD_OK) - { - /* Wait that writing process is completed or a timeout occurs */ - - timeout = HAL_GetTick(); - while((WriteStatus == 0) && ((HAL_GetTick() - timeout) < SD_TIMEOUT)) - { - } - /* incase of a timeout return error */ - if (WriteStatus == 0) - { - res = RES_ERROR; - } - else - { - WriteStatus = 0; - timeout = HAL_GetTick(); - - while((HAL_GetTick() - timeout) < SD_TIMEOUT) - { - if (BSP_SD_GetCardState() == SD_TRANSFER_OK) - { - res = RES_OK; - break; - } - } - } - } - else - { - /* Slow path, fetch each sector a part and memcpy to destination buffer */ -#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) - /* - * invalidate the scratch buffer before the next write to get the actual data instead of the cached one - */ - SCB_InvalidateDCache_by_Addr((uint32_t*)scratch, BLOCKSIZE); -#endif - - for (i = 0; i < count; i++) - { - WriteStatus = 0; - ret = BSP_SD_WriteBlocks_DMA((uint32_t*)scratch, (uint32_t)sector++, 1); - if (ret == MSD_OK) { - /* wait for a message from the queue or a timeout */ - timeout = HAL_GetTick(); - while((WriteStatus == 0) && ((HAL_GetTick() - timeout) < SD_TIMEOUT)) - { - } - if (WriteStatus == 0) - { - break; - } - - memcpy((void *)buff, (void *)scratch, BLOCKSIZE); - buff += BLOCKSIZE; - } - else - { - break; - } - } - if ((i == count) && (ret == MSD_OK)) - res = RES_OK; - } - - } - return res; -} -#endif /* _USE_WRITE == 1 */ - -/** -* @brief I/O control operation -* @param lun : not used -* @param cmd: Control code -* @param *buff: Buffer to send/receive control data -* @retval DRESULT: Operation result -*/ -#if _USE_IOCTL == 1 -DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff) -{ - DRESULT res = RES_ERROR; - BSP_SD_CardInfo CardInfo; - - if (Stat & STA_NOINIT) return RES_NOTRDY; - - switch (cmd) - { - /* Make sure that no pending write process */ - case CTRL_SYNC : - res = RES_OK; - break; - - /* Get number of sectors on the disk (DWORD) */ - case GET_SECTOR_COUNT : - BSP_SD_GetCardInfo(&CardInfo); - *(DWORD*)buff = CardInfo.LogBlockNbr; - res = RES_OK; - break; - - /* Get R/W sector size (WORD) */ - case GET_SECTOR_SIZE : - BSP_SD_GetCardInfo(&CardInfo); - *(WORD*)buff = CardInfo.LogBlockSize; - res = RES_OK; - break; - - /* Get erase block size in unit of sector (DWORD) */ - case GET_BLOCK_SIZE : - BSP_SD_GetCardInfo(&CardInfo); - *(DWORD*)buff = CardInfo.LogBlockSize / SD_DEFAULT_BLOCK_SIZE; - res = RES_OK; - break; - - default: - res = RES_PARERR; - } - - return res; -} -#endif /* _USE_IOCTL == 1 */ - - - -/** -* @brief Tx Transfer completed callbacks -* @param hsd: SD handle -* @retval None -*/ - -/* -=============================================================================== -Select the correct function signature depending on your platform. -please refer to the file "stm32xxxx_eval_sd.h" to verify the correct function -prototype -=============================================================================== -*/ -//void BSP_SD_WriteCpltCallback(uint32_t SdCard) -void BSP_SD_WriteCpltCallback(void) -{ - WriteStatus = 1; -} - -/** -* @brief Rx Transfer completed callbacks -* @param hsd: SD handle -* @retval None -*/ - -/* -=============================================================================== -Select the correct function signature depending on your platform. -please refer to the file "stm32xxxx_eval_sd.h" to verify the correct function -prototype -=============================================================================== -*/ -//void BSP_SD_ReadCpltCallback(uint32_t SdCard) -void BSP_SD_ReadCpltCallback(void) -{ - ReadStatus = 1; -} - -/* -============================================================================================== - depending on the SD_HAL_Driver version, either the HAL_SD_ErrorCallback() or HAL_SD_AbortCallback() - or both could be defined, activate the callbacks below when suitable and needed -============================================================================================== -void BSP_SD_AbortCallback(void) -{ -} - -void BSP_SD_ErrorCallback(void) -{ -} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_dma_template_bspv1.c b/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_dma_template_bspv1.c new file mode 100644 index 000000000..e457f0872 --- /dev/null +++ b/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_dma_template_bspv1.c @@ -0,0 +1,499 @@ + /** + ****************************************************************************** + * @file sd_diskio_dma_template.c + * @author MCD Application Team + * @brief SD DMA Disk I/O template driver. This file needs to be renamed and + copied into the application project alongside the respective header + file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +**/ + +/* Includes ------------------------------------------------------------------*/ +#include +#include "ff_gen_drv.h" +#include "sd_diskio_dma.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* +* the following Timeout is useful to give the control back to the applications +* in case of errors in either BSP_SD_ReadCpltCallback() or BSP_SD_WriteCpltCallback() +* the value by default is as defined in the BSP platform driver otherwise 30 secs +*/ + +#define SD_TIMEOUT 30 * 1000 + +#define SD_DEFAULT_BLOCK_SIZE 512 + +/* +* Depending on the usecase, the SD card initialization could be done at the +* application level, if it is the case define the flag below to disable +* the BSP_SD_Init() call in the SD_Initialize(). +*/ + +/* #define DISABLE_SD_INIT */ + +/* +* when using cachable memory region, it may be needed to maintain the cache +* validity. Enable the define below to activate a cache maintenance at each +* read and write operation. +* Notice: This is applicable only for cortex M7 based platform. +*/ + +/* #define ENABLE_SD_DMA_CACHE_MAINTENANCE 1 */ + +/* +* Some DMA requires 4-Byte aligned address buffer to correctly read/wite data, +* in FatFs some accesses aren't thus we need a 4-byte aligned scratch buffer to correctly +* transfer data +*/ +/* #define ENABLE_SCRATCH_BUFFER */ + + +/* Private variables ---------------------------------------------------------*/ + +#if defined(ENABLE_SCRATCH_BUFFER) +#if defined (ENABLE_SD_DMA_CACHE_MAINTENANCE) +ALIGN_32BYTES(static uint8_t scratch[BLOCKSIZE]); // 32-Byte aligned for cache maintenance +#else +__ALIGN_BEGIN static uint8_t scratch[BLOCKSIZE] __ALIGN_END; +#endif +#endif + +/* Disk status */ +static volatile DSTATUS Stat = STA_NOINIT; +static volatile UINT WriteStatus = 0, ReadStatus = 0; +/* Private function prototypes -----------------------------------------------*/ +static DSTATUS SD_CheckStatus(BYTE lun); +DSTATUS SD_initialize (BYTE); +DSTATUS SD_status (BYTE); +DRESULT SD_read (BYTE, BYTE*, DWORD, UINT); +#if _USE_WRITE == 1 +DRESULT SD_write (BYTE, const BYTE*, DWORD, UINT); +#endif /* _USE_WRITE == 1 */ +#if _USE_IOCTL == 1 +DRESULT SD_ioctl (BYTE, BYTE, void*); +#endif /* _USE_IOCTL == 1 */ + +const Diskio_drvTypeDef SD_Driver = +{ + SD_initialize, + SD_status, + SD_read, +#if _USE_WRITE == 1 + SD_write, +#endif /* _USE_WRITE == 1 */ + +#if _USE_IOCTL == 1 + SD_ioctl, +#endif /* _USE_IOCTL == 1 */ +}; + +/* Private functions ---------------------------------------------------------*/ +static int SD_CheckStatusWithTimeout(uint32_t timeout) +{ + uint32_t timer = HAL_GetTick(); + /* block until SDIO IP is ready again or a timeout occur */ + while(HAL_GetTick() - timer < timeout) + { + if (BSP_SD_GetCardState() == SD_TRANSFER_OK) + { + return 0; + } + } + + return -1; +} + +static DSTATUS SD_CheckStatus(BYTE lun) +{ + Stat = STA_NOINIT; + + if(BSP_SD_GetCardState() == MSD_OK) + { + Stat &= ~STA_NOINIT; + } + + return Stat; +} + +/** +* @brief Initializes a Drive +* @param lun : not used +* @retval DSTATUS: Operation status +*/ +DSTATUS SD_initialize(BYTE lun) +{ +#if !defined(DISABLE_SD_INIT) + + if(BSP_SD_Init() == MSD_OK) + { + Stat = SD_CheckStatus(lun); + } + +#else + Stat = SD_CheckStatus(lun); +#endif + return Stat; +} + +/** +* @brief Gets Disk Status +* @param lun : not used +* @retval DSTATUS: Operation status +*/ +DSTATUS SD_status(BYTE lun) +{ + return SD_CheckStatus(lun); +} + +/** +* @brief Reads Sector(s) +* @param lun : not used +* @param *buff: Data buffer to store read data +* @param sector: Sector address (LBA) +* @param count: Number of sectors to read (1..128) +* @retval DRESULT: Operation result +*/ +DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count) +{ + DRESULT res = RES_ERROR; + uint32_t timeout; +#if defined(ENABLE_SCRATCH_BUFFER) + uint8_t ret; +#endif +#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) + uint32_t alignedAddr; +#endif + + /* + * ensure the SDCard is ready for a new operation + */ + + if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0) + { + return res; + } + +#if defined(ENABLE_SCRATCH_BUFFER) + if (!((uint32_t)buff & 0x3)) + { +#endif + if(BSP_SD_ReadBlocks_DMA((uint32_t*)buff, + (uint32_t) (sector), + count) == MSD_OK) + { + ReadStatus = 0; + /* Wait that the reading process is completed or a timeout occurs */ + timeout = HAL_GetTick(); + while((ReadStatus == 0) && ((HAL_GetTick() - timeout) < SD_TIMEOUT)) + { + } + /* incase of a timeout return error */ + if (ReadStatus == 0) + { + res = RES_ERROR; + } + else + { + ReadStatus = 0; + timeout = HAL_GetTick(); + + while((HAL_GetTick() - timeout) < SD_TIMEOUT) + { + if (BSP_SD_GetCardState() == SD_TRANSFER_OK) + { + res = RES_OK; +#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) + /* + the SCB_InvalidateDCache_by_Addr() requires a 32-Byte aligned address, + adjust the address and the D-Cache size to invalidate accordingly. + */ + alignedAddr = (uint32_t)buff & ~0x1F; + SCB_InvalidateDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr)); +#endif + break; + } + } + } + } +#if defined(ENABLE_SCRATCH_BUFFER) + } + else + { + /* Slow path, fetch each sector a part and memcpy to destination buffer */ + int i; + + for (i = 0; i < count; i++) { + ret = BSP_SD_ReadBlocks_DMA((uint32_t*)scratch, (uint32_t)sector++, 1); + if (ret == MSD_OK) { + /* wait until the read is successful or a timeout occurs */ + + timeout = HAL_GetTick(); + while((ReadStatus == 0) && ((HAL_GetTick() - timeout) < SD_TIMEOUT)) + { + } + if (ReadStatus == 0) + { + res = RES_ERROR; + break; + } + ReadStatus = 0; + +#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) + /* + * + * invalidate the scratch buffer before the next read to get the actual data instead of the cached one + */ + SCB_InvalidateDCache_by_Addr((uint32_t*)scratch, BLOCKSIZE); +#endif + memcpy(buff, scratch, BLOCKSIZE); + buff += BLOCKSIZE; + } + else + { + break; + } + } + + if ((i == count) && (ret == MSD_OK)) + res = RES_OK; + } +#endif + + return res; +} +/** +* @brief Writes Sector(s) +* @param lun : not used +* @param *buff: Data to be written +* @param sector: Sector address (LBA) +* @param count: Number of sectors to write (1..128) +* @retval DRESULT: Operation result +*/ +#if _USE_WRITE == 1 +DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count) +{ + DRESULT res = RES_ERROR; + uint32_t timeout; +#if defined(ENABLE_SCRATCH_BUFFER) + uint8_t ret; + int i; +#endif + + WriteStatus = 0; +#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) + uint32_t alignedAddr; +#endif + + if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0) + { + return res; + } + +#if defined(ENABLE_SCRATCH_BUFFER) + if (!((uint32_t)buff & 0x3)) + { +#endif +#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) + + /* + the SCB_CleanDCache_by_Addr() requires a 32-Byte aligned address + adjust the address and the D-Cache size to clean accordingly. + */ + alignedAddr = (uint32_t)buff & ~0x1F; + SCB_CleanDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr)); +#endif + + + if(BSP_SD_WriteBlocks_DMA((uint32_t*)buff, + (uint32_t)(sector), + count) == MSD_OK) + { + /* Wait that writing process is completed or a timeout occurs */ + + timeout = HAL_GetTick(); + while((WriteStatus == 0) && ((HAL_GetTick() - timeout) < SD_TIMEOUT)) + { + } + /* incase of a timeout return error */ + if (WriteStatus == 0) + { + res = RES_ERROR; + } + else + { + WriteStatus = 0; + timeout = HAL_GetTick(); + + while((HAL_GetTick() - timeout) < SD_TIMEOUT) + { + if (BSP_SD_GetCardState() == SD_TRANSFER_OK) + { + res = RES_OK; + break; + } + } + } + } +#if defined(ENABLE_SCRATCH_BUFFER) + } + else + { + /* Slow path, fetch each sector a part and memcpy to destination buffer */ +#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) + /* + * invalidate the scratch buffer before the next write to get the actual data instead of the cached one + */ + SCB_InvalidateDCache_by_Addr((uint32_t*)scratch, BLOCKSIZE); +#endif + + for (i = 0; i < count; i++) + { + WriteStatus = 0; + + memcpy((void *)scratch, (void *)buff, BLOCKSIZE); + buff += BLOCKSIZE; + + ret = BSP_SD_WriteBlocks_DMA((uint32_t*)scratch, (uint32_t)sector++, 1); + if (ret == MSD_OK) { + /* wait for a message from the queue or a timeout */ + timeout = HAL_GetTick(); + while((WriteStatus == 0) && ((HAL_GetTick() - timeout) < SD_TIMEOUT)) + { + } + if (WriteStatus == 0) + { + break; + } + + } + else + { + break; + } + } + if ((i == count) && (ret == MSD_OK)) + res = RES_OK; + } +#endif + return res; +} +#endif /* _USE_WRITE == 1 */ + +/** +* @brief I/O control operation +* @param lun : not used +* @param cmd: Control code +* @param *buff: Buffer to send/receive control data +* @retval DRESULT: Operation result +*/ +#if _USE_IOCTL == 1 +DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff) +{ + DRESULT res = RES_ERROR; + BSP_SD_CardInfo CardInfo; + + if (Stat & STA_NOINIT) return RES_NOTRDY; + + switch (cmd) + { + /* Make sure that no pending write process */ + case CTRL_SYNC : + res = RES_OK; + break; + + /* Get number of sectors on the disk (DWORD) */ + case GET_SECTOR_COUNT : + BSP_SD_GetCardInfo(&CardInfo); + *(DWORD*)buff = CardInfo.LogBlockNbr; + res = RES_OK; + break; + + /* Get R/W sector size (WORD) */ + case GET_SECTOR_SIZE : + BSP_SD_GetCardInfo(&CardInfo); + *(WORD*)buff = CardInfo.LogBlockSize; + res = RES_OK; + break; + + /* Get erase block size in unit of sector (DWORD) */ + case GET_BLOCK_SIZE : + BSP_SD_GetCardInfo(&CardInfo); + *(DWORD*)buff = CardInfo.LogBlockSize / SD_DEFAULT_BLOCK_SIZE; + res = RES_OK; + break; + + default: + res = RES_PARERR; + } + + return res; +} +#endif /* _USE_IOCTL == 1 */ + + + +/** +* @brief Tx Transfer completed callbacks +* @param hsd: SD handle +* @retval None +*/ + +/* +=============================================================================== +Select the correct function signature depending on your platform. +please refer to the file "stm32xxxx_eval_sd.h" to verify the correct function +prototype +=============================================================================== +*/ +//void BSP_SD_WriteCpltCallback(uint32_t SdCard) +void BSP_SD_WriteCpltCallback(void) +{ + WriteStatus = 1; +} + +/** +* @brief Rx Transfer completed callbacks +* @param hsd: SD handle +* @retval None +*/ + +/* +=============================================================================== +Select the correct function signature depending on your platform. +please refer to the file "stm32xxxx_eval_sd.h" to verify the correct function +prototype +=============================================================================== +*/ +//void BSP_SD_ReadCpltCallback(uint32_t SdCard) +void BSP_SD_ReadCpltCallback(void) +{ + ReadStatus = 1; +} + +/* +============================================================================================== + depending on the SD_HAL_Driver version, either the HAL_SD_ErrorCallback() or HAL_SD_AbortCallback() + or both could be defined, activate the callbacks below when suitable and needed +============================================================================================== +void BSP_SD_AbortCallback(void) +{ +} + +void BSP_SD_ErrorCallback(void) +{ +} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_dma_template_bspv2.c b/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_dma_template_bspv2.c new file mode 100644 index 000000000..d78a1d806 --- /dev/null +++ b/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_dma_template_bspv2.c @@ -0,0 +1,493 @@ + /** + ****************************************************************************** + * @file sd_diskio_dma_template_bspv2.c + * @author MCD Application Team + * @brief SD DMA Disk I/O template driver based on the BSP v2 API. + * This file needs to be renamed and copied into the application + * project alongside the respective header file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +**/ + +/* Includes ------------------------------------------------------------------*/ +#include +#include "ff_gen_drv.h" +#include "sd_diskio.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* +* the following Timeout is useful to give the control back to the applications +* in case of errors in either BSP_SD_ReadCpltCallback() or BSP_SD_WriteCpltCallback() +* the value by default is as defined in the BSP platform driver otherwise 30 secs +*/ + +#define SD_TIMEOUT 30 * 1000 + +#define SD_DEFAULT_BLOCK_SIZE 512 + +#ifndef BSP_SD_INSTANCE +#define BSP_SD_INSTANCE 0 +#endif + +#if BSP_SD_INSTANCE >= SD_INSTANCES_NBR +#error "Wrong BSP_SD_INSTANCE" +#endif + +/* +* Depending on the usecase, the SD card initialization could be done at the +* application level, if it is the case define the flag below to disable +* the BSP_SD_Init() call in the SD_Initialize(). +*/ + +/*#define DISABLE_SD_INIT*/ + +/* +* when using cachable memory region, it may be needed to maintain the cache +* validity. Enable the define below to activate a cache maintenance at each +* read and write operation. +* Notice: This is applicable only for cortex M7 based platform. +*/ + +/* #define ENABLE_SD_DMA_CACHE_MAINTENANCE 1 */ + +/* +* Some DMA requires 4-Byte aligned address buffer to correctly read/wite data, +* in FatFs some accesses aren't thus we need a 4-byte aligned scratch buffer to correctly +* transfer data +*/ +/* #define ENABLE_SCRATCH_BUFFER */ + + +/* Private variables ---------------------------------------------------------*/ + +#if defined(ENABLE_SCRATCH_BUFFER) +#if defined (ENABLE_SD_DMA_CACHE_MAINTENANCE) +ALIGN_32BYTES(static uint8_t scratch[BLOCKSIZE]); // 32-Byte aligned for cache maintenance +#else +__ALIGN_BEGIN static uint8_t scratch[BLOCKSIZE] __ALIGN_END; +#endif +#endif + +/* Disk status */ +static volatile DSTATUS Stat = STA_NOINIT; +static volatile UINT WriteStatus = 0, ReadStatus = 0; +/* Private function prototypes -----------------------------------------------*/ +static DSTATUS SD_CheckStatus(BYTE lun); +DSTATUS SD_initialize (BYTE); +DSTATUS SD_status (BYTE); +DRESULT SD_read (BYTE, BYTE*, DWORD, UINT); +#if _USE_WRITE == 1 +DRESULT SD_write (BYTE, const BYTE*, DWORD, UINT); +#endif /* _USE_WRITE == 1 */ +#if _USE_IOCTL == 1 +DRESULT SD_ioctl (BYTE, BYTE, void*); +#endif /* _USE_IOCTL == 1 */ + +const Diskio_drvTypeDef SD_Driver = +{ + SD_initialize, + SD_status, + SD_read, +#if _USE_WRITE == 1 + SD_write, +#endif /* _USE_WRITE == 1 */ + +#if _USE_IOCTL == 1 + SD_ioctl, +#endif /* _USE_IOCTL == 1 */ +}; + +/* Private functions ---------------------------------------------------------*/ +static int SD_CheckStatusWithTimeout(uint32_t timeout) +{ + uint32_t timer = HAL_GetTick(); + /* block until SDIO IP is ready again or a timeout occur */ + while(HAL_GetTick() - timer < timeout) + { + if (BSP_SD_GetCardState(BSP_SD_INSTANCE) == SD_TRANSFER_OK) + { + return 0; + } + } + + return -1; +} + +static DSTATUS SD_CheckStatus(BYTE lun) +{ + Stat = STA_NOINIT; + + if(BSP_SD_GetCardState(BSP_SD_INSTANCE) == SD_TRANSFER_OK) + { + Stat &= ~STA_NOINIT; + } + + return Stat; +} + +/** +* @brief Initializes a Drive +* @param lun : not used +* @retval DSTATUS: Operation status +*/ +DSTATUS SD_initialize(BYTE lun) +{ +#if !defined(DISABLE_SD_INIT) + + if(BSP_SD_Init(BSP_SD_INSTANCE) == BSP_ERROR_NONE) + { + Stat = SD_CheckStatus(lun); + } + +#else + Stat = SD_CheckStatus(lun); +#endif + return Stat; +} + +/** +* @brief Gets Disk Status +* @param lun : not used +* @retval DSTATUS: Operation status +*/ +DSTATUS SD_status(BYTE lun) +{ + return SD_CheckStatus(lun); +} + +/** +* @brief Reads Sector(s) +* @param lun : not used +* @param *buff: Data buffer to store read data +* @param sector: Sector address (LBA) +* @param count: Number of sectors to read (1..128) +* @retval DRESULT: Operation result +*/ +DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count) +{ + DRESULT res = RES_ERROR; + uint32_t timeout; +#if defined(ENABLE_SCRATCH_BUFFER) + uint8_t ret; +#endif +#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) + uint32_t alignedAddr; +#endif + + /* + * ensure the SDCard is ready for a new operation + */ + + if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0) + { + return res; + } + +#if defined(ENABLE_SCRATCH_BUFFER) + if (!((uint32_t)buff & 0x3)) + { +#endif + ReadStatus = 0; + + if(BSP_SD_ReadBlocks_DMA(BSP_SD_INSTANCE,(uint32_t*)buff, + (uint32_t)(sector), count) == BSP_ERROR_NONE) + { + /* Wait that the reading process is completed or a timeout occurs */ + timeout = HAL_GetTick(); + while((ReadStatus == 0) && ((HAL_GetTick() - timeout) < SD_TIMEOUT)) + { + } + /* incase of a timeout return error */ + if (ReadStatus == 0) + { + res = RES_ERROR; + } + else + { + ReadStatus = 0; + timeout = HAL_GetTick(); + + while((HAL_GetTick() - timeout) < SD_TIMEOUT) + { + if (BSP_SD_GetCardState(BSP_SD_INSTANCE) == SD_TRANSFER_OK) + { + res = RES_OK; +#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) + /* + the SCB_InvalidateDCache_by_Addr() requires a 32-Byte aligned address, + adjust the address and the D-Cache size to invalidate accordingly. + */ + alignedAddr = (uint32_t)buff & ~0x1F; + SCB_InvalidateDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr)); +#endif + break; + } + } + } + } +#if defined(ENABLE_SCRATCH_BUFFER) + } + else + { + /* Slow path, fetch each sector a part and memcpy to destination buffer */ + int i; + + for (i = 0; i < count; i++) { + ret = BSP_SD_ReadBlocks_DMA(BSP_SD_INSTANCE, (uint32_t*)scratch, (uint32_t)sector++, 1); + if (ret == BSP_ERROR_NONE ) { + /* wait until the read is successful or a timeout occurs */ + + timeout = HAL_GetTick(); + while((ReadStatus == 0) && ((HAL_GetTick() - timeout) < SD_TIMEOUT)) + { + } + if (ReadStatus == 0) + { + res = RES_ERROR; + break; + } + ReadStatus = 0; + +#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) + /* + * + * invalidate the scratch buffer before the next read to get the actual data instead of the cached one + */ + SCB_InvalidateDCache_by_Addr((uint32_t*)scratch, BLOCKSIZE); +#endif + memcpy(buff, scratch, BLOCKSIZE); + buff += BLOCKSIZE; + } + else + { + break; + } + } + + if ((i == count) && (ret == BSP_ERROR_NONE )) + res = RES_OK; + } +#endif + return res; +} + +/** +* @brief Writes Sector(s) +* @param lun : not used +* @param *buff: Data to be written +* @param sector: Sector address (LBA) +* @param count: Number of sectors to write (1..128) +* @retval DRESULT: Operation result +*/ +#if _USE_WRITE == 1 +DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count) +{ + DRESULT res = RES_ERROR; + uint32_t timeout; +#if defined(ENABLE_SCRATCH_BUFFER) + uint8_t ret; + int i; +#endif + WriteStatus = 0; +#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) + uint32_t alignedAddr; +#endif + + if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0) + { + return res; + } + +#if defined(ENABLE_SCRATCH_BUFFER) + if (!((uint32_t)buff & 0x3)) + { +#endif +#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) + + /* + the SCB_CleanDCache_by_Addr() requires a 32-Byte aligned address + adjust the address and the D-Cache size to clean accordingly. + */ + alignedAddr = (uint32_t)buff & ~0x1F; + SCB_CleanDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr)); +#endif + + + if(BSP_SD_WriteBlocks_DMA(BSP_SD_INSTANCE, (uint32_t*)buff, + (uint32_t)(sector), + count) == BSP_ERROR_NONE ) + { + /* Wait that writing process is completed or a timeout occurs */ + timeout = HAL_GetTick(); + while((WriteStatus == 0) && ((HAL_GetTick() - timeout) < SD_TIMEOUT)) + { + } + /* incase of a timeout return error */ + if (WriteStatus == 0) + { + res = RES_ERROR; + } + else + { + WriteStatus = 0; + timeout = HAL_GetTick(); + + while((HAL_GetTick() - timeout) < SD_TIMEOUT) + { + if (BSP_SD_GetCardState(BSP_SD_INSTANCE) == SD_TRANSFER_OK) + { + res = RES_OK; + break; + } + } + } + } +#if defined(ENABLE_SCRATCH_BUFFER) + } + else + { + /* Slow path, fetch each sector a part and memcpy to destination buffer */ +#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) + /* + * invalidate the scratch buffer before the next write to get the actual data instead of the cached one + */ + SCB_InvalidateDCache_by_Addr((uint32_t*)scratch, BLOCKSIZE); +#endif + + for (i = 0; i < count; i++) + { + WriteStatus = 0; + + memcpy((void *)scratch, (void *)buff, BLOCKSIZE); + buff += BLOCKSIZE; + + ret = BSP_SD_WriteBlocks_DMA(BSP_SD_INSTANCE, (uint32_t*)scratch, (uint32_t)sector++, 1); + if (ret == BSP_ERROR_NONE ) { + /* wait for a message from the queue or a timeout */ + timeout = HAL_GetTick(); + while((WriteStatus == 0) && (HAL_GetTick() - timeout < SD_TIMEOUT)) + { + } + if (WriteStatus == 0) + { + break; + } + + } + else + { + break; + } + } + if ((i == count) && (ret == BSP_ERROR_NONE )) + res = RES_OK; + } +#endif + return res; +} +#endif /* _USE_WRITE == 1 */ + +/** +* @brief I/O control operation +* @param lun : not used +* @param cmd: Control code +* @param *buff: Buffer to send/receive control data +* @retval DRESULT: Operation result +*/ +#if _USE_IOCTL == 1 +DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff) +{ + DRESULT res = RES_ERROR; + BSP_SD_CardInfo CardInfo; + + if (Stat & STA_NOINIT) return RES_NOTRDY; + + switch (cmd) + { + /* Make sure that no pending write process */ + case CTRL_SYNC : + res = RES_OK; + break; + + /* Get number of sectors on the disk (DWORD) */ + case GET_SECTOR_COUNT : + BSP_SD_GetCardInfo(BSP_SD_INSTANCE, &CardInfo); + *(DWORD*)buff = CardInfo.LogBlockNbr; + res = RES_OK; + break; + + /* Get R/W sector size (WORD) */ + case GET_SECTOR_SIZE : + BSP_SD_GetCardInfo(BSP_SD_INSTANCE, &CardInfo); + *(WORD*)buff = CardInfo.LogBlockSize; + res = RES_OK; + break; + + /* Get erase block size in unit of sector (DWORD) */ + case GET_BLOCK_SIZE : + BSP_SD_GetCardInfo(BSP_SD_INSTANCE, &CardInfo); + *(DWORD*)buff = CardInfo.LogBlockSize / SD_DEFAULT_BLOCK_SIZE; + res = RES_OK; + break; + + default: + res = RES_PARERR; + } + + return res; +} +#endif /* _USE_IOCTL == 1 */ + + + +/** +* @brief Tx Transfer completed callbacks +* @param hsd: SD handle +* @retval None +*/ + +void BSP_SD_WriteCpltCallback(uint32_t Instance) +{ + if (Instance == BSP_SD_INSTANCE) + { + WriteStatus = 1; + } +} + +/** +* @brief Rx Transfer completed callbacks +* @param hsd: SD handle +* @retval None +*/ + +void BSP_SD_ReadCpltCallback(uint32_t Instance) +{ + if (Instance == BSP_SD_INSTANCE) + { + ReadStatus = 1; + } +} + + void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd) + { + while(1) + { + } + } +/* +void BSP_SD_AbortCallback(void) +{ +} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_template.c b/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_template.c deleted file mode 100644 index 6f034b5ae..000000000 --- a/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_template.c +++ /dev/null @@ -1,225 +0,0 @@ -/** - ****************************************************************************** - * @file sd_diskio_template.c - * @author MCD Application Team - * @brief SD Disk I/O template driver.This file needs to be renamed and copied - into the application project alongside the respective header file - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -**/ -/* Includes ------------------------------------------------------------------*/ -#include "ff_gen_drv.h" -#include "sd_diskio.h" - - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* use the default SD timout as defined in the platform BSP driver*/ -#if defined(SDMMC_DATATIMEOUT) -#define SD_TIMEOUT SDMMC_DATATIMEOUT -#elif defined(SD_DATATIMEOUT) -#define SD_TIMEOUT SD_DATATIMEOUT -#else -#define SD_TIMEOUT 30 * 1000 -#endif - -#define SD_DEFAULT_BLOCK_SIZE 512 - -/* - * Depending on the usecase, the SD card initialization could be done at the - * application level, if it is the case define the flag below to disable - * the BSP_SD_Init() call in the SD_Initialize(). - */ - -/* #define DISABLE_SD_INIT */ - -/* Private variables ---------------------------------------------------------*/ -/* Disk status */ -static volatile DSTATUS Stat = STA_NOINIT; - -/* Private function prototypes -----------------------------------------------*/ -static DSTATUS SD_CheckStatus(BYTE lun); -DSTATUS SD_initialize (BYTE); -DSTATUS SD_status (BYTE); -DRESULT SD_read (BYTE, BYTE*, DWORD, UINT); -#if _USE_WRITE == 1 - DRESULT SD_write (BYTE, const BYTE*, DWORD, UINT); -#endif /* _USE_WRITE == 1 */ -#if _USE_IOCTL == 1 - DRESULT SD_ioctl (BYTE, BYTE, void*); -#endif /* _USE_IOCTL == 1 */ - -const Diskio_drvTypeDef SD_Driver = -{ - SD_initialize, - SD_status, - SD_read, -#if _USE_WRITE == 1 - SD_write, -#endif /* _USE_WRITE == 1 */ - -#if _USE_IOCTL == 1 - SD_ioctl, -#endif /* _USE_IOCTL == 1 */ -}; - -/* Private functions ---------------------------------------------------------*/ -static DSTATUS SD_CheckStatus(BYTE lun) -{ - Stat = STA_NOINIT; - - if(BSP_SD_GetCardState() == MSD_OK) - { - Stat &= ~STA_NOINIT; - } - - return Stat; -} - -/** - * @brief Initializes a Drive - * @param lun : not used - * @retval DSTATUS: Operation status - */ -DSTATUS SD_initialize(BYTE lun) -{ - Stat = STA_NOINIT; -#if !defined(DISABLE_SD_INIT) - - if(BSP_SD_Init() == MSD_OK) - { - Stat = SD_CheckStatus(lun); - } - -#else - Stat = SD_CheckStatus(lun); -#endif - return Stat; -} - -/** - * @brief Gets Disk Status - * @param lun : not used - * @retval DSTATUS: Operation status - */ -DSTATUS SD_status(BYTE lun) -{ - return SD_CheckStatus(lun); -} - -/** - * @brief Reads Sector(s) - * @param lun : not used - * @param *buff: Data buffer to store read data - * @param sector: Sector address (LBA) - * @param count: Number of sectors to read (1..128) - * @retval DRESULT: Operation result - */ -DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count) -{ - DRESULT res = RES_ERROR; - - if(BSP_SD_ReadBlocks((uint32_t*)buff, - (uint32_t) (sector), - count, SD_TIMEOUT) == MSD_OK) - { - /* wait until the read operation is finished */ - while(BSP_SD_GetCardState()!= MSD_OK) - { - } - res = RES_OK; - } - - return res; -} - -/** - * @brief Writes Sector(s) - * @param lun : not used - * @param *buff: Data to be written - * @param sector: Sector address (LBA) - * @param count: Number of sectors to write (1..128) - * @retval DRESULT: Operation result - */ -#if _USE_WRITE == 1 -DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count) -{ - DRESULT res = RES_ERROR; - - if(BSP_SD_WriteBlocks((uint32_t*)buff, - (uint32_t)(sector), - count, SD_TIMEOUT) == MSD_OK) - { - /* wait until the Write operation is finished */ - while(BSP_SD_GetCardState() != MSD_OK) - { - } - res = RES_OK; - } - - return res; -} -#endif /* _USE_WRITE == 1 */ - -/** - * @brief I/O control operation - * @param lun : not used - * @param cmd: Control code - * @param *buff: Buffer to send/receive control data - * @retval DRESULT: Operation result - */ -#if _USE_IOCTL == 1 -DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff) -{ - DRESULT res = RES_ERROR; - BSP_SD_CardInfo CardInfo; - - if (Stat & STA_NOINIT) return RES_NOTRDY; - - switch (cmd) - { - /* Make sure that no pending write process */ - case CTRL_SYNC : - res = RES_OK; - break; - - /* Get number of sectors on the disk (DWORD) */ - case GET_SECTOR_COUNT : - BSP_SD_GetCardInfo(&CardInfo); - *(DWORD*)buff = CardInfo.LogBlockNbr; - res = RES_OK; - break; - - /* Get R/W sector size (WORD) */ - case GET_SECTOR_SIZE : - BSP_SD_GetCardInfo(&CardInfo); - *(WORD*)buff = CardInfo.LogBlockSize; - res = RES_OK; - break; - - /* Get erase block size in unit of sector (DWORD) */ - case GET_BLOCK_SIZE : - BSP_SD_GetCardInfo(&CardInfo); - *(DWORD*)buff = CardInfo.LogBlockSize / SD_DEFAULT_BLOCK_SIZE; - res = RES_OK; - break; - - default: - res = RES_PARERR; - } - - return res; -} -#endif /* _USE_IOCTL == 1 */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_template_bspv1.c b/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_template_bspv1.c new file mode 100644 index 000000000..0f2c25e61 --- /dev/null +++ b/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_template_bspv1.c @@ -0,0 +1,226 @@ +/** + ****************************************************************************** + * @file sd_diskio_template_bspv1.c + * @author MCD Application Team + * @brief SD Disk I/O template driver based on BSP v1 api. This file needs + * to be renamed and copied into the application project alongside + * the respective header file + ****************************************************************************** + * @attention + * + * Copyright (c) 2017-2019 STMicroelectronics. All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +**/ +/* Includes ------------------------------------------------------------------*/ +#include "ff_gen_drv.h" +#include "sd_diskio.h" + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* use the default SD timout as defined in the platform BSP driver*/ +#if defined(SDMMC_DATATIMEOUT) +#define SD_TIMEOUT SDMMC_DATATIMEOUT +#elif defined(SD_DATATIMEOUT) +#define SD_TIMEOUT SD_DATATIMEOUT +#else +#define SD_TIMEOUT 30 * 1000 +#endif + +#define SD_DEFAULT_BLOCK_SIZE 512 + +/* + * Depending on the usecase, the SD card initialization could be done at the + * application level, if it is the case define the flag below to disable + * the BSP_SD_Init() call in the SD_Initialize(). + */ + +/* #define DISABLE_SD_INIT */ + +/* Private variables ---------------------------------------------------------*/ +/* Disk status */ +static volatile DSTATUS Stat = STA_NOINIT; + +/* Private function prototypes -----------------------------------------------*/ +static DSTATUS SD_CheckStatus(BYTE lun); +DSTATUS SD_initialize (BYTE); +DSTATUS SD_status (BYTE); +DRESULT SD_read (BYTE, BYTE*, DWORD, UINT); +#if _USE_WRITE == 1 + DRESULT SD_write (BYTE, const BYTE*, DWORD, UINT); +#endif /* _USE_WRITE == 1 */ +#if _USE_IOCTL == 1 + DRESULT SD_ioctl (BYTE, BYTE, void*); +#endif /* _USE_IOCTL == 1 */ + +const Diskio_drvTypeDef SD_Driver = +{ + SD_initialize, + SD_status, + SD_read, +#if _USE_WRITE == 1 + SD_write, +#endif /* _USE_WRITE == 1 */ + +#if _USE_IOCTL == 1 + SD_ioctl, +#endif /* _USE_IOCTL == 1 */ +}; + +/* Private functions ---------------------------------------------------------*/ +static DSTATUS SD_CheckStatus(BYTE lun) +{ + Stat = STA_NOINIT; + + if(BSP_SD_GetCardState() == MSD_OK) + { + Stat &= ~STA_NOINIT; + } + + return Stat; +} + +/** + * @brief Initializes a Drive + * @param lun : not used + * @retval DSTATUS: Operation status + */ +DSTATUS SD_initialize(BYTE lun) +{ + Stat = STA_NOINIT; +#if !defined(DISABLE_SD_INIT) + + if(BSP_SD_Init() == MSD_OK) + { + Stat = SD_CheckStatus(lun); + } + +#else + Stat = SD_CheckStatus(lun); +#endif + return Stat; +} + +/** + * @brief Gets Disk Status + * @param lun : not used + * @retval DSTATUS: Operation status + */ +DSTATUS SD_status(BYTE lun) +{ + return SD_CheckStatus(lun); +} + +/** + * @brief Reads Sector(s) + * @param lun : not used + * @param *buff: Data buffer to store read data + * @param sector: Sector address (LBA) + * @param count: Number of sectors to read (1..128) + * @retval DRESULT: Operation result + */ +DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count) +{ + DRESULT res = RES_ERROR; + + if(BSP_SD_ReadBlocks((uint32_t*)buff, + (uint32_t) (sector), + count, SD_TIMEOUT) == MSD_OK) + { + /* wait until the read operation is finished */ + while(BSP_SD_GetCardState()!= MSD_OK) + { + } + res = RES_OK; + } + + return res; +} + +/** + * @brief Writes Sector(s) + * @param lun : not used + * @param *buff: Data to be written + * @param sector: Sector address (LBA) + * @param count: Number of sectors to write (1..128) + * @retval DRESULT: Operation result + */ +#if _USE_WRITE == 1 +DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count) +{ + DRESULT res = RES_ERROR; + + if(BSP_SD_WriteBlocks((uint32_t*)buff, + (uint32_t)(sector), + count, SD_TIMEOUT) == MSD_OK) + { + /* wait until the Write operation is finished */ + while(BSP_SD_GetCardState() != MSD_OK) + { + } + res = RES_OK; + } + + return res; +} +#endif /* _USE_WRITE == 1 */ + +/** + * @brief I/O control operation + * @param lun : not used + * @param cmd: Control code + * @param *buff: Buffer to send/receive control data + * @retval DRESULT: Operation result + */ +#if _USE_IOCTL == 1 +DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff) +{ + DRESULT res = RES_ERROR; + BSP_SD_CardInfo CardInfo; + + if (Stat & STA_NOINIT) return RES_NOTRDY; + + switch (cmd) + { + /* Make sure that no pending write process */ + case CTRL_SYNC : + res = RES_OK; + break; + + /* Get number of sectors on the disk (DWORD) */ + case GET_SECTOR_COUNT : + BSP_SD_GetCardInfo(&CardInfo); + *(DWORD*)buff = CardInfo.LogBlockNbr; + res = RES_OK; + break; + + /* Get R/W sector size (WORD) */ + case GET_SECTOR_SIZE : + BSP_SD_GetCardInfo(&CardInfo); + *(WORD*)buff = CardInfo.LogBlockSize; + res = RES_OK; + break; + + /* Get erase block size in unit of sector (DWORD) */ + case GET_BLOCK_SIZE : + BSP_SD_GetCardInfo(&CardInfo); + *(DWORD*)buff = CardInfo.LogBlockSize / SD_DEFAULT_BLOCK_SIZE; + res = RES_OK; + break; + + default: + res = RES_PARERR; + } + + return res; +} +#endif /* _USE_IOCTL == 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_template_bspv2.c b/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_template_bspv2.c new file mode 100644 index 000000000..8be2e158f --- /dev/null +++ b/Middlewares/Third_Party/FatFs/src/drivers/sd_diskio_template_bspv2.c @@ -0,0 +1,238 @@ +/** + ****************************************************************************** + * @file sd_diskio_template_bspv2.c + * @author MCD Application Team + * @brief SD Disk I/O template driver Using the BSPv2 API. This file needs + * to be renamed and copied into the application project + * alongside the respective header file + ****************************************************************************** + * @attention + * + * Copyright (c) 2017-2019 STMicroelectronics. All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +**/ + +/* Includes ------------------------------------------------------------------*/ +#include "ff_gen_drv.h" +#include "sd_diskio.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* use the default SD timeout as defined in the platform BSP driver*/ +#if defined(SDMMC_DATATIMEOUT) +#define SD_TIMEOUT SDMMC_DATATIMEOUT +#elif defined(SD_DATATIMEOUT) +#define SD_TIMEOUT SD_DATATIMEOUT +#else +#define SD_TIMEOUT 30 * 1000 +#endif + +#define SD_DEFAULT_BLOCK_SIZE 512 + +/* + * in case the BSP_SD_XXX() API is called by the application + * make sure the use the same instance in the application and the + * diskio driver + */ +#ifndef BSP_SD_INSTANCE +#define BSP_SD_INSTANCE 0 +#endif + +#if BSP_SD_INSTANCE >= SD_INSTANCES_NBR +#error "Wrong BSP_SD_INSTANCE" +#endif +/* + * Depending on the usecase, the SD card initialization could be done at the + * application level, if it is the case define the flag below to disable + * the BSP_SD_Init() call in the SD_Initialize(). + */ + +/* #define DISABLE_SD_INIT */ + +/* Private variables ---------------------------------------------------------*/ +/* Disk status */ +static volatile DSTATUS Stat = STA_NOINIT; + +/* Private function prototypes -----------------------------------------------*/ +static DSTATUS SD_CheckStatus(BYTE lun); +DSTATUS SD_initialize (BYTE); +DSTATUS SD_status (BYTE); +DRESULT SD_read (BYTE, BYTE*, DWORD, UINT); +#if _USE_WRITE == 1 + DRESULT SD_write (BYTE, const BYTE*, DWORD, UINT); +#endif /* _USE_WRITE == 1 */ +#if _USE_IOCTL == 1 + DRESULT SD_ioctl (BYTE, BYTE, void*); +#endif /* _USE_IOCTL == 1 */ + +const Diskio_drvTypeDef SD_Driver = +{ + SD_initialize, + SD_status, + SD_read, +#if _USE_WRITE == 1 + SD_write, +#endif /* _USE_WRITE == 1 */ + +#if _USE_IOCTL == 1 + SD_ioctl, +#endif /* _USE_IOCTL == 1 */ +}; + +/* Private functions ---------------------------------------------------------*/ +static DSTATUS SD_CheckStatus(BYTE lun) +{ + Stat = STA_NOINIT; + + if(BSP_SD_GetCardState(BSP_SD_INSTANCE) == BSP_ERROR_NONE) + { + Stat &= ~STA_NOINIT; + } + + return Stat; +} + +/** + * @brief Initializes a Drive + * @param lun : not used + * @retval DSTATUS: Operation status + */ +DSTATUS SD_initialize(BYTE lun) +{ + Stat = STA_NOINIT; +#if !defined(DISABLE_SD_INIT) + + if(BSP_SD_Init(BSP_SD_INSTANCE) == MSD_OK) + { + Stat = SD_CheckStatus(lun); + } + +#else + Stat = SD_CheckStatus(lun); +#endif + return Stat; +} + +/** + * @brief Gets Disk Status + * @param lun : not used + * @retval DSTATUS: Operation status + */ +DSTATUS SD_status(BYTE lun) +{ + return SD_CheckStatus(lun); +} + +/** + * @brief Reads Sector(s) + * @param lun : not used + * @param *buff: Data buffer to store read data + * @param sector: Sector address (LBA) + * @param count: Number of sectors to read (1..128) + * @retval DRESULT: Operation result + */ +DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count) +{ + DRESULT res = RES_ERROR; + + if(BSP_SD_ReadBlocks(BSP_SD_INSTANCE,(uint32_t*)buff, + (uint32_t) (sector), + count) == BSP_ERROR_NONE) + { + /* wait until the read operation is finished */ + while(BSP_SD_GetCardState(BSP_SD_INSTANCE)!= BSP_ERROR_NONE) + { + } + res = RES_OK; + } + + return res; +} + +/** + * @brief Writes Sector(s) + * @param lun : not used + * @param *buff: Data to be written + * @param sector: Sector address (LBA) + * @param count: Number of sectors to write (1..128) + * @retval DRESULT: Operation result + */ +#if _USE_WRITE == 1 +DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count) +{ + DRESULT res = RES_ERROR; + + if(BSP_SD_WriteBlocks(BSP_SD_INSTANCE,(uint32_t*)buff, + (uint32_t)(sector), + count) == BSP_ERROR_NONE) + { + /* wait until the Write operation is finished */ + while(BSP_SD_GetCardState(BSP_SD_INSTANCE) != BSP_ERROR_NONE) + { + } + res = RES_OK; + } + + return res; +} +#endif /* _USE_WRITE == 1 */ + +/** + * @brief I/O control operation + * @param lun : not used + * @param cmd: Control code + * @param *buff: Buffer to send/receive control data + * @retval DRESULT: Operation result + */ +#if _USE_IOCTL == 1 +DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff) +{ + DRESULT res = RES_ERROR; + BSP_SD_CardInfo CardInfo; + + if (Stat & STA_NOINIT) return RES_NOTRDY; + + switch (cmd) + { + /* Make sure that no pending write process */ + case CTRL_SYNC : + res = RES_OK; + break; + + /* Get number of sectors on the disk (DWORD) */ + case GET_SECTOR_COUNT : + BSP_SD_GetCardInfo(BSP_SD_INSTANCE,&CardInfo); + *(DWORD*)buff = CardInfo.LogBlockNbr; + res = RES_OK; + break; + + /* Get R/W sector size (WORD) */ + case GET_SECTOR_SIZE : + BSP_SD_GetCardInfo(BSP_SD_INSTANCE,&CardInfo); + *(WORD*)buff = CardInfo.LogBlockSize; + res = RES_OK; + break; + + /* Get erase block size in unit of sector (DWORD) */ + case GET_BLOCK_SIZE : + BSP_SD_GetCardInfo(BSP_SD_INSTANCE,&CardInfo); + *(DWORD*)buff = CardInfo.LogBlockSize / SD_DEFAULT_BLOCK_SIZE; + res = RES_OK; + break; + + default: + res = RES_PARERR; + } + + return res; +} +#endif /* _USE_IOCTL == 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Middlewares/Third_Party/FatFs/src/drivers/sdram_diskio_template.c b/Middlewares/Third_Party/FatFs/src/drivers/sdram_diskio_template.c deleted file mode 100644 index b33f38b53..000000000 --- a/Middlewares/Third_Party/FatFs/src/drivers/sdram_diskio_template.c +++ /dev/null @@ -1,181 +0,0 @@ -/** - ****************************************************************************** - * @file sdram_diskio_template.c - * @author MCD Application Team - * @brief SDRAM Disk I/O template driver.This file needs to be copied under - the application project alongside the respective header file. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -**/ -/* Includes ------------------------------------------------------------------*/ -#include "ff_gen_drv.h" -#include "sdram_diskio.h" - - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Block Size in Bytes */ -#define BLOCK_SIZE 512 - -/* Private variables ---------------------------------------------------------*/ -/* Disk status */ -static volatile DSTATUS Stat = STA_NOINIT; - -/* Private function prototypes -----------------------------------------------*/ -DSTATUS SDRAMDISK_initialize (BYTE); -DSTATUS SDRAMDISK_status (BYTE); -DRESULT SDRAMDISK_read (BYTE, BYTE*, DWORD, UINT); -#if _USE_WRITE == 1 - DRESULT SDRAMDISK_write (BYTE, const BYTE*, DWORD, UINT); -#endif /* _USE_WRITE == 1 */ -#if _USE_IOCTL == 1 - DRESULT SDRAMDISK_ioctl (BYTE, BYTE, void*); -#endif /* _USE_IOCTL == 1 */ - -const Diskio_drvTypeDef SDRAMDISK_Driver = -{ - SDRAMDISK_initialize, - SDRAMDISK_status, - SDRAMDISK_read, -#if _USE_WRITE - SDRAMDISK_write, -#endif /* _USE_WRITE == 1 */ -#if _USE_IOCTL == 1 - SDRAMDISK_ioctl, -#endif /* _USE_IOCTL == 1 */ -}; - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief Initializes a Drive - * @param lun : not used - * @retval DSTATUS: Operation status - */ -DSTATUS SDRAMDISK_initialize(BYTE lun) -{ - Stat = STA_NOINIT; - - /* Configure the SDRAM device */ - if(BSP_SDRAM_Init() == SDRAM_OK) - { - Stat &= ~STA_NOINIT; - } - - return Stat; -} - -/** - * @brief Gets Disk Status - * @param lun : not used - * @retval DSTATUS: Operation status - */ -DSTATUS SDRAMDISK_status(BYTE lun) -{ - return Stat; -} - -/** - * @brief Reads Sector(s) - * @param lun : not used - * @param *buff: Data buffer to store read data - * @param sector: Sector address (LBA) - * @param count: Number of sectors to read (1..128) - * @retval DRESULT: Operation result - */ -DRESULT SDRAMDISK_read(BYTE lun, BYTE *buff, DWORD sector, UINT count) -{ - uint32_t *pSrcBuffer = (uint32_t *)buff; - uint32_t BufferSize = (BLOCK_SIZE * count)/4; - uint32_t *pSdramAddress = (uint32_t *) (SDRAM_DEVICE_ADDR + (sector * BLOCK_SIZE)); - - for(; BufferSize != 0; BufferSize--) - { - *pSrcBuffer++ = *(__IO uint32_t *)pSdramAddress++; - } - - return RES_OK; -} - -/** - * @brief Writes Sector(s) - * @param lun : not used - * @param *buff: Data to be written - * @param sector: Sector address (LBA) - * @param count: Number of sectors to write (1..128) - * @retval DRESULT: Operation result - */ -#if _USE_WRITE == 1 -DRESULT SDRAMDISK_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count) -{ - uint32_t *pDstBuffer = (uint32_t *)buff; - uint32_t BufferSize = (BLOCK_SIZE * count)/4; - uint32_t *pSramAddress = (uint32_t *) (SDRAM_DEVICE_ADDR + (sector * BLOCK_SIZE)); - - for(; BufferSize != 0; BufferSize--) - { - *(__IO uint32_t *)pSramAddress++ = *pDstBuffer++; - } - - return RES_OK; -} -#endif /* _USE_WRITE == 1 */ - -/** - * @brief I/O control operation - * @param lun : not used - * @param cmd: Control code - * @param *buff: Buffer to send/receive control data - * @retval DRESULT: Operation result - */ -#if _USE_IOCTL == 1 -DRESULT SDRAMDISK_ioctl(BYTE lun, BYTE cmd, void *buff) -{ - DRESULT res = RES_ERROR; - - if (Stat & STA_NOINIT) return RES_NOTRDY; - - switch (cmd) - { - /* Make sure that no pending write process */ - case CTRL_SYNC : - res = RES_OK; - break; - - /* Get number of sectors on the disk (DWORD) */ - case GET_SECTOR_COUNT : - *(DWORD*)buff = SDRAM_DEVICE_SIZE / BLOCK_SIZE; - res = RES_OK; - break; - - /* Get R/W sector size (WORD) */ - case GET_SECTOR_SIZE : - *(WORD*)buff = BLOCK_SIZE; - res = RES_OK; - break; - - /* Get erase block size in unit of sector (DWORD) */ - case GET_BLOCK_SIZE : - *(DWORD*)buff = 1; - res = RES_OK; - break; - - default: - res = RES_PARERR; - } - - return res; -} -#endif /* _USE_IOCTL == 1 */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Middlewares/Third_Party/FatFs/src/drivers/sdram_diskio_template_bspv1.c b/Middlewares/Third_Party/FatFs/src/drivers/sdram_diskio_template_bspv1.c new file mode 100644 index 000000000..7386e2830 --- /dev/null +++ b/Middlewares/Third_Party/FatFs/src/drivers/sdram_diskio_template_bspv1.c @@ -0,0 +1,182 @@ +/** + ****************************************************************************** + * @file sdram_diskio_template_bspv1.c + * @author MCD Application Team + * @brief SDRAM Disk I/O template driver using BSP v1 API. + * This file needs to be copied under the application project + * alongside the respective header file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +**/ +/* Includes ------------------------------------------------------------------*/ +#include "ff_gen_drv.h" +#include "sdram_diskio.h" + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Block Size in Bytes */ +#define BLOCK_SIZE 512 + +/* Private variables ---------------------------------------------------------*/ +/* Disk status */ +static volatile DSTATUS Stat = STA_NOINIT; + +/* Private function prototypes -----------------------------------------------*/ +DSTATUS SDRAMDISK_initialize (BYTE); +DSTATUS SDRAMDISK_status (BYTE); +DRESULT SDRAMDISK_read (BYTE, BYTE*, DWORD, UINT); +#if _USE_WRITE == 1 + DRESULT SDRAMDISK_write (BYTE, const BYTE*, DWORD, UINT); +#endif /* _USE_WRITE == 1 */ +#if _USE_IOCTL == 1 + DRESULT SDRAMDISK_ioctl (BYTE, BYTE, void*); +#endif /* _USE_IOCTL == 1 */ + +const Diskio_drvTypeDef SDRAMDISK_Driver = +{ + SDRAMDISK_initialize, + SDRAMDISK_status, + SDRAMDISK_read, +#if _USE_WRITE + SDRAMDISK_write, +#endif /* _USE_WRITE == 1 */ +#if _USE_IOCTL == 1 + SDRAMDISK_ioctl, +#endif /* _USE_IOCTL == 1 */ +}; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Initializes a Drive + * @param lun : not used + * @retval DSTATUS: Operation status + */ +DSTATUS SDRAMDISK_initialize(BYTE lun) +{ + Stat = STA_NOINIT; + + /* Configure the SDRAM device */ + if(BSP_SDRAM_Init() == SDRAM_OK) + { + Stat &= ~STA_NOINIT; + } + + return Stat; +} + +/** + * @brief Gets Disk Status + * @param lun : not used + * @retval DSTATUS: Operation status + */ +DSTATUS SDRAMDISK_status(BYTE lun) +{ + return Stat; +} + +/** + * @brief Reads Sector(s) + * @param lun : not used + * @param *buff: Data buffer to store read data + * @param sector: Sector address (LBA) + * @param count: Number of sectors to read (1..128) + * @retval DRESULT: Operation result + */ +DRESULT SDRAMDISK_read(BYTE lun, BYTE *buff, DWORD sector, UINT count) +{ + uint32_t *pSrcBuffer = (uint32_t *)buff; + uint32_t BufferSize = (BLOCK_SIZE * count)/4; + uint32_t *pSdramAddress = (uint32_t *) (SDRAM_DEVICE_ADDR + (sector * BLOCK_SIZE)); + + for(; BufferSize != 0; BufferSize--) + { + *pSrcBuffer++ = *(__IO uint32_t *)pSdramAddress++; + } + + return RES_OK; +} + +/** + * @brief Writes Sector(s) + * @param lun : not used + * @param *buff: Data to be written + * @param sector: Sector address (LBA) + * @param count: Number of sectors to write (1..128) + * @retval DRESULT: Operation result + */ +#if _USE_WRITE == 1 +DRESULT SDRAMDISK_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count) +{ + uint32_t *pDstBuffer = (uint32_t *)buff; + uint32_t BufferSize = (BLOCK_SIZE * count)/4; + uint32_t *pSramAddress = (uint32_t *) (SDRAM_DEVICE_ADDR + (sector * BLOCK_SIZE)); + + for(; BufferSize != 0; BufferSize--) + { + *(__IO uint32_t *)pSramAddress++ = *pDstBuffer++; + } + + return RES_OK; +} +#endif /* _USE_WRITE == 1 */ + +/** + * @brief I/O control operation + * @param lun : not used + * @param cmd: Control code + * @param *buff: Buffer to send/receive control data + * @retval DRESULT: Operation result + */ +#if _USE_IOCTL == 1 +DRESULT SDRAMDISK_ioctl(BYTE lun, BYTE cmd, void *buff) +{ + DRESULT res = RES_ERROR; + + if (Stat & STA_NOINIT) return RES_NOTRDY; + + switch (cmd) + { + /* Make sure that no pending write process */ + case CTRL_SYNC : + res = RES_OK; + break; + + /* Get number of sectors on the disk (DWORD) */ + case GET_SECTOR_COUNT : + *(DWORD*)buff = SDRAM_DEVICE_SIZE / BLOCK_SIZE; + res = RES_OK; + break; + + /* Get R/W sector size (WORD) */ + case GET_SECTOR_SIZE : + *(WORD*)buff = BLOCK_SIZE; + res = RES_OK; + break; + + /* Get erase block size in unit of sector (DWORD) */ + case GET_BLOCK_SIZE : + *(DWORD*)buff = 1; + res = RES_OK; + break; + + default: + res = RES_PARERR; + } + + return res; +} +#endif /* _USE_IOCTL == 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Middlewares/Third_Party/FatFs/src/drivers/sdram_diskio_template_bspv2.c b/Middlewares/Third_Party/FatFs/src/drivers/sdram_diskio_template_bspv2.c new file mode 100644 index 000000000..ebc41a3b8 --- /dev/null +++ b/Middlewares/Third_Party/FatFs/src/drivers/sdram_diskio_template_bspv2.c @@ -0,0 +1,188 @@ +/** + ****************************************************************************** + * @file sdram_diskio_template_bspv2.c + * @author MCD Application Team + * @brief SDRAM Disk I/O template driver base on BSP v2 API. + * This file needs to be copied under the application project + * alongside the respective header file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017-2019 STMicroelectronics. All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +**/ + +/* Includes ------------------------------------------------------------------*/ +#include "ff_gen_drv.h" +#include "sdram_diskio.h" + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Block Size in Bytes */ +#define BLOCK_SIZE 512 + +#define BSP_SDRAM_INSTANCE 0 + +#if BSP_SDRAM_INSTANCE >= SDRAM_INSTANCES_NBR +#error "Wrong BSP_SDRAM_INSTANCE value" +#endif +/* Private variables ---------------------------------------------------------*/ +/* Disk status */ +static volatile DSTATUS Stat = STA_NOINIT; + +/* Private function prototypes -----------------------------------------------*/ +DSTATUS SDRAMDISK_initialize (BYTE); +DSTATUS SDRAMDISK_status (BYTE); +DRESULT SDRAMDISK_read (BYTE, BYTE*, DWORD, UINT); +#if _USE_WRITE == 1 + DRESULT SDRAMDISK_write (BYTE, const BYTE*, DWORD, UINT); +#endif /* _USE_WRITE == 1 */ +#if _USE_IOCTL == 1 + DRESULT SDRAMDISK_ioctl (BYTE, BYTE, void*); +#endif /* _USE_IOCTL == 1 */ + +const Diskio_drvTypeDef SDRAMDISK_Driver = +{ + SDRAMDISK_initialize, + SDRAMDISK_status, + SDRAMDISK_read, +#if _USE_WRITE + SDRAMDISK_write, +#endif /* _USE_WRITE == 1 */ +#if _USE_IOCTL == 1 + SDRAMDISK_ioctl, +#endif /* _USE_IOCTL == 1 */ +}; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Initializes a Drive + * @param lun : not used + * @retval DSTATUS: Operation status + */ +DSTATUS SDRAMDISK_initialize(BYTE lun) +{ + Stat = STA_NOINIT; + + /* Configure the SDRAM device */ + if(BSP_SDRAM_Init(BSP_SDRAM_INSTANCE) == BSP_ERROR_NONE) + { + Stat &= ~STA_NOINIT; + } + + return Stat; +} + +/** + * @brief Gets Disk Status + * @param lun : not used + * @retval DSTATUS: Operation status + */ +DSTATUS SDRAMDISK_status(BYTE lun) +{ + return Stat; +} + +/** + * @brief Reads Sector(s) + * @param lun : not used + * @param *buff: Data buffer to store read data + * @param sector: Sector address (LBA) + * @param count: Number of sectors to read (1..128) + * @retval DRESULT: Operation result + */ +DRESULT SDRAMDISK_read(BYTE lun, BYTE *buff, DWORD sector, UINT count) +{ + uint32_t *pSrcBuffer = (uint32_t *)buff; + uint32_t BufferSize = (BLOCK_SIZE * count)/4; + uint32_t *pSdramAddress = (uint32_t *) (SDRAM_DEVICE_ADDR + (sector * BLOCK_SIZE)); + + for(; BufferSize != 0; BufferSize--) + { + *pSrcBuffer++ = *(__IO uint32_t *)pSdramAddress++; + } + + return RES_OK; +} + +/** + * @brief Writes Sector(s) + * @param lun : not used + * @param *buff: Data to be written + * @param sector: Sector address (LBA) + * @param count: Number of sectors to write (1..128) + * @retval DRESULT: Operation result + */ +#if _USE_WRITE == 1 +DRESULT SDRAMDISK_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count) +{ + uint32_t *pDstBuffer = (uint32_t *)buff; + uint32_t BufferSize = (BLOCK_SIZE * count)/4; + uint32_t *pSramAddress = (uint32_t *) (SDRAM_DEVICE_ADDR + (sector * BLOCK_SIZE)); + + for(; BufferSize != 0; BufferSize--) + { + *(__IO uint32_t *)pSramAddress++ = *pDstBuffer++; + } + + return RES_OK; +} +#endif /* _USE_WRITE == 1 */ + +/** + * @brief I/O control operation + * @param lun : not used + * @param cmd: Control code + * @param *buff: Buffer to send/receive control data + * @retval DRESULT: Operation result + */ +#if _USE_IOCTL == 1 +DRESULT SDRAMDISK_ioctl(BYTE lun, BYTE cmd, void *buff) +{ + DRESULT res = RES_ERROR; + + if (Stat & STA_NOINIT) return RES_NOTRDY; + + switch (cmd) + { + /* Make sure that no pending write process */ + case CTRL_SYNC : + res = RES_OK; + break; + + /* Get number of sectors on the disk (DWORD) */ + case GET_SECTOR_COUNT : + *(DWORD*)buff = SDRAM_DEVICE_SIZE / BLOCK_SIZE; + res = RES_OK; + break; + + /* Get R/W sector size (WORD) */ + case GET_SECTOR_SIZE : + *(WORD*)buff = BLOCK_SIZE; + res = RES_OK; + break; + + /* Get erase block size in unit of sector (DWORD) */ + case GET_BLOCK_SIZE : + *(DWORD*)buff = 1; + res = RES_OK; + break; + + default: + res = RES_PARERR; + } + + return res; +} +#endif /* _USE_IOCTL == 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Middlewares/Third_Party/FatFs/src/drivers/usbh_diskio_dma_template.c b/Middlewares/Third_Party/FatFs/src/drivers/usbh_diskio_dma_template.c index a9e6837a9..071b2fe48 100644 --- a/Middlewares/Third_Party/FatFs/src/drivers/usbh_diskio_dma_template.c +++ b/Middlewares/Third_Party/FatFs/src/drivers/usbh_diskio_dma_template.c @@ -104,7 +104,7 @@ DRESULT USBH_read(BYTE lun, BYTE *buff, DWORD sector, UINT count) MSC_LUNTypeDef info; USBH_StatusTypeDef status = USBH_OK; - if (((DWORD)buff & 3) && (((HCD_HandleTypeDef *)hUSB_Host.pData)->Init.dma_enable)) + if ((DWORD)buff & 3) { while ((count--)&&(status == USBH_OK)) { @@ -166,7 +166,7 @@ DRESULT USBH_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count) MSC_LUNTypeDef info; USBH_StatusTypeDef status = USBH_OK; - if (((DWORD)buff & 3) && (((HCD_HandleTypeDef *)hUSB_Host.pData)->Init.dma_enable)) + if ((DWORD)buff & 3) { while (count--) diff --git a/Middlewares/Third_Party/FatFs/src/ffconf_template.h b/Middlewares/Third_Party/FatFs/src/ffconf_template.h index 5dd97d616..c74e72ea4 100644 --- a/Middlewares/Third_Party/FatFs/src/ffconf_template.h +++ b/Middlewares/Third_Party/FatFs/src/ffconf_template.h @@ -261,13 +261,32 @@ / can be opened simultaneously under file lock control. Note that the file / lock control is independent of re-entrancy. */ -#define _FS_REENTRANT 1 +#define _FS_REENTRANT 0 +#define _USE_MUTEX 0 +/* Use CMSIS-OS mutexes as _SYNC_t object instead of Semaphores */ #if _FS_REENTRANT + #include "cmsis_os.h" #define _FS_TIMEOUT 1000 -#define _SYNC_t osSemaphoreId + +#if _USE_MUTEX + +#if (osCMSIS < 0x20000U) +#define _SYNC_t osMutexId +#else +#define _SYNC_t osMutexId_t #endif + +#else +#if (osCMSIS < 0x20000U) +#define _SYNC_t osSemaphoreId +#else +#define _SYNC_t osSemaphoreId_t +#endif + +#endif +#endif //_FS_REENTRANT /* The option _FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs / module itself. Note that regardless of this option, file access to different / volume is always re-entrant and volume control functions, f_mount(), f_mkfs() @@ -288,6 +307,7 @@ /* #include // O/S definitions */ #if _USE_LFN == 3 + #if !defined(ff_malloc) || !defined(ff_free) #include #endif @@ -299,5 +319,23 @@ #if !defined(ff_free) #define ff_free free #endif + +/* by default the system malloc/free are used, but when the FreeRTOS is enabled +/ the macros pvPortMalloc()/vportFree() to be used thus uncomment the code below +/ +*/ +/* +#if !defined(ff_malloc) || !defined(ff_free) +#include "cmsis_os.h" +#endif + +#if !defined(ff_malloc) +#define ff_malloc pvPortMalloc +#endif + +#if !defined(ff_free) +#define ff_free vPortFree +#endif +*/ #endif /*--- End of configuration options ---*/ diff --git a/Middlewares/Third_Party/FatFs/src/option/syscall.c b/Middlewares/Third_Party/FatFs/src/option/syscall.c index 0cb3c1379..cd6370dc9 100644 --- a/Middlewares/Third_Party/FatFs/src/option/syscall.c +++ b/Middlewares/Third_Party/FatFs/src/option/syscall.c @@ -40,9 +40,25 @@ int ff_cre_syncobj ( /* 1:Function succeeded, 0:Could not create the sync object { int ret; +#if _USE_MUTEX +#if (osCMSIS < 0x20000U) + osMutexDef(MTX); + *sobj = osMutexCreate(osMutex(MTX)); +#else + *sobj = osMutexNew(NULL); +#endif + +#else + +#if (osCMSIS < 0x20000U) osSemaphoreDef(SEM); *sobj = osSemaphoreCreate(osSemaphore(SEM), 1); +#else + *sobj = osSemaphoreNew(1, 1, NULL); +#endif + +#endif ret = (*sobj != NULL); return ret; @@ -62,7 +78,11 @@ int ff_del_syncobj ( /* 1:Function succeeded, 0:Could not delete due to any erro _SYNC_t sobj /* Sync object tied to the logical drive to be deleted */ ) { +#if _USE_MUTEX + osMutexDelete (sobj); +#else osSemaphoreDelete (sobj); +#endif return 1; } @@ -80,8 +100,23 @@ int ff_req_grant ( /* 1:Got a grant to access the volume, 0:Could not get a gran ) { int ret = 0; +#if (osCMSIS < 0x20000U) +#if _USE_MUTEX + if(osMutexWait(sobj, _FS_TIMEOUT) == osOK) +#else if(osSemaphoreWait(sobj, _FS_TIMEOUT) == osOK) +#endif + +#else + +#if _USE_MUTEX + if(osMutexAcquire(sobj, _FS_TIMEOUT) == osOK) +#else + if(osSemaphoreAcquire(sobj, _FS_TIMEOUT) == osOK) +#endif + +#endif { ret = 1; } @@ -101,7 +136,11 @@ void ff_rel_grant ( _SYNC_t sobj /* Sync object to be signaled */ ) { +#if _USE_MUTEX + osMutexRelease(sobj); +#else osSemaphoreRelease(sobj); +#endif } #endif diff --git a/Middlewares/Third_Party/FatFs/src/st_readme.txt b/Middlewares/Third_Party/FatFs/src/st_readme.txt index d835ed018..a52e89a2e 100644 --- a/Middlewares/Third_Party/FatFs/src/st_readme.txt +++ b/Middlewares/Third_Party/FatFs/src/st_readme.txt @@ -19,6 +19,41 @@ ****************************************************************************** @endverbatim +### V2.1.4/18-10-2019 ### +============================ ++ Fix wrong usage of the "memcpy" in the SD_Write() function + - drivers/sd_diskio_dma_template_bspv1.c + - drivers/sd_diskio_dma_template_bspv2.c + - drivers/sd_diskio_dma_rtos_template_bspv1.c + - drivers/sd_diskio_dma_rtos_template_bspv2.c + ++ correct the usage of the "_USE_MUTEX" config flag + - syscall.c + +### V2.1.3/26-07-2019 ### +============================ ++ add new BSPv2 templates: + - drivers/sd_diskio_dma_rtos_template_bspv2.c + - drivers/sd_diskio_dma_template_bspv2.c + - drivers/sd_diskio_template_bspv2.c + - drivers/sdram_diskio_template_bspv2.c + ++ rename old template to "xxxx_diskio_template_bspv1.c": + - drivers/sd_diskio_dma_rtos_template_bspv1.c + - drivers/sd_diskio_dma_template_bspv1.c + - drivers/sd_diskio_template_bspv1.c + - drivers/sdram_diskio_template_bspv1.c + ++ Add CMSIS-OSv2 support in templates, syscall.c and ff_conf_template.h + - syscall.c + - ff_conf_template.h + - drivers/sd_diskio_dma_rtos_template_bspv2.c + ++ support usage of "osMutex" alongside "osSemaphore" as _SYNC_t type in fatfs + - syscall.c + - ff_conf_template.h + + ### V2.1.2/29-03-2019 ### ============================ + add st_license.txt in the root directory diff --git a/Middlewares/Third_Party/FreeRTOS/License/license.txt b/Middlewares/Third_Party/FreeRTOS/License/license.txt index 0072310c4..2977d52f6 100644 --- a/Middlewares/Third_Party/FreeRTOS/License/license.txt +++ b/Middlewares/Third_Party/FreeRTOS/License/license.txt @@ -17,7 +17,7 @@ source file. License text: ------------- -Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. +Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c index 72f23ad9c..89c36334e 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c @@ -364,7 +364,7 @@ osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void 1, // period should be filled when starting the Timer using osTimerStart (type == osTimerPeriodic) ? pdTRUE : pdFALSE, (void *) argument, - (TaskFunction_t)timer_def->ptimer, + (TimerCallbackFunction_t)timer_def->ptimer, (StaticTimer_t *)timer_def->controlblock); } else { @@ -372,21 +372,21 @@ osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void 1, // period should be filled when starting the Timer using osTimerStart (type == osTimerPeriodic) ? pdTRUE : pdFALSE, (void *) argument, - (TaskFunction_t)timer_def->ptimer); + (TimerCallbackFunction_t)timer_def->ptimer); } #elif( configSUPPORT_STATIC_ALLOCATION == 1 ) return xTimerCreateStatic((const char *)"", 1, // period should be filled when starting the Timer using osTimerStart (type == osTimerPeriodic) ? pdTRUE : pdFALSE, (void *) argument, - (TaskFunction_t)timer_def->ptimer, + (TimerCallbackFunction_t)timer_def->ptimer, (StaticTimer_t *)timer_def->controlblock); #else return xTimerCreate((const char *)"", 1, // period should be filled when starting the Timer using osTimerStart (type == osTimerPeriodic) ? pdTRUE : pdFALSE, (void *) argument, - (TaskFunction_t)timer_def->ptimer); + (TimerCallbackFunction_t)timer_def->ptimer); #endif #else diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h index 3b885bb5d..711408a52 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h @@ -1,7 +1,5 @@ -/* -------------------------------------------------------------------------- - * Portions Copyright 2017 STMicroelectronics International N.V. All rights reserved. - * Portions Copyright (c) 2013-2017 ARM Limited. All rights reserved. - * -------------------------------------------------------------------------- +/* + * Copyright (c) 2013-2019 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -17,8 +15,13 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ---------------------------------------------------------------------- + * + * $Date: 10. January 2017 + * $Revision: V2.1.0 + * * Project: CMSIS-RTOS API - * Title: cmsis_os.h header file + * Title: cmsis_os.h FreeRTOS header file * * Version 0.02 * Initial Proposal Phase @@ -36,7 +39,7 @@ * Version 1.02 * Control functions for short timeouts in microsecond resolution: * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec - * Removed: osSignalGet + * Removed: osSignalGet * Version 2.0.0 * OS objects creation without macros (dynamic creation and resource allocation): * - added: osXxxxNew functions which replace osXxxxCreate @@ -64,7 +67,7 @@ * - added: osThreadSuspend, osThreadResume * - added: osThreadJoin, osThreadDetach, osThreadExit * - added: osThreadGetCount, osThreadEnumerate - * - added: Thread Flags (moved from Signals) + * - added: Thread Flags (moved from Signals) * Signals: * - renamed osSignals to osThreadFlags (moved to Thread Flags) * - changed return value of Set/Clear/Wait functions @@ -107,7 +110,7 @@ * - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize * - added: osMessageQueueGetCount, osMessageQueueGetSpace * - added: osMessageQueueReset, osMessageQueueDelete - * Mail Queue: + * Mail Queue: * - deprecated (superseded by extended Message Queue functionality) * Version 2.1.0 * Support for critical and uncritical sections (nesting safe): @@ -116,16 +119,22 @@ * Updated Thread and Event Flags: * - changed flags parameter and return type from int32_t to uint32_t *---------------------------------------------------------------------------*/ - + #ifndef CMSIS_OS_H_ #define CMSIS_OS_H_ -#define osCMSIS 0x20001U ///< API version (main[31:16].sub[15:0]) +#include "FreeRTOS.h" +#include "task.h" -#define osCMSIS_FreeRTOS 0xA0001U ///< RTOS identification and version (main[31:16].sub[15:0]) +#define RTOS_ID_n ((tskKERNEL_VERSION_MAJOR << 16) | (tskKERNEL_VERSION_MINOR)) +#define RTOS_ID_s ("FreeRTOS " tskKERNEL_VERSION_NUMBER) -#define osKernelSystemId "FreeRTOS V10.0.1" ///< RTOS identification string +#define osCMSIS 0x20001U ///< API version (main[31:16].sub[15:0]) +#define osCMSIS_FreeRTOS RTOS_ID_n ///< RTOS identification and version (main[31:16].sub[15:0]) + +#define osKernelSystemId RTOS_ID_s ///< RTOS identification string + #define osFeature_MainThread 0 ///< main thread 1=main can be thread, 0=not available #define osFeature_Signals 24U ///< maximum number of Signal Flags available per thread #define osFeature_Semaphore 65535U ///< maximum count for \ref osSemaphoreCreate function @@ -134,7 +143,7 @@ #define osFeature_Pool 0 ///< Memory Pools: 1=available, 0=not available #define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available #define osFeature_MailQ 0 ///< Mail Queues: 1=available, 0=not available - + #if defined(__CC_ARM) #define os_InRegs __value_in_regs #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) @@ -142,18 +151,17 @@ #else #define os_InRegs #endif - + #include "cmsis_os2.h" -#include "FreeRTOS.h" - + #ifdef __cplusplus extern "C" { #endif - - + + // ==== Enumerations, structures, defines ==== - + /// Priority values. #if (osCMSIS < 0x20000U) typedef enum { @@ -173,10 +181,10 @@ typedef enum { /// Entry point of a thread. typedef void (*os_pthread) (void const *argument); - + /// Entry point of a timer call back function. typedef void (*os_ptimer) (void const *argument); - + /// Timer type. #if (osCMSIS < 0x20000U) typedef enum { @@ -186,10 +194,10 @@ typedef enum { #else #define os_timer_type osTimerType_t #endif - + /// Timeout value. #define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. - + /// Status code values returned by CMSIS-RTOS functions. #if (osCMSIS < 0x20000U) typedef enum { @@ -221,48 +229,48 @@ typedef int32_t osStatus; #define osErrorValue (-127) #define osErrorPriority (-128) #endif - - + + // >>> the following data type definitions may be adapted towards a specific RTOS - + /// Thread ID identifies the thread. #if (osCMSIS < 0x20000U) typedef void *osThreadId; #else #define osThreadId osThreadId_t #endif - + /// Timer ID identifies the timer. #if (osCMSIS < 0x20000U) typedef void *osTimerId; #else #define osTimerId osTimerId_t #endif - + /// Mutex ID identifies the mutex. #if (osCMSIS < 0x20000U) typedef void *osMutexId; #else #define osMutexId osMutexId_t #endif - + /// Semaphore ID identifies the semaphore. #if (osCMSIS < 0x20000U) typedef void *osSemaphoreId; #else #define osSemaphoreId osSemaphoreId_t #endif - + /// Pool ID identifies the memory pool. typedef void *osPoolId; - + /// Message ID identifies the message queue. typedef void *osMessageQId; - + /// Mail ID identifies the mail queue. typedef void *osMailQId; - - + + /// Thread Definition structure contains startup information of a thread. #if (osCMSIS < 0x20000U) typedef struct os_thread_def { @@ -277,7 +285,7 @@ typedef struct os_thread_def { osThreadAttr_t attr; ///< thread attributes } osThreadDef_t; #endif - + /// Timer Definition structure contains timer parameters. #if (osCMSIS < 0x20000U) typedef struct os_timer_def { @@ -289,7 +297,7 @@ typedef struct os_timer_def { osTimerAttr_t attr; ///< timer attributes } osTimerDef_t; #endif - + /// Mutex Definition structure contains setup information for a mutex. #if (osCMSIS < 0x20000U) typedef struct os_mutex_def { @@ -298,7 +306,7 @@ typedef struct os_mutex_def { #else #define osMutexDef_t osMutexAttr_t #endif - + /// Semaphore Definition structure contains setup information for a semaphore. #if (osCMSIS < 0x20000U) typedef struct os_semaphore_def { @@ -307,7 +315,7 @@ typedef struct os_semaphore_def { #else #define osSemaphoreDef_t osSemaphoreAttr_t #endif - + /// Definition structure for memory block allocation. #if (osCMSIS < 0x20000U) typedef struct os_pool_def { @@ -322,7 +330,7 @@ typedef struct os_pool_def { osMemoryPoolAttr_t attr; ///< memory pool attributes } osPoolDef_t; #endif - + /// Definition structure for message queue. #if (osCMSIS < 0x20000U) typedef struct os_messageQ_def { @@ -335,7 +343,7 @@ typedef struct os_messageQ_def { osMessageQueueAttr_t attr; ///< message queue attributes } osMessageQDef_t; #endif - + /// Definition structure for mail queue. #if (osCMSIS < 0x20000U) typedef struct os_mailQ_def { @@ -352,8 +360,8 @@ typedef struct os_mailQ_def { osMessageQueueAttr_t mq_attr; ///< message queue attributes } osMailQDef_t; #endif - - + + /// Event structure contains detailed information about an event. typedef struct { osStatus status; ///< status code: event or error information @@ -367,44 +375,44 @@ typedef struct { osMessageQId message_id; ///< message id obtained by \ref osMessageCreate } def; ///< event definition } osEvent; - - + + // ==== Kernel Management Functions ==== - + /// Initialize the RTOS Kernel for creating objects. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osKernelInitialize (void); #endif - + /// Start the RTOS Kernel scheduler. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osKernelStart (void); #endif - + /// Check if the RTOS kernel is already started. /// \return 0 RTOS is not started, 1 RTOS is started. #if (osCMSIS < 0x20000U) int32_t osKernelRunning(void); #endif - + #if (defined(osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available - + /// Get the RTOS kernel system timer counter. -/// \return RTOS kernel system timer as 32-bit value +/// \return RTOS kernel system timer as 32-bit value #if (osCMSIS < 0x20000U) uint32_t osKernelSysTick (void); #else #define osKernelSysTick osKernelGetSysTimerCount #endif - + /// The RTOS kernel system timer frequency in Hz. /// \note Reflects the system timer setting and is typically defined in a configuration file. #if (osCMSIS < 0x20000U) #define osKernelSysTickFrequency 100000000 #endif - + /// Convert a microseconds value to a RTOS kernel system timer value. /// \param microsec time value in microseconds. /// \return time value normalized to the \ref osKernelSysTickFrequency @@ -413,23 +421,23 @@ uint32_t osKernelSysTick (void); #else #define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * osKernelGetSysTimerFreq()) / 1000000) #endif - + #endif // System Timer available - - + + // ==== Thread Management Functions ==== - + /// Create a Thread Definition with function, priority, and stack requirements. /// \param name name of the thread function. /// \param priority initial priority of the thread function. -/// \param instances number of possible thread instances (used to statically allocate memory). +/// \param instances number of possible thread instances. /// \param stacksz stack size (in bytes) requirements for the thread function. #if defined (osObjectsExternal) // object is external #define osThreadDef(name, priority, instances, stacksz) \ extern const osThreadDef_t os_thread_def_##name #else // define the object #define osThreadDef(name, priority, instances, stacksz) \ -static uint32_t os_thread_stack##name[(stacksz)?(((stacksz+3)/4)):1]; \ +static uint64_t os_thread_stack##name[(stacksz)?(((stacksz+7)/8)):1]; \ static StaticTask_t os_thread_cb_##name; \ const osThreadDef_t os_thread_def_##name = \ { (name), \ @@ -437,27 +445,27 @@ const osThreadDef_t os_thread_def_##name = \ (instances == 1) ? (&os_thread_cb_##name) : NULL,\ (instances == 1) ? sizeof(StaticTask_t) : 0U, \ ((stacksz) && (instances == 1)) ? (&os_thread_stack##name) : NULL, \ - 4*((stacksz+3)/4), \ + 8*((stacksz+7)/8), \ (priority), 0U, 0U } } #endif - + /// Access a Thread definition. /// \param name name of the thread definition object. #define osThread(name) \ &os_thread_def_##name - + /// Create a thread and add it to Active Threads and set it to state READY. /// \param[in] thread_def thread definition referenced with \ref osThread. /// \param[in] argument pointer that is passed to the thread function as start argument. /// \return thread ID for reference by other functions or NULL in case of error. osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); - + /// Return the thread ID of the current running thread. /// \return thread ID for reference by other functions or NULL in case of error. #if (osCMSIS < 0x20000U) osThreadId osThreadGetId (void); #endif - + /// Change priority of a thread. /// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. /// \param[in] priority new priority value for the thread function. @@ -465,70 +473,70 @@ osThreadId osThreadGetId (void); #if (osCMSIS < 0x20000U) osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); #endif - + /// Get current priority of a thread. /// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. /// \return current priority value of the specified thread. #if (osCMSIS < 0x20000U) osPriority osThreadGetPriority (osThreadId thread_id); #endif - + /// Pass control to next thread that is in state \b READY. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osThreadYield (void); #endif - + /// Terminate execution of a thread. /// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osThreadTerminate (osThreadId thread_id); #endif - - + + // ==== Signal Management ==== - + /// Set the specified Signal Flags of an active thread. /// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. /// \param[in] signals specifies the signal flags of the thread that should be set. /// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. int32_t osSignalSet (osThreadId thread_id, int32_t signals); - + /// Clear the specified Signal Flags of an active thread. /// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. /// \param[in] signals specifies the signal flags of the thread that shall be cleared. /// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR. int32_t osSignalClear (osThreadId thread_id, int32_t signals); - + /// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. /// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. /// \return event flag information or error code. os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec); - - + + // ==== Generic Wait Functions ==== - + /// Wait for Timeout (Time Delay). /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osDelay (uint32_t millisec); #endif - + #if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available - + /// Wait for Signal, Message, Mail, or Timeout. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out /// \return event that contains signal, message, or mail information or error code. os_InRegs osEvent osWait (uint32_t millisec); - + #endif // Generic Wait available - - + + // ==== Timer Management Functions ==== - + /// Define a Timer object. /// \param name name of the timer object. /// \param function name of the timer call back function. @@ -541,19 +549,19 @@ static StaticTimer_t os_timer_cb_##name; \ const osTimerDef_t os_timer_def_##name = \ { (function), { NULL, 0U, (&os_timer_cb_##name), sizeof(StaticTimer_t) } } #endif - + /// Access a Timer definition. /// \param name name of the timer object. #define osTimer(name) \ &os_timer_def_##name - + /// Create and Initialize a timer. /// \param[in] timer_def timer object referenced with \ref osTimer. /// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. /// \param[in] argument argument to the timer call back function. /// \return timer ID for reference by other functions or NULL in case of error. osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); - + /// Start or restart a timer. /// \param[in] timer_id timer ID obtained by \ref osTimerCreate. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer. @@ -561,24 +569,24 @@ osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void #if (osCMSIS < 0x20000U) osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); #endif - + /// Stop a timer. /// \param[in] timer_id timer ID obtained by \ref osTimerCreate. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osTimerStop (osTimerId timer_id); #endif - + /// Delete a timer. /// \param[in] timer_id timer ID obtained by \ref osTimerCreate. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osTimerDelete (osTimerId timer_id); #endif - - + + // ==== Mutex Management Functions ==== - + /// Define a Mutex. /// \param name name of the mutex object. #if defined (osObjectsExternal) // object is external @@ -590,17 +598,17 @@ static StaticSemaphore_t os_mutex_cb_##name; \ const osMutexDef_t os_mutex_def_##name = \ { NULL, osMutexRecursive | osMutexPrioInherit, (&os_mutex_cb_##name), sizeof(StaticSemaphore_t) } #endif - + /// Access a Mutex definition. /// \param name name of the mutex object. #define osMutex(name) \ &os_mutex_def_##name - + /// Create and Initialize a Mutex object. /// \param[in] mutex_def mutex definition referenced with \ref osMutex. /// \return mutex ID for reference by other functions or NULL in case of error. osMutexId osMutexCreate (const osMutexDef_t *mutex_def); - + /// Wait until a Mutex becomes available. /// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. @@ -610,26 +618,26 @@ osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); #else #define osMutexWait osMutexAcquire #endif - + /// Release a Mutex that was obtained by \ref osMutexWait. /// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osMutexRelease (osMutexId mutex_id); #endif - + /// Delete a Mutex object. /// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osMutexDelete (osMutexId mutex_id); #endif - - + + // ==== Semaphore Management Functions ==== - + #if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) // Semaphore available - + /// Define a Semaphore object. /// \param name name of the semaphore object. #if defined (osObjectsExternal) // object is external @@ -641,45 +649,45 @@ static StaticSemaphore_t os_semaphore_cb_##name; \ const osSemaphoreDef_t os_semaphore_def_##name = \ { NULL, 0U, (&os_semaphore_cb_##name), sizeof(StaticSemaphore_t) } #endif - + /// Access a Semaphore definition. /// \param name name of the semaphore object. #define osSemaphore(name) \ &os_semaphore_def_##name - + /// Create and Initialize a Semaphore object. /// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. /// \param[in] count maximum and initial number of available tokens. /// \return semaphore ID for reference by other functions or NULL in case of error. osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); - + /// Wait until a Semaphore token becomes available. /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. /// \return number of available tokens, or -1 in case of incorrect parameters. int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); - + /// Release a Semaphore token. /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); #endif - + /// Delete a Semaphore object. /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); #endif - + #endif // Semaphore available - - + + // ==== Memory Pool Management Functions ==== #if (defined(osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool available - + /// \brief Define a Memory Pool. /// \param name name of the memory pool. /// \param no maximum number of blocks (objects) in the memory pool. @@ -690,42 +698,42 @@ extern const osPoolDef_t os_pool_def_##name #else // define the object #define osPoolDef(name, no, type) \ const osPoolDef_t os_pool_def_##name = \ -{ (no), sizeof(type), NULL } +{ (no), sizeof(type), {NULL} } #endif - + /// \brief Access a Memory Pool definition. /// \param name name of the memory pool #define osPool(name) \ &os_pool_def_##name - + /// Create and Initialize a Memory Pool object. /// \param[in] pool_def memory pool definition referenced with \ref osPool. /// \return memory pool ID for reference by other functions or NULL in case of error. osPoolId osPoolCreate (const osPoolDef_t *pool_def); - + /// Allocate a memory block from a Memory Pool. /// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. /// \return address of the allocated memory block or NULL in case of no memory available. void *osPoolAlloc (osPoolId pool_id); - + /// Allocate a memory block from a Memory Pool and set memory block to zero. /// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. /// \return address of the allocated memory block or NULL in case of no memory available. void *osPoolCAlloc (osPoolId pool_id); - + /// Return an allocated memory block back to a Memory Pool. /// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. /// \param[in] block address of the allocated memory block to be returned to the memory pool. /// \return status code that indicates the execution status of the function. osStatus osPoolFree (osPoolId pool_id, void *block); - + #endif // Memory Pool available - - + + // ==== Message Queue Management Functions ==== - + #if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queue available - + /// \brief Create a Message Queue Definition. /// \param name name of the queue. /// \param queue_sz maximum number of messages in the queue. @@ -742,38 +750,38 @@ const osMessageQDef_t os_messageQ_def_##name = \ { NULL, 0U, (&os_mq_cb_##name), sizeof(StaticQueue_t), \ (&os_mq_data_##name), sizeof(os_mq_data_##name) } } #endif - + /// \brief Access a Message Queue Definition. /// \param name name of the queue #define osMessageQ(name) \ &os_messageQ_def_##name - + /// Create and Initialize a Message Queue object. /// \param[in] queue_def message queue definition referenced with \ref osMessageQ. /// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. /// \return message queue ID for reference by other functions or NULL in case of error. osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); - + /// Put a Message to a Queue. /// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. /// \param[in] info message information. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. /// \return status code that indicates the execution status of the function. osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); - + /// Get a Message from a Queue or timeout if Queue is empty. /// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. /// \return event information that includes status code. os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); - + #endif // Message Queue available - - + + // ==== Mail Queue Management Functions ==== - + #if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queue available - + /// \brief Create a Mail Queue Definition. /// \param name name of the queue. /// \param queue_sz maximum number of mails in the queue. @@ -786,52 +794,53 @@ extern const osMailQDef_t os_mailQ_def_##name const osMailQDef_t os_mailQ_def_##name = \ { (queue_sz), sizeof(type), NULL } #endif - + /// \brief Access a Mail Queue Definition. /// \param name name of the queue #define osMailQ(name) \ &os_mailQ_def_##name - + /// Create and Initialize a Mail Queue object. /// \param[in] queue_def mail queue definition referenced with \ref osMailQ. /// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. /// \return mail queue ID for reference by other functions or NULL in case of error. osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); - + /// Allocate a memory block for mail from a mail memory pool. /// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out /// \return pointer to memory block that can be filled with mail or NULL in case of error. void *osMailAlloc (osMailQId queue_id, uint32_t millisec); - + /// Allocate a memory block for mail from a mail memory pool and set memory block to zero. /// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out /// \return pointer to memory block that can be filled with mail or NULL in case of error. void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); - + /// Put a Mail into a Queue. /// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. /// \param[in] mail pointer to memory with mail to put into a queue. /// \return status code that indicates the execution status of the function. osStatus osMailPut (osMailQId queue_id, const void *mail); - + /// Get a Mail from a Queue or timeout if Queue is empty. /// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. /// \return event information that includes status code. os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec); - + /// Free a memory block by returning it to a mail memory pool. /// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. /// \param[in] mail pointer to memory block that was obtained with \ref osMailGet. /// \return status code that indicates the execution status of the function. osStatus osMailFree (osMailQId queue_id, void *mail); - + #endif // Mail Queue available - + + #ifdef __cplusplus } #endif - + #endif // CMSIS_OS_H_ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os1.c b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os1.c deleted file mode 100644 index 05ffe36b4..000000000 --- a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os1.c +++ /dev/null @@ -1,368 +0,0 @@ -/*--------------------------------------------------------------------------- - * Portions Copyright (c) 2013-2017 ARM Limited. All rights reserved. - * Portions Copyright © 2017 STMicroelectronics International N.V. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Project: CMSIS-RTOS API V1 - * Title: cmsis_os1.c V1 module file - * - *----------------------------------------------------------------------------*/ - -#include -#include "cmsis_os.h" - -#if (osCMSIS >= 0x20000U) && !defined(os1_Disable) - - -// Thread -#if !defined(os1_Disable_Thread) -osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) { - - if (thread_def == NULL) { - return NULL; - } - return osThreadNew((osThreadFunc_t)thread_def->pthread, argument, &thread_def->attr); -} -#endif - - -// Signals - -#if !defined(os1_Disable_Signal) - -#define SignalMask ((1U< 0U) && (flags < 0x80000000U)) { - event.status = osEventSignal; - event.value.signals = (int32_t)flags; - } else { - switch ((int32_t)flags) { - case osErrorResource: - event.status = osOK; - break; - case osErrorTimeout: - event.status = osEventTimeout; - break; - case osErrorParameter: - event.status = osErrorValue; - break; - default: - event.status = (osStatus)flags; - break; - } - } - return event; -} - -#endif // Signal - - -// Timer -#if !defined(os1_Disable_Timer) -osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) { - - if (timer_def == NULL) { - return NULL; - } - return osTimerNew((osTimerFunc_t)timer_def->ptimer, type, argument, &timer_def->attr); -} -#endif - - -// Mutex -#if !defined(os1_Disable_Mutex) -osMutexId osMutexCreate (const osMutexDef_t *mutex_def) { - - if (mutex_def == NULL) { - return NULL; - } - return osMutexNew(mutex_def); -} -#endif - - -// Semaphore - -#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) && !defined(os1_Disable_Semaphore) - -osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) { - - if (semaphore_def == NULL) { - return NULL; - } - return osSemaphoreNew((uint32_t)count, (uint32_t)count, semaphore_def); -} - -int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) { - osStatus_t status; - uint32_t count; - - status = osSemaphoreAcquire(semaphore_id, millisec); - switch (status) { - case osOK: - count = osSemaphoreGetCount(semaphore_id); - return ((int32_t)count + 1); - case osErrorResource: - case osErrorTimeout: - return 0; - default: - break; - } - return -1; -} - -#endif // Semaphore - - -// Memory Pool - -#if (defined(osFeature_Pool) && (osFeature_Pool != 0))&& !defined(os1_Disable_Pool) - -osPoolId osPoolCreate (const osPoolDef_t *pool_def) { - - if (pool_def == NULL) { - return NULL; - } - return osMemoryPoolNew(pool_def->pool_sz, pool_def->item_sz, &pool_def->attr); -} - -void *osPoolAlloc (osPoolId pool_id) { - return osMemoryPoolAlloc(pool_id, 0U); -} - -void *osPoolCAlloc (osPoolId pool_id) { - void *block; - uint32_t block_size; - - block_size = osMemoryPoolGetBlockSize((osMemoryPoolId_t)pool_id); - if (block_size == 0U) { - return NULL; - } - block = osMemoryPoolAlloc(pool_id, 0U); - if (block != NULL) { - memset(block, 0, block_size); - } - return block; -} - -osStatus osPoolFree (osPoolId pool_id, void *block) { - return osMemoryPoolFree(pool_id, block); -} - -#endif // Memory Pool - - -// Message Queue - -#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) && !defined(os1_Disable_MessageQ) - -osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) { - (void)thread_id; - - if (queue_def == NULL) { - return NULL; - } - return osMessageQueueNew(queue_def->queue_sz, sizeof(uint32_t), &queue_def->attr); -} - -osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) { - return osMessageQueuePut(queue_id, &info, 0U, millisec); -} - -os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) { - osStatus_t status; - osEvent event; - uint32_t message; - - status = osMessageQueueGet(queue_id, &message, NULL, millisec); - switch (status) { - case osOK: - event.status = osEventMessage; - event.value.v = message; - break; - case osErrorResource: - event.status = osOK; - break; - case osErrorTimeout: - event.status = osEventTimeout; - break; - default: - event.status = status; - break; - } - return event; -} - -#endif // Message Queue - - -// Mail Queue - -#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) && !defined(os1_Disable_MailQ) - -typedef struct os_mail_queue_s { - osMemoryPoolId_t mp_id; - osMessageQueueId_t mq_id; -} os_mail_queue_t; - -osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) { - os_mail_queue_t *ptr; - (void)thread_id; - - if (queue_def == NULL) { - return NULL; - } - - ptr = queue_def->mail; - if (ptr == NULL) { - return NULL; - } - - ptr->mp_id = osMemoryPoolNew (queue_def->queue_sz, queue_def->item_sz, &queue_def->mp_attr); - ptr->mq_id = osMessageQueueNew(queue_def->queue_sz, sizeof(void *), &queue_def->mq_attr); - if ((ptr->mp_id == NULL) || (ptr->mq_id == NULL)) { - if (ptr->mp_id != NULL) { - osMemoryPoolDelete(ptr->mp_id); - } - if (ptr->mq_id != NULL) { - osMessageQueueDelete(ptr->mq_id); - } - return NULL; - } - - return ptr; -} - -void *osMailAlloc (osMailQId queue_id, uint32_t millisec) { - os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; - - if (ptr == NULL) { - return NULL; - } - return osMemoryPoolAlloc(ptr->mp_id, millisec); -} - -void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) { - os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; - void *block; - uint32_t block_size; - - if (ptr == NULL) { - return NULL; - } - block_size = osMemoryPoolGetBlockSize(ptr->mp_id); - if (block_size == 0U) { - return NULL; - } - block = osMemoryPoolAlloc(ptr->mp_id, millisec); - if (block != NULL) { - memset(block, 0, block_size); - } - - return block; - -} - -osStatus osMailPut (osMailQId queue_id, const void *mail) { - os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; - - if (ptr == NULL) { - return osErrorParameter; - } - if (mail == NULL) { - return osErrorValue; - } - return osMessageQueuePut(ptr->mq_id, &mail, 0U, 0U); -} - -os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) { - os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; - osStatus_t status; - osEvent event; - void *mail; - - if (ptr == NULL) { - event.status = osErrorParameter; - return event; - } - - status = osMessageQueueGet(ptr->mq_id, &mail, NULL, millisec); - switch (status) { - case osOK: - event.status = osEventMail; - event.value.p = mail; - break; - case osErrorResource: - event.status = osOK; - break; - case osErrorTimeout: - event.status = osEventTimeout; - break; - default: - event.status = status; - break; - } - return event; -} - -osStatus osMailFree (osMailQId queue_id, void *mail) { - os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; - - if (ptr == NULL) { - return osErrorParameter; - } - if (mail == NULL) { - return osErrorValue; - } - return osMemoryPoolFree(ptr->mp_id, mail); -} - -#endif // Mail Queue - - -#endif // osCMSIS diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c index b65b3a029..91fca3041 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c @@ -1,7 +1,6 @@ /* -------------------------------------------------------------------------- - * Portions Copyright © 2017 STMicroelectronics International N.V. All rights reserved. - * Portions Copyright (c) 2013-2017 ARM Limited. All rights reserved. - * -------------------------------------------------------------------------- + * Portions Copyright 2019 STMicroelectronics International N.V. All rights reserved. + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -52,11 +51,14 @@ #if ((__ARM_ARCH_7M__ == 1U) || \ (__ARM_ARCH_7EM__ == 1U) || \ (__ARM_ARCH_8M_MAIN__ == 1U)) -#define IS_IRQ_MASKED() ((__get_PRIMASK() != 0U) || ((KernelState == osKernelRunning) && (__get_BASEPRI() != 0U))) +#define IS_IRQ_MASKED() ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U)) #elif (__ARM_ARCH_6M__ == 1U) -#define IS_IRQ_MASKED() ((__get_PRIMASK() != 0U) && (KernelState == osKernelRunning)) -#elif (__ARM_ARCH_7A__ == 1) -#define IS_IRQ_MASKED() (0U) +#define IS_IRQ_MASKED() (__get_PRIMASK() != 0U) +#elif (__ARM_ARCH_7A__ == 1U) +/* CPSR mask bits */ +#define CPSR_MASKBIT_I 0x80U + +#define IS_IRQ_MASKED() ((__get_CPSR() & CPSR_MASKBIT_I) != 0U) #else #define IS_IRQ_MASKED() (__get_PRIMASK() != 0U) #endif @@ -71,7 +73,7 @@ #define IS_IRQ_MODE() (__get_IPSR() != 0U) #endif -#define IS_IRQ() (IS_IRQ_MODE() || IS_IRQ_MASKED()) +#define IS_IRQ() (IS_IRQ_MODE() || (IS_IRQ_MASKED() && (KernelState == osKernelRunning))) /* Limits */ #define MAX_BITS_TASK_NOTIFY 31U @@ -80,12 +82,12 @@ #define THREAD_FLAGS_INVALID_BITS (~((1UL << MAX_BITS_TASK_NOTIFY) - 1U)) #define EVENT_FLAGS_INVALID_BITS (~((1UL << MAX_BITS_EVENT_GROUPS) - 1U)) -/* Kernel version and identification string definition */ +/* Kernel version and identification string definition (major.minor.rev: mmnnnrrrr dec) */ #define KERNEL_VERSION (((uint32_t)tskKERNEL_VERSION_MAJOR * 10000000UL) | \ ((uint32_t)tskKERNEL_VERSION_MINOR * 10000UL) | \ ((uint32_t)tskKERNEL_VERSION_BUILD * 1UL)) -#define KERNEL_ID "FreeRTOS V10.0.1" +#define KERNEL_ID ("FreeRTOS " tskKERNEL_VERSION_NUMBER) /* Timer callback information structure definition */ typedef struct { @@ -94,27 +96,55 @@ typedef struct { } TimerCallback_t; /* Kernel initialization state */ -static osKernelState_t KernelState; +static osKernelState_t KernelState = osKernelInactive; -/* Heap region definition used by heap_5 variant */ -#if defined(USE_FreeRTOS_HEAP_5) -#if (configAPPLICATION_ALLOCATED_HEAP == 1) /* - The application writer has already defined the array used for the RTOS - heap - probably so it can be placed in a special segment or address. + Heap region definition used by heap_5 variant + + Define configAPPLICATION_ALLOCATED_HEAP as nonzero value in FreeRTOSConfig.h if + heap regions are already defined and vPortDefineHeapRegions is called in application. + + Otherwise vPortDefineHeapRegions will be called by osKernelInitialize using + definition configHEAP_5_REGIONS as parameter. Overriding configHEAP_5_REGIONS + is possible by defining it globally or in FreeRTOSConfig.h. */ - extern uint8_t ucHeap[configTOTAL_HEAP_SIZE]; +#if defined(USE_FREERTOS_HEAP_5) +#if (configAPPLICATION_ALLOCATED_HEAP == 0) + /* + FreeRTOS heap is not defined by the application. + Single region of size configTOTAL_HEAP_SIZE (defined in FreeRTOSConfig.h) + is provided by default. Define configHEAP_5_REGIONS to provide custom + HeapRegion_t array. + */ + #define HEAP_5_REGION_SETUP 1 + + #ifndef configHEAP_5_REGIONS + #define configHEAP_5_REGIONS xHeapRegions + + static uint8_t ucHeap[configTOTAL_HEAP_SIZE]; + + static HeapRegion_t xHeapRegions[] = { + { ucHeap, configTOTAL_HEAP_SIZE }, + { NULL, 0 } + }; + #else + /* Global definition is provided to override default heap array */ + extern HeapRegion_t configHEAP_5_REGIONS[]; + #endif #else - static uint8_t ucHeap[configTOTAL_HEAP_SIZE]; + /* + The application already defined the array used for the FreeRTOS heap and + called vPortDefineHeapRegions to initialize heap. + */ + #define HEAP_5_REGION_SETUP 0 #endif /* configAPPLICATION_ALLOCATED_HEAP */ - -static HeapRegion_t xHeapRegions[] = { - { ucHeap, configTOTAL_HEAP_SIZE }, - { NULL, 0 } -}; -#endif /* USE_FreeRTOS_HEAP_5 */ +#endif /* USE_FREERTOS_HEAP_5 */ #if defined(SysTick) +#undef SysTick_Handler + +/* CMSIS SysTick interrupt handler prototype */ +extern void SysTick_Handler (void); /* FreeRTOS tick timer interrupt handler prototype */ extern void xPortSysTickHandler (void); @@ -125,11 +155,31 @@ void SysTick_Handler (void) { /* Clear overflow flag */ SysTick->CTRL; - /* Call tick handler */ - xPortSysTickHandler(); + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { + /* Call tick handler */ + xPortSysTickHandler(); + } } #endif /* SysTick */ +/* + Setup SVC to reset value. +*/ +__STATIC_INLINE void SVC_Setup (void) { +#if (__ARM_ARCH_7A__ == 0U) + /* Service Call interrupt might be configured before kernel start */ + /* and when its priority is lower or equal to BASEPRI, svc intruction */ + /* causes a Hard Fault. */ + + /* + * the call below has introduced a regression compared to revious release + * The issue was logged under:https://github.com/ARM-software/CMSIS-FreeRTOS/issues/35 + * until it is correctly fixed, the code below is commented + */ +/* NVIC_SetPriority (SVCall_IRQn, 0U); */ +#endif +} + /*---------------------------------------------------------------------------*/ osStatus_t osKernelInitialize (void) { @@ -140,8 +190,8 @@ osStatus_t osKernelInitialize (void) { } else { if (KernelState == osKernelInactive) { - #if defined(USE_FreeRTOS_HEAP_5) - vPortDefineHeapRegions (xHeapRegions); + #if defined(USE_FREERTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) + vPortDefineHeapRegions (configHEAP_5_REGIONS); #endif KernelState = osKernelReady; stat = osOK; @@ -156,6 +206,7 @@ osStatus_t osKernelInitialize (void) { osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) { if (version != NULL) { + /* Version encoding is major.minor.rev: mmnnnrrrr dec */ version->api = KERNEL_VERSION; version->kernel = KERNEL_VERSION; } @@ -203,7 +254,11 @@ osStatus_t osKernelStart (void) { } else { if (KernelState == osKernelReady) { + /* Ensure SVC priority is at the reset value */ + SVC_Setup(); + /* Change state to enable IRQ masking check */ KernelState = osKernelRunning; + /* Start the kernel scheduler */ vTaskStartScheduler(); stat = osOK; } else { @@ -326,15 +381,18 @@ uint32_t osKernelGetTickFreq (void) { } uint32_t osKernelGetSysTimerCount (void) { + uint32_t irqmask = IS_IRQ_MASKED(); TickType_t ticks; uint32_t val; - portDISABLE_INTERRUPTS(); + __disable_irq(); ticks = xTaskGetTickCount(); val = ticks * ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); - portENABLE_INTERRUPTS(); + if (irqmask == 0U) { + __enable_irq(); + } return (val); } @@ -346,7 +404,6 @@ uint32_t osKernelGetSysTimerFreq (void) { /*---------------------------------------------------------------------------*/ osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { - char empty; const char *name; uint32_t stack; TaskHandle_t hTask; @@ -359,9 +416,8 @@ osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAtt stack = configMINIMAL_STACK_SIZE; prio = (UBaseType_t)osPriorityNormal; - empty = '\0'; - name = ∅ - mem = -1; + name = NULL; + mem = -1; if (attr != NULL) { if (attr->name != NULL) { @@ -427,11 +483,7 @@ const char *osThreadGetName (osThreadId_t thread_id) { osThreadId_t osThreadGetId (void) { osThreadId_t id; - if (IS_IRQ()) { - id = NULL; - } else { - id = (osThreadId_t)xTaskGetCurrentTaskHandle(); - } + id = (osThreadId_t)xTaskGetCurrentTaskHandle(); return (id); } @@ -471,16 +523,6 @@ uint32_t osThreadGetStackSpace (osThreadId_t thread_id) { return (sz); } -uint32_t osThreadGetStackSize (osThreadId_t thread_id) { - /* - * this implmentation is not correct. - * this function is implmented to avoid link errors (undefined reference) - * Bug reported : https://github.com/ARM-software/CMSIS-FreeRTOS/issues/14 - */ - (void) thread_id; - return 0; -} - osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) { TaskHandle_t hTask = (TaskHandle_t)thread_id; osStatus_t stat; @@ -806,7 +848,7 @@ osStatus_t osDelay (uint32_t ticks) { } osStatus_t osDelayUntil (uint32_t ticks) { - TickType_t tcnt; + TickType_t tcnt, delay; osStatus_t stat; if (IS_IRQ()) { @@ -816,7 +858,18 @@ osStatus_t osDelayUntil (uint32_t ticks) { stat = osOK; tcnt = xTaskGetTickCount(); - vTaskDelayUntil (&tcnt, (TickType_t)(ticks - tcnt)); + /* Determine remaining number of ticks to delay */ + delay = (TickType_t)ticks - tcnt; + + /* Check if target tick has not expired */ + if((delay != 0U) && (0 == (delay >> (8 * sizeof(TickType_t) - 1)))) { + vTaskDelayUntil (&tcnt, delay); + } + else + { + /* No delay or already expired */ + stat = osErrorParameter; + } } return (stat); @@ -1043,7 +1096,7 @@ uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) { else if (IS_IRQ()) { yield = pdFALSE; - if (xEventGroupSetBitsFromISR (hEventGroup, (EventBits_t)flags, &yield) != pdFAIL) { + if (xEventGroupSetBitsFromISR (hEventGroup, (EventBits_t)flags, &yield) == pdFAIL) { rflags = (uint32_t)osErrorResource; } else { rflags = flags; @@ -1416,7 +1469,7 @@ osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, cons hSemaphore = xSemaphoreCreateCounting (max_count, initial_count); } } - + #if (configQUEUE_REGISTRY_SIZE > 0) if (hSemaphore != NULL) { if (attr != NULL) { diff --git a/Middlewares/Third_Party/FreeRTOS/Source/croutine.c b/Middlewares/Third_Party/FreeRTOS/Source/croutine.c index b71588451..56c8ac290 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/croutine.c +++ b/Middlewares/Third_Party/FreeRTOS/Source/croutine.c @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -260,7 +260,7 @@ CRCB_t *pxCRCB; ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) ); /* Is the co-routine waiting on an event also? */ - if( pxCRCB->xEventListItem.pvContainer ) + if( pxCRCB->xEventListItem.pxContainer ) { ( void ) uxListRemove( &( pxCRCB->xEventListItem ) ); } diff --git a/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c b/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c index 14d7b024e..65a5ff259 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c +++ b/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -39,11 +39,11 @@ task.h is included from an application file. */ #include "timers.h" #include "event_groups.h" -/* Lint e961 and e750 are suppressed as a MISRA exception justified because the -MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the -header files above, but not in this file, in order to generate the correct -privileged Vs unprivileged linkage and placement. */ -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */ +/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified +because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined +for the header files above, but not in this file, in order to generate the +correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */ /* The following bit fields convey control information in a task's event list item value. It is important they don't clash with the @@ -60,7 +60,7 @@ taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */ #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL #endif -typedef struct xEventGroupDefinition +typedef struct EventGroupDef_t { EventBits_t uxEventBits; List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */ @@ -104,11 +104,11 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, co event group structure. */ volatile size_t xSize = sizeof( StaticEventGroup_t ); configASSERT( xSize == sizeof( EventGroup_t ) ); - } + } /*lint !e529 xSize is referenced if configASSERT() is defined. */ #endif /* configASSERT_DEFINED */ /* The user has provided a statically allocated event group - use it. */ - pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 EventGroup_t and StaticEventGroup_t are guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ + pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ if( pxEventBits != NULL ) { @@ -128,10 +128,13 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, co } else { + /* xEventGroupCreateStatic should only ever be called with + pxEventGroupBuffer pointing to a pre-allocated (compile time + allocated) StaticEventGroup_t variable. */ traceEVENT_GROUP_CREATE_FAILED(); } - return ( EventGroupHandle_t ) pxEventBits; + return pxEventBits; } #endif /* configSUPPORT_STATIC_ALLOCATION */ @@ -143,8 +146,20 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, co { EventGroup_t *pxEventBits; - /* Allocate the event group. */ - pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); + /* Allocate the event group. Justification for MISRA deviation as + follows: pvPortMalloc() always ensures returned memory blocks are + aligned per the requirements of the MCU stack. In this case + pvPortMalloc() must return a pointer that is guaranteed to meet the + alignment requirements of the EventGroup_t structure - which (if you + follow it through) is the alignment requirements of the TickType_t type + (EventBits_t being of TickType_t itself). Therefore, whenever the + stack alignment requirements are greater than or equal to the + TickType_t alignment requirements the cast is safe. In other cases, + where the natural word size of the architecture is less than + sizeof( TickType_t ), the TickType_t variables will be accessed in two + or more reads operations, and the alignment requirements is only that + of each individual read. */ + pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */ if( pxEventBits != NULL ) { @@ -164,10 +179,10 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, co } else { - traceEVENT_GROUP_CREATE_FAILED(); + traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */ } - return ( EventGroupHandle_t ) pxEventBits; + return pxEventBits; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ @@ -176,7 +191,7 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, co EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) { EventBits_t uxOriginalBitValue, uxReturn; -EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventGroup_t *pxEventBits = xEventGroup; BaseType_t xAlreadyYielded; BaseType_t xTimeoutOccurred = pdFALSE; @@ -295,7 +310,7 @@ BaseType_t xTimeoutOccurred = pdFALSE; EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) { -EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventGroup_t *pxEventBits = xEventGroup; EventBits_t uxReturn, uxControlBits = 0; BaseType_t xWaitConditionMet, xAlreadyYielded; BaseType_t xTimeoutOccurred = pdFALSE; @@ -445,7 +460,7 @@ BaseType_t xTimeoutOccurred = pdFALSE; EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) { -EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventGroup_t *pxEventBits = xEventGroup; EventBits_t uxReturn; /* Check the user is not attempting to clear the bits used by the kernel @@ -477,7 +492,7 @@ EventBits_t uxReturn; BaseType_t xReturn; traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ); - xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ return xReturn; } @@ -488,7 +503,7 @@ EventBits_t uxReturn; EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) { UBaseType_t uxSavedInterruptStatus; -EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventGroup_t const * const pxEventBits = xEventGroup; EventBits_t uxReturn; uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); @@ -498,16 +513,16 @@ EventBits_t uxReturn; portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return uxReturn; -} +} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */ /*-----------------------------------------------------------*/ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) { ListItem_t *pxListItem, *pxNext; ListItem_t const *pxListEnd; -List_t *pxList; +List_t const * pxList; EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits; -EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventGroup_t *pxEventBits = xEventGroup; BaseType_t xMatchFound = pdFALSE; /* Check the user is not attempting to set the bits used by the kernel @@ -516,7 +531,7 @@ BaseType_t xMatchFound = pdFALSE; configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); pxList = &( pxEventBits->xTasksWaitingForBits ); - pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ vTaskSuspendAll(); { traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ); @@ -597,7 +612,7 @@ BaseType_t xMatchFound = pdFALSE; void vEventGroupDelete( EventGroupHandle_t xEventGroup ) { -EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventGroup_t *pxEventBits = xEventGroup; const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); vTaskSuspendAll(); @@ -641,7 +656,7 @@ const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); an interrupt. */ void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) { - ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); + ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ } /*-----------------------------------------------------------*/ @@ -649,7 +664,7 @@ void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet an interrupt. */ void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) { - ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); + ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ } /*-----------------------------------------------------------*/ @@ -695,7 +710,7 @@ BaseType_t xWaitConditionMet = pdFALSE; BaseType_t xReturn; traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ); - xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ return xReturn; } @@ -708,7 +723,7 @@ BaseType_t xWaitConditionMet = pdFALSE; UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) { UBaseType_t xReturn; - EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; + EventGroup_t const *pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ if( xEventGroup == NULL ) { @@ -729,7 +744,7 @@ BaseType_t xWaitConditionMet = pdFALSE; void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber ) { - ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; + ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ } #endif /* configUSE_TRACE_FACILITY */ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h b/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h index 78d176a03..9d09d91af 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -156,6 +156,10 @@ extern "C" { #define INCLUDE_uxTaskGetStackHighWaterMark 0 #endif +#ifndef INCLUDE_uxTaskGetStackHighWaterMark2 + #define INCLUDE_uxTaskGetStackHighWaterMark2 0 +#endif + #ifndef INCLUDE_eTaskGetState #define INCLUDE_eTaskGetState 0 #endif @@ -237,6 +241,10 @@ extern "C" { #define configASSERT_DEFINED 1 #endif +#ifndef portMEMORY_BARRIER + #define portMEMORY_BARRIER() +#endif + /* The timers module relies on xTaskGetSchedulerState(). */ #if configUSE_TIMERS == 1 @@ -758,8 +766,12 @@ extern "C" { #define portTASK_USES_FLOATING_POINT() #endif -#ifndef portTASK_CALLS_SECURE_FUNCTIONS - #define portTASK_CALLS_SECURE_FUNCTIONS() +#ifndef portALLOCATE_SECURE_CONTEXT + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) +#endif + +#ifndef portDONT_DISCARD + #define portDONT_DISCARD #endif #ifndef configUSE_TIME_SLICING @@ -806,6 +818,10 @@ extern "C" { #define configUSE_TASK_NOTIFICATIONS 1 #endif +#ifndef configUSE_POSIX_ERRNO + #define configUSE_POSIX_ERRNO 0 +#endif + #ifndef portTICK_TYPE_IS_ATOMIC #define portTICK_TYPE_IS_ATOMIC 0 #endif @@ -826,6 +842,13 @@ extern "C" { #define configSTACK_DEPTH_TYPE uint16_t #endif +#ifndef configMESSAGE_BUFFER_LENGTH_TYPE + /* Defaults to size_t for backward compatibility, but can be overridden + in FreeRTOSConfig.h if lengths will always be less than the number of bytes + in a size_t. */ + #define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#endif + /* Sanity check the configuration. */ #if( configUSE_TICKLESS_IDLE != 0 ) #if( INCLUDE_vTaskSuspend != 1 ) @@ -921,6 +944,10 @@ V8 if desired. */ #define pdTASK_CODE TaskFunction_t #define xListItem ListItem_t #define xList List_t + + /* For libraries that break the list data hiding, and access list structure + members directly (which is not supposed to be done). */ + #define pxContainer pvContainer #endif /* configENABLE_BACKWARD_COMPATIBILITY */ #if( configUSE_ALTERNATIVE_API != 0 ) @@ -935,6 +962,75 @@ point support. */ #define configUSE_TASK_FPU_SUPPORT 1 #endif +/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is +currently used in ARMv8M ports. */ +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif + +/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is +currently used in ARMv8M ports. */ +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif + +/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it. +This is currently used in ARMv8M ports. */ +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 1 +#endif + +/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on +the Secure Side only. */ +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 0 +#endif + +/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using + * dynamically allocated RAM, in which case when any task is deleted it is known + * that both the task's stack and TCB need to be freed. Sometimes the + * FreeRTOSConfig.h settings only allow a task to be created using statically + * allocated RAM, in which case when any task is deleted it is known that neither + * the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h + * settings allow a task to be created using either statically or dynamically + * allocated RAM, in which case a member of the TCB is used to record whether the + * stack and/or TCB were allocated statically or dynamically, so when a task is + * deleted the RAM that was allocated dynamically is freed again and no attempt is + * made to free the RAM that was allocated statically. + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a + * task to be created using either statically or dynamically allocated RAM. Note + * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with + * a statically allocated stack and a dynamically allocated TCB. + * + * The following table lists various combinations of portUSING_MPU_WRAPPERS, + * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and + * when it is possible to have both static and dynamic allocation: + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | MPU | Dynamic | Static | Available Functions | Possible Allocations | Both Dynamic and | Need Free | + * | | | | | | Static Possible | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | 0 | 0 | 1 | xTaskCreateStatic | TCB - Static, Stack - Static | No | No | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 0 | xTaskCreate | TCB - Dynamic, Stack - Dynamic | No | Yes | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic | 2. TCB - Static, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 0 | 1 | xTaskCreateStatic, | TCB - Static, Stack - Static | No | No | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 0 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateRestricted | 2. TCB - Dynamic, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic, | 2. TCB - Dynamic, Stack - Static | | | + * | | | | xTaskCreateRestricted, | 3. TCB - Static, Stack - Static | | | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + */ +#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \ + ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) ) + /* * In line with software engineering best practice, FreeRTOS implements a strict * data hiding policy, so the real structures used by FreeRTOS to maintain the @@ -947,25 +1043,40 @@ point support. */ */ struct xSTATIC_LIST_ITEM { - TickType_t xDummy1; - void *pvDummy2[ 4 ]; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void *pvDummy3[ 4 ]; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy4; + #endif }; typedef struct xSTATIC_LIST_ITEM StaticListItem_t; /* See the comments above the struct xSTATIC_LIST_ITEM definition. */ struct xSTATIC_MINI_LIST_ITEM { - TickType_t xDummy1; - void *pvDummy2[ 2 ]; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void *pvDummy3[ 2 ]; }; typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t; /* See the comments above the struct xSTATIC_LIST_ITEM definition. */ typedef struct xSTATIC_LIST { - UBaseType_t uxDummy1; - void *pvDummy2; - StaticMiniListItem_t xDummy3; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + UBaseType_t uxDummy2; + void *pvDummy3; + StaticMiniListItem_t xDummy4; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy5; + #endif } StaticList_t; /* @@ -1019,14 +1130,16 @@ typedef struct xSTATIC_TCB uint32_t ulDummy18; uint8_t ucDummy19; #endif - #if( ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) || ( portUSING_MPU_WRAPPERS == 1 ) ) + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) uint8_t uxDummy20; #endif #if( INCLUDE_xTaskAbortDelay == 1 ) uint8_t ucDummy21; #endif - + #if ( configUSE_POSIX_ERRNO == 1 ) + int iDummy22; + #endif } StaticTask_t; /* @@ -1121,15 +1234,12 @@ typedef struct xSTATIC_TIMER void *pvDummy1; StaticListItem_t xDummy2; TickType_t xDummy3; - UBaseType_t uxDummy4; - void *pvDummy5[ 2 ]; + void *pvDummy5; + TaskFunction_t pvDummy6; #if( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxDummy6; - #endif - - #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) - uint8_t ucDummy7; + UBaseType_t uxDummy7; #endif + uint8_t ucDummy8; } StaticTimer_t; diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOSConfig_template.h b/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOSConfig_template.h index 0bef5a46d..e0dff5cb2 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOSConfig_template.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOSConfig_template.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h b/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h index 534f00456..3ed8b22d1 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h b/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h index f4c54d2ea..8b3b41b90 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h b/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h index 1125673c7..9cece988f 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h b/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h index 69ec2e60a..1f38bdb76 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -78,7 +78,8 @@ extern "C" { * \defgroup EventGroupHandle_t EventGroupHandle_t * \ingroup EventGroup */ -typedef void * EventGroupHandle_t; +struct EventGroupDef_t; +typedef struct EventGroupDef_t * EventGroupHandle_t; /* * The type that holds event bits always matches TickType_t - therefore the @@ -404,7 +405,7 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBit * \ingroup EventGroup */ #if( configUSE_TRACE_FACILITY == 1 ) - BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; #else #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ) #endif diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/list.h b/Middlewares/Third_Party/FreeRTOS/Source/include/list.h index 4a3afa16d..2fb6775ff 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/list.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/list.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -136,6 +136,7 @@ use of FreeRTOS.*/ /* * Definition of the only type of object that a list can contain. */ +struct xLIST; struct xLIST_ITEM { listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ @@ -143,7 +144,7 @@ struct xLIST_ITEM struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */ struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */ void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ - void * configLIST_VOLATILE pvContainer; /*< Pointer to the list in which this list item is placed (if any). */ + struct xLIST * configLIST_VOLATILE pxContainer; /*< Pointer to the list in which this list item is placed (if any). */ listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ }; typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ @@ -246,7 +247,7 @@ typedef struct xLIST * \page listLIST_IS_EMPTY listLIST_IS_EMPTY * \ingroup LinkedList */ -#define listLIST_IS_EMPTY( pxList ) ( ( BaseType_t ) ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ) +#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE ) /* * Access macro to return the number of items in the list. @@ -314,7 +315,7 @@ List_t * const pxConstList = ( pxList ); \ * @param pxListItem The list item we want to know if is in the list. * @return pdTRUE if the list item is in the list, otherwise pdFALSE. */ -#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( BaseType_t ) ( ( pxListItem )->pvContainer == ( void * ) ( pxList ) ) ) +#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) ) /* * Return the list a list item is contained within (referenced from). @@ -322,7 +323,7 @@ List_t * const pxConstList = ( pxList ); \ * @param pxListItem The list item being queried. * @return A pointer to the List_t object that references the pxListItem */ -#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pvContainer ) +#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer ) /* * This provides a crude means of knowing if a list has been initialised, as diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h b/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h index 91e34fa17..cfa08cb93 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -692,6 +692,26 @@ size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) ); * \ingroup MessageBufferManagement */ #define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) +#define xMessageBufferSpacesAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */ + +/** + * message_buffer.h + 
    + size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
+
    + * Returns the length (in bytes) of the next message in a message buffer. + * Useful if xMessageBufferReceive() returned 0 because the size of the buffer + * passed into xMessageBufferReceive() was too small to hold the next message. + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return The length (in bytes) of the next message in the message buffer, or 0 + * if the message buffer is empty. + * + * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes + * \ingroup MessageBufferManagement + */ +#define xMessageBufferNextLengthBytes( xMessageBuffer ) xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION; /** * message_buffer.h diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h index e2c89ab81..5d7490719 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -38,116 +38,118 @@ #define MPU_PROTOTYPES_H /* MPU versions of tasks.h API functions. */ -BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ); -TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ); -BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ); -BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ); -void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ); -void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ); -void MPU_vTaskDelay( const TickType_t xTicksToDelay ); -void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ); -BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ); -UBaseType_t MPU_uxTaskPriorityGet( TaskHandle_t xTask ); -eTaskState MPU_eTaskGetState( TaskHandle_t xTask ); -void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ); -void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ); -void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ); -void MPU_vTaskResume( TaskHandle_t xTaskToResume ); -void MPU_vTaskStartScheduler( void ); -void MPU_vTaskSuspendAll( void ); -BaseType_t MPU_xTaskResumeAll( void ); -TickType_t MPU_xTaskGetTickCount( void ); -UBaseType_t MPU_uxTaskGetNumberOfTasks( void ); -char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ); -TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ); -UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ); -void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ); -TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ); -void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ); -void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ); -BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ); -TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ); -UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ); -void MPU_vTaskList( char * pcWriteBuffer ); -void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ); -BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ); -BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ); -uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ); -BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ); -BaseType_t MPU_xTaskIncrementTick( void ); -TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ); -void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ); -BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ); -void MPU_vTaskMissedYield( void ); -BaseType_t MPU_xTaskGetSchedulerState( void ); +BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL; +char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL; +TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL; +void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL; /* MPU versions of queue.h API functions. */ -BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ); -BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ); -BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ); -BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ); -UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ); -UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ); -void MPU_vQueueDelete( QueueHandle_t xQueue ); -QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ); -QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ); -QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ); -QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ); -void* MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ); -BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ); -BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ); -void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ); -void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ); -const char * MPU_pcQueueGetName( QueueHandle_t xQueue ); -QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ); -QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ); -QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ); -BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ); -BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ); -QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ); -BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ); -void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ); -UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ); -uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ); +BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL; +QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; /* MPU versions of timers.h API functions. */ -TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ); -TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ); -void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ); -void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ); -BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ); -TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ); -BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ); -const char * MPU_pcTimerGetName( TimerHandle_t xTimer ); -TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ); -TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ); -BaseType_t MPU_xTimerCreateTimerTask( void ); -BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ); +TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL; +TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL; +void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; /* MPU versions of event_group.h API functions. */ -EventGroupHandle_t MPU_xEventGroupCreate( void ); -EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ); -EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ); -EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ); -EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ); -EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ); -void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ); -UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ); +EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL; +EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL; /* MPU versions of message/stream_buffer.h API functions. */ -size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ); -size_t MPU_xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken ); -size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ); -size_t MPU_xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken ); -void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ); -BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ); -BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ); -BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ); -size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ); -size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ); -BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ); -StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ); -StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ); +size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL; +StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL; +StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL; diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h index eb326e764..711393f6a 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -67,6 +67,7 @@ only for ports that are using the MPU. */ #define pcTaskGetName MPU_pcTaskGetName #define xTaskGetHandle MPU_xTaskGetHandle #define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark + #define uxTaskGetStackHighWaterMark2 MPU_uxTaskGetStackHighWaterMark2 #define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag #define xTaskGetApplicationTaskTag MPU_xTaskGetApplicationTaskTag #define vTaskSetThreadLocalStoragePointer MPU_vTaskSetThreadLocalStoragePointer @@ -76,6 +77,7 @@ only for ports that are using the MPU. */ #define uxTaskGetSystemState MPU_uxTaskGetSystemState #define vTaskList MPU_vTaskList #define vTaskGetRunTimeStats MPU_vTaskGetRunTimeStats + #define xTaskGetIdleRunTimeCounter MPU_xTaskGetIdleRunTimeCounter #define xTaskGenericNotify MPU_xTaskGenericNotify #define xTaskNotifyWait MPU_xTaskNotifyWait #define ulTaskNotifyTake MPU_ulTaskNotifyTake @@ -124,6 +126,7 @@ only for ports that are using the MPU. */ #define xTimerGetTimerDaemonTaskHandle MPU_xTimerGetTimerDaemonTaskHandle #define xTimerPendFunctionCall MPU_xTimerPendFunctionCall #define pcTimerGetName MPU_pcTimerGetName + #define vTimerSetReloadMode MPU_vTimerSetReloadMode #define xTimerGetPeriod MPU_xTimerGetPeriod #define xTimerGetExpiryTime MPU_xTimerGetExpiryTime #define xTimerGenericCommand MPU_xTimerGenericCommand @@ -140,9 +143,8 @@ only for ports that are using the MPU. */ /* Map standard message/stream_buffer.h API functions to the MPU equivalents. */ #define xStreamBufferSend MPU_xStreamBufferSend - #define xStreamBufferSendFromISR MPU_xStreamBufferSendFromISR #define xStreamBufferReceive MPU_xStreamBufferReceive - #define xStreamBufferReceiveFromISR MPU_xStreamBufferReceiveFromISR + #define xStreamBufferNextMessageLengthBytes MPU_xStreamBufferNextMessageLengthBytes #define vStreamBufferDelete MPU_vStreamBufferDelete #define xStreamBufferIsFull MPU_xStreamBufferIsFull #define xStreamBufferIsEmpty MPU_xStreamBufferIsEmpty @@ -159,12 +161,14 @@ only for ports that are using the MPU. */ (useful when using statically allocated objects). */ #define PRIVILEGED_FUNCTION #define PRIVILEGED_DATA __attribute__((section("privileged_data"))) + #define FREERTOS_SYSTEM_CALL #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ /* Ensure API functions go in the privileged execution section. */ #define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions"))) #define PRIVILEGED_DATA __attribute__((section("privileged_data"))) + #define FREERTOS_SYSTEM_CALL __attribute__((section( "freertos_system_calls"))) #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ @@ -172,6 +176,7 @@ only for ports that are using the MPU. */ #define PRIVILEGED_FUNCTION #define PRIVILEGED_DATA + #define FREERTOS_SYSTEM_CALL #define portUSING_MPU_WRAPPERS 0 #endif /* portUSING_MPU_WRAPPERS */ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h b/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h index 3d0ef0a62..59e816947 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -84,6 +84,14 @@ must be set in the compiler's include path. */ #define portNUM_CONFIGURABLE_REGIONS 1 #endif +#ifndef portHAS_STACK_OVERFLOW_CHECKING + #define portHAS_STACK_OVERFLOW_CHECKING 0 +#endif + +#ifndef portARCH_NAME + #define portARCH_NAME NULL +#endif + #ifdef __cplusplus extern "C" { #endif @@ -97,9 +105,17 @@ extern "C" { * */ #if( portUSING_MPU_WRAPPERS == 1 ) - StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + #if( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + #else + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + #endif #else - StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION; + #if( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION; + #else + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION; + #endif #endif /* Used by heap_5.c. */ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h b/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h index 27337a898..e0458619e 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h b/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h index a23fa1e62..3b9da937a 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -37,27 +37,29 @@ extern "C" { #endif +#include "task.h" /** * Type by which queues are referenced. For example, a call to xQueueCreate() * returns an QueueHandle_t variable that can then be used as a parameter to * xQueueSend(), xQueueReceive(), etc. */ -typedef void * QueueHandle_t; +struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */ +typedef struct QueueDefinition * QueueHandle_t; /** * Type by which queue sets are referenced. For example, a call to * xQueueCreateSet() returns an xQueueSet variable that can then be used as a * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc. */ -typedef void * QueueSetHandle_t; +typedef struct QueueDefinition * QueueSetHandle_t; /** * Queue sets can contain both queues and semaphores, so the * QueueSetMemberHandle_t is defined as a type to be used where a parameter or * return value can be either an QueueHandle_t or an SemaphoreHandle_t. */ -typedef void * QueueSetMemberHandle_t; +typedef struct QueueDefinition * QueueSetMemberHandle_t; /* For internal use only. */ #define queueSEND_TO_BACK ( ( BaseType_t ) 0 ) @@ -1414,15 +1416,15 @@ QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION; QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION; BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; -void* xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; -void* xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; +TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; +TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; /* * For internal use only. Use xSemaphoreTakeMutexRecursive() or * xSemaphoreGiveMutexRecursive() instead of calling these functions directly. */ BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; -BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION; /* * Reset a queue back to its original empty state. The return value is now @@ -1453,7 +1455,7 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION * preferably in ROM/Flash), not on the stack. */ #if( configQUEUE_REGISTRY_SIZE > 0 ) - void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ #endif /* diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h b/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h index e603b4afc..2c106eac0 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h b/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h index 79a83ea37..18406bbf9 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -82,10 +82,10 @@ const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \ const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \ \ - if( ( pulStack[ 0 ] != ulCheckValue ) || \ - ( pulStack[ 1 ] != ulCheckValue ) || \ - ( pulStack[ 2 ] != ulCheckValue ) || \ - ( pulStack[ 3 ] != ulCheckValue ) ) \ + if( ( pulStack[ 0 ] != ulCheckValue ) || \ + ( pulStack[ 1 ] != ulCheckValue ) || \ + ( pulStack[ 2 ] != ulCheckValue ) || \ + ( pulStack[ 3 ] != ulCheckValue ) ) \ { \ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ } \ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h b/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h index 5418e05ba..0f00119ee 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -61,7 +61,8 @@ extern "C" { * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(), * etc. */ -typedef void * StreamBufferHandle_t; +struct StreamBufferDef_t; +typedef struct StreamBufferDef_t * StreamBufferHandle_t; /** @@ -220,7 +221,7 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ); -
    +
    * * Sends bytes to a stream buffer. The bytes are copied into the stream buffer. * @@ -317,7 +318,7 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, BaseType_t *pxHigherPriorityTaskWoken ); -
    +
    * * Interrupt safe version of the API function that sends a stream of bytes to * the stream buffer. @@ -839,6 +840,8 @@ StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION; +size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + #if( configUSE_TRACE_FACILITY == 1 ) void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION; UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/task.h b/Middlewares/Third_Party/FreeRTOS/Source/include/task.h index d0ee06811..f3cf118f8 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/task.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/task.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -43,10 +43,18 @@ extern "C" { * MACROS AND DEFINITIONS *----------------------------------------------------------*/ -#define tskKERNEL_VERSION_NUMBER "V10.0.1" +#define tskKERNEL_VERSION_NUMBER "V10.2.0" #define tskKERNEL_VERSION_MAJOR 10 -#define tskKERNEL_VERSION_MINOR 0 -#define tskKERNEL_VERSION_BUILD 1 +#define tskKERNEL_VERSION_MINOR 2 +#define tskKERNEL_VERSION_BUILD 0 + +/* MPU region parameters passed in ulParameters + * of MemoryRegion_t struct. */ +#define tskMPU_REGION_READ_ONLY ( 1UL << 0UL ) +#define tskMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define tskMPU_REGION_EXECUTE_NEVER ( 1UL << 2UL ) +#define tskMPU_REGION_NORMAL_MEMORY ( 1UL << 3UL ) +#define tskMPU_REGION_DEVICE_MEMORY ( 1UL << 4UL ) /** * task. h @@ -58,7 +66,8 @@ extern "C" { * \defgroup TaskHandle_t TaskHandle_t * \ingroup Tasks */ -typedef void * TaskHandle_t; +struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +typedef struct tskTaskControlBlock* TaskHandle_t; /* * Defines the prototype to which the application task hook function must @@ -74,7 +83,7 @@ typedef enum eBlocked, /* The task being queried is in the Blocked state. */ eSuspended, /* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */ eDeleted, /* The task being queried has been deleted, but its TCB has not yet been freed. */ - eInvalid /* Used as an 'invalid state' value. */ + eInvalid /* Used as an 'invalid state' value. */ } eTaskState; /* Actions that can be performed when vTaskNotify() is called. */ @@ -113,7 +122,7 @@ typedef struct xTASK_PARAMETERS { TaskFunction_t pvTaskCode; const char * const pcName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ - uint16_t usStackDepth; + configSTACK_DEPTH_TYPE usStackDepth; void *pvParameters; UBaseType_t uxPriority; StackType_t *puxStackBuffer; @@ -135,7 +144,7 @@ typedef struct xTASK_STATUS UBaseType_t uxBasePriority; /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex. Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */ uint32_t ulRunTimeCounter; /* The total run time allocated to the task so far, as defined by the run time stats clock. See http://www.freertos.org/rtos-run-time-stats.html. Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */ StackType_t *pxStackBase; /* Points to the lowest address of the task's stack area. */ - uint16_t usStackHighWaterMark; /* The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack. */ + configSTACK_DEPTH_TYPE usStackHighWaterMark; /* The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack. */ } TaskStatus_t; /* Possible return values for eTaskConfirmSleepModeStatus(). */ @@ -375,9 +384,9 @@ is used in assert() statements. */ * memory to be allocated dynamically. * * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will - * be created and pdPASS is returned. If either pxStackBuffer or pxTaskBuffer - * are NULL then the task will not be created and - * errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY is returned. + * be created and a handle to the created task is returned. If either + * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and + * NULL is returned. * * Example usage: 
    @@ -834,7 +843,7 @@ BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
 
 /**
  * task. h
- * 
    UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask );
    
+ * 
    UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );
    
  *
  * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
  * See the configuration section for more information.
@@ -877,15 +886,15 @@ BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
  * \defgroup uxTaskPriorityGet uxTaskPriorityGet
  * \ingroup TaskCtrl
  */
-UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
 
 /**
  * task. h
- * 
    UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask );
    
+ * 
    UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );
    
  *
  * A version of uxTaskPriorityGet() that can be used from an ISR.
  */
-UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
 
 /**
  * task. h
@@ -1412,6 +1421,12 @@ TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*
  * a value of 1 means 4 bytes) since the task started.  The smaller the returned
  * number the closer the task has come to overflowing its stack.
  *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
  * @param xTask Handle of the task associated with the stack to be checked.
  * Set xTask to NULL to check the stack of the calling task.
  *
@@ -1421,6 +1436,33 @@ TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*
  */
 UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
 
+/**
+ * task.h
+ * 
    configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );
    
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
 /* When using trace macros it is sometimes necessary to include task.h before
 FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
 so the following two prototypes will cause a compilation error.  This can be
@@ -1443,9 +1485,20 @@ constant. */
 		 * task.h
 		 * 
    void xTaskGetApplicationTaskTag( TaskHandle_t xTask );
    
 		 *
-		 * Returns the pxHookFunction value assigned to the task xTask.
+		 * Returns the pxHookFunction value assigned to the task xTask.  Do not
+		 * call from an interrupt service routine - call
+		 * xTaskGetApplicationTaskTagFromISR() instead.
 		 */
 		TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * 
    void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );
    
+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.  Can
+		 * be called from an interrupt service routine.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
 	#endif /* configUSE_APPLICATION_TASK_TAG ==1 */
 #endif /* ifdef configUSE_APPLICATION_TASK_TAG */
 
@@ -1683,6 +1736,36 @@ void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unquali
  */
 void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 
+/**
+* task. h
+* 
    TickType_t xTaskGetIdleRunTimeCounter( void );
    
+*
+* configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+* must both be defined as 1 for this function to be available.  The application
+* must also then provide definitions for
+* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+* to configure a peripheral timer/counter and return the timers current count
+* value respectively.  The counter should be at least 10 times the frequency of
+* the tick count.
+*
+* Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+* accumulated execution time being stored for each task.  The resolution
+* of the accumulated time value depends on the frequency of the timer
+* configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+* While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
+* execution time of each task into a buffer, xTaskGetIdleRunTimeCounter()
+* returns the total execution time of just the idle task.
+*
+* @return The total run time of the idle task.  This is the amount of time the
+* idle task has actually been executing.  The unit of time is dependent on the
+* frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
+* portGET_RUN_TIME_COUNTER_VALUE() macros.
+*
+* \defgroup xTaskGetIdleRunTimeCounter xTaskGetIdleRunTimeCounter
+* \ingroup TaskUtils
+*/
+TickType_t xTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
+
 /**
  * task. h
  * 
    BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );
    
@@ -2221,7 +2304,7 @@ void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const Tick
  * Sets the pointer to the current TCB to the TCB of the highest priority task
  * that is ready to run.
  */
-void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
 
 /*
  * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
@@ -2301,7 +2384,7 @@ void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVIL
 void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
 
 /*
- * Only avilable when configUSE_TICKLESS_IDLE is set to 1.
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
  * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
  * specific sleep function to determine if it is ok to proceed with the sleep,
  * and if it is ok to proceed, if it is ok to sleep indefinitely.
@@ -2320,7 +2403,7 @@ eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
  * For internal use only.  Increment the mutex held count when a mutex is
  * taken and return the handle of the task that has taken the mutex.
  */
-void *pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
+TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
 
 /*
  * For internal use only.  Same as vTaskSetTimeOutState(), but without a critial
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h b/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
index 05eb90fc9..cb721797f 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -73,7 +73,8 @@ or interrupt version of the queue send function should be used. */
  * reference the subject timer in calls to other software timer API functions
  * (for example, xTimerStart(), xTimerReset(), etc.).
  */
-typedef void * TimerHandle_t;
+struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tmrTimerControl * TimerHandle_t;
 
 /*
  * Defines the prototype to which timer callback functions must conform.
@@ -1230,6 +1231,23 @@ BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvPar
  */
 const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 
+/**
+ * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );
+ *
+ * Updates a timer to be either an autoreload timer, in which case the timer
+ * automatically resets itself each time it expires, or a one shot timer, in
+ * which case the timer will only expire once unless it is manually restarted.
+ *
+ * @param xTimer The handle of the timer being updated.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the timer's period (see the
+ * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If
+ * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ */
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
+
 /**
  * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
  *
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/list.c b/Middlewares/Third_Party/FreeRTOS/Source/list.c
index 758523a3d..21dabdecd 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/list.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/list.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -39,7 +39,7 @@ void vListInitialise( List_t * const pxList )
 	/* The list structure contains a list item which is used to mark the
 	end of the list.  To initialise the list the list end is inserted
 	as the only list entry. */
-	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 
 	/* The list end value is the highest possible value in the list to
 	ensure it remains at the end of the list. */
@@ -47,8 +47,8 @@ void vListInitialise( List_t * const pxList )
 
 	/* The list end next and previous pointers point to itself so we know
 	when the list is empty. */
-	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
-	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 
 	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
 
@@ -62,7 +62,7 @@ void vListInitialise( List_t * const pxList )
 void vListInitialiseItem( ListItem_t * const pxItem )
 {
 	/* Make sure the list item is not recorded as being on a list. */
-	pxItem->pvContainer = NULL;
+	pxItem->pxContainer = NULL;
 
 	/* Write known values into the list item if
 	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
@@ -94,7 +94,7 @@ ListItem_t * const pxIndex = pxList->pxIndex;
 	pxIndex->pxPrevious = pxNewListItem;
 
 	/* Remember which list the item is in. */
-	pxNewListItem->pvContainer = ( void * ) pxList;
+	pxNewListItem->pxContainer = pxList;
 
 	( pxList->uxNumberOfItems )++;
 }
@@ -114,7 +114,7 @@ const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
 	/* Insert the new list item into the list, sorted in xItemValue order.
 
 	If the list already contains a list item with the same item value then the
-	new list item should be placed after it.  This ensures that TCB's which are
+	new list item should be placed after it.  This ensures that TCBs which are
 	stored in ready lists (all of which have the same xItemValue value) get a
 	share of the CPU.  However, if the xItemValue is the same as the back marker
 	the iteration loop below will not end.  Therefore the value is checked
@@ -127,18 +127,18 @@ const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
 	{
 		/* *** NOTE ***********************************************************
 		If you find your application is crashing here then likely causes are
-		listed below.  In addition see http://www.freertos.org/FAQHelp.html for
+		listed below.  In addition see https://www.freertos.org/FAQHelp.html for
 		more tips, and ensure configASSERT() is defined!
-		http://www.freertos.org/a00110.html#configASSERT
+		https://www.freertos.org/a00110.html#configASSERT
 
 			1) Stack overflow -
-			   see http://www.freertos.org/Stacks-and-stack-overflow-checking.html
+			   see https://www.freertos.org/Stacks-and-stack-overflow-checking.html
 			2) Incorrect interrupt priority assignment, especially on Cortex-M
 			   parts where numerically high priority values denote low actual
 			   interrupt priorities, which can seem counter intuitive.  See
-			   http://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
+			   https://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
 			   of configMAX_SYSCALL_INTERRUPT_PRIORITY on
-			   http://www.freertos.org/a00110.html
+			   https://www.freertos.org/a00110.html
 			3) Calling an API function from within a critical section or when
 			   the scheduler is suspended, or calling an API function that does
 			   not end in "FromISR" from an interrupt.
@@ -147,7 +147,7 @@ const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
 			   before vTaskStartScheduler() has been called?).
 		**********************************************************************/
 
-		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
 		{
 			/* There is nothing to do here, just iterating to the wanted
 			insertion position. */
@@ -161,7 +161,7 @@ const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
 
 	/* Remember which list the item is in.  This allows fast removal of the
 	item later. */
-	pxNewListItem->pvContainer = ( void * ) pxList;
+	pxNewListItem->pxContainer = pxList;
 
 	( pxList->uxNumberOfItems )++;
 }
@@ -171,7 +171,7 @@ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
 {
 /* The list item knows which list it is in.  Obtain the list from the list
 item. */
-List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer;
+List_t * const pxList = pxItemToRemove->pxContainer;
 
 	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
 	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
@@ -189,7 +189,7 @@ List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer;
 		mtCOVERAGE_TEST_MARKER();
 	}
 
-	pxItemToRemove->pvContainer = NULL;
+	pxItemToRemove->pxContainer = NULL;
 	( pxList->uxNumberOfItems )--;
 
 	return pxList->uxNumberOfItems;
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/Common/mpu_wrappers.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/Common/mpu_wrappers.c
index 6872b7431..8b3ff2728 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/Common/mpu_wrappers.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/Common/mpu_wrappers.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -46,17 +46,48 @@ task.h is included from an application file. */
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
-/*
- * Checks to see if being called from the context of an unprivileged task, and
- * if so raises the privilege level and returns false - otherwise does nothing
- * other than return true.
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
  */
-extern BaseType_t xPortRaisePrivilege( void );
+BaseType_t xPortRaisePrivilege( void ) FREERTOS_SYSTEM_CALL;
 
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+void vPortResetPrivilege( BaseType_t xRunningPrivileged );
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortRaisePrivilege( void ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xRunningPrivileged;
+
+	/* Check whether the processor is already privileged. */
+	xRunningPrivileged = portIS_PRIVILEGED();
+
+	/* If the processor is not already privileged, raise privilege. */
+	if( xRunningPrivileged != pdTRUE )
+	{
+		portRAISE_PRIVILEGE();
+	}
+
+	return xRunningPrivileged;
+}
+/*-----------------------------------------------------------*/
+
+void vPortResetPrivilege( BaseType_t xRunningPrivileged )
+{
+	if( xRunningPrivileged != pdTRUE )
+	{
+		portRESET_PRIVILEGE();
+	}
+}
 /*-----------------------------------------------------------*/
 
 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -69,7 +100,7 @@ extern BaseType_t xPortRaisePrivilege( void );
 /*-----------------------------------------------------------*/
 
 #if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -82,7 +113,7 @@ extern BaseType_t xPortRaisePrivilege( void );
 /*-----------------------------------------------------------*/
 
 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode, const char * const pcName, uint16_t usStackDepth, void *pvParameters, UBaseType_t uxPriority, TaskHandle_t *pxCreatedTask )
+	BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode, const char * const pcName, uint16_t usStackDepth, void *pvParameters, UBaseType_t uxPriority, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -95,7 +126,7 @@ extern BaseType_t xPortRaisePrivilege( void );
 /*-----------------------------------------------------------*/
 
 #if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer )
+	TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) /* FREERTOS_SYSTEM_CALL */
 	{
 	TaskHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -107,7 +138,7 @@ extern BaseType_t xPortRaisePrivilege( void );
 #endif /* configSUPPORT_STATIC_ALLOCATION */
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const xRegions )
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const xRegions ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -117,7 +148,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( INCLUDE_vTaskDelete == 1 )
-	void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete )
+	void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -128,7 +159,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( INCLUDE_vTaskDelayUntil == 1 )
-	void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, TickType_t xTimeIncrement )
+	void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -139,7 +170,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( INCLUDE_xTaskAbortDelay == 1 )
-	BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask )
+	BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -152,7 +183,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( INCLUDE_vTaskDelay == 1 )
-	void MPU_vTaskDelay( TickType_t xTicksToDelay )
+	void MPU_vTaskDelay( TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -163,7 +194,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( INCLUDE_uxTaskPriorityGet == 1 )
-	UBaseType_t MPU_uxTaskPriorityGet( TaskHandle_t pxTask )
+	UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
 	{
 	UBaseType_t uxReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -176,7 +207,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( INCLUDE_vTaskPrioritySet == 1 )
-	void MPU_vTaskPrioritySet( TaskHandle_t pxTask, UBaseType_t uxNewPriority )
+	void MPU_vTaskPrioritySet( TaskHandle_t pxTask, UBaseType_t uxNewPriority ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -187,7 +218,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( INCLUDE_eTaskGetState == 1 )
-	eTaskState MPU_eTaskGetState( TaskHandle_t pxTask )
+	eTaskState MPU_eTaskGetState( TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 	eTaskState eReturn;
@@ -200,7 +231,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configUSE_TRACE_FACILITY == 1 )
-	void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )
+	void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -211,7 +242,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
-	TaskHandle_t MPU_xTaskGetIdleTaskHandle( void )
+	TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
 	{
 	TaskHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -224,7 +255,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( INCLUDE_vTaskSuspend == 1 )
-	void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend )
+	void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -235,7 +266,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( INCLUDE_vTaskSuspend == 1 )
-	void MPU_vTaskResume( TaskHandle_t pxTaskToResume )
+	void MPU_vTaskResume( TaskHandle_t pxTaskToResume ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -245,7 +276,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 #endif
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSuspendAll( void )
+void MPU_vTaskSuspendAll( void ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -254,7 +285,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskResumeAll( void )
+BaseType_t MPU_xTaskResumeAll( void ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -265,7 +296,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-TickType_t MPU_xTaskGetTickCount( void )
+TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */
 {
 TickType_t xReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -276,7 +307,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void )
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */
 {
 UBaseType_t uxReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -287,7 +318,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery )
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */
 {
 char *pcReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -299,7 +330,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( INCLUDE_xTaskGetHandle == 1 )
-	TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery )
+	TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) /* FREERTOS_SYSTEM_CALL */
 	{
 	TaskHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -312,7 +343,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-	void MPU_vTaskList( char *pcWriteBuffer )
+	void MPU_vTaskList( char *pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -323,7 +354,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-	void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer )
+	void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -333,8 +364,21 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 #endif
 /*-----------------------------------------------------------*/
 
+#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+	TickType_t MPU_xTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */
+	{
+	TickType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTaskGetIdleRunTimeCounter();
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
 #if ( configUSE_APPLICATION_TASK_TAG == 1 )
-	void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxTagValue )
+	void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxTagValue ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -345,7 +389,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_APPLICATION_TASK_TAG == 1 )
-	TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask )
+	TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
 	{
 	TaskHookFunction_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -358,7 +402,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
-	void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )
+	void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -369,7 +413,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
-	void *MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )
+	void *MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */
 	{
 	void *pvReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -382,7 +426,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_APPLICATION_TASK_TAG == 1 )
-	BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
+	BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -395,7 +439,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TRACE_FACILITY == 1 )
-	UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t *pxTaskStatusArray, UBaseType_t uxArraySize, uint32_t *pulTotalRunTime )
+	UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t *pxTaskStatusArray, UBaseType_t uxArraySize, uint32_t *pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */
 	{
 	UBaseType_t uxReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -408,7 +452,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
-	UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
+	UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
 	{
 	UBaseType_t uxReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -420,8 +464,21 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 #endif
 /*-----------------------------------------------------------*/
 
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+	configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+	{
+	configSTACK_DEPTH_TYPE uxReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		uxReturn = uxTaskGetStackHighWaterMark2( xTask );
+		vPortResetPrivilege( xRunningPrivileged );
+		return uxReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
 #if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 )
-	TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void )
+	TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
 	{
 	TaskHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -434,7 +491,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if ( INCLUDE_xTaskGetSchedulerState == 1 )
-	BaseType_t MPU_xTaskGetSchedulerState( void )
+	BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -446,7 +503,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 #endif
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -455,7 +512,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -467,7 +524,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configUSE_TASK_NOTIFICATIONS == 1 )
-	BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
+	BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -480,7 +537,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configUSE_TASK_NOTIFICATIONS == 1 )
-	BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
+	BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -493,7 +550,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configUSE_TASK_NOTIFICATIONS == 1 )
-	uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
+	uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
 	{
 	uint32_t ulReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -506,7 +563,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configUSE_TASK_NOTIFICATIONS == 1 )
-	BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask )
+	BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -519,7 +576,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, UBaseType_t uxItemSize, uint8_t ucQueueType )
+	QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, UBaseType_t uxItemSize, uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
 	{
 	QueueHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -532,7 +589,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
+	QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
 	{
 	QueueHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -544,7 +601,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 #endif
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, BaseType_t xNewQueue )
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, BaseType_t xNewQueue ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -555,7 +612,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition )
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -566,7 +623,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue )
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 UBaseType_t uxReturn;
@@ -577,7 +634,7 @@ UBaseType_t uxReturn;
 }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue )
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 UBaseType_t uxReturn;
@@ -588,7 +645,7 @@ UBaseType_t uxReturn;
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue, void * const pvBuffer, TickType_t xTicksToWait )
+BaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue, void * const pvBuffer, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 BaseType_t xReturn;
@@ -599,7 +656,7 @@ BaseType_t xReturn;
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 BaseType_t xReturn;
@@ -610,7 +667,7 @@ BaseType_t xReturn;
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 BaseType_t xReturn;
@@ -621,30 +678,21 @@ BaseType_t xReturn;
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeekFromISR( QueueHandle_t pxQueue, void * const pvBuffer )
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-BaseType_t xReturn;
-
-	xReturn = xQueuePeekFromISR( pxQueue, pvBuffer );
-	vPortResetPrivilege( xRunningPrivileged );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void* MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore )
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-void * xReturn;
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+	TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+	void * xReturn;
 
-	xReturn = ( void * ) xQueueGetMutexHolder( xSemaphore );
-	vPortResetPrivilege( xRunningPrivileged );
-	return xReturn;
-}
+		xReturn = xQueueGetMutexHolder( xSemaphore );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
 /*-----------------------------------------------------------*/
 
 #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-	QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType )
+	QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
 	{
 	QueueHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -657,7 +705,7 @@ void * xReturn;
 /*-----------------------------------------------------------*/
 
 #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-	QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
+	QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
 	{
 	QueueHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -670,7 +718,7 @@ void * xReturn;
 /*-----------------------------------------------------------*/
 
 #if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-	QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, UBaseType_t uxInitialCount )
+	QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, UBaseType_t uxInitialCount ) /* FREERTOS_SYSTEM_CALL */
 	{
 	QueueHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -684,7 +732,7 @@ void * xReturn;
 
 #if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
 
-	QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
+	QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
 	{
 	QueueHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -697,7 +745,7 @@ void * xReturn;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_RECURSIVE_MUTEXES == 1 )
-	BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xBlockTime )
+	BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xBlockTime ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -710,7 +758,7 @@ void * xReturn;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_RECURSIVE_MUTEXES == 1 )
-	BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex )
+	BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -723,7 +771,7 @@ void * xReturn;
 /*-----------------------------------------------------------*/
 
 #if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-	QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength )
+	QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength ) /* FREERTOS_SYSTEM_CALL */
 	{
 	QueueSetHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -736,7 +784,7 @@ void * xReturn;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_QUEUE_SETS == 1 )
-	QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t xBlockTimeTicks )
+	QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t xBlockTimeTicks ) /* FREERTOS_SYSTEM_CALL */
 	{
 	QueueSetMemberHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -749,7 +797,7 @@ void * xReturn;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_QUEUE_SETS == 1 )
-	BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -762,7 +810,7 @@ void * xReturn;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_QUEUE_SETS == 1 )
-	BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -775,7 +823,7 @@ void * xReturn;
 /*-----------------------------------------------------------*/
 
 #if configQUEUE_REGISTRY_SIZE > 0
-	void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName )
+	void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -787,7 +835,7 @@ void * xReturn;
 /*-----------------------------------------------------------*/
 
 #if configQUEUE_REGISTRY_SIZE > 0
-	void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue )
+	void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -799,7 +847,7 @@ void * xReturn;
 /*-----------------------------------------------------------*/
 
 #if configQUEUE_REGISTRY_SIZE > 0
-	const char *MPU_pcQueueGetName( QueueHandle_t xQueue )
+	const char *MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 	const char *pcReturn;
@@ -812,7 +860,7 @@ void * xReturn;
 #endif
 /*-----------------------------------------------------------*/
 
-void MPU_vQueueDelete( QueueHandle_t xQueue )
+void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -823,7 +871,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	void *MPU_pvPortMalloc( size_t xSize )
+	void *MPU_pvPortMalloc( size_t xSize ) /* FREERTOS_SYSTEM_CALL */
 	{
 	void *pvReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -838,7 +886,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	void MPU_vPortFree( void *pv )
+	void MPU_vPortFree( void *pv ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -850,7 +898,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	void MPU_vPortInitialiseBlocks( void )
+	void MPU_vPortInitialiseBlocks( void ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -862,7 +910,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	size_t MPU_xPortGetFreeHeapSize( void )
+	size_t MPU_xPortGetFreeHeapSize( void ) /* FREERTOS_SYSTEM_CALL */
 	{
 	size_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -877,7 +925,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )
-	TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction )
+	TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) /* FREERTOS_SYSTEM_CALL */
 	{
 	TimerHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -891,7 +939,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )
-	TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer )
+	TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) /* FREERTOS_SYSTEM_CALL */
 	{
 	TimerHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -905,7 +953,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configUSE_TIMERS == 1 )
-	void *MPU_pvTimerGetTimerID( const TimerHandle_t xTimer )
+	void *MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
 	{
 	void * pvReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -919,7 +967,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configUSE_TIMERS == 1 )
-	void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
+	void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -930,7 +978,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configUSE_TIMERS == 1 )
-	BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer )
+	BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -944,7 +992,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configUSE_TIMERS == 1 )
-	TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void )
+	TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
 	{
 	TaskHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -958,7 +1006,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
-	BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )
+	BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -972,7 +1020,18 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configUSE_TIMERS == 1 )
-	const char * MPU_pcTimerGetName( TimerHandle_t xTimer )
+	void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		vTimerSetReloadMode( xTimer, uxAutoReload );
+		vPortResetPrivilege( xRunningPrivileged );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+	const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
 	{
 	const char * pcReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -986,7 +1045,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configUSE_TIMERS == 1 )
-	TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer )
+	TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
 	{
 	TickType_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1000,7 +1059,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configUSE_TIMERS == 1 )
-	TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer )
+	TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
 	{
 	TickType_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1014,7 +1073,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configUSE_TIMERS == 1 )
-	BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
+	BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
 	{
 	BaseType_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1028,7 +1087,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	EventGroupHandle_t MPU_xEventGroupCreate( void )
+	EventGroupHandle_t MPU_xEventGroupCreate( void ) /* FREERTOS_SYSTEM_CALL */
 	{
 	EventGroupHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1042,7 +1101,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer )
+	EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) /* FREERTOS_SYSTEM_CALL */
 	{
 	EventGroupHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1055,7 +1114,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 #endif
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait )
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
 {
 EventBits_t xReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1067,7 +1126,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */
 {
 EventBits_t xReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1079,7 +1138,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet )
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */
 {
 EventBits_t xReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1091,7 +1150,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait )
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
 {
 EventBits_t xReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1103,7 +1162,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup )
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -1112,7 +1171,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait )
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
 {
 size_t xReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1124,19 +1183,19 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken )
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
 {
 size_t xReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
-	xReturn = xStreamBufferSendFromISR( xStreamBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken );
+	xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );
 	vPortResetPrivilege( xRunningPrivileged );
 
 	return xReturn;
 }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait )
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
 {
 size_t xReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1148,19 +1207,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken )
-{
-size_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferReceiveFromISR( xStreamBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 
@@ -1169,7 +1216,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1181,7 +1228,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1193,7 +1240,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1205,7 +1252,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
 {
 size_t xReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1217,7 +1264,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
 {
 size_t xReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1229,7 +1276,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */
 {
 BaseType_t xReturn;
 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1242,7 +1289,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )
+	StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) /* FREERTOS_SYSTEM_CALL */
 	{
 	StreamBufferHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1256,7 +1303,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 /*-----------------------------------------------------------*/
 
 #if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer )
+	StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
 	{
 	StreamBufferHandle_t xReturn;
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
index dc2c5c6d8..a5fb4cc4f 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -213,7 +213,7 @@ void vPortStartFirstTask( void )
  */
 BaseType_t xPortStartScheduler( void )
 {
-	/* Make PendSV, CallSV and SysTick the same priroity as the kernel. */
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
 	*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
 	*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
 
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
index 2ca4cb954..e1aa450cc 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -115,6 +115,8 @@ extern void vClearInterruptMaskFromISR( uint32_t ulMask )  __attribute__((naked)
 
 #define portNOP()
 
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/port.c
new file mode 100644
index 000000000..bd85a6ffe
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/* Secure components includes. */
+	#include "secure_context.h"
+	#include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK				( 0x00000004 )
+#define portNVIC_SYSTICK_INT				( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
+#define portNVIC_PENDSVSET					( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY			( 255UL )
+#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE				( 3UL )
+#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS					( 20UL )
+#define portCPACR_CP11_POS					( 22UL )
+
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS					( 31UL )
+#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS					( 30UL )
+#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS				( 0UL )
+#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS				( 8UL )
+#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS				( 16UL )
+#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS				( 24UL )
+#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS				( 0UL )
+#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS				( 8UL )
+#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS				( 16UL )
+#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS				( 24UL )
+#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE			( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE						( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         FD
+	 * 1111 1111  1111 1111  1111 1111  1111 1101
+	 *
+	 * Bit[6] - 1 --> The exception was taken from the Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 1 --> The exception was taken to the Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
+#else
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         BC
+	 * 1111 1111  1111 1111  1111 1111  1011 1100
+	 *
+	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS			prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS				1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT				0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Setup the Memory Protection Unit (MPU).
+	 */
+	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+	/**
+	 * @brief Setup the Floating Point Unit (FPU).
+	 */
+	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Saved as part of the task context to indicate which context the
+	 * task is using on the secure side.
+	 */
+	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Stop and reset the SysTick. */
+	*( portNVIC_SYSTICK_CTRL ) = 0UL;
+	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	 * its caller as there is nothing to return to. If a task wants to exit it
+	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
+	 * to be triggered if configASSERT() is defined, then stop here so
+	 * application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		 * started to remove a compiler warning about the function being
+		 * defined but never called.  ulDummy is used purely to quieten other
+		 * warnings about code appearing after this function is called - making
+		 * ulDummy volatile makes the compiler think the function could return
+		 * and therefore not output an 'unreachable code' warning for code that
+		 * appears after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __privileged_functions_start__;
+		extern uint32_t * __privileged_functions_end__;
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+		extern uint32_t * __unprivileged_flash_start__;
+		extern uint32_t * __unprivileged_flash_end__;
+		extern uint32_t * __privileged_sram_start__;
+		extern uint32_t * __privileged_sram_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __privileged_functions_start__[];
+		extern uint32_t __privileged_functions_end__[];
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+		extern uint32_t __unprivileged_flash_start__[];
+		extern uint32_t __unprivileged_flash_end__[];
+		extern uint32_t __privileged_sram_start__[];
+		extern uint32_t __privileged_sram_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+
+		/* Check that the MPU is present. */
+		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+		{
+			/* MAIR0 - Index 0. */
+			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+			/* MAIR0 - Index 1. */
+			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+			/* Setup privileged flash as Read Only so that privileged tasks can
+			 * read it but not modify. */
+			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged flash as Read Only by both privileged and
+			 * unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged syscalls flash as Read Only by both privileged
+			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup RAM containing kernel data for privileged access only. */
+			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+								( portMPU_REGION_EXECUTE_NEVER );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Enable mem fault. */
+			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+			/* Enable MPU with privileged background access i.e. unmapped
+			 * regions have privileged access. */
+			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			/* Enable non-secure access to the FPU. */
+			SecureInit_EnableNSFPUAccess();
+		}
+		#endif /* configENABLE_TRUSTZONE */
+
+		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+		 * unprivileged code should be able to access FPU. CP11 should be
+		 * programmed to the same value as CP10. */
+		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+							);
+
+		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
+		 * context on exception entry and restore on exception return.
+		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
+		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+	}
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	portDISABLE_INTERRUPTS();
+	ulCriticalNesting++;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	configASSERT( ulCriticalNesting );
+	ulCriticalNesting--;
+
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	uint32_t ulR0;
+	#if( configENABLE_MPU == 1 )
+		uint32_t ulControl, ulIsTaskPrivileged;
+	#endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
+	 * R12, LR, PC, xPSR. */
+	ulPC = pulCallerStackAddress[ 6 ];
+	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+	switch( ucSVCNumber )
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+			case portSVC_ALLOCATE_SECURE_CONTEXT:
+			{
+				/* R0 contains the stack size passed as parameter to the
+				 * vPortAllocateSecureContext function. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Read the CONTROL register value. */
+					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+					/* The task that raised the SVC is privileged if Bit[0]
+					 * in the CONTROL register is 0. */
+					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+				}
+				#else
+				{
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0 );
+				}
+				#endif /* configENABLE_MPU */
+
+				configASSERT( xSecureContext != NULL );
+				SecureContext_LoadContext( xSecureContext );
+			}
+			break;
+
+			case portSVC_FREE_SECURE_CONTEXT:
+			{
+				/* R0 contains the secure context handle to be freed. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				/* Free the secure context. */
+				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+			}
+			break;
+		#endif /* configENABLE_TRUSTZONE */
+
+		case portSVC_START_SCHEDULER:
+		{
+			#if( configENABLE_TRUSTZONE == 1 )
+			{
+				/* De-prioritize the non-secure exceptions so that the
+				 * non-secure pendSV runs at the lowest priority. */
+				SecureInit_DePrioritizeNSExceptions();
+
+				/* Initialize the secure context management system. */
+				SecureContext_Init();
+			}
+			#endif /* configENABLE_TRUSTZONE */
+
+			#if( configENABLE_FPU == 1 )
+			{
+				/* Setup the Floating Point Unit (FPU). */
+				prvSetupFPU();
+			}
+			#endif /* configENABLE_FPU */
+
+			/* Setup the context of the first task so that the first task starts
+			 * executing. */
+			vRestoreContextOfFirstTask();
+		}
+		break;
+
+		#if( configENABLE_MPU == 1 )
+			case portSVC_RAISE_PRIVILEGE:
+			{
+				/* Only raise the privilege, if the svc was raised from any of
+				 * the system calls. */
+				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+				{
+					vRaisePrivilege();
+				}
+			}
+			break;
+		#endif /* configENABLE_MPU */
+
+		default:
+		{
+			/* Incorrect SVC call. */
+			configASSERT( pdFALSE );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	 * interrupt. */
+	#if( portPRELOAD_REGISTERS == 0 )
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
+		*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#else /* portPRELOAD_REGISTERS */
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
+		pxTopOfStack--;
+		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#endif /* portPRELOAD_REGISTERS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+	#if( configENABLE_MPU == 1 )
+	{
+		/* Setup the Memory Protection Unit (MPU). */
+		prvSetupMPU();
+	}
+	#endif /* configENABLE_MPU */
+
+	/* Start the timer that generates the tick ISR. Interrupts are disabled
+	 * here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialize the critical nesting count ready for the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task. */
+	vStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing. Call the task
+	 * exit error function to prevent compiler warnings about a static function
+	 * not being called in the case that the application writer overrides this
+	 * functionality by defining configTASK_RETURN_ADDRESS. Call
+	 * vTaskSwitchContext() so link time optimization does not remove the
+	 * symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Not implemented in ports where there is nothing to return to.
+	 * Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+	{
+	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+	int32_t lIndex = 0;
+
+		/* Setup MAIR0. */
+		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+		/* This function is called automatically when the task is created - in
+		 * which case the stack region parameters will be valid.  At all other
+		 * times the stack parameters will not be valid and it is assumed that
+		 * the stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
+															( portMPU_REGION_NON_SHAREABLE ) |
+															( portMPU_REGION_READ_WRITE ) |
+															( portMPU_REGION_EXECUTE_NEVER );
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
+															( portMPU_RLAR_ATTR_INDEX0 ) |
+															( portMPU_RLAR_REGION_ENABLE );
+		}
+
+		/* User supplied configurable regions. */
+		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+		{
+			/* If xRegions is NULL i.e. the task has not specified any MPU
+			 * region, the else part ensures that all the configurable MPU
+			 * regions are invalidated. */
+			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+			{
+				/* Translate the generic region definition contained in xRegions
+				 * into the ARMv8 specific MPU settings that are then stored in
+				 * xMPUSettings. */
+				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+				/* Start address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
+																			( portMPU_REGION_NON_SHAREABLE );
+
+				/* RO/RW. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+				}
+				else
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+				}
+
+				/* XN. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+				}
+
+				/* End Address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
+																			( portMPU_RLAR_REGION_ENABLE );
+
+				/* Normal memory/ Device memory. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+				{
+					/* Attr1 in MAIR0 is configured as device memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+				}
+				else
+				{
+					/* Attr1 in MAIR0 is configured as normal memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+				}
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.c
new file mode 100644
index 000000000..c8345c799
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.c
@@ -0,0 +1,468 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"													\n"
+	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr  r3, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr  r0, [r3]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r5, #1										\n" /* r5 = 1. */
+	"	bics r4, r5										\n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	"	ldr  r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
+	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str  r4, [r2]									\n" /* Program MAIR0. */
+	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	"	movs r5, #4										\n" /* r5 = 4. */
+	"	str  r5, [r2]									\n" /* Program RNR = 4. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read first set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write first set of RBAR/RLAR registers. */
+	"	movs r5, #5										\n" /* r5 = 5. */
+	"	str  r5, [r2]									\n" /* Program RNR = 5. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read second set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write second set of RBAR/RLAR registers. */
+	"	movs r5, #6										\n" /* r5 = 6. */
+	"	str  r5, [r2]									\n" /* Program RNR = 6. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read third set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write third set of RBAR/RLAR registers. */
+	"	movs r5, #7										\n" /* r5 = 7. */
+	"	str  r5, [r2]									\n" /* Program RNR = 7. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write fourth set of RBAR/RLAR registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r5, #1										\n" /* r5 = 1. */
+	"	orrs r4, r5										\n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldm  r0!, {r1-r4}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+	"	ldr  r5, xSecureContextConst2					\n"
+	"	str  r1, [r5]									\n" /* Set xSecureContext to this task's value for the same. */
+	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
+	"	msr  control, r3								\n" /* Set this task's CONTROL value. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r4											\n" /* Finally, branch to EXC_RETURN. */
+	#else /* configENABLE_MPU */
+	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+	"	ldr  r4, xSecureContextConst2					\n"
+	"	str  r1, [r4]									\n" /* Set xSecureContext to this task's value for the same. */
+	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
+	"	movs r1, #2										\n" /* r1 = 2. */
+	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+	"xSecureContextConst2: .word xSecureContext			\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst2: .word 0xe000ed94					\n"
+	"xMAIR0Const2: .word 0xe000edc0						\n"
+	"xRNRConst2: .word 0xe000ed98						\n"
+	"xRBARConst2: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	movs r1, #1										\n" /* r1 = 1. */
+	"	tst r0, r1										\n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+	"	beq running_privileged							\n" /* If the result of previous AND operation was 0, branch. */
+	"	movs r0, #0										\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	"	bx lr											\n" /* Return. */
+	" running_privileged:								\n"
+	"	movs r0, #1										\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	"	bx lr											\n" /* Return. */
+	"													\n"
+	"	.align 4										\n"
+	::: "r0", "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	 __asm volatile
+	(
+	"	mrs r0, control									\n" /* Read the CONTROL register. */
+	"	movs r1, #1										\n" /* r1 = 1. */
+	"	bics r0, r1										\n" /* Clear the bit 0. */
+	"	msr control, r0									\n" /* Write back the new CONTROL value. */
+	"	bx lr											\n" /* Return to the caller. */
+	::: "r0", "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	movs r1, #1										\n" /* r1 = 1. */
+	"	orrs r0, r1										\n" /* r0 = r0 | r1. */
+	"	msr control, r0									\n" /* CONTROL = r0. */
+	"	bx lr											\n" /* Return to the caller. */
+	:::"r0", "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
+	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
+	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
+	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
+	"	cpsie i											\n" /* Globally enable interrupts. */
+	"	dsb												\n"
+	"	isb												\n"
+	"	svc %0											\n" /* System call to start the first task. */
+	"	nop												\n"
+	"													\n"
+	"   .align 4										\n"
+	"xVTORConst: .word 0xe000ed08						\n"
+	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	mrs r0, PRIMASK									\n"
+	"	cpsid i											\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* To avoid compiler warnings.  The return statement will never be reached,
+	 * but some compilers warn if it is not included, while others won't compile
+	 * if it is. */
+	return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	msr PRIMASK, r0									\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* Just to avoid compiler warning.  ulMask is used from the asm code but
+	 * the compiler can't see that.  Some compilers generate warnings without
+	 * the following line, while others generate warnings if the line is
+	 * included. */
+	( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"	.extern SecureContext_SaveContext				\n"
+	"	.extern SecureContext_LoadContext				\n"
+	"													\n"
+	"	mrs r1, psp										\n" /* Read PSP in r1. */
+	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	"	ldr r0, [r2]									\n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+	"													\n"
+	"	cbz r0, save_ns_context							\n" /* No secure context to save. */
+	"	push {r0-r2, r14}								\n"
+	"	bl SecureContext_SaveContext					\n"
+	"	pop {r0-r3}										\n" /* LR is now in r3. */
+	"	mov lr, r3										\n" /* LR = r3. */
+	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	"	bpl save_ns_context								\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
+	#if( configENABLE_MPU == 1 )
+	"	subs r1, r1, #16								\n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mrs r3, control									\n" /* r3 = CONTROL. */
+	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
+	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+	"	subs r1, r1, #12								\n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+	#endif /* configENABLE_MPU */
+	"	b select_next_task								\n"
+	"													\n"
+	" save_ns_context:									\n"
+	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
+	#if( configENABLE_MPU == 1 )
+	"	subs r1, r1, #48								\n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	adds r1, r1, #16								\n" /* r1 = r1 + 16. */
+	"	stmia r1!, {r4-r7}								\n" /* Store the low registers that are not saved automatically. */
+	"	mov r4, r8										\n" /* r4 = r8. */
+	"	mov r5, r9										\n" /* r5 = r9. */
+	"	mov r6, r10										\n" /* r6 = r10. */
+	"	mov r7, r11										\n" /* r7 = r11. */
+	"	stmia r1!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mrs r3, control									\n" /* r3 = CONTROL. */
+	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
+	"	subs r1, r1, #48								\n" /* r1 = r1 - 48. */
+	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+	"	subs r1, r1, #44								\n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmia r1!, {r0, r2-r7}							\n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+	"	mov r4, r8										\n" /* r4 = r8. */
+	"	mov r5, r9										\n" /* r5 = r9. */
+	"	mov r6, r10										\n" /* r6 = r10. */
+	"	mov r7, r11										\n" /* r7 = r11. */
+	"	stmia r1!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	" select_next_task:									\n"
+	"	cpsid i											\n"
+	"	bl vTaskSwitchContext							\n"
+	"	cpsie i											\n"
+	"													\n"
+	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r3, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr r1, [r3]									\n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r5, #1										\n" /* r5 = 1. */
+	"	bics r4, r5										\n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	"	ldr r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
+	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str r4, [r2]									\n" /* Program MAIR0. */
+	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	"	movs r5, #4										\n" /* r5 = 4. */
+	"	str  r5, [r2]									\n" /* Program RNR = 4. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read first set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write first set of RBAR/RLAR registers. */
+	"	movs r5, #5										\n" /* r5 = 5. */
+	"	str  r5, [r2]									\n" /* Program RNR = 5. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read second set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write second set of RBAR/RLAR registers. */
+	"	movs r5, #6										\n" /* r5 = 6. */
+	"	str  r5, [r2]									\n" /* Program RNR = 6. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read third set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write third set of RBAR/RLAR registers. */
+	"	movs r5, #7										\n" /* r5 = 7. */
+	"	str  r5, [r2]									\n" /* Program RNR = 7. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write fourth set of RBAR/RLAR registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r5, #1										\n" /* r5 = 1. */
+	"	orrs r4, r5										\n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldmia r1!, {r0, r2-r4}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
+	"	msr control, r3									\n" /* Restore the CONTROL register value for the task. */
+	"	mov lr, r4										\n" /* LR = r4. */
+	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
+	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
+	"	push {r1,r4}									\n"
+	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
+	"	pop {r1,r4}										\n"
+	"	mov lr, r4										\n" /* LR = r4. */
+	"	lsls r2, r4, #25								\n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
+	"	bx lr											\n"
+	#else /* configENABLE_MPU */
+	"	ldmia r1!, {r0, r2-r3}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
+	"	mov lr, r3										\n" /* LR = r3. */
+	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
+	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
+	"	push {r1,r3}									\n"
+	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
+	"	pop {r1,r3}										\n"
+	"	mov lr, r3										\n" /* LR = r3. */
+	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
+	"	bx lr											\n"
+	#endif /* configENABLE_MPU */
+	"													\n"
+	" restore_ns_context:								\n"
+	"	adds r1, r1, #16								\n" /* Move to the high registers. */
+	"	ldmia r1!, {r4-r7}								\n" /* Restore the high registers that are not automatically restored. */
+	"	mov r8, r4										\n" /* r8 = r4. */
+	"	mov r9, r5										\n" /* r9 = r5. */
+	"	mov r10, r6										\n" /* r10 = r6. */
+	"	mov r11, r7										\n" /* r11 = r7. */
+	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
+	"	subs r1, r1, #32								\n" /* Go back to the low registers. */
+	"	ldmia r1!, {r4-r7}								\n" /* Restore the low registers that are not automatically restored. */
+	"	bx lr											\n"
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
+	"xSecureContextConst: .word xSecureContext			\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst: .word 0xe000ed94					\n"
+	"xMAIR0Const: .word 0xe000edc0						\n"
+	"xRNRConst: .word 0xe000ed98						\n"
+	"xRBARConst: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	movs r0, #4										\n"
+	"	mov r1, lr										\n"
+	"	tst r0, r1										\n"
+	"	beq stacking_used_msp							\n"
+	"	mrs r0, psp										\n"
+	"	ldr r2, svchandler_address_const				\n"
+	"	bx r2											\n"
+	" stacking_used_msp:								\n"
+	"	mrs r0, msp										\n"
+	"	ldr r2, svchandler_address_const				\n"
+	"	bx r2											\n"
+	"													\n"
+	"	.align 4										\n"
+	"svchandler_address_const: .word vPortSVCHandler_C	\n"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	svc %0											\n" /* Secure context is allocated in the supervisor call. */
+	"	bx lr											\n" /* Return. */
+	:: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	ldr r1, [r0]									\n" /* The first item in the TCB is the top of the stack. */
+	"	ldr r0, [r1]									\n" /* The first item on the stack is the task's xSecureContext. */
+	"	cmp r0, #0										\n" /* Raise svc if task's xSecureContext is not NULL. */
+	"	beq free_secure_context							\n"
+	"	bx lr											\n" /* There is no secure context (xSecureContext is NULL). */
+	" free_secure_context:								\n"
+	"	svc %0											\n" /* Secure context is freed in the supervisor call. */
+	"	bx lr											\n" /* Return. */
+	:: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.h
new file mode 100644
index 000000000..2ecf04ea6
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h
new file mode 100644
index 000000000..bbab1b7c8
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M23"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__attribute__(( used ))
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.c
new file mode 100644
index 000000000..53535cd9e
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.c
@@ -0,0 +1,204 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
+	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
+	uint8_t *pucStackStart;				/**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+	uint32_t ulIPSR;
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* No stack for thread mode until a task's context is loaded. */
+		secureportSET_PSPLIM( securecontextNO_STACK );
+		secureportSET_PSP( securecontextNO_STACK );
+
+		#if( configENABLE_MPU == 1 )
+		{
+			/* Configure thread mode to use PSP and to be unprivileged. */
+			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+		}
+		#else /* configENABLE_MPU */
+		{
+			/* Configure thread mode to use PSP and to be privileged.. */
+			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+		}
+		#endif /* configENABLE_MPU */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+	uint8_t *pucStackMemory = NULL;
+	uint32_t ulIPSR;
+	SecureContextHandle_t xSecureContextHandle = NULL;
+	#if( configENABLE_MPU == 1 )
+		uint32_t *pulCurrentStackPointer = NULL;
+	#endif /* configENABLE_MPU */
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* Allocate the context structure. */
+		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+		if( xSecureContextHandle != NULL )
+		{
+			/* Allocate the stack space. */
+			pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+			if( pucStackMemory != NULL )
+			{
+				/* Since stack grows down, the starting point will be the last
+				 * location. Note that this location is next to the last
+				 * allocated byte because the hardware decrements the stack
+				 * pointer before writing i.e. if stack pointer is 0x2, a push
+				 * operation will decrement the stack pointer to 0x1 and then
+				 * write at 0x1. */
+				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+				/* The stack cannot go beyond this location. This value is
+				 * programmed in the PSPLIM register on context switch.*/
+				xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Store the correct CONTROL value for the task on the stack.
+					 * This value is programmed in the CONTROL register on
+					 * context switch. */
+					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+					pulCurrentStackPointer--;
+					if( ulIsTaskPrivileged )
+					{
+						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+					}
+					else
+					{
+						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+					}
+
+					/* Store the current stack pointer. This value is programmed in
+					 * the PSP register on context switch. */
+					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+				}
+				#else /* configENABLE_MPU */
+				{
+					/* Current SP is set to the starting of the stack. This
+					 * value programmed in the PSP register on context switch. */
+					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+
+				}
+				#endif /* configENABLE_MPU */
+			}
+			else
+			{
+				/* Free the context to avoid memory leak and make sure to return
+				 * NULL to indicate failure. */
+				vPortFree( xSecureContextHandle );
+				xSecureContextHandle = NULL;
+			}
+		}
+	}
+
+	return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+	uint32_t ulIPSR;
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* Ensure that valid parameters are passed. */
+		secureportASSERT( xSecureContextHandle != NULL );
+
+		/* Free the stack space. */
+		vPortFree( xSecureContextHandle->pucStackLimit );
+
+		/* Free the context itself. */
+		vPortFree( xSecureContextHandle );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.h
new file mode 100644
index 000000000..e148bff8e
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.h
@@ -0,0 +1,111 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include 
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK	0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext*	SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if( configENABLE_MPU == 1 )
+	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c
new file mode 100644
index 000000000..e70349828
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c
@@ -0,0 +1,91 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+#if( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+	/* xSecureContextHandle value is in r0. */
+	__asm volatile
+	(
+	"	.syntax unified							\n"
+	"											\n"
+	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
+	"	cbz r1, load_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
+	"	ldmia r0!, {r1, r2}						\n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+	#if( configENABLE_MPU == 1 )
+	"	ldmia r1!, {r3}							\n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+	"	msr control, r3							\n" /* CONTROL = r3. */
+	#endif /* configENABLE_MPU */
+	"	msr psplim, r2							\n" /* PSPLIM = r2. */
+	"	msr psp, r1								\n" /* PSP = r1. */
+	"											\n"
+	" load_ctx_therad_mode:						\n"
+	"	nop										\n"
+	"											\n"
+	:::"r0", "r1", "r2"
+	);
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+	/* xSecureContextHandle value is in r0. */
+	__asm volatile
+	(
+	"	.syntax unified							\n"
+	"											\n"
+	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
+	"	cbz r1, save_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
+	"	mrs r1, psp								\n" /* r1 = PSP. */
+	#if( configENABLE_MPU == 1 )
+	"	mrs r2, control							\n" /* r2 = CONTROL. */
+	"	subs r1, r1, #4							\n" /* Make space for the CONTROL value on the stack. */
+	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	"	stmia r1!, {r2}							\n" /* Store CONTROL value on the stack. */
+	#else /* configENABLE_MPU */
+	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	#endif /* configENABLE_MPU */
+	"	movs r1, %0								\n" /* r1 = securecontextNO_STACK. */
+	"	msr psplim, r1							\n" /* PSPLIM = securecontextNO_STACK. */
+	"	msr psp, r1								\n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+	"											\n"
+	" save_ctx_therad_mode:						\n"
+	"	nop										\n"
+	"											\n"
+	:: "i" ( securecontextNO_STACK ) : "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.c
new file mode 100644
index 000000000..60fce5c66
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.c
@@ -0,0 +1,450 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+	#define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+	#define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+	#define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	 * heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
+	size_t xBlockSize;						/**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	 * blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	 * at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	 * entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	 * than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	 * make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	 * make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	 * before and the block after, then it's pxNextFreeBlock pointer will have
+	 * already been set, and should not be set here as that would make it point
+	 * to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	/* If this is the first call to malloc then the heap will require
+	 * initialisation to setup the list of free blocks. */
+	if( pxEnd == NULL )
+	{
+		prvHeapInit();
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Check the requested block size is not so large that the top bit is set.
+	 * The top bit of the block size member of the BlockLink_t structure is used
+	 * to determine who owns the block - the application or the kernel, so it
+	 * must be free. */
+	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+	{
+		/* The wanted size is increased so it can contain a BlockLink_t
+		 * structure in addition to the requested amount of bytes. */
+		if( xWantedSize > 0 )
+		{
+			xWantedSize += xHeapStructSize;
+
+			/* Ensure that blocks are always aligned to the required number of
+			 * bytes. */
+			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+			{
+				/* Byte alignment required. */
+				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+		{
+			/* Traverse the list from the start (lowest address) block until
+			 * one of adequate size is found. */
+			pxPreviousBlock = &xStart;
+			pxBlock = xStart.pxNextFreeBlock;
+			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+			{
+				pxPreviousBlock = pxBlock;
+				pxBlock = pxBlock->pxNextFreeBlock;
+			}
+
+			/* If the end marker was reached then a block of adequate size was
+			 * not found. */
+			if( pxBlock != pxEnd )
+			{
+				/* Return the memory space pointed to - jumping over the
+				 * BlockLink_t structure at its start. */
+				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+				/* This block is being returned for use so must be taken out
+				 * of the list of free blocks. */
+				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+				/* If the block is larger than required it can be split into
+				 * two. */
+				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+				{
+					/* This block is to be split into two.  Create a new
+					 * block following the number of bytes requested. The void
+					 * cast is used to prevent byte alignment warnings from the
+					 * compiler. */
+					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+					/* Calculate the sizes of two blocks split from the single
+					 * block. */
+					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+					pxBlock->xBlockSize = xWantedSize;
+
+					/* Insert the new block into the list of free blocks. */
+					prvInsertBlockIntoFreeList( pxNewBlockLink );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+				{
+					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* The block is being returned - it is allocated and owned by
+				 * the application and has no "next" block. */
+				pxBlock->xBlockSize |= xBlockAllocatedBit;
+				pxBlock->pxNextFreeBlock = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceMALLOC( pvReturn, xWantedSize );
+
+	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		 * before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				 * allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				secureportDISABLE_NON_SECURE_INTERRUPTS();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+				}
+				secureportENABLE_NON_SECURE_INTERRUPTS();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.h
new file mode 100644
index 000000000..69e4f2a86
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include 
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void *pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void *pv );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.c
new file mode 100644
index 000000000..c6525f755
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS			( 29UL )
+#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS				( 26UL )
+#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS			( 10UL )
+#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS			( 11UL )
+#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+	uint32_t ulIPSR;
+
+	 /* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
+	}
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+	uint32_t ulIPSR;
+
+	 /* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+		 * permitted. CP11 should be programmed to the same value as CP10. */
+		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+		 * that we can enable/disable lazy stacking in port.c file. */
+		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
+
+		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+		 * registers (S16-S31) are also pushed to stack on exception entry and
+		 * restored on exception return. */
+		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.h
new file mode 100644
index 000000000..6c5bc71f5
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h
new file mode 100644
index 000000000..760edab56
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT					8
+#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
+#else
+	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x )						\
+	if( ( x ) == 0 )								\
+	{												\
+		secureportDISABLE_SECURE_INTERRUPTS();		\
+		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
+		for( ;; );									\
+	}
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
new file mode 100644
index 000000000..bd85a6ffe
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/* Secure components includes. */
+	#include "secure_context.h"
+	#include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK				( 0x00000004 )
+#define portNVIC_SYSTICK_INT				( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
+#define portNVIC_PENDSVSET					( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY			( 255UL )
+#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE				( 3UL )
+#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS					( 20UL )
+#define portCPACR_CP11_POS					( 22UL )
+
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS					( 31UL )
+#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS					( 30UL )
+#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS				( 0UL )
+#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS				( 8UL )
+#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS				( 16UL )
+#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS				( 24UL )
+#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS				( 0UL )
+#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS				( 8UL )
+#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS				( 16UL )
+#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS				( 24UL )
+#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE			( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE						( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         FD
+	 * 1111 1111  1111 1111  1111 1111  1111 1101
+	 *
+	 * Bit[6] - 1 --> The exception was taken from the Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 1 --> The exception was taken to the Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
+#else
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         BC
+	 * 1111 1111  1111 1111  1111 1111  1011 1100
+	 *
+	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS			prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS				1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT				0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Setup the Memory Protection Unit (MPU).
+	 */
+	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+	/**
+	 * @brief Setup the Floating Point Unit (FPU).
+	 */
+	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Saved as part of the task context to indicate which context the
+	 * task is using on the secure side.
+	 */
+	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Stop and reset the SysTick. */
+	*( portNVIC_SYSTICK_CTRL ) = 0UL;
+	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	 * its caller as there is nothing to return to. If a task wants to exit it
+	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
+	 * to be triggered if configASSERT() is defined, then stop here so
+	 * application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		 * started to remove a compiler warning about the function being
+		 * defined but never called.  ulDummy is used purely to quieten other
+		 * warnings about code appearing after this function is called - making
+		 * ulDummy volatile makes the compiler think the function could return
+		 * and therefore not output an 'unreachable code' warning for code that
+		 * appears after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __privileged_functions_start__;
+		extern uint32_t * __privileged_functions_end__;
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+		extern uint32_t * __unprivileged_flash_start__;
+		extern uint32_t * __unprivileged_flash_end__;
+		extern uint32_t * __privileged_sram_start__;
+		extern uint32_t * __privileged_sram_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __privileged_functions_start__[];
+		extern uint32_t __privileged_functions_end__[];
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+		extern uint32_t __unprivileged_flash_start__[];
+		extern uint32_t __unprivileged_flash_end__[];
+		extern uint32_t __privileged_sram_start__[];
+		extern uint32_t __privileged_sram_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+
+		/* Check that the MPU is present. */
+		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+		{
+			/* MAIR0 - Index 0. */
+			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+			/* MAIR0 - Index 1. */
+			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+			/* Setup privileged flash as Read Only so that privileged tasks can
+			 * read it but not modify. */
+			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged flash as Read Only by both privileged and
+			 * unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged syscalls flash as Read Only by both privileged
+			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup RAM containing kernel data for privileged access only. */
+			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+								( portMPU_REGION_EXECUTE_NEVER );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Enable mem fault. */
+			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+			/* Enable MPU with privileged background access i.e. unmapped
+			 * regions have privileged access. */
+			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			/* Enable non-secure access to the FPU. */
+			SecureInit_EnableNSFPUAccess();
+		}
+		#endif /* configENABLE_TRUSTZONE */
+
+		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+		 * unprivileged code should be able to access FPU. CP11 should be
+		 * programmed to the same value as CP10. */
+		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+							);
+
+		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
+		 * context on exception entry and restore on exception return.
+		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
+		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+	}
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	portDISABLE_INTERRUPTS();
+	ulCriticalNesting++;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	configASSERT( ulCriticalNesting );
+	ulCriticalNesting--;
+
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	uint32_t ulR0;
+	#if( configENABLE_MPU == 1 )
+		uint32_t ulControl, ulIsTaskPrivileged;
+	#endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
+	 * R12, LR, PC, xPSR. */
+	ulPC = pulCallerStackAddress[ 6 ];
+	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+	switch( ucSVCNumber )
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+			case portSVC_ALLOCATE_SECURE_CONTEXT:
+			{
+				/* R0 contains the stack size passed as parameter to the
+				 * vPortAllocateSecureContext function. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Read the CONTROL register value. */
+					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+					/* The task that raised the SVC is privileged if Bit[0]
+					 * in the CONTROL register is 0. */
+					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+				}
+				#else
+				{
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0 );
+				}
+				#endif /* configENABLE_MPU */
+
+				configASSERT( xSecureContext != NULL );
+				SecureContext_LoadContext( xSecureContext );
+			}
+			break;
+
+			case portSVC_FREE_SECURE_CONTEXT:
+			{
+				/* R0 contains the secure context handle to be freed. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				/* Free the secure context. */
+				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+			}
+			break;
+		#endif /* configENABLE_TRUSTZONE */
+
+		case portSVC_START_SCHEDULER:
+		{
+			#if( configENABLE_TRUSTZONE == 1 )
+			{
+				/* De-prioritize the non-secure exceptions so that the
+				 * non-secure pendSV runs at the lowest priority. */
+				SecureInit_DePrioritizeNSExceptions();
+
+				/* Initialize the secure context management system. */
+				SecureContext_Init();
+			}
+			#endif /* configENABLE_TRUSTZONE */
+
+			#if( configENABLE_FPU == 1 )
+			{
+				/* Setup the Floating Point Unit (FPU). */
+				prvSetupFPU();
+			}
+			#endif /* configENABLE_FPU */
+
+			/* Setup the context of the first task so that the first task starts
+			 * executing. */
+			vRestoreContextOfFirstTask();
+		}
+		break;
+
+		#if( configENABLE_MPU == 1 )
+			case portSVC_RAISE_PRIVILEGE:
+			{
+				/* Only raise the privilege, if the svc was raised from any of
+				 * the system calls. */
+				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+				{
+					vRaisePrivilege();
+				}
+			}
+			break;
+		#endif /* configENABLE_MPU */
+
+		default:
+		{
+			/* Incorrect SVC call. */
+			configASSERT( pdFALSE );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	 * interrupt. */
+	#if( portPRELOAD_REGISTERS == 0 )
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
+		*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#else /* portPRELOAD_REGISTERS */
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
+		pxTopOfStack--;
+		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#endif /* portPRELOAD_REGISTERS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+	#if( configENABLE_MPU == 1 )
+	{
+		/* Setup the Memory Protection Unit (MPU). */
+		prvSetupMPU();
+	}
+	#endif /* configENABLE_MPU */
+
+	/* Start the timer that generates the tick ISR. Interrupts are disabled
+	 * here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialize the critical nesting count ready for the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task. */
+	vStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing. Call the task
+	 * exit error function to prevent compiler warnings about a static function
+	 * not being called in the case that the application writer overrides this
+	 * functionality by defining configTASK_RETURN_ADDRESS. Call
+	 * vTaskSwitchContext() so link time optimization does not remove the
+	 * symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Not implemented in ports where there is nothing to return to.
+	 * Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+	{
+	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+	int32_t lIndex = 0;
+
+		/* Setup MAIR0. */
+		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+		/* This function is called automatically when the task is created - in
+		 * which case the stack region parameters will be valid.  At all other
+		 * times the stack parameters will not be valid and it is assumed that
+		 * the stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
+															( portMPU_REGION_NON_SHAREABLE ) |
+															( portMPU_REGION_READ_WRITE ) |
+															( portMPU_REGION_EXECUTE_NEVER );
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
+															( portMPU_RLAR_ATTR_INDEX0 ) |
+															( portMPU_RLAR_REGION_ENABLE );
+		}
+
+		/* User supplied configurable regions. */
+		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+		{
+			/* If xRegions is NULL i.e. the task has not specified any MPU
+			 * region, the else part ensures that all the configurable MPU
+			 * regions are invalidated. */
+			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+			{
+				/* Translate the generic region definition contained in xRegions
+				 * into the ARMv8 specific MPU settings that are then stored in
+				 * xMPUSettings. */
+				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+				/* Start address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
+																			( portMPU_REGION_NON_SHAREABLE );
+
+				/* RO/RW. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+				}
+				else
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+				}
+
+				/* XN. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+				}
+
+				/* End Address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
+																			( portMPU_RLAR_REGION_ENABLE );
+
+				/* Normal memory/ Device memory. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+				{
+					/* Attr1 in MAIR0 is configured as device memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+				}
+				else
+				{
+					/* Attr1 in MAIR0 is configured as normal memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+				}
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
new file mode 100644
index 000000000..5b8e6047a
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
@@ -0,0 +1,381 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"													\n"
+	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr  r1, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr  r0, [r1]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r4, #1										\n" /* r4 = 1. */
+	"	bics r3, r4										\n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+	"	str r3, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	"	ldr  r4, [r1]									\n" /* r4 = *r1 i.e. r4 = MAIR0. */
+	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str  r4, [r2]									\n" /* Program MAIR0. */
+	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	"	movs r4, #4										\n" /* r4 = 4. */
+	"	str  r4, [r2]									\n" /* Program RNR = 4. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read first set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write first set of RBAR/RLAR registers. */
+	"	movs r4, #5										\n" /* r4 = 5. */
+	"	str  r4, [r2]									\n" /* Program RNR = 5. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read second set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write second set of RBAR/RLAR registers. */
+	"	movs r4, #6										\n" /* r4 = 6. */
+	"	str  r4, [r2]									\n" /* Program RNR = 6. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read third set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write third set of RBAR/RLAR registers. */
+	"	movs r4, #7										\n" /* r4 = 7. */
+	"	str  r4, [r2]									\n" /* Program RNR = 7. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write fourth set of RBAR/RLAR registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r4, #1										\n" /* r4 = 1. */
+	"	orrs r3, r4										\n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+	"	str r3, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
+	"	msr  control, r2								\n" /* Set this task's CONTROL value. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
+	#else /* configENABLE_MPU */
+	"	ldm  r0!, {r1-r2}								\n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
+	"	movs r1, #2										\n" /* r1 = 2. */
+	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r2											\n" /* Finally, branch to EXC_RETURN. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst2: .word 0xe000ed94					\n"
+	"xMAIR0Const2: .word 0xe000edc0						\n"
+	"xRNRConst2: .word 0xe000ed98						\n"
+	"xRBARConst2: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	movs r1, #1										\n" /* r1 = 1. */
+	"	tst r0, r1										\n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+	"	beq running_privileged							\n" /* If the result of previous AND operation was 0, branch. */
+	"	movs r0, #0										\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	"	bx lr											\n" /* Return. */
+	" running_privileged:								\n"
+	"	movs r0, #1										\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	"	bx lr											\n" /* Return. */
+	"													\n"
+	"	.align 4										\n"
+	::: "r0", "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	 __asm volatile
+	(
+	"	mrs  r0, control								\n" /* Read the CONTROL register. */
+	"	movs r1, #1										\n" /* r1 = 1. */
+	"	bics r0, r1										\n" /* Clear the bit 0. */
+	"	msr  control, r0								\n" /* Write back the new CONTROL value. */
+	"	bx lr											\n" /* Return to the caller. */
+	::: "r0", "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	movs r1, #1										\n" /* r1 = 1. */
+	"	orrs r0, r1										\n" /* r0 = r0 | r1. */
+	"	msr control, r0									\n" /* CONTROL = r0. */
+	"	bx lr											\n" /* Return to the caller. */
+	:::"r0", "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
+	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
+	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
+	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
+	"	cpsie i											\n" /* Globally enable interrupts. */
+	"	dsb												\n"
+	"	isb												\n"
+	"	svc %0											\n" /* System call to start the first task. */
+	"	nop												\n"
+	"													\n"
+	"   .align 4										\n"
+	"xVTORConst: .word 0xe000ed08						\n"
+	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	mrs r0, PRIMASK									\n"
+	"	cpsid i											\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* To avoid compiler warnings.  The return statement will never be reached,
+	 * but some compilers warn if it is not included, while others won't compile
+	 * if it is. */
+	return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	msr PRIMASK, r0									\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* Just to avoid compiler warning.  ulMask is used from the asm code but
+	 * the compiler can't see that.  Some compilers generate warnings without
+	 * the following line, while others generate warnings if the line is
+	 * included. */
+	( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"													\n"
+	"	mrs r0, psp										\n" /* Read PSP in r0. */
+	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
+	#if( configENABLE_MPU == 1 )
+	"	subs r0, r0, #44								\n" /* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r1, psplim									\n" /* r1 = PSPLIM. */
+	"	mrs r2, control									\n" /* r2 = CONTROL. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmia r0!, {r1-r7}								\n" /* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
+	"	mov r4, r8										\n" /* r4 = r8. */
+	"	mov r5, r9										\n" /* r5 = r9. */
+	"	mov r6, r10										\n" /* r6 = r10. */
+	"	mov r7, r11										\n" /* r7 = r11. */
+	"	stmia r0!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
+	#else /* configENABLE_MPU */
+	"	subs r0, r0, #40								\n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
+	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmia r0!, {r2-r7}								\n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
+	"	mov r4, r8										\n" /* r4 = r8. */
+	"	mov r5, r9										\n" /* r5 = r9. */
+	"	mov r6, r10										\n" /* r6 = r10. */
+	"	mov r7, r11										\n" /* r7 = r11. */
+	"	stmia r0!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	cpsid i											\n"
+	"	bl vTaskSwitchContext							\n"
+	"	cpsie i											\n"
+	"													\n"
+	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr r0, [r1]									\n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r4, #1										\n" /* r4 = 1. */
+	"	bics r3, r4										\n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+	"	str r3, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	"	ldr  r4, [r1]									\n" /* r4 = *r1 i.e. r4 = MAIR0. */
+	"	ldr  r2, xMAIR0Const							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str  r4, [r2]									\n" /* Program MAIR0. */
+	"	ldr  r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	"	movs r4, #4										\n" /* r4 = 4. */
+	"	str  r4, [r2]									\n" /* Program RNR = 4. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read first set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write first set of RBAR/RLAR registers. */
+	"	movs r4, #5										\n" /* r4 = 5. */
+	"	str  r4, [r2]									\n" /* Program RNR = 5. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read second set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write second set of RBAR/RLAR registers. */
+	"	movs r4, #6										\n" /* r4 = 6. */
+	"	str  r4, [r2]									\n" /* Program RNR = 6. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read third set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write third set of RBAR/RLAR registers. */
+	"	movs r4, #7										\n" /* r4 = 7. */
+	"	str  r4, [r2]									\n" /* Program RNR = 7. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write fourth set of RBAR/RLAR registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r4, #1										\n" /* r4 = 1. */
+	"	orrs r3, r4										\n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+	"	str r3, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	adds r0, r0, #28								\n" /* Move to the high registers. */
+	"	ldmia r0!, {r4-r7}								\n" /* Restore the high registers that are not automatically restored. */
+	"	mov r8, r4										\n" /* r8 = r4. */
+	"	mov r9, r5										\n" /* r9 = r5. */
+	"	mov r10, r6										\n" /* r10 = r6. */
+	"	mov r11, r7										\n" /* r11 = r7. */
+	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
+	"	subs r0, r0, #44								\n" /* Move to the starting of the saved context. */
+	"	ldmia r0!, {r1-r7}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
+	"	msr psplim, r1									\n" /* Restore the PSPLIM register value for the task. */
+	"	msr control, r2									\n" /* Restore the CONTROL register value for the task. */
+	"	bx r3											\n"
+	#else /* configENABLE_MPU */
+	"	adds r0, r0, #24								\n" /* Move to the high registers. */
+	"	ldmia r0!, {r4-r7}								\n" /* Restore the high registers that are not automatically restored. */
+	"	mov r8, r4										\n" /* r8 = r4. */
+	"	mov r9, r5										\n" /* r9 = r5. */
+	"	mov r10, r6										\n" /* r10 = r6. */
+	"	mov r11, r7										\n" /* r11 = r7. */
+	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
+	"	subs r0, r0, #40								\n" /* Move to the starting of the saved context. */
+	"	ldmia r0!, {r2-r7}								\n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
+	"	bx r3											\n"
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst: .word 0xe000ed94					\n"
+	"xMAIR0Const: .word 0xe000edc0						\n"
+	"xRNRConst: .word 0xe000ed98						\n"
+	"xRBARConst: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	movs r0, #4										\n"
+	"	mov r1, lr										\n"
+	"	tst r0, r1										\n"
+	"	beq stacking_used_msp							\n"
+	"	mrs r0, psp										\n"
+	"	ldr r2, svchandler_address_const				\n"
+	"	bx r2											\n"
+	" stacking_used_msp:								\n"
+	"	mrs r0, msp										\n"
+	"	ldr r2, svchandler_address_const				\n"
+	"	bx r2											\n"
+	"													\n"
+	"	.align 4										\n"
+	"svchandler_address_const: .word vPortSVCHandler_C	\n"
+	);
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
new file mode 100644
index 000000000..2ecf04ea6
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
new file mode 100644
index 000000000..bbab1b7c8
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M23"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__attribute__(( used ))
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
index d7709c00f..7451feeb4 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
index 77a5d2721..f1becb381 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -233,6 +233,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
 }
 /*-----------------------------------------------------------*/
 
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
 
 #ifdef __cplusplus
 }
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/port.c
new file mode 100644
index 000000000..bd85a6ffe
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/* Secure components includes. */
+	#include "secure_context.h"
+	#include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK				( 0x00000004 )
+#define portNVIC_SYSTICK_INT				( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
+#define portNVIC_PENDSVSET					( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY			( 255UL )
+#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE				( 3UL )
+#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS					( 20UL )
+#define portCPACR_CP11_POS					( 22UL )
+
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS					( 31UL )
+#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS					( 30UL )
+#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS				( 0UL )
+#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS				( 8UL )
+#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS				( 16UL )
+#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS				( 24UL )
+#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS				( 0UL )
+#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS				( 8UL )
+#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS				( 16UL )
+#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS				( 24UL )
+#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE			( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE						( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         FD
+	 * 1111 1111  1111 1111  1111 1111  1111 1101
+	 *
+	 * Bit[6] - 1 --> The exception was taken from the Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 1 --> The exception was taken to the Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
+#else
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         BC
+	 * 1111 1111  1111 1111  1111 1111  1011 1100
+	 *
+	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS			prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS				1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT				0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Setup the Memory Protection Unit (MPU).
+	 */
+	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+	/**
+	 * @brief Setup the Floating Point Unit (FPU).
+	 */
+	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Saved as part of the task context to indicate which context the
+	 * task is using on the secure side.
+	 */
+	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Stop and reset the SysTick. */
+	*( portNVIC_SYSTICK_CTRL ) = 0UL;
+	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	 * its caller as there is nothing to return to. If a task wants to exit it
+	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
+	 * to be triggered if configASSERT() is defined, then stop here so
+	 * application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		 * started to remove a compiler warning about the function being
+		 * defined but never called.  ulDummy is used purely to quieten other
+		 * warnings about code appearing after this function is called - making
+		 * ulDummy volatile makes the compiler think the function could return
+		 * and therefore not output an 'unreachable code' warning for code that
+		 * appears after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __privileged_functions_start__;
+		extern uint32_t * __privileged_functions_end__;
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+		extern uint32_t * __unprivileged_flash_start__;
+		extern uint32_t * __unprivileged_flash_end__;
+		extern uint32_t * __privileged_sram_start__;
+		extern uint32_t * __privileged_sram_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __privileged_functions_start__[];
+		extern uint32_t __privileged_functions_end__[];
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+		extern uint32_t __unprivileged_flash_start__[];
+		extern uint32_t __unprivileged_flash_end__[];
+		extern uint32_t __privileged_sram_start__[];
+		extern uint32_t __privileged_sram_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+
+		/* Check that the MPU is present. */
+		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+		{
+			/* MAIR0 - Index 0. */
+			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+			/* MAIR0 - Index 1. */
+			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+			/* Setup privileged flash as Read Only so that privileged tasks can
+			 * read it but not modify. */
+			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged flash as Read Only by both privileged and
+			 * unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged syscalls flash as Read Only by both privileged
+			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup RAM containing kernel data for privileged access only. */
+			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+								( portMPU_REGION_EXECUTE_NEVER );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Enable mem fault. */
+			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+			/* Enable MPU with privileged background access i.e. unmapped
+			 * regions have privileged access. */
+			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			/* Enable non-secure access to the FPU. */
+			SecureInit_EnableNSFPUAccess();
+		}
+		#endif /* configENABLE_TRUSTZONE */
+
+		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+		 * unprivileged code should be able to access FPU. CP11 should be
+		 * programmed to the same value as CP10. */
+		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+							);
+
+		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
+		 * context on exception entry and restore on exception return.
+		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
+		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+	}
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	portDISABLE_INTERRUPTS();
+	ulCriticalNesting++;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	configASSERT( ulCriticalNesting );
+	ulCriticalNesting--;
+
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	uint32_t ulR0;
+	#if( configENABLE_MPU == 1 )
+		uint32_t ulControl, ulIsTaskPrivileged;
+	#endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
+	 * R12, LR, PC, xPSR. */
+	ulPC = pulCallerStackAddress[ 6 ];
+	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+	switch( ucSVCNumber )
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+			case portSVC_ALLOCATE_SECURE_CONTEXT:
+			{
+				/* R0 contains the stack size passed as parameter to the
+				 * vPortAllocateSecureContext function. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Read the CONTROL register value. */
+					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+					/* The task that raised the SVC is privileged if Bit[0]
+					 * in the CONTROL register is 0. */
+					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+				}
+				#else
+				{
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0 );
+				}
+				#endif /* configENABLE_MPU */
+
+				configASSERT( xSecureContext != NULL );
+				SecureContext_LoadContext( xSecureContext );
+			}
+			break;
+
+			case portSVC_FREE_SECURE_CONTEXT:
+			{
+				/* R0 contains the secure context handle to be freed. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				/* Free the secure context. */
+				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+			}
+			break;
+		#endif /* configENABLE_TRUSTZONE */
+
+		case portSVC_START_SCHEDULER:
+		{
+			#if( configENABLE_TRUSTZONE == 1 )
+			{
+				/* De-prioritize the non-secure exceptions so that the
+				 * non-secure pendSV runs at the lowest priority. */
+				SecureInit_DePrioritizeNSExceptions();
+
+				/* Initialize the secure context management system. */
+				SecureContext_Init();
+			}
+			#endif /* configENABLE_TRUSTZONE */
+
+			#if( configENABLE_FPU == 1 )
+			{
+				/* Setup the Floating Point Unit (FPU). */
+				prvSetupFPU();
+			}
+			#endif /* configENABLE_FPU */
+
+			/* Setup the context of the first task so that the first task starts
+			 * executing. */
+			vRestoreContextOfFirstTask();
+		}
+		break;
+
+		#if( configENABLE_MPU == 1 )
+			case portSVC_RAISE_PRIVILEGE:
+			{
+				/* Only raise the privilege, if the svc was raised from any of
+				 * the system calls. */
+				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+				{
+					vRaisePrivilege();
+				}
+			}
+			break;
+		#endif /* configENABLE_MPU */
+
+		default:
+		{
+			/* Incorrect SVC call. */
+			configASSERT( pdFALSE );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	 * interrupt. */
+	#if( portPRELOAD_REGISTERS == 0 )
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
+		*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#else /* portPRELOAD_REGISTERS */
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
+		pxTopOfStack--;
+		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#endif /* portPRELOAD_REGISTERS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+	#if( configENABLE_MPU == 1 )
+	{
+		/* Setup the Memory Protection Unit (MPU). */
+		prvSetupMPU();
+	}
+	#endif /* configENABLE_MPU */
+
+	/* Start the timer that generates the tick ISR. Interrupts are disabled
+	 * here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialize the critical nesting count ready for the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task. */
+	vStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing. Call the task
+	 * exit error function to prevent compiler warnings about a static function
+	 * not being called in the case that the application writer overrides this
+	 * functionality by defining configTASK_RETURN_ADDRESS. Call
+	 * vTaskSwitchContext() so link time optimization does not remove the
+	 * symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Not implemented in ports where there is nothing to return to.
+	 * Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+	{
+	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+	int32_t lIndex = 0;
+
+		/* Setup MAIR0. */
+		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+		/* This function is called automatically when the task is created - in
+		 * which case the stack region parameters will be valid.  At all other
+		 * times the stack parameters will not be valid and it is assumed that
+		 * the stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
+															( portMPU_REGION_NON_SHAREABLE ) |
+															( portMPU_REGION_READ_WRITE ) |
+															( portMPU_REGION_EXECUTE_NEVER );
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
+															( portMPU_RLAR_ATTR_INDEX0 ) |
+															( portMPU_RLAR_REGION_ENABLE );
+		}
+
+		/* User supplied configurable regions. */
+		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+		{
+			/* If xRegions is NULL i.e. the task has not specified any MPU
+			 * region, the else part ensures that all the configurable MPU
+			 * regions are invalidated. */
+			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+			{
+				/* Translate the generic region definition contained in xRegions
+				 * into the ARMv8 specific MPU settings that are then stored in
+				 * xMPUSettings. */
+				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+				/* Start address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
+																			( portMPU_REGION_NON_SHAREABLE );
+
+				/* RO/RW. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+				}
+				else
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+				}
+
+				/* XN. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+				}
+
+				/* End Address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
+																			( portMPU_RLAR_REGION_ENABLE );
+
+				/* Normal memory/ Device memory. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+				{
+					/* Attr1 in MAIR0 is configured as device memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+				}
+				else
+				{
+					/* Attr1 in MAIR0 is configured as normal memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+				}
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c
new file mode 100644
index 000000000..3a24f3a42
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c
@@ -0,0 +1,415 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"													\n"
+	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr  r3, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr  r0, [r3]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	"	ldr  r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
+	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str  r4, [r2]									\n" /* Program MAIR0. */
+	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	movs r4, #4										\n" /* r4 = 4. */
+	"	str  r4, [r2]									\n" /* Program RNR = 4. */
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	"	ldr  r2, xRBARConst2							\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+	"	ldmia r3!, {r4-r11}								\n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldm  r0!, {r1-r4}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+	"	ldr  r5, xSecureContextConst2					\n"
+	"	str  r1, [r5]									\n" /* Set xSecureContext to this task's value for the same. */
+	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
+	"	msr  control, r3								\n" /* Set this task's CONTROL value. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r4											\n" /* Finally, branch to EXC_RETURN. */
+	#else /* configENABLE_MPU */
+	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+	"	ldr  r4, xSecureContextConst2					\n"
+	"	str  r1, [r4]									\n" /* Set xSecureContext to this task's value for the same. */
+	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
+	"	movs r1, #2										\n" /* r1 = 2. */
+	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+	"xSecureContextConst2: .word xSecureContext			\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst2: .word 0xe000ed94					\n"
+	"xMAIR0Const2: .word 0xe000edc0						\n"
+	"xRNRConst2: .word 0xe000ed98						\n"
+	"xRBARConst2: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	tst r0, #1										\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	"	ite ne											\n"
+	"	movne r0, #0									\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	"	moveq r0, #1									\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	"	bx lr											\n" /* Return. */
+	"													\n"
+	"	.align 4										\n"
+	::: "r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	 __asm volatile
+	(
+	"	mrs r0, control									\n" /* Read the CONTROL register. */
+	"	bic r0, #1										\n" /* Clear the bit 0. */
+	"	msr control, r0									\n" /* Write back the new CONTROL value. */
+	"	bx lr											\n" /* Return to the caller. */
+	::: "r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	orr r0, #1										\n" /* r0 = r0 | 1. */
+	"	msr control, r0									\n" /* CONTROL = r0. */
+	"	bx lr											\n" /* Return to the caller. */
+	:::"r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
+	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
+	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
+	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
+	"	cpsie i											\n" /* Globally enable interrupts. */
+	"	cpsie f											\n"
+	"	dsb												\n"
+	"	isb												\n"
+	"	svc %0											\n" /* System call to start the first task. */
+	"	nop												\n"
+	"													\n"
+	"   .align 4										\n"
+	"xVTORConst: .word 0xe000ed08						\n"
+	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	mrs r0, PRIMASK									\n"
+	"	cpsid i											\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* To avoid compiler warnings.  The return statement will never be reached,
+	 * but some compilers warn if it is not included, while others won't compile
+	 * if it is. */
+	return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	msr PRIMASK, r0									\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* Just to avoid compiler warning.  ulMask is used from the asm code but
+	 * the compiler can't see that.  Some compilers generate warnings without
+	 * the following line, while others generate warnings if the line is
+	 * included. */
+	( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"	.extern SecureContext_SaveContext				\n"
+	"	.extern SecureContext_LoadContext				\n"
+	"													\n"
+	"	mrs r1, psp										\n" /* Read PSP in r1. */
+	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	"	ldr r0, [r2]									\n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+	"													\n"
+	"	cbz r0, save_ns_context							\n" /* No secure context to save. */
+	"	push {r0-r2, r14}								\n"
+	"	bl SecureContext_SaveContext					\n"
+	"	pop {r0-r3}										\n" /* LR is now in r3. */
+	"	mov lr, r3										\n" /* LR = r3. */
+	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	"	bpl save_ns_context								\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
+	#if( configENABLE_MPU == 1 )
+	"	subs r1, r1, #16								\n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mrs r3, control									\n" /* r3 = CONTROL. */
+	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
+	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+	"	subs r1, r1, #12								\n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+	#endif /* configENABLE_MPU */
+	"	b select_next_task								\n"
+	"													\n"
+	" save_ns_context:									\n"
+	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
+	#if( configENABLE_FPU == 1 )
+	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	"	it eq											\n"
+	"	vstmdbeq r1!, {s16-s31}							\n" /* Store the FPU registers which are not saved automatically. */
+	#endif /* configENABLE_FPU */
+	#if( configENABLE_MPU == 1 )
+	"	subs r1, r1, #48								\n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	adds r1, r1, #16								\n" /* r1 = r1 + 16. */
+	"	stm r1, {r4-r11}								\n" /* Store the registers that are not saved automatically. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mrs r3, control									\n" /* r3 = CONTROL. */
+	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
+	"	subs r1, r1, #16								\n" /* r1 = r1 - 16. */
+	"	stm r1, {r0, r2-r4}								\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+	"	subs r1, r1, #44								\n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	adds r1, r1, #12								\n" /* r1 = r1 + 12. */
+	"	stm r1, {r4-r11}								\n" /* Store the registers that are not saved automatically. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	subs r1, r1, #12								\n" /* r1 = r1 - 12. */
+	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	" select_next_task:									\n"
+	"	cpsid i											\n"
+	"	bl vTaskSwitchContext							\n"
+	"	cpsie i											\n"
+	"													\n"
+	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r3, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr r1, [r3]									\n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	"	ldr r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
+	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str r4, [r2]									\n" /* Program MAIR0. */
+	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	movs r4, #4										\n" /* r4 = 4. */
+	"	str r4, [r2]									\n" /* Program RNR = 4. */
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	"	ldr  r2, xRBARConst								\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+	"	ldmia r3!, {r4-r11}								\n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldmia r1!, {r0, r2-r4}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
+	"	msr control, r3									\n" /* Restore the CONTROL register value for the task. */
+	"	mov lr, r4										\n" /* LR = r4. */
+	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
+	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
+	"	push {r1,r4}									\n"
+	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
+	"	pop {r1,r4}										\n"
+	"	mov lr, r4										\n" /* LR = r4. */
+	"	lsls r2, r4, #25								\n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
+	"	bx lr											\n"
+	#else /* configENABLE_MPU */
+	"	ldmia r1!, {r0, r2-r3}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
+	"	mov lr, r3										\n" /* LR = r3. */
+	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
+	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
+	"	push {r1,r3}									\n"
+	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
+	"	pop {r1,r3}										\n"
+	"	mov lr, r3										\n" /* LR = r3. */
+	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
+	"	bx lr											\n"
+	#endif /* configENABLE_MPU */
+	"													\n"
+	" restore_ns_context:								\n"
+	"	ldmia r1!, {r4-r11}								\n" /* Restore the registers that are not automatically restored. */
+	#if( configENABLE_FPU == 1 )
+	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	"	it eq											\n"
+	"	vldmiaeq r1!, {s16-s31}							\n" /* Restore the FPU registers which are not restored automatically. */
+	#endif /* configENABLE_FPU */
+	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
+	"	bx lr											\n"
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
+	"xSecureContextConst: .word xSecureContext			\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst: .word 0xe000ed94					\n"
+	"xMAIR0Const: .word 0xe000edc0						\n"
+	"xRNRConst: .word 0xe000ed98						\n"
+	"xRBARConst: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	tst lr, #4										\n"
+	"	ite eq											\n"
+	"	mrseq r0, msp									\n"
+	"	mrsne r0, psp									\n"
+	"	ldr r1, svchandler_address_const				\n"
+	"	bx r1											\n"
+	"													\n"
+	"	.align 4										\n"
+	"svchandler_address_const: .word vPortSVCHandler_C	\n"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	svc %0											\n" /* Secure context is allocated in the supervisor call. */
+	"	bx lr											\n" /* Return. */
+	:: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	ldr r1, [r0]									\n" /* The first item in the TCB is the top of the stack. */
+	"	ldr r0, [r1]									\n" /* The first item on the stack is the task's xSecureContext. */
+	"	cmp r0, #0										\n" /* Raise svc if task's xSecureContext is not NULL. */
+	"	it ne											\n"
+	"	svcne %0										\n" /* Secure context is freed in the supervisor call. */
+	"	bx lr											\n" /* Return. */
+	:: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.h
new file mode 100644
index 000000000..2ecf04ea6
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h
new file mode 100644
index 000000000..d051ddcef
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M33"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__attribute__(( used ))
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.c
new file mode 100644
index 000000000..53535cd9e
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.c
@@ -0,0 +1,204 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
+	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
+	uint8_t *pucStackStart;				/**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+	uint32_t ulIPSR;
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* No stack for thread mode until a task's context is loaded. */
+		secureportSET_PSPLIM( securecontextNO_STACK );
+		secureportSET_PSP( securecontextNO_STACK );
+
+		#if( configENABLE_MPU == 1 )
+		{
+			/* Configure thread mode to use PSP and to be unprivileged. */
+			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+		}
+		#else /* configENABLE_MPU */
+		{
+			/* Configure thread mode to use PSP and to be privileged.. */
+			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+		}
+		#endif /* configENABLE_MPU */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+	uint8_t *pucStackMemory = NULL;
+	uint32_t ulIPSR;
+	SecureContextHandle_t xSecureContextHandle = NULL;
+	#if( configENABLE_MPU == 1 )
+		uint32_t *pulCurrentStackPointer = NULL;
+	#endif /* configENABLE_MPU */
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* Allocate the context structure. */
+		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+		if( xSecureContextHandle != NULL )
+		{
+			/* Allocate the stack space. */
+			pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+			if( pucStackMemory != NULL )
+			{
+				/* Since stack grows down, the starting point will be the last
+				 * location. Note that this location is next to the last
+				 * allocated byte because the hardware decrements the stack
+				 * pointer before writing i.e. if stack pointer is 0x2, a push
+				 * operation will decrement the stack pointer to 0x1 and then
+				 * write at 0x1. */
+				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+				/* The stack cannot go beyond this location. This value is
+				 * programmed in the PSPLIM register on context switch.*/
+				xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Store the correct CONTROL value for the task on the stack.
+					 * This value is programmed in the CONTROL register on
+					 * context switch. */
+					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+					pulCurrentStackPointer--;
+					if( ulIsTaskPrivileged )
+					{
+						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+					}
+					else
+					{
+						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+					}
+
+					/* Store the current stack pointer. This value is programmed in
+					 * the PSP register on context switch. */
+					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+				}
+				#else /* configENABLE_MPU */
+				{
+					/* Current SP is set to the starting of the stack. This
+					 * value programmed in the PSP register on context switch. */
+					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+
+				}
+				#endif /* configENABLE_MPU */
+			}
+			else
+			{
+				/* Free the context to avoid memory leak and make sure to return
+				 * NULL to indicate failure. */
+				vPortFree( xSecureContextHandle );
+				xSecureContextHandle = NULL;
+			}
+		}
+	}
+
+	return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+	uint32_t ulIPSR;
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* Ensure that valid parameters are passed. */
+		secureportASSERT( xSecureContextHandle != NULL );
+
+		/* Free the stack space. */
+		vPortFree( xSecureContextHandle->pucStackLimit );
+
+		/* Free the context itself. */
+		vPortFree( xSecureContextHandle );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.h
new file mode 100644
index 000000000..e148bff8e
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.h
@@ -0,0 +1,111 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include 
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK	0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext*	SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if( configENABLE_MPU == 1 )
+	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
new file mode 100644
index 000000000..7c556f57a
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
@@ -0,0 +1,88 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+	/* xSecureContextHandle value is in r0. */
+	__asm volatile
+	(
+	"	.syntax unified							\n"
+	"											\n"
+	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
+	"	cbz r1, load_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
+	"	ldmia r0!, {r1, r2}						\n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+	#if( configENABLE_MPU == 1 )
+	"	ldmia r1!, {r3}							\n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+	"	msr control, r3							\n" /* CONTROL = r3. */
+	#endif /* configENABLE_MPU */
+	"	msr psplim, r2							\n" /* PSPLIM = r2. */
+	"	msr psp, r1								\n" /* PSP = r1. */
+	"											\n"
+	" load_ctx_therad_mode:						\n"
+	"	nop										\n"
+	"											\n"
+	:::"r0", "r1", "r2"
+	);
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+	/* xSecureContextHandle value is in r0. */
+	__asm volatile
+	(
+	"	.syntax unified							\n"
+	"											\n"
+	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
+	"	cbz r1, save_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
+	"	mrs r1, psp								\n" /* r1 = PSP. */
+	#if( configENABLE_FPU == 1 )
+	"	vstmdb r1!, {s0}						\n" /* Trigger the defferred stacking of FPU registers. */
+	"	vldmia r1!, {s0}						\n" /* Nullify the effect of the pervious statement. */
+	#endif /* configENABLE_FPU */
+	#if( configENABLE_MPU == 1 )
+	"	mrs r2, control							\n" /* r2 = CONTROL. */
+	"	stmdb r1!, {r2}							\n" /* Store CONTROL value on the stack. */
+	#endif /* configENABLE_MPU */
+	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	"	movs r1, %0								\n" /* r1 = securecontextNO_STACK. */
+	"	msr psplim, r1							\n" /* PSPLIM = securecontextNO_STACK. */
+	"	msr psp, r1								\n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+	"											\n"
+	" save_ctx_therad_mode:						\n"
+	"	nop										\n"
+	"											\n"
+	:: "i" ( securecontextNO_STACK ) : "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.c
new file mode 100644
index 000000000..60fce5c66
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.c
@@ -0,0 +1,450 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+	#define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+	#define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+	#define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	 * heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
+	size_t xBlockSize;						/**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	 * blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	 * at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	 * entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	 * than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	 * make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	 * make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	 * before and the block after, then it's pxNextFreeBlock pointer will have
+	 * already been set, and should not be set here as that would make it point
+	 * to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	/* If this is the first call to malloc then the heap will require
+	 * initialisation to setup the list of free blocks. */
+	if( pxEnd == NULL )
+	{
+		prvHeapInit();
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Check the requested block size is not so large that the top bit is set.
+	 * The top bit of the block size member of the BlockLink_t structure is used
+	 * to determine who owns the block - the application or the kernel, so it
+	 * must be free. */
+	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+	{
+		/* The wanted size is increased so it can contain a BlockLink_t
+		 * structure in addition to the requested amount of bytes. */
+		if( xWantedSize > 0 )
+		{
+			xWantedSize += xHeapStructSize;
+
+			/* Ensure that blocks are always aligned to the required number of
+			 * bytes. */
+			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+			{
+				/* Byte alignment required. */
+				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+		{
+			/* Traverse the list from the start (lowest address) block until
+			 * one of adequate size is found. */
+			pxPreviousBlock = &xStart;
+			pxBlock = xStart.pxNextFreeBlock;
+			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+			{
+				pxPreviousBlock = pxBlock;
+				pxBlock = pxBlock->pxNextFreeBlock;
+			}
+
+			/* If the end marker was reached then a block of adequate size was
+			 * not found. */
+			if( pxBlock != pxEnd )
+			{
+				/* Return the memory space pointed to - jumping over the
+				 * BlockLink_t structure at its start. */
+				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+				/* This block is being returned for use so must be taken out
+				 * of the list of free blocks. */
+				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+				/* If the block is larger than required it can be split into
+				 * two. */
+				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+				{
+					/* This block is to be split into two.  Create a new
+					 * block following the number of bytes requested. The void
+					 * cast is used to prevent byte alignment warnings from the
+					 * compiler. */
+					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+					/* Calculate the sizes of two blocks split from the single
+					 * block. */
+					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+					pxBlock->xBlockSize = xWantedSize;
+
+					/* Insert the new block into the list of free blocks. */
+					prvInsertBlockIntoFreeList( pxNewBlockLink );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+				{
+					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* The block is being returned - it is allocated and owned by
+				 * the application and has no "next" block. */
+				pxBlock->xBlockSize |= xBlockAllocatedBit;
+				pxBlock->pxNextFreeBlock = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceMALLOC( pvReturn, xWantedSize );
+
+	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		 * before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				 * allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				secureportDISABLE_NON_SECURE_INTERRUPTS();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+				}
+				secureportENABLE_NON_SECURE_INTERRUPTS();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.h
new file mode 100644
index 000000000..69e4f2a86
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include 
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void *pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void *pv );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.c
new file mode 100644
index 000000000..c6525f755
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS			( 29UL )
+#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS				( 26UL )
+#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS			( 10UL )
+#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS			( 11UL )
+#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+	uint32_t ulIPSR;
+
+	 /* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
+	}
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+	uint32_t ulIPSR;
+
+	 /* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+		 * permitted. CP11 should be programmed to the same value as CP10. */
+		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+		 * that we can enable/disable lazy stacking in port.c file. */
+		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
+
+		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+		 * registers (S16-S31) are also pushed to stack on exception entry and
+		 * restored on exception return. */
+		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.h
new file mode 100644
index 000000000..6c5bc71f5
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h
new file mode 100644
index 000000000..760edab56
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT					8
+#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
+#else
+	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x )						\
+	if( ( x ) == 0 )								\
+	{												\
+		secureportDISABLE_SECURE_INTERRUPTS();		\
+		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
+		for( ;; );									\
+	}
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
new file mode 100644
index 000000000..bd85a6ffe
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/* Secure components includes. */
+	#include "secure_context.h"
+	#include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK				( 0x00000004 )
+#define portNVIC_SYSTICK_INT				( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
+#define portNVIC_PENDSVSET					( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY			( 255UL )
+#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE				( 3UL )
+#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS					( 20UL )
+#define portCPACR_CP11_POS					( 22UL )
+
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS					( 31UL )
+#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS					( 30UL )
+#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS				( 0UL )
+#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS				( 8UL )
+#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS				( 16UL )
+#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS				( 24UL )
+#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS				( 0UL )
+#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS				( 8UL )
+#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS				( 16UL )
+#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS				( 24UL )
+#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE			( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE						( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         FD
+	 * 1111 1111  1111 1111  1111 1111  1111 1101
+	 *
+	 * Bit[6] - 1 --> The exception was taken from the Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 1 --> The exception was taken to the Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
+#else
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         BC
+	 * 1111 1111  1111 1111  1111 1111  1011 1100
+	 *
+	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS			prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS				1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT				0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Setup the Memory Protection Unit (MPU).
+	 */
+	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+	/**
+	 * @brief Setup the Floating Point Unit (FPU).
+	 */
+	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Saved as part of the task context to indicate which context the
+	 * task is using on the secure side.
+	 */
+	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Stop and reset the SysTick. */
+	*( portNVIC_SYSTICK_CTRL ) = 0UL;
+	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	 * its caller as there is nothing to return to. If a task wants to exit it
+	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
+	 * to be triggered if configASSERT() is defined, then stop here so
+	 * application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		 * started to remove a compiler warning about the function being
+		 * defined but never called.  ulDummy is used purely to quieten other
+		 * warnings about code appearing after this function is called - making
+		 * ulDummy volatile makes the compiler think the function could return
+		 * and therefore not output an 'unreachable code' warning for code that
+		 * appears after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __privileged_functions_start__;
+		extern uint32_t * __privileged_functions_end__;
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+		extern uint32_t * __unprivileged_flash_start__;
+		extern uint32_t * __unprivileged_flash_end__;
+		extern uint32_t * __privileged_sram_start__;
+		extern uint32_t * __privileged_sram_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __privileged_functions_start__[];
+		extern uint32_t __privileged_functions_end__[];
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+		extern uint32_t __unprivileged_flash_start__[];
+		extern uint32_t __unprivileged_flash_end__[];
+		extern uint32_t __privileged_sram_start__[];
+		extern uint32_t __privileged_sram_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+
+		/* Check that the MPU is present. */
+		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+		{
+			/* MAIR0 - Index 0. */
+			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+			/* MAIR0 - Index 1. */
+			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+			/* Setup privileged flash as Read Only so that privileged tasks can
+			 * read it but not modify. */
+			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged flash as Read Only by both privileged and
+			 * unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged syscalls flash as Read Only by both privileged
+			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup RAM containing kernel data for privileged access only. */
+			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+								( portMPU_REGION_EXECUTE_NEVER );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Enable mem fault. */
+			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+			/* Enable MPU with privileged background access i.e. unmapped
+			 * regions have privileged access. */
+			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			/* Enable non-secure access to the FPU. */
+			SecureInit_EnableNSFPUAccess();
+		}
+		#endif /* configENABLE_TRUSTZONE */
+
+		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+		 * unprivileged code should be able to access FPU. CP11 should be
+		 * programmed to the same value as CP10. */
+		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+							);
+
+		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
+		 * context on exception entry and restore on exception return.
+		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
+		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+	}
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	portDISABLE_INTERRUPTS();
+	ulCriticalNesting++;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	configASSERT( ulCriticalNesting );
+	ulCriticalNesting--;
+
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	uint32_t ulR0;
+	#if( configENABLE_MPU == 1 )
+		uint32_t ulControl, ulIsTaskPrivileged;
+	#endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
+	 * R12, LR, PC, xPSR. */
+	ulPC = pulCallerStackAddress[ 6 ];
+	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+	switch( ucSVCNumber )
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+			case portSVC_ALLOCATE_SECURE_CONTEXT:
+			{
+				/* R0 contains the stack size passed as parameter to the
+				 * vPortAllocateSecureContext function. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Read the CONTROL register value. */
+					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+					/* The task that raised the SVC is privileged if Bit[0]
+					 * in the CONTROL register is 0. */
+					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+				}
+				#else
+				{
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0 );
+				}
+				#endif /* configENABLE_MPU */
+
+				configASSERT( xSecureContext != NULL );
+				SecureContext_LoadContext( xSecureContext );
+			}
+			break;
+
+			case portSVC_FREE_SECURE_CONTEXT:
+			{
+				/* R0 contains the secure context handle to be freed. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				/* Free the secure context. */
+				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+			}
+			break;
+		#endif /* configENABLE_TRUSTZONE */
+
+		case portSVC_START_SCHEDULER:
+		{
+			#if( configENABLE_TRUSTZONE == 1 )
+			{
+				/* De-prioritize the non-secure exceptions so that the
+				 * non-secure pendSV runs at the lowest priority. */
+				SecureInit_DePrioritizeNSExceptions();
+
+				/* Initialize the secure context management system. */
+				SecureContext_Init();
+			}
+			#endif /* configENABLE_TRUSTZONE */
+
+			#if( configENABLE_FPU == 1 )
+			{
+				/* Setup the Floating Point Unit (FPU). */
+				prvSetupFPU();
+			}
+			#endif /* configENABLE_FPU */
+
+			/* Setup the context of the first task so that the first task starts
+			 * executing. */
+			vRestoreContextOfFirstTask();
+		}
+		break;
+
+		#if( configENABLE_MPU == 1 )
+			case portSVC_RAISE_PRIVILEGE:
+			{
+				/* Only raise the privilege, if the svc was raised from any of
+				 * the system calls. */
+				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+				{
+					vRaisePrivilege();
+				}
+			}
+			break;
+		#endif /* configENABLE_MPU */
+
+		default:
+		{
+			/* Incorrect SVC call. */
+			configASSERT( pdFALSE );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	 * interrupt. */
+	#if( portPRELOAD_REGISTERS == 0 )
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
+		*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#else /* portPRELOAD_REGISTERS */
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
+		pxTopOfStack--;
+		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#endif /* portPRELOAD_REGISTERS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+	#if( configENABLE_MPU == 1 )
+	{
+		/* Setup the Memory Protection Unit (MPU). */
+		prvSetupMPU();
+	}
+	#endif /* configENABLE_MPU */
+
+	/* Start the timer that generates the tick ISR. Interrupts are disabled
+	 * here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialize the critical nesting count ready for the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task. */
+	vStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing. Call the task
+	 * exit error function to prevent compiler warnings about a static function
+	 * not being called in the case that the application writer overrides this
+	 * functionality by defining configTASK_RETURN_ADDRESS. Call
+	 * vTaskSwitchContext() so link time optimization does not remove the
+	 * symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Not implemented in ports where there is nothing to return to.
+	 * Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+	{
+	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+	int32_t lIndex = 0;
+
+		/* Setup MAIR0. */
+		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+		/* This function is called automatically when the task is created - in
+		 * which case the stack region parameters will be valid.  At all other
+		 * times the stack parameters will not be valid and it is assumed that
+		 * the stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
+															( portMPU_REGION_NON_SHAREABLE ) |
+															( portMPU_REGION_READ_WRITE ) |
+															( portMPU_REGION_EXECUTE_NEVER );
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
+															( portMPU_RLAR_ATTR_INDEX0 ) |
+															( portMPU_RLAR_REGION_ENABLE );
+		}
+
+		/* User supplied configurable regions. */
+		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+		{
+			/* If xRegions is NULL i.e. the task has not specified any MPU
+			 * region, the else part ensures that all the configurable MPU
+			 * regions are invalidated. */
+			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+			{
+				/* Translate the generic region definition contained in xRegions
+				 * into the ARMv8 specific MPU settings that are then stored in
+				 * xMPUSettings. */
+				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+				/* Start address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
+																			( portMPU_REGION_NON_SHAREABLE );
+
+				/* RO/RW. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+				}
+				else
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+				}
+
+				/* XN. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+				}
+
+				/* End Address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
+																			( portMPU_RLAR_REGION_ENABLE );
+
+				/* Normal memory/ Device memory. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+				{
+					/* Attr1 in MAIR0 is configured as device memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+				}
+				else
+				{
+					/* Attr1 in MAIR0 is configured as normal memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+				}
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
new file mode 100644
index 000000000..ba4a69ccb
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
@@ -0,0 +1,321 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"													\n"
+	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr  r1, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr  r0, [r1]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	"	ldr  r3, [r1]									\n" /* r3 = *r1 i.e. r3 = MAIR0. */
+	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str  r3, [r2]									\n" /* Program MAIR0. */
+	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	movs r3, #4										\n" /* r3 = 4. */
+	"	str  r3, [r2]									\n" /* Program RNR = 4. */
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	"	ldr  r2, xRBARConst2							\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+	"	ldmia r1!, {r4-r11}								\n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
+	"	msr  control, r2								\n" /* Set this task's CONTROL value. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
+	#else /* configENABLE_MPU */
+	"	ldm  r0!, {r1-r2}								\n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
+	"	movs r1, #2										\n" /* r1 = 2. */
+	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r2											\n" /* Finally, branch to EXC_RETURN. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst2: .word 0xe000ed94					\n"
+	"xMAIR0Const2: .word 0xe000edc0						\n"
+	"xRNRConst2: .word 0xe000ed98						\n"
+	"xRBARConst2: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	tst r0, #1										\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	"	ite ne											\n"
+	"	movne r0, #0									\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	"	moveq r0, #1									\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	"	bx lr											\n" /* Return. */
+	"													\n"
+	"	.align 4										\n"
+	::: "r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	 __asm volatile
+	(
+	"	mrs  r0, control								\n" /* Read the CONTROL register. */
+	"	bic r0, #1										\n" /* Clear the bit 0. */
+	"	msr  control, r0								\n" /* Write back the new CONTROL value. */
+	"	bx lr											\n" /* Return to the caller. */
+	::: "r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	orr r0, #1										\n" /* r0 = r0 | 1. */
+	"	msr control, r0									\n" /* CONTROL = r0. */
+	"	bx lr											\n" /* Return to the caller. */
+	:::"r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
+	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
+	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
+	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
+	"	cpsie i											\n" /* Globally enable interrupts. */
+	"	cpsie f											\n"
+	"	dsb												\n"
+	"	isb												\n"
+	"	svc %0											\n" /* System call to start the first task. */
+	"	nop												\n"
+	"													\n"
+	"   .align 4										\n"
+	"xVTORConst: .word 0xe000ed08						\n"
+	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	mrs r0, PRIMASK									\n"
+	"	cpsid i											\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* To avoid compiler warnings.  The return statement will never be reached,
+	 * but some compilers warn if it is not included, while others won't compile
+	 * if it is. */
+	return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	msr PRIMASK, r0									\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* Just to avoid compiler warning.  ulMask is used from the asm code but
+	 * the compiler can't see that.  Some compilers generate warnings without
+	 * the following line, while others generate warnings if the line is
+	 * included. */
+	( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"													\n"
+	"	mrs r0, psp										\n" /* Read PSP in r0. */
+	#if( configENABLE_FPU == 1 )
+	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	"	it eq											\n"
+	"	vstmdbeq r0!, {s16-s31}							\n" /* Store the FPU registers which are not saved automatically. */
+	#endif /* configENABLE_FPU */
+	#if( configENABLE_MPU == 1 )
+	"	mrs r1, psplim									\n" /* r1 = PSPLIM. */
+	"	mrs r2, control									\n" /* r2 = CONTROL. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmdb r0!, {r1-r11}								\n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+	#else /* configENABLE_MPU */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmdb r0!, {r2-r11}								\n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
+	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
+	"													\n"
+	"	cpsid i											\n"
+	"	bl vTaskSwitchContext							\n"
+	"	cpsie i											\n"
+	"													\n"
+	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr r0, [r1]									\n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	"	ldr r3, [r1]									\n" /* r3 = *r1 i.e. r3 = MAIR0. */
+	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str r3, [r2]									\n" /* Program MAIR0. */
+	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	movs r3, #4										\n" /* r3 = 4. */
+	"	str r3, [r2]									\n" /* Program RNR = 4. */
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	"	ldr r2, xRBARConst								\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+	"	ldmia r1!, {r4-r11}								\n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldmia r0!, {r1-r11}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+	#else /* configENABLE_MPU */
+	"	ldmia r0!, {r2-r11}								\n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_FPU == 1 )
+	"	tst r3, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	"	it eq											\n"
+	"	vldmiaeq r0!, {s16-s31}							\n" /* Restore the FPU registers which are not restored automatically. */
+	#endif /* configENABLE_FPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	msr psplim, r1									\n" /* Restore the PSPLIM register value for the task. */
+	"	msr control, r2									\n" /* Restore the CONTROL register value for the task. */
+	#else /* configENABLE_MPU */
+	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
+	#endif /* configENABLE_MPU */
+	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
+	"	bx r3											\n"
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst: .word 0xe000ed94					\n"
+	"xMAIR0Const: .word 0xe000edc0						\n"
+	"xRNRConst: .word 0xe000ed98						\n"
+	"xRBARConst: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	tst lr, #4										\n"
+	"	ite eq											\n"
+	"	mrseq r0, msp									\n"
+	"	mrsne r0, psp									\n"
+	"	ldr r1, svchandler_address_const				\n"
+	"	bx r1											\n"
+	"													\n"
+	"	.align 4										\n"
+	"svchandler_address_const: .word vPortSVCHandler_C	\n"
+	);
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
new file mode 100644
index 000000000..2ecf04ea6
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
new file mode 100644
index 000000000..d051ddcef
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M33"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__attribute__(( used ))
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c
index 39cfbfce1..454f90f0c 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -114,13 +114,6 @@ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
  */
 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
 
-/*
- * Checks to see if being called from the context of an unprivileged task, and
- * if so raises the privilege level and returns false - otherwise does nothing
- * other than return true.
- */
-BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));
-
 /*
  * Setup the timer to generate the tick interrupts.  The implementation in this
  * file is weak to allow application writers to change the timer used to
@@ -146,6 +139,35 @@ static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVIL
  */
 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;
 
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
 /*-----------------------------------------------------------*/
 
 /* Each task maintains its own interrupt status in the critical nesting
@@ -585,21 +607,33 @@ uint32_t ulRegionSize, ulReturnValue = 4;
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t xPortRaisePrivilege( void )
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
 {
 	__asm volatile
 	(
-		"	mrs r0, control						\n"
-		"	tst r0, #1							\n" /* Is the task running privileged? */
-		"	itte ne								\n"
-		"	movne r0, #0						\n" /* CONTROL[0]!=0, return false. */
-		"	svcne %0							\n" /* Switch to privileged. */
-		"	moveq r0, #1						\n" /* CONTROL[0]==0, return true. */
-		"	bx lr								\n"
-		:: "i" (portSVC_RAISE_PRIVILEGE) : "r0", "memory"
+	"	mrs r0, control							\n" /* r0 = CONTROL. */
+	"	tst r0, #1								\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	"	ite ne									\n"
+	"	movne r0, #0							\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	"	moveq r0, #1							\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	"	bx lr									\n" /* Return. */
+	"											\n"
+	"	.align 4								\n"
+	::: "r0", "memory"
 	);
+}
+/*-----------------------------------------------------------*/
 
-	return 0;
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control							\n" /* r0 = CONTROL. */
+	"	orr r0, #1								\n" /* r0 = r0 | 1. */
+	"	msr control, r0							\n" /* CONTROL = r0. */
+	"	bx lr									\n" /* Return to the caller. */
+	:::"r0", "memory"
+	);
 }
 /*-----------------------------------------------------------*/
 
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
index 6057f1c0e..3458b0e0f 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -200,18 +200,28 @@ not necessary for to use this port.  They are defined so the common demo files
 #ifndef portFORCE_INLINE
 	#define portFORCE_INLINE inline __attribute__(( always_inline))
 #endif
+/*-----------------------------------------------------------*/
 
-/* Set the privilege level to user mode if xRunningPrivileged is false. */
-portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged )
-{
-	if( xRunningPrivileged != pdTRUE )
-	{
-		__asm volatile ( " mrs r0, control 	\n" \
-						 " orr r0, #1 		\n" \
-						 " msr control, r0	\n"	\
-						 :::"r0", "memory" );
-	}
-}
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED()			xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+*/
+#define portRAISE_PRIVILEGE()		__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE()		vResetPrivilege()
 /*-----------------------------------------------------------*/
 
 portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
@@ -281,6 +291,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
 }
 /*-----------------------------------------------------------*/
 
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
 
 #ifdef __cplusplus
 }
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
index ae96b4ca2..a065abffc 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
index 1a9501612..fd31d2265 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -233,6 +233,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
 }
 /*-----------------------------------------------------------*/
 
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
 
 #ifdef __cplusplus
 }
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c
index 5a881f465..9c6817858 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -123,13 +123,6 @@ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
  */
 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
 
-/*
- * Checks to see if being called from the context of an unprivileged task, and
- * if so raises the privilege level and returns false - otherwise does nothing
- * other than return true.
- */
-BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));
-
 /*
  * Setup the timer to generate the tick interrupts.  The implementation in this
  * file is weak to allow application writers to change the timer used to
@@ -160,6 +153,35 @@ static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline ))
  */
  static void vPortEnableVFP( void ) __attribute__ (( naked ));
 
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
 /*-----------------------------------------------------------*/
 
 /* Each task maintains its own interrupt status in the critical nesting
@@ -573,7 +595,7 @@ extern uint32_t __privileged_data_end__[];
 										( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
 										( portMPU_REGION_ENABLE );
 
-		/* Setup the first 16K for privileged only access (even though less
+		/* Setup the first nK for privileged only access (even though less
 		than 10K is actually being used).  This is where the kernel code is
 		placed. */
 		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
@@ -639,21 +661,33 @@ uint32_t ulRegionSize, ulReturnValue = 4;
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t xPortRaisePrivilege( void )
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
 {
 	__asm volatile
 	(
-		"	mrs r0, control						\n"
-		"	tst r0, #1							\n" /* Is the task running privileged? */
-		"	itte ne								\n"
-		"	movne r0, #0						\n" /* CONTROL[0]!=0, return false. */
-		"	svcne %0							\n" /* Switch to privileged. */
-		"	moveq r0, #1						\n" /* CONTROL[0]==0, return true. */
-		"	bx lr								\n"
-		:: "i" (portSVC_RAISE_PRIVILEGE) : "r0", "memory"
+	"	mrs r0, control							\n" /* r0 = CONTROL. */
+	"	tst r0, #1								\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	"	ite ne									\n"
+	"	movne r0, #0							\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	"	moveq r0, #1							\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	"	bx lr									\n" /* Return. */
+	"											\n"
+	"	.align 4								\n"
+	::: "r0", "memory"
 	);
+}
+/*-----------------------------------------------------------*/
 
-	return 0;
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control							\n" /* r0 = CONTROL. */
+	"	orr r0, #1								\n" /* r0 = r0 | 1. */
+	"	msr control, r0							\n" /* CONTROL = r0. */
+	"	bx lr									\n" /* Return to the caller. */
+	:::"r0", "memory"
+	);
 }
 /*-----------------------------------------------------------*/
 
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
index 6057f1c0e..3458b0e0f 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -200,18 +200,28 @@ not necessary for to use this port.  They are defined so the common demo files
 #ifndef portFORCE_INLINE
 	#define portFORCE_INLINE inline __attribute__(( always_inline))
 #endif
+/*-----------------------------------------------------------*/
 
-/* Set the privilege level to user mode if xRunningPrivileged is false. */
-portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged )
-{
-	if( xRunningPrivileged != pdTRUE )
-	{
-		__asm volatile ( " mrs r0, control 	\n" \
-						 " orr r0, #1 		\n" \
-						 " msr control, r0	\n"	\
-						 :::"r0", "memory" );
-	}
-}
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED()			xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+*/
+#define portRAISE_PRIVILEGE()		__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE()		vResetPrivilege()
 /*-----------------------------------------------------------*/
 
 portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
@@ -281,6 +291,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
 }
 /*-----------------------------------------------------------*/
 
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
 
 #ifdef __cplusplus
 }
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
index 325264d61..ce867ee67 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
index 5f912ae70..62543ac74 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -237,6 +237,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
 }
 /*-----------------------------------------------------------*/
 
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
 
 #ifdef __cplusplus
 }
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7_MPU/r0p1/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7_MPU/r0p1/port.c
index 1243f476f..84d0e5e46 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7_MPU/r0p1/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7_MPU/r0p1/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -47,12 +47,18 @@ task.h is included from an application file. */
 
 #ifndef configSYSTICK_CLOCK_HZ
 	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK	( 0 )
 #endif
 
 /* Constants required to access and manipulate the NVIC. */
 #define portNVIC_SYSTICK_CTRL_REG				( * ( ( volatile uint32_t * ) 0xe000e010 ) )
 #define portNVIC_SYSTICK_LOAD_REG				( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG	    ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG		( * ( ( volatile uint32_t * ) 0xe000e018 ) )
 #define portNVIC_SYSPRI2_REG					( *	( ( volatile uint32_t * ) 0xe000ed20 ) )
 #define portNVIC_SYSPRI1_REG					( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
 #define portNVIC_SYS_CTRL_STATE_REG				( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
@@ -73,9 +79,7 @@ task.h is included from an application file. */
 #define portPERIPHERALS_END_ADDRESS				0x5FFFFFFFUL
 
 /* Constants required to access and manipulate the SysTick. */
-#define portNVIC_SYSTICK_CLK					( 0x00000004UL )
 #define portNVIC_SYSTICK_INT					( 0x00000002UL )
-#define portNVIC_SYSTICK_COUNT_FLAG      		( 1UL << 16UL )
 #define portNVIC_SYSTICK_ENABLE					( 0x00000001UL )
 #define portNVIC_PENDSV_PRI						( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
 #define portNVIC_SYSTICK_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
@@ -87,7 +91,7 @@ task.h is included from an application file. */
 
 /* Constants required to set up the initial stack. */
 #define portINITIAL_XPSR						( 0x01000000UL )
-#define portINITIAL_EXEC_RETURN					( 0xfffffffdUL )
+#define portINITIAL_EXC_RETURN					( 0xfffffffdUL )
 #define portINITIAL_CONTROL_IF_UNPRIVILEGED		( 0x03 )
 #define portINITIAL_CONTROL_IF_PRIVILEGED		( 0x02 )
 
@@ -141,11 +145,11 @@ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
 
 /*
- * Checks to see if being called from the context of an unprivileged task, and
- * if so raises the privilege level and returns false - otherwise does nothing
- * other than return true.
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
  */
-BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));
+void vPortSetupTimerInterrupt( void );
 
 /*
  * Standard FreeRTOS exception handlers.
@@ -169,29 +173,42 @@ static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline ))
  * Function to enable the VFP.
  */
  static void vPortEnableVFP( void ) __attribute__ (( naked ));
- 
-/*
- * The number of SysTick increments that make up one tick period.
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
  */
-#if configUSE_TICKLESS_IDLE == 1
-	static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
 
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
  */
-#if configUSE_TICKLESS_IDLE == 1
-	static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
+void vResetPrivilege( void ) __attribute__ (( naked ));
 
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
  */
-#if configUSE_TICKLESS_IDLE == 1
-	static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable.  Note this is not saved as part of the task context as context
+switches can only occur when uxCriticalNesting is zero. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
 
 /*
  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
@@ -221,12 +238,12 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 	*pxTopOfStack = 0;	/* LR */
 	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
 	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-	
+
 	/* A save method is being used that requires each task to maintain its
 	own exec return value. */
 	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_EXEC_RETURN;
-	
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
 	pxTopOfStack -= 9;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
 
 	if( xRunPrivileged == pdTRUE )
@@ -256,7 +273,7 @@ void vPortSVCHandler( void )
 			"	mrs r0, psp						\n"
 		#endif
 			"	b %0							\n"
-			::"i"(prvSVCHandler):"r0"
+			::"i"(prvSVCHandler):"r0", "memory"
 	);
 }
 /*-----------------------------------------------------------*/
@@ -279,7 +296,7 @@ uint8_t ucSVCNumber;
 											but do ensure the code is completely
 											within the specified behaviour for the
 											architecture. */
-											__asm volatile( "dsb" );
+											__asm volatile( "dsb" ::: "memory" );
 											__asm volatile( "isb" );
 
 											break;
@@ -289,7 +306,7 @@ uint8_t ucSVCNumber;
 												"	mrs r1, control		\n" /* Obtain current control value. */
 												"	bic r1, #1			\n" /* Set privilege bit. */
 												"	msr control, r1		\n" /* Write back new control value. */
-												:::"r1"
+												::: "r1", "memory"
 											);
 											break;
 
@@ -369,6 +386,24 @@ BaseType_t xPortStartScheduler( void )
 			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
 		}
 
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
 		/* Shift the priority group value back to its position within the AIRCR
 		register. */
 		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
@@ -402,19 +437,24 @@ BaseType_t xPortStartScheduler( void )
 	/* Lazy save always. */
 	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
 
-	/* Start the first task. */
+	/* Start the first task.  This also clears the bit that indicates the FPU is
+	in use in case the FPU was used before the scheduler was started - which
+	would otherwise result in the unnecessary leaving of space in the SVC stack
+	for lazy saving of FPU registers. */
 	__asm volatile(
 					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
 					" ldr r0, [r0] 			\n"
 					" ldr r0, [r0] 			\n"
 					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
+					" mov r0, #0			\n" /* Clear the bit that indicates the FPU is in use, see comment above. */
+					" msr control, r0		\n"
 					" cpsie i				\n" /* Globally enable interrupts. */
 					" cpsie f				\n"
 					" dsb					\n"
 					" isb					\n"
 					" svc %0				\n" /* System call to start first task. */
 					" nop					\n"
-					:: "i" (portSVC_START_SCHEDULER) );
+					:: "i" (portSVC_START_SCHEDULER) : "memory" );
 
 	/* Should not get here! */
 	return 0;
@@ -461,6 +501,7 @@ void xPortPendSVHandler( void )
 	__asm volatile
 	(
 		"	mrs r0, psp							\n"
+		"	isb									\n"
 		"										\n"
 		"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
 		"	ldr	r2, [r3]						\n"
@@ -473,7 +514,7 @@ void xPortPendSVHandler( void )
 		"	stmdb r0!, {r1, r4-r11, r14}		\n" /* Save the remaining registers. */
 		"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
 		"										\n"
-		"	stmdb sp!, {r3}						\n"
+		"	stmdb sp!, {r0, r3}					\n"
 		"	mov r0, %0							\n"
 	  "	cpsid i								\n" /* Errata workaround. */
 		"	msr basepri, r0						\n"
@@ -483,8 +524,8 @@ void xPortPendSVHandler( void )
 		"	bl vTaskSwitchContext				\n"
 		"	mov r0, #0							\n"
 		"	msr basepri, r0						\n"
-		"	ldmia sp!, {r3}						\n"
-		"										\n"	/* Restore the context. */
+		"	ldmia sp!, {r0, r3}					\n"
+		"										\n" /* Restore the context. */
 		"	ldr r1, [r3]						\n"
 		"	ldr r0, [r1]						\n" /* The first item in the TCB is the task top of stack. */
 		"	add r1, r1, #4						\n" /* Move onto the second item in the TCB... */
@@ -686,14 +727,9 @@ uint32_t ulDummy;
  */
 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
 {
-	/* Calculate the constants required to configure the tick interrupt. */
-	#if configUSE_TICKLESS_IDLE == 1
-	{
-		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
-		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
-	}
-	#endif /* configUSE_TICKLESS_IDLE */
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
 	/* Configure SysTick to interrupt at the requested rate. */
 	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
@@ -725,6 +761,9 @@ extern uint32_t __FLASH_segment_end__[];
 extern uint32_t __privileged_data_start__[];
 extern uint32_t __privileged_data_end__[];
 
+	/* Check the expected MPU is present. */
+	if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+	{
 		/* First setup the entire flash for unprivileged read only access. */
 		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
 											( portMPU_REGION_VALID ) |
@@ -735,7 +774,7 @@ extern uint32_t __privileged_data_end__[];
 										( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
 										( portMPU_REGION_ENABLE );
 
-		/* Setup the first 16K for privileged only access (even though less
+		/* Setup the first nK for privileged only access (even though less
 		than 10K is actually being used).  This is where the kernel code is
 		placed. */
 		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
@@ -773,6 +812,7 @@ extern uint32_t __privileged_data_end__[];
 
 		/* Enable the MPU with the background region configured. */
 		portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+    }
 }
 /*-----------------------------------------------------------*/
 
@@ -800,21 +840,33 @@ uint32_t ulRegionSize, ulReturnValue = 4;
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t xPortRaisePrivilege( void )
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
 {
 	__asm volatile
 	(
-		"	mrs r0, control						\n"
-		"	tst r0, #1							\n" /* Is the task running privileged? */
-		"	itte ne								\n"
-		"	movne r0, #0						\n" /* CONTROL[0]!=0, return false. */
-		"	svcne %0							\n" /* Switch to privileged. */
-		"	moveq r0, #1						\n" /* CONTROL[0]==0, return true. */
-		"	bx lr								\n"
-		:: "i" (portSVC_RAISE_PRIVILEGE) : "r0"
+	"	mrs r0, control							\n" /* r0 = CONTROL. */
+	"	tst r0, #1								\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	"	ite ne									\n"
+	"	movne r0, #0							\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	"	moveq r0, #1							\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	"	bx lr									\n" /* Return. */
+	"											\n"
+	"	.align 4								\n"
+	::: "r0", "memory"
 	);
+}
+/*-----------------------------------------------------------*/
 
-	return 0;
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control							\n" /* r0 = CONTROL. */
+	"	orr r0, #1								\n" /* r0 = r0 | 1. */
+	"	msr control, r0							\n" /* CONTROL = r0. */
+	"	bx lr									\n" /* Return to the caller. */
+	:::"r0", "memory"
+	);
 }
 /*-----------------------------------------------------------*/
 
@@ -922,7 +974,7 @@ uint32_t ul;
 	uint8_t ucCurrentPriority;
 
 		/* Obtain the number of the currently executing interrupt. */
-		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
 
 		/* Is the interrupt number a user defined interrupt? */
 		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7_MPU/r0p1/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7_MPU/r0p1/portmacro.h
index be1d7427b..3a2d6045c 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7_MPU/r0p1/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7_MPU/r0p1/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -89,7 +89,7 @@ typedef unsigned long UBaseType_t;
 #define portNUM_CONFIGURABLE_REGIONS		( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
 #define portTOTAL_NUM_REGIONS				( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
 
-#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " :::"r0" )
+#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
 
 typedef struct MPU_REGION_REGISTERS
 {
@@ -116,7 +116,7 @@ typedef struct MPU_SETTINGS
 
 /* Scheduler utilities. */
 
-#define portYIELD()				__asm volatile ( "	SVC	%0	\n" :: "i" (portSVC_YIELD) )
+#define portYIELD()				__asm volatile ( "	SVC	%0	\n" :: "i" (portSVC_YIELD) : "memory" )
 #define portYIELD_WITHIN_API() 													\
 {																				\
 	/* Set a PendSV to request a context switch. */								\
@@ -124,7 +124,7 @@ typedef struct MPU_SETTINGS
 																				\
 	/* Barriers are normally not required but do ensure the code is completely	\
 	within the specified behaviour for the architecture. */						\
-	__asm volatile( "dsb" );													\
+	__asm volatile( "dsb" ::: "memory" );										\
 	__asm volatile( "isb" );													\
 }
 
@@ -165,7 +165,7 @@ not necessary for to use this port.  They are defined so the common demo files
 	{
 	uint8_t ucReturn;
 
-		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
 		return ucReturn;
 	}
 
@@ -199,18 +199,28 @@ not necessary for to use this port.  They are defined so the common demo files
 #ifndef portFORCE_INLINE
 	#define portFORCE_INLINE inline __attribute__(( always_inline))
 #endif
+/*-----------------------------------------------------------*/
 
-/* Set the privilege level to user mode if xRunningPrivileged is false. */
-portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged )
-{
-	if( xRunningPrivileged != pdTRUE ) 
-	{
-		__asm volatile ( " mrs r0, control 	\n" \
-						 " orr r0, #1 		\n" \
-						 " msr control, r0	\n"	\
-						 :::"r0" );
-	}
-}
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED()			xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+*/
+#define portRAISE_PRIVILEGE()		__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE()		vResetPrivilege()
 /*-----------------------------------------------------------*/
 
 portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
@@ -219,7 +229,7 @@ uint32_t ulCurrentInterrupt;
 BaseType_t xReturn;
 
 	/* Obtain the number of the currently executing interrupt. */
-	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
+	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
 
 	if( ulCurrentInterrupt == 0 )
 	{
@@ -247,7 +257,7 @@ uint32_t ulNewBASEPRI;
 		"	isb														\n" \
 		"	dsb														\n" \
 		"	cpsie i													\n" \
-		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
 	);
 }
 
@@ -266,7 +276,7 @@ uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
 		"	isb														\n" \
 		"	dsb														\n" \
 		"	cpsie i													\n" \
-		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
 	);
 
 	/* This return will not be reached but is necessary to prevent compiler
@@ -279,11 +289,12 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
 {
 	__asm volatile
 	(
-		"	msr basepri, %0	" :: "r" ( ulNewMaskValue )
+		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
 	);
 }
 /*-----------------------------------------------------------*/
 
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
 
 #ifdef __cplusplus
 }
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM0/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM0/port.c
index aaa180142..36b81aaba 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM0/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM0/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s
index ec98a866c..a2e3ce84a 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM0/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM0/portmacro.h
index 02e2cbdad..758f80f80 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM0/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM0/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/port.c
new file mode 100644
index 000000000..bd85a6ffe
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/* Secure components includes. */
+	#include "secure_context.h"
+	#include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK				( 0x00000004 )
+#define portNVIC_SYSTICK_INT				( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
+#define portNVIC_PENDSVSET					( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY			( 255UL )
+#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE				( 3UL )
+#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS					( 20UL )
+#define portCPACR_CP11_POS					( 22UL )
+
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS					( 31UL )
+#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS					( 30UL )
+#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS				( 0UL )
+#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS				( 8UL )
+#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS				( 16UL )
+#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS				( 24UL )
+#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS				( 0UL )
+#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS				( 8UL )
+#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS				( 16UL )
+#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS				( 24UL )
+#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE			( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE						( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         FD
+	 * 1111 1111  1111 1111  1111 1111  1111 1101
+	 *
+	 * Bit[6] - 1 --> The exception was taken from the Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 1 --> The exception was taken to the Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
+#else
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         BC
+	 * 1111 1111  1111 1111  1111 1111  1011 1100
+	 *
+	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS			prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS				1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT				0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Setup the Memory Protection Unit (MPU).
+	 */
+	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+	/**
+	 * @brief Setup the Floating Point Unit (FPU).
+	 */
+	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Saved as part of the task context to indicate which context the
+	 * task is using on the secure side.
+	 */
+	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Stop and reset the SysTick. */
+	*( portNVIC_SYSTICK_CTRL ) = 0UL;
+	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	 * its caller as there is nothing to return to. If a task wants to exit it
+	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
+	 * to be triggered if configASSERT() is defined, then stop here so
+	 * application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		 * started to remove a compiler warning about the function being
+		 * defined but never called.  ulDummy is used purely to quieten other
+		 * warnings about code appearing after this function is called - making
+		 * ulDummy volatile makes the compiler think the function could return
+		 * and therefore not output an 'unreachable code' warning for code that
+		 * appears after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __privileged_functions_start__;
+		extern uint32_t * __privileged_functions_end__;
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+		extern uint32_t * __unprivileged_flash_start__;
+		extern uint32_t * __unprivileged_flash_end__;
+		extern uint32_t * __privileged_sram_start__;
+		extern uint32_t * __privileged_sram_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __privileged_functions_start__[];
+		extern uint32_t __privileged_functions_end__[];
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+		extern uint32_t __unprivileged_flash_start__[];
+		extern uint32_t __unprivileged_flash_end__[];
+		extern uint32_t __privileged_sram_start__[];
+		extern uint32_t __privileged_sram_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+
+		/* Check that the MPU is present. */
+		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+		{
+			/* MAIR0 - Index 0. */
+			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+			/* MAIR0 - Index 1. */
+			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+			/* Setup privileged flash as Read Only so that privileged tasks can
+			 * read it but not modify. */
+			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged flash as Read Only by both privileged and
+			 * unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged syscalls flash as Read Only by both privileged
+			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup RAM containing kernel data for privileged access only. */
+			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+								( portMPU_REGION_EXECUTE_NEVER );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Enable mem fault. */
+			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+			/* Enable MPU with privileged background access i.e. unmapped
+			 * regions have privileged access. */
+			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			/* Enable non-secure access to the FPU. */
+			SecureInit_EnableNSFPUAccess();
+		}
+		#endif /* configENABLE_TRUSTZONE */
+
+		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+		 * unprivileged code should be able to access FPU. CP11 should be
+		 * programmed to the same value as CP10. */
+		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+							);
+
+		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
+		 * context on exception entry and restore on exception return.
+		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
+		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+	}
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	portDISABLE_INTERRUPTS();
+	ulCriticalNesting++;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	configASSERT( ulCriticalNesting );
+	ulCriticalNesting--;
+
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	uint32_t ulR0;
+	#if( configENABLE_MPU == 1 )
+		uint32_t ulControl, ulIsTaskPrivileged;
+	#endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
+	 * R12, LR, PC, xPSR. */
+	ulPC = pulCallerStackAddress[ 6 ];
+	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+	switch( ucSVCNumber )
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+			case portSVC_ALLOCATE_SECURE_CONTEXT:
+			{
+				/* R0 contains the stack size passed as parameter to the
+				 * vPortAllocateSecureContext function. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Read the CONTROL register value. */
+					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+					/* The task that raised the SVC is privileged if Bit[0]
+					 * in the CONTROL register is 0. */
+					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+				}
+				#else
+				{
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0 );
+				}
+				#endif /* configENABLE_MPU */
+
+				configASSERT( xSecureContext != NULL );
+				SecureContext_LoadContext( xSecureContext );
+			}
+			break;
+
+			case portSVC_FREE_SECURE_CONTEXT:
+			{
+				/* R0 contains the secure context handle to be freed. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				/* Free the secure context. */
+				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+			}
+			break;
+		#endif /* configENABLE_TRUSTZONE */
+
+		case portSVC_START_SCHEDULER:
+		{
+			#if( configENABLE_TRUSTZONE == 1 )
+			{
+				/* De-prioritize the non-secure exceptions so that the
+				 * non-secure pendSV runs at the lowest priority. */
+				SecureInit_DePrioritizeNSExceptions();
+
+				/* Initialize the secure context management system. */
+				SecureContext_Init();
+			}
+			#endif /* configENABLE_TRUSTZONE */
+
+			#if( configENABLE_FPU == 1 )
+			{
+				/* Setup the Floating Point Unit (FPU). */
+				prvSetupFPU();
+			}
+			#endif /* configENABLE_FPU */
+
+			/* Setup the context of the first task so that the first task starts
+			 * executing. */
+			vRestoreContextOfFirstTask();
+		}
+		break;
+
+		#if( configENABLE_MPU == 1 )
+			case portSVC_RAISE_PRIVILEGE:
+			{
+				/* Only raise the privilege, if the svc was raised from any of
+				 * the system calls. */
+				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+				{
+					vRaisePrivilege();
+				}
+			}
+			break;
+		#endif /* configENABLE_MPU */
+
+		default:
+		{
+			/* Incorrect SVC call. */
+			configASSERT( pdFALSE );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	 * interrupt. */
+	#if( portPRELOAD_REGISTERS == 0 )
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
+		*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#else /* portPRELOAD_REGISTERS */
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
+		pxTopOfStack--;
+		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#endif /* portPRELOAD_REGISTERS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+	#if( configENABLE_MPU == 1 )
+	{
+		/* Setup the Memory Protection Unit (MPU). */
+		prvSetupMPU();
+	}
+	#endif /* configENABLE_MPU */
+
+	/* Start the timer that generates the tick ISR. Interrupts are disabled
+	 * here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialize the critical nesting count ready for the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task. */
+	vStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing. Call the task
+	 * exit error function to prevent compiler warnings about a static function
+	 * not being called in the case that the application writer overrides this
+	 * functionality by defining configTASK_RETURN_ADDRESS. Call
+	 * vTaskSwitchContext() so link time optimization does not remove the
+	 * symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Not implemented in ports where there is nothing to return to.
+	 * Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+	{
+	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+	int32_t lIndex = 0;
+
+		/* Setup MAIR0. */
+		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+		/* This function is called automatically when the task is created - in
+		 * which case the stack region parameters will be valid.  At all other
+		 * times the stack parameters will not be valid and it is assumed that
+		 * the stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
+															( portMPU_REGION_NON_SHAREABLE ) |
+															( portMPU_REGION_READ_WRITE ) |
+															( portMPU_REGION_EXECUTE_NEVER );
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
+															( portMPU_RLAR_ATTR_INDEX0 ) |
+															( portMPU_RLAR_REGION_ENABLE );
+		}
+
+		/* User supplied configurable regions. */
+		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+		{
+			/* If xRegions is NULL i.e. the task has not specified any MPU
+			 * region, the else part ensures that all the configurable MPU
+			 * regions are invalidated. */
+			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+			{
+				/* Translate the generic region definition contained in xRegions
+				 * into the ARMv8 specific MPU settings that are then stored in
+				 * xMPUSettings. */
+				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+				/* Start address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
+																			( portMPU_REGION_NON_SHAREABLE );
+
+				/* RO/RW. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+				}
+				else
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+				}
+
+				/* XN. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+				}
+
+				/* End Address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
+																			( portMPU_RLAR_REGION_ENABLE );
+
+				/* Normal memory/ Device memory. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+				{
+					/* Attr1 in MAIR0 is configured as device memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+				}
+				else
+				{
+					/* Attr1 in MAIR0 is configured as normal memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+				}
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.h
new file mode 100644
index 000000000..2ecf04ea6
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.s b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.s
new file mode 100644
index 000000000..b1a543a93
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.s
@@ -0,0 +1,377 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN xSecureContext
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+	EXTERN SecureContext_SaveContext
+	EXTERN SecureContext_LoadContext
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vPortAllocateSecureContext
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMaskFromISR
+	PUBLIC vClearInterruptMaskFromISR
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+	PUBLIC vPortFreeSecureContext
+
+#if ( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	tst r0, r1								/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+	beq running_privileged					/* If the result of previous AND operation was 0, branch. */
+	movs r0, #0								/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+	running_privileged:
+		movs r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+		bx lr								/* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	orrs r0, r1								/* r0 = r0 | r1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vPortAllocateSecureContext:
+	svc 0									/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r3, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r3]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	movs r5, #1								/* r5 = 1. */
+	bics r4, r5								/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	ldr  r4, [r3]							/* r4 = *r3 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	movs r5, #4								/* r5 = 4. */
+	str  r5, [r2]							/* Program RNR = 4. */
+	ldmia r3!, {r6,r7}						/* Read first set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write first set of RBAR/RLAR registers. */
+	movs r5, #5								/* r5 = 5. */
+	str  r5, [r2]							/* Program RNR = 5. */
+	ldmia r3!, {r6,r7}						/* Read second set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write second set of RBAR/RLAR registers. */
+	movs r5, #6								/* r5 = 6. */
+	str  r5, [r2]							/* Program RNR = 6. */
+	ldmia r3!, {r6,r7}						/* Read third set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write third set of RBAR/RLAR registers. */
+	movs r5, #7								/* r5 = 7. */
+	str  r5, [r2]							/* Program RNR = 7. */
+	ldmia r3!, {r6,r7}						/* Read fourth set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write fourth set of RBAR/RLAR registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	movs r5, #1								/* r5 = 1. */
+	orrs r4, r5								/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r4}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+	ldr  r5, =xSecureContext
+	str  r1, [r5]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	msr  control, r3						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r4									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+	ldr  r4, =xSecureContext
+	str  r1, [r4]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs r0, control							/* Read the CONTROL register. */
+	movs r1, #1								/* r1 = 1. */
+	bics r0, r1								/* Clear the bit 0. */
+	msr control, r0							/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR:
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR:
+	msr PRIMASK, r0
+	bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r1, psp								/* Read PSP in r1. */
+	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+
+	cbz r0, save_ns_context					/* No secure context to save. */
+	push {r0-r2, r14}
+	bl SecureContext_SaveContext
+	pop {r0-r3}								/* LR is now in r3. */
+	mov lr, r3								/* LR = r3. */
+	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r2, [r3]							/* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mrs r3, control							/* r3 = CONTROL. */
+	mov r4, lr								/* r4 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+#else /* configENABLE_MPU */
+	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
+#endif /* configENABLE_MPU */
+	b select_next_task
+
+	save_ns_context:
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r2, [r3]						/* Read pxCurrentTCB. */
+	#if ( configENABLE_MPU == 1 )
+		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		adds r1, r1, #16					/* r1 = r1 + 16. */
+		stmia r1!, {r4-r7}					/* Store the low registers that are not saved automatically. */
+		mov r4, r8							/* r4 = r8. */
+		mov r5, r9							/* r5 = r9. */
+		mov r6, r10							/* r6 = r10. */
+		mov r7, r11							/* r7 = r11. */
+		stmia r1!, {r4-r7}					/* Store the high registers that are not saved automatically. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mrs r3, control						/* r3 = CONTROL. */
+		mov r4, lr							/* r4 = LR/EXC_RETURN. */
+		subs r1, r1, #48					/* r1 = r1 - 48. */
+		stmia r1!, {r0, r2-r4}				/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mov r3, lr							/* r3 = LR/EXC_RETURN. */
+		stmia r1!, {r0, r2-r7}				/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+		mov r4, r8							/* r4 = r8. */
+		mov r5, r9							/* r5 = r9. */
+		mov r6, r10							/* r6 = r10. */
+		mov r7, r11							/* r7 = r11. */
+		stmia r1!, {r4-r7}					/* Store the high registers that are not saved automatically. */
+	#endif /* configENABLE_MPU */
+
+	select_next_task:
+		cpsid i
+		bl vTaskSwitchContext
+		cpsie i
+
+		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r3, [r2]						/* Read pxCurrentTCB. */
+		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+
+	#if ( configENABLE_MPU == 1 )
+		dmb									/* Complete outstanding transfers before disabling MPU. */
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		movs r5, #1							/* r5 = 1. */
+		bics r4, r5							/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+		str r4, [r2]						/* Disable MPU. */
+
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
+		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+		str r4, [r2]						/* Program MAIR0. */
+		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+		movs r5, #4							/* r5 = 4. */
+		str  r5, [r2]						/* Program RNR = 4. */
+		ldmia r3!, {r6,r7}					/* Read first set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write first set of RBAR/RLAR registers. */
+		movs r5, #5							/* r5 = 5. */
+		str  r5, [r2]						/* Program RNR = 5. */
+		ldmia r3!, {r6,r7}					/* Read second set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write second set of RBAR/RLAR registers. */
+		movs r5, #6							/* r5 = 6. */
+		str  r5, [r2]						/* Program RNR = 6. */
+		ldmia r3!, {r6,r7}					/* Read third set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write third set of RBAR/RLAR registers. */
+		movs r5, #7							/* r5 = 7. */
+		str  r5, [r2]						/* Program RNR = 7. */
+		ldmia r3!, {r6,r7}					/* Read fourth set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write fourth set of RBAR/RLAR registers. */
+
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		movs r5, #1							/* r5 = 1. */
+		orrs r4, r5							/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+		str r4, [r2]						/* Enable MPU. */
+		dsb									/* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+
+	#if ( configENABLE_MPU == 1 )
+		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		msr control, r3						/* Restore the CONTROL register value for the task. */
+		mov lr, r4							/* LR = r4. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r4}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r4}
+		mov lr, r4							/* LR = r4. */
+		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#else /* configENABLE_MPU */
+		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		mov lr, r3							/* LR = r3. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r3}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r3}
+		mov lr, r3							/* LR = r3. */
+		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#endif /* configENABLE_MPU */
+
+	restore_ns_context:
+		adds r1, r1, #16					/* Move to the high registers. */
+		ldmia r1!, {r4-r7}					/* Restore the high registers that are not automatically restored. */
+		mov r8, r4							/* r8 = r4. */
+		mov r9, r5							/* r9 = r5. */
+		mov r10, r6							/* r10 = r6. */
+		mov r11, r7							/* r11 = r7. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		subs r1, r1, #32					/* Go back to the low registers. */
+		ldmia r1!, {r4-r7}					/* Restore the low registers that are not automatically restored. */
+		bx lr
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	movs r0, #4
+	mov r1, lr
+	tst r0, r1
+	beq stacking_used_msp
+	mrs r0, psp
+	b vPortSVCHandler_C
+	stacking_used_msp:
+		mrs r0, msp
+		b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+vPortFreeSecureContext:
+	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
+	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
+	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
+	beq free_secure_context
+	bx lr									/* There is no secure context (xSecureContext is NULL). */
+	free_secure_context:
+		svc 1								/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+		bx lr								/* Return. */
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h
new file mode 100644
index 000000000..8ea53403d
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h
@@ -0,0 +1,306 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M23"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+#pragma diag_suppress=Be006
+#pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.c
new file mode 100644
index 000000000..53535cd9e
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.c
@@ -0,0 +1,204 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
+	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
+	uint8_t *pucStackStart;				/**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+	uint32_t ulIPSR;
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* No stack for thread mode until a task's context is loaded. */
+		secureportSET_PSPLIM( securecontextNO_STACK );
+		secureportSET_PSP( securecontextNO_STACK );
+
+		#if( configENABLE_MPU == 1 )
+		{
+			/* Configure thread mode to use PSP and to be unprivileged. */
+			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+		}
+		#else /* configENABLE_MPU */
+		{
+			/* Configure thread mode to use PSP and to be privileged.. */
+			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+		}
+		#endif /* configENABLE_MPU */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+	uint8_t *pucStackMemory = NULL;
+	uint32_t ulIPSR;
+	SecureContextHandle_t xSecureContextHandle = NULL;
+	#if( configENABLE_MPU == 1 )
+		uint32_t *pulCurrentStackPointer = NULL;
+	#endif /* configENABLE_MPU */
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* Allocate the context structure. */
+		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+		if( xSecureContextHandle != NULL )
+		{
+			/* Allocate the stack space. */
+			pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+			if( pucStackMemory != NULL )
+			{
+				/* Since stack grows down, the starting point will be the last
+				 * location. Note that this location is next to the last
+				 * allocated byte because the hardware decrements the stack
+				 * pointer before writing i.e. if stack pointer is 0x2, a push
+				 * operation will decrement the stack pointer to 0x1 and then
+				 * write at 0x1. */
+				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+				/* The stack cannot go beyond this location. This value is
+				 * programmed in the PSPLIM register on context switch.*/
+				xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Store the correct CONTROL value for the task on the stack.
+					 * This value is programmed in the CONTROL register on
+					 * context switch. */
+					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+					pulCurrentStackPointer--;
+					if( ulIsTaskPrivileged )
+					{
+						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+					}
+					else
+					{
+						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+					}
+
+					/* Store the current stack pointer. This value is programmed in
+					 * the PSP register on context switch. */
+					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+				}
+				#else /* configENABLE_MPU */
+				{
+					/* Current SP is set to the starting of the stack. This
+					 * value programmed in the PSP register on context switch. */
+					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+
+				}
+				#endif /* configENABLE_MPU */
+			}
+			else
+			{
+				/* Free the context to avoid memory leak and make sure to return
+				 * NULL to indicate failure. */
+				vPortFree( xSecureContextHandle );
+				xSecureContextHandle = NULL;
+			}
+		}
+	}
+
+	return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+	uint32_t ulIPSR;
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* Ensure that valid parameters are passed. */
+		secureportASSERT( xSecureContextHandle != NULL );
+
+		/* Free the stack space. */
+		vPortFree( xSecureContextHandle->pucStackLimit );
+
+		/* Free the context itself. */
+		vPortFree( xSecureContextHandle );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.h
new file mode 100644
index 000000000..e148bff8e
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.h
@@ -0,0 +1,111 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include 
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK	0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext*	SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if( configENABLE_MPU == 1 )
+	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c
new file mode 100644
index 000000000..619db1ee3
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c
@@ -0,0 +1,48 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/* Functions implemented in assembler file. */
+extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
+extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+	SecureContext_LoadContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+	SecureContext_SaveContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
new file mode 100644
index 000000000..65cee0c6f
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
@@ -0,0 +1,76 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+
+	PUBLIC SecureContext_LoadContextAsm
+	PUBLIC SecureContext_SaveContextAsm
+
+#if ( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+/*-----------------------------------------------------------*/
+
+SecureContext_LoadContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, load_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+#if ( configENABLE_MPU == 1 )
+	ldmia r1!, {r3}							/* Read CONTROL register value from task's stack. r3 = CONTROL. */
+	msr control, r3							/* CONTROL = r3. */
+#endif /* configENABLE_MPU */
+	msr psplim, r2							/* PSPLIM = r2. */
+	msr psp, r1								/* PSP = r1. */
+
+	load_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+SecureContext_SaveContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, save_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	mrs r1, psp								/* r1 = PSP. */
+#if ( configENABLE_MPU == 1 )
+	mrs r2, control							/* r2 = CONTROL. */
+	subs r1, r1, #4							/* Make space for the CONTROL value on the stack. */
+	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	stmia r1!, {r2}							/* Store CONTROL value on the stack. */
+#else /* configENABLE_MPU */
+	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+#endif /* configENABLE_MPU */
+	movs r1, #0								/* r1 = securecontextNO_STACK. */
+	msr psplim, r1							/* PSPLIM = securecontextNO_STACK. */
+	msr psp, r1								/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+
+	save_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.c
new file mode 100644
index 000000000..60fce5c66
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.c
@@ -0,0 +1,450 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+	#define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+	#define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+	#define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	 * heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
+	size_t xBlockSize;						/**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	 * blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	 * at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	 * entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	 * than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	 * make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	 * make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	 * before and the block after, then it's pxNextFreeBlock pointer will have
+	 * already been set, and should not be set here as that would make it point
+	 * to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	/* If this is the first call to malloc then the heap will require
+	 * initialisation to setup the list of free blocks. */
+	if( pxEnd == NULL )
+	{
+		prvHeapInit();
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Check the requested block size is not so large that the top bit is set.
+	 * The top bit of the block size member of the BlockLink_t structure is used
+	 * to determine who owns the block - the application or the kernel, so it
+	 * must be free. */
+	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+	{
+		/* The wanted size is increased so it can contain a BlockLink_t
+		 * structure in addition to the requested amount of bytes. */
+		if( xWantedSize > 0 )
+		{
+			xWantedSize += xHeapStructSize;
+
+			/* Ensure that blocks are always aligned to the required number of
+			 * bytes. */
+			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+			{
+				/* Byte alignment required. */
+				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+		{
+			/* Traverse the list from the start (lowest address) block until
+			 * one of adequate size is found. */
+			pxPreviousBlock = &xStart;
+			pxBlock = xStart.pxNextFreeBlock;
+			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+			{
+				pxPreviousBlock = pxBlock;
+				pxBlock = pxBlock->pxNextFreeBlock;
+			}
+
+			/* If the end marker was reached then a block of adequate size was
+			 * not found. */
+			if( pxBlock != pxEnd )
+			{
+				/* Return the memory space pointed to - jumping over the
+				 * BlockLink_t structure at its start. */
+				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+				/* This block is being returned for use so must be taken out
+				 * of the list of free blocks. */
+				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+				/* If the block is larger than required it can be split into
+				 * two. */
+				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+				{
+					/* This block is to be split into two.  Create a new
+					 * block following the number of bytes requested. The void
+					 * cast is used to prevent byte alignment warnings from the
+					 * compiler. */
+					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+					/* Calculate the sizes of two blocks split from the single
+					 * block. */
+					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+					pxBlock->xBlockSize = xWantedSize;
+
+					/* Insert the new block into the list of free blocks. */
+					prvInsertBlockIntoFreeList( pxNewBlockLink );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+				{
+					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* The block is being returned - it is allocated and owned by
+				 * the application and has no "next" block. */
+				pxBlock->xBlockSize |= xBlockAllocatedBit;
+				pxBlock->pxNextFreeBlock = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceMALLOC( pvReturn, xWantedSize );
+
+	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		 * before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				 * allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				secureportDISABLE_NON_SECURE_INTERRUPTS();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+				}
+				secureportENABLE_NON_SECURE_INTERRUPTS();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.h
new file mode 100644
index 000000000..69e4f2a86
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include 
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void *pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void *pv );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.c
new file mode 100644
index 000000000..c6525f755
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS			( 29UL )
+#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS				( 26UL )
+#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS			( 10UL )
+#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS			( 11UL )
+#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+	uint32_t ulIPSR;
+
+	 /* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
+	}
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+	uint32_t ulIPSR;
+
+	 /* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+		 * permitted. CP11 should be programmed to the same value as CP10. */
+		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+		 * that we can enable/disable lazy stacking in port.c file. */
+		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
+
+		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+		 * registers (S16-S31) are also pushed to stack on exception entry and
+		 * restored on exception return. */
+		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.h
new file mode 100644
index 000000000..6c5bc71f5
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h
new file mode 100644
index 000000000..760edab56
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT					8
+#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
+#else
+	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x )						\
+	if( ( x ) == 0 )								\
+	{												\
+		secureportDISABLE_SECURE_INTERRUPTS();		\
+		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
+		for( ;; );									\
+	}
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
new file mode 100644
index 000000000..bd85a6ffe
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/* Secure components includes. */
+	#include "secure_context.h"
+	#include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK				( 0x00000004 )
+#define portNVIC_SYSTICK_INT				( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
+#define portNVIC_PENDSVSET					( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY			( 255UL )
+#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE				( 3UL )
+#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS					( 20UL )
+#define portCPACR_CP11_POS					( 22UL )
+
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS					( 31UL )
+#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS					( 30UL )
+#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS				( 0UL )
+#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS				( 8UL )
+#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS				( 16UL )
+#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS				( 24UL )
+#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS				( 0UL )
+#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS				( 8UL )
+#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS				( 16UL )
+#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS				( 24UL )
+#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE			( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE						( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         FD
+	 * 1111 1111  1111 1111  1111 1111  1111 1101
+	 *
+	 * Bit[6] - 1 --> The exception was taken from the Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 1 --> The exception was taken to the Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
+#else
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         BC
+	 * 1111 1111  1111 1111  1111 1111  1011 1100
+	 *
+	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS			prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS				1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT				0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Setup the Memory Protection Unit (MPU).
+	 */
+	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+	/**
+	 * @brief Setup the Floating Point Unit (FPU).
+	 */
+	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Saved as part of the task context to indicate which context the
+	 * task is using on the secure side.
+	 */
+	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Stop and reset the SysTick. */
+	*( portNVIC_SYSTICK_CTRL ) = 0UL;
+	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	 * its caller as there is nothing to return to. If a task wants to exit it
+	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
+	 * to be triggered if configASSERT() is defined, then stop here so
+	 * application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		 * started to remove a compiler warning about the function being
+		 * defined but never called.  ulDummy is used purely to quieten other
+		 * warnings about code appearing after this function is called - making
+		 * ulDummy volatile makes the compiler think the function could return
+		 * and therefore not output an 'unreachable code' warning for code that
+		 * appears after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __privileged_functions_start__;
+		extern uint32_t * __privileged_functions_end__;
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+		extern uint32_t * __unprivileged_flash_start__;
+		extern uint32_t * __unprivileged_flash_end__;
+		extern uint32_t * __privileged_sram_start__;
+		extern uint32_t * __privileged_sram_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __privileged_functions_start__[];
+		extern uint32_t __privileged_functions_end__[];
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+		extern uint32_t __unprivileged_flash_start__[];
+		extern uint32_t __unprivileged_flash_end__[];
+		extern uint32_t __privileged_sram_start__[];
+		extern uint32_t __privileged_sram_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+
+		/* Check that the MPU is present. */
+		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+		{
+			/* MAIR0 - Index 0. */
+			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+			/* MAIR0 - Index 1. */
+			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+			/* Setup privileged flash as Read Only so that privileged tasks can
+			 * read it but not modify. */
+			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged flash as Read Only by both privileged and
+			 * unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged syscalls flash as Read Only by both privileged
+			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup RAM containing kernel data for privileged access only. */
+			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+								( portMPU_REGION_EXECUTE_NEVER );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Enable mem fault. */
+			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+			/* Enable MPU with privileged background access i.e. unmapped
+			 * regions have privileged access. */
+			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			/* Enable non-secure access to the FPU. */
+			SecureInit_EnableNSFPUAccess();
+		}
+		#endif /* configENABLE_TRUSTZONE */
+
+		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+		 * unprivileged code should be able to access FPU. CP11 should be
+		 * programmed to the same value as CP10. */
+		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+							);
+
+		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
+		 * context on exception entry and restore on exception return.
+		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
+		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+	}
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	portDISABLE_INTERRUPTS();
+	ulCriticalNesting++;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	configASSERT( ulCriticalNesting );
+	ulCriticalNesting--;
+
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	uint32_t ulR0;
+	#if( configENABLE_MPU == 1 )
+		uint32_t ulControl, ulIsTaskPrivileged;
+	#endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
+	 * R12, LR, PC, xPSR. */
+	ulPC = pulCallerStackAddress[ 6 ];
+	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+	switch( ucSVCNumber )
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+			case portSVC_ALLOCATE_SECURE_CONTEXT:
+			{
+				/* R0 contains the stack size passed as parameter to the
+				 * vPortAllocateSecureContext function. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Read the CONTROL register value. */
+					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+					/* The task that raised the SVC is privileged if Bit[0]
+					 * in the CONTROL register is 0. */
+					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+				}
+				#else
+				{
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0 );
+				}
+				#endif /* configENABLE_MPU */
+
+				configASSERT( xSecureContext != NULL );
+				SecureContext_LoadContext( xSecureContext );
+			}
+			break;
+
+			case portSVC_FREE_SECURE_CONTEXT:
+			{
+				/* R0 contains the secure context handle to be freed. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				/* Free the secure context. */
+				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+			}
+			break;
+		#endif /* configENABLE_TRUSTZONE */
+
+		case portSVC_START_SCHEDULER:
+		{
+			#if( configENABLE_TRUSTZONE == 1 )
+			{
+				/* De-prioritize the non-secure exceptions so that the
+				 * non-secure pendSV runs at the lowest priority. */
+				SecureInit_DePrioritizeNSExceptions();
+
+				/* Initialize the secure context management system. */
+				SecureContext_Init();
+			}
+			#endif /* configENABLE_TRUSTZONE */
+
+			#if( configENABLE_FPU == 1 )
+			{
+				/* Setup the Floating Point Unit (FPU). */
+				prvSetupFPU();
+			}
+			#endif /* configENABLE_FPU */
+
+			/* Setup the context of the first task so that the first task starts
+			 * executing. */
+			vRestoreContextOfFirstTask();
+		}
+		break;
+
+		#if( configENABLE_MPU == 1 )
+			case portSVC_RAISE_PRIVILEGE:
+			{
+				/* Only raise the privilege, if the svc was raised from any of
+				 * the system calls. */
+				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+				{
+					vRaisePrivilege();
+				}
+			}
+			break;
+		#endif /* configENABLE_MPU */
+
+		default:
+		{
+			/* Incorrect SVC call. */
+			configASSERT( pdFALSE );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	 * interrupt. */
+	#if( portPRELOAD_REGISTERS == 0 )
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
+		*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#else /* portPRELOAD_REGISTERS */
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
+		pxTopOfStack--;
+		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#endif /* portPRELOAD_REGISTERS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+	#if( configENABLE_MPU == 1 )
+	{
+		/* Setup the Memory Protection Unit (MPU). */
+		prvSetupMPU();
+	}
+	#endif /* configENABLE_MPU */
+
+	/* Start the timer that generates the tick ISR. Interrupts are disabled
+	 * here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialize the critical nesting count ready for the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task. */
+	vStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing. Call the task
+	 * exit error function to prevent compiler warnings about a static function
+	 * not being called in the case that the application writer overrides this
+	 * functionality by defining configTASK_RETURN_ADDRESS. Call
+	 * vTaskSwitchContext() so link time optimization does not remove the
+	 * symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Not implemented in ports where there is nothing to return to.
+	 * Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+	{
+	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+	int32_t lIndex = 0;
+
+		/* Setup MAIR0. */
+		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+		/* This function is called automatically when the task is created - in
+		 * which case the stack region parameters will be valid.  At all other
+		 * times the stack parameters will not be valid and it is assumed that
+		 * the stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
+															( portMPU_REGION_NON_SHAREABLE ) |
+															( portMPU_REGION_READ_WRITE ) |
+															( portMPU_REGION_EXECUTE_NEVER );
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
+															( portMPU_RLAR_ATTR_INDEX0 ) |
+															( portMPU_RLAR_REGION_ENABLE );
+		}
+
+		/* User supplied configurable regions. */
+		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+		{
+			/* If xRegions is NULL i.e. the task has not specified any MPU
+			 * region, the else part ensures that all the configurable MPU
+			 * regions are invalidated. */
+			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+			{
+				/* Translate the generic region definition contained in xRegions
+				 * into the ARMv8 specific MPU settings that are then stored in
+				 * xMPUSettings. */
+				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+				/* Start address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
+																			( portMPU_REGION_NON_SHAREABLE );
+
+				/* RO/RW. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+				}
+				else
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+				}
+
+				/* XN. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+				}
+
+				/* End Address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
+																			( portMPU_RLAR_REGION_ENABLE );
+
+				/* Normal memory/ Device memory. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+				{
+					/* Attr1 in MAIR0 is configured as device memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+				}
+				else
+				{
+					/* Attr1 in MAIR0 is configured as normal memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+				}
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
new file mode 100644
index 000000000..2ecf04ea6
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
new file mode 100644
index 000000000..3121df6b7
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
@@ -0,0 +1,303 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMaskFromISR
+	PUBLIC vClearInterruptMaskFromISR
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+
+#if ( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	tst r0, r1								/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+	beq running_privileged					/* If the result of previous AND operation was 0, branch. */
+	movs r0, #0								/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+	running_privileged:
+		movs r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+		bx lr								/* Return. */
+
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	orrs r0, r1								/* r0 = r0 | r1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r1, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r1]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	bics r3, r4								/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+	str r3, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr  r4, [r1]							/* r4 = *r1 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	movs r4, #4								/* r4 = 4. */
+	str  r4, [r2]							/* Program RNR = 4. */
+	ldmia r1!, {r5,r6}						/* Read first set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write first set of RBAR/RLAR registers. */
+	movs r4, #5								/* r4 = 5. */
+	str  r4, [r2]							/* Program RNR = 5. */
+	ldmia r1!, {r5,r6}						/* Read second set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write second set of RBAR/RLAR registers. */
+	movs r4, #6								/* r4 = 6. */
+	str  r4, [r2]							/* Program RNR = 6. */
+	ldmia r1!, {r5,r6}						/* Read third set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write third set of RBAR/RLAR registers. */
+	movs r4, #7								/* r4 = 7. */
+	str  r4, [r2]							/* Program RNR = 7. */
+	ldmia r1!, {r5,r6}						/* Read fourth set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write fourth set of RBAR/RLAR registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	orrs r3, r4								/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+	str r3, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	msr  control, r2						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r2}						/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r2									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs  r0, control						/* Read the CONTROL register. */
+	movs r1, #1								/* r1 = 1. */
+	bics r0, r1								/* Clear the bit 0. */
+	msr  control, r0						/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+	nop
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR:
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR:
+	msr PRIMASK, r0
+	bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r0, psp								/* Read PSP in r0. */
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+	subs r0, r0, #44						/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+	str r0, [r1]							/* Save the new top of stack in TCB. */
+	mrs r1, psplim							/* r1 = PSPLIM. */
+	mrs r2, control							/* r2 = CONTROL. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r0!, {r1-r7}						/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
+	mov r4, r8								/* r4 = r8. */
+	mov r5, r9								/* r5 = r9. */
+	mov r6, r10								/* r6 = r10. */
+	mov r7, r11								/* r7 = r11. */
+	stmia r0!, {r4-r7}						/* Store the high registers that are not saved automatically. */
+#else /* configENABLE_MPU */
+	subs r0, r0, #40						/* Make space for PSPLIM, LR and the remaining registers on the stack. */
+	str r0, [r1]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r0!, {r2-r7}						/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
+	mov r4, r8								/* r4 = r8. */
+	mov r5, r9								/* r5 = r9. */
+	mov r6, r10								/* r6 = r10. */
+	mov r7, r11								/* r7 = r11. */
+	stmia r0!, {r4-r7}						/* Store the high registers that are not saved automatically. */
+#endif /* configENABLE_MPU */
+
+	cpsid i
+	bl vTaskSwitchContext
+	cpsie i
+
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+	ldr r0, [r1]							/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	bics r3, r4								/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+	str r3, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr  r4, [r1]							/* r4 = *r1 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	movs r4, #4								/* r4 = 4. */
+	str  r4, [r2]							/* Program RNR = 4. */
+	ldmia r1!, {r5,r6}						/* Read first set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write first set of RBAR/RLAR registers. */
+	movs r4, #5								/* r4 = 5. */
+	str  r4, [r2]							/* Program RNR = 5. */
+	ldmia r1!, {r5,r6}						/* Read second set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write second set of RBAR/RLAR registers. */
+	movs r4, #6								/* r4 = 6. */
+	str  r4, [r2]							/* Program RNR = 6. */
+	ldmia r1!, {r5,r6}						/* Read third set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write third set of RBAR/RLAR registers. */
+	movs r4, #7								/* r4 = 7. */
+	str  r4, [r2]							/* Program RNR = 7. */
+	ldmia r1!, {r5,r6}						/* Read fourth set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write fourth set of RBAR/RLAR registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	orrs r3, r4								/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+	str r3, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	adds r0, r0, #28						/* Move to the high registers. */
+	ldmia r0!, {r4-r7}						/* Restore the high registers that are not automatically restored. */
+	mov r8, r4								/* r8 = r4. */
+	mov r9, r5								/* r9 = r5. */
+	mov r10, r6								/* r10 = r6. */
+	mov r11, r7								/* r11 = r7. */
+	msr psp, r0								/* Remember the new top of stack for the task. */
+	subs r0, r0, #44						/* Move to the starting of the saved context. */
+	ldmia r0!, {r1-r7}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
+	msr psplim, r1							/* Restore the PSPLIM register value for the task. */
+	msr control, r2							/* Restore the CONTROL register value for the task. */
+	bx r3
+#else /* configENABLE_MPU */
+	adds r0, r0, #24						/* Move to the high registers. */
+	ldmia r0!, {r4-r7}						/* Restore the high registers that are not automatically restored. */
+	mov r8, r4								/* r8 = r4. */
+	mov r9, r5								/* r9 = r5. */
+	mov r10, r6								/* r10 = r6. */
+	mov r11, r7								/* r11 = r7. */
+	msr psp, r0								/* Remember the new top of stack for the task. */
+	subs r0, r0, #40						/* Move to the starting of the saved context. */
+	ldmia r0!, {r2-r7}						/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+	msr psplim, r2							/* Restore the PSPLIM register value for the task. */
+	bx r3
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	movs r0, #4
+	mov r1, lr
+	tst r0, r1
+	beq stacking_used_msp
+	mrs r0, psp
+	b vPortSVCHandler_C
+	stacking_used_msp:
+		mrs r0, msp
+		b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
new file mode 100644
index 000000000..8ea53403d
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -0,0 +1,306 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M23"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+#pragma diag_suppress=Be006
+#pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM3/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM3/port.c
index 7bf366e52..f13aa84d6 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM3/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM3/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s
index cf2e13e13..fbc278a65 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h
index 7fc59c2c7..1d69069c6 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -78,6 +78,12 @@ typedef unsigned long UBaseType_t;
 #define portBYTE_ALIGNMENT			8
 /*-----------------------------------------------------------*/
 
+/* Compiler directives. */
+#define portWEAK_SYMBOL				__attribute__( ( weak ) )
+
+/*-----------------------------------------------------------*/
+
+
 /* Scheduler utilities. */
 #define portYIELD()											\
 {															\
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/port.c
new file mode 100644
index 000000000..bd85a6ffe
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/* Secure components includes. */
+	#include "secure_context.h"
+	#include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK				( 0x00000004 )
+#define portNVIC_SYSTICK_INT				( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
+#define portNVIC_PENDSVSET					( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY			( 255UL )
+#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE				( 3UL )
+#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS					( 20UL )
+#define portCPACR_CP11_POS					( 22UL )
+
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS					( 31UL )
+#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS					( 30UL )
+#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS				( 0UL )
+#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS				( 8UL )
+#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS				( 16UL )
+#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS				( 24UL )
+#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS				( 0UL )
+#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS				( 8UL )
+#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS				( 16UL )
+#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS				( 24UL )
+#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE			( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE						( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         FD
+	 * 1111 1111  1111 1111  1111 1111  1111 1101
+	 *
+	 * Bit[6] - 1 --> The exception was taken from the Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 1 --> The exception was taken to the Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
+#else
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         BC
+	 * 1111 1111  1111 1111  1111 1111  1011 1100
+	 *
+	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS			prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS				1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT				0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Setup the Memory Protection Unit (MPU).
+	 */
+	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+	/**
+	 * @brief Setup the Floating Point Unit (FPU).
+	 */
+	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Saved as part of the task context to indicate which context the
+	 * task is using on the secure side.
+	 */
+	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Stop and reset the SysTick. */
+	*( portNVIC_SYSTICK_CTRL ) = 0UL;
+	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	 * its caller as there is nothing to return to. If a task wants to exit it
+	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
+	 * to be triggered if configASSERT() is defined, then stop here so
+	 * application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		 * started to remove a compiler warning about the function being
+		 * defined but never called.  ulDummy is used purely to quieten other
+		 * warnings about code appearing after this function is called - making
+		 * ulDummy volatile makes the compiler think the function could return
+		 * and therefore not output an 'unreachable code' warning for code that
+		 * appears after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __privileged_functions_start__;
+		extern uint32_t * __privileged_functions_end__;
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+		extern uint32_t * __unprivileged_flash_start__;
+		extern uint32_t * __unprivileged_flash_end__;
+		extern uint32_t * __privileged_sram_start__;
+		extern uint32_t * __privileged_sram_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __privileged_functions_start__[];
+		extern uint32_t __privileged_functions_end__[];
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+		extern uint32_t __unprivileged_flash_start__[];
+		extern uint32_t __unprivileged_flash_end__[];
+		extern uint32_t __privileged_sram_start__[];
+		extern uint32_t __privileged_sram_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+
+		/* Check that the MPU is present. */
+		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+		{
+			/* MAIR0 - Index 0. */
+			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+			/* MAIR0 - Index 1. */
+			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+			/* Setup privileged flash as Read Only so that privileged tasks can
+			 * read it but not modify. */
+			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged flash as Read Only by both privileged and
+			 * unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged syscalls flash as Read Only by both privileged
+			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup RAM containing kernel data for privileged access only. */
+			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+								( portMPU_REGION_EXECUTE_NEVER );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Enable mem fault. */
+			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+			/* Enable MPU with privileged background access i.e. unmapped
+			 * regions have privileged access. */
+			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			/* Enable non-secure access to the FPU. */
+			SecureInit_EnableNSFPUAccess();
+		}
+		#endif /* configENABLE_TRUSTZONE */
+
+		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+		 * unprivileged code should be able to access FPU. CP11 should be
+		 * programmed to the same value as CP10. */
+		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+							);
+
+		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
+		 * context on exception entry and restore on exception return.
+		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
+		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+	}
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	portDISABLE_INTERRUPTS();
+	ulCriticalNesting++;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	configASSERT( ulCriticalNesting );
+	ulCriticalNesting--;
+
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	uint32_t ulR0;
+	#if( configENABLE_MPU == 1 )
+		uint32_t ulControl, ulIsTaskPrivileged;
+	#endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
+	 * R12, LR, PC, xPSR. */
+	ulPC = pulCallerStackAddress[ 6 ];
+	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+	switch( ucSVCNumber )
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+			case portSVC_ALLOCATE_SECURE_CONTEXT:
+			{
+				/* R0 contains the stack size passed as parameter to the
+				 * vPortAllocateSecureContext function. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Read the CONTROL register value. */
+					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+					/* The task that raised the SVC is privileged if Bit[0]
+					 * in the CONTROL register is 0. */
+					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+				}
+				#else
+				{
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0 );
+				}
+				#endif /* configENABLE_MPU */
+
+				configASSERT( xSecureContext != NULL );
+				SecureContext_LoadContext( xSecureContext );
+			}
+			break;
+
+			case portSVC_FREE_SECURE_CONTEXT:
+			{
+				/* R0 contains the secure context handle to be freed. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				/* Free the secure context. */
+				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+			}
+			break;
+		#endif /* configENABLE_TRUSTZONE */
+
+		case portSVC_START_SCHEDULER:
+		{
+			#if( configENABLE_TRUSTZONE == 1 )
+			{
+				/* De-prioritize the non-secure exceptions so that the
+				 * non-secure pendSV runs at the lowest priority. */
+				SecureInit_DePrioritizeNSExceptions();
+
+				/* Initialize the secure context management system. */
+				SecureContext_Init();
+			}
+			#endif /* configENABLE_TRUSTZONE */
+
+			#if( configENABLE_FPU == 1 )
+			{
+				/* Setup the Floating Point Unit (FPU). */
+				prvSetupFPU();
+			}
+			#endif /* configENABLE_FPU */
+
+			/* Setup the context of the first task so that the first task starts
+			 * executing. */
+			vRestoreContextOfFirstTask();
+		}
+		break;
+
+		#if( configENABLE_MPU == 1 )
+			case portSVC_RAISE_PRIVILEGE:
+			{
+				/* Only raise the privilege, if the svc was raised from any of
+				 * the system calls. */
+				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+				{
+					vRaisePrivilege();
+				}
+			}
+			break;
+		#endif /* configENABLE_MPU */
+
+		default:
+		{
+			/* Incorrect SVC call. */
+			configASSERT( pdFALSE );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	 * interrupt. */
+	#if( portPRELOAD_REGISTERS == 0 )
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
+		*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#else /* portPRELOAD_REGISTERS */
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
+		pxTopOfStack--;
+		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#endif /* portPRELOAD_REGISTERS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+	#if( configENABLE_MPU == 1 )
+	{
+		/* Setup the Memory Protection Unit (MPU). */
+		prvSetupMPU();
+	}
+	#endif /* configENABLE_MPU */
+
+	/* Start the timer that generates the tick ISR. Interrupts are disabled
+	 * here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialize the critical nesting count ready for the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task. */
+	vStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing. Call the task
+	 * exit error function to prevent compiler warnings about a static function
+	 * not being called in the case that the application writer overrides this
+	 * functionality by defining configTASK_RETURN_ADDRESS. Call
+	 * vTaskSwitchContext() so link time optimization does not remove the
+	 * symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Not implemented in ports where there is nothing to return to.
+	 * Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+	{
+	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+	int32_t lIndex = 0;
+
+		/* Setup MAIR0. */
+		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+		/* This function is called automatically when the task is created - in
+		 * which case the stack region parameters will be valid.  At all other
+		 * times the stack parameters will not be valid and it is assumed that
+		 * the stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
+															( portMPU_REGION_NON_SHAREABLE ) |
+															( portMPU_REGION_READ_WRITE ) |
+															( portMPU_REGION_EXECUTE_NEVER );
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
+															( portMPU_RLAR_ATTR_INDEX0 ) |
+															( portMPU_RLAR_REGION_ENABLE );
+		}
+
+		/* User supplied configurable regions. */
+		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+		{
+			/* If xRegions is NULL i.e. the task has not specified any MPU
+			 * region, the else part ensures that all the configurable MPU
+			 * regions are invalidated. */
+			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+			{
+				/* Translate the generic region definition contained in xRegions
+				 * into the ARMv8 specific MPU settings that are then stored in
+				 * xMPUSettings. */
+				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+				/* Start address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
+																			( portMPU_REGION_NON_SHAREABLE );
+
+				/* RO/RW. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+				}
+				else
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+				}
+
+				/* XN. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+				}
+
+				/* End Address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
+																			( portMPU_RLAR_REGION_ENABLE );
+
+				/* Normal memory/ Device memory. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+				{
+					/* Attr1 in MAIR0 is configured as device memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+				}
+				else
+				{
+					/* Attr1 in MAIR0 is configured as normal memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+				}
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.h
new file mode 100644
index 000000000..2ecf04ea6
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.s b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.s
new file mode 100644
index 000000000..e38104c8f
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.s
@@ -0,0 +1,326 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN xSecureContext
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+	EXTERN SecureContext_SaveContext
+	EXTERN SecureContext_LoadContext
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vPortAllocateSecureContext
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMaskFromISR
+	PUBLIC vClearInterruptMaskFromISR
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+	PUBLIC vPortFreeSecureContext
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	ite ne
+	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	orr r0, r0, #1							/* r0 = r0 | 1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vPortAllocateSecureContext:
+	svc 0									/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r3, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r3]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	ldr  r4, [r3]							/* r4 = *r3 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	movs r4, #4								/* r4 = 4. */
+	str  r4, [r2]							/* Program RNR = 4. */
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	ldr  r2, =0xe000ed9c					/* r2 = 0xe000ed9c [Location of RBAR]. */
+	ldmia r3!, {r4-r11}						/* Read 4 set of RBAR/RLAR registers from TCB. */
+	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r4}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+	ldr  r5, =xSecureContext
+	str  r1, [r5]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	msr  control, r3						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r4									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+	ldr  r4, =xSecureContext
+	str  r1, [r4]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs  r0, control						/* Read the CONTROL register. */
+	bic r0, r0, #1							/* Clear the bit 0. */
+	msr  control, r0						/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	cpsie f
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR:
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR:
+	msr PRIMASK, r0
+	bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r1, psp								/* Read PSP in r1. */
+	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+
+	cbz r0, save_ns_context					/* No secure context to save. */
+	push {r0-r2, r14}
+	bl SecureContext_SaveContext
+	pop {r0-r3}								/* LR is now in r3. */
+	mov lr, r3								/* LR = r3. */
+	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r2, [r3]							/* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mrs r3, control							/* r3 = CONTROL. */
+	mov r4, lr								/* r4 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+#else /* configENABLE_MPU */
+	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
+#endif /* configENABLE_MPU */
+	b select_next_task
+
+	save_ns_context:
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r2, [r3]						/* Read pxCurrentTCB. */
+	#if ( configENABLE_FPU == 1 )
+		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+		it eq
+		vstmdbeq r1!, {s16-s31}				/* Store the FPU registers which are not saved automatically. */
+	#endif /* configENABLE_FPU */
+	#if ( configENABLE_MPU == 1 )
+		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		adds r1, r1, #16					/* r1 = r1 + 16. */
+		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mrs r3, control						/* r3 = CONTROL. */
+		mov r4, lr							/* r4 = LR/EXC_RETURN. */
+		subs r1, r1, #16					/* r1 = r1 - 16. */
+		stm r1, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		adds r1, r1, #12					/* r1 = r1 + 12. */
+		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mov r3, lr							/* r3 = LR/EXC_RETURN. */
+		subs r1, r1, #12					/* r1 = r1 - 12. */
+		stmia r1!, {r0, r2-r3}				/* Store xSecureContext, PSPLIM and LR on the stack. */
+	#endif /* configENABLE_MPU */
+
+	select_next_task:
+		cpsid i
+		bl vTaskSwitchContext
+		cpsie i
+
+		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r3, [r2]						/* Read pxCurrentTCB. */
+		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+
+	#if ( configENABLE_MPU == 1 )
+		dmb									/* Complete outstanding transfers before disabling MPU. */
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		bic r4, r4, #1						/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+		str r4, [r2]						/* Disable MPU. */
+
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
+		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+		str r4, [r2]						/* Program MAIR0. */
+		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+		movs r4, #4							/* r4 = 4. */
+		str r4, [r2]						/* Program RNR = 4. */
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+		ldr  r2, =0xe000ed9c				/* r2 = 0xe000ed9c [Location of RBAR]. */
+		ldmia r3!, {r4-r11}					/* Read 4 sets of RBAR/RLAR registers from TCB. */
+		stmia r2!, {r4-r11}					/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		orr r4, r4, #1						/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+		str r4, [r2]						/* Enable MPU. */
+		dsb									/* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+
+	#if ( configENABLE_MPU == 1 )
+		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		msr control, r3						/* Restore the CONTROL register value for the task. */
+		mov lr, r4							/* LR = r4. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r4}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r4}
+		mov lr, r4							/* LR = r4. */
+		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#else /* configENABLE_MPU */
+		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		mov lr, r3							/* LR = r3. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r3}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r3}
+		mov lr, r3							/* LR = r3. */
+		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#endif /* configENABLE_MPU */
+
+	restore_ns_context:
+		ldmia r1!, {r4-r11}					/* Restore the registers that are not automatically restored. */
+	#if ( configENABLE_FPU == 1 )
+		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+		it eq
+		vldmiaeq r1!, {s16-s31}				/* Restore the FPU registers which are not restored automatically. */
+	#endif /* configENABLE_FPU */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	tst lr, #4
+	ite eq
+	mrseq r0, msp
+	mrsne r0, psp
+	b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+vPortFreeSecureContext:
+	/* r0 = uint32_t *pulTCB. */
+	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
+	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
+	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
+	it ne
+	svcne 1									/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h
new file mode 100644
index 000000000..43a11d471
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h
@@ -0,0 +1,306 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M33"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+#pragma diag_suppress=Be006
+#pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.c
new file mode 100644
index 000000000..53535cd9e
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.c
@@ -0,0 +1,204 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
+	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
+	uint8_t *pucStackStart;				/**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+	uint32_t ulIPSR;
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* No stack for thread mode until a task's context is loaded. */
+		secureportSET_PSPLIM( securecontextNO_STACK );
+		secureportSET_PSP( securecontextNO_STACK );
+
+		#if( configENABLE_MPU == 1 )
+		{
+			/* Configure thread mode to use PSP and to be unprivileged. */
+			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+		}
+		#else /* configENABLE_MPU */
+		{
+			/* Configure thread mode to use PSP and to be privileged.. */
+			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+		}
+		#endif /* configENABLE_MPU */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+	uint8_t *pucStackMemory = NULL;
+	uint32_t ulIPSR;
+	SecureContextHandle_t xSecureContextHandle = NULL;
+	#if( configENABLE_MPU == 1 )
+		uint32_t *pulCurrentStackPointer = NULL;
+	#endif /* configENABLE_MPU */
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* Allocate the context structure. */
+		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+		if( xSecureContextHandle != NULL )
+		{
+			/* Allocate the stack space. */
+			pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+			if( pucStackMemory != NULL )
+			{
+				/* Since stack grows down, the starting point will be the last
+				 * location. Note that this location is next to the last
+				 * allocated byte because the hardware decrements the stack
+				 * pointer before writing i.e. if stack pointer is 0x2, a push
+				 * operation will decrement the stack pointer to 0x1 and then
+				 * write at 0x1. */
+				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+				/* The stack cannot go beyond this location. This value is
+				 * programmed in the PSPLIM register on context switch.*/
+				xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Store the correct CONTROL value for the task on the stack.
+					 * This value is programmed in the CONTROL register on
+					 * context switch. */
+					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+					pulCurrentStackPointer--;
+					if( ulIsTaskPrivileged )
+					{
+						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+					}
+					else
+					{
+						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+					}
+
+					/* Store the current stack pointer. This value is programmed in
+					 * the PSP register on context switch. */
+					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+				}
+				#else /* configENABLE_MPU */
+				{
+					/* Current SP is set to the starting of the stack. This
+					 * value programmed in the PSP register on context switch. */
+					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+
+				}
+				#endif /* configENABLE_MPU */
+			}
+			else
+			{
+				/* Free the context to avoid memory leak and make sure to return
+				 * NULL to indicate failure. */
+				vPortFree( xSecureContextHandle );
+				xSecureContextHandle = NULL;
+			}
+		}
+	}
+
+	return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+	uint32_t ulIPSR;
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* Ensure that valid parameters are passed. */
+		secureportASSERT( xSecureContextHandle != NULL );
+
+		/* Free the stack space. */
+		vPortFree( xSecureContextHandle->pucStackLimit );
+
+		/* Free the context itself. */
+		vPortFree( xSecureContextHandle );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.h
new file mode 100644
index 000000000..e148bff8e
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.h
@@ -0,0 +1,111 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include 
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK	0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext*	SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if( configENABLE_MPU == 1 )
+	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c
new file mode 100644
index 000000000..619db1ee3
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c
@@ -0,0 +1,48 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/* Functions implemented in assembler file. */
+extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
+extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+	SecureContext_LoadContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+	SecureContext_SaveContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
new file mode 100644
index 000000000..0cbfe6e72
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
@@ -0,0 +1,73 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+
+	PUBLIC SecureContext_LoadContextAsm
+	PUBLIC SecureContext_SaveContextAsm
+/*-----------------------------------------------------------*/
+
+SecureContext_LoadContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, load_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+#if ( configENABLE_MPU == 1 )
+	ldmia r1!, {r3}							/* Read CONTROL register value from task's stack. r3 = CONTROL. */
+	msr control, r3							/* CONTROL = r3. */
+#endif /* configENABLE_MPU */
+	msr psplim, r2							/* PSPLIM = r2. */
+	msr psp, r1								/* PSP = r1. */
+
+	load_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+SecureContext_SaveContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, save_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	mrs r1, psp								/* r1 = PSP. */
+#if ( configENABLE_FPU == 1 )
+	vstmdb r1!, {s0}						/* Trigger the defferred stacking of FPU registers. */
+	vldmia r1!, {s0}						/* Nullify the effect of the pervious statement. */
+#endif /* configENABLE_FPU */
+#if ( configENABLE_MPU == 1 )
+	mrs r2, control							/* r2 = CONTROL. */
+	stmdb r1!, {r2}							/* Store CONTROL value on the stack. */
+#endif /* configENABLE_MPU */
+	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	movs r1, #0								/* r1 = securecontextNO_STACK. */
+	msr psplim, r1							/* PSPLIM = securecontextNO_STACK. */
+	msr psp, r1								/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+
+	save_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.c
new file mode 100644
index 000000000..60fce5c66
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.c
@@ -0,0 +1,450 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+	#define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+	#define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+	#define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	 * heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
+	size_t xBlockSize;						/**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	 * blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	 * at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	 * entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	 * than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	 * make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	 * make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	 * before and the block after, then it's pxNextFreeBlock pointer will have
+	 * already been set, and should not be set here as that would make it point
+	 * to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	/* If this is the first call to malloc then the heap will require
+	 * initialisation to setup the list of free blocks. */
+	if( pxEnd == NULL )
+	{
+		prvHeapInit();
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Check the requested block size is not so large that the top bit is set.
+	 * The top bit of the block size member of the BlockLink_t structure is used
+	 * to determine who owns the block - the application or the kernel, so it
+	 * must be free. */
+	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+	{
+		/* The wanted size is increased so it can contain a BlockLink_t
+		 * structure in addition to the requested amount of bytes. */
+		if( xWantedSize > 0 )
+		{
+			xWantedSize += xHeapStructSize;
+
+			/* Ensure that blocks are always aligned to the required number of
+			 * bytes. */
+			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+			{
+				/* Byte alignment required. */
+				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+		{
+			/* Traverse the list from the start (lowest address) block until
+			 * one of adequate size is found. */
+			pxPreviousBlock = &xStart;
+			pxBlock = xStart.pxNextFreeBlock;
+			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+			{
+				pxPreviousBlock = pxBlock;
+				pxBlock = pxBlock->pxNextFreeBlock;
+			}
+
+			/* If the end marker was reached then a block of adequate size was
+			 * not found. */
+			if( pxBlock != pxEnd )
+			{
+				/* Return the memory space pointed to - jumping over the
+				 * BlockLink_t structure at its start. */
+				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+				/* This block is being returned for use so must be taken out
+				 * of the list of free blocks. */
+				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+				/* If the block is larger than required it can be split into
+				 * two. */
+				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+				{
+					/* This block is to be split into two.  Create a new
+					 * block following the number of bytes requested. The void
+					 * cast is used to prevent byte alignment warnings from the
+					 * compiler. */
+					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+					/* Calculate the sizes of two blocks split from the single
+					 * block. */
+					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+					pxBlock->xBlockSize = xWantedSize;
+
+					/* Insert the new block into the list of free blocks. */
+					prvInsertBlockIntoFreeList( pxNewBlockLink );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+				{
+					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* The block is being returned - it is allocated and owned by
+				 * the application and has no "next" block. */
+				pxBlock->xBlockSize |= xBlockAllocatedBit;
+				pxBlock->pxNextFreeBlock = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceMALLOC( pvReturn, xWantedSize );
+
+	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		 * before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				 * allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				secureportDISABLE_NON_SECURE_INTERRUPTS();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+				}
+				secureportENABLE_NON_SECURE_INTERRUPTS();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.h
new file mode 100644
index 000000000..69e4f2a86
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include 
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void *pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void *pv );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.c
new file mode 100644
index 000000000..c6525f755
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS			( 29UL )
+#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS				( 26UL )
+#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS			( 10UL )
+#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS			( 11UL )
+#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+	uint32_t ulIPSR;
+
+	 /* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
+	}
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+	uint32_t ulIPSR;
+
+	 /* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+		 * permitted. CP11 should be programmed to the same value as CP10. */
+		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+		 * that we can enable/disable lazy stacking in port.c file. */
+		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
+
+		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+		 * registers (S16-S31) are also pushed to stack on exception entry and
+		 * restored on exception return. */
+		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.h
new file mode 100644
index 000000000..6c5bc71f5
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h
new file mode 100644
index 000000000..760edab56
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT					8
+#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
+#else
+	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x )						\
+	if( ( x ) == 0 )								\
+	{												\
+		secureportDISABLE_SECURE_INTERRUPTS();		\
+		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
+		for( ;; );									\
+	}
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
new file mode 100644
index 000000000..bd85a6ffe
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/* Secure components includes. */
+	#include "secure_context.h"
+	#include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK				( 0x00000004 )
+#define portNVIC_SYSTICK_INT				( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
+#define portNVIC_PENDSVSET					( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY			( 255UL )
+#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE				( 3UL )
+#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS					( 20UL )
+#define portCPACR_CP11_POS					( 22UL )
+
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS					( 31UL )
+#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS					( 30UL )
+#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS				( 0UL )
+#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS				( 8UL )
+#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS				( 16UL )
+#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS				( 24UL )
+#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS				( 0UL )
+#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS				( 8UL )
+#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS				( 16UL )
+#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS				( 24UL )
+#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE			( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE						( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         FD
+	 * 1111 1111  1111 1111  1111 1111  1111 1101
+	 *
+	 * Bit[6] - 1 --> The exception was taken from the Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 1 --> The exception was taken to the Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
+#else
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         BC
+	 * 1111 1111  1111 1111  1111 1111  1011 1100
+	 *
+	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS			prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS				1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT				0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Setup the Memory Protection Unit (MPU).
+	 */
+	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+	/**
+	 * @brief Setup the Floating Point Unit (FPU).
+	 */
+	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Saved as part of the task context to indicate which context the
+	 * task is using on the secure side.
+	 */
+	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Stop and reset the SysTick. */
+	*( portNVIC_SYSTICK_CTRL ) = 0UL;
+	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	 * its caller as there is nothing to return to. If a task wants to exit it
+	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
+	 * to be triggered if configASSERT() is defined, then stop here so
+	 * application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		 * started to remove a compiler warning about the function being
+		 * defined but never called.  ulDummy is used purely to quieten other
+		 * warnings about code appearing after this function is called - making
+		 * ulDummy volatile makes the compiler think the function could return
+		 * and therefore not output an 'unreachable code' warning for code that
+		 * appears after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __privileged_functions_start__;
+		extern uint32_t * __privileged_functions_end__;
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+		extern uint32_t * __unprivileged_flash_start__;
+		extern uint32_t * __unprivileged_flash_end__;
+		extern uint32_t * __privileged_sram_start__;
+		extern uint32_t * __privileged_sram_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __privileged_functions_start__[];
+		extern uint32_t __privileged_functions_end__[];
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+		extern uint32_t __unprivileged_flash_start__[];
+		extern uint32_t __unprivileged_flash_end__[];
+		extern uint32_t __privileged_sram_start__[];
+		extern uint32_t __privileged_sram_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+
+		/* Check that the MPU is present. */
+		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+		{
+			/* MAIR0 - Index 0. */
+			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+			/* MAIR0 - Index 1. */
+			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+			/* Setup privileged flash as Read Only so that privileged tasks can
+			 * read it but not modify. */
+			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged flash as Read Only by both privileged and
+			 * unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged syscalls flash as Read Only by both privileged
+			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup RAM containing kernel data for privileged access only. */
+			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+								( portMPU_REGION_EXECUTE_NEVER );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Enable mem fault. */
+			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+			/* Enable MPU with privileged background access i.e. unmapped
+			 * regions have privileged access. */
+			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			/* Enable non-secure access to the FPU. */
+			SecureInit_EnableNSFPUAccess();
+		}
+		#endif /* configENABLE_TRUSTZONE */
+
+		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+		 * unprivileged code should be able to access FPU. CP11 should be
+		 * programmed to the same value as CP10. */
+		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+							);
+
+		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
+		 * context on exception entry and restore on exception return.
+		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
+		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+	}
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	portDISABLE_INTERRUPTS();
+	ulCriticalNesting++;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	configASSERT( ulCriticalNesting );
+	ulCriticalNesting--;
+
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	uint32_t ulR0;
+	#if( configENABLE_MPU == 1 )
+		uint32_t ulControl, ulIsTaskPrivileged;
+	#endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
+	 * R12, LR, PC, xPSR. */
+	ulPC = pulCallerStackAddress[ 6 ];
+	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+	switch( ucSVCNumber )
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+			case portSVC_ALLOCATE_SECURE_CONTEXT:
+			{
+				/* R0 contains the stack size passed as parameter to the
+				 * vPortAllocateSecureContext function. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Read the CONTROL register value. */
+					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+					/* The task that raised the SVC is privileged if Bit[0]
+					 * in the CONTROL register is 0. */
+					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+				}
+				#else
+				{
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0 );
+				}
+				#endif /* configENABLE_MPU */
+
+				configASSERT( xSecureContext != NULL );
+				SecureContext_LoadContext( xSecureContext );
+			}
+			break;
+
+			case portSVC_FREE_SECURE_CONTEXT:
+			{
+				/* R0 contains the secure context handle to be freed. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				/* Free the secure context. */
+				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+			}
+			break;
+		#endif /* configENABLE_TRUSTZONE */
+
+		case portSVC_START_SCHEDULER:
+		{
+			#if( configENABLE_TRUSTZONE == 1 )
+			{
+				/* De-prioritize the non-secure exceptions so that the
+				 * non-secure pendSV runs at the lowest priority. */
+				SecureInit_DePrioritizeNSExceptions();
+
+				/* Initialize the secure context management system. */
+				SecureContext_Init();
+			}
+			#endif /* configENABLE_TRUSTZONE */
+
+			#if( configENABLE_FPU == 1 )
+			{
+				/* Setup the Floating Point Unit (FPU). */
+				prvSetupFPU();
+			}
+			#endif /* configENABLE_FPU */
+
+			/* Setup the context of the first task so that the first task starts
+			 * executing. */
+			vRestoreContextOfFirstTask();
+		}
+		break;
+
+		#if( configENABLE_MPU == 1 )
+			case portSVC_RAISE_PRIVILEGE:
+			{
+				/* Only raise the privilege, if the svc was raised from any of
+				 * the system calls. */
+				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+				{
+					vRaisePrivilege();
+				}
+			}
+			break;
+		#endif /* configENABLE_MPU */
+
+		default:
+		{
+			/* Incorrect SVC call. */
+			configASSERT( pdFALSE );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	 * interrupt. */
+	#if( portPRELOAD_REGISTERS == 0 )
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
+		*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#else /* portPRELOAD_REGISTERS */
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
+		pxTopOfStack--;
+		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#endif /* portPRELOAD_REGISTERS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+	#if( configENABLE_MPU == 1 )
+	{
+		/* Setup the Memory Protection Unit (MPU). */
+		prvSetupMPU();
+	}
+	#endif /* configENABLE_MPU */
+
+	/* Start the timer that generates the tick ISR. Interrupts are disabled
+	 * here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialize the critical nesting count ready for the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task. */
+	vStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing. Call the task
+	 * exit error function to prevent compiler warnings about a static function
+	 * not being called in the case that the application writer overrides this
+	 * functionality by defining configTASK_RETURN_ADDRESS. Call
+	 * vTaskSwitchContext() so link time optimization does not remove the
+	 * symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Not implemented in ports where there is nothing to return to.
+	 * Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+	{
+	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+	int32_t lIndex = 0;
+
+		/* Setup MAIR0. */
+		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+		/* This function is called automatically when the task is created - in
+		 * which case the stack region parameters will be valid.  At all other
+		 * times the stack parameters will not be valid and it is assumed that
+		 * the stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
+															( portMPU_REGION_NON_SHAREABLE ) |
+															( portMPU_REGION_READ_WRITE ) |
+															( portMPU_REGION_EXECUTE_NEVER );
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
+															( portMPU_RLAR_ATTR_INDEX0 ) |
+															( portMPU_RLAR_REGION_ENABLE );
+		}
+
+		/* User supplied configurable regions. */
+		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+		{
+			/* If xRegions is NULL i.e. the task has not specified any MPU
+			 * region, the else part ensures that all the configurable MPU
+			 * regions are invalidated. */
+			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+			{
+				/* Translate the generic region definition contained in xRegions
+				 * into the ARMv8 specific MPU settings that are then stored in
+				 * xMPUSettings. */
+				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+				/* Start address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
+																			( portMPU_REGION_NON_SHAREABLE );
+
+				/* RO/RW. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+				}
+				else
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+				}
+
+				/* XN. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+				}
+
+				/* End Address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
+																			( portMPU_RLAR_REGION_ENABLE );
+
+				/* Normal memory/ Device memory. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+				{
+					/* Attr1 in MAIR0 is configured as device memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+				}
+				else
+				{
+					/* Attr1 in MAIR0 is configured as normal memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+				}
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
new file mode 100644
index 000000000..2ecf04ea6
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
new file mode 100644
index 000000000..400755b66
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
@@ -0,0 +1,242 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMaskFromISR
+	PUBLIC vClearInterruptMaskFromISR
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	ite ne
+	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	orr r0, r0, #1							/* r0 = r0 | 1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r1, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r1]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
+	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str r3, [r2]							/* Program MAIR0. */
+	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
+	movs r3, #4								/* r3 = 4. */
+	str r3, [r2]							/* Program RNR = 4. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
+	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
+	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	msr  control, r2						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r2}						/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r2									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs  r0, control						/* Read the CONTROL register. */
+	bic r0, r0, #1							/* Clear the bit 0. */
+	msr  control, r0						/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	cpsie f
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR:
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR:
+	msr PRIMASK, r0
+	bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r0, psp								/* Read PSP in r0. */
+#if ( configENABLE_FPU == 1 )
+	tst lr, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	it eq
+	vstmdbeq r0!, {s16-s31}					/* Store the FPU registers which are not saved automatically. */
+#endif /* configENABLE_FPU */
+#if ( configENABLE_MPU == 1 )
+	mrs r1, psplim							/* r1 = PSPLIM. */
+	mrs r2, control							/* r2 = CONTROL. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmdb r0!, {r1-r11}						/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+#else /* configENABLE_MPU */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmdb r0!, {r2-r11}						/* Store on the stack - PSPLIM, LR and registers that are not automatically. */
+#endif /* configENABLE_MPU */
+
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+	str r0, [r1]							/* Save the new top of stack in TCB. */
+
+	cpsid i
+	bl vTaskSwitchContext
+	cpsie i
+
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+	ldr r0, [r1]							/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
+	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str r3, [r2]							/* Program MAIR0. */
+	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
+	movs r3, #4								/* r3 = 4. */
+	str r3, [r2]							/* Program RNR = 4. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
+	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
+	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldmia r0!, {r1-r11}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+#else /* configENABLE_MPU */
+	ldmia r0!, {r2-r11}						/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+	tst r3, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	it eq
+	vldmiaeq r0!, {s16-s31}					/* Restore the FPU registers which are not restored automatically. */
+#endif /* configENABLE_FPU */
+
+ #if ( configENABLE_MPU == 1 )
+	msr psplim, r1							/* Restore the PSPLIM register value for the task. */
+	msr control, r2							/* Restore the CONTROL register value for the task. */
+#else /* configENABLE_MPU */
+	msr psplim, r2							/* Restore the PSPLIM register value for the task. */
+#endif /* configENABLE_MPU */
+	msr psp, r0								/* Remember the new top of stack for the task. */
+	bx r3
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	tst lr, #4
+	ite eq
+	mrseq r0, msp
+	mrsne r0, psp
+	b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
new file mode 100644
index 000000000..43a11d471
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -0,0 +1,306 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M33"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+#pragma diag_suppress=Be006
+#pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c
index 2710d2feb..f405163ea 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s
index 20fd9d2e9..da715ae46 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h
index f19ef4521..08f5d1c3f 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4_MPU/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4_MPU/port.c
index a13af49d1..b843e5692 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4_MPU/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4_MPU/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -10,8 +10,7 @@
  * subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ * copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
@@ -143,21 +142,14 @@ have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
 /*
  * Configure a number of standard MPU regions that are used by all tasks.
  */
-PRIVILEGED_FUNCTION static void prvSetupMPU( void );
+static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 
 /*
  * Return the smallest MPU region size that a given number of bytes will fit
  * into.  The region size is returned as the value that should be programmed
  * into the region attribute register for that region.
  */
-PRIVILEGED_FUNCTION static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes );
-
-/*
- * Checks to see if being called from the context of an unprivileged task, and
- * if so raises the privilege level and returns false - otherwise does nothing
- * other than return true.
- */
-extern BaseType_t xPortRaisePrivilege( void );
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
 
 /*
  * Setup the timer to generate the tick interrupts.  The implementation in this
@@ -169,12 +161,12 @@ void vPortSetupTimerInterrupt( void );
 /*
  * Exception handlers.
  */
-PRIVILEGED_FUNCTION void xPortSysTickHandler( void );
+void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
 
 /*
  * Start first task is a separate function so it can be tested in isolation.
  */
-PRIVILEGED_FUNCTION extern void vPortStartFirstTask( void );
+extern void vPortStartFirstTask( void ) PRIVILEGED_FUNCTION;
 
 /*
  * Turn the VFP on.
@@ -189,8 +181,20 @@ void vPortSVCHandler_C( uint32_t *pulParam );
 /*
  * Called from the SVC handler used to start the scheduler.
  */
-PRIVILEGED_FUNCTION extern void vPortRestoreContextOfFirstTask( void );
+extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
 
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
 /*-----------------------------------------------------------*/
 
 /* Each task maintains its own interrupt status in the critical nesting
@@ -484,6 +488,9 @@ extern uint32_t __FLASH_segment_end__;
 extern uint32_t __privileged_data_start__;
 extern uint32_t __privileged_data_end__;
 
+	/* Check the expected MPU is present. */
+	if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+	{
 		/* First setup the entire flash for unprivileged read only access. */
 		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
 											( portMPU_REGION_VALID ) |
@@ -532,6 +539,7 @@ extern uint32_t __privileged_data_end__;
 
 		/* Enable the MPU with the background region configured. */
 		portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+	}
 }
 /*-----------------------------------------------------------*/
 
@@ -559,18 +567,6 @@ uint32_t ulRegionSize, ulReturnValue = 4;
 }
 /*-----------------------------------------------------------*/
 
-void vPortResetPrivilege( BaseType_t xRunningPrivileged )
-{
-	if( xRunningPrivileged != pdTRUE )
-	{
-		__asm volatile ( " mrs r0, control 	\n" \
-						 " orr r0, r0, #1	\n" \
-						 " msr control, r0	\n"	\
-						 :::"r0", "memory" );
-	}
-}
-/*-----------------------------------------------------------*/
-
 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
 {
 extern uint32_t __SRAM_segment_start__;
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4_MPU/portasm.s b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4_MPU/portasm.s
index f7410694e..37f1a805c 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4_MPU/portasm.s
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4_MPU/portasm.s
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -10,8 +10,7 @@
  * subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ * copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
@@ -40,7 +39,8 @@
 	PUBLIC vPortStartFirstTask
 	PUBLIC vPortEnableVFP
 	PUBLIC vPortRestoreContextOfFirstTask
-	PUBLIC xPortRaisePrivilege
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
 
 /*-----------------------------------------------------------*/
 
@@ -115,7 +115,7 @@ vPortSVCHandler:
 
 /*-----------------------------------------------------------*/
 
-vPortStartFirstTask
+vPortStartFirstTask:
 	/* Use the NVIC offset register to locate the stack. */
 	ldr r0, =0xE000ED08
 	ldr r0, [r0]
@@ -137,7 +137,7 @@ vPortStartFirstTask
 
 /*-----------------------------------------------------------*/
 
-vPortRestoreContextOfFirstTask
+vPortRestoreContextOfFirstTask:
 	/* Use the NVIC offset register to locate the stack. */
 	ldr r0, =0xE000ED08
 	ldr r0, [r0]
@@ -168,7 +168,7 @@ vPortRestoreContextOfFirstTask
 
 /*-----------------------------------------------------------*/
 
-vPortEnableVFP
+vPortEnableVFP:
 	/* The FPU enable bits are in the CPACR. */
 	ldr.w r0, =0xE000ED88
 	ldr	r1, [r0]
@@ -180,19 +180,20 @@ vPortEnableVFP
 
 /*-----------------------------------------------------------*/
 
-xPortRaisePrivilege
-	mrs r0, control
-	/* Is the task running privileged? */
-	tst r0, #1
-	itte ne
-	/* CONTROL[0]!=0, return false. */
-	movne r0, #0
-	/* Switch to privileged. */
-	svcne 2	/* 2 == portSVC_RAISE_PRIVILEGE */
-	/* CONTROL[0]==0, return true. */
-	moveq r0, #1
-	bx lr
+xIsPrivileged:
+	mrs r0, control		/* r0 = CONTROL. */
+	tst r0, #1			/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	ite ne
+	movne r0, #0		/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	moveq r0, #1		/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	bx lr				/* Return. */
+/*-----------------------------------------------------------*/
 
+vResetPrivilege:
+	mrs r0, control		/* r0 = CONTROL. */
+	orr r0, r0, #1		/* r0 = r0 | 1. */
+	msr control, r0		/* CONTROL = r0. */
+	bx lr				/* Return to the caller. */
+/*-----------------------------------------------------------*/
 
 	END
-
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4_MPU/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4_MPU/portmacro.h
index 59d9c8b38..ecdd0cfe4 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4_MPU/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4_MPU/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -10,8 +10,7 @@
  * subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ * copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
@@ -191,11 +190,28 @@ not necessary for to use this port.  They are defined so the common demo files
 
 /* portNOP() is not required by this port. */
 #define portNOP()
+/*-----------------------------------------------------------*/
 
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
 
-/* Set the privilege level to user mode if xRunningPrivileged is false. */
-void vPortResetPrivilege( BaseType_t xRunningPrivileged );
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED()			xIsPrivileged()
 
+/**
+ * @brief Raise an SVC request to raise privilege.
+*/
+#define portRAISE_PRIVILEGE()		__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE()		vResetPrivilege()
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/port.c
index ee846daba..503f5db34 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portasm.s b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
index 5b492f1f3..ad8070c00 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
index 21146f4aa..9f3c261b8 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7_MPU/r0p1/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7_MPU/r0p1/port.c
index 43c1278ff..b884ba0a7 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7_MPU/r0p1/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7_MPU/r0p1/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -29,7 +29,7 @@
  * Implementation of functions defined in portable.h for the ARM CM4F port.
  *----------------------------------------------------------*/
 
-/* Compiler includes. */
+/* IAR includes. */
 #include 
 
 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
@@ -42,16 +42,15 @@ task.h is included from an application file. */
 #include "task.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
 #ifndef __ARMVFP__
 	#error This port can only be used when the project options are configured to enable hardware floating point support.
 #endif
 
-#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
+#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
 	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
 #endif
 
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
 #ifndef configSYSTICK_CLOCK_HZ
 	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
 	/* Ensure the SysTick is clocked at the same frequency as the core. */
@@ -63,13 +62,28 @@ task.h is included from an application file. */
 #endif
 
 /* Constants required to manipulate the core.  Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_CTRL_REG				( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG				( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG		( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG					( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
 #define portNVIC_SYSPRI1_REG					( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
 #define portNVIC_SYS_CTRL_STATE_REG				( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portNVIC_MEM_FAULT_ENABLE				( 1UL << 16UL )
+
+/* Constants required to access and manipulate the MPU. */
+#define portMPU_TYPE_REG						( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_REGION_BASE_ADDRESS_REG			( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
+#define portMPU_REGION_ATTRIBUTE_REG			( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
+#define portMPU_CTRL_REG						( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portEXPECTED_MPU_TYPE_VALUE				( 8UL << 8UL ) /* 8 regions, unified. */
+#define portMPU_ENABLE							( 0x01UL )
+#define portMPU_BACKGROUND_ENABLE				( 1UL << 2UL )
+#define portPRIVILEGED_EXECUTION_START_ADDRESS	( 0UL )
+#define portMPU_REGION_VALID					( 0x10UL )
+#define portMPU_REGION_ENABLE					( 0x01UL )
+#define portPERIPHERALS_START_ADDRESS			0x40000000UL
+#define portPERIPHERALS_END_ADDRESS				0x5FFFFFFFUL
+
 /* ...then bits in the registers. */
 #define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
 #define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
@@ -79,7 +93,7 @@ task.h is included from an application file. */
 
 #define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
 #define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI						( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
+#define portNVIC_SVC_PRI					( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
 
 /* Constants required to check the validity of an interrupt priority. */
 #define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
@@ -94,29 +108,15 @@ task.h is included from an application file. */
 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
 #define portVECTACTIVE_MASK					( 0xFFUL )
 
-/* Constants required to access and manipulate the MPU. */
-#define portMPU_TYPE_REG						( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_REGION_BASE_ADDRESS_REG			( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
-#define portMPU_REGION_ATTRIBUTE_REG			( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
-#define portMPU_CTRL_REG						( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portEXPECTED_MPU_TYPE_VALUE				( 8UL << 8UL ) /* 8 regions, unified. */
-#define portMPU_ENABLE							( 0x01UL )
-#define portMPU_BACKGROUND_ENABLE				( 1UL << 2UL )
-#define portPRIVILEGED_EXECUTION_START_ADDRESS	( 0UL )
-#define portMPU_REGION_VALID					( 0x10UL )
-#define portMPU_REGION_ENABLE					( 0x01UL )
-#define portPERIPHERALS_START_ADDRESS			0x40000000UL
-#define portPERIPHERALS_END_ADDRESS				0x5FFFFFFFUL
-
 /* Constants required to manipulate the VFP. */
 #define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
 #define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
 
 /* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR						( 0x01000000UL )
-#define portINITIAL_EXEC_RETURN					( 0xfffffffdUL )
-#define portINITIAL_CONTROL_IF_UNPRIVILEGED		( 0x03 )
-#define portINITIAL_CONTROL_IF_PRIVILEGED		( 0x02 )
+#define portINITIAL_XPSR					( 0x01000000 )
+#define portINITIAL_EXC_RETURN				( 0xfffffffd )
+#define portINITIAL_CONTROL_IF_UNPRIVILEGED	( 0x03 )
+#define portINITIAL_CONTROL_IF_PRIVILEGED	( 0x02 )
 
 /* Offsets in the stack to the parameters when inside the SVC handler. */
 #define portOFFSET_TO_PC						( 6 )
@@ -133,68 +133,83 @@ calculations. */
 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
 #define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
 
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
 /*
  * Configure a number of standard MPU regions that are used by all tasks.
  */
-PRIVILEGED_FUNCTION static void prvSetupMPU( void );
+static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 
 /*
  * Return the smallest MPU region size that a given number of bytes will fit
  * into.  The region size is returned as the value that should be programmed
  * into the region attribute register for that region.
  */
-PRIVILEGED_FUNCTION static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes );
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
 
 /*
  * Exception handlers.
  */
-void xPortSysTickHandler( void );
+void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
 
 /*
  * Start first task is a separate function so it can be tested in isolation.
  */
-extern void vPortStartFirstTask( void );
-
-extern void vRestoreContextOfFirstTask( void );
+extern void vPortStartFirstTask( void ) PRIVILEGED_FUNCTION;
 
 /*
  * Turn the VFP on.
  */
 extern void vPortEnableVFP( void );
 
+/*
+ * The C portion of the SVC handler.
+ */
+void vPortSVCHandler_C( uint32_t *pulParam );
+
+/*
+ * Called from the SVC handler used to start the scheduler.
+ */
+extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
 /*-----------------------------------------------------------*/
 
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+#if( configUSE_TICKLESS_IDLE == 1 )
 /*
  * The number of SysTick increments that make up one tick period.
  */
-#if configUSE_TICKLESS_IDLE == 1
 	static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
 /*
  * The maximum number of tick periods that can be suppressed is limited by the
  * 24 bit resolution of the SysTick timer.
  */
-#if configUSE_TICKLESS_IDLE == 1
 	static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
 
 /*
  * Compensate for the CPU cycles that pass while the SysTick is stopped (low
  * power functionality only.
  */
-#if configUSE_TICKLESS_IDLE == 1
 	static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 
@@ -203,7 +218,7 @@ extern void vPortEnableVFP( void );
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( configASSERT_DEFINED == 1 )
+#if( configASSERT_DEFINED == 1 )
 	 static uint8_t ucMaxSysCallPriority = 0;
 	 static uint32_t ulMaxPRIGROUPValue = 0;
 	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
@@ -236,61 +251,59 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 	/* A save method is being used that requires each task to maintain its
 	own exec return value. */
 	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_EXEC_RETURN;
-        
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
 	pxTopOfStack -= 9;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
-        
-        if( xRunPrivileged == pdTRUE )
+
+	if( xRunPrivileged == pdTRUE )
 	{
-          *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
+		*pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
 	}
 	else
 	{
-          *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
+		*pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
 	}
-        
+
 	return pxTopOfStack;
 }
-
 /*-----------------------------------------------------------*/
-void vSVCHandler( uint32_t *pulParam )
+
+void vPortSVCHandler_C( uint32_t *pulParam )
 {
 uint8_t ucSVCNumber;
-uint32_t ulReg;
 
 	/* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
 	xPSR.  The first argument (r0) is pulParam[ 0 ]. */
 	ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
 	switch( ucSVCNumber )
 	{
-		case portSVC_START_SCHEDULER :	
-                  portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
-		  vRestoreContextOfFirstTask();
-		 break;
-
-		case portSVC_YIELD :
-                  portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		  /* Barriers are normally not required
-		     but do ensure the code is completely
-		     within the specified behaviour for the
-		     architecture. */
-		  __DSB();
-		  __ISB();
-                  break;
-
-		case portSVC_RAISE_PRIVILEGE :
-
-                            ulReg = __get_CONTROL();
-          ulReg &= 0xFFFFFFFE;
-          __set_CONTROL(ulReg);
-                  
-		break;
-
-		default	:	/* Unknown SVC call. */
-                break;
+		case portSVC_START_SCHEDULER	:	portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
+											vPortRestoreContextOfFirstTask();
+											break;
+
+		case portSVC_YIELD				:	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+											/* Barriers are normally not required
+											but do ensure the code is completely
+											within the specified behaviour for the
+											architecture. */
+											__asm volatile( "dsb" ::: "memory" );
+											__asm volatile( "isb" );
+
+											break;
+
+		case portSVC_RAISE_PRIVILEGE	:	__asm volatile
+											(
+												"	mrs r1, control		\n" /* Obtain current control value. */
+												"	bic r1, r1, #1		\n" /* Set privilege bit. */
+												"	msr control, r1		\n" /* Write back new control value. */
+												::: "r1", "memory"
+											);
+											break;
+
+		default							:	/* Unknown SVC call. */
+											break;
 	}
 }
-
 /*-----------------------------------------------------------*/
 
 /*
@@ -298,6 +311,10 @@ uint32_t ulReg;
  */
 BaseType_t xPortStartScheduler( void )
 {
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
 	#if( configASSERT_DEFINED == 1 )
 	{
 		volatile uint32_t ulOriginalPriority;
@@ -331,6 +348,24 @@ BaseType_t xPortStartScheduler( void )
 			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
 		}
 
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
 		/* Shift the priority group value back to its position within the AIRCR
 		register. */
 		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
@@ -345,7 +380,7 @@ BaseType_t xPortStartScheduler( void )
 	/* Make PendSV and SysTick the lowest priority interrupts. */
 	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
 	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
-        
+
 	/* Configure the regions in the MPU that are common to all tasks. */
 	prvSetupMPU();
 
@@ -380,9 +415,13 @@ void vPortEndScheduler( void )
 
 void vPortEnterCritical( void )
 {
+ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
 	portDISABLE_INTERRUPTS();
 	uxCriticalNesting++;
 
+	vPortResetPrivilege( xRunningPrivileged );
+
 	/* This is not the interrupt safe version of the enter critical function so
 	assert() if it is being called from an interrupt context.  Only API
 	functions that end in "FromISR" can be used in an interrupt.  Only assert if
@@ -397,12 +436,17 @@ void vPortEnterCritical( void )
 
 void vPortExitCritical( void )
 {
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
 	configASSERT( uxCriticalNesting );
+
 	uxCriticalNesting--;
 	if( uxCriticalNesting == 0 )
 	{
 		portENABLE_INTERRUPTS();
 	}
+
+	vPortResetPrivilege( xRunningPrivileged );
 }
 /*-----------------------------------------------------------*/
 
@@ -424,24 +468,9 @@ void xPortSysTickHandler( void )
 	}
 	portENABLE_INTERRUPTS();
 }
-
-/*-----------------------------------------------------------*/
-
-void vPortResetPrivilege( BaseType_t xRunningPrivileged )
-{
-uint32_t ulReg;
-	
-	if( xRunningPrivileged != pdTRUE ) 
-	{
-          ulReg = __get_CONTROL();
-          ulReg |= 0x1;
-          __set_CONTROL(ulReg);
-	}
-}
-
 /*-----------------------------------------------------------*/
 
-#if configUSE_TICKLESS_IDLE == 1
+#if( configUSE_TICKLESS_IDLE == 1 )
 
 	__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
 	{
@@ -594,7 +623,6 @@ uint32_t ulReg;
 	}
 
 #endif /* #if configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
 
 /*
  * Setup the systick timer to generate the tick interrupts at the required
@@ -602,14 +630,18 @@ uint32_t ulReg;
  */
 __weak void vPortSetupTimerInterrupt( void )
 {
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
 	/* Calculate the constants required to configure the tick interrupt. */
-	#if( configUSE_TICKLESS_IDLE == 1 )
+#if( configUSE_TICKLESS_IDLE == 1 )
 	{
 		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
 		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
 		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
 	}
-	#endif /* configUSE_TICKLESS_IDLE */
+#endif /* configUSE_TICKLESS_IDLE */
 
 	/* Configure SysTick to interrupt at the requested rate. */
 	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
@@ -625,6 +657,9 @@ extern uint32_t __FLASH_segment_end__;
 extern uint32_t __privileged_data_start__;
 extern uint32_t __privileged_data_end__;
 
+	/* Check the expected MPU is present. */
+	if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+	{
 		/* First setup the entire flash for unprivileged read only access. */
 		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
 											( portMPU_REGION_VALID ) |
@@ -673,6 +708,7 @@ extern uint32_t __privileged_data_end__;
 
 		/* Enable the MPU with the background region configured. */
 		portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+	}
 }
 /*-----------------------------------------------------------*/
 
@@ -699,14 +735,13 @@ uint32_t ulRegionSize, ulReturnValue = 4;
 	return ( ulReturnValue << 1UL );
 }
 /*-----------------------------------------------------------*/
+
 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
 {
 extern uint32_t __SRAM_segment_start__;
 extern uint32_t __SRAM_segment_end__;
 extern uint32_t __privileged_data_start__;
 extern uint32_t __privileged_data_end__;
-
-	
 int32_t lIndex;
 uint32_t ul;
 
@@ -795,7 +830,6 @@ uint32_t ul;
 		}
 	}
 }
-
 /*-----------------------------------------------------------*/
 
 #if( configASSERT_DEFINED == 1 )
@@ -806,7 +840,7 @@ uint32_t ul;
 	uint8_t ucCurrentPriority;
 
 		/* Obtain the number of the currently executing interrupt. */
-		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
 
 		/* Is the interrupt number a user defined interrupt? */
 		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
@@ -852,7 +886,7 @@ uint32_t ul;
 		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
 		scheduler.  Note however that some vendor specific peripheral libraries
 		assume a non-zero priority group setting, in which cases using a value
-		of zero will result in unpredicable behaviour. */
+		of zero will result in unpredictable behaviour. */
 		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
 	}
 
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7_MPU/r0p1/portasm.s b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7_MPU/r0p1/portasm.s
index 47e8f31ec..86d5b297b 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7_MPU/r0p1/portasm.s
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7_MPU/r0p1/portasm.s
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -32,17 +32,15 @@
 
 	EXTERN pxCurrentTCB
 	EXTERN vTaskSwitchContext
-        EXTERN vSVCHandler
+	EXTERN vPortSVCHandler_C
 
 	PUBLIC xPortPendSVHandler
 	PUBLIC vPortSVCHandler
 	PUBLIC vPortStartFirstTask
-        PUBLIC vRestoreContextOfFirstTask
 	PUBLIC vPortEnableVFP
-        PUBLIC xPortRaisePrivilege
-        PUBLIC vPortSwitchToUserMode
-        
-
+	PUBLIC vPortRestoreContextOfFirstTask
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
 
 /*-----------------------------------------------------------*/
 
@@ -58,37 +56,39 @@ xPortPendSVHandler:
 	it eq
 	vstmdbeq r0!, {s16-s31}
 
+	/* Save the core registers. */
 	mrs r1, control
-        /* Save the core registers. */
 	stmdb r0!, {r1, r4-r11, r14}
 
 	/* Save the new top of stack into the first member of the TCB. */
 	str r0, [r2]
 
-	stmdb sp!, {r3}
+	stmdb sp!, {r0, r3}
 	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-  cpsid i
+    cpsid i
 	msr basepri, r0
 	dsb
 	isb
-  cpsie i
+    cpsie i
 	bl vTaskSwitchContext
 	mov r0, #0
 	msr basepri, r0
-	ldmia sp!, {r3}
+	ldmia sp!, {r0, r3}
 
 	/* The first item in pxCurrentTCB is the task top of stack. */
 	ldr r1, [r3]
 	ldr r0, [r1]
-        
- 	add r1, r1, #4					/* Move onto the second item in the TCB... */
-	ldr r2, =0xe000ed9c				/* Region Base Address register. */
-	ldmia r1!, {r4-r11}				/* Read 4 sets of MPU registers. */
-	stmia r2!, {r4-r11}				/* Write 4 sets of MPU registers. */
-
-	/* Pop the core registers. */
+	/* Move onto the second item in the TCB... */
+	add r1, r1, #4
+	/* Region Base Address register. */
+	ldr r2, =0xe000ed9c
+	/* Read 4 sets of MPU registers. */
+	ldmia r1!, {r4-r11}
+	/* Write 4 sets of MPU registers. */
+	stmia r2!, {r4-r11}
+	/* Pop the registers that are not automatically saved on exception entry. */
 	ldmia r0!, {r3-r11, r14}
-        msr control, r3
+	msr control, r3
 
 	/* Is the task using the FPU context?  If so, pop the high vfp registers
 	too. */
@@ -98,12 +98,6 @@ xPortPendSVHandler:
 
 	msr psp, r0
 	isb
-	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
-		#if WORKAROUND_PMU_CM001 == 1
-			push { r14 }
-			pop { pc }
-		#endif
-	#endif
 
 	bx r14
 
@@ -111,7 +105,6 @@ xPortPendSVHandler:
 /*-----------------------------------------------------------*/
 
 vPortSVCHandler:
-	/* Assumes psp was in use. */
 	#ifndef USE_PROCESS_STACK	/* Code should not be required if a main() is using the process stack. */
 		tst lr, #4
 		ite eq
@@ -120,7 +113,7 @@ vPortSVCHandler:
 	#else
 		mrs r0, psp
 	#endif
-		b vSVCHandler
+		b vPortSVCHandler_C
 
 /*-----------------------------------------------------------*/
 
@@ -131,33 +124,50 @@ vPortStartFirstTask:
 	ldr r0, [r0]
 	/* Set the msp back to the start of the stack. */
 	msr msp, r0
+	/* Clear the bit that indicates the FPU is in use in case the FPU was used
+	before the scheduler was started - which would otherwise result in the
+	unnecessary leaving of space in the SVC stack for lazy saving of FPU
+	registers. */
+	mov r0, #0
+	msr control, r0
 	/* Call SVC to start the first task. */
 	cpsie i
 	cpsie f
 	dsb
 	isb
-	svc 0	/* System call to start first task. */
-  
-vRestoreContextOfFirstTask:
+	svc 0
 
-	ldr r0, =0xE000ED08				/* Use the NVIC offset register to locate the stack. */
+/*-----------------------------------------------------------*/
+
+vPortRestoreContextOfFirstTask:
+	/* Use the NVIC offset register to locate the stack. */
+	ldr r0, =0xE000ED08
 	ldr r0, [r0]
 	ldr r0, [r0]
-	msr msp, r0						/* Set the msp back to the start of the stack. */
-	ldr	r3, =pxCurrentTCB			/* Restore the context. */
+	/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	/* Restore the context. */
+	ldr	r3, =pxCurrentTCB
 	ldr r1, [r3]
-	ldr r0, [r1]					/* The first item in the TCB is the task top of stack. */
-	add r1, r1, #4					/* Move onto the second item in the TCB... */
-	ldr r2, =0xe000ed9c				/* Region Base Address register. */
-	ldmia r1!, {r4-r11}				/* Read 4 sets of MPU registers. */
-	stmia r2!, {r4-r11}				/* Write 4 sets of MPU registers. */
-	ldmia r0!, {r3-r11, r14}	/* Pop the registers that are not automatically saved on exception entry. */
+	/* The first item in the TCB is the task top of stack. */
+	ldr r0, [r1]
+	/* Move onto the second item in the TCB... */
+	add r1, r1, #4
+	/* Region Base Address register. */
+	ldr r2, =0xe000ed9c
+	/* Read 4 sets of MPU registers. */
+	ldmia r1!, {r4-r11}
+	/* Write 4 sets of MPU registers. */
+	stmia r2!, {r4-r11}
+	/* Pop the registers that are not automatically saved on exception entry. */
+	ldmia r0!, {r3-r11, r14}
 	msr control, r3
-	msr psp, r0						/* Restore the task stack pointer. */
+	/* Restore the task stack pointer. */
+	msr psp, r0
 	mov r0, #0
 	msr	basepri, r0
 	bx r14
-  
+
 /*-----------------------------------------------------------*/
 
 vPortEnableVFP:
@@ -170,25 +180,22 @@ vPortEnableVFP:
 	str r1, [r0]
 	bx	r14
 
-xPortRaisePrivilege:
-	mrs r0, control
-	tst r0, #1						/* Is the task running privileged? */
-	itte ne
-	movne r0, #0					/* CONTROL[0]!=0, return false. */
-	svcne 2                                  	/* Switch to privileged. */
-	moveq r0, #1					/* CONTROL[0]==0, return true. */
-	bx lr
-        
 /*-----------------------------------------------------------*/
 
+xIsPrivileged:
+	mrs r0, control		/* r0 = CONTROL. */
+	tst r0, #1			/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	ite ne
+	movne r0, #0		/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	moveq r0, #1		/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	bx lr				/* Return. */
+/*-----------------------------------------------------------*/
 
-
-vPortSwitchToUserMode:
-	
-	mrs r0, control
-	orr r0, r0, #1
-	msr control, r0
-	bx r14
+vResetPrivilege:
+	mrs r0, control		/* r0 = CONTROL. */
+	orr r0, r0, #1		/* r0 = r0 | 1. */
+	msr control, r0		/* CONTROL = r0. */
+	bx lr				/* Return to the caller. */
+/*-----------------------------------------------------------*/
 
 	END
-
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7_MPU/r0p1/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7_MPU/r0p1/portmacro.h
index 43d4e4502..315e47c95 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7_MPU/r0p1/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM7_MPU/r0p1/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -42,6 +42,9 @@ extern "C" {
  *-----------------------------------------------------------
  */
 
+/* IAR includes. */
+#include 
+
 /* Type definitions. */
 #define portCHAR		char
 #define portFLOAT		float
@@ -66,8 +69,8 @@ typedef unsigned long UBaseType_t;
 	not need to be guarded with a critical section. */
 	#define portTICK_TYPE_IS_ATOMIC 1
 #endif
-
 /*-----------------------------------------------------------*/
+
 /* MPU specific constants. */
 #define portUSING_MPU_WRAPPERS		1
 #define portPRIVILEGE_BIT			( 0x80000000UL )
@@ -79,18 +82,17 @@ typedef unsigned long UBaseType_t;
 #define portMPU_REGION_CACHEABLE_BUFFERABLE		( 0x07UL << 16UL )
 #define portMPU_REGION_EXECUTE_NEVER			( 0x01UL << 28UL )
 
-#define portUNPRIVILEGED_FLASH_REGION		( 0UL )
-#define portPRIVILEGED_FLASH_REGION			( 1UL )
-#define portPRIVILEGED_RAM_REGION			( 2UL )
-#define portGENERAL_PERIPHERALS_REGION		( 3UL )
-#define portSTACK_REGION					( 4UL )
-#define portFIRST_CONFIGURABLE_REGION	    ( 5UL )
-#define portLAST_CONFIGURABLE_REGION		( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS		( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS				( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portUNPRIVILEGED_FLASH_REGION			( 0UL )
+#define portPRIVILEGED_FLASH_REGION				( 1UL )
+#define portPRIVILEGED_RAM_REGION				( 2UL )
+#define portGENERAL_PERIPHERALS_REGION			( 3UL )
+#define portSTACK_REGION						( 4UL )
+#define portFIRST_CONFIGURABLE_REGION			( 5UL )
+#define portLAST_CONFIGURABLE_REGION			( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS			( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS					( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
 
-void vPortSwitchToUserMode( void );
-#define portSWITCH_TO_USER_MODE()	vPortSwitchToUserMode()
+#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" )
 
 typedef struct MPU_REGION_REGISTERS
 {
@@ -105,20 +107,20 @@ typedef struct MPU_SETTINGS
 } xMPU_SETTINGS;
 
 
-
 /* Architecture specifics. */
 #define portSTACK_GROWTH			( -1 )
 #define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 #define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
 
 /* SVC numbers for various services. */
 #define portSVC_START_SCHEDULER				0
 #define portSVC_YIELD						1
 #define portSVC_RAISE_PRIVILEGE				2
-/*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
-#define portYIELD()											\
+#define portYIELD()				__asm volatile ( "	SVC	%0	\n" :: "i" (portSVC_YIELD) : "memory" )
+#define portYIELD_WITHIN_API()								\
 {															\
 	/* Set a PendSV to request a context switch. */			\
 	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;			\
@@ -126,11 +128,9 @@ typedef struct MPU_SETTINGS
 	__ISB();												\
 }
 
-
-
 #define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API()
 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
 
 /*-----------------------------------------------------------*/
@@ -140,7 +140,7 @@ typedef struct MPU_SETTINGS
 	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
 #endif
 
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
 	/* Check the configuration. */
 	#if( configMAX_PRIORITIES > 32 )
@@ -153,7 +153,6 @@ typedef struct MPU_SETTINGS
 
 	/*-----------------------------------------------------------*/
 
-	#include 
 	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
@@ -165,12 +164,11 @@ extern void vPortExitCritical( void );
 
 #define portDISABLE_INTERRUPTS()							\
 {															\
-	 /* Errata work around. */								\
-	__disable_interrupt();									\
+    __disable_interrupt();                                  \
 	__set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY );	\
 	__DSB();												\
 	__ISB();												\
-	__enable_interrupt();									\
+    __enable_interrupt();                                   \
 }
 
 #define portENABLE_INTERRUPTS()					__set_BASEPRI( 0 )
@@ -180,14 +178,6 @@ extern void vPortExitCritical( void );
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	__set_BASEPRI( x )
 /*-----------------------------------------------------------*/
 
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-
-/*-----------------------------------------------------------*/
-
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
 not necessary for to use this port.  They are defined so the common demo files
 (which build with all the ports) will build. */
@@ -200,9 +190,30 @@ not necessary for to use this port.  They are defined so the common demo files
 	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
 #endif
 
-void vSVCHandler( uint32_t *pulParam );
-void vPortResetPrivilege( BaseType_t xRunningPrivileged );
+/* portNOP() is not required by this port. */
+#define portNOP()
+/*-----------------------------------------------------------*/
 
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED()			xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+*/
+#define portRAISE_PRIVILEGE()		__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE()		vResetPrivilege()
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_1.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_1.c
index 7ff6dfab2..542317dc1 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_1.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_1.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -52,7 +52,6 @@ task.h is included from an application file. */
 /* A few bytes might be lost to byte aligning the heap start address. */
 #define configADJUSTED_HEAP_SIZE	( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
 
-/* Allocate the memory for the heap. */
 /* Allocate the memory for the heap. */
 #if( configAPPLICATION_ALLOCATED_HEAP == 1 )
 	/* The application writer has already defined the array used for the RTOS
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_2.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_2.c
index 941b4f222..7d0692129 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_2.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_2.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_3.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_3.c
index c8c3f542f..e6a299087 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_3.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_3.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
index 02251c094..d7cd8a5b4 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_5.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_5.c
index 51c53a94c..b52d61cc2 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_5.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_5.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM0/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM0/port.c
index 6e1ce5fde..33bf3eb44 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM0/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM0/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -193,7 +193,7 @@ __asm void prvPortStartFirstTask( void )
  */
 BaseType_t xPortStartScheduler( void )
 {
-	/* Make PendSV, CallSV and SysTick the same priroity as the kernel. */
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
 	*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
 	*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
 
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM0/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM0/portmacro.h
index 4f9f7a5c2..9843778ba 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM0/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM0/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c
index fab5a4d89..9d5755b93 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h
index a2bf018f3..65cd27ed9 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
index 4292826ca..a7658c32b 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
index a2bf018f3..65cd27ed9 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/port.c
index 621bc063e..79557fe22 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -129,13 +129,6 @@ static void prvStartFirstTask( void ) PRIVILEGED_FUNCTION;
  */
 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
 
-/*
- * Checks to see if being called from the context of an unprivileged task, and
- * if so raises the privilege level and returns false - otherwise does nothing
- * other than return true.
- */
-BaseType_t xPortRaisePrivilege( void );
-
 /*
  * Standard FreeRTOS exception handlers.
  */
@@ -175,6 +168,35 @@ static uint32_t prvPortGetIPSR( void );
 	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 #endif /* configASSERT_DEFINED */
 
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void );
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
 /*-----------------------------------------------------------*/
 
 /*
@@ -651,15 +673,27 @@ uint32_t ulRegionSize, ulReturnValue = 4;
 }
 /*-----------------------------------------------------------*/
 
-__asm BaseType_t xPortRaisePrivilege( void )
+__asm BaseType_t xIsPrivileged( void )
 {
-	mrs r0, control
-	tst r0, #1						/* Is the task running privileged? */
-	itte ne
-	movne r0, #0					/* CONTROL[0]!=0, return false. */
-	svcne portSVC_RAISE_PRIVILEGE	/* Switch to privileged. */
-	moveq r0, #1					/* CONTROL[0]==0, return true. */
-	bx lr
+	PRESERVE8
+
+	mrs r0, control		/* r0 = CONTROL. */
+	tst r0, #1			/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	ite ne
+	movne r0, #0		/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	moveq r0, #1		/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	bx lr				/* Return. */
+}
+/*-----------------------------------------------------------*/
+
+__asm void vResetPrivilege( void )
+{
+	PRESERVE8
+
+	mrs r0, control		/* r0 = CONTROL. */
+	orrs r0, #1			/* r0 = r0 | 1. */
+	msr control, r0		/* CONTROL = r0. */
+	bx lr				/* Return. */
 }
 /*-----------------------------------------------------------*/
 
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
index 8e1ad96b5..9a37600d7 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -85,7 +85,7 @@ typedef unsigned long UBaseType_t;
 #define portPRIVILEGED_RAM_REGION			( 2UL )
 #define portGENERAL_PERIPHERALS_REGION		( 3UL )
 #define portSTACK_REGION					( 4UL )
-#define portFIRST_CONFIGURABLE_REGION	    ( 5UL )
+#define portFIRST_CONFIGURABLE_REGION		( 5UL )
 #define portLAST_CONFIGURABLE_REGION		( 7UL )
 #define portNUM_CONFIGURABLE_REGIONS		( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
 #define portTOTAL_NUM_REGIONS				( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
@@ -197,7 +197,28 @@ not necessary for to use this port.  They are defined so the common demo files
 #ifndef portFORCE_INLINE
 	#define portFORCE_INLINE __forceinline
 #endif
+/*-----------------------------------------------------------*/
+
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED()			xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ */
+#define portRAISE_PRIVILEGE()		__asm { svc portSVC_RAISE_PRIVILEGE }
 
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE()		vResetPrivilege()
 /*-----------------------------------------------------------*/
 
 static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
@@ -280,24 +301,6 @@ BaseType_t xReturn;
 }
 /*-----------------------------------------------------------*/
 
-/* Set the privilege level to user mode if xRunningPrivileged is false. */
-portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged )
-{
-uint32_t ulReg;
-
-	if( xRunningPrivileged != pdTRUE )
-	{
-		__asm
-		{
-			mrs ulReg, control
-			orr ulReg, #1
-			msr control, ulReg
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/port.c
index f5e348f23..f430e8eea 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h
index 75934ecc9..700475630 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM7_MPU/r0p1/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM7_MPU/r0p1/port.c
index dba729c6b..f0982ca77 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM7_MPU/r0p1/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM7_MPU/r0p1/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -52,6 +52,24 @@ task.h is included from an application file. */
 #define portNVIC_SYSPRI1_REG					( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
 #define portNVIC_SYS_CTRL_STATE_REG				( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portNVIC_MEM_FAULT_ENABLE				( 1UL << 16UL )
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )
+#define portMISSED_COUNTS_FACTOR    ( 45UL )
 
 /* Constants required to access and manipulate the MPU. */
 #define portMPU_TYPE_REG						( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
@@ -71,7 +89,6 @@ task.h is included from an application file. */
 #define portNVIC_SYSTICK_CLK					( 0x00000004UL )
 #define portNVIC_SYSTICK_INT					( 0x00000002UL )
 #define portNVIC_SYSTICK_ENABLE					( 0x00000001UL )
-#define portNVIC_SYSTICK_COUNT_FLAG		( 1UL << 16UL )
 #define portNVIC_PENDSV_PRI						( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
 #define portNVIC_SYSTICK_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
 #define portNVIC_SVC_PRI						( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
@@ -82,7 +99,7 @@ task.h is included from an application file. */
 
 /* Constants required to set up the initial stack. */
 #define portINITIAL_XPSR						( 0x01000000UL )
-#define portINITIAL_EXEC_RETURN					( 0xfffffffdUL )
+#define portINITIAL_EXC_RETURN					( 0xfffffffdUL )
 #define portINITIAL_CONTROL_IF_UNPRIVILEGED		( 0x03 )
 #define portINITIAL_CONTROL_IF_PRIVILEGED		( 0x02 )
 
@@ -99,14 +116,6 @@ task.h is included from an application file. */
 /* Offsets in the stack to the parameters when inside the SVC handler. */
 #define portOFFSET_TO_PC						( 6 )
 
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER		( 0xffffffUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
-occurred while the SysTick counter is stopped during tickless idle
-calculations. */
-#define portMISSED_COUNTS_FACTOR	( 45UL )
-
 /* For strict compliance with the Cortex-M spec the task start address should
 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
 #define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
@@ -116,12 +125,30 @@ variable.  Note this is not saved as part of the task context as context
 switches can only occur when uxCriticalNesting is zero. */
 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
 
+#if( configUSE_TICKLESS_IDLE == 1 )
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+	static uint32_t ulTimerCountsForOneTick = 0;
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+
 /*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
+ * Setup the timer to generate the tick interrupts.
  */
-void vPortSetupTimerInterrupt( void );
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
 
 /*
  * Configure a number of standard MPU regions that are used by all tasks.
@@ -140,13 +167,6 @@ static void prvStartFirstTask( void ) PRIVILEGED_FUNCTION;
  */
 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
 
-/*
- * Checks to see if being called from the context of an unprivileged task, and
- * if so raises the privilege level and returns false - otherwise does nothing
- * other than return true.
- */
-BaseType_t xPortRaisePrivilege( void );
-
 /*
  * Standard FreeRTOS exception handlers.
  */
@@ -175,29 +195,6 @@ static void vPortEnableVFP( void );
  */
 static uint32_t prvPortGetIPSR( void );
 
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if configUSE_TICKLESS_IDLE == 1
-	static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if configUSE_TICKLESS_IDLE == 1
-	static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if configUSE_TICKLESS_IDLE == 1
-	static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-	
 /*
  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
  * FreeRTOS API functions are not called from interrupts that have been assigned
@@ -209,6 +206,35 @@ static uint32_t prvPortGetIPSR( void );
 	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 #endif /* configASSERT_DEFINED */
 
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void );
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
 /*-----------------------------------------------------------*/
 
 /*
@@ -230,7 +256,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 	/* A save method is being used that requires each task to maintain its
 	own exec return value. */
 	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_EXEC_RETURN;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
 
 	pxTopOfStack -= 9;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
 
@@ -371,6 +397,24 @@ BaseType_t xPortStartScheduler( void )
 			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
 		}
 
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
 		/* Shift the priority group value back to its position within the AIRCR
 		register. */
 		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
@@ -393,7 +437,7 @@ BaseType_t xPortStartScheduler( void )
 
 	/* Start the timer that generates the tick ISR.  Interrupts are disabled
 	here already. */
-	vPortSetupTimerInterrupt();
+	prvSetupTimerInterrupt();
 
 	/* Initialise the critical nesting count ready for the first task. */
 	uxCriticalNesting = 0;
@@ -415,12 +459,21 @@ BaseType_t xPortStartScheduler( void )
 __asm void prvStartFirstTask( void )
 {
 	PRESERVE8
-	
-	ldr r0, =0xE000ED08	/* Use the NVIC offset register to locate the stack. */
+
+	/* Use the NVIC offset register to locate the stack. */
+	ldr r0, =0xE000ED08
 	ldr r0, [r0]
 	ldr r0, [r0]
-	msr msp, r0			/* Set the msp back to the start of the stack. */
-	cpsie i				/* Globally enable interrupts. */
+	/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	/* Clear the bit that indicates the FPU is in use in case the FPU was used
+	before the scheduler was started - which would otherwise result in the
+	unnecessary leaving of space in the SVC stack for lazy saving of FPU
+	registers. */
+	mov r0, #0
+	msr control, r0
+	/* Globally enable interrupts. */
+	cpsie i
 	cpsie f
 	dsb
 	isb
@@ -472,8 +525,8 @@ __asm void xPortPendSVHandler( void )
 
 	mrs r0, psp
 
-	ldr	r3, =pxCurrentTCB			/* Get the location of the current TCB. */
-	ldr	r2, [r3]
+	ldr r3, =pxCurrentTCB			/* Get the location of the current TCB. */
+	ldr r2, [r3]
 
 	tst r14, #0x10					/* Is the task using the FPU context?  If so, push high vfp registers. */
 	it eq
@@ -483,9 +536,8 @@ __asm void xPortPendSVHandler( void )
 	stmdb r0!, {r1, r4-r11, r14}	/* Save the remaining registers. */
 	str r0, [r2]					/* Save the new top of stack into the first member of the TCB. */
 
-	stmdb sp!, {r3}
+	stmdb sp!, {r0, r3}
 	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-  cpsid i
 	msr basepri, r0
 	dsb
 	isb
@@ -493,7 +545,7 @@ __asm void xPortPendSVHandler( void )
 	bl vTaskSwitchContext
 	mov r0, #0
 	msr basepri, r0
-	ldmia sp!, {r3}
+	ldmia sp!, {r0, r3}
 									/* Restore the context. */
 	ldr r1, [r3]
 	ldr r0, [r1]					/* The first item in the TCB is the task top of stack. */
@@ -511,29 +563,16 @@ __asm void xPortPendSVHandler( void )
 	msr psp, r0
 	bx r14
 	nop
+	nop
 }
+
 /*-----------------------------------------------------------*/
 
-void xPortSysTickHandler( void )
-{
-uint32_t ulDummy;
+#if( configUSE_TICKLESS_IDLE == 1 )
 
-	ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
-}
-/*-----------------------------------------------------------*/
-#if configUSE_TICKLESS_IDLE == 1
 	__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
 	{
-	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
 	TickType_t xModifiableIdleTime;
 
 		/* Make sure the SysTick reload value does not overflow the counter. */
@@ -546,7 +585,7 @@ uint32_t ulDummy;
 		is accounted for as best it can be, but using the tickless mode will
 		inevitably result in some tiny drift of the time maintained by the
 		kernel with respect to calendar time. */
-		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE;
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
 
 		/* Calculate the reload value required to wait xExpectedIdleTime
 		tick periods.  -1 is used because this code will execute part way
@@ -572,7 +611,7 @@ uint32_t ulDummy;
 			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
 
 			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
 
 			/* Reset the reload register to the value required for normal tick
 			periods. */
@@ -592,7 +631,7 @@ uint32_t ulDummy;
 			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
 			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
 
 			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
 			set its parameter to 0 to indicate that its implementation contains
@@ -609,23 +648,41 @@ uint32_t ulDummy;
 			}
 			configPOST_SLEEP_PROCESSING( &xExpectedIdleTime );
 
-			/* Stop SysTick.  Again, the time the SysTick is stopped for is
-			accounted for as best it can be, but using the tickless mode will
-			inevitably result in some tiny drift of the time maintained by the
-			kernel with respect to calendar time. */
-			ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
-			portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE );
-
-			/* Re-enable interrupts - see comments above __disable_irq() call
-			above. */
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
 			__enable_irq();
-
-			if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG ) != 0 )
+			__dsb( portSY_FULL_READ_WRITE );
+			__isb( portSY_FULL_READ_WRITE );
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__disable_irq();
+			__dsb( portSY_FULL_READ_WRITE );
+			__isb( portSY_FULL_READ_WRITE );
+
+			/* Disable the SysTick clock without reading the
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+			the time the SysTick is stopped for is accounted for as best it can
+			be, but using the tickless mode will inevitably result in some tiny
+			drift of the time maintained by the kernel with respect to calendar
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
 			{
 				uint32_t ulCalculatedLoadValue;
 
-				/* The tick interrupt has already executed, and the SysTick
-				count reloaded with ulReloadValue.  Reset the
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
 				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
 				period. */
 				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
@@ -640,11 +697,9 @@ uint32_t ulDummy;
 
 				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
 
-				/* The tick interrupt handler will already have pended the tick
-				processing in the kernel.  As the pending tick will be
-				processed as soon as this function exits, the tick value
-				maintained by the tick is stepped forward by one less than the
-				time spent waiting. */
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
 				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
 			}
 			else
@@ -666,63 +721,75 @@ uint32_t ulDummy;
 
 			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
 			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
-			value.  The critical section is used to ensure the tick interrupt
-			can only execute once in the case that the reload register is near
-			zero. */
+			value. */
 			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-			portENTER_CRITICAL();
-			{
-				portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE;
-				vTaskStepTick( ulCompleteTickPeriods );
-				portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-			}
-			portEXIT_CRITICAL();
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrpts enabled. */
+			__enable_irq();
 		}
 	}
 
 #endif /* #if configUSE_TICKLESS_IDLE */
 
+void xPortSysTickHandler( void )
+{
+uint32_t ulDummy;
+
+	ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
 /*-----------------------------------------------------------*/
 
 /*
  * Setup the systick timer to generate the tick interrupts at the required
  * frequency.
  */
-#if configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0
+static void prvSetupTimerInterrupt( void )
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+#if( configUSE_TICKLESS_IDLE == 1 )
+    ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+    xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+    ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+#endif /* configUSE_TICKLESS_IDLE */
 
-	void vPortSetupTimerInterrupt( void )
-	{
-		/* Calculate the constants required to configure the tick interrupt. */
-		#if configUSE_TICKLESS_IDLE == 1
-		{
-			ulTimerCountsForOneTick = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
-			xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-			ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
-		}
-		#endif /* configUSE_TICKLESS_IDLE */
-		/* Configure SysTick to interrupt at the requested rate. */
-		portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-		portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-	}
-#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
 
+	/* Reset the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
 /*-----------------------------------------------------------*/
 
 __asm void vPortSwitchToUserMode( void )
 {
 	PRESERVE8
-	
+
 	mrs r0, control
 	orr r0, #1
 	msr control, r0
 	bx r14
 }
 /*-----------------------------------------------------------*/
-	
+
 __asm void vPortEnableVFP( void )
 {
 	PRESERVE8
-	
+
 	ldr.w r0, =0xE000ED88		/* The FPU enable bits are in the CPACR. */
 	ldr r1, [r0]
 
@@ -742,6 +809,9 @@ extern uint32_t __FLASH_segment_end__;
 extern uint32_t __privileged_data_start__;
 extern uint32_t __privileged_data_end__;
 
+	/* Check the expected MPU is present. */
+	if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+	{
 		/* First setup the entire flash for unprivileged read only access. */
 		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
 											( portMPU_REGION_VALID ) |
@@ -790,6 +860,7 @@ extern uint32_t __privileged_data_end__;
 
 		/* Enable the MPU with the background region configured. */
 		portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+	}
 }
 /*-----------------------------------------------------------*/
 
@@ -817,15 +888,27 @@ uint32_t ulRegionSize, ulReturnValue = 4;
 }
 /*-----------------------------------------------------------*/
 
-__asm BaseType_t xPortRaisePrivilege( void )
+__asm BaseType_t xIsPrivileged( void )
 {
-	mrs r0, control
-	tst r0, #1						/* Is the task running privileged? */
-	itte ne
-	movne r0, #0					/* CONTROL[0]!=0, return false. */
-	svcne portSVC_RAISE_PRIVILEGE	/* Switch to privileged. */
-	moveq r0, #1					/* CONTROL[0]==0, return true. */
-	bx lr
+	PRESERVE8
+
+	mrs r0, control		/* r0 = CONTROL. */
+	tst r0, #1			/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	ite ne
+	movne r0, #0		/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	moveq r0, #1		/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	bx lr				/* Return. */
+}
+/*-----------------------------------------------------------*/
+
+__asm void vResetPrivilege( void )
+{
+	PRESERVE8
+
+	mrs r0, control		/* r0 = CONTROL. */
+	orrs r0, #1			/* r0 = r0 | 1. */
+	msr control, r0		/* CONTROL = r0. */
+	bx lr				/* Return. */
 }
 /*-----------------------------------------------------------*/
 
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM7_MPU/r0p1/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM7_MPU/r0p1/portmacro.h
index 4957d43b8..3db6c162b 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM7_MPU/r0p1/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM7_MPU/r0p1/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -85,7 +85,7 @@ typedef unsigned long UBaseType_t;
 #define portPRIVILEGED_RAM_REGION			( 2UL )
 #define portGENERAL_PERIPHERALS_REGION		( 3UL )
 #define portSTACK_REGION					( 4UL )
-#define portFIRST_CONFIGURABLE_REGION	    ( 5UL )
+#define portFIRST_CONFIGURABLE_REGION		( 5UL )
 #define portLAST_CONFIGURABLE_REGION		( 7UL )
 #define portNUM_CONFIGURABLE_REGIONS		( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
 #define portTOTAL_NUM_REGIONS				( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
@@ -197,7 +197,28 @@ not necessary for to use this port.  They are defined so the common demo files
 #ifndef portFORCE_INLINE
 	#define portFORCE_INLINE __forceinline
 #endif
+/*-----------------------------------------------------------*/
+
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED()			xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ */
+#define portRAISE_PRIVILEGE()		__asm { svc portSVC_RAISE_PRIVILEGE }
 
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE()		vResetPrivilege()
 /*-----------------------------------------------------------*/
 
 static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
@@ -233,7 +254,7 @@ static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
 	__asm
 	{
 		/* Set BASEPRI to 0 so no interrupts are masked.  This function is only
-		used to lower the mask in an interrupt, so memory barriers are not 
+		used to lower the mask in an interrupt, so memory barriers are not
 		used. */
 		msr basepri, #0
 	}
@@ -284,24 +305,6 @@ BaseType_t xReturn;
 }
 /*-----------------------------------------------------------*/
 
-/* Set the privilege level to user mode if xRunningPrivileged is false. */
-portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged )
-{
-uint32_t ulReg;
-	
-	if( xRunningPrivileged != pdTRUE ) 
-	{
-		__asm 
-		{
-			mrs ulReg, control
-			orr ulReg, #1
-			msr control, ulReg
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c
index bb1274701..af77fe3fd 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port_asm.asm b/Middlewares/Third_Party/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port_asm.asm
index 2b4f707bc..22928def4 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port_asm.asm
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port_asm.asm
@@ -1,6 +1,6 @@
 ;/*
-; * FreeRTOS Kernel V10.0.1
-; * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * FreeRTOS Kernel V10.2.0
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 ; *
 ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
 ; * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h
index a8c567084..e3f3c2c5b 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/queue.c b/Middlewares/Third_Party/FreeRTOS/Source/queue.c
index 0730950e9..d882bf670 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/queue.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/queue.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -41,11 +41,11 @@ task.h is included from an application file. */
 	#include "croutine.h"
 #endif
 
-/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
-MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
-header files above, but not in this file, in order to generate the correct
-privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
 
 
 /* Constants used with the cRxLock and cTxLock structure members. */
@@ -56,17 +56,26 @@ privileged Vs unprivileged linkage and placement. */
 pcTail members are used as pointers into the queue storage area.  When the
 Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
 not necessary, and the pcHead pointer is set to NULL to indicate that the
-pcTail pointer actually points to the mutex holder (if any).  Map alternative
-names to the pcHead and pcTail structure members to ensure the readability of
-the code is maintained despite this dual use of two structure members.  An
-alternative implementation would be to use a union, but use of a union is
-against the coding standard (although an exception to the standard has been
-permitted where the dual use also significantly changes the type of the
-structure member). */
-#define pxMutexHolder					pcTail
+structure instead holds a pointer to the mutex holder (if any).  Map alternative
+names to the pcHead and structure member to ensure the readability of the code
+is maintained.  The QueuePointers_t and SemaphoreData_t types are used to form
+a union as their usage is mutually exclusive dependent on what the queue is
+being used for. */
 #define uxQueueType						pcHead
 #define queueQUEUE_IS_MUTEX				NULL
 
+typedef struct QueuePointers
+{
+	int8_t *pcTail;					/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
+	int8_t *pcReadFrom;				/*< Points to the last place that a queued item was read from when the structure is used as a queue. */
+} QueuePointers_t;
+
+typedef struct SemaphoreData
+{
+	TaskHandle_t xMutexHolder;		 /*< The handle of the task that holds the mutex. */
+	UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+} SemaphoreData_t;
+
 /* Semaphores do not actually store or copy data, so have an item size of
 zero. */
 #define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
@@ -83,18 +92,17 @@ zero. */
 /*
  * Definition of the queue used by the scheduler.
  * Items are queued by copy, not reference.  See the following link for the
- * rationale: http://www.freertos.org/Embedded-RTOS-Queues.html
+ * rationale: https://www.freertos.org/Embedded-RTOS-Queues.html
  */
-typedef struct QueueDefinition
+typedef struct QueueDefinition 		/* The old naming convention is used to prevent breaking kernel aware debuggers. */
 {
 	int8_t *pcHead;					/*< Points to the beginning of the queue storage area. */
-	int8_t *pcTail;					/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
 	int8_t *pcWriteTo;				/*< Points to the free next place in the storage area. */
 
-	union							/* Use of a union is an exception to the coding standard to ensure two mutually exclusive structure members don't appear simultaneously (wasting RAM). */
+	union
 	{
-		int8_t *pcReadFrom;			/*< Points to the last place that a queued item was read from when the structure is used as a queue. */
-		UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+		QueuePointers_t xQueue;		/*< Data required exclusively when this structure is used as a queue. */
+		SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */
 	} u;
 
 	List_t xTasksWaitingToSend;		/*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
@@ -246,16 +254,16 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 
 BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
 {
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
 
 	configASSERT( pxQueue );
 
 	taskENTER_CRITICAL();
 	{
-		pxQueue->pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize );
+		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
 		pxQueue->pcWriteTo = pxQueue->pcHead;
-		pxQueue->u.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - ( UBaseType_t ) 1U ) * pxQueue->uxItemSize );
+		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 		pxQueue->cRxLock = queueUNLOCKED;
 		pxQueue->cTxLock = queueUNLOCKED;
 
@@ -321,13 +329,14 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 			the real queue and semaphore structures. */
 			volatile size_t xSize = sizeof( StaticQueue_t );
 			configASSERT( xSize == sizeof( Queue_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
 		}
 		#endif /* configASSERT_DEFINED */
 
 		/* The address of a statically allocated queue was passed in, use it.
 		The address of a statically allocated storage area was also passed in
 		but is already set. */
-		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
 
 		if( pxNewQueue != NULL )
 		{
@@ -345,6 +354,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 		else
 		{
 			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
 		}
 
 		return pxNewQueue;
@@ -375,13 +385,23 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 			xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 		}
 
-		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes );
+		/* Allocate the queue and storage area.  Justification for MISRA
+		deviation as follows:  pvPortMalloc() always ensures returned memory
+		blocks are aligned per the requirements of the MCU stack.  In this case
+		pvPortMalloc() must return a pointer that is guaranteed to meet the
+		alignment requirements of the Queue_t structure - which in this case
+		is an int8_t *.  Therefore, whenever the stack alignment requirements
+		are greater than or equal to the pointer to char requirements the cast
+		is safe.  In other cases alignment requirements are not strict (one or
+		two bytes). */
+		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
 
 		if( pxNewQueue != NULL )
 		{
 			/* Jump past the queue structure to find the location of the queue
 			storage area. */
-			pucQueueStorage = ( ( uint8_t * ) pxNewQueue ) + sizeof( Queue_t );
+			pucQueueStorage = ( uint8_t * ) pxNewQueue;
+			pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 
 			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
 			{
@@ -397,6 +417,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 		else
 		{
 			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
 		}
 
 		return pxNewQueue;
@@ -457,11 +478,11 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 			correctly for a generic queue, but this function is creating a
 			mutex.  Overwrite those members that need to be set differently -
 			in particular the information required for priority inheritance. */
-			pxNewQueue->pxMutexHolder = NULL;
+			pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
 			pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
 
 			/* In case this is a recursive mutex. */
-			pxNewQueue->u.uxRecursiveCallCount = 0;
+			pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
 
 			traceCREATE_MUTEX( pxNewQueue );
 
@@ -481,13 +502,13 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 
 	QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
 	{
-	Queue_t *pxNewQueue;
+	QueueHandle_t xNewQueue;
 	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
 
-		pxNewQueue = ( Queue_t * ) xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
-		prvInitialiseMutex( pxNewQueue );
+		xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
 
-		return pxNewQueue;
+		return xNewQueue;
 	}
 
 #endif /* configUSE_MUTEXES */
@@ -497,17 +518,17 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 
 	QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
 	{
-	Queue_t *pxNewQueue;
+	QueueHandle_t xNewQueue;
 	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
 
 		/* Prevent compiler warnings about unused parameters if
 		configUSE_TRACE_FACILITY does not equal 1. */
 		( void ) ucQueueType;
 
-		pxNewQueue = ( Queue_t * ) xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
-		prvInitialiseMutex( pxNewQueue );
+		xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
 
-		return pxNewQueue;
+		return xNewQueue;
 	}
 
 #endif /* configUSE_MUTEXES */
@@ -515,9 +536,10 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 
 #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-	void* xQueueGetMutexHolder( QueueHandle_t xSemaphore )
+	TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )
 	{
-	void *pxReturn;
+	TaskHandle_t pxReturn;
+	Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
 
 		/* This function is called by xSemaphoreGetMutexHolder(), and should not
 		be called directly.  Note:  This is a good way of determining if the
@@ -526,9 +548,9 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 		following critical section exiting and the function returning. */
 		taskENTER_CRITICAL();
 		{
-			if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+			if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )
 			{
-				pxReturn = ( void * ) ( ( Queue_t * ) xSemaphore )->pxMutexHolder;
+				pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;
 			}
 			else
 			{
@@ -545,9 +567,9 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 
 #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-	void* xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
+	TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
 	{
-	void *pxReturn;
+	TaskHandle_t pxReturn;
 
 		configASSERT( xSemaphore );
 
@@ -556,7 +578,7 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 		not required here. */
 		if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
 		{
-			pxReturn = ( void * ) ( ( Queue_t * ) xSemaphore )->pxMutexHolder;
+			pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;
 		}
 		else
 		{
@@ -578,25 +600,25 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 
 		configASSERT( pxMutex );
 
-		/* If this is the task that holds the mutex then pxMutexHolder will not
+		/* If this is the task that holds the mutex then xMutexHolder will not
 		change outside of this task.  If this task does not hold the mutex then
 		pxMutexHolder can never coincidentally equal the tasks handle, and as
 		this is the only condition we are interested in it does not matter if
 		pxMutexHolder is accessed simultaneously by another task.  Therefore no
 		mutual exclusion is required to test the pxMutexHolder variable. */
-		if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Not a redundant cast as TaskHandle_t is a typedef. */
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
 		{
 			traceGIVE_MUTEX_RECURSIVE( pxMutex );
 
-			/* uxRecursiveCallCount cannot be zero if pxMutexHolder is equal to
+			/* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
 			the task handle, therefore no underflow check is required.  Also,
 			uxRecursiveCallCount is only modified by the mutex holder, and as
 			there can only be one, no mutual exclusion is required to modify the
 			uxRecursiveCallCount member. */
-			( pxMutex->u.uxRecursiveCallCount )--;
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
 
 			/* Has the recursive call count unwound to 0? */
-			if( pxMutex->u.uxRecursiveCallCount == ( UBaseType_t ) 0 )
+			if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
 			{
 				/* Return the mutex.  This will automatically unblock any other
 				task that might be waiting to access the mutex. */
@@ -638,9 +660,9 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 
 		traceTAKE_MUTEX_RECURSIVE( pxMutex );
 
-		if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
 		{
-			( pxMutex->u.uxRecursiveCallCount )++;
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
 			xReturn = pdPASS;
 		}
 		else
@@ -652,7 +674,7 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 			before reaching here. */
 			if( xReturn != pdFAIL )
 			{
-				( pxMutex->u.uxRecursiveCallCount )++;
+				( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
 			}
 			else
 			{
@@ -726,7 +748,7 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQ
 {
 BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
 TimeOut_t xTimeOut;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
 
 	configASSERT( pxQueue );
 	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
@@ -738,9 +760,9 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 	#endif
 
 
-	/* This function relaxes the coding standard somewhat to allow return
-	statements within the function itself.  This is done in the interest
-	of execution time efficiency. */
+	/*lint -save -e904 This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
 	for( ;; )
 	{
 		taskENTER_CRITICAL();
@@ -752,13 +774,23 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
 			{
 				traceQUEUE_SEND( pxQueue );
-				xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
 
 				#if ( configUSE_QUEUE_SETS == 1 )
 				{
+				UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
 					if( pxQueue->pxQueueSetContainer != NULL )
 					{
-						if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
+						if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+						{
+							/* Do not notify the queue set as an existing item
+							was overwritten in the queue so the number of items
+							in the queue has not changed. */
+							mtCOVERAGE_TEST_MARKER();
+						}
+						else if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
 						{
 							/* The queue is a member of a queue set, and posting
 							to the queue set caused a higher priority task to
@@ -805,6 +837,8 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 				}
 				#else /* configUSE_QUEUE_SETS */
 				{
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
 					/* If there was a task waiting for data to arrive on the
 					queue then unblock it now. */
 					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
@@ -916,7 +950,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 			traceQUEUE_SEND_FAILED( pxQueue );
 			return errQUEUE_FULL;
 		}
-	}
+	} /*lint -restore */
 }
 /*-----------------------------------------------------------*/
 
@@ -924,7 +958,7 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pv
 {
 BaseType_t xReturn;
 UBaseType_t uxSavedInterruptStatus;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
 
 	configASSERT( pxQueue );
 	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
@@ -1075,7 +1109,7 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherP
 {
 BaseType_t xReturn;
 UBaseType_t uxSavedInterruptStatus;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
 
 	/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
 	item size is 0.  Don't directly wake a task that was blocked on a queue
@@ -1092,7 +1126,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 	/* Normally a mutex would not be given from an interrupt, especially if
 	there is a mutex holder, as priority inheritance makes no sense for an
 	interrupts, only tasks. */
-	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->pxMutexHolder != NULL ) ) );
+	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
 
 	/* RTOS ports that support interrupt nesting have the concept of a maximum
 	system call (or maximum API call) interrupt priority.  Interrupts that are
@@ -1240,7 +1274,7 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_
 {
 BaseType_t xEntryTimeSet = pdFALSE;
 TimeOut_t xTimeOut;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
 
 	/* Check the pointer is not NULL. */
 	configASSERT( ( pxQueue ) );
@@ -1256,10 +1290,10 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 	}
 	#endif
 
-	/* This function relaxes the coding standard somewhat to allow return
-	statements within the function itself.  This is done in the interest
-	of execution time efficiency. */
 
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
 	for( ;; )
 	{
 		taskENTER_CRITICAL();
@@ -1373,7 +1407,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 				mtCOVERAGE_TEST_MARKER();
 			}
 		}
-	}
+	} /*lint -restore */
 }
 /*-----------------------------------------------------------*/
 
@@ -1381,7 +1415,7 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
 {
 BaseType_t xEntryTimeSet = pdFALSE;
 TimeOut_t xTimeOut;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
 
 #if( configUSE_MUTEXES == 1 )
 	BaseType_t xInheritanceOccurred = pdFALSE;
@@ -1402,10 +1436,9 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 	#endif
 
 
-	/* This function relaxes the coding standard somewhat to allow return
+	/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
 	statements within the function itself.  This is done in the interest
 	of execution time efficiency. */
-
 	for( ;; )
 	{
 		taskENTER_CRITICAL();
@@ -1430,7 +1463,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 					{
 						/* Record the information required to implement
 						priority inheritance should it become necessary. */
-						pxQueue->pxMutexHolder = ( int8_t * ) pvTaskIncrementMutexHeldCount(); /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */
+						pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
 					}
 					else
 					{
@@ -1518,7 +1551,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 					{
 						taskENTER_CRITICAL();
 						{
-							xInheritanceOccurred = xTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );
+							xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
 						}
 						taskEXIT_CRITICAL();
 					}
@@ -1577,7 +1610,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 							again, but only as low as the next highest priority
 							task that is waiting for the same mutex. */
 							uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
-							vTaskPriorityDisinheritAfterTimeout( ( void * ) pxQueue->pxMutexHolder, uxHighestWaitingPriority );
+							vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
 						}
 						taskEXIT_CRITICAL();
 					}
@@ -1592,7 +1625,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 				mtCOVERAGE_TEST_MARKER();
 			}
 		}
-	}
+	} /*lint -restore */
 }
 /*-----------------------------------------------------------*/
 
@@ -1601,7 +1634,7 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t x
 BaseType_t xEntryTimeSet = pdFALSE;
 TimeOut_t xTimeOut;
 int8_t *pcOriginalReadPosition;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
 
 	/* Check the pointer is not NULL. */
 	configASSERT( ( pxQueue ) );
@@ -1618,10 +1651,9 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 	#endif
 
 
-	/* This function relaxes the coding standard somewhat to allow return
-	statements within the function itself.  This is done in the interest
-	of execution time efficiency. */
-
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
 	for( ;; )
 	{
 		taskENTER_CRITICAL();
@@ -1635,13 +1667,13 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 				/* Remember the read position so it can be reset after the data
 				is read from the queue as this function is only peeking the
 				data, not removing it. */
-				pcOriginalReadPosition = pxQueue->u.pcReadFrom;
+				pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
 
 				prvCopyDataFromQueue( pxQueue, pvBuffer );
 				traceQUEUE_PEEK( pxQueue );
 
 				/* The data is not being removed, so reset the read pointer. */
-				pxQueue->u.pcReadFrom = pcOriginalReadPosition;
+				pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
 
 				/* The data is being left in the queue, so see if there are
 				any other tasks waiting for the data. */
@@ -1742,7 +1774,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 				mtCOVERAGE_TEST_MARKER();
 			}
 		}
-	}
+	} /*lint -restore */
 }
 /*-----------------------------------------------------------*/
 
@@ -1750,7 +1782,7 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, Ba
 {
 BaseType_t xReturn;
 UBaseType_t uxSavedInterruptStatus;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
 
 	configASSERT( pxQueue );
 	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
@@ -1842,7 +1874,7 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )
 BaseType_t xReturn;
 UBaseType_t uxSavedInterruptStatus;
 int8_t *pcOriginalReadPosition;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
 
 	configASSERT( pxQueue );
 	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
@@ -1873,9 +1905,9 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 
 			/* Remember the read position so it can be reset as nothing is
 			actually being removed from the queue. */
-			pcOriginalReadPosition = pxQueue->u.pcReadFrom;
+			pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
 			prvCopyDataFromQueue( pxQueue, pvBuffer );
-			pxQueue->u.pcReadFrom = pcOriginalReadPosition;
+			pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
 
 			xReturn = pdPASS;
 		}
@@ -1910,9 +1942,8 @@ UBaseType_t uxReturn;
 UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
 {
 UBaseType_t uxReturn;
-Queue_t *pxQueue;
+Queue_t * const pxQueue = xQueue;
 
-	pxQueue = ( Queue_t * ) xQueue;
 	configASSERT( pxQueue );
 
 	taskENTER_CRITICAL();
@@ -1928,10 +1959,10 @@ Queue_t *pxQueue;
 UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
 {
 UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
 
-	configASSERT( xQueue );
-
-	uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+	configASSERT( pxQueue );
+	uxReturn = pxQueue->uxMessagesWaiting;
 
 	return uxReturn;
 } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
@@ -1939,7 +1970,7 @@ UBaseType_t uxReturn;
 
 void vQueueDelete( QueueHandle_t xQueue )
 {
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
 
 	configASSERT( pxQueue );
 	traceQUEUE_DELETE( pxQueue );
@@ -2021,9 +2052,9 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 		other tasks that are waiting for the same mutex.  For this purpose,
 		return the priority of the highest priority task that is waiting for the
 		mutex. */
-		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0 )
+		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
 		{
-			uxHighestPriorityOfWaitingTasks = configMAX_PRIORITIES - listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
+			uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
 		}
 		else
 		{
@@ -2052,8 +2083,8 @@ UBaseType_t uxMessagesWaiting;
 			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
 			{
 				/* The mutex is no longer being held. */
-				xReturn = xTaskPriorityDisinherit( ( void * ) pxQueue->pxMutexHolder );
-				pxQueue->pxMutexHolder = NULL;
+				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
+				pxQueue->u.xSemaphore.xMutexHolder = NULL;
 			}
 			else
 			{
@@ -2064,9 +2095,9 @@ UBaseType_t uxMessagesWaiting;
 	}
 	else if( xPosition == queueSEND_TO_BACK )
 	{
-		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. */
-		pxQueue->pcWriteTo += pxQueue->uxItemSize;
-		if( pxQueue->pcWriteTo >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
 		{
 			pxQueue->pcWriteTo = pxQueue->pcHead;
 		}
@@ -2077,11 +2108,11 @@ UBaseType_t uxMessagesWaiting;
 	}
 	else
 	{
-		( void ) memcpy( ( void * ) pxQueue->u.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-		pxQueue->u.pcReadFrom -= pxQueue->uxItemSize;
-		if( pxQueue->u.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
+		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
+		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
 		{
-			pxQueue->u.pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize );
+			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
 		}
 		else
 		{
@@ -2119,16 +2150,16 @@ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer
 {
 	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
 	{
-		pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
-		if( pxQueue->u.pcReadFrom >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
 		{
-			pxQueue->u.pcReadFrom = pxQueue->pcHead;
+			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
 		}
 		else
 		{
 			mtCOVERAGE_TEST_MARKER();
 		}
-		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. */
+		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
 	}
 }
 /*-----------------------------------------------------------*/
@@ -2277,9 +2308,10 @@ BaseType_t xReturn;
 BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
 {
 BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
 
-	configASSERT( xQueue );
-	if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( UBaseType_t ) 0 )
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
 	{
 		xReturn = pdTRUE;
 	}
@@ -2316,9 +2348,10 @@ BaseType_t xReturn;
 BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
 {
 BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
 
-	configASSERT( xQueue );
-	if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( ( Queue_t * ) xQueue )->uxLength )
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
 	{
 		xReturn = pdTRUE;
 	}
@@ -2336,7 +2369,7 @@ BaseType_t xReturn;
 	BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
 	{
 	BaseType_t xReturn;
-	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+	Queue_t * const pxQueue = xQueue;
 
 		/* If the queue is already full we may have to block.  A critical section
 		is required to prevent an interrupt removing something from the queue
@@ -2413,7 +2446,7 @@ BaseType_t xReturn;
 	BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
 	{
 	BaseType_t xReturn;
-	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+	Queue_t * const pxQueue = xQueue;
 
 		/* If the queue is already empty we may have to block.  A critical section
 		is required to prevent an interrupt adding something to the queue
@@ -2450,17 +2483,17 @@ BaseType_t xReturn;
 			if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
 			{
 				/* Data is available from the queue. */
-				pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
-				if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )
+				pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+				if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
 				{
-					pxQueue->u.pcReadFrom = pxQueue->pcHead;
+					pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
 				}
 				else
 				{
 					mtCOVERAGE_TEST_MARKER();
 				}
 				--( pxQueue->uxMessagesWaiting );
-				( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+				( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
 
 				xReturn = pdPASS;
 
@@ -2502,7 +2535,7 @@ BaseType_t xReturn;
 
 	BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
 	{
-	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+	Queue_t * const pxQueue = xQueue;
 
 		/* Cannot block within an ISR so if there is no space on the queue then
 		exit without doing anything. */
@@ -2551,24 +2584,24 @@ BaseType_t xReturn;
 	BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
 	{
 	BaseType_t xReturn;
-	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+	Queue_t * const pxQueue = xQueue;
 
 		/* We cannot block from an ISR, so check there is data available. If
 		not then just leave without doing anything. */
 		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
 		{
 			/* Copy the data from the queue. */
-			pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
-			if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )
+			pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+			if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
 			{
-				pxQueue->u.pcReadFrom = pxQueue->pcHead;
+				pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
 			}
 			else
 			{
 				mtCOVERAGE_TEST_MARKER();
 			}
 			--( pxQueue->uxMessagesWaiting );
-			( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+			( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
 
 			if( ( *pxCoRoutineWoken ) == pdFALSE )
 			{
@@ -2699,7 +2732,7 @@ BaseType_t xReturn;
 
 	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
 	{
-	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+	Queue_t * const pxQueue = xQueue;
 
 		/* This function should not be called by application code hence the
 		'Restricted' in its name.  It is not part of the public API.  It is
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/st_readme.txt b/Middlewares/Third_Party/FreeRTOS/Source/st_readme.txt
index 4f12c01aa..8f70aa98d 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/st_readme.txt
+++ b/Middlewares/Third_Party/FreeRTOS/Source/st_readme.txt
@@ -25,6 +25,37 @@
 
 =======
 
+### 13-December-2019 ###
+=========================
+  + Remove warnings thrown by EWARM for CM33/CM23 ports
+      - IAR/ARM_CM23/non_secure/portmacro.h
+      - IAR/ARM_CM23_NTZ/non_secure/portmacro.h
+      - IAR/ARM_CM33/non_secure/portmacro.h
+      - IAR/ARM_CM33_NTZ/non_secure/portmacro.h
+
+### 19-July-2019 ###
+=========================
+  + Fix runtime error in the  IAR/CM4_MPU port
+       - IAR/ARM_CM4_MPU/port.c
+
+### 12-July-2019 ###
+=========================
+  + FreeRTOS: Update against the FreeRTOS v10.2.1 release
+    - support for the CM33 and CM23 cores
+
+  + CMSIS_RTOS_V2: update against the latest CMSIS-FreeRTOS v10.2.0 release
+
+  + Add MPU support for the CM7/r0p1:
+       - GCC/ARM_CM7_MPU/r0p1/port.c
+       - GCC/ARM_CM7_MPU/r0p1/portmacro.h
+       - IAR/ARM_CM7_MPU/r0p1/port.c
+       - IAR/ARM_CM7_MPU/r0p1/portasm.s
+       - IAR/ARM_CM7_MPU/r0p1/portmacro.h
+       - RVDS/ARM_CM7_MPU/r0p1/port.c
+       - RVDS/ARM_CM7_MPU/r0p1/portmacro.h
+
+  + cmsis_os.c: Fix compile errors by using the correct TimerCallbackFunction_t type for timer creation
+
 ### 29-Mars-2019 ###
 =========================
   + cmsis_os.c : Fix bug in osPoolAlloc(): memory blocks can't be reused after being free'd
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c b/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
index c60045f69..85519707b 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -43,11 +43,11 @@ task.h is included from an application file. */
 	#error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
 #endif
 
-/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
-MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
-header files above, but not in this file, in order to generate the correct
-privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
 
 /* If the user has not provided application specific Rx notification macros,
 or #defined the notification macros away, them provide default implementations
@@ -129,7 +129,7 @@ that uses task notifications. */
 /*lint -restore (9026) */
 
 /* The number of bytes used to hold the length of a message in the buffer. */
-#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( size_t ) )
+#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
 
 /* Bits stored in the ucFlags field of the stream buffer. */
 #define sbFLAGS_IS_MESSAGE_BUFFER		( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
@@ -138,7 +138,7 @@ that uses task notifications. */
 /*-----------------------------------------------------------*/
 
 /* Structure that hold state information on the buffer. */
-typedef struct xSTREAM_BUFFER /*lint !e9058 Style convention uses tag. */
+typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */
 {
 	volatile size_t xTail;				/* Index to the next item to read within the buffer. */
 	volatile size_t xHead;				/* Index to the next item to write within the buffer. */
@@ -200,7 +200,7 @@ static size_t prvWriteMessageToBuffer(  StreamBuffer_t * const pxStreamBuffer,
 static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer,
 									  uint8_t *pucData,
 									  size_t xMaxCount,
-									  size_t xBytesAvailable ); PRIVILEGED_FUNCTION
+									  size_t xBytesAvailable ) PRIVILEGED_FUNCTION;
 
 /*
  * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
@@ -210,7 +210,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 										  uint8_t * const pucBuffer,
 										  size_t xBufferSizeBytes,
 										  size_t xTriggerLevelBytes,
-										  BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+										  uint8_t ucFlags ) PRIVILEGED_FUNCTION;
 
 /*-----------------------------------------------------------*/
 
@@ -219,19 +219,31 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 	StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )
 	{
 	uint8_t *pucAllocatedMemory;
+	uint8_t ucFlags;
 
 		/* In case the stream buffer is going to be used as a message buffer
 		(that is, it will hold discrete messages with a little meta data that
 		says how big the next message is) check the buffer will be large enough
 		to hold at least one message. */
-		configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+		if( xIsMessageBuffer == pdTRUE )
+		{
+			/* Is a message buffer but not statically allocated. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
+			configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+		}
+		else
+		{
+			/* Not a message buffer and not statically allocated. */
+			ucFlags = 0;
+			configASSERT( xBufferSizeBytes > 0 );
+		}
 		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
 
 		/* A trigger level of 0 would cause a waiting task to unblock even when
 		the buffer was empty. */
 		if( xTriggerLevelBytes == ( size_t ) 0 )
 		{
-			xTriggerLevelBytes = ( size_t ) 1; /*lint !e9044 Parameter modified to ensure it doesn't have a dangerous value. */
+			xTriggerLevelBytes = ( size_t ) 1;
 		}
 
 		/* A stream buffer requires a StreamBuffer_t structure and a buffer.
@@ -251,7 +263,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 										   pucAllocatedMemory + sizeof( StreamBuffer_t ),  /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
 										   xBufferSizeBytes,
 										   xTriggerLevelBytes,
-										   xIsMessageBuffer );
+										   ucFlags );
 
 			traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
 		}
@@ -260,7 +272,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 			traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
 		}
 
-		return ( StreamBufferHandle_t * ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
+		return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
 	}
 
 #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
@@ -276,6 +288,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 	{
 	StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
 	StreamBufferHandle_t xReturn;
+	uint8_t ucFlags;
 
 		configASSERT( pucStreamBufferStorageArea );
 		configASSERT( pxStaticStreamBuffer );
@@ -285,7 +298,18 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 		the buffer was empty. */
 		if( xTriggerLevelBytes == ( size_t ) 0 )
 		{
-			xTriggerLevelBytes = ( size_t ) 1; /*lint !e9044 Function parameter deliberately modified to ensure it is in range. */
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		if( xIsMessageBuffer != pdFALSE )
+		{
+			/* Statically allocated message buffer. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+		else
+		{
+			/* Statically allocated stream buffer. */
+			ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
 		}
 
 		/* In case the stream buffer is going to be used as a message buffer
@@ -301,7 +325,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 			message buffer structure. */
 			volatile size_t xSize = sizeof( StaticStreamBuffer_t );
 			configASSERT( xSize == sizeof( StreamBuffer_t ) );
-		}
+		} /*lint !e529 xSize is referenced is configASSERT() is defined. */
 		#endif /* configASSERT_DEFINED */
 
 		if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
@@ -310,7 +334,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 										  pucStreamBufferStorageArea,
 										  xBufferSizeBytes,
 										  xTriggerLevelBytes,
-										  xIsMessageBuffer );
+										  ucFlags );
 
 			/* Remember this was statically allocated in case it is ever deleted
 			again. */
@@ -334,7 +358,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 
 void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
 {
-StreamBuffer_t * pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
 
 	configASSERT( pxStreamBuffer );
 
@@ -360,15 +384,15 @@ StreamBuffer_t * pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9
 	{
 		/* The structure and buffer were not allocated dynamically and cannot be
 		freed - just scrub the structure so future use will assert. */
-		memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
+		( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
 	}
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
 {
-StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
-BaseType_t xReturn = pdFAIL, xIsMessageBuffer;
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn = pdFAIL;
 
 #if( configUSE_TRACE_FACILITY == 1 )
 	UBaseType_t uxStreamBufferNumber;
@@ -385,35 +409,30 @@ BaseType_t xReturn = pdFAIL, xIsMessageBuffer;
 	#endif
 
 	/* Can only reset a message buffer if there are no tasks blocked on it. */
-	if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
+	taskENTER_CRITICAL();
 	{
-		if( pxStreamBuffer->xTaskWaitingToSend == NULL )
+		if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
 		{
-			if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-			{
-				xIsMessageBuffer = pdTRUE;
-			}
-			else
+			if( pxStreamBuffer->xTaskWaitingToSend == NULL )
 			{
-				xIsMessageBuffer = pdFALSE;
-			}
-
-			prvInitialiseNewStreamBuffer( pxStreamBuffer,
-										  pxStreamBuffer->pucBuffer,
-										  pxStreamBuffer->xLength,
-										  pxStreamBuffer->xTriggerLevelBytes,
-										  xIsMessageBuffer );
-			xReturn = pdPASS;
+				prvInitialiseNewStreamBuffer( pxStreamBuffer,
+											  pxStreamBuffer->pucBuffer,
+											  pxStreamBuffer->xLength,
+											  pxStreamBuffer->xTriggerLevelBytes,
+											  pxStreamBuffer->ucFlags );
+				xReturn = pdPASS;
+
+				#if( configUSE_TRACE_FACILITY == 1 )
+				{
+					pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+				}
+				#endif
 
-			#if( configUSE_TRACE_FACILITY == 1 )
-			{
-				pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+				traceSTREAM_BUFFER_RESET( xStreamBuffer );
 			}
-			#endif
-
-			traceSTREAM_BUFFER_RESET( xStreamBuffer );
 		}
 	}
+	taskEXIT_CRITICAL();
 
 	return xReturn;
 }
@@ -421,7 +440,7 @@ BaseType_t xReturn = pdFAIL, xIsMessageBuffer;
 
 BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )
 {
-StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
 BaseType_t xReturn;
 
 	configASSERT( pxStreamBuffer );
@@ -429,7 +448,7 @@ BaseType_t xReturn;
 	/* It is not valid for the trigger level to be 0. */
 	if( xTriggerLevel == ( size_t ) 0 )
 	{
-		xTriggerLevel = ( size_t ) 1; /*lint !e9044 Parameter modified to ensure it doesn't have a dangerous value. */
+		xTriggerLevel = ( size_t ) 1;
 	}
 
 	/* The trigger level is the number of bytes that must be in the stream
@@ -450,7 +469,7 @@ BaseType_t xReturn;
 
 size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
 {
-const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
 size_t xSpace;
 
 	configASSERT( pxStreamBuffer );
@@ -474,7 +493,7 @@ size_t xSpace;
 
 size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
 {
-const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
 size_t xReturn;
 
 	configASSERT( pxStreamBuffer );
@@ -489,7 +508,7 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
 						  size_t xDataLengthBytes,
 						  TickType_t xTicksToWait )
 {
-StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
 size_t xReturn, xSpace = 0;
 size_t xRequiredSpace = xDataLengthBytes;
 TimeOut_t xTimeOut;
@@ -504,6 +523,9 @@ TimeOut_t xTimeOut;
 	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
 	{
 		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+
+		/* Overflow? */
+		configASSERT( xRequiredSpace > xDataLengthBytes );
 	}
 	else
 	{
@@ -540,7 +562,7 @@ TimeOut_t xTimeOut;
 			taskEXIT_CRITICAL();
 
 			traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
-			( void ) xTaskNotifyWait( ( uint32_t ) 0, UINT32_MAX, NULL, xTicksToWait );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
 			pxStreamBuffer->xTaskWaitingToSend = NULL;
 
 		} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
@@ -590,7 +612,7 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
 								 size_t xDataLengthBytes,
 								 BaseType_t * const pxHigherPriorityTaskWoken )
 {
-StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
 size_t xReturn, xSpace;
 size_t xRequiredSpace = xDataLengthBytes;
 
@@ -657,7 +679,7 @@ static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
 		stream of bytes rather than discrete messages.  Write as many bytes as
 		possible. */
 		xShouldWrite = pdTRUE;
-		xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); /*lint !e9044 Function parameter modified to ensure it is capped to available space. */
+		xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
 	}
 	else if( xSpace >= xRequiredSpace )
 	{
@@ -693,7 +715,7 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
 							 size_t xBufferLengthBytes,
 							 TickType_t xTicksToWait )
 {
-StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
 size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
 
 	configASSERT( pvRxData );
@@ -746,7 +768,7 @@ size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
 		{
 			/* Wait for data to be available. */
 			traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
-			( void ) xTaskNotifyWait( ( uint32_t ) 0, UINT32_MAX, NULL, xTicksToWait );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
 			pxStreamBuffer->xTaskWaitingToReceive = NULL;
 
 			/* Recheck the data available after blocking. */
@@ -792,12 +814,56 @@ size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
 }
 /*-----------------------------------------------------------*/
 
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xBytesAvailable, xOriginalTail;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* Ensure the stream buffer is being used as a message buffer. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )
+		{
+			/* The number of bytes available is greater than the number of bytes
+			required to hold the length of the next message, so another message
+			is available.  Return its length without removing the length bytes
+			from the buffer.  A copy of the tail is stored so the buffer can be
+			returned to its prior state as the message is not actually being
+			removed from the buffer. */
+			xOriginalTail = pxStreamBuffer->xTail;
+			( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable );
+			xReturn = ( size_t ) xTempReturn;
+			pxStreamBuffer->xTail = xOriginalTail;
+		}
+		else
+		{
+			/* The minimum amount of bytes in a message buffer is
+			( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is
+			less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid
+			value is 0. */
+			configASSERT( xBytesAvailable == 0 );
+			xReturn = 0;
+		}
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
 size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
 									void *pvRxData,
 									size_t xBufferLengthBytes,
 									BaseType_t * const pxHigherPriorityTaskWoken )
 {
-StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
 size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
 
 	configASSERT( pvRxData );
@@ -856,6 +922,7 @@ static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
 										size_t xBytesToStoreMessageLength )
 {
 size_t xOriginalTail, xReceivedLength, xNextMessageLength;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;
 
 	if( xBytesToStoreMessageLength != ( size_t ) 0 )
 	{
@@ -864,7 +931,8 @@ size_t xOriginalTail, xReceivedLength, xNextMessageLength;
 		returned to its prior state if the length of the message is too
 		large for the provided buffer. */
 		xOriginalTail = pxStreamBuffer->xTail;
-		( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
+		( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
+		xNextMessageLength = ( size_t ) xTempNextMessageLength;
 
 		/* Reduce the number of bytes available by the number of bytes just
 		read out. */
@@ -901,7 +969,7 @@ size_t xOriginalTail, xReceivedLength, xNextMessageLength;
 
 BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
 {
-const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
 BaseType_t xReturn;
 size_t xTail;
 
@@ -926,7 +994,7 @@ BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
 {
 BaseType_t xReturn;
 size_t xBytesToStoreMessageLength;
-const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
 
 	configASSERT( pxStreamBuffer );
 
@@ -959,7 +1027,7 @@ const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer
 
 BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
 {
-StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
 BaseType_t xReturn;
 UBaseType_t uxSavedInterruptStatus;
 
@@ -989,7 +1057,7 @@ UBaseType_t uxSavedInterruptStatus;
 
 BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
 {
-StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
 BaseType_t xReturn;
 UBaseType_t uxSavedInterruptStatus;
 
@@ -1032,7 +1100,7 @@ size_t xNextHead, xFirstLength;
 
 	/* Write as many bytes as can be written in the first write. */
 	configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
-	memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+	( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
 
 	/* If the number of bytes written was less than the number that could be
 	written in the first write... */
@@ -1040,7 +1108,7 @@ size_t xNextHead, xFirstLength;
 	{
 		/* ...then write the remaining bytes to the start of the buffer. */
 		configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
-		memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+		( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
 	}
 	else
 	{
@@ -1083,7 +1151,7 @@ size_t xCount, xFirstLength, xNextTail;
 		read.  Asserts check bounds of read and write. */
 		configASSERT( xFirstLength <= xMaxCount );
 		configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );
-		memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+		( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
 
 		/* If the total number of wanted bytes is greater than the number
 		that could be read in the first read... */
@@ -1091,7 +1159,7 @@ size_t xCount, xFirstLength, xNextTail;
 		{
 			/*...then read the remaining bytes from the start of the buffer. */
 			configASSERT( xCount <= xMaxCount );
-			memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+			( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
 		}
 		else
 		{
@@ -1142,7 +1210,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 										  uint8_t * const pucBuffer,
 										  size_t xBufferSizeBytes,
 										  size_t xTriggerLevelBytes,
-										  BaseType_t xIsMessageBuffer )
+										  uint8_t ucFlags )
 {
 	/* Assert here is deliberately writing to the entire buffer to ensure it can
 	be written to without generating exceptions, and is setting the buffer to a
@@ -1154,25 +1222,21 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 		result in confusion as to what is actually being observed. */
 		const BaseType_t xWriteValue = 0x55;
 		configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
-	}
+	} /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
 	#endif
 
-	memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
+	( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
 	pxStreamBuffer->pucBuffer = pucBuffer;
 	pxStreamBuffer->xLength = xBufferSizeBytes;
 	pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
-
-	if( xIsMessageBuffer != pdFALSE )
-	{
-		pxStreamBuffer->ucFlags |= sbFLAGS_IS_MESSAGE_BUFFER;
-	}
+	pxStreamBuffer->ucFlags = ucFlags;
 }
 
 #if ( configUSE_TRACE_FACILITY == 1 )
 
 	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
 	{
-		return ( ( StreamBuffer_t * ) xStreamBuffer )->uxStreamBufferNumber;
+		return xStreamBuffer->uxStreamBufferNumber;
 	}
 
 #endif /* configUSE_TRACE_FACILITY */
@@ -1182,7 +1246,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 
 	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber )
 	{
-		( ( StreamBuffer_t * ) xStreamBuffer )->uxStreamBufferNumber = uxStreamBufferNumber;
+		xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
 	}
 
 #endif /* configUSE_TRACE_FACILITY */
@@ -1192,7 +1256,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 
 	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
 	{
-		return ( ( StreamBuffer_t * )xStreamBuffer )->ucFlags | sbFLAGS_IS_MESSAGE_BUFFER;
+		return ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );
 	}
 
 #endif /* configUSE_TRACE_FACILITY */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/tasks.c b/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
index e41d9d18e..db0516d70 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -40,11 +40,11 @@ task.h is included from an application file. */
 #include "timers.h"
 #include "stack_macros.h"
 
-/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
-MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
-header files above, but not in this file, in order to generate the correct
-privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
 
 /* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
 functions but without including stdio.h here. */
@@ -75,24 +75,7 @@ functions but without including stdio.h here. */
  */
 #define tskSTACK_FILL_BYTE	( 0xa5U )
 
-/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
-dynamically allocated RAM, in which case when any task is deleted it is known
-that both the task's stack and TCB need to be freed.  Sometimes the
-FreeRTOSConfig.h settings only allow a task to be created using statically
-allocated RAM, in which case when any task is deleted it is known that neither
-the task's stack or TCB should be freed.  Sometimes the FreeRTOSConfig.h
-settings allow a task to be created using either statically or dynamically
-allocated RAM, in which case a member of the TCB is used to record whether the
-stack and/or TCB were allocated statically or dynamically, so when a task is
-deleted the RAM that was allocated dynamically is freed again and no attempt is
-made to free the RAM that was allocated statically.
-tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a
-task to be created using either statically or dynamically allocated RAM.  Note
-that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with
-a statically allocated stack and a dynamically allocated TCB.
-!!!NOTE!!! If the definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is
-changed then the definition of StaticTask_t must also be updated. */
-#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE	( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+/* Bits used to recored how a task's stack and TCB were allocated. */
 #define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB 		( ( uint8_t ) 0 )
 #define tskSTATICALLY_ALLOCATED_STACK_ONLY 			( ( uint8_t ) 1 )
 #define tskSTATICALLY_ALLOCATED_STACK_AND_TCB		( ( uint8_t ) 2 )
@@ -100,7 +83,7 @@ changed then the definition of StaticTask_t must also be updated. */
 /* If any of the following are set then task stacks are filled with a known
 value so the high water mark can be determined.  If none of the following are
 set then don't fill the stack so there is no unnecessary dependency on memset. */
-#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
 	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	1
 #else
 	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	0
@@ -245,7 +228,7 @@ count overflows. */
  * task should be used in place of the parameter.  This macro simply checks to
  * see if the parameter is NULL and returns a pointer to the appropriate TCB.
  */
-#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? ( TCB_t * ) pxCurrentTCB : ( TCB_t * ) ( pxHandle ) )
+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )
 
 /* The item value of the event list item is normally used to hold the priority
 of the task to which it belongs (coded to allow it to be held in reverse
@@ -266,7 +249,7 @@ to its original value when it is released. */
  * and stores task state information, including a pointer to the task's context
  * (the task's run time environment, including register values)
  */
-typedef struct tskTaskControlBlock
+typedef struct tskTaskControlBlock 			/* The old naming convention is used to prevent breaking kernel aware debuggers. */
 {
 	volatile StackType_t	*pxTopOfStack;	/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
 
@@ -326,9 +309,9 @@ typedef struct tskTaskControlBlock
 		volatile uint8_t ucNotifyState;
 	#endif
 
-	/* See the comments above the definition of
+	/* See the comments in FreeRTOS.h with the definition of
 	tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
-	#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */
+	#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
 		uint8_t	ucStaticallyAllocated; 		/*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
 	#endif
 
@@ -336,6 +319,10 @@ typedef struct tskTaskControlBlock
 		uint8_t ucDelayAborted;
 	#endif
 
+	#if( configUSE_POSIX_ERRNO == 1 )
+		int iTaskErrno;
+	#endif
+
 } tskTCB;
 
 /* The old tskTCB name is maintained above then typedefed to the new TCB_t name
@@ -344,30 +331,38 @@ typedef tskTCB TCB_t;
 
 /*lint -save -e956 A manual analysis and inspection has been used to determine
 which static variables must be declared volatile. */
-
 PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
 
-/* Lists for ready and blocked tasks. --------------------*/
-PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ] = {0};	/*< Prioritised ready tasks. */
-PRIVILEGED_DATA static List_t xDelayedTaskList1 = {0};								/*< Delayed tasks. */
-PRIVILEGED_DATA static List_t xDelayedTaskList2 = {0};								/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
-PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList = NULL;					/*< Points to the delayed task list currently being used. */
-PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList = NULL;			/*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
-PRIVILEGED_DATA static List_t xPendingReadyList = {0};								/*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */
+/* Lists for ready and blocked tasks. --------------------
+xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but
+doing so breaks some kernel aware debuggers and debuggers that rely on removing
+the static qualifier. */
+PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ] = { 0 };/*< Prioritised ready tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList1 = { 0 };						/*< Delayed tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList2 = { 0 };						/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList = NULL;				/*< Points to the delayed task list currently being used. */
+PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList = NULL;		/*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t xPendingReadyList = { 0 };						/*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */
 
 #if( INCLUDE_vTaskDelete == 1 )
 
-	PRIVILEGED_DATA static List_t xTasksWaitingTermination = {0};					/*< Tasks that have been deleted - but their memory not yet freed. */
+PRIVILEGED_DATA static List_t xTasksWaitingTermination = { 0 };				/*< Tasks that have been deleted - but their memory not yet freed. */
 	PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
 
 #endif
 
 #if ( INCLUDE_vTaskSuspend == 1 )
 
-	PRIVILEGED_DATA static List_t xSuspendedTaskList = {0};						/*< Tasks that are currently suspended. */
+	PRIVILEGED_DATA static List_t xSuspendedTaskList = { 0 };					/*< Tasks that are currently suspended. */
 
 #endif
 
+/* Global POSIX errno. Its value is changed upon context switching to match
+the errno of the currently running task. */
+#if ( configUSE_POSIX_ERRNO == 1 )
+	int FreeRTOS_errno = 0;
+#endif
+
 /* Other file private variables. --------------------------------*/
 PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks 	= ( UBaseType_t ) 0U;
 PRIVILEGED_DATA static volatile TickType_t xTickCount 				= ( TickType_t ) configINITIAL_TICK_COUNT;
@@ -392,6 +387,8 @@ PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended	= ( UBaseType_t
 
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
+	/* Do not move these variables to function scope as doing so prevents the
+	code working with debuggers that need to remove the static qualifier. */
 	PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;	/*< Holds the value of a timer/counter the last time a task was switched in. */
 	PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;		/*< Holds the total amount of execution time as defined by the run time counter clock. */
 
@@ -403,15 +400,21 @@ PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended	= ( UBaseType_t
 
 /* Callback function prototypes. --------------------------*/
 #if(  configCHECK_FOR_STACK_OVERFLOW > 0 )
+
 	extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
+
 #endif
 
 #if( configUSE_TICK_HOOK > 0 )
-	extern void vApplicationTickHook( void );
+
+	extern void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+
 #endif
 
 #if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize );
+
+	extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
+
 #endif
 
 /* File private functions. --------------------------------*/
@@ -501,9 +504,9 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseT
  * This function determines the 'high water mark' of the task stack by
  * determining how much of the stack remains at the original preset value.
  */
-#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
 
-	static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
 
 #endif
 
@@ -593,6 +596,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
 			structure. */
 			volatile size_t xSize = sizeof( StaticTask_t );
 			configASSERT( xSize == sizeof( TCB_t ) );
+			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
 		}
 		#endif /* configASSERT_DEFINED */
 
@@ -601,16 +605,16 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
 		{
 			/* The memory used for the task's TCB and stack are passed into this
 			function - use them. */
-			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
 			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
 
-			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
 			{
 				/* Tasks can be created statically or dynamically, so note this
 				task was created statically in case the task is later deleted. */
 				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
 			}
-			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
 
 			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
 			prvAddNewTaskToReadyList( pxNewTCB );
@@ -652,7 +656,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
 				task was created statically in case the task is later deleted. */
 				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
 			}
-			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
 
 			prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
 									pxTaskDefinition->pcName,
@@ -693,14 +697,14 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
 				/* Store the stack location in the TCB. */
 				pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
 
-				#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+				#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
 				{
 					/* Tasks can be created statically or dynamically, so note
 					this task had a statically allocated stack in case it is
 					later deleted.  The TCB was allocated dynamically. */
 					pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
 				}
-				#endif
+				#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
 
 				prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
 										pxTaskDefinition->pcName,
@@ -763,12 +767,12 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
 		StackType_t *pxStack;
 
 			/* Allocate space for the stack used by the task being created. */
-			pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
 
 			if( pxStack != NULL )
 			{
 				/* Allocate space for the TCB. */
-				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e961 MISRA exception as the casts are only redundant for some paths. */
+				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
 
 				if( pxNewTCB != NULL )
 				{
@@ -791,13 +795,13 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
 
 		if( pxNewTCB != NULL )
 		{
-			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
 			{
 				/* Tasks can be created statically or dynamically, so note this
 				task was created dynamically in case it is later deleted. */
 				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
 			}
-			#endif /* configSUPPORT_STATIC_ALLOCATION */
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
 
 			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
 			prvAddNewTaskToReadyList( pxNewTCB );
@@ -854,8 +858,8 @@ UBaseType_t x;
 	by the port. */
 	#if( portSTACK_GROWTH < 0 )
 	{
-		pxTopOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
-		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type. */
+		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
+		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
 
 		/* Check the alignment of the calculated top of stack is correct. */
 		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
@@ -882,26 +886,35 @@ UBaseType_t x;
 	#endif /* portSTACK_GROWTH */
 
 	/* Store the task name in the TCB. */
-	for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+	if( pcName != NULL )
 	{
-		pxNewTCB->pcTaskName[ x ] = pcName[ x ];
-
-		/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
-		configMAX_TASK_NAME_LEN characters just in case the memory after the
-		string is not accessible (extremely unlikely). */
-		if( pcName[ x ] == 0x00 )
-		{
-			break;
-		}
-		else
+		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
 		{
-			mtCOVERAGE_TEST_MARKER();
+			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
+
+			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+			configMAX_TASK_NAME_LEN characters just in case the memory after the
+			string is not accessible (extremely unlikely). */
+			if( pcName[ x ] == ( char ) 0x00 )
+			{
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
 		}
-	}
 
-	/* Ensure the name string is terminated in the case that the string length
-	was greater or equal to configMAX_TASK_NAME_LEN. */
-	pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+		/* Ensure the name string is terminated in the case that the string length
+		was greater or equal to configMAX_TASK_NAME_LEN. */
+		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+	}
+	else
+	{
+		/* The task has not been given a name, so just ensure there is a NULL
+		terminator when it is read out. */
+		pxNewTCB->pcTaskName[ 0 ] = 0x00;
+	}
 
 	/* This is used as an array index so must ensure it's not too large.  First
 	remove the privilege bit if one is present. */
@@ -997,15 +1010,53 @@ UBaseType_t x;
 	the top of stack variable is updated. */
 	#if( portUSING_MPU_WRAPPERS == 1 )
 	{
-		pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+		/* If the port has capability to detect stack overflow,
+		pass the stack end address to the stack initialization
+		function as well. */
+		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		{
+			#if( portSTACK_GROWTH < 0 )
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );
+			}
+			#else /* portSTACK_GROWTH */
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
 	}
 	#else /* portUSING_MPU_WRAPPERS */
 	{
-		pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+		/* If the port has capability to detect stack overflow,
+		pass the stack end address to the stack initialization
+		function as well. */
+		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		{
+			#if( portSTACK_GROWTH < 0 )
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
+			}
+			#else /* portSTACK_GROWTH */
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
 	}
 	#endif /* portUSING_MPU_WRAPPERS */
 
-	if( ( void * ) pxCreatedTask != NULL )
+	if( pxCreatedTask != NULL )
 	{
 		/* Pass the handle out in an anonymous way.  The handle can be used to
 		change the created task's priority, delete the created task, etc.*/
@@ -1322,13 +1373,13 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 #endif /* INCLUDE_vTaskDelay */
 /*-----------------------------------------------------------*/
 
-#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) )
+#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
 
 	eTaskState eTaskGetState( TaskHandle_t xTask )
 	{
 	eTaskState eReturn;
-	List_t *pxStateList;
-	const TCB_t * const pxTCB = ( TCB_t * ) xTask;
+	List_t const * pxStateList, *pxDelayedList, *pxOverflowedDelayedList;
+	const TCB_t * const pxTCB = xTask;
 
 		configASSERT( pxTCB );
 
@@ -1341,11 +1392,13 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 		{
 			taskENTER_CRITICAL();
 			{
-				pxStateList = ( List_t * ) listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+				pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+				pxDelayedList = pxDelayedTaskList;
+				pxOverflowedDelayedList = pxOverflowDelayedTaskList;
 			}
 			taskEXIT_CRITICAL();
 
-			if( ( pxStateList == pxDelayedTaskList ) || ( pxStateList == pxOverflowDelayedTaskList ) )
+			if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
 			{
 				/* The task being queried is referenced from one of the Blocked
 				lists. */
@@ -1356,11 +1409,30 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 				else if( pxStateList == &xSuspendedTaskList )
 				{
 					/* The task being queried is referenced from the suspended
-					list.  Is it genuinely suspended or is it block
+					list.  Is it genuinely suspended or is it blocked
 					indefinitely? */
 					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
 					{
-						eReturn = eSuspended;
+						#if( configUSE_TASK_NOTIFICATIONS == 1 )
+						{
+							/* The task does not appear on the event list item of
+							and of the RTOS objects, but could still be in the
+							blocked state if it is waiting on its notification
+							rather than waiting on an object. */
+							if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+							{
+								eReturn = eBlocked;
+							}
+							else
+							{
+								eReturn = eSuspended;
+							}
+						}
+						#else
+						{
+							eReturn = eSuspended;
+						}
+						#endif
 					}
 					else
 					{
@@ -1395,15 +1467,15 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 
 #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-	UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask )
+	UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )
 	{
-	TCB_t *pxTCB;
+	TCB_t const *pxTCB;
 	UBaseType_t uxReturn;
 
 		taskENTER_CRITICAL();
 		{
-			/* If null is passed in here then it is the priority of the that
-			called uxTaskPriorityGet() that is being queried. */
+			/* If null is passed in here then it is the priority of the task
+			that called uxTaskPriorityGet() that is being queried. */
 			pxTCB = prvGetTCBFromHandle( xTask );
 			uxReturn = pxTCB->uxPriority;
 		}
@@ -1417,9 +1489,9 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 
 #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-	UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask )
+	UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )
 	{
-	TCB_t *pxTCB;
+	TCB_t const *pxTCB;
 	UBaseType_t uxReturn, uxSavedInterruptState;
 
 		/* RTOS ports that support interrupt nesting have the concept of a
@@ -1437,7 +1509,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 		separate interrupt safe API to ensure interrupt entry is as fast and as
 		simple as possible.  More information (albeit Cortex-M specific) is
 		provided on the following link:
-		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
 		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
 		uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
@@ -1697,7 +1769,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 				/* The scheduler is not running, but the task that was pointed
 				to by pxCurrentTCB has just been suspended and pxCurrentTCB
 				must be adjusted to point to a different task. */
-				if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks )
+				if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
 				{
 					/* No other tasks are ready, so set pxCurrentTCB back to
 					NULL so when the next task is created pxCurrentTCB will
@@ -1725,7 +1797,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
 	{
 	BaseType_t xReturn = pdFALSE;
-	const TCB_t * const pxTCB = ( TCB_t * ) xTask;
+	const TCB_t * const pxTCB = xTask;
 
 		/* Accesses xPendingReadyList so must be called from a critical
 		section. */
@@ -1770,14 +1842,14 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 
 	void vTaskResume( TaskHandle_t xTaskToResume )
 	{
-	TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;
+	TCB_t * const pxTCB = xTaskToResume;
 
 		/* It does not make sense to resume the calling task. */
 		configASSERT( xTaskToResume );
 
 		/* The parameter cannot be NULL as it is impossible to resume the
 		currently executing task. */
-		if( ( pxTCB != NULL ) && ( pxTCB != pxCurrentTCB ) )
+		if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
 		{
 			taskENTER_CRITICAL();
 			{
@@ -1825,7 +1897,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 	BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
 	{
 	BaseType_t xYieldRequired = pdFALSE;
-	TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;
+	TCB_t * const pxTCB = xTaskToResume;
 	UBaseType_t uxSavedInterruptStatus;
 
 		configASSERT( xTaskToResume );
@@ -1845,7 +1917,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 		separate interrupt safe API to ensure interrupt entry is as fast and as
 		simple as possible.  More information (albeit Cortex-M specific) is
 		provided on the following link:
-		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
 		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
 		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
@@ -1910,7 +1982,7 @@ BaseType_t xReturn;
 												configIDLE_TASK_NAME,
 												ulIdleTaskStackSize,
 												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
-												( tskIDLE_PRIORITY | portPRIVILEGE_BIT ),
+												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
 												pxIdleTaskStackBuffer,
 												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
 
@@ -1930,7 +2002,7 @@ BaseType_t xReturn;
 								configIDLE_TASK_NAME,
 								configMINIMAL_STACK_SIZE,
 								( void * ) NULL,
-								( tskIDLE_PRIORITY | portPRIVILEGE_BIT ),
+								portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
 								&xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
 	}
 	#endif /* configSUPPORT_STATIC_ALLOCATION */
@@ -1976,7 +2048,7 @@ BaseType_t xReturn;
 
 		xNextTaskUnblockTime = portMAX_DELAY;
 		xSchedulerRunning = pdTRUE;
-		xTickCount = ( TickType_t ) 0U;
+		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
 
 		/* If configGENERATE_RUN_TIME_STATS is defined then the following
 		macro must be defined to configure the timer/counter used to generate
@@ -1986,6 +2058,8 @@ BaseType_t xReturn;
 		FreeRTOSConfig.h file. */
 		portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
 
+		traceTASK_SWITCHED_IN();
+
 		/* Setting up the timer tick is hardware specific and thus in the
 		portable interface. */
 		if( xPortStartScheduler() != pdFALSE )
@@ -2030,6 +2104,7 @@ void vTaskSuspendAll( void )
 	post in the FreeRTOS support forum before reporting this as a bug! -
 	http://goo.gl/wu4acr */
 	++uxSchedulerSuspended;
+	portMEMORY_BARRIER();
 }
 /*----------------------------------------------------------*/
 
@@ -2122,7 +2197,7 @@ BaseType_t xAlreadyYielded = pdFALSE;
 				appropriate ready list. */
 				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
 				{
-					pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) );
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
 					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 					prvAddTaskToReadyList( pxTCB );
@@ -2239,7 +2314,7 @@ UBaseType_t uxSavedInterruptStatus;
 	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
 	safe API to ensure interrupt entry is as fast and as simple as possible.
 	More information (albeit Cortex-M specific) is provided on the following
-	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
 	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
 	uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
@@ -2279,19 +2354,21 @@ TCB_t *pxTCB;
 	TCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;
 	UBaseType_t x;
 	char cNextChar;
+	BaseType_t xBreakLoop;
 
 		/* This function is called with the scheduler suspended. */
 
 		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
 		{
-			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );  /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 
 			do
 			{
-				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 
 				/* Check each character in the name looking for a match or
 				mismatch. */
+				xBreakLoop = pdFALSE;
 				for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
 				{
 					cNextChar = pxNextTCB->pcTaskName[ x ];
@@ -2299,19 +2376,24 @@ TCB_t *pxTCB;
 					if( cNextChar != pcNameToQuery[ x ] )
 					{
 						/* Characters didn't match. */
-						break;
+						xBreakLoop = pdTRUE;
 					}
-					else if( cNextChar == 0x00 )
+					else if( cNextChar == ( char ) 0x00 )
 					{
 						/* Both strings terminated, a match must have been
 						found. */
 						pxReturn = pxNextTCB;
-						break;
+						xBreakLoop = pdTRUE;
 					}
 					else
 					{
 						mtCOVERAGE_TEST_MARKER();
 					}
+
+					if( xBreakLoop != pdFALSE )
+					{
+						break;
+					}
 				}
 
 				if( pxReturn != NULL )
@@ -2392,7 +2474,7 @@ TCB_t *pxTCB;
 		}
 		( void ) xTaskResumeAll();
 
-		return ( TaskHandle_t ) pxTCB;
+		return pxTCB;
 	}
 
 #endif /* INCLUDE_xTaskGetHandle */
@@ -2508,7 +2590,7 @@ implementations require configUSE_TICKLESS_IDLE to be set to a value other than
 
 	BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
 	{
-	TCB_t *pxTCB = ( TCB_t * ) xTask;
+	TCB_t *pxTCB = xTask;
 	BaseType_t xReturn;
 
 		configASSERT( pxTCB );
@@ -2633,7 +2715,7 @@ BaseType_t xSwitchRequired = pdFALSE;
 					item at the head of the delayed list.  This is the time
 					at which the task at the head of the delayed list must
 					be removed from the Blocked state. */
-					pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
 
 					if( xConstTickCount < xItemValue )
@@ -2644,7 +2726,7 @@ BaseType_t xSwitchRequired = pdFALSE;
 						state -	so record the item value in
 						xNextTaskUnblockTime. */
 						xNextTaskUnblockTime = xItemValue;
-						break;
+						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
 					}
 					else
 					{
@@ -2766,13 +2848,15 @@ BaseType_t xSwitchRequired = pdFALSE;
 		}
 		else
 		{
-			xTCB = ( TCB_t * ) xTask;
+			xTCB = xTask;
 		}
 
 		/* Save the hook function in the TCB.  A critical section is required as
 		the value can be accessed from an interrupt. */
 		taskENTER_CRITICAL();
+		{
 			xTCB->pxTaskTag = pxHookFunction;
+		}
 		taskEXIT_CRITICAL();
 	}
 
@@ -2783,24 +2867,17 @@ BaseType_t xSwitchRequired = pdFALSE;
 
 	TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
 	{
-	TCB_t *xTCB;
+	TCB_t *pxTCB;
 	TaskHookFunction_t xReturn;
 
-		/* If xTask is NULL then we are setting our own task hook. */
-		if( xTask == NULL )
-		{
-			xTCB = ( TCB_t * ) pxCurrentTCB;
-		}
-		else
-		{
-			xTCB = ( TCB_t * ) xTask;
-		}
+		/* If xTask is NULL then set the calling task's hook. */
+		pxTCB = prvGetTCBFromHandle( xTask );
 
 		/* Save the hook function in the TCB.  A critical section is required as
 		the value can be accessed from an interrupt. */
 		taskENTER_CRITICAL();
 		{
-			xReturn = xTCB->pxTaskTag;
+			xReturn = pxTCB->pxTaskTag;
 		}
 		taskEXIT_CRITICAL();
 
@@ -2810,6 +2887,31 @@ BaseType_t xSwitchRequired = pdFALSE;
 #endif /* configUSE_APPLICATION_TASK_TAG */
 /*-----------------------------------------------------------*/
 
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	TaskHookFunction_t xReturn;
+	UBaseType_t uxSavedInterruptStatus;
+
+		/* If xTask is NULL then set the calling task's hook. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			xReturn = pxTCB->pxTaskTag;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
 #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
 	BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
@@ -2820,11 +2922,11 @@ BaseType_t xSwitchRequired = pdFALSE;
 		/* If xTask is NULL then we are calling our own task hook. */
 		if( xTask == NULL )
 		{
-			xTCB = ( TCB_t * ) pxCurrentTCB;
+			xTCB = pxCurrentTCB;
 		}
 		else
 		{
-			xTCB = ( TCB_t * ) xTask;
+			xTCB = xTask;
 		}
 
 		if( xTCB->pxTaskTag != NULL )
@@ -2857,39 +2959,53 @@ void vTaskSwitchContext( void )
 
 		#if ( configGENERATE_RUN_TIME_STATS == 1 )
 		{
-				#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
-					portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
-				#else
-					ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
-				#endif
+			#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+				portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
+			#else
+				ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+			#endif
 
-				/* Add the amount of time the task has been running to the
-				accumulated time so far.  The time the task started running was
-				stored in ulTaskSwitchedInTime.  Note that there is no overflow
-				protection here so count values are only valid until the timer
-				overflows.  The guard against negative values is to protect
-				against suspect run time stat counter implementations - which
-				are provided by the application, not the kernel. */
-				if( ulTotalRunTime > ulTaskSwitchedInTime )
-				{
-					pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-				ulTaskSwitchedInTime = ulTotalRunTime;
+			/* Add the amount of time the task has been running to the
+			accumulated time so far.  The time the task started running was
+			stored in ulTaskSwitchedInTime.  Note that there is no overflow
+			protection here so count values are only valid until the timer
+			overflows.  The guard against negative values is to protect
+			against suspect run time stat counter implementations - which
+			are provided by the application, not the kernel. */
+			if( ulTotalRunTime > ulTaskSwitchedInTime )
+			{
+				pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			ulTaskSwitchedInTime = ulTotalRunTime;
 		}
 		#endif /* configGENERATE_RUN_TIME_STATS */
 
 		/* Check for stack overflow, if configured. */
 		taskCHECK_FOR_STACK_OVERFLOW();
 
+		/* Before the currently running task is switched out, save its errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+		}
+		#endif
+
 		/* Select a new task to run using either the generic C or port
 		optimised asm code. */
-		taskSELECT_HIGHEST_PRIORITY_TASK();
+		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 		traceTASK_SWITCHED_IN();
 
+		/* After the new task is switched in, update the global errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+		}
+		#endif
+
 		#if ( configUSE_NEWLIB_REENTRANT == 1 )
 		{
 			/* Switch Newlib's _impure_ptr variable to point to the _reent
@@ -2993,7 +3109,7 @@ BaseType_t xReturn;
 
 	This function assumes that a check has already been made to ensure that
 	pxEventList is not empty. */
-	pxUnblockedTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
+	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 	configASSERT( pxUnblockedTCB );
 	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
 
@@ -3001,6 +3117,20 @@ BaseType_t xReturn;
 	{
 		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
 		prvAddTaskToReadyList( pxUnblockedTCB );
+
+		#if( configUSE_TICKLESS_IDLE != 0 )
+		{
+			/* If a task is blocked on a kernel object then xNextTaskUnblockTime
+			might be set to the blocked task's time out time.  If the task is
+			unblocked for a reason other than a timeout xNextTaskUnblockTime is
+			normally left unchanged, because it is automatically reset to a new
+			value when the tick count equals xNextTaskUnblockTime.  However if
+			tickless idling is used it might be more important to enter sleep mode
+			at the earliest possible time - so reset xNextTaskUnblockTime here to
+			ensure it is updated at the earliest possible time. */
+			prvResetNextTaskUnblockTime();
+		}
+		#endif
 	}
 	else
 	{
@@ -3025,20 +3155,6 @@ BaseType_t xReturn;
 		xReturn = pdFALSE;
 	}
 
-	#if( configUSE_TICKLESS_IDLE != 0 )
-	{
-		/* If a task is blocked on a kernel object then xNextTaskUnblockTime
-		might be set to the blocked task's time out time.  If the task is
-		unblocked for a reason other than a timeout xNextTaskUnblockTime is
-		normally left unchanged, because it is automatically reset to a new
-		value when the tick count equals xNextTaskUnblockTime.  However if
-		tickless idling is used it might be more important to enter sleep mode
-		at the earliest possible time - so reset xNextTaskUnblockTime here to
-		ensure it is updated at the earliest possible time. */
-		prvResetNextTaskUnblockTime();
-	}
-	#endif
-
 	return xReturn;
 }
 /*-----------------------------------------------------------*/
@@ -3056,7 +3172,7 @@ TCB_t *pxUnblockedTCB;
 
 	/* Remove the event list form the event flag.  Interrupts do not access
 	event flags. */
-	pxUnblockedTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxEventListItem );
+	pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 	configASSERT( pxUnblockedTCB );
 	( void ) uxListRemove( pxEventListItem );
 
@@ -3111,7 +3227,7 @@ BaseType_t xReturn;
 		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
 
 		#if( INCLUDE_xTaskAbortDelay == 1 )
-			if( pxCurrentTCB->ucDelayAborted != pdFALSE )
+			if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
 			{
 				/* The delay was aborted, which is not the same as a time out,
 				but has the same result. */
@@ -3171,11 +3287,11 @@ void vTaskMissedYield( void )
 	UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
 	{
 	UBaseType_t uxReturn;
-	TCB_t *pxTCB;
+	TCB_t const *pxTCB;
 
 		if( xTask != NULL )
 		{
-			pxTCB = ( TCB_t * ) xTask;
+			pxTCB = xTask;
 			uxReturn = pxTCB->uxTaskNumber;
 		}
 		else
@@ -3193,11 +3309,11 @@ void vTaskMissedYield( void )
 
 	void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
 	{
-	TCB_t *pxTCB;
+	TCB_t * pxTCB;
 
 		if( xTask != NULL )
 		{
-			pxTCB = ( TCB_t * ) xTask;
+			pxTCB = xTask;
 			pxTCB->uxTaskNumber = uxHandle;
 		}
 	}
@@ -3226,7 +3342,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
 	/* In case a task that has a secure context deletes itself, in which case
 	the idle task is responsible for deleting the task's secure context, if
 	any. */
-	portTASK_CALLS_SECURE_FUNCTIONS();
+	portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
 
 	for( ;; )
 	{
@@ -3468,13 +3584,13 @@ static void prvCheckTasksWaitingTermination( void )
 	{
 		TCB_t *pxTCB;
 
-		/* uxDeletedTasksWaitingCleanUp is used to prevent vTaskSuspendAll()
+		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
 		being called too often in the idle task. */
 		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
 		{
 			taskENTER_CRITICAL();
 			{
-				pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );
+				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 				--uxCurrentNumberOfTasks;
 				--uxDeletedTasksWaitingCleanUp;
@@ -3593,7 +3709,7 @@ static void prvCheckTasksWaitingTermination( void )
 
 		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
 		{
-			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 
 			/* Populate an TaskStatus_t structure within the
 			pxTaskStatusArray array for each task that is referenced from
@@ -3601,7 +3717,7 @@ static void prvCheckTasksWaitingTermination( void )
 			meaning of each TaskStatus_t structure member. */
 			do
 			{
-				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 				vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
 				uxTask++;
 			} while( pxNextTCB != pxFirstTCB );
@@ -3617,9 +3733,9 @@ static void prvCheckTasksWaitingTermination( void )
 #endif /* configUSE_TRACE_FACILITY */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
 
-	static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
 	{
 	uint32_t ulCount = 0U;
 
@@ -3631,10 +3747,50 @@ static void prvCheckTasksWaitingTermination( void )
 
 		ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
 
-		return ( uint16_t ) ulCount;
+		return ( configSTACK_DEPTH_TYPE ) ulCount;
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+	/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+	same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+	user to determine the return type.  It gets around the problem of the value
+	overflowing on 8-bit types without breaking backward compatibility for
+	applications that expect an 8-bit return type. */
+	configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	configSTACK_DEPTH_TYPE uxReturn;
+
+		/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
+		the same except for their return type.  Using configSTACK_DEPTH_TYPE
+		allows the user to determine the return type.  It gets around the
+		problem of the value overflowing on 8-bit types without breaking
+		backward compatibility for applications that expect an 8-bit return
+		type. */
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
 	}
 
-#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) */
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */
 /*-----------------------------------------------------------*/
 
 #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
@@ -3689,7 +3845,7 @@ static void prvCheckTasksWaitingTermination( void )
 			vPortFree( pxTCB->pxStack );
 			vPortFree( pxTCB );
 		}
-		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */
+		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
 		{
 			/* The task could have been allocated statically or dynamically, so
 			check what was statically allocated before trying to free the
@@ -3739,7 +3895,7 @@ TCB_t *pxTCB;
 		the item at the head of the delayed list.  This is the time at
 		which the task at the head of the delayed list should be removed
 		from the Blocked state. */
-		( pxTCB ) = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
+		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
 	}
 }
@@ -3794,7 +3950,7 @@ TCB_t *pxTCB;
 
 	BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
 	{
-	TCB_t * const pxMutexHolderTCB = ( TCB_t * ) pxMutexHolder;
+	TCB_t * const pxMutexHolderTCB = pxMutexHolder;
 	BaseType_t xReturn = pdFALSE;
 
 		/* If the mutex was given back by an interrupt while the queue was
@@ -3881,7 +4037,7 @@ TCB_t *pxTCB;
 
 	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
 	{
-	TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;
+	TCB_t * const pxTCB = pxMutexHolder;
 	BaseType_t xReturn = pdFALSE;
 
 		if( pxMutexHolder != NULL )
@@ -3961,7 +4117,7 @@ TCB_t *pxTCB;
 
 	void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
 	{
-	TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;
+	TCB_t * const pxTCB = pxMutexHolder;
 	UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
 	const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
 
@@ -4139,7 +4295,7 @@ TCB_t *pxTCB;
 		}
 
 		/* Terminate. */
-		pcBuffer[ x ] = 0x00;
+		pcBuffer[ x ] = ( char ) 0x00;
 
 		/* Return the new end of string. */
 		return &( pcBuffer[ x ] );
@@ -4153,7 +4309,7 @@ TCB_t *pxTCB;
 	void vTaskList( char * pcWriteBuffer )
 	{
 	TaskStatus_t *pxTaskStatusArray;
-	volatile UBaseType_t uxArraySize, x;
+	UBaseType_t uxArraySize, x;
 	char cStatus;
 
 		/*
@@ -4182,7 +4338,7 @@ TCB_t *pxTCB;
 
 
 		/* Make sure the write buffer does not contain a string. */
-		*pcWriteBuffer = 0x00;
+		*pcWriteBuffer = ( char ) 0x00;
 
 		/* Take a snapshot of the number of tasks in case it changes while this
 		function is executing. */
@@ -4191,7 +4347,7 @@ TCB_t *pxTCB;
 		/* Allocate an array index for each task.  NOTE!  if
 		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
 		equate to NULL. */
-		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
 
 		if( pxTaskStatusArray != NULL )
 		{
@@ -4218,9 +4374,10 @@ TCB_t *pxTCB;
 					case eDeleted:		cStatus = tskDELETED_CHAR;
 										break;
 
+					case eInvalid:		/* Fall through. */
 					default:			/* Should not get here, but it is included
 										to prevent static checking errors. */
-										cStatus = 0x00;
+										cStatus = ( char ) 0x00;
 										break;
 				}
 
@@ -4229,8 +4386,8 @@ TCB_t *pxTCB;
 				pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
 
 				/* Write the rest of the string. */
-				sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber );
-				pcWriteBuffer += strlen( pcWriteBuffer );
+				sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+				pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
 			}
 
 			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
@@ -4251,7 +4408,7 @@ TCB_t *pxTCB;
 	void vTaskGetRunTimeStats( char *pcWriteBuffer )
 	{
 	TaskStatus_t *pxTaskStatusArray;
-	volatile UBaseType_t uxArraySize, x;
+	UBaseType_t uxArraySize, x;
 	uint32_t ulTotalTime, ulStatsAsPercentage;
 
 		#if( configUSE_TRACE_FACILITY != 1 )
@@ -4286,7 +4443,7 @@ TCB_t *pxTCB;
 		 */
 
 		/* Make sure the write buffer does not contain a string. */
-		*pcWriteBuffer = 0x00;
+		*pcWriteBuffer = ( char ) 0x00;
 
 		/* Take a snapshot of the number of tasks in case it changes while this
 		function is executing. */
@@ -4295,7 +4452,7 @@ TCB_t *pxTCB;
 		/* Allocate an array index for each task.  NOTE!  If
 		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
 		equate to NULL. */
-		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
 
 		if( pxTaskStatusArray != NULL )
 		{
@@ -4306,7 +4463,7 @@ TCB_t *pxTCB;
 			ulTotalTime /= 100UL;
 
 			/* Avoid divide by zero errors. */
-			if( ulTotalTime > 0 )
+			if( ulTotalTime > 0UL )
 			{
 				/* Create a human readable table from the binary data. */
 				for( x = 0; x < uxArraySize; x++ )
@@ -4331,7 +4488,7 @@ TCB_t *pxTCB;
 						{
 							/* sizeof( int ) == sizeof( long ) so a smaller
 							printf() library can be used. */
-							sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage );
+							sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
 						}
 						#endif
 					}
@@ -4347,12 +4504,12 @@ TCB_t *pxTCB;
 						{
 							/* sizeof( int ) == sizeof( long ) so a smaller
 							printf() library can be used. */
-							sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter );
+							sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
 						}
 						#endif
 					}
 
-					pcWriteBuffer += strlen( pcWriteBuffer );
+					pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
 				}
 			}
 			else
@@ -4389,7 +4546,7 @@ TickType_t uxReturn;
 
 #if ( configUSE_MUTEXES == 1 )
 
-	void *pvTaskIncrementMutexHeldCount( void )
+	TaskHandle_t pvTaskIncrementMutexHeldCount( void )
 	{
 		/* If xSemaphoreCreateMutex() is called before any tasks have been created
 		then pxCurrentTCB will be NULL. */
@@ -4561,7 +4718,7 @@ TickType_t uxReturn;
 	uint8_t ucOriginalNotifyState;
 
 		configASSERT( xTaskToNotify );
-		pxTCB = ( TCB_t * ) xTaskToNotify;
+		pxTCB = xTaskToNotify;
 
 		taskENTER_CRITICAL();
 		{
@@ -4604,6 +4761,14 @@ TickType_t uxReturn;
 					/* The task is being notified without its notify value being
 					updated. */
 					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+
+					break;
 			}
 
 			traceTASK_NOTIFY();
@@ -4687,7 +4852,7 @@ TickType_t uxReturn;
 		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
 		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
-		pxTCB = ( TCB_t * ) xTaskToNotify;
+		pxTCB = xTaskToNotify;
 
 		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
 		{
@@ -4729,6 +4894,13 @@ TickType_t uxReturn;
 					/* The task is being notified without its notify value being
 					updated. */
 					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+					break;
 			}
 
 			traceTASK_NOTIFY_FROM_ISR();
@@ -4760,13 +4932,11 @@ TickType_t uxReturn;
 					{
 						*pxHigherPriorityTaskWoken = pdTRUE;
 					}
-					else
-					{
-						/* Mark that a yield is pending in case the user is not
-						using the "xHigherPriorityTaskWoken" parameter to an ISR
-						safe FreeRTOS function. */
-						xYieldPending = pdTRUE;
-					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter to an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
 				}
 				else
 				{
@@ -4810,7 +4980,7 @@ TickType_t uxReturn;
 		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
 		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
-		pxTCB = ( TCB_t * ) xTaskToNotify;
+		pxTCB = xTaskToNotify;
 
 		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
 		{
@@ -4850,13 +5020,11 @@ TickType_t uxReturn;
 					{
 						*pxHigherPriorityTaskWoken = pdTRUE;
 					}
-					else
-					{
-						/* Mark that a yield is pending in case the user is not
-						using the "xHigherPriorityTaskWoken" parameter in an ISR
-						safe FreeRTOS function. */
-						xYieldPending = pdTRUE;
-					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter in an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
 				}
 				else
 				{
@@ -4902,6 +5070,13 @@ TickType_t uxReturn;
 #endif /* configUSE_TASK_NOTIFICATIONS */
 /*-----------------------------------------------------------*/
 
+#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+	TickType_t xTaskGetIdleRunTimeCounter( void )
+	{
+		return xIdleTaskHandle->ulRunTimeCounter;
+	}
+#endif
+/*-----------------------------------------------------------*/
 
 static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
 {
@@ -4923,7 +5098,7 @@ const TickType_t xConstTickCount = xTickCount;
 	{
 		/* The current task must be in a ready list, so there is no need to
 		check, and the port reset macro can be called directly. */
-		portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
+		portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
 	}
 	else
 	{
@@ -5027,12 +5202,12 @@ when performing module tests). */
 
 	#include "freertos_tasks_c_additions.h"
 
-	static void freertos_tasks_c_additions_init( void )
-	{
-		#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+	#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		static void freertos_tasks_c_additions_init( void )
+		{
 			FREERTOS_TASKS_C_ADDITIONS_INIT();
-		#endif
-	}
+		}
+	#endif
 
 #endif
 
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/timers.c b/Middlewares/Third_Party/FreeRTOS/Source/timers.c
index 002dd8bab..59b3840d7 100644
--- a/Middlewares/Third_Party/FreeRTOS/Source/timers.c
+++ b/Middlewares/Third_Party/FreeRTOS/Source/timers.c
@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -42,11 +42,11 @@ task.h is included from an application file. */
 	#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
 #endif
 
-/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
-MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
-header files above, but not in this file, in order to generate the correct
-privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */
 
 
 /* This entire source file will be skipped if the application is not configured
@@ -64,22 +64,23 @@ defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
 	#define configTIMER_SERVICE_TASK_NAME "Tmr Svc"
 #endif
 
+/* Bit definitions used in the ucStatus member of a timer structure. */
+#define tmrSTATUS_IS_ACTIVE					( ( uint8_t ) 0x01 )
+#define tmrSTATUS_IS_STATICALLY_ALLOCATED	( ( uint8_t ) 0x02 )
+#define tmrSTATUS_IS_AUTORELOAD				( ( uint8_t ) 0x04 )
+
 /* The definition of the timers themselves. */
-typedef struct tmrTimerControl
+typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */
 {
 	const char				*pcTimerName;		/*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 	ListItem_t				xTimerListItem;		/*<< Standard linked list item as used by all kernel features for event management. */
 	TickType_t				xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
-	UBaseType_t				uxAutoReload;		/*<< Set to pdTRUE if the timer should be automatically restarted once expired.  Set to pdFALSE if the timer is, in effect, a one-shot timer. */
 	void 					*pvTimerID;			/*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
 	TimerCallbackFunction_t	pxCallbackFunction;	/*<< The function that will be called when the timer expires. */
 	#if( configUSE_TRACE_FACILITY == 1 )
 		UBaseType_t			uxTimerNumber;		/*<< An ID assigned by trace tools such as FreeRTOS+Trace */
 	#endif
-
-	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-		uint8_t 			ucStaticallyAllocated; /*<< Set to pdTRUE if the timer was created statically so no attempt is made to free the memory again if the timer is later deleted. */
-	#endif
+	uint8_t 				ucStatus;			/*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
 } xTIMER;
 
 /* The old xTIMER name is maintained above then typedefed to the new Timer_t
@@ -127,9 +128,12 @@ which static variables must be declared volatile. */
 
 /* The list in which active timers are stored.  Timers are referenced in expire
 time order, with the nearest expiry time at the front of the list.  Only the
-timer service task is allowed to access these lists. */
-PRIVILEGED_DATA static List_t xActiveTimerList1 = {0};
-PRIVILEGED_DATA static List_t xActiveTimerList2 = {0};
+timer service task is allowed to access these lists.
+xActiveTimerList1 and xActiveTimerList2 could be at function scope but that
+breaks some kernel aware debuggers, and debuggers that reply on removing the
+static qualifier. */
+PRIVILEGED_DATA static List_t xActiveTimerList1 = { 0 };
+PRIVILEGED_DATA static List_t xActiveTimerList2 = { 0 };
 PRIVILEGED_DATA static List_t *pxCurrentTimerList = NULL;
 PRIVILEGED_DATA static List_t *pxOverflowTimerList = NULL;
 
@@ -162,7 +166,7 @@ static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
  * task.  Other tasks communicate with the timer service task using the
  * xTimerQueue queue.
  */
-static void prvTimerTask( void *pvParameters ) PRIVILEGED_FUNCTION;
+static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;
 
 /*
  * Called by the timer service task to interpret and process a command it
@@ -283,26 +287,21 @@ BaseType_t xReturn = pdFAIL;
 	{
 	Timer_t *pxNewTimer;
 
-		pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) );
+		pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
 
 		if( pxNewTimer != NULL )
 		{
+			/* Status is thus far zero as the timer is not created statically
+			and has not been started.  The autoreload bit may get set in
+			prvInitialiseNewTimer. */
+			pxNewTimer->ucStatus = 0x00;
 			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
-
-			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-			{
-				/* Timers can be created statically or dynamically, so note this
-				timer was created dynamically in case the timer is later
-				deleted. */
-				pxNewTimer->ucStaticallyAllocated = pdFALSE;
-			}
-			#endif /* configSUPPORT_STATIC_ALLOCATION */
 		}
 
 		return pxNewTimer;
 	}
 
-#endif /* configSUPPORT_STATIC_ALLOCATION */
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
 /*-----------------------------------------------------------*/
 
 #if( configSUPPORT_STATIC_ALLOCATION == 1 )
@@ -323,24 +322,22 @@ BaseType_t xReturn = pdFAIL;
 			structure. */
 			volatile size_t xSize = sizeof( StaticTimer_t );
 			configASSERT( xSize == sizeof( Timer_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
 		}
 		#endif /* configASSERT_DEFINED */
 
 		/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
 		configASSERT( pxTimerBuffer );
-		pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+		pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
 
 		if( pxNewTimer != NULL )
 		{
-			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+			/* Timers can be created statically or dynamically so note this
+			timer was created statically in case it is later deleted.  The
+			autoreload bit may get set in prvInitialiseNewTimer(). */
+			pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
 
-			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-			{
-				/* Timers can be created statically or dynamically so note this
-				timer was created statically in case it is later deleted. */
-				pxNewTimer->ucStaticallyAllocated = pdTRUE;
-			}
-			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
 		}
 
 		return pxNewTimer;
@@ -369,10 +366,13 @@ static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e97
 		parameters. */
 		pxNewTimer->pcTimerName = pcTimerName;
 		pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
-		pxNewTimer->uxAutoReload = uxAutoReload;
 		pxNewTimer->pvTimerID = pvTimerID;
 		pxNewTimer->pxCallbackFunction = pxCallbackFunction;
 		vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
+		if( uxAutoReload != pdFALSE )
+		{
+			pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+		}
 		traceTIMER_CREATE( pxNewTimer );
 	}
 }
@@ -392,7 +392,7 @@ DaemonTaskMessage_t xMessage;
 		/* Send a command to the timer service task to start the xTimer timer. */
 		xMessage.xMessageID = xCommandID;
 		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
-		xMessage.u.xTimerParameters.pxTimer = ( Timer_t * ) xTimer;
+		xMessage.u.xTimerParameters.pxTimer = xTimer;
 
 		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
 		{
@@ -432,16 +432,36 @@ TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
 
 TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
 {
-Timer_t *pxTimer = ( Timer_t * ) xTimer;
+Timer_t *pxTimer = xTimer;
 
 	configASSERT( xTimer );
 	return pxTimer->xTimerPeriodInTicks;
 }
 /*-----------------------------------------------------------*/
 
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload )
+{
+Timer_t * pxTimer =  xTimer;
+
+	configASSERT( xTimer );
+	taskENTER_CRITICAL();
+	{
+		if( uxAutoReload != pdFALSE )
+		{
+			pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+		}
+		else
+		{
+			pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD;
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
 TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
 {
-Timer_t * pxTimer = ( Timer_t * ) xTimer;
+Timer_t * pxTimer =  xTimer;
 TickType_t xReturn;
 
 	configASSERT( xTimer );
@@ -452,7 +472,7 @@ TickType_t xReturn;
 
 const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 {
-Timer_t *pxTimer = ( Timer_t * ) xTimer;
+Timer_t *pxTimer = xTimer;
 
 	configASSERT( xTimer );
 	return pxTimer->pcTimerName;
@@ -462,7 +482,7 @@ Timer_t *pxTimer = ( Timer_t * ) xTimer;
 static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
 {
 BaseType_t xResult;
-Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 
 	/* Remove the timer from the list of active timers.  A check has already
 	been performed to ensure the list is not empty. */
@@ -471,7 +491,7 @@ Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTi
 
 	/* If the timer is an auto reload timer then calculate the next
 	expiry time and re-insert the timer in the list of active timers. */
-	if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
+	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 	{
 		/* The timer is inserted into a list using a time relative to anything
 		other than the current time.  It will therefore be inserted into the
@@ -491,6 +511,7 @@ Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTi
 	}
 	else
 	{
+		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 		mtCOVERAGE_TEST_MARKER();
 	}
 
@@ -499,7 +520,7 @@ Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTi
 }
 /*-----------------------------------------------------------*/
 
-static void prvTimerTask( void *pvParameters )
+static portTASK_FUNCTION( prvTimerTask, pvParameters )
 {
 TickType_t xNextExpireTime;
 BaseType_t xListWasEmpty;
@@ -747,11 +768,12 @@ TickType_t xTimeNow;
 			switch( xMessage.xMessageID )
 			{
 				case tmrCOMMAND_START :
-			    case tmrCOMMAND_START_FROM_ISR :
-			    case tmrCOMMAND_RESET :
-			    case tmrCOMMAND_RESET_FROM_ISR :
+				case tmrCOMMAND_START_FROM_ISR :
+				case tmrCOMMAND_RESET :
+				case tmrCOMMAND_RESET_FROM_ISR :
 				case tmrCOMMAND_START_DONT_TRACE :
 					/* Start or restart a timer. */
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
 					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
 					{
 						/* The timer expired before it was added to the active
@@ -759,7 +781,7 @@ TickType_t xTimeNow;
 						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 						traceTIMER_EXPIRED( pxTimer );
 
-						if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 						{
 							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
 							configASSERT( xResult );
@@ -778,12 +800,13 @@ TickType_t xTimeNow;
 
 				case tmrCOMMAND_STOP :
 				case tmrCOMMAND_STOP_FROM_ISR :
-					/* The timer has already been removed from the active list.
-					There is nothing to do here. */
+					/* The timer has already been removed from the active list. */
+					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 					break;
 
 				case tmrCOMMAND_CHANGE_PERIOD :
 				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
 					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
 					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
 
@@ -797,29 +820,28 @@ TickType_t xTimeNow;
 					break;
 
 				case tmrCOMMAND_DELETE :
-					/* The timer has already been removed from the active list,
-					just free up the memory if the memory was dynamically
-					allocated. */
-					#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
-					{
-						/* The timer can only have been allocated dynamically -
-						free it again. */
-						vPortFree( pxTimer );
-					}
-					#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
 					{
-						/* The timer could have been allocated statically or
-						dynamically, so check before attempting to free the
-						memory. */
-						if( pxTimer->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+						/* The timer has already been removed from the active list,
+						just free up the memory if the memory was dynamically
+						allocated. */
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
 						{
 							vPortFree( pxTimer );
 						}
 						else
 						{
-							mtCOVERAGE_TEST_MARKER();
+							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 						}
 					}
+					#else
+					{
+						/* If dynamic allocation is not enabled, the memory
+						could not have been dynamically allocated. So there is
+						no need to free the memory - just mark the timer as
+						"not active". */
+						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					}
 					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
 					break;
 
@@ -848,7 +870,7 @@ BaseType_t xResult;
 		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
 
 		/* Remove the timer from the list. */
-		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
+		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 		traceTIMER_EXPIRED( pxTimer );
 
@@ -857,7 +879,7 @@ BaseType_t xResult;
 		have not yet been switched. */
 		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 
-		if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 		{
 			/* Calculate the reload value, and if the reload value results in
 			the timer going into the same timer list then it has already expired
@@ -944,28 +966,32 @@ static void prvCheckForValidListAndQueue( void )
 
 BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
 {
-BaseType_t xTimerIsInActiveList;
-Timer_t *pxTimer = ( Timer_t * ) xTimer;
+BaseType_t xReturn;
+Timer_t *pxTimer = xTimer;
 
 	configASSERT( xTimer );
 
 	/* Is the timer in the list of active timers? */
 	taskENTER_CRITICAL();
 	{
-		/* Checking to see if it is in the NULL list in effect checks to see if
-		it is referenced from either the current or the overflow timer lists in
-		one go, but the logic has to be reversed, hence the '!'. */
-		xTimerIsInActiveList = ( BaseType_t ) !( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) ); /*lint !e961. Cast is only redundant when NULL is passed into the macro. */
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
+		{
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			xReturn = pdTRUE;
+		}
 	}
 	taskEXIT_CRITICAL();
 
-	return xTimerIsInActiveList;
+	return xReturn;
 } /*lint !e818 Can't be pointer to const due to the typedef. */
 /*-----------------------------------------------------------*/
 
 void *pvTimerGetTimerID( const TimerHandle_t xTimer )
 {
-Timer_t * const pxTimer = ( Timer_t * ) xTimer;
+Timer_t * const pxTimer = xTimer;
 void *pvReturn;
 
 	configASSERT( xTimer );
@@ -982,7 +1008,7 @@ void *pvReturn;
 
 void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
 {
-Timer_t * const pxTimer = ( Timer_t * ) xTimer;
+Timer_t * const pxTimer = xTimer;
 
 	configASSERT( xTimer );
 
diff --git a/Middlewares/Third_Party/FreeRTOS/links_to_doc_pages_for_the_demo_projects.url b/Middlewares/Third_Party/FreeRTOS/links_to_doc_pages_for_the_demo_projects.url
deleted file mode 100644
index cfd5526f7..000000000
--- a/Middlewares/Third_Party/FreeRTOS/links_to_doc_pages_for_the_demo_projects.url
+++ /dev/null
@@ -1,5 +0,0 @@
-[{000214A0-0000-0000-C000-000000000046}]
-Prop3=19,2
-[InternetShortcut]
-URL=http://www.freertos.org/a00090.html
-IDList=
diff --git a/Middlewares/Third_Party/FreeRTOS/readme.txt b/Middlewares/Third_Party/FreeRTOS/readme.txt
deleted file mode 100644
index e69de29bb..000000000
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Binary/BLE_HeartRate.hex b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Binary/BLE_HeartRate.hex
new file mode 100644
index 000000000..b2d8eeab9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Binary/BLE_HeartRate.hex
@@ -0,0 +1,1070 @@
+:020000040800F2
+:10000000F814002095410008953F0008973F00082C
+:10001000993F00089B3F00089D3F0008000000003A
+:100020000000000000000000000000009F3F0008EA
+:10003000A13F000800000000A33F0008A53F000802
+:10004000B1410008B5410008B9410008E33F00088C
+:10005000BD410008C1410008D13F0008C54100086A
+:10006000C9410008CD410008D73F0008D141000830
+:10007000D5410008D9410008A93F0008DD4100082A
+:10008000E1410008E5410008E9410008ED410008B0
+:10009000F1410008F5410008F9410008DD3F000882
+:1000A000FD4100080142000805420008094200081D
+:1000B0000D420008114200081542000819420008CC
+:1000C0001D4200082142000825420008294200087C
+:1000D000AF3F0008B53F0008000000002D420008B7
+:1000E0003142000835420008394200083D4200080C
+:1000F000EB3F0008E73F0008414200084542000886
+:1001000049420008000000004D420008514200082A
+:1001100055420008594200085D420008614200084B
+:100120006542000869420008BB3F00086D420008B4
+:100130007142000875420008794200084FF0B04053
+:10014000006800F0F000B02888BFB02070472DE9AB
+:10015000F041040051D0207881064FF0B04535D5EC
+:10016000A868E96810F00C0001F0030103D00C2826
+:1001700008BF012943D12868800702D5E06900281B
+:100180003BD0FFF7DBFF616A884207D2084600F0E8
+:10019000B7FB002831D100F075FA0FE0286820F095
+:1001A000F000014329606968206A21F47F4141EA37
+:1001B00000216960606A00F0A3FBF0B900F043FC25
+:1001C000DFF8D407006800F0CDFCB0B92078C10793
+:1001D0000DD5A868E96800F00C00082801F00301BB
+:1001E00003D00C2808BF03292CD12868800340F1D4
+:1001F00040816068002840F03C8101203BE2E069DA
+:1002000080B1296841F0010100F026FB064628680C
+:10021000800700F12B8100F0C7FC801B0328F6D378
+:10022000032028E228684008400000F0CBFB064687
+:10023000286800F023FAC9D000F0B6FC801B032820
+:10024000F6D3EDE76068B0F5803F06D0B0F5A02F9B
+:10025000296807D141F480212960286840F4803062
+:10026000286006E021F4803129602A6822F4802287
+:100270002A60606860B100F097FC06462868800339
+:1002800000F1F78000F090FC801B6528F6D3C7E7EB
+:1002900000F08AFC06462868400C10F0010000F0CF
+:1002A000E88000F081FC801B6528F4D3B8E700F0FB
+:1002B0007BFCC01B0328C0F01081B1E7E06878B177
+:1002C000296841F4807100F0C7FA064628684005A5
+:1002D00000F1168100F068FC801B0328F6D39FE72D
+:1002E000286820F4807000F06DFB06462868800ABC
+:1002F00010F0010000F0DB8000F056FC801B0328AA
+:10030000F4D38DE700F050FCC01B0328C0F00A8135
+:1003100086E740F0010000F0C6F9074670688007E4
+:1003200000F11B8100F040FCC01B0328F6D377E7E7
+:10033000706820F0040000F0B6F907467068C00845
+:1003400010F0010000F0188100F02EFCC01B042802
+:10035000F4D365E70528306806D140F0040030602A
+:10036000316841F0010105E040084000306031682B
+:1003700021F004013160A06841F2893768B100F0D2
+:1003800013FC80463068800700F10B8100F00CFC04
+:10039000A0EB0800B842F5D342E700F005FC804628
+:1003A000306800F06BF900F0FC8000F0FDFBA0EB82
+:1003B0000800B842F4D333E700F0F6FBC01B032873
+:1003C000C0F0FD802CE7B06840084000B06000F04D
+:1003D000EBFB0746B06800F051F900F0F48000F044
+:1003E000E3FBC01B0328F5D31AE700F0DDFB801BFD
+:1003F0000328C0F01A8113E700F0D6FB001B032886
+:10040000C0F034810CE7286881010CD4296841F0E0
+:1004100080712960E86840F08050E86000F0C4FB1B
+:1004200004462868810100F1258100F0BDFB001B16
+:100430000328F6D3F4E60C2930D0286820F0807029
+:100440002860E96889088900E960E86820F0805040
+:10045000E86000F0A9FB04462868810140F10A81A8
+:1004600000F0A2FB001B0328F6D3D9E600F00AF93E
+:10047000ACE6207881071AD5A868E96800F00C007E
+:10048000042801F0030104D00C2808BF02297FF4DE
+:1004900015AF2868400503D5E06800283FF4ADAEED
+:1004A0006968206921F0FE4141EA006169602168C4
+:1004B000DFF8E86411F0180F38D0606900283FF4C5
+:1004C00037AFC90670687FF524AF800709D470681C
+:1004D00040F0010000F0E7F80746706880077FF5FC
+:1004E000E6AE706840F0040000F0DDF80746706882
+:1004F00000070DD400F058FBC01B0428F7D38FE68B
+:100500006868216920F0FE4040EA01606860CEE73B
+:100510007068A16920F4706040EA0120706000F00A
+:10052000BFF8074600F0A9F87FF4ECAE2078410749
+:1005300037D5DFF86C743868C10529D400F03AFB70
+:1005400000F032FB80463868C10521D400F02CFB56
+:10055000A0EB08000328F6D362E6706820F00400E0
+:1005600070607068C00810F00100DFD000F01CFB64
+:10057000C01B0428F5D353E600F092F8074600F0BC
+:100580007CF8D3D000F010FBC01B0328F7D347E65C
+:10059000A06801287FF4DEAE306840F001003060D2
+:1005A000E9E6217848060ED5A06A00283FF40BAF93
+:1005B000B16841F00101B16000F0F6FA0746B06899
+:1005C00080077FF5F9AEE06A002853D0A968EA6891
+:1005D000022801F00C017FF42EAF236B02F0030020
+:1005E000984202BF02F07000636B984214D1A36B73
+:1005F000C2F30620984202BF02F47810E36B9842DF
+:100600000AD1236C02F06060984202BF02F060429F
+:10061000606C82423FF4F7AE0C293FF4EEAD2868DF
+:1006200020F0807000F0CEF90646296888013FF579
+:10063000DCAEE968DFF86C03A26B0140206B01437C
+:10064000606B0143E06B41EA02210143206C0143EE
+:10065000606C0143E960286840F080702860E968B8
+:1006600041F08051E96000F09FFA0446286881015A
+:100670007FF5C2AE0020BDE8F0817068400810F040
+:10068000010070472968606A21F0F0010143296088
+:100690006868216A20F47F4040EA01206860704762
+:1006A000706840084000706000F07EBA2DE9F843A1
+:1006B0000400884644D0DFF8F06200F0C8F847D262
+:1006C00000F0CDF8074600F0C2F841D000F06CFA17
+:1006D000C01B0228F7D90320B7E000F065FA401BE1
+:1006E000022843D9F7E700F05FFAA0EB09000228DF
+:1006F0004CD9F0E700F058FAA0EB0900022854D9D1
+:10070000E9E700F051FA401B02285DD9E3E700F069
+:100710004BFA401B022867D9DDE700F045FA401B81
+:10072000484577D3D7E7032802D13968890103E028
+:100730000028396802D1890762D401E049055FD4F5
+:10074000012082E000F030FAC01B022872D9C2E713
+:10075000207881074FF0B0470BD5B968A06821F029
+:10076000F0010143B96000F01FFA0546B868C00304
+:10077000B3D52078DFF81C5281060AD52968606954
+:1007800021F0F001014300F067F8814628688003FA
+:10079000A9D5207841060BD52968A0690909090166
+:1007A00041EA101100F058F881462868C003A1D52D
+:1007B000207841070BD5B968E06821F4E061014376
+:1007C000B96000F0F1F90546B868800399D5207842
+:1007D00001070CD5B868216920F4605040EAC100D7
+:1007E000B86000F0E1F90546B86840038FD520787D
+:1007F000C10717D56068022895D1396889039FD54C
+:10080000B968890840EA8100B86041F2893900F08E
+:10081000CBF90546B868616800F00C00B0EB810FB9
+:100820007FF47BAF306800F00700804505D200F010
+:1008300016F8074600F00BF884D100F004F900F038
+:10084000D5F9BDE8F24300F08DB9BDE8F283306818
+:1008500000F0070040457047296000F0A5B93168F5
+:10086000C90848EAC101316000F09EB938B54FF0BF
+:10087000B0444F4DA16811F00C0106D1FFF75EFCAA
+:10088000C0F3031055F8200032BD0429494A05D0B1
+:100890000829494804D12168C90222D5104632BD31
+:1008A000E16801F00301022904D0032904D1216881
+:1008B000C90207D5104605E0FFF740FCC0F303105E
+:1008C00055F82000E168E268E368C1F30621484377
+:1008D000C2F30211491C5B0FB0FBF1F05B1CB0FBD3
+:1008E000F3F032BD80B5FFF7C1FF3049FFE7334A6F
+:1008F0000968C1F3031152F82110B0FBF1F002BDF9
+:1009000070B52B49B1282EBFCC6AC0F3031051F843
+:1009100020402048056800F087F92849284A05F05A
+:100920000F0551F82510B4FBF1F10024B1FBF2F1F1
+:10093000B0F5007F0FF2B002204609D10FF28C0310
+:1009400053F820508D4214D2401C0328F8D912E0ED
+:100950000FF2880353F820508D420AD2401C03281E
+:10096000F8D308E000F020F9801B03280BD3032004
+:1009700070BD52F820400C4D2868C00844EAC00001
+:1009800000F020F80646296801F00701A142E9D1EC
+:10099000002070BD0801005854000020900000584D
+:1009A000000400588C80C111004000580800005815
+:1009B000240B00080024F4000048E801E40A0008C1
+:1009C00040420F00286000F0EFB800001200000065
+:1009D0002400000036000000400000000600000077
+:1009E0000C000000100000000000000001000000EA
+:1009F00002000000030000003249002008604FF4AC
+:100A0000E0223148016841F4700101604FF0B041CB
+:100A1000086840F0010008608A602C480A680240BB
+:100A20002B480A60036823F00503036042685208FC
+:100A30005200426000222748C860086820F48020E5
+:100A400008608A6170474FF0B0410FF2D8000A6821
+:100A5000C2F3031250F822008A6802F00C02042A42
+:100A600004D0082A04D00C2A04D01CE01A481AE04A
+:100A70001A4818E0CA68CB68C3F3021302F00302F5
+:100A80005B1C022A08BF144802D0032A08BF13487F
+:100A9000B0FBF3F2C868CB68C0F306205B0F42439B
+:100AA0005B1CB2FBF3F00E4A0FF23803106088684B
+:100AB0001168C0F3031053F82000B1FBF0F0106090
+:100AC0007047000008ED00E088ED00E0FBFEF6FA5C
+:100AD00094000058001004220024F4000048E801AB
+:100AE0005C00002001000000030000000500000081
+:100AF0000100000001000000060000000A000000E4
+:100B000020000000020000000400000008000000B7
+:100B10001000000040000000800000000001000004
+:100B200000020000A0860100400D0300801A0600AC
+:100B300000350C0040420F0080841E0000093D007B
+:100B400000127A000024F40000366E010048E8012B
+:100B5000006CDC020000000000000000000000004B
+:100B60000000000070B50F4E0446B0680025A8B123
+:100B7000FFF7B8FEB2684FF47A71B1FBF2F1B0FB47
+:100B8000F1F000F0ACF848B9102C07D20022214651
+:100B90004FF0FF3000F06CF8746000E0012528464B
+:100BA00070BD00BF5000002001480068704700BFC2
+:100BB000500000200248016841F4807101607047D4
+:100BC00000040058154810B5016841F480710160B7
+:100BD000032000F040F80020FFF7C4FF00240028A5
+:100BE00014BF012400F0B8F8204610BD0C4840683E
+:100BF00070470B48806870470A48016849084900F7
+:100C0000016070470748016821F0020101607047E8
+:100C10000448016821F00401016070470040005859
+:100C200050000020042004E0DFF80800006800F411
+:100C3000C0607047000400580901020081B002D46E
+:100C40003C48815405E03C4802F00F02104400F893
+:100C5000041C01B07047394A13684FF6FF010002C7
+:100C60000B4000F4E06018433549084310607047BA
+:100C700038B5324B1C68C4F30223C3F10704052CBA
+:100C800028BF04241D1D072D34BF0023DB1E0125B2
+:100C900005FA04F4641E2140994005FA03F35B1E33
+:100CA0001A401143BDE83440C6E7010007D40122D1
+:100CB00000F01F01234B8A40400943F82020704771
+:100CC00001000BD4012200F01F011F4B8A40400994
+:100CD00043F82020BFF34F8FBFF36F8F704710B5DD
+:100CE000401EB0F1807F01D3012010BD174C606021
+:100CF0000F214FF0FF30FFF79FFF0022A260072077
+:100D00002060002010BD010007D4012200F01F0167
+:100D10000F4B8A40400943F820207047010007D458
+:100D2000012200F01F010B4B8A40400943F82020AC
+:100D30007047000000E400E018ED00E00CED00E07A
+:100D40000000FA0500E100E080E100E010E000E0D2
+:100D500000E200E080E200E0134881B0016841F465
+:100D600000210160006800F400200090009801B0AC
+:100D7000704710B504460D492068884213D1FFF72B
+:100D800019FFFFF717FF0A48016821F4407141F489
+:100D900080710160026842F4004202602046BDE8B2
+:100DA000104000F013B810BD50000058002800405B
+:100DB000900000588A60FF2102685162012180F88A
+:100DC0002110002180F820100020704790F820109A
+:100DD000012901D102207047012280F82020022140
+:100DE00080F82110CA2102685162532103685962B8
+:100DF00001688A6842F02002FFF7DCBFDFF83C158B
+:100E00000A6892B200E00246086880B28242FAD1D3
+:100E100070472DE9FC4104461825DFF82485DFF8EA
+:100E20002465684308EB00073078062808D131783C
+:100E30007170347078754FF0FF307060002039E0C9
+:100E400000F077F8B9680918B96008F10803B968C3
+:100E500032786A439A589142327813D308F11503D5
+:100E600015FB02FC13F80C30062B25D008F1080600
+:100E70006B43F358994222BF08F115036A439A5C09
+:100E8000EED219E01146337869439A420BD008F14B
+:100E9000140308F1150C5B5C15FB03F50CF8054019
+:100EA0007A753B7500E07A7508F114025454317874
+:100EB00071703470BDE8F6811146694308F115037D
+:100EC0005B5C062B04D008F1140615FB03F5745582
+:100ED0007B753A7508F115025454EBE7F8B5DFF865
+:100EE0006434DFF85C541E78182402466243B04232
+:100EF0002A4404D118785870507D18700FE0167D80
+:100F0000507D92F815C005F115076643062807F8CD
+:100F100006C004D0167D143514FB00F42E550120B4
+:100F200010731878062802BF00294FF0FF3159606E
+:100F3000F1BD10B5DFF80C44606810F1010F0FD05F
+:100F4000FFF75CFF6168DFF80024814261683CBF05
+:100F50005388C918081A517848431178C84000E0EE
+:100F6000002080B210BD2DE9F84FDFF8DC53DFF828
+:100F7000DCB3D5F80880D8F80000DBF800104A058B
+:100F800000F090F9DFF8BC63DFF8B4A321F48061CE
+:100F900081604FF0180934780AF1080019FB04F158
+:100FA0004758FFF7C6FF874217D200270121B170CB
+:100FB000062C3DD019FB04F40AF108010AF10802DD
+:100FC0000959814223BF0AF108010959091A002170
+:100FD00011510AEB04014C7DEAE7A9884118B94296
+:100FE00002D2AF880021E2E73F1ADFE7022802DAE7
+:100FF0002878012800D07F1ED8F80000C1684A0771
+:10100000FAD500F055F9DBF80C00000CBFB247EA46
+:101010000047CBF80C70FFF7F1FE7060A86800681D
+:10102000816841F480618160AFF30080BDE8F18F99
+:10103000B8B20028DAD1FFF7E1FE70600320BDE806
+:10104000F24FFFF760BE2DE9F843EFF3108872B658
+:10105000BD4DBB4BA8680168CA224A625320486252
+:10106000B84A886820F4806088601820167837466F
+:1010700047431F44387B022826D13C68D7F810909C
+:101080009078F0B17A7B012A0AD101213046FFF72E
+:1010900025FF88F310887968304600F016F904E0DF
+:1010A00088F31088304600F0C1F8A8680068CA21AB
+:1010B00041622246532141624846314600F050F9D0
+:1010C0000BE0FFF750FF06E0C8684207FCD500F0D0
+:1010D0007EF89F49086088F31088FF21A86802689D
+:1010E0005162BDE8F183F8B5974CA160CA22096846
+:1010F0004A6253224A62954A136843F02003136000
+:10110000136803F00703C3F10403237095682D0CE3
+:1011100005F07F056D1C6570EDB29268C2F30E029A
+:10112000521C628092B2521E6A43A2F5A072DA404B
+:101130004FF6FF739A422CBFA380A280854A1368A2
+:1011400043F400231360844B1D6845F400251D60A3
+:1011500048BB7C487A4E0123837018254FF0FF333B
+:10116000436000235FFA83FC06F10C0715FB0CFCBF
+:101170004FF0000E07F80CE05B1CDFB2062FF1DB2E
+:1011800006230370886820F48060886000F01FF8F0
+:10119000D0600320FFF7C2FDA1680868826842F4AE
+:1011A0008042826005E0C868410544BF0320FFF724
+:1011B000AAFDA1680A68FF205062002203210320D3
+:1011C000FFF756FDBDE8F2400320FFF76EBDC8688B
+:1011D00000F0800060F49060C8604FF40020704719
+:1011E000F0B504460025EFF3108672B61827DFF835
+:1011F00050C10CF10C0007FB05FE10F80E0010B1F9
+:101200006D1C062DF5DB062D0CD06F430CEB070093
+:101210000127077386F310880461427303600D7021
+:101220000020F0BD86F310880120F0BDF8B5074618
+:10123000EFF3108472B60320FFF742FD424DAE6813
+:101240003068CA2141623A4653214162182043491D
+:101250004243895C02291BD100213846FFF73EFE3C
+:101260003848017806290ED1306838490A68530594
+:1012700000F018F821F480618160C1684A07FCD54C
+:1012800000F016F804E04078884218BFFFF76BFEC4
+:10129000A9680A68FF2050620320FFF706FD84F367
+:1012A0001088F1BD02D5C1684A07FCD48168704737
+:1012B000C16801F0800161F49061C1604FF40020C9
+:1012C000234908600320FFF729BD2DE9F04180463E
+:1012D0000F46424618201A4942438C18207B0228A8
+:1012E00004BF4046FFF7A2FFEFF3108572B603205C
+:1012F000FFF7E6FC144EB0680068CA214162532132
+:10130000416202202073A76067604046FFF781FDBD
+:101310000C490A784978914202D0FFF724FE02E096
+:10132000A168081AA060FF20B1680A685062032013
+:10133000FFF7BBFC85F31088BDE8F081282800404A
+:10134000FC000020DC040020A80400200828004045
+:101350000C080058000800588008005808010020B8
+:101360001047000038B58EB002A80FF21C41DFF81C
+:101370006C43DFF86C53302200F02EFA0FF2B930D4
+:101380000190009469460FF2993000F069FA01214A
+:10139000022000F04EFBD34A0021042000F0DFFBC6
+:1013A00002A800F05BFC00F0A0F800F067FC002051
+:1013B00085F8900005F126044FF6FF70208000218B
+:1013C0000FF24532012000F0CAFB00F0B9FC00F03A
+:1013D000E0FC0FF22D33002205F191010020FFF710
+:1013E000FFFE0220E07080210120A0700D202071FE
+:1013F0000220A070182060710320A070BA480180FC
+:10140000A0214180012000F024F90FB030BD7CB54F
+:101410000646B34D7078052805F1900404D03E28A7
+:101420000DD0FF2824D03AE0B088E98C884202D160
+:101430000020E8842070012000F00BF92FE0F17803
+:10144000012908D00C292AD1E88C6A460DF1010146
+:1014500000F01BFD23E06078FFF7E8FE2078042809
+:101460000CBF062005202070B6F80500E88416E0C1
+:10147000B6F8030040F20241401A08D0C01E0BD05B
+:10148000001F02BF0121E88C00F039FF07E0E88C63
+:10149000964900F024FE02E0E88C00F0D8FE01201E
+:1014A00076BD00F0C2BE8E48C08C00F065BE1CB593
+:1014B0008B4CE08C01AA0DF1050100F0E6FC98B917
+:1014C0009DF80500022804BF9DF80410022903D1ED
+:1014D00000200090012302E0002000900223E08C15
+:1014E0001A46002100F02CFD13BD78B50FF25C20E8
+:1014F0007F4D00887F4E89B0ADF81A0000F090FC57
+:10150000286810F1010F0ED069683074090A020AC8
+:10151000000CB074727406F1100468683175F074D0
+:10152000090A717506E0002000F004FF040008BFFE
+:101530000FF2242422460621002000F00DFF6079DE
+:101540003072102120797072E078B072A078F07259
+:101550006078307320780FF20824707322461820C8
+:1015600000F0FAFE0FF2082600F06EF84EF66E500C
+:10157000089007AA2868079006212E2000F0ECFEAC
+:1015800022461021182000F0E7FE00F05DF8182137
+:10159000012000F008FF00F031FF0DF1160006A950
+:1015A0000190009105AB07220021012000F0B4FD5D
+:1015B0000FF29C10BDF81810494C00900723BDF89D
+:1015C0001400002200F0DAFF0DF11A00009002234F
+:1015D000BDF81610BDF81400002200F0CFFF022263
+:1015E0000221002000F084FC0120207000F02BFD7F
+:1015F000012060700020E070082060751020A07548
+:10160000012020753C48A0610120A0700020C1B2DB
+:1016100021440871401CC1B21029F8DB002004905D
+:101620000023A069617803900122207D0290A07DB3
+:101630000190607D0090A07800F01EFDA07808B1B8
+:1016400000F0D8FD0AB070BD32461021082000F02D
+:1016500083BE2DE9F8420746012F87B003D1224807
+:101660000588468803E04FF4C8654FF47A66DFF8D2
+:10167000709009F190046078FFF7D8FD022F05D132
+:101680002078012814BF022800F082FC2770002077
+:101690000690059009F129010491062299F8280085
+:1016A0000FF2DC0103900291019200230093324675
+:1016B0002946002000F07EFC0E490E2000F072FD4D
+:1016C000002808BF012F06D160780C4908B0BDE89A
+:1016D000F042FFF7FABD08B0BDE8F082AC88002008
+:1016E000680000209F180008EC04002040E2010080
+:1016F0008075FF1F0400002007B2010046E00100D2
+:101700000021012000F038BA0220A2E700210420C5
+:1017100000F032BA012000F051BA012000F056BAB0
+:1017200010B50446616801F1080000F0B7FA00B195
+:101730000120207010BD000010B1012803D07047B7
+:10174000072000F029BA072000F02EBA400300005D
+:1017500053544D33325742006C7AD8AC5772000064
+:10176000123456789ABCDEF0123456789ABCDEF009
+:10177000FEDCBA0987654321FEDCBA09876543218F
+:1017800009485253544D00000000000000000000C2
+:1017900000000000000000000000000044000800FD
+:1017A000400508013A799C00F4010000FFFFFFFFAB
+:1017B000480101000000000062B38B0708D0521EF0
+:1017C00011F8013B00F8013B00F024808B07F6D1B3
+:1017D000830740F0208000BF103A07D330B4B1E84F
+:1017E0003810103AA0E83810F9D230BC530724BFA3
+:1017F000B1E80810A0E8081044BF51F8043B40F8D5
+:10180000043BD20724BF31F8022B20F8022B44BF3F
+:101810000B7803707047121F17D35B0009D151F882
+:10182000043B20F8023B1B0C121F20F8023BF6D2AF
+:101830000BE051F8043B00F8013B1B0A20F8023B87
+:101840001B0C121F00F8013BF3D238BF121D521EB1
+:1018500024BF11F8013B00F8013BF8D870470000A5
+:101860007FB50C466D4D61686D4EE8612962284672
+:1018700000F0F0FE246805F1240000F0F5FE74602D
+:1018800006F1080000F0F0FE01203070296829B14F
+:101890000FF2551000900294684688477FBD1FB52F
+:1018A0005F4C04F1080000F0E2FE00BB2178F1B1CA
+:1018B000694604F1080000F003FF5848C16949B1C6
+:1018C0000098029001228DF8042001A888479DF815
+:1018D000040000E001202070207818B1009800F08A
+:1018E000A2FF04E0009904F1080000F0C9FE04F131
+:1018F000080000F0BCFE28B9207818B104F10800F7
+:10190000FFF704FF1FBD2DE9F8430646002000F055
+:101910005FF874883088B268DFF80081C4F3090486
+:1019200044EA8024F068A4B2C1B2204600F03CF83A
+:10193000002748F2E8094846FFF7EFFE08E068880C
+:10194000A04202D1316928780870687800B1012777
+:1019500008F1240000F08BFEF0B9694608F124007C
+:1019600000F0AEFE009800F10B05407A0F28E6D09B
+:10197000B5F80110A1420DD10098817AC81E716995
+:10198000C0B28842C8BF0846706102463069E91C8F
+:10199000FFF712FF2878D9E73800CCD0012000F0FB
+:1019A00017F80020BDE8F28310B513461C4A5468AE
+:1019B000A4F80900E1720A46194604F10C00FFF789
+:1019C000FBFE164A1369BDE81040002100201847AD
+:1019D0001249096A82B008B921B101E011B10120B0
+:1019E00002B0084702B0704710B50146487A0F2888
+:1019F00018BF0E2807D10B4800F04CFEBDE8104080
+:101A00000020FFF787BE064C04F1080000F042FEFC
+:101A100004F10800BDE81040FFF778BEE4030020A1
+:101A2000880400200804002019480021016041605A
+:101A3000704710B500F00CF85C6819B1012904D1A9
+:101A4000204301E024EA0000586082F3108810BDB2
+:101A5000EFF3108272B60E4B704738B5EFF3108477
+:101A600072B60B490B4D086820B129688847686831
+:101A700080470AE0486820B1A9688847E86880473D
+:101A800003E0286980476869804784F3108831BD86
+:101A9000B40400207C4100082DE9FC47594CDFF8D4
+:101AA0006891A5692840A0614FF0010A4FF0FF3806
+:101AB00030E0491C54F831000642FAD004EBC1076B
+:101AC000184079681040014208BFC7F804807E685A
+:101AD000304000F09BF860620AFA00F086437E60B6
+:101AE000EFF3108172B6626A20690AFA02F2D243F9
+:101AF00010402061022004EBC00353F8086C16402C
+:101B0000401E43F8086CF6D181F31088606A59F8DA
+:101B10002010884763692069A2691840104207D0E5
+:101B2000E069216A084203D1002103EA0206C1E705
+:101B300000F0C7FEEFF3108972B6216960690140B9
+:101B4000A069014201BFE169206A014200F013FF70
+:101B500089F3108800F02CFFA561BDE8F38738B544
+:101B60001446EFF3108572B600F050F8264941F89C
+:101B7000204085F3108831BD10B5EFF3108272B6A6
+:101B8000204B1C6904431C6153F83140204343F847
+:101B9000310082F3108810BDEFF3108172B6194A3C
+:101BA000536923EA000005E0EFF3108172B6154A8D
+:101BB00053691843506181F310887047EFF3108127
+:101BC00072B6104AD3691843D061F4E72DE9F041A9
+:101BD0000C4C626A266A2062012101FA02F803E0D5
+:101BE0003946404600F0C9FE276AE5693D42F7D014
+:101BF000404600F00BF825EA0707E76126626062BD
+:101C0000BDE8F08128000020A40200200246002048
+:101C1000110C090404BF1020120412F07F4F04BFFE
+:101C2000083012020FF2180112F0704F04BF001DAD
+:101C30001201120FC0F11F00895C401A70470000AA
+:101C40000403020201010101000000000000000085
+:101C500000F005FF9DF80E0005B000BDF8B500F1DD
+:101C60000C026B4621214FF66640F1E7F8B500F112
+:101C70000C026B460F214FF66840E9E71C49002033
+:101C8000087700221B48027000F036B818490A7F16
+:101C900041F82200087F401C0877704770B5044661
+:101CA0006078FF2802BFB4F8031001F47F41B1F55A
+:101CB000406F12D100260E4D00E0761C297FF0B255
+:101CC00088420AD2F1B255F8211020468847010017
+:101CD000F3D002D0022805D006E02046BDE87040CF
+:101CE000FFF795BB002070BD012070BD0000000013
+:101CF00058040020F404002080B500F0FFFE00F03E
+:101D0000FEFE00F0FDFE00F035FF00F034FF00F0B5
+:101D1000B1FF01F015F801F014F801F013F801F02B
+:101D200012F801F011F801F010F801F00FF801F0CD
+:101D30000EF801F00DF8BDE8014001F00AB800000E
+:101D4000E0B505A0042100908DF8041042F629208A
+:101D5000694600F0FCFE07BD53544D0010B50078F5
+:101D60002B4C18B102280FD004D310BDA080012045
+:101D7000207310BD607BFFF759FA607BBDE810400F
+:101D800040F60101FFF7A1BA607BBDE81040FFF704
+:101D90004DBA10B50FF2450200210220FFF7DFFE19
+:101DA0001B4C0021042021732070214642F638206C
+:101DB00000F0ABFF1F20E07204F10D010A20A080AB
+:101DC0000120A0724FF48060E0800122BDE8104045
+:101DD0000FF245030020FFF703BA00000D480C493D
+:101DE0000068CA7A00F00700413048801307087B7A
+:101DF00004D518B98888401D888003E0012804BFF5
+:101E000000200873891C42F6372000F07EBF0000D6
+:101E1000780400202828004000210220FFF7ACBEF3
+:101E200000B587B000F010F8012003220690ADF84D
+:101E30000420ADF8062000F0A5F800284CBFFF20D4
+:101E40009DF8000007B000BD00208DF800001822AA
+:101E5000002101A800F084BFADF80600049107A896
+:101E60000121082203900691ADF804207047092251
+:101E70000021684600F074BF1822002102A800F07B
+:101E80006FBF182201A800F06BBF70B5C8B006463E
+:101E90000C4615460522FFF7EBFFADF82060FFF773
+:101EA000EBFF302100F014F80521049000F019F840
+:101EB000002848BFFF2009D49DF8000030B99DF8E4
+:101EC000030020709DF804002870002048B070BD09
+:101ED000ADF80A1008200221ADF80800059108A805
+:101EE00070470791CDF818D0002102A8FFF70BBD6D
+:101EF00000B5C7B000F00EF8FFF7C3FF312000F0C7
+:101F000013F800F03FF800284CBFFF209DF80000B8
+:101F100047B000BD00238DF81C008DF8003007A8E5
+:101F20004170827000217047ADF8060007A90320B8
+:101F300004900822012003910690ADF80420704718
+:101F400030B5C7B00025ADF81C008DF81F2007A8DC
+:101F50004A9C817003718DF80050ADF82140FFF765
+:101F600076FF0F21029132200721FFF775FF00F065
+:101F700009F800284CBFFF209DF8000047B030BD95
+:101F800003900691CDF814D0002101A8FFF7BBBC47
+:101F900000B587B000F045F900F073F9812000F03A
+:101FA0003BF900F085F900284CBFFF209DF80000A8
+:101FB00007B000BD2DE9F84DC7B09446DDF840E10B
+:101FC000519A559D569EDDF84CA1ADF81D108DF827
+:101FD0001C004FF0000BADF81FC08DF821308DF8BC
+:101FE00022E000F024F800F017F824F8095F66807A
+:101FF00000F047F93F20832100F075F9574406911E
+:102000000D37049700F057F900284CBFFF209DF8CA
+:10201000000048B0BDE8F08D88F800A007AC5499E6
+:10202000E419524608F10100544400F093BE8DF8C3
+:102030002320174652998DF800B00DF1240809A805
+:10204000B84400F087BE00B5C7B000F00CF885209A
+:1020500000F0C3F800F02CF900284CBFFF209DF8D9
+:10206000000047B000BD00218DF81C008DF8001065
+:10207000182201A800F074BE2DE9F841C7B04FF056
+:10208000000800F026F80DF12300DDF844E14E9F32
+:102090004F9E509D529C8DF81F30C0F800E08DF887
+:1020A00000808DF820708DF821608DF822508DF819
+:1020B000274000F0E6F88620ADF8060007A90C20BE
+:1020C00000F0F2F800284CBFFF209DF8000000F05F
+:1020D00024B98DF81C0007A841708270704700B5C4
+:1020E000C7B00022ADF81C008DF800200DF11E00D5
+:1020F0001822016001A8002100F032FE8820ADF80E
+:10210000060007A9062000F0CFF800284CBFFF20EA
+:102110009DF8000047B000BDF8B5C8B005460E46B2
+:1021200017461C4600F023F808A8467087708DF803
+:10213000205000F0D3F88A21ADF80A103F20032187
+:1021400000F0BFF8002848BFFF200ED49DF8000023
+:1021500058B94F994E98BDF801202280BDF8032050
+:102160000280BDF805000880002049B0F0BD0722BC
+:102170000021684600F0F4BD00B5C7B00021ADF8FD
+:102180001C00FFF773FF0F2102918D20022100F048
+:102190007EF800F08EF800284CBFFF209DF800006C
+:1021A00047B000BD18B5C7B0044600F03AF88DF846
+:1021B0001C40224600F09FF800F063F83F208E217B
+:1021C00000F0AEF8641C049400F075F800284CBFD1
+:1021D000FF209DF8000048B010BDADF8060007A92B
+:1021E00001203F22039104907047ADF8060007A933
+:1021F0000220704700B587B000F013F800F041F8F6
+:10220000922000F009F800F053F800284CBFFF209E
+:102210009DF8000007B000BDADF806003F22012088
+:10222000704700208DF80000704700B587B0FFF7B9
+:10223000F8FF00F026F89420FFF7EEFF00F038F8E2
+:1022400000284CBFFF209DF8000007B000BD00B57E
+:10225000C7B00021ADF81C00FFF708FF9520FFF77D
+:10226000C4FF00F021F800284CBFFF209DF80000BB
+:1022700047B000BD00228DF80020ADF81C008DF89D
+:102280001E101822002101A800F06ABD0321ADF83C
+:102290000600049107A801213F2203900691704790
+:1022A000ADF8060007A9032004903F220120039106
+:1022B0000690ADF80420CDF814D0002101A8FFF756
+:1022C00022BBADF80800059108A8072104900791EA
+:1022D000CDF818D0002102A8FFF715BB1822002165
+:1022E00002A800F03DBDADF80400ADF8061007A847
+:1022F0000121039070470DF11D0000F02BBD00B5CA
+:10230000C7B0FFF7B7FFA520FFF7CAFF00284CBFF3
+:10231000FF209DF8000047B000BD48B0BDE8F08147
+:10232000ADF80400ADF8061007A80121039006914E
+:102330007047000001460648064AC3798B4218BF21
+:10234000904218BF0838F8D18B4218BF0020704760
+:10235000F873FF1F0070FF1F18B50C46C7B0114679
+:1023600000228DF800208DF81C008DF81D402246BB
+:102370000DF11E0000F0EEFC00F02AF83F200C21C9
+:10238000ADF80400ADF8061007A8012103900691EE
+:10239000A41C049400F02CF800284CBFFF209DF8EA
+:1023A000000048B010BD00B5C7B000F00AF80F201B
+:1023B00000F013F800284CBFFF209DF8000047B044
+:1023C00000BD00228DF800208DF81C008DF81D1036
+:1023D0001822002101A800F0C3BCADF8060007A92F
+:1023E000022004903F22012003910690ADF80420C2
+:1023F000CDF814D0002101A8FFF785BA00B587B049
+:1024000000208DF8000000F0E0F840F20110ADF877
+:1024100006003F220120069000F013F900284CBF6F
+:10242000FF209DF8000007B000BD2DE9F8410746E8
+:102430000128C7B0884615461E4608BF022003D0B3
+:1024400002280CBF102000200DF11D010C1800F017
+:1024500036F8012F8DF81C7002D0022F18D019E029
+:1024600002273A4641460DF11D0000F073FC25702D
+:10247000667000F0AAF83F204FF4817100F016F862
+:10248000FF1C049700F0DFF8002805D5FF2009E0C5
+:102490001027E6E7472005E09DF8000010B94E98A8
+:1024A00000F067F8FFE748B0BDE8F081ADF8040040
+:1024B000ADF8061007A80321039006917047032288
+:1024C0000021684600F04CBC2DE9F64F0C4605464D
+:1024D000012CC7B09B4608BF022003D0022C0CBFC2
+:1024E000102000200DF11F010E18FFF7E8FF012C4E
+:1024F000ADF81C508DF81E4002D0022C2CD02DE0DF
+:102500000227569C559DDDF85091DDF84CA1DDF871
+:10251000488148993A4600F054F8A6F800B086F889
+:10252000028086F803A086F804907571B47100F0FB
+:102530004CF83F20ADF804004FF4827107A8ADF8C5
+:102540000610039003210A370497069100F07BF8E8
+:10255000002805D5FF2009E01027D2E7472005E035
+:102560009DF8000010B9579800F003F849B0BDE895
+:10257000F08FBDF8011001800020704730B5C7B062
+:102580001C464A9B00F049F800258DF800508DF854
+:102590002140224619460DF1220000F0DBFB00F03D
+:1025A00014F83F204FF4837100F042F8A41D049406
+:1025B00000F049F800284CBFFF209DF8000047B00C
+:1025C00030BD0DF11F0000F0C5BB1822002101A88D
+:1025D00000F0C6BB78B5C7B04C9C4D9D00F01DF80F
+:1025E00000268DF821308DF800608DF822402246BB
+:1025F000294600F019F8FFF7E8FF3F204FF49371E8
+:1026000000F016F8E41D049400F01DF800284CBFFB
+:10261000FF209DF8000048B070BDADF81C00ADF87B
+:102620001E108DF8202070470DF1230000F092BBA2
+:10263000ADF80400ADF8061007A80121039006913B
+:102640007047ADF80420CDF814D0002101A8FFF7A1
+:102650005AB900000249016002490161704700BF98
+:10266000212700084B270008006040607047EFF307
+:10267000108172B6026882420CBF012000201CE06B
+:10268000EFF3108272B603680B604860016008685F
+:10269000416023E0EFF3108272B6086043684B603C
+:1026A00041604868016019E0EFF3108172B6436839
+:1026B00002681A6042680068426081F310887047BF
+:1026C00010B5EFF3108472B602680A600068FFE785
+:1026D000FFF7EAFF84F3108810BD086082F31088CA
+:1026E0007047000000F0BABB6C486D49016001F111
+:1026F0002002426001F13002826001F13C0202627C
+:1027000001F14402C26001F14C02026101F1680270
+:10271000426101F16C0282617831C16100F0B0BBAD
+:1027200038B504465F4D05F11000FFF79DFF5B498A
+:102730004868A1680160E168C160456005F1100169
+:10274000816000F0B9FB58482DE080B553494A68D4
+:1027500013680120187200F0B5FB002002BD38B5E7
+:10276000514C504D07E0694605F11000FFF7A8FFF6
+:1027700000982168884705F11000FFF778FF0028CE
+:10278000F1D031BD48484168084738B50446474D47
+:102790002846FFF769FF4148C068A16801604560AD
+:1027A00000F095FB424821680160616841600020AB
+:1027B00032BD80B53949CA6813681020187200F01C
+:1027C0008CFB002002BD3549CA68394910680B6886
+:1027D000184738B5364C354D06E069462846FFF7B0
+:1027E0006FFF0098616888472846FFF740FF002880
+:1027F000F3D031BD38B504462E4D2846FFF734FFDF
+:102800002D48FFF731FF25480069A1688160E16824
+:10281000C1600561216801606168416021694161B1
+:102820006169816131BD80B501462348FFF732FF00
+:10283000BDE802400FF2050000F05FBB38B5174C51
+:102840001D4D08E069462846FFF73AFF00992069C8
+:102850000069FFF71FFF2846FFF709FF0028F1D0A6
+:1028600031BD10B5154C2046FFF7FEFE0B484169FF
+:102870000C60BDE8104000F054BB1CB50F4C06E0E6
+:1028800069462046FFF71CFF009800F019F8204623
+:10289000FFF7EDFE0028F3D013BD000000800020FC
+:1028A000B88900208C880020C4040020A48800205F
+:1028B000CC0400203C8A0020BC040020448A002074
+:1028C0007047704710B52148214C88B0016841F429
+:1028D00000410160FFF7A8F81E490020FEF703FC45
+:1028E00000F043FB01210120FFF7A3F801210020A4
+:1028F00000F08BFC0121012000F087FC0121022067
+:1029000000F083FCFFF7F0FE134A00210820FFF7D8
+:1029100026F904F23C500FF24501009001916946FE
+:102920000FF23D0000F046F804F25470029004F5F6
+:10293000C96140F23C5005900391049402A8FFF74E
+:1029400059FFFFF7CFFE08B010BD00000800005887
+:102950002C80002010040020F72900087047000098
+:1029600080B500F030FBFEF7FDFCBDE8044000211F
+:102970000120FFF75EB8FFF770B84FF0FF30FFF7A8
+:102980008BB800210820FFF7F7B80220FFF716B92F
+:102990000220FFF71BB9012804D0102804D04028DA
+:1029A00004D07047FEF77DBDFEF77DBDFEF77FBD0D
+:1029B000704700007FB50C464D4D61684D4EE86193
+:1029C0002962284600F070FC2468746006F1080053
+:1029D000FFF74AFE012000F068F8012030702968F6
+:1029E00041B10FF2E9000FF2ED0200900192029462
+:1029F000684688477FBD1FB53E4C04F10800FFF7CD
+:102A000036FE00BB2178F1B1694604F10800FFF7FA
+:102A100057FE3748C16949B10098029001228DF8EC
+:102A2000042001A888479DF8040000E001202070E0
+:102A3000207818B10098FFF7F6FE04E0009904F141
+:102A40000800FFF71DFE04F10800FFF710FE28B98B
+:102A5000207818B104F10800FFF793FF1FBD2DE99E
+:102A6000F04105460E4690461C46002000F01DF839
+:102A7000204F7868A0F80950C672324641460C30A3
+:102A8000FEF79AFE1A4A136900210020984748F27F
+:102A9000E800FFF77DFF79688A78D21C04F108000E
+:102AA000FEF78AFEBDE8F04101201CB51049124C2A
+:102AB000096A20B901B188470020207013BD0120A8
+:102AC000207011B1BDE81C40084713BD0020FFF77E
+:102AD0005CBF000010B50146064C04F10800FFF78A
+:102AE000D9FD04F10800BDE81040FFF74ABF00001F
+:102AF0003404002098040020F5040020704770473B
+:102B000018B51B4C0020206087B041F60A00ADF8D4
+:102B1000180000940323012206A90120FFF785FC79
+:102B200042F629220121ADF818200491A01C05903D
+:102B30000A22002302210392029301930091202391
+:102B4000208806AA0121FFF7BFFC08B010BD80B5A0
+:102B500042F62922904209D10A68054800920022D3
+:102B60000B7941880088FFF709FD02BD002002BDF6
+:102B7000F00400207047704738B5024686B05078A0
+:102B80000024FF2839D1B2F803106B4840F6014306
+:102B9000C91A1FD0123901BFB2F80710C088401CF3
+:102BA00081422AD1957AB2F80500537A0124012D89
+:102BB00008D10A320192009300220023FFF70AFD98
+:102BC000002015E00A320192009301228023FFF7D2
+:102BD00001FD12E04088B2F80710801C81420CD140
+:102BE000507B0124C10748BF8DF8084002D4022061
+:102BF0008DF8080002A8FFF7B1F8204607B030BDF5
+:102C0000FEB5014601AA487A8DF804004B7A08887F
+:102C10005070DC0704D50888000A9070032300E098
+:102C20000223487A040707D54888D0545B1C48889B
+:102C3000DCB2000A10555B1C4C7AE00610D50D7A08
+:102C400000200BE001EB4004DFB2A688D6555B1CE8
+:102C5000A488DEB2240A94555B1C401CA842F1DB18
+:102C600001A935480091DBB2418800880022FFF7B6
+:102C700085FCFEBD18B587B030482F4CFFF706F82D
+:102C800041F60D01ADF8181000940823012206A9A1
+:102C90000120FFF7CAFB42F63720ADF818000122E9
+:102CA00004920A20A11C0390002310220591029394
+:102CB00001930092072300F023F842F63820ADF884
+:102CC000180000220492029201920A20211D039012
+:102CD0000222059100F012F842F63920ADF81800F2
+:102CE0000022049201920A20A11D039002230822CF
+:102CF0000591029300F002F808B010BD0092012384
+:102D0000208806AA0121FFF7DFBB80B5002242F62A
+:102D10003723C01A09D0401E0BD107480091012368
+:102D200081880088FFF72AFC02E00846FFF768FF69
+:102D30000246104602BD0000D4040020792B000892
+:102D400070477047704770477047704770477047CB
+:102D50007047704710B50446FEF72EFD204610BDA3
+:102D600010B5044610460A460146204600F0A6FA71
+:102D7000204610BDC0680840884201D1012070473C
+:102D800000207047C0690840884201D10120704787
+:102D90000020704710B5664C02212046FFF7F2FF75
+:102DA00038B16068C043810703D5FFF712FD0220E8
+:102DB00018E001212046FFF7E5FF38B16068C04305
+:102DC000C10703D5FFF7CBFC01200BE0082120460B
+:102DD000FFF7D8FF38B16068C043010703D5FFF79C
+:102DE0004CFD0820A06010BD10B5514C00F033F828
+:102DF00018B96068C043810306D400F02CF830B9DC
+:102E00006068C043810302D5BDE810406EE0082130
+:102E100000F022F870B96068C04301030AD5606809
+:102E2000444940F400206060086880474FF4002067
+:102E3000A06010BD202100F00FF858B96068C043B1
+:102E4000810207D5606840F400106060BDE8104062
+:102E5000FFF798BC10BD022120468BE73648016879
+:102E600041F4007101603548026842F4007202606A
+:102E700040BF20BF3248016841F400410160704703
+:102E800080B53048016841F480110160006800F4A9
+:102E90008010009000982648016841F0010101600F
+:102EA000026842F4803202602C20FDF7FEFEBDE88D
+:102EB00002402D20FDF7F9BE23480168490849006A
+:102EC0000160704721494FF48030086070471E4808
+:102ED000016821F00201016070471B484FF4003186
+:102EE0004160016821F400310160704716480168B3
+:102EF00041F400310160FFF766BC38B504460C4D63
+:102F000008212846FFF736FF30B10A480460686898
+:102F100020F40020686031BDA0474FF40021A96073
+:102F200031BD0948016821F00801016070470000C7
+:102F3000000C0058E4040020D40800582008005871
+:102F40000C04005850000058040C0058080C00589D
+:102F5000564900E0564981B00A6802430A60096890
+:102F600008400090009801B0704718B585B06846D9
+:102F7000142100F0D7F9032001904FF460410024A0
+:102F8000009102940120FFF7E3FF00F097F8474C0F
+:102F90002068400840002060182100910220FFF7BF
+:102FA000D7FF6946434800F0C1F9206820F00200CD
+:102FB0002060FDF721FEFDF725FEFDF729FE00F05C
+:102FC00011F806B010BD00B587B068460FF20821B1
+:102FD0001C22FEF701FCFFF744FC6846FEF746FEA4
+:102FE00007B000BDF0B585B06846142100F09AF92D
+:102FF00000260025002400210FF2CC0000EBC102C6
+:10300000907988B11368B3F1904F08D0294FBB4233
+:1030100008D0294FBB4204BF9088044304E0908845
+:10302000064301E090880543491C2229E4DB002087
+:1030300002900121032003900191B0B270B1009081
+:103040000120FFF785FF0120FFF784FF00F036F82D
+:103050000022B1B24FF0904000F026FAA8B280B141
+:1030600000900220FFF774FF0220FFF773FF114E5C
+:103070006946304600F05AF90022A9B2304600F005
+:1030800013FAA0B280B100900420FFF761FF042082
+:10309000FFF760FF084D6946284600F047F9002217
+:1030A000A1B2284600F000FA05B0F0BD4C0000586F
+:1030B0004C010058000400480008004869464FF0E1
+:1030C000904000F033B9000000000048010000000B
+:1030D000000000480100000000000048010000005E
+:1030E000000000480100000000000048010000004E
+:1030F000000000480100000000000048010000003E
+:10310000000000480100000000000048010000002D
+:10311000000000480100000000000048010000001D
+:10312000000000480100000000000048010000000D
+:1031300000000048010000000000004801000000FD
+:1031400000000048010000000000004801000000ED
+:1031500000000048010000000000004801000000DD
+:1031600000000048010000000000004801000000CD
+:1031700000000048010000000000004801000000BD
+:1031800000000048010000000000004801000000AD
+:10319000000000480100000000000048010000009D
+:1031A000000000480100000000000048010000008D
+:1031B000000000480100000000000048010000007D
+:1031C000000000480100000000000048010000006D
+:1031D00000000048010000000000000000000000A6
+:1031E00000000000C8300008248000202880002053
+:1031F00022040400264981B00A6802430A60096873
+:1032000008400090009801B07047F0B585B00546C1
+:103210000C466846142100F085F82DB1012D08BF39
+:10322000102002D0022D02D10120FFF7E3FF200081
+:10323000184E0FF268070DD137F8150000900021E5
+:103240000191012002900221039100F01BF801205E
+:1032500000F055FA012C13D137F815000090012128
+:103260000D480190029100F00DF80FF23800445D16
+:1032700000220F2160B2FDF7FBFC60B2FDF715FDE7
+:1032800005B0F0BD694656F8250000F04FB80000C3
+:103290004C0000581C00002000002110010010000C
+:1032A00040000000060A170002490160024901615E
+:1032B000704700BF8B270008B327000862F30F2276
+:1032C00062F31F42401810F0030308D0C91A1FD33D
+:1032D000DB0748BF00F8012D28BF20F8022D13009E
+:1032E00030B414461546103928BF20E93C00FAD8FE
+:1032F000490728BF20E90C0048BF40F8042D890089
+:1033000028BF20F8022D48BF00F8012D30BC7047BF
+:10331000C91818BF00F8012DCB0728BF00F8012DF0
+:1033200070470000002200F01BBA00002DE9F84FA2
+:103330004FF0000C644A654BDFF894814FF00F09A1
+:1033400082460F4633E0634DAA4514BF0725042586
+:103350008D40254348F82E50C1431C6801EA040EF5
+:103360007C68E50348BF40EA0E0EC3F800E05C68E5
+:1033700001EA040E7C68A50348BF40EA0E0EC3F8BC
+:1033800004E0146801EA040E7C68E50248BF40EAE4
+:103390000E0EC2F800E0546801EA040E79688C024F
+:1033A00048BF40EA0E0EC2F804E00CF1010C396887
+:1033B00031FA0CF076D0012000FA0CFE1EEA010072
+:1033C000F3D07C68022C18BF122C4FEA8C0110D16C
+:1033D0004FEADC040AEB840401F01C05266A09FAB2
+:1033E00005FB26EA0B06D7F810B00BFA05F53543B6
+:1033F00025624FEA4C040325DAF8006097F804B020
+:10340000A540ED430BF0030B2E400BFA04FB4BEAF7
+:103410000606CAF800607E68012E18BF022E03D08F
+:10342000112E18BF122E17D1DAF80860D7F80CB099
+:103430002E400BFA04FB4BEA0606CAF80860DAF8DD
+:10344000046026EA0E0E7E68C6F3001606FA0CF635
+:1034500046EA0E06CAF80460DAF80C603540BE6829
+:1034600006FA04F42C43CAF80C407C68E4009CD5AE
+:103470004FEA9C0E58F82E5001F00C0109FA01F4A5
+:1034800025EA0404BAF1904F08BF002509D0124D77
+:10349000AA4508BF012504D0104DAA457FF453AFBB
+:1034A000022555E7BDE8F18F81B0002A14BF816184
+:1034B000816201B070470A4A136803421CBF106062
+:1034C000FFF769BA704700000008005880080058EC
+:1034D00008000140001000480004004800080048AF
+:1034E0000C080058924900E0924981B00A680243F2
+:1034F0000A60096808400090009801B0704710B554
+:10350000FDF760FB8C4C606840010ED56068C00020
+:103510000BD4FDF74FFBFDF74DFB206840F48030E6
+:103520002060216821F48031216000F0C7F800207C
+:10353000FEF700FF40B180798049E160E16821F445
+:103540007C5141EA0021E16000F048F87C487D4C64
+:10355000016800220260026902F05002026101204B
+:10356000FFF7C2FF0220FFF7BFFF0420FFF7BAFFFB
+:103570000120FFF7B7FF0220FFF7B4FF00220F2161
+:103580000E20FDF775FB0E20FDF78FFB00220F21AB
+:103590003A20FDF76DFB3A20FDF787FB00216A48D2
+:1035A00041600F218160046047F6FF71C160002116
+:1035B00001618161C16100F0EDF8CA206062FF2104
+:1035C00053206062A068C008C000A0606162FFF77D
+:1035D00079F94FF0FF30FEF75FFAFAE730B5A9B09E
+:1035E00017A84821FFF79EFE01A81C21FFF79AFEAD
+:1035F00008A83C21FFF796FE4F48544C016821F083
+:10360000180101604FF48032206820F4C06040F45B
+:10361000007020604FF48075216801F4C061009152
+:1036200007210098179101201990002140201B903C
+:10363000189222911A9517A8FCF789FD6F20019026
+:1036400002210020029103900490059006900790BB
+:10365000012101A8FDF72AF843F603000890002194
+:103660004FF48040139009910A9110200221159087
+:103670001491129508A800F046F9E06920F0700056
+:10368000E06133480168C1F303200090009830B92D
+:10369000E1690909090141F00401E16108E00098CC
+:1036A000E169801E80F30400090940EA0110E0612D
+:1036B000E06940F40040E06129B030BD254881B0A8
+:1036C000016841F4801101603F21006800F480101E
+:1036D00000900098204841604161016841F47C11EC
+:1036E0000160026942F47C120261016841F03F010D
+:1036F0000160026942F03F02026101B0704738B5D3
+:103700000446FDF751FA14F1010F054609D0FDF703
+:1037100070FA041905E01148016821F00401016004
+:1037200030BFFDF741FA401BA042F4D331BD000089
+:10373000480000584C00005890000058FECAFECACD
+:1037400080080058002800401004002000040058A1
+:103750005875FF1F50000058040C005810ED00E091
+:1037600000B500BF130096469446103928BFA0E864
+:103770000C50FAD85FEA417C28BF0CC048BF40F823
+:10378000042BC90728BF20F8022B48BF00F8012BE3
+:1037900000BD000038B5040044D094F8210028B9D9
+:1037A000002184F820102046FDF7E3FA00F049F8E4
+:1037B000FF2510B100F03FF834E02168DFF8B000D9
+:1037C0008A6802408A6021688A68636820690343C6
+:1037D000A06903431A438A602168E0680861206891
+:1037E0000169A26841EA024101612068C16821F0D3
+:1037F0008001C1602068C16C89088900C1642168AA
+:10380000CA6CE369606903431A43CA64206881682B
+:10381000880609D400F020F830B120684562042100
+:1038200000F01FF8012032BD20684562012184F8B4
+:103830002110002032BD20684562042184F8211047
+:103840007047022084F82100CA2021684862532072
+:1038500022685062204626E020460BE02068C0F82F
+:10386000248084F82110002084F820007047000094
+:10387000BFFF8FFF70B5044640F2E9362068C1688B
+:1038800021F0A001C160FDF78FF905462068C168ED
+:10389000880606D4FDF788F9401BB042F6D3032012
+:1038A00070BD002070BD70B504462068C1684A062E
+:1038B00012D44FF0FF32C26040F2E936FDF774F9DE
+:1038C00005462068C168480606D4FDF76DF9401B1F
+:1038D000B042F6D3032070BD002070BDDFF8D811D0
+:1038E0000A68030903F47F2300019A4300F47F2050
+:1038F000DFE0DFF8C4211368010C23EA014343EA47
+:103900000043136070472DE9F04105460027286801
+:10391000DFF8A8610105B8462FD53468A86A04F419
+:103920004074844229D0FDF745F9002C316805D157
+:10393000A86A21F44071014331601DE0306840F411
+:103940008030306021F44071326822F4803232607D
+:10395000A86A014331603068C0070DD5FDF724F92E
+:10396000044641F289383068800705D4FDF71CF918
+:10397000001B4045F7D30327B8462878DFF84041BD
+:10398000C10705D5E16F6868890840EA8101E167F0
+:103990002878810705D5E16FA86821F440610143CB
+:1039A000E1672878C10644BF6869FFF7A2FF28785D
+:1039B000810644BFA869FFF79CFF2878410744BFF0
+:1039C000E868FFF78BFF2878010744BF2869FFF7F5
+:1039D00085FF2868C1050AD5E16FE86921F04061DB
+:1039E0000143E167E869B0F1006F00F05CF8286816
+:1039F00081051BD5286AB0F1804F18BFB0F1004F88
+:103A000000D018B9E16F21F0404108E0E16F21F0EA
+:103A10004041E16720F08050E16F21F040610843B0
+:103A2000E067286AB0F1C05F00F03DF82868410502
+:103A30000AD5E16F686A21F040510143E167686A85
+:103A4000B0F1005F00F029F82868C10405D571685D
+:103A5000E86A21F4404101437160286881040BD574
+:103A6000A169686B21F030010143A161A169286B54
+:103A7000890840EA8101A161286841040AD5E16F03
+:103A8000A86B21F440710143E167A86BB0F5007F9A
+:103A900000F003F84046BDE8F08103D1216841F40D
+:103AA00080312160704703D1216841F0807121602D
+:103AB0007047104308607047880000589000005815
+:103AC0000C000058206881684A067047F8B5044623
+:103AD00040F60F002568E9692A68AB6808400DD1F7
+:103AE000880602D5900602D4D80040F18980E16EA4
+:103AF00000294FD02046BDE8F44008476248034201
+:103B000004BF624E32427BD0CF0709D5D60507D518
+:103B100001262E62D4F8885045F00105C4F888507B
+:103B20008D070AD5DD0708D5266802253562D4F849
+:103B3000885045F00405C4F888504D070AD5DD07C4
+:103B400008D5266804253562D4F8885045F002056A
+:103B5000C4F888500D070CD5950601D4034208D04F
+:103B6000256808202862D4F8880040F00800C4F8CE
+:103B7000880008050BD5500109D525684FF4006071
+:103B80002862D4F8880040F02000C4F88800D4F8F7
+:103B90008800002870D0890607D5900601D4D80087
+:103BA00003D5E16E09B120468847D4F88800216822
+:103BB0008A68510602D410F0280F1AD0204600F06F
+:103BC00069F8FFF77FFF0FD500F057F860B1DFF815
+:103BD000C0108163A06F00F079F800284CD0A06F6E
+:103BE000816BBDE8F44008472046BDE8F24000F094
+:103BF00004B9204600F001F90020C4F88800F1BDA6
+:103C0000C80209D5580207D54FF480102862204613
+:103C1000BDE8F24000F0F2B8080609D5100601D45C
+:103C2000180205D5216F39B32046BDE8F440084796
+:103C300048060FD550060DD5286820F040002860B2
+:103C40002021C4F88010002020672046BDE8F24003
+:103C500000F0D6B8080206D5500004D52046BDE8CD
+:103C6000F24000F0DBB8C80148BF002A04D5204666
+:103C7000BDE8F24000F0D3B8F1BD816821F0400109
+:103C80008160A06F70470000010000102001000457
+:103C9000B93C000801680A6822F490720A60DFF8F3
+:103CA0002810026893680B4093602021C0F88410AC
+:103CB0000021C16670470000806A00F156010022B1
+:103CC0000A810A8000F099B8FEFFFFEF38B500F1D5
+:103CD000240200245178022903D004209061012499
+:103CE00028E001680B6823F00E030B6001680D6883
+:103CF0006D086D000D60516A0B6823F480730B60D2
+:103D0000012192F82030D56903F01C0399406960C5
+:103D1000936AD16A5960116B31B10B6823F48073D7
+:103D20000B60536B916B5960012151701470516994
+:103D300001B18847204632BDF8B500F124010423C3
+:103D4000CA6914680268156891F8206006F01C06BC
+:103D500003FA06F73C4210D06F070ED51468A5068B
+:103D600003D4156825F00405156000F03DF8C96816
+:103D7000002938D0BDE8F4400847022303FA06F7CB
+:103D80003C4213D0AF0711D51468A50605D41568B9
+:103D900025F00A05156001224A7000F025F800227E
+:103DA0000A708968F9B1BDE8F4400847082303FAAE
+:103DB00006F6344217D02B0715D5136823F00E03EF
+:103DC0001360012291F82030CC6903F01C039A4063
+:103DD000626001228A614A7000220A70096911B189
+:103DE000BDE8F4400847F1BD91F82020CC6902F00D
+:103DF0001C029340636070470000704770470000EA
+:103E000000680449884204D103490868002818BFA3
+:103E10000047704700380140E804002070477047B1
+:103E200000EB8100404AD0F88010914201D001207F
+:103E300070470020704742F4806240F821207047AC
+:103E400080B500F097F83948092181610168C908F7
+:103E5000C90041F0030100F026F861E000F092B8DB
+:103E600010B500F087F8324C00F04CF80028FBD178
+:103E7000042100F048F828B92E480068010403D551
+:103E800000F043F800F05CF80022032100F03FF856
+:103E900026480168C908C90041F0020100F003F892
+:103EA000016030BF10BD01602348016841F004018A
+:103EB000704710B51E4C00F028F800F023F80028D9
+:103EC000FBD14FF0B040816801F00C01042911D101
+:103ED000016841F48031016001688903FCD5816883
+:103EE0008908890041F002018160816801F00C01BC
+:103EF0000829FAD10022032100F009F8BDE810409A
+:103F000000F040B8032120468AE700220421204621
+:103F100091E780B500F02EF80748016821F0040110
+:103F2000016030BF01BD00000004008000040058A3
+:103F3000001400588804005810ED00E000F022B88A
+:103F40004FF0B040016841F480710160016849059B
+:103F5000FCD581688908890041F001018160416ACE
+:103F6000890889004162816801F00C010429FAD1B5
+:103F7000704700000248016821F0020101607047AB
+:103F800010E000E00248016841F002010160704762
+:103F900010E000E07047FEE7FEE7FEE7FEE770474F
+:103FA0007047704700F024B80548FFF7C5BE0548C4
+:103FB000FFF78CBD0448FFF789BD0448FFF7BCBE7E
+:103FC00024030020180200208C010020840300201C
+:103FD0000120FFF770BA1020FFF76DBA4020FFF7FD
+:103FE0006ABAFDF730B8FEF7FFBEFEF7D3BE000099
+:103FF00002490A68886882180A60704750000020E9
+:1040000019E050F8042BD30744BFA9F101039A1813
+:10401000091F0023042942F8043BF9D25FEA817C9E
+:10402000134604D54FF0000CA2F800C09B1CC90732
+:1040300044BF0021197050F8041B0029E1D17047DA
+:1040400030B5016884684218416802EB5103C90722
+:104050000BD54C4409E012F9011B12F8015B002951
+:1040600004F8015B05D5491CF9D19A42F3D10C3013
+:1040700030BD491EF1D5F8E710B500F013F8020085
+:104080000023DB4300241068984203D01100022073
+:10409000ABBE14605068984203D0111D0220ABBE25
+:1040A000546010BD0148704700000000600000200F
+:1040B00010B5074979441831064C7C44163404E0A5
+:1040C0000A68081D114488470146A142F8D110BD75
+:1040D0002C000000600000004EF68851CEF2000176
+:1040E000086840F470000860BFF34F8FBFF36F8F14
+:1040F0004FF00070E1EE100A7047000005FFFFFF6F
+:104100009004000068000020800800002C8000203F
+:10411000000000002DFFFFFF6401000048000000C8
+:10412000040000201DFFFFFF7801000004000000D4
+:104130002480002000F00DF8002801D0FFF7B8FF20
+:10414000AFF300800020AFF30080FFF7D8F900F054
+:1041500002F80120704700F001B800000746384619
+:1041600000F002F8FBE7000080B5FFF785FF024A88
+:1041700011001820ABBEFBE726000200133F000829
+:104180003D3F0008613E0008B33E0008413E000884
+:104190005D3E00080148804701480047F9090008D2
+:1041A000A5410008AFF30080FFF796FFFFF7C2FFBD
+:1041B000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF33
+:1041C000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF23
+:1041D000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF13
+:1041E000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF03
+:1041F000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFF3
+:10420000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFE2
+:10421000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFD2
+:10422000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFC2
+:10423000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFB2
+:10424000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFA2
+:10425000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF92
+:10426000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF82
+:10427000FFF7FEBFFFF7FEBFFFF7FEBF020DFF0116
+:10428000E800044800100048FD000048EC00F8FF7A
+:10429000F0000010FD000001FC0002093D00F8FFE5
+:0242A000F80024
+:04000005080041A509
+:00000001FF
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/app_common.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/app_common.h
new file mode 100644
index 000000000..4defc5d7a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/app_common.h
@@ -0,0 +1,114 @@
+/**
+ ******************************************************************************
+  * File Name          : app_common.h
+  * Description        : App Common application configuration file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_COMMON_H
+#define APP_COMMON_H
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "app_conf.h"
+
+  /* -------------------------------- *
+   *  Basic definitions               *
+   * -------------------------------- */
+
+#undef NULL
+#define NULL                    0
+
+#undef FALSE
+#define FALSE                   0
+
+#undef TRUE
+#define TRUE                    (!0)
+
+  /* -------------------------------- *
+   *  Critical Section definition     *
+   * -------------------------------- */
+#define BACKUP_PRIMASK()    uint32_t primask_bit= __get_PRIMASK()
+#define DISABLE_IRQ()       __disable_irq()
+#define RESTORE_PRIMASK()   __set_PRIMASK(primask_bit)
+
+  /* -------------------------------- *
+   *  Macro delimiters                *
+   * -------------------------------- */
+
+#define M_BEGIN     do {
+
+#define M_END       } while(0)
+
+  /* -------------------------------- *
+   *  Some useful macro definitions   *
+   * -------------------------------- */
+
+#define MAX( x, y )          (((x)>(y))?(x):(y))
+
+#define MIN( x, y )          (((x)<(y))?(x):(y))
+
+#define MODINC( a, m )       M_BEGIN  (a)++;  if ((a)>=(m)) (a)=0;  M_END
+
+#define MODDEC( a, m )       M_BEGIN  if ((a)==0) (a)=(m);  (a)--;  M_END
+
+#define MODADD( a, b, m )    M_BEGIN  (a)+=(b);  if ((a)>=(m)) (a)-=(m);  M_END
+
+#define MODSUB( a, b, m )    MODADD( a, (m)-(b), m )
+
+#define PAUSE( t )           M_BEGIN \
+                               __IO int _i; \
+                               for ( _i = t; _i > 0; _i -- ); \
+                             M_END
+
+#define DIVF( x, y )         ((x)/(y))
+
+#define DIVC( x, y )         (((x)+(y)-1)/(y))
+
+#define DIVR( x, y )         (((x)+((y)/2))/(y))
+
+#define SHRR( x, n )         ((((x)>>((n)-1))+1)>>1)
+
+#define BITN( w, n )         (((w)[(n)/32] >> ((n)%32)) & 1)
+
+#define BITNSET( w, n, b )   M_BEGIN (w)[(n)/32] |= ((U32)(b))<<((n)%32); M_END
+
+  /* -------------------------------- *
+   *  Compiler                         *
+   * -------------------------------- */
+#define PLACE_IN_SECTION( __x__ )  __attribute__((section (__x__)))
+
+#ifdef WIN32
+#define ALIGN(n)
+#else
+#define ALIGN(n)             __attribute__((aligned(n)))
+#endif
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*APP_COMMON_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/app_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/app_conf.h
new file mode 100644
index 000000000..6c3e16761
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/app_conf.h
@@ -0,0 +1,530 @@
+/**
+ ******************************************************************************
+  * File Name          : app_conf.h
+  * Description        : Application configuration file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_CONF_H
+#define APP_CONF_H
+
+#include "hw.h"
+#include "hw_conf.h"
+#include "hw_if.h"
+
+/******************************************************************************
+ * Application Config
+ ******************************************************************************/
+
+/**< generic parameters ******************************************************/
+
+/**
+ * Define Tx Power
+ */   
+#define CFG_TX_POWER                      (0x18) /**< 0dbm */
+
+/**
+ * Define Advertising parameters
+ */
+#define CFG_ADV_BD_ADDRESS                (0x7257acd87a6c)
+#define CFG_FAST_CONN_ADV_INTERVAL_MIN    (0x80)   /**< 80ms */
+#define CFG_FAST_CONN_ADV_INTERVAL_MAX    (0xa0)  /**< 100ms */
+#define CFG_LP_CONN_ADV_INTERVAL_MIN      (0x640) /**< 1s */
+#define CFG_LP_CONN_ADV_INTERVAL_MAX      (0xfa0) /**< 2.5s */
+
+/**
+ * Define IO Authentication
+ */
+#define CFG_BONDING_MODE                  (1)
+#define CFG_FIXED_PIN                     (111111)
+#define CFG_USED_FIXED_PIN                (0)
+#define CFG_ENCRYPTION_KEY_SIZE_MAX       (16)
+#define CFG_ENCRYPTION_KEY_SIZE_MIN       (8)
+
+/**
+ * Define IO capabilities
+ */
+#define CFG_IO_CAPABILITY_DISPLAY_ONLY       (0x00)
+#define CFG_IO_CAPABILITY_DISPLAY_YES_NO     (0x01)
+#define CFG_IO_CAPABILITY_KEYBOARD_ONLY      (0x02)
+#define CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT (0x03)
+#define CFG_IO_CAPABILITY_KEYBOARD_DISPLAY   (0x04)
+
+#define CFG_IO_CAPABILITY             CFG_IO_CAPABILITY_DISPLAY_YES_NO
+
+/**
+ * Define MITM modes
+ */
+#define CFG_MITM_PROTECTION_NOT_REQUIRED      (0x00)
+#define CFG_MITM_PROTECTION_REQUIRED          (0x01)
+
+#define CFG_MITM_PROTECTION             CFG_MITM_PROTECTION_REQUIRED
+
+/**
+ * Define PHY
+ */
+#define ALL_PHYS_PREFERENCE                             0x00
+#define RX_2M_PREFERRED                                 0x02
+#define TX_2M_PREFERRED                                 0x02
+#define TX_1M                                           0x01
+#define TX_2M                                           0x02
+#define RX_1M                                           0x01
+#define RX_2M                                           0x02 
+
+/**
+*   Identity root key used to derive LTK and CSRK
+*/
+#define CFG_BLE_IRK     {0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0,0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0}
+
+/**
+* Encryption root key used to derive LTK and CSRK
+*/
+#define CFG_BLE_ERK     {0xfe,0xdc,0xba,0x09,0x87,0x65,0x43,0x21,0xfe,0xdc,0xba,0x09,0x87,0x65,0x43,0x21}
+
+/* USER CODE BEGIN Generic_Parameters */
+/**
+ * SMPS supply
+ * SMPS not used when Set to 0
+ * SMPS used when Set to 1
+ */
+#define CFG_USE_SMPS    1
+/* USER CODE END Generic_Parameters */
+
+/**< specific parameters */
+/*****************************************************/
+/**
+* AD Element - Group B Feature
+*/ 
+/* LSB - Second Byte */
+#define CFG_FEATURE_OTA_REBOOT                  (0x20)
+
+/******************************************************************************
+ * BLE Stack
+ ******************************************************************************/
+/**
+ * Maximum number of simultaneous connections that the device will support.
+ * Valid values are from 1 to 8
+ */
+#define CFG_BLE_NUM_LINK            8
+
+/**
+ * Maximum number of Services that can be stored in the GATT database.
+ * Note that the GAP and GATT services are automatically added so this parameter should be 2 plus the number of user services
+ */
+#define CFG_BLE_NUM_GATT_SERVICES   8
+
+/**
+ * Maximum number of Attributes
+ * (i.e. the number of characteristic + the number of characteristic values + the number of descriptors, excluding the services)
+ * that can be stored in the GATT database.
+ * Note that certain characteristics and relative descriptors are added automatically during device initialization
+ * so this parameters should be 9 plus the number of user Attributes
+ */
+#define CFG_BLE_NUM_GATT_ATTRIBUTES 68
+
+/**
+ * Maximum supported ATT_MTU size
+ */
+#define CFG_BLE_MAX_ATT_MTU             (156)
+
+/**
+ * Size of the storage area for Attribute values
+ *  This value depends on the number of attributes used by application. In particular the sum of the following quantities (in octets) should be made for each attribute:
+ *  - attribute value length
+ *  - 5, if UUID is 16 bit; 19, if UUID is 128 bit
+ *  - 2, if server configuration descriptor is used
+ *  - 2*DTM_NUM_LINK, if client configuration descriptor is used
+ *  - 2, if extended properties is used
+ *  The total amount of memory needed is the sum of the above quantities for each attribute.
+ */
+#define CFG_BLE_ATT_VALUE_ARRAY_SIZE    (1344)
+
+/**
+ * Prepare Write List size in terms of number of packet with ATT_MTU=23 bytes
+ */
+#define CFG_BLE_PREPARE_WRITE_LIST_SIZE         ( 0x3A )
+
+/**
+ * Number of allocated memory blocks
+ */
+#define CFG_BLE_MBLOCK_COUNT            ( 0x79 )
+
+/**
+ * Enable or disable the Extended Packet length feature. Valid values are 0 or 1.
+ */
+#define CFG_BLE_DATA_LENGTH_EXTENSION   1
+
+/**
+ * Sleep clock accuracy in Slave mode (ppm value)
+ */
+#define CFG_BLE_SLAVE_SCA   500
+
+/**
+ * Sleep clock accuracy in Master mode
+ * 0 : 251 ppm to 500 ppm
+ * 1 : 151 ppm to 250 ppm
+ * 2 : 101 ppm to 150 ppm
+ * 3 : 76 ppm to 100 ppm
+ * 4 : 51 ppm to 75 ppm
+ * 5 : 31 ppm to 50 ppm
+ * 6 : 21 ppm to 30 ppm
+ * 7 : 0 ppm to 20 ppm
+ */
+#define CFG_BLE_MASTER_SCA   0
+
+/**
+ *  Source for the 32 kHz slow speed clock
+ *  1 : internal RO
+ *  0 : external crystal ( no calibration )
+ */
+#define CFG_BLE_LSE_SOURCE  0
+
+/**
+ * Start up time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us)
+ */
+#define CFG_BLE_HSE_STARTUP_TIME  0x148
+
+/**
+ * Maximum duration of the connection event when the device is in Slave mode in units of 625/256 us (~2.44 us)
+ */
+#define CFG_BLE_MAX_CONN_EVENT_LENGTH  ( 0xFFFFFFFF )
+
+/**
+ * Viterbi Mode
+ * 1 : enabled
+ * 0 : disabled
+ */
+#define CFG_BLE_VITERBI_MODE  1
+
+/**
+ *  LL Only Mode
+ *  1 : LL Only
+ *  0 : LL + Host
+ */
+#define CFG_BLE_LL_ONLY  0
+/******************************************************************************
+ * Transport Layer
+ ******************************************************************************/
+/**
+ * Queue length of BLE Event
+ * This parameter defines the number of asynchronous events that can be stored in the HCI layer before
+ * being reported to the application. When a command is sent to the BLE core coprocessor, the HCI layer
+ * is waiting for the event with the Num_HCI_Command_Packets set to 1. The receive queue shall be large
+ * enough to store all asynchronous events received in between.
+ * When CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE is set to 27, this allow to store three 255 bytes long asynchronous events
+ * between the HCI command and its event.
+ * This parameter depends on the value given to CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE. When the queue size is to small,
+ * the system may hang if the queue is full with asynchronous events and the HCI layer is still waiting
+ * for a CC/CS event, In that case, the notification TL_BLE_HCI_ToNot() is called to indicate
+ * to the application a HCI command did not receive its command event within 30s (Default HCI Timeout).
+ */
+#define CFG_TLBLE_EVT_QUEUE_LENGTH 5
+/**
+ * This parameter should be set to fit most events received by the HCI layer. It defines the buffer size of each element
+ * allocated in the queue of received events and can be used to optimize the amount of RAM allocated by the Memory Manager.
+ * It should not exceed 255 which is the maximum HCI packet payload size (a greater value is a lost of memory as it will
+ * never be used)
+ * It shall be at least 4 to receive the command status event in one frame.
+ * The default value is set to 27 to allow receiving an event of MTU size in a single buffer. This value maybe reduced
+ * further depending on the application.
+ *
+ */
+#define CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE 255   /**< Set to 255 with the memory manager and the mailbox */
+
+#define TL_BLE_EVENT_FRAME_SIZE ( TL_EVT_HDR_SIZE + CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE )
+/******************************************************************************
+ * UART interfaces
+ ******************************************************************************/
+
+/**
+ * Select UART interfaces
+ */
+#define CFG_DEBUG_TRACE_UART    hw_uart1
+#define CFG_CONSOLE_MENU      
+/******************************************************************************
+ * USB interface
+ ******************************************************************************/
+
+/**
+ * Enable/Disable USB interface
+ */
+#define CFG_USB_INTERFACE_ENABLE    0
+
+/******************************************************************************
+ * Low Power
+ ******************************************************************************/
+/**
+ *  When set to 1, the low power mode is enable
+ *  When set to 0, the device stays in RUN mode
+ */
+#define CFG_LPM_SUPPORTED    1
+
+/******************************************************************************
+ * Timer Server
+ ******************************************************************************/
+/**
+ *  CFG_RTC_WUCKSEL_DIVIDER:  This sets the RTCCLK divider to the wakeup timer.
+ *  The higher is the value, the better is the power consumption and the accuracy of the timerserver
+ *  The lower is the value, the finest is the granularity
+ *
+ *  CFG_RTC_ASYNCH_PRESCALER: This sets the asynchronous prescaler of the RTC. It should as high as possible ( to ouput
+ *  clock as low as possible) but the output clock should be equal or higher frequency compare to the clock feeding
+ *  the wakeup timer. A lower clock speed would impact the accuracy of the timer server.
+ *
+ *  CFG_RTC_SYNCH_PRESCALER: This sets the synchronous prescaler of the RTC.
+ *  When the 1Hz calendar clock is required, it shall be sets according to other settings
+ *  When the 1Hz calendar clock is not needed, CFG_RTC_SYNCH_PRESCALER should be set to 0x7FFF (MAX VALUE)
+ *
+ *  CFG_RTCCLK_DIVIDER_CONF:
+ *  Shall be set to either 0,2,4,8,16
+ *  When set to either 2,4,8,16, the 1Hhz calendar is supported
+ *  When set to 0, the user sets its own configuration
+ *
+ *  The following settings are computed with LSI as input to the RTC
+ */
+#define CFG_RTCCLK_DIVIDER_CONF 0
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 0)
+/**
+ * Custom configuration
+ * It does not support 1Hz calendar
+ * It divides the RTC CLK by 16
+ */
+#define CFG_RTCCLK_DIV  (16)
+#define CFG_RTC_WUCKSEL_DIVIDER (0)
+#define CFG_RTC_ASYNCH_PRESCALER (CFG_RTCCLK_DIV - 1)
+#define CFG_RTC_SYNCH_PRESCALER (0x7FFF)
+
+#else
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 2)
+/**
+ * It divides the RTC CLK by 2
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (3)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 4)
+/**
+ * It divides the RTC CLK by 4
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (2)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 8)
+/**
+ * It divides the RTC CLK by 8
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (1)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 16)
+/**
+ * It divides the RTC CLK by 16
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (0)
+#endif
+
+#define CFG_RTCCLK_DIV              CFG_RTCCLK_DIVIDER_CONF
+#define CFG_RTC_ASYNCH_PRESCALER    (CFG_RTCCLK_DIV - 1)
+#define CFG_RTC_SYNCH_PRESCALER     (DIVR( LSE_VALUE, (CFG_RTC_ASYNCH_PRESCALER+1) ) - 1 )
+
+#endif
+
+/** tick timer value in us */
+#define CFG_TS_TICK_VAL           DIVR( (CFG_RTCCLK_DIV * 1000000), LSE_VALUE )
+
+typedef enum
+{
+    CFG_TIM_PROC_ID_ISR,
+} CFG_TimProcID_t;
+
+/******************************************************************************
+ * Debug
+ ******************************************************************************/
+/**
+ * When set, this resets some hw resources to set the device in the same state than the power up
+ * The FW resets only register that may prevent the FW to run properly
+ *
+ * This shall be set to 0 in a final product
+ *
+ */
+#define CFG_HW_RESET_BY_FW         1
+
+/**
+ * keep debugger enabled while in any low power mode when set to 1
+ * should be set to 0 in production
+ */
+#define CFG_DEBUGGER_SUPPORTED    0
+
+/**
+ * When set to 1, the traces are enabled in the BLE services
+ */
+#define CFG_DEBUG_BLE_TRACE     0
+
+/**
+ * Enable or Disable traces in application
+ */
+#define CFG_DEBUG_APP_TRACE     0
+
+#if (CFG_DEBUG_APP_TRACE != 0)
+#define APP_DBG_MSG                 PRINT_MESG_DBG
+#else
+#define APP_DBG_MSG                 PRINT_NO_MESG
+#endif
+
+#if ( (CFG_DEBUG_BLE_TRACE != 0) || (CFG_DEBUG_APP_TRACE != 0) )
+#define CFG_DEBUG_TRACE             1
+#endif
+
+#if (CFG_DEBUG_TRACE != 0)
+#undef CFG_LPM_SUPPORTED
+#undef CFG_DEBUGGER_SUPPORTED
+#define CFG_LPM_SUPPORTED         0
+#define CFG_DEBUGGER_SUPPORTED      1
+#endif
+
+/**
+ * When CFG_DEBUG_TRACE_FULL is set to 1, the trace are output with the API name, the file name and the line number
+ * When CFG_DEBUG_TRACE_LIGHT is set to 1, only the debug message is output
+ *
+ * When both are set to 0, no trace are output
+ * When both are set to 1,  CFG_DEBUG_TRACE_FULL is selected
+ */
+#define CFG_DEBUG_TRACE_LIGHT     1
+#define CFG_DEBUG_TRACE_FULL      0
+
+#if (( CFG_DEBUG_TRACE != 0 ) && ( CFG_DEBUG_TRACE_LIGHT == 0 ) && (CFG_DEBUG_TRACE_FULL == 0))
+#undef CFG_DEBUG_TRACE_FULL
+#undef CFG_DEBUG_TRACE_LIGHT
+#define CFG_DEBUG_TRACE_FULL      0
+#define CFG_DEBUG_TRACE_LIGHT     1
+#endif
+
+#if ( CFG_DEBUG_TRACE == 0 )
+#undef CFG_DEBUG_TRACE_FULL
+#undef CFG_DEBUG_TRACE_LIGHT
+#define CFG_DEBUG_TRACE_FULL      0
+#define CFG_DEBUG_TRACE_LIGHT     0
+#endif
+
+/**
+ * When not set, the traces is looping on sending the trace over UART
+ */
+#define DBG_TRACE_USE_CIRCULAR_QUEUE 1
+
+/**
+ * max buffer Size to queue data traces and max data trace allowed.
+ * Only Used if DBG_TRACE_USE_CIRCULAR_QUEUE is defined
+ */
+#define DBG_TRACE_MSG_QUEUE_SIZE 4096
+#define MAX_DBG_TRACE_MSG_SIZE 1024
+
+/* USER CODE BEGIN Defines */
+#define CFG_LED_SUPPORTED         0
+#define CFG_BUTTON_SUPPORTED      1
+
+#ifdef LITTLE_DORY
+#define PUSH_BUTTON_SW1_EXTI_IRQHandler                         EXTI0_IRQHandler
+#define PUSH_BUTTON_SW2_EXTI_IRQHandler                         EXTI4_IRQHandler
+#define PUSH_BUTTON_SW3_EXTI_IRQHandler                         EXTI9_5_IRQHandler
+#else
+#define PUSH_BUTTON_SW1_EXTI_IRQHandler                         EXTI4_IRQHandler
+#define PUSH_BUTTON_SW2_EXTI_IRQHandler                         EXTI0_IRQHandler
+#define PUSH_BUTTON_SW3_EXTI_IRQHandler                         EXTI1_IRQHandler
+#endif
+/* USER CODE END Defines */
+
+/******************************************************************************
+ * Scheduler
+ ******************************************************************************/
+
+/**
+ * These are the lists of task id registered to the scheduler
+ * Each task id shall be in the range [0:31]
+ * This mechanism allows to implement a generic code in the API TL_BLE_HCI_StatusNot() to comply with
+ * the requirement that a HCI/ACI command shall never be sent if there is already one pending
+ */
+
+/**< Add in that list all tasks that may send a ACI/HCI command */
+typedef enum
+{
+    CFG_TASK_ADV_UPDATE_ID,
+    CFG_TASK_MEAS_REQ_ID,
+    CFG_TASK_HCI_ASYNCH_EVT_ID,
+/* USER CODE BEGIN CFG_Task_Id_With_HCI_Cmd_t */
+
+/* USER CODE END CFG_Task_Id_With_HCI_Cmd_t */
+    CFG_LAST_TASK_ID_WITH_HCICMD,                                               /**< Shall be LAST in the list */
+} CFG_Task_Id_With_HCI_Cmd_t;
+
+/**< Add in that list all tasks that never send a ACI/HCI command */
+typedef enum
+{
+    CFG_FIRST_TASK_ID_WITH_NO_HCICMD = CFG_LAST_TASK_ID_WITH_HCICMD - 1,        /**< Shall be FIRST in the list */
+    CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID,
+/* USER CODE BEGIN CFG_Task_Id_With_NO_HCI_Cmd_t */
+
+/* USER CODE END CFG_Task_Id_With_NO_HCI_Cmd_t */
+    CFG_LAST_TASK_ID_WITHO_NO_HCICMD                                            /**< Shall be LAST in the list */
+} CFG_Task_Id_With_NO_HCI_Cmd_t;
+#define CFG_TASK_NBR    CFG_LAST_TASK_ID_WITHO_NO_HCICMD
+
+/**
+ * This is the list of priority required by the application
+ * Each Id shall be in the range 0..31
+ */
+typedef enum
+{
+    CFG_SCH_PRIO_0,
+    CFG_PRIO_NBR,
+} CFG_SCH_Prio_Id_t;
+
+/**
+ * This is a bit mapping over 32bits listing all events id supported in the application
+ */
+typedef enum
+{
+    CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID,
+    CFG_IDLEEVT_SYSTEM_HCI_CMD_EVT_RSP_ID,
+} CFG_IdleEvt_Id_t;
+
+/******************************************************************************
+ * LOW POWER
+ ******************************************************************************/
+/**
+ * Supported requester to the MCU Low Power Manager - can be increased up  to 32
+ * It lits a bit mapping of all user of the Low Power Manager
+ */
+typedef enum
+{
+    CFG_LPM_APP,
+    CFG_LPM_APP_BLE,
+  /* USER CODE BEGIN CFG_LPM_Id_t */
+
+  /* USER CODE END CFG_LPM_Id_t */
+} CFG_LPM_Id_t;
+
+/******************************************************************************
+ * OTP manager
+ ******************************************************************************/
+#define CFG_OTP_BASE_ADDRESS    OTP_AREA_BASE
+
+#define CFG_OTP_END_ADRESS      OTP_AREA_END_ADDR
+
+#endif /*APP_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/app_debug.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/app_debug.h
new file mode 100644
index 000000000..13485c16b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/app_debug.h
@@ -0,0 +1,45 @@
+
+/**
+  ******************************************************************************
+  * @file    app_debug.h
+  * @author  MCD Application Team
+  * @brief   Interface to support debug in the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+  /* Exported types ------------------------------------------------------------*/
+  /* Exported constants --------------------------------------------------------*/
+  /* External variables --------------------------------------------------------*/
+  /* Exported macros -----------------------------------------------------------*/
+  /* Exported functions ------------------------------------------------------- */
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/app_entry.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/app_entry.h
new file mode 100644
index 000000000..77ead2384
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/app_entry.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    app_entry.h
+  * @author  MCD Application Team
+  * @brief   Interface to the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_ENTRY_H
+#define APP_ENTRY_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APPE_Init( void );
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*APP_ENTRY_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/hw_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/hw_conf.h
new file mode 100644
index 000000000..f4f55affa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/hw_conf.h
@@ -0,0 +1,196 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : hw_conf.h
+  * Description        : Hardware configuration file for BLE 
+  *                      middleWare.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef HW_CONF_H
+#define HW_CONF_H
+
+/******************************************************************************
+* Semaphores
+* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
+*****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
+/* Index of the semaphore used to manage the entry Stop Mode procedure */
+#define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
+
+/* Index of the semaphore used to access the RCC */
+#define CFG_HW_RCC_SEMID                                        3
+
+/* Index of the semaphore used to access the FLASH */
+#define CFG_HW_FLASH_SEMID                                      2
+
+/* Index of the semaphore used to access the PKA */
+#define CFG_HW_PKA_SEMID                                        1
+
+/* Index of the semaphore used to access the RNG */
+#define CFG_HW_RNG_SEMID                                        0
+
+/******************************************************************************
+ * HW TIMER SERVER
+ *****************************************************************************/
+/**
+ * The user may define the maximum number of virtual timers supported.
+ * It shall not exceed 255
+ */
+#define CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER  6
+
+/**
+ * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
+ * wakeup timer.
+ * This setting is the preemptpriority part of the NVIC.
+ */
+#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO  3
+
+/**
+ * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
+ * wakeup timer.
+ * This setting is the subpriority part of the NVIC. It does not exist on all processors. When it is not supported
+ * on the CPU, the setting is ignored
+ */
+#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO  0
+
+/**
+ *  Define a critical section in the Timer server
+ *  The Timer server does not support the API to be nested
+ *  The  Application shall either:
+ *    a) Ensure this will never happen
+ *    b) Define the critical section
+ *  The default implementations is masking all interrupts using the PRIMASK bit
+ *  The TimerServer driver uses critical sections to avoid context corruption. This is achieved with the macro
+ *  TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION. When CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION is set
+ *  to 1, all STM32 interrupts are masked with the PRIMASK bit of the CortexM CPU. It is possible to use the BASEPRI
+ *  register of the CortexM CPU to keep allowed some interrupts with high priority. In that case, the user shall
+ *  re-implement TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION and shall make sure that no TimerServer
+ *  API are called when the TIMER critical section is entered
+ */
+#define CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION  1
+
+/**
+   * This value shall reflect the maximum delay there could be in the application between the time the RTC interrupt
+   * is generated by the Hardware and the time when the  RTC interrupt handler is called. This time is measured in
+   * number of RTCCLK ticks.
+   * A relaxed timing would be 10ms
+   * When the value is too short, the timerserver will not be able to count properly and all timeout may be random.
+   * When the value is too long, the device may wake up more often than the most optimal configuration. However, the
+   * impact on power consumption would be marginal (unless the value selected is extremely too long). It is strongly
+   * recommended to select a value large enough to make sure it is not too short to ensure reliability of the system
+   * as this will have marginal impact on low power mode
+   */
+#define CFG_HW_TS_RTC_HANDLER_MAX_DELAY  ( 10 * (LSI_VALUE/1000) )
+
+  /**
+   * Interrupt ID in the NVIC of the RTC Wakeup interrupt handler
+   * It shall be type of IRQn_Type
+   */
+#define CFG_HW_TS_RTC_WAKEUP_HANDLER_ID  RTC_WKUP_IRQn
+
+/******************************************************************************
+ * HW UART
+ *****************************************************************************/
+
+#define CFG_HW_LPUART1_ENABLED           0
+#define CFG_HW_LPUART1_DMA_TX_SUPPORTED  0
+
+#define CFG_HW_USART1_ENABLED           1
+#define CFG_HW_USART1_DMA_TX_SUPPORTED  1
+
+/**
+ * UART1
+ */
+#define CFG_HW_USART1_PREEMPTPRIORITY         0x0F
+#define CFG_HW_USART1_SUBPRIORITY             0
+
+/** < The application shall check the selected source clock is enable */
+#define CFG_HW_USART1_SOURCE_CLOCK              RCC_USART1CLKSOURCE_SYSCLK
+
+#define CFG_HW_USART1_BAUDRATE                115200
+#define CFG_HW_USART1_WORDLENGTH              UART_WORDLENGTH_8B
+#define CFG_HW_USART1_STOPBITS                UART_STOPBITS_1
+#define CFG_HW_USART1_PARITY                  UART_PARITY_NONE
+#define CFG_HW_USART1_HWFLOWCTL               UART_HWCONTROL_NONE
+#define CFG_HW_USART1_MODE                    UART_MODE_TX_RX
+#define CFG_HW_USART1_ADVFEATUREINIT          UART_ADVFEATURE_NO_INIT
+#define CFG_HW_USART1_OVERSAMPLING            UART_OVERSAMPLING_8
+
+#define CFG_HW_USART1_TX_PORT_CLK_ENABLE      __HAL_RCC_GPIOB_CLK_ENABLE
+#define CFG_HW_USART1_TX_PORT                 GPIOB
+#define CFG_HW_USART1_TX_PIN                  GPIO_PIN_6
+#define CFG_HW_USART1_TX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_USART1_TX_PULL                 GPIO_NOPULL
+#define CFG_HW_USART1_TX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_TX_ALTERNATE            GPIO_AF7_USART1
+
+#define CFG_HW_USART1_RX_PORT_CLK_ENABLE      __HAL_RCC_GPIOB_CLK_ENABLE
+#define CFG_HW_USART1_RX_PORT                 GPIOB
+#define CFG_HW_USART1_RX_PIN                  GPIO_PIN_7
+#define CFG_HW_USART1_RX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_USART1_RX_PULL                 GPIO_NOPULL
+#define CFG_HW_USART1_RX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_RX_ALTERNATE            GPIO_AF7_USART1
+
+#define CFG_HW_USART1_CTS_PORT_CLK_ENABLE     __HAL_RCC_GPIOA_CLK_ENABLE
+#define CFG_HW_USART1_CTS_PORT                GPIOA
+#define CFG_HW_USART1_CTS_PIN                 GPIO_PIN_11
+#define CFG_HW_USART1_CTS_MODE                GPIO_MODE_AF_PP
+#define CFG_HW_USART1_CTS_PULL                GPIO_PULLDOWN
+#define CFG_HW_USART1_CTS_SPEED               GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_CTS_ALTERNATE           GPIO_AF7_USART1
+
+#define CFG_HW_USART1_DMA_TX_PREEMPTPRIORITY  0x0F
+#define CFG_HW_USART1_DMA_TX_SUBPRIORITY      0
+
+#define CFG_HW_USART1_DMAMUX_CLK_ENABLE       __HAL_RCC_DMAMUX1_CLK_ENABLE
+#define CFG_HW_USART1_DMA_CLK_ENABLE          __HAL_RCC_DMA2_CLK_ENABLE
+#define CFG_HW_USART1_TX_DMA_REQ			  DMA_REQUEST_USART1_TX
+#define CFG_HW_USART1_TX_DMA_CHANNEL          DMA2_CHANNEL_4
+#define CFG_HW_USART1_TX_DMA_IRQn             DMA2_CHANNEL_4_IRQn
+#define CFG_HW_USART1_DMA_TX_IRQHandler       DMA2_CHANNEL_4_IRQHandler
+
+#endif /*HW_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/hw_if.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/hw_if.h
new file mode 100644
index 000000000..5a15665ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/hw_if.h
@@ -0,0 +1,254 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    hw_if.h
+  * @author  MCD Application Team
+  * @brief   Hardware Interface
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef HW_IF_H
+#define HW_IF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_ipcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_hsem.h"
+#include "stm32wbxx_ll_gpio.h"
+#include "stm32wbxx_ll_rtc.h"
+
+#ifdef  USE_STM32WBXX_USB_DONGLE
+#include "stm32wbxx_usb_dongle.h"
+#endif
+#ifdef  USE_STM32WBXX_NUCLEO
+  #ifdef STM32WB35xx
+  #include "nucleo_wb35ce.h"
+  #else
+  #include "stm32wbxx_nucleo.h"
+  #endif
+#endif
+#ifdef  USE_X_NUCLEO_EPD
+#include "x_nucleo_epd.h"
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /******************************************************************************
+   * HW UART
+   ******************************************************************************/
+  typedef enum
+  {
+    hw_uart1,
+    hw_uart2,
+    hw_lpuart1,
+  } hw_uart_id_t;
+
+  typedef enum
+  {
+    hw_uart_ok,
+    hw_uart_error,
+    hw_uart_busy,
+    hw_uart_to,
+  } hw_status_t;
+
+  void HW_UART_Init(hw_uart_id_t hw_uart_id);
+  void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *pData, uint16_t Size, void (*Callback)(void));
+  void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *pData, uint16_t Size,  void (*Callback)(void));
+  hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout);
+  hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*Callback)(void));
+  void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id);
+  void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id);
+
+  /******************************************************************************
+   * HW TimerServer
+   ******************************************************************************/
+  /* Exported types ------------------------------------------------------------*/
+  /**
+   * This setting is used when standby mode is supported.
+   * hw_ts_InitMode_Limited should be used when the device restarts from Standby Mode. In that case, the Timer Server does
+   * not re-initialized its context. Only the Hardware register which content has been lost is reconfigured
+   * Otherwise, hw_ts_InitMode_Full should be requested (Start from Power ON) and everything is re-initialized.
+   */
+  typedef enum
+  {
+    hw_ts_InitMode_Full,
+    hw_ts_InitMode_Limited,
+  } HW_TS_InitMode_t;
+
+  /**
+   * When a Timer is created as a SingleShot timer, it is not automatically restarted when the timeout occurs. However,
+   * the timer is kept reserved in the list and could be restarted at anytime with HW_TS_Start()
+   *
+   * When a Timer is created as a Repeated timer, it is automatically restarted when the timeout occurs.
+   */
+  typedef enum
+  {
+    hw_ts_SingleShot,
+    hw_ts_Repeated
+  } HW_TS_Mode_t;
+
+  /**
+   * hw_ts_Successful is returned when a Timer has been successfully created with HW_TS_Create(). Otherwise, hw_ts_Failed
+   * is returned. When hw_ts_Failed is returned, that means there are not enough free slots in the list to create a
+   * Timer. In that case, CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER should be increased
+   */
+  typedef enum
+  {
+    hw_ts_Successful,
+    hw_ts_Failed,
+  }HW_TS_ReturnStatus_t;
+
+  typedef void (*HW_TS_pTimerCb_t)(void);
+
+  /**
+   * @brief  Initialize the timer server
+   *         This API shall be called by the application before any timer is requested to the timer server. It
+   *         configures the RTC module to be connected to the LSI input clock.
+   *
+   * @param  TimerInitMode: When the device restarts from Standby, it should request hw_ts_InitMode_Limited so that the
+   *         Timer context is not re-initialized. Otherwise, hw_ts_InitMode_Full should be requested
+   * @param  hrtc: RTC Handle
+   * @retval None
+   */
+  void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *hrtc);
+
+  /**
+   * @brief  Interface to create a virtual timer
+   *         The user shall call this API to create a timer. Once created, the timer is reserved to the module until it
+   *         has been deleted. When creating a timer, the user shall specify the mode (single shot or repeated), the
+   *         callback to be notified when the timer expires and a module ID to identify in the timer interrupt handler
+   *         which module is concerned. In return, the user gets a timer ID to handle it.
+   *
+   * @param  TimerProcessID:  This is an identifier provided by the user and returned in the callback to allow
+   *                          identification of the requester
+   * @param  pTimerId: Timer Id returned to the user to request operation (start, stop, delete)
+   * @param  TimerMode: Mode of the virtual timer (Single shot or repeated)
+   * @param  pTimerCallBack: Callback when the virtual timer expires
+   * @retval HW_TS_ReturnStatus_t: Return whether the creation is sucessfull or not
+   */
+  HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pTimerCallBack);
+
+  /**
+   * @brief  Stop a virtual timer
+   *         This API may be used to stop a running timer. A timer which is stopped is move to the pending state.
+   *         A pending timer may be restarted at any time with a different timeout value but the mode cannot be changed.
+   *         Nothing is done when it is called to stop a timer which has been already stopped
+   *
+   * @param  TimerID:  Id of the timer to stop
+   * @retval None
+   */
+  void HW_TS_Stop(uint8_t TimerID);
+
+  /**
+   * @brief  Start a virtual timer
+   *         This API shall be used to start a timer. The timeout value is specified and may be different each time.
+   *         When the timer is in the single shot mode, it will move to the pending state when it expires. The user may
+   *         restart it at any time with a different timeout value. When the timer is in the repeated mode, it always
+   *         stay in the running state. When the timer expires, it will be restarted with the same timeout value.
+   *         This API shall not be called on a running timer.
+   *
+   * @param  TimerID:  The ID Id of the timer to start
+   * @param  timeout_ticks: Number of ticks of the virtual timer (Maximum value is (0xFFFFFFFF-0xFFFF = 0xFFFF0000)
+   * @retval None
+   */
+  void HW_TS_Start(uint8_t TimerID, uint32_t timeout_ticks);
+
+  /**
+   * @brief  Delete a virtual timer from the list
+   *         This API should be used when a timer is not needed anymore by the user. A deleted timer is removed from
+   *         the timer list managed by the timer server. It cannot be restarted again. The user has to go with the
+   *         creation of a new timer if required and may get a different timer id
+   *
+   * @param  TimerID:  The ID of the timer to remove from the list
+   * @retval None
+   */
+  void HW_TS_Delete(uint8_t TimerID);
+
+  /**
+   * @brief  Schedule the timer list on the timer interrupt handler
+   *         This interrupt handler shall be called by the application in the RTC interrupt handler. This handler takes
+   *         care of clearing all status flag required in the RTC and EXTI peripherals
+   *
+   * @param  None
+   * @retval None
+   */
+  void HW_TS_RTC_Wakeup_Handler(void);
+
+  /**
+   * @brief  Return the number of ticks to count before the interrupt
+   *         This API returns the number of ticks left to be counted before an interrupt is generated by the
+   *         Timer Server. This API may be used by the application for power management optimization. When the system
+   *         enters low power mode, the mode selection is a tradeoff between the wakeup time where the CPU is running
+   *         and the time while the CPU will be kept in low power mode before next wakeup. The deeper is the
+   *         low power mode used, the longer is the wakeup time. The low power mode management considering wakeup time
+   *         versus time in low power mode is implementation specific
+   *         When the timer is disabled (No timer in the list), it returns 0xFFFF
+   *
+   * @param  None
+   * @retval The number of ticks left to count
+   */
+  uint16_t HW_TS_RTC_ReadLeftTicksToCount(void);
+
+  /**
+   * @brief  Notify the application that a registered timer has expired
+   *         This API shall be implemented by the user application.
+   *         This API notifies the application that a timer expires. This API is running in the RTC Wakeup interrupt
+   *         context. The application may implement an Operating System to change the context priority where the timer
+   *         callback may be handled. This API provides the module ID to identify which module is concerned and to allow
+   *         sending the information to the correct task
+   *
+   * @param  TimerProcessID: The TimerProcessId associated with the timer when it has been created
+   * @param  TimerID: The TimerID of the expired timer
+   * @param  pTimerCallBack: The Callback associated with the timer when it has been created
+   * @retval None
+   */
+  void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack);
+
+  /**
+   * @brief  Notify the application that the wakeupcounter has been updated
+   *         This API should be implemented by the user application
+   *         This API notifies the application that the counter has been updated. This is expected to be used along
+   *         with the HW_TS_RTC_ReadLeftTicksToCount () API. It could be that the counter has been updated since the
+   *         last call of HW_TS_RTC_ReadLeftTicksToCount () and before entering low power mode. This notification
+   *         provides a way to the application to solve that race condition to reevaluate the counter value before
+   *         entering low power mode
+   *
+   * @param  None
+   * @retval None
+   */
+  void HW_TS_RTC_CountUpdated_AppNot(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*HW_IF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/main.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/main.h
new file mode 100644
index 000000000..c8b13c23f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/main.h
@@ -0,0 +1,75 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#ifdef STM32WB35xx
+#include "nucleo_wb35ce.h"
+#else
+#include "stm32wbxx_nucleo.h"
+#endif
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/stm32_lpm_if.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/stm32_lpm_if.h
new file mode 100644
index 000000000..d8e67947f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/stm32_lpm_if.h
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+******************************************************************************
+* @file    stm32_lpm_if.h
+* @brief   Header for stm32_lpm_if.c module (device specific LP management)
+******************************************************************************
+* @attention
+*
+* 
    © Copyright (c) 2019 STMicroelectronics. 
+* All rights reserved.
    
+*
+* This software component is licensed by ST under BSD 3-Clause license,
+* the "License"; You may not use this file except in compliance with the 
+* License. You may obtain a copy of the License at:
+*                        opensource.org/licenses/BSD-3-Clause
+*
+******************************************************************************
+*/
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_LPM_IF_H
+#define __STM32_LPM_IF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/**
+  * @brief Enters Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_EnterOffMode( void );
+/**
+  * @brief Exits Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_ExitOffMode( void );
+
+/**
+  * @brief Enters Low Power Stop Mode
+  * @note ARM exists the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterStopMode( void );
+/**
+  * @brief Exits Low Power Stop Mode
+  * @note Enable the pll at 32MHz
+  * @param none
+  * @retval none
+  */
+void PWR_ExitStopMode( void );
+
+/**
+  * @brief Enters Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterSleepMode( void );
+
+/**
+  * @brief Exits Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_ExitSleepMode( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32_LPM_IF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..eff335ddf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,354 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+#define HAL_CORTEX_MODULE_ENABLED
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+/*#define HAL_I2C_MODULE_ENABLED   */
+#define HAL_IPCC_MODULE_ENABLED
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+#define HAL_PWR_MODULE_ENABLED
+/*#define HAL_QSPI_MODULE_ENABLED   */
+#define HAL_RCC_MODULE_ENABLED
+/*#define HAL_RNG_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100UL)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  (32000UL)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  (32000UL)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    (48000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    (2097000UL) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..12466d5e3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/stm32wbxx_it.h
@@ -0,0 +1,79 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "app_common.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void DMA1_Channel4_IRQHandler(void);
+void USART1_IRQHandler(void);
+void LPUART1_IRQHandler(void);
+void DMA2_Channel4_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+void RTC_WKUP_IRQHandler(void);
+void IPCC_C1_TX_IRQHandler(void);
+void IPCC_C1_RX_IRQHandler(void);
+void PUSH_BUTTON_SW1_EXTI_IRQHandler(void);
+void PUSH_BUTTON_SW2_EXTI_IRQHandler(void);
+void PUSH_BUTTON_SW3_EXTI_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/utilities_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/utilities_conf.h
new file mode 100644
index 000000000..4dde3509a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Inc/utilities_conf.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : utilities_conf.h
+  * Description        : Configuration file for STM32 Utilities.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef UTILITIES_CONF_H
+#define UTILITIES_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "cmsis_compiler.h"
+#include "string.h"
+
+/******************************************************************************
+ * common
+ ******************************************************************************/
+#define UTILS_ENTER_CRITICAL_SECTION( )   uint32_t primask_bit = __get_PRIMASK( );\
+                                          __disable_irq( )
+
+#define UTILS_EXIT_CRITICAL_SECTION( )          __set_PRIMASK( primask_bit )
+
+#define UTILS_MEMSET8( dest, value, size )      memset( dest, value, size);
+
+/******************************************************************************
+ * tiny low power manager
+ * (any macro that does not need to be modified can be removed)
+ ******************************************************************************/
+#define UTIL_LPM_INIT_CRITICAL_SECTION( )
+#define UTIL_LPM_ENTER_CRITICAL_SECTION( )      UTILS_ENTER_CRITICAL_SECTION( )
+#define UTIL_LPM_EXIT_CRITICAL_SECTION( )       UTILS_EXIT_CRITICAL_SECTION( )
+
+/******************************************************************************
+ * sequencer
+ * (any macro that does not need to be modified can be removed)
+ ******************************************************************************/
+#define UTIL_SEQ_INIT_CRITICAL_SECTION( )
+#define UTIL_SEQ_ENTER_CRITICAL_SECTION( )      UTILS_ENTER_CRITICAL_SECTION( )
+#define UTIL_SEQ_EXIT_CRITICAL_SECTION( )       UTILS_EXIT_CRITICAL_SECTION( )
+#define UTIL_SEQ_CONF_TASK_NBR                  (32)
+#define UTIL_SEQ_CONF_PRIO_NBR                  (2)
+#define UTIL_SEQ_MEMSET8( dest, value, size )   UTILS_MEMSET8( dest, value, size )
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*UTILITIES_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/app_debug.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/app_debug.c
new file mode 100644
index 000000000..756c4257f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/app_debug.c
@@ -0,0 +1,361 @@
+/**
+ ******************************************************************************
+ * @file    app_debug.c
+ * @author  MCD Application Team
+ * @brief   Debug capabilities
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+extern void MX_LPUART1_UART_Init(void);
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+extern void MX_USART1_UART_Init(void);
+#endif
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+#if (CFG_HW_USART1_ENABLED == 1)
+    MX_USART1_UART_Init();
+#endif
+#if (CFG_HW_LPUART1_ENABLED == 1)
+    MX_LPUART1_UART_Init();
+#endif
+  return;
+}
+
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/app_entry.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/app_entry.c
new file mode 100644
index 000000000..c16d0ea9c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/app_entry.c
@@ -0,0 +1,301 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    app_entry.c
+ * @author  MCD Application Team
+ * @brief   Entry point of the Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "main.h"
+#include "app_entry.h"
+#include "app_ble.h"
+#include "ble.h"
+#include "tl.h"
+#include "stm32_seq.h"
+#include "shci_tl.h"
+#include "stm32_lpm.h"
+#include "app_debug.h"
+
+/* Private includes -----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+extern RTC_HandleTypeDef hrtc;
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+#define POOL_SIZE (CFG_TLBLE_EVT_QUEUE_LENGTH*4U*DIVC(( sizeof(TL_PacketHeader_t) + TL_BLE_EVENT_FRAME_SIZE ), 4U))
+
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t EvtPool[POOL_SIZE];
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static TL_CmdPacket_t SystemCmdBuffer;
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t SystemSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255U];
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t BleSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255];
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private functions prototypes-----------------------------------------------*/
+static void SystemPower_Config( void );
+static void appe_Tl_Init( void );
+static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status );
+static void APPE_SysUserEvtRx( void * pPayload );
+
+/* USER CODE BEGIN PFP */
+static void Led_Init( void );
+static void Button_Init( void );
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APPE_Init( void )
+{
+  SystemPower_Config(); /**< Configure the system Power Mode */
+
+  HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
+
+/* USER CODE BEGIN APPE_Init_1 */
+  APPD_Init();
+  
+  /**
+   * The Standby mode should not be entered before the initialization is over
+   * The default state of the Low Power Manager is to allow the Standby Mode so an request is needed here
+   */
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP, UTIL_LPM_DISABLE);
+
+  Led_Init();
+
+  Button_Init();
+/* USER CODE END APPE_Init_1 */
+  appe_Tl_Init();	/* Initialize all transport layers */
+
+  /**
+   * From now, the application is waiting for the ready event ( VS_HCI_C2_Ready )
+   * received on the system channel before starting the Stack
+   * This system event is received with APPE_SysUserEvtRx()
+   */
+/* USER CODE BEGIN APPE_Init_2 */
+
+/* USER CODE END APPE_Init_2 */
+   return;
+}
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+ * @brief  Configure the system for power optimization
+ *
+ * @note  This API configures the system to be ready for low power mode
+ *
+ * @param  None
+ * @retval None
+ */
+static void SystemPower_Config( void )
+{
+
+  /**
+   * Select HSI as system clock source after Wake Up from Stop mode
+   */
+  LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
+
+  /* Initialize low power manager */
+  UTIL_LPM_Init( );
+
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+  /**
+   *  Enable USB power
+   */
+  HAL_PWREx_EnableVddUSB();
+#endif
+
+  return;
+}
+
+static void appe_Tl_Init( void )
+{
+  TL_MM_Config_t tl_mm_config;
+  SHCI_TL_HciInitConf_t SHci_Tl_Init_Conf;
+  /**< Reference table initialization */
+  TL_Init();
+
+  /**< System channel initialization */
+  UTIL_SEQ_RegTask( 1<< CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID, UTIL_SEQ_RFU, shci_user_evt_proc );
+  SHci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&SystemCmdBuffer;
+  SHci_Tl_Init_Conf.StatusNotCallBack = APPE_SysStatusNot;
+  shci_init(APPE_SysUserEvtRx, (void*) &SHci_Tl_Init_Conf);
+
+  /**< Memory Manager channel initialization */
+  tl_mm_config.p_BleSpareEvtBuffer = BleSpareEvtBuffer;
+  tl_mm_config.p_SystemSpareEvtBuffer = SystemSpareEvtBuffer;
+  tl_mm_config.p_AsynchEvtPool = EvtPool;
+  tl_mm_config.AsynchEvtPoolSize = POOL_SIZE;
+  TL_MM_Init( &tl_mm_config );
+
+  TL_Enable();
+
+  return;
+}
+
+static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status )
+{
+  UNUSED(status);
+  return;
+}
+
+/**
+ * The type of the payload for a system user event is tSHCI_UserEvtRxParam
+ * When the system event is both :
+ *    - a ready event (subevtcode = SHCI_SUB_EVT_CODE_READY)
+ *    - reported by the FUS (sysevt_ready_rsp == RSS_FW_RUNNING)
+ * The buffer shall not be released
+ * ( eg ((tSHCI_UserEvtRxParam*)pPayload)->status shall be set to SHCI_TL_UserEventFlow_Disable )
+ * When the status is not filled, the buffer is released by default
+ */
+static void APPE_SysUserEvtRx( void * pPayload )
+{
+  UNUSED(pPayload);
+  /* Traces channel initialization */
+  APPD_EnableCPU2();
+
+  APP_BLE_Init( );
+  UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE);
+  return;
+}
+
+/* USER CODE BEGIN FD_LOCAL_FUNCTIONS */
+static void Led_Init( void )
+{
+#if (CFG_LED_SUPPORTED == 1)
+  /**
+   * Leds Initialization
+   */
+
+  BSP_LED_Init(LED_BLUE);
+  BSP_LED_Init(LED_GREEN);
+  BSP_LED_Init(LED_RED);
+
+  BSP_LED_On(LED_GREEN);
+#endif
+
+  return;
+}
+
+static void Button_Init( void )
+{
+#if (CFG_BUTTON_SUPPORTED == 1)
+  /**
+   * Button Initialization
+   */
+
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+  BSP_PB_Init(BUTTON_SW2, BUTTON_MODE_EXTI);
+  BSP_PB_Init(BUTTON_SW3, BUTTON_MODE_EXTI);
+#endif
+
+  return;
+}
+/* USER CODE END FD_LOCAL_FUNCTIONS */
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+
+void UTIL_SEQ_Idle( void )
+{
+#if ( CFG_LPM_SUPPORTED == 1)
+  UTIL_LPM_EnterLowPower( );
+#endif
+  return;
+}
+
+/**
+  * @brief  This function is called by the scheduler each time an event
+  *         is pending.
+  *
+  * @param  evt_waited_bm : Event pending.
+  * @retval None
+  */
+void UTIL_SEQ_EvtIdle( UTIL_SEQ_bm_t task_id_bm, UTIL_SEQ_bm_t evt_waited_bm )
+{
+  UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+}
+
+void shci_notify_asynch_evt(void* pdata)
+{
+  UTIL_SEQ_SetTask( 1<
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "hw_conf.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef enum
+{
+  TimerID_Free,
+  TimerID_Created,
+  TimerID_Running
+}TimerIDStatus_t;
+
+typedef enum
+{
+  SSR_Read_Requested,
+  SSR_Read_Not_Requested
+}RequestReadSSR_t;
+
+typedef enum
+{
+  WakeupTimerValue_Overpassed,
+  WakeupTimerValue_LargeEnough
+}WakeupTimerLimitation_Status_t;
+
+typedef struct
+{
+  HW_TS_pTimerCb_t  pTimerCallBack;
+  uint32_t        CounterInit;
+  uint32_t        CountLeft;
+  TimerIDStatus_t     TimerIDStatus;
+  HW_TS_Mode_t   TimerMode;
+  uint32_t        TimerProcessID;
+  uint8_t         PreviousID;
+  uint8_t         NextID;
+}TimerContext_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define SSR_FORBIDDEN_VALUE   0xFFFFFFFF
+#define TIMER_LIST_EMPTY      0xFFFF
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/**
+ * START of Section TIMERSERVER_CONTEXT
+ */
+
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile TimerContext_t aTimerContext[CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER];
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint8_t CurrentRunningTimerID;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint8_t PreviousRunningTimerID;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint32_t SSRValueOnLastSetup;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile WakeupTimerLimitation_Status_t  WakeupTimerLimitation;
+
+/**
+ * END of Section TIMERSERVER_CONTEXT
+ */
+
+static RTC_HandleTypeDef *phrtc;  /**< RTC handle */
+static uint8_t  WakeupTimerDivider;
+static uint8_t  AsynchPrescalerUserConfig;
+static uint16_t SynchPrescalerUserConfig;
+static volatile uint16_t MaxWakeupTimerSetup;
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void RestartWakeupCounter(uint16_t Value);
+static uint16_t ReturnTimeElapsed(void);
+static void RescheduleTimerList(void);
+static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR);
+static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID);
+static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID);
+static uint16_t linkTimer(uint8_t TimerID);
+static uint32_t ReadRtcSsrValue(void);
+
+__weak void HW_TS_RTC_CountUpdated_AppNot(void);
+
+/* Functions Definition ------------------------------------------------------*/
+
+/**
+ * @brief  Read the RTC_SSR value
+ *         As described in the reference manual, the RTC_SSR shall be read twice to ensure
+ *         reliability of the value
+ * @param  None
+ * @retval SSR value read
+ */
+static uint32_t ReadRtcSsrValue(void)
+{
+  uint32_t first_read;
+  uint32_t second_read;
+
+  first_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+
+  second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+
+  while(first_read != second_read)
+  {
+    first_read = second_read;
+
+    second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+  }
+
+  return second_read;
+}
+
+/**
+ * @brief  Insert a Timer in the list after the Timer ID specified
+ * @param  TimerID:   The ID of the Timer
+ * @param  RefTimerID: The ID of the Timer to be linked after
+ * @retval None
+ */
+static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID)
+{
+  uint8_t next_id;
+
+  next_id = aTimerContext[RefTimerID].NextID;
+
+  if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    aTimerContext[next_id].PreviousID = TimerID;
+  }
+  aTimerContext[TimerID].NextID = next_id;
+  aTimerContext[TimerID].PreviousID = RefTimerID ;
+  aTimerContext[RefTimerID].NextID = TimerID;
+
+  return;
+}
+
+/**
+ * @brief  Insert a Timer in the list before the ID specified
+ * @param  TimerID:   The ID of the Timer
+ * @param  RefTimerID: The ID of the Timer to be linked before
+ * @retval None
+ */
+static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID)
+{
+  uint8_t previous_id;
+
+  if(RefTimerID != CurrentRunningTimerID)
+  {
+    previous_id = aTimerContext[RefTimerID].PreviousID;
+
+    aTimerContext[previous_id].NextID = TimerID;
+    aTimerContext[TimerID].NextID = RefTimerID;
+    aTimerContext[TimerID].PreviousID = previous_id ;
+    aTimerContext[RefTimerID].PreviousID = TimerID;
+  }
+  else
+  {
+    aTimerContext[TimerID].NextID = RefTimerID;
+    aTimerContext[RefTimerID].PreviousID = TimerID;
+  }
+
+  return;
+}
+
+/**
+ * @brief  Insert a Timer in the list
+ * @param  TimerID:   The ID of the Timer
+ * @retval None
+ */
+static uint16_t linkTimer(uint8_t TimerID)
+{
+  uint32_t time_left;
+  uint16_t time_elapsed;
+  uint8_t timer_id_lookup;
+  uint8_t next_id;
+
+  if(CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    /**
+     * No timer in the list
+     */
+    PreviousRunningTimerID = CurrentRunningTimerID;
+    CurrentRunningTimerID = TimerID;
+    aTimerContext[TimerID].NextID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;
+
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+    time_elapsed = 0;
+  }
+  else
+  {
+    time_elapsed = ReturnTimeElapsed();
+
+    /**
+     * update count of the timer to be linked
+     */
+    aTimerContext[TimerID].CountLeft += time_elapsed;
+    time_left = aTimerContext[TimerID].CountLeft;
+
+    /**
+     * Search for index where the new timer shall be linked
+     */
+    if(aTimerContext[CurrentRunningTimerID].CountLeft <= time_left)
+    {
+      /**
+       * Search for the ID after the first one
+       */
+      timer_id_lookup = CurrentRunningTimerID;
+      next_id = aTimerContext[timer_id_lookup].NextID;
+      while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left))
+      {
+        timer_id_lookup = aTimerContext[timer_id_lookup].NextID;
+        next_id = aTimerContext[timer_id_lookup].NextID;
+      }
+
+      /**
+       * Link after the ID
+       */
+      LinkTimerAfter(TimerID, timer_id_lookup);
+    }
+    else
+    {
+      /**
+       * Link before the first ID
+       */
+      LinkTimerBefore(TimerID, CurrentRunningTimerID);
+      PreviousRunningTimerID = CurrentRunningTimerID;
+      CurrentRunningTimerID = TimerID;
+    }
+  }
+
+  return time_elapsed;
+}
+
+/**
+ * @brief  Remove a Timer from the list
+ * @param  TimerID:   The ID of the Timer
+ * @param  RequestReadSSR: Request to read the SSR register or not
+ * @retval None
+ */
+static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR)
+{
+  uint8_t previous_id;
+  uint8_t next_id;
+
+  if(TimerID == CurrentRunningTimerID)
+  {
+    PreviousRunningTimerID = CurrentRunningTimerID;
+    CurrentRunningTimerID = aTimerContext[TimerID].NextID;
+  }
+  else
+  {
+    previous_id = aTimerContext[TimerID].PreviousID;
+    next_id = aTimerContext[TimerID].NextID;
+
+    aTimerContext[previous_id].NextID = aTimerContext[TimerID].NextID;
+    if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+    {
+      aTimerContext[next_id].PreviousID = aTimerContext[TimerID].PreviousID;
+    }
+  }
+
+  /**
+   * Timer is out of the list
+   */
+  aTimerContext[TimerID].TimerIDStatus = TimerID_Created;
+
+  if((CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (RequestReadSSR == SSR_Read_Requested))
+  {
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+  }
+
+  return;
+}
+
+/**
+ * @brief  Return the number of ticks counted by the wakeuptimer since it has been started
+ * @note  The API is reading the SSR register to get how many ticks have been counted
+ *        since the time the timer has been started
+ * @param  None
+ * @retval Time expired in Ticks
+ */
+static uint16_t ReturnTimeElapsed(void)
+{
+  uint32_t  return_value;
+  uint32_t  wrap_counter;
+
+  if(SSRValueOnLastSetup != SSR_FORBIDDEN_VALUE)
+  {
+    return_value = ReadRtcSsrValue(); /**< Read SSR register first */
+
+    if (SSRValueOnLastSetup >= return_value)
+    {
+      return_value = SSRValueOnLastSetup - return_value;
+    }
+    else
+    {
+      wrap_counter = SynchPrescalerUserConfig - return_value;
+      return_value = SSRValueOnLastSetup + wrap_counter;
+    }
+
+    /**
+     * At this stage, ReturnValue holds the number of ticks counted by SSR
+     * Need to translate in number of ticks counted by the Wakeuptimer
+     */
+    return_value = return_value*AsynchPrescalerUserConfig;
+    return_value = return_value >> WakeupTimerDivider;
+  }
+  else
+  {
+    return_value = 0;
+  }
+
+  return (uint16_t)return_value;
+}
+
+/**
+ * @brief  Set the wakeup counter
+ * @note  The API is writing the counter value so that the value is decreased by one to cope with the fact
+ *    the interrupt is generated with 1 extra clock cycle (See RefManuel)
+ *    It assumes all condition are met to be allowed to write the wakeup counter
+ * @param  Value: Value to be written in the counter
+ * @retval None
+ */
+static void RestartWakeupCounter(uint16_t Value)
+{
+  /**
+   * The wakeuptimer has been disabled in the calling function to reduce the time to poll the WUTWF
+   * FLAG when the new value will have to be written
+   *  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);
+   */
+
+  if(Value == 0)
+  {
+    SSRValueOnLastSetup = ReadRtcSsrValue();
+
+    /**
+     * Simulate that the Timer expired
+     */
+    HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
+  }
+  else
+  {
+    if((Value > 1) ||(WakeupTimerDivider != 1))
+    {
+      Value -= 1;
+    }
+
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+    /**
+     * make sure to clear the flags after checking the WUTWF.
+     * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+     * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+     * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+     * due to the autoreload feature
+     */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+    HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);   /**<  Clear pending bit in NVIC */
+
+    MODIFY_REG(RTC->WUTR, RTC_WUTR_WUT, Value);
+
+    /**
+     * Update the value here after the WUTWF polling that may take some time
+     */
+    SSRValueOnLastSetup = ReadRtcSsrValue();
+
+    __HAL_RTC_WAKEUPTIMER_ENABLE(phrtc);    /**<  Enable the Wakeup Timer */
+
+    HW_TS_RTC_CountUpdated_AppNot();
+  }
+
+  return ;
+}
+
+/**
+ * @brief  Reschedule the list of timer
+ * @note  1) Update the count left for each timer in the list
+ *    2) Setup the wakeuptimer
+ * @param  None
+ * @retval None
+ */
+static void RescheduleTimerList(void)
+{
+  uint8_t   localTimerID;
+  uint32_t  timecountleft;
+  uint16_t  wakeup_timer_value;
+  uint16_t  time_elapsed;
+
+  /**
+   * The wakeuptimer is disabled now to reduce the time to poll the WUTWF
+   * FLAG when the new value will have to be written
+   */
+  if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+  {
+    /**
+     * Wait for the flag to be back to 0 when the wakeup timer is enabled
+     */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == SET);
+  }
+  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);   /**<  Disable the Wakeup Timer */
+
+  localTimerID = CurrentRunningTimerID;
+
+  /**
+   * Calculate what will be the value to write in the wakeuptimer
+   */
+  timecountleft = aTimerContext[localTimerID].CountLeft;
+
+  /**
+   * Read how much has been counted
+   */
+  time_elapsed = ReturnTimeElapsed();
+
+  if(timecountleft < time_elapsed )
+  {
+    /**
+     * There is no tick left to count
+     */
+    wakeup_timer_value = 0;
+    WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+  }
+  else
+  {
+    if(timecountleft > (time_elapsed + MaxWakeupTimerSetup))
+    {
+      /**
+       * The number of tick left is greater than the Wakeuptimer maximum value
+       */
+      wakeup_timer_value = MaxWakeupTimerSetup;
+
+      WakeupTimerLimitation = WakeupTimerValue_Overpassed;
+    }
+    else
+    {
+      wakeup_timer_value = timecountleft - time_elapsed;
+      WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+    }
+
+  }
+
+  /**
+   * update ticks left to be counted for each timer
+   */
+  while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    if (aTimerContext[localTimerID].CountLeft < time_elapsed)
+    {
+      aTimerContext[localTimerID].CountLeft = 0;
+    }
+    else
+    {
+      aTimerContext[localTimerID].CountLeft -= time_elapsed;
+    }
+    localTimerID = aTimerContext[localTimerID].NextID;
+  }
+
+  /**
+   * Write next count
+   */
+  RestartWakeupCounter(wakeup_timer_value);
+
+  return ;
+}
+
+/* Public functions ----------------------------------------------------------*/
+
+/**
+ * For all public interface except that may need write access to the RTC, the RTC
+ * shall be unlock at the beginning and locked at the output
+ * In order to ease maintainability, the unlock is done at the top and the lock at then end
+ * in case some new implementation is coming in the future
+ */
+
+void HW_TS_RTC_Wakeup_Handler(void)
+{
+  HW_TS_pTimerCb_t ptimer_callback;
+  uint32_t timer_process_id;
+  uint8_t local_current_running_timer_id;
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  /**
+   * Disable the Wakeup Timer
+   * This may speed up a bit the processing to wait the timer to be disabled
+   * The timer is still counting 2 RTCCLK
+   */
+  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);
+
+  local_current_running_timer_id = CurrentRunningTimerID;
+
+  if(aTimerContext[local_current_running_timer_id].TimerIDStatus == TimerID_Running)
+  {
+    ptimer_callback = aTimerContext[local_current_running_timer_id].pTimerCallBack;
+    timer_process_id = aTimerContext[local_current_running_timer_id].TimerProcessID;
+
+    /**
+     * It should be good to check whether the TimeElapsed is greater or not than the tick left to be counted
+     * However, due to the inaccuracy of the reading of the time elapsed, it may return there is 1 tick
+     * to be left whereas the count is over
+     * A more secure implementation has been done with a flag to state whereas the full count has been written
+     * in the wakeuptimer or not
+     */
+    if(WakeupTimerLimitation != WakeupTimerValue_Overpassed)
+    {
+      if(aTimerContext[local_current_running_timer_id].TimerMode == hw_ts_Repeated)
+      {
+        UnlinkTimer(local_current_running_timer_id, SSR_Read_Not_Requested);
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+        __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+        HW_TS_Start(local_current_running_timer_id, aTimerContext[local_current_running_timer_id].CounterInit);
+
+        /* Disable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+      }
+      else
+      {
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+        __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+        HW_TS_Stop(local_current_running_timer_id);
+
+        /* Disable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+      }
+
+      HW_TS_RTC_Int_AppNot(timer_process_id, local_current_running_timer_id, ptimer_callback);
+    }
+    else
+    {
+      RescheduleTimerList();
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+      __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+    }
+  }
+  else
+  {
+    /**
+     * We should never end up in this case
+     * However, if due to any bug in the timer server this is the case, the mistake may not impact the user.
+     * We could just clean the interrupt flag and get out from this unexpected interrupt
+     */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+    /**
+     * make sure to clear the flags after checking the WUTWF.
+     * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+     * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+     * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+     * due to the autoreload feature
+     */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  return;
+}
+
+void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *hrtc)
+{
+  uint8_t loop;
+  uint32_t localmaxwakeuptimersetup;
+
+  /**
+   * Get RTC handler
+   */
+  phrtc = hrtc;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
+
+  /**
+   * Readout the user config
+   */
+  WakeupTimerDivider = (4 - ((uint32_t)(READ_BIT(RTC->CR, RTC_CR_WUCKSEL))));
+
+  AsynchPrescalerUserConfig = (uint8_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_A) >> (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)) + 1;
+
+  SynchPrescalerUserConfig = (uint16_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_S)) + 1;
+
+  /**
+   *  Margin is taken to avoid wrong calculation when the wrap around is there and some
+   *  application interrupts may have delayed the reading
+   */
+  localmaxwakeuptimersetup = ((((SynchPrescalerUserConfig - 1)*AsynchPrescalerUserConfig) - CFG_HW_TS_RTC_HANDLER_MAX_DELAY) >> WakeupTimerDivider);
+
+  if(localmaxwakeuptimersetup >= 0xFFFF)
+  {
+    MaxWakeupTimerSetup = 0xFFFF;
+  }
+  else
+  {
+    MaxWakeupTimerSetup = (uint16_t)localmaxwakeuptimersetup;
+  }
+
+  /**
+   * Configure EXTI module
+   */
+  LL_EXTI_EnableRisingTrig_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+  LL_EXTI_EnableIT_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+
+  if(TimerInitMode == hw_ts_InitMode_Full)
+  {
+    WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+
+    /**
+     * Initialize the timer server
+     */
+    for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++)
+    {
+      aTimerContext[loop].TimerIDStatus = TimerID_Free;
+    }
+
+    CurrentRunningTimerID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;   /**<  Set ID to non valid value */
+
+    __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);                       /**<  Disable the Wakeup Timer */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);     /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module  */
+    HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);       /**<  Clear pending bit in NVIC  */
+    __HAL_RTC_WAKEUPTIMER_ENABLE_IT(phrtc, RTC_IT_WUT);         /**<  Enable interrupt in RTC module  */
+  }
+  else
+  {
+    if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTF) != RESET)
+    {
+      /**
+       * Simulate that the Timer expired
+       */
+      HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_SetPriority(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO);   /**<  Set NVIC priority */
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+  return;
+}
+
+HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pftimeout_handler)
+{
+  HW_TS_ReturnStatus_t localreturnstatus;
+  uint8_t loop = 0;
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  while((loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[loop].TimerIDStatus != TimerID_Free))
+  {
+    loop++;
+  }
+
+  if(loop != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    aTimerContext[loop].TimerIDStatus = TimerID_Created;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+    aTimerContext[loop].TimerProcessID = TimerProcessID;
+    aTimerContext[loop].TimerMode = TimerMode;
+    aTimerContext[loop].pTimerCallBack = pftimeout_handler;
+    *pTimerId = loop;
+
+    localreturnstatus = hw_ts_Successful;
+  }
+  else
+  {
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+    localreturnstatus = hw_ts_Failed;
+  }
+
+  return(localreturnstatus);
+}
+
+void HW_TS_Delete(uint8_t timer_id)
+{
+  HW_TS_Stop(timer_id);
+
+  aTimerContext[timer_id].TimerIDStatus = TimerID_Free; /**<  release ID */
+
+  return;
+}
+
+void HW_TS_Stop(uint8_t timer_id)
+{
+  uint8_t localcurrentrunningtimerid;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);    /**<  Disable NVIC */
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
+  {
+    UnlinkTimer(timer_id, SSR_Read_Requested);
+    localcurrentrunningtimerid = CurrentRunningTimerID;
+
+    if(localcurrentrunningtimerid == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+    {
+      /**
+       * List is empty
+       */
+
+      /**
+       * Disable the timer
+       */
+      if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+      {
+        /**
+         * Wait for the flag to be back to 0 when the wakeup timer is enabled
+         */
+        while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == SET);
+      }
+      __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);   /**<  Disable the Wakeup Timer */
+
+      while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+      /**
+       * make sure to clear the flags after checking the WUTWF.
+       * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+       * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+       * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+       * due to the autoreload feature
+       */
+      __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+      __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+      HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);   /**<  Clear pending bit in NVIC */
+    }
+    else if(PreviousRunningTimerID != localcurrentrunningtimerid)
+    {
+      RescheduleTimerList();
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+  return;
+}
+
+void HW_TS_Start(uint8_t timer_id, uint32_t timeout_ticks)
+{
+  uint16_t time_elapsed;
+  uint8_t localcurrentrunningtimerid;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+  if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
+  {
+    HW_TS_Stop( timer_id );
+  }
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);    /**<  Disable NVIC */
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  aTimerContext[timer_id].TimerIDStatus = TimerID_Running;
+
+  aTimerContext[timer_id].CountLeft = timeout_ticks;
+  aTimerContext[timer_id].CounterInit = timeout_ticks;
+
+  time_elapsed =  linkTimer(timer_id);
+
+  localcurrentrunningtimerid = CurrentRunningTimerID;
+
+  if(PreviousRunningTimerID != localcurrentrunningtimerid)
+  {
+    RescheduleTimerList();
+  }
+  else
+  {
+    aTimerContext[timer_id].CountLeft -= time_elapsed;
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+  return;
+}
+
+uint16_t HW_TS_RTC_ReadLeftTicksToCount(void)
+{
+  uint32_t primask_bit;
+  uint16_t return_value, auro_reload_value, elapsed_time_value;
+
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();                /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+
+  if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+  {
+    auro_reload_value = (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT));
+
+    elapsed_time_value = ReturnTimeElapsed();
+
+    if(auro_reload_value > elapsed_time_value)
+    {
+      return_value = auro_reload_value - elapsed_time_value;
+    }
+    else
+    {
+      return_value = 0;
+    }
+  }
+  else
+  {
+    return_value = TIMER_LIST_EMPTY;
+  }
+
+  __set_PRIMASK(primask_bit);     /**< Restore PRIMASK bit*/
+
+  return (return_value);
+}
+
+__weak void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack)
+{
+  pTimerCallBack();
+
+  return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/hw_uart.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/hw_uart.c
new file mode 100644
index 000000000..9a553610d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/hw_uart.c
@@ -0,0 +1,318 @@
+/**
+ ******************************************************************************
+  * File Name          : Src/hw_uart.c
+  * Description        : HW UART source file for STM32WPAN Middleware.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "hw_conf.h"
+#if (CFG_HW_LPUART1_ENABLED == 1)
+extern UART_HandleTypeDef hlpuart1;
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+extern UART_HandleTypeDef huart1;
+#endif
+
+/* Macros --------------------------------------------------------------------*/
+#define HW_UART_RX_IT(__HANDLE__, __USART_BASE__)                                                   \
+        do{                                                                                         \
+            HW_##__HANDLE__##RxCb = cb;                                                             \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            HAL_UART_Receive_IT(&(__HANDLE__), p_data, size);                                       \
+        } while(0)
+
+#define HW_UART_TX_IT(__HANDLE__, __USART_BASE__)                                                   \
+        do{                                                                                         \
+            HW_##__HANDLE__##TxCb = cb;                                                             \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            HAL_UART_Transmit_IT(&(__HANDLE__), p_data, size);                                      \
+        } while(0)
+
+#define HW_UART_TX(__HANDLE__, __USART_BASE__)                                                      \
+        do{                                                                                         \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            hal_status = HAL_UART_Transmit(&(__HANDLE__), p_data, size, timeout);                   \
+        } while(0)
+
+/* Variables -----------------------------------------------------------------*/
+#if (CFG_HW_USART1_ENABLED == 1)
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+    DMA_HandleTypeDef HW_hdma_huart1_tx ={0};
+#endif
+    void (*HW_huart1RxCb)(void);
+    void (*HW_huart1TxCb)(void);
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+    DMA_HandleTypeDef HW_hdma_hlpuart1_tx ={0};
+#endif
+    void (*HW_hlpuart1RxCb)(void);
+    void (*HW_hlpuart1TxCb)(void);
+#endif
+
+void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_RX_IT(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_RX_IT(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  void (*cb)(void))
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_TX_IT(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_TX_IT(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout)
+{
+    HAL_StatusTypeDef hal_status = HAL_OK;
+    hw_status_t hw_status = hw_uart_ok;
+
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_TX(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_TX(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    switch (hal_status)
+    {
+        case HAL_OK:
+            hw_status = hw_uart_ok;
+            break;
+
+        case HAL_ERROR:
+            hw_status = hw_uart_error;
+            break;
+
+        case HAL_BUSY:
+            hw_status = hw_uart_busy;
+            break;
+
+        case HAL_TIMEOUT:
+            hw_status = hw_uart_to;
+            break;
+
+        default:
+            break;
+    }
+
+    return hw_status;
+}
+
+hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+{
+    HAL_StatusTypeDef hal_status = HAL_OK;
+    hw_status_t hw_status = hw_uart_ok;
+
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_huart1TxCb = cb;
+            huart1.Instance = USART1;
+            hal_status = HAL_UART_Transmit_DMA(&huart1, p_data, size);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_hlpuart1TxCb = cb;
+            hlpuart1.Instance = LPUART1;
+            hal_status = HAL_UART_Transmit_DMA(&hlpuart1, p_data, size);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    switch (hal_status)
+    {
+        case HAL_OK:
+            hw_status = hw_uart_ok;
+            break;
+
+        case HAL_ERROR:
+            hw_status = hw_uart_error;
+            break;
+
+        case HAL_BUSY:
+            hw_status = hw_uart_busy;
+            break;
+
+        case HAL_TIMEOUT:
+            hw_status = hw_uart_to;
+            break;
+
+        default:
+            break;
+    }
+
+    return hw_status;
+}
+
+void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HAL_UART_IRQHandler(&huart1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HAL_UART_IRQHandler(&hlpuart1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+        case hw_uart1:
+            HAL_DMA_IRQHandler(huart1.hdmatx);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+        case hw_lpuart1:
+            HAL_DMA_IRQHandler(hlpuart1.hdmatx);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+    switch ((uint32_t)huart->Instance)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case (uint32_t)USART1:
+            if(HW_huart1RxCb)
+            {
+                HW_huart1RxCb();
+            }
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case (uint32_t)LPUART1:
+            if(HW_hlpuart1RxCb)
+            {
+                HW_hlpuart1RxCb();
+            }
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+    switch ((uint32_t)huart->Instance)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case (uint32_t)USART1:
+            if(HW_huart1TxCb)
+            {
+                HW_huart1TxCb();
+            }
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case (uint32_t)LPUART1:
+            if(HW_hlpuart1TxCb)
+            {
+                HW_hlpuart1TxCb();
+            }
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/main.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/main.c
new file mode 100644
index 000000000..b4c3d4dd6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/main.c
@@ -0,0 +1,641 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    main.c
+ * @author  MCD Application Team
+ * @brief   BLE application with BLE core
+ *
+  @verbatim
+  ==============================================================================
+                    ##### IMPORTANT NOTE #####
+  ==============================================================================
+
+  This application requests having the stm32wb5x_BLE_Stack_fw.bin binary
+  flashed on the Wireless Coprocessor.
+  If it is not the case, you need to use STM32CubeProgrammer to load the appropriate
+  binary.
+
+  All available binaries are located under following directory:
+  /Projects/STM32_Copro_Wireless_Binaries
+
+  Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+  Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the
+  detailed procedure to change the Wireless Coprocessor binary.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "app_entry.h"
+#include "app_common.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "stm32_lpm.h"
+#include "stm32_seq.h"
+#include "dbg_trace.h"
+#include "hw_conf.h"
+#include "otp.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef hlpuart1;
+UART_HandleTypeDef huart1;
+DMA_HandleTypeDef hdma_lpuart1_tx;
+DMA_HandleTypeDef hdma_usart1_tx;
+
+RTC_HandleTypeDef hrtc;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+void MX_LPUART1_UART_Init(void);
+void MX_USART1_UART_Init(void);
+static void MX_RF_Init(void);
+static void MX_RTC_Init(void);
+/* USER CODE BEGIN PFP */
+void PeriphClock_Config(void);
+static void Reset_Device( void );
+static void Reset_IPCC( void );
+static void Reset_BackupDomain( void );
+static void Init_Exti( void );
+static void Config_HSE(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+  
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+  Reset_Device();
+  Config_HSE();
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  PeriphClock_Config();
+  Init_Exti(); /**< Configure the system Power Mode */
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_RF_Init();
+  MX_RTC_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Init code for STM32_WPAN */  
+  APPE_Init();
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+	while(1)
+	{
+		UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure LSE Drive Capability 
+  */
+  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE
+                              |RCC_OSCILLATORTYPE_LSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RFWAKEUP
+                              |RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1
+                              |RCC_PERIPHCLK_LPUART1;
+  PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+  PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* USER CODE BEGIN Smps */
+
+#if (CFG_USE_SMPS != 0)
+  /**
+   *  Configure and enable SMPS
+   *
+   *  The SMPS configuration is not yet supported by CubeMx
+   */
+  LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
+  LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
+  LL_PWR_SMPS_Enable();
+#endif
+
+  /* USER CODE END Smps */
+
+
+}
+
+/**
+  * @brief LPUART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+void MX_LPUART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN LPUART1_Init 0 */
+
+  /* USER CODE END LPUART1_Init 0 */
+
+  /* USER CODE BEGIN LPUART1_Init 1 */
+
+  /* USER CODE END LPUART1_Init 1 */
+  hlpuart1.Instance = LPUART1;
+  hlpuart1.Init.BaudRate = 115200;
+  hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
+  hlpuart1.Init.StopBits = UART_STOPBITS_1;
+  hlpuart1.Init.Parity = UART_PARITY_NONE;
+  hlpuart1.Init.Mode = UART_MODE_TX_RX;
+  hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  hlpuart1.FifoMode = UART_FIFOMODE_DISABLE;
+  if (HAL_UART_Init(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN LPUART1_Init 2 */
+
+  /* USER CODE END LPUART1_Init 2 */
+
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_8;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+  * @brief RF Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RF_Init(void)
+{
+
+  /* USER CODE BEGIN RF_Init 0 */
+
+  /* USER CODE END RF_Init 0 */
+
+  /* USER CODE BEGIN RF_Init 1 */
+
+  /* USER CODE END RF_Init 1 */
+  /* USER CODE BEGIN RF_Init 2 */
+
+  /* USER CODE END RF_Init 2 */
+
+}
+
+/**
+  * @brief RTC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RTC_Init(void)
+{
+
+  /* USER CODE BEGIN RTC_Init 0 */
+
+  /* USER CODE END RTC_Init 0 */
+
+  /* USER CODE BEGIN RTC_Init 1 */
+
+  /* USER CODE END RTC_Init 1 */
+  /** Initialize RTC Only 
+  */
+  hrtc.Instance = RTC;
+  hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
+  hrtc.Init.AsynchPrediv = CFG_RTC_ASYNCH_PRESCALER;
+  hrtc.Init.SynchPrediv = CFG_RTC_SYNCH_PRESCALER;
+  hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
+  hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+  hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+  if (HAL_RTC_Init(&hrtc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN RTC_Init 2 */
+  /* Disable RTC registers write protection */
+  LL_RTC_DisableWriteProtection(RTC);
+
+  LL_RTC_WAKEUP_SetClock(RTC, CFG_RTC_WUCKSEL_DIVIDER);
+
+  /* Enable RTC registers write protection */
+  LL_RTC_EnableWriteProtection(RTC);
+  /* USER CODE END RTC_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
+  __HAL_RCC_DMA2_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
+  /* DMA2_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA2_Channel4_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(DMA2_Channel4_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+void PeriphClock_Config(void)
+{
+  #if (CFG_USB_INTERFACE_ENABLE != 0)
+	RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
+	RCC_CRSInitTypeDef RCC_CRSInitStruct = { 0 };
+
+    /**
+    * This prevents the CPU2 to disable the HSI48 oscillator when
+    * it does not use anymore the RNG IP
+    */
+    LL_HSEM_1StepLock( HSEM, 5 );
+
+    LL_RCC_HSI48_Enable();
+
+	while(!LL_RCC_HSI48_IsReady());
+
+	/* Select HSI48 as USB clock source */
+	PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+	PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+	HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+	/*Configure the clock recovery system (CRS)**********************************/
+
+	/* Enable CRS Clock */
+	__HAL_RCC_CRS_CLK_ENABLE();
+
+	/* Default Synchro Signal division factor (not divided) */
+	RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+
+	/* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+	RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+
+	/* HSI48 is synchronized with USB SOF at 1KHz rate */
+	RCC_CRSInitStruct.ReloadValue = RCC_CRS_RELOADVALUE_DEFAULT;
+	RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+
+	RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+
+	/* Set the TRIM[5:0] to the default value*/
+	RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+
+	/* Start automatic synchronization */
+	HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+#endif
+
+	return;
+}
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+
+static void Config_HSE(void)
+{
+    OTP_ID0_t * p_otp;
+
+  /**
+   * Read HSE_Tuning from OTP
+   */
+  p_otp = (OTP_ID0_t *) OTP_Read(0);
+  if (p_otp)
+  {
+    LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
+  }
+
+  return;
+}  
+
+
+static void Reset_Device( void )
+{
+#if ( CFG_HW_RESET_BY_FW == 1 )
+	Reset_BackupDomain();
+
+	Reset_IPCC();
+#endif
+
+	return;
+}
+
+static void Reset_IPCC( void )
+{
+	LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
+
+	LL_C1_IPCC_ClearFlag_CHx(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_ClearFlag_CHx(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C1_IPCC_DisableTransmitChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_DisableTransmitChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C1_IPCC_DisableReceiveChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_DisableReceiveChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	return;
+}
+
+static void Reset_BackupDomain( void )
+{
+	if ((LL_RCC_IsActiveFlag_PINRST() != FALSE) && (LL_RCC_IsActiveFlag_SFTRST() == FALSE))
+	{
+		HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+		/**
+		 *  Write twice the value to flush the APB-AHB bridge
+		 *  This bit shall be written in the register before writing the next one
+		 */
+		HAL_PWR_EnableBkUpAccess();
+
+		__HAL_RCC_BACKUPRESET_FORCE();
+		__HAL_RCC_BACKUPRESET_RELEASE();
+	}
+
+	return;
+}
+
+static void Init_Exti( void )
+{
+  /**< Disable all wakeup interrupt on CPU1  except IPCC(36), HSEM(38) */
+  LL_EXTI_DisableIT_0_31(~0);
+  LL_EXTI_DisableIT_32_63( (~0) & (~(LL_EXTI_LINE_36 | LL_EXTI_LINE_38)) );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += HAL_GetTickFreq();
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+  {
+    /************************************************************************************
+     * ENTER SLEEP MODE
+     ***********************************************************************************/
+    LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+    /**
+     * This option is used to ensure that store operations are completed
+     */
+  #if defined ( __CC_ARM)
+    __force_stores();
+  #endif
+
+    __WFI( );
+  }
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/stm32_lpm_if.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/stm32_lpm_if.c
new file mode 100644
index 000000000..1418e0a36
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/stm32_lpm_if.c
@@ -0,0 +1,297 @@
+/* USER CODE BEGIN Header */
+/**
+ ***************************************************************************************
+  * File Name          : stm32_lpm_if.c
+  * Description        : Low layer function to enter/exit low power modes (stop, sleep).
+ ***************************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+  
+/* Includes ------------------------------------------------------------------*/  
+#include "stm32_lpm_if.h"
+#include "stm32_lpm.h"
+#include "app_conf.h"
+/* USER CODE BEGIN include */
+
+/* USER CODE END include */
+
+/* Exported variables --------------------------------------------------------*/
+const struct UTIL_LPM_Driver_s UTIL_PowerDriver = 
+{
+  PWR_EnterSleepMode,
+  PWR_ExitSleepMode,
+  
+  PWR_EnterStopMode,
+  PWR_ExitStopMode, 
+  
+  PWR_EnterOffMode,
+  PWR_ExitOffMode,
+};
+
+/* Private function prototypes -----------------------------------------------*/
+static void Switch_On_HSI( void );
+/* USER CODE BEGIN Private_Function_Prototypes */
+
+/* USER CODE END Private_Function_Prototypes */
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN Private_Typedef */
+
+/* USER CODE END Private_Typedef */
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Private_Define */
+
+/* USER CODE END Private_Define */
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Private_Macro */
+
+/* USER CODE END Private_Macro */
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN Private_Variables */
+
+/* USER CODE END Private_Variables */
+
+/* Functions Definition ------------------------------------------------------*/
+/**
+  * @brief Enters Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_EnterOffMode( void )
+{
+/* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
+  /************************************************************************************
+   * ENTER OFF MODE
+   ***********************************************************************************/
+  /*
+   * There is no risk to clear all the WUF here because in the current implementation, this API is called
+   * in critical section. If an interrupt occurs while in that critical section before that point,
+   * the flag is set and will be cleared here but the system will not enter Off Mode
+   * because an interrupt is pending in the NVIC. The ISR will be executed when moving out
+   * of this critical section
+   */
+  LL_PWR_ClearFlag_WU( );
+
+  LL_PWR_SetPowerMode( LL_PWR_MODE_STANDBY );
+
+  LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores( );
+#endif
+
+  __WFI( );
+/* USER CODE END PWR_EnterOffMode */
+}
+
+/**
+  * @brief Exits Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_ExitOffMode( void )
+{
+/* USER CODE BEGIN PWR_ExitOffMode */
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitOffMode */
+}
+
+/**
+  * @brief Enters Low Power Stop Mode
+  * @note ARM exists the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterStopMode( void )
+{
+/* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
+  /**
+   * This function is called from CRITICAL SECTION
+   */
+  while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
+
+  if ( ! LL_HSEM_1StepLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID ) )
+  {
+    if( LL_PWR_IsActiveFlag_C2DS( ) )
+    {
+      /* Release ENTRY_STOP_MODE semaphore */
+      LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
+
+      /**
+       * The switch on HSI before entering Stop Mode is required on Cut2.0
+       * It is useless from Cut2.1
+       */
+      Switch_On_HSI( );
+    }
+  }
+  else
+  {
+    /**
+     * The switch on HSI before entering Stop Mode is required on Cut2.0
+     * It is useless from Cut2.1
+     */
+    Switch_On_HSI( );
+  }
+
+  /* Release RCC semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  /************************************************************************************
+   * ENTER STOP MODE
+   ***********************************************************************************/
+  LL_PWR_SetPowerMode( LL_PWR_MODE_STOP2 );
+
+  LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores( );
+#endif
+
+  __WFI();
+/* USER CODE END PWR_EnterStopMode */
+}
+
+/**
+  * @brief Exits Low Power Stop Mode
+  * @note Enable the pll at 32MHz
+  * @param none
+  * @retval none
+  */
+void PWR_ExitStopMode( void )
+{
+/* USER CODE BEGIN PWR_ExitStopMode */
+  /**
+   * This function is called from CRITICAL SECTION
+   */
+
+  /* Release ENTRY_STOP_MODE semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
+
+  while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
+
+  if(LL_RCC_GetSysClkSource( ) == LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+    LL_RCC_HSE_Enable( );
+    while(!LL_RCC_HSE_IsReady( ));
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
+    while (LL_RCC_GetSysClkSource( ) != LL_RCC_SYS_CLKSOURCE_STATUS_HSE);
+  }
+  else
+  {
+    /**
+     * As long as the current application is fine with HSE as system clock source,
+     * there is nothing to do here
+     */
+  }
+
+  /* Release RCC semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitStopMode */
+}
+
+/**
+  * @brief Enters Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterSleepMode( void )
+{
+/* USER CODE BEGIN PWR_EnterSleepMode */
+
+  HAL_SuspendTick();
+
+  /************************************************************************************
+   * ENTER SLEEP MODE
+   ***********************************************************************************/
+  LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+
+  __WFI( );
+/* USER CODE END PWR_EnterSleepMode */
+}
+
+/**
+  * @brief Exits Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_ExitSleepMode( void )
+{
+/* USER CODE BEGIN PWR_ExitSleepMode */
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitSleepMode */
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+  * @brief Switch the system clock on HSI
+  * @param none
+  * @retval none
+  */
+static void Switch_On_HSI( void )
+{
+  LL_RCC_HSI_Enable( );
+  while(!LL_RCC_HSI_IsReady( ));
+  LL_RCC_SetSysClkSource( LL_RCC_SYS_CLKSOURCE_HSI );
+  LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSI);
+  while (LL_RCC_GetSysClkSource( ) != LL_RCC_SYS_CLKSOURCE_STATUS_HSI);
+}
+
+/* USER CODE BEGIN Private_Functions */
+
+/* USER CODE END Private_Functions */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..f22ad0f38
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,329 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32wbxx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_lpuart1_tx;
+
+extern DMA_HandleTypeDef hdma_usart1_tx;
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_HSEM_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  HAL_DMA_MuxSyncConfigTypeDef pSyncConfig;
+  if(huart->Instance==LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspInit 0 */
+
+  /* USER CODE END LPUART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_LPUART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**LPUART1 GPIO Configuration    
+    PA2     ------> LPUART1_TX
+    PA3     ------> LPUART1_RX
+    PA6     ------> LPUART1_CTS 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* LPUART1 DMA Init */
+    /* LPUART1_TX Init */
+    hdma_lpuart1_tx.Instance = DMA1_Channel4;
+    hdma_lpuart1_tx.Init.Request = DMA_REQUEST_LPUART1_TX;
+    hdma_lpuart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_lpuart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_lpuart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_lpuart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_lpuart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_lpuart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_lpuart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_lpuart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    pSyncConfig.SyncSignalID = HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT;
+    pSyncConfig.SyncPolarity = HAL_DMAMUX_SYNC_NO_EVENT;
+    pSyncConfig.SyncEnable = DISABLE;
+    pSyncConfig.EventEnable = DISABLE;
+    pSyncConfig.RequestNumber = 1;
+    if (HAL_DMAEx_ConfigMuxSync(&hdma_lpuart1_tx, &pSyncConfig) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmatx,hdma_lpuart1_tx);
+
+    /* LPUART1 interrupt Init */
+    HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(LPUART1_IRQn);
+  /* USER CODE BEGIN LPUART1_MspInit 1 */
+
+  /* USER CODE END LPUART1_MspInit 1 */
+  }
+  else if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspInit 0 */
+
+  /* USER CODE END USART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**USART1 GPIO Configuration    
+    PA11     ------> USART1_CTS
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_11;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* USART1 DMA Init */
+    /* USART1_TX Init */
+    hdma_usart1_tx.Instance = DMA2_Channel4;
+    hdma_usart1_tx.Init.Request = DMA_REQUEST_USART1_TX;
+    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx);
+
+    /* USART1 interrupt Init */
+    HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspInit 1 */
+
+  /* USER CODE END USART1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspDeInit 0 */
+
+  /* USER CODE END LPUART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_LPUART1_CLK_DISABLE();
+  
+    /**LPUART1 GPIO Configuration    
+    PA2     ------> LPUART1_TX
+    PA3     ------> LPUART1_RX
+    PA6     ------> LPUART1_CTS 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_6);
+
+    /* LPUART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmatx);
+
+    /* LPUART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(LPUART1_IRQn);
+  /* USER CODE BEGIN LPUART1_MspDeInit 1 */
+
+  /* USER CODE END LPUART1_MspDeInit 1 */
+  }
+  else if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+  /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+  
+    /**USART1 GPIO Configuration    
+    PA11     ------> USART1_CTS
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11);
+
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
+
+    /* USART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmatx);
+
+    /* USART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+  /* USER CODE END USART1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspInit 0 */
+  HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+  /**
+  *  Write twice the value to flush the APB-AHB bridge
+  *  This bit shall be written in the register before writing the next one
+  */
+  HAL_PWR_EnableBkUpAccess();
+
+  __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); /**< Select LSI as RTC Input */
+  /* USER CODE END RTC_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_RTC_ENABLE();
+  /* USER CODE BEGIN RTC_MspInit 1 */
+  HAL_RTCEx_EnableBypassShadow(hrtc);
+  /* USER CODE END RTC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspDeInit 0 */
+
+  /* USER CODE END RTC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RTC_DISABLE();
+  /* USER CODE BEGIN RTC_MspDeInit 1 */
+
+  /* USER CODE END RTC_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..d469f29ab
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/stm32wbxx_it.c
@@ -0,0 +1,315 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_lpuart1_tx;
+extern DMA_HandleTypeDef hdma_usart1_tx;
+extern UART_HandleTypeDef hlpuart1;
+extern UART_HandleTypeDef huart1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles DMA1 channel4 global interrupt.
+  */
+void DMA1_Channel4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_lpuart1_tx);
+  /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel4_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+
+  /* USER CODE END USART1_IRQn 0 */
+  HAL_UART_IRQHandler(&huart1);
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles LPUART1 global interrupt.
+  */
+void LPUART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN LPUART1_IRQn 0 */
+
+  /* USER CODE END LPUART1_IRQn 0 */
+  HAL_UART_IRQHandler(&hlpuart1);
+  /* USER CODE BEGIN LPUART1_IRQn 1 */
+
+  /* USER CODE END LPUART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA2 channel4 global interrupt.
+  */
+void DMA2_Channel4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2_Channel4_IRQn 0 */
+
+  /* USER CODE END DMA2_Channel4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart1_tx);
+  /* USER CODE BEGIN DMA2_Channel4_IRQn 1 */
+
+  /* USER CODE END DMA2_Channel4_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW1_EXTI_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW2_EXTI_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW2_PIN);
+}
+
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW3_EXTI_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW3_PIN);
+}
+
+void RTC_WKUP_IRQHandler(void)
+{
+  HW_TS_RTC_Wakeup_Handler();
+}
+
+void IPCC_C1_TX_IRQHandler(void)
+{
+  HW_IPCC_Tx_Handler();
+
+  return;
+}
+
+void IPCC_C1_RX_IRQHandler(void)
+{
+  HW_IPCC_Rx_Handler();
+  return;
+}
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..156ed20d3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/Core/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                        4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/BLE_HeartRate.ewd b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/BLE_HeartRate.ewd
new file mode 100644
index 000000000..f35bb1a61
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/BLE_HeartRate.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		BLE_HeartRate
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/BLE_HeartRate.ewp b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/BLE_HeartRate.ewp
new file mode 100644
index 000000000..a988910ff
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/BLE_HeartRate.ewp
@@ -0,0 +1,1258 @@
+
+
+  3
+  
+    BLE_HeartRate
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        30
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$\startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        Core
+        
+          $PROJ_DIR$\..\Core\Src\main.c
+        
+        
+          $PROJ_DIR$\..\Core\Src\app_debug.c
+        
+        
+          $PROJ_DIR$\..\Core\Src\app_entry.c
+        
+        
+          $PROJ_DIR$\..\Core\Src\stm32_lpm_if.c
+        
+        
+          $PROJ_DIR$\..\Core\Src\hw_timerserver.c
+        
+        
+          $PROJ_DIR$\..\Core\Src\hw_uart.c
+        
+        
+          $PROJ_DIR$\..\Core\Src\stm32wbxx_it.c
+        
+        
+          $PROJ_DIR$\..\Core\Src\stm32wbxx_hal_msp.c
+        
+      
+      
+        STM32_WPAN
+        
+          App
+          
+            $PROJ_DIR$\..\STM32_WPAN\App\app_ble.c
+          
+          
+            $PROJ_DIR$\..\STM32_WPAN\App\dis_app.c
+          
+          
+            $PROJ_DIR$\..\STM32_WPAN\App\hrs_app.c
+          
+        
+        
+          Target
+          
+            $PROJ_DIR$\..\STM32_WPAN\Target\hw_ipcc.c
+          
+        
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$\..\readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$\..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE\nucleo_wb35ce.c
+        
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$\..\Core\Src\system_stm32wbxx.c
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_ipcc.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_uart.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_uart_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rtc.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rtc_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal.c
+      
+    
+  
+  
+    Middlewares
+    
+      STM32_WPAN
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\hci_tl_if.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\shci_tl_if.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\tl_mbox.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\shci\shci.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\dbg_trace.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\otp.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\stm_list.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\stm_queue.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\template\osal.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\svc\Src\svc_ctl.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\svc\Src\dis.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\svc\Src\hrs.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_gap_aci.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_gatt_aci.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_hal_aci.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_hci_le.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_l2cap_aci.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\hci_tl.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\shci_tl.c
+      
+    
+  
+    
+        Utilities
+        
+            $PROJ_DIR$\..\..\..\..\..\..\Utilities\lpm\tiny_lpm\stm32_lpm.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\..\..\Utilities\sequencer\stm32_seq.c
+        
+    
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/Project.eww
new file mode 100644
index 000000000..032302caf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\BLE_HeartRate.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..8f3317a41
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/app_ble.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/app_ble.c
new file mode 100644
index 000000000..85a925fc2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/app_ble.c
@@ -0,0 +1,1099 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    app_ble.c
+ * @author  MCD Application Team
+ * @brief   BLE Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+#include "app_common.h"
+
+#include "dbg_trace.h"
+#include "ble.h"
+#include "tl.h"
+#include "app_ble.h"
+
+#include "stm32_seq.h"
+#include "shci.h"
+#include "stm32_lpm.h"
+#include "otp.h"
+#include "dis_app.h"
+#include "hrs_app.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+
+/**
+ * security parameters structure
+ */ 
+typedef struct _tSecurityParams
+{
+  /**
+   * IO capability of the device
+   */
+  uint8_t ioCapability;
+
+  /**
+   * Authentication requirement of the device
+   * Man In the Middle protection required?
+   */
+  uint8_t mitm_mode;
+
+  /**
+   * bonding mode of the device
+   */
+  uint8_t bonding_mode;
+
+  /**
+   * Flag to tell whether OOB data has
+   * to be used during the pairing process
+   */
+  uint8_t OOB_Data_Present; 
+
+  /**
+   * OOB data to be used in the pairing process if
+   * OOB_Data_Present is set to TRUE
+   */
+  uint8_t OOB_Data[16]; 
+
+  /**
+   * this variable indicates whether to use a fixed pin
+   * during the pairing process or a passkey has to be
+   * requested to the application during the pairing process
+   * 0 implies use fixed pin and 1 implies request for passkey
+   */
+  uint8_t Use_Fixed_Pin; 
+
+  /**
+   * minimum encryption key size requirement
+   */
+  uint8_t encryptionKeySizeMin;
+
+  /**
+   * maximum encryption key size requirement
+   */
+  uint8_t encryptionKeySizeMax;
+
+  /**
+   * fixed pin to be used in the pairing process if
+   * Use_Fixed_Pin is set to 1
+   */
+  uint32_t Fixed_Pin;
+
+  /**
+   * this flag indicates whether the host has to initiate
+   * the security, wait for pairing or does not have any security
+   * requirements.\n
+   * 0x00 : no security required
+   * 0x01 : host should initiate security by sending the slave security
+   *        request command
+   * 0x02 : host need not send the clave security request but it
+   * has to wait for paiirng to complete before doing any other
+   * processing
+   */
+  uint8_t initiateSecurity;
+}tSecurityParams;
+
+/**
+ * global context
+ * contains the variables common to all 
+ * services
+ */ 
+typedef struct _tBLEProfileGlobalContext
+{
+
+  /**
+   * security requirements of the host
+   */ 
+  tSecurityParams bleSecurityParam;
+
+  /**
+   * gap service handle
+   */
+  uint16_t gapServiceHandle;
+
+  /**
+   * device name characteristic handle
+   */ 
+  uint16_t devNameCharHandle;
+
+  /**
+   * appearance characteristic handle
+   */ 
+  uint16_t appearanceCharHandle;
+
+  /**
+   * connection handle of the current active connection
+   * When not in connection, the handle is set to 0xFFFF
+   */ 
+  uint16_t connectionHandle;
+
+  /**
+   * length of the UUID list to be used while advertising
+   */ 
+  uint8_t advtServUUIDlen;
+
+  /**
+   * the UUID list to be used while advertising
+   */ 
+  uint8_t advtServUUID[100];
+
+}BleGlobalContext_t;
+
+typedef struct
+{
+  BleGlobalContext_t BleApplicationContext_legacy;
+   APP_BLE_ConnStatus_t Device_Connection_Status;
+   /**
+   * ID of the Advertising Timeout
+   */
+   uint8_t Advertising_mgr_timer_Id;
+
+}BleApplicationContext_t;
+/* USER CODE BEGIN PTD */
+  
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+#define APPBLE_GAP_DEVICE_NAME_LENGTH 7
+#define FAST_ADV_TIMEOUT               (30*1000*1000/CFG_TS_TICK_VAL) /**< 30s */
+#define INITIAL_ADV_TIMEOUT            (60*1000*1000/CFG_TS_TICK_VAL) /**< 60s */
+
+#define BD_ADDR_SIZE_LOCAL    6
+
+/* USER CODE BEGIN PD */
+#define LED_ON_TIMEOUT                 (0.005*1000*1000/CFG_TS_TICK_VAL) /**< 5ms */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static TL_CmdPacket_t BleCmdBuffer;
+
+static const uint8_t M_bd_addr[BD_ADDR_SIZE_LOCAL] =
+    {
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x0000000000FF)),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x00000000FF00) >> 8),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x000000FF0000) >> 16),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x0000FF000000) >> 24),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x00FF00000000) >> 32),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0xFF0000000000) >> 40)
+    };
+
+static uint8_t bd_addr_udn[BD_ADDR_SIZE_LOCAL];
+
+/**
+*   Identity root key used to derive LTK and CSRK 
+*/
+static const uint8_t BLE_CFG_IR_VALUE[16] = CFG_BLE_IRK;
+
+/**
+* Encryption root key used to derive LTK and CSRK
+*/
+static const uint8_t BLE_CFG_ER_VALUE[16] = CFG_BLE_ERK;
+
+/**
+ * These are the two tags used to manage a power failure during OTA
+ * The MagicKeywordAdress shall be mapped @0x140 from start of the binary image
+ * The MagicKeywordvalue is checked in the ble_ota application
+ */
+PLACE_IN_SECTION("TAG_OTA_END") const uint32_t MagicKeywordValue = 0x94448A29 ;
+PLACE_IN_SECTION("TAG_OTA_START") const uint32_t MagicKeywordAddress = (uint32_t)&MagicKeywordValue;
+
+PLACE_IN_SECTION("BLE_APP_CONTEXT") static BleApplicationContext_t BleApplicationContext;
+PLACE_IN_SECTION("BLE_APP_CONTEXT") static uint16_t AdvIntervalMin, AdvIntervalMax;
+
+static const char local_name[] = { AD_TYPE_COMPLETE_LOCAL_NAME ,'H','R','S','T','M'};
+uint8_t  manuf_data[14] = {
+    sizeof(manuf_data)-1, AD_TYPE_MANUFACTURER_SPECIFIC_DATA,
+    0x01/*SKD version */,
+    0x00 /* Generic*/,
+    0x00 /* GROUP A Feature  */, 
+    0x00 /* GROUP A Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00, /* BLE MAC start -MSB */
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00, /* BLE MAC stop */
+
+};
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+static void BLE_UserEvtRx( void * pPayload );
+static void BLE_StatusNot( HCI_TL_CmdStatus_t status );
+static void Ble_Tl_Init( void );
+static void Ble_Hci_Gap_Gatt_Init(void);
+static const uint8_t* BleGetBdAddress( void );
+static void Adv_Request( APP_BLE_ConnStatus_t New_Status );
+static void Add_Advertisment_Service_UUID( uint16_t servUUID );
+static void Adv_Mgr( void );
+static void Adv_Update( void );
+
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APP_BLE_Init( void )
+{
+/* USER CODE BEGIN APP_BLE_Init_1 */
+
+/* USER CODE END APP_BLE_Init_1 */
+  SHCI_C2_Ble_Init_Cmd_Packet_t ble_init_cmd_packet =
+  {
+    {{0,0,0}},                          /**< Header unused */
+    {0,                                 /** pBleBufferAddress not used */
+    0,                                  /** BleBufferSize not used */
+    CFG_BLE_NUM_GATT_ATTRIBUTES,
+    CFG_BLE_NUM_GATT_SERVICES,
+    CFG_BLE_ATT_VALUE_ARRAY_SIZE,
+    CFG_BLE_NUM_LINK,
+    CFG_BLE_DATA_LENGTH_EXTENSION,
+    CFG_BLE_PREPARE_WRITE_LIST_SIZE,
+    CFG_BLE_MBLOCK_COUNT,
+    CFG_BLE_MAX_ATT_MTU,
+    CFG_BLE_SLAVE_SCA,
+    CFG_BLE_MASTER_SCA,
+    CFG_BLE_LSE_SOURCE,
+    CFG_BLE_MAX_CONN_EVENT_LENGTH,
+    CFG_BLE_HSE_STARTUP_TIME,
+    CFG_BLE_VITERBI_MODE,
+    CFG_BLE_LL_ONLY,
+    0}
+  };
+
+  /**
+   * Initialize Ble Transport Layer
+   */
+  Ble_Tl_Init( );
+
+  /**
+   * Do not allow standby in the application
+   */
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP_BLE, UTIL_LPM_DISABLE);
+
+  /**
+   * Register the hci transport layer to handle BLE User Asynchronous Events
+   */
+  UTIL_SEQ_RegTask( 1<data;
+
+  switch (event_pckt->evt)
+  {
+    case EVT_DISCONN_COMPLETE:
+    {
+      hci_disconnection_complete_event_rp0 *disconnection_complete_event;
+      disconnection_complete_event = (hci_disconnection_complete_event_rp0 *) event_pckt->data;
+
+      if (disconnection_complete_event->Connection_Handle == BleApplicationContext.BleApplicationContext_legacy.connectionHandle)
+      {
+        BleApplicationContext.BleApplicationContext_legacy.connectionHandle = 0;
+        BleApplicationContext.Device_Connection_Status = APP_BLE_IDLE;
+
+        APP_DBG_MSG("\r\n\r** DISCONNECTION EVENT WITH CLIENT \n");
+      }
+
+      /* restart advertising */
+      Adv_Request(APP_BLE_FAST_ADV);
+      /* USER CODE BEGIN EVT_DISCONN_COMPLETE */
+
+      /* USER CODE END EVT_DISCONN_COMPLETE */
+    }
+
+    break; /* EVT_DISCONN_COMPLETE */
+
+    case EVT_LE_META_EVENT:
+    {
+      meta_evt = (evt_le_meta_event*) event_pckt->data;
+      /* USER CODE BEGIN EVT_LE_META_EVENT */
+
+      /* USER CODE END EVT_LE_META_EVENT */
+      switch (meta_evt->subevent)
+      {
+        case EVT_LE_CONN_UPDATE_COMPLETE: 
+          APP_DBG_MSG("\r\n\r** CONNECTION UPDATE EVENT WITH CLIENT \n");
+
+          /* USER CODE BEGIN EVT_LE_CONN_UPDATE_COMPLETE */
+
+          /* USER CODE END EVT_LE_CONN_UPDATE_COMPLETE */
+          break;
+        case EVT_LE_PHY_UPDATE_COMPLETE:
+          APP_DBG_MSG("EVT_UPDATE_PHY_COMPLETE \n");
+
+          evt_le_phy_update_complete = (hci_le_phy_update_complete_event_rp0*)meta_evt->data;
+          if (evt_le_phy_update_complete->Status == 0)
+          {
+            APP_DBG_MSG("EVT_UPDATE_PHY_COMPLETE, status ok \n");
+          }
+          else
+          {
+            APP_DBG_MSG("EVT_UPDATE_PHY_COMPLETE, status nok \n");
+          }
+          ret = hci_le_read_phy(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,&TX_PHY,&RX_PHY);
+          if (ret == BLE_STATUS_SUCCESS)
+          {
+            APP_DBG_MSG("Read_PHY success \n");
+           
+            if ((TX_PHY == TX_2M) && (RX_PHY == RX_2M))
+            {
+              APP_DBG_MSG("PHY Param  TX= %d, RX= %d \n", TX_PHY, RX_PHY);
+            }
+            else
+            {
+              APP_DBG_MSG("PHY Param  TX= %d, RX= %d \n", TX_PHY, RX_PHY);
+            } 
+          }
+          else
+          {
+            APP_DBG_MSG("Read conf not succeess \n");
+          }
+          /* USER CODE BEGIN EVT_LE_PHY_UPDATE_COMPLETE */
+
+          /* USER CODE END EVT_LE_PHY_UPDATE_COMPLETE */          
+          break;
+        case EVT_LE_CONN_COMPLETE:
+          {
+          hci_le_connection_complete_event_rp0 *connection_complete_event;
+
+          /**
+           * The connection is done, there is no need anymore to schedule the LP ADV
+           */
+          connection_complete_event = (hci_le_connection_complete_event_rp0 *) meta_evt->data;
+          
+          HW_TS_Stop(BleApplicationContext.Advertising_mgr_timer_Id);
+
+          APP_DBG_MSG("EVT_LE_CONN_COMPLETE for connection handle 0x%x\n",
+          connection_complete_event->Connection_Handle);
+
+            if (BleApplicationContext.Device_Connection_Status == APP_BLE_LP_CONNECTING)
+            {
+              /* Connection as client */
+              BleApplicationContext.Device_Connection_Status = APP_BLE_CONNECTED_CLIENT;
+            }
+            else
+            {
+              /* Connection as server */
+              BleApplicationContext.Device_Connection_Status = APP_BLE_CONNECTED_SERVER;
+            }
+            BleApplicationContext.BleApplicationContext_legacy.connectionHandle =
+                connection_complete_event->Connection_Handle;
+          /* USER CODE BEGIN HCI_EVT_LE_CONN_COMPLETE */
+
+          /* USER CODE END HCI_EVT_LE_CONN_COMPLETE */
+          }
+        break; /* HCI_EVT_LE_CONN_COMPLETE */
+
+        default:
+          /* USER CODE BEGIN SUBEVENT_DEFAULT */
+
+          /* USER CODE END SUBEVENT_DEFAULT */
+          break;
+      }
+    }
+    break; /* HCI_EVT_LE_META_EVENT */
+
+    case EVT_VENDOR:
+      blue_evt = (evt_blue_aci*) event_pckt->data;
+      /* USER CODE BEGIN EVT_VENDOR */
+
+      /* USER CODE END EVT_VENDOR */
+      switch (blue_evt->ecode)
+      {
+      /* USER CODE BEGIN ecode */
+        aci_gap_pairing_complete_event_rp0 *pairing_complete;
+
+      case EVT_BLUE_GAP_LIMITED_DISCOVERABLE: 
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_LIMITED_DISCOVERABLE \n");
+          break; /* EVT_BLUE_GAP_LIMITED_DISCOVERABLE */
+          
+      case EVT_BLUE_GAP_PASS_KEY_REQUEST:  
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_PASS_KEY_REQUEST \n");
+
+        aci_gap_pass_key_resp(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,123456);
+
+        APP_DBG_MSG("\r\n\r** aci_gap_pass_key_resp \n");
+          break; /* EVT_BLUE_GAP_PASS_KEY_REQUEST */
+
+      case EVT_BLUE_GAP_AUTHORIZATION_REQUEST:    
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_AUTHORIZATION_REQUEST \n");
+          break; /* EVT_BLUE_GAP_AUTHORIZATION_REQUEST */
+
+      case EVT_BLUE_GAP_SLAVE_SECURITY_INITIATED:   
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_SLAVE_SECURITY_INITIATED \n");
+          break; /* EVT_BLUE_GAP_SLAVE_SECURITY_INITIATED */
+
+      case EVT_BLUE_GAP_BOND_LOST:    
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_BOND_LOST \n");
+          aci_gap_allow_rebond(BleApplicationContext.BleApplicationContext_legacy.connectionHandle);
+        APP_DBG_MSG("\r\n\r** Send allow rebond \n");
+          break; /* EVT_BLUE_GAP_BOND_LOST */
+
+      case EVT_BLUE_GAP_DEVICE_FOUND:  
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_DEVICE_FOUND \n");
+          break; /* EVT_BLUE_GAP_DEVICE_FOUND */
+
+      case EVT_BLUE_GAP_ADDR_NOT_RESOLVED:
+         APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_DEVICE_FOUND \n");
+          break; /* EVT_BLUE_GAP_DEVICE_FOUND */
+      
+      case (EVT_BLUE_GAP_KEYPRESS_NOTIFICATION):
+         APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_KEYPRESS_NOTIFICATION \n");
+          break; /* EVT_BLUE_GAP_KEY_PRESS_NOTIFICATION */    
+
+       case (EVT_BLUE_GAP_NUMERIC_COMPARISON_VALUE):
+          APP_DBG_MSG("numeric_value = %d\n",
+                      ((aci_gap_numeric_comparison_value_event_rp0 *)(blue_evt->data))->Numeric_Value);
+
+          APP_DBG_MSG("Hex_value = %x\n",
+                      ((aci_gap_numeric_comparison_value_event_rp0 *)(blue_evt->data))->Numeric_Value);
+
+          aci_gap_numeric_comparison_value_confirm_yesno(BleApplicationContext.BleApplicationContext_legacy.connectionHandle, 1); /* CONFIRM_YES = 1 */
+
+          APP_DBG_MSG("\r\n\r** aci_gap_numeric_comparison_value_confirm_yesno-->YES \n");
+          break;
+
+          case (EVT_BLUE_GAP_PAIRING_CMPLT):
+          {
+            pairing_complete = (aci_gap_pairing_complete_event_rp0*)blue_evt->data;
+
+            APP_DBG_MSG("BLE_CTRL_App_Notification: EVT_BLUE_GAP_PAIRING_CMPLT, pairing_complete->Status = %d\n",pairing_complete->Status);
+            if (pairing_complete->Status == 0)
+            {
+              APP_DBG_MSG("\r\n\r** Pairing OK \n");
+            }
+            else
+            {
+              APP_DBG_MSG("\r\n\r** Pairing KO \n");
+            }
+          }
+           break;    
+
+      /* USER CODE END ecode */
+        case EVT_BLUE_GAP_PROCEDURE_COMPLETE:
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_PROCEDURE_COMPLETE \n");
+        /* USER CODE BEGIN EVT_BLUE_GAP_PROCEDURE_COMPLETE */
+
+        /* USER CODE END EVT_BLUE_GAP_PROCEDURE_COMPLETE */
+        break; /* EVT_BLUE_GAP_PROCEDURE_COMPLETE */
+      }
+      break; /* EVT_VENDOR */
+
+        default:
+        /* USER CODE BEGIN ECODE_DEFAULT*/
+
+        /* USER CODE END ECODE_DEFAULT*/
+          break;
+  }
+
+  return (SVCCTL_UserEvtFlowEnable);
+}
+
+APP_BLE_ConnStatus_t APP_BLE_Get_Server_Connection_Status(void)
+{
+    return BleApplicationContext.Device_Connection_Status;
+}
+
+/* USER CODE BEGIN FD*/
+void APP_BLE_Key_Button1_Action(void)
+{
+  tBleStatus ret = BLE_STATUS_INVALID_PARAMS;
+  ret = aci_gap_clear_security_db();
+      if (ret == BLE_STATUS_SUCCESS)
+      {
+        APP_DBG_MSG("Successfully aci_gap_clear_security_db()\n");
+      }
+      else
+      {
+        APP_DBG_MSG("aci_gap_clear_security_db() Failed , result: %d \n", ret);
+      }
+}
+
+void APP_BLE_Key_Button2_Action(void)
+{
+  tBleStatus ret = BLE_STATUS_INVALID_PARAMS;
+  ret = aci_gap_slave_security_req(BleApplicationContext.BleApplicationContext_legacy.connectionHandle); 
+  if (ret == BLE_STATUS_SUCCESS)
+      {
+        APP_DBG_MSG("Successfully aci_gap_slave_security_req()");
+      }
+      else
+      {
+        APP_DBG_MSG("aci_gap_slave_security_req() Failed , result: %d \n", ret);
+      }
+}
+  
+void APP_BLE_Key_Button3_Action(void)
+{
+  uint8_t TX_PHY, RX_PHY;
+  tBleStatus ret = BLE_STATUS_INVALID_PARAMS;
+  ret = hci_le_read_phy(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,&TX_PHY,&RX_PHY);
+      if (ret == BLE_STATUS_SUCCESS)
+      {
+        APP_DBG_MSG("Read_PHY success \n");
+        APP_DBG_MSG("PHY Param  TX= %d, RX= %d \n", TX_PHY, RX_PHY);
+        if ((TX_PHY == TX_2M) && (RX_PHY == RX_2M))
+        {
+          APP_DBG_MSG("hci_le_set_phy PHY Param  TX= %d, RX= %d \n", TX_1M, RX_1M);
+          ret = hci_le_set_phy(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,ALL_PHYS_PREFERENCE,TX_1M,RX_1M,0);
+        }
+        else
+        {
+          APP_DBG_MSG("hci_le_set_phy PHY Param  TX= %d, RX= %d \n", TX_2M_PREFERRED, RX_2M_PREFERRED);
+          ret = hci_le_set_phy(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,ALL_PHYS_PREFERENCE,TX_2M_PREFERRED,RX_2M_PREFERRED,0);
+        } 
+      }
+      else
+      {
+        APP_DBG_MSG("Read conf not succeess \n");
+}
+
+        if (ret == BLE_STATUS_SUCCESS)
+        {
+          APP_DBG_MSG("set PHY cmd ok\n");
+        }
+        else 
+{
+          APP_DBG_MSG("set PHY cmd NOK\n");
+        }
+}
+
+/* USER CODE END FD*/
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void Ble_Tl_Init( void )
+{
+  HCI_TL_HciInitConf_t Hci_Tl_Init_Conf;
+
+  Hci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&BleCmdBuffer;
+  Hci_Tl_Init_Conf.StatusNotCallBack = BLE_StatusNot;
+  hci_init(BLE_UserEvtRx, (void*) &Hci_Tl_Init_Conf);
+
+  return;
+}
+
+ static void Ble_Hci_Gap_Gatt_Init(void){
+
+  uint8_t role;
+  uint8_t index;
+  uint16_t gap_service_handle, gap_dev_name_char_handle, gap_appearance_char_handle;
+  const uint8_t *bd_addr;
+  uint32_t srd_bd_addr[2];
+  uint16_t appearance[1] = { BLE_CFG_GAP_APPEARANCE }; 
+
+  /**
+   * Initialize HCI layer
+   */
+  /*HCI Reset to synchronise BLE Stack*/
+  hci_reset();
+
+  /**
+   * Write the BD Address
+   */
+
+  bd_addr = BleGetBdAddress();
+  aci_hal_write_config_data(CONFIG_DATA_PUBADDR_OFFSET,
+                            CONFIG_DATA_PUBADDR_LEN,
+                            (uint8_t*) bd_addr);
+
+  /* BLE MAC in ADV Packet */
+  manuf_data[ sizeof(manuf_data)-6] = bd_addr[5];
+  manuf_data[ sizeof(manuf_data)-5] = bd_addr[4];
+  manuf_data[ sizeof(manuf_data)-4] = bd_addr[3];
+  manuf_data[ sizeof(manuf_data)-3] = bd_addr[2];
+  manuf_data[ sizeof(manuf_data)-2] = bd_addr[1];
+  manuf_data[ sizeof(manuf_data)-1] = bd_addr[0];
+  
+  /**
+   * Write Identity root key used to derive LTK and CSRK 
+   */
+    aci_hal_write_config_data(CONFIG_DATA_IR_OFFSET,
+    CONFIG_DATA_IR_LEN,
+                            (uint8_t*) BLE_CFG_IR_VALUE);
+    
+   /**
+   * Write Encryption root key used to derive LTK and CSRK
+   */
+    aci_hal_write_config_data(CONFIG_DATA_ER_OFFSET,
+    CONFIG_DATA_ER_LEN,
+                            (uint8_t*) BLE_CFG_ER_VALUE);
+
+   /**
+   * Write random bd_address
+   */
+   /* random_bd_address = R_bd_address;
+    aci_hal_write_config_data(CONFIG_DATA_RANDOM_ADDRESS_WR,
+    CONFIG_DATA_RANDOM_ADDRESS_LEN,
+                            (uint8_t*) random_bd_address);
+  */
+
+  /**
+   * Static random Address
+   * The two upper bits shall be set to 1
+   * The lowest 32bits is read from the UDN to differentiate between devices
+   * The RNG may be used to provide a random number on each power on
+   */
+  srd_bd_addr[1] =  0x0000ED6E;
+  srd_bd_addr[0] =  LL_FLASH_GetUDN( );
+  aci_hal_write_config_data( CONFIG_DATA_RANDOM_ADDRESS_OFFSET, CONFIG_DATA_RANDOM_ADDRESS_LEN, (uint8_t*)srd_bd_addr );
+
+  /**
+   * Write Identity root key used to derive LTK and CSRK 
+   */
+    aci_hal_write_config_data( CONFIG_DATA_IR_OFFSET, CONFIG_DATA_IR_LEN, (uint8_t*)BLE_CFG_IR_VALUE );
+    
+   /**
+   * Write Encryption root key used to derive LTK and CSRK
+   */
+    aci_hal_write_config_data( CONFIG_DATA_ER_OFFSET, CONFIG_DATA_ER_LEN, (uint8_t*)BLE_CFG_ER_VALUE );
+
+  /**
+   * Set TX Power to 0dBm.
+   */
+  aci_hal_set_tx_power_level(1, CFG_TX_POWER);
+
+  /**
+   * Initialize GATT interface
+   */
+  aci_gatt_init();
+
+  /**
+   * Initialize GAP interface
+   */
+  role = 0;
+
+#if (BLE_CFG_PERIPHERAL == 1)
+  role |= GAP_PERIPHERAL_ROLE;
+#endif
+
+#if (BLE_CFG_CENTRAL == 1)
+  role |= GAP_CENTRAL_ROLE;
+#endif
+
+  if (role > 0)
+  {
+    const char *name = "STM32WB";
+    aci_gap_init(role, 0,
+                 APPBLE_GAP_DEVICE_NAME_LENGTH,
+                 &gap_service_handle, &gap_dev_name_char_handle, &gap_appearance_char_handle);
+
+    if (aci_gatt_update_char_value(gap_service_handle, gap_dev_name_char_handle, 0, strlen(name), (uint8_t *) name))
+    {
+      BLE_DBG_SVCCTL_MSG("Device Name aci_gatt_update_char_value failed.\n");
+    }
+  }
+
+  if(aci_gatt_update_char_value(gap_service_handle,
+                                gap_appearance_char_handle,
+                                0,
+                                2,
+                                (uint8_t *)&appearance))
+  {
+    BLE_DBG_SVCCTL_MSG("Appearance aci_gatt_update_char_value failed.\n");
+  }
+/**
+   * Initialize Default PHY
+   */
+  hci_le_set_default_phy(ALL_PHYS_PREFERENCE,TX_2M_PREFERRED,RX_2M_PREFERRED); 
+
+  /**
+   * Initialize IO capability
+   */
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.ioCapability = CFG_IO_CAPABILITY;
+  aci_gap_set_io_capability(BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.ioCapability);
+
+  /**
+   * Initialize authentication
+   */
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode = CFG_MITM_PROTECTION;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data_Present = 0;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin = 8;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax = 16;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin = 1;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin = 111111;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode = 1;
+  for (index = 0; index < 16; index++)
+  {
+    BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data[index] = (uint8_t) index;
+  }
+
+  aci_gap_set_authentication_requirement(BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode,
+                                         1,
+                                         0,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin,
+                                         0
+                                        );
+
+  /**
+   * Initialize whitelist
+   */
+   if (BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode)
+   {
+     aci_gap_configure_whitelist();
+   }
+}
+
+static void Adv_Request(APP_BLE_ConnStatus_t New_Status)
+{
+  tBleStatus ret = BLE_STATUS_INVALID_PARAMS;
+  uint16_t Min_Inter, Max_Inter;
+ 
+  if (New_Status == APP_BLE_FAST_ADV)
+  {
+    Min_Inter = AdvIntervalMin;
+    Max_Inter = AdvIntervalMax;
+  }
+  else
+  {
+    Min_Inter = CFG_LP_CONN_ADV_INTERVAL_MIN;
+    Max_Inter = CFG_LP_CONN_ADV_INTERVAL_MAX;
+  }
+
+    /**
+     * Stop the timer, it will be restarted for a new shot
+     * It does not hurt if the timer was not running
+     */
+    HW_TS_Stop(BleApplicationContext.Advertising_mgr_timer_Id);
+
+    APP_DBG_MSG("First index in %d state \n", BleApplicationContext.Device_Connection_Status);
+
+    if ((New_Status == APP_BLE_LP_ADV)
+        && ((BleApplicationContext.Device_Connection_Status == APP_BLE_FAST_ADV)
+            || (BleApplicationContext.Device_Connection_Status == APP_BLE_LP_ADV)))
+    {
+      /* Connection in ADVERTISE mode have to stop the current advertising */
+      ret = aci_gap_set_non_discoverable();
+      if (ret == BLE_STATUS_SUCCESS)
+      {
+        APP_DBG_MSG("Successfully Stopped Advertising \n");
+      }
+      else
+      {
+        APP_DBG_MSG("Stop Advertising Failed , result: %d \n", ret);
+      }
+    }
+
+    BleApplicationContext.Device_Connection_Status = New_Status;
+    /* Start Fast or Low Power Advertising */
+    ret = aci_gap_set_discoverable(
+        ADV_IND,
+        Min_Inter,
+        Max_Inter,
+        PUBLIC_ADDR,
+        NO_WHITE_LIST_USE, /* use white list */
+        sizeof(local_name),
+        (uint8_t*) &local_name,
+        BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen,
+        BleApplicationContext.BleApplicationContext_legacy.advtServUUID,
+        0,
+        0);
+    /* Update Advertising data */
+    ret = aci_gap_update_adv_data(sizeof(manuf_data), (uint8_t*) manuf_data);
+
+     if (ret == BLE_STATUS_SUCCESS)
+    {
+      if (New_Status == APP_BLE_FAST_ADV)
+      {
+        APP_DBG_MSG("Successfully Start Fast Advertising \n" );
+        /* Start Timer to STOP ADV - TIMEOUT */
+        HW_TS_Start(BleApplicationContext.Advertising_mgr_timer_Id, INITIAL_ADV_TIMEOUT);
+      }
+      else
+      {
+        APP_DBG_MSG("Successfully Start Low Power Advertising \n");
+      }
+    }
+    else
+    {
+      if (New_Status == APP_BLE_FAST_ADV)
+      {
+        APP_DBG_MSG("Start Fast Advertising Failed , result: %d \n", ret);
+      }
+      else
+      {
+        APP_DBG_MSG("Start Low Power Advertising Failed , result: %d \n", ret);
+      }
+    }
+
+  return;
+}
+
+const uint8_t* BleGetBdAddress( void )
+{
+  uint8_t *otp_addr;
+  const uint8_t *bd_addr;
+  uint32_t udn;
+  uint32_t company_id;
+  uint32_t device_id;
+
+  udn = LL_FLASH_GetUDN();
+
+  if(udn != 0xFFFFFFFF)
+  {
+    company_id = LL_FLASH_GetSTCompanyID();
+    device_id = LL_FLASH_GetDeviceID();
+
+    bd_addr_udn[0] = (uint8_t)(udn & 0x000000FF);
+    bd_addr_udn[1] = (uint8_t)( (udn & 0x0000FF00) >> 8 );
+    bd_addr_udn[2] = (uint8_t)( (udn & 0x00FF0000) >> 16 );
+    bd_addr_udn[3] = (uint8_t)device_id;
+    bd_addr_udn[4] = (uint8_t)(company_id & 0x000000FF);;
+    bd_addr_udn[5] = (uint8_t)( (company_id & 0x0000FF00) >> 8 );
+
+    bd_addr = (const uint8_t *)bd_addr_udn;
+  }
+  else
+  {
+    otp_addr = OTP_Read(0);
+    if(otp_addr)
+    {
+      bd_addr = ((OTP_ID0_t*)otp_addr)->bd_address;
+    }
+    else
+    {
+      bd_addr = M_bd_addr;
+    }
+
+  }
+
+  return bd_addr;
+}
+
+/* USER CODE BEGIN FD_LOCAL_FUNCTION */
+
+/* USER CODE END FD_LOCAL_FUNCTION */
+
+/*************************************************************
+ *
+ *SPECIFIC FUNCTIONS
+ *
+ *************************************************************/
+static void Add_Advertisment_Service_UUID( uint16_t servUUID )
+{
+  BleApplicationContext.BleApplicationContext_legacy.advtServUUID[BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen] =
+      (uint8_t) (servUUID & 0xFF);
+  BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen++;
+  BleApplicationContext.BleApplicationContext_legacy.advtServUUID[BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen] =
+      (uint8_t) (servUUID >> 8) & 0xFF;
+  BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen++;
+
+  return;
+}
+
+static void Adv_Mgr( void )
+{
+  /**
+   * The code shall be executed in the background as an aci command may be sent
+   * The background is the only place where the application can make sure a new aci command
+   * is not sent if there is a pending one
+   */
+   UTIL_SEQ_SetTask(1 << CFG_TASK_ADV_UPDATE_ID, CFG_SCH_PRIO_0);
+
+  return;
+}
+
+static void Adv_Update( void )
+{
+  Adv_Request(APP_BLE_LP_ADV);
+
+  return;
+}
+
+/* USER CODE BEGIN FD_SPECIFIC_FUNCTIONS */
+
+/* USER CODE END FD_SPECIFIC_FUNCTIONS */
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+void hci_notify_asynch_evt(void* pdata)
+{
+  UTIL_SEQ_SetTask(1 << CFG_TASK_HCI_ASYNCH_EVT_ID, CFG_SCH_PRIO_0);
+  return;
+}
+
+void hci_cmd_resp_release(uint32_t flag)
+{
+  UTIL_SEQ_SetEvt(1 << CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID);
+  return;
+}
+
+void hci_cmd_resp_wait(uint32_t timeout)
+{
+  UTIL_SEQ_WaitEvt(1 << CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID);
+  return;
+}
+
+static void BLE_UserEvtRx( void * pPayload )
+{
+  SVCCTL_UserEvtFlowStatus_t svctl_return_status;
+  tHCI_UserEvtRxParam *pParam;
+
+  pParam = (tHCI_UserEvtRxParam *)pPayload; 
+
+  svctl_return_status = SVCCTL_UserEvtRx((void *)&(pParam->pckt->evtserial));
+  if (svctl_return_status != SVCCTL_UserEvtFlowDisable)
+  {
+    pParam->status = HCI_TL_UserEventFlow_Enable;
+  }
+  else
+  {
+    pParam->status = HCI_TL_UserEventFlow_Disable;
+  }
+}
+
+static void BLE_StatusNot( HCI_TL_CmdStatus_t status )
+{
+  uint32_t task_id_list;
+  switch (status)
+  {
+    case HCI_TL_CmdBusy:
+      /**
+       * All tasks that may send an aci/hci commands shall be listed here
+       * This is to prevent a new command is sent while one is already pending
+       */
+      task_id_list = (1 << CFG_LAST_TASK_ID_WITH_HCICMD) - 1;
+      UTIL_SEQ_PauseTask(task_id_list);
+
+      break;
+
+    case HCI_TL_CmdAvailable:
+      /**
+       * All tasks that may send an aci/hci commands shall be listed here
+       * This is to prevent a new command is sent while one is already pending
+       */
+      task_id_list = (1 << CFG_LAST_TASK_ID_WITH_HCICMD) - 1;
+      UTIL_SEQ_ResumeTask(task_id_list);
+
+      break;
+
+    default:
+      break;
+  }
+  return;
+}
+
+void SVCCTL_ResumeUserEventFlow( void )
+{
+  hci_resume_flow();
+  return;
+}
+
+/* USER CODE BEGIN FD_WRAP_FUNCTIONS */
+
+/* USER CODE END FD_WRAP_FUNCTIONS */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/app_ble.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/app_ble.h
new file mode 100644
index 000000000..657ba432b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/app_ble.h
@@ -0,0 +1,88 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    app_ble.h
+  * @author  MCD Application Team
+  * @brief   Header for ble application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_BLE_H
+#define APP_BLE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "hci_tl.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+
+    typedef enum
+    {
+      APP_BLE_IDLE,
+      APP_BLE_FAST_ADV,
+      APP_BLE_LP_ADV,
+      APP_BLE_SCAN,
+      APP_BLE_LP_CONNECTING,
+      APP_BLE_CONNECTED_SERVER,
+      APP_BLE_CONNECTED_CLIENT
+    } APP_BLE_ConnStatus_t;
+    
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */  
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APP_BLE_Init( void ); 
+
+  APP_BLE_ConnStatus_t APP_BLE_Get_Server_Connection_Status(void);
+
+/* USER CODE BEGIN EF */
+void APP_BLE_Key_Button1_Action(void);
+void APP_BLE_Key_Button2_Action(void);
+void APP_BLE_Key_Button3_Action(void);
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*APP_BLE_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/ble_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/ble_conf.h
new file mode 100644
index 000000000..2e0c37951
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/ble_conf.h
@@ -0,0 +1,104 @@
+/**
+ ******************************************************************************
+  * File Name          : App/ble_conf.h
+  * Description        : Configuration file for BLE Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef BLE_CONF_H
+#define BLE_CONF_H
+
+#include "app_conf.h"
+
+/******************************************************************************
+ *
+ * BLE SERVICES CONFIGURATION
+ * blesvc
+ *
+ ******************************************************************************/
+
+ /**
+ * This setting shall be set to '1' if the device needs to support the Peripheral Role
+ * In the MS configuration, both BLE_CFG_PERIPHERAL and BLE_CFG_CENTRAL shall be set to '1'
+ */
+#define BLE_CFG_PERIPHERAL                                                     1
+
+/**
+ * This setting shall be set to '1' if the device needs to support the Central Role
+ * In the MS configuration, both BLE_CFG_PERIPHERAL and BLE_CFG_CENTRAL shall be set to '1'
+ */
+#define BLE_CFG_CENTRAL                                                        0
+
+/**
+ * There is one handler per service enabled
+ * Note: There is no handler for the Device Information Service
+ *
+ * This shall take into account all registered handlers
+ * (from either the provided services or the custom services)
+ */
+#define BLE_CFG_SVC_MAX_NBR_CB                                                 7
+
+#define BLE_CFG_CLT_MAX_NBR_CB                                                 0
+
+/******************************************************************************
+ * Device Information Service (DIS)
+ ******************************************************************************/
+/**< Options: Supported(1) or Not Supported(0) */
+#define BLE_CFG_DIS_MANUFACTURER_NAME_STRING                                   1
+#define BLE_CFG_DIS_MODEL_NUMBER_STRING                                        0
+#define BLE_CFG_DIS_SERIAL_NUMBER_STRING                                       0
+#define BLE_CFG_DIS_HARDWARE_REVISION_STRING                                   0
+#define BLE_CFG_DIS_FIRMWARE_REVISION_STRING                                   0
+#define BLE_CFG_DIS_SOFTWARE_REVISION_STRING                                   0
+#define BLE_CFG_DIS_SYSTEM_ID                                                  0
+#define BLE_CFG_DIS_IEEE_CERTIFICATION                                         0
+#define BLE_CFG_DIS_PNP_ID                                                     0
+
+/**
+ * device information service characteristic lengths
+ */
+#define BLE_CFG_DIS_SYSTEM_ID_LEN_MAX                                        (8)
+#define BLE_CFG_DIS_MODEL_NUMBER_STRING_LEN_MAX                              (32)
+#define BLE_CFG_DIS_SERIAL_NUMBER_STRING_LEN_MAX                             (32)
+#define BLE_CFG_DIS_FIRMWARE_REVISION_STRING_LEN_MAX                         (32)
+#define BLE_CFG_DIS_HARDWARE_REVISION_STRING_LEN_MAX                         (32)
+#define BLE_CFG_DIS_SOFTWARE_REVISION_STRING_LEN_MAX                         (32)
+#define BLE_CFG_DIS_MANUFACTURER_NAME_STRING_LEN_MAX                         (32)
+#define BLE_CFG_DIS_IEEE_CERTIFICATION_LEN_MAX                               (32)
+#define BLE_CFG_DIS_PNP_ID_LEN_MAX                                           (7)
+
+/******************************************************************************
+ * Heart Rate Service (HRS)
+ ******************************************************************************/
+#define BLE_CFG_HRS_BODY_SENSOR_LOCATION_CHAR               1/**< BODY SENSOR LOCATION CHARACTERISTIC */
+#define BLE_CFG_HRS_ENERGY_EXPENDED_INFO_FLAG               1/**< ENERGY EXTENDED INFO FLAG */
+#define BLE_CFG_HRS_ENERGY_RR_INTERVAL_FLAG                 1/**< Max number of RR interval values - Shall not be greater than 9 */
+
+/******************************************************************************
+ * GAP Service - Apprearance
+ ******************************************************************************/
+
+#define BLE_CFG_UNKNOWN_APPEARANCE                  (0)
+#define BLE_CFG_HR_SENSOR_APPEARANCE                (832)
+#define BLE_CFG_GAP_APPEARANCE                      (BLE_CFG_HR_SENSOR_APPEARANCE)
+
+/******************************************************************************
+ * Over The Air Feature (OTA) - STM Proprietary
+ ******************************************************************************/
+#define BLE_CFG_OTA_REBOOT_CHAR         0/**< REBOOT OTA MODE CHARACTERISTIC */
+
+#endif /*BLE_CONF_H */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/ble_dbg_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/ble_dbg_conf.h
new file mode 100644
index 000000000..a24660c50
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/ble_dbg_conf.h
@@ -0,0 +1,199 @@
+/**
+ ******************************************************************************
+  * File Name          : App/ble_dbg_conf.h
+  * Description        : Debug configuration file for BLE Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __BLE_DBG_CONF_H
+#define __BLE_DBG_CONF_H
+
+/**
+ * Enable or Disable traces from BLE
+ */
+
+#define BLE_DBG_APP_EN             0
+#define BLE_DBG_DIS_EN             1
+#define BLE_DBG_HRS_EN             1
+#define BLE_DBG_SVCCTL_EN          1
+#define BLE_DBG_BLS_EN             0
+#define BLE_DBG_HTS_EN             0
+#define BLE_DBG_P2P_STM_EN         0
+
+/**
+ * Macro definition
+ */
+#if ( BLE_DBG_APP_EN != 0 )
+#define BLE_DBG_APP_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_APP_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_DIS_EN != 0 )
+#define BLE_DBG_DIS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_DIS_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_HRS_EN != 0 )
+#define BLE_DBG_HRS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HRS_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_P2P_STM_EN != 0 )
+#define BLE_DBG_P2P_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_P2P_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_TEMPLATE_STM_EN != 0 )
+#define BLE_DBG_TEMPLATE_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_TEMPLATE_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_EDS_STM_EN != 0 )
+#define BLE_DBG_EDS_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_EDS_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_LBS_STM_EN != 0 )
+#define BLE_DBG_LBS_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_LBS_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_SVCCTL_EN != 0 )
+#define BLE_DBG_SVCCTL_MSG          PRINT_MESG_DBG
+#else
+#define BLE_DBG_SVCCTL_MSG          PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_CTS_EN != 0)
+#define BLE_DBG_CTS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_CTS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HIDS_EN != 0)
+#define BLE_DBG_HIDS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_HIDS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_PASS_EN != 0)
+#define BLE_DBG_PASS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_PASS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_BLS_EN != 0)
+#define BLE_DBG_BLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_BLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HTS_EN != 0)
+#define BLE_DBG_HTS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HTS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_ANS_EN != 0)
+#define BLE_DBG_ANS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_ANS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_ESS_EN != 0)
+#define BLE_DBG_ESS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_ESS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_GLS_EN != 0)
+#define BLE_DBG_GLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_GLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_BAS_EN != 0)
+#define BLE_DBG_BAS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_BAS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_RTUS_EN != 0)
+#define BLE_DBG_RTUS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_RTUS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HPS_EN != 0)
+#define BLE_DBG_HPS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HPS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_TPS_EN != 0)
+#define BLE_DBG_TPS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_TPS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_LLS_EN != 0)
+#define BLE_DBG_LLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_LLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_IAS_EN != 0)
+#define BLE_DBG_IAS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_IAS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_WSS_EN != 0)
+#define BLE_DBG_WSS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_WSS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_LNS_EN != 0)
+#define BLE_DBG_LNS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_LNS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_SCPS_EN != 0)
+#define BLE_DBG_SCPS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_SCPS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_DTS_EN != 0)
+#define BLE_DBG_DTS_MSG             PRINT_MESG_DBG
+#define BLE_DBG_DTS_BUF             PRINT_LOG_BUFF_DBG
+#else
+#define BLE_DBG_DTS_MSG             PRINT_NO_MESG
+#define BLE_DBG_DTS_BUF             PRINT_NO_MESG
+#endif
+
+#endif /*__BLE_DBG_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/dis_app.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/dis_app.c
new file mode 100644
index 000000000..59c66fad3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/dis_app.c
@@ -0,0 +1,221 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    dis_app.c
+  * @author  MCD Application Team
+  * @brief   Device Information Service Application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "ble.h"
+#include "dis_app.h"
+
+/* Private includes -----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+#if ((BLE_CFG_DIS_SYSTEM_ID != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+static const uint8_t system_id[BLE_CFG_DIS_SYSTEM_ID_LEN_MAX] = 
+{
+  (uint8_t)((DISAPP_MANUFACTURER_ID & 0xFF0000) >> 16),
+  (uint8_t)((DISAPP_MANUFACTURER_ID & 0x00FF00) >> 8),
+  (uint8_t)(DISAPP_MANUFACTURER_ID & 0x0000FF),
+  0xFE,
+  0xFF,
+  (uint8_t)((DISAPP_OUI & 0xFF0000) >> 16),
+  (uint8_t)((DISAPP_OUI & 0x00FF00) >> 8),
+  (uint8_t)(DISAPP_OUI & 0x0000FF)
+};
+#endif
+
+#if ((BLE_CFG_DIS_IEEE_CERTIFICATION != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+static const uint8_t ieee_id[BLE_CFG_DIS_IEEE_CERTIFICATION_LEN_MAX] = 
+{
+  0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 
+  0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 
+  0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 
+  0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 
+};
+#endif
+#if ((BLE_CFG_DIS_PNP_ID != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+static const uint8_t pnp_id[BLE_CFG_DIS_PNP_ID_LEN_MAX] = 
+{
+  0x1,
+  0xAD, 0xDE,
+  0xDE, 0xDA, 
+  0x01, 0x00
+};
+#endif
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void DISAPP_Init(void)
+{
+/* USER CODE BEGIN DISAPP_Init */
+  DIS_Data_t dis_information_data;
+
+#if ((BLE_CFG_DIS_MANUFACTURER_NAME_STRING != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+  /**
+   * Update MANUFACTURER NAME Information
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t*)DISAPP_MANUFACTURER_NAME;
+  dis_information_data.Length = sizeof(DISAPP_MANUFACTURER_NAME);
+  DIS_UpdateChar(MANUFACTURER_NAME_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_MODEL_NUMBER_STRING != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+  /**
+   * Update MODEL NUMBERInformation
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t*)DISAPP_MODEL_NUMBER;
+  dis_information_data.Length = sizeof(DISAPP_MODEL_NUMBER);
+  DIS_UpdateChar(MODEL_NUMBER_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_SERIAL_NUMBER_STRING != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+  /**
+   * Update SERIAL NUMBERInformation
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t*)DISAPP_SERIAL_NUMBER;
+  dis_information_data.Length = sizeof(DISAPP_SERIAL_NUMBER);
+  DIS_UpdateChar(SERIAL_NUMBER_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_HARDWARE_REVISION_STRING != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+  /**
+   * Update HARDWARE REVISION NUMBERInformation
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t*)DISAPP_HARDWARE_REVISION_NUMBER;
+  dis_information_data.Length = sizeof(DISAPP_HARDWARE_REVISION_NUMBER);
+  DIS_UpdateChar(HARDWARE_REVISION_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_FIRMWARE_REVISION_STRING != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+  /**
+   * Update FIRMWARE REVISION NUMBERInformation
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t*)DISAPP_FIRMWARE_REVISION_NUMBER;
+  dis_information_data.Length = sizeof(DISAPP_FIRMWARE_REVISION_NUMBER);
+  DIS_UpdateChar(FIRMWARE_REVISION_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_SOFTWARE_REVISION_STRING != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+  /**
+   * Update SOFTWARE REVISION NUMBERInformation
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t*)DISAPP_SOFTWARE_REVISION_NUMBER;
+  dis_information_data.Length = sizeof(DISAPP_SOFTWARE_REVISION_NUMBER);
+  DIS_UpdateChar(SOFTWARE_REVISION_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_SYSTEM_ID != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+
+  /**
+   * Update SYSTEM ID Information
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t *)system_id;
+  dis_information_data.Length = BLE_CFG_DIS_SYSTEM_ID_LEN_MAX;
+  DIS_UpdateChar(SYSTEM_ID_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_IEEE_CERTIFICATION != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+
+  /**
+   * Update IEEE CERTIFICATION ID Information
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t *)ieee_id;
+  dis_information_data.Length = BLE_CFG_DIS_IEEE_CERTIFICATION_LEN_MAX;
+  DIS_UpdateChar(IEEE_CERTIFICATION_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_PNP_ID != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+
+  /**
+   * Update PNP ID Information
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t *)pnp_id;
+  dis_information_data.Length = BLE_CFG_DIS_PNP_ID_LEN_MAX;
+  DIS_UpdateChar(PNP_ID_UUID, &dis_information_data);
+#endif
+/* USER CODE END DISAPP_Init */
+}
+
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/dis_app.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/dis_app.h
new file mode 100644
index 000000000..196ec9937
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/dis_app.h
@@ -0,0 +1,77 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    dis_app.h
+  * @author  MCD Application Team
+  * @brief   Header for dis_application.c module
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __DIS_APP_H
+#define __DIS_APP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes -----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros -----------------------------------------------------------*/
+#define DISAPP_MANUFACTURER_NAME              "STM"
+#define DISAPP_MODEL_NUMBER                   "4502-1.0"
+#define DISAPP_SERIAL_NUMBER                  "1.0"
+#define DISAPP_HARDWARE_REVISION_NUMBER       "1.0"
+#define DISAPP_FIRMWARE_REVISION_NUMBER       "1.0"
+#define DISAPP_SOFTWARE_REVISION_NUMBER       "1.0"
+#define DISAPP_OUI                            0x123456
+#define DISAPP_MANUFACTURER_ID                0x9ABCDE
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ------------------------------------------------------- */
+void DISAPP_Init(void);
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__DIS_APP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/hrs_app.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/hrs_app.c
new file mode 100644
index 000000000..e84751eaa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/hrs_app.c
@@ -0,0 +1,230 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    hrs_app.c
+  * @author  MCD Application Team
+  * @brief   Heart Rate Service Application
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "ble.h"
+#include "hrs_app.h"
+#include "stm32_seq.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+typedef struct
+{
+  HRS_BodySensorLocation_t BodySensorLocationChar;
+  HRS_MeasVal_t MeasurementvalueChar;
+  uint8_t ResetEnergyExpended;
+  uint8_t TimerMeasurement_Id;
+
+} HRSAPP_Context_t;
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private defines ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+#define HRSAPP_MEASUREMENT_INTERVAL   (1000000/CFG_TS_TICK_VAL)  /**< 1s */
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/**
+ * START of Section BLE_APP_CONTEXT
+ */
+
+PLACE_IN_SECTION("BLE_APP_CONTEXT") static HRSAPP_Context_t HRSAPP_Context;
+
+/**
+ * END of Section BLE_APP_CONTEXT
+ */
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private functions prototypes-----------------------------------------------*/
+static void HrMeas( void );
+static void HRSAPP_Measurement(void);
+static uint32_t HRSAPP_Read_RTC_SSR_SS ( void );
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void HRS_Notification(HRS_App_Notification_evt_t *pNotification)
+{
+/* USER CODE BEGIN HRS_Notification_1 */
+
+/* USER CODE END HRS_Notification_1 */
+  switch(pNotification->HRS_Evt_Opcode)
+  {
+/* USER CODE BEGIN HRS_Notification_HRS_Evt_Opcode */
+
+/* USER CODE END HRS_Notification_HRS_Evt_Opcode */
+#if (BLE_CFG_HRS_ENERGY_EXPENDED_INFO_FLAG != 0)
+    case HRS_RESET_ENERGY_EXPENDED_EVT:
+/* USER CODE BEGIN HRS_RESET_ENERGY_EXPENDED_EVT */
+      HRSAPP_Context.MeasurementvalueChar.EnergyExpended = 0;
+      HRSAPP_Context.ResetEnergyExpended = 1;
+/* USER CODE END HRS_RESET_ENERGY_EXPENDED_EVT */
+      break;
+#endif
+      
+    case HRS_NOTIFICATION_ENABLED:
+/* USER CODE BEGIN HRS_NOTIFICATION_ENABLED */
+      /**
+       * It could be the enable notification is received twice without the disable notification in between
+       */
+      HW_TS_Stop(HRSAPP_Context.TimerMeasurement_Id);
+      HW_TS_Start(HRSAPP_Context.TimerMeasurement_Id, HRSAPP_MEASUREMENT_INTERVAL);
+/* USER CODE END HRS_NOTIFICATION_ENABLED */
+      break;
+
+    case HRS_NOTIFICATION_DISABLED:
+/* USER CODE BEGIN HRS_NOTIFICATION_DISABLED */
+      HW_TS_Stop(HRSAPP_Context.TimerMeasurement_Id);
+/* USER CODE END HRS_NOTIFICATION_DISABLED */
+      break;
+      
+#if (BLE_CFG_OTA_REBOOT_CHAR != 0)
+    case HRS_STM_BOOT_REQUEST_EVT:
+/* USER CODE BEGIN HRS_STM_BOOT_REQUEST_EVT */
+      *(uint32_t*)SRAM1_BASE = *(uint32_t*)pNotification->DataTransfered.pPayload;
+      NVIC_SystemReset();
+/* USER CODE END HRS_STM_BOOT_REQUEST_EVT */
+      break;
+#endif
+      
+   default:
+/* USER CODE BEGIN HRS_Notification_Default */
+
+/* USER CODE END HRS_Notification_Default */
+      break;
+  }
+/* USER CODE BEGIN HRS_Notification_2 */
+
+/* USER CODE END HRS_Notification_2 */
+  return;
+}
+
+void HRSAPP_Init(void)
+{
+  UTIL_SEQ_RegTask( 1<< CFG_TASK_MEAS_REQ_ID, UTIL_SEQ_RFU, HRSAPP_Measurement );
+/* USER CODE BEGIN HRSAPP_Init */
+  /**
+   * Set Body Sensor Location
+   */
+  HRSAPP_Context.ResetEnergyExpended = 0;
+  HRSAPP_Context.BodySensorLocationChar = HRS_BODY_SENSOR_LOCATION_HAND;
+  HRS_UpdateChar(SENSOR_LOCATION_UUID, (uint8_t *)&HRSAPP_Context.BodySensorLocationChar);
+
+
+  /**
+   * Set Flags for measurement value
+   */
+
+  HRSAPP_Context.MeasurementvalueChar.Flags = ( HRS_HRM_VALUE_FORMAT_UINT16      | 
+                                                  HRS_HRM_SENSOR_CONTACTS_PRESENT   | 
+                                                  HRS_HRM_SENSOR_CONTACTS_SUPPORTED |
+                                                  HRS_HRM_ENERGY_EXPENDED_PRESENT  |
+                                                  HRS_HRM_RR_INTERVAL_PRESENT );
+
+#if (BLE_CFG_HRS_ENERGY_EXPENDED_INFO_FLAG != 0)
+  if(HRSAPP_Context.MeasurementvalueChar.Flags & HRS_HRM_ENERGY_EXPENDED_PRESENT)
+    HRSAPP_Context.MeasurementvalueChar.EnergyExpended = 10;
+#endif
+  
+#if (BLE_CFG_HRS_ENERGY_RR_INTERVAL_FLAG != 0)
+  if(HRSAPP_Context.MeasurementvalueChar.Flags & HRS_HRM_RR_INTERVAL_PRESENT)
+  {
+    uint8_t i;
+    
+    HRSAPP_Context.MeasurementvalueChar.NbreOfValidRRIntervalValues = BLE_CFG_HRS_ENERGY_RR_INTERVAL_FLAG;
+    for(i = 0; i < BLE_CFG_HRS_ENERGY_RR_INTERVAL_FLAG; i++)
+      HRSAPP_Context.MeasurementvalueChar.aRRIntervalValues[i] = 1024;
+  }
+#endif
+  
+  /**
+   * Create timer for Heart Rate Measurement
+   */
+  HW_TS_Create(CFG_TIM_PROC_ID_ISR, &(HRSAPP_Context.TimerMeasurement_Id), hw_ts_Repeated, HrMeas);
+
+/* USER CODE END HRSAPP_Init */
+  return;
+}
+
+static void HRSAPP_Measurement(void)
+{
+/* USER CODE BEGIN HRSAPP_Measurement */
+  uint32_t measurement;
+
+  measurement = ((HRSAPP_Read_RTC_SSR_SS()) & 0x07) + 65;
+
+  HRSAPP_Context.MeasurementvalueChar.MeasurementValue = measurement;
+#if (BLE_CFG_HRS_ENERGY_EXPENDED_INFO_FLAG != 0)
+  if((HRSAPP_Context.MeasurementvalueChar.Flags & HRS_HRM_ENERGY_EXPENDED_PRESENT) &&
+     (HRSAPP_Context.ResetEnergyExpended == 0))
+    HRSAPP_Context.MeasurementvalueChar.EnergyExpended += 5;
+  else if(HRSAPP_Context.ResetEnergyExpended == 1)
+    HRSAPP_Context.ResetEnergyExpended = 0;
+#endif
+
+  HRS_UpdateChar(HEART_RATE_MEASURMENT_UUID, (uint8_t *)&HRSAPP_Context.MeasurementvalueChar);
+
+/* USER CODE END HRSAPP_Measurement */
+  return;
+}
+
+static void HrMeas( void )
+{
+  /**
+   * The code shall be executed in the background as aci command may be sent
+   * The background is the only place where the application can make sure a new aci command
+   * is not sent if there is a pending one
+   */
+  UTIL_SEQ_SetTask( 1<SSR, RTC_SSR_SS)));
+}
+
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/hrs_app.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/hrs_app.h
new file mode 100644
index 000000000..0246d2811
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/hrs_app.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    hrs_app.h
+  * @author  MCD Application Team
+  * @brief   Header for hrs_application.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HRS_APP_H
+#define __HRS_APP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+void HRSAPP_Init( void );
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__HRS_APP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/Target/hw_ipcc.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/Target/hw_ipcc.c
new file mode 100644
index 000000000..0f839543a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/STM32_WPAN/Target/hw_ipcc.c
@@ -0,0 +1,523 @@
+/**
+ ******************************************************************************
+  * File Name          : Target/hw_ipcc.c
+  * Description        : Hardware IPCC source file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "mbox_def.h"
+
+/* Global variables ---------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+#define HW_IPCC_TX_PENDING( channel ) ( !(LL_C1_IPCC_IsActiveFlag_CHx( IPCC, channel )) ) &&  (((~(IPCC->C1MR)) & (channel << 16U)))
+#define HW_IPCC_RX_PENDING( channel )  (LL_C2_IPCC_IsActiveFlag_CHx( IPCC, channel )) && (((~(IPCC->C1MR)) & (channel << 0U)))
+
+/* Private macros ------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static void (*FreeBufCb)( void );
+
+/* Private function prototypes -----------------------------------------------*/
+static void HW_IPCC_BLE_EvtHandler( void );
+static void HW_IPCC_BLE_AclDataEvtHandler( void );
+static void HW_IPCC_MM_FreeBufHandler( void );
+static void HW_IPCC_SYS_CmdEvtHandler( void );
+static void HW_IPCC_SYS_EvtHandler( void );
+static void HW_IPCC_TRACES_EvtHandler( void );
+
+#ifdef THREAD_WB
+static void HW_IPCC_OT_CmdEvtHandler( void );
+static void HW_IPCC_THREAD_NotEvtHandler( void );
+static void HW_IPCC_THREAD_CliNotEvtHandler( void );
+#endif
+
+#ifdef MAC_802_15_4_WB
+static void HW_IPCC_MAC_802_15_4_CmdEvtHandler( void );
+static void HW_IPCC_MAC_802_15_4_NotEvtHandler( void );
+#endif
+
+#ifdef ZIGBEE_WB
+static void HW_IPCC_ZIGBEE_CmdEvtHandler( void );
+static void HW_IPCC_ZIGBEE_StackNotifEvtHandler( void );
+static void HW_IPCC_ZIGBEE_CliNotifEvtHandler( void );
+#endif
+
+/* Public function definition -----------------------------------------------*/
+
+/******************************************************************************
+ * INTERRUPT HANDLER
+ ******************************************************************************/
+void HW_IPCC_Rx_Handler( void )
+{
+  if (HW_IPCC_RX_PENDING( HW_IPCC_SYSTEM_EVENT_CHANNEL ))
+  {
+      HW_IPCC_SYS_EvtHandler();
+  }
+#ifdef MAC_802_15_4_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_MAC_802_15_4_NotEvtHandler();
+  }
+#endif /* MAC_802_15_4_WB */
+#ifdef THREAD_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_THREAD_NotEvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_THREAD_CliNotEvtHandler();
+  }
+#endif /* THREAD_WB */
+#ifdef ZIGBEE_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_ZIGBEE_StackNotifEvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
+  {
+      HW_IPCC_ZIGBEE_CliNotifEvtHandler();
+  }
+#endif /* ZIGBEE_WB */
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_BLE_EVENT_CHANNEL ))
+  {
+    HW_IPCC_BLE_EvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_TRACES_CHANNEL ))
+  {
+    HW_IPCC_TRACES_EvtHandler();
+  }
+
+  return;
+}
+
+void HW_IPCC_Tx_Handler( void )
+{
+  if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_SYS_CmdEvtHandler();
+  }
+#ifdef MAC_802_15_4_WB
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_MAC_802_15_4_CmdEvtHandler();
+  }
+#endif /* MAC_802_15_4_WB */
+#ifdef THREAD_WB
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_OT_CmdEvtHandler();
+  }
+#endif /* THREAD_WB */
+#ifdef ZIGBEE_WB
+  if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
+  {
+      HW_IPCC_ZIGBEE_CmdEvtHandler();
+  }
+#endif /* ZIGBEE_WB */
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_SYS_CmdEvtHandler();
+  }
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ))
+  {
+    HW_IPCC_MM_FreeBufHandler();
+  }
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_HCI_ACL_DATA_CHANNEL ))
+  {
+    HW_IPCC_BLE_AclDataEvtHandler();
+  }
+
+  return;
+}
+/******************************************************************************
+ * GENERAL
+ ******************************************************************************/
+void HW_IPCC_Enable( void )
+{
+  /**
+   * When the device is out of standby, it is required to use the EXTI mechanism to wakeup CPU2
+   */
+  LL_C2_EXTI_EnableEvent_32_63( LL_EXTI_LINE_41 );
+  LL_EXTI_EnableRisingTrig_32_63( LL_EXTI_LINE_41 );
+	
+  /**
+   * In case the SBSFU is implemented, it may have already set the C2BOOT bit to startup the CPU2.
+   * In that case, to keep the mechanism transparent to the user application, it shall call the system command
+   * SHCI_C2_Reinit( ) before jumping to the application.
+   * When the CPU2 receives that command, it waits for its event input to be set to restart the CPU2 firmware.
+   * This is required because once C2BOOT has been set once, a clear/set on C2BOOT has no effect.
+   * When SHCI_C2_Reinit( ) is not called, generating an event to the CPU2 does not have any effect
+   * So, by default, the application shall both set the event flag and set the C2BOOT bit.
+   */
+  __SEV( );       /* Set the internal event flag and send an event to the CPU2 */
+  __WFE( );       /* Clear the internal event flag */
+  LL_PWR_EnableBootC2( );
+
+  return;
+}
+
+void HW_IPCC_Init( void )
+{
+  LL_AHB3_GRP1_EnableClock( LL_AHB3_GRP1_PERIPH_IPCC );
+
+  LL_C1_IPCC_EnableIT_RXO( IPCC );
+  LL_C1_IPCC_EnableIT_TXF( IPCC );
+
+  HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn);
+  HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn);
+
+  return;
+}
+
+/******************************************************************************
+ * BLE
+ ******************************************************************************/
+void HW_IPCC_BLE_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_BLE_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_BLE_CMD_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_BLE_EvtHandler( void )
+{
+  HW_IPCC_BLE_RxEvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_BLE_SendAclData( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_BLE_AclDataEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+
+  HW_IPCC_BLE_AclDataAckNot();
+
+  return;
+}
+
+__weak void HW_IPCC_BLE_AclDataAckNot( void ){};
+__weak void HW_IPCC_BLE_RxEvtNot( void ){};
+
+/******************************************************************************
+ * SYSTEM
+ ******************************************************************************/
+void HW_IPCC_SYS_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_SYS_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_SYS_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+
+  HW_IPCC_SYS_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_SYS_EvtHandler( void )
+{
+  HW_IPCC_SYS_EvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
+
+  return;
+}
+
+__weak void HW_IPCC_SYS_CmdEvtNot( void ){};
+__weak void HW_IPCC_SYS_EvtNot( void ){};
+
+/******************************************************************************
+ * MAC 802.15.4
+ ******************************************************************************/
+#ifdef MAC_802_15_4_WB
+void HW_IPCC_MAC_802_15_4_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_MAC_802_15_4_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_MAC_802_15_4_SendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_MAC_802_15_4_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+
+  HW_IPCC_MAC_802_15_4_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_MAC_802_15_4_NotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_MAC_802_15_4_EvtNot();
+
+  return;
+}
+__weak void HW_IPCC_MAC_802_15_4_CmdEvtNot( void ){};
+__weak void HW_IPCC_MAC_802_15_4_EvtNot( void ){};
+#endif
+
+/******************************************************************************
+ * THREAD
+ ******************************************************************************/
+#ifdef THREAD_WB
+void HW_IPCC_THREAD_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_OT_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_CLI_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_THREAD_SendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_THREAD_CliSendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_OT_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  HW_IPCC_OT_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_THREAD_NotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_THREAD_EvtNot();
+
+  return;
+}
+
+static void HW_IPCC_THREAD_CliNotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_THREAD_CliEvtNot();
+
+  return;
+}
+
+__weak void HW_IPCC_OT_CmdEvtNot( void ){};
+__weak void HW_IPCC_CLI_CmdEvtNot( void ){};
+__weak void HW_IPCC_THREAD_EvtNot( void ){};
+
+#endif /* THREAD_WB */
+
+/******************************************************************************
+ * ZIGBEE
+ ******************************************************************************/
+#ifdef ZIGBEE_WB
+void HW_IPCC_ZIGBEE_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendAppliCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendCliCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
+
+   return;
+}
+
+void HW_IPCC_ZIGBEE_SendAppliCmdAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendCliCmdAck( void )
+{
+    LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+    LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_CmdEvtHandler( void )
+{
+    LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+    HW_IPCC_ZIGBEE_AppliCmdNotification();
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_StackNotifEvtHandler( void )
+{
+    LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+    HW_IPCC_ZIGBEE_AppliAsyncEvtNotification();
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_CliNotifEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_ZIGBEE_CliEvtNotification();
+
+  return;
+}
+
+__weak void HW_IPCC_ZIGBEE_AppliCmdNotification( void ){};
+__weak void HW_IPCC_ZIGBEE_AppliAsyncEvtNotification( void ){};
+__weak void HW_IPCC_ZIGBEE_CliEvtNotification( void ){};
+#endif /* ZIGBEE_WB */
+
+/******************************************************************************
+ * MEMORY MANAGER
+ ******************************************************************************/
+void HW_IPCC_MM_SendFreeBuf( void (*cb)( void ) )
+{
+  if ( LL_C1_IPCC_IsActiveFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ) )
+  {
+    FreeBufCb = cb;
+    LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+  }
+  else
+  {
+    cb();
+
+    LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+  }
+
+  return;
+}
+
+static void HW_IPCC_MM_FreeBufHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+
+  FreeBufCb();
+
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+
+  return;
+}
+
+/******************************************************************************
+ * TRACES
+ ******************************************************************************/
+void HW_IPCC_TRACES_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_TRACES_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_TRACES_EvtHandler( void )
+{
+  HW_IPCC_TRACES_EvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_TRACES_CHANNEL );
+
+  return;
+}
+
+__weak void HW_IPCC_TRACES_EvtNot( void ){};
+
+/******************* (C) COPYRIGHT 2019 STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/readme.txt b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/readme.txt
new file mode 100644
index 000000000..d3fedc91d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate/readme.txt
@@ -0,0 +1,110 @@
+/**
+  @page BLE_HeartRate example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    BLE/BLE_HeartRate/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the BLE_HeartRate example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                               www.st.com/SLA0044
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to use the Heart Rate profile as specified by the BLE SIG.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Directory contents 
+  
+  - BLE/BLE_HeartRate/Core/Inc/stm32wbxx_hal_conf.h		HAL configuration file
+  - BLE/BLE_HeartRate/Core/Inc/stm32wbxx_it.h          	Interrupt handlers header file
+  - BLE/BLE_HeartRate/Core/Inc/main.h                  	Header for main.c module
+  - BLE/BLE_HeartRate/STM32_WPAN/App/app_ble.h          Header for app_ble.c module
+  - BLE/BLE_HeartRate/Core/Inc/app_common.h            	Header for all modules with common definition
+  - BLE/BLE_HeartRate/Core/Inc/app_conf.h              	Parameters configuration file of the application
+  - BLE/BLE_HeartRate/Core/Inc/app_entry.h            	Parameters configuration file of the application
+  - BLE/BLE_HeartRate/STM32_WPAN/App/ble_conf.h         BLE Services configuration
+  - BLE/BLE_HeartRate/STM32_WPAN/App/ble_dbg_conf.h     BLE Traces configuration of the BLE services
+  - BLE/BLE_HeartRate/STM32_WPAN/App/dis_app.h          Header for dis_app.c module
+  - BLE/BLE_HeartRate/STM32_WPAN/App/hrs_app.h          Header for hrs_app.c module
+  - BLE/BLE_HeartRate/Core/Inc/hw_conf.h           		Configuration file of the HW
+  - BLE/BLE_HeartRate/Core/Inc/utilities_conf.h    		Configuration file of the utilities
+  - BLE/BLE_HeartRate/Core/Src/stm32wbxx_it.c          	Interrupt handlers
+  - BLE/BLE_HeartRate/Core/Src/main.c                  	Main program
+  - BLE/BLE_HeartRate/Core/Src/system_stm32wbxx.c      	stm32wbxx system source file
+  - BLE/BLE_HeartRate/STM32_WPAN/App/app_ble.c      	BLE Profile implementation
+  - BLE/BLE_HeartRate/Core/Src/app_entry.c      		Initialization of the application
+  - BLE/BLE_HeartRate/STM32_WPAN/App/dis_app.c      	Device Information Service application
+  - BLE/BLE_HeartRate/STM32_WPAN/App/hrs_app.c      	Heart Rate Service application
+  - BLE/BLE_HeartRate/STM32_WPAN/Target/hw_ipcc.c      	IPCC Driver
+  - BLE/BLE_HeartRate/Core/Src/stm32_lpm_if.c			Low Power Manager Interface
+  - BLE/BLE_HeartRate/Core/Src/hw_timerserver.c 		Timer Server based on RTC
+  - BLE/BLE_HeartRate/Core/Src/hw_uart.c 				UART Driver
+
+     
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35xx devices.
+  
+  - This example has been tested with an STMicroelectronics STM32WB35CE-Nucleo
+    board and can be easily tailored to any other supported device 
+    and development board.
+	
+  - This example is by default configured to support low power mode ( No traces - No debugger )
+    This can be modified in app_conf.h
+
+@par How to use it ? 
+
+This application requests having the stm32wb3x_BLE_Stack_fw.bin binary flashed on the Wireless Coprocessor.
+If it is not the case, you need to use STM32CubeProgrammer to load the appropriate binary.
+All available binaries are located under /Projects/STM32_Copro_Wireless_Binaries directory.
+Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the detailed procedure to change the
+Wireless Coprocessor binary.  
+
+In order to make the program work, you must do the following:
+ - Open your toolchain 
+ - Rebuild all files and flash the board with the executable file
+ - OR use the BLE_HeartRate_reference.hex from Binary directory
+
+ On the android/ios device, enable the Bluetooth communications, and if not done before,
+ - Install the ST BLE Profile application on the android device
+	https://play.google.com/store/apps/details?id=com.stm.bluetoothlevalidation&hl=en
+    https://itunes.apple.com/fr/App/st-ble-profile/id1081331769?mt=8
+
+ - Install the ST BLE Sensor application on the ios/android device
+	https://play.google.com/store/apps/details?id=com.st.bluems
+	https://itunes.apple.com/us/App/st-bluems/id993670214?mt=8
+
+ - Power on the Nucleo board with the BLE_HeartRate application
+ - Then, click on the App icon, ST BLE Sensor (android device)
+ - connect to a device
+ - select the HRSTM in the device list
+ - pairing is supported ( SW1 clears the security database, SW2 requests the slave req pairing )
+ - This example supports switch to 2Mbits PHY ( SW3 is used to enable the feature )
+ 
+The Heart Rate is displayed each second on the android device.
+
+For more details refer to the Application Note: 
+  AN5289 - Building a Wireless application 
+ 
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
+ 
\ No newline at end of file
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/FreeRTOSConfig.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/FreeRTOSConfig.h
new file mode 100644
index 000000000..6add07b2b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/FreeRTOSConfig.h
@@ -0,0 +1,151 @@
+/* USER CODE BEGIN Header */
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+/* USER CODE END Header */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * These parameters and more are described within the 'configuration' section of the
+ * FreeRTOS API documentation available on the FreeRTOS.org web site.
+ *
+ * See http://www.freertos.org/a00110.html
+ *----------------------------------------------------------*/
+
+/* USER CODE BEGIN Includes */   	      
+/* Section where include file can be added */
+/* USER CODE END Includes */ 
+
+/* Ensure stdint is only used by the compiler, and not the assembler. */
+#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
+  #include 
+  extern uint32_t SystemCoreClock;
+#endif
+
+#define configUSE_PREEMPTION                     1
+#define configSUPPORT_STATIC_ALLOCATION          1
+#define configSUPPORT_DYNAMIC_ALLOCATION         1
+#define configUSE_IDLE_HOOK                      0
+#define configUSE_TICK_HOOK                      0
+#define configCPU_CLOCK_HZ                       ( SystemCoreClock )
+#define configTICK_RATE_HZ                       ((TickType_t)1000)
+#define configMAX_PRIORITIES                     ( 56 )
+#define configMINIMAL_STACK_SIZE                 ((uint16_t)128)
+#define configTOTAL_HEAP_SIZE                    ((size_t)6000)
+#define configMAX_TASK_NAME_LEN                  ( 16 )
+#define configUSE_TRACE_FACILITY                 1
+#define configUSE_16_BIT_TICKS                   0
+#define configUSE_MUTEXES                        1
+#define configQUEUE_REGISTRY_SIZE                8
+#define configUSE_RECURSIVE_MUTEXES              1
+#define configUSE_COUNTING_SEMAPHORES            1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION  0
+#define configUSE_TICKLESS_IDLE                  2
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                    0
+#define configMAX_CO_ROUTINE_PRIORITIES          ( 2 )
+
+/* Software timer definitions. */
+#define configUSE_TIMERS                         1
+#define configTIMER_TASK_PRIORITY                ( 2 )
+#define configTIMER_QUEUE_LENGTH                 10
+#define configTIMER_TASK_STACK_DEPTH             256
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet            1
+#define INCLUDE_uxTaskPriorityGet           1
+#define INCLUDE_vTaskDelete                 1
+#define INCLUDE_vTaskCleanUpResources       0
+#define INCLUDE_vTaskSuspend                1
+#define INCLUDE_vTaskDelayUntil             1
+#define INCLUDE_vTaskDelay                  1
+#define INCLUDE_xTaskGetSchedulerState      1
+#define INCLUDE_xTimerPendFunctionCall      1
+#define INCLUDE_xQueueGetMutexHolder        1
+#define INCLUDE_uxTaskGetStackHighWaterMark 1
+#define INCLUDE_eTaskGetState               1
+
+/* 
+ * The CMSIS-RTOS V2 FreeRTOS wrapper is dependent on the heap implementation used
+ * by the application thus the correct define need to be enabled below
+ */
+#define USE_FreeRTOS_HEAP_4
+
+/* Cortex-M specific definitions. */
+#ifdef __NVIC_PRIO_BITS
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+ #define configPRIO_BITS         __NVIC_PRIO_BITS
+#else
+ #define configPRIO_BITS         4
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY   15
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* Normal assert() semantics without relying on the provision of an assert.h
+header file. */
+/* USER CODE BEGIN 1 */
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
+/* USER CODE END 1 */
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler    SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+
+/* IMPORTANT: This define is commented when used with STM32Cube firmware, when the timebase source is SysTick,
+              to prevent overwriting SysTick_Handler defined within STM32Cube HAL */
+#define xPortSysTickHandler SysTick_Handler
+
+/* USER CODE BEGIN Defines */   	      
+/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */
+#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 1  /* required only for Keil but does not hurt otherwise */
+/* USER CODE END Defines */ 
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_common.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_common.h
new file mode 100644
index 000000000..4defc5d7a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_common.h
@@ -0,0 +1,114 @@
+/**
+ ******************************************************************************
+  * File Name          : app_common.h
+  * Description        : App Common application configuration file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_COMMON_H
+#define APP_COMMON_H
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "app_conf.h"
+
+  /* -------------------------------- *
+   *  Basic definitions               *
+   * -------------------------------- */
+
+#undef NULL
+#define NULL                    0
+
+#undef FALSE
+#define FALSE                   0
+
+#undef TRUE
+#define TRUE                    (!0)
+
+  /* -------------------------------- *
+   *  Critical Section definition     *
+   * -------------------------------- */
+#define BACKUP_PRIMASK()    uint32_t primask_bit= __get_PRIMASK()
+#define DISABLE_IRQ()       __disable_irq()
+#define RESTORE_PRIMASK()   __set_PRIMASK(primask_bit)
+
+  /* -------------------------------- *
+   *  Macro delimiters                *
+   * -------------------------------- */
+
+#define M_BEGIN     do {
+
+#define M_END       } while(0)
+
+  /* -------------------------------- *
+   *  Some useful macro definitions   *
+   * -------------------------------- */
+
+#define MAX( x, y )          (((x)>(y))?(x):(y))
+
+#define MIN( x, y )          (((x)<(y))?(x):(y))
+
+#define MODINC( a, m )       M_BEGIN  (a)++;  if ((a)>=(m)) (a)=0;  M_END
+
+#define MODDEC( a, m )       M_BEGIN  if ((a)==0) (a)=(m);  (a)--;  M_END
+
+#define MODADD( a, b, m )    M_BEGIN  (a)+=(b);  if ((a)>=(m)) (a)-=(m);  M_END
+
+#define MODSUB( a, b, m )    MODADD( a, (m)-(b), m )
+
+#define PAUSE( t )           M_BEGIN \
+                               __IO int _i; \
+                               for ( _i = t; _i > 0; _i -- ); \
+                             M_END
+
+#define DIVF( x, y )         ((x)/(y))
+
+#define DIVC( x, y )         (((x)+(y)-1)/(y))
+
+#define DIVR( x, y )         (((x)+((y)/2))/(y))
+
+#define SHRR( x, n )         ((((x)>>((n)-1))+1)>>1)
+
+#define BITN( w, n )         (((w)[(n)/32] >> ((n)%32)) & 1)
+
+#define BITNSET( w, n, b )   M_BEGIN (w)[(n)/32] |= ((U32)(b))<<((n)%32); M_END
+
+  /* -------------------------------- *
+   *  Compiler                         *
+   * -------------------------------- */
+#define PLACE_IN_SECTION( __x__ )  __attribute__((section (__x__)))
+
+#ifdef WIN32
+#define ALIGN(n)
+#else
+#define ALIGN(n)             __attribute__((aligned(n)))
+#endif
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*APP_COMMON_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_conf.h
new file mode 100644
index 000000000..48de1ed22
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_conf.h
@@ -0,0 +1,529 @@
+/**
+ ******************************************************************************
+  * File Name          : app_conf.h
+  * Description        : Application configuration file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_CONF_H
+#define APP_CONF_H
+
+#include "hw.h"
+#include "hw_conf.h"
+#include "hw_if.h"
+
+/******************************************************************************
+ * Application Config
+ ******************************************************************************/
+
+/**< generic parameters ******************************************************/
+
+/**
+ * Define Tx Power
+ */   
+#define CFG_TX_POWER                      (0x18) /**< 0dbm */
+
+/**
+ * Define Advertising parameters
+ */
+#define CFG_ADV_BD_ADDRESS                (0x7257acd87a6c)
+#define CFG_FAST_CONN_ADV_INTERVAL_MIN    (0x80)   /**< 80ms */
+#define CFG_FAST_CONN_ADV_INTERVAL_MAX    (0xa0)  /**< 100ms */
+#define CFG_LP_CONN_ADV_INTERVAL_MIN      (0x640) /**< 1s */
+#define CFG_LP_CONN_ADV_INTERVAL_MAX      (0xfa0) /**< 2.5s */
+
+/**
+ * Define IO Authentication
+ */
+#define CFG_BONDING_MODE                  (1)
+#define CFG_FIXED_PIN                     (111111)
+#define CFG_USED_FIXED_PIN                (0)
+#define CFG_ENCRYPTION_KEY_SIZE_MAX       (16)
+#define CFG_ENCRYPTION_KEY_SIZE_MIN       (8)
+
+/**
+ * Define IO capabilities
+ */
+#define CFG_IO_CAPABILITY_DISPLAY_ONLY       (0x00)
+#define CFG_IO_CAPABILITY_DISPLAY_YES_NO     (0x01)
+#define CFG_IO_CAPABILITY_KEYBOARD_ONLY      (0x02)
+#define CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT (0x03)
+#define CFG_IO_CAPABILITY_KEYBOARD_DISPLAY   (0x04)
+
+#define CFG_IO_CAPABILITY             CFG_IO_CAPABILITY_DISPLAY_YES_NO
+
+/**
+ * Define MITM modes
+ */
+#define CFG_MITM_PROTECTION_NOT_REQUIRED      (0x00)
+#define CFG_MITM_PROTECTION_REQUIRED          (0x01)
+
+#define CFG_MITM_PROTECTION             CFG_MITM_PROTECTION_REQUIRED
+
+/**
+ * Define PHY
+ */
+#define ALL_PHYS_PREFERENCE                             0x00
+#define RX_2M_PREFERRED                                 0x02
+#define TX_2M_PREFERRED                                 0x02
+#define TX_1M                                           0x01
+#define TX_2M                                           0x02
+#define RX_1M                                           0x01
+#define RX_2M                                           0x02 
+
+/**
+*   Identity root key used to derive LTK and CSRK
+*/
+#define CFG_BLE_IRK     {0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0,0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0}
+
+/**
+* Encryption root key used to derive LTK and CSRK
+*/
+#define CFG_BLE_ERK     {0xfe,0xdc,0xba,0x09,0x87,0x65,0x43,0x21,0xfe,0xdc,0xba,0x09,0x87,0x65,0x43,0x21}
+
+/* USER CODE BEGIN Generic_Parameters */
+/**
+ * SMPS supply
+ * SMPS not used when Set to 0
+ * SMPS used when Set to 1
+ */
+#define CFG_USE_SMPS    1
+/* USER CODE END Generic_Parameters */
+
+/**< specific parameters */
+/*****************************************************/
+/**
+* AD Element - Group B Feature
+*/ 
+/* LSB - Second Byte */
+#define CFG_FEATURE_OTA_REBOOT                  (0x20)
+
+/******************************************************************************
+ * Information Table
+ *
+  * Version
+  * [0:3]   = Build - 0: Untracked - 15:Released - x: Tracked version
+  * [4:7]   = branch - 0: Mass Market - x: ...
+  * [8:15]  = Subversion
+  * [16:23] = Version minor
+  * [24:31] = Version major
+  *
+ ******************************************************************************/
+#define CFG_FW_MAJOR_VERSION      (0)
+#define CFG_FW_MINOR_VERSION      (0)
+#define CFG_FW_SUBVERSION         (1)
+#define CFG_FW_BRANCH             (0)
+#define CFG_FW_BUILD              (0)
+
+/******************************************************************************
+ * BLE Stack
+ ******************************************************************************/
+/**
+ * Maximum number of simultaneous connections that the device will support.
+ * Valid values are from 1 to 8
+ */
+#define CFG_BLE_NUM_LINK            8
+
+/**
+ * Maximum number of Services that can be stored in the GATT database.
+ * Note that the GAP and GATT services are automatically added so this parameter should be 2 plus the number of user services
+ */
+#define CFG_BLE_NUM_GATT_SERVICES   8
+
+/**
+ * Maximum number of Attributes
+ * (i.e. the number of characteristic + the number of characteristic values + the number of descriptors, excluding the services)
+ * that can be stored in the GATT database.
+ * Note that certain characteristics and relative descriptors are added automatically during device initialization
+ * so this parameters should be 9 plus the number of user Attributes
+ */
+#define CFG_BLE_NUM_GATT_ATTRIBUTES 68
+
+/**
+ * Maximum supported ATT_MTU size
+ */
+#define CFG_BLE_MAX_ATT_MTU             (156)
+
+/**
+ * Size of the storage area for Attribute values
+ *  This value depends on the number of attributes used by application. In particular the sum of the following quantities (in octets) should be made for each attribute:
+ *  - attribute value length
+ *  - 5, if UUID is 16 bit; 19, if UUID is 128 bit
+ *  - 2, if server configuration descriptor is used
+ *  - 2*DTM_NUM_LINK, if client configuration descriptor is used
+ *  - 2, if extended properties is used
+ *  The total amount of memory needed is the sum of the above quantities for each attribute.
+ */
+#define CFG_BLE_ATT_VALUE_ARRAY_SIZE    (1344)
+
+/**
+ * Prepare Write List size in terms of number of packet with ATT_MTU=23 bytes
+ */
+#define CFG_BLE_PREPARE_WRITE_LIST_SIZE         ( 0x3A )
+
+/**
+ * Number of allocated memory blocks
+ */
+#define CFG_BLE_MBLOCK_COUNT            ( 0x79 )
+
+/**
+ * Enable or disable the Extended Packet length feature. Valid values are 0 or 1.
+ */
+#define CFG_BLE_DATA_LENGTH_EXTENSION   1
+
+/**
+ * Sleep clock accuracy in Slave mode (ppm value)
+ */
+#define CFG_BLE_SLAVE_SCA   500
+
+/**
+ * Sleep clock accuracy in Master mode
+ * 0 : 251 ppm to 500 ppm
+ * 1 : 151 ppm to 250 ppm
+ * 2 : 101 ppm to 150 ppm
+ * 3 : 76 ppm to 100 ppm
+ * 4 : 51 ppm to 75 ppm
+ * 5 : 31 ppm to 50 ppm
+ * 6 : 21 ppm to 30 ppm
+ * 7 : 0 ppm to 20 ppm
+ */
+#define CFG_BLE_MASTER_SCA   0
+
+/**
+ *  Source for the 32 kHz slow speed clock
+ *  1 : internal RO
+ *  0 : external crystal ( no calibration )
+ */
+#define CFG_BLE_LSE_SOURCE  0
+
+/**
+ * Start up time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us)
+ */
+#define CFG_BLE_HSE_STARTUP_TIME  0x148
+
+/**
+ * Maximum duration of the connection event when the device is in Slave mode in units of 625/256 us (~2.44 us)
+ */
+#define CFG_BLE_MAX_CONN_EVENT_LENGTH  ( 0xFFFFFFFF )
+
+/**
+ * Viterbi Mode
+ * 1 : enabled
+ * 0 : disabled
+ */
+#define CFG_BLE_VITERBI_MODE  1
+
+/**
+ *  LL Only Mode
+ *  1 : LL Only
+ *  0 : LL + Host
+ */
+#define CFG_BLE_LL_ONLY  0
+/******************************************************************************
+ * Transport Layer
+ ******************************************************************************/
+/**
+ * Queue length of BLE Event
+ * This parameter defines the number of asynchronous events that can be stored in the HCI layer before
+ * being reported to the application. When a command is sent to the BLE core coprocessor, the HCI layer
+ * is waiting for the event with the Num_HCI_Command_Packets set to 1. The receive queue shall be large
+ * enough to store all asynchronous events received in between.
+ * When CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE is set to 27, this allow to store three 255 bytes long asynchronous events
+ * between the HCI command and its event.
+ * This parameter depends on the value given to CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE. When the queue size is to small,
+ * the system may hang if the queue is full with asynchronous events and the HCI layer is still waiting
+ * for a CC/CS event, In that case, the notification TL_BLE_HCI_ToNot() is called to indicate
+ * to the application a HCI command did not receive its command event within 30s (Default HCI Timeout).
+ */
+#define CFG_TLBLE_EVT_QUEUE_LENGTH 5
+/**
+ * This parameter should be set to fit most events received by the HCI layer. It defines the buffer size of each element
+ * allocated in the queue of received events and can be used to optimize the amount of RAM allocated by the Memory Manager.
+ * It should not exceed 255 which is the maximum HCI packet payload size (a greater value is a lost of memory as it will
+ * never be used)
+ * It shall be at least 4 to receive the command status event in one frame.
+ * The default value is set to 27 to allow receiving an event of MTU size in a single buffer. This value maybe reduced
+ * further depending on the application.
+ *
+ */
+#define CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE 255   /**< Set to 255 with the memory manager and the mailbox */
+
+#define TL_BLE_EVENT_FRAME_SIZE ( TL_EVT_HDR_SIZE + CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE )
+/******************************************************************************
+ * UART interfaces
+ ******************************************************************************/
+
+/**
+ * Select UART interfaces
+ */
+#define CFG_DEBUG_TRACE_UART    hw_uart1
+#define CFG_CONSOLE_MENU      
+/******************************************************************************
+ * USB interface
+ ******************************************************************************/
+
+/**
+ * Enable/Disable USB interface
+ */
+#define CFG_USB_INTERFACE_ENABLE    0
+
+/******************************************************************************
+ * Low Power
+ ******************************************************************************/
+/**
+ *  When set to 1, the low power mode is enable
+ *  When set to 0, the device stays in RUN mode
+ */
+#define CFG_LPM_SUPPORTED    1
+
+/******************************************************************************
+ * Timer Server
+ ******************************************************************************/
+/**
+ *  CFG_RTC_WUCKSEL_DIVIDER:  This sets the RTCCLK divider to the wakeup timer.
+ *  The higher is the value, the better is the power consumption and the accuracy of the timerserver
+ *  The lower is the value, the finest is the granularity
+ *
+ *  CFG_RTC_ASYNCH_PRESCALER: This sets the asynchronous prescaler of the RTC. It should as high as possible ( to ouput
+ *  clock as low as possible) but the output clock should be equal or higher frequency compare to the clock feeding
+ *  the wakeup timer. A lower clock speed would impact the accuracy of the timer server.
+ *
+ *  CFG_RTC_SYNCH_PRESCALER: This sets the synchronous prescaler of the RTC.
+ *  When the 1Hz calendar clock is required, it shall be sets according to other settings
+ *  When the 1Hz calendar clock is not needed, CFG_RTC_SYNCH_PRESCALER should be set to 0x7FFF (MAX VALUE)
+ *
+ *  CFG_RTCCLK_DIVIDER_CONF:
+ *  Shall be set to either 0,2,4,8,16
+ *  When set to either 2,4,8,16, the 1Hhz calendar is supported
+ *  When set to 0, the user sets its own configuration
+ *
+ *  The following settings are computed with LSI as input to the RTC
+ */
+#define CFG_RTCCLK_DIVIDER_CONF 0
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 0)
+/**
+ * Custom configuration
+ * It does not support 1Hz calendar
+ * It divides the RTC CLK by 16
+ */
+#define CFG_RTCCLK_DIV  (16)
+#define CFG_RTC_WUCKSEL_DIVIDER (0)
+#define CFG_RTC_ASYNCH_PRESCALER (CFG_RTCCLK_DIV - 1)
+#define CFG_RTC_SYNCH_PRESCALER (0x7FFF)
+
+#else
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 2)
+/**
+ * It divides the RTC CLK by 2
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (3)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 4)
+/**
+ * It divides the RTC CLK by 4
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (2)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 8)
+/**
+ * It divides the RTC CLK by 8
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (1)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 16)
+/**
+ * It divides the RTC CLK by 16
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (0)
+#endif
+
+#define CFG_RTCCLK_DIV              CFG_RTCCLK_DIVIDER_CONF
+#define CFG_RTC_ASYNCH_PRESCALER    (CFG_RTCCLK_DIV - 1)
+#define CFG_RTC_SYNCH_PRESCALER     (DIVR( LSE_VALUE, (CFG_RTC_ASYNCH_PRESCALER+1) ) - 1 )
+
+#endif
+
+/** tick timer value in us */
+#define CFG_TS_TICK_VAL           DIVR( (CFG_RTCCLK_DIV * 1000000), LSE_VALUE )
+
+typedef enum
+{
+  CFG_TIM_PROC_ID_ISR,
+} CFG_TimProcID_t;
+
+/******************************************************************************
+ * Debug
+ ******************************************************************************/
+/**
+ * When set, this resets some hw resources to set the device in the same state than the power up
+ * The FW resets only register that may prevent the FW to run properly
+ *
+ * This shall be set to 0 in a final product
+ *
+ */
+#define CFG_HW_RESET_BY_FW         1
+
+/**
+ * keep debugger enabled while in any low power mode when set to 1
+ * should be set to 0 in production
+ */
+#define CFG_DEBUGGER_SUPPORTED    0
+
+/**
+ * When set to 1, the traces are enabled in the BLE services
+ */
+#define CFG_DEBUG_BLE_TRACE     0
+
+/**
+ * Enable or Disable traces in application
+ */
+#define CFG_DEBUG_APP_TRACE     0
+
+#if (CFG_DEBUG_APP_TRACE != 0)
+#define APP_DBG_MSG                 PRINT_MESG_DBG
+#else
+#define APP_DBG_MSG                 PRINT_NO_MESG
+#endif
+
+#if ( (CFG_DEBUG_BLE_TRACE != 0) || (CFG_DEBUG_APP_TRACE != 0) )
+#define CFG_DEBUG_TRACE             1
+#endif
+
+#if (CFG_DEBUG_TRACE != 0)
+#undef CFG_LPM_SUPPORTED
+#undef CFG_DEBUGGER_SUPPORTED
+#define CFG_LPM_SUPPORTED         0
+#define CFG_DEBUGGER_SUPPORTED      1
+#endif
+
+/**
+ * When CFG_DEBUG_TRACE_FULL is set to 1, the trace are output with the API name, the file name and the line number
+ * When CFG_DEBUG_TRACE_LIGHT is set to 1, only the debug message is output
+ *
+ * When both are set to 0, no trace are output
+ * When both are set to 1,  CFG_DEBUG_TRACE_FULL is selected
+ */
+#define CFG_DEBUG_TRACE_LIGHT    0
+#define CFG_DEBUG_TRACE_FULL     0
+
+#if (( CFG_DEBUG_TRACE != 0 ) && ( CFG_DEBUG_TRACE_LIGHT == 0 ) && (CFG_DEBUG_TRACE_FULL == 0))
+#undef CFG_DEBUG_TRACE_FULL
+#undef CFG_DEBUG_TRACE_LIGHT
+#define CFG_DEBUG_TRACE_FULL      0
+#define CFG_DEBUG_TRACE_LIGHT     1
+#endif
+
+#if ( CFG_DEBUG_TRACE == 0 )
+#undef CFG_DEBUG_TRACE_FULL
+#undef CFG_DEBUG_TRACE_LIGHT
+#define CFG_DEBUG_TRACE_FULL      0
+#define CFG_DEBUG_TRACE_LIGHT     0
+#endif
+
+/**
+ * When not set, the traces is looping on sending the trace over UART
+ */
+#define DBG_TRACE_USE_CIRCULAR_QUEUE 1
+
+/**
+ * max buffer Size to queue data traces and max data trace allowed.
+ * Only Used if DBG_TRACE_USE_CIRCULAR_QUEUE is defined
+ */
+#define DBG_TRACE_MSG_QUEUE_SIZE 4096
+#define MAX_DBG_TRACE_MSG_SIZE 1024
+
+/* USER CODE BEGIN Defines */
+#define CFG_LED_SUPPORTED         0
+#define CFG_BUTTON_SUPPORTED      1
+/* USER CODE END Defines */
+
+/******************************************************************************
+ * FreeRTOS
+ ******************************************************************************/
+#define CFG_SHCI_USER_EVT_PROCESS_NAME        "SHCI_USER_EVT_PROCESS"
+#define CFG_SHCI_USER_EVT_PROCESS_ATTR_BITS   (0)
+#define CFG_SHCI_USER_EVT_PROCESS_CB_MEM      (0)
+#define CFG_SHCI_USER_EVT_PROCESS_CB_SIZE     (0)
+#define CFG_SHCI_USER_EVT_PROCESS_STACK_MEM   (0)
+#define CFG_SHCI_USER_EVT_PROCESS_PRIORITY    osPriorityNone
+#define CFG_SHCI_USER_EVT_PROCESS_STACk_SIZE  (128 * 7)
+
+#define CFG_HCI_USER_EVT_PROCESS_NAME         "HCI_USER_EVT_PROCESS"
+#define CFG_HCI_USER_EVT_PROCESS_ATTR_BITS    (0)
+#define CFG_HCI_USER_EVT_PROCESS_CB_MEM       (0)
+#define CFG_HCI_USER_EVT_PROCESS_CB_SIZE      (0)
+#define CFG_HCI_USER_EVT_PROCESS_STACK_MEM    (0)
+#define CFG_HCI_USER_EVT_PROCESS_PRIORITY     osPriorityNone
+#define CFG_HCI_USER_EVT_PROCESS_STACk_SIZE   (128 * 2)
+
+#define CFG_ADV_UPDATE_PROCESS_NAME           "ADV_UPDATE_PROCESS"
+#define CFG_ADV_UPDATE_PROCESS_ATTR_BITS      (0)
+#define CFG_ADV_UPDATE_PROCESS_CB_MEM         (0)
+#define CFG_ADV_UPDATE_PROCESS_CB_SIZE        (0)
+#define CFG_ADV_UPDATE_PROCESS_STACK_MEM      (0)
+#define CFG_ADV_UPDATE_PROCESS_PRIORITY       osPriorityNone
+#define CFG_ADV_UPDATE_PROCESS_STACk_SIZE     (128 * 6)
+
+#define CFG_HRS_PROCESS_NAME                  "HRS_PROCESS"
+#define CFG_HRS_PROCESS_ATTR_BITS             (0)
+#define CFG_HRS_PROCESS_CB_MEM                (0)
+#define CFG_HRS_PROCESS_CB_SIZE               (0)
+#define CFG_HRS_PROCESS_STACK_MEM             (0)
+#define CFG_HRS_PROCESS_PRIORITY              osPriorityNone
+#define CFG_HRS_PROCESS_STACk_SIZE            (128 * 5)
+/* USER CODE BEGIN FreeRTOS_Defines */
+#ifdef LITTLE_DORY
+#define PUSH_BUTTON_SW1_EXTI_IRQHandler                         EXTI0_IRQHandler
+#define PUSH_BUTTON_SW2_EXTI_IRQHandler                         EXTI4_IRQHandler
+#define PUSH_BUTTON_SW3_EXTI_IRQHandler                         EXTI9_5_IRQHandler
+#else
+#define PUSH_BUTTON_SW1_EXTI_IRQHandler                         EXTI4_IRQHandler
+#define PUSH_BUTTON_SW2_EXTI_IRQHandler                         EXTI0_IRQHandler
+#define PUSH_BUTTON_SW3_EXTI_IRQHandler                         EXTI1_IRQHandler
+#endif
+/* USER CODE END FreeRTOS_Defines */
+
+/******************************************************************************
+ * LOW POWER
+ ******************************************************************************/
+/**
+ * Supported requester to the MCU Low Power Manager - can be increased up  to 32
+ * It lits a bit mapping of all user of the Low Power Manager
+ */
+typedef enum
+{
+    CFG_LPM_APP,
+    CFG_LPM_APP_BLE,
+  /* USER CODE BEGIN CFG_LPM_Id_t */
+
+  /* USER CODE END CFG_LPM_Id_t */
+} CFG_LPM_Id_t;
+
+/******************************************************************************
+ * OTP manager
+ ******************************************************************************/
+#define CFG_OTP_BASE_ADDRESS    OTP_AREA_BASE
+
+#define CFG_OTP_END_ADRESS      OTP_AREA_END_ADDR
+
+#endif /*APP_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_debug.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_debug.h
new file mode 100644
index 000000000..13485c16b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_debug.h
@@ -0,0 +1,45 @@
+
+/**
+  ******************************************************************************
+  * @file    app_debug.h
+  * @author  MCD Application Team
+  * @brief   Interface to support debug in the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+  /* Exported types ------------------------------------------------------------*/
+  /* Exported constants --------------------------------------------------------*/
+  /* External variables --------------------------------------------------------*/
+  /* Exported macros -----------------------------------------------------------*/
+  /* Exported functions ------------------------------------------------------- */
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_entry.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_entry.h
new file mode 100644
index 000000000..77ead2384
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_entry.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    app_entry.h
+  * @author  MCD Application Team
+  * @brief   Interface to the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_ENTRY_H
+#define APP_ENTRY_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APPE_Init( void );
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*APP_ENTRY_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/hw_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/hw_conf.h
new file mode 100644
index 000000000..923d23fd6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/hw_conf.h
@@ -0,0 +1,198 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : hw_conf.h
+  * Description        : Hardware configuration file for BLE 
+  *                      middleWare.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef HW_CONF_H
+#define HW_CONF_H
+
+#include "FreeRTOSConfig.h"
+
+/******************************************************************************
+* Semaphores
+* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
+*****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
+/* Index of the semaphore used to manage the entry Stop Mode procedure */
+#define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
+
+/* Index of the semaphore used to access the RCC */
+#define CFG_HW_RCC_SEMID                                        3
+
+/* Index of the semaphore used to access the FLASH */
+#define CFG_HW_FLASH_SEMID                                      2
+
+/* Index of the semaphore used to access the PKA */
+#define CFG_HW_PKA_SEMID                                        1
+
+/* Index of the semaphore used to access the RNG */
+#define CFG_HW_RNG_SEMID                                        0
+
+/******************************************************************************
+ * HW TIMER SERVER
+ *****************************************************************************/
+/**
+ * The user may define the maximum number of virtual timers supported.
+ * It shall not exceed 255
+ */
+#define CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER  6
+
+/**
+ * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
+ * wakeup timer.
+ * This setting is the preemptpriority part of the NVIC.
+ */
+#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO    (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1) /* FreeRTOS requirement */
+
+/**
+ * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
+ * wakeup timer.
+ * This setting is the subpriority part of the NVIC. It does not exist on all processors. When it is not supported
+ * on the CPU, the setting is ignored
+ */
+#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO  0
+
+/**
+ *  Define a critical section in the Timer server
+ *  The Timer server does not support the API to be nested
+ *  The  Application shall either:
+ *    a) Ensure this will never happen
+ *    b) Define the critical section
+ *  The default implementations is masking all interrupts using the PRIMASK bit
+ *  The TimerServer driver uses critical sections to avoid context corruption. This is achieved with the macro
+ *  TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION. When CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION is set
+ *  to 1, all STM32 interrupts are masked with the PRIMASK bit of the CortexM CPU. It is possible to use the BASEPRI
+ *  register of the CortexM CPU to keep allowed some interrupts with high priority. In that case, the user shall
+ *  re-implement TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION and shall make sure that no TimerServer
+ *  API are called when the TIMER critical section is entered
+ */
+#define CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION  1
+
+/**
+   * This value shall reflect the maximum delay there could be in the application between the time the RTC interrupt
+   * is generated by the Hardware and the time when the  RTC interrupt handler is called. This time is measured in
+   * number of RTCCLK ticks.
+   * A relaxed timing would be 10ms
+   * When the value is too short, the timerserver will not be able to count properly and all timeout may be random.
+   * When the value is too long, the device may wake up more often than the most optimal configuration. However, the
+   * impact on power consumption would be marginal (unless the value selected is extremely too long). It is strongly
+   * recommended to select a value large enough to make sure it is not too short to ensure reliability of the system
+   * as this will have marginal impact on low power mode
+   */
+#define CFG_HW_TS_RTC_HANDLER_MAX_DELAY  ( 10 * (LSI_VALUE/1000) )
+
+  /**
+   * Interrupt ID in the NVIC of the RTC Wakeup interrupt handler
+   * It shall be type of IRQn_Type
+   */
+#define CFG_HW_TS_RTC_WAKEUP_HANDLER_ID  RTC_WKUP_IRQn
+
+/******************************************************************************
+ * HW UART
+ *****************************************************************************/
+
+#define CFG_HW_LPUART1_ENABLED           0
+#define CFG_HW_LPUART1_DMA_TX_SUPPORTED  0
+
+#define CFG_HW_USART1_ENABLED           1
+#define CFG_HW_USART1_DMA_TX_SUPPORTED  1
+
+/**
+ * UART1
+ */
+#define CFG_HW_USART1_PREEMPTPRIORITY         0x0F
+#define CFG_HW_USART1_SUBPRIORITY             0
+
+/** < The application shall check the selected source clock is enable */
+#define CFG_HW_USART1_SOURCE_CLOCK              RCC_USART1CLKSOURCE_SYSCLK
+
+#define CFG_HW_USART1_BAUDRATE                115200
+#define CFG_HW_USART1_WORDLENGTH              UART_WORDLENGTH_8B
+#define CFG_HW_USART1_STOPBITS                UART_STOPBITS_1
+#define CFG_HW_USART1_PARITY                  UART_PARITY_NONE
+#define CFG_HW_USART1_HWFLOWCTL               UART_HWCONTROL_NONE
+#define CFG_HW_USART1_MODE                    UART_MODE_TX_RX
+#define CFG_HW_USART1_ADVFEATUREINIT          UART_ADVFEATURE_NO_INIT
+#define CFG_HW_USART1_OVERSAMPLING            UART_OVERSAMPLING_8
+
+#define CFG_HW_USART1_TX_PORT_CLK_ENABLE      __HAL_RCC_GPIOB_CLK_ENABLE
+#define CFG_HW_USART1_TX_PORT                 GPIOB
+#define CFG_HW_USART1_TX_PIN                  GPIO_PIN_6
+#define CFG_HW_USART1_TX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_USART1_TX_PULL                 GPIO_NOPULL
+#define CFG_HW_USART1_TX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_TX_ALTERNATE            GPIO_AF7_USART1
+
+#define CFG_HW_USART1_RX_PORT_CLK_ENABLE      __HAL_RCC_GPIOB_CLK_ENABLE
+#define CFG_HW_USART1_RX_PORT                 GPIOB
+#define CFG_HW_USART1_RX_PIN                  GPIO_PIN_7
+#define CFG_HW_USART1_RX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_USART1_RX_PULL                 GPIO_NOPULL
+#define CFG_HW_USART1_RX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_RX_ALTERNATE            GPIO_AF7_USART1
+
+#define CFG_HW_USART1_CTS_PORT_CLK_ENABLE     __HAL_RCC_GPIOA_CLK_ENABLE
+#define CFG_HW_USART1_CTS_PORT                GPIOA
+#define CFG_HW_USART1_CTS_PIN                 GPIO_PIN_11
+#define CFG_HW_USART1_CTS_MODE                GPIO_MODE_AF_PP
+#define CFG_HW_USART1_CTS_PULL                GPIO_PULLDOWN
+#define CFG_HW_USART1_CTS_SPEED               GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_CTS_ALTERNATE           GPIO_AF7_USART1
+
+#define CFG_HW_USART1_DMA_TX_PREEMPTPRIORITY  0x0F
+#define CFG_HW_USART1_DMA_TX_SUBPRIORITY      0
+
+#define CFG_HW_USART1_DMAMUX_CLK_ENABLE       __HAL_RCC_DMAMUX1_CLK_ENABLE
+#define CFG_HW_USART1_DMA_CLK_ENABLE          __HAL_RCC_DMA2_CLK_ENABLE
+#define CFG_HW_USART1_TX_DMA_REQ			  DMA_REQUEST_USART1_TX
+#define CFG_HW_USART1_TX_DMA_CHANNEL          DMA2_CHANNEL_4
+#define CFG_HW_USART1_TX_DMA_IRQn             DMA2_CHANNEL_4_IRQn
+#define CFG_HW_USART1_DMA_TX_IRQHandler       DMA2_CHANNEL_4_IRQHandler
+
+#endif /*HW_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/hw_if.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/hw_if.h
new file mode 100644
index 000000000..5a15665ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/hw_if.h
@@ -0,0 +1,254 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    hw_if.h
+  * @author  MCD Application Team
+  * @brief   Hardware Interface
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef HW_IF_H
+#define HW_IF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_ipcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_hsem.h"
+#include "stm32wbxx_ll_gpio.h"
+#include "stm32wbxx_ll_rtc.h"
+
+#ifdef  USE_STM32WBXX_USB_DONGLE
+#include "stm32wbxx_usb_dongle.h"
+#endif
+#ifdef  USE_STM32WBXX_NUCLEO
+  #ifdef STM32WB35xx
+  #include "nucleo_wb35ce.h"
+  #else
+  #include "stm32wbxx_nucleo.h"
+  #endif
+#endif
+#ifdef  USE_X_NUCLEO_EPD
+#include "x_nucleo_epd.h"
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /******************************************************************************
+   * HW UART
+   ******************************************************************************/
+  typedef enum
+  {
+    hw_uart1,
+    hw_uart2,
+    hw_lpuart1,
+  } hw_uart_id_t;
+
+  typedef enum
+  {
+    hw_uart_ok,
+    hw_uart_error,
+    hw_uart_busy,
+    hw_uart_to,
+  } hw_status_t;
+
+  void HW_UART_Init(hw_uart_id_t hw_uart_id);
+  void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *pData, uint16_t Size, void (*Callback)(void));
+  void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *pData, uint16_t Size,  void (*Callback)(void));
+  hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout);
+  hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*Callback)(void));
+  void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id);
+  void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id);
+
+  /******************************************************************************
+   * HW TimerServer
+   ******************************************************************************/
+  /* Exported types ------------------------------------------------------------*/
+  /**
+   * This setting is used when standby mode is supported.
+   * hw_ts_InitMode_Limited should be used when the device restarts from Standby Mode. In that case, the Timer Server does
+   * not re-initialized its context. Only the Hardware register which content has been lost is reconfigured
+   * Otherwise, hw_ts_InitMode_Full should be requested (Start from Power ON) and everything is re-initialized.
+   */
+  typedef enum
+  {
+    hw_ts_InitMode_Full,
+    hw_ts_InitMode_Limited,
+  } HW_TS_InitMode_t;
+
+  /**
+   * When a Timer is created as a SingleShot timer, it is not automatically restarted when the timeout occurs. However,
+   * the timer is kept reserved in the list and could be restarted at anytime with HW_TS_Start()
+   *
+   * When a Timer is created as a Repeated timer, it is automatically restarted when the timeout occurs.
+   */
+  typedef enum
+  {
+    hw_ts_SingleShot,
+    hw_ts_Repeated
+  } HW_TS_Mode_t;
+
+  /**
+   * hw_ts_Successful is returned when a Timer has been successfully created with HW_TS_Create(). Otherwise, hw_ts_Failed
+   * is returned. When hw_ts_Failed is returned, that means there are not enough free slots in the list to create a
+   * Timer. In that case, CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER should be increased
+   */
+  typedef enum
+  {
+    hw_ts_Successful,
+    hw_ts_Failed,
+  }HW_TS_ReturnStatus_t;
+
+  typedef void (*HW_TS_pTimerCb_t)(void);
+
+  /**
+   * @brief  Initialize the timer server
+   *         This API shall be called by the application before any timer is requested to the timer server. It
+   *         configures the RTC module to be connected to the LSI input clock.
+   *
+   * @param  TimerInitMode: When the device restarts from Standby, it should request hw_ts_InitMode_Limited so that the
+   *         Timer context is not re-initialized. Otherwise, hw_ts_InitMode_Full should be requested
+   * @param  hrtc: RTC Handle
+   * @retval None
+   */
+  void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *hrtc);
+
+  /**
+   * @brief  Interface to create a virtual timer
+   *         The user shall call this API to create a timer. Once created, the timer is reserved to the module until it
+   *         has been deleted. When creating a timer, the user shall specify the mode (single shot or repeated), the
+   *         callback to be notified when the timer expires and a module ID to identify in the timer interrupt handler
+   *         which module is concerned. In return, the user gets a timer ID to handle it.
+   *
+   * @param  TimerProcessID:  This is an identifier provided by the user and returned in the callback to allow
+   *                          identification of the requester
+   * @param  pTimerId: Timer Id returned to the user to request operation (start, stop, delete)
+   * @param  TimerMode: Mode of the virtual timer (Single shot or repeated)
+   * @param  pTimerCallBack: Callback when the virtual timer expires
+   * @retval HW_TS_ReturnStatus_t: Return whether the creation is sucessfull or not
+   */
+  HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pTimerCallBack);
+
+  /**
+   * @brief  Stop a virtual timer
+   *         This API may be used to stop a running timer. A timer which is stopped is move to the pending state.
+   *         A pending timer may be restarted at any time with a different timeout value but the mode cannot be changed.
+   *         Nothing is done when it is called to stop a timer which has been already stopped
+   *
+   * @param  TimerID:  Id of the timer to stop
+   * @retval None
+   */
+  void HW_TS_Stop(uint8_t TimerID);
+
+  /**
+   * @brief  Start a virtual timer
+   *         This API shall be used to start a timer. The timeout value is specified and may be different each time.
+   *         When the timer is in the single shot mode, it will move to the pending state when it expires. The user may
+   *         restart it at any time with a different timeout value. When the timer is in the repeated mode, it always
+   *         stay in the running state. When the timer expires, it will be restarted with the same timeout value.
+   *         This API shall not be called on a running timer.
+   *
+   * @param  TimerID:  The ID Id of the timer to start
+   * @param  timeout_ticks: Number of ticks of the virtual timer (Maximum value is (0xFFFFFFFF-0xFFFF = 0xFFFF0000)
+   * @retval None
+   */
+  void HW_TS_Start(uint8_t TimerID, uint32_t timeout_ticks);
+
+  /**
+   * @brief  Delete a virtual timer from the list
+   *         This API should be used when a timer is not needed anymore by the user. A deleted timer is removed from
+   *         the timer list managed by the timer server. It cannot be restarted again. The user has to go with the
+   *         creation of a new timer if required and may get a different timer id
+   *
+   * @param  TimerID:  The ID of the timer to remove from the list
+   * @retval None
+   */
+  void HW_TS_Delete(uint8_t TimerID);
+
+  /**
+   * @brief  Schedule the timer list on the timer interrupt handler
+   *         This interrupt handler shall be called by the application in the RTC interrupt handler. This handler takes
+   *         care of clearing all status flag required in the RTC and EXTI peripherals
+   *
+   * @param  None
+   * @retval None
+   */
+  void HW_TS_RTC_Wakeup_Handler(void);
+
+  /**
+   * @brief  Return the number of ticks to count before the interrupt
+   *         This API returns the number of ticks left to be counted before an interrupt is generated by the
+   *         Timer Server. This API may be used by the application for power management optimization. When the system
+   *         enters low power mode, the mode selection is a tradeoff between the wakeup time where the CPU is running
+   *         and the time while the CPU will be kept in low power mode before next wakeup. The deeper is the
+   *         low power mode used, the longer is the wakeup time. The low power mode management considering wakeup time
+   *         versus time in low power mode is implementation specific
+   *         When the timer is disabled (No timer in the list), it returns 0xFFFF
+   *
+   * @param  None
+   * @retval The number of ticks left to count
+   */
+  uint16_t HW_TS_RTC_ReadLeftTicksToCount(void);
+
+  /**
+   * @brief  Notify the application that a registered timer has expired
+   *         This API shall be implemented by the user application.
+   *         This API notifies the application that a timer expires. This API is running in the RTC Wakeup interrupt
+   *         context. The application may implement an Operating System to change the context priority where the timer
+   *         callback may be handled. This API provides the module ID to identify which module is concerned and to allow
+   *         sending the information to the correct task
+   *
+   * @param  TimerProcessID: The TimerProcessId associated with the timer when it has been created
+   * @param  TimerID: The TimerID of the expired timer
+   * @param  pTimerCallBack: The Callback associated with the timer when it has been created
+   * @retval None
+   */
+  void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack);
+
+  /**
+   * @brief  Notify the application that the wakeupcounter has been updated
+   *         This API should be implemented by the user application
+   *         This API notifies the application that the counter has been updated. This is expected to be used along
+   *         with the HW_TS_RTC_ReadLeftTicksToCount () API. It could be that the counter has been updated since the
+   *         last call of HW_TS_RTC_ReadLeftTicksToCount () and before entering low power mode. This notification
+   *         provides a way to the application to solve that race condition to reevaluate the counter value before
+   *         entering low power mode
+   *
+   * @param  None
+   * @retval None
+   */
+  void HW_TS_RTC_CountUpdated_AppNot(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*HW_IF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/main.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/main.h
new file mode 100644
index 000000000..c8b13c23f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/main.h
@@ -0,0 +1,75 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#ifdef STM32WB35xx
+#include "nucleo_wb35ce.h"
+#else
+#include "stm32wbxx_nucleo.h"
+#endif
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/stm32_lpm_if.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/stm32_lpm_if.h
new file mode 100644
index 000000000..d8e67947f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/stm32_lpm_if.h
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+******************************************************************************
+* @file    stm32_lpm_if.h
+* @brief   Header for stm32_lpm_if.c module (device specific LP management)
+******************************************************************************
+* @attention
+*
+* 
    © Copyright (c) 2019 STMicroelectronics. 
+* All rights reserved.
    
+*
+* This software component is licensed by ST under BSD 3-Clause license,
+* the "License"; You may not use this file except in compliance with the 
+* License. You may obtain a copy of the License at:
+*                        opensource.org/licenses/BSD-3-Clause
+*
+******************************************************************************
+*/
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_LPM_IF_H
+#define __STM32_LPM_IF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/**
+  * @brief Enters Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_EnterOffMode( void );
+/**
+  * @brief Exits Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_ExitOffMode( void );
+
+/**
+  * @brief Enters Low Power Stop Mode
+  * @note ARM exists the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterStopMode( void );
+/**
+  * @brief Exits Low Power Stop Mode
+  * @note Enable the pll at 32MHz
+  * @param none
+  * @retval none
+  */
+void PWR_ExitStopMode( void );
+
+/**
+  * @brief Enters Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterSleepMode( void );
+
+/**
+  * @brief Exits Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_ExitSleepMode( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32_LPM_IF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..b5b48da1a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,354 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+#define HAL_CORTEX_MODULE_ENABLED
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+/*#define HAL_I2C_MODULE_ENABLED   */
+#define HAL_IPCC_MODULE_ENABLED
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+#define HAL_PWR_MODULE_ENABLED
+/*#define HAL_QSPI_MODULE_ENABLED   */
+#define HAL_RCC_MODULE_ENABLED
+/*#define HAL_RNG_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100UL)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  (32000UL)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  (32000UL)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    (48000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    (2097000UL) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..eaceee861
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/stm32wbxx_it.h
@@ -0,0 +1,77 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "app_common.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void DebugMon_Handler(void);
+void DMA1_Channel4_IRQHandler(void);
+void TIM1_TRG_COM_TIM17_IRQHandler(void);
+void USART1_IRQHandler(void);
+void LPUART1_IRQHandler(void);
+void DMA2_Channel4_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+void RTC_WKUP_IRQHandler(void);
+void IPCC_C1_TX_IRQHandler(void);
+void IPCC_C1_RX_IRQHandler(void);
+void PUSH_BUTTON_SW1_EXTI_IRQHandler(void);
+void PUSH_BUTTON_SW2_EXTI_IRQHandler(void);
+void PUSH_BUTTON_SW3_EXTI_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/utilities_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/utilities_conf.h
new file mode 100644
index 000000000..4dde3509a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/utilities_conf.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : utilities_conf.h
+  * Description        : Configuration file for STM32 Utilities.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef UTILITIES_CONF_H
+#define UTILITIES_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "cmsis_compiler.h"
+#include "string.h"
+
+/******************************************************************************
+ * common
+ ******************************************************************************/
+#define UTILS_ENTER_CRITICAL_SECTION( )   uint32_t primask_bit = __get_PRIMASK( );\
+                                          __disable_irq( )
+
+#define UTILS_EXIT_CRITICAL_SECTION( )          __set_PRIMASK( primask_bit )
+
+#define UTILS_MEMSET8( dest, value, size )      memset( dest, value, size);
+
+/******************************************************************************
+ * tiny low power manager
+ * (any macro that does not need to be modified can be removed)
+ ******************************************************************************/
+#define UTIL_LPM_INIT_CRITICAL_SECTION( )
+#define UTIL_LPM_ENTER_CRITICAL_SECTION( )      UTILS_ENTER_CRITICAL_SECTION( )
+#define UTIL_LPM_EXIT_CRITICAL_SECTION( )       UTILS_EXIT_CRITICAL_SECTION( )
+
+/******************************************************************************
+ * sequencer
+ * (any macro that does not need to be modified can be removed)
+ ******************************************************************************/
+#define UTIL_SEQ_INIT_CRITICAL_SECTION( )
+#define UTIL_SEQ_ENTER_CRITICAL_SECTION( )      UTILS_ENTER_CRITICAL_SECTION( )
+#define UTIL_SEQ_EXIT_CRITICAL_SECTION( )       UTILS_EXIT_CRITICAL_SECTION( )
+#define UTIL_SEQ_CONF_TASK_NBR                  (32)
+#define UTIL_SEQ_CONF_PRIO_NBR                  (2)
+#define UTIL_SEQ_MEMSET8( dest, value, size )   UTILS_MEMSET8( dest, value, size )
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*UTILITIES_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/vcp_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/vcp_conf.h
new file mode 100644
index 000000000..7280c33b9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/vcp_conf.h
@@ -0,0 +1,53 @@
+/**
+ ******************************************************************************
+ * @file    vcp_conf.h
+ * @author  MCD Application Team
+ * @brief   Configuration of the vcp interface
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __VCP_CONF_H
+#define __VCP_CONF_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+#define VCP_BAUD_RATE                             (115200)
+#define VCP_TX_PATH_INTERFACE_READY_SETUP_TIME    (20*1000*1000/CFG_TS_TICK_VAL)  /** 20s   */
+#define VCP_TASK_ID                               (CFG_TASK_VCP_SEND_DATA_ID)
+#define VCP_TASK_PRIO                             (CFG_SCH_PRIO_1)
+
+#ifdef  VCP_TX_PATH_INTERFACE_READY_SETUP_TIME
+#define VCP_TIMER_PROC_ID                         (CFG_TIM_PROC_ID_ISR)
+#endif
+
+/* External variables --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__VCP_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/app_debug.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/app_debug.c
new file mode 100644
index 000000000..af3fdfbce
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/app_debug.c
@@ -0,0 +1,360 @@
+/**
+ ******************************************************************************
+ * @file    app_debug.c
+ * @author  MCD Application Team
+ * @brief   Debug capabilities
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+extern void MX_LPUART1_UART_Init(void);
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+extern void MX_USART1_UART_Init(void);
+#endif
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+#if (CFG_HW_USART1_ENABLED == 1)
+    MX_USART1_UART_Init();
+#endif
+#if (CFG_HW_LPUART1_ENABLED == 1)
+    MX_LPUART1_UART_Init();
+#endif
+  return;
+}
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/app_entry.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/app_entry.c
new file mode 100644
index 000000000..4e023f827
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/app_entry.c
@@ -0,0 +1,336 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : app_entry.c
+  * Description        : Entry application source file for STM32WPAN Middleware
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "main.h"
+#include "app_entry.h"
+#include "app_ble.h"
+#include "ble.h"
+#include "tl.h"
+#include "cmsis_os.h"
+#include "shci_tl.h"
+#include "stm32_lpm.h"
+#include "app_debug.h"
+
+/* Private includes -----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+extern RTC_HandleTypeDef hrtc;
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+#define POOL_SIZE (CFG_TLBLE_EVT_QUEUE_LENGTH*4U*DIVC(( sizeof(TL_PacketHeader_t) + TL_BLE_EVENT_FRAME_SIZE ), 4U))
+
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t EvtPool[POOL_SIZE];
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static TL_CmdPacket_t SystemCmdBuffer;
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t SystemSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255U];
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t BleSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255];
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Global variables ----------------------------------------------------------*/
+osMutexId_t MtxShciId;
+osSemaphoreId_t SemShciId;
+osThreadId_t ShciUserEvtProcessId;
+
+const osThreadAttr_t ShciUserEvtProcess_attr = {
+    .name = CFG_SHCI_USER_EVT_PROCESS_NAME,
+    .attr_bits = CFG_SHCI_USER_EVT_PROCESS_ATTR_BITS,
+    .cb_mem = CFG_SHCI_USER_EVT_PROCESS_CB_MEM,
+    .cb_size = CFG_SHCI_USER_EVT_PROCESS_CB_SIZE,
+    .stack_mem = CFG_SHCI_USER_EVT_PROCESS_STACK_MEM,
+    .priority = CFG_SHCI_USER_EVT_PROCESS_PRIORITY,
+    .stack_size = CFG_SHCI_USER_EVT_PROCESS_STACk_SIZE
+};
+
+/* Private functions prototypes-----------------------------------------------*/
+static void ShciUserEvtProcess(void *argument);
+static void SystemPower_Config( void );
+static void appe_Tl_Init( void );
+static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status );
+static void APPE_SysUserEvtRx( void * pPayload );
+
+/* USER CODE BEGIN PFP */
+static void Led_Init( void );
+static void Button_Init( void );
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APPE_Init( void )
+{
+  SystemPower_Config(); /**< Configure the system Power Mode */
+
+  HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
+
+/* USER CODE BEGIN APPE_Init_1 */
+  APPD_Init();
+
+  /**
+   * The Standby mode should not be entered before the initialization is over
+   * The default state of the Low Power Manager is to allow the Standby Mode so an request is needed here
+   */
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP, UTIL_LPM_DISABLE);
+
+  Led_Init();
+
+  Button_Init();
+/* USER CODE END APPE_Init_1 */
+  appe_Tl_Init();	/* Initialize all transport layers */
+
+  /**
+   * From now, the application is waiting for the ready event ( VS_HCI_C2_Ready )
+   * received on the system channel before starting the Stack
+   * This system event is received with APPE_SysUserEvtRx()
+   */
+/* USER CODE BEGIN APPE_Init_2 */
+
+/* USER CODE END APPE_Init_2 */
+  return;
+}
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+ * @brief  Configure the system for power optimization
+ *
+ * @note  This API configures the system to be ready for low power mode
+ *
+ * @param  None
+ * @retval None
+ */
+static void SystemPower_Config( void )
+{
+
+  /**
+   * Select HSI as system clock source after Wake Up from Stop mode
+   */
+  LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
+
+  /* Initialize low power manager */
+  UTIL_LPM_Init( );
+
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+  /**
+   *  Enable USB power
+   */
+  HAL_PWREx_EnableVddUSB();
+#endif
+
+  return;
+}
+
+static void appe_Tl_Init( void )
+{
+  TL_MM_Config_t tl_mm_config;
+  SHCI_TL_HciInitConf_t SHci_Tl_Init_Conf;
+  /**< Reference table initialization */
+  TL_Init();
+
+  MtxShciId = osMutexNew( NULL );
+  SemShciId = osSemaphoreNew( 1, 0, NULL ); /*< Create the semaphore and make it busy at initialization */
+
+  /**< System channel initialization */
+  ShciUserEvtProcessId = osThreadNew(ShciUserEvtProcess, NULL, &ShciUserEvtProcess_attr);
+  SHci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&SystemCmdBuffer;
+  SHci_Tl_Init_Conf.StatusNotCallBack = APPE_SysStatusNot;
+  shci_init(APPE_SysUserEvtRx, (void*) &SHci_Tl_Init_Conf);
+
+  /**< Memory Manager channel initialization */
+  tl_mm_config.p_BleSpareEvtBuffer = BleSpareEvtBuffer;
+  tl_mm_config.p_SystemSpareEvtBuffer = SystemSpareEvtBuffer;
+  tl_mm_config.p_AsynchEvtPool = EvtPool;
+  tl_mm_config.AsynchEvtPoolSize = POOL_SIZE;
+  TL_MM_Init( &tl_mm_config );
+
+  TL_Enable();
+
+  return;
+}
+
+static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status )
+{
+  switch (status)
+  {
+    case SHCI_TL_CmdBusy:
+      osMutexAcquire( MtxShciId, osWaitForever );
+      break;
+
+    case SHCI_TL_CmdAvailable:
+      osMutexRelease( MtxShciId );
+      break;
+
+    default:
+      break;
+  }
+  return;
+}
+
+/**
+ * The type of the payload for a system user event is tSHCI_UserEvtRxParam
+ * When the system event is both :
+ *    - a ready event (subevtcode = SHCI_SUB_EVT_CODE_READY)
+ *    - reported by the FUS (sysevt_ready_rsp == RSS_FW_RUNNING)
+ * The buffer shall not be released
+ * ( eg ((tSHCI_UserEvtRxParam*)pPayload)->status shall be set to SHCI_TL_UserEventFlow_Disable )
+ * When the status is not filled, the buffer is released by default
+ */
+static void APPE_SysUserEvtRx( void * pPayload )
+{
+  UNUSED(pPayload);
+  /* Traces channel initialization */
+  APPD_EnableCPU2();
+
+  APP_BLE_Init( );
+  UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE);
+  return;
+}
+
+/*************************************************************
+ *
+ * FREERTOS WRAPPER FUNCTIONS
+ *
+*************************************************************/
+static void ShciUserEvtProcess(void *argument)
+{
+  UNUSED(argument);
+  for(;;)
+  {
+    /* USER CODE BEGIN SHCI_USER_EVT_PROCESS_1 */
+
+    /* USER CODE END SHCI_USER_EVT_PROCESS_1 */
+     osThreadFlagsWait(1, osFlagsWaitAny, osWaitForever);
+     shci_user_evt_proc();
+    /* USER CODE BEGIN SHCI_USER_EVT_PROCESS_2 */
+
+    /* USER CODE END SHCI_USER_EVT_PROCESS_2 */
+    }
+}
+
+/* USER CODE BEGIN FD_LOCAL_FUNCTIONS */
+static void Led_Init( void )
+{
+#if (CFG_LED_SUPPORTED == 1)
+  /**
+   * Leds Initialization
+   */
+
+  BSP_LED_Init(LED_BLUE);
+  BSP_LED_Init(LED_GREEN);
+  BSP_LED_Init(LED_RED);
+
+  BSP_LED_On(LED_GREEN);
+#endif
+
+  return;
+}
+
+static void Button_Init( void )
+{
+#if (CFG_BUTTON_SUPPORTED == 1)
+  /**
+   * Button Initialization
+   */
+
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+  BSP_PB_Init(BUTTON_SW2, BUTTON_MODE_EXTI);
+  BSP_PB_Init(BUTTON_SW3, BUTTON_MODE_EXTI);
+#endif
+
+  return;
+}
+
+/* USER CODE END FD_LOCAL_FUNCTIONS */
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+
+void shci_notify_asynch_evt(void* pdata)
+{
+  UNUSED(pdata);
+  osThreadFlagsSet( ShciUserEvtProcessId, 1 );
+  return;
+}
+
+void shci_cmd_resp_release(uint32_t flag)
+{
+  UNUSED(flag);
+  osSemaphoreRelease( SemShciId );
+  return;
+}
+
+void shci_cmd_resp_wait(uint32_t timeout)
+{
+  UNUSED(timeout);
+  osSemaphoreAcquire( SemShciId, osWaitForever );
+  return;
+}
+
+/* USER CODE BEGIN FD_WRAP_FUNCTIONS */
+void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin )
+{
+  switch (GPIO_Pin)
+  {
+    case BUTTON_SW1_PIN:
+     APP_BLE_Key_Button1_Action();
+      break; 
+
+    case BUTTON_SW2_PIN:
+      APP_BLE_Key_Button2_Action();
+      break; 
+
+    case BUTTON_SW3_PIN:
+      APP_BLE_Key_Button3_Action();
+      break;
+
+    default:
+      break;
+
+}
+  return;
+}
+/* USER CODE END FD_WRAP_FUNCTIONS */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/freertos_port.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/freertos_port.c
new file mode 100644
index 000000000..1348d0ffa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/freertos_port.c
@@ -0,0 +1,312 @@
+/**
+ ******************************************************************************
+ * File Name          : freertos_port.c
+ * Description        : Custom porting of FreeRTIS functionalities
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "stm32_lpm.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef struct
+{
+  uint32_t LpTimeLeftOnEntry;
+  uint8_t LpTimerFreeRTOS_Id;
+} LpTimerContext_t;
+
+/* Private defines -----------------------------------------------------------*/
+#ifndef configSYSTICK_CLOCK_HZ
+#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+/* Ensure the SysTick is clocked at the same frequency as the core. */
+#define portNVIC_SYSTICK_CLK_BIT        ( 1UL << 2UL )
+#else
+/* The way the SysTick is clocked is not modified in case it is not the same
+        as the core. */
+#define portNVIC_SYSTICK_CLK_BIT        ( 0 )
+#endif
+
+#define CPU_CLOCK_KHZ   ( configCPU_CLOCK_HZ / 1000 )
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG               ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG               ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSTICK_INT_BIT                ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT             ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+static uint32_t ulTimerCountsForOneTick;
+
+static LpTimerContext_t LpTimerContext;
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void LpTimerInit( void );
+static void LpTimerCb( void );
+static void LpTimerStart( uint32_t time_to_sleep );
+static void LpEnter( void );
+static uint32_t LpGetElapsedTime( void );
+void vPortSetupTimerInterrupt( void );
+
+/* Functions Definition ------------------------------------------------------*/
+
+/**
+ * @brief Implement the tickless feature
+ *
+ *
+ * @param: xExpectedIdleTime is given in number of FreeRTOS Ticks
+ * @retval: None
+ */
+void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+{
+  /**
+   * Although this is not documented as such, when xExpectedIdleTime = 0xFFFFFFFF = (~0),
+   * it likely means the system may enter low power for ever ( from a FreeRTOS point of view ).
+   * Otherwise, for a FreeRTOS tick set to 1ms, that would mean it is requested to wakeup in 8 years from now.
+   * When the system may enter low power mode for ever, FreeRTOS is not really interested to maintain a
+   * systick count and when the system exits from low power mode, there is no need to update the count with
+   * the time spent in low power mode
+   */
+    uint32_t ulCompleteTickPeriods;
+
+  /* Stop the SysTick  to avoid the interrupt to occur while in the critical section.
+   * Otherwise, this will prevent the device to enter low power mode
+   * At this time, an update of the systick will not be considered
+   *
+   */
+  portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+  /* Enter a critical section but don't use the taskENTER_CRITICAL()
+        method as that will mask interrupts that should exit sleep mode. */
+  __disable_irq();
+  __DSB();
+  __ISB();
+
+  /* If a context switch is pending or a task is waiting for the scheduler
+        to be unsuspended then abandon the low power entry. */
+  if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+  {
+    /* Restart SysTick. */
+    portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+    /* Re-enable interrupts - see comments above __disable_interrupt()
+                call above. */
+    __enable_irq();
+  }
+  else
+  {
+    if (xExpectedIdleTime != (~0))
+    {
+      /* Start the low power timer */
+      LpTimerStart( xExpectedIdleTime );
+    }
+
+    /* Enter low power mode */
+    LpEnter( );
+
+    if (xExpectedIdleTime != (~0))
+    {
+      /**
+       * Get the number of FreeRTOS ticks that has been suppressed
+       * In the current implementation, this shall be kept in critical section
+       * so that the timer server return the correct elapsed time
+       */
+      ulCompleteTickPeriods = LpGetElapsedTime( );
+      vTaskStepTick( ulCompleteTickPeriods );
+    }
+
+    /* Restart SysTick */
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+    portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+    portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+    /* Exit with interrUpts enabled. */
+    __enable_irq();
+  }
+}
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency and initialize a low power timer
+ * The current implementation is kept as close as possible to the default tickless
+ * mode provided.
+ * The systick is still used when there is no need to go in low power mode.
+ * When the system needs to enter low power mode, the tick is suppressed and a low power timer
+ * is used over that time
+ * Note that in sleep mode, the system clock is still running and the default tickless implementation
+ * using systick could have been kept.
+ * However, as at that time, it is not yet known whereas the low power mode that will be used is stop mode or
+ * sleep mode, it is easier and simpler to go with a low power timer as soon as the tick need to be
+ * suppressed.
+ */
+void vPortSetupTimerInterrupt( void )
+{
+  LpTimerInit( );
+
+  /* Calculate the constants required to configure the tick interrupt. */
+  ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+
+  /* Stop and clear the SysTick. */
+  portNVIC_SYSTICK_CTRL_REG = 0UL;
+  portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+  /* Configure SysTick to interrupt at the requested rate. */
+  portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+  portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+
+/**
+ * @brief The current implementation uses the hw_timerserver to provide a low power timer
+ *        This may be replaced by another low power timer.
+ *
+ * @param  None
+ * @retval None
+ */
+static void LpTimerInit( void )
+{
+  ( void ) HW_TS_Create(CFG_TIM_PROC_ID_ISR, &(LpTimerContext.LpTimerFreeRTOS_Id), hw_ts_SingleShot, LpTimerCb);
+
+  return;
+}
+
+/**
+ * @brief Low power timer callback
+ *
+ * @param  None
+ * @retval None
+ */
+static void LpTimerCb( void )
+{
+  /**
+   * Nothing to be done
+   */
+
+  return;
+}
+
+/**
+ * @brief  Request to start a low power timer ( running is stop mode )
+ *
+ * @param  time_to_sleep : Number of FreeRTOS ticks
+ * @retval None
+ */
+static void LpTimerStart( uint32_t time_to_sleep )
+{
+  /* Converts the number of FreeRTOS ticks into hw timer tick */
+  if(time_to_sleep <=  0x10C6)
+  {
+    /**
+     * ( time_to_sleep * 1000 * 1000 ) fit a 32bits word
+     */
+    time_to_sleep = (time_to_sleep * 1000 * 1000 );
+    time_to_sleep = time_to_sleep / ( CFG_TS_TICK_VAL * configTICK_RATE_HZ );
+  }
+  else if(time_to_sleep <= 0x418937)
+  {
+    /**
+     * ( time_to_sleep * 1000 ) fit a 32bits word
+     */
+    time_to_sleep = (time_to_sleep * 1000);
+    time_to_sleep = time_to_sleep / ( CFG_TS_TICK_VAL * configTICK_RATE_HZ );
+    if(time_to_sleep <= 0x418937)
+    {
+      /**
+       * ( time_to_sleep * 1000 ) fit a 32bits word
+       */
+      time_to_sleep = (time_to_sleep * 1000);
+    }
+    else
+    {
+      time_to_sleep = (~0); /* Max value */
+    }
+  }
+  else
+  {
+    time_to_sleep = time_to_sleep / ( CFG_TS_TICK_VAL * configTICK_RATE_HZ );
+    if(time_to_sleep <= 0x10C6)
+    {
+      /**
+       * ( time_to_sleep * 1000 * 1000 ) fit a 32bits word
+       */
+      time_to_sleep = (time_to_sleep * 1000 * 1000 );
+    }
+    else
+    {
+      time_to_sleep = (~0); /* Max value */
+    }
+  }
+
+  HW_TS_Start(LpTimerContext.LpTimerFreeRTOS_Id, time_to_sleep);
+
+  /**
+   * There might be other timers already running in the timer server that may elapse
+   * before this one.
+   * Store how long before the next event so that on wakeup, it will be possible to calculate
+   * how long the tick has been suppressed
+   */
+  LpTimerContext.LpTimeLeftOnEntry = HW_TS_RTC_ReadLeftTicksToCount( );
+
+  return;
+}
+
+/**
+ * @brief  Enter low power mode
+ *
+ * @param  None
+ * @retval None
+ */
+static void LpEnter( void )
+{
+#if ( CFG_LPM_SUPPORTED == 1)
+  UTIL_LPM_EnterLowPower();
+#endif
+  return;
+}
+
+/**
+ * @brief  Read how long the tick has been suppressed
+ *
+ * @param  None
+ * @retval The number of tick rate (FreeRTOS tick)
+ */
+static uint32_t LpGetElapsedTime( void )
+{
+  uint64_t return_value;
+
+  return_value = (configTICK_RATE_HZ) * (CFG_TS_TICK_VAL) * (uint64_t)(LpTimerContext.LpTimeLeftOnEntry - HW_TS_RTC_ReadLeftTicksToCount( ));
+  return_value = return_value / (1000 * 1000);
+
+  /**
+   * The system may have been out from another reason than the timer
+   * Stop the timer after the elapsed time is calculated other wise, HW_TS_RTC_ReadLeftTicksToCount()
+   * may return 0xFFFF ( TIMER LIST EMPTY )
+   * It does not hurt stopping a timer that exists but is not running.
+   */
+  HW_TS_Stop(LpTimerContext.LpTimerFreeRTOS_Id);
+
+  return (uint32_t)return_value;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_timerserver.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_timerserver.c
new file mode 100644
index 000000000..409d565c9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_timerserver.c
@@ -0,0 +1,893 @@
+/**
+ ******************************************************************************
+  * File Name          : hw_timerserver.c
+  * Description        : Hardware timerserver source file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "hw_conf.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef enum
+{
+  TimerID_Free,
+  TimerID_Created,
+  TimerID_Running
+}TimerIDStatus_t;
+
+typedef enum
+{
+  SSR_Read_Requested,
+  SSR_Read_Not_Requested
+}RequestReadSSR_t;
+
+typedef enum
+{
+  WakeupTimerValue_Overpassed,
+  WakeupTimerValue_LargeEnough
+}WakeupTimerLimitation_Status_t;
+
+typedef struct
+{
+  HW_TS_pTimerCb_t  pTimerCallBack;
+  uint32_t        CounterInit;
+  uint32_t        CountLeft;
+  TimerIDStatus_t     TimerIDStatus;
+  HW_TS_Mode_t   TimerMode;
+  uint32_t        TimerProcessID;
+  uint8_t         PreviousID;
+  uint8_t         NextID;
+}TimerContext_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define SSR_FORBIDDEN_VALUE   0xFFFFFFFF
+#define TIMER_LIST_EMPTY      0xFFFF
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/**
+ * START of Section TIMERSERVER_CONTEXT
+ */
+
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile TimerContext_t aTimerContext[CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER];
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint8_t CurrentRunningTimerID;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint8_t PreviousRunningTimerID;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint32_t SSRValueOnLastSetup;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile WakeupTimerLimitation_Status_t  WakeupTimerLimitation;
+
+/**
+ * END of Section TIMERSERVER_CONTEXT
+ */
+
+static RTC_HandleTypeDef *phrtc;  /**< RTC handle */
+static uint8_t  WakeupTimerDivider;
+static uint8_t  AsynchPrescalerUserConfig;
+static uint16_t SynchPrescalerUserConfig;
+static volatile uint16_t MaxWakeupTimerSetup;
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void RestartWakeupCounter(uint16_t Value);
+static uint16_t ReturnTimeElapsed(void);
+static void RescheduleTimerList(void);
+static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR);
+static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID);
+static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID);
+static uint16_t linkTimer(uint8_t TimerID);
+static uint32_t ReadRtcSsrValue(void);
+
+__weak void HW_TS_RTC_CountUpdated_AppNot(void);
+
+/* Functions Definition ------------------------------------------------------*/
+
+/**
+ * @brief  Read the RTC_SSR value
+ *         As described in the reference manual, the RTC_SSR shall be read twice to ensure
+ *         reliability of the value
+ * @param  None
+ * @retval SSR value read
+ */
+static uint32_t ReadRtcSsrValue(void)
+{
+  uint32_t first_read;
+  uint32_t second_read;
+
+  first_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+
+  second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+
+  while(first_read != second_read)
+  {
+    first_read = second_read;
+
+    second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+  }
+
+  return second_read;
+}
+
+/**
+ * @brief  Insert a Timer in the list after the Timer ID specified
+ * @param  TimerID:   The ID of the Timer
+ * @param  RefTimerID: The ID of the Timer to be linked after
+ * @retval None
+ */
+static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID)
+{
+  uint8_t next_id;
+
+  next_id = aTimerContext[RefTimerID].NextID;
+
+  if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    aTimerContext[next_id].PreviousID = TimerID;
+  }
+  aTimerContext[TimerID].NextID = next_id;
+  aTimerContext[TimerID].PreviousID = RefTimerID ;
+  aTimerContext[RefTimerID].NextID = TimerID;
+
+  return;
+}
+
+/**
+ * @brief  Insert a Timer in the list before the ID specified
+ * @param  TimerID:   The ID of the Timer
+ * @param  RefTimerID: The ID of the Timer to be linked before
+ * @retval None
+ */
+static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID)
+{
+  uint8_t previous_id;
+
+  if(RefTimerID != CurrentRunningTimerID)
+  {
+    previous_id = aTimerContext[RefTimerID].PreviousID;
+
+    aTimerContext[previous_id].NextID = TimerID;
+    aTimerContext[TimerID].NextID = RefTimerID;
+    aTimerContext[TimerID].PreviousID = previous_id ;
+    aTimerContext[RefTimerID].PreviousID = TimerID;
+  }
+  else
+  {
+    aTimerContext[TimerID].NextID = RefTimerID;
+    aTimerContext[RefTimerID].PreviousID = TimerID;
+  }
+
+  return;
+}
+
+/**
+ * @brief  Insert a Timer in the list
+ * @param  TimerID:   The ID of the Timer
+ * @retval None
+ */
+static uint16_t linkTimer(uint8_t TimerID)
+{
+  uint32_t time_left;
+  uint16_t time_elapsed;
+  uint8_t timer_id_lookup;
+  uint8_t next_id;
+
+  if(CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    /**
+     * No timer in the list
+     */
+    PreviousRunningTimerID = CurrentRunningTimerID;
+    CurrentRunningTimerID = TimerID;
+    aTimerContext[TimerID].NextID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;
+
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+    time_elapsed = 0;
+  }
+  else
+  {
+    time_elapsed = ReturnTimeElapsed();
+
+    /**
+     * update count of the timer to be linked
+     */
+    aTimerContext[TimerID].CountLeft += time_elapsed;
+    time_left = aTimerContext[TimerID].CountLeft;
+
+    /**
+     * Search for index where the new timer shall be linked
+     */
+    if(aTimerContext[CurrentRunningTimerID].CountLeft <= time_left)
+    {
+      /**
+       * Search for the ID after the first one
+       */
+      timer_id_lookup = CurrentRunningTimerID;
+      next_id = aTimerContext[timer_id_lookup].NextID;
+      while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left))
+      {
+        timer_id_lookup = aTimerContext[timer_id_lookup].NextID;
+        next_id = aTimerContext[timer_id_lookup].NextID;
+      }
+
+      /**
+       * Link after the ID
+       */
+      LinkTimerAfter(TimerID, timer_id_lookup);
+    }
+    else
+    {
+      /**
+       * Link before the first ID
+       */
+      LinkTimerBefore(TimerID, CurrentRunningTimerID);
+      PreviousRunningTimerID = CurrentRunningTimerID;
+      CurrentRunningTimerID = TimerID;
+    }
+  }
+
+  return time_elapsed;
+}
+
+/**
+ * @brief  Remove a Timer from the list
+ * @param  TimerID:   The ID of the Timer
+ * @param  RequestReadSSR: Request to read the SSR register or not
+ * @retval None
+ */
+static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR)
+{
+  uint8_t previous_id;
+  uint8_t next_id;
+
+  if(TimerID == CurrentRunningTimerID)
+  {
+    PreviousRunningTimerID = CurrentRunningTimerID;
+    CurrentRunningTimerID = aTimerContext[TimerID].NextID;
+  }
+  else
+  {
+    previous_id = aTimerContext[TimerID].PreviousID;
+    next_id = aTimerContext[TimerID].NextID;
+
+    aTimerContext[previous_id].NextID = aTimerContext[TimerID].NextID;
+    if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+    {
+      aTimerContext[next_id].PreviousID = aTimerContext[TimerID].PreviousID;
+    }
+  }
+
+  /**
+   * Timer is out of the list
+   */
+  aTimerContext[TimerID].TimerIDStatus = TimerID_Created;
+
+  if((CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (RequestReadSSR == SSR_Read_Requested))
+  {
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+  }
+
+  return;
+}
+
+/**
+ * @brief  Return the number of ticks counted by the wakeuptimer since it has been started
+ * @note  The API is reading the SSR register to get how many ticks have been counted
+ *        since the time the timer has been started
+ * @param  None
+ * @retval Time expired in Ticks
+ */
+static uint16_t ReturnTimeElapsed(void)
+{
+  uint32_t  return_value;
+  uint32_t  wrap_counter;
+
+  if(SSRValueOnLastSetup != SSR_FORBIDDEN_VALUE)
+  {
+    return_value = ReadRtcSsrValue(); /**< Read SSR register first */
+
+    if (SSRValueOnLastSetup >= return_value)
+    {
+      return_value = SSRValueOnLastSetup - return_value;
+    }
+    else
+    {
+      wrap_counter = SynchPrescalerUserConfig - return_value;
+      return_value = SSRValueOnLastSetup + wrap_counter;
+    }
+
+    /**
+     * At this stage, ReturnValue holds the number of ticks counted by SSR
+     * Need to translate in number of ticks counted by the Wakeuptimer
+     */
+    return_value = return_value*AsynchPrescalerUserConfig;
+    return_value = return_value >> WakeupTimerDivider;
+  }
+  else
+  {
+    return_value = 0;
+  }
+
+  return (uint16_t)return_value;
+}
+
+/**
+ * @brief  Set the wakeup counter
+ * @note  The API is writing the counter value so that the value is decreased by one to cope with the fact
+ *    the interrupt is generated with 1 extra clock cycle (See RefManuel)
+ *    It assumes all condition are met to be allowed to write the wakeup counter
+ * @param  Value: Value to be written in the counter
+ * @retval None
+ */
+static void RestartWakeupCounter(uint16_t Value)
+{
+  /**
+   * The wakeuptimer has been disabled in the calling function to reduce the time to poll the WUTWF
+   * FLAG when the new value will have to be written
+   *  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);
+   */
+
+  if(Value == 0)
+  {
+    SSRValueOnLastSetup = ReadRtcSsrValue();
+
+    /**
+     * Simulate that the Timer expired
+     */
+    HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
+  }
+  else
+  {
+    if((Value > 1) ||(WakeupTimerDivider != 1))
+    {
+      Value -= 1;
+    }
+
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+    /**
+     * make sure to clear the flags after checking the WUTWF.
+     * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+     * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+     * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+     * due to the autoreload feature
+     */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+    HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);   /**<  Clear pending bit in NVIC */
+
+    MODIFY_REG(RTC->WUTR, RTC_WUTR_WUT, Value);
+
+    /**
+     * Update the value here after the WUTWF polling that may take some time
+     */
+    SSRValueOnLastSetup = ReadRtcSsrValue();
+
+    __HAL_RTC_WAKEUPTIMER_ENABLE(phrtc);    /**<  Enable the Wakeup Timer */
+
+    HW_TS_RTC_CountUpdated_AppNot();
+  }
+
+  return ;
+}
+
+/**
+ * @brief  Reschedule the list of timer
+ * @note  1) Update the count left for each timer in the list
+ *    2) Setup the wakeuptimer
+ * @param  None
+ * @retval None
+ */
+static void RescheduleTimerList(void)
+{
+  uint8_t   localTimerID;
+  uint32_t  timecountleft;
+  uint16_t  wakeup_timer_value;
+  uint16_t  time_elapsed;
+
+  /**
+   * The wakeuptimer is disabled now to reduce the time to poll the WUTWF
+   * FLAG when the new value will have to be written
+   */
+  if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+  {
+    /**
+     * Wait for the flag to be back to 0 when the wakeup timer is enabled
+     */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == SET);
+  }
+  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);   /**<  Disable the Wakeup Timer */
+
+  localTimerID = CurrentRunningTimerID;
+
+  /**
+   * Calculate what will be the value to write in the wakeuptimer
+   */
+  timecountleft = aTimerContext[localTimerID].CountLeft;
+
+  /**
+   * Read how much has been counted
+   */
+  time_elapsed = ReturnTimeElapsed();
+
+  if(timecountleft < time_elapsed )
+  {
+    /**
+     * There is no tick left to count
+     */
+    wakeup_timer_value = 0;
+    WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+  }
+  else
+  {
+    if(timecountleft > (time_elapsed + MaxWakeupTimerSetup))
+    {
+      /**
+       * The number of tick left is greater than the Wakeuptimer maximum value
+       */
+      wakeup_timer_value = MaxWakeupTimerSetup;
+
+      WakeupTimerLimitation = WakeupTimerValue_Overpassed;
+    }
+    else
+    {
+      wakeup_timer_value = timecountleft - time_elapsed;
+      WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+    }
+
+  }
+
+  /**
+   * update ticks left to be counted for each timer
+   */
+  while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    if (aTimerContext[localTimerID].CountLeft < time_elapsed)
+    {
+      aTimerContext[localTimerID].CountLeft = 0;
+    }
+    else
+    {
+      aTimerContext[localTimerID].CountLeft -= time_elapsed;
+    }
+    localTimerID = aTimerContext[localTimerID].NextID;
+  }
+
+  /**
+   * Write next count
+   */
+  RestartWakeupCounter(wakeup_timer_value);
+
+  return ;
+}
+
+/* Public functions ----------------------------------------------------------*/
+
+/**
+ * For all public interface except that may need write access to the RTC, the RTC
+ * shall be unlock at the beginning and locked at the output
+ * In order to ease maintainability, the unlock is done at the top and the lock at then end
+ * in case some new implementation is coming in the future
+ */
+
+void HW_TS_RTC_Wakeup_Handler(void)
+{
+  HW_TS_pTimerCb_t ptimer_callback;
+  uint32_t timer_process_id;
+  uint8_t local_current_running_timer_id;
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  /**
+   * Disable the Wakeup Timer
+   * This may speed up a bit the processing to wait the timer to be disabled
+   * The timer is still counting 2 RTCCLK
+   */
+  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);
+
+  local_current_running_timer_id = CurrentRunningTimerID;
+
+  if(aTimerContext[local_current_running_timer_id].TimerIDStatus == TimerID_Running)
+  {
+    ptimer_callback = aTimerContext[local_current_running_timer_id].pTimerCallBack;
+    timer_process_id = aTimerContext[local_current_running_timer_id].TimerProcessID;
+
+    /**
+     * It should be good to check whether the TimeElapsed is greater or not than the tick left to be counted
+     * However, due to the inaccuracy of the reading of the time elapsed, it may return there is 1 tick
+     * to be left whereas the count is over
+     * A more secure implementation has been done with a flag to state whereas the full count has been written
+     * in the wakeuptimer or not
+     */
+    if(WakeupTimerLimitation != WakeupTimerValue_Overpassed)
+    {
+      if(aTimerContext[local_current_running_timer_id].TimerMode == hw_ts_Repeated)
+      {
+        UnlinkTimer(local_current_running_timer_id, SSR_Read_Not_Requested);
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+        __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+        HW_TS_Start(local_current_running_timer_id, aTimerContext[local_current_running_timer_id].CounterInit);
+
+        /* Disable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+      }
+      else
+      {
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+        __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+        HW_TS_Stop(local_current_running_timer_id);
+
+        /* Disable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+      }
+
+      HW_TS_RTC_Int_AppNot(timer_process_id, local_current_running_timer_id, ptimer_callback);
+    }
+    else
+    {
+      RescheduleTimerList();
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+      __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+    }
+  }
+  else
+  {
+    /**
+     * We should never end up in this case
+     * However, if due to any bug in the timer server this is the case, the mistake may not impact the user.
+     * We could just clean the interrupt flag and get out from this unexpected interrupt
+     */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+    /**
+     * make sure to clear the flags after checking the WUTWF.
+     * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+     * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+     * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+     * due to the autoreload feature
+     */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  return;
+}
+
+void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *hrtc)
+{
+  uint8_t loop;
+  uint32_t localmaxwakeuptimersetup;
+
+  /**
+   * Get RTC handler
+   */
+  phrtc = hrtc;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
+
+  /**
+   * Readout the user config
+   */
+  WakeupTimerDivider = (4 - ((uint32_t)(READ_BIT(RTC->CR, RTC_CR_WUCKSEL))));
+
+  AsynchPrescalerUserConfig = (uint8_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_A) >> (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)) + 1;
+
+  SynchPrescalerUserConfig = (uint16_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_S)) + 1;
+
+  /**
+   *  Margin is taken to avoid wrong calculation when the wrap around is there and some
+   *  application interrupts may have delayed the reading
+   */
+  localmaxwakeuptimersetup = ((((SynchPrescalerUserConfig - 1)*AsynchPrescalerUserConfig) - CFG_HW_TS_RTC_HANDLER_MAX_DELAY) >> WakeupTimerDivider);
+
+  if(localmaxwakeuptimersetup >= 0xFFFF)
+  {
+    MaxWakeupTimerSetup = 0xFFFF;
+  }
+  else
+  {
+    MaxWakeupTimerSetup = (uint16_t)localmaxwakeuptimersetup;
+  }
+
+  /**
+   * Configure EXTI module
+   */
+  LL_EXTI_EnableRisingTrig_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+  LL_EXTI_EnableIT_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+
+  if(TimerInitMode == hw_ts_InitMode_Full)
+  {
+    WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+
+    /**
+     * Initialize the timer server
+     */
+    for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++)
+    {
+      aTimerContext[loop].TimerIDStatus = TimerID_Free;
+    }
+
+    CurrentRunningTimerID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;   /**<  Set ID to non valid value */
+
+    __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);                       /**<  Disable the Wakeup Timer */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);     /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module  */
+    HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);       /**<  Clear pending bit in NVIC  */
+    __HAL_RTC_WAKEUPTIMER_ENABLE_IT(phrtc, RTC_IT_WUT);         /**<  Enable interrupt in RTC module  */
+  }
+  else
+  {
+    if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTF) != RESET)
+    {
+      /**
+       * Simulate that the Timer expired
+       */
+      HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_SetPriority(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO);   /**<  Set NVIC priority */
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+  return;
+}
+
+HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pftimeout_handler)
+{
+  HW_TS_ReturnStatus_t localreturnstatus;
+  uint8_t loop = 0;
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  while((loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[loop].TimerIDStatus != TimerID_Free))
+  {
+    loop++;
+  }
+
+  if(loop != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    aTimerContext[loop].TimerIDStatus = TimerID_Created;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+    aTimerContext[loop].TimerProcessID = TimerProcessID;
+    aTimerContext[loop].TimerMode = TimerMode;
+    aTimerContext[loop].pTimerCallBack = pftimeout_handler;
+    *pTimerId = loop;
+
+    localreturnstatus = hw_ts_Successful;
+  }
+  else
+  {
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+    localreturnstatus = hw_ts_Failed;
+  }
+
+  return(localreturnstatus);
+}
+
+void HW_TS_Delete(uint8_t timer_id)
+{
+  HW_TS_Stop(timer_id);
+
+  aTimerContext[timer_id].TimerIDStatus = TimerID_Free; /**<  release ID */
+
+  return;
+}
+
+void HW_TS_Stop(uint8_t timer_id)
+{
+  uint8_t localcurrentrunningtimerid;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);    /**<  Disable NVIC */
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
+  {
+    UnlinkTimer(timer_id, SSR_Read_Requested);
+    localcurrentrunningtimerid = CurrentRunningTimerID;
+
+    if(localcurrentrunningtimerid == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+    {
+      /**
+       * List is empty
+       */
+
+      /**
+       * Disable the timer
+       */
+      if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+      {
+        /**
+         * Wait for the flag to be back to 0 when the wakeup timer is enabled
+         */
+        while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == SET);
+      }
+      __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);   /**<  Disable the Wakeup Timer */
+
+      while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+      /**
+       * make sure to clear the flags after checking the WUTWF.
+       * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+       * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+       * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+       * due to the autoreload feature
+       */
+      __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+      __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+      HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);   /**<  Clear pending bit in NVIC */
+    }
+    else if(PreviousRunningTimerID != localcurrentrunningtimerid)
+    {
+      RescheduleTimerList();
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+  return;
+}
+
+void HW_TS_Start(uint8_t timer_id, uint32_t timeout_ticks)
+{
+  uint16_t time_elapsed;
+  uint8_t localcurrentrunningtimerid;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+  if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
+  {
+    HW_TS_Stop( timer_id );
+  }
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);    /**<  Disable NVIC */
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  aTimerContext[timer_id].TimerIDStatus = TimerID_Running;
+
+  aTimerContext[timer_id].CountLeft = timeout_ticks;
+  aTimerContext[timer_id].CounterInit = timeout_ticks;
+
+  time_elapsed =  linkTimer(timer_id);
+
+  localcurrentrunningtimerid = CurrentRunningTimerID;
+
+  if(PreviousRunningTimerID != localcurrentrunningtimerid)
+  {
+    RescheduleTimerList();
+  }
+  else
+  {
+    aTimerContext[timer_id].CountLeft -= time_elapsed;
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+  return;
+}
+
+uint16_t HW_TS_RTC_ReadLeftTicksToCount(void)
+{
+  uint32_t primask_bit;
+  uint16_t return_value, auro_reload_value, elapsed_time_value;
+
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();                /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+
+  if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+  {
+    auro_reload_value = (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT));
+
+    elapsed_time_value = ReturnTimeElapsed();
+
+    if(auro_reload_value > elapsed_time_value)
+    {
+      return_value = auro_reload_value - elapsed_time_value;
+    }
+    else
+    {
+      return_value = 0;
+    }
+  }
+  else
+  {
+    return_value = TIMER_LIST_EMPTY;
+  }
+
+  __set_PRIMASK(primask_bit);     /**< Restore PRIMASK bit*/
+
+  return (return_value);
+}
+
+__weak void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack)
+{
+  pTimerCallBack();
+
+  return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_uart.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_uart.c
new file mode 100644
index 000000000..9a553610d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_uart.c
@@ -0,0 +1,318 @@
+/**
+ ******************************************************************************
+  * File Name          : Src/hw_uart.c
+  * Description        : HW UART source file for STM32WPAN Middleware.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "hw_conf.h"
+#if (CFG_HW_LPUART1_ENABLED == 1)
+extern UART_HandleTypeDef hlpuart1;
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+extern UART_HandleTypeDef huart1;
+#endif
+
+/* Macros --------------------------------------------------------------------*/
+#define HW_UART_RX_IT(__HANDLE__, __USART_BASE__)                                                   \
+        do{                                                                                         \
+            HW_##__HANDLE__##RxCb = cb;                                                             \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            HAL_UART_Receive_IT(&(__HANDLE__), p_data, size);                                       \
+        } while(0)
+
+#define HW_UART_TX_IT(__HANDLE__, __USART_BASE__)                                                   \
+        do{                                                                                         \
+            HW_##__HANDLE__##TxCb = cb;                                                             \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            HAL_UART_Transmit_IT(&(__HANDLE__), p_data, size);                                      \
+        } while(0)
+
+#define HW_UART_TX(__HANDLE__, __USART_BASE__)                                                      \
+        do{                                                                                         \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            hal_status = HAL_UART_Transmit(&(__HANDLE__), p_data, size, timeout);                   \
+        } while(0)
+
+/* Variables -----------------------------------------------------------------*/
+#if (CFG_HW_USART1_ENABLED == 1)
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+    DMA_HandleTypeDef HW_hdma_huart1_tx ={0};
+#endif
+    void (*HW_huart1RxCb)(void);
+    void (*HW_huart1TxCb)(void);
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+    DMA_HandleTypeDef HW_hdma_hlpuart1_tx ={0};
+#endif
+    void (*HW_hlpuart1RxCb)(void);
+    void (*HW_hlpuart1TxCb)(void);
+#endif
+
+void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_RX_IT(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_RX_IT(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  void (*cb)(void))
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_TX_IT(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_TX_IT(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout)
+{
+    HAL_StatusTypeDef hal_status = HAL_OK;
+    hw_status_t hw_status = hw_uart_ok;
+
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_TX(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_TX(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    switch (hal_status)
+    {
+        case HAL_OK:
+            hw_status = hw_uart_ok;
+            break;
+
+        case HAL_ERROR:
+            hw_status = hw_uart_error;
+            break;
+
+        case HAL_BUSY:
+            hw_status = hw_uart_busy;
+            break;
+
+        case HAL_TIMEOUT:
+            hw_status = hw_uart_to;
+            break;
+
+        default:
+            break;
+    }
+
+    return hw_status;
+}
+
+hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+{
+    HAL_StatusTypeDef hal_status = HAL_OK;
+    hw_status_t hw_status = hw_uart_ok;
+
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_huart1TxCb = cb;
+            huart1.Instance = USART1;
+            hal_status = HAL_UART_Transmit_DMA(&huart1, p_data, size);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_hlpuart1TxCb = cb;
+            hlpuart1.Instance = LPUART1;
+            hal_status = HAL_UART_Transmit_DMA(&hlpuart1, p_data, size);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    switch (hal_status)
+    {
+        case HAL_OK:
+            hw_status = hw_uart_ok;
+            break;
+
+        case HAL_ERROR:
+            hw_status = hw_uart_error;
+            break;
+
+        case HAL_BUSY:
+            hw_status = hw_uart_busy;
+            break;
+
+        case HAL_TIMEOUT:
+            hw_status = hw_uart_to;
+            break;
+
+        default:
+            break;
+    }
+
+    return hw_status;
+}
+
+void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HAL_UART_IRQHandler(&huart1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HAL_UART_IRQHandler(&hlpuart1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+        case hw_uart1:
+            HAL_DMA_IRQHandler(huart1.hdmatx);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+        case hw_lpuart1:
+            HAL_DMA_IRQHandler(hlpuart1.hdmatx);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+    switch ((uint32_t)huart->Instance)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case (uint32_t)USART1:
+            if(HW_huart1RxCb)
+            {
+                HW_huart1RxCb();
+            }
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case (uint32_t)LPUART1:
+            if(HW_hlpuart1RxCb)
+            {
+                HW_hlpuart1RxCb();
+            }
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+    switch ((uint32_t)huart->Instance)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case (uint32_t)USART1:
+            if(HW_huart1TxCb)
+            {
+                HW_huart1TxCb();
+            }
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case (uint32_t)LPUART1:
+            if(HW_hlpuart1TxCb)
+            {
+                HW_hlpuart1TxCb();
+            }
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/main.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/main.c
new file mode 100644
index 000000000..96c27a0c1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/main.c
@@ -0,0 +1,723 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    main.c
+ * @author  MCD Application Team
+ * @brief   BLE application with BLE core
+ *
+  @verbatim
+  ==============================================================================
+                    ##### IMPORTANT NOTE #####
+  ==============================================================================
+
+  This application requests having the stm32wb5x_BLE_Stack_fw.bin binary
+  flashed on the Wireless Coprocessor.
+  If it is not the case, you need to use STM32CubeProgrammer to load the appropriate
+  binary.
+
+  All available binaries are located under following directory:
+  /Projects/STM32_Copro_Wireless_Binaries
+
+  Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+  Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the
+  detailed procedure to change the Wireless Coprocessor binary.
+
+  @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+ * All rights reserved.
    
+ *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+#include "app_entry.h"
+#include "app_common.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "stm32_lpm.h"
+#include "dbg_trace.h"
+#include "hw_conf.h"
+#include "otp.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef hlpuart1;
+UART_HandleTypeDef huart1;
+DMA_HandleTypeDef hdma_lpuart1_tx;
+DMA_HandleTypeDef hdma_usart1_tx;
+
+RTC_HandleTypeDef hrtc;
+
+osThreadId_t defaultTaskHandle;
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+void MX_LPUART1_UART_Init(void);
+void MX_USART1_UART_Init(void);
+static void MX_RF_Init(void);
+static void MX_RTC_Init(void);
+void StartDefaultTask(void *argument);
+
+/* USER CODE BEGIN PFP */
+void PeriphClock_Config(void);
+static void Reset_Device( void );
+static void Reset_IPCC( void );
+static void Reset_BackupDomain( void );
+static void Init_Exti( void );
+static void Config_HSE(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+  
+  
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* Initialize the OS */
+
+  /* USER CODE BEGIN Init */
+  Reset_Device();
+  Config_HSE();
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  PeriphClock_Config();
+  Init_Exti(); /**< Configure the system Power Mode */
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_RF_Init();
+  MX_RTC_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  osKernelInitialize(); // Initialize CMSIS-RTOS
+
+  /* USER CODE BEGIN RTOS_MUTEX */
+  /* add mutexes, ... */
+  /* USER CODE END RTOS_MUTEX */
+
+  /* USER CODE BEGIN RTOS_SEMAPHORES */
+  /* add semaphores, ... */
+  /* USER CODE END RTOS_SEMAPHORES */
+
+  /* USER CODE BEGIN RTOS_TIMERS */
+  /* start timers, add new ones, ... */
+  /* USER CODE END RTOS_TIMERS */
+
+  /* USER CODE BEGIN RTOS_QUEUES */
+  /* add queues, ... */
+  /* USER CODE END RTOS_QUEUES */
+
+  /* Create the thread(s) */
+  /* definition and creation of defaultTask */
+  const osThreadAttr_t defaultTask_attributes = {
+    .name = "defaultTask",
+    .priority = (osPriority_t) osPriorityNormal,
+    .stack_size = 256
+  };
+  defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);
+
+  /* USER CODE BEGIN RTOS_THREADS */
+  /* add threads, ... */
+  /* USER CODE END RTOS_THREADS */
+
+  /* Init code for STM32_WPAN */
+  APPE_Init();
+
+  /* Start scheduler */
+  osKernelStart();
+
+  /* We should never get here as control is now taken by the scheduler */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure LSE Drive Capability 
+  */
+  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE
+                              |RCC_OSCILLATORTYPE_LSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RFWAKEUP
+                              |RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1
+                              |RCC_PERIPHCLK_LPUART1;
+  PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+  PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* USER CODE BEGIN Smps */
+
+#if (CFG_USE_SMPS != 0)
+  /**
+   *  Configure and enable SMPS
+   *
+   *  The SMPS configuration is not yet supported by CubeMx
+   */
+  LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
+  LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
+  LL_PWR_SMPS_Enable();
+#endif
+
+  /* USER CODE END Smps */
+
+
+}
+
+/**
+  * @brief LPUART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+void MX_LPUART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN LPUART1_Init 0 */
+
+  /* USER CODE END LPUART1_Init 0 */
+
+  /* USER CODE BEGIN LPUART1_Init 1 */
+
+  /* USER CODE END LPUART1_Init 1 */
+  hlpuart1.Instance = LPUART1;
+  hlpuart1.Init.BaudRate = 115200;
+  hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
+  hlpuart1.Init.StopBits = UART_STOPBITS_1;
+  hlpuart1.Init.Parity = UART_PARITY_NONE;
+  hlpuart1.Init.Mode = UART_MODE_TX_RX;
+  hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  hlpuart1.FifoMode = UART_FIFOMODE_DISABLE;
+  if (HAL_UART_Init(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN LPUART1_Init 2 */
+
+  /* USER CODE END LPUART1_Init 2 */
+
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_8;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+  * @brief RF Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RF_Init(void)
+{
+
+  /* USER CODE BEGIN RF_Init 0 */
+
+  /* USER CODE END RF_Init 0 */
+
+  /* USER CODE BEGIN RF_Init 1 */
+
+  /* USER CODE END RF_Init 1 */
+  /* USER CODE BEGIN RF_Init 2 */
+
+  /* USER CODE END RF_Init 2 */
+
+}
+
+/**
+  * @brief RTC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RTC_Init(void)
+{
+
+  /* USER CODE BEGIN RTC_Init 0 */
+
+  /* USER CODE END RTC_Init 0 */
+
+  /* USER CODE BEGIN RTC_Init 1 */
+
+  /* USER CODE END RTC_Init 1 */
+  /** Initialize RTC Only 
+  */
+  hrtc.Instance = RTC;
+  hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
+  hrtc.Init.AsynchPrediv = CFG_RTC_ASYNCH_PRESCALER;
+  hrtc.Init.SynchPrediv = CFG_RTC_SYNCH_PRESCALER;
+  hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
+  hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+  hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+  if (HAL_RTC_Init(&hrtc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN RTC_Init 2 */
+  /* Disable RTC registers write protection */
+  LL_RTC_DisableWriteProtection(RTC);
+
+  LL_RTC_WAKEUP_SetClock(RTC, CFG_RTC_WUCKSEL_DIVIDER);
+
+  /* Enable RTC registers write protection */
+  LL_RTC_EnableWriteProtection(RTC);
+  /* USER CODE END RTC_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
+  __HAL_RCC_DMA2_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
+  /* DMA2_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA2_Channel4_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(DMA2_Channel4_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+void PeriphClock_Config(void)
+{
+  #if (CFG_USB_INTERFACE_ENABLE != 0)
+	RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
+	RCC_CRSInitTypeDef RCC_CRSInitStruct = { 0 };
+
+	/**
+   * This prevents the CPU2 to disable the HSI48 oscillator when
+   * it does not use anymore the RNG IP
+   */
+  LL_HSEM_1StepLock( HSEM, 5 );
+
+  LL_RCC_HSI48_Enable();
+
+	while(!LL_RCC_HSI48_IsReady());
+
+	/* Select HSI48 as USB clock source */
+	PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+	PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+	HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+	/*Configure the clock recovery system (CRS)**********************************/
+
+	/* Enable CRS Clock */
+	__HAL_RCC_CRS_CLK_ENABLE();
+
+	/* Default Synchro Signal division factor (not divided) */
+	RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+
+	/* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+	RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+
+	/* HSI48 is synchronized with USB SOF at 1KHz rate */
+	RCC_CRSInitStruct.ReloadValue = RCC_CRS_RELOADVALUE_DEFAULT;
+	RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+
+	RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+
+	/* Set the TRIM[5:0] to the default value*/
+	RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+
+	/* Start automatic synchronization */
+	HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+#endif
+
+	return;
+}
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+
+static void Config_HSE(void)
+{
+    OTP_ID0_t * p_otp;
+
+  /**
+   * Read HSE_Tuning from OTP
+   */
+  p_otp = (OTP_ID0_t *) OTP_Read(0);
+  if (p_otp)
+  {
+    LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
+  }
+
+  return;
+}  
+
+
+static void Reset_Device( void )
+{
+#if ( CFG_HW_RESET_BY_FW == 1 )
+	Reset_BackupDomain();
+
+	Reset_IPCC();
+#endif
+
+	return;
+}
+
+static void Reset_IPCC( void )
+{
+	LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
+
+	LL_C1_IPCC_ClearFlag_CHx(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_ClearFlag_CHx(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C1_IPCC_DisableTransmitChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_DisableTransmitChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C1_IPCC_DisableReceiveChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_DisableReceiveChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	return;
+}
+
+static void Reset_BackupDomain( void )
+{
+	if ((LL_RCC_IsActiveFlag_PINRST() != FALSE) && (LL_RCC_IsActiveFlag_SFTRST() == FALSE))
+	{
+		HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+		/**
+		 *  Write twice the value to flush the APB-AHB bridge
+		 *  This bit shall be written in the register before writing the next one
+		 */
+		HAL_PWR_EnableBkUpAccess();
+
+		__HAL_RCC_BACKUPRESET_FORCE();
+		__HAL_RCC_BACKUPRESET_RELEASE();
+	}
+
+	return;
+}
+
+static void Init_Exti( void )
+{
+  /**< Disable all wakeup interrupt on CPU1  except IPCC(36), HSEM(38) */
+  LL_EXTI_DisableIT_0_31(~0);
+  LL_EXTI_DisableIT_32_63( (~0) & (~(LL_EXTI_LINE_36 | LL_EXTI_LINE_38)) );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += HAL_GetTickFreq();
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+  {
+    /************************************************************************************
+     * ENTER SLEEP MODE
+     ***********************************************************************************/
+    LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+    /**
+     * This option is used to ensure that store operations are completed
+     */
+  #if defined ( __CC_ARM)
+    __force_stores();
+  #endif
+
+    __WFI( );
+  }
+}
+
+/* USER CODE END 4 */
+
+/* USER CODE BEGIN Header_StartDefaultTask */
+/**
+  * @brief  Function implementing the defaultTask thread.
+  * @param  argument: Not used 
+  * @retval None
+  */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void *argument)
+{
+
+  /* USER CODE BEGIN 5 */
+  /* Infinite loop */
+  for(;;)
+  {
+    osThreadFlagsWait(1,osFlagsWaitAll,osWaitForever);
+  }
+  /* USER CODE END 5 */ 
+}
+
+/**
+  * @brief  Period elapsed callback in non blocking mode
+  * @note   This function is called  when TIM17 interrupt took place, inside
+  * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+  * a global variable "uwTick" used as application time base.
+  * @param  htim : TIM handle
+  * @retval None
+  */
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* USER CODE BEGIN Callback 0 */
+
+  /* USER CODE END Callback 0 */
+  if (htim->Instance == TIM17) {
+    HAL_IncTick();
+  }
+  /* USER CODE BEGIN Callback 1 */
+
+  /* USER CODE END Callback 1 */
+}
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32_lpm_if.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32_lpm_if.c
new file mode 100644
index 000000000..68153652a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32_lpm_if.c
@@ -0,0 +1,278 @@
+/* USER CODE BEGIN Header */
+/**
+ ***************************************************************************************
+  * File Name          : stm32_lpm_if.c
+  * Description        : Low layer function to enter/exit low power modes (stop, sleep).
+ ***************************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+  
+/* Includes ------------------------------------------------------------------*/  
+#include "stm32_lpm_if.h"
+#include "stm32_lpm.h"
+#include "app_conf.h"
+/* USER CODE BEGIN include */
+
+/* USER CODE END include */
+
+/* Exported variables --------------------------------------------------------*/
+const struct UTIL_LPM_Driver_s UTIL_PowerDriver = 
+{
+  PWR_EnterSleepMode,
+  PWR_ExitSleepMode,
+  
+  PWR_EnterStopMode,
+  PWR_ExitStopMode, 
+  
+  PWR_EnterOffMode,
+  PWR_ExitOffMode,
+};
+
+/* Private function prototypes -----------------------------------------------*/
+static void Switch_On_HSI( void );
+/* USER CODE BEGIN Private_Function_Prototypes */
+
+/* USER CODE END Private_Function_Prototypes */
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN Private_Typedef */
+
+/* USER CODE END Private_Typedef */
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Private_Define */
+
+/* USER CODE END Private_Define */
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Private_Macro */
+
+/* USER CODE END Private_Macro */
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN Private_Variables */
+
+/* USER CODE END Private_Variables */
+
+/* Functions Definition ------------------------------------------------------*/
+/**
+  * @brief Enters Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_EnterOffMode( void )
+{
+/* USER CODE BEGIN PWR_EnterOffMode */
+  /************************************************************************************
+   * ENTER OFF MODE
+   ***********************************************************************************/
+  /*
+   * There is no risk to clear all the WUF here because in the current implementation, this API is called
+   * in critical section. If an interrupt occurs while in that critical section before that point,
+   * the flag is set and will be cleared here but the system will not enter Off Mode
+   * because an interrupt is pending in the NVIC. The ISR will be executed when moving out
+   * of this critical section
+   */
+  LL_PWR_ClearFlag_WU( );
+
+  LL_PWR_SetPowerMode( LL_PWR_MODE_STANDBY );
+
+  LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores( );
+#endif
+
+  __WFI( );
+/* USER CODE END PWR_EnterOffMode */
+}
+
+/**
+  * @brief Exits Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_ExitOffMode( void )
+{
+/* USER CODE BEGIN PWR_ExitOffMode */
+
+/* USER CODE END PWR_ExitOffMode */
+}
+
+/**
+  * @brief Enters Low Power Stop Mode
+  * @note ARM exists the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterStopMode( void )
+{
+/* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * This function is called from CRITICAL SECTION
+   */
+  while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
+
+  if ( ! LL_HSEM_1StepLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID ) )
+  {
+    if( LL_PWR_IsActiveFlag_C2DS( ) )
+    {
+      /* Release ENTRY_STOP_MODE semaphore */
+      LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
+
+      /**
+       * The switch on HSI before entering Stop Mode is required on Cut2.0
+       * It is useless from Cut2.1
+       */
+      Switch_On_HSI( );
+    }
+  }
+  else
+  {
+    /**
+     * The switch on HSI before entering Stop Mode is required on Cut2.0
+     * It is useless from Cut2.1
+     */
+    Switch_On_HSI( );
+  }
+
+  /* Release RCC semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  /************************************************************************************
+   * ENTER STOP MODE
+   ***********************************************************************************/
+  LL_PWR_SetPowerMode( LL_PWR_MODE_STOP2 );
+
+  LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores( );
+#endif
+
+  __WFI();
+/* USER CODE END PWR_EnterStopMode */
+}
+
+/**
+  * @brief Exits Low Power Stop Mode
+  * @note Enable the pll at 32MHz
+  * @param none
+  * @retval none
+  */
+void PWR_ExitStopMode( void )
+{
+/* USER CODE BEGIN PWR_ExitStopMode */
+  /**
+   * This function is called from CRITICAL SECTION
+   */
+
+  /* Release ENTRY_STOP_MODE semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
+
+  while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
+
+  if(LL_RCC_GetSysClkSource( ) == LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+    LL_RCC_HSE_Enable( );
+    while(!LL_RCC_HSE_IsReady( ));
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
+    while (LL_RCC_GetSysClkSource( ) != LL_RCC_SYS_CLKSOURCE_STATUS_HSE);
+  }
+  else
+  {
+    /**
+     * As long as the current application is fine with HSE as system clock source,
+     * there is nothing to do here
+     */
+  }
+
+  /* Release RCC semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+/* USER CODE END PWR_ExitStopMode */
+}
+
+/**
+  * @brief Enters Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterSleepMode( void )
+{
+/* USER CODE BEGIN PWR_EnterSleepMode */
+  /**
+   * When tickless FreeRTOS is used, the systick is fully managed in the file freertos_port.c
+   * It shall not be either started or stop in this API
+   */
+
+  /************************************************************************************
+   * ENTER SLEEP MODE
+   ***********************************************************************************/
+  LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+
+  __WFI( );
+/* USER CODE END PWR_EnterSleepMode */
+}
+
+/**
+  * @brief Exits Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_ExitSleepMode( void )
+{
+/* USER CODE BEGIN PWR_ExitSleepMode */
+  /**
+   * When tickless FreeRTOS is used, the systick is fully managed in the file freertos_port.c
+   * It shall not be either started or stop in this API
+   */
+/* USER CODE END PWR_ExitSleepMode */
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+  * @brief Switch the system clock on HSI
+  * @param none
+  * @retval none
+  */
+static void Switch_On_HSI( void )
+{
+  LL_RCC_HSI_Enable( );
+  while(!LL_RCC_HSI_IsReady( ));
+  LL_RCC_SetSysClkSource( LL_RCC_SYS_CLKSOURCE_HSI );
+  LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSI);
+  while (LL_RCC_GetSysClkSource( ) != LL_RCC_SYS_CLKSOURCE_STATUS_HSI);
+}
+
+/* USER CODE BEGIN Private_Functions */
+
+/* USER CODE END Private_Functions */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..207c26eb8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,334 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32wbxx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_lpuart1_tx;
+
+extern DMA_HandleTypeDef hdma_usart1_tx;
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_HSEM_CLK_ENABLE();
+
+  /* System interrupt init*/
+  /* PendSV_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  HAL_NVIC_SetPriority(IPCC_C1_RX_IRQn , 6, 0);
+  HAL_NVIC_SetPriority(IPCC_C1_TX_IRQn , 6, 0);
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  HAL_DMA_MuxSyncConfigTypeDef pSyncConfig;
+  if(huart->Instance==LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspInit 0 */
+
+  /* USER CODE END LPUART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_LPUART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**LPUART1 GPIO Configuration    
+    PA2     ------> LPUART1_TX
+    PA3     ------> LPUART1_RX
+    PA6     ------> LPUART1_CTS 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* LPUART1 DMA Init */
+    /* LPUART1_TX Init */
+    hdma_lpuart1_tx.Instance = DMA1_Channel4;
+    hdma_lpuart1_tx.Init.Request = DMA_REQUEST_LPUART1_TX;
+    hdma_lpuart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_lpuart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_lpuart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_lpuart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_lpuart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_lpuart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_lpuart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_lpuart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    pSyncConfig.SyncSignalID = HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT;
+    pSyncConfig.SyncPolarity = HAL_DMAMUX_SYNC_NO_EVENT;
+    pSyncConfig.SyncEnable = DISABLE;
+    pSyncConfig.EventEnable = DISABLE;
+    pSyncConfig.RequestNumber = 1;
+    if (HAL_DMAEx_ConfigMuxSync(&hdma_lpuart1_tx, &pSyncConfig) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmatx,hdma_lpuart1_tx);
+
+    /* LPUART1 interrupt Init */
+    HAL_NVIC_SetPriority(LPUART1_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(LPUART1_IRQn);
+  /* USER CODE BEGIN LPUART1_MspInit 1 */
+
+  /* USER CODE END LPUART1_MspInit 1 */
+  }
+  else if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspInit 0 */
+
+  /* USER CODE END USART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**USART1 GPIO Configuration    
+    PA11     ------> USART1_CTS
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_11;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* USART1 DMA Init */
+    /* USART1_TX Init */
+    hdma_usart1_tx.Instance = DMA2_Channel4;
+    hdma_usart1_tx.Init.Request = DMA_REQUEST_USART1_TX;
+    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx);
+
+    /* USART1 interrupt Init */
+    HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspInit 1 */
+
+  /* USER CODE END USART1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspDeInit 0 */
+
+  /* USER CODE END LPUART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_LPUART1_CLK_DISABLE();
+  
+    /**LPUART1 GPIO Configuration    
+    PA2     ------> LPUART1_TX
+    PA3     ------> LPUART1_RX
+    PA6     ------> LPUART1_CTS 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_6);
+
+    /* LPUART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmatx);
+
+    /* LPUART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(LPUART1_IRQn);
+  /* USER CODE BEGIN LPUART1_MspDeInit 1 */
+
+  /* USER CODE END LPUART1_MspDeInit 1 */
+  }
+  else if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+  /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+  
+    /**USART1 GPIO Configuration    
+    PA11     ------> USART1_CTS
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11);
+
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
+
+    /* USART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmatx);
+
+    /* USART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+  /* USER CODE END USART1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspInit 0 */
+  HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+  /**
+  *  Write twice the value to flush the APB-AHB bridge
+  *  This bit shall be written in the register before writing the next one
+  */
+  HAL_PWR_EnableBkUpAccess();
+
+  __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); /**< Select LSI as RTC Input */
+  /* USER CODE END RTC_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_RTC_ENABLE();
+  /* USER CODE BEGIN RTC_MspInit 1 */
+  HAL_RTCEx_EnableBypassShadow(hrtc);
+  /* USER CODE END RTC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspDeInit 0 */
+
+  /* USER CODE END RTC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RTC_DISABLE();
+  /* USER CODE BEGIN RTC_MspDeInit 1 */
+
+  /* USER CODE END RTC_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32wbxx_hal_timebase_tim.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32wbxx_hal_timebase_tim.c
new file mode 100644
index 000000000..2db479625
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32wbxx_hal_timebase_tim.c
@@ -0,0 +1,152 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_timebase_tim.c
+  * @author  MCD Application Team
+  * @brief   HAL time base based on the hardware TIM.
+  *
+  *          This file overrides the native HAL time base functions (defined as weak)
+  *          the TIM time base:
+  *           + Intializes the TIM peripheral to generate a Period elapsed Event each 1ms
+  *           + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
+  *
+ @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    This file must be copied to the application folder and modified as follows:
+    (#) Rename it to 'stm32g0xx_hal_timebase_tim.c'
+    (#) Add this file and the TIM HAL driver files to your project and make sure
+       HAL_TIM_MODULE_ENABLED is defined in stm32l4xx_hal_conf.h
+
+    [..]
+    (@) The application needs to ensure that the time base is always set to 1 millisecond
+       to have correct HAL operation.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+#include "stm32wbxx_hal_tim.h"
+ 
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+TIM_HandleTypeDef        htim17; 
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  This function configures the TIM17 as a time base source. 
+  *         The time source is configured  to have 1ms time base with a dedicated 
+  *         Tick interrupt priority. 
+  * @note   This function is called  automatically at the beginning of program after
+  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). 
+  * @param  TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  RCC_ClkInitTypeDef    clkconfig;
+  uint32_t              uwTimclock = 0;
+  uint32_t              uwPrescalerValue = 0;
+  uint32_t              pFLatency;
+  
+  /*Configure the TIM17 IRQ priority */
+  HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM17_IRQn, TickPriority ,0); 
+  
+  /* Enable the TIM17 global Interrupt */
+  HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM17_IRQn); 
+  
+  /* Enable TIM17 clock */
+  __HAL_RCC_TIM17_CLK_ENABLE();
+  
+  /* Get clock configuration */
+  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
+  
+  /* Compute TIM17 clock */
+  uwTimclock = HAL_RCC_GetPCLK2Freq();
+   
+  /* Compute the prescaler value to have TIM17 counter clock equal to 1MHz */
+  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1);
+  
+  /* Initialize TIM17 */
+  htim17.Instance = TIM17;
+  
+  /* Initialize TIMx peripheral as follow:
+  + Period = [(TIM17CLK/1000) - 1]. to have a (1/1000) s time base.
+  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+  + ClockDivision = 0
+  + Counter direction = Up
+  */
+  htim17.Init.Period = (1000000 / 1000) - 1;
+  htim17.Init.Prescaler = uwPrescalerValue;
+  htim17.Init.ClockDivision = 0;
+  htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
+  if(HAL_TIM_Base_Init(&htim17) == HAL_OK)
+  {
+    /* Start the TIM time Base generation in interrupt mode */
+    return HAL_TIM_Base_Start_IT(&htim17);
+  }
+  
+  /* Return function status */
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Suspend Tick increment.
+  * @note   Disable the tick increment by disabling TIM17 update interrupt.
+  * @param  None
+  * @retval None
+  */
+void HAL_SuspendTick(void)
+{
+  /* Disable TIM17 update Interrupt */
+  __HAL_TIM_DISABLE_IT(&htim17, TIM_IT_UPDATE);                                                  
+}
+
+/**
+  * @brief  Resume Tick increment.
+  * @note   Enable the tick increment by Enabling TIM17 update interrupt.
+  * @param  None
+  * @retval None
+  */
+void HAL_ResumeTick(void)
+{
+  /* Enable TIM17 Update interrupt */
+  __HAL_TIM_ENABLE_IT(&htim17, TIM_IT_UPDATE);
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..33043d814
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32wbxx_it.c
@@ -0,0 +1,296 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+#include "cmsis_os.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_lpuart1_tx;
+extern DMA_HandleTypeDef hdma_usart1_tx;
+extern UART_HandleTypeDef hlpuart1;
+extern UART_HandleTypeDef huart1;
+extern TIM_HandleTypeDef htim17;
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles DMA1 channel4 global interrupt.
+  */
+void DMA1_Channel4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_lpuart1_tx);
+  /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel4_IRQn 1 */
+}
+
+/**
+  * @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt.
+  */
+void TIM1_TRG_COM_TIM17_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */
+
+  /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */
+  HAL_TIM_IRQHandler(&htim17);
+  /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */
+
+  /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+
+  /* USER CODE END USART1_IRQn 0 */
+  HAL_UART_IRQHandler(&huart1);
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles LPUART1 global interrupt.
+  */
+void LPUART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN LPUART1_IRQn 0 */
+
+  /* USER CODE END LPUART1_IRQn 0 */
+  HAL_UART_IRQHandler(&hlpuart1);
+  /* USER CODE BEGIN LPUART1_IRQn 1 */
+
+  /* USER CODE END LPUART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA2 channel4 global interrupt.
+  */
+void DMA2_Channel4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2_Channel4_IRQn 0 */
+
+  /* USER CODE END DMA2_Channel4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart1_tx);
+  /* USER CODE BEGIN DMA2_Channel4_IRQn 1 */
+
+  /* USER CODE END DMA2_Channel4_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW1_EXTI_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW2_EXTI_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW2_PIN);
+}
+
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW3_EXTI_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW3_PIN);
+}
+
+void RTC_WKUP_IRQHandler(void)
+{
+  HW_TS_RTC_Wakeup_Handler();
+}
+
+void IPCC_C1_TX_IRQHandler(void)
+{
+  HW_IPCC_Tx_Handler();
+
+  return;
+}
+
+void IPCC_C1_RX_IRQHandler(void)
+{
+  HW_IPCC_Rx_Handler();
+  return;
+}
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..156ed20d3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                        4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/BLE_HeartRateFreeRTOS.ewd b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/BLE_HeartRateFreeRTOS.ewd
new file mode 100644
index 000000000..fd52e73ef
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/BLE_HeartRateFreeRTOS.ewd
@@ -0,0 +1,1419 @@
+
+
+    3
+    
+        BLE_HeartRateFreeRTOS
+        
+            ARM
+        
+        0
+        
+            C-SPY
+            2
+            
+                29
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            ARMSIM_ID
+            2
+            
+                1
+                1
+                0
+                
+                
+                
+                
+            
+        
+        
+            CADI_ID
+            2
+            
+                0
+                1
+                0
+                
+                
+                
+                
+                
+            
+        
+        
+            CMSISDAP_ID
+            2
+            
+                4
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            GDBSERVER_ID
+            2
+            
+                0
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            IJET_ID
+            2
+            
+                8
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            JLINK_ID
+            2
+            
+                16
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            LMIFTDI_ID
+            2
+            
+                2
+                1
+                0
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            PEMICRO_ID
+            2
+            
+                3
+                1
+                0
+                
+                
+                
+                
+            
+        
+        
+            STLINK_ID
+            2
+            
+                4
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            THIRDPARTY_ID
+            2
+            
+                0
+                1
+                0
+                
+                
+                
+                
+            
+        
+        
+            TIFET_ID
+            2
+            
+                1
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            XDS100_ID
+            2
+            
+                6
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            
+                $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+                0
+            
+            
+                $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+                1
+            
+            
+                $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+                0
+            
+            
+                $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+                0
+            
+            
+                $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+                0
+            
+        
+    
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/BLE_HeartRateFreeRTOS.ewp b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/BLE_HeartRateFreeRTOS.ewp
new file mode 100644
index 000000000..3af83b394
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/BLE_HeartRateFreeRTOS.ewp
@@ -0,0 +1,1339 @@
+
+
+    3
+    
+        BLE_HeartRateFreeRTOS
+        
+            ARM
+        
+        0
+        
+            General
+            3
+            
+                30
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            ICCARM
+            2
+            
+                34
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            AARM
+            2
+            
+                10
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            OBJCOPY
+            0
+            
+                1
+                1
+                0
+                
+                
+                
+                
+                
+            
+        
+        
+            CUSTOM
+            3
+            
+                
+                
+                0
+            
+        
+        
+            BICOMP
+            0
+            
+        
+        
+            BUILDACTION
+            1
+            
+                
+                
+            
+        
+        
+            ILINK
+            0
+            
+                20
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            IARCHIVE
+            0
+            
+                0
+                1
+                0
+                
+                
+                
+            
+        
+        
+            BILINK
+            0
+            
+        
+    
+    
+        Application
+        
+            Core
+            
+                $PROJ_DIR$\..\Core\Src\app_entry.c
+            
+            
+                $PROJ_DIR$\..\Core\Src\app_debug.c
+            
+            
+                $PROJ_DIR$\..\Core\Src\freertos_port.c
+            
+            
+                $PROJ_DIR$\..\Core\Src\hw_timerserver.c
+            
+            
+                $PROJ_DIR$\..\Core\Src\hw_uart.c
+            
+            
+                $PROJ_DIR$\..\Core\Src\main.c
+            
+            
+                $PROJ_DIR$\..\Core\Src\stm32_lpm_if.c
+            
+            
+                $PROJ_DIR$\..\Core\Src\stm32wbxx_hal_msp.c
+            
+            
+                $PROJ_DIR$\..\Core\Src\stm32wbxx_hal_timebase_tim.c
+            
+            
+                $PROJ_DIR$\..\Core\Src\stm32wbxx_it.c
+            
+        
+        
+            EWARM
+            
+                $PROJ_DIR$\startup_stm32wb35xx_cm4.s
+            
+        
+        
+            STM32_WPAN
+            
+                app
+                
+                    $PROJ_DIR$\..\STM32_WPAN\App\app_ble.c
+                
+                
+                    $PROJ_DIR$\..\STM32_WPAN\App\dis_app.c
+                
+                
+                    $PROJ_DIR$\..\STM32_WPAN\App\hrs_app.c
+                
+            
+            
+                target
+                
+                    $PROJ_DIR$\..\STM32_WPAN\Target\hw_ipcc.c
+                
+            
+        
+    
+    
+        Doc
+        
+            $PROJ_DIR$\..\readme.txt
+        
+    
+    
+        Drivers
+        
+            BSP
+            
+                NUCLEO-WB35CE
+                
+                    $PROJ_DIR$\..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE\nucleo_wb35ce.c
+                
+            
+        
+        
+            CMSIS
+            
+                $PROJ_DIR$\..\Core\Src\system_stm32wbxx.c
+            
+        
+        
+            STM32WBxx_HAL_Driver
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_adc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_adc_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_cortex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_gpio.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rtc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rtc_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_spi.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_spi_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_uart.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_uart_ex.c
+            
+        
+    
+    
+        Middlewares
+        
+            STM32_WPAN
+            
+                ble
+                
+                    blesvc
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\svc\Src\dis.c
+                    
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\svc\Src\hrs.c
+                    
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\svc\Src\svc_ctl.c
+                    
+                
+                
+                    core
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_gap_aci.c
+                    
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_gatt_aci.c
+                    
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_hal_aci.c
+                    
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_hci_le.c
+                    
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_l2cap_aci.c
+                    
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\template\osal.c
+                    
+                
+            
+            
+                interface
+                
+                    patterns
+                    
+                        ble_thread
+                        
+                            shci
+                            
+                                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\shci\shci.c
+                            
+                        
+                        
+                            tl
+                            
+                                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\hci_tl.c
+                            
+                            
+                                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\hci_tl_if.c
+                            
+                            
+                                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\shci_tl.c
+                            
+                            
+                                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\shci_tl_if.c
+                            
+                            
+                                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\tl_mbox.c
+                            
+                        
+                    
+                
+            
+            
+                utilities
+                
+                    $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\dbg_trace.c
+                
+                
+                    $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\otp.c
+                
+                
+                    $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\stm_list.c
+                
+                
+                    $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\stm_queue.c
+                
+            
+        
+        
+            Third_Party
+            
+                FreeRTOS
+                
+                    Source
+                    
+                        CMSIS_RTOS_V2
+                        
+                            $PROJ_DIR$\..\..\..\..\..\..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c
+                        
+                    
+                    
+                        portable
+                        
+                            IAR
+                            
+                                ARM_CM4F
+                                
+                                    $PROJ_DIR$\..\..\..\..\..\..\Middlewares\Third_Party\FreeRTOS\Source\portable\IAR\ARM_CM4F\port.c
+                                
+                                
+                                    $PROJ_DIR$\..\..\..\..\..\..\Middlewares\Third_Party\FreeRTOS\Source\portable\IAR\ARM_CM4F\portasm.s
+                                
+                            
+                        
+                        
+                            MemMang
+                            
+                                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c
+                            
+                        
+                    
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\Third_Party\FreeRTOS\Source\list.c
+                    
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\Third_Party\FreeRTOS\Source\queue.c
+                    
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\Third_Party\FreeRTOS\Source\tasks.c
+                    
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\Third_Party\FreeRTOS\Source\timers.c
+                    
+                
+            
+        
+    
+    
+        Utilities
+        
+            $PROJ_DIR$\..\..\..\..\..\..\Utilities\lpm\tiny_lpm\stm32_lpm.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\..\..\Utilities\sequencer\stm32_seq.c
+        
+    
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/Project.eww
new file mode 100644
index 000000000..ce5b81181
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+    
+        $WS_DIR$\BLE_HeartRateFreeRTOS.ewp
+    
+    
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..8f3317a41
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/app_ble.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/app_ble.c
new file mode 100644
index 000000000..45a77d596
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/app_ble.c
@@ -0,0 +1,1141 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    app_ble.c
+ * @author  MCD Application Team
+ * @brief   BLE Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+#include "app_common.h"
+
+#include "dbg_trace.h"
+#include "ble.h"
+#include "tl.h"
+#include "app_ble.h"
+
+#include "cmsis_os.h"
+#include "shci.h"
+#include "stm32_lpm.h"
+#include "otp.h"
+#include "dis_app.h"
+#include "hrs_app.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+
+/**
+ * security parameters structure
+ */ 
+typedef struct _tSecurityParams
+{
+  /**
+   * IO capability of the device
+   */
+  uint8_t ioCapability;
+
+  /**
+   * Authentication requirement of the device
+   * Man In the Middle protection required?
+   */
+  uint8_t mitm_mode;
+
+  /**
+   * bonding mode of the device
+   */
+  uint8_t bonding_mode;
+
+  /**
+   * Flag to tell whether OOB data has
+   * to be used during the pairing process
+   */
+  uint8_t OOB_Data_Present; 
+
+  /**
+   * OOB data to be used in the pairing process if
+   * OOB_Data_Present is set to TRUE
+   */
+  uint8_t OOB_Data[16]; 
+
+  /**
+   * this variable indicates whether to use a fixed pin
+   * during the pairing process or a passkey has to be
+   * requested to the application during the pairing process
+   * 0 implies use fixed pin and 1 implies request for passkey
+   */
+  uint8_t Use_Fixed_Pin; 
+
+  /**
+   * minimum encryption key size requirement
+   */
+  uint8_t encryptionKeySizeMin;
+
+  /**
+   * maximum encryption key size requirement
+   */
+  uint8_t encryptionKeySizeMax;
+
+  /**
+   * fixed pin to be used in the pairing process if
+   * Use_Fixed_Pin is set to 1
+   */
+  uint32_t Fixed_Pin;
+
+  /**
+   * this flag indicates whether the host has to initiate
+   * the security, wait for pairing or does not have any security
+   * requirements.\n
+   * 0x00 : no security required
+   * 0x01 : host should initiate security by sending the slave security
+   *        request command
+   * 0x02 : host need not send the clave security request but it
+   * has to wait for paiirng to complete before doing any other
+   * processing
+   */
+  uint8_t initiateSecurity;
+}tSecurityParams;
+
+/**
+ * global context
+ * contains the variables common to all 
+ * services
+ */ 
+typedef struct _tBLEProfileGlobalContext
+{
+
+  /**
+   * security requirements of the host
+   */ 
+  tSecurityParams bleSecurityParam;
+
+  /**
+   * gap service handle
+   */
+  uint16_t gapServiceHandle;
+
+  /**
+   * device name characteristic handle
+   */ 
+  uint16_t devNameCharHandle;
+
+  /**
+   * appearance characteristic handle
+   */ 
+  uint16_t appearanceCharHandle;
+
+  /**
+   * connection handle of the current active connection
+   * When not in connection, the handle is set to 0xFFFF
+   */ 
+  uint16_t connectionHandle;
+
+  /**
+   * length of the UUID list to be used while advertising
+   */ 
+  uint8_t advtServUUIDlen;
+
+  /**
+   * the UUID list to be used while advertising
+   */ 
+  uint8_t advtServUUID[100];
+
+}BleGlobalContext_t;
+
+typedef struct
+{
+  BleGlobalContext_t BleApplicationContext_legacy;
+   APP_BLE_ConnStatus_t Device_Connection_Status;
+   /**
+   * ID of the Advertising Timeout
+   */
+   uint8_t Advertising_mgr_timer_Id;
+
+}BleApplicationContext_t;
+/* USER CODE BEGIN PTD */
+  
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+#define APPBLE_GAP_DEVICE_NAME_LENGTH 7
+#define FAST_ADV_TIMEOUT               (30*1000*1000/CFG_TS_TICK_VAL) /**< 30s */
+#define INITIAL_ADV_TIMEOUT            (60*1000*1000/CFG_TS_TICK_VAL) /**< 60s */
+
+#define BD_ADDR_SIZE_LOCAL    6
+
+/* USER CODE BEGIN PD */
+#define LED_ON_TIMEOUT                 (0.005*1000*1000/CFG_TS_TICK_VAL) /**< 5ms */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static TL_CmdPacket_t BleCmdBuffer;
+
+static const uint8_t M_bd_addr[BD_ADDR_SIZE_LOCAL] =
+    {
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x0000000000FF)),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x00000000FF00) >> 8),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x000000FF0000) >> 16),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x0000FF000000) >> 24),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x00FF00000000) >> 32),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0xFF0000000000) >> 40)
+    };
+
+static uint8_t bd_addr_udn[BD_ADDR_SIZE_LOCAL];
+
+/**
+*   Identity root key used to derive LTK and CSRK 
+*/
+static const uint8_t BLE_CFG_IR_VALUE[16] = CFG_BLE_IRK;
+
+/**
+* Encryption root key used to derive LTK and CSRK
+*/
+static const uint8_t BLE_CFG_ER_VALUE[16] = CFG_BLE_ERK;
+
+/**
+ * These are the two tags used to manage a power failure during OTA
+ * The MagicKeywordAdress shall be mapped @0x140 from start of the binary image
+ * The MagicKeywordvalue is checked in the ble_ota application
+ */
+PLACE_IN_SECTION("TAG_OTA_END") const uint32_t MagicKeywordValue = 0x94448A29 ;
+PLACE_IN_SECTION("TAG_OTA_START") const uint32_t MagicKeywordAddress = (uint32_t)&MagicKeywordValue;
+
+PLACE_IN_SECTION("BLE_APP_CONTEXT") static BleApplicationContext_t BleApplicationContext;
+PLACE_IN_SECTION("BLE_APP_CONTEXT") static uint16_t AdvIntervalMin, AdvIntervalMax;
+
+static const char local_name[] = { AD_TYPE_COMPLETE_LOCAL_NAME ,'H','R','S','T','M'};
+uint8_t  manuf_data[14] = {
+    sizeof(manuf_data)-1, AD_TYPE_MANUFACTURER_SPECIFIC_DATA,
+    0x01/*SKD version */,
+    0x00 /* Generic*/,
+    0x00 /* GROUP A Feature  */, 
+    0x00 /* GROUP A Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00, /* BLE MAC start -MSB */
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00, /* BLE MAC stop */
+
+};
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Global variables ----------------------------------------------------------*/
+osMutexId_t MtxHciId;
+osSemaphoreId_t SemHciId;
+osThreadId_t AdvUpdateProcessId;
+osThreadId_t HciUserEvtProcessId;
+
+const osThreadAttr_t AdvUpdateProcess_attr = {
+    .name = CFG_ADV_UPDATE_PROCESS_NAME,
+    .attr_bits = CFG_ADV_UPDATE_PROCESS_ATTR_BITS,
+    .cb_mem = CFG_ADV_UPDATE_PROCESS_CB_MEM,
+    .cb_size = CFG_ADV_UPDATE_PROCESS_CB_SIZE,
+    .stack_mem = CFG_ADV_UPDATE_PROCESS_STACK_MEM,
+    .priority = CFG_ADV_UPDATE_PROCESS_PRIORITY,
+    .stack_size = CFG_ADV_UPDATE_PROCESS_STACk_SIZE
+};
+
+const osThreadAttr_t HciUserEvtProcess_attr = {
+    .name = CFG_HCI_USER_EVT_PROCESS_NAME,
+    .attr_bits = CFG_HCI_USER_EVT_PROCESS_ATTR_BITS,
+    .cb_mem = CFG_HCI_USER_EVT_PROCESS_CB_MEM,
+    .cb_size = CFG_HCI_USER_EVT_PROCESS_CB_SIZE,
+    .stack_mem = CFG_HCI_USER_EVT_PROCESS_STACK_MEM,
+    .priority = CFG_HCI_USER_EVT_PROCESS_PRIORITY,
+    .stack_size = CFG_HCI_USER_EVT_PROCESS_STACk_SIZE
+};
+
+/* Private function prototypes -----------------------------------------------*/
+static void HciUserEvtProcess(void *argument);
+static void BLE_UserEvtRx( void * pPayload );
+static void BLE_StatusNot( HCI_TL_CmdStatus_t status );
+static void Ble_Tl_Init( void );
+static void Ble_Hci_Gap_Gatt_Init(void);
+static const uint8_t* BleGetBdAddress( void );
+static void Adv_Request( APP_BLE_ConnStatus_t New_Status );
+static void Add_Advertisment_Service_UUID( uint16_t servUUID );
+static void Adv_Mgr( void );
+static void AdvUpdateProcess(void *argument);
+static void Adv_Update( void );
+
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APP_BLE_Init( void )
+{
+/* USER CODE BEGIN APP_BLE_Init_1 */
+
+/* USER CODE END APP_BLE_Init_1 */
+  SHCI_C2_Ble_Init_Cmd_Packet_t ble_init_cmd_packet =
+  {
+    {{0,0,0}},                          /**< Header unused */
+    {0,                                 /** pBleBufferAddress not used */
+    0,                                  /** BleBufferSize not used */
+    CFG_BLE_NUM_GATT_ATTRIBUTES,
+    CFG_BLE_NUM_GATT_SERVICES,
+    CFG_BLE_ATT_VALUE_ARRAY_SIZE,
+    CFG_BLE_NUM_LINK,
+    CFG_BLE_DATA_LENGTH_EXTENSION,
+    CFG_BLE_PREPARE_WRITE_LIST_SIZE,
+    CFG_BLE_MBLOCK_COUNT,
+    CFG_BLE_MAX_ATT_MTU,
+    CFG_BLE_SLAVE_SCA,
+    CFG_BLE_MASTER_SCA,
+    CFG_BLE_LSE_SOURCE,
+    CFG_BLE_MAX_CONN_EVENT_LENGTH,
+    CFG_BLE_HSE_STARTUP_TIME,
+    CFG_BLE_VITERBI_MODE,
+    CFG_BLE_LL_ONLY,
+    0}
+  };
+
+  /**
+   * Initialize Ble Transport Layer
+   */
+  Ble_Tl_Init( );
+
+  /**
+   * Do not allow standby in the application
+   */
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP_BLE, UTIL_LPM_DISABLE);
+
+  /**
+   * Register the hci transport layer to handle BLE User Asynchronous Events
+   */
+  HciUserEvtProcessId = osThreadNew(HciUserEvtProcess, NULL, &HciUserEvtProcess_attr);
+
+  /**
+   * Starts the BLE Stack on CPU2
+   */
+  SHCI_C2_BLE_Init( &ble_init_cmd_packet );
+
+  /**
+   * Initialization of HCI & GATT & GAP layer
+   */
+  Ble_Hci_Gap_Gatt_Init();
+
+  /**
+   * Initialization of the BLE Services
+   */
+  SVCCTL_Init();
+
+  /**
+   * Initialization of the BLE App Context
+   */
+  BleApplicationContext.Device_Connection_Status = APP_BLE_IDLE;
+  BleApplicationContext.BleApplicationContext_legacy.connectionHandle = 0xFFFF;  
+  /**
+   * From here, all initialization are BLE application specific
+   */
+  AdvUpdateProcessId = osThreadNew(AdvUpdateProcess, NULL, &AdvUpdateProcess_attr);
+  /**
+   * Initialization of ADV - Ad Manufacturer Element - Support OTA Bit Mask
+   */
+#if(BLE_CFG_OTA_REBOOT_CHAR != 0)  
+    manuf_data[sizeof(manuf_data)-8] = CFG_FEATURE_OTA_REBOOT;
+#endif
+  /**
+   * Initialize DIS Application
+   */
+  DISAPP_Init();
+
+  /**
+   * Initialize HRS Application
+   */
+  HRSAPP_Init();
+
+  /**
+   * Create timer to handle the connection state machine
+   */
+
+  HW_TS_Create(CFG_TIM_PROC_ID_ISR, &(BleApplicationContext.Advertising_mgr_timer_Id), hw_ts_SingleShot, Adv_Mgr);
+
+  /**
+   * Make device discoverable
+   */
+  BleApplicationContext.BleApplicationContext_legacy.advtServUUID[0] = AD_TYPE_16_BIT_SERV_UUID;
+  BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen = 1;
+  Add_Advertisment_Service_UUID(HEART_RATE_SERVICE_UUID);
+  /* Initialize intervals for reconnexion without intervals update */
+  AdvIntervalMin = CFG_FAST_CONN_ADV_INTERVAL_MIN;
+  AdvIntervalMax = CFG_FAST_CONN_ADV_INTERVAL_MAX;
+
+  /**
+  * Start to Advertise to be connected by Collector
+   */
+   Adv_Request(APP_BLE_FAST_ADV);
+
+/* USER CODE BEGIN APP_BLE_Init_2 */
+
+/* USER CODE END APP_BLE_Init_2 */
+  return;
+}
+
+SVCCTL_UserEvtFlowStatus_t SVCCTL_App_Notification( void *pckt )
+{
+  hci_event_pckt *event_pckt;
+  evt_le_meta_event *meta_evt;
+  evt_blue_aci *blue_evt;
+  hci_le_phy_update_complete_event_rp0 *evt_le_phy_update_complete; 
+  uint8_t TX_PHY, RX_PHY;
+  tBleStatus ret = BLE_STATUS_INVALID_PARAMS;
+
+  event_pckt = (hci_event_pckt*) ((hci_uart_pckt *) pckt)->data;
+
+  switch (event_pckt->evt)
+  {
+    case EVT_DISCONN_COMPLETE:
+    {
+      hci_disconnection_complete_event_rp0 *disconnection_complete_event;
+      disconnection_complete_event = (hci_disconnection_complete_event_rp0 *) event_pckt->data;
+
+      if (disconnection_complete_event->Connection_Handle == BleApplicationContext.BleApplicationContext_legacy.connectionHandle)
+      {
+        BleApplicationContext.BleApplicationContext_legacy.connectionHandle = 0;
+        BleApplicationContext.Device_Connection_Status = APP_BLE_IDLE;
+
+        APP_DBG_MSG("\r\n\r** DISCONNECTION EVENT WITH CLIENT \n");
+      }
+
+      /* restart advertising */
+      Adv_Request(APP_BLE_FAST_ADV);
+      /* USER CODE BEGIN EVT_DISCONN_COMPLETE */
+
+      /* USER CODE END EVT_DISCONN_COMPLETE */
+    }
+
+    break; /* EVT_DISCONN_COMPLETE */
+
+    case EVT_LE_META_EVENT:
+    {
+      meta_evt = (evt_le_meta_event*) event_pckt->data;
+      /* USER CODE BEGIN EVT_LE_META_EVENT */
+
+      /* USER CODE END EVT_LE_META_EVENT */
+      switch (meta_evt->subevent)
+      {
+        case EVT_LE_CONN_UPDATE_COMPLETE: 
+          APP_DBG_MSG("\r\n\r** CONNECTION UPDATE EVENT WITH CLIENT \n");
+
+          /* USER CODE BEGIN EVT_LE_CONN_UPDATE_COMPLETE */
+
+          /* USER CODE END EVT_LE_CONN_UPDATE_COMPLETE */
+          break;
+        case EVT_LE_PHY_UPDATE_COMPLETE:
+          APP_DBG_MSG("EVT_UPDATE_PHY_COMPLETE \n");
+
+          evt_le_phy_update_complete = (hci_le_phy_update_complete_event_rp0*)meta_evt->data;
+          if (evt_le_phy_update_complete->Status == 0)
+          {
+            APP_DBG_MSG("EVT_UPDATE_PHY_COMPLETE, status ok \n");
+          }
+          else
+          {
+            APP_DBG_MSG("EVT_UPDATE_PHY_COMPLETE, status nok \n");
+          }
+         
+          ret = hci_le_read_phy(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,&TX_PHY,&RX_PHY);
+          if (ret == BLE_STATUS_SUCCESS)
+          {
+            APP_DBG_MSG("Read_PHY success \n");
+       
+            if ((TX_PHY == TX_2M) && (RX_PHY == RX_2M))
+            {
+              APP_DBG_MSG("PHY Param  TX= %d, RX= %d \n", TX_PHY, RX_PHY);
+            }
+            else
+            {
+              APP_DBG_MSG("PHY Param  TX= %d, RX= %d \n", TX_PHY, RX_PHY);
+            } 
+          }
+          else
+          {
+            APP_DBG_MSG("Read conf not succeess \n");
+          }
+          /* USER CODE BEGIN EVT_LE_PHY_UPDATE_COMPLETE */
+
+          /* USER CODE END EVT_LE_PHY_UPDATE_COMPLETE */          
+          break;  
+          
+        case EVT_LE_CONN_COMPLETE:
+        {
+          hci_le_connection_complete_event_rp0 *connection_complete_event;
+
+          /**
+           * The connection is done, there is no need anymore to schedule the LP ADV
+           */
+          connection_complete_event = (hci_le_connection_complete_event_rp0 *) meta_evt->data;
+
+          HW_TS_Stop(BleApplicationContext.Advertising_mgr_timer_Id);
+
+          APP_DBG_MSG("EVT_LE_CONN_COMPLETE for connection handle 0x%x\n", connection_complete_event->Connection_Handle);
+          if (BleApplicationContext.Device_Connection_Status == APP_BLE_LP_CONNECTING)
+          {
+            /* Connection as client */
+            BleApplicationContext.Device_Connection_Status = APP_BLE_CONNECTED_CLIENT;
+          }
+          else
+          {
+            /* Connection as server */
+            BleApplicationContext.Device_Connection_Status = APP_BLE_CONNECTED_SERVER;
+          }
+          BleApplicationContext.BleApplicationContext_legacy.connectionHandle = connection_complete_event->Connection_Handle;
+          /* USER CODE BEGIN HCI_EVT_LE_CONN_COMPLETE */
+
+          /* USER CODE END HCI_EVT_LE_CONN_COMPLETE */
+        }
+        break; /* HCI_EVT_LE_CONN_COMPLETE */
+
+        default:
+          /* USER CODE BEGIN SUBEVENT_DEFAULT */
+
+          /* USER CODE END SUBEVENT_DEFAULT */
+          break;
+      }
+    }
+    break; /* HCI_EVT_LE_META_EVENT */
+
+    case EVT_VENDOR:
+      blue_evt = (evt_blue_aci*) event_pckt->data;
+      /* USER CODE BEGIN EVT_VENDOR */
+
+      /* USER CODE END EVT_VENDOR */
+      switch (blue_evt->ecode)
+      {
+      /* USER CODE BEGIN ecode */
+        aci_gap_pairing_complete_event_rp0 *pairing_complete;
+
+      case EVT_BLUE_GAP_LIMITED_DISCOVERABLE: 
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_LIMITED_DISCOVERABLE \n");
+          break; /* EVT_BLUE_GAP_LIMITED_DISCOVERABLE */
+          
+      case EVT_BLUE_GAP_PASS_KEY_REQUEST:  
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_PASS_KEY_REQUEST \n");
+
+        aci_gap_pass_key_resp(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,123456);
+
+        APP_DBG_MSG("\r\n\r** aci_gap_pass_key_resp \n");
+          break; /* EVT_BLUE_GAP_PASS_KEY_REQUEST */
+
+      case EVT_BLUE_GAP_AUTHORIZATION_REQUEST:    
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_AUTHORIZATION_REQUEST \n");
+          break; /* EVT_BLUE_GAP_AUTHORIZATION_REQUEST */
+
+      case EVT_BLUE_GAP_SLAVE_SECURITY_INITIATED:   
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_SLAVE_SECURITY_INITIATED \n");
+          break; /* EVT_BLUE_GAP_SLAVE_SECURITY_INITIATED */
+
+      case EVT_BLUE_GAP_BOND_LOST:    
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_BOND_LOST \n");
+          aci_gap_allow_rebond(BleApplicationContext.BleApplicationContext_legacy.connectionHandle);
+        APP_DBG_MSG("\r\n\r** Send allow rebond \n");
+          break; /* EVT_BLUE_GAP_BOND_LOST */
+
+      case EVT_BLUE_GAP_DEVICE_FOUND:  
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_DEVICE_FOUND \n");
+          break; /* EVT_BLUE_GAP_DEVICE_FOUND */
+
+      case EVT_BLUE_GAP_ADDR_NOT_RESOLVED:
+         APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_DEVICE_FOUND \n");
+          break; /* EVT_BLUE_GAP_DEVICE_FOUND */
+      
+      case (EVT_BLUE_GAP_KEYPRESS_NOTIFICATION):
+         APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_KEYPRESS_NOTIFICATION \n");
+          break; /* EVT_BLUE_GAP_KEY_PRESS_NOTIFICATION */    
+
+       case (EVT_BLUE_GAP_NUMERIC_COMPARISON_VALUE):
+          APP_DBG_MSG("numeric_value = %d\n",
+                      ((aci_gap_numeric_comparison_value_event_rp0 *)(blue_evt->data))->Numeric_Value);
+
+          APP_DBG_MSG("Hex_value = %x\n",
+                      ((aci_gap_numeric_comparison_value_event_rp0 *)(blue_evt->data))->Numeric_Value);
+
+          aci_gap_numeric_comparison_value_confirm_yesno(BleApplicationContext.BleApplicationContext_legacy.connectionHandle, 1); /* CONFIRM_YES = 1 */
+
+          APP_DBG_MSG("\r\n\r** aci_gap_numeric_comparison_value_confirm_yesno-->YES \n");
+          break;
+
+          case (EVT_BLUE_GAP_PAIRING_CMPLT):
+          {
+            pairing_complete = (aci_gap_pairing_complete_event_rp0*)blue_evt->data;
+
+            APP_DBG_MSG("BLE_CTRL_App_Notification: EVT_BLUE_GAP_PAIRING_CMPLT, pairing_complete->Status = %d\n",pairing_complete->Status);
+            if (pairing_complete->Status == 0)
+            {
+              APP_DBG_MSG("\r\n\r** Pairing OK \n");
+            }
+            else
+            {
+              APP_DBG_MSG("\r\n\r** Pairing KO \n");
+            }
+          }
+           break;    
+
+      /* USER CODE END ecode */
+        case EVT_BLUE_GAP_PROCEDURE_COMPLETE:
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_PROCEDURE_COMPLETE \n");
+        /* USER CODE BEGIN EVT_BLUE_GAP_PROCEDURE_COMPLETE */
+
+        /* USER CODE END EVT_BLUE_GAP_PROCEDURE_COMPLETE */
+          break; /* EVT_BLUE_GAP_PROCEDURE_COMPLETE */
+      }
+      break; /* EVT_VENDOR */
+
+        default:
+        /* USER CODE BEGIN ECODE_DEFAULT*/
+
+        /* USER CODE END ECODE_DEFAULT*/
+          break;
+  }
+
+  return (SVCCTL_UserEvtFlowEnable);
+}
+
+APP_BLE_ConnStatus_t APP_BLE_Get_Server_Connection_Status(void)
+{
+    return BleApplicationContext.Device_Connection_Status;
+}
+
+/* USER CODE BEGIN FD*/
+void APP_BLE_Key_Button1_Action(void)
+{
+  tBleStatus ret = BLE_STATUS_INVALID_PARAMS;
+  ret = aci_gap_clear_security_db();
+      if (ret == BLE_STATUS_SUCCESS)
+      {
+        APP_DBG_MSG("Successfully aci_gap_clear_security_db()\n");
+      }
+      else
+      {
+        APP_DBG_MSG("aci_gap_clear_security_db() Failed , result: %d \n", ret);
+      }
+}
+
+void APP_BLE_Key_Button2_Action(void)
+{
+  tBleStatus ret = BLE_STATUS_INVALID_PARAMS;
+  ret = aci_gap_slave_security_req(BleApplicationContext.BleApplicationContext_legacy.connectionHandle); 
+  if (ret == BLE_STATUS_SUCCESS)
+      {
+        APP_DBG_MSG("Successfully aci_gap_slave_security_req()");
+      }
+      else
+      {
+        APP_DBG_MSG("aci_gap_slave_security_req() Failed , result: %d \n", ret);
+      }
+}
+  
+void APP_BLE_Key_Button3_Action(void)
+{
+  uint8_t TX_PHY, RX_PHY;
+  tBleStatus ret = BLE_STATUS_INVALID_PARAMS;
+  ret = hci_le_read_phy(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,&TX_PHY,&RX_PHY);
+      if (ret == BLE_STATUS_SUCCESS)
+      {
+        APP_DBG_MSG("Read_PHY success \n");
+        APP_DBG_MSG("PHY Param  TX= %d, RX= %d \n", TX_PHY, RX_PHY);
+        if ((TX_PHY == TX_2M) && (RX_PHY == RX_2M))
+        {
+          APP_DBG_MSG("hci_le_set_phy PHY Param  TX= %d, RX= %d \n", TX_1M, RX_1M);
+          ret = hci_le_set_phy(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,ALL_PHYS_PREFERENCE,TX_1M,RX_1M,0);
+        }
+        else
+        {
+          APP_DBG_MSG("hci_le_set_phy PHY Param  TX= %d, RX= %d \n", TX_2M_PREFERRED, RX_2M_PREFERRED);
+          ret = hci_le_set_phy(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,ALL_PHYS_PREFERENCE,TX_2M_PREFERRED,RX_2M_PREFERRED,0);
+        } 
+      }
+      else
+      {
+        APP_DBG_MSG("Read conf not succeess \n");
+}
+
+        if (ret == BLE_STATUS_SUCCESS)
+        {
+          APP_DBG_MSG("set PHY cmd ok\n");
+        }
+        else 
+{
+          APP_DBG_MSG("set PHY cmd NOK\n");
+        }
+}
+
+/* USER CODE END FD*/
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void Ble_Tl_Init( void )
+{
+  HCI_TL_HciInitConf_t Hci_Tl_Init_Conf;
+
+  MtxHciId = osMutexNew( NULL );
+  SemHciId = osSemaphoreNew( 1, 0, NULL ); /*< Create the semaphore and make it busy at initialization */
+
+  Hci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&BleCmdBuffer;
+  Hci_Tl_Init_Conf.StatusNotCallBack = BLE_StatusNot;
+  hci_init(BLE_UserEvtRx, (void*) &Hci_Tl_Init_Conf);
+
+  return;
+}
+
+static void Ble_Hci_Gap_Gatt_Init(void){
+
+  uint8_t role;
+  uint8_t index;
+  uint16_t gap_service_handle, gap_dev_name_char_handle, gap_appearance_char_handle;
+  const uint8_t *bd_addr;
+  uint32_t srd_bd_addr[2];
+  uint16_t appearance[1] = { BLE_CFG_GAP_APPEARANCE }; 
+
+  /**
+   * Initialize HCI layer
+   */
+  /*HCI Reset to synchronise BLE Stack*/
+  hci_reset();
+
+  /**
+   * Write the BD Address
+   */
+
+  bd_addr = BleGetBdAddress();
+  aci_hal_write_config_data(CONFIG_DATA_PUBADDR_OFFSET,
+                            CONFIG_DATA_PUBADDR_LEN,
+                            (uint8_t*) bd_addr);
+
+  /* BLE MAC in ADV Packet */
+  manuf_data[ sizeof(manuf_data)-6] = bd_addr[5];
+  manuf_data[ sizeof(manuf_data)-5] = bd_addr[4];
+  manuf_data[ sizeof(manuf_data)-4] = bd_addr[3];
+  manuf_data[ sizeof(manuf_data)-3] = bd_addr[2];
+  manuf_data[ sizeof(manuf_data)-2] = bd_addr[1];
+  manuf_data[ sizeof(manuf_data)-1] = bd_addr[0];
+  
+  /**
+   * Write Identity root key used to derive LTK and CSRK 
+   */
+    aci_hal_write_config_data(CONFIG_DATA_IR_OFFSET,
+    CONFIG_DATA_IR_LEN,
+                            (uint8_t*) BLE_CFG_IR_VALUE);
+    
+   /**
+   * Write Encryption root key used to derive LTK and CSRK
+   */
+    aci_hal_write_config_data(CONFIG_DATA_ER_OFFSET,
+    CONFIG_DATA_ER_LEN,
+                            (uint8_t*) BLE_CFG_ER_VALUE);
+
+   /**
+   * Write random bd_address
+   */
+   /* random_bd_address = R_bd_address;
+    aci_hal_write_config_data(CONFIG_DATA_RANDOM_ADDRESS_WR,
+    CONFIG_DATA_RANDOM_ADDRESS_LEN,
+                            (uint8_t*) random_bd_address);
+  */
+
+  /**
+   * Static random Address
+   * The two upper bits shall be set to 1
+   * The lowest 32bits is read from the UDN to differentiate between devices
+   * The RNG may be used to provide a random number on each power on
+   */
+  srd_bd_addr[1] =  0x0000ED6E;
+  srd_bd_addr[0] =  LL_FLASH_GetUDN( );
+  aci_hal_write_config_data( CONFIG_DATA_RANDOM_ADDRESS_OFFSET, CONFIG_DATA_RANDOM_ADDRESS_LEN, (uint8_t*)srd_bd_addr );
+
+  /**
+   * Write Identity root key used to derive LTK and CSRK 
+   */
+    aci_hal_write_config_data( CONFIG_DATA_IR_OFFSET, CONFIG_DATA_IR_LEN, (uint8_t*)BLE_CFG_IR_VALUE );
+    
+   /**
+   * Write Encryption root key used to derive LTK and CSRK
+   */
+    aci_hal_write_config_data( CONFIG_DATA_ER_OFFSET, CONFIG_DATA_ER_LEN, (uint8_t*)BLE_CFG_ER_VALUE );
+
+  /**
+   * Set TX Power to 0dBm.
+   */
+  aci_hal_set_tx_power_level(1, CFG_TX_POWER);
+
+  /**
+   * Initialize GATT interface
+   */
+  aci_gatt_init();
+
+  /**
+   * Initialize GAP interface
+   */
+  role = 0;
+
+#if (BLE_CFG_PERIPHERAL == 1)
+  role |= GAP_PERIPHERAL_ROLE;
+#endif
+
+#if (BLE_CFG_CENTRAL == 1)
+  role |= GAP_CENTRAL_ROLE;
+#endif
+
+  if (role > 0)
+  {
+    const char *name = "STM32WB";
+    aci_gap_init(role, 0,
+                 APPBLE_GAP_DEVICE_NAME_LENGTH,
+                 &gap_service_handle, &gap_dev_name_char_handle, &gap_appearance_char_handle);
+
+    if (aci_gatt_update_char_value(gap_service_handle, gap_dev_name_char_handle, 0, strlen(name), (uint8_t *) name))
+    {
+      BLE_DBG_SVCCTL_MSG("Device Name aci_gatt_update_char_value failed.\n");
+    }
+  }
+
+  if(aci_gatt_update_char_value(gap_service_handle,
+                                gap_appearance_char_handle,
+                                0,
+                                2,
+                                (uint8_t *)&appearance))
+  {
+    BLE_DBG_SVCCTL_MSG("Appearance aci_gatt_update_char_value failed.\n");
+  }
+/**
+   * Initialize Default PHY
+   */
+  hci_le_set_default_phy(ALL_PHYS_PREFERENCE,TX_2M_PREFERRED,RX_2M_PREFERRED); 
+
+  /**
+   * Initialize IO capability
+   */
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.ioCapability = CFG_IO_CAPABILITY;
+  aci_gap_set_io_capability(BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.ioCapability);
+
+  /**
+   * Initialize authentication
+   */
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode = CFG_MITM_PROTECTION;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data_Present = 0;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin = 8;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax = 16;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin = 1;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin = 111111;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode = 1;
+  for (index = 0; index < 16; index++)
+  {
+    BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data[index] = (uint8_t) index;
+  }
+
+  aci_gap_set_authentication_requirement(BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode,
+                                         1,
+                                         0,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin,
+                                         0
+  );
+
+  /**
+   * Initialize whitelist
+   */
+   if (BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode)
+   {
+     aci_gap_configure_whitelist();
+   }
+}
+
+static void Adv_Request(APP_BLE_ConnStatus_t New_Status)
+{
+  tBleStatus ret = BLE_STATUS_INVALID_PARAMS;
+  uint16_t Min_Inter, Max_Inter;
+
+  if (New_Status == APP_BLE_FAST_ADV)
+  {
+    Min_Inter = AdvIntervalMin;
+    Max_Inter = AdvIntervalMax;
+  }
+  else
+  {
+    Min_Inter = CFG_LP_CONN_ADV_INTERVAL_MIN;
+    Max_Inter = CFG_LP_CONN_ADV_INTERVAL_MAX;
+  }
+
+    /**
+     * Stop the timer, it will be restarted for a new shot
+     * It does not hurt if the timer was not running
+     */
+    HW_TS_Stop(BleApplicationContext.Advertising_mgr_timer_Id);
+
+    APP_DBG_MSG("First index in %d state \n", BleApplicationContext.Device_Connection_Status);
+
+    if ((New_Status == APP_BLE_LP_ADV)
+        && ((BleApplicationContext.Device_Connection_Status == APP_BLE_FAST_ADV)
+            || (BleApplicationContext.Device_Connection_Status == APP_BLE_LP_ADV)))
+    {
+      /* Connection in ADVERTISE mode have to stop the current advertising */
+      ret = aci_gap_set_non_discoverable();
+      if (ret == BLE_STATUS_SUCCESS)
+      {
+        APP_DBG_MSG("Successfully Stopped Advertising \n");
+      }
+      else
+      {
+        APP_DBG_MSG("Stop Advertising Failed , result: %d \n", ret);
+      }
+    }
+
+    BleApplicationContext.Device_Connection_Status = New_Status;
+    /* Start Fast or Low Power Advertising */
+    ret = aci_gap_set_discoverable(
+        ADV_IND,
+        Min_Inter,
+        Max_Inter,
+        PUBLIC_ADDR,
+        NO_WHITE_LIST_USE, /* use white list */
+        sizeof(local_name),
+        (uint8_t*) &local_name,
+        BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen,
+        BleApplicationContext.BleApplicationContext_legacy.advtServUUID,
+        0,
+        0);
+    /* Update Advertising data */
+    ret = aci_gap_update_adv_data(sizeof(manuf_data), (uint8_t*) manuf_data);
+
+    if (ret == BLE_STATUS_SUCCESS)
+    {
+      if (New_Status == APP_BLE_FAST_ADV)
+      {
+        APP_DBG_MSG("Successfully Start Fast Advertising \n" );
+        /* Start Timer to STOP ADV - TIMEOUT */
+        HW_TS_Start(BleApplicationContext.Advertising_mgr_timer_Id, INITIAL_ADV_TIMEOUT);
+      }
+      else
+      {
+        APP_DBG_MSG("Successfully Start Low Power Advertising \n");
+      }
+    }
+    else
+    {
+      if (New_Status == APP_BLE_FAST_ADV)
+      {
+        APP_DBG_MSG("Start Fast Advertising Failed , result: %d \n", ret);
+      }
+      else
+      {
+        APP_DBG_MSG("Start Low Power Advertising Failed , result: %d \n", ret);
+    }
+  }
+
+  return;
+}
+
+const uint8_t* BleGetBdAddress( void )
+{
+  uint8_t *otp_addr;
+  const uint8_t *bd_addr;
+  uint32_t udn;
+  uint32_t company_id;
+  uint32_t device_id;
+
+  udn = LL_FLASH_GetUDN();
+
+  if(udn != 0xFFFFFFFF)
+  {
+    company_id = LL_FLASH_GetSTCompanyID();
+    device_id = LL_FLASH_GetDeviceID();
+
+    bd_addr_udn[0] = (uint8_t)(udn & 0x000000FF);
+    bd_addr_udn[1] = (uint8_t)( (udn & 0x0000FF00) >> 8 );
+    bd_addr_udn[2] = (uint8_t)( (udn & 0x00FF0000) >> 16 );
+    bd_addr_udn[3] = (uint8_t)device_id;
+    bd_addr_udn[4] = (uint8_t)(company_id & 0x000000FF);;
+    bd_addr_udn[5] = (uint8_t)( (company_id & 0x0000FF00) >> 8 );
+
+    bd_addr = (const uint8_t *)bd_addr_udn;
+  }
+  else
+  {
+    otp_addr = OTP_Read(0);
+    if(otp_addr)
+    {
+      bd_addr = ((OTP_ID0_t*)otp_addr)->bd_address;
+    }
+    else
+    {
+      bd_addr = M_bd_addr;
+    }
+
+  }
+
+  return bd_addr;
+}
+
+/* USER CODE BEGIN FD_LOCAL_FUNCTION */
+
+/* USER CODE END FD_LOCAL_FUNCTION */
+
+/*************************************************************
+ *
+ *SPECIFIC FUNCTIONS
+ *
+ *************************************************************/
+static void Add_Advertisment_Service_UUID( uint16_t servUUID )
+{
+  BleApplicationContext.BleApplicationContext_legacy.advtServUUID[BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen] =
+      (uint8_t) (servUUID & 0xFF);
+  BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen++;
+  BleApplicationContext.BleApplicationContext_legacy.advtServUUID[BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen] =
+      (uint8_t) (servUUID >> 8) & 0xFF;
+  BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen++;
+
+  return;
+}
+
+static void Adv_Mgr( void )
+{
+  /**
+   * The code shall be executed in the background as an aci command may be sent
+   * The background is the only place where the application can make sure a new aci command
+   * is not sent if there is a pending one
+   */
+  osThreadFlagsSet( AdvUpdateProcessId, 1 );
+
+  return;
+}
+
+static void AdvUpdateProcess(void *argument)
+{
+  UNUSED(argument);
+
+  for(;;)
+  {
+    osThreadFlagsWait( 1, osFlagsWaitAny, osWaitForever);
+    Adv_Update( );
+  }
+}
+
+static void Adv_Update( void )
+{
+  Adv_Request(APP_BLE_LP_ADV);
+
+  return;
+}
+
+static void HciUserEvtProcess(void *argument)
+{
+  UNUSED(argument);
+
+  for(;;)
+  {
+    osThreadFlagsWait( 1, osFlagsWaitAny, osWaitForever);
+    hci_user_evt_proc( );
+  }
+}
+
+/* USER CODE BEGIN FD_SPECIFIC_FUNCTIONS */
+
+/* USER CODE END FD_SPECIFIC_FUNCTIONS */
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+void hci_notify_asynch_evt(void* pdata)
+{
+  UNUSED(pdata);
+  osThreadFlagsSet( HciUserEvtProcessId, 1 );
+  return;
+}
+
+void hci_cmd_resp_release(uint32_t flag)
+{
+  UNUSED(flag);
+  osSemaphoreRelease( SemHciId );
+  return;
+}
+
+void hci_cmd_resp_wait(uint32_t timeout)
+{
+  UNUSED(timeout);
+  osSemaphoreAcquire( SemHciId, osWaitForever );
+  return;
+}
+
+static void BLE_UserEvtRx( void * pPayload )
+{
+  SVCCTL_UserEvtFlowStatus_t svctl_return_status;
+  tHCI_UserEvtRxParam *pParam;
+
+  pParam = (tHCI_UserEvtRxParam *)pPayload; 
+
+  svctl_return_status = SVCCTL_UserEvtRx((void *)&(pParam->pckt->evtserial));
+  if (svctl_return_status != SVCCTL_UserEvtFlowDisable)
+  {
+    pParam->status = HCI_TL_UserEventFlow_Enable;
+  }
+  else
+  {
+    pParam->status = HCI_TL_UserEventFlow_Disable;
+  }
+}
+
+static void BLE_StatusNot( HCI_TL_CmdStatus_t status )
+{
+  switch (status)
+  {
+    case HCI_TL_CmdBusy:
+      osMutexAcquire( MtxHciId, osWaitForever );
+      break;
+
+    case HCI_TL_CmdAvailable:
+      osMutexRelease( MtxHciId );
+      break;
+
+    default:
+      break;
+  }
+  return;
+}
+
+void SVCCTL_ResumeUserEventFlow( void )
+{
+  hci_resume_flow();
+  return;
+}
+
+/* USER CODE BEGIN FD_WRAP_FUNCTIONS */
+
+/* USER CODE END FD_WRAP_FUNCTIONS */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/app_ble.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/app_ble.h
new file mode 100644
index 000000000..657ba432b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/app_ble.h
@@ -0,0 +1,88 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    app_ble.h
+  * @author  MCD Application Team
+  * @brief   Header for ble application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_BLE_H
+#define APP_BLE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "hci_tl.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+
+    typedef enum
+    {
+      APP_BLE_IDLE,
+      APP_BLE_FAST_ADV,
+      APP_BLE_LP_ADV,
+      APP_BLE_SCAN,
+      APP_BLE_LP_CONNECTING,
+      APP_BLE_CONNECTED_SERVER,
+      APP_BLE_CONNECTED_CLIENT
+    } APP_BLE_ConnStatus_t;
+    
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */  
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APP_BLE_Init( void ); 
+
+  APP_BLE_ConnStatus_t APP_BLE_Get_Server_Connection_Status(void);
+
+/* USER CODE BEGIN EF */
+void APP_BLE_Key_Button1_Action(void);
+void APP_BLE_Key_Button2_Action(void);
+void APP_BLE_Key_Button3_Action(void);
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*APP_BLE_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/ble_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/ble_conf.h
new file mode 100644
index 000000000..2e0c37951
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/ble_conf.h
@@ -0,0 +1,104 @@
+/**
+ ******************************************************************************
+  * File Name          : App/ble_conf.h
+  * Description        : Configuration file for BLE Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef BLE_CONF_H
+#define BLE_CONF_H
+
+#include "app_conf.h"
+
+/******************************************************************************
+ *
+ * BLE SERVICES CONFIGURATION
+ * blesvc
+ *
+ ******************************************************************************/
+
+ /**
+ * This setting shall be set to '1' if the device needs to support the Peripheral Role
+ * In the MS configuration, both BLE_CFG_PERIPHERAL and BLE_CFG_CENTRAL shall be set to '1'
+ */
+#define BLE_CFG_PERIPHERAL                                                     1
+
+/**
+ * This setting shall be set to '1' if the device needs to support the Central Role
+ * In the MS configuration, both BLE_CFG_PERIPHERAL and BLE_CFG_CENTRAL shall be set to '1'
+ */
+#define BLE_CFG_CENTRAL                                                        0
+
+/**
+ * There is one handler per service enabled
+ * Note: There is no handler for the Device Information Service
+ *
+ * This shall take into account all registered handlers
+ * (from either the provided services or the custom services)
+ */
+#define BLE_CFG_SVC_MAX_NBR_CB                                                 7
+
+#define BLE_CFG_CLT_MAX_NBR_CB                                                 0
+
+/******************************************************************************
+ * Device Information Service (DIS)
+ ******************************************************************************/
+/**< Options: Supported(1) or Not Supported(0) */
+#define BLE_CFG_DIS_MANUFACTURER_NAME_STRING                                   1
+#define BLE_CFG_DIS_MODEL_NUMBER_STRING                                        0
+#define BLE_CFG_DIS_SERIAL_NUMBER_STRING                                       0
+#define BLE_CFG_DIS_HARDWARE_REVISION_STRING                                   0
+#define BLE_CFG_DIS_FIRMWARE_REVISION_STRING                                   0
+#define BLE_CFG_DIS_SOFTWARE_REVISION_STRING                                   0
+#define BLE_CFG_DIS_SYSTEM_ID                                                  0
+#define BLE_CFG_DIS_IEEE_CERTIFICATION                                         0
+#define BLE_CFG_DIS_PNP_ID                                                     0
+
+/**
+ * device information service characteristic lengths
+ */
+#define BLE_CFG_DIS_SYSTEM_ID_LEN_MAX                                        (8)
+#define BLE_CFG_DIS_MODEL_NUMBER_STRING_LEN_MAX                              (32)
+#define BLE_CFG_DIS_SERIAL_NUMBER_STRING_LEN_MAX                             (32)
+#define BLE_CFG_DIS_FIRMWARE_REVISION_STRING_LEN_MAX                         (32)
+#define BLE_CFG_DIS_HARDWARE_REVISION_STRING_LEN_MAX                         (32)
+#define BLE_CFG_DIS_SOFTWARE_REVISION_STRING_LEN_MAX                         (32)
+#define BLE_CFG_DIS_MANUFACTURER_NAME_STRING_LEN_MAX                         (32)
+#define BLE_CFG_DIS_IEEE_CERTIFICATION_LEN_MAX                               (32)
+#define BLE_CFG_DIS_PNP_ID_LEN_MAX                                           (7)
+
+/******************************************************************************
+ * Heart Rate Service (HRS)
+ ******************************************************************************/
+#define BLE_CFG_HRS_BODY_SENSOR_LOCATION_CHAR               1/**< BODY SENSOR LOCATION CHARACTERISTIC */
+#define BLE_CFG_HRS_ENERGY_EXPENDED_INFO_FLAG               1/**< ENERGY EXTENDED INFO FLAG */
+#define BLE_CFG_HRS_ENERGY_RR_INTERVAL_FLAG                 1/**< Max number of RR interval values - Shall not be greater than 9 */
+
+/******************************************************************************
+ * GAP Service - Apprearance
+ ******************************************************************************/
+
+#define BLE_CFG_UNKNOWN_APPEARANCE                  (0)
+#define BLE_CFG_HR_SENSOR_APPEARANCE                (832)
+#define BLE_CFG_GAP_APPEARANCE                      (BLE_CFG_HR_SENSOR_APPEARANCE)
+
+/******************************************************************************
+ * Over The Air Feature (OTA) - STM Proprietary
+ ******************************************************************************/
+#define BLE_CFG_OTA_REBOOT_CHAR         0/**< REBOOT OTA MODE CHARACTERISTIC */
+
+#endif /*BLE_CONF_H */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/ble_dbg_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/ble_dbg_conf.h
new file mode 100644
index 000000000..a24660c50
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/ble_dbg_conf.h
@@ -0,0 +1,199 @@
+/**
+ ******************************************************************************
+  * File Name          : App/ble_dbg_conf.h
+  * Description        : Debug configuration file for BLE Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __BLE_DBG_CONF_H
+#define __BLE_DBG_CONF_H
+
+/**
+ * Enable or Disable traces from BLE
+ */
+
+#define BLE_DBG_APP_EN             0
+#define BLE_DBG_DIS_EN             1
+#define BLE_DBG_HRS_EN             1
+#define BLE_DBG_SVCCTL_EN          1
+#define BLE_DBG_BLS_EN             0
+#define BLE_DBG_HTS_EN             0
+#define BLE_DBG_P2P_STM_EN         0
+
+/**
+ * Macro definition
+ */
+#if ( BLE_DBG_APP_EN != 0 )
+#define BLE_DBG_APP_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_APP_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_DIS_EN != 0 )
+#define BLE_DBG_DIS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_DIS_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_HRS_EN != 0 )
+#define BLE_DBG_HRS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HRS_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_P2P_STM_EN != 0 )
+#define BLE_DBG_P2P_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_P2P_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_TEMPLATE_STM_EN != 0 )
+#define BLE_DBG_TEMPLATE_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_TEMPLATE_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_EDS_STM_EN != 0 )
+#define BLE_DBG_EDS_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_EDS_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_LBS_STM_EN != 0 )
+#define BLE_DBG_LBS_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_LBS_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_SVCCTL_EN != 0 )
+#define BLE_DBG_SVCCTL_MSG          PRINT_MESG_DBG
+#else
+#define BLE_DBG_SVCCTL_MSG          PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_CTS_EN != 0)
+#define BLE_DBG_CTS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_CTS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HIDS_EN != 0)
+#define BLE_DBG_HIDS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_HIDS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_PASS_EN != 0)
+#define BLE_DBG_PASS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_PASS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_BLS_EN != 0)
+#define BLE_DBG_BLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_BLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HTS_EN != 0)
+#define BLE_DBG_HTS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HTS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_ANS_EN != 0)
+#define BLE_DBG_ANS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_ANS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_ESS_EN != 0)
+#define BLE_DBG_ESS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_ESS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_GLS_EN != 0)
+#define BLE_DBG_GLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_GLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_BAS_EN != 0)
+#define BLE_DBG_BAS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_BAS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_RTUS_EN != 0)
+#define BLE_DBG_RTUS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_RTUS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HPS_EN != 0)
+#define BLE_DBG_HPS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HPS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_TPS_EN != 0)
+#define BLE_DBG_TPS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_TPS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_LLS_EN != 0)
+#define BLE_DBG_LLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_LLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_IAS_EN != 0)
+#define BLE_DBG_IAS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_IAS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_WSS_EN != 0)
+#define BLE_DBG_WSS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_WSS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_LNS_EN != 0)
+#define BLE_DBG_LNS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_LNS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_SCPS_EN != 0)
+#define BLE_DBG_SCPS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_SCPS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_DTS_EN != 0)
+#define BLE_DBG_DTS_MSG             PRINT_MESG_DBG
+#define BLE_DBG_DTS_BUF             PRINT_LOG_BUFF_DBG
+#else
+#define BLE_DBG_DTS_MSG             PRINT_NO_MESG
+#define BLE_DBG_DTS_BUF             PRINT_NO_MESG
+#endif
+
+#endif /*__BLE_DBG_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/dis_app.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/dis_app.c
new file mode 100644
index 000000000..59c66fad3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/dis_app.c
@@ -0,0 +1,221 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    dis_app.c
+  * @author  MCD Application Team
+  * @brief   Device Information Service Application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "ble.h"
+#include "dis_app.h"
+
+/* Private includes -----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+#if ((BLE_CFG_DIS_SYSTEM_ID != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+static const uint8_t system_id[BLE_CFG_DIS_SYSTEM_ID_LEN_MAX] = 
+{
+  (uint8_t)((DISAPP_MANUFACTURER_ID & 0xFF0000) >> 16),
+  (uint8_t)((DISAPP_MANUFACTURER_ID & 0x00FF00) >> 8),
+  (uint8_t)(DISAPP_MANUFACTURER_ID & 0x0000FF),
+  0xFE,
+  0xFF,
+  (uint8_t)((DISAPP_OUI & 0xFF0000) >> 16),
+  (uint8_t)((DISAPP_OUI & 0x00FF00) >> 8),
+  (uint8_t)(DISAPP_OUI & 0x0000FF)
+};
+#endif
+
+#if ((BLE_CFG_DIS_IEEE_CERTIFICATION != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+static const uint8_t ieee_id[BLE_CFG_DIS_IEEE_CERTIFICATION_LEN_MAX] = 
+{
+  0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 
+  0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 
+  0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 
+  0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 
+};
+#endif
+#if ((BLE_CFG_DIS_PNP_ID != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+static const uint8_t pnp_id[BLE_CFG_DIS_PNP_ID_LEN_MAX] = 
+{
+  0x1,
+  0xAD, 0xDE,
+  0xDE, 0xDA, 
+  0x01, 0x00
+};
+#endif
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void DISAPP_Init(void)
+{
+/* USER CODE BEGIN DISAPP_Init */
+  DIS_Data_t dis_information_data;
+
+#if ((BLE_CFG_DIS_MANUFACTURER_NAME_STRING != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+  /**
+   * Update MANUFACTURER NAME Information
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t*)DISAPP_MANUFACTURER_NAME;
+  dis_information_data.Length = sizeof(DISAPP_MANUFACTURER_NAME);
+  DIS_UpdateChar(MANUFACTURER_NAME_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_MODEL_NUMBER_STRING != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+  /**
+   * Update MODEL NUMBERInformation
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t*)DISAPP_MODEL_NUMBER;
+  dis_information_data.Length = sizeof(DISAPP_MODEL_NUMBER);
+  DIS_UpdateChar(MODEL_NUMBER_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_SERIAL_NUMBER_STRING != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+  /**
+   * Update SERIAL NUMBERInformation
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t*)DISAPP_SERIAL_NUMBER;
+  dis_information_data.Length = sizeof(DISAPP_SERIAL_NUMBER);
+  DIS_UpdateChar(SERIAL_NUMBER_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_HARDWARE_REVISION_STRING != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+  /**
+   * Update HARDWARE REVISION NUMBERInformation
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t*)DISAPP_HARDWARE_REVISION_NUMBER;
+  dis_information_data.Length = sizeof(DISAPP_HARDWARE_REVISION_NUMBER);
+  DIS_UpdateChar(HARDWARE_REVISION_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_FIRMWARE_REVISION_STRING != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+  /**
+   * Update FIRMWARE REVISION NUMBERInformation
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t*)DISAPP_FIRMWARE_REVISION_NUMBER;
+  dis_information_data.Length = sizeof(DISAPP_FIRMWARE_REVISION_NUMBER);
+  DIS_UpdateChar(FIRMWARE_REVISION_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_SOFTWARE_REVISION_STRING != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+  /**
+   * Update SOFTWARE REVISION NUMBERInformation
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t*)DISAPP_SOFTWARE_REVISION_NUMBER;
+  dis_information_data.Length = sizeof(DISAPP_SOFTWARE_REVISION_NUMBER);
+  DIS_UpdateChar(SOFTWARE_REVISION_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_SYSTEM_ID != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+
+  /**
+   * Update SYSTEM ID Information
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t *)system_id;
+  dis_information_data.Length = BLE_CFG_DIS_SYSTEM_ID_LEN_MAX;
+  DIS_UpdateChar(SYSTEM_ID_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_IEEE_CERTIFICATION != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+
+  /**
+   * Update IEEE CERTIFICATION ID Information
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t *)ieee_id;
+  dis_information_data.Length = BLE_CFG_DIS_IEEE_CERTIFICATION_LEN_MAX;
+  DIS_UpdateChar(IEEE_CERTIFICATION_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_PNP_ID != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+
+  /**
+   * Update PNP ID Information
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t *)pnp_id;
+  dis_information_data.Length = BLE_CFG_DIS_PNP_ID_LEN_MAX;
+  DIS_UpdateChar(PNP_ID_UUID, &dis_information_data);
+#endif
+/* USER CODE END DISAPP_Init */
+}
+
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/dis_app.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/dis_app.h
new file mode 100644
index 000000000..196ec9937
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/dis_app.h
@@ -0,0 +1,77 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    dis_app.h
+  * @author  MCD Application Team
+  * @brief   Header for dis_application.c module
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __DIS_APP_H
+#define __DIS_APP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes -----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros -----------------------------------------------------------*/
+#define DISAPP_MANUFACTURER_NAME              "STM"
+#define DISAPP_MODEL_NUMBER                   "4502-1.0"
+#define DISAPP_SERIAL_NUMBER                  "1.0"
+#define DISAPP_HARDWARE_REVISION_NUMBER       "1.0"
+#define DISAPP_FIRMWARE_REVISION_NUMBER       "1.0"
+#define DISAPP_SOFTWARE_REVISION_NUMBER       "1.0"
+#define DISAPP_OUI                            0x123456
+#define DISAPP_MANUFACTURER_ID                0x9ABCDE
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ------------------------------------------------------- */
+void DISAPP_Init(void);
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__DIS_APP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/hrs_app.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/hrs_app.c
new file mode 100644
index 000000000..e3f77ee03
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/hrs_app.c
@@ -0,0 +1,256 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    hrs_app.c
+  * @author  MCD Application Team
+  * @brief   Heart Rate Service Application
+  ******************************************************************************
+  * @attention
+ *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+ * All rights reserved.
    
+ *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "ble.h"
+#include "hrs_app.h"
+#include "cmsis_os.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+typedef struct
+{
+  HRS_BodySensorLocation_t BodySensorLocationChar;
+  HRS_MeasVal_t MeasurementvalueChar;
+  uint8_t ResetEnergyExpended;
+  uint8_t TimerMeasurement_Id;
+
+} HRSAPP_Context_t;
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private defines ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+#define HRSAPP_MEASUREMENT_INTERVAL   (1000000/CFG_TS_TICK_VAL)  /**< 1s */
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/**
+ * START of Section BLE_APP_CONTEXT
+ */
+
+PLACE_IN_SECTION("BLE_APP_CONTEXT") static HRSAPP_Context_t HRSAPP_Context;
+
+/**
+ * END of Section BLE_APP_CONTEXT
+ */
+
+osThreadId_t HrsProcessId;
+
+const osThreadAttr_t HrsProcess_attr = {
+    .name = CFG_HRS_PROCESS_NAME,
+    .attr_bits = CFG_HRS_PROCESS_ATTR_BITS,
+    .cb_mem = CFG_HRS_PROCESS_CB_MEM,
+    .cb_size = CFG_HRS_PROCESS_CB_SIZE,
+    .stack_mem = CFG_HRS_PROCESS_STACK_MEM,
+    .priority = CFG_HRS_PROCESS_PRIORITY,
+    .stack_size = CFG_HRS_PROCESS_STACk_SIZE
+};
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private functions prototypes-----------------------------------------------*/
+static void HrMeas( void );
+static void HrsProcess(void *argument);
+static void HRSAPP_Measurement(void);
+static uint32_t HRSAPP_Read_RTC_SSR_SS ( void );
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void HRS_Notification(HRS_App_Notification_evt_t *pNotification)
+{
+/* USER CODE BEGIN HRS_Notification_1 */
+
+/* USER CODE END HRS_Notification_1 */
+  switch(pNotification->HRS_Evt_Opcode)
+  {
+/* USER CODE BEGIN HRS_Notification_HRS_Evt_Opcode */
+
+/* USER CODE END HRS_Notification_HRS_Evt_Opcode */
+#if (BLE_CFG_HRS_ENERGY_EXPENDED_INFO_FLAG != 0)
+    case HRS_RESET_ENERGY_EXPENDED_EVT:
+/* USER CODE BEGIN HRS_RESET_ENERGY_EXPENDED_EVT */
+      HRSAPP_Context.MeasurementvalueChar.EnergyExpended = 0;
+      HRSAPP_Context.ResetEnergyExpended = 1;
+/* USER CODE END HRS_RESET_ENERGY_EXPENDED_EVT */
+      break;
+#endif
+      
+    case HRS_NOTIFICATION_ENABLED:
+/* USER CODE BEGIN HRS_NOTIFICATION_ENABLED */
+      /**
+       * It could be the enable notification is received twice without the disable notification in between
+       */
+      HW_TS_Stop(HRSAPP_Context.TimerMeasurement_Id);
+      HW_TS_Start(HRSAPP_Context.TimerMeasurement_Id, HRSAPP_MEASUREMENT_INTERVAL);
+/* USER CODE END HRS_NOTIFICATION_ENABLED */
+      break;
+
+    case HRS_NOTIFICATION_DISABLED:
+/* USER CODE BEGIN HRS_NOTIFICATION_DISABLED */
+      HW_TS_Stop(HRSAPP_Context.TimerMeasurement_Id);
+/* USER CODE END HRS_NOTIFICATION_DISABLED */
+      break;
+      
+#if (BLE_CFG_OTA_REBOOT_CHAR != 0)
+    case HRS_STM_BOOT_REQUEST_EVT:
+/* USER CODE BEGIN HRS_STM_BOOT_REQUEST_EVT */
+      *(uint32_t*)SRAM1_BASE = *(uint32_t*)pNotification->DataTransfered.pPayload;
+      NVIC_SystemReset();
+/* USER CODE END HRS_STM_BOOT_REQUEST_EVT */
+      break;
+#endif
+      
+   default:
+/* USER CODE BEGIN HRS_Notification_Default */
+
+/* USER CODE END HRS_Notification_Default */
+      break;
+  }
+/* USER CODE BEGIN HRS_Notification_2 */
+
+/* USER CODE END HRS_Notification_2 */
+  return;
+}
+
+void HRSAPP_Init(void)
+{
+  HrsProcessId = osThreadNew(HrsProcess, NULL, &HrsProcess_attr);
+/* USER CODE BEGIN HRSAPP_Init */
+  /**
+   * Set Body Sensor Location
+   */
+  HRSAPP_Context.ResetEnergyExpended = 0;
+  HRSAPP_Context.BodySensorLocationChar = HRS_BODY_SENSOR_LOCATION_HAND;
+  HRS_UpdateChar(SENSOR_LOCATION_UUID, (uint8_t *)&HRSAPP_Context.BodySensorLocationChar);
+
+
+  /**
+   * Set Flags for measurement value
+   */
+
+  HRSAPP_Context.MeasurementvalueChar.Flags = ( HRS_HRM_VALUE_FORMAT_UINT16      | 
+                                                  HRS_HRM_SENSOR_CONTACTS_PRESENT   | 
+                                                  HRS_HRM_SENSOR_CONTACTS_SUPPORTED |
+                                                  HRS_HRM_ENERGY_EXPENDED_PRESENT  |
+                                                  HRS_HRM_RR_INTERVAL_PRESENT );
+
+#if (BLE_CFG_HRS_ENERGY_EXPENDED_INFO_FLAG != 0)
+  if(HRSAPP_Context.MeasurementvalueChar.Flags & HRS_HRM_ENERGY_EXPENDED_PRESENT)
+    HRSAPP_Context.MeasurementvalueChar.EnergyExpended = 10;
+#endif
+  
+#if (BLE_CFG_HRS_ENERGY_RR_INTERVAL_FLAG != 0)
+  if(HRSAPP_Context.MeasurementvalueChar.Flags & HRS_HRM_RR_INTERVAL_PRESENT)
+  {
+    uint8_t i;
+    
+    HRSAPP_Context.MeasurementvalueChar.NbreOfValidRRIntervalValues = BLE_CFG_HRS_ENERGY_RR_INTERVAL_FLAG;
+    for(i = 0; i < BLE_CFG_HRS_ENERGY_RR_INTERVAL_FLAG; i++)
+      HRSAPP_Context.MeasurementvalueChar.aRRIntervalValues[i] = 1024;
+  }
+#endif
+  
+  /**
+   * Create timer for Heart Rate Measurement
+   */
+  HW_TS_Create(CFG_TIM_PROC_ID_ISR, &(HRSAPP_Context.TimerMeasurement_Id), hw_ts_Repeated, HrMeas);
+
+/* USER CODE END HRSAPP_Init */
+  return;
+}
+
+static void HrsProcess(void *argument)
+{
+  UNUSED(argument);
+
+  for(;;)
+  {
+    osThreadFlagsWait( 1, osFlagsWaitAny, osWaitForever);
+    HRSAPP_Measurement( );
+  }
+}
+
+static void HRSAPP_Measurement(void)
+{
+/* USER CODE BEGIN HRSAPP_Measurement */
+  uint32_t measurement;
+
+  measurement = ((HRSAPP_Read_RTC_SSR_SS()) & 0x07) + 65;
+
+  HRSAPP_Context.MeasurementvalueChar.MeasurementValue = measurement;
+#if (BLE_CFG_HRS_ENERGY_EXPENDED_INFO_FLAG != 0)
+  if((HRSAPP_Context.MeasurementvalueChar.Flags & HRS_HRM_ENERGY_EXPENDED_PRESENT) &&
+     (HRSAPP_Context.ResetEnergyExpended == 0))
+    HRSAPP_Context.MeasurementvalueChar.EnergyExpended += 5;
+  else if(HRSAPP_Context.ResetEnergyExpended == 1)
+    HRSAPP_Context.ResetEnergyExpended = 0;
+#endif
+
+  HRS_UpdateChar(HEART_RATE_MEASURMENT_UUID, (uint8_t *)&HRSAPP_Context.MeasurementvalueChar);
+
+/* USER CODE END HRSAPP_Measurement */
+  return;
+}
+
+static void HrMeas( void )
+{
+  /**
+   * The code shall be executed in the background as aci command may be sent
+   * The background is the only place where the application can make sure a new aci command
+   * is not sent if there is a pending one
+   */
+  osThreadFlagsSet( HrsProcessId, 1 );
+  
+/* USER CODE BEGIN HrMeas */
+
+/* USER CODE END HrMeas */
+
+  return;
+}
+
+static uint32_t HRSAPP_Read_RTC_SSR_SS ( void )
+{
+  return ((uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS)));
+}
+
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/hrs_app.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/hrs_app.h
new file mode 100644
index 000000000..0246d2811
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/hrs_app.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    hrs_app.h
+  * @author  MCD Application Team
+  * @brief   Header for hrs_application.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HRS_APP_H
+#define __HRS_APP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+void HRSAPP_Init( void );
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__HRS_APP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/Target/hw_ipcc.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/Target/hw_ipcc.c
new file mode 100644
index 000000000..0f839543a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/Target/hw_ipcc.c
@@ -0,0 +1,523 @@
+/**
+ ******************************************************************************
+  * File Name          : Target/hw_ipcc.c
+  * Description        : Hardware IPCC source file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "mbox_def.h"
+
+/* Global variables ---------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+#define HW_IPCC_TX_PENDING( channel ) ( !(LL_C1_IPCC_IsActiveFlag_CHx( IPCC, channel )) ) &&  (((~(IPCC->C1MR)) & (channel << 16U)))
+#define HW_IPCC_RX_PENDING( channel )  (LL_C2_IPCC_IsActiveFlag_CHx( IPCC, channel )) && (((~(IPCC->C1MR)) & (channel << 0U)))
+
+/* Private macros ------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static void (*FreeBufCb)( void );
+
+/* Private function prototypes -----------------------------------------------*/
+static void HW_IPCC_BLE_EvtHandler( void );
+static void HW_IPCC_BLE_AclDataEvtHandler( void );
+static void HW_IPCC_MM_FreeBufHandler( void );
+static void HW_IPCC_SYS_CmdEvtHandler( void );
+static void HW_IPCC_SYS_EvtHandler( void );
+static void HW_IPCC_TRACES_EvtHandler( void );
+
+#ifdef THREAD_WB
+static void HW_IPCC_OT_CmdEvtHandler( void );
+static void HW_IPCC_THREAD_NotEvtHandler( void );
+static void HW_IPCC_THREAD_CliNotEvtHandler( void );
+#endif
+
+#ifdef MAC_802_15_4_WB
+static void HW_IPCC_MAC_802_15_4_CmdEvtHandler( void );
+static void HW_IPCC_MAC_802_15_4_NotEvtHandler( void );
+#endif
+
+#ifdef ZIGBEE_WB
+static void HW_IPCC_ZIGBEE_CmdEvtHandler( void );
+static void HW_IPCC_ZIGBEE_StackNotifEvtHandler( void );
+static void HW_IPCC_ZIGBEE_CliNotifEvtHandler( void );
+#endif
+
+/* Public function definition -----------------------------------------------*/
+
+/******************************************************************************
+ * INTERRUPT HANDLER
+ ******************************************************************************/
+void HW_IPCC_Rx_Handler( void )
+{
+  if (HW_IPCC_RX_PENDING( HW_IPCC_SYSTEM_EVENT_CHANNEL ))
+  {
+      HW_IPCC_SYS_EvtHandler();
+  }
+#ifdef MAC_802_15_4_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_MAC_802_15_4_NotEvtHandler();
+  }
+#endif /* MAC_802_15_4_WB */
+#ifdef THREAD_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_THREAD_NotEvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_THREAD_CliNotEvtHandler();
+  }
+#endif /* THREAD_WB */
+#ifdef ZIGBEE_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_ZIGBEE_StackNotifEvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
+  {
+      HW_IPCC_ZIGBEE_CliNotifEvtHandler();
+  }
+#endif /* ZIGBEE_WB */
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_BLE_EVENT_CHANNEL ))
+  {
+    HW_IPCC_BLE_EvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_TRACES_CHANNEL ))
+  {
+    HW_IPCC_TRACES_EvtHandler();
+  }
+
+  return;
+}
+
+void HW_IPCC_Tx_Handler( void )
+{
+  if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_SYS_CmdEvtHandler();
+  }
+#ifdef MAC_802_15_4_WB
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_MAC_802_15_4_CmdEvtHandler();
+  }
+#endif /* MAC_802_15_4_WB */
+#ifdef THREAD_WB
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_OT_CmdEvtHandler();
+  }
+#endif /* THREAD_WB */
+#ifdef ZIGBEE_WB
+  if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
+  {
+      HW_IPCC_ZIGBEE_CmdEvtHandler();
+  }
+#endif /* ZIGBEE_WB */
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_SYS_CmdEvtHandler();
+  }
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ))
+  {
+    HW_IPCC_MM_FreeBufHandler();
+  }
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_HCI_ACL_DATA_CHANNEL ))
+  {
+    HW_IPCC_BLE_AclDataEvtHandler();
+  }
+
+  return;
+}
+/******************************************************************************
+ * GENERAL
+ ******************************************************************************/
+void HW_IPCC_Enable( void )
+{
+  /**
+   * When the device is out of standby, it is required to use the EXTI mechanism to wakeup CPU2
+   */
+  LL_C2_EXTI_EnableEvent_32_63( LL_EXTI_LINE_41 );
+  LL_EXTI_EnableRisingTrig_32_63( LL_EXTI_LINE_41 );
+	
+  /**
+   * In case the SBSFU is implemented, it may have already set the C2BOOT bit to startup the CPU2.
+   * In that case, to keep the mechanism transparent to the user application, it shall call the system command
+   * SHCI_C2_Reinit( ) before jumping to the application.
+   * When the CPU2 receives that command, it waits for its event input to be set to restart the CPU2 firmware.
+   * This is required because once C2BOOT has been set once, a clear/set on C2BOOT has no effect.
+   * When SHCI_C2_Reinit( ) is not called, generating an event to the CPU2 does not have any effect
+   * So, by default, the application shall both set the event flag and set the C2BOOT bit.
+   */
+  __SEV( );       /* Set the internal event flag and send an event to the CPU2 */
+  __WFE( );       /* Clear the internal event flag */
+  LL_PWR_EnableBootC2( );
+
+  return;
+}
+
+void HW_IPCC_Init( void )
+{
+  LL_AHB3_GRP1_EnableClock( LL_AHB3_GRP1_PERIPH_IPCC );
+
+  LL_C1_IPCC_EnableIT_RXO( IPCC );
+  LL_C1_IPCC_EnableIT_TXF( IPCC );
+
+  HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn);
+  HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn);
+
+  return;
+}
+
+/******************************************************************************
+ * BLE
+ ******************************************************************************/
+void HW_IPCC_BLE_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_BLE_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_BLE_CMD_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_BLE_EvtHandler( void )
+{
+  HW_IPCC_BLE_RxEvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_BLE_SendAclData( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_BLE_AclDataEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+
+  HW_IPCC_BLE_AclDataAckNot();
+
+  return;
+}
+
+__weak void HW_IPCC_BLE_AclDataAckNot( void ){};
+__weak void HW_IPCC_BLE_RxEvtNot( void ){};
+
+/******************************************************************************
+ * SYSTEM
+ ******************************************************************************/
+void HW_IPCC_SYS_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_SYS_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_SYS_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+
+  HW_IPCC_SYS_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_SYS_EvtHandler( void )
+{
+  HW_IPCC_SYS_EvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
+
+  return;
+}
+
+__weak void HW_IPCC_SYS_CmdEvtNot( void ){};
+__weak void HW_IPCC_SYS_EvtNot( void ){};
+
+/******************************************************************************
+ * MAC 802.15.4
+ ******************************************************************************/
+#ifdef MAC_802_15_4_WB
+void HW_IPCC_MAC_802_15_4_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_MAC_802_15_4_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_MAC_802_15_4_SendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_MAC_802_15_4_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+
+  HW_IPCC_MAC_802_15_4_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_MAC_802_15_4_NotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_MAC_802_15_4_EvtNot();
+
+  return;
+}
+__weak void HW_IPCC_MAC_802_15_4_CmdEvtNot( void ){};
+__weak void HW_IPCC_MAC_802_15_4_EvtNot( void ){};
+#endif
+
+/******************************************************************************
+ * THREAD
+ ******************************************************************************/
+#ifdef THREAD_WB
+void HW_IPCC_THREAD_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_OT_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_CLI_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_THREAD_SendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_THREAD_CliSendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_OT_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  HW_IPCC_OT_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_THREAD_NotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_THREAD_EvtNot();
+
+  return;
+}
+
+static void HW_IPCC_THREAD_CliNotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_THREAD_CliEvtNot();
+
+  return;
+}
+
+__weak void HW_IPCC_OT_CmdEvtNot( void ){};
+__weak void HW_IPCC_CLI_CmdEvtNot( void ){};
+__weak void HW_IPCC_THREAD_EvtNot( void ){};
+
+#endif /* THREAD_WB */
+
+/******************************************************************************
+ * ZIGBEE
+ ******************************************************************************/
+#ifdef ZIGBEE_WB
+void HW_IPCC_ZIGBEE_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendAppliCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendCliCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
+
+   return;
+}
+
+void HW_IPCC_ZIGBEE_SendAppliCmdAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendCliCmdAck( void )
+{
+    LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+    LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_CmdEvtHandler( void )
+{
+    LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+    HW_IPCC_ZIGBEE_AppliCmdNotification();
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_StackNotifEvtHandler( void )
+{
+    LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+    HW_IPCC_ZIGBEE_AppliAsyncEvtNotification();
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_CliNotifEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_ZIGBEE_CliEvtNotification();
+
+  return;
+}
+
+__weak void HW_IPCC_ZIGBEE_AppliCmdNotification( void ){};
+__weak void HW_IPCC_ZIGBEE_AppliAsyncEvtNotification( void ){};
+__weak void HW_IPCC_ZIGBEE_CliEvtNotification( void ){};
+#endif /* ZIGBEE_WB */
+
+/******************************************************************************
+ * MEMORY MANAGER
+ ******************************************************************************/
+void HW_IPCC_MM_SendFreeBuf( void (*cb)( void ) )
+{
+  if ( LL_C1_IPCC_IsActiveFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ) )
+  {
+    FreeBufCb = cb;
+    LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+  }
+  else
+  {
+    cb();
+
+    LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+  }
+
+  return;
+}
+
+static void HW_IPCC_MM_FreeBufHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+
+  FreeBufCb();
+
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+
+  return;
+}
+
+/******************************************************************************
+ * TRACES
+ ******************************************************************************/
+void HW_IPCC_TRACES_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_TRACES_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_TRACES_EvtHandler( void )
+{
+  HW_IPCC_TRACES_EvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_TRACES_CHANNEL );
+
+  return;
+}
+
+__weak void HW_IPCC_TRACES_EvtNot( void ){};
+
+/******************* (C) COPYRIGHT 2019 STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/readme.txt b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/readme.txt
new file mode 100644
index 000000000..00076df27
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRateFreeRTOS/readme.txt
@@ -0,0 +1,108 @@
+/**
+  @page BLE_HeartRateFreeRTOSFreeRTOS example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    BLE/BLE_HeartRateFreeRTOS/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the BLE_HeartRateFreeRTOS example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                               www.st.com/SLA0044
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to use the Heart Rate profile as specified by the BLE SIG.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+      
+@note This application is not supported by CubeMx but has been copied from the project BLE_HeartRate generated
+      by CubeMx with some modifications to replace the call to the scheduler by the use of the cmsis_os interface
+
+@par Directory contents 
+  
+  - BLE/BLE_HeartRateFreeRTOS/Core/Inc/stm32wbxx_hal_conf.h		HAL configuration file
+  - BLE/BLE_HeartRateFreeRTOS/Core/Inc/stm32wbxx_it.h          	Interrupt handlers header file
+  - BLE/BLE_HeartRateFreeRTOS/Core/Inc/main.h                  	Header for main.c module
+  - BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/app_ble.h          Header for app_ble.c module
+  - BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_common.h            	Header for all modules with common definition
+  - BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_conf.h              	Parameters configuration file of the application
+  - BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_entry.h            	Parameters configuration file of the application
+  - BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/ble_conf.h         BLE Services configuration
+  - BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/ble_dbg_conf.h     BLE Traces configuration of the BLE services
+  - BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/dis_app.h          Header for dis_app.c module
+  - BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/hrs_app.h          Header for hrs_app.c module
+  - BLE/BLE_HeartRateFreeRTOS/Core/Inc/hw_conf.h           		Configuration file of the HW
+  - BLE/BLE_HeartRateFreeRTOS/Core/Inc/utilities_conf.h    		Configuration file of the utilities
+  - BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/FreeRTOSConfig.h   Configuration file of FreeRTOS
+  - BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32wbxx_it.c          	Interrupt handlers
+  - BLE/BLE_HeartRateFreeRTOS/Core/Src/main.c                  	Main program
+  - BLE/BLE_HeartRateFreeRTOS/Core/Src/system_stm32wbxx.c      	stm32wbxx system source file
+  - BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/app_ble.c      	BLE Profile implementation
+  - BLE/BLE_HeartRateFreeRTOS/Core/Src/app_entry.c      		Initialization of the application
+  - BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/dis_app.c      	Device Information Service application
+  - BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/hrs_app.c      	Heart Rate Service application
+  - BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/Target/hw_ipcc.c      	IPCC Driver
+  - BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32_lpm_if.c			Low Power Manager Interface
+  - BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_timerserver.c 		Timer Server based on RTC
+  - BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_uart.c 				UART Driver
+
+     
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35xx devices.
+  
+  - This example has been tested with an STMicroelectronics STM32WB35CE-Nucleo
+    board and can be easily tailored to any other supported device 
+    and development board.
+
+@par How to use it ? 
+
+This application requests having the stm32wb3x_BLE_Stack_fw.bin binary flashed on the Wireless Coprocessor.
+If it is not the case, you need to use STM32CubeProgrammer to load the appropriate binary.
+All available binaries are located under /Projects/STM32_Copro_Wireless_Binaries directory.
+Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the detailed procedure to change the
+Wireless Coprocessor binary.  
+
+In order to make the program work, you must do the following:
+ - Open your toolchain 
+ - Rebuild all files and flash the board with the executable file
+
+ On the android/ios device, enable the Bluetooth communications, and if not done before,
+ - Install the ST BLE Profile application on the android device
+	https://play.google.com/store/apps/details?id=com.stm.bluetoothlevalidation&hl=en
+    https://itunes.apple.com/fr/App/st-ble-profile/id1081331769?mt=8
+
+ - Install the ST BLE Sensor application on the ios/android device
+	https://play.google.com/store/apps/details?id=com.st.bluems
+	https://itunes.apple.com/us/App/st-bluems/id993670214?mt=8
+
+ - Power on the Nucleo board with the BLE_HeartRateFreeRTOS application
+ - Then, click on the App icon, ST BLE Sensor (android device)
+ - connect to a device
+ - select the HRSTM in the device list
+
+The Heart Rate is displayed each second on the android device.
+
+For more details refer to the Application Note: 
+  AN5289 - Building a Wireless application 
+ 
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
+ 
\ No newline at end of file
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Binary/BLE_HeartRate_ota.bin b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Binary/BLE_HeartRate_ota.bin
new file mode 100644
index 000000000..695a9eeee
Binary files /dev/null and b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Binary/BLE_HeartRate_ota.bin differ
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_common.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_common.h
new file mode 100644
index 000000000..4defc5d7a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_common.h
@@ -0,0 +1,114 @@
+/**
+ ******************************************************************************
+  * File Name          : app_common.h
+  * Description        : App Common application configuration file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_COMMON_H
+#define APP_COMMON_H
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "app_conf.h"
+
+  /* -------------------------------- *
+   *  Basic definitions               *
+   * -------------------------------- */
+
+#undef NULL
+#define NULL                    0
+
+#undef FALSE
+#define FALSE                   0
+
+#undef TRUE
+#define TRUE                    (!0)
+
+  /* -------------------------------- *
+   *  Critical Section definition     *
+   * -------------------------------- */
+#define BACKUP_PRIMASK()    uint32_t primask_bit= __get_PRIMASK()
+#define DISABLE_IRQ()       __disable_irq()
+#define RESTORE_PRIMASK()   __set_PRIMASK(primask_bit)
+
+  /* -------------------------------- *
+   *  Macro delimiters                *
+   * -------------------------------- */
+
+#define M_BEGIN     do {
+
+#define M_END       } while(0)
+
+  /* -------------------------------- *
+   *  Some useful macro definitions   *
+   * -------------------------------- */
+
+#define MAX( x, y )          (((x)>(y))?(x):(y))
+
+#define MIN( x, y )          (((x)<(y))?(x):(y))
+
+#define MODINC( a, m )       M_BEGIN  (a)++;  if ((a)>=(m)) (a)=0;  M_END
+
+#define MODDEC( a, m )       M_BEGIN  if ((a)==0) (a)=(m);  (a)--;  M_END
+
+#define MODADD( a, b, m )    M_BEGIN  (a)+=(b);  if ((a)>=(m)) (a)-=(m);  M_END
+
+#define MODSUB( a, b, m )    MODADD( a, (m)-(b), m )
+
+#define PAUSE( t )           M_BEGIN \
+                               __IO int _i; \
+                               for ( _i = t; _i > 0; _i -- ); \
+                             M_END
+
+#define DIVF( x, y )         ((x)/(y))
+
+#define DIVC( x, y )         (((x)+(y)-1)/(y))
+
+#define DIVR( x, y )         (((x)+((y)/2))/(y))
+
+#define SHRR( x, n )         ((((x)>>((n)-1))+1)>>1)
+
+#define BITN( w, n )         (((w)[(n)/32] >> ((n)%32)) & 1)
+
+#define BITNSET( w, n, b )   M_BEGIN (w)[(n)/32] |= ((U32)(b))<<((n)%32); M_END
+
+  /* -------------------------------- *
+   *  Compiler                         *
+   * -------------------------------- */
+#define PLACE_IN_SECTION( __x__ )  __attribute__((section (__x__)))
+
+#ifdef WIN32
+#define ALIGN(n)
+#else
+#define ALIGN(n)             __attribute__((aligned(n)))
+#endif
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*APP_COMMON_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_conf.h
new file mode 100644
index 000000000..6c3e16761
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_conf.h
@@ -0,0 +1,530 @@
+/**
+ ******************************************************************************
+  * File Name          : app_conf.h
+  * Description        : Application configuration file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_CONF_H
+#define APP_CONF_H
+
+#include "hw.h"
+#include "hw_conf.h"
+#include "hw_if.h"
+
+/******************************************************************************
+ * Application Config
+ ******************************************************************************/
+
+/**< generic parameters ******************************************************/
+
+/**
+ * Define Tx Power
+ */   
+#define CFG_TX_POWER                      (0x18) /**< 0dbm */
+
+/**
+ * Define Advertising parameters
+ */
+#define CFG_ADV_BD_ADDRESS                (0x7257acd87a6c)
+#define CFG_FAST_CONN_ADV_INTERVAL_MIN    (0x80)   /**< 80ms */
+#define CFG_FAST_CONN_ADV_INTERVAL_MAX    (0xa0)  /**< 100ms */
+#define CFG_LP_CONN_ADV_INTERVAL_MIN      (0x640) /**< 1s */
+#define CFG_LP_CONN_ADV_INTERVAL_MAX      (0xfa0) /**< 2.5s */
+
+/**
+ * Define IO Authentication
+ */
+#define CFG_BONDING_MODE                  (1)
+#define CFG_FIXED_PIN                     (111111)
+#define CFG_USED_FIXED_PIN                (0)
+#define CFG_ENCRYPTION_KEY_SIZE_MAX       (16)
+#define CFG_ENCRYPTION_KEY_SIZE_MIN       (8)
+
+/**
+ * Define IO capabilities
+ */
+#define CFG_IO_CAPABILITY_DISPLAY_ONLY       (0x00)
+#define CFG_IO_CAPABILITY_DISPLAY_YES_NO     (0x01)
+#define CFG_IO_CAPABILITY_KEYBOARD_ONLY      (0x02)
+#define CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT (0x03)
+#define CFG_IO_CAPABILITY_KEYBOARD_DISPLAY   (0x04)
+
+#define CFG_IO_CAPABILITY             CFG_IO_CAPABILITY_DISPLAY_YES_NO
+
+/**
+ * Define MITM modes
+ */
+#define CFG_MITM_PROTECTION_NOT_REQUIRED      (0x00)
+#define CFG_MITM_PROTECTION_REQUIRED          (0x01)
+
+#define CFG_MITM_PROTECTION             CFG_MITM_PROTECTION_REQUIRED
+
+/**
+ * Define PHY
+ */
+#define ALL_PHYS_PREFERENCE                             0x00
+#define RX_2M_PREFERRED                                 0x02
+#define TX_2M_PREFERRED                                 0x02
+#define TX_1M                                           0x01
+#define TX_2M                                           0x02
+#define RX_1M                                           0x01
+#define RX_2M                                           0x02 
+
+/**
+*   Identity root key used to derive LTK and CSRK
+*/
+#define CFG_BLE_IRK     {0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0,0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0}
+
+/**
+* Encryption root key used to derive LTK and CSRK
+*/
+#define CFG_BLE_ERK     {0xfe,0xdc,0xba,0x09,0x87,0x65,0x43,0x21,0xfe,0xdc,0xba,0x09,0x87,0x65,0x43,0x21}
+
+/* USER CODE BEGIN Generic_Parameters */
+/**
+ * SMPS supply
+ * SMPS not used when Set to 0
+ * SMPS used when Set to 1
+ */
+#define CFG_USE_SMPS    1
+/* USER CODE END Generic_Parameters */
+
+/**< specific parameters */
+/*****************************************************/
+/**
+* AD Element - Group B Feature
+*/ 
+/* LSB - Second Byte */
+#define CFG_FEATURE_OTA_REBOOT                  (0x20)
+
+/******************************************************************************
+ * BLE Stack
+ ******************************************************************************/
+/**
+ * Maximum number of simultaneous connections that the device will support.
+ * Valid values are from 1 to 8
+ */
+#define CFG_BLE_NUM_LINK            8
+
+/**
+ * Maximum number of Services that can be stored in the GATT database.
+ * Note that the GAP and GATT services are automatically added so this parameter should be 2 plus the number of user services
+ */
+#define CFG_BLE_NUM_GATT_SERVICES   8
+
+/**
+ * Maximum number of Attributes
+ * (i.e. the number of characteristic + the number of characteristic values + the number of descriptors, excluding the services)
+ * that can be stored in the GATT database.
+ * Note that certain characteristics and relative descriptors are added automatically during device initialization
+ * so this parameters should be 9 plus the number of user Attributes
+ */
+#define CFG_BLE_NUM_GATT_ATTRIBUTES 68
+
+/**
+ * Maximum supported ATT_MTU size
+ */
+#define CFG_BLE_MAX_ATT_MTU             (156)
+
+/**
+ * Size of the storage area for Attribute values
+ *  This value depends on the number of attributes used by application. In particular the sum of the following quantities (in octets) should be made for each attribute:
+ *  - attribute value length
+ *  - 5, if UUID is 16 bit; 19, if UUID is 128 bit
+ *  - 2, if server configuration descriptor is used
+ *  - 2*DTM_NUM_LINK, if client configuration descriptor is used
+ *  - 2, if extended properties is used
+ *  The total amount of memory needed is the sum of the above quantities for each attribute.
+ */
+#define CFG_BLE_ATT_VALUE_ARRAY_SIZE    (1344)
+
+/**
+ * Prepare Write List size in terms of number of packet with ATT_MTU=23 bytes
+ */
+#define CFG_BLE_PREPARE_WRITE_LIST_SIZE         ( 0x3A )
+
+/**
+ * Number of allocated memory blocks
+ */
+#define CFG_BLE_MBLOCK_COUNT            ( 0x79 )
+
+/**
+ * Enable or disable the Extended Packet length feature. Valid values are 0 or 1.
+ */
+#define CFG_BLE_DATA_LENGTH_EXTENSION   1
+
+/**
+ * Sleep clock accuracy in Slave mode (ppm value)
+ */
+#define CFG_BLE_SLAVE_SCA   500
+
+/**
+ * Sleep clock accuracy in Master mode
+ * 0 : 251 ppm to 500 ppm
+ * 1 : 151 ppm to 250 ppm
+ * 2 : 101 ppm to 150 ppm
+ * 3 : 76 ppm to 100 ppm
+ * 4 : 51 ppm to 75 ppm
+ * 5 : 31 ppm to 50 ppm
+ * 6 : 21 ppm to 30 ppm
+ * 7 : 0 ppm to 20 ppm
+ */
+#define CFG_BLE_MASTER_SCA   0
+
+/**
+ *  Source for the 32 kHz slow speed clock
+ *  1 : internal RO
+ *  0 : external crystal ( no calibration )
+ */
+#define CFG_BLE_LSE_SOURCE  0
+
+/**
+ * Start up time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us)
+ */
+#define CFG_BLE_HSE_STARTUP_TIME  0x148
+
+/**
+ * Maximum duration of the connection event when the device is in Slave mode in units of 625/256 us (~2.44 us)
+ */
+#define CFG_BLE_MAX_CONN_EVENT_LENGTH  ( 0xFFFFFFFF )
+
+/**
+ * Viterbi Mode
+ * 1 : enabled
+ * 0 : disabled
+ */
+#define CFG_BLE_VITERBI_MODE  1
+
+/**
+ *  LL Only Mode
+ *  1 : LL Only
+ *  0 : LL + Host
+ */
+#define CFG_BLE_LL_ONLY  0
+/******************************************************************************
+ * Transport Layer
+ ******************************************************************************/
+/**
+ * Queue length of BLE Event
+ * This parameter defines the number of asynchronous events that can be stored in the HCI layer before
+ * being reported to the application. When a command is sent to the BLE core coprocessor, the HCI layer
+ * is waiting for the event with the Num_HCI_Command_Packets set to 1. The receive queue shall be large
+ * enough to store all asynchronous events received in between.
+ * When CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE is set to 27, this allow to store three 255 bytes long asynchronous events
+ * between the HCI command and its event.
+ * This parameter depends on the value given to CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE. When the queue size is to small,
+ * the system may hang if the queue is full with asynchronous events and the HCI layer is still waiting
+ * for a CC/CS event, In that case, the notification TL_BLE_HCI_ToNot() is called to indicate
+ * to the application a HCI command did not receive its command event within 30s (Default HCI Timeout).
+ */
+#define CFG_TLBLE_EVT_QUEUE_LENGTH 5
+/**
+ * This parameter should be set to fit most events received by the HCI layer. It defines the buffer size of each element
+ * allocated in the queue of received events and can be used to optimize the amount of RAM allocated by the Memory Manager.
+ * It should not exceed 255 which is the maximum HCI packet payload size (a greater value is a lost of memory as it will
+ * never be used)
+ * It shall be at least 4 to receive the command status event in one frame.
+ * The default value is set to 27 to allow receiving an event of MTU size in a single buffer. This value maybe reduced
+ * further depending on the application.
+ *
+ */
+#define CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE 255   /**< Set to 255 with the memory manager and the mailbox */
+
+#define TL_BLE_EVENT_FRAME_SIZE ( TL_EVT_HDR_SIZE + CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE )
+/******************************************************************************
+ * UART interfaces
+ ******************************************************************************/
+
+/**
+ * Select UART interfaces
+ */
+#define CFG_DEBUG_TRACE_UART    hw_uart1
+#define CFG_CONSOLE_MENU      
+/******************************************************************************
+ * USB interface
+ ******************************************************************************/
+
+/**
+ * Enable/Disable USB interface
+ */
+#define CFG_USB_INTERFACE_ENABLE    0
+
+/******************************************************************************
+ * Low Power
+ ******************************************************************************/
+/**
+ *  When set to 1, the low power mode is enable
+ *  When set to 0, the device stays in RUN mode
+ */
+#define CFG_LPM_SUPPORTED    1
+
+/******************************************************************************
+ * Timer Server
+ ******************************************************************************/
+/**
+ *  CFG_RTC_WUCKSEL_DIVIDER:  This sets the RTCCLK divider to the wakeup timer.
+ *  The higher is the value, the better is the power consumption and the accuracy of the timerserver
+ *  The lower is the value, the finest is the granularity
+ *
+ *  CFG_RTC_ASYNCH_PRESCALER: This sets the asynchronous prescaler of the RTC. It should as high as possible ( to ouput
+ *  clock as low as possible) but the output clock should be equal or higher frequency compare to the clock feeding
+ *  the wakeup timer. A lower clock speed would impact the accuracy of the timer server.
+ *
+ *  CFG_RTC_SYNCH_PRESCALER: This sets the synchronous prescaler of the RTC.
+ *  When the 1Hz calendar clock is required, it shall be sets according to other settings
+ *  When the 1Hz calendar clock is not needed, CFG_RTC_SYNCH_PRESCALER should be set to 0x7FFF (MAX VALUE)
+ *
+ *  CFG_RTCCLK_DIVIDER_CONF:
+ *  Shall be set to either 0,2,4,8,16
+ *  When set to either 2,4,8,16, the 1Hhz calendar is supported
+ *  When set to 0, the user sets its own configuration
+ *
+ *  The following settings are computed with LSI as input to the RTC
+ */
+#define CFG_RTCCLK_DIVIDER_CONF 0
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 0)
+/**
+ * Custom configuration
+ * It does not support 1Hz calendar
+ * It divides the RTC CLK by 16
+ */
+#define CFG_RTCCLK_DIV  (16)
+#define CFG_RTC_WUCKSEL_DIVIDER (0)
+#define CFG_RTC_ASYNCH_PRESCALER (CFG_RTCCLK_DIV - 1)
+#define CFG_RTC_SYNCH_PRESCALER (0x7FFF)
+
+#else
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 2)
+/**
+ * It divides the RTC CLK by 2
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (3)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 4)
+/**
+ * It divides the RTC CLK by 4
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (2)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 8)
+/**
+ * It divides the RTC CLK by 8
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (1)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 16)
+/**
+ * It divides the RTC CLK by 16
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (0)
+#endif
+
+#define CFG_RTCCLK_DIV              CFG_RTCCLK_DIVIDER_CONF
+#define CFG_RTC_ASYNCH_PRESCALER    (CFG_RTCCLK_DIV - 1)
+#define CFG_RTC_SYNCH_PRESCALER     (DIVR( LSE_VALUE, (CFG_RTC_ASYNCH_PRESCALER+1) ) - 1 )
+
+#endif
+
+/** tick timer value in us */
+#define CFG_TS_TICK_VAL           DIVR( (CFG_RTCCLK_DIV * 1000000), LSE_VALUE )
+
+typedef enum
+{
+    CFG_TIM_PROC_ID_ISR,
+} CFG_TimProcID_t;
+
+/******************************************************************************
+ * Debug
+ ******************************************************************************/
+/**
+ * When set, this resets some hw resources to set the device in the same state than the power up
+ * The FW resets only register that may prevent the FW to run properly
+ *
+ * This shall be set to 0 in a final product
+ *
+ */
+#define CFG_HW_RESET_BY_FW         1
+
+/**
+ * keep debugger enabled while in any low power mode when set to 1
+ * should be set to 0 in production
+ */
+#define CFG_DEBUGGER_SUPPORTED    0
+
+/**
+ * When set to 1, the traces are enabled in the BLE services
+ */
+#define CFG_DEBUG_BLE_TRACE     0
+
+/**
+ * Enable or Disable traces in application
+ */
+#define CFG_DEBUG_APP_TRACE     0
+
+#if (CFG_DEBUG_APP_TRACE != 0)
+#define APP_DBG_MSG                 PRINT_MESG_DBG
+#else
+#define APP_DBG_MSG                 PRINT_NO_MESG
+#endif
+
+#if ( (CFG_DEBUG_BLE_TRACE != 0) || (CFG_DEBUG_APP_TRACE != 0) )
+#define CFG_DEBUG_TRACE             1
+#endif
+
+#if (CFG_DEBUG_TRACE != 0)
+#undef CFG_LPM_SUPPORTED
+#undef CFG_DEBUGGER_SUPPORTED
+#define CFG_LPM_SUPPORTED         0
+#define CFG_DEBUGGER_SUPPORTED      1
+#endif
+
+/**
+ * When CFG_DEBUG_TRACE_FULL is set to 1, the trace are output with the API name, the file name and the line number
+ * When CFG_DEBUG_TRACE_LIGHT is set to 1, only the debug message is output
+ *
+ * When both are set to 0, no trace are output
+ * When both are set to 1,  CFG_DEBUG_TRACE_FULL is selected
+ */
+#define CFG_DEBUG_TRACE_LIGHT     1
+#define CFG_DEBUG_TRACE_FULL      0
+
+#if (( CFG_DEBUG_TRACE != 0 ) && ( CFG_DEBUG_TRACE_LIGHT == 0 ) && (CFG_DEBUG_TRACE_FULL == 0))
+#undef CFG_DEBUG_TRACE_FULL
+#undef CFG_DEBUG_TRACE_LIGHT
+#define CFG_DEBUG_TRACE_FULL      0
+#define CFG_DEBUG_TRACE_LIGHT     1
+#endif
+
+#if ( CFG_DEBUG_TRACE == 0 )
+#undef CFG_DEBUG_TRACE_FULL
+#undef CFG_DEBUG_TRACE_LIGHT
+#define CFG_DEBUG_TRACE_FULL      0
+#define CFG_DEBUG_TRACE_LIGHT     0
+#endif
+
+/**
+ * When not set, the traces is looping on sending the trace over UART
+ */
+#define DBG_TRACE_USE_CIRCULAR_QUEUE 1
+
+/**
+ * max buffer Size to queue data traces and max data trace allowed.
+ * Only Used if DBG_TRACE_USE_CIRCULAR_QUEUE is defined
+ */
+#define DBG_TRACE_MSG_QUEUE_SIZE 4096
+#define MAX_DBG_TRACE_MSG_SIZE 1024
+
+/* USER CODE BEGIN Defines */
+#define CFG_LED_SUPPORTED         0
+#define CFG_BUTTON_SUPPORTED      1
+
+#ifdef LITTLE_DORY
+#define PUSH_BUTTON_SW1_EXTI_IRQHandler                         EXTI0_IRQHandler
+#define PUSH_BUTTON_SW2_EXTI_IRQHandler                         EXTI4_IRQHandler
+#define PUSH_BUTTON_SW3_EXTI_IRQHandler                         EXTI9_5_IRQHandler
+#else
+#define PUSH_BUTTON_SW1_EXTI_IRQHandler                         EXTI4_IRQHandler
+#define PUSH_BUTTON_SW2_EXTI_IRQHandler                         EXTI0_IRQHandler
+#define PUSH_BUTTON_SW3_EXTI_IRQHandler                         EXTI1_IRQHandler
+#endif
+/* USER CODE END Defines */
+
+/******************************************************************************
+ * Scheduler
+ ******************************************************************************/
+
+/**
+ * These are the lists of task id registered to the scheduler
+ * Each task id shall be in the range [0:31]
+ * This mechanism allows to implement a generic code in the API TL_BLE_HCI_StatusNot() to comply with
+ * the requirement that a HCI/ACI command shall never be sent if there is already one pending
+ */
+
+/**< Add in that list all tasks that may send a ACI/HCI command */
+typedef enum
+{
+    CFG_TASK_ADV_UPDATE_ID,
+    CFG_TASK_MEAS_REQ_ID,
+    CFG_TASK_HCI_ASYNCH_EVT_ID,
+/* USER CODE BEGIN CFG_Task_Id_With_HCI_Cmd_t */
+
+/* USER CODE END CFG_Task_Id_With_HCI_Cmd_t */
+    CFG_LAST_TASK_ID_WITH_HCICMD,                                               /**< Shall be LAST in the list */
+} CFG_Task_Id_With_HCI_Cmd_t;
+
+/**< Add in that list all tasks that never send a ACI/HCI command */
+typedef enum
+{
+    CFG_FIRST_TASK_ID_WITH_NO_HCICMD = CFG_LAST_TASK_ID_WITH_HCICMD - 1,        /**< Shall be FIRST in the list */
+    CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID,
+/* USER CODE BEGIN CFG_Task_Id_With_NO_HCI_Cmd_t */
+
+/* USER CODE END CFG_Task_Id_With_NO_HCI_Cmd_t */
+    CFG_LAST_TASK_ID_WITHO_NO_HCICMD                                            /**< Shall be LAST in the list */
+} CFG_Task_Id_With_NO_HCI_Cmd_t;
+#define CFG_TASK_NBR    CFG_LAST_TASK_ID_WITHO_NO_HCICMD
+
+/**
+ * This is the list of priority required by the application
+ * Each Id shall be in the range 0..31
+ */
+typedef enum
+{
+    CFG_SCH_PRIO_0,
+    CFG_PRIO_NBR,
+} CFG_SCH_Prio_Id_t;
+
+/**
+ * This is a bit mapping over 32bits listing all events id supported in the application
+ */
+typedef enum
+{
+    CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID,
+    CFG_IDLEEVT_SYSTEM_HCI_CMD_EVT_RSP_ID,
+} CFG_IdleEvt_Id_t;
+
+/******************************************************************************
+ * LOW POWER
+ ******************************************************************************/
+/**
+ * Supported requester to the MCU Low Power Manager - can be increased up  to 32
+ * It lits a bit mapping of all user of the Low Power Manager
+ */
+typedef enum
+{
+    CFG_LPM_APP,
+    CFG_LPM_APP_BLE,
+  /* USER CODE BEGIN CFG_LPM_Id_t */
+
+  /* USER CODE END CFG_LPM_Id_t */
+} CFG_LPM_Id_t;
+
+/******************************************************************************
+ * OTP manager
+ ******************************************************************************/
+#define CFG_OTP_BASE_ADDRESS    OTP_AREA_BASE
+
+#define CFG_OTP_END_ADRESS      OTP_AREA_END_ADDR
+
+#endif /*APP_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_debug.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_debug.h
new file mode 100644
index 000000000..13485c16b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_debug.h
@@ -0,0 +1,45 @@
+
+/**
+  ******************************************************************************
+  * @file    app_debug.h
+  * @author  MCD Application Team
+  * @brief   Interface to support debug in the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+  /* Exported types ------------------------------------------------------------*/
+  /* Exported constants --------------------------------------------------------*/
+  /* External variables --------------------------------------------------------*/
+  /* Exported macros -----------------------------------------------------------*/
+  /* Exported functions ------------------------------------------------------- */
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_entry.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_entry.h
new file mode 100644
index 000000000..77ead2384
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_entry.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    app_entry.h
+  * @author  MCD Application Team
+  * @brief   Interface to the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_ENTRY_H
+#define APP_ENTRY_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APPE_Init( void );
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*APP_ENTRY_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/hw_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/hw_conf.h
new file mode 100644
index 000000000..f4f55affa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/hw_conf.h
@@ -0,0 +1,196 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : hw_conf.h
+  * Description        : Hardware configuration file for BLE 
+  *                      middleWare.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef HW_CONF_H
+#define HW_CONF_H
+
+/******************************************************************************
+* Semaphores
+* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
+*****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
+/* Index of the semaphore used to manage the entry Stop Mode procedure */
+#define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
+
+/* Index of the semaphore used to access the RCC */
+#define CFG_HW_RCC_SEMID                                        3
+
+/* Index of the semaphore used to access the FLASH */
+#define CFG_HW_FLASH_SEMID                                      2
+
+/* Index of the semaphore used to access the PKA */
+#define CFG_HW_PKA_SEMID                                        1
+
+/* Index of the semaphore used to access the RNG */
+#define CFG_HW_RNG_SEMID                                        0
+
+/******************************************************************************
+ * HW TIMER SERVER
+ *****************************************************************************/
+/**
+ * The user may define the maximum number of virtual timers supported.
+ * It shall not exceed 255
+ */
+#define CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER  6
+
+/**
+ * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
+ * wakeup timer.
+ * This setting is the preemptpriority part of the NVIC.
+ */
+#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO  3
+
+/**
+ * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
+ * wakeup timer.
+ * This setting is the subpriority part of the NVIC. It does not exist on all processors. When it is not supported
+ * on the CPU, the setting is ignored
+ */
+#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO  0
+
+/**
+ *  Define a critical section in the Timer server
+ *  The Timer server does not support the API to be nested
+ *  The  Application shall either:
+ *    a) Ensure this will never happen
+ *    b) Define the critical section
+ *  The default implementations is masking all interrupts using the PRIMASK bit
+ *  The TimerServer driver uses critical sections to avoid context corruption. This is achieved with the macro
+ *  TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION. When CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION is set
+ *  to 1, all STM32 interrupts are masked with the PRIMASK bit of the CortexM CPU. It is possible to use the BASEPRI
+ *  register of the CortexM CPU to keep allowed some interrupts with high priority. In that case, the user shall
+ *  re-implement TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION and shall make sure that no TimerServer
+ *  API are called when the TIMER critical section is entered
+ */
+#define CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION  1
+
+/**
+   * This value shall reflect the maximum delay there could be in the application between the time the RTC interrupt
+   * is generated by the Hardware and the time when the  RTC interrupt handler is called. This time is measured in
+   * number of RTCCLK ticks.
+   * A relaxed timing would be 10ms
+   * When the value is too short, the timerserver will not be able to count properly and all timeout may be random.
+   * When the value is too long, the device may wake up more often than the most optimal configuration. However, the
+   * impact on power consumption would be marginal (unless the value selected is extremely too long). It is strongly
+   * recommended to select a value large enough to make sure it is not too short to ensure reliability of the system
+   * as this will have marginal impact on low power mode
+   */
+#define CFG_HW_TS_RTC_HANDLER_MAX_DELAY  ( 10 * (LSI_VALUE/1000) )
+
+  /**
+   * Interrupt ID in the NVIC of the RTC Wakeup interrupt handler
+   * It shall be type of IRQn_Type
+   */
+#define CFG_HW_TS_RTC_WAKEUP_HANDLER_ID  RTC_WKUP_IRQn
+
+/******************************************************************************
+ * HW UART
+ *****************************************************************************/
+
+#define CFG_HW_LPUART1_ENABLED           0
+#define CFG_HW_LPUART1_DMA_TX_SUPPORTED  0
+
+#define CFG_HW_USART1_ENABLED           1
+#define CFG_HW_USART1_DMA_TX_SUPPORTED  1
+
+/**
+ * UART1
+ */
+#define CFG_HW_USART1_PREEMPTPRIORITY         0x0F
+#define CFG_HW_USART1_SUBPRIORITY             0
+
+/** < The application shall check the selected source clock is enable */
+#define CFG_HW_USART1_SOURCE_CLOCK              RCC_USART1CLKSOURCE_SYSCLK
+
+#define CFG_HW_USART1_BAUDRATE                115200
+#define CFG_HW_USART1_WORDLENGTH              UART_WORDLENGTH_8B
+#define CFG_HW_USART1_STOPBITS                UART_STOPBITS_1
+#define CFG_HW_USART1_PARITY                  UART_PARITY_NONE
+#define CFG_HW_USART1_HWFLOWCTL               UART_HWCONTROL_NONE
+#define CFG_HW_USART1_MODE                    UART_MODE_TX_RX
+#define CFG_HW_USART1_ADVFEATUREINIT          UART_ADVFEATURE_NO_INIT
+#define CFG_HW_USART1_OVERSAMPLING            UART_OVERSAMPLING_8
+
+#define CFG_HW_USART1_TX_PORT_CLK_ENABLE      __HAL_RCC_GPIOB_CLK_ENABLE
+#define CFG_HW_USART1_TX_PORT                 GPIOB
+#define CFG_HW_USART1_TX_PIN                  GPIO_PIN_6
+#define CFG_HW_USART1_TX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_USART1_TX_PULL                 GPIO_NOPULL
+#define CFG_HW_USART1_TX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_TX_ALTERNATE            GPIO_AF7_USART1
+
+#define CFG_HW_USART1_RX_PORT_CLK_ENABLE      __HAL_RCC_GPIOB_CLK_ENABLE
+#define CFG_HW_USART1_RX_PORT                 GPIOB
+#define CFG_HW_USART1_RX_PIN                  GPIO_PIN_7
+#define CFG_HW_USART1_RX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_USART1_RX_PULL                 GPIO_NOPULL
+#define CFG_HW_USART1_RX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_RX_ALTERNATE            GPIO_AF7_USART1
+
+#define CFG_HW_USART1_CTS_PORT_CLK_ENABLE     __HAL_RCC_GPIOA_CLK_ENABLE
+#define CFG_HW_USART1_CTS_PORT                GPIOA
+#define CFG_HW_USART1_CTS_PIN                 GPIO_PIN_11
+#define CFG_HW_USART1_CTS_MODE                GPIO_MODE_AF_PP
+#define CFG_HW_USART1_CTS_PULL                GPIO_PULLDOWN
+#define CFG_HW_USART1_CTS_SPEED               GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_CTS_ALTERNATE           GPIO_AF7_USART1
+
+#define CFG_HW_USART1_DMA_TX_PREEMPTPRIORITY  0x0F
+#define CFG_HW_USART1_DMA_TX_SUBPRIORITY      0
+
+#define CFG_HW_USART1_DMAMUX_CLK_ENABLE       __HAL_RCC_DMAMUX1_CLK_ENABLE
+#define CFG_HW_USART1_DMA_CLK_ENABLE          __HAL_RCC_DMA2_CLK_ENABLE
+#define CFG_HW_USART1_TX_DMA_REQ			  DMA_REQUEST_USART1_TX
+#define CFG_HW_USART1_TX_DMA_CHANNEL          DMA2_CHANNEL_4
+#define CFG_HW_USART1_TX_DMA_IRQn             DMA2_CHANNEL_4_IRQn
+#define CFG_HW_USART1_DMA_TX_IRQHandler       DMA2_CHANNEL_4_IRQHandler
+
+#endif /*HW_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/hw_if.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/hw_if.h
new file mode 100644
index 000000000..5a15665ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/hw_if.h
@@ -0,0 +1,254 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    hw_if.h
+  * @author  MCD Application Team
+  * @brief   Hardware Interface
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef HW_IF_H
+#define HW_IF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_ipcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_hsem.h"
+#include "stm32wbxx_ll_gpio.h"
+#include "stm32wbxx_ll_rtc.h"
+
+#ifdef  USE_STM32WBXX_USB_DONGLE
+#include "stm32wbxx_usb_dongle.h"
+#endif
+#ifdef  USE_STM32WBXX_NUCLEO
+  #ifdef STM32WB35xx
+  #include "nucleo_wb35ce.h"
+  #else
+  #include "stm32wbxx_nucleo.h"
+  #endif
+#endif
+#ifdef  USE_X_NUCLEO_EPD
+#include "x_nucleo_epd.h"
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /******************************************************************************
+   * HW UART
+   ******************************************************************************/
+  typedef enum
+  {
+    hw_uart1,
+    hw_uart2,
+    hw_lpuart1,
+  } hw_uart_id_t;
+
+  typedef enum
+  {
+    hw_uart_ok,
+    hw_uart_error,
+    hw_uart_busy,
+    hw_uart_to,
+  } hw_status_t;
+
+  void HW_UART_Init(hw_uart_id_t hw_uart_id);
+  void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *pData, uint16_t Size, void (*Callback)(void));
+  void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *pData, uint16_t Size,  void (*Callback)(void));
+  hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout);
+  hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*Callback)(void));
+  void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id);
+  void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id);
+
+  /******************************************************************************
+   * HW TimerServer
+   ******************************************************************************/
+  /* Exported types ------------------------------------------------------------*/
+  /**
+   * This setting is used when standby mode is supported.
+   * hw_ts_InitMode_Limited should be used when the device restarts from Standby Mode. In that case, the Timer Server does
+   * not re-initialized its context. Only the Hardware register which content has been lost is reconfigured
+   * Otherwise, hw_ts_InitMode_Full should be requested (Start from Power ON) and everything is re-initialized.
+   */
+  typedef enum
+  {
+    hw_ts_InitMode_Full,
+    hw_ts_InitMode_Limited,
+  } HW_TS_InitMode_t;
+
+  /**
+   * When a Timer is created as a SingleShot timer, it is not automatically restarted when the timeout occurs. However,
+   * the timer is kept reserved in the list and could be restarted at anytime with HW_TS_Start()
+   *
+   * When a Timer is created as a Repeated timer, it is automatically restarted when the timeout occurs.
+   */
+  typedef enum
+  {
+    hw_ts_SingleShot,
+    hw_ts_Repeated
+  } HW_TS_Mode_t;
+
+  /**
+   * hw_ts_Successful is returned when a Timer has been successfully created with HW_TS_Create(). Otherwise, hw_ts_Failed
+   * is returned. When hw_ts_Failed is returned, that means there are not enough free slots in the list to create a
+   * Timer. In that case, CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER should be increased
+   */
+  typedef enum
+  {
+    hw_ts_Successful,
+    hw_ts_Failed,
+  }HW_TS_ReturnStatus_t;
+
+  typedef void (*HW_TS_pTimerCb_t)(void);
+
+  /**
+   * @brief  Initialize the timer server
+   *         This API shall be called by the application before any timer is requested to the timer server. It
+   *         configures the RTC module to be connected to the LSI input clock.
+   *
+   * @param  TimerInitMode: When the device restarts from Standby, it should request hw_ts_InitMode_Limited so that the
+   *         Timer context is not re-initialized. Otherwise, hw_ts_InitMode_Full should be requested
+   * @param  hrtc: RTC Handle
+   * @retval None
+   */
+  void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *hrtc);
+
+  /**
+   * @brief  Interface to create a virtual timer
+   *         The user shall call this API to create a timer. Once created, the timer is reserved to the module until it
+   *         has been deleted. When creating a timer, the user shall specify the mode (single shot or repeated), the
+   *         callback to be notified when the timer expires and a module ID to identify in the timer interrupt handler
+   *         which module is concerned. In return, the user gets a timer ID to handle it.
+   *
+   * @param  TimerProcessID:  This is an identifier provided by the user and returned in the callback to allow
+   *                          identification of the requester
+   * @param  pTimerId: Timer Id returned to the user to request operation (start, stop, delete)
+   * @param  TimerMode: Mode of the virtual timer (Single shot or repeated)
+   * @param  pTimerCallBack: Callback when the virtual timer expires
+   * @retval HW_TS_ReturnStatus_t: Return whether the creation is sucessfull or not
+   */
+  HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pTimerCallBack);
+
+  /**
+   * @brief  Stop a virtual timer
+   *         This API may be used to stop a running timer. A timer which is stopped is move to the pending state.
+   *         A pending timer may be restarted at any time with a different timeout value but the mode cannot be changed.
+   *         Nothing is done when it is called to stop a timer which has been already stopped
+   *
+   * @param  TimerID:  Id of the timer to stop
+   * @retval None
+   */
+  void HW_TS_Stop(uint8_t TimerID);
+
+  /**
+   * @brief  Start a virtual timer
+   *         This API shall be used to start a timer. The timeout value is specified and may be different each time.
+   *         When the timer is in the single shot mode, it will move to the pending state when it expires. The user may
+   *         restart it at any time with a different timeout value. When the timer is in the repeated mode, it always
+   *         stay in the running state. When the timer expires, it will be restarted with the same timeout value.
+   *         This API shall not be called on a running timer.
+   *
+   * @param  TimerID:  The ID Id of the timer to start
+   * @param  timeout_ticks: Number of ticks of the virtual timer (Maximum value is (0xFFFFFFFF-0xFFFF = 0xFFFF0000)
+   * @retval None
+   */
+  void HW_TS_Start(uint8_t TimerID, uint32_t timeout_ticks);
+
+  /**
+   * @brief  Delete a virtual timer from the list
+   *         This API should be used when a timer is not needed anymore by the user. A deleted timer is removed from
+   *         the timer list managed by the timer server. It cannot be restarted again. The user has to go with the
+   *         creation of a new timer if required and may get a different timer id
+   *
+   * @param  TimerID:  The ID of the timer to remove from the list
+   * @retval None
+   */
+  void HW_TS_Delete(uint8_t TimerID);
+
+  /**
+   * @brief  Schedule the timer list on the timer interrupt handler
+   *         This interrupt handler shall be called by the application in the RTC interrupt handler. This handler takes
+   *         care of clearing all status flag required in the RTC and EXTI peripherals
+   *
+   * @param  None
+   * @retval None
+   */
+  void HW_TS_RTC_Wakeup_Handler(void);
+
+  /**
+   * @brief  Return the number of ticks to count before the interrupt
+   *         This API returns the number of ticks left to be counted before an interrupt is generated by the
+   *         Timer Server. This API may be used by the application for power management optimization. When the system
+   *         enters low power mode, the mode selection is a tradeoff between the wakeup time where the CPU is running
+   *         and the time while the CPU will be kept in low power mode before next wakeup. The deeper is the
+   *         low power mode used, the longer is the wakeup time. The low power mode management considering wakeup time
+   *         versus time in low power mode is implementation specific
+   *         When the timer is disabled (No timer in the list), it returns 0xFFFF
+   *
+   * @param  None
+   * @retval The number of ticks left to count
+   */
+  uint16_t HW_TS_RTC_ReadLeftTicksToCount(void);
+
+  /**
+   * @brief  Notify the application that a registered timer has expired
+   *         This API shall be implemented by the user application.
+   *         This API notifies the application that a timer expires. This API is running in the RTC Wakeup interrupt
+   *         context. The application may implement an Operating System to change the context priority where the timer
+   *         callback may be handled. This API provides the module ID to identify which module is concerned and to allow
+   *         sending the information to the correct task
+   *
+   * @param  TimerProcessID: The TimerProcessId associated with the timer when it has been created
+   * @param  TimerID: The TimerID of the expired timer
+   * @param  pTimerCallBack: The Callback associated with the timer when it has been created
+   * @retval None
+   */
+  void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack);
+
+  /**
+   * @brief  Notify the application that the wakeupcounter has been updated
+   *         This API should be implemented by the user application
+   *         This API notifies the application that the counter has been updated. This is expected to be used along
+   *         with the HW_TS_RTC_ReadLeftTicksToCount () API. It could be that the counter has been updated since the
+   *         last call of HW_TS_RTC_ReadLeftTicksToCount () and before entering low power mode. This notification
+   *         provides a way to the application to solve that race condition to reevaluate the counter value before
+   *         entering low power mode
+   *
+   * @param  None
+   * @retval None
+   */
+  void HW_TS_RTC_CountUpdated_AppNot(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*HW_IF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/main.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/main.h
new file mode 100644
index 000000000..c8b13c23f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/main.h
@@ -0,0 +1,75 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#ifdef STM32WB35xx
+#include "nucleo_wb35ce.h"
+#else
+#include "stm32wbxx_nucleo.h"
+#endif
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/stm32_lpm_if.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/stm32_lpm_if.h
new file mode 100644
index 000000000..d8e67947f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/stm32_lpm_if.h
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+******************************************************************************
+* @file    stm32_lpm_if.h
+* @brief   Header for stm32_lpm_if.c module (device specific LP management)
+******************************************************************************
+* @attention
+*
+* 
    © Copyright (c) 2019 STMicroelectronics. 
+* All rights reserved.
    
+*
+* This software component is licensed by ST under BSD 3-Clause license,
+* the "License"; You may not use this file except in compliance with the 
+* License. You may obtain a copy of the License at:
+*                        opensource.org/licenses/BSD-3-Clause
+*
+******************************************************************************
+*/
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_LPM_IF_H
+#define __STM32_LPM_IF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/**
+  * @brief Enters Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_EnterOffMode( void );
+/**
+  * @brief Exits Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_ExitOffMode( void );
+
+/**
+  * @brief Enters Low Power Stop Mode
+  * @note ARM exists the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterStopMode( void );
+/**
+  * @brief Exits Low Power Stop Mode
+  * @note Enable the pll at 32MHz
+  * @param none
+  * @retval none
+  */
+void PWR_ExitStopMode( void );
+
+/**
+  * @brief Enters Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterSleepMode( void );
+
+/**
+  * @brief Exits Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_ExitSleepMode( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32_LPM_IF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..eff335ddf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,354 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+#define HAL_CORTEX_MODULE_ENABLED
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+/*#define HAL_I2C_MODULE_ENABLED   */
+#define HAL_IPCC_MODULE_ENABLED
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+#define HAL_PWR_MODULE_ENABLED
+/*#define HAL_QSPI_MODULE_ENABLED   */
+#define HAL_RCC_MODULE_ENABLED
+/*#define HAL_RNG_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100UL)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  (32000UL)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  (32000UL)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    (48000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    (2097000UL) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..12466d5e3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/stm32wbxx_it.h
@@ -0,0 +1,79 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "app_common.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void DMA1_Channel4_IRQHandler(void);
+void USART1_IRQHandler(void);
+void LPUART1_IRQHandler(void);
+void DMA2_Channel4_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+void RTC_WKUP_IRQHandler(void);
+void IPCC_C1_TX_IRQHandler(void);
+void IPCC_C1_RX_IRQHandler(void);
+void PUSH_BUTTON_SW1_EXTI_IRQHandler(void);
+void PUSH_BUTTON_SW2_EXTI_IRQHandler(void);
+void PUSH_BUTTON_SW3_EXTI_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/utilities_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/utilities_conf.h
new file mode 100644
index 000000000..4dde3509a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Inc/utilities_conf.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : utilities_conf.h
+  * Description        : Configuration file for STM32 Utilities.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef UTILITIES_CONF_H
+#define UTILITIES_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "cmsis_compiler.h"
+#include "string.h"
+
+/******************************************************************************
+ * common
+ ******************************************************************************/
+#define UTILS_ENTER_CRITICAL_SECTION( )   uint32_t primask_bit = __get_PRIMASK( );\
+                                          __disable_irq( )
+
+#define UTILS_EXIT_CRITICAL_SECTION( )          __set_PRIMASK( primask_bit )
+
+#define UTILS_MEMSET8( dest, value, size )      memset( dest, value, size);
+
+/******************************************************************************
+ * tiny low power manager
+ * (any macro that does not need to be modified can be removed)
+ ******************************************************************************/
+#define UTIL_LPM_INIT_CRITICAL_SECTION( )
+#define UTIL_LPM_ENTER_CRITICAL_SECTION( )      UTILS_ENTER_CRITICAL_SECTION( )
+#define UTIL_LPM_EXIT_CRITICAL_SECTION( )       UTILS_EXIT_CRITICAL_SECTION( )
+
+/******************************************************************************
+ * sequencer
+ * (any macro that does not need to be modified can be removed)
+ ******************************************************************************/
+#define UTIL_SEQ_INIT_CRITICAL_SECTION( )
+#define UTIL_SEQ_ENTER_CRITICAL_SECTION( )      UTILS_ENTER_CRITICAL_SECTION( )
+#define UTIL_SEQ_EXIT_CRITICAL_SECTION( )       UTILS_EXIT_CRITICAL_SECTION( )
+#define UTIL_SEQ_CONF_TASK_NBR                  (32)
+#define UTIL_SEQ_CONF_PRIO_NBR                  (2)
+#define UTIL_SEQ_MEMSET8( dest, value, size )   UTILS_MEMSET8( dest, value, size )
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*UTILITIES_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/app_debug.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/app_debug.c
new file mode 100644
index 000000000..af3fdfbce
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/app_debug.c
@@ -0,0 +1,360 @@
+/**
+ ******************************************************************************
+ * @file    app_debug.c
+ * @author  MCD Application Team
+ * @brief   Debug capabilities
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+extern void MX_LPUART1_UART_Init(void);
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+extern void MX_USART1_UART_Init(void);
+#endif
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+#if (CFG_HW_USART1_ENABLED == 1)
+    MX_USART1_UART_Init();
+#endif
+#if (CFG_HW_LPUART1_ENABLED == 1)
+    MX_LPUART1_UART_Init();
+#endif
+  return;
+}
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/app_entry.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/app_entry.c
new file mode 100644
index 000000000..c16d0ea9c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/app_entry.c
@@ -0,0 +1,301 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    app_entry.c
+ * @author  MCD Application Team
+ * @brief   Entry point of the Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "main.h"
+#include "app_entry.h"
+#include "app_ble.h"
+#include "ble.h"
+#include "tl.h"
+#include "stm32_seq.h"
+#include "shci_tl.h"
+#include "stm32_lpm.h"
+#include "app_debug.h"
+
+/* Private includes -----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+extern RTC_HandleTypeDef hrtc;
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+#define POOL_SIZE (CFG_TLBLE_EVT_QUEUE_LENGTH*4U*DIVC(( sizeof(TL_PacketHeader_t) + TL_BLE_EVENT_FRAME_SIZE ), 4U))
+
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t EvtPool[POOL_SIZE];
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static TL_CmdPacket_t SystemCmdBuffer;
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t SystemSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255U];
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t BleSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255];
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private functions prototypes-----------------------------------------------*/
+static void SystemPower_Config( void );
+static void appe_Tl_Init( void );
+static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status );
+static void APPE_SysUserEvtRx( void * pPayload );
+
+/* USER CODE BEGIN PFP */
+static void Led_Init( void );
+static void Button_Init( void );
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APPE_Init( void )
+{
+  SystemPower_Config(); /**< Configure the system Power Mode */
+
+  HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
+
+/* USER CODE BEGIN APPE_Init_1 */
+  APPD_Init();
+  
+  /**
+   * The Standby mode should not be entered before the initialization is over
+   * The default state of the Low Power Manager is to allow the Standby Mode so an request is needed here
+   */
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP, UTIL_LPM_DISABLE);
+
+  Led_Init();
+
+  Button_Init();
+/* USER CODE END APPE_Init_1 */
+  appe_Tl_Init();	/* Initialize all transport layers */
+
+  /**
+   * From now, the application is waiting for the ready event ( VS_HCI_C2_Ready )
+   * received on the system channel before starting the Stack
+   * This system event is received with APPE_SysUserEvtRx()
+   */
+/* USER CODE BEGIN APPE_Init_2 */
+
+/* USER CODE END APPE_Init_2 */
+   return;
+}
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+ * @brief  Configure the system for power optimization
+ *
+ * @note  This API configures the system to be ready for low power mode
+ *
+ * @param  None
+ * @retval None
+ */
+static void SystemPower_Config( void )
+{
+
+  /**
+   * Select HSI as system clock source after Wake Up from Stop mode
+   */
+  LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
+
+  /* Initialize low power manager */
+  UTIL_LPM_Init( );
+
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+  /**
+   *  Enable USB power
+   */
+  HAL_PWREx_EnableVddUSB();
+#endif
+
+  return;
+}
+
+static void appe_Tl_Init( void )
+{
+  TL_MM_Config_t tl_mm_config;
+  SHCI_TL_HciInitConf_t SHci_Tl_Init_Conf;
+  /**< Reference table initialization */
+  TL_Init();
+
+  /**< System channel initialization */
+  UTIL_SEQ_RegTask( 1<< CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID, UTIL_SEQ_RFU, shci_user_evt_proc );
+  SHci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&SystemCmdBuffer;
+  SHci_Tl_Init_Conf.StatusNotCallBack = APPE_SysStatusNot;
+  shci_init(APPE_SysUserEvtRx, (void*) &SHci_Tl_Init_Conf);
+
+  /**< Memory Manager channel initialization */
+  tl_mm_config.p_BleSpareEvtBuffer = BleSpareEvtBuffer;
+  tl_mm_config.p_SystemSpareEvtBuffer = SystemSpareEvtBuffer;
+  tl_mm_config.p_AsynchEvtPool = EvtPool;
+  tl_mm_config.AsynchEvtPoolSize = POOL_SIZE;
+  TL_MM_Init( &tl_mm_config );
+
+  TL_Enable();
+
+  return;
+}
+
+static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status )
+{
+  UNUSED(status);
+  return;
+}
+
+/**
+ * The type of the payload for a system user event is tSHCI_UserEvtRxParam
+ * When the system event is both :
+ *    - a ready event (subevtcode = SHCI_SUB_EVT_CODE_READY)
+ *    - reported by the FUS (sysevt_ready_rsp == RSS_FW_RUNNING)
+ * The buffer shall not be released
+ * ( eg ((tSHCI_UserEvtRxParam*)pPayload)->status shall be set to SHCI_TL_UserEventFlow_Disable )
+ * When the status is not filled, the buffer is released by default
+ */
+static void APPE_SysUserEvtRx( void * pPayload )
+{
+  UNUSED(pPayload);
+  /* Traces channel initialization */
+  APPD_EnableCPU2();
+
+  APP_BLE_Init( );
+  UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE);
+  return;
+}
+
+/* USER CODE BEGIN FD_LOCAL_FUNCTIONS */
+static void Led_Init( void )
+{
+#if (CFG_LED_SUPPORTED == 1)
+  /**
+   * Leds Initialization
+   */
+
+  BSP_LED_Init(LED_BLUE);
+  BSP_LED_Init(LED_GREEN);
+  BSP_LED_Init(LED_RED);
+
+  BSP_LED_On(LED_GREEN);
+#endif
+
+  return;
+}
+
+static void Button_Init( void )
+{
+#if (CFG_BUTTON_SUPPORTED == 1)
+  /**
+   * Button Initialization
+   */
+
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+  BSP_PB_Init(BUTTON_SW2, BUTTON_MODE_EXTI);
+  BSP_PB_Init(BUTTON_SW3, BUTTON_MODE_EXTI);
+#endif
+
+  return;
+}
+/* USER CODE END FD_LOCAL_FUNCTIONS */
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+
+void UTIL_SEQ_Idle( void )
+{
+#if ( CFG_LPM_SUPPORTED == 1)
+  UTIL_LPM_EnterLowPower( );
+#endif
+  return;
+}
+
+/**
+  * @brief  This function is called by the scheduler each time an event
+  *         is pending.
+  *
+  * @param  evt_waited_bm : Event pending.
+  * @retval None
+  */
+void UTIL_SEQ_EvtIdle( UTIL_SEQ_bm_t task_id_bm, UTIL_SEQ_bm_t evt_waited_bm )
+{
+  UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+}
+
+void shci_notify_asynch_evt(void* pdata)
+{
+  UTIL_SEQ_SetTask( 1<
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "hw_conf.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef enum
+{
+  TimerID_Free,
+  TimerID_Created,
+  TimerID_Running
+}TimerIDStatus_t;
+
+typedef enum
+{
+  SSR_Read_Requested,
+  SSR_Read_Not_Requested
+}RequestReadSSR_t;
+
+typedef enum
+{
+  WakeupTimerValue_Overpassed,
+  WakeupTimerValue_LargeEnough
+}WakeupTimerLimitation_Status_t;
+
+typedef struct
+{
+  HW_TS_pTimerCb_t  pTimerCallBack;
+  uint32_t        CounterInit;
+  uint32_t        CountLeft;
+  TimerIDStatus_t     TimerIDStatus;
+  HW_TS_Mode_t   TimerMode;
+  uint32_t        TimerProcessID;
+  uint8_t         PreviousID;
+  uint8_t         NextID;
+}TimerContext_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define SSR_FORBIDDEN_VALUE   0xFFFFFFFF
+#define TIMER_LIST_EMPTY      0xFFFF
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/**
+ * START of Section TIMERSERVER_CONTEXT
+ */
+
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile TimerContext_t aTimerContext[CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER];
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint8_t CurrentRunningTimerID;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint8_t PreviousRunningTimerID;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint32_t SSRValueOnLastSetup;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile WakeupTimerLimitation_Status_t  WakeupTimerLimitation;
+
+/**
+ * END of Section TIMERSERVER_CONTEXT
+ */
+
+static RTC_HandleTypeDef *phrtc;  /**< RTC handle */
+static uint8_t  WakeupTimerDivider;
+static uint8_t  AsynchPrescalerUserConfig;
+static uint16_t SynchPrescalerUserConfig;
+static volatile uint16_t MaxWakeupTimerSetup;
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void RestartWakeupCounter(uint16_t Value);
+static uint16_t ReturnTimeElapsed(void);
+static void RescheduleTimerList(void);
+static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR);
+static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID);
+static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID);
+static uint16_t linkTimer(uint8_t TimerID);
+static uint32_t ReadRtcSsrValue(void);
+
+__weak void HW_TS_RTC_CountUpdated_AppNot(void);
+
+/* Functions Definition ------------------------------------------------------*/
+
+/**
+ * @brief  Read the RTC_SSR value
+ *         As described in the reference manual, the RTC_SSR shall be read twice to ensure
+ *         reliability of the value
+ * @param  None
+ * @retval SSR value read
+ */
+static uint32_t ReadRtcSsrValue(void)
+{
+  uint32_t first_read;
+  uint32_t second_read;
+
+  first_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+
+  second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+
+  while(first_read != second_read)
+  {
+    first_read = second_read;
+
+    second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+  }
+
+  return second_read;
+}
+
+/**
+ * @brief  Insert a Timer in the list after the Timer ID specified
+ * @param  TimerID:   The ID of the Timer
+ * @param  RefTimerID: The ID of the Timer to be linked after
+ * @retval None
+ */
+static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID)
+{
+  uint8_t next_id;
+
+  next_id = aTimerContext[RefTimerID].NextID;
+
+  if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    aTimerContext[next_id].PreviousID = TimerID;
+  }
+  aTimerContext[TimerID].NextID = next_id;
+  aTimerContext[TimerID].PreviousID = RefTimerID ;
+  aTimerContext[RefTimerID].NextID = TimerID;
+
+  return;
+}
+
+/**
+ * @brief  Insert a Timer in the list before the ID specified
+ * @param  TimerID:   The ID of the Timer
+ * @param  RefTimerID: The ID of the Timer to be linked before
+ * @retval None
+ */
+static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID)
+{
+  uint8_t previous_id;
+
+  if(RefTimerID != CurrentRunningTimerID)
+  {
+    previous_id = aTimerContext[RefTimerID].PreviousID;
+
+    aTimerContext[previous_id].NextID = TimerID;
+    aTimerContext[TimerID].NextID = RefTimerID;
+    aTimerContext[TimerID].PreviousID = previous_id ;
+    aTimerContext[RefTimerID].PreviousID = TimerID;
+  }
+  else
+  {
+    aTimerContext[TimerID].NextID = RefTimerID;
+    aTimerContext[RefTimerID].PreviousID = TimerID;
+  }
+
+  return;
+}
+
+/**
+ * @brief  Insert a Timer in the list
+ * @param  TimerID:   The ID of the Timer
+ * @retval None
+ */
+static uint16_t linkTimer(uint8_t TimerID)
+{
+  uint32_t time_left;
+  uint16_t time_elapsed;
+  uint8_t timer_id_lookup;
+  uint8_t next_id;
+
+  if(CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    /**
+     * No timer in the list
+     */
+    PreviousRunningTimerID = CurrentRunningTimerID;
+    CurrentRunningTimerID = TimerID;
+    aTimerContext[TimerID].NextID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;
+
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+    time_elapsed = 0;
+  }
+  else
+  {
+    time_elapsed = ReturnTimeElapsed();
+
+    /**
+     * update count of the timer to be linked
+     */
+    aTimerContext[TimerID].CountLeft += time_elapsed;
+    time_left = aTimerContext[TimerID].CountLeft;
+
+    /**
+     * Search for index where the new timer shall be linked
+     */
+    if(aTimerContext[CurrentRunningTimerID].CountLeft <= time_left)
+    {
+      /**
+       * Search for the ID after the first one
+       */
+      timer_id_lookup = CurrentRunningTimerID;
+      next_id = aTimerContext[timer_id_lookup].NextID;
+      while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left))
+      {
+        timer_id_lookup = aTimerContext[timer_id_lookup].NextID;
+        next_id = aTimerContext[timer_id_lookup].NextID;
+      }
+
+      /**
+       * Link after the ID
+       */
+      LinkTimerAfter(TimerID, timer_id_lookup);
+    }
+    else
+    {
+      /**
+       * Link before the first ID
+       */
+      LinkTimerBefore(TimerID, CurrentRunningTimerID);
+      PreviousRunningTimerID = CurrentRunningTimerID;
+      CurrentRunningTimerID = TimerID;
+    }
+  }
+
+  return time_elapsed;
+}
+
+/**
+ * @brief  Remove a Timer from the list
+ * @param  TimerID:   The ID of the Timer
+ * @param  RequestReadSSR: Request to read the SSR register or not
+ * @retval None
+ */
+static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR)
+{
+  uint8_t previous_id;
+  uint8_t next_id;
+
+  if(TimerID == CurrentRunningTimerID)
+  {
+    PreviousRunningTimerID = CurrentRunningTimerID;
+    CurrentRunningTimerID = aTimerContext[TimerID].NextID;
+  }
+  else
+  {
+    previous_id = aTimerContext[TimerID].PreviousID;
+    next_id = aTimerContext[TimerID].NextID;
+
+    aTimerContext[previous_id].NextID = aTimerContext[TimerID].NextID;
+    if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+    {
+      aTimerContext[next_id].PreviousID = aTimerContext[TimerID].PreviousID;
+    }
+  }
+
+  /**
+   * Timer is out of the list
+   */
+  aTimerContext[TimerID].TimerIDStatus = TimerID_Created;
+
+  if((CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (RequestReadSSR == SSR_Read_Requested))
+  {
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+  }
+
+  return;
+}
+
+/**
+ * @brief  Return the number of ticks counted by the wakeuptimer since it has been started
+ * @note  The API is reading the SSR register to get how many ticks have been counted
+ *        since the time the timer has been started
+ * @param  None
+ * @retval Time expired in Ticks
+ */
+static uint16_t ReturnTimeElapsed(void)
+{
+  uint32_t  return_value;
+  uint32_t  wrap_counter;
+
+  if(SSRValueOnLastSetup != SSR_FORBIDDEN_VALUE)
+  {
+    return_value = ReadRtcSsrValue(); /**< Read SSR register first */
+
+    if (SSRValueOnLastSetup >= return_value)
+    {
+      return_value = SSRValueOnLastSetup - return_value;
+    }
+    else
+    {
+      wrap_counter = SynchPrescalerUserConfig - return_value;
+      return_value = SSRValueOnLastSetup + wrap_counter;
+    }
+
+    /**
+     * At this stage, ReturnValue holds the number of ticks counted by SSR
+     * Need to translate in number of ticks counted by the Wakeuptimer
+     */
+    return_value = return_value*AsynchPrescalerUserConfig;
+    return_value = return_value >> WakeupTimerDivider;
+  }
+  else
+  {
+    return_value = 0;
+  }
+
+  return (uint16_t)return_value;
+}
+
+/**
+ * @brief  Set the wakeup counter
+ * @note  The API is writing the counter value so that the value is decreased by one to cope with the fact
+ *    the interrupt is generated with 1 extra clock cycle (See RefManuel)
+ *    It assumes all condition are met to be allowed to write the wakeup counter
+ * @param  Value: Value to be written in the counter
+ * @retval None
+ */
+static void RestartWakeupCounter(uint16_t Value)
+{
+  /**
+   * The wakeuptimer has been disabled in the calling function to reduce the time to poll the WUTWF
+   * FLAG when the new value will have to be written
+   *  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);
+   */
+
+  if(Value == 0)
+  {
+    SSRValueOnLastSetup = ReadRtcSsrValue();
+
+    /**
+     * Simulate that the Timer expired
+     */
+    HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
+  }
+  else
+  {
+    if((Value > 1) ||(WakeupTimerDivider != 1))
+    {
+      Value -= 1;
+    }
+
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+    /**
+     * make sure to clear the flags after checking the WUTWF.
+     * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+     * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+     * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+     * due to the autoreload feature
+     */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+    HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);   /**<  Clear pending bit in NVIC */
+
+    MODIFY_REG(RTC->WUTR, RTC_WUTR_WUT, Value);
+
+    /**
+     * Update the value here after the WUTWF polling that may take some time
+     */
+    SSRValueOnLastSetup = ReadRtcSsrValue();
+
+    __HAL_RTC_WAKEUPTIMER_ENABLE(phrtc);    /**<  Enable the Wakeup Timer */
+
+    HW_TS_RTC_CountUpdated_AppNot();
+  }
+
+  return ;
+}
+
+/**
+ * @brief  Reschedule the list of timer
+ * @note  1) Update the count left for each timer in the list
+ *    2) Setup the wakeuptimer
+ * @param  None
+ * @retval None
+ */
+static void RescheduleTimerList(void)
+{
+  uint8_t   localTimerID;
+  uint32_t  timecountleft;
+  uint16_t  wakeup_timer_value;
+  uint16_t  time_elapsed;
+
+  /**
+   * The wakeuptimer is disabled now to reduce the time to poll the WUTWF
+   * FLAG when the new value will have to be written
+   */
+  if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+  {
+    /**
+     * Wait for the flag to be back to 0 when the wakeup timer is enabled
+     */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == SET);
+  }
+  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);   /**<  Disable the Wakeup Timer */
+
+  localTimerID = CurrentRunningTimerID;
+
+  /**
+   * Calculate what will be the value to write in the wakeuptimer
+   */
+  timecountleft = aTimerContext[localTimerID].CountLeft;
+
+  /**
+   * Read how much has been counted
+   */
+  time_elapsed = ReturnTimeElapsed();
+
+  if(timecountleft < time_elapsed )
+  {
+    /**
+     * There is no tick left to count
+     */
+    wakeup_timer_value = 0;
+    WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+  }
+  else
+  {
+    if(timecountleft > (time_elapsed + MaxWakeupTimerSetup))
+    {
+      /**
+       * The number of tick left is greater than the Wakeuptimer maximum value
+       */
+      wakeup_timer_value = MaxWakeupTimerSetup;
+
+      WakeupTimerLimitation = WakeupTimerValue_Overpassed;
+    }
+    else
+    {
+      wakeup_timer_value = timecountleft - time_elapsed;
+      WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+    }
+
+  }
+
+  /**
+   * update ticks left to be counted for each timer
+   */
+  while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    if (aTimerContext[localTimerID].CountLeft < time_elapsed)
+    {
+      aTimerContext[localTimerID].CountLeft = 0;
+    }
+    else
+    {
+      aTimerContext[localTimerID].CountLeft -= time_elapsed;
+    }
+    localTimerID = aTimerContext[localTimerID].NextID;
+  }
+
+  /**
+   * Write next count
+   */
+  RestartWakeupCounter(wakeup_timer_value);
+
+  return ;
+}
+
+/* Public functions ----------------------------------------------------------*/
+
+/**
+ * For all public interface except that may need write access to the RTC, the RTC
+ * shall be unlock at the beginning and locked at the output
+ * In order to ease maintainability, the unlock is done at the top and the lock at then end
+ * in case some new implementation is coming in the future
+ */
+
+void HW_TS_RTC_Wakeup_Handler(void)
+{
+  HW_TS_pTimerCb_t ptimer_callback;
+  uint32_t timer_process_id;
+  uint8_t local_current_running_timer_id;
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  /**
+   * Disable the Wakeup Timer
+   * This may speed up a bit the processing to wait the timer to be disabled
+   * The timer is still counting 2 RTCCLK
+   */
+  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);
+
+  local_current_running_timer_id = CurrentRunningTimerID;
+
+  if(aTimerContext[local_current_running_timer_id].TimerIDStatus == TimerID_Running)
+  {
+    ptimer_callback = aTimerContext[local_current_running_timer_id].pTimerCallBack;
+    timer_process_id = aTimerContext[local_current_running_timer_id].TimerProcessID;
+
+    /**
+     * It should be good to check whether the TimeElapsed is greater or not than the tick left to be counted
+     * However, due to the inaccuracy of the reading of the time elapsed, it may return there is 1 tick
+     * to be left whereas the count is over
+     * A more secure implementation has been done with a flag to state whereas the full count has been written
+     * in the wakeuptimer or not
+     */
+    if(WakeupTimerLimitation != WakeupTimerValue_Overpassed)
+    {
+      if(aTimerContext[local_current_running_timer_id].TimerMode == hw_ts_Repeated)
+      {
+        UnlinkTimer(local_current_running_timer_id, SSR_Read_Not_Requested);
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+        __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+        HW_TS_Start(local_current_running_timer_id, aTimerContext[local_current_running_timer_id].CounterInit);
+
+        /* Disable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+      }
+      else
+      {
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+        __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+        HW_TS_Stop(local_current_running_timer_id);
+
+        /* Disable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+      }
+
+      HW_TS_RTC_Int_AppNot(timer_process_id, local_current_running_timer_id, ptimer_callback);
+    }
+    else
+    {
+      RescheduleTimerList();
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+      __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+    }
+  }
+  else
+  {
+    /**
+     * We should never end up in this case
+     * However, if due to any bug in the timer server this is the case, the mistake may not impact the user.
+     * We could just clean the interrupt flag and get out from this unexpected interrupt
+     */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+    /**
+     * make sure to clear the flags after checking the WUTWF.
+     * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+     * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+     * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+     * due to the autoreload feature
+     */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  return;
+}
+
+void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *hrtc)
+{
+  uint8_t loop;
+  uint32_t localmaxwakeuptimersetup;
+
+  /**
+   * Get RTC handler
+   */
+  phrtc = hrtc;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
+
+  /**
+   * Readout the user config
+   */
+  WakeupTimerDivider = (4 - ((uint32_t)(READ_BIT(RTC->CR, RTC_CR_WUCKSEL))));
+
+  AsynchPrescalerUserConfig = (uint8_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_A) >> (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)) + 1;
+
+  SynchPrescalerUserConfig = (uint16_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_S)) + 1;
+
+  /**
+   *  Margin is taken to avoid wrong calculation when the wrap around is there and some
+   *  application interrupts may have delayed the reading
+   */
+  localmaxwakeuptimersetup = ((((SynchPrescalerUserConfig - 1)*AsynchPrescalerUserConfig) - CFG_HW_TS_RTC_HANDLER_MAX_DELAY) >> WakeupTimerDivider);
+
+  if(localmaxwakeuptimersetup >= 0xFFFF)
+  {
+    MaxWakeupTimerSetup = 0xFFFF;
+  }
+  else
+  {
+    MaxWakeupTimerSetup = (uint16_t)localmaxwakeuptimersetup;
+  }
+
+  /**
+   * Configure EXTI module
+   */
+  LL_EXTI_EnableRisingTrig_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+  LL_EXTI_EnableIT_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+
+  if(TimerInitMode == hw_ts_InitMode_Full)
+  {
+    WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+
+    /**
+     * Initialize the timer server
+     */
+    for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++)
+    {
+      aTimerContext[loop].TimerIDStatus = TimerID_Free;
+    }
+
+    CurrentRunningTimerID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;   /**<  Set ID to non valid value */
+
+    __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);                       /**<  Disable the Wakeup Timer */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);     /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module  */
+    HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);       /**<  Clear pending bit in NVIC  */
+    __HAL_RTC_WAKEUPTIMER_ENABLE_IT(phrtc, RTC_IT_WUT);         /**<  Enable interrupt in RTC module  */
+  }
+  else
+  {
+    if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTF) != RESET)
+    {
+      /**
+       * Simulate that the Timer expired
+       */
+      HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_SetPriority(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO);   /**<  Set NVIC priority */
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+  return;
+}
+
+HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pftimeout_handler)
+{
+  HW_TS_ReturnStatus_t localreturnstatus;
+  uint8_t loop = 0;
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  while((loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[loop].TimerIDStatus != TimerID_Free))
+  {
+    loop++;
+  }
+
+  if(loop != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    aTimerContext[loop].TimerIDStatus = TimerID_Created;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+    aTimerContext[loop].TimerProcessID = TimerProcessID;
+    aTimerContext[loop].TimerMode = TimerMode;
+    aTimerContext[loop].pTimerCallBack = pftimeout_handler;
+    *pTimerId = loop;
+
+    localreturnstatus = hw_ts_Successful;
+  }
+  else
+  {
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+    localreturnstatus = hw_ts_Failed;
+  }
+
+  return(localreturnstatus);
+}
+
+void HW_TS_Delete(uint8_t timer_id)
+{
+  HW_TS_Stop(timer_id);
+
+  aTimerContext[timer_id].TimerIDStatus = TimerID_Free; /**<  release ID */
+
+  return;
+}
+
+void HW_TS_Stop(uint8_t timer_id)
+{
+  uint8_t localcurrentrunningtimerid;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);    /**<  Disable NVIC */
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
+  {
+    UnlinkTimer(timer_id, SSR_Read_Requested);
+    localcurrentrunningtimerid = CurrentRunningTimerID;
+
+    if(localcurrentrunningtimerid == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+    {
+      /**
+       * List is empty
+       */
+
+      /**
+       * Disable the timer
+       */
+      if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+      {
+        /**
+         * Wait for the flag to be back to 0 when the wakeup timer is enabled
+         */
+        while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == SET);
+      }
+      __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);   /**<  Disable the Wakeup Timer */
+
+      while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+      /**
+       * make sure to clear the flags after checking the WUTWF.
+       * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+       * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+       * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+       * due to the autoreload feature
+       */
+      __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+      __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+      HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);   /**<  Clear pending bit in NVIC */
+    }
+    else if(PreviousRunningTimerID != localcurrentrunningtimerid)
+    {
+      RescheduleTimerList();
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+  return;
+}
+
+void HW_TS_Start(uint8_t timer_id, uint32_t timeout_ticks)
+{
+  uint16_t time_elapsed;
+  uint8_t localcurrentrunningtimerid;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+  if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
+  {
+    HW_TS_Stop( timer_id );
+  }
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);    /**<  Disable NVIC */
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  aTimerContext[timer_id].TimerIDStatus = TimerID_Running;
+
+  aTimerContext[timer_id].CountLeft = timeout_ticks;
+  aTimerContext[timer_id].CounterInit = timeout_ticks;
+
+  time_elapsed =  linkTimer(timer_id);
+
+  localcurrentrunningtimerid = CurrentRunningTimerID;
+
+  if(PreviousRunningTimerID != localcurrentrunningtimerid)
+  {
+    RescheduleTimerList();
+  }
+  else
+  {
+    aTimerContext[timer_id].CountLeft -= time_elapsed;
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+  return;
+}
+
+uint16_t HW_TS_RTC_ReadLeftTicksToCount(void)
+{
+  uint32_t primask_bit;
+  uint16_t return_value, auro_reload_value, elapsed_time_value;
+
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();                /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+
+  if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+  {
+    auro_reload_value = (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT));
+
+    elapsed_time_value = ReturnTimeElapsed();
+
+    if(auro_reload_value > elapsed_time_value)
+    {
+      return_value = auro_reload_value - elapsed_time_value;
+    }
+    else
+    {
+      return_value = 0;
+    }
+  }
+  else
+  {
+    return_value = TIMER_LIST_EMPTY;
+  }
+
+  __set_PRIMASK(primask_bit);     /**< Restore PRIMASK bit*/
+
+  return (return_value);
+}
+
+__weak void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack)
+{
+  pTimerCallBack();
+
+  return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/hw_uart.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/hw_uart.c
new file mode 100644
index 000000000..9a553610d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/hw_uart.c
@@ -0,0 +1,318 @@
+/**
+ ******************************************************************************
+  * File Name          : Src/hw_uart.c
+  * Description        : HW UART source file for STM32WPAN Middleware.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "hw_conf.h"
+#if (CFG_HW_LPUART1_ENABLED == 1)
+extern UART_HandleTypeDef hlpuart1;
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+extern UART_HandleTypeDef huart1;
+#endif
+
+/* Macros --------------------------------------------------------------------*/
+#define HW_UART_RX_IT(__HANDLE__, __USART_BASE__)                                                   \
+        do{                                                                                         \
+            HW_##__HANDLE__##RxCb = cb;                                                             \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            HAL_UART_Receive_IT(&(__HANDLE__), p_data, size);                                       \
+        } while(0)
+
+#define HW_UART_TX_IT(__HANDLE__, __USART_BASE__)                                                   \
+        do{                                                                                         \
+            HW_##__HANDLE__##TxCb = cb;                                                             \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            HAL_UART_Transmit_IT(&(__HANDLE__), p_data, size);                                      \
+        } while(0)
+
+#define HW_UART_TX(__HANDLE__, __USART_BASE__)                                                      \
+        do{                                                                                         \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            hal_status = HAL_UART_Transmit(&(__HANDLE__), p_data, size, timeout);                   \
+        } while(0)
+
+/* Variables -----------------------------------------------------------------*/
+#if (CFG_HW_USART1_ENABLED == 1)
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+    DMA_HandleTypeDef HW_hdma_huart1_tx ={0};
+#endif
+    void (*HW_huart1RxCb)(void);
+    void (*HW_huart1TxCb)(void);
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+    DMA_HandleTypeDef HW_hdma_hlpuart1_tx ={0};
+#endif
+    void (*HW_hlpuart1RxCb)(void);
+    void (*HW_hlpuart1TxCb)(void);
+#endif
+
+void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_RX_IT(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_RX_IT(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  void (*cb)(void))
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_TX_IT(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_TX_IT(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout)
+{
+    HAL_StatusTypeDef hal_status = HAL_OK;
+    hw_status_t hw_status = hw_uart_ok;
+
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_TX(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_TX(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    switch (hal_status)
+    {
+        case HAL_OK:
+            hw_status = hw_uart_ok;
+            break;
+
+        case HAL_ERROR:
+            hw_status = hw_uart_error;
+            break;
+
+        case HAL_BUSY:
+            hw_status = hw_uart_busy;
+            break;
+
+        case HAL_TIMEOUT:
+            hw_status = hw_uart_to;
+            break;
+
+        default:
+            break;
+    }
+
+    return hw_status;
+}
+
+hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+{
+    HAL_StatusTypeDef hal_status = HAL_OK;
+    hw_status_t hw_status = hw_uart_ok;
+
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_huart1TxCb = cb;
+            huart1.Instance = USART1;
+            hal_status = HAL_UART_Transmit_DMA(&huart1, p_data, size);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_hlpuart1TxCb = cb;
+            hlpuart1.Instance = LPUART1;
+            hal_status = HAL_UART_Transmit_DMA(&hlpuart1, p_data, size);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    switch (hal_status)
+    {
+        case HAL_OK:
+            hw_status = hw_uart_ok;
+            break;
+
+        case HAL_ERROR:
+            hw_status = hw_uart_error;
+            break;
+
+        case HAL_BUSY:
+            hw_status = hw_uart_busy;
+            break;
+
+        case HAL_TIMEOUT:
+            hw_status = hw_uart_to;
+            break;
+
+        default:
+            break;
+    }
+
+    return hw_status;
+}
+
+void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HAL_UART_IRQHandler(&huart1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HAL_UART_IRQHandler(&hlpuart1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+        case hw_uart1:
+            HAL_DMA_IRQHandler(huart1.hdmatx);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+        case hw_lpuart1:
+            HAL_DMA_IRQHandler(hlpuart1.hdmatx);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+    switch ((uint32_t)huart->Instance)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case (uint32_t)USART1:
+            if(HW_huart1RxCb)
+            {
+                HW_huart1RxCb();
+            }
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case (uint32_t)LPUART1:
+            if(HW_hlpuart1RxCb)
+            {
+                HW_hlpuart1RxCb();
+            }
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+    switch ((uint32_t)huart->Instance)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case (uint32_t)USART1:
+            if(HW_huart1TxCb)
+            {
+                HW_huart1TxCb();
+            }
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case (uint32_t)LPUART1:
+            if(HW_hlpuart1TxCb)
+            {
+                HW_hlpuart1TxCb();
+            }
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/main.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/main.c
new file mode 100644
index 000000000..b4c3d4dd6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/main.c
@@ -0,0 +1,641 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    main.c
+ * @author  MCD Application Team
+ * @brief   BLE application with BLE core
+ *
+  @verbatim
+  ==============================================================================
+                    ##### IMPORTANT NOTE #####
+  ==============================================================================
+
+  This application requests having the stm32wb5x_BLE_Stack_fw.bin binary
+  flashed on the Wireless Coprocessor.
+  If it is not the case, you need to use STM32CubeProgrammer to load the appropriate
+  binary.
+
+  All available binaries are located under following directory:
+  /Projects/STM32_Copro_Wireless_Binaries
+
+  Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+  Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the
+  detailed procedure to change the Wireless Coprocessor binary.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "app_entry.h"
+#include "app_common.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "stm32_lpm.h"
+#include "stm32_seq.h"
+#include "dbg_trace.h"
+#include "hw_conf.h"
+#include "otp.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef hlpuart1;
+UART_HandleTypeDef huart1;
+DMA_HandleTypeDef hdma_lpuart1_tx;
+DMA_HandleTypeDef hdma_usart1_tx;
+
+RTC_HandleTypeDef hrtc;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+void MX_LPUART1_UART_Init(void);
+void MX_USART1_UART_Init(void);
+static void MX_RF_Init(void);
+static void MX_RTC_Init(void);
+/* USER CODE BEGIN PFP */
+void PeriphClock_Config(void);
+static void Reset_Device( void );
+static void Reset_IPCC( void );
+static void Reset_BackupDomain( void );
+static void Init_Exti( void );
+static void Config_HSE(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+  
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+  Reset_Device();
+  Config_HSE();
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  PeriphClock_Config();
+  Init_Exti(); /**< Configure the system Power Mode */
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_RF_Init();
+  MX_RTC_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Init code for STM32_WPAN */  
+  APPE_Init();
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+	while(1)
+	{
+		UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure LSE Drive Capability 
+  */
+  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE
+                              |RCC_OSCILLATORTYPE_LSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RFWAKEUP
+                              |RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1
+                              |RCC_PERIPHCLK_LPUART1;
+  PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+  PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* USER CODE BEGIN Smps */
+
+#if (CFG_USE_SMPS != 0)
+  /**
+   *  Configure and enable SMPS
+   *
+   *  The SMPS configuration is not yet supported by CubeMx
+   */
+  LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
+  LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
+  LL_PWR_SMPS_Enable();
+#endif
+
+  /* USER CODE END Smps */
+
+
+}
+
+/**
+  * @brief LPUART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+void MX_LPUART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN LPUART1_Init 0 */
+
+  /* USER CODE END LPUART1_Init 0 */
+
+  /* USER CODE BEGIN LPUART1_Init 1 */
+
+  /* USER CODE END LPUART1_Init 1 */
+  hlpuart1.Instance = LPUART1;
+  hlpuart1.Init.BaudRate = 115200;
+  hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
+  hlpuart1.Init.StopBits = UART_STOPBITS_1;
+  hlpuart1.Init.Parity = UART_PARITY_NONE;
+  hlpuart1.Init.Mode = UART_MODE_TX_RX;
+  hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  hlpuart1.FifoMode = UART_FIFOMODE_DISABLE;
+  if (HAL_UART_Init(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN LPUART1_Init 2 */
+
+  /* USER CODE END LPUART1_Init 2 */
+
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_8;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+  * @brief RF Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RF_Init(void)
+{
+
+  /* USER CODE BEGIN RF_Init 0 */
+
+  /* USER CODE END RF_Init 0 */
+
+  /* USER CODE BEGIN RF_Init 1 */
+
+  /* USER CODE END RF_Init 1 */
+  /* USER CODE BEGIN RF_Init 2 */
+
+  /* USER CODE END RF_Init 2 */
+
+}
+
+/**
+  * @brief RTC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RTC_Init(void)
+{
+
+  /* USER CODE BEGIN RTC_Init 0 */
+
+  /* USER CODE END RTC_Init 0 */
+
+  /* USER CODE BEGIN RTC_Init 1 */
+
+  /* USER CODE END RTC_Init 1 */
+  /** Initialize RTC Only 
+  */
+  hrtc.Instance = RTC;
+  hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
+  hrtc.Init.AsynchPrediv = CFG_RTC_ASYNCH_PRESCALER;
+  hrtc.Init.SynchPrediv = CFG_RTC_SYNCH_PRESCALER;
+  hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
+  hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+  hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+  if (HAL_RTC_Init(&hrtc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN RTC_Init 2 */
+  /* Disable RTC registers write protection */
+  LL_RTC_DisableWriteProtection(RTC);
+
+  LL_RTC_WAKEUP_SetClock(RTC, CFG_RTC_WUCKSEL_DIVIDER);
+
+  /* Enable RTC registers write protection */
+  LL_RTC_EnableWriteProtection(RTC);
+  /* USER CODE END RTC_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
+  __HAL_RCC_DMA2_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
+  /* DMA2_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA2_Channel4_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(DMA2_Channel4_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+void PeriphClock_Config(void)
+{
+  #if (CFG_USB_INTERFACE_ENABLE != 0)
+	RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
+	RCC_CRSInitTypeDef RCC_CRSInitStruct = { 0 };
+
+    /**
+    * This prevents the CPU2 to disable the HSI48 oscillator when
+    * it does not use anymore the RNG IP
+    */
+    LL_HSEM_1StepLock( HSEM, 5 );
+
+    LL_RCC_HSI48_Enable();
+
+	while(!LL_RCC_HSI48_IsReady());
+
+	/* Select HSI48 as USB clock source */
+	PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+	PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+	HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+	/*Configure the clock recovery system (CRS)**********************************/
+
+	/* Enable CRS Clock */
+	__HAL_RCC_CRS_CLK_ENABLE();
+
+	/* Default Synchro Signal division factor (not divided) */
+	RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+
+	/* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+	RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+
+	/* HSI48 is synchronized with USB SOF at 1KHz rate */
+	RCC_CRSInitStruct.ReloadValue = RCC_CRS_RELOADVALUE_DEFAULT;
+	RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+
+	RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+
+	/* Set the TRIM[5:0] to the default value*/
+	RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+
+	/* Start automatic synchronization */
+	HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+#endif
+
+	return;
+}
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+
+static void Config_HSE(void)
+{
+    OTP_ID0_t * p_otp;
+
+  /**
+   * Read HSE_Tuning from OTP
+   */
+  p_otp = (OTP_ID0_t *) OTP_Read(0);
+  if (p_otp)
+  {
+    LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
+  }
+
+  return;
+}  
+
+
+static void Reset_Device( void )
+{
+#if ( CFG_HW_RESET_BY_FW == 1 )
+	Reset_BackupDomain();
+
+	Reset_IPCC();
+#endif
+
+	return;
+}
+
+static void Reset_IPCC( void )
+{
+	LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
+
+	LL_C1_IPCC_ClearFlag_CHx(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_ClearFlag_CHx(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C1_IPCC_DisableTransmitChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_DisableTransmitChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C1_IPCC_DisableReceiveChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_DisableReceiveChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	return;
+}
+
+static void Reset_BackupDomain( void )
+{
+	if ((LL_RCC_IsActiveFlag_PINRST() != FALSE) && (LL_RCC_IsActiveFlag_SFTRST() == FALSE))
+	{
+		HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+		/**
+		 *  Write twice the value to flush the APB-AHB bridge
+		 *  This bit shall be written in the register before writing the next one
+		 */
+		HAL_PWR_EnableBkUpAccess();
+
+		__HAL_RCC_BACKUPRESET_FORCE();
+		__HAL_RCC_BACKUPRESET_RELEASE();
+	}
+
+	return;
+}
+
+static void Init_Exti( void )
+{
+  /**< Disable all wakeup interrupt on CPU1  except IPCC(36), HSEM(38) */
+  LL_EXTI_DisableIT_0_31(~0);
+  LL_EXTI_DisableIT_32_63( (~0) & (~(LL_EXTI_LINE_36 | LL_EXTI_LINE_38)) );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += HAL_GetTickFreq();
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+  {
+    /************************************************************************************
+     * ENTER SLEEP MODE
+     ***********************************************************************************/
+    LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+    /**
+     * This option is used to ensure that store operations are completed
+     */
+  #if defined ( __CC_ARM)
+    __force_stores();
+  #endif
+
+    __WFI( );
+  }
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/stm32_lpm_if.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/stm32_lpm_if.c
new file mode 100644
index 000000000..1418e0a36
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/stm32_lpm_if.c
@@ -0,0 +1,297 @@
+/* USER CODE BEGIN Header */
+/**
+ ***************************************************************************************
+  * File Name          : stm32_lpm_if.c
+  * Description        : Low layer function to enter/exit low power modes (stop, sleep).
+ ***************************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+  
+/* Includes ------------------------------------------------------------------*/  
+#include "stm32_lpm_if.h"
+#include "stm32_lpm.h"
+#include "app_conf.h"
+/* USER CODE BEGIN include */
+
+/* USER CODE END include */
+
+/* Exported variables --------------------------------------------------------*/
+const struct UTIL_LPM_Driver_s UTIL_PowerDriver = 
+{
+  PWR_EnterSleepMode,
+  PWR_ExitSleepMode,
+  
+  PWR_EnterStopMode,
+  PWR_ExitStopMode, 
+  
+  PWR_EnterOffMode,
+  PWR_ExitOffMode,
+};
+
+/* Private function prototypes -----------------------------------------------*/
+static void Switch_On_HSI( void );
+/* USER CODE BEGIN Private_Function_Prototypes */
+
+/* USER CODE END Private_Function_Prototypes */
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN Private_Typedef */
+
+/* USER CODE END Private_Typedef */
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Private_Define */
+
+/* USER CODE END Private_Define */
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Private_Macro */
+
+/* USER CODE END Private_Macro */
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN Private_Variables */
+
+/* USER CODE END Private_Variables */
+
+/* Functions Definition ------------------------------------------------------*/
+/**
+  * @brief Enters Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_EnterOffMode( void )
+{
+/* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
+  /************************************************************************************
+   * ENTER OFF MODE
+   ***********************************************************************************/
+  /*
+   * There is no risk to clear all the WUF here because in the current implementation, this API is called
+   * in critical section. If an interrupt occurs while in that critical section before that point,
+   * the flag is set and will be cleared here but the system will not enter Off Mode
+   * because an interrupt is pending in the NVIC. The ISR will be executed when moving out
+   * of this critical section
+   */
+  LL_PWR_ClearFlag_WU( );
+
+  LL_PWR_SetPowerMode( LL_PWR_MODE_STANDBY );
+
+  LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores( );
+#endif
+
+  __WFI( );
+/* USER CODE END PWR_EnterOffMode */
+}
+
+/**
+  * @brief Exits Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_ExitOffMode( void )
+{
+/* USER CODE BEGIN PWR_ExitOffMode */
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitOffMode */
+}
+
+/**
+  * @brief Enters Low Power Stop Mode
+  * @note ARM exists the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterStopMode( void )
+{
+/* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
+  /**
+   * This function is called from CRITICAL SECTION
+   */
+  while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
+
+  if ( ! LL_HSEM_1StepLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID ) )
+  {
+    if( LL_PWR_IsActiveFlag_C2DS( ) )
+    {
+      /* Release ENTRY_STOP_MODE semaphore */
+      LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
+
+      /**
+       * The switch on HSI before entering Stop Mode is required on Cut2.0
+       * It is useless from Cut2.1
+       */
+      Switch_On_HSI( );
+    }
+  }
+  else
+  {
+    /**
+     * The switch on HSI before entering Stop Mode is required on Cut2.0
+     * It is useless from Cut2.1
+     */
+    Switch_On_HSI( );
+  }
+
+  /* Release RCC semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  /************************************************************************************
+   * ENTER STOP MODE
+   ***********************************************************************************/
+  LL_PWR_SetPowerMode( LL_PWR_MODE_STOP2 );
+
+  LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores( );
+#endif
+
+  __WFI();
+/* USER CODE END PWR_EnterStopMode */
+}
+
+/**
+  * @brief Exits Low Power Stop Mode
+  * @note Enable the pll at 32MHz
+  * @param none
+  * @retval none
+  */
+void PWR_ExitStopMode( void )
+{
+/* USER CODE BEGIN PWR_ExitStopMode */
+  /**
+   * This function is called from CRITICAL SECTION
+   */
+
+  /* Release ENTRY_STOP_MODE semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
+
+  while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
+
+  if(LL_RCC_GetSysClkSource( ) == LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+    LL_RCC_HSE_Enable( );
+    while(!LL_RCC_HSE_IsReady( ));
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
+    while (LL_RCC_GetSysClkSource( ) != LL_RCC_SYS_CLKSOURCE_STATUS_HSE);
+  }
+  else
+  {
+    /**
+     * As long as the current application is fine with HSE as system clock source,
+     * there is nothing to do here
+     */
+  }
+
+  /* Release RCC semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitStopMode */
+}
+
+/**
+  * @brief Enters Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterSleepMode( void )
+{
+/* USER CODE BEGIN PWR_EnterSleepMode */
+
+  HAL_SuspendTick();
+
+  /************************************************************************************
+   * ENTER SLEEP MODE
+   ***********************************************************************************/
+  LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+
+  __WFI( );
+/* USER CODE END PWR_EnterSleepMode */
+}
+
+/**
+  * @brief Exits Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_ExitSleepMode( void )
+{
+/* USER CODE BEGIN PWR_ExitSleepMode */
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitSleepMode */
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+  * @brief Switch the system clock on HSI
+  * @param none
+  * @retval none
+  */
+static void Switch_On_HSI( void )
+{
+  LL_RCC_HSI_Enable( );
+  while(!LL_RCC_HSI_IsReady( ));
+  LL_RCC_SetSysClkSource( LL_RCC_SYS_CLKSOURCE_HSI );
+  LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSI);
+  while (LL_RCC_GetSysClkSource( ) != LL_RCC_SYS_CLKSOURCE_STATUS_HSI);
+}
+
+/* USER CODE BEGIN Private_Functions */
+
+/* USER CODE END Private_Functions */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..f22ad0f38
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,329 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32wbxx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_lpuart1_tx;
+
+extern DMA_HandleTypeDef hdma_usart1_tx;
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_HSEM_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  HAL_DMA_MuxSyncConfigTypeDef pSyncConfig;
+  if(huart->Instance==LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspInit 0 */
+
+  /* USER CODE END LPUART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_LPUART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**LPUART1 GPIO Configuration    
+    PA2     ------> LPUART1_TX
+    PA3     ------> LPUART1_RX
+    PA6     ------> LPUART1_CTS 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* LPUART1 DMA Init */
+    /* LPUART1_TX Init */
+    hdma_lpuart1_tx.Instance = DMA1_Channel4;
+    hdma_lpuart1_tx.Init.Request = DMA_REQUEST_LPUART1_TX;
+    hdma_lpuart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_lpuart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_lpuart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_lpuart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_lpuart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_lpuart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_lpuart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_lpuart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    pSyncConfig.SyncSignalID = HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT;
+    pSyncConfig.SyncPolarity = HAL_DMAMUX_SYNC_NO_EVENT;
+    pSyncConfig.SyncEnable = DISABLE;
+    pSyncConfig.EventEnable = DISABLE;
+    pSyncConfig.RequestNumber = 1;
+    if (HAL_DMAEx_ConfigMuxSync(&hdma_lpuart1_tx, &pSyncConfig) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmatx,hdma_lpuart1_tx);
+
+    /* LPUART1 interrupt Init */
+    HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(LPUART1_IRQn);
+  /* USER CODE BEGIN LPUART1_MspInit 1 */
+
+  /* USER CODE END LPUART1_MspInit 1 */
+  }
+  else if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspInit 0 */
+
+  /* USER CODE END USART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**USART1 GPIO Configuration    
+    PA11     ------> USART1_CTS
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_11;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* USART1 DMA Init */
+    /* USART1_TX Init */
+    hdma_usart1_tx.Instance = DMA2_Channel4;
+    hdma_usart1_tx.Init.Request = DMA_REQUEST_USART1_TX;
+    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx);
+
+    /* USART1 interrupt Init */
+    HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspInit 1 */
+
+  /* USER CODE END USART1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspDeInit 0 */
+
+  /* USER CODE END LPUART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_LPUART1_CLK_DISABLE();
+  
+    /**LPUART1 GPIO Configuration    
+    PA2     ------> LPUART1_TX
+    PA3     ------> LPUART1_RX
+    PA6     ------> LPUART1_CTS 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_6);
+
+    /* LPUART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmatx);
+
+    /* LPUART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(LPUART1_IRQn);
+  /* USER CODE BEGIN LPUART1_MspDeInit 1 */
+
+  /* USER CODE END LPUART1_MspDeInit 1 */
+  }
+  else if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+  /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+  
+    /**USART1 GPIO Configuration    
+    PA11     ------> USART1_CTS
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11);
+
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
+
+    /* USART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmatx);
+
+    /* USART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+  /* USER CODE END USART1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspInit 0 */
+  HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+  /**
+  *  Write twice the value to flush the APB-AHB bridge
+  *  This bit shall be written in the register before writing the next one
+  */
+  HAL_PWR_EnableBkUpAccess();
+
+  __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); /**< Select LSI as RTC Input */
+  /* USER CODE END RTC_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_RTC_ENABLE();
+  /* USER CODE BEGIN RTC_MspInit 1 */
+  HAL_RTCEx_EnableBypassShadow(hrtc);
+  /* USER CODE END RTC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspDeInit 0 */
+
+  /* USER CODE END RTC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RTC_DISABLE();
+  /* USER CODE BEGIN RTC_MspDeInit 1 */
+
+  /* USER CODE END RTC_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..d469f29ab
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/stm32wbxx_it.c
@@ -0,0 +1,315 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_lpuart1_tx;
+extern DMA_HandleTypeDef hdma_usart1_tx;
+extern UART_HandleTypeDef hlpuart1;
+extern UART_HandleTypeDef huart1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles DMA1 channel4 global interrupt.
+  */
+void DMA1_Channel4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_lpuart1_tx);
+  /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel4_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+
+  /* USER CODE END USART1_IRQn 0 */
+  HAL_UART_IRQHandler(&huart1);
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles LPUART1 global interrupt.
+  */
+void LPUART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN LPUART1_IRQn 0 */
+
+  /* USER CODE END LPUART1_IRQn 0 */
+  HAL_UART_IRQHandler(&hlpuart1);
+  /* USER CODE BEGIN LPUART1_IRQn 1 */
+
+  /* USER CODE END LPUART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA2 channel4 global interrupt.
+  */
+void DMA2_Channel4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2_Channel4_IRQn 0 */
+
+  /* USER CODE END DMA2_Channel4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart1_tx);
+  /* USER CODE BEGIN DMA2_Channel4_IRQn 1 */
+
+  /* USER CODE END DMA2_Channel4_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW1_EXTI_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW2_EXTI_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW2_PIN);
+}
+
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW3_EXTI_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW3_PIN);
+}
+
+void RTC_WKUP_IRQHandler(void)
+{
+  HW_TS_RTC_Wakeup_Handler();
+}
+
+void IPCC_C1_TX_IRQHandler(void)
+{
+  HW_IPCC_Tx_Handler();
+
+  return;
+}
+
+void IPCC_C1_RX_IRQHandler(void)
+{
+  HW_IPCC_Rx_Handler();
+  return;
+}
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..733770023
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/Core/Src/system_stm32wbxx.c
@@ -0,0 +1,356 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                        4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+  /**
+   * When the application is expected to be downloaded by OTA, the SCB->VTOR shall not be modified
+   * as it has already been set to the correct value by the BLE_Ota application before jumping
+   * to the current application
+   */
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/BLE_HeartRate_ota.ewd b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/BLE_HeartRate_ota.ewd
new file mode 100644
index 000000000..333b2599f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/BLE_HeartRate_ota.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		BLE_HeartRate_ota
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/BLE_HeartRate_ota.ewp b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/BLE_HeartRate_ota.ewp
new file mode 100644
index 000000000..d4f28ead9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/BLE_HeartRate_ota.ewp
@@ -0,0 +1,1257 @@
+
+
+    3
+    
+        BLE_HeartRate_ota
+        
+            ARM
+        
+        1
+        
+            General
+            3
+            
+                30
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            ICCARM
+            2
+            
+                34
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            AARM
+            2
+            
+                10
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            OBJCOPY
+            0
+            
+                1
+                1
+                1
+                
+                
+                
+                
+                
+            
+        
+        
+            CUSTOM
+            3
+            
+                
+                
+                0
+            
+        
+        
+            BICOMP
+            0
+            
+        
+        
+            BUILDACTION
+            1
+            
+                
+                
+            
+        
+        
+            ILINK
+            0
+            
+                20
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            IARCHIVE
+            0
+            
+                0
+                1
+                1
+                
+                
+                
+            
+        
+        
+            BILINK
+            0
+            
+        
+    
+    
+        Application
+        
+            EWARM
+            
+                $PROJ_DIR$\startup_stm32wb35xx_cm4.s
+            
+        
+        
+            User
+            
+                Core
+                
+                    $PROJ_DIR$\..\Core\Src\app_entry.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\app_debug.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\hw_timerserver.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\hw_uart.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\main.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\stm32_lpm_if.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\stm32wbxx_hal_msp.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\stm32wbxx_it.c
+                
+            
+            
+                STM32_WPAN
+                
+                    App
+                    
+                        $PROJ_DIR$\..\STM32_WPAN\App\app_ble.c
+                    
+                    
+                        $PROJ_DIR$\..\STM32_WPAN\App\dis_app.c
+                    
+                    
+                        $PROJ_DIR$\..\STM32_WPAN\App\hrs_app.c
+                    
+                
+                
+                    Target
+                    
+                        $PROJ_DIR$\..\STM32_WPAN\Target\hw_ipcc.c
+                    
+                
+            
+        
+    
+    
+        Doc
+        
+            $PROJ_DIR$\..\readme.txt
+        
+    
+    
+        Drivers
+        
+            BSP
+            
+                NUCLEO-WB35CE
+                
+                    $PROJ_DIR$\..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE\nucleo_wb35ce.c
+                
+            
+        
+        
+            CMSIS
+            
+                $PROJ_DIR$\..\Core\Src\system_stm32wbxx.c
+            
+        
+        
+            STM32WBxx_HAL_Driver
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_cortex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_gpio.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_hsem.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_ipcc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rtc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rtc_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_uart.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_uart_ex.c
+            
+        
+    
+    
+        Middlewares
+        
+            STM32_WPAN
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_gap_aci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_gatt_aci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_hal_aci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_hci_le.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_l2cap_aci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\dbg_trace.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\svc\Src\dis.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\hci_tl.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\hci_tl_if.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\svc\Src\hrs.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\template\osal.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\otp.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\shci\shci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\shci_tl.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\shci_tl_if.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\stm_list.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\stm_queue.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\svc\Src\svc_ctl.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\tl_mbox.c
+            
+        
+    
+    
+        Utilities
+        
+            $PROJ_DIR$\..\..\..\..\..\..\Utilities\lpm\tiny_lpm\stm32_lpm.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\..\..\Utilities\sequencer\stm32_seq.c
+        
+    
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/Project.eww
new file mode 100644
index 000000000..5406999f5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\BLE_HeartRate_ota.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/stm32wb35xx_flash_cm4_ota.icf b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/stm32wb35xx_flash_cm4_ota.icf
new file mode 100644
index 000000000..cd8727641
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/EWARM/stm32wb35xx_flash_cm4_ota.icf
@@ -0,0 +1,44 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08007000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08007000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+define region OTA_TAG_region   = mem:[from (__ICFEDIT_region_ROM_start__ + 0x140)   to (__ICFEDIT_region_ROM_start__ + 0x140 + 4)];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+keep { section TAG_OTA_START};
+keep { section TAG_OTA_END };
+place in OTA_TAG_region   { section TAG_OTA_START };
+place in ROM_region   { readonly, last section TAG_OTA_END };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/app_ble.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/app_ble.c
new file mode 100644
index 000000000..926354cca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/app_ble.c
@@ -0,0 +1,1094 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    app_ble.c
+ * @author  MCD Application Team
+ * @brief   BLE Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+#include "app_common.h"
+
+#include "dbg_trace.h"
+#include "ble.h"
+#include "tl.h"
+#include "app_ble.h"
+
+#include "stm32_seq.h"
+#include "shci.h"
+#include "stm32_lpm.h"
+#include "otp.h"
+#include "dis_app.h"
+#include "hrs_app.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+
+/**
+ * security parameters structure
+ */ 
+typedef struct _tSecurityParams
+{
+  /**
+   * IO capability of the device
+   */
+  uint8_t ioCapability;
+
+  /**
+   * Authentication requirement of the device
+   * Man In the Middle protection required?
+   */
+  uint8_t mitm_mode;
+
+  /**
+   * bonding mode of the device
+   */
+  uint8_t bonding_mode;
+
+  /**
+   * Flag to tell whether OOB data has
+   * to be used during the pairing process
+   */
+  uint8_t OOB_Data_Present; 
+
+  /**
+   * OOB data to be used in the pairing process if
+   * OOB_Data_Present is set to TRUE
+   */
+  uint8_t OOB_Data[16]; 
+
+  /**
+   * this variable indicates whether to use a fixed pin
+   * during the pairing process or a passkey has to be
+   * requested to the application during the pairing process
+   * 0 implies use fixed pin and 1 implies request for passkey
+   */
+  uint8_t Use_Fixed_Pin; 
+
+  /**
+   * minimum encryption key size requirement
+   */
+  uint8_t encryptionKeySizeMin;
+
+  /**
+   * maximum encryption key size requirement
+   */
+  uint8_t encryptionKeySizeMax;
+
+  /**
+   * fixed pin to be used in the pairing process if
+   * Use_Fixed_Pin is set to 1
+   */
+  uint32_t Fixed_Pin;
+
+  /**
+   * this flag indicates whether the host has to initiate
+   * the security, wait for pairing or does not have any security
+   * requirements.\n
+   * 0x00 : no security required
+   * 0x01 : host should initiate security by sending the slave security
+   *        request command
+   * 0x02 : host need not send the clave security request but it
+   * has to wait for paiirng to complete before doing any other
+   * processing
+   */
+  uint8_t initiateSecurity;
+}tSecurityParams;
+
+/**
+ * global context
+ * contains the variables common to all 
+ * services
+ */ 
+typedef struct _tBLEProfileGlobalContext
+{
+
+  /**
+   * security requirements of the host
+   */ 
+  tSecurityParams bleSecurityParam;
+
+  /**
+   * gap service handle
+   */
+  uint16_t gapServiceHandle;
+
+  /**
+   * device name characteristic handle
+   */ 
+  uint16_t devNameCharHandle;
+
+  /**
+   * appearance characteristic handle
+   */ 
+  uint16_t appearanceCharHandle;
+
+  /**
+   * connection handle of the current active connection
+   * When not in connection, the handle is set to 0xFFFF
+   */ 
+  uint16_t connectionHandle;
+
+  /**
+   * length of the UUID list to be used while advertising
+   */ 
+  uint8_t advtServUUIDlen;
+
+  /**
+   * the UUID list to be used while advertising
+   */ 
+  uint8_t advtServUUID[100];
+
+}BleGlobalContext_t;
+
+typedef struct
+{
+  BleGlobalContext_t BleApplicationContext_legacy;
+   APP_BLE_ConnStatus_t Device_Connection_Status;
+   /**
+   * ID of the Advertising Timeout
+   */
+   uint8_t Advertising_mgr_timer_Id;
+
+}BleApplicationContext_t;
+/* USER CODE BEGIN PTD */
+  
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+#define APPBLE_GAP_DEVICE_NAME_LENGTH 7
+#define FAST_ADV_TIMEOUT               (30*1000*1000/CFG_TS_TICK_VAL) /**< 30s */
+#define INITIAL_ADV_TIMEOUT            (60*1000*1000/CFG_TS_TICK_VAL) /**< 60s */
+
+#define BD_ADDR_SIZE_LOCAL    6
+
+/* USER CODE BEGIN PD */
+#define LED_ON_TIMEOUT                 (0.005*1000*1000/CFG_TS_TICK_VAL) /**< 5ms */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static TL_CmdPacket_t BleCmdBuffer;
+
+static const uint8_t M_bd_addr[BD_ADDR_SIZE_LOCAL] =
+    {
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x0000000000FF)),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x00000000FF00) >> 8),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x000000FF0000) >> 16),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x0000FF000000) >> 24),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x00FF00000000) >> 32),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0xFF0000000000) >> 40)
+    };
+
+static uint8_t bd_addr_udn[BD_ADDR_SIZE_LOCAL];
+
+/**
+*   Identity root key used to derive LTK and CSRK 
+*/
+static const uint8_t BLE_CFG_IR_VALUE[16] = CFG_BLE_IRK;
+
+/**
+* Encryption root key used to derive LTK and CSRK
+*/
+static const uint8_t BLE_CFG_ER_VALUE[16] = CFG_BLE_ERK;
+
+/**
+ * These are the two tags used to manage a power failure during OTA
+ * The MagicKeywordAdress shall be mapped @0x140 from start of the binary image
+ * The MagicKeywordvalue is checked in the ble_ota application
+ */
+PLACE_IN_SECTION("TAG_OTA_END") const uint32_t MagicKeywordValue = 0x94448A29 ;
+PLACE_IN_SECTION("TAG_OTA_START") const uint32_t MagicKeywordAddress = (uint32_t)&MagicKeywordValue;
+
+PLACE_IN_SECTION("BLE_APP_CONTEXT") static BleApplicationContext_t BleApplicationContext;
+PLACE_IN_SECTION("BLE_APP_CONTEXT") static uint16_t AdvIntervalMin, AdvIntervalMax;
+
+static const char local_name[] = { AD_TYPE_COMPLETE_LOCAL_NAME ,'H','R','S','T','M'};
+uint8_t  manuf_data[14] = {
+    sizeof(manuf_data)-1, AD_TYPE_MANUFACTURER_SPECIFIC_DATA,
+    0x01/*SKD version */,
+    0x00 /* Generic*/,
+    0x00 /* GROUP A Feature  */, 
+    0x00 /* GROUP A Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00, /* BLE MAC start -MSB */
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00, /* BLE MAC stop */
+
+};
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+static void BLE_UserEvtRx( void * pPayload );
+static void BLE_StatusNot( HCI_TL_CmdStatus_t status );
+static void Ble_Tl_Init( void );
+static void Ble_Hci_Gap_Gatt_Init(void);
+static const uint8_t* BleGetBdAddress( void );
+static void Adv_Request( APP_BLE_ConnStatus_t New_Status );
+static void Add_Advertisment_Service_UUID( uint16_t servUUID );
+static void Adv_Mgr( void );
+static void Adv_Update( void );
+
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APP_BLE_Init( void )
+{
+/* USER CODE BEGIN APP_BLE_Init_1 */
+
+/* USER CODE END APP_BLE_Init_1 */
+  SHCI_C2_Ble_Init_Cmd_Packet_t ble_init_cmd_packet =
+  {
+    {{0,0,0}},                          /**< Header unused */
+    {0,                                 /** pBleBufferAddress not used */
+    0,                                  /** BleBufferSize not used */
+    CFG_BLE_NUM_GATT_ATTRIBUTES,
+    CFG_BLE_NUM_GATT_SERVICES,
+    CFG_BLE_ATT_VALUE_ARRAY_SIZE,
+    CFG_BLE_NUM_LINK,
+    CFG_BLE_DATA_LENGTH_EXTENSION,
+    CFG_BLE_PREPARE_WRITE_LIST_SIZE,
+    CFG_BLE_MBLOCK_COUNT,
+    CFG_BLE_MAX_ATT_MTU,
+    CFG_BLE_SLAVE_SCA,
+    CFG_BLE_MASTER_SCA,
+    CFG_BLE_LSE_SOURCE,
+    CFG_BLE_MAX_CONN_EVENT_LENGTH,
+    CFG_BLE_HSE_STARTUP_TIME,
+    CFG_BLE_VITERBI_MODE,
+    CFG_BLE_LL_ONLY,
+    0}
+  };
+
+  /**
+   * Initialize Ble Transport Layer
+   */
+  Ble_Tl_Init( );
+
+  /**
+   * Do not allow standby in the application
+   */
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP_BLE, UTIL_LPM_DISABLE);
+
+  /**
+   * Register the hci transport layer to handle BLE User Asynchronous Events
+   */
+  UTIL_SEQ_RegTask( 1<data;
+
+  switch (event_pckt->evt)
+  {
+    case EVT_DISCONN_COMPLETE:
+    {
+      hci_disconnection_complete_event_rp0 *disconnection_complete_event;
+      disconnection_complete_event = (hci_disconnection_complete_event_rp0 *) event_pckt->data;
+
+      if (disconnection_complete_event->Connection_Handle == BleApplicationContext.BleApplicationContext_legacy.connectionHandle)
+      {
+        BleApplicationContext.BleApplicationContext_legacy.connectionHandle = 0;
+        BleApplicationContext.Device_Connection_Status = APP_BLE_IDLE;
+
+        APP_DBG_MSG("\r\n\r** DISCONNECTION EVENT WITH CLIENT \n");
+      }
+
+      /* restart advertising */
+      Adv_Request(APP_BLE_FAST_ADV);
+}
+
+    break; /* EVT_DISCONN_COMPLETE */
+
+    case EVT_LE_META_EVENT:
+    {
+      meta_evt = (evt_le_meta_event*) event_pckt->data;
+      /* USER CODE BEGIN EVT_LE_META_EVENT */
+
+      /* USER CODE END EVT_LE_META_EVENT */
+      switch (meta_evt->subevent)
+      {
+        case EVT_LE_CONN_UPDATE_COMPLETE: 
+          APP_DBG_MSG("\r\n\r** CONNECTION UPDATE EVENT WITH CLIENT \n");
+
+          /* USER CODE BEGIN EVT_LE_CONN_UPDATE_COMPLETE */
+
+          /* USER CODE END EVT_LE_CONN_UPDATE_COMPLETE */
+          break;
+        case EVT_LE_PHY_UPDATE_COMPLETE:
+          APP_DBG_MSG("EVT_UPDATE_PHY_COMPLETE \n");
+
+          evt_le_phy_update_complete = (hci_le_phy_update_complete_event_rp0*)meta_evt->data;
+          if (evt_le_phy_update_complete->Status == 0)
+          {
+            APP_DBG_MSG("EVT_UPDATE_PHY_COMPLETE, status ok \n");
+          }
+          else
+          {
+            APP_DBG_MSG("EVT_UPDATE_PHY_COMPLETE, status nok \n");
+          }
+         
+      ret = hci_le_read_phy(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,&TX_PHY,&RX_PHY);
+      if (ret == BLE_STATUS_SUCCESS)
+      {
+        APP_DBG_MSG("Read_PHY success \n");
+       
+        if ((TX_PHY == TX_2M) && (RX_PHY == RX_2M))
+        {
+          APP_DBG_MSG("PHY Param  TX= %d, RX= %d \n", TX_PHY, RX_PHY);
+        }
+        else
+        {
+          APP_DBG_MSG("PHY Param  TX= %d, RX= %d \n", TX_PHY, RX_PHY);
+        } 
+      }
+      else
+      {
+        APP_DBG_MSG("Read conf not succeess \n");
+      }
+          
+          break;  
+          
+        case EVT_LE_CONN_COMPLETE:
+          {
+          hci_le_connection_complete_event_rp0 *connection_complete_event;
+
+          /**
+           * The connection is done, there is no need anymore to schedule the LP ADV
+           */
+          connection_complete_event = (hci_le_connection_complete_event_rp0 *) meta_evt->data;
+          
+          HW_TS_Stop(BleApplicationContext.Advertising_mgr_timer_Id);
+
+          APP_DBG_MSG("EVT_LE_CONN_COMPLETE for connection handle 0x%x\n",
+          connection_complete_event->Connection_Handle);
+            if (BleApplicationContext.Device_Connection_Status == APP_BLE_LP_CONNECTING)
+            {
+              /* Connection as client */
+              BleApplicationContext.Device_Connection_Status = APP_BLE_CONNECTED_CLIENT;
+            }
+            else
+            {
+              /* Connection as server */
+              BleApplicationContext.Device_Connection_Status = APP_BLE_CONNECTED_SERVER;
+            }
+            BleApplicationContext.BleApplicationContext_legacy.connectionHandle =
+                connection_complete_event->Connection_Handle;
+          /* USER CODE BEGIN HCI_EVT_LE_CONN_COMPLETE */
+
+          /* USER CODE END HCI_EVT_LE_CONN_COMPLETE */
+          }
+        break; /* HCI_EVT_LE_CONN_COMPLETE */
+
+        default:
+          /* USER CODE BEGIN SUBEVENT_DEFAULT */
+
+          /* USER CODE END SUBEVENT_DEFAULT */
+          break;
+      }
+    }
+    break; /* HCI_EVT_LE_META_EVENT */
+
+    case EVT_VENDOR:
+      blue_evt = (evt_blue_aci*) event_pckt->data;
+      /* USER CODE BEGIN EVT_VENDOR */
+
+      /* USER CODE END EVT_VENDOR */
+      switch (blue_evt->ecode)
+      {
+      /* USER CODE BEGIN ecode */
+        aci_gap_pairing_complete_event_rp0 *pairing_complete;
+
+      case EVT_BLUE_GAP_LIMITED_DISCOVERABLE: 
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_LIMITED_DISCOVERABLE \n");
+          break; /* EVT_BLUE_GAP_LIMITED_DISCOVERABLE */
+          
+      case EVT_BLUE_GAP_PASS_KEY_REQUEST:  
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_PASS_KEY_REQUEST \n");
+
+        aci_gap_pass_key_resp(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,123456);
+
+        APP_DBG_MSG("\r\n\r** aci_gap_pass_key_resp \n");
+          break; /* EVT_BLUE_GAP_PASS_KEY_REQUEST */
+
+      case EVT_BLUE_GAP_AUTHORIZATION_REQUEST:    
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_AUTHORIZATION_REQUEST \n");
+          break; /* EVT_BLUE_GAP_AUTHORIZATION_REQUEST */
+
+      case EVT_BLUE_GAP_SLAVE_SECURITY_INITIATED:   
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_SLAVE_SECURITY_INITIATED \n");
+          break; /* EVT_BLUE_GAP_SLAVE_SECURITY_INITIATED */
+
+      case EVT_BLUE_GAP_BOND_LOST:    
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_BOND_LOST \n");
+          aci_gap_allow_rebond(BleApplicationContext.BleApplicationContext_legacy.connectionHandle);
+        APP_DBG_MSG("\r\n\r** Send allow rebond \n");
+          break; /* EVT_BLUE_GAP_BOND_LOST */
+
+      case EVT_BLUE_GAP_DEVICE_FOUND:  
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_DEVICE_FOUND \n");
+          break; /* EVT_BLUE_GAP_DEVICE_FOUND */
+
+      case EVT_BLUE_GAP_ADDR_NOT_RESOLVED:
+         APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_DEVICE_FOUND \n");
+          break; /* EVT_BLUE_GAP_DEVICE_FOUND */
+      
+      case (EVT_BLUE_GAP_KEYPRESS_NOTIFICATION):
+         APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_KEYPRESS_NOTIFICATION \n");
+          break; /* EVT_BLUE_GAP_KEY_PRESS_NOTIFICATION */    
+
+       case (EVT_BLUE_GAP_NUMERIC_COMPARISON_VALUE):
+          APP_DBG_MSG("numeric_value = %d\n",
+                      ((aci_gap_numeric_comparison_value_event_rp0 *)(blue_evt->data))->Numeric_Value);
+
+          APP_DBG_MSG("Hex_value = %x\n",
+                      ((aci_gap_numeric_comparison_value_event_rp0 *)(blue_evt->data))->Numeric_Value);
+
+          aci_gap_numeric_comparison_value_confirm_yesno(BleApplicationContext.BleApplicationContext_legacy.connectionHandle, 1); /* CONFIRM_YES = 1 */
+
+          APP_DBG_MSG("\r\n\r** aci_gap_numeric_comparison_value_confirm_yesno-->YES \n");
+          break;
+
+          case (EVT_BLUE_GAP_PAIRING_CMPLT):
+          {
+            pairing_complete = (aci_gap_pairing_complete_event_rp0*)blue_evt->data;
+
+            APP_DBG_MSG("BLE_CTRL_App_Notification: EVT_BLUE_GAP_PAIRING_CMPLT, pairing_complete->Status = %d\n",pairing_complete->Status);
+            if (pairing_complete->Status == 0)
+            {
+              APP_DBG_MSG("\r\n\r** Pairing OK \n");
+            }
+            else
+            {
+              APP_DBG_MSG("\r\n\r** Pairing KO \n");
+            }
+          }
+           break;    
+
+      /* USER CODE END ecode */
+        case EVT_BLUE_GAP_PROCEDURE_COMPLETE:
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_PROCEDURE_COMPLETE \n");
+        /* USER CODE BEGIN EVT_BLUE_GAP_PROCEDURE_COMPLETE */
+
+        /* USER CODE END EVT_BLUE_GAP_PROCEDURE_COMPLETE */
+        break; /* EVT_BLUE_GAP_PROCEDURE_COMPLETE */
+      }
+      break; /* EVT_VENDOR */
+
+        default:
+        /* USER CODE BEGIN ECODE_DEFAULT*/
+
+        /* USER CODE END ECODE_DEFAULT*/
+          break;
+  }
+
+  return (SVCCTL_UserEvtFlowEnable);
+}
+
+APP_BLE_ConnStatus_t APP_BLE_Get_Server_Connection_Status(void)
+{
+    return BleApplicationContext.Device_Connection_Status;
+}
+
+/* USER CODE BEGIN FD*/
+void APP_BLE_Key_Button1_Action(void)
+{
+  tBleStatus ret = BLE_STATUS_INVALID_PARAMS;
+  ret = aci_gap_clear_security_db();
+      if (ret == BLE_STATUS_SUCCESS)
+      {
+        APP_DBG_MSG("Successfully aci_gap_clear_security_db()\n");
+      }
+      else
+      {
+        APP_DBG_MSG("aci_gap_clear_security_db() Failed , result: %d \n", ret);
+      }
+}
+
+void APP_BLE_Key_Button2_Action(void)
+{
+  tBleStatus ret = BLE_STATUS_INVALID_PARAMS;
+  ret = aci_gap_slave_security_req(BleApplicationContext.BleApplicationContext_legacy.connectionHandle); 
+  if (ret == BLE_STATUS_SUCCESS)
+      {
+        APP_DBG_MSG("Successfully aci_gap_slave_security_req()");
+      }
+      else
+      {
+        APP_DBG_MSG("aci_gap_slave_security_req() Failed , result: %d \n", ret);
+      }
+}
+  
+void APP_BLE_Key_Button3_Action(void)
+{
+  uint8_t TX_PHY, RX_PHY;
+  tBleStatus ret = BLE_STATUS_INVALID_PARAMS;
+  ret = hci_le_read_phy(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,&TX_PHY,&RX_PHY);
+      if (ret == BLE_STATUS_SUCCESS)
+      {
+        APP_DBG_MSG("Read_PHY success \n");
+        APP_DBG_MSG("PHY Param  TX= %d, RX= %d \n", TX_PHY, RX_PHY);
+        if ((TX_PHY == TX_2M) && (RX_PHY == RX_2M))
+        {
+          APP_DBG_MSG("hci_le_set_phy PHY Param  TX= %d, RX= %d \n", TX_1M, RX_1M);
+          ret = hci_le_set_phy(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,ALL_PHYS_PREFERENCE,TX_1M,RX_1M,0);
+        }
+        else
+        {
+          APP_DBG_MSG("hci_le_set_phy PHY Param  TX= %d, RX= %d \n", TX_2M_PREFERRED, RX_2M_PREFERRED);
+          ret = hci_le_set_phy(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,ALL_PHYS_PREFERENCE,TX_2M_PREFERRED,RX_2M_PREFERRED,0);
+        } 
+      }
+      else
+      {
+        APP_DBG_MSG("Read conf not succeess \n");
+}
+
+        if (ret == BLE_STATUS_SUCCESS)
+        {
+          APP_DBG_MSG("set PHY cmd ok\n");
+        }
+        else 
+{
+          APP_DBG_MSG("set PHY cmd NOK\n");
+        }
+}
+
+/* USER CODE END FD*/
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void Ble_Tl_Init( void )
+{
+  HCI_TL_HciInitConf_t Hci_Tl_Init_Conf;
+
+  Hci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&BleCmdBuffer;
+  Hci_Tl_Init_Conf.StatusNotCallBack = BLE_StatusNot;
+  hci_init(BLE_UserEvtRx, (void*) &Hci_Tl_Init_Conf);
+
+  return;
+}
+
+ static void Ble_Hci_Gap_Gatt_Init(void){
+
+  uint8_t role;
+  uint8_t index;
+  uint16_t gap_service_handle, gap_dev_name_char_handle, gap_appearance_char_handle;
+  const uint8_t *bd_addr;
+  uint32_t srd_bd_addr[2];
+  uint16_t appearance[1] = { BLE_CFG_GAP_APPEARANCE }; 
+
+  /**
+   * Initialize HCI layer
+   */
+  /*HCI Reset to synchronise BLE Stack*/
+  hci_reset();
+
+  /**
+   * Write the BD Address
+   */
+
+  bd_addr = BleGetBdAddress();
+  aci_hal_write_config_data(CONFIG_DATA_PUBADDR_OFFSET,
+                            CONFIG_DATA_PUBADDR_LEN,
+                            (uint8_t*) bd_addr);
+
+  /* BLE MAC in ADV Packet */
+  manuf_data[ sizeof(manuf_data)-6] = bd_addr[5];
+  manuf_data[ sizeof(manuf_data)-5] = bd_addr[4];
+  manuf_data[ sizeof(manuf_data)-4] = bd_addr[3];
+  manuf_data[ sizeof(manuf_data)-3] = bd_addr[2];
+  manuf_data[ sizeof(manuf_data)-2] = bd_addr[1];
+  manuf_data[ sizeof(manuf_data)-1] = bd_addr[0];
+  
+  /**
+   * Write Identity root key used to derive LTK and CSRK 
+   */
+    aci_hal_write_config_data(CONFIG_DATA_IR_OFFSET,
+    CONFIG_DATA_IR_LEN,
+                            (uint8_t*) BLE_CFG_IR_VALUE);
+    
+   /**
+   * Write Encryption root key used to derive LTK and CSRK
+   */
+    aci_hal_write_config_data(CONFIG_DATA_ER_OFFSET,
+    CONFIG_DATA_ER_LEN,
+                            (uint8_t*) BLE_CFG_ER_VALUE);
+
+   /**
+   * Write random bd_address
+   */
+   /* random_bd_address = R_bd_address;
+    aci_hal_write_config_data(CONFIG_DATA_RANDOM_ADDRESS_WR,
+    CONFIG_DATA_RANDOM_ADDRESS_LEN,
+                            (uint8_t*) random_bd_address);
+  */
+
+  /**
+   * Static random Address
+   * The two upper bits shall be set to 1
+   * The lowest 32bits is read from the UDN to differentiate between devices
+   * The RNG may be used to provide a random number on each power on
+   */
+  srd_bd_addr[1] =  0x0000ED6E;
+  srd_bd_addr[0] =  LL_FLASH_GetUDN( );
+  aci_hal_write_config_data( CONFIG_DATA_RANDOM_ADDRESS_OFFSET, CONFIG_DATA_RANDOM_ADDRESS_LEN, (uint8_t*)srd_bd_addr );
+
+  /**
+   * Write Identity root key used to derive LTK and CSRK 
+   */
+    aci_hal_write_config_data( CONFIG_DATA_IR_OFFSET, CONFIG_DATA_IR_LEN, (uint8_t*)BLE_CFG_IR_VALUE );
+    
+   /**
+   * Write Encryption root key used to derive LTK and CSRK
+   */
+    aci_hal_write_config_data( CONFIG_DATA_ER_OFFSET, CONFIG_DATA_ER_LEN, (uint8_t*)BLE_CFG_ER_VALUE );
+
+  /**
+   * Set TX Power to 0dBm.
+   */
+  aci_hal_set_tx_power_level(1, CFG_TX_POWER);
+
+  /**
+   * Initialize GATT interface
+   */
+  aci_gatt_init();
+
+  /**
+   * Initialize GAP interface
+   */
+  role = 0;
+
+#if (BLE_CFG_PERIPHERAL == 1)
+  role |= GAP_PERIPHERAL_ROLE;
+#endif
+
+#if (BLE_CFG_CENTRAL == 1)
+  role |= GAP_CENTRAL_ROLE;
+#endif
+
+  if (role > 0)
+  {
+    const char *name = "STM32WB";
+    aci_gap_init(role, 0,
+                 APPBLE_GAP_DEVICE_NAME_LENGTH,
+                 &gap_service_handle, &gap_dev_name_char_handle, &gap_appearance_char_handle);
+
+    if (aci_gatt_update_char_value(gap_service_handle, gap_dev_name_char_handle, 0, strlen(name), (uint8_t *) name))
+    {
+      BLE_DBG_SVCCTL_MSG("Device Name aci_gatt_update_char_value failed.\n");
+    }
+  }
+
+  if(aci_gatt_update_char_value(gap_service_handle,
+                                gap_appearance_char_handle,
+                                0,
+                                2,
+                                (uint8_t *)&appearance))
+  {
+    BLE_DBG_SVCCTL_MSG("Appearance aci_gatt_update_char_value failed.\n");
+  }
+/**
+   * Initialize Default PHY
+   */
+  hci_le_set_default_phy(ALL_PHYS_PREFERENCE,TX_2M_PREFERRED,RX_2M_PREFERRED); 
+
+  /**
+   * Initialize IO capability
+   */
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.ioCapability = CFG_IO_CAPABILITY;
+  aci_gap_set_io_capability(BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.ioCapability);
+
+  /**
+   * Initialize authentication
+   */
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode = CFG_MITM_PROTECTION;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data_Present = 0;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin = 8;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax = 16;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin = 1;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin = 111111;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode = 1;
+  for (index = 0; index < 16; index++)
+  {
+    BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data[index] = (uint8_t) index;
+  }
+
+  aci_gap_set_authentication_requirement(BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode,
+                                         1,
+                                         0,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin,
+0
+  );
+
+  /**
+   * Initialize whitelist
+   */
+   if (BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode)
+   {
+     aci_gap_configure_whitelist();
+   }
+}
+
+static void Adv_Request(APP_BLE_ConnStatus_t New_Status)
+{
+  tBleStatus ret = BLE_STATUS_INVALID_PARAMS;
+  uint16_t Min_Inter, Max_Inter;
+ 
+  if (New_Status == APP_BLE_FAST_ADV)
+  {
+    Min_Inter = AdvIntervalMin;
+    Max_Inter = AdvIntervalMax;
+  }
+  else
+  {
+    Min_Inter = CFG_LP_CONN_ADV_INTERVAL_MIN;
+    Max_Inter = CFG_LP_CONN_ADV_INTERVAL_MAX;
+  }
+
+    /**
+     * Stop the timer, it will be restarted for a new shot
+     * It does not hurt if the timer was not running
+     */
+    HW_TS_Stop(BleApplicationContext.Advertising_mgr_timer_Id);
+
+    APP_DBG_MSG("First index in %d state \n", BleApplicationContext.Device_Connection_Status);
+
+    if ((New_Status == APP_BLE_LP_ADV)
+        && ((BleApplicationContext.Device_Connection_Status == APP_BLE_FAST_ADV)
+            || (BleApplicationContext.Device_Connection_Status == APP_BLE_LP_ADV)))
+    {
+      /* Connection in ADVERTISE mode have to stop the current advertising */
+      ret = aci_gap_set_non_discoverable();
+      if (ret == BLE_STATUS_SUCCESS)
+      {
+        APP_DBG_MSG("Successfully Stopped Advertising \n");
+        }
+      else
+      {
+        APP_DBG_MSG("Stop Advertising Failed , result: %d \n", ret);
+        }
+    }
+
+    BleApplicationContext.Device_Connection_Status = New_Status;
+    /* Start Fast or Low Power Advertising */
+    ret = aci_gap_set_discoverable(
+        ADV_IND,
+        Min_Inter,
+        Max_Inter,
+        PUBLIC_ADDR,
+        NO_WHITE_LIST_USE, /* use white list */
+        sizeof(local_name),
+        (uint8_t*) &local_name,
+        BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen,
+        BleApplicationContext.BleApplicationContext_legacy.advtServUUID,
+        0,
+        0);
+    /* Update Advertising data */
+    ret = aci_gap_update_adv_data(sizeof(manuf_data), (uint8_t*) manuf_data);
+
+     if (ret == BLE_STATUS_SUCCESS)
+    {
+      if (New_Status == APP_BLE_FAST_ADV)
+      {
+        APP_DBG_MSG("Successfully Start Fast Advertising \n" );
+        /* Start Timer to STOP ADV - TIMEOUT */
+        HW_TS_Start(BleApplicationContext.Advertising_mgr_timer_Id, INITIAL_ADV_TIMEOUT);
+      }
+      else
+      {
+        APP_DBG_MSG("Successfully Start Low Power Advertising \n");
+        }
+    }
+    else
+    {
+      if (New_Status == APP_BLE_FAST_ADV)
+      {
+        APP_DBG_MSG("Start Fast Advertising Failed , result: %d \n", ret);
+      }
+      else
+      {
+        APP_DBG_MSG("Start Low Power Advertising Failed , result: %d \n", ret);
+      }
+    }
+
+  return;
+}
+
+const uint8_t* BleGetBdAddress( void )
+{
+  uint8_t *otp_addr;
+  const uint8_t *bd_addr;
+  uint32_t udn;
+  uint32_t company_id;
+  uint32_t device_id;
+
+  udn = LL_FLASH_GetUDN();
+
+  if(udn != 0xFFFFFFFF)
+  {
+    company_id = LL_FLASH_GetSTCompanyID();
+    device_id = LL_FLASH_GetDeviceID();
+
+    bd_addr_udn[0] = (uint8_t)(udn & 0x000000FF);
+    bd_addr_udn[1] = (uint8_t)( (udn & 0x0000FF00) >> 8 );
+    bd_addr_udn[2] = (uint8_t)( (udn & 0x00FF0000) >> 16 );
+    bd_addr_udn[3] = (uint8_t)device_id;
+    bd_addr_udn[4] = (uint8_t)(company_id & 0x000000FF);;
+    bd_addr_udn[5] = (uint8_t)( (company_id & 0x0000FF00) >> 8 );
+
+    bd_addr = (const uint8_t *)bd_addr_udn;
+  }
+  else
+  {
+    otp_addr = OTP_Read(0);
+    if(otp_addr)
+    {
+      bd_addr = ((OTP_ID0_t*)otp_addr)->bd_address;
+    }
+    else
+    {
+      bd_addr = M_bd_addr;
+    }
+
+  }
+
+  return bd_addr;
+}
+
+/* USER CODE BEGIN FD_LOCAL_FUNCTION */
+
+/* USER CODE END FD_LOCAL_FUNCTION */
+
+/*************************************************************
+ *
+ *SPECIFIC FUNCTIONS
+ *
+ *************************************************************/
+static void Add_Advertisment_Service_UUID( uint16_t servUUID )
+{
+  BleApplicationContext.BleApplicationContext_legacy.advtServUUID[BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen] =
+      (uint8_t) (servUUID & 0xFF);
+  BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen++;
+  BleApplicationContext.BleApplicationContext_legacy.advtServUUID[BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen] =
+      (uint8_t) (servUUID >> 8) & 0xFF;
+  BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen++;
+
+  return;
+}
+
+static void Adv_Mgr( void )
+{
+  /**
+   * The code shall be executed in the background as an aci command may be sent
+   * The background is the only place where the application can make sure a new aci command
+   * is not sent if there is a pending one
+   */
+  UTIL_SEQ_SetTask(1 << CFG_TASK_ADV_UPDATE_ID, CFG_SCH_PRIO_0);
+
+  return;
+}
+
+static void Adv_Update( void )
+{
+  Adv_Request(APP_BLE_LP_ADV);
+
+  return;
+}
+
+/* USER CODE BEGIN FD_SPECIFIC_FUNCTIONS */
+
+/* USER CODE END FD_SPECIFIC_FUNCTIONS */
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+void hci_notify_asynch_evt(void* pdata)
+{
+  UTIL_SEQ_SetTask(1 << CFG_TASK_HCI_ASYNCH_EVT_ID, CFG_SCH_PRIO_0);
+  return;
+}
+
+void hci_cmd_resp_release(uint32_t flag)
+{
+  UTIL_SEQ_SetEvt(1 << CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID);
+  return;
+}
+
+void hci_cmd_resp_wait(uint32_t timeout)
+{
+  UTIL_SEQ_WaitEvt(1 << CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID);
+  return;
+}
+
+static void BLE_UserEvtRx( void * pPayload )
+{
+  SVCCTL_UserEvtFlowStatus_t svctl_return_status;
+  tHCI_UserEvtRxParam *pParam;
+
+  pParam = (tHCI_UserEvtRxParam *)pPayload; 
+
+  svctl_return_status = SVCCTL_UserEvtRx((void *)&(pParam->pckt->evtserial));
+  if (svctl_return_status != SVCCTL_UserEvtFlowDisable)
+  {
+    pParam->status = HCI_TL_UserEventFlow_Enable;
+  }
+  else
+  {
+    pParam->status = HCI_TL_UserEventFlow_Disable;
+  }
+}
+
+static void BLE_StatusNot( HCI_TL_CmdStatus_t status )
+{
+  uint32_t task_id_list;
+  switch (status)
+  {
+    case HCI_TL_CmdBusy:
+      /**
+       * All tasks that may send an aci/hci commands shall be listed here
+       * This is to prevent a new command is sent while one is already pending
+       */
+      task_id_list = (1 << CFG_LAST_TASK_ID_WITH_HCICMD) - 1;
+      UTIL_SEQ_PauseTask(task_id_list);
+
+      break;
+
+    case HCI_TL_CmdAvailable:
+      /**
+       * All tasks that may send an aci/hci commands shall be listed here
+       * This is to prevent a new command is sent while one is already pending
+       */
+      task_id_list = (1 << CFG_LAST_TASK_ID_WITH_HCICMD) - 1;
+      UTIL_SEQ_ResumeTask(task_id_list);
+
+      break;
+
+    default:
+      break;
+  }
+  return;
+}
+
+void SVCCTL_ResumeUserEventFlow( void )
+{
+  hci_resume_flow();
+  return;
+}
+
+/* USER CODE BEGIN FD_WRAP_FUNCTIONS */
+
+/* USER CODE END FD_WRAP_FUNCTIONS */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/app_ble.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/app_ble.h
new file mode 100644
index 000000000..657ba432b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/app_ble.h
@@ -0,0 +1,88 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    app_ble.h
+  * @author  MCD Application Team
+  * @brief   Header for ble application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_BLE_H
+#define APP_BLE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "hci_tl.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+
+    typedef enum
+    {
+      APP_BLE_IDLE,
+      APP_BLE_FAST_ADV,
+      APP_BLE_LP_ADV,
+      APP_BLE_SCAN,
+      APP_BLE_LP_CONNECTING,
+      APP_BLE_CONNECTED_SERVER,
+      APP_BLE_CONNECTED_CLIENT
+    } APP_BLE_ConnStatus_t;
+    
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */  
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APP_BLE_Init( void ); 
+
+  APP_BLE_ConnStatus_t APP_BLE_Get_Server_Connection_Status(void);
+
+/* USER CODE BEGIN EF */
+void APP_BLE_Key_Button1_Action(void);
+void APP_BLE_Key_Button2_Action(void);
+void APP_BLE_Key_Button3_Action(void);
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*APP_BLE_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/ble_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/ble_conf.h
new file mode 100644
index 000000000..3e0d875d2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/ble_conf.h
@@ -0,0 +1,104 @@
+/**
+ ******************************************************************************
+  * File Name          : App/ble_conf.h
+  * Description        : Configuration file for BLE Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef BLE_CONF_H
+#define BLE_CONF_H
+
+#include "app_conf.h"
+
+/******************************************************************************
+ *
+ * BLE SERVICES CONFIGURATION
+ * blesvc
+ *
+ ******************************************************************************/
+
+ /**
+ * This setting shall be set to '1' if the device needs to support the Peripheral Role
+ * In the MS configuration, both BLE_CFG_PERIPHERAL and BLE_CFG_CENTRAL shall be set to '1'
+ */
+#define BLE_CFG_PERIPHERAL                                                     1
+
+/**
+ * This setting shall be set to '1' if the device needs to support the Central Role
+ * In the MS configuration, both BLE_CFG_PERIPHERAL and BLE_CFG_CENTRAL shall be set to '1'
+ */
+#define BLE_CFG_CENTRAL                                                        0
+
+/**
+ * There is one handler per service enabled
+ * Note: There is no handler for the Device Information Service
+ *
+ * This shall take into account all registered handlers
+ * (from either the provided services or the custom services)
+ */
+#define BLE_CFG_SVC_MAX_NBR_CB                                                 7
+
+#define BLE_CFG_CLT_MAX_NBR_CB                                                 0
+
+/******************************************************************************
+ * Device Information Service (DIS)
+ ******************************************************************************/
+/**< Options: Supported(1) or Not Supported(0) */
+#define BLE_CFG_DIS_MANUFACTURER_NAME_STRING                                   1
+#define BLE_CFG_DIS_MODEL_NUMBER_STRING                                        0
+#define BLE_CFG_DIS_SERIAL_NUMBER_STRING                                       0
+#define BLE_CFG_DIS_HARDWARE_REVISION_STRING                                   0
+#define BLE_CFG_DIS_FIRMWARE_REVISION_STRING                                   0
+#define BLE_CFG_DIS_SOFTWARE_REVISION_STRING                                   0
+#define BLE_CFG_DIS_SYSTEM_ID                                                  0
+#define BLE_CFG_DIS_IEEE_CERTIFICATION                                         0
+#define BLE_CFG_DIS_PNP_ID                                                     0
+
+/**
+ * device information service characteristic lengths
+ */
+#define BLE_CFG_DIS_SYSTEM_ID_LEN_MAX                                        (8)
+#define BLE_CFG_DIS_MODEL_NUMBER_STRING_LEN_MAX                              (32)
+#define BLE_CFG_DIS_SERIAL_NUMBER_STRING_LEN_MAX                             (32)
+#define BLE_CFG_DIS_FIRMWARE_REVISION_STRING_LEN_MAX                         (32)
+#define BLE_CFG_DIS_HARDWARE_REVISION_STRING_LEN_MAX                         (32)
+#define BLE_CFG_DIS_SOFTWARE_REVISION_STRING_LEN_MAX                         (32)
+#define BLE_CFG_DIS_MANUFACTURER_NAME_STRING_LEN_MAX                         (32)
+#define BLE_CFG_DIS_IEEE_CERTIFICATION_LEN_MAX                               (32)
+#define BLE_CFG_DIS_PNP_ID_LEN_MAX                                           (7)
+
+/******************************************************************************
+ * Heart Rate Service (HRS)
+ ******************************************************************************/
+#define BLE_CFG_HRS_BODY_SENSOR_LOCATION_CHAR               1/**< BODY SENSOR LOCATION CHARACTERISTIC */
+#define BLE_CFG_HRS_ENERGY_EXPENDED_INFO_FLAG               1/**< ENERGY EXTENDED INFO FLAG */
+#define BLE_CFG_HRS_ENERGY_RR_INTERVAL_FLAG                 1/**< Max number of RR interval values - Shall not be greater than 9 */
+
+/******************************************************************************
+ * GAP Service - Apprearance
+ ******************************************************************************/
+
+#define BLE_CFG_UNKNOWN_APPEARANCE                  (0)
+#define BLE_CFG_HR_SENSOR_APPEARANCE                (832)
+#define BLE_CFG_GAP_APPEARANCE                      (BLE_CFG_HR_SENSOR_APPEARANCE)
+
+/******************************************************************************
+ * Over The Air Feature (OTA) - STM Proprietary
+ ******************************************************************************/
+#define BLE_CFG_OTA_REBOOT_CHAR         1/**< REBOOT OTA MODE CHARACTERISTIC */
+
+#endif /*BLE_CONF_H */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/ble_dbg_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/ble_dbg_conf.h
new file mode 100644
index 000000000..a24660c50
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/ble_dbg_conf.h
@@ -0,0 +1,199 @@
+/**
+ ******************************************************************************
+  * File Name          : App/ble_dbg_conf.h
+  * Description        : Debug configuration file for BLE Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __BLE_DBG_CONF_H
+#define __BLE_DBG_CONF_H
+
+/**
+ * Enable or Disable traces from BLE
+ */
+
+#define BLE_DBG_APP_EN             0
+#define BLE_DBG_DIS_EN             1
+#define BLE_DBG_HRS_EN             1
+#define BLE_DBG_SVCCTL_EN          1
+#define BLE_DBG_BLS_EN             0
+#define BLE_DBG_HTS_EN             0
+#define BLE_DBG_P2P_STM_EN         0
+
+/**
+ * Macro definition
+ */
+#if ( BLE_DBG_APP_EN != 0 )
+#define BLE_DBG_APP_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_APP_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_DIS_EN != 0 )
+#define BLE_DBG_DIS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_DIS_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_HRS_EN != 0 )
+#define BLE_DBG_HRS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HRS_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_P2P_STM_EN != 0 )
+#define BLE_DBG_P2P_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_P2P_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_TEMPLATE_STM_EN != 0 )
+#define BLE_DBG_TEMPLATE_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_TEMPLATE_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_EDS_STM_EN != 0 )
+#define BLE_DBG_EDS_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_EDS_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_LBS_STM_EN != 0 )
+#define BLE_DBG_LBS_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_LBS_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_SVCCTL_EN != 0 )
+#define BLE_DBG_SVCCTL_MSG          PRINT_MESG_DBG
+#else
+#define BLE_DBG_SVCCTL_MSG          PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_CTS_EN != 0)
+#define BLE_DBG_CTS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_CTS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HIDS_EN != 0)
+#define BLE_DBG_HIDS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_HIDS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_PASS_EN != 0)
+#define BLE_DBG_PASS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_PASS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_BLS_EN != 0)
+#define BLE_DBG_BLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_BLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HTS_EN != 0)
+#define BLE_DBG_HTS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HTS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_ANS_EN != 0)
+#define BLE_DBG_ANS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_ANS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_ESS_EN != 0)
+#define BLE_DBG_ESS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_ESS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_GLS_EN != 0)
+#define BLE_DBG_GLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_GLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_BAS_EN != 0)
+#define BLE_DBG_BAS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_BAS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_RTUS_EN != 0)
+#define BLE_DBG_RTUS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_RTUS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HPS_EN != 0)
+#define BLE_DBG_HPS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HPS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_TPS_EN != 0)
+#define BLE_DBG_TPS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_TPS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_LLS_EN != 0)
+#define BLE_DBG_LLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_LLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_IAS_EN != 0)
+#define BLE_DBG_IAS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_IAS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_WSS_EN != 0)
+#define BLE_DBG_WSS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_WSS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_LNS_EN != 0)
+#define BLE_DBG_LNS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_LNS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_SCPS_EN != 0)
+#define BLE_DBG_SCPS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_SCPS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_DTS_EN != 0)
+#define BLE_DBG_DTS_MSG             PRINT_MESG_DBG
+#define BLE_DBG_DTS_BUF             PRINT_LOG_BUFF_DBG
+#else
+#define BLE_DBG_DTS_MSG             PRINT_NO_MESG
+#define BLE_DBG_DTS_BUF             PRINT_NO_MESG
+#endif
+
+#endif /*__BLE_DBG_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/dis_app.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/dis_app.c
new file mode 100644
index 000000000..59c66fad3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/dis_app.c
@@ -0,0 +1,221 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    dis_app.c
+  * @author  MCD Application Team
+  * @brief   Device Information Service Application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "ble.h"
+#include "dis_app.h"
+
+/* Private includes -----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+#if ((BLE_CFG_DIS_SYSTEM_ID != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+static const uint8_t system_id[BLE_CFG_DIS_SYSTEM_ID_LEN_MAX] = 
+{
+  (uint8_t)((DISAPP_MANUFACTURER_ID & 0xFF0000) >> 16),
+  (uint8_t)((DISAPP_MANUFACTURER_ID & 0x00FF00) >> 8),
+  (uint8_t)(DISAPP_MANUFACTURER_ID & 0x0000FF),
+  0xFE,
+  0xFF,
+  (uint8_t)((DISAPP_OUI & 0xFF0000) >> 16),
+  (uint8_t)((DISAPP_OUI & 0x00FF00) >> 8),
+  (uint8_t)(DISAPP_OUI & 0x0000FF)
+};
+#endif
+
+#if ((BLE_CFG_DIS_IEEE_CERTIFICATION != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+static const uint8_t ieee_id[BLE_CFG_DIS_IEEE_CERTIFICATION_LEN_MAX] = 
+{
+  0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 
+  0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 
+  0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 
+  0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 0xFE, 0xCA, 
+};
+#endif
+#if ((BLE_CFG_DIS_PNP_ID != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+static const uint8_t pnp_id[BLE_CFG_DIS_PNP_ID_LEN_MAX] = 
+{
+  0x1,
+  0xAD, 0xDE,
+  0xDE, 0xDA, 
+  0x01, 0x00
+};
+#endif
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void DISAPP_Init(void)
+{
+/* USER CODE BEGIN DISAPP_Init */
+  DIS_Data_t dis_information_data;
+
+#if ((BLE_CFG_DIS_MANUFACTURER_NAME_STRING != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+  /**
+   * Update MANUFACTURER NAME Information
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t*)DISAPP_MANUFACTURER_NAME;
+  dis_information_data.Length = sizeof(DISAPP_MANUFACTURER_NAME);
+  DIS_UpdateChar(MANUFACTURER_NAME_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_MODEL_NUMBER_STRING != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+  /**
+   * Update MODEL NUMBERInformation
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t*)DISAPP_MODEL_NUMBER;
+  dis_information_data.Length = sizeof(DISAPP_MODEL_NUMBER);
+  DIS_UpdateChar(MODEL_NUMBER_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_SERIAL_NUMBER_STRING != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+  /**
+   * Update SERIAL NUMBERInformation
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t*)DISAPP_SERIAL_NUMBER;
+  dis_information_data.Length = sizeof(DISAPP_SERIAL_NUMBER);
+  DIS_UpdateChar(SERIAL_NUMBER_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_HARDWARE_REVISION_STRING != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+  /**
+   * Update HARDWARE REVISION NUMBERInformation
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t*)DISAPP_HARDWARE_REVISION_NUMBER;
+  dis_information_data.Length = sizeof(DISAPP_HARDWARE_REVISION_NUMBER);
+  DIS_UpdateChar(HARDWARE_REVISION_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_FIRMWARE_REVISION_STRING != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+  /**
+   * Update FIRMWARE REVISION NUMBERInformation
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t*)DISAPP_FIRMWARE_REVISION_NUMBER;
+  dis_information_data.Length = sizeof(DISAPP_FIRMWARE_REVISION_NUMBER);
+  DIS_UpdateChar(FIRMWARE_REVISION_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_SOFTWARE_REVISION_STRING != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+  /**
+   * Update SOFTWARE REVISION NUMBERInformation
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t*)DISAPP_SOFTWARE_REVISION_NUMBER;
+  dis_information_data.Length = sizeof(DISAPP_SOFTWARE_REVISION_NUMBER);
+  DIS_UpdateChar(SOFTWARE_REVISION_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_SYSTEM_ID != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+
+  /**
+   * Update SYSTEM ID Information
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t *)system_id;
+  dis_information_data.Length = BLE_CFG_DIS_SYSTEM_ID_LEN_MAX;
+  DIS_UpdateChar(SYSTEM_ID_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_IEEE_CERTIFICATION != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+
+  /**
+   * Update IEEE CERTIFICATION ID Information
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t *)ieee_id;
+  dis_information_data.Length = BLE_CFG_DIS_IEEE_CERTIFICATION_LEN_MAX;
+  DIS_UpdateChar(IEEE_CERTIFICATION_UUID, &dis_information_data);
+#endif
+
+#if ((BLE_CFG_DIS_PNP_ID != 0) || (CFG_MENU_DEVICE_INFORMATION != 0))
+
+  /**
+   * Update PNP ID Information
+   *
+   * @param UUID
+   * @param pPData
+   * @return
+   */
+  dis_information_data.pPayload = (uint8_t *)pnp_id;
+  dis_information_data.Length = BLE_CFG_DIS_PNP_ID_LEN_MAX;
+  DIS_UpdateChar(PNP_ID_UUID, &dis_information_data);
+#endif
+/* USER CODE END DISAPP_Init */
+}
+
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/dis_app.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/dis_app.h
new file mode 100644
index 000000000..196ec9937
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/dis_app.h
@@ -0,0 +1,77 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    dis_app.h
+  * @author  MCD Application Team
+  * @brief   Header for dis_application.c module
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __DIS_APP_H
+#define __DIS_APP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes -----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros -----------------------------------------------------------*/
+#define DISAPP_MANUFACTURER_NAME              "STM"
+#define DISAPP_MODEL_NUMBER                   "4502-1.0"
+#define DISAPP_SERIAL_NUMBER                  "1.0"
+#define DISAPP_HARDWARE_REVISION_NUMBER       "1.0"
+#define DISAPP_FIRMWARE_REVISION_NUMBER       "1.0"
+#define DISAPP_SOFTWARE_REVISION_NUMBER       "1.0"
+#define DISAPP_OUI                            0x123456
+#define DISAPP_MANUFACTURER_ID                0x9ABCDE
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ------------------------------------------------------- */
+void DISAPP_Init(void);
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__DIS_APP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/hrs_app.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/hrs_app.c
new file mode 100644
index 000000000..e84751eaa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/hrs_app.c
@@ -0,0 +1,230 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    hrs_app.c
+  * @author  MCD Application Team
+  * @brief   Heart Rate Service Application
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "ble.h"
+#include "hrs_app.h"
+#include "stm32_seq.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+typedef struct
+{
+  HRS_BodySensorLocation_t BodySensorLocationChar;
+  HRS_MeasVal_t MeasurementvalueChar;
+  uint8_t ResetEnergyExpended;
+  uint8_t TimerMeasurement_Id;
+
+} HRSAPP_Context_t;
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private defines ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+#define HRSAPP_MEASUREMENT_INTERVAL   (1000000/CFG_TS_TICK_VAL)  /**< 1s */
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/**
+ * START of Section BLE_APP_CONTEXT
+ */
+
+PLACE_IN_SECTION("BLE_APP_CONTEXT") static HRSAPP_Context_t HRSAPP_Context;
+
+/**
+ * END of Section BLE_APP_CONTEXT
+ */
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private functions prototypes-----------------------------------------------*/
+static void HrMeas( void );
+static void HRSAPP_Measurement(void);
+static uint32_t HRSAPP_Read_RTC_SSR_SS ( void );
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void HRS_Notification(HRS_App_Notification_evt_t *pNotification)
+{
+/* USER CODE BEGIN HRS_Notification_1 */
+
+/* USER CODE END HRS_Notification_1 */
+  switch(pNotification->HRS_Evt_Opcode)
+  {
+/* USER CODE BEGIN HRS_Notification_HRS_Evt_Opcode */
+
+/* USER CODE END HRS_Notification_HRS_Evt_Opcode */
+#if (BLE_CFG_HRS_ENERGY_EXPENDED_INFO_FLAG != 0)
+    case HRS_RESET_ENERGY_EXPENDED_EVT:
+/* USER CODE BEGIN HRS_RESET_ENERGY_EXPENDED_EVT */
+      HRSAPP_Context.MeasurementvalueChar.EnergyExpended = 0;
+      HRSAPP_Context.ResetEnergyExpended = 1;
+/* USER CODE END HRS_RESET_ENERGY_EXPENDED_EVT */
+      break;
+#endif
+      
+    case HRS_NOTIFICATION_ENABLED:
+/* USER CODE BEGIN HRS_NOTIFICATION_ENABLED */
+      /**
+       * It could be the enable notification is received twice without the disable notification in between
+       */
+      HW_TS_Stop(HRSAPP_Context.TimerMeasurement_Id);
+      HW_TS_Start(HRSAPP_Context.TimerMeasurement_Id, HRSAPP_MEASUREMENT_INTERVAL);
+/* USER CODE END HRS_NOTIFICATION_ENABLED */
+      break;
+
+    case HRS_NOTIFICATION_DISABLED:
+/* USER CODE BEGIN HRS_NOTIFICATION_DISABLED */
+      HW_TS_Stop(HRSAPP_Context.TimerMeasurement_Id);
+/* USER CODE END HRS_NOTIFICATION_DISABLED */
+      break;
+      
+#if (BLE_CFG_OTA_REBOOT_CHAR != 0)
+    case HRS_STM_BOOT_REQUEST_EVT:
+/* USER CODE BEGIN HRS_STM_BOOT_REQUEST_EVT */
+      *(uint32_t*)SRAM1_BASE = *(uint32_t*)pNotification->DataTransfered.pPayload;
+      NVIC_SystemReset();
+/* USER CODE END HRS_STM_BOOT_REQUEST_EVT */
+      break;
+#endif
+      
+   default:
+/* USER CODE BEGIN HRS_Notification_Default */
+
+/* USER CODE END HRS_Notification_Default */
+      break;
+  }
+/* USER CODE BEGIN HRS_Notification_2 */
+
+/* USER CODE END HRS_Notification_2 */
+  return;
+}
+
+void HRSAPP_Init(void)
+{
+  UTIL_SEQ_RegTask( 1<< CFG_TASK_MEAS_REQ_ID, UTIL_SEQ_RFU, HRSAPP_Measurement );
+/* USER CODE BEGIN HRSAPP_Init */
+  /**
+   * Set Body Sensor Location
+   */
+  HRSAPP_Context.ResetEnergyExpended = 0;
+  HRSAPP_Context.BodySensorLocationChar = HRS_BODY_SENSOR_LOCATION_HAND;
+  HRS_UpdateChar(SENSOR_LOCATION_UUID, (uint8_t *)&HRSAPP_Context.BodySensorLocationChar);
+
+
+  /**
+   * Set Flags for measurement value
+   */
+
+  HRSAPP_Context.MeasurementvalueChar.Flags = ( HRS_HRM_VALUE_FORMAT_UINT16      | 
+                                                  HRS_HRM_SENSOR_CONTACTS_PRESENT   | 
+                                                  HRS_HRM_SENSOR_CONTACTS_SUPPORTED |
+                                                  HRS_HRM_ENERGY_EXPENDED_PRESENT  |
+                                                  HRS_HRM_RR_INTERVAL_PRESENT );
+
+#if (BLE_CFG_HRS_ENERGY_EXPENDED_INFO_FLAG != 0)
+  if(HRSAPP_Context.MeasurementvalueChar.Flags & HRS_HRM_ENERGY_EXPENDED_PRESENT)
+    HRSAPP_Context.MeasurementvalueChar.EnergyExpended = 10;
+#endif
+  
+#if (BLE_CFG_HRS_ENERGY_RR_INTERVAL_FLAG != 0)
+  if(HRSAPP_Context.MeasurementvalueChar.Flags & HRS_HRM_RR_INTERVAL_PRESENT)
+  {
+    uint8_t i;
+    
+    HRSAPP_Context.MeasurementvalueChar.NbreOfValidRRIntervalValues = BLE_CFG_HRS_ENERGY_RR_INTERVAL_FLAG;
+    for(i = 0; i < BLE_CFG_HRS_ENERGY_RR_INTERVAL_FLAG; i++)
+      HRSAPP_Context.MeasurementvalueChar.aRRIntervalValues[i] = 1024;
+  }
+#endif
+  
+  /**
+   * Create timer for Heart Rate Measurement
+   */
+  HW_TS_Create(CFG_TIM_PROC_ID_ISR, &(HRSAPP_Context.TimerMeasurement_Id), hw_ts_Repeated, HrMeas);
+
+/* USER CODE END HRSAPP_Init */
+  return;
+}
+
+static void HRSAPP_Measurement(void)
+{
+/* USER CODE BEGIN HRSAPP_Measurement */
+  uint32_t measurement;
+
+  measurement = ((HRSAPP_Read_RTC_SSR_SS()) & 0x07) + 65;
+
+  HRSAPP_Context.MeasurementvalueChar.MeasurementValue = measurement;
+#if (BLE_CFG_HRS_ENERGY_EXPENDED_INFO_FLAG != 0)
+  if((HRSAPP_Context.MeasurementvalueChar.Flags & HRS_HRM_ENERGY_EXPENDED_PRESENT) &&
+     (HRSAPP_Context.ResetEnergyExpended == 0))
+    HRSAPP_Context.MeasurementvalueChar.EnergyExpended += 5;
+  else if(HRSAPP_Context.ResetEnergyExpended == 1)
+    HRSAPP_Context.ResetEnergyExpended = 0;
+#endif
+
+  HRS_UpdateChar(HEART_RATE_MEASURMENT_UUID, (uint8_t *)&HRSAPP_Context.MeasurementvalueChar);
+
+/* USER CODE END HRSAPP_Measurement */
+  return;
+}
+
+static void HrMeas( void )
+{
+  /**
+   * The code shall be executed in the background as aci command may be sent
+   * The background is the only place where the application can make sure a new aci command
+   * is not sent if there is a pending one
+   */
+  UTIL_SEQ_SetTask( 1<SSR, RTC_SSR_SS)));
+}
+
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/hrs_app.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/hrs_app.h
new file mode 100644
index 000000000..0246d2811
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/App/hrs_app.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    hrs_app.h
+  * @author  MCD Application Team
+  * @brief   Header for hrs_application.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HRS_APP_H
+#define __HRS_APP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+void HRSAPP_Init( void );
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__HRS_APP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/Target/hw_ipcc.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/Target/hw_ipcc.c
new file mode 100644
index 000000000..0f839543a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/STM32_WPAN/Target/hw_ipcc.c
@@ -0,0 +1,523 @@
+/**
+ ******************************************************************************
+  * File Name          : Target/hw_ipcc.c
+  * Description        : Hardware IPCC source file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "mbox_def.h"
+
+/* Global variables ---------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+#define HW_IPCC_TX_PENDING( channel ) ( !(LL_C1_IPCC_IsActiveFlag_CHx( IPCC, channel )) ) &&  (((~(IPCC->C1MR)) & (channel << 16U)))
+#define HW_IPCC_RX_PENDING( channel )  (LL_C2_IPCC_IsActiveFlag_CHx( IPCC, channel )) && (((~(IPCC->C1MR)) & (channel << 0U)))
+
+/* Private macros ------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static void (*FreeBufCb)( void );
+
+/* Private function prototypes -----------------------------------------------*/
+static void HW_IPCC_BLE_EvtHandler( void );
+static void HW_IPCC_BLE_AclDataEvtHandler( void );
+static void HW_IPCC_MM_FreeBufHandler( void );
+static void HW_IPCC_SYS_CmdEvtHandler( void );
+static void HW_IPCC_SYS_EvtHandler( void );
+static void HW_IPCC_TRACES_EvtHandler( void );
+
+#ifdef THREAD_WB
+static void HW_IPCC_OT_CmdEvtHandler( void );
+static void HW_IPCC_THREAD_NotEvtHandler( void );
+static void HW_IPCC_THREAD_CliNotEvtHandler( void );
+#endif
+
+#ifdef MAC_802_15_4_WB
+static void HW_IPCC_MAC_802_15_4_CmdEvtHandler( void );
+static void HW_IPCC_MAC_802_15_4_NotEvtHandler( void );
+#endif
+
+#ifdef ZIGBEE_WB
+static void HW_IPCC_ZIGBEE_CmdEvtHandler( void );
+static void HW_IPCC_ZIGBEE_StackNotifEvtHandler( void );
+static void HW_IPCC_ZIGBEE_CliNotifEvtHandler( void );
+#endif
+
+/* Public function definition -----------------------------------------------*/
+
+/******************************************************************************
+ * INTERRUPT HANDLER
+ ******************************************************************************/
+void HW_IPCC_Rx_Handler( void )
+{
+  if (HW_IPCC_RX_PENDING( HW_IPCC_SYSTEM_EVENT_CHANNEL ))
+  {
+      HW_IPCC_SYS_EvtHandler();
+  }
+#ifdef MAC_802_15_4_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_MAC_802_15_4_NotEvtHandler();
+  }
+#endif /* MAC_802_15_4_WB */
+#ifdef THREAD_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_THREAD_NotEvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_THREAD_CliNotEvtHandler();
+  }
+#endif /* THREAD_WB */
+#ifdef ZIGBEE_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_ZIGBEE_StackNotifEvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
+  {
+      HW_IPCC_ZIGBEE_CliNotifEvtHandler();
+  }
+#endif /* ZIGBEE_WB */
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_BLE_EVENT_CHANNEL ))
+  {
+    HW_IPCC_BLE_EvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_TRACES_CHANNEL ))
+  {
+    HW_IPCC_TRACES_EvtHandler();
+  }
+
+  return;
+}
+
+void HW_IPCC_Tx_Handler( void )
+{
+  if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_SYS_CmdEvtHandler();
+  }
+#ifdef MAC_802_15_4_WB
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_MAC_802_15_4_CmdEvtHandler();
+  }
+#endif /* MAC_802_15_4_WB */
+#ifdef THREAD_WB
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_OT_CmdEvtHandler();
+  }
+#endif /* THREAD_WB */
+#ifdef ZIGBEE_WB
+  if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
+  {
+      HW_IPCC_ZIGBEE_CmdEvtHandler();
+  }
+#endif /* ZIGBEE_WB */
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_SYS_CmdEvtHandler();
+  }
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ))
+  {
+    HW_IPCC_MM_FreeBufHandler();
+  }
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_HCI_ACL_DATA_CHANNEL ))
+  {
+    HW_IPCC_BLE_AclDataEvtHandler();
+  }
+
+  return;
+}
+/******************************************************************************
+ * GENERAL
+ ******************************************************************************/
+void HW_IPCC_Enable( void )
+{
+  /**
+   * When the device is out of standby, it is required to use the EXTI mechanism to wakeup CPU2
+   */
+  LL_C2_EXTI_EnableEvent_32_63( LL_EXTI_LINE_41 );
+  LL_EXTI_EnableRisingTrig_32_63( LL_EXTI_LINE_41 );
+	
+  /**
+   * In case the SBSFU is implemented, it may have already set the C2BOOT bit to startup the CPU2.
+   * In that case, to keep the mechanism transparent to the user application, it shall call the system command
+   * SHCI_C2_Reinit( ) before jumping to the application.
+   * When the CPU2 receives that command, it waits for its event input to be set to restart the CPU2 firmware.
+   * This is required because once C2BOOT has been set once, a clear/set on C2BOOT has no effect.
+   * When SHCI_C2_Reinit( ) is not called, generating an event to the CPU2 does not have any effect
+   * So, by default, the application shall both set the event flag and set the C2BOOT bit.
+   */
+  __SEV( );       /* Set the internal event flag and send an event to the CPU2 */
+  __WFE( );       /* Clear the internal event flag */
+  LL_PWR_EnableBootC2( );
+
+  return;
+}
+
+void HW_IPCC_Init( void )
+{
+  LL_AHB3_GRP1_EnableClock( LL_AHB3_GRP1_PERIPH_IPCC );
+
+  LL_C1_IPCC_EnableIT_RXO( IPCC );
+  LL_C1_IPCC_EnableIT_TXF( IPCC );
+
+  HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn);
+  HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn);
+
+  return;
+}
+
+/******************************************************************************
+ * BLE
+ ******************************************************************************/
+void HW_IPCC_BLE_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_BLE_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_BLE_CMD_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_BLE_EvtHandler( void )
+{
+  HW_IPCC_BLE_RxEvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_BLE_SendAclData( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_BLE_AclDataEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+
+  HW_IPCC_BLE_AclDataAckNot();
+
+  return;
+}
+
+__weak void HW_IPCC_BLE_AclDataAckNot( void ){};
+__weak void HW_IPCC_BLE_RxEvtNot( void ){};
+
+/******************************************************************************
+ * SYSTEM
+ ******************************************************************************/
+void HW_IPCC_SYS_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_SYS_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_SYS_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+
+  HW_IPCC_SYS_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_SYS_EvtHandler( void )
+{
+  HW_IPCC_SYS_EvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
+
+  return;
+}
+
+__weak void HW_IPCC_SYS_CmdEvtNot( void ){};
+__weak void HW_IPCC_SYS_EvtNot( void ){};
+
+/******************************************************************************
+ * MAC 802.15.4
+ ******************************************************************************/
+#ifdef MAC_802_15_4_WB
+void HW_IPCC_MAC_802_15_4_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_MAC_802_15_4_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_MAC_802_15_4_SendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_MAC_802_15_4_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+
+  HW_IPCC_MAC_802_15_4_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_MAC_802_15_4_NotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_MAC_802_15_4_EvtNot();
+
+  return;
+}
+__weak void HW_IPCC_MAC_802_15_4_CmdEvtNot( void ){};
+__weak void HW_IPCC_MAC_802_15_4_EvtNot( void ){};
+#endif
+
+/******************************************************************************
+ * THREAD
+ ******************************************************************************/
+#ifdef THREAD_WB
+void HW_IPCC_THREAD_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_OT_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_CLI_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_THREAD_SendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_THREAD_CliSendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_OT_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  HW_IPCC_OT_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_THREAD_NotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_THREAD_EvtNot();
+
+  return;
+}
+
+static void HW_IPCC_THREAD_CliNotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_THREAD_CliEvtNot();
+
+  return;
+}
+
+__weak void HW_IPCC_OT_CmdEvtNot( void ){};
+__weak void HW_IPCC_CLI_CmdEvtNot( void ){};
+__weak void HW_IPCC_THREAD_EvtNot( void ){};
+
+#endif /* THREAD_WB */
+
+/******************************************************************************
+ * ZIGBEE
+ ******************************************************************************/
+#ifdef ZIGBEE_WB
+void HW_IPCC_ZIGBEE_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendAppliCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendCliCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
+
+   return;
+}
+
+void HW_IPCC_ZIGBEE_SendAppliCmdAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendCliCmdAck( void )
+{
+    LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+    LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_CmdEvtHandler( void )
+{
+    LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+    HW_IPCC_ZIGBEE_AppliCmdNotification();
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_StackNotifEvtHandler( void )
+{
+    LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+    HW_IPCC_ZIGBEE_AppliAsyncEvtNotification();
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_CliNotifEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_ZIGBEE_CliEvtNotification();
+
+  return;
+}
+
+__weak void HW_IPCC_ZIGBEE_AppliCmdNotification( void ){};
+__weak void HW_IPCC_ZIGBEE_AppliAsyncEvtNotification( void ){};
+__weak void HW_IPCC_ZIGBEE_CliEvtNotification( void ){};
+#endif /* ZIGBEE_WB */
+
+/******************************************************************************
+ * MEMORY MANAGER
+ ******************************************************************************/
+void HW_IPCC_MM_SendFreeBuf( void (*cb)( void ) )
+{
+  if ( LL_C1_IPCC_IsActiveFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ) )
+  {
+    FreeBufCb = cb;
+    LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+  }
+  else
+  {
+    cb();
+
+    LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+  }
+
+  return;
+}
+
+static void HW_IPCC_MM_FreeBufHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+
+  FreeBufCb();
+
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+
+  return;
+}
+
+/******************************************************************************
+ * TRACES
+ ******************************************************************************/
+void HW_IPCC_TRACES_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_TRACES_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_TRACES_EvtHandler( void )
+{
+  HW_IPCC_TRACES_EvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_TRACES_CHANNEL );
+
+  return;
+}
+
+__weak void HW_IPCC_TRACES_EvtNot( void ){};
+
+/******************* (C) COPYRIGHT 2019 STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/readme.txt b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/readme.txt
new file mode 100644
index 000000000..be549bde2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_HeartRate_ota/readme.txt
@@ -0,0 +1,124 @@
+/**
+  @page BLE_HeartRate_ota example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    BLE/BLE_HeartRate_ota/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the BLE_HeartRate_ota example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                               www.st.com/SLA0044
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to use the Heart Rate profile as specified by the BLE SIG.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+	  
+@note This application is not supported by CubeMx but has been copied from the project BLE_HeartRate generated
+      by CubeMx with some modifications in order to be able to download it with the BLE_Ota application.
+	  The steps to be done to move from the BLE_HeartRate application to the BLE_HeartRate_ota application are :
+	  - Copy the full folder BLE_HeartRate
+	  - Replace the linker file stm32wb55xx_flash_cm4.icf by stm32wb55xx_flash_cm4_ota.icf ( this adds the placement
+	  of the two sections TAG_OTA_START and TAG_OTA_END ).
+	  - Remove the update of SCB->VTOR in the file system_stm32wbxx.c ( The VTOR is already set by the BLE_Ota application
+	  and shall not be changed to a different value)
+          - set BLE_CFG_OTA_REBOOT_CHAR to 1 in ble_conf.h
+
+@par Directory contents 
+  
+  - BLE/BLE_HeartRate_ota/Core/Inc/stm32wbxx_hal_conf.h		HAL configuration file
+  - BLE/BLE_HeartRate_ota/Core/Inc/stm32wbxx_it.h          	Interrupt handlers header file
+  - BLE/BLE_HeartRate_ota/Core/Inc/main.h                  	Header for main.c module
+  - BLE/BLE_HeartRate_ota/STM32_WPAN/App/app_ble.h          Header for app_ble.c module
+  - BLE/BLE_HeartRate_ota/Core/Inc/app_common.h            	Header for all modules with common definition
+  - BLE/BLE_HeartRate_ota/Core/Inc/app_conf.h              	Parameters configuration file of the application
+  - BLE/BLE_HeartRate_ota/Core/Inc/app_entry.h            	Parameters configuration file of the application
+  - BLE/BLE_HeartRate_ota/STM32_WPAN/App/ble_conf.h         BLE Services configuration
+  - BLE/BLE_HeartRate_ota/STM32_WPAN/App/ble_dbg_conf.h     BLE Traces configuration of the BLE services
+  - BLE/BLE_HeartRate_ota/STM32_WPAN/App/dis_app.h          Header for dis_app.c module
+  - BLE/BLE_HeartRate_ota/STM32_WPAN/App/hrs_app.h          Header for hrs_app.c module
+  - BLE/BLE_HeartRate_ota/Core/Inc/hw_conf.h           		Configuration file of the HW
+  - BLE/BLE_HeartRate_ota/Core/Inc/utilities_conf.h    		Configuration file of the utilities
+  - BLE/BLE_HeartRate_ota/Core/Src/stm32wbxx_it.c          	Interrupt handlers
+  - BLE/BLE_HeartRate_ota/Core/Src/main.c                  	Main program
+  - BLE/BLE_HeartRate_ota/Core/Src/system_stm32wbxx.c      	stm32wbxx system source file
+  - BLE/BLE_HeartRate_ota/STM32_WPAN/App/app_ble.c      	BLE Profile implementation
+  - BLE/BLE_HeartRate_ota/Core/Src/app_entry.c      		Initialization of the application
+  - BLE/BLE_HeartRate_ota/STM32_WPAN/App/dis_app.c      	Device Information Service application
+  - BLE/BLE_HeartRate_ota/STM32_WPAN/App/hrs_app.c      	Heart Rate Service application
+  - BLE/BLE_HeartRate_ota/STM32_WPAN/Target/hw_ipcc.c      	IPCC Driver
+  - BLE/BLE_HeartRate_ota/Core/Src/stm32_lpm_if.c			Low Power Manager Interface
+  - BLE/BLE_HeartRate_ota/Core/Src/hw_timerserver.c 		Timer Server based on RTC
+  - BLE/BLE_HeartRate_ota/Core/Src/hw_uart.c 				UART Driver
+
+     
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35xx devices.
+  
+  - This example has been tested with an STMicroelectronics STM32WB35CE-Nucleo
+    board and can be easily tailored to any other supported device 
+    and development board.
+
+@par How to use it ? 
+
+This application requests having the stm32wb3x_BLE_Stack_fw.bin binary flashed on the Wireless Coprocessor.
+If it is not the case, you need to use STM32CubeProgrammer to load the appropriate binary.
+All available binaries are located under /Projects/STM32_Copro_Wireless_Binaries directory.
+Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the detailed procedure to change the
+Wireless Coprocessor binary.  
+
+In order to make the program work, you must do the following:
+ - Open your toolchain 
+ - Rebuild all files and flash the board with the executable file
+ - OR use the BLE_HeartRate_ota_reference.bin from Binary directory
+   - to be flashed at 0x0800 7000
+
+ On the android/ios device, enable the Bluetooth communications, and if not done before,
+ - Install the ST BLE Profile application on the android device
+	https://play.google.com/store/apps/details?id=com.stm.bluetoothlevalidation&hl=en
+    https://itunes.apple.com/fr/App/st-ble-profile/id1081331769?mt=8
+
+ - Install the ST BLE Sensor application on the ios/android device
+	https://play.google.com/store/apps/details?id=com.st.bluems
+	https://itunes.apple.com/us/App/st-bluems/id993670214?mt=8
+
+ - Power on the Nucleo board with the BLE_HeartRate_ota application
+ - Then, click on the App icon, ST BLE Sensor (android device)
+ - connect to a device
+ - select the HRSTM in the device list
+
+Next demonstration 
+ - Move to download panel with the smart Phone Application 
+ - select the binary to be downloaded on the Application Processor
+   -  BLE_HeartRate_ota_reference.bin or BLE_p2pServer_ota_reference.bin have to be copied into Smart phone directory
+ - Start download
+ - New Application is running and can be connected    
+ 
+The Heart Rate is displayed each second on the android device.
+
+For more details refer to the Application Note: 
+  AN5289 - Building a Wireless application 
+  UM2551 - STM32CubeWB Nucleo demonstration firmware
+ 
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
+ 
\ No newline at end of file
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Binary/BLE_Ota.hex b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Binary/BLE_Ota.hex
new file mode 100644
index 000000000..42ff38f97
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Binary/BLE_Ota.hex
@@ -0,0 +1,1125 @@
+:020000040800F2
+:10000000F02300206D4400084D4300084F430008D2
+:10001000894400088D440008914400080000000055
+:100020000000000000000000000000005143000834
+:1000300053430008000000005543000857430008E0
+:1000400095440008994400089D440008694300084D
+:10005000A1440008A54400085B430008A944000827
+:10006000AD440008B1440008B5440008B944000894
+:10007000BD440008C1440008C5440008C944000844
+:10008000CD440008D1440008D5440008D9440008F4
+:10009000DD440008E1440008E5440008E9440008A4
+:1000A000ED440008F1440008F5440008F944000854
+:1000B000FD44000801450008054500080945000801
+:1000C0000D450008114500081545000819450008B0
+:1000D0005D4300081D4500080000000021450008A0
+:1000E00025450008294500082D4500083145000830
+:1000F000714300086D430008354500083945000884
+:100100003D45000800000000414500084545000845
+:10011000494500084D45000851450008554500086F
+:10012000594500085D450008634300086145000823
+:1001300065450008694500086D45000838B50400AC
+:1001400009D004F17C05686808B900F01EF800F0D9
+:1001500021F8012801D1012032BDA06A08B100F0C8
+:100160002AF800F00AF821F02A01FFE7816000F088
+:100170001BF8BDE8324000F0DEBD2068416821F484
+:1001800090414160206881687047002129702046B5
+:1001900000F0C3BE24206860206801684908490057
+:1001A0000160204600F0F0B82068016841F00101CC
+:1001B000016020467047204600F05ABD20688168E3
+:1001C0004A067047F8B5044640F60F002568E9690D
+:1001D0002A68AB6808400DD1880602D5900602D483
+:1001E000D80040F18980E16E00294FD02046BDE85B
+:1001F000F44008476248034204BF624E32427BD05B
+:10020000CF0709D5D60507D501262E62D4F8885028
+:1002100045F00105C4F888508D070AD5DD0708D5DB
+:10022000266802253562D4F8885045F00405C4F8E4
+:1002300088504D070AD5DD0708D5266804253562A4
+:10024000D4F8885045F00205C4F888500D070CD545
+:10025000950601D4034208D0256808202862D4F806
+:10026000880040F00800C4F8880008050BD550014C
+:1002700009D525684FF400602862D4F8880040F062
+:100280002000C4F88800D4F88800002870D08906BF
+:1002900007D5900601D4D80003D5E16E09B12046F8
+:1002A0008847D4F8880021688A68510602D410F083
+:1002B000280F1AD0204600F0ABFDFFF77FFF0FD5C7
+:1002C00000F057F860B1DFF888198163A06F00F083
+:1002D00020FF00284CD0A06F816BBDE8F440084798
+:1002E0002046BDE8F24000F0E9BF204600F0E6FFFE
+:1002F0000020C4F88800F1BDC80209D5580207D50E
+:100300004FF4801028622046BDE8F24000F0D8BFCC
+:10031000080609D5100601D4180205D5216F39B396
+:100320002046BDE8F440084748060FD550060DD5D5
+:10033000286820F0400028602021C4F880100020A8
+:1003400020672046BDE8F24000F05FBE080206D5F7
+:10035000500004D52046BDE8F24000F0B2BFC8010D
+:1003600048BF002A04D52046BDE8F24000F0AABFED
+:10037000F1BD816821F040018160A06F70470000ED
+:1003800001000010200100042DE9F84F0446DFF8B9
+:10039000C8082768DFF8C4B83968DFF8C4A8014086
+:1003A000A06801432069014360690143E06901439A
+:1003B000606E0143396000267968E06821F440519D
+:1003C00001437960B046A169DFF8880887421CBF05
+:1003D000206A0143BA68DFF85C0A02401143B96041
+:1003E0004FF48075F96A606A090940EA0111F962FF
+:1003F0005F454FF400404FF400714FF480624FF4BA
+:1004000000634FF4805C4FF4005E4FF4804929D1C3
+:10041000DAF800B00BF0030BBBF1030F3ED8DFE8B6
+:100420000BF00237343A4FF0010AD4F81CB05746AB
+:10043000BBF5004F4FF6F07A40F01183012F09D041
+:10044000022F00F05482042F00F08D82082F00F05C
+:10045000C282F5E200F093FF0146606A002840F096
+:100460001B8242E2DFF8ECB75F4517D1DAF800A053
+:100470001AF4406A27D0BAF5806F09D0BAF5006F38
+:1004800003D0BAF5406F06D008E04FF0020A07E04B
+:100490004FF0040A04E04FF0080A01E04FF0100AA0
+:1004A000DFF8B0B75F45C0D1BAF1000F0BD0BAF199
+:1004B000020F49D0BAF1040F00F08280BAF1080FA0
+:1004C00000F0B080B6E300F052FF0146606A58B316
+:1004D000012808BF022028D0022808BF042024D009
+:1004E000032808BF062020D0042808BF08201CD0FD
+:1004F000052808BF0A2018D0062808BF0C2014D0F1
+:10050000072808BF102010D0082808BF20200CD0D2
+:10051000092808BF402008D00A2808BF802004D03E
+:100520000B2808BF284600D00120B1FBF0F00028BE
+:1005300000F08283626802EB4201884203D3110318
+:10054000814280F0A18075E3606AB0B3012808BFE2
+:10055000DFF8E408EED0022808BFDFF8E008E9D0B1
+:10056000032808BFDFF8D808E4D0042808BFDFF864
+:10057000D408DFD0052808BFDFF8CC08DAD0062879
+:1005800008BFDFF8C808D5D0072808BFDFF8C008C3
+:10059000D0D0082808BFDFF8BC08CBD0092808BF96
+:1005A000DFF8B408C6D00A2808BFDFF8B008C1D009
+:1005B0000B2808BF4FF22440BCD0DFF8A408B9E7ED
+:1005C00000F08BFE0146606A58B3012808BF022084
+:1005D000ABD0022808BF0420A7D0032808BF0620FC
+:1005E000A3D0042808BF08209FD0052808BF0A20F0
+:1005F0009BD0062808BF0C2097D0072808BF1020E2
+:1006000093D0082808BF20208FD0092808BF402099
+:100610008BD00A2808BF802087D00B2808BF284627
+:1006200083D081E7676A002F84D0012F08BF484636
+:10063000FAD0022F08BF7046F6D0032F08BF41F250
+:100640005550F1D0042F08BF6046EDD0052F08BFEC
+:1006500040F6CC40E8D0062F08BF40F6AA2012D0C2
+:10066000072F08BF18460ED0082F08BF10460AD023
+:10067000092F08BF084606D00A2F08BF284602D017
+:100680000B2F00D1802055E7BAF1000F0BD0BAF143
+:10069000020F38D0BAF1040F00F07280BAF1080FDF
+:1006A00000F0A780ECE000F062FE0146606A40B313
+:1006B000012808BF02251ED0022808BF04251AD031
+:1006C000032808BF062516D0042808BF082512D025
+:1006D000052808BF0A250ED0062808BF0C250AD019
+:1006E000072808BF102506D0082808BF202502D0FB
+:1006F000092808BF402572D00A280CBF80250B2886
+:100700006DD001256BE0606A002836D0012808BF53
+:10071000DFF860672BD0022808BFDFF85C6726D0BF
+:10072000032808BFDFF8546721D0042808BFDFF88A
+:1007300050671CD0052808BFDFF8486717D0062887
+:1007400008BFDFF8446712D0072808BFDFF83C670E
+:100750000DD0082808BFDFF8386708D0092808BF7F
+:10076000DFF8306703D00A2808BFDFF82C677CD099
+:100770000B2808BFDFF8E86677D0DFF8206774E061
+:1007800000F0ABFD0146606A40B3012808BF0225B6
+:1007900025D0022808BF042521D0032808BF06253C
+:1007A0001DD0042808BF082519D0052808BF0A2530
+:1007B00015D0062808BF0C2511D0072808BF102522
+:1007C0000DD0082808BF202509D0092808BF4025DA
+:1007D00005D00A280CBF80250B2800D001256268AF
+:1007E000B1FBF5F65008002110EB062051EB166125
+:1007F00041E0606A002836D0012808BF4FF4800627
+:1008000033D0022808BF4FF400162ED0032808BFAB
+:10081000DFF88C6629D0042808BF4FF4801624D056
+:10082000052808BFDFF87C661FD0062808BFDFF860
+:1008300078661AD0072808BF4FF4002615D008287C
+:1008400008BF4FF4802610D0092808BF4FF40036A7
+:100850000BD00A2808BF4FF4803606D00B2808BFFB
+:100860004FF4004601D04FF40006C246002116EBBB
+:1008700052004AEB0101002300F09EFD064601E014
+:100880004FF00108A6F54070DFF82016884280F08E
+:10089000D1812168CE60CFE1012808BF02251AD09E
+:1008A000022808BF042516D0032808BF062512D049
+:1008B000042808BF08250ED0052808BF0A250AD03D
+:1008C000062808BF0C2506D0072808BF102502D02F
+:1008D000082808BF202575D0092808BF402571D0F9
+:1008E0000A280CBF80250B286CD001256AE0606ABD
+:1008F000B0B3012808BFDFF8680521D0022808BF7F
+:10090000DFF834051CD0032808BFDFF8A40517D092
+:10091000042808BFDFF8240512D0052808BFDFF837
+:1009200094050DD0062808BFDFF8140508D0072865
+:1009300008BFDFF8100503D0082808BFDFF810054E
+:100940007AD0092808BFDFF80C0575D00A2808BF3F
+:10095000DFF8040570D00B2808BFDFF800056BD066
+:10096000DFF8340568E000F0B8FC0146606A40B387
+:10097000012808BF022525D0022808BF042521D060
+:10098000032808BF06251DD0042808BF082519D054
+:10099000052808BF0A2515D0062808BF0C2511D048
+:1009A000072808BF10250DD0082808BF202509D02A
+:1009B000092808BF402505D00A280CBF80250B2830
+:1009C00000D001256068B1FBF5F1420802EB41025D
+:1009D000B2FBF0F632E0666A66B3012E2CD0022E2E
+:1009E00008BF484628D0032E08BF42F6AA2023D0CD
+:1009F000042E08BF70461FD0052E08BF41F6981080
+:100A00001AD0062E08BF41F2545015D0072E08BF49
+:100A1000604611D0082E08BF18460DD0092E08BF19
+:100A2000104609D00A2E08BF084605D00B2E08BF75
+:100A3000284601D04FF4803000F014F9B6B201E03E
+:100A40004FF00108A6F11000504580F0F3800AEA4B
+:100A50000601C6F3420001432068C160ECE0012FAB
+:100A600007D0022F35D0042F70D0082F00F0A580BA
+:100A7000D7E000F084FC0146606A40B3012808BF5B
+:100A8000022516D0022808BF042512D0032808BF6B
+:100A900006250ED0042808BF08250AD0052808BF5F
+:100AA0000A2506D0062808BF0C2502D0072808BF53
+:100AB00010257AD0082808BF202576D0092808BF3D
+:100AC000402572D00A280CBF80250B286DD0012547
+:100AD0006BE0606AB0B3012808BFDFF85C1333D065
+:100AE000022808BFDFF854132ED0032808BFDFF810
+:100AF000501329D0042808BFDFF8481324D0052854
+:100B000008BFDFF844131FD0062808BFDFF83C13E6
+:100B10001AD0072808BFDFF8381315D0082808BFF7
+:100B2000DFF8301310D0092808BFDFF82C130BD0E2
+:100B30000A2808BFDFF8241306D00B2808BF4FF29D
+:100B4000244101D0DFF81813606831E000F0C5FBE4
+:100B50000146606A40B3012808BF022525D002285B
+:100B600008BF042521D0032808BF06251DD004286E
+:100B700008BF082519D0052808BF0A2515D0062862
+:100B800008BF0C2511D0072808BF10250DD0082854
+:100B900008BF202509D0092808BF402505D00A280C
+:100BA0000CBF80250B2800D001256068B1FBF5F152
+:100BB00001EB5001B1FBF0F631E0666A6EB3012E35
+:100BC00008BF484629D0022E08BF704625D0032E04
+:100BD00008BF41F2555020D0042E08BF60461CD0FB
+:100BE000052E08BF40F6CC4017D0062E08BF40F6B1
+:100BF000AA2012D0072E08BF18460ED0082E08BF14
+:100C000010460AD0092E08BF084606D00A2E08BF93
+:100C1000284602D00B2E08BF802000F023F8B6B281
+:100C200001E04FF00108A6F11000504502D2206803
+:100C3000C66001E04FF0010804F168000121418025
+:100C400001800021416081604046BDE8F28F0000D4
+:100C5000650E000800800040F369FFCF00380140B6
+:100C600088000058616800EB5100B0FBF1F6704756
+:100C700090F82810CA0706D502685368C16A23F4A1
+:100C800000330B43536090F828108A0706D502689A
+:100C90005368016B23F480330B43536090F82810A2
+:100CA0004A0706D502685368416B23F480230B433F
+:100CB000536090F828100A0706D502685368816BC4
+:100CC00023F400430B43536090F82810CA0606D55E
+:100CD00002689368C16B23F480530B43936090F8D0
+:100CE00028108A0606D502689368016C23F4005325
+:100CF0000B43936090F828104A0610D50268536899
+:100D0000416C23F480130B435360416CB1F5801F99
+:100D100005D15368816C23F4C0030B43536090F8F2
+:100D200028100A0606D501684A68C06C22F4002221
+:100D300002434A607047F8B5044604F17C05002080
+:100D4000E8606FF07E4700F04FFC064620680168BF
+:100D50000A0708D50097334600224FF400112046B9
+:100D600000F016F860B9206801684A070AD50097B4
+:100D7000334600224FF48001204600F009F808B104
+:100D80000320F2BD20206860A86000202870F2BD1A
+:100D90002DE9F041069C05460E4690461F46286800
+:100DA000C1693140B1420CBF0120002040451CD137
+:100DB00014F1010FF3D000F017FCC01B844200D3E4
+:100DC00014B900F015F80CE0286801684A07E6D568
+:100DD000C1690A05E3D54FF40062026200F008F829
+:100DE000C16000210170032000E00020BDE8F08117
+:100DF0002868016821F4D071016028688168490879
+:100E00004900816005F17C002021416081607047CC
+:100E100001680A6822F490720A60DFF89C10026888
+:100E200093680B4093602021C0F884100021C166B4
+:100E300070470000FFF4FF1100127A0000093D0026
+:100E4000AAB0280080841E00006A180055581400BB
+:100E500040420F0020A1070090D0030048E80100A5
+:100E60000024F400806A00F1560100220A810A8001
+:100E700000F024BA0000127A0000093D00AAB02850
+:100E80000080841E00006A18005558140040420F6C
+:100E90000020A1070090D0030048E801000024F4DE
+:100EA0000055150000CC0C0000AA0A0000FD0F0040
+:100EB0005461510000D43000FEFFFFEF584900E0BC
+:100EC000584981B00A6802430A60096808400090E6
+:100ED000009801B0704798B95348544901604FF4E5
+:100EE000E131416000218160C160016181610C21BB
+:100EF00041614FF40041C16100218162FFF71EB9D9
+:100F00007047002804BF4848FFF75CB9704718B91C
+:100F10004548406F00F033B9704738B586B0044695
+:100F20006846142100F066FB2168404A91425FD177
+:100F30000220FFF7C5FF402000F05CF83D4D284639
+:100F400000F05CFB0220FFF7BBFF802000F052F8AE
+:100F5000284600F053FB0120FFF7B2FF4FF400607A
+:100F60000221009001910291072003210391049036
+:100F700069464FF0904000F041FB2F482F4D816AA9
+:100F80008908890041F0010181620022016841F471
+:100F9000804101600F21006800F4804005900598B1
+:100FA000242000F019FC242000F033FC0220FFF77D
+:100FB00085FF0420FFF782FF214828600F2068602A
+:100FC0001020A8600020E86080202861002068616F
+:100FD000A861E8612862284600F034F86567AC62D1
+:100FE00000220F213A2000F0F7FB3A2000F011FC1C
+:100FF00007B030BD00900221002001910290032132
+:1010000007200391049069467047006807498842A9
+:1010100004D107490868002818BF0047704700003E
+:10102000480000584C00005848110020003801408A
+:10103000E41300200004004860000058541200200F
+:101040004404024038B5040001D1012032BD2168BA
+:10105000DFF84002814204F1240500F042F802204A
+:1010600068700A68A0686FF30E120243E0680243DA
+:101070002069024360690243A0690243E0690243B8
+:10108000206A02430A60204600F0DAF8A068B0F552
+:10109000804F04BF00216160696A207900F014F874
+:1010A00038B1052805D2204600F0E4F800F012F827
+:1010B00003E0002028636863A8630020A861012082
+:1010C00068700020287032BD0860A96AE86A48602C
+:1010D00060687047296B00200860696BA86B4860E6
+:1010E00070470AD2DFF8B00142181423B2FBF3F2C2
+:1010F00092002A62DFF8A40109E0DFF8A401421897
+:101100001423B2FBF3F292002A62DFF89801E8613F
+:10111000704738B500F1240200245178022903D029
+:1011200004209061012428E001680B6823F00E037D
+:101130000B6001680D686D086D000D60516A0B68E9
+:1011400023F480730B60012192F82030D56903F0FD
+:101150001C0399406960936AD16A5960116B31B17F
+:101160000B6823F480730B60536B916B5960012102
+:1011700051701470516901B18847204632BDF8B5ED
+:1011800000F124010423CA6914680268156891F803
+:10119000206006F01C0603FA06F73C4210D06F07E9
+:1011A0000ED51468A50603D4156825F0040515604E
+:1011B00000F03DF8C968002938D0BDE8F440084780
+:1011C000022303FA06F73C4213D0AF0711D5146887
+:1011D000A50605D4156825F00A05156001224A7098
+:1011E00000F025F800220A708968F9B1BDE8F440E2
+:1011F0000847082303FA06F6344217D02B0715D503
+:10120000136823F00E031360012291F82030CC699B
+:1012100003F01C039A40626001228A614A70002236
+:101220000A70096911B1BDE8F4400847F1BD91F8B1
+:101230002020CC6902F01C029340636070470000DC
+:10124000416C0268134B89089A4234BF164B174B06
+:1012500003EB8101816402F0FF02083A1421B2FB22
+:10126000F1F1134AC26401F01C01012202FA01F1FA
+:101270000165704701790F4A02EB81024265491E00
+:101280000D4A826501F0030101228A40C265704760
+:101290000000000008040240F8FFFDBF000002400B
+:1012A000F8FBFDBF00040240000802401C08024099
+:1012B00080080240FC0802404009024070470000DC
+:1012C00070477047704700004FF0B040006800F072
+:1012D000F000B02888BFB020704738B54FF0B04458
+:1012E000304DA16811F00C0106D1FFF7EDFFC0F3FE
+:1012F000031055F8200032BD04292B4A05D00829D7
+:101300002A4804D12168C90222D5104632BDE168BD
+:1013100001F00301022904D0032904D12168C90284
+:1013200007D5104605E0FFF7CFFFC0F3031055F8CF
+:101330002000E168E268E368C1F306214843C2F394
+:101340000211491C5B0FB0FBF1F05B1CB0FBF3F02A
+:1013500032BD80B5FFF7C1FF1149FFE7144A0968A4
+:10136000C1F3031152F82110B0FBF1F002BD80B5BA
+:10137000FFF7EFFF00F010F8C1F3022106E080B59F
+:10138000FFF7E7FF00F008F8C1F3C22112F82110BF
+:1013900001F01F01C84002BD0149064A09687047B3
+:1013A00008000058944200080024F4000048E801B6
+:1013B0005442000808440008B3BBD9B1B2F5803FDD
+:1013C0007DD2022A1ED98C46B1FBF2F102FB11C379
+:1013D0001B0443EA1043B3FBF2FC02FB1C3380B254
+:1013E00040EA0343B3FBF2F002FB103240EA0C4048
+:1013F00000237047022A05D98446B0FBF2F002FBB5
+:1014000010C270474AB105D100F0010249085FEAF5
+:101410003000704700220023704700F051BA0B00E3
+:101420000200002100207047904271EB030CF6D3BC
+:10143000B3F5803F2FD2F0B5B3FA83F7B1FA81F458
+:10144000A7F10F0E3D1B5340CEF1200602FA0EF21B
+:10145000F3415340B5F10F0746D80F3C2C444140AF
+:10146000C4F12006A040F1414140B1FBF3F603FB7B
+:101470001611A2FB0645001BA94102D2761E801858
+:10148000594180EA010221FA0EF362FA0EF20021BC
+:101490005A403046F0BD30B4B1FBF3FC03FB1C11E5
+:1014A000A2FB0C45001BA94103D2ACF1010C801832
+:1014B000594130BC02460B46604600217047B2F1EC
+:1014C000807F65D3F0B5B2FA82F7B1FA81F4C7F143
+:1014D0000F063D1B22FA06F307F1110EF2412035EB
+:1014E0005A40B5F10F07B8D94140C4F12006A040D9
+:1014F000F1414140B1FBF3FC03FB1C11A2FB0C4585
+:10150000001BA94103D2BCF1010C801859410F2FD7
+:1015100012D30F3FC90341EA5041B1FBF3F603FB7D
+:101520001611A2FB0645D4EBC030A94102D2761EAB
+:101530008018594146EACC3C07B34140C7F1200628
+:10154000B840F1414140B1FBF3F603FB1611A2FB99
+:101550000645001BA94102D2761E8018594180EA37
+:10156000010221FA0EF3C7F1200462FA0EF20CFA1E
+:1015700007F05A402CFA04F13043F0BD80EA010232
+:1015800021FA0EF3002162FA0EF260465A40F0BDD5
+:101590008C46B1FBF2F102FB11C31B0243EA10635C
+:1015A000B3FBF2FC02FB1C331B024CEA002043EAB3
+:1015B0001063B3FBF2FC02FB1C331B024CEA00205D
+:1015C00043EA1063B3FBF2FC02FB1C331B024CEA40
+:1015D000002043EA1063B3FBF2FC02FB1C324CEA2E
+:1015E000002000237047000001480068704700BFDA
+:1015F00078100020002200F065B900002DE9F84FB6
+:101600004FF0000C604A614BDFF884814FF00F0906
+:1016100082460F4633E05F4DAA4514BF07250425D7
+:101620008D40254348F82E50C1431C6801EA040E42
+:101630007C68E50348BF40EA0E0EC3F800E05C6832
+:1016400001EA040E7C68A50348BF40EA0E0EC3F809
+:1016500004E0146801EA040E7C68E50248BF40EA31
+:101660000E0EC2F800E0546801EA040E79688C029C
+:1016700048BF40EA0E0EC2F804E00CF1010C3968D4
+:1016800031FA0CF076D0012000FA0CFE1EEA0100BF
+:10169000F3D07C68022C18BF122C4FEA8C0110D1B9
+:1016A0004FEADC040AEB840401F01C05266A09FAFF
+:1016B00005FB26EA0B06D7F810B00BFA05F5354303
+:1016C00025624FEA4C040325DAF8006097F804B06D
+:1016D000A540ED430BF0030B2E400BFA04FB4BEA45
+:1016E0000606CAF800607E68012E18BF022E03D0DD
+:1016F000112E18BF122E17D1DAF80860D7F80CB0E7
+:101700002E400BFA04FB4BEA0606CAF80860DAF82A
+:10171000046026EA0E0E7E68C6F3001606FA0CF682
+:1017200046EA0E06CAF80460DAF80C603540BE6876
+:1017300006FA04F42C43CAF80C407C68E4009CD5FB
+:101740004FEA9C0E58F82E5001F00C0109FA01F4F2
+:1017500025EA0404BAF1904F08BF002509D00E4DC8
+:10176000AA4508BF012504D00C4DAA457FF453AF0C
+:10177000022555E7BDE8F18F81B0002A14BF8161D1
+:10178000816201B0704700000008005880080058CE
+:10179000080001400010004800040048000800480C
+:1017A0000901020081B002D43C48815405E03C4864
+:1017B00002F00F02104400F8041C01B07047394ACF
+:1017C00013684FF6FF0100020B4000F4E06018437D
+:1017D000354908431060704738B5324B1C68C4F374
+:1017E0000223C3F10704052C28BF04241D1D072D67
+:1017F00034BF0023DB1E012505FA04F4641E2140DA
+:10180000994005FA03F35B1E1A401143BDE83440CA
+:10181000C6E7010007D4012200F01F01234B8A40D4
+:10182000400943F82020704701000BD4012200F04A
+:101830001F011F4B8A40400943F82020BFF34F8F00
+:10184000BFF36F8F704710B5401EB0F1807F01D39A
+:10185000012010BD174C60600F214FF0FF30FFF7E3
+:101860009FFF0022A26007202060002010BD010021
+:1018700007D4012200F01F010F4B8A40400943F8B2
+:1018800020207047010007D4012200F01F010B4BFC
+:101890008A40400943F820207047000000E400E03F
+:1018A00018ED00E00CED00E00000FA0500E100E0BA
+:1018B00080E100E010E000E000E200E080E200E013
+:1018C0007047000000B500BF1300964694461039DB
+:1018D00028BFA0E80C50FAD85FEA417C28BF0CC0B2
+:1018E00048BF40F8042BC90728BF20F8022B48BF87
+:1018F00000F8012B00BD0000DFF8F0140A6892B276
+:1019000000E00246086880B28242FAD170472DE9B1
+:10191000FC4104461825DFF8D884DFF8D864684312
+:1019200008EB00073078062808D1317871703470E0
+:1019300078754FF0FF307060002039E000F077F8E4
+:10194000B9680918B96008F10803B96832786A43C0
+:101950009A589142327813D308F1150315FB02FC13
+:1019600013F80C30062B25D008F108066B43F3580A
+:10197000994222BF08F115036A439A5CEED219E03E
+:101980001146337869439A420BD008F1140308F1E9
+:10199000150C5B5C15FB03F50CF805407A753B757F
+:1019A00000E07A7508F11402545431787170347083
+:1019B000BDE8F6811146694308F115035B5C062B0F
+:1019C00004D008F1140615FB03F574557B753A75C0
+:1019D00008F115025454EBE7F8B5DFF81834DFF8D6
+:1019E00010541E78182402466243B0422A4404D19F
+:1019F00018785870507D18700FE0167D507D92F861
+:101A000015C005F115076643062807F806C004D07F
+:101A1000167D143514FB00F42E5501201073187830
+:101A2000062802BF00294FF0FF315960F1BD10B503
+:101A3000DFF8C043606810F1010F0FD0FFF75CFFC3
+:101A40006168DFF8B423814261683CBF5388C918DC
+:101A5000081A517848431178C84000E0002080B24D
+:101A600010BD2DE9F84FDFF89053DFF890B3D5F8AB
+:101A70000880D8F80000DBF800104A0500F06AF989
+:101A8000DFF87063DFF868A321F4806181604FF0B4
+:101A9000180934780AF1080019FB04F14758FFF7D8
+:101AA000C6FF874217D200270121B170062C3DD016
+:101AB00019FB04F40AF108010AF1080209598142EC
+:101AC00023BF0AF108010959091A002111510AEB33
+:101AD00004014C7DEAE7A9884118B94202D2AF88D7
+:101AE0000021E2E73F1ADFE7022802DA287801281E
+:101AF00000D07F1ED8F80000C1684A07FAD500F070
+:101B00002FF9DBF80C00000CBFB247EA0047CBF816
+:101B10000C70FFF7F1FE7060A8680068816841F4FE
+:101B200080618160AFF30080BDE8F18FB8B200281A
+:101B3000DAD1FFF7E1FE70600320BDE8F24FFFF756
+:101B400096BE2DE9F843EFF3108872B6AA4DA84B64
+:101B5000A8680168CA224A6253204862A54A886878
+:101B600020F48060886018201678374647431F4469
+:101B7000387B022826D13C68D7F810909078F0B1D5
+:101B80007A7B012A0AD101213046FFF725FF88F32D
+:101B900010887968304600F0F0F804E088F3108887
+:101BA000304600F09BF8A8680068CA2141622246CE
+:101BB000532141624846314600F02AF90BE0FFF715
+:101BC00050FF06E0C8684207FCD500F07EF88C495B
+:101BD000086088F31088FF21A86802685162BDE898
+:101BE000F183F8B5844CA160CA2209684A62532285
+:101BF0004A62824A136843F020031360136803F0BB
+:101C00000703C3F10403237095682D0C05F07F05CD
+:101C10006D1C6570EDB29268C2F30E02521C6280B8
+:101C200092B2521E6A43A2F5A072DA404FF6FF73D9
+:101C30009A422CBFA380A280724A136843F4002307
+:101C40001360714B1D6845F400251D6048BB694851
+:101C5000674E0123837018254FF0FF334360002344
+:101C60005FFA83FC06F10C0715FB0CFC4FF0000E2D
+:101C700007F80CE05B1CDFB2062FF1DB06230370D4
+:101C8000886820F48060886000F01FF8D06003202E
+:101C9000FFF7F8FDA1680868826842F4804282601C
+:101CA00005E0C868410544BF0320FFF7E0FDA168D7
+:101CB0000A68FF205062002203210320FFF78CFDF9
+:101CC000BDE8F2400320FFF7A4BDC86800F0800023
+:101CD00060F49060C8604FF400207047F8B5074684
+:101CE000EFF3108472B60320FFF79EFD424DAE68FD
+:101CF0003068CA2141623A46532141621820434963
+:101D00004243895C02291BD100213846FFF764FE5B
+:101D10003848017806290ED1306838490A685305D9
+:101D200000F018F821F480618160C1684A07FCD591
+:101D300000F016F804E04078884218BFFFF791FEE3
+:101D4000A9680A68FF2050620320FFF762FD84F350
+:101D50001088F1BD02D5C1684A07FCD4816870477C
+:101D6000C16801F0800161F49061C1604FF400200E
+:101D7000234908600320FFF785BD2DE9F041804627
+:101D80000F46424618201A4942438C18207B0228ED
+:101D900004BF4046FFF7A2FFEFF3108572B60320A1
+:101DA000FFF742FD144EB0680068CA21416253211A
+:101DB000416202202073A76067604046FFF7A7FDDD
+:101DC0000C490A784978914202D0FFF74AFE02E0B6
+:101DD000A168081AA060FF20B1680A685062032059
+:101DE000FFF717FD85F31088BDE8F0812828004033
+:101DF000B8100020D81300209813002008280040B5
+:101E00000C0800580008005880080058C410002032
+:101E10001047000018B595B009A80FF2BC21874CF7
+:101E2000302200F081F90FF265200190009469469C
+:101E30000FF2412000F0BCF90121022000F0A1FACC
+:101E40007F4A0021012000F016FB09A800F0B8FB32
+:101E50000020ADF81A0000F0C7FB00F0D3F80246EE
+:101E60000621002000F0E4FB4EF66E50089007AA11
+:101E700074490868079006212E2000F0D9FB0FF264
+:101E800030221021182000F0D3FB0FF23422102151
+:101E9000082000F0CDFB1821012000F0F0FB00F03D
+:101EA00019FC0DF1160006A90190009105AB07225F
+:101EB0000021012000F0A7FD0FF2E410BDF818107A
+:101EC00000900723BDF81400002200F0C3FC0DF1C0
+:101ED0001A0000900223BDF81610BDF8140000226D
+:101EE00000F0B8FC002000F042FD00200490102318
+:101EF000554903910820002201930090029200238B
+:101F00000121012000F04CFD00F010FE4F484FF47D
+:101F1000004101600221006F019100F07F004FF04D
+:101F200000514A780292062A0ED200200870BFF3B0
+:101F30004F8F474947480A6802F4E06202430A604B
+:101F4000BFF34F8F00BFFDE789780391891888425E
+:101F50003CBF801A039000F07CFE694601A800F0A7
+:101F6000D3FE00F084FE00F04DF83B4942790A723E
+:101F700002794A72C2788A728278CA7242780A7387
+:101F80000278521C4A73062142798DF805200279A5
+:101F90008DF80420C2788DF8032082788DF8022015
+:101FA00042788DF801206A460078401C8DF80000C8
+:101FB000002000F03DFB00F00AF816B010BD80B51F
+:101FC0004078052808BF00F002F8012002BD00B5E6
+:101FD00087B000200690059000220FF2F4000492D2
+:101FE000082100230290019100920393A0228021F6
+:101FF000002000F073FC07B05DF804EB16490E20DA
+:1020000000F031BD10B50F490A6812F1010F0DD073
+:1020100012484B6802701B0A140A120C447082703A
+:1020200049680371C1701B0A437110BD002000F0A4
+:10203000E5FE08B90FF2700010BD0000AC8800206A
+:10204000EF2100088075FF1F07B201001040005803
+:102050000CED00E00400FA0504000020B01300209D
+:102060000021012000F014BA012000F033BA012051
+:1020700000F038BA10B50446616801F1080000F0BC
+:1020800065FD00B10120207010BD000010B10128D5
+:1020900003D07047012000F00BBA00F011BA000025
+:1020A000424C45636F7265006C7AD8AC5772000081
+:1020B000123456789ABCDEF0123456789ABCDEF0B0
+:1020C000FEDCBA0987654321FEDCBA098765432136
+:1020D0000953544D5F4F54410000000000000000C0
+:1020E00000000000000000000000000044000800A4
+:1020F000400508013A799C00F4010000FFFFFFFF52
+:10210000480101000000000062B38B0708D0521E96
+:1021100011F8013B00F8013B00F024808B07F6D159
+:10212000830740F0208000BF103A07D330B4B1E8F5
+:102130003810103AA0E83810F9D230BC530724BF49
+:10214000B1E80810A0E8081044BF51F8043B40F87B
+:10215000043BD20724BF31F8022B20F8022B44BFE6
+:102160000B7803707047121F17D35B0009D151F829
+:10217000043B20F8023B1B0C121F20F8023BF6D256
+:102180000BE051F8043B00F8013B1B0A20F8023B2E
+:102190001B0C121F00F8013BF3D238BF121D521E58
+:1021A00024BF11F8013B00F8013BF8D8704700004C
+:1021B0007FB50C466D4D61686D4EE8612962284619
+:1021C00000F02EFE246805F1240000604060746079
+:1021D00006F108000060406001203070296829B1D4
+:1021E0000FF2551000900294684688477FBD1FB5D6
+:1021F0005F4C04F1080000F020FE00BB2178F1B133
+:10220000694604F1080000F041FE5848C16949B12F
+:102210000098029001228DF8042001A888479DF8BB
+:10222000040000E001202070207818B1009800F030
+:10223000E0FE04E0009904F1080000F007FE04F15C
+:10224000080000F0FAFD28B9207818B104F1080060
+:10225000FFF706FF1FBD2DE9F8430646002000F0FA
+:102260005FF874883088B268DFF80081C4F309042D
+:1022700044EA8024F068A4B2C1B2204600F03CF8E1
+:10228000002748F2E8094846FFF7F1FE08E06888B1
+:10229000A04202D1316928780870687800B101271E
+:1022A00008F1240000F0C9FDF0B9694608F12400E6
+:1022B00000F0ECFD009800F10B05407A0F28E6D005
+:1022C000B5F80110A1420DD10098817AC81E71693C
+:1022D000C0B28842C8BF0846706102463069E91C36
+:1022E000FFF712FF2878D9E73800CCD0012000F0A2
+:1022F00017F80020BDE8F28310B513461C4A546855
+:10230000A4F80900E1720A46194604F10C00FFF72F
+:10231000FBFE164A1369BDE8104000210020184753
+:102320001249096A82B008B921B101E011B1012056
+:1023300002B0084702B0704710B50146487A0F282E
+:1023400018BF0E2807D10B4800F08AFDBDE81040E9
+:102350000020FFF789BE064C04F1080000F080FD64
+:1023600004F10800BDE81040FFF77ABEB412002067
+:1023700078130020D81200200C4800210160416031
+:10238000704710B500F00CF85C6819B1012904D150
+:10239000204301E024EA0000586082F3108810BD59
+:1023A000EFF3108272B6014B70470000B8130020A3
+:1023B0002DE9FC47594CDFF86891A5692840A061D8
+:1023C0004FF0010A4FF0FF3830E0491C54F831005B
+:1023D0000642FAD004EBC107184079681040014268
+:1023E00008BFC7F804807E68304000F09BF8606248
+:1023F0000AFA00F086437E60EFF3108172B6626ADB
+:1024000020690AFA02F2D24310402061022004EB54
+:10241000C00353F8086C1640401E43F8086CF6D110
+:1024200081F31088606A59F8201088476369206931
+:10243000A2691840104207D0E069216A084203D11E
+:10244000002103EA0206C1E7C046C046EFF3108947
+:1024500072B6216960690140A069014201BFE1696A
+:10246000206A014200F0C0FE89F31088C046C046D1
+:10247000A561BDE8F38738B51446EFF3108572B651
+:1024800000F050F8264941F8204085F3108831BD0E
+:1024900010B5EFF3108272B6204B1C6904431C6127
+:1024A00053F83140204343F8310082F3108810BDC7
+:1024B000EFF3108172B6194A536923EA000005E070
+:1024C000EFF3108172B6154A53691843506181F3D6
+:1024D00010887047EFF3108172B6104AD369184321
+:1024E000D061F4E72DE9F0410C4C626A266A206263
+:1024F000012101FA02F803E03946404600F075FE7A
+:10250000276AE5693D42F7D0404600F00BF825EA1E
+:102510000707E76126626062BDE8F0815010002085
+:10252000D411002002460020110C090404BF102021
+:10253000120412F07F4F04BF083012020FF218018C
+:1025400012F0704F04BF001D1201120FC0F11F00E6
+:10255000895C401A70470000040302020101010176
+:1025600000000000000000001FB5044600F030F835
+:102570004FF6524000F09DFE14B19DF80F00207000
+:102580000EE01FB5002408B10090042409B10191A8
+:10259000241D6B466A46E1B24FF6544000F089FEB6
+:1025A0009DF80E0004B010BD00F083FE9DF80E00F3
+:1025B00005B000BDF8B500F00BF84FF65A40F3E750
+:1025C000F8B500F10C026B4621214FF66640EBE7AF
+:1025D0006B46002200217047F8B500F10C026B46F3
+:1025E0000F214FF66840DFE700B587B000F010F824
+:1025F000012003220690ADF80420ADF8062000F07B
+:1026000011F800284CBFFF209DF8000007B000BD66
+:1026100000208DF800001822002101A800F09EBEC5
+:1026200003900691CDF814D0002101A8FFF713BE46
+:1026300018B50C46C7B0114600228DF800208DF861
+:102640001C008DF81D4022460DF11E0000F080FE9A
+:1026500000F02AF83F200C21ADF80400ADF8061078
+:1026600007A8012103900691A41C049400F02CF803
+:1026700000284CBFFF209DF8000048B010BD00B5F9
+:10268000C7B000F00AF80F2000F013F800284CBF84
+:10269000FF209DF8000047B000BD00228DF800200B
+:1026A0008DF81C008DF81D101822002101A800F0E3
+:1026B00055BEADF8060007A9022004903F22012074
+:1026C00003910690ADF80420CDF814D0002101A8A4
+:1026D000FFF7C1BD00B587B000208DF8000000F005
+:1026E000E0F840F20110ADF806003F22012006900C
+:1026F00000F0ECF800284CBFFF209DF8000007B068
+:1027000000BD2DE9F84107460128C7B088461546A7
+:102710001E4608BF022003D002280CBF1020002054
+:102720000DF11D010C1800F036F8012F8DF81C700A
+:1027300002D0022F18D019E002273A4641460DF187
+:102740001D0000F005FE2570667000F0AAF83F201D
+:102750004FF4817100F016F8FF1C049700F0B8F8F0
+:10276000002805D5FF2009E01027E6E7472005E00F
+:102770009DF8000010B94E9800F067F8FFE748B0E8
+:10278000BDE8F081ADF80400ADF8061007A80321FC
+:1027900003900691704703220021684600F0DEBDD9
+:1027A0002DE9F64F0C460546012CC7B09B4608BFE5
+:1027B000022003D0022C0CBF102000200DF11F01BD
+:1027C0000E18FFF7E8FF012CADF81C508DF81E40E5
+:1027D00002D0022C2CD02DE00227569C559DDDF80E
+:1027E0005091DDF84CA1DDF8488148993A4600F057
+:1027F00054F8A6F800B086F8028086F803A086F8A0
+:1028000004907571B47100F04CF83F20ADF80400ED
+:102810004FF4827107A8ADF80610039003210A3720
+:102820000497069100F054F8002805D5FF2009E030
+:102830001027D2E7472005E09DF8000010B957980F
+:1028400000F003F849B0BDE8F08FBDF80110018039
+:102850000020704730B5C7B01C464A9B00F026F8F0
+:1028600000258DF800508DF82140224619460DF1C3
+:10287000220000F06DFD00F014F83F204FF483714A
+:1028800000F01BF8A41D049400F022F800284CBFAF
+:10289000FF209DF8000047B030BD0DF11F0000F093
+:1028A00057BD1822002101A800F058BDADF81C004A
+:1028B000ADF81E108DF820207047ADF80400ADF87B
+:1028C000061007A80121039006917047ADF8042077
+:1028D000CDF814D0002101A8FFF7BDBC2DE9F84DBB
+:1028E000C7B09446DDF840E1519A559D569EDDF8FB
+:1028F0004CA1ADF81D108DF81C004FF0000BADF889
+:102900001FC08DF821308DF822E000F024F800F08F
+:1029100017F824F8095F668000F0CCF83F20832187
+:1029200000F0ECF8574406910D37049700F0CEF80C
+:1029300000284CBFFF209DF8000048B0BDE8F08D96
+:1029400088F800A007AC5499E419524608F1010038
+:10295000544400F0FDBC8DF82320174652998DF8A1
+:1029600000B00DF1240809A8B84400F0F1BC00B58E
+:10297000C7B000F00CF8852000F090F800F0A3F844
+:1029800000284CBFFF209DF8000047B000BD00218B
+:102990008DF81C008DF80010182201A800F0DEBC94
+:1029A0002DE9F841C7B04FF0000800F026F80DF10E
+:1029B0002300DDF844E14E9F4F9E509D529C8DF8C0
+:1029C0001F30C0F800E08DF800808DF820708DF881
+:1029D00021608DF822508DF8274000F06BF886209A
+:1029E000ADF8060007A90C2000F069F800284CBFDC
+:1029F000FF209DF8000000F08DB88DF81C0007A89E
+:102A0000417082707047F8B5C8B005460E4617464B
+:102A10001C4600F023F808A8467087708DF82050F7
+:102A200000F067F88A21ADF80A103F20032100F07A
+:102A300053F8002848BFFF200ED49DF8000058B975
+:102A40004F994E98BDF801202280BDF803200280E6
+:102A5000BDF805000880002049B0F0BD0722002124
+:102A6000684600F07BBC18B5C7B0044600F01EF8FD
+:102A70008DF81C40224600F049F800F01BF83F207A
+:102A80008E2100F04AF8641C049400F01FF800281E
+:102A90004CBFFF209DF8000048B010BDADF8060007
+:102AA00007A901203F2203910490704700208DF870
+:102AB000000070471822002101A800F04FBC0490CC
+:102AC0003F22012003910690ADF80420CDF814D0E8
+:102AD000002101A8FFF7BFBBADF80800059108A8C9
+:102AE000072104900791CDF818D0002102A8FFF724
+:102AF000B2BB1822002102A800F030BCADF80400DF
+:102B0000ADF8061007A80121039070470DF11D00D4
+:102B100000F01EBC48B0BDE8F081ADF80400ADF88F
+:102B2000061007A801210390069170471C49002058
+:102B3000087700221B48027000F036B818490A7F57
+:102B400041F82200087F401C0877704770B50446A2
+:102B50006078FF2802BFB4F8031001F47F41B1F59B
+:102B6000406F12D100260E4D00E0761C297FF0B296
+:102B700088420AD2F1B255F8211020468847010058
+:102B8000F3D002D0022805D006E02046BDE8704010
+:102B9000FFF715BA002070BD012070BD00000000D5
+:102BA00028130020E813002080B5C046C046C04668
+:102BB000C046C046C046C046C046C046C046C046E5
+:102BC000C046C046C046C046C046C046C046C046D5
+:102BD000C046C046C046C046C04600F005FCC046E0
+:102BE000C046C046C046BDE8014000F075BC0000CC
+:102BF000DFF800F0891000202DE9F0413C4F064637
+:102C000038780128884614461D4608BF02201BD08C
+:102C1000012139700020786000F018F8010011D10E
+:102C2000012E22462B46404602D100F054F802E025
+:102C30001146FFF7DDFF00F009F82E490A6822EA85
+:102C400006060E6000213970BDE8F0814FF47A70FD
+:102C500018E02A49CA680020002A07D5284B294ACB
+:102C60000B600A60C968002948BF012070472149EC
+:102C70000A6842F000420A6000200968002958BF33
+:102C80000120704770B50546FEF7AEFC06461A4CAB
+:102C90002068C10311D5FEF7A7FC801BA842F7D31B
+:102CA000032070BD124920604860012070BDFEF70E
+:102CB0009BFC801BA84209D3F2E72068C10744BFF0
+:102CC000012121604CF2FA310840EBD12068410328
+:102CD000EDD4002070BD10B506490C6844F0010425
+:102CE0000C6040F8042BBFF36F8F036010BD000031
+:102CF000601300201440005810400058084000584D
+:102D000023016745AB89EFCD2DE9F04100F053F881
+:102D1000884608BF02204CD000F052F800F055F869
+:102D2000010044D12968DFF8C470022919D14FF09D
+:102D3000FF32C8F800206E6800E0761C6968AA6857
+:102D400051188E4208D2304600F043F800F03DF8AA
+:102D50000100F2D0C8F800607A69DFF894100A40E8
+:102D60007A6139688A050FD53A6822F400723A60B0
+:102D7000396841F4006139603A6822F400623A60CF
+:102D8000396841F4007139603A6851050FD53968E6
+:102D900021F4806139603A6842F480523A603968BF
+:102DA00021F4805139603A6842F480623A6000212F
+:102DB0002170BDE8F081104C05462078012870474D
+:102DC000002001216060217070474FF47A70FFF796
+:102DD00059BF08490A6822F47E7242EAC00242F4EE
+:102DE000803242F002020A60704700000040005842
+:102DF00005FCFFFF14400058601300200146064800
+:102E0000064AC3798B4218BF904218BF0838F8D1E0
+:102E10008B4218BF00207047F873FF1F0070FF1F20
+:102E20000249016002490161704700BFED2E0008B0
+:102E3000172F0008006040607047EFF3108172B6F2
+:102E4000026882420CBF012000201CE0EFF31082D8
+:102E500072B603680B60486001600868416023E057
+:102E6000EFF3108272B6086043684B6041604868B7
+:102E7000016019E0EFF3108172B6436802681A60CE
+:102E800042680068426081F31088704710B5EFF324
+:102E9000108472B602680A600068FFE7FFF7EAFF75
+:102EA00084F3108810BD086082F31088704700001A
+:102EB00000F088BB6C486D49016001F1200242605E
+:102EC00001F13002826001F13C02026201F1440230
+:102ED000C26001F14C02026101F16802426101F13C
+:102EE0006C0282617831C16100F07EBB38B5044666
+:102EF0005F4D05F11000FFF79DFF5B494868A16831
+:102F00000160E168C160456005F11001816000F079
+:102F100087FB58482DE080B553494A681368012063
+:102F2000187200F083FB002002BD38B5514C504DA3
+:102F300007E0694605F11000FFF7A8FF0098216837
+:102F4000884705F11000FFF778FF0028F1D031BD68
+:102F500048484168084738B50446474D2846006050
+:102F600040604148C068A1680160456000F063FBB3
+:102F700042482168016061684160002032BD80B52F
+:102F80003949CA6813681020187200F05AFB0020F3
+:102F900002BD3549CA68394910680B68184738B509
+:102FA000364C354D06E069462846FFF76FFF00981E
+:102FB000616888472846FFF740FF0028F3D031BDFD
+:102FC00038B504462E4D2846006040602D4800600C
+:102FD000406025480069A1688160E168C1600561C1
+:102FE00021680160616841602169416161698161B5
+:102FF00031BD80B501462348FFF732FFBDE80240EE
+:103000000FF2050000F02DBB38B5174C1D4D08E040
+:1030100069462846FFF73AFF009920690069FFF7E3
+:103020001FFF2846FFF709FF0028F1D031BD10B57A
+:10303000154C2046006040600B4841690C60BDE8BB
+:10304000104000F022BB1CB50F4C06E0694620463C
+:10305000FFF71CFF0098C046C0462046FFF7EDFE74
+:103060000028F3D013BD000000800020B8890020A4
+:103070008C880020C8130020A4880020D0130020D2
+:103080003C8A0020C0130020448A0020BFF34F8FE9
+:10309000284929480A6802F4E06202430A60BFF343
+:1030A0004F8F00BFFDE710B52448254C88B001685C
+:1030B00041F400410160FFF75FF922490020FEF76B
+:1030C00090FD00F006FB01210120FFF75AF90020D6
+:1030D00000F034FC012000F031FC022000F02EFC56
+:1030E000012000F051FC0121002000F063FCFFF7FB
+:1030F000E1FE154A00210220FFF7BDF904F23C5021
+:103100000FF249010090019169460FF2450000F06D
+:103110007BF804F25470029004F5C96140F23C500F
+:1031200005900391049402A8FFF74AFFFFF7C0FE41
+:1031300008B010BD0CED00E00400FA0508000058CE
+:103140002C800020E01200204B3200087047000065
+:1031500070B50546686800F10B063188B1F5124F6D
+:1031600015D1002000F01BFCB0784FF0005478B966
+:103170002178022908BF20702FD000F0B9FA002171
+:103180000120FFF7FEF8FEF745FE0120287070BD14
+:103190000020FFF7E9F9FF281FD028B1002000F038
+:1031A000F3FB00F01DF8FCE72078022809D100218C
+:1031B0002170FFF7FFF9002000F0E6FB00F010F8A7
+:1031C000FCE70220207000210020FFF7DAF9002040
+:1031D00000F0DAFB00F004F8FCE7FFF757FF00BF50
+:1031E0000121002000F046BC70474FF0FF30FFF790
+:1031F000DFB800210220FFF74BB90220FFF76AB9C0
+:103200000220FFF76FB900007FB50C464D4D616895
+:103210004D4EE8612962284600F050FC2468746035
+:1032200006F1080000604060012000F068F801200D
+:103230003070296841B10FF2E9000FF2ED02009001
+:1032400001920294684688477FBD1FB53E4C04F149
+:103250000800FFF7F2FD00BB2178F1B1694604F1E7
+:103260000800FFF713FE3748C16949B10098029082
+:1032700001228DF8042001A888479DF8040000E091
+:1032800001202070207818B10098FFF7B2FE04E00A
+:10329000009904F10800FFF7D9FD04F10800FFF7D9
+:1032A000CCFD28B9207818B104F10800FFF7A1FF80
+:1032B0001FBD2DE9F04105460E4690461C460020F4
+:1032C00000F01DF8204F7868A0F80950C672324609
+:1032D00041460C30FEF718FF1A4A136900210020FE
+:1032E000984748F2E800FFF78BFF79688A78D21C8C
+:1032F00004F10800FEF708FFBDE8F04101201CB50D
+:103300001049124C096A20B901B188470020207089
+:1033100013BD0120207011B1BDE81C40084713BD4A
+:103320000020FFF76ABF000010B50146064C04F10B
+:103330000800FFF795FD04F10800BDE81040FFF715
+:1033400058BF00000413002088130020E913002058
+:1033500010B50446FEF7D8FE204610BD10B5044651
+:1033600010460A460146204600F0B2FB204610BD3A
+:103370001CB541780024FF2934D1B0F80310444A29
+:1033800040F60143C91A02D016391AD02AE05388F0
+:10339000B0F807105B1C99420BD100218DF8041086
+:1033A00000F10D0200920124B0F80B108DF8051009
+:1033B00015E0D288521C914214D101248DF80440AA
+:1033C00006E0117A71B11472032101248DF8041002
+:1033D00000F10D020092B0F80B008DF80500684670
+:1033E00000F0BAFB204616BD10B586B02948284C1F
+:1033F000FFF7A4FB0094082301220FF29C01022096
+:10340000FFF77FF9002104910191A01C05900A2289
+:1034100001230421039202930091042320880FF2D8
+:1034200088020221FFF7BCF9002104910291019169
+:10343000201D05900A22202103920091012320885B
+:103440000FF274020221FFF7ABF9A01D05900121D4
+:103450000491029100200A2201900421039200911C
+:10346000142320880FF260020221FFF799F900204F
+:10347000207206B010BD80B50091012204488188F9
+:103480000272012300880022FFF7E4F902BD000068
+:10349000A4130020713300088FE5B3D52E7F4A981E
+:1034A0002A487ACC20FE000019ED82AEED214C9D19
+:1034B0004145228E22FE000019ED82AEED214C9D89
+:1034C0004145228E23FE000019ED82AEED214C9D78
+:1034D0004145228E24FE000070470000C06808406D
+:1034E000884201D10120704700207047C069084020
+:1034F000884201D1012070470020704710B5664C0A
+:1035000002212046FFF7F2FF38B16068C04381070F
+:1035100003D5FFF744FD022018E001212046FFF704
+:10352000E5FF38B16068C043C10703D5FFF7FDFC74
+:1035300001200BE008212046FFF7D8FF38B1606872
+:10354000C043010703D5FFF77EFD0820A06010BD32
+:1035500010B5514C00F033F818B96068C0438103CE
+:1035600006D400F02CF830B96068C043810302D55E
+:10357000BDE810406EE0082100F022F870B96068E4
+:10358000C04301030AD56068444940F400206060EC
+:10359000086880474FF40020A06010BD202100F093
+:1035A0000FF858B96068C043810207D5606840F4DD
+:1035B00000106060BDE81040FFF7CABC10BD0221DA
+:1035C00020468BE73648016841F4007101603548B8
+:1035D000026842F40072026040BF20BF32480168B6
+:1035E00041F400410160704780B53048016841F402
+:1035F00080110160006800F4801000900098264857
+:10360000016841F001010160026842F48032026009
+:103610002C20FEF7FEF8BDE802402D20FEF7F9B899
+:1036200023480168490849000160704721494FF467
+:103630008030086070471E48016821F00201016077
+:1036400070471B484FF400314160016821F400319C
+:10365000016070471648016841F400310160FFF7CE
+:1036600098BC38B504460C4D08212846FFF736FFB4
+:1036700030B10A480460686820F40020686031BDF9
+:10368000A0474FF40021A96031BD0948016821F02D
+:103690000801016070470000000C0058E013002092
+:1036A000D4080058200800580C0400585000005856
+:1036B000040C0058080C0058484900E0484981B003
+:1036C0000A6802430A60096808400090009801B047
+:1036D000704780B500F028FB00F028FB41480168E6
+:1036E00041F48031016000F033FBBDE801400EE0A1
+:1036F00000B587B068460FF210211C22FEF714FDBA
+:10370000FFF795FC6846FEF767FF07B000BDF0B510
+:1037100085B068461421FDF76DFF002600250024C2
+:1037200000210FF2D40000EBC102907988B1136838
+:10373000B3F1904F08D02C4FBB4208D02B4FBB4267
+:1037400004BF9088044304E09088064301E0908819
+:103750000543491C2229E4DB0020029001210320BB
+:1037600003900191B0B288B100900120FFF7A4FF4F
+:103770000120FFF7A3FF69464FF09040FDF73EFFA1
+:103780000022B1B24FF09040FDF7F6FFA8B280B131
+:1037900000900220FFF790FF0220FFF78FFF124EEC
+:1037A00069463046FDF72AFF0022A9B23046FDF7F0
+:1037B000E3FFA0B280B100900420FFF77DFF04205A
+:1037C000FFF77CFF094D69462846FDF717FF0022E9
+:1037D000A1B22846FDF7D0FF05B0F0BD4C0000585F
+:1037E0004C010058900800580004004800080048A8
+:1037F0000020FDF770BB0000000000480100000041
+:103800000000004801000000000000480100000026
+:103810000000004801000000000000480100000016
+:103820000000004801000000000000480100000006
+:1038300000000048010000000000004801000000F6
+:1038400000000048010000000000004801000000E6
+:1038500000000048010000000000004801000000D6
+:1038600000000048010000000000004801000000C6
+:1038700000000048010000000000004801000000B6
+:1038800000000048010000000000004801000000A6
+:103890000000004801000000000000480100000096
+:1038A0000000004801000000000000480100000086
+:1038B0000000004801000000000000480100000076
+:1038C0000000004801000000000000480100000066
+:1038D0000000004801000000000000480100000056
+:1038E0000000004801000000000000480100000046
+:1038F0000000004801000000000000480100000036
+:10390000000000480100000000000000000000006E
+:1039100000000000F83700082480002028800020E4
+:1039200022040400DFF81C1181B00A6802430A6017
+:10393000096808400090009801B0704778B585B0DC
+:10394000044600F07BF800F077F800F010F80095DE
+:10395000012001900021022003900291694656F84F
+:103960002400FDF74BFE00F009F806B070BD0FF221
+:10397000E400DFF8D46030F81450704756F82400A3
+:1039800000222946FDF7F8BE0FF2C801DFF8B83073
+:1039900031F8101053F820000122FDF7EDBE0FF2B0
+:1039A000B401DFF8A43031F8101053F820000022E1
+:1039B000FDF7E2BEF0B585B005460C4600F03EF8D6
+:1039C0002DB1012D08BF102002D0022D02D10120FF
+:1039D000FFF7A8FF2000DFF874600FF280070DD119
+:1039E00037F815000090002101910120029002217A
+:1039F000039100F01CF8012000F05CFA012C14D1B6
+:103A000037F8150000900121DFF844000190029181
+:103A100000F00DF80FF24C00445D00220F2160B25F
+:103A2000FDF7DAFE60B2FDF7F4FE05B0F0BD6946C1
+:103A300056F82500FDF7E2BD022073E76846142121
+:103A4000FDF7D8BD4C00005838100020441000206D
+:103A50000000211020000100020000000100100001
+:103A600040000000060A17001148016841F4807107
+:103A70000160704710B50C460E490028086805D152
+:103A8000810507D500F046FA20B110BD810558BF69
+:103A900000F03AFA0848016821F00401012C0160A5
+:103AA00001D130BF10BD40BF20BF20BF10BD0000FE
+:103AB000000400581404005810ED00E002490160B1
+:103AC00002490161704700BF572F00087F2F00088F
+:103AD00062F30F2262F31F42401810F0030308D074
+:103AE000C91A1FD3DB0748BF00F8012D28BF20F8F3
+:103AF000022D130030B414461546103928BF20E9B2
+:103B00003C00FAD8490728BF20E90C0048BF40F81C
+:103B1000042D890028BF20F8022D48BF00F8012D90
+:103B200030BC7047C91818BF00F8012DCB0728BF5B
+:103B300000F8012D7047000000EB8100604AD0F8CA
+:103B40008010914201D0012070470020704742F45C
+:103B5000806240F8212070472DE9F8430546DFF8E0
+:103B600064912879DFF86081584E20B1012825D072
+:103B7000032869D010E029680A78012A4FF0006014
+:103B800004D0022A0AD0072A10D005E000223060B3
+:103B9000727400F0ACF83274BDE8F183012130603A
+:103BA000717400F0A4F800203074F5E701228DF85C
+:103BB000002069460220FFF75EFCEDE76C790027E4
+:103BC00002214046FFF7B8FF0028F9D1FFF741F87E
+:103BD00022E0296806F1080339441844FEF794FAF4
+:103BE00000F07EF8D6E9022331680120FFF704F8DF
+:103BF000D6F800C0D6E90201DCE900238B4208BFF9
+:103C0000824209D10CF108003060307CC0F108001C
+:103C1000241AC71900203074307CC0F10802944285
+:103C2000D7D2FFF724F800F057F8002CB4D028685A
+:103C3000337CC11906F1080022461844FEF764FAE5
+:103C4000307C24183474A7E7307CD0B10221404680
+:103C5000FFF772FF0028F9D1FEF7FBFF04E000F048
+:103C60003FF80120FEF7C8FF3168D6E90223D1E909
+:103C700000459D4208BF9442F1D1FEF7F8FF00F0E5
+:103C80002BF8707C90B1012886D14FF000510020B4
+:103C90000870BFF34F8F0E490E480A6802F4E062C5
+:103CA00002430A60BFF34F8F00BFFDE7FEF75CFCE5
+:103CB0000020FEF759FC01210020FFF7DBFEFAE7A8
+:103CC00000040080104000580014005848130020E1
+:103CD0000CED00E00400FA0500220221404636E720
+:103CE000D9F80000C00C10F00100F9D17047286825
+:103CF000C178317029688878707028684178B1700F
+:103D000070470000032010B5FDF759FD0F2000F0AB
+:103D100023F90024002814BF012400F017F82046DE
+:103D200010BD084880687047074805E006480168EC
+:103D300041F0020101607047016841F0010101603A
+:103D40007047000078100020042004E07047000055
+:103D500080B5FFF74DFD022100910023044800F1DA
+:103D600024014FF48052001D00F018F901BD00003D
+:103D7000140000201CB5FFF7C5FF5A4C60684001D5
+:103D80000ED56068C0000BD4FFF76EFEFFF76CFE27
+:103D9000206840F480302060216821F48031216067
+:103DA00000F042F8FFF760FEFFF75EFE206840F08B
+:103DB0000100206020688007FCD560684A4920F433
+:103DC000404040F480406060086820F07000086067
+:103DD00046480268C2F303200090009830B90A6890
+:103DE0001209120142F004020A6008E000980A6811
+:103DF000801E80F30400120940EA021008600022CD
+:103E0000086840F4004008603948016802600269AF
+:103E100002F05002026100F028F8FFF744F94FF079
+:103E2000FF30FEF7C5FAFAE7324881B0016841F485
+:103E3000801101603F21006800F48010009000981C
+:103E40002D4841604161016841F47C1101600269C3
+:103E500042F47C120261016841F03F010160026995
+:103E600042F03F02026101B0704710B5FFF7FCFD60
+:103E7000FFF7FAFD1B48214C016821F4407141F421
+:103E8000807101600F21026842F4004202601C4808
+:103E9000816047F6FF71C160046000F093F8CA20AA
+:103EA0006062FF2153206062A068C008C000A0606B
+:103EB000616210BD38B50446FDF796FB14F1010FA1
+:103EC000054609D0FFF72DFF041905E00D480168EC
+:103ED00021F00401016030BFFDF786FB401BA042CA
+:103EE000F4D331BD900000581C0400585875FF1FD2
+:103EF0008008005850000058040C0058002800406A
+:103F0000E012002010ED00E01048016841F480410B
+:103F10000160704710B50D4A0D4B106820F48040C9
+:103F2000106032211C680B48B4FBF0F04843516923
+:103F30008B0506D5002818BF401EF8D101E00020EF
+:103F400010BD50698105FAD5032010BD000400584A
+:103F50008410002040420F0070B50F4E0446B06838
+:103F60000025A8B1FDF7F5F9B2684FF47A71B1FBFD
+:103F7000F2F1B0FBF1F0FDF766FC48B9102C07D266
+:103F8000002221464FF0FF30FDF726FC746000E070
+:103F90000125284670BD00BF7810002010B5029C96
+:103FA000016042600021C160016141618161038162
+:103FB000A107047704D5008910B14FF0FF3010BD80
+:103FC000002010BD38B5040044D094F8210028B971
+:103FD000002184F820102046C046C04600F049F871
+:103FE000FF2510B100F03FF834E02168DFF8B000A1
+:103FF0008A6802408A6021688A686368206903438E
+:10400000A06903431A438A602168E0680861206858
+:104010000169A26841EA024101612068C16821F09A
+:104020008001C1602068C16C89088900C164216871
+:10403000CA6CE369606903431A43CA6420688168F3
+:10404000880609D400F020F830B1206845620421C8
+:1040500000F01FF8012032BD20684562012184F87C
+:104060002110002032BD20684562042184F821100F
+:104070007047022084F82100CA202168486253203A
+:1040800022685062204626E020460BE02068C0F8F7
+:10409000248084F82110002084F82000704700005C
+:1040A000BFFF8FFF70B5044640F2E9362068C16853
+:1040B00021F0A001C160FDF797FA05462068C168AC
+:1040C000880606D4FDF790FA401BB042F6D30320D1
+:1040D00070BD002070BD70B504462068C1684A06F6
+:1040E00012D44FF0FF32C26040F2E936FDF77CFA9D
+:1040F00005462068C168480606D4FDF775FA401BDE
+:10410000B042F6D3032070BD002070BD4748484A36
+:1041100001681268B1F1006F0AD3120302F4FE22A3
+:10412000444882188A4203D308684349884201D030
+:10413000002070470120704780B540494048086022
+:10414000016881F308884068804730BF01BD10B521
+:10415000FFF7DCFF4FF0005420B100202070BDE8D5
+:104160001040E9E70120207007206070FF20A07058
+:1041700010BD38B5334C2068C00002D420688001DF
+:104180001AD54FF00055287828B9FFF7BFFF10B1B6
+:10419000FFF7D2FF12E0287848B9FFF7B7FF30B930
+:1041A0000120287007206870FF20A87006E028789A
+:1041B000012818BF022801D0FFF7C9FF2248016873
+:1041C00041F4700101600020FEF718FE40B18079D3
+:1041D0001E49A160A16821F47C5141EA0021A1603F
+:1041E0004FF0B040016841F48031016018490A681D
+:1041F000D208D20042F001020A600A6802F0070207
+:10420000012AFAD101688903FCD5816889088900EF
+:1042100041F002018160816801F00C010829FAD1A6
+:10422000016849084900016031BD00004071000883
+:1042300080400058FCFFFF07298A449408ED00E005
+:10424000007000089400005888ED00E0FECAFECA25
+:1042500000400058010000000300000005000000BD
+:104260000100000001000000060000000A0000003C
+:104270002000000002000000040000000800000010
+:10428000100000004000000080000000000100005D
+:1042900000020000A0860100400D0300801A060005
+:1042A00000350C0040420F0080841E0000093D00D4
+:1042B00000127A000024F40000366E010048E80184
+:1042C000006CDC02000000000000000000000000A4
+:1042D0000000000019E050F8042BD30744BFA9F1F7
+:1042E00001039A18091F0023042942F8043BF9D25C
+:1042F0005FEA817C134604D54FF0000CA2F800C0A1
+:104300009B1CC90744BF0021197050F8041B0029E9
+:10431000E1D1704730B5016884684218416802EB0A
+:104320005103C9070BD54C4409E012F9011B12F8DF
+:10433000015B002904F8015B05D5491CF9D19A42BB
+:10434000F3D10C3030BD491EF1D5F8E77047FEE7D8
+:1043500070477047704700F00DB870470020FCF7B9
+:10436000D0BD0020FCF7D3BDFDF7EBBBFFF7F0B8E5
+:10437000FFF7C4B802490A68886882180A60704763
+:104380007810002010B5074979441831064C7C4458
+:10439000163404E00A68081D114488470146A1420A
+:1043A000F8D110BD2C000000600000004EF68851CE
+:1043B000CEF20001086840F470000860BFF34F8F30
+:1043C000BFF36F8F4FF00070E1EE100A70470000EE
+:1043D00005FFFFFF34030000B81000208008000034
+:1043E0002C800020000000002DFFFFFF8401000052
+:1043F0004A010000040000201DFFFFFF1902000019
+:1044000004000000248000200000000000000000E4
+:104410000000000000000000010000000200000099
+:1044200003000000040000000120C046002801D065
+:10443000FFF7A8FFAFF300800020AFF30080FFF785
+:1044400099FC00F000F800F001B80000074638467B
+:1044500000F002F8FBE7000080B5AFF30080024AED
+:1044600011001820ABBEFBE7260002000148804780
+:1044700001480047734100087D440008AFF3008005
+:10448000FFF794FFFFF7D0FFFFF7FEBFFFF7FEBF78
+:10449000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF50
+:1044A000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF40
+:1044B000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF30
+:1044C000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF20
+:1044D000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF10
+:1044E000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF00
+:1044F000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFF0
+:10450000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFDF
+:10451000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFCF
+:10452000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFBF
+:10453000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFAF
+:10454000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF9F
+:10455000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF8F
+:10456000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF7F
+:10457000030DFF0186F400000181008100810081AC
+:104580000081008100810081008100810081008123
+:104590000081008100810081008100810081008113
+:1045A0000081008100810081008100810081008103
+:1045B000008100810081008100BC000A04004800E5
+:1045C00004004800040048FD00044800100048FDB5
+:1045D000000048EC00F8FFF0000010FD000001FCB6
+:1045E0000032093D0030B50A4B5A6842F480225A25
+:1045F00060EFF3108472B6802251F8045B40F80437
+:104600005B521EF9D11868C103FCD484F3108830C2
+:07461000BD10400058F80046
+:040000050800447D2E
+:00000001FF
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/app_common.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/app_common.h
new file mode 100644
index 000000000..4defc5d7a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/app_common.h
@@ -0,0 +1,114 @@
+/**
+ ******************************************************************************
+  * File Name          : app_common.h
+  * Description        : App Common application configuration file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_COMMON_H
+#define APP_COMMON_H
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "app_conf.h"
+
+  /* -------------------------------- *
+   *  Basic definitions               *
+   * -------------------------------- */
+
+#undef NULL
+#define NULL                    0
+
+#undef FALSE
+#define FALSE                   0
+
+#undef TRUE
+#define TRUE                    (!0)
+
+  /* -------------------------------- *
+   *  Critical Section definition     *
+   * -------------------------------- */
+#define BACKUP_PRIMASK()    uint32_t primask_bit= __get_PRIMASK()
+#define DISABLE_IRQ()       __disable_irq()
+#define RESTORE_PRIMASK()   __set_PRIMASK(primask_bit)
+
+  /* -------------------------------- *
+   *  Macro delimiters                *
+   * -------------------------------- */
+
+#define M_BEGIN     do {
+
+#define M_END       } while(0)
+
+  /* -------------------------------- *
+   *  Some useful macro definitions   *
+   * -------------------------------- */
+
+#define MAX( x, y )          (((x)>(y))?(x):(y))
+
+#define MIN( x, y )          (((x)<(y))?(x):(y))
+
+#define MODINC( a, m )       M_BEGIN  (a)++;  if ((a)>=(m)) (a)=0;  M_END
+
+#define MODDEC( a, m )       M_BEGIN  if ((a)==0) (a)=(m);  (a)--;  M_END
+
+#define MODADD( a, b, m )    M_BEGIN  (a)+=(b);  if ((a)>=(m)) (a)-=(m);  M_END
+
+#define MODSUB( a, b, m )    MODADD( a, (m)-(b), m )
+
+#define PAUSE( t )           M_BEGIN \
+                               __IO int _i; \
+                               for ( _i = t; _i > 0; _i -- ); \
+                             M_END
+
+#define DIVF( x, y )         ((x)/(y))
+
+#define DIVC( x, y )         (((x)+(y)-1)/(y))
+
+#define DIVR( x, y )         (((x)+((y)/2))/(y))
+
+#define SHRR( x, n )         ((((x)>>((n)-1))+1)>>1)
+
+#define BITN( w, n )         (((w)[(n)/32] >> ((n)%32)) & 1)
+
+#define BITNSET( w, n, b )   M_BEGIN (w)[(n)/32] |= ((U32)(b))<<((n)%32); M_END
+
+  /* -------------------------------- *
+   *  Compiler                         *
+   * -------------------------------- */
+#define PLACE_IN_SECTION( __x__ )  __attribute__((section (__x__)))
+
+#ifdef WIN32
+#define ALIGN(n)
+#else
+#define ALIGN(n)             __attribute__((aligned(n)))
+#endif
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*APP_COMMON_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/app_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/app_conf.h
new file mode 100644
index 000000000..30cbe8ebc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/app_conf.h
@@ -0,0 +1,560 @@
+/**
+ ******************************************************************************
+ * @file    app_conf.h
+ * @author  MCD Application Team
+ * @brief   Application configuration file
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_CONFIG_H
+#define __APP_CONFIG_H
+
+#include "hw.h"
+#include "hw_conf.h"
+#include "hw_if.h"
+
+/******************************************************************************
+ * OTA Application Config
+ ******************************************************************************/
+
+/**< generic parameters ******************************************************/
+
+/**
+ * Define Tx Power
+ */   
+#define CFG_TX_POWER                      (0x18) /**< 0dbm */
+
+/**
+ * Define Advertising parameters
+ */
+#define CFG_ADV_BD_ADDRESS                (0x7257acd87a6c)
+#define CFG_FAST_CONN_ADV_INTERVAL_MIN    (0x80)  /**< 80ms */
+#define CFG_FAST_CONN_ADV_INTERVAL_MAX    (0xA0)  /**< 100ms */
+#define CFG_LP_CONN_ADV_INTERVAL_MIN      (0x640) /**< 1s */
+#define CFG_LP_CONN_ADV_INTERVAL_MAX      (0xFA0) /**< 2.5s */
+
+/**
+ * Define IO Authentication
+ */
+#define CFG_BONDING_MODE                  (1)
+#define CFG_FIXED_PIN                     (111111)
+#define CFG_USED_FIXED_PIN                (0)
+#define CFG_ENCRYPTION_KEY_SIZE_MAX       (16)
+#define CFG_ENCRYPTION_KEY_SIZE_MIN       (8)
+
+/**
+ * Define IO capabilities
+ */
+#define CFG_IO_CAPABILITY_DISPLAY_ONLY       (0x00)
+#define CFG_IO_CAPABILITY_DISPLAY_YES_NO     (0x01)
+#define CFG_IO_CAPABILITY_KEYBOARD_ONLY      (0x02)
+#define CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT (0x03)
+#define CFG_IO_CAPABILITY_KEYBOARD_DISPLAY   (0x04)
+
+#define CFG_IO_CAPABILITY                     CFG_IO_CAPABILITY_DISPLAY_ONLY
+
+/**
+ * Define MITM modes
+ */
+#define CFG_MITM_PROTECTION_NOT_REQUIRED      (0x00)
+#define CFG_MITM_PROTECTION_REQUIRED          (0x01)
+
+#define CFG_MITM_PROTECTION                   CFG_MITM_PROTECTION_REQUIRED
+
+/**
+*   Identity root key used to derive LTK and CSRK
+*/
+#define CFG_BLE_IRK     {0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0,0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0}
+
+/**
+* Encryption root key used to derive LTK and CSRK
+*/
+#define CFG_BLE_ERK     {0xfe,0xdc,0xba,0x09,0x87,0x65,0x43,0x21,0xfe,0xdc,0xba,0x09,0x87,0x65,0x43,0x21}
+
+/* USER CODE BEGIN Generic_Parameters */
+/**
+ * SMPS supply
+ * SMPS not used when Set to 0
+ * SMPS used when Set to 1
+ */
+#define CFG_USE_SMPS    1
+/* USER CODE END Generic_Parameters */
+
+
+/**< specific parameters */
+/*****************************************************/
+#ifdef LITTLE_DORY
+#define PUSH_BUTTON_SW1_EXTI_IRQHandler                         EXTI0_IRQHandler
+#else
+#define PUSH_BUTTON_SW1_EXTI_IRQHandler                         EXTI4_IRQHandler
+#endif
+
+/******************************************************************************
+ * Information Table
+ *
+  * Version
+  * [0:3]   = Build - 0: Untracked - 15:Released - x: Tracked version
+  * [4:7]   = branch - 0: Mass Market - x: ...
+  * [8:15]  = Subversion
+  * [16:23] = Version minor
+  * [24:31] = Version major
+  *
+ ******************************************************************************/
+#define CFG_FW_MAJOR_VERSION      (0)
+#define CFG_FW_MINOR_VERSION      (0)
+#define CFG_FW_SUBVERSION         (1)
+#define CFG_FW_BRANCH             (0)
+#define CFG_FW_BUILD              (0)
+
+/**
+* AD Element - DEV ID
+*/
+#define CFG_DEV_ID_P2P_SERVER1                  (0x83)
+#define CFG_DEV_ID_P2P_SERVER2                  (0x84)
+#define CFG_DEV_ID_P2P_ROUTER                   (0x85)
+#define CFG_DEV_ID_OTA_FW_UPDATE                (0x86)
+
+/**
+* AD Element - Group B Feature
+*/
+/* LSB - Firt Byte */
+#define CFG_FEATURE_OTA_SW                      (0x08)
+
+
+/**
+ * Define the start address where the application shall be located
+ */
+#define CFG_APP_START_SECTOR_INDEX          (7)
+
+/**
+ * Define list of reboot reason
+ */
+#define CFG_REBOOT_ON_FW_APP          (0x00)
+#define CFG_REBOOT_ON_BLE_OTA_APP     (0x01)
+#define CFG_REBOOT_ON_CPU2_UPGRADE    (0x02)
+
+/**
+ * Define mapping of OTA messages in SRAM
+ */
+#define CFG_OTA_REBOOT_VAL_MSG            (*(uint8_t*)(SRAM1_BASE+0))
+#define CFG_OTA_START_SECTOR_IDX_VAL_MSG  (*(uint8_t*)(SRAM1_BASE+1))
+#define CFG_OTA_NBR_OF_SECTOR_VAL_MSG     (*(uint8_t*)(SRAM1_BASE+2))
+
+/******************************************************************************
+ * BLE Stack
+ ******************************************************************************/
+/**
+ * Maximum number of simultaneous connections that the device will support.
+ * Valid values are from 1 to 8
+ */
+#define CFG_BLE_NUM_LINK            8
+
+/**
+ * Maximum number of Services that can be stored in the GATT database.
+ * Note that the GAP and GATT services are automatically added so this parameter should be 2 plus the number of user services
+ */
+#define CFG_BLE_NUM_GATT_SERVICES   8
+
+/**
+ * Maximum number of Attributes
+ * (i.e. the number of characteristic + the number of characteristic values + the number of descriptors, excluding the services)
+ * that can be stored in the GATT database.
+ * Note that certain characteristics and relative descriptors are added automatically during device initialization
+ * so this parameters should be 9 plus the number of user Attributes
+ */
+#define CFG_BLE_NUM_GATT_ATTRIBUTES 68
+
+/**
+ * Maximum supported ATT_MTU size
+ */
+#define CFG_BLE_MAX_ATT_MTU             (156)
+
+/**
+ * Size of the storage area for Attribute values
+ *  This value depends on the number of attributes used by application. In particular the sum of the following quantities (in octets) should be made for each attribute:
+ *  - attribute value length
+ *  - 5, if UUID is 16 bit; 19, if UUID is 128 bit
+ *  - 2, if server configuration descriptor is used
+ *  - 2*DTM_NUM_LINK, if client configuration descriptor is used
+ *  - 2, if extended properties is used
+ *  The total amount of memory needed is the sum of the above quantities for each attribute.
+ */
+#define CFG_BLE_ATT_VALUE_ARRAY_SIZE    (1344)
+
+/**
+ * Prepare Write List size in terms of number of packet with ATT_MTU=23 bytes
+ */
+#define CFG_BLE_PREPARE_WRITE_LIST_SIZE         ( 0x3A )
+
+/**
+ * Number of allocated memory blocks
+ */
+#define CFG_BLE_MBLOCK_COUNT            ( 0x79 )
+
+/**
+ * Enable or disable the Extended Packet length feature. Valid values are 0 or 1.
+ */
+#define CFG_BLE_DATA_LENGTH_EXTENSION   1
+
+/**
+ * Sleep clock accuracy in Slave mode (ppm value)
+ */
+#define CFG_BLE_SLAVE_SCA   500
+
+/**
+ * Sleep clock accuracy in Master mode
+ * 0 : 251 ppm to 500 ppm
+ * 1 : 151 ppm to 250 ppm
+ * 2 : 101 ppm to 150 ppm
+ * 3 : 76 ppm to 100 ppm
+ * 4 : 51 ppm to 75 ppm
+ * 5 : 31 ppm to 50 ppm
+ * 6 : 21 ppm to 30 ppm
+ * 7 : 0 ppm to 20 ppm
+ */
+#define CFG_BLE_MASTER_SCA   0
+
+/**
+ *  Source for the 32 kHz slow speed clock
+ *  1 : internal RO
+ *  0 : external crystal ( no calibration )
+ */
+#define CFG_BLE_LSE_SOURCE  0
+
+/**
+ * Start up time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us)
+ */
+#define CFG_BLE_HSE_STARTUP_TIME  0x148
+
+/**
+ * Maximum duration of the connection event when the device is in Slave mode in units of 625/256 us (~2.44 us)
+ */
+#define CFG_BLE_MAX_CONN_EVENT_LENGTH  ( 0xFFFFFFFF )
+
+/**
+ * Viterbi Mode
+ * 1 : enabled
+ * 0 : disabled
+ */
+#define CFG_BLE_VITERBI_MODE  1
+
+/**
+ *  LL Only Mode
+ *  1 : LL Only
+ *  0 : LL + Host
+ */
+#define CFG_BLE_LL_ONLY  0
+
+
+/******************************************************************************
+ * Transport Layer
+ ******************************************************************************/
+/**
+ * Queue length of BLE Event
+ * This parameter defines the number of asynchronous events that can be stored in the HCI layer before
+ * being reported to the application. When a command is sent to the BLE core coprocessor, the HCI layer
+ * is waiting for the event with the Num_HCI_Command_Packets set to 1. The receive queue shall be large
+ * enough to store all asynchronous events received in between.
+ * When CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE is set to 27, this allow to store three 255 bytes long asynchronous events
+ * between the HCI command and its event.
+ * This parameter depends on the value given to CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE. When the queue size is to small,
+ * the system may hang if the queue is full with asynchronous events and the HCI layer is still waiting
+ * for a CC/CS event, In that case, the notification TL_BLE_HCI_ToNot() is called to indicate
+ * to the application a HCI command did not receive its command event within 30s (Default HCI Timeout).
+ */
+#define CFG_TLBLE_EVT_QUEUE_LENGTH 5
+
+/**
+ * This parameter should be set to fit most events received by the HCI layer. It defines the buffer size of each element
+ * allocated in the queue of received events and can be used to optimize the amount of RAM allocated by the Memory Manager.
+ * It should not exceed 255 which is the maximum HCI packet payload size (a greater value is a lost of memory as it will
+ * never be used)
+ * It shall be at least 4 to receive the command status event in one frame.
+ * The default value is set to 27 to allow receiving an event of MTU size in a single buffer. This value maybe reduced
+ * further depending on the application.
+ *
+ */
+#define CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE 255   /**< Set to 255 with the memory manager and the mailbox */
+
+#define TL_BLE_EVENT_FRAME_SIZE ( TL_EVT_HDR_SIZE + CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE )
+
+/******************************************************************************
+ * UART interfaces
+ ******************************************************************************/
+
+/**
+ * Select UART interfaces
+ */
+#define CFG_DEBUG_TRACE_UART      hw_uart1
+#define CFG_CONSOLE_MENU		hw_lpuart1
+
+/******************************************************************************
+ * USB interface
+ ******************************************************************************/
+
+/**
+ * Enable/Disable USB interface
+ */
+#define CFG_USB_INTERFACE_ENABLE        0
+
+/******************************************************************************
+ * Low Power
+ ******************************************************************************/
+/**
+ *  When set to 1, the low power mode is enable
+ *  When set to 0, the device stays in RUN mode
+ */
+#define CFG_LPM_SUPPORTED   1
+
+/******************************************************************************
+ * Timer Server
+ ******************************************************************************/
+/**
+ *  CFG_RTC_WUCKSEL_DIVIDER:  This sets the RTCCLK divider to the wakeup timer.
+ *  The higher is the value, the better is the power consumption and the accuracy of the timerserver
+ *  The lower is the value, the finest is the granularity
+ *
+ *  CFG_RTC_ASYNCH_PRESCALER: This sets the asynchronous prescaler of the RTC. It should as high as possible ( to ouput
+ *  clock as low as possible) but the output clock should be equal or higher frequency compare to the clock feeding
+ *  the wakeup timer. A lower clock speed would impact the accuracy of the timer server.
+ *
+ *  CFG_RTC_SYNCH_PRESCALER: This sets the synchronous prescaler of the RTC.
+ *  When the 1Hz calendar clock is required, it shall be sets according to other settings
+ *  When the 1Hz calendar clock is not needed, CFG_RTC_SYNCH_PRESCALER should be set to 0x7FFF (MAX VALUE)
+ *
+ *  CFG_RTCCLK_DIVIDER_CONF:
+ *  Shall be set to either 0,2,4,8,16
+ *  When set to either 2,4,8,16, the 1Hhz calendar is supported
+ *  When set to 0, the user sets its own configuration
+ *
+ *  The following settings are computed with LSI as input to the RTC
+ */
+#define CFG_RTCCLK_DIVIDER_CONF 0
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 0)
+/**
+ * Custom configuration
+ * It does not support 1Hz calendar
+ * It divides the RTC CLK by 16
+ */
+#define CFG_RTCCLK_DIV  (16)
+#define CFG_RTC_WUCKSEL_DIVIDER (0)
+#define CFG_RTC_ASYNCH_PRESCALER (CFG_RTCCLK_DIV - 1)
+#define CFG_RTC_SYNCH_PRESCALER (0x7FFF)
+
+#else
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 2)
+/**
+ * It divides the RTC CLK by 2
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (3)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 4)
+/**
+ * It divides the RTC CLK by 4
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (2)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 8)
+/**
+ * It divides the RTC CLK by 8
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (1)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 16)
+/**
+ * It divides the RTC CLK by 16
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (0)
+#endif
+
+#define CFG_RTCCLK_DIV              CFG_RTCCLK_DIVIDER_CONF
+#define CFG_RTC_ASYNCH_PRESCALER    (CFG_RTCCLK_DIV - 1)
+#define CFG_RTC_SYNCH_PRESCALER     (DIVR( LSE_VALUE, (CFG_RTC_ASYNCH_PRESCALER+1) ) - 1 )
+
+#endif
+
+/** tick timer value in us */
+#define CFG_TS_TICK_VAL           DIVR( (CFG_RTCCLK_DIV * 1000000), LSE_VALUE )
+
+typedef enum
+{
+    CFG_TIM_PROC_ID_ISR,
+} CFG_TimProcID_t;
+
+/******************************************************************************
+ * Debug
+ ******************************************************************************/
+/**
+ * When set, this resets some hw resources to set the device in the same state than the power up
+ * The FW resets only register that may prevent the FW to run properly
+ *
+ * This shall be set to 0 in a final product
+ *
+ */
+#define CFG_HW_RESET_BY_FW        1
+
+#define CFG_LED_SUPPORTED         1
+#define CFG_BUTTON_SUPPORTED      1
+
+/**
+ * keep debugger enabled while in any low power mode when set to 1
+ * should be set to 0 in production
+ */
+#define CFG_DEBUGGER_SUPPORTED    1
+
+/**
+ * When set to 1, the traces are enabled in the BLE services
+ */
+#define CFG_DEBUG_BLE_TRACE     1
+
+/**
+ * Enable or Disable traces in application
+ */
+#define CFG_DEBUG_APP_TRACE     1
+
+#if (CFG_DEBUG_APP_TRACE != 0)
+#define APP_DBG_MSG                 PRINT_MESG_DBG
+#else
+#define APP_DBG_MSG                 PRINT_NO_MESG
+#endif
+
+
+#if ( (CFG_DEBUG_BLE_TRACE != 0) || (CFG_DEBUG_APP_TRACE != 0) )
+#define CFG_DEBUG_TRACE             1
+#endif
+
+#if (CFG_DEBUG_TRACE != 0)
+#undef CFG_LPM_SUPPORTED
+#undef CFG_DEBUGGER_SUPPORTED
+#define CFG_LPM_SUPPORTED         0
+#define CFG_DEBUGGER_SUPPORTED      1
+#endif
+/**
+ * When CFG_DEBUG_TRACE_FULL is set to 1, the trace are output with the API name, the file name and the line number
+ * When CFG_DEBUG_TRACE_LIGHT is set to 1, only the debug message is output
+ *
+ * When both are set to 0, no trace are output
+ * When both are set to 1,  CFG_DEBUG_TRACE_FULL is selected
+ */
+#define CFG_DEBUG_TRACE_LIGHT     1
+#define CFG_DEBUG_TRACE_FULL      0
+
+#if (( CFG_DEBUG_TRACE != 0 ) && ( CFG_DEBUG_TRACE_LIGHT == 0 ) && (CFG_DEBUG_TRACE_FULL == 0))
+#undef CFG_DEBUG_TRACE_FULL
+#undef CFG_DEBUG_TRACE_LIGHT
+#define CFG_DEBUG_TRACE_FULL      0
+#define CFG_DEBUG_TRACE_LIGHT     1
+#endif
+
+#if ( CFG_DEBUG_TRACE == 0 )
+#undef CFG_DEBUG_TRACE_FULL
+#undef CFG_DEBUG_TRACE_LIGHT
+#define CFG_DEBUG_TRACE_FULL      0
+#define CFG_DEBUG_TRACE_LIGHT     0
+#endif
+
+/**
+ * When not set, the traces is looping on sending the trace over UART
+ */
+#define DBG_TRACE_USE_CIRCULAR_QUEUE 1
+
+/**
+ * max buffer Size to queue data traces and max data trace allowed.
+ * Only Used if DBG_TRACE_USE_CIRCULAR_QUEUE is defined
+ */
+#define DBG_TRACE_MSG_QUEUE_SIZE 4096
+#define MAX_DBG_TRACE_MSG_SIZE 1024
+
+/******************************************************************************
+ * Scheduler
+ ******************************************************************************/
+
+/**
+ * These are the lists of task id registered to the scheduler
+ * Each task id shall be in the range [0:31]
+ * This mechanism allows to implement a generic code in the API TL_BLE_HCI_StatusNot() to comply with
+ * the requirement that a HCI/ACI command shall never be sent if there is already one pending
+ */
+
+/**< Add in that list all tasks that may send a ACI/HCI command */
+typedef enum
+{
+    CFG_TASK_HCI_ASYNCH_EVT_ID,
+
+    CFG_LAST_TASK_ID_WITH_HCICMD,                                               /**< Shall be LAST in the list */
+} CFG_Task_Id_With_HCI_Cmd_t;
+
+/**< Add in that list all tasks that never send a ACI/HCI command */
+typedef enum
+{
+    CFG_FIRST_TASK_ID_WITH_NO_HCICMD = CFG_LAST_TASK_ID_WITH_HCICMD - 1,        /**< Shall be FIRST in the list */
+
+    CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID,
+
+    CFG_LAST_TASK_ID_WITHO_NO_HCICMD                                            /**< Shall be LAST in the list */
+} CFG_Task_Id_With_NO_HCI_Cmd_t;
+#define CFG_TASK_NBR    CFG_LAST_TASK_ID_WITHO_NO_HCICMD
+
+/**
+ * This is the list of priority required by the application
+ * Each Id shall be in the range 0..31
+ */
+typedef enum
+{
+    CFG_SCH_PRIO_0,
+    CFG_PRIO_NBR,
+} CFG_SCH_Prio_Id_t;
+
+/**
+ * This is a bit mapping over 32bits listing all events id supported in the application
+ */
+typedef enum
+{
+    CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID,
+    CFG_IDLEEVT_SYSTEM_HCI_CMD_EVT_RSP_ID,
+} CFG_IdleEvt_Id_t;
+
+/******************************************************************************
+ * LOW POWER
+ ******************************************************************************/
+/**
+ * Supported requester to the MCU Low Power Manager - can be increased up  to 32
+ * It lits a bit mapping of all user of the Low Power Manager
+ */
+typedef enum
+{
+    CFG_LPM_APP,
+    CFG_LPM_APP_BLE,
+  /* USER CODE BEGIN CFG_LPM_Id_t */
+
+  /* USER CODE END CFG_LPM_Id_t */
+} CFG_LPM_Id_t;
+
+/******************************************************************************
+ * OTP manager
+ ******************************************************************************/
+#define CFG_OTP_BASE_ADDRESS    OTP_AREA_BASE
+
+#define CFG_OTP_END_ADRESS      OTP_AREA_END_ADDR
+
+#endif /*__APP_CONFIG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/app_debug.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/app_debug.h
new file mode 100644
index 000000000..13485c16b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/app_debug.h
@@ -0,0 +1,45 @@
+
+/**
+  ******************************************************************************
+  * @file    app_debug.h
+  * @author  MCD Application Team
+  * @brief   Interface to support debug in the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+  /* Exported types ------------------------------------------------------------*/
+  /* Exported constants --------------------------------------------------------*/
+  /* External variables --------------------------------------------------------*/
+  /* Exported macros -----------------------------------------------------------*/
+  /* Exported functions ------------------------------------------------------- */
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/app_entry.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/app_entry.h
new file mode 100644
index 000000000..89d350648
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/app_entry.h
@@ -0,0 +1,44 @@
+
+/**
+  ******************************************************************************
+  * @file    app_entry.h
+  * @author  MCD Application Team
+  * @brief   Interface to the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_ENTRY_H
+#define __APP_ENTRY_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+  /* Exported types ------------------------------------------------------------*/
+  /* Exported constants --------------------------------------------------------*/
+  /* External variables --------------------------------------------------------*/
+  /* Exported macros -----------------------------------------------------------*/
+  /* Exported functions ------------------------------------------------------- */
+  void APPE_Init( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__APP_ENTRY_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/hw_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/hw_conf.h
new file mode 100644
index 000000000..078755183
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/hw_conf.h
@@ -0,0 +1,246 @@
+/**
+ ******************************************************************************
+ * @file    hw_conf.h
+ * @author  MCD Application Team
+ * @brief   Configuration of hardware interface
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HW_CONF_H
+#define __HW_CONF_H
+
+/******************************************************************************
+* Semaphores
+* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
+*****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
+/* Index of the semaphore used to manage the entry Stop Mode procedure */
+#define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
+
+/* Index of the semaphore used to access the RCC */
+#define CFG_HW_RCC_SEMID                                        3
+
+/* Index of the semaphore used to access the FLASH */
+#define CFG_HW_FLASH_SEMID                                      2
+
+/* Index of the semaphore used to access the PKA */
+#define CFG_HW_PKA_SEMID                                        1
+
+/* Index of the semaphore used to access the RNG */
+#define CFG_HW_RNG_SEMID                                        0
+
+/******************************************************************************
+ * HW TIMER SERVER
+ *****************************************************************************/
+/**
+ * The user may define the maximum number of virtual timers supported.
+ * It shall not exceed 255
+ */
+#define CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER  6
+
+/**
+ * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
+ * wakeup timer.
+ * This setting is the preemptpriority part of the NVIC.
+ */
+#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO   3
+
+/**
+ * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
+ * wakeup timer.
+ * This setting is the subpriority part of the NVIC. It does not exist on all processors. When it is not supported
+ * on the CPU, the setting is ignored
+ */
+#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO   0
+
+/**
+ *  Define a critical section in the Timer server
+ *  The Timer server does not support the API to be nested
+ *  The  Application shall either:
+ *    a) Ensure this will never happen
+ *    b) Define the critical section
+ *  The default implementations is masking all interrupts using the PRIMASK bit
+ *  The TimerServer driver uses critical sections to avoid context corruption. This is achieved with the macro
+ *  TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION. When CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION is set
+ *  to 1, all STM32 interrupts are masked with the PRIMASK bit of the CortexM CPU. It is possible to use the BASEPRI
+ *  register of the CortexM CPU to keep allowed some interrupts with high priority. In that case, the user shall
+ *  re-implement TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION and shall make sure that no TimerServer
+ *  API are called when the TIMER critical section is entered
+ */
+#define CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION   1
+
+/**
+ * This value shall reflect the maximum delay there could be in the application between the time the RTC interrupt
+ * is generated by the Hardware and the time when the  RTC interrupt handler is called. This time is measured in
+ * number of RTCCLK ticks.
+ * A relaxed timing would be 10ms
+ * When the value is too short, the timerserver will not be able to count properly and all timeout may be random.
+ * When the value is too long, the device may wake up more often than the most optimal configuration. However, the
+ * impact on power consumption would be marginal (unless the value selected is extremely too long). It is strongly
+ * recommended to select a value large enough to make sure it is not too short to ensure reliability of the system
+ * as this will have marginal impact on low power mode
+ */
+#define CFG_HW_TS_RTC_HANDLER_MAX_DELAY ( 10 * (LSI_VALUE/1000) )
+
+/**
+ * Interrupt ID in the NVIC of the RTC Wakeup interrupt handler
+ * It shall be type of IRQn_Type
+ */
+#define CFG_HW_TS_RTC_WAKEUP_HANDLER_ID  RTC_WKUP_IRQn
+
+/******************************************************************************
+ * HW UART
+ *****************************************************************************/
+#define CFG_HW_LPUART1_ENABLED                 0
+#define CFG_HW_LPUART1_DMA_TX_SUPPORTED        0
+
+#define CFG_HW_USART1_ENABLED                  1
+#define CFG_HW_USART1_DMA_TX_SUPPORTED         1
+
+/**
+ * LPUART1
+ */
+#define CFG_HW_LPUART1_PREEMPTPRIORITY         0x0F
+#define CFG_HW_LPUART1_SUBPRIORITY             0
+
+/** < The application shall check the selected source clock is enable */
+#define CFG_HW_LPUART1_SOURCE_CLOCK             RCC_LPUART1CLKSOURCE_SYSCLK
+
+#define CFG_HW_LPUART1_BAUDRATE                115200
+#define CFG_HW_LPUART1_WORDLENGTH              UART_WORDLENGTH_8B
+#define CFG_HW_LPUART1_STOPBITS                UART_STOPBITS_1
+#define CFG_HW_LPUART1_PARITY                  UART_PARITY_NONE
+#define CFG_HW_LPUART1_HWFLOWCTL               UART_HWCONTROL_NONE
+#define CFG_HW_LPUART1_MODE                    UART_MODE_TX_RX
+#define CFG_HW_LPUART1_ADVFEATUREINIT          UART_ADVFEATURE_NO_INIT
+#define CFG_HW_LPUART1_OVERSAMPLING            UART_OVERSAMPLING_8
+
+#define CFG_HW_LPUART1_TX_PORT_CLK_ENABLE      __HAL_RCC_GPIOA_CLK_ENABLE
+#define CFG_HW_LPUART1_TX_PORT                 GPIOA
+#define CFG_HW_LPUART1_TX_PIN                  GPIO_PIN_2
+#define CFG_HW_LPUART1_TX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_LPUART1_TX_PULL                 GPIO_NOPULL
+#define CFG_HW_LPUART1_TX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_LPUART1_TX_ALTERNATE            GPIO_AF8_LPUART1
+
+#define CFG_HW_LPUART1_RX_PORT_CLK_ENABLE      __HAL_RCC_GPIOA_CLK_ENABLE
+#define CFG_HW_LPUART1_RX_PORT                 GPIOA
+#define CFG_HW_LPUART1_RX_PIN                  GPIO_PIN_3
+#define CFG_HW_LPUART1_RX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_LPUART1_RX_PULL                 GPIO_NOPULL
+#define CFG_HW_LPUART1_RX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_LPUART1_RX_ALTERNATE            GPIO_AF8_LPUART1
+
+#define CFG_HW_LPUART1_CTS_PORT_CLK_ENABLE     __HAL_RCC_GPIOA_CLK_ENABLE
+#define CFG_HW_LPUART1_CTS_PORT                GPIOA
+#define CFG_HW_LPUART1_CTS_PIN                 GPIO_PIN_6
+#define CFG_HW_LPUART1_CTS_MODE                GPIO_MODE_AF_PP
+#define CFG_HW_LPUART1_CTS_PULL                GPIO_PULLDOWN
+#define CFG_HW_LPUART1_CTS_SPEED               GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_LPUART1_CTS_ALTERNATE           GPIO_AF8_LPUART1
+
+#define CFG_HW_LPUART1_DMA_TX_PREEMPTPRIORITY  0x0F
+#define CFG_HW_LPUART1_DMA_TX_SUBPRIORITY      0
+
+#define CFG_HW_LPUART1_DMAMUX_CLK_ENABLE       __HAL_RCC_DMAMUX1_CLK_ENABLE
+#define CFG_HW_LPUART1_DMA_CLK_ENABLE          __HAL_RCC_DMA1_CLK_ENABLE
+#define CFG_HW_LPUART1_TX_DMA_REQ              DMA_REQUEST_LPUART1_TX
+#define CFG_HW_LPUART1_TX_DMA_CHANNEL          DMA1_Channel4
+#define CFG_HW_LPUART1_TX_DMA_IRQn             DMA1_Channel4_IRQn
+#define CFG_HW_LPUART1_DMA_TX_IRQHandler       DMA1_Channel4_IRQHandler
+
+/**
+ * UART1
+ */
+#define CFG_HW_USART1_PREEMPTPRIORITY         0x0F
+#define CFG_HW_USART1_SUBPRIORITY             0
+
+/** < The application shall check the selected source clock is enable */
+#define CFG_HW_USART1_SOURCE_CLOCK              RCC_USART1CLKSOURCE_SYSCLK
+
+#define CFG_HW_USART1_BAUDRATE                115200
+#define CFG_HW_USART1_WORDLENGTH              UART_WORDLENGTH_8B
+#define CFG_HW_USART1_STOPBITS                UART_STOPBITS_1
+#define CFG_HW_USART1_PARITY                  UART_PARITY_NONE
+#define CFG_HW_USART1_HWFLOWCTL               UART_HWCONTROL_NONE
+#define CFG_HW_USART1_MODE                    UART_MODE_TX_RX
+#define CFG_HW_USART1_ADVFEATUREINIT          UART_ADVFEATURE_NO_INIT
+#define CFG_HW_USART1_OVERSAMPLING            UART_OVERSAMPLING_8
+
+#define CFG_HW_USART1_TX_PORT_CLK_ENABLE      __HAL_RCC_GPIOB_CLK_ENABLE
+#define CFG_HW_USART1_TX_PORT                 GPIOB
+#define CFG_HW_USART1_TX_PIN                  GPIO_PIN_6
+#define CFG_HW_USART1_TX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_USART1_TX_PULL                 GPIO_NOPULL
+#define CFG_HW_USART1_TX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_TX_ALTERNATE            GPIO_AF7_USART1
+
+#define CFG_HW_USART1_RX_PORT_CLK_ENABLE      __HAL_RCC_GPIOB_CLK_ENABLE
+#define CFG_HW_USART1_RX_PORT                 GPIOB
+#define CFG_HW_USART1_RX_PIN                  GPIO_PIN_7
+#define CFG_HW_USART1_RX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_USART1_RX_PULL                 GPIO_NOPULL
+#define CFG_HW_USART1_RX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_RX_ALTERNATE            GPIO_AF7_USART1
+
+#define CFG_HW_USART1_CTS_PORT_CLK_ENABLE     __HAL_RCC_GPIOA_CLK_ENABLE
+#define CFG_HW_USART1_CTS_PORT                GPIOA
+#define CFG_HW_USART1_CTS_PIN                 GPIO_PIN_11
+#define CFG_HW_USART1_CTS_MODE                GPIO_MODE_AF_PP
+#define CFG_HW_USART1_CTS_PULL                GPIO_PULLDOWN
+#define CFG_HW_USART1_CTS_SPEED               GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_CTS_ALTERNATE           GPIO_AF7_USART1
+
+#define CFG_HW_USART1_DMA_TX_PREEMPTPRIORITY  0x0F
+#define CFG_HW_USART1_DMA_TX_SUBPRIORITY      0
+
+#define CFG_HW_USART1_DMAMUX_CLK_ENABLE       __HAL_RCC_DMAMUX1_CLK_ENABLE
+#define CFG_HW_USART1_DMA_CLK_ENABLE          __HAL_RCC_DMA2_CLK_ENABLE
+#define CFG_HW_USART1_TX_DMA_REQ			  DMA_REQUEST_USART1_TX
+#define CFG_HW_USART1_TX_DMA_CHANNEL          DMA2_Channel4
+#define CFG_HW_USART1_TX_DMA_IRQn             DMA2_Channel4_IRQn
+#define CFG_HW_USART1_DMA_TX_IRQHandler       DMA2_Channel4_IRQHandler
+
+#endif /*__HW_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/hw_if.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/hw_if.h
new file mode 100644
index 000000000..5a15665ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/hw_if.h
@@ -0,0 +1,254 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    hw_if.h
+  * @author  MCD Application Team
+  * @brief   Hardware Interface
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef HW_IF_H
+#define HW_IF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_ipcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_hsem.h"
+#include "stm32wbxx_ll_gpio.h"
+#include "stm32wbxx_ll_rtc.h"
+
+#ifdef  USE_STM32WBXX_USB_DONGLE
+#include "stm32wbxx_usb_dongle.h"
+#endif
+#ifdef  USE_STM32WBXX_NUCLEO
+  #ifdef STM32WB35xx
+  #include "nucleo_wb35ce.h"
+  #else
+  #include "stm32wbxx_nucleo.h"
+  #endif
+#endif
+#ifdef  USE_X_NUCLEO_EPD
+#include "x_nucleo_epd.h"
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /******************************************************************************
+   * HW UART
+   ******************************************************************************/
+  typedef enum
+  {
+    hw_uart1,
+    hw_uart2,
+    hw_lpuart1,
+  } hw_uart_id_t;
+
+  typedef enum
+  {
+    hw_uart_ok,
+    hw_uart_error,
+    hw_uart_busy,
+    hw_uart_to,
+  } hw_status_t;
+
+  void HW_UART_Init(hw_uart_id_t hw_uart_id);
+  void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *pData, uint16_t Size, void (*Callback)(void));
+  void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *pData, uint16_t Size,  void (*Callback)(void));
+  hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout);
+  hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*Callback)(void));
+  void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id);
+  void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id);
+
+  /******************************************************************************
+   * HW TimerServer
+   ******************************************************************************/
+  /* Exported types ------------------------------------------------------------*/
+  /**
+   * This setting is used when standby mode is supported.
+   * hw_ts_InitMode_Limited should be used when the device restarts from Standby Mode. In that case, the Timer Server does
+   * not re-initialized its context. Only the Hardware register which content has been lost is reconfigured
+   * Otherwise, hw_ts_InitMode_Full should be requested (Start from Power ON) and everything is re-initialized.
+   */
+  typedef enum
+  {
+    hw_ts_InitMode_Full,
+    hw_ts_InitMode_Limited,
+  } HW_TS_InitMode_t;
+
+  /**
+   * When a Timer is created as a SingleShot timer, it is not automatically restarted when the timeout occurs. However,
+   * the timer is kept reserved in the list and could be restarted at anytime with HW_TS_Start()
+   *
+   * When a Timer is created as a Repeated timer, it is automatically restarted when the timeout occurs.
+   */
+  typedef enum
+  {
+    hw_ts_SingleShot,
+    hw_ts_Repeated
+  } HW_TS_Mode_t;
+
+  /**
+   * hw_ts_Successful is returned when a Timer has been successfully created with HW_TS_Create(). Otherwise, hw_ts_Failed
+   * is returned. When hw_ts_Failed is returned, that means there are not enough free slots in the list to create a
+   * Timer. In that case, CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER should be increased
+   */
+  typedef enum
+  {
+    hw_ts_Successful,
+    hw_ts_Failed,
+  }HW_TS_ReturnStatus_t;
+
+  typedef void (*HW_TS_pTimerCb_t)(void);
+
+  /**
+   * @brief  Initialize the timer server
+   *         This API shall be called by the application before any timer is requested to the timer server. It
+   *         configures the RTC module to be connected to the LSI input clock.
+   *
+   * @param  TimerInitMode: When the device restarts from Standby, it should request hw_ts_InitMode_Limited so that the
+   *         Timer context is not re-initialized. Otherwise, hw_ts_InitMode_Full should be requested
+   * @param  hrtc: RTC Handle
+   * @retval None
+   */
+  void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *hrtc);
+
+  /**
+   * @brief  Interface to create a virtual timer
+   *         The user shall call this API to create a timer. Once created, the timer is reserved to the module until it
+   *         has been deleted. When creating a timer, the user shall specify the mode (single shot or repeated), the
+   *         callback to be notified when the timer expires and a module ID to identify in the timer interrupt handler
+   *         which module is concerned. In return, the user gets a timer ID to handle it.
+   *
+   * @param  TimerProcessID:  This is an identifier provided by the user and returned in the callback to allow
+   *                          identification of the requester
+   * @param  pTimerId: Timer Id returned to the user to request operation (start, stop, delete)
+   * @param  TimerMode: Mode of the virtual timer (Single shot or repeated)
+   * @param  pTimerCallBack: Callback when the virtual timer expires
+   * @retval HW_TS_ReturnStatus_t: Return whether the creation is sucessfull or not
+   */
+  HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pTimerCallBack);
+
+  /**
+   * @brief  Stop a virtual timer
+   *         This API may be used to stop a running timer. A timer which is stopped is move to the pending state.
+   *         A pending timer may be restarted at any time with a different timeout value but the mode cannot be changed.
+   *         Nothing is done when it is called to stop a timer which has been already stopped
+   *
+   * @param  TimerID:  Id of the timer to stop
+   * @retval None
+   */
+  void HW_TS_Stop(uint8_t TimerID);
+
+  /**
+   * @brief  Start a virtual timer
+   *         This API shall be used to start a timer. The timeout value is specified and may be different each time.
+   *         When the timer is in the single shot mode, it will move to the pending state when it expires. The user may
+   *         restart it at any time with a different timeout value. When the timer is in the repeated mode, it always
+   *         stay in the running state. When the timer expires, it will be restarted with the same timeout value.
+   *         This API shall not be called on a running timer.
+   *
+   * @param  TimerID:  The ID Id of the timer to start
+   * @param  timeout_ticks: Number of ticks of the virtual timer (Maximum value is (0xFFFFFFFF-0xFFFF = 0xFFFF0000)
+   * @retval None
+   */
+  void HW_TS_Start(uint8_t TimerID, uint32_t timeout_ticks);
+
+  /**
+   * @brief  Delete a virtual timer from the list
+   *         This API should be used when a timer is not needed anymore by the user. A deleted timer is removed from
+   *         the timer list managed by the timer server. It cannot be restarted again. The user has to go with the
+   *         creation of a new timer if required and may get a different timer id
+   *
+   * @param  TimerID:  The ID of the timer to remove from the list
+   * @retval None
+   */
+  void HW_TS_Delete(uint8_t TimerID);
+
+  /**
+   * @brief  Schedule the timer list on the timer interrupt handler
+   *         This interrupt handler shall be called by the application in the RTC interrupt handler. This handler takes
+   *         care of clearing all status flag required in the RTC and EXTI peripherals
+   *
+   * @param  None
+   * @retval None
+   */
+  void HW_TS_RTC_Wakeup_Handler(void);
+
+  /**
+   * @brief  Return the number of ticks to count before the interrupt
+   *         This API returns the number of ticks left to be counted before an interrupt is generated by the
+   *         Timer Server. This API may be used by the application for power management optimization. When the system
+   *         enters low power mode, the mode selection is a tradeoff between the wakeup time where the CPU is running
+   *         and the time while the CPU will be kept in low power mode before next wakeup. The deeper is the
+   *         low power mode used, the longer is the wakeup time. The low power mode management considering wakeup time
+   *         versus time in low power mode is implementation specific
+   *         When the timer is disabled (No timer in the list), it returns 0xFFFF
+   *
+   * @param  None
+   * @retval The number of ticks left to count
+   */
+  uint16_t HW_TS_RTC_ReadLeftTicksToCount(void);
+
+  /**
+   * @brief  Notify the application that a registered timer has expired
+   *         This API shall be implemented by the user application.
+   *         This API notifies the application that a timer expires. This API is running in the RTC Wakeup interrupt
+   *         context. The application may implement an Operating System to change the context priority where the timer
+   *         callback may be handled. This API provides the module ID to identify which module is concerned and to allow
+   *         sending the information to the correct task
+   *
+   * @param  TimerProcessID: The TimerProcessId associated with the timer when it has been created
+   * @param  TimerID: The TimerID of the expired timer
+   * @param  pTimerCallBack: The Callback associated with the timer when it has been created
+   * @retval None
+   */
+  void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack);
+
+  /**
+   * @brief  Notify the application that the wakeupcounter has been updated
+   *         This API should be implemented by the user application
+   *         This API notifies the application that the counter has been updated. This is expected to be used along
+   *         with the HW_TS_RTC_ReadLeftTicksToCount () API. It could be that the counter has been updated since the
+   *         last call of HW_TS_RTC_ReadLeftTicksToCount () and before entering low power mode. This notification
+   *         provides a way to the application to solve that race condition to reevaluate the counter value before
+   *         entering low power mode
+   *
+   * @param  None
+   * @retval None
+   */
+  void HW_TS_RTC_CountUpdated_AppNot(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*HW_IF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/main.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/main.h
new file mode 100644
index 000000000..49d02b260
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/main.h
@@ -0,0 +1,74 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#ifdef STM32WB35xx
+#include "nucleo_wb35ce.h"
+#else
+#include "stm32wbxx_nucleo.h"
+#endif
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/stm32_lpm_if.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/stm32_lpm_if.h
new file mode 100644
index 000000000..d8e67947f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/stm32_lpm_if.h
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+******************************************************************************
+* @file    stm32_lpm_if.h
+* @brief   Header for stm32_lpm_if.c module (device specific LP management)
+******************************************************************************
+* @attention
+*
+* 
    © Copyright (c) 2019 STMicroelectronics. 
+* All rights reserved.
    
+*
+* This software component is licensed by ST under BSD 3-Clause license,
+* the "License"; You may not use this file except in compliance with the 
+* License. You may obtain a copy of the License at:
+*                        opensource.org/licenses/BSD-3-Clause
+*
+******************************************************************************
+*/
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_LPM_IF_H
+#define __STM32_LPM_IF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/**
+  * @brief Enters Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_EnterOffMode( void );
+/**
+  * @brief Exits Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_ExitOffMode( void );
+
+/**
+  * @brief Enters Low Power Stop Mode
+  * @note ARM exists the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterStopMode( void );
+/**
+  * @brief Exits Low Power Stop Mode
+  * @note Enable the pll at 32MHz
+  * @param none
+  * @retval none
+  */
+void PWR_ExitStopMode( void );
+
+/**
+  * @brief Enters Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterSleepMode( void );
+
+/**
+  * @brief Exits Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_ExitSleepMode( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32_LPM_IF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..ca4942528
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,355 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_IPCC_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LCD_MODULE_ENABLED
+#define HAL_LPTIM_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_PKA_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_QSPI_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_TSC_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100UL)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  (32000UL)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  (32000UL)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    (48000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)(1<<__NVIC_PRIO_BITS) - 1) /*!< tick interrupt priority (lowest by default) */
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              0U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   1U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..877423276
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/stm32wbxx_it.h
@@ -0,0 +1,62 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+void PUSH_BUTTON_SW1_EXTI_IRQHandler(void);
+void PUSH_BUTTON_SW2_EXTI_IRQHandler(void);
+void PUSH_BUTTON_SW3_EXTI_IRQHandler(void);
+void USART1_IRQHandler(void);
+void CFG_HW_USART1_DMA_TX_IRQHandler( void );
+void LPUART1_IRQHandler(void);
+void CFG_HW_LPUART1_DMA_TX_IRQHandler( void );
+void RTC_WKUP_IRQHandler(void);
+void IPCC_C1_TX_IRQHandler(void);
+void IPCC_C1_RX_IRQHandler(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/utilities_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/utilities_conf.h
new file mode 100644
index 000000000..4dde3509a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/utilities_conf.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : utilities_conf.h
+  * Description        : Configuration file for STM32 Utilities.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef UTILITIES_CONF_H
+#define UTILITIES_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "cmsis_compiler.h"
+#include "string.h"
+
+/******************************************************************************
+ * common
+ ******************************************************************************/
+#define UTILS_ENTER_CRITICAL_SECTION( )   uint32_t primask_bit = __get_PRIMASK( );\
+                                          __disable_irq( )
+
+#define UTILS_EXIT_CRITICAL_SECTION( )          __set_PRIMASK( primask_bit )
+
+#define UTILS_MEMSET8( dest, value, size )      memset( dest, value, size);
+
+/******************************************************************************
+ * tiny low power manager
+ * (any macro that does not need to be modified can be removed)
+ ******************************************************************************/
+#define UTIL_LPM_INIT_CRITICAL_SECTION( )
+#define UTIL_LPM_ENTER_CRITICAL_SECTION( )      UTILS_ENTER_CRITICAL_SECTION( )
+#define UTIL_LPM_EXIT_CRITICAL_SECTION( )       UTILS_EXIT_CRITICAL_SECTION( )
+
+/******************************************************************************
+ * sequencer
+ * (any macro that does not need to be modified can be removed)
+ ******************************************************************************/
+#define UTIL_SEQ_INIT_CRITICAL_SECTION( )
+#define UTIL_SEQ_ENTER_CRITICAL_SECTION( )      UTILS_ENTER_CRITICAL_SECTION( )
+#define UTIL_SEQ_EXIT_CRITICAL_SECTION( )       UTILS_EXIT_CRITICAL_SECTION( )
+#define UTIL_SEQ_CONF_TASK_NBR                  (32)
+#define UTIL_SEQ_CONF_PRIO_NBR                  (2)
+#define UTIL_SEQ_MEMSET8( dest, value, size )   UTILS_MEMSET8( dest, value, size )
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*UTILITIES_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/vcp_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/vcp_conf.h
new file mode 100644
index 000000000..7280c33b9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Inc/vcp_conf.h
@@ -0,0 +1,53 @@
+/**
+ ******************************************************************************
+ * @file    vcp_conf.h
+ * @author  MCD Application Team
+ * @brief   Configuration of the vcp interface
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __VCP_CONF_H
+#define __VCP_CONF_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+#define VCP_BAUD_RATE                             (115200)
+#define VCP_TX_PATH_INTERFACE_READY_SETUP_TIME    (20*1000*1000/CFG_TS_TICK_VAL)  /** 20s   */
+#define VCP_TASK_ID                               (CFG_TASK_VCP_SEND_DATA_ID)
+#define VCP_TASK_PRIO                             (CFG_SCH_PRIO_1)
+
+#ifdef  VCP_TX_PATH_INTERFACE_READY_SETUP_TIME
+#define VCP_TIMER_PROC_ID                         (CFG_TIM_PROC_ID_ISR)
+#endif
+
+/* External variables --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__VCP_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/app_debug.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/app_debug.c
new file mode 100644
index 000000000..246173ae6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/app_debug.c
@@ -0,0 +1,349 @@
+/**
+ ******************************************************************************
+ * @file    app_debug.c
+ * @author  MCD Application Team
+ * @brief   Debug capabilities
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+  HW_UART_Init(CFG_DEBUG_TRACE_UART);
+  return;
+}
+
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/app_entry.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/app_entry.c
new file mode 100644
index 000000000..d6910316e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/app_entry.c
@@ -0,0 +1,456 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    app_entry.c
+ * @author  MCD Application Team
+ * @brief   Entry point of the Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "main.h"
+#include "app_entry.h"
+#include "app_ble.h"
+
+#include "ble.h"
+#include "tl.h"
+
+#include "stm32_seq.h"
+#include "shci.h"
+#include "shci_tl.h"
+#include "stm32_lpm.h"
+
+
+#include "app_debug.h"
+
+/* Private includes -----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+
+/* Private defines -----------------------------------------------------------*/
+#define POOL_SIZE (CFG_TLBLE_EVT_QUEUE_LENGTH*4U*DIVC(( sizeof(TL_PacketHeader_t) + TL_BLE_EVENT_FRAME_SIZE ), 4U))
+#define INFORMATION_SECTION_KEYWORD   (0xA56959A6)
+
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("VERSION") const uint32_t FW_Version = (CFG_FW_MAJOR_VERSION << 24) + (CFG_FW_MINOR_VERSION << 16) + (CFG_FW_SUBVERSION << 8)
++ (CFG_FW_BRANCH << 4) + CFG_FW_BUILD;
+PLACE_IN_SECTION("VERSION") const uint32_t keyword = INFORMATION_SECTION_KEYWORD;
+
+extern RTC_HandleTypeDef hrtc; /**< RTC handler declaration */
+
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t EvtPool[POOL_SIZE];
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static TL_CmdPacket_t SystemCmdBuffer;
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t SystemSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255U];
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t BleSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255];
+
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private functions prototypes-----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+static void SystemPower_Config( void );
+static void appe_Tl_Init( void );
+static void Led_Init( void );
+static void Button_Init( void );
+
+
+static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status );
+static void APPE_SysUserEvtRx( void * pPayload );
+static SHCI_TL_UserEventFlowStatus_t APPE_SysevtReadyProcessing( SHCI_C2_Ready_Evt_t *pReadyEvt );
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APPE_Init( void )
+{
+  SystemPower_Config(); /**< Configure the system Power Mode */
+
+  HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
+
+/* USER CODE BEGIN APPE_Init_1 */
+  APPD_Init( );
+
+  /**
+   * The Standby mode should not be entered before the initialization is over
+   * The default state of the Low Power Manager is to allow the Standby Mode so an request is needed here
+   */
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP, UTIL_LPM_DISABLE);
+
+  Led_Init();
+
+  Button_Init();
+
+/* USER CODE END APPE_Init_1 */
+
+  appe_Tl_Init();	/* Initialize all transport layers */
+
+  /**
+   * From now, the application is waiting for the ready event ( VS_HCI_C2_Ready )
+   * received on the system channel before starting the Stack
+   * This system event is received with APPE_SysUserEvtRx()
+   */
+/* USER CODE BEGIN APPE_Init_2 */
+
+/* USER CODE END APPE_Init_2 */
+   return;
+}
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+ * @brief  Configure the system for power optimization
+ *
+ * @note  This API configures the system to be ready for low power mode
+ *
+ * @param  None
+ * @retval None
+ */
+static void SystemPower_Config( void )
+{
+
+  /**
+   * Select HSI as system clock source after Wake Up from Stop mode
+   */
+  LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
+
+  /* Initialize low power manager */
+  UTIL_LPM_Init( );
+
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+  /**
+   *  Enable USB power
+   */
+  HAL_PWREx_EnableVddUSB();
+#endif
+
+  return;
+}
+
+static void appe_Tl_Init( void )
+{
+  TL_MM_Config_t tl_mm_config;
+  SHCI_TL_HciInitConf_t SHci_Tl_Init_Conf;
+
+  /**< Reference table initialization */
+  TL_Init();
+
+  /**< System channel initialization */
+  UTIL_SEQ_RegTask( 1<< CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID, UTIL_SEQ_RFU, shci_user_evt_proc );
+  SHci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&SystemCmdBuffer;
+  SHci_Tl_Init_Conf.StatusNotCallBack = APPE_SysStatusNot;
+  shci_init(APPE_SysUserEvtRx, (void*) &SHci_Tl_Init_Conf);
+
+  /**< Memory Manager channel initialization */
+  tl_mm_config.p_BleSpareEvtBuffer = BleSpareEvtBuffer;
+  tl_mm_config.p_SystemSpareEvtBuffer = SystemSpareEvtBuffer;
+  tl_mm_config.p_AsynchEvtPool = EvtPool;
+  tl_mm_config.AsynchEvtPoolSize = POOL_SIZE;
+  TL_MM_Init( &tl_mm_config );
+
+  TL_Enable();
+
+  return;
+}
+
+/* USER CODE BEGIN FD_LOCAL_FUNCTIONS */
+static void Led_Init( void )
+{
+#if (CFG_LED_SUPPORTED == 1)
+  /**
+   * Leds Initialization
+   */
+
+  BSP_LED_Init(LED_BLUE);
+  BSP_LED_Init(LED_GREEN);
+  BSP_LED_Init(LED_RED);
+
+  BSP_LED_On(LED_GREEN);
+#endif
+
+  return;
+}
+
+static void Button_Init( void )
+{
+#if (CFG_BUTTON_SUPPORTED == 1)
+  /**
+   * Button Initialization
+   */
+
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+
+#endif
+
+  return;
+}
+/* USER CODE END FD_LOCAL_FUNCTIONS */
+
+
+static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status )
+{
+  return;
+}
+
+/**
+ * The type of the payload for a system user event is tSHCI_UserEvtRxParam
+ * When the system event is both :
+ *    - a ready event (subevtcode = SHCI_SUB_EVT_CODE_READY)
+ *    - reported by the FUS (sysevt_ready_rsp == RSS_FW_RUNNING)
+ * The buffer shall not be released
+ * ( eg ((tSHCI_UserEvtRxParam*)pPayload)->status shall be set to SHCI_TL_UserEventFlow_Disable )
+ * When the status is not filled, the buffer is released by default
+ */
+static void APPE_SysUserEvtRx( void * pPayload )
+{
+  TL_AsynchEvt_t *p_sys_event;
+
+  p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload);
+
+  switch(p_sys_event->subevtcode)
+  {
+    case SHCI_SUB_EVT_CODE_READY:
+      ((tSHCI_UserEvtRxParam*)pPayload)->status = APPE_SysevtReadyProcessing( (SHCI_C2_Ready_Evt_t*)p_sys_event->payload );
+      break;
+
+    default:
+      break;
+  }
+
+  return;
+}
+
+static SHCI_TL_UserEventFlowStatus_t APPE_SysevtReadyProcessing( SHCI_C2_Ready_Evt_t *pReadyEvt )
+{
+  uint8_t fus_state_value;
+  SHCI_TL_UserEventFlowStatus_t return_value;
+
+#if ( CFG_LED_SUPPORTED != 0)
+  BSP_LED_Off(LED_BLUE);
+#endif
+
+  if(pReadyEvt->sysevt_ready_rsp == WIRELESS_FW_RUNNING)
+  {
+    return_value = SHCI_TL_UserEventFlow_Enable;
+
+    if(CFG_OTA_REBOOT_VAL_MSG == CFG_REBOOT_ON_CPU2_UPGRADE)
+    {
+      /**
+       * The wireless stack update has been completed
+       * Reboot on the firmware application
+       */
+        CFG_OTA_REBOOT_VAL_MSG = CFG_REBOOT_ON_FW_APP;
+        NVIC_SystemReset(); /* it waits until reset */
+    }
+    else
+    {
+      /**
+       * Run the Application
+       */
+
+      /* Enable CPU2 debug feature*/
+      APPD_EnableCPU2( );
+
+      UTIL_LPM_SetOffMode(1 << CFG_LPM_APP, UTIL_LPM_ENABLE);
+
+      APP_BLE_Init( );
+    }
+  }
+  else
+  {
+    /**
+     * FUS is running on CPU2
+     */
+    return_value = SHCI_TL_UserEventFlow_Disable;
+
+    /**
+     * The CPU2 firmware update procedure is starting from now
+     * There may be several device reset during CPU2 firmware upgrade
+     * The key word at the beginning of SRAM1 shall be changed CFG_REBOOT_ON_CPU2_UPGRADE
+     *
+     * Wireless Firmware upgrade:
+     * Once the upgrade is over, the CPU2 will run the wireless stack
+     * When the wireless stack is running, the SRAM1 is checked and when equal to CFG_REBOOT_ON_CPU2_UPGRADE,
+     * it means we may restart on the firmware application.
+     *
+     * FUS Firmware Upgrade:
+     * Once the upgrade is over, the CPU2 will run FUS and the FUS return the Idle state
+     * The SRAM1 is checked and when equal to CFG_REBOOT_ON_CPU2_UPGRADE,
+     * it means we may restart on the firmware application.
+     */
+    fus_state_value = SHCI_C2_FUS_GetState( NULL );
+
+    if( fus_state_value == 0xFF)
+    {
+      /**
+       * This is the first time in the life of the product the FUS is involved. After this command, it will be properly initialized
+       * Request the device to reboot to install the wireless firmware
+       */
+      NVIC_SystemReset(); /* it waits until reset */
+    }
+    else if( fus_state_value != 0)
+    {
+      /**
+       * An upgrade is on going
+       * Wait to reboot on the wireless stack
+       */
+#if ( CFG_LED_SUPPORTED != 0)
+      BSP_LED_On(LED_BLUE);
+#endif
+      while(1)
+      {
+        HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+      }
+    }
+    else
+    {
+      /**
+       * FUS is idle
+       * Request an upgrade and wait to reboot on the wireless stack
+       * The first two parameters are currently not supported by the FUS
+       */
+      if(CFG_OTA_REBOOT_VAL_MSG == CFG_REBOOT_ON_CPU2_UPGRADE)
+      {
+        /**
+         * The FUS update has been completed
+         * Reboot the CPU2 on the firmware application
+         */
+        CFG_OTA_REBOOT_VAL_MSG = CFG_REBOOT_ON_FW_APP;
+        SHCI_C2_FUS_StartWs( );
+  #if ( CFG_LED_SUPPORTED != 0)
+        BSP_LED_On(LED_BLUE);
+  #endif
+        while(1)
+        {
+          HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+        }
+      }
+      else
+      {
+        CFG_OTA_REBOOT_VAL_MSG = CFG_REBOOT_ON_CPU2_UPGRADE;
+        /**
+         * Note:
+         * If a reset occurs now, on the next reboot the FUS will be idle and a CPU2 reboot on the
+         * wireless stack will be requested because SRAM1 is set to CFG_REBOOT_ON_CPU2_UPGRADE
+         * The device is still operational but no CPU2 update has been done.
+         */
+        SHCI_C2_FUS_FwUpgrade(0,0);
+  #if ( CFG_LED_SUPPORTED != 0)
+        BSP_LED_On(LED_BLUE);
+  #endif
+        while(1)
+        {
+          HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+        }
+      }
+    }
+  }
+
+  return return_value;
+}
+
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+
+void UTIL_SEQ_Idle( void )
+{
+#if ( CFG_LPM_SUPPORTED == 1)
+  UTIL_LPM_EnterLowPower( );
+#endif
+  return;
+}
+
+/**
+  * @brief  This function is called by the scheduler each time an event
+  *         is pending.
+  *
+  * @param  evt_waited_bm : Event pending.
+  * @retval None
+  */
+void UTIL_SEQ_EvtIdle( UTIL_SEQ_bm_t task_id_bm, UTIL_SEQ_bm_t evt_waited_bm )
+{
+  UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+
+  return;
+}
+
+void shci_notify_asynch_evt(void* pdata)
+{
+  UTIL_SEQ_SetTask( 1<
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "hw_conf.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef enum
+{
+  TimerID_Free,
+  TimerID_Created,
+  TimerID_Running
+}TimerIDStatus_t;
+
+typedef enum
+{
+  SSR_Read_Requested,
+  SSR_Read_Not_Requested
+}RequestReadSSR_t;
+
+typedef enum
+{
+  WakeupTimerValue_Overpassed,
+  WakeupTimerValue_LargeEnough
+}WakeupTimerLimitation_Status_t;
+
+typedef struct
+{
+  HW_TS_pTimerCb_t  pTimerCallBack;
+  uint32_t        CounterInit;
+  uint32_t        CountLeft;
+  TimerIDStatus_t     TimerIDStatus;
+  HW_TS_Mode_t   TimerMode;
+  uint32_t        TimerProcessID;
+  uint8_t         PreviousID;
+  uint8_t         NextID;
+}TimerContext_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define SSR_FORBIDDEN_VALUE   0xFFFFFFFF
+#define TIMER_LIST_EMPTY      0xFFFF
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/**
+ * START of Section TIMERSERVER_CONTEXT
+ */
+
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile TimerContext_t aTimerContext[CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER];
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint8_t CurrentRunningTimerID;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint8_t PreviousRunningTimerID;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint32_t SSRValueOnLastSetup;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile WakeupTimerLimitation_Status_t  WakeupTimerLimitation;
+
+/**
+ * END of Section TIMERSERVER_CONTEXT
+ */
+
+static RTC_HandleTypeDef *phrtc;  /**< RTC handle */
+static uint8_t  WakeupTimerDivider;
+static uint8_t  AsynchPrescalerUserConfig;
+static uint16_t SynchPrescalerUserConfig;
+static volatile uint16_t MaxWakeupTimerSetup;
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void RestartWakeupCounter(uint16_t Value);
+static uint16_t ReturnTimeElapsed(void);
+static void RescheduleTimerList(void);
+static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR);
+static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID);
+static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID);
+static uint16_t linkTimer(uint8_t TimerID);
+static uint32_t ReadRtcSsrValue(void);
+
+__weak void HW_TS_RTC_CountUpdated_AppNot(void);
+
+/* Functions Definition ------------------------------------------------------*/
+
+/**
+ * @brief  Read the RTC_SSR value
+ *         As described in the reference manual, the RTC_SSR shall be read twice to ensure
+ *         reliability of the value
+ * @param  None
+ * @retval SSR value read
+ */
+static uint32_t ReadRtcSsrValue(void)
+{
+  uint32_t first_read;
+  uint32_t second_read;
+
+  first_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+
+  second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+
+  while(first_read != second_read)
+  {
+    first_read = second_read;
+
+    second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+  }
+
+  return second_read;
+}
+
+/**
+ * @brief  Insert a Timer in the list after the Timer ID specified
+ * @param  TimerID:   The ID of the Timer
+ * @param  RefTimerID: The ID of the Timer to be linked after
+ * @retval None
+ */
+static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID)
+{
+  uint8_t next_id;
+
+  next_id = aTimerContext[RefTimerID].NextID;
+
+  if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    aTimerContext[next_id].PreviousID = TimerID;
+  }
+  aTimerContext[TimerID].NextID = next_id;
+  aTimerContext[TimerID].PreviousID = RefTimerID ;
+  aTimerContext[RefTimerID].NextID = TimerID;
+
+  return;
+}
+
+/**
+ * @brief  Insert a Timer in the list before the ID specified
+ * @param  TimerID:   The ID of the Timer
+ * @param  RefTimerID: The ID of the Timer to be linked before
+ * @retval None
+ */
+static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID)
+{
+  uint8_t previous_id;
+
+  if(RefTimerID != CurrentRunningTimerID)
+  {
+    previous_id = aTimerContext[RefTimerID].PreviousID;
+
+    aTimerContext[previous_id].NextID = TimerID;
+    aTimerContext[TimerID].NextID = RefTimerID;
+    aTimerContext[TimerID].PreviousID = previous_id ;
+    aTimerContext[RefTimerID].PreviousID = TimerID;
+  }
+  else
+  {
+    aTimerContext[TimerID].NextID = RefTimerID;
+    aTimerContext[RefTimerID].PreviousID = TimerID;
+  }
+
+  return;
+}
+
+/**
+ * @brief  Insert a Timer in the list
+ * @param  TimerID:   The ID of the Timer
+ * @retval None
+ */
+static uint16_t linkTimer(uint8_t TimerID)
+{
+  uint32_t time_left;
+  uint16_t time_elapsed;
+  uint8_t timer_id_lookup;
+  uint8_t next_id;
+
+  if(CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    /**
+     * No timer in the list
+     */
+    PreviousRunningTimerID = CurrentRunningTimerID;
+    CurrentRunningTimerID = TimerID;
+    aTimerContext[TimerID].NextID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;
+
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+    time_elapsed = 0;
+  }
+  else
+  {
+    time_elapsed = ReturnTimeElapsed();
+
+    /**
+     * update count of the timer to be linked
+     */
+    aTimerContext[TimerID].CountLeft += time_elapsed;
+    time_left = aTimerContext[TimerID].CountLeft;
+
+    /**
+     * Search for index where the new timer shall be linked
+     */
+    if(aTimerContext[CurrentRunningTimerID].CountLeft <= time_left)
+    {
+      /**
+       * Search for the ID after the first one
+       */
+      timer_id_lookup = CurrentRunningTimerID;
+      next_id = aTimerContext[timer_id_lookup].NextID;
+      while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left))
+      {
+        timer_id_lookup = aTimerContext[timer_id_lookup].NextID;
+        next_id = aTimerContext[timer_id_lookup].NextID;
+      }
+
+      /**
+       * Link after the ID
+       */
+      LinkTimerAfter(TimerID, timer_id_lookup);
+    }
+    else
+    {
+      /**
+       * Link before the first ID
+       */
+      LinkTimerBefore(TimerID, CurrentRunningTimerID);
+      PreviousRunningTimerID = CurrentRunningTimerID;
+      CurrentRunningTimerID = TimerID;
+    }
+  }
+
+  return time_elapsed;
+}
+
+/**
+ * @brief  Remove a Timer from the list
+ * @param  TimerID:   The ID of the Timer
+ * @param  RequestReadSSR: Request to read the SSR register or not
+ * @retval None
+ */
+static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR)
+{
+  uint8_t previous_id;
+  uint8_t next_id;
+
+  if(TimerID == CurrentRunningTimerID)
+  {
+    PreviousRunningTimerID = CurrentRunningTimerID;
+    CurrentRunningTimerID = aTimerContext[TimerID].NextID;
+  }
+  else
+  {
+    previous_id = aTimerContext[TimerID].PreviousID;
+    next_id = aTimerContext[TimerID].NextID;
+
+    aTimerContext[previous_id].NextID = aTimerContext[TimerID].NextID;
+    if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+    {
+      aTimerContext[next_id].PreviousID = aTimerContext[TimerID].PreviousID;
+    }
+  }
+
+  /**
+   * Timer is out of the list
+   */
+  aTimerContext[TimerID].TimerIDStatus = TimerID_Created;
+
+  if((CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (RequestReadSSR == SSR_Read_Requested))
+  {
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+  }
+
+  return;
+}
+
+/**
+ * @brief  Return the number of ticks counted by the wakeuptimer since it has been started
+ * @note  The API is reading the SSR register to get how many ticks have been counted
+ *        since the time the timer has been started
+ * @param  None
+ * @retval Time expired in Ticks
+ */
+static uint16_t ReturnTimeElapsed(void)
+{
+  uint32_t  return_value;
+  uint32_t  wrap_counter;
+
+  if(SSRValueOnLastSetup != SSR_FORBIDDEN_VALUE)
+  {
+    return_value = ReadRtcSsrValue(); /**< Read SSR register first */
+
+    if (SSRValueOnLastSetup >= return_value)
+    {
+      return_value = SSRValueOnLastSetup - return_value;
+    }
+    else
+    {
+      wrap_counter = SynchPrescalerUserConfig - return_value;
+      return_value = SSRValueOnLastSetup + wrap_counter;
+    }
+
+    /**
+     * At this stage, ReturnValue holds the number of ticks counted by SSR
+     * Need to translate in number of ticks counted by the Wakeuptimer
+     */
+    return_value = return_value*AsynchPrescalerUserConfig;
+    return_value = return_value >> WakeupTimerDivider;
+  }
+  else
+  {
+    return_value = 0;
+  }
+
+  return (uint16_t)return_value;
+}
+
+/**
+ * @brief  Set the wakeup counter
+ * @note  The API is writing the counter value so that the value is decreased by one to cope with the fact
+ *    the interrupt is generated with 1 extra clock cycle (See RefManuel)
+ *    It assumes all condition are met to be allowed to write the wakeup counter
+ * @param  Value: Value to be written in the counter
+ * @retval None
+ */
+static void RestartWakeupCounter(uint16_t Value)
+{
+  /**
+   * The wakeuptimer has been disabled in the calling function to reduce the time to poll the WUTWF
+   * FLAG when the new value will have to be written
+   *  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);
+   */
+
+  if(Value == 0)
+  {
+    SSRValueOnLastSetup = ReadRtcSsrValue();
+
+    /**
+     * Simulate that the Timer expired
+     */
+    HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
+  }
+  else
+  {
+    if((Value > 1) ||(WakeupTimerDivider != 1))
+    {
+      Value -= 1;
+    }
+
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+    /**
+     * make sure to clear the flags after checking the WUTWF.
+     * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+     * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+     * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+     * due to the autoreload feature
+     */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+    HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);   /**<  Clear pending bit in NVIC */
+
+    MODIFY_REG(RTC->WUTR, RTC_WUTR_WUT, Value);
+
+    /**
+     * Update the value here after the WUTWF polling that may take some time
+     */
+    SSRValueOnLastSetup = ReadRtcSsrValue();
+
+    __HAL_RTC_WAKEUPTIMER_ENABLE(phrtc);    /**<  Enable the Wakeup Timer */
+
+    HW_TS_RTC_CountUpdated_AppNot();
+  }
+
+  return ;
+}
+
+/**
+ * @brief  Reschedule the list of timer
+ * @note  1) Update the count left for each timer in the list
+ *    2) Setup the wakeuptimer
+ * @param  None
+ * @retval None
+ */
+static void RescheduleTimerList(void)
+{
+  uint8_t   localTimerID;
+  uint32_t  timecountleft;
+  uint16_t  wakeup_timer_value;
+  uint16_t  time_elapsed;
+
+  /**
+   * The wakeuptimer is disabled now to reduce the time to poll the WUTWF
+   * FLAG when the new value will have to be written
+   */
+  if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+  {
+    /**
+     * Wait for the flag to be back to 0 when the wakeup timer is enabled
+     */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == SET);
+  }
+  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);   /**<  Disable the Wakeup Timer */
+
+  localTimerID = CurrentRunningTimerID;
+
+  /**
+   * Calculate what will be the value to write in the wakeuptimer
+   */
+  timecountleft = aTimerContext[localTimerID].CountLeft;
+
+  /**
+   * Read how much has been counted
+   */
+  time_elapsed = ReturnTimeElapsed();
+
+  if(timecountleft < time_elapsed )
+  {
+    /**
+     * There is no tick left to count
+     */
+    wakeup_timer_value = 0;
+    WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+  }
+  else
+  {
+    if(timecountleft > (time_elapsed + MaxWakeupTimerSetup))
+    {
+      /**
+       * The number of tick left is greater than the Wakeuptimer maximum value
+       */
+      wakeup_timer_value = MaxWakeupTimerSetup;
+
+      WakeupTimerLimitation = WakeupTimerValue_Overpassed;
+    }
+    else
+    {
+      wakeup_timer_value = timecountleft - time_elapsed;
+      WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+    }
+
+  }
+
+  /**
+   * update ticks left to be counted for each timer
+   */
+  while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    if (aTimerContext[localTimerID].CountLeft < time_elapsed)
+    {
+      aTimerContext[localTimerID].CountLeft = 0;
+    }
+    else
+    {
+      aTimerContext[localTimerID].CountLeft -= time_elapsed;
+    }
+    localTimerID = aTimerContext[localTimerID].NextID;
+  }
+
+  /**
+   * Write next count
+   */
+  RestartWakeupCounter(wakeup_timer_value);
+
+  return ;
+}
+
+/* Public functions ----------------------------------------------------------*/
+
+/**
+ * For all public interface except that may need write access to the RTC, the RTC
+ * shall be unlock at the beginning and locked at the output
+ * In order to ease maintainability, the unlock is done at the top and the lock at then end
+ * in case some new implementation is coming in the future
+ */
+
+void HW_TS_RTC_Wakeup_Handler(void)
+{
+  HW_TS_pTimerCb_t ptimer_callback;
+  uint32_t timer_process_id;
+  uint8_t local_current_running_timer_id;
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  /**
+   * Disable the Wakeup Timer
+   * This may speed up a bit the processing to wait the timer to be disabled
+   * The timer is still counting 2 RTCCLK
+   */
+  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);
+
+  local_current_running_timer_id = CurrentRunningTimerID;
+
+  if(aTimerContext[local_current_running_timer_id].TimerIDStatus == TimerID_Running)
+  {
+    ptimer_callback = aTimerContext[local_current_running_timer_id].pTimerCallBack;
+    timer_process_id = aTimerContext[local_current_running_timer_id].TimerProcessID;
+
+    /**
+     * It should be good to check whether the TimeElapsed is greater or not than the tick left to be counted
+     * However, due to the inaccuracy of the reading of the time elapsed, it may return there is 1 tick
+     * to be left whereas the count is over
+     * A more secure implementation has been done with a flag to state whereas the full count has been written
+     * in the wakeuptimer or not
+     */
+    if(WakeupTimerLimitation != WakeupTimerValue_Overpassed)
+    {
+      if(aTimerContext[local_current_running_timer_id].TimerMode == hw_ts_Repeated)
+      {
+        UnlinkTimer(local_current_running_timer_id, SSR_Read_Not_Requested);
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+        __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+        HW_TS_Start(local_current_running_timer_id, aTimerContext[local_current_running_timer_id].CounterInit);
+
+        /* Disable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+      }
+      else
+      {
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+        __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+        HW_TS_Stop(local_current_running_timer_id);
+
+        /* Disable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+      }
+
+      HW_TS_RTC_Int_AppNot(timer_process_id, local_current_running_timer_id, ptimer_callback);
+    }
+    else
+    {
+      RescheduleTimerList();
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+      __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+    }
+  }
+  else
+  {
+    /**
+     * We should never end up in this case
+     * However, if due to any bug in the timer server this is the case, the mistake may not impact the user.
+     * We could just clean the interrupt flag and get out from this unexpected interrupt
+     */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+    /**
+     * make sure to clear the flags after checking the WUTWF.
+     * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+     * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+     * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+     * due to the autoreload feature
+     */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  return;
+}
+
+void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *hrtc)
+{
+  uint8_t loop;
+  uint32_t localmaxwakeuptimersetup;
+
+  /**
+   * Get RTC handler
+   */
+  phrtc = hrtc;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
+
+  /**
+   * Readout the user config
+   */
+  WakeupTimerDivider = (4 - ((uint32_t)(READ_BIT(RTC->CR, RTC_CR_WUCKSEL))));
+
+  AsynchPrescalerUserConfig = (uint8_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_A) >> (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)) + 1;
+
+  SynchPrescalerUserConfig = (uint16_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_S)) + 1;
+
+  /**
+   *  Margin is taken to avoid wrong calculation when the wrap around is there and some
+   *  application interrupts may have delayed the reading
+   */
+  localmaxwakeuptimersetup = ((((SynchPrescalerUserConfig - 1)*AsynchPrescalerUserConfig) - CFG_HW_TS_RTC_HANDLER_MAX_DELAY) >> WakeupTimerDivider);
+
+  if(localmaxwakeuptimersetup >= 0xFFFF)
+  {
+    MaxWakeupTimerSetup = 0xFFFF;
+  }
+  else
+  {
+    MaxWakeupTimerSetup = (uint16_t)localmaxwakeuptimersetup;
+  }
+
+  /**
+   * Configure EXTI module
+   */
+  LL_EXTI_EnableRisingTrig_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+  LL_EXTI_EnableIT_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+
+  if(TimerInitMode == hw_ts_InitMode_Full)
+  {
+    WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+
+    /**
+     * Initialize the timer server
+     */
+    for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++)
+    {
+      aTimerContext[loop].TimerIDStatus = TimerID_Free;
+    }
+
+    CurrentRunningTimerID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;   /**<  Set ID to non valid value */
+
+    __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);                       /**<  Disable the Wakeup Timer */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);     /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module  */
+    HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);       /**<  Clear pending bit in NVIC  */
+    __HAL_RTC_WAKEUPTIMER_ENABLE_IT(phrtc, RTC_IT_WUT);         /**<  Enable interrupt in RTC module  */
+  }
+  else
+  {
+    if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTF) != RESET)
+    {
+      /**
+       * Simulate that the Timer expired
+       */
+      HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_SetPriority(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO);   /**<  Set NVIC priority */
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+  return;
+}
+
+HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pftimeout_handler)
+{
+  HW_TS_ReturnStatus_t localreturnstatus;
+  uint8_t loop = 0;
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  while((loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[loop].TimerIDStatus != TimerID_Free))
+  {
+    loop++;
+  }
+
+  if(loop != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    aTimerContext[loop].TimerIDStatus = TimerID_Created;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+    aTimerContext[loop].TimerProcessID = TimerProcessID;
+    aTimerContext[loop].TimerMode = TimerMode;
+    aTimerContext[loop].pTimerCallBack = pftimeout_handler;
+    *pTimerId = loop;
+
+    localreturnstatus = hw_ts_Successful;
+  }
+  else
+  {
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+    localreturnstatus = hw_ts_Failed;
+  }
+
+  return(localreturnstatus);
+}
+
+void HW_TS_Delete(uint8_t timer_id)
+{
+  HW_TS_Stop(timer_id);
+
+  aTimerContext[timer_id].TimerIDStatus = TimerID_Free; /**<  release ID */
+
+  return;
+}
+
+void HW_TS_Stop(uint8_t timer_id)
+{
+  uint8_t localcurrentrunningtimerid;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);    /**<  Disable NVIC */
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
+  {
+    UnlinkTimer(timer_id, SSR_Read_Requested);
+    localcurrentrunningtimerid = CurrentRunningTimerID;
+
+    if(localcurrentrunningtimerid == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+    {
+      /**
+       * List is empty
+       */
+
+      /**
+       * Disable the timer
+       */
+      if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+      {
+        /**
+         * Wait for the flag to be back to 0 when the wakeup timer is enabled
+         */
+        while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == SET);
+      }
+      __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);   /**<  Disable the Wakeup Timer */
+
+      while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+      /**
+       * make sure to clear the flags after checking the WUTWF.
+       * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+       * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+       * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+       * due to the autoreload feature
+       */
+      __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+      __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+      HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);   /**<  Clear pending bit in NVIC */
+    }
+    else if(PreviousRunningTimerID != localcurrentrunningtimerid)
+    {
+      RescheduleTimerList();
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+  return;
+}
+
+void HW_TS_Start(uint8_t timer_id, uint32_t timeout_ticks)
+{
+  uint16_t time_elapsed;
+  uint8_t localcurrentrunningtimerid;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+  if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
+  {
+    HW_TS_Stop( timer_id );
+  }
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);    /**<  Disable NVIC */
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  aTimerContext[timer_id].TimerIDStatus = TimerID_Running;
+
+  aTimerContext[timer_id].CountLeft = timeout_ticks;
+  aTimerContext[timer_id].CounterInit = timeout_ticks;
+
+  time_elapsed =  linkTimer(timer_id);
+
+  localcurrentrunningtimerid = CurrentRunningTimerID;
+
+  if(PreviousRunningTimerID != localcurrentrunningtimerid)
+  {
+    RescheduleTimerList();
+  }
+  else
+  {
+    aTimerContext[timer_id].CountLeft -= time_elapsed;
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+  return;
+}
+
+uint16_t HW_TS_RTC_ReadLeftTicksToCount(void)
+{
+  uint32_t primask_bit;
+  uint16_t return_value, auro_reload_value, elapsed_time_value;
+
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();                /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+
+  if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+  {
+    auro_reload_value = (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT));
+
+    elapsed_time_value = ReturnTimeElapsed();
+
+    if(auro_reload_value > elapsed_time_value)
+    {
+      return_value = auro_reload_value - elapsed_time_value;
+    }
+    else
+    {
+      return_value = 0;
+    }
+  }
+  else
+  {
+    return_value = TIMER_LIST_EMPTY;
+  }
+
+  __set_PRIMASK(primask_bit);     /**< Restore PRIMASK bit*/
+
+  return (return_value);
+}
+
+__weak void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack)
+{
+  pTimerCallBack();
+
+  return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/hw_uart.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/hw_uart.c
new file mode 100644
index 000000000..775aa241d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/hw_uart.c
@@ -0,0 +1,471 @@
+/**
+ ******************************************************************************
+ * @file    hw_uart.c
+ * @author  MCD Application Team
+ * @brief   hardware access
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "hw_conf.h"
+
+/* Macros --------------------------------------------------------------------*/
+#define HW_UART_INIT(__HANDLE__, __USART_BASE__)                                                    \
+        do{                                                                                         \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            (__HANDLE__).Init.BaudRate  = CFG_HW_##__USART_BASE__##_BAUDRATE;                       \
+            (__HANDLE__).Init.WordLength = CFG_HW_##__USART_BASE__##_WORDLENGTH;                    \
+            (__HANDLE__).Init.StopBits = CFG_HW_##__USART_BASE__##_STOPBITS;                        \
+            (__HANDLE__).Init.Parity = CFG_HW_##__USART_BASE__##_PARITY;                            \
+            (__HANDLE__).Init.HwFlowCtl = CFG_HW_##__USART_BASE__##_HWFLOWCTL;                      \
+            (__HANDLE__).Init.Mode = CFG_HW_##__USART_BASE__##_MODE;                                \
+            (__HANDLE__).Init.OverSampling = CFG_HW_##__USART_BASE__##_OVERSAMPLING;                \
+            (__HANDLE__).AdvancedInit.AdvFeatureInit = CFG_HW_##__USART_BASE__##_ADVFEATUREINIT;    \
+            HAL_UART_Init(&(__HANDLE__));                                                           \
+        } while(0)
+
+#define HW_UART_RX_IT(__HANDLE__, __USART_BASE__)                                                   \
+        do{                                                                                         \
+            HW_##__HANDLE__##RxCb = cb;                                                             \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            HAL_UART_Receive_IT(&(__HANDLE__), p_data, size);                                       \
+        } while(0)
+
+#define HW_UART_TX_IT(__HANDLE__, __USART_BASE__)                                                   \
+        do{                                                                                         \
+            HW_##__HANDLE__##TxCb = cb;                                                             \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            HAL_UART_Transmit_IT(&(__HANDLE__), p_data, size);                                      \
+        } while(0)
+
+#define HW_UART_TX(__HANDLE__, __USART_BASE__)                                                      \
+        do{                                                                                         \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            hal_status = HAL_UART_Transmit(&(__HANDLE__), p_data, size, timeout);                   \
+        } while(0)
+
+#define HW_UART_MSP_UART_INIT(__HANDLE__, __USART_BASE__)                                           \
+        do{                                                                                         \
+                                                                                                    \
+            /* Configure Tx Pin */                                                                  \
+            CFG_HW_##__USART_BASE__##_TX_PORT_CLK_ENABLE();                                         \
+                                                                                                    \
+            GPIO_InitStruct.Pin = CFG_HW_##__USART_BASE__##_TX_PIN ;                                \
+            GPIO_InitStruct.Mode = CFG_HW_##__USART_BASE__##_TX_MODE;                               \
+            GPIO_InitStruct.Pull = CFG_HW_##__USART_BASE__##_TX_PULL;                               \
+            GPIO_InitStruct.Speed = CFG_HW_##__USART_BASE__##_TX_SPEED;                             \
+            GPIO_InitStruct.Alternate = CFG_HW_##__USART_BASE__##_TX_ALTERNATE;                     \
+            HAL_GPIO_Init(CFG_HW_##__USART_BASE__##_TX_PORT, &GPIO_InitStruct);                     \
+                                                                                                    \
+                                                                                                    \
+            /* Configure Rx Pin */                                                                  \
+            CFG_HW_##__USART_BASE__##_RX_PORT_CLK_ENABLE();                                         \
+                                                                                                    \
+            GPIO_InitStruct.Pin = CFG_HW_##__USART_BASE__##_RX_PIN;                                 \
+            GPIO_InitStruct.Mode = CFG_HW_##__USART_BASE__##_RX_MODE;                               \
+            GPIO_InitStruct.Pull = CFG_HW_##__USART_BASE__##_RX_PULL;                               \
+            GPIO_InitStruct.Speed = CFG_HW_##__USART_BASE__##_RX_SPEED;                             \
+            GPIO_InitStruct.Alternate = CFG_HW_##__USART_BASE__##_RX_ALTERNATE;                     \
+            HAL_GPIO_Init(CFG_HW_##__USART_BASE__##_RX_PORT, &GPIO_InitStruct);                     \
+                                                                                                    \
+                                                                                                    \
+            /* Configure CTS Pin */                                                                 \
+            CFG_HW_##__USART_BASE__##_CTS_PORT_CLK_ENABLE();                                        \
+                                                                                                    \
+            GPIO_InitStruct.Pin = CFG_HW_##__USART_BASE__##_CTS_PIN;                                \
+            GPIO_InitStruct.Mode = CFG_HW_##__USART_BASE__##_CTS_MODE;                              \
+            GPIO_InitStruct.Pull = CFG_HW_##__USART_BASE__##_CTS_PULL;                              \
+            GPIO_InitStruct.Speed = CFG_HW_##__USART_BASE__##_CTS_SPEED;                            \
+            GPIO_InitStruct.Alternate = CFG_HW_##__USART_BASE__##_CTS_ALTERNATE;                    \
+            HAL_GPIO_Init(CFG_HW_##__USART_BASE__##_CTS_PORT, &GPIO_InitStruct);                    \
+                                                                                                    \
+            /* Set USART source clock */                                                            \
+            __HAL_RCC_##__USART_BASE__##_CONFIG(CFG_HW_##__USART_BASE__##_SOURCE_CLOCK);            \
+                                                                                                    \
+            /* Enable USART clock */                                                                \
+            __HAL_RCC_##__USART_BASE__##_CLK_ENABLE();                                              \
+                                                                                                    \
+            HAL_NVIC_SetPriority(__USART_BASE__##_IRQn, CFG_HW_##__USART_BASE__##_PREEMPTPRIORITY, CFG_HW_##__USART_BASE__##_SUBPRIORITY); \
+            HAL_NVIC_EnableIRQ(__USART_BASE__##_IRQn);                                              \
+        } while(0)
+
+#define HW_UART_MSP_TX_DMA_INIT(__HANDLE__, __USART_BASE__)                                         \
+        do{                                                                                         \
+            /* Configure the DMA handler for Transmission process */                                \
+        /* Enable DMA clock */                                                                      \
+        CFG_HW_##__USART_BASE__##_DMA_CLK_ENABLE();                                                 \
+        /* Enable DMA MUX clock */                                                                  \
+        CFG_HW_##__USART_BASE__##_DMAMUX_CLK_ENABLE();                                              \
+                                                                                                    \
+        HW_hdma_##__HANDLE__##_tx.Instance                 = CFG_HW_##__USART_BASE__##_TX_DMA_CHANNEL; \
+        HW_hdma_##__HANDLE__##_tx.Init.Request             = CFG_HW_##__USART_BASE__##_TX_DMA_REQ;  \
+        HW_hdma_##__HANDLE__##_tx.Init.Direction           = DMA_MEMORY_TO_PERIPH;                  \
+        HW_hdma_##__HANDLE__##_tx.Init.PeriphInc           = DMA_PINC_DISABLE;                      \
+        HW_hdma_##__HANDLE__##_tx.Init.MemInc              = DMA_MINC_ENABLE;                       \
+        HW_hdma_##__HANDLE__##_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;                   \
+        HW_hdma_##__HANDLE__##_tx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;                   \
+        HW_hdma_##__HANDLE__##_tx.Init.Mode                = DMA_NORMAL;                            \
+        HW_hdma_##__HANDLE__##_tx.Init.Priority            = DMA_PRIORITY_LOW;                      \
+                                                                                                    \
+        HAL_DMA_Init(&HW_hdma_##__HANDLE__##_tx);                                                   \
+                                                                                                    \
+        /* Associate the initialized DMA handle to the UART handle */                               \
+        __HAL_LINKDMA(huart, hdmatx, HW_hdma_##__HANDLE__##_tx);                                    \
+                                                                                                    \
+        /* NVIC configuration for DMA transfer complete interrupt  */                               \
+        HAL_NVIC_SetPriority(CFG_HW_##__USART_BASE__##_TX_DMA_IRQn, CFG_HW_##__USART_BASE__##_DMA_TX_PREEMPTPRIORITY, CFG_HW_##__USART_BASE__##_DMA_TX_SUBPRIORITY); \
+        HAL_NVIC_EnableIRQ(CFG_HW_##__USART_BASE__##_TX_DMA_IRQn);                                  \
+    } while(0)
+
+/* Variables ------------------------------------------------------------------*/
+#if (CFG_HW_USART1_ENABLED == 1)
+        UART_HandleTypeDef huart1 = {0};
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+    DMA_HandleTypeDef HW_hdma_huart1_tx ={0};
+#endif
+    void (*HW_huart1RxCb)(void);
+    void (*HW_huart1TxCb)(void);
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+    UART_HandleTypeDef lpuart1 = {0};
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+    DMA_HandleTypeDef HW_hdma_lpuart1_tx ={0};
+#endif
+    void (*HW_lpuart1RxCb)(void);
+    void (*HW_lpuart1TxCb)(void);
+#endif
+
+    void HW_UART_Init(hw_uart_id_t hw_uart_id)
+    {
+        switch (hw_uart_id)
+        {
+#if (CFG_HW_USART1_ENABLED == 1)
+            case hw_uart1:
+                HW_UART_INIT(huart1, USART1);
+                break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+            case hw_lpuart1:
+                HW_UART_INIT(lpuart1, LPUART1);
+                break;
+#endif
+
+            default:
+                break;
+        }
+
+        return;
+    }
+
+    void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+    {
+        switch (hw_uart_id)
+        {
+#if (CFG_HW_USART1_ENABLED == 1)
+            case hw_uart1:
+                HW_UART_RX_IT(huart1, USART1);
+                break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+            case hw_lpuart1:
+                HW_UART_RX_IT(lpuart1, LPUART1);
+                break;
+#endif
+
+            default:
+                break;
+        }
+
+        return;
+    }
+
+    void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  void (*cb)(void))
+    {
+        switch (hw_uart_id)
+        {
+#if (CFG_HW_USART1_ENABLED == 1)
+            case hw_uart1:
+                HW_UART_TX_IT(huart1, USART1);
+                break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+            case hw_lpuart1:
+                HW_UART_TX_IT(lpuart1, LPUART1);
+                break;
+#endif
+
+            default:
+                break;
+        }
+
+        return;
+    }
+
+    hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout)
+    {
+        HAL_StatusTypeDef hal_status = HAL_OK;
+        hw_status_t hw_status = hw_uart_ok;
+
+        switch (hw_uart_id)
+        {
+#if (CFG_HW_USART1_ENABLED == 1)
+            case hw_uart1:
+                HW_UART_TX(huart1, USART1);
+                break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+            case hw_lpuart1:
+                HW_UART_TX(lpuart1, LPUART1);
+                break;
+#endif
+
+            default:
+                break;
+        }
+
+        switch (hal_status)
+        {
+            case HAL_OK:
+                hw_status = hw_uart_ok;
+                break;
+
+            case HAL_ERROR:
+                hw_status = hw_uart_error;
+                break;
+
+            case HAL_BUSY:
+                hw_status = hw_uart_busy;
+                break;
+
+            case HAL_TIMEOUT:
+                hw_status = hw_uart_to;
+                break;
+
+            default:
+                break;
+        }
+
+        return hw_status;
+    }
+
+    hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+    {
+        HAL_StatusTypeDef hal_status = HAL_OK;
+        hw_status_t hw_status = hw_uart_ok;
+
+        switch (hw_uart_id)
+        {
+#if (CFG_HW_USART1_ENABLED == 1)
+            case hw_uart1:
+                HW_huart1TxCb = cb;
+                huart1.Instance = USART1;
+                hal_status = HAL_UART_Transmit_DMA(&huart1, p_data, size);
+                break;
+#endif
+
+#if (CFG_HW_USART2_ENABLED == 1)
+            case hw_uart2:
+                HW_huart2TxCb = cb;
+                huart2.Instance = USART2;
+                hal_status = HAL_UART_Transmit_DMA(&huart2, p_data, size);
+                break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+            case hw_lpuart1:
+                HW_lpuart1TxCb = cb;
+                lpuart1.Instance = LPUART1;
+                hal_status = HAL_UART_Transmit_DMA(&lpuart1, p_data, size);
+                break;
+#endif
+
+            default:
+                break;
+        }
+
+        switch (hal_status)
+        {
+            case HAL_OK:
+                hw_status = hw_uart_ok;
+                break;
+
+            case HAL_ERROR:
+                hw_status = hw_uart_error;
+                break;
+
+            case HAL_BUSY:
+                hw_status = hw_uart_busy;
+                break;
+
+            case HAL_TIMEOUT:
+                hw_status = hw_uart_to;
+                break;
+
+            default:
+                break;
+        }
+
+        return hw_status;
+    }
+
+    void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+    {
+        switch (hw_uart_id)
+        {
+#if (CFG_HW_USART1_ENABLED == 1)
+            case hw_uart1:
+                HAL_UART_IRQHandler(&huart1);
+                break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+            case hw_lpuart1:
+                HAL_UART_IRQHandler(&lpuart1);
+                break;
+#endif
+
+            default:
+                break;
+        }
+
+        return;
+    }
+
+    void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+    {
+        switch (hw_uart_id)
+        {
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+            case hw_uart1:
+                HAL_DMA_IRQHandler(huart1.hdmatx);
+                break;
+#endif
+
+#if (CFG_HW_USART2_DMA_TX_SUPPORTED == 1)
+            case hw_uart2:
+                HAL_DMA_IRQHandler(huart2.hdmatx);
+                break;
+#endif
+
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+            case hw_lpuart1:
+                HAL_DMA_IRQHandler(lpuart1.hdmatx);
+                break;
+#endif
+
+            default:
+                break;
+        }
+
+        return;
+    }
+
+    void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+    {
+#if ( (CFG_HW_USART1_ENABLED == 1) || (CFG_HW_LPUART1_ENABLED == 1) )
+        GPIO_InitTypeDef  GPIO_InitStruct = {0};
+#endif
+        switch ((uint32_t)huart->Instance)
+        {
+#if (CFG_HW_USART1_ENABLED == 1)
+            case (uint32_t)USART1:
+      HW_UART_MSP_UART_INIT( huart1, USART1 );
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+            HW_UART_MSP_TX_DMA_INIT( huart1, USART1 );
+#endif
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+            case (uint32_t)LPUART1:
+      HW_UART_MSP_UART_INIT( lpuart1, LPUART1 );
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+            HW_UART_MSP_TX_DMA_INIT( lpuart1, LPUART1 );
+#endif
+            break;
+#endif
+
+            default:
+                break;
+        }
+
+        return;
+    }
+
+    void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+    {
+        switch ((uint32_t)huart->Instance)
+        {
+#if (CFG_HW_USART1_ENABLED == 1)
+            case (uint32_t)USART1:
+                    if(HW_huart1RxCb)
+                    {
+                        HW_huart1RxCb();
+                    }
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+            case (uint32_t)LPUART1:
+                    if(HW_lpuart1RxCb)
+                    {
+                        HW_lpuart1RxCb();
+                    }
+            break;
+#endif
+
+            default:
+                break;
+        }
+
+        return;
+    }
+
+    void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+    {
+        switch ((uint32_t)huart->Instance)
+        {
+#if (CFG_HW_USART1_ENABLED == 1)
+            case (uint32_t)USART1:
+                    if(HW_huart1TxCb)
+                    {
+                        HW_huart1TxCb();
+                    }
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+            case (uint32_t)LPUART1:
+                    if(HW_lpuart1TxCb)
+                    {
+                        HW_lpuart1TxCb();
+                    }
+            break;
+#endif
+
+            default:
+                break;
+        }
+
+        return;
+    }
+
+    /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/main.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/main.c
new file mode 100644
index 000000000..feccded0d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/main.c
@@ -0,0 +1,337 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    main.c
+ * @author  MCD Application Team
+ * @brief   BLE application with BLE core
+ *
+  @verbatim
+  ==============================================================================
+                    ##### IMPORTANT NOTE #####
+  ==============================================================================
+
+  This application requests having the stm32wb5x_BLE_Stack_fw.bin binary
+  flashed on the Wireless Coprocessor.
+  If it is not the case, you need to use STM32CubeProgrammer to load the appropriate
+  binary.
+
+  All available binaries are located under following directory:
+  /Projects/STM32_Copro_Wireless_Binaries
+
+  Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+  Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the
+  detailed procedure to change the Wireless Coprocessor binary.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "app_entry.h"
+#include "stm32_lpm.h"
+#include "stm32_seq.h"
+#include "dbg_trace.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Global variables ---------------------------------------------------------*/
+RTC_HandleTypeDef hrtc = { 0 }; /**< RTC handler declaration */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void Reset_BackupDomain( void );
+static void Init_RTC( void );
+static void SystemClock_Config( void );
+static void Reset_Device( void );
+static void Reset_IPCC( void );
+static void Init_Exti( void );
+
+/* Functions Definition ------------------------------------------------------*/
+
+/**
+ * @brief  Main program
+ * @param  None
+ * @retval None
+ */
+int main( void )
+{
+  HAL_Init();
+
+  Reset_Device();
+
+  /**
+   * When the application is expected to run at higher speed, it should be better to set the correct system clock
+   * in system_stm32yyxx.c so that the initialization phase is running at max speed.
+   */
+  SystemClock_Config(); /**< Configure the system clock */
+
+  Init_Exti( );
+
+  Init_RTC();
+
+  APPE_Init( );
+
+  while(1)
+  {
+    UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+  }
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void Init_Exti( void )
+{
+  /**< Disable all wakeup interrupt on CPU1  except IPCC(36), HSEM(38) */
+  LL_EXTI_DisableIT_0_31(~0);
+  LL_EXTI_DisableIT_32_63( (~0) & (~(LL_EXTI_LINE_36 | LL_EXTI_LINE_38)) );
+
+  return;
+}
+
+static void Reset_Device( void )
+{
+#if ( CFG_HW_RESET_BY_FW == 1 )
+  Reset_BackupDomain();
+
+  Reset_IPCC();
+#endif
+
+  return;
+}
+
+static void Reset_IPCC( void )
+{
+  LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
+
+  LL_C1_IPCC_ClearFlag_CHx(
+      IPCC,
+      LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+      | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+  LL_C2_IPCC_ClearFlag_CHx(
+      IPCC,
+      LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+      | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+  LL_C1_IPCC_DisableTransmitChannel(
+      IPCC,
+      LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+      | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+  LL_C2_IPCC_DisableTransmitChannel(
+      IPCC,
+      LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+      | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+  LL_C1_IPCC_DisableReceiveChannel(
+      IPCC,
+      LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+      | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+  LL_C2_IPCC_DisableReceiveChannel(
+      IPCC,
+      LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+      | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+  return;
+}
+
+static void Reset_BackupDomain( void )
+{
+  if ((LL_RCC_IsActiveFlag_PINRST() != FALSE) && (LL_RCC_IsActiveFlag_SFTRST() == FALSE))
+  {
+    HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+    /**
+     *  Write twice the value to flush the APB-AHB bridge
+     *  This bit shall be written in the register before writing the next one
+     */
+    HAL_PWR_EnableBkUpAccess();
+
+    __HAL_RCC_BACKUPRESET_FORCE();
+    __HAL_RCC_BACKUPRESET_RELEASE();
+  }
+
+  return;
+}
+
+static void Init_RTC( void )
+{
+  HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+  /**
+   *  Write twice the value to flush the APB-AHB bridge
+   *  This bit shall be written in the register before writing the next one
+   */
+  HAL_PWR_EnableBkUpAccess();
+
+  __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); /**< Select LSI as RTC Input */
+
+  __HAL_RCC_RTC_ENABLE(); /**< Enable RTC */
+
+  hrtc.Instance = RTC; /**< Define instance */
+
+  /**
+   * Set the Asynchronous prescaler
+   */
+  hrtc.Init.AsynchPrediv = CFG_RTC_ASYNCH_PRESCALER;
+  hrtc.Init.SynchPrediv = CFG_RTC_SYNCH_PRESCALER;
+  HAL_RTC_Init(&hrtc);
+
+  /* Disable RTC registers write protection */
+  LL_RTC_DisableWriteProtection(RTC);
+
+  LL_RTC_WAKEUP_SetClock(RTC, CFG_RTC_WUCKSEL_DIVIDER);
+
+  /* Enable RTC registers write protection */
+  LL_RTC_EnableWriteProtection(RTC);
+
+  return;
+}
+
+/**
+ * @brief  Configure the system clock
+ *
+ * @note   This API configures
+ *         - The system clock source
+ *           - The AHBCLK, APBCLK dividers
+ *           - The flash latency
+ *           - The PLL settings (when required)
+ *
+ * @param  None
+ * @retval None
+ */
+void SystemClock_Config( void )
+{
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
+  RCC_CRSInitTypeDef RCC_CRSInitStruct = { 0 };
+
+  /**
+   * This prevents the CPU2 to disable the HSI48 oscillator when
+   * it does not use anymore the RNG IP
+   */
+  LL_HSEM_1StepLock( HSEM, 5 );
+
+  LL_RCC_HSI48_Enable();
+
+  while(!LL_RCC_HSI48_IsReady());
+
+  /* Select HSI48 as USB clock source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /*Configure the clock recovery system (CRS)**********************************/
+
+  /* Enable CRS Clock */
+  __HAL_RCC_CRS_CLK_ENABLE();
+
+  /* Default Synchro Signal division factor (not divided) */
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+
+  /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+
+  /* HSI48 is synchronized with USB SOF at 1KHz rate */
+  RCC_CRSInitStruct.ReloadValue = RCC_CRS_RELOADVALUE_DEFAULT;
+  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+
+  RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+
+  /* Set the TRIM[5:0] to the default value*/
+  RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+
+  /* Start automatic synchronization */
+  HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+#endif
+
+        /**
+         *  Write twice the value to flush the APB-AHB bridge to ensure the  bit is written
+         */
+        HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+        HAL_PWR_EnableBkUpAccess();
+
+  /**
+   * Select LSE clock
+   */
+  LL_RCC_LSE_Enable();
+  while(!LL_RCC_LSE_IsReady());
+
+  /**
+   * Select wakeup source of BLE RF
+   */
+  LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_LSE);
+
+  /* USER CODE BEGIN Smps */
+
+#if (CFG_USE_SMPS != 0)
+  /**
+   *  Configure and enable SMPS
+   *
+   *  The SMPS configuration is not yet supported by CubeMx
+   */
+  LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
+  LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
+  LL_PWR_SMPS_Enable();
+#endif
+
+  /* USER CODE END Smps */
+
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += HAL_GetTickFreq();
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+  {
+    /************************************************************************************
+     * ENTER SLEEP MODE
+     ***********************************************************************************/
+    LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+    /**
+     * This option is used to ensure that store operations are completed
+     */
+  #if defined ( __CC_ARM)
+    __force_stores();
+  #endif
+
+    __WFI( );
+  }
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/stm32_lpm_if.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/stm32_lpm_if.c
new file mode 100644
index 000000000..1418e0a36
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/stm32_lpm_if.c
@@ -0,0 +1,297 @@
+/* USER CODE BEGIN Header */
+/**
+ ***************************************************************************************
+  * File Name          : stm32_lpm_if.c
+  * Description        : Low layer function to enter/exit low power modes (stop, sleep).
+ ***************************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+  
+/* Includes ------------------------------------------------------------------*/  
+#include "stm32_lpm_if.h"
+#include "stm32_lpm.h"
+#include "app_conf.h"
+/* USER CODE BEGIN include */
+
+/* USER CODE END include */
+
+/* Exported variables --------------------------------------------------------*/
+const struct UTIL_LPM_Driver_s UTIL_PowerDriver = 
+{
+  PWR_EnterSleepMode,
+  PWR_ExitSleepMode,
+  
+  PWR_EnterStopMode,
+  PWR_ExitStopMode, 
+  
+  PWR_EnterOffMode,
+  PWR_ExitOffMode,
+};
+
+/* Private function prototypes -----------------------------------------------*/
+static void Switch_On_HSI( void );
+/* USER CODE BEGIN Private_Function_Prototypes */
+
+/* USER CODE END Private_Function_Prototypes */
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN Private_Typedef */
+
+/* USER CODE END Private_Typedef */
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Private_Define */
+
+/* USER CODE END Private_Define */
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Private_Macro */
+
+/* USER CODE END Private_Macro */
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN Private_Variables */
+
+/* USER CODE END Private_Variables */
+
+/* Functions Definition ------------------------------------------------------*/
+/**
+  * @brief Enters Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_EnterOffMode( void )
+{
+/* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
+  /************************************************************************************
+   * ENTER OFF MODE
+   ***********************************************************************************/
+  /*
+   * There is no risk to clear all the WUF here because in the current implementation, this API is called
+   * in critical section. If an interrupt occurs while in that critical section before that point,
+   * the flag is set and will be cleared here but the system will not enter Off Mode
+   * because an interrupt is pending in the NVIC. The ISR will be executed when moving out
+   * of this critical section
+   */
+  LL_PWR_ClearFlag_WU( );
+
+  LL_PWR_SetPowerMode( LL_PWR_MODE_STANDBY );
+
+  LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores( );
+#endif
+
+  __WFI( );
+/* USER CODE END PWR_EnterOffMode */
+}
+
+/**
+  * @brief Exits Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_ExitOffMode( void )
+{
+/* USER CODE BEGIN PWR_ExitOffMode */
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitOffMode */
+}
+
+/**
+  * @brief Enters Low Power Stop Mode
+  * @note ARM exists the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterStopMode( void )
+{
+/* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
+  /**
+   * This function is called from CRITICAL SECTION
+   */
+  while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
+
+  if ( ! LL_HSEM_1StepLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID ) )
+  {
+    if( LL_PWR_IsActiveFlag_C2DS( ) )
+    {
+      /* Release ENTRY_STOP_MODE semaphore */
+      LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
+
+      /**
+       * The switch on HSI before entering Stop Mode is required on Cut2.0
+       * It is useless from Cut2.1
+       */
+      Switch_On_HSI( );
+    }
+  }
+  else
+  {
+    /**
+     * The switch on HSI before entering Stop Mode is required on Cut2.0
+     * It is useless from Cut2.1
+     */
+    Switch_On_HSI( );
+  }
+
+  /* Release RCC semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  /************************************************************************************
+   * ENTER STOP MODE
+   ***********************************************************************************/
+  LL_PWR_SetPowerMode( LL_PWR_MODE_STOP2 );
+
+  LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores( );
+#endif
+
+  __WFI();
+/* USER CODE END PWR_EnterStopMode */
+}
+
+/**
+  * @brief Exits Low Power Stop Mode
+  * @note Enable the pll at 32MHz
+  * @param none
+  * @retval none
+  */
+void PWR_ExitStopMode( void )
+{
+/* USER CODE BEGIN PWR_ExitStopMode */
+  /**
+   * This function is called from CRITICAL SECTION
+   */
+
+  /* Release ENTRY_STOP_MODE semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
+
+  while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
+
+  if(LL_RCC_GetSysClkSource( ) == LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+    LL_RCC_HSE_Enable( );
+    while(!LL_RCC_HSE_IsReady( ));
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
+    while (LL_RCC_GetSysClkSource( ) != LL_RCC_SYS_CLKSOURCE_STATUS_HSE);
+  }
+  else
+  {
+    /**
+     * As long as the current application is fine with HSE as system clock source,
+     * there is nothing to do here
+     */
+  }
+
+  /* Release RCC semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitStopMode */
+}
+
+/**
+  * @brief Enters Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterSleepMode( void )
+{
+/* USER CODE BEGIN PWR_EnterSleepMode */
+
+  HAL_SuspendTick();
+
+  /************************************************************************************
+   * ENTER SLEEP MODE
+   ***********************************************************************************/
+  LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+
+  __WFI( );
+/* USER CODE END PWR_EnterSleepMode */
+}
+
+/**
+  * @brief Exits Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_ExitSleepMode( void )
+{
+/* USER CODE BEGIN PWR_ExitSleepMode */
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitSleepMode */
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+  * @brief Switch the system clock on HSI
+  * @param none
+  * @retval none
+  */
+static void Switch_On_HSI( void )
+{
+  LL_RCC_HSI_Enable( );
+  while(!LL_RCC_HSI_IsReady( ));
+  LL_RCC_SetSysClkSource( LL_RCC_SYS_CLKSOURCE_HSI );
+  LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSI);
+  while (LL_RCC_GetSysClkSource( ) != LL_RCC_SYS_CLKSOURCE_STATUS_HSI);
+}
+
+/* USER CODE BEGIN Private_Functions */
+
+/* USER CODE END Private_Functions */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..01979a6d2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/stm32wbxx_it.c
@@ -0,0 +1,182 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "stm32wbxx_it.h"
+   
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M4 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+ * @brief  This function handles NMI exception.
+ * @param  None
+ * @retval None
+ */
+void NMI_Handler(void)
+{
+}
+
+/**
+ * @brief  This function handles Hard Fault exception.
+ * @param  None
+ * @retval None
+ */
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+ * @brief  This function handles SVCall exception.
+ * @param  None
+ * @retval None
+ */
+void SVC_Handler(void)
+{
+}
+
+/**
+ * @brief  This function handles Debug Monitor exception.
+ * @param  None
+ * @retval None
+ */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+ * @brief  This function handles PendSVC exception.
+ * @param  None
+ * @retval None
+ */
+void PendSV_Handler(void)
+{
+}
+
+/**
+ * @brief  This function handles SysTick Handler.
+ * @param  None
+ * @retval None
+ */
+void SysTick_Handler(void)
+{
+  HAL_IncTick();
+}
+
+/********************************************************************************/
+/*                 STM32WBxx Peripherals Interrupt Handlers                     */
+/*  Add here the Interrupt Handler for the used peripheral(s), for the          */
+/*  available peripheral interrupt handler's name please refer to the startup   */
+/*  file (startup_stm32wb55xx_cm4.s).                                           */
+/********************************************************************************/
+
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW1_EXTI_IRQHandler(void)
+{ 
+}
+
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW2_EXTI_IRQHandler(void)
+{
+}
+
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW3_EXTI_IRQHandler(void)
+{
+}
+
+#if(CFG_HW_USART1_ENABLED == 1)
+void USART1_IRQHandler(void)
+{
+  HW_UART_Interrupt_Handler(hw_uart1);
+}
+#endif
+
+#if(CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+void CFG_HW_USART1_DMA_TX_IRQHandler( void )
+{
+  HW_UART_DMA_Interrupt_Handler(hw_uart1);
+}
+#endif
+
+#if(CFG_HW_LPUART1_ENABLED == 1)
+void LPUART1_IRQHandler(void)
+{
+  HW_UART_Interrupt_Handler(hw_lpuart1);
+}
+#endif
+
+#if(CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+void CFG_HW_LPUART1_DMA_TX_IRQHandler( void )
+{
+  HW_UART_DMA_Interrupt_Handler(hw_lpuart1);
+}
+#endif
+
+void RTC_WKUP_IRQHandler(void)
+{
+  HW_TS_RTC_Wakeup_Handler();
+}
+
+void IPCC_C1_TX_IRQHandler(void)
+{
+  HW_IPCC_Tx_Handler();
+
+  return;
+}
+
+void IPCC_C1_RX_IRQHandler(void)
+{
+  HW_IPCC_Rx_Handler();
+  return;
+}
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..186a015d8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/Core/Src/system_stm32wbxx.c
@@ -0,0 +1,550 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "app_common.h"
+#include "otp.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+typedef void (*fct_t)(void);
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+/*!< Vector Table base offset field. This value must be a multiple of 0x200. */
+/* #define VECT_TAB_OFFSET  0x0U*/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                        4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+  /**
+   * @}
+   */
+
+   /** @addtogroup STM32WBxx_System_Private_Functions
+    * @{
+    */
+
+/****************************/
+static void JumpFwApp( void );
+static void BootModeCheck( void );
+static void JumpSelectionOnPowerUp( void );
+
+/**
+ * Return 0 if FW App not valid
+ * Return 1 if Fw App valid
+ */
+static uint8_t  CheckFwAppValidity( void );
+
+
+static uint8_t CheckFwAppValidity( void )
+{
+  uint8_t status;
+  uint32_t magic_keyword_address;
+  uint32_t last_user_flash_address;
+
+  magic_keyword_address = *(uint32_t*)(FLASH_BASE + (CFG_APP_START_SECTOR_INDEX * 0x1000 + 0x140));
+  last_user_flash_address = (((READ_BIT(FLASH->SFR, FLASH_SFR_SFSA) >> FLASH_SFR_SFSA_Pos) << 12) + FLASH_BASE) - 4;
+  if( (magic_keyword_address < FLASH_BASE) || (magic_keyword_address > last_user_flash_address) )
+  {
+    /**
+     * The address is not valid
+     */
+    status = 0;
+  }
+  else
+  {
+    if( (*(uint32_t*)magic_keyword_address) != 0x94448A29  )
+    {
+      /**
+       * A firmware update procedure did not complete
+       */
+      status = 0;
+    }
+    else
+    {
+      /**
+       * The firmware application is available
+       */
+      status = 1;
+    }
+  }
+
+  return status;
+}
+
+/**
+ * Jump to existing FW App in flash
+ * It never returns
+ */
+static void JumpFwApp( void )
+{
+  fct_t app_reset_handler;
+
+  SCB->VTOR = FLASH_BASE + (CFG_APP_START_SECTOR_INDEX * 0x1000);
+  __set_MSP(*(uint32_t*)(FLASH_BASE + (CFG_APP_START_SECTOR_INDEX * 0x1000)));
+  app_reset_handler = (fct_t)(*(uint32_t*)(FLASH_BASE + (CFG_APP_START_SECTOR_INDEX * 0x1000) + 4));
+  app_reset_handler();
+
+  /**
+   * app_reset_handler() never returns.
+   * However, if for any reason a PUSH instruction is added at the entry of  JumpFwApp(),
+   * we need to make sure the POP instruction is not there before app_reset_handler() is called
+   * The way to ensure this is to add a dummy code after app_reset_handler() is called
+   * This prevents app_reset_handler() to be the last code in the function.
+   */
+  __WFI();
+
+
+  return;
+}
+
+/**
+ * Check the Boot mode request
+ * Depending on the result, the CPU may either jump to an existing application in the user flash
+ * or keep on running the code to start the OTA loader
+ */
+static void BootModeCheck( void )
+{
+  if(LL_RCC_IsActiveFlag_SFTRST( ) || LL_RCC_IsActiveFlag_OBLRST( ))
+  {
+    /**
+     * The SRAM1 content is kept on Software Reset.
+     * In the Ble_Ota application, the first address of the SRAM1 indicates which kind of action has been requested
+     */
+
+    /**
+     * Check Boot Mode from SRAM1
+     */
+    if((CFG_OTA_REBOOT_VAL_MSG == CFG_REBOOT_ON_FW_APP) && (CheckFwAppValidity( ) != 0))
+    {
+      /**
+       * The user has requested to start on the firmware application and it has been checked
+       * a valid application is ready
+       * Jump now on the application
+       */
+      JumpFwApp();
+    }
+    else if((CFG_OTA_REBOOT_VAL_MSG == CFG_REBOOT_ON_FW_APP) && (CheckFwAppValidity( ) == 0))
+    {
+      /**
+       * The user has requested to start on the firmware application but there is no valid application
+       * Erase all sectors specified by byte1 and byte1 in SRAM1 to download a new App.
+       */
+      CFG_OTA_REBOOT_VAL_MSG = CFG_REBOOT_ON_BLE_OTA_APP;     /* Request to reboot on BLE_Ota application */
+      CFG_OTA_START_SECTOR_IDX_VAL_MSG = CFG_APP_START_SECTOR_INDEX;
+      CFG_OTA_NBR_OF_SECTOR_VAL_MSG = 0xFF;
+    }
+    else if(CFG_OTA_REBOOT_VAL_MSG == CFG_REBOOT_ON_BLE_OTA_APP)
+    {
+      /**
+       * It has been requested to reboot on BLE_Ota application to download data
+       */
+    }
+    else if(CFG_OTA_REBOOT_VAL_MSG == CFG_REBOOT_ON_CPU2_UPGRADE)
+    {
+      /**
+       * It has been requested to reboot on BLE_Ota application to keep running the firmware upgrade process
+       *
+       */
+    }
+    else
+    {
+      /**
+       * There should be no use case to be there because the device already starts from power up
+       * and the SRAM1 is then filled with the value define by the user
+       * However, it could be that a reset occurs just after a power up and in that case, the Ble_Ota
+       * will be running but the sectors to download a new App may not be erased
+       */
+      JumpSelectionOnPowerUp( );
+    }
+  }
+  else
+  {
+    /**
+     * On Power up, the content of SRAM1 is random
+     * The only thing that could be done is to jump on either the firmware application
+     * or the Ble_Ota application
+     */
+    JumpSelectionOnPowerUp( );
+  }
+
+  /**
+   * Return to the startup file and run the Ble_Ota application
+   */
+  return;
+}
+
+static void JumpSelectionOnPowerUp( void )
+{
+  /**
+   * Check if there is a FW App
+   */
+  if(CheckFwAppValidity( ) != 0)
+  {
+    /**
+     * The SRAM1 is random
+     * Initialize SRAM1 to indicate we requested to reboot of firmware application
+     */
+    CFG_OTA_REBOOT_VAL_MSG = CFG_REBOOT_ON_FW_APP;
+
+    /**
+     * A valid application is available
+     * Jump now on the application
+     */
+    JumpFwApp();
+  }
+  else
+  {
+    /**
+     * The SRAM1 is random
+     * Initialize SRAM1 to indicate we requested to reboot of BLE_Ota application
+     */
+    CFG_OTA_REBOOT_VAL_MSG = CFG_REBOOT_ON_BLE_OTA_APP;
+
+    /**
+     * There is no valid application available
+     * Erase all sectors specified by byte1 and byte1 in SRAM1 to download a new App.
+     */
+    CFG_OTA_START_SECTOR_IDX_VAL_MSG = CFG_APP_START_SECTOR_INDEX;
+    CFG_OTA_NBR_OF_SECTOR_VAL_MSG = 0xFF;
+  }
+  return;
+}
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  OTP_ID0_t * p_otp;
+
+  BootModeCheck();
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+
+  /**
+   * Read HSE_Tuning from OTP
+   */
+  p_otp = (OTP_ID0_t *) OTP_Read(0);
+  if (p_otp)
+  {
+    LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
+  }
+
+  LL_RCC_HSE_Enable();
+
+  /**
+   * Set FLASH latency to 1WS
+   */
+  LL_FLASH_SetLatency( LL_FLASH_LATENCY_1 );
+  while( LL_FLASH_GetLatency() != LL_FLASH_LATENCY_1 );
+
+  /**
+   * Switch to HSE
+   *
+   */
+  while(!LL_RCC_HSE_IsReady());
+  LL_RCC_SetSysClkSource( LL_RCC_SYS_CLKSOURCE_HSE );
+  while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE);
+
+  /**
+   * Switch OFF MSI
+   */
+  LL_RCC_MSI_Disable();
+
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM)
+  /* program in SRAM1 */
+  SCB->VTOR = RAM1_BASE | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAM1 for CPU1 */
+#elif defined(VECT_TAB_OFFSET)
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/BLE_Ota.ewd b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/BLE_Ota.ewd
new file mode 100644
index 000000000..e4aa36a06
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/BLE_Ota.ewd
@@ -0,0 +1,1419 @@
+
+
+    3
+    
+        BLE_Ota
+        
+            ARM
+        
+        0
+        
+            C-SPY
+            2
+            
+                29
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            ARMSIM_ID
+            2
+            
+                1
+                1
+                0
+                
+                
+                
+                
+            
+        
+        
+            CADI_ID
+            2
+            
+                0
+                1
+                0
+                
+                
+                
+                
+                
+            
+        
+        
+            CMSISDAP_ID
+            2
+            
+                4
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            GDBSERVER_ID
+            2
+            
+                0
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            IJET_ID
+            2
+            
+                8
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            JLINK_ID
+            2
+            
+                16
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            LMIFTDI_ID
+            2
+            
+                2
+                1
+                0
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            PEMICRO_ID
+            2
+            
+                3
+                1
+                0
+                
+                
+                
+                
+            
+        
+        
+            STLINK_ID
+            2
+            
+                4
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            THIRDPARTY_ID
+            2
+            
+                0
+                1
+                0
+                
+                
+                
+                
+            
+        
+        
+            TIFET_ID
+            2
+            
+                1
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            XDS100_ID
+            2
+            
+                6
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            
+                $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+                0
+            
+            
+                $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+                1
+            
+            
+                $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+                0
+            
+            
+                $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+                0
+            
+            
+                $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+                0
+            
+        
+    
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/BLE_Ota.ewp b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/BLE_Ota.ewp
new file mode 100644
index 000000000..0cf99772f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/BLE_Ota.ewp
@@ -0,0 +1,1273 @@
+
+
+    3
+    
+        BLE_Ota
+        
+            ARM
+        
+        0
+        
+            General
+            3
+            
+                30
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            ICCARM
+            2
+            
+                34
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            AARM
+            2
+            
+                10
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            OBJCOPY
+            0
+            
+                1
+                1
+                0
+                
+                
+                
+                
+                
+            
+        
+        
+            CUSTOM
+            3
+            
+                
+                
+                0
+            
+        
+        
+            BICOMP
+            0
+            
+        
+        
+            BUILDACTION
+            1
+            
+                
+                
+            
+        
+        
+            ILINK
+            0
+            
+                20
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            IARCHIVE
+            0
+            
+                0
+                1
+                0
+                
+                
+                
+            
+        
+        
+            BILINK
+            0
+            
+        
+    
+    
+        Application
+        
+            Core
+            
+                $PROJ_DIR$\..\Core\Src\app_debug.c
+            
+            
+                $PROJ_DIR$\..\Core\Src\app_entry.c
+            
+            
+                $PROJ_DIR$\..\Core\Src\app_debug.c
+            
+            
+                $PROJ_DIR$\..\Core\Src\stm32_lpm_if.c
+            
+            
+                $PROJ_DIR$\..\Core\Src\hw_timerserver.c
+            
+            
+                $PROJ_DIR$\..\Core\Src\hw_uart.c
+            
+            
+                $PROJ_DIR$\..\Core\Src\main.c
+            
+            
+                $PROJ_DIR$\..\Core\Src\stm32wbxx_it.c
+            
+        
+        
+            EWARM
+            
+                $PROJ_DIR$\startup_stm32wb35xx_cm4.s
+            
+        
+        
+            STM32_WPAN
+            
+                app
+                
+                    $PROJ_DIR$\..\STM32_WPAN\App\app_ble.c
+                
+                
+                    $PROJ_DIR$\..\STM32_WPAN\App\otas_app.c
+                
+            
+            
+                target
+                
+                    $PROJ_DIR$\..\STM32_WPAN\Target\hw_ipcc.c
+                
+            
+        
+    
+    
+        Doc
+        
+            $PROJ_DIR$\..\readme.txt
+        
+    
+    
+        Drivers
+        
+            BSP
+            
+                NUCLEO-WB35CE
+                
+                    $PROJ_DIR$\..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE\nucleo_wb35ce.c
+                
+            
+        
+        
+            CMSIS
+            
+                $PROJ_DIR$\..\Core\Src\system_stm32wbxx.c
+            
+        
+        
+            STM32WBxx_HAL_Driver
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_adc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_adc_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_cortex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_gpio.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rtc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rtc_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_spi.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_spi_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_uart.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_uart_ex.c
+            
+        
+    
+    
+        Middlewares
+        
+            STM32_WPAN
+            
+                ble
+                
+                    blesvc
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\svc\Src\otas_stm.c
+                    
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\svc\Src\svc_ctl.c
+                    
+                
+                
+                    core
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_gap_aci.c
+                    
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_gatt_aci.c
+                    
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_hal_aci.c
+                    
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_hci_le.c
+                    
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_l2cap_aci.c
+                    
+                    
+                        $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\template\osal.c
+                    
+                
+            
+            
+                interface
+                
+                    patterns
+                    
+                        ble_thread
+                        
+                            shci
+                            
+                                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\shci\shci.c
+                            
+                        
+                        
+                            tl
+                            
+                                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\hci_tl.c
+                            
+                            
+                                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\shci_tl.c
+                            
+                            
+                                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\hci_tl_if.c
+                            
+                            
+                                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\shci_tl_if.c
+                            
+                            
+                                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\tl_mbox.c
+                            
+                        
+                    
+                
+            
+            
+                utilities
+                
+                    $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\dbg_trace.c
+                
+                
+                    $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\otp.c
+                
+                
+                    $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\stm_list.c
+                
+                
+                    $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\stm_queue.c
+                
+            
+        
+    
+    
+        Utilities
+        
+            $PROJ_DIR$\..\..\..\..\..\..\Utilities\lpm\tiny_lpm\stm32_lpm.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\..\..\Utilities\sequencer\stm32_seq.c
+        
+    
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/Project.eww
new file mode 100644
index 000000000..a84cfe9c7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+    
+        $WS_DIR$\BLE_Ota.ewp
+    
+    
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..8f3317a41
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/app_ble.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/app_ble.c
new file mode 100644
index 000000000..01dfeec3b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/app_ble.c
@@ -0,0 +1,555 @@
+/**
+ ******************************************************************************
+ * @file    app_ble.c
+ * @author  MCD Application Team
+ * @brief   BLE Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "dbg_trace.h"
+#include "ble.h"
+#include "tl.h"
+#include "app_ble.h"
+
+#include "stm32_seq.h"
+#include "shci.h"
+#include "stm32_lpm.h"
+#include "otp.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+#define APPBLE_GAP_DEVICE_NAME_LENGTH 7
+   
+#define BD_ADDR_SIZE_LOCAL    6
+   
+ 
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static TL_CmdPacket_t BleCmdBuffer;
+
+static const uint8_t M_bd_addr[BD_ADDR_SIZE_LOCAL] =
+    {
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x0000000000FF)),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x00000000FF00) >> 8),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x000000FF0000) >> 16),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x0000FF000000) >> 24),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x00FF00000000) >> 32),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0xFF0000000000) >> 40)
+    };
+
+static uint8_t bd_addr_udn[BD_ADDR_SIZE_LOCAL];
+
+/**
+*   Identity root key used to derive LTK and CSRK 
+*/
+static const uint8_t BLE_CFG_IR_VALUE[16] = CFG_BLE_IRK;
+
+/**
+* Encryption root key used to derive LTK and CSRK
+*/
+static const uint8_t BLE_CFG_ER_VALUE[16] = CFG_BLE_ERK;
+
+static const char local_name[] = { AD_TYPE_COMPLETE_LOCAL_NAME, 'S', 'T', 'M','_', 'O', 'T', 'A' };
+uint8_t manuf_data[14] = { 
+    sizeof(manuf_data)-1, AD_TYPE_MANUFACTURER_SPECIFIC_DATA, 
+    0x01/*SKD version */,
+    CFG_DEV_ID_OTA_FW_UPDATE /* STM32WB - OTA*/,
+    0x00 /* GROUP A Feature  */, 
+    0x00 /* GROUP A Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00, /* BLE MAC start -MSB */
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00, /* BLE MAC stop */
+};
+
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void BLE_UserEvtRx( void * pPayload );
+static void BLE_StatusNot( HCI_TL_CmdStatus_t status );
+static void Ble_Tl_Init( void );
+static void Ble_Hci_Gap_Gatt_Init(void);
+static const uint8_t* BleGetBdAddress( void );
+static void Adv_Request(void);
+static void Delete_Sectors( void );
+
+/* Functions Definition ------------------------------------------------------*/
+void APP_BLE_Init( void )
+{
+  SHCI_C2_Ble_Init_Cmd_Packet_t ble_init_cmd_packet =
+  {
+    {{0,0,0}},                          /**< Header unused */
+    {0,                                 /** pBleBufferAddress not used */
+    0,                                  /** BleBufferSize not used */
+    CFG_BLE_NUM_GATT_ATTRIBUTES,
+    CFG_BLE_NUM_GATT_SERVICES,
+    CFG_BLE_ATT_VALUE_ARRAY_SIZE,
+    CFG_BLE_NUM_LINK,
+    CFG_BLE_DATA_LENGTH_EXTENSION,
+    CFG_BLE_PREPARE_WRITE_LIST_SIZE,
+    CFG_BLE_MBLOCK_COUNT,
+    CFG_BLE_MAX_ATT_MTU,
+    CFG_BLE_SLAVE_SCA,
+    CFG_BLE_MASTER_SCA,
+    CFG_BLE_LSE_SOURCE,
+    CFG_BLE_MAX_CONN_EVENT_LENGTH,
+    CFG_BLE_HSE_STARTUP_TIME,
+    CFG_BLE_VITERBI_MODE,
+    CFG_BLE_LL_ONLY,
+    0}
+  };
+
+  /**
+   * Initialize Ble Transport Layer
+   */
+  Ble_Tl_Init( );
+
+  /**
+   * Do not allow standby in the application
+   */
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP_BLE, UTIL_LPM_DISABLE);
+
+  /**
+   * Register the hci transport layer to handle BLE User Asynchronous Events
+   */
+  UTIL_SEQ_RegTask( 1<data;
+
+  switch (event_pckt->evt)
+  {
+    case EVT_DISCONN_COMPLETE:
+    {
+      
+      Adv_Request();
+      
+    }
+    break; /* EVT_DISCONN_COMPLETE */
+
+    case EVT_LE_META_EVENT:
+      meta_evt = (evt_le_meta_event*) event_pckt->data;
+
+      switch (meta_evt->subevent)
+      {
+        case EVT_LE_CONN_COMPLETE:
+          break; /* HCI_EVT_LE_CONN_COMPLETE */
+
+        default:
+          break;
+      }
+      break; /* HCI_EVT_LE_META_EVENT */
+
+        case EVT_VENDOR:
+          blue_evt = (evt_blue_aci*) event_pckt->data;
+          switch (blue_evt->ecode)
+          {
+            case EVT_BLUE_GAP_PROCEDURE_COMPLETE:
+              break; /* EVT_BLUE_GAP_PROCEDURE_COMPLETE */
+          }
+          break; /* EVT_VENDOR */
+
+            default:
+              break;
+  }
+
+  return (SVCCTL_UserEvtFlowEnable);
+}
+
+void APP_BLE_Key_Button1_Action(void)
+{
+}
+
+void APP_BLE_Key_Button2_Action(void)
+{
+}
+
+void APP_BLE_Key_Button3_Action(void)
+{
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void Ble_Tl_Init( void )
+{
+  HCI_TL_HciInitConf_t Hci_Tl_Init_Conf;
+
+  Hci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&BleCmdBuffer;
+  Hci_Tl_Init_Conf.StatusNotCallBack = BLE_StatusNot;
+  hci_init(BLE_UserEvtRx, (void*) &Hci_Tl_Init_Conf);
+
+  return;
+}
+
+static void Ble_Hci_Gap_Gatt_Init(void){
+
+  uint8_t role;
+  uint16_t gap_service_handle, gap_dev_name_char_handle, gap_appearance_char_handle;
+  const uint8_t *bd_addr;
+  uint32_t srd_bd_addr[2];
+  uint16_t appearance[1] = { BLE_CFG_GAP_APPEARANCE }; 
+
+  /**
+   * Initialize HCI layer
+   */
+  /*HCI Reset to synchronise BLE Stack*/
+  hci_reset();
+
+  /**
+   * Write the BD Address
+   */
+
+  bd_addr = BleGetBdAddress();
+  aci_hal_write_config_data(CONFIG_DATA_PUBADDR_OFFSET,
+                            CONFIG_DATA_PUBADDR_LEN,
+                            (uint8_t*) bd_addr);
+
+
+  
+  /**
+   * Static random Address
+   * The two upper bits shall be set to 1
+   * The lowest 32bits is read from the UDN to differentiate between devices
+   * The RNG may be used to provide a random number on each power on
+   */
+  srd_bd_addr[1] =  0x0000ED6E;
+  srd_bd_addr[0] =  LL_FLASH_GetUDN( );
+  aci_hal_write_config_data( CONFIG_DATA_RANDOM_ADDRESS_OFFSET, CONFIG_DATA_RANDOM_ADDRESS_LEN, (uint8_t*)srd_bd_addr );
+
+  /**
+   * Write Identity root key used to derive LTK and CSRK 
+   */
+    aci_hal_write_config_data( CONFIG_DATA_IR_OFFSET, CONFIG_DATA_IR_LEN, (uint8_t*)BLE_CFG_IR_VALUE );
+    
+   /**
+   * Write Encryption root key used to derive LTK and CSRK
+   */
+    aci_hal_write_config_data( CONFIG_DATA_ER_OFFSET, CONFIG_DATA_ER_LEN, (uint8_t*)BLE_CFG_ER_VALUE );
+  
+  /**
+   * Set TX Power to 0dBm.
+   */
+  aci_hal_set_tx_power_level(1, CFG_TX_POWER);
+
+  /**
+   * Initialize GATT interface
+   */
+  aci_gatt_init();
+
+  /**
+   * Initialize GAP interface
+   */
+  role = 0;
+
+#if (BLE_CFG_PERIPHERAL == 1)
+  role |= GAP_PERIPHERAL_ROLE;
+#endif
+
+#if (BLE_CFG_CENTRAL == 1)
+  role |= GAP_CENTRAL_ROLE;
+#endif
+
+  if (role > 0)
+  {
+    const char *name = "BLEcore";
+
+    aci_gap_init(role, 0,
+                 APPBLE_GAP_DEVICE_NAME_LENGTH,
+                 &gap_service_handle, &gap_dev_name_char_handle, &gap_appearance_char_handle);
+
+    if (aci_gatt_update_char_value(gap_service_handle, gap_dev_name_char_handle, 0, strlen(name), (uint8_t *) name))
+    {
+      BLE_DBG_SVCCTL_MSG("Device Name aci_gatt_update_char_value failed.\n");
+    }
+  }
+
+  if(aci_gatt_update_char_value(gap_service_handle,
+                                gap_appearance_char_handle,
+                                0,
+                                2,
+                                (uint8_t *)&appearance))
+  {
+    BLE_DBG_SVCCTL_MSG("Appearance aci_gatt_update_char_value failed.\n");
+  }
+
+
+
+  /**
+   * Initialize IO capability
+   */
+  aci_gap_set_io_capability(CFG_IO_CAPABILITY);
+
+  /**
+   * Initialize authentication
+   */
+
+
+  aci_gap_set_authentication_requirement(CFG_BONDING_MODE,
+                                         CFG_MITM_PROTECTION,
+                                         0,
+                                         0,
+                                         CFG_ENCRYPTION_KEY_SIZE_MIN,
+                                         CFG_ENCRYPTION_KEY_SIZE_MAX,
+                                         CFG_USED_FIXED_PIN,
+                                         CFG_FIXED_PIN,
+                                         0
+  );
+
+
+}
+
+static void Adv_Request(void){
+  aci_gap_set_discoverable(ADV_IND,
+                               CFG_FAST_CONN_ADV_INTERVAL_MIN,
+                               CFG_FAST_CONN_ADV_INTERVAL_MAX,
+                               PUBLIC_ADDR,
+                               NO_WHITE_LIST_USE, sizeof(local_name), (uint8_t*) &local_name, 0, 0, 0, 0);
+
+  /* Send Advertising data */
+  aci_gap_update_adv_data(sizeof(manuf_data), (uint8_t*) manuf_data);
+}
+
+static void Delete_Sectors( void )
+{
+  /**
+   * The number of sectors to erase is read from SRAM1.
+   * It shall be checked whether the number of sectors to erase does not overlap on the secured Flash
+   * The limit can be read from the SFSA option byte which provides the first secured sector address.
+   */
+
+  uint32_t page_error;
+  FLASH_EraseInitTypeDef p_erase_init;
+  uint32_t first_secure_sector_idx;
+
+  first_secure_sector_idx = (READ_BIT(FLASH->SFR, FLASH_SFR_SFSA) >> FLASH_SFR_SFSA_Pos);
+
+  p_erase_init.TypeErase = FLASH_TYPEERASE_PAGES;
+
+  p_erase_init.Page = CFG_OTA_START_SECTOR_IDX_VAL_MSG;
+  if(p_erase_init.Page < (CFG_APP_START_SECTOR_INDEX - 1))
+  {
+    /**
+     * Something has been wrong as there is no case we should delete the BLE_Ota application
+     * Reboot on the firmware application
+     */
+    CFG_OTA_REBOOT_VAL_MSG = CFG_REBOOT_ON_FW_APP;
+    NVIC_SystemReset(); /* it waits until reset */
+  }
+  p_erase_init.NbPages = CFG_OTA_NBR_OF_SECTOR_VAL_MSG;
+
+  if ((p_erase_init.Page + p_erase_init.NbPages) > first_secure_sector_idx)
+  {
+    p_erase_init.NbPages = first_secure_sector_idx - p_erase_init.Page;
+  }
+
+  HAL_FLASH_Unlock();
+
+  HAL_FLASHEx_Erase(&p_erase_init, &page_error);
+
+  HAL_FLASH_Lock();
+
+  return;
+}
+
+const uint8_t* BleGetBdAddress( void )
+{
+  uint8_t *otp_addr;
+  const uint8_t *bd_addr;
+  uint32_t udn;
+  uint32_t company_id;
+  uint32_t device_id;
+
+  udn = LL_FLASH_GetUDN();
+
+  if(udn != 0xFFFFFFFF)
+  {
+    company_id = LL_FLASH_GetSTCompanyID();
+    device_id = LL_FLASH_GetDeviceID();
+
+    bd_addr_udn[0] = (uint8_t)(udn & 0x000000FF);
+    bd_addr_udn[1] = (uint8_t)( (udn & 0x0000FF00) >> 8 );
+    bd_addr_udn[2] = (uint8_t)( (udn & 0x00FF0000) >> 16 );
+    bd_addr_udn[3] = (uint8_t)device_id;
+    bd_addr_udn[4] = (uint8_t)(company_id & 0x000000FF);;
+    bd_addr_udn[5] = (uint8_t)( (company_id & 0x0000FF00) >> 8 );
+
+    bd_addr = (const uint8_t *)bd_addr_udn;
+  }
+  else
+  {
+    otp_addr = OTP_Read(0);
+    if(otp_addr)
+    {
+      bd_addr = ((OTP_ID0_t*)otp_addr)->bd_address;
+    }
+    else
+    {
+      bd_addr = M_bd_addr;
+    }
+
+  }
+
+  return bd_addr;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+void hci_notify_asynch_evt(void* pdata)
+{
+  UTIL_SEQ_SetTask(1 << CFG_TASK_HCI_ASYNCH_EVT_ID, CFG_SCH_PRIO_0);
+  return;
+}
+
+void hci_cmd_resp_release(uint32_t flag)
+{
+  UTIL_SEQ_SetEvt(1 << CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID);
+  return;
+}
+
+void hci_cmd_resp_wait(uint32_t timeout)
+{
+  UTIL_SEQ_WaitEvt(1 << CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID);
+  return;
+}
+
+static void BLE_UserEvtRx( void * pPayload )
+{
+  SVCCTL_UserEvtFlowStatus_t svctl_return_status;
+  tHCI_UserEvtRxParam *pParam;
+
+  pParam = (tHCI_UserEvtRxParam *)pPayload; 
+
+  svctl_return_status = SVCCTL_UserEvtRx((void *)&(pParam->pckt->evtserial));
+  if (svctl_return_status != SVCCTL_UserEvtFlowDisable)
+  {
+    pParam->status = HCI_TL_UserEventFlow_Enable;
+  }
+  else
+  {
+    pParam->status = HCI_TL_UserEventFlow_Disable;
+  }
+}
+
+static void BLE_StatusNot( HCI_TL_CmdStatus_t status )
+{
+  uint32_t task_id_list;
+  switch (status)
+  {
+    case HCI_TL_CmdBusy:
+      /**
+       * All tasks that may send an aci/hci commands shall be listed here
+       * This is to prevent a new command is sent while one is already pending
+       */
+      task_id_list = (1 << CFG_LAST_TASK_ID_WITH_HCICMD) - 1;
+      UTIL_SEQ_PauseTask(task_id_list);
+
+      break;
+
+    case HCI_TL_CmdAvailable:
+      /**
+       * All tasks that may send an aci/hci commands shall be listed here
+       * This is to prevent a new command is sent while one is already pending
+       */
+      task_id_list = (1 << CFG_LAST_TASK_ID_WITH_HCICMD) - 1;
+      UTIL_SEQ_ResumeTask(task_id_list);
+
+      break;
+
+    default:
+      break;
+  }
+  return;
+}
+
+void SVCCTL_ResumeUserEventFlow( void )
+{
+  hci_resume_flow();
+  return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/app_ble.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/app_ble.h
new file mode 100644
index 000000000..34dd2643e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/app_ble.h
@@ -0,0 +1,52 @@
+
+/**
+  ******************************************************************************
+  * @file    app_ble.h
+  * @author  MCD Application Team
+  * @brief   Header for ble application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_BLE_H
+#define __APP_BLE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+#include "hci_tl.h"
+  
+  /* Exported types ------------------------------------------------------------*/
+
+
+  /* Exported constants --------------------------------------------------------*/
+  /* External variables --------------------------------------------------------*/
+  /* Exported macros -----------------------------------------------------------*/
+  /* Exported functions ------------------------------------------------------- */
+  void APP_BLE_Init( void );
+      
+  void APP_BLE_Key_Button1_Action(void);
+  void APP_BLE_Key_Button2_Action(void);
+  void APP_BLE_Key_Button3_Action(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__APP_BLE_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/ble_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/ble_conf.h
new file mode 100644
index 000000000..3162e1277
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/ble_conf.h
@@ -0,0 +1,66 @@
+/**
+ ******************************************************************************
+ * @file    ble_conf.h
+ * @author  MCD Application Team
+ * @brief   BLE configuration file
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __BLE_CONF_H
+#define __BLE_CONF_H
+
+#include "app_conf.h"
+
+/******************************************************************************
+ *
+ * BLE SERVICES CONFIGURATION
+ * blesvc
+ *
+ ******************************************************************************/
+
+/**
+ * This setting shall be set to '1' if the device needs to support the Peripheral Role
+ * In the MS configuration, both BLE_CFG_PERIPHERAL and BLE_CFG_CENTRAL shall be set to '1'
+ */
+#define BLE_CFG_PERIPHERAL                                                     1
+
+/**
+ * This setting shall be set to '1' if the device needs to support the Central Role
+ * In the MS configuration, both BLE_CFG_PERIPHERAL and BLE_CFG_CENTRAL shall be set to '1'
+ */
+#define BLE_CFG_CENTRAL                                                        0
+
+/**
+ * There is one handler per service enabled
+ * Note: There is no handler for the Device Information Service
+ *
+ * This shall take into account all registered handlers
+ * (from either the provided services or the custom services)
+ */
+#define BLE_CFG_SVC_MAX_NBR_CB                                                 7
+
+#define BLE_CFG_CLT_MAX_NBR_CB                                                 0
+
+/******************************************************************************
+ * GAP Service - Apprearance
+ ******************************************************************************/
+#define BLE_CFG_UNKNOWN_APPEARANCE                  (0)
+#define BLE_CFG_HR_SENSOR_APPEARANCE                (832)
+#define BLE_CFG_GAP_APPEARANCE                      (BLE_CFG_UNKNOWN_APPEARANCE)
+
+#endif /*__BLE_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/ble_dbg_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/ble_dbg_conf.h
new file mode 100644
index 000000000..6d72ba832
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/ble_dbg_conf.h
@@ -0,0 +1,207 @@
+/**
+ ******************************************************************************
+ * @file    ble_dbg_conf.h
+ * @author  MCD Application Team
+ * @brief   BLE Debug configuration file
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __BLE_DBG_CONF_H
+#define __BLE_DBG_CONF_H
+
+/**
+ * Enable or Disable traces from BLE
+ */
+
+#define BLE_DBG_DIS_EN          0
+#define BLE_DBG_HRS_EN          0
+#define BLE_DBG_EDS_STM_EN      0
+#define BLE_DBG_LBS_STM_EN      0
+#define BLE_DBG_SVCCTL_EN       0
+#define BLE_DBG_CTS_EN          0
+#define BLE_DBG_HIDS_EN         0
+#define BLE_DBG_PASS_EN         0
+#define BLE_DBG_BLS_EN          0
+#define BLE_DBG_HTS_EN          0
+#define BLE_DBG_ANS_EN          0
+#define BLE_DBG_ESS_EN          0
+#define BLE_DBG_GLS_EN          0
+#define BLE_DBG_BAS_EN          0
+#define BLE_DBG_RTUS_EN         0
+#define BLE_DBG_HPS_EN          0
+#define BLE_DBG_TPS_EN          0
+#define BLE_DBG_LLS_EN          0
+#define BLE_DBG_IAS_EN          0
+#define BLE_DBG_DTS_EN          0
+#define BLE_DBG_WSS_EN          0
+#define BLE_DBG_LNS_EN          0
+#define BLE_DBG_SCPS_EN         0
+#define BLE_DBG_P2P_STM_EN      0
+
+
+/**
+ * Macro definition
+ */
+#if ( BLE_DBG_DIS_EN != 0 )
+#define BLE_DBG_DIS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_DIS_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_HRS_EN != 0 )
+#define BLE_DBG_HRS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HRS_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_P2P_STM_EN != 0 )
+#define BLE_DBG_P2P_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_P2P_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_EDS_STM_EN != 0 )
+#define BLE_DBG_EDS_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_EDS_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_LBS_STM_EN != 0 )
+#define BLE_DBG_LBS_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_LBS_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_SVCCTL_EN != 0 )
+#define BLE_DBG_SVCCTL_MSG          PRINT_MESG_DBG
+#else
+#define BLE_DBG_SVCCTL_MSG          PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_CTS_EN != 0)
+#define BLE_DBG_CTS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_CTS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HIDS_EN != 0)
+#define BLE_DBG_HIDS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_HIDS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_PASS_EN != 0)
+#define BLE_DBG_PASS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_PASS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_BLS_EN != 0)
+#define BLE_DBG_BLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_BLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HTS_EN != 0)
+#define BLE_DBG_HTS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HTS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_ANS_EN != 0)
+#define BLE_DBG_ANS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_ANS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_ESS_EN != 0)
+#define BLE_DBG_ESS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_ESS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_GLS_EN != 0)
+#define BLE_DBG_GLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_GLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_BAS_EN != 0)
+#define BLE_DBG_BAS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_BAS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_RTUS_EN != 0)
+#define BLE_DBG_RTUS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_RTUS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HPS_EN != 0)
+#define BLE_DBG_HPS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HPS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_TPS_EN != 0)
+#define BLE_DBG_TPS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_TPS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_LLS_EN != 0)
+#define BLE_DBG_LLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_LLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_IAS_EN != 0)
+#define BLE_DBG_IAS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_IAS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_WSS_EN != 0)
+#define BLE_DBG_WSS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_WSS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_LNS_EN != 0)
+#define BLE_DBG_LNS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_LNS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_SCPS_EN != 0)
+#define BLE_DBG_SCPS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_SCPS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_DTS_EN != 0)
+#define BLE_DBG_DTS_MSG             PRINT_MESG_DBG
+#define BLE_DBG_DTS_BUF             PRINT_LOG_BUFF_DBG
+#else
+#define BLE_DBG_DTS_MSG             PRINT_NO_MESG
+#define BLE_DBG_DTS_BUF             PRINT_NO_MESG
+#endif
+
+
+#endif /*__BLE_DBG_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/otas_app.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/otas_app.c
new file mode 100644
index 000000000..d0104cb96
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/App/otas_app.c
@@ -0,0 +1,212 @@
+/**
+ ******************************************************************************
+ * @file    otas_app.c
+ * @author  MCD Application Team
+ * @brief   OTA Service Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "ble.h"
+#include "shci.h"
+
+
+
+/* Private typedef -----------------------------------------------------------*/
+
+/* Private typedef -----------------------------------------------------------*/
+typedef enum
+{
+  Wireless_Fw,
+  Fw_App,
+} OTAS_APP_FileType_t;
+
+typedef struct
+{
+  uint32_t base_address;
+  uint64_t write_value;
+  uint8_t  write_value_index;
+  uint8_t  file_type;
+} OTAS_APP_Context_t;
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+OTAS_APP_Context_t OTAS_APP_Context;
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Functions Definition ------------------------------------------------------*/
+/* Private functions ----------------------------------------------------------*/
+/* Public functions ----------------------------------------------------------*/
+
+void OTAS_STM_Notification( OTA_STM_Notification_t *p_notification )
+{
+  uint32_t count;
+  uint32_t size_left;
+  OTAS_STM_Indication_Msg_t msg_conf;
+
+  switch(p_notification->ChardId)
+  {
+    case OTAS_STM_BASE_ADDR_ID:
+    {
+      switch( ((OTA_STM_Base_Addr_Event_Format_t*)(p_notification->pPayload))->Command )
+      {
+        case OTAS_STM_STOP_ALL_UPLOAD:
+          break;
+
+        case OTAS_STM_WIRELESS_FW_UPLOAD:
+          OTAS_APP_Context.file_type = Wireless_Fw;
+          OTAS_APP_Context.base_address = FLASH_BASE;
+          ((uint8_t*)&OTAS_APP_Context.base_address)[0] = (((uint8_t*)((OTA_STM_Base_Addr_Event_Format_t*)(p_notification->pPayload))->Base_Addr))[2];
+          ((uint8_t*)&OTAS_APP_Context.base_address)[1] = (((uint8_t*)((OTA_STM_Base_Addr_Event_Format_t*)(p_notification->pPayload))->Base_Addr))[1];
+          ((uint8_t*)&OTAS_APP_Context.base_address)[2] = (((uint8_t*)((OTA_STM_Base_Addr_Event_Format_t*)(p_notification->pPayload))->Base_Addr))[0];
+          OTAS_APP_Context.write_value_index = 0;
+          break;
+
+        case OTAS_STM_APPLICATION_UPLOAD:
+          OTAS_APP_Context.file_type = Fw_App;
+          OTAS_APP_Context.base_address = FLASH_BASE;
+          ((uint8_t*)&OTAS_APP_Context.base_address)[0] = (((uint8_t*)((OTA_STM_Base_Addr_Event_Format_t*)(p_notification->pPayload))->Base_Addr))[2];
+          ((uint8_t*)&OTAS_APP_Context.base_address)[1] = (((uint8_t*)((OTA_STM_Base_Addr_Event_Format_t*)(p_notification->pPayload))->Base_Addr))[1];
+          ((uint8_t*)&OTAS_APP_Context.base_address)[2] = (((uint8_t*)((OTA_STM_Base_Addr_Event_Format_t*)(p_notification->pPayload))->Base_Addr))[0];
+          OTAS_APP_Context.write_value_index = 0;
+          break;
+
+        case OTAS_STM_UPLOAD_FINISHED:
+          msg_conf = OTAS_STM_REBOOT_CONFIRMED;
+          (void) OTAS_STM_UpdateChar(OTAS_STM_CONF_ID, (uint8_t*)&msg_conf);
+          break;
+
+        case OTAS_STM_CANCEL_UPLOAD:
+          break;
+
+        default:
+          break;
+      }
+    }
+    break;
+
+    case OTAS_STM_RAW_DATA_ID:
+      /**
+       * Write in Flash the data received in the BLE packet
+       */
+      count = 0;
+      size_left = p_notification->ValueLength;
+
+      while( LL_HSEM_1StepLock( HSEM, CFG_HW_FLASH_SEMID ) );
+      HAL_FLASH_Unlock();
+      while( size_left >= (8 - OTAS_APP_Context.write_value_index) )
+      {
+        memcpy( (uint8_t*)&OTAS_APP_Context.write_value + OTAS_APP_Context.write_value_index,
+                ((OTA_STM_Raw_Data_Event_Format_t*)(p_notification->pPayload))->Raw_Data + count,
+                8 - OTAS_APP_Context.write_value_index );
+        while(LL_FLASH_IsActiveFlag_OperationSuspended());
+        HAL_FLASH_Program( FLASH_TYPEPROGRAM_DOUBLEWORD,
+                           OTAS_APP_Context.base_address,
+                           OTAS_APP_Context.write_value);
+        if(*(uint64_t*)(OTAS_APP_Context.base_address)==OTAS_APP_Context.write_value)
+        {
+          OTAS_APP_Context.base_address += 8;
+          size_left -= (8 - OTAS_APP_Context.write_value_index);
+          count += (8 - OTAS_APP_Context.write_value_index);
+          OTAS_APP_Context.write_value_index = 0;
+        }
+      }
+      HAL_FLASH_Lock();
+      LL_HSEM_ReleaseLock( HSEM, CFG_HW_FLASH_SEMID, 0 );
+
+      /**
+       * The Flash shall be written by 32bits data. In case the packet received is not a multiple of 4 bytes,
+       * it shall be recorded how much bytes is left to pe written in flash
+       */
+      if(size_left != 0)
+      {
+        memcpy( (uint8_t*)&OTAS_APP_Context.write_value + OTAS_APP_Context.write_value_index,
+                ((OTA_STM_Raw_Data_Event_Format_t*)(p_notification->pPayload))->Raw_Data + count,
+                size_left );
+        OTAS_APP_Context.write_value_index += size_left;
+      }
+      break;
+
+    case OTAS_STM_CONF_EVENT_ID:
+    {
+      /**
+       * The Remote notifies it has send all the data to be written in Flash
+       */
+
+      /**
+       * Write now in Flash the remaining data that has not been written before because they were less than
+       * 4 bytes to be written
+       * As it is mandatory to write 4 bytes, some random bytes will be written at the same time than the left
+       * unwritten bytes to complete up to 4 bytes.
+       */
+      if(OTAS_APP_Context.write_value_index != 0)
+      {
+        while( LL_HSEM_1StepLock( HSEM, CFG_HW_FLASH_SEMID ) );
+        HAL_FLASH_Unlock();
+        while(*(uint64_t*)(OTAS_APP_Context.base_address) != OTAS_APP_Context.write_value)
+        {
+          while(LL_FLASH_IsActiveFlag_OperationSuspended());
+          HAL_FLASH_Program( FLASH_TYPEPROGRAM_DOUBLEWORD,
+                             OTAS_APP_Context.base_address,
+                             OTAS_APP_Context.write_value);
+        }
+        HAL_FLASH_Lock();
+        LL_HSEM_ReleaseLock( HSEM, CFG_HW_FLASH_SEMID, 0 );
+      }
+
+      /**
+       * Decide now what to do after all the data has been written in Flash
+       */
+      switch(OTAS_APP_Context.file_type)
+      {
+        case Fw_App:
+          /**
+           * Reboot on FW Application
+           */
+          CFG_OTA_REBOOT_VAL_MSG = CFG_REBOOT_ON_FW_APP;
+          NVIC_SystemReset(); /* it waits until reset */
+          break;
+
+        case Wireless_Fw:
+          /**
+           * Wireless firmware update is requested
+           * Request CPU2 to reboot on FUS by sending two FUS command
+           */
+          SHCI_C2_FUS_GetState( NULL );
+          SHCI_C2_FUS_GetState( NULL );
+          while(1)
+          {
+            HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+          }
+          break;
+
+        default:
+          break;
+      }
+    }
+    break;
+
+    default:
+      break;
+  }
+
+  return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/Target/hw_ipcc.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/Target/hw_ipcc.c
new file mode 100644
index 000000000..0f839543a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/STM32_WPAN/Target/hw_ipcc.c
@@ -0,0 +1,523 @@
+/**
+ ******************************************************************************
+  * File Name          : Target/hw_ipcc.c
+  * Description        : Hardware IPCC source file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "mbox_def.h"
+
+/* Global variables ---------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+#define HW_IPCC_TX_PENDING( channel ) ( !(LL_C1_IPCC_IsActiveFlag_CHx( IPCC, channel )) ) &&  (((~(IPCC->C1MR)) & (channel << 16U)))
+#define HW_IPCC_RX_PENDING( channel )  (LL_C2_IPCC_IsActiveFlag_CHx( IPCC, channel )) && (((~(IPCC->C1MR)) & (channel << 0U)))
+
+/* Private macros ------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static void (*FreeBufCb)( void );
+
+/* Private function prototypes -----------------------------------------------*/
+static void HW_IPCC_BLE_EvtHandler( void );
+static void HW_IPCC_BLE_AclDataEvtHandler( void );
+static void HW_IPCC_MM_FreeBufHandler( void );
+static void HW_IPCC_SYS_CmdEvtHandler( void );
+static void HW_IPCC_SYS_EvtHandler( void );
+static void HW_IPCC_TRACES_EvtHandler( void );
+
+#ifdef THREAD_WB
+static void HW_IPCC_OT_CmdEvtHandler( void );
+static void HW_IPCC_THREAD_NotEvtHandler( void );
+static void HW_IPCC_THREAD_CliNotEvtHandler( void );
+#endif
+
+#ifdef MAC_802_15_4_WB
+static void HW_IPCC_MAC_802_15_4_CmdEvtHandler( void );
+static void HW_IPCC_MAC_802_15_4_NotEvtHandler( void );
+#endif
+
+#ifdef ZIGBEE_WB
+static void HW_IPCC_ZIGBEE_CmdEvtHandler( void );
+static void HW_IPCC_ZIGBEE_StackNotifEvtHandler( void );
+static void HW_IPCC_ZIGBEE_CliNotifEvtHandler( void );
+#endif
+
+/* Public function definition -----------------------------------------------*/
+
+/******************************************************************************
+ * INTERRUPT HANDLER
+ ******************************************************************************/
+void HW_IPCC_Rx_Handler( void )
+{
+  if (HW_IPCC_RX_PENDING( HW_IPCC_SYSTEM_EVENT_CHANNEL ))
+  {
+      HW_IPCC_SYS_EvtHandler();
+  }
+#ifdef MAC_802_15_4_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_MAC_802_15_4_NotEvtHandler();
+  }
+#endif /* MAC_802_15_4_WB */
+#ifdef THREAD_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_THREAD_NotEvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_THREAD_CliNotEvtHandler();
+  }
+#endif /* THREAD_WB */
+#ifdef ZIGBEE_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_ZIGBEE_StackNotifEvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
+  {
+      HW_IPCC_ZIGBEE_CliNotifEvtHandler();
+  }
+#endif /* ZIGBEE_WB */
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_BLE_EVENT_CHANNEL ))
+  {
+    HW_IPCC_BLE_EvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_TRACES_CHANNEL ))
+  {
+    HW_IPCC_TRACES_EvtHandler();
+  }
+
+  return;
+}
+
+void HW_IPCC_Tx_Handler( void )
+{
+  if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_SYS_CmdEvtHandler();
+  }
+#ifdef MAC_802_15_4_WB
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_MAC_802_15_4_CmdEvtHandler();
+  }
+#endif /* MAC_802_15_4_WB */
+#ifdef THREAD_WB
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_OT_CmdEvtHandler();
+  }
+#endif /* THREAD_WB */
+#ifdef ZIGBEE_WB
+  if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
+  {
+      HW_IPCC_ZIGBEE_CmdEvtHandler();
+  }
+#endif /* ZIGBEE_WB */
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_SYS_CmdEvtHandler();
+  }
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ))
+  {
+    HW_IPCC_MM_FreeBufHandler();
+  }
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_HCI_ACL_DATA_CHANNEL ))
+  {
+    HW_IPCC_BLE_AclDataEvtHandler();
+  }
+
+  return;
+}
+/******************************************************************************
+ * GENERAL
+ ******************************************************************************/
+void HW_IPCC_Enable( void )
+{
+  /**
+   * When the device is out of standby, it is required to use the EXTI mechanism to wakeup CPU2
+   */
+  LL_C2_EXTI_EnableEvent_32_63( LL_EXTI_LINE_41 );
+  LL_EXTI_EnableRisingTrig_32_63( LL_EXTI_LINE_41 );
+	
+  /**
+   * In case the SBSFU is implemented, it may have already set the C2BOOT bit to startup the CPU2.
+   * In that case, to keep the mechanism transparent to the user application, it shall call the system command
+   * SHCI_C2_Reinit( ) before jumping to the application.
+   * When the CPU2 receives that command, it waits for its event input to be set to restart the CPU2 firmware.
+   * This is required because once C2BOOT has been set once, a clear/set on C2BOOT has no effect.
+   * When SHCI_C2_Reinit( ) is not called, generating an event to the CPU2 does not have any effect
+   * So, by default, the application shall both set the event flag and set the C2BOOT bit.
+   */
+  __SEV( );       /* Set the internal event flag and send an event to the CPU2 */
+  __WFE( );       /* Clear the internal event flag */
+  LL_PWR_EnableBootC2( );
+
+  return;
+}
+
+void HW_IPCC_Init( void )
+{
+  LL_AHB3_GRP1_EnableClock( LL_AHB3_GRP1_PERIPH_IPCC );
+
+  LL_C1_IPCC_EnableIT_RXO( IPCC );
+  LL_C1_IPCC_EnableIT_TXF( IPCC );
+
+  HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn);
+  HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn);
+
+  return;
+}
+
+/******************************************************************************
+ * BLE
+ ******************************************************************************/
+void HW_IPCC_BLE_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_BLE_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_BLE_CMD_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_BLE_EvtHandler( void )
+{
+  HW_IPCC_BLE_RxEvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_BLE_SendAclData( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_BLE_AclDataEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+
+  HW_IPCC_BLE_AclDataAckNot();
+
+  return;
+}
+
+__weak void HW_IPCC_BLE_AclDataAckNot( void ){};
+__weak void HW_IPCC_BLE_RxEvtNot( void ){};
+
+/******************************************************************************
+ * SYSTEM
+ ******************************************************************************/
+void HW_IPCC_SYS_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_SYS_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_SYS_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+
+  HW_IPCC_SYS_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_SYS_EvtHandler( void )
+{
+  HW_IPCC_SYS_EvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
+
+  return;
+}
+
+__weak void HW_IPCC_SYS_CmdEvtNot( void ){};
+__weak void HW_IPCC_SYS_EvtNot( void ){};
+
+/******************************************************************************
+ * MAC 802.15.4
+ ******************************************************************************/
+#ifdef MAC_802_15_4_WB
+void HW_IPCC_MAC_802_15_4_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_MAC_802_15_4_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_MAC_802_15_4_SendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_MAC_802_15_4_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+
+  HW_IPCC_MAC_802_15_4_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_MAC_802_15_4_NotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_MAC_802_15_4_EvtNot();
+
+  return;
+}
+__weak void HW_IPCC_MAC_802_15_4_CmdEvtNot( void ){};
+__weak void HW_IPCC_MAC_802_15_4_EvtNot( void ){};
+#endif
+
+/******************************************************************************
+ * THREAD
+ ******************************************************************************/
+#ifdef THREAD_WB
+void HW_IPCC_THREAD_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_OT_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_CLI_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_THREAD_SendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_THREAD_CliSendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_OT_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  HW_IPCC_OT_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_THREAD_NotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_THREAD_EvtNot();
+
+  return;
+}
+
+static void HW_IPCC_THREAD_CliNotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_THREAD_CliEvtNot();
+
+  return;
+}
+
+__weak void HW_IPCC_OT_CmdEvtNot( void ){};
+__weak void HW_IPCC_CLI_CmdEvtNot( void ){};
+__weak void HW_IPCC_THREAD_EvtNot( void ){};
+
+#endif /* THREAD_WB */
+
+/******************************************************************************
+ * ZIGBEE
+ ******************************************************************************/
+#ifdef ZIGBEE_WB
+void HW_IPCC_ZIGBEE_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendAppliCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendCliCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
+
+   return;
+}
+
+void HW_IPCC_ZIGBEE_SendAppliCmdAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendCliCmdAck( void )
+{
+    LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+    LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_CmdEvtHandler( void )
+{
+    LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+    HW_IPCC_ZIGBEE_AppliCmdNotification();
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_StackNotifEvtHandler( void )
+{
+    LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+    HW_IPCC_ZIGBEE_AppliAsyncEvtNotification();
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_CliNotifEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_ZIGBEE_CliEvtNotification();
+
+  return;
+}
+
+__weak void HW_IPCC_ZIGBEE_AppliCmdNotification( void ){};
+__weak void HW_IPCC_ZIGBEE_AppliAsyncEvtNotification( void ){};
+__weak void HW_IPCC_ZIGBEE_CliEvtNotification( void ){};
+#endif /* ZIGBEE_WB */
+
+/******************************************************************************
+ * MEMORY MANAGER
+ ******************************************************************************/
+void HW_IPCC_MM_SendFreeBuf( void (*cb)( void ) )
+{
+  if ( LL_C1_IPCC_IsActiveFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ) )
+  {
+    FreeBufCb = cb;
+    LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+  }
+  else
+  {
+    cb();
+
+    LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+  }
+
+  return;
+}
+
+static void HW_IPCC_MM_FreeBufHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+
+  FreeBufCb();
+
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+
+  return;
+}
+
+/******************************************************************************
+ * TRACES
+ ******************************************************************************/
+void HW_IPCC_TRACES_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_TRACES_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_TRACES_EvtHandler( void )
+{
+  HW_IPCC_TRACES_EvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_TRACES_CHANNEL );
+
+  return;
+}
+
+__weak void HW_IPCC_TRACES_EvtNot( void ){};
+
+/******************* (C) COPYRIGHT 2019 STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/readme.txt b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/readme.txt
new file mode 100644
index 000000000..6f785bea4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_Ota/readme.txt
@@ -0,0 +1,99 @@
+/**
+  @page BLE_Ota add here description
+  
+  @verbatim
+  ******************************************************************************
+  * @file    BLE/BLE_Ota/readme.txt 
+  * @author  MCD Application Team
+  * @brief   OTA implementation
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                               www.st.com/SLA0044
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+OTA implementation to download a new image into the user flash.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Directory contents 
+  
+  - BLE/BLE_Ota/Core/Inc/stm32wbxx_hal_conf.h		HAL configuration file
+  - BLE/BLE_Ota/Core/Inc/stm32wbxx_it.h          	Interrupt handlers header file
+  - BLE/BLE_Ota/Core/Inc/main.h                  	Header for main.c module
+  - BLE/BLE_Ota/STM32_WPAN/App/app_ble.h            Header for app_ble.c module
+  - BLE/BLE_Ota/Core/Inc/app_common.h            	Header for all modules with common definition
+  - BLE/BLE_Ota/Core/Inc/app_conf.h              	Parameters configuration file of the application
+  - BLE/BLE_Ota/Core/Inc/app_entry.h              	Parameters configuration file of the application
+  - BLE/BLE_Ota/STM32_WPAN/App/ble_conf.h           BLE Services configuration
+  - BLE/BLE_Ota/STM32_WPAN/App/ble_dbg_conf.h       BLE Traces configuration of the BLE services
+  - BLE/BLE_Ota/Core/Inc/hw_conf.h           		Configuration file of the HW
+  - BLE/BLE_Ota/Core/Inc/utilities_conf.h    		Configuration file of the utilities
+  - BLE/BLE_Ota/Core/Src/stm32wbxx_it.c          	Interrupt handlers
+  - BLE/BLE_Ota/Core/Src/main.c                  	Main program
+  - BLE/BLE_Ota/Core/Src/system_stm32wbxx.c      	stm32wbxx system source file
+  - BLE/BLE_Ota/STM32_WPAN/App/app_ble.c      		BLE Profile implementation
+  - BLE/BLE_Ota/Core/Src/app_entry.c      			Initialization of the application
+  - BLE/BLE_Ota/STM32_WPAN/Target/hw_ipcc.c      	IPCC Driver
+  - BLE/BLE_Ota/Core/Src/stm32_lpm_if.c				Low Power Manager Interface
+  - BLE/BLE_Ota/Core/Src/hw_timerserver.c 			Timer Server based on RTC
+  - BLE/BLE_Ota/Core/Src/hw_uart.c 					UART Driver
+  - BLE/BLE_Ota/STM32_WPAN/App/otas_app.c 			The OTA service mangement
+
+     
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35xx devices.
+  
+  - This example has been tested with an STMicroelectronics STM32WB35CE-Nucleo
+    board and can be easily tailored to any other supported device 
+    and development board.
+
+@par How to use it ? 
+
+This application requests having the stm32wb3x_BLE_Stack_fw.bin binary flashed on the Wireless Coprocessor.
+If it is not the case, you need to use STM32CubeProgrammer to load the appropriate binary.
+All available binaries are located under /Projects/STM32_Copro_Wireless_Binaries directory.
+Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the detailed procedure to change the
+Wireless Coprocessor binary.  
+
+In order to make the program work, you must do the following:
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - OR use BLE_Ota_reference.hex from Binary directory
+
+On the android/ios device, enable the Bluetooth communications, and if not done before,
+ - Install the ST BLE Sensor application on the ios/android device
+	https://play.google.com/store/apps/details?id=com.st.bluems
+	https://itunes.apple.com/us/App/st-bluems/id993670214?mt=8
+	
+The Ble_Ota Application allows a remote device to download an application binary.
+ - At Startup, the Ble_Ota application advertises "STM_OTA"
+ - with Smart Phone "ST BLE Sensor" application, scan and connect to "STM_OTA" Application.
+ - Next, select the binary to be downloaded on the Application Processor
+   -  BLE_HeartRate_ota_reference.bin or BLE_p2pServer_ota_reference.bin have to be copied into Smart phone directory
+ - Start download
+ - New Application is running and can be connected
+ 
+For more details refer to the Application Note: 
+  AN5289 - Building a Wireless application 
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
+ 
\ No newline at end of file
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Binary/BLE_TransparentMode.hex b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Binary/BLE_TransparentMode.hex
new file mode 100644
index 000000000..f87fa32b4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Binary/BLE_TransparentMode.hex
@@ -0,0 +1,1173 @@
+:020000040800F2
+:10000000F0130020ED4700082D4600082F46000899
+:10001000314600083346000835460008000000005D
+:10002000000000000000000000000000374600084B
+:1000300039460008000000003B4600083D46000825
+:10004000094800080D480008114800085B460008F0
+:100050001548000819480008554600081D480008C2
+:100060002148000825480008294800082D480008B4
+:100070003148000835480008394800083D48000864
+:100080004148000845480008494800084D48000814
+:100090005148000855480008594800085D480008C4
+:1000A0006148000865480008694800086D48000874
+:1000B0007148000875480008794800087D48000824
+:1000C0008148000885480008894800088D480008D4
+:1000D00041460008914800080000000095480008CB
+:1000E000994800089D480008A1480008A548000854
+:1000F000634600085F460008A9480008AD480008AC
+:10010000B148000800000000B5480008B9480008E0
+:10011000BD480008C1480008C5480008C948000893
+:10012000CD480008D148000847460008D5480008D7
+:10013000D9480008DD480008E148000838B5040047
+:1001400009D004F17C05686808B900F01EF800F0D9
+:1001500021F8012801D1012032BDA06A08B100F0C8
+:100160002AF800F00AF821F02A01FFE7816000F088
+:100170001BF8BDE8324000F0AABE2068416821F4B7
+:1001800090414160206881687047002129702046B5
+:1001900001F0DEB824206860206801684908490041
+:1001A0000160204600F0BCB92068016841F00101FF
+:1001B000016020467047204600F026BE30B500F1B1
+:1001C0007C035C68202C41D109B1140001D10120CD
+:1001D00030BD1C78012C39D001251D7000F154046C
+:1001E0000165228062800021E161D960212159608E
+:1001F00021698268B1F1005F13D1B2F5805F04BF5D
+:100200000169002907BFDFF8F022E261DFF8EC1294
+:10021000E161002119700068816841F4000181608A
+:1002200012E0B2F5805F04BF0169002907BFDFF863
+:10023000D022E261DFF8CC12E16100211970006880
+:10024000016841F080010160002030BD022030BD16
+:1002500030B500F17C039C68202C6AD109B11400F0
+:1002600001D1012030BD1C78012C62D001251D7008
+:1002700000F15C0481652280628000212161FF25FC
+:100280008168B1F5805F04D1016961B940F2FF1561
+:1002900009E011B9016929B905E0B1F1805F06D122
+:1002A000016911B97F25A58003E03F2100E000210D
+:1002B000A1800021D9602221996001688D6845F0F4
+:1002C00001058D60A168B1F1005F1CD1A589AA422A
+:1002D00019D38268B2F5805F04BF0169002907BFA6
+:1002E000DFF824222261DFF8241221610021197035
+:1002F00001680A6842F480720A600068816841F00F
+:100300008051816013E08268B2F5805F04BF0169AB
+:10031000002907BFDFF8F8212261DFF8F811216119
+:10032000002119700068016841F49071016000209B
+:1003300030BD022030BD206881684A067047F8B59C
+:10034000044640F60F002568E9692A68AB68084052
+:100350000DD1880602D5900602D4D80040F18980DC
+:10036000E16E00294FD02046BDE8F44008476A48B6
+:10037000034204BF694E32427BD0CF0709D5D60570
+:1003800007D501262E62D4F8885045F00105C4F83F
+:1003900088508D070AD5DD0708D526680225356205
+:1003A000D4F8885045F00405C4F888504D070AD5A4
+:1003B000DD0708D5266804253562D4F8885045F055
+:1003C0000205C4F888500D070CD5950601D40342E8
+:1003D00008D0256808202862D4F8880040F008007A
+:1003E000C4F8880008050BD5500109D525684FF4DD
+:1003F00000602862D4F8880040F02000C4F888002B
+:10040000D4F88800002870D0890607D5900601D45A
+:10041000D80003D5E16E09B120468847D4F888009A
+:1004200021688A68510602D410F0280F1AD020469D
+:1004300000F0BAFDFFF77FFF0FD500F057F860B16D
+:10044000DFF8A4198163A06F01F047F800284CD0B1
+:10045000A06F816BBDE8F44008472046BDE8F2403C
+:1004600001F010B9204601F00DF90020C4F8880011
+:10047000F1BDC80209D5580207D54FF48010286293
+:100480002046BDE8F24001F085B9080609D51006FE
+:1004900001D4180205D5216F39B32046BDE8F440D8
+:1004A000084748060FD550060DD5286820F04000B3
+:1004B00028602021C4F88010002020672046BDE875
+:1004C000F24001F085B9080206D5500004D5204657
+:1004D000BDE8F24001F08EB9C80148BF002A04D53A
+:1004E0002046BDE8F24001F086B9F1BD816821F0F7
+:1004F00040018160A06F7047B910000879100008B2
+:100500004B10000821100008FB110008A31100087F
+:10051000351100081111000801000010200100042D
+:100520002DE9F84F0446DFF8C8082768DFF8C4B89B
+:100530003968DFF8C4A80140A0680143206901437D
+:1005400060690143E0690143606E01433960002640
+:100550007968E06821F4405101437960B046A169AF
+:10056000DFF8880887421CBF206A0143BA68DFF8B9
+:100570005C0A02401143B9604FF48075F96A606A01
+:10058000090940EA0111F9625F454FF400404FF458
+:1005900000714FF480624FF400634FF4805C4FF4BD
+:1005A000005E4FF4804929D1DAF800B00BF0030B5C
+:1005B000BBF1030F3ED8DFE80BF00237343A4FF0BF
+:1005C000010AD4F81CB05746BBF5004F4FF6F07A3D
+:1005D00040F01183012F09D0022F00F05482042F24
+:1005E00000F08D82082F00F0C282F5E201F0EEFCEF
+:1005F0000146606A002840F01B8242E2DFF8ECB757
+:100600005F4517D1DAF800A01AF4406A27D0BAF58E
+:10061000806F09D0BAF5006F03D0BAF5406F06D0ED
+:1006200008E04FF0020A07E04FF0040A04E04FF040
+:10063000080A01E04FF0100ADFF8B0B75F45C0D1FB
+:10064000BAF1000F0BD0BAF1020F49D0BAF1040F82
+:1006500000F08280BAF1080F00F0B080B6E301F03C
+:10066000ADFC0146606A58B3012808BF022028D0BB
+:10067000022808BF042024D0032808BF062020D069
+:10068000042808BF08201CD0052808BF0A2018D05D
+:10069000062808BF0C2014D0072808BF102010D04F
+:1006A000082808BF20200CD0092808BF402008D007
+:1006B0000A2808BF802004D00B2808BF284600D095
+:1006C0000120B1FBF0F0002800F08283626802EBA9
+:1006D0004201884203D31103814280F0A18075E377
+:1006E000606AB0B3012808BFDFF8E408EED0022842
+:1006F00008BFDFF8E008E9D0032808BFDFF8D80812
+:10070000E4D0042808BFDFF8D408DFD0052808BFEC
+:10071000DFF8CC08DAD0062808BFDFF8C808D5D043
+:10072000072808BFDFF8C008D0D0082808BFDFF8C6
+:10073000BC08CBD0092808BFDFF8B408C6D00A2807
+:1007400008BFDFF8B008C1D00B2808BF4FF2244023
+:10075000BCD0DFF8A408B9E701F0E6FB0146606A07
+:1007600058B3012808BF0220ABD0022808BF0420DC
+:10077000A7D0032808BF0620A3D0042808BF08205C
+:100780009FD0052808BF0A209BD0062808BF0C2050
+:1007900097D0072808BF102093D0082808BF202032
+:1007A0008FD0092808BF40208BD00A2808BF80209E
+:1007B00087D00B2808BF284683D081E7676A002FBF
+:1007C00084D0012F08BF4846FAD0022F08BF7046D8
+:1007D000F6D0032F08BF41F25550F1D0042F08BFC7
+:1007E0006046EDD0052F08BF40F6CC40E8D0062F7C
+:1007F00008BF40F6AA2012D0072F08BF18460ED017
+:10080000082F08BF10460AD0092F08BF084606D097
+:100810000A2F08BF284602D00B2F00D1802055E7B1
+:10082000BAF1000F0BD0BAF1020F38D0BAF1040FB1
+:1008300000F07280BAF1080F00F0A780ECE001F040
+:10084000BDFB0146606A40B3012808BF02251ED0E7
+:10085000022808BF04251AD0032808BF062516D091
+:10086000042808BF082512D0052808BF0A250ED085
+:10087000062808BF0C250AD0072808BF102506D077
+:10088000082808BF202502D0092808BF402572D0BB
+:100890000A280CBF80250B286DD001256BE0606A0B
+:1008A000002836D0012808BFDFF89C692BD0022829
+:1008B00008BFDFF8986926D0032808BFDFF89069E1
+:1008C00021D0042808BFDFF88C691CD0052808BF98
+:1008D000DFF8846917D0062808BFDFF8806912D0D6
+:1008E000072808BFDFF878690DD0082808BFDFF8AF
+:1008F000746908D0092808BFDFF86C6903D00A289A
+:1009000008BFDFF868697CD00B2808BFDFF8E8660D
+:1009100077D0DFF85C6974E001F006FB0146606A9D
+:1009200040B3012808BF022525D0022808BF0425AE
+:1009300021D0032808BF06251DD0042808BF08259C
+:1009400019D0052808BF0A2515D0062808BF0C2590
+:1009500011D0072808BF10250DD0082808BF202572
+:1009600009D0092808BF402505D00A280CBF8025DA
+:100970000B2800D001256268B1FBF5F65008002174
+:1009800010EB062051EB166141E0606A002836D07A
+:10099000012808BF4FF4800633D0022808BF4FF467
+:1009A00000162ED0032808BFDFF8C86829D0042815
+:1009B00008BF4FF4801624D0052808BFDFF8B868B8
+:1009C0001FD0062808BFDFF8B4681AD0072808BF70
+:1009D0004FF4002615D0082808BF4FF4802610D009
+:1009E000092808BF4FF400360BD00A2808BF4FF47F
+:1009F000803606D00B2808BF4FF4004601D04FF4D4
+:100A00000006C246002116EB52004AEB010100230A
+:100A100001F06CFB064601E04FF00108A6F54070BE
+:100A2000DFF85C18884280F0D1812168CE60CFE188
+:100A3000012808BF02251AD0022808BF042516D0B5
+:100A4000032808BF062512D0042808BF08250ED0A9
+:100A5000052808BF0A250AD0062808BF0C2506D09D
+:100A6000072808BF102502D0082808BF202575D008
+:100A7000092808BF402571D00A280CBF80250B2803
+:100A80006CD001256AE0606AB0B3012808BFDFF8C6
+:100A9000680521D0022808BFDFF834051CD00328E0
+:100AA00008BFDFF8E00717D0042808BFDFF82405E7
+:100AB00012D0052808BFDFF8D0070DD0062808BFE0
+:100AC000DFF8140508D0072808BFDFF8100503D0A9
+:100AD000082808BFDFF810057AD0092808BFDFF81A
+:100AE0000C0575D00A2808BFDFF8040570D00B2864
+:100AF00008BFDFF800056BD0DFF8700768E001F091
+:100B000013FA0146606A40B3012808BF022525D0C8
+:100B1000022808BF042521D0032808BF06251DD0C0
+:100B2000042808BF082519D0052808BF0A2515D0B4
+:100B3000062808BF0C2511D0072808BF10250DD0A6
+:100B4000082808BF202509D0092808BF402505D05E
+:100B50000A280CBF80250B2800D001256068B1FB56
+:100B6000F5F1420802EB4102B2FBF0F632E0666AB0
+:100B700066B3012E2CD0022E08BF484628D0032E83
+:100B800008BF42F6AA2023D0042E08BF70461FD00B
+:100B9000052E08BF41F698101AD0062E08BF41F264
+:100BA000545015D0072E08BF604611D0082E08BF3C
+:100BB00018460DD0092E08BF104609D00A2E08BFCE
+:100BC000084605D00B2E08BF284601D04FF48030D0
+:100BD00000F014F9B6B201E04FF00108A6F11000E0
+:100BE000504580F0F3800AEA0601C6F34200014353
+:100BF0002068C160ECE0012F07D0022F35D0042F10
+:100C000070D0082F00F0A580D7E001F0DFF9014691
+:100C1000606A40B3012808BF022516D0022808BF29
+:100C2000042512D0032808BF06250ED0042808BFCB
+:100C300008250AD0052808BF0A2506D0062808BFBF
+:100C40000C2502D0072808BF10257AD0082808BF35
+:100C5000202576D0092808BF402572D00A280CBF6D
+:100C600080250B286DD001256BE0606AB0B30128A8
+:100C700008BFDFF85C1333D0022808BFDFF8541335
+:100C80002ED0032808BFDFF8501329D0042808BF4E
+:100C9000DFF8481324D0052808BFDFF844131FD01D
+:100CA000062808BFDFF83C131AD0072808BFDFF872
+:100CB000381315D0082808BFDFF8301310D00928E2
+:100CC00008BFDFF82C130BD00A2808BFDFF8241365
+:100CD00006D00B2808BF4FF2244101D0DFF81813CB
+:100CE000606831E001F020F90146606A40B30128F4
+:100CF00008BF022525D0022808BF042521D00328DB
+:100D000008BF06251DD0042808BF082519D00528CE
+:100D100008BF0A2515D0062808BF0C2511D00728C2
+:100D200008BF10250DD0082808BF202509D00928A4
+:100D300008BF402505D00A280CBF80250B2800D00D
+:100D400001256068B1FBF5F101EB5001B1FBF0F654
+:100D500031E0666A6EB3012E08BF484629D0022EE4
+:100D600008BF704625D0032E08BF41F2555020D051
+:100D7000042E08BF60461CD0052E08BF40F6CC40AC
+:100D800017D0062E08BF40F6AA2012D0072E08BFA3
+:100D900018460ED0082E08BF10460AD0092E08BFEC
+:100DA000084606D00A2E08BF284602D00B2E08BFE0
+:100DB000802000F023F8B6B201E04FF00108A6F160
+:100DC0001000504502D22068C66001E04FF00108D3
+:100DD00004F16800012141800180002141608160AF
+:100DE0004046BDE8F28F000011100008008000406E
+:100DF000F369FFCF0038014088000058616800EBBC
+:100E00005100B0FBF1F6704790F82810CA0706D5DC
+:100E100002685368C16A23F400330B43536090F8AF
+:100E200028108A0706D502685368016B23F48033C3
+:100E30000B43536090F828104A0706D502685368A0
+:100E4000416B23F480230B43536090F828100A076A
+:100E500006D502685368816B23F400430B4353604B
+:100E600090F82810CA0606D502689368C16B23F46F
+:100E700080530B43936090F828108A0606D50268C9
+:100E80009368016C23F400530B43936090F828108F
+:100E90004A0610D502685368416C23F480130B4353
+:100EA0005360416CB1F5801F05D15368816C23F408
+:100EB000C0030B43536090F828100A0606D501685A
+:100EC0004A68C06C22F4002202434A607047F8B5B9
+:100ED000044604F17C050020E8606FF07E4701F0D5
+:100EE0001DFA0646206801680A0708D500973346B0
+:100EF00000224FF40011204600F016F860B9206877
+:100F000001684A070AD50097334600224FF4800152
+:100F1000204600F009F808B10320F2BD20206860E7
+:100F2000A86000202870F2BD2DE9F041069C05461E
+:100F30000E4690461F462868C1693140B1420CBF39
+:100F40000120002040451CD114F1010FF3D001F025
+:100F5000E5F9C01B844200D314B900F015F80CE089
+:100F6000286801684A07E6D5C1690A05E3D54FF448
+:100F70000062026200F008F8C160002101700320E5
+:100F800000E00020BDE8F0812868016821F4D071FC
+:100F900001602868816849084900816005F17C008A
+:100FA000202141608160704701680A6822F49072D4
+:100FB0000A60DFF8D812026893680B409360202122
+:100FC000C0F884100021C16670470000FFF4FF11D3
+:100FD00000127A0000093D00AAB0280080841E009B
+:100FE000006A18005558140040420F0020A1070065
+:100FF00090D0030048E801000024F400136823F0B7
+:10100000800313600068016841F04001016070478F
+:10101000806A00F1560100220A810A8000F032BB8A
+:10102000D0F8801021290FD10268B0F8561001B90C
+:10103000E4E7036D19789162016D4A1C0265B0F80E
+:1010400056104A1EA0F856207047D0F8801021296B
+:1010500011D10268B0F8561001B9CFE7036D1988B5
+:10106000C1F308019162016D8A1C0265B0F8561047
+:101070004A1EA0F856207047D0F88010212900D0D1
+:10108000704730B500F15602938A0CE0E1690D0615
+:1010900008D5016D0D78A562016D4C1C046514889E
+:1010A000611E11805B1E99B229B104681188002964
+:1010B000ECD100F023F830BDD0F88010212900D009
+:1010C000704730B500F15602938A0EE0E1690D06D3
+:1010D0000AD5016D0D88C5F30805A562016D8C1C4C
+:1010E00004651488611E11805B1E99B229B10468E1
+:1010F00011880029EAD100F001F830BDA26822F47D
+:101100000002A2600068016841F040010160704780
+:1011100010B500F027F808D100F02AF80B70816DA7
+:101120004B1C00F019F821B929E0886940F008004B
+:10113000886110BD10B500F015F808D100F018F85E
+:101140000B80816D8B1C00F007F821B917E08869CE
+:1011500040F00800886110BD83652388591E2180F6
+:101160002188704700F16C0201689369222B704757
+:101170004B6A00F15E0461880B40816D7047016825
+:101180000B6823F490730B6001688B685B085B004D
+:101190008B602021916100211160BDE8104000F0BA
+:1011A0000DBB2DE9F84300F07DF81CD16789DFF80D
+:1011B000DC900AE000F08DF80870B06D411C00F082
+:1011C0006BF808B900F08BF87F1EB8B20028F1D197
+:1011D000208850B16189884207DA00F074F82C4801
+:1011E00000F06AF801E000F002F8BDE8F183306831
+:1011F000816941F00801816170472DE9F84300F0F1
+:1012000051F81CD16789DFF884900AE000F061F89A
+:101210000880B06D811C00F03FF808B900F05FF85D
+:101220007F1EB8B20028F1D1208850B16189884270
+:1012300007DA00F048F8174800F03EF801E0FFF741
+:10124000D6FFBDE8F18300000000127A0000093DDE
+:1012500000AAB0280080841E00006A1800555814A7
+:101260000040420F0020A1070090D0030048E80191
+:10127000000024F40055150000CC0C0000AA0A0060
+:1012800000FD0F005461510000D43000FEFFFFEF5D
+:101290001111000835110008B1652188481E208011
+:1012A00020887047064606F15E0406F16C05B4F826
+:1012B0000280A8692228704728603068016841F0E0
+:1012C0002001016070473068816821F080518160A1
+:1012D00070473068406AB16D08EA000070473068B6
+:1012E000016821F4807101603068816809EA0101B8
+:1012F00081602020A86100202860304600F05EBA9E
+:101300003A4881B0016841F400210160006800F4AE
+:1013100000200090009801B0704710B50446344991
+:101320002068884213D100F0FFFF00F0FDFF314834
+:10133000016821F4407141F480710160026842F457
+:10134000004202602046BDE8104001F001B810BD27
+:1013500038B586B0044601A8142101F011F82168BF
+:10136000254A914240D12548254D416941F48041AB
+:1013700041610222416901F48041009100990168B4
+:1013800041F002010160C021006800F002000090FD
+:1013900000980191012003900321072004910590FA
+:1013A000029201A9174800F0EFFF174828600F20AC
+:1013B00068601020A8600020E8608020286100207C
+:1013C0006861A861E8612862284600F01FF808B14A
+:1013D00001F00EFA6567AC6200220021242001F0C2
+:1013E00025FA242001F03FFA07B030BD5000005824
+:1013F0000028004090000058003801404C00005880
+:1014000004030020000400484404024038B50400EE
+:1014100001D1012032BD2168DFF84002814204F190
+:10142000240500F042F8022068700A68A0686FF393
+:101430000E120243E06802432069024360690243DE
+:10144000A0690243E0690243206A02430A60204621
+:1014500000F0DAF8A068B0F5804F04BF00216160A9
+:10146000696A207900F014F838B1052805D22046C1
+:1014700000F0E4F800F012F803E00020286368634D
+:10148000A8630020A861012068700020287032BD88
+:101490000860A96AE86A486060687047296B0020A4
+:1014A0000860696BA86B486070470AD2DFF8B0012A
+:1014B00042181423B2FBF3F292002A62DFF8A4016F
+:1014C00009E0DFF8A40142181423B2FBF3F2920002
+:1014D0002A62DFF89801E861704738B500F124020C
+:1014E00000245178022903D004209061012428E0CF
+:1014F00001680B6823F00E030B6001680D686D082E
+:101500006D000D60516A0B6823F480730B6001213C
+:1015100092F82030D56903F01C0399406960936A02
+:10152000D16A5960116B31B10B6823F480730B6081
+:10153000536B916B5960012151701470516901B165
+:101540008847204632BDF8B500F124010423CA695A
+:1015500014680268156891F8206006F01C0603FA0A
+:1015600006F73C4210D06F070ED51468A50603D4C9
+:10157000156825F00405156000F03DF8C9680029DC
+:1015800038D0BDE8F4400847022303FA06F73C428E
+:1015900013D0AF0711D51468A50605D4156825F03A
+:1015A0000A05156001224A7000F025F800220A7031
+:1015B0008968F9B1BDE8F4400847082303FA06F644
+:1015C000344217D02B0715D5136823F00E03136090
+:1015D000012291F82030CC6903F01C039A4062602C
+:1015E00001228A614A7000220A70096911B1BDE8BE
+:1015F000F4400847F1BD91F82020CC6902F01C02AC
+:101600009340636070470000416C0268134B890887
+:101610009A4234BF164B174B03EB8101816402F0F1
+:10162000FF02083A1421B2FBF1F1134AC26401F03F
+:101630001C01012202FA01F10165704701790F4A8C
+:1016400002EB81024265491E0D4A826501F00301E9
+:1016500001228A40C2657047000000000804024071
+:10166000F8FFFDBF00000240F8FBFDBF0004024090
+:10167000000802401C08024080080240FC080240AA
+:10168000400902407047000010B500F17C010A7863
+:10169000012A01D1022010BD01230B7024224A60CF
+:1016A00002681368146864086400146000224266CB
+:1016B00023F0005300680360202048600020087079
+:1016C00010BD70B500F01EF801D1022070BD00F011
+:1016D0001FF822F0604209E070B500F013F801D164
+:1016E000022070BD00F014F822F0606211438160A6
+:1016F000204600F01AF8206806602020686000206C
+:10170000287070BD044604F17C05287801287047D4
+:1017100001222A7024206860206806680268520846
+:1017200052000260206882687047FFB50FF25402D1
+:101730000FF25806D2E9003402A9C1E90034D6E913
+:101740000071CDE90071416E11B90121012213E050
+:1017500001688A688968520E02F00702490F02ACDC
+:10176000655CA45C1DF801101DF80220ED00E4008A
+:1017700095FBF1F194FBF2F2683041800280FFBDED
+:101780000000000001010103070100000804020439
+:10179000080101017047000030B912480360124887
+:1017A000124B0360FEF754BD704730B91048036018
+:1017B0000D480E4B0360FEF701BD704700680B49F2
+:1017C000884204D107490868002818BF00477047BD
+:1017D00000680649884204D105490868002818BFF6
+:1017E00000477047E8030020F8010020003801405E
+:1017F000EC030020704770474FF0B040006800F0E5
+:10180000F000B02888BFB02070472DE9F0410400F7
+:1018100051D0207881064FF0B04535D5A868E968E9
+:1018200010F00C0001F0030103D00C2808BF0129BF
+:1018300043D12868800702D5E06900283BD0FFF734
+:10184000DBFF616A884207D2084600F0D0FB00281F
+:1018500031D100F075FA0FE0286820F0F000014364
+:1018600029606968206A21F47F4141EA00216960AA
+:10187000606A00F0BCFBF0B901F073F8DFF808080B
+:10188000006801F0FDF8B0B92078C1070DD5A8684F
+:10189000E96800F00C00082801F0030103D00C28CF
+:1018A00008BF03292CD12868800340F1408160687B
+:1018B000002840F03C8101203BE2E06980B12968CA
+:1018C00041F0010100F026FB06462868800700F180
+:1018D0002B8100F023FD801B0328F6D3032028E290
+:1018E00028684008400000F0E7FB0646286800F042
+:1018F00023FAC9D000F012FD801B0328F6D3EDE7D0
+:101900006068B0F5803F06D0B0F5A02F296807D1F8
+:1019100041F480212960286840F48030286006E086
+:1019200021F4803129602A6822F480222A606068CC
+:1019300060B100F0F3FC06462868800300F1F780F0
+:1019400000F0ECFC801B6528F6D3C7E700F0E6FC4E
+:1019500006462868400C10F0010000F0E88000F016
+:10196000DDFC801B6528F4D3B8E700F0D7FCC01B72
+:101970000328C0F01081B1E7E06878B1296841F42C
+:10198000807100F0C7FA06462868400500F116810C
+:1019900000F0C4FC801B0328F6D39FE7286820F4DE
+:1019A000807000F089FB06462868800A10F001006C
+:1019B00000F0DB8000F0B2FC801B0328F4D38DE73D
+:1019C00000F0ACFCC01B0328C0F00A8186E740F0A1
+:1019D000010000F0C6F907467068800700F11B811E
+:1019E00000F09CFCC01B0328F6D377E7706820F05A
+:1019F000040000F0B6F907467068C00810F0010056
+:101A000000F0188100F08AFCC01B0428F4D365E7BD
+:101A10000528306806D140F004003060316841F09C
+:101A2000010105E0400840003060316821F0040108
+:101A30003160A06841F2893768B100F06FFC8046E0
+:101A40003068800700F10B8100F068FCA0EB080013
+:101A5000B842F5D342E700F061FC8046306800F000
+:101A60006BF900F0FC8000F059FCA0EB0800B842D4
+:101A7000F4D333E700F052FCC01B0328C0F0FD8014
+:101A80002CE7B06840084000B06000F047FC074613
+:101A9000B06800F051F900F0F48000F03FFCC01B8A
+:101AA0000328F5D31AE700F039FC801B0328C0F0A7
+:101AB0001A8113E700F032FC001B0328C0F03481C8
+:101AC0000CE7286881010CD4296841F080712960F5
+:101AD000E86840F08050E86000F020FC0446286888
+:101AE000810100F1258100F019FC001B0328F6D3C9
+:101AF000F4E60C2930D0286820F080702860E9686E
+:101B000089088900E960E86820F08050E86000F00A
+:101B100005FC04462868810140F10A8100F0FEFBC3
+:101B2000001B0328F6D3D9E600F00AF9ACE62078CA
+:101B300081071AD5A868E96800F00C00042801F0B4
+:101B4000030104D00C2808BF02297FF415AF2868D0
+:101B5000400503D5E06800283FF4ADAE6968206910
+:101B600021F0FE4141EA006169602168DFF81C65EF
+:101B700011F0180F38D0606900283FF437AFC9065C
+:101B800070687FF524AF800709D4706840F00100C9
+:101B900000F0E7F80746706880077FF5E6AE7068EA
+:101BA00040F0040000F0DDF80746706800070DD42F
+:101BB00000F0B4FBC01B0428F7D38FE668682169E6
+:101BC00020F0FE4040EA01606860CEE77068A169DD
+:101BD00020F4706040EA0120706000F0BFF8074612
+:101BE00000F0A9F87FF4ECAE2078410737D5DFF894
+:101BF000A0743868C10529D400F096FB00F08EFB74
+:101C000080463868C10521D400F088FBA0EB0800AD
+:101C10000328F6D362E6706820F0040070607068F4
+:101C2000C00810F00100DFD000F078FBC01B0428D2
+:101C3000F5D353E600F092F8074600F07CF8D3D0D5
+:101C400000F06CFBC01B0328F7D347E6A06801280F
+:101C50007FF4DEAE306840F001003060E9E62178C4
+:101C600048060ED5A06A00283FF40BAFB16841F0DA
+:101C70000101B16000F052FB0746B06880077FF5B4
+:101C8000F9AEE06A002853D0A968EA68022801F09A
+:101C90000C017FF42EAF236B02F00300984202BFC9
+:101CA00002F07000636B984214D1A36BC2F306205C
+:101CB000984202BF02F47810E36B98420AD1236C79
+:101CC00002F06060984202BF02F06042606C8242A3
+:101CD0003FF4F7AE0C293FF4EEAD286820F0807099
+:101CE00000F0EAF90646296888013FF5DCAEE968AC
+:101CF000DFF8A003A26B0140206B0143606B01433E
+:101D0000E06B41EA02210143206C0143606C014316
+:101D1000E960286840F080702860E96841F08051EF
+:101D2000E96000F0FBFA0446286881017FF5C2AE45
+:101D30000020BDE8F0817068400810F00100704795
+:101D40002968606A21F0F001014329606868216A0E
+:101D500020F47F4040EA01206860704770684008C6
+:101D60004000706000F0DABA2DE9F84304008846BC
+:101D700044D0DFF8246300F0C8F847D200F0CDF873
+:101D8000074600F0C2F841D000F0C8FAC01B022894
+:101D9000F7D90320B7E000F0C1FA401B022843D96D
+:101DA000F7E700F0BBFAA0EB090002284CD9F0E7F6
+:101DB00000F0B4FAA0EB0900022854D9E9E700F0DA
+:101DC000ADFA401B02285DD9E3E700F0A7FA401BFB
+:101DD000022867D9DDE700F0A1FA401B484577D318
+:101DE000D7E7032802D13968890103E00028396860
+:101DF00002D1890762D401E049055FD4012082E065
+:101E000000F08CFAC01B022872D9C2E72078810743
+:101E10004FF0B0470BD5B968A06821F0F00101433D
+:101E2000B96000F07BFA0546B868C003B3D52078E6
+:101E3000DFF8505281060AD52968606921F0F00167
+:101E4000014300F067F8814628688003A9D520780F
+:101E500041060BD52968A0690909090141EA101159
+:101E600000F058F881462868C003A1D520784107C2
+:101E70000BD5B968E06821F4E0610143B96000F076
+:101E80004DFA0546B868800399D5207801070CD52E
+:101E9000B868216920F4605040EAC100B86000F0E1
+:101EA0003DFA0546B86840038FD52078C10717D59D
+:101EB0006068022895D1396889039FD5B968890877
+:101EC00040EA8100B86041F2893900F027FA0546FE
+:101ED000B868616800F00C00B0EB810F7FF47BAF55
+:101EE000306800F00700804505D200F016F807467C
+:101EF00000F00BF884D100F034FD00F0F7FDBDE8F0
+:101F0000F24300F0BDBDBDE8F283306800F0070089
+:101F100040457047296000F001BA3168C90848EAB5
+:101F2000C101316000F0FAB938B54FF0B0445C4DF2
+:101F3000A16811F00C0106D1FFF75EFCC0F303109D
+:101F400055F8200032BD0429564A05D008295648C4
+:101F500004D12168C90222D5104632BDE16801F0E2
+:101F60000301022904D0032904D12168C90207D53D
+:101F7000104605E0FFF740FCC0F3031055F82000C1
+:101F8000E168E268E368C1F306214843C2F3021145
+:101F9000491C5B0FB0FBF1F05B1CB0FBF3F032BDF2
+:101FA00080B5FFF7C1FF3D49FFE7404A0968C1F32B
+:101FB000031152F82110B0FBF1F002BD80B5FFF71C
+:101FC000EFFF00F010F8C1F3022106E080B5FFF743
+:101FD000E7FF00F008F8C1F3C22112F8211001F068
+:101FE0001F01C84002BD2D49314A0968704770B5CC
+:101FF0002B49B1282EBFCC6AC0F3031051F8204002
+:102000002048056800F090FD28492A4A05F00F0590
+:1020100051F82510B4FBF1F10024B1FBF2F1B0F559
+:10202000007F0FF2B802204609D10FF2940353F853
+:1020300020508D4214D2401C0328F8D912E00FF230
+:10204000900353F820508D420AD2401C0328F8D345
+:1020500008E000F063F9801B03280BD3032070BD58
+:1020600052F820400C4D2868C00844EAC00000F037
+:1020700023F80646296801F00701A142E9D10020B2
+:1020800070BD000008010058480000209000005872
+:10209000000400588C80C11100400058080000580E
+:1020A000402A00080024F4000048E801002A000843
+:1020B0006C47000840420F00286000F02FB9000074
+:1020C0001200000024000000360000004000000064
+:1020D000060000000C0000001000000000000000DE
+:1020E000010000000200000003000000B3BBD9B1F2
+:1020F000B2F5803F7DD2022A1ED98C46B1FBF2F1A7
+:1021000002FB11C31B0443EA1043B3FBF2FC02FBC6
+:102110001C3380B240EA0343B3FBF2F002FB1032FF
+:1021200040EA0C4000237047022A05D98446B0FBE0
+:10213000F2F002FB10C270474AB105D100F0010273
+:1021400049085FEA3000704700220023704700F022
+:10215000F3BC0B000200002100207047904271EB9D
+:10216000030CF6D3B3F5803F2FD2F0B5B3FA83F763
+:10217000B1FA81F4A7F10F0E3D1B5340CEF12006BA
+:1021800002FA0EF2F3415340B5F10F0746D80F3C67
+:102190002C444140C4F12006A040F1414140B1FB34
+:1021A000F3F603FB1611A2FB0645001BA94102D260
+:1021B000761E8018594180EA010221FA0EF362FA74
+:1021C0000EF200215A403046F0BD30B4B1FBF3FCB2
+:1021D00003FB1C11A2FB0C45001BA94103D2ACF16F
+:1021E000010C8018594130BC02460B466046002164
+:1021F0007047B2F1807F65D3F0B5B2FA82F7B1FAD9
+:1022000081F4C7F10F063D1B22FA06F307F1110E08
+:10221000F24120355A40B5F10F07B8D94140C4F119
+:102220002006A040F1414140B1FBF3FC03FB1C112F
+:10223000A2FB0C45001BA94103D2BCF1010C801884
+:1022400059410F2F12D30F3FC90341EA5041B1FB4F
+:10225000F3F603FB1611A2FB0645D4EBC030A941EF
+:1022600002D2761E8018594146EACC3C07B3414061
+:10227000C7F12006B840F1414140B1FBF3F603FB42
+:102280001611A2FB0645001BA94102D2761E80183A
+:10229000594180EA010221FA0EF3C7F1200462FAE3
+:1022A0000EF20CFA07F05A402CFA04F13043F0BD5C
+:1022B00080EA010221FA0EF3002162FA0EF2604672
+:1022C0005A40F0BD8C46B1FBF2F102FB11C31B0278
+:1022D00043EA1063B3FBF2FC02FB1C331B024CEA23
+:1022E000002043EA1063B3FBF2FC02FB1C331B0229
+:1022F0004CEA002043EA1063B3FBF2FC02FB1C3300
+:102300001B024CEA002043EA1063B3FBF2FC02FB21
+:102310001C324CEA0020002370470000014800688E
+:10232000704700BF440000200248016841F48071FA
+:1023300001607047000400588A60FF210268516202
+:10234000012180F82110002180F820100020704722
+:1023500090F82010012901D102207047012280F855
+:102360002020022180F82110CA21026851625321E5
+:102370000368596201688A6842F02002FFF7DCBFF7
+:10238000002200F0DBBB00002DE9F84F4FF0000CFD
+:10239000644A654BDFF894814FF00F0982460F467F
+:1023A00033E0634DAA4514BF072504258D4025431E
+:1023B00048F82E50C1431C6801EA040E7C68E5030E
+:1023C00048BF40EA0E0EC3F800E05C6801EA040E64
+:1023D0007C68A50348BF40EA0E0EC3F804E0146809
+:1023E00001EA040E7C68E50248BF40EA0E0EC2F81E
+:1023F00000E0546801EA040E79688C0248BF40EAA4
+:102400000E0EC2F804E00CF1010C396831FA0CF040
+:1024100076D0012000FA0CFE1EEA0100F3D07C68A1
+:10242000022C18BF122C4FEA8C0110D14FEADC04A9
+:102430000AEB840401F01C05266A09FA05FB26EA6A
+:102440000B06D7F810B00BFA05F5354325624FEAB5
+:102450004C040325DAF8006097F804B0A540ED437A
+:102460000BF0030B2E400BFA04FB4BEA0606CAF8EE
+:1024700000607E68012E18BF022E03D0112E18BFF7
+:10248000122E17D1DAF80860D7F80CB02E400BFAEC
+:1024900004FB4BEA0606CAF80860DAF8046026EA8C
+:1024A0000E0E7E68C6F3001606FA0CF646EA0E0615
+:1024B000CAF80460DAF80C603540BE6806FA04F425
+:1024C0002C43CAF80C407C68E4009CD54FEA9C0E73
+:1024D00058F82E5001F00C0109FA01F425EA040421
+:1024E000BAF1904F08BF002509D0124DAA4508BF88
+:1024F000012504D0104DAA457FF453AF022555E7BE
+:10250000BDE8F18F81B0002A14BF8161816201B002
+:1025100070470A4A136803421CBF106000F0A2BB58
+:10252000704700000008005880080058080001406B
+:102530000010004800040048000800480C0800583B
+:102540009D4900E09D4981B00A6802430A6009681C
+:1025500008400090009801B0704710B500F0B2FA42
+:10256000974C606840010ED56068C0000BD4FFF73F
+:10257000DBFEFFF7D9FE206840F480302060216840
+:1025800021F48031216000F0DDF8002000F070FBC4
+:1025900040B180798B49E160E16821F47C5141EAE6
+:1025A0000021E16000F039F88748884C016800227A
+:1025B0000260026902F0500202610120FFF7C2FFCF
+:1025C0000220FFF7BFFF0420FFF7BAFF0220FFF74A
+:1025D000B7FF00220F213A2000F028F93A2000F03E
+:1025E00042F900217A4841600F218160046047F67A
+:1025F000FF71C16000F04EFBCA206062FF215320D2
+:102600006062A068C008C000A060616200F0B0FA1B
+:102610004FF0FF3000F0E2FBFAE730B5A9B017A8A1
+:102620004821FFF7ADFE01A81C21FFF7A9FE08A86D
+:102630003C21FFF7A5FE6248664C016821F01801B5
+:1026400001604FF48032206820F4C06040F40070D4
+:1026500020604FF48075216801F4C061009107216A
+:102660000098179101201990002140201B9018928A
+:1026700022911A9517A8FFF7C8F86F200190022140
+:10268000002002910390049005900690079001218C
+:1026900001A8FFF769FB43F60100089000214FF401
+:1026A00080401390099110200221159014911295E9
+:1026B00008A800F076FCE06920F07000E061464870
+:1026C0000168C1F303200090009830B9E16909095D
+:1026D000090141F00A01E16108E00098E169001D8B
+:1026E00080F30400090940EA0110E061E06940F468
+:1026F0000040E06129B030BD10B5384C384820604A
+:102700004FF4E13060600020A060E06020610C20A8
+:1027100060610020A0614FF40040E0610020206271
+:102720006062A0622046FDF709FD00212046FEF709
+:10273000C8FF00212046FEF7CFFF2046BDE810402D
+:10274000FEF7A2BF274881B0016841F48011016003
+:102750003F21006800F480100090009822484160FA
+:102760004161016841F47C110160026942F47C120C
+:102770000261016841F03F010160026942F03F02DD
+:10278000026101B0704738B50446FFF7C7FD14F188
+:10279000010F054609D000F0ACF9041905E0134813
+:1027A000016821F00401016030BFFFF7B7FD401B55
+:1027B000A042F4D331BD0000480000584C0000583E
+:1027C00090000058FECAFECA800800580028004049
+:1027D00064030020000400585875FF1FF801002012
+:1027E0000038014050000058040C005810ED00E083
+:1027F000704700000901020081B002D43C488154B6
+:1028000005E03C4802F00F02104400F8041C01B03F
+:102810007047394A13684FF6FF0100020B4000F47D
+:10282000E0601843354908431060704738B5324BB3
+:102830001C68C4F30223C3F10704052C28BF042439
+:102840001D1D072D34BF0023DB1E012505FA04F4EE
+:10285000641E2140994005FA03F35B1E1A401143A0
+:10286000BDE83440C6E7010007D4012200F01F0193
+:10287000234B8A40400943F82020704701000BD4C5
+:10288000012200F01F011F4B8A40400943F820201D
+:10289000BFF34F8FBFF36F8F704710B5401EB0F17D
+:1028A000807F01D3012010BD174C60600F214FF0D5
+:1028B000FF30FFF79FFF0022A2600720206000206A
+:1028C00010BD010007D4012200F01F010F4B8A4008
+:1028D000400943F820207047010007D4012200F08E
+:1028E0001F010B4B8A40400943F82020704700002D
+:1028F00000E400E018ED00E00CED00E00000FA0557
+:1029000000E100E080E100E010E000E000E200E033
+:1029100080E200E03249002008604FF4E0223148B4
+:10292000016841F4700101604FF0B041086840F067
+:10293000010008608A602C480A6802402B480A603F
+:10294000036823F0050303604268520852004260A6
+:1029500000222748C860086820F4802008608A6147
+:1029600070474FF0B0410FF2D8000A68C2F303126B
+:1029700050F822008A6802F00C02042A04D0082AC7
+:1029800004D00C2A04D01CE01A481AE01A4818E0B7
+:10299000CA68CB68C3F3021302F003025B1C022A6D
+:1029A00008BF144802D0032A08BF1348B0FBF3F253
+:1029B000C868CB68C0F306205B0F42435B1CB2FBC8
+:1029C000F3F00E4A0FF23803106088681168C0F304
+:1029D000031053F82000B1FBF0F0106070470000C6
+:1029E00008ED00E088ED00E0FBFEF6FA94000058E8
+:1029F000001004220024F4000048E80150000020E8
+:102A000001000000030000000500000001000000BC
+:102A100001000000060000000A0000002000000085
+:102A20000200000004000000080000001000000088
+:102A300040000000800000000001000000020000D3
+:102A4000A0860100400D0300801A060000350C002E
+:102A500040420F0080841E0000093D0000127A00F1
+:102A60000024F40000366E010048E801006CDC022E
+:102A70000000000000000000000000000000000056
+:102A800070B50F4E0446B0680025A8B1FFF788FA6C
+:102A9000B2684FF47A71B1FBF2F1B0FBF1F0FFF7DD
+:102AA000FCFE48B9102C07D2002221464FF0FF301F
+:102AB000FFF7BCFE746000E00125284670BD00BF32
+:102AC00044000020154810B5016841F48071016090
+:102AD0000320FFF79EFE0020FFF7D2FF002400280E
+:102AE00014BF0124FEF70CFC204610BD0C484068C2
+:102AF00070470B48806870470A48016849084900D8
+:102B0000016070470748016821F0020101607047C9
+:102B10000448016821F0040101607047004000583A
+:102B200044000020042004E0DFF80800006800F4FE
+:102B3000C0607047000400587047000000B500BF37
+:102B4000130096469446103928BFA0E80C50FAD8D6
+:102B50005FEA417C28BF0CC048BF40F8042BC9077E
+:102B600028BF20F8022B48BF00F8012B00BD000051
+:102B700018B53448344C89B0016841F40041016013
+:102B800000F0EEFA3149002000F0A5FC00F0C9FD8C
+:102B90000121012000F0F6FA002000F012FF0120D0
+:102BA00000F00FFF022000F00CFF012000F031FFC9
+:102BB0000121002000F041FF00F096FF244801F0C1
+:102BC0008AF80FF25D020021202000F06AF904F279
+:102BD0003C5002901F490FF231000190009168466D
+:102BE00000F0DDFF04F25470039004F5C96140F277
+:102BF0003C5006900491059403A801F005F800F0FC
+:102C000071FF0AB010BD000080B50146104801F008
+:102C10006EF8BDE804400021202000F04FB900000C
+:102C200080B500F0ACFD0021012000F0ABFA694650
+:102C3000074801F072F8009800F0FFFF01F07EF8FD
+:102C400001BD0000080000582C8000206403002013
+:102C5000B4030020093E000800F0A8BA4FF0FF308E
+:102C600000F0BCB8012808BF01F0DDB870470000D3
+:102C700001460648064AC3798B4218BF904218BFE6
+:102C80000838F8D18B4218BF00207047F873FF1F37
+:102C90000070FF1F38B5040044D094F8210028B913
+:102CA000002184F820102046FEF737FB00F049F899
+:102CB000FF2510B100F03FF834E02168DFF8B000E4
+:102CC0008A6802408A6021688A68636820690343D1
+:102CD000A06903431A438A602168E068086120689C
+:102CE0000169A26841EA024101612068C16821F0DE
+:102CF0008001C1602068C16C89088900C1642168B5
+:102D0000CA6CE369606903431A43CA642068816836
+:102D1000880609D400F020F830B12068456204210B
+:102D200000F01FF8012032BD20684562012184F8BF
+:102D30002110002032BD20684562042184F8211052
+:102D40007047022084F82100CA202168486253207D
+:102D500022685062204626E020460BE02068C0F83A
+:102D6000248084F82110002084F82000704700009F
+:102D7000BFFF8FFF70B5044640F2E9362068C16896
+:102D800021F0A001C160FFF7C9FA05462068C168BB
+:102D9000880606D4FFF7C2FA401BB042F6D30320E0
+:102DA00070BD002070BD70B504462068C1684A0639
+:102DB00012D44FF0FF32C26040F2E936FFF7AEFAAC
+:102DC00005462068C168480606D4FFF7A7FA401BED
+:102DD000B042F6D3032070BD002070BD2DE9FC4742
+:102DE000524CDFF84C91A5692840A0614FF0010AD0
+:102DF0004FF0FF3830E0491C54F831000642FAD059
+:102E000004EBC107184079681040014208BFC7F8B9
+:102E100004807E68304000F08DF860620AFA00F0AD
+:102E200086437E60EFF3108172B6626A20690AFA07
+:102E300002F2D24310402061022004EBC00353F899
+:102E4000086C1640401E43F8086CF6D181F31088D8
+:102E5000606A59F82010884763692069A2691840A0
+:102E6000104207D0E069216A084203D1002103EA39
+:102E70000206C1E701F03CF9EFF3108972B621694F
+:102E800060690140A069014201BFE169206A014215
+:102E9000FFF7E2FE89F3108801F02BF9A561BDE888
+:102EA000F38738B51446EFF3108572B600F042F898
+:102EB0001F4941F8204085F3108831BD10B5EFF36C
+:102EC000108272B6194B1C6904431C6153F83140DF
+:102ED000204343F8310082F3108810BD506181F324
+:102EE00010887047EFF3108172B6104AD369184307
+:102EF000D061F4E72DE9F0410C4C626A266A206249
+:102F0000012101FA02F803E039464046FFF7A6FE28
+:102F1000276AE5693D42F7D0404600F00BF825EA04
+:102F20000707E76126626062BDE8F0811C000020AF
+:102F30008402002002460020110C090404BF102066
+:102F4000120412F07F4F04BF083012020FF2180172
+:102F500012F0704F04BF001D1201120FC0F11F00CC
+:102F6000895C401A7047000004030202010101015C
+:102F70000000000000000000DFF8D8110A68030913
+:102F800003F47F2300019A4300F47F20DFE0DFF8A1
+:102F9000C4211368010C23EA014343EA0043136090
+:102FA00070472DE9F041054600272868DFF8A86141
+:102FB0000105B8462FD53468A86A04F440748442E9
+:102FC00029D0FFF7B1F9002C316805D1A86A21F4A6
+:102FD0004071014331601DE0306840F48030306062
+:102FE00021F44071326822F480323260A86A0143D1
+:102FF00031603068C0070DD5FFF790F9044641F203
+:1030000089383068800705D4FFF788F9001B4045F0
+:10301000F7D30327B8462878DFF84041C10705D524
+:10302000E16F6868890840EA8101E16728788107D3
+:1030300005D5E16FA86821F440610143E167287874
+:10304000C10644BF6869FFF7A2FF2878810644BF24
+:10305000A869FFF79CFF2878410744BFE868FFF79D
+:103060008BFF2878010744BF2869FFF785FF286890
+:10307000C1050AD5E16FE86921F040610143E167CC
+:10308000E869B0F1006F00F05CF8286881051BD595
+:10309000286AB0F1804F18BFB0F1004F00D018B9C6
+:1030A000E16F21F0404108E0E16F21F04041E1672C
+:1030B00020F08050E16F21F040610843E067286A0A
+:1030C000B0F1C05F00F03DF8286841050AD5E16F16
+:1030D000686A21F040510143E167686AB0F1005F1E
+:1030E00000F029F82868C10405D57168E86A21F460
+:1030F000404101437160286881040BD5A169686B68
+:1031000021F030010143A161A169286B890840EADF
+:103110008101A161286841040AD5E16FA86B21F4FF
+:1031200040710143E167A86BB0F5007F00F003F840
+:103130004046BDE8F08103D1216841F4803121602F
+:10314000704703D1216841F08071216070471043BE
+:103150000860704788000058900000580C00005824
+:103160002048002101604160704710B500F019F857
+:103170001C6819B1012904D1204301E024EA0000B0
+:1031800018600BE010B500F00CF85C6819B101296B
+:1031900004D1204301E024EA0000586082F3108843
+:1031A00010BDEFF3108272B60E4B704738B5EFF3D7
+:1031B000108472B60B490C4D086820B12968884705
+:1031C000686880470AE0486820B1A9688847E868CD
+:1031D000804703E0286980476869804784F3108846
+:1031E00031BD0000BC030020D4470008DFF8F01414
+:1031F0000A6892B200E00246086880B28242FAD1C0
+:1032000070472DE9FC4104461825DFF8D884DFF823
+:10321000D864684308EB00073078062808D1317875
+:103220007170347078754FF0FF307060002039E0B5
+:1032300000F077F8B9680918B96008F10803B968AF
+:1032400032786A439A589142327813D308F11503C1
+:1032500015FB02FC13F80C30062B25D008F10806EC
+:103260006B43F358994222BF08F115036A439A5CF5
+:10327000EED219E01146337869439A420BD008F137
+:10328000140308F1150C5B5C15FB03F50CF8054005
+:103290007A753B7500E07A7508F114025454317860
+:1032A00071703470BDE8F6811146694308F1150369
+:1032B0005B5C062B04D008F1140615FB03F574556E
+:1032C0007B753A7508F115025454EBE7F8B5DFF851
+:1032D0001834DFF810541E78182402466243B042B6
+:1032E0002A4404D118785870507D18700FE0167D6C
+:1032F000507D92F815C005F115076643062807F8BA
+:1033000006C004D0167D143514FB00F42E550120A0
+:1033100010731878062802BF00294FF0FF3159605A
+:10332000F1BD10B5DFF8C043606810F1010F0FD098
+:10333000FFF75CFF6168DFF8B423814261683CBF3E
+:103340005388C918081A517848431178C84000E0DA
+:10335000002080B210BD2DE9F84FDFF89053DFF860
+:1033600090B3D5F80880D8F80000DBF800104A05C3
+:1033700000F06AF9DFF87063DFF868A321F4806178
+:1033800081604FF0180934780AF1080019FB04F144
+:103390004758FFF7C6FF874217D200270121B170B7
+:1033A000062C3DD019FB04F40AF108010AF10802C9
+:1033B0000959814223BF0AF108010959091A00215C
+:1033C00011510AEB04014C7DEAE7A9884118B94282
+:1033D00002D2AF880021E2E73F1ADFE7022802DAD3
+:1033E0002878012800D07F1ED8F80000C1684A075D
+:1033F000FAD500F02FF9DBF80C00000CBFB247EA59
+:103400000047CBF80C70FFF7F1FE7060A868006809
+:10341000816841F480618160AFF30080BDE8F18F85
+:10342000B8B20028DAD1FFF7E1FE70600320BDE8F2
+:10343000F24FFFF746BA2DE9F843EFF3108872B662
+:10344000AA4DA84BA8680168CA224A625320486264
+:10345000A54A886820F4806088601820167837466E
+:1034600047431F44387B022826D13C68D7F8109088
+:103470009078F0B17A7B012A0AD101213046FFF71A
+:1034800025FF88F310887968304600F0F0F804E0F2
+:1034900088F31088304600F09BF8A8680068CA21BD
+:1034A00041622246532141624846314600F02AF9E2
+:1034B0000BE0FFF750FF06E0C8684207FCD500F0BC
+:1034C0007EF88C49086088F31088FF21A86802689C
+:1034D0005162BDE8F183F8B5844CA160CA22096845
+:1034E0004A6253224A62824A136843F020031360FF
+:1034F000136803F00703C3F10403237095682D0CD0
+:1035000005F07F056D1C6570EDB29268C2F30E0286
+:10351000521C628092B2521E6A43A2F5A072DA4037
+:103520004FF6FF739A422CBFA380A280724A1368A1
+:1035300043F400231360714B1D6845F400251D60A2
+:1035400048BB6948674E0123837018254FF0FF334D
+:10355000436000235FFA83FC06F10C0715FB0CFCAB
+:103560004FF0000E07F80CE05B1CDFB2062FF1DB1A
+:1035700006230370886820F48060886000F01FF8DC
+:10358000D0600320FFF7A8F9A1680868826842F4B8
+:103590008042826005E0C868410544BF0320FFF710
+:1035A00090F9A1680A68FF205062002203210320DD
+:1035B000FFF73CF9BDE8F2400320FFF754B9C868B3
+:1035C00000F0800060F49060C8604FF40020704705
+:1035D000F8B50746EFF3108472B60320FFF74EF9F3
+:1035E000424DAE683068CA2141623A465321416279
+:1035F000182043494243895C02291BD100213846E7
+:10360000FFF764FE3848017806290ED13068384942
+:103610000A68530500F018F821F480618160C168E0
+:103620004A07FCD500F016F804E04078884218BF3D
+:10363000FFF791FEA9680A68FF2050620320FFF798
+:1036400012F984F31088F1BD02D5C1684A07FCD491
+:1036500081687047C16801F0800161F49061C160C8
+:103660004FF40020234908600320FFF735B92DE906
+:10367000F04180460F46424618201A4942438C18B2
+:10368000207B022804BF4046FFF7A2FFEFF310851E
+:1036900072B60320FFF7F2F8144EB0680068CA2132
+:1036A00041625321416202202073A7606760404657
+:1036B000FFF7A7FD0C490A784978914202D0FFF73D
+:1036C0004AFE02E0A168081AA060FF20B1680A68FB
+:1036D00050620320FFF7C7F885F31088BDE8F0813A
+:1036E0002828004068010020DC030020A8030020F7
+:1036F000082800400C0800580008005880080058AE
+:103700007401002010470000564900E0564981B07E
+:103710000A6802430A60096808400090009801B0F6
+:10372000704718B585B068461421FEF729FE0320BE
+:1037300001904FF460410024009102940120FFF7B2
+:10374000E3FF00F097F8474C2068400840002060F5
+:10375000182100910220FFF7D7FF69464348FEF782
+:1037600013FE206820F002002060FFF7C5F9FFF784
+:10377000C9F9FFF7CDF900F011F806B010BD00B59A
+:1037800087B068460FF208211C2200F0C3FC00F04D
+:1037900072FA684600F010FD07B000BDF0B585B0C4
+:1037A00068461421FEF7ECFD0026002500240021C8
+:1037B0000FF2CC0000EBC102907988B11368B3F12D
+:1037C000904F08D0294FBB4208D0294FBB4204BFBD
+:1037D0009088044304E09088064301E09088054304
+:1037E000491C2229E4DB00200290012103200390E0
+:1037F0000191B0B270B100900120FFF785FF012068
+:10380000FFF784FF00F036F80022B1B24FF090408D
+:10381000FEF778FEA8B280B100900220FFF774FF97
+:103820000220FFF773FF114E69463046FEF7ACFDEC
+:103830000022A9B23046FEF765FEA0B280B100902A
+:103840000420FFF761FF0420FFF760FF084D694681
+:103850002846FEF799FD0022A1B22846FEF752FE47
+:1038600005B0F0BD4C0000584C0100580004004861
+:103870000008004869464FF09040FEF785BD000003
+:1038800000000048010000000000004801000000A6
+:103890000000004801000000000000480100000096
+:1038A0000000004801000000000000480100000086
+:1038B0000000004801000000000000480100000076
+:1038C0000000004801000000000000480100000066
+:1038D0000000004801000000000000480100000056
+:1038E0000000004801000000000000480100000046
+:1038F0000000004801000000000000480100000036
+:103900000000004801000000000000480100000025
+:103910000000004801000000000000480100000015
+:103920000000004801000000000000480100000005
+:1039300000000048010000000000004801000000F5
+:1039400000000048010000000000004801000000E5
+:1039500000000048010000000000004801000000D5
+:1039600000000048010000000000004801000000C5
+:1039700000000048010000000000004801000000B5
+:1039800000000048010000000000004801000000A5
+:103990000000000000000000000000008038000867
+:1039A000248000202880002022040400444981B0A3
+:1039B0000A6802430A60096808400090009801B054
+:1039C000704778B585B0044668461421FEF7D8FCE8
+:1039D0000220FFF7EBFF00F010F8009501200190A6
+:1039E0000021022003900291694656F82400FEF758
+:1039F000CBFC00F008F806B070BD0FF2D400314ED9
+:103A000030F81450704756F8240000222946FEF77B
+:103A100079BD0FF2BC012B4B31F8101053F8200088
+:103A20000122FEF76FBD0FF2A801264B31F81010EE
+:103A300053F820000022FEF765BDF0B585B00546BD
+:103A40000C4668461421FEF79BFC2DB1012D08BFE2
+:103A5000102002D0022D02D10120FFF7A7FF200085
+:103A6000194E0FF274070DD137F8150000900021A0
+:103A70000191012002900221039100F01BF8012026
+:103A8000FEF781FE012C13D137F8150000900121BB
+:103A90000E480190029100F00DF80FF24400445DD1
+:103AA00000220F2160B2FEF7C1FE60B2FEF7DBFE1E
+:103AB00005B0F0BD694656F82500FEF765BC00006C
+:103AC0004C000058040000201000002000002110CD
+:103AD0002000010002000000010010004000000072
+:103AE000060A170000F0E4BB71487249016001F159
+:103AF0002002426001F13002826001F13C02026268
+:103B000001F14402C26001F14C02026101F168025C
+:103B1000426101F16C0282617831C16100F0DABB6F
+:103B200038B50446644D05F1100000F0D4F8604942
+:103B30004868A1680160E168C160456005F1100155
+:103B4000816000F0E3FB5D4837E080B558494A6882
+:103B500013680120187200F0DFFB002002BD38B5A9
+:103B6000564C554D07E0694605F1100000F0D5F8B8
+:103B700000982168884705F1100000F0AFF8002890
+:103B8000F1D031BD80B54A494A68D1680220087237
+:103B900000F0C7FB002002BD48484168084738B51F
+:103BA0000446474D284600F096F84148C068A16891
+:103BB0000160456000F0BEFB424821680160616819
+:103BC0004160002032BD80B53949CA6813681020B1
+:103BD000187200F0B5FB002002BD3549CA683949AA
+:103BE00010680B68184738B5364C354D06E0694605
+:103BF000284600F092F8009861688847284600F04F
+:103C00006DF80028F3D031BD38B504462E4D284656
+:103C100000F061F82D4800F05EF825480069A168C1
+:103C20008160E168C160056121680160616841608F
+:103C3000216941616169816131BD80B501462348D7
+:103C400000F055F8BDE802400FF2050000F088BB17
+:103C500038B5174C1D4D08E06946284600F05DF860
+:103C600000992069006900F042F8284600F036F813
+:103C70000028F1D031BD10B5154C204600F02BF8CE
+:103C80000B4841690C60BDE8104000F07DBB1CB5DD
+:103C90000F4C06E06946204600F03FF8009800F01F
+:103CA00019F8204600F01AF80028F3D013BD0000E0
+:103CB00000800020C08A0020A08A0020CC030020C1
+:103CC000B88A0020D4030020448B0020C4030020C5
+:103CD0004C8B00207047006040607047EFF310810C
+:103CE00072B6026882420CBF0120002012E0EFF39E
+:103CF000108272B6086043684B604160486801609A
+:103D000019E0EFF3108172B6436802681A604268E6
+:103D10000068426081F31088704710B5EFF310849B
+:103D200072B602680A600068FFE7FFF7EAFF84F3F3
+:103D3000108810BD086082F31088704710B590B0ED
+:103D400004A80FF27C31DFF85443302200F0E2F98E
+:103D50002068DFF84C434FF6FC7101EA8001DFF880
+:103D60004403029001F1005100F5867001F5004115
+:103D70000390E1600FF2CD200FF2B121019000918C
+:103D80006846FFF7CDFE01210220FFF7FBF9012174
+:103D90000220FFF7EAF90020E070A07004A800F00C
+:103DA00003FA0FF2051200210820FFF77AF8BE4A45
+:103DB00000210120FFF775F80FF299020021102071
+:103DC000FFF76FF8B94A00210220FFF76AF8B84AF6
+:103DD00000210420FFF765F8012060700020A0603A
+:103DE00004F11800FFF777FFFEF786FC04F11000DE
+:103DF00060600020207001220FF2FD0304F1100129
+:103E0000FDF7CAFC10B010BD80B5A54A917831B15C
+:103E1000002090700120BDE80240FFF763B8014622
+:103E200002F1180006E110B59D4CE07830B9012090
+:103E3000FFF7F9FD0121E170002105E00120FFF706
+:103E4000E8FD0020E0700121BDE810400220FFF7EE
+:103E50008CB9000038B5EFF31084914D68780128D3
+:103E600021D10021697005F1180005F10801FFF763
+:103E700054FFE878A0B9A8680FF27D13017A0229EF
+:103E800072B607BFB0F80B20521D827AD21C00F127
+:103E9000080192B20020FDF788FC84F3108831BD40
+:103EA000BDE83140A8E031BD10B5824CB4F809003E
+:103EB0004FF66051401A02D0401E04D007E0204661
+:103EC00000F078FA10E0204600F0AFFA0CE04FF670
+:103ED0006250A0814220A0720020A0730120E072F5
+:103EE000212020720E20607221467348FFF7FFFEEA
+:103EF000BDE81040A2E00000F8B5694D69682A7875
+:103F0000002400201AB1022A64D013D358E00978A3
+:103F1000012905D0022907D0102918BF202907D16F
+:103F20000120287003244BE001202870042447E07E
+:103F3000012445E00E78E868022E11D0102E02D040
+:103F4000202E03D01CE0CC78C0681BE0CC78594808
+:103F500005F1100100F108070A6840F8082F18E081
+:103F60004068CA780979C36802EB012403F10807A5
+:103F7000052205F11001384600F0BCF8052009E0E3
+:103F8000CC784068016805F1100001F1080701686C
+:103F9000396004206F60A1B211B1022129700FE0D5
+:103FA000022E25D0102E1DD0202E1ED00021012043
+:103FB000FEF784FF002005F11001287001246960DC
+:103FC000A2B201B069683D4BBDE8F0400144002059
+:103FD000FDF7E2BB087802280AD0102802D020287A
+:103FE00003D0E3E700210220E2E700210820DFE719
+:103FF00000210420DCE700001CB5294C0120607082
+:10400000E0680169A0688A68904205D3C9681144D4
+:10401000884238BFFFF711FE04F11800FFF75EFE7B
+:1040200010B9BDE81C4009E013BD000080B5014691
+:10403000DFF88400FFF75BFEBDE80440002110209C
+:10404000FEF73CBF704770B51446144A144E126810
+:104050001D460123B3704FF6FC7303EA820303F19C
+:10406000005303F50043DA681668A6F80900F172F8
+:104070000A46214606F10C0000F03CF80021002021
+:10408000FFF7A1FD0120FEF735FF314605F10800DD
+:10409000B278BDE87040D21C00F02CB83C4000580B
+:1040A000880300208C8800204B3B0008C73B000899
+:1040B000853B00085C000020A0030020F93E0008BA
+:1040C00000000000000000000000000000000000F0
+:1040D0000000000044000800400508013A799C00F7
+:1040E000F4010000FFFFFFFF480101000000000095
+:1040F0007047704762B38B0708D0521E11F8013B1E
+:1041000000F8013B00F024808B07F6D1830740F0D4
+:10411000208000BF103A07D330B4B1E83810103A0D
+:10412000A0E83810F9D230BC530724BFB1E808101A
+:10413000A0E8081044BF51F8043B40F8043BD20704
+:1041400024BF31F8022B20F8022B44BF0B780370F8
+:104150007047121F17D35B0009D151F8043B20F8B8
+:10416000023B1B0C121F20F8023BF6D20BE051F869
+:10417000043B00F8013B1B0A20F8023B1B0C121FFA
+:1041800000F8013BF3D238BF121D521E24BF11F8B4
+:10419000013B00F8013BF8D870470000FFF753FFE0
+:1041A0009DF80E0005B000BDF8B500F10C026B469D
+:1041B00021214FF66640F1E7F8B500F10C026B469D
+:1041C0000F214FF66840E9E7C0680840884201D1F6
+:1041D0000120704700207047C0690840884201D123
+:1041E000012070470020704710B56A4C022120461C
+:1041F000FFF7F2FF38B16068C043810703D5FFF7CE
+:10420000F2FC022018E001212046FFF7E5FF38B15B
+:104210006068C043C10703D5FFF7A1FC01200BE094
+:1042200008212046FFF7D8FF38B16068C043010776
+:1042300003D5FFF72CFD0820A06010BD10B5554C2C
+:1042400000F033F818B96068C043810306D400F069
+:104250002CF830B96068C043810302D5BDE8104036
+:1042600077E0082100F022F870B96068C0430103CC
+:104270000AD56068484940F40020606008688047BB
+:104280004FF40020A06010BD202100F00FF858B9B5
+:104290006068C043810207D5606840F40010606028
+:1042A000BDE81040FFF778BC10BD022120468BE727
+:1042B0003A48016841F4007101603948026842F4EB
+:1042C0000072026040BF20BF3648016841F40041DF
+:1042D0000160704780B53448016841F48011016085
+:1042E000006800F48010009000982A48016841F0AE
+:1042F00001010160026842F4803202602C20FEF766
+:10430000B2FABDE802402D20FEF7ADBA2748016899
+:10431000490849000160704725494FF48030086022
+:10432000704722484FF400114160016821F40011E8
+:10433000016070471D48016821F00201016070476B
+:104340001A484FF400314160016821F400310160E6
+:1043500070471648016841F400310160FFF73DBC29
+:1043600038B504460B4D08212846FFF72DFF30B124
+:1043700009480460686820F40020686031BDA047E7
+:104380004FF40021A96031BD0848016821F00801FF
+:1043900001607047000C0058E4030020D408005866
+:1043A000200800580C04005850000058040C005815
+:1043B000080C005870B5EFF31081027B012A02D07F
+:1043C000022A07D00DE000F028F8137800F01FF85B
+:1043D00014700CE000F021F8138800F018F8148035
+:1043E00005E000F01AF8136800F011F8146081F38A
+:1043F0001088212101720E214172042181724FF631
+:1044000060518181002181730121C17270BD2646F6
+:1044100023EA040435402C43704772B6D0F81120CB
+:10442000D0F80D40D0F81550704781B0017B0129BC
+:1044300002D0022904D008E0D0F80D10097807E076
+:10444000D0F80D100A88009203E0D0F80D1009682A
+:1044500000910E21417221220821817202724FF6D1
+:10446000615181810121C17200218173009A40F85C
+:104470000F2F01B07047000000EB8100404AD0F8D8
+:104480008010914201D0012070470020704742F413
+:10449000806240F82120704780B500F097F83948D5
+:1044A000092181610168C908C90041F0030100F0D8
+:1044B00026F861E000F092B810B500F087F8324CB1
+:1044C00000F04CF80028FBD1042100F048F828B98E
+:1044D0002E480068010403D500F043F800F05CF8B2
+:1044E0000022032100F03FF826480168C908C900EE
+:1044F00041F0020100F003F8016030BF10BD01601F
+:104500002348016841F00401704710B51E4C00F0CB
+:1045100028F800F023F80028FBD14FF0B040816864
+:1045200001F00C01042911D1016841F480310160CE
+:1045300001688903FCD581688908890041F002017E
+:104540008160816801F00C010829FAD10022032161
+:1045500000F009F8BDE8104000F040B80321204603
+:104560008AE700220421204691E780B500F02EF86A
+:104570000748016821F00401016030BF01BD00005F
+:1045800000040080000400580014005888040058FB
+:1045900010ED00E000F022B84FF0B040016841F4A7
+:1045A0008071016001684905FCD58168890889002E
+:1045B00041F001018160416A890889004162816896
+:1045C00001F00C010429FAD170470000024801688B
+:1045D00021F002010160704710E000E0024801682C
+:1045E00041F002010160704710E000E019E050F86E
+:1045F000042BD30744BFA9F101039A18091F002314
+:10460000042942F8043BF9D25FEA817C134604D5C1
+:104610004FF0000CA2F800C09B1CC90744BF00214A
+:10462000197050F8041B0029E1D170477047FEE76C
+:10463000FEE7FEE7FEE770477047704700F014B8EA
+:104640000248FBF77CBE0248FCF77DBFF801002062
+:10465000040300200120FDF75CBFFEF7ECBEFFF76E
+:10466000EDBDFFF7C1BD000002490A6888688218E5
+:104670000A6070474400002030B501688468421821
+:10468000416802EB5103C9070BD54C4409E012F90C
+:10469000011B12F8015B002904F8015B05D5491CD8
+:1046A000F9D19A42F3D10C3030BD491EF1D5F8E76B
+:1046B00010B500F013F802000023DB43002410685B
+:1046C000984203D011000220ABBE1460506898429B
+:1046D00003D0111D0220ABBE546010BD01487047CD
+:1046E000000000005400002010B50749794418313B
+:1046F000064C7C44163404E00A68081D11448847BF
+:104700000146A142F8D110BD2C000000600000005D
+:104710004EF68851CEF20001086840F4700008603F
+:10472000BFF34F8FBFF36F8F4FF00070E1EE100AB1
+:1047300070470000B9FEFFFF940300005C000020FA
+:10474000940A00002C800020000000002DFFFFFFD5
+:10475000940100005A000000040000201DFFFFFF2C
+:10476000B1010000040000002480002000000000CF
+:104770000000000000000000000000000100000038
+:1047800002000000030000000400000000F00DF82B
+:10479000002801D0FFF7A8FFAFF300800020AFF39F
+:1047A0000080FDF7DAFE00F002F80120704700F00B
+:1047B00001B800000746384600F002F8FBE70000A9
+:1047C00080B5FFF775FF024A11001820ABBEFBE76A
+:1047D000260002006B45000895450008B944000812
+:1047E0000B45000899440008B5440008014880477B
+:1047F0000148004715290008FD470008AFF3008075
+:10480000FFF786FFFFF7C2FFFFF7FEBFFFF7FEBF10
+:10481000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFCC
+:10482000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFBC
+:10483000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFAC
+:10484000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF9C
+:10485000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF8C
+:10486000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF7C
+:10487000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF6C
+:10488000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF5C
+:10489000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF4C
+:1048A000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF3C
+:1048B000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF2C
+:1048C000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF1C
+:1048D000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF0C
+:1048E000FFF7FEBF0B00040048000400480004006E
+:1048F00048FD00044800100048FD000048EC00F8A6
+:10490000FFF0000010FD000001FC0002093D00F86E
+:03491000FFF800AD
+:04000005080047FDAB
+:00000001FF
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/app_common.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/app_common.h
new file mode 100644
index 000000000..4defc5d7a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/app_common.h
@@ -0,0 +1,114 @@
+/**
+ ******************************************************************************
+  * File Name          : app_common.h
+  * Description        : App Common application configuration file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_COMMON_H
+#define APP_COMMON_H
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "app_conf.h"
+
+  /* -------------------------------- *
+   *  Basic definitions               *
+   * -------------------------------- */
+
+#undef NULL
+#define NULL                    0
+
+#undef FALSE
+#define FALSE                   0
+
+#undef TRUE
+#define TRUE                    (!0)
+
+  /* -------------------------------- *
+   *  Critical Section definition     *
+   * -------------------------------- */
+#define BACKUP_PRIMASK()    uint32_t primask_bit= __get_PRIMASK()
+#define DISABLE_IRQ()       __disable_irq()
+#define RESTORE_PRIMASK()   __set_PRIMASK(primask_bit)
+
+  /* -------------------------------- *
+   *  Macro delimiters                *
+   * -------------------------------- */
+
+#define M_BEGIN     do {
+
+#define M_END       } while(0)
+
+  /* -------------------------------- *
+   *  Some useful macro definitions   *
+   * -------------------------------- */
+
+#define MAX( x, y )          (((x)>(y))?(x):(y))
+
+#define MIN( x, y )          (((x)<(y))?(x):(y))
+
+#define MODINC( a, m )       M_BEGIN  (a)++;  if ((a)>=(m)) (a)=0;  M_END
+
+#define MODDEC( a, m )       M_BEGIN  if ((a)==0) (a)=(m);  (a)--;  M_END
+
+#define MODADD( a, b, m )    M_BEGIN  (a)+=(b);  if ((a)>=(m)) (a)-=(m);  M_END
+
+#define MODSUB( a, b, m )    MODADD( a, (m)-(b), m )
+
+#define PAUSE( t )           M_BEGIN \
+                               __IO int _i; \
+                               for ( _i = t; _i > 0; _i -- ); \
+                             M_END
+
+#define DIVF( x, y )         ((x)/(y))
+
+#define DIVC( x, y )         (((x)+(y)-1)/(y))
+
+#define DIVR( x, y )         (((x)+((y)/2))/(y))
+
+#define SHRR( x, n )         ((((x)>>((n)-1))+1)>>1)
+
+#define BITN( w, n )         (((w)[(n)/32] >> ((n)%32)) & 1)
+
+#define BITNSET( w, n, b )   M_BEGIN (w)[(n)/32] |= ((U32)(b))<<((n)%32); M_END
+
+  /* -------------------------------- *
+   *  Compiler                         *
+   * -------------------------------- */
+#define PLACE_IN_SECTION( __x__ )  __attribute__((section (__x__)))
+
+#ifdef WIN32
+#define ALIGN(n)
+#else
+#define ALIGN(n)             __attribute__((aligned(n)))
+#endif
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*APP_COMMON_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/app_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/app_conf.h
new file mode 100644
index 000000000..f148c4d55
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/app_conf.h
@@ -0,0 +1,483 @@
+/**
+ ******************************************************************************
+  * File Name          : app_conf.h
+  * Description        : Application configuration file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_CONF_H
+#define APP_CONF_H
+
+#include "hw.h"
+#include "hw_conf.h"
+#include "hw_if.h"
+
+/******************************************************************************
+ * Application Config
+ ******************************************************************************/
+
+/**
+*   Identity root key used to derive LTK and CSRK
+*/
+#define CFG_BLE_IRK     {0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0,0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0}
+
+/**
+* Encryption root key used to derive LTK and CSRK
+*/
+#define CFG_BLE_ERK     {0xfe,0xdc,0xba,0x09,0x87,0x65,0x43,0x21,0xfe,0xdc,0xba,0x09,0x87,0x65,0x43,0x21}
+
+/* USER CODE BEGIN Generic_Parameters */
+/**
+ * SMPS supply
+ * SMPS not used when Set to 0
+ * SMPS used when Set to 1
+ */
+#define CFG_USE_SMPS    1
+/* USER CODE END Generic_Parameters */
+
+/**< specific parameters */
+/*****************************************************/
+#ifdef LITTLE_DORY
+#define PUSH_BUTTON_SW1_EXTI_IRQHandler                         EXTI0_IRQHandler
+#else
+#define PUSH_BUTTON_SW1_EXTI_IRQHandler                         EXTI4_IRQHandler
+#endif
+
+/******************************************************************************
+ * Information Table
+ *
+  * Version
+  * [0:3]   = Build - 0: Untracked - 15:Released - x: Tracked version
+  * [4:7]   = branch - 0: Mass Market - x: ...
+  * [8:15]  = Subversion
+  * [16:23] = Version minor
+  * [24:31] = Version major
+  *
+ ******************************************************************************/
+#define CFG_FW_MAJOR_VERSION      (0)
+#define CFG_FW_MINOR_VERSION      (0)
+#define CFG_FW_SUBVERSION         (1)
+#define CFG_FW_BRANCH             (0)
+#define CFG_FW_BUILD              (0)
+
+/******************************************************************************
+ * BLE Stack
+ ******************************************************************************/
+/**
+ * Maximum number of simultaneous connections that the device will support.
+ * Valid values are from 1 to 8
+ */
+#define CFG_BLE_NUM_LINK            8
+
+/**
+ * Maximum number of Services that can be stored in the GATT database.
+ * Note that the GAP and GATT services are automatically added so this parameter should be 2 plus the number of user services
+ */
+#define CFG_BLE_NUM_GATT_SERVICES   8
+
+/**
+ * Maximum number of Attributes
+ * (i.e. the number of characteristic + the number of characteristic values + the number of descriptors, excluding the services)
+ * that can be stored in the GATT database.
+ * Note that certain characteristics and relative descriptors are added automatically during device initialization
+ * so this parameters should be 9 plus the number of user Attributes
+ */
+#define CFG_BLE_NUM_GATT_ATTRIBUTES 68
+
+/**
+ * Maximum supported ATT_MTU size
+ */
+#define CFG_BLE_MAX_ATT_MTU             (156)
+
+/**
+ * Size of the storage area for Attribute values
+ *  This value depends on the number of attributes used by application. In particular the sum of the following quantities (in octets) should be made for each attribute:
+ *  - attribute value length
+ *  - 5, if UUID is 16 bit; 19, if UUID is 128 bit
+ *  - 2, if server configuration descriptor is used
+ *  - 2*DTM_NUM_LINK, if client configuration descriptor is used
+ *  - 2, if extended properties is used
+ *  The total amount of memory needed is the sum of the above quantities for each attribute.
+ */
+#define CFG_BLE_ATT_VALUE_ARRAY_SIZE    (1344)
+
+/**
+ * Prepare Write List size in terms of number of packet with ATT_MTU=23 bytes
+ */
+#define CFG_BLE_PREPARE_WRITE_LIST_SIZE         ( 0x3A )
+
+/**
+ * Number of allocated memory blocks
+ */
+#define CFG_BLE_MBLOCK_COUNT            ( 0x79 )
+
+/**
+ * Enable or disable the Extended Packet length feature. Valid values are 0 or 1.
+ */
+#define CFG_BLE_DATA_LENGTH_EXTENSION   1
+
+/**
+ * Sleep clock accuracy in Slave mode (ppm value)
+ */
+#define CFG_BLE_SLAVE_SCA   500
+
+/**
+ * Sleep clock accuracy in Master mode
+ * 0 : 251 ppm to 500 ppm
+ * 1 : 151 ppm to 250 ppm
+ * 2 : 101 ppm to 150 ppm
+ * 3 : 76 ppm to 100 ppm
+ * 4 : 51 ppm to 75 ppm
+ * 5 : 31 ppm to 50 ppm
+ * 6 : 21 ppm to 30 ppm
+ * 7 : 0 ppm to 20 ppm
+ */
+#define CFG_BLE_MASTER_SCA   0
+
+/**
+ *  Source for the 32 kHz slow speed clock
+ *  1 : internal RO
+ *  0 : external crystal ( no calibration )
+ */
+#define CFG_BLE_LSE_SOURCE  0
+
+/**
+ * Start up time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us)
+ */
+#define CFG_BLE_HSE_STARTUP_TIME  0x148
+
+/**
+ * Maximum duration of the connection event when the device is in Slave mode in units of 625/256 us (~2.44 us)
+ */
+#define CFG_BLE_MAX_CONN_EVENT_LENGTH  ( 0xFFFFFFFF )
+
+/**
+ * Viterbi Mode
+ * 1 : enabled
+ * 0 : disabled
+ */
+#define CFG_BLE_VITERBI_MODE  1
+
+/**
+ *  LL Only Mode
+ *  1 : LL Only
+ *  0 : LL + Host
+ */
+#define CFG_BLE_LL_ONLY  0
+/******************************************************************************
+ * Transport Layer
+ ******************************************************************************/
+/**
+ * Queue length of BLE Event
+ * This parameter defines the number of asynchronous events that can be stored in the HCI layer before
+ * being reported to the application. When a command is sent to the BLE core coprocessor, the HCI layer
+ * is waiting for the event with the Num_HCI_Command_Packets set to 1. The receive queue shall be large
+ * enough to store all asynchronous events received in between.
+ * When CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE is set to 27, this allow to store three 255 bytes long asynchronous events
+ * between the HCI command and its event.
+ * This parameter depends on the value given to CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE. When the queue size is to small,
+ * the system may hang if the queue is full with asynchronous events and the HCI layer is still waiting
+ * for a CC/CS event, In that case, the notification TL_BLE_HCI_ToNot() is called to indicate
+ * to the application a HCI command did not receive its command event within 30s (Default HCI Timeout).
+ */
+#define CFG_TLBLE_EVT_QUEUE_LENGTH 5
+/**
+ * This parameter should be set to fit most events received by the HCI layer. It defines the buffer size of each element
+ * allocated in the queue of received events and can be used to optimize the amount of RAM allocated by the Memory Manager.
+ * It should not exceed 255 which is the maximum HCI packet payload size (a greater value is a lost of memory as it will
+ * never be used)
+ * It shall be at least 4 to receive the command status event in one frame.
+ * The default value is set to 27 to allow receiving an event of MTU size in a single buffer. This value maybe reduced
+ * further depending on the application.
+ *
+ */
+#define CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE 255   /**< Set to 255 with the memory manager and the mailbox */
+
+#define TL_BLE_EVENT_FRAME_SIZE ( TL_EVT_HDR_SIZE + CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE )
+/******************************************************************************
+ * UART interfaces
+ ******************************************************************************/
+
+/**
+ * Select UART interfaces
+ */
+#define CFG_UART_GUI          hw_uart1
+#define CFG_DEBUG_TRACE_UART    
+/******************************************************************************
+ * USB interface
+ ******************************************************************************/
+
+/**
+ * Enable/Disable USB interface
+ */
+#define CFG_USB_INTERFACE_ENABLE    0
+
+/******************************************************************************
+ * Low Power
+ ******************************************************************************/
+/**
+ *  When set to 1, the low power mode is enable
+ *  When set to 0, the device stays in RUN mode
+ */
+#define CFG_LPM_SUPPORTED    1
+
+/******************************************************************************
+ * Timer Server
+ ******************************************************************************/
+/**
+ *  CFG_RTC_WUCKSEL_DIVIDER:  This sets the RTCCLK divider to the wakeup timer.
+ *  The higher is the value, the better is the power consumption and the accuracy of the timerserver
+ *  The lower is the value, the finest is the granularity
+ *
+ *  CFG_RTC_ASYNCH_PRESCALER: This sets the asynchronous prescaler of the RTC. It should as high as possible ( to ouput
+ *  clock as low as possible) but the output clock should be equal or higher frequency compare to the clock feeding
+ *  the wakeup timer. A lower clock speed would impact the accuracy of the timer server.
+ *
+ *  CFG_RTC_SYNCH_PRESCALER: This sets the synchronous prescaler of the RTC.
+ *  When the 1Hz calendar clock is required, it shall be sets according to other settings
+ *  When the 1Hz calendar clock is not needed, CFG_RTC_SYNCH_PRESCALER should be set to 0x7FFF (MAX VALUE)
+ *
+ *  CFG_RTCCLK_DIVIDER_CONF:
+ *  Shall be set to either 0,2,4,8,16
+ *  When set to either 2,4,8,16, the 1Hhz calendar is supported
+ *  When set to 0, the user sets its own configuration
+ *
+ *  The following settings are computed with LSI as input to the RTC
+ */
+#define CFG_RTCCLK_DIVIDER_CONF 0
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 0)
+/**
+ * Custom configuration
+ * It does not support 1Hz calendar
+ * It divides the RTC CLK by 16
+ */
+#define CFG_RTCCLK_DIV  (16)
+#define CFG_RTC_WUCKSEL_DIVIDER (0)
+#define CFG_RTC_ASYNCH_PRESCALER (CFG_RTCCLK_DIV - 1)
+#define CFG_RTC_SYNCH_PRESCALER (0x7FFF)
+
+#else
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 2)
+/**
+ * It divides the RTC CLK by 2
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (3)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 4)
+/**
+ * It divides the RTC CLK by 4
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (2)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 8)
+/**
+ * It divides the RTC CLK by 8
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (1)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 16)
+/**
+ * It divides the RTC CLK by 16
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (0)
+#endif
+
+#define CFG_RTCCLK_DIV              CFG_RTCCLK_DIVIDER_CONF
+#define CFG_RTC_ASYNCH_PRESCALER    (CFG_RTCCLK_DIV - 1)
+#define CFG_RTC_SYNCH_PRESCALER     (DIVR( LSE_VALUE, (CFG_RTC_ASYNCH_PRESCALER+1) ) - 1 )
+
+#endif
+
+/** tick timer value in us */
+#define CFG_TS_TICK_VAL           DIVR( (CFG_RTCCLK_DIV * 1000000), LSE_VALUE )
+
+typedef enum
+{
+    CFG_TIM_PROC_ID_ISR,
+} CFG_TimProcID_t;
+
+/******************************************************************************
+ * Debug
+ ******************************************************************************/
+/**
+ * When set, this resets some hw resources to set the device in the same state than the power up
+ * The FW resets only register that may prevent the FW to run properly
+ *
+ * This shall be set to 0 in a final product
+ *
+ */
+#define CFG_HW_RESET_BY_FW         1
+
+/**
+ * keep debugger enabled while in any low power mode when set to 1
+ * should be set to 0 in production
+ */
+#define CFG_DEBUGGER_SUPPORTED    0
+
+/**
+ * When set to 1, the traces are enabled in the BLE services
+ */
+#define CFG_DEBUG_BLE_TRACE     0
+
+/**
+ * Enable or Disable traces in application
+ */
+#define CFG_DEBUG_APP_TRACE     0
+
+#if (CFG_DEBUG_APP_TRACE != 0)
+#define APP_DBG_MSG                 PRINT_MESG_DBG
+#else
+#define APP_DBG_MSG                 PRINT_NO_MESG
+#endif
+
+#if ( (CFG_DEBUG_BLE_TRACE != 0) || (CFG_DEBUG_APP_TRACE != 0) )
+#define CFG_DEBUG_TRACE             1
+#endif
+
+#if (CFG_DEBUG_TRACE != 0)
+#undef CFG_LPM_SUPPORTED
+#undef CFG_DEBUGGER_SUPPORTED
+#define CFG_LPM_SUPPORTED         0
+#define CFG_DEBUGGER_SUPPORTED      1
+#endif
+
+/**
+ * When CFG_DEBUG_TRACE_FULL is set to 1, the trace are output with the API name, the file name and the line number
+ * When CFG_DEBUG_TRACE_LIGHT is set to 1, only the debug message is output
+ *
+ * When both are set to 0, no trace are output
+ * When both are set to 1,  CFG_DEBUG_TRACE_FULL is selected
+ */
+#define CFG_DEBUG_TRACE_LIGHT     0
+#define CFG_DEBUG_TRACE_FULL      0
+
+#if (( CFG_DEBUG_TRACE != 0 ) && ( CFG_DEBUG_TRACE_LIGHT == 0 ) && (CFG_DEBUG_TRACE_FULL == 0))
+#undef CFG_DEBUG_TRACE_FULL
+#undef CFG_DEBUG_TRACE_LIGHT
+#define CFG_DEBUG_TRACE_FULL      0
+#define CFG_DEBUG_TRACE_LIGHT     1
+#endif
+
+#if ( CFG_DEBUG_TRACE == 0 )
+#undef CFG_DEBUG_TRACE_FULL
+#undef CFG_DEBUG_TRACE_LIGHT
+#define CFG_DEBUG_TRACE_FULL      0
+#define CFG_DEBUG_TRACE_LIGHT     0
+#endif
+
+/**
+ * When not set, the traces is looping on sending the trace over UART
+ */
+#define DBG_TRACE_USE_CIRCULAR_QUEUE 1
+
+/**
+ * max buffer Size to queue data traces and max data trace allowed.
+ * Only Used if DBG_TRACE_USE_CIRCULAR_QUEUE is defined
+ */
+#define DBG_TRACE_MSG_QUEUE_SIZE 4096
+#define MAX_DBG_TRACE_MSG_SIZE 1024
+
+/* USER CODE BEGIN Defines */
+#define CFG_LED_SUPPORTED         1
+#define CFG_BUTTON_SUPPORTED      1
+/* USER CODE END Defines */
+
+/******************************************************************************
+ * Scheduler
+ ******************************************************************************/
+
+/**
+ * These are the lists of task id registered to the scheduler
+ * Each task id shall be in the range [0:31]
+ * This mechanism allows to implement a generic code in the API TL_BLE_HCI_StatusNot() to comply with
+ * the requirement that a HCI/ACI command shall never be sent if there is already one pending
+ */
+
+/**< Add in that list all tasks that may send a ACI/HCI command */
+typedef enum
+{
+  CFG_TASK_BLE_HCI_CMD_ID,
+  CFG_TASK_SYS_HCI_CMD_ID,
+  CFG_TASK_HCI_ACL_DATA_ID,
+  CFG_TASK_SYS_LOCAL_CMD_ID,
+  CFG_TASK_TX_TO_HOST_ID,
+/* USER CODE BEGIN CFG_Task_Id_With_HCI_Cmd_t */
+
+/* USER CODE END CFG_Task_Id_With_HCI_Cmd_t */
+    CFG_LAST_TASK_ID_WITH_HCICMD,                                               /**< Shall be LAST in the list */
+} CFG_Task_Id_With_HCI_Cmd_t;
+
+/**< Add in that list all tasks that never send a ACI/HCI command */
+typedef enum
+{
+    CFG_FIRST_TASK_ID_WITH_NO_HCICMD = CFG_LAST_TASK_ID_WITH_HCICMD - 1,        /**< Shall be FIRST in the list */
+    CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID,
+/* USER CODE BEGIN CFG_Task_Id_With_NO_HCI_Cmd_t */
+
+/* USER CODE END CFG_Task_Id_With_NO_HCI_Cmd_t */
+    CFG_LAST_TASK_ID_WITHO_NO_HCICMD                                            /**< Shall be LAST in the list */
+} CFG_Task_Id_With_NO_HCI_Cmd_t;
+#define CFG_TASK_NBR    CFG_LAST_TASK_ID_WITHO_NO_HCICMD
+
+/**
+ * This is the list of priority required by the application
+ * Each Id shall be in the range 0..31
+ */
+typedef enum
+{
+    CFG_SCH_PRIO_0,
+    CFG_PRIO_NBR,
+} CFG_SCH_Prio_Id_t;
+
+/**
+ * This is a bit mapping over 32bits listing all events id supported in the application
+ */
+typedef enum
+{
+    CFG_IDLEEVT_SYSTEM_HCI_CMD_EVT_RSP_ID,
+} CFG_IdleEvt_Id_t;
+
+/******************************************************************************
+ * LOW POWER
+ ******************************************************************************/
+/**
+ * Supported requester to the MCU Low Power Manager - can be increased up  to 32
+ * It lits a bit mapping of all user of the Low Power Manager
+ */
+typedef enum
+{
+    CFG_LPM_APP,
+    CFG_LPM_APP_BLE,
+  /* USER CODE BEGIN CFG_LPM_Id_t */
+
+  /* USER CODE END CFG_LPM_Id_t */
+} CFG_LPM_Id_t;
+
+/******************************************************************************
+ * OTP manager
+ ******************************************************************************/
+#define CFG_OTP_BASE_ADDRESS    OTP_AREA_BASE
+
+#define CFG_OTP_END_ADRESS      OTP_AREA_END_ADDR
+
+#endif /*APP_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/app_debug.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/app_debug.h
new file mode 100644
index 000000000..13485c16b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/app_debug.h
@@ -0,0 +1,45 @@
+
+/**
+  ******************************************************************************
+  * @file    app_debug.h
+  * @author  MCD Application Team
+  * @brief   Interface to support debug in the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+  /* Exported types ------------------------------------------------------------*/
+  /* Exported constants --------------------------------------------------------*/
+  /* External variables --------------------------------------------------------*/
+  /* Exported macros -----------------------------------------------------------*/
+  /* Exported functions ------------------------------------------------------- */
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/app_entry.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/app_entry.h
new file mode 100644
index 000000000..77ead2384
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/app_entry.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    app_entry.h
+  * @author  MCD Application Team
+  * @brief   Interface to the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_ENTRY_H
+#define APP_ENTRY_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APPE_Init( void );
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*APP_ENTRY_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/hw_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/hw_conf.h
new file mode 100644
index 000000000..0440ae479
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/hw_conf.h
@@ -0,0 +1,196 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : hw_conf.h
+  * Description        : Hardware configuration file for BLE 
+  *                      middleWare.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef HW_CONF_H
+#define HW_CONF_H
+
+/******************************************************************************
+* Semaphores
+* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
+*****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
+/* Index of the semaphore used to manage the entry Stop Mode procedure */
+#define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
+
+/* Index of the semaphore used to access the RCC */
+#define CFG_HW_RCC_SEMID                                        3
+
+/* Index of the semaphore used to access the FLASH */
+#define CFG_HW_FLASH_SEMID                                      2
+
+/* Index of the semaphore used to access the PKA */
+#define CFG_HW_PKA_SEMID                                        1
+
+/* Index of the semaphore used to access the RNG */
+#define CFG_HW_RNG_SEMID                                        0
+
+/******************************************************************************
+ * HW TIMER SERVER
+ *****************************************************************************/
+/**
+ * The user may define the maximum number of virtual timers supported.
+ * It shall not exceed 255
+ */
+#define CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER  6
+
+/**
+ * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
+ * wakeup timer.
+ * This setting is the preemptpriority part of the NVIC.
+ */
+#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO  3
+
+/**
+ * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
+ * wakeup timer.
+ * This setting is the subpriority part of the NVIC. It does not exist on all processors. When it is not supported
+ * on the CPU, the setting is ignored
+ */
+#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO  0
+
+/**
+ *  Define a critical section in the Timer server
+ *  The Timer server does not support the API to be nested
+ *  The  Application shall either:
+ *    a) Ensure this will never happen
+ *    b) Define the critical section
+ *  The default implementations is masking all interrupts using the PRIMASK bit
+ *  The TimerServer driver uses critical sections to avoid context corruption. This is achieved with the macro
+ *  TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION. When CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION is set
+ *  to 1, all STM32 interrupts are masked with the PRIMASK bit of the CortexM CPU. It is possible to use the BASEPRI
+ *  register of the CortexM CPU to keep allowed some interrupts with high priority. In that case, the user shall
+ *  re-implement TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION and shall make sure that no TimerServer
+ *  API are called when the TIMER critical section is entered
+ */
+#define CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION  1
+
+/**
+   * This value shall reflect the maximum delay there could be in the application between the time the RTC interrupt
+   * is generated by the Hardware and the time when the  RTC interrupt handler is called. This time is measured in
+   * number of RTCCLK ticks.
+   * A relaxed timing would be 10ms
+   * When the value is too short, the timerserver will not be able to count properly and all timeout may be random.
+   * When the value is too long, the device may wake up more often than the most optimal configuration. However, the
+   * impact on power consumption would be marginal (unless the value selected is extremely too long). It is strongly
+   * recommended to select a value large enough to make sure it is not too short to ensure reliability of the system
+   * as this will have marginal impact on low power mode
+   */
+#define CFG_HW_TS_RTC_HANDLER_MAX_DELAY  ( 10 * (LSI_VALUE/1000) )
+
+  /**
+   * Interrupt ID in the NVIC of the RTC Wakeup interrupt handler
+   * It shall be type of IRQn_Type
+   */
+#define CFG_HW_TS_RTC_WAKEUP_HANDLER_ID  RTC_WKUP_IRQn
+
+/******************************************************************************
+ * HW UART
+ *****************************************************************************/
+
+#define CFG_HW_LPUART1_ENABLED           0
+#define CFG_HW_LPUART1_DMA_TX_SUPPORTED  0
+
+#define CFG_HW_USART1_ENABLED           1
+#define CFG_HW_USART1_DMA_TX_SUPPORTED  1
+
+/**
+ * UART1
+ */
+#define CFG_HW_USART1_PREEMPTPRIORITY         0x0F
+#define CFG_HW_USART1_SUBPRIORITY             0
+
+/** < The application shall check the selected source clock is enable */
+#define CFG_HW_USART1_SOURCE_CLOCK              RCC_USART1CLKSOURCE_SYSCLK
+
+#define CFG_HW_USART1_BAUDRATE                115200
+#define CFG_HW_USART1_WORDLENGTH              UART_WORDLENGTH_8B
+#define CFG_HW_USART1_STOPBITS                UART_STOPBITS_1
+#define CFG_HW_USART1_PARITY                  UART_PARITY_NONE
+#define CFG_HW_USART1_HWFLOWCTL               UART_HWCONTROL_NONE
+#define CFG_HW_USART1_MODE                    UART_MODE_TX_RX
+#define CFG_HW_USART1_ADVFEATUREINIT          UART_ADVFEATURE_NO_INIT
+#define CFG_HW_USART1_OVERSAMPLING            UART_OVERSAMPLING_8
+
+#define CFG_HW_USART1_TX_PORT_CLK_ENABLE      __HAL_RCC_GPIOB_CLK_ENABLE
+#define CFG_HW_USART1_TX_PORT                 GPIOB
+#define CFG_HW_USART1_TX_PIN                  GPIO_PIN_6
+#define CFG_HW_USART1_TX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_USART1_TX_PULL                 GPIO_NOPULL
+#define CFG_HW_USART1_TX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_TX_ALTERNATE            GPIO_AF7_USART1
+
+#define CFG_HW_USART1_RX_PORT_CLK_ENABLE      __HAL_RCC_GPIOB_CLK_ENABLE
+#define CFG_HW_USART1_RX_PORT                 GPIOB
+#define CFG_HW_USART1_RX_PIN                  GPIO_PIN_7
+#define CFG_HW_USART1_RX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_USART1_RX_PULL                 GPIO_NOPULL
+#define CFG_HW_USART1_RX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_RX_ALTERNATE            GPIO_AF7_USART1
+
+#define CFG_HW_USART1_CTS_PORT_CLK_ENABLE     __HAL_RCC_GPIOvalueNotSetted_CLK_ENABLE
+#define CFG_HW_USART1_CTS_PORT                GPIOvalueNotSetted
+#define CFG_HW_USART1_CTS_PIN                 GPIO_PIN_valueNotSetted
+#define CFG_HW_USART1_CTS_MODE                GPIO_MODE_AF_PP
+#define CFG_HW_USART1_CTS_PULL                GPIO_PULLDOWN
+#define CFG_HW_USART1_CTS_SPEED               GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_CTS_ALTERNATE           GPIO_AFvalueNotSetted_USART1
+
+#define CFG_HW_USART1_DMA_TX_PREEMPTPRIORITY  0x0F
+#define CFG_HW_USART1_DMA_TX_SUBPRIORITY      0
+
+#define CFG_HW_USART1_DMAMUX_CLK_ENABLE       __HAL_RCC_DMAMUX1_CLK_ENABLE
+#define CFG_HW_USART1_DMA_CLK_ENABLE          __HAL_RCC_DMA2_CLK_ENABLE
+#define CFG_HW_USART1_TX_DMA_REQ			  DMA_REQUEST_USART1_TX
+#define CFG_HW_USART1_TX_DMA_CHANNEL          DMA2_CHANNEL_4
+#define CFG_HW_USART1_TX_DMA_IRQn             DMA2_CHANNEL_4_IRQn
+#define CFG_HW_USART1_DMA_TX_IRQHandler       DMA2_CHANNEL_4_IRQHandler
+
+#endif /*HW_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/hw_if.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/hw_if.h
new file mode 100644
index 000000000..5a15665ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/hw_if.h
@@ -0,0 +1,254 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    hw_if.h
+  * @author  MCD Application Team
+  * @brief   Hardware Interface
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef HW_IF_H
+#define HW_IF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_ipcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_hsem.h"
+#include "stm32wbxx_ll_gpio.h"
+#include "stm32wbxx_ll_rtc.h"
+
+#ifdef  USE_STM32WBXX_USB_DONGLE
+#include "stm32wbxx_usb_dongle.h"
+#endif
+#ifdef  USE_STM32WBXX_NUCLEO
+  #ifdef STM32WB35xx
+  #include "nucleo_wb35ce.h"
+  #else
+  #include "stm32wbxx_nucleo.h"
+  #endif
+#endif
+#ifdef  USE_X_NUCLEO_EPD
+#include "x_nucleo_epd.h"
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /******************************************************************************
+   * HW UART
+   ******************************************************************************/
+  typedef enum
+  {
+    hw_uart1,
+    hw_uart2,
+    hw_lpuart1,
+  } hw_uart_id_t;
+
+  typedef enum
+  {
+    hw_uart_ok,
+    hw_uart_error,
+    hw_uart_busy,
+    hw_uart_to,
+  } hw_status_t;
+
+  void HW_UART_Init(hw_uart_id_t hw_uart_id);
+  void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *pData, uint16_t Size, void (*Callback)(void));
+  void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *pData, uint16_t Size,  void (*Callback)(void));
+  hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout);
+  hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*Callback)(void));
+  void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id);
+  void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id);
+
+  /******************************************************************************
+   * HW TimerServer
+   ******************************************************************************/
+  /* Exported types ------------------------------------------------------------*/
+  /**
+   * This setting is used when standby mode is supported.
+   * hw_ts_InitMode_Limited should be used when the device restarts from Standby Mode. In that case, the Timer Server does
+   * not re-initialized its context. Only the Hardware register which content has been lost is reconfigured
+   * Otherwise, hw_ts_InitMode_Full should be requested (Start from Power ON) and everything is re-initialized.
+   */
+  typedef enum
+  {
+    hw_ts_InitMode_Full,
+    hw_ts_InitMode_Limited,
+  } HW_TS_InitMode_t;
+
+  /**
+   * When a Timer is created as a SingleShot timer, it is not automatically restarted when the timeout occurs. However,
+   * the timer is kept reserved in the list and could be restarted at anytime with HW_TS_Start()
+   *
+   * When a Timer is created as a Repeated timer, it is automatically restarted when the timeout occurs.
+   */
+  typedef enum
+  {
+    hw_ts_SingleShot,
+    hw_ts_Repeated
+  } HW_TS_Mode_t;
+
+  /**
+   * hw_ts_Successful is returned when a Timer has been successfully created with HW_TS_Create(). Otherwise, hw_ts_Failed
+   * is returned. When hw_ts_Failed is returned, that means there are not enough free slots in the list to create a
+   * Timer. In that case, CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER should be increased
+   */
+  typedef enum
+  {
+    hw_ts_Successful,
+    hw_ts_Failed,
+  }HW_TS_ReturnStatus_t;
+
+  typedef void (*HW_TS_pTimerCb_t)(void);
+
+  /**
+   * @brief  Initialize the timer server
+   *         This API shall be called by the application before any timer is requested to the timer server. It
+   *         configures the RTC module to be connected to the LSI input clock.
+   *
+   * @param  TimerInitMode: When the device restarts from Standby, it should request hw_ts_InitMode_Limited so that the
+   *         Timer context is not re-initialized. Otherwise, hw_ts_InitMode_Full should be requested
+   * @param  hrtc: RTC Handle
+   * @retval None
+   */
+  void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *hrtc);
+
+  /**
+   * @brief  Interface to create a virtual timer
+   *         The user shall call this API to create a timer. Once created, the timer is reserved to the module until it
+   *         has been deleted. When creating a timer, the user shall specify the mode (single shot or repeated), the
+   *         callback to be notified when the timer expires and a module ID to identify in the timer interrupt handler
+   *         which module is concerned. In return, the user gets a timer ID to handle it.
+   *
+   * @param  TimerProcessID:  This is an identifier provided by the user and returned in the callback to allow
+   *                          identification of the requester
+   * @param  pTimerId: Timer Id returned to the user to request operation (start, stop, delete)
+   * @param  TimerMode: Mode of the virtual timer (Single shot or repeated)
+   * @param  pTimerCallBack: Callback when the virtual timer expires
+   * @retval HW_TS_ReturnStatus_t: Return whether the creation is sucessfull or not
+   */
+  HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pTimerCallBack);
+
+  /**
+   * @brief  Stop a virtual timer
+   *         This API may be used to stop a running timer. A timer which is stopped is move to the pending state.
+   *         A pending timer may be restarted at any time with a different timeout value but the mode cannot be changed.
+   *         Nothing is done when it is called to stop a timer which has been already stopped
+   *
+   * @param  TimerID:  Id of the timer to stop
+   * @retval None
+   */
+  void HW_TS_Stop(uint8_t TimerID);
+
+  /**
+   * @brief  Start a virtual timer
+   *         This API shall be used to start a timer. The timeout value is specified and may be different each time.
+   *         When the timer is in the single shot mode, it will move to the pending state when it expires. The user may
+   *         restart it at any time with a different timeout value. When the timer is in the repeated mode, it always
+   *         stay in the running state. When the timer expires, it will be restarted with the same timeout value.
+   *         This API shall not be called on a running timer.
+   *
+   * @param  TimerID:  The ID Id of the timer to start
+   * @param  timeout_ticks: Number of ticks of the virtual timer (Maximum value is (0xFFFFFFFF-0xFFFF = 0xFFFF0000)
+   * @retval None
+   */
+  void HW_TS_Start(uint8_t TimerID, uint32_t timeout_ticks);
+
+  /**
+   * @brief  Delete a virtual timer from the list
+   *         This API should be used when a timer is not needed anymore by the user. A deleted timer is removed from
+   *         the timer list managed by the timer server. It cannot be restarted again. The user has to go with the
+   *         creation of a new timer if required and may get a different timer id
+   *
+   * @param  TimerID:  The ID of the timer to remove from the list
+   * @retval None
+   */
+  void HW_TS_Delete(uint8_t TimerID);
+
+  /**
+   * @brief  Schedule the timer list on the timer interrupt handler
+   *         This interrupt handler shall be called by the application in the RTC interrupt handler. This handler takes
+   *         care of clearing all status flag required in the RTC and EXTI peripherals
+   *
+   * @param  None
+   * @retval None
+   */
+  void HW_TS_RTC_Wakeup_Handler(void);
+
+  /**
+   * @brief  Return the number of ticks to count before the interrupt
+   *         This API returns the number of ticks left to be counted before an interrupt is generated by the
+   *         Timer Server. This API may be used by the application for power management optimization. When the system
+   *         enters low power mode, the mode selection is a tradeoff between the wakeup time where the CPU is running
+   *         and the time while the CPU will be kept in low power mode before next wakeup. The deeper is the
+   *         low power mode used, the longer is the wakeup time. The low power mode management considering wakeup time
+   *         versus time in low power mode is implementation specific
+   *         When the timer is disabled (No timer in the list), it returns 0xFFFF
+   *
+   * @param  None
+   * @retval The number of ticks left to count
+   */
+  uint16_t HW_TS_RTC_ReadLeftTicksToCount(void);
+
+  /**
+   * @brief  Notify the application that a registered timer has expired
+   *         This API shall be implemented by the user application.
+   *         This API notifies the application that a timer expires. This API is running in the RTC Wakeup interrupt
+   *         context. The application may implement an Operating System to change the context priority where the timer
+   *         callback may be handled. This API provides the module ID to identify which module is concerned and to allow
+   *         sending the information to the correct task
+   *
+   * @param  TimerProcessID: The TimerProcessId associated with the timer when it has been created
+   * @param  TimerID: The TimerID of the expired timer
+   * @param  pTimerCallBack: The Callback associated with the timer when it has been created
+   * @retval None
+   */
+  void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack);
+
+  /**
+   * @brief  Notify the application that the wakeupcounter has been updated
+   *         This API should be implemented by the user application
+   *         This API notifies the application that the counter has been updated. This is expected to be used along
+   *         with the HW_TS_RTC_ReadLeftTicksToCount () API. It could be that the counter has been updated since the
+   *         last call of HW_TS_RTC_ReadLeftTicksToCount () and before entering low power mode. This notification
+   *         provides a way to the application to solve that race condition to reevaluate the counter value before
+   *         entering low power mode
+   *
+   * @param  None
+   * @retval None
+   */
+  void HW_TS_RTC_CountUpdated_AppNot(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*HW_IF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/main.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/main.h
new file mode 100644
index 000000000..c8b13c23f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/main.h
@@ -0,0 +1,75 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#ifdef STM32WB35xx
+#include "nucleo_wb35ce.h"
+#else
+#include "stm32wbxx_nucleo.h"
+#endif
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/stm32_lpm_if.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/stm32_lpm_if.h
new file mode 100644
index 000000000..d8e67947f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/stm32_lpm_if.h
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+******************************************************************************
+* @file    stm32_lpm_if.h
+* @brief   Header for stm32_lpm_if.c module (device specific LP management)
+******************************************************************************
+* @attention
+*
+* 
    © Copyright (c) 2019 STMicroelectronics. 
+* All rights reserved.
    
+*
+* This software component is licensed by ST under BSD 3-Clause license,
+* the "License"; You may not use this file except in compliance with the 
+* License. You may obtain a copy of the License at:
+*                        opensource.org/licenses/BSD-3-Clause
+*
+******************************************************************************
+*/
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_LPM_IF_H
+#define __STM32_LPM_IF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/**
+  * @brief Enters Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_EnterOffMode( void );
+/**
+  * @brief Exits Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_ExitOffMode( void );
+
+/**
+  * @brief Enters Low Power Stop Mode
+  * @note ARM exists the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterStopMode( void );
+/**
+  * @brief Exits Low Power Stop Mode
+  * @note Enable the pll at 32MHz
+  * @param none
+  * @retval none
+  */
+void PWR_ExitStopMode( void );
+
+/**
+  * @brief Enters Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterSleepMode( void );
+
+/**
+  * @brief Exits Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_ExitSleepMode( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32_LPM_IF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..eff335ddf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,354 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+#define HAL_CORTEX_MODULE_ENABLED
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+/*#define HAL_I2C_MODULE_ENABLED   */
+#define HAL_IPCC_MODULE_ENABLED
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+#define HAL_PWR_MODULE_ENABLED
+/*#define HAL_QSPI_MODULE_ENABLED   */
+#define HAL_RCC_MODULE_ENABLED
+/*#define HAL_RNG_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100UL)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  (32000UL)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  (32000UL)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    (48000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    (2097000UL) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..cf6cc65e7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/stm32wbxx_it.h
@@ -0,0 +1,78 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "app_common.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void DMA1_Channel4_IRQHandler(void);
+void USART1_IRQHandler(void);
+void LPUART1_IRQHandler(void);
+void DMA2_Channel4_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+void RTC_WKUP_IRQHandler(void);
+void IPCC_C1_TX_IRQHandler(void);
+void IPCC_C1_RX_IRQHandler(void);
+void PUSH_BUTTON_SW1_EXTI_IRQHandler(void);
+void PUSH_BUTTON_SW2_EXTI_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/utilities_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/utilities_conf.h
new file mode 100644
index 000000000..4dde3509a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Inc/utilities_conf.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : utilities_conf.h
+  * Description        : Configuration file for STM32 Utilities.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef UTILITIES_CONF_H
+#define UTILITIES_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "cmsis_compiler.h"
+#include "string.h"
+
+/******************************************************************************
+ * common
+ ******************************************************************************/
+#define UTILS_ENTER_CRITICAL_SECTION( )   uint32_t primask_bit = __get_PRIMASK( );\
+                                          __disable_irq( )
+
+#define UTILS_EXIT_CRITICAL_SECTION( )          __set_PRIMASK( primask_bit )
+
+#define UTILS_MEMSET8( dest, value, size )      memset( dest, value, size);
+
+/******************************************************************************
+ * tiny low power manager
+ * (any macro that does not need to be modified can be removed)
+ ******************************************************************************/
+#define UTIL_LPM_INIT_CRITICAL_SECTION( )
+#define UTIL_LPM_ENTER_CRITICAL_SECTION( )      UTILS_ENTER_CRITICAL_SECTION( )
+#define UTIL_LPM_EXIT_CRITICAL_SECTION( )       UTILS_EXIT_CRITICAL_SECTION( )
+
+/******************************************************************************
+ * sequencer
+ * (any macro that does not need to be modified can be removed)
+ ******************************************************************************/
+#define UTIL_SEQ_INIT_CRITICAL_SECTION( )
+#define UTIL_SEQ_ENTER_CRITICAL_SECTION( )      UTILS_ENTER_CRITICAL_SECTION( )
+#define UTIL_SEQ_EXIT_CRITICAL_SECTION( )       UTILS_EXIT_CRITICAL_SECTION( )
+#define UTIL_SEQ_CONF_TASK_NBR                  (32)
+#define UTIL_SEQ_CONF_PRIO_NBR                  (2)
+#define UTIL_SEQ_MEMSET8( dest, value, size )   UTILS_MEMSET8( dest, value, size )
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*UTILITIES_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/app_debug.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/app_debug.c
new file mode 100644
index 000000000..756c4257f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/app_debug.c
@@ -0,0 +1,361 @@
+/**
+ ******************************************************************************
+ * @file    app_debug.c
+ * @author  MCD Application Team
+ * @brief   Debug capabilities
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+extern void MX_LPUART1_UART_Init(void);
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+extern void MX_USART1_UART_Init(void);
+#endif
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+#if (CFG_HW_USART1_ENABLED == 1)
+    MX_USART1_UART_Init();
+#endif
+#if (CFG_HW_LPUART1_ENABLED == 1)
+    MX_LPUART1_UART_Init();
+#endif
+  return;
+}
+
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/app_entry.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/app_entry.c
new file mode 100644
index 000000000..9734527c9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/app_entry.c
@@ -0,0 +1,283 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    app_entry.c
+ * @author  MCD Application Team
+ * @brief   Entry point of the Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "main.h"
+#include "app_entry.h"
+#include "tm.h"
+#include "tl.h"
+#include "stm32_seq.h"
+#include "stm_list.h"
+#include "stm32_lpm.h"
+#include "app_debug.h"
+
+/* Private includes -----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+extern RTC_HandleTypeDef hrtc;
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+#define POOL_SIZE (CFG_TLBLE_EVT_QUEUE_LENGTH*4U*DIVC(( sizeof(TL_PacketHeader_t) + TL_BLE_EVENT_FRAME_SIZE ), 4U))
+#define INFORMATION_SECTION_KEYWORD   (0xA56959A6)
+
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("VERSION") const uint32_t FW_Version = (CFG_FW_MAJOR_VERSION << 24) + (CFG_FW_MINOR_VERSION << 16) + (CFG_FW_SUBVERSION << 8)
++ (CFG_FW_BRANCH << 4) + CFG_FW_BUILD;
+PLACE_IN_SECTION("VERSION") const uint32_t keyword = INFORMATION_SECTION_KEYWORD;
+
+extern RTC_HandleTypeDef hrtc; /**< RTC handler declaration */
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t EvtPool[POOL_SIZE];
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static TL_CmdPacket_t SystemCmdBuffer;
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t SystemSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255U];
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t BleSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255];
+static tListNode  SysEvtQueue;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private functions prototypes-----------------------------------------------*/
+static void SystemPower_Config( void );
+static void appe_Tl_Init( void );
+static void APPE_SysUserEvtRx( TL_EvtPacket_t * p_evt_rx );
+static void shci_user_evt_proc( void );
+
+/* USER CODE BEGIN PFP */
+static void Led_Init( void );
+static void Button_Init( void );
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APPE_Init( void )
+{
+  SystemPower_Config(); /**< Configure the system Power Mode */
+
+  HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
+
+/* USER CODE BEGIN APPE_Init_1 */
+  APPD_Init();
+
+  /**
+   * The Standby mode should not be entered before the initialization is over
+   * The default state of the Low Power Manager is to allow the Standby Mode so an request is needed here
+   */
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP, UTIL_LPM_DISABLE);
+
+  Led_Init();
+
+  Button_Init();
+
+/* USER CODE END APPE_Init_1 */
+  appe_Tl_Init();	/* Initialize all transport layers */
+
+  /**
+   * From now, the application is waiting for the ready event ( VS_HCI_C2_Ready )
+   * received on the system channel before starting the Stack
+   * This system event is received with APPE_SysUserEvtRx()
+   */
+/* USER CODE BEGIN APPE_Init_2 */
+
+/* USER CODE END APPE_Init_2 */
+   return;
+}
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+ * @brief  Configure the system for power optimization
+ *
+ * @note  This API configures the system to be ready for low power mode
+ *
+ * @param  None
+ * @retval None
+ */
+static void SystemPower_Config( void )
+{
+
+  /**
+   * Select HSI as system clock source after Wake Up from Stop mode
+   */
+  LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
+
+  /* Initialize low power manager */
+  UTIL_LPM_Init( );
+
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+  /**
+   *  Enable USB power
+   */
+  HAL_PWREx_EnableVddUSB();
+#endif
+
+  return;
+}
+
+static void appe_Tl_Init( void )
+{
+  TL_MM_Config_t tl_mm_config;
+  TL_SYS_InitConf_t tl_sys_init_conf;
+  /**< Reference table initialization */
+  TL_Init();
+
+  /**< System channel initialization */
+  LST_init_head (&SysEvtQueue);
+  UTIL_SEQ_RegTask( 1<< CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID, UTIL_SEQ_RFU, shci_user_evt_proc );
+  tl_sys_init_conf.p_cmdbuffer =  (uint8_t*)&SystemCmdBuffer;
+  tl_sys_init_conf.IoBusCallBackCmdEvt = TM_SysCmdRspCb;
+  tl_sys_init_conf.IoBusCallBackUserEvt = APPE_SysUserEvtRx;
+  TL_SYS_Init( (void*) &tl_sys_init_conf );
+
+  /**< Memory Manager channel initialization */
+  tl_mm_config.p_BleSpareEvtBuffer = BleSpareEvtBuffer;
+  tl_mm_config.p_SystemSpareEvtBuffer = SystemSpareEvtBuffer;
+  tl_mm_config.p_AsynchEvtPool = EvtPool;
+  tl_mm_config.AsynchEvtPoolSize = POOL_SIZE;
+  TL_MM_Init( &tl_mm_config );
+
+  TL_Enable();
+
+  return;
+}
+
+static void APPE_SysUserEvtRx( TL_EvtPacket_t * p_evt_rx )
+{
+  LST_insert_tail (&SysEvtQueue, (tListNode *)p_evt_rx);
+
+  UTIL_SEQ_SetTask( 1<
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "hw_conf.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef enum
+{
+  TimerID_Free,
+  TimerID_Created,
+  TimerID_Running
+}TimerIDStatus_t;
+
+typedef enum
+{
+  SSR_Read_Requested,
+  SSR_Read_Not_Requested
+}RequestReadSSR_t;
+
+typedef enum
+{
+  WakeupTimerValue_Overpassed,
+  WakeupTimerValue_LargeEnough
+}WakeupTimerLimitation_Status_t;
+
+typedef struct
+{
+  HW_TS_pTimerCb_t  pTimerCallBack;
+  uint32_t        CounterInit;
+  uint32_t        CountLeft;
+  TimerIDStatus_t     TimerIDStatus;
+  HW_TS_Mode_t   TimerMode;
+  uint32_t        TimerProcessID;
+  uint8_t         PreviousID;
+  uint8_t         NextID;
+}TimerContext_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define SSR_FORBIDDEN_VALUE   0xFFFFFFFF
+#define TIMER_LIST_EMPTY      0xFFFF
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/**
+ * START of Section TIMERSERVER_CONTEXT
+ */
+
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile TimerContext_t aTimerContext[CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER];
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint8_t CurrentRunningTimerID;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint8_t PreviousRunningTimerID;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint32_t SSRValueOnLastSetup;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile WakeupTimerLimitation_Status_t  WakeupTimerLimitation;
+
+/**
+ * END of Section TIMERSERVER_CONTEXT
+ */
+
+static RTC_HandleTypeDef *phrtc;  /**< RTC handle */
+static uint8_t  WakeupTimerDivider;
+static uint8_t  AsynchPrescalerUserConfig;
+static uint16_t SynchPrescalerUserConfig;
+static volatile uint16_t MaxWakeupTimerSetup;
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void RestartWakeupCounter(uint16_t Value);
+static uint16_t ReturnTimeElapsed(void);
+static void RescheduleTimerList(void);
+static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR);
+static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID);
+static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID);
+static uint16_t linkTimer(uint8_t TimerID);
+static uint32_t ReadRtcSsrValue(void);
+
+__weak void HW_TS_RTC_CountUpdated_AppNot(void);
+
+/* Functions Definition ------------------------------------------------------*/
+
+/**
+ * @brief  Read the RTC_SSR value
+ *         As described in the reference manual, the RTC_SSR shall be read twice to ensure
+ *         reliability of the value
+ * @param  None
+ * @retval SSR value read
+ */
+static uint32_t ReadRtcSsrValue(void)
+{
+  uint32_t first_read;
+  uint32_t second_read;
+
+  first_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+
+  second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+
+  while(first_read != second_read)
+  {
+    first_read = second_read;
+
+    second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+  }
+
+  return second_read;
+}
+
+/**
+ * @brief  Insert a Timer in the list after the Timer ID specified
+ * @param  TimerID:   The ID of the Timer
+ * @param  RefTimerID: The ID of the Timer to be linked after
+ * @retval None
+ */
+static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID)
+{
+  uint8_t next_id;
+
+  next_id = aTimerContext[RefTimerID].NextID;
+
+  if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    aTimerContext[next_id].PreviousID = TimerID;
+  }
+  aTimerContext[TimerID].NextID = next_id;
+  aTimerContext[TimerID].PreviousID = RefTimerID ;
+  aTimerContext[RefTimerID].NextID = TimerID;
+
+  return;
+}
+
+/**
+ * @brief  Insert a Timer in the list before the ID specified
+ * @param  TimerID:   The ID of the Timer
+ * @param  RefTimerID: The ID of the Timer to be linked before
+ * @retval None
+ */
+static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID)
+{
+  uint8_t previous_id;
+
+  if(RefTimerID != CurrentRunningTimerID)
+  {
+    previous_id = aTimerContext[RefTimerID].PreviousID;
+
+    aTimerContext[previous_id].NextID = TimerID;
+    aTimerContext[TimerID].NextID = RefTimerID;
+    aTimerContext[TimerID].PreviousID = previous_id ;
+    aTimerContext[RefTimerID].PreviousID = TimerID;
+  }
+  else
+  {
+    aTimerContext[TimerID].NextID = RefTimerID;
+    aTimerContext[RefTimerID].PreviousID = TimerID;
+  }
+
+  return;
+}
+
+/**
+ * @brief  Insert a Timer in the list
+ * @param  TimerID:   The ID of the Timer
+ * @retval None
+ */
+static uint16_t linkTimer(uint8_t TimerID)
+{
+  uint32_t time_left;
+  uint16_t time_elapsed;
+  uint8_t timer_id_lookup;
+  uint8_t next_id;
+
+  if(CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    /**
+     * No timer in the list
+     */
+    PreviousRunningTimerID = CurrentRunningTimerID;
+    CurrentRunningTimerID = TimerID;
+    aTimerContext[TimerID].NextID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;
+
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+    time_elapsed = 0;
+  }
+  else
+  {
+    time_elapsed = ReturnTimeElapsed();
+
+    /**
+     * update count of the timer to be linked
+     */
+    aTimerContext[TimerID].CountLeft += time_elapsed;
+    time_left = aTimerContext[TimerID].CountLeft;
+
+    /**
+     * Search for index where the new timer shall be linked
+     */
+    if(aTimerContext[CurrentRunningTimerID].CountLeft <= time_left)
+    {
+      /**
+       * Search for the ID after the first one
+       */
+      timer_id_lookup = CurrentRunningTimerID;
+      next_id = aTimerContext[timer_id_lookup].NextID;
+      while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left))
+      {
+        timer_id_lookup = aTimerContext[timer_id_lookup].NextID;
+        next_id = aTimerContext[timer_id_lookup].NextID;
+      }
+
+      /**
+       * Link after the ID
+       */
+      LinkTimerAfter(TimerID, timer_id_lookup);
+    }
+    else
+    {
+      /**
+       * Link before the first ID
+       */
+      LinkTimerBefore(TimerID, CurrentRunningTimerID);
+      PreviousRunningTimerID = CurrentRunningTimerID;
+      CurrentRunningTimerID = TimerID;
+    }
+  }
+
+  return time_elapsed;
+}
+
+/**
+ * @brief  Remove a Timer from the list
+ * @param  TimerID:   The ID of the Timer
+ * @param  RequestReadSSR: Request to read the SSR register or not
+ * @retval None
+ */
+static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR)
+{
+  uint8_t previous_id;
+  uint8_t next_id;
+
+  if(TimerID == CurrentRunningTimerID)
+  {
+    PreviousRunningTimerID = CurrentRunningTimerID;
+    CurrentRunningTimerID = aTimerContext[TimerID].NextID;
+  }
+  else
+  {
+    previous_id = aTimerContext[TimerID].PreviousID;
+    next_id = aTimerContext[TimerID].NextID;
+
+    aTimerContext[previous_id].NextID = aTimerContext[TimerID].NextID;
+    if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+    {
+      aTimerContext[next_id].PreviousID = aTimerContext[TimerID].PreviousID;
+    }
+  }
+
+  /**
+   * Timer is out of the list
+   */
+  aTimerContext[TimerID].TimerIDStatus = TimerID_Created;
+
+  if((CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (RequestReadSSR == SSR_Read_Requested))
+  {
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+  }
+
+  return;
+}
+
+/**
+ * @brief  Return the number of ticks counted by the wakeuptimer since it has been started
+ * @note  The API is reading the SSR register to get how many ticks have been counted
+ *        since the time the timer has been started
+ * @param  None
+ * @retval Time expired in Ticks
+ */
+static uint16_t ReturnTimeElapsed(void)
+{
+  uint32_t  return_value;
+  uint32_t  wrap_counter;
+
+  if(SSRValueOnLastSetup != SSR_FORBIDDEN_VALUE)
+  {
+    return_value = ReadRtcSsrValue(); /**< Read SSR register first */
+
+    if (SSRValueOnLastSetup >= return_value)
+    {
+      return_value = SSRValueOnLastSetup - return_value;
+    }
+    else
+    {
+      wrap_counter = SynchPrescalerUserConfig - return_value;
+      return_value = SSRValueOnLastSetup + wrap_counter;
+    }
+
+    /**
+     * At this stage, ReturnValue holds the number of ticks counted by SSR
+     * Need to translate in number of ticks counted by the Wakeuptimer
+     */
+    return_value = return_value*AsynchPrescalerUserConfig;
+    return_value = return_value >> WakeupTimerDivider;
+  }
+  else
+  {
+    return_value = 0;
+  }
+
+  return (uint16_t)return_value;
+}
+
+/**
+ * @brief  Set the wakeup counter
+ * @note  The API is writing the counter value so that the value is decreased by one to cope with the fact
+ *    the interrupt is generated with 1 extra clock cycle (See RefManuel)
+ *    It assumes all condition are met to be allowed to write the wakeup counter
+ * @param  Value: Value to be written in the counter
+ * @retval None
+ */
+static void RestartWakeupCounter(uint16_t Value)
+{
+  /**
+   * The wakeuptimer has been disabled in the calling function to reduce the time to poll the WUTWF
+   * FLAG when the new value will have to be written
+   *  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);
+   */
+
+  if(Value == 0)
+  {
+    SSRValueOnLastSetup = ReadRtcSsrValue();
+
+    /**
+     * Simulate that the Timer expired
+     */
+    HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
+  }
+  else
+  {
+    if((Value > 1) ||(WakeupTimerDivider != 1))
+    {
+      Value -= 1;
+    }
+
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+    /**
+     * make sure to clear the flags after checking the WUTWF.
+     * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+     * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+     * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+     * due to the autoreload feature
+     */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+    HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);   /**<  Clear pending bit in NVIC */
+
+    MODIFY_REG(RTC->WUTR, RTC_WUTR_WUT, Value);
+
+    /**
+     * Update the value here after the WUTWF polling that may take some time
+     */
+    SSRValueOnLastSetup = ReadRtcSsrValue();
+
+    __HAL_RTC_WAKEUPTIMER_ENABLE(phrtc);    /**<  Enable the Wakeup Timer */
+
+    HW_TS_RTC_CountUpdated_AppNot();
+  }
+
+  return ;
+}
+
+/**
+ * @brief  Reschedule the list of timer
+ * @note  1) Update the count left for each timer in the list
+ *    2) Setup the wakeuptimer
+ * @param  None
+ * @retval None
+ */
+static void RescheduleTimerList(void)
+{
+  uint8_t   localTimerID;
+  uint32_t  timecountleft;
+  uint16_t  wakeup_timer_value;
+  uint16_t  time_elapsed;
+
+  /**
+   * The wakeuptimer is disabled now to reduce the time to poll the WUTWF
+   * FLAG when the new value will have to be written
+   */
+  if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+  {
+    /**
+     * Wait for the flag to be back to 0 when the wakeup timer is enabled
+     */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == SET);
+  }
+  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);   /**<  Disable the Wakeup Timer */
+
+  localTimerID = CurrentRunningTimerID;
+
+  /**
+   * Calculate what will be the value to write in the wakeuptimer
+   */
+  timecountleft = aTimerContext[localTimerID].CountLeft;
+
+  /**
+   * Read how much has been counted
+   */
+  time_elapsed = ReturnTimeElapsed();
+
+  if(timecountleft < time_elapsed )
+  {
+    /**
+     * There is no tick left to count
+     */
+    wakeup_timer_value = 0;
+    WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+  }
+  else
+  {
+    if(timecountleft > (time_elapsed + MaxWakeupTimerSetup))
+    {
+      /**
+       * The number of tick left is greater than the Wakeuptimer maximum value
+       */
+      wakeup_timer_value = MaxWakeupTimerSetup;
+
+      WakeupTimerLimitation = WakeupTimerValue_Overpassed;
+    }
+    else
+    {
+      wakeup_timer_value = timecountleft - time_elapsed;
+      WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+    }
+
+  }
+
+  /**
+   * update ticks left to be counted for each timer
+   */
+  while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    if (aTimerContext[localTimerID].CountLeft < time_elapsed)
+    {
+      aTimerContext[localTimerID].CountLeft = 0;
+    }
+    else
+    {
+      aTimerContext[localTimerID].CountLeft -= time_elapsed;
+    }
+    localTimerID = aTimerContext[localTimerID].NextID;
+  }
+
+  /**
+   * Write next count
+   */
+  RestartWakeupCounter(wakeup_timer_value);
+
+  return ;
+}
+
+/* Public functions ----------------------------------------------------------*/
+
+/**
+ * For all public interface except that may need write access to the RTC, the RTC
+ * shall be unlock at the beginning and locked at the output
+ * In order to ease maintainability, the unlock is done at the top and the lock at then end
+ * in case some new implementation is coming in the future
+ */
+
+void HW_TS_RTC_Wakeup_Handler(void)
+{
+  HW_TS_pTimerCb_t ptimer_callback;
+  uint32_t timer_process_id;
+  uint8_t local_current_running_timer_id;
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  /**
+   * Disable the Wakeup Timer
+   * This may speed up a bit the processing to wait the timer to be disabled
+   * The timer is still counting 2 RTCCLK
+   */
+  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);
+
+  local_current_running_timer_id = CurrentRunningTimerID;
+
+  if(aTimerContext[local_current_running_timer_id].TimerIDStatus == TimerID_Running)
+  {
+    ptimer_callback = aTimerContext[local_current_running_timer_id].pTimerCallBack;
+    timer_process_id = aTimerContext[local_current_running_timer_id].TimerProcessID;
+
+    /**
+     * It should be good to check whether the TimeElapsed is greater or not than the tick left to be counted
+     * However, due to the inaccuracy of the reading of the time elapsed, it may return there is 1 tick
+     * to be left whereas the count is over
+     * A more secure implementation has been done with a flag to state whereas the full count has been written
+     * in the wakeuptimer or not
+     */
+    if(WakeupTimerLimitation != WakeupTimerValue_Overpassed)
+    {
+      if(aTimerContext[local_current_running_timer_id].TimerMode == hw_ts_Repeated)
+      {
+        UnlinkTimer(local_current_running_timer_id, SSR_Read_Not_Requested);
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+        __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+        HW_TS_Start(local_current_running_timer_id, aTimerContext[local_current_running_timer_id].CounterInit);
+
+        /* Disable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+      }
+      else
+      {
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+        __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+        HW_TS_Stop(local_current_running_timer_id);
+
+        /* Disable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+      }
+
+      HW_TS_RTC_Int_AppNot(timer_process_id, local_current_running_timer_id, ptimer_callback);
+    }
+    else
+    {
+      RescheduleTimerList();
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+      __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+    }
+  }
+  else
+  {
+    /**
+     * We should never end up in this case
+     * However, if due to any bug in the timer server this is the case, the mistake may not impact the user.
+     * We could just clean the interrupt flag and get out from this unexpected interrupt
+     */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+    /**
+     * make sure to clear the flags after checking the WUTWF.
+     * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+     * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+     * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+     * due to the autoreload feature
+     */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  return;
+}
+
+void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *hrtc)
+{
+  uint8_t loop;
+  uint32_t localmaxwakeuptimersetup;
+
+  /**
+   * Get RTC handler
+   */
+  phrtc = hrtc;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
+
+  /**
+   * Readout the user config
+   */
+  WakeupTimerDivider = (4 - ((uint32_t)(READ_BIT(RTC->CR, RTC_CR_WUCKSEL))));
+
+  AsynchPrescalerUserConfig = (uint8_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_A) >> (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)) + 1;
+
+  SynchPrescalerUserConfig = (uint16_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_S)) + 1;
+
+  /**
+   *  Margin is taken to avoid wrong calculation when the wrap around is there and some
+   *  application interrupts may have delayed the reading
+   */
+  localmaxwakeuptimersetup = ((((SynchPrescalerUserConfig - 1)*AsynchPrescalerUserConfig) - CFG_HW_TS_RTC_HANDLER_MAX_DELAY) >> WakeupTimerDivider);
+
+  if(localmaxwakeuptimersetup >= 0xFFFF)
+  {
+    MaxWakeupTimerSetup = 0xFFFF;
+  }
+  else
+  {
+    MaxWakeupTimerSetup = (uint16_t)localmaxwakeuptimersetup;
+  }
+
+  /**
+   * Configure EXTI module
+   */
+  LL_EXTI_EnableRisingTrig_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+  LL_EXTI_EnableIT_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+
+  if(TimerInitMode == hw_ts_InitMode_Full)
+  {
+    WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+
+    /**
+     * Initialize the timer server
+     */
+    for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++)
+    {
+      aTimerContext[loop].TimerIDStatus = TimerID_Free;
+    }
+
+    CurrentRunningTimerID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;   /**<  Set ID to non valid value */
+
+    __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);                       /**<  Disable the Wakeup Timer */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);     /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module  */
+    HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);       /**<  Clear pending bit in NVIC  */
+    __HAL_RTC_WAKEUPTIMER_ENABLE_IT(phrtc, RTC_IT_WUT);         /**<  Enable interrupt in RTC module  */
+  }
+  else
+  {
+    if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTF) != RESET)
+    {
+      /**
+       * Simulate that the Timer expired
+       */
+      HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_SetPriority(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO);   /**<  Set NVIC priority */
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+  return;
+}
+
+HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pftimeout_handler)
+{
+  HW_TS_ReturnStatus_t localreturnstatus;
+  uint8_t loop = 0;
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  while((loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[loop].TimerIDStatus != TimerID_Free))
+  {
+    loop++;
+  }
+
+  if(loop != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    aTimerContext[loop].TimerIDStatus = TimerID_Created;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+    aTimerContext[loop].TimerProcessID = TimerProcessID;
+    aTimerContext[loop].TimerMode = TimerMode;
+    aTimerContext[loop].pTimerCallBack = pftimeout_handler;
+    *pTimerId = loop;
+
+    localreturnstatus = hw_ts_Successful;
+  }
+  else
+  {
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+    localreturnstatus = hw_ts_Failed;
+  }
+
+  return(localreturnstatus);
+}
+
+void HW_TS_Delete(uint8_t timer_id)
+{
+  HW_TS_Stop(timer_id);
+
+  aTimerContext[timer_id].TimerIDStatus = TimerID_Free; /**<  release ID */
+
+  return;
+}
+
+void HW_TS_Stop(uint8_t timer_id)
+{
+  uint8_t localcurrentrunningtimerid;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);    /**<  Disable NVIC */
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
+  {
+    UnlinkTimer(timer_id, SSR_Read_Requested);
+    localcurrentrunningtimerid = CurrentRunningTimerID;
+
+    if(localcurrentrunningtimerid == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+    {
+      /**
+       * List is empty
+       */
+
+      /**
+       * Disable the timer
+       */
+      if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+      {
+        /**
+         * Wait for the flag to be back to 0 when the wakeup timer is enabled
+         */
+        while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == SET);
+      }
+      __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);   /**<  Disable the Wakeup Timer */
+
+      while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+      /**
+       * make sure to clear the flags after checking the WUTWF.
+       * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+       * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+       * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+       * due to the autoreload feature
+       */
+      __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+      __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+      HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);   /**<  Clear pending bit in NVIC */
+    }
+    else if(PreviousRunningTimerID != localcurrentrunningtimerid)
+    {
+      RescheduleTimerList();
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+  return;
+}
+
+void HW_TS_Start(uint8_t timer_id, uint32_t timeout_ticks)
+{
+  uint16_t time_elapsed;
+  uint8_t localcurrentrunningtimerid;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+  if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
+  {
+    HW_TS_Stop( timer_id );
+  }
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);    /**<  Disable NVIC */
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  aTimerContext[timer_id].TimerIDStatus = TimerID_Running;
+
+  aTimerContext[timer_id].CountLeft = timeout_ticks;
+  aTimerContext[timer_id].CounterInit = timeout_ticks;
+
+  time_elapsed =  linkTimer(timer_id);
+
+  localcurrentrunningtimerid = CurrentRunningTimerID;
+
+  if(PreviousRunningTimerID != localcurrentrunningtimerid)
+  {
+    RescheduleTimerList();
+  }
+  else
+  {
+    aTimerContext[timer_id].CountLeft -= time_elapsed;
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+  return;
+}
+
+uint16_t HW_TS_RTC_ReadLeftTicksToCount(void)
+{
+  uint32_t primask_bit;
+  uint16_t return_value, auro_reload_value, elapsed_time_value;
+
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();                /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+
+  if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+  {
+    auro_reload_value = (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT));
+
+    elapsed_time_value = ReturnTimeElapsed();
+
+    if(auro_reload_value > elapsed_time_value)
+    {
+      return_value = auro_reload_value - elapsed_time_value;
+    }
+    else
+    {
+      return_value = 0;
+    }
+  }
+  else
+  {
+    return_value = TIMER_LIST_EMPTY;
+  }
+
+  __set_PRIMASK(primask_bit);     /**< Restore PRIMASK bit*/
+
+  return (return_value);
+}
+
+__weak void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack)
+{
+  pTimerCallBack();
+
+  return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/hw_uart.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/hw_uart.c
new file mode 100644
index 000000000..9a553610d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/hw_uart.c
@@ -0,0 +1,318 @@
+/**
+ ******************************************************************************
+  * File Name          : Src/hw_uart.c
+  * Description        : HW UART source file for STM32WPAN Middleware.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "hw_conf.h"
+#if (CFG_HW_LPUART1_ENABLED == 1)
+extern UART_HandleTypeDef hlpuart1;
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+extern UART_HandleTypeDef huart1;
+#endif
+
+/* Macros --------------------------------------------------------------------*/
+#define HW_UART_RX_IT(__HANDLE__, __USART_BASE__)                                                   \
+        do{                                                                                         \
+            HW_##__HANDLE__##RxCb = cb;                                                             \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            HAL_UART_Receive_IT(&(__HANDLE__), p_data, size);                                       \
+        } while(0)
+
+#define HW_UART_TX_IT(__HANDLE__, __USART_BASE__)                                                   \
+        do{                                                                                         \
+            HW_##__HANDLE__##TxCb = cb;                                                             \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            HAL_UART_Transmit_IT(&(__HANDLE__), p_data, size);                                      \
+        } while(0)
+
+#define HW_UART_TX(__HANDLE__, __USART_BASE__)                                                      \
+        do{                                                                                         \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            hal_status = HAL_UART_Transmit(&(__HANDLE__), p_data, size, timeout);                   \
+        } while(0)
+
+/* Variables -----------------------------------------------------------------*/
+#if (CFG_HW_USART1_ENABLED == 1)
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+    DMA_HandleTypeDef HW_hdma_huart1_tx ={0};
+#endif
+    void (*HW_huart1RxCb)(void);
+    void (*HW_huart1TxCb)(void);
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+    DMA_HandleTypeDef HW_hdma_hlpuart1_tx ={0};
+#endif
+    void (*HW_hlpuart1RxCb)(void);
+    void (*HW_hlpuart1TxCb)(void);
+#endif
+
+void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_RX_IT(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_RX_IT(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  void (*cb)(void))
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_TX_IT(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_TX_IT(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout)
+{
+    HAL_StatusTypeDef hal_status = HAL_OK;
+    hw_status_t hw_status = hw_uart_ok;
+
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_TX(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_TX(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    switch (hal_status)
+    {
+        case HAL_OK:
+            hw_status = hw_uart_ok;
+            break;
+
+        case HAL_ERROR:
+            hw_status = hw_uart_error;
+            break;
+
+        case HAL_BUSY:
+            hw_status = hw_uart_busy;
+            break;
+
+        case HAL_TIMEOUT:
+            hw_status = hw_uart_to;
+            break;
+
+        default:
+            break;
+    }
+
+    return hw_status;
+}
+
+hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+{
+    HAL_StatusTypeDef hal_status = HAL_OK;
+    hw_status_t hw_status = hw_uart_ok;
+
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_huart1TxCb = cb;
+            huart1.Instance = USART1;
+            hal_status = HAL_UART_Transmit_DMA(&huart1, p_data, size);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_hlpuart1TxCb = cb;
+            hlpuart1.Instance = LPUART1;
+            hal_status = HAL_UART_Transmit_DMA(&hlpuart1, p_data, size);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    switch (hal_status)
+    {
+        case HAL_OK:
+            hw_status = hw_uart_ok;
+            break;
+
+        case HAL_ERROR:
+            hw_status = hw_uart_error;
+            break;
+
+        case HAL_BUSY:
+            hw_status = hw_uart_busy;
+            break;
+
+        case HAL_TIMEOUT:
+            hw_status = hw_uart_to;
+            break;
+
+        default:
+            break;
+    }
+
+    return hw_status;
+}
+
+void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HAL_UART_IRQHandler(&huart1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HAL_UART_IRQHandler(&hlpuart1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+        case hw_uart1:
+            HAL_DMA_IRQHandler(huart1.hdmatx);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+        case hw_lpuart1:
+            HAL_DMA_IRQHandler(hlpuart1.hdmatx);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+    switch ((uint32_t)huart->Instance)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case (uint32_t)USART1:
+            if(HW_huart1RxCb)
+            {
+                HW_huart1RxCb();
+            }
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case (uint32_t)LPUART1:
+            if(HW_hlpuart1RxCb)
+            {
+                HW_hlpuart1RxCb();
+            }
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+    switch ((uint32_t)huart->Instance)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case (uint32_t)USART1:
+            if(HW_huart1TxCb)
+            {
+                HW_huart1TxCb();
+            }
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case (uint32_t)LPUART1:
+            if(HW_hlpuart1TxCb)
+            {
+                HW_hlpuart1TxCb();
+            }
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/main.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/main.c
new file mode 100644
index 000000000..389fe64d7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/main.c
@@ -0,0 +1,579 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    main.c
+ * @author  MCD Application Team
+ * @brief   BLE application with BLE core
+ *
+  @verbatim
+  ==============================================================================
+                    ##### IMPORTANT NOTE #####
+  ==============================================================================
+
+  This application requests having the stm32wb5x_BLE_Stack_fw.bin binary
+  flashed on the Wireless Coprocessor.
+  If it is not the case, you need to use STM32CubeProgrammer to load the appropriate
+  binary.
+
+  All available binaries are located under following directory:
+  /Projects/STM32_Copro_Wireless_Binaries
+
+  Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+  Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the
+  detailed procedure to change the Wireless Coprocessor binary.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "app_entry.h"
+#include "app_common.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "stm32_lpm.h"
+#include "stm32_seq.h"
+#include "dbg_trace.h"
+#include "hw_conf.h"
+#include "otp.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+RTC_HandleTypeDef hrtc;
+
+UART_HandleTypeDef huart1;
+DMA_HandleTypeDef hdma_usart1_tx;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+void MX_USART1_UART_Init(void);
+static void MX_RF_Init(void);
+static void MX_RTC_Init(void);
+/* USER CODE BEGIN PFP */
+void PeriphClock_Config(void);
+static void Reset_Device( void );
+static void Reset_IPCC( void );
+static void Reset_BackupDomain( void );
+static void Init_Exti( void );
+static void Config_HSE(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+  
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+  Reset_Device();
+  Config_HSE();
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  PeriphClock_Config();
+  Init_Exti(); /**< Configure the system Power Mode */
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_RF_Init();
+  MX_RTC_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Init code for STM32_WPAN */  
+  APPE_Init();
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+	while(1)
+	{
+		UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure LSE Drive Capability 
+  */
+  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE
+                              |RCC_OSCILLATORTYPE_LSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RFWAKEUP
+                              |RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1;
+  PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+  PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN Smps */
+
+#if (CFG_USE_SMPS != 0)
+  /**
+   *  Configure and enable SMPS
+   *
+   *  The SMPS configuration is not yet supported by CubeMx
+   */
+  LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
+  LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70);
+  LL_PWR_SMPS_Enable();
+#endif
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief RF Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RF_Init(void)
+{
+
+  /* USER CODE BEGIN RF_Init 0 */
+
+  /* USER CODE END RF_Init 0 */
+
+  /* USER CODE BEGIN RF_Init 1 */
+
+  /* USER CODE END RF_Init 1 */
+  /* USER CODE BEGIN RF_Init 2 */
+
+  /* USER CODE END RF_Init 2 */
+
+}
+
+/**
+  * @brief RTC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RTC_Init(void)
+{
+
+  /* USER CODE BEGIN RTC_Init 0 */
+
+  /* USER CODE END RTC_Init 0 */
+
+  /* USER CODE BEGIN RTC_Init 1 */
+
+  /* USER CODE END RTC_Init 1 */
+  /** Initialize RTC Only 
+  */
+  hrtc.Instance = RTC;
+  hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
+  hrtc.Init.AsynchPrediv = CFG_RTC_ASYNCH_PRESCALER;
+  hrtc.Init.SynchPrediv = CFG_RTC_SYNCH_PRESCALER;
+  if (HAL_RTC_Init(&hrtc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN RTC_Init 2 */
+  /* Disable RTC registers write protection */
+  LL_RTC_DisableWriteProtection(RTC);
+
+  LL_RTC_WAKEUP_SetClock(RTC, CFG_RTC_WUCKSEL_DIVIDER);
+
+  /* Enable RTC registers write protection */
+  LL_RTC_EnableWriteProtection(RTC);
+  /* USER CODE END RTC_Init 2 */
+
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_8;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA2_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA2_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA2_Channel4_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(DMA2_Channel4_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+void PeriphClock_Config(void)
+{
+  #if (CFG_USB_INTERFACE_ENABLE != 0)
+	RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
+	RCC_CRSInitTypeDef RCC_CRSInitStruct = { 0 };
+
+	/**
+   * This prevents the CPU2 to disable the HSI48 oscillator when
+   * it does not use anymore the RNG IP
+   */
+  LL_HSEM_1StepLock( HSEM, 5 );
+
+  LL_RCC_HSI48_Enable();
+
+	while(!LL_RCC_HSI48_IsReady());
+
+	/* Select HSI48 as USB clock source */
+	PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+	PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+	HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+	/*Configure the clock recovery system (CRS)**********************************/
+
+	/* Enable CRS Clock */
+	__HAL_RCC_CRS_CLK_ENABLE();
+
+	/* Default Synchro Signal division factor (not divided) */
+	RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+
+	/* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+	RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+
+	/* HSI48 is synchronized with USB SOF at 1KHz rate */
+	RCC_CRSInitStruct.ReloadValue = RCC_CRS_RELOADVALUE_DEFAULT;
+	RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+
+	RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+
+	/* Set the TRIM[5:0] to the default value*/
+	RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+
+	/* Start automatic synchronization */
+	HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+#endif
+
+	return;
+}
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+
+static void Config_HSE(void)
+{
+    OTP_ID0_t * p_otp;
+
+  /**
+   * Read HSE_Tuning from OTP
+   */
+  p_otp = (OTP_ID0_t *) OTP_Read(0);
+  if (p_otp)
+  {
+    LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
+  }
+
+  return;
+}  
+
+
+static void Reset_Device( void )
+{
+#if ( CFG_HW_RESET_BY_FW == 1 )
+	Reset_BackupDomain();
+
+	Reset_IPCC();
+#endif
+
+	return;
+}
+
+static void Reset_IPCC( void )
+{
+	LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
+
+	LL_C1_IPCC_ClearFlag_CHx(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_ClearFlag_CHx(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C1_IPCC_DisableTransmitChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_DisableTransmitChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C1_IPCC_DisableReceiveChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_DisableReceiveChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	return;
+}
+
+static void Reset_BackupDomain( void )
+{
+	if ((LL_RCC_IsActiveFlag_PINRST() != FALSE) && (LL_RCC_IsActiveFlag_SFTRST() == FALSE))
+	{
+		HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+		/**
+		 *  Write twice the value to flush the APB-AHB bridge
+		 *  This bit shall be written in the register before writing the next one
+		 */
+		HAL_PWR_EnableBkUpAccess();
+
+		__HAL_RCC_BACKUPRESET_FORCE();
+		__HAL_RCC_BACKUPRESET_RELEASE();
+	}
+
+	return;
+}
+
+static void Init_Exti( void )
+{
+  /**< Disable all wakeup interrupt on CPU1  except IPCC(36), HSEM(38) */
+  LL_EXTI_DisableIT_0_31(~0);
+  LL_EXTI_DisableIT_32_63( (~0) & (~(LL_EXTI_LINE_36 | LL_EXTI_LINE_38)) );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += HAL_GetTickFreq();
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+  {
+    /************************************************************************************
+     * ENTER SLEEP MODE
+     ***********************************************************************************/
+    LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+    /**
+     * This option is used to ensure that store operations are completed
+     */
+  #if defined ( __CC_ARM)
+    __force_stores();
+  #endif
+
+    __WFI( );
+  }
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/stm32_lpm_if.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/stm32_lpm_if.c
new file mode 100644
index 000000000..1418e0a36
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/stm32_lpm_if.c
@@ -0,0 +1,297 @@
+/* USER CODE BEGIN Header */
+/**
+ ***************************************************************************************
+  * File Name          : stm32_lpm_if.c
+  * Description        : Low layer function to enter/exit low power modes (stop, sleep).
+ ***************************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+  
+/* Includes ------------------------------------------------------------------*/  
+#include "stm32_lpm_if.h"
+#include "stm32_lpm.h"
+#include "app_conf.h"
+/* USER CODE BEGIN include */
+
+/* USER CODE END include */
+
+/* Exported variables --------------------------------------------------------*/
+const struct UTIL_LPM_Driver_s UTIL_PowerDriver = 
+{
+  PWR_EnterSleepMode,
+  PWR_ExitSleepMode,
+  
+  PWR_EnterStopMode,
+  PWR_ExitStopMode, 
+  
+  PWR_EnterOffMode,
+  PWR_ExitOffMode,
+};
+
+/* Private function prototypes -----------------------------------------------*/
+static void Switch_On_HSI( void );
+/* USER CODE BEGIN Private_Function_Prototypes */
+
+/* USER CODE END Private_Function_Prototypes */
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN Private_Typedef */
+
+/* USER CODE END Private_Typedef */
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Private_Define */
+
+/* USER CODE END Private_Define */
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Private_Macro */
+
+/* USER CODE END Private_Macro */
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN Private_Variables */
+
+/* USER CODE END Private_Variables */
+
+/* Functions Definition ------------------------------------------------------*/
+/**
+  * @brief Enters Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_EnterOffMode( void )
+{
+/* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
+  /************************************************************************************
+   * ENTER OFF MODE
+   ***********************************************************************************/
+  /*
+   * There is no risk to clear all the WUF here because in the current implementation, this API is called
+   * in critical section. If an interrupt occurs while in that critical section before that point,
+   * the flag is set and will be cleared here but the system will not enter Off Mode
+   * because an interrupt is pending in the NVIC. The ISR will be executed when moving out
+   * of this critical section
+   */
+  LL_PWR_ClearFlag_WU( );
+
+  LL_PWR_SetPowerMode( LL_PWR_MODE_STANDBY );
+
+  LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores( );
+#endif
+
+  __WFI( );
+/* USER CODE END PWR_EnterOffMode */
+}
+
+/**
+  * @brief Exits Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_ExitOffMode( void )
+{
+/* USER CODE BEGIN PWR_ExitOffMode */
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitOffMode */
+}
+
+/**
+  * @brief Enters Low Power Stop Mode
+  * @note ARM exists the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterStopMode( void )
+{
+/* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
+  /**
+   * This function is called from CRITICAL SECTION
+   */
+  while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
+
+  if ( ! LL_HSEM_1StepLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID ) )
+  {
+    if( LL_PWR_IsActiveFlag_C2DS( ) )
+    {
+      /* Release ENTRY_STOP_MODE semaphore */
+      LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
+
+      /**
+       * The switch on HSI before entering Stop Mode is required on Cut2.0
+       * It is useless from Cut2.1
+       */
+      Switch_On_HSI( );
+    }
+  }
+  else
+  {
+    /**
+     * The switch on HSI before entering Stop Mode is required on Cut2.0
+     * It is useless from Cut2.1
+     */
+    Switch_On_HSI( );
+  }
+
+  /* Release RCC semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  /************************************************************************************
+   * ENTER STOP MODE
+   ***********************************************************************************/
+  LL_PWR_SetPowerMode( LL_PWR_MODE_STOP2 );
+
+  LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores( );
+#endif
+
+  __WFI();
+/* USER CODE END PWR_EnterStopMode */
+}
+
+/**
+  * @brief Exits Low Power Stop Mode
+  * @note Enable the pll at 32MHz
+  * @param none
+  * @retval none
+  */
+void PWR_ExitStopMode( void )
+{
+/* USER CODE BEGIN PWR_ExitStopMode */
+  /**
+   * This function is called from CRITICAL SECTION
+   */
+
+  /* Release ENTRY_STOP_MODE semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
+
+  while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
+
+  if(LL_RCC_GetSysClkSource( ) == LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+    LL_RCC_HSE_Enable( );
+    while(!LL_RCC_HSE_IsReady( ));
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
+    while (LL_RCC_GetSysClkSource( ) != LL_RCC_SYS_CLKSOURCE_STATUS_HSE);
+  }
+  else
+  {
+    /**
+     * As long as the current application is fine with HSE as system clock source,
+     * there is nothing to do here
+     */
+  }
+
+  /* Release RCC semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitStopMode */
+}
+
+/**
+  * @brief Enters Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterSleepMode( void )
+{
+/* USER CODE BEGIN PWR_EnterSleepMode */
+
+  HAL_SuspendTick();
+
+  /************************************************************************************
+   * ENTER SLEEP MODE
+   ***********************************************************************************/
+  LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+
+  __WFI( );
+/* USER CODE END PWR_EnterSleepMode */
+}
+
+/**
+  * @brief Exits Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_ExitSleepMode( void )
+{
+/* USER CODE BEGIN PWR_ExitSleepMode */
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitSleepMode */
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+  * @brief Switch the system clock on HSI
+  * @param none
+  * @retval none
+  */
+static void Switch_On_HSI( void )
+{
+  LL_RCC_HSI_Enable( );
+  while(!LL_RCC_HSI_IsReady( ));
+  LL_RCC_SetSysClkSource( LL_RCC_SYS_CLKSOURCE_HSI );
+  LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSI);
+  while (LL_RCC_GetSysClkSource( ) != LL_RCC_SYS_CLKSOURCE_STATUS_HSI);
+}
+
+/* USER CODE BEGIN Private_Functions */
+
+/* USER CODE END Private_Functions */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..12c69084e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,227 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32wbxx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_usart1_tx;
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_HSEM_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief RTC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspInit 0 */
+  HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+  /**
+  *  Write twice the value to flush the APB-AHB bridge
+  *  This bit shall be written in the register before writing the next one
+  */
+  HAL_PWR_EnableBkUpAccess();
+
+  __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); /**< Select LSI as RTC Input */
+  /* USER CODE END RTC_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_RTC_ENABLE();
+  /* USER CODE BEGIN RTC_MspInit 1 */
+  HAL_RTCEx_EnableBypassShadow(hrtc);
+  /* USER CODE END RTC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspDeInit 0 */
+
+  /* USER CODE END RTC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RTC_DISABLE();
+  /* USER CODE BEGIN RTC_MspDeInit 1 */
+
+  /* USER CODE END RTC_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspInit 0 */
+
+  /* USER CODE END USART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**USART1 GPIO Configuration    
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* USART1 DMA Init */
+    /* USART1_TX Init */
+    hdma_usart1_tx.Instance = DMA2_Channel4;
+    hdma_usart1_tx.Init.Request = DMA_REQUEST_USART1_TX;
+    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx);
+
+    /* USART1 interrupt Init */
+    HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspInit 1 */
+
+  /* USER CODE END USART1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+  /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+  
+    /**USART1 GPIO Configuration    
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
+
+    /* USART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmatx);
+
+    /* USART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+  /* USER CODE END USART1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..b5cc21eb6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/stm32wbxx_it.c
@@ -0,0 +1,274 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_usart1_tx;
+extern UART_HandleTypeDef huart1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+
+  /* USER CODE END USART1_IRQn 0 */
+  HAL_UART_IRQHandler(&huart1);
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA2 channel4 global interrupt.
+  */
+void DMA2_Channel4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2_Channel4_IRQn 0 */
+
+  /* USER CODE END DMA2_Channel4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart1_tx);
+  /* USER CODE BEGIN DMA2_Channel4_IRQn 1 */
+
+  /* USER CODE END DMA2_Channel4_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW1_EXTI_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW2_EXTI_IRQHandler(void)
+{
+
+}
+
+void RTC_WKUP_IRQHandler(void)
+{
+  HW_TS_RTC_Wakeup_Handler();
+}
+
+void IPCC_C1_TX_IRQHandler(void)
+{
+  HW_IPCC_Tx_Handler();
+
+  return;
+}
+
+void IPCC_C1_RX_IRQHandler(void)
+{
+  HW_IPCC_Rx_Handler();
+  return;
+}
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..156ed20d3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/Core/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                        4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/BLE_TransparentMode.ewd b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/BLE_TransparentMode.ewd
new file mode 100644
index 000000000..8433158a4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/BLE_TransparentMode.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		BLE_TransparentMode
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/BLE_TransparentMode.ewp b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/BLE_TransparentMode.ewp
new file mode 100644
index 000000000..c751d8b34
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/BLE_TransparentMode.ewp
@@ -0,0 +1,1226 @@
+
+
+    3
+    
+        BLE_TransparentMode
+        
+            ARM
+        
+        1
+        
+            General
+            3
+            
+                30
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            ICCARM
+            2
+            
+                34
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            AARM
+            2
+            
+                10
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            OBJCOPY
+            0
+            
+                1
+                1
+                1
+                
+                
+                
+                
+                
+            
+        
+        
+            CUSTOM
+            3
+            
+                
+                
+                0
+            
+        
+        
+            BICOMP
+            0
+            
+        
+        
+            BUILDACTION
+            1
+            
+                
+                
+            
+        
+        
+            ILINK
+            0
+            
+                20
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            IARCHIVE
+            0
+            
+                0
+                1
+                1
+                
+                
+                
+            
+        
+        
+            BILINK
+            0
+            
+        
+    
+    
+        Application
+        
+            EWARM
+            
+                $PROJ_DIR$\startup_stm32wb35xx_cm4.s
+            
+        
+        
+            User
+            
+                Core
+                
+                    $PROJ_DIR$\..\Core\Src\app_entry.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\app_debug.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\hw_timerserver.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\hw_uart.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\main.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\stm32_lpm_if.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\stm32wbxx_hal_msp.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\stm32wbxx_it.c
+                
+            
+            
+                STM32_WPAN
+                
+                    App
+                    
+                        $PROJ_DIR$\..\STM32_WPAN\App\tm.c
+                    
+                
+                
+                    Target
+                    
+                        $PROJ_DIR$\..\STM32_WPAN\Target\hw_ipcc.c
+                    
+                
+            
+        
+    
+    
+        Doc
+        
+            $PROJ_DIR$\..\readme.txt
+        
+    
+    
+        Drivers
+        
+            BSP
+            
+                NUCLEO-WB35CE
+                
+                    $PROJ_DIR$\..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE\nucleo_wb35ce.c
+                
+            
+        
+        
+            CMSIS
+            
+                $PROJ_DIR$\..\Core\Src\system_stm32wbxx.c
+            
+        
+        
+            STM32WBxx_HAL_Driver
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_cortex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_gpio.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_hsem.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_ipcc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rtc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rtc_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_uart.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_uart_ex.c
+            
+        
+    
+    
+        Middlewares
+        
+            STM32_WPAN
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\dbg_trace.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\hci_tl_if.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\lhci\lhci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\template\osal.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\otp.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\shci\shci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\shci_tl_if.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\stm_list.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\stm_queue.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\tl_mbox.c
+            
+        
+    
+    
+        Utilities
+        
+            $PROJ_DIR$\..\..\..\..\..\..\Utilities\lpm\tiny_lpm\stm32_lpm.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\..\..\Utilities\sequencer\stm32_seq.c
+        
+    
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/Project.eww
new file mode 100644
index 000000000..7cc6a64be
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\BLE_TransparentMode.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..8f3317a41
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/ble_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/ble_conf.h
new file mode 100644
index 000000000..ec2d0e166
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/ble_conf.h
@@ -0,0 +1,92 @@
+/**
+ ******************************************************************************
+  * File Name          : App/ble_conf.h
+  * Description        : Configuration file for BLE Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef BLE_CONF_H
+#define BLE_CONF_H
+
+#include "app_conf.h"
+
+/******************************************************************************
+ *
+ * BLE SERVICES CONFIGURATION
+ * blesvc
+ *
+ ******************************************************************************/
+
+ /**
+ * This setting shall be set to '1' if the device needs to support the Peripheral Role
+ * In the MS configuration, both BLE_CFG_PERIPHERAL and BLE_CFG_CENTRAL shall be set to '1'
+ */
+#define BLE_CFG_PERIPHERAL                                                     1
+
+/**
+ * This setting shall be set to '1' if the device needs to support the Central Role
+ * In the MS configuration, both BLE_CFG_PERIPHERAL and BLE_CFG_CENTRAL shall be set to '1'
+ */
+#define BLE_CFG_CENTRAL                                                        0
+
+/**
+ * There is one handler per service enabled
+ * Note: There is no handler for the Device Information Service
+ *
+ * This shall take into account all registered handlers
+ * (from either the provided services or the custom services)
+ */
+#define BLE_CFG_SVC_MAX_NBR_CB                                                 7
+
+#define BLE_CFG_CLT_MAX_NBR_CB                                                 0
+
+/******************************************************************************
+ * Device Information Service (DIS)
+ ******************************************************************************/
+/**< Options: Supported(1) or Not Supported(0) */
+#define BLE_CFG_DIS_MANUFACTURER_NAME_STRING                                   
+#define BLE_CFG_DIS_MODEL_NUMBER_STRING                                        1
+#define BLE_CFG_DIS_SERIAL_NUMBER_STRING                                       
+#define BLE_CFG_DIS_HARDWARE_REVISION_STRING                                   
+#define BLE_CFG_DIS_FIRMWARE_REVISION_STRING                                   
+#define BLE_CFG_DIS_SOFTWARE_REVISION_STRING                                   
+#define BLE_CFG_DIS_SYSTEM_ID                                                  1
+#define BLE_CFG_DIS_IEEE_CERTIFICATION                                         
+#define BLE_CFG_DIS_PNP_ID                                                     
+
+/**
+ * device information service characteristic lengths
+ */
+#define BLE_CFG_DIS_SYSTEM_ID_LEN_MAX                                        (8)
+#define BLE_CFG_DIS_MODEL_NUMBER_STRING_LEN_MAX                              (32)
+#define BLE_CFG_DIS_SERIAL_NUMBER_STRING_LEN_MAX                             (32)
+#define BLE_CFG_DIS_FIRMWARE_REVISION_STRING_LEN_MAX                         (32)
+#define BLE_CFG_DIS_HARDWARE_REVISION_STRING_LEN_MAX                         (32)
+#define BLE_CFG_DIS_SOFTWARE_REVISION_STRING_LEN_MAX                         (32)
+#define BLE_CFG_DIS_MANUFACTURER_NAME_STRING_LEN_MAX                         (32)
+#define BLE_CFG_DIS_IEEE_CERTIFICATION_LEN_MAX                               (32)
+#define BLE_CFG_DIS_PNP_ID_LEN_MAX                                           (7)
+
+/******************************************************************************
+ * GAP Service - Apprearance
+ ******************************************************************************/
+
+#define BLE_CFG_UNKNOWN_APPEARANCE                  (0)
+#define BLE_CFG_HR_SENSOR_APPEARANCE                (832)
+#define BLE_CFG_GAP_APPEARANCE                      (BLE_CFG_UNKNOWN_APPEARANCE)
+
+#endif /*BLE_CONF_H */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/ble_dbg_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/ble_dbg_conf.h
new file mode 100644
index 000000000..1f9b21135
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/ble_dbg_conf.h
@@ -0,0 +1,199 @@
+/**
+ ******************************************************************************
+  * File Name          : App/ble_dbg_conf.h
+  * Description        : Debug configuration file for BLE Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __BLE_DBG_CONF_H
+#define __BLE_DBG_CONF_H
+
+/**
+ * Enable or Disable traces from BLE
+ */
+
+#define BLE_DBG_APP_EN             0
+#define BLE_DBG_DIS_EN             0
+#define BLE_DBG_HRS_EN             0
+#define BLE_DBG_SVCCTL_EN          0
+#define BLE_DBG_BLS_EN             0
+#define BLE_DBG_HTS_EN             0
+#define BLE_DBG_P2P_STM_EN         0
+
+/**
+ * Macro definition
+ */
+#if ( BLE_DBG_APP_EN != 0 )
+#define BLE_DBG_APP_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_APP_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_DIS_EN != 0 )
+#define BLE_DBG_DIS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_DIS_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_HRS_EN != 0 )
+#define BLE_DBG_HRS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HRS_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_P2P_STM_EN != 0 )
+#define BLE_DBG_P2P_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_P2P_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_TEMPLATE_STM_EN != 0 )
+#define BLE_DBG_TEMPLATE_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_TEMPLATE_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_EDS_STM_EN != 0 )
+#define BLE_DBG_EDS_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_EDS_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_LBS_STM_EN != 0 )
+#define BLE_DBG_LBS_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_LBS_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_SVCCTL_EN != 0 )
+#define BLE_DBG_SVCCTL_MSG          PRINT_MESG_DBG
+#else
+#define BLE_DBG_SVCCTL_MSG          PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_CTS_EN != 0)
+#define BLE_DBG_CTS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_CTS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HIDS_EN != 0)
+#define BLE_DBG_HIDS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_HIDS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_PASS_EN != 0)
+#define BLE_DBG_PASS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_PASS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_BLS_EN != 0)
+#define BLE_DBG_BLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_BLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HTS_EN != 0)
+#define BLE_DBG_HTS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HTS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_ANS_EN != 0)
+#define BLE_DBG_ANS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_ANS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_ESS_EN != 0)
+#define BLE_DBG_ESS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_ESS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_GLS_EN != 0)
+#define BLE_DBG_GLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_GLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_BAS_EN != 0)
+#define BLE_DBG_BAS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_BAS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_RTUS_EN != 0)
+#define BLE_DBG_RTUS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_RTUS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HPS_EN != 0)
+#define BLE_DBG_HPS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HPS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_TPS_EN != 0)
+#define BLE_DBG_TPS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_TPS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_LLS_EN != 0)
+#define BLE_DBG_LLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_LLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_IAS_EN != 0)
+#define BLE_DBG_IAS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_IAS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_WSS_EN != 0)
+#define BLE_DBG_WSS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_WSS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_LNS_EN != 0)
+#define BLE_DBG_LNS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_LNS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_SCPS_EN != 0)
+#define BLE_DBG_SCPS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_SCPS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_DTS_EN != 0)
+#define BLE_DBG_DTS_MSG             PRINT_MESG_DBG
+#define BLE_DBG_DTS_BUF             PRINT_LOG_BUFF_DBG
+#else
+#define BLE_DBG_DTS_MSG             PRINT_NO_MESG
+#define BLE_DBG_DTS_BUF             PRINT_NO_MESG
+#endif
+
+#endif /*__BLE_DBG_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/tm.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/tm.c
new file mode 100644
index 000000000..aa215bfdf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/tm.c
@@ -0,0 +1,538 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    tm.c
+ * @author  MCD Application Team
+ * @brief   Transparent mode
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "app_common.h"
+#include "tl.h"
+#include "mbox_def.h"
+#include "lhci.h"
+#include "shci.h"
+#include "stm_list.h"
+#include "tm.h"
+#include "stm32_lpm.h"
+#include "shci_tl.h"
+#include "stm32_seq.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+typedef enum
+{
+  LOW_POWER_MODE_DISABLE,
+  LOW_POWER_MODE_ENABLE,
+}LowPowerModeStatus_t;
+
+typedef enum
+{
+  WAITING_TYPE,
+  WAITING_LENGTH,
+  WAITING_PAYLOAD
+}HciReceiveStatus_t;
+
+typedef enum
+{
+  TX_ONGOING,
+  TX_DONE
+}HostTxStatus_t;
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static TL_CmdPacket_t BleCmdBuffer;
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t HciAclDataBuffer[sizeof(TL_PacketHeader_t) + 5 + 251];
+
+static uint8_t RxHostData[5];
+static HciReceiveStatus_t HciReceiveStatus;
+static TL_CmdPacket_t SysLocalCmd;
+static uint8_t *pHostRx;
+static tListNode  HostTxQueue;
+static TL_EvtPacket_t *pTxToHostPacket;
+static HostTxStatus_t HostTxStatus;
+static MB_RefTable_t * p_RefTable;
+static uint8_t SysLocalCmdStatus;
+static LowPowerModeStatus_t LowPowerModeStatus;
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+static void RxCpltCallback(void);
+static void HostTxCb( void );
+static void TM_SysLocalCmd( void );
+static void TM_TxToHost( void );
+static void TM_BleEvtRx( TL_EvtPacket_t *phcievt );
+static void TM_AclDataAck( void );
+#if (CFG_HW_LPUART1_ENABLED == 1)
+extern void MX_LPUART1_UART_Init(void);
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+extern void MX_USART1_UART_Init(void);
+#endif
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void TM_Init( void  )
+{
+/* USER CODE BEGIN TM_Init_1 */
+
+/* USER CODE END TM_Init_1 */
+  TL_BLE_InitConf_t tl_ble_init_conf;
+  uint32_t ipccdba;
+  SHCI_C2_Ble_Init_Cmd_Packet_t ble_init_cmd_packet =
+  {
+    {{0,0,0}},                          /**< Header unused */
+    {0,                                 /** pBleBufferAddress not used */
+    0,                                  /** BleBufferSize not used */
+    CFG_BLE_NUM_GATT_ATTRIBUTES,
+    CFG_BLE_NUM_GATT_SERVICES,
+    CFG_BLE_ATT_VALUE_ARRAY_SIZE,
+    CFG_BLE_NUM_LINK,
+    CFG_BLE_DATA_LENGTH_EXTENSION,
+    CFG_BLE_PREPARE_WRITE_LIST_SIZE,
+    CFG_BLE_MBLOCK_COUNT,
+    CFG_BLE_MAX_ATT_MTU,
+    CFG_BLE_SLAVE_SCA,
+    CFG_BLE_MASTER_SCA,
+    CFG_BLE_LSE_SOURCE,
+    CFG_BLE_MAX_CONN_EVENT_LENGTH,
+    CFG_BLE_HSE_STARTUP_TIME,
+    CFG_BLE_VITERBI_MODE,
+    CFG_BLE_LL_ONLY,
+    0}
+  };
+
+  ipccdba = READ_BIT( FLASH->IPCCBR, FLASH_IPCCBR_IPCCDBA );
+#ifndef LITTLE_DORY    
+  p_RefTable = (MB_RefTable_t*)((ipccdba<<2) + SRAM2A_BASE);
+#else
+  p_RefTable = (MB_RefTable_t*)((ipccdba<<2) + (0x20008000));
+#endif  
+
+  tl_ble_init_conf.p_cmdbuffer = (uint8_t*)&BleCmdBuffer;
+  tl_ble_init_conf.p_AclDataBuffer = HciAclDataBuffer;
+  tl_ble_init_conf.IoBusEvtCallBack = TM_BleEvtRx;
+  tl_ble_init_conf.IoBusAclDataTxAck = TM_AclDataAck;
+  TL_BLE_Init( (void*) &tl_ble_init_conf );
+
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP_BLE, UTIL_LPM_DISABLE);
+  UTIL_LPM_SetStopMode( 1<evtserial.type == TL_ACL_DATA_PKT_TYPE)
+      {
+        /**
+         * The uart interrupt shall be disable when the HAL is called to send data
+         * This is because in the Rx uart handler, the HAL is called to receive new data
+         */
+        DISABLE_IRQ();
+        HW_UART_Transmit_IT(CFG_UART_GUI, (uint8_t *)&((TL_AclDataPacket_t *)pTxToHostPacket)->AclDataSerial, ((TL_AclDataPacket_t *)pTxToHostPacket)->AclDataSerial.length + 5, HostTxCb);
+        RESTORE_PRIMASK();
+      }
+      else
+      {
+        /**
+         * The uart interrupt shall be disable when the HAL is called to send data
+         * This is because in the Rx uart handler, the HAL is called to receive new data
+         */
+        DISABLE_IRQ();
+        HW_UART_Transmit_IT(CFG_UART_GUI, (uint8_t *)&pTxToHostPacket->evtserial, pTxToHostPacket->evtserial.evt.plen + TL_EVT_HDR_SIZE, HostTxCb);
+        RESTORE_PRIMASK();
+      }
+    }
+    else
+    {
+      HostTxCb( );
+    }
+  }
+
+  return;
+}
+
+static void TM_SysLocalCmd ( void )
+{
+  switch( SysLocalCmd.cmdserial.cmd.cmdcode )
+  {
+    case LHCI_OPCODE_C1_WRITE_REG:
+      LHCI_C1_Write_Register( &SysLocalCmd );
+      break;
+
+    case LHCI_OPCODE_C1_READ_REG:
+      LHCI_C1_Read_Register( &SysLocalCmd );
+      break;
+#ifndef LITTLE_DORY
+    case LHCI_OPCODE_C1_DEVICE_INF:
+      LHCI_C1_Read_Device_Information( &SysLocalCmd );
+      break;
+#endif      
+
+    default:
+      
+#ifndef LITTLE_DORY
+      ((TL_CcEvt_t *)(((TL_EvtPacket_t*)&SysLocalCmd)->evtserial.evt.payload))->cmdcode = SysLocalCmd.cmdserial.cmd.cmdcode;
+      ((TL_EvtPacket_t*)&SysLocalCmd)->evtserial.evt.plen = TL_EVT_CS_PAYLOAD_SIZE;
+      ((TL_CcEvt_t *)(((TL_EvtPacket_t*)&SysLocalCmd)->evtserial.evt.payload))->payload[0] = 0x01;
+#else      
+      ((TL_CcEvt_t *)(((TL_EvtPacket_t*)&SysLocalCmd)->evtserial.evt.payload))->cmdcode = LHCI_OPCODE_C1_DEVICE_INF;
+      ((TL_EvtPacket_t*)&SysLocalCmd)->evtserial.evt.plen = TL_EVT_HDR_SIZE + sizeof(LHCI_C1_Device_Information_ccrp_t);
+      ((TL_CcEvt_t *)(((TL_EvtPacket_t*)&SysLocalCmd)->evtserial.evt.payload))->payload[0] = 0x00;
+#endif      
+      ((TL_CcEvt_t *)(((TL_EvtPacket_t*)&SysLocalCmd)->evtserial.evt.payload))->numcmd = 1;
+      ((TL_EvtPacket_t*)&SysLocalCmd)->evtserial.type = TL_LOCRSP_PKT_TYPE;
+      ((TL_EvtPacket_t*)&SysLocalCmd)->evtserial.evt.evtcode = TL_BLEEVT_CC_OPCODE;
+
+      break;
+  }
+
+  LST_insert_tail (&HostTxQueue, (tListNode *)&SysLocalCmd);
+  UTIL_SEQ_SetTask( 1<p_sys_table->pcmd_buffer))->cmdserial);
+          memcpy(pHostRx, RxHostData, 4);
+          buffer_index = 4;
+          break;
+
+        case TL_LOCCMD_PKT_TYPE:
+          nb_bytes_to_receive = pHostRx[3];
+          pHostRx = (uint8_t*)&SysLocalCmd.cmdserial;
+          memcpy(pHostRx, RxHostData, 4);
+          buffer_index = 4;
+          break;
+
+        case TL_ACL_DATA_PKT_TYPE:
+          nb_bytes_to_receive = pHostRx[3] + (pHostRx[4] << 8);
+          pHostRx = (uint8_t*)&(((TL_AclDataPacket_t*)(p_RefTable->p_ble_table->phci_acl_data_buffer))->AclDataSerial);
+          memcpy(pHostRx, RxHostData, 5);
+          buffer_index = 5;
+          break;
+
+        default:
+          nb_bytes_to_receive = pHostRx[3];
+          pHostRx = (uint8_t*)&(((TL_CmdPacket_t*)(p_RefTable->p_ble_table->pcmd_buffer))->cmdserial);
+          memcpy(pHostRx, RxHostData, 4);
+          buffer_index = 4;
+          break;
+      }
+
+      if(nb_bytes_to_receive)
+      {
+        HciReceiveStatus = WAITING_PAYLOAD;
+      }
+      else
+      {
+        switch ( packet_indicator )
+        {
+          case TL_SYSCMD_PKT_TYPE:
+            UTIL_SEQ_SetTask( 1<= (TL_EvtPacket_t *)(p_RefTable->p_mem_manager_table->blepool)) && (pTxToHostPacket < ( (TL_EvtPacket_t *)((p_RefTable->p_mem_manager_table->blepool) + p_RefTable->p_mem_manager_table->blepoolsize))))
+  {
+    TL_MM_EvtDone(pTxToHostPacket);
+  }
+
+  if ( LST_is_empty( &HostTxQueue ) == FALSE )
+  {
+    UTIL_SEQ_SetTask( 1<IPCCBR, FLASH_IPCCBR_IPCCDBA );
+#ifndef LITTLE_DORY  
+  p_ref_table = (MB_RefTable_t*)((ipccdba<<2) + SRAM2A_BASE);
+#else
+  p_ref_table = (MB_RefTable_t*)((ipccdba<<2) + (0x20008000));
+#endif  
+
+  SysLocalCmdStatus = 1;
+
+  p_cmd_buffer = (TL_CmdPacket_t *)(p_ref_table->p_sys_table->pcmd_buffer);
+
+  p_cmd_buffer->cmdserial.cmd.cmdcode = cmd_code;
+  p_cmd_buffer->cmdserial.cmd.plen = len_cmd_payload;
+
+  memcpy(p_cmd_buffer->cmdserial.cmd.payload, p_cmd_payload, len_cmd_payload );
+
+  TL_SYS_SendCmd( 0, 0 );
+
+  UTIL_SEQ_WaitEvt( 1<< CFG_IDLEEVT_SYSTEM_HCI_CMD_EVT_RSP_ID );
+
+  /**
+   * The command complete of a system command does not have the header
+   * It starts immediately with the evtserial field
+   */
+  memcpy( &(p_rsp_status->evtserial), p_cmd_buffer, ((TL_EvtSerial_t*)p_cmd_buffer)->evt.plen + TL_EVT_HDR_SIZE );
+
+  return;
+}
+
+
+/* USER CODE BEGIN FD_WRAP_FUNCTIONS*/
+
+/* USER CODE END FD_WRAP_FUNCTIONS*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/tm.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/tm.h
new file mode 100644
index 000000000..ed49b4036
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/tm.h
@@ -0,0 +1,97 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    tm.h
+  * @author  MCD Application Team
+  * @brief   Transparent mode interface
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TM_H
+#define __TM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "tl.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  /**
+   * @brief  Transparent mode initialization
+   *
+   * @param  None
+   * @retval None
+   */
+  void TM_Init( void );
+  /**
+   * @brief  Call back to receive system command response
+   *
+   * @param  None
+   * @retval None
+   */
+  void TM_SysCmdRspCb(TL_EvtPacket_t * p_cmd_resp);
+
+  /**
+   * @brief  Call back to receive system user user
+   *
+   * @param  None
+   * @retval None
+   */
+  void TM_SysUserEvtRxCb(TL_EvtPacket_t * p_evt_rx);
+
+/* USER CODE BEGIN EFP */
+  /**
+   * @brief  Set the low power mode
+   *
+   * @param  None
+   * @retval None
+   */
+  void TM_SetLowPowerMode( void );
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__TM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/Target/hw_ipcc.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/Target/hw_ipcc.c
new file mode 100644
index 000000000..0f839543a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/STM32_WPAN/Target/hw_ipcc.c
@@ -0,0 +1,523 @@
+/**
+ ******************************************************************************
+  * File Name          : Target/hw_ipcc.c
+  * Description        : Hardware IPCC source file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "mbox_def.h"
+
+/* Global variables ---------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+#define HW_IPCC_TX_PENDING( channel ) ( !(LL_C1_IPCC_IsActiveFlag_CHx( IPCC, channel )) ) &&  (((~(IPCC->C1MR)) & (channel << 16U)))
+#define HW_IPCC_RX_PENDING( channel )  (LL_C2_IPCC_IsActiveFlag_CHx( IPCC, channel )) && (((~(IPCC->C1MR)) & (channel << 0U)))
+
+/* Private macros ------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static void (*FreeBufCb)( void );
+
+/* Private function prototypes -----------------------------------------------*/
+static void HW_IPCC_BLE_EvtHandler( void );
+static void HW_IPCC_BLE_AclDataEvtHandler( void );
+static void HW_IPCC_MM_FreeBufHandler( void );
+static void HW_IPCC_SYS_CmdEvtHandler( void );
+static void HW_IPCC_SYS_EvtHandler( void );
+static void HW_IPCC_TRACES_EvtHandler( void );
+
+#ifdef THREAD_WB
+static void HW_IPCC_OT_CmdEvtHandler( void );
+static void HW_IPCC_THREAD_NotEvtHandler( void );
+static void HW_IPCC_THREAD_CliNotEvtHandler( void );
+#endif
+
+#ifdef MAC_802_15_4_WB
+static void HW_IPCC_MAC_802_15_4_CmdEvtHandler( void );
+static void HW_IPCC_MAC_802_15_4_NotEvtHandler( void );
+#endif
+
+#ifdef ZIGBEE_WB
+static void HW_IPCC_ZIGBEE_CmdEvtHandler( void );
+static void HW_IPCC_ZIGBEE_StackNotifEvtHandler( void );
+static void HW_IPCC_ZIGBEE_CliNotifEvtHandler( void );
+#endif
+
+/* Public function definition -----------------------------------------------*/
+
+/******************************************************************************
+ * INTERRUPT HANDLER
+ ******************************************************************************/
+void HW_IPCC_Rx_Handler( void )
+{
+  if (HW_IPCC_RX_PENDING( HW_IPCC_SYSTEM_EVENT_CHANNEL ))
+  {
+      HW_IPCC_SYS_EvtHandler();
+  }
+#ifdef MAC_802_15_4_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_MAC_802_15_4_NotEvtHandler();
+  }
+#endif /* MAC_802_15_4_WB */
+#ifdef THREAD_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_THREAD_NotEvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_THREAD_CliNotEvtHandler();
+  }
+#endif /* THREAD_WB */
+#ifdef ZIGBEE_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_ZIGBEE_StackNotifEvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
+  {
+      HW_IPCC_ZIGBEE_CliNotifEvtHandler();
+  }
+#endif /* ZIGBEE_WB */
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_BLE_EVENT_CHANNEL ))
+  {
+    HW_IPCC_BLE_EvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_TRACES_CHANNEL ))
+  {
+    HW_IPCC_TRACES_EvtHandler();
+  }
+
+  return;
+}
+
+void HW_IPCC_Tx_Handler( void )
+{
+  if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_SYS_CmdEvtHandler();
+  }
+#ifdef MAC_802_15_4_WB
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_MAC_802_15_4_CmdEvtHandler();
+  }
+#endif /* MAC_802_15_4_WB */
+#ifdef THREAD_WB
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_OT_CmdEvtHandler();
+  }
+#endif /* THREAD_WB */
+#ifdef ZIGBEE_WB
+  if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
+  {
+      HW_IPCC_ZIGBEE_CmdEvtHandler();
+  }
+#endif /* ZIGBEE_WB */
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_SYS_CmdEvtHandler();
+  }
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ))
+  {
+    HW_IPCC_MM_FreeBufHandler();
+  }
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_HCI_ACL_DATA_CHANNEL ))
+  {
+    HW_IPCC_BLE_AclDataEvtHandler();
+  }
+
+  return;
+}
+/******************************************************************************
+ * GENERAL
+ ******************************************************************************/
+void HW_IPCC_Enable( void )
+{
+  /**
+   * When the device is out of standby, it is required to use the EXTI mechanism to wakeup CPU2
+   */
+  LL_C2_EXTI_EnableEvent_32_63( LL_EXTI_LINE_41 );
+  LL_EXTI_EnableRisingTrig_32_63( LL_EXTI_LINE_41 );
+	
+  /**
+   * In case the SBSFU is implemented, it may have already set the C2BOOT bit to startup the CPU2.
+   * In that case, to keep the mechanism transparent to the user application, it shall call the system command
+   * SHCI_C2_Reinit( ) before jumping to the application.
+   * When the CPU2 receives that command, it waits for its event input to be set to restart the CPU2 firmware.
+   * This is required because once C2BOOT has been set once, a clear/set on C2BOOT has no effect.
+   * When SHCI_C2_Reinit( ) is not called, generating an event to the CPU2 does not have any effect
+   * So, by default, the application shall both set the event flag and set the C2BOOT bit.
+   */
+  __SEV( );       /* Set the internal event flag and send an event to the CPU2 */
+  __WFE( );       /* Clear the internal event flag */
+  LL_PWR_EnableBootC2( );
+
+  return;
+}
+
+void HW_IPCC_Init( void )
+{
+  LL_AHB3_GRP1_EnableClock( LL_AHB3_GRP1_PERIPH_IPCC );
+
+  LL_C1_IPCC_EnableIT_RXO( IPCC );
+  LL_C1_IPCC_EnableIT_TXF( IPCC );
+
+  HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn);
+  HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn);
+
+  return;
+}
+
+/******************************************************************************
+ * BLE
+ ******************************************************************************/
+void HW_IPCC_BLE_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_BLE_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_BLE_CMD_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_BLE_EvtHandler( void )
+{
+  HW_IPCC_BLE_RxEvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_BLE_SendAclData( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_BLE_AclDataEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+
+  HW_IPCC_BLE_AclDataAckNot();
+
+  return;
+}
+
+__weak void HW_IPCC_BLE_AclDataAckNot( void ){};
+__weak void HW_IPCC_BLE_RxEvtNot( void ){};
+
+/******************************************************************************
+ * SYSTEM
+ ******************************************************************************/
+void HW_IPCC_SYS_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_SYS_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_SYS_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+
+  HW_IPCC_SYS_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_SYS_EvtHandler( void )
+{
+  HW_IPCC_SYS_EvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
+
+  return;
+}
+
+__weak void HW_IPCC_SYS_CmdEvtNot( void ){};
+__weak void HW_IPCC_SYS_EvtNot( void ){};
+
+/******************************************************************************
+ * MAC 802.15.4
+ ******************************************************************************/
+#ifdef MAC_802_15_4_WB
+void HW_IPCC_MAC_802_15_4_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_MAC_802_15_4_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_MAC_802_15_4_SendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_MAC_802_15_4_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+
+  HW_IPCC_MAC_802_15_4_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_MAC_802_15_4_NotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_MAC_802_15_4_EvtNot();
+
+  return;
+}
+__weak void HW_IPCC_MAC_802_15_4_CmdEvtNot( void ){};
+__weak void HW_IPCC_MAC_802_15_4_EvtNot( void ){};
+#endif
+
+/******************************************************************************
+ * THREAD
+ ******************************************************************************/
+#ifdef THREAD_WB
+void HW_IPCC_THREAD_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_OT_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_CLI_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_THREAD_SendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_THREAD_CliSendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_OT_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  HW_IPCC_OT_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_THREAD_NotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_THREAD_EvtNot();
+
+  return;
+}
+
+static void HW_IPCC_THREAD_CliNotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_THREAD_CliEvtNot();
+
+  return;
+}
+
+__weak void HW_IPCC_OT_CmdEvtNot( void ){};
+__weak void HW_IPCC_CLI_CmdEvtNot( void ){};
+__weak void HW_IPCC_THREAD_EvtNot( void ){};
+
+#endif /* THREAD_WB */
+
+/******************************************************************************
+ * ZIGBEE
+ ******************************************************************************/
+#ifdef ZIGBEE_WB
+void HW_IPCC_ZIGBEE_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendAppliCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendCliCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
+
+   return;
+}
+
+void HW_IPCC_ZIGBEE_SendAppliCmdAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendCliCmdAck( void )
+{
+    LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+    LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_CmdEvtHandler( void )
+{
+    LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+    HW_IPCC_ZIGBEE_AppliCmdNotification();
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_StackNotifEvtHandler( void )
+{
+    LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+    HW_IPCC_ZIGBEE_AppliAsyncEvtNotification();
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_CliNotifEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_ZIGBEE_CliEvtNotification();
+
+  return;
+}
+
+__weak void HW_IPCC_ZIGBEE_AppliCmdNotification( void ){};
+__weak void HW_IPCC_ZIGBEE_AppliAsyncEvtNotification( void ){};
+__weak void HW_IPCC_ZIGBEE_CliEvtNotification( void ){};
+#endif /* ZIGBEE_WB */
+
+/******************************************************************************
+ * MEMORY MANAGER
+ ******************************************************************************/
+void HW_IPCC_MM_SendFreeBuf( void (*cb)( void ) )
+{
+  if ( LL_C1_IPCC_IsActiveFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ) )
+  {
+    FreeBufCb = cb;
+    LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+  }
+  else
+  {
+    cb();
+
+    LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+  }
+
+  return;
+}
+
+static void HW_IPCC_MM_FreeBufHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+
+  FreeBufCb();
+
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+
+  return;
+}
+
+/******************************************************************************
+ * TRACES
+ ******************************************************************************/
+void HW_IPCC_TRACES_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_TRACES_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_TRACES_EvtHandler( void )
+{
+  HW_IPCC_TRACES_EvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_TRACES_CHANNEL );
+
+  return;
+}
+
+__weak void HW_IPCC_TRACES_EvtNot( void ){};
+
+/******************* (C) COPYRIGHT 2019 STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/readme.txt b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/readme.txt
new file mode 100644
index 000000000..79fc9a0e6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_TransparentMode/readme.txt
@@ -0,0 +1,89 @@
+/**
+  @page BLE_TransparentMode example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    BLE/BLE_TransparentMode/readme.txt 
+  * @author  MCD Application Team
+  * @brief   add here the very short description of the example (the name ?).
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                               www.st.com/SLA0044
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to communicate with the STM32CubeMonitor-RF Tool using the transparent mode.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Directory contents 
+  
+  - BLE/BLE_TransparentMode/Core/Inc/stm32wbxx_hal_conf.h		HAL configuration file
+  - BLE/BLE_TransparentMode/Core/Inc/stm32wbxx_it.h          	Interrupt handlers header file
+  - BLE/BLE_TransparentMode/Core/Inc/main.h                  	Header for main.c module
+  - BLE/BLE_TransparentMode/STM32_WPAN/App/tm.h               	Header for tm.c module
+  - BLE/BLE_TransparentMode/Core/Inc/app_common.h            	Header for all modules with common definition
+  - BLE/BLE_TransparentMode/Core/Inc/app_conf.h              	Parameters configuration file of the application
+  - BLE/BLE_TransparentMode/Core/Inc/app_entry.h              	Parameters configuration file of the application
+  - BLE/BLE_TransparentMode/STM32_WPAN/App/ble_conf.h          	BLE Services configuration
+  - BLE/BLE_TransparentMode/STM32_WPAN/App/ble_dbg_conf.h      	BLE Traces configuration of the BLE services
+  - BLE/BLE_TransparentMode/Core/Inc/hw_conf.h           		Configuration file of the HW
+  - BLE/BLE_TransparentMode/Core/Inc/utilities_conf.h    		Configuration file of the utilities
+  - BLE/BLE_TransparentMode/Core/Src/stm32wbxx_it.c          	Interrupt handlers
+  - BLE/BLE_TransparentMode/Core/Src/main.c                  	Main program
+  - BLE/BLE_TransparentMode/Core/Src/system_stm32wbxx.c      	stm32wbxx system source file
+  - BLE/BLE_TransparentMode/Core/Src/app_entry.c      			Initialization of the application
+  - BLE/BLE_TransparentMode/STM32_WPAN/Target/hw_ipcc.c      	IPCC Driver
+  - BLE/BLE_TransparentMode/Core/Src/stm32_lpm_if.c				Low Power Manager Interface
+  - BLE/BLE_TransparentMode/Core/Src/hw_timerserver.c 			Timer Server based on RTC
+  - BLE/BLE_TransparentMode/Core/Src/hw_uart.c 					UART Driver
+  - BLE/BLE_TransparentMode/STM32_WPAN/App/tm.c 				Transparent Mode implementation
+  
+     
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35xx devices.
+  
+  - This example has been tested with an STMicroelectronics STM32WB35CE-Nucleo
+    board and can be easily tailored to any other supported device 
+    and development board.
+
+@par How to use it ? 
+
+This application requests having the stm32wb3x_BLE_Stack_fw.bin binary flashed on the Wireless Coprocessor.
+If it is not the case, you need to use STM32CubeProgrammer to load the appropriate binary.
+All available binaries are located under /Projects/STM32_Copro_Wireless_Binaries directory.
+Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the detailed procedure to change the
+Wireless Coprocessor binary.  
+
+In order to make the program work, you must do the following:
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into Target memory
+ - OR use BLE_TransparentMode_reference.hex from Binary directory
+ - to test the BLE Transparent Mode application, use the STM32CubeMonitor RF tool
+ - make the connection between STM32CubeMonitor RF tool and BLE_TransparentMode application
+ - send some ACI commands from STM32CubeMonitor RF tool as HCI_RESET, HCI_LE_RECEIVER_TEST, HCI_LE_TRANSMITTER_TEST, ...
+ - the application must acknowledge the command with a "Command Complete" answer 
+ 
+For more details refer to the Application Note: 
+  AN5289 - Building a Wireless application 
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
+ 
\ No newline at end of file
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Binary/BLE_p2pClient.hex b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Binary/BLE_p2pClient.hex
new file mode 100644
index 000000000..cb726830e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Binary/BLE_p2pClient.hex
@@ -0,0 +1,2049 @@
+:020000040800F2
+:10000000D02700201D7E0008457C0008477C0008A2
+:10001000497C00084B7C00084D7C00080000000073
+:100020000000000000000000000000004F7C0008FD
+:10003000517C000800000000537C0008557C00083B
+:100040003F7E0008437E0008477E0008897C000848
+:100050004B7E00084F7E0008817C0008537E00081C
+:10006000577E00085B7E0008877C00085F7E0008E2
+:10007000637E0008677E0008597C00086B7E0008DC
+:100080006F7E0008737E0008777E00087B7E000884
+:100090007F7E0008837E0008877E00088B7E000834
+:1000A0008F7E0008937E0008977E00089B7E0008E4
+:1000B0009F7E0008A37E0008A77E0008AB7E000894
+:1000C000AF7E0008B37E0008B77E0008BB7E000844
+:1000D0005F7C0008657C000800000000BF7E00080F
+:1000E000C37E0008C77E0008CB7E0008CF7E0008D4
+:1000F000917C00088D7C0008D37E0008D77E000824
+:10010000DB7E000800000000DF7E0008E37E0008C0
+:10011000E77E0008EB7E0008EF7E0008F37E000813
+:10012000F77E0008FB7E00086B7C0008FF7E00085D
+:10013000037F0008077F00080B7F00082DE9F84FB8
+:100140000FF2D017A2B0D7E90045CDE900452C9EAB
+:10015000DFF82C7C04918DF8436000210FF2BC1471
+:100160000D9112944FF0FF368246904699460FE06B
+:10017000C3462C461BF8011B0498D0470028049066
+:1001800000F0B2800D98401C641E0D90F2D1A8447E
+:1001900098F80000252807D10021079108910991BE
+:1001A0000A910B910C910DE06A463146404600F0F1
+:1001B000FDFF050001D10D98B4E0D9D50125E6E792
+:1001C00041F0010118F8010F2028F9D023280CD0A4
+:1001D0002B2804D02D2805D0302809D086E041F006
+:1001E0000201EFE741F00401ECE741F00801E9E723
+:1001F00041F01001E6E700200F900AE00F98B842A6
+:1002000005DA00EB800302EB4302303A0F9208F16B
+:10021000010898F80020A2F130000A28EED398F8DF
+:1002200000002E2818BF0E9629D118F8010F2A2891
+:100230000BD1D9F80000C9F8000008F1010850F806
+:10024000042BC9F800000E9219E02D280CBF18F8F5
+:10025000010B002000220E920BE040B90E9ABA4228
+:1002600005DA02EB820403EB4403303B0E9308F102
+:10027000010898F80030A3F130020A2AEDD3ADF856
+:100280004010129898F8001000F09CFF08B118F880
+:10029000010B8DF842009DF84200682804BF98F8D1
+:1002A0000010682903D162208DF8420008E06C2814
+:1002B00004BF98F800006C2804D171218DF8421019
+:1002C00008F1010813A806904A4618F8013B02A954
+:1002D000504600F067F838B913AA02A9504600F05A
+:1002E000C9F900287FF554AF30461BE02A2882D197
+:1002F000D9F80020C9F8002052F8040BC9F80020F2
+:1003000000280F9003D540420F9041F0040108F1FE
+:10031000010884E70000000000000000686A6C74B7
+:100320007A4C000023B0BDE8F08F622820D0682806
+:1003300011D06A2803D06C2827D0712825D10868ED
+:10034000C01D20F007000860D0E9002308300860D5
+:10035000194610467047002A0A680A60106803D0E0
+:10036000121D0A6000B217E0121D0A6080B217E089
+:10037000002A0A680A60106803D0121D0A6040B2A1
+:100380000AE0121D0A60C0B20AE0002A0A680A6088
+:10039000106803D0121D0A60C1177047121D0A6051
+:1003A000002170477CB50D4611461C462E69B4F1FC
+:1003B000250200F04D811C3A00F08680121F022AAF
+:1003C00040F282800E3A00F00781521F5AD0093A5B
+:1003D0007AD0921E16D0521E35D0521E022A73D9E0
+:1003E000121F30D0521F00F09A80521E4AD0521E67
+:1003F00000F0E480D21E00F0FD80921E42D0D21E9A
+:1004000040D02BE195F83A206C2A09D06869421C4B
+:100410006A610A680A6052F8043B0A60335427E1B3
+:100420000A680A6052F8043B0A60002100930191B7
+:100430004FF0FF322A6329466A4600F096F90028F9
+:1004400040F1168101E195F83A000122FFF76DFFB6
+:10045000C5E900010023994204DA6869411C696119
+:100460002D210DE0288F810704D56869411C696141
+:100470002B2105E0C00722D56869411C6961202154
+:1004800031541CE095F83A000022FFF74EFFC5E911
+:10049000000195F83800010711D5D5E900230020A7
+:1004A000834208BF82420AD044F02000782806D157
+:1004B000686930213154401C411C69613454214623
+:1004C00068693044E86083E00868C01D20F00700D8
+:1004D0000860D0E9002308300860C5E90023D5E9A9
+:1004E0000001C80F04D06869411C69612D210DE02D
+:1004F000288F810704D56869411C69612B2105E0BB
+:10050000C00704D56869411C6961202131546869BC
+:100510003044E8602146284600F032FAA8E005F1B0
+:100520003A02507820B14FF0FF340FF6243070E0DB
+:100530001078622808D0682824D06A2812D06C2845
+:100540002ED071280ED02BE00A680A6052F8040BF6
+:100550000A6020B94FF0FF340FF60C3059E0E96A19
+:10056000017085E00A680A6052F8040B0A6020B93D
+:100570004FF0FF340FF6F0204BE0EA6AD317C0E9E2
+:10058000002375E00A680A6052F8040B0A6020B97B
+:100590004FF0FF340FF6D0203BE0E96A018067E0BE
+:1005A0000A680A6052F8040B0A6020B94FF0FF3461
+:1005B0000FF6B4202DE0E96A016059E00A680A608C
+:1005C00052F8040B0A600021C5E90001EE607821B1
+:1005D000284600F029F94BE06C2285F83A200B6898
+:1005E0000B6053F8042B0B6052BB4FF0FF340FF637
+:1005F000AC200EE095F83A206C2AF0D0086808602C
+:1006000050F8044B0860EC603CB94FF0FF340FF633
+:10061000702000F0F1FD201A76BD2E6B002E04D55F
+:10062000204600F00BFE044608E03246002120463A
+:1006300000F020FE002814BF041B3446AC6117E014
+:10064000294600F092F8002812D54FF0FF3076BD11
+:100650006869411C69612521315409E06969481CB8
+:10066000686125227254210002D0411C6961345412
+:10067000002076BD2DE9F0410E460546716B70698C
+:10068000B46A091A306A091AB069091A706A091A33
+:10069000F069091A96F838000C1B410790460DD4F2
+:1006A000002C0BDD2746B0682021A8470028B06049
+:1006B00057D0F06A401C7F1EF062F4D17369424645
+:1006C0003146284600F0ACFC00284AD1376A002F9A
+:1006D0000ADDB0683021A8470028B06041D0F06A38
+:1006E000401C7F1EF062F4D1B369F268314628469F
+:1006F00000F096FCA8BB776A002F09DDB0683021B6
+:10070000A847B06068B3F06A401C7F1EF062F5D164
+:10071000F068B169F36942183146284600F080FC60
+:10072000F8B9B76A002F09DDB0683021A847B0607A
+:10073000B8B1F06A401C7F1EF062F5D196F838001F
+:1007400041070BD5002C09DDB0682021A847B06017
+:1007500038B1F06A401C641EF062F5D10020BDE89B
+:10076000F0814FF0FF30BDE8F0812DE9F8470D46EC
+:10077000A3B02F6B002F8146904648BF6FF0004713
+:1007800000F0A4FD696B40180FF62C118128D1E907
+:100790000023CDE9012328BF4FF0FF303ED20024D3
+:1007A000002F2FDDD8F8001001AA684600F000FDE8
+:1007B0000646002E35D4D8F8000008B9761E30D48D
+:1007C000B7421FDB6869301881280AD300206863AC
+:1007D00003AA29464846FFF74DFF040012D4002023
+:1007E000686103A8D5F814A032466946504400F069
+:1007F00073FDB244C5F814A058F8040B002818BFC4
+:10080000BF1BCDD12CB903AA29464846FFF732FFBA
+:10081000044614B9002068616863204624B0BDE82E
+:10082000F0874FF0FF34F8E72DE9FC4707468A468A
+:100830003E69BAF16F0F08BF082405D04AF02001C5
+:10084000782914BF0A2410243C25D7E90023BAF1E3
+:10085000640F18BFBAF1690F9046994606D100217E
+:100860008B4203DAD8F1000869EB49090020814581
+:1008700008BF80451FD1386BE8B9082C4CD197F8D8
+:100880003800010748D530203B2586F83B0043E07F
+:1008900000280ED597F8380000F01400102808D171
+:1008A0007A6B7869121A386A121A511A0029C8BF6D
+:1008B0003962BDE8F3878DF800A0404649462246DC
+:1008C000E31700F05DFD3032D0B26D1E3A2801957D
+:1008D00004DB9DF80000A0F151018A1872554046D2
+:1008E00049462246E31700F04BFD8046894600202A
+:1008F000814508BF804503D0F86871198842DCD370
+:10090000082C09D197F83800010705D5715D302909
+:1009100002D06D1E30207055C5F13C01B9617019CF
+:10092000F860386B8142B3DA411A39624FF6EF70E2
+:10093000398F01403987BDE8F3872DE9D04306465A
+:100940000F4614464FF00008DFF8389412E0E00735
+:1009500007D542464B463046394600F029FE06464A
+:100960000F464046494642464B4600F021FE641081
+:1009700080468946002CEAD130463946BDE8D0830E
+:100980002DE9F34F054641F020048DB0D5E90089EB
+:10099000612C02AE09D0286B002848BF062003D482
+:1009A00008BF672C01D101202863D5E90023580036
+:1009B0004015401C0ED119030CD00320A8619DF8EE
+:1009C000380061381A2802D20FF2F46111E00FF2F8
+:1009D000F4610EE058004015401C0FD119030DD1F1
+:1009E0000320A8619DF8380061381A2814D30FF24B
+:1009F000DC61E868032200F06FFCD3E1194621F0C6
+:100A00000043B3F5801F10460DD20027BB4208BF3C
+:100A1000BA42019703D111E00FF2AC61E9E701AAF4
+:100A200000F098FE0AE0DFF8607307EB1352DFF87E
+:100A30005C3301921940DFF858331943C5E90001CE
+:100A4000612C0ED1E86830210170811CE9609DF8AD
+:100A5000381061290CBF7821582141706869801CC9
+:100A60006861D5E900AB2BF0004300202AF00002BA
+:100A7000834204BF8242002300F05A81612C40F07F
+:100A8000A980286B00284CBF2120401C00904046C4
+:100A9000009F7F1C49460022002300F093FED946A8
+:100AA00001988DF8082038BF89F00049001F019097
+:100AB000002FD0460DF1090040F3498140F2FF714B
+:100AC000DFF8D0B20C91064640464946002200238A
+:100AD00000F090FE80F03A814800400D00F11C02C9
+:100AE00010D0002A0EDD0C98824205DB09F0004090
+:100AF00040EA0B01002013E0A448084040EA0251FC
+:100B000040460DE029F00043002028F00002834217
+:100B100008BF82420FBF40461C22404600F082FEC2
+:100B20008046894600F01CFFFF1F002F044609DDA8
+:100B300000F034FF02460B464046494600F040FFB5
+:100B400080468946F01D072104E004F00F0200F8FA
+:100B5000012D2411002C01DD491EF6D5491E5CBF74
+:100B6000002200F8012DF9D5ECE00020194602AA78
+:100B70000A4400E05B1E12F80149491E8442F9D084
+:100B80000F2804D10DF10900425C521C4254002987
+:100B900004D50198001D02AE5B1C0190591E12D4B1
+:100BA0009DF838007218147804F130085FFA88F460
+:100BB000392CC4BFA0F13A04A044491E02F80189AF
+:100BC000F1D58DF83800286B002840F1B080591E0F
+:100BD0002963ACE0404649460022002300F0F2FDC4
+:100BE000019938BF89F0004947F2975041436A4A5A
+:100BF00091FBF2F20192D2F1070204DD4046494630
+:100C0000FFF79BFE0AE0524200206449FFF795FE81
+:100C100002460B464046494600F044FF8046662C9B
+:100C2000286BDFF87CB106BF019F0A3706273F1803
+:100C3000142FC8BF142730208DF8080089460DF105
+:100C4000090000E03046002F34DD064640464946A4
+:100C500001F04CF801460A4606F1080304200A2672
+:100C6000B2FBF6F606EB860EA2EB4E02303203F82C
+:100C7000012C0A22B6FBF2F202EB820EA6EB4E0624
+:100C80003036401E03F8026DE9D1083F002F03F112
+:100C90000806D7DD084601F03DF802460B464046FF
+:100CA000494600F08DFE00225B4600F081FC804644
+:100CB0008946CBE70DF10901401A0DF1090604E060
+:100CC0000199491E401E0191761C31783029F7D0D8
+:100CD000662C02D10199491C03E0652C0CBF01214F
+:100CE00000212B6BCB189842B8BF431E002B1ED49B
+:100CF000834204DAF05C3528A8BF392000DA3020BE
+:100D00001946721E02EB010800E05B1E18F80199FB
+:100D1000491E8145F9D0392802D1705C401C7054BD
+:100D2000002904D50198401C16465B1C01900198CF
+:100D300000B200901BB29DF838103246284600F0F1
+:100D400034F82FE0C61D002F3FF7BEAE30460DF140
+:100D50000901401A009903468842C8BF0B46002B80
+:100D60000DF109063FF52FAF8342BFF6FEAE0DF140
+:100D70000900C05C07287FF7F8AE0F20F6E60000F8
+:100D8000CBCCCC0C0000244002FCFFFFFFFF0F8007
+:100D90000000E03F0000F07FA08601000000F03F6F
+:100DA00084D797410FB0BDE8F08F2DE9F84783B0A5
+:100DB00006468A461746984600F0FCF9B8F1000F3F
+:100DC000406A356B90F8009003DC4FF001080FF299
+:100DD0000037BDF930404AF02000662808BF641C87
+:100DE00015D0672840F0848014F1040FC0F286808B
+:100DF000AC4280F2838096F83800641C010702D46C
+:100E0000A845B8BF454620B22D1A48BF00250FFAA5
+:100E100084FAF068B169BAF1000F25DC4A1C30236E
+:100E20004354002D03DC96F83800010703D5F06821
+:100E300000F80290521C15EB0A0FB8BF6C4220B2AA
+:100E4000441941424445B8BFA046B26171620FFAED
+:100E500088F5F561F068B3692A463946184400F010
+:100E60003BFA641BB462C4E022B29045084417DA2E
+:100E70004246394600F030FAB0694044B061AAEB0E
+:100E80000801002D716203DC96F838100A0705D5B9
+:100E9000F16801F80090F069401CF061B562A8E0CB
+:100EA000394600F019FAB069002D5044A8EB040847
+:100EB00003DC96F838100A0703D5F16801F80090B2
+:100EC000401CB0610FFA88F08542F068B369B8BF82
+:100ED000A8460FFA88F207EB0A01184400F0FCF963
+:100EE000B0690FFA88F10844B061681A706280E056
+:100EF000BAF1610F14D14FF0700A16E0A84504DA78
+:100F000096F838100A0758BF45466D1E48BF0025A1
+:100F1000BAF1670F14BF4FF0450A4FF0650A04E0BD
+:100F2000BAF1410F08BF4FF0500AB169F368481C8D
+:100F3000B061002D17F8012B5A5403DC96F83810D5
+:100F40000A071BD5F168431CB36101F80090002D1E
+:100F500014DDA8F101080FFA88F08542F068B8BFE7
+:100F6000A8460FFA88F23946184400F0B5F9B0697E
+:100F70000FFA88F108446D1AB0617562F068B169C2
+:100F80000844002C80F800A003D42B214170811C60
+:100F900003E02D2141706442811C00206A460AE072
+:100FA00023460A2493FBF4F404EB8405A3EB4503E6
+:100FB00002F8013B401C24B2002CF1DC012806DCC5
+:100FC0004AF02002652A04BF302201F8012B48B9FB
+:100FD000302001F8010B07E0401E1DF800203032E0
+:100FE00001F8012B0028F7DCF068B2691044091AF7
+:100FF000F16196F8380000F0140010280DD17169E5
+:10100000B0694118706A4118F0694118B06A411816
+:10101000706B8142BCBF411A316204B0BDE8F087F9
+:10102000F8B505460E4617461C46002074B117F861
+:10103000011BB068A847B06030B1F06A401CF06294
+:101040000020641EF3D1F2BD4FF0FF30F2BD00006E
+:101050007072696E74665F733A20256E20646973DE
+:10106000616C6C6F776564007072696E74663A20AB
+:1010700062616420256E20617267756D656E740013
+:101080007072696E74665F733A20626164202573C2
+:1010900020617267756D656E740000007072696E14
+:1010A00074665F733A2062616420256C73206172FC
+:1010B00067756D656E7400000000000000000000A0
+:1010C0006E616E004E414E00696E6600494E4600EC
+:1010D0003000F0B40246106895681318506803EBAE
+:1010E0005004C00721D54D441FE0F0BC02F10C00B4
+:1010F000704713F8017B05F8017B491EF9D1A0B1B7
+:10110000B60813F8011B06F00306032E08BF13F8F8
+:10111000016B01EB06214942801C294405D011F8DE
+:10112000016B05F8016B401EF9D1A342DDD013F825
+:10113000016B16F0030104BF13F8011BC91C300931
+:101140000F28DAD113F8010B0F30D6E71B48704790
+:1011500030B45368D418042B09DA41B1057804F887
+:10116000015B10F8015B15B15B1C491EF3E753608E
+:1011700030BC704738B514461D4661B1FFF7E8FF33
+:1011800061686A6B204690476FF00102811A02D0B5
+:10119000491E03D005E06FF0010032BD4FF0FF3073
+:1011A00032BD0021616032BDDA6B1047034BE1E7CD
+:1011B000024BF9E70248704700000000B010002021
+:1011C000781000200278C9B28A421AB11CBF10F808
+:1011D000012FF9E718BF00207047B1F5807F02D3D7
+:1011E0004FF0FF3070470170012070470078401EBB
+:1011F0008041C043C00F704780B508B90FF21C0092
+:1012000005490B681BB122220021984701E000F03C
+:101210008EFD222002BD0000C4170020636F6E7394
+:10122000747261696E742068616E646C65723A20D4
+:10123000626164206D6573736167650000F101038D
+:10124000810704D010F8011B89B18107FAD1026827
+:10125000B2F10131914311F0803F04BF50F8042FE7
+:10126000F6E710F8011B11B110F8011BFBE7C01ADB
+:1012700070470000C9B2830706D0521E22D310F86F
+:10128000013B9942F7D11FE0083A13D302F104025F
+:1012900041EA012141EA014150F8043B121F21BFFC
+:1012A0004B40A3F1013C2CEA030C1CF0803FF3D02F
+:1012B000C9B2001F083210F8013B521E28BF91EA44
+:1012C000030FF8D818BF0120401E704780B5FFF704
+:1012D0003DFF006C02BD000062B38B0708D0521EB8
+:1012E00011F8013B00F8013B00F024808B07F6D198
+:1012F000830740F0208000BF103A07D330B4B1E834
+:101300003810103AA0E83810F9D230BC530724BF87
+:10131000B1E80810A0E8081044BF51F8043B40F8B9
+:10132000043BD20724BF31F8022B20F8022B44BF24
+:101330000B7803707047121F17D35B0009D151F867
+:10134000043B20F8023B1B0C121F20F8023BF6D294
+:101350000BE051F8043B00F8013B1B0A20F8023B6C
+:101360001B0C121F00F8013BF3D238BF121D521E96
+:1013700024BF11F8013B00F8013BF8D8704700008A
+:10138000B3BBD9B1B2F5803F7DD2022A1ED98C46BB
+:10139000B1FBF2F102FB11C31B0443EA1043B3FBA0
+:1013A000F2FC02FB1C3380B240EA0343B3FBF2F0D1
+:1013B00002FB103240EA0C4000237047022A05D994
+:1013C0008446B0FBF2F002FB10C270474AB105D16F
+:1013D00000F0010249085FEA300070470022002354
+:1013E000704700F0A7BC0B000200002100207047EE
+:1013F000904271EB030CF6D3B3F5803F2FD2F0B5DA
+:10140000B3FA83F7B1FA81F4A7F10F0E3D1B5340F5
+:10141000CEF1200602FA0EF2F3415340B5F10F0768
+:1014200046D80F3C2C444140C4F12006A040F14175
+:101430004140B1FBF3F603FB1611A2FB0645001B6E
+:10144000A94102D2761E8018594180EA010221FA90
+:101450000EF362FA0EF200215A403046F0BD30B46D
+:10146000B1FBF3FC03FB1C11A2FB0C45001BA941C3
+:1014700003D2ACF1010C8018594130BC02460B4636
+:10148000604600217047B2F1807F65D3F0B5B2FAB3
+:1014900082F7B1FA81F4C7F10F063D1B22FA06F379
+:1014A00007F1110EF24120355A40B5F10F07B8D9B6
+:1014B0004140C4F12006A040F1414140B1FBF3FCA2
+:1014C00003FB1C11A2FB0C45001BA94103D2BCF17C
+:1014D000010C801859410F2F12D30F3FC90341EA65
+:1014E0005041B1FBF3F603FB1611A2FB0645D4EB0A
+:1014F000C030A94102D2761E8018594146EACC3C40
+:1015000007B34140C7F12006B840F1414140B1FB6B
+:10151000F3F603FB1611A2FB0645001BA94102D2FC
+:10152000761E8018594180EA010221FA0EF3C7F1B4
+:10153000200462FA0EF20CFA07F05A402CFA04F179
+:101540003043F0BD80EA010221FA0EF3002162FA75
+:101550000EF260465A40F0BD8C46B1FBF2F102FB40
+:1015600011C31B0243EA1063B3FBF2FC02FB1C3302
+:101570001B024CEA002043EA1063B3FBF2FC02FBBF
+:101580001C331B024CEA002043EA1063B3FBF2FC5D
+:1015900002FB1C331B024CEA002043EA1063B3FB3E
+:1015A000F2FC02FB1C324CEA0020002370470000D2
+:1015B000B0B581EA030C0CF0004C40F2FF7515EA5F
+:1015C00011541DBF15EA1357AC42AF4239E0E4197C
+:1015D00023EA455343F48013C90241F0004141EA34
+:1015E000505EC7021100A7FB020200284FF0000066
+:1015F000EEFB01204FF00001E3FB072118BF42F092
+:101600000102401800214941E3FB0E01A4F580646A
+:101610000F0302D252004041494154F101046CDDF4
+:10162000470872F1004250F1000051EB0451A1F55E
+:1016300080115CBF41EA0C01B0BD4CEA05510020AD
+:10164000B0BD05EA1357AC4214BFAF4241E050EAC7
+:10165000410E1CBF52EA430E02E061460020B0BDBD
+:1016600024423C441BD15FEA070EF6D0090302BFB7
+:1016700001460020AEF1140EB1FA81F7AEEB07047B
+:1016800001FA07FE0C37C7F1200100FA07F7C8403E
+:101690004EEA000E23EA455343F48013A2E733F0E9
+:1016A0000043B3FA83F704BFB2FA82FE77440B3FDC
+:1016B000E41BB7F1200E2FBF02FA0EF3BB40C7F1B7
+:1016C000200E22FA0EFE38BF43EA0E03BA40641C15
+:1016D00082E750EA410E14BF52EA430E6FF0000158
+:1016E0004FF4001717EB430F8ABF194617EB410F52
+:1016F000B5E74CEA05510020B0BDD4F10104B4F1C6
+:1017000020070FDAC4F12007520828BF42F0010277
+:1017100010FA07F501FA07F7E1BF2A43E040384322
+:10172000E1400FE0352C98DCC7F1200452EA40027A
+:1017300020FA07F218BF42F0010231FA07F0A14087
+:101740000A43002172F1004250F1000051EB0C01FC
+:10175000B0BD000010B5144600F002F8226010BDC4
+:10176000C1F30A5343B14A0012F5001F28D2A3F275
+:10177000FE32A1EB0251704750EA410C20D001F03B
+:10178000004C31EA0C01B1FA81F204BFB0FA80F3E7
+:10179000D2180B3AB2F120032CBF00FA03F19140AA
+:1017A00041EA0C013EBFC2F1200C20FA0CF31943B0
+:1017B0009040524240F2FD33D21A01EB0351704780
+:1017C000002270474FF4001C1CEB410F94BF1CEB30
+:1017D000430F09E041EA030C50EA4C0C52EA0C0CAE
+:1017E00003D2994208BF9042704714BF8B42824295
+:1017F000704700004FF4001C1CEB410F94BF1CEB22
+:10180000430F09E041EA030C50EA4C0C52EA0C0C7D
+:1018100003D28B4208BF8242704714BF9942904264
+:1018200070470000124254D440F2FF7C1CEA11536E
+:101830000FD0634531D09B1863453CBF01EB02518B
+:10184000704701F0004141EA0C510020AFF30080E5
+:10185000704750EA410320D001F0004C91EA0C019E
+:101860001CD0B1FA81F30B3B9A420DD9D21A9940A0
+:1018700051EA0C01C3F1200C20FA0CFC61449840A1
+:10188000531C40F2FF7CD7E7914041EA0C01C2F1C2
+:10189000200C20FA0CF3194390407047B0FA80F303
+:1018A0001533202BE0D3202AEED3203A203B9A4256
+:1018B00009D9D21A00FA03F141EA0C010020531CA5
+:1018C00040F2FF7CB8E700FA02F141EA0C01002087
+:1018D0007047524240F2FF7C1CEA11530DD0634521
+:1018E000DBD0B2EB030C3CBFA1EB025170470CF113
+:1018F000010221EA035141F4801150EA410CCCD09D
+:1019000001F0004C352A27DC30B481EA0C01B2F139
+:10191000200309DAC2F12003044601FA03F5D0409E
+:101920002843D1409C400CE0C3F12002450020FA3E
+:1019300003F418BF44F0010421FA03F091400C4372
+:10194000002174F1004550F1000051EB0C012442DC
+:1019500030BC7FF47BAF70476146002076E7000023
+:10196000C1F30A5340F2FE329B1A14DDD3F1200377
+:101970004FEAE17208DDC90241EA505141F00040EE
+:10198000D84080185040704703F2E13010B1D24384
+:1019900082F000407047002070470000C11768B116
+:1019A0004840401AB0FA80F29040D21CC907C2F5F4
+:1019B000846241EA025202EBD021400570470000E8
+:1019C00070B44FF0004591EA030F40F1B5816B40D0
+:1019D000841A71EB030603D2001BB1411219734143
+:1019E0004FF4001C1CEB410F34BF7CEB430442E07E
+:1019F0000C0DA4EB1356352E4FDC45EAC323DB0A4E
+:101A000045EAC121C912B6F120050DDD63FA05F6DC
+:101A1000EB4086EA0305124218BF45F00105C018E5
+:101A200051F100010CD213E062FA06F5F240554084
+:101A3000F3415A40B340F3405A408018594107D30C
+:101A400049085FEA30005FEA350528BF45F0010527
+:101A500001F58011420875F1004250F1000041EBA0
+:101A600004514E0016F5001F70BC38BF70470020AF
+:101A7000090D090570471CEB410F10D252EA4306CD
+:101A80000BD0BCEB410F05D80C0DAB43661E342EBA
+:101A9000B6DD02E0AB438018594170BC704770BCA2
+:101AA00070470000F0B540F2FF7581EA030C0CF0BE
+:101AB000004C15EA11541DBF15EA1357AC42AF4252
+:101AC000E5E0BC41C1F31301C3F31303801A99414C
+:101AD00043F4801304D2641E4000494180185941E8
+:101AE000C90241EA5051B1FBF3F603FB1611A2FB08
+:101AF0000675D7EBC020A94102D2761E8018594145
+:101B0000C90241EA5051B1FBF3FE03FB1E11A2FBD7
+:101B10000E75D7EBC020A94103D2AEF1010E80189B
+:101B20005941890241EA9051760546EA8E2EB1FB71
+:101B3000F3F603FB1611A2FB0675D7EB8020A94133
+:101B400002D2761E80185941C90241EA50514EEA2C
+:101B5000060EB1FBF3F603FB1611A2FB0675D7EBDD
+:101B6000C020A94102D2761E80185941C90241EA1B
+:101B70005051B1FBF3F703FB1711A2FB0735D3EB71
+:101B8000C020A94167F100070CBF004247F00107E0
+:101B900066F3D5274FEA1E31B80814F5806412DDCC
+:101BA000BD0775F1004250EB0E5051EB045111F599
+:101BB000801F5CBF41EA0C01F0BD4CF07F6141F039
+:101BC000E0410020F0BDBD076D0840EA0E5041F431
+:101BD0008011D4F10104B4F120060ADAC4F1200620
+:101BE0000200E04001FA06F3E1401843B240154319
+:101BF0000EE0342C13DCC6F1200445EA40056D08E4
+:101C000020FA06F2154321FA06F0A1400D43002107
+:101C100075F1004250F1000051EB0C01F0BD0020C5
+:101C20005FEA0C01F0BDCFB992185B41B3FA83F7BC
+:101C300004BFB2FA82F6BF190B3FB7F120062FBFDF
+:101C400002FA06F3BB40C7F1200622FA06F638BFB7
+:101C50003343BA401CB1E419641E33E77F4231F0CC
+:101C60000041B1FA81F404BFB0FA80F6A4190B3C2C
+:101C7000B4F120062FBF00FA06F1A140C4F12006FE
+:101C800020FA06F638BF3143A0403C1B1AE7AC42AD
+:101C90001ABF05EA1357AF4212E050EA41061CBFD3
+:101CA00052EA4306BFE750EA4107304661461CBF8F
+:101CB00041EA0551F0BD52EA430C08BFC143F0BDF3
+:101CC00000204FF4001616EB410F98BF16EB430FA0
+:101CD00008BF16EB410F24BFC14305E016EB430FCD
+:101CE0000CBF61464CEA0551F0BD0000400D49189B
+:101CF00040EA81200CD2490DA1F58061491C40F0D9
+:101D0000004005DBD1F11F0154BFC840C017704728
+:101D100000207047014648B1B0FA80F18840C91CE4
+:101D2000C1F58461090501EBD02140057047012010
+:101D300000F0B6B870470000841A71EB030604D2B5
+:101D40006E40001BB141121973414FF4001C1CEB93
+:101D5000410F34BF7CEB430682E00C0DA4EB13561D
+:101D6000362E7BDC012E45EAC32341DC43EA525385
+:101D700012BFD20292025B08240545EAC12141EA62
+:101D80005051D2EBC020994125D407D1B0FA80F64A
+:101D900010FA06F162D00020203608E0B1FA81F690
+:101DA000B140C6F1200220FA02F21143B0404FEADE
+:101DB000F474B4EB465434F001064FEA74040AD8C4
+:101DC000D6F50016760D04F00044F04061FA06F2F4
+:101DD0005040F1404840C00A40EA415021F00041E3
+:101DE00028BF5FEA500550F1000044EBD12135E0F7
+:101DF000DB0A45EAC121C90AB6F120050EDD42EA37
+:101E00000242120CC5F1200603FA06F6EB4042EA44
+:101E100006056D42984161F100010DE062FA06F598
+:101E2000F240554063FA06FC82EA0C02F3405A4045
+:101E30006D42904161EB030111F4801F05D1641ED6
+:101E4000620502D06D004041494121F480114308F0
+:101E500075F1004350F1000041EB045170BC704734
+:101E60001CEB410F15D223F0004352EA43060BD07E
+:101E70004FEA4C0CBCEB410F04D80C0D661E342EFF
+:101E8000B7DDEBE7801A994150EA410608BF00210F
+:101E9000E4E708BF1CEB430F28BF6FF00001DDE74C
+:101EA00080B5AFF30080024A11001820ABBEFBE7FB
+:101EB0002600020038B5040009D004F17C056868EA
+:101EC00008B900F01EF800F021F8012801D1012026
+:101ED00032BDA06A08B100F02AF800F00AF821F03B
+:101EE0002A01FFE7816000F01BF8BDE8324000F0F6
+:101EF0002EBE2068416821F49041416020688168CD
+:101F0000704700212970204600F049BF24206860F6
+:101F100020680168490849000160204600F040B986
+:101F20002068016841F001010160204670472046A9
+:101F300000F0AABD70B5044604F17C05134668683C
+:101F4000202836D149B3180027D02878012830D06E
+:101F500001222A7004F15406216533807380002029
+:101F6000E86021206860306AC8B1DFF82012C162E1
+:101F7000DFF81C02316A0863316ADFF8180248632F
+:101F80000020316A88632068216D00F12802306AE0
+:101F900001F043F818B100F00EF8012070BD21687F
+:101FA00040200862002028702068816841F080018C
+:101FB00008E0022070BD1020E8600020287020207A
+:101FC000686070478160002070BD206881684A06A3
+:101FD0007047F8B5044640F60F002568E9692A689D
+:101FE000AB6808400DD1880602D5900602D4D8000F
+:101FF00040F18980E16E00294FD02046BDE8F440D1
+:1020000008476548034204BF644E32427BD0CF0785
+:1020100009D5D60507D501262E62D4F8885045F09B
+:102020000105C4F888508D070AD5DD0708D5266854
+:1020300002253562D4F8885045F00405C4F888506C
+:102040004D070AD5DD0708D5266804253562D4F882
+:10205000885045F00205C4F888500D070CD5950648
+:1020600001D4034208D0256808202862D4F88800EB
+:1020700040F00800C4F8880008050BD5500109D5C8
+:1020800025684FF400602862D4F8880040F02000F2
+:10209000C4F88800D4F88800002870D0890607D5D5
+:1020A000900601D4D80003D5E16E09B120468847D7
+:1020B000D4F8880021688A68510602D410F0280FED
+:1020C0001AD0204600F0BEFDFFF77FFF0FD500F0CD
+:1020D00057F860B1DFF890198163A06F00F0E0FF5E
+:1020E00000284CD0A06F816BBDE8F4400847204623
+:1020F000BDE8F24001F0C4B8204601F0C1F800206C
+:10210000C4F88800F1BDC80209D5580207D54FF4BC
+:10211000801028622046BDE8F24001F039B9080677
+:1021200009D5100601D4180205D5216F39B3204610
+:10213000BDE8F440084748060FD550060DD528687D
+:1021400020F0400028602021C4F880100020206783
+:102150002046BDE8F24001F034B9080206D550002F
+:1021600004D52046BDE8F24001F03CB9C80148BFA3
+:10217000002A04D52046BDE8F24001F034B9F1BD93
+:10218000816821F040018160A06F7047992C0008A0
+:10219000C72C0008CD2C000801000010200100040D
+:1021A0002DE9F84F0446DFF8C8082768DFF8C4B8FF
+:1021B0003968DFF8C4A80140A068014320690143E1
+:1021C00060690143E0690143606E014339600026A4
+:1021D0007968E06821F4405101437960B046A16913
+:1021E000DFF8880887421CBF206A0143BA68DFF81D
+:1021F000780A02401143B9604FF48075F96A606A49
+:10220000090940EA0111F9625F454FF400404FF4BB
+:1022100000714FF480624FF400634FF4805C4FF420
+:10222000005E4FF4804929D1DAF800B00BF0030BBF
+:10223000BBF1030F3ED8DFE80BF00237343A4FF022
+:10224000010AD4F81CB05746BBF5004F4FF6F07AA0
+:1022500040F01183012F09D0022F00F05482042F87
+:1022600000F08D82082F00F0C282F5E201F0A6FC9A
+:102270000146606A002840F01B8242E2DFF8ECB7BA
+:102280005F4517D1DAF800A01AF4406A27D0BAF5F2
+:10229000806F09D0BAF5006F03D0BAF5406F06D051
+:1022A00008E04FF0020A07E04FF0040A04E04FF0A4
+:1022B000080A01E04FF0100ADFF8B0B75F45C0D15F
+:1022C000BAF1000F0BD0BAF1020F49D0BAF1040FE6
+:1022D00000F08280BAF1080F00F0B080B6E301F0A0
+:1022E00065FC0146606A58B3012808BF022028D067
+:1022F000022808BF042024D0032808BF062020D0CD
+:10230000042808BF08201CD0052808BF0A2018D0C0
+:10231000062808BF0C2014D0072808BF102010D0B2
+:10232000082808BF20200CD0092808BF402008D06A
+:102330000A2808BF802004D00B2808BF284600D0F8
+:102340000120B1FBF0F0002800F08283626802EB0C
+:102350004201884203D31103814280F0A18075E3DA
+:10236000606AB0B3012808BFDFF80009EED0022888
+:1023700008BFDFF8FC08E9D0032808BFDFF8F4083D
+:10238000E4D0042808BFDFF8F008DFD0052808BF34
+:10239000DFF8E808DAD0062808BFDFF8E408D5D06F
+:1023A000072808BFDFF8DC08D0D0082808BFDFF80E
+:1023B000D808CBD0092808BFDFF8D008C6D00A2833
+:1023C00008BFDFF8CC08C1D00B2808BF4FF224406B
+:1023D000BCD0DFF8C008B9E701F09EFB0146606A97
+:1023E00058B3012808BF0220ABD0022808BF042040
+:1023F000A7D0032808BF0620A3D0042808BF0820C0
+:102400009FD0052808BF0A209BD0062808BF0C20B3
+:1024100097D0072808BF102093D0082808BF202095
+:102420008FD0092808BF40208BD00A2808BF802001
+:1024300087D00B2808BF284683D081E7676A002F22
+:1024400084D0012F08BF4846FAD0022F08BF70463B
+:10245000F6D0032F08BF41F25550F1D0042F08BF2A
+:102460006046EDD0052F08BF40F6CC40E8D0062FDF
+:1024700008BF40F6AA2012D0072F08BF18460ED07A
+:10248000082F08BF10460AD0092F08BF084606D0FB
+:102490000A2F08BF284602D00B2F00D1802055E715
+:1024A000BAF1000F0BD0BAF1020F38D0BAF1040F15
+:1024B00000F07280BAF1080F00F0A780ECE001F0A4
+:1024C00075FB0146606A40B3012808BF02251ED093
+:1024D000022808BF04251AD0032808BF062516D0F5
+:1024E000042808BF082512D0052808BF0A250ED0E9
+:1024F000062808BF0C250AD0072808BF102506D0DB
+:10250000082808BF202502D0092808BF402572D01E
+:102510000A280CBF80250B286DD001256BE0606A6E
+:10252000002836D0012808BFDFF800682BD0022829
+:1025300008BFDFF8FC6726D0032808BFDFF8F46780
+:1025400021D0042808BFDFF8F0671CD0052808BF99
+:10255000DFF8E86717D0062808BFDFF8E46712D075
+:10256000072808BFDFF8DC670DD0082808BFDFF8B0
+:10257000D86708D0092808BFDFF8D06703D00A2839
+:1025800008BFDFF8CC677CD00B2808BFDFF80467F2
+:1025900077D0DFF8C06774E001F0BEFA0146606AE8
+:1025A00040B3012808BF022525D0022808BF042512
+:1025B00021D0032808BF06251DD0042808BF082500
+:1025C00019D0052808BF0A2515D0062808BF0C25F4
+:1025D00011D0072808BF10250DD0082808BF2025D6
+:1025E00009D0092808BF402505D00A280CBF80253E
+:1025F0000B2800D001256268B1FBF5F650080021D8
+:1026000010EB062051EB166141E0606A002836D0DD
+:10261000012808BF4FF4800633D0022808BF4FF4CA
+:1026200000162ED0032808BFDFF82C6729D0042815
+:1026300008BF4FF4801624D0052808BFDFF81C67B8
+:102640001FD0062808BFDFF818671AD0072808BF70
+:102650004FF4002615D0082808BF4FF4802610D06C
+:10266000092808BF4FF400360BD00A2808BF4FF4E2
+:10267000803606D00B2808BF4FF4004601D04FF437
+:102680000006C246002116EB52004AEB010100236E
+:10269000FEF776FE064601E04FF00108A6F5407011
+:1026A000DFF8C016884280F0D1812168CE60CFE18A
+:1026B000012808BF02251AD0022808BF042516D019
+:1026C000032808BF062512D0042808BF08250ED00D
+:1026D000052808BF0A250AD0062808BF0C2506D001
+:1026E000072808BF102502D0082808BF202575D06C
+:1026F000092808BF402571D00A280CBF80250B2867
+:102700006CD001256AE0606AB0B3012808BFDFF829
+:10271000840521D0022808BFDFF850051CD003280B
+:1027200008BFDFF8440617D0042808BFDFF84005CB
+:1027300012D0052808BFDFF834060DD0062808BFE0
+:10274000DFF8300508D0072808BFDFF82C0503D0D4
+:10275000082808BFDFF82C057AD0092808BFDFF861
+:10276000280575D00A2808BFDFF8200570D00B288F
+:1027700008BFDFF81C056BD0DFF8D40568E001F076
+:10278000CBF90146606A40B3012808BF022525D075
+:10279000022808BF042521D0032808BF06251DD024
+:1027A000042808BF082519D0052808BF0A2515D018
+:1027B000062808BF0C2511D0072808BF10250DD00A
+:1027C000082808BF202509D0092808BF402505D0C2
+:1027D0000A280CBF80250B2800D001256068B1FBBA
+:1027E000F5F1420802EB4102B2FBF0F632E0666A14
+:1027F00066B3012E2CD0022E08BF484628D0032EE7
+:1028000008BF42F6AA2023D0042E08BF70461FD06E
+:10281000052E08BF41F698101AD0062E08BF41F2C7
+:10282000545015D0072E08BF604611D0082E08BF9F
+:1028300018460DD0092E08BF104609D00A2E08BF31
+:10284000084605D00B2E08BF284601D04FF4803033
+:1028500000F014F9B6B201E04FF00108A6F1100043
+:10286000504580F0F3800AEA0601C6F342000143B6
+:102870002068C160ECE0012F07D0022F35D0042F73
+:1028800070D0082F00F0A580D7E001F097F901463D
+:10289000606A40B3012808BF022516D0022808BF8D
+:1028A000042512D0032808BF06250ED0042808BF2F
+:1028B00008250AD0052808BF0A2506D0062808BF23
+:1028C0000C2502D0072808BF10257AD0082808BF99
+:1028D000202576D0092808BF402572D00A280CBFD1
+:1028E00080250B286DD001256BE0606AB0B301280C
+:1028F00008BFDFF8781333D0022808BFDFF8701361
+:102900002ED0032808BFDFF86C1329D0042808BF95
+:10291000DFF8641324D0052808BFDFF860131FD048
+:10292000062808BFDFF858131AD0072808BFDFF8B9
+:10293000541315D0082808BFDFF84C1310D009280D
+:1029400008BFDFF848130BD00A2808BFDFF8401390
+:1029500006D00B2808BF4FF2244101D0DFF8341312
+:10296000606831E001F0D8F80146606A40B30128A0
+:1029700008BF022525D0022808BF042521D003283E
+:1029800008BF06251DD0042808BF082519D0052832
+:1029900008BF0A2515D0062808BF0C2511D0072826
+:1029A00008BF10250DD0082808BF202509D0092808
+:1029B00008BF402505D00A280CBF80250B2800D071
+:1029C00001256068B1FBF5F101EB5001B1FBF0F6B8
+:1029D00031E0666A6EB3012E08BF484629D0022E48
+:1029E00008BF704625D0032E08BF41F2555020D0B5
+:1029F000042E08BF60461CD0052E08BF40F6CC4010
+:102A000017D0062E08BF40F6AA2012D0072E08BF06
+:102A100018460ED0082E08BF10460AD0092E08BF4F
+:102A2000084606D00A2E08BF284602D00B2E08BF43
+:102A3000802000F023F8B6B201E04FF00108A6F1C3
+:102A40001000504502D22068C66001E04FF0010836
+:102A500004F1680001214180018000214160816012
+:102A60004046BDE8F28F00001B2D000800800040AA
+:102A7000F369FFCF0038014088000058616800EB1F
+:102A80005100B0FBF1F6704790F82810CA0706D540
+:102A900002685368C16A23F400330B43536090F813
+:102AA00028108A0706D502685368016B23F4803327
+:102AB0000B43536090F828104A0706D50268536804
+:102AC000416B23F480230B43536090F828100A07CE
+:102AD00006D502685368816B23F400430B435360AF
+:102AE00090F82810CA0606D502689368C16B23F4D3
+:102AF00080530B43936090F828108A0606D502682D
+:102B00009368016C23F400530B43936090F82810F2
+:102B10004A0610D502685368416C23F480130B43B6
+:102B20005360416CB1F5801F05D15368816C23F46B
+:102B3000C0030B43536090F828100A0606D50168BD
+:102B40004A68C06C22F4002202434A607047F8B51C
+:102B5000044604F17C050020E8606FF07E4701F038
+:102B6000BDF80646206801680A0708D50097334675
+:102B700000224FF40011204600F016F860B92068DA
+:102B800001684A070AD50097334600224FF48001B6
+:102B9000204600F009F808B10320F2BD202068604B
+:102BA000A86000202870F2BD2DE9F041069C054682
+:102BB0000E4690461F462868C1693140B1420CBF9D
+:102BC0000120002040451CD114F1010FF3D001F089
+:102BD00085F8C01B844200D314B900F015F80CE04E
+:102BE000286801684A07E6D5C1690A05E3D54FF4AC
+:102BF0000062026200F008F8C16000210170032049
+:102C000000E00020BDE8F0812868016821F4D0715F
+:102C100001602868816849084900816005F17C00ED
+:102C2000202141608160704701680A6822F0C0027B
+:102C30000A6001688A6822F400028A602021C0F8D4
+:102C40008010704701680A6822F490720A60DFF809
+:102C50002011026893680B4093602021C0F8841013
+:102C60000021C16670470000FFF4FF1100127A00D6
+:102C700000093D00AAB0280080841E00006A1800E8
+:102C80005558140040420F0020A1070090D00300C7
+:102C900048E801000024F400816A00680268930695
+:102CA00044BF084600F08DBB0020A1F8560008681C
+:102CB000826822F0800282600868FFE7016841F0C4
+:102CC000400101607047806A01F00EB8F8B5846A6F
+:102CD00004F1800504F1560728686E6821688A6847
+:102CE000110606D5212804D1002038802046FFF7A0
+:102CF0009BFF20688168480606D5222E04D100205B
+:102D000038812046FFF79EFFA86840F01000A860B9
+:102D10002046BDE8F24000F0B3BA806A00F15601E7
+:102D200000220A810A8000F0ABBA00000000127A8B
+:102D30000000093D00AAB0280080841E00006A1827
+:102D4000005558140040420F0020A1070090D00306
+:102D50000048E801000024F40055150000CC0C00E8
+:102D600000AA0A0000FD0F005461510000D4300099
+:102D7000FEFFFFEF694981B00A6802430A600968F3
+:102D8000084008E0664881B0016841F40021016014
+:102D9000006800F400200090009801B0704738B53A
+:102DA0008AB004466846142100F0A0FF20685D4AFE
+:102DB0005D4990423ED108685C4D40F001000860DA
+:102DC000096801F00101059105980120FFF7D2FF84
+:102DD0000C20009002210020019102900321082084
+:102DE000039100F06AF8402000F060F8082000F03D
+:102DF00064F84F482860112000F065F808B101F030
+:102E0000E5F84FF088500690002101200791ADF8B9
+:102E10002010099006A9284601F0DAF808B101F05F
+:102E2000D5F86567AC6200220021252001F012F977
+:102E3000252037E03F4A904236D148683E4D40F465
+:102E400080404860486800F4804005900598012063
+:102E5000FFF790FF0220FFF78DFF4FF4006000F0B6
+:102E600025F8072000F029F8C02000900221012059
+:102E700001910290032107200391049069462F4895
+:102E800001F05CF92E4828600F2000F01CF808B112
+:102E900001F09CF86567AC6200220021242001F05B
+:102EA000D9F8242001F0F3F80BB030BD00900221D6
+:102EB00000200290039001917047049069464FF002
+:102EC000904001F03BB968601020A8600020E860E5
+:102ED0008020286100206861A861E8612862284696
+:102EE00000F034B810B5044616492068884213D162
+:102EF00001F000FA01F0FEF91348016821F4407175
+:102F000041F480710160026842F400420260204690
+:102F1000BDE8104001F002BA10BD00004C0000589E
+:102F200050000058008000405C0000582C15002024
+:102F300044000240003801408C1500200004004885
+:102F400044040240002800409000005838B50400B6
+:102F500001D1012032BD2168DFF8FC02814204F179
+:102F6000240500F042F8022068700A68A0686FF338
+:102F70000E120243E0680243206902436069024383
+:102F8000A0690243E0690243206A02430A602046C6
+:102F900000F039F9A068B0F5804F04BF00216160EE
+:102FA000696A207900F014F838B1052805D2204666
+:102FB00000F043F900F012F803E000202863686392
+:102FC000A8630020A861012068700020287032BD2D
+:102FD0000860A96AE86A486060687047296B002049
+:102FE0000860696BA86B486070470AD2DFF86C0212
+:102FF00042181423B2FBF3F292002A62DFF8600257
+:1030000009E0DFF8600242181423B2FBF3F29200E9
+:103010002A62DFF85402E8617047F8B5044604F10B
+:10302000240600253078012801D10220F2BD0127B5
+:103030003770707801282FD102277770B56120682A
+:1030400007687F087F000760204600F0C0F821680D
+:10305000F06820B10A6842F00E020A6008E00868D1
+:1030600020F0040008602068016841F00A01016056
+:10307000706A0168CA0303D5026842F48072026074
+:10308000306B18B1016841F48071016020680268FA
+:1030900042F00102026001E0357002252846F2BDCF
+:1030A00038B500F1240200245178022903D004200D
+:1030B0009061012428E001680B6823F00E030B6087
+:1030C00001680D686D086D000D60516A0B6823F48E
+:1030D00080730B60012192F82030D56903F01C0346
+:1030E00099406960936AD16A5960116B31B10B687C
+:1030F00023F480730B60536B916B59600121517005
+:103100001470516901B18847204632BDF8B500F10D
+:1031100024010423CA6914680268156891F82060C4
+:1031200006F01C0603FA06F73C4210D06F070ED5D6
+:103130001468A50603D4156825F00405156000F091
+:103140003DF8C968002938D0BDE8F440084702239B
+:1031500003FA06F73C4213D0AF0711D51468A50651
+:1031600005D4156825F00A05156001224A7000F0A3
+:1031700025F800220A708968F9B1BDE8F4400847D3
+:10318000082303FA06F6344217D02B0715D5136827
+:1031900023F00E031360012291F82030CC6903F074
+:1031A0001C039A40626001228A614A7000220A7000
+:1031B000096911B1BDE8F4400847F1BD91F820203C
+:1031C000CC6902F01C02934063607047000078B540
+:1031D000C56C046D6C60446D14B1846DC56D656023
+:1031E000012590F84440066C04F01C04A54075606D
+:1031F000046863608068102802D1A260E16071BD3C
+:10320000A160E26071BD416C0268134B89089A426B
+:1032100034BF164B164B03EB8101816402F0FF02B1
+:10322000083A1421B2FBF1F1124AC26401F01C0108
+:10323000012202FA01F10165704701790E4A02EBA1
+:1032400081024265491E0D4A826501F00301012297
+:103250008A40C2657047000008040240F8FFFDBFC5
+:1032600000000240F8FBFDBF0004024000080240DD
+:103270001C08024080080240FC080240400902404D
+:103280007047000010B500F17C010A78012A01D1D5
+:10329000022010BD01230B7024224A6002681368CB
+:1032A00014686408640014600022426623F000532E
+:1032B00000680360202048600020087010BD70B5D1
+:1032C00000F01EF801D1022070BD00F01FF822F0BE
+:1032D000604209E070B500F013F801D1022070BD22
+:1032E00000F014F822F0606211438160204600F083
+:1032F0001AF820680660202068600020287070BDE1
+:10330000044604F17C0528780128704701222A70C0
+:103310002420686020680668026852085200026033
+:10332000206882687047FFB50FF254020FF258060A
+:10333000D2E9003402A9C1E90034D6E90071CDE92F
+:103340000071416E11B90121012213E001688A6800
+:103350008968520E02F00702490F02AC655CA45C5A
+:103360001DF801101DF80220ED00E40095FBF1F1BD
+:1033700094FBF2F2683041800280FFBD0000000043
+:103380000101010307010000080402040801010112
+:103390007047000010B5002488B9114803600E483A
+:1033A0000E4B0360FEF7C6FD012805D007D30328A6
+:1033B00004D038BF022402E0012400E003242046A8
+:1033C00010BD00680549884204D1054908680028F5
+:1033D00018BF004770470000A013002000380140CC
+:1033E000C0170020704770474FF0B040006800F0F1
+:1033F000F000B02888BFB02070472DE9F0410400EC
+:1034000051D0207881064FF0B04535D5A868E968DD
+:1034100010F00C0001F0030103D00C2808BF0129B3
+:1034200043D12868800702D5E06900283BD0FFF728
+:10343000DBFF616A884207D2084600F0D0FB002813
+:1034400031D100F075FA0FE0286820F0F000014358
+:1034500029606968206A21F47F4141EA002169609E
+:10346000606A00F0BCFBF0B900F097FFDFF80808D5
+:10347000006801F021F8B0B92078C1070DD5A8681F
+:10348000E96800F00C00082801F0030103D00C28C3
+:1034900008BF03292CD12868800340F1408160686F
+:1034A000002840F03C8101203BE2E06980B12968BE
+:1034B00041F0010100F026FB06462868800700F174
+:1034C0002B8100F00BFC801B0328F6D3032028E29D
+:1034D00028684008400000F0E7FB0646286800F036
+:1034E00023FAC9D000F0FAFB801B0328F6D3EDE7DE
+:1034F0006068B0F5803F06D0B0F5A02F296807D1ED
+:1035000041F480212960286840F48030286006E07A
+:1035100021F4803129602A6822F480222A606068C0
+:1035200060B100F0DBFB06462868800300F1F780FD
+:1035300000F0D4FB801B6528F6D3C7E700F0CEFB74
+:1035400006462868400C10F0010000F0E88000F00A
+:10355000C5FB801B6528F4D3B8E700F0BFFBC01B98
+:103560000328C0F01081B1E7E06878B1296841F420
+:10357000807100F0C7FA06462868400500F1168100
+:1035800000F0ACFB801B0328F6D39FE7286820F4EB
+:10359000807000F089FB06462868800A10F0010060
+:1035A00000F0DB8000F09AFB801B0328F4D38DE74A
+:1035B00000F094FBC01B0328C0F00A8186E740F0AE
+:1035C000010000F0C6F907467068800700F11B8112
+:1035D00000F084FBC01B0328F6D377E7706820F067
+:1035E000040000F0B6F907467068C00810F001004A
+:1035F00000F0188100F072FBC01B0428F4D365E7CB
+:103600000528306806D140F004003060316841F090
+:10361000010105E0400840003060316821F00401FC
+:103620003160A06841F2893768B100F057FB8046ED
+:103630003068800700F10B8100F050FBA0EB080020
+:10364000B842F5D342E700F049FB8046306800F00D
+:103650006BF900F0FC8000F041FBA0EB0800B842E1
+:10366000F4D333E700F03AFBC01B0328C0F0FD8021
+:103670002CE7B06840084000B06000F02FFB074620
+:10368000B06800F051F900F0F48000F027FBC01B97
+:103690000328F5D31AE700F021FB801B0328C0F0B4
+:1036A0001A8113E700F01AFB001B0328C0F03481D5
+:1036B0000CE7286881010CD4296841F080712960E9
+:1036C000E86840F08050E86000F008FB0446286895
+:1036D000810100F1258100F001FB001B0328F6D3D6
+:1036E000F4E60C2930D0286820F080702860E96862
+:1036F00089088900E960E86820F08050E86000F0FF
+:10370000EDFA04462868810140F10A8100F0E6FAEA
+:10371000001B0328F6D3D9E600F00AF9ACE62078BE
+:1037200081071AD5A868E96800F00C00042801F0A8
+:10373000030104D00C2808BF02297FF415AF2868C4
+:10374000400503D5E06800283FF4ADAE6968206904
+:1037500021F0FE4141EA006169602168DFF81C65E3
+:1037600011F0180F38D0606900283FF437AFC90650
+:1037700070687FF524AF800709D4706840F00100BD
+:1037800000F0E7F80746706880077FF5E6AE7068DE
+:1037900040F0040000F0DDF80746706800070DD423
+:1037A00000F09CFAC01B0428F7D38FE668682169F3
+:1037B00020F0FE4040EA01606860CEE77068A169D1
+:1037C00020F4706040EA0120706000F0BFF8074606
+:1037D00000F0A9F87FF4ECAE2078410737D5DFF888
+:1037E000A0743868C10529D400F084FD00F076FA91
+:1037F00080463868C10521D400F070FAA0EB0800BB
+:103800000328F6D362E6706820F0040070607068E8
+:10381000C00810F00100DFD000F060FAC01B0428DF
+:10382000F5D353E600F092F8074600F07CF8D3D0C9
+:1038300000F054FAC01B0328F7D347E6A06801281C
+:103840007FF4DEAE306840F001003060E9E62178B8
+:1038500048060ED5A06A00283FF40BAFB16841F0CE
+:103860000101B16000F03AFA0746B06880077FF5C1
+:10387000F9AEE06A002853D0A968EA68022801F08E
+:103880000C017FF42EAF236B02F00300984202BFBD
+:1038900002F07000636B984214D1A36BC2F3062050
+:1038A000984202BF02F47810E36B98420AD1236C6D
+:1038B00002F06060984202BF02F06042606C824297
+:1038C0003FF4F7AE0C293FF4EEAD286820F080708D
+:1038D00000F0EAF90646296888013FF5DCAEE968A0
+:1038E000DFF8A003A26B0140206B0143606B014332
+:1038F000E06B41EA02210143206C0143606C01430B
+:10390000E960286840F080702860E96841F08051E3
+:10391000E96000F0E3F90446286881017FF5C2AE52
+:103920000020BDE8F0817068400810F00100704789
+:103930002968606A21F0F001014329606868216A02
+:1039400020F47F4040EA01206860704770684008BA
+:103950004000706000F0C2B92DE9F84304008846C9
+:1039600044D0DFF8246300F0C8F847D200F0CDF867
+:10397000074600F0C2F841D000F0B0F9C01B0228A1
+:10398000F7D90320B7E000F0A9F9401B022843D97A
+:10399000F7E700F0A3F9A0EB090002284CD9F0E703
+:1039A00000F09CF9A0EB0900022854D9E9E700F0E7
+:1039B00095F9401B02285DD9E3E700F08FF9401B21
+:1039C000022867D9DDE700F089F9401B484577D325
+:1039D000D7E7032802D13968890103E00028396854
+:1039E00002D1890762D401E049055FD4012082E059
+:1039F00000F074F9C01B022872D9C2E72078810751
+:103A00004FF0B0470BD5B968A06821F0F001014331
+:103A1000B96000F063F90546B868C003B3D52078F3
+:103A2000DFF8505281060AD52968606921F0F0015B
+:103A3000014300F067F8814628688003A9D5207803
+:103A400041060BD52968A0690909090141EA10114D
+:103A500000F058F881462868C003A1D520784107B6
+:103A60000BD5B968E06821F4E0610143B96000F06A
+:103A700035F90546B868800399D5207801070CD53B
+:103A8000B868216920F4605040EAC100B86000F0D5
+:103A900025F90546B86840038FD52078C10717D5AA
+:103AA0006068022895D1396889039FD5B96889086B
+:103AB00040EA8100B86041F2893900F00FF905460B
+:103AC000B868616800F00C00B0EB810F7FF47BAF49
+:103AD000306800F00700804505D200F016F8074670
+:103AE00000F00BF884D100F058FC00F01BFDBDE89D
+:103AF000F24300F0E1BCBDE8F283306800F007005B
+:103B000040457047296000F0E9B83168C90848EAC3
+:103B1000C101316000F0E2B838B54FF0B0445C4DFF
+:103B2000A16811F00C0106D1FFF75EFCC0F3031091
+:103B300055F8200032BD0429564A05D008295648B8
+:103B400004D12168C90222D5104632BDE16801F0D6
+:103B50000301022904D0032904D12168C90207D531
+:103B6000104605E0FFF740FCC0F3031055F82000B5
+:103B7000E168E268E368C1F306214843C2F3021139
+:103B8000491C5B0FB0FBF1F05B1CB0FBF3F032BDE6
+:103B900080B5FFF7C1FF3D49FFE7404A0968C1F31F
+:103BA000031152F82110B0FBF1F002BD80B5FFF710
+:103BB000EFFF00F010F8C1F3022106E080B5FFF737
+:103BC000E7FF00F008F8C1F3C22112F8211001F05C
+:103BD0001F01C84002BD2D49314A0968704770B5C0
+:103BE0002B49B1282EBFCC6AC0F3031051F82040F6
+:103BF0002048056800F0B0FC28492A4A05F00F0566
+:103C000051F82510B4FBF1F10024B1FBF2F1B0F54D
+:103C1000007F0FF2B802204609D10FF2940353F847
+:103C200020508D4214D2401C0328F8D912E00FF224
+:103C3000900353F820508D420AD2401C0328F8D339
+:103C400008E000F04BF8801B03280BD3032070BD65
+:103C500052F820400C4D2868C00844EAC00000F02B
+:103C600023F80646296801F00701A142E9D10020A6
+:103C700070BD0000080100586C1000209000005832
+:103C8000000400588C80C111004000580800005802
+:103C9000784400080024F4000048E8013844000893
+:103CA000A47D000840420F00286000F017B8000013
+:103CB0001200000024000000360000004000000058
+:103CC000060000000C0000001000000000000000D2
+:103CD000010000000200000003000000014800682D
+:103CE000704700BF6810002070470000002200F0FD
+:103CF0003BBC0000A74900E0A74981B00A68024325
+:103D00000A60096808400090009801B0704710B53B
+:103D100000F0F4FBA14C606840010ED56068C00063
+:103D20000BD400F0E7FA00F0E5FA206840F48030A8
+:103D30002060216821F48031216000F0F0F800203B
+:103D400000F02CFC40B180799549E160E16821F4F4
+:103D50007C5141EA0021E16000F048F89148924C22
+:103D6000016800220260026902F050020261012033
+:103D7000FFF7C2FF0220FFF7BFFF0420FFF7BAFFE3
+:103D80000120FFF7B7FF0220FFF7B4FF00220F2149
+:103D90000E2000F05FF90E2000F079F900220F21CB
+:103DA0003A2000F057F93A2000F071F900217F48DD
+:103DB00041600F218160046047F6FF71C1600021FE
+:103DC00001618161C16100F0FBFBCA206062FF21DB
+:103DD00053206062A068C008C000A060616200F06B
+:103DE00093FC4FF0FF3000F009FDFAE730B5A9B0C1
+:103DF00017A84821FFF77AFF01A81C21FFF776FFDB
+:103E000008A83C21FFF772FF6448694C016821F063
+:103E1000180101604FF48032206820F4C06040F443
+:103E2000007020604FF48075216801F4C06100913A
+:103E300007210098179101201990002140201B9024
+:103E4000189222911A9517A8FFF7D7FA6F200190C0
+:103E500002210020029103900490059006900790A3
+:103E6000012101A8FFF778FD43F603000890002127
+:103E70004FF48040139009910A911020022115906F
+:103E80001491129508A800F0AAFDE06920F07000D6
+:103E9000E06148480168C1F303200090009830B900
+:103EA000E1690909090141F00401E16108E00098B4
+:103EB000E169801E80F30400090940EA0110E06115
+:103EC000E06940F40040E06129B030BD10B53A4CE3
+:103ED0003A4800F017F84FF40040E06100202062FB
+:103EE0006062A0622046FDF7E5FF00212046FFF753
+:103EF000E6F900212046FFF7EDF92046BDE8104025
+:103F0000FFF7C0B920604FF4E13060600020A0608E
+:103F1000E06020610C2060610020A06170472848AB
+:103F200081B0016841F4801101603F21006800F414
+:103F3000801000900098234841604161016841F47D
+:103F40007C110160026942F47C120261016841F057
+:103F50003F010160026942F03F02026101B0704717
+:103F600038B50446FFF7BAFE14F1010F054609D033
+:103F700000F0DBFA041905E01348016821F00401A0
+:103F8000016030BFFFF7AAFE401BA042F4D331BD51
+:103F900000000000480000584C00005890000058F5
+:103FA000FECAFECA8008005800280040B81600204B
+:103FB000000400585875FF1FA0130020003801406E
+:103FC00050000058040C005810ED00E0704700004D
+:103FD00018B500F12402507801281BD11378012B69
+:103FE00001D1022012BD536A10701C680A480440B7
+:103FF00008680443C868401E44EAC0444868044353
+:10400000087A497A44EA004444EA41241C600020CA
+:10401000107012BD012012BDFFFD00E00901020079
+:1040200081B002D43C48815405E03C4802F00F02C4
+:10403000104400F8041C01B07047394A13684FF669
+:10404000FF0100020B4000F4E060184335490843CB
+:104050001060704738B5324B1C68C4F30223C3F1BB
+:104060000704052C28BF04241D1D072D34BF002381
+:10407000DB1E012505FA04F4641E2140994005FA6F
+:1040800003F35B1E1A401143BDE83440C6E701004C
+:1040900007D4012200F01F01234B8A40400943F856
+:1040A0002020704701000BD4012200F01F011F4B9C
+:1040B0008A40400943F82020BFF34F8FBFF36F8F32
+:1040C000704710B5401EB0F1807F01D3012010BDB4
+:1040D000174C60600F214FF0FF30FFF79FFF002269
+:1040E000A26007202060002010BD010007D401223B
+:1040F00000F01F010F4B8A40400943F82020704711
+:10410000010007D4012200F01F010B4B8A40400937
+:1041100043F820207047000000E400E018ED00E0C4
+:104120000CED00E00000FA0500E100E080E100E0B5
+:1041300010E000E000E200E080E200E02DE9F84F4E
+:104140004FF0000C644A654BDFF894814FF00F0983
+:1041500082460F4633E0634DAA4514BF0725042568
+:104160008D40254348F82E50C1431C6801EA040ED7
+:104170007C68E50348BF40EA0E0EC3F800E05C68C7
+:1041800001EA040E7C68A50348BF40EA0E0EC3F89E
+:1041900004E0146801EA040E7C68E50248BF40EAC6
+:1041A0000E0EC2F800E0546801EA040E79688C0231
+:1041B00048BF40EA0E0EC2F804E00CF1010C396869
+:1041C00031FA0CF076D0012000FA0CFE1EEA010054
+:1041D000F3D07C68022C18BF122C4FEA8C0110D14E
+:1041E0004FEADC040AEB840401F01C05266A09FA94
+:1041F00005FB26EA0B06D7F810B00BFA05F5354398
+:1042000025624FEA4C040325DAF8006097F804B001
+:10421000A540ED430BF0030B2E400BFA04FB4BEAD9
+:104220000606CAF800607E68012E18BF022E03D071
+:10423000112E18BF122E17D1DAF80860D7F80CB07B
+:104240002E400BFA04FB4BEA0606CAF80860DAF8BF
+:10425000046026EA0E0E7E68C6F3001606FA0CF617
+:1042600046EA0E06CAF80460DAF80C603540BE680B
+:1042700006FA04F42C43CAF80C407C68E4009CD590
+:104280004FEA9C0E58F82E5001F00C0109FA01F487
+:1042900025EA0404BAF1904F08BF002509D0124D59
+:1042A000AA4508BF012504D0104DAA457FF453AF9D
+:1042B000022555E7BDE8F18F81B0002A14BF816166
+:1042C000816201B070470A4A136803421CBF106044
+:1042D00000F086BA704700000008005880080058B7
+:1042E0000800014000100048000400480008004891
+:1042F0000C0800580248016841F480710160704761
+:10430000000400588A60FF2102685162012180F890
+:104310002110002180F820100020704790F8201014
+:10432000012901D102207047012280F820200221BA
+:1043300080F82110CA210268516253210368596232
+:1043400001688A6842F02002FFF7DCBF3249002092
+:1043500008604FF4E0223148016841F470010160C7
+:104360004FF0B041086840F0010008608A602C48B6
+:104370000A6802402B480A60036823F005030360C3
+:10438000426852085200426000222748C86008680C
+:1043900020F4802008608A6170474FF0B0410FF22E
+:1043A000D8000A68C2F3031250F822008A6802F0AB
+:1043B0000C02042A04D0082A04D00C2A04D01CE0E1
+:1043C0001A481AE01A4818E0CA68CB68C3F3021307
+:1043D00002F003025B1C022A08BF144802D0032A21
+:1043E00008BF1348B0FBF3F2C868CB68C0F30620DF
+:1043F0005B0F42435B1CB2FBF3F00E4A0FF2380333
+:10440000106088681168C0F3031053F82000B1FBF6
+:10441000F0F010607047000008ED00E088ED00E06B
+:10442000FBFEF6FA94000058001004220024F40069
+:104430000048E801741000200100000003000000A3
+:10444000050000000100000001000000060000005F
+:104450000A0000002000000002000000040000002C
+:104460000800000010000000400000008000000074
+:104470000001000000020000A0860100400D0300C2
+:10448000801A060000350C0040420F0080841E0098
+:1044900000093D0000127A000024F40000366E018D
+:1044A0000048E801006CDC02000000000000000091
+:1044B000000000000000000070B50F4E0446B06818
+:1044C0000025A8B1FFF764FBB2684FF47A71B1FB25
+:1044D000F2F1B0FBF1F0FFF7F4FD48B9102C07D270
+:1044E000002221464FF0FF30FFF7B4FD746000E07A
+:1044F0000125284670BD00BF68100020134810B584
+:10450000016841F4807101600320FFF796FD0020EF
+:10451000FFF7D2FF0024002814BF0124FEF732FC6D
+:10452000204610BD0A4840687047094880687047B7
+:10453000084805E00748016841F002010160704742
+:10454000016841F00101016070470000004000581F
+:1045500068100020042004E0DFF80800006800F480
+:10456000C06070470004005800B500BF13009646B5
+:104570009446103928BFA0E80C50FAD85FEA417C75
+:1045800028BF0CC048BF40F8042BC90728BF20F83B
+:10459000022B48BF00F8012B00BD00000146064871
+:1045A000064AC3798B4218BF904218BF0838F8D129
+:1045B0008B4218BF00207047F873FF1F0070FF1F69
+:1045C00038B5040044D094F8210028B9002184F8BB
+:1045D00020102046FEF786FC00F049F8FF2510B1B8
+:1045E00000F03FF834E02168DFF8B0008A6802404C
+:1045F0008A6021688A68636820690343A06903436D
+:104600001A438A602168E068086120680169A2682D
+:1046100041EA024101612068C16821F08001C16066
+:104620002068C16C89088900C1642168CA6CE3698B
+:10463000606903431A43CA6420688168880609D404
+:1046400000F020F830B120684562042100F01FF826
+:10465000012032BD20684562012184F8211000202C
+:1046600032BD20684562042184F821107047022081
+:1046700084F82100CA2021684862532022685062D1
+:10468000204626E020460BE02068C0F8248084F80D
+:104690002110002084F8200070470000BFFF8FFF2A
+:1046A00070B5044640F2E9362068C16821F0A001E7
+:1046B000C160FFF713FB05462068C168880606D471
+:1046C000FFF70CFB401BB042F6D3032070BD002067
+:1046D00070BD70B504462068C1684A0612D44FF018
+:1046E000FF32C26040F2E936FFF7F8FA054620686B
+:1046F000C168480606D4FFF7F1FA401BB042F6D372
+:10470000032070BD002070BD10B52348234C88B035
+:10471000016841F40041016000F040FA20490020A6
+:1047200000F0CDFB00F017FD0121012000F03BFA65
+:10473000002000F048FE012000F045FE022000F0BD
+:1047400042FE012000F067FE0121002000F077FE0C
+:1047500000F0CCFE134A0021402000F0B2F804F231
+:104760003C500FF245010090019169460FF23D0067
+:1047700000F0AAFF04F25470029004F5C96140F2FF
+:104780003C5005900391049402A800F035FF00F01E
+:10479000ABFE08B010BD0000080000582C800020BF
+:1047A000B81600200B5700087047000080B500F0D5
+:1047B000E1FC01F02DF8BDE804400021012000F0EB
+:1047C000F2B970474FF0FF3000F018B800214020D8
+:1047D00000F084B8022000F0A3B8022000F0A8B8CE
+:1047E000012804D0102804D0402804D0704701F0DC
+:1047F0002FB901F03CB901F03BB900002DE9FC47AD
+:10480000594CDFF86891A5692840A0614FF0010A72
+:104810004FF0FF3830E0491C54F831000642FAD01E
+:1048200004EBC107184079681040014208BFC7F87F
+:1048300004807E68304000F09BF860620AFA00F065
+:1048400086437E60EFF3108172B6626A20690AFACD
+:1048500002F2D24310402061022004EBC00353F85F
+:10486000086C1640401E43F8086CF6D181F310889E
+:10487000606A59F82010884763692069A269184066
+:10488000104207D0E069216A084203D1002103EAFF
+:104890000206C1E701F026FBEFF3108972B6216929
+:1048A00060690140A069014201BFE169206A0142DB
+:1048B000FFF787FF89F3108801F015FBA561BDE8BC
+:1048C000F38738B51446EFF3108572B600F050F850
+:1048D000264941F8204085F3108831BD10B5EFF32B
+:1048E000108272B6204B1C6904431C6153F831409E
+:1048F000204343F8310082F3108810BDEFF310819C
+:1049000072B6194A536923EA000005E0EFF31081FB
+:1049100072B6154A53691843506181F31088704785
+:10492000EFF3108172B6104AD3691843D061F4E7EF
+:104930002DE9F0410C4C626A266A2062012101FADD
+:1049400002F803E039464046FFF73CFF276AE56975
+:104950003D42F7D0404600F00BF825EA0707E76133
+:1049600026626062BDE8F081401000202C14002017
+:1049700002460020110C090404BF1020120412F09A
+:104980007F4F04BF083012020FF2180112F0704F6F
+:1049900004BF001D1201120FC0F11F00895C401AF4
+:1049A0007047000004030202010101010000000041
+:1049B00000000000DFF8D8110A68030903F47F2320
+:1049C00000019A4300F47F20DFE0DFF8C421136880
+:1049D000010C23EA014343EA0043136070472DE9C9
+:1049E000F041054600272868DFF8A8610105B846B0
+:1049F0002FD53468A86A04F44074844229D0FFF7A4
+:104A000079FC002C316805D1A86A21F4407101437A
+:104A100031601DE0306840F48030306021F4407136
+:104A2000326822F480323260A86A01433160306813
+:104A3000C0070DD5FFF752F9044641F289383068B6
+:104A4000800705D4FFF74AF9001B4045F7D3032739
+:104A5000B8462878DFF84041C10705D5E16F68689E
+:104A6000890840EA8101E1672878810705D5E16F6F
+:104A7000A86821F440610143E1672878C10644BF7A
+:104A80006869FFF7A2FF2878810644BFA869FFF78D
+:104A90009CFF2878410744BFE868FFF78BFF287820
+:104AA000010744BF2869FFF785FF2868C1050AD5BB
+:104AB000E16FE86921F040610143E167E869B0F125
+:104AC000006F00F05CF8286881051BD5286AB0F1FA
+:104AD000804F18BFB0F1004F00D018B9E16F21F03E
+:104AE000404108E0E16F21F04041E16720F0805053
+:104AF000E16F21F040610843E067286AB0F1C05FD0
+:104B000000F03DF8286841050AD5E16F686A21F098
+:104B100040510143E167686AB0F1005F00F029F895
+:104B20002868C10405D57168E86A21F44041014351
+:104B30007160286881040BD5A169686B21F0300190
+:104B40000143A161A169286B890840EA8101A16143
+:104B5000286841040AD5E16FA86B21F44071014334
+:104B6000E167A86BB0F5007F00F003F84046BDE8B0
+:104B7000F08103D1216841F480312160704703D175
+:104B8000216841F0807121607047104308607047D0
+:104B900088000058900000580C0000580C48002174
+:104BA00001604160704710B500F00CF85C6819B105
+:104BB000012904D1204301E024EA0000586082F377
+:104BC000108810BDEFF3108272B6014B70470000E1
+:104BD00084170020DFF83C150A6892B200E0024614
+:104BE000086880B28242FAD170472DE9FC41044640
+:104BF0001825DFF82485DFF82465684308EB0007F3
+:104C00003078062808D131787170347078754FF09B
+:104C1000FF307060002039E000F077F8B9680918BB
+:104C2000B96008F10803B96832786A439A5891422A
+:104C3000327813D308F1150315FB02FC13F80C307E
+:104C4000062B25D008F108066B43F358994222BF82
+:104C500008F115036A439A5CEED219E011463378E5
+:104C600069439A420BD008F1140308F1150C5B5C00
+:104C700015FB03F50CF805407A753B7500E07A7575
+:104C800008F114025454317871703470BDE8F68123
+:104C90001146694308F115035B5C062B04D008F14B
+:104CA000140615FB03F574557B753A7508F115026A
+:104CB0005454EBE7F8B5DFF86434DFF85C541E7841
+:104CC000182402466243B0422A4404D1187858702E
+:104CD000507D18700FE0167D507D92F815C005F1DB
+:104CE00015076643062807F806C004D0167D14355C
+:104CF00014FB00F42E55012010731878062802BF0B
+:104D000000294FF0FF315960F1BD10B5DFF80C44B8
+:104D1000606810F1010F0FD0FFF75CFF6168DFF8EA
+:104D20000024814261683CBF5388C918081A517831
+:104D300048431178C84000E0002080B210BD2DE942
+:104D4000F84FDFF8DC53DFF8DCB3D5F80880D8F88B
+:104D50000000DBF800104A0500F090F9DFF8BC63B2
+:104D6000DFF8B4A321F4806181604FF01809347832
+:104D70000AF1080019FB04F14758FFF7C6FF874204
+:104D800017D200270121B170062C3DD019FB04F485
+:104D90000AF108010AF108020959814223BF0AF108
+:104DA00008010959091A002111510AEB04014C7D2F
+:104DB000EAE7A9884118B94202D2AF880021E2E7A8
+:104DC0003F1ADFE7022802DA2878012800D07F1E88
+:104DD000D8F80000C1684A07FAD500F055F9DBF8A9
+:104DE0000C00000CBFB247EA0047CBF80C70FFF78D
+:104DF000F1FE7060A8680068816841F4806181609C
+:104E0000AFF30080BDE8F18FB8B20028DAD1FFF728
+:104E1000E1FE70600320BDE8F24FFFF766B92DE9AF
+:104E2000F843EFF3108872B6BD4DBB4BA86801681C
+:104E3000CA224A6253204862B84A886820F48060D7
+:104E4000886018201678374647431F44387B02286D
+:104E500026D13C68D7F810909078F0B17A7B012A7F
+:104E60000AD101213046FFF725FF88F310887968C1
+:104E7000304600F016F904E088F31088304600F060
+:104E8000C1F8A8680068CA214162224653214162E4
+:104E90004846314600F050F90BE0FFF750FF06E0BE
+:104EA000C8684207FCD500F07EF89F49086088F387
+:104EB0001088FF21A86802685162BDE8F183F8B547
+:104EC000974CA160CA2209684A6253224A62954AF5
+:104ED000136843F020031360136803F00703C3F162
+:104EE0000403237095682D0C05F07F056D1C65701B
+:104EF000EDB29268C2F30E02521C628092B2521E50
+:104F00006A43A2F5A072DA404FF6FF739A422CBFB3
+:104F1000A380A280854A136843F400231360844B66
+:104F20001D6845F400251D6048BB7C487A4E01236E
+:104F3000837018254FF0FF33436000235FFA83FC32
+:104F400006F10C0715FB0CFC4FF0000E07F80CE007
+:104F50005B1CDFB2062FF1DB06230370886820F4A8
+:104F60008060886000F01FF8D0600320FFF7C8F869
+:104F7000A1680868826842F48042826005E0C868DF
+:104F8000410544BF0320FFF7B0F8A1680A68FF207D
+:104F90005062002203210320FFF75CF8BDE8F240D5
+:104FA0000320FFF774B8C86800F0800060F49060D8
+:104FB000C8604FF400207047F0B504460025EFF3B9
+:104FC000108672B61827DFF850C10CF10C0007FBF1
+:104FD00005FE10F80E0010B16D1C062DF5DB062D38
+:104FE0000CD06F430CEB07000127077386F3108882
+:104FF0000461427303600D700020F0BD86F31088D9
+:105000000120F0BDF8B50746EFF3108472B6032017
+:10501000FFF748F8424DAE683068CA2141623A460F
+:1050200053214162182043494243895C02291BD124
+:1050300000213846FFF73EFE3848017806290ED198
+:10504000306838490A68530500F018F821F4806187
+:105050008160C1684A07FCD500F016F804E040788A
+:10506000884218BFFFF76BFEA9680A68FF205062EC
+:105070000320FFF70CF884F31088F1BD02D5C16856
+:105080004A07FCD481687047C16801F0800161F46F
+:105090009061C1604FF40020234908600320FFF7AE
+:1050A0002FB82DE9F04180460F46424618201A4994
+:1050B00042438C18207B022804BF4046FFF7A2FF22
+:1050C000EFF3108572B60320FEF7ECFF144EB068C4
+:1050D0000068CA2141625321416202202073A76007
+:1050E00067604046FFF781FD0C490A784978914294
+:1050F00002D0FFF724FE02E0A168081AA060FF209A
+:10510000B1680A6850620320FEF7C1FF85F310887A
+:10511000BDE8F0812828004084120020B417002048
+:1051200070170020082800400C080058000800589C
+:10513000800800589012002010470000484900E005
+:10514000484981B00A6802430A6009680840009033
+:10515000009801B0704780B5FFF7EAF9FFF7EAF968
+:105160004148016841F48031016000F0D8FEBDE89B
+:1051700001400EE000B587B068460FF218211C22EE
+:10518000FCF7BAF800F06FFA684600F015FF07B0B8
+:1051900000BDF0B585B068461421FEF7A7FD0026D6
+:1051A0000025002400210FF2DC0000EBC102907901
+:1051B00088B11368B3F1904F08D02C4FBB4208D090
+:1051C0002B4FBB4204BF9088044304E09088064301
+:1051D00001E090880543491C2229E4DB002002906D
+:1051E0000121032003900191B0B288B10090012009
+:1051F000FFF7A4FF0120FFF7A3FF69464FF090409F
+:10520000FEF79CFF0022B1B24FF09040FFF754F838
+:10521000A8B280B100900220FFF790FF0220FFF7B4
+:105220008FFF124E69463046FEF788FF0022A9B272
+:105230003046FFF741F8A0B280B100900420FFF79C
+:105240007DFF0420FFF77CFF094D69462846FEF7E5
+:1052500075FF0022A1B22846FFF72EF805B0F0BD79
+:105260004C0000584C0100589008005800040048B9
+:1052700000080048FEF72ABE13460A4601460020F1
+:10528000FEF788B800000048010000000000004858
+:10529000010000000000004801000000000000487C
+:1052A000010000000000004801000000000000486C
+:1052B000010000000000004801000000000000485C
+:1052C000010000000000004801000000000000484C
+:1052D000010000000000004801000000000000483C
+:1052E000010000000000004801000000000000482C
+:1052F000010000000000004801000000000000481C
+:10530000010000000000004801000000000000480B
+:1053100001000000000000480100000000000048FB
+:1053200001000000000000480100000000000048EB
+:1053300001000000000000480100000000000048DB
+:1053400001000000000000480100000000000048CB
+:1053500001000000000000480100000000000048BB
+:1053600001000000000000480100000000000048AB
+:10537000010000000000004801000000000000489B
+:10538000010000000000004801000000000000488B
+:10539000010000000000000000000000000000000C
+:1053A0008452000824800020288000202204040069
+:1053B000444981B00A6802430A60096808400090C5
+:1053C000009801B0704778B585B00446684614214E
+:1053D000FEF78CFC0220FFF7EBFF00F010F80095C1
+:1053E000012001900021022003900291694656F8A5
+:1053F0002400FEF7A3FE00F008F806B070BD0FF21F
+:10540000D400314E30F81450704756F82400002272
+:105410002946FEF751BF0FF2BC012B4B31F810109B
+:1054200053F820000122FEF747BF0FF2A801264BD8
+:1054300031F8101053F820000022FEF73DBFF0B500
+:1054400085B005460C4668461421FEF74FFC2DB189
+:10545000012D08BF102002D0022D02D10120FFF73C
+:10546000A7FF2000194E0FF274070DD137F8150071
+:10547000009000210191012002900221039100F08F
+:105480001BF80120FEF76CFD012C13D137F8150035
+:10549000009001210E480190029100F00DF80FF2EA
+:1054A0004400445D00220F2160B2FEF7D3FD60B2DC
+:1054B000FEF7EDFD05B0F0BD694656F82500FEF794
+:1054C0003DBE00004C000058281000203410002081
+:1054D0000000211020000100020000000100100067
+:1054E00040000000060A170000F0E2BD6C486D495C
+:1054F000016001F12002426001F13002826001F19D
+:105500003C02026201F14402C26001F14C020261FC
+:1055100001F16802426101F16C0282617831C1617E
+:1055200000F0D8BD38B504465F4D05F1100000F01D
+:1055300039FE5B494868A1680160E168C160456067
+:1055400005F11001816000F0E1FD58482DE080B5C3
+:1055500053494A6813680120187200F0DDFD0020ED
+:1055600002BD38B5514C504D07E0694605F11000B9
+:1055700000F044FE00982168884705F1100000F013
+:1055800014FE0028F1D031BD48484168084738B5BD
+:105590000446474D284600F005FE4148C068A16812
+:1055A0000160456000F0BDFD42482168016061680E
+:1055B0004160002032BD80B53949CA6813681020A7
+:1055C000187200F0B4FD002002BD3549CA6839499F
+:1055D00010680B68184738B5364C354D06E06946FB
+:1055E000284600F00BFE009861688847284600F0C6
+:1055F000DCFD0028F3D031BD38B504462E4D2846D9
+:1056000000F0D0FD2D4800F0CDFD25480069A168CF
+:105610008160E168C1600561216801606168416085
+:10562000216941616169816131BD80B501462348CD
+:1056300000F0CEFDBDE802400FF2050000F087BD8E
+:1056400038B5174C1D4D08E06946284600F0D6FDD8
+:1056500000992069006900F0BBFD284600F0A5FD17
+:105660000028F1D031BD10B5154C204600F09AFD50
+:105670000B4841690C60BDE8104000F07CBD1CB5D2
+:105680000F4C06E06946204600F0B8FD009800F097
+:1056900019F8204600F089FD0028F3D013BD000062
+:1056A00000800020B88900208C88002094170020FA
+:1056B000A48800209C1700203C8A00208C17002022
+:1056C000448A0020704700007FB50C464D4D61684C
+:1056D0004D4EE8612962284600F0A2FD24687460FE
+:1056E00006F1080000F05EFD012000F068F80120DE
+:1056F0003070296841B10FF2E9000FF2ED0200901D
+:1057000001920294684688477FBD1FB53E4C04F164
+:10571000080000F04AFD00BB2178F1B1694604F1B0
+:10572000080000F06BFD3748C16949B1009802904C
+:1057300001228DF8042001A888479DF8040000E0AC
+:1057400001202070207818B10098FFF76EFF04E068
+:10575000009904F1080000F031FD04F1080000F0A8
+:1057600024FD28B9207818B104F10800FFF72EF8BD
+:105770001FBD2DE9F04105460E4690461C4600200F
+:1057800000F01DF8204F7868A0F80950C672324624
+:1057900041460C30FBF7A0FD1A4A13690021002096
+:1057A000984748F2E800FFF718F879688A78D21C21
+:1057B00004F10800FBF790FDBDE8F04101201CB5A5
+:1057C0001049124C096A20B901B1884700202070A5
+:1057D00013BD0120207011B1BDE81C40084713BD66
+:1057E0000020FEF7F7BF000010B50146064C04F19B
+:1057F000080000F0EDFC04F10800BDE81040FEF7E1
+:10580000E5BF0000DC16002060170020CC17002048
+:1058100010B58EB002A80FF29C61DFF81044302260
+:10582000FBF76AFD0FF255400190009469460FF2B4
+:105830003540DFF8FC4300F0FDFC01210220FFF7BA
+:10584000B2F9DFF8F02300212020FFF73AF802A890
+:1058500000F0AAFB00F00DF900F0D0FD0FF2393294
+:1058600000210120FFF72DF80FF2693200210220FC
+:10587000FFF727F8002084F89000202000F062FE57
+:1058800000F094FE0FF2C133002204F191010020D8
+:10589000FFF792FB0EB010BD2DE9F043074685B02F
+:1058A0007878DFF88C43DFF8906305284FF0000824
+:1058B00004F1900554D03E2863D0FF280DD101207B
+:1058C0003072B7F80300042842D040F20741884202
+:1058D00004D040F60201884218D0A6E07879022868
+:1058E00004BFB9790029F8D10020FFF79EFD0FF21F
+:1058F000A03001F099F9A878012806D12978062965
+:1059000003D000210220FEF7E9FF8EE0002000F026
+:1059100019FEF879307301253889F081798931824F
+:10592000BA897282FB89B382388A04950090F0822A
+:10593000357BE08C039510260296019601F088F9DC
+:1059400010B10220FFF767FD202000F0FBFD6CE0A6
+:105950000120FFF760FD68780A21FFF7A2FB64E0F1
+:10596000B888E18C884260D1A4F8268085F8008050
+:105970000FF24C3001F058F90120307200F059F864
+:1059800053E0F878012802D002281DD04DE0B7F886
+:105990000500E084062028700FF24C3001F044F935
+:1059A00086F8088000F045F8E08C01F0DAF930B9AB
+:1059B0000FF25C3001F038F90FF2883001E00FF29D
+:1059C000B43001F031F930E097F80D90787960BB90
+:1059D00029E007EB0800847BC07BFF2821D1072C3E
+:1059E0001FDB07EB0800007C01281AD10FF2C4303E
+:1059F00001F01AF907EB0800407C832811D10FF25F
+:105A0000D43001F011F90120A870F8793070387A9B
+:105A10007070787AB070B87AF070F87A3071387B3C
+:105A20007071641CA044C845D3DB012005B0BDE8FB
+:105A3000F083E08C708106F1080000F0D8BD7C494D
+:105A4000CA8C824202D191F89000704700207047C2
+:105A500080B500F0ECFE062805D0BDE8044000212A
+:105A60000120FEF73BBFBDE8014000F0D2BD70470A
+:105A7000704718B589B00020ADF81A0001F02FFA70
+:105A80006E4C216811F1010F0DD06D4862680170F4
+:105A9000120A0B0A090C8170437061680271C170AF
+:105AA000120A427105E00020FEF778FD08B90FF2F6
+:105AB000DC3002460621002000F00FFD4EF66E504D
+:105AC000089007AA20685A4C079006212E2000F063
+:105AD00004FD0FF2C0321021182000F0FEFC0FF27E
+:105AE000C4321021082000F0F8FC1821012000F039
+:105AF0001BFD01F0EFF80DF1160006A901900091D1
+:105B000005AB07220021042001F059FA0FF2E8202A
+:105B1000BDF8181000900723BDF81400002201F012
+:105B2000F0F80DF11A0000900223BDF81610BDF830
+:105B30001400002201F0E5F80020207001F0F3F9D4
+:105B4000012060700020E070082060751020A075B2
+:105B5000012020753B48A0610120A0700020C1B247
+:105B600021440871401CC1B21029F8DB00200490C8
+:105B70000023A069617803900122207D0290A07D1E
+:105B80000190607D0090A07801F0E6F9A07808B15E
+:105B900001F04DFA0AB010BD254890F89010062982
+:105BA00000D1704780B50020FFF735FC4FF44871F5
+:105BB00001230022084601F055FA10B90FF24020E7
+:105BC00004E00220FFF727FC0FF26420BDE802404A
+:105BD00001F02AB818B587B00FF28420144C01F0F8
+:105BE00023F894F8900006281DD010210691059105
+:105BF0004FF4FA70049050210023029128220020D3
+:105C00000393019200904FF448710B4B0022084619
+:105C100001F04DFA08B9042003E00220FFF7FBFB76
+:105C2000002084F8900008B010BD0000AC8800206F
+:105C3000F011002073620008201700208075FF1FFC
+:105C40007C17002007B201000120FFF7EEBB002106
+:105C50002020FEF743BE0120FEF762BE0120FEF7C2
+:105C600067BE000010B50446616801F1080000F04D
+:105C7000D5FB00B10120207010BD000010B101283B
+:105C800003D070473F20FEF739BE3F20FEF73EBEEF
+:105C90002D2D204741502047454E4552414C204430
+:105CA0004953434F564552592050524F434544554E
+:105CB00052455F434F4D504C455445440A00000047
+:105CC0000D0A0D2A2A20444953434F4E4E45435452
+:105CD000494F4E204556454E54205749544820536D
+:105CE0004552564552200A000D0A0D2A2A20434FDC
+:105CF0004E4E454354494F4E204556454E5420572D
+:105D000049544820534552564552200A000000008D
+:105D10000D0A0D2A2A204741545420534552564912
+:105D2000434553202620434841524143544552495C
+:105D3000535449435320444953434F5645525920E5
+:105D4000200A00002A2047415454203A202053744E
+:105D500061727420536561726368696E6720507266
+:105D6000696D617279205365727669636573200D80
+:105D70000A0D0000424C455F4354524C5F41707025
+:105D80005F4E6F74696669636174696F6E28292C50
+:105D900020416C6C20736572766963657320646959
+:105DA00073636F76657279204661696C6564200D56
+:105DB0000A0D00002D2D2D205354204D414E5546E7
+:105DC00041435455524552204944202D2D2D200A3F
+:105DD000000000002D2D20534552564552204445C9
+:105DE000544543544544202D2D20564941204D41D2
+:105DF0004E2049440A00000053544D3332574200AC
+:105E0000200D0A0D2A2A2053544152542047454E52
+:105E10004552414C20444953434F5645525920283E
+:105E20005343414E29202A2A20200D0A0D0000004C
+:105E30002D2D20424C455F4170705F537461727428
+:105E40005F4C696D697465645F446973635F526533
+:105E5000712C204661696C6564200D0A0D000000FC
+:105E60000D0A0D2A2A2043524541544520434F4EE6
+:105E70004E454354494F4E20544F205345525645AA
+:105E800052202A2A20200D0A0D0000006C7AD8AC7E
+:105E900057720000123456789ABCDEF012345678ED
+:105EA0009ABCDEF0FEDCBA0987654321FEDCBA0944
+:105EB0008765432100000000000000000000000092
+:105EC0000000000000000000440008004005080138
+:105ED0003A799C00F4010000FFFFFFFF4801010038
+:105EE000000000007047704738B5EFF3108472B6B9
+:105EF000284D6946281D01F06AFA6946281D01F0FF
+:105F0000C3FA38B184F31088BDF80010224AFFF7B5
+:105F1000B3F931BD0120287084F3108831BD80B5FC
+:105F2000FFF7A8F90221009100231A4800F124018B
+:105F30004FF48052001D01F031F901BD00BFF8B5EA
+:105F400014460026EFF3108510F1010F1ED0012832
+:105F50001CBF02284FF0FF3618D1BCB1264672B6DE
+:105F60000C4F012392B2381D01F02CF900281CBF00
+:105F70003978002908D000223A7085F31088A1B240
+:105F8000054AFFF779F901E085F310883046F2BD44
+:105F90000000000004000020E95E0008FFF7E9FBB4
+:105FA0009DF80E0005B000BDF8B500F10C026B467F
+:105FB00021214FF66640F1E7F8B500F10C026B467F
+:105FC0000F214FF66840E9E7C0680840884201D1D8
+:105FD0000120704700207047C0690840884201D105
+:105FE000012070470020704710B5664C0221204602
+:105FF000FFF7F2FF38B16068C043810703D5FFF7B0
+:10600000EAFA022018E001212046FFF7E5FF38B147
+:106010006068C043C10703D5FFF7A3FA01200BE076
+:1060200008212046FFF7D8FF38B16068C043010758
+:1060300003D5FFF724FB0820A06010BD10B5514C1C
+:1060400000F033F818B96068C043810306D400F04B
+:106050002CF830B96068C043810302D5BDE8104018
+:106060006EE0082100F022F870B96068C0430103B7
+:106070000AD56068444940F40020606008688047A1
+:106080004FF40020A06010BD202100F00FF858B997
+:106090006068C043810207D5606840F4001060600A
+:1060A000BDE81040FFF770BA10BD022120468BE713
+:1060B0003648016841F4007101603548026842F4D5
+:1060C0000072026040BF20BF3248016841F40041C5
+:1060D0000160704780B53048016841F4801101606B
+:1060E000006800F48010009000982648016841F094
+:1060F00001010160026842F4803202602C20FDF749
+:10610000C6FFBDE802402D20FDF7C1BF234801684E
+:10611000490849000160704721494FF48030086008
+:1061200070471E48016821F00201016070471B485A
+:106130004FF400314160016821F400310160704783
+:106140001648016841F400310160FFF73EBA38B5E6
+:1061500004460C4D08212846FFF736FF30B10A48A7
+:106160000460686820F40020686031BDA0474FF4E7
+:106170000021A96031BD0948016821F008010160D2
+:1061800070470000000C0058BC170020D4080058CD
+:10619000200800580C04005850000058040C005807
+:1061A000080C0058006040607047EFF3108172B631
+:1061B000026882420CBF012000201CE0EFF3108235
+:1061C00072B603680B60486001600868416023E0B4
+:1061D000EFF3108272B6086043684B604160486814
+:1061E000016019E0EFF3108172B6436802681A602B
+:1061F00042680068426081F31088704710B5EFF381
+:10620000108472B602680A600068FFE7FFF7EAFFD1
+:1062100084F3108810BD086082F310887047000076
+:106220000249016002490161704700BF8F550008B3
+:10623000B75500087FB50C466D4D61686D4EE8613D
+:106240002962284601F06AF9246805F12400FFF765
+:10625000A9FF746006F10800FFF7A4FF0120307069
+:10626000296829B10FF255100090029468468847BA
+:106270007FBD1FB55F4C04F10800FFF796FF00BB20
+:106280002178F1B1694604F10800FFF7B7FF5848DB
+:10629000C16949B10098029001228DF8042001A83B
+:1062A00088479DF8040000E001202070207818B194
+:1062B0000098FFF7BAF904E0009904F10800FFF72D
+:1062C0007DFF04F10800FFF770FF28B9207818B1AE
+:1062D00004F10800FFF7BBFC1FBD2DE9F84306469B
+:1062E000002000F05FF874883088B268DFF8008121
+:1062F000C4F3090444EA8024F068A4B2C1B2204681
+:1063000000F03CF8002748F2E8094846FFF7A6FCF1
+:1063100008E06888A04202D131692878087068785E
+:1063200000B1012708F12400FFF73FFFF0B96946EB
+:1063300008F12400FFF762FF009800F10B05407A96
+:106340000F28E6D0B5F80110A1420DD10098817A4E
+:10635000C81E7169C0B28842C8BF08467061024653
+:106360003069E91CFAF7B8FF2878D9E73800CCD0B3
+:10637000012000F017F80020BDE8F28310B51346A5
+:106380001C4A5468A4F80900E1720A46194604F14F
+:106390000C00FAF7A1FF164A1369BDE8104000216E
+:1063A000002018471249096A82B008B921B101E0FA
+:1063B00011B1012002B0084702B0704710B5014684
+:1063C000487A0F2818BF0E2807D10B48FFF700FFA7
+:1063D000BDE810400020FFF73EBC064C04F1080069
+:1063E000FFF7F6FE04F10800BDE81040FFF72FBCF0
+:1063F0008C16002050170020B016002023490020E2
+:10640000087700222248027100F044B820490A7936
+:1064100041F822000879401C0871704770B50446A5
+:106420006078FF2802BFB4F8031001F47F41B1F592
+:10643000406F1FD10025154E317FE8B2884222D22D
+:10644000E9B256F8211020468847002808BF6D1C85
+:10645000F2D018E0761C2979F0B288420AD2F1B263
+:1064600055F82110204688470100F3D002D00228B9
+:1064700005D006E02046BDE87040FFF70DBA0020C9
+:1064800070BD012070BD0026014DE4E7001700201B
+:10649000AC17002080B501F04BF801F04AF801F08C
+:1064A00049F801F048F801F047F801F046F801F02A
+:1064B00045F801F044F801F043F801F042F801F02A
+:1064C00041F801F040F801F03FF801F03EF801F02A
+:1064D0003DF8BDE8014001F03AB818B50C46C7B028
+:1064E000114600228DF800208DF81C008DF81D400B
+:1064F00022460DF11E0001F02BF800F03BF83F2082
+:106500000C21ADF80400ADF8061007A80121039096
+:106510000691A41C049400F043F800284CBFFF200F
+:106520009DF8000048B010BD00B5C7B000F01BF8E2
+:106530000F2000F02AF800284CBFFF209DF8000033
+:1065400047B000BD00B5C7B00021ADF81C0000F099
+:1065500016F8182000F019F800284CBFFF209DF80D
+:10656000000047B000BD00228DF800208DF81C000F
+:106570008DF81D101822002101A800F0EFBF8DF842
+:106580000010182201A800F0E9BFADF8060007A925
+:10659000022004903F22012003910690ADF80420D0
+:1065A000CDF814D0002101A8FFF797BE80B50FF2F7
+:1065B000B92200210420FEF784F90FF2792200218C
+:1065C0000820FEF77EF9CD4800210180C18081704E
+:1065D0000121C1700021017101720FF24100FFF72A
+:1065E00015FFBDE802400FF2243000F01DBB027819
+:1065F000C24912B1012A03D070474088C880704751
+:106600000020C880087A08B100220A720020FEF734
+:106610000CBF00210820FEF761B900002DE9F84FFA
+:1066200005466878FF2812D1B44CB5F8030061899B
+:1066300040F60442801A00F08B80801E4DD0001F6F
+:1066400006D0401F00F0B780401E00F0DD80EBE078
+:10665000B5F80560207A58B10846FFF7F0F9217ABD
+:10666000062908BF0028F2D120724FF6FF70608122
+:106670006681E879297A91FBF0F914285FFA89F9A3
+:10668000E5D14FF0100A00270FF29C284FF6406624
+:10669000F8B24845DBDA05EB0A0B9BF809009BF8DA
+:1066A0000A1040EA0120B04211D16189404600F051
+:1066B000BBFAABF107000178427841EA0221A181DF
+:1066C0008178C07841EA0021E181082121720AF134
+:1066D00006005FFA80FA7F1CDAE7B5F80500814210
+:1066E00002BF1126E87915283CD1297A0FF2AC298E
+:1066F0000FF2702B481E28724FF6426A4FF641681F
+:10670000287A0028A3D0A91905F10A02487A11F8BD
+:10671000057D925D497840EA022047EA01276189B8
+:10672000404508D050450CD1484600F07DFA0A207B
+:106730002072A78205E0584600F076FA0920207200
+:1067400027821536287AA0F115012972F6B2D7E70B
+:10675000B5F80500814201BF95F808B04FF0000878
+:10676000E879012860D100270FF2742942F6021A55
+:10677000F8B2B0EB9B0F57DA05EB080005F10A0100
+:10678000C27A467A007B11F8081042EA002252458C
+:1067900046EA012609D16189484600F045FA207A87
+:1067A0000A2802D1E6820B21217208F104005FFA67
+:1067B00080F87F1CDCE7B5F80500814202BFB5F820
+:1067C0000700A18A88422FD1687A022802BFA87ADE
+:1067D0006070012828D1E87AA07046A448B9FEF775
+:1067E00024FE0FF2742000F01FFA204600F01CFA7D
+:1067F0001AE00FF2A42000F017FA204600F014FA75
+:106800000020FEF708FE0FE00FF21C2000F00CFA4B
+:1068100039A000F009FA6089B5F80510884203D163
+:1068200000210420FEF75AF80020BDE8F28F33481B
+:10683000007A704710B50FF2A020304C00F0F4F948
+:106840002CA000F0F1F92079401E8041C00F20718A
+:10685000207A38B1218A6089E31CBDE81040022209
+:1068600000F0EDBA10BD00001CB50120ADF800002D
+:10687000224C207A00283BD0C01F052838D8DFE8FA
+:1068800000F003081218232F0FF28C2000F0CCF92F
+:1068900013BD0FF29C2000F0C7F9E289A18960893D
+:1068A00000F079FA13BD0FF2B02000F0BDF9218A93
+:1068B00004E00FF2E02000F0B7F9A18A60898A1C99
+:1068C00092B200F079FA13BD0FF20C3000F0ACF97F
+:1068D00000F016F8062020720220FEF7A6FD13BD78
+:1068E0000FF21C3000F0A0F900F00AF80620207228
+:1068F00013BD0000200A0D000A0000003817002018
+:10690000E18A60896B46022200F06CBA2D2D20507E
+:10691000325020434C49454E5420494E4954494138
+:106920004C495A4544200A002D2D204741545420FB
+:106930003A205032505F534552564943455F5555B2
+:10694000494420464F554E44202D20636F6E6E659E
+:106950006374696F6E2068616E646C6520307825A1
+:1069600078200A002D2D2047415454203A205752B8
+:106970004954455F5555494420464F554E44202DB6
+:1069800020636F6E6E656374696F6E2068616E64FC
+:106990006C6520307825780A000000002D2D2047F6
+:1069A000415454203A204E4F54494649434154499A
+:1069B0004F4E5F434841525F5555494420464F551D
+:1069C0004E4420202D20636F6E6E656374696F6E78
+:1069D0002068616E646C6520307825780A000000BC
+:1069E0002D2D2047415454203A20434C49454E54C4
+:1069F0005F434841525F434F4E4649475F444553CA
+:106A000043524950544F525F555549442D20636FAE
+:106A10006E6E656374696F6E2068616E646C65206C
+:106A2000307825780A0000002D2D2047415454204D
+:106A30003A204556545F424C55455F474154545F98
+:106A400050524F4345445552455F434F4D504C457E
+:106A50005445200A00000000202D2D2050325020E7
+:106A60004150504C49434154494F4E20434C4945B5
+:106A70004E54203A204E4F54494649434154494FC1
+:106A80004E205245434549564544202D204C45440F
+:106A9000204F4646200A0D00202D2D205032502038
+:106AA0004150504C49434154494F4E20434C494575
+:106AB0004E54203A204E4F54494649434154494F81
+:106AC0004E205245434549564544202D204C4544CF
+:106AD000204F4E0A0D0000002D2D20503250204135
+:106AE00050504C49434154494F4E20434C49454E28
+:106AF0005420203A20425554544F4E20505553486C
+:106B00004544202D20575249544520544F20534589
+:106B100052564552200A20005032505F4449534398
+:106B20004F5645525F53455256494345530A00005C
+:106B30002A2047415454203A20446973636F766594
+:106B400072205032502043686172616374657269CB
+:106B500073746963730A00002A2047415454203A31
+:106B600020446973636F766572204465736372694C
+:106B700070746F72206F66205458202D20577269F0
+:106B800074652043686172616374657269746963D6
+:106B90000A0000002A2047415454203A20446973D7
+:106BA000636F7665722044657363726970746F7287
+:106BB000206F66205278202D204E6F7469666963BD
+:106BC0006174696F6E204368617261637465726994
+:106BD0007469630A000000002A2047415454203A97
+:106BE00020456E61626C6520536572766572204E39
+:106BF0006F74696669636174696F6E0A00000000F2
+:106C00002A2047415454203A2044697361626C65DC
+:106C100020536572766572204E6F74696669636190
+:106C200074696F6E0A0000000EB4C0B5024603A876
+:106C300000210190009101AB0121044878440C30FF
+:106C4000F9F77CFA06BC5DF810FB00BFAF1100003D
+:106C50002DE9F841C7B04FF00008ADF81C00DDF891
+:106C600038C14F9E509F519D529C8DF8008007A8BF
+:106C70004180ADF82020ADF82230A0F808C0ADF872
+:106C8000266087818DF82A508DF82B4000F015F88A
+:106C90004FF4C170ADF8060007A9102004903F2200
+:106CA00001200391069000F00DF800284CBFFF2052
+:106CB0009DF8000048B0BDE8F0811822002101A82D
+:106CC00000F04CBCADF80420CDF814D0002101A890
+:106CD000FFF703BB00B587B000208DF8000000F07F
+:106CE0007CF840F20110ADF806003F22012006902A
+:106CF00000F0EDF800284CBFFF209DF8000007B021
+:106D000000BD30B5C7B01C464A9B00F0C7F800254F
+:106D10008DF800508DF82140224619460DF12200D1
+:106D200000F016FC00F059F83F204FF4837100F09A
+:106D3000BCF8A41D049400F0CCF800284CBFFF2040
+:106D40009DF8000047B030BD0023ADF81C008DF861
+:106D5000003007A8418082800021182201A800F09D
+:106D6000FDBB00B5C7B000F010F8FFF7F6FF0F212C
+:106D700002914FF48970022100F0A1F800284CBF65
+:106D8000FF209DF8000047B000BD0021ADF81C00B9
+:106D90008DF80010704700B5C7B0FFF7D5FF0F2181
+:106DA000029140F2151000F089F800284CBFFF2036
+:106DB0009DF8000047B000BD00B5C7B0FFF7C4FFA5
+:106DC0000F21029140F2171000F078F800284CBF14
+:106DD000FF209DF8000047B000BD1822002101A847
+:106DE00000F0BCBB18B5C7B000F011F800F045F8D2
+:106DF000FFF7F3FF40F2211100F013F800F069F8FB
+:106E000000284CBFFF209DF8000048B010BD14467C
+:106E1000ADF81C00002207A88DF800204180047105
+:106E20007047ADF806103F2007A9ADF804000391A4
+:106E30000F20012102900691641D0494704718B53B
+:106E4000C7B000F010F8FFF7C8FF3F2040F2231151
+:106E500000F019F800F03DF800284CBFFF209DF825
+:106E6000000048B010BD144600228DF80020ADF897
+:106E70001C00ADF81E108DF82040224619460DF179
+:106E8000210000F065BBADF80400ADF8061007A8BE
+:106E9000012103900691641D04947047ADF81C0015
+:106EA000ADF81E108DF820207047ADF80400ADF845
+:106EB000061007A801210390069170470621ADF83E
+:106EC0000600049107A801213F2203900691ADF826
+:106ED0000420CDF814D0002101A8FFF7FEB900B5B9
+:106EE00087B000F010F8012003220690ADF80420CE
+:106EF000ADF8062000F011F800284CBFFF209DF8E7
+:106F0000000007B000BD00208DF80000182200210D
+:106F100001A800F023BB03900691CDF814D0002106
+:106F200001A8FFF7DAB900B5C7B000F00CF885206A
+:106F300000F075F800F014F900284CBFFF209DF810
+:106F4000000047B000BD00218DF81C008DF8001036
+:106F5000182201A800F002BB2DE9F841C7B04FF09C
+:106F6000000800F026F80DF12300DDF844E14E9F03
+:106F70004F9E509D529C8DF81F30C0F800E08DF858
+:106F800000808DF820708DF821608DF822508DF8EA
+:106F9000274000F087F88620ADF8060007A90C20EE
+:106FA00000F0DAF800284CBFFF209DF8000000F048
+:106FB000F2B88DF81C0007A8417082707047F8B5D0
+:106FC000C8B005460E4617461C4600F023F808A830
+:106FD000467087708DF8205000F0D8F88A21ADF8FF
+:106FE0000A103F20032100F0C4F8002848BFFF200A
+:106FF0000ED49DF8000058B94F994E98BDF8012065
+:107000002280BDF803200280BDF805000880002022
+:1070100049B0F0BD07220021684600F09FBAADF8E4
+:10702000060007A901203F2203910490704700B594
+:1070300087B000F013F800F035F8922000F009F85E
+:1070400000F08EF800284CBFFF209DF8000007B02C
+:1070500000BDADF806003F220120704700208DF8EA
+:107060000000704718B5C7B000F011F800F01AF82A
+:107070000F2102919720062100F065F800F071F8C9
+:1070800000284CBFFF209DF8000048B010BD002430
+:10709000ADF81C008DF8213007A8418002718DF8F1
+:1070A000004070471822002101A800F057BA2DE9CE
+:1070B000F04F0646C7B000F020F800F012F8FFF7D6
+:1070C000F1FF3F20ADF804009C2100F030F800F003
+:1070D0004AF800284CBFFF209DF8000047B0BDE8EB
+:1070E000F08F8DF82790B581ADF82AB03782ADF8D2
+:1070F0002E80B482ADF832A0704708461946559CE0
+:10710000DDF84091519DDDF848B1539FDDF8508185
+:10711000DDF858A1ADF81C60002307AE8DF80030F3
+:10712000708032710DF12100062200F011BA0F209B
+:107130000290ADF806101820049007A901200391D1
+:10714000069070470321ADF80600049107A80121BD
+:107150003F2203900691704704903F220120039143
+:107160000690ADF80420CDF814D0002101A8FFF757
+:10717000B4B8ADF80800059108A80721049007915C
+:10718000CDF818D0002102A8FFF7A7B818220021D7
+:1071900002A800F0E3B948B0BDE8F08110B5029C48
+:1071A000016042600021C160016141618161038130
+:1071B000A107047704D5008910B14FF0FF3010BD4E
+:1071C000002010BD2DE9F04F064685B030890C46F1
+:1071D0000027BB4600287169DC460CBF4FF002084F
+:1071E000D84681B168B930697768451CBD4228BF6F
+:1071F000ED1B3768385C7D5D00EB0527BF1CBFB217
+:1072000003E0074600E000B102463069F568A84295
+:1072100023BF7568281AC01B0020154608EB050916
+:1072200003FB09FE864532BF0020B0FBF9FA09FBDB
+:107230001A00C0B2804509DA96F81C905FEAC97A54
+:1072400048BF84465FEA897048BFC446100000F01A
+:10725000B4807068714461448842C0F0AE8008EB2D
+:10726000020080B20390D946100AADF802000294E1
+:10727000ADF80020049359E0800740D530890028FC
+:1072800040F09B803268D018A34600F8024C200AD8
+:1072900032681A4402F8010C224630681844FAF7A2
+:1072A0001BF8706920187061B069019C401CB061C6
+:1072B000200A31680C70316848701CE08CB3307F54
+:1072C000C207D9D5308940B931681944FF2001F887
+:1072D000020C3168194401F8010C4FF0000B706981
+:1072E000241874612C463089002340B931680C7031
+:1072F000210A3068417002237069801C706108EBBC
+:1073000004070021BFB231615CB1DA44029800EB9E
+:107310000A01306822461844F9F7DEFF7069241824
+:10732000746109F10109B069401CB061049A706888
+:107330003169914545D2791881422CBF081A084617
+:10734000306103463089A0B93068BDF80010C154DF
+:107350005B1C70683168834228BF1B1ABDF80200AD
+:10736000C8545B1C7068834228BF1B1A7069801C5C
+:10737000706105FB09FA7468BDF80000E41A8442E4
+:1073800088BF0446029800EB0A01281BAC4201901A
+:1073900003D093D2307F002890D137682246F81866
+:1073A000F9F79AFF706920187061A346019C039F4A
+:1073B0000023A9E73068404400E0002005B0BDE8A4
+:1073C000F08F88448045F5D3A8EB0008F2E778B544
+:1073D000028900230B80002A44690CBF0225002586
+:1073E000002C4FD0028952B9C2684668531CB34280
+:1073F00028BF9B1B0668B25CF35C02EB03220A8089
+:10740000027F02F00302012A25D10B884FF6FF729A
+:10741000934204BF0289002A09D0C36802699A42D4
+:1074200019D20289BAB14668F31A934213D243685B
+:10743000C268E41A14190022C260446102894AB980
+:1074400002681478012B94BFC3F101030123D25CBD
+:1074500004EB02220A80C468426806682B19934232
+:1074600028BF9B1A33440E884169891B491B41611F
+:1074700005D034192D19954228BFAD1AC560816910
+:10748000491E8161184672BDF8B5028900230B8040
+:10749000002A42690CBF02240024002A3BD0C568A0
+:1074A00002892B464AB946686A1CB24228BF921B21
+:1074B0000668775DB25C07EB02220A80067F06F061
+:1074C0000306012E20D10F884FF6FF72974204BFAA
+:1074D0000289002A07D142680023012A94BFC2F121
+:1074E000010201220AE00269AA420DD202895AB1C0
+:1074F0004668751B954207D2002304E005682E7884
+:10750000AA5C06EB02220A8041680068E4188C42FB
+:1075100028BF641A03191846F2BD00000249016031
+:1075200002490161704700BF255500084F5500080A
+:107530007047704770477047704770477047704793
+:107540007047704770477047704770477047704783
+:1075500010B50446F9F7C0FE204610BD10B504462C
+:1075600010460A460146204600F002F8204610BDAB
+:1075700062F30F2262F31F42401810F0030308D099
+:10758000C91A1FD3DB0748BF00F8012D28BF20F818
+:10759000022D130030B414461546103928BF20E9D7
+:1075A0003C00FAD8490728BF20E90C0048BF40F842
+:1075B000042D890028BF20F8022D48BF00F8012DB6
+:1075C00030BC7047C91818BF00F8012DCB0728BF81
+:1075D00000F8012D7047000010B50446AFF300809D
+:1075E000204600F005F80446AFF30080204610BDA9
+:1075F0007CB500F10F06F608F600B04240D2082E26
+:1076000004D2082602E0083000F047F8DFF8045101
+:107610002C68210005D1002007E00268B24221D287
+:10762000011D08680028F8D12068291D0A688242D7
+:1076300022D01368B34238BF111DF7D312E093195B
+:107640000B60801B54685C600B68186016600968EA
+:1076500000291DBF48680028081D0020286002F18D
+:10766000080076BD61B10A681068A0F10803B34252
+:10767000E5D250680860EAE700F04EF80028C2D171
+:10768000002076BD10B5040006D0AFF30080204680
+:1076900000F003F8AFF3008010BD002800D1704760
+:1076A00050B4A0F108021368072B2BD913F0070F71
+:1076B00028D1184C616809B18A4202D251606260D7
+:1076C00013E0486800B3904238BF0146F9D31BE08D
+:1076D000964203D11B180B600A4606E0486810B1B9
+:1076E000134498420ED350604A60506850B11368FA
+:1076F000D118814206D1002121600168CB181360A6
+:107700004068506050BC704708680E18B242DFD223
+:1077100050BC7047A41700200749086808B1002032
+:1077200070470648C008C00008600549C908C9007C
+:10773000091A0160704700BFC8170020D727002032
+:10774000D02B00202DE9F04107468846387810F00C
+:10775000030F16461D4633D0384600F099F878BB23
+:10776000B8F1000F1CBFD8E900018619012D2ED1F8
+:107770003888C10415D5396A07F14402384600F04B
+:10778000A3F83A6B044602B93A69F968384600F042
+:107790009BF8361B341A7A69F968384600F094F879
+:1077A000261A1EB94DB916F1010F09D097F9030039
+:1077B0002A46314600F08EF8064616F1010F09D12F
+:1077C0002320AFF300804FF0FF30BDE8F081022DA1
+:1077D000E8D1EBE7388810F4405F0ED07868F860A5
+:1077E00038617861B8617868F86107F144003862FF
+:1077F00007F13000786200203863B8F1000F05D03F
+:10780000D8E9020107F13402C2E9000139884CF6D7
+:10781000FF60014039800020BDE8F08170B5054669
+:10782000AFF300802888810415D56E680024EA68CB
+:1078300095F903003146914212D2521AFEF77EFBAF
+:1078400010F1010F1CBF00283618F0D10FE04DF6E3
+:10785000FF70014029802846AFF30080002070BDF2
+:1078600000220021FEF76AFB10F1010F00D1012474
+:107870006868E860A861E861002C2988E7D041F4D5
+:10788000007129802846AFF300804FF0FF3070BDB3
+:10789000F8B5A0B9AFF3008000250A4E08244FF0D8
+:1078A000FF37306820B1FFF7B9FF002848BF3D46D9
+:1078B000361D641EF5D1AFF300802846F2BDBDE849
+:1078C000F240ABE7D0110020914234BF511A0021A1
+:1078D000084670473EB504000D00012A02D100F0B1
+:1078E00063F807E0022A07D100940020019069465E
+:1078F0000C20ABBE2D1801E0002A0CD1009401959C
+:1079000069460A20ABBE002805D1002221002800CC
+:1079100000F027F801E00020C04303B030BD0000B4
+:1079200010B4314A002113461C6884421EBF491C12
+:107930009C6884421EBF491C1C69844209D09C6912
+:10794000491C844205D0491C20331029ECD310BCBB
+:107950007047002342F8313002EBC1014B6010BC8C
+:10796000704778B4204C002325462E688E421EBFF7
+:107970005B1CAE688E421EBF5B1C2E698E4209D016
+:10798000AE695B1C8E4205D05B1C2035102BECD3FE
+:1079900072BC7047054604EBC303012A04BF596853
+:1079A0004D195D6072BC704710B40F4A0021134638
+:1079B0001C6884421EBF491C9C6884421EBF491C2F
+:1079C0001C6984420AD09C69491C844206D0491C27
+:1079D00020331029ECD310BC0020704702EBC1000B
+:1079E000406810BC70470000AC14002010B504467D
+:1079F000E068A169884251D3218849F202030B4013
+:107A0000022B08D008044CBF4FF400704FF48440A0
+:107A1000014321803BE001F4C042B2F5C04F06D1E2
+:107A2000A168884203D32046FFF732FF78BB208845
+:107A300010F4406F02BF606804F14401884217D11E
+:107A40004FF40070FFF7C8FD606030B904F14400E6
+:107A50006060E060401CA0600AE0218841F04001C5
+:107A60002180E060606100F500726068A260E06102
+:107A700060682061A068A061207841070AD50222D1
+:107A80000021204600F00CF810F1010F02D14FF058
+:107A9000FF3010BD208840F4C0402080002010BD81
+:107AA00070B504460D461646AFF3008033462A46AD
+:107AB00000212046FFF746FE05462046AFF3008032
+:107AC000284670BD38B504000ED0207810F0030FA2
+:107AD00003D094F90300002809D5AFF300802046B5
+:107AE00000F030F8AFF300804FF0FF3032BD204699
+:107AF000FFF7CEFE0546AFF300802078410644BF75
+:107B0000606800F05DF80020606094F903000228CE
+:107B100004D900F057F808B14FF0FF35E06B48B1D9
+:107B200000F05CF808B14FF0FF35E06B00F048F86A
+:107B30000020E063204600F005F8AFF300802846FF
+:107B400032BD000001780A0626D51C4A13680021C0
+:107B5000834203D1002342F821301BE05368012106
+:107B600083421EBF022193688342F3D0D36803216E
+:107B700083421EBF042113698342EBD05369052160
+:107B800083421EBF0621936983421EBF0721D3692A
+:107B90008342DFD000F014B8002101804FF0FF31A4
+:107BA000C17000F144014160C160016141618161C6
+:107BB000C161016200F1300141627047D0110020C3
+:107BC000FFF760BD1CB50200009269460220ABBE03
+:107BD00004001000FFF7A4FE200016BDE0B50090E1
+:107BE000F9F72CFB019069460E20ABBE03B000BD37
+:107BF00038B50C46C5B22046AFF30080E068A169F5
+:107C0000884204D32046FFF7F1FE00280FD4E06835
+:107C1000401CE06000F8015D2088010503D44005A8
+:107C20000BD50A2D09D12046FFF732FE28B1204698
+:107C3000AFF300804FF0FF3032BD2046AFF300803D
+:107C4000284632BD7047FEE7FEE7FEE7FEE77047D5
+:107C50007047704700F01EB80548FBF757BA054853
+:107C6000FAF7B7B90448FAF7B4B90448FBF74EBAC3
+:107C70002C150020A0130020141300208C150020C8
+:107C80000120FCF720BB7047FDF7C9B8FEF7D6B955
+:107C9000FEF7AAB902490A68886882180A60704724
+:107CA0006810002019E050F8042BD30744BFA9F155
+:107CB00001039A18091F0023042942F8043BF9D252
+:107CC0005FEA817C134604D54FF0000CA2F800C097
+:107CD0009B1CC90744BF0021197050F8041B0029E0
+:107CE000E1D1704738B50D4D0824286800281CBF25
+:107CF000017811F0030F05D090F90310002958BF47
+:107D0000FFF7E0FE2D1D641EEFD1BDE838400022D4
+:107D100000214FF0FF30FEF711B900BFD011002055
+:107D200010B5074979441831064C7C44163404E0F8
+:107D30000A68081D114488470146A142F8D110BDC8
+:107D40002C000000600000004EF68851CEF20001C9
+:107D5000086840F470000860BFF34F8FBFF36F8F67
+:107D60004FF00070E1EE100A7047000039FFFFFF8E
+:107D7000E0050000F0110020800800002C800020A9
+:107D8000000000004F93FFFF880100009A010000EF
+:107D9000040000203F93FFFF4502000006000000A2
+:107DA000248000200000000000000000000000000F
+:107DB00000000000010000000200000003000000BD
+:107DC0000400000000F00DF8002801D0FFF7A8FF24
+:107DD000AFF300800020AFF30080FBF798FF00F0C6
+:107DE00002F80120704700F001B800000746FFF7D5
+:107DF00079FF3846FAF754F8FBE738B504460D46E4
+:107E0000284600F005F8A84218BF0024204632BDDD
+:107E10000149FFF7EDBE00BF401100200148804737
+:107E2000014800474D4300082D7E0008AFF3008055
+:107E3000FFF78AFFFFF7C6FF00002E004300FFF7A1
+:107E4000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF766
+:107E5000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF756
+:107E6000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF746
+:107E7000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF736
+:107E8000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF726
+:107E9000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF716
+:107EA000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF706
+:107EB000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF7F6
+:107EC000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF7E6
+:107ED000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF7D6
+:107EE000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF7C6
+:107EF000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF7B6
+:107F0000FEBFFFF7FEBFFFF7FEBFFFF7FEBF00009B
+:107F1000F3FF010001F1FF01F1FF01F1FF01F1FFAA
+:107F200001F1FF01F1FF01F1FF01F1FF01F1FF019B
+:107F3000F1FF01F1FF01F1FF01F1FF01F1FF01F19B
+:107F40002201700104004804120004521008F102DA
+:107F50000152FF01E11C1210113D6C10F0050709E0
+:107F60003D00387E0008046140F2003A1410010020
+:107F7000003C0C2144FC021778100020B7102002AE
+:107F8000ED1100082C43DB113C21011301044C10BE
+:107F9000021100203D04523C04211BA108F31128CA
+:107FA00011641007020401013C1600208C04523CAD
+:107FB0000431405108128444F2137048400308020F
+:107FC00002EC1540210821042134610812CC44F24E
+:107FD00012B84816F818124028F206882C520001F0
+:0400000508007E2D44
+:00000001FF
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/app_common.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/app_common.h
new file mode 100644
index 000000000..4defc5d7a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/app_common.h
@@ -0,0 +1,114 @@
+/**
+ ******************************************************************************
+  * File Name          : app_common.h
+  * Description        : App Common application configuration file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_COMMON_H
+#define APP_COMMON_H
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "app_conf.h"
+
+  /* -------------------------------- *
+   *  Basic definitions               *
+   * -------------------------------- */
+
+#undef NULL
+#define NULL                    0
+
+#undef FALSE
+#define FALSE                   0
+
+#undef TRUE
+#define TRUE                    (!0)
+
+  /* -------------------------------- *
+   *  Critical Section definition     *
+   * -------------------------------- */
+#define BACKUP_PRIMASK()    uint32_t primask_bit= __get_PRIMASK()
+#define DISABLE_IRQ()       __disable_irq()
+#define RESTORE_PRIMASK()   __set_PRIMASK(primask_bit)
+
+  /* -------------------------------- *
+   *  Macro delimiters                *
+   * -------------------------------- */
+
+#define M_BEGIN     do {
+
+#define M_END       } while(0)
+
+  /* -------------------------------- *
+   *  Some useful macro definitions   *
+   * -------------------------------- */
+
+#define MAX( x, y )          (((x)>(y))?(x):(y))
+
+#define MIN( x, y )          (((x)<(y))?(x):(y))
+
+#define MODINC( a, m )       M_BEGIN  (a)++;  if ((a)>=(m)) (a)=0;  M_END
+
+#define MODDEC( a, m )       M_BEGIN  if ((a)==0) (a)=(m);  (a)--;  M_END
+
+#define MODADD( a, b, m )    M_BEGIN  (a)+=(b);  if ((a)>=(m)) (a)-=(m);  M_END
+
+#define MODSUB( a, b, m )    MODADD( a, (m)-(b), m )
+
+#define PAUSE( t )           M_BEGIN \
+                               __IO int _i; \
+                               for ( _i = t; _i > 0; _i -- ); \
+                             M_END
+
+#define DIVF( x, y )         ((x)/(y))
+
+#define DIVC( x, y )         (((x)+(y)-1)/(y))
+
+#define DIVR( x, y )         (((x)+((y)/2))/(y))
+
+#define SHRR( x, n )         ((((x)>>((n)-1))+1)>>1)
+
+#define BITN( w, n )         (((w)[(n)/32] >> ((n)%32)) & 1)
+
+#define BITNSET( w, n, b )   M_BEGIN (w)[(n)/32] |= ((U32)(b))<<((n)%32); M_END
+
+  /* -------------------------------- *
+   *  Compiler                         *
+   * -------------------------------- */
+#define PLACE_IN_SECTION( __x__ )  __attribute__((section (__x__)))
+
+#ifdef WIN32
+#define ALIGN(n)
+#else
+#define ALIGN(n)             __attribute__((aligned(n)))
+#endif
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*APP_COMMON_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/app_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/app_conf.h
new file mode 100644
index 000000000..e45f97788
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/app_conf.h
@@ -0,0 +1,523 @@
+/**
+ ******************************************************************************
+  * File Name          : app_conf.h
+  * Description        : Application configuration file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_CONF_H
+#define APP_CONF_H
+
+#include "hw.h"
+#include "hw_conf.h"
+#include "hw_if.h"
+
+/******************************************************************************
+ * Application Config
+ ******************************************************************************/
+
+/**< generic parameters ******************************************************/
+
+/**
+ * Define Tx Power
+ */   
+#define CFG_TX_POWER                      (0x18) /**< 0dbm */
+
+/**
+ * Define Advertising parameters
+ */
+#define CFG_ADV_BD_ADDRESS                (0x7257acd87a6c)
+
+/**
+ * Define IO Authentication
+ */
+#define CFG_BONDING_MODE                  (1)
+#define CFG_FIXED_PIN                     (111111)
+#define CFG_USED_FIXED_PIN                (0)
+#define CFG_ENCRYPTION_KEY_SIZE_MAX       (16)
+#define CFG_ENCRYPTION_KEY_SIZE_MIN       (8)
+
+/**
+ * Define IO capabilities
+ */
+#define CFG_IO_CAPABILITY_DISPLAY_ONLY       (0x00)
+#define CFG_IO_CAPABILITY_DISPLAY_YES_NO     (0x01)
+#define CFG_IO_CAPABILITY_KEYBOARD_ONLY      (0x02)
+#define CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT (0x03)
+#define CFG_IO_CAPABILITY_KEYBOARD_DISPLAY   (0x04)
+
+#define CFG_IO_CAPABILITY             CFG_IO_CAPABILITY_DISPLAY_ONLY
+
+/**
+ * Define MITM modes
+ */
+#define CFG_MITM_PROTECTION_NOT_REQUIRED      (0x00)
+#define CFG_MITM_PROTECTION_REQUIRED          (0x01)
+
+#define CFG_MITM_PROTECTION             CFG_MITM_PROTECTION_REQUIRED
+
+/**
+*   Identity root key used to derive LTK and CSRK
+*/
+#define CFG_BLE_IRK     {0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0,0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0}
+
+/**
+* Encryption root key used to derive LTK and CSRK
+*/
+#define CFG_BLE_ERK     {0xfe,0xdc,0xba,0x09,0x87,0x65,0x43,0x21,0xfe,0xdc,0xba,0x09,0x87,0x65,0x43,0x21}
+
+/* USER CODE BEGIN Generic_Parameters */
+/**
+ * SMPS supply
+ * SMPS not used when Set to 0
+ * SMPS used when Set to 1
+ */
+#define CFG_USE_SMPS    1
+/* USER CODE END Generic_Parameters */
+
+/**< specific parameters */
+/*****************************************************/
+#define CFG_MAX_CONNECTION                      1
+#define UUID_128BIT_FORMAT                      1
+#define CFG_DEV_ID_P2P_SERVER1                  (0x83)
+#define CONN_L(x) ((int)((x)/0.625f))
+#define CONN_P(x) ((int)((x)/1.25f))
+#define SCAN_P (0x320)
+#define SCAN_L (0x320)
+#define CONN_P1   (CONN_P(50))
+#define CONN_P2   (CONN_P(100))
+#define SUPERV_TIMEOUT (0x1F4)
+#define CONN_L1   (CONN_L(10))
+#define CONN_L2   (CONN_L(10))
+#define OOB_DEMO                                1   /* Out Of Box Demo */  
+
+/******************************************************************************
+ * BLE Stack
+ ******************************************************************************/
+/**
+ * Maximum number of simultaneous connections that the device will support.
+ * Valid values are from 1 to 8
+ */
+#define CFG_BLE_NUM_LINK            8
+
+/**
+ * Maximum number of Services that can be stored in the GATT database.
+ * Note that the GAP and GATT services are automatically added so this parameter should be 2 plus the number of user services
+ */
+#define CFG_BLE_NUM_GATT_SERVICES   8
+
+/**
+ * Maximum number of Attributes
+ * (i.e. the number of characteristic + the number of characteristic values + the number of descriptors, excluding the services)
+ * that can be stored in the GATT database.
+ * Note that certain characteristics and relative descriptors are added automatically during device initialization
+ * so this parameters should be 9 plus the number of user Attributes
+ */
+#define CFG_BLE_NUM_GATT_ATTRIBUTES 68
+
+/**
+ * Maximum supported ATT_MTU size
+ */
+#define CFG_BLE_MAX_ATT_MTU             (156)
+
+/**
+ * Size of the storage area for Attribute values
+ *  This value depends on the number of attributes used by application. In particular the sum of the following quantities (in octets) should be made for each attribute:
+ *  - attribute value length
+ *  - 5, if UUID is 16 bit; 19, if UUID is 128 bit
+ *  - 2, if server configuration descriptor is used
+ *  - 2*DTM_NUM_LINK, if client configuration descriptor is used
+ *  - 2, if extended properties is used
+ *  The total amount of memory needed is the sum of the above quantities for each attribute.
+ */
+#define CFG_BLE_ATT_VALUE_ARRAY_SIZE    (1344)
+
+/**
+ * Prepare Write List size in terms of number of packet with ATT_MTU=23 bytes
+ */
+#define CFG_BLE_PREPARE_WRITE_LIST_SIZE         ( 0x3A )
+
+/**
+ * Number of allocated memory blocks
+ */
+#define CFG_BLE_MBLOCK_COUNT            ( 0x79 )
+
+/**
+ * Enable or disable the Extended Packet length feature. Valid values are 0 or 1.
+ */
+#define CFG_BLE_DATA_LENGTH_EXTENSION   1
+
+/**
+ * Sleep clock accuracy in Slave mode (ppm value)
+ */
+#define CFG_BLE_SLAVE_SCA   500
+
+/**
+ * Sleep clock accuracy in Master mode
+ * 0 : 251 ppm to 500 ppm
+ * 1 : 151 ppm to 250 ppm
+ * 2 : 101 ppm to 150 ppm
+ * 3 : 76 ppm to 100 ppm
+ * 4 : 51 ppm to 75 ppm
+ * 5 : 31 ppm to 50 ppm
+ * 6 : 21 ppm to 30 ppm
+ * 7 : 0 ppm to 20 ppm
+ */
+#define CFG_BLE_MASTER_SCA   0
+
+/**
+ *  Source for the 32 kHz slow speed clock
+ *  1 : internal RO
+ *  0 : external crystal ( no calibration )
+ */
+#define CFG_BLE_LSE_SOURCE  0
+
+/**
+ * Start up time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us)
+ */
+#define CFG_BLE_HSE_STARTUP_TIME  0x148
+
+/**
+ * Maximum duration of the connection event when the device is in Slave mode in units of 625/256 us (~2.44 us)
+ */
+#define CFG_BLE_MAX_CONN_EVENT_LENGTH  ( 0xFFFFFFFF )
+
+/**
+ * Viterbi Mode
+ * 1 : enabled
+ * 0 : disabled
+ */
+#define CFG_BLE_VITERBI_MODE  1
+
+/**
+ *  LL Only Mode
+ *  1 : LL Only
+ *  0 : LL + Host
+ */
+#define CFG_BLE_LL_ONLY  0
+/******************************************************************************
+ * Transport Layer
+ ******************************************************************************/
+/**
+ * Queue length of BLE Event
+ * This parameter defines the number of asynchronous events that can be stored in the HCI layer before
+ * being reported to the application. When a command is sent to the BLE core coprocessor, the HCI layer
+ * is waiting for the event with the Num_HCI_Command_Packets set to 1. The receive queue shall be large
+ * enough to store all asynchronous events received in between.
+ * When CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE is set to 27, this allow to store three 255 bytes long asynchronous events
+ * between the HCI command and its event.
+ * This parameter depends on the value given to CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE. When the queue size is to small,
+ * the system may hang if the queue is full with asynchronous events and the HCI layer is still waiting
+ * for a CC/CS event, In that case, the notification TL_BLE_HCI_ToNot() is called to indicate
+ * to the application a HCI command did not receive its command event within 30s (Default HCI Timeout).
+ */
+#define CFG_TLBLE_EVT_QUEUE_LENGTH 5
+/**
+ * This parameter should be set to fit most events received by the HCI layer. It defines the buffer size of each element
+ * allocated in the queue of received events and can be used to optimize the amount of RAM allocated by the Memory Manager.
+ * It should not exceed 255 which is the maximum HCI packet payload size (a greater value is a lost of memory as it will
+ * never be used)
+ * It shall be at least 4 to receive the command status event in one frame.
+ * The default value is set to 27 to allow receiving an event of MTU size in a single buffer. This value maybe reduced
+ * further depending on the application.
+ *
+ */
+#define CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE 255   /**< Set to 255 with the memory manager and the mailbox */
+
+#define TL_BLE_EVENT_FRAME_SIZE ( TL_EVT_HDR_SIZE + CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE )
+/******************************************************************************
+ * UART interfaces
+ ******************************************************************************/
+
+/**
+ * Select UART interfaces
+ */
+#define CFG_DEBUG_TRACE_UART    hw_uart1
+#define CFG_CONSOLE_MENU      
+/******************************************************************************
+ * USB interface
+ ******************************************************************************/
+
+/**
+ * Enable/Disable USB interface
+ */
+#define CFG_USB_INTERFACE_ENABLE    0
+
+/******************************************************************************
+ * Low Power
+ ******************************************************************************/
+/**
+ *  When set to 1, the low power mode is enable
+ *  When set to 0, the device stays in RUN mode
+ */
+#define CFG_LPM_SUPPORTED    1
+
+/******************************************************************************
+ * Timer Server
+ ******************************************************************************/
+/**
+ *  CFG_RTC_WUCKSEL_DIVIDER:  This sets the RTCCLK divider to the wakeup timer.
+ *  The higher is the value, the better is the power consumption and the accuracy of the timerserver
+ *  The lower is the value, the finest is the granularity
+ *
+ *  CFG_RTC_ASYNCH_PRESCALER: This sets the asynchronous prescaler of the RTC. It should as high as possible ( to ouput
+ *  clock as low as possible) but the output clock should be equal or higher frequency compare to the clock feeding
+ *  the wakeup timer. A lower clock speed would impact the accuracy of the timer server.
+ *
+ *  CFG_RTC_SYNCH_PRESCALER: This sets the synchronous prescaler of the RTC.
+ *  When the 1Hz calendar clock is required, it shall be sets according to other settings
+ *  When the 1Hz calendar clock is not needed, CFG_RTC_SYNCH_PRESCALER should be set to 0x7FFF (MAX VALUE)
+ *
+ *  CFG_RTCCLK_DIVIDER_CONF:
+ *  Shall be set to either 0,2,4,8,16
+ *  When set to either 2,4,8,16, the 1Hhz calendar is supported
+ *  When set to 0, the user sets its own configuration
+ *
+ *  The following settings are computed with LSI as input to the RTC
+ */
+#define CFG_RTCCLK_DIVIDER_CONF 0
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 0)
+/**
+ * Custom configuration
+ * It does not support 1Hz calendar
+ * It divides the RTC CLK by 16
+ */
+#define CFG_RTCCLK_DIV  (16)
+#define CFG_RTC_WUCKSEL_DIVIDER (0)
+#define CFG_RTC_ASYNCH_PRESCALER (CFG_RTCCLK_DIV - 1)
+#define CFG_RTC_SYNCH_PRESCALER (0x7FFF)
+
+#else
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 2)
+/**
+ * It divides the RTC CLK by 2
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (3)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 4)
+/**
+ * It divides the RTC CLK by 4
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (2)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 8)
+/**
+ * It divides the RTC CLK by 8
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (1)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 16)
+/**
+ * It divides the RTC CLK by 16
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (0)
+#endif
+
+#define CFG_RTCCLK_DIV              CFG_RTCCLK_DIVIDER_CONF
+#define CFG_RTC_ASYNCH_PRESCALER    (CFG_RTCCLK_DIV - 1)
+#define CFG_RTC_SYNCH_PRESCALER     (DIVR( LSE_VALUE, (CFG_RTC_ASYNCH_PRESCALER+1) ) - 1 )
+
+#endif
+
+/** tick timer value in us */
+#define CFG_TS_TICK_VAL           DIVR( (CFG_RTCCLK_DIV * 1000000), LSE_VALUE )
+
+typedef enum
+{
+    CFG_TIM_PROC_ID_ISR,
+} CFG_TimProcID_t;
+
+/******************************************************************************
+ * Debug
+ ******************************************************************************/
+/**
+ * When set, this resets some hw resources to set the device in the same state than the power up
+ * The FW resets only register that may prevent the FW to run properly
+ *
+ * This shall be set to 0 in a final product
+ *
+ */
+#define CFG_HW_RESET_BY_FW         1
+
+/**
+ * keep debugger enabled while in any low power mode when set to 1
+ * should be set to 0 in production
+ */
+#define CFG_DEBUGGER_SUPPORTED    1
+
+/**
+ * When set to 1, the traces are enabled in the BLE services
+ */
+#define CFG_DEBUG_BLE_TRACE     1
+
+/**
+ * Enable or Disable traces in application
+ */
+#define CFG_DEBUG_APP_TRACE     1
+
+#if (CFG_DEBUG_APP_TRACE != 0)
+#define APP_DBG_MSG                 PRINT_MESG_DBG
+#else
+#define APP_DBG_MSG                 PRINT_NO_MESG
+#endif
+
+#if ( (CFG_DEBUG_BLE_TRACE != 0) || (CFG_DEBUG_APP_TRACE != 0) )
+#define CFG_DEBUG_TRACE             1
+#endif
+
+#if (CFG_DEBUG_TRACE != 0)
+#undef CFG_LPM_SUPPORTED
+#undef CFG_DEBUGGER_SUPPORTED
+#define CFG_LPM_SUPPORTED         0
+#define CFG_DEBUGGER_SUPPORTED      1
+#endif
+/**
+ * When CFG_DEBUG_TRACE_FULL is set to 1, the trace are output with the API name, the file name and the line number
+ * When CFG_DEBUG_TRACE_LIGHT is set to 1, only the debug message is output
+ *
+ * When both are set to 0, no trace are output
+ * When both are set to 1,  CFG_DEBUG_TRACE_FULL is selected
+ */
+#define CFG_DEBUG_TRACE_LIGHT     1
+#define CFG_DEBUG_TRACE_FULL      0
+
+#if (( CFG_DEBUG_TRACE != 0 ) && ( CFG_DEBUG_TRACE_LIGHT == 0 ) && (CFG_DEBUG_TRACE_FULL == 0))
+#undef CFG_DEBUG_TRACE_FULL
+#undef CFG_DEBUG_TRACE_LIGHT
+#define CFG_DEBUG_TRACE_FULL      0
+#define CFG_DEBUG_TRACE_LIGHT     1
+#endif
+
+#if ( CFG_DEBUG_TRACE == 0 )
+#undef CFG_DEBUG_TRACE_FULL
+#undef CFG_DEBUG_TRACE_LIGHT
+#define CFG_DEBUG_TRACE_FULL      0
+#define CFG_DEBUG_TRACE_LIGHT     0
+#endif
+
+/**
+ * When not set, the traces is looping on sending the trace over UART
+ */
+#define DBG_TRACE_USE_CIRCULAR_QUEUE 1
+
+/**
+ * max buffer Size to queue data traces and max data trace allowed.
+ * Only Used if DBG_TRACE_USE_CIRCULAR_QUEUE is defined
+ */
+#define DBG_TRACE_MSG_QUEUE_SIZE 4096
+#define MAX_DBG_TRACE_MSG_SIZE 1024
+
+/* USER CODE BEGIN Defines */
+#define CFG_LED_SUPPORTED         1
+#define CFG_BUTTON_SUPPORTED      1
+
+#ifdef LITTLE_DORY
+#define PUSH_BUTTON_SW1_EXTI_IRQHandler                         EXTI0_IRQHandler
+#define PUSH_BUTTON_SW2_EXTI_IRQHandler                         EXTI4_IRQHandler
+#else
+#define PUSH_BUTTON_SW1_EXTI_IRQHandler                         EXTI4_IRQHandler
+#define PUSH_BUTTON_SW2_EXTI_IRQHandler                         EXTI0_IRQHandler
+#endif
+/* USER CODE END Defines */
+
+/******************************************************************************
+ * Scheduler
+ ******************************************************************************/
+
+/**
+ * These are the lists of task id registered to the scheduler
+ * Each task id shall be in the range [0:31]
+ * This mechanism allows to implement a generic code in the API TL_BLE_HCI_StatusNot() to comply with
+ * the requirement that a HCI/ACI command shall never be sent if there is already one pending
+ */
+
+/**< Add in that list all tasks that may send a ACI/HCI command */
+typedef enum
+{
+    CFG_TASK_START_SCAN_ID,
+    CFG_TASK_CONN_DEV_1_ID,
+    CFG_TASK_SEARCH_SERVICE_ID,
+    CFG_TASK_SW1_BUTTON_PUSHED_ID,
+    CFG_TASK_CONN_UPDATE_ID,
+    CFG_TASK_HCI_ASYNCH_EVT_ID,
+/* USER CODE BEGIN CFG_Task_Id_With_HCI_Cmd_t */
+
+/* USER CODE END CFG_Task_Id_With_HCI_Cmd_t */
+    CFG_LAST_TASK_ID_WITH_HCICMD,                                               /**< Shall be LAST in the list */
+} CFG_Task_Id_With_HCI_Cmd_t;
+
+/**< Add in that list all tasks that never send a ACI/HCI command */
+typedef enum
+{
+    CFG_FIRST_TASK_ID_WITH_NO_HCICMD = CFG_LAST_TASK_ID_WITH_HCICMD - 1,        /**< Shall be FIRST in the list */
+    CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID,
+/* USER CODE BEGIN CFG_Task_Id_With_NO_HCI_Cmd_t */
+
+/* USER CODE END CFG_Task_Id_With_NO_HCI_Cmd_t */
+    CFG_LAST_TASK_ID_WITHO_NO_HCICMD                                            /**< Shall be LAST in the list */
+} CFG_Task_Id_With_NO_HCI_Cmd_t;
+#define CFG_TASK_NBR    CFG_LAST_TASK_ID_WITHO_NO_HCICMD
+
+/**
+ * This is the list of priority required by the application
+ * Each Id shall be in the range 0..31
+ */
+typedef enum
+{
+    CFG_SCH_PRIO_0,
+    CFG_PRIO_NBR,
+} CFG_SCH_Prio_Id_t;
+
+/**
+ * This is a bit mapping over 32bits listing all events id supported in the application
+ */
+typedef enum
+{
+    CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID,
+    CFG_IDLEEVT_SYSTEM_HCI_CMD_EVT_RSP_ID,
+} CFG_IdleEvt_Id_t;
+
+/******************************************************************************
+ * LOW POWER
+ ******************************************************************************/
+/**
+ * Supported requester to the MCU Low Power Manager - can be increased up  to 32
+ * It lits a bit mapping of all user of the Low Power Manager
+ */
+typedef enum
+{
+    CFG_LPM_APP,
+    CFG_LPM_APP_BLE,
+  /* USER CODE BEGIN CFG_LPM_Id_t */
+
+  /* USER CODE END CFG_LPM_Id_t */
+} CFG_LPM_Id_t;
+
+/******************************************************************************
+ * OTP manager
+ ******************************************************************************/
+#define CFG_OTP_BASE_ADDRESS    OTP_AREA_BASE
+
+#define CFG_OTP_END_ADRESS      OTP_AREA_END_ADDR
+
+#endif /*APP_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/app_debug.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/app_debug.h
new file mode 100644
index 000000000..13485c16b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/app_debug.h
@@ -0,0 +1,45 @@
+
+/**
+  ******************************************************************************
+  * @file    app_debug.h
+  * @author  MCD Application Team
+  * @brief   Interface to support debug in the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+  /* Exported types ------------------------------------------------------------*/
+  /* Exported constants --------------------------------------------------------*/
+  /* External variables --------------------------------------------------------*/
+  /* Exported macros -----------------------------------------------------------*/
+  /* Exported functions ------------------------------------------------------- */
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/app_entry.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/app_entry.h
new file mode 100644
index 000000000..77ead2384
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/app_entry.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    app_entry.h
+  * @author  MCD Application Team
+  * @brief   Interface to the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_ENTRY_H
+#define APP_ENTRY_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APPE_Init( void );
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*APP_ENTRY_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/hw_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/hw_conf.h
new file mode 100644
index 000000000..f4f55affa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/hw_conf.h
@@ -0,0 +1,196 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : hw_conf.h
+  * Description        : Hardware configuration file for BLE 
+  *                      middleWare.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef HW_CONF_H
+#define HW_CONF_H
+
+/******************************************************************************
+* Semaphores
+* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
+*****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
+/* Index of the semaphore used to manage the entry Stop Mode procedure */
+#define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
+
+/* Index of the semaphore used to access the RCC */
+#define CFG_HW_RCC_SEMID                                        3
+
+/* Index of the semaphore used to access the FLASH */
+#define CFG_HW_FLASH_SEMID                                      2
+
+/* Index of the semaphore used to access the PKA */
+#define CFG_HW_PKA_SEMID                                        1
+
+/* Index of the semaphore used to access the RNG */
+#define CFG_HW_RNG_SEMID                                        0
+
+/******************************************************************************
+ * HW TIMER SERVER
+ *****************************************************************************/
+/**
+ * The user may define the maximum number of virtual timers supported.
+ * It shall not exceed 255
+ */
+#define CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER  6
+
+/**
+ * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
+ * wakeup timer.
+ * This setting is the preemptpriority part of the NVIC.
+ */
+#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO  3
+
+/**
+ * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
+ * wakeup timer.
+ * This setting is the subpriority part of the NVIC. It does not exist on all processors. When it is not supported
+ * on the CPU, the setting is ignored
+ */
+#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO  0
+
+/**
+ *  Define a critical section in the Timer server
+ *  The Timer server does not support the API to be nested
+ *  The  Application shall either:
+ *    a) Ensure this will never happen
+ *    b) Define the critical section
+ *  The default implementations is masking all interrupts using the PRIMASK bit
+ *  The TimerServer driver uses critical sections to avoid context corruption. This is achieved with the macro
+ *  TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION. When CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION is set
+ *  to 1, all STM32 interrupts are masked with the PRIMASK bit of the CortexM CPU. It is possible to use the BASEPRI
+ *  register of the CortexM CPU to keep allowed some interrupts with high priority. In that case, the user shall
+ *  re-implement TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION and shall make sure that no TimerServer
+ *  API are called when the TIMER critical section is entered
+ */
+#define CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION  1
+
+/**
+   * This value shall reflect the maximum delay there could be in the application between the time the RTC interrupt
+   * is generated by the Hardware and the time when the  RTC interrupt handler is called. This time is measured in
+   * number of RTCCLK ticks.
+   * A relaxed timing would be 10ms
+   * When the value is too short, the timerserver will not be able to count properly and all timeout may be random.
+   * When the value is too long, the device may wake up more often than the most optimal configuration. However, the
+   * impact on power consumption would be marginal (unless the value selected is extremely too long). It is strongly
+   * recommended to select a value large enough to make sure it is not too short to ensure reliability of the system
+   * as this will have marginal impact on low power mode
+   */
+#define CFG_HW_TS_RTC_HANDLER_MAX_DELAY  ( 10 * (LSI_VALUE/1000) )
+
+  /**
+   * Interrupt ID in the NVIC of the RTC Wakeup interrupt handler
+   * It shall be type of IRQn_Type
+   */
+#define CFG_HW_TS_RTC_WAKEUP_HANDLER_ID  RTC_WKUP_IRQn
+
+/******************************************************************************
+ * HW UART
+ *****************************************************************************/
+
+#define CFG_HW_LPUART1_ENABLED           0
+#define CFG_HW_LPUART1_DMA_TX_SUPPORTED  0
+
+#define CFG_HW_USART1_ENABLED           1
+#define CFG_HW_USART1_DMA_TX_SUPPORTED  1
+
+/**
+ * UART1
+ */
+#define CFG_HW_USART1_PREEMPTPRIORITY         0x0F
+#define CFG_HW_USART1_SUBPRIORITY             0
+
+/** < The application shall check the selected source clock is enable */
+#define CFG_HW_USART1_SOURCE_CLOCK              RCC_USART1CLKSOURCE_SYSCLK
+
+#define CFG_HW_USART1_BAUDRATE                115200
+#define CFG_HW_USART1_WORDLENGTH              UART_WORDLENGTH_8B
+#define CFG_HW_USART1_STOPBITS                UART_STOPBITS_1
+#define CFG_HW_USART1_PARITY                  UART_PARITY_NONE
+#define CFG_HW_USART1_HWFLOWCTL               UART_HWCONTROL_NONE
+#define CFG_HW_USART1_MODE                    UART_MODE_TX_RX
+#define CFG_HW_USART1_ADVFEATUREINIT          UART_ADVFEATURE_NO_INIT
+#define CFG_HW_USART1_OVERSAMPLING            UART_OVERSAMPLING_8
+
+#define CFG_HW_USART1_TX_PORT_CLK_ENABLE      __HAL_RCC_GPIOB_CLK_ENABLE
+#define CFG_HW_USART1_TX_PORT                 GPIOB
+#define CFG_HW_USART1_TX_PIN                  GPIO_PIN_6
+#define CFG_HW_USART1_TX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_USART1_TX_PULL                 GPIO_NOPULL
+#define CFG_HW_USART1_TX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_TX_ALTERNATE            GPIO_AF7_USART1
+
+#define CFG_HW_USART1_RX_PORT_CLK_ENABLE      __HAL_RCC_GPIOB_CLK_ENABLE
+#define CFG_HW_USART1_RX_PORT                 GPIOB
+#define CFG_HW_USART1_RX_PIN                  GPIO_PIN_7
+#define CFG_HW_USART1_RX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_USART1_RX_PULL                 GPIO_NOPULL
+#define CFG_HW_USART1_RX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_RX_ALTERNATE            GPIO_AF7_USART1
+
+#define CFG_HW_USART1_CTS_PORT_CLK_ENABLE     __HAL_RCC_GPIOA_CLK_ENABLE
+#define CFG_HW_USART1_CTS_PORT                GPIOA
+#define CFG_HW_USART1_CTS_PIN                 GPIO_PIN_11
+#define CFG_HW_USART1_CTS_MODE                GPIO_MODE_AF_PP
+#define CFG_HW_USART1_CTS_PULL                GPIO_PULLDOWN
+#define CFG_HW_USART1_CTS_SPEED               GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_CTS_ALTERNATE           GPIO_AF7_USART1
+
+#define CFG_HW_USART1_DMA_TX_PREEMPTPRIORITY  0x0F
+#define CFG_HW_USART1_DMA_TX_SUBPRIORITY      0
+
+#define CFG_HW_USART1_DMAMUX_CLK_ENABLE       __HAL_RCC_DMAMUX1_CLK_ENABLE
+#define CFG_HW_USART1_DMA_CLK_ENABLE          __HAL_RCC_DMA2_CLK_ENABLE
+#define CFG_HW_USART1_TX_DMA_REQ			  DMA_REQUEST_USART1_TX
+#define CFG_HW_USART1_TX_DMA_CHANNEL          DMA2_CHANNEL_4
+#define CFG_HW_USART1_TX_DMA_IRQn             DMA2_CHANNEL_4_IRQn
+#define CFG_HW_USART1_DMA_TX_IRQHandler       DMA2_CHANNEL_4_IRQHandler
+
+#endif /*HW_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/hw_if.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/hw_if.h
new file mode 100644
index 000000000..5a15665ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/hw_if.h
@@ -0,0 +1,254 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    hw_if.h
+  * @author  MCD Application Team
+  * @brief   Hardware Interface
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef HW_IF_H
+#define HW_IF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_ipcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_hsem.h"
+#include "stm32wbxx_ll_gpio.h"
+#include "stm32wbxx_ll_rtc.h"
+
+#ifdef  USE_STM32WBXX_USB_DONGLE
+#include "stm32wbxx_usb_dongle.h"
+#endif
+#ifdef  USE_STM32WBXX_NUCLEO
+  #ifdef STM32WB35xx
+  #include "nucleo_wb35ce.h"
+  #else
+  #include "stm32wbxx_nucleo.h"
+  #endif
+#endif
+#ifdef  USE_X_NUCLEO_EPD
+#include "x_nucleo_epd.h"
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /******************************************************************************
+   * HW UART
+   ******************************************************************************/
+  typedef enum
+  {
+    hw_uart1,
+    hw_uart2,
+    hw_lpuart1,
+  } hw_uart_id_t;
+
+  typedef enum
+  {
+    hw_uart_ok,
+    hw_uart_error,
+    hw_uart_busy,
+    hw_uart_to,
+  } hw_status_t;
+
+  void HW_UART_Init(hw_uart_id_t hw_uart_id);
+  void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *pData, uint16_t Size, void (*Callback)(void));
+  void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *pData, uint16_t Size,  void (*Callback)(void));
+  hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout);
+  hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*Callback)(void));
+  void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id);
+  void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id);
+
+  /******************************************************************************
+   * HW TimerServer
+   ******************************************************************************/
+  /* Exported types ------------------------------------------------------------*/
+  /**
+   * This setting is used when standby mode is supported.
+   * hw_ts_InitMode_Limited should be used when the device restarts from Standby Mode. In that case, the Timer Server does
+   * not re-initialized its context. Only the Hardware register which content has been lost is reconfigured
+   * Otherwise, hw_ts_InitMode_Full should be requested (Start from Power ON) and everything is re-initialized.
+   */
+  typedef enum
+  {
+    hw_ts_InitMode_Full,
+    hw_ts_InitMode_Limited,
+  } HW_TS_InitMode_t;
+
+  /**
+   * When a Timer is created as a SingleShot timer, it is not automatically restarted when the timeout occurs. However,
+   * the timer is kept reserved in the list and could be restarted at anytime with HW_TS_Start()
+   *
+   * When a Timer is created as a Repeated timer, it is automatically restarted when the timeout occurs.
+   */
+  typedef enum
+  {
+    hw_ts_SingleShot,
+    hw_ts_Repeated
+  } HW_TS_Mode_t;
+
+  /**
+   * hw_ts_Successful is returned when a Timer has been successfully created with HW_TS_Create(). Otherwise, hw_ts_Failed
+   * is returned. When hw_ts_Failed is returned, that means there are not enough free slots in the list to create a
+   * Timer. In that case, CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER should be increased
+   */
+  typedef enum
+  {
+    hw_ts_Successful,
+    hw_ts_Failed,
+  }HW_TS_ReturnStatus_t;
+
+  typedef void (*HW_TS_pTimerCb_t)(void);
+
+  /**
+   * @brief  Initialize the timer server
+   *         This API shall be called by the application before any timer is requested to the timer server. It
+   *         configures the RTC module to be connected to the LSI input clock.
+   *
+   * @param  TimerInitMode: When the device restarts from Standby, it should request hw_ts_InitMode_Limited so that the
+   *         Timer context is not re-initialized. Otherwise, hw_ts_InitMode_Full should be requested
+   * @param  hrtc: RTC Handle
+   * @retval None
+   */
+  void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *hrtc);
+
+  /**
+   * @brief  Interface to create a virtual timer
+   *         The user shall call this API to create a timer. Once created, the timer is reserved to the module until it
+   *         has been deleted. When creating a timer, the user shall specify the mode (single shot or repeated), the
+   *         callback to be notified when the timer expires and a module ID to identify in the timer interrupt handler
+   *         which module is concerned. In return, the user gets a timer ID to handle it.
+   *
+   * @param  TimerProcessID:  This is an identifier provided by the user and returned in the callback to allow
+   *                          identification of the requester
+   * @param  pTimerId: Timer Id returned to the user to request operation (start, stop, delete)
+   * @param  TimerMode: Mode of the virtual timer (Single shot or repeated)
+   * @param  pTimerCallBack: Callback when the virtual timer expires
+   * @retval HW_TS_ReturnStatus_t: Return whether the creation is sucessfull or not
+   */
+  HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pTimerCallBack);
+
+  /**
+   * @brief  Stop a virtual timer
+   *         This API may be used to stop a running timer. A timer which is stopped is move to the pending state.
+   *         A pending timer may be restarted at any time with a different timeout value but the mode cannot be changed.
+   *         Nothing is done when it is called to stop a timer which has been already stopped
+   *
+   * @param  TimerID:  Id of the timer to stop
+   * @retval None
+   */
+  void HW_TS_Stop(uint8_t TimerID);
+
+  /**
+   * @brief  Start a virtual timer
+   *         This API shall be used to start a timer. The timeout value is specified and may be different each time.
+   *         When the timer is in the single shot mode, it will move to the pending state when it expires. The user may
+   *         restart it at any time with a different timeout value. When the timer is in the repeated mode, it always
+   *         stay in the running state. When the timer expires, it will be restarted with the same timeout value.
+   *         This API shall not be called on a running timer.
+   *
+   * @param  TimerID:  The ID Id of the timer to start
+   * @param  timeout_ticks: Number of ticks of the virtual timer (Maximum value is (0xFFFFFFFF-0xFFFF = 0xFFFF0000)
+   * @retval None
+   */
+  void HW_TS_Start(uint8_t TimerID, uint32_t timeout_ticks);
+
+  /**
+   * @brief  Delete a virtual timer from the list
+   *         This API should be used when a timer is not needed anymore by the user. A deleted timer is removed from
+   *         the timer list managed by the timer server. It cannot be restarted again. The user has to go with the
+   *         creation of a new timer if required and may get a different timer id
+   *
+   * @param  TimerID:  The ID of the timer to remove from the list
+   * @retval None
+   */
+  void HW_TS_Delete(uint8_t TimerID);
+
+  /**
+   * @brief  Schedule the timer list on the timer interrupt handler
+   *         This interrupt handler shall be called by the application in the RTC interrupt handler. This handler takes
+   *         care of clearing all status flag required in the RTC and EXTI peripherals
+   *
+   * @param  None
+   * @retval None
+   */
+  void HW_TS_RTC_Wakeup_Handler(void);
+
+  /**
+   * @brief  Return the number of ticks to count before the interrupt
+   *         This API returns the number of ticks left to be counted before an interrupt is generated by the
+   *         Timer Server. This API may be used by the application for power management optimization. When the system
+   *         enters low power mode, the mode selection is a tradeoff between the wakeup time where the CPU is running
+   *         and the time while the CPU will be kept in low power mode before next wakeup. The deeper is the
+   *         low power mode used, the longer is the wakeup time. The low power mode management considering wakeup time
+   *         versus time in low power mode is implementation specific
+   *         When the timer is disabled (No timer in the list), it returns 0xFFFF
+   *
+   * @param  None
+   * @retval The number of ticks left to count
+   */
+  uint16_t HW_TS_RTC_ReadLeftTicksToCount(void);
+
+  /**
+   * @brief  Notify the application that a registered timer has expired
+   *         This API shall be implemented by the user application.
+   *         This API notifies the application that a timer expires. This API is running in the RTC Wakeup interrupt
+   *         context. The application may implement an Operating System to change the context priority where the timer
+   *         callback may be handled. This API provides the module ID to identify which module is concerned and to allow
+   *         sending the information to the correct task
+   *
+   * @param  TimerProcessID: The TimerProcessId associated with the timer when it has been created
+   * @param  TimerID: The TimerID of the expired timer
+   * @param  pTimerCallBack: The Callback associated with the timer when it has been created
+   * @retval None
+   */
+  void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack);
+
+  /**
+   * @brief  Notify the application that the wakeupcounter has been updated
+   *         This API should be implemented by the user application
+   *         This API notifies the application that the counter has been updated. This is expected to be used along
+   *         with the HW_TS_RTC_ReadLeftTicksToCount () API. It could be that the counter has been updated since the
+   *         last call of HW_TS_RTC_ReadLeftTicksToCount () and before entering low power mode. This notification
+   *         provides a way to the application to solve that race condition to reevaluate the counter value before
+   *         entering low power mode
+   *
+   * @param  None
+   * @retval None
+   */
+  void HW_TS_RTC_CountUpdated_AppNot(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*HW_IF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/main.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/main.h
new file mode 100644
index 000000000..c8b13c23f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/main.h
@@ -0,0 +1,75 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#ifdef STM32WB35xx
+#include "nucleo_wb35ce.h"
+#else
+#include "stm32wbxx_nucleo.h"
+#endif
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/stm32_lpm_if.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/stm32_lpm_if.h
new file mode 100644
index 000000000..d8e67947f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/stm32_lpm_if.h
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+******************************************************************************
+* @file    stm32_lpm_if.h
+* @brief   Header for stm32_lpm_if.c module (device specific LP management)
+******************************************************************************
+* @attention
+*
+* 
    © Copyright (c) 2019 STMicroelectronics. 
+* All rights reserved.
    
+*
+* This software component is licensed by ST under BSD 3-Clause license,
+* the "License"; You may not use this file except in compliance with the 
+* License. You may obtain a copy of the License at:
+*                        opensource.org/licenses/BSD-3-Clause
+*
+******************************************************************************
+*/
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_LPM_IF_H
+#define __STM32_LPM_IF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/**
+  * @brief Enters Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_EnterOffMode( void );
+/**
+  * @brief Exits Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_ExitOffMode( void );
+
+/**
+  * @brief Enters Low Power Stop Mode
+  * @note ARM exists the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterStopMode( void );
+/**
+  * @brief Exits Low Power Stop Mode
+  * @note Enable the pll at 32MHz
+  * @param none
+  * @retval none
+  */
+void PWR_ExitStopMode( void );
+
+/**
+  * @brief Enters Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterSleepMode( void );
+
+/**
+  * @brief Exits Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_ExitSleepMode( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32_LPM_IF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..eff335ddf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,354 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+#define HAL_CORTEX_MODULE_ENABLED
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+/*#define HAL_I2C_MODULE_ENABLED   */
+#define HAL_IPCC_MODULE_ENABLED
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+#define HAL_PWR_MODULE_ENABLED
+/*#define HAL_QSPI_MODULE_ENABLED   */
+#define HAL_RCC_MODULE_ENABLED
+/*#define HAL_RNG_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100UL)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  (32000UL)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  (32000UL)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    (48000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    (2097000UL) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..cf6cc65e7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/stm32wbxx_it.h
@@ -0,0 +1,78 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "app_common.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void DMA1_Channel4_IRQHandler(void);
+void USART1_IRQHandler(void);
+void LPUART1_IRQHandler(void);
+void DMA2_Channel4_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+void RTC_WKUP_IRQHandler(void);
+void IPCC_C1_TX_IRQHandler(void);
+void IPCC_C1_RX_IRQHandler(void);
+void PUSH_BUTTON_SW1_EXTI_IRQHandler(void);
+void PUSH_BUTTON_SW2_EXTI_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/utilities_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/utilities_conf.h
new file mode 100644
index 000000000..4dde3509a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Inc/utilities_conf.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : utilities_conf.h
+  * Description        : Configuration file for STM32 Utilities.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef UTILITIES_CONF_H
+#define UTILITIES_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "cmsis_compiler.h"
+#include "string.h"
+
+/******************************************************************************
+ * common
+ ******************************************************************************/
+#define UTILS_ENTER_CRITICAL_SECTION( )   uint32_t primask_bit = __get_PRIMASK( );\
+                                          __disable_irq( )
+
+#define UTILS_EXIT_CRITICAL_SECTION( )          __set_PRIMASK( primask_bit )
+
+#define UTILS_MEMSET8( dest, value, size )      memset( dest, value, size);
+
+/******************************************************************************
+ * tiny low power manager
+ * (any macro that does not need to be modified can be removed)
+ ******************************************************************************/
+#define UTIL_LPM_INIT_CRITICAL_SECTION( )
+#define UTIL_LPM_ENTER_CRITICAL_SECTION( )      UTILS_ENTER_CRITICAL_SECTION( )
+#define UTIL_LPM_EXIT_CRITICAL_SECTION( )       UTILS_EXIT_CRITICAL_SECTION( )
+
+/******************************************************************************
+ * sequencer
+ * (any macro that does not need to be modified can be removed)
+ ******************************************************************************/
+#define UTIL_SEQ_INIT_CRITICAL_SECTION( )
+#define UTIL_SEQ_ENTER_CRITICAL_SECTION( )      UTILS_ENTER_CRITICAL_SECTION( )
+#define UTIL_SEQ_EXIT_CRITICAL_SECTION( )       UTILS_EXIT_CRITICAL_SECTION( )
+#define UTIL_SEQ_CONF_TASK_NBR                  (32)
+#define UTIL_SEQ_CONF_PRIO_NBR                  (2)
+#define UTIL_SEQ_MEMSET8( dest, value, size )   UTILS_MEMSET8( dest, value, size )
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*UTILITIES_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/app_debug.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/app_debug.c
new file mode 100644
index 000000000..af3fdfbce
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/app_debug.c
@@ -0,0 +1,360 @@
+/**
+ ******************************************************************************
+ * @file    app_debug.c
+ * @author  MCD Application Team
+ * @brief   Debug capabilities
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+extern void MX_LPUART1_UART_Init(void);
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+extern void MX_USART1_UART_Init(void);
+#endif
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+#if (CFG_HW_USART1_ENABLED == 1)
+    MX_USART1_UART_Init();
+#endif
+#if (CFG_HW_LPUART1_ENABLED == 1)
+    MX_LPUART1_UART_Init();
+#endif
+  return;
+}
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/app_entry.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/app_entry.c
new file mode 100644
index 000000000..b7b0773cb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/app_entry.c
@@ -0,0 +1,299 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    app_entry.c
+ * @author  MCD Application Team
+ * @brief   Entry point of the Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "main.h"
+#include "app_entry.h"
+#include "app_ble.h"
+#include "ble.h"
+#include "tl.h"
+#include "stm32_seq.h"
+#include "shci_tl.h"
+#include "stm32_lpm.h"
+#include "app_debug.h"
+
+/* Private includes -----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+extern RTC_HandleTypeDef hrtc;
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+#define POOL_SIZE (CFG_TLBLE_EVT_QUEUE_LENGTH*4U*DIVC(( sizeof(TL_PacketHeader_t) + TL_BLE_EVENT_FRAME_SIZE ), 4U))
+
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t EvtPool[POOL_SIZE];
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static TL_CmdPacket_t SystemCmdBuffer;
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t SystemSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255U];
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t BleSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255];
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private functions prototypes-----------------------------------------------*/
+static void SystemPower_Config( void );
+static void appe_Tl_Init( void );
+static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status );
+static void APPE_SysUserEvtRx( void * pPayload );
+
+/* USER CODE BEGIN PFP */
+static void Led_Init( void );
+static void Button_Init( void );
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APPE_Init( void )
+{
+  SystemPower_Config(); /**< Configure the system Power Mode */
+
+  HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
+
+/* USER CODE BEGIN APPE_Init_1 */
+  APPD_Init();
+  
+  /**
+   * The Standby mode should not be entered before the initialization is over
+   * The default state of the Low Power Manager is to allow the Standby Mode so an request is needed here
+   */
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP, UTIL_LPM_DISABLE);
+
+  Led_Init();
+
+  Button_Init();
+/* USER CODE END APPE_Init_1 */
+  appe_Tl_Init();	/* Initialize all transport layers */
+
+  /**
+   * From now, the application is waiting for the ready event ( VS_HCI_C2_Ready )
+   * received on the system channel before starting the Stack
+   * This system event is received with APPE_SysUserEvtRx()
+   */
+/* USER CODE BEGIN APPE_Init_2 */
+
+/* USER CODE END APPE_Init_2 */
+   return;
+}
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+ * @brief  Configure the system for power optimization
+ *
+ * @note  This API configures the system to be ready for low power mode
+ *
+ * @param  None
+ * @retval None
+ */
+static void SystemPower_Config( void )
+{
+
+  /**
+   * Select HSI as system clock source after Wake Up from Stop mode
+   */
+  LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
+
+  /* Initialize low power manager */
+  UTIL_LPM_Init( );
+
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+  /**
+   *  Enable USB power
+   */
+  HAL_PWREx_EnableVddUSB();
+#endif
+
+  return;
+}
+
+static void appe_Tl_Init( void )
+{
+  TL_MM_Config_t tl_mm_config;
+  SHCI_TL_HciInitConf_t SHci_Tl_Init_Conf;
+  /**< Reference table initialization */
+  TL_Init();
+
+  /**< System channel initialization */
+  UTIL_SEQ_RegTask( 1<< CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID, UTIL_SEQ_RFU, shci_user_evt_proc );
+  SHci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&SystemCmdBuffer;
+  SHci_Tl_Init_Conf.StatusNotCallBack = APPE_SysStatusNot;
+  shci_init(APPE_SysUserEvtRx, (void*) &SHci_Tl_Init_Conf);
+
+  /**< Memory Manager channel initialization */
+  tl_mm_config.p_BleSpareEvtBuffer = BleSpareEvtBuffer;
+  tl_mm_config.p_SystemSpareEvtBuffer = SystemSpareEvtBuffer;
+  tl_mm_config.p_AsynchEvtPool = EvtPool;
+  tl_mm_config.AsynchEvtPoolSize = POOL_SIZE;
+  TL_MM_Init( &tl_mm_config );
+
+  TL_Enable();
+
+  return;
+}
+
+static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status )
+{
+  UNUSED(status);
+  return;
+}
+
+/**
+ * The type of the payload for a system user event is tSHCI_UserEvtRxParam
+ * When the system event is both :
+ *    - a ready event (subevtcode = SHCI_SUB_EVT_CODE_READY)
+ *    - reported by the FUS (sysevt_ready_rsp == RSS_FW_RUNNING)
+ * The buffer shall not be released
+ * ( eg ((tSHCI_UserEvtRxParam*)pPayload)->status shall be set to SHCI_TL_UserEventFlow_Disable )
+ * When the status is not filled, the buffer is released by default
+ */
+static void APPE_SysUserEvtRx( void * pPayload )
+{
+  UNUSED(pPayload);
+  /* Traces channel initialization */
+  APPD_EnableCPU2();
+
+  APP_BLE_Init( );
+  UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE);
+  return;
+}
+
+/* USER CODE BEGIN FD_LOCAL_FUNCTIONS */
+static void Led_Init( void )
+{
+#if (CFG_LED_SUPPORTED == 1)
+  /**
+   * Leds Initialization
+   */
+
+  BSP_LED_Init(LED_BLUE);
+  BSP_LED_Init(LED_GREEN);
+  BSP_LED_Init(LED_RED);
+
+  BSP_LED_On(LED_GREEN);
+#endif
+
+  return;
+}
+
+static void Button_Init( void )
+{
+#if (CFG_BUTTON_SUPPORTED == 1)
+  /**
+   * Button Initialization
+   */
+
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+#endif
+
+  return;
+}
+/* USER CODE END FD_LOCAL_FUNCTIONS */
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+
+void UTIL_SEQ_Idle( void )
+{
+#if ( CFG_LPM_SUPPORTED == 1)
+  UTIL_LPM_EnterLowPower( );
+#endif
+  return;
+}
+
+/**
+  * @brief  This function is called by the scheduler each time an event
+  *         is pending.
+  *
+  * @param  evt_waited_bm : Event pending.
+  * @retval None
+  */
+void UTIL_SEQ_EvtIdle( UTIL_SEQ_bm_t task_id_bm, UTIL_SEQ_bm_t evt_waited_bm )
+{
+  UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+}
+
+void shci_notify_asynch_evt(void* pdata)
+{
+  UTIL_SEQ_SetTask( 1<
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "hw_conf.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef enum
+{
+  TimerID_Free,
+  TimerID_Created,
+  TimerID_Running
+}TimerIDStatus_t;
+
+typedef enum
+{
+  SSR_Read_Requested,
+  SSR_Read_Not_Requested
+}RequestReadSSR_t;
+
+typedef enum
+{
+  WakeupTimerValue_Overpassed,
+  WakeupTimerValue_LargeEnough
+}WakeupTimerLimitation_Status_t;
+
+typedef struct
+{
+  HW_TS_pTimerCb_t  pTimerCallBack;
+  uint32_t        CounterInit;
+  uint32_t        CountLeft;
+  TimerIDStatus_t     TimerIDStatus;
+  HW_TS_Mode_t   TimerMode;
+  uint32_t        TimerProcessID;
+  uint8_t         PreviousID;
+  uint8_t         NextID;
+}TimerContext_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define SSR_FORBIDDEN_VALUE   0xFFFFFFFF
+#define TIMER_LIST_EMPTY      0xFFFF
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/**
+ * START of Section TIMERSERVER_CONTEXT
+ */
+
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile TimerContext_t aTimerContext[CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER];
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint8_t CurrentRunningTimerID;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint8_t PreviousRunningTimerID;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint32_t SSRValueOnLastSetup;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile WakeupTimerLimitation_Status_t  WakeupTimerLimitation;
+
+/**
+ * END of Section TIMERSERVER_CONTEXT
+ */
+
+static RTC_HandleTypeDef *phrtc;  /**< RTC handle */
+static uint8_t  WakeupTimerDivider;
+static uint8_t  AsynchPrescalerUserConfig;
+static uint16_t SynchPrescalerUserConfig;
+static volatile uint16_t MaxWakeupTimerSetup;
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void RestartWakeupCounter(uint16_t Value);
+static uint16_t ReturnTimeElapsed(void);
+static void RescheduleTimerList(void);
+static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR);
+static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID);
+static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID);
+static uint16_t linkTimer(uint8_t TimerID);
+static uint32_t ReadRtcSsrValue(void);
+
+__weak void HW_TS_RTC_CountUpdated_AppNot(void);
+
+/* Functions Definition ------------------------------------------------------*/
+
+/**
+ * @brief  Read the RTC_SSR value
+ *         As described in the reference manual, the RTC_SSR shall be read twice to ensure
+ *         reliability of the value
+ * @param  None
+ * @retval SSR value read
+ */
+static uint32_t ReadRtcSsrValue(void)
+{
+  uint32_t first_read;
+  uint32_t second_read;
+
+  first_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+
+  second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+
+  while(first_read != second_read)
+  {
+    first_read = second_read;
+
+    second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+  }
+
+  return second_read;
+}
+
+/**
+ * @brief  Insert a Timer in the list after the Timer ID specified
+ * @param  TimerID:   The ID of the Timer
+ * @param  RefTimerID: The ID of the Timer to be linked after
+ * @retval None
+ */
+static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID)
+{
+  uint8_t next_id;
+
+  next_id = aTimerContext[RefTimerID].NextID;
+
+  if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    aTimerContext[next_id].PreviousID = TimerID;
+  }
+  aTimerContext[TimerID].NextID = next_id;
+  aTimerContext[TimerID].PreviousID = RefTimerID ;
+  aTimerContext[RefTimerID].NextID = TimerID;
+
+  return;
+}
+
+/**
+ * @brief  Insert a Timer in the list before the ID specified
+ * @param  TimerID:   The ID of the Timer
+ * @param  RefTimerID: The ID of the Timer to be linked before
+ * @retval None
+ */
+static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID)
+{
+  uint8_t previous_id;
+
+  if(RefTimerID != CurrentRunningTimerID)
+  {
+    previous_id = aTimerContext[RefTimerID].PreviousID;
+
+    aTimerContext[previous_id].NextID = TimerID;
+    aTimerContext[TimerID].NextID = RefTimerID;
+    aTimerContext[TimerID].PreviousID = previous_id ;
+    aTimerContext[RefTimerID].PreviousID = TimerID;
+  }
+  else
+  {
+    aTimerContext[TimerID].NextID = RefTimerID;
+    aTimerContext[RefTimerID].PreviousID = TimerID;
+  }
+
+  return;
+}
+
+/**
+ * @brief  Insert a Timer in the list
+ * @param  TimerID:   The ID of the Timer
+ * @retval None
+ */
+static uint16_t linkTimer(uint8_t TimerID)
+{
+  uint32_t time_left;
+  uint16_t time_elapsed;
+  uint8_t timer_id_lookup;
+  uint8_t next_id;
+
+  if(CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    /**
+     * No timer in the list
+     */
+    PreviousRunningTimerID = CurrentRunningTimerID;
+    CurrentRunningTimerID = TimerID;
+    aTimerContext[TimerID].NextID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;
+
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+    time_elapsed = 0;
+  }
+  else
+  {
+    time_elapsed = ReturnTimeElapsed();
+
+    /**
+     * update count of the timer to be linked
+     */
+    aTimerContext[TimerID].CountLeft += time_elapsed;
+    time_left = aTimerContext[TimerID].CountLeft;
+
+    /**
+     * Search for index where the new timer shall be linked
+     */
+    if(aTimerContext[CurrentRunningTimerID].CountLeft <= time_left)
+    {
+      /**
+       * Search for the ID after the first one
+       */
+      timer_id_lookup = CurrentRunningTimerID;
+      next_id = aTimerContext[timer_id_lookup].NextID;
+      while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left))
+      {
+        timer_id_lookup = aTimerContext[timer_id_lookup].NextID;
+        next_id = aTimerContext[timer_id_lookup].NextID;
+      }
+
+      /**
+       * Link after the ID
+       */
+      LinkTimerAfter(TimerID, timer_id_lookup);
+    }
+    else
+    {
+      /**
+       * Link before the first ID
+       */
+      LinkTimerBefore(TimerID, CurrentRunningTimerID);
+      PreviousRunningTimerID = CurrentRunningTimerID;
+      CurrentRunningTimerID = TimerID;
+    }
+  }
+
+  return time_elapsed;
+}
+
+/**
+ * @brief  Remove a Timer from the list
+ * @param  TimerID:   The ID of the Timer
+ * @param  RequestReadSSR: Request to read the SSR register or not
+ * @retval None
+ */
+static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR)
+{
+  uint8_t previous_id;
+  uint8_t next_id;
+
+  if(TimerID == CurrentRunningTimerID)
+  {
+    PreviousRunningTimerID = CurrentRunningTimerID;
+    CurrentRunningTimerID = aTimerContext[TimerID].NextID;
+  }
+  else
+  {
+    previous_id = aTimerContext[TimerID].PreviousID;
+    next_id = aTimerContext[TimerID].NextID;
+
+    aTimerContext[previous_id].NextID = aTimerContext[TimerID].NextID;
+    if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+    {
+      aTimerContext[next_id].PreviousID = aTimerContext[TimerID].PreviousID;
+    }
+  }
+
+  /**
+   * Timer is out of the list
+   */
+  aTimerContext[TimerID].TimerIDStatus = TimerID_Created;
+
+  if((CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (RequestReadSSR == SSR_Read_Requested))
+  {
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+  }
+
+  return;
+}
+
+/**
+ * @brief  Return the number of ticks counted by the wakeuptimer since it has been started
+ * @note  The API is reading the SSR register to get how many ticks have been counted
+ *        since the time the timer has been started
+ * @param  None
+ * @retval Time expired in Ticks
+ */
+static uint16_t ReturnTimeElapsed(void)
+{
+  uint32_t  return_value;
+  uint32_t  wrap_counter;
+
+  if(SSRValueOnLastSetup != SSR_FORBIDDEN_VALUE)
+  {
+    return_value = ReadRtcSsrValue(); /**< Read SSR register first */
+
+    if (SSRValueOnLastSetup >= return_value)
+    {
+      return_value = SSRValueOnLastSetup - return_value;
+    }
+    else
+    {
+      wrap_counter = SynchPrescalerUserConfig - return_value;
+      return_value = SSRValueOnLastSetup + wrap_counter;
+    }
+
+    /**
+     * At this stage, ReturnValue holds the number of ticks counted by SSR
+     * Need to translate in number of ticks counted by the Wakeuptimer
+     */
+    return_value = return_value*AsynchPrescalerUserConfig;
+    return_value = return_value >> WakeupTimerDivider;
+  }
+  else
+  {
+    return_value = 0;
+  }
+
+  return (uint16_t)return_value;
+}
+
+/**
+ * @brief  Set the wakeup counter
+ * @note  The API is writing the counter value so that the value is decreased by one to cope with the fact
+ *    the interrupt is generated with 1 extra clock cycle (See RefManuel)
+ *    It assumes all condition are met to be allowed to write the wakeup counter
+ * @param  Value: Value to be written in the counter
+ * @retval None
+ */
+static void RestartWakeupCounter(uint16_t Value)
+{
+  /**
+   * The wakeuptimer has been disabled in the calling function to reduce the time to poll the WUTWF
+   * FLAG when the new value will have to be written
+   *  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);
+   */
+
+  if(Value == 0)
+  {
+    SSRValueOnLastSetup = ReadRtcSsrValue();
+
+    /**
+     * Simulate that the Timer expired
+     */
+    HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
+  }
+  else
+  {
+    if((Value > 1) ||(WakeupTimerDivider != 1))
+    {
+      Value -= 1;
+    }
+
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+    /**
+     * make sure to clear the flags after checking the WUTWF.
+     * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+     * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+     * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+     * due to the autoreload feature
+     */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+    HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);   /**<  Clear pending bit in NVIC */
+
+    MODIFY_REG(RTC->WUTR, RTC_WUTR_WUT, Value);
+
+    /**
+     * Update the value here after the WUTWF polling that may take some time
+     */
+    SSRValueOnLastSetup = ReadRtcSsrValue();
+
+    __HAL_RTC_WAKEUPTIMER_ENABLE(phrtc);    /**<  Enable the Wakeup Timer */
+
+    HW_TS_RTC_CountUpdated_AppNot();
+  }
+
+  return ;
+}
+
+/**
+ * @brief  Reschedule the list of timer
+ * @note  1) Update the count left for each timer in the list
+ *    2) Setup the wakeuptimer
+ * @param  None
+ * @retval None
+ */
+static void RescheduleTimerList(void)
+{
+  uint8_t   localTimerID;
+  uint32_t  timecountleft;
+  uint16_t  wakeup_timer_value;
+  uint16_t  time_elapsed;
+
+  /**
+   * The wakeuptimer is disabled now to reduce the time to poll the WUTWF
+   * FLAG when the new value will have to be written
+   */
+  if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+  {
+    /**
+     * Wait for the flag to be back to 0 when the wakeup timer is enabled
+     */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == SET);
+  }
+  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);   /**<  Disable the Wakeup Timer */
+
+  localTimerID = CurrentRunningTimerID;
+
+  /**
+   * Calculate what will be the value to write in the wakeuptimer
+   */
+  timecountleft = aTimerContext[localTimerID].CountLeft;
+
+  /**
+   * Read how much has been counted
+   */
+  time_elapsed = ReturnTimeElapsed();
+
+  if(timecountleft < time_elapsed )
+  {
+    /**
+     * There is no tick left to count
+     */
+    wakeup_timer_value = 0;
+    WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+  }
+  else
+  {
+    if(timecountleft > (time_elapsed + MaxWakeupTimerSetup))
+    {
+      /**
+       * The number of tick left is greater than the Wakeuptimer maximum value
+       */
+      wakeup_timer_value = MaxWakeupTimerSetup;
+
+      WakeupTimerLimitation = WakeupTimerValue_Overpassed;
+    }
+    else
+    {
+      wakeup_timer_value = timecountleft - time_elapsed;
+      WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+    }
+
+  }
+
+  /**
+   * update ticks left to be counted for each timer
+   */
+  while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    if (aTimerContext[localTimerID].CountLeft < time_elapsed)
+    {
+      aTimerContext[localTimerID].CountLeft = 0;
+    }
+    else
+    {
+      aTimerContext[localTimerID].CountLeft -= time_elapsed;
+    }
+    localTimerID = aTimerContext[localTimerID].NextID;
+  }
+
+  /**
+   * Write next count
+   */
+  RestartWakeupCounter(wakeup_timer_value);
+
+  return ;
+}
+
+/* Public functions ----------------------------------------------------------*/
+
+/**
+ * For all public interface except that may need write access to the RTC, the RTC
+ * shall be unlock at the beginning and locked at the output
+ * In order to ease maintainability, the unlock is done at the top and the lock at then end
+ * in case some new implementation is coming in the future
+ */
+
+void HW_TS_RTC_Wakeup_Handler(void)
+{
+  HW_TS_pTimerCb_t ptimer_callback;
+  uint32_t timer_process_id;
+  uint8_t local_current_running_timer_id;
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  /**
+   * Disable the Wakeup Timer
+   * This may speed up a bit the processing to wait the timer to be disabled
+   * The timer is still counting 2 RTCCLK
+   */
+  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);
+
+  local_current_running_timer_id = CurrentRunningTimerID;
+
+  if(aTimerContext[local_current_running_timer_id].TimerIDStatus == TimerID_Running)
+  {
+    ptimer_callback = aTimerContext[local_current_running_timer_id].pTimerCallBack;
+    timer_process_id = aTimerContext[local_current_running_timer_id].TimerProcessID;
+
+    /**
+     * It should be good to check whether the TimeElapsed is greater or not than the tick left to be counted
+     * However, due to the inaccuracy of the reading of the time elapsed, it may return there is 1 tick
+     * to be left whereas the count is over
+     * A more secure implementation has been done with a flag to state whereas the full count has been written
+     * in the wakeuptimer or not
+     */
+    if(WakeupTimerLimitation != WakeupTimerValue_Overpassed)
+    {
+      if(aTimerContext[local_current_running_timer_id].TimerMode == hw_ts_Repeated)
+      {
+        UnlinkTimer(local_current_running_timer_id, SSR_Read_Not_Requested);
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+        __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+        HW_TS_Start(local_current_running_timer_id, aTimerContext[local_current_running_timer_id].CounterInit);
+
+        /* Disable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+      }
+      else
+      {
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+        __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+        HW_TS_Stop(local_current_running_timer_id);
+
+        /* Disable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+      }
+
+      HW_TS_RTC_Int_AppNot(timer_process_id, local_current_running_timer_id, ptimer_callback);
+    }
+    else
+    {
+      RescheduleTimerList();
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+      __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+    }
+  }
+  else
+  {
+    /**
+     * We should never end up in this case
+     * However, if due to any bug in the timer server this is the case, the mistake may not impact the user.
+     * We could just clean the interrupt flag and get out from this unexpected interrupt
+     */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+    /**
+     * make sure to clear the flags after checking the WUTWF.
+     * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+     * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+     * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+     * due to the autoreload feature
+     */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  return;
+}
+
+void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *hrtc)
+{
+  uint8_t loop;
+  uint32_t localmaxwakeuptimersetup;
+
+  /**
+   * Get RTC handler
+   */
+  phrtc = hrtc;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
+
+  /**
+   * Readout the user config
+   */
+  WakeupTimerDivider = (4 - ((uint32_t)(READ_BIT(RTC->CR, RTC_CR_WUCKSEL))));
+
+  AsynchPrescalerUserConfig = (uint8_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_A) >> (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)) + 1;
+
+  SynchPrescalerUserConfig = (uint16_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_S)) + 1;
+
+  /**
+   *  Margin is taken to avoid wrong calculation when the wrap around is there and some
+   *  application interrupts may have delayed the reading
+   */
+  localmaxwakeuptimersetup = ((((SynchPrescalerUserConfig - 1)*AsynchPrescalerUserConfig) - CFG_HW_TS_RTC_HANDLER_MAX_DELAY) >> WakeupTimerDivider);
+
+  if(localmaxwakeuptimersetup >= 0xFFFF)
+  {
+    MaxWakeupTimerSetup = 0xFFFF;
+  }
+  else
+  {
+    MaxWakeupTimerSetup = (uint16_t)localmaxwakeuptimersetup;
+  }
+
+  /**
+   * Configure EXTI module
+   */
+  LL_EXTI_EnableRisingTrig_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+  LL_EXTI_EnableIT_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+
+  if(TimerInitMode == hw_ts_InitMode_Full)
+  {
+    WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+
+    /**
+     * Initialize the timer server
+     */
+    for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++)
+    {
+      aTimerContext[loop].TimerIDStatus = TimerID_Free;
+    }
+
+    CurrentRunningTimerID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;   /**<  Set ID to non valid value */
+
+    __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);                       /**<  Disable the Wakeup Timer */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);     /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module  */
+    HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);       /**<  Clear pending bit in NVIC  */
+    __HAL_RTC_WAKEUPTIMER_ENABLE_IT(phrtc, RTC_IT_WUT);         /**<  Enable interrupt in RTC module  */
+  }
+  else
+  {
+    if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTF) != RESET)
+    {
+      /**
+       * Simulate that the Timer expired
+       */
+      HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_SetPriority(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO);   /**<  Set NVIC priority */
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+  return;
+}
+
+HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pftimeout_handler)
+{
+  HW_TS_ReturnStatus_t localreturnstatus;
+  uint8_t loop = 0;
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  while((loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[loop].TimerIDStatus != TimerID_Free))
+  {
+    loop++;
+  }
+
+  if(loop != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    aTimerContext[loop].TimerIDStatus = TimerID_Created;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+    aTimerContext[loop].TimerProcessID = TimerProcessID;
+    aTimerContext[loop].TimerMode = TimerMode;
+    aTimerContext[loop].pTimerCallBack = pftimeout_handler;
+    *pTimerId = loop;
+
+    localreturnstatus = hw_ts_Successful;
+  }
+  else
+  {
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+    localreturnstatus = hw_ts_Failed;
+  }
+
+  return(localreturnstatus);
+}
+
+void HW_TS_Delete(uint8_t timer_id)
+{
+  HW_TS_Stop(timer_id);
+
+  aTimerContext[timer_id].TimerIDStatus = TimerID_Free; /**<  release ID */
+
+  return;
+}
+
+void HW_TS_Stop(uint8_t timer_id)
+{
+  uint8_t localcurrentrunningtimerid;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);    /**<  Disable NVIC */
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
+  {
+    UnlinkTimer(timer_id, SSR_Read_Requested);
+    localcurrentrunningtimerid = CurrentRunningTimerID;
+
+    if(localcurrentrunningtimerid == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+    {
+      /**
+       * List is empty
+       */
+
+      /**
+       * Disable the timer
+       */
+      if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+      {
+        /**
+         * Wait for the flag to be back to 0 when the wakeup timer is enabled
+         */
+        while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == SET);
+      }
+      __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);   /**<  Disable the Wakeup Timer */
+
+      while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+      /**
+       * make sure to clear the flags after checking the WUTWF.
+       * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+       * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+       * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+       * due to the autoreload feature
+       */
+      __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+      __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+      HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);   /**<  Clear pending bit in NVIC */
+    }
+    else if(PreviousRunningTimerID != localcurrentrunningtimerid)
+    {
+      RescheduleTimerList();
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+  return;
+}
+
+void HW_TS_Start(uint8_t timer_id, uint32_t timeout_ticks)
+{
+  uint16_t time_elapsed;
+  uint8_t localcurrentrunningtimerid;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+  if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
+  {
+    HW_TS_Stop( timer_id );
+  }
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);    /**<  Disable NVIC */
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  aTimerContext[timer_id].TimerIDStatus = TimerID_Running;
+
+  aTimerContext[timer_id].CountLeft = timeout_ticks;
+  aTimerContext[timer_id].CounterInit = timeout_ticks;
+
+  time_elapsed =  linkTimer(timer_id);
+
+  localcurrentrunningtimerid = CurrentRunningTimerID;
+
+  if(PreviousRunningTimerID != localcurrentrunningtimerid)
+  {
+    RescheduleTimerList();
+  }
+  else
+  {
+    aTimerContext[timer_id].CountLeft -= time_elapsed;
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+  return;
+}
+
+uint16_t HW_TS_RTC_ReadLeftTicksToCount(void)
+{
+  uint32_t primask_bit;
+  uint16_t return_value, auro_reload_value, elapsed_time_value;
+
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();                /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+
+  if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+  {
+    auro_reload_value = (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT));
+
+    elapsed_time_value = ReturnTimeElapsed();
+
+    if(auro_reload_value > elapsed_time_value)
+    {
+      return_value = auro_reload_value - elapsed_time_value;
+    }
+    else
+    {
+      return_value = 0;
+    }
+  }
+  else
+  {
+    return_value = TIMER_LIST_EMPTY;
+  }
+
+  __set_PRIMASK(primask_bit);     /**< Restore PRIMASK bit*/
+
+  return (return_value);
+}
+
+__weak void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack)
+{
+  pTimerCallBack();
+
+  return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/hw_uart.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/hw_uart.c
new file mode 100644
index 000000000..9a553610d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/hw_uart.c
@@ -0,0 +1,318 @@
+/**
+ ******************************************************************************
+  * File Name          : Src/hw_uart.c
+  * Description        : HW UART source file for STM32WPAN Middleware.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "hw_conf.h"
+#if (CFG_HW_LPUART1_ENABLED == 1)
+extern UART_HandleTypeDef hlpuart1;
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+extern UART_HandleTypeDef huart1;
+#endif
+
+/* Macros --------------------------------------------------------------------*/
+#define HW_UART_RX_IT(__HANDLE__, __USART_BASE__)                                                   \
+        do{                                                                                         \
+            HW_##__HANDLE__##RxCb = cb;                                                             \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            HAL_UART_Receive_IT(&(__HANDLE__), p_data, size);                                       \
+        } while(0)
+
+#define HW_UART_TX_IT(__HANDLE__, __USART_BASE__)                                                   \
+        do{                                                                                         \
+            HW_##__HANDLE__##TxCb = cb;                                                             \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            HAL_UART_Transmit_IT(&(__HANDLE__), p_data, size);                                      \
+        } while(0)
+
+#define HW_UART_TX(__HANDLE__, __USART_BASE__)                                                      \
+        do{                                                                                         \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            hal_status = HAL_UART_Transmit(&(__HANDLE__), p_data, size, timeout);                   \
+        } while(0)
+
+/* Variables -----------------------------------------------------------------*/
+#if (CFG_HW_USART1_ENABLED == 1)
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+    DMA_HandleTypeDef HW_hdma_huart1_tx ={0};
+#endif
+    void (*HW_huart1RxCb)(void);
+    void (*HW_huart1TxCb)(void);
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+    DMA_HandleTypeDef HW_hdma_hlpuart1_tx ={0};
+#endif
+    void (*HW_hlpuart1RxCb)(void);
+    void (*HW_hlpuart1TxCb)(void);
+#endif
+
+void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_RX_IT(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_RX_IT(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  void (*cb)(void))
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_TX_IT(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_TX_IT(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout)
+{
+    HAL_StatusTypeDef hal_status = HAL_OK;
+    hw_status_t hw_status = hw_uart_ok;
+
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_TX(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_TX(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    switch (hal_status)
+    {
+        case HAL_OK:
+            hw_status = hw_uart_ok;
+            break;
+
+        case HAL_ERROR:
+            hw_status = hw_uart_error;
+            break;
+
+        case HAL_BUSY:
+            hw_status = hw_uart_busy;
+            break;
+
+        case HAL_TIMEOUT:
+            hw_status = hw_uart_to;
+            break;
+
+        default:
+            break;
+    }
+
+    return hw_status;
+}
+
+hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+{
+    HAL_StatusTypeDef hal_status = HAL_OK;
+    hw_status_t hw_status = hw_uart_ok;
+
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_huart1TxCb = cb;
+            huart1.Instance = USART1;
+            hal_status = HAL_UART_Transmit_DMA(&huart1, p_data, size);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_hlpuart1TxCb = cb;
+            hlpuart1.Instance = LPUART1;
+            hal_status = HAL_UART_Transmit_DMA(&hlpuart1, p_data, size);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    switch (hal_status)
+    {
+        case HAL_OK:
+            hw_status = hw_uart_ok;
+            break;
+
+        case HAL_ERROR:
+            hw_status = hw_uart_error;
+            break;
+
+        case HAL_BUSY:
+            hw_status = hw_uart_busy;
+            break;
+
+        case HAL_TIMEOUT:
+            hw_status = hw_uart_to;
+            break;
+
+        default:
+            break;
+    }
+
+    return hw_status;
+}
+
+void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HAL_UART_IRQHandler(&huart1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HAL_UART_IRQHandler(&hlpuart1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+        case hw_uart1:
+            HAL_DMA_IRQHandler(huart1.hdmatx);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+        case hw_lpuart1:
+            HAL_DMA_IRQHandler(hlpuart1.hdmatx);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+    switch ((uint32_t)huart->Instance)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case (uint32_t)USART1:
+            if(HW_huart1RxCb)
+            {
+                HW_huart1RxCb();
+            }
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case (uint32_t)LPUART1:
+            if(HW_hlpuart1RxCb)
+            {
+                HW_hlpuart1RxCb();
+            }
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+    switch ((uint32_t)huart->Instance)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case (uint32_t)USART1:
+            if(HW_huart1TxCb)
+            {
+                HW_huart1TxCb();
+            }
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case (uint32_t)LPUART1:
+            if(HW_hlpuart1TxCb)
+            {
+                HW_hlpuart1TxCb();
+            }
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/main.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/main.c
new file mode 100644
index 000000000..b4c3d4dd6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/main.c
@@ -0,0 +1,641 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    main.c
+ * @author  MCD Application Team
+ * @brief   BLE application with BLE core
+ *
+  @verbatim
+  ==============================================================================
+                    ##### IMPORTANT NOTE #####
+  ==============================================================================
+
+  This application requests having the stm32wb5x_BLE_Stack_fw.bin binary
+  flashed on the Wireless Coprocessor.
+  If it is not the case, you need to use STM32CubeProgrammer to load the appropriate
+  binary.
+
+  All available binaries are located under following directory:
+  /Projects/STM32_Copro_Wireless_Binaries
+
+  Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+  Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the
+  detailed procedure to change the Wireless Coprocessor binary.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "app_entry.h"
+#include "app_common.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "stm32_lpm.h"
+#include "stm32_seq.h"
+#include "dbg_trace.h"
+#include "hw_conf.h"
+#include "otp.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef hlpuart1;
+UART_HandleTypeDef huart1;
+DMA_HandleTypeDef hdma_lpuart1_tx;
+DMA_HandleTypeDef hdma_usart1_tx;
+
+RTC_HandleTypeDef hrtc;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+void MX_LPUART1_UART_Init(void);
+void MX_USART1_UART_Init(void);
+static void MX_RF_Init(void);
+static void MX_RTC_Init(void);
+/* USER CODE BEGIN PFP */
+void PeriphClock_Config(void);
+static void Reset_Device( void );
+static void Reset_IPCC( void );
+static void Reset_BackupDomain( void );
+static void Init_Exti( void );
+static void Config_HSE(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+  
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+  Reset_Device();
+  Config_HSE();
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  PeriphClock_Config();
+  Init_Exti(); /**< Configure the system Power Mode */
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_RF_Init();
+  MX_RTC_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Init code for STM32_WPAN */  
+  APPE_Init();
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+	while(1)
+	{
+		UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure LSE Drive Capability 
+  */
+  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE
+                              |RCC_OSCILLATORTYPE_LSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RFWAKEUP
+                              |RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1
+                              |RCC_PERIPHCLK_LPUART1;
+  PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+  PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* USER CODE BEGIN Smps */
+
+#if (CFG_USE_SMPS != 0)
+  /**
+   *  Configure and enable SMPS
+   *
+   *  The SMPS configuration is not yet supported by CubeMx
+   */
+  LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
+  LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
+  LL_PWR_SMPS_Enable();
+#endif
+
+  /* USER CODE END Smps */
+
+
+}
+
+/**
+  * @brief LPUART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+void MX_LPUART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN LPUART1_Init 0 */
+
+  /* USER CODE END LPUART1_Init 0 */
+
+  /* USER CODE BEGIN LPUART1_Init 1 */
+
+  /* USER CODE END LPUART1_Init 1 */
+  hlpuart1.Instance = LPUART1;
+  hlpuart1.Init.BaudRate = 115200;
+  hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
+  hlpuart1.Init.StopBits = UART_STOPBITS_1;
+  hlpuart1.Init.Parity = UART_PARITY_NONE;
+  hlpuart1.Init.Mode = UART_MODE_TX_RX;
+  hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  hlpuart1.FifoMode = UART_FIFOMODE_DISABLE;
+  if (HAL_UART_Init(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN LPUART1_Init 2 */
+
+  /* USER CODE END LPUART1_Init 2 */
+
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_8;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+  * @brief RF Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RF_Init(void)
+{
+
+  /* USER CODE BEGIN RF_Init 0 */
+
+  /* USER CODE END RF_Init 0 */
+
+  /* USER CODE BEGIN RF_Init 1 */
+
+  /* USER CODE END RF_Init 1 */
+  /* USER CODE BEGIN RF_Init 2 */
+
+  /* USER CODE END RF_Init 2 */
+
+}
+
+/**
+  * @brief RTC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RTC_Init(void)
+{
+
+  /* USER CODE BEGIN RTC_Init 0 */
+
+  /* USER CODE END RTC_Init 0 */
+
+  /* USER CODE BEGIN RTC_Init 1 */
+
+  /* USER CODE END RTC_Init 1 */
+  /** Initialize RTC Only 
+  */
+  hrtc.Instance = RTC;
+  hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
+  hrtc.Init.AsynchPrediv = CFG_RTC_ASYNCH_PRESCALER;
+  hrtc.Init.SynchPrediv = CFG_RTC_SYNCH_PRESCALER;
+  hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
+  hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+  hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+  if (HAL_RTC_Init(&hrtc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN RTC_Init 2 */
+  /* Disable RTC registers write protection */
+  LL_RTC_DisableWriteProtection(RTC);
+
+  LL_RTC_WAKEUP_SetClock(RTC, CFG_RTC_WUCKSEL_DIVIDER);
+
+  /* Enable RTC registers write protection */
+  LL_RTC_EnableWriteProtection(RTC);
+  /* USER CODE END RTC_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
+  __HAL_RCC_DMA2_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
+  /* DMA2_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA2_Channel4_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(DMA2_Channel4_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+void PeriphClock_Config(void)
+{
+  #if (CFG_USB_INTERFACE_ENABLE != 0)
+	RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
+	RCC_CRSInitTypeDef RCC_CRSInitStruct = { 0 };
+
+    /**
+    * This prevents the CPU2 to disable the HSI48 oscillator when
+    * it does not use anymore the RNG IP
+    */
+    LL_HSEM_1StepLock( HSEM, 5 );
+
+    LL_RCC_HSI48_Enable();
+
+	while(!LL_RCC_HSI48_IsReady());
+
+	/* Select HSI48 as USB clock source */
+	PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+	PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+	HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+	/*Configure the clock recovery system (CRS)**********************************/
+
+	/* Enable CRS Clock */
+	__HAL_RCC_CRS_CLK_ENABLE();
+
+	/* Default Synchro Signal division factor (not divided) */
+	RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+
+	/* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+	RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+
+	/* HSI48 is synchronized with USB SOF at 1KHz rate */
+	RCC_CRSInitStruct.ReloadValue = RCC_CRS_RELOADVALUE_DEFAULT;
+	RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+
+	RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+
+	/* Set the TRIM[5:0] to the default value*/
+	RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+
+	/* Start automatic synchronization */
+	HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+#endif
+
+	return;
+}
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+
+static void Config_HSE(void)
+{
+    OTP_ID0_t * p_otp;
+
+  /**
+   * Read HSE_Tuning from OTP
+   */
+  p_otp = (OTP_ID0_t *) OTP_Read(0);
+  if (p_otp)
+  {
+    LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
+  }
+
+  return;
+}  
+
+
+static void Reset_Device( void )
+{
+#if ( CFG_HW_RESET_BY_FW == 1 )
+	Reset_BackupDomain();
+
+	Reset_IPCC();
+#endif
+
+	return;
+}
+
+static void Reset_IPCC( void )
+{
+	LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
+
+	LL_C1_IPCC_ClearFlag_CHx(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_ClearFlag_CHx(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C1_IPCC_DisableTransmitChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_DisableTransmitChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C1_IPCC_DisableReceiveChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_DisableReceiveChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	return;
+}
+
+static void Reset_BackupDomain( void )
+{
+	if ((LL_RCC_IsActiveFlag_PINRST() != FALSE) && (LL_RCC_IsActiveFlag_SFTRST() == FALSE))
+	{
+		HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+		/**
+		 *  Write twice the value to flush the APB-AHB bridge
+		 *  This bit shall be written in the register before writing the next one
+		 */
+		HAL_PWR_EnableBkUpAccess();
+
+		__HAL_RCC_BACKUPRESET_FORCE();
+		__HAL_RCC_BACKUPRESET_RELEASE();
+	}
+
+	return;
+}
+
+static void Init_Exti( void )
+{
+  /**< Disable all wakeup interrupt on CPU1  except IPCC(36), HSEM(38) */
+  LL_EXTI_DisableIT_0_31(~0);
+  LL_EXTI_DisableIT_32_63( (~0) & (~(LL_EXTI_LINE_36 | LL_EXTI_LINE_38)) );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += HAL_GetTickFreq();
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+  {
+    /************************************************************************************
+     * ENTER SLEEP MODE
+     ***********************************************************************************/
+    LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+    /**
+     * This option is used to ensure that store operations are completed
+     */
+  #if defined ( __CC_ARM)
+    __force_stores();
+  #endif
+
+    __WFI( );
+  }
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/stm32_lpm_if.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/stm32_lpm_if.c
new file mode 100644
index 000000000..1418e0a36
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/stm32_lpm_if.c
@@ -0,0 +1,297 @@
+/* USER CODE BEGIN Header */
+/**
+ ***************************************************************************************
+  * File Name          : stm32_lpm_if.c
+  * Description        : Low layer function to enter/exit low power modes (stop, sleep).
+ ***************************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+  
+/* Includes ------------------------------------------------------------------*/  
+#include "stm32_lpm_if.h"
+#include "stm32_lpm.h"
+#include "app_conf.h"
+/* USER CODE BEGIN include */
+
+/* USER CODE END include */
+
+/* Exported variables --------------------------------------------------------*/
+const struct UTIL_LPM_Driver_s UTIL_PowerDriver = 
+{
+  PWR_EnterSleepMode,
+  PWR_ExitSleepMode,
+  
+  PWR_EnterStopMode,
+  PWR_ExitStopMode, 
+  
+  PWR_EnterOffMode,
+  PWR_ExitOffMode,
+};
+
+/* Private function prototypes -----------------------------------------------*/
+static void Switch_On_HSI( void );
+/* USER CODE BEGIN Private_Function_Prototypes */
+
+/* USER CODE END Private_Function_Prototypes */
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN Private_Typedef */
+
+/* USER CODE END Private_Typedef */
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Private_Define */
+
+/* USER CODE END Private_Define */
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Private_Macro */
+
+/* USER CODE END Private_Macro */
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN Private_Variables */
+
+/* USER CODE END Private_Variables */
+
+/* Functions Definition ------------------------------------------------------*/
+/**
+  * @brief Enters Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_EnterOffMode( void )
+{
+/* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
+  /************************************************************************************
+   * ENTER OFF MODE
+   ***********************************************************************************/
+  /*
+   * There is no risk to clear all the WUF here because in the current implementation, this API is called
+   * in critical section. If an interrupt occurs while in that critical section before that point,
+   * the flag is set and will be cleared here but the system will not enter Off Mode
+   * because an interrupt is pending in the NVIC. The ISR will be executed when moving out
+   * of this critical section
+   */
+  LL_PWR_ClearFlag_WU( );
+
+  LL_PWR_SetPowerMode( LL_PWR_MODE_STANDBY );
+
+  LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores( );
+#endif
+
+  __WFI( );
+/* USER CODE END PWR_EnterOffMode */
+}
+
+/**
+  * @brief Exits Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_ExitOffMode( void )
+{
+/* USER CODE BEGIN PWR_ExitOffMode */
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitOffMode */
+}
+
+/**
+  * @brief Enters Low Power Stop Mode
+  * @note ARM exists the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterStopMode( void )
+{
+/* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
+  /**
+   * This function is called from CRITICAL SECTION
+   */
+  while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
+
+  if ( ! LL_HSEM_1StepLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID ) )
+  {
+    if( LL_PWR_IsActiveFlag_C2DS( ) )
+    {
+      /* Release ENTRY_STOP_MODE semaphore */
+      LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
+
+      /**
+       * The switch on HSI before entering Stop Mode is required on Cut2.0
+       * It is useless from Cut2.1
+       */
+      Switch_On_HSI( );
+    }
+  }
+  else
+  {
+    /**
+     * The switch on HSI before entering Stop Mode is required on Cut2.0
+     * It is useless from Cut2.1
+     */
+    Switch_On_HSI( );
+  }
+
+  /* Release RCC semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  /************************************************************************************
+   * ENTER STOP MODE
+   ***********************************************************************************/
+  LL_PWR_SetPowerMode( LL_PWR_MODE_STOP2 );
+
+  LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores( );
+#endif
+
+  __WFI();
+/* USER CODE END PWR_EnterStopMode */
+}
+
+/**
+  * @brief Exits Low Power Stop Mode
+  * @note Enable the pll at 32MHz
+  * @param none
+  * @retval none
+  */
+void PWR_ExitStopMode( void )
+{
+/* USER CODE BEGIN PWR_ExitStopMode */
+  /**
+   * This function is called from CRITICAL SECTION
+   */
+
+  /* Release ENTRY_STOP_MODE semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
+
+  while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
+
+  if(LL_RCC_GetSysClkSource( ) == LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+    LL_RCC_HSE_Enable( );
+    while(!LL_RCC_HSE_IsReady( ));
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
+    while (LL_RCC_GetSysClkSource( ) != LL_RCC_SYS_CLKSOURCE_STATUS_HSE);
+  }
+  else
+  {
+    /**
+     * As long as the current application is fine with HSE as system clock source,
+     * there is nothing to do here
+     */
+  }
+
+  /* Release RCC semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitStopMode */
+}
+
+/**
+  * @brief Enters Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterSleepMode( void )
+{
+/* USER CODE BEGIN PWR_EnterSleepMode */
+
+  HAL_SuspendTick();
+
+  /************************************************************************************
+   * ENTER SLEEP MODE
+   ***********************************************************************************/
+  LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+
+  __WFI( );
+/* USER CODE END PWR_EnterSleepMode */
+}
+
+/**
+  * @brief Exits Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_ExitSleepMode( void )
+{
+/* USER CODE BEGIN PWR_ExitSleepMode */
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitSleepMode */
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+  * @brief Switch the system clock on HSI
+  * @param none
+  * @retval none
+  */
+static void Switch_On_HSI( void )
+{
+  LL_RCC_HSI_Enable( );
+  while(!LL_RCC_HSI_IsReady( ));
+  LL_RCC_SetSysClkSource( LL_RCC_SYS_CLKSOURCE_HSI );
+  LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSI);
+  while (LL_RCC_GetSysClkSource( ) != LL_RCC_SYS_CLKSOURCE_STATUS_HSI);
+}
+
+/* USER CODE BEGIN Private_Functions */
+
+/* USER CODE END Private_Functions */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..f22ad0f38
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,329 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32wbxx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_lpuart1_tx;
+
+extern DMA_HandleTypeDef hdma_usart1_tx;
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_HSEM_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  HAL_DMA_MuxSyncConfigTypeDef pSyncConfig;
+  if(huart->Instance==LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspInit 0 */
+
+  /* USER CODE END LPUART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_LPUART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**LPUART1 GPIO Configuration    
+    PA2     ------> LPUART1_TX
+    PA3     ------> LPUART1_RX
+    PA6     ------> LPUART1_CTS 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* LPUART1 DMA Init */
+    /* LPUART1_TX Init */
+    hdma_lpuart1_tx.Instance = DMA1_Channel4;
+    hdma_lpuart1_tx.Init.Request = DMA_REQUEST_LPUART1_TX;
+    hdma_lpuart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_lpuart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_lpuart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_lpuart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_lpuart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_lpuart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_lpuart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_lpuart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    pSyncConfig.SyncSignalID = HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT;
+    pSyncConfig.SyncPolarity = HAL_DMAMUX_SYNC_NO_EVENT;
+    pSyncConfig.SyncEnable = DISABLE;
+    pSyncConfig.EventEnable = DISABLE;
+    pSyncConfig.RequestNumber = 1;
+    if (HAL_DMAEx_ConfigMuxSync(&hdma_lpuart1_tx, &pSyncConfig) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmatx,hdma_lpuart1_tx);
+
+    /* LPUART1 interrupt Init */
+    HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(LPUART1_IRQn);
+  /* USER CODE BEGIN LPUART1_MspInit 1 */
+
+  /* USER CODE END LPUART1_MspInit 1 */
+  }
+  else if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspInit 0 */
+
+  /* USER CODE END USART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**USART1 GPIO Configuration    
+    PA11     ------> USART1_CTS
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_11;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* USART1 DMA Init */
+    /* USART1_TX Init */
+    hdma_usart1_tx.Instance = DMA2_Channel4;
+    hdma_usart1_tx.Init.Request = DMA_REQUEST_USART1_TX;
+    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx);
+
+    /* USART1 interrupt Init */
+    HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspInit 1 */
+
+  /* USER CODE END USART1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspDeInit 0 */
+
+  /* USER CODE END LPUART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_LPUART1_CLK_DISABLE();
+  
+    /**LPUART1 GPIO Configuration    
+    PA2     ------> LPUART1_TX
+    PA3     ------> LPUART1_RX
+    PA6     ------> LPUART1_CTS 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_6);
+
+    /* LPUART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmatx);
+
+    /* LPUART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(LPUART1_IRQn);
+  /* USER CODE BEGIN LPUART1_MspDeInit 1 */
+
+  /* USER CODE END LPUART1_MspDeInit 1 */
+  }
+  else if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+  /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+  
+    /**USART1 GPIO Configuration    
+    PA11     ------> USART1_CTS
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11);
+
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
+
+    /* USART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmatx);
+
+    /* USART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+  /* USER CODE END USART1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspInit 0 */
+  HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+  /**
+  *  Write twice the value to flush the APB-AHB bridge
+  *  This bit shall be written in the register before writing the next one
+  */
+  HAL_PWR_EnableBkUpAccess();
+
+  __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); /**< Select LSI as RTC Input */
+  /* USER CODE END RTC_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_RTC_ENABLE();
+  /* USER CODE BEGIN RTC_MspInit 1 */
+  HAL_RTCEx_EnableBypassShadow(hrtc);
+  /* USER CODE END RTC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspDeInit 0 */
+
+  /* USER CODE END RTC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RTC_DISABLE();
+  /* USER CODE BEGIN RTC_MspDeInit 1 */
+
+  /* USER CODE END RTC_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..f06353d51
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/stm32wbxx_it.c
@@ -0,0 +1,304 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_lpuart1_tx;
+extern DMA_HandleTypeDef hdma_usart1_tx;
+extern UART_HandleTypeDef hlpuart1;
+extern UART_HandleTypeDef huart1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles DMA1 channel4 global interrupt.
+  */
+void DMA1_Channel4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_lpuart1_tx);
+  /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel4_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+
+  /* USER CODE END USART1_IRQn 0 */
+  HAL_UART_IRQHandler(&huart1);
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles LPUART1 global interrupt.
+  */
+void LPUART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN LPUART1_IRQn 0 */
+
+  /* USER CODE END LPUART1_IRQn 0 */
+  HAL_UART_IRQHandler(&hlpuart1);
+  /* USER CODE BEGIN LPUART1_IRQn 1 */
+
+  /* USER CODE END LPUART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA2 channel4 global interrupt.
+  */
+void DMA2_Channel4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2_Channel4_IRQn 0 */
+
+  /* USER CODE END DMA2_Channel4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart1_tx);
+  /* USER CODE BEGIN DMA2_Channel4_IRQn 1 */
+
+  /* USER CODE END DMA2_Channel4_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW1_EXTI_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW2_EXTI_IRQHandler(void)
+{
+
+}
+
+void RTC_WKUP_IRQHandler(void)
+{
+  HW_TS_RTC_Wakeup_Handler();
+}
+
+void IPCC_C1_TX_IRQHandler(void)
+{
+  HW_IPCC_Tx_Handler();
+
+  return;
+}
+
+void IPCC_C1_RX_IRQHandler(void)
+{
+  HW_IPCC_Rx_Handler();
+  return;
+}
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..156ed20d3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/Core/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                        4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/BLE_p2pClient.ewd b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/BLE_p2pClient.ewd
new file mode 100644
index 000000000..5db29c471
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/BLE_p2pClient.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		BLE_p2pClient
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/BLE_p2pClient.ewp b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/BLE_p2pClient.ewp
new file mode 100644
index 000000000..b7cbdceb5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/BLE_p2pClient.ewp
@@ -0,0 +1,1248 @@
+
+
+    3
+    
+        BLE_p2pClient
+        
+            ARM
+        
+        1
+        
+            General
+            3
+            
+                30
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            ICCARM
+            2
+            
+                34
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            AARM
+            2
+            
+                10
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            OBJCOPY
+            0
+            
+                1
+                1
+                1
+                
+                
+                
+                
+                
+            
+        
+        
+            CUSTOM
+            3
+            
+                
+                
+                0
+            
+        
+        
+            BICOMP
+            0
+            
+        
+        
+            BUILDACTION
+            1
+            
+                
+                
+            
+        
+        
+            ILINK
+            0
+            
+                20
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            IARCHIVE
+            0
+            
+                0
+                1
+                1
+                
+                
+                
+            
+        
+        
+            BILINK
+            0
+            
+        
+    
+    
+        Application
+        
+            EWARM
+            
+                $PROJ_DIR$\startup_stm32wb35xx_cm4.s
+            
+        
+        
+            User
+            
+                Core
+                
+                    $PROJ_DIR$\..\Core\Src\app_entry.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\app_debug.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\hw_timerserver.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\hw_uart.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\main.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\stm32_lpm_if.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\stm32wbxx_hal_msp.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\stm32wbxx_it.c
+                
+            
+            
+                STM32_WPAN
+                
+                    App
+                    
+                        $PROJ_DIR$\..\STM32_WPAN\App\app_ble.c
+                    
+                    
+                        $PROJ_DIR$\..\STM32_WPAN\App\p2p_client_app.c
+                    
+                
+                
+                    Target
+                    
+                        $PROJ_DIR$\..\STM32_WPAN\Target\hw_ipcc.c
+                    
+                
+            
+        
+    
+    
+        Doc
+        
+            $PROJ_DIR$\..\readme.txt
+        
+    
+    
+        Drivers
+        
+            BSP
+            
+                NUCLEO-WB35CE
+                
+                    $PROJ_DIR$\..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE\nucleo_wb35ce.c
+                
+            
+        
+        
+            CMSIS
+            
+                $PROJ_DIR$\..\Core\Src\system_stm32wbxx.c
+            
+        
+        
+            STM32WBxx_HAL_Driver
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_cortex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_gpio.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_hsem.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_ipcc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rtc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rtc_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_uart.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_uart_ex.c
+            
+        
+    
+    
+        Middlewares
+        
+            STM32_WPAN
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_gap_aci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_gatt_aci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_hal_aci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_hci_le.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_l2cap_aci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\dbg_trace.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\hci_tl.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\hci_tl_if.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\template\osal.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\otp.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\shci\shci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\shci_tl.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\shci_tl_if.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\stm_list.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\stm_queue.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\svc\Src\svc_ctl.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\tl_mbox.c
+            
+        
+    
+    
+        Utilities
+        
+            $PROJ_DIR$\..\..\..\..\..\..\Utilities\lpm\tiny_lpm\stm32_lpm.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\..\..\Utilities\sequencer\stm32_seq.c
+        
+    
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/Project.eww
new file mode 100644
index 000000000..b3952cb75
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\BLE_p2pClient.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..8f3317a41
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/app_ble.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/app_ble.c
new file mode 100644
index 000000000..d030bbd9d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/app_ble.c
@@ -0,0 +1,1022 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    app_ble.c
+ * @author  MCD Application Team
+ * @brief   BLE Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "dbg_trace.h"
+
+#include "ble.h"
+#include "tl.h"
+#include "app_ble.h"
+
+#include "stm32_seq.h"
+#include "shci.h"
+#include "stm32_lpm.h"
+#include "otp.h"
+
+#include "p2p_client_app.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "main.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+
+/**
+ * security parameters structure
+ */
+typedef struct _tSecurityParams
+{
+/**
+ * IO capability of the device
+ */
+uint8_t ioCapability;
+
+/**
+ * Authentication requirement of the device
+ * Man In the Middle protection required?
+ */
+uint8_t mitm_mode;
+
+/**
+ * bonding mode of the device
+ */
+uint8_t bonding_mode;
+
+/**
+ * Flag to tell whether OOB data has
+ * to be used during the pairing process
+ */
+uint8_t OOB_Data_Present;
+
+/**
+ * OOB data to be used in the pairing process if
+ * OOB_Data_Present is set to TRUE
+ */
+uint8_t OOB_Data[16];
+
+/**
+ * this variable indicates whether to use a fixed pin
+ * during the pairing process or a passkey has to be
+ * requested to the application during the pairing process
+ * 0 implies use fixed pin and 1 implies request for passkey
+ */
+uint8_t Use_Fixed_Pin;
+
+/**
+ * minimum encryption key size requirement
+ */
+uint8_t encryptionKeySizeMin;
+
+/**
+ * maximum encryption key size requirement
+ */
+uint8_t encryptionKeySizeMax;
+
+/**
+ * fixed pin to be used in the pairing process if
+ * Use_Fixed_Pin is set to 1
+ */
+uint32_t Fixed_Pin;
+
+/**
+ * this flag indicates whether the host has to initiate
+ * the security, wait for pairing or does not have any security
+ * requirements.\n
+ * 0x00 : no security required
+ * 0x01 : host should initiate security by sending the slave security
+ *        request command
+ * 0x02 : host need not send the clave security request but it
+ * has to wait for paiirng to complete before doing any other
+ * processing
+ */
+uint8_t initiateSecurity;
+} tSecurityParams;
+
+/**
+ * global context
+ * contains the variables common to all
+ * services
+ */
+typedef struct _tBLEProfileGlobalContext
+{
+
+/**
+ * security requirements of the host
+ */
+tSecurityParams bleSecurityParam;
+
+/**
+ * gap service handle
+ */
+uint16_t gapServiceHandle;
+
+/**
+ * device name characteristic handle
+ */
+uint16_t devNameCharHandle;
+
+/**
+ * appearance characteristic handle
+ */
+uint16_t appearanceCharHandle;
+
+  /**
+   * connection handle of the current active connection
+   * When not in connection, the handle is set to 0xFFFF
+   */
+  uint16_t connectionHandle;
+
+/**
+ * length of the UUID list to be used while advertising
+ */
+uint8_t advtServUUIDlen;
+
+/**
+ * the UUID list to be used while advertising
+ */
+uint8_t advtServUUID[100];
+
+} BleGlobalContext_t;
+
+typedef struct
+{
+BleGlobalContext_t BleApplicationContext_legacy;
+APP_BLE_ConnStatus_t Device_Connection_Status;
+uint8_t SwitchOffGPIO_timer_Id;
+uint8_t DeviceServerFound;
+} BleApplicationContext_t;
+
+#if OOB_DEMO != 0
+typedef struct
+{
+  uint8_t  Identifier;
+  uint16_t L2CAP_Length;
+  uint16_t Interval_Min;
+  uint16_t Interval_Max;
+  uint16_t Slave_Latency;
+  uint16_t Timeout_Multiplier;
+} APP_BLE_p2p_Conn_Update_req_t;
+#endif 
+
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+#define APPBLE_GAP_DEVICE_NAME_LENGTH 7
+#define BD_ADDR_SIZE_LOCAL    6
+
+/* USER CODE BEGIN PD */
+#if OOB_DEMO != 0 
+#define LED_ON_TIMEOUT            (0.005*1000*1000/CFG_TS_TICK_VAL) /**< 5ms */
+#endif 
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static TL_CmdPacket_t BleCmdBuffer;
+
+static const uint8_t M_bd_addr[BD_ADDR_SIZE_LOCAL] =
+    {
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x0000000000FF)),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x00000000FF00) >> 8),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x000000FF0000) >> 16),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x0000FF000000) >> 24),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x00FF00000000) >> 32),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0xFF0000000000) >> 40)
+    };
+
+static uint8_t bd_addr_udn[BD_ADDR_SIZE_LOCAL];
+
+/**
+*   Identity root key used to derive LTK and CSRK 
+*/
+static const uint8_t BLE_CFG_IR_VALUE[16] = CFG_BLE_IRK;
+
+/**
+* Encryption root key used to derive LTK and CSRK
+*/
+static const uint8_t BLE_CFG_ER_VALUE[16] = CFG_BLE_ERK;
+
+tBDAddr SERVER_REMOTE_BDADDR;
+
+P2PC_APP_ConnHandle_Not_evt_t handleNotification;
+
+PLACE_IN_SECTION("BLE_APP_CONTEXT") static BleApplicationContext_t BleApplicationContext;
+
+#if OOB_DEMO != 0
+APP_BLE_p2p_Conn_Update_req_t APP_BLE_p2p_Conn_Update_req;
+#endif
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+static void BLE_UserEvtRx( void * pPayload );
+static void BLE_StatusNot( HCI_TL_CmdStatus_t status );
+static void Ble_Tl_Init( void );
+static void Ble_Hci_Gap_Gatt_Init(void);
+static const uint8_t* BleGetBdAddress( void );
+static void Scan_Request( void );
+static void Connect_Request( void );
+static void Switch_OFF_GPIO( void );
+ 
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* Functions Definition ------------------------------------------------------*/
+void APP_BLE_Init( void )
+{
+/* USER CODE BEGIN APP_BLE_Init_1 */
+
+/* USER CODE END APP_BLE_Init_1 */
+  SHCI_C2_Ble_Init_Cmd_Packet_t ble_init_cmd_packet =
+  {
+    {{0,0,0}},                          /**< Header unused */
+    {0,                                 /** pBleBufferAddress not used */
+    0,                                  /** BleBufferSize not used */
+    CFG_BLE_NUM_GATT_ATTRIBUTES,
+    CFG_BLE_NUM_GATT_SERVICES,
+    CFG_BLE_ATT_VALUE_ARRAY_SIZE,
+    CFG_BLE_NUM_LINK,
+    CFG_BLE_DATA_LENGTH_EXTENSION,
+    CFG_BLE_PREPARE_WRITE_LIST_SIZE,
+    CFG_BLE_MBLOCK_COUNT,
+    CFG_BLE_MAX_ATT_MTU,
+    CFG_BLE_SLAVE_SCA,
+    CFG_BLE_MASTER_SCA,
+    CFG_BLE_LSE_SOURCE,
+    CFG_BLE_MAX_CONN_EVENT_LENGTH,
+    CFG_BLE_HSE_STARTUP_TIME,
+    CFG_BLE_VITERBI_MODE,
+    CFG_BLE_LL_ONLY,
+    0}
+  };
+
+  /**
+   * Initialize Ble Transport Layer
+   */
+  Ble_Tl_Init( );
+
+  /**
+   * Do not allow standby in the application
+   */
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP_BLE, UTIL_LPM_DISABLE);
+
+/**
+   * Register the hci transport layer to handle BLE User Asynchronous Events
+   */
+  UTIL_SEQ_RegTask( 1<data;
+  hci_disconnection_complete_event_rp0 *cc = (void *) event_pckt->data;
+  uint8_t result;
+  uint8_t event_type, event_data_size;
+  int k = 0;
+  uint8_t adtype, adlength;
+
+  switch (event_pckt->evt)
+  {
+    /* USER CODE BEGIN evt */
+
+    /* USER CODE END evt */
+    case EVT_VENDOR:
+    {
+      handleNotification.P2P_Evt_Opcode = PEER_DISCON_HANDLE_EVT;
+      blue_evt = (evt_blue_aci*) event_pckt->data;
+      /* USER CODE BEGIN EVT_VENDOR */
+
+      /* USER CODE END EVT_VENDOR */
+      switch (blue_evt->ecode)
+      {
+      /* USER CODE BEGIN ecode */
+
+      /* USER CODE END ecode */
+
+        case EVT_BLUE_GAP_PROCEDURE_COMPLETE:
+        {
+        /* USER CODE BEGIN EVT_BLUE_GAP_PROCEDURE_COMPLETE */
+
+        /* USER CODE END EVT_BLUE_GAP_PROCEDURE_COMPLETE */
+          aci_gap_proc_complete_event_rp0 *gap_evt_proc_complete = (void*) blue_evt->data;
+          /* CHECK GAP GENERAL DISCOVERY PROCEDURE COMPLETED & SUCCEED */
+          if (gap_evt_proc_complete->Procedure_Code == GAP_GENERAL_DISCOVERY_PROC
+              && gap_evt_proc_complete->Status == 0x00)
+          {
+            /* USER CODE BEGIN GAP_GENERAL_DISCOVERY_PROC */
+            BSP_LED_Off(LED_BLUE);
+            /* USER CODE END GAP_GENERAL_DISCOVERY_PROC */
+            APP_DBG_MSG("-- GAP GENERAL DISCOVERY PROCEDURE_COMPLETED\n");
+            /*if a device found, connect to it, device 1 being chosen first if both found*/
+            if (BleApplicationContext.DeviceServerFound == 0x01 && BleApplicationContext.Device_Connection_Status != APP_BLE_CONNECTED_CLIENT)
+            {
+              UTIL_SEQ_SetTask(1 << CFG_TASK_CONN_DEV_1_ID, CFG_SCH_PRIO_0);
+            }
+          }
+        }
+        break;
+#if (OOB_DEMO != 0)
+        case EVT_BLUE_L2CAP_CONNECTION_UPDATE_REQ: 
+        {
+          /* USER CODE BEGIN EVT_BLUE_L2CAP_CONNECTION_UPDATE_REQ */
+
+          /* USER CODE END EVT_BLUE_L2CAP_CONNECTION_UPDATE_REQ */
+          aci_l2cap_connection_update_req_event_rp0 *pr = (aci_l2cap_connection_update_req_event_rp0 *) blue_evt->data;
+          aci_hal_set_radio_activity_mask(0x0000);
+          APP_BLE_p2p_Conn_Update_req.Identifier = pr->Identifier;
+          APP_BLE_p2p_Conn_Update_req.L2CAP_Length = pr->L2CAP_Length;
+          APP_BLE_p2p_Conn_Update_req.Interval_Min = pr->Interval_Min;
+          APP_BLE_p2p_Conn_Update_req.Interval_Max = pr->Interval_Max;
+          APP_BLE_p2p_Conn_Update_req.Slave_Latency = pr->Slave_Latency;
+          APP_BLE_p2p_Conn_Update_req.Timeout_Multiplier = pr->Timeout_Multiplier;
+            
+          result = aci_l2cap_connection_parameter_update_resp(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,
+                                                           APP_BLE_p2p_Conn_Update_req.Interval_Min,
+                                                           APP_BLE_p2p_Conn_Update_req.Interval_Max,
+                                                           APP_BLE_p2p_Conn_Update_req.Slave_Latency,
+                                                           APP_BLE_p2p_Conn_Update_req.Timeout_Multiplier,
+                                                           CONN_L1,
+                                                           CONN_L2,
+                                                           APP_BLE_p2p_Conn_Update_req.Identifier,
+                                                           0x01);
+          if(result != BLE_STATUS_SUCCESS) {
+              /* USER CODE BEGIN BLE_STATUS_SUCCESS */
+              BSP_LED_On(LED_RED);
+              /* USER CODE END BLE_STATUS_SUCCESS */
+          }
+          aci_hal_set_radio_activity_mask(0x0020);
+          
+        } 
+        
+        break;
+        
+        case 0x0004:
+        {
+          /* USER CODE BEGIN RADIO_ACTIVITY_EVENT */
+          BSP_LED_On(LED_GREEN);
+          HW_TS_Start(BleApplicationContext.SwitchOffGPIO_timer_Id, (uint32_t)LED_ON_TIMEOUT);
+          /* USER CODE END RADIO_ACTIVITY_EVENT */
+        }
+        break; 
+#endif 
+        default:
+          /* USER CODE BEGIN ecode_default */
+
+          /* USER CODE END ecode_default */
+          break;
+       
+      }
+    }
+    break; 
+
+    case EVT_DISCONN_COMPLETE:
+      {
+      /* USER CODE BEGIN EVT_DISCONN_COMPLETE */
+
+      /* USER CODE END EVT_DISCONN_COMPLETE */
+      if (cc->Connection_Handle == BleApplicationContext.BleApplicationContext_legacy.connectionHandle)
+          {
+            BleApplicationContext.BleApplicationContext_legacy.connectionHandle = 0;
+            BleApplicationContext.Device_Connection_Status = APP_BLE_IDLE;
+            APP_DBG_MSG("\r\n\r** DISCONNECTION EVENT WITH SERVER \n");
+            handleNotification.P2P_Evt_Opcode = PEER_DISCON_HANDLE_EVT;
+            handleNotification.ConnectionHandle = BleApplicationContext.BleApplicationContext_legacy.connectionHandle;
+            P2PC_APP_Notification(&handleNotification);
+          }
+       }
+      break; /* EVT_DISCONN_COMPLETE */
+
+    case EVT_LE_META_EVENT:
+    {
+      /* USER CODE BEGIN EVT_LE_META_EVENT */
+
+      /* USER CODE END EVT_LE_META_EVENT */
+      meta_evt = (evt_le_meta_event*) event_pckt->data;
+
+      switch (meta_evt->subevent)
+      {
+      /* USER CODE BEGIN subevent */
+
+      /* USER CODE END subevent */
+          case EVT_LE_CONN_COMPLETE:
+          /* USER CODE BEGIN EVT_LE_CONN_COMPLETE */
+
+          /* USER CODE END EVT_LE_CONN_COMPLETE */
+          /**
+           * The connection is done, 
+           */
+          connection_complete_event = (hci_le_connection_complete_event_rp0 *) meta_evt->data;
+          BleApplicationContext.BleApplicationContext_legacy.connectionHandle = connection_complete_event->Connection_Handle;
+          BleApplicationContext.Device_Connection_Status = APP_BLE_CONNECTED_CLIENT;
+
+          /* CONNECTION WITH CLIENT */
+          APP_DBG_MSG("\r\n\r** CONNECTION EVENT WITH SERVER \n");
+          handleNotification.P2P_Evt_Opcode = PEER_CONN_HANDLE_EVT;
+          handleNotification.ConnectionHandle = BleApplicationContext.BleApplicationContext_legacy.connectionHandle;
+          P2PC_APP_Notification(&handleNotification);
+
+          result = aci_gatt_disc_all_primary_services(BleApplicationContext.BleApplicationContext_legacy.connectionHandle);
+          if (result == BLE_STATUS_SUCCESS)
+          {
+            APP_DBG_MSG("\r\n\r** GATT SERVICES & CHARACTERISTICS DISCOVERY  \n");
+            APP_DBG_MSG("* GATT :  Start Searching Primary Services \r\n\r");
+          }
+          else
+          {
+            APP_DBG_MSG("BLE_CTRL_App_Notification(), All services discovery Failed \r\n\r");
+          }
+
+          break; /* HCI_EVT_LE_CONN_COMPLETE */
+
+        case EVT_LE_ADVERTISING_REPORT:
+        {
+          uint8_t *adv_report_data;
+          /* USER CODE BEGIN EVT_LE_ADVERTISING_REPORT */
+
+          /* USER CODE END EVT_LE_ADVERTISING_REPORT */
+          le_advertising_event = (hci_le_advertising_report_event_rp0 *) meta_evt->data;
+
+          event_type = le_advertising_event->Advertising_Report[0].Event_Type;
+
+          event_data_size = le_advertising_event->Advertising_Report[0].Length_Data;
+
+          /* WARNING: be careful when decoding advertising report as its raw format cannot be mapped on a C structure. 
+          The data and RSSI values could not be directly decoded from the RAM using the data and RSSI field from hci_le_advertising_report_event_rp0 structure.
+          Instead they must be read by using offsets (please refer to BLE specification).
+          RSSI = *(uint8_t*) (adv_report_data + le_advertising_event->Advertising_Report[0].Length_Data);
+          */
+          adv_report_data = (uint8_t*)(&le_advertising_event->Advertising_Report[0].Length_Data) + 1;
+          k = 0;
+
+          /* search AD TYPE 0x09 (Complete Local Name) */
+          /* search AD Type 0x02 (16 bits UUIDS) */
+          if (event_type == ADV_IND)
+          {
+
+            /* ISOLATION OF BD ADDRESS AND LOCAL NAME */
+
+            while(k < event_data_size)
+            {
+              adlength = adv_report_data[k];
+              adtype = adv_report_data[k + 1];
+              switch (adtype)
+              {
+                case AD_TYPE_FLAGS: /* now get flags */
+                /* USER CODE BEGIN AD_TYPE_FLAGS */
+
+                /* USER CODE END AD_TYPE_FLAGS */
+                  break;
+
+                case AD_TYPE_TX_POWER_LEVEL: /* Tx power level */
+                /* USER CODE BEGIN AD_TYPE_TX_POWER_LEVEL */
+
+                /* USER CODE END AD_TYPE_TX_POWER_LEVEL */
+                break;
+                case AD_TYPE_MANUFACTURER_SPECIFIC_DATA: /* Manufacturer Specific */
+                /* USER CODE BEGIN AD_TYPE_MANUFACTURER_SPECIFIC_DATA */
+
+                /* USER CODE END AD_TYPE_MANUFACTURER_SPECIFIC_DATA */
+                  if (adlength >= 7 && adv_report_data[k + 2] == 0x01)
+                  { /* ST VERSION ID 01 */
+                    APP_DBG_MSG("--- ST MANUFACTURER ID --- \n");
+                    switch (adv_report_data[k + 3])
+                    {   /* Demo ID */
+			          case CFG_DEV_ID_P2P_SERVER1: /* (0End Device 1) */
+                        APP_DBG_MSG("-- SERVER DETECTED -- VIA MAN ID\n");
+                        BleApplicationContext.DeviceServerFound = 0x01;
+                        SERVER_REMOTE_BDADDR[0] = le_advertising_event->Advertising_Report[0].Address[0];
+                        SERVER_REMOTE_BDADDR[1] = le_advertising_event->Advertising_Report[0].Address[1];
+                        SERVER_REMOTE_BDADDR[2] = le_advertising_event->Advertising_Report[0].Address[2];
+                        SERVER_REMOTE_BDADDR[3] = le_advertising_event->Advertising_Report[0].Address[3];
+                        SERVER_REMOTE_BDADDR[4] = le_advertising_event->Advertising_Report[0].Address[4];
+                        SERVER_REMOTE_BDADDR[5] = le_advertising_event->Advertising_Report[0].Address[5];
+                        break;
+
+                      default:
+                        break;
+                    }
+
+                  }
+                  break;
+                case AD_TYPE_SERVICE_DATA: /* service data 16 bits */
+                  /* USER CODE BEGIN AD_TYPE_SERVICE_DATA */
+
+                  /* USER CODE END AD_TYPE_SERVICE_DATA */
+                  break;
+                default:
+                  /* USER CODE BEGIN adtype_default */
+
+                  /* USER CODE END adtype_default */
+                  break;
+              } /* end switch Data[k+adlength] */
+              k += adlength + 1;
+            } /* end while */
+
+          } /* end if ADV_IND */
+        }
+
+          break;
+
+        default:
+          /* USER CODE BEGIN subevent_default */
+
+          /* USER CODE END subevent_default */
+          break;
+
+      }
+    }
+    break; /* HCI_EVT_LE_META_EVENT */
+
+    default:
+      /* USER CODE BEGIN evt_default */
+
+      /* USER CODE END evt_default */
+      break;
+  }
+
+  return (SVCCTL_UserEvtFlowEnable);
+}
+
+APP_BLE_ConnStatus_t APP_BLE_Get_Client_Connection_Status( uint16_t Connection_Handle )
+{
+
+  if (BleApplicationContext.BleApplicationContext_legacy.connectionHandle == Connection_Handle)
+  {
+    return BleApplicationContext.Device_Connection_Status;
+  }
+  return APP_BLE_IDLE;
+}
+/* USER CODE BEGIN FD */
+void APP_BLE_Key_Button1_Action(void)
+{
+#if OOB_DEMO == 0 
+      P2PC_APP_SW1_Button_Action();
+#else 
+      if(P2P_Client_APP_Get_State () != APP_BLE_CONNECTED_CLIENT)
+      {
+        UTIL_SEQ_SetTask(1 << CFG_TASK_START_SCAN_ID, CFG_SCH_PRIO_0);
+      }
+      else 
+      {
+        P2PC_APP_SW1_Button_Action();
+      }   
+#endif 
+}
+
+void APP_BLE_Key_Button2_Action(void)
+{
+}
+
+void APP_BLE_Key_Button3_Action(void)
+{
+}
+/* USER CODE END FD */
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void Ble_Tl_Init( void )
+{
+  HCI_TL_HciInitConf_t Hci_Tl_Init_Conf;
+
+  Hci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&BleCmdBuffer;
+  Hci_Tl_Init_Conf.StatusNotCallBack = BLE_StatusNot;
+  hci_init(BLE_UserEvtRx, (void*) &Hci_Tl_Init_Conf);
+
+  return;
+}
+
+ static void Ble_Hci_Gap_Gatt_Init(void){
+ 
+  uint8_t role;
+  uint8_t index;
+  uint16_t gap_service_handle, gap_dev_name_char_handle, gap_appearance_char_handle;
+  const uint8_t *bd_addr;
+  uint32_t srd_bd_addr[2];
+  uint16_t appearance[1] = { BLE_CFG_GAP_APPEARANCE }; 
+  
+  /**
+   * Initialize HCI layer
+   */
+  /*HCI Reset to synchronise BLE Stack*/
+   hci_reset();
+  
+   /**
+   * Write the BD Address
+   */
+ 
+  bd_addr = BleGetBdAddress();
+  aci_hal_write_config_data(CONFIG_DATA_PUBADDR_OFFSET,
+                            CONFIG_DATA_PUBADDR_LEN,
+                            (uint8_t*) bd_addr);
+
+  /**
+   * Static random Address
+   * The two upper bits shall be set to 1
+   * The lowest 32bits is read from the UDN to differentiate between devices
+   * The RNG may be used to provide a random number on each power on
+   */
+  srd_bd_addr[1] =  0x0000ED6E;
+  srd_bd_addr[0] =  LL_FLASH_GetUDN( );
+  aci_hal_write_config_data( CONFIG_DATA_RANDOM_ADDRESS_OFFSET, CONFIG_DATA_RANDOM_ADDRESS_LEN, (uint8_t*)srd_bd_addr );
+
+  /**
+   * Write Identity root key used to derive LTK and CSRK 
+   */
+    aci_hal_write_config_data( CONFIG_DATA_IR_OFFSET, CONFIG_DATA_IR_LEN, (uint8_t*)BLE_CFG_IR_VALUE );
+    
+   /**
+   * Write Encryption root key used to derive LTK and CSRK
+   */
+    aci_hal_write_config_data( CONFIG_DATA_ER_OFFSET, CONFIG_DATA_ER_LEN, (uint8_t*)BLE_CFG_ER_VALUE );
+  
+  /**
+     * Set TX Power to 0dBm.
+     */
+    aci_hal_set_tx_power_level(1, CFG_TX_POWER);
+  
+/**
+   * Initialize GATT interface
+   */
+  aci_gatt_init();
+
+  /**
+   * Initialize GAP interface
+   */
+  role = 0;
+
+#if (BLE_CFG_PERIPHERAL == 1)
+  role |= GAP_PERIPHERAL_ROLE;
+#endif
+
+#if (BLE_CFG_CENTRAL == 1)
+  role |= GAP_CENTRAL_ROLE;
+#endif
+
+  if (role > 0)
+  {
+    const char *name = "STM32WB";
+
+    aci_gap_init(role, 0,
+                 APPBLE_GAP_DEVICE_NAME_LENGTH,
+                 &gap_service_handle, &gap_dev_name_char_handle, &gap_appearance_char_handle);
+
+    if (aci_gatt_update_char_value(gap_service_handle, gap_dev_name_char_handle, 0, strlen(name), (uint8_t *) name))
+    {
+      BLE_DBG_SVCCTL_MSG("Device Name aci_gatt_update_char_value failed.\n");
+    }
+  }
+
+    if(aci_gatt_update_char_value(gap_service_handle,
+                                  gap_appearance_char_handle,
+                                  0,
+                                  2,
+                                 (uint8_t *)&appearance))
+    {
+      BLE_DBG_SVCCTL_MSG("Appearance aci_gatt_update_char_value failed.\n");
+    }
+
+    /**
+     * Initialize IO capability
+     */
+    BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.ioCapability = CFG_IO_CAPABILITY;
+    aci_gap_set_io_capability(BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.ioCapability);
+
+    /**
+     * Initialize authentication
+     */
+    BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode = CFG_MITM_PROTECTION;
+    BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data_Present = 0;
+    BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin = 8;
+    BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax = 16;
+    BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin = 1;
+    BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin = 111111;
+    BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode = 1;
+    for (index = 0; index < 16; index++)
+    {
+      BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data[index] = (uint8_t) index;
+    }
+
+    aci_gap_set_authentication_requirement(BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode,
+                                           BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode,
+                                           1,
+                                           0,
+                                           BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin,
+                                           BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax,
+                                           BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin,
+                                           BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin,
+                                           0
+                                           );
+
+    /**
+     * Initialize whitelist
+     */
+    if (BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode)
+    {
+      aci_gap_configure_whitelist();
+    }
+  
+}
+
+static void Scan_Request( void )
+{
+  /* USER CODE BEGIN Scan_Request_1 */
+
+  /* USER CODE END Scan_Request_1 */
+  tBleStatus result;
+  if (BleApplicationContext.Device_Connection_Status != APP_BLE_CONNECTED_CLIENT)
+  {
+    /* USER CODE BEGIN APP_BLE_CONNECTED_CLIENT */
+    BSP_LED_On(LED_BLUE);
+    /* USER CODE END APP_BLE_CONNECTED_CLIENT */
+    result = aci_gap_start_general_discovery_proc(SCAN_P, SCAN_L, PUBLIC_ADDR, 1);
+    if (result == BLE_STATUS_SUCCESS)
+    {
+    /* USER CODE BEGIN BLE_SCAN_SUCCESS */
+
+    /* USER CODE END BLE_SCAN_SUCCESS */
+      APP_DBG_MSG(" \r\n\r** START GENERAL DISCOVERY (SCAN) **  \r\n\r");
+    }
+    else
+    {
+    /* USER CODE BEGIN BLE_SCAN_FAILED */
+      BSP_LED_On(LED_RED);
+    /* USER CODE END BLE_SCAN_FAILED */
+      APP_DBG_MSG("-- BLE_App_Start_Limited_Disc_Req, Failed \r\n\r");
+    }
+  }
+  /* USER CODE BEGIN Scan_Request_2 */
+
+  /* USER CODE END Scan_Request_2 */
+  return;
+}
+
+static void Connect_Request( void )
+{
+  /* USER CODE BEGIN Connect_Request_1 */
+
+  /* USER CODE END Connect_Request_1 */
+  tBleStatus result;
+  
+  APP_DBG_MSG("\r\n\r** CREATE CONNECTION TO SERVER **  \r\n\r");
+
+  if (BleApplicationContext.Device_Connection_Status != APP_BLE_CONNECTED_CLIENT)
+  {
+    result = aci_gap_create_connection(SCAN_P,
+    SCAN_L,
+                                       PUBLIC_ADDR, SERVER_REMOTE_BDADDR,
+                                       PUBLIC_ADDR,
+                                       CONN_P1,
+                                       CONN_P2,
+                                       0,
+                                       SUPERV_TIMEOUT,
+                                       CONN_L1,
+                                       CONN_L2);
+
+    if (result == BLE_STATUS_SUCCESS)
+    {
+    /* USER CODE BEGIN BLE_CONNECT_SUCCESS */
+
+    /* USER CODE END BLE_CONNECT_SUCCESS */
+    BleApplicationContext.Device_Connection_Status = APP_BLE_LP_CONNECTING;
+
+    }
+    else
+    {
+    /* USER CODE BEGIN BLE_CONNECT_FAILED */
+      BSP_LED_On(LED_RED);
+    /* USER CODE END BLE_CONNECT_FAILED */
+      BleApplicationContext.Device_Connection_Status = APP_BLE_IDLE;
+
+    }
+  }
+  /* USER CODE BEGIN Connect_Request_2 */
+
+  /* USER CODE END Connect_Request_2 */
+  return;
+}
+
+static void Switch_OFF_GPIO(){
+/* USER CODE BEGIN Switch_OFF_GPIO */
+  BSP_LED_Off(LED_GREEN);
+/* USER CODE END Switch_OFF_GPIO */
+}
+
+const uint8_t* BleGetBdAddress( void )
+{
+  uint8_t *otp_addr;
+  const uint8_t *bd_addr;
+  uint32_t udn;
+  uint32_t company_id;
+  uint32_t device_id;
+
+  udn = LL_FLASH_GetUDN();
+
+  if(udn != 0xFFFFFFFF)
+  {
+    company_id = LL_FLASH_GetSTCompanyID();
+    device_id = LL_FLASH_GetDeviceID();
+
+    bd_addr_udn[0] = (uint8_t)(udn & 0x000000FF);
+    bd_addr_udn[1] = (uint8_t)( (udn & 0x0000FF00) >> 8 );
+    bd_addr_udn[2] = (uint8_t)( (udn & 0x00FF0000) >> 16 );
+    bd_addr_udn[3] = (uint8_t)device_id;
+    bd_addr_udn[4] = (uint8_t)(company_id & 0x000000FF);;
+    bd_addr_udn[5] = (uint8_t)( (company_id & 0x0000FF00) >> 8 );
+
+    bd_addr = (const uint8_t *)bd_addr_udn;
+  }
+  else
+  {
+    otp_addr = OTP_Read(0);
+    if(otp_addr)
+    {
+      bd_addr = ((OTP_ID0_t*)otp_addr)->bd_address;
+    }
+    else
+    {
+      bd_addr = M_bd_addr;
+    }
+
+  }
+
+  return bd_addr;
+}
+/* USER CODE BEGIN FD_LOCAL_FUNCTIONS */
+
+/* USER CODE END FD_LOCAL_FUNCTIONS */
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+void hci_notify_asynch_evt(void* pdata)
+{
+  UTIL_SEQ_SetTask(1 << CFG_TASK_HCI_ASYNCH_EVT_ID, CFG_SCH_PRIO_0);
+  return;
+}
+
+void hci_cmd_resp_release(uint32_t flag)
+{
+  UTIL_SEQ_SetEvt(1 << CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID);
+  return;
+}
+
+void hci_cmd_resp_wait(uint32_t timeout)
+{
+  UTIL_SEQ_WaitEvt(1 << CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID);
+  return;
+}
+
+static void BLE_UserEvtRx( void * pPayload )
+{
+  SVCCTL_UserEvtFlowStatus_t svctl_return_status;
+  tHCI_UserEvtRxParam *pParam;
+
+  pParam = (tHCI_UserEvtRxParam *)pPayload; 
+  
+  svctl_return_status = SVCCTL_UserEvtRx((void *)&(pParam->pckt->evtserial));
+  if (svctl_return_status != SVCCTL_UserEvtFlowDisable)
+{
+    pParam->status = HCI_TL_UserEventFlow_Enable;
+}
+  else
+{
+    pParam->status = HCI_TL_UserEventFlow_Disable;
+  }
+}
+
+static void BLE_StatusNot( HCI_TL_CmdStatus_t status )
+{
+  uint32_t task_id_list;
+  switch (status)
+  {
+    case HCI_TL_CmdBusy:
+      /**
+       * All tasks that may send an aci/hci commands shall be listed here
+       * This is to prevent a new command is sent while one is already pending
+       */
+      task_id_list = (1 << CFG_LAST_TASK_ID_WITH_HCICMD) - 1;
+      UTIL_SEQ_PauseTask(task_id_list);
+
+      break;
+
+    case HCI_TL_CmdAvailable:
+      /**
+       * All tasks that may send an aci/hci commands shall be listed here
+       * This is to prevent a new command is sent while one is already pending
+       */
+      task_id_list = (1 << CFG_LAST_TASK_ID_WITH_HCICMD) - 1;
+      UTIL_SEQ_ResumeTask(task_id_list);
+
+      break;
+
+    default:
+      break;
+  }
+  return;
+}
+
+void SVCCTL_ResumeUserEventFlow( void )
+{
+  hci_resume_flow();
+  return;
+}
+
+/* USER CODE BEGIN FD_WRAP_FUNCTIONS */
+
+/* USER CODE END FD_WRAP_FUNCTIONS */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/app_ble.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/app_ble.h
new file mode 100644
index 000000000..bf56b6f24
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/app_ble.h
@@ -0,0 +1,94 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    app_ble.h
+  * @author  MCD Application Team
+  * @brief   Header for ble application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_BLE_H
+#define APP_BLE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "hci_tl.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+
+    typedef enum
+    {
+      APP_BLE_IDLE,
+      APP_BLE_FAST_ADV,
+      APP_BLE_LP_ADV,
+      APP_BLE_SCAN,
+      APP_BLE_LP_CONNECTING,
+      APP_BLE_CONNECTED_SERVER,
+      APP_BLE_CONNECTED_CLIENT,
+      
+      APP_BLE_DISCOVER_SERVICES,
+      APP_BLE_DISCOVER_CHARACS,
+      APP_BLE_DISCOVER_WRITE_DESC,
+      APP_BLE_DISCOVER_NOTIFICATION_CHAR_DESC,
+      APP_BLE_ENABLE_NOTIFICATION_DESC,
+      APP_BLE_DISABLE_NOTIFICATION_DESC
+    } APP_BLE_ConnStatus_t;
+
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */  
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APP_BLE_Init( void ); 
+
+  APP_BLE_ConnStatus_t APP_BLE_Get_Client_Connection_Status( uint16_t Connection_Handle );
+
+/* USER CODE BEGIN EF */
+  void APP_BLE_Key_Button1_Action(void);
+  void APP_BLE_Key_Button2_Action(void);
+  void APP_BLE_Key_Button3_Action(void);
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*APP_BLE_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/ble_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/ble_conf.h
new file mode 100644
index 000000000..82d851668
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/ble_conf.h
@@ -0,0 +1,65 @@
+/**
+ ******************************************************************************
+  * File Name          : App/ble_conf.h
+  * Description        : Configuration file for BLE Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef BLE_CONF_H
+#define BLE_CONF_H
+
+#include "app_conf.h"
+
+/******************************************************************************
+ *
+ * BLE SERVICES CONFIGURATION
+ * blesvc
+ *
+ ******************************************************************************/
+
+ /**
+ * This setting shall be set to '1' if the device needs to support the Peripheral Role
+ * In the MS configuration, both BLE_CFG_PERIPHERAL and BLE_CFG_CENTRAL shall be set to '1'
+ */
+#define BLE_CFG_PERIPHERAL                                                     0
+
+/**
+ * This setting shall be set to '1' if the device needs to support the Central Role
+ * In the MS configuration, both BLE_CFG_PERIPHERAL and BLE_CFG_CENTRAL shall be set to '1'
+ */
+#define BLE_CFG_CENTRAL                                                        1
+
+/**
+ * There is one handler per service enabled
+ * Note: There is no handler for the Device Information Service
+ *
+ * This shall take into account all registered handlers
+ * (from either the provided services or the custom services)
+ */
+#define BLE_CFG_SVC_MAX_NBR_CB                                                 7
+
+#define BLE_CFG_CLT_MAX_NBR_CB                                                 1
+
+/******************************************************************************
+ * GAP Service - Apprearance
+ ******************************************************************************/
+
+#define BLE_CFG_UNKNOWN_APPEARANCE                  (0)
+#define BLE_CFG_HR_SENSOR_APPEARANCE                (832)
+#define BLE_CFG_GAP_APPEARANCE                      (BLE_CFG_UNKNOWN_APPEARANCE)
+
+#endif /*BLE_CONF_H */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/ble_dbg_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/ble_dbg_conf.h
new file mode 100644
index 000000000..1f9b21135
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/ble_dbg_conf.h
@@ -0,0 +1,199 @@
+/**
+ ******************************************************************************
+  * File Name          : App/ble_dbg_conf.h
+  * Description        : Debug configuration file for BLE Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __BLE_DBG_CONF_H
+#define __BLE_DBG_CONF_H
+
+/**
+ * Enable or Disable traces from BLE
+ */
+
+#define BLE_DBG_APP_EN             0
+#define BLE_DBG_DIS_EN             0
+#define BLE_DBG_HRS_EN             0
+#define BLE_DBG_SVCCTL_EN          0
+#define BLE_DBG_BLS_EN             0
+#define BLE_DBG_HTS_EN             0
+#define BLE_DBG_P2P_STM_EN         0
+
+/**
+ * Macro definition
+ */
+#if ( BLE_DBG_APP_EN != 0 )
+#define BLE_DBG_APP_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_APP_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_DIS_EN != 0 )
+#define BLE_DBG_DIS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_DIS_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_HRS_EN != 0 )
+#define BLE_DBG_HRS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HRS_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_P2P_STM_EN != 0 )
+#define BLE_DBG_P2P_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_P2P_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_TEMPLATE_STM_EN != 0 )
+#define BLE_DBG_TEMPLATE_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_TEMPLATE_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_EDS_STM_EN != 0 )
+#define BLE_DBG_EDS_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_EDS_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_LBS_STM_EN != 0 )
+#define BLE_DBG_LBS_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_LBS_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_SVCCTL_EN != 0 )
+#define BLE_DBG_SVCCTL_MSG          PRINT_MESG_DBG
+#else
+#define BLE_DBG_SVCCTL_MSG          PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_CTS_EN != 0)
+#define BLE_DBG_CTS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_CTS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HIDS_EN != 0)
+#define BLE_DBG_HIDS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_HIDS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_PASS_EN != 0)
+#define BLE_DBG_PASS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_PASS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_BLS_EN != 0)
+#define BLE_DBG_BLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_BLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HTS_EN != 0)
+#define BLE_DBG_HTS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HTS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_ANS_EN != 0)
+#define BLE_DBG_ANS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_ANS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_ESS_EN != 0)
+#define BLE_DBG_ESS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_ESS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_GLS_EN != 0)
+#define BLE_DBG_GLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_GLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_BAS_EN != 0)
+#define BLE_DBG_BAS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_BAS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_RTUS_EN != 0)
+#define BLE_DBG_RTUS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_RTUS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HPS_EN != 0)
+#define BLE_DBG_HPS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HPS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_TPS_EN != 0)
+#define BLE_DBG_TPS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_TPS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_LLS_EN != 0)
+#define BLE_DBG_LLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_LLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_IAS_EN != 0)
+#define BLE_DBG_IAS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_IAS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_WSS_EN != 0)
+#define BLE_DBG_WSS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_WSS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_LNS_EN != 0)
+#define BLE_DBG_LNS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_LNS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_SCPS_EN != 0)
+#define BLE_DBG_SCPS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_SCPS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_DTS_EN != 0)
+#define BLE_DBG_DTS_MSG             PRINT_MESG_DBG
+#define BLE_DBG_DTS_BUF             PRINT_LOG_BUFF_DBG
+#else
+#define BLE_DBG_DTS_MSG             PRINT_NO_MESG
+#define BLE_DBG_DTS_BUF             PRINT_NO_MESG
+#endif
+
+#endif /*__BLE_DBG_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/p2p_client_app.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/p2p_client_app.c
new file mode 100644
index 000000000..2e2db17cc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/p2p_client_app.c
@@ -0,0 +1,750 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    p2p_server_app.c
+ * @author  MCD Application Team
+ * @brief   peer to peer Server Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "main.h"
+#include "app_common.h"
+
+#include "dbg_trace.h"
+
+#include "ble.h"
+#include "p2p_client_app.h"
+
+#include "stm32_seq.h"
+#include "app_ble.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+
+typedef enum
+{
+  P2P_START_TIMER_EVT,
+  P2P_STOP_TIMER_EVT,
+  P2P_NOTIFICATION_INFO_RECEIVED_EVT,
+} P2P_Client_Opcode_Notification_evt_t;
+
+typedef struct
+{
+  uint8_t * pPayload;
+  uint8_t     Length;
+}P2P_Client_Data_t;
+
+typedef struct
+{
+  P2P_Client_Opcode_Notification_evt_t  P2P_Client_Evt_Opcode;
+  P2P_Client_Data_t DataTransfered;
+}P2P_Client_App_Notification_evt_t;
+
+typedef struct
+{
+  /**
+   * state of the P2P Client
+   * state machine
+   */
+  APP_BLE_ConnStatus_t state;
+
+  /**
+   * connection handle
+   */
+  uint16_t connHandle;
+
+  /**
+   * handle of the P2P service
+   */
+  uint16_t P2PServiceHandle;
+
+  /**
+   * end handle of the P2P service
+   */
+  uint16_t P2PServiceEndHandle;
+
+  /**
+   * handle of the Tx characteristic - Write To Server
+   *
+   */
+  uint16_t P2PWriteToServerCharHdle;
+
+  /**
+   * handle of the client configuration
+   * descriptor of Tx characteristic
+   */
+  uint16_t P2PWriteToServerDescHandle;
+
+  /**
+   * handle of the Rx characteristic - Notification From Server
+   *
+   */
+  uint16_t P2PNotificationCharHdle;
+
+  /**
+   * handle of the client configuration
+   * descriptor of Rx characteristic
+   */
+  uint16_t P2PNotificationDescHandle;
+
+}P2P_ClientContext_t;
+
+/* USER CODE BEGIN PTD */
+typedef struct{
+  uint8_t                                     Device_Led_Selection;
+  uint8_t                                     Led1;
+}P2P_LedCharValue_t;
+
+typedef struct{
+  uint8_t                                     Device_Button_Selection;
+  uint8_t                                     Button1;
+}P2P_ButtonCharValue_t;
+
+typedef struct
+{
+
+  uint8_t       Notification_Status; /* used to chek if P2P Server is enabled to Notify */
+
+  P2P_LedCharValue_t         LedControl;
+  P2P_ButtonCharValue_t      ButtonStatus;
+
+  uint16_t ConnectionHandle; 
+
+
+} P2P_Client_App_Context_t;
+
+/* USER CODE END PTD */
+
+/* Private defines ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros -------------------------------------------------------------*/
+#define UNPACK_2_BYTE_PARAMETER(ptr)  \
+        (uint16_t)((uint16_t)(*((uint8_t *)ptr))) |   \
+        (uint16_t)((((uint16_t)(*((uint8_t *)ptr + 1))) << 8))
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/**
+ * START of Section BLE_APP_CONTEXT
+ */
+
+PLACE_IN_SECTION("BLE_APP_CONTEXT") static P2P_ClientContext_t aP2PClientContext[BLE_CFG_CLT_MAX_NBR_CB];
+
+/**
+ * END of Section BLE_APP_CONTEXT
+ */
+/* USER CODE BEGIN PV */
+PLACE_IN_SECTION("BLE_APP_CONTEXT") static P2P_Client_App_Context_t P2P_Client_App_Context;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+static void Gatt_Notification(P2P_Client_App_Notification_evt_t *pNotification);
+static SVCCTL_EvtAckStatus_t Event_Handler(void *Event);
+/* USER CODE BEGIN PFP */
+static tBleStatus Write_Char(uint16_t UUID, uint8_t Service_Instance, uint8_t *pPayload);
+static void Button_Trigger_Received( void );
+static void Update_Service( void );
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+/**
+ * @brief  Service initialization
+ * @param  None
+ * @retval None
+ */
+void P2PC_APP_Init(void)
+{
+  uint8_t index =0;
+/* USER CODE BEGIN P2PC_APP_Init_1 */
+  UTIL_SEQ_RegTask( 1<< CFG_TASK_SEARCH_SERVICE_ID, UTIL_SEQ_RFU, Update_Service );
+  UTIL_SEQ_RegTask( 1<< CFG_TASK_SW1_BUTTON_PUSHED_ID, UTIL_SEQ_RFU, Button_Trigger_Received );
+
+  /**
+   * Initialize LedButton Service
+   */
+  P2P_Client_App_Context.Notification_Status=0;
+  P2P_Client_App_Context.ConnectionHandle =  0x00;
+
+  P2P_Client_App_Context.LedControl.Device_Led_Selection=0x00;/* device Led */
+  P2P_Client_App_Context.LedControl.Led1=0x00; /* led OFF */
+  P2P_Client_App_Context.ButtonStatus.Device_Button_Selection=0x01;/* Device1 */
+  P2P_Client_App_Context.ButtonStatus.Button1=0x00;
+/* USER CODE END P2PC_APP_Init_1 */
+  for(index = 0; index < BLE_CFG_CLT_MAX_NBR_CB; index++)
+  {
+    aP2PClientContext[index].state= APP_BLE_IDLE;
+  }
+
+  /**
+   *  Register the event handler to the BLE controller
+   */
+  SVCCTL_RegisterCltHandler(Event_Handler);
+
+#if(CFG_DEBUG_APP_TRACE != 0)
+  APP_DBG_MSG("-- P2P CLIENT INITIALIZED \n");
+#endif
+
+/* USER CODE BEGIN P2PC_APP_Init_2 */
+
+/* USER CODE END P2PC_APP_Init_2 */
+  return;
+}
+
+void P2PC_APP_Notification(P2PC_APP_ConnHandle_Not_evt_t *pNotification)
+{
+/* USER CODE BEGIN P2PC_APP_Notification_1 */
+
+/* USER CODE END P2PC_APP_Notification_1 */
+  switch(pNotification->P2P_Evt_Opcode)
+  {
+/* USER CODE BEGIN P2P_Evt_Opcode */
+
+/* USER CODE END P2P_Evt_Opcode */
+
+  case PEER_CONN_HANDLE_EVT :
+/* USER CODE BEGIN PEER_CONN_HANDLE_EVT */
+    P2P_Client_App_Context.ConnectionHandle = pNotification->ConnectionHandle;
+/* USER CODE END PEER_CONN_HANDLE_EVT */
+      break;
+
+    case PEER_DISCON_HANDLE_EVT :
+/* USER CODE BEGIN PEER_DISCON_HANDLE_EVT */
+      {
+      uint8_t index = 0;
+      P2P_Client_App_Context.ConnectionHandle =  0x00;
+      while((index < BLE_CFG_CLT_MAX_NBR_CB) &&
+                  (aP2PClientContext[index].state != APP_BLE_IDLE))
+      {
+        aP2PClientContext[index].state = APP_BLE_IDLE;
+      }
+      BSP_LED_Off(LED_BLUE); 
+        
+#if OOB_DEMO == 0
+      UTIL_SEQ_SetTask(1<data);
+
+
+
+  switch(event_pckt->evt)
+  {
+    case EVT_VENDOR:
+    {
+      blue_evt = (evt_blue_aci*)event_pckt->data;
+      switch(blue_evt->ecode)
+      {
+
+        case EVT_BLUE_ATT_READ_BY_GROUP_TYPE_RESP:
+        {
+          aci_att_read_by_group_type_resp_event_rp0 *pr = (void*)blue_evt->data;
+          uint8_t numServ, i, idx;
+          uint16_t uuid, handle;
+
+          uint8_t index;
+          handle = pr->Connection_Handle;
+          index = 0;
+          while((index < BLE_CFG_CLT_MAX_NBR_CB) &&
+                  (aP2PClientContext[index].state != APP_BLE_IDLE))
+          {
+            APP_BLE_ConnStatus_t status;
+
+            status = APP_BLE_Get_Client_Connection_Status(aP2PClientContext[index].connHandle);
+
+            if((aP2PClientContext[index].state == APP_BLE_CONNECTED_CLIENT)&&
+                    (status == APP_BLE_IDLE))
+            {
+              /* Handle deconnected */
+
+              aP2PClientContext[index].state = APP_BLE_IDLE;
+              aP2PClientContext[index].connHandle = 0xFFFF;
+              break;
+            }
+            index++;
+          }
+
+          if(index < BLE_CFG_CLT_MAX_NBR_CB)
+          {
+            aP2PClientContext[index].connHandle= handle;
+
+
+            numServ = (pr->Data_Length) / pr->Attribute_Data_Length;
+
+            /* the event data will be
+             * 2bytes start handle
+             * 2bytes end handle
+             * 2 or 16 bytes data
+             * we are interested only if the UUID is 16 bit.
+             * So check if the data length is 6
+             */
+#if (UUID_128BIT_FORMAT==1)           
+          if (pr->Attribute_Data_Length == 20)
+          {
+            idx = 16;
+#else
+          if (pr->Attribute_Data_Length == 6)
+          {
+            idx = 4;
+#endif             
+              for (i=0; iAttribute_Data_List[idx]);
+                if(uuid == P2P_SERVICE_UUID)
+                {
+#if(CFG_DEBUG_APP_TRACE != 0)
+                  APP_DBG_MSG("-- GATT : P2P_SERVICE_UUID FOUND - connection handle 0x%x \n", aP2PClientContext[index].connHandle);
+#endif
+#if (UUID_128BIT_FORMAT==1)                     
+                aP2PClientContext[index].P2PServiceHandle = UNPACK_2_BYTE_PARAMETER(&pr->Attribute_Data_List[idx-16]);
+                aP2PClientContext[index].P2PServiceEndHandle = UNPACK_2_BYTE_PARAMETER (&pr->Attribute_Data_List[idx-14]);
+#else   
+                aP2PClientContext[index].P2PServiceHandle = UNPACK_2_BYTE_PARAMETER(&pr->Attribute_Data_List[idx-4]);
+                aP2PClientContext[index].P2PServiceEndHandle = UNPACK_2_BYTE_PARAMETER (&pr->Attribute_Data_List[idx-2]);
+#endif                  
+                  aP2PClientContext[index].state = APP_BLE_DISCOVER_CHARACS ;
+                }
+                idx += 6;
+              }
+            }
+          }
+        }
+        break;
+
+        case EVT_BLUE_ATT_READ_BY_TYPE_RESP:
+        {
+
+          aci_att_read_by_type_resp_event_rp0 *pr = (void*)blue_evt->data;
+          uint8_t idx;
+          uint16_t uuid, handle;
+
+          /* the event data will be
+           * 2 bytes start handle
+           * 1 byte char properties
+           * 2 bytes handle
+           * 2 or 16 bytes data
+           */
+
+          uint8_t index;
+
+          index = 0;
+          while((index < BLE_CFG_CLT_MAX_NBR_CB) &&
+                  (aP2PClientContext[index].connHandle != pr->Connection_Handle))
+            index++;
+
+          if(index < BLE_CFG_CLT_MAX_NBR_CB)
+          {
+
+            /* we are interested in only 16 bit UUIDs */
+#if (UUID_128BIT_FORMAT==1)
+            idx = 17;
+            if (pr->Handle_Value_Pair_Length == 21)
+#else
+              idx = 5;
+            if (pr->Handle_Value_Pair_Length == 7)
+#endif
+            {
+              pr->Data_Length -= 1;
+              while(pr->Data_Length > 0)
+              {
+                uuid = UNPACK_2_BYTE_PARAMETER(&pr->Handle_Value_Pair_Data[idx]);
+                /* store the characteristic handle not the attribute handle */
+#if (UUID_128BIT_FORMAT==1)
+                handle = UNPACK_2_BYTE_PARAMETER(&pr->Handle_Value_Pair_Data[idx-14]);
+#else
+                handle = UNPACK_2_BYTE_PARAMETER(&pr->Handle_Value_Pair_Data[idx-2]);
+#endif
+                if(uuid == P2P_WRITE_CHAR_UUID)
+                {
+#if(CFG_DEBUG_APP_TRACE != 0)
+                  APP_DBG_MSG("-- GATT : WRITE_UUID FOUND - connection handle 0x%x\n", aP2PClientContext[index].connHandle);
+#endif
+                  aP2PClientContext[index].state = APP_BLE_DISCOVER_WRITE_DESC;
+                  aP2PClientContext[index].P2PWriteToServerCharHdle = handle;
+                }
+
+                else if(uuid == P2P_NOTIFY_CHAR_UUID)
+                {
+#if(CFG_DEBUG_APP_TRACE != 0)
+                  APP_DBG_MSG("-- GATT : NOTIFICATION_CHAR_UUID FOUND  - connection handle 0x%x\n", aP2PClientContext[index].connHandle);
+#endif
+                  aP2PClientContext[index].state = APP_BLE_DISCOVER_NOTIFICATION_CHAR_DESC;
+                  aP2PClientContext[index].P2PNotificationCharHdle = handle;
+                }
+#if (UUID_128BIT_FORMAT==1)
+                pr->Data_Length -= 21;
+                idx += 21;
+#else
+                pr->Data_Length -= 7;
+                idx += 7;
+#endif
+              }
+            }
+          }
+        }
+        break;
+
+        case EVT_BLUE_ATT_FIND_INFORMATION_RESP:
+        {
+          aci_att_find_info_resp_event_rp0 *pr = (void*)blue_evt->data;
+
+          uint8_t numDesc, idx, i;
+          uint16_t uuid, handle;
+
+          /*
+           * event data will be of the format
+           * 2 bytes handle
+           * 2 bytes UUID
+           */
+
+          uint8_t index;
+
+          index = 0;
+          while((index < BLE_CFG_CLT_MAX_NBR_CB) &&
+                  (aP2PClientContext[index].connHandle != pr->Connection_Handle))
+
+            index++;
+
+          if(index < BLE_CFG_CLT_MAX_NBR_CB)
+          {
+
+            numDesc = (pr->Event_Data_Length) / 4;
+            /* we are interested only in 16 bit UUIDs */
+            idx = 0;
+            if (pr->Format == UUID_TYPE_16)
+            {
+              for (i=0; iHandle_UUID_Pair[idx]);
+                uuid = UNPACK_2_BYTE_PARAMETER(&pr->Handle_UUID_Pair[idx+2]);
+
+                if(uuid == CLIENT_CHAR_CONFIG_DESCRIPTOR_UUID)
+                {
+#if(CFG_DEBUG_APP_TRACE != 0)
+                  APP_DBG_MSG("-- GATT : CLIENT_CHAR_CONFIG_DESCRIPTOR_UUID- connection handle 0x%x\n", aP2PClientContext[index].connHandle);
+#endif
+                  if( aP2PClientContext[index].state == APP_BLE_DISCOVER_NOTIFICATION_CHAR_DESC)
+                  {
+
+                    aP2PClientContext[index].P2PNotificationDescHandle = handle;
+                    aP2PClientContext[index].state = APP_BLE_ENABLE_NOTIFICATION_DESC;
+
+                  }
+                }
+                idx += 4;
+              }
+            }
+          }
+        }
+        break; /*EVT_BLUE_ATT_FIND_INFORMATION_RESP*/
+
+        case EVT_BLUE_GATT_NOTIFICATION:
+        {
+          aci_gatt_notification_event_rp0 *pr = (void*)blue_evt->data;
+          uint8_t index;
+
+          index = 0;
+          while((index < BLE_CFG_CLT_MAX_NBR_CB) &&
+                  (aP2PClientContext[index].connHandle != pr->Connection_Handle))
+            index++;
+
+          if(index < BLE_CFG_CLT_MAX_NBR_CB)
+          {
+
+            if ( (pr->Attribute_Handle == aP2PClientContext[index].P2PNotificationCharHdle) &&
+                    (pr->Attribute_Value_Length == (2)) )
+            {
+
+              Notification.P2P_Client_Evt_Opcode = P2P_NOTIFICATION_INFO_RECEIVED_EVT;
+              Notification.DataTransfered.Length = pr->Attribute_Value_Length;
+              Notification.DataTransfered.pPayload = &pr->Attribute_Value[0];
+
+              Gatt_Notification(&Notification);
+
+              /* INFORM APPLICATION BUTTON IS PUSHED BY END DEVICE */
+
+            }
+          }
+        }
+        break;/* end EVT_BLUE_GATT_NOTIFICATION */
+
+        case EVT_BLUE_GATT_PROCEDURE_COMPLETE:
+        {
+          aci_gatt_proc_complete_event_rp0 *pr = (void*)blue_evt->data;
+#if(CFG_DEBUG_APP_TRACE != 0)
+          APP_DBG_MSG("-- GATT : EVT_BLUE_GATT_PROCEDURE_COMPLETE \n");
+          APP_DBG_MSG("\n");
+#endif
+
+          uint8_t index;
+
+          index = 0;
+          while((index < BLE_CFG_CLT_MAX_NBR_CB) &&
+                  (aP2PClientContext[index].connHandle != pr->Connection_Handle))
+            index++;
+
+          if(index < BLE_CFG_CLT_MAX_NBR_CB)
+          {
+
+            UTIL_SEQ_SetTask( 1<P2P_Client_Evt_Opcode)
+  {
+/* USER CODE BEGIN P2P_Client_Evt_Opcode */
+
+/* USER CODE END P2P_Client_Evt_Opcode */
+
+    case P2P_NOTIFICATION_INFO_RECEIVED_EVT:
+/* USER CODE BEGIN P2P_NOTIFICATION_INFO_RECEIVED_EVT */
+    {
+      P2P_Client_App_Context.LedControl.Device_Led_Selection=pNotification->DataTransfered.pPayload[0];
+      switch(P2P_Client_App_Context.LedControl.Device_Led_Selection) {
+
+        case 0x01 : {
+
+          P2P_Client_App_Context.LedControl.Led1=pNotification->DataTransfered.pPayload[1];
+
+          if(P2P_Client_App_Context.LedControl.Led1==0x00){
+            BSP_LED_Off(LED_BLUE);
+            APP_DBG_MSG(" -- P2P APPLICATION CLIENT : NOTIFICATION RECEIVED - LED OFF \n\r");
+            APP_DBG_MSG(" \n\r");
+          } else {
+            APP_DBG_MSG(" -- P2P APPLICATION CLIENT : NOTIFICATION RECEIVED - LED ON\n\r");
+            APP_DBG_MSG(" \n\r");
+            BSP_LED_On(LED_BLUE);
+          }
+
+          break;
+        }
+        default : break;
+      }
+
+    }
+/* USER CODE END P2P_NOTIFICATION_INFO_RECEIVED_EVT */
+      break;
+
+    default:
+/* USER CODE BEGIN P2P_Client_Evt_Opcode_Default */
+
+/* USER CODE END P2P_Client_Evt_Opcode_Default */
+      break;
+  }
+/* USER CODE BEGIN Gatt_Notification_2*/
+
+/* USER CODE END Gatt_Notification_2 */
+  return;
+}
+
+uint8_t P2P_Client_APP_Get_State( void ) {
+  return aP2PClientContext[0].state;
+}
+/* USER CODE BEGIN LF */
+/**
+ * @brief  Feature Characteristic update
+ * @param  pFeatureValue: The address of the new value to be written
+ * @retval None
+ */
+tBleStatus Write_Char(uint16_t UUID, uint8_t Service_Instance, uint8_t *pPayload)
+{
+
+  tBleStatus ret = BLE_STATUS_INVALID_PARAMS;
+  uint8_t index;
+
+  index = 0;
+  while((index < BLE_CFG_CLT_MAX_NBR_CB) &&
+          (aP2PClientContext[index].state != APP_BLE_IDLE))
+  {
+
+    switch(UUID)
+    {
+      case P2P_WRITE_CHAR_UUID: /* SERVER RX -- so CLIENT TX */
+        ret =aci_gatt_write_without_resp(aP2PClientContext[index].connHandle,
+                                         aP2PClientContext[index].P2PWriteToServerCharHdle,
+                                         2, /* charValueLen */
+                                         (uint8_t *)  pPayload);
+
+        break;
+
+      default:
+        break;
+    }
+    index++;
+  }
+
+  return ret;
+}/* end Write_Char() */
+
+void Button_Trigger_Received(void)
+{
+
+
+  APP_DBG_MSG("-- P2P APPLICATION CLIENT  : BUTTON PUSHED - WRITE TO SERVER \n ");
+  APP_DBG_MSG(" \n\r");
+  if(P2P_Client_App_Context.ButtonStatus.Button1==0x00){
+    P2P_Client_App_Context.ButtonStatus.Button1=0x01;
+  }else {
+    P2P_Client_App_Context.ButtonStatus.Button1=0x00;
+  }
+
+  Write_Char( P2P_WRITE_CHAR_UUID, 0, (uint8_t *)&P2P_Client_App_Context.ButtonStatus);
+
+  return;
+}
+
+void Update_Service()
+{
+  uint16_t enable = 0x0001;
+
+
+  uint8_t index;
+
+  index = 0;
+  while((index < BLE_CFG_CLT_MAX_NBR_CB) &&
+          (aP2PClientContext[index].state != APP_BLE_IDLE))
+  {
+
+
+    switch(aP2PClientContext[index].state)
+    {
+
+      case APP_BLE_DISCOVER_SERVICES:
+        APP_DBG_MSG("P2P_DISCOVER_SERVICES\n");
+        break;
+      case APP_BLE_DISCOVER_CHARACS:
+        APP_DBG_MSG("* GATT : Discover P2P Characteristics\n");
+        aci_gatt_disc_all_char_of_service(aP2PClientContext[index].connHandle,
+                                          aP2PClientContext[index].P2PServiceHandle,
+                                          aP2PClientContext[index].P2PServiceEndHandle);
+
+        break;
+      case APP_BLE_DISCOVER_WRITE_DESC: /* Not Used - No decriptor */
+        APP_DBG_MSG("* GATT : Discover Descriptor of TX - Write Characteritic\n");
+        aci_gatt_disc_all_char_desc(aP2PClientContext[index].connHandle,
+                                    aP2PClientContext[index].P2PWriteToServerCharHdle,
+                                    aP2PClientContext[index].P2PWriteToServerCharHdle+2);
+
+        break;
+      case APP_BLE_DISCOVER_NOTIFICATION_CHAR_DESC:
+        APP_DBG_MSG("* GATT : Discover Descriptor of Rx - Notification Characteritic\n");
+        aci_gatt_disc_all_char_desc(aP2PClientContext[index].connHandle,
+                                    aP2PClientContext[index].P2PNotificationCharHdle,
+                                    aP2PClientContext[index].P2PNotificationCharHdle+2);
+
+        break;
+      case APP_BLE_ENABLE_NOTIFICATION_DESC:
+        APP_DBG_MSG("* GATT : Enable Server Notification\n");
+        aci_gatt_write_char_desc(aP2PClientContext[index].connHandle,
+                                 aP2PClientContext[index].P2PNotificationDescHandle,
+                                 2,
+                                 (uint8_t *)&enable);
+
+        aP2PClientContext[index].state = APP_BLE_CONNECTED_CLIENT;
+        BSP_LED_Off(LED_RED);
+
+        break;
+      case APP_BLE_DISABLE_NOTIFICATION_DESC :
+        APP_DBG_MSG("* GATT : Disable Server Notification\n");
+        aci_gatt_write_char_desc(aP2PClientContext[index].connHandle,
+                                 aP2PClientContext[index].P2PNotificationDescHandle,
+                                 2,
+                                 (uint8_t *)&enable);
+
+        aP2PClientContext[index].state = APP_BLE_CONNECTED_CLIENT;
+
+        break;
+      default:
+        break;
+    }
+    index++;
+  }
+  return;
+}
+/* USER CODE END LF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/p2p_client_app.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/p2p_client_app.h
new file mode 100644
index 000000000..bbb0aaa39
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/App/p2p_client_app.h
@@ -0,0 +1,83 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    p2p_server_app.h
+ * @author  MCD Application Team
+ * @brief   Header for p2p_server_app.c module
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __P2P_APPLICATION_H
+#define __P2P_APPLICATION_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+typedef enum
+{
+  PEER_CONN_HANDLE_EVT,
+  PEER_DISCON_HANDLE_EVT,
+} P2PC_APP_Opcode_Notification_evt_t;
+
+typedef struct
+{
+  P2PC_APP_Opcode_Notification_evt_t          P2P_Evt_Opcode;
+  uint16_t                                    ConnectionHandle;
+
+}P2PC_APP_ConnHandle_Not_evt_t;
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+void P2PC_APP_Init( void );
+void P2PC_APP_Notification( P2PC_APP_ConnHandle_Not_evt_t *pNotification );
+uint8_t P2P_Client_APP_Get_State( void );
+/* USER CODE BEGIN EFP */
+void P2PC_APP_SW1_Button_Action(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__P2P_APPLICATION_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/Target/hw_ipcc.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/Target/hw_ipcc.c
new file mode 100644
index 000000000..0f839543a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/STM32_WPAN/Target/hw_ipcc.c
@@ -0,0 +1,523 @@
+/**
+ ******************************************************************************
+  * File Name          : Target/hw_ipcc.c
+  * Description        : Hardware IPCC source file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "mbox_def.h"
+
+/* Global variables ---------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+#define HW_IPCC_TX_PENDING( channel ) ( !(LL_C1_IPCC_IsActiveFlag_CHx( IPCC, channel )) ) &&  (((~(IPCC->C1MR)) & (channel << 16U)))
+#define HW_IPCC_RX_PENDING( channel )  (LL_C2_IPCC_IsActiveFlag_CHx( IPCC, channel )) && (((~(IPCC->C1MR)) & (channel << 0U)))
+
+/* Private macros ------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static void (*FreeBufCb)( void );
+
+/* Private function prototypes -----------------------------------------------*/
+static void HW_IPCC_BLE_EvtHandler( void );
+static void HW_IPCC_BLE_AclDataEvtHandler( void );
+static void HW_IPCC_MM_FreeBufHandler( void );
+static void HW_IPCC_SYS_CmdEvtHandler( void );
+static void HW_IPCC_SYS_EvtHandler( void );
+static void HW_IPCC_TRACES_EvtHandler( void );
+
+#ifdef THREAD_WB
+static void HW_IPCC_OT_CmdEvtHandler( void );
+static void HW_IPCC_THREAD_NotEvtHandler( void );
+static void HW_IPCC_THREAD_CliNotEvtHandler( void );
+#endif
+
+#ifdef MAC_802_15_4_WB
+static void HW_IPCC_MAC_802_15_4_CmdEvtHandler( void );
+static void HW_IPCC_MAC_802_15_4_NotEvtHandler( void );
+#endif
+
+#ifdef ZIGBEE_WB
+static void HW_IPCC_ZIGBEE_CmdEvtHandler( void );
+static void HW_IPCC_ZIGBEE_StackNotifEvtHandler( void );
+static void HW_IPCC_ZIGBEE_CliNotifEvtHandler( void );
+#endif
+
+/* Public function definition -----------------------------------------------*/
+
+/******************************************************************************
+ * INTERRUPT HANDLER
+ ******************************************************************************/
+void HW_IPCC_Rx_Handler( void )
+{
+  if (HW_IPCC_RX_PENDING( HW_IPCC_SYSTEM_EVENT_CHANNEL ))
+  {
+      HW_IPCC_SYS_EvtHandler();
+  }
+#ifdef MAC_802_15_4_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_MAC_802_15_4_NotEvtHandler();
+  }
+#endif /* MAC_802_15_4_WB */
+#ifdef THREAD_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_THREAD_NotEvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_THREAD_CliNotEvtHandler();
+  }
+#endif /* THREAD_WB */
+#ifdef ZIGBEE_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_ZIGBEE_StackNotifEvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
+  {
+      HW_IPCC_ZIGBEE_CliNotifEvtHandler();
+  }
+#endif /* ZIGBEE_WB */
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_BLE_EVENT_CHANNEL ))
+  {
+    HW_IPCC_BLE_EvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_TRACES_CHANNEL ))
+  {
+    HW_IPCC_TRACES_EvtHandler();
+  }
+
+  return;
+}
+
+void HW_IPCC_Tx_Handler( void )
+{
+  if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_SYS_CmdEvtHandler();
+  }
+#ifdef MAC_802_15_4_WB
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_MAC_802_15_4_CmdEvtHandler();
+  }
+#endif /* MAC_802_15_4_WB */
+#ifdef THREAD_WB
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_OT_CmdEvtHandler();
+  }
+#endif /* THREAD_WB */
+#ifdef ZIGBEE_WB
+  if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
+  {
+      HW_IPCC_ZIGBEE_CmdEvtHandler();
+  }
+#endif /* ZIGBEE_WB */
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_SYS_CmdEvtHandler();
+  }
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ))
+  {
+    HW_IPCC_MM_FreeBufHandler();
+  }
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_HCI_ACL_DATA_CHANNEL ))
+  {
+    HW_IPCC_BLE_AclDataEvtHandler();
+  }
+
+  return;
+}
+/******************************************************************************
+ * GENERAL
+ ******************************************************************************/
+void HW_IPCC_Enable( void )
+{
+  /**
+   * When the device is out of standby, it is required to use the EXTI mechanism to wakeup CPU2
+   */
+  LL_C2_EXTI_EnableEvent_32_63( LL_EXTI_LINE_41 );
+  LL_EXTI_EnableRisingTrig_32_63( LL_EXTI_LINE_41 );
+	
+  /**
+   * In case the SBSFU is implemented, it may have already set the C2BOOT bit to startup the CPU2.
+   * In that case, to keep the mechanism transparent to the user application, it shall call the system command
+   * SHCI_C2_Reinit( ) before jumping to the application.
+   * When the CPU2 receives that command, it waits for its event input to be set to restart the CPU2 firmware.
+   * This is required because once C2BOOT has been set once, a clear/set on C2BOOT has no effect.
+   * When SHCI_C2_Reinit( ) is not called, generating an event to the CPU2 does not have any effect
+   * So, by default, the application shall both set the event flag and set the C2BOOT bit.
+   */
+  __SEV( );       /* Set the internal event flag and send an event to the CPU2 */
+  __WFE( );       /* Clear the internal event flag */
+  LL_PWR_EnableBootC2( );
+
+  return;
+}
+
+void HW_IPCC_Init( void )
+{
+  LL_AHB3_GRP1_EnableClock( LL_AHB3_GRP1_PERIPH_IPCC );
+
+  LL_C1_IPCC_EnableIT_RXO( IPCC );
+  LL_C1_IPCC_EnableIT_TXF( IPCC );
+
+  HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn);
+  HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn);
+
+  return;
+}
+
+/******************************************************************************
+ * BLE
+ ******************************************************************************/
+void HW_IPCC_BLE_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_BLE_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_BLE_CMD_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_BLE_EvtHandler( void )
+{
+  HW_IPCC_BLE_RxEvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_BLE_SendAclData( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_BLE_AclDataEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+
+  HW_IPCC_BLE_AclDataAckNot();
+
+  return;
+}
+
+__weak void HW_IPCC_BLE_AclDataAckNot( void ){};
+__weak void HW_IPCC_BLE_RxEvtNot( void ){};
+
+/******************************************************************************
+ * SYSTEM
+ ******************************************************************************/
+void HW_IPCC_SYS_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_SYS_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_SYS_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+
+  HW_IPCC_SYS_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_SYS_EvtHandler( void )
+{
+  HW_IPCC_SYS_EvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
+
+  return;
+}
+
+__weak void HW_IPCC_SYS_CmdEvtNot( void ){};
+__weak void HW_IPCC_SYS_EvtNot( void ){};
+
+/******************************************************************************
+ * MAC 802.15.4
+ ******************************************************************************/
+#ifdef MAC_802_15_4_WB
+void HW_IPCC_MAC_802_15_4_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_MAC_802_15_4_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_MAC_802_15_4_SendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_MAC_802_15_4_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+
+  HW_IPCC_MAC_802_15_4_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_MAC_802_15_4_NotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_MAC_802_15_4_EvtNot();
+
+  return;
+}
+__weak void HW_IPCC_MAC_802_15_4_CmdEvtNot( void ){};
+__weak void HW_IPCC_MAC_802_15_4_EvtNot( void ){};
+#endif
+
+/******************************************************************************
+ * THREAD
+ ******************************************************************************/
+#ifdef THREAD_WB
+void HW_IPCC_THREAD_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_OT_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_CLI_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_THREAD_SendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_THREAD_CliSendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_OT_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  HW_IPCC_OT_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_THREAD_NotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_THREAD_EvtNot();
+
+  return;
+}
+
+static void HW_IPCC_THREAD_CliNotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_THREAD_CliEvtNot();
+
+  return;
+}
+
+__weak void HW_IPCC_OT_CmdEvtNot( void ){};
+__weak void HW_IPCC_CLI_CmdEvtNot( void ){};
+__weak void HW_IPCC_THREAD_EvtNot( void ){};
+
+#endif /* THREAD_WB */
+
+/******************************************************************************
+ * ZIGBEE
+ ******************************************************************************/
+#ifdef ZIGBEE_WB
+void HW_IPCC_ZIGBEE_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendAppliCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendCliCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
+
+   return;
+}
+
+void HW_IPCC_ZIGBEE_SendAppliCmdAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendCliCmdAck( void )
+{
+    LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+    LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_CmdEvtHandler( void )
+{
+    LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+    HW_IPCC_ZIGBEE_AppliCmdNotification();
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_StackNotifEvtHandler( void )
+{
+    LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+    HW_IPCC_ZIGBEE_AppliAsyncEvtNotification();
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_CliNotifEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_ZIGBEE_CliEvtNotification();
+
+  return;
+}
+
+__weak void HW_IPCC_ZIGBEE_AppliCmdNotification( void ){};
+__weak void HW_IPCC_ZIGBEE_AppliAsyncEvtNotification( void ){};
+__weak void HW_IPCC_ZIGBEE_CliEvtNotification( void ){};
+#endif /* ZIGBEE_WB */
+
+/******************************************************************************
+ * MEMORY MANAGER
+ ******************************************************************************/
+void HW_IPCC_MM_SendFreeBuf( void (*cb)( void ) )
+{
+  if ( LL_C1_IPCC_IsActiveFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ) )
+  {
+    FreeBufCb = cb;
+    LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+  }
+  else
+  {
+    cb();
+
+    LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+  }
+
+  return;
+}
+
+static void HW_IPCC_MM_FreeBufHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+
+  FreeBufCb();
+
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+
+  return;
+}
+
+/******************************************************************************
+ * TRACES
+ ******************************************************************************/
+void HW_IPCC_TRACES_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_TRACES_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_TRACES_EvtHandler( void )
+{
+  HW_IPCC_TRACES_EvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_TRACES_CHANNEL );
+
+  return;
+}
+
+__weak void HW_IPCC_TRACES_EvtNot( void ){};
+
+/******************* (C) COPYRIGHT 2019 STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/readme.txt b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/readme.txt
new file mode 100644
index 000000000..54f3a9a31
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pClient/readme.txt
@@ -0,0 +1,100 @@
+/**
+  @page BLE_p2pClient Application
+
+  @verbatim
+  ******************************************************************************
+  * @file    BLE/BLE_p2pClient/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the BLE_p2pClient application
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                               www.st.com/SLA0044
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Application Description
+
+This example is to demonstrate Point-to-Point communication using BLE component. 
+
+Two STM32WB35xx boards are used, one acting as GATT client, and one as GATT server.
+For example, BLE_p2pClient application is downloaded in a Nucleo board (MB1507A) and BLE P2P_Server application in a Nucleo board (MB1507A).
+
+
+
+@par Directory contents 
+  
+  - BLE/BLE_p2pClient/Core/Inc/stm32wbxx_hal_conf.h		HAL configuration file
+  - BLE/BLE_p2pClient/Core/Inc/stm32wbxx_it.h          	Interrupt handlers header file
+  - BLE/BLE_p2pClient/Core/Inc/main.h                  	Header for main.c module
+  - BLE/BLE_p2pClient/STM32_WPAN/App/app_ble.h          Header for app_ble.c module
+  - BLE/BLE_p2pClient/Core/Inc/app_common.h            	Header for all modules with common definition
+  - BLE/BLE_p2pClient/Core/Inc/app_conf.h              	Parameters configuration file of the application
+  - BLE/BLE_p2pClient/Core/Inc/app_entry.h            	Parameters configuration file of the application
+  - BLE/BLE_p2pClient/STM32_WPAN/App/ble_conf.h         BLE Services configuration
+  - BLE/BLE_p2pClient/STM32_WPAN/App/ble_dbg_conf.h     BLE Traces configuration of the BLE services
+  - BLE/BLE_p2pClient/STM32_WPAN/App/p2p_client_app.h   Header for p2p_lcient_app.c module
+  - BLE/BLE_p2pClient/Core/Inc/hw_conf.h           		Configuration file of the HW
+  - BLE/BLE_p2pClient/Core/Inc/utilities_conf.h    		Configuration file of the utilities
+  - BLE/BLE_p2pClient/Core/Src/stm32wbxx_it.c          	Interrupt handlers
+  - BLE/BLE_p2pClient/Core/Src/main.c                  	Main program
+  - BLE/BLE_p2pClient/Core/Src/system_stm32wbxx.c      	stm32wbxx system source file
+  - BLE/BLE_p2pClient/STM32_WPAN/App/app_ble.c      	BLE Profile implementation
+  - BLE/BLE_p2pClient/Core/Src/app_entry.c      		Initialization of the application
+  - BLE/BLE_p2pClient/STM32_WPAN/App/p2p_client_app.c   P2P Client Application Implementation
+  - BLE/BLE_p2pClient/STM32_WPAN/Target/hw_ipcc.c      	IPCC Driver
+  - BLE/BLE_p2pClient/Core/Src/stm32_lpm_if.c			Low Power Manager Interface
+  - BLE/BLE_p2pClient/Core/Src/hw_timerserver.c 		Timer Server based on RTC
+  - BLE/BLE_p2pClient/Core/Src/hw_uart.c 				UART Driver
+  
+@par Hardware and Software environment
+
+    - This application runs on STM32WB35xx Nucleo board (MB1507A)
+    
+    - Nucleo board (MB1507A) Set-up    
+       - Connect that Board to your PC with a USB cable type A to mini-B to ST-LINK connector (USB_STLINK).
+       - Please ensure that the ST-LINK connectors and jumpers are fitted.
+
+@par How to use it ? 
+
+This application requests having the stm32wb3x_BLE_Stack_fw.bin binary flashed on the Wireless Coprocessor.
+If it is not the case, you need to use STM32CubeProgrammer to load the appropriate binary.
+All available binaries are located under /Projects/STM32_Copro_Wireless_Binaries directory.
+Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the detailed procedure to change the
+Wireless Coprocessor binary.  
+   
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load the image into Target memory
+ - OR use the BLE_p2pClient_reference.hex from Binary directory
+ - This must be done for BLE_p2pServer (MB1507A) for example, and BLE_p2pClient (MB1507A).
+
+ - BLE_p2pServer may be connected by BLE_p2pClient.
+ - Once the code (BLE_p2pServer & BLE_p2pClient) is downloaded into the two STM32WB35xx boards and executed, the modules are initialized. 
+
+ - The Peripheral device (BLE_p2pServer) starts advertising (during 1 minute), the green led blinks for each advertising event.
+ - The Central device (BLE_p2pClient) starts scanning when pressing the User button (SW1). 
+   - BLE_p2pClient blue led becomes on. 
+   - Scan req takes about 5 seconds.
+   - Make sure BLE_p2pServer advertises, if not press reset button or switch off/on to restart advertising.
+ - Then, it automatically connects to the BLE_p2pServer. 
+   - Blue led turns off and green led starts blinking as on the MB1507A. Connection is done.
+ - When pressing SW1 on a board, the blue led toggles on the other one.
+   - The SW1 button can be pressed independently on the GATT Client or on the GATT Server.
+ - When the server is located on a MB1507A, the connection interval can be modified from 50ms to 1s and vice-versa using SW2. 
+ - The green led on the 2 boards blinks for each advertising event, it means quickly when 50ms and slowly when 1s. 
+ - Passing from 50ms to 1s is instantaneous, but from 1s to 50ms takes around 10 seconds.
+ - The SW1 event, switch on/off blue led, depends on the connection Interval event. 
+   - So the delay from SW1 action and blue led change is more or less fast.
+  
+For more details refer to the Application Note: 
+  AN5289 - Building a Wireless application 
+ 
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Binary/BLE_p2pServer.hex b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Binary/BLE_p2pServer.hex
new file mode 100644
index 000000000..d654d71f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Binary/BLE_p2pServer.hex
@@ -0,0 +1,2124 @@
+:020000040800F2
+:10000000B8270020BD8200088D8000088F8000087E
+:10001000918000089380000895800008000000008F
+:1000200000000000000000000000000097800008B1
+:1000300099800008000000009B8000089D80000857
+:10004000DF820008E3820008E7820008D58000080C
+:10005000EB820008EF820008C9800008F3820008E4
+:10006000F7820008FB820008CF800008FF820008AA
+:100070000383000807830008A18000080B830008A1
+:100080000F83000813830008178300081B830008F0
+:100090001F83000823830008278300082B830008A0
+:1000A0002F83000833830008378300083B83000850
+:1000B0003F83000843830008478300084B83000800
+:1000C0004F83000853830008578300085B830008B0
+:1000D000A7800008AD800008000000005F830008D2
+:1000E00063830008678300086B8300086F83000840
+:1000F000DD800008D980000873830008778300083A
+:100100007B830008000000007F83000883830008D1
+:10011000878300088B8300088F830008938300087F
+:10012000978300089B830008B38000089F83000822
+:10013000A3830008A7830008AB8300082DE9F84FCC
+:100140000FF2D017A2B0D7E90045CDE900452C9EAB
+:10015000DFF82C7C04918DF8436000210FF2BC1471
+:100160000D9112944FF0FF368246904699460FE06B
+:10017000C3462C461BF8011B0498D0470028049066
+:1001800000F0B2800D98401C641E0D90F2D1A8447E
+:1001900098F80000252807D10021079108910991BE
+:1001A0000A910B910C910DE06A463146404600F0F1
+:1001B000FDFF050001D10D98B4E0D9D50125E6E792
+:1001C00041F0010118F8010F2028F9D023280CD0A4
+:1001D0002B2804D02D2805D0302809D086E041F006
+:1001E0000201EFE741F00401ECE741F00801E9E723
+:1001F00041F01001E6E700200F900AE00F98B842A6
+:1002000005DA00EB800302EB4302303A0F9208F16B
+:10021000010898F80020A2F130000A28EED398F8DF
+:1002200000002E2818BF0E9629D118F8010F2A2891
+:100230000BD1D9F80000C9F8000008F1010850F806
+:10024000042BC9F800000E9219E02D280CBF18F8F5
+:10025000010B002000220E920BE040B90E9ABA4228
+:1002600005DA02EB820403EB4403303B0E9308F102
+:10027000010898F80030A3F130020A2AEDD3ADF856
+:100280004010129898F8001000F09CFF08B118F880
+:10029000010B8DF842009DF84200682804BF98F8D1
+:1002A0000010682903D162208DF8420008E06C2814
+:1002B00004BF98F800006C2804D171218DF8421019
+:1002C00008F1010813A806904A4618F8013B02A954
+:1002D000504600F067F838B913AA02A9504600F05A
+:1002E000C9F900287FF554AF30461BE02A2882D197
+:1002F000D9F80020C9F8002052F8040BC9F80020F2
+:1003000000280F9003D540420F9041F0040108F1FE
+:10031000010884E70000000000000000686A6C74B7
+:100320007A4C000023B0BDE8F08F622820D0682806
+:1003300011D06A2803D06C2827D0712825D10868ED
+:10034000C01D20F007000860D0E9002308300860D5
+:10035000194610467047002A0A680A60106803D0E0
+:10036000121D0A6000B217E0121D0A6080B217E089
+:10037000002A0A680A60106803D0121D0A6040B2A1
+:100380000AE0121D0A60C0B20AE0002A0A680A6088
+:10039000106803D0121D0A60C1177047121D0A6051
+:1003A000002170477CB50D4611461C462E69B4F1FC
+:1003B000250200F04D811C3A00F08680121F022AAF
+:1003C00040F282800E3A00F00781521F5AD0093A5B
+:1003D0007AD0921E16D0521E35D0521E022A73D9E0
+:1003E000121F30D0521F00F09A80521E4AD0521E67
+:1003F00000F0E480D21E00F0FD80921E42D0D21E9A
+:1004000040D02BE195F83A206C2A09D06869421C4B
+:100410006A610A680A6052F8043B0A60335427E1B3
+:100420000A680A6052F8043B0A60002100930191B7
+:100430004FF0FF322A6329466A4600F096F90028F9
+:1004400040F1168101E195F83A000122FFF76DFFB6
+:10045000C5E900010023994204DA6869411C696119
+:100460002D210DE0288F810704D56869411C696141
+:100470002B2105E0C00722D56869411C6961202154
+:1004800031541CE095F83A000022FFF74EFFC5E911
+:10049000000195F83800010711D5D5E900230020A7
+:1004A000834208BF82420AD044F02000782806D157
+:1004B000686930213154401C411C69613454214623
+:1004C00068693044E86083E00868C01D20F00700D8
+:1004D0000860D0E9002308300860C5E90023D5E9A9
+:1004E0000001C80F04D06869411C69612D210DE02D
+:1004F000288F810704D56869411C69612B2105E0BB
+:10050000C00704D56869411C6961202131546869BC
+:100510003044E8602146284600F032FAA8E005F1B0
+:100520003A02507820B14FF0FF340FF6243070E0DB
+:100530001078622808D0682824D06A2812D06C2845
+:100540002ED071280ED02BE00A680A6052F8040BF6
+:100550000A6020B94FF0FF340FF60C3059E0E96A19
+:10056000017085E00A680A6052F8040B0A6020B93D
+:100570004FF0FF340FF6F0204BE0EA6AD317C0E9E2
+:10058000002375E00A680A6052F8040B0A6020B97B
+:100590004FF0FF340FF6D0203BE0E96A018067E0BE
+:1005A0000A680A6052F8040B0A6020B94FF0FF3461
+:1005B0000FF6B4202DE0E96A016059E00A680A608C
+:1005C00052F8040B0A600021C5E90001EE607821B1
+:1005D000284600F029F94BE06C2285F83A200B6898
+:1005E0000B6053F8042B0B6052BB4FF0FF340FF637
+:1005F000AC200EE095F83A206C2AF0D0086808602C
+:1006000050F8044B0860EC603CB94FF0FF340FF633
+:10061000702000F0F1FD201A76BD2E6B002E04D55F
+:10062000204600F00BFE044608E03246002120463A
+:1006300000F020FE002814BF041B3446AC6117E014
+:10064000294600F092F8002812D54FF0FF3076BD11
+:100650006869411C69612521315409E06969481CB8
+:10066000686125227254210002D0411C6961345412
+:10067000002076BD2DE9F0410E460546716B70698C
+:10068000B46A091A306A091AB069091A706A091A33
+:10069000F069091A96F838000C1B410790460DD4F2
+:1006A000002C0BDD2746B0682021A8470028B06049
+:1006B00057D0F06A401C7F1EF062F4D17369424645
+:1006C0003146284600F0ACFC00284AD1376A002F9A
+:1006D0000ADDB0683021A8470028B06041D0F06A38
+:1006E000401C7F1EF062F4D1B369F268314628469F
+:1006F00000F096FCA8BB776A002F09DDB0683021B6
+:10070000A847B06068B3F06A401C7F1EF062F5D164
+:10071000F068B169F36942183146284600F080FC60
+:10072000F8B9B76A002F09DDB0683021A847B0607A
+:10073000B8B1F06A401C7F1EF062F5D196F838001F
+:1007400041070BD5002C09DDB0682021A847B06017
+:1007500038B1F06A401C641EF062F5D10020BDE89B
+:10076000F0814FF0FF30BDE8F0812DE9F8470D46EC
+:10077000A3B02F6B002F8146904648BF6FF0004713
+:1007800000F0A4FD696B40180FF62C118128D1E907
+:100790000023CDE9012328BF4FF0FF303ED20024D3
+:1007A000002F2FDDD8F8001001AA684600F000FDE8
+:1007B0000646002E35D4D8F8000008B9761E30D48D
+:1007C000B7421FDB6869301881280AD300206863AC
+:1007D00003AA29464846FFF74DFF040012D4002023
+:1007E000686103A8D5F814A032466946504400F069
+:1007F00073FDB244C5F814A058F8040B002818BFC4
+:10080000BF1BCDD12CB903AA29464846FFF732FFBA
+:10081000044614B9002068616863204624B0BDE82E
+:10082000F0874FF0FF34F8E72DE9FC4707468A468A
+:100830003E69BAF16F0F08BF082405D04AF02001C5
+:10084000782914BF0A2410243C25D7E90023BAF1E3
+:10085000640F18BFBAF1690F9046994606D100217E
+:100860008B4203DAD8F1000869EB49090020814581
+:1008700008BF80451FD1386BE8B9082C4CD197F8D8
+:100880003800010748D530203B2586F83B0043E07F
+:1008900000280ED597F8380000F01400102808D171
+:1008A0007A6B7869121A386A121A511A0029C8BF6D
+:1008B0003962BDE8F3878DF800A0404649462246DC
+:1008C000E31700F05DFD3032D0B26D1E3A2801957D
+:1008D00004DB9DF80000A0F151018A1872554046D2
+:1008E00049462246E31700F04BFD8046894600202A
+:1008F000814508BF804503D0F86871198842DCD370
+:10090000082C09D197F83800010705D5715D302909
+:1009100002D06D1E30207055C5F13C01B9617019CF
+:10092000F860386B8142B3DA411A39624FF6EF70E2
+:10093000398F01403987BDE8F3872DE9D04306465A
+:100940000F4614464FF00008DFF8389412E0E00735
+:1009500007D542464B463046394600F029FE06464A
+:100960000F464046494642464B4600F021FE641081
+:1009700080468946002CEAD130463946BDE8D0830E
+:100980002DE9F34F054641F020048DB0D5E90089EB
+:10099000612C02AE09D0286B002848BF062003D482
+:1009A00008BF672C01D101202863D5E90023580036
+:1009B0004015401C0ED119030CD00320A8619DF8EE
+:1009C000380061381A2802D20FF2F46111E00FF2F8
+:1009D000F4610EE058004015401C0FD119030DD1F1
+:1009E0000320A8619DF8380061381A2814D30FF24B
+:1009F000DC61E868032200F06FFCD3E1194621F0C6
+:100A00000043B3F5801F10460DD20027BB4208BF3C
+:100A1000BA42019703D111E00FF2AC61E9E701AAF4
+:100A200000F098FE0AE0DFF8607307EB1352DFF87E
+:100A30005C3301921940DFF858331943C5E90001CE
+:100A4000612C0ED1E86830210170811CE9609DF8AD
+:100A5000381061290CBF7821582141706869801CC9
+:100A60006861D5E900AB2BF0004300202AF00002BA
+:100A7000834204BF8242002300F05A81612C40F07F
+:100A8000A980286B00284CBF2120401C00904046C4
+:100A9000009F7F1C49460022002300F093FED946A8
+:100AA00001988DF8082038BF89F00049001F019097
+:100AB000002FD0460DF1090040F3498140F2FF714B
+:100AC000DFF8D0B20C91064640464946002200238A
+:100AD00000F090FE80F03A814800400D00F11C02C9
+:100AE00010D0002A0EDD0C98824205DB09F0004090
+:100AF00040EA0B01002013E0A448084040EA0251FC
+:100B000040460DE029F00043002028F00002834217
+:100B100008BF82420FBF40461C22404600F082FEC2
+:100B20008046894600F01CFFFF1F002F044609DDA8
+:100B300000F034FF02460B464046494600F040FFB5
+:100B400080468946F01D072104E004F00F0200F8FA
+:100B5000012D2411002C01DD491EF6D5491E5CBF74
+:100B6000002200F8012DF9D5ECE00020194602AA78
+:100B70000A4400E05B1E12F80149491E8442F9D084
+:100B80000F2804D10DF10900425C521C4254002987
+:100B900004D50198001D02AE5B1C0190591E12D4B1
+:100BA0009DF838007218147804F130085FFA88F460
+:100BB000392CC4BFA0F13A04A044491E02F80189AF
+:100BC000F1D58DF83800286B002840F1B080591E0F
+:100BD0002963ACE0404649460022002300F0F2FDC4
+:100BE000019938BF89F0004947F2975041436A4A5A
+:100BF00091FBF2F20192D2F1070204DD4046494630
+:100C0000FFF79BFE0AE0524200206449FFF795FE81
+:100C100002460B464046494600F044FF8046662C9B
+:100C2000286BDFF87CB106BF019F0A3706273F1803
+:100C3000142FC8BF142730208DF8080089460DF105
+:100C4000090000E03046002F34DD064640464946A4
+:100C500001F04CF801460A4606F1080304200A2672
+:100C6000B2FBF6F606EB860EA2EB4E02303203F82C
+:100C7000012C0A22B6FBF2F202EB820EA6EB4E0624
+:100C80003036401E03F8026DE9D1083F002F03F112
+:100C90000806D7DD084601F03DF802460B464046FF
+:100CA000494600F08DFE00225B4600F081FC804644
+:100CB0008946CBE70DF10901401A0DF1090604E060
+:100CC0000199491E401E0191761C31783029F7D0D8
+:100CD000662C02D10199491C03E0652C0CBF01214F
+:100CE00000212B6BCB189842B8BF431E002B1ED49B
+:100CF000834204DAF05C3528A8BF392000DA3020BE
+:100D00001946721E02EB010800E05B1E18F80199FB
+:100D1000491E8145F9D0392802D1705C401C7054BD
+:100D2000002904D50198401C16465B1C01900198CF
+:100D300000B200901BB29DF838103246284600F0F1
+:100D400034F82FE0C61D002F3FF7BEAE30460DF140
+:100D50000901401A009903468842C8BF0B46002B80
+:100D60000DF109063FF52FAF8342BFF6FEAE0DF140
+:100D70000900C05C07287FF7F8AE0F20F6E60000F8
+:100D8000CBCCCC0C0000244002FCFFFFFFFF0F8007
+:100D90000000E03F0000F07FA08601000000F03F6F
+:100DA00084D797410FB0BDE8F08F2DE9F84783B0A5
+:100DB00006468A461746984600F0FCF9B8F1000F3F
+:100DC000406A356B90F8009003DC4FF001080FF299
+:100DD0000037BDF930404AF02000662808BF641C87
+:100DE00015D0672840F0848014F1040FC0F286808B
+:100DF000AC4280F2838096F83800641C010702D46C
+:100E0000A845B8BF454620B22D1A48BF00250FFAA5
+:100E100084FAF068B169BAF1000F25DC4A1C30236E
+:100E20004354002D03DC96F83800010703D5F06821
+:100E300000F80290521C15EB0A0FB8BF6C4220B2AA
+:100E4000441941424445B8BFA046B26171620FFAED
+:100E500088F5F561F068B3692A463946184400F010
+:100E60003BFA641BB462C4E022B29045084417DA2E
+:100E70004246394600F030FAB0694044B061AAEB0E
+:100E80000801002D716203DC96F838100A0705D5B9
+:100E9000F16801F80090F069401CF061B562A8E0CB
+:100EA000394600F019FAB069002D5044A8EB040847
+:100EB00003DC96F838100A0703D5F16801F80090B2
+:100EC000401CB0610FFA88F08542F068B369B8BF82
+:100ED000A8460FFA88F207EB0A01184400F0FCF963
+:100EE000B0690FFA88F10844B061681A706280E056
+:100EF000BAF1610F14D14FF0700A16E0A84504DA78
+:100F000096F838100A0758BF45466D1E48BF0025A1
+:100F1000BAF1670F14BF4FF0450A4FF0650A04E0BD
+:100F2000BAF1410F08BF4FF0500AB169F368481C8D
+:100F3000B061002D17F8012B5A5403DC96F83810D5
+:100F40000A071BD5F168431CB36101F80090002D1E
+:100F500014DDA8F101080FFA88F08542F068B8BFE7
+:100F6000A8460FFA88F23946184400F0B5F9B0697E
+:100F70000FFA88F108446D1AB0617562F068B169C2
+:100F80000844002C80F800A003D42B214170811C60
+:100F900003E02D2141706442811C00206A460AE072
+:100FA00023460A2493FBF4F404EB8405A3EB4503E6
+:100FB00002F8013B401C24B2002CF1DC012806DCC5
+:100FC0004AF02002652A04BF302201F8012B48B9FB
+:100FD000302001F8010B07E0401E1DF800203032E0
+:100FE00001F8012B0028F7DCF068B2691044091AF7
+:100FF000F16196F8380000F0140010280DD17169E5
+:10100000B0694118706A4118F0694118B06A411816
+:10101000706B8142BCBF411A316204B0BDE8F087F9
+:10102000F8B505460E4617461C46002074B117F861
+:10103000011BB068A847B06030B1F06A401CF06294
+:101040000020641EF3D1F2BD4FF0FF30F2BD00006E
+:101050007072696E74665F733A20256E20646973DE
+:10106000616C6C6F776564007072696E74663A20AB
+:1010700062616420256E20617267756D656E740013
+:101080007072696E74665F733A20626164202573C2
+:1010900020617267756D656E740000007072696E14
+:1010A00074665F733A2062616420256C73206172FC
+:1010B00067756D656E7400000000000000000000A0
+:1010C0006E616E004E414E00696E6600494E4600EC
+:1010D0003000F0B40246106895681318506803EBAE
+:1010E0005004C00721D54D441FE0F0BC02F10C00B4
+:1010F000704713F8017B05F8017B491EF9D1A0B1B7
+:10110000B60813F8011B06F00306032E08BF13F8F8
+:10111000016B01EB06214942801C294405D011F8DE
+:10112000016B05F8016B401EF9D1A342DDD013F825
+:10113000016B16F0030104BF13F8011BC91C300931
+:101140000F28DAD113F8010B0F30D6E71B48704790
+:1011500030B45368D418042B09DA41B1057804F887
+:10116000015B10F8015B15B15B1C491EF3E753608E
+:1011700030BC704738B514461D4661B1FFF7E8FF33
+:1011800061686A6B204690476FF00102811A02D0B5
+:10119000491E03D005E06FF0010032BD4FF0FF3073
+:1011A00032BD0021616032BDDA6B1047034BE1E7CD
+:1011B000024BF9E70248704700000000D8100020F9
+:1011C000A01000200278C9B28A421AB11CBF10F8E0
+:1011D000012FF9E718BF00207047B1F5807F02D3D7
+:1011E0004FF0FF3070470170012070470078401EBB
+:1011F0008041C043C00F704780B508B90FF21C0092
+:1012000005490B681BB122220021984701E000F03C
+:101210008EFD222002BD0000AC170020636F6E73AC
+:10122000747261696E742068616E646C65723A20D4
+:10123000626164206D6573736167650000F101038D
+:10124000810704D010F8011B89B18107FAD1026827
+:10125000B2F10131914311F0803F04BF50F8042FE7
+:10126000F6E710F8011B11B110F8011BFBE7C01ADB
+:1012700070470000C9B2830706D0521E22D310F86F
+:10128000013B9942F7D11FE0083A13D302F104025F
+:1012900041EA012141EA014150F8043B121F21BFFC
+:1012A0004B40A3F1013C2CEA030C1CF0803FF3D02F
+:1012B000C9B2001F083210F8013B521E28BF91EA44
+:1012C000030FF8D818BF0120401E704780B5FFF704
+:1012D0003DFF006C02BD000062B38B0708D0521EB8
+:1012E00011F8013B00F8013B00F024808B07F6D198
+:1012F000830740F0208000BF103A07D330B4B1E834
+:101300003810103AA0E83810F9D230BC530724BF87
+:10131000B1E80810A0E8081044BF51F8043B40F8B9
+:10132000043BD20724BF31F8022B20F8022B44BF24
+:101330000B7803707047121F17D35B0009D151F867
+:10134000043B20F8023B1B0C121F20F8023BF6D294
+:101350000BE051F8043B00F8013B1B0A20F8023B6C
+:101360001B0C121F00F8013BF3D238BF121D521E96
+:1013700024BF11F8013B00F8013BF8D8704700008A
+:10138000B3BBD9B1B2F5803F7DD2022A1ED98C46BB
+:10139000B1FBF2F102FB11C31B0443EA1043B3FBA0
+:1013A000F2FC02FB1C3380B240EA0343B3FBF2F0D1
+:1013B00002FB103240EA0C4000237047022A05D994
+:1013C0008446B0FBF2F002FB10C270474AB105D16F
+:1013D00000F0010249085FEA300070470022002354
+:1013E000704700F0A7BC0B000200002100207047EE
+:1013F000904271EB030CF6D3B3F5803F2FD2F0B5DA
+:10140000B3FA83F7B1FA81F4A7F10F0E3D1B5340F5
+:10141000CEF1200602FA0EF2F3415340B5F10F0768
+:1014200046D80F3C2C444140C4F12006A040F14175
+:101430004140B1FBF3F603FB1611A2FB0645001B6E
+:10144000A94102D2761E8018594180EA010221FA90
+:101450000EF362FA0EF200215A403046F0BD30B46D
+:10146000B1FBF3FC03FB1C11A2FB0C45001BA941C3
+:1014700003D2ACF1010C8018594130BC02460B4636
+:10148000604600217047B2F1807F65D3F0B5B2FAB3
+:1014900082F7B1FA81F4C7F10F063D1B22FA06F379
+:1014A00007F1110EF24120355A40B5F10F07B8D9B6
+:1014B0004140C4F12006A040F1414140B1FBF3FCA2
+:1014C00003FB1C11A2FB0C45001BA94103D2BCF17C
+:1014D000010C801859410F2F12D30F3FC90341EA65
+:1014E0005041B1FBF3F603FB1611A2FB0645D4EB0A
+:1014F000C030A94102D2761E8018594146EACC3C40
+:1015000007B34140C7F12006B840F1414140B1FB6B
+:10151000F3F603FB1611A2FB0645001BA94102D2FC
+:10152000761E8018594180EA010221FA0EF3C7F1B4
+:10153000200462FA0EF20CFA07F05A402CFA04F179
+:101540003043F0BD80EA010221FA0EF3002162FA75
+:101550000EF260465A40F0BD8C46B1FBF2F102FB40
+:1015600011C31B0243EA1063B3FBF2FC02FB1C3302
+:101570001B024CEA002043EA1063B3FBF2FC02FBBF
+:101580001C331B024CEA002043EA1063B3FBF2FC5D
+:1015900002FB1C331B024CEA002043EA1063B3FB3E
+:1015A000F2FC02FB1C324CEA0020002370470000D2
+:1015B000B0B581EA030C0CF0004C40F2FF7515EA5F
+:1015C00011541DBF15EA1357AC42AF4239E0E4197C
+:1015D00023EA455343F48013C90241F0004141EA34
+:1015E000505EC7021100A7FB020200284FF0000066
+:1015F000EEFB01204FF00001E3FB072118BF42F092
+:101600000102401800214941E3FB0E01A4F580646A
+:101610000F0302D252004041494154F101046CDDF4
+:10162000470872F1004250F1000051EB0451A1F55E
+:1016300080115CBF41EA0C01B0BD4CEA05510020AD
+:10164000B0BD05EA1357AC4214BFAF4241E050EAC7
+:10165000410E1CBF52EA430E02E061460020B0BDBD
+:1016600024423C441BD15FEA070EF6D0090302BFB7
+:1016700001460020AEF1140EB1FA81F7AEEB07047B
+:1016800001FA07FE0C37C7F1200100FA07F7C8403E
+:101690004EEA000E23EA455343F48013A2E733F0E9
+:1016A0000043B3FA83F704BFB2FA82FE77440B3FDC
+:1016B000E41BB7F1200E2FBF02FA0EF3BB40C7F1B7
+:1016C000200E22FA0EFE38BF43EA0E03BA40641C15
+:1016D00082E750EA410E14BF52EA430E6FF0000158
+:1016E0004FF4001717EB430F8ABF194617EB410F52
+:1016F000B5E74CEA05510020B0BDD4F10104B4F1C6
+:1017000020070FDAC4F12007520828BF42F0010277
+:1017100010FA07F501FA07F7E1BF2A43E040384322
+:10172000E1400FE0352C98DCC7F1200452EA40027A
+:1017300020FA07F218BF42F0010231FA07F0A14087
+:101740000A43002172F1004250F1000051EB0C01FC
+:10175000B0BD000010B5144600F002F8226010BDC4
+:10176000C1F30A5343B14A0012F5001F28D2A3F275
+:10177000FE32A1EB0251704750EA410C20D001F03B
+:10178000004C31EA0C01B1FA81F204BFB0FA80F3E7
+:10179000D2180B3AB2F120032CBF00FA03F19140AA
+:1017A00041EA0C013EBFC2F1200C20FA0CF31943B0
+:1017B0009040524240F2FD33D21A01EB0351704780
+:1017C000002270474FF4001C1CEB410F94BF1CEB30
+:1017D000430F09E041EA030C50EA4C0C52EA0C0CAE
+:1017E00003D2994208BF9042704714BF8B42824295
+:1017F000704700004FF4001C1CEB410F94BF1CEB22
+:10180000430F09E041EA030C50EA4C0C52EA0C0C7D
+:1018100003D28B4208BF8242704714BF9942904264
+:1018200070470000124254D440F2FF7C1CEA11536E
+:101830000FD0634531D09B1863453CBF01EB02518B
+:10184000704701F0004141EA0C510020AFF30080E5
+:10185000704750EA410320D001F0004C91EA0C019E
+:101860001CD0B1FA81F30B3B9A420DD9D21A9940A0
+:1018700051EA0C01C3F1200C20FA0CFC61449840A1
+:10188000531C40F2FF7CD7E7914041EA0C01C2F1C2
+:10189000200C20FA0CF3194390407047B0FA80F303
+:1018A0001533202BE0D3202AEED3203A203B9A4256
+:1018B00009D9D21A00FA03F141EA0C010020531CA5
+:1018C00040F2FF7CB8E700FA02F141EA0C01002087
+:1018D0007047524240F2FF7C1CEA11530DD0634521
+:1018E000DBD0B2EB030C3CBFA1EB025170470CF113
+:1018F000010221EA035141F4801150EA410CCCD09D
+:1019000001F0004C352A27DC30B481EA0C01B2F139
+:10191000200309DAC2F12003044601FA03F5D0409E
+:101920002843D1409C400CE0C3F12002450020FA3E
+:1019300003F418BF44F0010421FA03F091400C4372
+:10194000002174F1004550F1000051EB0C012442DC
+:1019500030BC7FF47BAF70476146002076E7000023
+:10196000C1F30A5340F2FE329B1A14DDD3F1200377
+:101970004FEAE17208DDC90241EA505141F00040EE
+:10198000D84080185040704703F2E13010B1D24384
+:1019900082F000407047002070470000C11768B116
+:1019A0004840401AB0FA80F29040D21CC907C2F5F4
+:1019B000846241EA025202EBD021400570470000E8
+:1019C00070B44FF0004591EA030F40F1B5816B40D0
+:1019D000841A71EB030603D2001BB1411219734143
+:1019E0004FF4001C1CEB410F34BF7CEB430442E07E
+:1019F0000C0DA4EB1356352E4FDC45EAC323DB0A4E
+:101A000045EAC121C912B6F120050DDD63FA05F6DC
+:101A1000EB4086EA0305124218BF45F00105C018E5
+:101A200051F100010CD213E062FA06F5F240554084
+:101A3000F3415A40B340F3405A408018594107D30C
+:101A400049085FEA30005FEA350528BF45F0010527
+:101A500001F58011420875F1004250F1000041EBA0
+:101A600004514E0016F5001F70BC38BF70470020AF
+:101A7000090D090570471CEB410F10D252EA4306CD
+:101A80000BD0BCEB410F05D80C0DAB43661E342EBA
+:101A9000B6DD02E0AB438018594170BC704770BCA2
+:101AA00070470000F0B540F2FF7581EA030C0CF0BE
+:101AB000004C15EA11541DBF15EA1357AC42AF4252
+:101AC000E5E0BC41C1F31301C3F31303801A99414C
+:101AD00043F4801304D2641E4000494180185941E8
+:101AE000C90241EA5051B1FBF3F603FB1611A2FB08
+:101AF0000675D7EBC020A94102D2761E8018594145
+:101B0000C90241EA5051B1FBF3FE03FB1E11A2FBD7
+:101B10000E75D7EBC020A94103D2AEF1010E80189B
+:101B20005941890241EA9051760546EA8E2EB1FB71
+:101B3000F3F603FB1611A2FB0675D7EB8020A94133
+:101B400002D2761E80185941C90241EA50514EEA2C
+:101B5000060EB1FBF3F603FB1611A2FB0675D7EBDD
+:101B6000C020A94102D2761E80185941C90241EA1B
+:101B70005051B1FBF3F703FB1711A2FB0735D3EB71
+:101B8000C020A94167F100070CBF004247F00107E0
+:101B900066F3D5274FEA1E31B80814F5806412DDCC
+:101BA000BD0775F1004250EB0E5051EB045111F599
+:101BB000801F5CBF41EA0C01F0BD4CF07F6141F039
+:101BC000E0410020F0BDBD076D0840EA0E5041F431
+:101BD0008011D4F10104B4F120060ADAC4F1200620
+:101BE0000200E04001FA06F3E1401843B240154319
+:101BF0000EE0342C13DCC6F1200445EA40056D08E4
+:101C000020FA06F2154321FA06F0A1400D43002107
+:101C100075F1004250F1000051EB0C01F0BD0020C5
+:101C20005FEA0C01F0BDCFB992185B41B3FA83F7BC
+:101C300004BFB2FA82F6BF190B3FB7F120062FBFDF
+:101C400002FA06F3BB40C7F1200622FA06F638BFB7
+:101C50003343BA401CB1E419641E33E77F4231F0CC
+:101C60000041B1FA81F404BFB0FA80F6A4190B3C2C
+:101C7000B4F120062FBF00FA06F1A140C4F12006FE
+:101C800020FA06F638BF3143A0403C1B1AE7AC42AD
+:101C90001ABF05EA1357AF4212E050EA41061CBFD3
+:101CA00052EA4306BFE750EA4107304661461CBF8F
+:101CB00041EA0551F0BD52EA430C08BFC143F0BDF3
+:101CC00000204FF4001616EB410F98BF16EB430FA0
+:101CD00008BF16EB410F24BFC14305E016EB430FCD
+:101CE0000CBF61464CEA0551F0BD0000400D49189B
+:101CF00040EA81200CD2490DA1F58061491C40F0D9
+:101D0000004005DBD1F11F0154BFC840C017704728
+:101D100000207047014648B1B0FA80F18840C91CE4
+:101D2000C1F58461090501EBD02140057047012010
+:101D300000F0B6B870470000841A71EB030604D2B5
+:101D40006E40001BB141121973414FF4001C1CEB93
+:101D5000410F34BF7CEB430682E00C0DA4EB13561D
+:101D6000362E7BDC012E45EAC32341DC43EA525385
+:101D700012BFD20292025B08240545EAC12141EA62
+:101D80005051D2EBC020994125D407D1B0FA80F64A
+:101D900010FA06F162D00020203608E0B1FA81F690
+:101DA000B140C6F1200220FA02F21143B0404FEADE
+:101DB000F474B4EB465434F001064FEA74040AD8C4
+:101DC000D6F50016760D04F00044F04061FA06F2F4
+:101DD0005040F1404840C00A40EA415021F00041E3
+:101DE00028BF5FEA500550F1000044EBD12135E0F7
+:101DF000DB0A45EAC121C90AB6F120050EDD42EA37
+:101E00000242120CC5F1200603FA06F6EB4042EA44
+:101E100006056D42984161F100010DE062FA06F598
+:101E2000F240554063FA06FC82EA0C02F3405A4045
+:101E30006D42904161EB030111F4801F05D1641ED6
+:101E4000620502D06D004041494121F480114308F0
+:101E500075F1004350F1000041EB045170BC704734
+:101E60001CEB410F15D223F0004352EA43060BD07E
+:101E70004FEA4C0CBCEB410F04D80C0D661E342EFF
+:101E8000B7DDEBE7801A994150EA410608BF00210F
+:101E9000E4E708BF1CEB430F28BF6FF00001DDE74C
+:101EA00080B5AFF30080024A11001820ABBEFBE7FB
+:101EB0002600020038B5040009D004F17C056868EA
+:101EC00008B900F01EF800F021F8012801D1012026
+:101ED00032BDA06A08B100F02AF800F00AF821F03B
+:101EE0002A01FFE7816000F01BF8BDE8324000F0F6
+:101EF0002EBE2068416821F49041416020688168CD
+:101F0000704700212970204600F049BF24206860F6
+:101F100020680168490849000160204600F040B986
+:101F20002068016841F001010160204670472046A9
+:101F300000F0AABD70B5044604F17C05134668683C
+:101F4000202836D149B3180027D02878012830D06E
+:101F500001222A7004F15406216533807380002029
+:101F6000E86021206860306AC8B1DFF82012C162E1
+:101F7000DFF81C02316A0863316ADFF8180248632F
+:101F80000020316A88632068216D00F12802306AE0
+:101F900001F043F818B100F00EF8012070BD21687F
+:101FA00040200862002028702068816841F080018C
+:101FB00008E0022070BD1020E8600020287020207A
+:101FC000686070478160002070BD206881684A06A3
+:101FD0007047F8B5044640F60F002568E9692A689D
+:101FE000AB6808400DD1880602D5900602D4D8000F
+:101FF00040F18980E16E00294FD02046BDE8F440D1
+:1020000008476548034204BF644E32427BD0CF0785
+:1020100009D5D60507D501262E62D4F8885045F09B
+:102020000105C4F888508D070AD5DD0708D5266854
+:1020300002253562D4F8885045F00405C4F888506C
+:102040004D070AD5DD0708D5266804253562D4F882
+:10205000885045F00205C4F888500D070CD5950648
+:1020600001D4034208D0256808202862D4F88800EB
+:1020700040F00800C4F8880008050BD5500109D5C8
+:1020800025684FF400602862D4F8880040F02000F2
+:10209000C4F88800D4F88800002870D0890607D5D5
+:1020A000900601D4D80003D5E16E09B120468847D7
+:1020B000D4F8880021688A68510602D410F0280FED
+:1020C0001AD0204600F0BEFDFFF77FFF0FD500F0CD
+:1020D00057F860B1DFF890198163A06F00F0E0FF5E
+:1020E00000284CD0A06F816BBDE8F4400847204623
+:1020F000BDE8F24001F0C4B8204601F0C1F800206C
+:10210000C4F88800F1BDC80209D5580207D54FF4BC
+:10211000801028622046BDE8F24001F039B9080677
+:1021200009D5100601D4180205D5216F39B3204610
+:10213000BDE8F440084748060FD550060DD528687D
+:1021400020F0400028602021C4F880100020206783
+:102150002046BDE8F24001F046B9080206D550001D
+:1021600004D52046BDE8F24001F05AB9C80148BF85
+:10217000002A04D52046BDE8F24001F052B9F1BD75
+:10218000816821F040018160A06F7047992C0008A0
+:10219000C72C0008CD2C000801000010200100040D
+:1021A0002DE9F84F0446DFF8C8082768DFF8C4B8FF
+:1021B0003968DFF8C4A80140A068014320690143E1
+:1021C00060690143E0690143606E014339600026A4
+:1021D0007968E06821F4405101437960B046A16913
+:1021E000DFF8880887421CBF206A0143BA68DFF81D
+:1021F000780A02401143B9604FF48075F96A606A49
+:10220000090940EA0111F9625F454FF400404FF4BB
+:1022100000714FF480624FF400634FF4805C4FF420
+:10222000005E4FF4804929D1DAF800B00BF0030BBF
+:10223000BBF1030F3ED8DFE80BF00237343A4FF022
+:10224000010AD4F81CB05746BBF5004F4FF6F07AA0
+:1022500040F01183012F09D0022F00F05482042F87
+:1022600000F08D82082F00F0C282F5E201F0C4FC7C
+:102270000146606A002840F01B8242E2DFF8ECB7BA
+:102280005F4517D1DAF800A01AF4406A27D0BAF5F2
+:10229000806F09D0BAF5006F03D0BAF5406F06D051
+:1022A00008E04FF0020A07E04FF0040A04E04FF0A4
+:1022B000080A01E04FF0100ADFF8B0B75F45C0D15F
+:1022C000BAF1000F0BD0BAF1020F49D0BAF1040FE6
+:1022D00000F08280BAF1080F00F0B080B6E301F0A0
+:1022E00083FC0146606A58B3012808BF022028D049
+:1022F000022808BF042024D0032808BF062020D0CD
+:10230000042808BF08201CD0052808BF0A2018D0C0
+:10231000062808BF0C2014D0072808BF102010D0B2
+:10232000082808BF20200CD0092808BF402008D06A
+:102330000A2808BF802004D00B2808BF284600D0F8
+:102340000120B1FBF0F0002800F08283626802EB0C
+:102350004201884203D31103814280F0A18075E3DA
+:10236000606AB0B3012808BFDFF80009EED0022888
+:1023700008BFDFF8FC08E9D0032808BFDFF8F4083D
+:10238000E4D0042808BFDFF8F008DFD0052808BF34
+:10239000DFF8E808DAD0062808BFDFF8E408D5D06F
+:1023A000072808BFDFF8DC08D0D0082808BFDFF80E
+:1023B000D808CBD0092808BFDFF8D008C6D00A2833
+:1023C00008BFDFF8CC08C1D00B2808BF4FF224406B
+:1023D000BCD0DFF8C008B9E701F0BCFB0146606A79
+:1023E00058B3012808BF0220ABD0022808BF042040
+:1023F000A7D0032808BF0620A3D0042808BF0820C0
+:102400009FD0052808BF0A209BD0062808BF0C20B3
+:1024100097D0072808BF102093D0082808BF202095
+:102420008FD0092808BF40208BD00A2808BF802001
+:1024300087D00B2808BF284683D081E7676A002F22
+:1024400084D0012F08BF4846FAD0022F08BF70463B
+:10245000F6D0032F08BF41F25550F1D0042F08BF2A
+:102460006046EDD0052F08BF40F6CC40E8D0062FDF
+:1024700008BF40F6AA2012D0072F08BF18460ED07A
+:10248000082F08BF10460AD0092F08BF084606D0FB
+:102490000A2F08BF284602D00B2F00D1802055E715
+:1024A000BAF1000F0BD0BAF1020F38D0BAF1040F15
+:1024B00000F07280BAF1080F00F0A780ECE001F0A4
+:1024C00093FB0146606A40B3012808BF02251ED075
+:1024D000022808BF04251AD0032808BF062516D0F5
+:1024E000042808BF082512D0052808BF0A250ED0E9
+:1024F000062808BF0C250AD0072808BF102506D0DB
+:10250000082808BF202502D0092808BF402572D01E
+:102510000A280CBF80250B286DD001256BE0606A6E
+:10252000002836D0012808BFDFF800682BD0022829
+:1025300008BFDFF8FC6726D0032808BFDFF8F46780
+:1025400021D0042808BFDFF8F0671CD0052808BF99
+:10255000DFF8E86717D0062808BFDFF8E46712D075
+:10256000072808BFDFF8DC670DD0082808BFDFF8B0
+:10257000D86708D0092808BFDFF8D06703D00A2839
+:1025800008BFDFF8CC677CD00B2808BFDFF80467F2
+:1025900077D0DFF8C06774E001F0DCFA0146606ACA
+:1025A00040B3012808BF022525D0022808BF042512
+:1025B00021D0032808BF06251DD0042808BF082500
+:1025C00019D0052808BF0A2515D0062808BF0C25F4
+:1025D00011D0072808BF10250DD0082808BF2025D6
+:1025E00009D0092808BF402505D00A280CBF80253E
+:1025F0000B2800D001256268B1FBF5F650080021D8
+:1026000010EB062051EB166141E0606A002836D0DD
+:10261000012808BF4FF4800633D0022808BF4FF4CA
+:1026200000162ED0032808BFDFF82C6729D0042815
+:1026300008BF4FF4801624D0052808BFDFF81C67B8
+:102640001FD0062808BFDFF818671AD0072808BF70
+:102650004FF4002615D0082808BF4FF4802610D06C
+:10266000092808BF4FF400360BD00A2808BF4FF4E2
+:10267000803606D00B2808BF4FF4004601D04FF437
+:102680000006C246002116EB52004AEB010100236E
+:10269000FEF776FE064601E04FF00108A6F5407011
+:1026A000DFF8C016884280F0D1812168CE60CFE18A
+:1026B000012808BF02251AD0022808BF042516D019
+:1026C000032808BF062512D0042808BF08250ED00D
+:1026D000052808BF0A250AD0062808BF0C2506D001
+:1026E000072808BF102502D0082808BF202575D06C
+:1026F000092808BF402571D00A280CBF80250B2867
+:102700006CD001256AE0606AB0B3012808BFDFF829
+:10271000840521D0022808BFDFF850051CD003280B
+:1027200008BFDFF8440617D0042808BFDFF84005CB
+:1027300012D0052808BFDFF834060DD0062808BFE0
+:10274000DFF8300508D0072808BFDFF82C0503D0D4
+:10275000082808BFDFF82C057AD0092808BFDFF861
+:10276000280575D00A2808BFDFF8200570D00B288F
+:1027700008BFDFF81C056BD0DFF8D40568E001F076
+:10278000E9F90146606A40B3012808BF022525D057
+:10279000022808BF042521D0032808BF06251DD024
+:1027A000042808BF082519D0052808BF0A2515D018
+:1027B000062808BF0C2511D0072808BF10250DD00A
+:1027C000082808BF202509D0092808BF402505D0C2
+:1027D0000A280CBF80250B2800D001256068B1FBBA
+:1027E000F5F1420802EB4102B2FBF0F632E0666A14
+:1027F00066B3012E2CD0022E08BF484628D0032EE7
+:1028000008BF42F6AA2023D0042E08BF70461FD06E
+:10281000052E08BF41F698101AD0062E08BF41F2C7
+:10282000545015D0072E08BF604611D0082E08BF9F
+:1028300018460DD0092E08BF104609D00A2E08BF31
+:10284000084605D00B2E08BF284601D04FF4803033
+:1028500000F014F9B6B201E04FF00108A6F1100043
+:10286000504580F0F3800AEA0601C6F342000143B6
+:102870002068C160ECE0012F07D0022F35D0042F73
+:1028800070D0082F00F0A580D7E001F0B5F901461F
+:10289000606A40B3012808BF022516D0022808BF8D
+:1028A000042512D0032808BF06250ED0042808BF2F
+:1028B00008250AD0052808BF0A2506D0062808BF23
+:1028C0000C2502D0072808BF10257AD0082808BF99
+:1028D000202576D0092808BF402572D00A280CBFD1
+:1028E00080250B286DD001256BE0606AB0B301280C
+:1028F00008BFDFF8781333D0022808BFDFF8701361
+:102900002ED0032808BFDFF86C1329D0042808BF95
+:10291000DFF8641324D0052808BFDFF860131FD048
+:10292000062808BFDFF858131AD0072808BFDFF8B9
+:10293000541315D0082808BFDFF84C1310D009280D
+:1029400008BFDFF848130BD00A2808BFDFF8401390
+:1029500006D00B2808BF4FF2244101D0DFF8341312
+:10296000606831E001F0F6F80146606A40B3012882
+:1029700008BF022525D0022808BF042521D003283E
+:1029800008BF06251DD0042808BF082519D0052832
+:1029900008BF0A2515D0062808BF0C2511D0072826
+:1029A00008BF10250DD0082808BF202509D0092808
+:1029B00008BF402505D00A280CBF80250B2800D071
+:1029C00001256068B1FBF5F101EB5001B1FBF0F6B8
+:1029D00031E0666A6EB3012E08BF484629D0022E48
+:1029E00008BF704625D0032E08BF41F2555020D0B5
+:1029F000042E08BF60461CD0052E08BF40F6CC4010
+:102A000017D0062E08BF40F6AA2012D0072E08BF06
+:102A100018460ED0082E08BF10460AD0092E08BF4F
+:102A2000084606D00A2E08BF284602D00B2E08BF43
+:102A3000802000F023F8B6B201E04FF00108A6F1C3
+:102A40001000504502D22068C66001E04FF0010836
+:102A500004F1680001214180018000214160816012
+:102A60004046BDE8F28F00001B2D000800800040AA
+:102A7000F369FFCF0038014088000058616800EB1F
+:102A80005100B0FBF1F6704790F82810CA0706D540
+:102A900002685368C16A23F400330B43536090F813
+:102AA00028108A0706D502685368016B23F4803327
+:102AB0000B43536090F828104A0706D50268536804
+:102AC000416B23F480230B43536090F828100A07CE
+:102AD00006D502685368816B23F400430B435360AF
+:102AE00090F82810CA0606D502689368C16B23F4D3
+:102AF00080530B43936090F828108A0606D502682D
+:102B00009368016C23F400530B43936090F82810F2
+:102B10004A0610D502685368416C23F480130B43B6
+:102B20005360416CB1F5801F05D15368816C23F46B
+:102B3000C0030B43536090F828100A0606D50168BD
+:102B40004A68C06C22F4002202434A607047F8B51C
+:102B5000044604F17C050020E8606FF07E4701F038
+:102B6000DBF80646206801680A0708D50097334657
+:102B700000224FF40011204600F016F860B92068DA
+:102B800001684A070AD50097334600224FF48001B6
+:102B9000204600F009F808B10320F2BD202068604B
+:102BA000A86000202870F2BD2DE9F041069C054682
+:102BB0000E4690461F462868C1693140B1420CBF9D
+:102BC0000120002040451CD114F1010FF3D001F089
+:102BD000A3F8C01B844200D314B900F015F80CE030
+:102BE000286801684A07E6D5C1690A05E3D54FF4AC
+:102BF0000062026200F008F8C16000210170032049
+:102C000000E00020BDE8F0812868016821F4D0715F
+:102C100001602868816849084900816005F17C00ED
+:102C2000202141608160704701680A6822F0C0027B
+:102C30000A6001688A6822F400028A602021C0F8D4
+:102C40008010704701680A6822F490720A60DFF809
+:102C50002011026893680B4093602021C0F8841013
+:102C60000021C16670470000FFF4FF1100127A00D6
+:102C700000093D00AAB0280080841E00006A1800E8
+:102C80005558140040420F0020A1070090D00300C7
+:102C900048E801000024F400816A00680268930695
+:102CA00044BF084600F09FBB0020A1F8560008680A
+:102CB000826822F0800282600868FFE7016841F0C4
+:102CC000400101607047806A01F02CB8F8B5846A51
+:102CD00004F1800504F1560728686E6821688A6847
+:102CE000110606D5212804D1002038802046FFF7A0
+:102CF0009BFF20688168480606D5222E04D100205B
+:102D000038812046FFF79EFFA86840F01000A860B9
+:102D10002046BDE8F24000F0B3BA806A00F15601E7
+:102D200000220A810A8000F0ABBA00000000127A8B
+:102D30000000093D00AAB0280080841E00006A1827
+:102D4000005558140040420F0020A1070090D00306
+:102D50000048E801000024F40055150000CC0C00E8
+:102D600000AA0A0000FD0F005461510000D4300099
+:102D7000FEFFFFEF694981B00A6802430A600968F3
+:102D8000084008E0664881B0016841F40021016014
+:102D9000006800F400200090009801B0704738B53A
+:102DA0008AB004466846142100F0BEFF20685D4AE0
+:102DB0005D4990423ED108685C4D40F001000860DA
+:102DC000096801F00101059105980120FFF7D2FF84
+:102DD0000C20009002210020019102900321082084
+:102DE000039100F06AF8402000F060F8082000F03D
+:102DF00064F84F482860112000F065F808B101F030
+:102E000011F94FF088500690002101200791ADF88C
+:102E10002010099006A9284601F006F908B101F032
+:102E200001F96567AC6200220021252001F03EF91E
+:102E3000252037E03F4A904236D148683E4D40F465
+:102E400080404860486800F4804005900598012063
+:102E5000FFF790FF0220FFF78DFF4FF4006000F0B6
+:102E600025F8072000F029F8C02000900221012059
+:102E700001910290032107200391049069462F4895
+:102E800001F088F92E4828600F2000F01CF808B1E6
+:102E900001F0C8F86567AC6200220021242001F02F
+:102EA00005F9242001F01FF90BB030BD009002217C
+:102EB00000200290039001917047049069464FF002
+:102EC000904001F067B968601020A8600020E860B9
+:102ED0008020286100206861A861E8612862284696
+:102EE00000F034B810B5044616492068884213D162
+:102EF00001F02CFA01F02AFA1348016821F440711C
+:102F000041F480710160026842F400420260204690
+:102F1000BDE8104001F02EBA10BD00004C00005872
+:102F200050000058008000405C00005854150020FC
+:102F30004400024000380140B4150020000400485D
+:102F400044040240002800409000005838B50400B6
+:102F500001D1012032BD2168DFF8FC02814204F179
+:102F6000240500F042F8022068700A68A0686FF338
+:102F70000E120243E0680243206902436069024383
+:102F8000A0690243E0690243206A02430A602046C6
+:102F900000F039F9A068B0F5804F04BF00216160EE
+:102FA000696A207900F014F838B1052805D2204666
+:102FB00000F043F900F012F803E000202863686392
+:102FC000A8630020A861012068700020287032BD2D
+:102FD0000860A96AE86A486060687047296B002049
+:102FE0000860696BA86B486070470AD2DFF86C0212
+:102FF00042181423B2FBF3F292002A62DFF8600257
+:1030000009E0DFF8600242181423B2FBF3F29200E9
+:103010002A62DFF85402E8617047F8B5044604F10B
+:10302000240600253078012801D10220F2BD0127B5
+:103030003770707801282FD102277770B56120682A
+:1030400007687F087F000760204600F0C0F821680D
+:10305000F06820B10A6842F00E020A6008E00868D1
+:1030600020F0040008602068016841F00A01016056
+:10307000706A0168CA0303D5026842F48072026074
+:10308000306B18B1016841F48071016020680268FA
+:1030900042F00102026001E0357002252846F2BDCF
+:1030A00038B500F1240200245178022903D004200D
+:1030B0009061012428E001680B6823F00E030B6087
+:1030C00001680D686D086D000D60516A0B6823F48E
+:1030D00080730B60012192F82030D56903F01C0346
+:1030E00099406960936AD16A5960116B31B10B687C
+:1030F00023F480730B60536B916B59600121517005
+:103100001470516901B18847204632BDF8B500F10D
+:1031100024010423CA6914680268156891F82060C4
+:1031200006F01C0603FA06F73C4210D06F070ED5D6
+:103130001468A50603D4156825F00405156000F091
+:103140003DF8C968002938D0BDE8F440084702239B
+:1031500003FA06F73C4213D0AF0711D51468A50651
+:1031600005D4156825F00A05156001224A7000F0A3
+:1031700025F800220A708968F9B1BDE8F4400847D3
+:10318000082303FA06F6344217D02B0715D5136827
+:1031900023F00E031360012291F82030CC6903F074
+:1031A0001C039A40626001228A614A7000220A7000
+:1031B000096911B1BDE8F4400847F1BD91F820203C
+:1031C000CC6902F01C02934063607047000078B540
+:1031D000C56C046D6C60446D14B1846DC56D656023
+:1031E000012590F84440066C04F01C04A54075606D
+:1031F000046863608068102802D1A260E16071BD3C
+:10320000A160E26071BD416C0268134B89089A426B
+:1032100034BF164B164B03EB8101816402F0FF02B1
+:10322000083A1421B2FBF1F1124AC26401F01C0108
+:10323000012202FA01F10165704701790E4A02EBA1
+:1032400081024265491E0D4A826501F00301012297
+:103250008A40C2657047000008040240F8FFFDBFC5
+:1032600000000240F8FBFDBF0004024000080240DD
+:103270001C08024080080240FC080240400902404D
+:103280007047000010B500F17C010A78012A01D1D5
+:10329000022010BD01230B7024224A6002681368CB
+:1032A00014686408640014600022426623F000532E
+:1032B00000680360202048600020087010BD70B5D1
+:1032C00000F01EF801D1022070BD00F01FF822F0BE
+:1032D000604209E070B500F013F801D1022070BD22
+:1032E00000F014F822F0606211438160204600F083
+:1032F0001AF820680660202068600020287070BDE1
+:10330000044604F17C0528780128704701222A70C0
+:103310002420686020680668026852085200026033
+:10332000206882687047FFB50FF254020FF258060A
+:10333000D2E9003402A9C1E90034D6E90071CDE92F
+:103340000071416E11B90121012213E001688A6800
+:103350008968520E02F00702490F02AC655CA45C5A
+:103360001DF801101DF80220ED00E40095FBF1F1BD
+:1033700094FBF2F2683041800280FFBD0000000043
+:103380000101010307010000080402040801010112
+:103390007047000063601D481D4B704723601D4847
+:1033A0001D4B704770B51C46002300251B4E10B105
+:1033B000022804D00AE03460FFF7F1FF02E07460F5
+:1033C000FFF7E9FF0360FEF7B5FD0346012B05D0CB
+:1033D00007D3032B04D038BF022502E0012500E00B
+:1033E0000325284670BD82B00068094A0B49904207
+:1033F00006D0094A904207D1086828B102B00047B8
+:10340000486808B102B0004702B070473C13002082
+:1034100000800040C81300200038014060170020E1
+:10342000704770474FF0B040006800F0F000B028DF
+:1034300088BFB02070472DE9F041040051D02078BA
+:1034400081064FF0B04535D5A868E96810F00C004A
+:1034500001F0030103D00C2808BF012943D12868DB
+:10346000800702D5E06900283BD0FFF7DBFF616AE7
+:10347000884207D2084600F0D0FB002831D100F086
+:1034800075FA0FE0286820F0F000014329606968B0
+:10349000206A21F47F4141EA00216960606A00F0FE
+:1034A000BCFBF0B900F0A5FFDFF80808006801F0E8
+:1034B0002FF8B0B92078C1070DD5A868E96800F0E9
+:1034C0000C00082801F0030103D00C2808BF0329D1
+:1034D0002CD12868800340F140816068002840F0CA
+:1034E0003C8101203BE2E06980B1296841F00101A3
+:1034F00000F026FB06462868800700F12B8100F0CB
+:103500000BFC801B0328F6D3032028E22868400820
+:10351000400000F0E7FB0646286800F023FAC9D017
+:1035200000F0FAFB801B0328F6D3EDE76068B0F5E6
+:10353000803F06D0B0F5A02F296807D141F4802143
+:103540002960286840F48030286006E021F480314A
+:1035500029602A6822F480222A60606860B100F045
+:10356000DBFB06462868800300F1F78000F0D4FBFF
+:10357000801B6528F6D3C7E700F0CEFB0646286817
+:10358000400C10F0010000F0E88000F0C5FB801B4B
+:103590006528F4D3B8E700F0BFFBC01B0328C0F0D8
+:1035A0001081B1E7E06878B1296841F4807100F0DA
+:1035B000C7FA06462868400500F1168100F0ACFB0A
+:1035C000801B0328F6D39FE7286820F4807000F062
+:1035D00089FB06462868800A10F0010000F0DB80B5
+:1035E00000F09AFB801B0328F4D38DE700F094FBD6
+:1035F000C01B0328C0F00A8186E740F0010000F0FC
+:10360000C6F907467068800700F11B8100F084FB53
+:10361000C01B0328F6D377E7706820F0040000F0A1
+:10362000B6F907467068C00810F0010000F0188174
+:1036300000F072FBC01B0428F4D365E7052830684E
+:1036400006D140F004003060316841F0010105E02E
+:10365000400840003060316821F004013160A0680A
+:1036600041F2893768B100F057FB80463068800727
+:1036700000F10B8100F050FBA0EB0800B842F5D33D
+:1036800042E700F049FB8046306800F06BF900F03B
+:10369000FC8000F041FBA0EB0800B842F4D333E714
+:1036A00000F03AFBC01B0328C0F0FD802CE7B06897
+:1036B00040084000B06000F02FFB0746B06800F003
+:1036C00051F900F0F48000F027FBC01B0328F5D36C
+:1036D0001AE700F021FB801B0328C0F01A8113E7D2
+:1036E00000F01AFB001B0328C0F034810CE72868A7
+:1036F00081010CD4296841F080712960E86840F0AC
+:103700008050E86000F008FB04462868810100F161
+:10371000258100F001FB001B0328F6D3F4E60C29F9
+:1037200030D0286820F080702860E9688908890016
+:10373000E960E86820F08050E86000F0EDFA0446A7
+:103740002868810140F10A8100F0E6FA001B032895
+:10375000F6D3D9E600F00AF9ACE6207881071AD54D
+:10376000A868E96800F00C00042801F0030104D007
+:103770000C2808BF02297FF415AF2868400503D53F
+:10378000E06800283FF4ADAE6968206921F0FE4191
+:1037900041EA006169602168DFF81C6511F0180FCB
+:1037A00038D0606900283FF437AFC90670687FF5EC
+:1037B00024AF800709D4706840F0010000F0E7F8FA
+:1037C0000746706880077FF5E6AE706840F0040039
+:1037D00000F0DDF80746706800070DD400F09CFA91
+:1037E000C01B0428F7D38FE66868216920F0FE40EB
+:1037F00040EA01606860CEE77068A16920F47060FB
+:1038000040EA0120706000F0BFF8074600F0A9F818
+:103810007FF4ECAE2078410737D5DFF8A074386824
+:10382000C10529D400F092FD00F076FA8046386890
+:10383000C10521D400F070FAA0EB08000328F6D3EC
+:1038400062E6706820F0040070607068C00810F0D4
+:103850000100DFD000F060FAC01B0428F5D353E666
+:1038600000F092F8074600F07CF8D3D000F054FA4C
+:10387000C01B0328F7D347E6A06801287FF4DEAE1B
+:10388000306840F001003060E9E6217848060ED546
+:10389000A06A00283FF40BAFB16841F00101B160AC
+:1038A00000F03AFA0746B06880077FF5F9AEE06AA3
+:1038B000002853D0A968EA68022801F00C017FF4BF
+:1038C0002EAF236B02F00300984202BF02F070009B
+:1038D000636B984214D1A36BC2F30620984202BFD7
+:1038E00002F47810E36B98420AD1236C02F0606016
+:1038F000984202BF02F06042606C82423FF4F7AE31
+:103900000C293FF4EEAD286820F0807000F0EAF951
+:103910000646296888013FF5DCAEE968DFF8A003B8
+:10392000A26B0140206B0143606B0143E06B41EAF5
+:1039300002210143206C0143606C0143E960286867
+:1039400040F080702860E96841F08051E96000F043
+:10395000E3F90446286881017FF5C2AE0020BDE886
+:10396000F0817068400810F0010070472968606AB3
+:1039700021F0F001014329606868216A20F47F404A
+:1039800040EA01206860704770684008400070603D
+:1039900000F0C2B92DE9F8430400884644D0DFF8AE
+:1039A000246300F0C8F847D200F0CDF8074600F0D5
+:1039B000C2F841D000F0B0F9C01B0228F7D90320AB
+:1039C000B7E000F0A9F9401B022843D9F7E700F05F
+:1039D000A3F9A0EB090002284CD9F0E700F09CF90C
+:1039E000A0EB0900022854D9E9E700F095F9401B43
+:1039F00002285DD9E3E700F08FF9401B022867D960
+:103A0000DDE700F089F9401B484577D3D7E7032865
+:103A100002D13968890103E00028396802D1890799
+:103A200062D401E049055FD4012082E000F074F91E
+:103A3000C01B022872D9C2E7207881074FF0B04737
+:103A40000BD5B968A06821F0F0010143B96000F01E
+:103A500063F90546B868C003B3D52078DFF8505243
+:103A600081060AD52968606921F0F001014300F060
+:103A700067F8814628688003A9D5207841060BD5D0
+:103A80002968A0690909090141EA101100F058F8F4
+:103A900081462868C003A1D5207841070BD5B968B5
+:103AA000E06821F4E0610143B96000F035F90546B2
+:103AB000B868800399D5207801070CD5B8682169CA
+:103AC00020F4605040EAC100B86000F025F90546D6
+:103AD000B86840038FD52078C10717D560680228E1
+:103AE00095D1396889039FD5B968890840EA810072
+:103AF000B86041F2893900F00FF90546B86861688D
+:103B000000F00C00B0EB810F7FF47BAF306800F069
+:103B10000700804505D200F016F8074600F00BF8C4
+:103B200084D100F066FC00F029FDBDE8F24300F00E
+:103B3000EFBCBDE8F283306800F0070040457047F5
+:103B4000296000F0E9B83168C90848EAC10131606C
+:103B500000F0E2B838B54FF0B0445C4DA16811F008
+:103B60000C0106D1FFF75EFCC0F3031055F82000EE
+:103B700032BD0429564A05D00829564804D1216887
+:103B8000C90222D5104632BDE16801F003010229C5
+:103B900004D0032904D12168C90207D5104605E0E5
+:103BA000FFF740FCC0F3031055F82000E168E2681D
+:103BB000E368C1F306214843C2F30211491C5B0FBD
+:103BC000B0FBF1F05B1CB0FBF3F032BD80B5FFF74A
+:103BD000C1FF3D49FFE7404A0968C1F3031152F8AC
+:103BE0002110B0FBF1F002BD80B5FFF7EFFF00F050
+:103BF00010F8C1F3022106E080B5FFF7E7FF00F0FF
+:103C000008F8C1F3C22112F8211001F01F01C840C9
+:103C100002BD2D49314A0968704770B52B49B1285A
+:103C20002EBFCC6AC0F3031051F82040204805682D
+:103C300000F0BEFC28492A4A05F00F0551F825106E
+:103C4000B4FBF1F10024B1FBF2F1B0F5007F0FF20B
+:103C5000B802204609D10FF2940353F820508D4248
+:103C600014D2401C0328F8D912E00FF2900353F845
+:103C700020508D420AD2401C0328F8D308E000F0FF
+:103C80004BF8801B03280BD3032070BD52F8204053
+:103C90000C4D2868C00844EAC00000F023F806462E
+:103CA000296801F00701A142E9D1002070BD0000A0
+:103CB000080100589410002090000058000400589B
+:103CC0008C80C1110040005808000058D044000802
+:103CD0000024F4000048E8019044000844820008F1
+:103CE00040420F00286000F017B8000012000000EA
+:103CF0002400000036000000400000000600000024
+:103D00000C00000010000000000000000100000096
+:103D1000020000000300000001480068704700BF77
+:103D20009010002070470000002200F049BC000005
+:103D3000AC4900E0AC4981B00A6802430A600968F6
+:103D400008400090009801B0704710B500F002FCE8
+:103D5000A64C606840010ED56068C0000BD400F02E
+:103D6000F5FA00F0F3FA206840F480302060216812
+:103D700021F48031216000F0FAF8002000F03AFCD4
+:103D800040B180799A49E160E16821F47C5141EACF
+:103D90000021E16000F048F89648974C0168002245
+:103DA0000260026902F0500202610120FFF7C2FFC7
+:103DB0000220FFF7BFFF0420FFF7BAFF0120FFF743
+:103DC000B7FF0220FFF7B4FF00220F210E2000F002
+:103DD0006DF90E2000F087F900220F213A2000F043
+:103DE00065F93A2000F07FF90021844841600F21F5
+:103DF0008160046047F6FF71C1600021016181614B
+:103E0000C16100F009FCCA206062FF21532060629A
+:103E1000A068C008C000A060616200F0A1FC4FF083
+:103E2000FF3000F01BFDFAE730B5A9B017A8482114
+:103E3000FFF77AFF01A81C21FFF776FF08A83C21B5
+:103E4000FFF772FF69486E4C016821F018010160AC
+:103E50004FF48032206820F4C06040F4007020608D
+:103E60004FF48075216801F4C0610091072100982A
+:103E7000179101201990002140201B901892229147
+:103E80001A9517A8FFF7D7FA6F200190022100209A
+:103E9000029103900490059006900790012101A8DB
+:103EA000FFF778FD43F60300089000214FF48040AF
+:103EB000139009910A9110200221159014911295E6
+:103EC00008A800F0BCFDE06920F07000E0614D48FA
+:103ED0000168C1F303200090009830B9E169090935
+:103EE000090141F00401E16108E00098E169801EE8
+:103EF00080F30400090940EA0110E061E06940F440
+:103F00000040E06129B030BD10B53F4C3F4800F0A3
+:103F100021F820626062A06260660BE010B53C4C44
+:103F20003C4800F017F84FF40040E06100202062A8
+:103F30006062A0622046FDF7BDFF00212046FFF72A
+:103F4000BEF900212046FFF7C5F92046BDE8104024
+:103F5000FFF798B920604FF4E13060600020A06066
+:103F6000E06020610C2060610020A06170472A4859
+:103F700081B0016841F4801101603F21006800F4C4
+:103F8000801000900098254841604161016841F42B
+:103F90007C110160026942F47C120261016841F007
+:103FA0003F010160026942F03F02026101B07047C7
+:103FB00038B50446FFF7B0FE14F1010F054609D0ED
+:103FC00000F0DFFA041905E01548016821F004014A
+:103FD000016030BFFFF7A0FE401BA042F4D331BD0B
+:103FE00000000000480000584C00005890000058A5
+:103FF000FECAFECA8008005800280040E0160020D3
+:10400000000400585875FF1F3C130020008000403A
+:10401000C81300200038014050000058040C00581C
+:1040200010ED00E07047000018B500F12402507850
+:1040300001281BD11378012B01D1022012BD536A34
+:1040400010701C680A48044008680443C868401E91
+:1040500044EAC04448680443087A497A44EA004480
+:1040600044EA41241C600020107012BD012012BDE2
+:10407000FFFD00E00901020081B002D43C488154F8
+:1040800005E03C4802F00F02104400F8041C01B0A7
+:104090007047394A13684FF6FF0100020B4000F4E5
+:1040A000E0601843354908431060704738B5324B1B
+:1040B0001C68C4F30223C3F10704052C28BF0424A1
+:1040C0001D1D072D34BF0023DB1E012505FA04F456
+:1040D000641E2140994005FA03F35B1E1A40114308
+:1040E000BDE83440C6E7010007D4012200F01F01FB
+:1040F000234B8A40400943F82020704701000BD42D
+:10410000012200F01F011F4B8A40400943F8202084
+:10411000BFF34F8FBFF36F8F704710B5401EB0F1E4
+:10412000807F01D3012010BD174C60600F214FF03C
+:10413000FF30FFF79FFF0022A260072020600020D1
+:1041400010BD010007D4012200F01F010F4B8A406F
+:10415000400943F820207047010007D4012200F0F5
+:104160001F010B4B8A40400943F820207047000094
+:1041700000E400E018ED00E00CED00E00000FA05BE
+:1041800000E100E080E100E010E000E000E200E09B
+:1041900080E200E02DE9F84F4FF0000C644A654BD7
+:1041A000DFF894814FF00F0982460F4633E0634DEC
+:1041B000AA4514BF072504258D40254348F82E50F5
+:1041C000C1431C6801EA040E7C68E50348BF40EA6D
+:1041D0000E0EC3F800E05C6801EA040E7C68A503DB
+:1041E00048BF40EA0E0EC3F804E0146801EA040E6A
+:1041F0007C68E50248BF40EA0E0EC2F800E0546851
+:1042000001EA040E79688C0248BF40EA0E0EC2F83B
+:1042100004E00CF1010C396831FA0CF076D0012081
+:1042200000FA0CFE1EEA0100F3D07C68022C18BFD5
+:10423000122C4FEA8C0110D14FEADC040AEB840403
+:1042400001F01C05266A09FA05FB26EA0B06D7F8D9
+:1042500010B00BFA05F5354325624FEA4C040325EF
+:10426000DAF8006097F804B0A540ED430BF0030BBB
+:104270002E400BFA04FB4BEA0606CAF800607E6883
+:10428000012E18BF022E03D0112E18BF122E17D1E7
+:10429000DAF80860D7F80CB02E400BFA04FB4BEAB2
+:1042A0000606CAF80860DAF8046026EA0E0E7E6890
+:1042B000C6F3001606FA0CF646EA0E06CAF80460C3
+:1042C000DAF80C603540BE6806FA04F42C43CAF8EC
+:1042D0000C407C68E4009CD54FEA9C0E58F82E50A8
+:1042E00001F00C0109FA01F425EA0404BAF1904F37
+:1042F00008BF002509D0124DAA4508BF012504D0EA
+:10430000104DAA457FF453AF022555E7BDE8F18F64
+:1043100081B0002A14BF8161816201B070470A4AEE
+:10432000136803421CBF106000F08ABA7047000097
+:10433000000800588008005808000140001000489C
+:1043400000040048000800480C08005802480168B2
+:1043500041F4807101607047000400588A60FF21B9
+:1043600002685162012180F82110002180F820109C
+:104370000020704790F82010012901D102207047D9
+:10438000012280F82020022180F82110CA21026831
+:10439000516253210368596201688A6842F0200221
+:1043A000FFF7DCBF3249002008604FF4E0223148BB
+:1043B000016841F4700101604FF0B041086840F0BD
+:1043C000010008608A602C480A6802402B480A6095
+:1043D000036823F0050303604268520852004260FC
+:1043E00000222748C860086820F4802008608A619D
+:1043F00070474FF0B0410FF2D8000A68C2F30312C1
+:1044000050F822008A6802F00C02042A04D0082A1C
+:1044100004D00C2A04D01CE01A481AE01A4818E00C
+:10442000CA68CB68C3F3021302F003025B1C022AC2
+:1044300008BF144802D0032A08BF1348B0FBF3F2A8
+:10444000C868CB68C0F306205B0F42435B1CB2FB1D
+:10445000F3F00E4A0FF23803106088681168C0F359
+:10446000031053F82000B1FBF0F01060704700001B
+:1044700008ED00E088ED00E0FBFEF6FA940000583D
+:10448000001004220024F4000048E8019C100020E1
+:104490000100000003000000050000000100000012
+:1044A00001000000060000000A00000020000000DB
+:1044B00002000000040000000800000010000000DE
+:1044C0004000000080000000000100000002000029
+:1044D000A0860100400D0300801A060000350C0084
+:1044E00040420F0080841E0000093D0000127A0047
+:1044F0000024F40000366E010048E801006CDC0284
+:1045000000000000000000000000000000000000AB
+:1045100070B50F4E0446B0680025A8B1FFF756FBF2
+:10452000B2684FF47A71B1FBF2F1B0FBF1F0FFF732
+:10453000F4FD48B9102C07D2002221464FF0FF307D
+:10454000FFF7B4FD746000E00125284670BD00BF90
+:1045500090100020134810B5016841F4807101608B
+:104560000320FFF796FD0020FFF7D2FF002400286C
+:1045700014BF0124FEF706FC204610BD0A4840681F
+:104580007047094880687047084805E00748016897
+:1045900041F0020101607047016841F001010160D2
+:1045A000704700000040005890100020042004E0F4
+:1045B000DFF80800006800F4C0607047000400588D
+:1045C00000B500BF130096469446103928BFA0E8F6
+:1045D0000C50FAD85FEA417C28BF0CC048BF40F8B5
+:1045E000042BC90728BF20F8022B48BF00F8012B75
+:1045F00000BD000001460648064AC3798B4218BF39
+:10460000904218BF0838F8D18B4218BF002070477D
+:10461000F873FF1F0070FF1F38B5040044D094F8F2
+:10462000210028B9002184F820102046FEF75AFC0A
+:1046300000F049F8FF2510B100F03FF834E02168A0
+:10464000DFF8B0008A6802408A6021688A6863687F
+:1046500020690343A06903431A438A602168E06824
+:10466000086120680169A26841EA0241016120688D
+:10467000C16821F08001C1602068C16C890889008F
+:10468000C1642168CA6CE369606903431A43CA6460
+:1046900020688168880609D400F020F830B12068CD
+:1046A0004562042100F01FF8012032BD20684562F8
+:1046B000012184F82110002032BD206845620421C8
+:1046C00084F821107047022084F82100CA20216854
+:1046D0004862532022685062204626E020460BE0C4
+:1046E0002068C0F8248084F82110002084F820007D
+:1046F00070470000BFFF8FFF70B5044640F2E936F7
+:104700002068C16821F0A001C160FFF705FB0546E4
+:104710002068C168880606D4FFF7FEFA401BB04245
+:10472000F6D3032070BD002070BD70B5044620682C
+:10473000C1684A0612D44FF0FF32C26040F2E93637
+:10474000FFF7EAFA05462068C168480606D4FFF775
+:10475000E3FA401BB042F6D3032070BD002070BDC9
+:1047600010B52548254C88B0016841F4004101602E
+:1047700000F044FA2249002000F0D1FB00F01BFDBC
+:104780000121012000F03FFA002000F052FE01203C
+:1047900000F04FFE022000F04CFE012000F071FE00
+:1047A0000121002000F081FE0121012000F07DFEAA
+:1047B00000F0D2FE134A0021102000F0B2F804F2FB
+:1047C0003C500FF245010090019169460FF23D0007
+:1047D00000F0B0FF04F25470029004F5C96140F299
+:1047E0003C5005900391049402A800F03BFF00F0B8
+:1047F000B1FE08B010BD0000080000582C80002059
+:10480000E0160020775700087047000080B500F0E0
+:10481000E1FC01F033F8BDE804400021012000F084
+:10482000F2B970474FF0FF3000F018B800211020A7
+:1048300000F084B8022000F0A3B8022000F0A8B86D
+:10484000012804D0102804D0402804D0704701F07B
+:1048500057B901F057B901F059B900002DE9FC47EB
+:10486000594CDFF86891A5692840A0614FF0010A12
+:104870004FF0FF3830E0491C54F831000642FAD0BE
+:1048800004EBC107184079681040014208BFC7F81F
+:1048900004807E68304000F09BF860620AFA00F005
+:1048A00086437E60EFF3108172B6626A20690AFA6D
+:1048B00002F2D24310402061022004EBC00353F8FF
+:1048C000086C1640401E43F8086CF6D181F310883E
+:1048D000606A59F82010884763692069A269184006
+:1048E000104207D0E069216A084203D1002103EA9F
+:1048F0000206C1E701F098FDEFF3108972B6216955
+:1049000060690140A069014201BFE169206A01427A
+:10491000FFF787FF89F3108801F087FDA561BDE8E7
+:10492000F38738B51446EFF3108572B600F050F8EF
+:10493000264941F8204085F3108831BD10B5EFF3CA
+:10494000108272B6204B1C6904431C6153F831403D
+:10495000204343F8310082F3108810BDEFF310813B
+:1049600072B6194A536923EA000005E0EFF310819B
+:1049700072B6154A53691843506181F31088704725
+:10498000EFF3108172B6104AD3691843D061F4E78F
+:104990002DE9F0410C4C626A266A2062012101FA7D
+:1049A00002F803E039464046FFF73CFF276AE56915
+:1049B0003D42F7D0404600F00BF825EA0707E761D3
+:1049C00026626062BDE8F081681000205414002067
+:1049D00002460020110C090404BF1020120412F03A
+:1049E0007F4F04BF083012020FF2180112F0704F0F
+:1049F00004BF001D1201120FC0F11F00895C401A94
+:104A000070470000040302020101010100000000E0
+:104A100000000000DFF8D8110A68030903F47F23BF
+:104A200000019A4300F47F20DFE0DFF8C42113681F
+:104A3000010C23EA014343EA0043136070472DE968
+:104A4000F041054600272868DFF8A8610105B8464F
+:104A50002FD53468A86A04F44074844229D0FFF743
+:104A600075FC002C316805D1A86A21F4407101431E
+:104A700031601DE0306840F48030306021F44071D6
+:104A8000326822F480323260A86A014331603068B3
+:104A9000C0070DD5FFF740F9044641F28938306868
+:104AA000800705D4FFF738F9001B4045F7D30327EB
+:104AB000B8462878DFF84041C10705D5E16F68683E
+:104AC000890840EA8101E1672878810705D5E16F0F
+:104AD000A86821F440610143E1672878C10644BF1A
+:104AE0006869FFF7A2FF2878810644BFA869FFF72D
+:104AF0009CFF2878410744BFE868FFF78BFF2878C0
+:104B0000010744BF2869FFF785FF2868C1050AD55A
+:104B1000E16FE86921F040610143E167E869B0F1C4
+:104B2000006F00F05CF8286881051BD5286AB0F199
+:104B3000804F18BFB0F1004F00D018B9E16F21F0DD
+:104B4000404108E0E16F21F04041E16720F08050F2
+:104B5000E16F21F040610843E067286AB0F1C05F6F
+:104B600000F03DF8286841050AD5E16F686A21F038
+:104B700040510143E167686AB0F1005F00F029F835
+:104B80002868C10405D57168E86A21F440410143F1
+:104B90007160286881040BD5A169686B21F0300130
+:104BA0000143A161A169286B890840EA8101A161E3
+:104BB000286841040AD5E16FA86B21F440710143D4
+:104BC000E167A86BB0F5007F00F003F84046BDE850
+:104BD000F08103D1216841F480312160704703D115
+:104BE000216841F080712160704710430860704770
+:104BF00088000058900000580C0000580C48002114
+:104C000001604160704710B500F00CF85C6819B1A4
+:104C1000012904D1204301E024EA0000586082F316
+:104C2000108810BDEFF3108272B6014B7047000080
+:104C300068170020DFF83C150A6892B200E00246CF
+:104C4000086880B28242FAD170472DE9FC410446DF
+:104C50001825DFF82485DFF82465684308EB000792
+:104C60003078062808D131787170347078754FF03B
+:104C7000FF307060002039E000F077F8B96809185B
+:104C8000B96008F10803B96832786A439A589142CA
+:104C9000327813D308F1150315FB02FC13F80C301E
+:104CA000062B25D008F108066B43F358994222BF22
+:104CB00008F115036A439A5CEED219E01146337885
+:104CC00069439A420BD008F1140308F1150C5B5CA0
+:104CD00015FB03F50CF805407A753B7500E07A7515
+:104CE00008F114025454317871703470BDE8F681C3
+:104CF0001146694308F115035B5C062B04D008F1EB
+:104D0000140615FB03F574557B753A7508F1150209
+:104D10005454EBE7F8B5DFF86434DFF85C541E78E0
+:104D2000182402466243B0422A4404D118785870CD
+:104D3000507D18700FE0167D507D92F815C005F17A
+:104D400015076643062807F806C004D0167D1435FB
+:104D500014FB00F42E55012010731878062802BFAA
+:104D600000294FF0FF315960F1BD10B5DFF80C4458
+:104D7000606810F1010F0FD0FFF75CFF6168DFF88A
+:104D80000024814261683CBF5388C918081A5178D1
+:104D900048431178C84000E0002080B210BD2DE9E2
+:104DA000F84FDFF8DC53DFF8DCB3D5F80880D8F82B
+:104DB0000000DBF800104A0500F090F9DFF8BC6352
+:104DC000DFF8B4A321F4806181604FF018093478D2
+:104DD0000AF1080019FB04F14758FFF7C6FF8742A4
+:104DE00017D200270121B170062C3DD019FB04F425
+:104DF0000AF108010AF108020959814223BF0AF1A8
+:104E000008010959091A002111510AEB04014C7DCE
+:104E1000EAE7A9884118B94202D2AF880021E2E747
+:104E20003F1ADFE7022802DA2878012800D07F1E27
+:104E3000D8F80000C1684A07FAD500F055F9DBF848
+:104E40000C00000CBFB247EA0047CBF80C70FFF72C
+:104E5000F1FE7060A8680068816841F4806181603B
+:104E6000AFF30080BDE8F18FB8B20028DAD1FFF7C8
+:104E7000E1FE70600320BDE8F24FFFF762B92DE953
+:104E8000F843EFF3108872B6BD4DBB4BA8680168BC
+:104E9000CA224A6253204862B84A886820F4806077
+:104EA000886018201678374647431F44387B02280D
+:104EB00026D13C68D7F810909078F0B17A7B012A1F
+:104EC0000AD101213046FFF725FF88F31088796861
+:104ED000304600F016F904E088F31088304600F000
+:104EE000C1F8A8680068CA21416222465321416284
+:104EF0004846314600F050F90BE0FFF750FF06E05E
+:104F0000C8684207FCD500F07EF89F49086088F326
+:104F10001088FF21A86802685162BDE8F183F8B5E6
+:104F2000974CA160CA2209684A6253224A62954A94
+:104F3000136843F020031360136803F00703C3F101
+:104F40000403237095682D0C05F07F056D1C6570BA
+:104F5000EDB29268C2F30E02521C628092B2521EEF
+:104F60006A43A2F5A072DA404FF6FF739A422CBF53
+:104F7000A380A280854A136843F400231360844B06
+:104F80001D6845F400251D6048BB7C487A4E01230E
+:104F9000837018254FF0FF33436000235FFA83FCD2
+:104FA00006F10C0715FB0CFC4FF0000E07F80CE0A7
+:104FB0005B1CDFB2062FF1DB06230370886820F448
+:104FC0008060886000F01FF8D0600320FFF7C4F80D
+:104FD000A1680868826842F48042826005E0C8687F
+:104FE000410544BF0320FFF7ACF8A1680A68FF2021
+:104FF0005062002203210320FFF758F8BDE8F24079
+:105000000320FFF770B8C86800F0800060F490607B
+:10501000C8604FF400207047F0B504460025EFF358
+:10502000108672B61827DFF850C10CF10C0007FB90
+:1050300005FE10F80E0010B16D1C062DF5DB062DD7
+:105040000CD06F430CEB07000127077386F3108821
+:105050000461427303600D700020F0BD86F3108878
+:105060000120F0BDF8B50746EFF3108472B60320B7
+:10507000FFF744F8424DAE683068CA2141623A46B3
+:1050800053214162182043494243895C02291BD1C4
+:1050900000213846FFF73EFE3848017806290ED138
+:1050A000306838490A68530500F018F821F4806127
+:1050B0008160C1684A07FCD500F016F804E040782A
+:1050C000884218BFFFF76BFEA9680A68FF2050628C
+:1050D0000320FFF708F884F31088F1BD02D5C168FA
+:1050E0004A07FCD481687047C16801F0800161F40F
+:1050F0009061C1604FF40020234908600320FFF74E
+:105100002BB82DE9F04180460F46424618201A4937
+:1051100042438C18207B022804BF4046FFF7A2FFC1
+:10512000EFF3108572B60320FEF7E8FF144EB06867
+:105130000068CA2141625321416202202073A760A6
+:1051400067604046FFF781FD0C490A784978914233
+:1051500002D0FFF724FE02E0A168081AA060FF2039
+:10516000B1680A6850620320FEF7BDFF85F310881E
+:10517000BDE8F08128280040AC120020A0170020D4
+:1051800048170020082800400C0800580008005864
+:1051900080080058B812002010470000484900E07D
+:1051A000484981B00A6802430A60096808400090D3
+:1051B000009801B0704780B5FFF7E6F9FFF7E6F910
+:1051C0004148016841F48031016001F04AF9BDE8CD
+:1051D00001400EE000B587B068460FF224211C2282
+:1051E000FCF78AF800F075FA684601F087F907B015
+:1051F00000BDF0B585B068461421FEF795FD002688
+:105200000025002400210FF2E80000EBC102907994
+:1052100088B11368B3F1904F08D02C4FBB4208D02F
+:105220002B4FBB4204BF9088044304E090880643A0
+:1052300001E090880543491C2229E4DB002002900C
+:105240000121032003900191B0B288B100900120A8
+:10525000FFF7A4FF0120FFF7A3FF69464FF090403E
+:10526000FEF798FF0022B1B24FF09040FFF750F8E0
+:10527000A8B280B100900220FFF790FF0220FFF754
+:105280008FFF124E69463046FEF784FF0022A9B216
+:105290003046FFF73DF8A0B280B100900420FFF740
+:1052A0007DFF0420FFF77CFF094D69462846FEF785
+:1052B00071FF0022A1B22846FFF72AF805B0F0BD21
+:1052C0004C0000584C010058900800580004004859
+:1052D0000008004880B5FEF721FEBDE80140FEF75A
+:1052E00013BE13460A4601460020FEF75BB80000D5
+:1052F000000000480100000000000048010000001C
+:10530000000000480100000000000048010000000B
+:1053100000000048010000000000004801000000FB
+:1053200000000048010000000000004801000000EB
+:1053300000000048010000000000004801000000DB
+:1053400000000048010000000000004801000000CB
+:1053500000000048010000000000004801000000BB
+:1053600000000048010000000000004801000000AB
+:10537000000000480100000000000048010000009B
+:10538000000000480100000000000048010000008B
+:10539000000000480100000000000048010000007B
+:1053A000000000480100000000000048010000006B
+:1053B000000000480100000000000048010000005B
+:1053C000000000480100000000000048010000004B
+:1053D000000000480100000000000048010000003B
+:1053E000000000480100000000000048010000002B
+:1053F000000000480100000000000048010000001B
+:10540000000000000000000000000000F052000852
+:10541000248000202880002022040400444981B018
+:105420000A6802430A60096808400090009801B0C9
+:10543000704778B585B0044668461421FEF774FCC1
+:105440000220FFF7EBFF00F010F80095012001901B
+:105450000021022003900291694656F82400FEF7CD
+:1054600099FE00F008F806B070BD0FF2D400314E7E
+:1054700030F81450704756F8240000222946FEF7F1
+:1054800047BF0FF2BC012B4B31F8101053F820002E
+:105490000122FEF73DBF0FF2A801264B31F8101094
+:1054A00053F820000022FEF733BFF0B585B0054663
+:1054B0000C4668461421FEF737FC2DB1012D08BFBC
+:1054C000102002D0022D02D10120FFF7A7FF2000FB
+:1054D000194E0FF274070DD137F815000090002116
+:1054E0000191012002900221039100F01BF801209C
+:1054F000FEF75EFD012C13D137F815000090012155
+:105500000E480190029100F00DF80FF24400445D46
+:1055100000220F2160B2FEF7C9FD60B2FEF7E3FD85
+:1055200005B0F0BD694656F82500FEF733BE000011
+:105530004C000058501000205C100020000021108A
+:1055400020000100020000000100100040000000E7
+:10555000060A170001F04EB86C486D49016001F170
+:105560002002426001F13002826001F13C020262DD
+:1055700001F14402C26001F14C02026101F16802D2
+:10558000426101F16C0282617831C16101F044B87D
+:1055900038B504465F4D05F1100001F0A5F85B49F0
+:1055A0004868A1680160E168C160456005F11001CB
+:1055B000816001F04DF858482DE080B553494A68A4
+:1055C00013680120187201F049F8002002BD38B5B7
+:1055D000514C504D07E0694605F1100001F0B0F85C
+:1055E00000982168884705F1100001F080F8002834
+:1055F000F1D031BD48484168084738B50446474DA9
+:10560000284601F071F84148C068A1680160456012
+:1056100001F029F84248216801606168416000207A
+:1056200032BD80B53949CA6813681020187201F07C
+:1056300020F8002002BD3549CA68394910680B6856
+:10564000184738B5364C354D06E06946284601F016
+:1056500077F8009861688847284601F048F80028E4
+:10566000F3D031BD38B504462E4D284601F03CF844
+:105670002D4801F039F825480069A1688160E1688A
+:10568000C160056121680160616841602169416113
+:105690006169816131BD80B50146234801F03AF866
+:1056A000BDE802400FF2050000F0F3BF38B5174C1B
+:1056B0001D4D08E06946284601F042F8009920692E
+:1056C000006901F027F8284601F011F80028F1D010
+:1056D00031BD10B5154C204601F006F80B48416964
+:1056E0000C60BDE8104000F0E8BF1CB50F4C06E0B0
+:1056F0006946204601F024F8009800F019F8204689
+:1057000000F0F5FF0028F3D013BD0000008000205A
+:10571000B88900208C88002078170020A4880020F9
+:10572000801700203C8A002070170020448A002047
+:10573000704700007FB50C464D4D61684D4EE861E5
+:105740002962284601F00EF82468746006F108000A
+:1057500000F0CAFF012000F068F8012030702968CD
+:1057600041B10FF2E9000FF2ED02009001920294B4
+:10577000684688477FBD1FB53E4C04F1080000F025
+:10578000B6FF00BB2178F1B1694604F1080000F0D2
+:10579000D7FF3748C16949B10098029001228DF8BE
+:1057A000042001A888479DF8040000E00120207033
+:1057B000207818B10098FFF76EFF04E0009904F11B
+:1057C000080000F09DFF04F1080000F090FF28B9E8
+:1057D000207818B104F10800FFF728F81FBD2DE963
+:1057E000F04105460E4690461C46002000F01DF88C
+:1057F000204F7868A0F80950C672324641460C30F6
+:10580000FBF76AFD1A4A136900210020984748F205
+:10581000E800FFF712F879688A78D21C04F10800D2
+:10582000FBF75AFDBDE8F04101201CB51049124CB0
+:10583000096A20B901B188470020207013BD0120FA
+:10584000207011B1BDE81C40084713BD0020FEF7D1
+:10585000F1BF000010B50146064C04F1080000F04D
+:1058600059FF04F10800BDE81040FEF7DFBF00005B
+:1058700004170020381700205D17002038B58EB0BF
+:1058800002A80FF67431DFF864453022FBF734FDCF
+:105890000FF2A9500190009469460FF28950DFF889
+:1058A000504500F069FF01210220FFF7ACF9DFF855
+:1058B000442500210820FFF734F802A800F016FE66
+:1058C00000F025F901F03CF8002084F8900004F184
+:1058D00026054FF6FF70288000210FF25542012067
+:1058E000FFF71FF80FF2954200210420FFF719F887
+:1058F000062001F0B7F8DFF8000500210170012152
+:10590000417001F044F90FF26543002204F1910166
+:105910000020FFF781FB0FF25D43002204F19201AA
+:105920000020FFF779FB002068808021DFF8CC049D
+:105930000180A0214180012000F090F90FB030BD1E
+:10594000F8B50746DFF8A8447878DFF8AC540528A6
+:1059500004F1900604D03E2812D0FF285FD0CDE09D
+:10596000B888E18C884206D10020E08430700FF2C4
+:10597000E04001F017FA012000F070F9012047E043
+:10598000F87801282BD0032802D00C2803D0B5E0EA
+:105990000FF2E440A8E00FF20C5001F003FA38795E
+:1059A00000280CBF0FF218500FF23C5001F0FAF92A
+:1059B000E08C6A460DF1010101F032FA60B90FF294
+:1059C000505001F0EFF99DF800209DF801100FF202
+:1059D000545001F0E7F991E00FF2645084E07078E0
+:1059E000FFF740FBB7F805100FF2705001F0DAF93D
+:1059F000307804280CBF0620052030700021B7F84D
+:105A00000500E084E8802971281D01F0BAF8002023
+:105A10002871E08CE880281D01F0B3F86EE0B7F83B
+:105A20000300001F63D04FF47F71401A1AD0401E4C
+:105A30004BD0401E19D0401E1ED0401E1FD0401E0D
+:105A400020D0401E28D0401E4CD0401E24D0401EE6
+:105A500028D0401E23D040F2F631401A04BF012066
+:105A600068704BE00FF228503EE00FF2505001F00A
+:105A700099F90FF2705037E00FF2885034E00FF2CE
+:105A8000B05031E00FF2D85001F08CF9E08C01F009
+:105A900044FB0FF2EC5027E00FF2006024E00FF21D
+:105AA000206021E0D7F807100FF2406001F07AF98A
+:105AB000D7F807100FF24C6001F074F9E08C012167
+:105AC00001F079FB0FF250600EE0F9790FF2886077
+:105AD00001F068F9F879002814BF0FF2E8600FF2BE
+:105AE000D06001E00FF2F06001F05CF906E0012007
+:105AF000FFF7C7FCB0780A21FFF703FB0120F2BDD6
+:105B000001F05FB800210420FEF718BF704778B598
+:105B100089B00020ADF81A0001F058F9B84DB94E1F
+:105B2000286810F1010F0ED069683074090A020A62
+:105B3000000CB074727406F1100468683175F0746A
+:105B4000090A717506E00020FEF754FD040008BF45
+:105B50000FF6740422460621002000F04EFF607903
+:105B6000307207AA207970720621E078B072A078AE
+:105B7000F0726078307320789D4C70734EF66E50E2
+:105B80000890286807902E2000F037FF0FF640029B
+:105B90001021182000F031FF0FF6440210210820D8
+:105BA00000F02BFF1821012000F04EFF01F01DFB3B
+:105BB0000DF1160006A90190009105AB0722002106
+:105BC000012001F037FA0FF23860BDF8181000908C
+:105BD0000723BDF81400002201F0C7FB0DF11A00E5
+:105BE00000900223BDF81610BDF81400002201F049
+:105BF000BCFB02220221002001F045F903202070A5
+:105C000001F0CCF9012060700020E0700820607580
+:105C10001020A075012020757B48A0610120A07094
+:105C20000020C1B221440871401CC1B21029F8DB28
+:105C3000002004900023A069617803900122207D58
+:105C40000290A07D0190607D0090A07801F0BFF9E6
+:105C5000A07808B101F046FA0AB070BD2DE9F8410C
+:105C60000446012C87B003D164480588478803E0C7
+:105C70004FF4C8654FF47A67DFF8748108F1900635
+:105C80007078FFF7EFF931780FF27C5001F08AF865
+:105C9000022C11D13078012818BF02280CD101F054
+:105CA00022F9010004D10FF27C5001F07BF803E0EF
+:105CB0000FF2945001F076F83470002006900590B1
+:105CC00008F129010491082298F828000FF22071A8
+:105CD000039002910192002300933A462946002046
+:105CE00001F013F947490E2001F0D4F9010013D156
+:105CF000012C0AD10FF2785001F054F87078434922
+:105D000008B0BDE8F041FFF7FCB908B0BDE8F041CC
+:105D10000FF2845001F046B808B0012CBDE8F04104
+:105D20000CBF0FF2A0500FF2CC5001F03BB80000B6
+:105D300010B50120FFF7AFFB2D4C94F8900005281B
+:105D400012D001F0D0F8002184F8901030B90FF291
+:105D5000D85001F027F80FF2D85001E00FF2EC50C4
+:105D6000BDE8104001F01EB810BD00000021012068
+:105D7000FEF7E4BD0120FFF78EBB00001CB51C4CF4
+:105D800094F89000012818BF00282DD01A484178B7
+:105D9000012929D1002201784270491C01EBD172FE
+:105DA0005210A1EB42010170F7EE040A017800EBFA
+:105DB00081004FF4FA7190ED020AE08C0091C0EE80
+:105DC000200AFDEEE00A10EE902A92B2002311465E
+:105DD00001F00FFBBDE8164000280CBF0FF29050F9
+:105DE0000FF2BC5000F0DEBF13BD0000AC880020F5
+:105DF00018120020B76700081C000020B41700200C
+:105E00008075FF1F0400002007B2010046E001007A
+:105E100000210820FEF792BD0120FEF7B1BD012050
+:105E2000FEF7B6BD10B50446616801F1080000F048
+:105E300095FD00B10120207010BD000010B10128B7
+:105E400003D070470F20FEF789BD0F20FEF78EBDEF
+:105E50000D0A0D2A2A20444953434F4E4E454354C0
+:105E6000494F4E204556454E5420574954482043EB
+:105E70004C49454E54200A000D0A0D2A2A20434F52
+:105E80004E4E454354494F4E2055504441544520B1
+:105E90004556454E54205749544820434C49454E99
+:105EA00054200A004556545F5550444154455F50B4
+:105EB00048595F434F4D504C455445200A0000005F
+:105EC0004556545F5550444154455F5048595F43CF
+:105ED0004F4D504C4554452C20737461747573209C
+:105EE0006F6B200A000000004556545F5550444136
+:105EF00054455F5048595F434F4D504C4554452CD5
+:105F000020737461747573206E6F6B200A0000003B
+:105F1000526561645F50485920737563636573739C
+:105F2000200A000050485920506172616D202054B1
+:105F3000583D2025642C2052583D202564200A001D
+:105F40005265616420636F6E66206E6F7420737596
+:105F5000636365657373200A000000004556545F53
+:105F60004C455F434F4E4E5F434F4D504C4554455B
+:105F700020666F7220636F6E6E656374696F6E204A
+:105F800068616E646C6520307825780A0000000036
+:105F90000D0A0D2A2A204556545F424C55455F474D
+:105FA00041505F4C494D495445445F444953434F28
+:105FB00056455241424C45200A0000000D0A0D2A68
+:105FC0002A204556545F424C55455F4741505F502B
+:105FD0004153535F4B45595F5245515545535420EA
+:105FE0000A0000000D0A0D2A2A206163695F6761BB
+:105FF000705F706173735F6B65795F72657370203A
+:106000000A0000000D0A0D2A2A204556545F424C12
+:1060100055455F4741505F415554484F52495A4199
+:1060200054494F4E5F52455155455354200A000084
+:106030000D0A0D2A2A204556545F424C55455F47AC
+:1060400041505F534C4156455F5345435552495467
+:10605000595F494E49544941544544200A000000C3
+:106060000D0A0D2A2A204556545F424C55455F477C
+:1060700041505F424F4E445F4C4F5354200A000042
+:106080000D0A0D2A2A2053656E6420616C6C6F77AF
+:10609000207265626F6E64200A0000000D0A0D2AEE
+:1060A0002A204556545F424C55455F4741505F4456
+:1060B00045564943455F464F554E44200A0000006F
+:1060C0000D0A0D2A2A204556545F424C55455F471C
+:1060D00041505F4B455950524553535F4E4F5449C1
+:1060E0004649434154494F4E200A00006E756D6584
+:1060F0007269635F76616C7565203D20256C640A6A
+:10610000000000004865785F76616C7565203D2071
+:10611000256C780A000000000D0A0D2A2A20616310
+:10612000695F6761705F6E756D657269635F636FEC
+:106130006D70617269736F6E5F76616C75655F63B8
+:106140006F6E6669726D5F7965736E6F2D2D3E5946
+:106150004553200A00000000424C455F4354524C16
+:106160005F4170705F4E6F74696669636174696FD7
+:106170006E3A204556545F424C55455F4741505F4B
+:1061800050414952494E475F434D504C542C20706A
+:10619000616972696E675F636F6D706C6574652DA0
+:1061A0003E537461747573203D2025640A0000001D
+:1061B0000D0A0D2A2A2050616972696E67204F4BC3
+:1061C000200A00000D0A0D2A2A2050616972696EAA
+:1061D00067204B4F200A00000D0A0D2A2A20455641
+:1061E000545F424C55455F4741505F50524F4345C5
+:1061F000445552455F434F4D504C455445200A008D
+:106200005032505352563100466972737420696E91
+:1062100064657820696E202564207374617465203C
+:106220000A0000005375636365737366756C6C795F
+:106230002053746F70706564204164766572746970
+:1062400073696E67200A000053746F702041647692
+:106250006572746973696E67204661696C65642054
+:106260002C20726573756C743A202564200A000036
+:106270005375636365737366756C6C7920537461D1
+:106280007274204661737420416476657274697318
+:10629000696E67200A000000537563636573736657
+:1062A000756C6C79205374617274204C6F77205038
+:1062B0006F776572204164766572746973696E6781
+:1062C000200A000053746172742046617374204187
+:1062D00064766572746973696E67204661696C657E
+:1062E00064202C20726573756C743A202564200A32
+:1062F000000000005374617274204C6F7720506F5F
+:10630000776572204164766572746973696E67207F
+:106310004661696C6564202C20726573756C743AF3
+:10632000202564200A00000020200D0A0D00000036
+:106330002A2A2053544F5020414456455254495321
+:10634000494E47202A2A20200D0A0D002A2A2053D0
+:10635000544F50204144564552544953494E4720CA
+:106360002A2A20204661696C6564200D0A0D000010
+:10637000424C455F5356435F4C324341505F436F3D
+:106380006E6E5F55706461746528292C20537563A7
+:106390006365737366756C6C79200D0A0D000000DF
+:1063A000424C455F5356435F4C324341505F436F0D
+:1063B0006E6E5F55706461746528292C2046616992
+:1063C0006C6564200D0A0D006C7AD8AC5772000021
+:1063D000123456789ABCDEF0123456789ABCDEF04D
+:1063E000FEDCBA0987654321FEDCBA0987654321D3
+:1063F0000950325053525631000000000000000096
+:106400000000000000000000000000004400080040
+:10641000400508013A799C00F4010000FFFFFFFFEE
+:1064200048010100000000007047704738B5EFF3E5
+:10643000108472B6284D6946281D01F026F9694678
+:10644000281D01F07FF938B184F31088BDF80010E1
+:10645000224AFEF746FF31BD0120287084F31088E0
+:1064600031BD80B5FEF736FF0221009100231A48A6
+:1064700000F124014FF48052001D00F0EDFF01BD3A
+:1064800000BFF8B514460026EFF3108510F1010F98
+:106490001ED001281CBF02284FF0FF3618D1BCB116
+:1064A000264672B60C4F012392B2381D00F0E8FF69
+:1064B00000281CBF3978002908D000223A7085F3E3
+:1064C0001088A1B2054AFEF70CFF01E085F31088A1
+:1064D0003046F2BD000000002C0000202D640008B2
+:1064E000FFF77DF99DF80E0005B000BDF8B500F18D
+:1064F0000C026B4621214FF66640F1E7F8B500F13A
+:106500000C026B460F214FF66840E9E7C06808406F
+:10651000884201D10120704700207047C0690840BF
+:10652000884201D1012070470020704710B5664CA9
+:1065300002212046FFF7F2FF38B16068C0438107AF
+:1065400003D5FFF77EF8022018E001212046FFF76F
+:10655000E5FF38B16068C043C10703D5FFF737F8DE
+:1065600001200BE008212046FFF7D8FF38B1606812
+:10657000C043010703D5FFF7B8F80820A06010BD9D
+:1065800010B5514C00F033F818B96068C04381036E
+:1065900006D400F02CF830B96068C043810302D5FE
+:1065A000BDE810406EE0082100F022F870B9606884
+:1065B000C04301030AD56068444940F4002060608C
+:1065C000086880474FF40020A06010BD202100F033
+:1065D0000FF858B96068C043810207D5606840F47D
+:1065E00000106060BDE81040FFF704B810BD022144
+:1065F00020468BE73648016841F400710160354858
+:10660000026842F40072026040BF20BF3248016855
+:1066100041F400410160704780B53048016841F4A1
+:1066200080110160006800F48010009000982648F6
+:10663000016841F001010160026842F480320260A9
+:106640002C20FDF750FDBDE802402D20FDF74BBD8D
+:1066500023480168490849000160704721494FF407
+:106660008030086070471E48016821F00201016017
+:1066700070471B484FF400314160016821F400313C
+:10668000016070471648016841F400310160FEF76F
+:10669000D2BF38B504460C4D08212846FFF736FF17
+:1066A00030B10A480460686820F40020686031BD99
+:1066B000A0474FF40021A96031BD0948016821F0CD
+:1066C0000801016070470000000C0058A817002066
+:1066D000D4080058200800580C04005850000058F6
+:1066E000040C0058080C0058006040607047EFF33D
+:1066F000108172B6026882420CBF012000201CE0AB
+:10670000EFF3108272B603680B604860016008689E
+:10671000416023E0EFF3108272B6086043684B607B
+:1067200041604868016019E0EFF3108172B6436878
+:1067300002681A6042680068426081F310887047FE
+:1067400010B5EFF3108472B602680A600068FFE7C4
+:10675000FFF7EAFF84F3108810BD086082F3108809
+:10676000704700000249016002490161704700BFA3
+:10677000FB550008235600087FB50C466D4D616837
+:106780006D4EE8612962284601F026F8246805F17B
+:106790002400FFF7A9FF746006F10800FFF7A4FFCB
+:1067A00001203070296829B10FF255100090029431
+:1067B000684688477FBD1FB55F4C04F10800FFF7AE
+:1067C00096FF00BB2178F1B1694604F10800FFF79C
+:1067D000B7FF5848C16949B10098029001228DF86D
+:1067E000042001A888479DF8040000E001202070E3
+:1067F000207818B10098FEF74EFF04E0009904F1EC
+:106800000800FFF77DFF04F10800FFF770FF28B9CB
+:10681000207818B104F10800FFF7FAFA1FBD2DE93E
+:10682000F8430646002000F05FF874883088B268AC
+:10683000DFF80081C4F3090444EA8024F068A4B2BC
+:10684000C1B2204600F03CF8002748F2E80948466B
+:10685000FFF7E5FA08E06888A04202D1316928789C
+:106860000870687800B1012708F12400FFF73FFFA6
+:10687000F0B9694608F12400FFF762FF009800F1C3
+:106880000B05407A0F28E6D0B5F80110A1420DD1D2
+:106890000098817AC81E7169C0B28842C8BF084694
+:1068A000706102463069E91CFAF716FD2878D9E7CD
+:1068B0003800CCD0012000F017F80020BDE8F283AA
+:1068C00010B513461C4A5468A4F80900E1720A4640
+:1068D000194604F10C00FAF7FFFC164A1369BDE8EB
+:1068E00010400021002018471249096A82B008B9F7
+:1068F00021B101E011B1012002B0084702B0704798
+:1069000010B50146487A0F2818BF0E2807D10B484A
+:10691000FFF700FFBDE810400020FFF77DBA064CEE
+:1069200004F10800FFF7F6FE04F10800BDE810408E
+:10693000FFF76EBAB416002028170020D8160020E2
+:106940001B4800210171017200F034B818490A791E
+:1069500041F822000879401C0871704770B5044660
+:106960006078FF2802BFB4F8031001F47F41B1F54D
+:10697000406F12D100260E4D00E0761C2979F0B24E
+:1069800088420AD2F1B255F821102046884701000A
+:10699000F3D002D0022805D006E02046BDE87040C2
+:1069A000FEF7CEBF002070BD012070BD00000000CA
+:1069B0005417002080B500F019FF00F018FF00F018
+:1069C00017FF00F016FF00F015FF00F014FF00F0B5
+:1069D00013FF00F012FF00F011FF00F010FF00F0B5
+:1069E0000FFF00F045FF00F0FDFF00F0FCFF00F09E
+:1069F000FBFFBDE8014000F0F8BF18B50C46C7B07A
+:106A0000114600228DF800208DF81C008DF81D40E5
+:106A100022460DF11E0000F0E9FF00F03BF83F2098
+:106A20000C21ADF80400ADF8061007A80121039071
+:106A30000691A41C049400F043F800284CBFFF20EA
+:106A40009DF8000048B010BD00B5C7B000F01BF8BD
+:106A50000F2000F02AF800284CBFFF209DF800000E
+:106A600047B000BD00B5C7B00021ADF81C0000F074
+:106A700016F8182000F019F800284CBFFF209DF8E8
+:106A8000000047B000BD00228DF800208DF81C00EA
+:106A90008DF81D101822002101A800F0ADBF8DF85F
+:106AA0000010182201A800F0A7BFADF8060007A942
+:106AB000022004903F22012003910690ADF80420AB
+:106AC000CDF814D0002101A8FFF7A9BE70B5064685
+:106AD0004E4C30784CA520B1012807D0032810D0A7
+:106AE00070BD012020700FF2281003E000212170FA
+:106AF0000FF2501000F056F92846BDE8704000F043
+:106B000051B971680878C8B94978012909D1FEF7E7
+:106B1000B8FC0FF2641000F045F900F02FF80120E6
+:106B2000A0707168487848B9FEF7B5FC0FF2701094
+:106B300000F038F900F022F80020A07070680178A9
+:106B400001291AD1407801280AD10020FEF799FCCA
+:106B50000FF2741000F026F900F010F80120A07078
+:106B60007168487848B9FEF796FC0FF2841000F07F
+:106B700019F900F003F80020A07070BD284600F05D
+:106B800011B90078012808BF00F00DB8704780B532
+:106B90000FF2390200210220FDF7C3FE1B4900223B
+:106BA0000A70BDE8014080B50020FEF774FC17486C
+:106BB00001214170002181700121C170002101710A
+:106BC00001BD00210220FDF7B9BE000010B50F4C39
+:106BD0002079401E8041C00F2071207868B10FF2EB
+:106BE000381000F0DFF808A000F0DCF8E11CBDE888
+:106BF00010404FF6426000F0CBBEBDE810400FF2EF
+:106C0000581000F0CFB80000200A0D0090170020A7
+:106C10002D2D20503250204150504C494341544971
+:106C20004F4E20534552564552203A204E4F54491C
+:106C30004649434154494F4E20454E41424C4544FC
+:106C40000A0000002D2D20503250204150504C4958
+:106C5000434154494F4E20534552564552203A2005
+:106C60004E4F54494649434154494F4E204449539D
+:106C700041424C45440A00002D2D20503250204105
+:106C800050504C49434154494F4E2053455256456C
+:106C90005220203A204C454431204F4E0A0000003B
+:106CA0002D2D20503250204150504C4943415449E1
+:106CB0004F4E2053455256455220203A204C4544D1
+:106CC00031204F46460A00002D2D205032502041E1
+:106CD00050504C49434154494F4E2053455256451C
+:106CE000522031203A204C454431204F4E0A0000BA
+:106CF0002D2D20503250204150504C494341544991
+:106D00004F4E205345525645522031203A204C4593
+:106D10004431204F46460A002D2D2050325020414C
+:106D200050504C49434154494F4E205345525645CB
+:106D30005220203A20494E464F524D20434C49455F
+:106D40004E5420425554544F4E20312050555348F4
+:106D50004544200A200000002D2D205032502041B3
+:106D600050504C49434154494F4E2053455256458B
+:106D700052203A2043414E275420494E464F524D0F
+:106D800020434C49454E54202D20204E4F54494617
+:106D900049434154494F4E2044495341424C454494
+:106DA0000A2000000EB4C0B5024603A800210190DD
+:106DB000009101AB0121044878440C30F9F7BEF989
+:106DC00006BC5DF810FB00BFD314000000B587B00F
+:106DD00000F010F8012003220690ADF80420ADF871
+:106DE000062000F07AF800284CBFFF209DF8000034
+:106DF00007B000BD00208DF800001822002101A876
+:106E000000F0FABD09220021684600F0F5BD182205
+:106E1000002102A800F0F0BD182201A800F0ECBD8E
+:106E200070B5C8B006460C4615460522FFF7EBFFC5
+:106E3000ADF82060FFF7EBFF302100F014F80521DA
+:106E4000049000F019F8002848BFFF2009D49DF8ED
+:106E5000000030B99DF8030020709DF804002870F0
+:106E6000002048B070BDADF80A1008200221ADF82E
+:106E70000800059108A870470791CDF818D00021A7
+:106E800002A8FFF7CCBC00B5C7B000F00EF8FFF7C2
+:106E9000C3FF312000F013F800F01FF800284CBFAA
+:106EA000FF209DF8000047B000BD00238DF81C00B6
+:106EB0008DF8003007A84170827000217047ADF84E
+:106EC000060007A9032004900822012003910690E0
+:106ED000ADF80420704703900691CDF814D000213E
+:106EE00001A8FFF79CBC00B587B000F012F900F0D4
+:106EF0002EF9812000F008F900F036F900284CBF87
+:106F0000FF209DF8000007B000BD2DE9F84DC7B087
+:106F10009446DDF840E1519A559D569EDDF84CA10E
+:106F2000ADF81D108DF81C004FF0000BADF81FC020
+:106F30008DF821308DF822E000F024F800F017F8E9
+:106F400024F8095F668000F002F93F20832100F0F9
+:106F500026F9574406910D37049700F008F90028E8
+:106F60004CBFFF209DF8000048B0BDE8F08D88F8C8
+:106F700000A007AC5499E419524608F101005444AA
+:106F800000F034BD8DF82320174652998DF800B0DB
+:106F90000DF1240809A8B84400F028BD00B5C7B019
+:106FA00000F00CF8852000F090F800F0DDF80028E3
+:106FB0004CBFFF209DF8000047B000BD00218DF8B8
+:106FC0001C008DF80010182201A800F015BD2DE955
+:106FD000F841C7B04FF0000800F026F80DF123008B
+:106FE000DDF844E14E9F4F9E509D529C8DF81F301E
+:106FF000C0F800E08DF800808DF820708DF82160D9
+:107000008DF822508DF8274000F0A1F88620ADF8C9
+:10701000060007A90C2000F0A3F800284CBFFF20B1
+:107020009DF8000000F0D5B88DF81C0007A841704D
+:1070300082707047F8B5C8B005460E4617461C4624
+:1070400000F023F808A8467087708DF8205000F0F3
+:10705000A1F88A21ADF80A103F20032100F08DF835
+:10706000002848BFFF200ED49DF8000058B94F9962
+:107070004E98BDF801202280BDF803200280BDF8A3
+:1070800005000880002049B0F0BD072200216846B5
+:1070900000F0B2BC18B5C7B0044600F03AF88DF85D
+:1070A0001C40224600F083F800F051F83F208E216A
+:1070B00000F092F8641C049400F059F800284CBFCA
+:1070C000FF209DF8000048B010BDADF8060007A9EC
+:1070D00001203F22039104907047ADF8060007A9F4
+:1070E0000220704700B587B000F013F800F02FF8C9
+:1070F000922000F009F800F037F800284CBFFF207C
+:107100009DF8000007B000BDADF806003F22012049
+:10711000704700208DF80000704700B5C7B000210F
+:10712000ADF81C00FFF74DFF9520FFF7D6FF00F0EC
+:1071300017F800284CBFFF209DF8000047B000BDA5
+:1071400000228DF80020ADF81C008DF81E101822CA
+:10715000002101A800F050BCADF8060007A90320EB
+:1071600004903F22012003910690ADF80420CDF851
+:1071700014D0002101A8FFF752BBADF8080005911B
+:1071800008A8072104900791CDF818D0002102A883
+:10719000FFF745BB1822002102A800F02DBCADF876
+:1071A0000400ADF8061007A80121039070470DF107
+:1071B0001D0000F01BBC00B5C7B0FFF7C1FFA52044
+:1071C000FFF7CAFF00284CBFFF209DF8000047B022
+:1071D00000BD48B0BDE8F081ADF80400ADF8061080
+:1071E00007A8012103900691704700B587B00020E1
+:1071F0008DF8000000F0E0F840F20110ADF8060054
+:107200003F220120069000F0ECF800284CBFFF2040
+:107210009DF8000007B000BD2DE9F84107460128A0
+:10722000C7B0884615461E4608BF022003D0022874
+:107230000CBF102000200DF11D010C1800F036F8D5
+:10724000012F8DF81C7002D0022F18D019E00227F0
+:107250003A4641460DF11D0000F0C8FB25706670EE
+:1072600000F0AAF83F204FF4817100F016F8FF1CDF
+:10727000049700F0B8F8002805D5FF2009E0102792
+:10728000E6E7472005E09DF8000010B94E9800F0B1
+:1072900067F8FFE748B0BDE8F081ADF80400ADF84D
+:1072A000061007A8032103900691704703220021CE
+:1072B000684600F0A1BB2DE9F64F0C460546012CAF
+:1072C000C7B09B4608BF022003D0022C0CBF102081
+:1072D00000200DF11F010E18FFF7E8FF012CADF89B
+:1072E0001C508DF81E4002D0022C2CD02DE002271D
+:1072F000569C559DDDF85091DDF84CA1DDF8488194
+:1073000048993A4600F054F8A6F800B086F8028092
+:1073100086F803A086F804907571B47100F04CF8FB
+:107320003F20ADF804004FF4827107A8ADF80610B5
+:10733000039003210A370497069100F054F80028BF
+:1073400005D5FF2009E01027D2E7472005E09DF88A
+:10735000000010B9579800F003F849B0BDE8F08F6D
+:10736000BDF8011001800020704730B5C7B01C4641
+:107370004A9B00F026F800258DF800508DF821403A
+:10738000224619460DF1220000F030FB00F014F8FF
+:107390003F204FF4837100F01BF8A41D049400F00B
+:1073A00022F800284CBFFF209DF8000047B030BDF8
+:1073B0000DF11F0000F01ABB1822002101A800F0F7
+:1073C0001BBBADF81C00ADF81E108DF820207047D7
+:1073D000ADF80400ADF8061007A80121039006914E
+:1073E0007047ADF80420CDF814D0002101A8FFF7B4
+:1073F00016BA30B5C7B00025ADF81C0007A84A9CE6
+:1074000041808280ADF8223004818DF8005000F078
+:1074100016F80F21029140F281100A21ADF8060002
+:10742000049107A801213F220390069100F00CF877
+:1074300000284CBFFF209DF8000047B030BD182247
+:10744000002101A800F0D8BAADF80420CDF814D07E
+:10745000002101A8FFF7E3B910B5029C016042606A
+:107460000021C1600161416181610381A10704774D
+:1074700004D5008910B14FF0FF3010BD002010BDC1
+:107480002DE9F04F064685B030890C460027BB46F3
+:1074900000287169DC460CBF4FF00208D84681B164
+:1074A00068B930697768451CBD4228BFED1B376855
+:1074B000385C7D5D00EB0527BF1CBFB203E00746CB
+:1074C00000E000B102463069F568A84223BF756844
+:1074D000281AC01B0020154608EB050903FB09FE0E
+:1074E000864532BF0020B0FBF9FA09FB1A00C0B292
+:1074F000804509DA96F81C905FEAC97A48BF84464D
+:107500005FEA897048BFC446100000F0B48070681C
+:10751000714461448842C0F0AE8008EB020080B242
+:107520000390D946100AADF802000294ADF800208D
+:10753000049359E0800740D53089002840F09B80B3
+:107540003268D018A34600F8024C200A32681A4468
+:1075500002F8010C224630681844F9F7BDFE706944
+:1075600020187061B069019C401CB061200A31682C
+:107570000C70316848701CE08CB3307FC207D9D5DD
+:10758000308940B931681944FF2001F8020C316894
+:10759000194401F8010C4FF0000B70692418746154
+:1075A0002C463089002340B931680C70210A3068BC
+:1075B000417002237069801C706108EB0407002190
+:1075C000BFB231615CB1DA44029800EB0A01306865
+:1075D00022461844F9F780FE70692418746109F195
+:1075E0000109B069401CB061049A70683169914525
+:1075F00045D2791881422CBF081A084630610346EB
+:107600003089A0B93068BDF80010C1545B1C7068A7
+:107610003168834228BF1B1ABDF80200C8545B1CA6
+:107620007068834228BF1B1A7069801C706105FB5B
+:1076300009FA7468BDF80000E41A844288BF044661
+:10764000029800EB0A01281BAC42019003D093D2B0
+:10765000307F002890D137682246F818F9F73CFEB1
+:10766000706920187061A346019C039F0023A9E75D
+:107670003068404400E0002005B0BDE8F08F884449
+:107680008045F5D3A8EB0008F2E778B5028900231E
+:107690000B80002A44690CBF02250025002C4FD026
+:1076A000028952B9C2684668531CB34228BF9B1B6B
+:1076B0000668B25CF35C02EB03220A80027F02F0F0
+:1076C0000302012A25D10B884FF6FF72934204BFB3
+:1076D0000289002A09D0C36802699A4219D2028934
+:1076E000BAB14668F31A934213D24368C268E41AE7
+:1076F00014190022C260446102894AB902681478F0
+:10770000012B94BFC3F101030123D25C04EB0222DD
+:107710000A80C468426806682B19934228BF9B1AE6
+:1077200033440E884169891B491B416105D03419D6
+:107730002D19954228BFAD1AC5608169491E816126
+:10774000184672BDF8B5028900230B80002A4269F1
+:107750000CBF02240024002A3BD0C56802892B46B6
+:107760004AB946686A1CB24228BF921B0668775D18
+:10777000B25C07EB02220A80067F06F00306012EA8
+:1077800020D10F884FF6FF72974204BF0289002A6A
+:1077900007D142680023012A94BFC2F101020122ED
+:1077A0000AE00269AA420DD202895AB14668751BE5
+:1077B000954207D2002304E005682E78AA5C06EB08
+:1077C00002220A8041680068E4188C4228BF641ACB
+:1077D00003191846F2BD0000024901600249016127
+:1077E000704700BF91550008BB55000870477047AF
+:1077F00070477047704770477047704770477047D1
+:107800007047000038B5054684B068780024FF282A
+:1078100002BFB5F8031040F60140814225D1654909
+:107820008A88B5F80700921C904209D1687B012430
+:10783000C10752BF8DF8004000218DF8001011E003
+:107840004988491C884210D10FF27010FFF7AAFA3C
+:1078500003208DF8000005F10D00B5F80B108DF830
+:10786000081001906846FFF731F9204605B030BD99
+:1078700010B58AB050484F4CFFF768F88F218DF84B
+:107880001810E520B3218DF819008DF81A10D520B5
+:107890002E218DF81B008DF81C107F204A218DF8B9
+:1078A0001D008DF81E1098202A218DF81F008DF8DC
+:1078B000201048207A218DF821008DF82210CC204C
+:1078C00040218DF823008DF82410FE2000218DF832
+:1078D0002500ADF8261000940823012206A90220F5
+:1078E000FFF79AFC00F032F8412000F023F8A01CCA
+:1078F00000F010F8062100F015F800F027F84220FB
+:1079000000F018F8201D00F005F8102100F00AF82A
+:107910000AB010BD059001210491029100200A22B5
+:1079200001907047039200910223208806AA022149
+:10793000FFF7C1BC8E218DF824008DF823100020A4
+:10794000FE21ADF826008DF82510704719208DF81E
+:107950001800ED2182208DF81A008DF81910ED2005
+:10796000AE218DF81C008DF81B104C2021218DF8C4
+:107970001E008DF81D1041209D218DF820008DF8EE
+:107980001F10222045218DF822008DF8211070470C
+:1079900080B542224FF64263984208D105480091D3
+:1079A0000223818800880022FFF7DFFC0246104690
+:1079B00002BD000098170020057800082D2D2047F3
+:1079C000415454203A204C454420434F4E464947A9
+:1079D00055524154494F4E2052454345495645441E
+:1079E0000A000000704770477047704710B50446A2
+:1079F000F9F772FC204610BD10B5044610460A4641
+:107A00000146204600F002F8204610BD62F30F2226
+:107A100062F31F42401810F0030308D0C91A1FD3A5
+:107A2000DB0748BF00F8012D28BF20F8022D130006
+:107A300030B414461546103928BF20E93C00FAD866
+:107A4000490728BF20E90C0048BF40F8042D8900F1
+:107A500028BF20F8022D48BF00F8012D30BC704728
+:107A6000C91818BF00F8012DCB0728BF00F8012D59
+:107A70007047000010B50446AFF30080204600F0C8
+:107A800005F80446AFF30080204610BD7CB500F138
+:107A90000F06F608F600B04240D2082E04D208269F
+:107AA00002E0083000F047F8DFF804512C682100AC
+:107AB00005D1002007E00268B24221D2011D08680A
+:107AC0000028F8D12068291D0A68824222D0136854
+:107AD000B34238BF111DF7D312E093190B60801B1E
+:107AE00054685C600B6818601660096800291DBF47
+:107AF00048680028081D0020286002F1080076BDB3
+:107B000061B10A681068A0F10803B342E5D2506879
+:107B10000860EAE700F04EF80028C2D1002076BDE8
+:107B200010B5040006D0AFF30080204600F003F843
+:107B3000AFF3008010BD002800D1704750B4A0F111
+:107B400008021368072B2BD913F0070F28D1184C04
+:107B5000616809B18A4202D25160626013E04868EC
+:107B600000B3904238BF0146F9D31BE0964203D1DF
+:107B70001B180B600A4606E0486810B1134498428F
+:107B80000ED350604A60506850B11368D1188142DA
+:107B900006D1002121600168CB1813604068506055
+:107BA00050BC704708680E18B242DFD250BC704714
+:107BB000881700200749086808B100207047064868
+:107BC000C008C00008600549C908C900091A016059
+:107BD000704700BFB0170020BF270020B82B00203F
+:107BE0002DE9F04107468846387810F0030F164615
+:107BF0001D4633D0384600F099F878BBB8F1000F35
+:107C00001CBFD8E900018619012D2ED13888C10486
+:107C100015D5396A07F14402384600F0A3F83A6BEB
+:107C2000044602B93A69F968384600F09BF8361BF9
+:107C3000341A7A69F968384600F094F8261A1EB9A1
+:107C40004DB916F1010F09D097F903002A463146C4
+:107C500000F08EF8064616F1010F09D12320AFF38C
+:107C600000804FF0FF30BDE8F081022DE8D1EBE756
+:107C7000388810F4405F0ED07868F8603861786119
+:107C8000B8617868F86107F14400386207F13000A4
+:107C9000786200203863B8F1000F05D0D8E90201FE
+:107CA00007F13402C2E9000139884CF6FF60014057
+:107CB00039800020BDE8F08170B50546AFF3008043
+:107CC0002888810415D56E680024EA6895F90300B8
+:107CD0003146914212D2521AFEF7D2FB10F1010F37
+:107CE0001CBF00283618F0D10FE04DF6FF700140A0
+:107CF00029802846AFF30080002070BD00220021BB
+:107D0000FEF7BEFB10F1010F00D101246868E860A6
+:107D1000A861E861002C2988E7D041F4007129802E
+:107D20002846AFF300804FF0FF3070BDF8B5A0B922
+:107D3000AFF3008000250A4E08244FF0FF3730686B
+:107D400020B1FFF7B9FF002848BF3D46361D641E2D
+:107D5000F5D1AFF300802846F2BDBDE8F240ABE7B5
+:107D6000F8110020914234BF511A00210846704793
+:107D70003EB504000D00012A02D100F063F807E0CF
+:107D8000022A07D100940020019069460C20ABBE66
+:107D90002D1801E0002A0CD10094019569460A20B3
+:107DA000ABBE002805D100222100280000F027F8F2
+:107DB00001E00020C04303B030BD000010B4314AE0
+:107DC000002113461C6884421EBF491C9C688442E3
+:107DD0001EBF491C1C69844209D09C69491C84420D
+:107DE00005D0491C20331029ECD310BC7047002368
+:107DF00042F8313002EBC1014B6010BC704778B4DF
+:107E0000204C002325462E688E421EBF5B1CAE68A8
+:107E10008E421EBF5B1C2E698E4209D0AE695B1C70
+:107E20008E4205D05B1C2035102BECD372BC704702
+:107E3000054604EBC303012A04BF59684D195D6070
+:107E400072BC704710B40F4A002113461C6884426C
+:107E50001EBF491C9C6884421EBF491C1C69844289
+:107E60000AD09C69491C844206D0491C2033102941
+:107E7000ECD310BC0020704702EBC100406810BC7E
+:107E800070470000D414002010B50446E068A169D2
+:107E9000884251D3218849F202030B40022B08D0BB
+:107EA00008044CBF4FF400704FF48440014321801C
+:107EB0003BE001F4C042B2F5C04F06D1A168884250
+:107EC00003D32046FFF732FF78BB208810F4406FC1
+:107ED00002BF606804F14401884217D14FF400707A
+:107EE000FFF7C8FD606030B904F144006060E060F5
+:107EF000401CA0600AE0218841F040012180E06040
+:107F0000606100F500726068A260E06160682061F5
+:107F1000A068A061207841070AD5022200212046EE
+:107F200000F00CF810F1010F02D14FF0FF3010BD3E
+:107F3000208840F4C0402080002010BD70B5044669
+:107F40000D461646AFF3008033462A4600212046F0
+:107F5000FFF746FE05462046AFF30080284670BD79
+:107F600038B504000ED0207810F0030F03D094F938
+:107F70000300002809D5AFF30080204600F030F858
+:107F8000AFF300804FF0FF3032BD2046FFF7CEFE4A
+:107F90000546AFF300802078410644BF606800F0DA
+:107FA0005DF80020606094F90300022804D900F015
+:107FB00057F808B14FF0FF35E06B48B100F05CF8BE
+:107FC00008B14FF0FF35E06B00F048F80020E063A7
+:107FD000204600F005F8AFF30080284632BD0000CF
+:107FE00001780A0626D51C4A13680021834203D172
+:107FF000002342F821301BE05368012183421EBF59
+:10800000022193688342F3D0D368032183421EBFC9
+:10801000042113698342EBD05369052183421EBFBB
+:108020000621936983421EBF0721D3698342DFD0B3
+:1080300000F014B8002101804FF0FF31C17000F151
+:1080400044014160C160016141618161C1610162BE
+:1080500000F1300141627047F8110020FFF760BD68
+:108060001CB50200009269460220ABBE040010005D
+:10807000FFF7A4FE200016BDE0B50090F9F7DEF88A
+:10808000019069460E20ABBE03B000BD7047FEE70D
+:10809000FEE7FEE7FEE770477047704700F020B844
+:1080A0000548FBF733B80548F9F793BF0448F9F7DB
+:1080B00090BF0448FBF72AB854150020C8130020CD
+:1080C0003C130020B41500200120FCF728B9102033
+:1080D000FCF725B9FCF7D3BEFEF752BAFEF726BA75
+:1080E00002490A68886882180A6070479010002068
+:1080F00038B50C46C5B22046AFF30080E068A169F0
+:10810000884204D32046FFF7BFFE00280FD4E06862
+:10811000401CE06000F8015D2088010503D44005A3
+:108120000BD50A2D09D12046FFF700FE28B12046C5
+:10813000AFF300804FF0FF3032BD2046AFF3008038
+:10814000284632BD19E050F8042BD30744BFA9F1EB
+:1081500001039A18091F0023042942F8043BF9D2AD
+:108160005FEA817C134604D54FF0000CA2F800C0F2
+:108170009B1CC90744BF0021197050F8041B00293B
+:10818000E1D1704738B50D4D0824286800281CBF80
+:10819000017811F0030F05D090F90310002958BFA2
+:1081A000FFF7DEFE2D1D641EEFD1BDE83840002232
+:1081B00000214FF0FF30FEF763B900BFF811002037
+:1081C00010B5074979441831064C7C44163404E054
+:1081D0000A68081D114488470146A142F8D110BD24
+:1081E0002C000000600000004EF68851CEF2000125
+:1081F000086840F470000860BFF34F8FBFF36F8FC3
+:108200004FF00070E1EE100A7047000039FFFFFFE9
+:10821000A005000018120020800800002C8000201B
+:1082200000000000AF8EFFFF88010000BA010000CF
+:10823000040000209F8EFFFF550200000600000092
+:10824000248000200000000000000000000000006A
+:108250000000000001000000020000000300000018
+:108260000400000000F00DF8002801D0FFF7A8FF7F
+:10827000AFF300800020AFF30080FBF766FD00F055
+:1082800002F80120704700F001B800000746FFF730
+:1082900079FF3846F9F704FEFBE738B504460D468A
+:1082A000284600F005F8A84218BF0024204632BD39
+:1082B0000149FFF71DBF00BF68110020014880473A
+:1082C00001480047A5430008CD820008AFF30080B5
+:1082D000FFF78AFFFFF7C6FF00002E004300FFF7FD
+:1082E000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF7C2
+:1082F000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF7B2
+:10830000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF7A1
+:10831000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF791
+:10832000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF781
+:10833000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF771
+:10834000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF761
+:10835000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF751
+:10836000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF741
+:10837000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF731
+:10838000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF721
+:10839000FEBFFFF7FEBFFFF7FEBFFFF7FEBFFFF711
+:1083A000FEBFFFF7FEBFFFF7FEBFFFF7FEBF0000F7
+:1083B000F0030C0DFF01830001F006FF48420000AE
+:1083C0007A44010001F1FF01F1FF01F1FF01F1FF2A
+:1083D00001F1FF01F1FF01F1FF01F1FF01F1FF01E7
+:1083E000F1FF01F1FF01F1FF01F1FF01F1FF01F1E7
+:1083F00022017001040048041D391053001008F1D7
+:10840000020152FF01E11C1210113D6C10F0050732
+:10841000093D00D8820008046140F200DA1410011E
+:108420000000DC0C2144FC0217A0100020B7102033
+:1084300002ED1100082C43DB113C2101100701045F
+:108440000000641100206504526404211BA108F39C
+:108450001150116410070204010164160020B404D5
+:108460005264043140510812AC44F213984850024F
+:1084700008020214405214042134610812F444F238
+:1084800012E048122024126804F206B02C520001B7
+:04000005080082CDA0
+:00000001FF
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/app_common.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/app_common.h
new file mode 100644
index 000000000..4defc5d7a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/app_common.h
@@ -0,0 +1,114 @@
+/**
+ ******************************************************************************
+  * File Name          : app_common.h
+  * Description        : App Common application configuration file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_COMMON_H
+#define APP_COMMON_H
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "app_conf.h"
+
+  /* -------------------------------- *
+   *  Basic definitions               *
+   * -------------------------------- */
+
+#undef NULL
+#define NULL                    0
+
+#undef FALSE
+#define FALSE                   0
+
+#undef TRUE
+#define TRUE                    (!0)
+
+  /* -------------------------------- *
+   *  Critical Section definition     *
+   * -------------------------------- */
+#define BACKUP_PRIMASK()    uint32_t primask_bit= __get_PRIMASK()
+#define DISABLE_IRQ()       __disable_irq()
+#define RESTORE_PRIMASK()   __set_PRIMASK(primask_bit)
+
+  /* -------------------------------- *
+   *  Macro delimiters                *
+   * -------------------------------- */
+
+#define M_BEGIN     do {
+
+#define M_END       } while(0)
+
+  /* -------------------------------- *
+   *  Some useful macro definitions   *
+   * -------------------------------- */
+
+#define MAX( x, y )          (((x)>(y))?(x):(y))
+
+#define MIN( x, y )          (((x)<(y))?(x):(y))
+
+#define MODINC( a, m )       M_BEGIN  (a)++;  if ((a)>=(m)) (a)=0;  M_END
+
+#define MODDEC( a, m )       M_BEGIN  if ((a)==0) (a)=(m);  (a)--;  M_END
+
+#define MODADD( a, b, m )    M_BEGIN  (a)+=(b);  if ((a)>=(m)) (a)-=(m);  M_END
+
+#define MODSUB( a, b, m )    MODADD( a, (m)-(b), m )
+
+#define PAUSE( t )           M_BEGIN \
+                               __IO int _i; \
+                               for ( _i = t; _i > 0; _i -- ); \
+                             M_END
+
+#define DIVF( x, y )         ((x)/(y))
+
+#define DIVC( x, y )         (((x)+(y)-1)/(y))
+
+#define DIVR( x, y )         (((x)+((y)/2))/(y))
+
+#define SHRR( x, n )         ((((x)>>((n)-1))+1)>>1)
+
+#define BITN( w, n )         (((w)[(n)/32] >> ((n)%32)) & 1)
+
+#define BITNSET( w, n, b )   M_BEGIN (w)[(n)/32] |= ((U32)(b))<<((n)%32); M_END
+
+  /* -------------------------------- *
+   *  Compiler                         *
+   * -------------------------------- */
+#define PLACE_IN_SECTION( __x__ )  __attribute__((section (__x__)))
+
+#ifdef WIN32
+#define ALIGN(n)
+#else
+#define ALIGN(n)             __attribute__((aligned(n)))
+#endif
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*APP_COMMON_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/app_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/app_conf.h
new file mode 100644
index 000000000..bfaf79704
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/app_conf.h
@@ -0,0 +1,562 @@
+/**
+ ******************************************************************************
+  * File Name          : app_conf.h
+  * Description        : Application configuration file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_CONF_H
+#define APP_CONF_H
+
+#include "hw.h"
+#include "hw_conf.h"
+#include "hw_if.h"
+
+/******************************************************************************
+ * Application Config
+ ******************************************************************************/
+
+/**< generic parameters ******************************************************/
+
+/**
+ * Define Tx Power
+ */   
+#define CFG_TX_POWER                      (0x18) /**< 0dbm */
+
+/**
+ * Define Advertising parameters
+ */
+#define CFG_ADV_BD_ADDRESS                (0x7257acd87a6c)
+#define CFG_FAST_CONN_ADV_INTERVAL_MIN    (0x80)   /**< 80ms */
+#define CFG_FAST_CONN_ADV_INTERVAL_MAX    (0xa0)  /**< 100ms */
+#define CFG_LP_CONN_ADV_INTERVAL_MIN      (0x640) /**< 1s */
+#define CFG_LP_CONN_ADV_INTERVAL_MAX      (0xfa0) /**< 2.5s */
+
+/**
+ * Define IO Authentication
+ */
+#define CFG_BONDING_MODE                  (1)
+#define CFG_FIXED_PIN                     (111111)
+#define CFG_USED_FIXED_PIN                (0)
+#define CFG_ENCRYPTION_KEY_SIZE_MAX       (16)
+#define CFG_ENCRYPTION_KEY_SIZE_MIN       (8)
+
+/**
+ * Define IO capabilities
+ */
+#define CFG_IO_CAPABILITY_DISPLAY_ONLY       (0x00)
+#define CFG_IO_CAPABILITY_DISPLAY_YES_NO     (0x01)
+#define CFG_IO_CAPABILITY_KEYBOARD_ONLY      (0x02)
+#define CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT (0x03)
+#define CFG_IO_CAPABILITY_KEYBOARD_DISPLAY   (0x04)
+
+#define CFG_IO_CAPABILITY              CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT
+
+/**
+ * Define MITM modes
+ */
+#define CFG_MITM_PROTECTION_NOT_REQUIRED      (0x00)
+#define CFG_MITM_PROTECTION_REQUIRED          (0x01)
+
+#define CFG_MITM_PROTECTION             CFG_MITM_PROTECTION_REQUIRED
+
+/**
+ * Define PHY
+ */
+#define ALL_PHYS_PREFERENCE                             0x00
+#define RX_2M_PREFERRED                                 0x02
+#define TX_2M_PREFERRED                                 0x02
+#define TX_1M                                           0x01
+#define TX_2M                                           0x02
+#define RX_1M                                           0x01
+#define RX_2M                                           0x02 
+
+/**
+*   Identity root key used to derive LTK and CSRK
+*/
+#define CFG_BLE_IRK     {0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0,0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0}
+
+/**
+* Encryption root key used to derive LTK and CSRK
+*/
+#define CFG_BLE_ERK     {0xfe,0xdc,0xba,0x09,0x87,0x65,0x43,0x21,0xfe,0xdc,0xba,0x09,0x87,0x65,0x43,0x21}
+
+/* USER CODE BEGIN Generic_Parameters */
+/**
+ * SMPS supply
+ * SMPS not used when Set to 0
+ * SMPS used when Set to 1
+ */
+#define CFG_USE_SMPS    1
+/* USER CODE END Generic_Parameters */
+
+/**< specific parameters */
+/*****************************************************/
+#ifdef LITTLE_DORY
+#define PUSH_BUTTON_SW1_EXTI_IRQHandler                         EXTI0_IRQHandler
+#define PUSH_BUTTON_SW2_EXTI_IRQHandler                         EXTI4_IRQHandler
+#else
+#define PUSH_BUTTON_SW1_EXTI_IRQHandler                         EXTI4_IRQHandler
+#define PUSH_BUTTON_SW2_EXTI_IRQHandler                         EXTI0_IRQHandler
+#endif
+
+#define P2P_SERVER1    1    /*1 = Device is Peripherique*/
+#define P2P_SERVER2    0
+#define P2P_SERVER3    0
+#define P2P_SERVER4    0
+#define P2P_SERVER5    0
+#define P2P_SERVER6    0
+
+#define CFG_DEV_ID_P2P_SERVER1                  (0x83)
+#define CFG_DEV_ID_P2P_SERVER2                  (0x84)
+#define CFG_DEV_ID_P2P_SERVER3                  (0x87)
+#define CFG_DEV_ID_P2P_SERVER4                  (0x88)
+#define CFG_DEV_ID_P2P_SERVER5                  (0x89)   
+#define CFG_DEV_ID_P2P_SERVER6                  (0x8A)   
+#define CFG_DEV_ID_P2P_ROUTER                   (0x85)
+
+#define  RADIO_ACTIVITY_EVENT   1          /* 1 for OOB Demo */
+
+/**
+* AD Element - Group B Feature
+*/ 
+/* LSB - First Byte */
+#define CFG_FEATURE_THREAD_SWITCH               (0x40)
+
+/* LSB - Second Byte */
+#define CFG_FEATURE_OTA_REBOOT                  (0x20)
+
+#define CONN_L(x) ((int)((x)/0.625f))
+#define CONN_P(x) ((int)((x)/1.25f))
+
+  /*  L2CAP Connection Update request parameters used for test only with smart Phone */
+#define L2CAP_REQUEST_NEW_CONN_PARAM             1
+
+#define L2CAP_INTERVAL_MIN              CONN_P(1000) /* 1s */
+#define L2CAP_INTERVAL_MAX              CONN_P(1000) /* 1s */
+#define L2CAP_SLAVE_LATENCY             0x0000
+#define L2CAP_TIMEOUT_MULTIPLIER        0x1F4
+
+/******************************************************************************
+ * BLE Stack
+ ******************************************************************************/
+/**
+ * Maximum number of simultaneous connections that the device will support.
+ * Valid values are from 1 to 8
+ */
+#define CFG_BLE_NUM_LINK            8
+
+/**
+ * Maximum number of Services that can be stored in the GATT database.
+ * Note that the GAP and GATT services are automatically added so this parameter should be 2 plus the number of user services
+ */
+#define CFG_BLE_NUM_GATT_SERVICES   8
+
+/**
+ * Maximum number of Attributes
+ * (i.e. the number of characteristic + the number of characteristic values + the number of descriptors, excluding the services)
+ * that can be stored in the GATT database.
+ * Note that certain characteristics and relative descriptors are added automatically during device initialization
+ * so this parameters should be 9 plus the number of user Attributes
+ */
+#define CFG_BLE_NUM_GATT_ATTRIBUTES 68
+
+/**
+ * Maximum supported ATT_MTU size
+ */
+#define CFG_BLE_MAX_ATT_MTU             (156)
+
+/**
+ * Size of the storage area for Attribute values
+ *  This value depends on the number of attributes used by application. In particular the sum of the following quantities (in octets) should be made for each attribute:
+ *  - attribute value length
+ *  - 5, if UUID is 16 bit; 19, if UUID is 128 bit
+ *  - 2, if server configuration descriptor is used
+ *  - 2*DTM_NUM_LINK, if client configuration descriptor is used
+ *  - 2, if extended properties is used
+ *  The total amount of memory needed is the sum of the above quantities for each attribute.
+ */
+#define CFG_BLE_ATT_VALUE_ARRAY_SIZE    (1344)
+
+/**
+ * Prepare Write List size in terms of number of packet with ATT_MTU=23 bytes
+ */
+#define CFG_BLE_PREPARE_WRITE_LIST_SIZE         ( 0x3A )
+
+/**
+ * Number of allocated memory blocks
+ */
+#define CFG_BLE_MBLOCK_COUNT            ( 0x79 )
+
+/**
+ * Enable or disable the Extended Packet length feature. Valid values are 0 or 1.
+ */
+#define CFG_BLE_DATA_LENGTH_EXTENSION   1
+
+/**
+ * Sleep clock accuracy in Slave mode (ppm value)
+ */
+#define CFG_BLE_SLAVE_SCA   500
+
+/**
+ * Sleep clock accuracy in Master mode
+ * 0 : 251 ppm to 500 ppm
+ * 1 : 151 ppm to 250 ppm
+ * 2 : 101 ppm to 150 ppm
+ * 3 : 76 ppm to 100 ppm
+ * 4 : 51 ppm to 75 ppm
+ * 5 : 31 ppm to 50 ppm
+ * 6 : 21 ppm to 30 ppm
+ * 7 : 0 ppm to 20 ppm
+ */
+#define CFG_BLE_MASTER_SCA   0
+
+/**
+ *  Source for the 32 kHz slow speed clock
+ *  1 : internal RO
+ *  0 : external crystal ( no calibration )
+ */
+#define CFG_BLE_LSE_SOURCE  0
+
+/**
+ * Start up time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us)
+ */
+#define CFG_BLE_HSE_STARTUP_TIME  0x148
+
+/**
+ * Maximum duration of the connection event when the device is in Slave mode in units of 625/256 us (~2.44 us)
+ */
+#define CFG_BLE_MAX_CONN_EVENT_LENGTH  ( 0xFFFFFFFF )
+
+/**
+ * Viterbi Mode
+ * 1 : enabled
+ * 0 : disabled
+ */
+#define CFG_BLE_VITERBI_MODE  1
+
+/**
+ *  LL Only Mode
+ *  1 : LL Only
+ *  0 : LL + Host
+ */
+#define CFG_BLE_LL_ONLY  0
+/******************************************************************************
+ * Transport Layer
+ ******************************************************************************/
+/**
+ * Queue length of BLE Event
+ * This parameter defines the number of asynchronous events that can be stored in the HCI layer before
+ * being reported to the application. When a command is sent to the BLE core coprocessor, the HCI layer
+ * is waiting for the event with the Num_HCI_Command_Packets set to 1. The receive queue shall be large
+ * enough to store all asynchronous events received in between.
+ * When CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE is set to 27, this allow to store three 255 bytes long asynchronous events
+ * between the HCI command and its event.
+ * This parameter depends on the value given to CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE. When the queue size is to small,
+ * the system may hang if the queue is full with asynchronous events and the HCI layer is still waiting
+ * for a CC/CS event, In that case, the notification TL_BLE_HCI_ToNot() is called to indicate
+ * to the application a HCI command did not receive its command event within 30s (Default HCI Timeout).
+ */
+#define CFG_TLBLE_EVT_QUEUE_LENGTH 5
+/**
+ * This parameter should be set to fit most events received by the HCI layer. It defines the buffer size of each element
+ * allocated in the queue of received events and can be used to optimize the amount of RAM allocated by the Memory Manager.
+ * It should not exceed 255 which is the maximum HCI packet payload size (a greater value is a lost of memory as it will
+ * never be used)
+ * It shall be at least 4 to receive the command status event in one frame.
+ * The default value is set to 27 to allow receiving an event of MTU size in a single buffer. This value maybe reduced
+ * further depending on the application.
+ *
+ */
+#define CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE 255   /**< Set to 255 with the memory manager and the mailbox */
+
+#define TL_BLE_EVENT_FRAME_SIZE ( TL_EVT_HDR_SIZE + CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE )
+/******************************************************************************
+ * UART interfaces
+ ******************************************************************************/
+
+/**
+ * Select UART interfaces
+ */
+#define CFG_DEBUG_TRACE_UART    hw_uart1
+#define CFG_CONSOLE_MENU      hw_lpuart1
+/******************************************************************************
+ * USB interface
+ ******************************************************************************/
+
+/**
+ * Enable/Disable USB interface
+ */
+#define CFG_USB_INTERFACE_ENABLE    0
+
+/******************************************************************************
+ * Low Power
+ ******************************************************************************/
+/**
+ *  When set to 1, the low power mode is enable
+ *  When set to 0, the device stays in RUN mode
+ */
+#define CFG_LPM_SUPPORTED    1
+
+/******************************************************************************
+ * Timer Server
+ ******************************************************************************/
+/**
+ *  CFG_RTC_WUCKSEL_DIVIDER:  This sets the RTCCLK divider to the wakeup timer.
+ *  The higher is the value, the better is the power consumption and the accuracy of the timerserver
+ *  The lower is the value, the finest is the granularity
+ *
+ *  CFG_RTC_ASYNCH_PRESCALER: This sets the asynchronous prescaler of the RTC. It should as high as possible ( to ouput
+ *  clock as low as possible) but the output clock should be equal or higher frequency compare to the clock feeding
+ *  the wakeup timer. A lower clock speed would impact the accuracy of the timer server.
+ *
+ *  CFG_RTC_SYNCH_PRESCALER: This sets the synchronous prescaler of the RTC.
+ *  When the 1Hz calendar clock is required, it shall be sets according to other settings
+ *  When the 1Hz calendar clock is not needed, CFG_RTC_SYNCH_PRESCALER should be set to 0x7FFF (MAX VALUE)
+ *
+ *  CFG_RTCCLK_DIVIDER_CONF:
+ *  Shall be set to either 0,2,4,8,16
+ *  When set to either 2,4,8,16, the 1Hhz calendar is supported
+ *  When set to 0, the user sets its own configuration
+ *
+ *  The following settings are computed with LSI as input to the RTC
+ */
+#define CFG_RTCCLK_DIVIDER_CONF 0
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 0)
+/**
+ * Custom configuration
+ * It does not support 1Hz calendar
+ * It divides the RTC CLK by 16
+ */
+#define CFG_RTCCLK_DIV  (16)
+#define CFG_RTC_WUCKSEL_DIVIDER (0)
+#define CFG_RTC_ASYNCH_PRESCALER (CFG_RTCCLK_DIV - 1)
+#define CFG_RTC_SYNCH_PRESCALER (0x7FFF)
+
+#else
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 2)
+/**
+ * It divides the RTC CLK by 2
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (3)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 4)
+/**
+ * It divides the RTC CLK by 4
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (2)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 8)
+/**
+ * It divides the RTC CLK by 8
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (1)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 16)
+/**
+ * It divides the RTC CLK by 16
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (0)
+#endif
+
+#define CFG_RTCCLK_DIV              CFG_RTCCLK_DIVIDER_CONF
+#define CFG_RTC_ASYNCH_PRESCALER    (CFG_RTCCLK_DIV - 1)
+#define CFG_RTC_SYNCH_PRESCALER     (DIVR( LSE_VALUE, (CFG_RTC_ASYNCH_PRESCALER+1) ) - 1 )
+
+#endif
+
+/** tick timer value in us */
+#define CFG_TS_TICK_VAL           DIVR( (CFG_RTCCLK_DIV * 1000000), LSE_VALUE )
+
+typedef enum
+{
+  CFG_TIM_PROC_ID_ISR,
+} CFG_TimProcID_t;
+
+/******************************************************************************
+ * Debug
+ ******************************************************************************/
+/**
+ * When set, this resets some hw resources to set the device in the same state than the power up
+ * The FW resets only register that may prevent the FW to run properly
+ *
+ * This shall be set to 0 in a final product
+ *
+ */
+#define CFG_HW_RESET_BY_FW         1
+
+/**
+ * keep debugger enabled while in any low power mode when set to 1
+ * should be set to 0 in production
+ */
+#define CFG_DEBUGGER_SUPPORTED    1
+
+/**
+ * When set to 1, the traces are enabled in the BLE services
+ */
+#define CFG_DEBUG_BLE_TRACE     1
+
+/**
+ * Enable or Disable traces in application
+ */
+#define CFG_DEBUG_APP_TRACE     1
+
+#if (CFG_DEBUG_APP_TRACE != 0)
+#define APP_DBG_MSG                 PRINT_MESG_DBG
+#else
+#define APP_DBG_MSG                 PRINT_NO_MESG
+#endif
+
+#if ( (CFG_DEBUG_BLE_TRACE != 0) || (CFG_DEBUG_APP_TRACE != 0) )
+#define CFG_DEBUG_TRACE             1
+#endif
+
+#if (CFG_DEBUG_TRACE != 0)
+#undef CFG_LPM_SUPPORTED
+#undef CFG_DEBUGGER_SUPPORTED
+#define CFG_LPM_SUPPORTED         0
+#define CFG_DEBUGGER_SUPPORTED      1
+#endif
+
+/**
+ * When CFG_DEBUG_TRACE_FULL is set to 1, the trace are output with the API name, the file name and the line number
+ * When CFG_DEBUG_TRACE_LIGHT is set to 1, only the debug message is output
+ *
+ * When both are set to 0, no trace are output
+ * When both are set to 1,  CFG_DEBUG_TRACE_FULL is selected
+ */
+#define CFG_DEBUG_TRACE_LIGHT     1
+#define CFG_DEBUG_TRACE_FULL      0
+
+#if (( CFG_DEBUG_TRACE != 0 ) && ( CFG_DEBUG_TRACE_LIGHT == 0 ) && (CFG_DEBUG_TRACE_FULL == 0))
+#undef CFG_DEBUG_TRACE_FULL
+#undef CFG_DEBUG_TRACE_LIGHT
+#define CFG_DEBUG_TRACE_FULL      0
+#define CFG_DEBUG_TRACE_LIGHT     1
+#endif
+
+#if ( CFG_DEBUG_TRACE == 0 )
+#undef CFG_DEBUG_TRACE_FULL
+#undef CFG_DEBUG_TRACE_LIGHT
+#define CFG_DEBUG_TRACE_FULL      0
+#define CFG_DEBUG_TRACE_LIGHT     0
+#endif
+
+/**
+ * When not set, the traces is looping on sending the trace over UART
+ */
+#define DBG_TRACE_USE_CIRCULAR_QUEUE 1
+
+/**
+ * max buffer Size to queue data traces and max data trace allowed.
+ * Only Used if DBG_TRACE_USE_CIRCULAR_QUEUE is defined
+ */
+#define DBG_TRACE_MSG_QUEUE_SIZE 4096
+#define MAX_DBG_TRACE_MSG_SIZE 1024
+
+/* USER CODE BEGIN Defines */
+#define CFG_LED_SUPPORTED         1
+#define CFG_BUTTON_SUPPORTED      1
+/* USER CODE END Defines */
+
+/******************************************************************************
+ * Scheduler
+ ******************************************************************************/
+
+/**
+ * These are the lists of task id registered to the scheduler
+ * Each task id shall be in the range [0:31]
+ * This mechanism allows to implement a generic code in the API TL_BLE_HCI_StatusNot() to comply with
+ * the requirement that a HCI/ACI command shall never be sent if there is already one pending
+ */
+
+/**< Add in that list all tasks that may send a ACI/HCI command */
+typedef enum
+{
+    CFG_TASK_ADV_CANCEL_ID,
+    CFG_TASK_SW1_BUTTON_PUSHED_ID,
+#if (L2CAP_REQUEST_NEW_CONN_PARAM != 0 )    
+    CFG_TASK_CONN_UPDATE_REG_ID,
+#endif
+    CFG_TASK_HCI_ASYNCH_EVT_ID,
+/* USER CODE BEGIN CFG_Task_Id_With_HCI_Cmd_t */
+
+/* USER CODE END CFG_Task_Id_With_HCI_Cmd_t */
+    CFG_LAST_TASK_ID_WITH_HCICMD,                                               /**< Shall be LAST in the list */
+} CFG_Task_Id_With_HCI_Cmd_t;
+
+/**< Add in that list all tasks that never send a ACI/HCI command */
+typedef enum
+{
+    CFG_FIRST_TASK_ID_WITH_NO_HCICMD = CFG_LAST_TASK_ID_WITH_HCICMD - 1,        /**< Shall be FIRST in the list */
+    CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID,
+/* USER CODE BEGIN CFG_Task_Id_With_NO_HCI_Cmd_t */
+
+/* USER CODE END CFG_Task_Id_With_NO_HCI_Cmd_t */
+    CFG_LAST_TASK_ID_WITHO_NO_HCICMD                                            /**< Shall be LAST in the list */
+} CFG_Task_Id_With_NO_HCI_Cmd_t;
+#define CFG_TASK_NBR    CFG_LAST_TASK_ID_WITHO_NO_HCICMD
+
+/**
+ * This is the list of priority required by the application
+ * Each Id shall be in the range 0..31
+ */
+typedef enum
+{
+    CFG_SCH_PRIO_0,
+    CFG_PRIO_NBR,
+} CFG_SCH_Prio_Id_t;
+
+/**
+ * This is a bit mapping over 32bits listing all events id supported in the application
+ */
+typedef enum
+{
+    CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID,
+    CFG_IDLEEVT_SYSTEM_HCI_CMD_EVT_RSP_ID,
+} CFG_IdleEvt_Id_t;
+
+/******************************************************************************
+ * LOW POWER
+ ******************************************************************************/
+/**
+ * Supported requester to the MCU Low Power Manager - can be increased up  to 32
+ * It lits a bit mapping of all user of the Low Power Manager
+ */
+typedef enum
+{
+    CFG_LPM_APP,
+    CFG_LPM_APP_BLE,
+  /* USER CODE BEGIN CFG_LPM_Id_t */
+
+  /* USER CODE END CFG_LPM_Id_t */
+} CFG_LPM_Id_t;
+
+/******************************************************************************
+ * OTP manager
+ ******************************************************************************/
+#define CFG_OTP_BASE_ADDRESS    OTP_AREA_BASE
+
+#define CFG_OTP_END_ADRESS      OTP_AREA_END_ADDR
+
+#endif /*APP_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/app_debug.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/app_debug.h
new file mode 100644
index 000000000..13485c16b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/app_debug.h
@@ -0,0 +1,45 @@
+
+/**
+  ******************************************************************************
+  * @file    app_debug.h
+  * @author  MCD Application Team
+  * @brief   Interface to support debug in the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+  /* Exported types ------------------------------------------------------------*/
+  /* Exported constants --------------------------------------------------------*/
+  /* External variables --------------------------------------------------------*/
+  /* Exported macros -----------------------------------------------------------*/
+  /* Exported functions ------------------------------------------------------- */
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/app_entry.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/app_entry.h
new file mode 100644
index 000000000..77ead2384
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/app_entry.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    app_entry.h
+  * @author  MCD Application Team
+  * @brief   Interface to the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_ENTRY_H
+#define APP_ENTRY_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APPE_Init( void );
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*APP_ENTRY_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/hw_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/hw_conf.h
new file mode 100644
index 000000000..523eb30f6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/hw_conf.h
@@ -0,0 +1,248 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : hw_conf.h
+  * Description        : Hardware configuration file for BLE 
+  *                      middleWare.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef HW_CONF_H
+#define HW_CONF_H
+
+/******************************************************************************
+* Semaphores
+* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
+*****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
+/* Index of the semaphore used to manage the entry Stop Mode procedure */
+#define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
+
+/* Index of the semaphore used to access the RCC */
+#define CFG_HW_RCC_SEMID                                        3
+
+/* Index of the semaphore used to access the FLASH */
+#define CFG_HW_FLASH_SEMID                                      2
+
+/* Index of the semaphore used to access the PKA */
+#define CFG_HW_PKA_SEMID                                        1
+
+/* Index of the semaphore used to access the RNG */
+#define CFG_HW_RNG_SEMID                                        0
+
+/******************************************************************************
+ * HW TIMER SERVER
+ *****************************************************************************/
+/**
+ * The user may define the maximum number of virtual timers supported.
+ * It shall not exceed 255
+ */
+#define CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER  6
+
+/**
+ * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
+ * wakeup timer.
+ * This setting is the preemptpriority part of the NVIC.
+ */
+#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO  3
+
+/**
+ * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
+ * wakeup timer.
+ * This setting is the subpriority part of the NVIC. It does not exist on all processors. When it is not supported
+ * on the CPU, the setting is ignored
+ */
+#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO  0
+
+/**
+ *  Define a critical section in the Timer server
+ *  The Timer server does not support the API to be nested
+ *  The  Application shall either:
+ *    a) Ensure this will never happen
+ *    b) Define the critical section
+ *  The default implementations is masking all interrupts using the PRIMASK bit
+ *  The TimerServer driver uses critical sections to avoid context corruption. This is achieved with the macro
+ *  TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION. When CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION is set
+ *  to 1, all STM32 interrupts are masked with the PRIMASK bit of the CortexM CPU. It is possible to use the BASEPRI
+ *  register of the CortexM CPU to keep allowed some interrupts with high priority. In that case, the user shall
+ *  re-implement TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION and shall make sure that no TimerServer
+ *  API are called when the TIMER critical section is entered
+ */
+#define CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION  1
+
+/**
+   * This value shall reflect the maximum delay there could be in the application between the time the RTC interrupt
+   * is generated by the Hardware and the time when the  RTC interrupt handler is called. This time is measured in
+   * number of RTCCLK ticks.
+   * A relaxed timing would be 10ms
+   * When the value is too short, the timerserver will not be able to count properly and all timeout may be random.
+   * When the value is too long, the device may wake up more often than the most optimal configuration. However, the
+   * impact on power consumption would be marginal (unless the value selected is extremely too long). It is strongly
+   * recommended to select a value large enough to make sure it is not too short to ensure reliability of the system
+   * as this will have marginal impact on low power mode
+   */
+#define CFG_HW_TS_RTC_HANDLER_MAX_DELAY  ( 10 * (LSI_VALUE/1000) )
+
+  /**
+   * Interrupt ID in the NVIC of the RTC Wakeup interrupt handler
+   * It shall be type of IRQn_Type
+   */
+#define CFG_HW_TS_RTC_WAKEUP_HANDLER_ID  RTC_WKUP_IRQn
+
+/******************************************************************************
+ * HW UART
+ *****************************************************************************/
+
+#define CFG_HW_LPUART1_ENABLED           1
+#define CFG_HW_LPUART1_DMA_TX_SUPPORTED  1
+
+#define CFG_HW_USART1_ENABLED           1
+#define CFG_HW_USART1_DMA_TX_SUPPORTED  1
+
+/**
+ * LPUART1
+ */
+#define CFG_HW_LPUART1_PREEMPTPRIORITY         0x0F
+#define CFG_HW_LPUART1_SUBPRIORITY             0
+
+/** < The application shall check the selected source clock is enable */
+#define CFG_HW_LPUART1_SOURCE_CLOCK             RCC_LPUART1CLKSOURCE_SYSCLK
+
+#define CFG_HW_LPUART1_BAUDRATE                115200
+#define CFG_HW_LPUART1_WORDLENGTH              UART_WORDLENGTH_8B
+#define CFG_HW_LPUART1_STOPBITS                UART_STOPBITS_1
+#define CFG_HW_LPUART1_PARITY                  UART_PARITY_NONE
+#define CFG_HW_LPUART1_HWFLOWCTL               UART_HWCONTROL_NONE
+#define CFG_HW_LPUART1_MODE                    UART_MODE_TX_RX
+#define CFG_HW_LPUART1_ADVFEATUREINIT          UART_ADVFEATURE_NO_INIT
+#define CFG_HW_LPUART1_OVERSAMPLING            UART_OVERSAMPLING_8
+
+#define CFG_HW_LPUART1_TX_PORT_CLK_ENABLE      __HAL_RCC_GPIOA_CLK_ENABLE
+#define CFG_HW_LPUART1_TX_PORT                 GPIOA
+#define CFG_HW_LPUART1_TX_PIN                  GPIO_PIN_2
+#define CFG_HW_LPUART1_TX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_LPUART1_TX_PULL                 GPIO_NOPULL
+#define CFG_HW_LPUART1_TX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_LPUART1_TX_ALTERNATE            GPIO_AF8_LPUART1
+
+#define CFG_HW_LPUART1_RX_PORT_CLK_ENABLE      __HAL_RCC_GPIOA_CLK_ENABLE
+#define CFG_HW_LPUART1_RX_PORT                 GPIOA
+#define CFG_HW_LPUART1_RX_PIN                  GPIO_PIN_3
+#define CFG_HW_LPUART1_RX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_LPUART1_RX_PULL                 GPIO_NOPULL
+#define CFG_HW_LPUART1_RX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_LPUART1_RX_ALTERNATE            GPIO_AF8_LPUART1
+
+#define CFG_HW_LPUART1_CTS_PORT_CLK_ENABLE     __HAL_RCC_GPIOA_CLK_ENABLE
+#define CFG_HW_LPUART1_CTS_PORT                GPIOA
+#define CFG_HW_LPUART1_CTS_PIN                 GPIO_PIN_6
+#define CFG_HW_LPUART1_CTS_MODE                GPIO_MODE_AF_PP
+#define CFG_HW_LPUART1_CTS_PULL                GPIO_PULLDOWN
+#define CFG_HW_LPUART1_CTS_SPEED               GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_LPUART1_CTS_ALTERNATE           GPIO_AF8_LPUART1
+
+#define CFG_HW_LPUART1_DMA_TX_PREEMPTPRIORITY  0x0F
+#define CFG_HW_LPUART1_DMA_TX_SUBPRIORITY      0
+
+#define CFG_HW_LPUART1_DMAMUX_CLK_ENABLE       __HAL_RCC_DMAMUX1_CLK_ENABLE
+#define CFG_HW_LPUART1_DMA_CLK_ENABLE          __HAL_RCC_DMA1_CLK_ENABLE
+#define CFG_HW_LPUART1_TX_DMA_REQ              DMA_REQUEST_LPUART1_TX
+#define CFG_HW_LPUART1_TX_DMA_CHANNEL          DMA1_CHANNEL_4
+#define CFG_HW_LPUART1_TX_DMA_IRQn             DMA1_CHANNEL_4_IRQn
+#define CFG_HW_LPUART1_DMA_TX_IRQHandler       DMA1_CHANNEL_4_IRQHandler
+
+/**
+ * UART1
+ */
+#define CFG_HW_USART1_PREEMPTPRIORITY         0x0F
+#define CFG_HW_USART1_SUBPRIORITY             0
+
+/** < The application shall check the selected source clock is enable */
+#define CFG_HW_USART1_SOURCE_CLOCK              RCC_USART1CLKSOURCE_SYSCLK
+
+#define CFG_HW_USART1_BAUDRATE                115200
+#define CFG_HW_USART1_WORDLENGTH              UART_WORDLENGTH_8B
+#define CFG_HW_USART1_STOPBITS                UART_STOPBITS_1
+#define CFG_HW_USART1_PARITY                  UART_PARITY_NONE
+#define CFG_HW_USART1_HWFLOWCTL               UART_HWCONTROL_NONE
+#define CFG_HW_USART1_MODE                    UART_MODE_TX_RX
+#define CFG_HW_USART1_ADVFEATUREINIT          UART_ADVFEATURE_NO_INIT
+#define CFG_HW_USART1_OVERSAMPLING            UART_OVERSAMPLING_8
+
+#define CFG_HW_USART1_TX_PORT_CLK_ENABLE      __HAL_RCC_GPIOB_CLK_ENABLE
+#define CFG_HW_USART1_TX_PORT                 GPIOB
+#define CFG_HW_USART1_TX_PIN                  GPIO_PIN_6
+#define CFG_HW_USART1_TX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_USART1_TX_PULL                 GPIO_NOPULL
+#define CFG_HW_USART1_TX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_TX_ALTERNATE            GPIO_AF7_USART1
+
+#define CFG_HW_USART1_RX_PORT_CLK_ENABLE      __HAL_RCC_GPIOB_CLK_ENABLE
+#define CFG_HW_USART1_RX_PORT                 GPIOB
+#define CFG_HW_USART1_RX_PIN                  GPIO_PIN_7
+#define CFG_HW_USART1_RX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_USART1_RX_PULL                 GPIO_NOPULL
+#define CFG_HW_USART1_RX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_RX_ALTERNATE            GPIO_AF7_USART1
+
+#define CFG_HW_USART1_CTS_PORT_CLK_ENABLE     __HAL_RCC_GPIOA_CLK_ENABLE
+#define CFG_HW_USART1_CTS_PORT                GPIOA
+#define CFG_HW_USART1_CTS_PIN                 GPIO_PIN_11
+#define CFG_HW_USART1_CTS_MODE                GPIO_MODE_AF_PP
+#define CFG_HW_USART1_CTS_PULL                GPIO_PULLDOWN
+#define CFG_HW_USART1_CTS_SPEED               GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_CTS_ALTERNATE           GPIO_AF7_USART1
+
+#define CFG_HW_USART1_DMA_TX_PREEMPTPRIORITY  0x0F
+#define CFG_HW_USART1_DMA_TX_SUBPRIORITY      0
+
+#define CFG_HW_USART1_DMAMUX_CLK_ENABLE       __HAL_RCC_DMAMUX1_CLK_ENABLE
+#define CFG_HW_USART1_DMA_CLK_ENABLE          __HAL_RCC_DMA2_CLK_ENABLE
+#define CFG_HW_USART1_TX_DMA_REQ			  DMA_REQUEST_USART1_TX
+#define CFG_HW_USART1_TX_DMA_CHANNEL          DMA2_CHANNEL_4
+#define CFG_HW_USART1_TX_DMA_IRQn             DMA2_CHANNEL_4_IRQn
+#define CFG_HW_USART1_DMA_TX_IRQHandler       DMA2_CHANNEL_4_IRQHandler
+
+#endif /*HW_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/hw_if.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/hw_if.h
new file mode 100644
index 000000000..5a15665ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/hw_if.h
@@ -0,0 +1,254 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    hw_if.h
+  * @author  MCD Application Team
+  * @brief   Hardware Interface
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef HW_IF_H
+#define HW_IF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_ipcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_hsem.h"
+#include "stm32wbxx_ll_gpio.h"
+#include "stm32wbxx_ll_rtc.h"
+
+#ifdef  USE_STM32WBXX_USB_DONGLE
+#include "stm32wbxx_usb_dongle.h"
+#endif
+#ifdef  USE_STM32WBXX_NUCLEO
+  #ifdef STM32WB35xx
+  #include "nucleo_wb35ce.h"
+  #else
+  #include "stm32wbxx_nucleo.h"
+  #endif
+#endif
+#ifdef  USE_X_NUCLEO_EPD
+#include "x_nucleo_epd.h"
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /******************************************************************************
+   * HW UART
+   ******************************************************************************/
+  typedef enum
+  {
+    hw_uart1,
+    hw_uart2,
+    hw_lpuart1,
+  } hw_uart_id_t;
+
+  typedef enum
+  {
+    hw_uart_ok,
+    hw_uart_error,
+    hw_uart_busy,
+    hw_uart_to,
+  } hw_status_t;
+
+  void HW_UART_Init(hw_uart_id_t hw_uart_id);
+  void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *pData, uint16_t Size, void (*Callback)(void));
+  void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *pData, uint16_t Size,  void (*Callback)(void));
+  hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout);
+  hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*Callback)(void));
+  void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id);
+  void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id);
+
+  /******************************************************************************
+   * HW TimerServer
+   ******************************************************************************/
+  /* Exported types ------------------------------------------------------------*/
+  /**
+   * This setting is used when standby mode is supported.
+   * hw_ts_InitMode_Limited should be used when the device restarts from Standby Mode. In that case, the Timer Server does
+   * not re-initialized its context. Only the Hardware register which content has been lost is reconfigured
+   * Otherwise, hw_ts_InitMode_Full should be requested (Start from Power ON) and everything is re-initialized.
+   */
+  typedef enum
+  {
+    hw_ts_InitMode_Full,
+    hw_ts_InitMode_Limited,
+  } HW_TS_InitMode_t;
+
+  /**
+   * When a Timer is created as a SingleShot timer, it is not automatically restarted when the timeout occurs. However,
+   * the timer is kept reserved in the list and could be restarted at anytime with HW_TS_Start()
+   *
+   * When a Timer is created as a Repeated timer, it is automatically restarted when the timeout occurs.
+   */
+  typedef enum
+  {
+    hw_ts_SingleShot,
+    hw_ts_Repeated
+  } HW_TS_Mode_t;
+
+  /**
+   * hw_ts_Successful is returned when a Timer has been successfully created with HW_TS_Create(). Otherwise, hw_ts_Failed
+   * is returned. When hw_ts_Failed is returned, that means there are not enough free slots in the list to create a
+   * Timer. In that case, CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER should be increased
+   */
+  typedef enum
+  {
+    hw_ts_Successful,
+    hw_ts_Failed,
+  }HW_TS_ReturnStatus_t;
+
+  typedef void (*HW_TS_pTimerCb_t)(void);
+
+  /**
+   * @brief  Initialize the timer server
+   *         This API shall be called by the application before any timer is requested to the timer server. It
+   *         configures the RTC module to be connected to the LSI input clock.
+   *
+   * @param  TimerInitMode: When the device restarts from Standby, it should request hw_ts_InitMode_Limited so that the
+   *         Timer context is not re-initialized. Otherwise, hw_ts_InitMode_Full should be requested
+   * @param  hrtc: RTC Handle
+   * @retval None
+   */
+  void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *hrtc);
+
+  /**
+   * @brief  Interface to create a virtual timer
+   *         The user shall call this API to create a timer. Once created, the timer is reserved to the module until it
+   *         has been deleted. When creating a timer, the user shall specify the mode (single shot or repeated), the
+   *         callback to be notified when the timer expires and a module ID to identify in the timer interrupt handler
+   *         which module is concerned. In return, the user gets a timer ID to handle it.
+   *
+   * @param  TimerProcessID:  This is an identifier provided by the user and returned in the callback to allow
+   *                          identification of the requester
+   * @param  pTimerId: Timer Id returned to the user to request operation (start, stop, delete)
+   * @param  TimerMode: Mode of the virtual timer (Single shot or repeated)
+   * @param  pTimerCallBack: Callback when the virtual timer expires
+   * @retval HW_TS_ReturnStatus_t: Return whether the creation is sucessfull or not
+   */
+  HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pTimerCallBack);
+
+  /**
+   * @brief  Stop a virtual timer
+   *         This API may be used to stop a running timer. A timer which is stopped is move to the pending state.
+   *         A pending timer may be restarted at any time with a different timeout value but the mode cannot be changed.
+   *         Nothing is done when it is called to stop a timer which has been already stopped
+   *
+   * @param  TimerID:  Id of the timer to stop
+   * @retval None
+   */
+  void HW_TS_Stop(uint8_t TimerID);
+
+  /**
+   * @brief  Start a virtual timer
+   *         This API shall be used to start a timer. The timeout value is specified and may be different each time.
+   *         When the timer is in the single shot mode, it will move to the pending state when it expires. The user may
+   *         restart it at any time with a different timeout value. When the timer is in the repeated mode, it always
+   *         stay in the running state. When the timer expires, it will be restarted with the same timeout value.
+   *         This API shall not be called on a running timer.
+   *
+   * @param  TimerID:  The ID Id of the timer to start
+   * @param  timeout_ticks: Number of ticks of the virtual timer (Maximum value is (0xFFFFFFFF-0xFFFF = 0xFFFF0000)
+   * @retval None
+   */
+  void HW_TS_Start(uint8_t TimerID, uint32_t timeout_ticks);
+
+  /**
+   * @brief  Delete a virtual timer from the list
+   *         This API should be used when a timer is not needed anymore by the user. A deleted timer is removed from
+   *         the timer list managed by the timer server. It cannot be restarted again. The user has to go with the
+   *         creation of a new timer if required and may get a different timer id
+   *
+   * @param  TimerID:  The ID of the timer to remove from the list
+   * @retval None
+   */
+  void HW_TS_Delete(uint8_t TimerID);
+
+  /**
+   * @brief  Schedule the timer list on the timer interrupt handler
+   *         This interrupt handler shall be called by the application in the RTC interrupt handler. This handler takes
+   *         care of clearing all status flag required in the RTC and EXTI peripherals
+   *
+   * @param  None
+   * @retval None
+   */
+  void HW_TS_RTC_Wakeup_Handler(void);
+
+  /**
+   * @brief  Return the number of ticks to count before the interrupt
+   *         This API returns the number of ticks left to be counted before an interrupt is generated by the
+   *         Timer Server. This API may be used by the application for power management optimization. When the system
+   *         enters low power mode, the mode selection is a tradeoff between the wakeup time where the CPU is running
+   *         and the time while the CPU will be kept in low power mode before next wakeup. The deeper is the
+   *         low power mode used, the longer is the wakeup time. The low power mode management considering wakeup time
+   *         versus time in low power mode is implementation specific
+   *         When the timer is disabled (No timer in the list), it returns 0xFFFF
+   *
+   * @param  None
+   * @retval The number of ticks left to count
+   */
+  uint16_t HW_TS_RTC_ReadLeftTicksToCount(void);
+
+  /**
+   * @brief  Notify the application that a registered timer has expired
+   *         This API shall be implemented by the user application.
+   *         This API notifies the application that a timer expires. This API is running in the RTC Wakeup interrupt
+   *         context. The application may implement an Operating System to change the context priority where the timer
+   *         callback may be handled. This API provides the module ID to identify which module is concerned and to allow
+   *         sending the information to the correct task
+   *
+   * @param  TimerProcessID: The TimerProcessId associated with the timer when it has been created
+   * @param  TimerID: The TimerID of the expired timer
+   * @param  pTimerCallBack: The Callback associated with the timer when it has been created
+   * @retval None
+   */
+  void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack);
+
+  /**
+   * @brief  Notify the application that the wakeupcounter has been updated
+   *         This API should be implemented by the user application
+   *         This API notifies the application that the counter has been updated. This is expected to be used along
+   *         with the HW_TS_RTC_ReadLeftTicksToCount () API. It could be that the counter has been updated since the
+   *         last call of HW_TS_RTC_ReadLeftTicksToCount () and before entering low power mode. This notification
+   *         provides a way to the application to solve that race condition to reevaluate the counter value before
+   *         entering low power mode
+   *
+   * @param  None
+   * @retval None
+   */
+  void HW_TS_RTC_CountUpdated_AppNot(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*HW_IF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/main.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/main.h
new file mode 100644
index 000000000..c8b13c23f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/main.h
@@ -0,0 +1,75 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#ifdef STM32WB35xx
+#include "nucleo_wb35ce.h"
+#else
+#include "stm32wbxx_nucleo.h"
+#endif
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/stm32_lpm_if.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/stm32_lpm_if.h
new file mode 100644
index 000000000..d8e67947f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/stm32_lpm_if.h
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+******************************************************************************
+* @file    stm32_lpm_if.h
+* @brief   Header for stm32_lpm_if.c module (device specific LP management)
+******************************************************************************
+* @attention
+*
+* 
    © Copyright (c) 2019 STMicroelectronics. 
+* All rights reserved.
    
+*
+* This software component is licensed by ST under BSD 3-Clause license,
+* the "License"; You may not use this file except in compliance with the 
+* License. You may obtain a copy of the License at:
+*                        opensource.org/licenses/BSD-3-Clause
+*
+******************************************************************************
+*/
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_LPM_IF_H
+#define __STM32_LPM_IF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/**
+  * @brief Enters Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_EnterOffMode( void );
+/**
+  * @brief Exits Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_ExitOffMode( void );
+
+/**
+  * @brief Enters Low Power Stop Mode
+  * @note ARM exists the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterStopMode( void );
+/**
+  * @brief Exits Low Power Stop Mode
+  * @note Enable the pll at 32MHz
+  * @param none
+  * @retval none
+  */
+void PWR_ExitStopMode( void );
+
+/**
+  * @brief Enters Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterSleepMode( void );
+
+/**
+  * @brief Exits Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_ExitSleepMode( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32_LPM_IF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..eff335ddf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,354 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+#define HAL_CORTEX_MODULE_ENABLED
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+/*#define HAL_I2C_MODULE_ENABLED   */
+#define HAL_IPCC_MODULE_ENABLED
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+#define HAL_PWR_MODULE_ENABLED
+/*#define HAL_QSPI_MODULE_ENABLED   */
+#define HAL_RCC_MODULE_ENABLED
+/*#define HAL_RNG_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100UL)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  (32000UL)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  (32000UL)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    (48000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    (2097000UL) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..cf6cc65e7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/stm32wbxx_it.h
@@ -0,0 +1,78 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "app_common.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void DMA1_Channel4_IRQHandler(void);
+void USART1_IRQHandler(void);
+void LPUART1_IRQHandler(void);
+void DMA2_Channel4_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+void RTC_WKUP_IRQHandler(void);
+void IPCC_C1_TX_IRQHandler(void);
+void IPCC_C1_RX_IRQHandler(void);
+void PUSH_BUTTON_SW1_EXTI_IRQHandler(void);
+void PUSH_BUTTON_SW2_EXTI_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/utilities_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/utilities_conf.h
new file mode 100644
index 000000000..4dde3509a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Inc/utilities_conf.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : utilities_conf.h
+  * Description        : Configuration file for STM32 Utilities.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef UTILITIES_CONF_H
+#define UTILITIES_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "cmsis_compiler.h"
+#include "string.h"
+
+/******************************************************************************
+ * common
+ ******************************************************************************/
+#define UTILS_ENTER_CRITICAL_SECTION( )   uint32_t primask_bit = __get_PRIMASK( );\
+                                          __disable_irq( )
+
+#define UTILS_EXIT_CRITICAL_SECTION( )          __set_PRIMASK( primask_bit )
+
+#define UTILS_MEMSET8( dest, value, size )      memset( dest, value, size);
+
+/******************************************************************************
+ * tiny low power manager
+ * (any macro that does not need to be modified can be removed)
+ ******************************************************************************/
+#define UTIL_LPM_INIT_CRITICAL_SECTION( )
+#define UTIL_LPM_ENTER_CRITICAL_SECTION( )      UTILS_ENTER_CRITICAL_SECTION( )
+#define UTIL_LPM_EXIT_CRITICAL_SECTION( )       UTILS_EXIT_CRITICAL_SECTION( )
+
+/******************************************************************************
+ * sequencer
+ * (any macro that does not need to be modified can be removed)
+ ******************************************************************************/
+#define UTIL_SEQ_INIT_CRITICAL_SECTION( )
+#define UTIL_SEQ_ENTER_CRITICAL_SECTION( )      UTILS_ENTER_CRITICAL_SECTION( )
+#define UTIL_SEQ_EXIT_CRITICAL_SECTION( )       UTILS_EXIT_CRITICAL_SECTION( )
+#define UTIL_SEQ_CONF_TASK_NBR                  (32)
+#define UTIL_SEQ_CONF_PRIO_NBR                  (2)
+#define UTIL_SEQ_MEMSET8( dest, value, size )   UTILS_MEMSET8( dest, value, size )
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*UTILITIES_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/app_debug.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/app_debug.c
new file mode 100644
index 000000000..af3fdfbce
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/app_debug.c
@@ -0,0 +1,360 @@
+/**
+ ******************************************************************************
+ * @file    app_debug.c
+ * @author  MCD Application Team
+ * @brief   Debug capabilities
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+extern void MX_LPUART1_UART_Init(void);
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+extern void MX_USART1_UART_Init(void);
+#endif
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+#if (CFG_HW_USART1_ENABLED == 1)
+    MX_USART1_UART_Init();
+#endif
+#if (CFG_HW_LPUART1_ENABLED == 1)
+    MX_LPUART1_UART_Init();
+#endif
+  return;
+}
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/app_entry.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/app_entry.c
new file mode 100644
index 000000000..52ea9ea05
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/app_entry.c
@@ -0,0 +1,300 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    app_entry.c
+ * @author  MCD Application Team
+ * @brief   Entry point of the Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "main.h"
+#include "app_entry.h"
+#include "app_ble.h"
+#include "ble.h"
+#include "tl.h"
+#include "stm32_seq.h"
+#include "shci_tl.h"
+#include "stm32_lpm.h"
+#include "app_debug.h"
+
+/* Private includes -----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+extern RTC_HandleTypeDef hrtc;
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+#define POOL_SIZE (CFG_TLBLE_EVT_QUEUE_LENGTH*4U*DIVC(( sizeof(TL_PacketHeader_t) + TL_BLE_EVENT_FRAME_SIZE ), 4U))
+
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t EvtPool[POOL_SIZE];
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static TL_CmdPacket_t SystemCmdBuffer;
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t SystemSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255U];
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t BleSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255];
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private functions prototypes-----------------------------------------------*/
+static void SystemPower_Config( void );
+static void appe_Tl_Init( void );
+static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status );
+static void APPE_SysUserEvtRx( void * pPayload );
+
+/* USER CODE BEGIN PFP */
+static void Led_Init( void );
+static void Button_Init( void );
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APPE_Init( void )
+{
+  SystemPower_Config(); /**< Configure the system Power Mode */
+
+  HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
+
+/* USER CODE BEGIN APPE_Init_1 */
+  APPD_Init();
+  
+  /**
+   * The Standby mode should not be entered before the initialization is over
+   * The default state of the Low Power Manager is to allow the Standby Mode so an request is needed here
+   */
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP, UTIL_LPM_DISABLE);
+
+  Led_Init();
+
+  Button_Init();
+/* USER CODE END APPE_Init_1 */
+  appe_Tl_Init();	/* Initialize all transport layers */
+
+  /**
+   * From now, the application is waiting for the ready event ( VS_HCI_C2_Ready )
+   * received on the system channel before starting the Stack
+   * This system event is received with APPE_SysUserEvtRx()
+   */
+/* USER CODE BEGIN APPE_Init_2 */
+
+/* USER CODE END APPE_Init_2 */
+   return;
+}
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+ * @brief  Configure the system for power optimization
+ *
+ * @note  This API configures the system to be ready for low power mode
+ *
+ * @param  None
+ * @retval None
+ */
+static void SystemPower_Config( void )
+{
+
+  /**
+   * Select HSI as system clock source after Wake Up from Stop mode
+   */
+  LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
+
+  /* Initialize low power manager */
+  UTIL_LPM_Init( );
+
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+  /**
+   *  Enable USB power
+   */
+  HAL_PWREx_EnableVddUSB();
+#endif
+
+  return;
+}
+
+static void appe_Tl_Init( void )
+{
+  TL_MM_Config_t tl_mm_config;
+  SHCI_TL_HciInitConf_t SHci_Tl_Init_Conf;
+  /**< Reference table initialization */
+  TL_Init();
+
+  /**< System channel initialization */
+  UTIL_SEQ_RegTask( 1<< CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID, UTIL_SEQ_RFU, shci_user_evt_proc );
+  SHci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&SystemCmdBuffer;
+  SHci_Tl_Init_Conf.StatusNotCallBack = APPE_SysStatusNot;
+  shci_init(APPE_SysUserEvtRx, (void*) &SHci_Tl_Init_Conf);
+
+  /**< Memory Manager channel initialization */
+  tl_mm_config.p_BleSpareEvtBuffer = BleSpareEvtBuffer;
+  tl_mm_config.p_SystemSpareEvtBuffer = SystemSpareEvtBuffer;
+  tl_mm_config.p_AsynchEvtPool = EvtPool;
+  tl_mm_config.AsynchEvtPoolSize = POOL_SIZE;
+  TL_MM_Init( &tl_mm_config );
+
+  TL_Enable();
+
+  return;
+}
+
+static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status )
+{
+  UNUSED(status);
+  return;
+}
+
+/**
+ * The type of the payload for a system user event is tSHCI_UserEvtRxParam
+ * When the system event is both :
+ *    - a ready event (subevtcode = SHCI_SUB_EVT_CODE_READY)
+ *    - reported by the FUS (sysevt_ready_rsp == RSS_FW_RUNNING)
+ * The buffer shall not be released
+ * ( eg ((tSHCI_UserEvtRxParam*)pPayload)->status shall be set to SHCI_TL_UserEventFlow_Disable )
+ * When the status is not filled, the buffer is released by default
+ */
+static void APPE_SysUserEvtRx( void * pPayload )
+{
+  UNUSED(pPayload);
+  /* Traces channel initialization */
+  APPD_EnableCPU2();
+
+  APP_BLE_Init( );
+  UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE);
+  return;
+}
+
+/* USER CODE BEGIN FD_LOCAL_FUNCTIONS */
+static void Led_Init( void )
+{
+#if (CFG_LED_SUPPORTED == 1)
+  /**
+   * Leds Initialization
+   */
+
+  BSP_LED_Init(LED_BLUE);
+  BSP_LED_Init(LED_GREEN);
+  BSP_LED_Init(LED_RED);
+
+  BSP_LED_On(LED_GREEN);
+#endif
+
+  return;
+}
+
+static void Button_Init( void )
+{
+#if (CFG_BUTTON_SUPPORTED == 1)
+  /**
+   * Button Initialization
+   */
+
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+  BSP_PB_Init(BUTTON_SW2, BUTTON_MODE_EXTI);
+#endif
+
+  return;
+}
+/* USER CODE END FD_LOCAL_FUNCTIONS */
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+
+void UTIL_SEQ_Idle( void )
+{
+#if ( CFG_LPM_SUPPORTED == 1)
+  UTIL_LPM_EnterLowPower( );
+#endif
+  return;
+}
+
+/**
+  * @brief  This function is called by the scheduler each time an event
+  *         is pending.
+  *
+  * @param  evt_waited_bm : Event pending.
+  * @retval None
+  */
+void UTIL_SEQ_EvtIdle( UTIL_SEQ_bm_t task_id_bm, UTIL_SEQ_bm_t evt_waited_bm )
+{
+  UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+}
+
+void shci_notify_asynch_evt(void* pdata)
+{
+  UTIL_SEQ_SetTask( 1<
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "hw_conf.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef enum
+{
+  TimerID_Free,
+  TimerID_Created,
+  TimerID_Running
+}TimerIDStatus_t;
+
+typedef enum
+{
+  SSR_Read_Requested,
+  SSR_Read_Not_Requested
+}RequestReadSSR_t;
+
+typedef enum
+{
+  WakeupTimerValue_Overpassed,
+  WakeupTimerValue_LargeEnough
+}WakeupTimerLimitation_Status_t;
+
+typedef struct
+{
+  HW_TS_pTimerCb_t  pTimerCallBack;
+  uint32_t        CounterInit;
+  uint32_t        CountLeft;
+  TimerIDStatus_t     TimerIDStatus;
+  HW_TS_Mode_t   TimerMode;
+  uint32_t        TimerProcessID;
+  uint8_t         PreviousID;
+  uint8_t         NextID;
+}TimerContext_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define SSR_FORBIDDEN_VALUE   0xFFFFFFFF
+#define TIMER_LIST_EMPTY      0xFFFF
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/**
+ * START of Section TIMERSERVER_CONTEXT
+ */
+
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile TimerContext_t aTimerContext[CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER];
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint8_t CurrentRunningTimerID;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint8_t PreviousRunningTimerID;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint32_t SSRValueOnLastSetup;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile WakeupTimerLimitation_Status_t  WakeupTimerLimitation;
+
+/**
+ * END of Section TIMERSERVER_CONTEXT
+ */
+
+static RTC_HandleTypeDef *phrtc;  /**< RTC handle */
+static uint8_t  WakeupTimerDivider;
+static uint8_t  AsynchPrescalerUserConfig;
+static uint16_t SynchPrescalerUserConfig;
+static volatile uint16_t MaxWakeupTimerSetup;
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void RestartWakeupCounter(uint16_t Value);
+static uint16_t ReturnTimeElapsed(void);
+static void RescheduleTimerList(void);
+static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR);
+static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID);
+static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID);
+static uint16_t linkTimer(uint8_t TimerID);
+static uint32_t ReadRtcSsrValue(void);
+
+__weak void HW_TS_RTC_CountUpdated_AppNot(void);
+
+/* Functions Definition ------------------------------------------------------*/
+
+/**
+ * @brief  Read the RTC_SSR value
+ *         As described in the reference manual, the RTC_SSR shall be read twice to ensure
+ *         reliability of the value
+ * @param  None
+ * @retval SSR value read
+ */
+static uint32_t ReadRtcSsrValue(void)
+{
+  uint32_t first_read;
+  uint32_t second_read;
+
+  first_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+
+  second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+
+  while(first_read != second_read)
+  {
+    first_read = second_read;
+
+    second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+  }
+
+  return second_read;
+}
+
+/**
+ * @brief  Insert a Timer in the list after the Timer ID specified
+ * @param  TimerID:   The ID of the Timer
+ * @param  RefTimerID: The ID of the Timer to be linked after
+ * @retval None
+ */
+static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID)
+{
+  uint8_t next_id;
+
+  next_id = aTimerContext[RefTimerID].NextID;
+
+  if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    aTimerContext[next_id].PreviousID = TimerID;
+  }
+  aTimerContext[TimerID].NextID = next_id;
+  aTimerContext[TimerID].PreviousID = RefTimerID ;
+  aTimerContext[RefTimerID].NextID = TimerID;
+
+  return;
+}
+
+/**
+ * @brief  Insert a Timer in the list before the ID specified
+ * @param  TimerID:   The ID of the Timer
+ * @param  RefTimerID: The ID of the Timer to be linked before
+ * @retval None
+ */
+static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID)
+{
+  uint8_t previous_id;
+
+  if(RefTimerID != CurrentRunningTimerID)
+  {
+    previous_id = aTimerContext[RefTimerID].PreviousID;
+
+    aTimerContext[previous_id].NextID = TimerID;
+    aTimerContext[TimerID].NextID = RefTimerID;
+    aTimerContext[TimerID].PreviousID = previous_id ;
+    aTimerContext[RefTimerID].PreviousID = TimerID;
+  }
+  else
+  {
+    aTimerContext[TimerID].NextID = RefTimerID;
+    aTimerContext[RefTimerID].PreviousID = TimerID;
+  }
+
+  return;
+}
+
+/**
+ * @brief  Insert a Timer in the list
+ * @param  TimerID:   The ID of the Timer
+ * @retval None
+ */
+static uint16_t linkTimer(uint8_t TimerID)
+{
+  uint32_t time_left;
+  uint16_t time_elapsed;
+  uint8_t timer_id_lookup;
+  uint8_t next_id;
+
+  if(CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    /**
+     * No timer in the list
+     */
+    PreviousRunningTimerID = CurrentRunningTimerID;
+    CurrentRunningTimerID = TimerID;
+    aTimerContext[TimerID].NextID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;
+
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+    time_elapsed = 0;
+  }
+  else
+  {
+    time_elapsed = ReturnTimeElapsed();
+
+    /**
+     * update count of the timer to be linked
+     */
+    aTimerContext[TimerID].CountLeft += time_elapsed;
+    time_left = aTimerContext[TimerID].CountLeft;
+
+    /**
+     * Search for index where the new timer shall be linked
+     */
+    if(aTimerContext[CurrentRunningTimerID].CountLeft <= time_left)
+    {
+      /**
+       * Search for the ID after the first one
+       */
+      timer_id_lookup = CurrentRunningTimerID;
+      next_id = aTimerContext[timer_id_lookup].NextID;
+      while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left))
+      {
+        timer_id_lookup = aTimerContext[timer_id_lookup].NextID;
+        next_id = aTimerContext[timer_id_lookup].NextID;
+      }
+
+      /**
+       * Link after the ID
+       */
+      LinkTimerAfter(TimerID, timer_id_lookup);
+    }
+    else
+    {
+      /**
+       * Link before the first ID
+       */
+      LinkTimerBefore(TimerID, CurrentRunningTimerID);
+      PreviousRunningTimerID = CurrentRunningTimerID;
+      CurrentRunningTimerID = TimerID;
+    }
+  }
+
+  return time_elapsed;
+}
+
+/**
+ * @brief  Remove a Timer from the list
+ * @param  TimerID:   The ID of the Timer
+ * @param  RequestReadSSR: Request to read the SSR register or not
+ * @retval None
+ */
+static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR)
+{
+  uint8_t previous_id;
+  uint8_t next_id;
+
+  if(TimerID == CurrentRunningTimerID)
+  {
+    PreviousRunningTimerID = CurrentRunningTimerID;
+    CurrentRunningTimerID = aTimerContext[TimerID].NextID;
+  }
+  else
+  {
+    previous_id = aTimerContext[TimerID].PreviousID;
+    next_id = aTimerContext[TimerID].NextID;
+
+    aTimerContext[previous_id].NextID = aTimerContext[TimerID].NextID;
+    if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+    {
+      aTimerContext[next_id].PreviousID = aTimerContext[TimerID].PreviousID;
+    }
+  }
+
+  /**
+   * Timer is out of the list
+   */
+  aTimerContext[TimerID].TimerIDStatus = TimerID_Created;
+
+  if((CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (RequestReadSSR == SSR_Read_Requested))
+  {
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+  }
+
+  return;
+}
+
+/**
+ * @brief  Return the number of ticks counted by the wakeuptimer since it has been started
+ * @note  The API is reading the SSR register to get how many ticks have been counted
+ *        since the time the timer has been started
+ * @param  None
+ * @retval Time expired in Ticks
+ */
+static uint16_t ReturnTimeElapsed(void)
+{
+  uint32_t  return_value;
+  uint32_t  wrap_counter;
+
+  if(SSRValueOnLastSetup != SSR_FORBIDDEN_VALUE)
+  {
+    return_value = ReadRtcSsrValue(); /**< Read SSR register first */
+
+    if (SSRValueOnLastSetup >= return_value)
+    {
+      return_value = SSRValueOnLastSetup - return_value;
+    }
+    else
+    {
+      wrap_counter = SynchPrescalerUserConfig - return_value;
+      return_value = SSRValueOnLastSetup + wrap_counter;
+    }
+
+    /**
+     * At this stage, ReturnValue holds the number of ticks counted by SSR
+     * Need to translate in number of ticks counted by the Wakeuptimer
+     */
+    return_value = return_value*AsynchPrescalerUserConfig;
+    return_value = return_value >> WakeupTimerDivider;
+  }
+  else
+  {
+    return_value = 0;
+  }
+
+  return (uint16_t)return_value;
+}
+
+/**
+ * @brief  Set the wakeup counter
+ * @note  The API is writing the counter value so that the value is decreased by one to cope with the fact
+ *    the interrupt is generated with 1 extra clock cycle (See RefManuel)
+ *    It assumes all condition are met to be allowed to write the wakeup counter
+ * @param  Value: Value to be written in the counter
+ * @retval None
+ */
+static void RestartWakeupCounter(uint16_t Value)
+{
+  /**
+   * The wakeuptimer has been disabled in the calling function to reduce the time to poll the WUTWF
+   * FLAG when the new value will have to be written
+   *  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);
+   */
+
+  if(Value == 0)
+  {
+    SSRValueOnLastSetup = ReadRtcSsrValue();
+
+    /**
+     * Simulate that the Timer expired
+     */
+    HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
+  }
+  else
+  {
+    if((Value > 1) ||(WakeupTimerDivider != 1))
+    {
+      Value -= 1;
+    }
+
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+    /**
+     * make sure to clear the flags after checking the WUTWF.
+     * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+     * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+     * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+     * due to the autoreload feature
+     */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+    HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);   /**<  Clear pending bit in NVIC */
+
+    MODIFY_REG(RTC->WUTR, RTC_WUTR_WUT, Value);
+
+    /**
+     * Update the value here after the WUTWF polling that may take some time
+     */
+    SSRValueOnLastSetup = ReadRtcSsrValue();
+
+    __HAL_RTC_WAKEUPTIMER_ENABLE(phrtc);    /**<  Enable the Wakeup Timer */
+
+    HW_TS_RTC_CountUpdated_AppNot();
+  }
+
+  return ;
+}
+
+/**
+ * @brief  Reschedule the list of timer
+ * @note  1) Update the count left for each timer in the list
+ *    2) Setup the wakeuptimer
+ * @param  None
+ * @retval None
+ */
+static void RescheduleTimerList(void)
+{
+  uint8_t   localTimerID;
+  uint32_t  timecountleft;
+  uint16_t  wakeup_timer_value;
+  uint16_t  time_elapsed;
+
+  /**
+   * The wakeuptimer is disabled now to reduce the time to poll the WUTWF
+   * FLAG when the new value will have to be written
+   */
+  if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+  {
+    /**
+     * Wait for the flag to be back to 0 when the wakeup timer is enabled
+     */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == SET);
+  }
+  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);   /**<  Disable the Wakeup Timer */
+
+  localTimerID = CurrentRunningTimerID;
+
+  /**
+   * Calculate what will be the value to write in the wakeuptimer
+   */
+  timecountleft = aTimerContext[localTimerID].CountLeft;
+
+  /**
+   * Read how much has been counted
+   */
+  time_elapsed = ReturnTimeElapsed();
+
+  if(timecountleft < time_elapsed )
+  {
+    /**
+     * There is no tick left to count
+     */
+    wakeup_timer_value = 0;
+    WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+  }
+  else
+  {
+    if(timecountleft > (time_elapsed + MaxWakeupTimerSetup))
+    {
+      /**
+       * The number of tick left is greater than the Wakeuptimer maximum value
+       */
+      wakeup_timer_value = MaxWakeupTimerSetup;
+
+      WakeupTimerLimitation = WakeupTimerValue_Overpassed;
+    }
+    else
+    {
+      wakeup_timer_value = timecountleft - time_elapsed;
+      WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+    }
+
+  }
+
+  /**
+   * update ticks left to be counted for each timer
+   */
+  while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    if (aTimerContext[localTimerID].CountLeft < time_elapsed)
+    {
+      aTimerContext[localTimerID].CountLeft = 0;
+    }
+    else
+    {
+      aTimerContext[localTimerID].CountLeft -= time_elapsed;
+    }
+    localTimerID = aTimerContext[localTimerID].NextID;
+  }
+
+  /**
+   * Write next count
+   */
+  RestartWakeupCounter(wakeup_timer_value);
+
+  return ;
+}
+
+/* Public functions ----------------------------------------------------------*/
+
+/**
+ * For all public interface except that may need write access to the RTC, the RTC
+ * shall be unlock at the beginning and locked at the output
+ * In order to ease maintainability, the unlock is done at the top and the lock at then end
+ * in case some new implementation is coming in the future
+ */
+
+void HW_TS_RTC_Wakeup_Handler(void)
+{
+  HW_TS_pTimerCb_t ptimer_callback;
+  uint32_t timer_process_id;
+  uint8_t local_current_running_timer_id;
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  /**
+   * Disable the Wakeup Timer
+   * This may speed up a bit the processing to wait the timer to be disabled
+   * The timer is still counting 2 RTCCLK
+   */
+  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);
+
+  local_current_running_timer_id = CurrentRunningTimerID;
+
+  if(aTimerContext[local_current_running_timer_id].TimerIDStatus == TimerID_Running)
+  {
+    ptimer_callback = aTimerContext[local_current_running_timer_id].pTimerCallBack;
+    timer_process_id = aTimerContext[local_current_running_timer_id].TimerProcessID;
+
+    /**
+     * It should be good to check whether the TimeElapsed is greater or not than the tick left to be counted
+     * However, due to the inaccuracy of the reading of the time elapsed, it may return there is 1 tick
+     * to be left whereas the count is over
+     * A more secure implementation has been done with a flag to state whereas the full count has been written
+     * in the wakeuptimer or not
+     */
+    if(WakeupTimerLimitation != WakeupTimerValue_Overpassed)
+    {
+      if(aTimerContext[local_current_running_timer_id].TimerMode == hw_ts_Repeated)
+      {
+        UnlinkTimer(local_current_running_timer_id, SSR_Read_Not_Requested);
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+        __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+        HW_TS_Start(local_current_running_timer_id, aTimerContext[local_current_running_timer_id].CounterInit);
+
+        /* Disable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+      }
+      else
+      {
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+        __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+        HW_TS_Stop(local_current_running_timer_id);
+
+        /* Disable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+      }
+
+      HW_TS_RTC_Int_AppNot(timer_process_id, local_current_running_timer_id, ptimer_callback);
+    }
+    else
+    {
+      RescheduleTimerList();
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+      __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+    }
+  }
+  else
+  {
+    /**
+     * We should never end up in this case
+     * However, if due to any bug in the timer server this is the case, the mistake may not impact the user.
+     * We could just clean the interrupt flag and get out from this unexpected interrupt
+     */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+    /**
+     * make sure to clear the flags after checking the WUTWF.
+     * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+     * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+     * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+     * due to the autoreload feature
+     */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  return;
+}
+
+void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *hrtc)
+{
+  uint8_t loop;
+  uint32_t localmaxwakeuptimersetup;
+
+  /**
+   * Get RTC handler
+   */
+  phrtc = hrtc;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
+
+  /**
+   * Readout the user config
+   */
+  WakeupTimerDivider = (4 - ((uint32_t)(READ_BIT(RTC->CR, RTC_CR_WUCKSEL))));
+
+  AsynchPrescalerUserConfig = (uint8_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_A) >> (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)) + 1;
+
+  SynchPrescalerUserConfig = (uint16_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_S)) + 1;
+
+  /**
+   *  Margin is taken to avoid wrong calculation when the wrap around is there and some
+   *  application interrupts may have delayed the reading
+   */
+  localmaxwakeuptimersetup = ((((SynchPrescalerUserConfig - 1)*AsynchPrescalerUserConfig) - CFG_HW_TS_RTC_HANDLER_MAX_DELAY) >> WakeupTimerDivider);
+
+  if(localmaxwakeuptimersetup >= 0xFFFF)
+  {
+    MaxWakeupTimerSetup = 0xFFFF;
+  }
+  else
+  {
+    MaxWakeupTimerSetup = (uint16_t)localmaxwakeuptimersetup;
+  }
+
+  /**
+   * Configure EXTI module
+   */
+  LL_EXTI_EnableRisingTrig_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+  LL_EXTI_EnableIT_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+
+  if(TimerInitMode == hw_ts_InitMode_Full)
+  {
+    WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+
+    /**
+     * Initialize the timer server
+     */
+    for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++)
+    {
+      aTimerContext[loop].TimerIDStatus = TimerID_Free;
+    }
+
+    CurrentRunningTimerID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;   /**<  Set ID to non valid value */
+
+    __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);                       /**<  Disable the Wakeup Timer */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);     /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module  */
+    HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);       /**<  Clear pending bit in NVIC  */
+    __HAL_RTC_WAKEUPTIMER_ENABLE_IT(phrtc, RTC_IT_WUT);         /**<  Enable interrupt in RTC module  */
+  }
+  else
+  {
+    if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTF) != RESET)
+    {
+      /**
+       * Simulate that the Timer expired
+       */
+      HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_SetPriority(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO);   /**<  Set NVIC priority */
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+  return;
+}
+
+HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pftimeout_handler)
+{
+  HW_TS_ReturnStatus_t localreturnstatus;
+  uint8_t loop = 0;
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  while((loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[loop].TimerIDStatus != TimerID_Free))
+  {
+    loop++;
+  }
+
+  if(loop != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    aTimerContext[loop].TimerIDStatus = TimerID_Created;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+    aTimerContext[loop].TimerProcessID = TimerProcessID;
+    aTimerContext[loop].TimerMode = TimerMode;
+    aTimerContext[loop].pTimerCallBack = pftimeout_handler;
+    *pTimerId = loop;
+
+    localreturnstatus = hw_ts_Successful;
+  }
+  else
+  {
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+    localreturnstatus = hw_ts_Failed;
+  }
+
+  return(localreturnstatus);
+}
+
+void HW_TS_Delete(uint8_t timer_id)
+{
+  HW_TS_Stop(timer_id);
+
+  aTimerContext[timer_id].TimerIDStatus = TimerID_Free; /**<  release ID */
+
+  return;
+}
+
+void HW_TS_Stop(uint8_t timer_id)
+{
+  uint8_t localcurrentrunningtimerid;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);    /**<  Disable NVIC */
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
+  {
+    UnlinkTimer(timer_id, SSR_Read_Requested);
+    localcurrentrunningtimerid = CurrentRunningTimerID;
+
+    if(localcurrentrunningtimerid == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+    {
+      /**
+       * List is empty
+       */
+
+      /**
+       * Disable the timer
+       */
+      if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+      {
+        /**
+         * Wait for the flag to be back to 0 when the wakeup timer is enabled
+         */
+        while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == SET);
+      }
+      __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);   /**<  Disable the Wakeup Timer */
+
+      while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+      /**
+       * make sure to clear the flags after checking the WUTWF.
+       * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+       * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+       * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+       * due to the autoreload feature
+       */
+      __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+      __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+      HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);   /**<  Clear pending bit in NVIC */
+    }
+    else if(PreviousRunningTimerID != localcurrentrunningtimerid)
+    {
+      RescheduleTimerList();
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+  return;
+}
+
+void HW_TS_Start(uint8_t timer_id, uint32_t timeout_ticks)
+{
+  uint16_t time_elapsed;
+  uint8_t localcurrentrunningtimerid;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+  if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
+  {
+    HW_TS_Stop( timer_id );
+  }
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);    /**<  Disable NVIC */
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  aTimerContext[timer_id].TimerIDStatus = TimerID_Running;
+
+  aTimerContext[timer_id].CountLeft = timeout_ticks;
+  aTimerContext[timer_id].CounterInit = timeout_ticks;
+
+  time_elapsed =  linkTimer(timer_id);
+
+  localcurrentrunningtimerid = CurrentRunningTimerID;
+
+  if(PreviousRunningTimerID != localcurrentrunningtimerid)
+  {
+    RescheduleTimerList();
+  }
+  else
+  {
+    aTimerContext[timer_id].CountLeft -= time_elapsed;
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+  return;
+}
+
+uint16_t HW_TS_RTC_ReadLeftTicksToCount(void)
+{
+  uint32_t primask_bit;
+  uint16_t return_value, auro_reload_value, elapsed_time_value;
+
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();                /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+
+  if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+  {
+    auro_reload_value = (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT));
+
+    elapsed_time_value = ReturnTimeElapsed();
+
+    if(auro_reload_value > elapsed_time_value)
+    {
+      return_value = auro_reload_value - elapsed_time_value;
+    }
+    else
+    {
+      return_value = 0;
+    }
+  }
+  else
+  {
+    return_value = TIMER_LIST_EMPTY;
+  }
+
+  __set_PRIMASK(primask_bit);     /**< Restore PRIMASK bit*/
+
+  return (return_value);
+}
+
+__weak void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack)
+{
+  pTimerCallBack();
+
+  return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/hw_uart.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/hw_uart.c
new file mode 100644
index 000000000..9a553610d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/hw_uart.c
@@ -0,0 +1,318 @@
+/**
+ ******************************************************************************
+  * File Name          : Src/hw_uart.c
+  * Description        : HW UART source file for STM32WPAN Middleware.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "hw_conf.h"
+#if (CFG_HW_LPUART1_ENABLED == 1)
+extern UART_HandleTypeDef hlpuart1;
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+extern UART_HandleTypeDef huart1;
+#endif
+
+/* Macros --------------------------------------------------------------------*/
+#define HW_UART_RX_IT(__HANDLE__, __USART_BASE__)                                                   \
+        do{                                                                                         \
+            HW_##__HANDLE__##RxCb = cb;                                                             \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            HAL_UART_Receive_IT(&(__HANDLE__), p_data, size);                                       \
+        } while(0)
+
+#define HW_UART_TX_IT(__HANDLE__, __USART_BASE__)                                                   \
+        do{                                                                                         \
+            HW_##__HANDLE__##TxCb = cb;                                                             \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            HAL_UART_Transmit_IT(&(__HANDLE__), p_data, size);                                      \
+        } while(0)
+
+#define HW_UART_TX(__HANDLE__, __USART_BASE__)                                                      \
+        do{                                                                                         \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            hal_status = HAL_UART_Transmit(&(__HANDLE__), p_data, size, timeout);                   \
+        } while(0)
+
+/* Variables -----------------------------------------------------------------*/
+#if (CFG_HW_USART1_ENABLED == 1)
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+    DMA_HandleTypeDef HW_hdma_huart1_tx ={0};
+#endif
+    void (*HW_huart1RxCb)(void);
+    void (*HW_huart1TxCb)(void);
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+    DMA_HandleTypeDef HW_hdma_hlpuart1_tx ={0};
+#endif
+    void (*HW_hlpuart1RxCb)(void);
+    void (*HW_hlpuart1TxCb)(void);
+#endif
+
+void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_RX_IT(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_RX_IT(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  void (*cb)(void))
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_TX_IT(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_TX_IT(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout)
+{
+    HAL_StatusTypeDef hal_status = HAL_OK;
+    hw_status_t hw_status = hw_uart_ok;
+
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_TX(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_TX(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    switch (hal_status)
+    {
+        case HAL_OK:
+            hw_status = hw_uart_ok;
+            break;
+
+        case HAL_ERROR:
+            hw_status = hw_uart_error;
+            break;
+
+        case HAL_BUSY:
+            hw_status = hw_uart_busy;
+            break;
+
+        case HAL_TIMEOUT:
+            hw_status = hw_uart_to;
+            break;
+
+        default:
+            break;
+    }
+
+    return hw_status;
+}
+
+hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+{
+    HAL_StatusTypeDef hal_status = HAL_OK;
+    hw_status_t hw_status = hw_uart_ok;
+
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_huart1TxCb = cb;
+            huart1.Instance = USART1;
+            hal_status = HAL_UART_Transmit_DMA(&huart1, p_data, size);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_hlpuart1TxCb = cb;
+            hlpuart1.Instance = LPUART1;
+            hal_status = HAL_UART_Transmit_DMA(&hlpuart1, p_data, size);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    switch (hal_status)
+    {
+        case HAL_OK:
+            hw_status = hw_uart_ok;
+            break;
+
+        case HAL_ERROR:
+            hw_status = hw_uart_error;
+            break;
+
+        case HAL_BUSY:
+            hw_status = hw_uart_busy;
+            break;
+
+        case HAL_TIMEOUT:
+            hw_status = hw_uart_to;
+            break;
+
+        default:
+            break;
+    }
+
+    return hw_status;
+}
+
+void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HAL_UART_IRQHandler(&huart1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HAL_UART_IRQHandler(&hlpuart1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+        case hw_uart1:
+            HAL_DMA_IRQHandler(huart1.hdmatx);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+        case hw_lpuart1:
+            HAL_DMA_IRQHandler(hlpuart1.hdmatx);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+    switch ((uint32_t)huart->Instance)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case (uint32_t)USART1:
+            if(HW_huart1RxCb)
+            {
+                HW_huart1RxCb();
+            }
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case (uint32_t)LPUART1:
+            if(HW_hlpuart1RxCb)
+            {
+                HW_hlpuart1RxCb();
+            }
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+    switch ((uint32_t)huart->Instance)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case (uint32_t)USART1:
+            if(HW_huart1TxCb)
+            {
+                HW_huart1TxCb();
+            }
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case (uint32_t)LPUART1:
+            if(HW_hlpuart1TxCb)
+            {
+                HW_hlpuart1TxCb();
+            }
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/main.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/main.c
new file mode 100644
index 000000000..b4c3d4dd6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/main.c
@@ -0,0 +1,641 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    main.c
+ * @author  MCD Application Team
+ * @brief   BLE application with BLE core
+ *
+  @verbatim
+  ==============================================================================
+                    ##### IMPORTANT NOTE #####
+  ==============================================================================
+
+  This application requests having the stm32wb5x_BLE_Stack_fw.bin binary
+  flashed on the Wireless Coprocessor.
+  If it is not the case, you need to use STM32CubeProgrammer to load the appropriate
+  binary.
+
+  All available binaries are located under following directory:
+  /Projects/STM32_Copro_Wireless_Binaries
+
+  Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+  Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the
+  detailed procedure to change the Wireless Coprocessor binary.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "app_entry.h"
+#include "app_common.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "stm32_lpm.h"
+#include "stm32_seq.h"
+#include "dbg_trace.h"
+#include "hw_conf.h"
+#include "otp.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef hlpuart1;
+UART_HandleTypeDef huart1;
+DMA_HandleTypeDef hdma_lpuart1_tx;
+DMA_HandleTypeDef hdma_usart1_tx;
+
+RTC_HandleTypeDef hrtc;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+void MX_LPUART1_UART_Init(void);
+void MX_USART1_UART_Init(void);
+static void MX_RF_Init(void);
+static void MX_RTC_Init(void);
+/* USER CODE BEGIN PFP */
+void PeriphClock_Config(void);
+static void Reset_Device( void );
+static void Reset_IPCC( void );
+static void Reset_BackupDomain( void );
+static void Init_Exti( void );
+static void Config_HSE(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+  
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+  Reset_Device();
+  Config_HSE();
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  PeriphClock_Config();
+  Init_Exti(); /**< Configure the system Power Mode */
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_RF_Init();
+  MX_RTC_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Init code for STM32_WPAN */  
+  APPE_Init();
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+	while(1)
+	{
+		UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure LSE Drive Capability 
+  */
+  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE
+                              |RCC_OSCILLATORTYPE_LSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RFWAKEUP
+                              |RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1
+                              |RCC_PERIPHCLK_LPUART1;
+  PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+  PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* USER CODE BEGIN Smps */
+
+#if (CFG_USE_SMPS != 0)
+  /**
+   *  Configure and enable SMPS
+   *
+   *  The SMPS configuration is not yet supported by CubeMx
+   */
+  LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
+  LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
+  LL_PWR_SMPS_Enable();
+#endif
+
+  /* USER CODE END Smps */
+
+
+}
+
+/**
+  * @brief LPUART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+void MX_LPUART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN LPUART1_Init 0 */
+
+  /* USER CODE END LPUART1_Init 0 */
+
+  /* USER CODE BEGIN LPUART1_Init 1 */
+
+  /* USER CODE END LPUART1_Init 1 */
+  hlpuart1.Instance = LPUART1;
+  hlpuart1.Init.BaudRate = 115200;
+  hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
+  hlpuart1.Init.StopBits = UART_STOPBITS_1;
+  hlpuart1.Init.Parity = UART_PARITY_NONE;
+  hlpuart1.Init.Mode = UART_MODE_TX_RX;
+  hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  hlpuart1.FifoMode = UART_FIFOMODE_DISABLE;
+  if (HAL_UART_Init(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN LPUART1_Init 2 */
+
+  /* USER CODE END LPUART1_Init 2 */
+
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_8;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+  * @brief RF Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RF_Init(void)
+{
+
+  /* USER CODE BEGIN RF_Init 0 */
+
+  /* USER CODE END RF_Init 0 */
+
+  /* USER CODE BEGIN RF_Init 1 */
+
+  /* USER CODE END RF_Init 1 */
+  /* USER CODE BEGIN RF_Init 2 */
+
+  /* USER CODE END RF_Init 2 */
+
+}
+
+/**
+  * @brief RTC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RTC_Init(void)
+{
+
+  /* USER CODE BEGIN RTC_Init 0 */
+
+  /* USER CODE END RTC_Init 0 */
+
+  /* USER CODE BEGIN RTC_Init 1 */
+
+  /* USER CODE END RTC_Init 1 */
+  /** Initialize RTC Only 
+  */
+  hrtc.Instance = RTC;
+  hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
+  hrtc.Init.AsynchPrediv = CFG_RTC_ASYNCH_PRESCALER;
+  hrtc.Init.SynchPrediv = CFG_RTC_SYNCH_PRESCALER;
+  hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
+  hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+  hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+  if (HAL_RTC_Init(&hrtc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN RTC_Init 2 */
+  /* Disable RTC registers write protection */
+  LL_RTC_DisableWriteProtection(RTC);
+
+  LL_RTC_WAKEUP_SetClock(RTC, CFG_RTC_WUCKSEL_DIVIDER);
+
+  /* Enable RTC registers write protection */
+  LL_RTC_EnableWriteProtection(RTC);
+  /* USER CODE END RTC_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
+  __HAL_RCC_DMA2_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
+  /* DMA2_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA2_Channel4_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(DMA2_Channel4_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+void PeriphClock_Config(void)
+{
+  #if (CFG_USB_INTERFACE_ENABLE != 0)
+	RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
+	RCC_CRSInitTypeDef RCC_CRSInitStruct = { 0 };
+
+    /**
+    * This prevents the CPU2 to disable the HSI48 oscillator when
+    * it does not use anymore the RNG IP
+    */
+    LL_HSEM_1StepLock( HSEM, 5 );
+
+    LL_RCC_HSI48_Enable();
+
+	while(!LL_RCC_HSI48_IsReady());
+
+	/* Select HSI48 as USB clock source */
+	PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+	PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+	HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+	/*Configure the clock recovery system (CRS)**********************************/
+
+	/* Enable CRS Clock */
+	__HAL_RCC_CRS_CLK_ENABLE();
+
+	/* Default Synchro Signal division factor (not divided) */
+	RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+
+	/* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+	RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+
+	/* HSI48 is synchronized with USB SOF at 1KHz rate */
+	RCC_CRSInitStruct.ReloadValue = RCC_CRS_RELOADVALUE_DEFAULT;
+	RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+
+	RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+
+	/* Set the TRIM[5:0] to the default value*/
+	RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+
+	/* Start automatic synchronization */
+	HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+#endif
+
+	return;
+}
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+
+static void Config_HSE(void)
+{
+    OTP_ID0_t * p_otp;
+
+  /**
+   * Read HSE_Tuning from OTP
+   */
+  p_otp = (OTP_ID0_t *) OTP_Read(0);
+  if (p_otp)
+  {
+    LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
+  }
+
+  return;
+}  
+
+
+static void Reset_Device( void )
+{
+#if ( CFG_HW_RESET_BY_FW == 1 )
+	Reset_BackupDomain();
+
+	Reset_IPCC();
+#endif
+
+	return;
+}
+
+static void Reset_IPCC( void )
+{
+	LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
+
+	LL_C1_IPCC_ClearFlag_CHx(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_ClearFlag_CHx(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C1_IPCC_DisableTransmitChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_DisableTransmitChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C1_IPCC_DisableReceiveChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_DisableReceiveChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	return;
+}
+
+static void Reset_BackupDomain( void )
+{
+	if ((LL_RCC_IsActiveFlag_PINRST() != FALSE) && (LL_RCC_IsActiveFlag_SFTRST() == FALSE))
+	{
+		HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+		/**
+		 *  Write twice the value to flush the APB-AHB bridge
+		 *  This bit shall be written in the register before writing the next one
+		 */
+		HAL_PWR_EnableBkUpAccess();
+
+		__HAL_RCC_BACKUPRESET_FORCE();
+		__HAL_RCC_BACKUPRESET_RELEASE();
+	}
+
+	return;
+}
+
+static void Init_Exti( void )
+{
+  /**< Disable all wakeup interrupt on CPU1  except IPCC(36), HSEM(38) */
+  LL_EXTI_DisableIT_0_31(~0);
+  LL_EXTI_DisableIT_32_63( (~0) & (~(LL_EXTI_LINE_36 | LL_EXTI_LINE_38)) );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += HAL_GetTickFreq();
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+  {
+    /************************************************************************************
+     * ENTER SLEEP MODE
+     ***********************************************************************************/
+    LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+    /**
+     * This option is used to ensure that store operations are completed
+     */
+  #if defined ( __CC_ARM)
+    __force_stores();
+  #endif
+
+    __WFI( );
+  }
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/stm32_lpm_if.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/stm32_lpm_if.c
new file mode 100644
index 000000000..1418e0a36
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/stm32_lpm_if.c
@@ -0,0 +1,297 @@
+/* USER CODE BEGIN Header */
+/**
+ ***************************************************************************************
+  * File Name          : stm32_lpm_if.c
+  * Description        : Low layer function to enter/exit low power modes (stop, sleep).
+ ***************************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+  
+/* Includes ------------------------------------------------------------------*/  
+#include "stm32_lpm_if.h"
+#include "stm32_lpm.h"
+#include "app_conf.h"
+/* USER CODE BEGIN include */
+
+/* USER CODE END include */
+
+/* Exported variables --------------------------------------------------------*/
+const struct UTIL_LPM_Driver_s UTIL_PowerDriver = 
+{
+  PWR_EnterSleepMode,
+  PWR_ExitSleepMode,
+  
+  PWR_EnterStopMode,
+  PWR_ExitStopMode, 
+  
+  PWR_EnterOffMode,
+  PWR_ExitOffMode,
+};
+
+/* Private function prototypes -----------------------------------------------*/
+static void Switch_On_HSI( void );
+/* USER CODE BEGIN Private_Function_Prototypes */
+
+/* USER CODE END Private_Function_Prototypes */
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN Private_Typedef */
+
+/* USER CODE END Private_Typedef */
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Private_Define */
+
+/* USER CODE END Private_Define */
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Private_Macro */
+
+/* USER CODE END Private_Macro */
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN Private_Variables */
+
+/* USER CODE END Private_Variables */
+
+/* Functions Definition ------------------------------------------------------*/
+/**
+  * @brief Enters Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_EnterOffMode( void )
+{
+/* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
+  /************************************************************************************
+   * ENTER OFF MODE
+   ***********************************************************************************/
+  /*
+   * There is no risk to clear all the WUF here because in the current implementation, this API is called
+   * in critical section. If an interrupt occurs while in that critical section before that point,
+   * the flag is set and will be cleared here but the system will not enter Off Mode
+   * because an interrupt is pending in the NVIC. The ISR will be executed when moving out
+   * of this critical section
+   */
+  LL_PWR_ClearFlag_WU( );
+
+  LL_PWR_SetPowerMode( LL_PWR_MODE_STANDBY );
+
+  LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores( );
+#endif
+
+  __WFI( );
+/* USER CODE END PWR_EnterOffMode */
+}
+
+/**
+  * @brief Exits Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_ExitOffMode( void )
+{
+/* USER CODE BEGIN PWR_ExitOffMode */
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitOffMode */
+}
+
+/**
+  * @brief Enters Low Power Stop Mode
+  * @note ARM exists the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterStopMode( void )
+{
+/* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
+  /**
+   * This function is called from CRITICAL SECTION
+   */
+  while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
+
+  if ( ! LL_HSEM_1StepLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID ) )
+  {
+    if( LL_PWR_IsActiveFlag_C2DS( ) )
+    {
+      /* Release ENTRY_STOP_MODE semaphore */
+      LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
+
+      /**
+       * The switch on HSI before entering Stop Mode is required on Cut2.0
+       * It is useless from Cut2.1
+       */
+      Switch_On_HSI( );
+    }
+  }
+  else
+  {
+    /**
+     * The switch on HSI before entering Stop Mode is required on Cut2.0
+     * It is useless from Cut2.1
+     */
+    Switch_On_HSI( );
+  }
+
+  /* Release RCC semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  /************************************************************************************
+   * ENTER STOP MODE
+   ***********************************************************************************/
+  LL_PWR_SetPowerMode( LL_PWR_MODE_STOP2 );
+
+  LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores( );
+#endif
+
+  __WFI();
+/* USER CODE END PWR_EnterStopMode */
+}
+
+/**
+  * @brief Exits Low Power Stop Mode
+  * @note Enable the pll at 32MHz
+  * @param none
+  * @retval none
+  */
+void PWR_ExitStopMode( void )
+{
+/* USER CODE BEGIN PWR_ExitStopMode */
+  /**
+   * This function is called from CRITICAL SECTION
+   */
+
+  /* Release ENTRY_STOP_MODE semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
+
+  while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
+
+  if(LL_RCC_GetSysClkSource( ) == LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+    LL_RCC_HSE_Enable( );
+    while(!LL_RCC_HSE_IsReady( ));
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
+    while (LL_RCC_GetSysClkSource( ) != LL_RCC_SYS_CLKSOURCE_STATUS_HSE);
+  }
+  else
+  {
+    /**
+     * As long as the current application is fine with HSE as system clock source,
+     * there is nothing to do here
+     */
+  }
+
+  /* Release RCC semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitStopMode */
+}
+
+/**
+  * @brief Enters Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterSleepMode( void )
+{
+/* USER CODE BEGIN PWR_EnterSleepMode */
+
+  HAL_SuspendTick();
+
+  /************************************************************************************
+   * ENTER SLEEP MODE
+   ***********************************************************************************/
+  LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+
+  __WFI( );
+/* USER CODE END PWR_EnterSleepMode */
+}
+
+/**
+  * @brief Exits Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_ExitSleepMode( void )
+{
+/* USER CODE BEGIN PWR_ExitSleepMode */
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitSleepMode */
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+  * @brief Switch the system clock on HSI
+  * @param none
+  * @retval none
+  */
+static void Switch_On_HSI( void )
+{
+  LL_RCC_HSI_Enable( );
+  while(!LL_RCC_HSI_IsReady( ));
+  LL_RCC_SetSysClkSource( LL_RCC_SYS_CLKSOURCE_HSI );
+  LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSI);
+  while (LL_RCC_GetSysClkSource( ) != LL_RCC_SYS_CLKSOURCE_STATUS_HSI);
+}
+
+/* USER CODE BEGIN Private_Functions */
+
+/* USER CODE END Private_Functions */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..f22ad0f38
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,329 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32wbxx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_lpuart1_tx;
+
+extern DMA_HandleTypeDef hdma_usart1_tx;
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_HSEM_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  HAL_DMA_MuxSyncConfigTypeDef pSyncConfig;
+  if(huart->Instance==LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspInit 0 */
+
+  /* USER CODE END LPUART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_LPUART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**LPUART1 GPIO Configuration    
+    PA2     ------> LPUART1_TX
+    PA3     ------> LPUART1_RX
+    PA6     ------> LPUART1_CTS 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* LPUART1 DMA Init */
+    /* LPUART1_TX Init */
+    hdma_lpuart1_tx.Instance = DMA1_Channel4;
+    hdma_lpuart1_tx.Init.Request = DMA_REQUEST_LPUART1_TX;
+    hdma_lpuart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_lpuart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_lpuart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_lpuart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_lpuart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_lpuart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_lpuart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_lpuart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    pSyncConfig.SyncSignalID = HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT;
+    pSyncConfig.SyncPolarity = HAL_DMAMUX_SYNC_NO_EVENT;
+    pSyncConfig.SyncEnable = DISABLE;
+    pSyncConfig.EventEnable = DISABLE;
+    pSyncConfig.RequestNumber = 1;
+    if (HAL_DMAEx_ConfigMuxSync(&hdma_lpuart1_tx, &pSyncConfig) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmatx,hdma_lpuart1_tx);
+
+    /* LPUART1 interrupt Init */
+    HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(LPUART1_IRQn);
+  /* USER CODE BEGIN LPUART1_MspInit 1 */
+
+  /* USER CODE END LPUART1_MspInit 1 */
+  }
+  else if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspInit 0 */
+
+  /* USER CODE END USART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**USART1 GPIO Configuration    
+    PA11     ------> USART1_CTS
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_11;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* USART1 DMA Init */
+    /* USART1_TX Init */
+    hdma_usart1_tx.Instance = DMA2_Channel4;
+    hdma_usart1_tx.Init.Request = DMA_REQUEST_USART1_TX;
+    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx);
+
+    /* USART1 interrupt Init */
+    HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspInit 1 */
+
+  /* USER CODE END USART1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspDeInit 0 */
+
+  /* USER CODE END LPUART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_LPUART1_CLK_DISABLE();
+  
+    /**LPUART1 GPIO Configuration    
+    PA2     ------> LPUART1_TX
+    PA3     ------> LPUART1_RX
+    PA6     ------> LPUART1_CTS 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_6);
+
+    /* LPUART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmatx);
+
+    /* LPUART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(LPUART1_IRQn);
+  /* USER CODE BEGIN LPUART1_MspDeInit 1 */
+
+  /* USER CODE END LPUART1_MspDeInit 1 */
+  }
+  else if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+  /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+  
+    /**USART1 GPIO Configuration    
+    PA11     ------> USART1_CTS
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11);
+
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
+
+    /* USART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmatx);
+
+    /* USART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+  /* USER CODE END USART1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspInit 0 */
+  HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+  /**
+  *  Write twice the value to flush the APB-AHB bridge
+  *  This bit shall be written in the register before writing the next one
+  */
+  HAL_PWR_EnableBkUpAccess();
+
+  __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); /**< Select LSI as RTC Input */
+  /* USER CODE END RTC_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_RTC_ENABLE();
+  /* USER CODE BEGIN RTC_MspInit 1 */
+  HAL_RTCEx_EnableBypassShadow(hrtc);
+  /* USER CODE END RTC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspDeInit 0 */
+
+  /* USER CODE END RTC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RTC_DISABLE();
+  /* USER CODE BEGIN RTC_MspDeInit 1 */
+
+  /* USER CODE END RTC_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..2a345be14
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/stm32wbxx_it.c
@@ -0,0 +1,304 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_lpuart1_tx;
+extern DMA_HandleTypeDef hdma_usart1_tx;
+extern UART_HandleTypeDef hlpuart1;
+extern UART_HandleTypeDef huart1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles DMA1 channel4 global interrupt.
+  */
+void DMA1_Channel4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_lpuart1_tx);
+  /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel4_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+
+  /* USER CODE END USART1_IRQn 0 */
+  HAL_UART_IRQHandler(&huart1);
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles LPUART1 global interrupt.
+  */
+void LPUART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN LPUART1_IRQn 0 */
+
+  /* USER CODE END LPUART1_IRQn 0 */
+  HAL_UART_IRQHandler(&hlpuart1);
+  /* USER CODE BEGIN LPUART1_IRQn 1 */
+
+  /* USER CODE END LPUART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA2 channel4 global interrupt.
+  */
+void DMA2_Channel4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2_Channel4_IRQn 0 */
+
+  /* USER CODE END DMA2_Channel4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart1_tx);
+  /* USER CODE BEGIN DMA2_Channel4_IRQn 1 */
+
+  /* USER CODE END DMA2_Channel4_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW1_EXTI_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW2_EXTI_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW2_PIN);
+}
+
+void RTC_WKUP_IRQHandler(void)
+{
+  HW_TS_RTC_Wakeup_Handler();
+}
+
+void IPCC_C1_TX_IRQHandler(void)
+{
+  HW_IPCC_Tx_Handler();
+
+  return;
+}
+
+void IPCC_C1_RX_IRQHandler(void)
+{
+  HW_IPCC_Rx_Handler();
+  return;
+}
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..156ed20d3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/Core/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                        4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/BLE_p2pServer.ewd b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/BLE_p2pServer.ewd
new file mode 100644
index 000000000..6ce585d63
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/BLE_p2pServer.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		BLE_p2pServer
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/BLE_p2pServer.ewp b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/BLE_p2pServer.ewp
new file mode 100644
index 000000000..db8a1237c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/BLE_p2pServer.ewp
@@ -0,0 +1,1251 @@
+
+
+    3
+    
+        BLE_p2pServer
+        
+            ARM
+        
+        1
+        
+            General
+            3
+            
+                30
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            ICCARM
+            2
+            
+                34
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            AARM
+            2
+            
+                10
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            OBJCOPY
+            0
+            
+                1
+                1
+                1
+                
+                
+                
+                
+                
+            
+        
+        
+            CUSTOM
+            3
+            
+                
+                
+                0
+            
+        
+        
+            BICOMP
+            0
+            
+        
+        
+            BUILDACTION
+            1
+            
+                
+                
+            
+        
+        
+            ILINK
+            0
+            
+                20
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            IARCHIVE
+            0
+            
+                0
+                1
+                1
+                
+                
+                
+            
+        
+        
+            BILINK
+            0
+            
+        
+    
+    
+        Application
+        
+            EWARM
+            
+                $PROJ_DIR$\startup_stm32wb35xx_cm4.s
+            
+        
+        
+            User
+            
+                Core
+                
+                    $PROJ_DIR$\..\Core\Src\app_entry.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\app_debug.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\hw_timerserver.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\hw_uart.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\main.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\stm32_lpm_if.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\stm32wbxx_hal_msp.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\stm32wbxx_it.c
+                
+            
+            
+                STM32_WPAN
+                
+                    App
+                    
+                        $PROJ_DIR$\..\STM32_WPAN\App\app_ble.c
+                    
+                    
+                        $PROJ_DIR$\..\STM32_WPAN\App\p2p_server_app.c
+                    
+                
+                
+                    Target
+                    
+                        $PROJ_DIR$\..\STM32_WPAN\Target\hw_ipcc.c
+                    
+                
+            
+        
+    
+    
+        Doc
+        
+            $PROJ_DIR$\..\readme.txt
+        
+    
+    
+        Drivers
+        
+            BSP
+            
+                NUCLEO-WB35CE
+                
+                    $PROJ_DIR$\..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE\nucleo_wb35ce.c
+                
+            
+        
+        
+            CMSIS
+            
+                $PROJ_DIR$\..\Core\Src\system_stm32wbxx.c
+            
+        
+        
+            STM32WBxx_HAL_Driver
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_cortex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_gpio.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_hsem.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_ipcc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rtc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rtc_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_uart.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_uart_ex.c
+            
+        
+    
+    
+        Middlewares
+        
+            STM32_WPAN
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_gap_aci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_gatt_aci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_hal_aci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_hci_le.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_l2cap_aci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\dbg_trace.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\hci_tl.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\hci_tl_if.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\template\osal.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\otp.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\svc\Src\p2p_stm.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\shci\shci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\shci_tl.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\shci_tl_if.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\stm_list.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\stm_queue.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\svc\Src\svc_ctl.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\tl_mbox.c
+            
+        
+    
+    
+        Utilities
+        
+            $PROJ_DIR$\..\..\..\..\..\..\Utilities\lpm\tiny_lpm\stm32_lpm.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\..\..\Utilities\sequencer\stm32_seq.c
+        
+    
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/Project.eww
new file mode 100644
index 000000000..6485345b5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\BLE_p2pServer.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..8f3317a41
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/app_ble.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/app_ble.c
new file mode 100644
index 000000000..b3c332e8c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/app_ble.c
@@ -0,0 +1,1238 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    app_ble.c
+ * @author  MCD Application Team
+ * @brief   BLE Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+#include "app_common.h"
+
+#include "dbg_trace.h"
+#include "ble.h"
+#include "tl.h"
+#include "app_ble.h"
+
+#include "stm32_seq.h"
+#include "shci.h"
+#include "stm32_lpm.h"
+#include "otp.h"
+#include "p2p_server_app.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+
+/**
+ * security parameters structure
+ */ 
+typedef struct _tSecurityParams
+{
+  /**
+   * IO capability of the device
+   */
+  uint8_t ioCapability;
+
+  /**
+   * Authentication requirement of the device
+   * Man In the Middle protection required?
+   */
+  uint8_t mitm_mode;
+
+  /**
+   * bonding mode of the device
+   */
+  uint8_t bonding_mode;
+
+  /**
+   * Flag to tell whether OOB data has
+   * to be used during the pairing process
+   */
+  uint8_t OOB_Data_Present; 
+
+  /**
+   * OOB data to be used in the pairing process if
+   * OOB_Data_Present is set to TRUE
+   */
+  uint8_t OOB_Data[16]; 
+
+  /**
+   * this variable indicates whether to use a fixed pin
+   * during the pairing process or a passkey has to be
+   * requested to the application during the pairing process
+   * 0 implies use fixed pin and 1 implies request for passkey
+   */
+  uint8_t Use_Fixed_Pin; 
+
+  /**
+   * minimum encryption key size requirement
+   */
+  uint8_t encryptionKeySizeMin;
+
+  /**
+   * maximum encryption key size requirement
+   */
+  uint8_t encryptionKeySizeMax;
+
+  /**
+   * fixed pin to be used in the pairing process if
+   * Use_Fixed_Pin is set to 1
+   */
+  uint32_t Fixed_Pin;
+
+  /**
+   * this flag indicates whether the host has to initiate
+   * the security, wait for pairing or does not have any security
+   * requirements.\n
+   * 0x00 : no security required
+   * 0x01 : host should initiate security by sending the slave security
+   *        request command
+   * 0x02 : host need not send the clave security request but it
+   * has to wait for paiirng to complete before doing any other
+   * processing
+   */
+  uint8_t initiateSecurity;
+}tSecurityParams;
+
+/**
+ * global context
+ * contains the variables common to all 
+ * services
+ */ 
+typedef struct _tBLEProfileGlobalContext
+{
+
+  /**
+   * security requirements of the host
+   */ 
+  tSecurityParams bleSecurityParam;
+
+  /**
+   * gap service handle
+   */
+  uint16_t gapServiceHandle;
+
+  /**
+   * device name characteristic handle
+   */ 
+  uint16_t devNameCharHandle;
+
+  /**
+   * appearance characteristic handle
+   */ 
+  uint16_t appearanceCharHandle;
+
+  /**
+   * connection handle of the current active connection
+   * When not in connection, the handle is set to 0xFFFF
+   */ 
+  uint16_t connectionHandle;
+
+  /**
+   * length of the UUID list to be used while advertising
+   */ 
+  uint8_t advtServUUIDlen;
+
+  /**
+   * the UUID list to be used while advertising
+   */ 
+  uint8_t advtServUUID[100];
+
+}BleGlobalContext_t;
+
+typedef struct
+{
+  BleGlobalContext_t BleApplicationContext_legacy;
+   APP_BLE_ConnStatus_t Device_Connection_Status;
+   /**
+   * ID of the Advertising Timeout
+   */
+   uint8_t Advertising_mgr_timer_Id;
+
+  uint8_t SwitchOffGPIO_timer_Id;
+}BleApplicationContext_t;
+/* USER CODE BEGIN PTD */
+  
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+#define APPBLE_GAP_DEVICE_NAME_LENGTH 7
+#define FAST_ADV_TIMEOUT               (30*1000*1000/CFG_TS_TICK_VAL) /**< 30s */
+#define INITIAL_ADV_TIMEOUT            (60*1000*1000/CFG_TS_TICK_VAL) /**< 60s */
+
+#define BD_ADDR_SIZE_LOCAL    6
+
+/* USER CODE BEGIN PD */
+#define LED_ON_TIMEOUT                 (0.005*1000*1000/CFG_TS_TICK_VAL) /**< 5ms */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static TL_CmdPacket_t BleCmdBuffer;
+
+static const uint8_t M_bd_addr[BD_ADDR_SIZE_LOCAL] =
+    {
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x0000000000FF)),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x00000000FF00) >> 8),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x000000FF0000) >> 16),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x0000FF000000) >> 24),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x00FF00000000) >> 32),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0xFF0000000000) >> 40)
+    };
+
+static uint8_t bd_addr_udn[BD_ADDR_SIZE_LOCAL];
+
+/**
+*   Identity root key used to derive LTK and CSRK 
+*/
+static const uint8_t BLE_CFG_IR_VALUE[16] = CFG_BLE_IRK;
+
+/**
+* Encryption root key used to derive LTK and CSRK
+*/
+static const uint8_t BLE_CFG_ER_VALUE[16] = CFG_BLE_ERK;
+
+/**
+ * These are the two tags used to manage a power failure during OTA
+ * The MagicKeywordAdress shall be mapped @0x140 from start of the binary image
+ * The MagicKeywordvalue is checked in the ble_ota application
+ */
+PLACE_IN_SECTION("TAG_OTA_END") const uint32_t MagicKeywordValue = 0x94448A29 ;
+PLACE_IN_SECTION("TAG_OTA_START") const uint32_t MagicKeywordAddress = (uint32_t)&MagicKeywordValue;
+
+PLACE_IN_SECTION("BLE_APP_CONTEXT") static BleApplicationContext_t BleApplicationContext;
+PLACE_IN_SECTION("BLE_APP_CONTEXT") static uint16_t AdvIntervalMin, AdvIntervalMax;
+
+P2PS_APP_ConnHandle_Not_evt_t handleNotification;
+
+#if L2CAP_REQUEST_NEW_CONN_PARAM != 0
+#define SIZE_TAB_CONN_INT            2
+float tab_conn_interval[SIZE_TAB_CONN_INT] = {50, 1000} ; /* ms */
+uint8_t index_con_int, mutex; 
+#endif 
+
+/**
+ * Advertising Data
+ */
+#if (P2P_SERVER1 != 0)
+static const char local_name[] = { AD_TYPE_COMPLETE_LOCAL_NAME ,'P','2','P','S','R','V','1'};
+uint8_t manuf_data[14] = {
+    sizeof(manuf_data)-1, AD_TYPE_MANUFACTURER_SPECIFIC_DATA, 
+    0x01/*SKD version */,
+    CFG_DEV_ID_P2P_SERVER1 /* STM32WB - P2P Server 1*/,
+    0x00 /* GROUP A Feature  */, 
+    0x00 /* GROUP A Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00, /* BLE MAC start -MSB */
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00, /* BLE MAC stop */
+};
+#endif
+/**
+ * Advertising Data
+ */
+#if (P2P_SERVER2 != 0)
+static const char local_name[] = { AD_TYPE_COMPLETE_LOCAL_NAME, 'P', '2', 'P', 'S', 'R', 'V', '2'};
+uint8_t manuf_data[14] = {
+    sizeof(manuf_data)-1, AD_TYPE_MANUFACTURER_SPECIFIC_DATA, 
+    0x01/*SKD version */,
+    CFG_DEV_ID_P2P_SERVER2 /* STM32WB - P2P Server 2*/,
+    0x00 /* GROUP A Feature  */, 
+    0x00 /* GROUP A Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00, /* BLE MAC start -MSB */
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00, /* BLE MAC stop */
+};
+
+#endif
+
+#if (P2P_SERVER3 != 0)
+static const char local_name[] = { AD_TYPE_COMPLETE_LOCAL_NAME, 'P', '2', 'P', 'S', 'R', 'V', '3'};
+uint8_t manuf_data[14] = {
+    sizeof(manuf_data)-1, AD_TYPE_MANUFACTURER_SPECIFIC_DATA, 
+    0x01/*SKD version */,
+    CFG_DEV_ID_P2P_SERVER3 /* STM32WB - P2P Server 3*/,
+    0x00 /* GROUP A Feature  */, 
+    0x00 /* GROUP A Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00, /* BLE MAC start -MSB */
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00, /* BLE MAC stop */
+};
+#endif
+
+#if (P2P_SERVER4 != 0)
+static const char local_name[] = { AD_TYPE_COMPLETE_LOCAL_NAME, 'P', '2', 'P', 'S', 'R', 'V', '4'};
+uint8_t manuf_data[14] = {
+    sizeof(manuf_data)-1, AD_TYPE_MANUFACTURER_SPECIFIC_DATA, 
+    0x01/*SKD version */,
+    CFG_DEV_ID_P2P_SERVER4 /* STM32WB - P2P Server 4*/,
+    0x00 /* GROUP A Feature  */, 
+    0x00 /* GROUP A Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00, /* BLE MAC start -MSB */
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00, /* BLE MAC stop */
+};
+#endif
+
+#if (P2P_SERVER5 != 0)
+static const char local_name[] = { AD_TYPE_COMPLETE_LOCAL_NAME, 'P', '2', 'P', 'S', 'R', 'V', '5'};
+uint8_t manuf_data[14] = {
+    sizeof(manuf_data)-1, AD_TYPE_MANUFACTURER_SPECIFIC_DATA, 
+    0x01/*SKD version */,
+    CFG_DEV_ID_P2P_SERVER5 /* STM32WB - P2P Server 5*/,
+    0x00 /* GROUP A Feature  */, 
+    0x00 /* GROUP A Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00, /* BLE MAC start -MSB */
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00, /* BLE MAC stop */
+};
+#endif
+
+#if (P2P_SERVER6 != 0)
+static const char local_name[] = { AD_TYPE_COMPLETE_LOCAL_NAME, 'P', '2', 'P', 'S', 'R', 'V', '6'};
+uint8_t manuf_data[14] = {
+    sizeof(manuf_data)-1, AD_TYPE_MANUFACTURER_SPECIFIC_DATA, 
+    0x01/*SKD version */,
+    CFG_DEV_ID_P2P_SERVER6 /* STM32WB - P2P Server 1*/,
+    0x00 /* GROUP A Feature  */, 
+    0x00 /* GROUP A Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00, /* BLE MAC start -MSB */
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00, /* BLE MAC stop */
+};
+#endif
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+static void BLE_UserEvtRx( void * pPayload );
+static void BLE_StatusNot( HCI_TL_CmdStatus_t status );
+static void Ble_Tl_Init( void );
+static void Ble_Hci_Gap_Gatt_Init(void);
+static const uint8_t* BleGetBdAddress( void );
+static void Adv_Request( APP_BLE_ConnStatus_t New_Status );
+static void Adv_Cancel( void );
+static void Adv_Cancel_Req( void );
+static void Switch_OFF_GPIO( void );
+#if(L2CAP_REQUEST_NEW_CONN_PARAM != 0)  
+static void BLE_SVC_L2CAP_Conn_Update(uint16_t Connection_Handle);
+static void Connection_Interval_Update_Req( void );
+#endif
+
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APP_BLE_Init( void )
+{
+/* USER CODE BEGIN APP_BLE_Init_1 */
+
+/* USER CODE END APP_BLE_Init_1 */
+  SHCI_C2_Ble_Init_Cmd_Packet_t ble_init_cmd_packet =
+  {
+    {{0,0,0}},                          /**< Header unused */
+    {0,                                 /** pBleBufferAddress not used */
+    0,                                  /** BleBufferSize not used */
+    CFG_BLE_NUM_GATT_ATTRIBUTES,
+    CFG_BLE_NUM_GATT_SERVICES,
+    CFG_BLE_ATT_VALUE_ARRAY_SIZE,
+    CFG_BLE_NUM_LINK,
+    CFG_BLE_DATA_LENGTH_EXTENSION,
+    CFG_BLE_PREPARE_WRITE_LIST_SIZE,
+    CFG_BLE_MBLOCK_COUNT,
+    CFG_BLE_MAX_ATT_MTU,
+    CFG_BLE_SLAVE_SCA,
+    CFG_BLE_MASTER_SCA,
+    CFG_BLE_LSE_SOURCE,
+    CFG_BLE_MAX_CONN_EVENT_LENGTH,
+    CFG_BLE_HSE_STARTUP_TIME,
+    CFG_BLE_VITERBI_MODE,
+    CFG_BLE_LL_ONLY,
+    0}
+  };
+
+  /**
+   * Initialize Ble Transport Layer
+   */
+  Ble_Tl_Init( );
+
+  /**
+   * Do not allow standby in the application
+   */
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP_BLE, UTIL_LPM_DISABLE);
+
+  /**
+   * Register the hci transport layer to handle BLE User Asynchronous Events
+   */
+  UTIL_SEQ_RegTask( 1<data;
+
+  switch (event_pckt->evt)
+  {
+    case EVT_DISCONN_COMPLETE:
+    {
+      hci_disconnection_complete_event_rp0 *disconnection_complete_event;
+      disconnection_complete_event = (hci_disconnection_complete_event_rp0 *) event_pckt->data;
+
+      if (disconnection_complete_event->Connection_Handle == BleApplicationContext.BleApplicationContext_legacy.connectionHandle)
+      {
+        BleApplicationContext.BleApplicationContext_legacy.connectionHandle = 0;
+        BleApplicationContext.Device_Connection_Status = APP_BLE_IDLE;
+
+        APP_DBG_MSG("\r\n\r** DISCONNECTION EVENT WITH CLIENT \n");
+      }
+
+      /* restart advertising */
+      Adv_Request(APP_BLE_FAST_ADV);
+ /*
+* SPECIFIC to P2P Server APP
+*/     
+      handleNotification.P2P_Evt_Opcode = PEER_DISCON_HANDLE_EVT;
+      handleNotification.ConnectionHandle = BleApplicationContext.BleApplicationContext_legacy.connectionHandle;
+      P2PS_APP_Notification(&handleNotification);
+
+      /* USER CODE BEGIN EVT_DISCONN_COMPLETE */
+
+      /* USER CODE END EVT_DISCONN_COMPLETE */
+    }
+
+    break; /* EVT_DISCONN_COMPLETE */
+
+    case EVT_LE_META_EVENT:
+    {
+      meta_evt = (evt_le_meta_event*) event_pckt->data;
+      /* USER CODE BEGIN EVT_LE_META_EVENT */
+
+      /* USER CODE END EVT_LE_META_EVENT */
+      switch (meta_evt->subevent)
+      {
+        case EVT_LE_CONN_UPDATE_COMPLETE: 
+          APP_DBG_MSG("\r\n\r** CONNECTION UPDATE EVENT WITH CLIENT \n");
+
+          /* USER CODE BEGIN EVT_LE_CONN_UPDATE_COMPLETE */
+
+          /* USER CODE END EVT_LE_CONN_UPDATE_COMPLETE */
+          break;
+        case EVT_LE_PHY_UPDATE_COMPLETE:
+          APP_DBG_MSG("EVT_UPDATE_PHY_COMPLETE \n");
+          evt_le_phy_update_complete = (hci_le_phy_update_complete_event_rp0*)meta_evt->data;
+          if (evt_le_phy_update_complete->Status == 0)
+          {
+            APP_DBG_MSG("EVT_UPDATE_PHY_COMPLETE, status ok \n");
+          }
+          else
+          {
+            APP_DBG_MSG("EVT_UPDATE_PHY_COMPLETE, status nok \n");
+          }
+          ret = hci_le_read_phy(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,&TX_PHY,&RX_PHY);
+          if (ret == BLE_STATUS_SUCCESS)
+          {
+            APP_DBG_MSG("Read_PHY success \n");
+            if ((TX_PHY == TX_2M) && (RX_PHY == RX_2M))
+            {
+              APP_DBG_MSG("PHY Param  TX= %d, RX= %d \n", TX_PHY, RX_PHY);
+            }
+            else
+            {
+              APP_DBG_MSG("PHY Param  TX= %d, RX= %d \n", TX_PHY, RX_PHY);
+            } 
+          }
+          else
+          {
+            APP_DBG_MSG("Read conf not succeess \n");
+          }
+          /* USER CODE BEGIN EVT_LE_PHY_UPDATE_COMPLETE */
+
+          /* USER CODE END EVT_LE_PHY_UPDATE_COMPLETE */          
+          break;
+        case EVT_LE_CONN_COMPLETE:
+        {
+          hci_le_connection_complete_event_rp0 *connection_complete_event;
+
+          /**
+           * The connection is done, there is no need anymore to schedule the LP ADV
+           */
+          connection_complete_event = (hci_le_connection_complete_event_rp0 *) meta_evt->data;
+
+          HW_TS_Stop(BleApplicationContext.Advertising_mgr_timer_Id);
+
+          APP_DBG_MSG("EVT_LE_CONN_COMPLETE for connection handle 0x%x\n", connection_complete_event->Connection_Handle);
+          if (BleApplicationContext.Device_Connection_Status == APP_BLE_LP_CONNECTING)
+          {
+            /* Connection as client */
+            BleApplicationContext.Device_Connection_Status = APP_BLE_CONNECTED_CLIENT;
+          }
+          else
+          {
+            /* Connection as server */
+            BleApplicationContext.Device_Connection_Status = APP_BLE_CONNECTED_SERVER;
+          }
+          BleApplicationContext.BleApplicationContext_legacy.connectionHandle = connection_complete_event->Connection_Handle;
+ /*
+* SPECIFIC to P2P Server APP
+*/             
+          handleNotification.P2P_Evt_Opcode = PEER_CONN_HANDLE_EVT;
+          handleNotification.ConnectionHandle = BleApplicationContext.BleApplicationContext_legacy.connectionHandle;
+          P2PS_APP_Notification(&handleNotification);
+          /* USER CODE BEGIN HCI_EVT_LE_CONN_COMPLETE */
+ /*
+* SPECIFIC to P2P Server APP
+*/             
+          handleNotification.P2P_Evt_Opcode = PEER_CONN_HANDLE_EVT;
+          handleNotification.ConnectionHandle = BleApplicationContext.BleApplicationContext_legacy.connectionHandle;
+          P2PS_APP_Notification(&handleNotification);
+/**/
+          /* USER CODE END HCI_EVT_LE_CONN_COMPLETE */
+        }
+        break; /* HCI_EVT_LE_CONN_COMPLETE */
+
+        default:
+          /* USER CODE BEGIN SUBEVENT_DEFAULT */
+
+          /* USER CODE END SUBEVENT_DEFAULT */
+          break;
+      }
+    }
+    break; /* HCI_EVT_LE_META_EVENT */
+
+    case EVT_VENDOR:
+      blue_evt = (evt_blue_aci*) event_pckt->data;
+      /* USER CODE BEGIN EVT_VENDOR */
+
+      /* USER CODE END EVT_VENDOR */
+      switch (blue_evt->ecode)
+      {
+      /* USER CODE BEGIN ecode */
+        aci_gap_pairing_complete_event_rp0 *pairing_complete;
+
+      case EVT_BLUE_GAP_LIMITED_DISCOVERABLE: 
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_LIMITED_DISCOVERABLE \n");
+          break; /* EVT_BLUE_GAP_LIMITED_DISCOVERABLE */
+      case EVT_BLUE_GAP_PASS_KEY_REQUEST:  
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_PASS_KEY_REQUEST \n");
+/*
+        aci_gap_pass_key_resp(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,123456);
+*/
+        APP_DBG_MSG("\r\n\r** aci_gap_pass_key_resp \n");
+          break; /* EVT_BLUE_GAP_PASS_KEY_REQUEST */
+      case EVT_BLUE_GAP_AUTHORIZATION_REQUEST:    
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_AUTHORIZATION_REQUEST \n");
+          break; /* EVT_BLUE_GAP_AUTHORIZATION_REQUEST */
+      case EVT_BLUE_GAP_SLAVE_SECURITY_INITIATED:   
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_SLAVE_SECURITY_INITIATED \n");
+          break; /* EVT_BLUE_GAP_SLAVE_SECURITY_INITIATED */
+      case EVT_BLUE_GAP_BOND_LOST:    
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_BOND_LOST \n");
+          aci_gap_allow_rebond(BleApplicationContext.BleApplicationContext_legacy.connectionHandle);
+        APP_DBG_MSG("\r\n\r** Send allow rebond \n");
+          break; /* EVT_BLUE_GAP_BOND_LOST */
+      case EVT_BLUE_GAP_DEVICE_FOUND:  
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_DEVICE_FOUND \n");
+          break; /* EVT_BLUE_GAP_DEVICE_FOUND */
+      case EVT_BLUE_GAP_ADDR_NOT_RESOLVED:
+         APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_DEVICE_FOUND \n");
+          break; /* EVT_BLUE_GAP_DEVICE_FOUND */
+      case (EVT_BLUE_GAP_KEYPRESS_NOTIFICATION):
+         APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_KEYPRESS_NOTIFICATION \n");
+          break; /* EVT_BLUE_GAP_KEY_PRESS_NOTIFICATION */    
+       case (EVT_BLUE_GAP_NUMERIC_COMPARISON_VALUE):
+          APP_DBG_MSG("numeric_value = %ld\n",
+                      ((aci_gap_numeric_comparison_value_event_rp0 *)(blue_evt->data))->Numeric_Value);
+
+          APP_DBG_MSG("Hex_value = %lx\n",
+                      ((aci_gap_numeric_comparison_value_event_rp0 *)(blue_evt->data))->Numeric_Value);
+
+          aci_gap_numeric_comparison_value_confirm_yesno(BleApplicationContext.BleApplicationContext_legacy.connectionHandle, 1); /* CONFIRM_YES = 1 */
+
+          APP_DBG_MSG("\r\n\r** aci_gap_numeric_comparison_value_confirm_yesno-->YES \n");
+      break;
+          case (EVT_BLUE_GAP_PAIRING_CMPLT):
+          {
+            pairing_complete = (aci_gap_pairing_complete_event_rp0*)blue_evt->data;
+            APP_DBG_MSG("BLE_CTRL_App_Notification: EVT_BLUE_GAP_PAIRING_CMPLT, pairing_complete->Status = %d\n",pairing_complete->Status);
+            if (pairing_complete->Status == 0)
+            {
+              APP_DBG_MSG("\r\n\r** Pairing OK \n");
+            }
+            else
+            {
+              APP_DBG_MSG("\r\n\r** Pairing KO \n");
+            }
+          }
+           break;    
+      /* USER CODE END ecode */
+/*
+* SPECIFIC to P2P Server APP
+*/
+        case EVT_BLUE_L2CAP_CONNECTION_UPDATE_RESP:
+#if (L2CAP_REQUEST_NEW_CONN_PARAM != 0 )
+          mutex = 1;
+#endif
+      /* USER CODE BEGIN EVT_BLUE_L2CAP_CONNECTION_UPDATE_RESP */
+
+      /* USER CODE END EVT_BLUE_L2CAP_CONNECTION_UPDATE_RESP */
+      break;
+        case EVT_BLUE_GAP_PROCEDURE_COMPLETE:
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_PROCEDURE_COMPLETE \n");
+        /* USER CODE BEGIN EVT_BLUE_GAP_PROCEDURE_COMPLETE */
+
+        /* USER CODE END EVT_BLUE_GAP_PROCEDURE_COMPLETE */
+          break; /* EVT_BLUE_GAP_PROCEDURE_COMPLETE */
+#if(RADIO_ACTIVITY_EVENT != 0)
+        case ACI_HAL_END_OF_RADIO_ACTIVITY_VSEVT_CODE:
+        /* USER CODE BEGIN RADIO_ACTIVITY_EVENT*/
+          BSP_LED_On(LED_GREEN);
+          HW_TS_Start(BleApplicationContext.SwitchOffGPIO_timer_Id, (uint32_t)LED_ON_TIMEOUT);
+        /* USER CODE END RADIO_ACTIVITY_EVENT*/
+          break; /* RADIO_ACTIVITY_EVENT */
+#endif
+      }
+      break; /* EVT_VENDOR */
+
+      default:
+      /* USER CODE BEGIN ECODE_DEFAULT*/
+
+      /* USER CODE END ECODE_DEFAULT*/
+        break;
+  }
+
+  return (SVCCTL_UserEvtFlowEnable);
+}
+
+APP_BLE_ConnStatus_t APP_BLE_Get_Server_Connection_Status(void)
+{
+    return BleApplicationContext.Device_Connection_Status;
+}
+
+/* USER CODE BEGIN FD*/
+void APP_BLE_Key_Button1_Action(void)
+{
+  P2PS_APP_SW1_Button_Action();
+}
+
+void APP_BLE_Key_Button2_Action(void)
+{
+#if (L2CAP_REQUEST_NEW_CONN_PARAM != 0 )    
+  UTIL_SEQ_SetTask( 1< 0)
+  {
+    const char *name = "P2PSRV1";
+    aci_gap_init(role, 0,
+                 APPBLE_GAP_DEVICE_NAME_LENGTH,
+                 &gap_service_handle, &gap_dev_name_char_handle, &gap_appearance_char_handle);
+
+    if (aci_gatt_update_char_value(gap_service_handle, gap_dev_name_char_handle, 0, strlen(name), (uint8_t *) name))
+    {
+      BLE_DBG_SVCCTL_MSG("Device Name aci_gatt_update_char_value failed.\n");
+    }
+  }
+
+  if(aci_gatt_update_char_value(gap_service_handle,
+                                gap_appearance_char_handle,
+                                0,
+                                2,
+                                (uint8_t *)&appearance))
+  {
+    BLE_DBG_SVCCTL_MSG("Appearance aci_gatt_update_char_value failed.\n");
+  }
+/**
+   * Initialize Default PHY
+   */
+  hci_le_set_default_phy(ALL_PHYS_PREFERENCE,TX_2M_PREFERRED,RX_2M_PREFERRED); 
+
+  /**
+   * Initialize IO capability
+   */
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.ioCapability = CFG_IO_CAPABILITY;
+  aci_gap_set_io_capability(BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.ioCapability);
+
+  /**
+   * Initialize authentication
+   */
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode = CFG_MITM_PROTECTION;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data_Present = 0;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin = 8;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax = 16;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin = 1;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin = 111111;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode = 1;
+  for (index = 0; index < 16; index++)
+  {
+    BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data[index] = (uint8_t) index;
+  }
+
+  aci_gap_set_authentication_requirement(BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode,
+                                         1,
+                                         0,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin,
+                                         0
+                                        );
+
+  /**
+   * Initialize whitelist
+   */
+   if (BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode)
+   {
+     aci_gap_configure_whitelist();
+   }
+}
+
+static void Adv_Request(APP_BLE_ConnStatus_t New_Status)
+{
+  tBleStatus ret = BLE_STATUS_INVALID_PARAMS;
+  uint16_t Min_Inter, Max_Inter;
+
+  if (New_Status == APP_BLE_FAST_ADV)
+  {
+    Min_Inter = AdvIntervalMin;
+    Max_Inter = AdvIntervalMax;
+  }
+  else
+  {
+    Min_Inter = CFG_LP_CONN_ADV_INTERVAL_MIN;
+    Max_Inter = CFG_LP_CONN_ADV_INTERVAL_MAX;
+  }
+
+    /**
+     * Stop the timer, it will be restarted for a new shot
+     * It does not hurt if the timer was not running
+     */
+    HW_TS_Stop(BleApplicationContext.Advertising_mgr_timer_Id);
+
+    APP_DBG_MSG("First index in %d state \n", BleApplicationContext.Device_Connection_Status);
+    if ((New_Status == APP_BLE_LP_ADV)
+        && ((BleApplicationContext.Device_Connection_Status == APP_BLE_FAST_ADV)
+            || (BleApplicationContext.Device_Connection_Status == APP_BLE_LP_ADV)))
+    {
+      /* Connection in ADVERTISE mode have to stop the current advertising */
+      ret = aci_gap_set_non_discoverable();
+      if (ret == BLE_STATUS_SUCCESS)
+      {
+        APP_DBG_MSG("Successfully Stopped Advertising \n");
+      }
+      else
+      {
+        APP_DBG_MSG("Stop Advertising Failed , result: %d \n", ret);
+      }
+    }
+
+    BleApplicationContext.Device_Connection_Status = New_Status;
+    /* Start Fast or Low Power Advertising */
+    ret = aci_gap_set_discoverable(
+        ADV_IND,
+        Min_Inter,
+        Max_Inter,
+        PUBLIC_ADDR,
+        NO_WHITE_LIST_USE, /* use white list */
+        sizeof(local_name),
+        (uint8_t*) &local_name,
+        BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen,
+        BleApplicationContext.BleApplicationContext_legacy.advtServUUID,
+        0,
+        0);
+    /* Update Advertising data */
+    ret = aci_gap_update_adv_data(sizeof(manuf_data), (uint8_t*) manuf_data);
+
+    if (ret == BLE_STATUS_SUCCESS)
+    {
+      if (New_Status == APP_BLE_FAST_ADV)
+      {
+        APP_DBG_MSG("Successfully Start Fast Advertising \n" );
+        /* Start Timer to STOP ADV - TIMEOUT */
+        HW_TS_Start(BleApplicationContext.Advertising_mgr_timer_Id, INITIAL_ADV_TIMEOUT);
+      }
+      else
+      {
+        APP_DBG_MSG("Successfully Start Low Power Advertising \n");
+      }
+    }
+    else
+    {
+      if (New_Status == APP_BLE_FAST_ADV)
+      {
+        APP_DBG_MSG("Start Fast Advertising Failed , result: %d \n", ret);
+      }
+      else
+      {
+        APP_DBG_MSG("Start Low Power Advertising Failed , result: %d \n", ret);
+      }
+    }
+
+  return;
+}
+
+const uint8_t* BleGetBdAddress( void )
+{
+  uint8_t *otp_addr;
+  const uint8_t *bd_addr;
+  uint32_t udn;
+  uint32_t company_id;
+  uint32_t device_id;
+
+  udn = LL_FLASH_GetUDN();
+
+  if(udn != 0xFFFFFFFF)
+  {
+    company_id = LL_FLASH_GetSTCompanyID();
+    device_id = LL_FLASH_GetDeviceID();
+
+    bd_addr_udn[0] = (uint8_t)(udn & 0x000000FF);
+    bd_addr_udn[1] = (uint8_t)( (udn & 0x0000FF00) >> 8 );
+    bd_addr_udn[2] = (uint8_t)( (udn & 0x00FF0000) >> 16 );
+    bd_addr_udn[3] = (uint8_t)device_id;
+    bd_addr_udn[4] = (uint8_t)(company_id & 0x000000FF);;
+    bd_addr_udn[5] = (uint8_t)( (company_id & 0x0000FF00) >> 8 );
+
+    bd_addr = (const uint8_t *)bd_addr_udn;
+  }
+  else
+  {
+    otp_addr = OTP_Read(0);
+    if(otp_addr)
+    {
+      bd_addr = ((OTP_ID0_t*)otp_addr)->bd_address;
+    }
+    else
+    {
+      bd_addr = M_bd_addr;
+    }
+
+  }
+
+  return bd_addr;
+}
+
+/* USER CODE BEGIN FD_LOCAL_FUNCTION */
+
+/* USER CODE END FD_LOCAL_FUNCTION */
+
+/*************************************************************
+ *
+ *SPECIFIC FUNCTIONS FOR P2P SERVER
+ *
+ *************************************************************/
+static void Adv_Cancel( void )
+{
+/* USER CODE BEGIN Adv_Cancel_1 */
+  BSP_LED_Off(LED_GREEN);
+/* USER CODE END Adv_Cancel_1 */
+
+  if (BleApplicationContext.Device_Connection_Status != APP_BLE_CONNECTED_SERVER)
+
+  {
+
+    tBleStatus result = 0x00;
+
+    result = aci_gap_set_non_discoverable();
+
+    BleApplicationContext.Device_Connection_Status = APP_BLE_IDLE;
+    if (result == BLE_STATUS_SUCCESS)
+    {
+      APP_DBG_MSG("  \r\n\r");APP_DBG_MSG("** STOP ADVERTISING **  \r\n\r");
+    }
+    else
+    {
+      APP_DBG_MSG("** STOP ADVERTISING **  Failed \r\n\r");
+    }
+
+  }
+
+/* USER CODE BEGIN Adv_Cancel_2 */
+
+/* USER CODE END Adv_Cancel_2 */
+  return;
+}
+
+static void Adv_Cancel_Req( void )
+{
+/* USER CODE BEGIN Adv_Cancel_Req_1 */
+
+/* USER CODE END Adv_Cancel_Req_1 */
+  UTIL_SEQ_SetTask(1 << CFG_TASK_ADV_CANCEL_ID, CFG_SCH_PRIO_0);
+/* USER CODE BEGIN Adv_Cancel_Req_2 */
+
+/* USER CODE END Adv_Cancel_Req_2 */
+  return;
+}
+
+static void Switch_OFF_GPIO(){
+/* USER CODE BEGIN Switch_OFF_GPIO */
+  BSP_LED_Off(LED_GREEN);
+/* USER CODE END Switch_OFF_GPIO */
+}
+
+#if(L2CAP_REQUEST_NEW_CONN_PARAM != 0)  
+void BLE_SVC_L2CAP_Conn_Update(uint16_t Connection_Handle)
+{
+/* USER CODE BEGIN BLE_SVC_L2CAP_Conn_Update_1 */
+
+/* USER CODE END BLE_SVC_L2CAP_Conn_Update_1 */
+  if(mutex == 1) { 
+    mutex = 0;
+    index_con_int = (index_con_int + 1)%SIZE_TAB_CONN_INT;
+    uint16_t interval_min = CONN_P(tab_conn_interval[index_con_int]);
+    uint16_t interval_max = CONN_P(tab_conn_interval[index_con_int]);
+    uint16_t slave_latency = L2CAP_SLAVE_LATENCY;
+    uint16_t timeout_multiplier = L2CAP_TIMEOUT_MULTIPLIER;
+    tBleStatus result;
+
+    result = aci_l2cap_connection_parameter_update_req(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,
+                                                       interval_min, interval_max,
+                                                       slave_latency, timeout_multiplier);
+    if( result == BLE_STATUS_SUCCESS )
+    {
+      APP_DBG_MSG("BLE_SVC_L2CAP_Conn_Update(), Successfully \r\n\r");
+    }
+    else
+    {
+      APP_DBG_MSG("BLE_SVC_L2CAP_Conn_Update(), Failed \r\n\r");
+    }
+  }
+/* USER CODE BEGIN BLE_SVC_L2CAP_Conn_Update_2 */
+
+/* USER CODE END BLE_SVC_L2CAP_Conn_Update_2 */
+  return;
+}
+#endif
+
+#if (L2CAP_REQUEST_NEW_CONN_PARAM != 0 )    
+static void Connection_Interval_Update_Req( void )
+{
+  if (BleApplicationContext.Device_Connection_Status != APP_BLE_FAST_ADV && BleApplicationContext.Device_Connection_Status != APP_BLE_IDLE)
+  {
+    BLE_SVC_L2CAP_Conn_Update(BleApplicationContext.BleApplicationContext_legacy.connectionHandle);
+  }
+  return;
+}
+#endif    
+/* USER CODE BEGIN FD_SPECIFIC_FUNCTIONS */
+
+/* USER CODE END FD_SPECIFIC_FUNCTIONS */
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+void hci_notify_asynch_evt(void* pdata)
+{
+  UTIL_SEQ_SetTask(1 << CFG_TASK_HCI_ASYNCH_EVT_ID, CFG_SCH_PRIO_0);
+  return;
+}
+
+void hci_cmd_resp_release(uint32_t flag)
+{
+  UTIL_SEQ_SetEvt(1 << CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID);
+  return;
+}
+
+void hci_cmd_resp_wait(uint32_t timeout)
+{
+  UTIL_SEQ_WaitEvt(1 << CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID);
+  return;
+}
+
+static void BLE_UserEvtRx( void * pPayload )
+{
+  SVCCTL_UserEvtFlowStatus_t svctl_return_status;
+  tHCI_UserEvtRxParam *pParam;
+
+  pParam = (tHCI_UserEvtRxParam *)pPayload; 
+
+  svctl_return_status = SVCCTL_UserEvtRx((void *)&(pParam->pckt->evtserial));
+  if (svctl_return_status != SVCCTL_UserEvtFlowDisable)
+  {
+    pParam->status = HCI_TL_UserEventFlow_Enable;
+  }
+  else
+  {
+    pParam->status = HCI_TL_UserEventFlow_Disable;
+  }
+}
+
+static void BLE_StatusNot( HCI_TL_CmdStatus_t status )
+{
+  uint32_t task_id_list;
+  switch (status)
+  {
+    case HCI_TL_CmdBusy:
+      /**
+       * All tasks that may send an aci/hci commands shall be listed here
+       * This is to prevent a new command is sent while one is already pending
+       */
+      task_id_list = (1 << CFG_LAST_TASK_ID_WITH_HCICMD) - 1;
+      UTIL_SEQ_PauseTask(task_id_list);
+
+      break;
+
+    case HCI_TL_CmdAvailable:
+      /**
+       * All tasks that may send an aci/hci commands shall be listed here
+       * This is to prevent a new command is sent while one is already pending
+       */
+      task_id_list = (1 << CFG_LAST_TASK_ID_WITH_HCICMD) - 1;
+      UTIL_SEQ_ResumeTask(task_id_list);
+
+      break;
+
+    default:
+      break;
+  }
+  return;
+}
+
+void SVCCTL_ResumeUserEventFlow( void )
+{
+  hci_resume_flow();
+  return;
+}
+
+/* USER CODE BEGIN FD_WRAP_FUNCTIONS */
+
+/* USER CODE END FD_WRAP_FUNCTIONS */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/app_ble.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/app_ble.h
new file mode 100644
index 000000000..657ba432b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/app_ble.h
@@ -0,0 +1,88 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    app_ble.h
+  * @author  MCD Application Team
+  * @brief   Header for ble application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_BLE_H
+#define APP_BLE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "hci_tl.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+
+    typedef enum
+    {
+      APP_BLE_IDLE,
+      APP_BLE_FAST_ADV,
+      APP_BLE_LP_ADV,
+      APP_BLE_SCAN,
+      APP_BLE_LP_CONNECTING,
+      APP_BLE_CONNECTED_SERVER,
+      APP_BLE_CONNECTED_CLIENT
+    } APP_BLE_ConnStatus_t;
+    
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */  
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APP_BLE_Init( void ); 
+
+  APP_BLE_ConnStatus_t APP_BLE_Get_Server_Connection_Status(void);
+
+/* USER CODE BEGIN EF */
+void APP_BLE_Key_Button1_Action(void);
+void APP_BLE_Key_Button2_Action(void);
+void APP_BLE_Key_Button3_Action(void);
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*APP_BLE_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/ble_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/ble_conf.h
new file mode 100644
index 000000000..538713f85
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/ble_conf.h
@@ -0,0 +1,70 @@
+/**
+ ******************************************************************************
+  * File Name          : App/ble_conf.h
+  * Description        : Configuration file for BLE Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef BLE_CONF_H
+#define BLE_CONF_H
+
+#include "app_conf.h"
+
+/******************************************************************************
+ *
+ * BLE SERVICES CONFIGURATION
+ * blesvc
+ *
+ ******************************************************************************/
+
+ /**
+ * This setting shall be set to '1' if the device needs to support the Peripheral Role
+ * In the MS configuration, both BLE_CFG_PERIPHERAL and BLE_CFG_CENTRAL shall be set to '1'
+ */
+#define BLE_CFG_PERIPHERAL                                                     1
+
+/**
+ * This setting shall be set to '1' if the device needs to support the Central Role
+ * In the MS configuration, both BLE_CFG_PERIPHERAL and BLE_CFG_CENTRAL shall be set to '1'
+ */
+#define BLE_CFG_CENTRAL                                                        0
+
+/**
+ * There is one handler per service enabled
+ * Note: There is no handler for the Device Information Service
+ *
+ * This shall take into account all registered handlers
+ * (from either the provided services or the custom services)
+ */
+#define BLE_CFG_SVC_MAX_NBR_CB                                                 1
+
+#define BLE_CFG_CLT_MAX_NBR_CB                                                 0
+
+/******************************************************************************
+ * GAP Service - Apprearance
+ ******************************************************************************/
+
+#define BLE_CFG_UNKNOWN_APPEARANCE                  (0)
+#define BLE_CFG_HR_SENSOR_APPEARANCE                (832)
+#define BLE_CFG_GAP_APPEARANCE                      (BLE_CFG_UNKNOWN_APPEARANCE)
+
+/******************************************************************************
+ * Over The Air Feature (OTA) - STM Proprietary
+ ******************************************************************************/
+#define BLE_CFG_OTA_REBOOT_CHAR         0/**< REBOOT OTA MODE CHARACTERISTIC */
+
+#endif /*BLE_CONF_H */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/ble_dbg_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/ble_dbg_conf.h
new file mode 100644
index 000000000..bec936bbe
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/ble_dbg_conf.h
@@ -0,0 +1,199 @@
+/**
+ ******************************************************************************
+  * File Name          : App/ble_dbg_conf.h
+  * Description        : Debug configuration file for BLE Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __BLE_DBG_CONF_H
+#define __BLE_DBG_CONF_H
+
+/**
+ * Enable or Disable traces from BLE
+ */
+
+#define BLE_DBG_APP_EN             0
+#define BLE_DBG_DIS_EN             0
+#define BLE_DBG_HRS_EN             0
+#define BLE_DBG_SVCCTL_EN          0
+#define BLE_DBG_BLS_EN             0
+#define BLE_DBG_HTS_EN             0
+#define BLE_DBG_P2P_STM_EN         1
+
+/**
+ * Macro definition
+ */
+#if ( BLE_DBG_APP_EN != 0 )
+#define BLE_DBG_APP_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_APP_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_DIS_EN != 0 )
+#define BLE_DBG_DIS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_DIS_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_HRS_EN != 0 )
+#define BLE_DBG_HRS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HRS_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_P2P_STM_EN != 0 )
+#define BLE_DBG_P2P_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_P2P_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_TEMPLATE_STM_EN != 0 )
+#define BLE_DBG_TEMPLATE_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_TEMPLATE_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_EDS_STM_EN != 0 )
+#define BLE_DBG_EDS_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_EDS_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_LBS_STM_EN != 0 )
+#define BLE_DBG_LBS_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_LBS_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_SVCCTL_EN != 0 )
+#define BLE_DBG_SVCCTL_MSG          PRINT_MESG_DBG
+#else
+#define BLE_DBG_SVCCTL_MSG          PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_CTS_EN != 0)
+#define BLE_DBG_CTS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_CTS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HIDS_EN != 0)
+#define BLE_DBG_HIDS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_HIDS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_PASS_EN != 0)
+#define BLE_DBG_PASS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_PASS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_BLS_EN != 0)
+#define BLE_DBG_BLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_BLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HTS_EN != 0)
+#define BLE_DBG_HTS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HTS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_ANS_EN != 0)
+#define BLE_DBG_ANS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_ANS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_ESS_EN != 0)
+#define BLE_DBG_ESS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_ESS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_GLS_EN != 0)
+#define BLE_DBG_GLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_GLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_BAS_EN != 0)
+#define BLE_DBG_BAS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_BAS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_RTUS_EN != 0)
+#define BLE_DBG_RTUS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_RTUS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HPS_EN != 0)
+#define BLE_DBG_HPS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HPS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_TPS_EN != 0)
+#define BLE_DBG_TPS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_TPS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_LLS_EN != 0)
+#define BLE_DBG_LLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_LLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_IAS_EN != 0)
+#define BLE_DBG_IAS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_IAS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_WSS_EN != 0)
+#define BLE_DBG_WSS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_WSS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_LNS_EN != 0)
+#define BLE_DBG_LNS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_LNS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_SCPS_EN != 0)
+#define BLE_DBG_SCPS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_SCPS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_DTS_EN != 0)
+#define BLE_DBG_DTS_MSG             PRINT_MESG_DBG
+#define BLE_DBG_DTS_BUF             PRINT_LOG_BUFF_DBG
+#else
+#define BLE_DBG_DTS_MSG             PRINT_NO_MESG
+#define BLE_DBG_DTS_BUF             PRINT_NO_MESG
+#endif
+
+#endif /*__BLE_DBG_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/p2p_server_app.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/p2p_server_app.c
new file mode 100644
index 000000000..5c95b3afe
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/App/p2p_server_app.c
@@ -0,0 +1,389 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    p2p_server_app.c
+ * @author  MCD Application Team
+ * @brief   peer to peer Server Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "app_common.h"
+#include "dbg_trace.h"
+#include "ble.h"
+#include "p2p_server_app.h"
+#include "stm32_seq.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+ typedef struct{
+    uint8_t             Device_Led_Selection;
+    uint8_t             Led1;
+ }P2P_LedCharValue_t;
+
+ typedef struct{
+    uint8_t             Device_Button_Selection;
+    uint8_t             ButtonStatus;
+ }P2P_ButtonCharValue_t;
+
+typedef struct
+{
+  uint8_t               Notification_Status; /* used to chek if P2P Server is enabled to Notify */
+  P2P_LedCharValue_t    LedControl;
+  P2P_ButtonCharValue_t ButtonControl;
+  uint16_t              ConnectionHandle;
+} P2P_Server_App_Context_t;
+/* USER CODE END PTD */
+
+/* Private defines ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+/**
+ * START of Section BLE_APP_CONTEXT
+ */
+
+PLACE_IN_SECTION("BLE_APP_CONTEXT") static P2P_Server_App_Context_t P2P_Server_App_Context;
+
+/**
+ * END of Section BLE_APP_CONTEXT
+ */
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+static void P2PS_Send_Notification(void);
+static void P2PS_APP_LED_BUTTON_context_Init(void);
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void P2PS_STM_App_Notification(P2PS_STM_App_Notification_evt_t *pNotification)
+{
+/* USER CODE BEGIN P2PS_STM_App_Notification_1 */
+
+/* USER CODE END P2PS_STM_App_Notification_1 */
+  switch(pNotification->P2P_Evt_Opcode)
+  {
+/* USER CODE BEGIN P2PS_STM_App_Notification_P2P_Evt_Opcode */
+#if(BLE_CFG_OTA_REBOOT_CHAR != 0)
+    case P2PS_STM_BOOT_REQUEST_EVT:
+      APP_DBG_MSG("-- P2P APPLICATION SERVER : BOOT REQUESTED\n");
+      APP_DBG_MSG(" \n\r");
+
+      *(uint32_t*)SRAM1_BASE = *(uint32_t*)pNotification->DataTransfered.pPayload;
+      NVIC_SystemReset();
+      break;
+#endif
+/* USER CODE END P2PS_STM_App_Notification_P2P_Evt_Opcode */
+
+    case P2PS_STM__NOTIFY_ENABLED_EVT:
+/* USER CODE BEGIN P2PS_STM__NOTIFY_ENABLED_EVT */
+      P2P_Server_App_Context.Notification_Status = 1;
+      APP_DBG_MSG("-- P2P APPLICATION SERVER : NOTIFICATION ENABLED\n"); 
+      APP_DBG_MSG(" \n\r");
+/* USER CODE END P2PS_STM__NOTIFY_ENABLED_EVT */
+      break;
+
+    case P2PS_STM_NOTIFY_DISABLED_EVT:
+/* USER CODE BEGIN P2PS_STM_NOTIFY_DISABLED_EVT */
+      P2P_Server_App_Context.Notification_Status = 0;
+      APP_DBG_MSG("-- P2P APPLICATION SERVER : NOTIFICATION DISABLED\n");
+      APP_DBG_MSG(" \n\r");
+/* USER CODE END P2PS_STM_NOTIFY_DISABLED_EVT */
+      break;
+      
+    case P2PS_STM_WRITE_EVT:
+/* USER CODE BEGIN P2PS_STM_WRITE_EVT */
+      if(pNotification->DataTransfered.pPayload[0] == 0x00){ /* ALL Deviceselected - may be necessary as LB Routeur informs all connection */
+        if(pNotification->DataTransfered.pPayload[1] == 0x01)
+        {
+          BSP_LED_On(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER  : LED1 ON\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x01; /* LED1 ON */
+        }
+        if(pNotification->DataTransfered.pPayload[1] == 0x00)
+        {
+          BSP_LED_Off(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER  : LED1 OFF\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x00; /* LED1 OFF */
+        }
+      }
+#if(P2P_SERVER1 != 0)  
+      if(pNotification->DataTransfered.pPayload[0] == 0x01){ /* end device 1 selected - may be necessary as LB Routeur informs all connection */
+        if(pNotification->DataTransfered.pPayload[1] == 0x01)
+        {
+          BSP_LED_On(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER 1 : LED1 ON\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x01; /* LED1 ON */
+        }
+        if(pNotification->DataTransfered.pPayload[1] == 0x00)
+        {
+          BSP_LED_Off(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER 1 : LED1 OFF\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x00; /* LED1 OFF */
+        }
+      }
+#endif
+#if(P2P_SERVER2 != 0)
+      if(pNotification->DataTransfered.pPayload[0] == 0x02){ /* end device 2 selected */ 
+        if(pNotification->DataTransfered.pPayload[1] == 0x01)
+        {
+          BSP_LED_On(LED_BLUE);
+           APP_DBG_MSG("-- P2P APPLICATION SERVER 2 : LED1 ON\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x01; /* LED1 ON */
+        }
+        if(pNotification->DataTransfered.pPayload[1] == 0x00)
+        {
+          BSP_LED_Off(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER 2 : LED1 OFF\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x00; /* LED1 OFF */
+        }   
+      }
+#endif      
+#if(P2P_SERVER3 != 0)  
+      if(pNotification->DataTransfered.pPayload[0] == 0x03){ /* end device 3 selected - may be necessary as LB Routeur informs all connection */
+        if(pNotification->DataTransfered.pPayload[1] == 0x01)
+        {
+          BSP_LED_On(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER 3 : LED1 ON\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x01; /* LED1 ON */
+        }
+        if(pNotification->DataTransfered.pPayload[1] == 0x00)
+        {
+          BSP_LED_Off(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER 3 : LED1 OFF\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x00; /* LED1 OFF */
+        }
+      }
+#endif
+#if(P2P_SERVER4 != 0)
+      if(pNotification->DataTransfered.pPayload[0] == 0x04){ /* end device 4 selected */ 
+        if(pNotification->DataTransfered.pPayload[1] == 0x01)
+        {
+          BSP_LED_On(LED_BLUE);
+           APP_DBG_MSG("-- P2P APPLICATION SERVER 2 : LED1 ON\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x01; /* LED1 ON */
+        }
+        if(pNotification->DataTransfered.pPayload[1] == 0x00)
+        {
+          BSP_LED_Off(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER 2 : LED1 OFF\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x00; /* LED1 OFF */
+        }   
+      }
+#endif     
+#if(P2P_SERVER5 != 0)  
+      if(pNotification->DataTransfered.pPayload[0] == 0x05){ /* end device 5 selected - may be necessary as LB Routeur informs all connection */
+        if(pNotification->DataTransfered.pPayload[1] == 0x01)
+        {
+          BSP_LED_On(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER 5 : LED1 ON\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x01; /* LED1 ON */
+        }
+        if(pNotification->DataTransfered.pPayload[1] == 0x00)
+        {
+          BSP_LED_Off(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER 5 : LED1 OFF\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x00; /* LED1 OFF */
+        }
+      }
+#endif
+#if(P2P_SERVER6 != 0)
+      if(pNotification->DataTransfered.pPayload[0] == 0x06){ /* end device 6 selected */ 
+        if(pNotification->DataTransfered.pPayload[1] == 0x01)
+        {
+          BSP_LED_On(LED_BLUE);
+           APP_DBG_MSG("-- P2P APPLICATION SERVER 6 : LED1 ON\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x01; /* LED1 ON */
+        }
+        if(pNotification->DataTransfered.pPayload[1] == 0x00)
+        {
+          BSP_LED_Off(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER 6 : LED1 OFF\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x00; /* LED1 OFF */
+        }   
+      }
+#endif 
+/* USER CODE END P2PS_STM_WRITE_EVT */
+      break;
+
+    default:
+/* USER CODE BEGIN P2PS_STM_App_Notification_default */
+      
+/* USER CODE END P2PS_STM_App_Notification_default */
+      break;
+  }
+/* USER CODE BEGIN P2PS_STM_App_Notification_2 */
+
+/* USER CODE END P2PS_STM_App_Notification_2 */
+  return;
+}
+
+void P2PS_APP_Notification(P2PS_APP_ConnHandle_Not_evt_t *pNotification)
+{
+/* USER CODE BEGIN P2PS_APP_Notification_1 */
+
+/* USER CODE END P2PS_APP_Notification_1 */
+  switch(pNotification->P2P_Evt_Opcode)
+  {
+/* USER CODE BEGIN P2PS_APP_Notification_P2P_Evt_Opcode */
+
+/* USER CODE END P2PS_APP_Notification_P2P_Evt_Opcode */
+  case PEER_CONN_HANDLE_EVT :
+/* USER CODE BEGIN PEER_CONN_HANDLE_EVT */
+          
+/* USER CODE END PEER_CONN_HANDLE_EVT */
+    break;
+
+    case PEER_DISCON_HANDLE_EVT :
+/* USER CODE BEGIN PEER_DISCON_HANDLE_EVT */
+       P2PS_APP_LED_BUTTON_context_Init();       
+/* USER CODE END PEER_DISCON_HANDLE_EVT */
+    break;
+    
+    default:
+/* USER CODE BEGIN P2PS_APP_Notification_default */
+
+/* USER CODE END P2PS_APP_Notification_default */
+      break;
+  }
+/* USER CODE BEGIN P2PS_APP_Notification_2 */
+
+/* USER CODE END P2PS_APP_Notification_2 */
+  return;
+}
+
+void P2PS_APP_Init(void)
+{
+/* USER CODE BEGIN P2PS_APP_Init */
+  UTIL_SEQ_RegTask( 1<< CFG_TASK_SW1_BUTTON_PUSHED_ID, UTIL_SEQ_RFU, P2PS_Send_Notification );
+
+  /**
+   * Initialize LedButton Service
+   */
+  P2P_Server_App_Context.Notification_Status=0; 
+  P2PS_APP_LED_BUTTON_context_Init();
+/* USER CODE END P2PS_APP_Init */
+  return;
+}
+
+/* USER CODE BEGIN FD */
+void P2PS_APP_LED_BUTTON_context_Init(void){
+  
+  BSP_LED_Off(LED_BLUE);
+  
+  #if(P2P_SERVER1 != 0)
+  P2P_Server_App_Context.LedControl.Device_Led_Selection=0x01; /* Device1 */
+  P2P_Server_App_Context.LedControl.Led1=0x00; /* led OFF */
+  P2P_Server_App_Context.ButtonControl.Device_Button_Selection=0x01;/* Device1 */
+  P2P_Server_App_Context.ButtonControl.ButtonStatus=0x00;
+#endif
+#if(P2P_SERVER2 != 0)
+  P2P_Server_App_Context.LedControl.Device_Led_Selection=0x02; /* Device2 */
+  P2P_Server_App_Context.LedControl.Led1=0x00; /* led OFF */
+  P2P_Server_App_Context.ButtonControl.Device_Button_Selection=0x02;/* Device2 */
+  P2P_Server_App_Context.ButtonControl.ButtonStatus=0x00;
+#endif  
+#if(P2P_SERVER3 != 0)
+  P2P_Server_App_Context.LedControl.Device_Led_Selection=0x03; /* Device3 */
+  P2P_Server_App_Context.LedControl.Led1=0x00; /* led OFF */
+  P2P_Server_App_Context.ButtonControl.Device_Button_Selection=0x03; /* Device3 */
+  P2P_Server_App_Context.ButtonControl.ButtonStatus=0x00;
+#endif
+#if(P2P_SERVER4 != 0)
+  P2P_Server_App_Context.LedControl.Device_Led_Selection=0x04; /* Device4 */
+  P2P_Server_App_Context.LedControl.Led1=0x00; /* led OFF */
+  P2P_Server_App_Context.ButtonControl.Device_Button_Selection=0x04; /* Device4 */
+  P2P_Server_App_Context.ButtonControl.ButtonStatus=0x00;
+#endif  
+ #if(P2P_SERVER5 != 0)
+  P2P_Server_App_Context.LedControl.Device_Led_Selection=0x05; /* Device5 */
+  P2P_Server_App_Context.LedControl.Led1=0x00; /* led OFF */
+  P2P_Server_App_Context.ButtonControl.Device_Button_Selection=0x05; /* Device5 */
+  P2P_Server_App_Context.ButtonControl.ButtonStatus=0x00;
+#endif
+#if(P2P_SERVER6 != 0)
+  P2P_Server_App_Context.LedControl.Device_Led_Selection=0x06; /* device6 */
+  P2P_Server_App_Context.LedControl.Led1=0x00; /* led OFF */
+  P2P_Server_App_Context.ButtonControl.Device_Button_Selection=0x06; /* Device6 */
+  P2P_Server_App_Context.ButtonControl.ButtonStatus=0x00;
+#endif  
+}
+
+void P2PS_APP_SW1_Button_Action(void)
+{
+  UTIL_SEQ_SetTask( 1<
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __P2P_SERVER_APP_H
+#define __P2P_SERVER_APP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+typedef enum
+{
+  PEER_CONN_HANDLE_EVT,
+  PEER_DISCON_HANDLE_EVT,
+} P2PS_APP__Opcode_Notification_evt_t;
+
+typedef struct
+{
+  P2PS_APP__Opcode_Notification_evt_t   P2P_Evt_Opcode;
+  uint16_t                              ConnectionHandle;
+}P2PS_APP_ConnHandle_Not_evt_t;
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void P2PS_APP_Init( void );
+  void P2PS_APP_Notification( P2PS_APP_ConnHandle_Not_evt_t *pNotification );
+/* USER CODE BEGIN EF */
+  void P2PS_APP_SW1_Button_Action( void );
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__P2P_SERVER_APP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/Target/hw_ipcc.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/Target/hw_ipcc.c
new file mode 100644
index 000000000..0f839543a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/STM32_WPAN/Target/hw_ipcc.c
@@ -0,0 +1,523 @@
+/**
+ ******************************************************************************
+  * File Name          : Target/hw_ipcc.c
+  * Description        : Hardware IPCC source file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "mbox_def.h"
+
+/* Global variables ---------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+#define HW_IPCC_TX_PENDING( channel ) ( !(LL_C1_IPCC_IsActiveFlag_CHx( IPCC, channel )) ) &&  (((~(IPCC->C1MR)) & (channel << 16U)))
+#define HW_IPCC_RX_PENDING( channel )  (LL_C2_IPCC_IsActiveFlag_CHx( IPCC, channel )) && (((~(IPCC->C1MR)) & (channel << 0U)))
+
+/* Private macros ------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static void (*FreeBufCb)( void );
+
+/* Private function prototypes -----------------------------------------------*/
+static void HW_IPCC_BLE_EvtHandler( void );
+static void HW_IPCC_BLE_AclDataEvtHandler( void );
+static void HW_IPCC_MM_FreeBufHandler( void );
+static void HW_IPCC_SYS_CmdEvtHandler( void );
+static void HW_IPCC_SYS_EvtHandler( void );
+static void HW_IPCC_TRACES_EvtHandler( void );
+
+#ifdef THREAD_WB
+static void HW_IPCC_OT_CmdEvtHandler( void );
+static void HW_IPCC_THREAD_NotEvtHandler( void );
+static void HW_IPCC_THREAD_CliNotEvtHandler( void );
+#endif
+
+#ifdef MAC_802_15_4_WB
+static void HW_IPCC_MAC_802_15_4_CmdEvtHandler( void );
+static void HW_IPCC_MAC_802_15_4_NotEvtHandler( void );
+#endif
+
+#ifdef ZIGBEE_WB
+static void HW_IPCC_ZIGBEE_CmdEvtHandler( void );
+static void HW_IPCC_ZIGBEE_StackNotifEvtHandler( void );
+static void HW_IPCC_ZIGBEE_CliNotifEvtHandler( void );
+#endif
+
+/* Public function definition -----------------------------------------------*/
+
+/******************************************************************************
+ * INTERRUPT HANDLER
+ ******************************************************************************/
+void HW_IPCC_Rx_Handler( void )
+{
+  if (HW_IPCC_RX_PENDING( HW_IPCC_SYSTEM_EVENT_CHANNEL ))
+  {
+      HW_IPCC_SYS_EvtHandler();
+  }
+#ifdef MAC_802_15_4_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_MAC_802_15_4_NotEvtHandler();
+  }
+#endif /* MAC_802_15_4_WB */
+#ifdef THREAD_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_THREAD_NotEvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_THREAD_CliNotEvtHandler();
+  }
+#endif /* THREAD_WB */
+#ifdef ZIGBEE_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_ZIGBEE_StackNotifEvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
+  {
+      HW_IPCC_ZIGBEE_CliNotifEvtHandler();
+  }
+#endif /* ZIGBEE_WB */
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_BLE_EVENT_CHANNEL ))
+  {
+    HW_IPCC_BLE_EvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_TRACES_CHANNEL ))
+  {
+    HW_IPCC_TRACES_EvtHandler();
+  }
+
+  return;
+}
+
+void HW_IPCC_Tx_Handler( void )
+{
+  if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_SYS_CmdEvtHandler();
+  }
+#ifdef MAC_802_15_4_WB
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_MAC_802_15_4_CmdEvtHandler();
+  }
+#endif /* MAC_802_15_4_WB */
+#ifdef THREAD_WB
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_OT_CmdEvtHandler();
+  }
+#endif /* THREAD_WB */
+#ifdef ZIGBEE_WB
+  if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
+  {
+      HW_IPCC_ZIGBEE_CmdEvtHandler();
+  }
+#endif /* ZIGBEE_WB */
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_SYS_CmdEvtHandler();
+  }
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ))
+  {
+    HW_IPCC_MM_FreeBufHandler();
+  }
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_HCI_ACL_DATA_CHANNEL ))
+  {
+    HW_IPCC_BLE_AclDataEvtHandler();
+  }
+
+  return;
+}
+/******************************************************************************
+ * GENERAL
+ ******************************************************************************/
+void HW_IPCC_Enable( void )
+{
+  /**
+   * When the device is out of standby, it is required to use the EXTI mechanism to wakeup CPU2
+   */
+  LL_C2_EXTI_EnableEvent_32_63( LL_EXTI_LINE_41 );
+  LL_EXTI_EnableRisingTrig_32_63( LL_EXTI_LINE_41 );
+	
+  /**
+   * In case the SBSFU is implemented, it may have already set the C2BOOT bit to startup the CPU2.
+   * In that case, to keep the mechanism transparent to the user application, it shall call the system command
+   * SHCI_C2_Reinit( ) before jumping to the application.
+   * When the CPU2 receives that command, it waits for its event input to be set to restart the CPU2 firmware.
+   * This is required because once C2BOOT has been set once, a clear/set on C2BOOT has no effect.
+   * When SHCI_C2_Reinit( ) is not called, generating an event to the CPU2 does not have any effect
+   * So, by default, the application shall both set the event flag and set the C2BOOT bit.
+   */
+  __SEV( );       /* Set the internal event flag and send an event to the CPU2 */
+  __WFE( );       /* Clear the internal event flag */
+  LL_PWR_EnableBootC2( );
+
+  return;
+}
+
+void HW_IPCC_Init( void )
+{
+  LL_AHB3_GRP1_EnableClock( LL_AHB3_GRP1_PERIPH_IPCC );
+
+  LL_C1_IPCC_EnableIT_RXO( IPCC );
+  LL_C1_IPCC_EnableIT_TXF( IPCC );
+
+  HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn);
+  HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn);
+
+  return;
+}
+
+/******************************************************************************
+ * BLE
+ ******************************************************************************/
+void HW_IPCC_BLE_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_BLE_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_BLE_CMD_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_BLE_EvtHandler( void )
+{
+  HW_IPCC_BLE_RxEvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_BLE_SendAclData( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_BLE_AclDataEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+
+  HW_IPCC_BLE_AclDataAckNot();
+
+  return;
+}
+
+__weak void HW_IPCC_BLE_AclDataAckNot( void ){};
+__weak void HW_IPCC_BLE_RxEvtNot( void ){};
+
+/******************************************************************************
+ * SYSTEM
+ ******************************************************************************/
+void HW_IPCC_SYS_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_SYS_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_SYS_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+
+  HW_IPCC_SYS_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_SYS_EvtHandler( void )
+{
+  HW_IPCC_SYS_EvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
+
+  return;
+}
+
+__weak void HW_IPCC_SYS_CmdEvtNot( void ){};
+__weak void HW_IPCC_SYS_EvtNot( void ){};
+
+/******************************************************************************
+ * MAC 802.15.4
+ ******************************************************************************/
+#ifdef MAC_802_15_4_WB
+void HW_IPCC_MAC_802_15_4_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_MAC_802_15_4_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_MAC_802_15_4_SendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_MAC_802_15_4_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+
+  HW_IPCC_MAC_802_15_4_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_MAC_802_15_4_NotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_MAC_802_15_4_EvtNot();
+
+  return;
+}
+__weak void HW_IPCC_MAC_802_15_4_CmdEvtNot( void ){};
+__weak void HW_IPCC_MAC_802_15_4_EvtNot( void ){};
+#endif
+
+/******************************************************************************
+ * THREAD
+ ******************************************************************************/
+#ifdef THREAD_WB
+void HW_IPCC_THREAD_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_OT_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_CLI_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_THREAD_SendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_THREAD_CliSendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_OT_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  HW_IPCC_OT_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_THREAD_NotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_THREAD_EvtNot();
+
+  return;
+}
+
+static void HW_IPCC_THREAD_CliNotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_THREAD_CliEvtNot();
+
+  return;
+}
+
+__weak void HW_IPCC_OT_CmdEvtNot( void ){};
+__weak void HW_IPCC_CLI_CmdEvtNot( void ){};
+__weak void HW_IPCC_THREAD_EvtNot( void ){};
+
+#endif /* THREAD_WB */
+
+/******************************************************************************
+ * ZIGBEE
+ ******************************************************************************/
+#ifdef ZIGBEE_WB
+void HW_IPCC_ZIGBEE_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendAppliCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendCliCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
+
+   return;
+}
+
+void HW_IPCC_ZIGBEE_SendAppliCmdAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendCliCmdAck( void )
+{
+    LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+    LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_CmdEvtHandler( void )
+{
+    LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+    HW_IPCC_ZIGBEE_AppliCmdNotification();
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_StackNotifEvtHandler( void )
+{
+    LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+    HW_IPCC_ZIGBEE_AppliAsyncEvtNotification();
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_CliNotifEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_ZIGBEE_CliEvtNotification();
+
+  return;
+}
+
+__weak void HW_IPCC_ZIGBEE_AppliCmdNotification( void ){};
+__weak void HW_IPCC_ZIGBEE_AppliAsyncEvtNotification( void ){};
+__weak void HW_IPCC_ZIGBEE_CliEvtNotification( void ){};
+#endif /* ZIGBEE_WB */
+
+/******************************************************************************
+ * MEMORY MANAGER
+ ******************************************************************************/
+void HW_IPCC_MM_SendFreeBuf( void (*cb)( void ) )
+{
+  if ( LL_C1_IPCC_IsActiveFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ) )
+  {
+    FreeBufCb = cb;
+    LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+  }
+  else
+  {
+    cb();
+
+    LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+  }
+
+  return;
+}
+
+static void HW_IPCC_MM_FreeBufHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+
+  FreeBufCb();
+
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+
+  return;
+}
+
+/******************************************************************************
+ * TRACES
+ ******************************************************************************/
+void HW_IPCC_TRACES_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_TRACES_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_TRACES_EvtHandler( void )
+{
+  HW_IPCC_TRACES_EvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_TRACES_CHANNEL );
+
+  return;
+}
+
+__weak void HW_IPCC_TRACES_EvtNot( void ){};
+
+/******************* (C) COPYRIGHT 2019 STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/readme.txt b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/readme.txt
new file mode 100644
index 000000000..6ec52344d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer/readme.txt
@@ -0,0 +1,124 @@
+/**
+  @page BLE_p2pServer Application
+
+  @verbatim
+  ******************************************************************************
+  * @file    BLE/BLE_p2pServer/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the BLE_p2pServer application
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                               www.st.com/SLA0044
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Application Description
+
+This example is to demonstrate Point-to-Point communication using BLE component. 
+
+Two STM32WB35xx boards are used, one acting as GATT client, and one as GATT server.
+For example, BLE_P2PClient application is downloaded in a Nucleo board (MB1507A) and BLE_p2pServer application in a Nucleo board (MB1507A).
+The client could be located in a phone also, using the ST BLE Sensor application instead of the MB1507A board. 
+
+	
+@par Directory contents 
+  
+  - BLE/BLE_p2pServer/Core/Inc/stm32wbxx_hal_conf.h	        HAL configuration file
+  - BLE/BLE_p2pServer/Core/Inc/stm32wbxx_it.h          		Interrupt handlers header file
+  - BLE/BLE_p2pServer/Core/Inc/main.h                  		Header for main.c module
+  - BLE/BLE_p2pServer/STM32_WPAN/App/app_ble.h           	Header for app_ble.c module
+  - BLE/BLE_p2pServer/Core/Inc/app_common.h            		Header for all modules with common definition
+  - BLE/BLE_p2pServer/Core/Inc/app_conf.h              		Parameters configuration file of the application
+  - BLE/BLE_p2pServer/Core/Inc/app_entry.h            		Parameters configuration file of the application
+  - BLE/BLE_p2pServer/STM32_WPAN/App/ble_conf.h            	BLE Services configuration
+  - BLE/BLE_p2pServer/STM32_WPAN/App/ble_dbg_conf.h        	BLE Traces configuration of the BLE services
+  - BLE/BLE_p2pServer/STM32_WPAN/App/p2p_server_app.h      	Header for p2p_server_app.c module
+  - BLE/BLE_p2pServer/Core/Inc/hw_conf.h           		Configuration file of the HW
+  - BLE/BLE_p2pServer/Core/Inc/utilities_conf.h    		Configuration file of the utilities
+  - BLE/BLE_p2pServer/Core/Src/stm32wbxx_it.c          		Interrupt handlers
+  - BLE/BLE_p2pServer/Core/Src/main.c                  		Main program
+  - BLE/BLE_p2pServer/Core/Src/system_stm32wbxx.c      		stm32wbxx system source file
+  - BLE/BLE_p2pServer/STM32_WPAN/App/app_ble.c      		BLE Profile implementation
+  - BLE/BLE_p2pServer/Core/Src/app_entry.c      		Initialization of the application
+  - BLE/BLE_p2pServer/STM32_WPAN/App/p2p_server_app.c   	P2P Server application
+  - BLE/BLE_p2pServer/STM32_WPAN/Target/hw_ipcc.c      		IPCC Driver
+  - BLE/BLE_p2pServer/Core/Src/stm32_lpm_if.c			Low Power Manager Interface
+  - BLE/BLE_p2pServer/Core/Src/hw_timerserver.c 		Timer Server based on RTC
+  - BLE/BLE_p2pServer/Core/Src/hw_uart.c 			UART Driver
+  
+@par Hardware and Software environment
+
+    - This application runs on STM32WB35xx devices, Nucleo boards (MB1507A)
+    
+    - Nucleo board (MB1507A) Set-up    
+       - Connect the USB Nucleo board to your PC with a USB cable type A to mini-B to ST-LINK connector (USB_STLINK)
+       - Please ensure that the ST-LINK connectors and jumpers are fitted.
+    
+    - Nucleo board (MB1507A) Set-up    
+       - Connect the Nucleo Board to your PC with a USB cable type A to mini-B to ST-LINK connector (USB_STLINK).
+       - Please ensure that the ST-LINK connectors and jumpers are fitted.
+
+@par How to use it ? 
+
+This application requests having the stm32wb3x_BLE_Stack_fw.bin binary flashed on the Wireless Coprocessor.
+If it is not the case, you need to use STM32CubeProgrammer to load the appropriate binary.
+All available binaries are located under /Projects/STM32_Copro_Wireless_Binaries directory.
+Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the detailed procedure to change the
+Wireless Coprocessor binary.  
+   
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load the image into Target memory
+ - OR use the BLE_p2pServer_reference.hex from Binary directory
+ - This must be done for BLE_p2pServer (MB1507A) 
+
+First demonstration
+On the android/ios device, enable the Bluetooth communications, and if not done before,
+ - Install the ST BLE Profile application on the android device
+	https://play.google.com/store/apps/details?id=com.stm.bluetoothlevalidation&hl=en
+    https://itunes.apple.com/fr/App/st-ble-profile/id1081331769?mt=8
+
+ - Install the ST BLE Sensor application on the ios/android device
+	https://play.google.com/store/apps/details?id=com.st.bluems
+	https://itunes.apple.com/us/App/st-bluems/id993670214?mt=8
+
+ - Power on the Nucleo board with the BLE_P2P_Server application
+ - Then, click on the App icon, ST BLE Sensor (android device)
+ - connect to the device
+ - select the P2PSRVx in the device list and play with the Light and the SW1 button of the board
+
+
+Second demonstration
+ - BLE_p2pServer may be connected by BLE_p2pClient.
+ - Once the code (BLE_p2pServer & BLE_p2pClient) is downloaded into the two STM32WB35xx boards and executed, the modules are initialized. 
+ 
+ - BLE_p2pServer may be connected by BLE_p2pClient.
+ - Once the code (BLE_p2pServer & BLE_p2pClient) is downloaded into the two STM32WB35xx boards and executed, the modules are initialized. 
+
+ - The Peripheral device (BLE_p2pServer) starts advertising (during 1 minute), the green led blinks for each advertising event.
+ - The Central device (BLE_p2pClient) starts scanning when pressing the User button (SW1). 
+   - BLE_p2pClient blue led becomes on. 
+   - Scan req takes about 5 seconds.
+   - Make sure BLE_p2pServer advertises, if not press reset button or switch off/on to restart advertising.
+ - Then, it automatically connects to the BLE_p2pServer. 
+   - Blue led turns off and green led starts blinking as on the MB1507A. Connection is done.
+ - When pressing SW1 on a board, the blue led toggles on the other one.
+   - The SW1 button can be pressed independently on the GATT Client or on the GATT Server.
+ - When the server is located on a MB1507A, the connection interval can be modified from 50ms to 1s and vice-versa using SW2. 
+ - The green led on the 2 boards blinks for each advertising event, it means quickly when 50ms and slowly when 1s. 
+ - Passing from 50ms to 1s is instantaneous, but from 1s to 50ms takes around 10 seconds.
+ - The SW1 event, switch on/off blue led, depends on the connection Interval event. 
+   - So the delay from SW1 action and blue led change is more or less fast.
+
+   For more details refer to the Application Note: 
+  AN5289 - Building a Wireless application  
+ 
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Binary/BLE_p2pServer_ota.bin b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Binary/BLE_p2pServer_ota.bin
new file mode 100644
index 000000000..4a14695e4
Binary files /dev/null and b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Binary/BLE_p2pServer_ota.bin differ
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_common.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_common.h
new file mode 100644
index 000000000..4defc5d7a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_common.h
@@ -0,0 +1,114 @@
+/**
+ ******************************************************************************
+  * File Name          : app_common.h
+  * Description        : App Common application configuration file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_COMMON_H
+#define APP_COMMON_H
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "app_conf.h"
+
+  /* -------------------------------- *
+   *  Basic definitions               *
+   * -------------------------------- */
+
+#undef NULL
+#define NULL                    0
+
+#undef FALSE
+#define FALSE                   0
+
+#undef TRUE
+#define TRUE                    (!0)
+
+  /* -------------------------------- *
+   *  Critical Section definition     *
+   * -------------------------------- */
+#define BACKUP_PRIMASK()    uint32_t primask_bit= __get_PRIMASK()
+#define DISABLE_IRQ()       __disable_irq()
+#define RESTORE_PRIMASK()   __set_PRIMASK(primask_bit)
+
+  /* -------------------------------- *
+   *  Macro delimiters                *
+   * -------------------------------- */
+
+#define M_BEGIN     do {
+
+#define M_END       } while(0)
+
+  /* -------------------------------- *
+   *  Some useful macro definitions   *
+   * -------------------------------- */
+
+#define MAX( x, y )          (((x)>(y))?(x):(y))
+
+#define MIN( x, y )          (((x)<(y))?(x):(y))
+
+#define MODINC( a, m )       M_BEGIN  (a)++;  if ((a)>=(m)) (a)=0;  M_END
+
+#define MODDEC( a, m )       M_BEGIN  if ((a)==0) (a)=(m);  (a)--;  M_END
+
+#define MODADD( a, b, m )    M_BEGIN  (a)+=(b);  if ((a)>=(m)) (a)-=(m);  M_END
+
+#define MODSUB( a, b, m )    MODADD( a, (m)-(b), m )
+
+#define PAUSE( t )           M_BEGIN \
+                               __IO int _i; \
+                               for ( _i = t; _i > 0; _i -- ); \
+                             M_END
+
+#define DIVF( x, y )         ((x)/(y))
+
+#define DIVC( x, y )         (((x)+(y)-1)/(y))
+
+#define DIVR( x, y )         (((x)+((y)/2))/(y))
+
+#define SHRR( x, n )         ((((x)>>((n)-1))+1)>>1)
+
+#define BITN( w, n )         (((w)[(n)/32] >> ((n)%32)) & 1)
+
+#define BITNSET( w, n, b )   M_BEGIN (w)[(n)/32] |= ((U32)(b))<<((n)%32); M_END
+
+  /* -------------------------------- *
+   *  Compiler                         *
+   * -------------------------------- */
+#define PLACE_IN_SECTION( __x__ )  __attribute__((section (__x__)))
+
+#ifdef WIN32
+#define ALIGN(n)
+#else
+#define ALIGN(n)             __attribute__((aligned(n)))
+#endif
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*APP_COMMON_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_conf.h
new file mode 100644
index 000000000..0c0a2d87a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_conf.h
@@ -0,0 +1,559 @@
+/**
+ ******************************************************************************
+  * File Name          : app_conf.h
+  * Description        : Application configuration file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_CONF_H
+#define APP_CONF_H
+
+#include "hw.h"
+#include "hw_conf.h"
+#include "hw_if.h"
+
+/******************************************************************************
+ * Application Config
+ ******************************************************************************/
+
+/**< generic parameters ******************************************************/
+
+/**
+ * Define Tx Power
+ */   
+#define CFG_TX_POWER                      (0x18) /**< 0dbm */
+
+/**
+ * Define Advertising parameters
+ */
+#define CFG_ADV_BD_ADDRESS                (0x7257acd87a6c)
+#define CFG_FAST_CONN_ADV_INTERVAL_MIN    (0x80)   /**< 80ms */
+#define CFG_FAST_CONN_ADV_INTERVAL_MAX    (0xa0)  /**< 100ms */
+#define CFG_LP_CONN_ADV_INTERVAL_MIN      (0x640) /**< 1s */
+#define CFG_LP_CONN_ADV_INTERVAL_MAX      (0xfa0) /**< 2.5s */
+
+/**
+ * Define IO Authentication
+ */
+#define CFG_BONDING_MODE                  (1)
+#define CFG_FIXED_PIN                     (111111)
+#define CFG_USED_FIXED_PIN                (0)
+#define CFG_ENCRYPTION_KEY_SIZE_MAX       (16)
+#define CFG_ENCRYPTION_KEY_SIZE_MIN       (8)
+
+/**
+ * Define IO capabilities
+ */
+#define CFG_IO_CAPABILITY_DISPLAY_ONLY       (0x00)
+#define CFG_IO_CAPABILITY_DISPLAY_YES_NO     (0x01)
+#define CFG_IO_CAPABILITY_KEYBOARD_ONLY      (0x02)
+#define CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT (0x03)
+#define CFG_IO_CAPABILITY_KEYBOARD_DISPLAY   (0x04)
+
+#define CFG_IO_CAPABILITY             CFG_IO_CAPABILITY_DISPLAY_ONLY
+
+/**
+ * Define MITM modes
+ */
+#define CFG_MITM_PROTECTION_NOT_REQUIRED      (0x00)
+#define CFG_MITM_PROTECTION_REQUIRED          (0x01)
+
+#define CFG_MITM_PROTECTION             CFG_MITM_PROTECTION_REQUIRED
+
+/**
+ * Define PHY
+ */
+#define ALL_PHYS_PREFERENCE                             0x00
+#define RX_2M_PREFERRED                                 0x02
+#define TX_2M_PREFERRED                                 0x02
+#define TX_1M                                           0x01
+#define TX_2M                                           0x02
+#define RX_1M                                           0x01
+#define RX_2M                                           0x02 
+
+/**
+*   Identity root key used to derive LTK and CSRK
+*/
+#define CFG_BLE_IRK     {0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0,0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0}
+
+/**
+* Encryption root key used to derive LTK and CSRK
+*/
+#define CFG_BLE_ERK     {0xfe,0xdc,0xba,0x09,0x87,0x65,0x43,0x21,0xfe,0xdc,0xba,0x09,0x87,0x65,0x43,0x21}
+
+/* USER CODE BEGIN Generic_Parameters */
+/**
+ * SMPS supply
+ * SMPS not used when Set to 0
+ * SMPS used when Set to 1
+ */
+#define CFG_USE_SMPS    1
+/* USER CODE END Generic_Parameters */
+
+/**< specific parameters */
+/*****************************************************/
+#ifdef LITTLE_DORY
+#define PUSH_BUTTON_SW1_EXTI_IRQHandler                         EXTI0_IRQHandler
+#define PUSH_BUTTON_SW2_EXTI_IRQHandler                         EXTI4_IRQHandler
+#else
+#define PUSH_BUTTON_SW1_EXTI_IRQHandler                         EXTI4_IRQHandler
+#define PUSH_BUTTON_SW2_EXTI_IRQHandler                         EXTI0_IRQHandler
+#endif
+
+#define P2P_SERVER1    1    /*1 = Device is Peripherique*/
+#define P2P_SERVER2    0
+#define P2P_SERVER3    0
+#define P2P_SERVER4    0
+#define P2P_SERVER5    0
+#define P2P_SERVER6    0
+
+#define CFG_DEV_ID_P2P_SERVER1                  (0x83)
+#define CFG_DEV_ID_P2P_SERVER2                  (0x84)
+#define CFG_DEV_ID_P2P_SERVER3                  (0x87)
+#define CFG_DEV_ID_P2P_SERVER4                  (0x88)
+#define CFG_DEV_ID_P2P_SERVER5                  (0x89)   
+#define CFG_DEV_ID_P2P_SERVER6                  (0x8A)   
+#define CFG_DEV_ID_P2P_ROUTER                   (0x85)
+
+#define  RADIO_ACTIVITY_EVENT   1          /* 1 for OOB Demo */
+
+/**
+* AD Element - Group B Feature
+*/ 
+/* LSB - First Byte */
+#define CFG_FEATURE_THREAD_SWITCH               (0x40)
+
+/* LSB - Second Byte */
+#define CFG_FEATURE_OTA_REBOOT                  (0x20)
+
+#define CONN_L(x) ((int)((x)/0.625f))
+#define CONN_P(x) ((int)((x)/1.25f))
+
+  /*  L2CAP Connection Update request parameters used for test only with smart Phone */
+#define L2CAP_REQUEST_NEW_CONN_PARAM             1
+
+#define L2CAP_INTERVAL_MIN              CONN_P(1000) /* 1s */
+#define L2CAP_INTERVAL_MAX              CONN_P(1000) /* 1s */
+#define L2CAP_SLAVE_LATENCY             0x0000
+#define L2CAP_TIMEOUT_MULTIPLIER        0x1F4
+
+/******************************************************************************
+ * BLE Stack
+ ******************************************************************************/
+/**
+ * Maximum number of simultaneous connections that the device will support.
+ * Valid values are from 1 to 8
+ */
+#define CFG_BLE_NUM_LINK            8
+
+/**
+ * Maximum number of Services that can be stored in the GATT database.
+ * Note that the GAP and GATT services are automatically added so this parameter should be 2 plus the number of user services
+ */
+#define CFG_BLE_NUM_GATT_SERVICES   8
+
+/**
+ * Maximum number of Attributes
+ * (i.e. the number of characteristic + the number of characteristic values + the number of descriptors, excluding the services)
+ * that can be stored in the GATT database.
+ * Note that certain characteristics and relative descriptors are added automatically during device initialization
+ * so this parameters should be 9 plus the number of user Attributes
+ */
+#define CFG_BLE_NUM_GATT_ATTRIBUTES 68
+
+/**
+ * Maximum supported ATT_MTU size
+ */
+#define CFG_BLE_MAX_ATT_MTU             (156)
+
+/**
+ * Size of the storage area for Attribute values
+ *  This value depends on the number of attributes used by application. In particular the sum of the following quantities (in octets) should be made for each attribute:
+ *  - attribute value length
+ *  - 5, if UUID is 16 bit; 19, if UUID is 128 bit
+ *  - 2, if server configuration descriptor is used
+ *  - 2*DTM_NUM_LINK, if client configuration descriptor is used
+ *  - 2, if extended properties is used
+ *  The total amount of memory needed is the sum of the above quantities for each attribute.
+ */
+#define CFG_BLE_ATT_VALUE_ARRAY_SIZE    (1344)
+
+/**
+ * Prepare Write List size in terms of number of packet with ATT_MTU=23 bytes
+ */
+#define CFG_BLE_PREPARE_WRITE_LIST_SIZE         ( 0x3A )
+
+/**
+ * Number of allocated memory blocks
+ */
+#define CFG_BLE_MBLOCK_COUNT            ( 0x79 )
+
+/**
+ * Enable or disable the Extended Packet length feature. Valid values are 0 or 1.
+ */
+#define CFG_BLE_DATA_LENGTH_EXTENSION   1
+
+/**
+ * Sleep clock accuracy in Slave mode (ppm value)
+ */
+#define CFG_BLE_SLAVE_SCA   500
+
+/**
+ * Sleep clock accuracy in Master mode
+ * 0 : 251 ppm to 500 ppm
+ * 1 : 151 ppm to 250 ppm
+ * 2 : 101 ppm to 150 ppm
+ * 3 : 76 ppm to 100 ppm
+ * 4 : 51 ppm to 75 ppm
+ * 5 : 31 ppm to 50 ppm
+ * 6 : 21 ppm to 30 ppm
+ * 7 : 0 ppm to 20 ppm
+ */
+#define CFG_BLE_MASTER_SCA   0
+
+/**
+ *  Source for the 32 kHz slow speed clock
+ *  1 : internal RO
+ *  0 : external crystal ( no calibration )
+ */
+#define CFG_BLE_LSE_SOURCE  0
+
+/**
+ * Start up time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us)
+ */
+#define CFG_BLE_HSE_STARTUP_TIME  0x148
+
+/**
+ * Maximum duration of the connection event when the device is in Slave mode in units of 625/256 us (~2.44 us)
+ */
+#define CFG_BLE_MAX_CONN_EVENT_LENGTH  ( 0xFFFFFFFF )
+
+/**
+ * Viterbi Mode
+ * 1 : enabled
+ * 0 : disabled
+ */
+#define CFG_BLE_VITERBI_MODE  1
+
+/**
+ *  LL Only Mode
+ *  1 : LL Only
+ *  0 : LL + Host
+ */
+#define CFG_BLE_LL_ONLY  0
+/******************************************************************************
+ * Transport Layer
+ ******************************************************************************/
+/**
+ * Queue length of BLE Event
+ * This parameter defines the number of asynchronous events that can be stored in the HCI layer before
+ * being reported to the application. When a command is sent to the BLE core coprocessor, the HCI layer
+ * is waiting for the event with the Num_HCI_Command_Packets set to 1. The receive queue shall be large
+ * enough to store all asynchronous events received in between.
+ * When CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE is set to 27, this allow to store three 255 bytes long asynchronous events
+ * between the HCI command and its event.
+ * This parameter depends on the value given to CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE. When the queue size is to small,
+ * the system may hang if the queue is full with asynchronous events and the HCI layer is still waiting
+ * for a CC/CS event, In that case, the notification TL_BLE_HCI_ToNot() is called to indicate
+ * to the application a HCI command did not receive its command event within 30s (Default HCI Timeout).
+ */
+#define CFG_TLBLE_EVT_QUEUE_LENGTH 5
+/**
+ * This parameter should be set to fit most events received by the HCI layer. It defines the buffer size of each element
+ * allocated in the queue of received events and can be used to optimize the amount of RAM allocated by the Memory Manager.
+ * It should not exceed 255 which is the maximum HCI packet payload size (a greater value is a lost of memory as it will
+ * never be used)
+ * It shall be at least 4 to receive the command status event in one frame.
+ * The default value is set to 27 to allow receiving an event of MTU size in a single buffer. This value maybe reduced
+ * further depending on the application.
+ *
+ */
+#define CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE 255   /**< Set to 255 with the memory manager and the mailbox */
+
+#define TL_BLE_EVENT_FRAME_SIZE ( TL_EVT_HDR_SIZE + CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE )
+/******************************************************************************
+ * UART interfaces
+ ******************************************************************************/
+
+/**
+ * Select UART interfaces
+ */
+#define CFG_DEBUG_TRACE_UART    hw_uart1
+#define CFG_CONSOLE_MENU      hw_lpuart1
+/******************************************************************************
+ * USB interface
+ ******************************************************************************/
+
+/**
+ * Enable/Disable USB interface
+ */
+#define CFG_USB_INTERFACE_ENABLE    0
+
+/******************************************************************************
+ * Low Power
+ ******************************************************************************/
+/**
+ *  When set to 1, the low power mode is enable
+ *  When set to 0, the device stays in RUN mode
+ */
+#define CFG_LPM_SUPPORTED    1
+
+/******************************************************************************
+ * Timer Server
+ ******************************************************************************/
+/**
+ *  CFG_RTC_WUCKSEL_DIVIDER:  This sets the RTCCLK divider to the wakeup timer.
+ *  The higher is the value, the better is the power consumption and the accuracy of the timerserver
+ *  The lower is the value, the finest is the granularity
+ *
+ *  CFG_RTC_ASYNCH_PRESCALER: This sets the asynchronous prescaler of the RTC. It should as high as possible ( to ouput
+ *  clock as low as possible) but the output clock should be equal or higher frequency compare to the clock feeding
+ *  the wakeup timer. A lower clock speed would impact the accuracy of the timer server.
+ *
+ *  CFG_RTC_SYNCH_PRESCALER: This sets the synchronous prescaler of the RTC.
+ *  When the 1Hz calendar clock is required, it shall be sets according to other settings
+ *  When the 1Hz calendar clock is not needed, CFG_RTC_SYNCH_PRESCALER should be set to 0x7FFF (MAX VALUE)
+ *
+ *  CFG_RTCCLK_DIVIDER_CONF:
+ *  Shall be set to either 0,2,4,8,16
+ *  When set to either 2,4,8,16, the 1Hhz calendar is supported
+ *  When set to 0, the user sets its own configuration
+ *
+ *  The following settings are computed with LSI as input to the RTC
+ */
+#define CFG_RTCCLK_DIVIDER_CONF 0
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 0)
+/**
+ * Custom configuration
+ * It does not support 1Hz calendar
+ * It divides the RTC CLK by 16
+ */
+#define CFG_RTCCLK_DIV  (16)
+#define CFG_RTC_WUCKSEL_DIVIDER (0)
+#define CFG_RTC_ASYNCH_PRESCALER (CFG_RTCCLK_DIV - 1)
+#define CFG_RTC_SYNCH_PRESCALER (0x7FFF)
+
+#else
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 2)
+/**
+ * It divides the RTC CLK by 2
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (3)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 4)
+/**
+ * It divides the RTC CLK by 4
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (2)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 8)
+/**
+ * It divides the RTC CLK by 8
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (1)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 16)
+/**
+ * It divides the RTC CLK by 16
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (0)
+#endif
+
+#define CFG_RTCCLK_DIV              CFG_RTCCLK_DIVIDER_CONF
+#define CFG_RTC_ASYNCH_PRESCALER    (CFG_RTCCLK_DIV - 1)
+#define CFG_RTC_SYNCH_PRESCALER     (DIVR( LSE_VALUE, (CFG_RTC_ASYNCH_PRESCALER+1) ) - 1 )
+
+#endif
+
+/** tick timer value in us */
+#define CFG_TS_TICK_VAL           DIVR( (CFG_RTCCLK_DIV * 1000000), LSE_VALUE )
+
+typedef enum
+{
+    CFG_TIM_PROC_ID_ISR,
+} CFG_TimProcID_t;
+
+/******************************************************************************
+ * Debug
+ ******************************************************************************/
+/**
+ * When set, this resets some hw resources to set the device in the same state than the power up
+ * The FW resets only register that may prevent the FW to run properly
+ *
+ * This shall be set to 0 in a final product
+ *
+ */
+#define CFG_HW_RESET_BY_FW         1
+
+/**
+ * keep debugger enabled while in any low power mode when set to 1
+ * should be set to 0 in production
+ */
+#define CFG_DEBUGGER_SUPPORTED    1
+
+/**
+ * When set to 1, the traces are enabled in the BLE services
+ */
+#define CFG_DEBUG_BLE_TRACE     1
+
+/**
+ * Enable or Disable traces in application
+ */
+#define CFG_DEBUG_APP_TRACE     1
+
+#if (CFG_DEBUG_APP_TRACE != 0)
+#define APP_DBG_MSG                 PRINT_MESG_DBG
+#else
+#define APP_DBG_MSG                 PRINT_NO_MESG
+#endif
+
+#if ( (CFG_DEBUG_BLE_TRACE != 0) || (CFG_DEBUG_APP_TRACE != 0) )
+#define CFG_DEBUG_TRACE             1
+#endif
+
+#if (CFG_DEBUG_TRACE != 0)
+#undef CFG_LPM_SUPPORTED
+#undef CFG_DEBUGGER_SUPPORTED
+#define CFG_LPM_SUPPORTED         0
+#define CFG_DEBUGGER_SUPPORTED      1
+#endif
+
+/**
+ * When CFG_DEBUG_TRACE_FULL is set to 1, the trace are output with the API name, the file name and the line number
+ * When CFG_DEBUG_TRACE_LIGHT is set to 1, only the debug message is output
+ *
+ * When both are set to 0, no trace are output
+ * When both are set to 1,  CFG_DEBUG_TRACE_FULL is selected
+ */
+#define CFG_DEBUG_TRACE_LIGHT     1
+#define CFG_DEBUG_TRACE_FULL      0
+
+#if (( CFG_DEBUG_TRACE != 0 ) && ( CFG_DEBUG_TRACE_LIGHT == 0 ) && (CFG_DEBUG_TRACE_FULL == 0))
+#undef CFG_DEBUG_TRACE_FULL
+#undef CFG_DEBUG_TRACE_LIGHT
+#define CFG_DEBUG_TRACE_FULL      0
+#define CFG_DEBUG_TRACE_LIGHT     1
+#endif
+
+#if ( CFG_DEBUG_TRACE == 0 )
+#undef CFG_DEBUG_TRACE_FULL
+#undef CFG_DEBUG_TRACE_LIGHT
+#define CFG_DEBUG_TRACE_FULL      0
+#define CFG_DEBUG_TRACE_LIGHT     0
+#endif
+
+/**
+ * When not set, the traces is looping on sending the trace over UART
+ */
+#define DBG_TRACE_USE_CIRCULAR_QUEUE 1
+
+/**
+ * max buffer Size to queue data traces and max data trace allowed.
+ * Only Used if DBG_TRACE_USE_CIRCULAR_QUEUE is defined
+ */
+#define DBG_TRACE_MSG_QUEUE_SIZE 4096
+#define MAX_DBG_TRACE_MSG_SIZE 1024
+
+/* USER CODE BEGIN Defines */
+#define CFG_LED_SUPPORTED         1
+#define CFG_BUTTON_SUPPORTED      1
+/* USER CODE END Defines */
+
+/******************************************************************************
+ * Scheduler
+ ******************************************************************************/
+
+/**
+ * These are the lists of task id registered to the scheduler
+ * Each task id shall be in the range [0:31]
+ * This mechanism allows to implement a generic code in the API TL_BLE_HCI_StatusNot() to comply with
+ * the requirement that a HCI/ACI command shall never be sent if there is already one pending
+ */
+
+/**< Add in that list all tasks that may send a ACI/HCI command */
+typedef enum
+{
+    CFG_TASK_ADV_CANCEL_ID,
+    CFG_TASK_SW1_BUTTON_PUSHED_ID,
+    CFG_TASK_HCI_ASYNCH_EVT_ID,
+/* USER CODE BEGIN CFG_Task_Id_With_HCI_Cmd_t */
+
+/* USER CODE END CFG_Task_Id_With_HCI_Cmd_t */
+    CFG_LAST_TASK_ID_WITH_HCICMD,                                               /**< Shall be LAST in the list */
+} CFG_Task_Id_With_HCI_Cmd_t;
+
+/**< Add in that list all tasks that never send a ACI/HCI command */
+typedef enum
+{
+    CFG_FIRST_TASK_ID_WITH_NO_HCICMD = CFG_LAST_TASK_ID_WITH_HCICMD - 1,        /**< Shall be FIRST in the list */
+    CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID,
+/* USER CODE BEGIN CFG_Task_Id_With_NO_HCI_Cmd_t */
+
+/* USER CODE END CFG_Task_Id_With_NO_HCI_Cmd_t */
+    CFG_LAST_TASK_ID_WITHO_NO_HCICMD                                            /**< Shall be LAST in the list */
+} CFG_Task_Id_With_NO_HCI_Cmd_t;
+#define CFG_TASK_NBR    CFG_LAST_TASK_ID_WITHO_NO_HCICMD
+
+/**
+ * This is the list of priority required by the application
+ * Each Id shall be in the range 0..31
+ */
+typedef enum
+{
+    CFG_SCH_PRIO_0,
+    CFG_PRIO_NBR,
+} CFG_SCH_Prio_Id_t;
+
+/**
+ * This is a bit mapping over 32bits listing all events id supported in the application
+ */
+typedef enum
+{
+    CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID,
+    CFG_IDLEEVT_SYSTEM_HCI_CMD_EVT_RSP_ID,
+} CFG_IdleEvt_Id_t;
+
+/******************************************************************************
+ * LOW POWER
+ ******************************************************************************/
+/**
+ * Supported requester to the MCU Low Power Manager - can be increased up  to 32
+ * It lits a bit mapping of all user of the Low Power Manager
+ */
+typedef enum
+{
+    CFG_LPM_APP,
+    CFG_LPM_APP_BLE,
+  /* USER CODE BEGIN CFG_LPM_Id_t */
+
+  /* USER CODE END CFG_LPM_Id_t */
+} CFG_LPM_Id_t;
+
+/******************************************************************************
+ * OTP manager
+ ******************************************************************************/
+#define CFG_OTP_BASE_ADDRESS    OTP_AREA_BASE
+
+#define CFG_OTP_END_ADRESS      OTP_AREA_END_ADDR
+
+#endif /*APP_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_debug.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_debug.h
new file mode 100644
index 000000000..13485c16b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_debug.h
@@ -0,0 +1,45 @@
+
+/**
+  ******************************************************************************
+  * @file    app_debug.h
+  * @author  MCD Application Team
+  * @brief   Interface to support debug in the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+  /* Exported types ------------------------------------------------------------*/
+  /* Exported constants --------------------------------------------------------*/
+  /* External variables --------------------------------------------------------*/
+  /* Exported macros -----------------------------------------------------------*/
+  /* Exported functions ------------------------------------------------------- */
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_entry.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_entry.h
new file mode 100644
index 000000000..77ead2384
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_entry.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    app_entry.h
+  * @author  MCD Application Team
+  * @brief   Interface to the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_ENTRY_H
+#define APP_ENTRY_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APPE_Init( void );
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*APP_ENTRY_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/hw_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/hw_conf.h
new file mode 100644
index 000000000..523eb30f6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/hw_conf.h
@@ -0,0 +1,248 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : hw_conf.h
+  * Description        : Hardware configuration file for BLE 
+  *                      middleWare.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef HW_CONF_H
+#define HW_CONF_H
+
+/******************************************************************************
+* Semaphores
+* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
+*****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
+/* Index of the semaphore used to manage the entry Stop Mode procedure */
+#define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
+
+/* Index of the semaphore used to access the RCC */
+#define CFG_HW_RCC_SEMID                                        3
+
+/* Index of the semaphore used to access the FLASH */
+#define CFG_HW_FLASH_SEMID                                      2
+
+/* Index of the semaphore used to access the PKA */
+#define CFG_HW_PKA_SEMID                                        1
+
+/* Index of the semaphore used to access the RNG */
+#define CFG_HW_RNG_SEMID                                        0
+
+/******************************************************************************
+ * HW TIMER SERVER
+ *****************************************************************************/
+/**
+ * The user may define the maximum number of virtual timers supported.
+ * It shall not exceed 255
+ */
+#define CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER  6
+
+/**
+ * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
+ * wakeup timer.
+ * This setting is the preemptpriority part of the NVIC.
+ */
+#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO  3
+
+/**
+ * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
+ * wakeup timer.
+ * This setting is the subpriority part of the NVIC. It does not exist on all processors. When it is not supported
+ * on the CPU, the setting is ignored
+ */
+#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO  0
+
+/**
+ *  Define a critical section in the Timer server
+ *  The Timer server does not support the API to be nested
+ *  The  Application shall either:
+ *    a) Ensure this will never happen
+ *    b) Define the critical section
+ *  The default implementations is masking all interrupts using the PRIMASK bit
+ *  The TimerServer driver uses critical sections to avoid context corruption. This is achieved with the macro
+ *  TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION. When CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION is set
+ *  to 1, all STM32 interrupts are masked with the PRIMASK bit of the CortexM CPU. It is possible to use the BASEPRI
+ *  register of the CortexM CPU to keep allowed some interrupts with high priority. In that case, the user shall
+ *  re-implement TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION and shall make sure that no TimerServer
+ *  API are called when the TIMER critical section is entered
+ */
+#define CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION  1
+
+/**
+   * This value shall reflect the maximum delay there could be in the application between the time the RTC interrupt
+   * is generated by the Hardware and the time when the  RTC interrupt handler is called. This time is measured in
+   * number of RTCCLK ticks.
+   * A relaxed timing would be 10ms
+   * When the value is too short, the timerserver will not be able to count properly and all timeout may be random.
+   * When the value is too long, the device may wake up more often than the most optimal configuration. However, the
+   * impact on power consumption would be marginal (unless the value selected is extremely too long). It is strongly
+   * recommended to select a value large enough to make sure it is not too short to ensure reliability of the system
+   * as this will have marginal impact on low power mode
+   */
+#define CFG_HW_TS_RTC_HANDLER_MAX_DELAY  ( 10 * (LSI_VALUE/1000) )
+
+  /**
+   * Interrupt ID in the NVIC of the RTC Wakeup interrupt handler
+   * It shall be type of IRQn_Type
+   */
+#define CFG_HW_TS_RTC_WAKEUP_HANDLER_ID  RTC_WKUP_IRQn
+
+/******************************************************************************
+ * HW UART
+ *****************************************************************************/
+
+#define CFG_HW_LPUART1_ENABLED           1
+#define CFG_HW_LPUART1_DMA_TX_SUPPORTED  1
+
+#define CFG_HW_USART1_ENABLED           1
+#define CFG_HW_USART1_DMA_TX_SUPPORTED  1
+
+/**
+ * LPUART1
+ */
+#define CFG_HW_LPUART1_PREEMPTPRIORITY         0x0F
+#define CFG_HW_LPUART1_SUBPRIORITY             0
+
+/** < The application shall check the selected source clock is enable */
+#define CFG_HW_LPUART1_SOURCE_CLOCK             RCC_LPUART1CLKSOURCE_SYSCLK
+
+#define CFG_HW_LPUART1_BAUDRATE                115200
+#define CFG_HW_LPUART1_WORDLENGTH              UART_WORDLENGTH_8B
+#define CFG_HW_LPUART1_STOPBITS                UART_STOPBITS_1
+#define CFG_HW_LPUART1_PARITY                  UART_PARITY_NONE
+#define CFG_HW_LPUART1_HWFLOWCTL               UART_HWCONTROL_NONE
+#define CFG_HW_LPUART1_MODE                    UART_MODE_TX_RX
+#define CFG_HW_LPUART1_ADVFEATUREINIT          UART_ADVFEATURE_NO_INIT
+#define CFG_HW_LPUART1_OVERSAMPLING            UART_OVERSAMPLING_8
+
+#define CFG_HW_LPUART1_TX_PORT_CLK_ENABLE      __HAL_RCC_GPIOA_CLK_ENABLE
+#define CFG_HW_LPUART1_TX_PORT                 GPIOA
+#define CFG_HW_LPUART1_TX_PIN                  GPIO_PIN_2
+#define CFG_HW_LPUART1_TX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_LPUART1_TX_PULL                 GPIO_NOPULL
+#define CFG_HW_LPUART1_TX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_LPUART1_TX_ALTERNATE            GPIO_AF8_LPUART1
+
+#define CFG_HW_LPUART1_RX_PORT_CLK_ENABLE      __HAL_RCC_GPIOA_CLK_ENABLE
+#define CFG_HW_LPUART1_RX_PORT                 GPIOA
+#define CFG_HW_LPUART1_RX_PIN                  GPIO_PIN_3
+#define CFG_HW_LPUART1_RX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_LPUART1_RX_PULL                 GPIO_NOPULL
+#define CFG_HW_LPUART1_RX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_LPUART1_RX_ALTERNATE            GPIO_AF8_LPUART1
+
+#define CFG_HW_LPUART1_CTS_PORT_CLK_ENABLE     __HAL_RCC_GPIOA_CLK_ENABLE
+#define CFG_HW_LPUART1_CTS_PORT                GPIOA
+#define CFG_HW_LPUART1_CTS_PIN                 GPIO_PIN_6
+#define CFG_HW_LPUART1_CTS_MODE                GPIO_MODE_AF_PP
+#define CFG_HW_LPUART1_CTS_PULL                GPIO_PULLDOWN
+#define CFG_HW_LPUART1_CTS_SPEED               GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_LPUART1_CTS_ALTERNATE           GPIO_AF8_LPUART1
+
+#define CFG_HW_LPUART1_DMA_TX_PREEMPTPRIORITY  0x0F
+#define CFG_HW_LPUART1_DMA_TX_SUBPRIORITY      0
+
+#define CFG_HW_LPUART1_DMAMUX_CLK_ENABLE       __HAL_RCC_DMAMUX1_CLK_ENABLE
+#define CFG_HW_LPUART1_DMA_CLK_ENABLE          __HAL_RCC_DMA1_CLK_ENABLE
+#define CFG_HW_LPUART1_TX_DMA_REQ              DMA_REQUEST_LPUART1_TX
+#define CFG_HW_LPUART1_TX_DMA_CHANNEL          DMA1_CHANNEL_4
+#define CFG_HW_LPUART1_TX_DMA_IRQn             DMA1_CHANNEL_4_IRQn
+#define CFG_HW_LPUART1_DMA_TX_IRQHandler       DMA1_CHANNEL_4_IRQHandler
+
+/**
+ * UART1
+ */
+#define CFG_HW_USART1_PREEMPTPRIORITY         0x0F
+#define CFG_HW_USART1_SUBPRIORITY             0
+
+/** < The application shall check the selected source clock is enable */
+#define CFG_HW_USART1_SOURCE_CLOCK              RCC_USART1CLKSOURCE_SYSCLK
+
+#define CFG_HW_USART1_BAUDRATE                115200
+#define CFG_HW_USART1_WORDLENGTH              UART_WORDLENGTH_8B
+#define CFG_HW_USART1_STOPBITS                UART_STOPBITS_1
+#define CFG_HW_USART1_PARITY                  UART_PARITY_NONE
+#define CFG_HW_USART1_HWFLOWCTL               UART_HWCONTROL_NONE
+#define CFG_HW_USART1_MODE                    UART_MODE_TX_RX
+#define CFG_HW_USART1_ADVFEATUREINIT          UART_ADVFEATURE_NO_INIT
+#define CFG_HW_USART1_OVERSAMPLING            UART_OVERSAMPLING_8
+
+#define CFG_HW_USART1_TX_PORT_CLK_ENABLE      __HAL_RCC_GPIOB_CLK_ENABLE
+#define CFG_HW_USART1_TX_PORT                 GPIOB
+#define CFG_HW_USART1_TX_PIN                  GPIO_PIN_6
+#define CFG_HW_USART1_TX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_USART1_TX_PULL                 GPIO_NOPULL
+#define CFG_HW_USART1_TX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_TX_ALTERNATE            GPIO_AF7_USART1
+
+#define CFG_HW_USART1_RX_PORT_CLK_ENABLE      __HAL_RCC_GPIOB_CLK_ENABLE
+#define CFG_HW_USART1_RX_PORT                 GPIOB
+#define CFG_HW_USART1_RX_PIN                  GPIO_PIN_7
+#define CFG_HW_USART1_RX_MODE                 GPIO_MODE_AF_PP
+#define CFG_HW_USART1_RX_PULL                 GPIO_NOPULL
+#define CFG_HW_USART1_RX_SPEED                GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_RX_ALTERNATE            GPIO_AF7_USART1
+
+#define CFG_HW_USART1_CTS_PORT_CLK_ENABLE     __HAL_RCC_GPIOA_CLK_ENABLE
+#define CFG_HW_USART1_CTS_PORT                GPIOA
+#define CFG_HW_USART1_CTS_PIN                 GPIO_PIN_11
+#define CFG_HW_USART1_CTS_MODE                GPIO_MODE_AF_PP
+#define CFG_HW_USART1_CTS_PULL                GPIO_PULLDOWN
+#define CFG_HW_USART1_CTS_SPEED               GPIO_SPEED_FREQ_VERY_HIGH
+#define CFG_HW_USART1_CTS_ALTERNATE           GPIO_AF7_USART1
+
+#define CFG_HW_USART1_DMA_TX_PREEMPTPRIORITY  0x0F
+#define CFG_HW_USART1_DMA_TX_SUBPRIORITY      0
+
+#define CFG_HW_USART1_DMAMUX_CLK_ENABLE       __HAL_RCC_DMAMUX1_CLK_ENABLE
+#define CFG_HW_USART1_DMA_CLK_ENABLE          __HAL_RCC_DMA2_CLK_ENABLE
+#define CFG_HW_USART1_TX_DMA_REQ			  DMA_REQUEST_USART1_TX
+#define CFG_HW_USART1_TX_DMA_CHANNEL          DMA2_CHANNEL_4
+#define CFG_HW_USART1_TX_DMA_IRQn             DMA2_CHANNEL_4_IRQn
+#define CFG_HW_USART1_DMA_TX_IRQHandler       DMA2_CHANNEL_4_IRQHandler
+
+#endif /*HW_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/hw_if.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/hw_if.h
new file mode 100644
index 000000000..5a15665ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/hw_if.h
@@ -0,0 +1,254 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    hw_if.h
+  * @author  MCD Application Team
+  * @brief   Hardware Interface
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef HW_IF_H
+#define HW_IF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_ipcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_hsem.h"
+#include "stm32wbxx_ll_gpio.h"
+#include "stm32wbxx_ll_rtc.h"
+
+#ifdef  USE_STM32WBXX_USB_DONGLE
+#include "stm32wbxx_usb_dongle.h"
+#endif
+#ifdef  USE_STM32WBXX_NUCLEO
+  #ifdef STM32WB35xx
+  #include "nucleo_wb35ce.h"
+  #else
+  #include "stm32wbxx_nucleo.h"
+  #endif
+#endif
+#ifdef  USE_X_NUCLEO_EPD
+#include "x_nucleo_epd.h"
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /******************************************************************************
+   * HW UART
+   ******************************************************************************/
+  typedef enum
+  {
+    hw_uart1,
+    hw_uart2,
+    hw_lpuart1,
+  } hw_uart_id_t;
+
+  typedef enum
+  {
+    hw_uart_ok,
+    hw_uart_error,
+    hw_uart_busy,
+    hw_uart_to,
+  } hw_status_t;
+
+  void HW_UART_Init(hw_uart_id_t hw_uart_id);
+  void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *pData, uint16_t Size, void (*Callback)(void));
+  void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *pData, uint16_t Size,  void (*Callback)(void));
+  hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout);
+  hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*Callback)(void));
+  void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id);
+  void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id);
+
+  /******************************************************************************
+   * HW TimerServer
+   ******************************************************************************/
+  /* Exported types ------------------------------------------------------------*/
+  /**
+   * This setting is used when standby mode is supported.
+   * hw_ts_InitMode_Limited should be used when the device restarts from Standby Mode. In that case, the Timer Server does
+   * not re-initialized its context. Only the Hardware register which content has been lost is reconfigured
+   * Otherwise, hw_ts_InitMode_Full should be requested (Start from Power ON) and everything is re-initialized.
+   */
+  typedef enum
+  {
+    hw_ts_InitMode_Full,
+    hw_ts_InitMode_Limited,
+  } HW_TS_InitMode_t;
+
+  /**
+   * When a Timer is created as a SingleShot timer, it is not automatically restarted when the timeout occurs. However,
+   * the timer is kept reserved in the list and could be restarted at anytime with HW_TS_Start()
+   *
+   * When a Timer is created as a Repeated timer, it is automatically restarted when the timeout occurs.
+   */
+  typedef enum
+  {
+    hw_ts_SingleShot,
+    hw_ts_Repeated
+  } HW_TS_Mode_t;
+
+  /**
+   * hw_ts_Successful is returned when a Timer has been successfully created with HW_TS_Create(). Otherwise, hw_ts_Failed
+   * is returned. When hw_ts_Failed is returned, that means there are not enough free slots in the list to create a
+   * Timer. In that case, CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER should be increased
+   */
+  typedef enum
+  {
+    hw_ts_Successful,
+    hw_ts_Failed,
+  }HW_TS_ReturnStatus_t;
+
+  typedef void (*HW_TS_pTimerCb_t)(void);
+
+  /**
+   * @brief  Initialize the timer server
+   *         This API shall be called by the application before any timer is requested to the timer server. It
+   *         configures the RTC module to be connected to the LSI input clock.
+   *
+   * @param  TimerInitMode: When the device restarts from Standby, it should request hw_ts_InitMode_Limited so that the
+   *         Timer context is not re-initialized. Otherwise, hw_ts_InitMode_Full should be requested
+   * @param  hrtc: RTC Handle
+   * @retval None
+   */
+  void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *hrtc);
+
+  /**
+   * @brief  Interface to create a virtual timer
+   *         The user shall call this API to create a timer. Once created, the timer is reserved to the module until it
+   *         has been deleted. When creating a timer, the user shall specify the mode (single shot or repeated), the
+   *         callback to be notified when the timer expires and a module ID to identify in the timer interrupt handler
+   *         which module is concerned. In return, the user gets a timer ID to handle it.
+   *
+   * @param  TimerProcessID:  This is an identifier provided by the user and returned in the callback to allow
+   *                          identification of the requester
+   * @param  pTimerId: Timer Id returned to the user to request operation (start, stop, delete)
+   * @param  TimerMode: Mode of the virtual timer (Single shot or repeated)
+   * @param  pTimerCallBack: Callback when the virtual timer expires
+   * @retval HW_TS_ReturnStatus_t: Return whether the creation is sucessfull or not
+   */
+  HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pTimerCallBack);
+
+  /**
+   * @brief  Stop a virtual timer
+   *         This API may be used to stop a running timer. A timer which is stopped is move to the pending state.
+   *         A pending timer may be restarted at any time with a different timeout value but the mode cannot be changed.
+   *         Nothing is done when it is called to stop a timer which has been already stopped
+   *
+   * @param  TimerID:  Id of the timer to stop
+   * @retval None
+   */
+  void HW_TS_Stop(uint8_t TimerID);
+
+  /**
+   * @brief  Start a virtual timer
+   *         This API shall be used to start a timer. The timeout value is specified and may be different each time.
+   *         When the timer is in the single shot mode, it will move to the pending state when it expires. The user may
+   *         restart it at any time with a different timeout value. When the timer is in the repeated mode, it always
+   *         stay in the running state. When the timer expires, it will be restarted with the same timeout value.
+   *         This API shall not be called on a running timer.
+   *
+   * @param  TimerID:  The ID Id of the timer to start
+   * @param  timeout_ticks: Number of ticks of the virtual timer (Maximum value is (0xFFFFFFFF-0xFFFF = 0xFFFF0000)
+   * @retval None
+   */
+  void HW_TS_Start(uint8_t TimerID, uint32_t timeout_ticks);
+
+  /**
+   * @brief  Delete a virtual timer from the list
+   *         This API should be used when a timer is not needed anymore by the user. A deleted timer is removed from
+   *         the timer list managed by the timer server. It cannot be restarted again. The user has to go with the
+   *         creation of a new timer if required and may get a different timer id
+   *
+   * @param  TimerID:  The ID of the timer to remove from the list
+   * @retval None
+   */
+  void HW_TS_Delete(uint8_t TimerID);
+
+  /**
+   * @brief  Schedule the timer list on the timer interrupt handler
+   *         This interrupt handler shall be called by the application in the RTC interrupt handler. This handler takes
+   *         care of clearing all status flag required in the RTC and EXTI peripherals
+   *
+   * @param  None
+   * @retval None
+   */
+  void HW_TS_RTC_Wakeup_Handler(void);
+
+  /**
+   * @brief  Return the number of ticks to count before the interrupt
+   *         This API returns the number of ticks left to be counted before an interrupt is generated by the
+   *         Timer Server. This API may be used by the application for power management optimization. When the system
+   *         enters low power mode, the mode selection is a tradeoff between the wakeup time where the CPU is running
+   *         and the time while the CPU will be kept in low power mode before next wakeup. The deeper is the
+   *         low power mode used, the longer is the wakeup time. The low power mode management considering wakeup time
+   *         versus time in low power mode is implementation specific
+   *         When the timer is disabled (No timer in the list), it returns 0xFFFF
+   *
+   * @param  None
+   * @retval The number of ticks left to count
+   */
+  uint16_t HW_TS_RTC_ReadLeftTicksToCount(void);
+
+  /**
+   * @brief  Notify the application that a registered timer has expired
+   *         This API shall be implemented by the user application.
+   *         This API notifies the application that a timer expires. This API is running in the RTC Wakeup interrupt
+   *         context. The application may implement an Operating System to change the context priority where the timer
+   *         callback may be handled. This API provides the module ID to identify which module is concerned and to allow
+   *         sending the information to the correct task
+   *
+   * @param  TimerProcessID: The TimerProcessId associated with the timer when it has been created
+   * @param  TimerID: The TimerID of the expired timer
+   * @param  pTimerCallBack: The Callback associated with the timer when it has been created
+   * @retval None
+   */
+  void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack);
+
+  /**
+   * @brief  Notify the application that the wakeupcounter has been updated
+   *         This API should be implemented by the user application
+   *         This API notifies the application that the counter has been updated. This is expected to be used along
+   *         with the HW_TS_RTC_ReadLeftTicksToCount () API. It could be that the counter has been updated since the
+   *         last call of HW_TS_RTC_ReadLeftTicksToCount () and before entering low power mode. This notification
+   *         provides a way to the application to solve that race condition to reevaluate the counter value before
+   *         entering low power mode
+   *
+   * @param  None
+   * @retval None
+   */
+  void HW_TS_RTC_CountUpdated_AppNot(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*HW_IF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/main.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/main.h
new file mode 100644
index 000000000..c8b13c23f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/main.h
@@ -0,0 +1,75 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#ifdef STM32WB35xx
+#include "nucleo_wb35ce.h"
+#else
+#include "stm32wbxx_nucleo.h"
+#endif
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/stm32_lpm_if.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/stm32_lpm_if.h
new file mode 100644
index 000000000..d8e67947f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/stm32_lpm_if.h
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+******************************************************************************
+* @file    stm32_lpm_if.h
+* @brief   Header for stm32_lpm_if.c module (device specific LP management)
+******************************************************************************
+* @attention
+*
+* 
    © Copyright (c) 2019 STMicroelectronics. 
+* All rights reserved.
    
+*
+* This software component is licensed by ST under BSD 3-Clause license,
+* the "License"; You may not use this file except in compliance with the 
+* License. You may obtain a copy of the License at:
+*                        opensource.org/licenses/BSD-3-Clause
+*
+******************************************************************************
+*/
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_LPM_IF_H
+#define __STM32_LPM_IF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/**
+  * @brief Enters Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_EnterOffMode( void );
+/**
+  * @brief Exits Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_ExitOffMode( void );
+
+/**
+  * @brief Enters Low Power Stop Mode
+  * @note ARM exists the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterStopMode( void );
+/**
+  * @brief Exits Low Power Stop Mode
+  * @note Enable the pll at 32MHz
+  * @param none
+  * @retval none
+  */
+void PWR_ExitStopMode( void );
+
+/**
+  * @brief Enters Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterSleepMode( void );
+
+/**
+  * @brief Exits Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_ExitSleepMode( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32_LPM_IF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..eff335ddf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,354 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+#define HAL_CORTEX_MODULE_ENABLED
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+/*#define HAL_I2C_MODULE_ENABLED   */
+#define HAL_IPCC_MODULE_ENABLED
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+#define HAL_PWR_MODULE_ENABLED
+/*#define HAL_QSPI_MODULE_ENABLED   */
+#define HAL_RCC_MODULE_ENABLED
+/*#define HAL_RNG_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100UL)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  (32000UL)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  (32000UL)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    (48000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    (2097000UL) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..cf6cc65e7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/stm32wbxx_it.h
@@ -0,0 +1,78 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "app_common.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void DMA1_Channel4_IRQHandler(void);
+void USART1_IRQHandler(void);
+void LPUART1_IRQHandler(void);
+void DMA2_Channel4_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+void RTC_WKUP_IRQHandler(void);
+void IPCC_C1_TX_IRQHandler(void);
+void IPCC_C1_RX_IRQHandler(void);
+void PUSH_BUTTON_SW1_EXTI_IRQHandler(void);
+void PUSH_BUTTON_SW2_EXTI_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/utilities_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/utilities_conf.h
new file mode 100644
index 000000000..4dde3509a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Inc/utilities_conf.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : utilities_conf.h
+  * Description        : Configuration file for STM32 Utilities.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef UTILITIES_CONF_H
+#define UTILITIES_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "cmsis_compiler.h"
+#include "string.h"
+
+/******************************************************************************
+ * common
+ ******************************************************************************/
+#define UTILS_ENTER_CRITICAL_SECTION( )   uint32_t primask_bit = __get_PRIMASK( );\
+                                          __disable_irq( )
+
+#define UTILS_EXIT_CRITICAL_SECTION( )          __set_PRIMASK( primask_bit )
+
+#define UTILS_MEMSET8( dest, value, size )      memset( dest, value, size);
+
+/******************************************************************************
+ * tiny low power manager
+ * (any macro that does not need to be modified can be removed)
+ ******************************************************************************/
+#define UTIL_LPM_INIT_CRITICAL_SECTION( )
+#define UTIL_LPM_ENTER_CRITICAL_SECTION( )      UTILS_ENTER_CRITICAL_SECTION( )
+#define UTIL_LPM_EXIT_CRITICAL_SECTION( )       UTILS_EXIT_CRITICAL_SECTION( )
+
+/******************************************************************************
+ * sequencer
+ * (any macro that does not need to be modified can be removed)
+ ******************************************************************************/
+#define UTIL_SEQ_INIT_CRITICAL_SECTION( )
+#define UTIL_SEQ_ENTER_CRITICAL_SECTION( )      UTILS_ENTER_CRITICAL_SECTION( )
+#define UTIL_SEQ_EXIT_CRITICAL_SECTION( )       UTILS_EXIT_CRITICAL_SECTION( )
+#define UTIL_SEQ_CONF_TASK_NBR                  (32)
+#define UTIL_SEQ_CONF_PRIO_NBR                  (2)
+#define UTIL_SEQ_MEMSET8( dest, value, size )   UTILS_MEMSET8( dest, value, size )
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*UTILITIES_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/app_debug.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/app_debug.c
new file mode 100644
index 000000000..af3fdfbce
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/app_debug.c
@@ -0,0 +1,360 @@
+/**
+ ******************************************************************************
+ * @file    app_debug.c
+ * @author  MCD Application Team
+ * @brief   Debug capabilities
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+extern void MX_LPUART1_UART_Init(void);
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+extern void MX_USART1_UART_Init(void);
+#endif
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+#if (CFG_HW_USART1_ENABLED == 1)
+    MX_USART1_UART_Init();
+#endif
+#if (CFG_HW_LPUART1_ENABLED == 1)
+    MX_LPUART1_UART_Init();
+#endif
+  return;
+}
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/app_entry.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/app_entry.c
new file mode 100644
index 000000000..52ea9ea05
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/app_entry.c
@@ -0,0 +1,300 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    app_entry.c
+ * @author  MCD Application Team
+ * @brief   Entry point of the Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "main.h"
+#include "app_entry.h"
+#include "app_ble.h"
+#include "ble.h"
+#include "tl.h"
+#include "stm32_seq.h"
+#include "shci_tl.h"
+#include "stm32_lpm.h"
+#include "app_debug.h"
+
+/* Private includes -----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+extern RTC_HandleTypeDef hrtc;
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+#define POOL_SIZE (CFG_TLBLE_EVT_QUEUE_LENGTH*4U*DIVC(( sizeof(TL_PacketHeader_t) + TL_BLE_EVENT_FRAME_SIZE ), 4U))
+
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t EvtPool[POOL_SIZE];
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static TL_CmdPacket_t SystemCmdBuffer;
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t SystemSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255U];
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t BleSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255];
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private functions prototypes-----------------------------------------------*/
+static void SystemPower_Config( void );
+static void appe_Tl_Init( void );
+static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status );
+static void APPE_SysUserEvtRx( void * pPayload );
+
+/* USER CODE BEGIN PFP */
+static void Led_Init( void );
+static void Button_Init( void );
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APPE_Init( void )
+{
+  SystemPower_Config(); /**< Configure the system Power Mode */
+
+  HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
+
+/* USER CODE BEGIN APPE_Init_1 */
+  APPD_Init();
+  
+  /**
+   * The Standby mode should not be entered before the initialization is over
+   * The default state of the Low Power Manager is to allow the Standby Mode so an request is needed here
+   */
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP, UTIL_LPM_DISABLE);
+
+  Led_Init();
+
+  Button_Init();
+/* USER CODE END APPE_Init_1 */
+  appe_Tl_Init();	/* Initialize all transport layers */
+
+  /**
+   * From now, the application is waiting for the ready event ( VS_HCI_C2_Ready )
+   * received on the system channel before starting the Stack
+   * This system event is received with APPE_SysUserEvtRx()
+   */
+/* USER CODE BEGIN APPE_Init_2 */
+
+/* USER CODE END APPE_Init_2 */
+   return;
+}
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+ * @brief  Configure the system for power optimization
+ *
+ * @note  This API configures the system to be ready for low power mode
+ *
+ * @param  None
+ * @retval None
+ */
+static void SystemPower_Config( void )
+{
+
+  /**
+   * Select HSI as system clock source after Wake Up from Stop mode
+   */
+  LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
+
+  /* Initialize low power manager */
+  UTIL_LPM_Init( );
+
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+  /**
+   *  Enable USB power
+   */
+  HAL_PWREx_EnableVddUSB();
+#endif
+
+  return;
+}
+
+static void appe_Tl_Init( void )
+{
+  TL_MM_Config_t tl_mm_config;
+  SHCI_TL_HciInitConf_t SHci_Tl_Init_Conf;
+  /**< Reference table initialization */
+  TL_Init();
+
+  /**< System channel initialization */
+  UTIL_SEQ_RegTask( 1<< CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID, UTIL_SEQ_RFU, shci_user_evt_proc );
+  SHci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&SystemCmdBuffer;
+  SHci_Tl_Init_Conf.StatusNotCallBack = APPE_SysStatusNot;
+  shci_init(APPE_SysUserEvtRx, (void*) &SHci_Tl_Init_Conf);
+
+  /**< Memory Manager channel initialization */
+  tl_mm_config.p_BleSpareEvtBuffer = BleSpareEvtBuffer;
+  tl_mm_config.p_SystemSpareEvtBuffer = SystemSpareEvtBuffer;
+  tl_mm_config.p_AsynchEvtPool = EvtPool;
+  tl_mm_config.AsynchEvtPoolSize = POOL_SIZE;
+  TL_MM_Init( &tl_mm_config );
+
+  TL_Enable();
+
+  return;
+}
+
+static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status )
+{
+  UNUSED(status);
+  return;
+}
+
+/**
+ * The type of the payload for a system user event is tSHCI_UserEvtRxParam
+ * When the system event is both :
+ *    - a ready event (subevtcode = SHCI_SUB_EVT_CODE_READY)
+ *    - reported by the FUS (sysevt_ready_rsp == RSS_FW_RUNNING)
+ * The buffer shall not be released
+ * ( eg ((tSHCI_UserEvtRxParam*)pPayload)->status shall be set to SHCI_TL_UserEventFlow_Disable )
+ * When the status is not filled, the buffer is released by default
+ */
+static void APPE_SysUserEvtRx( void * pPayload )
+{
+  UNUSED(pPayload);
+  /* Traces channel initialization */
+  APPD_EnableCPU2();
+
+  APP_BLE_Init( );
+  UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE);
+  return;
+}
+
+/* USER CODE BEGIN FD_LOCAL_FUNCTIONS */
+static void Led_Init( void )
+{
+#if (CFG_LED_SUPPORTED == 1)
+  /**
+   * Leds Initialization
+   */
+
+  BSP_LED_Init(LED_BLUE);
+  BSP_LED_Init(LED_GREEN);
+  BSP_LED_Init(LED_RED);
+
+  BSP_LED_On(LED_GREEN);
+#endif
+
+  return;
+}
+
+static void Button_Init( void )
+{
+#if (CFG_BUTTON_SUPPORTED == 1)
+  /**
+   * Button Initialization
+   */
+
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+  BSP_PB_Init(BUTTON_SW2, BUTTON_MODE_EXTI);
+#endif
+
+  return;
+}
+/* USER CODE END FD_LOCAL_FUNCTIONS */
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+
+void UTIL_SEQ_Idle( void )
+{
+#if ( CFG_LPM_SUPPORTED == 1)
+  UTIL_LPM_EnterLowPower( );
+#endif
+  return;
+}
+
+/**
+  * @brief  This function is called by the scheduler each time an event
+  *         is pending.
+  *
+  * @param  evt_waited_bm : Event pending.
+  * @retval None
+  */
+void UTIL_SEQ_EvtIdle( UTIL_SEQ_bm_t task_id_bm, UTIL_SEQ_bm_t evt_waited_bm )
+{
+  UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+}
+
+void shci_notify_asynch_evt(void* pdata)
+{
+  UTIL_SEQ_SetTask( 1<
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "hw_conf.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef enum
+{
+  TimerID_Free,
+  TimerID_Created,
+  TimerID_Running
+}TimerIDStatus_t;
+
+typedef enum
+{
+  SSR_Read_Requested,
+  SSR_Read_Not_Requested
+}RequestReadSSR_t;
+
+typedef enum
+{
+  WakeupTimerValue_Overpassed,
+  WakeupTimerValue_LargeEnough
+}WakeupTimerLimitation_Status_t;
+
+typedef struct
+{
+  HW_TS_pTimerCb_t  pTimerCallBack;
+  uint32_t        CounterInit;
+  uint32_t        CountLeft;
+  TimerIDStatus_t     TimerIDStatus;
+  HW_TS_Mode_t   TimerMode;
+  uint32_t        TimerProcessID;
+  uint8_t         PreviousID;
+  uint8_t         NextID;
+}TimerContext_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define SSR_FORBIDDEN_VALUE   0xFFFFFFFF
+#define TIMER_LIST_EMPTY      0xFFFF
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/**
+ * START of Section TIMERSERVER_CONTEXT
+ */
+
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile TimerContext_t aTimerContext[CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER];
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint8_t CurrentRunningTimerID;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint8_t PreviousRunningTimerID;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint32_t SSRValueOnLastSetup;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile WakeupTimerLimitation_Status_t  WakeupTimerLimitation;
+
+/**
+ * END of Section TIMERSERVER_CONTEXT
+ */
+
+static RTC_HandleTypeDef *phrtc;  /**< RTC handle */
+static uint8_t  WakeupTimerDivider;
+static uint8_t  AsynchPrescalerUserConfig;
+static uint16_t SynchPrescalerUserConfig;
+static volatile uint16_t MaxWakeupTimerSetup;
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void RestartWakeupCounter(uint16_t Value);
+static uint16_t ReturnTimeElapsed(void);
+static void RescheduleTimerList(void);
+static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR);
+static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID);
+static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID);
+static uint16_t linkTimer(uint8_t TimerID);
+static uint32_t ReadRtcSsrValue(void);
+
+__weak void HW_TS_RTC_CountUpdated_AppNot(void);
+
+/* Functions Definition ------------------------------------------------------*/
+
+/**
+ * @brief  Read the RTC_SSR value
+ *         As described in the reference manual, the RTC_SSR shall be read twice to ensure
+ *         reliability of the value
+ * @param  None
+ * @retval SSR value read
+ */
+static uint32_t ReadRtcSsrValue(void)
+{
+  uint32_t first_read;
+  uint32_t second_read;
+
+  first_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+
+  second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+
+  while(first_read != second_read)
+  {
+    first_read = second_read;
+
+    second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+  }
+
+  return second_read;
+}
+
+/**
+ * @brief  Insert a Timer in the list after the Timer ID specified
+ * @param  TimerID:   The ID of the Timer
+ * @param  RefTimerID: The ID of the Timer to be linked after
+ * @retval None
+ */
+static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID)
+{
+  uint8_t next_id;
+
+  next_id = aTimerContext[RefTimerID].NextID;
+
+  if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    aTimerContext[next_id].PreviousID = TimerID;
+  }
+  aTimerContext[TimerID].NextID = next_id;
+  aTimerContext[TimerID].PreviousID = RefTimerID ;
+  aTimerContext[RefTimerID].NextID = TimerID;
+
+  return;
+}
+
+/**
+ * @brief  Insert a Timer in the list before the ID specified
+ * @param  TimerID:   The ID of the Timer
+ * @param  RefTimerID: The ID of the Timer to be linked before
+ * @retval None
+ */
+static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID)
+{
+  uint8_t previous_id;
+
+  if(RefTimerID != CurrentRunningTimerID)
+  {
+    previous_id = aTimerContext[RefTimerID].PreviousID;
+
+    aTimerContext[previous_id].NextID = TimerID;
+    aTimerContext[TimerID].NextID = RefTimerID;
+    aTimerContext[TimerID].PreviousID = previous_id ;
+    aTimerContext[RefTimerID].PreviousID = TimerID;
+  }
+  else
+  {
+    aTimerContext[TimerID].NextID = RefTimerID;
+    aTimerContext[RefTimerID].PreviousID = TimerID;
+  }
+
+  return;
+}
+
+/**
+ * @brief  Insert a Timer in the list
+ * @param  TimerID:   The ID of the Timer
+ * @retval None
+ */
+static uint16_t linkTimer(uint8_t TimerID)
+{
+  uint32_t time_left;
+  uint16_t time_elapsed;
+  uint8_t timer_id_lookup;
+  uint8_t next_id;
+
+  if(CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    /**
+     * No timer in the list
+     */
+    PreviousRunningTimerID = CurrentRunningTimerID;
+    CurrentRunningTimerID = TimerID;
+    aTimerContext[TimerID].NextID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;
+
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+    time_elapsed = 0;
+  }
+  else
+  {
+    time_elapsed = ReturnTimeElapsed();
+
+    /**
+     * update count of the timer to be linked
+     */
+    aTimerContext[TimerID].CountLeft += time_elapsed;
+    time_left = aTimerContext[TimerID].CountLeft;
+
+    /**
+     * Search for index where the new timer shall be linked
+     */
+    if(aTimerContext[CurrentRunningTimerID].CountLeft <= time_left)
+    {
+      /**
+       * Search for the ID after the first one
+       */
+      timer_id_lookup = CurrentRunningTimerID;
+      next_id = aTimerContext[timer_id_lookup].NextID;
+      while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left))
+      {
+        timer_id_lookup = aTimerContext[timer_id_lookup].NextID;
+        next_id = aTimerContext[timer_id_lookup].NextID;
+      }
+
+      /**
+       * Link after the ID
+       */
+      LinkTimerAfter(TimerID, timer_id_lookup);
+    }
+    else
+    {
+      /**
+       * Link before the first ID
+       */
+      LinkTimerBefore(TimerID, CurrentRunningTimerID);
+      PreviousRunningTimerID = CurrentRunningTimerID;
+      CurrentRunningTimerID = TimerID;
+    }
+  }
+
+  return time_elapsed;
+}
+
+/**
+ * @brief  Remove a Timer from the list
+ * @param  TimerID:   The ID of the Timer
+ * @param  RequestReadSSR: Request to read the SSR register or not
+ * @retval None
+ */
+static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR)
+{
+  uint8_t previous_id;
+  uint8_t next_id;
+
+  if(TimerID == CurrentRunningTimerID)
+  {
+    PreviousRunningTimerID = CurrentRunningTimerID;
+    CurrentRunningTimerID = aTimerContext[TimerID].NextID;
+  }
+  else
+  {
+    previous_id = aTimerContext[TimerID].PreviousID;
+    next_id = aTimerContext[TimerID].NextID;
+
+    aTimerContext[previous_id].NextID = aTimerContext[TimerID].NextID;
+    if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+    {
+      aTimerContext[next_id].PreviousID = aTimerContext[TimerID].PreviousID;
+    }
+  }
+
+  /**
+   * Timer is out of the list
+   */
+  aTimerContext[TimerID].TimerIDStatus = TimerID_Created;
+
+  if((CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (RequestReadSSR == SSR_Read_Requested))
+  {
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+  }
+
+  return;
+}
+
+/**
+ * @brief  Return the number of ticks counted by the wakeuptimer since it has been started
+ * @note  The API is reading the SSR register to get how many ticks have been counted
+ *        since the time the timer has been started
+ * @param  None
+ * @retval Time expired in Ticks
+ */
+static uint16_t ReturnTimeElapsed(void)
+{
+  uint32_t  return_value;
+  uint32_t  wrap_counter;
+
+  if(SSRValueOnLastSetup != SSR_FORBIDDEN_VALUE)
+  {
+    return_value = ReadRtcSsrValue(); /**< Read SSR register first */
+
+    if (SSRValueOnLastSetup >= return_value)
+    {
+      return_value = SSRValueOnLastSetup - return_value;
+    }
+    else
+    {
+      wrap_counter = SynchPrescalerUserConfig - return_value;
+      return_value = SSRValueOnLastSetup + wrap_counter;
+    }
+
+    /**
+     * At this stage, ReturnValue holds the number of ticks counted by SSR
+     * Need to translate in number of ticks counted by the Wakeuptimer
+     */
+    return_value = return_value*AsynchPrescalerUserConfig;
+    return_value = return_value >> WakeupTimerDivider;
+  }
+  else
+  {
+    return_value = 0;
+  }
+
+  return (uint16_t)return_value;
+}
+
+/**
+ * @brief  Set the wakeup counter
+ * @note  The API is writing the counter value so that the value is decreased by one to cope with the fact
+ *    the interrupt is generated with 1 extra clock cycle (See RefManuel)
+ *    It assumes all condition are met to be allowed to write the wakeup counter
+ * @param  Value: Value to be written in the counter
+ * @retval None
+ */
+static void RestartWakeupCounter(uint16_t Value)
+{
+  /**
+   * The wakeuptimer has been disabled in the calling function to reduce the time to poll the WUTWF
+   * FLAG when the new value will have to be written
+   *  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);
+   */
+
+  if(Value == 0)
+  {
+    SSRValueOnLastSetup = ReadRtcSsrValue();
+
+    /**
+     * Simulate that the Timer expired
+     */
+    HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
+  }
+  else
+  {
+    if((Value > 1) ||(WakeupTimerDivider != 1))
+    {
+      Value -= 1;
+    }
+
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+    /**
+     * make sure to clear the flags after checking the WUTWF.
+     * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+     * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+     * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+     * due to the autoreload feature
+     */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+    HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);   /**<  Clear pending bit in NVIC */
+
+    MODIFY_REG(RTC->WUTR, RTC_WUTR_WUT, Value);
+
+    /**
+     * Update the value here after the WUTWF polling that may take some time
+     */
+    SSRValueOnLastSetup = ReadRtcSsrValue();
+
+    __HAL_RTC_WAKEUPTIMER_ENABLE(phrtc);    /**<  Enable the Wakeup Timer */
+
+    HW_TS_RTC_CountUpdated_AppNot();
+  }
+
+  return ;
+}
+
+/**
+ * @brief  Reschedule the list of timer
+ * @note  1) Update the count left for each timer in the list
+ *    2) Setup the wakeuptimer
+ * @param  None
+ * @retval None
+ */
+static void RescheduleTimerList(void)
+{
+  uint8_t   localTimerID;
+  uint32_t  timecountleft;
+  uint16_t  wakeup_timer_value;
+  uint16_t  time_elapsed;
+
+  /**
+   * The wakeuptimer is disabled now to reduce the time to poll the WUTWF
+   * FLAG when the new value will have to be written
+   */
+  if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+  {
+    /**
+     * Wait for the flag to be back to 0 when the wakeup timer is enabled
+     */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == SET);
+  }
+  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);   /**<  Disable the Wakeup Timer */
+
+  localTimerID = CurrentRunningTimerID;
+
+  /**
+   * Calculate what will be the value to write in the wakeuptimer
+   */
+  timecountleft = aTimerContext[localTimerID].CountLeft;
+
+  /**
+   * Read how much has been counted
+   */
+  time_elapsed = ReturnTimeElapsed();
+
+  if(timecountleft < time_elapsed )
+  {
+    /**
+     * There is no tick left to count
+     */
+    wakeup_timer_value = 0;
+    WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+  }
+  else
+  {
+    if(timecountleft > (time_elapsed + MaxWakeupTimerSetup))
+    {
+      /**
+       * The number of tick left is greater than the Wakeuptimer maximum value
+       */
+      wakeup_timer_value = MaxWakeupTimerSetup;
+
+      WakeupTimerLimitation = WakeupTimerValue_Overpassed;
+    }
+    else
+    {
+      wakeup_timer_value = timecountleft - time_elapsed;
+      WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+    }
+
+  }
+
+  /**
+   * update ticks left to be counted for each timer
+   */
+  while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    if (aTimerContext[localTimerID].CountLeft < time_elapsed)
+    {
+      aTimerContext[localTimerID].CountLeft = 0;
+    }
+    else
+    {
+      aTimerContext[localTimerID].CountLeft -= time_elapsed;
+    }
+    localTimerID = aTimerContext[localTimerID].NextID;
+  }
+
+  /**
+   * Write next count
+   */
+  RestartWakeupCounter(wakeup_timer_value);
+
+  return ;
+}
+
+/* Public functions ----------------------------------------------------------*/
+
+/**
+ * For all public interface except that may need write access to the RTC, the RTC
+ * shall be unlock at the beginning and locked at the output
+ * In order to ease maintainability, the unlock is done at the top and the lock at then end
+ * in case some new implementation is coming in the future
+ */
+
+void HW_TS_RTC_Wakeup_Handler(void)
+{
+  HW_TS_pTimerCb_t ptimer_callback;
+  uint32_t timer_process_id;
+  uint8_t local_current_running_timer_id;
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  /**
+   * Disable the Wakeup Timer
+   * This may speed up a bit the processing to wait the timer to be disabled
+   * The timer is still counting 2 RTCCLK
+   */
+  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);
+
+  local_current_running_timer_id = CurrentRunningTimerID;
+
+  if(aTimerContext[local_current_running_timer_id].TimerIDStatus == TimerID_Running)
+  {
+    ptimer_callback = aTimerContext[local_current_running_timer_id].pTimerCallBack;
+    timer_process_id = aTimerContext[local_current_running_timer_id].TimerProcessID;
+
+    /**
+     * It should be good to check whether the TimeElapsed is greater or not than the tick left to be counted
+     * However, due to the inaccuracy of the reading of the time elapsed, it may return there is 1 tick
+     * to be left whereas the count is over
+     * A more secure implementation has been done with a flag to state whereas the full count has been written
+     * in the wakeuptimer or not
+     */
+    if(WakeupTimerLimitation != WakeupTimerValue_Overpassed)
+    {
+      if(aTimerContext[local_current_running_timer_id].TimerMode == hw_ts_Repeated)
+      {
+        UnlinkTimer(local_current_running_timer_id, SSR_Read_Not_Requested);
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+        __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+        HW_TS_Start(local_current_running_timer_id, aTimerContext[local_current_running_timer_id].CounterInit);
+
+        /* Disable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+      }
+      else
+      {
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+        __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+        HW_TS_Stop(local_current_running_timer_id);
+
+        /* Disable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+      }
+
+      HW_TS_RTC_Int_AppNot(timer_process_id, local_current_running_timer_id, ptimer_callback);
+    }
+    else
+    {
+      RescheduleTimerList();
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+      __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+    }
+  }
+  else
+  {
+    /**
+     * We should never end up in this case
+     * However, if due to any bug in the timer server this is the case, the mistake may not impact the user.
+     * We could just clean the interrupt flag and get out from this unexpected interrupt
+     */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+    /**
+     * make sure to clear the flags after checking the WUTWF.
+     * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+     * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+     * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+     * due to the autoreload feature
+     */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  return;
+}
+
+void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *hrtc)
+{
+  uint8_t loop;
+  uint32_t localmaxwakeuptimersetup;
+
+  /**
+   * Get RTC handler
+   */
+  phrtc = hrtc;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
+
+  /**
+   * Readout the user config
+   */
+  WakeupTimerDivider = (4 - ((uint32_t)(READ_BIT(RTC->CR, RTC_CR_WUCKSEL))));
+
+  AsynchPrescalerUserConfig = (uint8_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_A) >> (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)) + 1;
+
+  SynchPrescalerUserConfig = (uint16_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_S)) + 1;
+
+  /**
+   *  Margin is taken to avoid wrong calculation when the wrap around is there and some
+   *  application interrupts may have delayed the reading
+   */
+  localmaxwakeuptimersetup = ((((SynchPrescalerUserConfig - 1)*AsynchPrescalerUserConfig) - CFG_HW_TS_RTC_HANDLER_MAX_DELAY) >> WakeupTimerDivider);
+
+  if(localmaxwakeuptimersetup >= 0xFFFF)
+  {
+    MaxWakeupTimerSetup = 0xFFFF;
+  }
+  else
+  {
+    MaxWakeupTimerSetup = (uint16_t)localmaxwakeuptimersetup;
+  }
+
+  /**
+   * Configure EXTI module
+   */
+  LL_EXTI_EnableRisingTrig_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+  LL_EXTI_EnableIT_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+
+  if(TimerInitMode == hw_ts_InitMode_Full)
+  {
+    WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+
+    /**
+     * Initialize the timer server
+     */
+    for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++)
+    {
+      aTimerContext[loop].TimerIDStatus = TimerID_Free;
+    }
+
+    CurrentRunningTimerID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;   /**<  Set ID to non valid value */
+
+    __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);                       /**<  Disable the Wakeup Timer */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);     /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module  */
+    HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);       /**<  Clear pending bit in NVIC  */
+    __HAL_RTC_WAKEUPTIMER_ENABLE_IT(phrtc, RTC_IT_WUT);         /**<  Enable interrupt in RTC module  */
+  }
+  else
+  {
+    if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTF) != RESET)
+    {
+      /**
+       * Simulate that the Timer expired
+       */
+      HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_SetPriority(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO);   /**<  Set NVIC priority */
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+  return;
+}
+
+HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pftimeout_handler)
+{
+  HW_TS_ReturnStatus_t localreturnstatus;
+  uint8_t loop = 0;
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  while((loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[loop].TimerIDStatus != TimerID_Free))
+  {
+    loop++;
+  }
+
+  if(loop != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    aTimerContext[loop].TimerIDStatus = TimerID_Created;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+    aTimerContext[loop].TimerProcessID = TimerProcessID;
+    aTimerContext[loop].TimerMode = TimerMode;
+    aTimerContext[loop].pTimerCallBack = pftimeout_handler;
+    *pTimerId = loop;
+
+    localreturnstatus = hw_ts_Successful;
+  }
+  else
+  {
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+    localreturnstatus = hw_ts_Failed;
+  }
+
+  return(localreturnstatus);
+}
+
+void HW_TS_Delete(uint8_t timer_id)
+{
+  HW_TS_Stop(timer_id);
+
+  aTimerContext[timer_id].TimerIDStatus = TimerID_Free; /**<  release ID */
+
+  return;
+}
+
+void HW_TS_Stop(uint8_t timer_id)
+{
+  uint8_t localcurrentrunningtimerid;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);    /**<  Disable NVIC */
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
+  {
+    UnlinkTimer(timer_id, SSR_Read_Requested);
+    localcurrentrunningtimerid = CurrentRunningTimerID;
+
+    if(localcurrentrunningtimerid == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+    {
+      /**
+       * List is empty
+       */
+
+      /**
+       * Disable the timer
+       */
+      if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+      {
+        /**
+         * Wait for the flag to be back to 0 when the wakeup timer is enabled
+         */
+        while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == SET);
+      }
+      __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);   /**<  Disable the Wakeup Timer */
+
+      while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+      /**
+       * make sure to clear the flags after checking the WUTWF.
+       * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+       * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+       * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+       * due to the autoreload feature
+       */
+      __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+      __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+      HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);   /**<  Clear pending bit in NVIC */
+    }
+    else if(PreviousRunningTimerID != localcurrentrunningtimerid)
+    {
+      RescheduleTimerList();
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+  return;
+}
+
+void HW_TS_Start(uint8_t timer_id, uint32_t timeout_ticks)
+{
+  uint16_t time_elapsed;
+  uint8_t localcurrentrunningtimerid;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+  if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
+  {
+    HW_TS_Stop( timer_id );
+  }
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);    /**<  Disable NVIC */
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  aTimerContext[timer_id].TimerIDStatus = TimerID_Running;
+
+  aTimerContext[timer_id].CountLeft = timeout_ticks;
+  aTimerContext[timer_id].CounterInit = timeout_ticks;
+
+  time_elapsed =  linkTimer(timer_id);
+
+  localcurrentrunningtimerid = CurrentRunningTimerID;
+
+  if(PreviousRunningTimerID != localcurrentrunningtimerid)
+  {
+    RescheduleTimerList();
+  }
+  else
+  {
+    aTimerContext[timer_id].CountLeft -= time_elapsed;
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+  return;
+}
+
+uint16_t HW_TS_RTC_ReadLeftTicksToCount(void)
+{
+  uint32_t primask_bit;
+  uint16_t return_value, auro_reload_value, elapsed_time_value;
+
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();                /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+
+  if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+  {
+    auro_reload_value = (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT));
+
+    elapsed_time_value = ReturnTimeElapsed();
+
+    if(auro_reload_value > elapsed_time_value)
+    {
+      return_value = auro_reload_value - elapsed_time_value;
+    }
+    else
+    {
+      return_value = 0;
+    }
+  }
+  else
+  {
+    return_value = TIMER_LIST_EMPTY;
+  }
+
+  __set_PRIMASK(primask_bit);     /**< Restore PRIMASK bit*/
+
+  return (return_value);
+}
+
+__weak void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack)
+{
+  pTimerCallBack();
+
+  return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/hw_uart.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/hw_uart.c
new file mode 100644
index 000000000..9a553610d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/hw_uart.c
@@ -0,0 +1,318 @@
+/**
+ ******************************************************************************
+  * File Name          : Src/hw_uart.c
+  * Description        : HW UART source file for STM32WPAN Middleware.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "hw_conf.h"
+#if (CFG_HW_LPUART1_ENABLED == 1)
+extern UART_HandleTypeDef hlpuart1;
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+extern UART_HandleTypeDef huart1;
+#endif
+
+/* Macros --------------------------------------------------------------------*/
+#define HW_UART_RX_IT(__HANDLE__, __USART_BASE__)                                                   \
+        do{                                                                                         \
+            HW_##__HANDLE__##RxCb = cb;                                                             \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            HAL_UART_Receive_IT(&(__HANDLE__), p_data, size);                                       \
+        } while(0)
+
+#define HW_UART_TX_IT(__HANDLE__, __USART_BASE__)                                                   \
+        do{                                                                                         \
+            HW_##__HANDLE__##TxCb = cb;                                                             \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            HAL_UART_Transmit_IT(&(__HANDLE__), p_data, size);                                      \
+        } while(0)
+
+#define HW_UART_TX(__HANDLE__, __USART_BASE__)                                                      \
+        do{                                                                                         \
+            (__HANDLE__).Instance = (__USART_BASE__);                                               \
+            hal_status = HAL_UART_Transmit(&(__HANDLE__), p_data, size, timeout);                   \
+        } while(0)
+
+/* Variables -----------------------------------------------------------------*/
+#if (CFG_HW_USART1_ENABLED == 1)
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+    DMA_HandleTypeDef HW_hdma_huart1_tx ={0};
+#endif
+    void (*HW_huart1RxCb)(void);
+    void (*HW_huart1TxCb)(void);
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+    DMA_HandleTypeDef HW_hdma_hlpuart1_tx ={0};
+#endif
+    void (*HW_hlpuart1RxCb)(void);
+    void (*HW_hlpuart1TxCb)(void);
+#endif
+
+void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_RX_IT(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_RX_IT(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  void (*cb)(void))
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_TX_IT(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_TX_IT(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout)
+{
+    HAL_StatusTypeDef hal_status = HAL_OK;
+    hw_status_t hw_status = hw_uart_ok;
+
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_UART_TX(huart1, USART1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_UART_TX(hlpuart1, LPUART1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    switch (hal_status)
+    {
+        case HAL_OK:
+            hw_status = hw_uart_ok;
+            break;
+
+        case HAL_ERROR:
+            hw_status = hw_uart_error;
+            break;
+
+        case HAL_BUSY:
+            hw_status = hw_uart_busy;
+            break;
+
+        case HAL_TIMEOUT:
+            hw_status = hw_uart_to;
+            break;
+
+        default:
+            break;
+    }
+
+    return hw_status;
+}
+
+hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+{
+    HAL_StatusTypeDef hal_status = HAL_OK;
+    hw_status_t hw_status = hw_uart_ok;
+
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_huart1TxCb = cb;
+            huart1.Instance = USART1;
+            hal_status = HAL_UART_Transmit_DMA(&huart1, p_data, size);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HW_hlpuart1TxCb = cb;
+            hlpuart1.Instance = LPUART1;
+            hal_status = HAL_UART_Transmit_DMA(&hlpuart1, p_data, size);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    switch (hal_status)
+    {
+        case HAL_OK:
+            hw_status = hw_uart_ok;
+            break;
+
+        case HAL_ERROR:
+            hw_status = hw_uart_error;
+            break;
+
+        case HAL_BUSY:
+            hw_status = hw_uart_busy;
+            break;
+
+        case HAL_TIMEOUT:
+            hw_status = hw_uart_to;
+            break;
+
+        default:
+            break;
+    }
+
+    return hw_status;
+}
+
+void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HAL_UART_IRQHandler(&huart1);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case hw_lpuart1:
+            HAL_UART_IRQHandler(&hlpuart1);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+{
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+        case hw_uart1:
+            HAL_DMA_IRQHandler(huart1.hdmatx);
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+        case hw_lpuart1:
+            HAL_DMA_IRQHandler(hlpuart1.hdmatx);
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+    switch ((uint32_t)huart->Instance)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case (uint32_t)USART1:
+            if(HW_huart1RxCb)
+            {
+                HW_huart1RxCb();
+            }
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case (uint32_t)LPUART1:
+            if(HW_hlpuart1RxCb)
+            {
+                HW_hlpuart1RxCb();
+            }
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+    switch ((uint32_t)huart->Instance)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case (uint32_t)USART1:
+            if(HW_huart1TxCb)
+            {
+                HW_huart1TxCb();
+            }
+            break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+        case (uint32_t)LPUART1:
+            if(HW_hlpuart1TxCb)
+            {
+                HW_hlpuart1TxCb();
+            }
+            break;
+#endif
+
+        default:
+            break;
+    }
+
+    return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/main.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/main.c
new file mode 100644
index 000000000..b4c3d4dd6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/main.c
@@ -0,0 +1,641 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    main.c
+ * @author  MCD Application Team
+ * @brief   BLE application with BLE core
+ *
+  @verbatim
+  ==============================================================================
+                    ##### IMPORTANT NOTE #####
+  ==============================================================================
+
+  This application requests having the stm32wb5x_BLE_Stack_fw.bin binary
+  flashed on the Wireless Coprocessor.
+  If it is not the case, you need to use STM32CubeProgrammer to load the appropriate
+  binary.
+
+  All available binaries are located under following directory:
+  /Projects/STM32_Copro_Wireless_Binaries
+
+  Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+  Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the
+  detailed procedure to change the Wireless Coprocessor binary.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "app_entry.h"
+#include "app_common.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "stm32_lpm.h"
+#include "stm32_seq.h"
+#include "dbg_trace.h"
+#include "hw_conf.h"
+#include "otp.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef hlpuart1;
+UART_HandleTypeDef huart1;
+DMA_HandleTypeDef hdma_lpuart1_tx;
+DMA_HandleTypeDef hdma_usart1_tx;
+
+RTC_HandleTypeDef hrtc;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+void MX_LPUART1_UART_Init(void);
+void MX_USART1_UART_Init(void);
+static void MX_RF_Init(void);
+static void MX_RTC_Init(void);
+/* USER CODE BEGIN PFP */
+void PeriphClock_Config(void);
+static void Reset_Device( void );
+static void Reset_IPCC( void );
+static void Reset_BackupDomain( void );
+static void Init_Exti( void );
+static void Config_HSE(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+  
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+  Reset_Device();
+  Config_HSE();
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  PeriphClock_Config();
+  Init_Exti(); /**< Configure the system Power Mode */
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_RF_Init();
+  MX_RTC_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Init code for STM32_WPAN */  
+  APPE_Init();
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+	while(1)
+	{
+		UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure LSE Drive Capability 
+  */
+  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE
+                              |RCC_OSCILLATORTYPE_LSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RFWAKEUP
+                              |RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1
+                              |RCC_PERIPHCLK_LPUART1;
+  PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+  PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* USER CODE BEGIN Smps */
+
+#if (CFG_USE_SMPS != 0)
+  /**
+   *  Configure and enable SMPS
+   *
+   *  The SMPS configuration is not yet supported by CubeMx
+   */
+  LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
+  LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
+  LL_PWR_SMPS_Enable();
+#endif
+
+  /* USER CODE END Smps */
+
+
+}
+
+/**
+  * @brief LPUART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+void MX_LPUART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN LPUART1_Init 0 */
+
+  /* USER CODE END LPUART1_Init 0 */
+
+  /* USER CODE BEGIN LPUART1_Init 1 */
+
+  /* USER CODE END LPUART1_Init 1 */
+  hlpuart1.Instance = LPUART1;
+  hlpuart1.Init.BaudRate = 115200;
+  hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
+  hlpuart1.Init.StopBits = UART_STOPBITS_1;
+  hlpuart1.Init.Parity = UART_PARITY_NONE;
+  hlpuart1.Init.Mode = UART_MODE_TX_RX;
+  hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  hlpuart1.FifoMode = UART_FIFOMODE_DISABLE;
+  if (HAL_UART_Init(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN LPUART1_Init 2 */
+
+  /* USER CODE END LPUART1_Init 2 */
+
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_8;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+  * @brief RF Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RF_Init(void)
+{
+
+  /* USER CODE BEGIN RF_Init 0 */
+
+  /* USER CODE END RF_Init 0 */
+
+  /* USER CODE BEGIN RF_Init 1 */
+
+  /* USER CODE END RF_Init 1 */
+  /* USER CODE BEGIN RF_Init 2 */
+
+  /* USER CODE END RF_Init 2 */
+
+}
+
+/**
+  * @brief RTC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RTC_Init(void)
+{
+
+  /* USER CODE BEGIN RTC_Init 0 */
+
+  /* USER CODE END RTC_Init 0 */
+
+  /* USER CODE BEGIN RTC_Init 1 */
+
+  /* USER CODE END RTC_Init 1 */
+  /** Initialize RTC Only 
+  */
+  hrtc.Instance = RTC;
+  hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
+  hrtc.Init.AsynchPrediv = CFG_RTC_ASYNCH_PRESCALER;
+  hrtc.Init.SynchPrediv = CFG_RTC_SYNCH_PRESCALER;
+  hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
+  hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+  hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+  if (HAL_RTC_Init(&hrtc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN RTC_Init 2 */
+  /* Disable RTC registers write protection */
+  LL_RTC_DisableWriteProtection(RTC);
+
+  LL_RTC_WAKEUP_SetClock(RTC, CFG_RTC_WUCKSEL_DIVIDER);
+
+  /* Enable RTC registers write protection */
+  LL_RTC_EnableWriteProtection(RTC);
+  /* USER CODE END RTC_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
+  __HAL_RCC_DMA2_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
+  /* DMA2_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA2_Channel4_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(DMA2_Channel4_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+void PeriphClock_Config(void)
+{
+  #if (CFG_USB_INTERFACE_ENABLE != 0)
+	RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
+	RCC_CRSInitTypeDef RCC_CRSInitStruct = { 0 };
+
+    /**
+    * This prevents the CPU2 to disable the HSI48 oscillator when
+    * it does not use anymore the RNG IP
+    */
+    LL_HSEM_1StepLock( HSEM, 5 );
+
+    LL_RCC_HSI48_Enable();
+
+	while(!LL_RCC_HSI48_IsReady());
+
+	/* Select HSI48 as USB clock source */
+	PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+	PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+	HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+	/*Configure the clock recovery system (CRS)**********************************/
+
+	/* Enable CRS Clock */
+	__HAL_RCC_CRS_CLK_ENABLE();
+
+	/* Default Synchro Signal division factor (not divided) */
+	RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+
+	/* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+	RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+
+	/* HSI48 is synchronized with USB SOF at 1KHz rate */
+	RCC_CRSInitStruct.ReloadValue = RCC_CRS_RELOADVALUE_DEFAULT;
+	RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+
+	RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+
+	/* Set the TRIM[5:0] to the default value*/
+	RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+
+	/* Start automatic synchronization */
+	HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+#endif
+
+	return;
+}
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+
+static void Config_HSE(void)
+{
+    OTP_ID0_t * p_otp;
+
+  /**
+   * Read HSE_Tuning from OTP
+   */
+  p_otp = (OTP_ID0_t *) OTP_Read(0);
+  if (p_otp)
+  {
+    LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
+  }
+
+  return;
+}  
+
+
+static void Reset_Device( void )
+{
+#if ( CFG_HW_RESET_BY_FW == 1 )
+	Reset_BackupDomain();
+
+	Reset_IPCC();
+#endif
+
+	return;
+}
+
+static void Reset_IPCC( void )
+{
+	LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
+
+	LL_C1_IPCC_ClearFlag_CHx(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_ClearFlag_CHx(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C1_IPCC_DisableTransmitChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_DisableTransmitChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C1_IPCC_DisableReceiveChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_DisableReceiveChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	return;
+}
+
+static void Reset_BackupDomain( void )
+{
+	if ((LL_RCC_IsActiveFlag_PINRST() != FALSE) && (LL_RCC_IsActiveFlag_SFTRST() == FALSE))
+	{
+		HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+		/**
+		 *  Write twice the value to flush the APB-AHB bridge
+		 *  This bit shall be written in the register before writing the next one
+		 */
+		HAL_PWR_EnableBkUpAccess();
+
+		__HAL_RCC_BACKUPRESET_FORCE();
+		__HAL_RCC_BACKUPRESET_RELEASE();
+	}
+
+	return;
+}
+
+static void Init_Exti( void )
+{
+  /**< Disable all wakeup interrupt on CPU1  except IPCC(36), HSEM(38) */
+  LL_EXTI_DisableIT_0_31(~0);
+  LL_EXTI_DisableIT_32_63( (~0) & (~(LL_EXTI_LINE_36 | LL_EXTI_LINE_38)) );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += HAL_GetTickFreq();
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+  {
+    /************************************************************************************
+     * ENTER SLEEP MODE
+     ***********************************************************************************/
+    LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+    /**
+     * This option is used to ensure that store operations are completed
+     */
+  #if defined ( __CC_ARM)
+    __force_stores();
+  #endif
+
+    __WFI( );
+  }
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/stm32_lpm_if.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/stm32_lpm_if.c
new file mode 100644
index 000000000..1418e0a36
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/stm32_lpm_if.c
@@ -0,0 +1,297 @@
+/* USER CODE BEGIN Header */
+/**
+ ***************************************************************************************
+  * File Name          : stm32_lpm_if.c
+  * Description        : Low layer function to enter/exit low power modes (stop, sleep).
+ ***************************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+  
+/* Includes ------------------------------------------------------------------*/  
+#include "stm32_lpm_if.h"
+#include "stm32_lpm.h"
+#include "app_conf.h"
+/* USER CODE BEGIN include */
+
+/* USER CODE END include */
+
+/* Exported variables --------------------------------------------------------*/
+const struct UTIL_LPM_Driver_s UTIL_PowerDriver = 
+{
+  PWR_EnterSleepMode,
+  PWR_ExitSleepMode,
+  
+  PWR_EnterStopMode,
+  PWR_ExitStopMode, 
+  
+  PWR_EnterOffMode,
+  PWR_ExitOffMode,
+};
+
+/* Private function prototypes -----------------------------------------------*/
+static void Switch_On_HSI( void );
+/* USER CODE BEGIN Private_Function_Prototypes */
+
+/* USER CODE END Private_Function_Prototypes */
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN Private_Typedef */
+
+/* USER CODE END Private_Typedef */
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Private_Define */
+
+/* USER CODE END Private_Define */
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Private_Macro */
+
+/* USER CODE END Private_Macro */
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN Private_Variables */
+
+/* USER CODE END Private_Variables */
+
+/* Functions Definition ------------------------------------------------------*/
+/**
+  * @brief Enters Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_EnterOffMode( void )
+{
+/* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
+  /************************************************************************************
+   * ENTER OFF MODE
+   ***********************************************************************************/
+  /*
+   * There is no risk to clear all the WUF here because in the current implementation, this API is called
+   * in critical section. If an interrupt occurs while in that critical section before that point,
+   * the flag is set and will be cleared here but the system will not enter Off Mode
+   * because an interrupt is pending in the NVIC. The ISR will be executed when moving out
+   * of this critical section
+   */
+  LL_PWR_ClearFlag_WU( );
+
+  LL_PWR_SetPowerMode( LL_PWR_MODE_STANDBY );
+
+  LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores( );
+#endif
+
+  __WFI( );
+/* USER CODE END PWR_EnterOffMode */
+}
+
+/**
+  * @brief Exits Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_ExitOffMode( void )
+{
+/* USER CODE BEGIN PWR_ExitOffMode */
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitOffMode */
+}
+
+/**
+  * @brief Enters Low Power Stop Mode
+  * @note ARM exists the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterStopMode( void )
+{
+/* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
+  /**
+   * This function is called from CRITICAL SECTION
+   */
+  while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
+
+  if ( ! LL_HSEM_1StepLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID ) )
+  {
+    if( LL_PWR_IsActiveFlag_C2DS( ) )
+    {
+      /* Release ENTRY_STOP_MODE semaphore */
+      LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
+
+      /**
+       * The switch on HSI before entering Stop Mode is required on Cut2.0
+       * It is useless from Cut2.1
+       */
+      Switch_On_HSI( );
+    }
+  }
+  else
+  {
+    /**
+     * The switch on HSI before entering Stop Mode is required on Cut2.0
+     * It is useless from Cut2.1
+     */
+    Switch_On_HSI( );
+  }
+
+  /* Release RCC semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  /************************************************************************************
+   * ENTER STOP MODE
+   ***********************************************************************************/
+  LL_PWR_SetPowerMode( LL_PWR_MODE_STOP2 );
+
+  LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores( );
+#endif
+
+  __WFI();
+/* USER CODE END PWR_EnterStopMode */
+}
+
+/**
+  * @brief Exits Low Power Stop Mode
+  * @note Enable the pll at 32MHz
+  * @param none
+  * @retval none
+  */
+void PWR_ExitStopMode( void )
+{
+/* USER CODE BEGIN PWR_ExitStopMode */
+  /**
+   * This function is called from CRITICAL SECTION
+   */
+
+  /* Release ENTRY_STOP_MODE semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
+
+  while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
+
+  if(LL_RCC_GetSysClkSource( ) == LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+    LL_RCC_HSE_Enable( );
+    while(!LL_RCC_HSE_IsReady( ));
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
+    while (LL_RCC_GetSysClkSource( ) != LL_RCC_SYS_CLKSOURCE_STATUS_HSE);
+  }
+  else
+  {
+    /**
+     * As long as the current application is fine with HSE as system clock source,
+     * there is nothing to do here
+     */
+  }
+
+  /* Release RCC semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitStopMode */
+}
+
+/**
+  * @brief Enters Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterSleepMode( void )
+{
+/* USER CODE BEGIN PWR_EnterSleepMode */
+
+  HAL_SuspendTick();
+
+  /************************************************************************************
+   * ENTER SLEEP MODE
+   ***********************************************************************************/
+  LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+
+  __WFI( );
+/* USER CODE END PWR_EnterSleepMode */
+}
+
+/**
+  * @brief Exits Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_ExitSleepMode( void )
+{
+/* USER CODE BEGIN PWR_ExitSleepMode */
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitSleepMode */
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+  * @brief Switch the system clock on HSI
+  * @param none
+  * @retval none
+  */
+static void Switch_On_HSI( void )
+{
+  LL_RCC_HSI_Enable( );
+  while(!LL_RCC_HSI_IsReady( ));
+  LL_RCC_SetSysClkSource( LL_RCC_SYS_CLKSOURCE_HSI );
+  LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSI);
+  while (LL_RCC_GetSysClkSource( ) != LL_RCC_SYS_CLKSOURCE_STATUS_HSI);
+}
+
+/* USER CODE BEGIN Private_Functions */
+
+/* USER CODE END Private_Functions */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..f22ad0f38
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,329 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32wbxx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_lpuart1_tx;
+
+extern DMA_HandleTypeDef hdma_usart1_tx;
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_HSEM_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  HAL_DMA_MuxSyncConfigTypeDef pSyncConfig;
+  if(huart->Instance==LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspInit 0 */
+
+  /* USER CODE END LPUART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_LPUART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**LPUART1 GPIO Configuration    
+    PA2     ------> LPUART1_TX
+    PA3     ------> LPUART1_RX
+    PA6     ------> LPUART1_CTS 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* LPUART1 DMA Init */
+    /* LPUART1_TX Init */
+    hdma_lpuart1_tx.Instance = DMA1_Channel4;
+    hdma_lpuart1_tx.Init.Request = DMA_REQUEST_LPUART1_TX;
+    hdma_lpuart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_lpuart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_lpuart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_lpuart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_lpuart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_lpuart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_lpuart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_lpuart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    pSyncConfig.SyncSignalID = HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT;
+    pSyncConfig.SyncPolarity = HAL_DMAMUX_SYNC_NO_EVENT;
+    pSyncConfig.SyncEnable = DISABLE;
+    pSyncConfig.EventEnable = DISABLE;
+    pSyncConfig.RequestNumber = 1;
+    if (HAL_DMAEx_ConfigMuxSync(&hdma_lpuart1_tx, &pSyncConfig) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmatx,hdma_lpuart1_tx);
+
+    /* LPUART1 interrupt Init */
+    HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(LPUART1_IRQn);
+  /* USER CODE BEGIN LPUART1_MspInit 1 */
+
+  /* USER CODE END LPUART1_MspInit 1 */
+  }
+  else if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspInit 0 */
+
+  /* USER CODE END USART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**USART1 GPIO Configuration    
+    PA11     ------> USART1_CTS
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_11;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* USART1 DMA Init */
+    /* USART1_TX Init */
+    hdma_usart1_tx.Instance = DMA2_Channel4;
+    hdma_usart1_tx.Init.Request = DMA_REQUEST_USART1_TX;
+    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx);
+
+    /* USART1 interrupt Init */
+    HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspInit 1 */
+
+  /* USER CODE END USART1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspDeInit 0 */
+
+  /* USER CODE END LPUART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_LPUART1_CLK_DISABLE();
+  
+    /**LPUART1 GPIO Configuration    
+    PA2     ------> LPUART1_TX
+    PA3     ------> LPUART1_RX
+    PA6     ------> LPUART1_CTS 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_6);
+
+    /* LPUART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmatx);
+
+    /* LPUART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(LPUART1_IRQn);
+  /* USER CODE BEGIN LPUART1_MspDeInit 1 */
+
+  /* USER CODE END LPUART1_MspDeInit 1 */
+  }
+  else if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+  /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+  
+    /**USART1 GPIO Configuration    
+    PA11     ------> USART1_CTS
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11);
+
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
+
+    /* USART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmatx);
+
+    /* USART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+  /* USER CODE END USART1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspInit 0 */
+  HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+  /**
+  *  Write twice the value to flush the APB-AHB bridge
+  *  This bit shall be written in the register before writing the next one
+  */
+  HAL_PWR_EnableBkUpAccess();
+
+  __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); /**< Select LSI as RTC Input */
+  /* USER CODE END RTC_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_RTC_ENABLE();
+  /* USER CODE BEGIN RTC_MspInit 1 */
+  HAL_RTCEx_EnableBypassShadow(hrtc);
+  /* USER CODE END RTC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspDeInit 0 */
+
+  /* USER CODE END RTC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RTC_DISABLE();
+  /* USER CODE BEGIN RTC_MspDeInit 1 */
+
+  /* USER CODE END RTC_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..2a345be14
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/stm32wbxx_it.c
@@ -0,0 +1,304 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_lpuart1_tx;
+extern DMA_HandleTypeDef hdma_usart1_tx;
+extern UART_HandleTypeDef hlpuart1;
+extern UART_HandleTypeDef huart1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles DMA1 channel4 global interrupt.
+  */
+void DMA1_Channel4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_lpuart1_tx);
+  /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel4_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+
+  /* USER CODE END USART1_IRQn 0 */
+  HAL_UART_IRQHandler(&huart1);
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles LPUART1 global interrupt.
+  */
+void LPUART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN LPUART1_IRQn 0 */
+
+  /* USER CODE END LPUART1_IRQn 0 */
+  HAL_UART_IRQHandler(&hlpuart1);
+  /* USER CODE BEGIN LPUART1_IRQn 1 */
+
+  /* USER CODE END LPUART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA2 channel4 global interrupt.
+  */
+void DMA2_Channel4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2_Channel4_IRQn 0 */
+
+  /* USER CODE END DMA2_Channel4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart1_tx);
+  /* USER CODE BEGIN DMA2_Channel4_IRQn 1 */
+
+  /* USER CODE END DMA2_Channel4_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW1_EXTI_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+
+/**
+ * @brief  This function handles External line
+ *         interrupt request.
+ * @param  None
+ * @retval None
+ */
+void PUSH_BUTTON_SW2_EXTI_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW2_PIN);
+}
+
+void RTC_WKUP_IRQHandler(void)
+{
+  HW_TS_RTC_Wakeup_Handler();
+}
+
+void IPCC_C1_TX_IRQHandler(void)
+{
+  HW_IPCC_Tx_Handler();
+
+  return;
+}
+
+void IPCC_C1_RX_IRQHandler(void)
+{
+  HW_IPCC_Rx_Handler();
+  return;
+}
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..733770023
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/Core/Src/system_stm32wbxx.c
@@ -0,0 +1,356 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                        4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+  /**
+   * When the application is expected to be downloaded by OTA, the SCB->VTOR shall not be modified
+   * as it has already been set to the correct value by the BLE_Ota application before jumping
+   * to the current application
+   */
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/BLE_p2pServer_ota.ewd b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/BLE_p2pServer_ota.ewd
new file mode 100644
index 000000000..dde5e64c2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/BLE_p2pServer_ota.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		BLE_p2pServer_ota
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/BLE_p2pServer_ota.ewp b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/BLE_p2pServer_ota.ewp
new file mode 100644
index 000000000..80d29a87d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/BLE_p2pServer_ota.ewp
@@ -0,0 +1,1251 @@
+
+
+    3
+    
+        BLE_p2pServer_ota
+        
+            ARM
+        
+        1
+        
+            General
+            3
+            
+                30
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            ICCARM
+            2
+            
+                34
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            AARM
+            2
+            
+                10
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            OBJCOPY
+            0
+            
+                1
+                1
+                1
+                
+                
+                
+                
+                
+            
+        
+        
+            CUSTOM
+            3
+            
+                
+                
+                0
+            
+        
+        
+            BICOMP
+            0
+            
+        
+        
+            BUILDACTION
+            1
+            
+                
+                
+            
+        
+        
+            ILINK
+            0
+            
+                20
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            IARCHIVE
+            0
+            
+                0
+                1
+                1
+                
+                
+                
+            
+        
+        
+            BILINK
+            0
+            
+        
+    
+    
+        Application
+        
+            EWARM
+            
+                $PROJ_DIR$\startup_stm32wb35xx_cm4.s
+            
+        
+        
+            User
+            
+                Core
+                
+                    $PROJ_DIR$\..\Core\Src\app_entry.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\app_debug.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\hw_timerserver.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\hw_uart.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\main.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\stm32_lpm_if.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\stm32wbxx_hal_msp.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\stm32wbxx_it.c
+                
+            
+            
+                STM32_WPAN
+                
+                    App
+                    
+                        $PROJ_DIR$\..\STM32_WPAN\App\app_ble.c
+                    
+                    
+                        $PROJ_DIR$\..\STM32_WPAN\App\p2p_server_app.c
+                    
+                
+                
+                    Target
+                    
+                        $PROJ_DIR$\..\STM32_WPAN\Target\hw_ipcc.c
+                    
+                
+            
+        
+    
+    
+        Doc
+        
+            $PROJ_DIR$\..\readme.txt
+        
+    
+    
+        Drivers
+        
+            BSP
+            
+                NUCLEO-WB35CE
+                
+                    $PROJ_DIR$\..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE\nucleo_wb35ce.c
+                
+            
+        
+        
+            CMSIS
+            
+                $PROJ_DIR$\..\Core\Src\system_stm32wbxx.c
+            
+        
+        
+            STM32WBxx_HAL_Driver
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_cortex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_gpio.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_hsem.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_ipcc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rtc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rtc_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_uart.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_uart_ex.c
+            
+        
+    
+    
+        Middlewares
+        
+            STM32_WPAN
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_gap_aci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_gatt_aci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_hal_aci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_hci_le.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\auto\ble_l2cap_aci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\dbg_trace.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\hci_tl.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\hci_tl_if.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\core\template\osal.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\otp.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\svc\Src\p2p_stm.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\shci\shci.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\shci_tl.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\shci_tl_if.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\stm_list.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\utilities\stm_queue.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\ble\svc\Src\svc_ctl.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\..\Middlewares\ST\STM32_WPAN\interface\patterns\ble_thread\tl\tl_mbox.c
+            
+        
+    
+    
+        Utilities
+        
+            $PROJ_DIR$\..\..\..\..\..\..\Utilities\lpm\tiny_lpm\stm32_lpm.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\..\..\Utilities\sequencer\stm32_seq.c
+        
+    
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/Project.eww
new file mode 100644
index 000000000..cba60bdfd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\BLE_p2pServer_ota.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/stm32wb35xx_flash_cm4_ota.icf b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/stm32wb35xx_flash_cm4_ota.icf
new file mode 100644
index 000000000..cd8727641
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/EWARM/stm32wb35xx_flash_cm4_ota.icf
@@ -0,0 +1,44 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08007000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08007000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+define region OTA_TAG_region   = mem:[from (__ICFEDIT_region_ROM_start__ + 0x140)   to (__ICFEDIT_region_ROM_start__ + 0x140 + 4)];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+keep { section TAG_OTA_START};
+keep { section TAG_OTA_END };
+place in OTA_TAG_region   { section TAG_OTA_START };
+place in ROM_region   { readonly, last section TAG_OTA_END };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/app_ble.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/app_ble.c
new file mode 100644
index 000000000..27a3dcc39
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/app_ble.c
@@ -0,0 +1,1228 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    app_ble.c
+ * @author  MCD Application Team
+ * @brief   BLE Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+#include "app_common.h"
+
+#include "dbg_trace.h"
+#include "ble.h"
+#include "tl.h"
+#include "app_ble.h"
+
+#include "stm32_seq.h"
+#include "shci.h"
+#include "stm32_lpm.h"
+#include "otp.h"
+#include "p2p_server_app.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+
+/**
+ * security parameters structure
+ */ 
+typedef struct _tSecurityParams
+{
+  /**
+   * IO capability of the device
+   */
+  uint8_t ioCapability;
+
+  /**
+   * Authentication requirement of the device
+   * Man In the Middle protection required?
+   */
+  uint8_t mitm_mode;
+
+  /**
+   * bonding mode of the device
+   */
+  uint8_t bonding_mode;
+
+  /**
+   * Flag to tell whether OOB data has
+   * to be used during the pairing process
+   */
+  uint8_t OOB_Data_Present; 
+
+  /**
+   * OOB data to be used in the pairing process if
+   * OOB_Data_Present is set to TRUE
+   */
+  uint8_t OOB_Data[16]; 
+
+  /**
+   * this variable indicates whether to use a fixed pin
+   * during the pairing process or a passkey has to be
+   * requested to the application during the pairing process
+   * 0 implies use fixed pin and 1 implies request for passkey
+   */
+  uint8_t Use_Fixed_Pin; 
+
+  /**
+   * minimum encryption key size requirement
+   */
+  uint8_t encryptionKeySizeMin;
+
+  /**
+   * maximum encryption key size requirement
+   */
+  uint8_t encryptionKeySizeMax;
+
+  /**
+   * fixed pin to be used in the pairing process if
+   * Use_Fixed_Pin is set to 1
+   */
+  uint32_t Fixed_Pin;
+
+  /**
+   * this flag indicates whether the host has to initiate
+   * the security, wait for pairing or does not have any security
+   * requirements.\n
+   * 0x00 : no security required
+   * 0x01 : host should initiate security by sending the slave security
+   *        request command
+   * 0x02 : host need not send the clave security request but it
+   * has to wait for paiirng to complete before doing any other
+   * processing
+   */
+  uint8_t initiateSecurity;
+}tSecurityParams;
+
+/**
+ * global context
+ * contains the variables common to all 
+ * services
+ */ 
+typedef struct _tBLEProfileGlobalContext
+{
+
+  /**
+   * security requirements of the host
+   */ 
+  tSecurityParams bleSecurityParam;
+
+  /**
+   * gap service handle
+   */
+  uint16_t gapServiceHandle;
+
+  /**
+   * device name characteristic handle
+   */ 
+  uint16_t devNameCharHandle;
+
+  /**
+   * appearance characteristic handle
+   */ 
+  uint16_t appearanceCharHandle;
+
+  /**
+   * connection handle of the current active connection
+   * When not in connection, the handle is set to 0xFFFF
+   */ 
+  uint16_t connectionHandle;
+
+  /**
+   * length of the UUID list to be used while advertising
+   */ 
+  uint8_t advtServUUIDlen;
+
+  /**
+   * the UUID list to be used while advertising
+   */ 
+  uint8_t advtServUUID[100];
+
+}BleGlobalContext_t;
+
+typedef struct
+{
+  BleGlobalContext_t BleApplicationContext_legacy;
+   APP_BLE_ConnStatus_t Device_Connection_Status;
+   /**
+   * ID of the Advertising Timeout
+   */
+   uint8_t Advertising_mgr_timer_Id;
+
+  uint8_t SwitchOffGPIO_timer_Id;
+}BleApplicationContext_t;
+/* USER CODE BEGIN PTD */
+  
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+#define APPBLE_GAP_DEVICE_NAME_LENGTH 7
+#define FAST_ADV_TIMEOUT               (30*1000*1000/CFG_TS_TICK_VAL) /**< 30s */
+#define INITIAL_ADV_TIMEOUT            (60*1000*1000/CFG_TS_TICK_VAL) /**< 60s */
+
+#define BD_ADDR_SIZE_LOCAL    6
+
+/* USER CODE BEGIN PD */
+#define LED_ON_TIMEOUT                 (0.005*1000*1000/CFG_TS_TICK_VAL) /**< 5ms */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static TL_CmdPacket_t BleCmdBuffer;
+
+static const uint8_t M_bd_addr[BD_ADDR_SIZE_LOCAL] =
+    {
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x0000000000FF)),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x00000000FF00) >> 8),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x000000FF0000) >> 16),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x0000FF000000) >> 24),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0x00FF00000000) >> 32),
+        (uint8_t)((CFG_ADV_BD_ADDRESS & 0xFF0000000000) >> 40)
+    };
+
+static uint8_t bd_addr_udn[BD_ADDR_SIZE_LOCAL];
+
+/**
+*   Identity root key used to derive LTK and CSRK 
+*/
+static const uint8_t BLE_CFG_IR_VALUE[16] = CFG_BLE_IRK;
+
+/**
+* Encryption root key used to derive LTK and CSRK
+*/
+static const uint8_t BLE_CFG_ER_VALUE[16] = CFG_BLE_ERK;
+
+/**
+ * These are the two tags used to manage a power failure during OTA
+ * The MagicKeywordAdress shall be mapped @0x140 from start of the binary image
+ * The MagicKeywordvalue is checked in the ble_ota application
+ */
+PLACE_IN_SECTION("TAG_OTA_END") const uint32_t MagicKeywordValue = 0x94448A29 ;
+PLACE_IN_SECTION("TAG_OTA_START") const uint32_t MagicKeywordAddress = (uint32_t)&MagicKeywordValue;
+
+PLACE_IN_SECTION("BLE_APP_CONTEXT") static BleApplicationContext_t BleApplicationContext;
+PLACE_IN_SECTION("BLE_APP_CONTEXT") static uint16_t AdvIntervalMin, AdvIntervalMax;
+
+P2PS_APP_ConnHandle_Not_evt_t handleNotification;
+
+#if L2CAP_REQUEST_NEW_CONN_PARAM != 0
+#define SIZE_TAB_CONN_INT            2
+float tab_conn_interval[SIZE_TAB_CONN_INT] = {50, 1000} ; /* ms */
+uint8_t index_con_int, mutex; 
+#endif 
+
+/**
+ * Advertising Data
+ */
+#if (P2P_SERVER1 != 0)
+static const char local_name[] = { AD_TYPE_COMPLETE_LOCAL_NAME ,'P','2','P','S','R','V','1'};
+uint8_t manuf_data[14] = {
+    sizeof(manuf_data)-1, AD_TYPE_MANUFACTURER_SPECIFIC_DATA, 
+    0x01/*SKD version */,
+    CFG_DEV_ID_P2P_SERVER1 /* STM32WB - P2P Server 1*/,
+    0x00 /* GROUP A Feature  */, 
+    0x00 /* GROUP A Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00, /* BLE MAC start -MSB */
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00, /* BLE MAC stop */
+};
+#endif
+/**
+ * Advertising Data
+ */
+#if (P2P_SERVER2 != 0)
+static const char local_name[] = { AD_TYPE_COMPLETE_LOCAL_NAME, 'P', '2', 'P', 'S', 'R', 'V', '2'};
+uint8_t manuf_data[14] = {
+    sizeof(manuf_data)-1, AD_TYPE_MANUFACTURER_SPECIFIC_DATA, 
+    0x01/*SKD version */,
+    CFG_DEV_ID_P2P_SERVER2 /* STM32WB - P2P Server 2*/,
+    0x00 /* GROUP A Feature  */, 
+    0x00 /* GROUP A Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00, /* BLE MAC start -MSB */
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00, /* BLE MAC stop */
+};
+
+#endif
+
+#if (P2P_SERVER3 != 0)
+static const char local_name[] = { AD_TYPE_COMPLETE_LOCAL_NAME, 'P', '2', 'P', 'S', 'R', 'V', '3'};
+uint8_t manuf_data[14] = {
+    sizeof(manuf_data)-1, AD_TYPE_MANUFACTURER_SPECIFIC_DATA, 
+    0x01/*SKD version */,
+    CFG_DEV_ID_P2P_SERVER3 /* STM32WB - P2P Server 3*/,
+    0x00 /* GROUP A Feature  */, 
+    0x00 /* GROUP A Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00, /* BLE MAC start -MSB */
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00, /* BLE MAC stop */
+};
+#endif
+
+#if (P2P_SERVER4 != 0)
+static const char local_name[] = { AD_TYPE_COMPLETE_LOCAL_NAME, 'P', '2', 'P', 'S', 'R', 'V', '4'};
+uint8_t manuf_data[14] = {
+    sizeof(manuf_data)-1, AD_TYPE_MANUFACTURER_SPECIFIC_DATA, 
+    0x01/*SKD version */,
+    CFG_DEV_ID_P2P_SERVER4 /* STM32WB - P2P Server 4*/,
+    0x00 /* GROUP A Feature  */, 
+    0x00 /* GROUP A Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00, /* BLE MAC start -MSB */
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00, /* BLE MAC stop */
+};
+#endif
+
+#if (P2P_SERVER5 != 0)
+static const char local_name[] = { AD_TYPE_COMPLETE_LOCAL_NAME, 'P', '2', 'P', 'S', 'R', 'V', '5'};
+uint8_t manuf_data[14] = {
+    sizeof(manuf_data)-1, AD_TYPE_MANUFACTURER_SPECIFIC_DATA, 
+    0x01/*SKD version */,
+    CFG_DEV_ID_P2P_SERVER5 /* STM32WB - P2P Server 5*/,
+    0x00 /* GROUP A Feature  */, 
+    0x00 /* GROUP A Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00, /* BLE MAC start -MSB */
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00, /* BLE MAC stop */
+};
+#endif
+
+#if (P2P_SERVER6 != 0)
+static const char local_name[] = { AD_TYPE_COMPLETE_LOCAL_NAME, 'P', '2', 'P', 'S', 'R', 'V', '6'};
+uint8_t manuf_data[14] = {
+    sizeof(manuf_data)-1, AD_TYPE_MANUFACTURER_SPECIFIC_DATA, 
+    0x01/*SKD version */,
+    CFG_DEV_ID_P2P_SERVER6 /* STM32WB - P2P Server 1*/,
+    0x00 /* GROUP A Feature  */, 
+    0x00 /* GROUP A Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00 /* GROUP B Feature */,
+    0x00, /* BLE MAC start -MSB */
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00, /* BLE MAC stop */
+};
+#endif
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+static void BLE_UserEvtRx( void * pPayload );
+static void BLE_StatusNot( HCI_TL_CmdStatus_t status );
+static void Ble_Tl_Init( void );
+static void Ble_Hci_Gap_Gatt_Init(void);
+static const uint8_t* BleGetBdAddress( void );
+static void Adv_Request( APP_BLE_ConnStatus_t New_Status );
+static void Adv_Cancel( void );
+static void Adv_Cancel_Req( void );
+static void Switch_OFF_GPIO( void );
+#if(L2CAP_REQUEST_NEW_CONN_PARAM != 0)  
+static void BLE_SVC_L2CAP_Conn_Update(uint16_t Connection_Handle);
+#endif
+
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APP_BLE_Init( void )
+{
+/* USER CODE BEGIN APP_BLE_Init_1 */
+
+/* USER CODE END APP_BLE_Init_1 */
+  SHCI_C2_Ble_Init_Cmd_Packet_t ble_init_cmd_packet =
+  {
+    {{0,0,0}},                          /**< Header unused */
+    {0,                                 /** pBleBufferAddress not used */
+    0,                                  /** BleBufferSize not used */
+    CFG_BLE_NUM_GATT_ATTRIBUTES,
+    CFG_BLE_NUM_GATT_SERVICES,
+    CFG_BLE_ATT_VALUE_ARRAY_SIZE,
+    CFG_BLE_NUM_LINK,
+    CFG_BLE_DATA_LENGTH_EXTENSION,
+    CFG_BLE_PREPARE_WRITE_LIST_SIZE,
+    CFG_BLE_MBLOCK_COUNT,
+    CFG_BLE_MAX_ATT_MTU,
+    CFG_BLE_SLAVE_SCA,
+    CFG_BLE_MASTER_SCA,
+    CFG_BLE_LSE_SOURCE,
+    CFG_BLE_MAX_CONN_EVENT_LENGTH,
+    CFG_BLE_HSE_STARTUP_TIME,
+    CFG_BLE_VITERBI_MODE,
+    CFG_BLE_LL_ONLY,
+    0}
+  };
+
+  /**
+   * Initialize Ble Transport Layer
+   */
+  Ble_Tl_Init( );
+
+  /**
+   * Do not allow standby in the application
+   */
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP_BLE, UTIL_LPM_DISABLE);
+
+  /**
+   * Register the hci transport layer to handle BLE User Asynchronous Events
+   */
+  UTIL_SEQ_RegTask( 1<data;
+
+  switch (event_pckt->evt)
+  {
+    case EVT_DISCONN_COMPLETE:
+    {
+      hci_disconnection_complete_event_rp0 *disconnection_complete_event;
+      disconnection_complete_event = (hci_disconnection_complete_event_rp0 *) event_pckt->data;
+
+      if (disconnection_complete_event->Connection_Handle == BleApplicationContext.BleApplicationContext_legacy.connectionHandle)
+      {
+        BleApplicationContext.BleApplicationContext_legacy.connectionHandle = 0;
+        BleApplicationContext.Device_Connection_Status = APP_BLE_IDLE;
+
+        APP_DBG_MSG("\r\n\r** DISCONNECTION EVENT WITH CLIENT \n");
+      }
+
+      /* restart advertising */
+      Adv_Request(APP_BLE_FAST_ADV);
+ /*
+* SPECIFIC to P2P Server APP
+*/     
+      handleNotification.P2P_Evt_Opcode = PEER_DISCON_HANDLE_EVT;
+      handleNotification.ConnectionHandle = BleApplicationContext.BleApplicationContext_legacy.connectionHandle;
+      P2PS_APP_Notification(&handleNotification);
+
+      /* USER CODE BEGIN EVT_DISCONN_COMPLETE */
+
+      /* USER CODE END EVT_DISCONN_COMPLETE */
+    }
+
+    break; /* EVT_DISCONN_COMPLETE */
+
+    case EVT_LE_META_EVENT:
+    {
+      meta_evt = (evt_le_meta_event*) event_pckt->data;
+      /* USER CODE BEGIN EVT_LE_META_EVENT */
+
+      /* USER CODE END EVT_LE_META_EVENT */
+      switch (meta_evt->subevent)
+      {
+        case EVT_LE_CONN_UPDATE_COMPLETE: 
+          APP_DBG_MSG("\r\n\r** CONNECTION UPDATE EVENT WITH CLIENT \n");
+
+          /* USER CODE BEGIN EVT_LE_CONN_UPDATE_COMPLETE */
+
+          /* USER CODE END EVT_LE_CONN_UPDATE_COMPLETE */
+          break;
+        case EVT_LE_PHY_UPDATE_COMPLETE:
+          APP_DBG_MSG("EVT_UPDATE_PHY_COMPLETE \n");
+          evt_le_phy_update_complete = (hci_le_phy_update_complete_event_rp0*)meta_evt->data;
+          if (evt_le_phy_update_complete->Status == 0)
+          {
+            APP_DBG_MSG("EVT_UPDATE_PHY_COMPLETE, status ok \n");
+          }
+          else
+          {
+            APP_DBG_MSG("EVT_UPDATE_PHY_COMPLETE, status nok \n");
+          }
+          ret = hci_le_read_phy(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,&TX_PHY,&RX_PHY);
+          if (ret == BLE_STATUS_SUCCESS)
+          {
+            APP_DBG_MSG("Read_PHY success \n");
+            if ((TX_PHY == TX_2M) && (RX_PHY == RX_2M))
+            {
+              APP_DBG_MSG("PHY Param  TX= %d, RX= %d \n", TX_PHY, RX_PHY);
+            }
+            else
+            {
+              APP_DBG_MSG("PHY Param  TX= %d, RX= %d \n", TX_PHY, RX_PHY);
+            } 
+          }
+          else
+          {
+            APP_DBG_MSG("Read conf not succeess \n");
+          }
+          /* USER CODE BEGIN EVT_LE_PHY_UPDATE_COMPLETE */
+
+          /* USER CODE END EVT_LE_PHY_UPDATE_COMPLETE */          
+          break;
+        case EVT_LE_CONN_COMPLETE:
+          {
+          hci_le_connection_complete_event_rp0 *connection_complete_event;
+
+          /**
+           * The connection is done, there is no need anymore to schedule the LP ADV
+           */
+          connection_complete_event = (hci_le_connection_complete_event_rp0 *) meta_evt->data;
+          
+          HW_TS_Stop(BleApplicationContext.Advertising_mgr_timer_Id);
+
+          APP_DBG_MSG("EVT_LE_CONN_COMPLETE for connection handle 0x%x\n",
+          connection_complete_event->Connection_Handle);
+            if (BleApplicationContext.Device_Connection_Status == APP_BLE_LP_CONNECTING)
+            {
+              /* Connection as client */
+              BleApplicationContext.Device_Connection_Status = APP_BLE_CONNECTED_CLIENT;
+            }
+            else
+            {
+              /* Connection as server */
+              BleApplicationContext.Device_Connection_Status = APP_BLE_CONNECTED_SERVER;
+            }
+            BleApplicationContext.BleApplicationContext_legacy.connectionHandle =
+                connection_complete_event->Connection_Handle;
+ /*
+* SPECIFIC to P2P Server APP
+*/             
+          handleNotification.P2P_Evt_Opcode = PEER_CONN_HANDLE_EVT;
+          handleNotification.ConnectionHandle = BleApplicationContext.BleApplicationContext_legacy.connectionHandle;
+          P2PS_APP_Notification(&handleNotification);
+          /* USER CODE BEGIN HCI_EVT_LE_CONN_COMPLETE */
+ /*
+* SPECIFIC to P2P Server APP
+*/             
+          handleNotification.P2P_Evt_Opcode = PEER_CONN_HANDLE_EVT;
+          handleNotification.ConnectionHandle = BleApplicationContext.BleApplicationContext_legacy.connectionHandle;
+          P2PS_APP_Notification(&handleNotification);
+/**/
+          /* USER CODE END HCI_EVT_LE_CONN_COMPLETE */
+          }
+        break; /* HCI_EVT_LE_CONN_COMPLETE */
+
+        default:
+          /* USER CODE BEGIN SUBEVENT_DEFAULT */
+
+          /* USER CODE END SUBEVENT_DEFAULT */
+          break;
+      }
+    }
+    break; /* HCI_EVT_LE_META_EVENT */
+
+    case EVT_VENDOR:
+      blue_evt = (evt_blue_aci*) event_pckt->data;
+      /* USER CODE BEGIN EVT_VENDOR */
+
+      /* USER CODE END EVT_VENDOR */
+      switch (blue_evt->ecode)
+      {
+      /* USER CODE BEGIN ecode */
+        aci_gap_pairing_complete_event_rp0 *pairing_complete;
+
+      case EVT_BLUE_GAP_LIMITED_DISCOVERABLE: 
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_LIMITED_DISCOVERABLE \n");
+          break; /* EVT_BLUE_GAP_LIMITED_DISCOVERABLE */
+      case EVT_BLUE_GAP_PASS_KEY_REQUEST:  
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_PASS_KEY_REQUEST \n");
+/*
+        aci_gap_pass_key_resp(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,123456);
+*/
+        APP_DBG_MSG("\r\n\r** aci_gap_pass_key_resp \n");
+          break; /* EVT_BLUE_GAP_PASS_KEY_REQUEST */
+      case EVT_BLUE_GAP_AUTHORIZATION_REQUEST:    
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_AUTHORIZATION_REQUEST \n");
+          break; /* EVT_BLUE_GAP_AUTHORIZATION_REQUEST */
+      case EVT_BLUE_GAP_SLAVE_SECURITY_INITIATED:   
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_SLAVE_SECURITY_INITIATED \n");
+          break; /* EVT_BLUE_GAP_SLAVE_SECURITY_INITIATED */
+      case EVT_BLUE_GAP_BOND_LOST:    
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_BOND_LOST \n");
+          aci_gap_allow_rebond(BleApplicationContext.BleApplicationContext_legacy.connectionHandle);
+        APP_DBG_MSG("\r\n\r** Send allow rebond \n");
+          break; /* EVT_BLUE_GAP_BOND_LOST */
+      case EVT_BLUE_GAP_DEVICE_FOUND:  
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_DEVICE_FOUND \n");
+          break; /* EVT_BLUE_GAP_DEVICE_FOUND */
+      case EVT_BLUE_GAP_ADDR_NOT_RESOLVED:
+         APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_DEVICE_FOUND \n");
+          break; /* EVT_BLUE_GAP_DEVICE_FOUND */
+      case (EVT_BLUE_GAP_KEYPRESS_NOTIFICATION):
+         APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_KEYPRESS_NOTIFICATION \n");
+          break; /* EVT_BLUE_GAP_KEY_PRESS_NOTIFICATION */    
+       case (EVT_BLUE_GAP_NUMERIC_COMPARISON_VALUE):
+          APP_DBG_MSG("numeric_value = %ld\n",
+                      ((aci_gap_numeric_comparison_value_event_rp0 *)(blue_evt->data))->Numeric_Value);
+
+          APP_DBG_MSG("Hex_value = %lx\n",
+                      ((aci_gap_numeric_comparison_value_event_rp0 *)(blue_evt->data))->Numeric_Value);
+
+          aci_gap_numeric_comparison_value_confirm_yesno(BleApplicationContext.BleApplicationContext_legacy.connectionHandle, 1); /* CONFIRM_YES = 1 */
+
+          APP_DBG_MSG("\r\n\r** aci_gap_numeric_comparison_value_confirm_yesno-->YES \n");
+      break;
+          case (EVT_BLUE_GAP_PAIRING_CMPLT):
+          {
+            pairing_complete = (aci_gap_pairing_complete_event_rp0*)blue_evt->data;
+            APP_DBG_MSG("BLE_CTRL_App_Notification: EVT_BLUE_GAP_PAIRING_CMPLT, pairing_complete->Status = %d\n",pairing_complete->Status);
+            if (pairing_complete->Status == 0)
+            {
+              APP_DBG_MSG("\r\n\r** Pairing OK \n");
+            }
+            else
+            {
+              APP_DBG_MSG("\r\n\r** Pairing KO \n");
+            }
+          }
+           break;    
+      /* USER CODE END ecode */
+/*
+* SPECIFIC to P2P Server APP
+*/
+        case EVT_BLUE_L2CAP_CONNECTION_UPDATE_RESP:
+#if (L2CAP_REQUEST_NEW_CONN_PARAM != 0 )
+          mutex = 1;
+#endif
+      /* USER CODE BEGIN EVT_BLUE_L2CAP_CONNECTION_UPDATE_RESP */
+
+      /* USER CODE END EVT_BLUE_L2CAP_CONNECTION_UPDATE_RESP */
+      break;
+        case EVT_BLUE_GAP_PROCEDURE_COMPLETE:
+        APP_DBG_MSG("\r\n\r** EVT_BLUE_GAP_PROCEDURE_COMPLETE \n");
+        /* USER CODE BEGIN EVT_BLUE_GAP_PROCEDURE_COMPLETE */
+
+        /* USER CODE END EVT_BLUE_GAP_PROCEDURE_COMPLETE */
+        break; /* EVT_BLUE_GAP_PROCEDURE_COMPLETE */
+#if(RADIO_ACTIVITY_EVENT != 0)
+        case 0x0004:
+        /* USER CODE BEGIN RADIO_ACTIVITY_EVENT*/
+          BSP_LED_On(LED_GREEN);
+          HW_TS_Start(BleApplicationContext.SwitchOffGPIO_timer_Id, (uint32_t)LED_ON_TIMEOUT);
+        /* USER CODE END RADIO_ACTIVITY_EVENT*/
+        break; /* RADIO_ACTIVITY_EVENT */
+#endif
+      }
+      break; /* EVT_VENDOR */
+
+        default:
+        /* USER CODE BEGIN ECODE_DEFAULT*/
+
+        /* USER CODE END ECODE_DEFAULT*/
+          break;
+  }
+
+  return (SVCCTL_UserEvtFlowEnable);
+}
+
+APP_BLE_ConnStatus_t APP_BLE_Get_Server_Connection_Status(void)
+{
+    return BleApplicationContext.Device_Connection_Status;
+}
+
+/* USER CODE BEGIN FD*/
+void APP_BLE_Key_Button1_Action(void)
+{
+  P2PS_APP_SW1_Button_Action();
+}
+
+void APP_BLE_Key_Button2_Action(void)
+{
+#if (L2CAP_REQUEST_NEW_CONN_PARAM != 0 )    
+    if (BleApplicationContext.Device_Connection_Status != APP_BLE_FAST_ADV && BleApplicationContext.Device_Connection_Status != APP_BLE_IDLE)
+  {
+    BLE_SVC_L2CAP_Conn_Update(BleApplicationContext.BleApplicationContext_legacy.connectionHandle);
+
+  }
+  return;
+#endif    
+}
+
+void APP_BLE_Key_Button3_Action(void)
+{
+}
+
+/* USER CODE END FD*/
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void Ble_Tl_Init( void )
+{
+  HCI_TL_HciInitConf_t Hci_Tl_Init_Conf;
+
+  Hci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&BleCmdBuffer;
+  Hci_Tl_Init_Conf.StatusNotCallBack = BLE_StatusNot;
+  hci_init(BLE_UserEvtRx, (void*) &Hci_Tl_Init_Conf);
+
+  return;
+}
+
+ static void Ble_Hci_Gap_Gatt_Init(void){
+
+  uint8_t role;
+  uint8_t index;
+  uint16_t gap_service_handle, gap_dev_name_char_handle, gap_appearance_char_handle;
+  const uint8_t *bd_addr;
+  uint32_t srd_bd_addr[2];
+  uint16_t appearance[1] = { BLE_CFG_GAP_APPEARANCE }; 
+
+  /**
+   * Initialize HCI layer
+   */
+  /*HCI Reset to synchronise BLE Stack*/
+  hci_reset();
+
+  /**
+   * Write the BD Address
+   */
+
+  bd_addr = BleGetBdAddress();
+  aci_hal_write_config_data(CONFIG_DATA_PUBADDR_OFFSET,
+                            CONFIG_DATA_PUBADDR_LEN,
+                            (uint8_t*) bd_addr);
+
+  /* BLE MAC in ADV Packet */
+  manuf_data[ sizeof(manuf_data)-6] = bd_addr[5];
+  manuf_data[ sizeof(manuf_data)-5] = bd_addr[4];
+  manuf_data[ sizeof(manuf_data)-4] = bd_addr[3];
+  manuf_data[ sizeof(manuf_data)-3] = bd_addr[2];
+  manuf_data[ sizeof(manuf_data)-2] = bd_addr[1];
+  manuf_data[ sizeof(manuf_data)-1] = bd_addr[0];
+  
+  /**
+   * Static random Address
+   * The two upper bits shall be set to 1
+   * The lowest 32bits is read from the UDN to differentiate between devices
+   * The RNG may be used to provide a random number on each power on
+   */
+  srd_bd_addr[1] =  0x0000ED6E;
+  srd_bd_addr[0] =  LL_FLASH_GetUDN( );
+  aci_hal_write_config_data( CONFIG_DATA_RANDOM_ADDRESS_OFFSET, CONFIG_DATA_RANDOM_ADDRESS_LEN, (uint8_t*)srd_bd_addr );
+
+  /**
+   * Write Identity root key used to derive LTK and CSRK 
+   */
+    aci_hal_write_config_data( CONFIG_DATA_IR_OFFSET, CONFIG_DATA_IR_LEN, (uint8_t*)BLE_CFG_IR_VALUE );
+    
+   /**
+   * Write Encryption root key used to derive LTK and CSRK
+   */
+    aci_hal_write_config_data( CONFIG_DATA_ER_OFFSET, CONFIG_DATA_ER_LEN, (uint8_t*)BLE_CFG_ER_VALUE );
+
+  /**
+   * Set TX Power to 0dBm.
+   */
+  aci_hal_set_tx_power_level(1, CFG_TX_POWER);
+
+  /**
+   * Initialize GATT interface
+   */
+  aci_gatt_init();
+
+  /**
+   * Initialize GAP interface
+   */
+  role = 0;
+
+#if (BLE_CFG_PERIPHERAL == 1)
+  role |= GAP_PERIPHERAL_ROLE;
+#endif
+
+#if (BLE_CFG_CENTRAL == 1)
+  role |= GAP_CENTRAL_ROLE;
+#endif
+
+  if (role > 0)
+  {
+    const char *name = "STM32WB";
+    aci_gap_init(role, 0,
+                 APPBLE_GAP_DEVICE_NAME_LENGTH,
+                 &gap_service_handle, &gap_dev_name_char_handle, &gap_appearance_char_handle);
+
+    if (aci_gatt_update_char_value(gap_service_handle, gap_dev_name_char_handle, 0, strlen(name), (uint8_t *) name))
+    {
+      BLE_DBG_SVCCTL_MSG("Device Name aci_gatt_update_char_value failed.\n");
+    }
+  }
+
+  if(aci_gatt_update_char_value(gap_service_handle,
+                                gap_appearance_char_handle,
+                                0,
+                                2,
+                                (uint8_t *)&appearance))
+  {
+    BLE_DBG_SVCCTL_MSG("Appearance aci_gatt_update_char_value failed.\n");
+  }
+/**
+   * Initialize Default PHY
+   */
+  hci_le_set_default_phy(ALL_PHYS_PREFERENCE,TX_2M_PREFERRED,RX_2M_PREFERRED); 
+
+  /**
+   * Initialize IO capability
+   */
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.ioCapability = CFG_IO_CAPABILITY;
+  aci_gap_set_io_capability(BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.ioCapability);
+
+  /**
+   * Initialize authentication
+   */
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode = CFG_MITM_PROTECTION;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data_Present = 0;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin = 8;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax = 16;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin = 1;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin = 111111;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode = 1;
+  for (index = 0; index < 16; index++)
+  {
+    BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data[index] = (uint8_t) index;
+  }
+
+  aci_gap_set_authentication_requirement(BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode,
+                                         1,
+                                         0,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin,
+                                         BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin,
+0
+  );
+
+  /**
+   * Initialize whitelist
+   */
+   if (BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode)
+   {
+     aci_gap_configure_whitelist();
+   }
+}
+
+static void Adv_Request(APP_BLE_ConnStatus_t New_Status)
+{
+  tBleStatus ret = BLE_STATUS_INVALID_PARAMS;
+  uint16_t Min_Inter, Max_Inter;
+ 
+  if (New_Status == APP_BLE_FAST_ADV)
+  {
+    Min_Inter = AdvIntervalMin;
+    Max_Inter = AdvIntervalMax;
+  }
+  else
+  {
+    Min_Inter = CFG_LP_CONN_ADV_INTERVAL_MIN;
+    Max_Inter = CFG_LP_CONN_ADV_INTERVAL_MAX;
+  }
+
+    /**
+     * Stop the timer, it will be restarted for a new shot
+     * It does not hurt if the timer was not running
+     */
+    HW_TS_Stop(BleApplicationContext.Advertising_mgr_timer_Id);
+
+    APP_DBG_MSG("First index in %d state \n", BleApplicationContext.Device_Connection_Status);
+    if ((New_Status == APP_BLE_LP_ADV)
+        && ((BleApplicationContext.Device_Connection_Status == APP_BLE_FAST_ADV)
+            || (BleApplicationContext.Device_Connection_Status == APP_BLE_LP_ADV)))
+    {
+      /* Connection in ADVERTISE mode have to stop the current advertising */
+      ret = aci_gap_set_non_discoverable();
+      if (ret == BLE_STATUS_SUCCESS)
+      {
+        APP_DBG_MSG("Successfully Stopped Advertising \n");
+        }
+      else
+      {
+        APP_DBG_MSG("Stop Advertising Failed , result: %d \n", ret);
+      }
+    }
+
+    BleApplicationContext.Device_Connection_Status = New_Status;
+    /* Start Fast or Low Power Advertising */
+    ret = aci_gap_set_discoverable(
+        ADV_IND,
+        Min_Inter,
+        Max_Inter,
+        PUBLIC_ADDR,
+        NO_WHITE_LIST_USE, /* use white list */
+        sizeof(local_name),
+        (uint8_t*) &local_name,
+        BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen,
+        BleApplicationContext.BleApplicationContext_legacy.advtServUUID,
+        0,
+        0);
+    /* Update Advertising data */
+    ret = aci_gap_update_adv_data(sizeof(manuf_data), (uint8_t*) manuf_data);
+
+     if (ret == BLE_STATUS_SUCCESS)
+    {
+      if (New_Status == APP_BLE_FAST_ADV)
+      {
+        APP_DBG_MSG("Successfully Start Fast Advertising \n" );
+        /* Start Timer to STOP ADV - TIMEOUT */
+        HW_TS_Start(BleApplicationContext.Advertising_mgr_timer_Id, INITIAL_ADV_TIMEOUT);
+      }
+      else
+      {
+        APP_DBG_MSG("Successfully Start Low Power Advertising \n");
+        }
+    }
+    else
+    {
+      if (New_Status == APP_BLE_FAST_ADV)
+      {
+        APP_DBG_MSG("Start Fast Advertising Failed , result: %d \n", ret);
+      }
+      else
+      {
+        APP_DBG_MSG("Start Low Power Advertising Failed , result: %d \n", ret);
+      }
+    }
+
+  return;
+}
+
+const uint8_t* BleGetBdAddress( void )
+{
+  uint8_t *otp_addr;
+  const uint8_t *bd_addr;
+  uint32_t udn;
+  uint32_t company_id;
+  uint32_t device_id;
+
+  udn = LL_FLASH_GetUDN();
+
+  if(udn != 0xFFFFFFFF)
+  {
+    company_id = LL_FLASH_GetSTCompanyID();
+    device_id = LL_FLASH_GetDeviceID();
+
+    bd_addr_udn[0] = (uint8_t)(udn & 0x000000FF);
+    bd_addr_udn[1] = (uint8_t)( (udn & 0x0000FF00) >> 8 );
+    bd_addr_udn[2] = (uint8_t)( (udn & 0x00FF0000) >> 16 );
+    bd_addr_udn[3] = (uint8_t)device_id;
+    bd_addr_udn[4] = (uint8_t)(company_id & 0x000000FF);;
+    bd_addr_udn[5] = (uint8_t)( (company_id & 0x0000FF00) >> 8 );
+
+    bd_addr = (const uint8_t *)bd_addr_udn;
+  }
+  else
+  {
+    otp_addr = OTP_Read(0);
+    if(otp_addr)
+    {
+      bd_addr = ((OTP_ID0_t*)otp_addr)->bd_address;
+    }
+    else
+    {
+      bd_addr = M_bd_addr;
+    }
+
+  }
+
+  return bd_addr;
+}
+
+/* USER CODE BEGIN FD_LOCAL_FUNCTION */
+
+/* USER CODE END FD_LOCAL_FUNCTION */
+
+/*************************************************************
+ *
+ *SPECIFIC FUNCTIONS FOR P2P SERVER
+ *
+ *************************************************************/
+static void Adv_Cancel( void )
+{
+/* USER CODE BEGIN Adv_Cancel_1 */
+  BSP_LED_Off(LED_GREEN);
+/* USER CODE END Adv_Cancel_1 */
+
+  if (BleApplicationContext.Device_Connection_Status != APP_BLE_CONNECTED_SERVER)
+
+  {
+
+    tBleStatus result = 0x00;
+
+    result = aci_gap_set_non_discoverable();
+
+    BleApplicationContext.Device_Connection_Status = APP_BLE_IDLE;
+    if (result == BLE_STATUS_SUCCESS)
+    {
+      APP_DBG_MSG("  \r\n\r");APP_DBG_MSG("** STOP ADVERTISING **  \r\n\r");
+    }
+    else
+    {
+      APP_DBG_MSG("** STOP ADVERTISING **  Failed \r\n\r");
+    }
+
+  }
+
+/* USER CODE BEGIN Adv_Cancel_2 */
+
+/* USER CODE END Adv_Cancel_2 */
+  return;
+}
+
+static void Adv_Cancel_Req( void )
+{
+/* USER CODE BEGIN Adv_Cancel_Req_1 */
+
+/* USER CODE END Adv_Cancel_Req_1 */
+  UTIL_SEQ_SetTask(1 << CFG_TASK_ADV_CANCEL_ID, CFG_SCH_PRIO_0);
+/* USER CODE BEGIN Adv_Cancel_Req_2 */
+
+/* USER CODE END Adv_Cancel_Req_2 */
+  return;
+}
+
+static void Switch_OFF_GPIO(){
+/* USER CODE BEGIN Switch_OFF_GPIO */
+  BSP_LED_Off(LED_GREEN);
+/* USER CODE END Switch_OFF_GPIO */
+}
+
+#if(L2CAP_REQUEST_NEW_CONN_PARAM != 0)  
+void BLE_SVC_L2CAP_Conn_Update(uint16_t Connection_Handle)
+{
+/* USER CODE BEGIN BLE_SVC_L2CAP_Conn_Update_1 */
+
+/* USER CODE END BLE_SVC_L2CAP_Conn_Update_1 */
+  if(mutex == 1) { 
+    mutex = 0;
+    index_con_int = (index_con_int + 1)%SIZE_TAB_CONN_INT;
+    uint16_t interval_min = CONN_P(tab_conn_interval[index_con_int]);
+    uint16_t interval_max = CONN_P(tab_conn_interval[index_con_int]);
+    uint16_t slave_latency = L2CAP_SLAVE_LATENCY;
+    uint16_t timeout_multiplier = L2CAP_TIMEOUT_MULTIPLIER;
+    tBleStatus result;
+
+    result = aci_l2cap_connection_parameter_update_req(BleApplicationContext.BleApplicationContext_legacy.connectionHandle,
+                                                       interval_min, interval_max,
+                                                       slave_latency, timeout_multiplier);
+    if( result == BLE_STATUS_SUCCESS )
+    {
+      APP_DBG_MSG("BLE_SVC_L2CAP_Conn_Update(), Successfully \r\n\r");
+    }
+    else
+    {
+      APP_DBG_MSG("BLE_SVC_L2CAP_Conn_Update(), Failed \r\n\r");
+    }
+  }
+/* USER CODE BEGIN BLE_SVC_L2CAP_Conn_Update_2 */
+
+/* USER CODE END BLE_SVC_L2CAP_Conn_Update_2 */
+  return;
+}
+#endif
+
+/* USER CODE BEGIN FD_SPECIFIC_FUNCTIONS */
+
+/* USER CODE END FD_SPECIFIC_FUNCTIONS */
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+void hci_notify_asynch_evt(void* pdata)
+{
+  UTIL_SEQ_SetTask(1 << CFG_TASK_HCI_ASYNCH_EVT_ID, CFG_SCH_PRIO_0);
+  return;
+}
+
+void hci_cmd_resp_release(uint32_t flag)
+{
+  UTIL_SEQ_SetEvt(1 << CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID);
+  return;
+}
+
+void hci_cmd_resp_wait(uint32_t timeout)
+{
+  UTIL_SEQ_WaitEvt(1 << CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID);
+  return;
+}
+
+static void BLE_UserEvtRx( void * pPayload )
+{
+  SVCCTL_UserEvtFlowStatus_t svctl_return_status;
+  tHCI_UserEvtRxParam *pParam;
+
+  pParam = (tHCI_UserEvtRxParam *)pPayload; 
+
+  svctl_return_status = SVCCTL_UserEvtRx((void *)&(pParam->pckt->evtserial));
+  if (svctl_return_status != SVCCTL_UserEvtFlowDisable)
+  {
+    pParam->status = HCI_TL_UserEventFlow_Enable;
+  }
+  else
+  {
+    pParam->status = HCI_TL_UserEventFlow_Disable;
+  }
+}
+
+static void BLE_StatusNot( HCI_TL_CmdStatus_t status )
+{
+  uint32_t task_id_list;
+  switch (status)
+  {
+    case HCI_TL_CmdBusy:
+      /**
+       * All tasks that may send an aci/hci commands shall be listed here
+       * This is to prevent a new command is sent while one is already pending
+       */
+      task_id_list = (1 << CFG_LAST_TASK_ID_WITH_HCICMD) - 1;
+      UTIL_SEQ_PauseTask(task_id_list);
+
+      break;
+
+    case HCI_TL_CmdAvailable:
+      /**
+       * All tasks that may send an aci/hci commands shall be listed here
+       * This is to prevent a new command is sent while one is already pending
+       */
+      task_id_list = (1 << CFG_LAST_TASK_ID_WITH_HCICMD) - 1;
+      UTIL_SEQ_ResumeTask(task_id_list);
+
+      break;
+
+    default:
+      break;
+  }
+  return;
+}
+
+void SVCCTL_ResumeUserEventFlow( void )
+{
+  hci_resume_flow();
+  return;
+}
+
+/* USER CODE BEGIN FD_WRAP_FUNCTIONS */
+
+/* USER CODE END FD_WRAP_FUNCTIONS */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/app_ble.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/app_ble.h
new file mode 100644
index 000000000..657ba432b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/app_ble.h
@@ -0,0 +1,88 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    app_ble.h
+  * @author  MCD Application Team
+  * @brief   Header for ble application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_BLE_H
+#define APP_BLE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "hci_tl.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+
+    typedef enum
+    {
+      APP_BLE_IDLE,
+      APP_BLE_FAST_ADV,
+      APP_BLE_LP_ADV,
+      APP_BLE_SCAN,
+      APP_BLE_LP_CONNECTING,
+      APP_BLE_CONNECTED_SERVER,
+      APP_BLE_CONNECTED_CLIENT
+    } APP_BLE_ConnStatus_t;
+    
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */  
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APP_BLE_Init( void ); 
+
+  APP_BLE_ConnStatus_t APP_BLE_Get_Server_Connection_Status(void);
+
+/* USER CODE BEGIN EF */
+void APP_BLE_Key_Button1_Action(void);
+void APP_BLE_Key_Button2_Action(void);
+void APP_BLE_Key_Button3_Action(void);
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*APP_BLE_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/ble_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/ble_conf.h
new file mode 100644
index 000000000..f6e04686e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/ble_conf.h
@@ -0,0 +1,70 @@
+/**
+ ******************************************************************************
+  * File Name          : App/ble_conf.h
+  * Description        : Configuration file for BLE Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef BLE_CONF_H
+#define BLE_CONF_H
+
+#include "app_conf.h"
+
+/******************************************************************************
+ *
+ * BLE SERVICES CONFIGURATION
+ * blesvc
+ *
+ ******************************************************************************/
+
+ /**
+ * This setting shall be set to '1' if the device needs to support the Peripheral Role
+ * In the MS configuration, both BLE_CFG_PERIPHERAL and BLE_CFG_CENTRAL shall be set to '1'
+ */
+#define BLE_CFG_PERIPHERAL                                                     1
+
+/**
+ * This setting shall be set to '1' if the device needs to support the Central Role
+ * In the MS configuration, both BLE_CFG_PERIPHERAL and BLE_CFG_CENTRAL shall be set to '1'
+ */
+#define BLE_CFG_CENTRAL                                                        0
+
+/**
+ * There is one handler per service enabled
+ * Note: There is no handler for the Device Information Service
+ *
+ * This shall take into account all registered handlers
+ * (from either the provided services or the custom services)
+ */
+#define BLE_CFG_SVC_MAX_NBR_CB                                                 1
+
+#define BLE_CFG_CLT_MAX_NBR_CB                                                 0
+
+/******************************************************************************
+ * GAP Service - Apprearance
+ ******************************************************************************/
+
+#define BLE_CFG_UNKNOWN_APPEARANCE                  (0)
+#define BLE_CFG_HR_SENSOR_APPEARANCE                (832)
+#define BLE_CFG_GAP_APPEARANCE                      (BLE_CFG_UNKNOWN_APPEARANCE)
+
+/******************************************************************************
+ * Over The Air Feature (OTA) - STM Proprietary
+ ******************************************************************************/
+#define BLE_CFG_OTA_REBOOT_CHAR         1/**< REBOOT OTA MODE CHARACTERISTIC */
+
+#endif /*BLE_CONF_H */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/ble_dbg_conf.h b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/ble_dbg_conf.h
new file mode 100644
index 000000000..bec936bbe
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/ble_dbg_conf.h
@@ -0,0 +1,199 @@
+/**
+ ******************************************************************************
+  * File Name          : App/ble_dbg_conf.h
+  * Description        : Debug configuration file for BLE Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __BLE_DBG_CONF_H
+#define __BLE_DBG_CONF_H
+
+/**
+ * Enable or Disable traces from BLE
+ */
+
+#define BLE_DBG_APP_EN             0
+#define BLE_DBG_DIS_EN             0
+#define BLE_DBG_HRS_EN             0
+#define BLE_DBG_SVCCTL_EN          0
+#define BLE_DBG_BLS_EN             0
+#define BLE_DBG_HTS_EN             0
+#define BLE_DBG_P2P_STM_EN         1
+
+/**
+ * Macro definition
+ */
+#if ( BLE_DBG_APP_EN != 0 )
+#define BLE_DBG_APP_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_APP_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_DIS_EN != 0 )
+#define BLE_DBG_DIS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_DIS_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_HRS_EN != 0 )
+#define BLE_DBG_HRS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HRS_MSG             PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_P2P_STM_EN != 0 )
+#define BLE_DBG_P2P_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_P2P_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_TEMPLATE_STM_EN != 0 )
+#define BLE_DBG_TEMPLATE_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_TEMPLATE_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_EDS_STM_EN != 0 )
+#define BLE_DBG_EDS_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_EDS_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_LBS_STM_EN != 0 )
+#define BLE_DBG_LBS_STM_MSG         PRINT_MESG_DBG
+#else
+#define BLE_DBG_LBS_STM_MSG         PRINT_NO_MESG
+#endif
+
+#if ( BLE_DBG_SVCCTL_EN != 0 )
+#define BLE_DBG_SVCCTL_MSG          PRINT_MESG_DBG
+#else
+#define BLE_DBG_SVCCTL_MSG          PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_CTS_EN != 0)
+#define BLE_DBG_CTS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_CTS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HIDS_EN != 0)
+#define BLE_DBG_HIDS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_HIDS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_PASS_EN != 0)
+#define BLE_DBG_PASS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_PASS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_BLS_EN != 0)
+#define BLE_DBG_BLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_BLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HTS_EN != 0)
+#define BLE_DBG_HTS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HTS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_ANS_EN != 0)
+#define BLE_DBG_ANS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_ANS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_ESS_EN != 0)
+#define BLE_DBG_ESS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_ESS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_GLS_EN != 0)
+#define BLE_DBG_GLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_GLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_BAS_EN != 0)
+#define BLE_DBG_BAS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_BAS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_RTUS_EN != 0)
+#define BLE_DBG_RTUS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_RTUS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_HPS_EN != 0)
+#define BLE_DBG_HPS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_HPS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_TPS_EN != 0)
+#define BLE_DBG_TPS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_TPS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_LLS_EN != 0)
+#define BLE_DBG_LLS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_LLS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_IAS_EN != 0)
+#define BLE_DBG_IAS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_IAS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_WSS_EN != 0)
+#define BLE_DBG_WSS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_WSS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_LNS_EN != 0)
+#define BLE_DBG_LNS_MSG             PRINT_MESG_DBG
+#else
+#define BLE_DBG_LNS_MSG             PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_SCPS_EN != 0)
+#define BLE_DBG_SCPS_MSG            PRINT_MESG_DBG
+#else
+#define BLE_DBG_SCPS_MSG            PRINT_NO_MESG
+#endif
+
+#if (BLE_DBG_DTS_EN != 0)
+#define BLE_DBG_DTS_MSG             PRINT_MESG_DBG
+#define BLE_DBG_DTS_BUF             PRINT_LOG_BUFF_DBG
+#else
+#define BLE_DBG_DTS_MSG             PRINT_NO_MESG
+#define BLE_DBG_DTS_BUF             PRINT_NO_MESG
+#endif
+
+#endif /*__BLE_DBG_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/p2p_server_app.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/p2p_server_app.c
new file mode 100644
index 000000000..5c95b3afe
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/App/p2p_server_app.c
@@ -0,0 +1,389 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    p2p_server_app.c
+ * @author  MCD Application Team
+ * @brief   peer to peer Server Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "app_common.h"
+#include "dbg_trace.h"
+#include "ble.h"
+#include "p2p_server_app.h"
+#include "stm32_seq.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+ typedef struct{
+    uint8_t             Device_Led_Selection;
+    uint8_t             Led1;
+ }P2P_LedCharValue_t;
+
+ typedef struct{
+    uint8_t             Device_Button_Selection;
+    uint8_t             ButtonStatus;
+ }P2P_ButtonCharValue_t;
+
+typedef struct
+{
+  uint8_t               Notification_Status; /* used to chek if P2P Server is enabled to Notify */
+  P2P_LedCharValue_t    LedControl;
+  P2P_ButtonCharValue_t ButtonControl;
+  uint16_t              ConnectionHandle;
+} P2P_Server_App_Context_t;
+/* USER CODE END PTD */
+
+/* Private defines ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+/**
+ * START of Section BLE_APP_CONTEXT
+ */
+
+PLACE_IN_SECTION("BLE_APP_CONTEXT") static P2P_Server_App_Context_t P2P_Server_App_Context;
+
+/**
+ * END of Section BLE_APP_CONTEXT
+ */
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+static void P2PS_Send_Notification(void);
+static void P2PS_APP_LED_BUTTON_context_Init(void);
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void P2PS_STM_App_Notification(P2PS_STM_App_Notification_evt_t *pNotification)
+{
+/* USER CODE BEGIN P2PS_STM_App_Notification_1 */
+
+/* USER CODE END P2PS_STM_App_Notification_1 */
+  switch(pNotification->P2P_Evt_Opcode)
+  {
+/* USER CODE BEGIN P2PS_STM_App_Notification_P2P_Evt_Opcode */
+#if(BLE_CFG_OTA_REBOOT_CHAR != 0)
+    case P2PS_STM_BOOT_REQUEST_EVT:
+      APP_DBG_MSG("-- P2P APPLICATION SERVER : BOOT REQUESTED\n");
+      APP_DBG_MSG(" \n\r");
+
+      *(uint32_t*)SRAM1_BASE = *(uint32_t*)pNotification->DataTransfered.pPayload;
+      NVIC_SystemReset();
+      break;
+#endif
+/* USER CODE END P2PS_STM_App_Notification_P2P_Evt_Opcode */
+
+    case P2PS_STM__NOTIFY_ENABLED_EVT:
+/* USER CODE BEGIN P2PS_STM__NOTIFY_ENABLED_EVT */
+      P2P_Server_App_Context.Notification_Status = 1;
+      APP_DBG_MSG("-- P2P APPLICATION SERVER : NOTIFICATION ENABLED\n"); 
+      APP_DBG_MSG(" \n\r");
+/* USER CODE END P2PS_STM__NOTIFY_ENABLED_EVT */
+      break;
+
+    case P2PS_STM_NOTIFY_DISABLED_EVT:
+/* USER CODE BEGIN P2PS_STM_NOTIFY_DISABLED_EVT */
+      P2P_Server_App_Context.Notification_Status = 0;
+      APP_DBG_MSG("-- P2P APPLICATION SERVER : NOTIFICATION DISABLED\n");
+      APP_DBG_MSG(" \n\r");
+/* USER CODE END P2PS_STM_NOTIFY_DISABLED_EVT */
+      break;
+      
+    case P2PS_STM_WRITE_EVT:
+/* USER CODE BEGIN P2PS_STM_WRITE_EVT */
+      if(pNotification->DataTransfered.pPayload[0] == 0x00){ /* ALL Deviceselected - may be necessary as LB Routeur informs all connection */
+        if(pNotification->DataTransfered.pPayload[1] == 0x01)
+        {
+          BSP_LED_On(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER  : LED1 ON\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x01; /* LED1 ON */
+        }
+        if(pNotification->DataTransfered.pPayload[1] == 0x00)
+        {
+          BSP_LED_Off(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER  : LED1 OFF\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x00; /* LED1 OFF */
+        }
+      }
+#if(P2P_SERVER1 != 0)  
+      if(pNotification->DataTransfered.pPayload[0] == 0x01){ /* end device 1 selected - may be necessary as LB Routeur informs all connection */
+        if(pNotification->DataTransfered.pPayload[1] == 0x01)
+        {
+          BSP_LED_On(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER 1 : LED1 ON\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x01; /* LED1 ON */
+        }
+        if(pNotification->DataTransfered.pPayload[1] == 0x00)
+        {
+          BSP_LED_Off(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER 1 : LED1 OFF\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x00; /* LED1 OFF */
+        }
+      }
+#endif
+#if(P2P_SERVER2 != 0)
+      if(pNotification->DataTransfered.pPayload[0] == 0x02){ /* end device 2 selected */ 
+        if(pNotification->DataTransfered.pPayload[1] == 0x01)
+        {
+          BSP_LED_On(LED_BLUE);
+           APP_DBG_MSG("-- P2P APPLICATION SERVER 2 : LED1 ON\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x01; /* LED1 ON */
+        }
+        if(pNotification->DataTransfered.pPayload[1] == 0x00)
+        {
+          BSP_LED_Off(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER 2 : LED1 OFF\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x00; /* LED1 OFF */
+        }   
+      }
+#endif      
+#if(P2P_SERVER3 != 0)  
+      if(pNotification->DataTransfered.pPayload[0] == 0x03){ /* end device 3 selected - may be necessary as LB Routeur informs all connection */
+        if(pNotification->DataTransfered.pPayload[1] == 0x01)
+        {
+          BSP_LED_On(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER 3 : LED1 ON\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x01; /* LED1 ON */
+        }
+        if(pNotification->DataTransfered.pPayload[1] == 0x00)
+        {
+          BSP_LED_Off(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER 3 : LED1 OFF\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x00; /* LED1 OFF */
+        }
+      }
+#endif
+#if(P2P_SERVER4 != 0)
+      if(pNotification->DataTransfered.pPayload[0] == 0x04){ /* end device 4 selected */ 
+        if(pNotification->DataTransfered.pPayload[1] == 0x01)
+        {
+          BSP_LED_On(LED_BLUE);
+           APP_DBG_MSG("-- P2P APPLICATION SERVER 2 : LED1 ON\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x01; /* LED1 ON */
+        }
+        if(pNotification->DataTransfered.pPayload[1] == 0x00)
+        {
+          BSP_LED_Off(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER 2 : LED1 OFF\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x00; /* LED1 OFF */
+        }   
+      }
+#endif     
+#if(P2P_SERVER5 != 0)  
+      if(pNotification->DataTransfered.pPayload[0] == 0x05){ /* end device 5 selected - may be necessary as LB Routeur informs all connection */
+        if(pNotification->DataTransfered.pPayload[1] == 0x01)
+        {
+          BSP_LED_On(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER 5 : LED1 ON\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x01; /* LED1 ON */
+        }
+        if(pNotification->DataTransfered.pPayload[1] == 0x00)
+        {
+          BSP_LED_Off(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER 5 : LED1 OFF\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x00; /* LED1 OFF */
+        }
+      }
+#endif
+#if(P2P_SERVER6 != 0)
+      if(pNotification->DataTransfered.pPayload[0] == 0x06){ /* end device 6 selected */ 
+        if(pNotification->DataTransfered.pPayload[1] == 0x01)
+        {
+          BSP_LED_On(LED_BLUE);
+           APP_DBG_MSG("-- P2P APPLICATION SERVER 6 : LED1 ON\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x01; /* LED1 ON */
+        }
+        if(pNotification->DataTransfered.pPayload[1] == 0x00)
+        {
+          BSP_LED_Off(LED_BLUE);
+          APP_DBG_MSG("-- P2P APPLICATION SERVER 6 : LED1 OFF\n"); 
+          APP_DBG_MSG(" \n\r");
+          P2P_Server_App_Context.LedControl.Led1=0x00; /* LED1 OFF */
+        }   
+      }
+#endif 
+/* USER CODE END P2PS_STM_WRITE_EVT */
+      break;
+
+    default:
+/* USER CODE BEGIN P2PS_STM_App_Notification_default */
+      
+/* USER CODE END P2PS_STM_App_Notification_default */
+      break;
+  }
+/* USER CODE BEGIN P2PS_STM_App_Notification_2 */
+
+/* USER CODE END P2PS_STM_App_Notification_2 */
+  return;
+}
+
+void P2PS_APP_Notification(P2PS_APP_ConnHandle_Not_evt_t *pNotification)
+{
+/* USER CODE BEGIN P2PS_APP_Notification_1 */
+
+/* USER CODE END P2PS_APP_Notification_1 */
+  switch(pNotification->P2P_Evt_Opcode)
+  {
+/* USER CODE BEGIN P2PS_APP_Notification_P2P_Evt_Opcode */
+
+/* USER CODE END P2PS_APP_Notification_P2P_Evt_Opcode */
+  case PEER_CONN_HANDLE_EVT :
+/* USER CODE BEGIN PEER_CONN_HANDLE_EVT */
+          
+/* USER CODE END PEER_CONN_HANDLE_EVT */
+    break;
+
+    case PEER_DISCON_HANDLE_EVT :
+/* USER CODE BEGIN PEER_DISCON_HANDLE_EVT */
+       P2PS_APP_LED_BUTTON_context_Init();       
+/* USER CODE END PEER_DISCON_HANDLE_EVT */
+    break;
+    
+    default:
+/* USER CODE BEGIN P2PS_APP_Notification_default */
+
+/* USER CODE END P2PS_APP_Notification_default */
+      break;
+  }
+/* USER CODE BEGIN P2PS_APP_Notification_2 */
+
+/* USER CODE END P2PS_APP_Notification_2 */
+  return;
+}
+
+void P2PS_APP_Init(void)
+{
+/* USER CODE BEGIN P2PS_APP_Init */
+  UTIL_SEQ_RegTask( 1<< CFG_TASK_SW1_BUTTON_PUSHED_ID, UTIL_SEQ_RFU, P2PS_Send_Notification );
+
+  /**
+   * Initialize LedButton Service
+   */
+  P2P_Server_App_Context.Notification_Status=0; 
+  P2PS_APP_LED_BUTTON_context_Init();
+/* USER CODE END P2PS_APP_Init */
+  return;
+}
+
+/* USER CODE BEGIN FD */
+void P2PS_APP_LED_BUTTON_context_Init(void){
+  
+  BSP_LED_Off(LED_BLUE);
+  
+  #if(P2P_SERVER1 != 0)
+  P2P_Server_App_Context.LedControl.Device_Led_Selection=0x01; /* Device1 */
+  P2P_Server_App_Context.LedControl.Led1=0x00; /* led OFF */
+  P2P_Server_App_Context.ButtonControl.Device_Button_Selection=0x01;/* Device1 */
+  P2P_Server_App_Context.ButtonControl.ButtonStatus=0x00;
+#endif
+#if(P2P_SERVER2 != 0)
+  P2P_Server_App_Context.LedControl.Device_Led_Selection=0x02; /* Device2 */
+  P2P_Server_App_Context.LedControl.Led1=0x00; /* led OFF */
+  P2P_Server_App_Context.ButtonControl.Device_Button_Selection=0x02;/* Device2 */
+  P2P_Server_App_Context.ButtonControl.ButtonStatus=0x00;
+#endif  
+#if(P2P_SERVER3 != 0)
+  P2P_Server_App_Context.LedControl.Device_Led_Selection=0x03; /* Device3 */
+  P2P_Server_App_Context.LedControl.Led1=0x00; /* led OFF */
+  P2P_Server_App_Context.ButtonControl.Device_Button_Selection=0x03; /* Device3 */
+  P2P_Server_App_Context.ButtonControl.ButtonStatus=0x00;
+#endif
+#if(P2P_SERVER4 != 0)
+  P2P_Server_App_Context.LedControl.Device_Led_Selection=0x04; /* Device4 */
+  P2P_Server_App_Context.LedControl.Led1=0x00; /* led OFF */
+  P2P_Server_App_Context.ButtonControl.Device_Button_Selection=0x04; /* Device4 */
+  P2P_Server_App_Context.ButtonControl.ButtonStatus=0x00;
+#endif  
+ #if(P2P_SERVER5 != 0)
+  P2P_Server_App_Context.LedControl.Device_Led_Selection=0x05; /* Device5 */
+  P2P_Server_App_Context.LedControl.Led1=0x00; /* led OFF */
+  P2P_Server_App_Context.ButtonControl.Device_Button_Selection=0x05; /* Device5 */
+  P2P_Server_App_Context.ButtonControl.ButtonStatus=0x00;
+#endif
+#if(P2P_SERVER6 != 0)
+  P2P_Server_App_Context.LedControl.Device_Led_Selection=0x06; /* device6 */
+  P2P_Server_App_Context.LedControl.Led1=0x00; /* led OFF */
+  P2P_Server_App_Context.ButtonControl.Device_Button_Selection=0x06; /* Device6 */
+  P2P_Server_App_Context.ButtonControl.ButtonStatus=0x00;
+#endif  
+}
+
+void P2PS_APP_SW1_Button_Action(void)
+{
+  UTIL_SEQ_SetTask( 1<
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __P2P_SERVER_APP_H
+#define __P2P_SERVER_APP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+typedef enum
+{
+  PEER_CONN_HANDLE_EVT,
+  PEER_DISCON_HANDLE_EVT,
+} P2PS_APP__Opcode_Notification_evt_t;
+
+typedef struct
+{
+  P2PS_APP__Opcode_Notification_evt_t   P2P_Evt_Opcode;
+  uint16_t                              ConnectionHandle;
+}P2PS_APP_ConnHandle_Not_evt_t;
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void P2PS_APP_Init( void );
+  void P2PS_APP_Notification( P2PS_APP_ConnHandle_Not_evt_t *pNotification );
+/* USER CODE BEGIN EF */
+  void P2PS_APP_SW1_Button_Action( void );
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__P2P_SERVER_APP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/Target/hw_ipcc.c b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/Target/hw_ipcc.c
new file mode 100644
index 000000000..0f839543a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/STM32_WPAN/Target/hw_ipcc.c
@@ -0,0 +1,523 @@
+/**
+ ******************************************************************************
+  * File Name          : Target/hw_ipcc.c
+  * Description        : Hardware IPCC source file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "mbox_def.h"
+
+/* Global variables ---------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+#define HW_IPCC_TX_PENDING( channel ) ( !(LL_C1_IPCC_IsActiveFlag_CHx( IPCC, channel )) ) &&  (((~(IPCC->C1MR)) & (channel << 16U)))
+#define HW_IPCC_RX_PENDING( channel )  (LL_C2_IPCC_IsActiveFlag_CHx( IPCC, channel )) && (((~(IPCC->C1MR)) & (channel << 0U)))
+
+/* Private macros ------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static void (*FreeBufCb)( void );
+
+/* Private function prototypes -----------------------------------------------*/
+static void HW_IPCC_BLE_EvtHandler( void );
+static void HW_IPCC_BLE_AclDataEvtHandler( void );
+static void HW_IPCC_MM_FreeBufHandler( void );
+static void HW_IPCC_SYS_CmdEvtHandler( void );
+static void HW_IPCC_SYS_EvtHandler( void );
+static void HW_IPCC_TRACES_EvtHandler( void );
+
+#ifdef THREAD_WB
+static void HW_IPCC_OT_CmdEvtHandler( void );
+static void HW_IPCC_THREAD_NotEvtHandler( void );
+static void HW_IPCC_THREAD_CliNotEvtHandler( void );
+#endif
+
+#ifdef MAC_802_15_4_WB
+static void HW_IPCC_MAC_802_15_4_CmdEvtHandler( void );
+static void HW_IPCC_MAC_802_15_4_NotEvtHandler( void );
+#endif
+
+#ifdef ZIGBEE_WB
+static void HW_IPCC_ZIGBEE_CmdEvtHandler( void );
+static void HW_IPCC_ZIGBEE_StackNotifEvtHandler( void );
+static void HW_IPCC_ZIGBEE_CliNotifEvtHandler( void );
+#endif
+
+/* Public function definition -----------------------------------------------*/
+
+/******************************************************************************
+ * INTERRUPT HANDLER
+ ******************************************************************************/
+void HW_IPCC_Rx_Handler( void )
+{
+  if (HW_IPCC_RX_PENDING( HW_IPCC_SYSTEM_EVENT_CHANNEL ))
+  {
+      HW_IPCC_SYS_EvtHandler();
+  }
+#ifdef MAC_802_15_4_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_MAC_802_15_4_NotEvtHandler();
+  }
+#endif /* MAC_802_15_4_WB */
+#ifdef THREAD_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_THREAD_NotEvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_THREAD_CliNotEvtHandler();
+  }
+#endif /* THREAD_WB */
+#ifdef ZIGBEE_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_ZIGBEE_StackNotifEvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
+  {
+      HW_IPCC_ZIGBEE_CliNotifEvtHandler();
+  }
+#endif /* ZIGBEE_WB */
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_BLE_EVENT_CHANNEL ))
+  {
+    HW_IPCC_BLE_EvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_TRACES_CHANNEL ))
+  {
+    HW_IPCC_TRACES_EvtHandler();
+  }
+
+  return;
+}
+
+void HW_IPCC_Tx_Handler( void )
+{
+  if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_SYS_CmdEvtHandler();
+  }
+#ifdef MAC_802_15_4_WB
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_MAC_802_15_4_CmdEvtHandler();
+  }
+#endif /* MAC_802_15_4_WB */
+#ifdef THREAD_WB
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_OT_CmdEvtHandler();
+  }
+#endif /* THREAD_WB */
+#ifdef ZIGBEE_WB
+  if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
+  {
+      HW_IPCC_ZIGBEE_CmdEvtHandler();
+  }
+#endif /* ZIGBEE_WB */
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_SYS_CmdEvtHandler();
+  }
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ))
+  {
+    HW_IPCC_MM_FreeBufHandler();
+  }
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_HCI_ACL_DATA_CHANNEL ))
+  {
+    HW_IPCC_BLE_AclDataEvtHandler();
+  }
+
+  return;
+}
+/******************************************************************************
+ * GENERAL
+ ******************************************************************************/
+void HW_IPCC_Enable( void )
+{
+  /**
+   * When the device is out of standby, it is required to use the EXTI mechanism to wakeup CPU2
+   */
+  LL_C2_EXTI_EnableEvent_32_63( LL_EXTI_LINE_41 );
+  LL_EXTI_EnableRisingTrig_32_63( LL_EXTI_LINE_41 );
+	
+  /**
+   * In case the SBSFU is implemented, it may have already set the C2BOOT bit to startup the CPU2.
+   * In that case, to keep the mechanism transparent to the user application, it shall call the system command
+   * SHCI_C2_Reinit( ) before jumping to the application.
+   * When the CPU2 receives that command, it waits for its event input to be set to restart the CPU2 firmware.
+   * This is required because once C2BOOT has been set once, a clear/set on C2BOOT has no effect.
+   * When SHCI_C2_Reinit( ) is not called, generating an event to the CPU2 does not have any effect
+   * So, by default, the application shall both set the event flag and set the C2BOOT bit.
+   */
+  __SEV( );       /* Set the internal event flag and send an event to the CPU2 */
+  __WFE( );       /* Clear the internal event flag */
+  LL_PWR_EnableBootC2( );
+
+  return;
+}
+
+void HW_IPCC_Init( void )
+{
+  LL_AHB3_GRP1_EnableClock( LL_AHB3_GRP1_PERIPH_IPCC );
+
+  LL_C1_IPCC_EnableIT_RXO( IPCC );
+  LL_C1_IPCC_EnableIT_TXF( IPCC );
+
+  HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn);
+  HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn);
+
+  return;
+}
+
+/******************************************************************************
+ * BLE
+ ******************************************************************************/
+void HW_IPCC_BLE_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_BLE_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_BLE_CMD_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_BLE_EvtHandler( void )
+{
+  HW_IPCC_BLE_RxEvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_BLE_SendAclData( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_BLE_AclDataEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+
+  HW_IPCC_BLE_AclDataAckNot();
+
+  return;
+}
+
+__weak void HW_IPCC_BLE_AclDataAckNot( void ){};
+__weak void HW_IPCC_BLE_RxEvtNot( void ){};
+
+/******************************************************************************
+ * SYSTEM
+ ******************************************************************************/
+void HW_IPCC_SYS_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_SYS_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_SYS_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+
+  HW_IPCC_SYS_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_SYS_EvtHandler( void )
+{
+  HW_IPCC_SYS_EvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
+
+  return;
+}
+
+__weak void HW_IPCC_SYS_CmdEvtNot( void ){};
+__weak void HW_IPCC_SYS_EvtNot( void ){};
+
+/******************************************************************************
+ * MAC 802.15.4
+ ******************************************************************************/
+#ifdef MAC_802_15_4_WB
+void HW_IPCC_MAC_802_15_4_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_MAC_802_15_4_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_MAC_802_15_4_SendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_MAC_802_15_4_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+
+  HW_IPCC_MAC_802_15_4_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_MAC_802_15_4_NotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_MAC_802_15_4_EvtNot();
+
+  return;
+}
+__weak void HW_IPCC_MAC_802_15_4_CmdEvtNot( void ){};
+__weak void HW_IPCC_MAC_802_15_4_EvtNot( void ){};
+#endif
+
+/******************************************************************************
+ * THREAD
+ ******************************************************************************/
+#ifdef THREAD_WB
+void HW_IPCC_THREAD_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_OT_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_CLI_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_THREAD_SendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_THREAD_CliSendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_OT_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  HW_IPCC_OT_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_THREAD_NotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_THREAD_EvtNot();
+
+  return;
+}
+
+static void HW_IPCC_THREAD_CliNotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_THREAD_CliEvtNot();
+
+  return;
+}
+
+__weak void HW_IPCC_OT_CmdEvtNot( void ){};
+__weak void HW_IPCC_CLI_CmdEvtNot( void ){};
+__weak void HW_IPCC_THREAD_EvtNot( void ){};
+
+#endif /* THREAD_WB */
+
+/******************************************************************************
+ * ZIGBEE
+ ******************************************************************************/
+#ifdef ZIGBEE_WB
+void HW_IPCC_ZIGBEE_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendAppliCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendCliCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
+
+   return;
+}
+
+void HW_IPCC_ZIGBEE_SendAppliCmdAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendCliCmdAck( void )
+{
+    LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+    LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_CmdEvtHandler( void )
+{
+    LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+    HW_IPCC_ZIGBEE_AppliCmdNotification();
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_StackNotifEvtHandler( void )
+{
+    LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+    HW_IPCC_ZIGBEE_AppliAsyncEvtNotification();
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_CliNotifEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_ZIGBEE_CliEvtNotification();
+
+  return;
+}
+
+__weak void HW_IPCC_ZIGBEE_AppliCmdNotification( void ){};
+__weak void HW_IPCC_ZIGBEE_AppliAsyncEvtNotification( void ){};
+__weak void HW_IPCC_ZIGBEE_CliEvtNotification( void ){};
+#endif /* ZIGBEE_WB */
+
+/******************************************************************************
+ * MEMORY MANAGER
+ ******************************************************************************/
+void HW_IPCC_MM_SendFreeBuf( void (*cb)( void ) )
+{
+  if ( LL_C1_IPCC_IsActiveFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ) )
+  {
+    FreeBufCb = cb;
+    LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+  }
+  else
+  {
+    cb();
+
+    LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+  }
+
+  return;
+}
+
+static void HW_IPCC_MM_FreeBufHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+
+  FreeBufCb();
+
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+
+  return;
+}
+
+/******************************************************************************
+ * TRACES
+ ******************************************************************************/
+void HW_IPCC_TRACES_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_TRACES_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_TRACES_EvtHandler( void )
+{
+  HW_IPCC_TRACES_EvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_TRACES_CHANNEL );
+
+  return;
+}
+
+__weak void HW_IPCC_TRACES_EvtNot( void ){};
+
+/******************* (C) COPYRIGHT 2019 STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/readme.txt b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/readme.txt
new file mode 100644
index 000000000..f35ca6380
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/BLE/BLE_p2pServer_ota/readme.txt
@@ -0,0 +1,141 @@
+/**
+  @page BLE_p2pServer_ota Application
+
+  @verbatim
+  ******************************************************************************
+  * @file    BLE/BLE_p2pServer_ota/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the BLE_p2pServer_ota application
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                               www.st.com/SLA0044
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Application Description
+
+This example is to demonstrate Point-to-Point communication using BLE component. 
+
+Two STM32WB35xx boards are used, one acting as GATT client, and one as GATT server.
+For example, BLE P2P_Client application is downloaded a Nucleo board (MB1507A) and BLE_p2pServer_ota application in a Nucleo board (MB1507A).
+The client could be located in a phone also, using the ST BLE Sensor application instead of the MB1507A board.
+
+@note This application is not supported by CubeMx but has been copied from the project BLE_p2pServer generated
+      by CubeMx with some modifications in order to be able to download it with the BLE_Ota application.
+	  The steps to be done to move from the BLE_p2pServer application to the BLE_p2pServer_ota application are :
+	  - Copy the full folder BLE_p2pServer
+	  - Replace the linker file stm32wb35xx_flash_cm4.icf by stm32wb35xx_flash_cm4_ota.icf ( this adds the placement
+	  of the two sections TAG_OTA_START and TAG_OTA_END ).
+	  - Remove the update of SCB->VTOR in the file system_stm32wbxx.c ( The VTOR is already set by the BLE_Ota application
+	  and shall not be changed to a different value)
+          - set BLE_CFG_OTA_REBOOT_CHAR to 1 in ble_conf.h
+	
+@par Directory contents 
+  
+  - BLE/BLE_p2pServer_ota/Core/Inc/stm32wbxx_hal_conf.h			HAL configuration file
+  - BLE/BLE_p2pServer_ota/Core/Inc/stm32wbxx_it.h          		Interrupt handlers header file
+  - BLE/BLE_p2pServer_ota/Core/Inc/main.h                  		Header for main.c module
+  - BLE/BLE_p2pServer_ota/STM32_WPAN/App/app_ble.h           	Header for app_ble.c module
+  - BLE/BLE_p2pServer_ota/Core/Inc/app_common.h            		Header for all modules with common definition
+  - BLE/BLE_p2pServer_ota/Core/Inc/app_conf.h              		Parameters configuration file of the application
+  - BLE/BLE_p2pServer_ota/Core/Inc/app_entry.h            		Parameters configuration file of the application
+  - BLE/BLE_p2pServer_ota/STM32_WPAN/App/ble_conf.h            	BLE Services configuration
+  - BLE/BLE_p2pServer_ota/STM32_WPAN/App/ble_dbg_conf.h        	BLE Traces configuration of the BLE services
+  - BLE/BLE_p2pServer_ota/STM32_WPAN/App/p2p_server_app.h      	Header for p2p_server_app.c module
+  - BLE/BLE_p2pServer_ota/Core/Inc/hw_conf.h           			Configuration file of the HW
+  - BLE/BLE_p2pServer_ota/Core/Inc/utilities_conf.h    			Configuration file of the utilities
+  - BLE/BLE_p2pServer_ota/Core/Src/stm32wbxx_it.c          		Interrupt handlers
+  - BLE/BLE_p2pServer_ota/Core/Src/main.c                  		Main program
+  - BLE/BLE_p2pServer_ota/Core/Src/system_stm32wbxx.c      		stm32wbxx system source file
+  - BLE/BLE_p2pServer_ota/STM32_WPAN/App/app_ble.c      		BLE Profile implementation
+  - BLE/BLE_p2pServer_ota/Core/Src/app_entry.c      			Initialization of the application
+  - BLE/BLE_p2pServer_ota/STM32_WPAN/App/p2p_server_app.c   	P2P Server application
+  - BLE/BLE_p2pServer_ota/STM32_WPAN/Target/hw_ipcc.c      		IPCC Driver
+  - BLE/BLE_p2pServer_ota/Core/Src/stm32_lpm_if.c				Low Power Manager Interface
+  - BLE/BLE_p2pServer_ota/Core/Src/hw_timerserver.c 			Timer Server based on RTC
+  - BLE/BLE_p2pServer_ota/Core/Src/hw_uart.c 					UART Driver
+  
+@par Hardware and Software environment
+
+    - This application runs on STM32WB35xx devices, Nucleo boards (MB1507A)
+    
+    - Nucleo board (MB1507A) Set-up    
+       - Connect the USB Nucleo board to your PC with a USB cable type A to mini-B to ST-LINK connector (USB_STLINK)
+       - Please ensure that the ST-LINK connectors and jumpers are fitted.
+    
+    - Nucleo board (MB1507A) Set-up    
+       - Connect the Nucleo Board to your PC with a USB cable type A to mini-B to ST-LINK connector (USB_STLINK).
+       - Please ensure that the ST-LINK connectors and jumpers are fitted.
+
+@par How to use it ? 
+
+This application requests having the stm32wb3x_BLE_Stack_fw.bin binary flashed on the Wireless Coprocessor.
+If it is not the case, you need to use STM32CubeProgrammer to load the appropriate binary.
+All available binaries are located under /Projects/STM32_Copro_Wireless_Binaries directory.
+Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the detailed procedure to change the
+Wireless Coprocessor binary.  
+   
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load the image into Target memory
+ - OR use the BLE_p2pServer_ota_reference.bin from Binary directory
+   - to be flashed at 0x0800 7000
+ - This must be done for BLE_p2pServer (MB1507A) 
+
+First demonstration
+On the android/ios device, enable the Bluetooth communications, and if not done before,
+ - Install the ST BLE Profile application on the android device
+	https://play.google.com/store/apps/details?id=com.stm.bluetoothlevalidation&hl=en
+    https://itunes.apple.com/fr/App/st-ble-profile/id1081331769?mt=8
+
+ - Install the ST BLE Sensor application on the ios/android device
+	https://play.google.com/store/apps/details?id=com.st.bluems
+	https://itunes.apple.com/us/App/st-bluems/id993670214?mt=8
+
+ - Power on the Nucleo board with the BLE_P2P_Server application
+ - Then, click on the App icon, ST BLE Sensor (android device)
+ - connect to the device
+ - select the P2PSRVx in the device list and play with the Light and the SW1 button of the board
+
+
+Second demonstration
+ - BLE_p2pServer may be connected by BLE_p2pClient.
+ - Once the code (BLE_p2pServer & BLE_p2pClient) is downloaded into the two STM32WB35xx boards and executed, the modules are initialized. 
+ 
+ - BLE_p2pServer may be connected by BLE_p2pClient.
+ - Once the code (BLE_p2pServer & BLE_p2pClient) is downloaded into the two STM32WB35xx boards and executed, the modules are initialized. 
+
+ - The Peripheral device (BLE_p2pServer) starts advertising (during 1 minute), the green led blinks for each advertising event.
+ - The Central device (BLE_p2pClient) starts scanning when pressing the User button (SW1). 
+   - BLE_p2pClient blue led becomes on. 
+   - Scan req takes about 5 seconds.
+   - Make sure BLE_p2pServer advertises, if not press reset button or switch off/on to restart advertising.
+ - Then, it automatically connects to the BLE_p2pServer. 
+   - Blue led turns off and green led starts blinking as on the MB1507A. Connection is done.
+ - When pressing SW1 on a board, the blue led toggles on the other one.
+   - The SW1 button can be pressed independently on the GATT Client or on the GATT Server.
+ - When the server is located on a MB1507A, the connection interval can be modified from 50ms to 1s and vice-versa using SW2. 
+ - The green led on the 2 boards blinks for each advertising event, it means quickly when 50ms and slowly when 1s. 
+ - Passing from 50ms to 1s is instantaneous, but from 1s to 50ms takes around 10 seconds.
+ - The SW1 event, switch on/off blue led, depends on the connection Interval event. 
+   - So the delay from SW1 action and blue led change is more or less fast.
+
+Third demonstration
+Move to download panel with the smart Phone Application 
+ - select the binary to be downloaded on the Application Processor
+   -  BLE_HeartRate_ota_reference.bin or BLE_p2pServer_ota_reference.bin have to be copied into Smart phone directory
+ - Start download
+ - New Application is running and can be connected   
+   
+For more details refer to the Application Note: 
+  AN5289 - Building a Wireless application 
+ 
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/.extSettings b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/.extSettings
new file mode 100644
index 000000000..3b432df5f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/.extSettings
@@ -0,0 +1,12 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE;..\..\..\..\..\..\Drivers\BSP\Adafruit_Shield;..\..\..\..\..\..\Drivers\BSP\Components;..\..\..\..\..\..\Drivers\BSP\Components\Common
+[Others]
+Define=USE_STM32WBXX_NUCLEO
+HALModule=SPI
+[Groups]
+Application/User/Core=../Core/Src/main.c;../Core/Src/stm32wbxx_it.c;../Core/Src/stm32wbxx_hal_msp.c;
+Doc=../readme.txt;
+Drivers/BSP/Adafruit_Shield=../../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_sd.c;../../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_lcd.c;
+Drivers/BSP/Components=../../../../../../Drivers/BSP/Components/st7735/st7735.c;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
+Drivers/STM32WBxx_HAL_Driver=../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c;../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c;
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Inc/main.h b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Inc/main.h
new file mode 100644
index 000000000..41b101791
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Inc/main.h
@@ -0,0 +1,76 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FatFs/FatFs_uSD_Standalone/Core/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "stm32_adafruit_sd.h"
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+#define LED_OK                     LED2
+#define LED_ERROR                  LED3
+#define APP_OK                     0
+#define APP_ERROR                  -1
+#define APP_INIT                   1
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..afd5aac3b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+#define HAL_SPI_MODULE_ENABLED
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..399e01150
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FatFs/FatFs_uSD_Standalone/Core/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Src/main.c b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Src/main.c
new file mode 100644
index 000000000..9ee50c291
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Src/main.c
@@ -0,0 +1,222 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FatFs/FatFs_uSD_Standalone/Core/Src/main.c
+  * @author  MCD Application Team
+  * @brief   Main program body
+  *          This sample code shows how to use FatFs with uSD card drive.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "app_fatfs.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+__IO int32_t ProcessStatus = 0;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+  
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* Configure LED_OK and LED_ERROR */
+  BSP_LED_Init(LED_OK);
+  BSP_LED_Init(LED_ERROR);
+
+  /* Initialize the micro SD Card */
+  BSP_SD_Init();
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  if (MX_FATFS_Init() != APP_OK) {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+ 
+ 
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    ProcessStatus = MX_FATFS_Process();
+    /* Call middleware background task */
+    if (ProcessStatus == APP_ERROR)
+    {
+      Error_Handler();
+    }
+    else
+    {
+      BSP_LED_Off(LED_ERROR);
+      BSP_LED_On(LED_OK);
+    }
+
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  BSP_LED_Off(LED_OK);
+  BSP_LED_On(LED_ERROR);
+  while(1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..96b142032
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,82 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FatFs/FatFs_uSD_Standalone/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This file provides code for the MSP Initialization
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+extern void Error_Handler(void);
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..a6405c46f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Src/stm32wbxx_it.c
@@ -0,0 +1,205 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FatFs/FatFs_uSD_Standalone/Core/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..4cb9e0e42
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/Core/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx) || defined(STM32WB5Mxx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/FatFs_uSD_Standalone.ewd b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/FatFs_uSD_Standalone.ewd
new file mode 100644
index 000000000..8bd362085
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/FatFs_uSD_Standalone.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		FatFs_uSD_Standalone
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/FatFs_uSD_Standalone.ewp b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/FatFs_uSD_Standalone.ewp
new file mode 100644
index 000000000..71f4828a6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/FatFs_uSD_Standalone.ewp
@@ -0,0 +1,1183 @@
+
+
+  3
+  
+    FatFs_uSD_Standalone
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        Core
+        
+          $PROJ_DIR$/../Core/Src/main.c
+        
+        
+          $PROJ_DIR$/../Core/Src/stm32wbxx_it.c
+        
+        
+          $PROJ_DIR$/../Core/Src/stm32wbxx_hal_msp.c
+        
+      
+      
+        FATFS
+        
+          Target
+          
+            $PROJ_DIR$/../FATFS/Target/sd_diskio.c
+          
+        
+        
+          App
+          
+            $PROJ_DIR$/../FATFS/App/app_fatfs.c
+          
+        
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        Adafruit_Shield
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_sd.c
+        
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_lcd.c
+        
+      
+      
+        Components
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/Components/st7735/st7735.c
+        
+      
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Core/Src/system_stm32wbxx.c
+      
+    
+  
+  
+    Middlewares
+    
+      FatFs
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FatFs/src/diskio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FatFs/src/ff.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FatFs/src/ff_gen_drv.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FatFs/src/option/syscall.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/Project.eww
new file mode 100644
index 000000000..7e77ae9b4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\FatFs_uSD_Standalone.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..52725db75
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/stm32wb35xx_sram_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/stm32wb35xx_sram_cm4.icf
new file mode 100644
index 000000000..c654ec05b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/EWARM/stm32wb35xx_sram_cm4.icf
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20003FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20004000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20008000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x2000FFFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/App/app_fatfs.c b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/App/app_fatfs.c
new file mode 100644
index 000000000..5682d85fa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/App/app_fatfs.c
@@ -0,0 +1,234 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FatFs/FatFs_uSD_Standalone/FatFs/App/app_fatfs.c
+  * @author  MCD Application Team
+  * @brief   FatFs_uSD_Standalone application file
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_fatfs.h"
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+typedef enum {
+  APPLICATION_IDLE = 0,
+  APPLICATION_INIT,
+  APPLICATION_RUNNING,
+}FS_FileOperationsTypeDef;
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define FATFS_MKFS_ALLOWED 1
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+FATFS SDFatFs;    /* File system object for SD logical drive */
+FIL SDFile;       /* File  object for SD */
+char SDPath[4];   /* SD logical drive path */
+/* USER CODE BEGIN PV */
+FS_FileOperationsTypeDef Appli_state = APPLICATION_IDLE;
+uint8_t workBuffer[_MAX_SS];
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+static int32_t FS_FileOperations(void);
+static uint8_t Buffercmp(uint32_t* pBuffer1, uint32_t* pBuffer2, uint16_t BufferLength);
+/* USER CODE END PFP */
+
+/**
+  * @brief  FatFs initialization
+  * @param  None
+  * @retval Initialization result 
+  */
+int32_t MX_FATFS_Init(void) 
+{
+  /*## FatFS: Link the disk I/O driver(s)  ###########################*/
+  if (FATFS_LinkDriver(&SD_Driver, SDPath) != 0)
+  /* USER CODE BEGIN FATFS_Init */
+  {
+    return APP_ERROR;
+  }
+  else
+  {
+    Appli_state = APPLICATION_INIT;
+    return APP_OK;
+  }
+  /* USER CODE END FATFS_Init */
+}
+
+/**
+  * @brief  FatFs application main process
+  * @param  None
+  * @retval Process result 
+  */
+int32_t MX_FATFS_Process(void)
+{
+  /* USER CODE BEGIN FATFS_Process */
+  int32_t process_res = APP_OK;
+  /* Mass Storage Application State Machine */
+  switch(Appli_state)
+  {
+  case APPLICATION_INIT:
+    if(BSP_SD_GetCardState() == BSP_SD_OK)
+    {
+#if FATFS_MKFS_ALLOWED
+      FRESULT res;
+
+      res = f_mkfs(SDPath, FM_ANY, 0, workBuffer, sizeof(workBuffer));
+
+      if (res != FR_OK)
+      {
+        process_res = APP_ERROR;
+      }
+      else
+      {
+        process_res = APP_INIT;
+        Appli_state = APPLICATION_RUNNING;
+      }
+#else
+      process_res = APP_INIT;
+      Appli_state = APPLICATION_RUNNING;
+#endif
+    }
+    else
+    {
+    process_res = APP_ERROR;
+
+    }
+
+    break;
+  case APPLICATION_RUNNING:
+      process_res = FS_FileOperations();
+      Appli_state = APPLICATION_IDLE;
+    break;
+
+  case APPLICATION_IDLE:
+  default:
+    break;
+  }
+  return process_res;
+  /* USER CODE END FATFS_Process */
+}  
+
+/**
+  * @brief  Gets Time from RTC (generated when FS_NORTC==0; see ff.c)
+  * @param  None
+  * @retval Time in DWORD
+  */
+DWORD get_fattime(void)
+{
+  /* USER CODE BEGIN get_fattime */
+  return 0;
+  /* USER CODE END get_fattime */  
+}
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN Application */
+/**
+  * @brief File system : file operation
+  * @retval File operation result
+  */
+static int32_t FS_FileOperations(void)
+{
+  FRESULT res; /* FatFs function common result code */
+  uint32_t byteswritten, bytesread; /* File write/read counts */
+  uint8_t wtext[] = "This is STM32 working with FatFs and uSD diskio driver"; /* File write buffer */
+  uint8_t rtext[100]; /* File read buffer */
+
+  /* Register the file system object to the FatFs module */
+  if(f_mount(&SDFatFs, (TCHAR const*)SDPath, 0) == FR_OK)
+  {
+    /* Create and Open a new text file object with write access */
+    if(f_open(&SDFile, "STM32.TXT", FA_CREATE_ALWAYS | FA_WRITE) == FR_OK)
+    {
+      /* Write data to the text file */
+      res = f_write(&SDFile, wtext, sizeof(wtext), (void *)&byteswritten);
+
+      if((byteswritten > 0) && (res == FR_OK))
+      {
+        /* Close the open text file */
+        f_close(&SDFile);
+
+        /* Open the text file object with read access */
+        if(f_open(&SDFile, "STM32.TXT", FA_READ) == FR_OK)
+        {
+          /* Read data from the text file */
+          res = f_read(&SDFile, rtext, sizeof(rtext), (void *)&bytesread);
+
+          if((bytesread > 0) && (res == FR_OK))
+          {
+            /* Close the open text file */
+            f_close(&SDFile);
+
+            /* Compare read data with the expected data */
+            if((bytesread == byteswritten))
+            {
+              if(Buffercmp((uint32_t *)rtext, (uint32_t *)wtext, sizeof(rtext)))
+              {  /* Success of the demo: no error occurrence */
+                return 0;
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+  /* Error */
+  return -1;
+}
+
+
+/**
+  * @brief  Compares two buffers.
+  * @param  pBuffer1, pBuffer2: buffers to be compared.
+  * @param  BufferLength: buffer's length
+  * @retval 1: pBuffer identical to pBuffer1
+  *         0: pBuffer differs from pBuffer1
+  */
+static uint8_t Buffercmp(uint32_t* pBuffer1, uint32_t* pBuffer2, uint16_t BufferLength)
+{
+
+  while (BufferLength--)
+  {
+    if (*pBuffer1 != *pBuffer2)
+    {
+      return 1;
+    }
+
+    pBuffer1++;
+    pBuffer2++;
+  }
+
+  return 0;
+}
+
+/* USER CODE END Application */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/App/app_fatfs.h b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/App/app_fatfs.h
new file mode 100644
index 000000000..92869de5e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/App/app_fatfs.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FatFs/FatFs_uSD_Standalone/FatFsApp/Inc/app_fatfs.h
+  * @author  MCD Application Team
+  * @brief   Header for app_fatfs.c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_FATFS_H
+#define __APP_FATFS_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "ff.h"
+#include "ff_gen_drv.h"
+#include "sd_diskio.h" /* defines SD_Driver as external */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */     
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+int32_t MX_FATFS_Init(void);
+int32_t MX_FATFS_Process(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+extern FATFS SDFatFs;    /* File system object for SD logical drive */
+extern FIL SDFile;       /* File  object for SD */
+extern char SDPath[4];   /* SD logical drive path */
+
+#endif /*__APP_FATFS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/Target/ffconf.h b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/Target/ffconf.h
new file mode 100644
index 000000000..2f93a582d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/Target/ffconf.h
@@ -0,0 +1,272 @@
+/* USER CODE BEGIN Header */
+/**
+  ****************************************************************************** 
+  * FatFs - Generic FAT file system module R0.12c 
+  ****************************************************************************** 
+  * Copyright (C) 2017, ChaN, all right reserved.
+  * Copyright (C) 2017, STMicroelectronics, all right reserved. 
+  * 
+  * FatFs module is an open source software. Redistribution and use of FatFs in 
+  * source and binary forms, with or without modification, are permitted provided 
+  * that the following condition is met: 
+  * 
+  * 1. Redistributions of source code must retain the above copyright notice, 
+  * this condition and the following disclaimer. 
+  * 
+  * This software is provided by the copyright holder and contributors "AS IS" 
+  * and any warranties related to this software are DISCLAIMED. 
+  * The copyright owner or contributors be NOT LIABLE for any damages caused 
+  * by use of this software. 
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+#ifndef _FFCONF
+#define _FFCONF 68300	/* Revision ID */
+
+/*-----------------------------------------------------------------------------/
+/ Additional user header to be used  
+/-----------------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_hal.h"
+
+/*-----------------------------------------------------------------------------/
+/ Function Configurations
+/-----------------------------------------------------------------------------*/
+
+#define _FS_READONLY         0      /* 0:Read/Write or 1:Read only */
+/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
+/  Read-only configuration removes writing API functions, f_write(), f_sync(),
+/  f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
+/  and optional writing functions as well. */
+
+#define _FS_MINIMIZE         0      /* 0 to 3 */
+/* This option defines minimization level to remove some basic API functions.
+/
+/   0: All basic functions are enabled.
+/   1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
+/      are removed.
+/   2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
+/   3: f_lseek() function is removed in addition to 2. */
+
+#define _USE_STRFUNC         0      /* 0:Disable or 1-2:Enable */
+/* This option switches string functions, f_gets(), f_putc(), f_puts() and
+/  f_printf().
+/
+/  0: Disable string functions.
+/  1: Enable without LF-CRLF conversion.
+/  2: Enable with LF-CRLF conversion. */
+
+#define _USE_FIND            0
+/* This option switches filtered directory read functions, f_findfirst() and
+/  f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
+
+#define _USE_MKFS            1
+/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
+
+#define _USE_FASTSEEK        1
+/* This option switches fast seek feature. (0:Disable or 1:Enable) */
+
+#define	_USE_EXPAND		0
+/* This option switches f_expand function. (0:Disable or 1:Enable) */
+
+#define _USE_CHMOD		0
+/* This option switches attribute manipulation functions, f_chmod() and f_utime().
+/  (0:Disable or 1:Enable) Also _FS_READONLY needs to be 0 to enable this option. */
+
+#define _USE_LABEL           0
+/* This option switches volume label functions, f_getlabel() and f_setlabel().
+/  (0:Disable or 1:Enable) */
+
+#define _USE_FORWARD         0
+/* This option switches f_forward() function. (0:Disable or 1:Enable) */
+
+/*-----------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/-----------------------------------------------------------------------------*/
+
+#define _CODE_PAGE         850
+/* This option specifies the OEM code page to be used on the target system.
+/  Incorrect setting of the code page can cause a file open failure.
+/
+/   1   - ASCII (No extended character. Non-LFN cfg. only)
+/   437 - U.S.
+/   720 - Arabic
+/   737 - Greek
+/   771 - KBL
+/   775 - Baltic
+/   850 - Latin 1
+/   852 - Latin 2
+/   855 - Cyrillic
+/   857 - Turkish
+/   860 - Portuguese
+/   861 - Icelandic
+/   862 - Hebrew
+/   863 - Canadian French
+/   864 - Arabic
+/   865 - Nordic
+/   866 - Russian
+/   869 - Greek 2
+/   932 - Japanese (DBCS)
+/   936 - Simplified Chinese (DBCS)
+/   949 - Korean (DBCS)
+/   950 - Traditional Chinese (DBCS)
+*/
+
+#define _USE_LFN     0    /* 0 to 3 */
+#define _MAX_LFN     255  /* Maximum LFN length to handle (12 to 255) */
+/* The _USE_LFN switches the support of long file name (LFN).
+/
+/   0: Disable support of LFN. _MAX_LFN has no effect.
+/   1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
+/   2: Enable LFN with dynamic working buffer on the STACK.
+/   3: Enable LFN with dynamic working buffer on the HEAP.
+/
+/  To enable the LFN, Unicode handling functions (option/unicode.c) must be added
+/  to the project. The working buffer occupies (_MAX_LFN + 1) * 2 bytes and
+/  additional 608 bytes at exFAT enabled. _MAX_LFN can be in range from 12 to 255.
+/  It should be set 255 to support full featured LFN operations.
+/  When use stack for the working buffer, take care on stack overflow. When use heap
+/  memory for the working buffer, memory management functions, ff_memalloc() and
+/  ff_memfree(), must be added to the project. */
+
+#define _LFN_UNICODE    0 /* 0:ANSI/OEM or 1:Unicode */
+/* This option switches character encoding on the API. (0:ANSI/OEM or 1:UTF-16)
+/  To use Unicode string for the path name, enable LFN and set _LFN_UNICODE = 1.
+/  This option also affects behavior of string I/O functions. */
+
+#define _STRF_ENCODE    3
+/* When _LFN_UNICODE == 1, this option selects the character encoding ON THE FILE to
+/  be read/written via string I/O functions, f_gets(), f_putc(), f_puts and f_printf().
+/
+/  0: ANSI/OEM
+/  1: UTF-16LE
+/  2: UTF-16BE
+/  3: UTF-8
+/
+/  This option has no effect when _LFN_UNICODE == 0. */
+
+#define _FS_RPATH       0 /* 0 to 2 */
+/* This option configures support of relative path.
+/
+/   0: Disable relative path and remove related functions.
+/   1: Enable relative path. f_chdir() and f_chdrive() are available.
+/   2: f_getcwd() function is available in addition to 1.
+*/
+
+/*---------------------------------------------------------------------------/
+/ Drive/Volume Configurations
+/----------------------------------------------------------------------------*/
+
+#define _VOLUMES    1
+/* Number of volumes (logical drives) to be used. */
+
+/* USER CODE BEGIN Volumes */  
+#define _STR_VOLUME_ID          0	/* 0:Use only 0-9 for drive ID, 1:Use strings for drive ID */
+#define _VOLUME_STRS            "RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3"
+/* _STR_VOLUME_ID switches string support of volume ID.
+/  When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive
+/  number in the path name. _VOLUME_STRS defines the drive ID strings for each
+/  logical drives. Number of items must be equal to _VOLUMES. Valid characters for
+/  the drive ID strings are: A-Z and 0-9. */
+/* USER CODE END Volumes */  
+
+#define _MULTI_PARTITION     0 /* 0:Single partition, 1:Multiple partition */
+/* This option switches support of multi-partition on a physical drive.
+/  By default (0), each logical drive number is bound to the same physical drive
+/  number and only an FAT volume found on the physical drive will be mounted.
+/  When multi-partition is enabled (1), each logical drive number can be bound to
+/  arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
+/  funciton will be available. */
+#define _MIN_SS    512  /* 512, 1024, 2048 or 4096 */
+#define _MAX_SS    512  /* 512, 1024, 2048 or 4096 */
+/* These options configure the range of sector size to be supported. (512, 1024,
+/  2048 or 4096) Always set both 512 for most systems, all type of memory cards and
+/  harddisk. But a larger value may be required for on-board flash memory and some
+/  type of optical media. When _MAX_SS is larger than _MIN_SS, FatFs is configured
+/  to variable sector size and GET_SECTOR_SIZE command must be implemented to the
+/  disk_ioctl() function. */
+
+#define	_USE_TRIM      0
+/* This option switches support of ATA-TRIM. (0:Disable or 1:Enable)
+/  To enable Trim function, also CTRL_TRIM command should be implemented to the
+/  disk_ioctl() function. */
+
+#define _FS_NOFSINFO    0 /* 0,1,2 or 3 */
+/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
+/  option, and f_getfree() function at first time after volume mount will force
+/  a full FAT scan. Bit 1 controls the use of last allocated cluster number.
+/
+/  bit0=0: Use free cluster count in the FSINFO if available.
+/  bit0=1: Do not trust free cluster count in the FSINFO.
+/  bit1=0: Use last allocated cluster number in the FSINFO if available.
+/  bit1=1: Do not trust last allocated cluster number in the FSINFO.
+*/
+
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/----------------------------------------------------------------------------*/
+
+#define _FS_TINY    0      /* 0:Normal or 1:Tiny */
+/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
+/  At the tiny configuration, size of file object (FIL) is reduced _MAX_SS bytes.
+/  Instead of private sector buffer eliminated from the file object, common sector
+/  buffer in the file system object (FATFS) is used for the file data transfer. */
+
+#define _FS_EXFAT	0
+/* This option switches support of exFAT file system. (0:Disable or 1:Enable)
+/  When enable exFAT, also LFN needs to be enabled. (_USE_LFN >= 1)
+/  Note that enabling exFAT discards C89 compatibility. */
+
+#define _FS_NORTC	0
+#define _NORTC_MON	6
+#define _NORTC_MDAY	4
+#define _NORTC_YEAR	2015
+/* The option _FS_NORTC switches timestamp functiton. If the system does not have
+/  any RTC function or valid timestamp is not needed, set _FS_NORTC = 1 to disable
+/  the timestamp function. All objects modified by FatFs will have a fixed timestamp
+/  defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR in local time.
+/  To enable timestamp function (_FS_NORTC = 0), get_fattime() function need to be
+/  added to the project to get current time form real-time clock. _NORTC_MON,
+/  _NORTC_MDAY and _NORTC_YEAR have no effect. 
+/  These options have no effect at read-only configuration (_FS_READONLY = 1). */
+
+#define _FS_LOCK    2     /* 0:Disable or >=1:Enable */
+/* The option _FS_LOCK switches file lock function to control duplicated file open
+/  and illegal operation to open objects. This option must be 0 when _FS_READONLY
+/  is 1.
+/
+/  0:  Disable file lock function. To avoid volume corruption, application program
+/      should avoid illegal open, remove and rename to the open objects.
+/  >0: Enable file lock function. The value defines how many files/sub-directories
+/      can be opened simultaneously under file lock control. Note that the file
+/      lock control is independent of re-entrancy. */
+
+#define _FS_REENTRANT    0  /* 0:Disable or 1:Enable */
+#define _FS_TIMEOUT      1000 /* Timeout period in unit of time ticks */
+#define _SYNC_t          NULL
+/* The option _FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
+/  module itself. Note that regardless of this option, file access to different
+/  volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
+/  and f_fdisk() function, are always not re-entrant. Only file/directory access
+/  to the same volume is under control of this function.
+/
+/   0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect.
+/   1: Enable re-entrancy. Also user provided synchronization handlers,
+/      ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
+/      function, must be added to the project. Samples are available in
+/      option/syscall.c.
+/
+/  The _FS_TIMEOUT defines timeout period in unit of time tick.
+/  The _SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
+/  SemaphoreHandle_t and etc.. A header file for O/S definitions needs to be
+/  included somewhere in the scope of ff.h. */
+
+/* define the ff_malloc ff_free macros as standard malloc free */
+#if !defined(ff_malloc) && !defined(ff_free)
+#include 
+#define ff_malloc  malloc
+#define ff_free  free
+#endif
+
+#endif /* _FFCONF */
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/Target/sd_diskio.c b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/Target/sd_diskio.c
new file mode 100644
index 000000000..ce07b6365
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/Target/sd_diskio.c
@@ -0,0 +1,237 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FatFs/FatFs_uSD_Standalone/FatFs/Target/sd_diskio.c
+  * @author  MCD Application Team
+  * @brief   SD Disk I/O driver
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "ff_gen_drv.h"
+#include "sd_diskio.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#if defined(SDMMC_DATATIMEOUT)
+#define SD_TIMEOUT SDMMC_DATATIMEOUT
+#elif defined(SD_DATATIMEOUT)
+#define SD_TIMEOUT SD_DATATIMEOUT
+#else
+#define SD_TIMEOUT 30 * 1000
+#endif
+
+#define SD_DEFAULT_BLOCK_SIZE 512
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* Disk status */
+static volatile DSTATUS Stat = STA_NOINIT;
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+static DSTATUS SD_CheckStatus(BYTE lun);
+DSTATUS SD_initialize (BYTE);
+DSTATUS SD_status (BYTE);
+DRESULT SD_read (BYTE, BYTE*, DWORD, UINT);
+#if _USE_WRITE == 1
+  DRESULT SD_write (BYTE, const BYTE*, DWORD, UINT);
+#endif /* _USE_WRITE == 1 */
+#if _USE_IOCTL == 1
+  DRESULT SD_ioctl (BYTE, BYTE, void*);
+#endif  /* _USE_IOCTL == 1 */
+
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+const Diskio_drvTypeDef  SD_Driver =
+{
+  SD_initialize,
+  SD_status,
+  SD_read,
+#if  _USE_WRITE == 1
+  SD_write,
+#endif /* _USE_WRITE == 1 */
+
+#if  _USE_IOCTL == 1
+  SD_ioctl,
+#endif /* _USE_IOCTL == 1 */
+};
+
+/* Private functions ---------------------------------------------------------*/
+static DSTATUS SD_CheckStatus(BYTE lun)
+{
+  Stat = STA_NOINIT;
+  if(BSP_SD_GetCardState() == BSP_SD_OK)
+  {
+    Stat &= ~STA_NOINIT;
+  }
+
+  return Stat;
+}
+
+/**
+  * @brief  Initializes a Drive
+  * @param  lun : not used
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS SD_initialize(BYTE lun)
+{
+  /* USER CODE BEGIN SDinitialize */
+  Stat = STA_NOINIT;
+#if !defined(DISABLE_SD_INIT)
+  if(BSP_SD_Init() == MSD_OK)
+  {
+    Stat = SD_CheckStatus(lun);
+  }
+#else
+  Stat = SD_CheckStatus(lun);
+#endif
+  return Stat;
+  /* USER CODE END SDinitialize */
+}
+
+/**
+  * @brief  Gets Disk Status
+  * @param  lun : not used
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS SD_status(BYTE lun)
+{
+  return SD_CheckStatus(lun);
+}
+
+/**
+  * @brief  Reads Sector(s)
+  * @param  lun : not used
+  * @param  *buff: Data buffer to store read data
+  * @param  sector: Sector address (LBA)
+  * @param  count: Number of sectors to read (1..128)
+  * @retval DRESULT: Operation result
+  */
+DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count)
+{
+  DRESULT res = RES_ERROR;
+  if(BSP_SD_ReadBlocks((uint32_t*)buff,
+                       (uint32_t) (sector),
+                       count, SD_TIMEOUT) == BSP_SD_OK)
+  {
+    /* wait until the read operation is finished */
+    while(BSP_SD_GetCardState()!= BSP_SD_OK)
+    {
+    }
+    res = RES_OK;
+  }
+  return res;
+}
+
+/**
+  * @brief  Writes Sector(s)
+  * @param  lun : not used
+  * @param  *buff: Data to be written
+  * @param  sector: Sector address (LBA)
+  * @param  count: Number of sectors to write (1..128)
+  * @retval DRESULT: Operation result
+  */
+#if _USE_WRITE == 1
+DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count)
+{
+  DRESULT res = RES_ERROR;
+  if(BSP_SD_WriteBlocks((uint32_t*)buff,
+                        (uint32_t)(sector),
+                        count, SD_TIMEOUT) == MSD_OK)
+  {
+  /* wait until the Write operation is finished */
+    while(BSP_SD_GetCardState() != BSP_SD_OK)
+    {
+    }
+    res = RES_OK;
+  }
+
+  return res;
+
+}
+#endif /* _USE_WRITE == 1 */
+
+/**
+  * @brief  I/O control operation
+  * @param  lun : not used
+  * @param  cmd: Control code
+  * @param  *buff: Buffer to send/receive control data
+  * @retval DRESULT: Operation result
+  */
+#if _USE_IOCTL == 1
+DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff)
+{
+  DRESULT res = RES_ERROR;
+  BSP_SD_CardInfo CardInfo;
+
+  if (Stat & STA_NOINIT) return RES_NOTRDY;
+
+  switch (cmd)
+  {
+  /* Make sure that no pending write process */
+  case CTRL_SYNC :
+    res = RES_OK;
+    break;
+
+  /* Get number of sectors on the disk (DWORD) */
+  case GET_SECTOR_COUNT :
+    BSP_SD_GetCardInfo(&CardInfo);
+    *(DWORD*)buff = CardInfo.LogBlockNbr;
+    res = RES_OK;
+    break;
+
+  /* Get R/W sector size (WORD) */
+  case GET_SECTOR_SIZE :
+    BSP_SD_GetCardInfo(&CardInfo);
+    *(WORD*)buff = CardInfo.LogBlockSize;
+    res = RES_OK;
+    break;
+
+  /* Get erase block size in unit of sector (DWORD) */
+  case GET_BLOCK_SIZE :
+    BSP_SD_GetCardInfo(&CardInfo);
+    *(DWORD*)buff = CardInfo.LogBlockSize / SD_DEFAULT_BLOCK_SIZE;
+	res = RES_OK;
+    break;
+
+  default:
+    res = RES_PARERR;
+  }
+
+  return res;
+}
+#endif /* _USE_IOCTL == 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/Target/sd_diskio.h b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/Target/sd_diskio.h
new file mode 100644
index 000000000..04ea1a176
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/FATFS/Target/sd_diskio.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FatFs/FatFs_uSD_Standalone/FatFs/Target/sd_diskio.h
+  * @author  MCD Application Team
+  * @brief   Header for sd_diskio.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __SD_DISKIO_H
+#define __SD_DISKIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+extern const Diskio_drvTypeDef  SD_Driver;
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SD_DISKIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/MDK-ARM/FatFs_uSD_Standalone.uvoptx b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/MDK-ARM/FatFs_uSD_Standalone.uvoptx
new file mode 100644
index 000000000..ce64a7974
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/MDK-ARM/FatFs_uSD_Standalone.uvoptx
@@ -0,0 +1,669 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    FatFs_uSD_Standalone
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User/Core
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Core/Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Core/Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      2
+      4
+      1
+      0
+      0
+      0
+      ../Core/Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Application/User/FATFS/Target
+    0
+    0
+    0
+    0
+    
+      3
+      5
+      1
+      0
+      0
+      0
+      ../FATFS/Target/sd_diskio.c
+      sd_diskio.c
+      0
+      0
+    
+  
+
+  
+    Application/User/FATFS/App
+    0
+    0
+    0
+    0
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../FATFS/App/app_fatfs.c
+      app_fatfs.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      5
+      7
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/Adafruit_Shield
+    0
+    0
+    0
+    0
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_sd.c
+      stm32_adafruit_sd.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_lcd.c
+      stm32_adafruit_lcd.c
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/Components
+    0
+    0
+    0
+    0
+    
+      7
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/Components/st7735/st7735.c
+      st7735.c
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      8
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      9
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+      stm32wbxx_hal_spi.c
+      0
+      0
+    
+    
+      9
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+      stm32wbxx_hal_spi_ex.c
+      0
+      0
+    
+    
+      9
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      9
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      9
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      9
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      9
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      9
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      9
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      9
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      9
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      9
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      9
+      24
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      9
+      25
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      9
+      26
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      9
+      27
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      9
+      28
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      10
+      29
+      1
+      0
+      0
+      0
+      ../Core/Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    Middlewares/FatFs
+    0
+    0
+    0
+    0
+    
+      11
+      30
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FatFs/src/diskio.c
+      diskio.c
+      0
+      0
+    
+    
+      11
+      31
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FatFs/src/ff.c
+      ff.c
+      0
+      0
+    
+    
+      11
+      32
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FatFs/src/ff_gen_drv.c
+      ff_gen_drv.c
+      0
+      0
+    
+    
+      11
+      33
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FatFs/src/option/syscall.c
+      syscall.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/MDK-ARM/FatFs_uSD_Standalone.uvprojx b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/MDK-ARM/FatFs_uSD_Standalone.uvprojx
new file mode 100644
index 000000000..c0dadb4e7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/MDK-ARM/FatFs_uSD_Standalone.uvprojx
@@ -0,0 +1,622 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      FatFs_uSD_Standalone
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          FatFs_uSD_Standalone\
+          FatFs_uSD_Standalone
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_STM32WBXX_NUCLEO,USE_HAL_DRIVER,STM32WB35xx
+              
+              ../FATFS/Target;../FATFS/App;../Core/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Middlewares/Third_Party/FatFs/src;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE;../../../../../../Drivers/BSP/Adafruit_Shield;../../../../../../Drivers/BSP/Components;../../../../../../Drivers/BSP/Components/Common
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User/Core
+          
+            
+              main.c
+              1
+              ../Core/Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Core/Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Core/Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Application/User/FATFS/Target
+          
+            
+              sd_diskio.c
+              1
+              ../FATFS/Target/sd_diskio.c
+            
+          
+        
+        
+          Application/User/FATFS/App
+          
+            
+              app_fatfs.c
+              1
+              ../FATFS/App/app_fatfs.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/Adafruit_Shield
+          
+            
+              stm32_adafruit_sd.c
+              1
+              ../../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_sd.c
+            
+            
+              stm32_adafruit_lcd.c
+              1
+              ../../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_lcd.c
+            
+          
+        
+        
+          Drivers/BSP/Components
+          
+            
+              st7735.c
+              1
+              ../../../../../../Drivers/BSP/Components/st7735/st7735.c
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_spi.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+            
+            
+              stm32wbxx_hal_spi_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Core/Src/system_stm32wbxx.c
+            
+          
+        
+        
+          Middlewares/FatFs
+          
+            
+              diskio.c
+              1
+              ../../../../../../Middlewares/Third_Party/FatFs/src/diskio.c
+            
+            
+              ff.c
+              1
+              ../../../../../../Middlewares/Third_Party/FatFs/src/ff.c
+            
+            
+              ff_gen_drv.c
+              1
+              ../../../../../../Middlewares/Third_Party/FatFs/src/ff_gen_drv.c
+            
+            
+              syscall.c
+              1
+              ../../../../../../Middlewares/Third_Party/FatFs/src/option/syscall.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..f7a2eea7b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x400
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..396e2854b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/.cproject
@@ -0,0 +1,183 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/.project
new file mode 100644
index 000000000..00dcdb48d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/.project
@@ -0,0 +1,201 @@
+
+
+	FatFs_uSD_Standalone
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			FatFs_uSD_Standalone.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/FatFs_uSD_Standalone.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Core/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Core/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Core/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Core/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_spi.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_spi_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Middlewares/FatFs/diskio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FatFs/src/diskio.c
+		
+		
+			Middlewares/FatFs/ff.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FatFs/src/ff.c
+		
+		
+			Middlewares/FatFs/ff_gen_drv.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FatFs/src/ff_gen_drv.c
+		
+		
+			Middlewares/FatFs/syscall.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FatFs/src/option/syscall.c
+		
+		
+			Drivers/BSP/Adafruit_Shield/stm32_adafruit_lcd.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/Adafruit_Shield/stm32_adafruit_lcd.c
+		
+		
+			Drivers/BSP/Adafruit_Shield/stm32_adafruit_sd.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/Adafruit_Shield/stm32_adafruit_sd.c
+		
+		
+			Drivers/BSP/Components/st7735.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/Components/st7735/st7735.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+		
+			Application/User/FATFS/App/app_fatfs.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/FATFS/App/app_fatfs.c
+		
+		
+			Application/User/FATFS/Target/sd_diskio.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/FATFS/Target/sd_diskio.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..eea98ff9c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb35xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB35xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..4ec95844d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,159 @@
+/**
+ ******************************************************************************
+ * @file      syscalls.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..4665417ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,58 @@
+/**
+ ******************************************************************************
+ * @file      sysmem.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System Memory calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..88456398d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x400 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/readme.txt b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/readme.txt
new file mode 100644
index 000000000..7d03898fc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FatFs/FatFs_uSD_Standalone/readme.txt
@@ -0,0 +1,111 @@
+/**
+  @page FatFs_uSD_Standalone  FatFs with uSD card drive application
+
+  @verbatim
+  ******************************************************************************
+  * @file    FatFS/FatFS_uSD_Standalone/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the FatFs with uSD card drive application
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Application Description
+
+How to use STM32Cube firmware with FatFs middleware component as a generic FAT
+file system module. This example develops an application that exploits FatFs
+features to configure a microSD drive.
+
+At the beginning of the main program the HAL_Init() function is called to reset
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system clock
+(SYSCLK) to run at 64 MHz.
+
+The application is based on writing and reading back a text file from a drive,
+and it's performed using FatFs APIs to access the FAT volume as described
+in the following steps:
+
+ - Link the uSD disk I/O driver;
+ - Register the file system object (mount) to the FatFs module for the uSD drive;
+ - Create a FAT file system (format) on the uSD drive;
+ - Create and Open new text file object with write access;
+ - Write data to the text file;
+ - Close the open text file;
+ - Open text file object with read access;
+ - Read back data from the text file;
+ - Close the open text file;
+ - Check on read data from text file;
+ - Unlink the uSD disk I/O driver.
+
+It is worth nothing that the application manages any error occurred during the
+access to FAT volume, when using FatFs APIs. Otherwise, user can check if the
+written text file is available on the uSD card.
+
+It is possible to fine tune needed FatFs features by modifying defines values
+in FatFs configuration file "ffconf.h" available under the project includes
+directory, in a way to fit the application requirements.
+
+@note: for some uSD's, replacing it  while the application is running makes the application
+       fail. It is recommended to reset the board using the "Reset button" after replacing
+       the uSD.
+
+NUCLEO-WB35CE's LED can be used to monitor the application status:
+  - LED2 is ON when the application runs successfully.
+  - LED3 is ON when any error occurs.
+
+@par Keywords
+
+Middleware, SD Card, FatFs, File system, FAT Volume, Format, Mount, Read, Write,
+
+@note SD module is part of the Adafruit shield.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Directory contents
+
+  - FatFs/FatFs_uSD_Standalone/Core/Inc/stm32wbxx_hal_conf.h               HAL configuration file
+  - FatFs/FatFs_uSD_Standalone/Core/Inc/stm32wbxx_it.h                     Interrupt handlers header file
+  - FatFs/FatFs_uSD_Standalone/Core/Inc/main.h                             Header for main.c module
+  - FatFs/FatFs_uSD_Standalone/Core/Src/stm32wbxx_it.c                     Interrupt handlers
+  - FatFs/FatFs_uSD_Standalone/Core/Src/main.c                             Main program
+  - FatFs/FatFs_uSD_Standalone/Core/Src/system_stm32wbxx.c                 STM32WBxx system source file
+  - FatFs/FatFs_uSD_Standalone/FATFS/Target/ffconf.h                       FAT file system module configuration file
+  - FatFs/FatFs_uSD_Standalone/FATFS/Target/sd_diskio.h                    uSD diskio header file
+  - FatFs/FatFs_uSD_Standalone/FATFS/Target/sd_diskio.c                    FatFs uSD diskio driver
+  - FatFs/FatFs_uSD_Standalone/FATFS/App/app_fatfs.h                       Header file for App_fatfs.c file
+  - FatFs/FatFs_uSD_Standalone/FATFS/App/app_fatfs.c                       FatFs application code
+
+@par Hardware and Software environment
+
+  - This application runs on STM32WB35CEUx devices
+
+  - This application has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+@par How to use it ?
+
+In order to make the program work, you must do the following:
+ - Insert a microSD card in the board appropriate slot from Adafruit shield
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the application
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/.extSettings b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/.extSettings
new file mode 100644
index 000000000..e75e48ab0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/.extSettings
@@ -0,0 +1,9 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=TIM
+[Groups]
+Application/User=../Src/main.c;../Src/stm32wbxx_it.c;../Src/stm32wbxx_hal_timebase_tim.c;../Src/app_freertos.c;../Src/stm32wbxx_hal_msp.c;
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/FreeRTOS_Mutexes.ewd b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/FreeRTOS_Mutexes.ewd
new file mode 100644
index 000000000..2d115a29f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/FreeRTOS_Mutexes.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		FreeRTOS_Mutexes
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/FreeRTOS_Mutexes.ewp b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/FreeRTOS_Mutexes.ewp
new file mode 100644
index 000000000..773a04c13
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/FreeRTOS_Mutexes.ewp
@@ -0,0 +1,1167 @@
+
+
+  3
+  
+    FreeRTOS_Mutexes
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_timebase_tim.c
+      
+      
+        $PROJ_DIR$/../Src/app_freertos.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+  
+    Middlewares
+    
+      FreeRTOS
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/croutine.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/list.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/queue.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/tasks.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/timers.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/Project.eww
new file mode 100644
index 000000000..a3327a905
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\FreeRTOS_Mutexes.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/stm32wb35xx_sram_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/stm32wb35xx_sram_cm4.icf
new file mode 100644
index 000000000..6426355fb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/EWARM/stm32wb35xx_sram_cm4.icf
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20003FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20004000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20008000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x2000FFFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/FreeRTOS_Mutexes.ioc b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/FreeRTOS_Mutexes.ioc
new file mode 100644
index 000000000..c4b02dcbe
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/FreeRTOS_Mutexes.ioc
@@ -0,0 +1,162 @@
+#MicroXplorer Configuration settings - do not modify
+FREERTOS.HEAP_NUMBER=4
+FREERTOS.INCLUDE_eTaskGetState=1
+FREERTOS.INCLUDE_pcTaskGetTaskName=0
+FREERTOS.INCLUDE_uxTaskGetStackHighWaterMark=0
+FREERTOS.INCLUDE_uxTaskPriorityGet=1
+FREERTOS.INCLUDE_vTaskCleanUpResources=0
+FREERTOS.INCLUDE_vTaskDelay=1
+FREERTOS.INCLUDE_vTaskDelayUntil=0
+FREERTOS.INCLUDE_vTaskDelete=1
+FREERTOS.INCLUDE_vTaskPrioritySet=1
+FREERTOS.INCLUDE_vTaskSuspend=1
+FREERTOS.INCLUDE_xEventGroupSetBitFromISR=0
+FREERTOS.INCLUDE_xQueueGetMutexHolder=1
+FREERTOS.INCLUDE_xSemaphoreGetMutexHolder=0
+FREERTOS.INCLUDE_xTaskAbortDelay=0
+FREERTOS.INCLUDE_xTaskGetCurrentTaskHandle=0
+FREERTOS.INCLUDE_xTaskGetHandle=0
+FREERTOS.INCLUDE_xTaskResumeFromISR=1
+FREERTOS.IPParameters=Tasks01,configUSE_RECURSIVE_MUTEXES,configUSE_COUNTING_SEMAPHORES,configTOTAL_HEAP_SIZE,configUSE_TRACE_FACILITY,configLIBRARY_LOWEST_INTERRUPT_PRIORITY,configIDLE_SHOULD_YIELD,INCLUDE_vTaskCleanUpResources,INCLUDE_vTaskDelayUntil,INCLUDE_eTaskGetState,INCLUDE_xQueueGetMutexHolder,INCLUDE_xTaskResumeFromISR,Mutexes01,configUSE_PREEMPTION,MEMORY_ALLOCATION,configTICK_RATE_HZ,configMAX_PRIORITIES,configMINIMAL_STACK_SIZE,configMAX_TASK_NAME_LEN,configUSE_MUTEXES,configQUEUE_REGISTRY_SIZE,configUSE_APPLICATION_TASK_TAG,HEAP_NUMBER,configUSE_IDLE_HOOK,configUSE_TICK_HOOK,configUSE_MALLOC_FAILED_HOOK,configUSE_DAEMON_TASK_STARTUP_HOOK,configCHECK_FOR_STACK_OVERFLOW,configGENERATE_RUN_TIME_STATS,configUSE_STATS_FORMATTING_FUNCTIONS,configUSE_CO_ROUTINES,configMAX_CO_ROUTINE_PRIORITIES,configUSE_TIMERS,configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY,INCLUDE_vTaskPrioritySet,INCLUDE_uxTaskPriorityGet,INCLUDE_vTaskDelete,INCLUDE_vTaskSuspend,INCLUDE_vTaskDelay,INCLUDE_xSemaphoreGetMutexHolder,INCLUDE_pcTaskGetTaskName,INCLUDE_uxTaskGetStackHighWaterMark,INCLUDE_xTaskGetCurrentTaskHandle,INCLUDE_xEventGroupSetBitFromISR,configENABLE_BACKWARD_COMPATIBILITY,configUSE_TICKLESS_IDLE,configUSE_TASK_NOTIFICATIONS,INCLUDE_xTaskAbortDelay,INCLUDE_xTaskGetHandle,configRECORD_STACK_HIGH_ADDRESS
+FREERTOS.MEMORY_ALLOCATION=0
+FREERTOS.Mutexes01=osMutex
+FREERTOS.Tasks01=MutHigh,-1,128,MutexHighPriorityThreadr,Default,NULL,Dynamic,NULL,NULL;MutMedium,-2,128,MutexMediumPriorityThread,Default,NULL,Dynamic,NULL,NULL;MutLow,-3,128,MutexLowPriorityThread,Default,NULL,Dynamic,NULL,NULL
+FREERTOS.configCHECK_FOR_STACK_OVERFLOW=0
+FREERTOS.configENABLE_BACKWARD_COMPATIBILITY=1
+FREERTOS.configGENERATE_RUN_TIME_STATS=0
+FREERTOS.configIDLE_SHOULD_YIELD=1
+FREERTOS.configLIBRARY_LOWEST_INTERRUPT_PRIORITY=15
+FREERTOS.configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY=5
+FREERTOS.configMAX_CO_ROUTINE_PRIORITIES=2
+FREERTOS.configMAX_PRIORITIES=7
+FREERTOS.configMAX_TASK_NAME_LEN=16
+FREERTOS.configMINIMAL_STACK_SIZE=128
+FREERTOS.configQUEUE_REGISTRY_SIZE=8
+FREERTOS.configRECORD_STACK_HIGH_ADDRESS=0
+FREERTOS.configTICK_RATE_HZ=1000
+FREERTOS.configTOTAL_HEAP_SIZE=3072
+FREERTOS.configUSE_APPLICATION_TASK_TAG=0
+FREERTOS.configUSE_COUNTING_SEMAPHORES=1
+FREERTOS.configUSE_CO_ROUTINES=0
+FREERTOS.configUSE_DAEMON_TASK_STARTUP_HOOK=0
+FREERTOS.configUSE_IDLE_HOOK=0
+FREERTOS.configUSE_MALLOC_FAILED_HOOK=0
+FREERTOS.configUSE_MUTEXES=1
+FREERTOS.configUSE_PREEMPTION=1
+FREERTOS.configUSE_RECURSIVE_MUTEXES=1
+FREERTOS.configUSE_STATS_FORMATTING_FUNCTIONS=0
+FREERTOS.configUSE_TASK_NOTIFICATIONS=1
+FREERTOS.configUSE_TICKLESS_IDLE=0
+FREERTOS.configUSE_TICK_HOOK=0
+FREERTOS.configUSE_TIMERS=0
+FREERTOS.configUSE_TRACE_FACILITY=1
+File.Version=6
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=FREERTOS
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_FREERTOS_VS_CMSIS_V1
+Mcu.Pin1=VP_SYS_VS_tim17
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false
+NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:true\:false
+NVIC.TIM1_TRG_COM_TIM17_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
+NVIC.TimeBase=TIM1_TRG_COM_TIM17_IRQn
+NVIC.TimeBaseIP=TIM17
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=FreeRTOS_Mutexes.ioc
+ProjectManager.ProjectName=FreeRTOS_Mutexes
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_FREERTOS_VS_CMSIS_V1.Mode=CMSIS_V1
+VP_FREERTOS_VS_CMSIS_V1.Signal=FREERTOS_VS_CMSIS_V1
+VP_SYS_VS_tim17.Mode=TIM17
+VP_SYS_VS_tim17.Signal=SYS_VS_tim17
+board=STM32G081B-EVAL
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Inc/FreeRTOSConfig.h b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Inc/FreeRTOSConfig.h
new file mode 100644
index 000000000..de661759c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Inc/FreeRTOSConfig.h
@@ -0,0 +1,143 @@
+/* USER CODE BEGIN Header */
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+/* USER CODE END Header */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+/* USER CODE BEGIN Includes */   	      
+/* Section where include file can be added */
+/* USER CODE END Includes */ 
+
+/* Ensure definitions are only used by the compiler, and not by the assembler. */
+#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
+  #include 
+  extern uint32_t SystemCoreClock;
+#endif
+#define configENABLE_FPU                         0
+#define configENABLE_MPU                         0
+
+#define configUSE_PREEMPTION                     1
+#define configSUPPORT_STATIC_ALLOCATION          0
+#define configSUPPORT_DYNAMIC_ALLOCATION         1
+#define configUSE_IDLE_HOOK                      0
+#define configUSE_TICK_HOOK                      0
+#define configCPU_CLOCK_HZ                       ( SystemCoreClock )
+#define configTICK_RATE_HZ                       ((TickType_t)1000)
+#define configMAX_PRIORITIES                     ( 7 )
+#define configMINIMAL_STACK_SIZE                 ((uint16_t)128)
+#define configTOTAL_HEAP_SIZE                    ((size_t)3072)
+#define configMAX_TASK_NAME_LEN                  ( 16 )
+#define configUSE_TRACE_FACILITY                 1
+#define configUSE_16_BIT_TICKS                   0
+#define configUSE_MUTEXES                        1
+#define configQUEUE_REGISTRY_SIZE                8
+#define configUSE_RECURSIVE_MUTEXES              1
+#define configUSE_COUNTING_SEMAPHORES            1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION  1
+/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */
+/* Defaults to size_t for backward compatibility, but can be changed
+   if lengths will always be less than the number of bytes in a size_t. */
+#define configMESSAGE_BUFFER_LENGTH_TYPE         size_t
+/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */ 
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                    0
+#define configMAX_CO_ROUTINE_PRIORITIES          ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet             1
+#define INCLUDE_uxTaskPriorityGet            1
+#define INCLUDE_vTaskDelete                  1
+#define INCLUDE_vTaskCleanUpResources        0
+#define INCLUDE_vTaskSuspend                 1
+#define INCLUDE_vTaskDelayUntil              0
+#define INCLUDE_vTaskDelay                   1
+#define INCLUDE_xTaskGetSchedulerState       1
+#define INCLUDE_xQueueGetMutexHolder         1
+#define INCLUDE_eTaskGetState                1
+
+/* Cortex-M specific definitions. */
+#ifdef __NVIC_PRIO_BITS
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+ #define configPRIO_BITS         __NVIC_PRIO_BITS
+#else
+ #define configPRIO_BITS         4
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY   15
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* Normal assert() semantics without relying on the provision of an assert.h
+header file. */
+/* USER CODE BEGIN 1 */
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
+/* USER CODE END 1 */
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler    SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+
+/* IMPORTANT: This define is commented when used with STM32Cube firmware, when the timebase source is SysTick,
+              to prevent overwriting SysTick_Handler defined within STM32Cube HAL */
+ 
+#define xPortSysTickHandler SysTick_Handler
+
+/* USER CODE BEGIN Defines */   	      
+/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */
+/* USER CODE END Defines */ 
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Inc/main.h b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Inc/main.h
new file mode 100644
index 000000000..c64dd4832
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Inc/main.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FreeRTOS\FreeRTOS_Mutexes\Inc\main.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the main.c
+  *          file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..3e4ba1426
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..2543ed823
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Inc/stm32wbxx_it.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Mutexes/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void DebugMon_Handler(void);
+void TIM1_TRG_COM_TIM17_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/MDK-ARM/FreeRTOS_Mutexes.uvoptx b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/MDK-ARM/FreeRTOS_Mutexes.uvoptx
new file mode 100644
index 000000000..283f0d84b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/MDK-ARM/FreeRTOS_Mutexes.uvoptx
@@ -0,0 +1,649 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    FreeRTOS_Mutexes
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      2
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_timebase_tim.c
+      stm32wbxx_hal_timebase_tim.c
+      0
+      0
+    
+    
+      2
+      5
+      1
+      0
+      0
+      0
+      ../Src/app_freertos.c
+      app_freertos.c
+      0
+      0
+    
+    
+      2
+      6
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      7
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      4
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      5
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      5
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      5
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      5
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      5
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      5
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      5
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      5
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      5
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      5
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      5
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      5
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      24
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    Middlewares/FreeRTOS
+    0
+    0
+    0
+    0
+    
+      7
+      25
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/croutine.c
+      croutine.c
+      0
+      0
+    
+    
+      7
+      26
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
+      event_groups.c
+      0
+      0
+    
+    
+      7
+      27
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/list.c
+      list.c
+      0
+      0
+    
+    
+      7
+      28
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/queue.c
+      queue.c
+      0
+      0
+    
+    
+      7
+      29
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
+      stream_buffer.c
+      0
+      0
+    
+    
+      7
+      30
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/tasks.c
+      tasks.c
+      0
+      0
+    
+    
+      7
+      31
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/timers.c
+      timers.c
+      0
+      0
+    
+    
+      7
+      32
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c
+      cmsis_os.c
+      0
+      0
+    
+    
+      7
+      33
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
+      heap_4.c
+      0
+      0
+    
+    
+      7
+      34
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
+      port.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/MDK-ARM/FreeRTOS_Mutexes.uvprojx b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/MDK-ARM/FreeRTOS_Mutexes.uvprojx
new file mode 100644
index 000000000..fbec960de
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/MDK-ARM/FreeRTOS_Mutexes.uvprojx
@@ -0,0 +1,606 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      FreeRTOS_Mutexes
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          FreeRTOS_Mutexes\
+          FreeRTOS_Mutexes
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Middlewares/Third_Party/FreeRTOS/Source/include;../../../../../../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS;../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              ..\Inc
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_timebase_tim.c
+              1
+              ../Src/stm32wbxx_hal_timebase_tim.c
+            
+            
+              app_freertos.c
+              1
+              ../Src/app_freertos.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          Middlewares/FreeRTOS
+          
+            
+              croutine.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/croutine.c
+            
+            
+              event_groups.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
+            
+            
+              list.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/list.c
+            
+            
+              queue.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/queue.c
+            
+            
+              stream_buffer.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
+            
+            
+              tasks.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/tasks.c
+            
+            
+              timers.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/timers.c
+            
+            
+              cmsis_os.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c
+            
+            
+              heap_4.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
+            
+            
+              port.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..4ec02790c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/.cproject
@@ -0,0 +1,175 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/.project
new file mode 100644
index 000000000..3f5498322
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/.project
@@ -0,0 +1,205 @@
+
+
+	FreeRTOS_Mutexes
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			FreeRTOS_Mutexes.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/FreeRTOS_Mutexes.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/app_freertos.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/app_freertos.c
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_hal_timebase_tim.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_timebase_tim.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Middlewares/FreeRTOS/cmsis_os.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c
+		
+		
+			Middlewares/FreeRTOS/croutine.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/croutine.c
+		
+		
+			Middlewares/FreeRTOS/event_groups.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
+		
+		
+			Middlewares/FreeRTOS/heap_4.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
+		
+		
+			Middlewares/FreeRTOS/list.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/list.c
+		
+		
+			Middlewares/FreeRTOS/port.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
+		
+		
+			Middlewares/FreeRTOS/queue.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/queue.c
+		
+		
+			Middlewares/FreeRTOS/stream_buffer.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
+		
+		
+			Middlewares/FreeRTOS/tasks.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
+		
+		
+			Middlewares/FreeRTOS/timers.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/timers.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/app_freertos.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/app_freertos.c
new file mode 100644
index 000000000..85521ac69
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/app_freertos.c
@@ -0,0 +1,62 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Mutexes/Src/freertos.c
+  * @author  MCD Application Team
+  * @brief   Code for freertos applications
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "FreeRTOS.h"
+#include "task.h"
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */     
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN Variables */
+
+/* USER CODE END Variables */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN FunctionPrototypes */
+
+/* USER CODE END FunctionPrototypes */
+
+/* Private application code --------------------------------------------------*/
+/* USER CODE BEGIN Application */
+
+/* USER CODE END Application */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/main.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/main.c
new file mode 100644
index 000000000..fbc4fb71a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/main.c
@@ -0,0 +1,481 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Mutexes/Src/main.c
+  * @author  MCD Application Team
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+#define mutexSHORT_DELAY     ((uint32_t) 20)
+#define mutexNO_DELAY        ((uint32_t) 0)
+#define mutexTWO_TICK_DELAY  ((uint32_t) 2)
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+osThreadId MutHighHandle;
+osThreadId MutMediumHandle;
+osThreadId MutLowHandle;
+osMutexId osMutexHandle;
+/* USER CODE BEGIN PV */
+
+/* Variables used to detect and latch errors */
+__IO uint32_t HighPriorityThreadCycles = 0, MediumPriorityThreadCycles = 0, LowPriorityThreadCycles = 0;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+void MutexHighPriorityThreadr(void const * argument);
+void MutexMediumPriorityThread(void const * argument);
+void MutexLowPriorityThread(void const * argument);
+
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* Initialize LEDs */
+  BSP_LED_Init(LED1);
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Create the mutex(es) */
+  /* definition and creation of osMutex */
+  osMutexDef(osMutex);
+  osMutexHandle = osMutexCreate(osMutex(osMutex));
+
+  /* USER CODE BEGIN RTOS_MUTEX */
+
+  /* USER CODE END RTOS_MUTEX */
+
+  /* USER CODE BEGIN RTOS_SEMAPHORES */
+
+  /* USER CODE END RTOS_SEMAPHORES */
+
+  /* USER CODE BEGIN RTOS_TIMERS */
+
+  /* USER CODE END RTOS_TIMERS */
+
+  /* USER CODE BEGIN RTOS_QUEUES */
+
+  /* USER CODE END RTOS_QUEUES */
+
+  /* Create the thread(s) */
+  /* definition and creation of MutHigh */
+  osThreadDef(MutHigh, MutexHighPriorityThreadr, osPriorityBelowNormal, 0, 128);
+  MutHighHandle = osThreadCreate(osThread(MutHigh), NULL);
+
+  /* definition and creation of MutMedium */
+  osThreadDef(MutMedium, MutexMediumPriorityThread, osPriorityLow, 0, 128);
+  MutMediumHandle = osThreadCreate(osThread(MutMedium), NULL);
+
+  /* definition and creation of MutLow */
+  osThreadDef(MutLow, MutexLowPriorityThread, osPriorityIdle, 0, 128);
+  MutLowHandle = osThreadCreate(osThread(MutLow), NULL);
+
+  /* USER CODE BEGIN RTOS_THREADS */
+
+  /* USER CODE END RTOS_THREADS */
+
+  /* Start scheduler */
+  osKernelStart();
+ 
+  /* We should never get here as control is now taken by the scheduler */
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/* USER CODE BEGIN Header_MutexHighPriorityThreadr */
+/**
+  * @brief  Function implementing the MutHigh thread.
+  * @param  argument: Not used
+  * @retval None
+  */
+/* USER CODE END Header_MutexHighPriorityThreadr */
+void MutexHighPriorityThreadr(void const * argument)
+{
+  /* USER CODE BEGIN 5 */
+  /* Just to remove compiler warning */
+  (void) argument;
+  /* Infinite loop */
+  for (;;)
+  {
+    /* The first time through the mutex will be immediately available, on
+    subsequent times through the mutex will be held by the low priority thread
+    at this point and this Take will cause the low priority thread to inherit
+    the priority of this tadhr.  In this case the block time must be
+    long enough to ensure the low priority thread will execute again before the
+    block time expires.  If the block time does expire then the error
+    flag will be set here */
+    if (osMutexWait(osMutexHandle, mutexTWO_TICK_DELAY) != osOK)
+    {
+      /* Toggle LED3 to indicate error */
+      BSP_LED_Toggle(LED3);
+    }
+
+    /* Ensure the other thread attempting to access the mutex
+    are able to execute to ensure they either block (where a block
+    time is specified) or return an error (where no block time is
+    specified) as the mutex is held by this task */
+    osDelay(mutexSHORT_DELAY);
+
+    /* We should now be able to release the mutex .
+    When the mutex is available again the medium priority thread
+    should be unblocked but not run because it has a lower priority
+    than this thread.  The low priority thread should also not run
+    at this point as it too has a lower priority than this thread */
+    if (osMutexRelease(osMutexHandle) != osOK)
+    {
+      /* Toggle LED3 to indicate error */
+      BSP_LED_Toggle(LED3);
+    }
+
+    /* Keep count of the number of cycles this thread has performed */
+    HighPriorityThreadCycles++;
+    BSP_LED_Toggle(LED1);
+
+    /* Suspend ourselves to the medium priority thread can execute */
+    osThreadSuspend(NULL);
+  }
+  /* USER CODE END 5 */ 
+}
+
+/* USER CODE BEGIN Header_MutexMediumPriorityThread */
+/**
+* @brief Function implementing the MutMedium thread.
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_MutexMediumPriorityThread */
+void MutexMediumPriorityThread(void const * argument)
+{
+  /* USER CODE BEGIN MutexMediumPriorityThread */
+  /* Just to remove compiler warning */
+  (void) argument;
+
+  /* Infinite loop */
+  for (;;)
+  {
+    /* This thread will run while the high-priority thread is blocked, and the
+    high-priority thread will block only once it has the mutex - therefore
+    this call should block until the high-priority thread has given up the
+    mutex, and not actually execute past this call until the high-priority
+    thread is suspended */
+    if (osMutexWait(osMutexHandle, osWaitForever) == osOK)
+    {
+      if (osThreadGetState(MutHighHandle) != osThreadSuspended)
+      {
+        /* Did not expect to execute until the high priority thread was
+        suspended.
+        Toggle LED3 to indicate error */
+        BSP_LED_Toggle(LED3);
+      }
+      else
+      {
+        /* Give the mutex back before suspending ourselves to allow
+        the low priority thread to obtain the mutex */
+        if (osMutexRelease(osMutexHandle) != osOK)
+        {
+          /* Toggle LED3 to indicate error */
+          BSP_LED_Toggle(LED3);
+        }
+        osThreadSuspend(NULL);
+      }
+    }
+    else
+    {
+      /* We should not leave the osMutexWait() function
+      until the mutex was obtained.
+      Toggle LED3 to indicate error */
+      BSP_LED_Toggle(LED3);
+    }
+
+    /* The High and Medium priority threads should be in lock step */
+    if (HighPriorityThreadCycles != (MediumPriorityThreadCycles + 1))
+    {
+      /* Toggle LED3 to indicate error */
+      BSP_LED_Toggle(LED3);
+    }
+
+    /* Keep count of the number of cycles this task has performed so a
+    stall can be detected */
+    MediumPriorityThreadCycles++;
+    BSP_LED_Toggle(LED2);
+  }
+  /* USER CODE END MutexMediumPriorityThread */
+}
+
+/* USER CODE BEGIN Header_MutexLowPriorityThread */
+/**
+* @brief Function implementing the MutLow thread.
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_MutexLowPriorityThread */
+void MutexLowPriorityThread(void const * argument)
+{
+  /* USER CODE BEGIN MutexLowPriorityThread */
+  /* Just to remove compiler warning */
+  (void) argument;
+
+  /* Infinite loop */
+  for (;;)
+  {
+    /* Keep attempting to obtain the mutex.  We should only obtain it when
+    the medium-priority thread has suspended itself, which in turn should only
+    happen when the high-priority thread is also suspended */
+    if (osMutexWait(osMutexHandle, mutexNO_DELAY) == osOK)
+    {
+      /* Is the haigh and medium-priority threads suspended? */
+      if ((osThreadGetState(MutHighHandle) != osThreadSuspended) || (osThreadGetState(MutMediumHandle) != osThreadSuspended))
+      {
+        /* Toggle LED3 to indicate error */
+        BSP_LED_Toggle(LED3);
+      }
+      else
+      {
+        /* Keep count of the number of cycles this task has performed
+        so a stall can be detected */
+        LowPriorityThreadCycles++;
+
+        /* We can resume the other tasks here even though they have a
+        higher priority than the this thread. When they execute they
+        will attempt to obtain the mutex but fail because the low-priority
+        thread is still the mutex holder.  this thread will then inherit
+        the higher priority.  The medium-priority thread will block indefinitely
+        when it attempts to obtain the mutex, the high-priority thread will only
+        block for a fixed period and an error will be latched if the
+        high-priority thread has not returned the mutex by the time this
+        fixed period has expired */
+        osThreadResume(MutMediumHandle);
+        osThreadResume(MutHighHandle);
+
+        /* The other two tasks should now have executed and no longer
+        be suspended */
+        if ((osThreadGetState(MutHighHandle) == osThreadSuspended) || (osThreadGetState(MutMediumHandle) == osThreadSuspended))
+        {
+          /* Toggle LED3 to indicate error */
+          BSP_LED_Toggle(LED3);
+        }
+
+        /* Release the mutex, disinheriting the higher priority again */
+        if (osMutexRelease(osMutexHandle) != osOK)
+        {
+          /* Toggle LED3 to indicate error */
+          BSP_LED_Toggle(LED3);
+        }
+      }
+    }
+
+#if configUSE_PREEMPTION == 0
+    {
+      taskYIELD();
+    }
+#endif
+  }
+  /* USER CODE END MutexLowPriorityThread */
+}
+
+/**
+  * @brief  Period elapsed callback in non blocking mode
+  * @note   This function is called  when TIM17 interrupt took place, inside
+  * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+  * a global variable "uwTick" used as application time base.
+  * @param  htim : TIM handle
+  * @retval None
+  */
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* USER CODE BEGIN Callback 0 */
+
+  /* USER CODE END Callback 0 */
+  if (htim->Instance == TIM17) {
+    HAL_IncTick();
+  }
+  /* USER CODE BEGIN Callback 1 */
+
+  /* USER CODE END Callback 1 */
+}
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {}
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..8c51e2b32
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,84 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Mutexes/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   This file provides code for the MSP Initialization
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+  /* PendSV_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/stm32wbxx_hal_timebase_tim.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/stm32wbxx_hal_timebase_tim.c
new file mode 100644
index 000000000..717e15eb1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/stm32wbxx_hal_timebase_tim.c
@@ -0,0 +1,136 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_timebase_tim.c
+  * @author  MCD Application Team
+  * @brief   HAL time base based on the hardware TIM.
+  *
+  *          This file overrides the native HAL time base functions (defined as weak)
+  *          the TIM time base:
+  *           + Intializes the TIM peripheral to generate a Period elapsed Event each 1ms
+  *           + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
+  *
+ @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    This file must be copied to the application folder and modified as follows:
+    (#) Rename it to 'stm32g0xx_hal_timebase_tim.c'
+    (#) Add this file and the TIM HAL driver files to your project and make sure
+       HAL_TIM_MODULE_ENABLED is defined in stm32l4xx_hal_conf.h
+
+    [..]
+    (@) The application needs to ensure that the time base is always set to 1 millisecond
+       to have correct HAL operation.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+#include "stm32wbxx_hal_tim.h"
+ 
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+TIM_HandleTypeDef        htim17; 
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  This function configures the TIM17 as a time base source. 
+  *         The time source is configured  to have 1ms time base with a dedicated 
+  *         Tick interrupt priority. 
+  * @note   This function is called  automatically at the beginning of program after
+  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). 
+  * @param  TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  RCC_ClkInitTypeDef    clkconfig;
+  uint32_t              uwTimclock = 0;
+  uint32_t              uwPrescalerValue = 0;
+  uint32_t              pFLatency;
+  
+  /*Configure the TIM17 IRQ priority */
+  HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM17_IRQn, TickPriority ,0); 
+  
+  /* Enable the TIM17 global Interrupt */
+  HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM17_IRQn); 
+  
+  /* Enable TIM17 clock */
+  __HAL_RCC_TIM17_CLK_ENABLE();
+  
+  /* Get clock configuration */
+  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
+  
+  /* Compute TIM17 clock */
+  uwTimclock = HAL_RCC_GetPCLK2Freq();
+   
+  /* Compute the prescaler value to have TIM17 counter clock equal to 1MHz */
+  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1);
+  
+  /* Initialize TIM17 */
+  htim17.Instance = TIM17;
+  
+  /* Initialize TIMx peripheral as follow:
+  + Period = [(TIM17CLK/1000) - 1]. to have a (1/1000) s time base.
+  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+  + ClockDivision = 0
+  + Counter direction = Up
+  */
+  htim17.Init.Period = (1000000 / 1000) - 1;
+  htim17.Init.Prescaler = uwPrescalerValue;
+  htim17.Init.ClockDivision = 0;
+  htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
+  if(HAL_TIM_Base_Init(&htim17) == HAL_OK)
+  {
+    /* Start the TIM time Base generation in interrupt mode */
+    return HAL_TIM_Base_Start_IT(&htim17);
+  }
+  
+  /* Return function status */
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Suspend Tick increment.
+  * @note   Disable the tick increment by disabling TIM17 update interrupt.
+  * @param  None
+  * @retval None
+  */
+void HAL_SuspendTick(void)
+{
+  /* Disable TIM17 update Interrupt */
+  __HAL_TIM_DISABLE_IT(&htim17, TIM_IT_UPDATE);                                                  
+}
+
+/**
+  * @brief  Resume Tick increment.
+  * @note   Enable the tick increment by Enabling TIM17 update interrupt.
+  * @param  None
+  * @retval None
+  */
+void HAL_ResumeTick(void)
+{
+  /* Enable TIM17 Update interrupt */
+  __HAL_TIM_ENABLE_IT(&htim17, TIM_IT_UPDATE);
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..0fbfb359b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/stm32wbxx_it.c
@@ -0,0 +1,183 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Mutexes/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+#include "FreeRTOS.h"
+#include "task.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern TIM_HandleTypeDef htim17;
+
+/* USER CODE BEGIN EV */
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt.
+  */
+void TIM1_TRG_COM_TIM17_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */
+
+  /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */
+  HAL_TIM_IRQHandler(&htim17);
+  /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */
+
+  /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/readme.txt b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/readme.txt
new file mode 100644
index 000000000..6ca5277a8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Mutexes/readme.txt
@@ -0,0 +1,106 @@
+/**
+  @page FreeRTOS_Mutexes FreeRTOS Mutexes example
+
+  @verbatim
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Mutexes/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the FreeRTOS Mutexes example.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Application Description
+
+How to use mutexes with CMSIS RTOS API.
+
+This application creates three threads, with different priorities, that access the
+same mutex, as described below:
+
+MutexHighPriorityThread() has the highest priority so executes
+first and grabs the mutex and sleeps for a short period to let the lower
+priority threads execute.  When it has completed its demo functionality
+it gives the mutex back before suspending itself.
+At that point, LED1 toggles.
+
+MutexMediumPriorityThread() attempts to access the mutex by performing
+a blocking 'wait'.  This thread blocks when the mutex is already taken
+by the high priority thread. It does not unblock until the highest
+priority thread  has released the mutex, and it does not actually run until
+the highest priority thread has suspended itself.
+When it eventually does obtain the mutex all it does is give the mutex back
+prior to also suspending itself.
+At this point both the high and medium priority threads are suspended and LED2 toggles.
+
+MutexLowPriorityThread() runs at the idle priority.  It spins round
+a tight loop attempting to obtain the mutex with a non-blocking call.  As
+the lowest priority thread it will not successfully obtain the mutex until
+both high and medium priority threads are suspended.  Once it eventually
+does obtains the mutex, it first resumes both suspended threads prior to giving the mutex back,
+resulting in the low priority thread temporarily inheriting the highest thread priority.
+
+In case of error, LED3 toggles.
+
+The following variables can be displayed on the debugger via LiveWatch:
+ - HighPriorityThreadCycles
+ - MediumPriorityThreadCycles
+ - LowPriorityThreadCycles
+ These variables must remain equals all the time. If not equal, it means a stall has occurred.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate
+      delay (in milliseconds) based on variable incremented in HAL time base ISR.
+      This implies that if HAL_Delay() is called from a peripheral ISR process, then
+      the HAL time base interrupt must have higher priority (numerically lower) than
+      the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the HAL time base interrupt priority you have to use HAL_NVIC_SetPriority()
+      function.
+
+@note The application needs to ensure that the HAL time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@note The FreeRTOS heap size configTOTAL_HEAP_SIZE defined in FreeRTOSConfig.h is set accordingly to the
+      OS resources memory requirements of the application with +10% margin and rounded to the upper Kbyte boundary.
+
+For more details about FreeRTOS implementation on STM32Cube, please refer to UM1722 "Developing Applications
+on STM32Cube with RTOS".
+
+
+@par Directory contents
+    - FreeRTOS/FreeRTOS_Mutexes/Src/main.c                       Main program
+    - FreeRTOS/FreeRTOS_Mutexes/Src/app_FreeRTOS.c               Code for freertos applications
+    - FreeRTOS/FreeRTOS_Mutexes/Src/stm32wbxx_hal_timebase_tim.c HAL timebase file
+    - FreeRTOS/FreeRTOS_Mutexes/Src/stm32wbxx_it.c               Interrupt handlers
+    - FreeRTOS/FreeRTOS_Mutexes/Src/stm32wbxx_hal_msp.c          MSP Initialization file
+    - FreeRTOS/FreeRTOS_Mutexes/Src/system_stm32wbxx.c           STM32WBxx system clock configuration file
+    - FreeRTOS/FreeRTOS_Mutexes/Inc/main.h                       Main program header file
+    - FreeRTOS/FreeRTOS_Mutexes/Inc/stm32wbxx_hal_conf.h         HAL Library Configuration file
+    - FreeRTOS/FreeRTOS_Mutexes/Inc/stm32wbxx_it.h               Interrupt handlers header file
+    - FreeRTOS/FreeRTOS_Mutexes/Inc/FreeRTOSConfig.h             FreeRTOS Configuration file
+
+@par Hardware and Software environment
+
+  - This application runs on STM32WB35CEUx devices.
+
+  - This application has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ?
+
+In order to make the program work, you must do the following:
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/.extSettings b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/.extSettings
new file mode 100644
index 000000000..e75e48ab0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/.extSettings
@@ -0,0 +1,9 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=TIM
+[Groups]
+Application/User=../Src/main.c;../Src/stm32wbxx_it.c;../Src/stm32wbxx_hal_timebase_tim.c;../Src/app_freertos.c;../Src/stm32wbxx_hal_msp.c;
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/FreeRTOS_Queues.ewd b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/FreeRTOS_Queues.ewd
new file mode 100644
index 000000000..066fa8b79
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/FreeRTOS_Queues.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		FreeRTOS_Queues
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/FreeRTOS_Queues.ewp b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/FreeRTOS_Queues.ewp
new file mode 100644
index 000000000..09734669d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/FreeRTOS_Queues.ewp
@@ -0,0 +1,1167 @@
+
+
+  3
+  
+    FreeRTOS_Queues
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_timebase_tim.c
+      
+      
+        $PROJ_DIR$/../Src/app_freertos.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+  
+    Middlewares
+    
+      FreeRTOS
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/croutine.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/list.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/queue.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/tasks.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/timers.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/Project.eww
new file mode 100644
index 000000000..d9a015be4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\FreeRTOS_Queues.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/stm32wb35xx_sram_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/stm32wb35xx_sram_cm4.icf
new file mode 100644
index 000000000..6426355fb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/EWARM/stm32wb35xx_sram_cm4.icf
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20003FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20004000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20008000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x2000FFFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/FreeRTOS_Queues.ioc b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/FreeRTOS_Queues.ioc
new file mode 100644
index 000000000..cc3215816
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/FreeRTOS_Queues.ioc
@@ -0,0 +1,163 @@
+#MicroXplorer Configuration settings - do not modify
+FREERTOS.FootprintOK=true
+FREERTOS.HEAP_NUMBER=4
+FREERTOS.INCLUDE_eTaskGetState=1
+FREERTOS.INCLUDE_pcTaskGetTaskName=0
+FREERTOS.INCLUDE_uxTaskGetStackHighWaterMark=0
+FREERTOS.INCLUDE_uxTaskPriorityGet=1
+FREERTOS.INCLUDE_vTaskCleanUpResources=0
+FREERTOS.INCLUDE_vTaskDelay=1
+FREERTOS.INCLUDE_vTaskDelayUntil=0
+FREERTOS.INCLUDE_vTaskDelete=1
+FREERTOS.INCLUDE_vTaskPrioritySet=1
+FREERTOS.INCLUDE_vTaskSuspend=1
+FREERTOS.INCLUDE_xEventGroupSetBitFromISR=0
+FREERTOS.INCLUDE_xQueueGetMutexHolder=1
+FREERTOS.INCLUDE_xSemaphoreGetMutexHolder=0
+FREERTOS.INCLUDE_xTaskAbortDelay=0
+FREERTOS.INCLUDE_xTaskGetCurrentTaskHandle=0
+FREERTOS.INCLUDE_xTaskGetHandle=0
+FREERTOS.INCLUDE_xTaskResumeFromISR=1
+FREERTOS.IPParameters=Tasks01,configUSE_RECURSIVE_MUTEXES,configUSE_COUNTING_SEMAPHORES,configTOTAL_HEAP_SIZE,configUSE_TRACE_FACILITY,configLIBRARY_LOWEST_INTERRUPT_PRIORITY,configIDLE_SHOULD_YIELD,INCLUDE_vTaskCleanUpResources,INCLUDE_vTaskDelayUntil,INCLUDE_eTaskGetState,INCLUDE_xQueueGetMutexHolder,INCLUDE_xTaskResumeFromISR,Queues01,FootprintOK,configUSE_PREEMPTION,MEMORY_ALLOCATION,configTICK_RATE_HZ,configMAX_PRIORITIES,configMINIMAL_STACK_SIZE,configMAX_TASK_NAME_LEN,configUSE_MUTEXES,configQUEUE_REGISTRY_SIZE,configUSE_APPLICATION_TASK_TAG,HEAP_NUMBER,configUSE_IDLE_HOOK,configUSE_TICK_HOOK,configUSE_MALLOC_FAILED_HOOK,configUSE_DAEMON_TASK_STARTUP_HOOK,configCHECK_FOR_STACK_OVERFLOW,configGENERATE_RUN_TIME_STATS,configUSE_STATS_FORMATTING_FUNCTIONS,configUSE_CO_ROUTINES,configMAX_CO_ROUTINE_PRIORITIES,configUSE_TIMERS,configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY,INCLUDE_vTaskPrioritySet,INCLUDE_uxTaskPriorityGet,INCLUDE_vTaskDelete,INCLUDE_vTaskSuspend,INCLUDE_vTaskDelay,INCLUDE_xSemaphoreGetMutexHolder,INCLUDE_pcTaskGetTaskName,INCLUDE_uxTaskGetStackHighWaterMark,INCLUDE_xTaskGetCurrentTaskHandle,INCLUDE_xEventGroupSetBitFromISR,configENABLE_BACKWARD_COMPATIBILITY,configUSE_TICKLESS_IDLE,configUSE_TASK_NOTIFICATIONS,INCLUDE_xTaskAbortDelay,INCLUDE_xTaskGetHandle,configRECORD_STACK_HIGH_ADDRESS
+FREERTOS.MEMORY_ALLOCATION=0
+FREERTOS.Queues01=osQueue,1,uint16_t,0,Dynamic,NULL,NULL
+FREERTOS.Tasks01=MessageQueuePro,-1,128,MessageQueueProducer,Default,NULL,Dynamic,NULL,NULL;MessageQueueCon,-1,128,MessageQueueConsumer,Default,NULL,Dynamic,NULL,NULL
+FREERTOS.configCHECK_FOR_STACK_OVERFLOW=0
+FREERTOS.configENABLE_BACKWARD_COMPATIBILITY=1
+FREERTOS.configGENERATE_RUN_TIME_STATS=0
+FREERTOS.configIDLE_SHOULD_YIELD=1
+FREERTOS.configLIBRARY_LOWEST_INTERRUPT_PRIORITY=15
+FREERTOS.configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY=5
+FREERTOS.configMAX_CO_ROUTINE_PRIORITIES=2
+FREERTOS.configMAX_PRIORITIES=7
+FREERTOS.configMAX_TASK_NAME_LEN=16
+FREERTOS.configMINIMAL_STACK_SIZE=128
+FREERTOS.configQUEUE_REGISTRY_SIZE=8
+FREERTOS.configRECORD_STACK_HIGH_ADDRESS=0
+FREERTOS.configTICK_RATE_HZ=1000
+FREERTOS.configTOTAL_HEAP_SIZE=3072
+FREERTOS.configUSE_APPLICATION_TASK_TAG=0
+FREERTOS.configUSE_COUNTING_SEMAPHORES=1
+FREERTOS.configUSE_CO_ROUTINES=0
+FREERTOS.configUSE_DAEMON_TASK_STARTUP_HOOK=0
+FREERTOS.configUSE_IDLE_HOOK=0
+FREERTOS.configUSE_MALLOC_FAILED_HOOK=0
+FREERTOS.configUSE_MUTEXES=1
+FREERTOS.configUSE_PREEMPTION=1
+FREERTOS.configUSE_RECURSIVE_MUTEXES=1
+FREERTOS.configUSE_STATS_FORMATTING_FUNCTIONS=0
+FREERTOS.configUSE_TASK_NOTIFICATIONS=1
+FREERTOS.configUSE_TICKLESS_IDLE=0
+FREERTOS.configUSE_TICK_HOOK=0
+FREERTOS.configUSE_TIMERS=0
+FREERTOS.configUSE_TRACE_FACILITY=1
+File.Version=6
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=FREERTOS
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_FREERTOS_VS_CMSIS_V1
+Mcu.Pin1=VP_SYS_VS_tim17
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false
+NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:true\:false
+NVIC.TIM1_TRG_COM_TIM17_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
+NVIC.TimeBase=TIM1_TRG_COM_TIM17_IRQn
+NVIC.TimeBaseIP=TIM17
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=FreeRTOS_Queues.ioc
+ProjectManager.ProjectName=FreeRTOS_Queues
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_FREERTOS_VS_CMSIS_V1.Mode=CMSIS_V1
+VP_FREERTOS_VS_CMSIS_V1.Signal=FREERTOS_VS_CMSIS_V1
+VP_SYS_VS_tim17.Mode=TIM17
+VP_SYS_VS_tim17.Signal=SYS_VS_tim17
+board=STM32G081B-EVAL
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Inc/FreeRTOSConfig.h b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Inc/FreeRTOSConfig.h
new file mode 100644
index 000000000..de661759c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Inc/FreeRTOSConfig.h
@@ -0,0 +1,143 @@
+/* USER CODE BEGIN Header */
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+/* USER CODE END Header */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+/* USER CODE BEGIN Includes */   	      
+/* Section where include file can be added */
+/* USER CODE END Includes */ 
+
+/* Ensure definitions are only used by the compiler, and not by the assembler. */
+#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
+  #include 
+  extern uint32_t SystemCoreClock;
+#endif
+#define configENABLE_FPU                         0
+#define configENABLE_MPU                         0
+
+#define configUSE_PREEMPTION                     1
+#define configSUPPORT_STATIC_ALLOCATION          0
+#define configSUPPORT_DYNAMIC_ALLOCATION         1
+#define configUSE_IDLE_HOOK                      0
+#define configUSE_TICK_HOOK                      0
+#define configCPU_CLOCK_HZ                       ( SystemCoreClock )
+#define configTICK_RATE_HZ                       ((TickType_t)1000)
+#define configMAX_PRIORITIES                     ( 7 )
+#define configMINIMAL_STACK_SIZE                 ((uint16_t)128)
+#define configTOTAL_HEAP_SIZE                    ((size_t)3072)
+#define configMAX_TASK_NAME_LEN                  ( 16 )
+#define configUSE_TRACE_FACILITY                 1
+#define configUSE_16_BIT_TICKS                   0
+#define configUSE_MUTEXES                        1
+#define configQUEUE_REGISTRY_SIZE                8
+#define configUSE_RECURSIVE_MUTEXES              1
+#define configUSE_COUNTING_SEMAPHORES            1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION  1
+/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */
+/* Defaults to size_t for backward compatibility, but can be changed
+   if lengths will always be less than the number of bytes in a size_t. */
+#define configMESSAGE_BUFFER_LENGTH_TYPE         size_t
+/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */ 
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                    0
+#define configMAX_CO_ROUTINE_PRIORITIES          ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet             1
+#define INCLUDE_uxTaskPriorityGet            1
+#define INCLUDE_vTaskDelete                  1
+#define INCLUDE_vTaskCleanUpResources        0
+#define INCLUDE_vTaskSuspend                 1
+#define INCLUDE_vTaskDelayUntil              0
+#define INCLUDE_vTaskDelay                   1
+#define INCLUDE_xTaskGetSchedulerState       1
+#define INCLUDE_xQueueGetMutexHolder         1
+#define INCLUDE_eTaskGetState                1
+
+/* Cortex-M specific definitions. */
+#ifdef __NVIC_PRIO_BITS
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+ #define configPRIO_BITS         __NVIC_PRIO_BITS
+#else
+ #define configPRIO_BITS         4
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY   15
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* Normal assert() semantics without relying on the provision of an assert.h
+header file. */
+/* USER CODE BEGIN 1 */
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
+/* USER CODE END 1 */
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler    SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+
+/* IMPORTANT: This define is commented when used with STM32Cube firmware, when the timebase source is SysTick,
+              to prevent overwriting SysTick_Handler defined within STM32Cube HAL */
+ 
+#define xPortSysTickHandler SysTick_Handler
+
+/* USER CODE BEGIN Defines */   	      
+/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */
+/* USER CODE END Defines */ 
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Inc/main.h b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Inc/main.h
new file mode 100644
index 000000000..deb325342
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Inc/main.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Queues/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the main.c
+  *          file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..3e4ba1426
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..ee353943d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Inc/stm32wbxx_it.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Queues/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void DebugMon_Handler(void);
+void TIM1_TRG_COM_TIM17_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/MDK-ARM/FreeRTOS_Queues.uvoptx b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/MDK-ARM/FreeRTOS_Queues.uvoptx
new file mode 100644
index 000000000..ed40813f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/MDK-ARM/FreeRTOS_Queues.uvoptx
@@ -0,0 +1,649 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    FreeRTOS_Queues
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_timebase_tim.c
+      stm32wbxx_hal_timebase_tim.c
+      0
+      0
+    
+    
+      3
+      5
+      1
+      0
+      0
+      0
+      ../Src/app_freertos.c
+      app_freertos.c
+      0
+      0
+    
+    
+      3
+      6
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      7
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      24
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    Middlewares/FreeRTOS
+    0
+    0
+    0
+    0
+    
+      8
+      25
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/croutine.c
+      croutine.c
+      0
+      0
+    
+    
+      8
+      26
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
+      event_groups.c
+      0
+      0
+    
+    
+      8
+      27
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/list.c
+      list.c
+      0
+      0
+    
+    
+      8
+      28
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/queue.c
+      queue.c
+      0
+      0
+    
+    
+      8
+      29
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
+      stream_buffer.c
+      0
+      0
+    
+    
+      8
+      30
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/tasks.c
+      tasks.c
+      0
+      0
+    
+    
+      8
+      31
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/timers.c
+      timers.c
+      0
+      0
+    
+    
+      8
+      32
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c
+      cmsis_os.c
+      0
+      0
+    
+    
+      8
+      33
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
+      heap_4.c
+      0
+      0
+    
+    
+      8
+      34
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
+      port.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/MDK-ARM/FreeRTOS_Queues.uvprojx b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/MDK-ARM/FreeRTOS_Queues.uvprojx
new file mode 100644
index 000000000..e8d094737
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/MDK-ARM/FreeRTOS_Queues.uvprojx
@@ -0,0 +1,606 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      FreeRTOS_Queues
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          FreeRTOS_Queues\
+          FreeRTOS_Queues
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Middlewares/Third_Party/FreeRTOS/Source/include;../../../../../../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS;../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              ..\Inc
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_timebase_tim.c
+              1
+              ../Src/stm32wbxx_hal_timebase_tim.c
+            
+            
+              app_freertos.c
+              1
+              ../Src/app_freertos.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          Middlewares/FreeRTOS
+          
+            
+              croutine.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/croutine.c
+            
+            
+              event_groups.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
+            
+            
+              list.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/list.c
+            
+            
+              queue.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/queue.c
+            
+            
+              stream_buffer.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
+            
+            
+              tasks.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/tasks.c
+            
+            
+              timers.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/timers.c
+            
+            
+              cmsis_os.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c
+            
+            
+              heap_4.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
+            
+            
+              port.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..6f149d2b8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/.cproject
@@ -0,0 +1,175 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/.project
new file mode 100644
index 000000000..6e0eb8fe4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/.project
@@ -0,0 +1,205 @@
+
+
+	FreeRTOS_Queues
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			FreeRTOS_Queues.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/FreeRTOS_Queues.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/app_freertos.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/app_freertos.c
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_hal_timebase_tim.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_timebase_tim.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Middlewares/FreeRTOS/cmsis_os.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c
+		
+		
+			Middlewares/FreeRTOS/croutine.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/croutine.c
+		
+		
+			Middlewares/FreeRTOS/event_groups.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
+		
+		
+			Middlewares/FreeRTOS/heap_4.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
+		
+		
+			Middlewares/FreeRTOS/list.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/list.c
+		
+		
+			Middlewares/FreeRTOS/port.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
+		
+		
+			Middlewares/FreeRTOS/queue.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/queue.c
+		
+		
+			Middlewares/FreeRTOS/stream_buffer.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
+		
+		
+			Middlewares/FreeRTOS/tasks.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
+		
+		
+			Middlewares/FreeRTOS/timers.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/timers.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/app_freertos.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/app_freertos.c
new file mode 100644
index 000000000..719aa1beb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/app_freertos.c
@@ -0,0 +1,62 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Queues/Src/freertos.c
+  * @author  MCD Application Team
+  * @brief   Code for freertos applications
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "FreeRTOS.h"
+#include "task.h"
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */     
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN Variables */
+
+/* USER CODE END Variables */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN FunctionPrototypes */
+
+/* USER CODE END FunctionPrototypes */
+
+/* Private application code --------------------------------------------------*/
+/* USER CODE BEGIN Application */
+
+/* USER CODE END Application */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/main.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/main.c
new file mode 100644
index 000000000..126a89e34
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/main.c
@@ -0,0 +1,355 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Queues/Src/main.c
+  * @author  MCD Application Team
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+#define blckqSTACK_SIZE   configMINIMAL_STACK_SIZE
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+osThreadId MessageQueueProHandle;
+osThreadId MessageQueueConHandle;
+osMessageQId osQueueHandle;
+/* USER CODE BEGIN PV */
+uint32_t ProducerValue = 0, ConsumerValue = 0;
+__IO uint32_t ProducerErrors = 0, ConsumerErrors = 0;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+void MessageQueueProducer(void const * argument);
+void MessageQueueConsumer(void const * argument);
+
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* Initialize LEDs */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* USER CODE BEGIN RTOS_MUTEX */
+
+  /* USER CODE END RTOS_MUTEX */
+
+  /* USER CODE BEGIN RTOS_SEMAPHORES */
+
+  /* USER CODE END RTOS_SEMAPHORES */
+
+  /* USER CODE BEGIN RTOS_TIMERS */
+
+  /* USER CODE END RTOS_TIMERS */
+
+  /* Create the queue(s) */
+  /* definition and creation of osQueue */
+  osMessageQDef(osQueue, 1, uint16_t);
+  osQueueHandle = osMessageCreate(osMessageQ(osQueue), NULL);
+
+  /* USER CODE BEGIN RTOS_QUEUES */
+
+  /* USER CODE END RTOS_QUEUES */
+
+  /* Create the thread(s) */
+  /* definition and creation of MessageQueuePro */
+  osThreadDef(MessageQueuePro, MessageQueueProducer, osPriorityBelowNormal, 0, 128);
+  MessageQueueProHandle = osThreadCreate(osThread(MessageQueuePro), NULL);
+
+  /* definition and creation of MessageQueueCon */
+  osThreadDef(MessageQueueCon, MessageQueueConsumer, osPriorityBelowNormal, 0, 128);
+  MessageQueueConHandle = osThreadCreate(osThread(MessageQueueCon), NULL);
+
+  /* USER CODE BEGIN RTOS_THREADS */
+
+  /* USER CODE END RTOS_THREADS */
+
+  /* Start scheduler */
+  osKernelStart();
+ 
+  /* We should never get here as control is now taken by the scheduler */
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/* USER CODE BEGIN Header_MessageQueueProducer */
+/**
+  * @brief  Function implementing the MessageQueuePro thread.
+  * @param  argument: Not used
+  * @retval None
+  */
+/* USER CODE END Header_MessageQueueProducer */
+void MessageQueueProducer(void const * argument)
+{
+  /* USER CODE BEGIN 5 */
+  /* Infinite loop */
+  for (;;)
+  {
+    if (osMessagePut(osQueueHandle, ProducerValue, 100) != osOK)
+    {
+      ++ProducerErrors;
+
+      /* Toggle LED3 to indicate error  */
+      BSP_LED_Toggle(LED3);
+    }
+    else
+    {
+      /* Increment the variable we are going to post next time round.  The
+      consumer will expect the numbers to follow in numerical order */
+      ++ProducerValue;
+
+      /* Toggle LED2 to indicate a correct number received  */
+      BSP_LED_Toggle(LED2);
+      osDelay(1000);
+    }
+  }
+  /* USER CODE END 5 */ 
+}
+
+/* USER CODE BEGIN Header_MessageQueueConsumer */
+/**
+* @brief Function implementing the MessageQueueCon thread.
+  * @param  argument: Not used
+  * @retval None
+  */
+/* USER CODE END Header_MessageQueueConsumer */
+void MessageQueueConsumer(void const * argument)
+{
+  /* USER CODE BEGIN MessageQueueConsumer */
+  osEvent event;
+
+  for (;;)
+  {
+    /* Get the message from the queue */
+    event = osMessageGet(osQueueHandle, 100);
+
+    if (event.status == osEventMessage)
+    {
+      if (event.value.v != ConsumerValue)
+      {
+        /* Catch-up */
+        ConsumerValue = event.value.v;
+
+        ++ConsumerErrors;
+
+      /* Toggle LED3 to indicate error */
+        BSP_LED_Toggle(LED3);
+      }
+      else
+      {
+        /* Increment the value we expect to remove from the queue next time
+        round */
+        ++ConsumerValue;
+      }
+    }
+  }
+  /* USER CODE END MessageQueueConsumer */
+}
+
+/**
+  * @brief  Period elapsed callback in non blocking mode
+  * @note   This function is called  when TIM17 interrupt took place, inside
+  * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+  * a global variable "uwTick" used as application time base.
+  * @param  htim : TIM handle
+  * @retval None
+  */
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* USER CODE BEGIN Callback 0 */
+
+  /* USER CODE END Callback 0 */
+  if (htim->Instance == TIM17) {
+    HAL_IncTick();
+  }
+  /* USER CODE BEGIN Callback 1 */
+
+  /* USER CODE END Callback 1 */
+}
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {}
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..3b3f4c342
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,84 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Queues/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   This file provides code for the MSP Initialization
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+  /* PendSV_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/stm32wbxx_hal_timebase_tim.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/stm32wbxx_hal_timebase_tim.c
new file mode 100644
index 000000000..717e15eb1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/stm32wbxx_hal_timebase_tim.c
@@ -0,0 +1,136 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_timebase_tim.c
+  * @author  MCD Application Team
+  * @brief   HAL time base based on the hardware TIM.
+  *
+  *          This file overrides the native HAL time base functions (defined as weak)
+  *          the TIM time base:
+  *           + Intializes the TIM peripheral to generate a Period elapsed Event each 1ms
+  *           + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
+  *
+ @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    This file must be copied to the application folder and modified as follows:
+    (#) Rename it to 'stm32g0xx_hal_timebase_tim.c'
+    (#) Add this file and the TIM HAL driver files to your project and make sure
+       HAL_TIM_MODULE_ENABLED is defined in stm32l4xx_hal_conf.h
+
+    [..]
+    (@) The application needs to ensure that the time base is always set to 1 millisecond
+       to have correct HAL operation.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+#include "stm32wbxx_hal_tim.h"
+ 
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+TIM_HandleTypeDef        htim17; 
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  This function configures the TIM17 as a time base source. 
+  *         The time source is configured  to have 1ms time base with a dedicated 
+  *         Tick interrupt priority. 
+  * @note   This function is called  automatically at the beginning of program after
+  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). 
+  * @param  TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  RCC_ClkInitTypeDef    clkconfig;
+  uint32_t              uwTimclock = 0;
+  uint32_t              uwPrescalerValue = 0;
+  uint32_t              pFLatency;
+  
+  /*Configure the TIM17 IRQ priority */
+  HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM17_IRQn, TickPriority ,0); 
+  
+  /* Enable the TIM17 global Interrupt */
+  HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM17_IRQn); 
+  
+  /* Enable TIM17 clock */
+  __HAL_RCC_TIM17_CLK_ENABLE();
+  
+  /* Get clock configuration */
+  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
+  
+  /* Compute TIM17 clock */
+  uwTimclock = HAL_RCC_GetPCLK2Freq();
+   
+  /* Compute the prescaler value to have TIM17 counter clock equal to 1MHz */
+  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1);
+  
+  /* Initialize TIM17 */
+  htim17.Instance = TIM17;
+  
+  /* Initialize TIMx peripheral as follow:
+  + Period = [(TIM17CLK/1000) - 1]. to have a (1/1000) s time base.
+  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+  + ClockDivision = 0
+  + Counter direction = Up
+  */
+  htim17.Init.Period = (1000000 / 1000) - 1;
+  htim17.Init.Prescaler = uwPrescalerValue;
+  htim17.Init.ClockDivision = 0;
+  htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
+  if(HAL_TIM_Base_Init(&htim17) == HAL_OK)
+  {
+    /* Start the TIM time Base generation in interrupt mode */
+    return HAL_TIM_Base_Start_IT(&htim17);
+  }
+  
+  /* Return function status */
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Suspend Tick increment.
+  * @note   Disable the tick increment by disabling TIM17 update interrupt.
+  * @param  None
+  * @retval None
+  */
+void HAL_SuspendTick(void)
+{
+  /* Disable TIM17 update Interrupt */
+  __HAL_TIM_DISABLE_IT(&htim17, TIM_IT_UPDATE);                                                  
+}
+
+/**
+  * @brief  Resume Tick increment.
+  * @note   Enable the tick increment by Enabling TIM17 update interrupt.
+  * @param  None
+  * @retval None
+  */
+void HAL_ResumeTick(void)
+{
+  /* Enable TIM17 Update interrupt */
+  __HAL_TIM_ENABLE_IT(&htim17, TIM_IT_UPDATE);
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..a6dcd2640
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/stm32wbxx_it.c
@@ -0,0 +1,183 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Queues/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+#include "FreeRTOS.h"
+#include "task.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern TIM_HandleTypeDef htim17;
+
+/* USER CODE BEGIN EV */
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt.
+  */
+void TIM1_TRG_COM_TIM17_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */
+
+  /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */
+  HAL_TIM_IRQHandler(&htim17);
+  /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */
+
+  /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/readme.txt b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/readme.txt
new file mode 100644
index 000000000..109f501c1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Queues/readme.txt
@@ -0,0 +1,90 @@
+/**
+  @page FreeRTOS_Queues FreeRTOS Queues example
+
+  @verbatim
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Queues/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the FreeRTOS Queues example.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Application Description
+
+How to use message queues with CMSIS RTOS API.
+
+This application creates two threads that send and receive an incrementing number
+to/from a queue, as following:
+One thread acts as a producer and the other as the consumer. The consumer
+is a higher priority than the producer and is set to block on queue reads.
+The queue only has space for one item, as soon as the producer posts a
+message on the queue (every 1 second) the consumer will unblock, preempt
+the producer, and remove the item.
+
+Add the following variables to LiveWatch, these variables must remain equals all the time:
+ - ProducerValue
+ - ConsumerValue
+
+NUCLEO-WB35CE's LEDs can be used to monitor the application status:
+  - LED2 should toggle as soon as the producer posts a
+    message on the queue (every 1 second).
+  - LED3 should toggle each time any error occurs.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate
+      delay (in milliseconds) based on variable incremented in HAL time base ISR.
+      This implies that if HAL_Delay() is called from a peripheral ISR process, then
+      the HAL time base interrupt must have higher priority (numerically lower) than
+      the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the HAL time base interrupt priority you have to use HAL_NVIC_SetPriority()
+      function.
+
+@note The application needs to ensure that the HAL time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@note The FreeRTOS heap size configTOTAL_HEAP_SIZE defined in FreeRTOSConfig.h is set accordingly to the
+      OS resources memory requirements of the application with +10% margin and rounded to the upper Kbyte boundary.
+
+For more details about FreeRTOS implementation on STM32Cube, please refer to UM1722 "Developing Applications
+on STM32Cube with RTOS".
+
+
+@par Directory contents
+    - FreeRTOS/FreeRTOS_Queues/Src/main.c                       Main program
+  - FreeRTOS/FreeRTOS_Queues/Src/app_FreeRTOS.c               Code for freertos applications
+    - FreeRTOS/FreeRTOS_Queues/Src/stm32wbxx_hal_timebase_tim.c HAL timebase file
+    - FreeRTOS/FreeRTOS_Queues/Src/stm32wbxx_it.c               Interrupt handlers
+  - FreeRTOS/FreeRTOS_Queues/Src/stm32wbxx_hal_msp.c          MSP Initialization file
+    - FreeRTOS/FreeRTOS_Queues/Src/system_stm32wbxx.c           STM32WBxx system clock configuration file
+    - FreeRTOS/FreeRTOS_Queues/Inc/main.h                       Main program header file
+    - FreeRTOS/FreeRTOS_Queues/Inc/stm32wbxx_hal_conf.h         HAL Library Configuration file
+    - FreeRTOS/FreeRTOS_Queues/Inc/stm32wbxx_it.h               Interrupt handlers header file
+    - FreeRTOS/FreeRTOS_Queues/Inc/FreeRTOSConfig.h             FreeRTOS Configuration file
+
+@par Hardware and Software environment
+
+  - This application runs on STM32WB35CEUx devices.
+
+  - This application has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ?
+
+In order to make the program work, you must do the following:
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/.extSettings b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/.extSettings
new file mode 100644
index 000000000..cec189c91
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/.extSettings
@@ -0,0 +1,9 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=TIM
+[Groups]
+Application/User=../Src/main.c;../Src/stm32wbxx_it.c;../Src/stm32wbxx_hal_timebase_tim.c;../Src/stm32wbxx_hal_msp.c;../Src/app_freertos.c;
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/FreeRTOS_Semaphore.ewd b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/FreeRTOS_Semaphore.ewd
new file mode 100644
index 000000000..57ff78d37
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/FreeRTOS_Semaphore.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		FreeRTOS_Semaphore
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/FreeRTOS_Semaphore.ewp b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/FreeRTOS_Semaphore.ewp
new file mode 100644
index 000000000..4deb23e72
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/FreeRTOS_Semaphore.ewp
@@ -0,0 +1,1167 @@
+
+
+  3
+  
+    FreeRTOS_Semaphore
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_timebase_tim.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+      
+        $PROJ_DIR$/../Src/app_freertos.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+  
+    Middlewares
+    
+      FreeRTOS
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/croutine.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/list.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/queue.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/tasks.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/timers.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/Project.eww
new file mode 100644
index 000000000..7ab62b75c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\FreeRTOS_Semaphore.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/stm32wb35xx_sram_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/stm32wb35xx_sram_cm4.icf
new file mode 100644
index 000000000..6426355fb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/EWARM/stm32wb35xx_sram_cm4.icf
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20003FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20004000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20008000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x2000FFFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/FreeRTOS_Semaphore.ioc b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/FreeRTOS_Semaphore.ioc
new file mode 100644
index 000000000..d5c1900fa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/FreeRTOS_Semaphore.ioc
@@ -0,0 +1,162 @@
+#MicroXplorer Configuration settings - do not modify
+FREERTOS.BinarySemaphores01=osSemaphore,Dynamic,NULL
+FREERTOS.HEAP_NUMBER=4
+FREERTOS.INCLUDE_eTaskGetState=1
+FREERTOS.INCLUDE_pcTaskGetTaskName=0
+FREERTOS.INCLUDE_uxTaskGetStackHighWaterMark=0
+FREERTOS.INCLUDE_uxTaskPriorityGet=1
+FREERTOS.INCLUDE_vTaskCleanUpResources=0
+FREERTOS.INCLUDE_vTaskDelay=1
+FREERTOS.INCLUDE_vTaskDelayUntil=0
+FREERTOS.INCLUDE_vTaskDelete=1
+FREERTOS.INCLUDE_vTaskPrioritySet=1
+FREERTOS.INCLUDE_vTaskSuspend=1
+FREERTOS.INCLUDE_xEventGroupSetBitFromISR=0
+FREERTOS.INCLUDE_xQueueGetMutexHolder=1
+FREERTOS.INCLUDE_xSemaphoreGetMutexHolder=0
+FREERTOS.INCLUDE_xTaskAbortDelay=0
+FREERTOS.INCLUDE_xTaskGetCurrentTaskHandle=0
+FREERTOS.INCLUDE_xTaskGetHandle=0
+FREERTOS.INCLUDE_xTaskResumeFromISR=1
+FREERTOS.IPParameters=Tasks01,configUSE_RECURSIVE_MUTEXES,configUSE_COUNTING_SEMAPHORES,configTOTAL_HEAP_SIZE,configUSE_TRACE_FACILITY,configLIBRARY_LOWEST_INTERRUPT_PRIORITY,configIDLE_SHOULD_YIELD,INCLUDE_xTaskResumeFromISR,INCLUDE_xQueueGetMutexHolder,INCLUDE_eTaskGetState,BinarySemaphores01,configUSE_PREEMPTION,MEMORY_ALLOCATION,configTICK_RATE_HZ,configMAX_PRIORITIES,configMINIMAL_STACK_SIZE,configMAX_TASK_NAME_LEN,configUSE_MUTEXES,configQUEUE_REGISTRY_SIZE,configUSE_APPLICATION_TASK_TAG,HEAP_NUMBER,configUSE_IDLE_HOOK,configUSE_TICK_HOOK,configUSE_MALLOC_FAILED_HOOK,configUSE_DAEMON_TASK_STARTUP_HOOK,configCHECK_FOR_STACK_OVERFLOW,configGENERATE_RUN_TIME_STATS,configUSE_STATS_FORMATTING_FUNCTIONS,configUSE_CO_ROUTINES,configMAX_CO_ROUTINE_PRIORITIES,configUSE_TIMERS,configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY,INCLUDE_vTaskPrioritySet,INCLUDE_uxTaskPriorityGet,INCLUDE_vTaskDelete,INCLUDE_vTaskCleanUpResources,INCLUDE_vTaskSuspend,INCLUDE_vTaskDelayUntil,INCLUDE_vTaskDelay,INCLUDE_xSemaphoreGetMutexHolder,INCLUDE_pcTaskGetTaskName,INCLUDE_uxTaskGetStackHighWaterMark,INCLUDE_xTaskGetCurrentTaskHandle,INCLUDE_xEventGroupSetBitFromISR,configENABLE_BACKWARD_COMPATIBILITY,configUSE_TICKLESS_IDLE,configUSE_TASK_NOTIFICATIONS,INCLUDE_xTaskAbortDelay,INCLUDE_xTaskGetHandle,configRECORD_STACK_HIGH_ADDRESS
+FREERTOS.MEMORY_ALLOCATION=0
+FREERTOS.Tasks01=SEM_Thread1,-2,128,SemaphoreThread1,Default,(void *) osSemaphoreHandle,Dynamic,NULL,NULL;SEM_Thread2,-3,128,SemaphoreThread2,Default,(void *) osSemaphoreHandle,Dynamic,NULL,NULL
+FREERTOS.configCHECK_FOR_STACK_OVERFLOW=0
+FREERTOS.configENABLE_BACKWARD_COMPATIBILITY=1
+FREERTOS.configGENERATE_RUN_TIME_STATS=0
+FREERTOS.configIDLE_SHOULD_YIELD=0
+FREERTOS.configLIBRARY_LOWEST_INTERRUPT_PRIORITY=15
+FREERTOS.configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY=5
+FREERTOS.configMAX_CO_ROUTINE_PRIORITIES=2
+FREERTOS.configMAX_PRIORITIES=7
+FREERTOS.configMAX_TASK_NAME_LEN=16
+FREERTOS.configMINIMAL_STACK_SIZE=128
+FREERTOS.configQUEUE_REGISTRY_SIZE=8
+FREERTOS.configRECORD_STACK_HIGH_ADDRESS=0
+FREERTOS.configTICK_RATE_HZ=1000
+FREERTOS.configTOTAL_HEAP_SIZE=3072
+FREERTOS.configUSE_APPLICATION_TASK_TAG=0
+FREERTOS.configUSE_COUNTING_SEMAPHORES=1
+FREERTOS.configUSE_CO_ROUTINES=0
+FREERTOS.configUSE_DAEMON_TASK_STARTUP_HOOK=0
+FREERTOS.configUSE_IDLE_HOOK=0
+FREERTOS.configUSE_MALLOC_FAILED_HOOK=0
+FREERTOS.configUSE_MUTEXES=1
+FREERTOS.configUSE_PREEMPTION=1
+FREERTOS.configUSE_RECURSIVE_MUTEXES=1
+FREERTOS.configUSE_STATS_FORMATTING_FUNCTIONS=0
+FREERTOS.configUSE_TASK_NOTIFICATIONS=1
+FREERTOS.configUSE_TICKLESS_IDLE=0
+FREERTOS.configUSE_TICK_HOOK=0
+FREERTOS.configUSE_TIMERS=0
+FREERTOS.configUSE_TRACE_FACILITY=1
+File.Version=6
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=FREERTOS
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_FREERTOS_VS_CMSIS_V1
+Mcu.Pin1=VP_SYS_VS_tim17
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false
+NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:true\:false
+NVIC.TIM1_TRG_COM_TIM17_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
+NVIC.TimeBase=TIM1_TRG_COM_TIM17_IRQn
+NVIC.TimeBaseIP=TIM17
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=FreeRTOS_Semaphore.ioc
+ProjectManager.ProjectName=FreeRTOS_Semaphore
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_FREERTOS_VS_CMSIS_V1.Mode=CMSIS_V1
+VP_FREERTOS_VS_CMSIS_V1.Signal=FREERTOS_VS_CMSIS_V1
+VP_SYS_VS_tim17.Mode=TIM17
+VP_SYS_VS_tim17.Signal=SYS_VS_tim17
+board=STM32G081B-EVAL
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Inc/FreeRTOSConfig.h b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Inc/FreeRTOSConfig.h
new file mode 100644
index 000000000..2275b8c98
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Inc/FreeRTOSConfig.h
@@ -0,0 +1,144 @@
+/* USER CODE BEGIN Header */
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+/* USER CODE END Header */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+/* USER CODE BEGIN Includes */   	      
+/* Section where include file can be added */
+/* USER CODE END Includes */ 
+
+/* Ensure definitions are only used by the compiler, and not by the assembler. */
+#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
+  #include 
+  extern uint32_t SystemCoreClock;
+#endif
+#define configENABLE_FPU                         0
+#define configENABLE_MPU                         0
+
+#define configUSE_PREEMPTION                     1
+#define configSUPPORT_STATIC_ALLOCATION          0
+#define configSUPPORT_DYNAMIC_ALLOCATION         1
+#define configUSE_IDLE_HOOK                      0
+#define configUSE_TICK_HOOK                      0
+#define configCPU_CLOCK_HZ                       ( SystemCoreClock )
+#define configTICK_RATE_HZ                       ((TickType_t)1000)
+#define configMAX_PRIORITIES                     ( 7 )
+#define configMINIMAL_STACK_SIZE                 ((uint16_t)128)
+#define configTOTAL_HEAP_SIZE                    ((size_t)3072)
+#define configMAX_TASK_NAME_LEN                  ( 16 )
+#define configUSE_TRACE_FACILITY                 1
+#define configUSE_16_BIT_TICKS                   0
+#define configIDLE_SHOULD_YIELD                  0
+#define configUSE_MUTEXES                        1
+#define configQUEUE_REGISTRY_SIZE                8
+#define configUSE_RECURSIVE_MUTEXES              1
+#define configUSE_COUNTING_SEMAPHORES            1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION  1
+/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */
+/* Defaults to size_t for backward compatibility, but can be changed
+   if lengths will always be less than the number of bytes in a size_t. */
+#define configMESSAGE_BUFFER_LENGTH_TYPE         size_t
+/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */ 
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                    0
+#define configMAX_CO_ROUTINE_PRIORITIES          ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet             1
+#define INCLUDE_uxTaskPriorityGet            1
+#define INCLUDE_vTaskDelete                  1
+#define INCLUDE_vTaskCleanUpResources        0
+#define INCLUDE_vTaskSuspend                 1
+#define INCLUDE_vTaskDelayUntil              0
+#define INCLUDE_vTaskDelay                   1
+#define INCLUDE_xTaskGetSchedulerState       1
+#define INCLUDE_xQueueGetMutexHolder         1
+#define INCLUDE_eTaskGetState                1
+
+/* Cortex-M specific definitions. */
+#ifdef __NVIC_PRIO_BITS
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+ #define configPRIO_BITS         __NVIC_PRIO_BITS
+#else
+ #define configPRIO_BITS         4
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY   15
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* Normal assert() semantics without relying on the provision of an assert.h
+header file. */
+/* USER CODE BEGIN 1 */
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
+/* USER CODE END 1 */
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler    SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+
+/* IMPORTANT: This define is commented when used with STM32Cube firmware, when the timebase source is SysTick,
+              to prevent overwriting SysTick_Handler defined within STM32Cube HAL */
+ 
+#define xPortSysTickHandler SysTick_Handler
+
+/* USER CODE BEGIN Defines */   	      
+/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */
+/* USER CODE END Defines */ 
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Inc/main.h b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Inc/main.h
new file mode 100644
index 000000000..99badb8cb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Inc/main.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Semaphore/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the main.c
+  *          file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..3e4ba1426
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..688ede50d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Inc/stm32wbxx_it.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Semaphore/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void DebugMon_Handler(void);
+void TIM1_TRG_COM_TIM17_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/MDK-ARM/FreeRTOS_Semaphore.uvoptx b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/MDK-ARM/FreeRTOS_Semaphore.uvoptx
new file mode 100644
index 000000000..2e2d5acba
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/MDK-ARM/FreeRTOS_Semaphore.uvoptx
@@ -0,0 +1,649 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    FreeRTOS_Semaphore
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_timebase_tim.c
+      stm32wbxx_hal_timebase_tim.c
+      0
+      0
+    
+    
+      3
+      5
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+    
+      3
+      6
+      1
+      0
+      0
+      0
+      ../Src/app_freertos.c
+      app_freertos.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      7
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      24
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    Middlewares/FreeRTOS
+    0
+    0
+    0
+    0
+    
+      8
+      25
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/croutine.c
+      croutine.c
+      0
+      0
+    
+    
+      8
+      26
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
+      event_groups.c
+      0
+      0
+    
+    
+      8
+      27
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/list.c
+      list.c
+      0
+      0
+    
+    
+      8
+      28
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/queue.c
+      queue.c
+      0
+      0
+    
+    
+      8
+      29
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
+      stream_buffer.c
+      0
+      0
+    
+    
+      8
+      30
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/tasks.c
+      tasks.c
+      0
+      0
+    
+    
+      8
+      31
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/timers.c
+      timers.c
+      0
+      0
+    
+    
+      8
+      32
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c
+      cmsis_os.c
+      0
+      0
+    
+    
+      8
+      33
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
+      heap_4.c
+      0
+      0
+    
+    
+      8
+      34
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
+      port.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/MDK-ARM/FreeRTOS_Semaphore.uvprojx b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/MDK-ARM/FreeRTOS_Semaphore.uvprojx
new file mode 100644
index 000000000..9dbc641a5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/MDK-ARM/FreeRTOS_Semaphore.uvprojx
@@ -0,0 +1,606 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      FreeRTOS_Semaphore
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          FreeRTOS_Semaphore\
+          FreeRTOS_Semaphore
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Middlewares/Third_Party/FreeRTOS/Source/include;../../../../../../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS;../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              ..\Inc
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_timebase_tim.c
+              1
+              ../Src/stm32wbxx_hal_timebase_tim.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+            
+              app_freertos.c
+              1
+              ../Src/app_freertos.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          Middlewares/FreeRTOS
+          
+            
+              croutine.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/croutine.c
+            
+            
+              event_groups.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
+            
+            
+              list.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/list.c
+            
+            
+              queue.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/queue.c
+            
+            
+              stream_buffer.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
+            
+            
+              tasks.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/tasks.c
+            
+            
+              timers.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/timers.c
+            
+            
+              cmsis_os.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c
+            
+            
+              heap_4.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
+            
+            
+              port.c
+              1
+              ../../../../../../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..c1dde4e20
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/.cproject
@@ -0,0 +1,175 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/.project
new file mode 100644
index 000000000..1b24d750d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/.project
@@ -0,0 +1,205 @@
+
+
+	FreeRTOS_Semaphore
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			FreeRTOS_Semaphore.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/FreeRTOS_Semaphore.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/app_freertos.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/app_freertos.c
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_hal_timebase_tim.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_timebase_tim.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Middlewares/FreeRTOS/cmsis_os.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c
+		
+		
+			Middlewares/FreeRTOS/croutine.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/croutine.c
+		
+		
+			Middlewares/FreeRTOS/event_groups.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
+		
+		
+			Middlewares/FreeRTOS/heap_4.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
+		
+		
+			Middlewares/FreeRTOS/list.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/list.c
+		
+		
+			Middlewares/FreeRTOS/port.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
+		
+		
+			Middlewares/FreeRTOS/queue.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/queue.c
+		
+		
+			Middlewares/FreeRTOS/stream_buffer.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
+		
+		
+			Middlewares/FreeRTOS/tasks.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
+		
+		
+			Middlewares/FreeRTOS/timers.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/Third_Party/FreeRTOS/Source/timers.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/app_freertos.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/app_freertos.c
new file mode 100644
index 000000000..adce7d927
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/app_freertos.c
@@ -0,0 +1,62 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Semaphore/Src/freertos.c
+  * @author  MCD Application Team
+  * @brief   Code for freertos applications
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "FreeRTOS.h"
+#include "task.h"
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */     
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN Variables */
+
+/* USER CODE END Variables */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN FunctionPrototypes */
+
+/* USER CODE END FunctionPrototypes */
+
+/* Private application code --------------------------------------------------*/
+/* USER CODE BEGIN Application */
+
+/* USER CODE END Application */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/main.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/main.c
new file mode 100644
index 000000000..b93184007
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/main.c
@@ -0,0 +1,370 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Semaphore/Src/main.c
+  * @author  MCD Application Team
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+#define semtstSTACK_SIZE      configMINIMAL_STACK_SIZE
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+osThreadId SEM_Thread1Handle;
+osThreadId SEM_Thread2Handle;
+osSemaphoreId osSemaphoreHandle;
+/* USER CODE BEGIN PV */
+__IO uint32_t OsStatus = 0;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+void SemaphoreThread1(void const * argument);
+void SemaphoreThread2(void const * argument);
+
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* Initialize LEDs */
+  BSP_LED_Init(LED3);
+  BSP_LED_Init(LED2);
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* USER CODE BEGIN RTOS_MUTEX */
+
+  /* USER CODE END RTOS_MUTEX */
+
+  /* Create the semaphores(s) */
+  /* definition and creation of osSemaphore */
+  osSemaphoreDef(osSemaphore);
+  osSemaphoreHandle = osSemaphoreCreate(osSemaphore(osSemaphore), 1);
+
+  /* USER CODE BEGIN RTOS_SEMAPHORES */
+
+  /* USER CODE END RTOS_SEMAPHORES */
+
+  /* USER CODE BEGIN RTOS_TIMERS */
+
+  /* USER CODE END RTOS_TIMERS */
+
+  /* USER CODE BEGIN RTOS_QUEUES */
+
+  /* USER CODE END RTOS_QUEUES */
+
+  /* Create the thread(s) */
+  /* definition and creation of SEM_Thread1 */
+  osThreadDef(SEM_Thread1, SemaphoreThread1, osPriorityLow, 0, 128);
+  SEM_Thread1Handle = osThreadCreate(osThread(SEM_Thread1), (void *) osSemaphoreHandle);
+
+  /* definition and creation of SEM_Thread2 */
+  osThreadDef(SEM_Thread2, SemaphoreThread2, osPriorityIdle, 0, 128);
+  SEM_Thread2Handle = osThreadCreate(osThread(SEM_Thread2), (void *) osSemaphoreHandle);
+
+  /* USER CODE BEGIN RTOS_THREADS */
+
+  /* USER CODE END RTOS_THREADS */
+
+  /* Start scheduler */
+  osKernelStart();
+ 
+  /* We should never get here as control is now taken by the scheduler */
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/* USER CODE BEGIN Header_SemaphoreThread1 */
+/**
+  * @brief  Function implementing the SEM_Thread1 thread.
+  * @param  argument: Not used
+  * @retval None
+  */
+/* USER CODE END Header_SemaphoreThread1 */
+void SemaphoreThread1(void const * argument)
+{
+  /* USER CODE BEGIN 5 */
+  uint32_t count = 0;
+  osSemaphoreId semaphore = (osSemaphoreId) argument;
+  /* Infinite loop */
+  for (;;)
+  {
+
+    if (semaphore != NULL)
+    {
+    OsStatus = osSemaphoreWait(semaphore , 100);
+      /* Try to obtain the semaphore */
+      if (OsStatus == osOK)
+      {
+        count = osKernelSysTick() + 5000;
+
+        /* Toggle LED3 every 200 ms for 5 seconds */
+        while (count > osKernelSysTick())
+        {
+          /* Toggle LED3 */
+          BSP_LED_Toggle(LED3);
+
+          /* Delay 200 ms */
+          osDelay(200);
+        }
+
+        /* Turn off LED3*/
+        BSP_LED_Off(LED3);
+        /* Release the semaphore */
+        OsStatus = osSemaphoreRelease(semaphore);
+
+        /* Suspend ourseleves to execute thread 2 (lower priority)  */
+        OsStatus = osThreadSuspend(NULL);
+      }
+    }
+  }
+  /* USER CODE END 5 */ 
+}
+
+/* USER CODE BEGIN Header_SemaphoreThread2 */
+/**
+* @brief Function implementing the SEM_Thread2 thread.
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_SemaphoreThread2 */
+void SemaphoreThread2(void const * argument)
+{
+  /* USER CODE BEGIN SemaphoreThread2 */
+  uint32_t count = 0;
+  osSemaphoreId semaphore = (osSemaphoreId) argument;
+  /* Infinite loop */
+  for (;;)
+  {
+    if (semaphore != NULL)
+    {
+      /* Try to obtain the semaphore */
+      if (osSemaphoreWait(semaphore , 0) == osOK)
+      {
+        /* Resume Thread 1 (higher priority)*/
+        OsStatus = osThreadResume(SEM_Thread1Handle);
+
+        count = osKernelSysTick() + 5000;
+
+        /* Toggle LED2 every 200 ms for 5 seconds*/
+        while (count > osKernelSysTick())
+        {
+          BSP_LED_Toggle(LED2);
+
+          osDelay(200);
+        }
+
+        /* Turn off LED2 */
+        BSP_LED_Off(LED2);
+
+        /* Release the semaphore to unblock Thread 1 (higher priority)  */
+        OsStatus = osSemaphoreRelease(semaphore);
+      }
+    }
+  }
+  /* USER CODE END SemaphoreThread2 */
+}
+
+/**
+  * @brief  Period elapsed callback in non blocking mode
+  * @note   This function is called  when TIM17 interrupt took place, inside
+  * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+  * a global variable "uwTick" used as application time base.
+  * @param  htim : TIM handle
+  * @retval None
+  */
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* USER CODE BEGIN Callback 0 */
+
+  /* USER CODE END Callback 0 */
+  if (htim->Instance == TIM17) {
+    HAL_IncTick();
+  }
+  /* USER CODE BEGIN Callback 1 */
+
+  /* USER CODE END Callback 1 */
+}
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {}
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..5585eca36
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,84 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Semaphore/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   This file provides code for the MSP Initialization
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+  /* PendSV_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/stm32wbxx_hal_timebase_tim.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/stm32wbxx_hal_timebase_tim.c
new file mode 100644
index 000000000..717e15eb1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/stm32wbxx_hal_timebase_tim.c
@@ -0,0 +1,136 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_timebase_tim.c
+  * @author  MCD Application Team
+  * @brief   HAL time base based on the hardware TIM.
+  *
+  *          This file overrides the native HAL time base functions (defined as weak)
+  *          the TIM time base:
+  *           + Intializes the TIM peripheral to generate a Period elapsed Event each 1ms
+  *           + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
+  *
+ @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    This file must be copied to the application folder and modified as follows:
+    (#) Rename it to 'stm32g0xx_hal_timebase_tim.c'
+    (#) Add this file and the TIM HAL driver files to your project and make sure
+       HAL_TIM_MODULE_ENABLED is defined in stm32l4xx_hal_conf.h
+
+    [..]
+    (@) The application needs to ensure that the time base is always set to 1 millisecond
+       to have correct HAL operation.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+#include "stm32wbxx_hal_tim.h"
+ 
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+TIM_HandleTypeDef        htim17; 
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  This function configures the TIM17 as a time base source. 
+  *         The time source is configured  to have 1ms time base with a dedicated 
+  *         Tick interrupt priority. 
+  * @note   This function is called  automatically at the beginning of program after
+  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). 
+  * @param  TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  RCC_ClkInitTypeDef    clkconfig;
+  uint32_t              uwTimclock = 0;
+  uint32_t              uwPrescalerValue = 0;
+  uint32_t              pFLatency;
+  
+  /*Configure the TIM17 IRQ priority */
+  HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM17_IRQn, TickPriority ,0); 
+  
+  /* Enable the TIM17 global Interrupt */
+  HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM17_IRQn); 
+  
+  /* Enable TIM17 clock */
+  __HAL_RCC_TIM17_CLK_ENABLE();
+  
+  /* Get clock configuration */
+  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
+  
+  /* Compute TIM17 clock */
+  uwTimclock = HAL_RCC_GetPCLK2Freq();
+   
+  /* Compute the prescaler value to have TIM17 counter clock equal to 1MHz */
+  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1);
+  
+  /* Initialize TIM17 */
+  htim17.Instance = TIM17;
+  
+  /* Initialize TIMx peripheral as follow:
+  + Period = [(TIM17CLK/1000) - 1]. to have a (1/1000) s time base.
+  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+  + ClockDivision = 0
+  + Counter direction = Up
+  */
+  htim17.Init.Period = (1000000 / 1000) - 1;
+  htim17.Init.Prescaler = uwPrescalerValue;
+  htim17.Init.ClockDivision = 0;
+  htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
+  if(HAL_TIM_Base_Init(&htim17) == HAL_OK)
+  {
+    /* Start the TIM time Base generation in interrupt mode */
+    return HAL_TIM_Base_Start_IT(&htim17);
+  }
+  
+  /* Return function status */
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Suspend Tick increment.
+  * @note   Disable the tick increment by disabling TIM17 update interrupt.
+  * @param  None
+  * @retval None
+  */
+void HAL_SuspendTick(void)
+{
+  /* Disable TIM17 update Interrupt */
+  __HAL_TIM_DISABLE_IT(&htim17, TIM_IT_UPDATE);                                                  
+}
+
+/**
+  * @brief  Resume Tick increment.
+  * @note   Enable the tick increment by Enabling TIM17 update interrupt.
+  * @param  None
+  * @retval None
+  */
+void HAL_ResumeTick(void)
+{
+  /* Enable TIM17 Update interrupt */
+  __HAL_TIM_ENABLE_IT(&htim17, TIM_IT_UPDATE);
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..f3216e71f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/stm32wbxx_it.c
@@ -0,0 +1,183 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Semaphore/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+#include "FreeRTOS.h"
+#include "task.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern TIM_HandleTypeDef htim17;
+
+/* USER CODE BEGIN EV */
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt.
+  */
+void TIM1_TRG_COM_TIM17_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */
+
+  /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */
+  HAL_TIM_IRQHandler(&htim17);
+  /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */
+
+  /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/readme.txt b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/readme.txt
new file mode 100644
index 000000000..b92277904
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/FreeRTOS/FreeRTOS_Semaphore/readme.txt
@@ -0,0 +1,87 @@
+/**
+  @page FreeRTOS_Semaphore FreeRTOS Semaphore example
+
+  @verbatim
+  ******************************************************************************
+  * @file    FreeRTOS/FreeRTOS_Semaphore/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the FreeRTOS Semaphore example.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Application Description
+
+How to use semaphores with CMSIS RTOS API.
+
+This application creates two threads that toggle LEDs through a shared semaphore,
+as following:
+
+The first thread which have the higher priority obtains the semaphore and
+toggle the LED3 each 200 ms. After 5 seconds it releases the semaphore and
+suspends itself.
+
+The low priority thread can execute now, it obtains the semaphore and
+resume execution of the first thread, as it has the higher priority
+the first thread will try to obtain the semaphore but it fails because
+the semaphore is already taken by the low priority thread, which will
+toggle the LED2 each 200 ms for 5 seconds before releasing the semaphore
+to begin a new cycle
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate
+      delay (in milliseconds) based on variable incremented in HAL time base ISR.
+      This implies that if HAL_Delay() is called from a peripheral ISR process, then
+      the HAL time base interrupt must have higher priority (numerically lower) than
+      the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the HAL time base interrupt priority you have to use HAL_NVIC_SetPriority()
+      function.
+
+@note The application needs to ensure that the HAL time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@note The FreeRTOS heap size configTOTAL_HEAP_SIZE defined in FreeRTOSConfig.h is set accordingly to the
+      OS resources memory requirements of the application with +10% margin and rounded to the upper Kbyte boundary.
+
+For more details about FreeRTOS implementation on STM32Cube, please refer to UM1722 "Developing Applications
+on STM32Cube with RTOS".
+
+
+@par Directory contents
+    - FreeRTOS/FreeRTOS_Semaphore/Src/main.c                       Main program
+  - FreeRTOS/FreeRTOS_Semaphore/Src/app_FreeRTOS.c               Code for freertos applications
+    - FreeRTOS/FreeRTOS_Semaphore/Src/stm32wbxx_hal_timebase_tim.c HAL timebase file
+    - FreeRTOS/FreeRTOS_Semaphore/Src/stm32wbxx_it.c               Interrupt handlers
+  - FreeRTOS/FreeRTOS_Semaphore/Src/stm32wbxx_hal_msp.c          MSP Initialization file
+    - FreeRTOS/FreeRTOS_Semaphore/Src/system_stm32wbxx.c           STM32WBxx system clock configuration file
+    - FreeRTOS/FreeRTOS_Semaphore/Inc/main.h                       Main program header file
+    - FreeRTOS/FreeRTOS_Semaphore/Inc/stm32wbxx_hal_conf.h         HAL Library Configuration file
+    - FreeRTOS/FreeRTOS_Semaphore/Inc/stm32wbxx_it.h               Interrupt handlers header file
+    - FreeRTOS/FreeRTOS_Semaphore/Inc/FreeRTOSConfig.h             FreeRTOS Configuration file
+
+@par Hardware and Software environment
+
+  - This application runs on STM32WB35CEUx devices.
+
+  - This application has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ?
+
+In order to make the program work, you must do the following:
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/app_common.h b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/app_common.h
new file mode 100644
index 000000000..652b0ef3c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/app_common.h
@@ -0,0 +1,119 @@
+/**
+ ******************************************************************************
+  * File Name          : app_common.h
+  * Description        : App Common application configuration file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_COMMON_H
+#define APP_COMMON_H
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "main.h"
+#include "app_conf.h"
+
+  /* -------------------------------- *
+   *  Basic definitions               *
+   * -------------------------------- */
+
+#undef NULL
+#define NULL                    0
+
+#undef FALSE
+#define FALSE                   0
+
+#undef TRUE
+#define TRUE                    (!0)
+
+  /* -------------------------------- *
+   *  Critical Section definition     *
+   * -------------------------------- */
+#define BACKUP_PRIMASK()    uint32_t primask_bit= __get_PRIMASK()
+#define DISABLE_IRQ()       __disable_irq()
+#define RESTORE_PRIMASK()   __set_PRIMASK(primask_bit)
+
+  /* -------------------------------- *
+   *  Macro delimiters                *
+   * -------------------------------- */
+
+#define M_BEGIN     do {
+
+#define M_END       } while(0)
+
+  /* -------------------------------- *
+   *  Some useful macro definitions   *
+   * -------------------------------- */
+
+#define MAX( x, y )          (((x)>(y))?(x):(y))
+
+#define MIN( x, y )          (((x)<(y))?(x):(y))
+
+#define MODINC( a, m )       M_BEGIN  (a)++;  if ((a)>=(m)) (a)=0;  M_END
+
+#define MODDEC( a, m )       M_BEGIN  if ((a)==0) (a)=(m);  (a)--;  M_END
+
+#define MODADD( a, b, m )    M_BEGIN  (a)+=(b);  if ((a)>=(m)) (a)-=(m);  M_END
+
+#define MODSUB( a, b, m )    MODADD( a, (m)-(b), m )
+
+#define PAUSE( t )           M_BEGIN \
+                               __IO int _i; \
+                               for ( _i = t; _i > 0; _i -- ); \
+                             M_END
+
+#define DIVF( x, y )         ((x)/(y))
+
+#define DIVC( x, y )         (((x)+(y)-1)/(y))
+
+#define DIVR( x, y )         (((x)+((y)/2))/(y))
+
+#define SHRR( x, n )         ((((x)>>((n)-1))+1)>>1)
+
+#define BITN( w, n )         (((w)[(n)/32] >> ((n)%32)) & 1)
+
+#define BITNSET( w, n, b )   M_BEGIN (w)[(n)/32] |= ((U32)(b))<<((n)%32); M_END
+
+#define CRITICAL_BEGIN( )    M_BEGIN BACKUP_PRIMASK(); DISABLE_IRQ()
+
+#define CRITICAL_END( )      RESTORE_PRIMASK(); M_END
+
+  /* -------------------------------- *
+   *  Compiler                         *
+   * -------------------------------- */
+#define PLACE_IN_SECTION( __x__ )  __attribute__((section (__x__)))
+
+#ifdef WIN32
+#define ALIGN(n)
+#else
+#define ALIGN(n)             __attribute__((aligned(n)))
+#endif
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*APP_COMMON_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/app_conf.h b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/app_conf.h
new file mode 100644
index 000000000..5c1df6a1b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/app_conf.h
@@ -0,0 +1,360 @@
+/**
+ ******************************************************************************
+  * File Name          : app_conf.h
+  * Description        : Application configuration file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_CONF_H
+#define APP_CONF_H
+
+#include "hw_conf.h"
+#include "hw_if.h"
+#include "hw.h"
+
+/******************************************************************************
+ * Application Config
+ ******************************************************************************/
+
+/******************************************************************************
+ * Transport Layer
+ ******************************************************************************/
+/**
+ * Queue length of BLE Event
+ * This parameter defines the number of asynchronous events that can be stored in the HCI layer before
+ * being reported to the application. When a command is sent to the BLE core coprocessor, the HCI layer
+ * is waiting for the event with the Num_HCI_Command_Packets set to 1. The receive queue shall be large
+ * enough to store all asynchronous events received in between.
+ * When CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE is set to 27, this allow to store three 255 bytes long asynchronous events
+ * between the HCI command and its event.
+ * This parameter depends on the value given to CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE. When the queue size is to small,
+ * the system may hang if the queue is full with asynchronous events and the HCI layer is still waiting
+ * for a CC/CS event, In that case, the notification TL_BLE_HCI_ToNot() is called to indicate
+ * to the application a HCI command did not receive its command event within 30s (Default HCI Timeout).
+ */
+#define CFG_TL_EVT_QUEUE_LENGTH 5
+/**
+ * This parameter should be set to fit most events received by the HCI layer. It defines the buffer size of each element
+ * allocated in the queue of received events and can be used to optimize the amount of RAM allocated by the Memory Manager.
+ * It should not exceed 255 which is the maximum HCI packet payload size (a greater value is a lost of memory as it will
+ * never be used)
+ * It shall be at least 4 to receive the command status event in one frame.
+ * The default value is set to 27 to allow receiving an event of MTU size in a single buffer. This value maybe reduced
+ * further depending on the application.
+ *
+ */
+/**< Set to 255 with the memory manager and the mailbox */
+#define CFG_TL_MOST_EVENT_PAYLOAD_SIZE 255
+
+#define TL_EVENT_FRAME_SIZE ( TL_EVT_HDR_SIZE + CFG_TL_MOST_EVENT_PAYLOAD_SIZE )
+
+/******************************************************************************
+ * UART interfaces
+ ******************************************************************************/
+/**
+ * Select UART interfaces
+ */
+#define CFG_DEBUG_TRACE_UART    hw_lpuart1
+#define CFG_CONSOLE_MENU      
+#define CFG_CLI_UART    hw_uart1
+
+/******************************************************************************
+ * USB interface
+ ******************************************************************************/
+
+/**
+ * Enable/Disable USB interface
+ */
+#define CFG_USB_INTERFACE_ENABLE    0
+
+/******************************************************************************
+ * Low Power
+ *
+ *  When CFG_FULL_LOW_POWER is set to 1, the system is configured in full
+ *  low power mode. It means that all what can have an impact on the consumptions
+ *  are powered down.(For instance LED, Access to Debugger, Etc.)
+ *
+ *  When CFG_FULL_LOW_POWER is set to 0, the low power mode is not activated
+ *
+ ******************************************************************************/
+
+#define CFG_FULL_LOW_POWER    0
+
+#if (CFG_FULL_LOW_POWER == 1)
+#undef CFG_LPM_SUPPORTED
+#define CFG_LPM_SUPPORTED   1
+#endif /* CFG_FULL_LOW_POWER */
+
+/******************************************************************************
+ * Timer Server
+ ******************************************************************************/
+/**
+ *  CFG_RTC_WUCKSEL_DIVIDER:  This sets the RTCCLK divider to the wakeup timer.
+ *  The higher is the value, the better is the power consumption and the accuracy of the timerserver
+ *  The lower is the value, the finest is the granularity
+ *
+ *  CFG_RTC_ASYNCH_PRESCALER: This sets the asynchronous prescaler of the RTC. It should as high as possible ( to ouput
+ *  clock as low as possible) but the output clock should be equal or higher frequency compare to the clock feeding
+ *  the wakeup timer. A lower clock speed would impact the accuracy of the timer server.
+ *
+ *  CFG_RTC_SYNCH_PRESCALER: This sets the synchronous prescaler of the RTC.
+ *  When the 1Hz calendar clock is required, it shall be sets according to other settings
+ *  When the 1Hz calendar clock is not needed, CFG_RTC_SYNCH_PRESCALER should be set to 0x7FFF (MAX VALUE)
+ *
+ *  CFG_RTCCLK_DIVIDER_CONF:
+ *  Shall be set to either 0,2,4,8,16
+ *  When set to either 2,4,8,16, the 1Hhz calendar is supported
+ *  When set to 0, the user sets its own configuration
+ *
+ *  The following settings are computed with LSI as input to the RTC
+ */
+#define CFG_RTCCLK_DIVIDER_CONF 0
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 0)
+/**
+ * Custom configuration
+ * It does not support 1Hz calendar
+ * It divides the RTC CLK by 16
+ */
+#define CFG_RTCCLK_DIV  (16)
+#define CFG_RTC_WUCKSEL_DIVIDER (0)
+#define CFG_RTC_ASYNCH_PRESCALER (CFG_RTCCLK_DIV - 1)
+#define CFG_RTC_SYNCH_PRESCALER (0x7FFF)
+
+#else
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 2)
+/**
+ * It divides the RTC CLK by 2
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (3)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 4)
+/**
+ * It divides the RTC CLK by 4
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (2)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 8)
+/**
+ * It divides the RTC CLK by 8
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (1)
+#endif
+
+#if (CFG_RTCCLK_DIVIDER_CONF == 16)
+/**
+ * It divides the RTC CLK by 16
+ */
+#define CFG_RTC_WUCKSEL_DIVIDER (0)
+#endif
+
+#define CFG_RTCCLK_DIV              CFG_RTCCLK_DIVIDER_CONF
+#define CFG_RTC_ASYNCH_PRESCALER    (CFG_RTCCLK_DIV - 1)
+#define CFG_RTC_SYNCH_PRESCALER     (DIVR( LSE_VALUE, (CFG_RTC_ASYNCH_PRESCALER+1) ) - 1 )
+
+#endif
+
+/** tick timer value in us */
+#define CFG_TS_TICK_VAL           DIVR( (CFG_RTCCLK_DIV * 1000000), LSE_VALUE )
+
+typedef enum
+{
+  CFG_TIM_PROC_ID_ISR,
+} CFG_TimProcID_t;
+
+/******************************************************************************
+ * Debug
+ ******************************************************************************/
+/**
+ * When set, this resets some hw resources to set the device in the same state than the power up
+ * The FW resets only register that may prevent the FW to run properly
+ *
+ * This shall be set to 0 in a final product
+ *
+ */
+#define CFG_HW_RESET_BY_FW         1
+
+/**
+ * keep debugger enabled while in any low power mode when set to 1
+ * should be set to 0 in production
+ */
+#define CFG_DEBUGGER_SUPPORTED    1
+
+#if (CFG_FULL_LOW_POWER == 1)
+#undef CFG_DEBUGGER_SUPPORTED
+#define CFG_DEBUGGER_SUPPORTED    0
+#endif /* CFG_FULL_LOW_POWER */
+
+/*****************************************************************************
+ * Traces
+ * Enable or Disable traces in application
+ * When CFG_DEBUG_TRACE is set, traces are activated
+ *
+ * Note : Refer to utilities_conf.h file in order to details
+ *        the level of traces : CFG_DEBUG_TRACE_FULL or CFG_DEBUG_TRACE_LIGHT
+ *****************************************************************************/
+#define CFG_DEBUG_TRACE    1
+
+#if (CFG_FULL_LOW_POWER == 1)
+#undef CFG_DEBUG_TRACE
+#define CFG_DEBUG_TRACE      0
+#endif /* CFG_FULL_LOW_POWER */
+
+/**
+ * When CFG_DEBUG_TRACE_FULL is set to 1, the trace are output with the API name, the file name and the line number
+ * When CFG_DEBUG_TRACE_LIGHT is set to 1, only the debug message is output
+ *
+ * When both are set to 0, no trace are output
+ * When both are set to 1,  CFG_DEBUG_TRACE_FULL is selected
+ */
+#define CFG_DEBUG_TRACE_LIGHT     1
+#define CFG_DEBUG_TRACE_FULL      0
+
+#if (( CFG_DEBUG_TRACE != 0 ) && ( CFG_DEBUG_TRACE_LIGHT == 0 ) && (CFG_DEBUG_TRACE_FULL == 0))
+#undef CFG_DEBUG_TRACE_FULL
+#undef CFG_DEBUG_TRACE_LIGHT
+#define CFG_DEBUG_TRACE_FULL      0
+#define CFG_DEBUG_TRACE_LIGHT     1
+#endif
+
+#if ( CFG_DEBUG_TRACE == 0 )
+#undef CFG_DEBUG_TRACE_FULL
+#undef CFG_DEBUG_TRACE_LIGHT
+#define CFG_DEBUG_TRACE_FULL      0
+#define CFG_DEBUG_TRACE_LIGHT     0
+#endif
+
+/**
+ * When not set, the traces is looping on sending the trace over UART
+ */
+#define DBG_TRACE_USE_CIRCULAR_QUEUE 1
+
+/**
+ * max buffer Size to queue data traces and max data trace allowed.
+ * Only Used if DBG_TRACE_USE_CIRCULAR_QUEUE is defined
+ */
+#define DBG_TRACE_MSG_QUEUE_SIZE 4096
+#define MAX_DBG_TRACE_MSG_SIZE 1024
+
+/******************************************************************************
+ * Configure Log level for Application
+ ******************************************************************************/
+#define APPLI_CONFIG_LOG_LEVEL    LOG_LEVEL_INFO
+#define APPLI_PRINT_FILE_FUNC_LINE    0
+
+/* USER CODE BEGIN Defines */
+/******************************************************************************
+ * User interaction
+ * When CFG_LED_SUPPORTED is set, LEDS are activated if requested
+ * When CFG_BUTTON_SUPPORTED is set, the push button are activated if requested
+ ******************************************************************************/
+#if (CFG_FULL_LOW_POWER == 1)
+#define CFG_LED_SUPPORTED         0
+#define CFG_BUTTON_SUPPORTED      0
+#else
+#define CFG_LED_SUPPORTED         1
+#define CFG_BUTTON_SUPPORTED      1
+#endif /* CFG_FULL_LOW_POWER */
+/* USER CODE END Defines */
+
+/******************************************************************************
+ * Scheduler
+ ******************************************************************************/
+  /**
+   * This is the list of task id required by the application
+   * Each Id shall be in the range 0..31
+   */
+
+typedef enum
+{
+  CFG_TASK_MSG_FROM_M0_TO_M4,
+  CFG_TASK_SEND_CLI_TO_M0,
+  CFG_TASK_SYSTEM_HCI_ASYNCH_EVT,
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+  CFG_TASK_VCP_SEND_DATA,
+#endif /* (CFG_USB_INTERFACE_ENABLE != 0) */
+  /* USER CODE BEGIN CFG_IdleTask_Id_t */
+
+  /* USER CODE END CFG_IdleTask_Id_t */
+  CFG_TASK_NBR  /**< Shall be last in the list */
+} CFG_IdleTask_Id_t;
+
+/* Scheduler types and defines        */
+/*------------------------------------*/
+#define TASK_MSG_FROM_M0_TO_M4      (1U << CFG_TASK_MSG_FROM_M0_TO_M4)
+/* USER CODE BEGIN DEFINE_TASK */ 
+
+/* USER CODE END DEFINE_TASK */  
+ 
+/**
+ * This is the list of priority required by the application
+ * Each Id shall be in the range 0..31
+ */
+typedef enum
+{
+    CFG_SCH_PRIO_0,
+    CFG_SCH_PRIO_1,
+    CFG_PRIO_NBR,
+} CFG_SCH_Prio_Id_t;
+
+/**
+ * This is a bit mapping over 32bits listing all events id supported in the application
+ */
+typedef enum
+{
+  CFG_EVT_SYSTEM_HCI_CMD_EVT_RESP,
+  CFG_EVT_ACK_FROM_M0_EVT,
+  CFG_EVT_SYNCHRO_BYPASS_IDLE,
+  /* USER CODE BEGIN CFG_IdleEvt_Id_t */
+
+  /* USER CODE END CFG_IdleEvt_Id_t */
+} CFG_IdleEvt_Id_t;
+
+#define EVENT_ACK_FROM_M0_EVT           (1U << CFG_EVT_ACK_FROM_M0_EVT)
+#define EVENT_SYNCHRO_BYPASS_IDLE       (1U << CFG_EVT_SYNCHRO_BYPASS_IDLE)
+/* USER CODE BEGIN DEFINE_EVENT */
+
+/* USER CODE END DEFINE_EVENT */
+
+/******************************************************************************
+ * LOW POWER
+ ******************************************************************************/
+/**
+ * Supported requester to the MCU Low Power Manager - can be increased up  to 32
+ * It lits a bit mapping of all user of the Low Power Manager
+ */
+typedef enum
+{
+    CFG_LPM_APP,
+    CFG_LPM_APP_THREAD,
+  /* USER CODE BEGIN CFG_LPM_Id_t */
+
+  /* USER CODE END CFG_LPM_Id_t */
+} CFG_LPM_Id_t;
+
+/******************************************************************************
+ * OTP manager
+ ******************************************************************************/
+#define CFG_OTP_BASE_ADDRESS    OTP_AREA_BASE
+
+#define CFG_OTP_END_ADRESS      OTP_AREA_END_ADDR
+
+#endif /*APP_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/app_entry.h b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/app_entry.h
new file mode 100644
index 000000000..77ead2384
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/app_entry.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    app_entry.h
+  * @author  MCD Application Team
+  * @brief   Interface to the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_ENTRY_H
+#define APP_ENTRY_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APPE_Init( void );
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*APP_ENTRY_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/hw_conf.h b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/hw_conf.h
new file mode 100644
index 000000000..2bd221120
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/hw_conf.h
@@ -0,0 +1,143 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : hw_conf.h
+  * Description        : Hardware configuration file for the application.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef HW_CONF_H
+#define HW_CONF_H
+
+/******************************************************************************
+* Semaphores
+* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
+*****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
+/* Index of the semaphore used to manage the entry Stop Mode procedure */
+#define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
+
+/* Index of the semaphore used to access the RCC */
+#define CFG_HW_RCC_SEMID                                        3
+
+/* Index of the semaphore used to access the FLASH */
+#define CFG_HW_FLASH_SEMID                                      2
+
+/* Index of the semaphore used to access the PKA */
+#define CFG_HW_PKA_SEMID                                        1
+
+/* Index of the semaphore used to access the RNG */
+#define CFG_HW_RNG_SEMID                                        0
+
+/******************************************************************************
+ * HW TIMER SERVER
+ *****************************************************************************/
+/**
+ * The user may define the maximum number of virtual timers supported.
+ * It shall not exceed 255
+ */
+#define CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER  6
+
+/**
+ * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
+ * wakeup timer.
+ * This setting is the preemptpriority part of the NVIC.
+ */
+#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO  3
+
+/**
+ * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
+ * wakeup timer.
+ * This setting is the subpriority part of the NVIC. It does not exist on all processors. When it is not supported
+ * on the CPU, the setting is ignored
+ */
+#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO  0
+
+/**
+ *  Define a critical section in the Timer server
+ *  The Timer server does not support the API to be nested
+ *  The  Application shall either:
+ *    a) Ensure this will never happen
+ *    b) Define the critical section
+ *  The default implementations is masking all interrupts using the PRIMASK bit
+ *  The TimerServer driver uses critical sections to avoid context corruption. This is achieved with the macro
+ *  TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION. When CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION is set
+ *  to 1, all STM32 interrupts are masked with the PRIMASK bit of the CortexM CPU. It is possible to use the BASEPRI
+ *  register of the CortexM CPU to keep allowed some interrupts with high priority. In that case, the user shall
+ *  re-implement TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION and shall make sure that no TimerServer
+ *  API are called when the TIMER critical section is entered
+ */
+#define CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION  1
+
+/**
+   * This value shall reflect the maximum delay there could be in the application between the time the RTC interrupt
+   * is generated by the Hardware and the time when the  RTC interrupt handler is called. This time is measured in
+   * number of RTCCLK ticks.
+   * A relaxed timing would be 10ms
+   * When the value is too short, the timerserver will not be able to count properly and all timeout may be random.
+   * When the value is too long, the device may wake up more often than the most optimal configuration. However, the
+   * impact on power consumption would be marginal (unless the value selected is extremely too long). It is strongly
+   * recommended to select a value large enough to make sure it is not too short to ensure reliability of the system
+   * as this will have marginal impact on low power mode
+   */
+#define CFG_HW_TS_RTC_HANDLER_MAX_DELAY  ( 10 * (LSI_VALUE/1000) )
+
+  /**
+   * Interrupt ID in the NVIC of the RTC Wakeup interrupt handler
+   * It shall be type of IRQn_Type
+   */
+#define CFG_HW_TS_RTC_WAKEUP_HANDLER_ID  RTC_WKUP_IRQn
+
+/******************************************************************************
+ * HW UART
+ *****************************************************************************/
+
+#define CFG_HW_LPUART1_ENABLED           1
+#define CFG_HW_LPUART1_DMA_TX_SUPPORTED  1
+
+#define CFG_HW_USART1_ENABLED           1
+#define CFG_HW_USART1_DMA_TX_SUPPORTED  1
+
+#endif /*HW_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/hw_if.h b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/hw_if.h
new file mode 100644
index 000000000..8b139aee8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/hw_if.h
@@ -0,0 +1,274 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    hw_if.h
+  * @author  MCD Application Team
+  * @brief   Hardware Interface
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef HW_IF_H
+#define HW_IF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_ipcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_hsem.h"
+#include "stm32wbxx_ll_gpio.h"
+#include "stm32wbxx_ll_rtc.h"
+
+#ifdef  USE_STM32WBXX_USB_DONGLE
+#include "stm32wbxx_usb_dongle.h"
+#endif
+#ifdef  USE_STM32WBXX_NUCLEO
+#ifdef STM32WB35xx
+#include "nucleo_wb35ce.h"
+#else
+#include "stm32wbxx_nucleo.h"
+#endif
+#endif
+#ifdef  USE_X_NUCLEO_EPD
+#include "x_nucleo_epd.h"
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/******************************************************************************
+ * HW UART
+ ******************************************************************************/
+typedef enum
+{
+  hw_uart1,
+  hw_uart2,
+  hw_lpuart1,
+} hw_uart_id_t;
+
+typedef enum
+{
+  hw_uart_ok,
+  hw_uart_error,
+  hw_uart_busy,
+  hw_uart_to,
+} hw_status_t;
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+extern UART_HandleTypeDef hlpuart1;
+extern DMA_HandleTypeDef hdma_lpuart1_tx;
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+extern UART_HandleTypeDef huart1;
+extern DMA_HandleTypeDef hdma_usart1_tx;
+#endif
+
+//void HW_UART_Init(hw_uart_id_t hw_uart_id);
+hw_status_t HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *pData, uint16_t Size, void (*Callback)(void));
+hw_status_t HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *pData, uint16_t Size,  void (*Callback)(void));
+hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout);
+hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*Callback)(void));
+#if 0
+void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id);
+void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id);
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+void MX_LPUART1_UART_Init(void);
+void MX_LPUART1_UART_DeInit(void);
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+void MX_USART1_UART_Init(void);
+void MX_USART1_UART_DeInit(void);
+#endif
+
+  /******************************************************************************
+   * HW TimerServer
+   ******************************************************************************/
+  /* Exported types ------------------------------------------------------------*/
+  /**
+   * This setting is used when standby mode is supported.
+   * hw_ts_InitMode_Limited should be used when the device restarts from Standby Mode. In that case, the Timer Server does
+   * not re-initialized its context. Only the Hardware register which content has been lost is reconfigured
+   * Otherwise, hw_ts_InitMode_Full should be requested (Start from Power ON) and everything is re-initialized.
+   */
+  typedef enum
+  {
+    hw_ts_InitMode_Full,
+    hw_ts_InitMode_Limited,
+  } HW_TS_InitMode_t;
+
+  /**
+   * When a Timer is created as a SingleShot timer, it is not automatically restarted when the timeout occurs. However,
+   * the timer is kept reserved in the list and could be restarted at anytime with HW_TS_Start()
+   *
+   * When a Timer is created as a Repeated timer, it is automatically restarted when the timeout occurs.
+   */
+  typedef enum
+  {
+    hw_ts_SingleShot,
+    hw_ts_Repeated
+  } HW_TS_Mode_t;
+
+  /**
+   * hw_ts_Successful is returned when a Timer has been successfully created with HW_TS_Create(). Otherwise, hw_ts_Failed
+   * is returned. When hw_ts_Failed is returned, that means there are not enough free slots in the list to create a
+   * Timer. In that case, CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER should be increased
+   */
+  typedef enum
+  {
+    hw_ts_Successful,
+    hw_ts_Failed,
+  }HW_TS_ReturnStatus_t;
+
+  typedef void (*HW_TS_pTimerCb_t)(void);
+
+  /**
+   * @brief  Initialize the timer server
+   *         This API shall be called by the application before any timer is requested to the timer server. It
+   *         configures the RTC module to be connected to the LSI input clock.
+   *
+   * @param  TimerInitMode: When the device restarts from Standby, it should request hw_ts_InitMode_Limited so that the
+   *         Timer context is not re-initialized. Otherwise, hw_ts_InitMode_Full should be requested
+   * @param  hrtc: RTC Handle
+   * @retval None
+   */
+  void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *hrtc);
+
+  /**
+   * @brief  Interface to create a virtual timer
+   *         The user shall call this API to create a timer. Once created, the timer is reserved to the module until it
+   *         has been deleted. When creating a timer, the user shall specify the mode (single shot or repeated), the
+   *         callback to be notified when the timer expires and a module ID to identify in the timer interrupt handler
+   *         which module is concerned. In return, the user gets a timer ID to handle it.
+   *
+   * @param  TimerProcessID:  This is an identifier provided by the user and returned in the callback to allow
+   *                          identification of the requester
+   * @param  pTimerId: Timer Id returned to the user to request operation (start, stop, delete)
+   * @param  TimerMode: Mode of the virtual timer (Single shot or repeated)
+   * @param  pTimerCallBack: Callback when the virtual timer expires
+   * @retval HW_TS_ReturnStatus_t: Return whether the creation is sucessfull or not
+   */
+  HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pTimerCallBack);
+
+  /**
+   * @brief  Stop a virtual timer
+   *         This API may be used to stop a running timer. A timer which is stopped is move to the pending state.
+   *         A pending timer may be restarted at any time with a different timeout value but the mode cannot be changed.
+   *         Nothing is done when it is called to stop a timer which has been already stopped
+   *
+   * @param  TimerID:  Id of the timer to stop
+   * @retval None
+   */
+  void HW_TS_Stop(uint8_t TimerID);
+
+  /**
+   * @brief  Start a virtual timer
+   *         This API shall be used to start a timer. The timeout value is specified and may be different each time.
+   *         When the timer is in the single shot mode, it will move to the pending state when it expires. The user may
+   *         restart it at any time with a different timeout value. When the timer is in the repeated mode, it always
+   *         stay in the running state. When the timer expires, it will be restarted with the same timeout value.
+   *         This API shall not be called on a running timer.
+   *
+   * @param  TimerID:  The ID Id of the timer to start
+   * @param  timeout_ticks: Number of ticks of the virtual timer (Maximum value is (0xFFFFFFFF-0xFFFF = 0xFFFF0000)
+   * @retval None
+   */
+  void HW_TS_Start(uint8_t TimerID, uint32_t timeout_ticks);
+
+  /**
+   * @brief  Delete a virtual timer from the list
+   *         This API should be used when a timer is not needed anymore by the user. A deleted timer is removed from
+   *         the timer list managed by the timer server. It cannot be restarted again. The user has to go with the
+   *         creation of a new timer if required and may get a different timer id
+   *
+   * @param  TimerID:  The ID of the timer to remove from the list
+   * @retval None
+   */
+  void HW_TS_Delete(uint8_t TimerID);
+
+  /**
+   * @brief  Schedule the timer list on the timer interrupt handler
+   *         This interrupt handler shall be called by the application in the RTC interrupt handler. This handler takes
+   *         care of clearing all status flag required in the RTC and EXTI peripherals
+   *
+   * @param  None
+   * @retval None
+   */
+  void HW_TS_RTC_Wakeup_Handler(void);
+
+  /**
+   * @brief  Return the number of ticks to count before the interrupt
+   *         This API returns the number of ticks left to be counted before an interrupt is generated by the
+   *         Timer Server. This API may be used by the application for power management optimization. When the system
+   *         enters low power mode, the mode selection is a tradeoff between the wakeup time where the CPU is running
+   *         and the time while the CPU will be kept in low power mode before next wakeup. The deeper is the
+   *         low power mode used, the longer is the wakeup time. The low power mode management considering wakeup time
+   *         versus time in low power mode is implementation specific
+   *         When the timer is disabled (No timer in the list), it returns 0xFFFF
+   *
+   * @param  None
+   * @retval The number of ticks left to count
+   */
+  uint16_t HW_TS_RTC_ReadLeftTicksToCount(void);
+
+  /**
+   * @brief  Notify the application that a registered timer has expired
+   *         This API shall be implemented by the user application.
+   *         This API notifies the application that a timer expires. This API is running in the RTC Wakeup interrupt
+   *         context. The application may implement an Operating System to change the context priority where the timer
+   *         callback may be handled. This API provides the module ID to identify which module is concerned and to allow
+   *         sending the information to the correct task
+   *
+   * @param  TimerProcessID: The TimerProcessId associated with the timer when it has been created
+   * @param  TimerID: The TimerID of the expired timer
+   * @param  pTimerCallBack: The Callback associated with the timer when it has been created
+   * @retval None
+   */
+  void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack);
+
+  /**
+   * @brief  Notify the application that the wakeupcounter has been updated
+   *         This API should be implemented by the user application
+   *         This API notifies the application that the counter has been updated. This is expected to be used along
+   *         with the HW_TS_RTC_ReadLeftTicksToCount () API. It could be that the counter has been updated since the
+   *         last call of HW_TS_RTC_ReadLeftTicksToCount () and before entering low power mode. This notification
+   *         provides a way to the application to solve that race condition to reevaluate the counter value before
+   *         entering low power mode
+   *
+   * @param  None
+   * @retval None
+   */
+  void HW_TS_RTC_CountUpdated_AppNot(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*HW_IF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/main.h b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/main.h
new file mode 100644
index 000000000..27baf67b1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+void SystemClock_Config(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/stm32_lpm_if.h b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/stm32_lpm_if.h
new file mode 100644
index 000000000..aeb10fa95
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/stm32_lpm_if.h
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    stm32_lpm_if.h
+ * @brief   Header for stm32_lpm_if.c module (device specific LP management)
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics. 
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the 
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_LPM_IF_H
+#define __STM32_LPM_IF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/**
+  * @brief Enters Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_EnterOffMode( void );
+/**
+  * @brief Exits Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_ExitOffMode( void );
+
+/**
+  * @brief Enters Low Power Stop Mode
+  * @note ARM exists the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterStopMode( void );
+/**
+  * @brief Exits Low Power Stop Mode
+  * @note Enable the pll at 32MHz
+  * @param none
+  * @retval none
+  */
+void PWR_ExitStopMode( void );
+
+/**
+  * @brief Enters Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterSleepMode( void );
+
+/**
+  * @brief Exits Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_ExitSleepMode( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32_LPM_IF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..4c3dc80b8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,353 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32WBxx_HAL_CONF_H
+#define STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+#define HAL_CORTEX_MODULE_ENABLED
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+#define HAL_PWR_MODULE_ENABLED
+/*#define HAL_QSPI_MODULE_ENABLED   */
+#define HAL_RCC_MODULE_ENABLED
+/*#define HAL_RNG_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100UL)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  (32000UL)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  (32000UL)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    (48000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    (5000UL)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    (48000UL) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    (3300UL) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority (lowest by default) */
+#define  USE_RTOS                     0
+#define  PREFETCH_ENABLE              1
+#define  INSTRUCTION_CACHE_ENABLE     1
+#define  DATA_CACHE_ENABLE            1
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1 */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..9cf479c9d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/stm32wbxx_it.h
@@ -0,0 +1,89 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "app_common.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void PVD_PVM_IRQHandler(void);
+void FLASH_IRQHandler(void);
+void RCC_IRQHandler(void);
+#ifdef STM32WB35xx
+void DMA1_Channel4_IRQHandler(void);
+void DMA2_Channel4_IRQHandler(void);
+#else
+void DMA1_Channel1_IRQHandler(void);
+void DMA1_Channel2_IRQHandler(void);
+#endif
+void C2SEV_PWR_C2H_IRQHandler(void);
+void USART1_IRQHandler(void);
+void LPUART1_IRQHandler(void);
+void PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler(void);
+void HSEM_IRQHandler(void);
+void FPU_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+void RTC_WKUP_IRQHandler(void);
+void IPCC_C1_TX_IRQHandler(void);
+void IPCC_C1_RX_IRQHandler(void);
+void EXTI4_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/stm_logging.h b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/stm_logging.h
new file mode 100644
index 000000000..38e2cf788
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/stm_logging.h
@@ -0,0 +1,63 @@
+/**
+ ******************************************************************************
+  * File Name          : stm_logging.h
+  * Description        : Application header file for logging
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+#ifndef STM_LOGGING_H_
+#define STM_LOGGING_H_
+
+#define LOG_LEVEL_NONE  0  /* None     */
+#define LOG_LEVEL_CRIT  1U  /* Critical */
+#define LOG_LEVEL_WARN  2U  /* Warning  */
+#define LOG_LEVEL_INFO  3U  /* Info     */
+#define LOG_LEVEL_DEBG  4U  /* Debug    */
+
+#define APP_DBG_FULL(level, region, ...)                                                      \
+    {                                                                                         \
+      if (APPLI_PRINT_FILE_FUNC_LINE == 1U)                                                   \
+      {                                                                                       \
+        printf("\r\n[%s][%s][%d] ", DbgTraceGetFileName(__FILE__),__FUNCTION__,__LINE__);     \
+      }                                                                                       \
+      logApplication(level, region, __VA_ARGS__);                                             \
+    }
+
+#define APP_DBG(...)                                                                          \
+    {                                                                                         \
+    if (APPLI_PRINT_FILE_FUNC_LINE == 1U)                                                     \
+    {                                                                                         \
+        printf("\r\n[%s][%s][%d] ", DbgTraceGetFileName(__FILE__),__FUNCTION__,__LINE__);     \
+    }                                                                                         \
+    logApplication(LOG_LEVEL_NONE, APPLI_LOG_REGION_GENERAL, __VA_ARGS__);                    \
+    }
+
+/**
+ * This enumeration represents log regions.
+ *
+ */
+typedef enum 
+{
+  APPLI_LOG_REGION_GENERAL                    = 1U,  /* General                 */
+  APPLI_LOG_REGION_OPENTHREAD_API             = 2U,  /* OpenThread API          */
+  APPLI_LOG_REGION_OT_API_LINK                = 3U,  /* OpenThread Link API     */
+  APPLI_LOG_REGION_OT_API_INSTANCE            = 4U,  /* OpenThread Instance API */
+  APPLI_LOG_REGION_OT_API_MESSAGE             = 5U   /* OpenThread Message API  */
+} appliLogRegion_t;
+
+typedef uint8_t appliLogLevel_t;
+
+void logApplication(appliLogLevel_t aLogLevel, appliLogRegion_t aLogRegion, const char *aFormat, ...);
+
+#endif  /* STM_LOGGING_H_ */
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/utilities_conf.h b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/utilities_conf.h
new file mode 100644
index 000000000..e01b32e59
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Inc/utilities_conf.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    utilities_conf.h
+ * @author  MCD Application Team
+ * @brief   Configuration file to utilities
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef UTILITIES_CONF_H
+#define UTILITIES_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "cmsis_compiler.h"
+#include "string.h"
+
+/******************************************************************************
+ * common
+ ******************************************************************************/
+#define UTILS_ENTER_CRITICAL_SECTION( )   uint32_t primask_bit = __get_PRIMASK( );\
+                                          __disable_irq( )
+
+#define UTILS_EXIT_CRITICAL_SECTION( )          __set_PRIMASK( primask_bit )
+
+#define UTILS_MEMSET8( dest, value, size )      memset( dest, value, size);
+
+/******************************************************************************
+ * tiny low power manager
+ * (any macro that does not need to be modified can be removed)
+ ******************************************************************************/
+#define UTIL_LPM_INIT_CRITICAL_SECTION( )
+#define UTIL_LPM_ENTER_CRITICAL_SECTION( )      UTILS_ENTER_CRITICAL_SECTION( )
+#define UTIL_LPM_EXIT_CRITICAL_SECTION( )       UTILS_EXIT_CRITICAL_SECTION( )
+
+/******************************************************************************
+ * sequencer
+ * (any macro that does not need to be modified can be removed)
+ ******************************************************************************/
+#define UTIL_SEQ_INIT_CRITICAL_SECTION( )
+#define UTIL_SEQ_ENTER_CRITICAL_SECTION( )      UTILS_ENTER_CRITICAL_SECTION( )
+#define UTIL_SEQ_EXIT_CRITICAL_SECTION( )       UTILS_EXIT_CRITICAL_SECTION( )
+#define UTIL_SEQ_CONF_TASK_NBR                  (32)
+#define UTIL_SEQ_CONF_PRIO_NBR                  (2)
+#define UTIL_SEQ_MEMSET8( dest, value, size )   UTILS_MEMSET8( dest, value, size )
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*UTILITIES_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/app_entry.c b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/app_entry.c
new file mode 100644
index 000000000..a6370ec50
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/app_entry.c
@@ -0,0 +1,450 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    app_entry.c
+ * @author  MCD Application Team
+ * @brief   Entry point of the Application
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "app_entry.h"
+#include "app_thread.h"
+#include "app_conf.h"
+#include "hw_conf.h"
+#include "stm32_seq.h"
+#include "stm_logging.h"
+#include "shci_tl.h"
+#include "stm32_lpm.h"
+#include "dbg_trace.h"
+#include "shci.h"
+
+/* Private includes -----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+extern RTC_HandleTypeDef hrtc;
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+/* POOL_SIZE = 2(TL_PacketHeader_t) + 258 (3(TL_EVT_HDR_SIZE) + 255(Payload size)) */
+#define POOL_SIZE (CFG_TL_EVT_QUEUE_LENGTH * 4U * DIVC(( sizeof(TL_PacketHeader_t) + TL_EVENT_FRAME_SIZE ), 4U))
+
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t EvtPool[POOL_SIZE];
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static TL_CmdPacket_t SystemCmdBuffer;
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t SystemSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255U];
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Global function prototypes -----------------------------------------------*/
+#if(CFG_DEBUG_TRACE != 0)
+size_t DbgTraceWrite(int handle, const unsigned char * buf, size_t bufSize);
+#endif
+
+/* USER CODE BEGIN GFP */
+
+/* USER CODE END GFP */
+
+/* Private functions prototypes-----------------------------------------------*/
+static void SystemPower_Config( void );
+static void Init_Debug( void );
+static void appe_Tl_Init( void );
+static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status );
+static void APPE_SysUserEvtRx( void * pPayload );
+static void APPE_SysEvtReadyProcessing( void );
+static void APPE_SysEvtError( SCHI_SystemErrCode_t ErrorCode);
+
+/* USER CODE BEGIN PFP */
+static void Led_Init( void );
+static void Button_Init( void );
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APPE_Init( void )
+{
+  /**< Configure the system Power Mode */
+  SystemPower_Config();
+  
+  HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
+  
+/* USER CODE BEGIN APPE_Init_1 */
+  /* initialize debugger module if supported and debug trace if activated */
+  Init_Debug();
+  
+  /**
+   * The Standby mode should not be entered before the initialization is over
+   * The default state of the Low Power Manager is to allow the Standby Mode so an request is needed here
+   */
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP, UTIL_LPM_DISABLE);
+  
+  Led_Init();
+  Button_Init();
+  
+/* USER CODE END APPE_Init_1 */
+  /* Initialize all transport layers and start CPU2 which will send back a ready event to CPU1 */
+  appe_Tl_Init();
+  
+  /**
+   * From now, the application is waiting for the ready event ( VS_HCI_C2_Ready )
+   * received on the system channel before starting the Stack
+   * This system event is received with APPE_SysUserEvtRx()
+   */
+/* USER CODE BEGIN APPE_Init_2 */
+
+/* USER CODE END APPE_Init_2 */
+   return;
+}
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void Init_Debug( void )
+{
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  
+  /* Enable debugger EXTI lines */
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+  LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  /* Disable debugger EXTI lines GPIOs */
+  GPIO_InitTypeDef gpio_config = {0};
+  
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  gpio_config.Pin  = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+  
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+  
+  /* Disable debugger EXTI lines */
+  LL_EXTI_DisableIT_32_63(LL_EXTI_LINE_48);
+  LL_C2_EXTI_DisableIT_32_63(LL_EXTI_LINE_48);
+
+  /**
+   * Do not keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+  
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+  
+  return;
+}
+
+/**
+ * @brief  Configure the system for power optimization
+ *
+ * @note  This API configures the system to be ready for low power mode
+ *
+ * @param  None
+ * @retval None
+ */
+static void SystemPower_Config( void )
+{
+
+  /**
+   * Select HSI as system clock source after Wake Up from Stop mode
+   */
+  LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
+  
+  /* Initialize low power manager */
+  UTIL_LPM_Init( );
+  
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+  /**
+   *  Enable USB power
+   */
+  HAL_PWREx_EnableVddUSB();
+#endif
+  
+  return;
+}
+
+static void appe_Tl_Init( void )
+{
+  TL_MM_Config_t tl_mm_config;
+  SHCI_TL_HciInitConf_t SHci_Tl_Init_Conf;
+  
+  /**< Reference table initialization */
+  TL_Init();
+  
+  /**< System channel initialization */
+  UTIL_SEQ_RegTask( 1<< CFG_TASK_SYSTEM_HCI_ASYNCH_EVT, UTIL_SEQ_RFU, shci_user_evt_proc);
+  SHci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&SystemCmdBuffer;
+  SHci_Tl_Init_Conf.StatusNotCallBack = APPE_SysStatusNot;
+  shci_init(APPE_SysUserEvtRx, (void*) &SHci_Tl_Init_Conf);
+  
+  /**< Memory Manager channel initialization */
+  tl_mm_config.p_BleSpareEvtBuffer = 0;
+  tl_mm_config.p_SystemSpareEvtBuffer = SystemSpareEvtBuffer;
+  tl_mm_config.p_AsynchEvtPool = EvtPool;
+  tl_mm_config.AsynchEvtPoolSize = POOL_SIZE;
+  TL_MM_Init( &tl_mm_config );
+  
+  /* Enable transport layer and start CPU2 */
+  TL_Enable();
+  
+  return;
+}
+
+static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status )
+{
+  UNUSED(status);
+  return;
+}
+
+/**
+ * The type of the payload for a system user event is tSHCI_UserEvtRxParam
+ * When the system event is both :
+ *    - a ready event (subevtcode = SHCI_SUB_EVT_CODE_READY)
+ *    - reported by the FUS (sysevt_ready_rsp == RSS_FW_RUNNING)
+ * The buffer shall not be released
+ * ( eg ((tSHCI_UserEvtRxParam*)pPayload)->status shall be set to SHCI_TL_UserEventFlow_Disable )
+ * When the status is not filled, the buffer is released by default
+ */
+static void APPE_SysUserEvtRx( void * pPayload )
+{
+  TL_AsynchEvt_t *p_sys_event;
+  p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload);
+  
+  switch(p_sys_event->subevtcode)
+  {
+    case SHCI_SUB_EVT_CODE_READY:
+      APPE_SysEvtReadyProcessing();
+      break;
+      
+    case SHCI_SUB_EVT_ERROR_NOTIF:
+      APPE_SysEvtError((SCHI_SystemErrCode_t) (p_sys_event->payload[0]));
+      break;
+      
+    default:
+      break;
+  }
+  return;
+}
+
+/**
+ * @brief Notify a system error coming from the M0 firmware
+ * @param  ErrorCode  : errorCode detected by the M0 firmware
+ *
+ * @retval None
+ */
+static void APPE_SysEvtError( SCHI_SystemErrCode_t ErrorCode)
+{
+  switch(ErrorCode)
+  {
+  case ERR_THREAD_LLD_FATAL_ERROR:
+    APP_DBG("** ERR_THREAD : LLD_FATAL_ERROR \n");
+    break;
+    
+  case ERR_THREAD_UNKNOWN_CMD:
+    APP_DBG("** ERR_THREAD : UNKNOWN_CMD \n");
+    break;
+    
+  default:
+    APP_DBG("** ERR_THREAD : ErroCode=%d \n",ErrorCode);
+    break;
+  }
+  return;
+}
+
+static void APPE_SysEvtReadyProcessing( void )
+{
+  /* Traces channel initialization */
+  TL_TRACES_Init();
+  
+  APP_THREAD_Init();
+  
+  UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE);
+  return;
+}
+
+/* USER CODE BEGIN FD_LOCAL_FUNCTIONS */
+static void Led_Init( void )
+{
+#if (CFG_LED_SUPPORTED == 1U)
+  /**
+   * Leds Initialization
+   */
+#if (CFG_HW_LPUART1_ENABLED != 1) || ! defined (STM32WB35xx)
+  // On Little DORY, LED_BLUE share the GPIO PB5 with LPUART
+  BSP_LED_Init(LED_BLUE);
+#endif
+  BSP_LED_Init(LED_GREEN);
+  BSP_LED_Init(LED_RED);
+#endif
+  
+  return;
+}
+
+static void Button_Init( void )
+{
+#if (CFG_BUTTON_SUPPORTED == 1U)
+  /**
+   * Button Initialization
+   */
+
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+#endif
+  
+  return;
+}
+
+/* USER CODE END FD_LOCAL_FUNCTIONS */
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+
+void UTIL_SEQ_Idle( void )
+{
+#if ( CFG_LPM_SUPPORTED == 1)
+  UTIL_LPM_EnterLowPower( );
+#endif
+  return;
+}
+
+/**
+  * @brief  This function is called by the scheduler each time an event
+  *         is pending.
+  *
+  * @param  evt_waited_bm : Event pending.
+  * @retval None
+  */
+void UTIL_SEQ_EvtIdle( UTIL_SEQ_bm_t task_id_bm, UTIL_SEQ_bm_t evt_waited_bm )
+{
+  switch(evt_waited_bm)
+  {
+    case EVENT_ACK_FROM_M0_EVT:
+      /* Does not allow other tasks when waiting for OT Cmd response */
+      UTIL_SEQ_Run(0);
+      break;
+    case EVENT_SYNCHRO_BYPASS_IDLE:
+      UTIL_SEQ_SetEvt(EVENT_SYNCHRO_BYPASS_IDLE);
+      /* Run only the task CFG_TASK_MSG_FROM_M0_TO_M4 */
+      UTIL_SEQ_Run(TASK_MSG_FROM_M0_TO_M4);
+      break;
+    default :
+      /* default case : schedule all tasks */
+      UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+      break;
+  }
+}
+
+void shci_notify_asynch_evt(void* pdata)
+{
+  UNUSED(pdata);
+  UTIL_SEQ_SetTask(1U << CFG_TASK_SYSTEM_HCI_ASYNCH_EVT, CFG_SCH_PRIO_0);
+  return;
+}
+
+void shci_cmd_resp_release(uint32_t flag)
+{
+  UNUSED(flag);
+  UTIL_SEQ_SetEvt(1U << CFG_EVT_SYSTEM_HCI_CMD_EVT_RESP);
+  return;
+}
+
+void shci_cmd_resp_wait(uint32_t timeout)
+{
+  UNUSED(timeout);
+  UTIL_SEQ_WaitEvt(1U << CFG_EVT_SYSTEM_HCI_CMD_EVT_RESP);
+  return;
+}
+
+/* Received trace buffer from M0 */
+void TL_TRACES_EvtReceived( TL_EvtPacket_t * hcievt )
+{
+#if(CFG_DEBUG_TRACE != 0)
+  /* Call write/print function using DMA from dbg_trace */
+  /* - Cast to TL_AsynchEvt_t* to get "real" payload (without Sub Evt code 2bytes),
+     - (-2) to size to remove Sub Evt Code */
+  DbgTraceWrite(1U, (const unsigned char *) ((TL_AsynchEvt_t *)(hcievt->evtserial.evt.payload))->payload, hcievt->evtserial.evt.plen - 2U);
+#endif /* CFG_DEBUG_TRACE */
+  /* Release buffer */
+  TL_MM_EvtDone( hcievt );
+}
+/**
+  * @brief  Initialisation of the trace mechanism
+  * @param  None
+  * @retval None
+  */
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+#if (CFG_HW_LPUART1_ENABLED == 1)
+  MX_LPUART1_UART_Init();
+#endif
+  
+  return;
+}
+
+/**
+  * @brief  Management of the traces
+  * @param  p_data : data
+  * @param  size : size
+  * @param  call-back :
+  * @retval None
+  */
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+  return;
+}
+#endif
+
+/* USER CODE BEGIN FD_WRAP_FUNCTIONS */
+
+/* USER CODE END FD_WRAP_FUNCTIONS */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/hw_timerserver.c b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/hw_timerserver.c
new file mode 100644
index 000000000..c842ba55e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/hw_timerserver.c
@@ -0,0 +1,893 @@
+/**
+ ******************************************************************************
+  * File Name          : hw_timerserver.c
+  * Description        : Hardware timerserver source file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "hw_conf.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef enum
+{
+  TimerID_Free,
+  TimerID_Created,
+  TimerID_Running
+}TimerIDStatus_t;
+
+typedef enum
+{
+  SSR_Read_Requested,
+  SSR_Read_Not_Requested
+}RequestReadSSR_t;
+
+typedef enum
+{
+  WakeupTimerValue_Overpassed,
+  WakeupTimerValue_LargeEnough
+}WakeupTimerLimitation_Status_t;
+
+typedef struct
+{
+  HW_TS_pTimerCb_t  pTimerCallBack;
+  uint32_t        CounterInit;
+  uint32_t        CountLeft;
+  TimerIDStatus_t     TimerIDStatus;
+  HW_TS_Mode_t   TimerMode;
+  uint32_t        TimerProcessID;
+  uint8_t         PreviousID;
+  uint8_t         NextID;
+}TimerContext_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define SSR_FORBIDDEN_VALUE   0xFFFFFFFF
+#define TIMER_LIST_EMPTY      0xFFFF
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/**
+ * START of Section TIMERSERVER_CONTEXT
+ */
+
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile TimerContext_t aTimerContext[CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER];
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint8_t CurrentRunningTimerID;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint8_t PreviousRunningTimerID;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile uint32_t SSRValueOnLastSetup;
+PLACE_IN_SECTION("TIMERSERVER_CONTEXT") static volatile WakeupTimerLimitation_Status_t  WakeupTimerLimitation;
+
+/**
+ * END of Section TIMERSERVER_CONTEXT
+ */
+
+static RTC_HandleTypeDef *phrtc;  /**< RTC handle */
+static uint8_t  WakeupTimerDivider;
+static uint8_t  AsynchPrescalerUserConfig;
+static uint16_t SynchPrescalerUserConfig;
+static volatile uint16_t MaxWakeupTimerSetup;
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void RestartWakeupCounter(uint16_t Value);
+static uint16_t ReturnTimeElapsed(void);
+static void RescheduleTimerList(void);
+static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR);
+static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID);
+static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID);
+static uint16_t linkTimer(uint8_t TimerID);
+static uint32_t ReadRtcSsrValue(void);
+
+__weak void HW_TS_RTC_CountUpdated_AppNot(void);
+
+/* Functions Definition ------------------------------------------------------*/
+
+/**
+ * @brief  Read the RTC_SSR value
+ *         As described in the reference manual, the RTC_SSR shall be read twice to ensure
+ *         reliability of the value
+ * @param  None
+ * @retval SSR value read
+ */
+static uint32_t ReadRtcSsrValue(void)
+{
+  uint32_t first_read;
+  uint32_t second_read;
+
+  first_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+
+  second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+
+  while(first_read != second_read)
+  {
+    first_read = second_read;
+
+    second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
+  }
+
+  return second_read;
+}
+
+/**
+ * @brief  Insert a Timer in the list after the Timer ID specified
+ * @param  TimerID:   The ID of the Timer
+ * @param  RefTimerID: The ID of the Timer to be linked after
+ * @retval None
+ */
+static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID)
+{
+  uint8_t next_id;
+
+  next_id = aTimerContext[RefTimerID].NextID;
+
+  if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    aTimerContext[next_id].PreviousID = TimerID;
+  }
+  aTimerContext[TimerID].NextID = next_id;
+  aTimerContext[TimerID].PreviousID = RefTimerID ;
+  aTimerContext[RefTimerID].NextID = TimerID;
+
+  return;
+}
+
+/**
+ * @brief  Insert a Timer in the list before the ID specified
+ * @param  TimerID:   The ID of the Timer
+ * @param  RefTimerID: The ID of the Timer to be linked before
+ * @retval None
+ */
+static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID)
+{
+  uint8_t previous_id;
+
+  if(RefTimerID != CurrentRunningTimerID)
+  {
+    previous_id = aTimerContext[RefTimerID].PreviousID;
+
+    aTimerContext[previous_id].NextID = TimerID;
+    aTimerContext[TimerID].NextID = RefTimerID;
+    aTimerContext[TimerID].PreviousID = previous_id ;
+    aTimerContext[RefTimerID].PreviousID = TimerID;
+  }
+  else
+  {
+    aTimerContext[TimerID].NextID = RefTimerID;
+    aTimerContext[RefTimerID].PreviousID = TimerID;
+  }
+
+  return;
+}
+
+/**
+ * @brief  Insert a Timer in the list
+ * @param  TimerID:   The ID of the Timer
+ * @retval None
+ */
+static uint16_t linkTimer(uint8_t TimerID)
+{
+  uint32_t time_left;
+  uint16_t time_elapsed;
+  uint8_t timer_id_lookup;
+  uint8_t next_id;
+
+  if(CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    /**
+     * No timer in the list
+     */
+    PreviousRunningTimerID = CurrentRunningTimerID;
+    CurrentRunningTimerID = TimerID;
+    aTimerContext[TimerID].NextID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;
+
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+    time_elapsed = 0;
+  }
+  else
+  {
+    time_elapsed = ReturnTimeElapsed();
+
+    /**
+     * update count of the timer to be linked
+     */
+    aTimerContext[TimerID].CountLeft += time_elapsed;
+    time_left = aTimerContext[TimerID].CountLeft;
+
+    /**
+     * Search for index where the new timer shall be linked
+     */
+    if(aTimerContext[CurrentRunningTimerID].CountLeft <= time_left)
+    {
+      /**
+       * Search for the ID after the first one
+       */
+      timer_id_lookup = CurrentRunningTimerID;
+      next_id = aTimerContext[timer_id_lookup].NextID;
+      while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left))
+      {
+        timer_id_lookup = aTimerContext[timer_id_lookup].NextID;
+        next_id = aTimerContext[timer_id_lookup].NextID;
+      }
+
+      /**
+       * Link after the ID
+       */
+      LinkTimerAfter(TimerID, timer_id_lookup);
+    }
+    else
+    {
+      /**
+       * Link before the first ID
+       */
+      LinkTimerBefore(TimerID, CurrentRunningTimerID);
+      PreviousRunningTimerID = CurrentRunningTimerID;
+      CurrentRunningTimerID = TimerID;
+    }
+  }
+
+  return time_elapsed;
+}
+
+/**
+ * @brief  Remove a Timer from the list
+ * @param  TimerID:   The ID of the Timer
+ * @param  RequestReadSSR: Request to read the SSR register or not
+ * @retval None
+ */
+static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR)
+{
+  uint8_t previous_id;
+  uint8_t next_id;
+
+  if(TimerID == CurrentRunningTimerID)
+  {
+    PreviousRunningTimerID = CurrentRunningTimerID;
+    CurrentRunningTimerID = aTimerContext[TimerID].NextID;
+  }
+  else
+  {
+    previous_id = aTimerContext[TimerID].PreviousID;
+    next_id = aTimerContext[TimerID].NextID;
+
+    aTimerContext[previous_id].NextID = aTimerContext[TimerID].NextID;
+    if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+    {
+      aTimerContext[next_id].PreviousID = aTimerContext[TimerID].PreviousID;
+    }
+  }
+
+  /**
+   * Timer is out of the list
+   */
+  aTimerContext[TimerID].TimerIDStatus = TimerID_Created;
+
+  if((CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (RequestReadSSR == SSR_Read_Requested))
+  {
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+  }
+
+  return;
+}
+
+/**
+ * @brief  Return the number of ticks counted by the wakeuptimer since it has been started
+ * @note  The API is reading the SSR register to get how many ticks have been counted
+ *        since the time the timer has been started
+ * @param  None
+ * @retval Time expired in Ticks
+ */
+static uint16_t ReturnTimeElapsed(void)
+{
+  uint32_t  return_value;
+  uint32_t  wrap_counter;
+
+  if(SSRValueOnLastSetup != SSR_FORBIDDEN_VALUE)
+  {
+    return_value = ReadRtcSsrValue(); /**< Read SSR register first */
+
+    if (SSRValueOnLastSetup >= return_value)
+    {
+      return_value = SSRValueOnLastSetup - return_value;
+    }
+    else
+    {
+      wrap_counter = SynchPrescalerUserConfig - return_value;
+      return_value = SSRValueOnLastSetup + wrap_counter;
+    }
+
+    /**
+     * At this stage, ReturnValue holds the number of ticks counted by SSR
+     * Need to translate in number of ticks counted by the Wakeuptimer
+     */
+    return_value = return_value*AsynchPrescalerUserConfig;
+    return_value = return_value >> WakeupTimerDivider;
+  }
+  else
+  {
+    return_value = 0;
+  }
+
+  return (uint16_t)return_value;
+}
+
+/**
+ * @brief  Set the wakeup counter
+ * @note  The API is writing the counter value so that the value is decreased by one to cope with the fact
+ *    the interrupt is generated with 1 extra clock cycle (See RefManuel)
+ *    It assumes all condition are met to be allowed to write the wakeup counter
+ * @param  Value: Value to be written in the counter
+ * @retval None
+ */
+static void RestartWakeupCounter(uint16_t Value)
+{
+  /**
+   * The wakeuptimer has been disabled in the calling function to reduce the time to poll the WUTWF
+   * FLAG when the new value will have to be written
+   *  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);
+   */
+
+  if(Value == 0)
+  {
+    SSRValueOnLastSetup = ReadRtcSsrValue();
+
+    /**
+     * Simulate that the Timer expired
+     */
+    HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
+  }
+  else
+  {
+    if((Value > 1) ||(WakeupTimerDivider != 1))
+    {
+      Value -= 1;
+    }
+
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+    /**
+     * make sure to clear the flags after checking the WUTWF.
+     * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+     * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+     * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+     * due to the autoreload feature
+     */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+    HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);   /**<  Clear pending bit in NVIC */
+
+    MODIFY_REG(RTC->WUTR, RTC_WUTR_WUT, Value);
+
+    /**
+     * Update the value here after the WUTWF polling that may take some time
+     */
+    SSRValueOnLastSetup = ReadRtcSsrValue();
+
+    __HAL_RTC_WAKEUPTIMER_ENABLE(phrtc);    /**<  Enable the Wakeup Timer */
+
+    HW_TS_RTC_CountUpdated_AppNot();
+  }
+
+  return ;
+}
+
+/**
+ * @brief  Reschedule the list of timer
+ * @note  1) Update the count left for each timer in the list
+ *    2) Setup the wakeuptimer
+ * @param  None
+ * @retval None
+ */
+static void RescheduleTimerList(void)
+{
+  uint8_t   localTimerID;
+  uint32_t  timecountleft;
+  uint16_t  wakeup_timer_value;
+  uint16_t  time_elapsed;
+
+  /**
+   * The wakeuptimer is disabled now to reduce the time to poll the WUTWF
+   * FLAG when the new value will have to be written
+   */
+  if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+  {
+    /**
+     * Wait for the flag to be back to 0 when the wakeup timer is enabled
+     */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == SET);
+  }
+  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);   /**<  Disable the Wakeup Timer */
+
+  localTimerID = CurrentRunningTimerID;
+
+  /**
+   * Calculate what will be the value to write in the wakeuptimer
+   */
+  timecountleft = aTimerContext[localTimerID].CountLeft;
+
+  /**
+   * Read how much has been counted
+   */
+  time_elapsed = ReturnTimeElapsed();
+
+  if(timecountleft < time_elapsed )
+  {
+    /**
+     * There is no tick left to count
+     */
+    wakeup_timer_value = 0;
+    WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+  }
+  else
+  {
+    if(timecountleft > (time_elapsed + MaxWakeupTimerSetup))
+    {
+      /**
+       * The number of tick left is greater than the Wakeuptimer maximum value
+       */
+      wakeup_timer_value = MaxWakeupTimerSetup;
+
+      WakeupTimerLimitation = WakeupTimerValue_Overpassed;
+    }
+    else
+    {
+      wakeup_timer_value = timecountleft - time_elapsed;
+      WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+    }
+
+  }
+
+  /**
+   * update ticks left to be counted for each timer
+   */
+  while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    if (aTimerContext[localTimerID].CountLeft < time_elapsed)
+    {
+      aTimerContext[localTimerID].CountLeft = 0;
+    }
+    else
+    {
+      aTimerContext[localTimerID].CountLeft -= time_elapsed;
+    }
+    localTimerID = aTimerContext[localTimerID].NextID;
+  }
+
+  /**
+   * Write next count
+   */
+  RestartWakeupCounter(wakeup_timer_value);
+
+  return ;
+}
+
+/* Public functions ----------------------------------------------------------*/
+
+/**
+ * For all public interface except that may need write access to the RTC, the RTC
+ * shall be unlock at the beginning and locked at the output
+ * In order to ease maintainability, the unlock is done at the top and the lock at then end
+ * in case some new implementation is coming in the future
+ */
+
+void HW_TS_RTC_Wakeup_Handler(void)
+{
+  HW_TS_pTimerCb_t ptimer_callback;
+  uint32_t timer_process_id;
+  uint8_t local_current_running_timer_id;
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+/* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  /**
+   * Disable the Wakeup Timer
+   * This may speed up a bit the processing to wait the timer to be disabled
+   * The timer is still counting 2 RTCCLK
+   */
+  __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);
+
+  local_current_running_timer_id = CurrentRunningTimerID;
+
+  if(aTimerContext[local_current_running_timer_id].TimerIDStatus == TimerID_Running)
+  {
+    ptimer_callback = aTimerContext[local_current_running_timer_id].pTimerCallBack;
+    timer_process_id = aTimerContext[local_current_running_timer_id].TimerProcessID;
+
+    /**
+     * It should be good to check whether the TimeElapsed is greater or not than the tick left to be counted
+     * However, due to the inaccuracy of the reading of the time elapsed, it may return there is 1 tick
+     * to be left whereas the count is over
+     * A more secure implementation has been done with a flag to state whereas the full count has been written
+     * in the wakeuptimer or not
+     */
+    if(WakeupTimerLimitation != WakeupTimerValue_Overpassed)
+    {
+      if(aTimerContext[local_current_running_timer_id].TimerMode == hw_ts_Repeated)
+      {
+        UnlinkTimer(local_current_running_timer_id, SSR_Read_Not_Requested);
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+        __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+        HW_TS_Start(local_current_running_timer_id, aTimerContext[local_current_running_timer_id].CounterInit);
+
+        /* Disable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+        }
+      else
+      {
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+        __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+        HW_TS_Stop(local_current_running_timer_id);
+
+        /* Disable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+        }
+
+      HW_TS_RTC_Int_AppNot(timer_process_id, local_current_running_timer_id, ptimer_callback);
+    }
+    else
+    {
+      RescheduleTimerList();
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+      __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+    }
+  }
+  else
+  {
+    /**
+     * We should never end up in this case
+     * However, if due to any bug in the timer server this is the case, the mistake may not impact the user.
+     * We could just clean the interrupt flag and get out from this unexpected interrupt
+     */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+    /**
+     * make sure to clear the flags after checking the WUTWF.
+     * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+     * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+     * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+     * due to the autoreload feature
+     */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  return;
+}
+
+void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *hrtc)
+{
+  uint8_t loop;
+  uint32_t localmaxwakeuptimersetup;
+
+  /**
+   * Get RTC handler
+   */
+  phrtc = hrtc;
+
+ /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
+
+  /**
+   * Readout the user config
+   */
+  WakeupTimerDivider = (4 - ((uint32_t)(READ_BIT(RTC->CR, RTC_CR_WUCKSEL))));
+
+  AsynchPrescalerUserConfig = (uint8_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_A) >> (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)) + 1;
+
+  SynchPrescalerUserConfig = (uint16_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_S)) + 1;
+
+  /**
+   *  Margin is taken to avoid wrong calculation when the wrap around is there and some
+   *  application interrupts may have delayed the reading
+   */
+  localmaxwakeuptimersetup = ((((SynchPrescalerUserConfig - 1)*AsynchPrescalerUserConfig) - CFG_HW_TS_RTC_HANDLER_MAX_DELAY) >> WakeupTimerDivider);
+
+  if(localmaxwakeuptimersetup >= 0xFFFF)
+  {
+    MaxWakeupTimerSetup = 0xFFFF;
+  }
+  else
+  {
+    MaxWakeupTimerSetup = (uint16_t)localmaxwakeuptimersetup;
+  }
+
+  /**
+   * Configure EXTI module
+   */
+  LL_EXTI_EnableRisingTrig_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+  LL_EXTI_EnableIT_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+
+  if(TimerInitMode == hw_ts_InitMode_Full)
+  {
+    WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
+    SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
+
+    /**
+     * Initialize the timer server
+     */
+    for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++)
+    {
+      aTimerContext[loop].TimerIDStatus = TimerID_Free;
+    }
+
+    CurrentRunningTimerID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;   /**<  Set ID to non valid value */
+
+    __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);                       /**<  Disable the Wakeup Timer */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);     /**<  Clear flag in RTC module */
+    __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module  */
+    HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);       /**<  Clear pending bit in NVIC  */
+    __HAL_RTC_WAKEUPTIMER_ENABLE_IT(phrtc, RTC_IT_WUT);         /**<  Enable interrupt in RTC module  */
+  }
+  else
+  {
+    if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTF) != RESET)
+    {
+      /**
+       * Simulate that the Timer expired
+       */
+      HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_SetPriority(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO);   /**<  Set NVIC priority */
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+  return;
+}
+
+HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pftimeout_handler)
+{
+  HW_TS_ReturnStatus_t localreturnstatus;
+  uint8_t loop = 0;
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  while((loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[loop].TimerIDStatus != TimerID_Free))
+  {
+    loop++;
+  }
+
+  if(loop != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+  {
+    aTimerContext[loop].TimerIDStatus = TimerID_Created;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+    aTimerContext[loop].TimerProcessID = TimerProcessID;
+    aTimerContext[loop].TimerMode = TimerMode;
+    aTimerContext[loop].pTimerCallBack = pftimeout_handler;
+    *pTimerId = loop;
+
+    localreturnstatus = hw_ts_Successful;
+  }
+  else
+  {
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+    __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+    localreturnstatus = hw_ts_Failed;
+  }
+
+  return(localreturnstatus);
+}
+
+void HW_TS_Delete(uint8_t timer_id)
+{
+  HW_TS_Stop(timer_id);
+
+  aTimerContext[timer_id].TimerIDStatus = TimerID_Free; /**<  release ID */
+
+  return;
+}
+
+void HW_TS_Stop(uint8_t timer_id)
+{
+  uint8_t localcurrentrunningtimerid;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);    /**<  Disable NVIC */
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
+  {
+    UnlinkTimer(timer_id, SSR_Read_Requested);
+    localcurrentrunningtimerid = CurrentRunningTimerID;
+
+    if(localcurrentrunningtimerid == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
+    {
+      /**
+       * List is empty
+       */
+
+      /**
+       * Disable the timer
+       */
+      if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+      {
+        /**
+         * Wait for the flag to be back to 0 when the wakeup timer is enabled
+         */
+        while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == SET);
+      }
+      __HAL_RTC_WAKEUPTIMER_DISABLE(phrtc);   /**<  Disable the Wakeup Timer */
+
+      while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(phrtc, RTC_FLAG_WUTWF) == RESET);
+
+      /**
+       * make sure to clear the flags after checking the WUTWF.
+       * It takes 2 RTCCLK between the time the WUTE bit is disabled and the
+       * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
+       * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
+       * due to the autoreload feature
+       */
+      __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(phrtc, RTC_FLAG_WUTF);   /**<  Clear flag in RTC module */
+      __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**<  Clear flag in EXTI module */
+      HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);   /**<  Clear pending bit in NVIC */
+    }
+    else if(PreviousRunningTimerID != localcurrentrunningtimerid)
+    {
+      RescheduleTimerList();
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+  return;
+}
+
+void HW_TS_Start(uint8_t timer_id, uint32_t timeout_ticks)
+{
+  uint16_t time_elapsed;
+  uint8_t localcurrentrunningtimerid;
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  uint32_t primask_bit;
+#endif
+
+  if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
+  {
+    HW_TS_Stop( timer_id );
+  }
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();          /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+#endif
+
+  HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);    /**<  Disable NVIC */
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE( phrtc );
+
+  aTimerContext[timer_id].TimerIDStatus = TimerID_Running;
+
+  aTimerContext[timer_id].CountLeft = timeout_ticks;
+  aTimerContext[timer_id].CounterInit = timeout_ticks;
+
+  time_elapsed =  linkTimer(timer_id);
+
+  localcurrentrunningtimerid = CurrentRunningTimerID;
+
+  if(PreviousRunningTimerID != localcurrentrunningtimerid)
+  {
+    RescheduleTimerList();
+  }
+  else
+  {
+    aTimerContext[timer_id].CountLeft -= time_elapsed;
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE( phrtc );
+
+  HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**<  Enable NVIC */
+
+#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
+  __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
+#endif
+
+  return;
+}
+
+uint16_t HW_TS_RTC_ReadLeftTicksToCount(void)
+{
+  uint32_t primask_bit;
+  uint16_t return_value, auro_reload_value, elapsed_time_value;
+
+  primask_bit = __get_PRIMASK();  /**< backup PRIMASK bit */
+  __disable_irq();                /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
+
+  if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
+  {
+    auro_reload_value = (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT));
+
+    elapsed_time_value = ReturnTimeElapsed();
+
+    if(auro_reload_value > elapsed_time_value)
+    {
+      return_value = auro_reload_value - elapsed_time_value;
+    }
+    else
+    {
+      return_value = 0;
+    }
+  }
+  else
+  {
+    return_value = TIMER_LIST_EMPTY;
+  }
+
+  __set_PRIMASK(primask_bit);     /**< Restore PRIMASK bit*/
+
+  return (return_value);
+}
+
+__weak void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack)
+{
+  pTimerCallBack();
+
+  return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/hw_uart.c b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/hw_uart.c
new file mode 100644
index 000000000..8ea61633f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/hw_uart.c
@@ -0,0 +1,484 @@
+/**
+ ******************************************************************************
+  * File Name          : Src/hw_uart.c
+  * Description        : HW UART source file for STM32WPAN Middleware.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+/* Macros --------------------------------------------------------------------*/
+#define HW_UART_RX_IT(__HANDLE__, __USART_BASE__)                                    \
+        do{                                                                          \
+            HW_##__HANDLE__##RxCb = cb;                                              \
+            (__HANDLE__).Instance = (__USART_BASE__);                                \
+            hal_status = HAL_UART_Receive_IT(&(__HANDLE__), p_data, size);           \
+        } while(0)
+
+#define HW_UART_TX_IT(__HANDLE__, __USART_BASE__)                                    \
+        do{                                                                          \
+            HW_##__HANDLE__##TxCb = cb;                                              \
+            (__HANDLE__).Instance = (__USART_BASE__);                                \
+            hal_status = HAL_UART_Transmit_IT(&(__HANDLE__), p_data, size);          \
+        } while(0)
+
+#define HW_UART_TX(__HANDLE__, __USART_BASE__)                                       \
+        do{                                                                          \
+            (__HANDLE__).Instance = (__USART_BASE__);                                \
+            hal_status = HAL_UART_Transmit(&(__HANDLE__), p_data, size, timeout);    \
+        } while(0)
+
+/* Variables -----------------------------------------------------------------*/
+#if (CFG_HW_USART1_ENABLED == 1)
+UART_HandleTypeDef huart1;
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+DMA_HandleTypeDef hdma_usart1_tx;
+#endif
+void (*HW_huart1RxCb)(void);
+void (*HW_huart1TxCb)(void);
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+UART_HandleTypeDef hlpuart1;
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+DMA_HandleTypeDef hdma_lpuart1_tx;
+#endif
+void (*HW_hlpuart1RxCb)(void);
+void (*HW_hlpuart1TxCb)(void);
+#endif
+
+/* Functions Definition ------------------------------------------------------*/
+#if (CFG_HW_LPUART1_ENABLED == 1)
+/**
+  * @brief LPUART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+void MX_LPUART1_UART_Init(void)
+{
+  hlpuart1.Instance = LPUART1;
+  hlpuart1.Init.BaudRate = 115200;
+  hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
+  hlpuart1.Init.StopBits = UART_STOPBITS_1;
+  hlpuart1.Init.Parity = UART_PARITY_NONE;
+  hlpuart1.Init.Mode = UART_MODE_TX_RX;
+  hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  hlpuart1.Init.OverSampling = UART_OVERSAMPLING_16;
+  hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  hlpuart1.FifoMode = UART_FIFOMODE_DISABLE;
+  if (HAL_UART_Init(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+void MX_LPUART1_UART_DeInit(void)
+{
+  hlpuart1.Instance = LPUART1;
+  hlpuart1.Init.BaudRate = 115200;
+  hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
+  hlpuart1.Init.StopBits = UART_STOPBITS_1;
+  hlpuart1.Init.Parity = UART_PARITY_NONE;
+  hlpuart1.Init.Mode = UART_MODE_TX_RX;
+  hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  hlpuart1.Init.OverSampling = UART_OVERSAMPLING_16;
+  hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  hlpuart1.FifoMode = UART_FIFOMODE_DISABLE;
+  if (HAL_UART_DeInit(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+#endif
+
+#if (CFG_HW_USART1_ENABLED == 1)
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+void MX_USART1_UART_Init(void)
+{
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  huart1.FifoMode = UART_FIFOMODE_DISABLE;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+void MX_USART1_UART_DeInit(void)
+{
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  huart1.FifoMode = UART_FIFOMODE_DISABLE;
+  if (HAL_UART_DeInit(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+#endif
+
+hw_status_t HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  hw_status_t hw_status = hw_uart_ok;
+  
+  switch (hw_uart_id)
+  {
+#if (CFG_HW_USART1_ENABLED == 1)
+    case hw_uart1:
+      HW_UART_RX_IT(huart1, USART1);
+      break;
+#endif
+    
+#if (CFG_HW_LPUART1_ENABLED == 1)
+    case hw_lpuart1:
+      HW_UART_RX_IT(hlpuart1, LPUART1);
+      break;
+#endif
+    
+    default:
+      break;
+  }
+  
+  switch (hal_status)
+  {
+    case HAL_OK:
+      hw_status = hw_uart_ok;
+      break;
+    
+    case HAL_ERROR:
+      hw_status = hw_uart_error;
+      break;
+    
+    case HAL_BUSY:
+      hw_status = hw_uart_busy;
+      break;
+    
+    case HAL_TIMEOUT:
+      hw_status = hw_uart_to;
+      break;
+    
+    default:
+      break;
+  }
+  
+  return hw_status;
+}
+
+hw_status_t HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  void (*cb)(void))
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  hw_status_t hw_status = hw_uart_ok;
+  
+  switch (hw_uart_id)
+  {
+#if (CFG_HW_USART1_ENABLED == 1)
+    case hw_uart1:
+      HW_UART_TX_IT(huart1, USART1);
+      break;
+#endif
+    
+#if (CFG_HW_LPUART1_ENABLED == 1)
+    case hw_lpuart1:
+      HW_UART_TX_IT(hlpuart1, LPUART1);
+      break;
+#endif
+    
+    default:
+      break;
+  }
+  
+  switch (hal_status)
+  {
+    case HAL_OK:
+      hw_status = hw_uart_ok;
+      break;
+    
+    case HAL_ERROR:
+      hw_status = hw_uart_error;
+      break;
+    
+    case HAL_BUSY:
+      hw_status = hw_uart_busy;
+      break;
+    
+    case HAL_TIMEOUT:
+      hw_status = hw_uart_to;
+      break;
+    
+    default:
+      break;
+  }
+  
+  return hw_status;
+}
+
+hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  hw_status_t hw_status = hw_uart_ok;
+  
+  switch (hw_uart_id)
+  {
+#if (CFG_HW_USART1_ENABLED == 1)
+    case hw_uart1:
+      HW_UART_TX(huart1, USART1);
+      break;
+#endif
+    
+#if (CFG_HW_LPUART1_ENABLED == 1)
+    case hw_lpuart1:
+      HW_UART_TX(hlpuart1, LPUART1);
+      break;
+#endif
+    
+    default:
+      break;
+  }
+  
+  switch (hal_status)
+  {
+    case HAL_OK:
+      hw_status = hw_uart_ok;
+      break;
+    
+    case HAL_ERROR:
+      hw_status = hw_uart_error;
+      break;
+    
+    case HAL_BUSY:
+      hw_status = hw_uart_busy;
+      break;
+    
+    case HAL_TIMEOUT:
+      hw_status = hw_uart_to;
+      break;
+    
+    default:
+      break;
+  }
+  
+  return hw_status;
+}
+
+hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  hw_status_t hw_status = hw_uart_ok;
+  
+  switch (hw_uart_id)
+  {
+#if (CFG_HW_USART1_ENABLED == 1)
+    case hw_uart1:
+      HW_huart1TxCb = cb;
+      huart1.Instance = USART1;
+      hal_status = HAL_UART_Transmit_DMA(&huart1, p_data, size);
+      break;
+#endif
+    
+#if (CFG_HW_LPUART1_ENABLED == 1)
+    case hw_lpuart1:
+      HW_hlpuart1TxCb = cb;
+      hlpuart1.Instance = LPUART1;
+      hal_status = HAL_UART_Transmit_DMA(&hlpuart1, p_data, size);
+      break;
+#endif
+    
+    default:
+      break;
+  }
+  
+  switch (hal_status)
+  {
+    case HAL_OK:
+      hw_status = hw_uart_ok;
+      break;
+    
+    case HAL_ERROR:
+      hw_status = hw_uart_error;
+      break;
+    
+    case HAL_BUSY:
+      hw_status = hw_uart_busy;
+      break;
+    
+    case HAL_TIMEOUT:
+      hw_status = hw_uart_to;
+      break;
+    
+    default:
+      break;
+  }
+  
+  return hw_status;
+}
+
+#if 0
+void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+{
+  switch (hw_uart_id)
+  {
+#if (CFG_HW_USART1_ENABLED == 1)
+    case hw_uart1:
+      HAL_UART_IRQHandler(&huart1);
+      break;
+#endif
+    
+#if (CFG_HW_LPUART1_ENABLED == 1)
+    case hw_lpuart1:
+      HAL_UART_IRQHandler(&hlpuart1);
+      break;
+#endif
+    
+    default:
+      break;
+  }
+  
+  return;
+}
+
+void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+{
+  switch (hw_uart_id)
+  {
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+    case hw_uart1:
+      HAL_DMA_IRQHandler(huart1.hdmatx);
+      break;
+#endif
+    
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+    case hw_lpuart1:
+      HAL_DMA_IRQHandler(hlpuart1.hdmatx);
+      break;
+#endif
+    
+    default:
+      break;
+  }
+  
+  return;
+}
+#endif
+
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+  switch ((uint32_t)huart->Instance)
+  {
+#if (CFG_HW_USART1_ENABLED == 1)
+    case (uint32_t)USART1:
+      if(HW_huart1RxCb)
+      {
+          HW_huart1RxCb();
+      }
+      break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+    case (uint32_t)LPUART1:
+      if(HW_hlpuart1RxCb)
+      {
+          HW_hlpuart1RxCb();
+      }
+      break;
+#endif
+    
+    default:
+      break;
+  }
+  
+  return;
+}
+
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+  switch ((uint32_t)huart->Instance)
+  {
+#if (CFG_HW_USART1_ENABLED == 1)
+    case (uint32_t)USART1:
+      if(HW_huart1TxCb)
+      {
+          HW_huart1TxCb();
+      }
+      break;
+#endif
+
+#if (CFG_HW_LPUART1_ENABLED == 1)
+    case (uint32_t)LPUART1:
+      if(HW_hlpuart1TxCb)
+      {
+          HW_hlpuart1TxCb();
+      }
+      break;
+#endif
+    
+    default:
+      break;
+  }
+  
+  return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/main.c b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/main.c
new file mode 100644
index 000000000..784e9307d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/main.c
@@ -0,0 +1,520 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    main.c
+ * @author  MCD Application Team
+ * @brief   main of the application
+ *
+  @verbatim
+  ==============================================================================
+                    ##### IMPORTANT NOTE #####
+  ==============================================================================
+
+  This application requests having the stm32wbx5xx_Thread_FTD_fw.bin or 
+  stm32wbx5xx_Thread_MTD_fw.bin binary flashed on the Wireless Coprocessor.
+  If it is not the case, you need to use STM32CubeProgrammer to load the appropriate
+  binary.
+
+  All available binaries are located under following directory:
+  /Projects/STM32_Copro_Wireless_Binaries
+
+  Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+  Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the
+  detailed procedure to change the Wireless Coprocessor binary.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "app_entry.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "stm32_lpm.h"
+#include "stm32_seq.h"
+#include "dbg_trace.h"
+#include "otp.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+RTC_HandleTypeDef hrtc;
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+static void MX_RF_Init(void);
+static void MX_RTC_Init(void);
+/* USER CODE BEGIN PFP */
+static void PeriphClock_Config(void);
+static void Reset_Device( void );
+static void Reset_IPCC( void );
+static void Reset_BackupDomain( void );
+static void Init_Exti( void );
+static void Config_HSE(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+  
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+  Reset_Device();
+  Config_HSE();
+  /* USER CODE END Init */
+  
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  PeriphClock_Config();
+  Init_Exti();
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_RF_Init();
+  MX_RTC_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+  
+  /* Init code for STM32_WPAN */  
+  APPE_Init();
+  
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure LSE Drive Capability 
+  */
+  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE
+                              |RCC_OSCILLATORTYPE_LSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RFWAKEUP
+                              |RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1
+                              |RCC_PERIPHCLK_LPUART1;
+  PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+  PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0;
+
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+  * @brief RF Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RF_Init(void)
+{
+
+  /* USER CODE BEGIN RF_Init 0 */
+
+  /* USER CODE END RF_Init 0 */
+
+  /* USER CODE BEGIN RF_Init 1 */
+
+  /* USER CODE END RF_Init 1 */
+  /* USER CODE BEGIN RF_Init 2 */
+
+  /* USER CODE END RF_Init 2 */
+
+}
+
+/**
+  * @brief RTC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RTC_Init(void)
+{
+
+  /* USER CODE BEGIN RTC_Init 0 */
+
+  /* USER CODE END RTC_Init 0 */
+
+  /* USER CODE BEGIN RTC_Init 1 */
+
+  /* USER CODE END RTC_Init 1 */
+  /** Initialize RTC Only 
+  */
+  hrtc.Instance = RTC;
+  hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
+  hrtc.Init.AsynchPrediv = CFG_RTC_ASYNCH_PRESCALER;
+  hrtc.Init.SynchPrediv = CFG_RTC_SYNCH_PRESCALER;
+  if (HAL_RTC_Init(&hrtc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN RTC_Init 2 */
+
+  /* USER CODE END RTC_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
+#ifdef STM32WB35xx
+  __HAL_RCC_DMA2_CLK_ENABLE();
+#endif
+
+  /* DMA interrupt init */
+#ifdef STM32WB35xx
+  /* DMA1_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
+  /* DMA2_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA2_Channel4_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(DMA2_Channel4_IRQn);
+#else
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+  /* DMA1_Channel2_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
+#endif
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  //__HAL_RCC_GPIOC_CLK_ENABLE();
+  //__HAL_RCC_GPIOA_CLK_ENABLE();
+  //__HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+static void PeriphClock_Config(void)
+{
+  #if (CFG_USB_INTERFACE_ENABLE != 0)
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
+  RCC_CRSInitTypeDef RCC_CRSInitStruct = { 0 };
+
+  /**
+   * This prevents the CPU2 to disable the HSI48 oscillator when
+   * it does not use anymore the RNG IP
+   */
+  LL_HSEM_1StepLock( HSEM, 5 );
+
+  LL_RCC_HSI48_Enable();
+
+  while(!LL_RCC_HSI48_IsReady());
+
+  /* Select HSI48 as USB clock source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /*Configure the clock recovery system (CRS)**********************************/
+
+  /* Enable CRS Clock */
+  __HAL_RCC_CRS_CLK_ENABLE();
+
+  /* Default Synchro Signal division factor (not divided) */
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+
+  /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+
+  /* HSI48 is synchronized with USB SOF at 1KHz rate */
+  RCC_CRSInitStruct.ReloadValue = RCC_CRS_RELOADVALUE_DEFAULT;
+  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+
+  RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+
+  /* Set the TRIM[5:0] to the default value*/
+  RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+
+  /* Start automatic synchronization */
+  HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+#endif
+
+  return;
+}
+
+static void Config_HSE(void)
+{
+    OTP_ID0_t * p_otp;
+
+  /**
+   * Read HSE_Tuning from OTP
+   */
+  p_otp = (OTP_ID0_t *) OTP_Read(0);
+  if (p_otp)
+  {
+    LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
+  }
+
+  return;
+}
+
+
+static void Reset_Device( void )
+{
+#if ( CFG_HW_RESET_BY_FW == 1 )
+  Reset_BackupDomain();
+  
+  Reset_IPCC();
+#endif
+  
+  return;
+}
+
+static void Reset_IPCC( void )
+{
+  LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
+
+  LL_C1_IPCC_ClearFlag_CHx(
+      IPCC,
+      LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+      | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+  LL_C2_IPCC_ClearFlag_CHx(
+      IPCC,
+      LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+      | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+  LL_C1_IPCC_DisableTransmitChannel(
+      IPCC,
+      LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+      | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+  LL_C2_IPCC_DisableTransmitChannel(
+      IPCC,
+      LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+      | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+  LL_C1_IPCC_DisableReceiveChannel(
+      IPCC,
+      LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+      | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+  LL_C2_IPCC_DisableReceiveChannel(
+      IPCC,
+      LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+      | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+  return;
+}
+
+static void Reset_BackupDomain( void )
+{
+  if ((LL_RCC_IsActiveFlag_PINRST() != FALSE) && (LL_RCC_IsActiveFlag_SFTRST() == FALSE))
+  {
+    HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+    
+    /**
+     *  Write twice the value to flush the APB-AHB bridge
+     *  This bit shall be written in the register before writing the next one
+     */
+    HAL_PWR_EnableBkUpAccess();
+    
+    __HAL_RCC_BACKUPRESET_FORCE();
+    __HAL_RCC_BACKUPRESET_RELEASE();
+  }
+  
+  return;
+}
+
+static void Init_Exti( void )
+{
+  /**< Disable all wakeup interrupt on CPU1  except LPUART(25), IPCC(36), HSEM(38) */
+  LL_EXTI_DisableIT_0_31( (~0) & (~(LL_EXTI_LINE_25)) );
+  LL_EXTI_DisableIT_32_63( (~0) & (~(LL_EXTI_LINE_36 | LL_EXTI_LINE_38)) );
+  
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += HAL_GetTickFreq();
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+  {
+    /************************************************************************************
+     * ENTER SLEEP MODE
+     ***********************************************************************************/
+    LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+    /**
+     * This option is used to ensure that store operations are completed
+     */
+  #if defined ( __CC_ARM)
+    __force_stores();
+  #endif
+
+    __WFI( );
+  }
+}
+/* USER CODE END 4 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/stm32_lpm_if.c b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/stm32_lpm_if.c
new file mode 100644
index 000000000..1418e0a36
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/stm32_lpm_if.c
@@ -0,0 +1,297 @@
+/* USER CODE BEGIN Header */
+/**
+ ***************************************************************************************
+  * File Name          : stm32_lpm_if.c
+  * Description        : Low layer function to enter/exit low power modes (stop, sleep).
+ ***************************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+  
+/* Includes ------------------------------------------------------------------*/  
+#include "stm32_lpm_if.h"
+#include "stm32_lpm.h"
+#include "app_conf.h"
+/* USER CODE BEGIN include */
+
+/* USER CODE END include */
+
+/* Exported variables --------------------------------------------------------*/
+const struct UTIL_LPM_Driver_s UTIL_PowerDriver = 
+{
+  PWR_EnterSleepMode,
+  PWR_ExitSleepMode,
+  
+  PWR_EnterStopMode,
+  PWR_ExitStopMode, 
+  
+  PWR_EnterOffMode,
+  PWR_ExitOffMode,
+};
+
+/* Private function prototypes -----------------------------------------------*/
+static void Switch_On_HSI( void );
+/* USER CODE BEGIN Private_Function_Prototypes */
+
+/* USER CODE END Private_Function_Prototypes */
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN Private_Typedef */
+
+/* USER CODE END Private_Typedef */
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Private_Define */
+
+/* USER CODE END Private_Define */
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Private_Macro */
+
+/* USER CODE END Private_Macro */
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN Private_Variables */
+
+/* USER CODE END Private_Variables */
+
+/* Functions Definition ------------------------------------------------------*/
+/**
+  * @brief Enters Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_EnterOffMode( void )
+{
+/* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
+  /************************************************************************************
+   * ENTER OFF MODE
+   ***********************************************************************************/
+  /*
+   * There is no risk to clear all the WUF here because in the current implementation, this API is called
+   * in critical section. If an interrupt occurs while in that critical section before that point,
+   * the flag is set and will be cleared here but the system will not enter Off Mode
+   * because an interrupt is pending in the NVIC. The ISR will be executed when moving out
+   * of this critical section
+   */
+  LL_PWR_ClearFlag_WU( );
+
+  LL_PWR_SetPowerMode( LL_PWR_MODE_STANDBY );
+
+  LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores( );
+#endif
+
+  __WFI( );
+/* USER CODE END PWR_EnterOffMode */
+}
+
+/**
+  * @brief Exits Low Power Off Mode
+  * @param none
+  * @retval none
+  */
+void PWR_ExitOffMode( void )
+{
+/* USER CODE BEGIN PWR_ExitOffMode */
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitOffMode */
+}
+
+/**
+  * @brief Enters Low Power Stop Mode
+  * @note ARM exists the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterStopMode( void )
+{
+/* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
+  /**
+   * This function is called from CRITICAL SECTION
+   */
+  while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
+
+  if ( ! LL_HSEM_1StepLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID ) )
+  {
+    if( LL_PWR_IsActiveFlag_C2DS( ) )
+    {
+      /* Release ENTRY_STOP_MODE semaphore */
+      LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
+
+      /**
+       * The switch on HSI before entering Stop Mode is required on Cut2.0
+       * It is useless from Cut2.1
+       */
+      Switch_On_HSI( );
+    }
+  }
+  else
+  {
+    /**
+     * The switch on HSI before entering Stop Mode is required on Cut2.0
+     * It is useless from Cut2.1
+     */
+    Switch_On_HSI( );
+  }
+
+  /* Release RCC semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  /************************************************************************************
+   * ENTER STOP MODE
+   ***********************************************************************************/
+  LL_PWR_SetPowerMode( LL_PWR_MODE_STOP2 );
+
+  LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores( );
+#endif
+
+  __WFI();
+/* USER CODE END PWR_EnterStopMode */
+}
+
+/**
+  * @brief Exits Low Power Stop Mode
+  * @note Enable the pll at 32MHz
+  * @param none
+  * @retval none
+  */
+void PWR_ExitStopMode( void )
+{
+/* USER CODE BEGIN PWR_ExitStopMode */
+  /**
+   * This function is called from CRITICAL SECTION
+   */
+
+  /* Release ENTRY_STOP_MODE semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
+
+  while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
+
+  if(LL_RCC_GetSysClkSource( ) == LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+    LL_RCC_HSE_Enable( );
+    while(!LL_RCC_HSE_IsReady( ));
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
+    while (LL_RCC_GetSysClkSource( ) != LL_RCC_SYS_CLKSOURCE_STATUS_HSE);
+  }
+  else
+  {
+    /**
+     * As long as the current application is fine with HSE as system clock source,
+     * there is nothing to do here
+     */
+  }
+
+  /* Release RCC semaphore */
+  LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitStopMode */
+}
+
+/**
+  * @brief Enters Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_EnterSleepMode( void )
+{
+/* USER CODE BEGIN PWR_EnterSleepMode */
+
+  HAL_SuspendTick();
+
+  /************************************************************************************
+   * ENTER SLEEP MODE
+   ***********************************************************************************/
+  LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+  /**
+   * This option is used to ensure that store operations are completed
+   */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+
+  __WFI( );
+/* USER CODE END PWR_EnterSleepMode */
+}
+
+/**
+  * @brief Exits Low Power Sleep Mode
+  * @note ARM exits the function when waking up
+  * @param none
+  * @retval none
+  */
+void PWR_ExitSleepMode( void )
+{
+/* USER CODE BEGIN PWR_ExitSleepMode */
+
+  HAL_ResumeTick();
+
+/* USER CODE END PWR_ExitSleepMode */
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+  * @brief Switch the system clock on HSI
+  * @param none
+  * @retval none
+  */
+static void Switch_On_HSI( void )
+{
+  LL_RCC_HSI_Enable( );
+  while(!LL_RCC_HSI_IsReady( ));
+  LL_RCC_SetSysClkSource( LL_RCC_SYS_CLKSOURCE_HSI );
+  LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSI);
+  while (LL_RCC_GetSysClkSource( ) != LL_RCC_SYS_CLKSOURCE_STATUS_HSI);
+}
+
+/* USER CODE BEGIN Private_Functions */
+
+/* USER CODE END Private_Functions */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..6d29b02b9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,360 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   This file contains the HAL System and Peripheral (UARTs, RTC) MSP initialization
+  *          and de-initialization functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+#include "app_common.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_HSEM_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* Peripheral interrupt init */
+  /* PVD_PVM_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(PVD_PVM_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(PVD_PVM_IRQn);
+  /* FLASH_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(FLASH_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(FLASH_IRQn);
+  /* RCC_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(RCC_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(RCC_IRQn);
+  /* C2SEV_PWR_C2H_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(C2SEV_PWR_C2H_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(C2SEV_PWR_C2H_IRQn);
+  /* PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQn);
+  /* HSEM_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(HSEM_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(HSEM_IRQn);
+  /* FPU_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(FPU_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(FPU_IRQn);
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+  * @brief UART MSP Initialization
+  * This function configures the hardware resources used in this example
+  * @param huart: UART handle pointer
+  * @retval None
+  */
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  HAL_DMA_MuxSyncConfigTypeDef pSyncConfig;
+  
+#if (CFG_HW_LPUART1_ENABLED == 1)
+  if(huart->Instance == LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspInit 0 */
+
+  /* USER CODE END LPUART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_LPUART1_CLK_ENABLE();
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+#ifdef STM32WB35xx
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+#else
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+#endif
+    /**LPUART1 GPIO Configuration    
+    PB5 on Little DORY PC1 on DORY ------> LPUART1_TX
+    PA3                            ------> LPUART1_RX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_3;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+#ifdef STM32WB35xx
+    GPIO_InitStruct.Pin = GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#else
+    GPIO_InitStruct.Pin = GPIO_PIN_1;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+#endif
+    
+    /* LPUART1 DMA Init */
+    /* LPUART1_TX Init */
+#ifdef STM32WB35xx
+    hdma_lpuart1_tx.Instance = DMA1_Channel4;
+#else
+    hdma_lpuart1_tx.Instance = DMA1_Channel1;
+#endif
+    hdma_lpuart1_tx.Init.Request = DMA_REQUEST_LPUART1_TX;
+    hdma_lpuart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_lpuart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_lpuart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_lpuart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_lpuart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_lpuart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_lpuart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_lpuart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+    
+    pSyncConfig.SyncSignalID = HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT;
+    pSyncConfig.SyncPolarity = HAL_DMAMUX_SYNC_NO_EVENT;
+    pSyncConfig.SyncEnable = DISABLE;
+    pSyncConfig.EventEnable = DISABLE;
+    pSyncConfig.RequestNumber = 1;
+    if (HAL_DMAEx_ConfigMuxSync(&hdma_lpuart1_tx, &pSyncConfig) != HAL_OK)
+    {
+      Error_Handler();
+    }
+    
+    __HAL_LINKDMA(huart,hdmatx,hdma_lpuart1_tx);
+    
+    /* LPUART1 interrupt Init */
+    HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(LPUART1_IRQn);
+  /* USER CODE BEGIN LPUART1_MspInit 1 */
+
+  /* USER CODE END LPUART1_MspInit 1 */
+  }
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+  if(huart->Instance == USART1)
+  {
+  /* USER CODE BEGIN USART1_MspInit 0 */
+
+  /* USER CODE END USART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**USART1 GPIO Configuration    
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+    
+    /* USART1 DMA Init */
+    /* USART1_TX Init */
+#ifdef STM32WB35xx
+    hdma_usart1_tx.Instance = DMA2_Channel4;
+#else
+    hdma_usart1_tx.Instance = DMA1_Channel2;
+#endif
+    hdma_usart1_tx.Init.Request = DMA_REQUEST_USART1_TX;
+    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+    
+    __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx);
+    
+    /* USART1 interrupt Init */
+    HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspInit 1 */
+
+  /* USER CODE END USART1_MspInit 1 */
+  }
+#endif
+}
+
+/**
+  * @brief UART MSP De-Initialization
+  * This function freeze the hardware resources used in this example
+  * @param huart: UART handle pointer
+  * @retval None
+  */
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+#if (CFG_HW_LPUART1_ENABLED == 1)
+  if(huart->Instance == LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspDeInit 0 */
+
+  /* USER CODE END LPUART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_LPUART1_CLK_DISABLE();
+    
+    /**LPUART1 GPIO Configuration    
+    PA2     ------> LPUART1_TX
+    PA3     ------> LPUART1_RX 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_3);
+#ifdef STM32WB35xx
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5);
+#else
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1);
+#endif
+    
+    /* LPUART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmatx);
+    
+    /* LPUART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(LPUART1_IRQn);
+  /* USER CODE BEGIN LPUART1_MspDeInit 1 */
+
+  /* USER CODE END LPUART1_MspDeInit 1 */
+  }
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+  if(huart->Instance == USART1)
+  {
+  /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+  /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+    
+    /**USART1 GPIO Configuration    
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
+    
+    /* USART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmatx);
+    
+    /* USART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+  /* USER CODE END USART1_MspDeInit 1 */
+  }
+#endif
+}
+
+/**
+* @brief RTC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspInit 0 */
+
+  /* USER CODE END RTC_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_RTC_ENABLE();
+  /* USER CODE BEGIN RTC_MspInit 1 */
+
+  /* USER CODE END RTC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspDeInit 0 */
+
+  /* USER CODE END RTC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RTC_DISABLE();
+  /* USER CODE BEGIN RTC_MspDeInit 1 */
+
+  /* USER CODE END RTC_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..9b5e7f207
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/stm32wbxx_it.c
@@ -0,0 +1,431 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_it.c
+  * @brief   Interrupt Service Routines.
+  *******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles PVD/PVM0/PVM2 interrupts through EXTI lines 16/31/33.
+  */
+void PVD_PVM_IRQHandler(void)
+{
+  /* USER CODE BEGIN PVD_PVM_IRQn 0 */
+
+  /* USER CODE END PVD_PVM_IRQn 0 */
+  HAL_PWREx_PVD_PVM_IRQHandler();
+  /* USER CODE BEGIN PVD_PVM_IRQn 1 */
+
+  /* USER CODE END PVD_PVM_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Flash global interrupt.
+  */
+void FLASH_IRQHandler(void)
+{
+  /* USER CODE BEGIN FLASH_IRQn 0 */
+
+  /* USER CODE END FLASH_IRQn 0 */
+  HAL_FLASH_IRQHandler();
+  /* USER CODE BEGIN FLASH_IRQn 1 */
+
+  /* USER CODE END FLASH_IRQn 1 */
+}
+
+/**
+  * @brief This function handles RCC global interrupt.
+  */
+void RCC_IRQHandler(void)
+{
+  /* USER CODE BEGIN RCC_IRQn 0 */
+
+  /* USER CODE END RCC_IRQn 0 */
+  /* USER CODE BEGIN RCC_IRQn 1 */
+
+  /* USER CODE END RCC_IRQn 1 */
+}
+
+#ifdef STM32WB35xx
+/**
+  * @brief This function handles DMA1 channel4 global interrupt.
+  */
+void DMA1_Channel4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel4_IRQn 0 */
+#if (CFG_HW_LPUART1_ENABLED == 1)
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+  HAL_DMA_IRQHandler(&hdma_lpuart1_tx);
+#endif
+#endif
+  /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel4_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA2 channel4 global interrupt.
+  */
+void DMA2_Channel4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2_Channel4_IRQn 0 */
+
+  /* USER CODE END DMA2_Channel4_IRQn 0 */
+#if (CFG_HW_USART1_ENABLED == 1)
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+  HAL_DMA_IRQHandler(&hdma_usart1_tx);
+#endif
+#endif
+  /* USER CODE BEGIN DMA2_Channel4_IRQn 1 */
+
+  /* USER CODE END DMA2_Channel4_IRQn 1 */
+}
+
+#else
+/**
+  * @brief This function handles DMA1 channel1 global interrupt.
+  */
+void DMA1_Channel1_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel1_IRQn 0 */
+#if (CFG_HW_LPUART1_ENABLED == 1)
+#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
+  HAL_DMA_IRQHandler(&hdma_lpuart1_tx);
+#endif
+#endif
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA1 channel2 global interrupt.
+  */
+void DMA1_Channel2_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel2_IRQn 0 */
+#if (CFG_HW_USART1_ENABLED == 1)
+#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
+  HAL_DMA_IRQHandler(&hdma_usart1_tx);
+#endif
+#endif
+  /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel2_IRQn 1 */
+}
+#endif
+
+/**
+  * @brief This function handles CPU2 SEV interrupt through EXTI line 40 and PWR CPU2 HOLD wake-up interrupt.
+  */
+void C2SEV_PWR_C2H_IRQHandler(void)
+{
+  /* USER CODE BEGIN C2SEV_PWR_C2H_IRQn 0 */
+
+  /* USER CODE END C2SEV_PWR_C2H_IRQn 0 */
+  /* USER CODE BEGIN C2SEV_PWR_C2H_IRQn 1 */
+
+  /* USER CODE END C2SEV_PWR_C2H_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+
+  /* USER CODE END USART1_IRQn 0 */
+#if (CFG_HW_USART1_ENABLED == 1)
+  HAL_UART_IRQHandler(&huart1);
+#endif
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles LPUART1 global interrupt.
+  */
+void LPUART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN LPUART1_IRQn 0 */
+
+  /* USER CODE END LPUART1_IRQn 0 */
+#if (CFG_HW_LPUART1_ENABLED == 1)
+  HAL_UART_IRQHandler(&hlpuart1);
+#endif
+  /* USER CODE BEGIN LPUART1_IRQn 1 */
+
+  /* USER CODE END LPUART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles PWR switching on the fly, end of BLE activity, end of 802.15.4 activity, end of critical radio phase interrupt.
+  */
+void PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler(void)
+{
+  /* USER CODE BEGIN PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQn 0 */
+
+  /* USER CODE END PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQn 0 */
+  /* USER CODE BEGIN PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQn 1 */
+
+  /* USER CODE END PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQn 1 */
+}
+
+/**
+  * @brief This function handles HSEM global interrupt.
+  */
+void HSEM_IRQHandler(void)
+{
+  /* USER CODE BEGIN HSEM_IRQn 0 */
+
+  /* USER CODE END HSEM_IRQn 0 */
+  HAL_HSEM_IRQHandler();
+  /* USER CODE BEGIN HSEM_IRQn 1 */
+
+  /* USER CODE END HSEM_IRQn 1 */
+}
+
+/**
+  * @brief This function handles FPU global interrupt.
+  */
+void FPU_IRQHandler(void)
+{
+  /* USER CODE BEGIN FPU_IRQn 0 */
+
+  /* USER CODE END FPU_IRQn 0 */
+  /* USER CODE BEGIN FPU_IRQn 1 */
+
+  /* USER CODE END FPU_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+void RTC_WKUP_IRQHandler(void)
+{
+  HW_TS_RTC_Wakeup_Handler();
+}
+
+/**
+  * @brief  This function handles EXTI4_IRQ Handler.
+  * @param  None
+  * @retval None
+  */
+void EXTI4_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+
+
+void IPCC_C1_TX_IRQHandler(void)
+{
+  HW_IPCC_Tx_Handler();
+
+  return;
+}
+
+void IPCC_C1_RX_IRQHandler(void)
+{
+  HW_IPCC_Rx_Handler();
+  return;
+}
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/stm_logging.c b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/stm_logging.c
new file mode 100644
index 000000000..ed0b9f432
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/stm_logging.c
@@ -0,0 +1,212 @@
+/**
+ ******************************************************************************
+  * File Name          : stm_logging.c
+  * Description        : This file contains all the defines and functions used 
+  *                     for logging on Application examples.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/**
+ * @file
+ *   This file implements logging functions to be used in Application examples.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "app_conf.h"
+#include "stm_logging.h"
+
+#define LOG_PARSE_BUFFER_SIZE  256U
+
+#define LOG_TIMESTAMP_ENABLE 0
+#define LOG_REGION_ENABLE 1U
+#define LOG_RTT_COLOR_ENABLE 1U
+
+#if (LOG_RTT_COLOR_ENABLE == 1U)
+#define RTT_COLOR_CODE_DEFAULT "\x1b[0m"
+#define RTT_COLOR_CODE_RED     "\x1b[0;91m"
+#define RTT_COLOR_CODE_GREEN   "\x1b[0;92m"
+#define RTT_COLOR_CODE_YELLOW  "\x1b[0;93m"
+#define RTT_COLOR_CODE_CYAN    "\x1b[0;96m"
+
+#else /* LOG_RTT_COLOR_ENABLE == 1 */
+#define RTT_COLOR_CODE_DEFAULT ""
+#define RTT_COLOR_CODE_RED     ""
+#define RTT_COLOR_CODE_GREEN   ""
+#define RTT_COLOR_CODE_YELLOW  ""
+#define RTT_COLOR_CODE_CYAN    ""
+#endif /* LOG_RTT_COLOR_ENABLE == 1 */
+
+#if (CFG_DEBUG_TRACE != 0)
+/**
+ * Function for outputting code region string.
+ *
+ * @param[inout]  aLogString  Pointer to log buffer.
+ * @param[in]     aMaxSize    Maximum size of log buffer.
+ * @param[in]     otLogRegion The region ID.
+ *
+ * @returns  String with a log level color value.
+ */
+static inline uint16_t logRegion(char *aLogString, uint16_t aMaxSize,
+        appliLogRegion_t aLogRegion)
+{
+  char logRegionString[30U];
+
+  switch (aLogRegion)
+  {
+    case APPLI_LOG_REGION_GENERAL:
+      strcpy(logRegionString, "[M4 APPLICATION]");
+      break;
+    case APPLI_LOG_REGION_OPENTHREAD_API:
+      strcpy(logRegionString, "[M4 OPENTHREAD API]");
+      break;
+    case APPLI_LOG_REGION_OT_API_LINK:
+      strcpy(logRegionString, "[M4 LINK API]");
+      break;
+    case APPLI_LOG_REGION_OT_API_INSTANCE:
+      strcpy(logRegionString, "[M4 INSTANCE API]");
+      break;
+    case APPLI_LOG_REGION_OT_API_MESSAGE:
+      strcpy(logRegionString, "[M4 MESSAGE API]");
+      break;
+    default:
+      strcpy(logRegionString, "[M4]");
+      break;
+  }
+
+  return snprintf(aLogString, aMaxSize, "%s ", logRegionString);
+}
+#endif /* CFG_DEBUG_TRACE */
+
+#if (LOG_RTT_COLOR_ENABLE == 1U)
+#if (CFG_DEBUG_TRACE != 0)
+/**
+ * Function for getting color of a given level log.
+ *
+ * @param[in]  aLogLevel The log level.
+ *
+ * @returns  String with a log level color value.
+ */
+static inline const char *levelToString(appliLogLevel_t aLogLevel)
+{
+  switch (aLogLevel)
+  {
+  case LOG_LEVEL_CRIT:
+    return RTT_COLOR_CODE_RED;
+
+  case LOG_LEVEL_WARN:
+    return RTT_COLOR_CODE_YELLOW;
+
+  case LOG_LEVEL_INFO:
+    return RTT_COLOR_CODE_GREEN;
+
+  case LOG_LEVEL_DEBG:
+  default:
+    return RTT_COLOR_CODE_DEFAULT;
+  }
+}
+#endif /* CFG_DEBUG_TRACE */
+
+#if (CFG_DEBUG_TRACE != 0)
+/**
+ * Function for printing log level.
+ *
+ * @param[inout]  aLogString  Pointer to log buffer.
+ * @param[in]     aMaxSize    Maximum size of log buffer.
+ * @param[in]     aLogLevel   Log level.
+ *
+ * @returns  Number of bytes successfully written to the log buffer.
+ */
+static inline uint16_t logLevel(char *aLogString, uint16_t aMaxSize,
+                                appliLogLevel_t aLogLevel)
+{
+  return snprintf(aLogString, aMaxSize, "%s", levelToString(aLogLevel));
+}
+#endif /* CFG_DEBUG_TRACE */
+#endif /* LOG_RTT_COLOR_ENABLE */
+
+#if (LOG_TIMESTAMP_ENABLE == 1U)
+/**
+ * Function for printing actual timestamp.
+ *
+ * @param[inout]  aLogString Pointer to the log buffer.
+ * @param[in]     aMaxSize   Maximum size of the log buffer.
+ *
+ * @returns  Number of bytes successfully written to the log buffer.
+ */
+static inline uint16_t logTimestamp(char *aLogString, uint16_t aMaxSize)
+{
+  return snprintf(aLogString, aMaxSize, "%s[%010ld]", RTT_COLOR_CODE_DEFAULT,
+                  otPlatAlarmMilliGetNow());
+}
+#endif /* LOG_TIMESTAMP_ENABLE */
+
+/**
+ * Function for printing application log
+ *
+ * @param[in]     aLogLevel   Log level.
+ * @param[in]     aLogRegion  The region ID.
+ * @param[in]     aFormat     User string format.
+ *
+ * @returns  Number of bytes successfully written to the log buffer.
+ */
+void logApplication(appliLogLevel_t aLogLevel, appliLogRegion_t aLogRegion, const char *aFormat, ...)
+{
+#if (CFG_DEBUG_TRACE != 0) /* Since the traces are disabled, there is nothing to print */
+  uint16_t length = 0;
+  char logString[LOG_PARSE_BUFFER_SIZE + 1U];
+
+#if (LOG_TIMESTAMP_ENABLE == 1U)
+  length += logTimestamp(logString, LOG_PARSE_BUFFER_SIZE);
+#endif
+
+#if (LOG_RTT_COLOR_ENABLE == 1U)
+  /* Add level information */
+  length += logLevel(&logString[length], (LOG_PARSE_BUFFER_SIZE - length),
+      aLogLevel);
+#endif
+
+#if (LOG_REGION_ENABLE == 1U)
+  /* Add Region information */
+  length += logRegion(&logString[length], (LOG_PARSE_BUFFER_SIZE - length),
+      aLogRegion);
+#endif
+
+  /* Parse user string */
+  va_list paramList;
+  va_start(paramList, aFormat);
+  length += vsnprintf(&logString[length], (LOG_PARSE_BUFFER_SIZE - length),
+      aFormat, paramList);
+  logString[length++] = '\r';
+  logString[length++] = '\n';
+  logString[length++] = 0;
+  va_end(paramList);
+
+  if (aLogLevel <= APPLI_CONFIG_LOG_LEVEL)
+  {
+    printf("%s", logString);
+  }
+  else
+  {
+    /* Print nothing */
+  }
+#endif /* CFG_DEBUG_TRACE */
+}
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/Core/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/Project.eww
new file mode 100644
index 000000000..8370d517a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\Thread_Cli_Cmd.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/Thread_Cli_Cmd.ewd b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/Thread_Cli_Cmd.ewd
new file mode 100644
index 000000000..2d8535df9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/Thread_Cli_Cmd.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		Thread_Cli_Cmd_LittleDory
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/Thread_Cli_Cmd.ewp b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/Thread_Cli_Cmd.ewp
new file mode 100644
index 000000000..3b2a2b2f1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/Thread_Cli_Cmd.ewp
@@ -0,0 +1,1305 @@
+
+
+  3
+  
+    Thread_Cli_Cmd_LittleDory
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        Core
+        
+          $PROJ_DIR$/../Core/Src/main.c
+        
+        
+          $PROJ_DIR$/../Core/Src/stm_logging.c
+        
+        
+          $PROJ_DIR$/../Core/Src/app_entry.c
+        
+        
+          $PROJ_DIR$/../Core/Src/stm32_lpm_if.c
+        
+        
+          $PROJ_DIR$/../Core/Src/hw_timerserver.c
+        
+        
+          $PROJ_DIR$/../Core/Src/hw_uart.c
+        
+        
+          $PROJ_DIR$/../Core/Src/stm32wbxx_it.c
+        
+        
+          $PROJ_DIR$/../Core/Src/stm32wbxx_hal_msp.c
+        
+      
+      
+        STM32_WPAN
+        
+          Target
+          
+            $PROJ_DIR$/../STM32_WPAN/Target/hw_ipcc.c
+          
+        
+        
+          App
+          
+            $PROJ_DIR$/../STM32_WPAN/App/app_thread.c
+          
+        
+      
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE\nucleo_wb35ce.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Core/Src/system_stm32wbxx.c
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+  
+  
+    Middlewares
+    
+      STM32_WPAN
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/shci_tl_if.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl_mbox.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/shci/shci.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/utilities/dbg_trace.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/utilities/otp.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/utilities/stm_list.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/utilities/stm_queue.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl_thread_hci.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/shci_tl.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/channel_manager.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/channel_monitor.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/child_supervision.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/coap.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/commissioner.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/crypto.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/dataset.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/dataset_ftd.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/dhcp6_client.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/dhcp6_server.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/diag.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/dns.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/icmp6.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/instance.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/ip6.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/jam_detection.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/joiner.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/link.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/link_raw.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/message.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/netdata.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/openthread.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/openthread_api_wb.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/server.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/tasklet.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/thread.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/thread_ftd.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/udp.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_WPAN/thread/openthread/core/openthread_api/radio.c
+      
+    
+  
+    
+        Utilities
+        
+            $PROJ_DIR$\..\..\..\..\..\..\Utilities\lpm\tiny_lpm\stm32_lpm.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\..\..\Utilities\sequencer\stm32_seq.c
+        
+    
+	
+        Doc
+        
+            $PROJ_DIR$\..\readme.txt
+        
+    
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..3bf72d404
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/STM32_WPAN/App/app_thread.c b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/STM32_WPAN/App/app_thread.c
new file mode 100644
index 000000000..8f7ce4db0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/STM32_WPAN/App/app_thread.c
@@ -0,0 +1,747 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : App/app_thread.c
+  * Description        : Thread Application.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "utilities_common.h"
+#include "app_entry.h"
+#include "dbg_trace.h"
+#include "app_thread.h"
+#include "stm32wbxx_core_interface_def.h"
+#include "openthread_api_wb.h"
+#include "shci.h"
+#include "stm_logging.h"
+#include "stm32_lpm.h"
+#include "stm32_seq.h"
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+#include "vcp.h"
+#include "vcp_conf.h"
+#endif /* (CFG_USB_INTERFACE_ENABLE != 0) */
+
+/* Private includes -----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+
+typedef PACKED_STRUCT
+{
+  uint8_t ble_dtb_cfg;
+  uint8_t reserved[3];
+} APPD_GeneralConfig_t;
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+#define C_SIZE_CMD_STRING       256U
+
+/* USER CODE BEGIN PD */
+
+/* Debug */
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private function prototypes -----------------------------------------------*/
+static void APP_THREAD_CheckWirelessFirmwareInfo(void);
+static void APP_THREAD_DeviceConfig(void);
+static void APP_THREAD_StateNotif(uint32_t NotifFlags, void *pContext);
+static void APP_THREAD_TraceError(const char * pMess, uint32_t ErrCode);
+#if (CFG_FULL_LOW_POWER == 0)
+static void Send_CLI_To_M0(void);
+#endif /* (CFG_FULL_LOW_POWER == 0) */
+static void Send_CLI_Ack_For_OT(void);
+static void HostTxCb( void );
+static void Wait_Getting_Ack_From_M0(void);
+static void Receive_Ack_From_M0(void);
+static void Receive_Notification_From_M0(void);
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+static uint32_t ProcessCmdString(uint8_t* buf , uint32_t len);
+#else
+#if (CFG_FULL_LOW_POWER == 0)
+static void RxCpltCallback(void);
+#endif /* (CFG_FULL_LOW_POWER == 0) */
+#endif /* (CFG_USB_INTERFACE_ENABLE != 0) */
+
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private variables -----------------------------------------------*/
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+static uint8_t TmpString[C_SIZE_CMD_STRING];
+static uint8_t VcpRxBuffer[sizeof(TL_CmdSerial_t)];        /* Received Data over USB are stored in this buffer */
+static uint8_t VcpTxBuffer[sizeof(TL_EvtPacket_t) + 254U]; /* Transmit buffer over USB */
+#else
+#if (CFG_FULL_LOW_POWER == 0)
+static uint8_t aRxBuffer[C_SIZE_CMD_STRING];
+#endif /* (CFG_FULL_LOW_POWER == 0) */
+#endif /* (CFG_USB_INTERFACE_ENABLE != 0) */
+
+#if (CFG_FULL_LOW_POWER == 0)
+static uint8_t CommandString[C_SIZE_CMD_STRING];
+#endif /* (CFG_FULL_LOW_POWER == 0) */
+static __IO uint16_t indexReceiveChar = 0;
+static __IO uint16_t CptReceiveCmdFromUser = 0;
+
+static TL_CmdPacket_t *p_thread_otcmdbuffer;
+static TL_EvtPacket_t *p_thread_notif_M0_to_M4;
+static __IO uint32_t  CptReceiveMsgFromM0 = 0;
+PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static TL_TH_Config_t ThreadConfigBuffer;
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static TL_CmdPacket_t ThreadOtCmdBuffer;
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t ThreadNotifRspEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255U];
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static TL_CmdPacket_t ThreadCliCmdBuffer;
+
+/* USER CODE BEGIN PV */
+
+/* Debug */
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig;
+/* USER CODE END PV */
+
+/* Functions Definition ------------------------------------------------------*/
+
+void APP_THREAD_Init( void )
+{
+  /* USER CODE BEGIN APP_THREAD_INIT_1 */
+
+  /* USER CODE END APP_THREAD_INIT_1 */
+
+  SHCI_CmdStatus_t ThreadInitStatus;
+  
+  /* Check the compatibility with the Coprocessor Wireless Firmware loaded */
+  APP_THREAD_CheckWirelessFirmwareInfo();
+
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+  VCP_Init(&VcpTxBuffer[0], &VcpRxBuffer[0]);
+#endif /* (CFG_USB_INTERFACE_ENABLE != 0) */
+
+  /* Register cmdbuffer */
+  APP_THREAD_RegisterCmdBuffer(&ThreadOtCmdBuffer);
+
+  /**
+   * Do not allow standby in the application
+   */
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP_THREAD, UTIL_LPM_DISABLE);
+
+  /* Init config buffer and call TL_THREAD_Init */
+  APP_THREAD_TL_THREAD_INIT();
+
+  /* Configure UART for sending CLI command from M4 */
+  APP_THREAD_Init_UART_CLI();
+
+  /* Send Thread start system cmd to M0 */
+  ThreadInitStatus = SHCI_C2_THREAD_Init();
+  
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ThreadInitStatus);
+
+  /* Register task */
+  /* Create the different tasks */
+  UTIL_SEQ_RegTask( 1<<(uint32_t)CFG_TASK_MSG_FROM_M0_TO_M4, UTIL_SEQ_RFU, APP_THREAD_ProcessMsgM0ToM4);
+
+  /* USER CODE BEGIN INIT TASKS */
+
+  /* USER CODE END INIT TASKS */
+
+  /* Initialize and configure the Thread device */
+  APP_THREAD_DeviceConfig();
+
+  /* USER CODE BEGIN APP_THREAD_INIT_2 */
+  /* Debug Configuration */
+  APPD_TracesConfig.thread_config = 0x1;
+
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)NULL,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)NULL,
+    0,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    0}
+  };
+
+  SHCI_C2_DEBUG_Init(&DebugCmdPacket);
+  /* USER CODE END APP_THREAD_INIT_2 */
+}
+
+/**
+  * @brief  Trace the error or the warning reported.
+  * @param  ErrId :
+  * @param  ErrCode
+  * @retval None
+  */
+void APP_THREAD_Error(uint32_t ErrId, uint32_t ErrCode)
+{
+  /* USER CODE BEGIN APP_THREAD_Error_1 */
+
+  /* USER CODE END APP_THREAD_Error_1 */
+  switch(ErrId)
+  {
+  case ERR_REC_MULTI_MSG_FROM_M0 :
+    APP_THREAD_TraceError("ERROR : ERR_REC_MULTI_MSG_FROM_M0 ", ErrCode);
+    break;
+  case ERR_THREAD_SET_STATE_CB :
+    APP_THREAD_TraceError("ERROR : ERR_THREAD_SET_STATE_CB ",ErrCode);
+    break;
+  case ERR_THREAD_ERASE_PERSISTENT_INFO :
+    APP_THREAD_TraceError("ERROR : ERR_THREAD_ERASE_PERSISTENT_INFO ",ErrCode);
+    break;
+  case ERR_THREAD_CHECK_WIRELESS :
+    APP_THREAD_TraceError("ERROR : ERR_THREAD_CHECK_WIRELESS ",ErrCode);
+    break;
+  /* USER CODE BEGIN APP_THREAD_Error_2 */
+
+  /* USER CODE END APP_THREAD_Error_2 */
+  default :
+    APP_THREAD_TraceError("ERROR Unknown ", 0);
+    break;
+  }
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+
+/**
+ * @brief Thread initialization.
+ * @param  None
+ * @retval None
+ */
+static void APP_THREAD_DeviceConfig(void)
+{
+  otError error;
+  error = otSetStateChangedCallback(NULL, APP_THREAD_StateNotif, NULL);
+  if (error != OT_ERROR_NONE)
+  {
+    APP_THREAD_Error((uint32_t)ERR_THREAD_SET_STATE_CB, (uint32_t)ERR_INTERFACE_FATAL);
+  }
+
+  /* USER CODE BEGIN DEVICECONFIG */
+
+  /* USER CODE END DEVICECONFIG */
+}
+
+/**
+ * @brief Thread notification when the state changes.
+ * @param  aFlags  : Define the item that has been modified
+ *         aContext: Context
+ *
+ * @retval None
+ */
+static void APP_THREAD_StateNotif(uint32_t NotifFlags, void *pContext)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(pContext);
+
+  /* USER CODE BEGIN APP_THREAD_STATENOTIF */
+
+  /* USER CODE END APP_THREAD_STATENOTIF */
+
+  if ((NotifFlags & (uint32_t)OT_CHANGED_THREAD_ROLE) == (uint32_t)OT_CHANGED_THREAD_ROLE)
+  {
+    switch (otThreadGetDeviceRole(NULL))
+    {
+    case OT_DEVICE_ROLE_DISABLED:
+      /* USER CODE BEGIN OT_DEVICE_ROLE_DISABLED */
+      BSP_LED_Off(LED2);
+      BSP_LED_Off(LED3);
+      /* USER CODE END OT_DEVICE_ROLE_DISABLED */
+      break;
+    case OT_DEVICE_ROLE_DETACHED:
+      /* USER CODE BEGIN OT_DEVICE_ROLE_DETACHED */
+      BSP_LED_Off(LED2);
+      BSP_LED_Off(LED3);
+      /* USER CODE END OT_DEVICE_ROLE_DETACHED */
+      break;
+    case OT_DEVICE_ROLE_CHILD:
+      /* USER CODE BEGIN OT_DEVICE_ROLE_CHILD */
+      BSP_LED_Off(LED2);
+      BSP_LED_On(LED3);
+      /* USER CODE END OT_DEVICE_ROLE_CHILD */
+      break;
+    case OT_DEVICE_ROLE_ROUTER :
+      /* USER CODE BEGIN OT_DEVICE_ROLE_ROUTER */
+      BSP_LED_Off(LED2);
+      BSP_LED_On(LED3);
+      /* USER CODE END OT_DEVICE_ROLE_ROUTER */
+      break;
+    case OT_DEVICE_ROLE_LEADER :
+      /* USER CODE BEGIN OT_DEVICE_ROLE_LEADER */
+      BSP_LED_On(LED2);
+      BSP_LED_Off(LED3);
+      /* USER CODE END OT_DEVICE_ROLE_LEADER */
+      break;
+    default:
+      /* USER CODE BEGIN DEFAULT */
+      BSP_LED_Off(LED2);
+      BSP_LED_Off(LED3);
+      /* USER CODE END DEFAULT */
+      break;
+    }
+  }
+}
+
+/**
+  * @brief  Warn the user that an error has occurred.In this case,
+  *         the LEDs on the Board will start blinking.
+  *
+  * @param  pMess  : Message associated to the error.
+  * @param  ErrCode: Error code associated to the module (OpenThread or other module if any)
+  * @retval None
+  */
+static void APP_THREAD_TraceError(const char * pMess, uint32_t ErrCode)
+{
+  /* USER CODE BEGIN TRACE_ERROR */
+  APP_DBG("**** Fatal error = %s (Err = %d)", pMess, ErrCode);
+  while(1U == 1U)
+  {
+    BSP_LED_Toggle(LED1);
+    HAL_Delay(500U);
+    BSP_LED_Toggle(LED2);
+    HAL_Delay(500U);
+    BSP_LED_Toggle(LED3);
+    HAL_Delay(500U);
+  }
+  /* USER CODE END TRACE_ERROR */
+}
+
+/**
+ * @brief Check if the Coprocessor Wireless Firmware loaded supports Thread
+ *        and display associated informations
+ * @param  None
+ * @retval None
+ */
+static void APP_THREAD_CheckWirelessFirmwareInfo(void)
+{
+  WirelessFwInfo_t wireless_info_instance;
+  WirelessFwInfo_t* p_wireless_info = &wireless_info_instance;
+
+  if (SHCI_GetWirelessFwInfo(p_wireless_info) != SHCI_Success)
+  {
+    APP_THREAD_Error((uint32_t)ERR_THREAD_CHECK_WIRELESS, (uint32_t)ERR_INTERFACE_FATAL);
+  }
+  else
+  {
+    APP_DBG("**********************************************************");
+    APP_DBG("WIRELESS COPROCESSOR FW:");
+    /* Print version */
+    APP_DBG("VERSION ID = %d.%d.%d", p_wireless_info->VersionMajor, p_wireless_info->VersionMinor, p_wireless_info->VersionSub);
+
+    switch(p_wireless_info->StackType)
+    {
+    case INFO_STACK_TYPE_THREAD_FTD :
+      APP_DBG("FW Type : Thread FTD");
+      break;
+    case INFO_STACK_TYPE_THREAD_MTD :
+      APP_DBG("FW Type : Thread MTD");
+      break;
+    case INFO_STACK_TYPE_BLE_THREAD_FTD_STATIC :
+      APP_DBG("FW Type : Static Concurrent Mode BLE/Thread");
+      break;
+    default :
+      /* No Thread device supported ! */
+      APP_THREAD_Error((uint32_t)ERR_THREAD_CHECK_WIRELESS, (uint32_t)ERR_INTERFACE_FATAL);
+      break;
+    }
+    APP_DBG("**********************************************************");
+  }
+}
+/* USER CODE BEGIN FD_LOCAL_FUNCTIONS */
+
+/* USER CODE END FD_LOCAL_FUNCTIONS */
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+
+void APP_THREAD_RegisterCmdBuffer(TL_CmdPacket_t* p_buffer)
+{
+  p_thread_otcmdbuffer = p_buffer;
+}
+
+Thread_OT_Cmd_Request_t* THREAD_Get_OTCmdPayloadBuffer(void)
+{
+  return (Thread_OT_Cmd_Request_t*)p_thread_otcmdbuffer->cmdserial.cmd.payload;
+}
+
+Thread_OT_Cmd_Request_t* THREAD_Get_OTCmdRspPayloadBuffer(void)
+{
+  return (Thread_OT_Cmd_Request_t*)((TL_EvtPacket_t *)p_thread_otcmdbuffer)->evtserial.evt.payload;
+}
+
+Thread_OT_Cmd_Request_t* THREAD_Get_NotificationPayloadBuffer(void)
+{
+  return (Thread_OT_Cmd_Request_t*)(p_thread_notif_M0_to_M4)->evtserial.evt.payload;
+}
+
+/**
+ * @brief  This function is used to transfer the Ot commands from the
+ *         M4 to the M0.
+ *
+ * @param   None
+ * @return  None
+ */
+void Ot_Cmd_Transfer(void)
+{
+  /* OpenThread OT command cmdcode range 0x280 .. 0x3DF = 352 */
+  p_thread_otcmdbuffer->cmdserial.cmd.cmdcode = 0x280U;
+  /* Size = otCmdBuffer->Size (Number of OT cmd arguments : 1 arg = 32bits so multiply by 4 to get size in bytes)
+   * + ID (4 bytes) + Size (4 bytes) */
+  uint32_t l_size = ((Thread_OT_Cmd_Request_t*)(p_thread_otcmdbuffer->cmdserial.cmd.payload))->Size * 4U + 8U;
+  p_thread_otcmdbuffer->cmdserial.cmd.plen = l_size;
+
+  TL_OT_SendCmd();
+
+  /* Wait completion of cmd */
+  Wait_Getting_Ack_From_M0();
+}
+
+/**
+ * @brief  This function is called when acknowledge from OT command is received from the M0+.
+ *
+ * @param   Otbuffer : a pointer to TL_EvtPacket_t
+ * @return  None
+ */
+void TL_OT_CmdEvtReceived( TL_EvtPacket_t * Otbuffer )
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Otbuffer);
+
+  Receive_Ack_From_M0();
+}
+
+/**
+ * @brief  This function is called when notification from M0+ is received.
+ *
+ * @param   Notbuffer : a pointer to TL_EvtPacket_t
+ * @return  None
+ */
+void TL_THREAD_NotReceived( TL_EvtPacket_t * Notbuffer )
+{
+  p_thread_notif_M0_to_M4 = Notbuffer;
+
+  Receive_Notification_From_M0();
+}
+
+/**
+  * @brief  This function is called before sending any ot command to the M0
+  *         core. The purpose of this function is to be able to check if
+  *         there are no notifications coming from the M0 core which are
+  *         pending before sending a new ot command.
+  * @param  None
+  * @retval None
+  */
+void Pre_OtCmdProcessing(void)
+{
+  UTIL_SEQ_WaitEvt(EVENT_SYNCHRO_BYPASS_IDLE);
+}
+
+/**
+  * @brief  This function waits for getting an acknowledgment from the M0.
+  *
+  * @param  None
+  * @retval None
+  */
+static void Wait_Getting_Ack_From_M0(void)
+{
+  UTIL_SEQ_WaitEvt(EVENT_ACK_FROM_M0_EVT);
+}
+
+/**
+  * @brief  Receive an acknowledgment from the M0+ core.
+  *         Each command send by the M4 to the M0 are acknowledged.
+  *         This function is called under interrupt.
+  * @param  None
+  * @retval None
+  */
+static void Receive_Ack_From_M0(void)
+{
+  UTIL_SEQ_SetEvt(EVENT_ACK_FROM_M0_EVT);
+}
+
+/**
+  * @brief  Receive a notification from the M0+ through the IPCC.
+  *         This function is called under interrupt.
+  * @param  None
+  * @retval None
+  */
+static void Receive_Notification_From_M0(void)
+{
+  CptReceiveMsgFromM0++;
+  UTIL_SEQ_SetTask(TASK_MSG_FROM_M0_TO_M4,CFG_SCH_PRIO_0);
+}
+
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+#else
+#if (CFG_FULL_LOW_POWER == 0)
+static void RxCpltCallback(void)
+{
+  /* Filling buffer and wait for '\r' char */
+  if (indexReceiveChar < C_SIZE_CMD_STRING)
+  {
+    CommandString[indexReceiveChar++] = aRxBuffer[0];
+    if (aRxBuffer[0] == '\r')
+    {
+      CptReceiveCmdFromUser = 1U;
+
+      /* UART task scheduling*/
+      UTIL_SEQ_SetTask(1U << CFG_TASK_SEND_CLI_TO_M0, CFG_SCH_PRIO_0);
+    }
+  }
+
+  /* Once a character has been sent, put back the device in reception mode */
+  HW_UART_Receive_IT(CFG_CLI_UART, aRxBuffer, 1U, RxCpltCallback);
+}
+#endif /* (CFG_FULL_LOW_POWER == 0) */
+#endif /* (CFG_USB_INTERFACE_ENABLE != 0) */
+
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+/**
+ * @brief Process the command strings.
+ *        As soon as a complete command string has been received, the task
+ *        in charge of sending the command to the M0 is scheduled
+ * @param  None
+ * @retval None
+ */
+static uint32_t  ProcessCmdString( uint8_t* buf , uint32_t len )
+{
+  uint32_t i,j,tmp_start;
+  tmp_start = 0;
+  uint32_t res = 0;
+
+  i= 0;
+  while ((buf[i] != '\r') && (i < len))
+  {
+    i++;
+  }
+
+  if (i != len)
+  {
+    memcpy(CommandString, buf,(i+1));
+    indexReceiveChar = i + 1U; /* Length of the buffer containing the command string */
+    UTIL_SEQ_SetTask(1U << CFG_TASK_SEND_CLI_TO_M0, CFG_SCH_PRIO_0);
+    tmp_start = i;
+    for (j = 0; j < (len - tmp_start - 1U) ; j++)
+    {
+      buf[j] = buf[tmp_start + j + 1U];
+    }
+    res = len - tmp_start - 1U;
+  }
+  else
+  {
+    res = len;
+  }
+  return res; /* Remaining characters in the temporary buffer */
+}
+#endif/* (CFG_USB_INTERFACE_ENABLE != 0) */
+
+#if (CFG_FULL_LOW_POWER == 0)
+/**
+ * @brief Process sends receive CLI command to M0.
+ * @param  None
+ * @retval None
+ */
+static void Send_CLI_To_M0(void)
+{
+  memset(ThreadCliCmdBuffer.cmdserial.cmd.payload, 0x0U, 255U);
+  memcpy(ThreadCliCmdBuffer.cmdserial.cmd.payload, CommandString, indexReceiveChar);
+  ThreadCliCmdBuffer.cmdserial.cmd.plen = indexReceiveChar;
+  ThreadCliCmdBuffer.cmdserial.cmd.cmdcode = 0x0;
+
+  /* Clear receive buffer, character counter and command complete */
+  CptReceiveCmdFromUser = 0;
+  indexReceiveChar = 0;
+  memset(CommandString, 0, C_SIZE_CMD_STRING);
+
+  TL_CLI_SendCmd();
+}
+#endif /* (CFG_FULL_LOW_POWER == 0) */
+
+/**
+ * @brief Send notification for CLI TL Channel.
+ * @param  None
+ * @retval None
+ */
+static void Send_CLI_Ack_For_OT(void)
+{
+
+  /* Notify M0 that characters have been sent to UART */
+  TL_THREAD_CliSendAck();
+}
+
+/**
+ * @brief Perform initialization of CLI UART interface.
+ * @param  None
+ * @retval None
+ */
+void APP_THREAD_Init_UART_CLI(void)
+{
+#if (CFG_FULL_LOW_POWER == 0)
+  UTIL_SEQ_RegTask( 1<cmdserial.cmd.plen;
+
+  /* WORKAROUND: if string to output is "> " then respond directly to M0 and do not output it */
+  if (strcmp((const char *)l_CliBuffer->cmdserial.cmd.payload, "> ") != 0)
+  {
+    /* Write to CLI UART */
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+    VCP_SendData( l_CliBuffer->cmdserial.cmd.payload, l_size, HostTxCb);
+#else
+    HW_UART_Transmit_IT(CFG_CLI_UART, l_CliBuffer->cmdserial.cmd.payload, l_size, HostTxCb);
+#endif /*USAGE_OF_VCP */
+  }
+  else
+  {
+    Send_CLI_Ack_For_OT();
+  }
+}
+
+/**
+ * @brief  End of transfer callback for CLI UART sending.
+ *
+ * @param   Notbuffer : a pointer to TL_EvtPacket_t
+ * @return  None
+ */
+void HostTxCb(void)
+{
+  Send_CLI_Ack_For_OT();
+}
+
+/**
+ * @brief Process the messages coming from the M0.
+ * @param  None
+ * @retval None
+ */
+void APP_THREAD_ProcessMsgM0ToM4(void)
+{
+  if (CptReceiveMsgFromM0 != 0)
+  {
+    /* If CptReceiveMsgFromM0 is > 1. it means that we did not serve all the events from the radio */
+    if (CptReceiveMsgFromM0 > 1U)
+    {
+      APP_THREAD_Error(ERR_REC_MULTI_MSG_FROM_M0, 0);
+    }
+    else
+    {
+      OpenThread_CallBack_Processing();
+    }
+    /* Reset counter */
+    CptReceiveMsgFromM0 = 0;
+  }
+}
+
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+/**
+ * @brief  This function is called when thereare some data coming
+ *         from the Hyperterminal via the USB port
+ *         Data received over USB OUT endpoint are sent over CDC interface
+ *         through this function.
+ * @param  Buf: Buffer of data received
+ * @param  Len: Number of data received (in bytes)
+ * @retval Number of characters remaining in the buffer and not yet processed
+ */
+void VCP_DataReceived(uint8_t* Buf , uint32_t *Len)
+{
+  uint32_t i,flag_continue_checking = TRUE;
+  uint32_t char_remaining = 0;
+  static uint32_t len_total = 0;
+
+  /* Copy the characteres in the temporary buffer */
+  for (i = 0; i < *Len; i++)
+  {
+    TmpString[len_total++] = Buf[i];
+  }
+
+  /* Process the buffer commands one by one     */
+  /* A command is limited by a \r caracaters    */
+  while (flag_continue_checking == TRUE)
+  {
+    char_remaining = ProcessCmdString(TmpString,len_total);
+    /* If char_remaining is equal to len_total, it means that the command string is not yet
+     * completed.
+     * If char_remaining is equal to 0, it means that the command string has
+     * been entirely processed.
+     */
+    if ((char_remaining == 0) || (char_remaining == len_total))
+    {
+      flag_continue_checking = FALSE;
+    }
+    len_total = char_remaining;
+  }
+}
+#endif /* (CFG_USB_INTERFACE_ENABLE != 0) */
+
+/* USER CODE BEGIN FD_WRAP_FUNCTIONS */
+
+/* USER CODE END FD_WRAP_FUNCTIONS */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/STM32_WPAN/App/app_thread.h b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/STM32_WPAN/App/app_thread.h
new file mode 100644
index 000000000..b5a20ccc3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/STM32_WPAN/App/app_thread.h
@@ -0,0 +1,105 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * File Name          : App/app_thread.h
+  * Description        : Header for Thread Application.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef APP_THREAD_H
+#define APP_THREAD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Private includes ----------------------------------------------------------*/
+#include "tl.h"
+#include "stm32wbxx_core_interface_def.h"
+#include "tl_thread_hci.h"
+
+/* OpenThread Library */
+#include OPENTHREAD_CONFIG_FILE
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Thread application generic defines */
+/*------------------------------------*/
+typedef enum
+{
+  APP_THREAD_LIMITED,
+  APP_THREAD_FULL,
+} APP_THREAD_InitMode_t;
+
+/* Application errors                 */
+/*------------------------------------*/
+
+/*
+ *  List of all errors tracked by the Thread application
+ *  running on M4. Some of these errors may be fatal
+ *  or just warnings
+ */
+typedef enum
+{
+  ERR_REC_MULTI_MSG_FROM_M0,
+  ERR_THREAD_SET_STATE_CB,
+  ERR_THREAD_ERASE_PERSISTENT_INFO,
+/* USER CODE BEGIN ERROR_APPLI_ENUM */
+
+/* USER CODE END ERROR_APPLI_ENUM */
+  ERR_THREAD_CHECK_WIRELESS
+  } ErrAppliIdEnum_t;
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ------------------------------------------------------- */
+void APP_THREAD_Init( void );
+void APP_THREAD_Error(uint32_t ErrId, uint32_t ErrCode);
+void APP_THREAD_RegisterCmdBuffer(TL_CmdPacket_t* p_buffer);
+void APP_THREAD_ProcessMsgM0ToM4(void);
+void APP_THREAD_Init_UART_CLI(void);
+void APP_THREAD_TL_THREAD_INIT(void);
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* APP_THREAD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/STM32_WPAN/Target/hw_ipcc.c b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/STM32_WPAN/Target/hw_ipcc.c
new file mode 100644
index 000000000..a0d8b3b5b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/STM32_WPAN/Target/hw_ipcc.c
@@ -0,0 +1,523 @@
+/**
+ ******************************************************************************
+  * File Name          : Target/hw_ipcc.c
+  * Description        : Hardware IPCC source file for STM32WPAN Middleware.
+  *
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+#include "mbox_def.h"
+
+/* Global variables ---------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+#define HW_IPCC_TX_PENDING( channel ) ( !(LL_C1_IPCC_IsActiveFlag_CHx( IPCC, channel )) ) &&  (((~(IPCC->C1MR)) & (channel << 16U)))
+#define HW_IPCC_RX_PENDING( channel )  (LL_C2_IPCC_IsActiveFlag_CHx( IPCC, channel )) && (((~(IPCC->C1MR)) & (channel << 0U)))
+
+/* Private macros ------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static void (*FreeBufCb)( void );
+
+/* Private function prototypes -----------------------------------------------*/
+static void HW_IPCC_BLE_EvtHandler( void );
+static void HW_IPCC_BLE_AclDataEvtHandler( void );
+static void HW_IPCC_MM_FreeBufHandler( void );
+static void HW_IPCC_SYS_CmdEvtHandler( void );
+static void HW_IPCC_SYS_EvtHandler( void );
+static void HW_IPCC_TRACES_EvtHandler( void );
+
+#ifdef THREAD_WB
+static void HW_IPCC_OT_CmdEvtHandler( void );
+static void HW_IPCC_THREAD_NotEvtHandler( void );
+static void HW_IPCC_THREAD_CliNotEvtHandler( void );
+#endif
+
+#ifdef MAC_802_15_4_WB
+static void HW_IPCC_MAC_802_15_4_CmdEvtHandler( void );
+static void HW_IPCC_MAC_802_15_4_NotEvtHandler( void );
+#endif
+
+#ifdef ZIGBEE_WB
+static void HW_IPCC_ZIGBEE_CmdEvtHandler( void );
+static void HW_IPCC_ZIGBEE_StackNotifEvtHandler( void );
+static void HW_IPCC_ZIGBEE_CliNotifEvtHandler( void );
+#endif
+
+/* Public function definition -----------------------------------------------*/
+
+/******************************************************************************
+ * INTERRUPT HANDLER
+ ******************************************************************************/
+void HW_IPCC_Rx_Handler( void )
+{
+  if (HW_IPCC_RX_PENDING( HW_IPCC_SYSTEM_EVENT_CHANNEL ))
+  {
+      HW_IPCC_SYS_EvtHandler();
+  }
+#ifdef MAC_802_15_4_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_MAC_802_15_4_NotEvtHandler();
+  }
+#endif /* MAC_802_15_4_WB */
+#ifdef THREAD_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_THREAD_NotEvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_THREAD_CliNotEvtHandler();
+  }
+#endif /* THREAD_WB */
+#ifdef ZIGBEE_WB
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
+  {
+    HW_IPCC_ZIGBEE_StackNotifEvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
+  {
+      HW_IPCC_ZIGBEE_CliNotifEvtHandler();
+  }
+#endif /* ZIGBEE_WB */
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_BLE_EVENT_CHANNEL ))
+  {
+    HW_IPCC_BLE_EvtHandler();
+  }
+  else if (HW_IPCC_RX_PENDING( HW_IPCC_TRACES_CHANNEL ))
+  {
+    HW_IPCC_TRACES_EvtHandler();
+  }
+
+  return;
+}
+
+void HW_IPCC_Tx_Handler( void )
+{
+  if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_SYS_CmdEvtHandler();
+  }
+#ifdef MAC_802_15_4_WB
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_MAC_802_15_4_CmdEvtHandler();
+  }
+#endif /* MAC_802_15_4_WB */
+#ifdef THREAD_WB
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_OT_CmdEvtHandler();
+  }
+#endif /* THREAD_WB */
+#ifdef ZIGBEE_WB
+  if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
+  {
+      HW_IPCC_ZIGBEE_CmdEvtHandler();
+  }
+#endif /* ZIGBEE_WB */
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
+  {
+    HW_IPCC_SYS_CmdEvtHandler();
+  }
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ))
+  {
+    HW_IPCC_MM_FreeBufHandler();
+  }
+  else if (HW_IPCC_TX_PENDING( HW_IPCC_HCI_ACL_DATA_CHANNEL ))
+  {
+    HW_IPCC_BLE_AclDataEvtHandler();
+  }
+
+  return;
+}
+/******************************************************************************
+ * GENERAL
+ ******************************************************************************/
+void HW_IPCC_Enable( void )
+{
+  /**
+   * When the device is out of standby, it is required to use the EXTI mechanism to wakeup CPU2
+   */
+  LL_C2_EXTI_EnableEvent_32_63( LL_EXTI_LINE_41 );
+  LL_EXTI_EnableRisingTrig_32_63( LL_EXTI_LINE_41 );
+
+  /**
+   * In case the SBSFU is implemented, it may have already set the C2BOOT bit to startup the CPU2.
+   * In that case, to keep the mechanism transparent to the user application, it shall call the system command
+   * SHCI_C2_Reinit( ) before jumping to the application.
+   * When the CPU2 receives that command, it waits for its event input to be set to restart the CPU2 firmware.
+   * This is required because once C2BOOT has been set once, a clear/set on C2BOOT has no effect.
+   * When SHCI_C2_Reinit( ) is not called, generating an event to the CPU2 does not have any effect
+   * So, by default, the application shall both set the event flag and set the C2BOOT bit.
+   */
+  __SEV( );       /* Set the internal event flag and send an event to the CPU2 */
+  __WFE( );       /* Clear the internal event flag */
+  LL_PWR_EnableBootC2( );
+
+  return;
+}
+
+void HW_IPCC_Init( void )
+{
+  LL_AHB3_GRP1_EnableClock( LL_AHB3_GRP1_PERIPH_IPCC );
+
+  LL_C1_IPCC_EnableIT_RXO( IPCC );
+  LL_C1_IPCC_EnableIT_TXF( IPCC );
+
+  HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn);
+  HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn);
+
+  return;
+}
+
+/******************************************************************************
+ * BLE
+ ******************************************************************************/
+void HW_IPCC_BLE_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_BLE_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_BLE_CMD_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_BLE_EvtHandler( void )
+{
+  HW_IPCC_BLE_RxEvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_BLE_SendAclData( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_BLE_AclDataEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
+
+  HW_IPCC_BLE_AclDataAckNot();
+
+  return;
+}
+
+__weak void HW_IPCC_BLE_AclDataAckNot( void ){};
+__weak void HW_IPCC_BLE_RxEvtNot( void ){};
+
+/******************************************************************************
+ * SYSTEM
+ ******************************************************************************/
+void HW_IPCC_SYS_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_SYS_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_SYS_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
+
+  HW_IPCC_SYS_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_SYS_EvtHandler( void )
+{
+  HW_IPCC_SYS_EvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
+
+  return;
+}
+
+__weak void HW_IPCC_SYS_CmdEvtNot( void ){};
+__weak void HW_IPCC_SYS_EvtNot( void ){};
+
+/******************************************************************************
+ * MAC 802.15.4
+ ******************************************************************************/
+#ifdef MAC_802_15_4_WB
+void HW_IPCC_MAC_802_15_4_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_MAC_802_15_4_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_MAC_802_15_4_SendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_MAC_802_15_4_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL );
+
+  HW_IPCC_MAC_802_15_4_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_MAC_802_15_4_NotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_MAC_802_15_4_EvtNot();
+
+  return;
+}
+__weak void HW_IPCC_MAC_802_15_4_CmdEvtNot( void ){};
+__weak void HW_IPCC_MAC_802_15_4_EvtNot( void ){};
+#endif
+
+/******************************************************************************
+ * THREAD
+ ******************************************************************************/
+#ifdef THREAD_WB
+void HW_IPCC_THREAD_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_OT_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_CLI_SendCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_THREAD_SendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_THREAD_CliSendAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_OT_CmdEvtHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  HW_IPCC_OT_CmdEvtNot();
+
+  return;
+}
+
+static void HW_IPCC_THREAD_NotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_THREAD_EvtNot();
+
+  return;
+}
+
+static void HW_IPCC_THREAD_CliNotEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_THREAD_CliEvtNot();
+
+  return;
+}
+
+__weak void HW_IPCC_OT_CmdEvtNot( void ){};
+__weak void HW_IPCC_CLI_CmdEvtNot( void ){};
+__weak void HW_IPCC_THREAD_EvtNot( void ){};
+
+#endif /* THREAD_WB */
+
+/******************************************************************************
+ * ZIGBEE
+ ******************************************************************************/
+#ifdef ZIGBEE_WB
+void HW_IPCC_ZIGBEE_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendAppliCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+  LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendCliCmd( void )
+{
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
+
+   return;
+}
+
+void HW_IPCC_ZIGBEE_SendAppliCmdAck( void )
+{
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+  return;
+}
+
+void HW_IPCC_ZIGBEE_SendCliCmdAck( void )
+{
+    LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+    LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_CmdEvtHandler( void )
+{
+    LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
+
+    HW_IPCC_ZIGBEE_AppliCmdNotification();
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_StackNotifEvtHandler( void )
+{
+    LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
+
+    HW_IPCC_ZIGBEE_AppliAsyncEvtNotification();
+
+    return;
+}
+
+static void HW_IPCC_ZIGBEE_CliNotifEvtHandler( void )
+{
+  LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
+
+  HW_IPCC_ZIGBEE_CliEvtNotification();
+
+  return;
+}
+
+__weak void HW_IPCC_ZIGBEE_AppliCmdNotification( void ){};
+__weak void HW_IPCC_ZIGBEE_AppliAsyncEvtNotification( void ){};
+__weak void HW_IPCC_ZIGBEE_CliEvtNotification( void ){};
+#endif /* ZIGBEE_WB */
+
+/******************************************************************************
+ * MEMORY MANAGER
+ ******************************************************************************/
+void HW_IPCC_MM_SendFreeBuf( void (*cb)( void ) )
+{
+  if ( LL_C1_IPCC_IsActiveFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ) )
+  {
+    FreeBufCb = cb;
+    LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+  }
+  else
+  {
+    cb();
+
+    LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+  }
+
+  return;
+}
+
+static void HW_IPCC_MM_FreeBufHandler( void )
+{
+  LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+
+  FreeBufCb();
+
+  LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
+
+  return;
+}
+
+/******************************************************************************
+ * TRACES
+ ******************************************************************************/
+void HW_IPCC_TRACES_Init( void )
+{
+  LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_TRACES_CHANNEL );
+
+  return;
+}
+
+static void HW_IPCC_TRACES_EvtHandler( void )
+{
+  HW_IPCC_TRACES_EvtNot();
+
+  LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_TRACES_CHANNEL );
+
+  return;
+}
+
+__weak void HW_IPCC_TRACES_EvtNot( void ){};
+
+/******************* (C) COPYRIGHT 2019 STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/readme.txt b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/readme.txt
new file mode 100644
index 000000000..3879531a1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/Thread/Thread_Cli_Cmd/readme.txt
@@ -0,0 +1,176 @@
+/**
+  @page Thread_Cli_Cmd application
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Thread/Thread_Cli_Cmd/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the Thread Cli command application
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under Ultimate Liberty license 
+  * SLA0044, the "License"; You may not use this file except in compliance with 
+  * the License. You may obtain a copy of the License at:
+  *                               www.st.com/SLA0044
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Application Description 
+
+How to control the Thread stack via Cli commands.
+
+The Cli (Command Line Interface) commands are sent via an UART from an HyperTerminal (PC)
+to the STM32WB35RG_Nucleo Board.
+
+   ___________________________ 
+  |                           |     
+  |           ________________|                       _____________________________________
+  |          |USART1          |                      |     HyperTerminal 1                 |
+  |          |                |                      |=> Used to ctrl the stack via Cli Cmd|
+  |          |                |                      |                                     |
+  |          |                |                      |                                     |
+  |          |                |______________________|                                     |
+  |          |                |______________________| ST_Link virtual port                |
+  |          |                |     ST_Link Cable    |                                     |             
+  |          |                |                      |                                     |
+  |          |                |                      |                                     |
+  |          |                |                      |                                     |             
+  |          |________________|                      |_____________________________________|          
+  |                           |                       
+  |           _______________ |                       ______________________________________
+  |          |LPUART1         |                      |     HyperTerminal 2 (Optional)       |
+  |          |                |                      |=> Used to display traces             |   
+  |          |                |                      |                                      |
+  |          |CN10(Pin21) TX  |______________________|RX                                    | 
+  |          |                |                      |                                      |
+  |          |                |     RS232 Cable      |                                      |             
+  |          |                |                      |                                      |
+  |          |CN7(Pin38) RX   |______________________|TX                                    |          
+  |          |                |                      |                                      |           
+  |          |________________|                      |______________________________________|          
+  |                           |                                                
+  |                           |                      
+  |                           |                      
+  |_STM32WB35RG_Nucleo________|                      
+
+
+
+- Through the Cli commands, it is possible to control and configure the Thread 
+stack.
+- On the HyperTerminal, the user can type the command 'help' in order to display the list of 
+all available cli commands. Additional information can be found looking at the OpenThread 
+web site: https://openthread.io/guides/
+
+- As an example, the user can play the following scenario in order to properly initiate the Thread
+mesh network by typing the following commands: 
+
+  >panid 0x1234
+   Done
+  >channel 12
+   Done
+  >ifconfig up
+   Done
+  >thread start
+   Done
+
+At this point, the user can check the state of its device by using the cli command 'state' 
+   >state
+   Leader
+
+- When running on two STM32WB35RG_Nucleo boards the same Thread_Cli_Cmd application, and by playing the 
+ same scenario as described above on both boards, the first board should reach the state 'leader' 
+ while the second one should reach the state 'child'. 
+
+- When the Thread device changes state, a specific LED color is being displayed.
+  LED2 ON (Green) means that the device is in "Leader" mode.
+  LED3 ON (Red) means that the device is in "Router" or "Child" mode.
+  LED2 OFF and LED3 OFF means that the device is disabled or detached.
+  
+- When all LEDS are blinking, it means that a fatal error has been detected.
+
+     
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+@par Directory contents 
+  
+  - Thread/Thread_Cli_Cmd/Core/Inc/app_common.h            Header for all modules with common definition
+  - Thread/Thread_Cli_Cmd/Core/Inc/app_conf.h              Parameters configuration file of the application 
+  - Thread/Thread_Cli_Cmd/Core/Inc/app_entry.h             Parameters configuration file of the application
+  - Thread/Thread_Cli_Cmd/STM32_WPAN/App/app_thread.h      Header for app_thread.c module
+  - Thread/Thread_Cli_Cmd/Core/Inc/hw_conf.h               Configuration file of the HW 
+  - Thread/Thread_Cli_Cmd/Core/Inc/main.h                  Header for main.c module
+  - Thread/Thread_Cli_Cmd/Core/Inc/stm_logging.h           Header for stm_logging.c module
+  - Thread/Thread_Cli_Cmd/Core/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - Thread/Thread_Cli_Cmd/Core/Src/stm32wbxx_it.h          Interrupt header file
+  - Thread/Thread_Cli_Cmd/Core/Inc/system_infra.h          System infrastructure header file
+  - Thread/Thread_Cli_Cmd/Core/Inc/utilities_conf.h        Configuration file of the utilities
+  - Thread/Thread_Cli_Cmd/Core/Src/app_entry.c             Initialization of the application
+  - Thread/Thread_Cli_Cmd/STM32_WPAN/App/app_thread.c      Thread application implementation
+  - Thread/Thread_Cli_Cmd/STM32_WPAN/Target/hw_ipcc.c      IPCC Driver
+  - Thread/Thread_Cli_Cmd/Core/Src/stm32_lpm_if.c          Low Power Manager Interface
+  - Thread/Thread_Cli_Cmd/Core/Src/hw_uart.c               UART driver
+  - Thread/Thread_Cli_Cmd/Core/Src/main.c                  Main program
+  - Thread/Thread_Cli_Cmd/Core/Src/stm_logging.c           Logging module for traces
+  - Thread/Thread_Cli_Cmd/Core/Src/stm32xx_it.c            Interrupt handlers
+  - Thread/Thread_Cli_Cmd/Core/Src/system_stm32wbxx.c      stm32wbxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35xx devices (Nucleo board and dongle) 
+  
+  - This example has been tested with an STMicroelectronics STM32WB35RG_Nucleo 
+    board and can be easily tailored to any other supported device 
+    and development board.
+    
+  - On STM32WB35RG_Nucleo, the jumpers must be configured as described
+    in this section. Starting from the top left position up to the bottom 
+    right position, the jumpers on the Board must be set as follows: 
+
+     CN11:    GND         [OFF]
+     JP4:     VDDRF       [ON]
+     JP6:     VC0         [ON]
+     JP2:     +3V3        [ON] 
+     JP1:     USB_STL     [ON]   All others [OFF]
+     CN12:    GND         [OFF]
+     CN7:            [OFF]
+     JP3:     VDD_MCU     [ON]
+     JP5:     GND         [OFF]  All others [ON]
+     CN10:           [OFF]
+
+ 
+@par How to use it ? 
+
+This application requests having the stm32wb5x_Thread_FTD_fw.bin binary flashed on the Wireless Coprocessor.
+If it is not the case, you need to use STM32CubeProgrammer to load the appropriate binary.
+All available binaries are located under /Projects/STM32_Copro_Wireless_Binaries directory.
+Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the detailed procedure to change the
+Wireless Coprocessor binary. 
+
+
+In order to make the program work, you must do the following: 
+ - Connect an STM32WB35xx_Nucleo board to your PC 
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image OR use the Thread_Cli_Cmd_reference.hex from Binary directory
+ - Connect one HyperTerminal (ST_Link) to be able to control the Thread stack via Cli commands 
+ - Connect a second HyperTerminal as described below to get the traces (optional)
+ - Run the example and use the HyperTerminal to interact with the Board via the Cli commands
+
+Note: when LED1, LED2 and LED3 are toggling it is indicating an error has occurred on application.
+
+For the Cli control and for the traces, the UART must be configured as follows:
+    - BaudRate = 115200 baud  
+    - Word Length = 8 Bits 
+    - Stop Bit = 1 bit
+    - Parity = none
+    - Flow control = none
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
\ No newline at end of file
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/.extSettings b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/.extSettings
new file mode 100644
index 000000000..299daa44b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/.extSettings
@@ -0,0 +1,11 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Application/User/Core=../Core/Src/main.c;../Core/Src/stm32wbxx_it.c;../Core/Src/stm32wbxx_hal_msp.c;../Core/Src/stm32wbxx_hal_msp.c;
+Application/User/USB_Device/App=../USB_Device/App/usbd_desc.c;../USB_Device/App/usb_device.c;
+Application/User/USB_Device/Target=../USB_Device/Target/usbd_conf.c;
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Inc/main.h b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Inc/main.h
new file mode 100644
index 000000000..692b73a97
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Inc/main.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    USB_Device/HID_Standalone/Core/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+#define BUTTON_KEY1                      BUTTON_SW1
+#define BUTTON_KEY1_PIN                  BUTTON_SW1_PIN
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..fbe05df3e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+#define HAL_PCD_MODULE_ENABLED
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..8a348aed1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Inc/stm32wbxx_it.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    USB_Device/HID_Standalone/Core/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void USB_LP_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+void EXTI0_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Src/main.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Src/main.c
new file mode 100644
index 000000000..c278092cb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Src/main.c
@@ -0,0 +1,229 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    USB_Device/HID_Standalone/Core/Src/main.c
+  * @author  MCD Application Team
+  * @brief   USB device HID demo main file
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "usb_device.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_USB_Device_Init();
+  /* USER CODE BEGIN 2 */
+  /* Configure the application hardware resources */
+  BSP_PB_Init(BUTTON_KEY1, BUTTON_MODE_EXTI);
+  BSP_LED_Init(LED3);
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief This function provides accurate delay (in milliseconds) based
+  * on SysTick counter flag.
+  * @note This function is declared as __weak to be overwritten in case of other
+  * implementations in user file.
+  * @param Delay: specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+void HAL_Delay(__IO uint32_t Delay)
+{
+  while (Delay)
+  {
+    if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)
+    {
+      Delay--;
+    }
+  }
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  BSP_LED_On(LED3);
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..0ed084ebd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,83 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    USB_Device/HID_Standalone/Core/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  *          This file provides code for the MSP Initialization
+  *          and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..cd737ebb9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Src/stm32wbxx_it.c
@@ -0,0 +1,229 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    USB_Device/HID_Standalone/Core/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern PCD_HandleTypeDef hpcd_USB_FS;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles USB low priority interrupt, USB wake-up interrupt through EXTI line 28.
+  */
+void USB_LP_IRQHandler(void)
+{
+  /* USER CODE BEGIN USB_LP_IRQn 0 */
+
+  /* USER CODE END USB_LP_IRQn 0 */
+  HAL_PCD_IRQHandler(&hpcd_USB_FS);
+  /* USER CODE BEGIN USB_LP_IRQn 1 */
+
+  /* USER CODE END USB_LP_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles External lines interrupt request.
+  * @param  None
+  * @retval None
+  */
+
+void EXTI0_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_KEY1_PIN);
+}
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..4cb9e0e42
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/Core/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx) || defined(STM32WB5Mxx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/HID_Standalone.ewd b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/HID_Standalone.ewd
new file mode 100644
index 000000000..16bb2ea56
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/HID_Standalone.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		HID_Standalone
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/HID_Standalone.ewp b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/HID_Standalone.ewp
new file mode 100644
index 000000000..742508e38
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/HID_Standalone.ewp
@@ -0,0 +1,1171 @@
+
+
+  3
+  
+    HID_Standalone
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        Core
+        
+          $PROJ_DIR$/../Core/Src/main.c
+        
+        
+          $PROJ_DIR$/../Core/Src/stm32wbxx_it.c
+        
+        
+          $PROJ_DIR$/../Core/Src/stm32wbxx_hal_msp.c
+        
+      
+      
+        USB_Device
+        
+          App
+          
+            $PROJ_DIR$/../USB_Device/App/usbd_desc.c
+          
+          
+            $PROJ_DIR$/../USB_Device/App/usb_device.c
+          
+        
+        
+          Target
+          
+            $PROJ_DIR$/../USB_Device/Target/usbd_conf.c
+          
+        
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Core/Src/system_stm32wbxx.c
+      
+    
+  
+  
+    Middlewares
+    
+      USB_Device_Library
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/Project.eww
new file mode 100644
index 000000000..c10012689
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\HID_Standalone.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..43a793371
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/stm32wb35xx_sram_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/stm32wb35xx_sram_cm4.icf
new file mode 100644
index 000000000..572eeb981
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/EWARM/stm32wb35xx_sram_cm4.icf
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20003FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20004000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20008000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x2000FFFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/HID_Standalone.ioc b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/HID_Standalone.ioc
new file mode 100644
index 000000000..1448454f6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/HID_Standalone.ioc
@@ -0,0 +1,148 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=USB
+Mcu.IP4=USB_DEVICE
+Mcu.IPNb=5
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA11
+Mcu.Pin1=PA12
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.Pin3=VP_USB_DEVICE_VS_USB_DEVICE_HID_FS
+Mcu.PinsNb=4
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.USB_LP_IRQn=true\:6\:0\:true\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA11.GPIOParameters=GPIO_Speed
+PA11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA11.Mode=Device
+PA11.Signal=USB_DM
+PA12.GPIOParameters=GPIO_Speed
+PA12.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA12.Mode=Device
+PA12.Signal=USB_DP
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=3
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x1000
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=false
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Core/Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=HID_Standalone.ioc
+ProjectManager.ProjectName=HID_Standalone
+ProjectManager.StackSize=0x1000
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USB_Device_Init-USB_DEVICE-false-HAL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+USB.DeviceSpeed=PCD_SPEED_FULL
+USB.IPParameters=DeviceSpeed,phy_itface,Sof_enable,low_power_enable,lpm_enable,battery_charging_enable
+USB.Sof_enable=DISABLE
+USB.battery_charging_enable=DISABLE
+USB.low_power_enable=DISABLE
+USB.lpm_enable=DISABLE
+USB.phy_itface=PCD_PHY_EMBEDDED
+USB_DEVICE.CLASS_NAME_FS=HID
+USB_DEVICE.CONFIGURATION_STRING_HID_FS=HID Config
+USB_DEVICE.HID_FS_BINTERVAL=0xA
+USB_DEVICE.INTERFACE_STRING_HID_FS=HID Interface
+USB_DEVICE.IPParameters=VirtualMode,VirtualModeFS,CLASS_NAME_FS,USBD_MAX_NUM_INTERFACES,USBD_MAX_STR_DESC_SIZ,VID,PID_HID_FS,USBD_LPM_ENABLED,HID_FS_BINTERVAL,USBD_MAX_NUM_CONFIGURATION,USBD_SELF_POWERED,USBD_DEBUG_LEVEL,LANGID_STRING,MANUFACTURER_STRING,PRODUCT_STRING_HID_FS,CONFIGURATION_STRING_HID_FS,INTERFACE_STRING_HID_FS
+USB_DEVICE.IPParametersWithoutCheck=USBD_MAX_STR_DESC_SIZ,USBD_MAX_NUM_INTERFACES
+USB_DEVICE.LANGID_STRING=1033
+USB_DEVICE.MANUFACTURER_STRING=STMicroelectronics
+USB_DEVICE.PID_HID_FS=0x5710
+USB_DEVICE.PRODUCT_STRING_HID_FS=STM32 Human interface
+USB_DEVICE.USBD_DEBUG_LEVEL=0
+USB_DEVICE.USBD_LPM_ENABLED=0
+USB_DEVICE.USBD_MAX_NUM_CONFIGURATION=1
+USB_DEVICE.USBD_MAX_NUM_INTERFACES=1
+USB_DEVICE.USBD_MAX_STR_DESC_SIZ=64
+USB_DEVICE.USBD_SELF_POWERED=1
+USB_DEVICE.VID=0x483
+USB_DEVICE.VirtualMode=Hid
+USB_DEVICE.VirtualModeFS=Hid_FS
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+VP_USB_DEVICE_VS_USB_DEVICE_HID_FS.Mode=HID_FS
+VP_USB_DEVICE_VS_USB_DEVICE_HID_FS.Signal=USB_DEVICE_VS_USB_DEVICE_HID_FS
+board=NUCLEO-WB55RG
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/MDK-ARM/HID_Standalone.uvoptx b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/MDK-ARM/HID_Standalone.uvoptx
new file mode 100644
index 000000000..872cf99ad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/MDK-ARM/HID_Standalone.uvoptx
@@ -0,0 +1,641 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    HID_Standalone
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User/Core
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Core/Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Core/Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      2
+      4
+      1
+      0
+      0
+      0
+      ../Core/Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Application/User/USB_Device/App
+    0
+    0
+    0
+    0
+    
+      3
+      5
+      1
+      0
+      0
+      0
+      ../USB_Device/App/usbd_desc.c
+      usbd_desc.c
+      0
+      0
+    
+    
+      3
+      6
+      1
+      0
+      0
+      0
+      ../USB_Device/App/usb_device.c
+      usb_device.c
+      0
+      0
+    
+  
+
+  
+    Application/User/USB_Device/Target
+    0
+    0
+    0
+    0
+    
+      4
+      7
+      1
+      0
+      0
+      0
+      ../USB_Device/Target/usbd_conf.c
+      usbd_conf.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      5
+      8
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      7
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      7
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c
+      stm32wbxx_hal_pcd.c
+      0
+      0
+    
+    
+      7
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd_ex.c
+      stm32wbxx_hal_pcd_ex.c
+      0
+      0
+    
+    
+      7
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c
+      stm32wbxx_ll_usb.c
+      0
+      0
+    
+    
+      7
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      7
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      7
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      7
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      7
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      7
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      7
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      7
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      7
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      7
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      7
+      24
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      7
+      25
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      7
+      26
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      7
+      27
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      8
+      28
+      1
+      0
+      0
+      0
+      ../Core/Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    Middlewares/USB_Device_Library
+    0
+    0
+    0
+    0
+    
+      9
+      29
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c
+      usbd_core.c
+      0
+      0
+    
+    
+      9
+      30
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
+      usbd_ctlreq.c
+      0
+      0
+    
+    
+      9
+      31
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
+      usbd_ioreq.c
+      0
+      0
+    
+    
+      9
+      32
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c
+      usbd_hid.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/MDK-ARM/HID_Standalone.uvprojx b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/MDK-ARM/HID_Standalone.uvprojx
new file mode 100644
index 000000000..1a9c4e04a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/MDK-ARM/HID_Standalone.uvprojx
@@ -0,0 +1,607 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      HID_Standalone
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          HID_Standalone\
+          HID_Standalone
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../USB_Device/App;../USB_Device/Target;../Core/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Inc;../../../../../../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User/Core
+          
+            
+              main.c
+              1
+              ../Core/Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Core/Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Core/Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Application/User/USB_Device/App
+          
+            
+              usbd_desc.c
+              1
+              ../USB_Device/App/usbd_desc.c
+            
+            
+              usb_device.c
+              1
+              ../USB_Device/App/usb_device.c
+            
+          
+        
+        
+          Application/User/USB_Device/Target
+          
+            
+              usbd_conf.c
+              1
+              ../USB_Device/Target/usbd_conf.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_pcd.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c
+            
+            
+              stm32wbxx_hal_pcd_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd_ex.c
+            
+            
+              stm32wbxx_ll_usb.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Core/Src/system_stm32wbxx.c
+            
+          
+        
+        
+          Middlewares/USB_Device_Library
+          
+            
+              usbd_core.c
+              1
+              ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c
+            
+            
+              usbd_ctlreq.c
+              1
+              ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
+            
+            
+              usbd_ioreq.c
+              1
+              ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
+            
+            
+              usbd_hid.c
+              1
+              ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..ae049b184
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x1000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x1000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..6527cf423
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/.cproject
@@ -0,0 +1,178 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/.project
new file mode 100644
index 000000000..954a59590
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/.project
@@ -0,0 +1,196 @@
+
+
+	HID_Standalone
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			HID_Standalone.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/HID_Standalone.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Core/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Core/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Core/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Core/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pcd.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pcd_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_usb.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c
+		
+		
+			Middlewares/USB_Device_Library/usbd_core.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c
+		
+		
+			Middlewares/USB_Device_Library/usbd_ctlreq.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
+		
+		
+			Middlewares/USB_Device_Library/usbd_hid.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c
+		
+		
+			Middlewares/USB_Device_Library/usbd_ioreq.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+		
+			Application/User/USB_Device/App/usb_device.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/USB_Device/App/usb_device.c
+		
+		
+			Application/User/USB_Device/App/usbd_desc.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/USB_Device/App/usbd_desc.c
+		
+		
+			Application/User/USB_Device/Target/usbd_conf.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/USB_Device/Target/usbd_conf.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..eea98ff9c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb35xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB35xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f9a002eb7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x1000 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x1000 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/App/usb_device.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/App/usb_device.c
new file mode 100644
index 000000000..16b30bc21
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/App/usb_device.c
@@ -0,0 +1,210 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    USB_Device/HID_Standalone/USB_Device/App/usb_device.c
+  * @author  MCD Application Team
+  * @brief   This file implements the USB Device
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+ 
+#include "usb_device.h"
+#include "usbd_core.h"
+#include "usbd_desc.h"
+#include "usbd_hid.h"
+
+/* USER CODE BEGIN Includes */
+#include "main.h"
+/* USER CODE END Includes */
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+__IO uint32_t remotewakeupon = 0;
+uint8_t HID_Buffer[4];
+extern PCD_HandleTypeDef hpcd_USB_FS;
+#define CURSOR_STEP     5
+/* USER CODE END PV */
+
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+static void GetPointerData(uint8_t *pbuf);
+extern void SystemClockConfig_Resume(void);
+void USBD_Clock_Config(void);
+/* USER CODE END PFP */
+
+extern void Error_Handler(void);
+/* USB Device Core handle declaration. */
+USBD_HandleTypeDef hUsbDeviceFS;
+extern USBD_DescriptorsTypeDef HID_Desc;
+
+/*
+ * -- Insert your variables declaration here --
+ */
+/* USER CODE BEGIN 0 */
+/**
+  * @brief USB Clock Configuration
+  * @retval None
+  */
+void USBD_Clock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_CRSInitTypeDef RCC_CRSInitStruct= {0};
+
+  /* Enable HSI48 */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct)!= HAL_OK)
+  {
+    Error_Handler();
+  }
+  /*Configure the clock recovery system (CRS)**********************************/
+
+  /*Enable CRS Clock*/
+  __HAL_RCC_CRS_CLK_ENABLE();
+
+  /* Default Synchro Signal division factor (not divided) */
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+
+  /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+
+  /* HSI48 is synchronized with USB SOF at 1KHz rate */
+  RCC_CRSInitStruct.ReloadValue =  __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
+  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+
+  /* Set the TRIM[5:0] to the default value */
+  RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+
+  /* Start automatic synchronization */
+  HAL_RCCEx_CRSConfig (&RCC_CRSInitStruct);
+}
+/* USER CODE END 0 */
+
+/*
+ * -- Insert your external function declaration here --
+ */
+/* USER CODE BEGIN 1 */
+
+/**
+  * @brief  Gets Pointer Data.
+  * @param  pbuf: Pointer to report
+  * @retval None
+  */
+void GetPointerData(uint8_t * pbuf)
+{
+  static int8_t cnt = 0;
+  int8_t x = 0, y = 0;
+
+  if (cnt++ > 0)
+  {
+    x = CURSOR_STEP;
+  }
+  else
+  {
+    x = -CURSOR_STEP;
+  }
+  pbuf[0] = 0;
+  pbuf[1] = x;
+  pbuf[2] = y;
+  pbuf[3] = 0;
+}
+
+/**
+  * @brief  GPIO EXTI Callback function
+  *         Handle remote-wakeup through key button
+  * @param  GPIO_Pin
+  * @retval None
+  */
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  if (GPIO_Pin == BUTTON_KEY1_PIN)
+  {
+    if ((((USBD_HandleTypeDef *) hpcd_USB_FS.pData)->dev_remote_wakeup == 1) &&
+        (((USBD_HandleTypeDef *) hpcd_USB_FS.pData)->dev_state ==
+         USBD_STATE_SUSPENDED))
+    {
+      if ((&hpcd_USB_FS)->Init.low_power_enable)
+      {
+        HAL_ResumeTick();
+        SystemClockConfig_Resume();
+      }
+      /* Activate Remote wakeup */
+      HAL_PCD_ActivateRemoteWakeup((&hpcd_USB_FS));
+
+      /* Remote wakeup delay */
+      HAL_Delay(10);
+
+      /* Disable Remote wakeup */
+      HAL_PCD_DeActivateRemoteWakeup((&hpcd_USB_FS));
+
+      /* change state to configured */
+      ((USBD_HandleTypeDef *) hpcd_USB_FS.pData)->dev_state = USBD_STATE_CONFIGURED;
+
+      /* Change remote_wakeup feature to 0 */
+      ((USBD_HandleTypeDef *) hpcd_USB_FS.pData)->dev_remote_wakeup = 0;
+      remotewakeupon = 1;
+    }
+    else if (((USBD_HandleTypeDef *) hpcd_USB_FS.pData)->dev_state ==
+         USBD_STATE_CONFIGURED)
+    {
+      GetPointerData(HID_Buffer);
+      USBD_HID_SendReport(&hUsbDeviceFS, HID_Buffer, 4);
+    }
+    else
+    {
+      /* ... */
+    }
+  }
+}
+
+/* USER CODE END 1 */
+
+/**
+  * Init USB device Library, add supported class and start the library
+  * @retval None
+  */
+void MX_USB_Device_Init(void)
+{
+  /* USER CODE BEGIN USB_Device_Init_PreTreatment */
+  /* USB Clock Initialization */
+   USBD_Clock_Config();
+  /* USER CODE END USB_Device_Init_PreTreatment */
+  
+  /* Init Device Library, add supported class and start the library. */
+  if (USBD_Init(&hUsbDeviceFS, &HID_Desc, DEVICE_FS) != USBD_OK) {
+    Error_Handler();
+  }
+  if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_HID) != USBD_OK) {
+    Error_Handler();
+  }
+  if (USBD_Start(&hUsbDeviceFS) != USBD_OK) {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USB_Device_Init_PostTreatment */
+
+  /* USER CODE END USB_Device_Init_PostTreatment */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/App/usb_device.h b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/App/usb_device.h
new file mode 100644
index 000000000..57fb199fe
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/App/usb_device.h
@@ -0,0 +1,105 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           USB_Device/HID_Standalone/USB_Device/App/usb_device.h
+  * @author         MCD Application Team
+  * @brief          Header for usb_device.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_DEVICE__H__
+#define __USB_DEVICE__H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx.h"
+#include "stm32wbxx_hal.h"
+#include "usbd_def.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/** @addtogroup USBD_OTG_DRIVER
+  * @{
+  */
+
+/** @defgroup USBD_DEVICE USBD_DEVICE
+  * @brief Device file for Usb otg low level driver.
+  * @{
+  */
+
+/** @defgroup USBD_DEVICE_Exported_Variables USBD_DEVICE_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/*
+ * -- Insert your variables declaration here --
+ */
+/* USER CODE BEGIN VARIABLES */
+
+/* USER CODE END VARIABLES */
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DEVICE_Exported_FunctionsPrototype USBD_DEVICE_Exported_FunctionsPrototype
+  * @brief Declaration of public functions for Usb device.
+  * @{
+  */
+
+/** USB Device initialization function. */
+void MX_USB_Device_Init(void);
+
+/*
+ * -- Insert functions declaration here --
+ */
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_DEVICE__H__ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/App/usbd_desc.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/App/usbd_desc.c
new file mode 100644
index 000000000..0d7c43a2c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/App/usbd_desc.c
@@ -0,0 +1,397 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           USB_Device/HID_Standalone/USB_Device/App/usbd_desc.c
+  * @author         MCD Application Team
+  * @brief          This file implements the USB device descriptors.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_core.h"
+#include "usbd_desc.h"
+#include "usbd_conf.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @addtogroup USBD_DESC
+  * @{
+  */
+
+/** @defgroup USBD_DESC_Private_TypesDefinitions USBD_DESC_Private_TypesDefinitions
+  * @brief Private types.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_TYPES */
+
+/* USER CODE END PRIVATE_TYPES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Defines USBD_DESC_Private_Defines
+  * @brief Private defines.
+  * @{
+  */
+
+#define USBD_VID     0x483
+#define USBD_LANGID_STRING     1033
+#define USBD_MANUFACTURER_STRING     "STMicroelectronics"
+#define USBD_PID     0x5710
+#define USBD_PRODUCT_STRING     "STM32 Human interface"
+#define USBD_CONFIGURATION_STRING     "HID Config"
+#define USBD_INTERFACE_STRING     "HID Interface"
+
+/* USER CODE BEGIN PRIVATE_DEFINES */
+
+/* USER CODE END PRIVATE_DEFINES */
+
+/**
+  * @}
+  */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/** @defgroup USBD_DESC_Private_Macros USBD_DESC_Private_Macros
+  * @brief Private macros.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_MACRO */
+
+/* USER CODE END PRIVATE_MACRO */
+
+/**
+  * @}
+  */
+  
+/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
+  * @brief Private functions declaration.
+  * @{
+  */
+  
+static void Get_SerialNum(void);
+static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len);
+  
+/**
+  * @}
+  */  
+  
+
+/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
+  * @brief Private functions declaration.
+  * @{
+  */
+
+uint8_t * USBD_HID_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_HID_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_HID_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_HID_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_HID_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_HID_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_HID_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables
+  * @brief Private variables.
+  * @{
+  */
+
+USBD_DescriptorsTypeDef HID_Desc =
+{
+  USBD_HID_DeviceDescriptor, 
+  USBD_HID_LangIDStrDescriptor, 
+  USBD_HID_ManufacturerStrDescriptor, 
+  USBD_HID_ProductStrDescriptor, 
+  USBD_HID_SerialStrDescriptor, 
+  USBD_HID_ConfigStrDescriptor, 
+  USBD_HID_InterfaceStrDescriptor
+};
+
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+/** USB standard device descriptor. */
+__ALIGN_BEGIN uint8_t USBD_HID_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END =
+{
+  0x12,                       /*bLength */
+  USB_DESC_TYPE_DEVICE,       /*bDescriptorType*/
+  0x00,                       /*bcdUSB */
+  0x02,
+  0x00,                       /*bDeviceClass*/
+  0x00,                       /*bDeviceSubClass*/
+  0x00,                       /*bDeviceProtocol*/
+  USB_MAX_EP0_SIZE,           /*bMaxPacketSize*/
+  LOBYTE(USBD_VID),           /*idVendor*/
+  HIBYTE(USBD_VID),           /*idVendor*/
+  LOBYTE(USBD_PID),           /*idProduct*/
+  HIBYTE(USBD_PID),           /*idProduct*/
+  0x00,                       /*bcdDevice rel. 2.00*/
+  0x02,
+  USBD_IDX_MFC_STR,           /*Index of manufacturer  string*/
+  USBD_IDX_PRODUCT_STR,       /*Index of product string*/
+  USBD_IDX_SERIAL_STR,        /*Index of serial number string*/
+  USBD_MAX_NUM_CONFIGURATION  /*bNumConfigurations*/
+};
+
+/* USB_DeviceDescriptor */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables
+  * @brief Private variables.
+  * @{
+  */
+
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+
+/** USB lang indentifier descriptor. */
+__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END =
+{
+     USB_LEN_LANGID_STR_DESC,
+     USB_DESC_TYPE_STRING,
+     LOBYTE(USBD_LANGID_STRING),
+     HIBYTE(USBD_LANGID_STRING)
+};
+
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+/* Internal string descriptor. */
+__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END;
+
+#if defined ( __ICCARM__ ) /*!< IAR Compiler */
+  #pragma data_alignment=4   
+#endif
+__ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] __ALIGN_END = {
+  USB_SIZ_STRING_SERIAL,
+  USB_DESC_TYPE_STRING,
+};
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Functions USBD_DESC_Private_Functions
+  * @brief Private functions.
+  * @{
+  */
+
+/**
+  * @brief  Return the device descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_HID_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  *length = sizeof(USBD_HID_DeviceDesc);
+  return USBD_HID_DeviceDesc;
+}
+
+/**
+  * @brief  Return the LangID string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_HID_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  *length = sizeof(USBD_LangIDDesc);
+  return USBD_LangIDDesc;
+}
+
+/**
+  * @brief  Return the product string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_HID_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  if(speed == 0)
+  {
+    USBD_GetString((uint8_t *)USBD_PRODUCT_STRING, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString((uint8_t *)USBD_PRODUCT_STRING, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Return the manufacturer string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_HID_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Return the serial number string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_HID_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  *length = USB_SIZ_STRING_SERIAL;
+
+  /* Update the serial number string descriptor with the data from the unique
+   * ID */
+  Get_SerialNum();
+  
+  /* USER CODE BEGIN USBD_HID_SerialStrDescriptor */
+  
+  /* USER CODE END USBD_HID_SerialStrDescriptor */
+
+  return (uint8_t *) USBD_StringSerial;
+}
+
+/**
+  * @brief  Return the configuration string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_HID_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  if(speed == USBD_SPEED_HIGH)
+  {
+    USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Return the interface string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_HID_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  if(speed == 0)
+  {
+    USBD_GetString((uint8_t *)USBD_INTERFACE_STRING, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString((uint8_t *)USBD_INTERFACE_STRING, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Create the serial number string descriptor 
+  * @param  None 
+  * @retval None
+  */
+static void Get_SerialNum(void)
+{
+  uint32_t deviceserial0, deviceserial1, deviceserial2;
+
+  deviceserial0 = *(uint32_t *) DEVICE_ID1;
+  deviceserial1 = *(uint32_t *) DEVICE_ID2;
+  deviceserial2 = *(uint32_t *) DEVICE_ID3;
+
+  deviceserial0 += deviceserial2;
+
+  if (deviceserial0 != 0)
+  {
+    IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
+    IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
+  }
+}
+
+/**
+  * @brief  Convert Hex 32Bits value into char 
+  * @param  value: value to convert
+  * @param  pbuf: pointer to the buffer 
+  * @param  len: buffer length
+  * @retval None
+  */
+static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
+{
+  uint8_t idx = 0;
+
+  for (idx = 0; idx < len; idx++)
+  {
+    if (((value >> 28)) < 0xA)
+    {
+      pbuf[2 * idx] = (value >> 28) + '0';
+    }
+    else
+    {
+      pbuf[2 * idx] = (value >> 28) + 'A' - 10;
+    }
+
+    value = value << 4;
+
+    pbuf[2 * idx + 1] = 0;
+  }
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/App/usbd_desc.h b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/App/usbd_desc.h
new file mode 100644
index 000000000..0369b52e8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/App/usbd_desc.h
@@ -0,0 +1,145 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           USB_Device/HID_Standalone/USB_Device/App/usbd_desc.h
+  * @author         MCD Application Team
+  * @brief          Header for usbd_desc.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_DESC__C__
+#define __USBD_DESC__C__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_def.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup USBD_DESC USBD_DESC
+  * @brief Usb device descriptors module.
+  * @{
+  */
+  
+/** @defgroup USBD_DESC_Exported_Constants USBD_DESC_Exported_Constants
+  * @brief Constants.
+  * @{
+  */
+#define         DEVICE_ID1          (UID_BASE)
+#define         DEVICE_ID2          (UID_BASE + 0x4)
+#define         DEVICE_ID3          (UID_BASE + 0x8)
+
+#define         USB_SIZ_STRING_SERIAL       0x1A
+
+/* USER CODE BEGIN EXPORTED_CONSTANTS */
+
+/* USER CODE END EXPORTED_CONSTANTS */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_Defines USBD_DESC_Exported_Defines
+  * @brief Defines.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_DEFINES */
+
+/* USER CODE END EXPORTED_DEFINES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_TypesDefinitions USBD_DESC_Exported_TypesDefinitions
+  * @brief Types.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_TYPES */
+
+/* USER CODE END EXPORTED_TYPES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_Macros USBD_DESC_Exported_Macros
+  * @brief Aliases.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_MACRO */
+
+/* USER CODE END EXPORTED_MACRO */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_Variables USBD_DESC_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+extern USBD_DescriptorsTypeDef     HID_Desc;
+
+/* USER CODE BEGIN EXPORTED_VARIABLES */
+
+/* USER CODE END EXPORTED_VARIABLES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_FunctionsPrototype USBD_DESC_Exported_FunctionsPrototype
+  * @brief Public functions declaration.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_FUNCTIONS */
+
+/* USER CODE END EXPORTED_FUNCTIONS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_DESC__C__ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/Target/usbd_conf.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/Target/usbd_conf.c
new file mode 100644
index 000000000..f3bf38f9f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/Target/usbd_conf.c
@@ -0,0 +1,774 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           USB_Device/HID_Standalone/USB_Device/Target/usbd_conf.c
+  * @author         MCD Application Team
+  * @brief          This file implements the board support package for the USB device library
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx.h"
+#include "stm32wbxx_hal.h"
+#include "usbd_def.h"
+#include "usbd_core.h"
+
+#include "usbd_hid.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+PCD_HandleTypeDef hpcd_USB_FS;
+void Error_Handler(void);
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* Exported function prototypes ----------------------------------------------*/
+
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+extern void USBD_Clock_Config(void);
+void SystemClockConfig_Resume(void);
+/* USER CODE END PFP */
+
+/* Private functions ---------------------------------------------------------*/
+static USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status);
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+extern void SystemClock_Config(void);
+
+/*******************************************************************************
+                       LL Driver Callbacks (PCD -> USB Device Library)
+*******************************************************************************/
+/* MSP Init */
+
+#if (USE_HAL_PCD_REGISTER_CALLBACK == 1U)
+static void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
+#else
+void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACK */
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(pcdHandle->Instance==USB)
+  {
+  /* USER CODE BEGIN USB_MspInit 0 */
+
+  /* USER CODE END USB_MspInit 0 */
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**USB GPIO Configuration    
+    PA11     ------> USB_DM
+    PA12     ------> USB_DP 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF10_USB;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* Peripheral clock enable */
+    __HAL_RCC_USB_CLK_ENABLE();
+
+    /* Peripheral interrupt init */
+    HAL_NVIC_SetPriority(USB_LP_IRQn, 6, 0);
+    HAL_NVIC_EnableIRQ(USB_LP_IRQn);
+  /* USER CODE BEGIN USB_MspInit 1 */
+
+  /* USER CODE END USB_MspInit 1 */
+  }
+}
+
+#if (USE_HAL_PCD_REGISTER_CALLBACK == 1U)
+static void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle)
+#else
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACK */
+{
+  if(pcdHandle->Instance==USB)
+  {
+  /* USER CODE BEGIN USB_MspDeInit 0 */
+
+  /* USER CODE END USB_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USB_CLK_DISABLE();
+  
+    /**USB GPIO Configuration    
+    PA11     ------> USB_DM
+    PA12     ------> USB_DP 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12);
+
+    /* Peripheral interrupt Deinit*/
+    HAL_NVIC_DisableIRQ(USB_LP_IRQn);
+
+  /* USER CODE BEGIN USB_MspDeInit 1 */
+    __HAL_RCC_GPIOA_CLK_DISABLE();
+  /* USER CODE END USB_MspDeInit 1 */
+  }
+}
+
+/**
+  * @brief  Setup stage callback
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_SetupStageCallback_PreTreatment */
+
+  /* USER CODE END  HAL_PCD_SetupStageCallback_PreTreatment */
+  USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);  
+  /* USER CODE BEGIN HAL_PCD_SetupStageCallback_PostTreatment */
+
+  /* USER CODE END  HAL_PCD_SetupStageCallback_PostTreatment */
+}
+
+/**
+  * @brief  Data Out stage callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_DataOutStageCallback_PreTreatment */
+  USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);  
+  /* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PostTreatment */
+
+  /* USER CODE END HAL_PCD_DataOutStageCallback_PostTreatment */
+}
+
+/**
+  * @brief  Data In stage callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_DataInStageCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_DataInStageCallback_PreTreatment */  
+  USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);  
+  /* USER CODE BEGIN HAL_PCD_DataInStageCallback_PostTreatment  */
+
+  /* USER CODE END HAL_PCD_DataInStageCallback_PostTreatment */
+}
+
+/**
+  * @brief  SOF callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_SOFCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_SOFCallback_PreTreatment */  
+  USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);  
+  /* USER CODE BEGIN HAL_PCD_SOFCallback_PostTreatment */
+
+  /* USER CODE END HAL_PCD_SOFCallback_PostTreatment */
+}
+
+/**
+  * @brief  Reset callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{ 
+  /* USER CODE BEGIN HAL_PCD_ResetCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_ResetCallback_PreTreatment */
+  USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
+
+  if ( hpcd->Init.speed != PCD_SPEED_FULL)
+  {
+    Error_Handler();
+  }
+    /* Set Speed. */
+  USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
+
+  /* Reset Device. */
+  USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
+  /* USER CODE BEGIN HAL_PCD_ResetCallback_PostTreatment */
+
+  /* USER CODE END HAL_PCD_ResetCallback_PostTreatment */
+}
+
+/**
+  * @brief  Suspend callback.
+  * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it)
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_SuspendCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_SuspendCallback_PreTreatment */
+  /* Inform USB library that core enters in suspend Mode. */
+  USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
+  /* Enter in STOP mode. */
+  /* USER CODE BEGIN 2 */
+  if (hpcd->Init.low_power_enable)
+  {
+    HAL_SuspendTick();
+
+    /* Stop 1 mode with Main Regulator */
+    PWR->CR1 |= PWR_CR1_LPMS_1;
+    /* Set SLEEPDEEP bit of Cortex System Control Register. */
+    SCB->SCR |= (uint32_t)(SCB_SCR_SLEEPDEEP_Msk);
+  }
+  /* USER CODE END 2 */
+  /* USER CODE BEGIN HAL_PCD_SuspendCallback_PostTreatment */
+
+  /* USER CODE END HAL_PCD_SuspendCallback_PostTreatment */
+}
+
+/**
+  * @brief  Resume callback.
+  * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it)
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_ResumeCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_ResumeCallback_PreTreatment */
+
+  /* USER CODE BEGIN 3 */
+  if (hpcd->Init.low_power_enable)
+  {
+    HAL_ResumeTick();
+    /* Reset SLEEPDEEP bit of Cortex System Control Register. */
+    SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
+    SystemClockConfig_Resume();
+  }
+  /* USER CODE END 3 */
+ 
+  USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
+  /* USER CODE BEGIN HAL_PCD_ResumeCallback_PostTreatment */
+
+  /* USER CODE END HAL_PCD_ResumeCallback_PostTreatment */
+}
+
+/**
+  * @brief  ISOOUTIncomplete callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_ISOOUTIncompleteCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_ISOOUTIncompleteCallback_PreTreatment */
+  USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
+  /* USER CODE BEGIN HAL_PCD_ISOOUTIncompleteCallback_PostTreatment */
+
+  /* USER CODE END HAL_PCD_ISOOUTIncompleteCallback_PostTreatment */
+}
+
+/**
+  * @brief  ISOINIncomplete callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_ISOINIncompleteCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_ISOINIncompleteCallback_PreTreatment */
+  USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
+  /* USER CODE BEGIN HAL_PCD_ISOINIncompleteCallback_PostTreatment */
+
+  /* USER CODE END HAL_PCD_ISOINIncompleteCallback_PostTreatment */
+}
+
+/**
+  * @brief  Connect callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_ConnectCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_ConnectCallback_PreTreatment */
+  USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData);
+  /* USER CODE BEGIN HAL_PCD_ConnectCallback_PostTreatment */
+
+  /* USER CODE END HAL_PCD_ConnectCallback_PostTreatment */
+}
+
+/**
+  * @brief  Disconnect callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_DisconnectCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_DisconnectCallback_PreTreatment */
+  USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData);
+  /* USER CODE BEGIN HAL_PCD_DisconnectCallback_PostTreatment */
+
+  /* USER CODE END HAL_PCD_DisconnectCallback_PostTreatment */
+}
+
+  /* USER CODE BEGIN LowLevelInterface */
+
+  /* USER CODE END LowLevelInterface */
+
+/*******************************************************************************
+                       LL Driver Interface (USB Device Library --> PCD)
+*******************************************************************************/
+
+/**
+  * @brief  Initializes the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
+{
+  /* Init USB Ip. */
+  hpcd_USB_FS.pData = pdev;
+  /* Link the driver to the stack. */
+  pdev->pData = &hpcd_USB_FS;
+  /* Enable USB power on Pwrctrl CR2 register. */
+  HAL_PWREx_EnableVddUSB();
+
+  hpcd_USB_FS.Instance = USB;
+  hpcd_USB_FS.Init.dev_endpoints = 8;
+  hpcd_USB_FS.Init.speed = PCD_SPEED_FULL;
+  hpcd_USB_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
+  hpcd_USB_FS.Init.Sof_enable = DISABLE;
+  hpcd_USB_FS.Init.low_power_enable = DISABLE;
+  hpcd_USB_FS.Init.lpm_enable = DISABLE;
+  hpcd_USB_FS.Init.battery_charging_enable = DISABLE;
+
+  #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  /* register Msp Callbacks (before the Init) */
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_MSPINIT_CB_ID, PCD_MspInit);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_MSPDEINIT_CB_ID, PCD_MspDeInit);
+  #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+  if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK)
+  {
+    Error_Handler( );
+  }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  /* Register USB PCD CallBacks */
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SOF_CB_ID, PCD_SOFCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SETUPSTAGE_CB_ID, PCD_SetupStageCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_RESET_CB_ID, PCD_ResetCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SUSPEND_CB_ID, PCD_SuspendCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_RESUME_CB_ID, PCD_ResumeCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_CONNECT_CB_ID, PCD_ConnectCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_DISCONNECT_CB_ID, PCD_DisconnectCallback);
+  /* USER CODE BEGIN RegisterCallBackFirstPart */
+
+  /* USER CODE END RegisterCallBackFirstPart */
+  HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_FS, PCD_DataOutStageCallback);
+  HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_FS, PCD_DataInStageCallback);
+  HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_FS, PCD_ISOOUTIncompleteCallback);
+  HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_FS, PCD_ISOINIncompleteCallback);
+  /* USER CODE BEGIN RegisterCallBackSecondPart */
+
+  /* USER CODE END RegisterCallBackSecondPart */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  /* USER CODE BEGIN EndPoint_Configuration */
+  HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData, 0x00, PCD_SNG_BUF, 0x0C);
+  HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData, 0x80, PCD_SNG_BUF, 0x4C);
+  /* USER CODE END EndPoint_Configuration */
+  /* USER CODE BEGIN EndPoint_Configuration_HID */
+  HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData, HID_EPIN_ADDR, PCD_SNG_BUF, 0x8C);
+  /* USER CODE END EndPoint_Configuration_HID */
+  return USBD_OK;
+}
+
+/**
+  * @brief  De-Initializes the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_DeInit(pdev->pData);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+ 
+  return usb_status; 
+}
+
+/**
+  * @brief  Starts the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+ 
+  hal_status = HAL_PCD_Start(pdev->pData);
+     
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status;
+}
+
+/**
+  * @brief  Stops the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_Stop(pdev->pData);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status;
+}
+
+/**
+  * @brief  Opens an endpoint of the low level driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @param  ep_type: Endpoint type
+  * @param  ep_mps: Endpoint max packet size
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+ 
+  return usb_status;
+}
+
+/**
+  * @brief  Closes an endpoint of the low level driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
+      
+  usb_status =  USBD_Get_USB_Status(hal_status);
+
+  return usb_status;  
+}
+
+/**
+  * @brief  Flushes an endpoint of the Low Level Driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr);
+      
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status;  
+}
+
+/**
+  * @brief  Sets a Stall condition on an endpoint of the Low Level Driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+ 
+  return usb_status;  
+}
+
+/**
+  * @brief  Clears a Stall condition on an endpoint of the Low Level Driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);  
+     
+  usb_status =  USBD_Get_USB_Status(hal_status);
+
+  return usb_status; 
+}
+
+/**
+  * @brief  Returns Stall condition.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval Stall (1: Yes, 0: No)
+  */
+uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
+  
+  if((ep_addr & 0x80) == 0x80)
+  {
+    return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 
+  }
+  else
+  {
+    return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 
+  }
+}
+
+/**
+  * @brief  Assigns a USB address to the device.
+  * @param  pdev: Device handle
+  * @param  dev_addr: Device address
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
+     
+  usb_status =  USBD_Get_USB_Status(hal_status);
+ 
+  return usb_status;  
+}
+
+/**
+  * @brief  Transmits data over an endpoint.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @param  pbuf: Pointer to data to be sent
+  * @param  size: Data size    
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
+     
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status;    
+}
+
+/**
+  * @brief  Prepares an endpoint for reception.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @param  pbuf: Pointer to data to be received
+  * @param  size: Data size
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
+     
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  	
+  return usb_status; 
+}
+
+/**
+  * @brief  Returns the last transfered packet size.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval Recived Data Size
+  */
+uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
+}
+
+/**
+  * @brief  Delays routine for the USB Device Library.
+  * @param  Delay: Delay in ms
+  * @retval None
+  */
+void USBD_LL_Delay(uint32_t Delay)
+{
+  HAL_Delay(Delay);
+}
+
+/**
+  * @brief  Static single allocation.
+  * @param  size: Size of allocated memory
+  * @retval None
+  */
+void *USBD_static_malloc(uint32_t size)
+{
+  static uint32_t mem[(sizeof(USBD_HID_HandleTypeDef)/4)+1];/* On 32-bit boundary */
+  return mem;
+}
+
+/**
+  * @brief  Dummy memory free
+  * @param  p: Pointer to allocated  memory address
+  * @retval None
+  */
+void USBD_static_free(void *p)
+{
+
+}
+
+/* USER CODE BEGIN 5 */
+/**
+  * @brief  Configures system clock after wake-up from USB resume callBack:
+  *         enable HSI, PLL and select PLL as system clock source.
+  * @retval None
+  */
+ void SystemClockConfig_Resume(void)
+{
+  SystemClock_Config();
+  USBD_Clock_Config();
+}
+/* USER CODE END 5 */
+
+/**
+  * @brief  Retuns the USB status depending on the HAL status:
+  * @param  hal_status: HAL status
+  * @retval USB status
+  */
+USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
+{
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  switch (hal_status)
+  {
+    case HAL_OK :
+      usb_status = USBD_OK;
+    break;
+    case HAL_ERROR :
+      usb_status = USBD_FAIL;
+    break;
+    case HAL_BUSY :
+      usb_status = USBD_BUSY;
+    break;
+    case HAL_TIMEOUT :
+      usb_status = USBD_FAIL;
+    break;
+    default :
+      usb_status = USBD_FAIL;
+    break;
+  }
+  return usb_status;
+}
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/Target/usbd_conf.h b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/Target/usbd_conf.h
new file mode 100644
index 000000000..5ccdf091e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/USB_Device/Target/usbd_conf.h
@@ -0,0 +1,179 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           USB_Device/HID_Standalone/USB_Device/Target/usbd_conf.h
+  * @author         MCD Application Team
+  * @brief          Header for usbd_conf.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_CONF__H__
+#define __USBD_CONF__H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include 
+#include 
+#include 
+#include "stm32wbxx.h"
+#include "stm32wbxx_hal.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/** @addtogroup USBD_OTG_DRIVER
+  * @brief Driver for Usb device.
+  * @{
+  */
+
+/** @defgroup USBD_CONF USBD_CONF
+  * @brief Configuration file for Usb otg low level driver.
+  * @{
+  */
+
+/** @defgroup USBD_CONF_Exported_Variables USBD_CONF_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+/* USER CODE END PV */
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_Defines USBD_CONF_Exported_Defines
+  * @brief Defines for configuration of the Usb device.
+  * @{
+  */
+
+/*---------- -----------*/
+#define USBD_MAX_NUM_INTERFACES     1U
+/*---------- -----------*/
+#define USBD_MAX_NUM_CONFIGURATION     1U
+/*---------- -----------*/
+#define USBD_MAX_STR_DESC_SIZ     64U
+/*---------- -----------*/
+#define USBD_DEBUG_LEVEL     0U
+/*---------- -----------*/
+#define USBD_LPM_ENABLED     0U
+/*---------- -----------*/
+#define USBD_SELF_POWERED     1U
+/*---------- -----------*/
+#define HID_FS_BINTERVAL     0xAU
+
+/****************************************/
+/* #define for FS and HS identification */
+#define DEVICE_FS 		0
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_Macros USBD_CONF_Exported_Macros
+  * @brief Aliases.
+  * @{
+  */
+
+/* Memory management macros */
+
+/** Alias for memory allocation. */
+#define USBD_malloc         (uint32_t *)USBD_static_malloc
+
+/** Alias for memory release. */
+#define USBD_free           USBD_static_free
+
+/** Alias for memory set. */
+#define USBD_memset         /* Not used */
+
+/** Alias for memory copy. */
+#define USBD_memcpy         /* Not used */
+
+/** Alias for delay. */
+#define USBD_Delay          HAL_Delay
+
+/* DEBUG macros */
+
+#if (USBD_DEBUG_LEVEL > 0)
+#define USBD_UsrLog(...)    printf(__VA_ARGS__);\
+                            printf("\n");
+#else
+#define USBD_UsrLog(...)
+#endif
+
+#if (USBD_DEBUG_LEVEL > 1)
+
+#define USBD_ErrLog(...)    printf("ERROR: ") ;\
+                            printf(__VA_ARGS__);\
+                            printf("\n");
+#else
+#define USBD_ErrLog(...)
+#endif
+
+#if (USBD_DEBUG_LEVEL > 2)
+#define USBD_DbgLog(...)    printf("DEBUG : ") ;\
+                            printf(__VA_ARGS__);\
+                            printf("\n");
+#else
+#define USBD_DbgLog(...)
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_Types USBD_CONF_Exported_Types
+  * @brief Types.
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_FunctionsPrototype USBD_CONF_Exported_FunctionsPrototype
+  * @brief Declaration of public functions for Usb device.
+  * @{
+  */
+
+/* Exported functions -------------------------------------------------------*/
+void *USBD_static_malloc(uint32_t size);
+void USBD_static_free(void *p);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_CONF__H__ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/readme.txt b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/readme.txt
new file mode 100644
index 000000000..e086acb71
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/HID_Standalone/readme.txt
@@ -0,0 +1,101 @@
+/**
+  @page HID_Standalone USB Device Human Interface (HID) application
+
+  @verbatim
+  ******************************************************************************
+  * @file    USB_Device/HID_Standalone/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the USB HID application.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                               www.st.com/SLA0044
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Application Description
+
+Use of the USB device application based on the Human Interface (HID).
+  This is a typical application on how to use the stm32wbxx USB Device peripheral, where the STM32 MCU is
+enumerated as a HID device using the native PC Host HID driver to which the NUCLEO-WB35CE
+board is connected, in order to emulate the Mouse directions using User push-button mounted on the
+NUCLEO-WB35CE board.
+
+At the beginning of the main program the HAL_Init() function is called to reset all the peripherals,
+initialize the Flash interface and the systick. The user is provided with the SystemClock_Config()
+function to configure the system clock (SYSCLK). The Full Speed (FS) USB module uses
+internally a 48-MHz clock which is coming from a specific output of two PLLs (PLL or PLL SAI) or from MSI
+
+This example supports remote wakeup (which is the ability of a USB device to bring a suspended bus back
+to the active condition), and the User push-button is used as the remote wakeup source.
+
+By default, in Windows powered PC the Power Management feature of USB mouse devices is turned off.
+This setting is different from classic PS/2 computer functionality. Therefore, to enable the Wake from
+standby option, user must manually turn on the Power Management feature for the USB mouse.
+
+To manually enable the wake from standby option for the USB mouse, proceed as follows:
+ - Start "Device Manager",
+ - Select "Mice and other pointing devices",
+ - Select the "HID-compliant mouse" device (make sure that PID & VID are equal to 0x5710 & 0x0483 respectively)
+ - Right click and select "Properties",
+ - Select "Power Management" tab,
+ - Finally click to select "Allow this device to wake the computer" check box.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+For more details about the STM32Cube USB Device library, please refer to UM1734
+"STM32Cube USB Device library".
+
+@par Keywords
+
+Connectivity, USB Device, HID, Full Speed, Mouse, Remote Wakeup
+
+@par Directory contents
+
+  - USB_Device/HID_Standalone/Core/Src/main.c                  Main program
+  - USB_Device/HID_Standalone/Core/Src/stm32wbxx_hal_msp.c     MSP Initialization and de-Initialization codes
+  - USB_Device/HID_Standalone/Core/Src/system_stm32wbxx.c      STM32WBxx system clock configuration file
+  - USB_Device/HID_Standalone/Core/Src/stm32wbxx_it.c          Interrupt handlers
+  - USB_Device/HID_Standalone/USB_Device/Target/usbd_conf.c    General low level driver configuration
+  - USB_Device/HID_Standalone/USB_Device/App/usbd_desc.c       USB device HID descriptor
+  - USB_Device/HID_Standalone/USB_Device/App/usbd_device.c     USB Device
+  - USB_Device/HID_Standalone/Core/Inc/main.h                  Main program header file
+  - USB_Device/HID_Standalone/Core/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - USB_Device/HID_Standalone/Core/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - USB_Device/HID_Standalone/USB_Device/Target/usbd_conf.h    USB device driver Configuration file
+  - USB_Device/HID_Standalone/USB_Device/App/usbd_desc.h       USB device HID descriptor header file
+  - USB_Device/HID_Standalone/USB_Device/App/usbd_device.h     USB Device header
+
+
+@par Hardware and Software environment
+
+  - This application runs on STM32WBxx devices.
+
+  - This application has been tested with STMicroelectronics NUCLEO-WB35CE board
+    and can be easily tailored to any other supported device and development board.
+
+  - NUCLEO-WB35CE board Set-up
+    - Connect the NUCLEO-WB35CE board CN1 to the PC through micro A-Male to standard A Male cable.
+    - Press the User push-button (SW1)  to move the cursor.
+
+@par How to use it ?
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the application
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/.extSettings b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/.extSettings
new file mode 100644
index 000000000..6fe67f7d3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/.extSettings
@@ -0,0 +1,14 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE;..\..\..\..\..\..\Drivers\BSP\Adafruit_Shield;..\..\..\..\..\..\Drivers\BSP\Components;..\..\..\..\..\..\Drivers\BSP\Components\Common
+[Others]
+Define=USE_STM32WBXX_NUCLEO
+HALModule=SPI
+[Groups]
+Application/User/Core=../Core/Src/main.c;../Core/Src/stm32wbxx_it.c;../Core/Src/stm32wbxx_hal_msp.c;../Core/Src/stm32wbxx_hal_msp.c;
+Application/User/USB_Device/App=../USB_Device/App/usbd_desc.c;../USB_Device/App/usbd_storage_if.c;../USB_Device/App/usb_device.c;
+Application/User/USB_Device/Target=../USB_Device/Target/usbd_conf.c;
+Doc=../readme.txt;
+Drivers/BSP/Adafruit_Shield=../../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_sd.c;../../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_lcd.c;
+Drivers/BSP/Components=../../../../../../Drivers/BSP/Components/st7735/st7735.c;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
+Drivers/STM32WBxx_HAL_Driver=../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c;../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c;
\ No newline at end of file
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Inc/main.h b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Inc/main.h
new file mode 100644
index 000000000..2d9db6d24
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Inc/main.h
@@ -0,0 +1,76 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    USB_Device/MSC_Standalone/Core/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "usbd_core.h"
+#include "usbd_desc.h"
+#include "usbd_msc.h"
+#include "usbd_storage_if.h"
+#include "nucleo_wb35ce.h"
+#include "stm32_adafruit_sd.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..e4bf02655
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+#define HAL_PCD_MODULE_ENABLED
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+#define HAL_SPI_MODULE_ENABLED
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..29e322d81
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Inc/stm32wbxx_it.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    USB_Device/MSC_Standalone/Core/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void USB_LP_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Src/main.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Src/main.c
new file mode 100644
index 000000000..021dc743d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Src/main.c
@@ -0,0 +1,227 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    USB_Device/MSC_Standalone/Core/Src/main.c
+  * @author  MCD Application Team
+  * @brief   USB device MSC demo main file
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "usb_device.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* Configure LEDs */
+  BSP_LED_Init(LED1);
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_USB_Device_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief This function provides accurate delay (in milliseconds) based
+  * on SysTick counter flag.
+  * @note This function is declared as __weak to be overwritten in case of other
+  * implementations in user file.
+  * @param Delay: specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+void HAL_Delay(__IO uint32_t Delay)
+{
+  while (Delay)
+  {
+    if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)
+    {
+      Delay--;
+    }
+  }
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  /* Turn LED1 on */
+  BSP_LED_On(LED1);
+
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..bf32bc604
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,83 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    USB_Device/MSC_Standalone/Core/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  *          This file provides code for the MSP Initialization
+  *          and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..31223addd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Src/stm32wbxx_it.c
@@ -0,0 +1,221 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    USB_Device/MSC_Standalone/Core/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern PCD_HandleTypeDef hpcd_USB_FS;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles USB low priority interrupt, USB wake-up interrupt through EXTI line 28.
+  */
+void USB_LP_IRQHandler(void)
+{
+  /* USER CODE BEGIN USB_LP_IRQn 0 */
+
+  /* USER CODE END USB_LP_IRQn 0 */
+  HAL_PCD_IRQHandler(&hpcd_USB_FS);
+  /* USER CODE BEGIN USB_LP_IRQn 1 */
+
+  /* USER CODE END USB_LP_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..4cb9e0e42
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/Core/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx) || defined(STM32WB5Mxx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/MSC_Standalone.ewd b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/MSC_Standalone.ewd
new file mode 100644
index 000000000..18648e590
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/MSC_Standalone.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		MSC_Standalone
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/MSC_Standalone.ewp b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/MSC_Standalone.ewp
new file mode 100644
index 000000000..85224ed7a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/MSC_Standalone.ewp
@@ -0,0 +1,1208 @@
+
+
+  3
+  
+    MSC_Standalone
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        Core
+        
+          $PROJ_DIR$/../Core/Src/main.c
+        
+        
+          $PROJ_DIR$/../Core/Src/stm32wbxx_it.c
+        
+        
+          $PROJ_DIR$/../Core/Src/stm32wbxx_hal_msp.c
+        
+      
+      
+        USB_Device
+        
+          App
+          
+            $PROJ_DIR$/../USB_Device/App/usbd_desc.c
+          
+          
+            $PROJ_DIR$/../USB_Device/App/usbd_storage_if.c
+          
+          
+            $PROJ_DIR$/../USB_Device/App/usb_device.c
+          
+        
+        
+          Target
+          
+            $PROJ_DIR$/../USB_Device/Target/usbd_conf.c
+          
+        
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        Adafruit_Shield
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_sd.c
+        
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_lcd.c
+        
+      
+      
+        Components
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/Components/st7735/st7735.c
+        
+      
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Core/Src/system_stm32wbxx.c
+      
+    
+  
+  
+    Middlewares
+    
+      USB_Device_Library
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_bot.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_data.c
+      
+      
+        $PROJ_DIR$/../../../../../../Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_scsi.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/Project.eww
new file mode 100644
index 000000000..c55141cda
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\MSC_Standalone.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..43a793371
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/stm32wb35xx_sram_cm4.icf b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/stm32wb35xx_sram_cm4.icf
new file mode 100644
index 000000000..572eeb981
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/EWARM/stm32wb35xx_sram_cm4.icf
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20003FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20004000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20008000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x2000FFFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MDK-ARM/MSC_Standalone.uvoptx b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MDK-ARM/MSC_Standalone.uvoptx
new file mode 100644
index 000000000..ee4ca2802
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MDK-ARM/MSC_Standalone.uvoptx
@@ -0,0 +1,765 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    MSC_Standalone
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U0667FF303337554E43181419 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User/Core
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Core/Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Core/Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      2
+      4
+      1
+      0
+      0
+      0
+      ../Core/Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Application/User/USB_Device/App
+    0
+    0
+    0
+    0
+    
+      3
+      5
+      1
+      0
+      0
+      0
+      ../USB_Device/App/usbd_desc.c
+      usbd_desc.c
+      0
+      0
+    
+    
+      3
+      6
+      1
+      0
+      0
+      0
+      ../USB_Device/App/usbd_storage_if.c
+      usbd_storage_if.c
+      0
+      0
+    
+    
+      3
+      7
+      1
+      0
+      0
+      0
+      ../USB_Device/App/usb_device.c
+      usb_device.c
+      0
+      0
+    
+  
+
+  
+    Application/User/USB_Device/Target
+    0
+    0
+    0
+    0
+    
+      4
+      8
+      1
+      0
+      0
+      0
+      ../USB_Device/Target/usbd_conf.c
+      usbd_conf.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      5
+      9
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/Adafruit_Shield
+    0
+    0
+    0
+    0
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_sd.c
+      stm32_adafruit_sd.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_lcd.c
+      stm32_adafruit_lcd.c
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/Components
+    0
+    0
+    0
+    0
+    
+      7
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/Components/st7735/st7735.c
+      st7735.c
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      8
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      9
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+      stm32wbxx_hal_spi.c
+      0
+      0
+    
+    
+      9
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+      stm32wbxx_hal_spi_ex.c
+      0
+      0
+    
+    
+      9
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      9
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c
+      stm32wbxx_hal_pcd.c
+      0
+      0
+    
+    
+      9
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd_ex.c
+      stm32wbxx_hal_pcd_ex.c
+      0
+      0
+    
+    
+      9
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c
+      stm32wbxx_ll_usb.c
+      0
+      0
+    
+    
+      9
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      9
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      9
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      9
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      9
+      24
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      9
+      25
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      9
+      26
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      9
+      27
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      9
+      28
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      9
+      29
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      9
+      30
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      9
+      31
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      9
+      32
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      9
+      33
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      10
+      34
+      1
+      0
+      0
+      0
+      ../Core/Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    Middlewares/USB_Device_Library
+    0
+    0
+    0
+    0
+    
+      11
+      35
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c
+      usbd_core.c
+      0
+      0
+    
+    
+      11
+      36
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
+      usbd_ctlreq.c
+      0
+      0
+    
+    
+      11
+      37
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
+      usbd_ioreq.c
+      0
+      0
+    
+    
+      11
+      38
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc.c
+      usbd_msc.c
+      0
+      0
+    
+    
+      11
+      39
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_bot.c
+      usbd_msc_bot.c
+      0
+      0
+    
+    
+      11
+      40
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_data.c
+      usbd_msc_data.c
+      0
+      0
+    
+    
+      11
+      41
+      1
+      0
+      0
+      0
+      ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_scsi.c
+      usbd_msc_scsi.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MDK-ARM/MSC_Standalone.uvprojx b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MDK-ARM/MSC_Standalone.uvprojx
new file mode 100644
index 000000000..80c9cbed0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MDK-ARM/MSC_Standalone.uvprojx
@@ -0,0 +1,662 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      MSC_Standalone
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          MSC_Standalone\
+          MSC_Standalone
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4101
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          "" ()
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_STM32WBXX_NUCLEO,USE_HAL_DRIVER,STM32WB35xx
+              
+              ../USB_Device/App;../USB_Device/Target;../Core/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Inc;../../../../../../Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE;../../../../../../Drivers/BSP/Adafruit_Shield;../../../../../../Drivers/BSP/Components;../../../../../../Drivers/BSP/Components/Common
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User/Core
+          
+            
+              main.c
+              1
+              ../Core/Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Core/Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Core/Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Application/User/USB_Device/App
+          
+            
+              usbd_desc.c
+              1
+              ../USB_Device/App/usbd_desc.c
+            
+            
+              usbd_storage_if.c
+              1
+              ../USB_Device/App/usbd_storage_if.c
+            
+            
+              usb_device.c
+              1
+              ../USB_Device/App/usb_device.c
+            
+          
+        
+        
+          Application/User/USB_Device/Target
+          
+            
+              usbd_conf.c
+              1
+              ../USB_Device/Target/usbd_conf.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/Adafruit_Shield
+          
+            
+              stm32_adafruit_sd.c
+              1
+              ../../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_sd.c
+            
+            
+              stm32_adafruit_lcd.c
+              1
+              ../../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_lcd.c
+            
+          
+        
+        
+          Drivers/BSP/Components
+          
+            
+              st7735.c
+              1
+              ../../../../../../Drivers/BSP/Components/st7735/st7735.c
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_spi.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+            
+            
+              stm32wbxx_hal_spi_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_pcd.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c
+            
+            
+              stm32wbxx_hal_pcd_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd_ex.c
+            
+            
+              stm32wbxx_ll_usb.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Core/Src/system_stm32wbxx.c
+            
+          
+        
+        
+          Middlewares/USB_Device_Library
+          
+            
+              usbd_core.c
+              1
+              ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c
+            
+            
+              usbd_ctlreq.c
+              1
+              ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
+            
+            
+              usbd_ioreq.c
+              1
+              ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
+            
+            
+              usbd_msc.c
+              1
+              ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc.c
+            
+            
+              usbd_msc_bot.c
+              1
+              ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_bot.c
+            
+            
+              usbd_msc_data.c
+              1
+              ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_data.c
+            
+            
+              usbd_msc_scsi.c
+              1
+              ../../../../../../Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_scsi.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..ae049b184
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x1000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x1000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MSC_Standalone.ioc b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MSC_Standalone.ioc
new file mode 100644
index 000000000..6456fddbd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/MSC_Standalone.ioc
@@ -0,0 +1,152 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=USB
+Mcu.IP4=USB_DEVICE
+Mcu.IPNb=5
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA11
+Mcu.Pin1=PA12
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.Pin3=VP_USB_DEVICE_VS_USB_DEVICE_MSC_FS
+Mcu.PinsNb=4
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.USB_LP_IRQn=true\:6\:0\:true\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA11.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Mode
+PA11.GPIO_Mode=GPIO_MODE_AF_PP
+PA11.GPIO_PuPd=GPIO_NOPULL
+PA11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA11.Mode=Device
+PA11.Signal=USB_DM
+PA12.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Mode
+PA12.GPIO_Mode=GPIO_MODE_AF_PP
+PA12.GPIO_PuPd=GPIO_NOPULL
+PA12.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA12.Mode=Device
+PA12.Signal=USB_DP
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=3
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x1000
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=false
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Core/Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=MSC_Standalone.ioc
+ProjectManager.ProjectName=MSC_Standalone
+ProjectManager.StackSize=0x1000
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USB_Device_Init-USB_DEVICE-false-HAL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+USB.DeviceSpeed=PCD_SPEED_FULL
+USB.IPParameters=DeviceSpeed,phy_itface,Sof_enable,low_power_enable,lpm_enable,battery_charging_enable
+USB.Sof_enable=DISABLE
+USB.battery_charging_enable=DISABLE
+USB.low_power_enable=DISABLE
+USB.lpm_enable=DISABLE
+USB.phy_itface=PCD_PHY_EMBEDDED
+USB_DEVICE.CLASS_NAME_FS=MSC
+USB_DEVICE.CONFIGURATION_STRING_MSC_FS=MSC Config
+USB_DEVICE.INTERFACE_STRING_MSC_FS=MSC Interface
+USB_DEVICE.IPParameters=VirtualMode,VirtualModeFS,CLASS_NAME_FS,USBD_MAX_STR_DESC_SIZ,VID,PID_MSC_FS,PRODUCT_STRING_MSC_FS,USBD_LPM_ENABLED,USBD_MAX_NUM_INTERFACES,USBD_MAX_NUM_CONFIGURATION,USBD_SELF_POWERED,USBD_DEBUG_LEVEL,LANGID_STRING,MANUFACTURER_STRING,CONFIGURATION_STRING_MSC_FS,INTERFACE_STRING_MSC_FS,MSC_MEDIA_PACKET
+USB_DEVICE.IPParametersWithoutCheck=USBD_MAX_STR_DESC_SIZ,USBD_MAX_NUM_INTERFACES
+USB_DEVICE.LANGID_STRING=1033
+USB_DEVICE.MANUFACTURER_STRING=STMicroelectronics
+USB_DEVICE.MSC_MEDIA_PACKET=512
+USB_DEVICE.PID_MSC_FS=0x5720
+USB_DEVICE.PRODUCT_STRING_MSC_FS=Mass Storage in FS Mode
+USB_DEVICE.USBD_DEBUG_LEVEL=0
+USB_DEVICE.USBD_LPM_ENABLED=0
+USB_DEVICE.USBD_MAX_NUM_CONFIGURATION=1
+USB_DEVICE.USBD_MAX_NUM_INTERFACES=1
+USB_DEVICE.USBD_MAX_STR_DESC_SIZ=64
+USB_DEVICE.USBD_SELF_POWERED=1
+USB_DEVICE.VID=0x483
+USB_DEVICE.VirtualMode=Msc
+USB_DEVICE.VirtualModeFS=Msc_FS
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+VP_USB_DEVICE_VS_USB_DEVICE_MSC_FS.Mode=MSC_FS
+VP_USB_DEVICE_VS_USB_DEVICE_MSC_FS.Signal=USB_DEVICE_VS_USB_DEVICE_MSC_FS
+board=NUCLEO-WB55RG
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..c8bbb639f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/.cproject
@@ -0,0 +1,185 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/.project
new file mode 100644
index 000000000..093e7e654
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/.project
@@ -0,0 +1,241 @@
+
+
+	MSC_Standalone
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			MSC_Standalone.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/MSC_Standalone.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Core/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Core/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Core/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Core/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pcd.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pcd_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_spi.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_spi_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_usb.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c
+		
+		
+			Middlewares/USB_Device_Library/usbd_core.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c
+		
+		
+			Middlewares/USB_Device_Library/usbd_ctlreq.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
+		
+		
+			Middlewares/USB_Device_Library/usbd_ioreq.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
+		
+		
+			Middlewares/USB_Device_Library/usbd_msc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc.c
+		
+		
+			Middlewares/USB_Device_Library/usbd_msc_bot.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_bot.c
+		
+		
+			Middlewares/USB_Device_Library/usbd_msc_data.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_data.c
+		
+		
+			Middlewares/USB_Device_Library/usbd_msc_scsi.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_scsi.c
+		
+		
+			Drivers/BSP/Adafruit_Shield/stm32_adafruit_lcd.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/Adafruit_Shield/stm32_adafruit_lcd.c
+		
+		
+			Drivers/BSP/Adafruit_Shield/stm32_adafruit_sd.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/Adafruit_Shield/stm32_adafruit_sd.c
+		
+		
+			Drivers/BSP/Components/st7735.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/Components/st7735/st7735.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+		
+			Application/User/USB_Device/App/usb_device.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/USB_Device/App/usb_device.c
+		
+		
+			Application/User/USB_Device/App/usbd_desc.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/USB_Device/App/usbd_desc.c
+		
+		
+			Application/User/USB_Device/App/usbd_storage_if.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/USB_Device/App/usbd_storage_if.c
+		
+		
+			Application/User/USB_Device/Target/usbd_conf.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/USB_Device/Target/usbd_conf.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..eea98ff9c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb35xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB35xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f9a002eb7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x1000 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x1000 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usb_device.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usb_device.c
new file mode 100644
index 000000000..81a996d18
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usb_device.c
@@ -0,0 +1,181 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    USB_Device/MSC_Standalone/USB_Device/App/usb_device.c
+  * @author  MCD Application Team
+  * @brief   This file implements the USB Device
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+ 
+#include "usb_device.h"
+#include "usbd_core.h"
+#include "usbd_desc.h"
+#include "usbd_msc.h"
+#include "usbd_storage_if.h"
+
+/* USER CODE BEGIN Includes */
+#include "main.h"
+/* USER CODE END Includes */
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+typedef enum
+{
+  SHIELD_NOT_DETECTED = 0,
+  SHIELD_DETECTED
+}ShieldStatus;
+/* USER CODE END PV */
+
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+void USBD_Clock_Config(void);
+static ShieldStatus TFT_ShieldDetect(void);
+/* USER CODE END PFP */
+
+extern void Error_Handler(void);
+/* USB Device Core handle declaration. */
+USBD_HandleTypeDef hUsbDeviceFS;
+extern USBD_DescriptorsTypeDef MSC_Desc;
+
+/*
+ * -- Insert your variables declaration here --
+ */
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/*
+ * -- Insert your external function declaration here --
+ */
+/* USER CODE BEGIN 1 */
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void USBD_Clock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
+
+  /* Enable HSI48 */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct)!= HAL_OK)
+  {
+    Error_Handler();
+  }
+  /*Configure the clock recovery system (CRS)**********************************/
+
+  /*Enable CRS Clock*/
+  __HAL_RCC_CRS_CLK_ENABLE();
+
+  /* Default Synchro Signal division factor (not divided) */
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+
+  /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+
+  /* HSI48 is synchronized with USB SOF at 1KHz rate */
+  RCC_CRSInitStruct.ReloadValue =  __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
+  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+
+  /* Set the TRIM[5:0] to the default value */
+  RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+
+  /* Start automatic synchronization */
+  HAL_RCCEx_CRSConfig (&RCC_CRSInitStruct);
+}
+
+/**
+  * @brief  Check the availability of adafruit 1.8" TFT shield on top of STM32NUCLEO
+  *         board. This is done by reading the state of IO PF.03 pin (mapped to
+  *         JoyStick available on adafruit 1.8" TFT shield). If the state of PF.03
+  *         is high then the adafruit 1.8" TFT shield is available.
+  * @param  None
+  * @retval SHIELD_DETECTED: 1.8" TFT shield is available
+  *         SHIELD_NOT_DETECTED: 1.8" TFT shield is not available
+  */
+static ShieldStatus TFT_ShieldDetect(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStruct;
+
+  /* Enable GPIO clock */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+  GPIO_InitStruct.Pin = GPIO_PIN_0;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  if (HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_0) != 0U)
+  {
+    return SHIELD_DETECTED;
+  }
+  else
+  {
+    return SHIELD_NOT_DETECTED;
+  }
+}
+/* USER CODE END 1 */
+
+/**
+  * Init USB device Library, add supported class and start the library
+  * @retval None
+  */
+void MX_USB_Device_Init(void)
+{
+  /* USER CODE BEGIN USB_Device_Init_PreTreatment */
+  /* Check the availability of adafruit 1.8" TFT shield on top of STM32NUCLEO
+     board. This is done by reading the state of IO PF.03 pin (mapped to JoyStick
+     available on adafruit 1.8" TFT shield). If the state of PF.03 is high then
+     the adafruit 1.8" TFT shield is available. */
+  if(TFT_ShieldDetect() != SHIELD_DETECTED)
+  {
+    Error_Handler();
+  }
+  /* Enable USB Device clock */
+  USBD_Clock_Config();
+  /* USER CODE END USB_Device_Init_PreTreatment */
+  
+  /* Init Device Library, add supported class and start the library. */
+  if (USBD_Init(&hUsbDeviceFS, &MSC_Desc, DEVICE_FS) != USBD_OK) {
+    Error_Handler();
+  }
+  if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_MSC) != USBD_OK) {
+    Error_Handler();
+  }
+  if (USBD_MSC_RegisterStorage(&hUsbDeviceFS, &USBD_Storage_Interface_fops_FS) != USBD_OK) {
+    Error_Handler();
+  }
+  if (USBD_Start(&hUsbDeviceFS) != USBD_OK) {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USB_Device_Init_PostTreatment */
+
+  /* USER CODE END USB_Device_Init_PostTreatment */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usb_device.h b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usb_device.h
new file mode 100644
index 000000000..e958065eb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usb_device.h
@@ -0,0 +1,105 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           USB_Device/msc_Standalone/USB_Device/App/usb_device.h
+  * @author         MCD Application Team
+  * @brief          Header for usb_device.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_DEVICE__H__
+#define __USB_DEVICE__H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx.h"
+#include "stm32wbxx_hal.h"
+#include "usbd_def.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/** @addtogroup USBD_OTG_DRIVER
+  * @{
+  */
+
+/** @defgroup USBD_DEVICE USBD_DEVICE
+  * @brief Device file for Usb otg low level driver.
+  * @{
+  */
+
+/** @defgroup USBD_DEVICE_Exported_Variables USBD_DEVICE_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/*
+ * -- Insert your variables declaration here --
+ */
+/* USER CODE BEGIN VARIABLES */
+
+/* USER CODE END VARIABLES */
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DEVICE_Exported_FunctionsPrototype USBD_DEVICE_Exported_FunctionsPrototype
+  * @brief Declaration of public functions for Usb device.
+  * @{
+  */
+
+/** USB Device initialization function. */
+void MX_USB_Device_Init(void);
+
+/*
+ * -- Insert functions declaration here --
+ */
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_DEVICE__H__ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usbd_desc.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usbd_desc.c
new file mode 100644
index 000000000..1a6b8367b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usbd_desc.c
@@ -0,0 +1,397 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           USB_Device/MSC_Standalone/USB_Device/App/usbd_desc.c
+  * @author         MCD Application Team
+  * @brief          This file implements the USB device descriptors.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_core.h"
+#include "usbd_desc.h"
+#include "usbd_conf.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @addtogroup USBD_DESC
+  * @{
+  */
+
+/** @defgroup USBD_DESC_Private_TypesDefinitions USBD_DESC_Private_TypesDefinitions
+  * @brief Private types.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_TYPES */
+
+/* USER CODE END PRIVATE_TYPES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Defines USBD_DESC_Private_Defines
+  * @brief Private defines.
+  * @{
+  */
+
+#define USBD_VID     0x483
+#define USBD_LANGID_STRING     1033
+#define USBD_MANUFACTURER_STRING     "STMicroelectronics"
+#define USBD_PID     0x5720
+#define USBD_PRODUCT_STRING     "Mass Storage in FS Mode"
+#define USBD_CONFIGURATION_STRING     "MSC Config"
+#define USBD_INTERFACE_STRING     "MSC Interface"
+
+/* USER CODE BEGIN PRIVATE_DEFINES */
+
+/* USER CODE END PRIVATE_DEFINES */
+
+/**
+  * @}
+  */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/** @defgroup USBD_DESC_Private_Macros USBD_DESC_Private_Macros
+  * @brief Private macros.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_MACRO */
+
+/* USER CODE END PRIVATE_MACRO */
+
+/**
+  * @}
+  */
+  
+/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
+  * @brief Private functions declaration.
+  * @{
+  */
+  
+static void Get_SerialNum(void);
+static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len);
+  
+/**
+  * @}
+  */  
+  
+
+/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
+  * @brief Private functions declaration.
+  * @{
+  */
+
+uint8_t * USBD_MSC_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_MSC_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_MSC_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_MSC_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_MSC_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_MSC_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_MSC_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables
+  * @brief Private variables.
+  * @{
+  */
+
+USBD_DescriptorsTypeDef MSC_Desc =
+{
+  USBD_MSC_DeviceDescriptor, 
+  USBD_MSC_LangIDStrDescriptor, 
+  USBD_MSC_ManufacturerStrDescriptor, 
+  USBD_MSC_ProductStrDescriptor, 
+  USBD_MSC_SerialStrDescriptor, 
+  USBD_MSC_ConfigStrDescriptor, 
+  USBD_MSC_InterfaceStrDescriptor
+};
+
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+/** USB standard device descriptor. */
+__ALIGN_BEGIN uint8_t USBD_MSC_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END =
+{
+  0x12,                       /*bLength */
+  USB_DESC_TYPE_DEVICE,       /*bDescriptorType*/
+  0x00,                       /*bcdUSB */
+  0x02,
+  0x00,                       /*bDeviceClass*/
+  0x00,                       /*bDeviceSubClass*/
+  0x00,                       /*bDeviceProtocol*/
+  USB_MAX_EP0_SIZE,           /*bMaxPacketSize*/
+  LOBYTE(USBD_VID),           /*idVendor*/
+  HIBYTE(USBD_VID),           /*idVendor*/
+  LOBYTE(USBD_PID),           /*idProduct*/
+  HIBYTE(USBD_PID),           /*idProduct*/
+  0x00,                       /*bcdDevice rel. 2.00*/
+  0x02,
+  USBD_IDX_MFC_STR,           /*Index of manufacturer  string*/
+  USBD_IDX_PRODUCT_STR,       /*Index of product string*/
+  USBD_IDX_SERIAL_STR,        /*Index of serial number string*/
+  USBD_MAX_NUM_CONFIGURATION  /*bNumConfigurations*/
+};
+
+/* USB_DeviceDescriptor */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables
+  * @brief Private variables.
+  * @{
+  */
+
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+
+/** USB lang indentifier descriptor. */
+__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END =
+{
+     USB_LEN_LANGID_STR_DESC,
+     USB_DESC_TYPE_STRING,
+     LOBYTE(USBD_LANGID_STRING),
+     HIBYTE(USBD_LANGID_STRING)
+};
+
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+/* Internal string descriptor. */
+__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END;
+
+#if defined ( __ICCARM__ ) /*!< IAR Compiler */
+  #pragma data_alignment=4   
+#endif
+__ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] __ALIGN_END = {
+  USB_SIZ_STRING_SERIAL,
+  USB_DESC_TYPE_STRING,
+};
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Functions USBD_DESC_Private_Functions
+  * @brief Private functions.
+  * @{
+  */
+
+/**
+  * @brief  Return the device descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_MSC_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  *length = sizeof(USBD_MSC_DeviceDesc);
+  return USBD_MSC_DeviceDesc;
+}
+
+/**
+  * @brief  Return the LangID string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_MSC_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  *length = sizeof(USBD_LangIDDesc);
+  return USBD_LangIDDesc;
+}
+
+/**
+  * @brief  Return the product string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_MSC_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  if(speed == 0)
+  {
+    USBD_GetString((uint8_t *)USBD_PRODUCT_STRING, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString((uint8_t *)USBD_PRODUCT_STRING, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Return the manufacturer string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_MSC_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Return the serial number string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_MSC_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  *length = USB_SIZ_STRING_SERIAL;
+
+  /* Update the serial number string descriptor with the data from the unique
+   * ID */
+  Get_SerialNum();
+  
+  /* USER CODE BEGIN USBD_MSC_SerialStrDescriptor */
+  
+  /* USER CODE END USBD_MSC_SerialStrDescriptor */
+
+  return (uint8_t *) USBD_StringSerial;
+}
+
+/**
+  * @brief  Return the configuration string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_MSC_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  if(speed == USBD_SPEED_HIGH)
+  {
+    USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Return the interface string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_MSC_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  if(speed == 0)
+  {
+    USBD_GetString((uint8_t *)USBD_INTERFACE_STRING, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString((uint8_t *)USBD_INTERFACE_STRING, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Create the serial number string descriptor 
+  * @param  None 
+  * @retval None
+  */
+static void Get_SerialNum(void)
+{
+  uint32_t deviceserial0, deviceserial1, deviceserial2;
+
+  deviceserial0 = *(uint32_t *) DEVICE_ID1;
+  deviceserial1 = *(uint32_t *) DEVICE_ID2;
+  deviceserial2 = *(uint32_t *) DEVICE_ID3;
+
+  deviceserial0 += deviceserial2;
+
+  if (deviceserial0 != 0)
+  {
+    IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
+    IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
+  }
+}
+
+/**
+  * @brief  Convert Hex 32Bits value into char 
+  * @param  value: value to convert
+  * @param  pbuf: pointer to the buffer 
+  * @param  len: buffer length
+  * @retval None
+  */
+static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
+{
+  uint8_t idx = 0;
+
+  for (idx = 0; idx < len; idx++)
+  {
+    if (((value >> 28)) < 0xA)
+    {
+      pbuf[2 * idx] = (value >> 28) + '0';
+    }
+    else
+    {
+      pbuf[2 * idx] = (value >> 28) + 'A' - 10;
+    }
+
+    value = value << 4;
+
+    pbuf[2 * idx + 1] = 0;
+  }
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usbd_desc.h b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usbd_desc.h
new file mode 100644
index 000000000..d9a14ad4b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usbd_desc.h
@@ -0,0 +1,145 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           USB_Device/MSC_Standalone/USB_Device/App/usbd_desc.h
+  * @author         MCD Application Team
+  * @brief          Header for usbd_desc.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_DESC__C__
+#define __USBD_DESC__C__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_def.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup USBD_DESC USBD_DESC
+  * @brief Usb device descriptors module.
+  * @{
+  */
+  
+/** @defgroup USBD_DESC_Exported_Constants USBD_DESC_Exported_Constants
+  * @brief Constants.
+  * @{
+  */
+#define         DEVICE_ID1          (UID_BASE)
+#define         DEVICE_ID2          (UID_BASE + 0x4)
+#define         DEVICE_ID3          (UID_BASE + 0x8)
+
+#define         USB_SIZ_STRING_SERIAL       0x1A
+
+/* USER CODE BEGIN EXPORTED_CONSTANTS */
+
+/* USER CODE END EXPORTED_CONSTANTS */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_Defines USBD_DESC_Exported_Defines
+  * @brief Defines.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_DEFINES */
+
+/* USER CODE END EXPORTED_DEFINES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_TypesDefinitions USBD_DESC_Exported_TypesDefinitions
+  * @brief Types.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_TYPES */
+
+/* USER CODE END EXPORTED_TYPES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_Macros USBD_DESC_Exported_Macros
+  * @brief Aliases.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_MACRO */
+
+/* USER CODE END EXPORTED_MACRO */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_Variables USBD_DESC_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+extern USBD_DescriptorsTypeDef     MSC_Desc;
+
+/* USER CODE BEGIN EXPORTED_VARIABLES */
+
+/* USER CODE END EXPORTED_VARIABLES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_FunctionsPrototype USBD_DESC_Exported_FunctionsPrototype
+  * @brief Public functions declaration.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_FUNCTIONS */
+
+/* USER CODE END EXPORTED_FUNCTIONS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_DESC__C__ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usbd_storage_if.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usbd_storage_if.c
new file mode 100644
index 000000000..bf12e10d1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usbd_storage_if.c
@@ -0,0 +1,321 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           USB_Device/MSC_Standalone/USB_Device/App/usbd_storage_if.c
+  * @author         MCD Application Team
+  * @brief          Memory management layer
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_storage_if.h"
+
+/* USER CODE BEGIN INCLUDE */
+#include "main.h"
+/* USER CODE END INCLUDE */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  * @brief Usb device.
+  * @{
+  */
+
+/** @defgroup USBD_STORAGE
+  * @brief Usb mass storage device module
+  * @{
+  */
+
+/** @defgroup USBD_STORAGE_Private_TypesDefinitions
+  * @brief Private types.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_TYPES */
+
+/* USER CODE END PRIVATE_TYPES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_STORAGE_Private_Defines
+  * @brief Private defines.
+  * @{
+  */
+
+#define STORAGE_LUN_NBR                  1
+#define STORAGE_BLK_NBR                  0x10000
+#define STORAGE_BLK_SIZ                  0x200
+
+/* USER CODE BEGIN PRIVATE_DEFINES */
+
+/* USER CODE END PRIVATE_DEFINES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_STORAGE_Private_Macros
+  * @brief Private macros.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_MACRO */
+
+/* USER CODE END PRIVATE_MACRO */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_STORAGE_Private_Variables
+  * @brief Private variables.
+  * @{
+  */
+
+/* USER CODE BEGIN INQUIRY_DATA_FS */
+/** USB Mass storage Standard Inquiry Data. */
+const int8_t STORAGE_Inquirydata_FS[] = {/* 36 */
+
+  /* LUN 0 */
+  0x00,
+  0x80,
+  0x02,
+  0x02,
+  (STANDARD_INQUIRY_DATA_LEN - 5),
+  0x00,
+  0x00,
+  0x00,
+  'S', 'T', 'M', ' ', ' ', ' ', ' ', ' ', /* Manufacturer : 8 bytes */
+  'P', 'r', 'o', 'd', 'u', 'c', 't', ' ', /* Product      : 16 Bytes */
+  ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ',
+  '0', '.', '0' ,'1'                      /* Version      : 4 Bytes */
+};
+/* USER CODE END INQUIRY_DATA_FS */
+
+/* USER CODE BEGIN PRIVATE_VARIABLES */
+
+/* USER CODE END PRIVATE_VARIABLES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_STORAGE_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+extern USBD_HandleTypeDef hUsbDeviceFS;
+
+/* USER CODE BEGIN EXPORTED_VARIABLES */
+
+/* USER CODE END EXPORTED_VARIABLES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_STORAGE_Private_FunctionPrototypes
+  * @brief Private functions declaration.
+  * @{
+  */
+
+static int8_t STORAGE_Init_FS(uint8_t lun);
+static int8_t STORAGE_GetCapacity_FS(uint8_t lun, uint32_t *block_num, uint16_t *block_size);
+static int8_t STORAGE_IsReady_FS(uint8_t lun);
+static int8_t STORAGE_IsWriteProtected_FS(uint8_t lun);
+static int8_t STORAGE_Read_FS(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
+static int8_t STORAGE_Write_FS(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
+static int8_t STORAGE_GetMaxLun_FS(void);
+
+/* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */
+
+/* USER CODE END PRIVATE_FUNCTIONS_DECLARATION */
+
+/**
+  * @}
+  */
+
+USBD_StorageTypeDef USBD_Storage_Interface_fops_FS =
+{
+  STORAGE_Init_FS,
+  STORAGE_GetCapacity_FS,
+  STORAGE_IsReady_FS,
+  STORAGE_IsWriteProtected_FS,
+  STORAGE_Read_FS,
+  STORAGE_Write_FS,
+  STORAGE_GetMaxLun_FS,
+  (int8_t *)STORAGE_Inquirydata_FS
+};
+
+/* Private functions ---------------------------------------------------------*/
+/**
+  * @brief  Initializes over USB FS IP
+  * @param  lun:
+  * @retval USBD_OK if all operations are OK else USBD_FAIL
+  */
+int8_t STORAGE_Init_FS(uint8_t lun)
+{
+  /* USER CODE BEGIN 2 */
+  BSP_SD_Init();
+  return (USBD_OK);
+  /* USER CODE END 2 */
+}
+
+/**
+  * @brief  .
+  * @param  lun: .
+  * @param  block_num: .
+  * @param  block_size: .
+  * @retval USBD_OK if all operations are OK else USBD_FAIL
+  */
+int8_t STORAGE_GetCapacity_FS(uint8_t lun, uint32_t *block_num, uint16_t *block_size)
+{
+  /* USER CODE BEGIN 3 */
+  SD_CardInfo info;
+  int8_t ret = 0;
+
+  if (BSP_SD_GetCardInfo(&info) != BSP_SD_OK)
+  {
+    ret = -1;
+  }
+
+  *block_num = info.LogBlockNbr;
+  *block_size = info.LogBlockSize;
+
+
+  return ret;
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief  .
+  * @param  lun: .
+  * @retval USBD_OK if all operations are OK else USBD_FAIL
+  */
+int8_t STORAGE_IsReady_FS(uint8_t lun)
+{
+  /* USER CODE BEGIN 4 */
+  static int8_t prev_status = 0;
+  int8_t ret = -1;
+
+  if(prev_status < 0)
+  {
+    BSP_SD_Init();
+    prev_status = 0;
+  }
+if(BSP_SD_GetCardState() == BSP_SD_OK)
+  {
+    ret = 0;
+  }
+
+  return ret;
+  /* USER CODE END 4 */
+}
+
+/**
+  * @brief  .
+  * @param  lun: .
+  * @retval USBD_OK if all operations are OK else USBD_FAIL
+  */
+int8_t STORAGE_IsWriteProtected_FS(uint8_t lun)
+{
+  /* USER CODE BEGIN 5 */
+  return (USBD_OK);
+  /* USER CODE END 5 */
+}
+
+/**
+  * @brief  .
+  * @param  lun: .
+  * @retval USBD_OK if all operations are OK else USBD_FAIL
+  */
+int8_t STORAGE_Read_FS(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len)
+{
+  /* USER CODE BEGIN 6 */
+  int8_t ret = -1;
+  uint32_t timeout = 100000;
+  BSP_SD_ReadBlocks((uint32_t *)buf, blk_addr, blk_len, SD_DATATIMEOUT);
+  while(BSP_SD_GetCardState() != BSP_SD_OK)
+  {
+    if (timeout-- == 0)
+    {
+      return ret;
+    }
+  }
+  ret = 0;
+
+  return ret;
+  /* USER CODE END 6 */
+}
+
+/**
+  * @brief  .
+  * @param  lun: .
+  * @retval USBD_OK if all operations are OK else USBD_FAIL
+  */
+int8_t STORAGE_Write_FS(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len)
+{
+  /* USER CODE BEGIN 7 */
+  int8_t ret = -1;
+  uint32_t timeout = 100000;
+   BSP_SD_WriteBlocks((uint32_t *)buf, blk_addr, blk_len, SD_DATATIMEOUT);
+   while(BSP_SD_GetCardState() != BSP_SD_OK)
+  {
+    if (timeout-- == 0)
+    {
+      return ret;
+    }
+  }
+  ret = 0;
+
+  return ret;
+  /* USER CODE END 7 */
+}
+
+/**
+  * @brief  .
+  * @param  None
+  * @retval .
+  */
+int8_t STORAGE_GetMaxLun_FS(void)
+{
+  /* USER CODE BEGIN 8 */
+  return (STORAGE_LUN_NBR - 1);
+  /* USER CODE END 8 */
+}
+
+/* USER CODE BEGIN PRIVATE_FUNCTIONS_IMPLEMENTATION */
+
+/* USER CODE END PRIVATE_FUNCTIONS_IMPLEMENTATION */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usbd_storage_if.h b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usbd_storage_if.h
new file mode 100644
index 000000000..44ec58ebf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/App/usbd_storage_if.h
@@ -0,0 +1,129 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           USB_Device/MSC_Standalone/USB_Device/App/usbd_storage_if.h
+  * @author         MCD Application Team
+  * @brief          Header for usbd_storage_if.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_STORAGE_IF_H__
+#define __USBD_STORAGE_IF_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_msc.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  * @brief For Usb device.
+  * @{
+  */
+
+/** @defgroup USBD_STORAGE USBD_STORAGE
+  * @brief Header file for the usb_storage_if.c file
+  * @{
+  */
+
+/** @defgroup USBD_STORAGE_Exported_Defines USBD_STORAGE_Exported_Defines
+  * @brief Defines.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_DEFINES */
+
+/* USER CODE END EXPORTED_DEFINES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_STORAGE_Exported_Types USBD_STORAGE_Exported_Types
+  * @brief Types.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_TYPES */
+
+/* USER CODE END EXPORTED_TYPES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_STORAGE_Exported_Macros USBD_STORAGE_Exported_Macros
+  * @brief Aliases.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_MACRO */
+
+/* USER CODE END EXPORTED_MACRO */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_STORAGE_Exported_Variables USBD_STORAGE_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+/** STORAGE Interface callback. */
+extern USBD_StorageTypeDef USBD_Storage_Interface_fops_FS;
+
+/* USER CODE BEGIN EXPORTED_VARIABLES */
+
+/* USER CODE END EXPORTED_VARIABLES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_STORAGE_Exported_FunctionsPrototype USBD_STORAGE_Exported_FunctionsPrototype
+  * @brief Public functions declaration.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_FUNCTIONS */
+
+/* USER CODE END EXPORTED_FUNCTIONS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_STORAGE_IF_H__ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/Target/usbd_conf.c b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/Target/usbd_conf.c
new file mode 100644
index 000000000..1cd926c8e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/Target/usbd_conf.c
@@ -0,0 +1,770 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           USB_Device/MSC_Standalone/USB_Device/Target/usbd_conf.c
+  * @author         MCD Application Team
+  * @brief          This file implements the board support package for the USB device library
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx.h"
+#include "stm32wbxx_hal.h"
+#include "usbd_def.h"
+#include "usbd_core.h"
+
+#include "usbd_msc.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+PCD_HandleTypeDef hpcd_USB_FS;
+void Error_Handler(void);
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* Exported function prototypes ----------------------------------------------*/
+
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+
+/* USER CODE END PFP */
+
+/* Private functions ---------------------------------------------------------*/
+static USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status);
+/* USER CODE BEGIN 1 */
+static void SystemClockConfig_Resume(void);
+extern void USBD_Clock_Config(void);
+/* USER CODE END 1 */
+extern void SystemClock_Config(void);
+
+/*******************************************************************************
+                       LL Driver Callbacks (PCD -> USB Device Library)
+*******************************************************************************/
+/* MSP Init */
+
+#if (USE_HAL_PCD_REGISTER_CALLBACK == 1U)
+static void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
+#else
+void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACK */
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(pcdHandle->Instance==USB)
+  {
+  /* USER CODE BEGIN USB_MspInit 0 */
+
+  /* USER CODE END USB_MspInit 0 */
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**USB GPIO Configuration    
+    PA11     ------> USB_DM
+    PA12     ------> USB_DP 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF10_USB;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* Peripheral clock enable */
+    __HAL_RCC_USB_CLK_ENABLE();
+
+    /* Peripheral interrupt init */
+    HAL_NVIC_SetPriority(USB_LP_IRQn, 6, 0);
+    HAL_NVIC_EnableIRQ(USB_LP_IRQn);
+  /* USER CODE BEGIN USB_MspInit 1 */
+
+  /* USER CODE END USB_MspInit 1 */
+  }
+}
+
+#if (USE_HAL_PCD_REGISTER_CALLBACK == 1U)
+static void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle)
+#else
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACK */
+{
+  if(pcdHandle->Instance==USB)
+  {
+  /* USER CODE BEGIN USB_MspDeInit 0 */
+
+  /* USER CODE END USB_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USB_CLK_DISABLE();
+  
+    /**USB GPIO Configuration    
+    PA11     ------> USB_DM
+    PA12     ------> USB_DP 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12);
+
+    /* Peripheral interrupt Deinit*/
+    HAL_NVIC_DisableIRQ(USB_LP_IRQn);
+
+  /* USER CODE BEGIN USB_MspDeInit 1 */
+    __HAL_RCC_GPIOA_CLK_DISABLE();
+  /* USER CODE END USB_MspDeInit 1 */
+  }
+}
+
+/**
+  * @brief  Setup stage callback
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_SetupStageCallback_PreTreatment */
+  
+  /* USER CODE END  HAL_PCD_SetupStageCallback_PreTreatment */
+  USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);  
+  /* USER CODE BEGIN HAL_PCD_SetupStageCallback_PostTreatment */
+  
+  /* USER CODE END  HAL_PCD_SetupStageCallback_PostTreatment */
+}
+
+/**
+  * @brief  Data Out stage callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PreTreatment */
+  
+  /* USER CODE END HAL_PCD_DataOutStageCallback_PreTreatment */
+  USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);  
+  /* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PostTreatment */
+  
+  /* USER CODE END HAL_PCD_DataOutStageCallback_PostTreatment */
+}
+
+/**
+  * @brief  Data In stage callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_DataInStageCallback_PreTreatment */
+  
+  /* USER CODE END HAL_PCD_DataInStageCallback_PreTreatment */  
+  USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);  
+  /* USER CODE BEGIN HAL_PCD_DataInStageCallback_PostTreatment  */
+  
+  /* USER CODE END HAL_PCD_DataInStageCallback_PostTreatment */
+}
+
+/**
+  * @brief  SOF callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_SOFCallback_PreTreatment */
+  
+  /* USER CODE END HAL_PCD_SOFCallback_PreTreatment */  
+  USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);  
+  /* USER CODE BEGIN HAL_PCD_SOFCallback_PostTreatment */
+  
+  /* USER CODE END HAL_PCD_SOFCallback_PostTreatment */
+}
+
+/**
+  * @brief  Reset callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{ 
+  /* USER CODE BEGIN HAL_PCD_ResetCallback_PreTreatment */
+  
+  /* USER CODE END HAL_PCD_ResetCallback_PreTreatment */
+  USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
+
+  if ( hpcd->Init.speed != PCD_SPEED_FULL)
+  {
+    Error_Handler();
+  }
+    /* Set Speed. */
+  USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
+
+  /* Reset Device. */
+  USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
+  /* USER CODE BEGIN HAL_PCD_ResetCallback_PostTreatment */
+  
+  /* USER CODE END HAL_PCD_ResetCallback_PostTreatment */
+}
+
+/**
+  * @brief  Suspend callback.
+  * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it)
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_SuspendCallback_PreTreatment */
+  
+  /* USER CODE END HAL_PCD_SuspendCallback_PreTreatment */
+  /* Inform USB library that core enters in suspend Mode. */
+  USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
+  /* Enter in STOP mode. */
+  /* USER CODE BEGIN 2 */
+  if (hpcd->Init.low_power_enable)
+  {
+    /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
+    SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
+  }
+  /* USER CODE END 2 */
+  /* USER CODE BEGIN HAL_PCD_SuspendCallback_PostTreatment */
+  
+  /* USER CODE END HAL_PCD_SuspendCallback_PostTreatment */
+}
+
+/**
+  * @brief  Resume callback.
+  * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it)
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_ResumeCallback_PreTreatment */
+  
+  /* USER CODE END HAL_PCD_ResumeCallback_PreTreatment */
+
+  /* USER CODE BEGIN 3 */
+  if (hpcd->Init.low_power_enable)
+  {
+    /* Reset SLEEPDEEP bit of Cortex System Control Register. */
+    SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
+    SystemClockConfig_Resume();
+  }
+  /* USER CODE END 3 */
+ 
+  USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
+  /* USER CODE BEGIN HAL_PCD_ResumeCallback_PostTreatment */
+  
+  /* USER CODE END HAL_PCD_ResumeCallback_PostTreatment */
+}
+
+/**
+  * @brief  ISOOUTIncomplete callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_ISOOUTIncompleteCallback_PreTreatment */
+  
+  /* USER CODE END HAL_PCD_ISOOUTIncompleteCallback_PreTreatment */
+  USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
+  /* USER CODE BEGIN HAL_PCD_ISOOUTIncompleteCallback_PostTreatment */
+  
+  /* USER CODE END HAL_PCD_ISOOUTIncompleteCallback_PostTreatment */
+}
+
+/**
+  * @brief  ISOINIncomplete callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_ISOINIncompleteCallback_PreTreatment */
+  
+  /* USER CODE END HAL_PCD_ISOINIncompleteCallback_PreTreatment */
+  USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
+  /* USER CODE BEGIN HAL_PCD_ISOINIncompleteCallback_PostTreatment */
+  
+  /* USER CODE END HAL_PCD_ISOINIncompleteCallback_PostTreatment */
+}
+
+/**
+  * @brief  Connect callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_ConnectCallback_PreTreatment */
+  
+  /* USER CODE END HAL_PCD_ConnectCallback_PreTreatment */
+  USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData);
+  /* USER CODE BEGIN HAL_PCD_ConnectCallback_PostTreatment */
+  
+  /* USER CODE END HAL_PCD_ConnectCallback_PostTreatment */
+}
+
+/**
+  * @brief  Disconnect callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_DisconnectCallback_PreTreatment */
+  
+  /* USER CODE END HAL_PCD_DisconnectCallback_PreTreatment */
+  USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData);
+  /* USER CODE BEGIN HAL_PCD_DisconnectCallback_PostTreatment */
+  
+  /* USER CODE END HAL_PCD_DisconnectCallback_PostTreatment */
+}
+
+  /* USER CODE BEGIN LowLevelInterface */
+
+  /* USER CODE END LowLevelInterface */
+
+/*******************************************************************************
+                       LL Driver Interface (USB Device Library --> PCD)
+*******************************************************************************/
+
+/**
+  * @brief  Initializes the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
+{
+  /* Init USB Ip. */
+  hpcd_USB_FS.pData = pdev;
+  /* Link the driver to the stack. */
+  pdev->pData = &hpcd_USB_FS;
+  /* Enable USB power on Pwrctrl CR2 register. */
+  HAL_PWREx_EnableVddUSB();
+
+  hpcd_USB_FS.Instance = USB;
+  hpcd_USB_FS.Init.dev_endpoints = 8;
+  hpcd_USB_FS.Init.speed = PCD_SPEED_FULL;
+  hpcd_USB_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
+  hpcd_USB_FS.Init.Sof_enable = DISABLE;
+  hpcd_USB_FS.Init.low_power_enable = DISABLE;
+  hpcd_USB_FS.Init.lpm_enable = DISABLE;
+  hpcd_USB_FS.Init.battery_charging_enable = DISABLE;
+
+  #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  /* register Msp Callbacks (before the Init) */
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_MSPINIT_CB_ID, PCD_MspInit);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_MSPDEINIT_CB_ID, PCD_MspDeInit);
+  #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+  if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK)
+  {
+    Error_Handler( );
+  }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  /* Register USB PCD CallBacks */
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SOF_CB_ID, PCD_SOFCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SETUPSTAGE_CB_ID, PCD_SetupStageCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_RESET_CB_ID, PCD_ResetCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SUSPEND_CB_ID, PCD_SuspendCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_RESUME_CB_ID, PCD_ResumeCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_CONNECT_CB_ID, PCD_ConnectCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_DISCONNECT_CB_ID, PCD_DisconnectCallback);
+  /* USER CODE BEGIN RegisterCallBackFirstPart */
+
+  /* USER CODE END RegisterCallBackFirstPart */
+  HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_FS, PCD_DataOutStageCallback);
+  HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_FS, PCD_DataInStageCallback);
+  HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_FS, PCD_ISOOUTIncompleteCallback);
+  HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_FS, PCD_ISOINIncompleteCallback);
+  /* USER CODE BEGIN RegisterCallBackSecondPart */
+
+  /* USER CODE END RegisterCallBackSecondPart */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  /* USER CODE BEGIN EndPoint_Configuration */
+  HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData, 0x00, PCD_SNG_BUF, 0x10);
+  HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData, 0x80, PCD_SNG_BUF, 0x50);
+  /* USER CODE END EndPoint_Configuration */
+  /* USER CODE BEGIN EndPoint_Configuration_MSC */
+  HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData, MSC_EPIN_ADDR, PCD_SNG_BUF, 0x90);
+  HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData, MSC_EPOUT_ADDR, PCD_SNG_BUF, 0xD0);
+  /* USER CODE END EndPoint_Configuration_MSC */
+  return USBD_OK;
+}
+
+/**
+  * @brief  De-Initializes the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_DeInit(pdev->pData);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+ 
+  return usb_status; 
+}
+
+/**
+  * @brief  Starts the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+ 
+  hal_status = HAL_PCD_Start(pdev->pData);
+     
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status;
+}
+
+/**
+  * @brief  Stops the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_Stop(pdev->pData);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status;
+}
+
+/**
+  * @brief  Opens an endpoint of the low level driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @param  ep_type: Endpoint type
+  * @param  ep_mps: Endpoint max packet size
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+ 
+  return usb_status;
+}
+
+/**
+  * @brief  Closes an endpoint of the low level driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
+      
+  usb_status =  USBD_Get_USB_Status(hal_status);
+
+  return usb_status;  
+}
+
+/**
+  * @brief  Flushes an endpoint of the Low Level Driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr);
+      
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status;  
+}
+
+/**
+  * @brief  Sets a Stall condition on an endpoint of the Low Level Driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+ 
+  return usb_status;  
+}
+
+/**
+  * @brief  Clears a Stall condition on an endpoint of the Low Level Driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);  
+     
+  usb_status =  USBD_Get_USB_Status(hal_status);
+
+  return usb_status; 
+}
+
+/**
+  * @brief  Returns Stall condition.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval Stall (1: Yes, 0: No)
+  */
+uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
+  
+  if((ep_addr & 0x80) == 0x80)
+  {
+    return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 
+  }
+  else
+  {
+    return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 
+  }
+}
+
+/**
+  * @brief  Assigns a USB address to the device.
+  * @param  pdev: Device handle
+  * @param  dev_addr: Device address
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
+     
+  usb_status =  USBD_Get_USB_Status(hal_status);
+ 
+  return usb_status;  
+}
+
+/**
+  * @brief  Transmits data over an endpoint.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @param  pbuf: Pointer to data to be sent
+  * @param  size: Data size    
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
+     
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status;    
+}
+
+/**
+  * @brief  Prepares an endpoint for reception.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @param  pbuf: Pointer to data to be received
+  * @param  size: Data size
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
+     
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  	
+  return usb_status; 
+}
+
+/**
+  * @brief  Returns the last transfered packet size.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval Recived Data Size
+  */
+uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
+}
+
+/**
+  * @brief  Delays routine for the USB Device Library.
+  * @param  Delay: Delay in ms
+  * @retval None
+  */
+void USBD_LL_Delay(uint32_t Delay)
+{
+  HAL_Delay(Delay);
+}
+
+/**
+  * @brief  Static single allocation.
+  * @param  size: Size of allocated memory
+  * @retval None
+  */
+void *USBD_static_malloc(uint32_t size)
+{
+  static uint32_t mem[(sizeof(USBD_MSC_BOT_HandleTypeDef)/4)+1];/* On 32-bit boundary */
+  return mem;
+}
+
+/**
+  * @brief  Dummy memory free
+  * @param  p: Pointer to allocated  memory address
+  * @retval None
+  */
+void USBD_static_free(void *p)
+{
+
+}
+
+/* USER CODE BEGIN 5 */
+/**
+  * @brief  Configures system clock after wake-up from USB resume callBack:
+  *         enable HSI, PLL and select PLL as system clock source.
+  * @retval None
+  */
+static void SystemClockConfig_Resume(void)
+{
+  SystemClock_Config();
+  USBD_Clock_Config();
+}
+/* USER CODE END 5 */
+
+/**
+  * @brief  Retuns the USB status depending on the HAL status:
+  * @param  hal_status: HAL status
+  * @retval USB status
+  */
+USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
+{
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  switch (hal_status)
+  {
+    case HAL_OK :
+      usb_status = USBD_OK;
+    break;
+    case HAL_ERROR :
+      usb_status = USBD_FAIL;
+    break;
+    case HAL_BUSY :
+      usb_status = USBD_BUSY;
+    break;
+    case HAL_TIMEOUT :
+      usb_status = USBD_FAIL;
+    break;
+    default :
+      usb_status = USBD_FAIL;
+    break;
+  }
+  return usb_status;
+}
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/Target/usbd_conf.h b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/Target/usbd_conf.h
new file mode 100644
index 000000000..d50d8d506
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/USB_Device/Target/usbd_conf.h
@@ -0,0 +1,179 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           USB_Device/MSC_Standalone/USB_Device/Target/usbd_conf.h
+  * @author         MCD Application Team
+  * @brief          Header for usbd_conf.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_CONF__H__
+#define __USBD_CONF__H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include 
+#include 
+#include 
+#include "stm32wbxx.h"
+#include "stm32wbxx_hal.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/** @addtogroup USBD_OTG_DRIVER
+  * @brief Driver for Usb device.
+  * @{
+  */
+
+/** @defgroup USBD_CONF USBD_CONF
+  * @brief Configuration file for Usb otg low level driver.
+  * @{
+  */
+
+/** @defgroup USBD_CONF_Exported_Variables USBD_CONF_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+/* USER CODE END PV */
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_Defines USBD_CONF_Exported_Defines
+  * @brief Defines for configuration of the Usb device.
+  * @{
+  */
+
+/*---------- -----------*/
+#define USBD_MAX_NUM_INTERFACES     1U
+/*---------- -----------*/
+#define USBD_MAX_NUM_CONFIGURATION     1U
+/*---------- -----------*/
+#define USBD_MAX_STR_DESC_SIZ     64U
+/*---------- -----------*/
+#define USBD_DEBUG_LEVEL     0U
+/*---------- -----------*/
+#define USBD_LPM_ENABLED     0U
+/*---------- -----------*/
+#define USBD_SELF_POWERED     1U
+/*---------- -----------*/
+#define MSC_MEDIA_PACKET     512U
+
+/****************************************/
+/* #define for FS and HS identification */
+#define DEVICE_FS 		0
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_Macros USBD_CONF_Exported_Macros
+  * @brief Aliases.
+  * @{
+  */
+
+/* Memory management macros */
+
+/** Alias for memory allocation. */
+#define USBD_malloc         (uint32_t *)USBD_static_malloc
+
+/** Alias for memory release. */
+#define USBD_free           USBD_static_free
+
+/** Alias for memory set. */
+#define USBD_memset         /* Not used */
+
+/** Alias for memory copy. */
+#define USBD_memcpy         /* Not used */
+
+/** Alias for delay. */
+#define USBD_Delay          HAL_Delay
+
+/* DEBUG macros */
+
+#if (USBD_DEBUG_LEVEL > 0)
+#define USBD_UsrLog(...)    printf(__VA_ARGS__);\
+                            printf("\n");
+#else
+#define USBD_UsrLog(...)
+#endif
+
+#if (USBD_DEBUG_LEVEL > 1)
+
+#define USBD_ErrLog(...)    printf("ERROR: ") ;\
+                            printf(__VA_ARGS__);\
+                            printf("\n");
+#else
+#define USBD_ErrLog(...)
+#endif
+
+#if (USBD_DEBUG_LEVEL > 2)
+#define USBD_DbgLog(...)    printf("DEBUG : ") ;\
+                            printf(__VA_ARGS__);\
+                            printf("\n");
+#else
+#define USBD_DbgLog(...)
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_Types USBD_CONF_Exported_Types
+  * @brief Types.
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_FunctionsPrototype USBD_CONF_Exported_FunctionsPrototype
+  * @brief Declaration of public functions for Usb device.
+  * @{
+  */
+
+/* Exported functions -------------------------------------------------------*/
+void *USBD_static_malloc(uint32_t size);
+void USBD_static_free(void *p);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_CONF__H__ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/readme.txt b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/readme.txt
new file mode 100644
index 000000000..a8d7159ea
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Applications/USB_Device/MSC_Standalone/readme.txt
@@ -0,0 +1,99 @@
+/**
+  @page MSC_Standalone USB Device Mass Storage (MSC) application
+
+  @verbatim
+  ******************************************************************************
+  * @file    USB_Device/MSC_Standalone/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the USB MSC application.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                               www.st.com/SLA0044
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Application Description
+
+This application shows how to use the USB device application based on the Mass Storage Class (MSC) on the STM32WBxx devices.
+
+This is a typical application on how to use the stm32wbxx USB Device peripheral to communicate with a PC
+Host using the Bulk Only Transfer (BOT) and Small Computer System Interface (SCSI) transparent commands,
+while the microSD card is used as storage media. The STM32 MCU is enumerated as a MSC device using the
+native PC Host MSC driver to which the NUCLEO-WB35CE board is connected.
+
+At the beginning of the main program the HAL_Init() function is called to reset all the peripherals,
+initialize the Flash interface and the systick. The user is provided with the SystemClock_Config()
+function to configure the system clock (SYSCLK). The Full Speed (FS) USB module uses
+internally a 48-MHz clock, which is generated from an internal PLL.
+
+
+
+When the application is started, the user has just to plug the USB cable into a PC host and the device
+is automatically detected. A new removable drive appears in the system window and write/read/format
+operations can be performed as with any other removable drive.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+For more details about the STM32Cube USB Device library, please refer to UM1734
+"STM32Cube USB Device library".
+
+@par Keywords
+
+Connectivity, USB Device, MSC, Full Speed, flash, microSD card
+
+@par Directory contents
+
+  - USB_Device/MSC_Standalone/Core/Src/main.c                    Main program
+  - USB_Device/MSC_Standalone/Core/Src/system_stm32wbxx.c        stm32wbxx system clock configuration file
+  - USB_Device/MSC_Standalone/Core/Src/stm32wbxx_it.c            Interrupt handlers
+  - USB_Device/MSC_Standalone/Core/Src/stm32wbxx_hal_msp.c       HAL MSP Module
+  - USB_Device/MSC_Standalone/USB_Device/App/usb_device.c        USB Device application code
+  - USB_Device/MSC_Standalone/USB_Device/App/usb_desc.c          USB device descriptor
+  - USB_Device/MSC_Standalone/USB_Device/App/usbd_storage_if.c   Internal flash memory management
+  - USB_Device/MSC_Standalone/USB_Device/Target/usbd_conf.c      General low level driver configuration
+  - USB_Device/MSC_Standalone/Core/Inc/main.h                    Main program header file
+  - USB_Device/MSC_Standalone/Core/Inc/stm32wbxx_it.h            Interrupt handlers header file
+  - USB_Device/MSC_Standalone/Core/Inc/stm32wbxx_hal_conf.h      HAL configuration file
+  - USB_Device/MSC_Standalone/USB_Device/App/usb_device.h        USB Device application header file
+  - USB_Device/MSC_Standalone/USB_Device/App/usbd_desc.h         USB device descriptor header file
+  - USB_Device/MSC_Standalone/USB_Device/App/usbd_storage_if.h   Internal flash memory management header file
+  - USB_Device/MSC_Standalone/USB_Device/Target/usbd_conf.h      USB device driver Configuration file
+
+
+@par Hardware and Software environment
+
+  - This application runs on STM32WBxx devices.
+
+  - This application has been tested with STMicroelectronics NUCLEO-WB35CE boards
+    and can be easily tailored to any other supported device and development board.
+  - NUCLEO-WB35CE Set-up
+    - Insert a microSD card into the NUCLEO-WB35CE Adafruit Shield
+    - Connect the NUCLEO-WB35CE board to the PC through micro A-Male to standard A Male cable.
+   cable to the connector: CN1: to use USB Full Speed (FS)
+
+
+
+  - Adafruit 1.8" TFT shield must be connected on CN5,CN6, CN8 and CN9 Arduino connectors,
+    for more details please refer to board User manual.
+@par How to use it ?
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the application
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/.extSettings b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/.extSettings
new file mode 100644
index 000000000..4fd031e3e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/.extSettings
@@ -0,0 +1,12 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE;..\..\..\..\..\Drivers\BSP\Adafruit_Shield;..\..\..\..\..\Drivers\BSP\Components;..\..\..\..\..\Drivers\BSP\Components\Common
+[Others]
+Define=USE_STM32WBXX_NUCLEO
+HALModule=SPI;ADC;SPI
+[Groups]
+Application/User/Core=../Core/Src/main.c;../Core/Src/stm32wbxx_it.c;../Core/Src/stm32wbxx_hal_msp.c;
+Doc=../readme.txt;
+Drivers/BSP/Adafruit_Shield=../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_sd.c;../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_lcd.c;
+Drivers/BSP/Components=../../../../../Drivers/BSP/Components/st7735/st7735.c;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../Drivers//BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
+Drivers/STM32WBxx_HAL_Driver=../../../../../Drivers//STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c;../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c;
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Adafruit_LCD_1_8_SD_Joystick.ioc b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Adafruit_LCD_1_8_SD_Joystick.ioc
new file mode 100644
index 000000000..0c28760c3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Adafruit_LCD_1_8_SD_Joystick.ioc
@@ -0,0 +1,139 @@
+#MicroXplorer Configuration settings - do not modify
+FATFS.BOARD_NAME=none
+FATFS.DISKIO_CODE=1
+FATFS.IPParameters=DISKIO_CODE,_USE_STRFUNC,_USE_FIND,_USE_LFN,_VOLUMES,_FS_NORTC,_FS_LOCK,_FS_READONLY,_FS_MINIMIZE,_USE_MKFS,_USE_FASTSEEK,_USE_EXPAND,_USE_CHMOD,_USE_LABEL,_USE_FORWARD,_CODE_PAGE,_MAX_LFN,_LFN_UNICODE,_STRF_ENCODE,_FS_RPATH,_MAX_SS,_MIN_SS,_MULTI_PARTITION,_USE_TRIM,_FS_NOFSINFO,_FS_TINY,_FS_EXFAT,_FS_REENTRANT,_FS_TIMEOUT,BOARD_NAME
+FATFS._CODE_PAGE=850
+FATFS._FS_EXFAT=0
+FATFS._FS_LOCK=12
+FATFS._FS_MINIMIZE=0
+FATFS._FS_NOFSINFO=0
+FATFS._FS_NORTC=0
+FATFS._FS_READONLY=0
+FATFS._FS_REENTRANT=0
+FATFS._FS_RPATH=0
+FATFS._FS_TIMEOUT=1000
+FATFS._FS_TINY=0
+FATFS._LFN_UNICODE=0
+FATFS._MAX_LFN=255
+FATFS._MAX_SS=512
+FATFS._MIN_SS=512
+FATFS._MULTI_PARTITION=0
+FATFS._STRF_ENCODE=3
+FATFS._USE_CHMOD=0
+FATFS._USE_EXPAND=0
+FATFS._USE_FASTSEEK=1
+FATFS._USE_FIND=1
+FATFS._USE_FORWARD=0
+FATFS._USE_LABEL=0
+FATFS._USE_LFN=3
+FATFS._USE_MKFS=1
+FATFS._USE_STRFUNC=0
+FATFS._USE_TRIM=0
+FATFS._VOLUMES=2
+File.Version=6
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=FATFS
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_FATFS_VS_Generic
+Mcu.Pin1=VP_SYS_VS_Systick
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x1000
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Core/Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=Adafruit_LCD_1_8_SD_Joystick.ioc
+ProjectManager.ProjectName=Adafruit_LCD_1_8_SD_Joystick
+ProjectManager.StackSize=0x1000
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_FATFS_Init-FATFS-false-HAL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_FATFS_VS_Generic.Mode=User_defined
+VP_FATFS_VS_Generic.Signal=FATFS_VS_Generic
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Inc/main.h b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Inc/main.h
new file mode 100644
index 000000000..0812d5130
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Inc/main.h
@@ -0,0 +1,111 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Inc/main.h 
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics International N.V. 
+  * All rights reserved.
    
+  *
+  * Redistribution and use in source and binary forms, with or without 
+  * modification, are permitted, provided that the following conditions are met:
+  *
+  * 1. Redistribution of source code must retain the above copyright notice, 
+  *    this list of conditions and the following disclaimer.
+  * 2. Redistributions in binary form must reproduce the above copyright notice,
+  *    this list of conditions and the following disclaimer in the documentation
+  *    and/or other materials provided with the distribution.
+  * 3. Neither the name of STMicroelectronics nor the names of other 
+  *    contributors to this software may be used to endorse or promote products 
+  *    derived from this software without specific written permission.
+  * 4. This software, including modifications and/or derivative works of this 
+  *    software, must execute solely and exclusively on microcontroller or
+  *    microprocessor devices manufactured by or for STMicroelectronics.
+  * 5. Redistribution and use of this software other than as permitted under 
+  *    this license is void and will automatically terminate your rights under 
+  *    this license. 
+  *
+  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" 
+  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT 
+  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 
+  * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
+  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT 
+  * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 
+  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 
+  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 
+  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+#include "stm32_adafruit_sd.h"
+#include "stm32_adafruit_lcd.h"
+#include 
+#include 
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+#define  MAX_BMP_FILES  25
+#define  MAX_BMP_FILE_NAME 11
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+void TFT_DisplayErrorMessage(uint8_t message);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+#define APP_OK                     0
+#define APP_ERROR                  -1
+#define SD_CARD_NOT_FORMATTED                    0
+#define SD_CARD_FILE_NOT_SUPPORTED               1
+#define SD_CARD_OPEN_FAIL                        2
+#define FATFS_NOT_MOUNTED                        3
+#define BSP_SD_INIT_FAILED                       4
+
+#define POSITION_X_BITMAP                        0
+#define POSITION_Y_BITMAP                        0
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..870650b60
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+#define HAL_ADC_MODULE_ENABLED
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+#define HAL_SPI_MODULE_ENABLED
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..20113411d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Inc/stm32wbxx_it.h
@@ -0,0 +1,88 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Inc/stm32wbxx_it.h 
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics International N.V. 
+  * All rights reserved.
    
+  *
+  * Redistribution and use in source and binary forms, with or without 
+  * modification, are permitted, provided that the following conditions are met:
+  *
+  * 1. Redistribution of source code must retain the above copyright notice, 
+  *    this list of conditions and the following disclaimer.
+  * 2. Redistributions in binary form must reproduce the above copyright notice,
+  *    this list of conditions and the following disclaimer in the documentation
+  *    and/or other materials provided with the distribution.
+  * 3. Neither the name of STMicroelectronics nor the names of other 
+  *    contributors to this software may be used to endorse or promote products 
+  *    derived from this software without specific written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void EXTI0_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Src/main.c b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Src/main.c
new file mode 100644
index 000000000..314e8f070
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Src/main.c
@@ -0,0 +1,676 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Src/main.c 
+  * @author  MCD Application Team
+  * @brief   This demo describes how display bmp images from SD card on LCD using
+             the Adafruit 1.8" TFT shield with Joystick and microSD mounted on top
+             of the STM32 Nucleo board.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics International N.V. 
+  * All rights reserved.
    
+  *
+  * Redistribution and use in source and binary forms, with or without 
+  * modification, are permitted, provided that the following conditions are met:
+  *
+  * 1. Redistribution of source code must retain the above copyright notice, 
+  *    this list of conditions and the following disclaimer.
+  * 2. Redistributions in binary form must reproduce the above copyright notice,
+  *    this list of conditions and the following disclaimer in the documentation
+  *    and/or other materials provided with the distribution.
+  * 3. Neither the name of STMicroelectronics nor the names of other 
+  *    contributors to this software may be used to endorse or promote products 
+  *    derived from this software without specific written permission.
+  * 4. This software, including modifications and/or derivative works of this 
+  *    software, must execute solely and exclusively on microcontroller or
+  *    microprocessor devices manufactured by or for STMicroelectronics.
+  * 5. Redistribution and use of this software other than as permitted under 
+  *    this license is void and will automatically terminate your rights under 
+  *    this license. 
+  *
+  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" 
+  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT 
+  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 
+  * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
+  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT 
+  * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 
+  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 
+  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 
+  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "app_fatfs.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+typedef enum 
+{
+  SHIELD_NOT_DETECTED = 0, 
+  SHIELD_DETECTED
+}ShieldStatus;
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+uint8_t BlinkSpeed = 0, str[20];
+__IO uint8_t JoystickValue = 0;
+char* pDirectoryFiles[MAX_BMP_FILES];
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+static void LED2_Blink(void);
+static ShieldStatus TFT_ShieldDetect(void);
+static void TFT_DisplayMenu(void);
+static void TFT_DisplayImages(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* Check the availability of adafruit 1.8" TFT shield on top of STM32NUCLEO
+     board. This is done by reading the state of IO PA.00 pin (mapped to JoyStick
+     available on adafruit 1.8" TFT shield). If the state of PA.00 is high then
+     the adafruit 1.8" TFT shield is available. */  
+  if(TFT_ShieldDetect() == SHIELD_DETECTED)
+  {
+    /* Initialize the LCD */
+    BSP_LCD_Init();
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  if (MX_FATFS_Init() != APP_OK) {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN 2 */
+    
+    /* Display on TFT Images existing on SD card */
+    TFT_DisplayImages();
+  }  
+  else /* Shield not mounted */
+  {   
+    LED2_Blink();
+  } 
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+	if (MX_FATFS_Process() != APP_OK)
+	{
+      Error_Handler();
+	}
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Displays demonstration menu.
+  * @param  None
+  * @retval None
+  */
+static void TFT_DisplayMenu(void)
+{
+  JOYState_TypeDef tmp = JOY_NONE;
+  
+  /* Set Menu font */
+  BSP_LCD_SetFont(&Font12);
+
+  /* Set Text color */
+  BSP_LCD_SetTextColor(LCD_COLOR_RED);
+  /* Display message */
+  BSP_LCD_DisplayStringAtLine(1, (uint8_t*)" NUCLEO-STM32WBxx   ");
+  BSP_LCD_DisplayStringAtLine(2, (uint8_t*)"       DEMO         ");
+  
+  /* Set Text color */
+  BSP_LCD_SetTextColor(LCD_COLOR_BLUE);
+  /* Display message */  
+  BSP_LCD_DisplayStringAtLine(4, (uint8_t*)" Display images      ");
+  BSP_LCD_DisplayStringAtLine(6, (uint8_t*)" stored under uSD    ");
+  BSP_LCD_DisplayStringAtLine(8, (uint8_t*)" on TFT LCD          ");
+  
+  /* Set Text color */
+  BSP_LCD_SetTextColor(LCD_COLOR_BLACK);
+  /* Display message */ 
+  BSP_LCD_DisplayStringAtLine(11, (uint8_t*)"  Press JOY DOWN   ");
+  BSP_LCD_DisplayStringAtLine(12, (uint8_t*)"  to continue...   ");
+ 
+  /* Wait for JOY_DOWN is pressed */
+  while (BSP_JOY_GetState() != JOY_DOWN)
+  {
+  }
+  
+  /* Wait for JOY_DOWN is released */
+  while (BSP_JOY_GetState() == JOY_DOWN)
+  {
+  }
+  
+  /* Set Text color */
+  BSP_LCD_SetTextColor(LCD_COLOR_BLACK);  
+  /* Display message */ 
+  BSP_LCD_DisplayStringAtLine(4,  (uint8_t*)"                   ");
+  BSP_LCD_DisplayStringAtLine(6,  (uint8_t*)"  Press Joystick   ");
+  
+  /* Set Text color */
+  BSP_LCD_SetTextColor(LCD_COLOR_BLUE);
+  /* Display message */ 
+  BSP_LCD_DisplayStringAtLine(8,  (uint8_t*)"  UP for:          ");
+  BSP_LCD_DisplayStringAtLine(9,  (uint8_t*)"  Manual Mode      ");
+  BSP_LCD_DisplayStringAtLine(11, (uint8_t*)"  DOWN for:        ");
+  BSP_LCD_DisplayStringAtLine(12, (uint8_t*)"  Automatic Mode   ");
+
+  /* Wait for JOY_DOWN or JOY_UP is pressed */
+  tmp = JOY_RIGHT;
+  while ((tmp != JOY_DOWN) && (tmp != JOY_UP))
+  {
+    tmp = BSP_JOY_GetState();
+  }
+  
+  /* LCD Clear */
+  BSP_LCD_Clear(LCD_COLOR_WHITE); 
+  
+  /* JOY_UP is pressed: Display Manual mode menu #############################*/
+  if(tmp == JOY_UP)
+  {
+    /* Set Text color */
+    BSP_LCD_SetTextColor(LCD_COLOR_RED);    
+    /* Display message */ 
+    BSP_LCD_DisplayStringAtLine(3,  (uint8_t*)"   Manual Mode   ");
+    BSP_LCD_DisplayStringAtLine(5,  (uint8_t*)"    Selected     "); 
+    
+    /* Set Text color */
+    BSP_LCD_SetTextColor(LCD_COLOR_BLUE);      
+    /* Display message */
+    BSP_LCD_DisplayStringAtLine(9,  (uint8_t*)" RIGHT: Next image"); 
+    BSP_LCD_DisplayStringAtLine(10, (uint8_t*)" LEFT : Previous  ");
+    BSP_LCD_DisplayStringAtLine(11, (uint8_t*)" SEL  : Switch to ");
+    BSP_LCD_DisplayStringAtLine(12, (uint8_t*)" automatic mode   ");    
+    JoystickValue = 2;  
+  }
+  /* JOY_DOWN is pressed: Display Automatic mode menu ########################*/
+  else if (tmp == JOY_DOWN)    
+  {
+    /* Set Text color */
+    BSP_LCD_SetTextColor(LCD_COLOR_RED);
+    /* Display message */ 
+    BSP_LCD_DisplayStringAtLine(3,  (uint8_t*)"  Automatic Mode  ");
+    BSP_LCD_DisplayStringAtLine(5,  (uint8_t*)"     Selected     ");
+    
+
+    JoystickValue = 1;  
+    HAL_Delay(200);
+  }
+}
+
+/**
+  * @brief  Displays on TFT Images or error messages when error occurred.
+  * @param  None
+  * @retval None
+  */
+static void TFT_DisplayImages(void)
+{    
+  uint32_t bmplen = 0x00;
+  uint32_t checkstatus = 0x00;
+  uint32_t filesnumbers = 0x00;
+  uint32_t joystickstatus = JOY_NONE;
+  uint32_t bmpcounter = 0x00;
+  uint32_t tickstart;
+  DIR directory;
+  FRESULT res;
+  
+  /* Initialize the Joystick available on adafruit 1.8" TFT shield */
+  BSP_JOY_Init();
+  
+  /* Welcome message */
+  TFT_DisplayMenu(); 
+  
+  /* Open directory */
+  res = f_opendir(&directory, "/");
+  if((res != FR_OK))
+  {
+    if(res == FR_NO_FILESYSTEM)
+    {
+      /* Display message: SD card not FAT formated */
+      TFT_DisplayErrorMessage(SD_CARD_NOT_FORMATTED);    
+    }
+    else
+    {
+      /* Display message: Fail to open directory */
+      TFT_DisplayErrorMessage(SD_CARD_OPEN_FAIL);  
+    }
+  }
+  
+  /* Get number of bitmap files */
+  filesnumbers = Storage_GetDirectoryBitmapFiles ("/", pDirectoryFiles);    
+  /* Set bitmap counter to display first image */
+  bmpcounter = 1;
+  tickstart = HAL_GetTick();
+  
+  while (1)
+  {     
+    /* Ensure a small tempo between images display unless a user action occurs */
+    while ( ((HAL_GetTick() - tickstart) < 1500) && (joystickstatus == JOY_NONE) )
+    {
+      /* Get JoyStick status */    
+      joystickstatus = BSP_JOY_GetState();
+      HAL_Delay(200);
+    }
+    
+    if(joystickstatus == JOY_SEL)
+    {      
+      JoystickValue++;
+      if (JoystickValue > 2)
+      {
+        JoystickValue = 1;
+      }
+    }
+    
+    tickstart = HAL_GetTick();
+
+    /*## Display BMP pictures in Automatic mode ##############################*/
+    if(JoystickValue == 1) 
+    {
+      sprintf((char*)str, "%-11.11s", pDirectoryFiles[bmpcounter -1]);
+      
+      checkstatus = Storage_CheckBitmapFile((const char*)str, &bmplen);
+      
+      if(checkstatus == 0)
+      {
+        /* Format the string */
+        checkstatus = Storage_OpenReadFile(POSITION_X_BITMAP, POSITION_Y_BITMAP, (const char*)str);
+      }
+      
+      if (checkstatus == 1)
+      {
+        /* Display message: File not supported */
+        TFT_DisplayErrorMessage(SD_CARD_FILE_NOT_SUPPORTED);
+      }
+
+      bmpcounter++;
+      if(bmpcounter > filesnumbers)
+      {
+        bmpcounter = 1;
+      }
+    }   
+    
+    /*## Display BMP pictures in Manual mode #################################*/
+    if(JoystickValue == 2)
+    {
+      if(joystickstatus == JOY_RIGHT)
+      {
+        if((bmpcounter + 1) > filesnumbers)
+        {
+          bmpcounter = 1;
+        }
+        else
+        {
+          bmpcounter++;
+        }
+        sprintf ((char*)str, "%-11.11s", pDirectoryFiles[bmpcounter - 1]);
+        
+        checkstatus = Storage_CheckBitmapFile((const char*)str, &bmplen);
+        
+        if(checkstatus == 0)
+        {
+          /* Format the string */
+          Storage_OpenReadFile(POSITION_X_BITMAP, POSITION_Y_BITMAP, (const char*)str); 
+        }
+        
+        if(checkstatus == 1)
+        {
+          /* Display message: File not supported */
+          TFT_DisplayErrorMessage(SD_CARD_FILE_NOT_SUPPORTED); 
+        }
+        JoystickValue = 2;          
+      }
+      else if(joystickstatus == JOY_LEFT)
+      {
+        if((bmpcounter - 1) == 0)
+        {
+          bmpcounter = filesnumbers;
+        }
+        else
+        {
+          bmpcounter--;
+        }
+        sprintf ((char*)str, "%-11.11s", pDirectoryFiles[bmpcounter - 1]); 
+        checkstatus = Storage_CheckBitmapFile((const char*)str, &bmplen);
+        
+        if(checkstatus == 0)
+        {
+          /* Format the string */
+          Storage_OpenReadFile(POSITION_X_BITMAP, POSITION_Y_BITMAP, (const char*)str); 
+        }
+        
+        if (checkstatus == 1)
+        {
+          /* Display message: File not supported */
+          TFT_DisplayErrorMessage(SD_CARD_FILE_NOT_SUPPORTED);
+        }
+        JoystickValue = 2;
+      }
+    }
+
+    joystickstatus = JOY_NONE;
+  }  
+}
+
+/**
+  * @brief  Displays adequate message on TFT available on adafruit 1.8" TFT shield  
+  * @param  message: Error message to be displayed on the LCD.
+  *   This parameter can be one of following values:   
+  *     @arg SD_CARD_NOT_FORMATTED: SD CARD is not FAT formatted
+  *     @arg SD_CARD_FILE_NOT_SUPPORTED: File is not supported
+  *     @arg SD_CARD_OPEN_FAIL: Failure to open directory
+  *     @arg FATFS_NOT_MOUNTED: FatFs is not mounted
+  * @retval None
+  */
+void TFT_DisplayErrorMessage(uint8_t message)
+{
+  /* LCD Clear */
+  BSP_LCD_Clear(LCD_COLOR_WHITE); 
+  /* Set Error Message Font */
+  BSP_LCD_SetFont(&Font12);
+  /* Set Text and Back colors */
+  BSP_LCD_SetBackColor(LCD_COLOR_GREY); 
+  BSP_LCD_SetTextColor(LCD_COLOR_RED);
+
+  if(message == SD_CARD_NOT_FORMATTED)
+  {
+    /* Display message */
+    BSP_LCD_DisplayStringAtLine(5, (uint8_t*)" SD Card is not    ");
+    BSP_LCD_DisplayStringAtLine(6, (uint8_t*)" FAT formatted.    ");  
+    BSP_LCD_DisplayStringAtLine(7, (uint8_t*)" Please Format the ");
+    BSP_LCD_DisplayStringAtLine(8, (uint8_t*)" microSD card.     ");
+    while (1)
+    {
+    }    
+  }
+  if(message == SD_CARD_FILE_NOT_SUPPORTED)
+  {
+    /* Display message */
+    BSP_LCD_DisplayStringAtLine(5, (uint8_t*)"                   ");
+    BSP_LCD_DisplayStringAtLine(6, (uint8_t*)" File type is not  ");
+    BSP_LCD_DisplayStringAtLine(7, (uint8_t*)" supported.        ");
+    BSP_LCD_DisplayStringAtLine(8, (uint8_t*)"                   ");
+    while(1)
+    {
+    }    
+  }
+  if(message == SD_CARD_OPEN_FAIL)
+  {
+    /* Display message */
+    BSP_LCD_DisplayStringAtLine(5, (uint8_t*)"                   ");
+    BSP_LCD_DisplayStringAtLine(6, (uint8_t*)" Open directory    ");
+    BSP_LCD_DisplayStringAtLine(7, (uint8_t*)" fails.            ");
+    BSP_LCD_DisplayStringAtLine(8, (uint8_t*)"                   ");
+    while(1)
+    {
+    }     
+  }
+  if(message == FATFS_NOT_MOUNTED)
+  {
+    /* Display message */
+    BSP_LCD_DisplayStringAtLine(5, (uint8_t*)"                   ");
+    BSP_LCD_DisplayStringAtLine(6, (uint8_t*)" Cannot mount      ");
+    BSP_LCD_DisplayStringAtLine(7, (uint8_t*)" FatFs on Drive.   "); 
+    BSP_LCD_DisplayStringAtLine(8, (uint8_t*)"                   ");
+    while (1)
+    {
+    }  
+  }
+  if(message == BSP_SD_INIT_FAILED)
+  {
+    /* Display message */
+    BSP_LCD_DisplayStringAtLine(5, (uint8_t*)"                   ");
+    BSP_LCD_DisplayStringAtLine(6, (uint8_t*)" SD Init           ");
+    BSP_LCD_DisplayStringAtLine(7, (uint8_t*)" fails.            ");
+    BSP_LCD_DisplayStringAtLine(8, (uint8_t*)"                   ");
+    while(1)
+    {
+    }     
+  }
+}
+
+/**
+  * @brief  Blinks LED2 with two frequencies depending on User press button.
+  * @param  None
+  * @retval None
+  */
+static void LED2_Blink(void)
+{
+  /* Configure LED2 on Nucleo */
+  BSP_LED_Init(LED2);
+
+  /* Configure the User Button in EXTI Mode */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+  
+  /* Initiate BlinkSpeed variable */ 
+  BlinkSpeed = 0;  
+  
+  /* Infinite loop */
+  while(1)
+  {
+    /* Test on blink speed */
+    if(BlinkSpeed == 0)
+    {
+      BSP_LED_Toggle(LED2);
+      /* Wait for 500ms */      
+      HAL_Delay(500);      
+    }      
+    else if(BlinkSpeed == 1)
+    {
+      BSP_LED_Toggle(LED2);
+      /* Wait for 100ms */
+      HAL_Delay(100); 
+    }
+    else if(BlinkSpeed == 2)
+    {
+      BSP_LED_Toggle(LED2);    
+      /* wait for 50ms */
+      HAL_Delay(50);  
+    }
+  }
+}
+
+/**
+  * @brief  EXTI line detection callbacks.
+  * @param  GPIO_Pin: Specifies the pins connected EXTI line
+  * @retval None
+  */
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  if(BlinkSpeed == 2)
+  {
+    BlinkSpeed = 0;
+  }
+  else
+  {
+    BlinkSpeed ++;
+  }
+}
+
+/**
+  * @brief  Check the availability of adafruit 1.8" TFT shield on top of STM32NUCLEO
+  *         board. This is done by reading the state of IO PA.00 pin (mapped to 
+  *         JoyStick available on adafruit 1.8" TFT shield). If the state of PA.00 
+  *         is high then the adafruit 1.8" TFT shield is available.
+  * @param  None
+  * @retval SHIELD_DETECTED: 1.8" TFT shield is available
+  *         SHIELD_NOT_DETECTED: 1.8" TFT shield is not available
+  */
+static ShieldStatus TFT_ShieldDetect(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStruct; 
+
+  /* Enable GPIO clock */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  
+  GPIO_InitStruct.Pin = GPIO_PIN_0;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+  
+  if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_0) != 0)  
+  {
+    return SHIELD_DETECTED;
+  }
+  else
+  {
+    return SHIELD_NOT_DETECTED;
+  }
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  BSP_LED_On(LED2);
+  while(1)
+  {
+  }	  
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..11b8d25ff
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,82 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    /Adafruit_LCD_1_8_SD_Joystick/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+extern void Error_Handler(void);
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..086c10521
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Src/stm32wbxx_it.c
@@ -0,0 +1,234 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and 
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics International N.V. 
+  * All rights reserved.
    
+  *
+  * Redistribution and use in source and binary forms, with or without 
+  * modification, are permitted, provided that the following conditions are met:
+  *
+  * 1. Redistribution of source code must retain the above copyright notice, 
+  *    this list of conditions and the following disclaimer.
+  * 2. Redistributions in binary form must reproduce the above copyright notice,
+  *    this list of conditions and the following disclaimer in the documentation
+  *    and/or other materials provided with the distribution.
+  * 3. Neither the name of STMicroelectronics nor the names of other 
+  *    contributors to this software may be used to endorse or promote products 
+  *    derived from this software without specific written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles line 0 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Core/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/Adafruit_LCD_1_8_SD_Joystick.ewd b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/Adafruit_LCD_1_8_SD_Joystick.ewd
new file mode 100644
index 000000000..9a537f2c4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/Adafruit_LCD_1_8_SD_Joystick.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		Adafruit_LCD_1_8_SD_Joystick
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/Adafruit_LCD_1_8_SD_Joystick.ewp b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/Adafruit_LCD_1_8_SD_Joystick.ewp
new file mode 100644
index 000000000..55951d54b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/Adafruit_LCD_1_8_SD_Joystick.ewp
@@ -0,0 +1,1197 @@
+
+
+    3
+    
+        Adafruit_LCD_1_8_SD_Joystick
+        
+            ARM
+        
+        1
+        
+            General
+            3
+            
+                30
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            ICCARM
+            2
+            
+                34
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            AARM
+            2
+            
+                10
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            OBJCOPY
+            0
+            
+                1
+                1
+                1
+                
+                
+                
+                
+                
+            
+        
+        
+            CUSTOM
+            3
+            
+                
+                
+                0
+            
+        
+        
+            BICOMP
+            0
+            
+        
+        
+            BUILDACTION
+            1
+            
+                
+                
+            
+        
+        
+            ILINK
+            0
+            
+                20
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            IARCHIVE
+            0
+            
+                0
+                1
+                1
+                
+                
+                
+            
+        
+        
+            BILINK
+            0
+            
+        
+    
+    
+        Application
+        
+            EWARM
+            
+                $PROJ_DIR$\startup_stm32wb35xx_cm4.s
+            
+        
+        
+            User
+            
+                Core
+                
+                    $PROJ_DIR$\..\Core\Src\main.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\stm32wbxx_hal_msp.c
+                
+                
+                    $PROJ_DIR$\..\Core\Src\stm32wbxx_it.c
+                
+            
+            
+                FATFS
+                
+                    App
+                    
+                        $PROJ_DIR$\..\FATFS\App\app_fatfs.c
+                    
+                
+                
+                    Target
+                    
+                        $PROJ_DIR$\..\FATFS\Target\sd_diskio.c
+                    
+                
+            
+        
+    
+    
+        Doc
+        
+            $PROJ_DIR$\..\readme.txt
+        
+    
+    
+        Drivers
+        
+            BSP
+            
+                Adafruit_Shield
+                
+                    $PROJ_DIR$\..\..\..\..\..\Drivers\BSP\Adafruit_Shield\stm32_adafruit_lcd.c
+                
+                
+                    $PROJ_DIR$\..\..\..\..\..\Drivers\BSP\Adafruit_Shield\stm32_adafruit_sd.c
+                
+            
+            
+                Components
+                
+                    $PROJ_DIR$\..\..\..\..\..\Drivers\BSP\Components\st7735\st7735.c
+                
+            
+            
+                NUCLEO-WB35CE
+                
+                    $PROJ_DIR$\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE\nucleo_wb35ce.c
+                
+            
+        
+        
+            CMSIS
+            
+                $PROJ_DIR$\..\Core\Src\system_stm32wbxx.c
+            
+        
+        
+            STM32WBxx_HAL_Driver
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_adc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_adc_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_cortex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_exti.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_gpio.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_hsem.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_spi.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_spi_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim_ex.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_ll_adc.c
+            
+        
+    
+    
+        Middlewares
+        
+            FatFs
+            
+                $PROJ_DIR$\..\..\..\..\..\Middlewares\Third_Party\FatFs\src\option\ccsbcs.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Middlewares\Third_Party\FatFs\src\diskio.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Middlewares\Third_Party\FatFs\src\ff.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Middlewares\Third_Party\FatFs\src\ff_gen_drv.c
+            
+            
+                $PROJ_DIR$\..\..\..\..\..\Middlewares\Third_Party\FatFs\src\option\syscall.c
+            
+        
+    
+
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/Project.eww
new file mode 100644
index 000000000..d7393a941
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\Adafruit_LCD_1_8_SD_Joystick.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..43a793371
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/App/app_fatfs.c b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/App/app_fatfs.c
new file mode 100644
index 000000000..a3ae2feae
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/App/app_fatfs.c
@@ -0,0 +1,320 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Adafruit_LCD_1_8_SD_Joystick/FatFs/App/app_fatfs.c
+  * @author  MCD Application Team
+  * @brief   FatFs_uSD_Standalone application file
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_fatfs.h"
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include 
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define FATFS_MKFS_ALLOWED 1
+#define BITMAP_BUFFER_SIZE 512//1 * 512 /* You can adapt this size depending on the amount of RAM available */
+#define BITMAP_HEADER_SIZE sizeof(BmpHeader) /* Bitmap specificity */
+#define MIN(a,b) (((a)<(b))?(a):(b))
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+FATFS SDFatFs;    /* File system object for SD logical drive */
+FIL SDFile;       /* File  object for SD */
+char SDPath[4];   /* SD logical drive path */
+/* USER CODE BEGIN PV */
+uint32_t counter = 0;
+uint8_t aBuffer[BITMAP_HEADER_SIZE + BITMAP_BUFFER_SIZE];
+FILINFO MyFileInfo;
+DIR MyDirectory;
+FIL MyFile;
+UINT BytesWritten, BytesRead;
+extern char* pDirectoryFiles[MAX_BMP_FILES];
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/**
+  * @brief  FatFs initialization
+  * @param  None
+  * @retval Initialization result 
+  */
+int32_t MX_FATFS_Init(void) 
+{
+  /*## FatFS: Link the disk I/O driver(s)  ###########################*/
+  if (FATFS_LinkDriver(&SD_Driver, SDPath) != 0)
+  /* USER CODE BEGIN FATFS_Init */
+  {
+    return APP_ERROR;
+  }
+  else
+  {
+	/* Initialize the SD mounted on adafruit 1.8" TFT shield */
+    if(BSP_SD_Init() != MSD_OK)
+    {
+      TFT_DisplayErrorMessage(BSP_SD_INIT_FAILED);
+	  return APP_ERROR;
+    }  
+    
+    /* Check the mounted device */
+    if(f_mount(&SDFatFs, (TCHAR const*)"/", 0) != FR_OK)
+    {
+      TFT_DisplayErrorMessage(FATFS_NOT_MOUNTED);
+	  return APP_ERROR;
+    }  
+    else
+    {
+      /* Initialize the Directory Files pointers (heap) */
+      for (counter = 0; counter < MAX_BMP_FILES; counter++)
+      {
+        pDirectoryFiles[counter] = malloc(11); 
+      }
+    }
+    return APP_OK;
+  }
+  /* USER CODE END FATFS_Init */
+}
+
+/**
+  * @brief  FatFs application main process
+  * @param  None
+  * @retval Process result 
+  */
+int32_t MX_FATFS_Process(void)
+{
+  /* USER CODE BEGIN FATFS_Process */
+  return APP_OK;
+  /* USER CODE END FATFS_Process */
+}  
+
+/**
+  * @brief  Gets Time from RTC (generated when FS_NORTC==0; see ff.c)
+  * @param  None
+  * @retval Time in DWORD
+  */
+DWORD get_fattime(void)
+{
+  /* USER CODE BEGIN get_fattime */
+  return 0;
+  /* USER CODE END get_fattime */  
+}
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN Application */
+/**
+  * @brief  Open a file and display it on lcd
+  * @param  DirName: the Directory name to open
+  * @param  FileName: the file name to open
+  * @param  BufferAddress: A pointer to a buffer to copy the file to
+  * @param  FileLen: the File length
+  * @retval err: Error status (0=> success, 1=> fail)
+  */
+uint32_t Storage_OpenReadFile(uint8_t Xpoz, uint16_t Ypoz, const char *BmpName)
+{
+  uint32_t size = 0;
+  FIL bmpfile;
+  uint32_t nbline;
+  BmpHeader* pbmpheader = (BmpHeader*)aBuffer;
+  
+  /* Close a bmp file */
+  f_open(&bmpfile, BmpName, FA_READ);
+  
+  /* Read the constant part of the header from the file and store it at the top of aBuffer*/
+  f_read(&bmpfile, &aBuffer, BITMAP_HEADER_SIZE, &BytesRead);
+  
+  /* Get the size of the data stored inside the file */
+  size = pbmpheader->fsize - pbmpheader->offset;
+  
+  /* Start reading at the top of the file */
+  f_lseek(&bmpfile, 0);
+  
+  /* Read the entire header from the file and store it at the top of aBuffer */
+  f_read(&bmpfile, &aBuffer, pbmpheader->offset, &BytesRead);
+  
+  /* Compute the number of entire lines which can be stored inside the buffer */
+  nbline = (BITMAP_BUFFER_SIZE - pbmpheader->offset + BITMAP_HEADER_SIZE)/(pbmpheader->w * 2);
+  
+  /* As long as the entire bitmap file as not been displayed */
+  do
+  {
+    uint32_t nbbytetoread;
+    
+    /* Get the number of bytes which can be stored inside the buffer */
+    nbbytetoread = MIN(size,nbline*pbmpheader->w*2);
+  
+    /* Adapt the total size of the bitmap, stored inside the header, to this chunck */
+    pbmpheader->fsize = pbmpheader->offset + nbbytetoread;
+  
+    /* Adapt the number of line, stored inside the header, to this chunck */
+    pbmpheader->h = nbbytetoread/(pbmpheader->w*2);
+    
+    /* Start reading at the end of the file */
+    f_lseek(&bmpfile, pbmpheader->offset + size - nbbytetoread);
+    
+    /* Store this chunck (or the entire part if possible) of the file inside a buffer */
+    f_read(&bmpfile, aBuffer + pbmpheader->offset, nbbytetoread, &BytesRead);
+  
+    /* Draw the bitmap */
+    BSP_LCD_DrawBitmap(Xpoz, Ypoz, aBuffer);    
+      
+    /* Update the remaining number of bytes to read */
+    size -= nbbytetoread;
+    
+    /* Change the display position of the next bitmap */
+    Ypoz += nbline;
+      
+  }while (size > 0);
+  
+  /* Close the bmp file */
+  f_close(&bmpfile);
+  
+  return 0;
+}      
+
+/**
+  * @brief  Copy file BmpName1 to BmpName2 
+  * @param  BmpName1: the source file name
+  * @param  BmpName2: the destination file name
+  * @retval err: Error status (0=> success, 1=> fail)
+  */
+uint32_t Storage_CopyFile(const char* BmpName1, const char* BmpName2)
+{
+  uint32_t index = 0;
+  FIL file1, file2;
+  
+  /* Open an Existent BMP file system */
+  f_open(&file1, BmpName1, FA_READ);
+  /* Create a new BMP file system */
+  f_open(&file2, BmpName2, FA_CREATE_ALWAYS | FA_WRITE);
+  
+  do 
+  {
+    f_read(&file1, aBuffer, _MAX_SS, &BytesRead);
+    f_write(&file2, aBuffer, _MAX_SS, &BytesWritten);  
+    index+= _MAX_SS;
+    
+  } while(index < f_size(&file1));
+  
+  f_close(&file1);
+  f_close(&file2);
+  
+  return 1;
+}
+
+/**
+  * @brief  Opens a file and copies its content to a buffer.
+  * @param  DirName: the Directory name to open
+  * @param  FileName: the file name to open
+  * @param  BufferAddress: A pointer to a buffer to copy the file to
+  * @param  FileLen: File length
+  * @retval err: Error status (0=> success, 1=> fail)
+  */
+uint32_t Storage_CheckBitmapFile(const char* BmpName, uint32_t *FileLen)
+{
+  uint32_t err = 0;
+ 
+  if(f_open(&MyFile, BmpName, FA_READ) != FR_OK)
+  {
+    err = 1;
+  }
+  f_close(&MyFile);  
+  return err;
+}
+
+/**
+  * @brief  List up to 25 file on the root directory with extension .BMP
+  * @param  DirName: Directory name
+  * @param  Files: Buffer to contain read files
+  * @retval The number of the found files
+  */
+uint32_t Storage_GetDirectoryBitmapFiles(const char* DirName, char* Files[])
+{
+  FRESULT res;
+  uint32_t index = 0;
+
+  /* Start to search for wave files */
+  res = f_findfirst(&MyDirectory, &MyFileInfo, DirName, "*.bmp");
+  
+  /* Repeat while an item is found */
+  while (MyFileInfo.fname[0])
+  {
+    if(res == FR_OK)
+    {
+      if(index < MAX_BMP_FILES)
+      {
+        sprintf (Files[index++], "%s", MyFileInfo.fname);
+      }
+      /* Search for next item */
+      res = f_findnext(&MyDirectory, &MyFileInfo);
+    }
+    else
+    {
+      index = 0;
+      break;
+    }
+  }
+  
+  f_closedir(&MyDirectory);
+  
+  return index;
+}
+
+/**
+  * @brief  Compares two buffers.
+  * @param  pBuffer1, pBuffer2: buffers to be compared
+  * @param  BufferLength: buffer's length
+  * @retval  0: pBuffer1 identical to pBuffer2
+  *          1: pBuffer1 differs from pBuffer2
+  */
+uint8_t Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
+{
+  uint8_t ret = 1;
+  
+  while (BufferLength--)
+  {
+    if(*pBuffer1 != *pBuffer2)
+    {
+      ret = 0;
+    }
+    
+    pBuffer1++;
+    pBuffer2++;
+  }
+  
+  return ret;
+}
+
+/* USER CODE END Application */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/App/app_fatfs.h b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/App/app_fatfs.h
new file mode 100644
index 000000000..dd7703bca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/App/app_fatfs.h
@@ -0,0 +1,95 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Adafruit_LCD_1_8_SD_Joystick/FatFs/App/app_fatfs.h
+  * @author  MCD Application Team
+  * @brief   Header for FatFs_uSD_Standalone.c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_FATFS_H
+#define __APP_FATFS_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "ff.h"
+#include "ff_gen_drv.h"
+#include "sd_diskio.h" /* defines SD_Driver as external */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */     
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+/* Header of a bitmap file */
+#pragma pack(1) /* Mandatory to remove any padding */
+typedef struct BmpHeader
+{
+  uint8_t  B;
+  uint8_t  M;
+  uint32_t fsize;
+  uint16_t res1;
+  uint16_t res2;
+  uint32_t offset;
+  uint32_t hsize;
+  uint32_t w;
+  uint32_t h;
+  uint16_t planes;
+  uint16_t bpp;
+  uint32_t ctype;
+  uint32_t dsize;
+  uint32_t hppm;
+  uint32_t vppm;
+  uint32_t colorsused;
+  uint32_t colorreq;
+}BmpHeader;
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+int32_t MX_FATFS_Init(void);
+int32_t MX_FATFS_Process(void);
+/* USER CODE BEGIN EFP */
+uint32_t Storage_OpenReadFile(uint8_t Xpoz, uint16_t Ypoz, const char *BmpName);
+uint32_t Storage_CopyFile(const char *BmpName1, const char *BmpName2);
+uint32_t Storage_GetDirectoryBitmapFiles(const char* DirName, char* Files[]);
+uint32_t Storage_CheckBitmapFile(const char *BmpName, uint32_t *FileLen);
+uint8_t  Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+extern FATFS SDFatFs;    /* File system object for SD logical drive */
+extern FIL SDFile;       /* File  object for SD */
+extern char SDPath[4];   /* SD logical drive path */
+
+#endif /*__APP_FATFS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/Target/ffconf.h b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/Target/ffconf.h
new file mode 100644
index 000000000..24f266d6a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/Target/ffconf.h
@@ -0,0 +1,268 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  *  FatFs - Generic FAT file system module  R0.12c (C)ChaN, 2017
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+#ifndef _FFCONF
+#define _FFCONF 68300	/* Revision ID */
+
+/*-----------------------------------------------------------------------------/
+/ Additional user header to be used  
+/-----------------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_hal.h"
+
+/*-----------------------------------------------------------------------------/
+/ Function Configurations
+/-----------------------------------------------------------------------------*/
+
+#define _FS_READONLY         0      /* 0:Read/Write or 1:Read only */
+/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
+/  Read-only configuration removes writing API functions, f_write(), f_sync(),
+/  f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
+/  and optional writing functions as well. */
+
+#define _FS_MINIMIZE         0      /* 0 to 3 */
+/* This option defines minimization level to remove some basic API functions.
+/
+/   0: All basic functions are enabled.
+/   1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
+/      are removed.
+/   2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
+/   3: f_lseek() function is removed in addition to 2. */
+
+#define _USE_STRFUNC         0      /* 0:Disable or 1-2:Enable */
+/* This option switches string functions, f_gets(), f_putc(), f_puts() and
+/  f_printf().
+/
+/  0: Disable string functions.
+/  1: Enable without LF-CRLF conversion.
+/  2: Enable with LF-CRLF conversion. */
+
+#define _USE_FIND            1
+/* This option switches filtered directory read functions, f_findfirst() and
+/  f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
+
+#define _USE_MKFS            1
+/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
+
+#define _USE_FASTSEEK        1
+/* This option switches fast seek feature. (0:Disable or 1:Enable) */
+
+#define	_USE_EXPAND		0
+/* This option switches f_expand function. (0:Disable or 1:Enable) */
+
+#define _USE_CHMOD		0
+/* This option switches attribute manipulation functions, f_chmod() and f_utime().
+/  (0:Disable or 1:Enable) Also _FS_READONLY needs to be 0 to enable this option. */
+
+#define _USE_LABEL           0
+/* This option switches volume label functions, f_getlabel() and f_setlabel().
+/  (0:Disable or 1:Enable) */
+
+#define _USE_FORWARD         0
+/* This option switches f_forward() function. (0:Disable or 1:Enable) */
+
+/*-----------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/-----------------------------------------------------------------------------*/
+
+#define _CODE_PAGE         850
+/* This option specifies the OEM code page to be used on the target system.
+/  Incorrect setting of the code page can cause a file open failure.
+/
+/   1   - ASCII (No extended character. Non-LFN cfg. only)
+/   437 - U.S.
+/   720 - Arabic
+/   737 - Greek
+/   771 - KBL
+/   775 - Baltic
+/   850 - Latin 1
+/   852 - Latin 2
+/   855 - Cyrillic
+/   857 - Turkish
+/   860 - Portuguese
+/   861 - Icelandic
+/   862 - Hebrew
+/   863 - Canadian French
+/   864 - Arabic
+/   865 - Nordic
+/   866 - Russian
+/   869 - Greek 2
+/   932 - Japanese (DBCS)
+/   936 - Simplified Chinese (DBCS)
+/   949 - Korean (DBCS)
+/   950 - Traditional Chinese (DBCS)
+*/
+
+#define _USE_LFN     3    /* 0 to 3 */
+#define _MAX_LFN     255  /* Maximum LFN length to handle (12 to 255) */
+/* The _USE_LFN switches the support of long file name (LFN).
+/
+/   0: Disable support of LFN. _MAX_LFN has no effect.
+/   1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
+/   2: Enable LFN with dynamic working buffer on the STACK.
+/   3: Enable LFN with dynamic working buffer on the HEAP.
+/
+/  To enable the LFN, Unicode handling functions (option/unicode.c) must be added
+/  to the project. The working buffer occupies (_MAX_LFN + 1) * 2 bytes and
+/  additional 608 bytes at exFAT enabled. _MAX_LFN can be in range from 12 to 255.
+/  It should be set 255 to support full featured LFN operations.
+/  When use stack for the working buffer, take care on stack overflow. When use heap
+/  memory for the working buffer, memory management functions, ff_memalloc() and
+/  ff_memfree(), must be added to the project. */
+
+#define _LFN_UNICODE    0 /* 0:ANSI/OEM or 1:Unicode */
+/* This option switches character encoding on the API. (0:ANSI/OEM or 1:UTF-16)
+/  To use Unicode string for the path name, enable LFN and set _LFN_UNICODE = 1.
+/  This option also affects behavior of string I/O functions. */
+
+#define _STRF_ENCODE    3
+/* When _LFN_UNICODE == 1, this option selects the character encoding ON THE FILE to
+/  be read/written via string I/O functions, f_gets(), f_putc(), f_puts and f_printf().
+/
+/  0: ANSI/OEM
+/  1: UTF-16LE
+/  2: UTF-16BE
+/  3: UTF-8
+/
+/  This option has no effect when _LFN_UNICODE == 0. */
+
+#define _FS_RPATH       0 /* 0 to 2 */
+/* This option configures support of relative path.
+/
+/   0: Disable relative path and remove related functions.
+/   1: Enable relative path. f_chdir() and f_chdrive() are available.
+/   2: f_getcwd() function is available in addition to 1.
+*/
+
+/*---------------------------------------------------------------------------/
+/ Drive/Volume Configurations
+/----------------------------------------------------------------------------*/
+
+#define _VOLUMES    2
+/* Number of volumes (logical drives) to be used. */
+
+/* USER CODE BEGIN Volumes */  
+#define _STR_VOLUME_ID          0	/* 0:Use only 0-9 for drive ID, 1:Use strings for drive ID */
+#define _VOLUME_STRS            "RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3"
+/* _STR_VOLUME_ID switches string support of volume ID.
+/  When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive
+/  number in the path name. _VOLUME_STRS defines the drive ID strings for each
+/  logical drives. Number of items must be equal to _VOLUMES. Valid characters for
+/  the drive ID strings are: A-Z and 0-9. */
+/* USER CODE END Volumes */  
+
+#define _MULTI_PARTITION     0 /* 0:Single partition, 1:Multiple partition */
+/* This option switches support of multi-partition on a physical drive.
+/  By default (0), each logical drive number is bound to the same physical drive
+/  number and only an FAT volume found on the physical drive will be mounted.
+/  When multi-partition is enabled (1), each logical drive number can be bound to
+/  arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
+/  funciton will be available. */
+#define _MIN_SS    512  /* 512, 1024, 2048 or 4096 */
+#define _MAX_SS    512  /* 512, 1024, 2048 or 4096 */
+/* These options configure the range of sector size to be supported. (512, 1024,
+/  2048 or 4096) Always set both 512 for most systems, all type of memory cards and
+/  harddisk. But a larger value may be required for on-board flash memory and some
+/  type of optical media. When _MAX_SS is larger than _MIN_SS, FatFs is configured
+/  to variable sector size and GET_SECTOR_SIZE command must be implemented to the
+/  disk_ioctl() function. */
+
+#define	_USE_TRIM      0
+/* This option switches support of ATA-TRIM. (0:Disable or 1:Enable)
+/  To enable Trim function, also CTRL_TRIM command should be implemented to the
+/  disk_ioctl() function. */
+
+#define _FS_NOFSINFO    0 /* 0,1,2 or 3 */
+/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
+/  option, and f_getfree() function at first time after volume mount will force
+/  a full FAT scan. Bit 1 controls the use of last allocated cluster number.
+/
+/  bit0=0: Use free cluster count in the FSINFO if available.
+/  bit0=1: Do not trust free cluster count in the FSINFO.
+/  bit1=0: Use last allocated cluster number in the FSINFO if available.
+/  bit1=1: Do not trust last allocated cluster number in the FSINFO.
+*/
+
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/----------------------------------------------------------------------------*/
+
+#define _FS_TINY    0      /* 0:Normal or 1:Tiny */
+/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
+/  At the tiny configuration, size of file object (FIL) is reduced _MAX_SS bytes.
+/  Instead of private sector buffer eliminated from the file object, common sector
+/  buffer in the file system object (FATFS) is used for the file data transfer. */
+
+#define _FS_EXFAT	0
+/* This option switches support of exFAT file system. (0:Disable or 1:Enable)
+/  When enable exFAT, also LFN needs to be enabled. (_USE_LFN >= 1)
+/  Note that enabling exFAT discards C89 compatibility. */
+
+#define _FS_NORTC	0
+#define _NORTC_MON	6
+#define _NORTC_MDAY	4
+#define _NORTC_YEAR	2015
+/* The option _FS_NORTC switches timestamp functiton. If the system does not have
+/  any RTC function or valid timestamp is not needed, set _FS_NORTC = 1 to disable
+/  the timestamp function. All objects modified by FatFs will have a fixed timestamp
+/  defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR in local time.
+/  To enable timestamp function (_FS_NORTC = 0), get_fattime() function need to be
+/  added to the project to get current time form real-time clock. _NORTC_MON,
+/  _NORTC_MDAY and _NORTC_YEAR have no effect. 
+/  These options have no effect at read-only configuration (_FS_READONLY = 1). */
+
+#define _FS_LOCK    12     /* 0:Disable or >=1:Enable */
+/* The option _FS_LOCK switches file lock function to control duplicated file open
+/  and illegal operation to open objects. This option must be 0 when _FS_READONLY
+/  is 1.
+/
+/  0:  Disable file lock function. To avoid volume corruption, application program
+/      should avoid illegal open, remove and rename to the open objects.
+/  >0: Enable file lock function. The value defines how many files/sub-directories
+/      can be opened simultaneously under file lock control. Note that the file
+/      lock control is independent of re-entrancy. */
+
+#define _FS_REENTRANT    0  /* 0:Disable or 1:Enable */
+#define _FS_TIMEOUT      1000 /* Timeout period in unit of time ticks */
+#define _SYNC_t          NULL
+/* The option _FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
+/  module itself. Note that regardless of this option, file access to different
+/  volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
+/  and f_fdisk() function, are always not re-entrant. Only file/directory access
+/  to the same volume is under control of this function.
+/
+/   0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect.
+/   1: Enable re-entrancy. Also user provided synchronization handlers,
+/      ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
+/      function, must be added to the project. Samples are available in
+/      option/syscall.c.
+/
+/  The _FS_TIMEOUT defines timeout period in unit of time tick.
+/  The _SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
+/  SemaphoreHandle_t and etc.. A header file for O/S definitions needs to be
+/  included somewhere in the scope of ff.h. */
+
+/* define the ff_malloc ff_free macros as standard malloc free */
+#if !defined(ff_malloc) && !defined(ff_free)
+#include 
+#define ff_malloc  malloc
+#define ff_free  free
+#endif
+
+#endif /* _FFCONF */
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/Target/sd_diskio.c b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/Target/sd_diskio.c
new file mode 100644
index 000000000..17ad24771
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/Target/sd_diskio.c
@@ -0,0 +1,239 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Src/sd_diskio.c
+  * @author  MCD Application Team
+  * @brief   SD Disk I/O driver
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "ff_gen_drv.h"
+#include "sd_diskio.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#if defined(SDMMC_DATATIMEOUT)
+#define SD_TIMEOUT SDMMC_DATATIMEOUT
+#elif defined(SD_DATATIMEOUT)
+#define SD_TIMEOUT SD_DATATIMEOUT
+#else
+#define SD_TIMEOUT 30 * 1000
+#endif
+
+#define SD_DEFAULT_BLOCK_SIZE 512
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* Disk status */
+static volatile DSTATUS Stat = STA_NOINIT;
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+static DSTATUS SD_CheckStatus(BYTE lun);
+DSTATUS SD_initialize (BYTE);
+DSTATUS SD_status (BYTE);
+DRESULT SD_read (BYTE, BYTE*, DWORD, UINT);
+#if _USE_WRITE == 1
+  DRESULT SD_write (BYTE, const BYTE*, DWORD, UINT);
+#endif /* _USE_WRITE == 1 */
+#if _USE_IOCTL == 1
+  DRESULT SD_ioctl (BYTE, BYTE, void*);
+#endif  /* _USE_IOCTL == 1 */
+
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+const Diskio_drvTypeDef  SD_Driver =
+{
+  SD_initialize,
+  SD_status,
+  SD_read,
+#if  _USE_WRITE == 1
+  SD_write,
+#endif /* _USE_WRITE == 1 */
+
+#if  _USE_IOCTL == 1
+  SD_ioctl,
+#endif /* _USE_IOCTL == 1 */
+};
+
+/* Private functions ---------------------------------------------------------*/
+static DSTATUS SD_CheckStatus(BYTE lun)
+{
+  Stat = STA_NOINIT;
+  if(BSP_SD_GetCardState() == BSP_SD_OK)
+  {
+    Stat &= ~STA_NOINIT;
+  }
+
+  return Stat;
+}
+
+/**
+  * @brief  Initializes a Drive
+  * @param  lun : not used
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS SD_initialize(BYTE lun)
+{
+  /* USER CODE BEGIN SDinitialize */
+  Stat = STA_NOINIT;
+#if !defined(DISABLE_SD_INIT)
+
+  if(BSP_SD_Init() == MSD_OK)
+  {
+    Stat = SD_CheckStatus(lun);
+  }
+
+#else
+  Stat = SD_CheckStatus(lun);
+#endif
+  return Stat;
+  /* USER CODE END SDinitialize */
+}
+
+/**
+  * @brief  Gets Disk Status
+  * @param  lun : not used
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS SD_status(BYTE lun)
+{
+  return SD_CheckStatus(lun);
+}
+
+/**
+  * @brief  Reads Sector(s)
+  * @param  lun : not used
+  * @param  *buff: Data buffer to store read data
+  * @param  sector: Sector address (LBA)
+  * @param  count: Number of sectors to read (1..128)
+  * @retval DRESULT: Operation result
+  */
+DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count)
+{
+  DRESULT res = RES_ERROR;
+  if(BSP_SD_ReadBlocks((uint32_t*)buff,
+                       (uint32_t) (sector),
+                       count, SD_TIMEOUT) == BSP_SD_OK)
+  {
+    /* wait until the read operation is finished */
+    while(BSP_SD_GetCardState()!= BSP_SD_OK)
+    {
+    }
+    res = RES_OK;
+  }
+  return res;
+}
+
+/**
+  * @brief  Writes Sector(s)
+  * @param  lun : not used
+  * @param  *buff: Data to be written
+  * @param  sector: Sector address (LBA)
+  * @param  count: Number of sectors to write (1..128)
+  * @retval DRESULT: Operation result
+  */
+#if _USE_WRITE == 1
+DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count)
+{
+  DRESULT res = RES_ERROR;
+  if(BSP_SD_WriteBlocks((uint32_t*)buff,
+                        (uint32_t)(sector),
+                        count, SD_TIMEOUT) == MSD_OK)
+  {
+  /* wait until the Write operation is finished */
+    while(BSP_SD_GetCardState() != BSP_SD_OK)
+    {
+    }
+    res = RES_OK;
+  }
+
+  return res;
+
+}
+#endif /* _USE_WRITE == 1 */
+
+/**
+  * @brief  I/O control operation
+  * @param  lun : not used
+  * @param  cmd: Control code
+  * @param  *buff: Buffer to send/receive control data
+  * @retval DRESULT: Operation result
+  */
+#if _USE_IOCTL == 1
+DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff)
+{
+  DRESULT res = RES_ERROR;
+  BSP_SD_CardInfo CardInfo;
+
+  if (Stat & STA_NOINIT) return RES_NOTRDY;
+
+  switch (cmd)
+  {
+  /* Make sure that no pending write process */
+  case CTRL_SYNC :
+    res = RES_OK;
+    break;
+
+  /* Get number of sectors on the disk (DWORD) */
+  case GET_SECTOR_COUNT :
+    BSP_SD_GetCardInfo(&CardInfo);
+    *(DWORD*)buff = CardInfo.LogBlockNbr;
+    res = RES_OK;
+    break;
+
+  /* Get R/W sector size (WORD) */
+  case GET_SECTOR_SIZE :
+    BSP_SD_GetCardInfo(&CardInfo);
+    *(WORD*)buff = CardInfo.LogBlockSize;
+    res = RES_OK;
+    break;
+
+  /* Get erase block size in unit of sector (DWORD) */
+  case GET_BLOCK_SIZE :
+    BSP_SD_GetCardInfo(&CardInfo);
+    *(DWORD*)buff = CardInfo.LogBlockSize / SD_DEFAULT_BLOCK_SIZE;
+	res = RES_OK;
+    break;
+
+  default:
+    res = RES_PARERR;
+  }
+
+  return res;
+}
+#endif /* _USE_IOCTL == 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/Target/sd_diskio.h b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/Target/sd_diskio.h
new file mode 100644
index 000000000..b3ac10b64
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/FATFS/Target/sd_diskio.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Demonstrations/Adafruit_LCD_1_8_SD_Joystick/Inc/sd_diskio.h
+  * @author  MCD Application Team
+  * @brief   Header for sd_diskio.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __SD_DISKIO_H
+#define __SD_DISKIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+extern const Diskio_drvTypeDef  SD_Driver;
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SD_DISKIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/MDK-ARM/Adafruit_LCD_1_8_SD_Joystick.uvoptx b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/MDK-ARM/Adafruit_LCD_1_8_SD_Joystick.uvoptx
new file mode 100644
index 000000000..0c5ec8907
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/MDK-ARM/Adafruit_LCD_1_8_SD_Joystick.uvoptx
@@ -0,0 +1,717 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    Adafruit_LCD_1_8_SD_Joystick
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U0667FF303337554E43181419 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User/Core
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Core/Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Core/Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Core/Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Application/User/FATFS/Target
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      1
+      0
+      0
+      0
+      ../FATFS/Target/sd_diskio.c
+      sd_diskio.c
+      0
+      0
+    
+  
+
+  
+    Application/User/FATFS/App
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../FATFS/App/app_fatfs.c
+      app_fatfs.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/Adafruit_Shield
+    0
+    0
+    0
+    0
+    
+      7
+      8
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_sd.c
+      stm32_adafruit_sd.c
+      0
+      0
+    
+    
+      7
+      9
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_lcd.c
+      stm32_adafruit_lcd.c
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/Components
+    0
+    0
+    0
+    0
+    
+      8
+      10
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/BSP/Components/st7735/st7735.c
+      st7735.c
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      9
+      11
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      10
+      12
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+      stm32wbxx_hal_spi.c
+      0
+      0
+    
+    
+      10
+      13
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+      stm32wbxx_hal_spi_ex.c
+      0
+      0
+    
+    
+      10
+      14
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
+      stm32wbxx_hal_adc.c
+      0
+      0
+    
+    
+      10
+      15
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c
+      stm32wbxx_hal_adc_ex.c
+      0
+      0
+    
+    
+      10
+      16
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+      stm32wbxx_ll_adc.c
+      0
+      0
+    
+    
+      10
+      17
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      10
+      18
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      10
+      19
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      10
+      20
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      10
+      21
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      10
+      22
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      10
+      23
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      10
+      24
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      10
+      25
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      10
+      26
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      10
+      27
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      10
+      28
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      10
+      29
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      10
+      30
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      10
+      31
+      1
+      0
+      0
+      0
+      ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      11
+      32
+      1
+      0
+      0
+      0
+      ../Core/Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    Middlewares/FatFs
+    0
+    0
+    0
+    0
+    
+      12
+      33
+      1
+      0
+      0
+      0
+      ../../../../../Middlewares/Third_Party/FatFs/src/diskio.c
+      diskio.c
+      0
+      0
+    
+    
+      12
+      34
+      1
+      0
+      0
+      0
+      ../../../../../Middlewares/Third_Party/FatFs/src/ff.c
+      ff.c
+      0
+      0
+    
+    
+      12
+      35
+      1
+      0
+      0
+      0
+      ../../../../../Middlewares/Third_Party/FatFs/src/ff_gen_drv.c
+      ff_gen_drv.c
+      0
+      0
+    
+    
+      12
+      36
+      1
+      0
+      0
+      0
+      ../../../../../Middlewares/Third_Party/FatFs/src/option/syscall.c
+      syscall.c
+      0
+      0
+    
+    
+      12
+      37
+      1
+      0
+      0
+      0
+      ../../../../../Middlewares/Third_Party/FatFs/src/option/ccsbcs.c
+      ccsbcs.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/MDK-ARM/Adafruit_LCD_1_8_SD_Joystick.uvprojx b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/MDK-ARM/Adafruit_LCD_1_8_SD_Joystick.uvprojx
new file mode 100644
index 000000000..eff943f75
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/MDK-ARM/Adafruit_LCD_1_8_SD_Joystick.uvprojx
@@ -0,0 +1,642 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      Adafruit_LCD_1_8_SD_Joystick
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          Adafruit_LCD_1_8_SD_Joystick\
+          Adafruit_LCD_1_8_SD_Joystick
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_STM32WBXX_NUCLEO,USE_HAL_DRIVER,STM32WB35xx
+              
+              ../FATFS/Target;../FATFS/App;../Core/Inc;../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../Middlewares/Third_Party/FatFs/src;../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../Drivers/CMSIS/Include;../../../../../Drivers/BSP/NUCLEO-WB35CE;../../../../../Drivers/BSP/Adafruit_Shield;../../../../../Drivers/BSP/Components;../../../../../Drivers/BSP/Components/Common
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User/Core
+          
+            
+              main.c
+              1
+              ../Core/Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Core/Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Core/Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Application/User/FATFS/Target
+          
+            
+              sd_diskio.c
+              1
+              ../FATFS/Target/sd_diskio.c
+            
+          
+        
+        
+          Application/User/FATFS/App
+          
+            
+              app_fatfs.c
+              1
+              ../FATFS/App/app_fatfs.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/Adafruit_Shield
+          
+            
+              stm32_adafruit_sd.c
+              1
+              ../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_sd.c
+            
+            
+              stm32_adafruit_lcd.c
+              1
+              ../../../../../Drivers/BSP/Adafruit_Shield/stm32_adafruit_lcd.c
+            
+          
+        
+        
+          Drivers/BSP/Components
+          
+            
+              st7735.c
+              1
+              ../../../../../Drivers/BSP/Components/st7735/st7735.c
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_spi.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+            
+            
+              stm32wbxx_hal_spi_ex.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+            
+            
+              stm32wbxx_hal_adc.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
+            
+            
+              stm32wbxx_hal_adc_ex.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c
+            
+            
+              stm32wbxx_ll_adc.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Core/Src/system_stm32wbxx.c
+            
+          
+        
+        
+          Middlewares/FatFs
+          
+            
+              diskio.c
+              1
+              ../../../../../Middlewares/Third_Party/FatFs/src/diskio.c
+            
+            
+              ff.c
+              1
+              ../../../../../Middlewares/Third_Party/FatFs/src/ff.c
+            
+            
+              ff_gen_drv.c
+              1
+              ../../../../../Middlewares/Third_Party/FatFs/src/ff_gen_drv.c
+            
+            
+              syscall.c
+              1
+              ../../../../../Middlewares/Third_Party/FatFs/src/option/syscall.c
+            
+            
+              ccsbcs.c
+              1
+              ../../../../../Middlewares/Third_Party/FatFs/src/option/ccsbcs.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..ae049b184
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x1000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x1000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..9059c2340
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/.cproject
@@ -0,0 +1,183 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/.project
new file mode 100644
index 000000000..2d55b9ce9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/.project
@@ -0,0 +1,221 @@
+
+
+	Adafruit_LCD_1_8_SD_Joystick
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			Adafruit_LCD_1_8_SD_Joystick.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Adafruit_LCD_1_8_SD_Joystick.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Core/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Core/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Core/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Core/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_adc.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_adc_ex.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_spi.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_spi_ex.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_adc.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+		
+		
+			Middlewares/FatFs/ccsbcs.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Middlewares/Third_Party/FatFs/src/option/ccsbcs.c
+		
+		
+			Middlewares/FatFs/diskio.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Middlewares/Third_Party/FatFs/src/diskio.c
+		
+		
+			Middlewares/FatFs/ff.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Middlewares/Third_Party/FatFs/src/ff.c
+		
+		
+			Middlewares/FatFs/ff_gen_drv.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Middlewares/Third_Party/FatFs/src/ff_gen_drv.c
+		
+		
+			Middlewares/FatFs/syscall.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Middlewares/Third_Party/FatFs/src/option/syscall.c
+		
+		
+			Drivers/BSP/Adafruit_Shield/stm32_adafruit_lcd.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/BSP/Adafruit_Shield/stm32_adafruit_lcd.c
+		
+		
+			Drivers/BSP/Adafruit_Shield/stm32_adafruit_sd.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/BSP/Adafruit_Shield/stm32_adafruit_sd.c
+		
+		
+			Drivers/BSP/Components/st7735.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/BSP/Components/st7735/st7735.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-5-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+		
+			Application/User/FATFS/App/app_fatfs.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/FATFS/App/app_fatfs.c
+		
+		
+			Application/User/FATFS/Target/sd_diskio.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/FATFS/Target/sd_diskio.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..eea98ff9c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb35xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB35xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f9a002eb7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x1000 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x1000 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/readme.txt b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/readme.txt
new file mode 100644
index 000000000..3f2e72462
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Demonstrations/Adafruit_LCD_1_8_SD_Joystick/readme.txt
@@ -0,0 +1,158 @@
+/**
+  @page Demo   Demo NUCLEO-WB35CE
+ 
+  @verbatim
+  ******************************************************************************
+  * @file    readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of NUCLEO-WB35CE Demo
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics International N.V. All rights reserved.
+  *
+  * Redistribution and use in source and binary forms, with or without 
+  * modification, are permitted, provided that the following conditions are met:
+  *
+  * 1. Redistribution of source code must retain the above copyright notice, 
+  *    this list of conditions and the following disclaimer.
+  * 2. Redistributions in binary form must reproduce the above copyright notice,
+  *    this list of conditions and the following disclaimer in the documentation
+  *    and/or other materials provided with the distribution.
+  * 3. Neither the name of STMicroelectronics nor the names of other 
+  *    contributors to this software may be used to endorse or promote products 
+  *    derived from this software without specific written permission.
+  * 4. This software, including modifications and/or derivative works of this 
+  *    software, must execute solely and exclusively on microcontroller or
+  *    microprocessor devices manufactured by or for STMicroelectronics.
+  * 5. Redistribution and use of this software other than as permitted under 
+  *    this license is void and will automatically terminate your rights under 
+  *    this license. 
+  *
+  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" 
+  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT 
+  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 
+  * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
+  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT 
+  * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 
+  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 
+  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 
+  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Demo Description
+
+This demonstration firmware is based on STM32Cube. It helps you to discover STM32
+Cortex-M devices that can be plugged on a STM32 Nucleo board.
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system clock
+(SYSCLK) to run at 64 MHz.
+ 
+ 
+Below you find the sequence to discover the demonstration :
+
+ - Check the availability of adafruit 1.8" TFT shield on top of STM32 Nucleo 
+   board. This is done by reading the state of IO PA.00 pin (mapped to JoyStick 
+   available on adafruit 1.8" TFT shield). If the state of PA.00 is high then 
+   the adafruit 1.8" TFT shield is available. 
+    
+   - Adafruit 1.8" TFT shield is not available:
+     LED2 is toggling with a first frequency equal to ~1Hz.
+     Pressing User button lets LED2 toggling with a second frequency equal to ~5Hz.
+     Pressing User button again, changes LED2 toggling frequency to ~10Hz.
+     This is done in an infinite loop.      
+
+   - Adafruit 1.8" TFT shield is available:
+     LED3 is turned ON, because it's sharing the same pin with the SPI CLK signal
+     used to communicate with the Adafruit 1.8" TFT shield.
+     A menu will be displayed on TFT. Follow instructions below:
+     
+     - Joystick DOWN to continue menu display
+     - Choose the desired display mode: Press Joystick DOWN for automatic mode 
+       or Joystick UP for manual mode.
+       
+       - Manual Mode selected:
+         Images available on SD Card, are displayed by pressing Joystick RIGHT 
+         to display next image or Joystick LEFT to display previous one. 
+         Pressing long (~1s) Joystick SEL, switches display mode to automatic one.
+       
+       - Automatic Mode selected:
+         Images available on SD Card are displayed sequentially in a forever loop.
+
+
+It is worth noting that the application manages some errors occurring during the 
+access to uSD card to parse bmp images:
+
+ - If SD Card is not FAT formatted, a message will be displayed on TFT. 
+   In this case, format the SD card and put into its root directory the .bmp 
+   files available within the FW package under Utilities\Media\Pictures folder.
+
+ - If the content of the SD card is other than a bitmap file, a message will 
+   be displayed on TFT mentioning that it is not supported.
+   In this case, put into the SD card's root directory the .bmp 
+   files available within the FW package under Utilities\Media\Images\Nucleo folder which are respecting
+   the following criteria:
+   o Dimensions: 128x160
+   o Width: 128 pixels
+   o Height: 160 pixels
+   o Bit depth: 16
+   o Item type: BMP file
+   o The name of the bmp image file must not exceed 11 characters (including
+     .bmp extension).
+
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate
+      delay (in milliseconds) based on variable incremented in SysTick ISR. 
+      This implies that if HAL_Delay() is called from a peripheral ISR process, 
+      then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application need to ensure that the SysTick time base is always set to
+      1 millisecond to have correct HAL operation.
+
+@par Directory contents
+ 
+  - Adafruit_LCD_1_8_SD_Joystick/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - Adafruit_LCD_1_8_SD_Joystick/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - Adafruit_LCD_1_8_SD_Joystick/Inc/main.h                        Header for main.c module
+  - Adafruit_LCD_1_8_SD_Joystick/Inc/app_fatfs.h                   Header for app_fatfs.c module
+  - Adafruit_LCD_1_8_SD_Joystick/Inc/ffconf.h                      FAT file system module configuration file   
+  - Adafruit_LCD_1_8_SD_Joystick/Src/stm32wbxx_it.c          Interrupt handlers
+  - Adafruit_LCD_1_8_SD_Joystick/Src/stm32wbxx_hal_msp.c     HAL MSP configuration file
+  - Adafruit_LCD_1_8_SD_Joystick/Src/main.c                        Main program
+  - Adafruit_LCD_1_8_SD_Joystick/Src/app_fatfs.c                   FatFs application file
+  - Adafruit_LCD_1_8_SD_Joystick/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.      
+    
+  - A SDSC microSD card (capacity up to 8GB), must contain the .bmp files at root
+    available under the FW package Utilities\Media\Pictures folder.
+
+  - Adafruit 1.8" TFT shield must be connected on CN5,CN6, CN8 and CN9 Arduino connectors, 
+    for more details please refer to UM1726.
+
+
+For more details about the adafruit 1.8" TFT shield, please visit: 
+http://www.adafruit.com/blog/2012/04/26/new-product-adafruit-1-8-18-bit-color-tft-shield-wmicrosd-and-joystick/
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+  - Open your preferred toolchain 
+  - Rebuild all files and load your image into target memory
+  - Run the example
+ 
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/.extSettings b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/.extSettings
new file mode 100644
index 000000000..0858dfa8d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=ADC;ADC
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/ADC_SingleConversion_TriggerSW_IT.ioc b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/ADC_SingleConversion_TriggerSW_IT.ioc
new file mode 100644
index 000000000..48da4b66a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/ADC_SingleConversion_TriggerSW_IT.ioc
@@ -0,0 +1,106 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=ADC_SingleConversion_TriggerSW_IT.ioc
+ProjectManager.ProjectName=ADC_SingleConversion_TriggerSW_IT
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/ADC_SingleConversion_TriggerSW_IT.ewd b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/ADC_SingleConversion_TriggerSW_IT.ewd
new file mode 100644
index 000000000..9a6d86fb3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/ADC_SingleConversion_TriggerSW_IT.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		ADC_SingleConversion_TriggerSW_IT
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/ADC_SingleConversion_TriggerSW_IT.ewp b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/ADC_SingleConversion_TriggerSW_IT.ewp
new file mode 100644
index 000000000..90aaa41bf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/ADC_SingleConversion_TriggerSW_IT.ewp
@@ -0,0 +1,1128 @@
+
+
+  3
+  
+    ADC_SingleConversion_TriggerSW_IT
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/Project.eww
new file mode 100644
index 000000000..8d249907a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\ADC_SingleConversion_TriggerSW_IT.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/main.h
new file mode 100644
index 000000000..bffc2c2d4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/main.h
@@ -0,0 +1,124 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+/* Definitions of environment analog values */
+  /* Value of analog reference voltage (Vref+), connected to analog voltage   */
+  /* supply Vdda (unit: mV).                                                  */
+  #define VDDA_APPLI                       ((uint32_t)3300)
+  
+/* Definitions of data related to this example */
+  /* Full-scale digital value with a resolution of 12 bits (voltage range     */
+  /* determined by analog voltage references Vref+ and Vref-,                 */
+  /* refer to reference manual).                                              */
+  #define DIGITAL_SCALE_12BITS             ((uint32_t) 0xFFF)
+
+  /* Init variable out of ADC expected conversion data range */
+  #define VAR_CONVERTED_DATA_INIT_VALUE    (DIGITAL_SCALE_12BITS + 1)
+
+/* ## Definition of ADC related resources ################################### */
+/* Definition of ADCx clock resources */
+#define ADCx                            ADC1
+#define ADCx_CLK_ENABLE()               __HAL_RCC_ADC_CLK_ENABLE()
+
+#define ADCx_FORCE_RESET()              __HAL_RCC_ADC_FORCE_RESET()
+#define ADCx_RELEASE_RESET()            __HAL_RCC_ADC_RELEASE_RESET()
+
+/* Definition of ADCx channels */
+#define ADCx_CHANNELa                   ADC_CHANNEL_9
+
+/* Definition of ADCx NVIC resources */
+#define ADCx_IRQn                       ADC1_IRQn
+#define ADCx_IRQHandler                 ADC1_IRQHandler
+
+/* Definition of ADCx channels pins */
+#define ADCx_CHANNELa_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
+#define ADCx_CHANNELa_GPIO_PORT         GPIOA
+#define ADCx_CHANNELa_PIN               GPIO_PIN_4
+
+
+/* Private macro -------------------------------------------------------------*/
+
+/**
+  * @brief  Macro to calculate the voltage (unit: mVolt)
+  *         corresponding to a ADC conversion data (unit: digital value).
+  * @note   ADC measurement data must correspond to a resolution of 12bits
+  *         (full scale digital value 4095). If not the case, the data must be
+  *         preliminarily rescaled to an equivalent resolution of 12 bits.
+  * @note   Analog reference voltage (Vref+) must be known from
+  *         user board environment.
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *                       (unit: digital value).
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __ADC_CALC_DATA_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__)       \
+  ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) / DIGITAL_SCALE_12BITS)
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..7e43311e8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+#define HAL_ADC_MODULE_ENABLED
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..57263ea7c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_it.h
@@ -0,0 +1,66 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void EXTI0_IRQHandler(void);
+
+void ADCx_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/ADC_SingleConversion_TriggerSW_IT.uvoptx b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/ADC_SingleConversion_TriggerSW_IT.uvoptx
new file mode 100644
index 000000000..73fd03b33
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/ADC_SingleConversion_TriggerSW_IT.uvoptx
@@ -0,0 +1,533 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    ADC_SingleConversion_TriggerSW_IT
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
+      stm32wbxx_hal_adc.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c
+      stm32wbxx_hal_adc_ex.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+      stm32wbxx_ll_adc.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      24
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      25
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/ADC_SingleConversion_TriggerSW_IT.uvprojx b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/ADC_SingleConversion_TriggerSW_IT.uvprojx
new file mode 100644
index 000000000..9a2af316e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/ADC_SingleConversion_TriggerSW_IT.uvprojx
@@ -0,0 +1,556 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      ADC_SingleConversion_TriggerSW_IT
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          ADC_SingleConversion_TriggerSW_IT\
+          ADC_SingleConversion_TriggerSW_IT
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_adc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
+            
+            
+              stm32wbxx_hal_adc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c
+            
+            
+              stm32wbxx_ll_adc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..c4a6c235d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.cproject
@@ -0,0 +1,170 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.project
new file mode 100644
index 000000000..cfc8df772
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.project
@@ -0,0 +1,160 @@
+
+
+	ADC_SingleConversion_TriggerSW_IT
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			ADC_SingleConversion_TriggerSW_IT.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/ADC_SingleConversion_TriggerSW_IT.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_adc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_adc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_adc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.settings/language.settings.xml b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.settings/language.settings.xml
new file mode 100644
index 000000000..f49ce6100
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.settings/language.settings.xml
@@ -0,0 +1,27 @@
+
+
+	
+		
+			
+			
+			
+			
+			
+				
+				
+			
+		
+	
+	
+		
+			
+			
+			
+			
+			
+				
+				
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/main.c
new file mode 100644
index 000000000..1cfe37c2b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/main.c
@@ -0,0 +1,490 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/main.c
+  * @author  MCD Application Team
+  * @brief   Use ADC to convert a single channel at each SW start.
+  *          Conversion performed using programming model: interrupt
+  *          (for programming models polling or DMA transfer, refer to other examples).
+  *          Example using the STM32WBxx ADC HAL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* Peripherals handlers declaration */
+/* ADC handler declaration */
+ADC_HandleTypeDef    AdcHandle;
+/* Variables for ADC conversion data */
+__IO   uint16_t   uhADCxConvertedData = VAR_CONVERTED_DATA_INIT_VALUE; /* ADC group regular conversion data */
+
+/* Variables for ADC conversion data computation to physical values */
+uint16_t   uhADCxConvertedData_Voltage_mVolt = 0;  /* Value of voltage calculated from ADC conversion data (unit: mV) */
+
+/* Variable to report status of ADC group regular unitary conversion          */
+/*  0: ADC group regular unitary conversion is not completed                  */
+/*  1: ADC group regular unitary conversion is completed                      */
+/*  2: ADC group regular unitary conversion has not been started yet          */
+/*     (initial state)                                                        */
+__IO   uint8_t ubAdcGrpRegularUnitaryConvStatus = 2; /* Variable set into ADC interruption callback */
+
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+static void Configure_ADC(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+  
+  /* Initialize LED on board */
+  BSP_LED_Init(LED2);
+  
+/* Configure ADC */
+  /* Note: This function configures the ADC but does not enable it.           */
+  /*       Only ADC internal voltage regulator is enabled by function         */
+  /*       "HAL_ADC_Init()".                                                  */
+  /*       To activate ADC (ADC enable and ADC conversion start), use         */
+  /*       function "HAL_ADC_Start_xxx()".                                    */
+  /*       This is intended to optimize power consumption:                    */
+  /*       1. ADC configuration can be done once at the beginning             */
+  /*          (ADC disabled, minimal power consumption)                       */
+  /*       2. ADC enable (higher power consumption) can be done just before   */
+  /*          ADC conversions needed.                                         */
+  /*          Then, possible to perform successive ADC activation and         */
+  /*          deactivation without having to set again ADC configuration.     */
+  Configure_ADC();
+  
+  
+  /* Run the ADC calibration in single-ended mode */
+  if (HAL_ADCEx_Calibration_Start(&AdcHandle, ADC_SINGLE_ENDED) != HAL_OK)
+  {
+    /* Calibration Error */
+    Error_Handler();
+  }
+
+  
+  /*## Enable peripherals ####################################################*/
+  
+  /* Note: ADC is enabled afterwards when starting ADC conversion using       */
+  /*       function "HAL_ADC_Start_xxx()".                                    */
+  
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* Note: At this step, a voltage can be supplied to ADC channel input     */
+    /*       (by connecting an external signal voltage generator to the       */
+    /*       analog input pin) to perform a ADC conversion on a determined    */
+    /*       voltage level.                                                   */
+    /*       Otherwise, ADC channel input can be let floating, in this case   */
+    /*       ADC conversion data will be undetermined.                        */
+
+    /* Turn LED off before performing a new ADC conversion start */
+    BSP_LED_Off(LED2);
+    
+    /* Reset status variable of ADC group regular unitary conversion before   */
+    /* performing a new ADC group regular conversion start.                   */
+    ubAdcGrpRegularUnitaryConvStatus = 0;
+    
+    /* Init variable containing ADC conversion data */
+    uhADCxConvertedData = VAR_CONVERTED_DATA_INIT_VALUE;
+    
+    /*## Start ADC conversions ###############################################*/
+    
+    /* Start ADC group regular conversion with IT */
+    if (HAL_ADC_Start_IT(&AdcHandle) != HAL_OK)
+    {
+      /* ADC conversion start error */
+      Error_Handler();
+    }
+    
+    /* Wait till conversion is done */
+    while (ubAdcGrpRegularUnitaryConvStatus == 0);
+
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    /* Note: LED state depending on conversion status set in ADC              */
+    /*       IRQ handler, refer to functions "HAL_ADC_ConvCpltCallback()"     */
+
+    /* Note: ADC conversions data are stored into variable                    */
+    /*       "uhADCxConvertedData".                                           */
+    /*       (for debug: see variable content into watch window).             */
+    
+    /* Note: ADC conversion data are computed to physical values              */
+    /*       into variable "uhADCxConvertedData_Voltage_mVolt"                */
+    /*       using helper macro "__ADC_CALC_DATA_VOLTAGE()".                  */
+    /*       (for debug: see variable content into watch window).             */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  Configure ADC (ADC instance: ADCx) and GPIO used by ADC channels.
+  *         Configuration of GPIO:
+  *           - Pin:                    PA.04 (on this STM32 device, ADC1 channel 9 is mapped on this GPIO)
+  *           - Mode:                   analog
+  *         Configuration of ADC:
+  *         - Common to several ADC:
+  *           - Conversion clock:       Synchronous from PCLK
+  *           - Internal path:          None                         (default configuration from reset state)
+  *         - Multimode
+  *           Feature not used: all parameters let to default configuration from reset state
+  *           - Mode                    Independent                  (default configuration from reset state)
+  *           - DMA transfer:           Disabled                     (default configuration from reset state)
+  *           - Delay sampling phases   1 ADC clock cycle            (default configuration from reset state)
+  *         - ADC instance
+  *           - Resolution:             12 bits                      (default configuration from reset state)
+  *           - Data alignment:         right aligned                (default configuration from reset state)
+  *           - Low power mode:         disabled                     (default configuration from reset state)
+  *           - Offset:                 none                         (default configuration from reset state)
+  *         - Group regular
+
+  *           - Continuous mode:        single conversion            (default configuration from reset state)
+  *           - DMA transfer:           disabled                     (default configuration from reset state)
+  *           - Overrun:                data overwritten
+  *           - Sequencer length:       disabled: 1 rank             (default configuration from reset state)
+  *           - Sequencer discont:      disabled: sequence done in 1 scan (default configuration from reset state)
+  *           - Sequencer rank 1:       ADCx ADCx_CHANNELa
+  *         - Group injected
+  *           Feature not used: all parameters let to default configuration from reset state
+  *           - Trigger source:         SW start                     (default configuration from reset state)
+  *           - Trigger edge:           not applicable with SW start
+  *           - Auto injection:         disabled                     (default configuration from reset state)
+  *           - Contexts queue:         disabled                     (default configuration from reset state)
+  *           - Sequencer length:       disabled: 1 rank             (default configuration from reset state)
+  *           - Sequencer discont:      disabled: sequence done in 1 scan (default configuration from reset state)
+  *           - Sequencer rank 1:       first channel available      (default configuration from reset state)
+  *         - Channel
+  *           - Sampling time:          ADCx ADCx_CHANNELa set to sampling time 47.5 ADC clock cycles (on this STM32 serie, sampling time is channel wise)
+  *           - Differential mode:      single ended                 (default configuration from reset state)
+  *         - Analog watchdog
+  *           Feature not used: all parameters let to default configuration from reset state
+  *           - AWD number:             1
+  *           - Monitored channels:     none                         (default configuration from reset state)
+  *           - Threshold high:         0x000                        (default configuration from reset state)
+  *           - Threshold low:          0xFFF                        (default configuration from reset state)
+  *         - Oversampling
+  *           Feature not used: all parameters let to default configuration from reset state
+  *           - Scope:                  none                         (default configuration from reset state)
+  *           - Discontinuous mode:     disabled                     (default configuration from reset state)
+  *           - Ratio:                  2                            (default configuration from reset state)
+  *           - Shift:                  none                         (default configuration from reset state)
+  *         - Interruptions
+  *           None: with HAL driver, ADC interruptions are set using
+  *           function "HAL_ADC_start_xxx()".
+  * @note   Using HAL driver, configuration of GPIO used by ADC channels,
+  *         NVIC and clock source at top level (RCC)
+  *         are not implemented into this function,
+  *         must be implemented into function "HAL_ADC_MspInit()".
+  * @param  None
+  * @retval None
+  */
+__STATIC_INLINE void Configure_ADC(void)
+{
+  ADC_ChannelConfTypeDef   sConfig;
+  
+  /*## Configuration of ADC ##################################################*/
+  
+  /*## Configuration of ADC hierarchical scope: ##############################*/
+  /*## common to several ADC, ADC instance, ADC group regular  ###############*/
+  
+  /* Set ADC instance of HAL ADC handle AdcHandle */
+  AdcHandle.Instance = ADCx;
+  
+  /* Configuration of HAL ADC handle init structure:                          */
+  /* parameters of scope ADC instance and ADC group regular.                  */
+  /* Note: On this STM32 serie, ADC group regular sequencer is                */
+  /*       fully configurable: sequencer length and each rank                 */
+  /*       affectation to a channel are configurable.                         */
+  AdcHandle.Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV2;
+  AdcHandle.Init.Resolution            = ADC_RESOLUTION_12B;
+  AdcHandle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+  AdcHandle.Init.ScanConvMode          = ADC_SCAN_DISABLE;              /* Sequencer disabled (ADC conversion on only 1 channel: channel set on rank 1) */
+  AdcHandle.Init.EOCSelection          = ADC_EOC_SINGLE_CONV;
+  AdcHandle.Init.LowPowerAutoWait      = DISABLE;
+  AdcHandle.Init.ContinuousConvMode    = DISABLE;                       /* Continuous mode disabled to have only 1 conversion at each conversion trig */
+  AdcHandle.Init.NbrOfConversion       = 1;                             /* Parameter discarded because sequencer is disabled */
+  AdcHandle.Init.DiscontinuousConvMode = DISABLE;                       /* Parameter discarded because sequencer is disabled */
+  AdcHandle.Init.NbrOfDiscConversion   = 1;                             /* Parameter discarded because sequencer is disabled */
+  AdcHandle.Init.ExternalTrigConv      = ADC_SOFTWARE_START;            /* Software start to trig the 1st conversion manually, without external event */
+  AdcHandle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE; /* Parameter discarded because trig of conversion by software start (no external event) */
+  AdcHandle.Init.DMAContinuousRequests = DISABLE;                       /* ADC with DMA transfer: continuous requests to DMA disabled (default state) since DMA is not used in this example. */
+  AdcHandle.Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN;
+  AdcHandle.Init.OversamplingMode      = DISABLE;
+  
+  if (HAL_ADC_Init(&AdcHandle) != HAL_OK)
+  {
+    /* ADC initialization error */
+    Error_Handler();
+  }
+  
+  
+  /*## Configuration of ADC hierarchical scope: ##############################*/
+  /*## ADC group injected and channels mapped on group injected ##############*/
+  
+  /* Note: ADC group injected not used and not configured in this example.    */
+  /*       Refer to other ADC examples using this feature.                    */
+  /* Note: Call of the functions below are commented because they are         */
+  /*       useless in this example:                                           */
+  /*       setting corresponding to default configuration from reset state.   */
+  
+  
+  /*## Configuration of ADC hierarchical scope: ##############################*/
+  /*## channels mapped on group regular         ##############################*/
+  
+  /* Configuration of channel on ADCx regular group on sequencer rank 1 */
+  /* Note: On this STM32 serie, ADC group regular sequencer is                */
+  /*       fully configurable: sequencer length and each rank                 */
+  /*       affectation to a channel are configurable.                         */
+  /* Note: Considering IT occurring after each ADC conversion                 */
+  /*       (IT by ADC group regular end of unitary conversion),               */
+  /*       select sampling time and ADC clock with sufficient                 */
+  /*       duration to not create an overhead situation in IRQHandler.        */
+  sConfig.Channel      = ADCx_CHANNELa;               /* ADC channel selection */
+  sConfig.Rank         = ADC_REGULAR_RANK_1;          /* ADC group regular rank in which is mapped the selected ADC channel */
+  sConfig.SamplingTime = ADC_SAMPLETIME_47CYCLES_5;  /* ADC channel sampling time */
+  sConfig.SingleDiff   = ADC_SINGLE_ENDED;            /* ADC channel differential mode */
+  sConfig.OffsetNumber = ADC_OFFSET_NONE;             /* ADC channel affected to offset number */
+  sConfig.Offset       = 0;                           /* Parameter discarded because offset correction is disabled */
+  
+  if (HAL_ADC_ConfigChannel(&AdcHandle, &sConfig) != HAL_OK)
+  {
+    /* Channel Configuration Error */
+    Error_Handler();
+  }
+  
+  
+  /*## Configuration of ADC hierarchical scope: multimode ####################*/
+  /* Note: ADC multimode is not available on this device:                     */
+  /*       only 1 ADC instance is present.                                    */
+  
+  
+  /*## Configuration of ADC transversal scope: analog watchdog ###############*/
+  
+  /* Note: ADC analog watchdog not used and not configured in this example.   */
+  /*       Refer to other ADC examples using this feature.                    */
+  
+  
+  /*## Configuration of ADC transversal scope: oversampling ##################*/
+  
+  /* Note: ADC oversampling not used and not configured in this example.      */
+  /*       Refer to other ADC examples using this feature.                    */
+  
+}
+
+
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT                                               */
+/******************************************************************************/
+
+
+/**
+  * @brief  Conversion complete callback in non blocking mode 
+  * @param  hadc: ADC handle
+  * @note   This example shows a simple way to report end of conversion
+  *         and get conversion result. You can add your own implementation.
+  * @retval None
+  */
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Retrieve ADC conversion data */
+  uhADCxConvertedData = HAL_ADC_GetValue(hadc);
+  
+  /* Computation of ADC conversions raw data to physical values           */
+  /* using helper macro.                                                  */
+  uhADCxConvertedData_Voltage_mVolt = __ADC_CALC_DATA_VOLTAGE(VDDA_APPLI, uhADCxConvertedData);
+  
+  /* Update status variable of ADC unitary conversion                     */
+  ubAdcGrpRegularUnitaryConvStatus = 1;
+  
+  /* Set LED depending on ADC unitary conversion status                   */
+  /* - Turn-on if ADC group regular unitary conversion is completed       */
+  /* - Turn-off if ADC group regular unitary conversion is not completed  */
+  BSP_LED_On(LED2);
+}
+
+/**
+  * @brief  ADC error callback in non blocking mode
+  *        (ADC conversion with interruption or transfer by DMA)
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+  /* In case of ADC error, call main error handler */
+  Error_Handler();
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  while(1) 
+  {
+    /* Toggle LED2 */
+    BSP_LED_Off(LED2);
+    HAL_Delay(800);
+    BSP_LED_On(LED2);
+    HAL_Delay(10);
+    BSP_LED_Off(LED2);
+    HAL_Delay(180);
+    BSP_LED_On(LED2);
+    HAL_Delay(10);
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  Error_Handler();
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..f8f532304
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,156 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/**
+  * @brief ADC MSP initialization
+  *        This function configures the hardware resources used in this example:
+  *          - Enable clock of ADC peripheral
+  *          - Configure the GPIO associated to the peripheral channels
+  *          - Configure the DMA associated to the peripheral
+  *          - Configure the NVIC associated to the peripheral interruptions
+  * @param hadc: ADC handle pointer
+  * @retval None
+  */
+void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
+{
+  GPIO_InitTypeDef          GPIO_InitStruct;
+  
+  /*##-1- Enable peripherals and GPIO Clocks #################################*/
+  /* Enable clock of GPIO associated to the peripheral channels */
+  ADCx_CHANNELa_GPIO_CLK_ENABLE();
+  
+  /* Enable clock of ADCx peripheral (core clock) */
+  ADCx_CLK_ENABLE();
+  
+  /* Note: In case of usage of asynchronous clock for ADC, with ADC setting   */
+  /*       "AdcHandle.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIVx",            */
+  /*       the clock source has to be enabled at RCC top level using function */
+  /*       "HAL_RCCEx_PeriphCLKConfig()" or macro "__HAL_RCC_ADC_CONFIG()"    */
+  /*       (refer to comments in driver file header).                         */
+
+  /*##-2- Configure peripheral GPIO ##########################################*/
+  /* Configure GPIO pin of the selected ADC channel */
+  GPIO_InitStruct.Pin = ADCx_CHANNELa_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(ADCx_CHANNELa_GPIO_PORT, &GPIO_InitStruct);
+  
+  /*##-4- Configure the NVIC #################################################*/
+  /* NVIC configuration for ADC interrupt */
+  /* Priority: high-priority */
+  HAL_NVIC_SetPriority(ADCx_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(ADCx_IRQn);
+}
+
+/**
+  * @brief ADC MSP de-initialization
+  *        This function frees the hardware resources used in this example:
+  *          - Disable clock of ADC peripheral
+  *          - Revert GPIO associated to the peripheral channels to their default state
+  *          - Revert DMA associated to the peripheral to its default state
+  *          - Revert NVIC associated to the peripheral interruptions to its default state
+  * @param hadc: ADC handle pointer
+  * @retval None
+  */
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
+{
+  /*##-1- Reset peripherals ##################################################*/
+  ADCx_FORCE_RESET();
+  ADCx_RELEASE_RESET();
+
+  /*##-2- Disable peripherals and GPIO Clocks ################################*/
+  /* De-initialize GPIO pin of the selected ADC channel */
+  HAL_GPIO_DeInit(ADCx_CHANNELa_GPIO_PORT, ADCx_CHANNELa_PIN);
+
+  /*##-3- Disable the DMA ####################################################*/
+  /* De-Initialize the DMA associated to the peripheral */
+  if(hadc->DMA_Handle != NULL)
+  {
+    HAL_DMA_DeInit(hadc->DMA_Handle);
+  }
+
+  /*##-4- Disable the NVIC ###################################################*/
+  /* Disable the NVIC configuration for ADC interrupt */
+  HAL_NVIC_DisableIRQ(ADCx_IRQn);
+  
+}
+
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..a02aee08f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_it.c
@@ -0,0 +1,133 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+extern ADC_HandleTypeDef    AdcHandle;
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+
+/**
+  * @brief  This function handles ADC interrupt request.
+  * @param  None
+  * @retval None
+  */
+void ADCx_IRQHandler(void)
+{
+  HAL_ADC_IRQHandler(&AdcHandle);
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/readme.txt b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/readme.txt
new file mode 100644
index 000000000..d97416766
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerSW_IT/readme.txt
@@ -0,0 +1,97 @@
+/**
+  @page ADC_SingleConversion_TriggerSW_IT ADC example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples/ADC/ADC_SingleConversion_TriggerSW_IT/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the ADC_SingleConversion_TriggerSW_IT example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+Use ADC to convert a single channel at each SW start, 
+conversion performed using programming model: interrupt 
+
+Example configuration:
+ADC is configured to convert a single channel, in single conversion mode,
+from SW trigger.
+ADC interruption enabled: EOC (end of conversion of ADC group regular).
+
+Example execution:
+The ADC performs 1 conversion of the selected channel. When conversion is completed,
+ADC interruption occurs. IRQ handler callback function reads conversion data from
+ADC data register and stores it into a variable, LED2 is turned on.
+
+For debug: variables to monitor with debugger watch window:
+ - "uhADCxConvertedData": ADC group regular conversion data
+ - "uhADCxConvertedData_Voltage_mVolt": ADC conversion data computation to physical values
+
+Connection needed:
+None.
+Note: Optionally, a voltage can be supplied to the analog input pin (cf pin below),
+      between 0V and Vdda=3.3V, to perform a ADC conversion on a determined
+      voltage level.
+      Otherwise, this pin can be let floating (in this case ADC conversion data
+      will be undetermined).
+
+Other peripherals used:
+  1 GPIO for LED
+  1 GPIO for analog input: PA4 (Arduino connector CN8 pin A0, Morpho connector CN7 pin 28)
+
+Board settings:
+ - ADC is configured to convert ADC_CHANNEL_9 (Arduino connector CN8 pin A0, Morpho connector CN7 pin 28).
+ - The voltage input on ADC channel must be provided by an external source connected to Arduino connector CN8 pin A0, Morpho connector CN7 pin 28.
+
+
+To observe voltage level applied on ADC channel through GPIO, connect a voltmeter on
+pin PA4 (Arduino connector CN8 pin A0, Morpho connector CN7 pin 28).
+
+NUCLEO-WB35CE board LED is be used to monitor the program execution status:
+ - Normal operation: LED2 is turned-on/off in function of ADC conversion
+   result.
+    - "On" upon conversion completion
+    - "Off" during conversion
+ - Error: In case of error, LED2 is toggling twice at a frequency of 1Hz.
+
+@par Keywords
+
+Analog, ADC, Analog to Digital, single conversion, Software trigger, interrupt.
+
+@par Directory contents 
+
+  - ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - ADC/ADC_SingleConversion_TriggerSW_IT/Inc/main.h                        Header for main.c module  
+  - ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_it.c          Interrupt handlers
+  - ADC/ADC_SingleConversion_TriggerSW_IT/Src/main.c                        Main program
+  - ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_hal_msp.c     HAL MSP module
+  - ADC/ADC_SingleConversion_TriggerSW_IT/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35xx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/.extSettings b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/.extSettings
new file mode 100644
index 000000000..3f7938341
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=ADC
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/ADC_SingleConversion_TriggerTimer_DMA.ioc b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/ADC_SingleConversion_TriggerTimer_DMA.ioc
new file mode 100644
index 000000000..cb13c9a0d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/ADC_SingleConversion_TriggerTimer_DMA.ioc
@@ -0,0 +1,121 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=TIM2
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.Pin1=VP_TIM2_VS_ClockSourceINT
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.TIM2_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=ADC_SingleConversion_TriggerTimer_DMA.ioc
+ProjectManager.ProjectName=ADC_SingleConversion_TriggerTimer_DMA
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+TIM2.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_DISABLE
+TIM2.ClockDivision=TIM_CLOCKDIVISION_DIV1
+TIM2.CounterMode=TIM_COUNTERMODE_UP
+TIM2.IPParameters=Prescaler,CounterMode,Period,ClockDivision,AutoReloadPreload,TIM_MasterSlaveMode,TIM_MasterOutputTrigger,PERIOD,PRESCALER
+TIM2.PERIOD=39999
+TIM2.PRESCALER=1
+TIM2.Period=39999
+TIM2.Prescaler=1
+TIM2.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE
+TIM2.TIM_MasterSlaveMode=TIM_MASTERSLAVEMODE_DISABLE
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+VP_TIM2_VS_ClockSourceINT.Mode=Internal
+VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/ADC_SingleConversion_TriggerTimer_DMA.ewd b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/ADC_SingleConversion_TriggerTimer_DMA.ewd
new file mode 100644
index 000000000..09f1cbfdf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/ADC_SingleConversion_TriggerTimer_DMA.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		ADC_SingleConversion_TriggerTimer_DMA
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/ADC_SingleConversion_TriggerTimer_DMA.ewp b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/ADC_SingleConversion_TriggerTimer_DMA.ewp
new file mode 100644
index 000000000..5c78159a8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/ADC_SingleConversion_TriggerTimer_DMA.ewp
@@ -0,0 +1,1128 @@
+
+
+  3
+  
+    ADC_SingleConversion_TriggerTimer_DMA
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/Project.eww
new file mode 100644
index 000000000..b0c2bc927
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\ADC_SingleConversion_TriggerTimer_DMA.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Inc/main.h
new file mode 100644
index 000000000..a3ad7af59
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Inc/main.h
@@ -0,0 +1,141 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+/* User can use this section to tailor ADCx instance under use and associated
+   resources */
+
+/* ## Definition of ADC related resources ################################### */
+/* Definition of ADCx clock resources */
+#define ADCx                            ADC1
+#define ADCx_CLK_ENABLE()               __HAL_RCC_ADC_CLK_ENABLE()
+
+#define ADCx_FORCE_RESET()              __HAL_RCC_ADC_FORCE_RESET()
+#define ADCx_RELEASE_RESET()            __HAL_RCC_ADC_RELEASE_RESET()
+
+/* Definition of ADCx channels */
+#define ADCx_CHANNELa                   ADC_CHANNEL_9
+
+/* Definition of ADCx NVIC resources */
+#define ADCx_IRQn                       ADC1_IRQn
+#define ADCx_IRQHandler                 ADC1_IRQHandler
+
+/* Definition of ADCx channels pins */
+#define ADCx_CHANNELa_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
+#define ADCx_CHANNELa_GPIO_PORT         GPIOA
+#define ADCx_CHANNELa_PIN               GPIO_PIN_4
+
+/* Definition of ADCx DMA resources */
+#define ADCx_DMA_CLK_ENABLE()           do { \
+                                             LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1); \
+                                             __HAL_RCC_DMAMUX1_CLK_ENABLE(); \
+                                           }while(0)
+#define ADCx_DMA                        DMA1_Channel1
+
+#define ADCx_DMA_IRQn                   DMA1_Channel1_IRQn
+#define ADCx_DMA_IRQHandler             DMA1_Channel1_IRQHandler
+
+
+
+/* Definitions of environment analog values */
+  /* Value of analog reference voltage (Vref+), connected to analog voltage   */
+  /* supply Vdda (unit: mV).                                                  */
+  #define VDDA_APPLI                       ((uint32_t)3300)
+  
+/* Definitions of data related to this example */
+  /* Full-scale digital value with a resolution of 12 bits (voltage range     */
+  /* determined by analog voltage references Vref+ and Vref-,                 */
+  /* refer to reference manual).                                              */
+  #define DIGITAL_SCALE_12BITS             ((uint32_t) 0xFFF)
+
+  /* Init variable out of ADC expected conversion data range */
+  #define VAR_CONVERTED_DATA_INIT_VALUE    (DIGITAL_SCALE_12BITS + 1)
+
+  /* Definition of ADCx conversions data table size */
+  #define ADC_CONVERTED_DATA_BUFFER_SIZE   ((uint32_t)  64)
+
+/* Private macro -------------------------------------------------------------*/
+
+/**
+  * @brief  Macro to calculate the voltage (unit: mVolt)
+  *         corresponding to a ADC conversion data (unit: digital value).
+  * @note   ADC measurement data must correspond to a resolution of 12bits
+  *         (full scale digital value 4095). If not the case, the data must be
+  *         preliminarily rescaled to an equivalent resolution of 12 bits.
+  * @note   Analog reference voltage (Vref+) must be known from
+  *         user board environment.
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *                       (unit: digital value).
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __ADC_CALC_DATA_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__)       \
+  ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) / DIGITAL_SCALE_12BITS)
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..f107476b0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+#define HAL_ADC_MODULE_ENABLED
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..eddfc615b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Inc/stm32wbxx_it.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void TIM2_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+void EXTI0_IRQHandler(void);
+
+void ADCx_IRQHandler(void);
+void ADCx_DMA_IRQHandler(void);
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/MDK-ARM/ADC_SingleConversion_TriggerTimer_DMA.uvoptx b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/MDK-ARM/ADC_SingleConversion_TriggerTimer_DMA.uvoptx
new file mode 100644
index 000000000..ea30df02c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/MDK-ARM/ADC_SingleConversion_TriggerTimer_DMA.uvoptx
@@ -0,0 +1,533 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    ADC_SingleConversion_TriggerTimer_DMA
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
+      stm32wbxx_hal_adc.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c
+      stm32wbxx_hal_adc_ex.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+      stm32wbxx_ll_adc.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      24
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      25
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/MDK-ARM/ADC_SingleConversion_TriggerTimer_DMA.uvprojx b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/MDK-ARM/ADC_SingleConversion_TriggerTimer_DMA.uvprojx
new file mode 100644
index 000000000..0e43c572c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/MDK-ARM/ADC_SingleConversion_TriggerTimer_DMA.uvprojx
@@ -0,0 +1,556 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      ADC_SingleConversion_TriggerTimer_DMA
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          ADC_SingleConversion_TriggerTimer_DMA\
+          ADC_SingleConversion_TriggerTimer_DMA
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_adc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
+            
+            
+              stm32wbxx_hal_adc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c
+            
+            
+              stm32wbxx_ll_adc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..d02a4ec38
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/.project
new file mode 100644
index 000000000..45a3a7eac
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/.project
@@ -0,0 +1,160 @@
+
+
+	ADC_SingleConversion_TriggerTimer_DMA
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			ADC_SingleConversion_TriggerTimer_DMA.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/ADC_SingleConversion_TriggerTimer_DMA.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_adc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_adc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_adc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/main.c
new file mode 100644
index 000000000..e31e67516
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/main.c
@@ -0,0 +1,560 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/main.c
+  * @author  MCD Application Team
+  * @brief   Use ADC to convert a single channel at each trig from timer.
+  *          Conversion data are transferred by DMA into a table,
+  *          indefinitely (circular mode).
+  *          Example using the STM32WBxx ADC HAL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+TIM_HandleTypeDef htim2;
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+/* ADC handler declaration */
+ADC_HandleTypeDef    AdcHandle;
+/* Variables for ADC conversion data */
+__IO   uint16_t   aADCxConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE]; /* ADC group regular conversion data (array of data) */
+
+/* Variables for ADC conversion data computation to physical values */
+uint16_t   aADCxConvertedData_Voltage_mVolt[ADC_CONVERTED_DATA_BUFFER_SIZE];  /* Value of voltage calculated from ADC conversion data (unit: mV) (array of data) */
+
+/* Variable to report status of DMA transfer of ADC group regular conversions */
+/*  0: DMA transfer is not completed                                          */
+/*  1: DMA transfer is completed                                              */
+/*  2: DMA transfer has not yet been started yet (initial state)              */
+__IO   uint8_t ubDmaTransferStatus = 2; /* Variable set into DMA interruption callback */
+
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_TIM2_Init(void);
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+static void Configure_ADC(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  uint32_t tmp_index_adc_converted_data = 0;
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_TIM2_Init();
+  /* USER CODE BEGIN 2 */
+  for (tmp_index_adc_converted_data = 0; tmp_index_adc_converted_data < ADC_CONVERTED_DATA_BUFFER_SIZE; tmp_index_adc_converted_data++)
+  {
+    aADCxConvertedData[tmp_index_adc_converted_data] = VAR_CONVERTED_DATA_INIT_VALUE;
+  }
+  
+  /* Initialize LED on board */
+  BSP_LED_Init(LED2);
+  
+ /* Configure ADC */
+  /* Note: This function configures the ADC but does not enable it.           */
+  /*       Only ADC internal voltage regulator is enabled by function         */
+  /*       "HAL_ADC_Init()".                                                  */
+  /*       To activate ADC (ADC enable and ADC conversion start), use         */
+  /*       function "HAL_ADC_Start_xxx()".                                    */
+  /*       This is intended to optimize power consumption:                    */
+  /*       1. ADC configuration can be done once at the beginning             */
+  /*          (ADC disabled, minimal power consumption)                       */
+  /*       2. ADC enable (higher power consumption) can be done just before   */
+  /*          ADC conversions needed.                                         */
+  /*          Then, possible to perform successive ADC activation and         */
+  /*          deactivation without having to set again ADC configuration.     */
+  Configure_ADC();
+  
+  /* Run the ADC calibration in single-ended mode */
+  if (HAL_ADCEx_Calibration_Start(&AdcHandle, ADC_SINGLE_ENDED) != HAL_OK)
+  {
+    /* Calibration Error */
+    Error_Handler();
+  }
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  /*## Enable Timer ########################################################*/
+  if (HAL_TIM_Base_Start(&htim2) != HAL_OK)
+  {
+    /* Counter enable error */
+    Error_Handler();
+  }
+  
+  /*## Start ADC conversions ###############################################*/
+  /* Start ADC group regular conversion with DMA */
+  if (HAL_ADC_Start_DMA(&AdcHandle,
+                        (uint32_t *)aADCxConvertedData,
+                        ADC_CONVERTED_DATA_BUFFER_SIZE
+                       ) != HAL_OK)
+  {
+    /* ADC conversion start error */
+    Error_Handler();
+  }  
+  
+  while (1)
+  {
+    /* Note: At this step, a voltage can be supplied to ADC channel input     */
+    /*       (by connecting an external signal voltage generator to the       */
+    /*       analog input pin) to perform a ADC conversion on a determined    */
+    /*       voltage level.                                                   */
+    /*       Otherwise, ADC channel input can be let floating, in this case   */
+    /*       ADC conversion data will be undetermined.                        */
+
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    /* Note: LED state depending on DMA transfer status is set into DMA       */
+    /*       IRQ handler, refer to functions "HAL_ADC_ConvCpltCallback()"     */
+    /*       and "HAL_ADC_ConvHalfCpltCallback()".                            */
+
+    /* Note: ADC conversions data are stored into array                       */
+    /*       "aADCConvertedData"                                              */
+    /*       (for debug: see variable content into watch window).             */
+    
+    /* Note: ADC conversion data are computed to physical values              */
+    /*       into array "aADCxConvertedData_Voltage_mVolt"                    */
+    /*       using helper macro "__ADC_CALC_DATA_VOLTAGE()".                  */
+    /*       (for debug: see variable content into watch window).             */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief TIM2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM2_Init(void)
+{
+
+  /* USER CODE BEGIN TIM2_Init 0 */
+
+  /* USER CODE END TIM2_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM2_Init 1 */
+
+  /* USER CODE END TIM2_Init 1 */
+  htim2.Instance = TIM2;
+  htim2.Init.Prescaler = 1;
+  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim2.Init.Period = 39999;
+  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM2_Init 2 */
+
+  /* USER CODE END TIM2_Init 2 */
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  Configure ADC (ADC instance: ADCx) and GPIO used by ADC channels.
+  *         Configuration of GPIO:
+  *           - Pin:                    PA.04 (on this STM32 device, ADC1 channel 9 is mapped on this GPIO)
+  *           - Mode:                   analog
+  *         Configuration of ADC:
+  *         - Common to several ADC:
+  *           - Conversion clock:       Synchronous from PCLK
+  *           - Internal path:          None                         (default configuration from reset state)
+  *         - Multimode
+  *           Feature not used: all parameters let to default configuration from reset state
+  *           - Mode                    Independent                  (default configuration from reset state)
+  *           - DMA transfer:           Disabled                     (default configuration from reset state)
+  *           - Delay sampling phases   1 ADC clock cycle            (default configuration from reset state)
+  *         - ADC instance
+  *           - Resolution:             12 bits                      (default configuration from reset state)
+  *           - Data alignment:         right aligned                (default configuration from reset state)
+  *           - Low power mode:         disabled                     (default configuration from reset state)
+  *           - Offset:                 none                         (default configuration from reset state)
+  *         - Group regular
+  *           - Trigger source:         external trigger from TIM2
+  *           - Trigger edge:           rising                       (default configuration from reset state)
+  *           - Continuous mode:        single conversion            (default configuration from reset state)
+  *           - DMA transfer:           enabled, unlimited requests
+  *           - Overrun:                data overwritten
+  *           - Sequencer length:       disabled: 1 rank             (default configuration from reset state)
+  *           - Sequencer discont:      disabled: sequence done in 1 scan (default configuration from reset state)
+  *           - Sequencer rank 1:       ADCx ADCx_CHANNELa
+  *         - Group injected
+  *           Feature not used: all parameters let to default configuration from reset state
+  *           - Trigger source:         SW start                     (default configuration from reset state)
+  *           - Trigger edge:           not applicable with SW start
+  *           - Auto injection:         disabled                     (default configuration from reset state)
+  *           - Contexts queue:         disabled                     (default configuration from reset state)
+  *           - Sequencer length:       disabled: 1 rank             (default configuration from reset state)
+  *           - Sequencer discont:      disabled: sequence done in 1 scan (default configuration from reset state)
+  *           - Sequencer rank 1:       first channel available      (default configuration from reset state)
+  *         - Channel
+  *           - Sampling time:          ADCx ADCx_CHANNELa set to sampling time 247.5 ADC clock cycles (on this STM32 serie, sampling time is channel wise)
+  *           - Differential mode:      single ended                 (default configuration from reset state)
+  *         - Analog watchdog
+  *           Feature not used: all parameters let to default configuration from reset state
+  *           - AWD number:             1
+  *           - Monitored channels:     none                         (default configuration from reset state)
+  *           - Threshold high:         0x000                        (default configuration from reset state)
+  *           - Threshold low:          0xFFF                        (default configuration from reset state)
+  *         - Oversampling
+  *           Feature not used: all parameters let to default configuration from reset state
+  *           - Scope:                  none                         (default configuration from reset state)
+  *           - Discontinuous mode:     disabled                     (default configuration from reset state)
+  *           - Ratio:                  2                            (default configuration from reset state)
+  *           - Shift:                  none                         (default configuration from reset state)
+  *         - Interruptions
+  *           None: with HAL driver, ADC interruptions are set using
+  *           function "HAL_ADC_start_xxx()".
+  * @note   Using HAL driver, configuration of GPIO used by ADC channels,
+  *         NVIC and clock source at top level (RCC)
+  *         are not implemented into this function,
+  *         must be implemented into function "HAL_ADC_MspInit()".
+  * @param  None
+  * @retval None
+  */
+__STATIC_INLINE void Configure_ADC(void)
+{
+  ADC_ChannelConfTypeDef   sConfig;
+  
+  /*## Configuration of ADC ##################################################*/
+  
+  /*## Configuration of ADC hierarchical scope: ##############################*/
+  /*## common to several ADC, ADC instance, ADC group regular  ###############*/
+  
+  /* Set ADC instance of HAL ADC handle AdcHandle */
+  AdcHandle.Instance = ADCx;
+  
+  /* Configuration of HAL ADC handle init structure:                          */
+  /* parameters of scope ADC instance and ADC group regular.                  */
+  /* Note: On this STM32 serie, ADC group regular sequencer is                */
+  /*       fully configurable: sequencer length and each rank                 */
+  /*       affectation to a channel are configurable.                         */
+  AdcHandle.Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV2;
+  AdcHandle.Init.Resolution            = ADC_RESOLUTION_12B;
+  AdcHandle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+  AdcHandle.Init.ScanConvMode          = ADC_SCAN_DISABLE;              /* Sequencer disabled (ADC conversion on only 1 channel: channel set on rank 1) */
+  AdcHandle.Init.EOCSelection          = ADC_EOC_SINGLE_CONV;
+  AdcHandle.Init.LowPowerAutoWait      = DISABLE;
+  AdcHandle.Init.ContinuousConvMode    = ENABLE;                        /* Continuous mode to have maximum conversion speed (no delay between conversions) */
+  AdcHandle.Init.NbrOfConversion       = 1;                             /* Parameter discarded because sequencer is disabled */
+  AdcHandle.Init.DiscontinuousConvMode = DISABLE;                       /* Parameter discarded because sequencer is disabled */
+  AdcHandle.Init.NbrOfDiscConversion   = 1;                             /* Parameter discarded because sequencer is disabled */
+  AdcHandle.Init.ExternalTrigConv      = ADC_EXTERNALTRIG_T2_TRGO;            /*!< ADC conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+  AdcHandle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_RISING; /*!< ADC group regular conversion trigger polarity set to rising edge */
+  AdcHandle.Init.DMAContinuousRequests = ENABLE;                        /* ADC with DMA transfer: continuous requests to DMA to match with DMA configured in circular mode */
+  AdcHandle.Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN;
+  AdcHandle.Init.OversamplingMode      = DISABLE;
+
+  if (HAL_ADC_Init(&AdcHandle) != HAL_OK)
+  {
+    /* ADC initialization error */
+    Error_Handler();
+  }
+  
+  
+  /*## Configuration of ADC hierarchical scope: ##############################*/
+  /*## ADC group injected and channels mapped on group injected ##############*/
+  
+  /* Note: ADC group injected not used and not configured in this example.    */
+  /*       Refer to other ADC examples using this feature.                    */
+  /* Note: Call of the functions below are commented because they are         */
+  /*       useless in this example:                                           */
+  /*       setting corresponding to default configuration from reset state.   */
+  
+  
+  /*## Configuration of ADC hierarchical scope: ##############################*/
+  /*## channels mapped on group regular         ##############################*/
+  
+  /* Configuration of channel on ADCx regular group on sequencer rank 1 */
+  /* Note: On this STM32 serie, ADC group regular sequencer is                */
+  /*       fully configurable: sequencer length and each rank                 */
+  /*       affectation to a channel are configurable.                         */
+  /* Note: Considering IT occurring after each ADC conversion                 */
+  /*       (IT by ADC group regular end of unitary conversion),               */
+  /*       select sampling time and ADC clock with sufficient                 */
+  /*       duration to not create an overhead situation in IRQHandler.        */
+  sConfig.Channel      = ADCx_CHANNELa;               /* ADC channel selection */
+  sConfig.Rank         = ADC_REGULAR_RANK_1;          /* ADC group regular rank in which is mapped the selected ADC channel */
+  sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;  /* ADC channel sampling time */
+  sConfig.SingleDiff   = ADC_SINGLE_ENDED;            /* ADC channel differential mode */
+  sConfig.OffsetNumber = ADC_OFFSET_NONE;             /* ADC channel affected to offset number */
+  sConfig.Offset       = 0;                           /* Parameter discarded because offset correction is disabled */
+  
+  if (HAL_ADC_ConfigChannel(&AdcHandle, &sConfig) != HAL_OK)
+  {
+    /* Channel Configuration Error */
+    Error_Handler();
+  }
+  
+  
+  /*## Configuration of ADC hierarchical scope: multimode ####################*/
+  /* Note: ADC multimode is not available on this device:                     */
+  /*       only 1 ADC instance is present.                                    */
+  
+  
+  /*## Configuration of ADC transversal scope: analog watchdog ###############*/
+  
+  /* Note: ADC analog watchdog not used and not configured in this example.   */
+  /*       Refer to other ADC examples using this feature.                    */
+  
+  
+  /*## Configuration of ADC transversal scope: oversampling ##################*/
+  
+  /* Note: ADC oversampling not used and not configured in this example.      */
+  /*       Refer to other ADC examples using this feature.                    */
+  
+}
+
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT                                               */
+/******************************************************************************/
+
+
+/**
+  * @brief  Conversion complete callback in non blocking mode 
+  * @param  hadc: ADC handle
+  * @note   This example shows a simple way to report end of conversion
+  *         and get conversion result. You can add your own implementation.
+  * @retval None
+  */
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
+{
+  uint32_t tmp_index = 0;
+  
+  /* Computation of ADC conversions raw data to physical values               */
+  /* using LL ADC driver helper macro.                                        */
+  /* Management of the 2nd half of the buffer */
+  for (tmp_index = (ADC_CONVERTED_DATA_BUFFER_SIZE/2); tmp_index < ADC_CONVERTED_DATA_BUFFER_SIZE; tmp_index++)
+  {
+    aADCxConvertedData_Voltage_mVolt[tmp_index] = __ADC_CALC_DATA_VOLTAGE(VDDA_APPLI, aADCxConvertedData[tmp_index]);
+  }
+  
+  /* Update status variable of DMA transfer */
+  ubDmaTransferStatus = 1;
+  
+  /* Set LED depending on DMA transfer status */
+  /* - Turn-on if DMA transfer is completed */
+  /* - Turn-off if DMA transfer is not completed */
+  BSP_LED_On(LED2);
+}
+
+/**
+  * @brief  Conversion DMA half-transfer callback in non blocking mode 
+  * @note   This example shows a simple way to report end of conversion
+  *         and get conversion result. You can add your own implementation.
+  * @retval None
+  */
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
+{
+  uint32_t tmp_index = 0;
+  
+  /* Computation of ADC conversions raw data to physical values               */
+  /* using LL ADC driver helper macro.                                        */
+  /* Management of the 1st half of the buffer */
+  for (tmp_index = 0; tmp_index < (ADC_CONVERTED_DATA_BUFFER_SIZE/2); tmp_index++)
+  {
+    aADCxConvertedData_Voltage_mVolt[tmp_index] = __ADC_CALC_DATA_VOLTAGE(VDDA_APPLI, aADCxConvertedData[tmp_index]);
+  }
+  
+  /* Update status variable of DMA transfer */
+  ubDmaTransferStatus = 0;
+  
+  /* Set LED depending on DMA transfer status */
+  /* - Turn-on if DMA transfer is completed */
+  /* - Turn-off if DMA transfer is not completed */
+  BSP_LED_Off(LED2);
+}
+
+/**
+  * @brief  ADC error callback in non blocking mode
+  *        (ADC conversion with interruption or transfer by DMA)
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+  /* In case of ADC error, call main error handler */
+  Error_Handler();
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  while(1) 
+  {
+    /* Toggle LED2 */
+    BSP_LED_Off(LED2);
+    HAL_Delay(800);
+    BSP_LED_On(LED2);
+    HAL_Delay(10);
+    BSP_LED_Off(LED2);
+    HAL_Delay(180);
+    BSP_LED_On(LED2);
+    HAL_Delay(10);
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  Error_Handler();
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..0d2d3d126
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,238 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief TIM_Base MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+{
+  if(htim_base->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspInit 0 */
+
+  /* USER CODE END TIM2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM2_CLK_ENABLE();
+    /* TIM2 interrupt Init */
+    HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(TIM2_IRQn);
+  /* USER CODE BEGIN TIM2_MspInit 1 */
+
+  /* USER CODE END TIM2_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief TIM_Base MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
+{
+  if(htim_base->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspDeInit 0 */
+
+  /* USER CODE END TIM2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM2_CLK_DISABLE();
+
+    /* TIM2 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(TIM2_IRQn);
+  /* USER CODE BEGIN TIM2_MspDeInit 1 */
+
+  /* USER CODE END TIM2_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/**
+  * @brief ADC MSP initialization
+  *        This function configures the hardware resources used in this example:
+  *          - Enable clock of ADC peripheral
+  *          - Configure the GPIO associated to the peripheral channels
+  *          - Configure the DMA associated to the peripheral
+  *          - Configure the NVIC associated to the peripheral interruptions
+  * @param hadc: ADC handle pointer
+  * @retval None
+  */
+void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
+{
+  GPIO_InitTypeDef          GPIO_InitStruct;
+  static DMA_HandleTypeDef  DmaHandle;
+  
+  /*##-1- Enable peripherals and GPIO Clocks #################################*/
+  /* Enable clock of GPIO associated to the peripheral channels */
+  ADCx_CHANNELa_GPIO_CLK_ENABLE();
+  
+  /* Enable clock of ADCx peripheral (core clock) */
+  ADCx_CLK_ENABLE();
+  
+  /* Note: In case of usage of asynchronous clock for ADC, with ADC setting   */
+  /*       "AdcHandle.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIVx",            */
+  /*       the clock source has to be enabled at RCC top level using function */
+  /*       "HAL_RCCEx_PeriphCLKConfig()" or macro "__HAL_RCC_ADC_CONFIG()"    */
+  /*       (refer to comments in driver file header).                         */
+
+  /* Enable clock of DMA associated to the peripheral */
+  ADCx_DMA_CLK_ENABLE();
+  
+  /*##-2- Configure peripheral GPIO ##########################################*/
+  /* Configure GPIO pin of the selected ADC channel */
+  GPIO_InitStruct.Pin = ADCx_CHANNELa_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(ADCx_CHANNELa_GPIO_PORT, &GPIO_InitStruct);
+  
+  /*##-3- Configure the DMA ##################################################*/
+  /* Configure DMA parameters */
+  DmaHandle.Instance = ADCx_DMA;
+
+  DmaHandle.Init.Request             = DMA_REQUEST_ADC1;
+  DmaHandle.Init.Direction           = DMA_PERIPH_TO_MEMORY;
+  DmaHandle.Init.PeriphInc           = DMA_PINC_DISABLE;
+  DmaHandle.Init.MemInc              = DMA_MINC_ENABLE;
+  DmaHandle.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;   /* Transfer from ADC by half-word to match with ADC configuration: ADC resolution 10 or 12 bits */
+  DmaHandle.Init.MemDataAlignment    = DMA_MDATAALIGN_HALFWORD;   /* Transfer to memory by half-word to match with buffer variable type: half-word */
+  DmaHandle.Init.Mode                = DMA_CIRCULAR;              /* DMA in circular mode to match with ADC configuration: DMA continuous requests */
+  DmaHandle.Init.Priority            = DMA_PRIORITY_HIGH;
+  
+  /* Deinitialize  & Initialize the DMA for new transfer */
+  HAL_DMA_DeInit(&DmaHandle);
+  HAL_DMA_Init(&DmaHandle);
+
+  /* Associate the initialized DMA handle to the ADC handle */
+  __HAL_LINKDMA(hadc, DMA_Handle, DmaHandle);
+  
+  /*##-4- Configure the NVIC #################################################*/
+  /* NVIC configuration for ADC interrupt */
+  /* Priority: high-priority */
+  HAL_NVIC_SetPriority(ADCx_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(ADCx_IRQn);
+  
+  /* NVIC configuration for DMA interrupt (transfer completion or error) */
+  /* Priority: high-priority */
+  HAL_NVIC_SetPriority(ADCx_DMA_IRQn, 1, 0);
+  HAL_NVIC_EnableIRQ(ADCx_DMA_IRQn);
+}
+
+/**
+  * @brief ADC MSP de-initialization
+  *        This function frees the hardware resources used in this example:
+  *          - Disable clock of ADC peripheral
+  *          - Revert GPIO associated to the peripheral channels to their default state
+  *          - Revert DMA associated to the peripheral to its default state
+  *          - Revert NVIC associated to the peripheral interruptions to its default state
+  * @param hadc: ADC handle pointer
+  * @retval None
+  */
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
+{
+  /*##-1- Reset peripherals ##################################################*/
+  ADCx_FORCE_RESET();
+  ADCx_RELEASE_RESET();
+
+  /*##-2- Disable peripherals and GPIO Clocks ################################*/
+  /* De-initialize GPIO pin of the selected ADC channel */
+  HAL_GPIO_DeInit(ADCx_CHANNELa_GPIO_PORT, ADCx_CHANNELa_PIN);
+
+  /*##-3- Disable the DMA ####################################################*/
+  /* De-Initialize the DMA associated to the peripheral */
+  if(hadc->DMA_Handle != NULL)
+  {
+    HAL_DMA_DeInit(hadc->DMA_Handle);
+  }
+
+  /*##-4- Disable the NVIC ###################################################*/
+  /* Disable the NVIC configuration for ADC interrupt */
+  HAL_NVIC_DisableIRQ(ADCx_IRQn);
+  
+  /* Disable the NVIC configuration for DMA interrupt */
+  HAL_NVIC_DisableIRQ(ADCx_DMA_IRQn);
+  
+}
+
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..a8972af32
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/stm32wbxx_it.c
@@ -0,0 +1,156 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern TIM_HandleTypeDef htim2;
+/* USER CODE BEGIN EV */
+extern ADC_HandleTypeDef    AdcHandle;
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles TIM2 global interrupt.
+  */
+void TIM2_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM2_IRQn 0 */
+
+  /* USER CODE END TIM2_IRQn 0 */
+  HAL_TIM_IRQHandler(&htim2);
+  /* USER CODE BEGIN TIM2_IRQn 1 */
+
+  /* USER CODE END TIM2_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles ADC interrupt request.
+  * @param  None
+  * @retval None
+  */
+void ADCx_IRQHandler(void)
+{
+  HAL_ADC_IRQHandler(&AdcHandle);
+}
+
+/**
+  * @brief  This function handles DMA interrupt request.
+  * @param  None
+  * @retval None
+  */
+void ADCx_DMA_IRQHandler(void)
+{
+  HAL_DMA_IRQHandler(AdcHandle.DMA_Handle);
+}
+
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/readme.txt b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/readme.txt
new file mode 100644
index 000000000..05ec3b7c7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/readme.txt
@@ -0,0 +1,103 @@
+/* USER CODE BEGIN Header */
+/**
+  @page ADC_SingleConversion_TriggerTimer_DMA ADC example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the ADC_SingleConversion_TriggerTimer_DMA example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+Use ADC to convert a single channel at each trig from timer, 
+conversion data are transferred by DMA into an array, indefinitely (circular mode).
+
+Example configuration:
+ADC is configured to convert a single channel, in single conversion mode,
+from HW trigger: timer peripheral.
+DMA is configured to transfer conversion data in an array, in circular mode.
+A timer is configured in time base and to generate TRGO events.
+
+Example execution:
+From the start, the ADC converts the selected channel at each trig from timer.
+DMA transfers conversion data to the array, DMA transfer complete interruption occurs.
+Results array is updated indefinitely (DMA in circular mode).
+LED2 is turned on when the DMA transfer is completed (results array full)
+and turned off at next DMA half-transfer (result array first half updated).
+
+For debug: variables to monitor with debugger watch window:
+ - "aADCxConvertedData": ADC group regular conversion data (array of data)
+ - "aADCxConvertedData_Voltage_mVolt": ADC conversion data computation to physical values (array of data)
+
+Connection needed:
+None.
+Note: Optionally, a voltage can be supplied to the analog input pin (cf pin below),
+      between 0V and Vdda=3.3V, to perform a ADC conversion on a determined
+      voltage level.
+      Otherwise, this pin can be let floating (in this case ADC conversion data
+      will be undetermined).
+
+Other peripherals used:
+  1 GPIO for LED
+  1 GPIO for analog input: PA4 ()
+  DMA
+  Timer
+
+Board settings:
+ - ADC is configured to convert ADC_CHANNEL_9 ().
+ - The voltage input on ADC channel must be provided by an external source connected to .
+
+
+To observe voltage level applied on ADC channel through GPIO, connect a voltmeter on
+pin PA4 ().
+
+NUCLEO-WB35CE board LED is be used to monitor the program execution status:
+ - Normal operation: LED2 is turned-on/off in function of ADC conversion
+   result.
+    - Toggling: "On" upon conversion completion (full DMA buffer filled)
+                "Off" upon half conversion completion (half DMA buffer filled)
+ - Error: In case of error, LED2 is toggling twice at a frequency of 1Hz.
+
+@par Keywords
+
+Analog, ADC, Analog to Digital, Single conversion, Timer trigger, DMA, circular mode
+
+@par Directory contents 
+
+  - ADC/ADC_SingleConversion_TriggerTimer_DMA/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - ADC/ADC_SingleConversion_TriggerTimer_DMA/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - ADC/ADC_SingleConversion_TriggerTimer_DMA/Inc/main.h                        Header for main.c module  
+  - ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/stm32wbxx_it.c          Interrupt handlers
+  - ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/main.c                        Main program
+  - ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/stm32wbxx_hal_msp.c     HAL MSP module
+  - ADC/ADC_SingleConversion_TriggerTimer_DMA/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35xx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/.extSettings b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/BSP_Example.ioc b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/BSP_Example.ioc
new file mode 100644
index 000000000..59e68f31d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/BSP_Example.ioc
@@ -0,0 +1,106 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+KeepUserPlacement=false
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x400
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=false
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=BSP_Example.ioc
+ProjectManager.ProjectName=BSP_Example
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FLatency=FLASH_LATENCY_3
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FLatency,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/BSP_Example.ewd b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/BSP_Example.ewd
new file mode 100644
index 000000000..f75281ed6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/BSP_Example.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		BSP_Example
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/BSP_Example.ewp b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/BSP_Example.ewp
new file mode 100644
index 000000000..f3dbd2356
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/BSP_Example.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    BSP_Example
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/Project.eww
new file mode 100644
index 000000000..bb27a43d3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\BSP_Example.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..52725db75
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/stm32wb35xx_sram_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/stm32wb35xx_sram_cm4.icf
new file mode 100644
index 000000000..c654ec05b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/EWARM/stm32wb35xx_sram_cm4.icf
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20003FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20004000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20008000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x2000FFFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Inc/main.h
new file mode 100644
index 000000000..a221fe6a8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Inc/main.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    BSP/BSP/Inc/main.h 
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..19d12a61f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..7a25428d8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Inc/stm32wbxx_it.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    BSP/BSP/Inc/stm32wbxx_it.h 
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void EXTI0_IRQHandler(void);
+void EXTI4_IRQHandler(void);
+void EXTI9_5_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/MDK-ARM/BSP_Example.uvoptx b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/MDK-ARM/BSP_Example.uvoptx
new file mode 100644
index 000000000..a73a025bb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/MDK-ARM/BSP_Example.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    BSP_Example
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      2
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      5
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      5
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      5
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      5
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      5
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      5
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      5
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      5
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      5
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      5
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/MDK-ARM/BSP_Example.uvprojx b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/MDK-ARM/BSP_Example.uvprojx
new file mode 100644
index 000000000..62731dc08
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/MDK-ARM/BSP_Example.uvprojx
@@ -0,0 +1,541 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      BSP_Example
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          BSP_Example\
+          BSP_Example
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..f7a2eea7b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x400
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..903abe152
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/.project
new file mode 100644
index 000000000..97c0ede78
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	BSP_Example
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			BSP_Example.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/BSP_Example.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..88456398d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x400 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Src/main.c
new file mode 100644
index 000000000..0ebc11e55
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Src/main.c
@@ -0,0 +1,238 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    BSP/BSP/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to use the bsp API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+static uint32_t delay = 250;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* Initialize LEDs */
+  BSP_LED_Init(LED1);  
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+  /* Initialize the button in interrupt mode */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+  BSP_PB_Init(BUTTON_SW2, BUTTON_MODE_EXTI);
+  BSP_PB_Init(BUTTON_SW3, BUTTON_MODE_EXTI);
+  /* From there, pressing the button will change the frequency of the toggling of the LEDs */
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    BSP_LED_Toggle(LED1);
+    HAL_Delay(delay);
+
+    BSP_LED_Toggle(LED2);
+    HAL_Delay(delay);
+
+    BSP_LED_Toggle(LED3);
+    HAL_Delay(delay);
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief EXTI line detection callback.
+  * @param GPIO_Pin: Specifies the pins connected EXTI line
+  * @retval None
+  */
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  switch(GPIO_Pin) 
+  {
+    case BUTTON_SW1_PIN:
+      /* Change the period to 100 ms */
+      delay = 100;
+      break;
+    case BUTTON_SW2_PIN:
+      /* Change the period to 500 ms */
+      delay = 500;
+      break;
+    case BUTTON_SW3_PIN:
+      /* Change the period to 1000 ms */
+      delay = 1000;
+      break;
+    default:
+      break;
+  }
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  while(1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..88e676a14
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32wbxx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..91927af49
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Src/stm32wbxx_it.c
@@ -0,0 +1,231 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    BSP/BSP/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles External External line 4 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+/**
+  * @brief  This function handles External External line 0 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI4_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW2_PIN);
+}
+/**
+  * @brief  This function handles External External line 1 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI9_5_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW3_PIN);
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/readme.txt b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/readme.txt
new file mode 100644
index 000000000..b2f5b65fe
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/BSP/BSP_Example/readme.txt
@@ -0,0 +1,69 @@
+/**
+  @page BSP  Example on how to use the BSP drivers
+  
+  @verbatim
+  ******************************************************************************
+  * @file    BSP/BSP_Example/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the BSP example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+This example describes how to use the bsp API. 
+
+The 3 LEDs toggle one after the other in a forever loop. This shows the usage of
+BSP_LED_Toggle, BSP_LED_On and BSP_LED_Off.
+
+When the buttons SW1, SW2 or SW3 are pressed, the toggle delay is changed.
+  - SW1 set the delay to 100ms.
+  - SW2 set the delay to 500ms.
+  - SW3 set the delay to 1000ms.
+
+LED3 demonstrate BSP_LED_On and BSP_LED_Off in the same loop and so the toggle frequency is different from LED1 and LED2
+which are demonstrating BSP_LED_Toggle.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in HAL time base ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the HAL time base interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the HAL time base interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the HAL time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Directory contents 
+
+  - BSP/BSP/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - BSP/BSP/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - BSP/BSP/Inc/main.h                  Header for main.c module  
+  - BSP/BSP/Src/stm32wbxx_it.c          Interrupt handlers
+  - BSP/BSP/Src/main.c                  Main program
+  - BSP/BSP/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35xx devices.
+    
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/.extSettings b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/COMP_CompareGpioVsVrefInt_IT.ioc b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/COMP_CompareGpioVsVrefInt_IT.ioc
new file mode 100644
index 000000000..bd01e70bd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/COMP_CompareGpioVsVrefInt_IT.ioc
@@ -0,0 +1,120 @@
+#MicroXplorer Configuration settings - do not modify
+COMP1.BlankingSrce=COMP_BLANKINGSRC_NONE
+COMP1.Hysteresis=COMP_HYSTERESIS_LOW
+COMP1.IPParameters=Mode,TriggerMode,Hysteresis,BlankingSrce,OutputPol
+COMP1.Mode=COMP_POWERMODE_MEDIUMSPEED
+COMP1.OutputPol=COMP_OUTPUTPOL_NONINVERTED
+COMP1.TriggerMode=COMP_TRIGGERMODE_IT_RISING_FALLING
+File.Version=6
+KeepUserPlacement=false
+Mcu.Family=STM32WB
+Mcu.IP0=COMP1
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA1
+Mcu.Pin1=VP_COMP1_VS_VREFINT
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.COMP_IRQn=true\:3\:0\:true\:false\:true\:true\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+PA1.Mode=INP
+PA1.Signal=COMP1_INP
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=true
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=false
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=COMP_CompareGpioVsVrefInt_IT.ioc
+ProjectManager.ProjectName=COMP_CompareGpioVsVrefInt_IT
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_COMP1_Init-COMP1-false-HAL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FLatency=FLASH_LATENCY_3
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FLatency,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_COMP1_VS_VREFINT.Mode=VREFINT
+VP_COMP1_VS_VREFINT.Signal=COMP1_VS_VREFINT
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/COMP_CompareGpioVsVrefInt_IT.ewd b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/COMP_CompareGpioVsVrefInt_IT.ewd
new file mode 100644
index 000000000..6e01bcdd6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/COMP_CompareGpioVsVrefInt_IT.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		COMP_CompareGpioVsVrefInt_IT
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/COMP_CompareGpioVsVrefInt_IT.ewp b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/COMP_CompareGpioVsVrefInt_IT.ewp
new file mode 100644
index 000000000..8d7f28216
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/COMP_CompareGpioVsVrefInt_IT.ewp
@@ -0,0 +1,1125 @@
+
+
+  3
+  
+    COMP_CompareGpioVsVrefInt_IT
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        30
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$\startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$\..\Src\main.c
+      
+      
+        $PROJ_DIR$\..\Src\stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$\..\Src\stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$\..\readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$\..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE\nucleo_wb35ce.c
+        
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$\..\Src\system_stm32wbxx.c
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_comp.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim_ex.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/Project.eww
new file mode 100644
index 000000000..ac2b944fa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\COMP_CompareGpioVsVrefInt_IT.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/stm32wb35xx_sram_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/stm32wb35xx_sram_cm4.icf
new file mode 100644
index 000000000..6426355fb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/EWARM/stm32wb35xx_sram_cm4.icf
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20003FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20004000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20008000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x2000FFFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Inc/main.h
new file mode 100644
index 000000000..bc1cc6c43
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    COMP/COMP_CompareGpioVsVrefInt_IT/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..89749bd9c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+#define HAL_COMP_MODULE_ENABLED
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..194649561
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    COMP/COMP_CompareGpioVsVrefInt_IT/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void COMP_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/MDK-ARM/COMP_CompareGpioVsVrefInt_IT.uvoptx b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/MDK-ARM/COMP_CompareGpioVsVrefInt_IT.uvoptx
new file mode 100644
index 000000000..e461d33ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/MDK-ARM/COMP_CompareGpioVsVrefInt_IT.uvoptx
@@ -0,0 +1,509 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    COMP_CompareGpioVsVrefInt_IT
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U001D00263137510133333639 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      2
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_comp.c
+      stm32wbxx_hal_comp.c
+      0
+      0
+    
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      5
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      5
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      5
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      5
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      5
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      5
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      5
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      5
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      5
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      5
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      5
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/MDK-ARM/COMP_CompareGpioVsVrefInt_IT.uvprojx b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/MDK-ARM/COMP_CompareGpioVsVrefInt_IT.uvprojx
new file mode 100644
index 000000000..a726de9f9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/MDK-ARM/COMP_CompareGpioVsVrefInt_IT.uvprojx
@@ -0,0 +1,547 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      COMP_CompareGpioVsVrefInt_IT
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          COMP_CompareGpioVsVrefInt_IT\
+          COMP_CompareGpioVsVrefInt_IT
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_comp.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_comp.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..335e9071a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/.project
new file mode 100644
index 000000000..4110151d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/.project
@@ -0,0 +1,150 @@
+
+
+	COMP_CompareGpioVsVrefInt_IT
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			COMP_CompareGpioVsVrefInt_IT.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/COMP_CompareGpioVsVrefInt_IT.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_comp.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_comp.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..eea98ff9c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb35xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB35xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..4ec95844d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,159 @@
+/**
+ ******************************************************************************
+ * @file      syscalls.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..4665417ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,58 @@
+/**
+ ******************************************************************************
+ * @file      sysmem.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System Memory calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Src/main.c
new file mode 100644
index 000000000..87a84f200
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Src/main.c
@@ -0,0 +1,346 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    COMP/COMP_CompareGpioVsVrefInt_IT/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example provides a short description of how to use the COMP 
+  *          peripheral Interrupt.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+COMP_HandleTypeDef hcomp1;
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_COMP1_Init(void);
+/* USER CODE BEGIN PFP */
+static void StopSequence_Config(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_COMP1_Init();
+  /* USER CODE BEGIN 2 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+
+  /* Start COMP1 */
+  if(HAL_COMP_Start(&hcomp1) != HAL_OK)
+  {
+    /* Initialization Error */
+    Error_Handler(); 
+  }
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    /* Insert 5 second delay */
+    HAL_Delay(5000);
+
+    /* LED2 Off */
+    BSP_LED_Off(LED2);
+	
+    /* Enter STOP mode */
+    StopSequence_Config();
+    /* ... STOP mode ... */
+  
+    /* at that point, MCU has been awoken */
+
+    /* Re-configure the system clock */
+    SystemClock_Config();
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief COMP1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_COMP1_Init(void)
+{
+
+  /* USER CODE BEGIN COMP1_Init 0 */
+
+  /* USER CODE END COMP1_Init 0 */
+
+  /* USER CODE BEGIN COMP1_Init 1 */
+
+  /* USER CODE END COMP1_Init 1 */
+  hcomp1.Instance = COMP1;
+  hcomp1.Init.InputMinus = COMP_INPUT_MINUS_VREFINT;
+  hcomp1.Init.InputPlus = COMP_INPUT_PLUS_IO3;
+  hcomp1.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED;
+  hcomp1.Init.Hysteresis = COMP_HYSTERESIS_LOW;
+  hcomp1.Init.BlankingSrce = COMP_BLANKINGSRC_NONE;
+  hcomp1.Init.Mode = COMP_POWERMODE_MEDIUMSPEED;
+  hcomp1.Init.WindowMode = COMP_WINDOWMODE_DISABLE;
+  hcomp1.Init.TriggerMode = COMP_TRIGGERMODE_IT_RISING_FALLING;
+  if (HAL_COMP_Init(&hcomp1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN COMP1_Init 2 */
+
+  /* USER CODE END COMP1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+
+  /*Configure GPIO pins : PC14 PC15 */
+  GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PH3 */
+  GPIO_InitStruct.Pin = GPIO_PIN_3;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PB8 PB9 PB2 PB0 
+                           PB1 PB3 PB4 PB5 
+                           PB6 PB7 */
+  GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_2|GPIO_PIN_0 
+                          |GPIO_PIN_1|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5 
+                          |GPIO_PIN_6|GPIO_PIN_7;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PA0 PA2 PA3 PA4 
+                           PA5 PA6 PA7 PA8 
+                           PA9 PA10 PA11 PA12 
+                           PA13 PA14 PA15 */
+  GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4 
+                          |GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8 
+                          |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12 
+                          |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PE4 */
+  GPIO_InitStruct.Pin = GPIO_PIN_4;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Prepare the system to enter STOP mode.
+  * @param  None
+  * @retval None
+  */
+
+static void StopSequence_Config(void)
+{
+  /* Request to enter STOP mode with regulator in low power */
+  HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+}
+/**
+  * @brief  Comparator interrupt callback.
+  * @param  hcomp: COMP handle
+  * @retval None
+  */
+void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
+{
+  /* Toggle LED2 */
+  BSP_LED_Toggle(LED2);
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  while(1) 
+  {
+    /* Toggle LED2 */
+    BSP_LED_Toggle(LED2);
+	
+    /* Add a delay */
+    HAL_Delay(500);
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  Error_Handler();
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..7ad3f0b75
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,143 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    COMP/COMP_CompareGpioVsVrefInt_IT/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief COMP MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hcomp: COMP handle pointer
+* @retval None
+*/
+void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hcomp->Instance==COMP1)
+  {
+  /* USER CODE BEGIN COMP1_MspInit 0 */
+
+  /* USER CODE END COMP1_MspInit 0 */
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**COMP1 GPIO Configuration    
+    PA1     ------> COMP1_INP 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_1;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* COMP1 interrupt Init */
+    HAL_NVIC_SetPriority(COMP_IRQn, 3, 0);
+    HAL_NVIC_EnableIRQ(COMP_IRQn);
+  /* USER CODE BEGIN COMP1_MspInit 1 */
+
+  /* USER CODE END COMP1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief COMP MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hcomp: COMP handle pointer
+* @retval None
+*/
+void HAL_COMP_MspDeInit(COMP_HandleTypeDef* hcomp)
+{
+  if(hcomp->Instance==COMP1)
+  {
+  /* USER CODE BEGIN COMP1_MspDeInit 0 */
+
+  /* USER CODE END COMP1_MspDeInit 0 */
+  
+    /**COMP1 GPIO Configuration    
+    PA1     ------> COMP1_INP 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1);
+
+    /* COMP1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(COMP_IRQn);
+  /* USER CODE BEGIN COMP1_MspDeInit 1 */
+
+  /* USER CODE END COMP1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..479b9a02a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Src/stm32wbxx_it.c
@@ -0,0 +1,208 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    COMP/COMP_CompareGpioVsVrefInt_IT/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern COMP_HandleTypeDef hcomp1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles COMP1 and COMP2 interrupts through EXTI lines 20 and 21.
+  */
+void COMP_IRQHandler(void)
+{
+  /* USER CODE BEGIN COMP_IRQn 0 */
+
+  /* USER CODE END COMP_IRQn 0 */
+  HAL_COMP_IRQHandler(&hcomp1);
+  /* USER CODE BEGIN COMP_IRQn 1 */
+
+  /* USER CODE END COMP_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/readme.txt b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/readme.txt
new file mode 100644
index 000000000..51266e3e8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/COMP/COMP_CompareGpioVsVrefInt_IT/readme.txt
@@ -0,0 +1,87 @@
+/**
+  @page COMP_CompareGpioVsVrefInt_IT COMP example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples/COMP/COMP_CompareGpioVsVrefInt_IT/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the COMP_CompareGpioVsVrefInt_IT Example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to configure the COMP peripheral to compare the external
+voltage applied on a specific pin with the Internal Voltage Reference. 
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+
+The SystemClock_Config() function is used to configure the system clock for STM32WB35CEUx  Devices
+
+When the comparator input crosses (either rising or falling edges) the internal 
+reference voltage VREFINT (1.22V), the comparator generates an interrupt
+and exit from STOP mode.
+
+The System enters STOP mode 5 seconds after the comparator is started and 
+after any system wake-up triggered by the comparator interrupt.
+
+In this example, the comparator input is connected on the pin PA1 (Arduino connector CN8 pin A2, Morpho connector CN7 pin 32).
+The user shall apply a voltage on and each time the comparator input crosses VREFINT, MCU is awake,
+system clock is reconfigured and LED2 is ON.
+
+If LED3 is toggling continuously without any voltage update, it indicates that the system 
+generated an error.
+
+@note Care must be taken when using HAL_Delay(), this function provides 
+      accurate delay (in milliseconds) based on variable incremented in SysTick ISR. 
+      This implies that if HAL_Delay() is called from a peripheral ISR process, then 
+      the SysTick interrupt must have higher priority (numerically lower) than the 
+      peripheral interrupt. Otherwise the caller ISR process will be blocked. 
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application need to ensure that the SysTick time base is always set 
+      to 1 millisecond to have correct HAL operation.
+@par Keywords
+
+comparator, stop mode, voltage compare, wakeup trigger, comparator interrupt.
+
+@par Directory contents 
+
+  - COMP/COMP_CompareGpioVsVrefInt_IT/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - COMP/COMP_CompareGpioVsVrefInt_IT/Inc/stm32wbxx_it.h          COMP interrupt handlers header file
+  - COMP/COMP_CompareGpioVsVrefInt_IT/Inc/main.h                  Header for main.c module
+  - COMP/COMP_CompareGpioVsVrefInt_IT/Src/stm32wbxx_it.c          COMP interrupt handlers
+  - COMP/COMP_CompareGpioVsVrefInt_IT/Src/main.c                  Main program
+  - COMP/COMP_CompareGpioVsVrefInt_IT/Src/stm32wbxx_hal_msp.c     HAL MSP file 
+  - COMP/COMP_CompareGpioVsVrefInt_IT/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment 
+
+  - This example runs on STM32WB35xx devices.
+
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+  - Apply an external variable voltage on PA1 (Arduino connector CN8 pin A2, Morpho connector CN7 pin 32) with average voltage 1.22V.
+    
+    
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
\ No newline at end of file
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/.extSettings b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/CORTEXM_SysTick.ioc b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/CORTEXM_SysTick.ioc
new file mode 100644
index 000000000..e5c2620ce
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/CORTEXM_SysTick.ioc
@@ -0,0 +1,106 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=CORTEXM_SysTick.ioc
+ProjectManager.ProjectName=CORTEXM_SysTick
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/CORTEXM_SysTick.ewd b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/CORTEXM_SysTick.ewd
new file mode 100644
index 000000000..ca2b5c97d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/CORTEXM_SysTick.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		CORTEXM_SysTick
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/CORTEXM_SysTick.ewp b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/CORTEXM_SysTick.ewp
new file mode 100644
index 000000000..d0dc7a8e9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/CORTEXM_SysTick.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    CORTEXM_SysTick
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/Project.eww
new file mode 100644
index 000000000..3257644f3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\CORTEXM_SysTick.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Inc/main.h
new file mode 100644
index 000000000..5d341e967
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Cortex/CORTEXM_SysTick/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..19d12a61f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..7f59022c1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Inc/stm32wbxx_it.h
@@ -0,0 +1,66 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Cortex/CORTEXM_SysTick/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/MDK-ARM/CORTEXM_SysTick.uvoptx b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/MDK-ARM/CORTEXM_SysTick.uvoptx
new file mode 100644
index 000000000..f7b755a65
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/MDK-ARM/CORTEXM_SysTick.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    CORTEXM_SysTick
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/MDK-ARM/CORTEXM_SysTick.uvprojx b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/MDK-ARM/CORTEXM_SysTick.uvprojx
new file mode 100644
index 000000000..ced09b67c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/MDK-ARM/CORTEXM_SysTick.uvprojx
@@ -0,0 +1,541 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      CORTEXM_SysTick
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          CORTEXM_SysTick\
+          CORTEXM_SysTick
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..9e20e6b29
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/.project
new file mode 100644
index 000000000..df1a79939
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	CORTEXM_SysTick
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			CORTEXM_SysTick.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/CORTEXM_SysTick.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Src/main.c
new file mode 100644
index 000000000..a7179dfd9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Src/main.c
@@ -0,0 +1,242 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Cortex/CORTEXM_SysTick/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example shows how to configure the SysTick.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+  /* Initialize LEDs */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED1);
+  BSP_LED_Init(LED3);
+
+  /* Turn on LED2 and LED3 */
+  BSP_LED_On(LED2);
+  BSP_LED_On(LED3);
+
+  /* SysTick Timer is configured by default to generate an interrupt each 1 msec.
+     ---------------------------------------------------------------------------
+    1. The configuration is done using HAL_SYSTICK_Config() located in HAL_Init().
+
+    2. The HAL_SYSTICK_Config() function configure:
+       - The SysTick Reload register with value passed as function parameter.
+       - Configure the SysTick IRQ priority to the lowest value.
+       - Reset the SysTick Counter register.
+       - Configure the SysTick Counter clock source to be Core Clock Source (HCLK).
+       - Enable the SysTick Interrupt.
+       - Start the SysTick Counter.
+
+    3. The SysTick time base 1 msec is computed using the following formula:
+
+         Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
+
+       - Reload Value is the parameter to be passed for SysTick_Config() function
+       - Reload Value should not exceed 0xFFFFFF
+
+    @note: Caution, the SysTick time base 1 msec must not be changed due to use
+           of these time base by HAL driver.
+  */
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    /* Toggle LED1 */
+    BSP_LED_Toggle(LED1);
+
+    /* Insert 50 ms delay */
+    HAL_Delay(50);
+
+    /* Toggle LED2 and LED3 */
+    BSP_LED_Toggle(LED2);
+    BSP_LED_Toggle(LED3);
+
+    /* Insert 100 ms delay */
+    HAL_Delay(100);
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  while(1) 
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* Infinite loop */
+  while(1) 
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..8efc7d79c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,82 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Cortex/CORTEXM_SysTick/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   This file provides code for the MSP Initialization 
+  *          and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..a3c232df9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Src/stm32wbxx_it.c
@@ -0,0 +1,149 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Cortex/CORTEXM_SysTick/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/readme.txt b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/readme.txt
new file mode 100644
index 000000000..0b0db6597
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CORTEX/CORTEXM_SysTick/readme.txt
@@ -0,0 +1,66 @@
+    /**
+  @page CORTEXM_SysTick CORTEXM SysTick example
+
+  @verbatim
+  ******************************************************************************
+  * @file    CORTEX/CORTEXM_SysTick/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the CortexM SysTick example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+  
+How to use the default SysTick configuration with a 1 ms timebase to toggle LEDs.
+
+  A "HAL_Delay" function is implemented based on the SysTick end-of-count event.
+  Three LEDs are toggled with a timing defined by the HAL_Delay function.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate
+      delay (in milliseconds) based on variable incremented in SysTick ISR. This
+      implies that if HAL_Delay() is called from a peripheral ISR process, then 
+      the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application need to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+System, Cortex, Time base, Systick, HCLK 
+
+@par Directory contents 
+
+  - CORTEX/CORTEXM_SysTick/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - CORTEX/CORTEXM_SysTick/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - CORTEX/CORTEXM_SysTick/Inc/main.h                  Header for main.c module
+  - CORTEX/CORTEXM_SysTick/Src/stm32wbxx_it.c          Interrupt handlers
+  - CORTEX/CORTEXM_SysTick/Src//stm32wbxx_hal_msp.c     HAL MSP file
+  - CORTEX/CORTEXM_SysTick/Src/main.c                  Main program
+  - CORTEX/CORTEXM_SysTick/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+@par Hardware and Software environment 
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+@par How to use it ? 
+In order to make the program work, you must do the following :
+- Open your preferred toolchain 
+- Rebuild all files and load your image into target memory
+- Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/.extSettings b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/CRC_Example.ioc b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/CRC_Example.ioc
new file mode 100644
index 000000000..7b395cdc2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/CRC_Example.ioc
@@ -0,0 +1,116 @@
+#MicroXplorer Configuration settings - do not modify
+CRC.DefaultInitValueUse=DEFAULT_INIT_VALUE_ENABLE
+CRC.DefaultPolynomialUse=DEFAULT_POLYNOMIAL_ENABLE
+CRC.IPParameters=DefaultPolynomialUse,DefaultInitValueUse,InputDataInversionMode,OutputDataInversionMode,InputDataFormat
+CRC.InputDataFormat=CRC_INPUTDATA_FORMAT_WORDS
+CRC.InputDataInversionMode=CRC_INPUTDATA_INVERSION_NONE
+CRC.OutputDataInversionMode=CRC_OUTPUTDATA_INVERSION_DISABLE
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=CRC
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_CRC_VS_CRC
+Mcu.Pin1=VP_SYS_VS_Systick
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=CRC_Example.ioc
+ProjectManager.ProjectName=CRC_Example
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_CRC_VS_CRC.Mode=CRC_Activate
+VP_CRC_VS_CRC.Signal=CRC_VS_CRC
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/CRC_Example.ewd b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/CRC_Example.ewd
new file mode 100644
index 000000000..0bd478e4b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/CRC_Example.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		CRC_Example
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/CRC_Example.ewp b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/CRC_Example.ewp
new file mode 100644
index 000000000..a2cbb4b15
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/CRC_Example.ewp
@@ -0,0 +1,1125 @@
+
+
+  3
+  
+    CRC_Example
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/Project.eww
new file mode 100644
index 000000000..d699b2b26
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\CRC_Example.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Inc/main.h
new file mode 100644
index 000000000..9bf26dd24
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    CRC/CRC_Example/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..f8e06ce64
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+#define HAL_CRC_MODULE_ENABLED
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..ecb45ac56
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Inc/stm32wbxx_it.h
@@ -0,0 +1,64 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    CRC/CRC_Example/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/MDK-ARM/CRC_Example.uvoptx b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/MDK-ARM/CRC_Example.uvoptx
new file mode 100644
index 000000000..ff58ec6c1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/MDK-ARM/CRC_Example.uvoptx
@@ -0,0 +1,521 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    CRC_Example
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc.c
+      stm32wbxx_hal_crc.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc_ex.c
+      stm32wbxx_hal_crc_ex.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      24
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/MDK-ARM/CRC_Example.uvprojx b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/MDK-ARM/CRC_Example.uvprojx
new file mode 100644
index 000000000..3c6cebb65
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/MDK-ARM/CRC_Example.uvprojx
@@ -0,0 +1,551 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      CRC_Example
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          CRC_Example\
+          CRC_Example
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_crc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc.c
+            
+            
+              stm32wbxx_hal_crc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc_ex.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..27cad0d6b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/.project
new file mode 100644
index 000000000..9a6c38216
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/.project
@@ -0,0 +1,155 @@
+
+
+	CRC_Example
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			CRC_Example.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/CRC_Example.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_crc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_crc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Src/main.c
new file mode 100644
index 000000000..dc40ed46d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Src/main.c
@@ -0,0 +1,279 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    CRC/CRC_Example/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use the STM32WBxx CRC HAL API
+  *          to get a CRC code of a given buffer of data words (32-bit),
+  *          based on a fixed generator polynomial (0x4C11DB7).
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define BUFFER_SIZE    114
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+CRC_HandleTypeDef hcrc;
+
+/* USER CODE BEGIN PV */
+
+/* Used for storing CRC Value */
+__IO uint32_t uwCRCValue = 0;
+
+static const uint32_t aDataBuffer[BUFFER_SIZE] =
+{
+  0x00001021, 0x20423063, 0x408450a5, 0x60c670e7, 0x9129a14a, 0xb16bc18c,
+  0xd1ade1ce, 0xf1ef1231, 0x32732252, 0x52b54294, 0x72f762d6, 0x93398318,
+  0xa35ad3bd, 0xc39cf3ff, 0xe3de2462, 0x34430420, 0x64e674c7, 0x44a45485,
+  0xa56ab54b, 0x85289509, 0xf5cfc5ac, 0xd58d3653, 0x26721611, 0x063076d7,
+  0x569546b4, 0xb75ba77a, 0x97198738, 0xf7dfe7fe, 0xc7bc48c4, 0x58e56886,
+  0x78a70840, 0x18612802, 0xc9ccd9ed, 0xe98ef9af, 0x89489969, 0xa90ab92b,
+  0x4ad47ab7, 0x6a961a71, 0x0a503a33, 0x2a12dbfd, 0xfbbfeb9e, 0x9b798b58,
+  0xbb3bab1a, 0x6ca67c87, 0x5cc52c22, 0x3c030c60, 0x1c41edae, 0xfd8fcdec,
+  0xad2abd0b, 0x8d689d49, 0x7e976eb6, 0x5ed54ef4, 0x2e321e51, 0x0e70ff9f,
+  0xefbedfdd, 0xcffcbf1b, 0x9f598f78, 0x918881a9, 0xb1caa1eb, 0xd10cc12d,
+  0xe16f1080, 0x00a130c2, 0x20e35004, 0x40257046, 0x83b99398, 0xa3fbb3da,
+  0xc33dd31c, 0xe37ff35e, 0x129022f3, 0x32d24235, 0x52146277, 0x7256b5ea,
+  0x95a88589, 0xf56ee54f, 0xd52cc50d, 0x34e224c3, 0x04817466, 0x64475424,
+  0x4405a7db, 0xb7fa8799, 0xe75ff77e, 0xc71dd73c, 0x26d336f2, 0x069116b0,
+  0x76764615, 0x5634d94c, 0xc96df90e, 0xe92f99c8, 0xb98aa9ab, 0x58444865,
+  0x78066827, 0x18c008e1, 0x28a3cb7d, 0xdb5ceb3f, 0xfb1e8bf9, 0x9bd8abbb,
+  0x4a755a54, 0x6a377a16, 0x0af11ad0, 0x2ab33a92, 0xed0fdd6c, 0xcd4dbdaa,
+  0xad8b9de8, 0x8dc97c26, 0x5c644c45, 0x3ca22c83, 0x1ce00cc1, 0xef1fff3e,
+  0xdf7caf9b, 0xbfba8fd9, 0x9ff86e17, 0x7e364e55, 0x2e933eb2, 0x0ed11ef0
+};
+
+/* Expected CRC Value */
+uint32_t uwExpectedCRCValue = 0x379E9F06;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_CRC_Init(void);
+/* USER CODE BEGIN PFP */
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_CRC_Init();
+  /* USER CODE BEGIN 2 */
+  /* Configure LED1 and LED3 */
+  BSP_LED_Init(LED1);
+  BSP_LED_Init(LED3);
+
+  /* Compute the CRC of "aDataBuffer" */
+  uwCRCValue = HAL_CRC_Calculate(&hcrc, (uint32_t *)aDataBuffer, BUFFER_SIZE);
+
+  /* Compare the CRC value to the Expected one */
+  if (uwCRCValue != uwExpectedCRCValue)
+  {
+    /* Wrong CRC value: Turn LED3 on */
+    Error_Handler();
+  }
+  else
+  {
+    /* Right CRC value: Turn LED1 on */
+    BSP_LED_On(LED1);
+  }
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief CRC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_CRC_Init(void)
+{
+
+  /* USER CODE BEGIN CRC_Init 0 */
+
+  /* USER CODE END CRC_Init 0 */
+
+  /* USER CODE BEGIN CRC_Init 1 */
+
+  /* USER CODE END CRC_Init 1 */
+  hcrc.Instance = CRC;
+  hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE;
+  hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE;
+  hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE;
+  hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE;
+  hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_WORDS;
+  if (HAL_CRC_Init(&hcrc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN CRC_Init 2 */
+
+  /* USER CODE END CRC_Init 2 */
+
+}
+
+/* USER CODE BEGIN 4 */
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..276b7cfc9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,125 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    CRC/CRC_Example/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief CRC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hcrc: CRC handle pointer
+* @retval None
+*/
+void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc)
+{
+  if(hcrc->Instance==CRC)
+  {
+  /* USER CODE BEGIN CRC_MspInit 0 */
+
+  /* USER CODE END CRC_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_CRC_CLK_ENABLE();
+  /* USER CODE BEGIN CRC_MspInit 1 */
+
+  /* USER CODE END CRC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief CRC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hcrc: CRC handle pointer
+* @retval None
+*/
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef* hcrc)
+{
+  if(hcrc->Instance==CRC)
+  {
+  /* USER CODE BEGIN CRC_MspDeInit 0 */
+
+  /* USER CODE END CRC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_CRC_CLK_DISABLE();
+  /* USER CODE BEGIN CRC_MspDeInit 1 */
+
+  /* USER CODE END CRC_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..9111cc61f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Src/stm32wbxx_it.c
@@ -0,0 +1,122 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    CRC/CRC_Example/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/readme.txt b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/readme.txt
new file mode 100644
index 000000000..d31ff18d1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRC/CRC_Example/readme.txt
@@ -0,0 +1,85 @@
+/**
+  @page CRC_Example Cyclic Redundancy Check Example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    CRC/CRC_Example/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of Cyclic Redundancy Check Example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to configure the CRC using the HAL API. The CRC (cyclic
+redundancy check) calculation unit computes the CRC code of a given buffer of
+32-bit data words, using a fixed generator polynomial (0x4C11DB7).
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz.
+
+The CRC peripheral configuration is ensured by HAL_CRC_Init() function.
+The latter is calling HAL_CRC_MspInit() function which core is implementing
+the configuration of the needed CRC resources according to the used hardware (CLOCK). 
+You can update HAL_CRC_Init() input parameters to change the CRC configuration.
+
+The calculated CRC code is stored in uwCRCValue variable
+and compared with the expected one stored in uwExpectedCRCValue variable.
+
+STM32 board LEDs are used to monitor the example status:
+  - LED1 (GREEN) is ON when the correct CRC value is calculated
+  - LED3 (LED3) is ON when there is an error in initialization or if an incorrect CRC value is calculated.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The example needs to ensure that the SysTick time base is always set to 1 millisecond
+ to have correct HAL operation.
+
+@par Keywords
+
+Security, CRC, CRC Polynomial, IEC 60870-5, hardware CRC
+
+@par Directory contents
+
+  - CRC/CRC_Example/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - CRC/CRC_Example/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - CRC/CRC_Example/Inc/main.h                  Header for main.c module
+  - CRC/CRC_Example/Src/stm32wbxx_it.c          Interrupt handlers
+  - CRC/CRC_Example/Src/main.c                  Main program
+  - CRC/CRC_Example/Src/stm32wbxx_hal_msp.c     HAL MSP module 
+  - CRC/CRC_Example/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+     
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+  
+  - This example has been tested with an STMicroelectronics NUCLEO-WB35CE
+    board and can be easily tailored to any other supported device 
+    and development board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following:
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+ 
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
+ 
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/.extSettings b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/.extSettings
new file mode 100644
index 000000000..1077a5ac8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=UART
+[Groups]
+Doc=../readme.txt;../Expected_Results.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/CRYP_DMA.ioc b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/CRYP_DMA.ioc
new file mode 100644
index 000000000..d34ec13c3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/CRYP_DMA.ioc
@@ -0,0 +1,157 @@
+#MicroXplorer Configuration settings - do not modify
+AES1.Algorithm=CRYP_AES_ECB
+AES1.DataType=CRYP_DATATYPE_32B
+AES1.DataWidthUnit=CRYP_DATAWIDTHUNIT_WORD
+AES1.IPParameters=Algorithm,DataType,KeySize,pKey,DataWidthUnit,KeyIVConfigSkip
+AES1.KeyIVConfigSkip=CRYP_KEYIVCONFIG_ALWAYS
+AES1.KeySize=CRYP_KEYSIZE_128B
+AES1.pKey=2B7E1516 28AED2A6 ABF71588 09CF4F3C
+Dma.AES1_IN.0.Direction=DMA_MEMORY_TO_PERIPH
+Dma.AES1_IN.0.EventEnable=DISABLE
+Dma.AES1_IN.0.Instance=DMA1_Channel1
+Dma.AES1_IN.0.MemDataAlignment=DMA_MDATAALIGN_WORD
+Dma.AES1_IN.0.MemInc=DMA_MINC_ENABLE
+Dma.AES1_IN.0.Mode=DMA_NORMAL
+Dma.AES1_IN.0.PeriphDataAlignment=DMA_PDATAALIGN_WORD
+Dma.AES1_IN.0.PeriphInc=DMA_PINC_DISABLE
+Dma.AES1_IN.0.Polarity=HAL_DMAMUX_REQUEST_GEN_RISING
+Dma.AES1_IN.0.Priority=DMA_PRIORITY_LOW
+Dma.AES1_IN.0.RequestNumber=1
+Dma.AES1_IN.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.AES1_IN.0.SignalID=NONE
+Dma.AES1_IN.0.SyncEnable=DISABLE
+Dma.AES1_IN.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.AES1_IN.0.SyncRequestNumber=1
+Dma.AES1_IN.0.SyncSignalID=NONE
+Dma.AES1_OUT.1.Direction=DMA_PERIPH_TO_MEMORY
+Dma.AES1_OUT.1.EventEnable=DISABLE
+Dma.AES1_OUT.1.Instance=DMA1_Channel2
+Dma.AES1_OUT.1.MemDataAlignment=DMA_MDATAALIGN_WORD
+Dma.AES1_OUT.1.MemInc=DMA_MINC_ENABLE
+Dma.AES1_OUT.1.Mode=DMA_NORMAL
+Dma.AES1_OUT.1.PeriphDataAlignment=DMA_PDATAALIGN_WORD
+Dma.AES1_OUT.1.PeriphInc=DMA_PINC_DISABLE
+Dma.AES1_OUT.1.Polarity=HAL_DMAMUX_REQUEST_GEN_RISING
+Dma.AES1_OUT.1.Priority=DMA_PRIORITY_LOW
+Dma.AES1_OUT.1.RequestNumber=1
+Dma.AES1_OUT.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.AES1_OUT.1.SignalID=NONE
+Dma.AES1_OUT.1.SyncEnable=DISABLE
+Dma.AES1_OUT.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.AES1_OUT.1.SyncRequestNumber=1
+Dma.AES1_OUT.1.SyncSignalID=NONE
+Dma.Request0=AES1_IN
+Dma.Request1=AES1_OUT
+Dma.RequestsNb=2
+File.Version=6
+KeepUserPlacement=false
+Mcu.Family=STM32WB
+Mcu.IP0=AES1
+Mcu.IP1=DMA
+Mcu.IP2=NVIC
+Mcu.IP3=RCC
+Mcu.IP4=SYS
+Mcu.IPNb=5
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_AES1_VS_AES
+Mcu.Pin1=VP_SYS_VS_Systick
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:false\:false\:false
+NVIC.DMA1_Channel2_IRQn=true\:0\:0\:false\:false\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=3
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=false
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=CRYP_DMA.ioc
+ProjectManager.ProjectName=CRYP_DMA
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_DMA_Init-DMA-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_AES1_Init-AES1-false-HAL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FLatency=FLASH_LATENCY_3
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FLatency,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_AES1_VS_AES.Mode=AES_Activate
+VP_AES1_VS_AES.Signal=AES1_VS_AES
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/CRYP_DMA.ewd b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/CRYP_DMA.ewd
new file mode 100644
index 000000000..93c3325fb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/CRYP_DMA.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		CRYP_DMA
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/CRYP_DMA.ewp b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/CRYP_DMA.ewp
new file mode 100644
index 000000000..3cd3b11cb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/CRYP_DMA.ewp
@@ -0,0 +1,1138 @@
+
+
+  3
+  
+    CRYP_DMA
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        30
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\CMSIS\Device\ST\STM32WBxx\Source\Templates\iar\startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$\..\Src\main.c
+      
+      
+        $PROJ_DIR$\..\Src\stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$\..\Src\stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$\..\readme.txt
+    
+    
+      $PROJ_DIR$\..\Expected_Results.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$\..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE\nucleo_wb35ce.c
+        
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$\..\Src\system_stm32wbxx.c
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_uart.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_uart_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_cryp.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_cryp_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim_ex.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/Project.eww
new file mode 100644
index 000000000..a8a86d001
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\CRYP_DMA.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/stm32wb35xx_sram_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/stm32wb35xx_sram_cm4.icf
new file mode 100644
index 000000000..6426355fb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/EWARM/stm32wb35xx_sram_cm4.icf
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20003FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20004000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20008000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x2000FFFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Expected_Results.txt b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Expected_Results.txt
new file mode 100644
index 000000000..2b25be832
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Expected_Results.txt
@@ -0,0 +1,31 @@
+ =============================================================
+
 ================== Crypt Using HW Cryp  =====================
+
 =============================================================
+
 ---------------------------------------
+
 Plain Data :
+
 ---------------------------------------
+
[0xE2][0xBE][0xC1][0x6B][0x96][0x9F][0x40][0x2E][0x11][0x7E][0x3D][0xE9][0x2A][0x17][0x93][0x73]  Block 0 
+
[0x57][0x8A][0x2D][0xAE][0x9C][0xAC][0x03][0x1E][0xAC][0x6F][0xB7][0x9E][0x51][0x8E][0xAF][0x45]  Block 1 
+
[0x46][0x1C][0xC8][0x30][0x11][0xE4][0x5C][0xA3][0x19][0xC1][0xFB][0xE5][0xEF][0x52][0x0A][0x1A]  Block 2 
+
[0x45][0x24][0x9F][0xF6][0x17][0x9B][0x4F][0xDF][0x7B][0x41][0x2B][0xAD][0x10][0x37][0x6C][0xE6]  Block 3 
+
+
 =======================================
+
 Encrypted Data with AES 128  Mode  ECB
+
 ---------------------------------------
+
[0xB4][0x7B][0xD7][0x3A][0x60][0x36][0x7A][0x0D][0xF3][0xCA][0x9E][0xA8][0x97][0xEF][0x66][0x24] Block 0 
+
[0x85][0xD5][0xD3][0xF5][0x9D][0x69][0xB9][0x03][0x5A][0x89][0x85][0xE7][0xAF][0xBA][0xFD][0x96] Block 1 
+
[0x7F][0xCD][0xB1][0x43][0x23][0xCE][0x8E][0x59][0xE3][0x00][0x1B][0x88][0x88][0x06][0x03][0xED] Block 2 
+
[0x5E][0x78][0x0C][0x7B][0x3F][0xAD][0xE8][0x27][0x71][0x20][0x23][0x82][0xD4][0x5D][0x72][0x04] Block 3 
+
+
 =======================================
+
 Decrypted Data with AES 128  Mode  ECB
+
 ---------------------------------------
+
[0xE2][0xBE][0xC1][0x6B][0x96][0x9F][0x40][0x2E][0x11][0x7E][0x3D][0xE9][0x2A][0x17][0x93][0x73] Block 0 
+
[0x57][0x8A][0x2D][0xAE][0x9C][0xAC][0x03][0x1E][0xAC][0x6F][0xB7][0x9E][0x51][0x8E][0xAF][0x45] Block 1 
+
[0x46][0x1C][0xC8][0x30][0x11][0xE4][0x5C][0xA3][0x19][0xC1][0xFB][0xE5][0xEF][0x52][0x0A][0x1A] Block 2 
+
[0x45][0x24][0x9F][0xF6][0x17][0x9B][0x4F][0xDF][0x7B][0x41][0x2B][0xAD][0x10][0x37][0x6C][0xE6] Block 3 
+
======================================================
+
+
 DMA-based AES 128 ECB encryption/decryption done.
+
+
 No issue detected.
\ No newline at end of file
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Inc/main.h
new file mode 100644
index 000000000..d5a836464
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Inc/main.h
@@ -0,0 +1,73 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    CRYP/CRYP_DMA/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+#include "stdio.h"
+#include "string.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..588d5e390
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+#define HAL_CRYP_MODULE_ENABLED
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..27cd42787
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Inc/stm32wbxx_it.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    CRYP/CRYP_DMA/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+ ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void DMA1_Channel1_IRQHandler(void);
+void DMA1_Channel2_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/CRYP_DMA.uvoptx b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/CRYP_DMA.uvoptx
new file mode 100644
index 000000000..e58298d6b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/CRYP_DMA.uvoptx
@@ -0,0 +1,589 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    CRYP_DMA
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          ARMRTXEVENTFLAGS
+          -L70 -Z18 -C0 -M0 -T1
+        
+        
+          0
+          DLGTARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          
+        
+        
+          0
+          DLGUARM
+          (105=-1,-1,-1,-1,0)
+        
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U0667FF303337554E43181419 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO19 -TC64000000 -TP21 -TDS8005 -TDT0 -TDC1F -TIE1 -TIP1 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        1
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      2
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+    
+      2
+      5
+      1
+      0
+      0
+      0
+      .\Retarget.c
+      Retarget.c
+      0
+      0
+    
+    
+      2
+      6
+      1
+      0
+      0
+      0
+      .\Serial.c
+      Serial.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      7
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+    
+      3
+      8
+      5
+      0
+      0
+      0
+      ../Expected_Results.txt
+      Expected_Results.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      4
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+      stm32wbxx_hal_uart.c
+      0
+      0
+    
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+      stm32wbxx_hal_uart_ex.c
+      0
+      0
+    
+    
+      5
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp.c
+      stm32wbxx_hal_cryp.c
+      0
+      0
+    
+    
+      5
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp_ex.c
+      stm32wbxx_hal_cryp_ex.c
+      0
+      0
+    
+    
+      5
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      5
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      5
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      5
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      5
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      5
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      5
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      5
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      5
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      5
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      5
+      24
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      5
+      25
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      5
+      26
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      5
+      27
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      28
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/CRYP_DMA.uvprojx b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/CRYP_DMA.uvprojx
new file mode 100644
index 000000000..004cee110
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/CRYP_DMA.uvprojx
@@ -0,0 +1,572 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      CRYP_DMA
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          CRYP_DMA\
+          CRYP_DMA
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx,__DBG_ITM
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+            
+              Retarget.c
+              1
+              .\Retarget.c
+            
+            
+              Serial.c
+              1
+              .\Serial.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+            
+              Expected_Results.txt
+              5
+              ../Expected_Results.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_uart.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+            
+            
+              stm32wbxx_hal_uart_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+            
+            
+              stm32wbxx_hal_cryp.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp.c
+            
+            
+              stm32wbxx_hal_cryp_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp_ex.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/Retarget.c b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/Retarget.c
new file mode 100644
index 000000000..1557e71f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/Retarget.c
@@ -0,0 +1,52 @@
+/*----------------------------------------------------------------------------
+ * Name:    Retarget.c
+ * Purpose: 'Retarget' layer for target-dependent low level functions
+ * Note(s):
+ *----------------------------------------------------------------------------
+ * This file is part of the uVision/ARM development tools.
+ * This software may only be used under the terms of a valid, current,
+ * end user licence from KEIL for a compatible version of KEIL software
+ * development tools. Nothing else gives you the right to use this software.
+ *
+ * This software is supplied "AS IS" without warranties of any kind.
+ *
+ * Copyright (c) 2011 Keil - An ARM Company. All rights reserved.
+ *----------------------------------------------------------------------------*/
+
+#include 
+#include 
+#include "Serial.h"
+
+#pragma import(__use_no_semihosting_swi)
+
+
+
+struct __FILE { int handle; /* Add whatever you need here */ };
+FILE __stdout;
+FILE __stdin;
+
+
+int fputc(int c, FILE *f) {
+  return (SER_PutChar(c));
+}
+
+
+int fgetc(FILE *f) {
+  return (SER_GetChar());
+}
+
+
+int ferror(FILE *f) {
+  /* Your implementation of ferror */
+  return EOF;
+}
+
+
+void _ttywrch(int c) {
+  SER_PutChar(c);
+}
+
+
+void _sys_exit(int return_code) {
+label:  goto label;  /* endless loop */
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/Serial.c b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/Serial.c
new file mode 100644
index 000000000..ecf1b36da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/Serial.c
@@ -0,0 +1,43 @@
+/*----------------------------------------------------------------------------
+ * Name:    Serial.c
+ * Purpose: Low Level Serial Routines
+ * Note(s): possible defines select the used communication interface:
+ *            __DBG_ITM   - ITM SWO interface
+ *----------------------------------------------------------------------------
+ * This file is part of the uVision/ARM development tools.
+ * This software may only be used under the terms of a valid, current,
+ * end user licence from KEIL for a compatible version of KEIL software
+ * development tools. Nothing else gives you the right to use this software.
+ *
+ * This software is supplied "AS IS" without warranties of any kind.
+ *
+ * Copyright (c) 2019 Keil - An ARM Company. All rights reserved.
+ *----------------------------------------------------------------------------*/
+
+#include                   /* STM32WBxx Definitions              */
+#include "Serial.h"
+
+#ifdef __DBG_ITM
+volatile int ITM_RxBuffer = ITM_RXBUFFER_EMPTY;  /*  CMSIS Debug Input        */
+#endif
+
+
+/*----------------------------------------------------------------------------
+  Write character to Serial Port
+ *----------------------------------------------------------------------------*/
+int SER_PutChar (int c) {
+
+  ITM_SendChar(c);
+  return (c);
+}
+
+
+/*----------------------------------------------------------------------------
+  Read character from Serial Port   (blocking read)
+ *----------------------------------------------------------------------------*/
+int SER_GetChar (void) {
+
+  while (ITM_CheckChar() != 1) __NOP();
+  return (ITM_ReceiveChar());
+
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/Serial.h b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/Serial.h
new file mode 100644
index 000000000..81e691df2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/Serial.h
@@ -0,0 +1,24 @@
+/*----------------------------------------------------------------------------
+ * Name:    Serial.h
+ * Purpose: Low level serial definitions
+ * Note(s):
+ *----------------------------------------------------------------------------
+ * This file is part of the uVision/ARM development tools.
+ * This software may only be used under the terms of a valid, current,
+ * end user licence from KEIL for a compatible version of KEIL software
+ * development tools. Nothing else gives you the right to use this software.
+ *
+ * This software is supplied "AS IS" without warranties of any kind.
+ *
+ * Copyright (c) 2010 Keil - An ARM Company. All rights reserved.
+ *----------------------------------------------------------------------------*/
+
+#ifndef __SERIAL_H
+#define __SERIAL_H
+#include 
+
+extern void SER_Init      (void);
+extern int  SER_GetChar   (void);
+extern int SER_PutChar 		(int c);
+
+#endif
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..23d0a63af
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/.cproject
@@ -0,0 +1,180 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+					
+						
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/.project
new file mode 100644
index 000000000..9b846c613
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/.project
@@ -0,0 +1,170 @@
+
+
+	CRYP_DMA
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			CRYP_DMA.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/CRYP_DMA.ioc
+		
+		
+			Doc/Expected_Results.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Expected_Results.txt
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cryp.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cryp_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Src/main.c
new file mode 100644
index 000000000..d8e3cd2ac
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Src/main.c
@@ -0,0 +1,626 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    CRYP/CRYP_DMA/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example provides a short description of how to use the CRYPTO
+  *          peripheral to encrypt and decrypt data using CRYP Algorithm with
+  *          AES ECB chaining mode.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+CRYP_HandleTypeDef hcryp1;
+__ALIGN_BEGIN static const uint32_t pKeyAES1[4] __ALIGN_END = {
+                            0x2B7E1516,0x28AED2A6,0xABF71588,0x09CF4F3C};
+DMA_HandleTypeDef hdma_aes1_in;
+DMA_HandleTypeDef hdma_aes1_out;
+
+/* USER CODE BEGIN PV */
+/* Private define ------------------------------------------------------------*/
+
+#define KEY_SIZE          128 /* Key size in bits */
+
+/* The size of the plaintext in Words */
+#define PLAINTEXT_SIZE          ((uint32_t)16)
+#define AES_TEXT_SIZE           ((uint32_t)16)
+
+#define ECB               1
+#define CBC               2
+#define CTR               3
+
+#if (USE_VCP_CONNECTION == 1)
+/**
+  * @brief Defines related to Timeout to uart tranmission
+  */
+#define UART_TIMEOUT_VALUE  1000 /* 1 Second */
+
+/* UART handler declaration */
+UART_HandleTypeDef     UartHandle;
+
+/**
+  * @brief  Retargets the C library printf function to the USARTx.
+  * @param  ch: character to send
+  * @param  f: pointer to file (not used)
+  * @retval The character transmitted
+  */
+#ifdef __GNUC__
+/* With GCC, small printf (option LD Linker->Libraries->Small printf
+   set to 'Yes') calls __io_putchar() */
+int __io_putchar(int ch)
+#else
+int fputc(int ch, FILE *f)
+#endif /* __GNUC__ */
+{
+  /* Place your implementation of fputc here */
+  /* e.g. write a character to the UART and Loop until the end of transmission */
+  HAL_UART_Transmit(&UartHandle, (uint8_t *)&ch, 1, UART_TIMEOUT_VALUE);
+
+  return ch;
+}
+
+void BSP_COM_Init(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct;
+
+  /* Peripheral clock enable */
+  __HAL_RCC_USART1_CLK_ENABLE();
+  
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  /**USART1 GPIO Configuration    
+  PB6     ------> USART1_TX
+  PB7     ------> USART1_RX 
+  */
+  GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* Configure the UART peripheral                                        */
+  /* Put the USART peripheral in the Asynchronous mode (UART Mode) */
+  /* UART configured as follows:
+      - Word Length = 8 Bits
+      - Stop Bit = One Stop bit
+      - Parity = None
+      - BaudRate = 115200 baud
+      - Hardware flow control disabled (RTS and CTS signals) */
+  UartHandle.Instance                    = USART1;
+  UartHandle.Init.BaudRate               = 115200;
+  UartHandle.Init.WordLength             = UART_WORDLENGTH_8B;
+  UartHandle.Init.StopBits               = UART_STOPBITS_1;
+  UartHandle.Init.Parity                 = UART_PARITY_NONE;
+  UartHandle.Init.HwFlowCtl              = UART_HWCONTROL_NONE;
+  UartHandle.Init.Mode                   = UART_MODE_TX_RX;
+  UartHandle.Init.HwFlowCtl              = UART_HWCONTROL_NONE;
+  UartHandle.Init.OverSampling           = UART_OVERSAMPLING_16;
+  UartHandle.Init.OneBitSampling         = UART_ONE_BIT_SAMPLE_DISABLE;
+  UartHandle.Init.ClockPrescaler         = UART_PRESCALER_DIV1;
+  UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  
+  if(HAL_UART_DeInit(&UartHandle) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  
+  if(HAL_UART_Init(&UartHandle) != HAL_OK)
+  {
+    Error_Handler();
+  }  
+}
+#endif
+
+/* Plaintext */
+uint32_t aPlaintext[AES_TEXT_SIZE] =
+                        { 0x6BC1BEE2 ,0x2E409F96 ,0xE93D7E11 ,0x7393172A ,
+                          0xAE2D8A57 ,0x1E03AC9C ,0x9EB76FAC ,0x45AF8E51 ,
+                          0x30C81C46 ,0xA35CE411 ,0xE5FBC119 ,0x1A0A52EF ,
+                          0xF69F2445 ,0xDF4F9B17 ,0xAD2B417B ,0xE66C3710};
+
+
+/* Cyphertext */
+uint32_t aEncryptedtextExpected[AES_TEXT_SIZE] =
+                          {0x3AD77BB4 ,0x0D7A3660 ,0xA89ECAF3 ,0x2466EF97 ,
+                           0xF5D3D585 ,0x03B9699D ,0xE785895A ,0x96FDBAAF ,
+                           0x43B1CD7F ,0x598ECE23 ,0x881B00E3 ,0xED030688 ,
+                           0x7B0C785E ,0x27E8AD3F ,0x82232071 ,0x04725DD4};
+
+/* Used for storing the encrypted text */
+uint32_t aEncryptedText[AES_TEXT_SIZE] = {0};
+
+/* Used for storing the decrypted text */
+uint32_t aDecryptedText[PLAINTEXT_SIZE] = {0};
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_DMA_Init(void);
+static void MX_AES1_Init(void);
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+static void Display_PlainData(uint32_t datalength);
+static void Display_EncryptedData(uint8_t mode, uint16_t keysize, uint32_t datalength);
+static void Display_DecryptedData(uint8_t mode, uint16_t keysize, uint32_t datalength);
+#if defined(__GNUC__)
+extern void initialise_monitor_handles(void);
+#endif
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+#if defined(__GNUC__)
+  initialise_monitor_handles(); 
+#endif
+
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_DMA_Init();
+  MX_AES1_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Configure LEDs */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+
+#if (USE_VCP_CONNECTION == 1)
+	/* Configure the virtual com port */
+  BSP_COM_Init(&UartHandle);
+#endif
+
+   /*#######################################################################*/
+   /*                                                                       */
+   /*##-         DMA-based AES 128 ECB encryption              #############*/
+   /*                                                                       */   
+   /*#######################################################################*/
+  /*##- Configure the CRYP peripheral ######################################*/
+  if (HAL_CRYP_DeInit(&hcryp1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  
+  hcryp1.Instance = AES1;
+  hcryp1.Init.DataType      = CRYP_DATATYPE_32B;
+  hcryp1.Init.KeySize       = CRYP_KEYSIZE_128B;
+  hcryp1.Init.Algorithm     = CRYP_AES_ECB;
+  hcryp1.Init.pKey          = (uint32_t *)pKeyAES1;
+  hcryp1.Init.DataWidthUnit = CRYP_DATAWIDTHUNIT_WORD;
+
+  if (HAL_CRYP_Init(&hcryp1) != HAL_OK)
+  {
+    /* Initialization Error */
+    Error_Handler();
+  }
+  
+  /* Display Plain Data*/
+  Display_PlainData(PLAINTEXT_SIZE);
+
+  HAL_Delay(1);
+  
+  if (HAL_CRYP_Encrypt_DMA(&hcryp1, aPlaintext, PLAINTEXT_SIZE, aEncryptedText) != HAL_OK)
+  {
+    /* Processing Error */
+    Error_Handler(); 
+  }
+
+  /*  Before starting a new process, the current state of the peripheral is checked; 
+      as long as the state is not set back to READY, no new ciphering processing
+      can be started.
+      For simplicity's sake, this example is just waiting till the end of the 
+      process, but application may perform other tasks while cihering operation
+      is ongoing. */ 
+  while (HAL_CRYP_GetState(&hcryp1) != HAL_CRYP_STATE_READY)
+  {
+  }
+  
+  /* Display encrypted Data */
+  Display_EncryptedData(ECB, 128, AES_TEXT_SIZE);
+  
+  /*##- Compare the encrypted text with the expected one #####################*/
+  if(memcmp(aEncryptedText, aEncryptedtextExpected, PLAINTEXT_SIZE*4) != 0)
+  {
+    Error_Handler();
+  }
+  else
+  {
+    /* Correct encryption */
+  }
+  
+   /*#######################################################################*/
+   /*                                                                       */
+   /*##-         DMA-based AES 128 ECB decryption              #############*/
+   /*                                                                       */   
+   /*#######################################################################*/
+  /* Deinitialize Crypto peripheral */
+  HAL_CRYP_DeInit(&hcryp1);
+  
+  
+  if(HAL_CRYP_Init(&hcryp1) != HAL_OK)
+  {
+    /* Initialization Error */
+    Error_Handler(); 
+  }
+  
+  if(HAL_CRYP_Decrypt_DMA(&hcryp1, aEncryptedtextExpected, PLAINTEXT_SIZE, aDecryptedText) != HAL_OK)
+  {
+    /* Processing Error */
+    Error_Handler(); 
+  }
+  
+  /*  Before starting a new process, the current state of the peripheral is checked; 
+      as long as the state is not set back to READY, no new ciphering processing
+      can be started.
+      For simplicity's sake, this example is just waiting till the end of the 
+      process, but application may perform other tasks while cihering operation
+      is ongoing. */ 
+  while (HAL_CRYP_GetState(&hcryp1) != HAL_CRYP_STATE_READY)
+  {
+  }
+          
+  /* Display decrypted Data */
+  Display_DecryptedData(ECB, 128, PLAINTEXT_SIZE);
+
+  /*##- Compare the decrypted text with the expected one #####################*/
+  if(memcmp(aDecryptedText, aPlaintext, PLAINTEXT_SIZE*4) != 0)
+  {
+    Error_Handler();
+  }
+  else
+  {
+    /* Correct decryption */
+  }
+  
+  printf("======================================================\n");
+  printf("\n\r DMA-based AES 128 ECB encryption/decryption done.\n");
+  printf("\n\r No issue detected.\n");
+
+  /* Turn LED2 on */
+  BSP_LED_On(LED2);
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief AES1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_AES1_Init(void)
+{
+
+  /* USER CODE BEGIN AES1_Init 0 */
+
+  /* USER CODE END AES1_Init 0 */
+
+  /* USER CODE BEGIN AES1_Init 1 */
+
+  /* USER CODE END AES1_Init 1 */
+  hcryp1.Instance = AES1;
+  hcryp1.Init.DataType = CRYP_DATATYPE_32B;
+  hcryp1.Init.KeySize = CRYP_KEYSIZE_128B;
+  hcryp1.Init.pKey = (uint32_t *)pKeyAES1;
+  hcryp1.Init.Algorithm = CRYP_AES_ECB;
+  hcryp1.Init.DataWidthUnit = CRYP_DATAWIDTHUNIT_WORD;
+  hcryp1.Init.KeyIVConfigSkip = CRYP_KEYIVCONFIG_ALWAYS;
+  if (HAL_CRYP_Init(&hcryp1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN AES1_Init 2 */
+
+  /* USER CODE END AES1_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+  /* DMA1_Channel2_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
+
+}
+ 
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  Display Plain Data
+  * @param  datalength: length of the data to display
+  * @retval None
+  */
+static void Display_PlainData(uint32_t datalength)
+{
+  uint32_t BufferCounter = 0;
+  uint32_t count = 0;
+  uint8_t * ptr = (uint8_t *)aPlaintext;
+
+  printf("\n\r =============================================================\n\r");
+  printf(" ================== Crypt Using HW Cryp  =====================\n\r");
+  printf(" =============================================================\n\r");
+  printf(" ---------------------------------------\n\r");
+  printf(" Plain Data :\n\r");
+  printf(" ---------------------------------------\n\r");
+
+  for (BufferCounter = 0; BufferCounter < datalength*4; BufferCounter++)
+  {
+    printf("[0x%02X]", *ptr++);
+    count++;
+
+    if (count == 16)
+    {
+      count = 0;
+      printf("  Block %lu \n\r", BufferCounter / 16);
+    }
+  }
+}
+
+/**
+  * @brief  Display Encrypted Data
+  * @param  mode: chaining mode
+  * @param  keysize: AES key size used
+  * @param  datalength: length of the data to display
+  * @retval None
+  */
+static void Display_EncryptedData(uint8_t mode, uint16_t keysize, uint32_t datalength)
+{
+  uint32_t BufferCounter = 0;
+  uint32_t count = 0;
+  uint8_t * ptr = (uint8_t *)aEncryptedText;
+
+  printf("\n\r =======================================\n\r");
+  printf(" Encrypted Data with AES %d  Mode  ", keysize);
+
+  if (mode == ECB)
+  {
+    printf("ECB\n\r");
+  }
+  else if (mode == CBC)
+  {
+    printf("CBC\n\r");
+  }
+  else /* if(mode == CTR)*/
+  {
+    printf("CTR\n\r");
+  }
+
+  printf(" ---------------------------------------\n\r");
+
+  for (BufferCounter = 0; BufferCounter < datalength*4; BufferCounter++)
+  {
+    printf("[0x%02X]", *ptr++);
+
+    count++;
+    if (count == 16)
+    {
+      count = 0;
+      printf(" Block %lu \n\r", BufferCounter / 16);
+    }
+  }
+}
+
+/**
+  * @brief  Display Decrypted Data
+  * @param  mode: chaining mode
+  * @param  keysize: AES key size used
+  * @param  datalength: length of the data to display
+  * @retval None
+  */
+static void Display_DecryptedData(uint8_t mode, uint16_t keysize, uint32_t datalength)
+{
+  uint32_t BufferCounter = 0;
+  uint32_t count = 0;
+  uint8_t * ptr = (uint8_t *)aDecryptedText;
+
+  printf("\n\r =======================================\n\r");
+  printf(" Decrypted Data with AES %d  Mode  ", keysize);
+
+  if (mode == ECB)
+  {
+    printf("ECB\n\r");
+  }
+  else if (mode == CBC)
+  {
+    printf("CBC\n\r");
+  }
+  else /* if(mode == CTR)*/
+  {
+    printf("CTR\n\r");
+  }
+
+  printf(" ---------------------------------------\n\r");
+
+  for (BufferCounter = 0; BufferCounter < datalength*4; BufferCounter++)
+  {
+    printf("[0x%02X]", *ptr++);
+    count++;
+
+    if (count == 16)
+    {
+      count = 0;
+      printf(" Block %lu \n\r", BufferCounter / 16);
+    }
+  }
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  printf("\n\r Error Detected...\n ");  
+
+  while(1)
+  {
+    /* Toggle LED3 */
+    BSP_LED_Toggle(LED3);
+    HAL_Delay(200);
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..1d28743b1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,168 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    CRYP/CRYP_DMA/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_aes1_in;
+
+extern DMA_HandleTypeDef hdma_aes1_out;
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief CRYP MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hcryp: CRYP handle pointer
+* @retval None
+*/
+void HAL_CRYP_MspInit(CRYP_HandleTypeDef* hcryp)
+{
+  if(hcryp->Instance==AES1)
+  {
+  /* USER CODE BEGIN AES1_MspInit 0 */
+
+  /* USER CODE END AES1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_AES1_CLK_ENABLE();
+  
+    /* AES1 DMA Init */
+    /* AES1_IN Init */
+    hdma_aes1_in.Instance = DMA1_Channel1;
+    hdma_aes1_in.Init.Request = DMA_REQUEST_AES1_IN;
+    hdma_aes1_in.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_aes1_in.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_aes1_in.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_aes1_in.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
+    hdma_aes1_in.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
+    hdma_aes1_in.Init.Mode = DMA_NORMAL;
+    hdma_aes1_in.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_aes1_in) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(hcryp,hdmain,hdma_aes1_in);
+
+    /* AES1_OUT Init */
+    hdma_aes1_out.Instance = DMA1_Channel2;
+    hdma_aes1_out.Init.Request = DMA_REQUEST_AES1_OUT;
+    hdma_aes1_out.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_aes1_out.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_aes1_out.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_aes1_out.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
+    hdma_aes1_out.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
+    hdma_aes1_out.Init.Mode = DMA_NORMAL;
+    hdma_aes1_out.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_aes1_out) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(hcryp,hdmaout,hdma_aes1_out);
+
+  /* USER CODE BEGIN AES1_MspInit 1 */
+
+  /* USER CODE END AES1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief CRYP MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hcryp: CRYP handle pointer
+* @retval None
+*/
+void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef* hcryp)
+{
+  if(hcryp->Instance==AES1)
+  {
+  /* USER CODE BEGIN AES1_MspDeInit 0 */
+
+  /* USER CODE END AES1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_AES1_CLK_DISABLE();
+
+    /* AES1 DMA DeInit */
+    HAL_DMA_DeInit(hcryp->hdmain);
+    HAL_DMA_DeInit(hcryp->hdmaout);
+  /* USER CODE BEGIN AES1_MspDeInit 1 */
+
+  /* USER CODE END AES1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..f2a227f53
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Src/stm32wbxx_it.c
@@ -0,0 +1,234 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    CRYP/CRYP_DMA/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+extern CRYP_HandleTypeDef hcryp1;
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_aes1_in;
+extern DMA_HandleTypeDef hdma_aes1_out;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+ /**
+* @brief This function handles DMA1_Channel1_IRQ global interrupt.
+*/
+void DMA1_Channel1_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
+      
+  /* USER CODE END DMA1_Channel1_IRQn 0 */
+  HAL_DMA_IRQHandler(hcryp1.hdmain);
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
+     
+  /* USER CODE END DMA1_Channel1_IRQn 1 */
+}
+
+/**
+* @brief This function handles DMA1_Channel2_IRQ global interrupt.
+*/
+void DMA1_Channel2_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */
+     
+  /* USER CODE END DMA1_Channel2_IRQn 0 */
+  HAL_DMA_IRQHandler(hcryp1.hdmaout);
+  /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */
+   
+  /* USER CODE END DMA1_Channel2_IRQn 1 */
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..759409368
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/readme.txt b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/readme.txt
new file mode 100644
index 000000000..becb8a4d4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/CRYP/CRYP_DMA/readme.txt
@@ -0,0 +1,94 @@
+/**
+  @page CRYP_DMA  Encrypt and Decrypt data using AES Algo in ECB chaining
+   mode using DMA
+  
+  @verbatim
+  ******************************************************************************
+  * @file    CRYP/CRYP_DMA/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the CRYP AES Algorithm in ECB mode with DMA Example
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to use the AES1 peripheral to encrypt and decrypt data using AES 128 
+Algorithm with ECB chaining mode in DMA mode.
+
+DMA is used to transfer data from memory to the AES processor
+input as well as to transfer data from AES processor output to memory.
+
+64-byte buffers are ciphered and deciphered (4 AES blocks)
+Ciphering/Deciphering with a 128-bit long key is used with data type set to 8-bit (byte swapping).
+
+This example unrolls as follows: 
+- AES Encryption (Plain Data --> Encrypted Data)
+- AES Decryption with key derivation (Encrypted Data --> Decrypted Data)
+
+Plain data, encrypted data and decrypted data are displayed on debugger terminal IO. 
+Note that when resorting to MDK-ARM KEIL IDE, plain data, encrypted data and decrypted 
+data are displayed on debugger as follows:  View --> Serial Viewer --> Debug (printf) Viewer.
+When resorting to AC6 SW4STM32 IDE:
+ Command Code is displayed on debugger as follows: Window--> Show View--> Console.
+ In Debug configuration :
+  - Window\Debugger, select the Debug probe : ST-LINK(OpenOCD)
+  - window\Startup,add the command "monitor arm semihosting enable"
+
+When all ciphering and deciphering operations are successful, LED2 is turned on.
+In case of ciphering or deciphering issue, LED3 toggle each 200ms. 
+
+
+@par Keywords
+
+Security, Cryptography, CRYPT, AES, ECB, DMA, cipher, UART
+
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate
+      delay (in milliseconds) based on variable incremented in SysTick ISR. This
+      implies that if HAL_Delay() is called from a peripheral ISR process, then 
+      the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application need to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Directory contents 
+
+  - CRYP/CRYP_DMA/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - CRYP/CRYP_DMA/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - CRYP/CRYP_DMA/Inc/main.h                  Header for main.c module  
+  - CRYP/CRYP_DMA/Src/stm32wbxx_it.c          Interrupt handlers
+  - CRYP/CRYP_DMA/Src/main.c                  Main program
+  - CRYP/CRYP_DMA/Src/stm32wbxx_hal_msp.c     HAL MSP module
+  - CRYP/CRYP_DMA/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+   - This example runs on STM32WB35xx devices.
+  
+    - This example has been tested with a STM32WB35CEUx embedded on an 
+    NUCLEO-WB35CE board and can be easily tailored to any other supported 
+    device and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following:
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/.extSettings b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/DMA_FLASHToRAM.ioc b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/DMA_FLASHToRAM.ioc
new file mode 100644
index 000000000..88dfd86f9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/DMA_FLASHToRAM.ioc
@@ -0,0 +1,127 @@
+#MicroXplorer Configuration settings - do not modify
+Dma.MEMTOMEM.0.Direction=DMA_MEMORY_TO_MEMORY
+Dma.MEMTOMEM.0.EventEnable=DISABLE
+Dma.MEMTOMEM.0.Instance=DMA1_Channel1
+Dma.MEMTOMEM.0.MemDataAlignment=DMA_MDATAALIGN_WORD
+Dma.MEMTOMEM.0.MemInc=DMA_MINC_ENABLE
+Dma.MEMTOMEM.0.Mode=DMA_NORMAL
+Dma.MEMTOMEM.0.PeriphDataAlignment=DMA_PDATAALIGN_WORD
+Dma.MEMTOMEM.0.PeriphInc=DMA_PINC_ENABLE
+Dma.MEMTOMEM.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.MEMTOMEM.0.Priority=DMA_PRIORITY_LOW
+Dma.MEMTOMEM.0.RequestNumber=1
+Dma.MEMTOMEM.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.MEMTOMEM.0.SignalID=NONE
+Dma.MEMTOMEM.0.SyncEnable=DISABLE
+Dma.MEMTOMEM.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.MEMTOMEM.0.SyncRequestNumber=1
+Dma.MEMTOMEM.0.SyncSignalID=NONE
+Dma.Request0=MEMTOMEM
+Dma.RequestsNb=1
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=DMA
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=DMA_FLASHToRAM.ioc
+ProjectManager.ProjectName=DMA_FLASHToRAM
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewd b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewd
new file mode 100644
index 000000000..583958c44
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		DMA_FLASHToRAM
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewp b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewp
new file mode 100644
index 000000000..403a590c1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    DMA_FLASHToRAM
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/Project.eww
new file mode 100644
index 000000000..d6ac81382
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\DMA_FLASHToRAM.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Inc/main.h
new file mode 100644
index 000000000..80d308b58
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    DMA/DMA_FLASHToRAM/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+#define BUFFER_SIZE 32
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..19d12a61f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..2932088d6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Inc/stm32wbxx_it.h
@@ -0,0 +1,65 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    DMA/DMA_FLASHToRAM/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void DMA1_Channel1_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvoptx b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvoptx
new file mode 100644
index 000000000..32b3c0534
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    DMA_FLASHToRAM
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvprojx b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvprojx
new file mode 100644
index 000000000..b1ccf6de0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvprojx
@@ -0,0 +1,541 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      DMA_FLASHToRAM
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          DMA_FLASHToRAM\
+          DMA_FLASHToRAM
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..406d8f1b9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/.project
new file mode 100644
index 000000000..894492b5a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	DMA_FLASHToRAM
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			DMA_FLASHToRAM.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/DMA_FLASHToRAM.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Src/main.c
new file mode 100644
index 000000000..e91d0066c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Src/main.c
@@ -0,0 +1,316 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    DMA/DMA_FLASHToRAM/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example provides a description of how to use a DMA channel
+  *          to transfer a word data buffer from FLASH memory to embedded
+  *          SRAM memory through the STM32WBxx HAL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+DMA_HandleTypeDef hdma_memtomem_dma1_channel1;
+/* USER CODE BEGIN PV */
+
+static const uint32_t aSRC_Const_Buffer[BUFFER_SIZE] =
+{
+  0x01020304, 0x05060708, 0x090A0B0C, 0x0D0E0F10,
+  0x11121314, 0x15161718, 0x191A1B1C, 0x1D1E1F20,
+  0x21222324, 0x25262728, 0x292A2B2C, 0x2D2E2F30,
+  0x31323334, 0x35363738, 0x393A3B3C, 0x3D3E3F40,
+  0x41424344, 0x45464748, 0x494A4B4C, 0x4D4E4F50,
+  0x51525354, 0x55565758, 0x595A5B5C, 0x5D5E5F60,
+  0x61626364, 0x65666768, 0x696A6B6C, 0x6D6E6F70,
+  0x71727374, 0x75767778, 0x797A7B7C, 0x7D7E7F80
+};
+
+static uint32_t aDST_Buffer[BUFFER_SIZE];
+
+static __IO uint32_t transferErrorDetected;    /* Set to 1 if an error transfer is detected */
+static __IO uint32_t transferCompleteDetected; /* Set to 1 if transfer is correctly completed */
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_DMA_Init(void);
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+static void TransferComplete(DMA_HandleTypeDef *hdma_memtomem_dma1_channel1);
+static void TransferError(DMA_HandleTypeDef *hdma_memtomem_dma1_channel1);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+    
+
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_DMA_Init();
+  /* USER CODE BEGIN 2 */
+  /* Initialize LEDs */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED1);
+  BSP_LED_Init(LED3);
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  /* Reset transferErrorDetected to 0, it will be set to 1 if a transfer error is detected */
+  transferErrorDetected = 0;
+  /* Reset transferCompleteDetected to 0, it will be set to 1 if a transfer is correctly completed */
+  transferCompleteDetected = 0;
+
+  /* Select Callbacks functions called after Transfer complete and Transfer error */
+  HAL_DMA_RegisterCallback(&hdma_memtomem_dma1_channel1, HAL_DMA_XFER_CPLT_CB_ID, TransferComplete);
+  HAL_DMA_RegisterCallback(&hdma_memtomem_dma1_channel1, HAL_DMA_XFER_ERROR_CB_ID, TransferError);
+  
+  /* Configure the source, destination and buffer size DMA fields and Start DMA Channel/Stream transfer */
+  /* Enable All the DMA interrupts */
+  if (HAL_DMA_Start_IT(&hdma_memtomem_dma1_channel1, (uint32_t)&aSRC_Const_Buffer, (uint32_t)&aDST_Buffer, BUFFER_SIZE) != HAL_OK)
+  {
+    /* Transfer Error */
+    Error_Handler();
+  }
+
+  /* Infinite loop */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    if (transferErrorDetected == 1)
+    {
+      /* Turn LED1 on*/
+      BSP_LED_On(LED1);
+      transferErrorDetected = 0;
+    }
+    if (transferCompleteDetected == 1)
+    {
+      /* Turn LED2 on*/
+      BSP_LED_On(LED2);
+      transferCompleteDetected = 0;
+    }
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/** 
+  * Enable DMA controller clock
+  * Configure DMA for memory to memory transfers
+  *   hdma_memtomem_dma1_channel1
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+  /* Configure DMA request hdma_memtomem_dma1_channel1 on DMA1_Channel1 */
+  hdma_memtomem_dma1_channel1.Instance = DMA1_Channel1;
+  hdma_memtomem_dma1_channel1.Init.Request = DMA_REQUEST_MEM2MEM;
+  hdma_memtomem_dma1_channel1.Init.Direction = DMA_MEMORY_TO_MEMORY;
+  hdma_memtomem_dma1_channel1.Init.PeriphInc = DMA_PINC_ENABLE;
+  hdma_memtomem_dma1_channel1.Init.MemInc = DMA_MINC_ENABLE;
+  hdma_memtomem_dma1_channel1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
+  hdma_memtomem_dma1_channel1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
+  hdma_memtomem_dma1_channel1.Init.Mode = DMA_NORMAL;
+  hdma_memtomem_dma1_channel1.Init.Priority = DMA_PRIORITY_LOW;
+  if (HAL_DMA_Init(&hdma_memtomem_dma1_channel1) != HAL_OK)
+  {
+    Error_Handler( );
+  }
+
+  /* DMA interrupt init */
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+
+}
+ 
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  DMA conversion complete callback
+  * @note   This function is executed when the transfer complete interrupt
+  *         is generated
+  * @retval None
+  */
+static void TransferComplete(DMA_HandleTypeDef *hdma_memtomem_dma1_channel1)
+{
+  transferCompleteDetected = 1;
+}
+
+/**
+  * @brief  DMA conversion error callback
+  * @note   This function is executed when the transfer error interrupt
+  *         is generated during DMA transfer
+  * @retval None
+  */
+static void TransferError(DMA_HandleTypeDef *hdma_memtomem_dma1_channel1)
+{
+  transferErrorDetected = 1;
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* Turn LED3 on: Transfer Error */
+  BSP_LED_On(LED3);
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..f9463e6fe
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    DMA/DMA_FLASHToRAM/Inc/stm32wbxx_hal_msp.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..7a6494097
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Src/stm32wbxx_it.c
@@ -0,0 +1,134 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    DMA/DMA_FLASHToRAM/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_memtomem_dma1_channel1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles DMA1 channel1 global interrupt.
+  */
+void DMA1_Channel1_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel1_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_memtomem_dma1_channel1);
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel1_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/readme.txt b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/readme.txt
new file mode 100644
index 000000000..6ad85a736
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_FLASHToRAM/readme.txt
@@ -0,0 +1,90 @@
+/**
+  @page DMA_FLASHToRAM DMA FLASH To RAM Example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    DMA/DMA_FLASHToRAM/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the DMA FLASH to RAM example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to use a DMA to transfer a word data buffer from Flash memory to embedded 
+SRAM through the HAL API.
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz.
+
+DMA1_Channel1 is configured to transfer the contents of a 32-word data 
+buffer stored in Flash memory to the reception buffer declared in RAM.
+
+The start of transfer is triggered by software. DMA1_Channel1 memory-to-memory
+transfer is enabled. Source and destination addresses incrementing is also enabled.
+The transfer is started by setting the channel enable bit for DMA1_Channel1.
+At the end of the transfer a Transfer Complete interrupt is generated since it
+is enabled and the callback function (customized by user) is called.
+
+NUCLEO-WB35CE board's LEDs can be used to monitor the transfer status:
+ - LED2 is ON when the transfer is complete (into the Transfer Complete interrupt
+   routine).
+ - LED1 is ON when there is a transfer error 
+ - LED3 is ON when a Error_Handler is called
+ 
+It is possible to select a different channel for the DMA transfer
+example by modifying defines values in the file main.h.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application need to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+System, DMA, Data Transfer, Memory to memory, Stream, Flash, RAM
+
+@par Directory contents 
+
+  - DMA/DMA_FLASHToRAM/Src/system_stm32wbxx.c           stm32wbxx system source file
+  - DMA/DMA_FLASHToRAM/Src/stm32wbxx_it.c               Interrupt handlers
+  - DMA/DMA_FLASHToRAM/Src/main.c                             Main program
+  - DMA/DMA_FLASHToRAM/Inc/stm32wbxx_hal_conf.h         HAL Configuration file
+  - DMA/DMA_FLASHToRAM/Inc/stm32wbxx_it.h               Interrupt handlers header file
+  - DMA/DMA_FLASHToRAM/Inc/main.h                             Main program header file
+  - DMA/DMA_FLASHToRAM/Src/stm32wbxx_hal_msp.c          HAL MSP module
+
+     
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx Devices.
+
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE 
+    board and can be easily tailored to any other supported device 
+    and development board.    
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+   
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/.extSettings b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/DMA_MUXSYNC.ioc b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/DMA_MUXSYNC.ioc
new file mode 100644
index 000000000..9baa54748
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/DMA_MUXSYNC.ioc
@@ -0,0 +1,177 @@
+#MicroXplorer Configuration settings - do not modify
+Dma.Request0=USART1_TX
+Dma.RequestsNb=1
+Dma.USART1_TX.0.Direction=DMA_MEMORY_TO_PERIPH
+Dma.USART1_TX.0.EventEnable=ENABLE
+Dma.USART1_TX.0.Instance=DMA1_Channel1
+Dma.USART1_TX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.USART1_TX.0.MemInc=DMA_MINC_ENABLE
+Dma.USART1_TX.0.Mode=DMA_NORMAL
+Dma.USART1_TX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.USART1_TX.0.PeriphInc=DMA_PINC_DISABLE
+Dma.USART1_TX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.USART1_TX.0.Priority=DMA_PRIORITY_LOW
+Dma.USART1_TX.0.RequestNumber=1
+Dma.USART1_TX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.USART1_TX.0.SignalID=HAL_DMAMUX1_REQ_GEN_EXTI0
+Dma.USART1_TX.0.SyncEnable=ENABLE
+Dma.USART1_TX.0.SyncPolarity=HAL_DMAMUX_SYNC_RISING
+Dma.USART1_TX.0.SyncRequestNumber=4
+Dma.USART1_TX.0.SyncSignalID=HAL_DMAMUX1_SYNC_LPTIM1_OUT
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+LPTIM1.ClockPrescaler=LPTIM_PRESCALER_DIV4
+LPTIM1.IPParameters=ClockPrescaler,UpdateMode,TriggerSource
+LPTIM1.TriggerSource=LPTIM_TRIGSOURCE_SOFTWARE
+LPTIM1.UpdateMode=LPTIM_UPDATE_ENDOFPERIOD
+Mcu.Family=STM32WB
+Mcu.IP0=DMA
+Mcu.IP1=LPTIM1
+Mcu.IP2=NVIC
+Mcu.IP3=RCC
+Mcu.IP4=SYS
+Mcu.IP5=USART1
+Mcu.IPNb=6
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PC14-OSC32_IN
+Mcu.Pin1=PC15-OSC32_OUT
+Mcu.Pin2=PB6
+Mcu.Pin3=PB7
+Mcu.Pin4=VP_LPTIM1_VS_LPTIM_counterModeInternalClock
+Mcu.Pin5=VP_SYS_VS_Systick
+Mcu.PinsNb=6
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.DMAMUX1_OVR_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PB6.GPIOParameters=GPIO_Speed
+PB6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PB6.Locked=true
+PB6.Mode=Asynchronous
+PB6.Signal=USART1_TX
+PB7.GPIOParameters=GPIO_Speed
+PB7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PB7.Locked=true
+PB7.Mode=Asynchronous
+PB7.Signal=USART1_RX
+PC14-OSC32_IN.Mode=LSE-External-Oscillator
+PC14-OSC32_IN.Signal=RCC_OSC32_IN
+PC15-OSC32_OUT.Mode=LSE-External-Oscillator
+PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=DMA_MUXSYNC.ioc
+ProjectManager.ProjectName=DMA_MUXSYNC
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_LPTIM1_Init-LPTIM1-false-HAL-true,5-MX_USART1_UART_Init-USART1-false-HAL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=true
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1CLockSelection,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1CLockSelection=RCC_LPTIM1CLKSOURCE_LSE
+RCC.LPTIM1Freq_Value=32768
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+USART1.AutoBaudRateEnableParam=UART_ADVFEATURE_AUTOBAUDRATE_DISABLE
+USART1.BaudRate=115200
+USART1.ClockPrescaler=PRESCALER_DIV1
+USART1.DMADisableonRxErrorParam=ADVFEATURE_DMA_ENABLEONRXERROR
+USART1.DataInvertParam=ADVFEATURE_DATAINV_DISABLE
+USART1.FIFOMode=FIFOMODE_DISABLE
+USART1.IPParameters=BaudRate,WordLength,Parity,StopBits,Mode,OverSampling,OneBitSampling,ClockPrescaler,FIFOMode,TXFIFOThreshold,RXFIFOThreshold,AutoBaudRateEnableParam,TxPinLevelInvertParam,RxPinLevelInvertParam,DataInvertParam,SwapParam,OverrunDisableParam,DMADisableonRxErrorParam,MSBFirstParam,VirtualMode-Asynchronous
+USART1.MSBFirstParam=ADVFEATURE_MSBFIRST_DISABLE
+USART1.Mode=MODE_TX_RX
+USART1.OneBitSampling=UART_ONE_BIT_SAMPLE_DISABLE
+USART1.OverSampling=UART_OVERSAMPLING_16
+USART1.OverrunDisableParam=ADVFEATURE_OVERRUN_ENABLE
+USART1.Parity=PARITY_NONE
+USART1.RXFIFOThreshold=RXFIFO_THRESHOLD_1EIGHTHFULL
+USART1.RxPinLevelInvertParam=ADVFEATURE_RXINV_DISABLE
+USART1.StopBits=STOPBITS_1
+USART1.SwapParam=ADVFEATURE_SWAP_DISABLE
+USART1.TXFIFOThreshold=TXFIFO_THRESHOLD_1EIGHTHFULL
+USART1.TxPinLevelInvertParam=ADVFEATURE_TXINV_DISABLE
+USART1.VirtualMode-Asynchronous=VM_ASYNC
+USART1.WordLength=WORDLENGTH_8B
+VP_LPTIM1_VS_LPTIM_counterModeInternalClock.Mode=Counts__internal_clock_event_00
+VP_LPTIM1_VS_LPTIM_counterModeInternalClock.Signal=LPTIM1_VS_LPTIM_counterModeInternalClock
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/DMA_MUXSYNC.ewd b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/DMA_MUXSYNC.ewd
new file mode 100644
index 000000000..72c145b7b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/DMA_MUXSYNC.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		DMA_MUXSYNC
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/DMA_MUXSYNC.ewp b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/DMA_MUXSYNC.ewp
new file mode 100644
index 000000000..062180169
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/DMA_MUXSYNC.ewp
@@ -0,0 +1,1128 @@
+
+
+  3
+  
+    DMA_MUXSYNC
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/Project.eww
new file mode 100644
index 000000000..06db829b1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\DMA_MUXSYNC.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Inc/main.h
new file mode 100644
index 000000000..e33e5ae11
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Inc/main.h
@@ -0,0 +1,106 @@
+/* USER CODE BEGIN Header */
+
+/**
+  ******************************************************************************
+  * @file    DMA/DMAMUX_SYNC/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+/* Definition for USARTx clock resources */
+#define USARTx                           USART1
+#define USARTx_CLK_ENABLE()              __HAL_RCC_USART1_CLK_ENABLE()
+#define DMAx_CLK_ENABLE()                do {                                \
+                                            __HAL_RCC_DMA1_CLK_ENABLE();    \
+                                            __HAL_RCC_DMAMUX1_CLK_ENABLE(); \
+                                         }while(0)
+#define USARTx_RX_GPIO_CLK_ENABLE()      __HAL_RCC_GPIOB_CLK_ENABLE()
+#define USARTx_TX_GPIO_CLK_ENABLE()      __HAL_RCC_GPIOB_CLK_ENABLE()
+
+#define USARTx_FORCE_RESET()             __HAL_RCC_USART1_FORCE_RESET()
+#define USARTx_RELEASE_RESET()           __HAL_RCC_USART1_RELEASE_RESET()
+
+/* Definition for USARTx Pins */
+#define USARTx_TX_PIN                    GPIO_PIN_6
+#define USARTx_TX_GPIO_PORT              GPIOB
+#define USARTx_TX_AF                     GPIO_AF7_USART1
+#define USARTx_RX_PIN                    GPIO_PIN_7
+#define USARTx_RX_GPIO_PORT              GPIOB
+#define USARTx_RX_AF                     GPIO_AF7_USART1
+
+/* Definition for USARTx's DMA */
+#define USARTx_TX_DMA_INSTANCE           DMA1_Channel1
+
+#define USARTx_TX_DMA_REQUEST            DMA_REQUEST_USART1_TX
+
+
+/* Definition for USARTx's NVIC */
+#define USARTx_DMA_TX_IRQn               DMA1_Channel1_IRQn
+#define USARTx_DMA_TX_IRQHandler         DMA1_Channel1_IRQHandler
+
+/* Definition for USARTx's NVIC */
+#define USARTx_IRQn                      USART1_IRQn
+#define USARTx_IRQHandler                USART1_IRQHandler
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+#define COUNTOF(__BUFFER__)   (sizeof(__BUFFER__) / sizeof(*(__BUFFER__)))
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..9c61c0f47
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+#define HAL_LPTIM_MODULE_ENABLED
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..ca4bfb2f5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Inc/stm32wbxx_it.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    DMA/DMAMUX_SYNC/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void DMA1_Channel1_IRQHandler(void);
+void USART1_IRQHandler(void);
+void DMAMUX1_OVR_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/MDK-ARM/DMA_MUXSYNC.uvoptx b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/MDK-ARM/DMA_MUXSYNC.uvoptx
new file mode 100644
index 000000000..c85cd95cf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/MDK-ARM/DMA_MUXSYNC.uvoptx
@@ -0,0 +1,533 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    DMA_MUXSYNC
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c
+      stm32wbxx_hal_lptim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+      stm32wbxx_hal_uart.c
+      0
+      0
+    
+    
+      6
+      24
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+      stm32wbxx_hal_uart_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      25
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/MDK-ARM/DMA_MUXSYNC.uvprojx b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/MDK-ARM/DMA_MUXSYNC.uvprojx
new file mode 100644
index 000000000..d053814e8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/MDK-ARM/DMA_MUXSYNC.uvprojx
@@ -0,0 +1,556 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      DMA_MUXSYNC
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          DMA_MUXSYNC\
+          DMA_MUXSYNC
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_lptim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_uart.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+            
+            
+              stm32wbxx_hal_uart_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..f7d74c914
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/.project
new file mode 100644
index 000000000..34a0b01df
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/.project
@@ -0,0 +1,160 @@
+
+
+	DMA_MUXSYNC
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			DMA_MUXSYNC.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/DMA_MUXSYNC.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_lptim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Src/main.c
new file mode 100644
index 000000000..e27a5782d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Src/main.c
@@ -0,0 +1,402 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    DMA/DMAMUX_SYNC/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example shows how to use the DMA with the DMAMUX to 
+  *          synchronize a transfer with LPTIM1 output period using the STM32WBxx HAL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+LPTIM_HandleTypeDef hlptim1;
+
+UART_HandleTypeDef huart1;
+DMA_HandleTypeDef hdma_usart1_tx;
+
+/* USER CODE BEGIN PV */
+uint8_t TxSyncMessage[] = "\n\r10\n\r09\n\r08\n\r07\n\r06\n\r05\n\r04\n\r03\n\r02\n\r01\n\r00";
+/* Size of Transmission buffer */
+#define TX_SYNC_MESSAGE_SIZE               (COUNTOF(TxSyncMessage) - 1)
+
+uint8_t BriefMessage[] = "This example shows how to use the DMA with the DMAMUX to synchronize a transfer with LPTIM1 output signal.\n\rThe USART1 is used in DMA synchronized mode to send a countdown from 10 to 00 with a period of 2sec \n\r\n\rStart countdown :\n\r";
+#define BRIEF_MESSAGE_SIZE               (COUNTOF(BriefMessage) - 1)
+
+uint8_t TxEndMessage[] = "\n\r\n\rExample Finished\n\r";
+#define TX_END_MESSAGE_SIZE               (COUNTOF(TxEndMessage) - 1)
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+static void MX_LPTIM1_Init(void);
+static void MX_USART1_UART_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  uint32_t periodValue;
+  uint32_t pulseValue;
+
+
+
+ 
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_LPTIM1_Init();
+  MX_USART1_UART_Init();
+  /* USER CODE BEGIN 2 */
+
+  /*##-1- Configure LED2 and LED3 ##*/
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+  
+   periodValue = (2 * LSE_VALUE)/4;    /* Calculate the Timer  Autoreload value for 2sec period */
+   pulseValue  = periodValue/2;        /* Set the Timer  pulse value for 50% duty cycle         */
+  
+  /* Start the timer */
+  if (HAL_LPTIM_PWM_Start(&hlptim1, periodValue, pulseValue) != HAL_OK)
+  {
+    Error_Handler();
+  } 
+ 
+  /*##Send Brief Message with the UART in Polling mode ######################*/
+  /* Start transmission data through "BriefMessage" buffer */
+  if(HAL_UART_Transmit(&huart1, (uint8_t*)BriefMessage, BRIEF_MESSAGE_SIZE, HAL_MAX_DELAY )!= HAL_OK)
+  {
+    /* Transfer error in transmission process */
+    Error_Handler();
+  }
+
+  /*## Start the synchronized transmission process #####################################*/
+  /* Start transmission of the countdown data through "TxSyncMessage" buffer */
+  if(HAL_UART_Transmit_DMA(&huart1, (uint8_t*)TxSyncMessage, TX_SYNC_MESSAGE_SIZE)!= HAL_OK)
+  {
+    /* Transfer error in transmission process */
+    Error_Handler();
+  }
+
+  /*## Wait for the end of the synchronized transfer ###################################*/
+  while (HAL_UART_GetState(&huart1) != HAL_UART_STATE_READY)
+  {
+  }
+
+  /*## Send example ending  Message with the UART in Polling mode #####################################*/
+  /* Start transmission data through "TxEndMessage" buffer */
+  if(HAL_UART_Transmit(&huart1, (uint8_t*)TxEndMessage, TX_END_MESSAGE_SIZE, HAL_MAX_DELAY )!= HAL_OK)
+  {
+    /* Transfer error in transmission process */
+    Error_Handler();
+  }
+
+  BSP_LED_On(LED2);
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure LSE Drive Capability 
+  */
+  HAL_PWR_EnableBkUpAccess();
+  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSE
+                              |RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_USART1
+                              |RCC_PERIPHCLK_LPTIM1;
+  PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+  PeriphClkInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSE;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief LPTIM1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_LPTIM1_Init(void)
+{
+
+  /* USER CODE BEGIN LPTIM1_Init 0 */
+
+  /* USER CODE END LPTIM1_Init 0 */
+
+  /* USER CODE BEGIN LPTIM1_Init 1 */
+
+  /* USER CODE END LPTIM1_Init 1 */
+  hlptim1.Instance = LPTIM1;
+  hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC;
+  hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV4;
+  hlptim1.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE;
+  hlptim1.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH;
+  hlptim1.Init.UpdateMode = LPTIM_UPDATE_ENDOFPERIOD;
+  hlptim1.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL;
+  hlptim1.Init.Input1Source = LPTIM_INPUT1SOURCE_GPIO;
+  hlptim1.Init.Input2Source = LPTIM_INPUT2SOURCE_GPIO;
+  if (HAL_LPTIM_Init(&hlptim1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN LPTIM1_Init 2 */
+
+  /* USER CODE END LPTIM1_Init 2 */
+
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+  /* DMAMUX1_OVR_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMAMUX1_OVR_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMAMUX1_OVR_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+
+  while(1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..0ea802ec1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,228 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    DMA/DMAMUX_SYNC/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_usart1_tx;
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief LPTIM MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hlptim: LPTIM handle pointer
+* @retval None
+*/
+void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim)
+{
+  if(hlptim->Instance==LPTIM1)
+  {
+  /* USER CODE BEGIN LPTIM1_MspInit 0 */
+
+  /* USER CODE END LPTIM1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_LPTIM1_CLK_ENABLE();
+  /* USER CODE BEGIN LPTIM1_MspInit 1 */
+
+  /* USER CODE END LPTIM1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief LPTIM MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hlptim: LPTIM handle pointer
+* @retval None
+*/
+void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef* hlptim)
+{
+  if(hlptim->Instance==LPTIM1)
+  {
+  /* USER CODE BEGIN LPTIM1_MspDeInit 0 */
+
+  /* USER CODE END LPTIM1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_LPTIM1_CLK_DISABLE();
+  /* USER CODE BEGIN LPTIM1_MspDeInit 1 */
+
+  /* USER CODE END LPTIM1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  HAL_DMA_MuxSyncConfigTypeDef pSyncConfig;
+  if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspInit 0 */
+
+  /* USER CODE END USART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**USART1 GPIO Configuration    
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* USART1 DMA Init */
+    /* USART1_TX Init */
+    hdma_usart1_tx.Instance = DMA1_Channel1;
+    hdma_usart1_tx.Init.Request = DMA_REQUEST_USART1_TX;
+    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    pSyncConfig.SyncSignalID = HAL_DMAMUX1_SYNC_LPTIM1_OUT;
+    pSyncConfig.SyncPolarity = HAL_DMAMUX_SYNC_RISING;
+    pSyncConfig.SyncEnable = ENABLE;
+    pSyncConfig.EventEnable = ENABLE;
+    pSyncConfig.RequestNumber = 4;
+    if (HAL_DMAEx_ConfigMuxSync(&hdma_usart1_tx, &pSyncConfig) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx);
+
+    /* USART1 interrupt Init */
+    HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspInit 1 */
+
+  /* USER CODE END USART1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+  /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+  
+    /**USART1 GPIO Configuration    
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
+
+    /* USART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmatx);
+
+    /* USART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+  /* USER CODE END USART1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..471d48029
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Src/stm32wbxx_it.c
@@ -0,0 +1,249 @@
+/* USER CODE BEGIN Header */
+
+/**
+  ******************************************************************************
+  * @file    DMA/DMAMUX_SYNC/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_usart1_tx;
+extern UART_HandleTypeDef huart1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles DMA1 channel1 global interrupt.
+  */
+void DMA1_Channel1_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel1_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart1_tx);
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+
+  /* USER CODE END USART1_IRQn 0 */
+  HAL_UART_IRQHandler(&huart1);
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMAMUX1 overrun interrupt.
+  */
+void DMAMUX1_OVR_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMAMUX1_OVR_IRQn 0 */
+
+  /* USER CODE END DMAMUX1_OVR_IRQn 0 */
+  // Handle DMA1_Channel1
+  HAL_DMAEx_MUX_IRQHandler(&hdma_usart1_tx);
+  /* USER CODE BEGIN DMAMUX1_OVR_IRQn 1 */
+
+  /* USER CODE END DMAMUX1_OVR_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/readme.txt b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/readme.txt
new file mode 100644
index 000000000..ee967c5d6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUXSYNC/readme.txt
@@ -0,0 +1,143 @@
+/**
+  @page DMAMUX_SYNC DMA & DMAMUX Synchronization Example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    DMA/DMAMUX_SYNC/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the DMA & DMAMUX Synchronization Example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to use the DMA with the DMAMUX to synchronize a transfer with the LPTIM1
+output signal. USART1 is used in DMA synchronized mode to send a countdown from
+10 to 00, with a period of 2 seconds. 
+
+The example uses the USART1 in DMA synchronized mode to send a countdown from 10 to 00 with 2sec period.
+The DMAMUX synchronization block is configured to synchronize the DMA transfer with the LPTIM1 output signal.
+Each rising edge of the synchronization signal (i.e LPTIM1 output signal) will authorize 4 USART1 requests to be
+transmitted to the the USART1 peripheral using the DMA. these four requests represent the 2 characters '\n\r' plus 
+the 2 characters count down itself from '10' to '00'.
+The LPTIM1 is configured to generate a PWM with 2 seconds period.
+
+The example requires to connect the board to an HyperTerminal PC application through Virtual Com port feature of STLINK.
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz for STM32WBxx Devices.
+
+The DMA is configured in memory to peripheral mode to ensure data transfer 
+from the source transmission buffer (TxSyncMessage) to the USART1 (in order to be transmitted to the UART/HyperTerminal).
+
+The DMAMUX synchronization block is configured using function "HAL_DMAEx_ConfigMuxSync" with the following parameters :
+- SyncSignalID  : set to HAL_DMAMUX1_SYNC_LPTIM1_OUT which corresponds to LPTIM1_OUT signal.
+- SyncPolarity  : Set to RISING to use rising edge of LPTIM1 output signal for synchronization.
+- RequestNumber : 4 i.e four USART1 requests are authorized after each rising edge of the sync signal.
+- EventState : enabled , in order to generate an event each time "RequestNumber" are transmitted.
+  Note that this event could be used with the DMAMUX external request generator to trigger another DMA stream transfer.
+
+The LPTIM1 is configured using function  HAL_LPTIM_PWM_Start() in order to configure and start a PWM on the LPTIM1 timer with
+2 seconds period and 50% duty cycle.
+The USART1 peripheral configuration is ensured by the HAL_UART_Init() function.
+This later is calling the HAL_UART_MspInit()function which core is implementing
+the configuration of the needed UART resources according to the used hardware (CLOCK, 
+GPIO and NVIC). 
+DMA & DMAMUX configurations are performed in the main.c module as the example first purpose is to show 
+the DMA & DMAMUX configuration when using the DMAMUX synchronization block. 
+In normal conditions DMA and DMAMUX configuration should be placed in the HAL_UART_MspInit()function.
+
+A first example brief description message is then transmitted using the USART1 to the PC HyperTerminal
+in Polling mode (using message buffer ).
+
+Then a second UART transfer is started in DMA synchronized mode to transfer the countdown buffer "TxEndMessage".
+As result the countdown from 10 to 00 with a period of 2 seconds should be displayed on the HyperTerminal. 
+The end of this step is monitored through the HAL_UART_GetState() function result.
+
+In the last step an ending message is sent using the USART1 in polling mode through the "TxEndMessage" buffer.  
+
+NUCLEO-WB35CE board's LEDs can be used to monitor the transfer status:
+ - LED2 is ON when the transmission process is complete.
+ - LED3 is ON when there is an error in transmission process.
+
+The UART is configured as follows:
+    - BaudRate = 115200 baud  
+    - Word Length = 8 Bits
+    - One Stop Bit
+    - parity none
+    - Hardware flow control disabled (RTS and CTS signals)
+
+@note USARTx/UARTx instance used and associated resources can be updated in "main.h"
+file depending hardware configuration used.
+
+@note This example can be easily modified to use any other peripheral (than the USART1) with a DMA synchronized transfer.
+In this case user will need to replace the USART1 initialization and processing by the used IP initialization and processing functions.
+User can also change the synchronization signal (based on the sync signals list available in the reference manual),
+in this case the sync signal IP should be configured (replacing the function LPTIM_Config by the required sync signal IP configuration)
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+	  
+@par Keywords
+
+System, DMA, DMAMUX, LPTIM, USART, Data Transfer, Memory to periph, synchronization
+
+@par Directory contents 
+
+  - DMA/DMAMUX_SYNC/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - DMA/DMAMUX_SYNC/Inc/stm32wbxx_it.h          DMA interrupt handlers header file
+  - DMA/DMAMUX_SYNC/Inc/main.h                  Header for main.c module  
+  - DMA/DMAMUX_SYNC/Src/stm32wbxx_it.c          DMA interrupt handlers
+  - DMA/DMAMUX_SYNC/Src/main.c                  Main program
+  - DMA/DMAMUX_SYNC/Src/stm32wbxx_hal_msp.c     HAL MSP module
+  - DMA/DMAMUX_SYNC/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WBxx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+  - NUCLEO-WB35CE Set-up
+    Example is delivered for using Virtual Com port feature of STLINK for connection between NUCLEO-WB35CE and PC,
+    Please ensure that USART communication between the target MCU and ST-LINK MCU is properly enabled 
+    on HW board in order to support Virtual Com Port (Default HW SB configuration allows use of VCP)
+    GPIOs connected to USART1 TX/RX (PB.06 and PB.07) are automatically mapped
+    on RX and TX pins of PC UART Com port selected on PC side (please ensure VCP com port is selected).
+
+  - Launch serial communication SW on PC (as HyperTerminal or TeraTerm) with proper configuration 
+    - Word Length = 8 Bits
+    - One Stop Bit
+    - None parity
+    - Baud Rate = 115200 baud
+    - flow control: None 
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/.extSettings b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/DMA_MUX_RequestGen.ioc b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/DMA_MUX_RequestGen.ioc
new file mode 100644
index 000000000..54b7ca4c2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/DMA_MUX_RequestGen.ioc
@@ -0,0 +1,106 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=DMA_MUX_RequestGen.ioc
+ProjectManager.ProjectName=DMA_MUX_RequestGen
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/DMA_MUX_RequestGen.ewd b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/DMA_MUX_RequestGen.ewd
new file mode 100644
index 000000000..8f9143052
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/DMA_MUX_RequestGen.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		DMA_MUX_RequestGen
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/DMA_MUX_RequestGen.ewp b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/DMA_MUX_RequestGen.ewp
new file mode 100644
index 000000000..97f0894bb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/DMA_MUX_RequestGen.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    DMA_MUX_RequestGen
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/Project.eww
new file mode 100644
index 000000000..d6be0687b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\DMA_MUX_RequestGen.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Inc/main.h
new file mode 100644
index 000000000..0c1486c5e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Inc/main.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    DMA/DMAMUX_RequestGen/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+/* Definition for DMA1 clock resources */
+#define DMAx_CLK_ENABLE()                do {                                \
+                                            __HAL_RCC_DMA1_CLK_ENABLE();    \
+                                            __HAL_RCC_DMAMUX1_CLK_ENABLE(); \
+                                        }while(0)
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..19d12a61f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..a806f5981
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Inc/stm32wbxx_it.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    DMA/DMAMUX_RequestGen/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void EXTI0_IRQHandler(void);
+void DMA1_Channel1_IRQHandler(void);
+void DMAMUX1_OVR_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/MDK-ARM/DMA_MUX_RequestGen.uvoptx b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/MDK-ARM/DMA_MUX_RequestGen.uvoptx
new file mode 100644
index 000000000..4087415c2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/MDK-ARM/DMA_MUX_RequestGen.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    DMA_MUX_RequestGen
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      2
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      5
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      5
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      5
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      5
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      5
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      5
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      5
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      5
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      5
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      5
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/MDK-ARM/DMA_MUX_RequestGen.uvprojx b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/MDK-ARM/DMA_MUX_RequestGen.uvprojx
new file mode 100644
index 000000000..728989d29
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/MDK-ARM/DMA_MUX_RequestGen.uvprojx
@@ -0,0 +1,542 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      DMA_MUX_RequestGen
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          DMA_MUX_RequestGen\
+          DMA_MUX_RequestGen
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..381446a4e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/.project
new file mode 100644
index 000000000..69f80306d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	DMA_MUX_RequestGen
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			DMA_MUX_RequestGen.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/DMA_MUX_RequestGen.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Src/main.c
new file mode 100644
index 000000000..7fb85b90c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Src/main.c
@@ -0,0 +1,262 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    DMA/DMAMUX_RequestGen/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example shows how to use the DMA with the DMAMUX to 
+  *          request generator using the STM32WBxx HAL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */ 
+
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+__IO   uint32_t DMA_TransferErrorFlag = 0;
+
+uint32_t SRC_Buffer_LED2_Toggle[2]  =
+                                      {  0,          /*Value for LED2 ON  */
+                                         LED2_PIN    /*Value for LED2 OFF */  
+                                      };
+
+DMA_HandleTypeDef DMA_Handle;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+static void HAL_TransferError(DMA_HandleTypeDef *hdma);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  HAL_DMA_MuxRequestGeneratorConfigTypeDef dmamux_ReqGenParams;
+  
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+  /* -1- Initialize LEDs mounted on NUCLEO-WB35CE board */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+
+  /*##-2- Configure the DMA ##################################################*/
+  /* Enable DMA1 clock */
+  DMAx_CLK_ENABLE();
+
+  /* Configure the DMA handler for Transmission process     */
+  /* DMA mode is set to circular for an infinite DMA transfer */
+  DMA_Handle.Instance                 = DMA1_Channel1;
+
+  DMA_Handle.Init.Request             = DMA_REQUEST_GENERATOR0;
+  DMA_Handle.Init.Direction           = DMA_MEMORY_TO_PERIPH;
+  DMA_Handle.Init.PeriphInc           = DMA_PINC_DISABLE;
+  DMA_Handle.Init.MemInc              = DMA_MINC_ENABLE;
+  DMA_Handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
+  DMA_Handle.Init.MemDataAlignment    = DMA_MDATAALIGN_WORD;
+  DMA_Handle.Init.Mode                = DMA_CIRCULAR;
+  DMA_Handle.Init.Priority            = DMA_PRIORITY_LOW;
+
+  /* Initialize the DMA with for Transmission process */
+  HAL_DMA_Init(&DMA_Handle);
+
+  /* Register Error Callback */
+  HAL_DMA_RegisterCallback(&DMA_Handle, HAL_DMA_XFER_ERROR_CB_ID, &HAL_TransferError);
+
+  /* NVIC configuration for DMA transfer complete interrupt*/
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 1);
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+
+  /*##-3- Configure and enable the DMAMUX Request generator  ####################*/
+  dmamux_ReqGenParams.SignalID  = HAL_DMAMUX1_REQ_GEN_EXTI0;    /* External request signal is EXTI0 signal */
+  dmamux_ReqGenParams.Polarity  = HAL_DMAMUX_REQ_GEN_RISING;    /* External request signal edge is Rising  */
+  dmamux_ReqGenParams.RequestNumber = 1;                        /* 1 requests on each edge of the external request signal  */
+
+  HAL_DMAEx_ConfigMuxRequestGenerator(&DMA_Handle, &dmamux_ReqGenParams);
+  
+  /* NVIC configuration for DMAMUX request generator overrun errors*/
+  HAL_NVIC_SetPriority(DMAMUX1_OVR_IRQn, 0, 1);
+  HAL_NVIC_EnableIRQ(DMAMUX1_OVR_IRQn);
+  HAL_DMAEx_EnableMuxRequestGenerator (&DMA_Handle);
+
+  /*##-4- Configure and enable the User push-button (SW1) in EXTI mode used as DMA external request signal #####*/
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+
+  /*##-5- Start the DMA transfer ################################################*/
+  /* DMA source buffer is SRC_BUFFER_LED2_TOGGLE containing values to be written 
+  to LED2 GPIO ODR register in order to turn LED2 On/Off each time comes a request from the DMAMUX request generator */  
+  HAL_DMA_Start_IT(&DMA_Handle, (uint32_t)SRC_Buffer_LED2_Toggle, (uint32_t)&LED2_GPIO_PORT->ODR, 2);
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+   if(DMA_TransferErrorFlag != 0)
+    {
+      Error_Handler();
+    }
+ 
+
+  }
+   
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  This function is executed in case of DMA error occurrence.
+  * @param  None
+  * @retval None
+  */
+static void HAL_TransferError(DMA_HandleTypeDef *hdma)
+{
+  DMA_TransferErrorFlag = 1;
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+
+  while(1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..a44a9a3c6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,83 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    DMA/DMAMUX_RequestGen/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..d169b70ca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Src/stm32wbxx_it.c
@@ -0,0 +1,213 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    DMA/DMAMUX_RequestGen/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+extern DMA_HandleTypeDef DMA_Handle;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles External line 0 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+
+/**
+  * @brief  This function handles DMA1_Channel1 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void DMA1_Channel1_IRQHandler(void)
+{
+  HAL_DMA_IRQHandler(&DMA_Handle);
+}
+
+/**
+  * @brief  This function handles DMAMUX1 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void DMAMUX1_OVR_IRQHandler(void)
+{
+  HAL_DMAEx_MUX_IRQHandler(&DMA_Handle);
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/readme.txt b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/readme.txt
new file mode 100644
index 000000000..cbfdbe375
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/DMA/DMA_MUX_RequestGen/readme.txt
@@ -0,0 +1,104 @@
+/**
+  @page DMAMUX_RequestGen DMA & DMAMUX request generator Example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    DMA/DMAMUX_RequestGen/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the DMA & request generator Example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to use the DMA with the DMAMUX request generator to generate DMA transfer
+requests upon an External line 0 rising edge signal.
+
+The example uses the DMA1_Channel1 configured in memory to peripheral mode.
+The DMA request is set to the DMAMUX request generator 0.
+
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz for STM32WBxx Devices.
+
+The DMA1_Channel1 is configured in memory to peripheral mode to ensure data transfer from the source transmission 
+buffer (SRC_Buffer_LED2_Toggle) to the LED2 GPIO ODR register (in order to toggle LED2).
+The DMA is configured in circular mode so the transfer will restart automatically each time the amount of data 
+to be transmitted has been reached.
+
+The DMAMUX request generator block is configured using function "HAL_DMAEx_ConfigMuxRequestGenerator" 
+with the following parameters :
+- SignalID      : set to HAL_DMAMUX1_REQ_GEN_EXTI0 which corresponds to External line 0 signal.
+- Polarity  : Set to RISING to use rising edge the External line 0 for DMA requests generation.
+- RequestNumber : 1 i.e on each rising edge of the External line 0 signal a DMA request is generated.
+
+The DMA request generator is then enabled using function "HAL_DMAEx_EnableMuxRequestGenerator".
+
+The function BSP_PB_Init is then used to configure the PA.00 pin to  
+external Interrupt Mode with Rising edge trigger detection. 
+
+Then the DMA transfer is started in non-blocking mode using the HAL function "HAL_DMA_Start_IT"
+Note that PA.00 pin is connected to the User push-button (SW1) of the board.
+Each time the User push-button (SW1) is pressed an External line 0 event is generated and the DMAMUX will generate a DMA request
+upon the rising edge of the External line 0 signal.
+As consequence the DMA will serve the request and write a new value to the LED2 GPIO ODR register to toggle the LED2 
+without any CPU intervention.
+
+The CPU is only used to intercept a DMA transfer interrupt error or a DMAMUX overrun interrupt error if any.
+Then it sets the LED3 (Red LED) to On in this case.
+
+
+NUCLEO-WB35CE board's LEDs can be used to monitor the transfer status:
+ - LED2 toggles each time the PA.00 is pressed.
+ - LED3 is ON when there is an error during the DMA transfer.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+	  
+@par Keywords
+
+System, DMA, Data Transfer, Memory to memory, Channel, Flash
+
+@par Directory contents 
+
+  - DMA/DMAMUX_RequestGen/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - DMA/DMAMUX_RequestGen/Inc/stm32wbxx_it.h          DMA interrupt handlers header file
+  - DMA/DMAMUX_RequestGen/Inc/main.h                  Header for main.c module  
+  - DMA/DMAMUX_RequestGen/Src/stm32wbxx_it.c          DMA interrupt handlers
+  - DMA/DMAMUX_RequestGen/Src/main.c                  Main program
+  - DMA/DMAMUX_RequestGen/Src/system_stm32wbxx.c      STM32WBxx system source file
+  - DMA/DMAMUX_RequestGen/Src/stm32wbxx_hal_msp.c     HAL MSP module
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WBxx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/.extSettings b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/FLASH_EraseProgram.ewd b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/FLASH_EraseProgram.ewd
new file mode 100644
index 000000000..4695d4fad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/FLASH_EraseProgram.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		FLASH_EraseProgram
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/FLASH_EraseProgram.ewp b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/FLASH_EraseProgram.ewp
new file mode 100644
index 000000000..15a36d597
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/FLASH_EraseProgram.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    FLASH_EraseProgram
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/Project.eww
new file mode 100644
index 000000000..f7c2d132e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\FLASH_EraseProgram.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/FLASH_EraseProgram.ioc b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/FLASH_EraseProgram.ioc
new file mode 100644
index 000000000..07d173f0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/FLASH_EraseProgram.ioc
@@ -0,0 +1,106 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=FLASH_EraseProgram.ioc
+ProjectManager.ProjectName=FLASH_EraseProgram
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Inc/main.h
new file mode 100644
index 000000000..1996c37f4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Inc/main.h
@@ -0,0 +1,329 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FLASH/FLASH_EraseProgram/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+/* Base address of the Flash s */
+
+#define ADDR_FLASH_PAGE_0     ((uint32_t)0x08000000) /* Base @ of Page 0, 4 Kbytes */
+#define ADDR_FLASH_PAGE_1     ((uint32_t)0x08001000) /* Base @ of Page 1, 4 Kbytes */
+#define ADDR_FLASH_PAGE_2     ((uint32_t)0x08002000) /* Base @ of Page 2, 4 Kbytes */
+#define ADDR_FLASH_PAGE_3     ((uint32_t)0x08003000) /* Base @ of Page 3, 4 Kbytes */
+#define ADDR_FLASH_PAGE_4     ((uint32_t)0x08004000) /* Base @ of Page 4, 4 Kbytes */
+#define ADDR_FLASH_PAGE_5     ((uint32_t)0x08005000) /* Base @ of Page 5, 4 Kbytes */
+#define ADDR_FLASH_PAGE_6     ((uint32_t)0x08006000) /* Base @ of Page 6, 4 Kbytes */
+#define ADDR_FLASH_PAGE_7     ((uint32_t)0x08007000) /* Base @ of Page 7, 4 Kbytes */
+#define ADDR_FLASH_PAGE_8     ((uint32_t)0x08008000) /* Base @ of Page 8, 4 Kbytes */
+#define ADDR_FLASH_PAGE_9     ((uint32_t)0x08009000) /* Base @ of Page 9, 4 Kbytes */
+#define ADDR_FLASH_PAGE_10    ((uint32_t)0x0800A000) /* Base @ of Page 10, 4 Kbytes */
+#define ADDR_FLASH_PAGE_11    ((uint32_t)0x0800B000) /* Base @ of Page 11, 4 Kbytes */
+#define ADDR_FLASH_PAGE_12    ((uint32_t)0x0800C000) /* Base @ of Page 12, 4 Kbytes */
+#define ADDR_FLASH_PAGE_13    ((uint32_t)0x0800D000) /* Base @ of Page 13, 4 Kbytes */
+#define ADDR_FLASH_PAGE_14    ((uint32_t)0x0800E000) /* Base @ of Page 14, 4 Kbytes */
+#define ADDR_FLASH_PAGE_15    ((uint32_t)0x0800F000) /* Base @ of Page 15, 4 Kbytes */
+#define ADDR_FLASH_PAGE_16    ((uint32_t)0x08010000) /* Base @ of Page 16, 4 Kbytes */
+#define ADDR_FLASH_PAGE_17    ((uint32_t)0x08011000) /* Base @ of Page 17, 4 Kbytes */
+#define ADDR_FLASH_PAGE_18    ((uint32_t)0x08012000) /* Base @ of Page 18, 4 Kbytes */
+#define ADDR_FLASH_PAGE_19    ((uint32_t)0x08013000) /* Base @ of Page 19, 4 Kbytes */
+#define ADDR_FLASH_PAGE_20    ((uint32_t)0x08014000) /* Base @ of Page 20, 4 Kbytes */
+#define ADDR_FLASH_PAGE_21    ((uint32_t)0x08015000) /* Base @ of Page 21, 4 Kbytes */
+#define ADDR_FLASH_PAGE_22    ((uint32_t)0x08016000) /* Base @ of Page 22, 4 Kbytes */
+#define ADDR_FLASH_PAGE_23    ((uint32_t)0x08017000) /* Base @ of Page 23, 4 Kbytes */
+#define ADDR_FLASH_PAGE_24    ((uint32_t)0x08018000) /* Base @ of Page 24, 4 Kbytes */
+#define ADDR_FLASH_PAGE_25    ((uint32_t)0x08019000) /* Base @ of Page 25, 4 Kbytes */
+#define ADDR_FLASH_PAGE_26    ((uint32_t)0x0801A000) /* Base @ of Page 26, 4 Kbytes */
+#define ADDR_FLASH_PAGE_27    ((uint32_t)0x0801B000) /* Base @ of Page 27, 4 Kbytes */
+#define ADDR_FLASH_PAGE_28    ((uint32_t)0x0801C000) /* Base @ of Page 28, 4 Kbytes */
+#define ADDR_FLASH_PAGE_29    ((uint32_t)0x0801D000) /* Base @ of Page 29, 4 Kbytes */
+#define ADDR_FLASH_PAGE_30    ((uint32_t)0x0801E000) /* Base @ of Page 30, 4 Kbytes */
+#define ADDR_FLASH_PAGE_31    ((uint32_t)0x0801F000) /* Base @ of Page 31, 4 Kbytes */
+#define ADDR_FLASH_PAGE_32    ((uint32_t)0x08020000) /* Base @ of Page 32, 4 Kbytes */
+#define ADDR_FLASH_PAGE_33    ((uint32_t)0x08021000) /* Base @ of Page 33, 4 Kbytes */
+#define ADDR_FLASH_PAGE_34    ((uint32_t)0x08022000) /* Base @ of Page 34, 4 Kbytes */
+#define ADDR_FLASH_PAGE_35    ((uint32_t)0x08023000) /* Base @ of Page 35, 4 Kbytes */
+#define ADDR_FLASH_PAGE_36    ((uint32_t)0x08024000) /* Base @ of Page 36, 4 Kbytes */
+#define ADDR_FLASH_PAGE_37    ((uint32_t)0x08025000) /* Base @ of Page 37, 4 Kbytes */
+#define ADDR_FLASH_PAGE_38    ((uint32_t)0x08026000) /* Base @ of Page 38, 4 Kbytes */
+#define ADDR_FLASH_PAGE_39    ((uint32_t)0x08027000) /* Base @ of Page 39, 4 Kbytes */
+#define ADDR_FLASH_PAGE_40    ((uint32_t)0x08028000) /* Base @ of Page 40, 4 Kbytes */
+#define ADDR_FLASH_PAGE_41    ((uint32_t)0x08029000) /* Base @ of Page 41, 4 Kbytes */
+#define ADDR_FLASH_PAGE_42    ((uint32_t)0x0802A000) /* Base @ of Page 42, 4 Kbytes */
+#define ADDR_FLASH_PAGE_43    ((uint32_t)0x0802B000) /* Base @ of Page 43, 4 Kbytes */
+#define ADDR_FLASH_PAGE_44    ((uint32_t)0x0802C000) /* Base @ of Page 44, 4 Kbytes */
+#define ADDR_FLASH_PAGE_45    ((uint32_t)0x0802D000) /* Base @ of Page 45, 4 Kbytes */
+#define ADDR_FLASH_PAGE_46    ((uint32_t)0x0802E000) /* Base @ of Page 46, 4 Kbytes */
+#define ADDR_FLASH_PAGE_47    ((uint32_t)0x0802F000) /* Base @ of Page 47, 4 Kbytes */
+#define ADDR_FLASH_PAGE_48    ((uint32_t)0x08030000) /* Base @ of Page 48, 4 Kbytes */
+#define ADDR_FLASH_PAGE_49    ((uint32_t)0x08031000) /* Base @ of Page 49, 4 Kbytes */
+#define ADDR_FLASH_PAGE_50    ((uint32_t)0x08032000) /* Base @ of Page 50, 4 Kbytes */
+#define ADDR_FLASH_PAGE_51    ((uint32_t)0x08033000) /* Base @ of Page 51, 4 Kbytes */
+#define ADDR_FLASH_PAGE_52    ((uint32_t)0x08034000) /* Base @ of Page 52, 4 Kbytes */
+#define ADDR_FLASH_PAGE_53    ((uint32_t)0x08035000) /* Base @ of Page 53, 4 Kbytes */
+#define ADDR_FLASH_PAGE_54    ((uint32_t)0x08036000) /* Base @ of Page 54, 4 Kbytes */
+#define ADDR_FLASH_PAGE_55    ((uint32_t)0x08037000) /* Base @ of Page 55, 4 Kbytes */
+#define ADDR_FLASH_PAGE_56    ((uint32_t)0x08038000) /* Base @ of Page 56, 4 Kbytes */
+#define ADDR_FLASH_PAGE_57    ((uint32_t)0x08039000) /* Base @ of Page 57, 4 Kbytes */
+#define ADDR_FLASH_PAGE_58    ((uint32_t)0x0803A000) /* Base @ of Page 58, 4 Kbytes */
+#define ADDR_FLASH_PAGE_59    ((uint32_t)0x0803B000) /* Base @ of Page 59, 4 Kbytes */
+#define ADDR_FLASH_PAGE_60    ((uint32_t)0x0803C000) /* Base @ of Page 60, 4 Kbytes */
+#define ADDR_FLASH_PAGE_61    ((uint32_t)0x0803D000) /* Base @ of Page 61, 4 Kbytes */
+#define ADDR_FLASH_PAGE_62    ((uint32_t)0x0803E000) /* Base @ of Page 62, 4 Kbytes */
+#define ADDR_FLASH_PAGE_63    ((uint32_t)0x0803F000) /* Base @ of Page 63, 4 Kbytes */
+#define ADDR_FLASH_PAGE_64    ((uint32_t)0x08040000) /* Base @ of Page 64, 4 Kbytes */
+#define ADDR_FLASH_PAGE_65    ((uint32_t)0x08041000) /* Base @ of Page 65, 4 Kbytes */
+#define ADDR_FLASH_PAGE_66    ((uint32_t)0x08042000) /* Base @ of Page 66, 4 Kbytes */
+#define ADDR_FLASH_PAGE_67    ((uint32_t)0x08043000) /* Base @ of Page 67, 4 Kbytes */
+#define ADDR_FLASH_PAGE_68    ((uint32_t)0x08044000) /* Base @ of Page 68, 4 Kbytes */
+#define ADDR_FLASH_PAGE_69    ((uint32_t)0x08045000) /* Base @ of Page 69, 4 Kbytes */
+#define ADDR_FLASH_PAGE_70    ((uint32_t)0x08046000) /* Base @ of Page 70, 4 Kbytes */
+#define ADDR_FLASH_PAGE_71    ((uint32_t)0x08047000) /* Base @ of Page 71, 4 Kbytes */
+#define ADDR_FLASH_PAGE_72    ((uint32_t)0x08048000) /* Base @ of Page 72, 4 Kbytes */
+#define ADDR_FLASH_PAGE_73    ((uint32_t)0x08049000) /* Base @ of Page 73, 4 Kbytes */
+#define ADDR_FLASH_PAGE_74    ((uint32_t)0x0804A000) /* Base @ of Page 74, 4 Kbytes */
+#define ADDR_FLASH_PAGE_75    ((uint32_t)0x0804B000) /* Base @ of Page 75, 4 Kbytes */
+#define ADDR_FLASH_PAGE_76    ((uint32_t)0x0804C000) /* Base @ of Page 76, 4 Kbytes */
+#define ADDR_FLASH_PAGE_77    ((uint32_t)0x0804D000) /* Base @ of Page 77, 4 Kbytes */
+#define ADDR_FLASH_PAGE_78    ((uint32_t)0x0804E000) /* Base @ of Page 78, 4 Kbytes */
+#define ADDR_FLASH_PAGE_79    ((uint32_t)0x0804F000) /* Base @ of Page 79, 4 Kbytes */
+#define ADDR_FLASH_PAGE_80    ((uint32_t)0x08050000) /* Base @ of Page 80, 4 Kbytes */
+#define ADDR_FLASH_PAGE_81    ((uint32_t)0x08051000) /* Base @ of Page 81, 4 Kbytes */
+#define ADDR_FLASH_PAGE_82    ((uint32_t)0x08052000) /* Base @ of Page 82, 4 Kbytes */
+#define ADDR_FLASH_PAGE_83    ((uint32_t)0x08053000) /* Base @ of Page 83, 4 Kbytes */
+#define ADDR_FLASH_PAGE_84    ((uint32_t)0x08054000) /* Base @ of Page 84, 4 Kbytes */
+#define ADDR_FLASH_PAGE_85    ((uint32_t)0x08055000) /* Base @ of Page 85, 4 Kbytes */
+#define ADDR_FLASH_PAGE_86    ((uint32_t)0x08056000) /* Base @ of Page 86, 4 Kbytes */
+#define ADDR_FLASH_PAGE_87    ((uint32_t)0x08057000) /* Base @ of Page 87, 4 Kbytes */
+#define ADDR_FLASH_PAGE_88    ((uint32_t)0x08058000) /* Base @ of Page 88, 4 Kbytes */
+#define ADDR_FLASH_PAGE_89    ((uint32_t)0x08059000) /* Base @ of Page 89, 4 Kbytes */
+#define ADDR_FLASH_PAGE_90    ((uint32_t)0x0805A000) /* Base @ of Page 90, 4 Kbytes */
+#define ADDR_FLASH_PAGE_91    ((uint32_t)0x0805B000) /* Base @ of Page 91, 4 Kbytes */
+#define ADDR_FLASH_PAGE_92    ((uint32_t)0x0805C000) /* Base @ of Page 92, 4 Kbytes */
+#define ADDR_FLASH_PAGE_93    ((uint32_t)0x0805D000) /* Base @ of Page 93, 4 Kbytes */
+#define ADDR_FLASH_PAGE_94    ((uint32_t)0x0805E000) /* Base @ of Page 94, 4 Kbytes */
+#define ADDR_FLASH_PAGE_95    ((uint32_t)0x0805F000) /* Base @ of Page 95, 4 Kbytes */
+#define ADDR_FLASH_PAGE_96    ((uint32_t)0x08060000) /* Base @ of Page 96, 4 Kbytes */
+#define ADDR_FLASH_PAGE_97    ((uint32_t)0x08061000) /* Base @ of Page 97, 4 Kbytes */
+#define ADDR_FLASH_PAGE_98    ((uint32_t)0x08062000) /* Base @ of Page 98, 4 Kbytes */
+#define ADDR_FLASH_PAGE_99    ((uint32_t)0x08063000) /* Base @ of Page 99, 4 Kbytes */
+#define ADDR_FLASH_PAGE_100   ((uint32_t)0x08064000) /* Base @ of Page 100, 4 Kbytes */
+#define ADDR_FLASH_PAGE_101   ((uint32_t)0x08065000) /* Base @ of Page 101, 4 Kbytes */
+#define ADDR_FLASH_PAGE_102   ((uint32_t)0x08066000) /* Base @ of Page 102, 4 Kbytes */
+#define ADDR_FLASH_PAGE_103   ((uint32_t)0x08067000) /* Base @ of Page 103, 4 Kbytes */
+#define ADDR_FLASH_PAGE_104   ((uint32_t)0x08068000) /* Base @ of Page 104, 4 Kbytes */
+#define ADDR_FLASH_PAGE_105   ((uint32_t)0x08069000) /* Base @ of Page 105, 4 Kbytes */
+#define ADDR_FLASH_PAGE_106   ((uint32_t)0x0806A000) /* Base @ of Page 106, 4 Kbytes */
+#define ADDR_FLASH_PAGE_107   ((uint32_t)0x0806B000) /* Base @ of Page 107, 4 Kbytes */
+#define ADDR_FLASH_PAGE_108   ((uint32_t)0x0806C000) /* Base @ of Page 108, 4 Kbytes */
+#define ADDR_FLASH_PAGE_109   ((uint32_t)0x0806D000) /* Base @ of Page 109, 4 Kbytes */
+#define ADDR_FLASH_PAGE_110   ((uint32_t)0x0806E000) /* Base @ of Page 110, 4 Kbytes */
+#define ADDR_FLASH_PAGE_111   ((uint32_t)0x0806F000) /* Base @ of Page 111, 4 Kbytes */
+#define ADDR_FLASH_PAGE_112   ((uint32_t)0x08070000) /* Base @ of Page 112, 4 Kbytes */
+#define ADDR_FLASH_PAGE_113   ((uint32_t)0x08071000) /* Base @ of Page 113, 4 Kbytes */
+#define ADDR_FLASH_PAGE_114   ((uint32_t)0x08072000) /* Base @ of Page 114, 4 Kbytes */
+#define ADDR_FLASH_PAGE_115   ((uint32_t)0x08073000) /* Base @ of Page 115, 4 Kbytes */
+#define ADDR_FLASH_PAGE_116   ((uint32_t)0x08074000) /* Base @ of Page 116, 4 Kbytes */
+#define ADDR_FLASH_PAGE_117   ((uint32_t)0x08075000) /* Base @ of Page 117, 4 Kbytes */
+#define ADDR_FLASH_PAGE_118   ((uint32_t)0x08076000) /* Base @ of Page 118, 4 Kbytes */
+#define ADDR_FLASH_PAGE_119   ((uint32_t)0x08077000) /* Base @ of Page 119, 4 Kbytes */
+#define ADDR_FLASH_PAGE_120   ((uint32_t)0x08078000) /* Base @ of Page 120, 4 Kbytes */
+#define ADDR_FLASH_PAGE_121   ((uint32_t)0x08079000) /* Base @ of Page 121, 4 Kbytes */
+#define ADDR_FLASH_PAGE_122   ((uint32_t)0x0807A000) /* Base @ of Page 122, 4 Kbytes */
+#define ADDR_FLASH_PAGE_123   ((uint32_t)0x0807B000) /* Base @ of Page 123, 4 Kbytes */
+#define ADDR_FLASH_PAGE_124   ((uint32_t)0x0807C000) /* Base @ of Page 124, 4 Kbytes */
+#define ADDR_FLASH_PAGE_125   ((uint32_t)0x0807D000) /* Base @ of Page 125, 4 Kbytes */
+#define ADDR_FLASH_PAGE_126   ((uint32_t)0x0807E000) /* Base @ of Page 126, 4 Kbytes */
+#define ADDR_FLASH_PAGE_127   ((uint32_t)0x0807F000) /* Base @ of Page 127, 4 Kbytes */
+#define ADDR_FLASH_PAGE_128   ((uint32_t)0x08080000) /* Base @ of Page 128, 4 Kbytes */
+#define ADDR_FLASH_PAGE_129   ((uint32_t)0x08081000) /* Base @ of Page 129, 4 Kbytes */
+#define ADDR_FLASH_PAGE_130   ((uint32_t)0x08082000) /* Base @ of Page 130, 4 Kbytes */
+#define ADDR_FLASH_PAGE_131   ((uint32_t)0x08083000) /* Base @ of Page 131, 4 Kbytes */
+#define ADDR_FLASH_PAGE_132   ((uint32_t)0x08084000) /* Base @ of Page 132, 4 Kbytes */
+#define ADDR_FLASH_PAGE_133   ((uint32_t)0x08085000) /* Base @ of Page 133, 4 Kbytes */
+#define ADDR_FLASH_PAGE_134   ((uint32_t)0x08086000) /* Base @ of Page 134, 4 Kbytes */
+#define ADDR_FLASH_PAGE_135   ((uint32_t)0x08087000) /* Base @ of Page 135, 4 Kbytes */
+#define ADDR_FLASH_PAGE_136   ((uint32_t)0x08088000) /* Base @ of Page 136, 4 Kbytes */
+#define ADDR_FLASH_PAGE_137   ((uint32_t)0x08089000) /* Base @ of Page 137, 4 Kbytes */
+#define ADDR_FLASH_PAGE_138   ((uint32_t)0x0808A000) /* Base @ of Page 138, 4 Kbytes */
+#define ADDR_FLASH_PAGE_139   ((uint32_t)0x0808B000) /* Base @ of Page 139, 4 Kbytes */
+#define ADDR_FLASH_PAGE_140   ((uint32_t)0x0808C000) /* Base @ of Page 140, 4 Kbytes */
+#define ADDR_FLASH_PAGE_141   ((uint32_t)0x0808D000) /* Base @ of Page 141, 4 Kbytes */
+#define ADDR_FLASH_PAGE_142   ((uint32_t)0x0808E000) /* Base @ of Page 142, 4 Kbytes */
+#define ADDR_FLASH_PAGE_143   ((uint32_t)0x0808F000) /* Base @ of Page 143, 4 Kbytes */
+#define ADDR_FLASH_PAGE_144   ((uint32_t)0x08090000) /* Base @ of Page 144, 4 Kbytes */
+#define ADDR_FLASH_PAGE_145   ((uint32_t)0x08091000) /* Base @ of Page 145, 4 Kbytes */
+#define ADDR_FLASH_PAGE_146   ((uint32_t)0x08092000) /* Base @ of Page 146, 4 Kbytes */
+#define ADDR_FLASH_PAGE_147   ((uint32_t)0x08093000) /* Base @ of Page 147, 4 Kbytes */
+#define ADDR_FLASH_PAGE_148   ((uint32_t)0x08094000) /* Base @ of Page 148, 4 Kbytes */
+#define ADDR_FLASH_PAGE_149   ((uint32_t)0x08095000) /* Base @ of Page 149, 4 Kbytes */
+#define ADDR_FLASH_PAGE_150   ((uint32_t)0x08096000) /* Base @ of Page 150, 4 Kbytes */
+#define ADDR_FLASH_PAGE_151   ((uint32_t)0x08097000) /* Base @ of Page 151, 4 Kbytes */
+#define ADDR_FLASH_PAGE_152   ((uint32_t)0x08098000) /* Base @ of Page 152, 4 Kbytes */
+#define ADDR_FLASH_PAGE_153   ((uint32_t)0x08099000) /* Base @ of Page 153, 4 Kbytes */
+#define ADDR_FLASH_PAGE_154   ((uint32_t)0x0809A000) /* Base @ of Page 154, 4 Kbytes */
+#define ADDR_FLASH_PAGE_155   ((uint32_t)0x0809B000) /* Base @ of Page 155, 4 Kbytes */
+#define ADDR_FLASH_PAGE_156   ((uint32_t)0x0809C000) /* Base @ of Page 156, 4 Kbytes */
+#define ADDR_FLASH_PAGE_157   ((uint32_t)0x0809D000) /* Base @ of Page 157, 4 Kbytes */
+#define ADDR_FLASH_PAGE_158   ((uint32_t)0x0809E000) /* Base @ of Page 158, 4 Kbytes */
+#define ADDR_FLASH_PAGE_159   ((uint32_t)0x0809F000) /* Base @ of Page 159, 4 Kbytes */
+#define ADDR_FLASH_PAGE_160   ((uint32_t)0x080A0000) /* Base @ of Page 160, 4 Kbytes */
+#define ADDR_FLASH_PAGE_161   ((uint32_t)0x080A1000) /* Base @ of Page 161, 4 Kbytes */
+#define ADDR_FLASH_PAGE_162   ((uint32_t)0x080A2000) /* Base @ of Page 162, 4 Kbytes */
+#define ADDR_FLASH_PAGE_163   ((uint32_t)0x080A3000) /* Base @ of Page 163, 4 Kbytes */
+#define ADDR_FLASH_PAGE_164   ((uint32_t)0x080A4000) /* Base @ of Page 164, 4 Kbytes */
+#define ADDR_FLASH_PAGE_165   ((uint32_t)0x080A5000) /* Base @ of Page 165, 4 Kbytes */
+#define ADDR_FLASH_PAGE_166   ((uint32_t)0x080A6000) /* Base @ of Page 166, 4 Kbytes */
+#define ADDR_FLASH_PAGE_167   ((uint32_t)0x080A7000) /* Base @ of Page 167, 4 Kbytes */
+#define ADDR_FLASH_PAGE_168   ((uint32_t)0x080A8000) /* Base @ of Page 168, 4 Kbytes */
+#define ADDR_FLASH_PAGE_169   ((uint32_t)0x080A9000) /* Base @ of Page 169, 4 Kbytes */
+#define ADDR_FLASH_PAGE_170   ((uint32_t)0x080AA000) /* Base @ of Page 170, 4 Kbytes */
+#define ADDR_FLASH_PAGE_171   ((uint32_t)0x080AB000) /* Base @ of Page 171, 4 Kbytes */
+#define ADDR_FLASH_PAGE_172   ((uint32_t)0x080AC000) /* Base @ of Page 172, 4 Kbytes */
+#define ADDR_FLASH_PAGE_173   ((uint32_t)0x080AD000) /* Base @ of Page 173, 4 Kbytes */
+#define ADDR_FLASH_PAGE_174   ((uint32_t)0x080AE000) /* Base @ of Page 174, 4 Kbytes */
+#define ADDR_FLASH_PAGE_175   ((uint32_t)0x080AF000) /* Base @ of Page 175, 4 Kbytes */
+#define ADDR_FLASH_PAGE_176   ((uint32_t)0x080B0000) /* Base @ of Page 176, 4 Kbytes */
+#define ADDR_FLASH_PAGE_177   ((uint32_t)0x080B1000) /* Base @ of Page 177, 4 Kbytes */
+#define ADDR_FLASH_PAGE_178   ((uint32_t)0x080B2000) /* Base @ of Page 178, 4 Kbytes */
+#define ADDR_FLASH_PAGE_179   ((uint32_t)0x080B3000) /* Base @ of Page 179, 4 Kbytes */
+#define ADDR_FLASH_PAGE_180   ((uint32_t)0x080B4000) /* Base @ of Page 180, 4 Kbytes */
+#define ADDR_FLASH_PAGE_181   ((uint32_t)0x080B5000) /* Base @ of Page 181, 4 Kbytes */
+#define ADDR_FLASH_PAGE_182   ((uint32_t)0x080B6000) /* Base @ of Page 182, 4 Kbytes */
+#define ADDR_FLASH_PAGE_183   ((uint32_t)0x080B7000) /* Base @ of Page 183, 4 Kbytes */
+#define ADDR_FLASH_PAGE_184   ((uint32_t)0x080B8000) /* Base @ of Page 184, 4 Kbytes */
+#define ADDR_FLASH_PAGE_185   ((uint32_t)0x080B9000) /* Base @ of Page 185, 4 Kbytes */
+#define ADDR_FLASH_PAGE_186   ((uint32_t)0x080BA000) /* Base @ of Page 186, 4 Kbytes */
+#define ADDR_FLASH_PAGE_187   ((uint32_t)0x080BB000) /* Base @ of Page 187, 4 Kbytes */
+#define ADDR_FLASH_PAGE_188   ((uint32_t)0x080BC000) /* Base @ of Page 188, 4 Kbytes */
+#define ADDR_FLASH_PAGE_189   ((uint32_t)0x080BD000) /* Base @ of Page 189, 4 Kbytes */
+#define ADDR_FLASH_PAGE_190   ((uint32_t)0x080BE000) /* Base @ of Page 190, 4 Kbytes */
+#define ADDR_FLASH_PAGE_191   ((uint32_t)0x080BF000) /* Base @ of Page 191, 4 Kbytes */
+#define ADDR_FLASH_PAGE_192   ((uint32_t)0x080C0000) /* Base @ of Page 192, 4 Kbytes */
+#define ADDR_FLASH_PAGE_193   ((uint32_t)0x080C1000) /* Base @ of Page 193, 4 Kbytes */
+#define ADDR_FLASH_PAGE_194   ((uint32_t)0x080C2000) /* Base @ of Page 194, 4 Kbytes */
+#define ADDR_FLASH_PAGE_195   ((uint32_t)0x080C3000) /* Base @ of Page 195, 4 Kbytes */
+#define ADDR_FLASH_PAGE_196   ((uint32_t)0x080C4000) /* Base @ of Page 196, 4 Kbytes */
+#define ADDR_FLASH_PAGE_197   ((uint32_t)0x080C5000) /* Base @ of Page 197, 4 Kbytes */
+#define ADDR_FLASH_PAGE_198   ((uint32_t)0x080C6000) /* Base @ of Page 198, 4 Kbytes */
+#define ADDR_FLASH_PAGE_199   ((uint32_t)0x080C7000) /* Base @ of Page 199, 4 Kbytes */
+#define ADDR_FLASH_PAGE_200   ((uint32_t)0x080C8000) /* Base @ of Page 200, 4 Kbytes */
+#define ADDR_FLASH_PAGE_201   ((uint32_t)0x080C9000) /* Base @ of Page 201, 4 Kbytes */
+#define ADDR_FLASH_PAGE_202   ((uint32_t)0x080CA000) /* Base @ of Page 202, 4 Kbytes */
+#define ADDR_FLASH_PAGE_203   ((uint32_t)0x080CB000) /* Base @ of Page 203, 4 Kbytes */
+#define ADDR_FLASH_PAGE_204   ((uint32_t)0x080CC000) /* Base @ of Page 204, 4 Kbytes */
+#define ADDR_FLASH_PAGE_205   ((uint32_t)0x080CD000) /* Base @ of Page 205, 4 Kbytes */
+#define ADDR_FLASH_PAGE_206   ((uint32_t)0x080CE000) /* Base @ of Page 206, 4 Kbytes */
+#define ADDR_FLASH_PAGE_207   ((uint32_t)0x080CF000) /* Base @ of Page 207, 4 Kbytes */
+#define ADDR_FLASH_PAGE_208   ((uint32_t)0x080D0000) /* Base @ of Page 208, 4 Kbytes */
+#define ADDR_FLASH_PAGE_209   ((uint32_t)0x080D1000) /* Base @ of Page 209, 4 Kbytes */
+#define ADDR_FLASH_PAGE_210   ((uint32_t)0x080D2000) /* Base @ of Page 210, 4 Kbytes */
+#define ADDR_FLASH_PAGE_211   ((uint32_t)0x080D3000) /* Base @ of Page 211, 4 Kbytes */
+#define ADDR_FLASH_PAGE_212   ((uint32_t)0x080D4000) /* Base @ of Page 212, 4 Kbytes */
+#define ADDR_FLASH_PAGE_213   ((uint32_t)0x080D5000) /* Base @ of Page 213, 4 Kbytes */
+#define ADDR_FLASH_PAGE_214   ((uint32_t)0x080D6000) /* Base @ of Page 214, 4 Kbytes */
+#define ADDR_FLASH_PAGE_215   ((uint32_t)0x080D7000) /* Base @ of Page 215, 4 Kbytes */
+#define ADDR_FLASH_PAGE_216   ((uint32_t)0x080D8000) /* Base @ of Page 216, 4 Kbytes */
+#define ADDR_FLASH_PAGE_217   ((uint32_t)0x080D9000) /* Base @ of Page 217, 4 Kbytes */
+#define ADDR_FLASH_PAGE_218   ((uint32_t)0x080DA000) /* Base @ of Page 218, 4 Kbytes */
+#define ADDR_FLASH_PAGE_219   ((uint32_t)0x080DB000) /* Base @ of Page 219, 4 Kbytes */
+#define ADDR_FLASH_PAGE_220   ((uint32_t)0x080DC000) /* Base @ of Page 220, 4 Kbytes */
+#define ADDR_FLASH_PAGE_221   ((uint32_t)0x080DD000) /* Base @ of Page 221, 4 Kbytes */
+#define ADDR_FLASH_PAGE_222   ((uint32_t)0x080DE000) /* Base @ of Page 222, 4 Kbytes */
+#define ADDR_FLASH_PAGE_223   ((uint32_t)0x080DF000) /* Base @ of Page 223, 4 Kbytes */
+#define ADDR_FLASH_PAGE_224   ((uint32_t)0x080E0000) /* Base @ of Page 224, 4 Kbytes */
+#define ADDR_FLASH_PAGE_225   ((uint32_t)0x080E1000) /* Base @ of Page 225, 4 Kbytes */
+#define ADDR_FLASH_PAGE_226   ((uint32_t)0x080E2000) /* Base @ of Page 226, 4 Kbytes */
+#define ADDR_FLASH_PAGE_227   ((uint32_t)0x080E3000) /* Base @ of Page 227, 4 Kbytes */
+#define ADDR_FLASH_PAGE_228   ((uint32_t)0x080E4000) /* Base @ of Page 228, 4 Kbytes */
+#define ADDR_FLASH_PAGE_229   ((uint32_t)0x080E5000) /* Base @ of Page 229, 4 Kbytes */
+#define ADDR_FLASH_PAGE_230   ((uint32_t)0x080E6000) /* Base @ of Page 230, 4 Kbytes */
+#define ADDR_FLASH_PAGE_231   ((uint32_t)0x080E7000) /* Base @ of Page 231, 4 Kbytes */
+#define ADDR_FLASH_PAGE_232   ((uint32_t)0x080E8000) /* Base @ of Page 232, 4 Kbytes */
+#define ADDR_FLASH_PAGE_233   ((uint32_t)0x080E9000) /* Base @ of Page 233, 4 Kbytes */
+#define ADDR_FLASH_PAGE_234   ((uint32_t)0x080EA000) /* Base @ of Page 234, 4 Kbytes */
+#define ADDR_FLASH_PAGE_235   ((uint32_t)0x080EB000) /* Base @ of Page 235, 4 Kbytes */
+#define ADDR_FLASH_PAGE_236   ((uint32_t)0x080EC000) /* Base @ of Page 236, 4 Kbytes */
+#define ADDR_FLASH_PAGE_237   ((uint32_t)0x080ED000) /* Base @ of Page 237, 4 Kbytes */
+#define ADDR_FLASH_PAGE_238   ((uint32_t)0x080EE000) /* Base @ of Page 238, 4 Kbytes */
+#define ADDR_FLASH_PAGE_239   ((uint32_t)0x080EF000) /* Base @ of Page 239, 4 Kbytes */
+#define ADDR_FLASH_PAGE_240   ((uint32_t)0x080F0000) /* Base @ of Page 240, 4 Kbytes */
+#define ADDR_FLASH_PAGE_241   ((uint32_t)0x080F1000) /* Base @ of Page 241, 4 Kbytes */
+#define ADDR_FLASH_PAGE_242   ((uint32_t)0x080F2000) /* Base @ of Page 242, 4 Kbytes */
+#define ADDR_FLASH_PAGE_243   ((uint32_t)0x080F3000) /* Base @ of Page 243, 4 Kbytes */
+#define ADDR_FLASH_PAGE_244   ((uint32_t)0x080F4000) /* Base @ of Page 244, 4 Kbytes */
+#define ADDR_FLASH_PAGE_245   ((uint32_t)0x080F5000) /* Base @ of Page 245, 4 Kbytes */
+#define ADDR_FLASH_PAGE_246   ((uint32_t)0x080F6000) /* Base @ of Page 246, 4 Kbytes */
+#define ADDR_FLASH_PAGE_247   ((uint32_t)0x080F7000) /* Base @ of Page 247, 4 Kbytes */
+#define ADDR_FLASH_PAGE_248   ((uint32_t)0x080F8000) /* Base @ of Page 248, 4 Kbytes */
+#define ADDR_FLASH_PAGE_249   ((uint32_t)0x080F9000) /* Base @ of Page 249, 4 Kbytes */
+#define ADDR_FLASH_PAGE_250   ((uint32_t)0x080FA000) /* Base @ of Page 250, 4 Kbytes */
+#define ADDR_FLASH_PAGE_251   ((uint32_t)0x080FB000) /* Base @ of Page 251, 4 Kbytes */
+#define ADDR_FLASH_PAGE_252   ((uint32_t)0x080FC000) /* Base @ of Page 252, 4 Kbytes */
+#define ADDR_FLASH_PAGE_253   ((uint32_t)0x080FD000) /* Base @ of Page 253, 4 Kbytes */
+#define ADDR_FLASH_PAGE_254   ((uint32_t)0x080FE000) /* Base @ of Page 254, 4 Kbytes */
+#define ADDR_FLASH_PAGE_255   ((uint32_t)0x080FF000) /* Base @ of Page 255, 4 Kbytes */
+      
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..19d12a61f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..a024bbc06
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Inc/stm32wbxx_it.h
@@ -0,0 +1,64 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FLASH/FLASH_EraseProgram/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/MDK-ARM/FLASH_EraseProgram.uvoptx b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/MDK-ARM/FLASH_EraseProgram.uvoptx
new file mode 100644
index 000000000..569887c87
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/MDK-ARM/FLASH_EraseProgram.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    FLASH_EraseProgram
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/MDK-ARM/FLASH_EraseProgram.uvprojx b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/MDK-ARM/FLASH_EraseProgram.uvprojx
new file mode 100644
index 000000000..535585860
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/MDK-ARM/FLASH_EraseProgram.uvprojx
@@ -0,0 +1,541 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      FLASH_EraseProgram
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          FLASH_EraseProgram\
+          FLASH_EraseProgram
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..ace10e83c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/.project
new file mode 100644
index 000000000..7808a6b49
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	FLASH_EraseProgram
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			FLASH_EraseProgram.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/FLASH_EraseProgram.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Src/main.c
new file mode 100644
index 000000000..b5be96e13
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Src/main.c
@@ -0,0 +1,331 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FLASH/FLASH_EraseProgram/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example provides a description of how to erase and program the
+  *          STM32WBxx FLASH.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define FLASH_USER_START_ADDR   ADDR_FLASH_PAGE_16   /* Start @ of user Flash area */
+#define FLASH_USER_END_ADDR     (ADDR_FLASH_PAGE_127 + FLASH_PAGE_SIZE - 1)   /* End @ of user Flash area */
+
+#define DATA_32                 ((uint32_t)0x12345678)
+#define DATA_64                 ((uint64_t)0x1234567812345678)
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+uint32_t FirstPage = 0, NbOfPages = 0;
+uint32_t Address = 0, PageError = 0;
+__IO uint32_t MemoryProgramStatus = 0;
+__IO uint32_t data32 = 0;
+
+/*Variable used for Erase procedure*/
+static FLASH_EraseInitTypeDef EraseInitStruct;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+static uint32_t GetPage(uint32_t Address);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+  /* Configure the system clock to 64 MHz */
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+  /* Initialize LED2, LED1 and LED3 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED1);
+  BSP_LED_Init(LED3);
+
+  /* Unlock the Flash to enable the flash control register access *************/
+  HAL_FLASH_Unlock();
+
+ /* Clear OPTVERR bit set on virgin samples */
+  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
+
+  /* Erase the user Flash area
+    (area defined by FLASH_USER_START_ADDR and FLASH_USER_END_ADDR) ***********/
+
+  /* Get the 1st page to erase */
+  FirstPage = GetPage(FLASH_USER_START_ADDR);
+
+  /* Get the number of pages to erase from 1st page */
+  NbOfPages = GetPage(FLASH_USER_END_ADDR) - FirstPage + 1;
+
+  /* Fill EraseInit structure*/
+  EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
+  EraseInitStruct.Page        = FirstPage;
+  EraseInitStruct.NbPages     = NbOfPages;
+
+  /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
+     you have to make sure that these data are rewritten before they are accessed during code
+     execution. If this cannot be done safely, it is recommended to flush the caches by setting the
+     DCRST and ICRST bits in the FLASH_CR register. */
+  if (HAL_FLASHEx_Erase(&EraseInitStruct, &PageError) != HAL_OK)
+  {
+    /*
+      Error occurred while  erase.
+      User can add here some code to deal with this error.
+      PageError will contain the faulty  and then to know the code error on this ,
+      user can call function 'HAL_FLASH_GetError()'
+    */
+    /* Infinite loop */
+    while (1)
+    {
+      /* Turn on LED3 */
+      BSP_LED_On(LED3);
+    }
+  }
+
+  /* Program the user Flash area word by word
+    (area defined by FLASH_USER_START_ADDR and FLASH_USER_END_ADDR) ***********/
+
+  Address = FLASH_USER_START_ADDR;
+
+  while (Address < FLASH_USER_END_ADDR)
+  {
+    if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, Address, DATA_64) == HAL_OK)
+    {
+      Address = Address + 8;  /* increment to next double word*/
+    }
+   else
+    {
+      /* Error occurred while writing data in Flash memory.
+         User can add here some code to deal with this error */
+      while (1)
+      {
+        /* Turn on LED3 */
+        BSP_LED_On(LED3);
+      }
+    }
+  }
+
+  /* Lock the Flash to disable the flash control register access (recommended
+     to protect the FLASH memory against possible unwanted operation) *********/
+  HAL_FLASH_Lock();
+
+  /* Check if the programmed data is OK
+      MemoryProgramStatus = 0: data programmed correctly
+      MemoryProgramStatus != 0: number of words not programmed correctly ******/
+  Address = FLASH_USER_START_ADDR;
+  MemoryProgramStatus = 0x0;
+
+  while (Address < FLASH_USER_END_ADDR)
+  {
+    data32 = *(__IO uint32_t *)Address;
+
+    if (data32 != DATA_32)
+    {
+      MemoryProgramStatus++;
+    }
+    Address = Address + 4;
+  }
+
+  /*Check if there is an issue to program data*/
+  if (MemoryProgramStatus == 0)
+  {
+    /* No error detected. Switch on LED2*/
+    BSP_LED_On(LED2);
+  }
+  else
+  {
+    /* Error detected. Switch on LED1*/
+    BSP_LED_On(LED1);
+  }
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+
+
+
+/**
+  * @brief  Gets the page of a given address
+  * @param  Addr: Address of the FLASH Memory
+  * @retval The page of a given address
+  */
+static uint32_t GetPage(uint32_t Addr)
+{
+  return (Addr - FLASH_BASE) / FLASH_PAGE_SIZE;;
+}
+
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  while(1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..bbd5520b1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FLASH/FLASH_EraseProgram/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..a5b64b12e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Src/stm32wbxx_it.c
@@ -0,0 +1,119 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FLASH/FLASH_EraseProgram/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/readme.txt b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/readme.txt
new file mode 100644
index 000000000..9f7150e07
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_EraseProgram/readme.txt
@@ -0,0 +1,88 @@
+/**
+  @page FLASH_EraseProgram FLASH Erase and Program example
+
+  @verbatim
+  ******************************************************************************
+  * @file    FLASH/FLASH_EraseProgram/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the FLASH Erase and Program example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to configure and use the FLASH HAL API to erase and program the internal
+Flash memory.
+
+At the beginning of the main program the HAL_Init() function is called to reset
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system clock (SYSCLK)
+to run at 64 MHz.
+
+After Reset, the Flash memory Program/Erase Controller is locked. A dedicated function
+is used to enable the FLASH control register access.
+Before programming the desired addresses, an erase operation is performed using
+the flash erase  feature. The erase procedure is done by filling the erase init
+structure giving the starting erase  and the number of s to erase.
+At this stage, all these s will be erased one by one separately.
+
+@note: if problem occurs on a , erase will be stopped and faulty  will
+be returned to user (through variable 'PageError').
+
+Once this operation is finished,  double-word programming operation will be performed
+in the Flash memory. The written data is then read back and checked.
+
+The NUCLEO-WB35CE board LEDs can be used to monitor the transfer status:
+ - LED2 is ON when there are no errors detected after data programming
+ - LED1 is ON when there are errors detected after data programming
+ - LED3 is ON when there is an issue during erase or program procedure
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+Memory, FLASH, Erase, Program, Sector, Mass Erase
+
+@par Directory contents
+
+  - FLASH/FLASH_EraseProgram/Inc/stm32wbxx_hal_conf.h        HAL Configuration file
+  - FLASH/FLASH_EraseProgram/Inc/stm32wbxx_it.h              Header for stm32wbxx_it.c
+  - FLASH/FLASH_EraseProgram/Inc/main.h                      Header for main.c module
+  - FLASH/FLASH_EraseProgram/Src/stm32wbxx_it.c              Interrupt handlers
+  - FLASH/FLASH_EraseProgram/Src/main.c                      Main program
+  - FLASH/FLASH_EraseProgram/Src/stm32wbxx_hal_msp.c         MSP initialization and de-initialization
+  - FLASH/FLASH_EraseProgram/Src/system_stm32wbxx.c          STM32WBxx system clock configuration file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+@par How to use it ?
+
+In order to make the program work, you must do the following:
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/.extSettings b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/FLASH_WriteProtection.ewd b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/FLASH_WriteProtection.ewd
new file mode 100644
index 000000000..b59e64bfe
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/FLASH_WriteProtection.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		FLASH_WriteProtection
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/FLASH_WriteProtection.ewp b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/FLASH_WriteProtection.ewp
new file mode 100644
index 000000000..32c235021
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/FLASH_WriteProtection.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    FLASH_WriteProtection
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/Project.eww
new file mode 100644
index 000000000..04a601f2a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\FLASH_WriteProtection.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/FLASH_WriteProtection.ioc b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/FLASH_WriteProtection.ioc
new file mode 100644
index 000000000..afa888b13
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/FLASH_WriteProtection.ioc
@@ -0,0 +1,106 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=FLASH_WriteProtection.ioc
+ProjectManager.ProjectName=FLASH_WriteProtection
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Inc/main.h
new file mode 100644
index 000000000..012833d50
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Inc/main.h
@@ -0,0 +1,330 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FLASH/FLASH_WriteProtection/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+/* Base address of the Flash pages */
+
+#define ADDR_FLASH_PAGE_0     ((uint32_t)0x08000000) /* Base @ of Page 0, 4 Kbytes */
+#define ADDR_FLASH_PAGE_1     ((uint32_t)0x08001000) /* Base @ of Page 1, 4 Kbytes */
+#define ADDR_FLASH_PAGE_2     ((uint32_t)0x08002000) /* Base @ of Page 2, 4 Kbytes */
+#define ADDR_FLASH_PAGE_3     ((uint32_t)0x08003000) /* Base @ of Page 3, 4 Kbytes */
+#define ADDR_FLASH_PAGE_4     ((uint32_t)0x08004000) /* Base @ of Page 4, 4 Kbytes */
+#define ADDR_FLASH_PAGE_5     ((uint32_t)0x08005000) /* Base @ of Page 5, 4 Kbytes */
+#define ADDR_FLASH_PAGE_6     ((uint32_t)0x08006000) /* Base @ of Page 6, 4 Kbytes */
+#define ADDR_FLASH_PAGE_7     ((uint32_t)0x08007000) /* Base @ of Page 7, 4 Kbytes */
+#define ADDR_FLASH_PAGE_8     ((uint32_t)0x08008000) /* Base @ of Page 8, 4 Kbytes */
+#define ADDR_FLASH_PAGE_9     ((uint32_t)0x08009000) /* Base @ of Page 9, 4 Kbytes */
+#define ADDR_FLASH_PAGE_10    ((uint32_t)0x0800A000) /* Base @ of Page 10, 4 Kbytes */
+#define ADDR_FLASH_PAGE_11    ((uint32_t)0x0800B000) /* Base @ of Page 11, 4 Kbytes */
+#define ADDR_FLASH_PAGE_12    ((uint32_t)0x0800C000) /* Base @ of Page 12, 4 Kbytes */
+#define ADDR_FLASH_PAGE_13    ((uint32_t)0x0800D000) /* Base @ of Page 13, 4 Kbytes */
+#define ADDR_FLASH_PAGE_14    ((uint32_t)0x0800E000) /* Base @ of Page 14, 4 Kbytes */
+#define ADDR_FLASH_PAGE_15    ((uint32_t)0x0800F000) /* Base @ of Page 15, 4 Kbytes */
+#define ADDR_FLASH_PAGE_16    ((uint32_t)0x08010000) /* Base @ of Page 16, 4 Kbytes */
+#define ADDR_FLASH_PAGE_17    ((uint32_t)0x08011000) /* Base @ of Page 17, 4 Kbytes */
+#define ADDR_FLASH_PAGE_18    ((uint32_t)0x08012000) /* Base @ of Page 18, 4 Kbytes */
+#define ADDR_FLASH_PAGE_19    ((uint32_t)0x08013000) /* Base @ of Page 19, 4 Kbytes */
+#define ADDR_FLASH_PAGE_20    ((uint32_t)0x08014000) /* Base @ of Page 20, 4 Kbytes */
+#define ADDR_FLASH_PAGE_21    ((uint32_t)0x08015000) /* Base @ of Page 21, 4 Kbytes */
+#define ADDR_FLASH_PAGE_22    ((uint32_t)0x08016000) /* Base @ of Page 22, 4 Kbytes */
+#define ADDR_FLASH_PAGE_23    ((uint32_t)0x08017000) /* Base @ of Page 23, 4 Kbytes */
+#define ADDR_FLASH_PAGE_24    ((uint32_t)0x08018000) /* Base @ of Page 24, 4 Kbytes */
+#define ADDR_FLASH_PAGE_25    ((uint32_t)0x08019000) /* Base @ of Page 25, 4 Kbytes */
+#define ADDR_FLASH_PAGE_26    ((uint32_t)0x0801A000) /* Base @ of Page 26, 4 Kbytes */
+#define ADDR_FLASH_PAGE_27    ((uint32_t)0x0801B000) /* Base @ of Page 27, 4 Kbytes */
+#define ADDR_FLASH_PAGE_28    ((uint32_t)0x0801C000) /* Base @ of Page 28, 4 Kbytes */
+#define ADDR_FLASH_PAGE_29    ((uint32_t)0x0801D000) /* Base @ of Page 29, 4 Kbytes */
+#define ADDR_FLASH_PAGE_30    ((uint32_t)0x0801E000) /* Base @ of Page 30, 4 Kbytes */
+#define ADDR_FLASH_PAGE_31    ((uint32_t)0x0801F000) /* Base @ of Page 31, 4 Kbytes */
+#define ADDR_FLASH_PAGE_32    ((uint32_t)0x08020000) /* Base @ of Page 32, 4 Kbytes */
+#define ADDR_FLASH_PAGE_33    ((uint32_t)0x08021000) /* Base @ of Page 33, 4 Kbytes */
+#define ADDR_FLASH_PAGE_34    ((uint32_t)0x08022000) /* Base @ of Page 34, 4 Kbytes */
+#define ADDR_FLASH_PAGE_35    ((uint32_t)0x08023000) /* Base @ of Page 35, 4 Kbytes */
+#define ADDR_FLASH_PAGE_36    ((uint32_t)0x08024000) /* Base @ of Page 36, 4 Kbytes */
+#define ADDR_FLASH_PAGE_37    ((uint32_t)0x08025000) /* Base @ of Page 37, 4 Kbytes */
+#define ADDR_FLASH_PAGE_38    ((uint32_t)0x08026000) /* Base @ of Page 38, 4 Kbytes */
+#define ADDR_FLASH_PAGE_39    ((uint32_t)0x08027000) /* Base @ of Page 39, 4 Kbytes */
+#define ADDR_FLASH_PAGE_40    ((uint32_t)0x08028000) /* Base @ of Page 40, 4 Kbytes */
+#define ADDR_FLASH_PAGE_41    ((uint32_t)0x08029000) /* Base @ of Page 41, 4 Kbytes */
+#define ADDR_FLASH_PAGE_42    ((uint32_t)0x0802A000) /* Base @ of Page 42, 4 Kbytes */
+#define ADDR_FLASH_PAGE_43    ((uint32_t)0x0802B000) /* Base @ of Page 43, 4 Kbytes */
+#define ADDR_FLASH_PAGE_44    ((uint32_t)0x0802C000) /* Base @ of Page 44, 4 Kbytes */
+#define ADDR_FLASH_PAGE_45    ((uint32_t)0x0802D000) /* Base @ of Page 45, 4 Kbytes */
+#define ADDR_FLASH_PAGE_46    ((uint32_t)0x0802E000) /* Base @ of Page 46, 4 Kbytes */
+#define ADDR_FLASH_PAGE_47    ((uint32_t)0x0802F000) /* Base @ of Page 47, 4 Kbytes */
+#define ADDR_FLASH_PAGE_48    ((uint32_t)0x08030000) /* Base @ of Page 48, 4 Kbytes */
+#define ADDR_FLASH_PAGE_49    ((uint32_t)0x08031000) /* Base @ of Page 49, 4 Kbytes */
+#define ADDR_FLASH_PAGE_50    ((uint32_t)0x08032000) /* Base @ of Page 50, 4 Kbytes */
+#define ADDR_FLASH_PAGE_51    ((uint32_t)0x08033000) /* Base @ of Page 51, 4 Kbytes */
+#define ADDR_FLASH_PAGE_52    ((uint32_t)0x08034000) /* Base @ of Page 52, 4 Kbytes */
+#define ADDR_FLASH_PAGE_53    ((uint32_t)0x08035000) /* Base @ of Page 53, 4 Kbytes */
+#define ADDR_FLASH_PAGE_54    ((uint32_t)0x08036000) /* Base @ of Page 54, 4 Kbytes */
+#define ADDR_FLASH_PAGE_55    ((uint32_t)0x08037000) /* Base @ of Page 55, 4 Kbytes */
+#define ADDR_FLASH_PAGE_56    ((uint32_t)0x08038000) /* Base @ of Page 56, 4 Kbytes */
+#define ADDR_FLASH_PAGE_57    ((uint32_t)0x08039000) /* Base @ of Page 57, 4 Kbytes */
+#define ADDR_FLASH_PAGE_58    ((uint32_t)0x0803A000) /* Base @ of Page 58, 4 Kbytes */
+#define ADDR_FLASH_PAGE_59    ((uint32_t)0x0803B000) /* Base @ of Page 59, 4 Kbytes */
+#define ADDR_FLASH_PAGE_60    ((uint32_t)0x0803C000) /* Base @ of Page 60, 4 Kbytes */
+#define ADDR_FLASH_PAGE_61    ((uint32_t)0x0803D000) /* Base @ of Page 61, 4 Kbytes */
+#define ADDR_FLASH_PAGE_62    ((uint32_t)0x0803E000) /* Base @ of Page 62, 4 Kbytes */
+#define ADDR_FLASH_PAGE_63    ((uint32_t)0x0803F000) /* Base @ of Page 63, 4 Kbytes */
+#define ADDR_FLASH_PAGE_64    ((uint32_t)0x08040000) /* Base @ of Page 64, 4 Kbytes */
+#define ADDR_FLASH_PAGE_65    ((uint32_t)0x08041000) /* Base @ of Page 65, 4 Kbytes */
+#define ADDR_FLASH_PAGE_66    ((uint32_t)0x08042000) /* Base @ of Page 66, 4 Kbytes */
+#define ADDR_FLASH_PAGE_67    ((uint32_t)0x08043000) /* Base @ of Page 67, 4 Kbytes */
+#define ADDR_FLASH_PAGE_68    ((uint32_t)0x08044000) /* Base @ of Page 68, 4 Kbytes */
+#define ADDR_FLASH_PAGE_69    ((uint32_t)0x08045000) /* Base @ of Page 69, 4 Kbytes */
+#define ADDR_FLASH_PAGE_70    ((uint32_t)0x08046000) /* Base @ of Page 70, 4 Kbytes */
+#define ADDR_FLASH_PAGE_71    ((uint32_t)0x08047000) /* Base @ of Page 71, 4 Kbytes */
+#define ADDR_FLASH_PAGE_72    ((uint32_t)0x08048000) /* Base @ of Page 72, 4 Kbytes */
+#define ADDR_FLASH_PAGE_73    ((uint32_t)0x08049000) /* Base @ of Page 73, 4 Kbytes */
+#define ADDR_FLASH_PAGE_74    ((uint32_t)0x0804A000) /* Base @ of Page 74, 4 Kbytes */
+#define ADDR_FLASH_PAGE_75    ((uint32_t)0x0804B000) /* Base @ of Page 75, 4 Kbytes */
+#define ADDR_FLASH_PAGE_76    ((uint32_t)0x0804C000) /* Base @ of Page 76, 4 Kbytes */
+#define ADDR_FLASH_PAGE_77    ((uint32_t)0x0804D000) /* Base @ of Page 77, 4 Kbytes */
+#define ADDR_FLASH_PAGE_78    ((uint32_t)0x0804E000) /* Base @ of Page 78, 4 Kbytes */
+#define ADDR_FLASH_PAGE_79    ((uint32_t)0x0804F000) /* Base @ of Page 79, 4 Kbytes */
+#define ADDR_FLASH_PAGE_80    ((uint32_t)0x08050000) /* Base @ of Page 80, 4 Kbytes */
+#define ADDR_FLASH_PAGE_81    ((uint32_t)0x08051000) /* Base @ of Page 81, 4 Kbytes */
+#define ADDR_FLASH_PAGE_82    ((uint32_t)0x08052000) /* Base @ of Page 82, 4 Kbytes */
+#define ADDR_FLASH_PAGE_83    ((uint32_t)0x08053000) /* Base @ of Page 83, 4 Kbytes */
+#define ADDR_FLASH_PAGE_84    ((uint32_t)0x08054000) /* Base @ of Page 84, 4 Kbytes */
+#define ADDR_FLASH_PAGE_85    ((uint32_t)0x08055000) /* Base @ of Page 85, 4 Kbytes */
+#define ADDR_FLASH_PAGE_86    ((uint32_t)0x08056000) /* Base @ of Page 86, 4 Kbytes */
+#define ADDR_FLASH_PAGE_87    ((uint32_t)0x08057000) /* Base @ of Page 87, 4 Kbytes */
+#define ADDR_FLASH_PAGE_88    ((uint32_t)0x08058000) /* Base @ of Page 88, 4 Kbytes */
+#define ADDR_FLASH_PAGE_89    ((uint32_t)0x08059000) /* Base @ of Page 89, 4 Kbytes */
+#define ADDR_FLASH_PAGE_90    ((uint32_t)0x0805A000) /* Base @ of Page 90, 4 Kbytes */
+#define ADDR_FLASH_PAGE_91    ((uint32_t)0x0805B000) /* Base @ of Page 91, 4 Kbytes */
+#define ADDR_FLASH_PAGE_92    ((uint32_t)0x0805C000) /* Base @ of Page 92, 4 Kbytes */
+#define ADDR_FLASH_PAGE_93    ((uint32_t)0x0805D000) /* Base @ of Page 93, 4 Kbytes */
+#define ADDR_FLASH_PAGE_94    ((uint32_t)0x0805E000) /* Base @ of Page 94, 4 Kbytes */
+#define ADDR_FLASH_PAGE_95    ((uint32_t)0x0805F000) /* Base @ of Page 95, 4 Kbytes */
+#define ADDR_FLASH_PAGE_96    ((uint32_t)0x08060000) /* Base @ of Page 96, 4 Kbytes */
+#define ADDR_FLASH_PAGE_97    ((uint32_t)0x08061000) /* Base @ of Page 97, 4 Kbytes */
+#define ADDR_FLASH_PAGE_98    ((uint32_t)0x08062000) /* Base @ of Page 98, 4 Kbytes */
+#define ADDR_FLASH_PAGE_99    ((uint32_t)0x08063000) /* Base @ of Page 99, 4 Kbytes */
+#define ADDR_FLASH_PAGE_100   ((uint32_t)0x08064000) /* Base @ of Page 100, 4 Kbytes */
+#define ADDR_FLASH_PAGE_101   ((uint32_t)0x08065000) /* Base @ of Page 101, 4 Kbytes */
+#define ADDR_FLASH_PAGE_102   ((uint32_t)0x08066000) /* Base @ of Page 102, 4 Kbytes */
+#define ADDR_FLASH_PAGE_103   ((uint32_t)0x08067000) /* Base @ of Page 103, 4 Kbytes */
+#define ADDR_FLASH_PAGE_104   ((uint32_t)0x08068000) /* Base @ of Page 104, 4 Kbytes */
+#define ADDR_FLASH_PAGE_105   ((uint32_t)0x08069000) /* Base @ of Page 105, 4 Kbytes */
+#define ADDR_FLASH_PAGE_106   ((uint32_t)0x0806A000) /* Base @ of Page 106, 4 Kbytes */
+#define ADDR_FLASH_PAGE_107   ((uint32_t)0x0806B000) /* Base @ of Page 107, 4 Kbytes */
+#define ADDR_FLASH_PAGE_108   ((uint32_t)0x0806C000) /* Base @ of Page 108, 4 Kbytes */
+#define ADDR_FLASH_PAGE_109   ((uint32_t)0x0806D000) /* Base @ of Page 109, 4 Kbytes */
+#define ADDR_FLASH_PAGE_110   ((uint32_t)0x0806E000) /* Base @ of Page 110, 4 Kbytes */
+#define ADDR_FLASH_PAGE_111   ((uint32_t)0x0806F000) /* Base @ of Page 111, 4 Kbytes */
+#define ADDR_FLASH_PAGE_112   ((uint32_t)0x08070000) /* Base @ of Page 112, 4 Kbytes */
+#define ADDR_FLASH_PAGE_113   ((uint32_t)0x08071000) /* Base @ of Page 113, 4 Kbytes */
+#define ADDR_FLASH_PAGE_114   ((uint32_t)0x08072000) /* Base @ of Page 114, 4 Kbytes */
+#define ADDR_FLASH_PAGE_115   ((uint32_t)0x08073000) /* Base @ of Page 115, 4 Kbytes */
+#define ADDR_FLASH_PAGE_116   ((uint32_t)0x08074000) /* Base @ of Page 116, 4 Kbytes */
+#define ADDR_FLASH_PAGE_117   ((uint32_t)0x08075000) /* Base @ of Page 117, 4 Kbytes */
+#define ADDR_FLASH_PAGE_118   ((uint32_t)0x08076000) /* Base @ of Page 118, 4 Kbytes */
+#define ADDR_FLASH_PAGE_119   ((uint32_t)0x08077000) /* Base @ of Page 119, 4 Kbytes */
+#define ADDR_FLASH_PAGE_120   ((uint32_t)0x08078000) /* Base @ of Page 120, 4 Kbytes */
+#define ADDR_FLASH_PAGE_121   ((uint32_t)0x08079000) /* Base @ of Page 121, 4 Kbytes */
+#define ADDR_FLASH_PAGE_122   ((uint32_t)0x0807A000) /* Base @ of Page 122, 4 Kbytes */
+#define ADDR_FLASH_PAGE_123   ((uint32_t)0x0807B000) /* Base @ of Page 123, 4 Kbytes */
+#define ADDR_FLASH_PAGE_124   ((uint32_t)0x0807C000) /* Base @ of Page 124, 4 Kbytes */
+#define ADDR_FLASH_PAGE_125   ((uint32_t)0x0807D000) /* Base @ of Page 125, 4 Kbytes */
+#define ADDR_FLASH_PAGE_126   ((uint32_t)0x0807E000) /* Base @ of Page 126, 4 Kbytes */
+#define ADDR_FLASH_PAGE_127   ((uint32_t)0x0807F000) /* Base @ of Page 127, 4 Kbytes */
+#define ADDR_FLASH_PAGE_128   ((uint32_t)0x08080000) /* Base @ of Page 128, 4 Kbytes */
+#define ADDR_FLASH_PAGE_129   ((uint32_t)0x08081000) /* Base @ of Page 129, 4 Kbytes */
+#define ADDR_FLASH_PAGE_130   ((uint32_t)0x08082000) /* Base @ of Page 130, 4 Kbytes */
+#define ADDR_FLASH_PAGE_131   ((uint32_t)0x08083000) /* Base @ of Page 131, 4 Kbytes */
+#define ADDR_FLASH_PAGE_132   ((uint32_t)0x08084000) /* Base @ of Page 132, 4 Kbytes */
+#define ADDR_FLASH_PAGE_133   ((uint32_t)0x08085000) /* Base @ of Page 133, 4 Kbytes */
+#define ADDR_FLASH_PAGE_134   ((uint32_t)0x08086000) /* Base @ of Page 134, 4 Kbytes */
+#define ADDR_FLASH_PAGE_135   ((uint32_t)0x08087000) /* Base @ of Page 135, 4 Kbytes */
+#define ADDR_FLASH_PAGE_136   ((uint32_t)0x08088000) /* Base @ of Page 136, 4 Kbytes */
+#define ADDR_FLASH_PAGE_137   ((uint32_t)0x08089000) /* Base @ of Page 137, 4 Kbytes */
+#define ADDR_FLASH_PAGE_138   ((uint32_t)0x0808A000) /* Base @ of Page 138, 4 Kbytes */
+#define ADDR_FLASH_PAGE_139   ((uint32_t)0x0808B000) /* Base @ of Page 139, 4 Kbytes */
+#define ADDR_FLASH_PAGE_140   ((uint32_t)0x0808C000) /* Base @ of Page 140, 4 Kbytes */
+#define ADDR_FLASH_PAGE_141   ((uint32_t)0x0808D000) /* Base @ of Page 141, 4 Kbytes */
+#define ADDR_FLASH_PAGE_142   ((uint32_t)0x0808E000) /* Base @ of Page 142, 4 Kbytes */
+#define ADDR_FLASH_PAGE_143   ((uint32_t)0x0808F000) /* Base @ of Page 143, 4 Kbytes */
+#define ADDR_FLASH_PAGE_144   ((uint32_t)0x08090000) /* Base @ of Page 144, 4 Kbytes */
+#define ADDR_FLASH_PAGE_145   ((uint32_t)0x08091000) /* Base @ of Page 145, 4 Kbytes */
+#define ADDR_FLASH_PAGE_146   ((uint32_t)0x08092000) /* Base @ of Page 146, 4 Kbytes */
+#define ADDR_FLASH_PAGE_147   ((uint32_t)0x08093000) /* Base @ of Page 147, 4 Kbytes */
+#define ADDR_FLASH_PAGE_148   ((uint32_t)0x08094000) /* Base @ of Page 148, 4 Kbytes */
+#define ADDR_FLASH_PAGE_149   ((uint32_t)0x08095000) /* Base @ of Page 149, 4 Kbytes */
+#define ADDR_FLASH_PAGE_150   ((uint32_t)0x08096000) /* Base @ of Page 150, 4 Kbytes */
+#define ADDR_FLASH_PAGE_151   ((uint32_t)0x08097000) /* Base @ of Page 151, 4 Kbytes */
+#define ADDR_FLASH_PAGE_152   ((uint32_t)0x08098000) /* Base @ of Page 152, 4 Kbytes */
+#define ADDR_FLASH_PAGE_153   ((uint32_t)0x08099000) /* Base @ of Page 153, 4 Kbytes */
+#define ADDR_FLASH_PAGE_154   ((uint32_t)0x0809A000) /* Base @ of Page 154, 4 Kbytes */
+#define ADDR_FLASH_PAGE_155   ((uint32_t)0x0809B000) /* Base @ of Page 155, 4 Kbytes */
+#define ADDR_FLASH_PAGE_156   ((uint32_t)0x0809C000) /* Base @ of Page 156, 4 Kbytes */
+#define ADDR_FLASH_PAGE_157   ((uint32_t)0x0809D000) /* Base @ of Page 157, 4 Kbytes */
+#define ADDR_FLASH_PAGE_158   ((uint32_t)0x0809E000) /* Base @ of Page 158, 4 Kbytes */
+#define ADDR_FLASH_PAGE_159   ((uint32_t)0x0809F000) /* Base @ of Page 159, 4 Kbytes */
+#define ADDR_FLASH_PAGE_160   ((uint32_t)0x080A0000) /* Base @ of Page 160, 4 Kbytes */
+#define ADDR_FLASH_PAGE_161   ((uint32_t)0x080A1000) /* Base @ of Page 161, 4 Kbytes */
+#define ADDR_FLASH_PAGE_162   ((uint32_t)0x080A2000) /* Base @ of Page 162, 4 Kbytes */
+#define ADDR_FLASH_PAGE_163   ((uint32_t)0x080A3000) /* Base @ of Page 163, 4 Kbytes */
+#define ADDR_FLASH_PAGE_164   ((uint32_t)0x080A4000) /* Base @ of Page 164, 4 Kbytes */
+#define ADDR_FLASH_PAGE_165   ((uint32_t)0x080A5000) /* Base @ of Page 165, 4 Kbytes */
+#define ADDR_FLASH_PAGE_166   ((uint32_t)0x080A6000) /* Base @ of Page 166, 4 Kbytes */
+#define ADDR_FLASH_PAGE_167   ((uint32_t)0x080A7000) /* Base @ of Page 167, 4 Kbytes */
+#define ADDR_FLASH_PAGE_168   ((uint32_t)0x080A8000) /* Base @ of Page 168, 4 Kbytes */
+#define ADDR_FLASH_PAGE_169   ((uint32_t)0x080A9000) /* Base @ of Page 169, 4 Kbytes */
+#define ADDR_FLASH_PAGE_170   ((uint32_t)0x080AA000) /* Base @ of Page 170, 4 Kbytes */
+#define ADDR_FLASH_PAGE_171   ((uint32_t)0x080AB000) /* Base @ of Page 171, 4 Kbytes */
+#define ADDR_FLASH_PAGE_172   ((uint32_t)0x080AC000) /* Base @ of Page 172, 4 Kbytes */
+#define ADDR_FLASH_PAGE_173   ((uint32_t)0x080AD000) /* Base @ of Page 173, 4 Kbytes */
+#define ADDR_FLASH_PAGE_174   ((uint32_t)0x080AE000) /* Base @ of Page 174, 4 Kbytes */
+#define ADDR_FLASH_PAGE_175   ((uint32_t)0x080AF000) /* Base @ of Page 175, 4 Kbytes */
+#define ADDR_FLASH_PAGE_176   ((uint32_t)0x080B0000) /* Base @ of Page 176, 4 Kbytes */
+#define ADDR_FLASH_PAGE_177   ((uint32_t)0x080B1000) /* Base @ of Page 177, 4 Kbytes */
+#define ADDR_FLASH_PAGE_178   ((uint32_t)0x080B2000) /* Base @ of Page 178, 4 Kbytes */
+#define ADDR_FLASH_PAGE_179   ((uint32_t)0x080B3000) /* Base @ of Page 179, 4 Kbytes */
+#define ADDR_FLASH_PAGE_180   ((uint32_t)0x080B4000) /* Base @ of Page 180, 4 Kbytes */
+#define ADDR_FLASH_PAGE_181   ((uint32_t)0x080B5000) /* Base @ of Page 181, 4 Kbytes */
+#define ADDR_FLASH_PAGE_182   ((uint32_t)0x080B6000) /* Base @ of Page 182, 4 Kbytes */
+#define ADDR_FLASH_PAGE_183   ((uint32_t)0x080B7000) /* Base @ of Page 183, 4 Kbytes */
+#define ADDR_FLASH_PAGE_184   ((uint32_t)0x080B8000) /* Base @ of Page 184, 4 Kbytes */
+#define ADDR_FLASH_PAGE_185   ((uint32_t)0x080B9000) /* Base @ of Page 185, 4 Kbytes */
+#define ADDR_FLASH_PAGE_186   ((uint32_t)0x080BA000) /* Base @ of Page 186, 4 Kbytes */
+#define ADDR_FLASH_PAGE_187   ((uint32_t)0x080BB000) /* Base @ of Page 187, 4 Kbytes */
+#define ADDR_FLASH_PAGE_188   ((uint32_t)0x080BC000) /* Base @ of Page 188, 4 Kbytes */
+#define ADDR_FLASH_PAGE_189   ((uint32_t)0x080BD000) /* Base @ of Page 189, 4 Kbytes */
+#define ADDR_FLASH_PAGE_190   ((uint32_t)0x080BE000) /* Base @ of Page 190, 4 Kbytes */
+#define ADDR_FLASH_PAGE_191   ((uint32_t)0x080BF000) /* Base @ of Page 191, 4 Kbytes */
+#define ADDR_FLASH_PAGE_192   ((uint32_t)0x080C0000) /* Base @ of Page 192, 4 Kbytes */
+#define ADDR_FLASH_PAGE_193   ((uint32_t)0x080C1000) /* Base @ of Page 193, 4 Kbytes */
+#define ADDR_FLASH_PAGE_194   ((uint32_t)0x080C2000) /* Base @ of Page 194, 4 Kbytes */
+#define ADDR_FLASH_PAGE_195   ((uint32_t)0x080C3000) /* Base @ of Page 195, 4 Kbytes */
+#define ADDR_FLASH_PAGE_196   ((uint32_t)0x080C4000) /* Base @ of Page 196, 4 Kbytes */
+#define ADDR_FLASH_PAGE_197   ((uint32_t)0x080C5000) /* Base @ of Page 197, 4 Kbytes */
+#define ADDR_FLASH_PAGE_198   ((uint32_t)0x080C6000) /* Base @ of Page 198, 4 Kbytes */
+#define ADDR_FLASH_PAGE_199   ((uint32_t)0x080C7000) /* Base @ of Page 199, 4 Kbytes */
+#define ADDR_FLASH_PAGE_200   ((uint32_t)0x080C8000) /* Base @ of Page 200, 4 Kbytes */
+#define ADDR_FLASH_PAGE_201   ((uint32_t)0x080C9000) /* Base @ of Page 201, 4 Kbytes */
+#define ADDR_FLASH_PAGE_202   ((uint32_t)0x080CA000) /* Base @ of Page 202, 4 Kbytes */
+#define ADDR_FLASH_PAGE_203   ((uint32_t)0x080CB000) /* Base @ of Page 203, 4 Kbytes */
+#define ADDR_FLASH_PAGE_204   ((uint32_t)0x080CC000) /* Base @ of Page 204, 4 Kbytes */
+#define ADDR_FLASH_PAGE_205   ((uint32_t)0x080CD000) /* Base @ of Page 205, 4 Kbytes */
+#define ADDR_FLASH_PAGE_206   ((uint32_t)0x080CE000) /* Base @ of Page 206, 4 Kbytes */
+#define ADDR_FLASH_PAGE_207   ((uint32_t)0x080CF000) /* Base @ of Page 207, 4 Kbytes */
+#define ADDR_FLASH_PAGE_208   ((uint32_t)0x080D0000) /* Base @ of Page 208, 4 Kbytes */
+#define ADDR_FLASH_PAGE_209   ((uint32_t)0x080D1000) /* Base @ of Page 209, 4 Kbytes */
+#define ADDR_FLASH_PAGE_210   ((uint32_t)0x080D2000) /* Base @ of Page 210, 4 Kbytes */
+#define ADDR_FLASH_PAGE_211   ((uint32_t)0x080D3000) /* Base @ of Page 211, 4 Kbytes */
+#define ADDR_FLASH_PAGE_212   ((uint32_t)0x080D4000) /* Base @ of Page 212, 4 Kbytes */
+#define ADDR_FLASH_PAGE_213   ((uint32_t)0x080D5000) /* Base @ of Page 213, 4 Kbytes */
+#define ADDR_FLASH_PAGE_214   ((uint32_t)0x080D6000) /* Base @ of Page 214, 4 Kbytes */
+#define ADDR_FLASH_PAGE_215   ((uint32_t)0x080D7000) /* Base @ of Page 215, 4 Kbytes */
+#define ADDR_FLASH_PAGE_216   ((uint32_t)0x080D8000) /* Base @ of Page 216, 4 Kbytes */
+#define ADDR_FLASH_PAGE_217   ((uint32_t)0x080D9000) /* Base @ of Page 217, 4 Kbytes */
+#define ADDR_FLASH_PAGE_218   ((uint32_t)0x080DA000) /* Base @ of Page 218, 4 Kbytes */
+#define ADDR_FLASH_PAGE_219   ((uint32_t)0x080DB000) /* Base @ of Page 219, 4 Kbytes */
+#define ADDR_FLASH_PAGE_220   ((uint32_t)0x080DC000) /* Base @ of Page 220, 4 Kbytes */
+#define ADDR_FLASH_PAGE_221   ((uint32_t)0x080DD000) /* Base @ of Page 221, 4 Kbytes */
+#define ADDR_FLASH_PAGE_222   ((uint32_t)0x080DE000) /* Base @ of Page 222, 4 Kbytes */
+#define ADDR_FLASH_PAGE_223   ((uint32_t)0x080DF000) /* Base @ of Page 223, 4 Kbytes */
+#define ADDR_FLASH_PAGE_224   ((uint32_t)0x080E0000) /* Base @ of Page 224, 4 Kbytes */
+#define ADDR_FLASH_PAGE_225   ((uint32_t)0x080E1000) /* Base @ of Page 225, 4 Kbytes */
+#define ADDR_FLASH_PAGE_226   ((uint32_t)0x080E2000) /* Base @ of Page 226, 4 Kbytes */
+#define ADDR_FLASH_PAGE_227   ((uint32_t)0x080E3000) /* Base @ of Page 227, 4 Kbytes */
+#define ADDR_FLASH_PAGE_228   ((uint32_t)0x080E4000) /* Base @ of Page 228, 4 Kbytes */
+#define ADDR_FLASH_PAGE_229   ((uint32_t)0x080E5000) /* Base @ of Page 229, 4 Kbytes */
+#define ADDR_FLASH_PAGE_230   ((uint32_t)0x080E6000) /* Base @ of Page 230, 4 Kbytes */
+#define ADDR_FLASH_PAGE_231   ((uint32_t)0x080E7000) /* Base @ of Page 231, 4 Kbytes */
+#define ADDR_FLASH_PAGE_232   ((uint32_t)0x080E8000) /* Base @ of Page 232, 4 Kbytes */
+#define ADDR_FLASH_PAGE_233   ((uint32_t)0x080E9000) /* Base @ of Page 233, 4 Kbytes */
+#define ADDR_FLASH_PAGE_234   ((uint32_t)0x080EA000) /* Base @ of Page 234, 4 Kbytes */
+#define ADDR_FLASH_PAGE_235   ((uint32_t)0x080EB000) /* Base @ of Page 235, 4 Kbytes */
+#define ADDR_FLASH_PAGE_236   ((uint32_t)0x080EC000) /* Base @ of Page 236, 4 Kbytes */
+#define ADDR_FLASH_PAGE_237   ((uint32_t)0x080ED000) /* Base @ of Page 237, 4 Kbytes */
+#define ADDR_FLASH_PAGE_238   ((uint32_t)0x080EE000) /* Base @ of Page 238, 4 Kbytes */
+#define ADDR_FLASH_PAGE_239   ((uint32_t)0x080EF000) /* Base @ of Page 239, 4 Kbytes */
+#define ADDR_FLASH_PAGE_240   ((uint32_t)0x080F0000) /* Base @ of Page 240, 4 Kbytes */
+#define ADDR_FLASH_PAGE_241   ((uint32_t)0x080F1000) /* Base @ of Page 241, 4 Kbytes */
+#define ADDR_FLASH_PAGE_242   ((uint32_t)0x080F2000) /* Base @ of Page 242, 4 Kbytes */
+#define ADDR_FLASH_PAGE_243   ((uint32_t)0x080F3000) /* Base @ of Page 243, 4 Kbytes */
+#define ADDR_FLASH_PAGE_244   ((uint32_t)0x080F4000) /* Base @ of Page 244, 4 Kbytes */
+#define ADDR_FLASH_PAGE_245   ((uint32_t)0x080F5000) /* Base @ of Page 245, 4 Kbytes */
+#define ADDR_FLASH_PAGE_246   ((uint32_t)0x080F6000) /* Base @ of Page 246, 4 Kbytes */
+#define ADDR_FLASH_PAGE_247   ((uint32_t)0x080F7000) /* Base @ of Page 247, 4 Kbytes */
+#define ADDR_FLASH_PAGE_248   ((uint32_t)0x080F8000) /* Base @ of Page 248, 4 Kbytes */
+#define ADDR_FLASH_PAGE_249   ((uint32_t)0x080F9000) /* Base @ of Page 249, 4 Kbytes */
+#define ADDR_FLASH_PAGE_250   ((uint32_t)0x080FA000) /* Base @ of Page 250, 4 Kbytes */
+#define ADDR_FLASH_PAGE_251   ((uint32_t)0x080FB000) /* Base @ of Page 251, 4 Kbytes */
+#define ADDR_FLASH_PAGE_252   ((uint32_t)0x080FC000) /* Base @ of Page 252, 4 Kbytes */
+#define ADDR_FLASH_PAGE_253   ((uint32_t)0x080FD000) /* Base @ of Page 253, 4 Kbytes */
+#define ADDR_FLASH_PAGE_254   ((uint32_t)0x080FE000) /* Base @ of Page 254, 4 Kbytes */
+#define ADDR_FLASH_PAGE_255   ((uint32_t)0x080FF000) /* Base @ of Page 255, 4 Kbytes */
+
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..19d12a61f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..9c100b00c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Inc/stm32wbxx_it.h
@@ -0,0 +1,64 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FLASH/FLASH_WriteProtection/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/MDK-ARM/FLASH_WriteProtection.uvoptx b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/MDK-ARM/FLASH_WriteProtection.uvoptx
new file mode 100644
index 000000000..bf88b37ce
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/MDK-ARM/FLASH_WriteProtection.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    FLASH_WriteProtection
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/MDK-ARM/FLASH_WriteProtection.uvprojx b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/MDK-ARM/FLASH_WriteProtection.uvprojx
new file mode 100644
index 000000000..f440424a9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/MDK-ARM/FLASH_WriteProtection.uvprojx
@@ -0,0 +1,541 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      FLASH_WriteProtection
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          FLASH_WriteProtection\
+          FLASH_WriteProtection
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..838e724b8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/.project
new file mode 100644
index 000000000..bdd2b1821
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	FLASH_WriteProtection
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			FLASH_WriteProtection.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/FLASH_WriteProtection.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Src/main.c
new file mode 100644
index 000000000..286e25447
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Src/main.c
@@ -0,0 +1,600 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FLASH/FLASH_WriteProtection/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example provides a description of how to set write protection on
+  *          STM32WBxx FLASH.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+#define FLASH_USER_START_ADDR       ADDR_FLASH_PAGE_16   /* Start @ of user Flash area */
+#define FLASH_USER_END_ADDR         ADDR_FLASH_PAGE_126 + FLASH_PAGE_SIZE - 1   /* End @ of user Flash area */
+
+#define DATA_32                     ((uint32_t)0x12345678)
+#define DATA_64                     ((uint64_t)0x1234567812345678)
+
+/* Uncomment this line to program the Flash pages */
+#define FLASH_PAGE_PROGRAM
+
+/* Uncomment this line to Enable Write Protection */
+/* #define WRITE_PROTECTION_ENABLE */
+
+/* Uncomment this line to Disable Write Protection */
+/* #define WRITE_PROTECTION_DISABLE */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+uint32_t StartPage = 0, EndPage = 0;
+uint32_t Address = 0;
+uint32_t PageError = 0;
+__IO TestStatus MemoryProgramStatus = PASSED;
+/*Variable used for Erase procedure*/
+#ifdef FLASH_PAGE_PROGRAM
+static FLASH_EraseInitTypeDef EraseInitStruct;
+#endif
+/*Variable used to handle the Options Bytes*/
+static FLASH_OBProgramInitTypeDef OptionsBytesStruct, OptionsBytesStruct2;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+static uint32_t GetPage(uint32_t Address);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+  /* Initialize LED2, LED1 and LED3 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED1);
+  BSP_LED_Init(LED3);
+
+  /* Initialize test status */
+  MemoryProgramStatus = PASSED;
+
+  /* Unlock the Flash to enable the flash control register access *************/
+  HAL_FLASH_Unlock();
+  
+  /* Clear OPTVERR bit set on virgin samples */
+  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
+
+  /* Unlock the Options Bytes *************************************************/
+  HAL_FLASH_OB_Unlock();
+
+  /* Get the number of the start and end pages */
+  StartPage = GetPage(FLASH_USER_START_ADDR);
+  EndPage   = GetPage(FLASH_USER_END_ADDR);
+
+  OptionsBytesStruct.WRPArea  = OB_WRPAREA_BANK1_AREAA;
+  OptionsBytesStruct2.WRPArea = OB_WRPAREA_BANK1_AREAB;
+
+  /* Get pages write protection status ****************************************/
+  HAL_FLASHEx_OBGetConfig(&OptionsBytesStruct);
+  HAL_FLASHEx_OBGetConfig(&OptionsBytesStruct2);
+
+#ifdef WRITE_PROTECTION_DISABLE
+  /* Check if desired pages are already write protected ***********************/
+  if ((OptionsBytesStruct.WRPStartOffset == StartPage) && (OptionsBytesStruct.WRPEndOffset == EndPage))
+  {
+    /* Current area correspond to the area to disable */
+    OptionsBytesStruct.OptionType     = OPTIONBYTE_WRP;
+    OptionsBytesStruct.WRPStartOffset = 0xFF;
+    OptionsBytesStruct.WRPEndOffset   = 0;
+  }
+  else if ((OptionsBytesStruct.WRPStartOffset == StartPage) && (OptionsBytesStruct.WRPEndOffset > EndPage))
+  {
+    /* Current area is bigger than the area to disable : */
+    /* - End of area is bigger than the last page to un-protect */
+    OptionsBytesStruct.OptionType     = OPTIONBYTE_WRP;
+    OptionsBytesStruct.WRPStartOffset = EndPage + 1;
+  }
+  else if ((OptionsBytesStruct.WRPStartOffset < StartPage) && (OptionsBytesStruct.WRPEndOffset == EndPage))
+  {
+    /* Current area is bigger than the area to disable : */
+    /* - Start of area is lower than the first page to un-protect */
+    OptionsBytesStruct.OptionType     = OPTIONBYTE_WRP;
+    OptionsBytesStruct.WRPEndOffset   = StartPage - 1;
+  }
+  else if ((OptionsBytesStruct.WRPStartOffset < StartPage) && (OptionsBytesStruct.WRPEndOffset > EndPage))
+  {
+    /* Current area is bigger than the area to disable */
+    /* - Start of area is lower than the first page to un-protect */
+    /* - End of area is bigger than the last page to un-protect */
+    if (OptionsBytesStruct2.WRPStartOffset > OptionsBytesStruct2.WRPEndOffset)
+    {
+      /* Second area of the bank can be used */
+      OptionsBytesStruct2.OptionType     = OPTIONBYTE_WRP;
+      OptionsBytesStruct2.WRPStartOffset = EndPage + 1;
+      OptionsBytesStruct2.WRPEndOffset   = OptionsBytesStruct.WRPEndOffset;
+
+      OptionsBytesStruct.OptionType     = OPTIONBYTE_WRP;
+      OptionsBytesStruct.WRPEndOffset   = StartPage - 1;
+    }
+    else
+    {
+      /* Second area of the bank already used for WRP */
+      /* => Error : not possible to deactivate only the pages indicated */
+      while (1)
+      {
+        BSP_LED_On(LED3);
+      }
+    }
+  }
+  else if ((OptionsBytesStruct2.WRPStartOffset == StartPage) && (OptionsBytesStruct2.WRPEndOffset == EndPage))
+  {
+    /* Current area correspond to the area to disable */
+    OptionsBytesStruct2.OptionType     = OPTIONBYTE_WRP;
+    OptionsBytesStruct2.WRPStartOffset = 0xFF;
+    OptionsBytesStruct2.WRPEndOffset   = 0;
+  }
+  else if ((OptionsBytesStruct2.WRPStartOffset == StartPage) && (OptionsBytesStruct2.WRPEndOffset > EndPage))
+  {
+    /* Current area is bigger than the area to disable : */
+    /* - End of area is bigger than the last page to un-protect */
+    OptionsBytesStruct2.OptionType     = OPTIONBYTE_WRP;
+    OptionsBytesStruct2.WRPStartOffset = EndPage + 1;
+  }
+  else if ((OptionsBytesStruct2.WRPStartOffset < StartPage) && (OptionsBytesStruct2.WRPEndOffset == EndPage))
+  {
+    /* Current area is bigger than the area to disable : */
+    /* - Start of area is lower than the first page to un-protect */
+    OptionsBytesStruct2.OptionType     = OPTIONBYTE_WRP;
+    OptionsBytesStruct2.WRPEndOffset   = StartPage - 1;
+  }
+  else if ((OptionsBytesStruct2.WRPStartOffset < StartPage) && (OptionsBytesStruct2.WRPEndOffset > EndPage))
+  {
+    /* Current area is bigger than the area to disable */
+    /* - Start of area is lower than the first page to un-protect */
+    /* - End of area is bigger than the last page to un-protect */
+    if (OptionsBytesStruct.WRPStartOffset > OptionsBytesStruct.WRPEndOffset)
+    {
+      /* Second area of the bank can be used */
+      OptionsBytesStruct.OptionType     = OPTIONBYTE_WRP;
+      OptionsBytesStruct.WRPStartOffset = EndPage + 1;
+      OptionsBytesStruct.WRPEndOffset   = OptionsBytesStruct2.WRPEndOffset;
+
+      OptionsBytesStruct2.OptionType     = OPTIONBYTE_WRP;
+      OptionsBytesStruct2.WRPEndOffset   = StartPage - 1;
+    }
+    else
+    {
+      /* Second area of the bank already used for WRP */
+      /* => Error : not possible to deactivate only the pages indicated */
+      while (1)
+      {
+        BSP_LED_On(LED3);
+      }
+    }
+  }
+
+#elif defined WRITE_PROTECTION_ENABLE
+  /* Check if desired pages are not yet write protected ***********************/
+  if ((OptionsBytesStruct.WRPStartOffset <= StartPage) && (OptionsBytesStruct.WRPEndOffset >= (StartPage - 1)))
+  {
+    /* Current area is adjacent to pages to be write protected */
+    if (OptionsBytesStruct.WRPEndOffset < EndPage)
+    {
+      /* Current area will be extended to include the pages to be write protected */
+      OptionsBytesStruct.OptionType     = OPTIONBYTE_WRP;
+      OptionsBytesStruct.WRPEndOffset   = EndPage;
+    }
+  }
+  else if ((OptionsBytesStruct.WRPStartOffset <= (EndPage + 1)) && (OptionsBytesStruct.WRPEndOffset >= EndPage))
+  {
+    /* Current area is adjacent to pages to be write protected */
+    if (OptionsBytesStruct.WRPStartOffset > StartPage)
+    {
+      /* Current area will be extended to include the pages to be write protected */
+      OptionsBytesStruct.OptionType     = OPTIONBYTE_WRP;
+      OptionsBytesStruct.WRPStartOffset = StartPage;
+    }
+  }
+  else if ((OptionsBytesStruct.WRPStartOffset > StartPage) && (OptionsBytesStruct.WRPEndOffset < EndPage))
+  {
+    /* Current area is included in pages to be write protected */
+    OptionsBytesStruct.OptionType     = OPTIONBYTE_WRP;
+    OptionsBytesStruct.WRPStartOffset = StartPage;
+    OptionsBytesStruct.WRPEndOffset   = EndPage;
+  }
+  else if ((OptionsBytesStruct2.WRPStartOffset <= StartPage) && (OptionsBytesStruct2.WRPEndOffset >= (StartPage - 1)))
+  {
+    /* Current area is adjacent to pages to be write protected */
+    if (OptionsBytesStruct2.WRPEndOffset < EndPage)
+    {
+      /* Current area will be extended to include the pages to be write protected */
+      OptionsBytesStruct2.OptionType     = OPTIONBYTE_WRP;
+      OptionsBytesStruct2.WRPEndOffset   = EndPage;
+    }
+  }
+  else if ((OptionsBytesStruct2.WRPStartOffset <= (EndPage + 1)) && (OptionsBytesStruct2.WRPEndOffset >= EndPage))
+  {
+    /* Current area is adjacent to pages to be write protected */
+    if (OptionsBytesStruct2.WRPStartOffset > StartPage)
+    {
+      /* Current area will be extended to include the pages to be write protected */
+      OptionsBytesStruct2.OptionType     = OPTIONBYTE_WRP;
+      OptionsBytesStruct2.WRPStartOffset = StartPage;
+    }
+  }
+  else if ((OptionsBytesStruct2.WRPStartOffset > StartPage) && (OptionsBytesStruct2.WRPEndOffset < EndPage))
+  {
+    /* Current area is included in pages to be write protected */
+    OptionsBytesStruct2.OptionType     = OPTIONBYTE_WRP;
+    OptionsBytesStruct2.WRPStartOffset = StartPage;
+    OptionsBytesStruct2.WRPEndOffset   = EndPage;
+  }
+  else if (OptionsBytesStruct.WRPStartOffset > OptionsBytesStruct.WRPEndOffset)
+  {
+    /* Current area is not used => it will be configured to protect the pages */
+    OptionsBytesStruct.OptionType     = OPTIONBYTE_WRP;
+    OptionsBytesStruct.WRPStartOffset = StartPage;
+    OptionsBytesStruct.WRPEndOffset   = EndPage;
+  }
+  else if (OptionsBytesStruct2.WRPStartOffset > OptionsBytesStruct2.WRPEndOffset)
+  {
+    /* Current area is not used => it will be configured to protect the pages */
+    OptionsBytesStruct2.OptionType     = OPTIONBYTE_WRP;
+    OptionsBytesStruct2.WRPStartOffset = StartPage;
+    OptionsBytesStruct2.WRPEndOffset   = EndPage;
+  }
+  else
+  {
+    /* No more area available to protect the pages */
+    /* => Error : not possible to activate the pages indicated */
+    while (1)
+    {
+      BSP_LED_On(LED3);
+    }
+  }
+
+#endif /* WRITE_PROTECTION_DISABLE */
+
+  /* Configure write protected pages */
+  if (OptionsBytesStruct.OptionType == OPTIONBYTE_WRP)
+  {
+    if(HAL_FLASHEx_OBProgram(&OptionsBytesStruct) != HAL_OK)
+    {
+      /* Error occurred while options bytes programming. **********************/
+      while (1)
+      {
+        BSP_LED_On(LED3);
+      }
+    }
+  }
+
+  if (OptionsBytesStruct2.OptionType == OPTIONBYTE_WRP)
+  {
+    if(HAL_FLASHEx_OBProgram(&OptionsBytesStruct2) != HAL_OK)
+    {
+      /* Error occurred while options bytes programming. **********************/
+      while (1)
+      {
+        BSP_LED_On(LED3);
+      }
+    }
+  }
+
+  /* Generate System Reset to load the new option byte values ***************/
+  if ((OptionsBytesStruct.OptionType == OPTIONBYTE_WRP) || (OptionsBytesStruct2.OptionType == OPTIONBYTE_WRP))
+  {
+    HAL_FLASH_OB_Launch();
+  }
+
+  /* Lock the Options Bytes *************************************************/
+  HAL_FLASH_OB_Lock();
+
+#ifdef FLASH_PAGE_PROGRAM
+  /* The selected pages are write protected *******************************/
+  if (((OptionsBytesStruct.WRPStartOffset  <= StartPage) && (OptionsBytesStruct.WRPEndOffset  >= EndPage)) ||
+      ((OptionsBytesStruct2.WRPStartOffset <= StartPage) && (OptionsBytesStruct2.WRPEndOffset >= EndPage)))
+  {
+    /* The desired pages are write protected */
+    /* Check that it is not allowed to write in this page */
+    Address = FLASH_USER_START_ADDR;
+    if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, Address, DATA_64) != HAL_OK)
+      {
+      /* Error returned during programming. */
+      /* Check that WRPERR flag is well set */
+      if ((HAL_FLASH_GetError() & HAL_FLASH_ERROR_WRP) != 0)
+      {
+        MemoryProgramStatus = FAILED;
+      }
+      else
+      {
+        /* Another error occurred.
+           User can add here some code to deal with this error */
+        while (1)
+        {
+          BSP_LED_On(LED3);
+        }
+      }
+    }
+    else
+    {
+      /* Write operation is successful. Should not occur
+         User can add here some code to deal with this error */
+      while (1)
+      {
+        BSP_LED_On(LED3);
+      }
+    }
+  }
+  else
+  {
+    /* The desired pages are not write protected */
+    /* Fill EraseInit structure************************************************/
+    EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
+    EraseInitStruct.Page        = StartPage;
+    EraseInitStruct.NbPages     = EndPage - StartPage + 1;
+
+    if (HAL_FLASHEx_Erase(&EraseInitStruct, &PageError) != HAL_OK)
+    {
+      /*
+        Error occurred while page erase.
+        User can add here some code to deal with this error.
+        PageError will contain the faulty page and then to know the code error on this page,
+        user can call function 'HAL_FLASH_GetError()'
+      */
+      while (1)
+      {
+        BSP_LED_On(LED3);
+      }
+    }
+
+    /* FLASH Word program of DATA_32 at addresses defined by FLASH_USER_START_ADDR and FLASH_USER_END_ADDR */
+    Address = FLASH_USER_START_ADDR;
+    while (Address < FLASH_USER_END_ADDR)
+    {
+      if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, Address, DATA_64) == HAL_OK)
+      {
+        Address = Address + 8;
+      }
+      else
+      {
+        /* Error occurred while writing data in Flash memory.
+           User can add here some code to deal with this error */
+        while (1)
+        {
+          BSP_LED_On(LED3);
+        }
+      }
+    }
+
+    /* Check the correctness of written data */
+    Address = FLASH_USER_START_ADDR;
+
+    while (Address < FLASH_USER_END_ADDR)
+    {
+      if((*(__IO uint32_t*) Address) != DATA_32)
+      {
+        MemoryProgramStatus = FAILED;
+      }
+      Address += 4;
+    }
+  }
+#endif /* FLASH_PAGE_PROGRAM */
+
+  /* Lock the Flash to disable the flash control register access (recommended
+     to protect the FLASH memory against possible unwanted operation) *********/
+  HAL_FLASH_Lock();
+
+  /*Check if there is an issue to program data*/
+  if (MemoryProgramStatus == PASSED)
+  {
+    /* No error detected. Switch on LED2*/
+    BSP_LED_On(LED2);
+  }
+  else
+  {
+    /* Error detected. Switch on LED1*/
+    BSP_LED_On(LED1);
+  }
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Gets the page of a given address
+  * @param  Addr: Address of the FLASH Memory
+  * @retval The page of a given address
+  */
+static uint32_t GetPage(uint32_t Addr)
+{
+  uint32_t page = 0;
+
+  if (Addr < (FLASH_BASE + FLASH_BANK_SIZE))
+  {
+    /* Bank 1 */
+    page = (Addr - FLASH_BASE) / FLASH_PAGE_SIZE;
+  }
+  else
+  {
+    /* Bank 2 */
+    page = (Addr - (FLASH_BASE + FLASH_BANK_SIZE)) / FLASH_PAGE_SIZE;
+  }
+
+  return page;
+}
+
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  while(1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..00262ec15
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FLASH/FLASH_WriteProtection/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..d574f6fa5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Src/stm32wbxx_it.c
@@ -0,0 +1,119 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    FLASH/FLASH_WriteProtection/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/readme.txt b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/readme.txt
new file mode 100644
index 000000000..e4f3d519b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/FLASH/FLASH_WriteProtection/readme.txt
@@ -0,0 +1,98 @@
+/**
+  @page FLASH_WriteProtection FLASH write protection
+
+  @verbatim
+  ******************************************************************************
+  * @file    FLASH/FLASH_WriteProtection/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the FLASH write protection example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to configure and use the FLASH HAL API to enable and disable the write
+protection of the internal Flash memory.
+
+At the beginning of the main program the HAL_Init() function is called to reset
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system clock (SYSCLK)
+to run at 64 MHz.
+
+  - If WRITE_PROTECTION_ENABLE is selected, the write protection will be enabled
+    for the defined pages.
+    To load the new option byte values, a system Reset is necessary, for this, the
+    function HAL_FLASH_OB_Launch() is used.
+
+  - If WRITE_PROTECTION_DISABLE is selected, the write protection will be disabled
+    for the defined pages.
+    To load the new option byte values, a system Reset is necessary, for this, the
+    function HAL_FLASH_OB_Launch() is used.
+
+  - If FLASH_PAGE_PROGRAM is selected, then an erase operation is done by filling
+    the erase init structure giving the starting erase page and the number of
+    pages to erase. At this stage, all these pages will be erased one by one separately.
+
+    @note: if problem occurs on a page, erase will be stopped and faulty page will
+    be returned to user (through variable 'PageError').
+
+    Once this operation is finished, double-word programming operation will be performed
+    in the Flash memory. The written data is then read back and checked.
+
+NUCLEO-WB35CE board's LED can be used to monitor the transfer status:
+ - LED2 is ON when there are no errors detected after programming
+    => should be the case when WRITE_PROTECTION_DISABLE flag is enabled
+ - LED1 is ON when there are errors detected after programming
+    => should be the case when WRITE_PROTECTION_ENABLE flag is enabled
+ - LED3 is ON when there is an issue during erase, program or OB program procedure
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate
+      delay (in milliseconds) based on variable incremented in SysTick ISR. This
+      implies that if HAL_Delay() is called from a peripheral ISR process, then
+      the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note The application need to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+Memory, FLASH, write protection, AREA, Sector, Mass Erase
+
+@par Directory contents
+
+  - FLASH/FLASH_WriteProtection/Inc/stm32wbxx_hal_conf.h        HAL Configuration file
+  - FLASH/FLASH_WriteProtection/Inc/stm32wbxx_it.h              Header for stm32wbxx_it.c
+  - FLASH/FLASH_WriteProtection/Inc/main.h                      Header for main.c module
+  - FLASH/FLASH_WriteProtection/Src/stm32wbxx_it.c              Interrupt handlers
+  - FLASH/FLASH_WriteProtection/Src/main.c                      Main program
+  - FLASH/FLASH_WriteProtection/Src/stm32wbxx_hal_msp.c         MSP initialization and de-initialization
+  - FLASH/FLASH_WriteProtection/Src/system_stm32wbxx.c          STM32WBxx system clock configuration file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+@par How to use it ?
+
+In order to make the program work, you must do the following:
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/.extSettings b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/GPIO_EXTI.ewd b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/GPIO_EXTI.ewd
new file mode 100644
index 000000000..ba77874f3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/GPIO_EXTI.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		GPIO_EXTI
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/GPIO_EXTI.ewp b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/GPIO_EXTI.ewp
new file mode 100644
index 000000000..c0514f255
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/GPIO_EXTI.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    GPIO_EXTI
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/Project.eww
new file mode 100644
index 000000000..6d4f47b72
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\GPIO_EXTI.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/GPIO_EXTI.ioc b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/GPIO_EXTI.ioc
new file mode 100644
index 000000000..1ccbd9fe3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/GPIO_EXTI.ioc
@@ -0,0 +1,106 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:true\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=GPIO_EXTI.ioc
+ProjectManager.ProjectName=GPIO_EXTI
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Inc/main.h
new file mode 100644
index 000000000..165eff5c2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    GPIO/GPIO_EXTI/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..19d12a61f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..7426b7e25
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Inc/stm32wbxx_it.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    GPIO/GPIO_EXTI/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void EXTI0_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/MDK-ARM/GPIO_EXTI.uvoptx b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/MDK-ARM/GPIO_EXTI.uvoptx
new file mode 100644
index 000000000..e5ccbce4e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/MDK-ARM/GPIO_EXTI.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    GPIO_EXTI
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/MDK-ARM/GPIO_EXTI.uvprojx b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/MDK-ARM/GPIO_EXTI.uvprojx
new file mode 100644
index 000000000..8ab824bc7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/MDK-ARM/GPIO_EXTI.uvprojx
@@ -0,0 +1,541 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      GPIO_EXTI
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          GPIO_EXTI\
+          GPIO_EXTI
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..b1b3eb42c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/.project
new file mode 100644
index 000000000..d89d4cc58
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	GPIO_EXTI
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			GPIO_EXTI.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/GPIO_EXTI.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Src/main.c
new file mode 100644
index 000000000..a3f75d564
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Src/main.c
@@ -0,0 +1,249 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    GPIO/GPIO_EXTI/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to configure and use GPIOs through
+  *          the STM32WBxx HAL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+static void EXTI0_IRQHandler_Config(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+  /* -1- Initialize LEDs mounted on NUCLEO-WB35CE board */
+  BSP_LED_Init(LED2);
+
+  /* -2- Configure External line 0 (connected to PA.00 pin) in interrupt mode */
+  EXTI0_IRQHandler_Config();
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Configures EXTI line 0 (connected to PA.00 pin) in interrupt mode
+  * @param  None
+  * @retval None
+  */
+static void EXTI0_IRQHandler_Config(void)
+{
+  GPIO_InitTypeDef   GPIO_InitStructure;
+
+
+  /* Enable GPIOA clock */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+  /* Configure PA.00 pin as input floating */
+  GPIO_InitStructure.Mode = GPIO_MODE_IT_FALLING;
+
+
+  GPIO_InitStructure.Pull = GPIO_PULLUP;
+  GPIO_InitStructure.Pin = GPIO_PIN_0;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+
+  /* Enable and set line 0 Interrupt to the lowest priority */
+  HAL_NVIC_SetPriority(EXTI0_IRQn, 2, 0);
+  HAL_NVIC_EnableIRQ(EXTI0_IRQn);
+}
+
+
+/**
+  * @brief EXTI line detection callbacks
+  * @param GPIO_Pin: Specifies the pins connected EXTI line
+  * @retval None
+  */
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  if (GPIO_Pin == GPIO_PIN_0)
+  {
+    /* Toggle LED2 */
+    BSP_LED_Toggle(LED2);
+  }
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..fc9051292
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,82 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    GPIO/GPIO_EXTI/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   This file provides code for the MSP Initialization
+  *          and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..dffb1b93c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Src/stm32wbxx_it.c
@@ -0,0 +1,187 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    GPIO/GPIO_EXTI/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles external line 0 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/readme.txt b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/readme.txt
new file mode 100644
index 000000000..90c63971d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_EXTI/readme.txt
@@ -0,0 +1,77 @@
+/**
+  @page GPIO_EXTI GPIO EXTI example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    GPIO/GPIO_EXTI/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the GPIO EXTI example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to configure external interrupt lines.
+
+In this example, one EXTI line (External line 0) is configured to generate
+an interrupt on each falling edge.
+In the interrupt routine a led connected to a specific GPIO pin is toggled.
+
+In this example:
+    - External line 0 is connected to PA.00 pin
+      - when falling edge is detected on External line 0 by pressing User push-button (SW1), LED2 toggles once
+
+On NUCLEO-WB35CE:
+    - External line 0 is connected to User push-button (SW1)
+
+In this example, HCLK is configured at 64 MHz.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The example needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+System, GPIO, EXTI, Output, Alternate function, Push-pull, Toggle
+
+@par Directory contents 
+
+  - GPIO/GPIO_EXTI/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - GPIO/GPIO_EXTI/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - GPIO/GPIO_EXTI/Inc/main.h                  Header for main.c module  
+  - GPIO/GPIO_EXTI/Src/stm32wbxx_it.c          Interrupt handlers
+  - GPIO/GPIO_EXTI/Src/stm32wbxx_hal_msp.c     HAL MSP file
+  - GPIO/GPIO_EXTI/Src/main.c                  Main program
+  - GPIO/GPIO_EXTI/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/.extSettings b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/GPIO_IOToggle.ewd b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/GPIO_IOToggle.ewd
new file mode 100644
index 000000000..9d2b30c8f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/GPIO_IOToggle.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		GPIO_IOToggle
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/GPIO_IOToggle.ewp b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/GPIO_IOToggle.ewp
new file mode 100644
index 000000000..7277cca0a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/GPIO_IOToggle.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    GPIO_IOToggle
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/Project.eww
new file mode 100644
index 000000000..eb6a8dfe0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\GPIO_IOToggle.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/GPIO_IOToggle.ioc b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/GPIO_IOToggle.ioc
new file mode 100644
index 000000000..eaf36fc09
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/GPIO_IOToggle.ioc
@@ -0,0 +1,106 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:true\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=GPIO_IOToggle.ioc
+ProjectManager.ProjectName=GPIO_IOToggle
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Inc/main.h
new file mode 100644
index 000000000..49360eb56
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    GPIO/GPIO_IOToggle/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..19d12a61f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..4b19246e3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Inc/stm32wbxx_it.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    GPIO/GPIO_IOToggle/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/MDK-ARM/GPIO_IOToggle.uvoptx b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/MDK-ARM/GPIO_IOToggle.uvoptx
new file mode 100644
index 000000000..a62d124d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/MDK-ARM/GPIO_IOToggle.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    GPIO_IOToggle
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/MDK-ARM/GPIO_IOToggle.uvprojx b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/MDK-ARM/GPIO_IOToggle.uvprojx
new file mode 100644
index 000000000..b20468120
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/MDK-ARM/GPIO_IOToggle.uvprojx
@@ -0,0 +1,541 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      GPIO_IOToggle
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          GPIO_IOToggle\
+          GPIO_IOToggle
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..5c65a5b75
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/.project
new file mode 100644
index 000000000..7c0a6b172
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	GPIO_IOToggle
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			GPIO_IOToggle.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/GPIO_IOToggle.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Src/main.c
new file mode 100644
index 000000000..460acda3e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Src/main.c
@@ -0,0 +1,224 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    GPIO/GPIO_IOToggle/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to configure and use GPIOs through
+  *          the STM32WBxx HAL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+static GPIO_InitTypeDef  GPIO_InitStruct;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+
+   /* -1- Enable GPIO Clock (to be able to program the configuration registers) */
+  LED2_GPIO_CLK_ENABLE();
+  LED1_GPIO_CLK_ENABLE();
+
+  /* -2- Configure IO in output push-pull mode to drive external LEDs */
+  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull  = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+
+  GPIO_InitStruct.Pin = LED2_PIN;
+  HAL_GPIO_Init(LED2_GPIO_PORT, &GPIO_InitStruct);
+  GPIO_InitStruct.Pin = LED1_PIN;
+  HAL_GPIO_Init(LED1_GPIO_PORT, &GPIO_InitStruct);
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    HAL_GPIO_TogglePin(LED2_GPIO_PORT, LED2_PIN);
+    /* Insert delay 100 ms */
+    HAL_Delay(100);
+    HAL_GPIO_TogglePin(LED1_GPIO_PORT, LED1_PIN);
+    /* Insert delay 100 ms */
+    HAL_Delay(100);
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  while(1) 
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* Infinite loop */
+  while (1)
+  {
+  }
+
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..1d6bb7052
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,82 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    GPIO/GPIO_IOToggle/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   This file provides code for the MSP Initialization 
+  *          and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..8121f9a97
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Src/stm32wbxx_it.c
@@ -0,0 +1,176 @@
+/* USER CODE BEGIN Header */
+/** 
+  ******************************************************************************
+  * @file    GPIO/GPIO_IOToggle/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/readme.txt b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/readme.txt
new file mode 100644
index 000000000..eeb826776
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/GPIO/GPIO_IOToggle/readme.txt
@@ -0,0 +1,70 @@
+/**
+  @page GPIO_IOToggle GPIO IO Toggle example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    GPIO/GPIO_IOToggle/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the GPIO IO Toggle example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to configure and use GPIOs through the HAL API.
+
+PB.00 and PB.05 IOs (configured in output pushpull mode) toggle in a forever loop.
+On NUCLEO-WB35CE board these IOs are connected to LED2 and LED1.
+
+In this example, HCLK is configured at 64 MHz.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The example needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+System, GPIO, Input, Output, Alternate function, Push-pull, Toggle
+
+@par Directory contents 
+
+  - GPIO/GPIO_IOToggle/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - GPIO/GPIO_IOToggle/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - GPIO/GPIO_IOToggle/Inc/main.h                  Header for main.c module  
+  - GPIO/GPIO_IOToggle/Src/stm32wbxx_it.c          Interrupt handlers
+  - GPIO/GPIO_IOToggle/Src/stm32wbxx_hal_msp.c     HAL MSP file
+  - GPIO/GPIO_IOToggle/Src/main.c                  Main program
+  - GPIO/GPIO_IOToggle/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/.extSettings b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/.extSettings
new file mode 100644
index 000000000..9099ff622
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=TIM
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/HAL_TimeBase.ewd b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/HAL_TimeBase.ewd
new file mode 100644
index 000000000..70c54b5b3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/HAL_TimeBase.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		HAL_TimeBase
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/HAL_TimeBase.ewp b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/HAL_TimeBase.ewp
new file mode 100644
index 000000000..39a5c479a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/HAL_TimeBase.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    HAL_TimeBase
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/Project.eww
new file mode 100644
index 000000000..e080a1818
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\HAL_TimeBase.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/HAL_TimeBase.ioc b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/HAL_TimeBase.ioc
new file mode 100644
index 000000000..4ebb7114a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/HAL_TimeBase.ioc
@@ -0,0 +1,106 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=HAL_TimeBase.ioc
+ProjectManager.ProjectName=HAL_TimeBase
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Inc/main.h
new file mode 100644
index 000000000..92361e0d3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase/Inc/main.h 
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..3e4ba1426
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..09fbec148
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Inc/stm32wbxx_it.h
@@ -0,0 +1,65 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase/Inc/stm32wbxx_it.h 
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void TIM2_IRQHandler(void);
+void EXTI0_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/MDK-ARM/HAL_TimeBase.uvoptx b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/MDK-ARM/HAL_TimeBase.uvoptx
new file mode 100644
index 000000000..3b688dd3b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/MDK-ARM/HAL_TimeBase.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    HAL_TimeBase
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/MDK-ARM/HAL_TimeBase.uvprojx b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/MDK-ARM/HAL_TimeBase.uvprojx
new file mode 100644
index 000000000..0b4591f4b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/MDK-ARM/HAL_TimeBase.uvprojx
@@ -0,0 +1,541 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      HAL_TimeBase
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          HAL_TimeBase\
+          HAL_TimeBase
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..e16cab805
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/.project
new file mode 100644
index 000000000..08f7b83f0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	HAL_TimeBase
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			HAL_TimeBase.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/HAL_TimeBase.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Src/main.c
new file mode 100644
index 000000000..5abe4b856
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Src/main.c
@@ -0,0 +1,357 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase/Src/main.c 
+  * @author  MCD Application Team
+  * @brief   This example describes how to configure HAL time base using
+  *          the STM32WBxx HAL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © COPYRIGHT(c) 2016 STMicroelectronics
    
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+TIM_HandleTypeDef htim2;
+/* Private variables ---------------------------------------------------------*/
+uint32_t                 uwIncrementState = 0;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+  /* Configure LED2 */
+  BSP_LED_Init(LED2);
+
+  /* Configure User push-button */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    /* Insert a 1s delay */
+    HAL_Delay(1000);
+    
+    /* Toggle LED2 */
+    BSP_LED_Toggle(LED2);
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  This function configures the TIM2 as a time base source. 
+  *         The time source is configured  to have 1ms time base with a dedicated 
+  *         Tick interrupt priority. 
+  * @note   This function is called  automatically at the beginning of program after
+  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). 
+  * @param  TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
+{
+  RCC_ClkInitTypeDef    clkconfig;
+  uint32_t              uwTimclock, uwAPB1Prescaler = 0;
+  uint32_t              uwPrescalerValue = 0;
+  uint32_t              pFLatency;
+  
+    /*Configure the TIM2 IRQ priority */
+  HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority ,0);
+  
+  /* Enable the TIM2 global Interrupt */
+  HAL_NVIC_EnableIRQ(TIM2_IRQn);
+  
+  /* Enable TIM2 clock */
+  __HAL_RCC_TIM2_CLK_ENABLE();
+  
+  /* Get clock configuration */
+  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
+  
+  /* Get APB1 prescaler */
+  uwAPB1Prescaler = clkconfig.APB1CLKDivider;
+  
+  /* Compute TIM2 clock */
+  if (uwAPB1Prescaler == RCC_HCLK_DIV1) 
+  {
+    uwTimclock = HAL_RCC_GetPCLK1Freq();
+  }
+  else
+  {
+    uwTimclock = 2*HAL_RCC_GetPCLK1Freq();
+  }
+
+  /* Compute the prescaler value to have TIM2 counter clock equal to 1MHz */
+  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1);
+  
+  /* Initialize TIM2 */
+  htim2.Instance = TIM2;
+    
+  /* Initialize TIMx peripheral as follow:
+       + Period = [(TIM2CLK/1000) - 1]. to have a (1/1000) s time base.
+       + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+       + ClockDivision = 0
+       + Counter direction = Up
+  */
+  htim2.Init.Period = (1000000 / 1000) - 1;
+  htim2.Init.Prescaler = uwPrescalerValue;
+  htim2.Init.ClockDivision = 0;
+  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+  if(HAL_TIM_Base_Init(&htim2) != HAL_OK)
+  {
+    /* Initialization Error */
+    Error_Handler();
+  }
+  
+  /* Start the TIM time Base generation in interrupt mode */
+  if(HAL_TIM_Base_Start_IT(&htim2) != HAL_OK)
+  {
+    /* Starting Error */
+    Error_Handler();
+  }
+ 
+
+   /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Suspend Tick increment.
+  * @note   Disable the tick increment by disabling TIM2 update interrupt.
+  * @param  None
+  * @retval None
+  */
+void HAL_SuspendTick(void)
+{
+  /* Disable TIM2 update Interrupt */
+  __HAL_TIM_DISABLE_IT(&htim2, TIM_IT_UPDATE);
+}
+
+/**
+  * @brief  Resume Tick increment.
+  * @note   Enable the tick increment by Enabling TIM2 update interrupt.
+  * @param  None
+  * @retval None
+  */
+void HAL_ResumeTick(void)
+{
+  /* Enable TIM2 Update interrupt */
+  __HAL_TIM_ENABLE_IT(&htim2, TIM_IT_UPDATE);
+}
+
+/**
+  * @brief  Period elapsed callback in non blocking mode
+  * @note   This function is called  when TIM2 interrupt took place, inside
+  * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+  * a global variable "uwTick" used as application time base.
+  * @param  htim : TIM handle
+  * @retval None
+  */
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  HAL_IncTick();
+}
+
+/**
+  * @brief EXTI line detection callback.
+  * @param GPIO_Pin: Specifies the pins connected EXTI line
+  * @retval None
+  */
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  if(GPIO_Pin == BUTTON_SW1_PIN)
+  {
+    if (uwIncrementState == 0)
+    {
+      /* Suspend tick increment */
+      HAL_SuspendTick();
+      
+      /* Change the Push button state */
+      uwIncrementState = 1;
+    }
+    else
+    {
+      /* Resume tick increment */
+      HAL_ResumeTick();
+      
+      /* Change the Push button state */
+      uwIncrementState = 0;
+    }
+  }  
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  while(1) 
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..cdd5c716f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32wbxx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..f14d81ce5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Src/stm32wbxx_it.c
@@ -0,0 +1,157 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and 
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+extern TIM_HandleTypeDef        htim2;
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief This function handles TIM2 global interrupt.
+  */
+void TIM2_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM2_IRQn 0 */
+
+  /* USER CODE END TIM2_IRQn 0 */
+  HAL_TIM_IRQHandler(&htim2);
+  /* USER CODE BEGIN TIM2_IRQn 1 */
+
+  /* USER CODE END TIM2_IRQn 1 */
+}
+
+/**
+* @brief  This function handles external line 0 interrupt request
+*/
+
+void EXTI0_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI15_10_IRQn 0 */
+
+  /* USER CODE END EXTI15_10_IRQn 0 */
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+  /* USER CODE BEGIN EXTI15_10_IRQn 1 */
+
+  /* USER CODE END EXTI15_10_IRQn 1 */
+}
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/readme.txt b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/readme.txt
new file mode 100644
index 000000000..643f8ecd3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase/readme.txt
@@ -0,0 +1,87 @@
+/**
+  @page HAL_TimeBase HAL Time base example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the HAL time base example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to customize HAL using a general-purpose timer as main source of time base, 
+instead of Systick.
+
+In this example the used timer is TIM2.
+
+Time base duration is kept unchanged: 1ms  since PPP_TIMEOUT_VALUEs are defined 
+and handled in milliseconds basis.
+
+The example brings, in user file, a new implementation of the following HAL weak functions:
+
+HAL_InitTick() 
+HAL_SuspendTick()
+HAL_ResumeTick()
+
+This implementation will overwrite native implementation from stm32wbxx_hal.c
+and so user functions will be invoked instead when called.
+
+The following time base functions are kept as implemented natively:
+
+HAL_IncTick()
+HAL_Delay()
+HAL_IncTick()
+
+When user pushes the User push-button (SW1), the Tick increment is suspended if it is already
+enabled, else it will be resumed.
+In an infinite loop, LED2 toggles spaced out over 1s delay, except when tick increment is suspended.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in TIM2 ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the TIM2 interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the TIM2 interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application need to ensure that the TIM2 time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+System, TIM, Time base, HAL
+
+@par Directory contents
+
+  - HAL/HAL_TimeBase/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - HAL/HAL_TimeBase/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - HAL/HAL_TimeBase/Inc/stm32wbxx.h             Header for main.c module  
+  - HAL/HAL_TimeBase/Src/stm32wbxx_it.c          Interrupt handlers
+  - HAL/HAL_TimeBase/Src/stm32wbxx_hal_msp.c     HAL MSP file
+  - HAL/HAL_TimeBase/Src/main.c                        Main program
+  - HAL/HAL_TimeBase/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices
+    
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.      
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example 
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/.extSettings b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/.extSettings
new file mode 100644
index 000000000..b647c1a3b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/.extSettings
@@ -0,0 +1,9 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=RTC
+[Groups]
+Application/User=../Src/stm32wbxx_hal_timebase_rtc_alarm.c;
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/HAL_TimeBase_RTC_ALARM.ewd b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/HAL_TimeBase_RTC_ALARM.ewd
new file mode 100644
index 000000000..d0e248d8b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/HAL_TimeBase_RTC_ALARM.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		HAL_TimeBase_RTC_ALARM
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/HAL_TimeBase_RTC_ALARM.ewp b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/HAL_TimeBase_RTC_ALARM.ewp
new file mode 100644
index 000000000..05a6d9721
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/HAL_TimeBase_RTC_ALARM.ewp
@@ -0,0 +1,1128 @@
+
+
+  3
+  
+    HAL_TimeBase_RTC_ALARM
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_timebase_rtc_alarm.c
+      
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/Project.eww
new file mode 100644
index 000000000..4befa9e2a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\HAL_TimeBase_RTC_ALARM.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/HAL_TimeBase_RTC_ALARM.ioc b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/HAL_TimeBase_RTC_ALARM.ioc
new file mode 100644
index 000000000..c47722306
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/HAL_TimeBase_RTC_ALARM.ioc
@@ -0,0 +1,106 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=HAL_TimeBase_RTC_ALARM.ioc
+ProjectManager.ProjectName=HAL_TimeBase_RTC_ALARM
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Inc/main.h
new file mode 100644
index 000000000..b6e80a67b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase_RTC_ALARM/Inc/main.h 
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..03d5d81d5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..6d1286318
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Inc/stm32wbxx_it.h
@@ -0,0 +1,64 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase_RTC_ALARM/Inc/stm32wbxx_it.h 
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void EXTI0_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/MDK-ARM/HAL_TimeBase_RTC_ALARM.uvoptx b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/MDK-ARM/HAL_TimeBase_RTC_ALARM.uvoptx
new file mode 100644
index 000000000..f0c1629b0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/MDK-ARM/HAL_TimeBase_RTC_ALARM.uvoptx
@@ -0,0 +1,533 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    HAL_TimeBase_RTC_ALARM
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_timebase_rtc_alarm.c
+      stm32wbxx_hal_timebase_rtc_alarm.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      5
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      6
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+      stm32wbxx_hal_rtc.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+      stm32wbxx_hal_rtc_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      24
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      25
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/MDK-ARM/HAL_TimeBase_RTC_ALARM.uvprojx b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/MDK-ARM/HAL_TimeBase_RTC_ALARM.uvprojx
new file mode 100644
index 000000000..82ea09d7a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/MDK-ARM/HAL_TimeBase_RTC_ALARM.uvprojx
@@ -0,0 +1,556 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      HAL_TimeBase_RTC_ALARM
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          HAL_TimeBase_RTC_ALARM\
+          HAL_TimeBase_RTC_ALARM
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              stm32wbxx_hal_timebase_rtc_alarm.c
+              1
+              ../Src/stm32wbxx_hal_timebase_rtc_alarm.c
+            
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_rtc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+            
+            
+              stm32wbxx_hal_rtc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..d1f4da165
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/.project
new file mode 100644
index 000000000..f3ead9d05
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/.project
@@ -0,0 +1,160 @@
+
+
+	HAL_TimeBase_RTC_ALARM
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			HAL_TimeBase_RTC_ALARM.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/HAL_TimeBase_RTC_ALARM.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_hal_timebase_rtc_alarm.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_timebase_rtc_alarm.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/main.c
new file mode 100644
index 000000000..63d0c6d5e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/main.c
@@ -0,0 +1,227 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase_RTC_ALARM/Src/main.c 
+  * @author  MCD Application Team
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+uint32_t uwIncrementState = 0;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch, instruction and Data caches
+       - Configure the RTC Alarm to generate an interrupt each 1 msec
+       - Set NVIC Group Priority to 4
+       - Global MSP (MCU Support Package) initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+  /* Configure LED2 */
+  BSP_LED_Init(LED2);  
+  
+  /* Configure User push-button (SW1) */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+  /* Insert a Delay of 500 ms and toggle LED2, in an infinite loop */
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* Insert a 500ms delay */
+    HAL_Delay(500);
+    
+    /* Toggle LED2 */
+    BSP_LED_Toggle(LED2);
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief EXTI line detection callback.
+  * @param GPIO_Pin: Specifies the pins connected EXTI line
+  * @retval None
+  */
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  if(GPIO_Pin == BUTTON_SW1_PIN)
+  {
+    if (uwIncrementState == 0)
+    {
+      /* Suspend tick increment */
+      HAL_SuspendTick();
+      
+      /* Change the Push button state */
+      uwIncrementState = 1;
+    }
+    else
+    {
+      /* Resume tick increment */
+      HAL_ResumeTick();
+      
+      /* Change the Push button state */
+      uwIncrementState = 0;
+    }
+  }  
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..cdd5c716f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32wbxx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/stm32wbxx_hal_timebase_rtc_alarm.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/stm32wbxx_hal_timebase_rtc_alarm.c
new file mode 100644
index 000000000..2eb21dae3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/stm32wbxx_hal_timebase_rtc_alarm.c
@@ -0,0 +1,301 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_timebase_rtc_alarm.c 
+  * @author  MCD Application Team
+  * @brief   HAL time base based on the hardware RTC_ALARM.
+  *
+  *          This file override the native HAL time base functions (defined as weak)
+  *          to use the RTC ALARM for time base generation:
+  *           + Intializes the RTC peripheral to increment the seconds registers each 1ms
+  *           + The alarm is configured to assert an interrupt when the RTC reaches 1ms 
+  *           + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00
+  *           + HSE (default), LSE or LSI can be selected as RTC clock source  
+ @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    This file must be copied to the application folder and modified as follows:
+    (#) Rename it to 'stm32wbxx_hal_timebase_rtc_alarm.c'
+    (#) Add this file and the RTC HAL drivers to your project and uncomment
+       HAL_RTC_MODULE_ENABLED define in stm32wbxx_hal_conf.h 
+
+    [..]
+    (@) HAL RTC alarm and HAL RTC wakeup drivers cant be used with low power modes:
+        The wake up capability of the RTC may be intrusive in case of prior low power mode
+        configuration requiring different wake up sources.
+        Application/Example behavior is no more guaranteed 
+    (@) The stm32wbxx_hal_timebase_tim use is recommended for the Applications/Examples
+          requiring low power modes
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+/** @addtogroup STM32WBxx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL_TimeBase_RTC_Alarm  HAL TimeBase RTC Alarm
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Uncomment the line below to select the appropriate RTC Clock source for your application: 
+  + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
+  + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
+                          precision.
+  + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing
+                          precision.
+  */
+#define RTC_CLOCK_SOURCE_HSE
+/* #define RTC_CLOCK_SOURCE_LSE */
+/* #define RTC_CLOCK_SOURCE_LSI */
+
+#ifdef RTC_CLOCK_SOURCE_HSE
+  #define RTC_ASYNCH_PREDIV       99U
+  #define RTC_SYNCH_PREDIV        9U
+  #define RCC_RTCCLKSOURCE_1MHZ   ((uint32_t)((uint32_t)RCC_BDCR_RTCSEL | (uint32_t)((HSE_VALUE/1000000U) << 16U)))
+#else /* RTC_CLOCK_SOURCE_LSE || RTC_CLOCK_SOURCE_LSI */
+  #define RTC_ASYNCH_PREDIV       0U
+  #define RTC_SYNCH_PREDIV        31U
+#endif /* RTC_CLOCK_SOURCE_HSE */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+extern RTC_HandleTypeDef hRTC_Handle;
+RTC_HandleTypeDef hRTC_Handle;
+
+/* Private function prototypes -----------------------------------------------*/
+void RTC_Alarm_IRQHandler(void);
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  This function configures the RTC_ALARMA as a time base source. 
+  *         The time source is configured  to have 1ms time base with a dedicated 
+  *         Tick interrupt priority. 
+  * @note   This function is called  automatically at the beginning of program after
+  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+  * @param  TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
+{
+  __IO uint32_t counter = 0U;
+
+  RCC_OscInitTypeDef        RCC_OscInitStruct;
+  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
+
+#ifdef RTC_CLOCK_SOURCE_LSE
+  /* Configue LSE as RTC clock soucre */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+#elif defined (RTC_CLOCK_SOURCE_LSI)
+  /* Configue LSI as RTC clock soucre */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+#elif defined (RTC_CLOCK_SOURCE_HSE)
+  /* Configue HSE as RTC clock soucre */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  /* Ensure that RTC is clocked by 1MHz */
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_1MHZ;
+#else
+#error Please select the RTC Clock source
+#endif /* RTC_CLOCK_SOURCE_LSE */
+
+  if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
+  {
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+    if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
+    {
+      /* Enable RTC Clock */
+      __HAL_RCC_RTC_ENABLE();
+      /* The time base should be 1ms
+         Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK 
+         HSE as RTC clock 
+           Time base = ((99 + 1) * (9 + 1)) / 1MHz
+                     = 1ms
+         LSE as RTC clock 
+           Time base = ((31 + 1) * (0 + 1)) / 32.768KHz
+                     = ~1ms
+         LSI as RTC clock 
+           Time base = ((31 + 1) * (0 + 1)) / 32KHz
+                     = 1ms
+      */
+      hRTC_Handle.Instance = RTC;
+      hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24;
+      hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
+      hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
+      hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
+      hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+      hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+      if (HAL_RTC_Init(&hRTC_Handle) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Disable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+
+      /* Disable the Alarm A interrupt */
+      __HAL_RTC_ALARMA_DISABLE(&hRTC_Handle);
+
+      /* Clear flag alarm A */
+      __HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF);
+
+      counter = 0U;
+      /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
+      while(__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAWF) == 0U)
+      {
+        if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
+        {
+          return HAL_ERROR;
+        }
+      }
+
+      hRTC_Handle.Instance->ALRMAR = (uint32_t)0x01U;
+
+      /* Configure the Alarm state: Enable Alarm */
+      __HAL_RTC_ALARMA_ENABLE(&hRTC_Handle);
+      /* Configure the Alarm interrupt */
+      __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
+
+      /* RTC Alarm Interrupt Configuration: EXTI configuration */
+      __HAL_RTC_ALARM_EXTI_ENABLE_IT();
+      __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
+
+      /* Check if the Initialization mode is set */
+      if((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+      {
+        /* Set the Initialization mode */
+        hRTC_Handle.Instance->ISR = (uint32_t)RTC_INIT_MASK;
+        counter = 0U;
+        while((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+        {
+          if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
+          {
+            return HAL_ERROR;
+          }
+        }
+      }
+      hRTC_Handle.Instance->DR = 0U;
+      hRTC_Handle.Instance->TR = 0U;
+
+      hRTC_Handle.Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+
+      /* Enable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+
+      HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority, 0U);
+      HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
+      return HAL_OK;
+    }
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Suspend Tick increment.
+  * @note   Disable the tick increment by disabling RTC ALARM interrupt.
+  * @retval None
+  */
+void HAL_SuspendTick(void)
+{
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+  /* Disable RTC ALARM update Interrupt */
+  __HAL_RTC_ALARM_DISABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+}
+
+/**
+  * @brief  Resume Tick increment.
+  * @note   Enable the tick increment by Enabling RTC ALARM interrupt.
+  * @retval None
+  */
+void HAL_ResumeTick(void)
+{
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+  /* Enable RTC ALARM Update interrupt */
+  __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+}
+
+/**
+  * @brief  ALARM A Event Callback in non blocking mode
+  * @note   This function is called  when RTC_ALARM interrupt took place, inside
+  * RTC_ALARM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+  * a global variable "uwTick" used as application time base.
+  * @param  hrtc : RTC handle
+  * @retval None
+  */
+void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+{
+  __IO uint32_t counter = 0U;
+
+  HAL_IncTick();
+
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Set the Initialization mode */
+  hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
+
+  while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+  {
+    if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
+    {
+      break;
+    }
+  }
+
+  hrtc->Instance->DR = 0U;
+  hrtc->Instance->TR = 0U;
+
+  hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+}
+
+/**
+  * @brief  This function handles RTC ALARM interrupt request.
+  * @retval None
+  */
+void RTC_Alarm_IRQHandler(void)
+{
+  HAL_RTC_AlarmIRQHandler(&hRTC_Handle);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..135003a05
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/stm32wbxx_it.c
@@ -0,0 +1,137 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase_RTC_ALARM/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles External External line 0 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/readme.txt b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/readme.txt
new file mode 100644
index 000000000..dfcfe6803
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_ALARM/readme.txt
@@ -0,0 +1,92 @@
+s/**
+  @page HAL_TimeBase_RTC_Alarm HAL TimeBase RTC Alarm
+  
+  @verbatim
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase_RTC_ALARM/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the HAL TimeBase RTC Alarm example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to customize HAL using RTC alarm as main source of time base, 
+instead of Systick.
+
+The User push-button (SW1) is used to suspend or Resume tick increment. 
+
+Each time the button is pressed; an interrupt is generated (External line 0)
+and in the ISR the uwIncrementState is checked:
+  1- If the uwIncrementState = 0: the tick increment is suspended by calling 
+     HAL_SuspendTick() API (RTC alarm interrupt is disabled).
+  2- If the uwIncrementState = 1: the tick increment is Resumed by calling 
+     HAL_ResumeTick() API(RTC alarm interrupt is enabled).
+
+The alarm is configured to assert an interrupt when the RTC reaches 1 ms 
+
+The example brings, in user file, a new implementation of the following HAL weak functions:
+
+HAL_InitTick() 
+HAL_SuspendTick()
+HAL_ResumeTick()
+
+This implementation will overwrite native implementation in stm32wbxx_hal.c
+and so user functions will be invoked instead when called.
+
+The following time base functions are kept as implemented natively:
+
+HAL_IncTick()
+HAL_Delay()
+
+In an infinite loop, LED2 toggles spaced out over 500ms delay, except when tick increment is suspended.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in HAL time base ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the HAL time base interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the HAL time base interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the HAL time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+System, RTC Alarm, Time base, HAL
+
+@par Directory contents
+
+  - HAL/HAL_TimeBase_RTC_ALARM/Inc/stm32wbxx_hal_conf.h               HAL configuration file
+  - HAL/HAL_TimeBase_RTC_ALARM/Inc/stm32wbxx_it.h                     Interrupt handlers header file
+  - HAL/HAL_TimeBase_RTC_ALARM/Inc/main.h                                   Header for main.c module  
+  - HAL/HAL_TimeBase_RTC_ALARM/Src/stm32wbxx_it.c                     Interrupt handlers
+  - HAL/HAL_TimeBase_RTC_ALARM/Src/main.c                                   Main program
+  - HAL/HAL_TimeBase_RTC_ALARM/Src/stm32wbxx_hal_msp.c                HAL MSP file
+  - HAL/HAL_TimeBase_RTC_ALARM/Src/stm32wbxx_hal_timebase_rtc_alarm.c HAL time base rtc alarm functions
+  - HAL/HAL_TimeBase_RTC_ALARM/Src/system_stm32wbxx.c                 STM32WBxx system source file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.      
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/.extSettings b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/.extSettings
new file mode 100644
index 000000000..77bad2400
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/.extSettings
@@ -0,0 +1,9 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=RTC
+[Groups]
+Application/User=../Src/stm32wbxx_hal_timebase_rtc_wakeup.c;
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/HAL_TimeBase_RTC_WKUP.ewd b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/HAL_TimeBase_RTC_WKUP.ewd
new file mode 100644
index 000000000..a9af46d82
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/HAL_TimeBase_RTC_WKUP.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		HAL_TimeBase_RTC_WKUP
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/HAL_TimeBase_RTC_WKUP.ewp b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/HAL_TimeBase_RTC_WKUP.ewp
new file mode 100644
index 000000000..a997235ea
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/HAL_TimeBase_RTC_WKUP.ewp
@@ -0,0 +1,1128 @@
+
+
+  3
+  
+    HAL_TimeBase_RTC_WKUP
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_timebase_rtc_wakeup.c
+      
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/Project.eww
new file mode 100644
index 000000000..add81d86b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\HAL_TimeBase_RTC_WKUP.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/HAL_TimeBase_RTC_WKUP.ioc b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/HAL_TimeBase_RTC_WKUP.ioc
new file mode 100644
index 000000000..6d7fe0b69
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/HAL_TimeBase_RTC_WKUP.ioc
@@ -0,0 +1,106 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=HAL_TimeBase_RTC_WKUP.ioc
+ProjectManager.ProjectName=HAL_TimeBase_RTC_WKUP
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Inc/main.h
new file mode 100644
index 000000000..ef6346b8c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase_RTC_WKUP/Inc/main.h 
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..03d5d81d5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..618f82a54
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Inc/stm32wbxx_it.h
@@ -0,0 +1,64 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase_RTC_WKUP/Inc/stm32wbxx_it.h 
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void EXTI0_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/MDK-ARM/HAL_TimeBase_RTC_WKUP.uvoptx b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/MDK-ARM/HAL_TimeBase_RTC_WKUP.uvoptx
new file mode 100644
index 000000000..5471d1933
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/MDK-ARM/HAL_TimeBase_RTC_WKUP.uvoptx
@@ -0,0 +1,533 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    HAL_TimeBase_RTC_WKUP
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_timebase_rtc_wakeup.c
+      stm32wbxx_hal_timebase_rtc_wakeup.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      5
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      6
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+      stm32wbxx_hal_rtc.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+      stm32wbxx_hal_rtc_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      24
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      25
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/MDK-ARM/HAL_TimeBase_RTC_WKUP.uvprojx b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/MDK-ARM/HAL_TimeBase_RTC_WKUP.uvprojx
new file mode 100644
index 000000000..73537bdf9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/MDK-ARM/HAL_TimeBase_RTC_WKUP.uvprojx
@@ -0,0 +1,556 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      HAL_TimeBase_RTC_WKUP
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          HAL_TimeBase_RTC_WKUP\
+          HAL_TimeBase_RTC_WKUP
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              stm32wbxx_hal_timebase_rtc_wakeup.c
+              1
+              ../Src/stm32wbxx_hal_timebase_rtc_wakeup.c
+            
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_rtc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+            
+            
+              stm32wbxx_hal_rtc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..d0b77d19e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/.project
new file mode 100644
index 000000000..debcbb8af
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/.project
@@ -0,0 +1,160 @@
+
+
+	HAL_TimeBase_RTC_WKUP
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			HAL_TimeBase_RTC_WKUP.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/HAL_TimeBase_RTC_WKUP.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_hal_timebase_rtc_wakeup.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_timebase_rtc_wakeup.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/main.c
new file mode 100644
index 000000000..477590343
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/main.c
@@ -0,0 +1,227 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase_RTC_WKUP/Src/main.c 
+  * @author  MCD Application Team
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+uint32_t uwIncrementState = 0;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch, instruction and Data caches
+       - Configure the RTC Wakeup to generate an interrupt each 1 msec
+       - Set NVIC Group Priority to 4
+       - Global MSP (MCU Support Package) initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+  /* Configure LED2 */
+  BSP_LED_Init(LED2);  
+  
+  /* Configure User push-button (SW1) */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+  /* Insert a Delay of 500 ms and toggle LED2, in an infinite loop */
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* Insert a 500ms delay */
+    HAL_Delay(500);
+    
+    /* Toggle LED2 */
+    BSP_LED_Toggle(LED2);
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief EXTI line detection callback.
+  * @param GPIO_Pin: Specifies the pins connected EXTI line
+  * @retval None
+  */
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  if(GPIO_Pin == BUTTON_SW1_PIN)
+  {
+    if (uwIncrementState == 0)
+    {
+      /* Suspend tick increment */
+      HAL_SuspendTick();
+      
+      /* Change the Push button state */
+      uwIncrementState = 1;
+    }
+    else
+    {
+      /* Resume tick increment */
+      HAL_ResumeTick();
+      
+      /* Change the Push button state */
+      uwIncrementState = 0;
+    }
+  }  
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..cdd5c716f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32wbxx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/stm32wbxx_hal_timebase_rtc_wakeup.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/stm32wbxx_hal_timebase_rtc_wakeup.c
new file mode 100644
index 000000000..705d1d32c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/stm32wbxx_hal_timebase_rtc_wakeup.c
@@ -0,0 +1,279 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_timebase_rtc_wakeup.c 
+  * @author  MCD Application Team
+  * @brief   HAL time base based on the hardware RTC_WAKEUP.
+  *    
+  *          This file overrides the native HAL time base functions (defined as weak)
+  *          to use the RTC WAKEUP for the time base generation:
+  *           + Intializes the RTC peripheral and configures the wakeup timer to be
+  *             incremented each 1ms
+  *           + The wakeup feature is configured to assert an interrupt each 1ms 
+  *           + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback
+  *           + HSE (default), LSE or LSI can be selected as RTC clock source
+ @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    This file must be copied to the application folder and modified as follows:
+    (#) Rename it to 'stm32wbxx_hal_timebase_rtc_wakeup.c'
+    (#) Add this file and the RTC HAL drivers to your project and uncomment
+       HAL_RTC_MODULE_ENABLED define in stm32wbxx_hal_conf.h 
+
+    [..]
+    (@) HAL RTC alarm and HAL RTC wakeup drivers cant be used with low power modes:
+        The wake up capability of the RTC may be intrusive in case of prior low power mode
+        configuration requiring different wake up sources.
+        Application/Example behavior is no more guaranteed 
+    (@) The stm32wbxx_hal_timebase_tim use is recommended for the Applications/Examples
+          requiring low power modes
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+/** @addtogroup STM32WBxx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL_TimeBase_RTC_WakeUp  HAL TimeBase RTC WakeUp
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Uncomment the line below to select the appropriate RTC Clock source for your application: 
+  + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
+  + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
+                          precision.
+  + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing
+                          precision.
+  */
+#define RTC_CLOCK_SOURCE_HSE
+/* #define RTC_CLOCK_SOURCE_LSE */
+/* #define RTC_CLOCK_SOURCE_LSI */
+
+#ifdef RTC_CLOCK_SOURCE_HSE
+  #define RTC_ASYNCH_PREDIV       99U
+  #define RTC_SYNCH_PREDIV        9U
+  #define RCC_RTCCLKSOURCE_1MHZ   ((uint32_t)((uint32_t)RCC_BDCR_RTCSEL | (uint32_t)((HSE_VALUE/1000000U) << 16U)))
+#else /* RTC_CLOCK_SOURCE_LSE || RTC_CLOCK_SOURCE_LSI */
+  #define RTC_ASYNCH_PREDIV       0U
+  #define RTC_SYNCH_PREDIV        31U
+#endif /* RTC_CLOCK_SOURCE_HSE */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+extern RTC_HandleTypeDef hRTC_Handle;
+RTC_HandleTypeDef        hRTC_Handle;
+
+/* Private function prototypes -----------------------------------------------*/
+void RTC_WKUP_IRQHandler(void);
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  This function configures the RTC_WKUP as a time base source. 
+  *         The time source is configured  to have 1ms time base with a dedicated 
+  *         Tick interrupt priority. 
+  *         Wakeup Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK 
+                             = 1ms
+  *         Wakeup Time = WakeupTimebase * WakeUpCounter (0 + 1) 
+                        = 1 ms
+  * @note   This function is called  automatically at the beginning of program after
+  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). 
+  * @param  TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
+{
+  __IO uint32_t counter = 0U;
+
+  RCC_OscInitTypeDef        RCC_OscInitStruct;
+  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
+
+#ifdef RTC_CLOCK_SOURCE_LSE
+  /* Configue LSE as RTC clock soucre */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+#elif defined (RTC_CLOCK_SOURCE_LSI)
+  /* Configue LSI as RTC clock soucre */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+#elif defined (RTC_CLOCK_SOURCE_HSE)
+  /* Configue HSE as RTC clock soucre */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  /* Ensure that RTC is clocked by 1MHz */
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_1MHZ;
+#else
+#error Please select the RTC Clock source
+#endif /* RTC_CLOCK_SOURCE_LSE */
+
+  if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
+  { 
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+    if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
+    {
+      /* Enable RTC Clock */
+      __HAL_RCC_RTC_ENABLE();
+      /* The time base should be 1ms 
+         Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK 
+         HSE as RTC clock 
+           Time base = ((99 + 1) * (9 + 1)) / 1Mhz
+                     = 1ms
+         LSE as RTC clock 
+           Time base = ((31 + 1) * (0 + 1)) / 32.768Khz
+                     = ~1ms
+         LSI as RTC clock 
+           Time base = ((31 + 1) * (0 + 1)) / 32Khz
+                     = 1ms
+      */
+      hRTC_Handle.Instance = RTC;
+      hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24;
+      hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
+      hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
+      hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
+      hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+      hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+      if (HAL_RTC_Init(&hRTC_Handle) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Disable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+
+      /* Disable the Wake-up Timer */
+      __HAL_RTC_WAKEUPTIMER_DISABLE(&hRTC_Handle);
+
+      /* In case of interrupt mode is used, the interrupt source must disabled */ 
+      __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle,RTC_IT_WUT);
+
+      /* Wait till RTC WUTWF flag is set  */
+      while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hRTC_Handle, RTC_FLAG_WUTWF) == 0U)
+      {
+        if(counter++ == (SystemCoreClock /48U)) 
+        {
+          return HAL_ERROR;
+        }
+      }
+
+      /* Clear PWR wake up Flag */
+      __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU);
+
+      /* Clear RTC Wake Up timer Flag */
+      __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_WUTF);
+
+      /* Configure the Wake-up Timer counter */
+      hRTC_Handle.Instance->WUTR = 0U;
+
+      /* Clear the Wake-up Timer clock source bits in CR register */
+      hRTC_Handle.Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+      /* Configure the clock source */
+      hRTC_Handle.Instance->CR |= (uint32_t)RTC_WAKEUPCLOCK_CK_SPRE_16BITS;
+
+      /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
+      __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
+
+      __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
+
+      /* Configure the Interrupt in the RTC_CR register */
+      __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle,RTC_IT_WUT);
+
+      /* Enable the Wake-up Timer */
+      __HAL_RTC_WAKEUPTIMER_ENABLE(&hRTC_Handle);
+
+      /* Enable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+
+      HAL_NVIC_SetPriority(RTC_WKUP_IRQn, TickPriority, 0U);
+      HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn); 
+      return HAL_OK;
+    }
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Suspend Tick increment.
+  * @note   Disable the tick increment by disabling RTC_WKUP interrupt.
+  * @retval None
+  */
+void HAL_SuspendTick(void)
+{
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+  /* Disable WAKE UP TIMER Interrupt */
+  __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT);
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+}
+
+/**
+  * @brief  Resume Tick increment.
+  * @note   Enable the tick increment by Enabling RTC_WKUP interrupt.
+  * @retval None
+  */
+void HAL_ResumeTick(void)
+{
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+  /* Enable  WAKE UP TIMER  interrupt */
+  __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle, RTC_IT_WUT);
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+}
+
+/**
+  * @brief  Wake Up Timer Event Callback in non blocking mode
+  * @note   This function is called  when RTC_WKUP interrupt took place, inside
+  * RTC_WKUP_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+  * a global variable "uwTick" used as application time base.
+  * @param  hrtc : RTC handle
+  * @retval None
+  */
+void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
+{
+  HAL_IncTick();
+}
+
+/**
+  * @brief  This function handles  WAKE UP TIMER  interrupt request.
+  * @retval None
+  */
+void RTC_WKUP_IRQHandler(void)
+{
+  HAL_RTCEx_WakeUpTimerIRQHandler(&hRTC_Handle);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..548ed8d0c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/stm32wbxx_it.c
@@ -0,0 +1,137 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase_RTC_WAKEUP/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles External External line 0 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/readme.txt b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/readme.txt
new file mode 100644
index 000000000..ec37c97c8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_RTC_WKUP/readme.txt
@@ -0,0 +1,93 @@
+/**
+  @page HAL_TimeBase_RTC_WKUP HAL TimeBase RTC WakeUp
+  
+  @verbatim
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase_RTC_WAKUP/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the HAL TimeBase RTC WakeUp example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to customize HAL using RTC wakeup as main source of time base, 
+instead of Systick.
+
+The User push-button (SW1) is used to suspend or resume tick increment. 
+
+Each time the button is pressed; an interrupt is generated (External line 0)
+and in the ISR the uwIncrementState is checked:
+  1- If the uwIncrementState = 0: the tick increment is suspended by calling 
+     HAL_SuspendTick() API (RTC wakeup timer interrupt is disabled).
+  2- If the uwIncrementState = 1: the tick increment is Resumed by calling 
+     HAL_ResumeTick() API(RTC wakeup timer interrupt is enabled).
+
+The wakeup feature is configured to assert an interrupt each 1ms  
+
+The example brings, in user file, a new implementation of the following HAL weak functions:
+
+HAL_InitTick() 
+HAL_SuspendTick()
+HAL_ResumeTick()
+
+This implementation will overwrite native implementation in stm32wbxx_hal.c
+and so user functions will be invoked instead when called.
+
+The following time base functions are kept as implemented natively:
+
+HAL_IncTick()
+HAL_Delay()
+
+In an infinite loop, LED2 toggles spaced out over 500ms delay, except when tick increment is suspended.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in HAL time base ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the HAL time base interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the HAL time base interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the HAL time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+System, RTC Wakeup, Time base, HAL
+
+@par Directory contents
+
+  - HAL/HAL_TimeBase_RTC_WKUP/Inc/stm32wbxx_hal_conf.h                HAL configuration file
+  - HAL/HAL_TimeBase_RTC_WKUP/Inc/stm32wbxx_it.h                      Interrupt handlers header file
+  - HAL/HAL_TimeBase_RTC_WKUP/Inc/main.h                                    Header for main.c module  
+  - HAL/HAL_TimeBase_RTC_WKUP/Src/stm32wbxx_it.c                      Interrupt handlers
+  - HAL/HAL_TimeBase_RTC_WKUP/Src/main.c                                    Main program
+  - HAL/HAL_TimeBase_RTC_WKUP/Src/stm32wbxx_hal_msp.c                 HAL MSP file
+  - HAL/HAL_TimeBase_RTC_WKUP/Src/stm32wbxx_hal_timebase_rtc_wakeup.c HAL time base functions
+  - HAL/HAL_TimeBase_RTC_WKUP/Src/system_stm32wbxx.c                  STM32WBxx system source file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.      
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/.extSettings b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/.extSettings
new file mode 100644
index 000000000..61b63bf5c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/.extSettings
@@ -0,0 +1,9 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Application/User=../Src/stm32wbxx_hal_timebase_tim.c;
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/HAL_TimeBase_TIM.ewd b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/HAL_TimeBase_TIM.ewd
new file mode 100644
index 000000000..9429a3061
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/HAL_TimeBase_TIM.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		HAL_TimeBase_TIM
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/HAL_TimeBase_TIM.ewp b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/HAL_TimeBase_TIM.ewp
new file mode 100644
index 000000000..3b7f81b96
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/HAL_TimeBase_TIM.ewp
@@ -0,0 +1,1122 @@
+
+
+  3
+  
+    HAL_TimeBase_TIM
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_timebase_tim.c
+      
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/Project.eww
new file mode 100644
index 000000000..78adb7295
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\HAL_TimeBase_TIM.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/HAL_TimeBase_TIM.ioc b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/HAL_TimeBase_TIM.ioc
new file mode 100644
index 000000000..11521cab7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/HAL_TimeBase_TIM.ioc
@@ -0,0 +1,109 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_tim17
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.TIM1_TRG_COM_TIM17_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.TimeBase=TIM1_TRG_COM_TIM17_IRQn
+NVIC.TimeBaseIP=TIM17
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=HAL_TimeBase_TIM.ioc
+ProjectManager.ProjectName=HAL_TimeBase_TIM
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_tim17.Mode=TIM17
+VP_SYS_VS_tim17.Signal=SYS_VS_tim17
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Inc/main.h
new file mode 100644
index 000000000..53b4e6f43
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase_TIM/Inc/main.h 
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..3e4ba1426
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..013d3bd10
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Inc/stm32wbxx_it.h
@@ -0,0 +1,65 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase_TIM/Inc/stm32wbxx_it.h 
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void TIM1_TRG_COM_TIM17_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+void EXTI0_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/MDK-ARM/HAL_TimeBase_TIM.uvoptx b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/MDK-ARM/HAL_TimeBase_TIM.uvoptx
new file mode 100644
index 000000000..8a2688d3d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/MDK-ARM/HAL_TimeBase_TIM.uvoptx
@@ -0,0 +1,133 @@
+
+
+	
+		HAL_TimeBase_TIM
+		0x4
+		ARM-ADS
+		
+			64000000
+			
+				1
+				1
+				0
+				1
+			
+			
+				1
+				65535
+				0
+				0
+				0
+			
+			
+				79
+				66
+				8
+				
+			
+			
+				1
+				1
+				1
+				0
+				1
+				1
+				0
+				1
+				0
+				0
+				0
+				0
+			
+			
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				0
+				0
+			
+			
+				0
+				0
+				1
+			
+			0
+			
+				0
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				0
+				0
+				13
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				STLink\ST-LINKIII-KEIL_SWO.dll
+			
+			
+				
+					0
+					ST-LINKIII-KEIL_SWO
+					-U-O142 -O2254 -S0 -C0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CE$CMSIS\Flash\STM32WB_M4.FLM)
+				
+				
+					0
+					
+					-U-O142 -O2254 -S0 -C0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CE$CMSIS\Flash\STM32WB_M4.FLM)
+				
+			
+			
+				0
+				1
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+			
+			
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/MDK-ARM/HAL_TimeBase_TIM.uvprojx b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/MDK-ARM/HAL_TimeBase_TIM.uvprojx
new file mode 100644
index 000000000..3a30c93a0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/MDK-ARM/HAL_TimeBase_TIM.uvprojx
@@ -0,0 +1,566 @@
+
+
+	1.1
+
+	
    ### uVision Project, (C) Keil Software
    
+
+	
+		 
+			HAL_TimeBase_TIM
+			0x4
+			ARM-ADS
+			
+				
+					STM32WB35CEUx
+					STMicroelectronics
+					IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					0
+					0
+					
+					
+					
+					
+					
+					
+						0
+						0
+						0
+						0
+						1
+					
+					HAL_TimeBase_TIM\
+					HAL_TimeBase_TIM
+					1
+					0
+					1
+					1
+					1
+					./HAL_TimeBase_TIM/
+					1
+					0
+					0
+					
+						0
+						0
+						
+						
+						0
+						0
+					
+					
+						0
+						0
+						
+						
+						0
+						0
+						0
+						0
+					
+					
+						0
+						0
+						
+						
+						0
+						0
+					
+					0
+					
+				
+				
+					0
+					0
+					0
+					0
+					0
+					1
+					0
+					0
+					0
+					0
+					3
+					
+					
+					
+				
+				
+					SARMCM3.DLL
+					-REMAP -MPU
+					DCM.DLL
+					-pCM4
+					SARMCM3.DLL
+					-MPU
+					TCM.DLL
+					-pCM4
+				
+				
+					
+						1
+						0
+						0
+						0
+						16
+					
+					
+						0
+						1
+						1
+						1
+						1
+						1
+						1
+						1
+						0
+						1
+					
+					
+						1
+						1
+						1
+						1
+						1
+						1
+						0
+						1
+						1 
+						1
+					
+					0
+					13
+					
+						
+						
+						
+						
+						
+					
+					
+						
+						
+						
+						
+						
+						STLink\ST-LINKIII-KEIL_SWO.dll
+					
+				
+				
+					
+						1
+						0
+						0
+						1
+						1
+						4107
+					
+					1
+					STLink\ST-LINKIII-KEIL_SWO.dll
+					
+					
+					
+					
+					
+					0
+				
+				
+					
+						0
+						1
+						1
+						1
+						1
+						1
+						1
+						1
+						0
+						1
+						1
+						0
+						1
+						1
+						0
+						0
+						1
+						1
+						1
+						1
+						1
+						1
+						1
+						1
+						1
+						0
+						0
+						"Cortex-M4"
+						
+						0
+						0
+						0
+						1
+						1
+						0
+						0
+						2
+						0
+						0
+						8
+						1
+						0
+						0
+						3
+						3
+						0
+						0
+						0
+						0
+						0
+						0
+						0
+						0
+						0
+						0
+						1
+						0
+						0
+						0
+						0
+						1
+						0
+						
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								
+								
+							
+							
+								1
+								
+								
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								1
+								0x0
+								0x0
+							
+							
+								1
+								0x0
+								0x0
+							
+							
+								1
+								0x0
+								0x0
+							
+							
+								1
+								
+								
+							
+							
+								1
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								
+								
+							
+							
+								0
+								0x0
+								0x0
+							
+						
+						
+					
+					
+						1
+						4
+						0
+						0
+						1
+						0
+						0
+						0
+						0
+						0
+						2
+						0
+						0
+						1
+						0
+						
+							
+							USE_HAL_DRIVER,STM32WB35xx
+							
+							../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+						
+					
+					
+						1
+						0
+						0
+						0
+						0
+						0
+						0
+						
+							
+							
+							
+							
+						
+					
+					
+						0
+						0
+						0
+						0
+						1
+						0
+						0x08000000
+						0x20000000
+						
+						stm32wb35xx_flash_cm4.sct
+						
+						
+						--diag_suppress L6314W
+						
+						
+					
+				
+			     
+			
+        
+					Application/MDK-ARM
+				
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+				
+				
+					::CMSIS
+				
+			
+          Application/User
+          
+            
+              stm32wbxx_hal_timebase_tim.c
+              1
+              ../Src/stm32wbxx_hal_timebase_tim.c
+            
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+
+		
+	
+	
+		
+		
+			
+				
+				
+					
+				
+			
+		
+		
+	
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..01a30358f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/.project
new file mode 100644
index 000000000..c59f85df9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/.project
@@ -0,0 +1,150 @@
+
+
+	HAL_TimeBase_TIM
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			HAL_TimeBase_TIM.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/HAL_TimeBase_TIM.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_hal_timebase_tim.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_timebase_tim.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/main.c
new file mode 100644
index 000000000..7d41ed8d5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/main.c
@@ -0,0 +1,260 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase_TIM/Src/main.c 
+  * @author  MCD Application Team
+  * @brief   This example describes how to configure HAL time base using
+  *          the STM32WBxx HAL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+uint32_t uwIncrementState = 0;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+ /* This sample code shows how to configure The HAL time base source base with a 
+    dedicated  Tick interrupt priority.
+    A general purpose timer(TIM2) is used instead of Systick  as source of  time base.  
+    Time base duration is fixed to 1ms  since PPP_TIMEOUT_VALUEs are defined and 
+    handled in milliseconds basis.
+    */
+
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Configure timer (TIM2) to generate an interrupt each 1 msec
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+  /* Configure LED2 */
+  BSP_LED_Init(LED2);
+
+  /* Configure User push-button */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  /* Insert a Delay of 1000 ms and toggle LED2, in an infinite loop */ 
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    /* Insert a 1s delay */
+    HAL_Delay(1000);
+    
+    /* Toggle LED2 */
+    BSP_LED_Toggle(LED2);
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief EXTI line detection callback.
+  * @param GPIO_Pin: Specifies the pins connected EXTI line
+  * @retval None
+  */
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  if(GPIO_Pin == BUTTON_SW1_PIN)
+  {
+    if (uwIncrementState == 0)
+    {
+      /* Suspend tick increment */
+      HAL_SuspendTick();
+      
+      /* Change the Push button state */
+      uwIncrementState = 1;
+    }
+    else
+    {
+      /* Resume tick increment */
+      HAL_ResumeTick();
+      
+      /* Change the Push button state */
+      uwIncrementState = 0;
+    }
+  }  
+}
+
+
+/* USER CODE END 4 */
+
+ /**
+  * @brief  Period elapsed callback in non blocking mode
+  * @note   This function is called  when TIM17 interrupt took place, inside
+  * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+  * a global variable "uwTick" used as application time base.
+  * @param  htim : TIM handle
+  * @retval None
+  */
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* USER CODE BEGIN Callback 0 */
+
+  /* USER CODE END Callback 0 */
+  if (htim->Instance == TIM17) {
+    HAL_IncTick();
+  }
+  /* USER CODE BEGIN Callback 1 */
+
+  /* USER CODE END Callback 1 */
+}
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  while(1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..cdd5c716f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32wbxx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/stm32wbxx_hal_timebase_tim.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/stm32wbxx_hal_timebase_tim.c
new file mode 100644
index 000000000..3a44c9fb1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/stm32wbxx_hal_timebase_tim.c
@@ -0,0 +1,114 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_timebase_TIM.c 
+  * @brief   HAL time base based on the hardware TIM.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+#include "stm32wbxx_hal_tim.h"
+ 
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+TIM_HandleTypeDef        htim17; 
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  This function configures the TIM17 as a time base source. 
+  *         The time source is configured  to have 1ms time base with a dedicated 
+  *         Tick interrupt priority. 
+  * @note   This function is called  automatically at the beginning of program after
+  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). 
+  * @param  TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  RCC_ClkInitTypeDef    clkconfig;
+  uint32_t              uwTimclock = 0;
+  uint32_t              uwPrescalerValue = 0;
+  uint32_t              pFLatency;
+  
+  /*Configure the TIM17 IRQ priority */
+  HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM17_IRQn, TickPriority ,0); 
+  
+  /* Enable the TIM17 global Interrupt */
+  HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM17_IRQn); 
+  
+  /* Enable TIM17 clock */
+  __HAL_RCC_TIM17_CLK_ENABLE();
+  
+  /* Get clock configuration */
+  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
+  
+  /* Compute TIM17 clock */
+  uwTimclock = HAL_RCC_GetPCLK2Freq();
+   
+  /* Compute the prescaler value to have TIM17 counter clock equal to 1MHz */
+  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1);
+  
+  /* Initialize TIM17 */
+  htim17.Instance = TIM17;
+  
+  /* Initialize TIMx peripheral as follow:
+  + Period = [(TIM17CLK/1000) - 1]. to have a (1/1000) s time base.
+  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+  + ClockDivision = 0
+  + Counter direction = Up
+  */
+  htim17.Init.Period = (1000000 / 1000) - 1;
+  htim17.Init.Prescaler = uwPrescalerValue;
+  htim17.Init.ClockDivision = 0;
+  htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
+  if(HAL_TIM_Base_Init(&htim17) == HAL_OK)
+  {
+    /* Start the TIM time Base generation in interrupt mode */
+    return HAL_TIM_Base_Start_IT(&htim17);
+  }
+  
+  /* Return function status */
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Suspend Tick increment.
+  * @note   Disable the tick increment by disabling TIM17 update interrupt.
+  * @param  None
+  * @retval None
+  */
+void HAL_SuspendTick(void)
+{
+  /* Disable TIM17 update Interrupt */
+  __HAL_TIM_DISABLE_IT(&htim17, TIM_IT_UPDATE);                                                  
+}
+
+/**
+  * @brief  Resume Tick increment.
+  * @note   Enable the tick increment by Enabling TIM17 update interrupt.
+  * @param  None
+  * @retval None
+  */
+void HAL_ResumeTick(void)
+{
+  /* Enable TIM17 Update interrupt */
+  __HAL_TIM_ENABLE_IT(&htim17, TIM_IT_UPDATE);
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..782f84518
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/stm32wbxx_it.c
@@ -0,0 +1,158 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase_TIM/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and 
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern TIM_HandleTypeDef htim17;
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt.
+  */
+void TIM1_TRG_COM_TIM17_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */
+
+  /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */
+  HAL_TIM_IRQHandler(&htim17);
+  /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */
+
+  /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief This function handles EXTI line 0 interrupts.
+  */
+
+void EXTI0_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI0_IRQn 0 */
+
+  /* USER CODE END EXTI0_IRQn 0 */
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+  /* USER CODE BEGIN EXTI0_IRQn 1 */
+
+  /* USER CODE END EXTI0_IRQn 1 */
+}
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/readme.txt b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/readme.txt
new file mode 100644
index 000000000..37386bd4a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/HAL/HAL_TimeBase_TIM/readme.txt
@@ -0,0 +1,88 @@
+/**
+  @page HAL_TimeBase_TIM HAL Time base example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    HAL/HAL_TimeBase_TIM/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the HAL time base example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to customize HAL using a general-purpose timer as main source of time base 
+instead of Systick.
+
+In this example the used timer is TIM2.
+
+Time base duration is kept unchanged: 1ms  since PPP_TIMEOUT_VALUEs are defined 
+and handled in milliseconds basis.
+
+The example brings, in user file, a new implementation of the following HAL weak functions:
+
+HAL_InitTick() 
+HAL_SuspendTick()
+HAL_ResumeTick()
+
+This implementation will overwrite native implementation in stm32wbxx_hal.c
+and so user functions will be invoked instead when called.
+
+The following time base functions are kept as implemented natively:
+
+HAL_IncTick()
+HAL_Delay()
+
+When user pushes the User push-button (SW1), the Tick increment is suspended if it is already
+enabled, else it will be resumed.
+In an infinite loop, LED2 toggles spaced out over 1s delay.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in TIM2 ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the TIM2 interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the TIM2 interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the TIM2 time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+System, TIM, Time base, HAL
+
+@par Directory contents
+
+  - HAL/HAL_TimeBase_TIM/Inc/stm32wbxx_hal_conf.h          HAL configuration file
+  - HAL/HAL_TimeBase_TIM/Inc/stm32wbxx_it.h                Interrupt handlers header file
+  - HAL/HAL_TimeBase_TIM/Inc/stm32wbxx.h                   Header for main.c module  
+  - HAL/HAL_TimeBase_TIM/Src/stm32wbxx_it.c                Interrupt handlers
+  - HAL/HAL_TimeBase_TIM/Src/main.c                              Main program
+  - HAL/HAL_TimeBase_TIM/Src/stm32wbxx_hal_msp.c           HAL MSP file
+  - HAL/HAL_TimeBase_TIM/Src/stm32wbxx_hal_timebase_tim.c  HAL time base functions
+  - HAL/HAL_TimeBase_TIM/Src/system_stm32wbxx.c            STM32WBxx system source file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.      
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/.extSettings b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/I2C_TwoBoards_ComDMA.ewd b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/I2C_TwoBoards_ComDMA.ewd
new file mode 100644
index 000000000..48a342c14
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/I2C_TwoBoards_ComDMA.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		I2C_TwoBoards_ComDMA
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/I2C_TwoBoards_ComDMA.ewp b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/I2C_TwoBoards_ComDMA.ewp
new file mode 100644
index 000000000..db58989d3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/I2C_TwoBoards_ComDMA.ewp
@@ -0,0 +1,1125 @@
+
+
+  3
+  
+    I2C_TwoBoards_ComDMA
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/Project.eww
new file mode 100644
index 000000000..11e41f228
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\I2C_TwoBoards_ComDMA.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/I2C_TwoBoards_ComDMA.ioc b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/I2C_TwoBoards_ComDMA.ioc
new file mode 100644
index 000000000..9f2a2d8b3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/I2C_TwoBoards_ComDMA.ioc
@@ -0,0 +1,170 @@
+#MicroXplorer Configuration settings - do not modify
+Dma.I2C1_RX.1.Direction=DMA_PERIPH_TO_MEMORY
+Dma.I2C1_RX.1.EventEnable=DISABLE
+Dma.I2C1_RX.1.Instance=DMA1_Channel2
+Dma.I2C1_RX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.I2C1_RX.1.MemInc=DMA_MINC_ENABLE
+Dma.I2C1_RX.1.Mode=DMA_NORMAL
+Dma.I2C1_RX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.I2C1_RX.1.PeriphInc=DMA_PINC_DISABLE
+Dma.I2C1_RX.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.I2C1_RX.1.Priority=DMA_PRIORITY_HIGH
+Dma.I2C1_RX.1.RequestNumber=1
+Dma.I2C1_RX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.I2C1_RX.1.SignalID=NONE
+Dma.I2C1_RX.1.SyncEnable=DISABLE
+Dma.I2C1_RX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.I2C1_RX.1.SyncRequestNumber=1
+Dma.I2C1_RX.1.SyncSignalID=NONE
+Dma.I2C1_TX.0.Direction=DMA_MEMORY_TO_PERIPH
+Dma.I2C1_TX.0.EventEnable=DISABLE
+Dma.I2C1_TX.0.Instance=DMA1_Channel1
+Dma.I2C1_TX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.I2C1_TX.0.MemInc=DMA_MINC_ENABLE
+Dma.I2C1_TX.0.Mode=DMA_NORMAL
+Dma.I2C1_TX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.I2C1_TX.0.PeriphInc=DMA_PINC_DISABLE
+Dma.I2C1_TX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.I2C1_TX.0.Priority=DMA_PRIORITY_LOW
+Dma.I2C1_TX.0.RequestNumber=1
+Dma.I2C1_TX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.I2C1_TX.0.SignalID=NONE
+Dma.I2C1_TX.0.SyncEnable=DISABLE
+Dma.I2C1_TX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.I2C1_TX.0.SyncRequestNumber=1
+Dma.I2C1_TX.0.SyncSignalID=NONE
+Dma.Request0=I2C1_TX
+Dma.Request1=I2C1_RX
+Dma.RequestsNb=2
+File.Version=6
+GPIO.groupedBy=
+I2C1.AddressingMode=I2C_ADDRESSINGMODE_10BIT
+I2C1.Analog_Filter=I2C_ANALOGFILTER_ENABLE
+I2C1.CustomTiming=Disabled
+I2C1.DualAddressMode=I2C_DUALADDRESS_DISABLE
+I2C1.GeneralCallMode=I2C_GENERALCALL_DISABLE
+I2C1.I2C_Coeff_DF=0x0
+I2C1.I2C_Fall_Time=2
+I2C1.I2C_Rise_Time=26
+I2C1.I2C_Speed_Mode=I2C_Fast_Plus
+I2C1.IPParameters=CustomTiming,I2C_Speed_Mode,Speed,I2C_Rise_Time,I2C_Fall_Time,I2C_Coeff_DF,Analog_Filter,NoStretchMode,GeneralCallMode,AddressingMode,DualAddressMode,OwnAddress,Timing
+I2C1.IPParametersWithoutCheck=OwnAddress
+I2C1.NoStretchMode=I2C_NOSTRETCH_DISABLE
+I2C1.OwnAddress=I2C_ADDRESS
+I2C1.Speed=1000
+I2C1.Timing=0x00400B27
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=DMA
+Mcu.IP1=I2C1
+Mcu.IP2=NVIC
+Mcu.IP3=RCC
+Mcu.IP4=SYS
+Mcu.IPNb=5
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB8
+Mcu.Pin1=PB9
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=I2C_ADDRESS,0x30F
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.DMA1_Channel2_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.I2C1_ER_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.I2C1_EV_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PB8.Mode=I2C
+PB8.Signal=I2C1_SCL
+PB9.Mode=I2C
+PB9.Signal=I2C1_SDA
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=I2C_TwoBoards_ComDMA.ioc
+ProjectManager.ProjectName=I2C_TwoBoards_ComDMA
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Inc/main.h
new file mode 100644
index 000000000..dd3e116ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Inc/main.h
@@ -0,0 +1,76 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    I2C/I2C_TwoBoards_ComDMA/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+#define COUNTOF(__BUFFER__)   (sizeof(__BUFFER__) / sizeof(*(__BUFFER__)))
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define I2C_ADDRESS 0x30F
+/* USER CODE BEGIN Private defines */
+
+/* Size of Transmission buffer */
+#define TXBUFFERSIZE                      (COUNTOF(aTxBuffer) - 1)
+/* Size of Reception buffer */
+#define RXBUFFERSIZE                      TXBUFFERSIZE
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..ee44a80b3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+#define HAL_I2C_MODULE_ENABLED
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..b3ae959e7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    I2C/I2C_TwoBoards_ComDMA/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void DMA1_Channel1_IRQHandler(void);
+void DMA1_Channel2_IRQHandler(void);
+void I2C1_EV_IRQHandler(void);
+void I2C1_ER_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/MDK-ARM/I2C_TwoBoards_ComDMA.uvoptx b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/MDK-ARM/I2C_TwoBoards_ComDMA.uvoptx
new file mode 100644
index 000000000..5d82a278e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/MDK-ARM/I2C_TwoBoards_ComDMA.uvoptx
@@ -0,0 +1,133 @@
+
+
+	
+		I2C_TwoBoards_ComDMA
+		0x4
+		ARM-ADS
+		
+			64000000
+			
+				1
+				1
+				0
+				1
+			
+			
+				1
+				65535
+				0
+				0
+				0
+			
+			
+				79
+				66
+				8
+				
+			
+			
+				1
+				1
+				1
+				0
+				1
+				1
+				0
+				1
+				0
+				0
+				0
+				0
+			
+			
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				0
+				0
+			
+			
+				0
+				0
+				1
+			
+			0
+			
+				0
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				0
+				0
+				13
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				STLink\ST-LINKIII-KEIL_SWO.dll
+			
+			
+				
+					0
+					ST-LINKIII-KEIL_SWO
+					-U-O142 -O2254 -S0 -C0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CE$CMSIS\Flash\STM32WB_M4.FLM)
+				
+				
+					0
+					
+					-U-O142 -O2254 -S0 -C0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CE$CMSIS\Flash\STM32WB_M4.FLM)
+				
+			
+			
+				0
+				1
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+			
+			
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/MDK-ARM/I2C_TwoBoards_ComDMA.uvprojx b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/MDK-ARM/I2C_TwoBoards_ComDMA.uvprojx
new file mode 100644
index 000000000..b09eab5c7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/MDK-ARM/I2C_TwoBoards_ComDMA.uvprojx
@@ -0,0 +1,571 @@
+
+
+	1.1
+
+	
    ### uVision Project, (C) Keil Software
    
+
+	
+		 
+			I2C_TwoBoards_ComDMA
+			0x4
+			ARM-ADS
+			
+				
+					STM32WB35CEUx
+					STMicroelectronics
+					IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					0
+					0
+					
+					
+					
+					
+					
+					
+						0
+						0
+						0
+						0
+						1
+					
+					I2C_TwoBoards_ComDMA\
+					I2C_TwoBoards_ComDMA
+					1
+					0
+					1
+					1
+					1
+					./I2C_TwoBoards_ComDMA/
+					1
+					0
+					0
+					
+						0
+						0
+						
+						
+						0
+						0
+					
+					
+						0
+						0
+						
+						
+						0
+						0
+						0
+						0
+					
+					
+						0
+						0
+						
+						
+						0
+						0
+					
+					0
+					
+				
+				
+					0
+					0
+					0
+					0
+					0
+					1
+					0
+					0
+					0
+					0
+					3
+					
+					
+					
+				
+				
+					SARMCM3.DLL
+					-REMAP -MPU
+					DCM.DLL
+					-pCM4
+					SARMCM3.DLL
+					-MPU
+					TCM.DLL
+					-pCM4
+				
+				
+					
+						1
+						0
+						0
+						0
+						16
+					
+					
+						0
+						1
+						1
+						1
+						1
+						1
+						1
+						1
+						0
+						1
+					
+					
+						1
+						1
+						1
+						1
+						1
+						1
+						0
+						1
+						1 
+						1
+					
+					0
+					13
+					
+						
+						
+						
+						
+						
+					
+					
+						
+						
+						
+						
+						
+						STLink\ST-LINKIII-KEIL_SWO.dll
+					
+				
+				
+					
+						1
+						0
+						0
+						1
+						1
+						4107
+					
+					1
+					STLink\ST-LINKIII-KEIL_SWO.dll
+					
+					
+					
+					
+					
+					0
+				
+				
+					
+						0
+						1
+						1
+						1
+						1
+						1
+						1
+						1
+						0
+						1
+						1
+						0
+						1
+						1
+						0
+						0
+						1
+						1
+						1
+						1
+						1
+						1
+						1
+						1
+						1
+						0
+						0
+						"Cortex-M4"
+						
+						0
+						0
+						0
+						1
+						1
+						0
+						0
+						2
+						0
+						0
+						8
+						1
+						0
+						0
+						3
+						3
+						0
+						0
+						0
+						0
+						0
+						0
+						0
+						0
+						0
+						0
+						1
+						0
+						0
+						0
+						0
+						1
+						0
+						
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								
+								
+							
+							
+								1
+								
+								
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								1
+								0x0
+								0x0
+							
+							
+								1
+								0x0
+								0x0
+							
+							
+								1
+								0x0
+								0x0
+							
+							
+								1
+								
+								
+							
+							
+								1
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								
+								
+							
+							
+								0
+								0x0
+								0x0
+							
+						
+						
+					
+					
+						1
+						4
+						0
+						0
+						1
+						0
+						0
+						0
+						0
+						0
+						2
+						0
+						0
+						1
+						0
+						
+							
+							USE_HAL_DRIVER,STM32WB35xx
+							
+							../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+						
+					
+					
+						1
+						0
+						0
+						0
+						0
+						0
+						0
+						
+							
+							
+							
+							
+						
+					
+					
+						0
+						0
+						0
+						0
+						1
+						0
+						0x08000000
+						0x20000000
+						
+						stm32wb35xx_flash_cm4.sct
+						
+						
+						--diag_suppress L6314W
+						
+						
+					
+				
+			     
+			
+        
+					Application/MDK-ARM
+				
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+				
+				
+					::CMSIS
+				
+			
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_i2c.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
+            
+            
+              stm32wbxx_hal_i2c_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+
+		
+	
+	
+		
+		
+			
+				
+				
+					
+				
+			
+		
+		
+	
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..708cea2f8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/.project
new file mode 100644
index 000000000..16534530c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/.project
@@ -0,0 +1,155 @@
+
+
+	I2C_TwoBoards_ComDMA
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			I2C_TwoBoards_ComDMA.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/I2C_TwoBoards_ComDMA.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_i2c.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_i2c_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Src/main.c
new file mode 100644
index 000000000..9760e8306
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Src/main.c
@@ -0,0 +1,525 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    I2C/I2C_TwoBoards_ComDMA/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use STM32WBxx I2C HAL API to transmit
+  *          and receive a data buffer with a communication process based on
+  *          DMA transfer.
+  *          The communication is done using 2 Boards.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* Uncomment this line to use the board as master, if not it is used as slave */
+//#define MASTER_BOARD
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+I2C_HandleTypeDef hi2c1;
+DMA_HandleTypeDef hdma_i2c1_tx;
+DMA_HandleTypeDef hdma_i2c1_rx;
+
+/* USER CODE BEGIN PV */
+/* Buffer used for transmission */
+uint8_t aTxBuffer[] = " ****I2C_TwoBoards communication based on DMA****  ****I2C_TwoBoards communication based on DMA****  ****I2C_TwoBoards communication based on DMA**** ";
+
+/* Buffer used for reception */
+uint8_t aRxBuffer[RXBUFFERSIZE];
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+static void MX_I2C1_Init(void);
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+static uint16_t Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_I2C1_Init();
+  /* USER CODE BEGIN 2 */
+  /* Configure LED2 and LED3 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+
+
+#ifdef MASTER_BOARD
+
+  /* Configure User push-button (SW1) */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_GPIO);
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  /* Wait for User push-button (SW1) press before starting the Communication */
+  while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_RESET)
+  {
+  }
+
+  /* Delay to avoid that possible signal rebound is taken as button release */
+  HAL_Delay(50);
+
+  /* Wait for User push-button (SW1) release before starting the Communication */
+  while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_SET)
+  {
+  }
+
+  /* The board sends the message and expects to receive it back */
+
+  /*##- Start the transmission process #####################################*/
+  /* While the I2C in reception process, user can transmit data through
+     "aTxBuffer" buffer */
+  do
+  {
+    if (HAL_I2C_Master_Transmit_DMA(&hi2c1, (uint16_t)I2C_ADDRESS, (uint8_t *)aTxBuffer, TXBUFFERSIZE) != HAL_OK)
+    {
+      /* Error_Handler() function is called when error occurs. */
+      Error_Handler();
+    }
+
+    /*##- Wait for the end of the transfer #################################*/
+    /*  Before starting a new communication transfer, you need to check the current
+        state of the peripheral; if its busy you need to wait for the end of current
+        transfer before starting a new one.
+        For simplicity reasons, this example is just waiting till the end of the
+        transfer, but application may perform other tasks while transfer operation
+        is ongoing. */
+    while (HAL_I2C_GetState(&hi2c1) != HAL_I2C_STATE_READY)
+    {
+    }
+
+    /* When Acknowledge failure occurs (Slave don't acknowledge it's address)
+       Master restarts communication */
+  }
+  while (HAL_I2C_GetError(&hi2c1) == HAL_I2C_ERROR_AF);
+
+  /* Wait for User push-button (SW1) press before starting the Communication */
+  while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_RESET)
+  {
+  }
+
+  /* Delay to avoid that possible signal rebound is taken as button release */
+  HAL_Delay(50);
+
+  /* Wait for User push-button (SW1) release before starting the Communication */
+  while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_SET)
+  {
+  }
+
+  /*##- Put I2C peripheral in reception process ###########################*/
+  do
+  {
+    if (HAL_I2C_Master_Receive_DMA(&hi2c1, (uint16_t)I2C_ADDRESS, (uint8_t *)aRxBuffer, RXBUFFERSIZE) != HAL_OK)
+    {
+      /* Error_Handler() function is called when error occurs. */
+      Error_Handler();
+    }
+
+    /*##- Wait for the end of the transfer #################################*/
+    /*  Before starting a new communication transfer, you need to check the current
+        state of the peripheral; if its busy you need to wait for the end of current
+        transfer before starting a new one.
+        For simplicity reasons, this example is just waiting till the end of the
+        transfer, but application may perform other tasks while transfer operation
+        is ongoing. */
+    while (HAL_I2C_GetState(&hi2c1) != HAL_I2C_STATE_READY)
+    {
+    }
+
+    /* When Acknowledge failure occurs (Slave don't acknowledge it's address)
+       Master restarts communication */
+  }
+  while (HAL_I2C_GetError(&hi2c1) == HAL_I2C_ERROR_AF);
+
+#else
+
+  /* The board receives the message and sends it back */
+
+  /*##- Put I2C peripheral in reception process ###########################*/
+  if (HAL_I2C_Slave_Receive_DMA(&hi2c1, (uint8_t *)aRxBuffer, RXBUFFERSIZE) != HAL_OK)
+  {
+    /* Transfer error in reception process */
+    Error_Handler();
+  }
+
+  /*##- Wait for the end of the transfer ###################################*/
+  /*  Before starting a new communication transfer, you need to check the current
+      state of the peripheral; if its busy you need to wait for the end of current
+      transfer before starting a new one.
+      For simplicity reasons, this example is just waiting till the end of the
+      transfer, but application may perform other tasks while transfer operation
+      is ongoing. */
+  while (HAL_I2C_GetState(&hi2c1) != HAL_I2C_STATE_READY)
+  {
+  }
+
+  /*##- Start the transmission process #####################################*/
+  /* While the I2C in reception process, user can transmit data through
+     "aTxBuffer" buffer */
+  if (HAL_I2C_Slave_Transmit_DMA(&hi2c1, (uint8_t *)aTxBuffer, TXBUFFERSIZE) != HAL_OK)
+  {
+    /* Transfer error in transmission process */
+    Error_Handler();
+  }
+
+#endif /* MASTER_BOARD */
+
+  /*##- Wait for the end of the transfer ###################################*/
+  /*  Before starting a new communication transfer, you need to check the current
+      state of the peripheral; if its busy you need to wait for the end of current
+      transfer before starting a new one.
+      For simplicity reasons, this example is just waiting till the end of the
+      transfer, but application may perform other tasks while transfer operation
+      is ongoing. */
+  while (HAL_I2C_GetState(&hi2c1) != HAL_I2C_STATE_READY)
+  {
+  }
+
+  /*##- Compare the sent and received buffers ##############################*/
+  if (Buffercmp((uint8_t *)aTxBuffer, (uint8_t *)aRxBuffer, RXBUFFERSIZE))
+  {
+    /* Processing Error */
+    Error_Handler();
+  }
+
+  /* Infinite loop */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief I2C1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_I2C1_Init(void)
+{
+
+  /* USER CODE BEGIN I2C1_Init 0 */
+
+  /* USER CODE END I2C1_Init 0 */
+
+  /* USER CODE BEGIN I2C1_Init 1 */
+
+  /* USER CODE END I2C1_Init 1 */
+  hi2c1.Instance = I2C1;
+  hi2c1.Init.Timing = 0x00400B27;
+  hi2c1.Init.OwnAddress1 = I2C_ADDRESS;
+  hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_10BIT;
+  hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+  hi2c1.Init.OwnAddress2 = 0;
+  hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+  hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+  hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+  if (HAL_I2C_Init(&hi2c1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Analogue filter 
+  */
+  if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Digital filter 
+  */
+  if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0x0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** I2C Enable Fast Mode Plus 
+  */
+  HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C1);
+  /* USER CODE BEGIN I2C1_Init 2 */
+
+  /* USER CODE END I2C1_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+  /* DMA1_Channel2_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Compares two buffers.
+  * @param  pBuffer1, pBuffer2: buffers to be compared.
+  * @param  BufferLength: buffer's length
+  * @retval 0  : pBuffer1 identical to pBuffer2
+  *         >0 : pBuffer1 differs from pBuffer2
+  */
+static uint16_t Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
+{
+  while (BufferLength--)
+  {
+    if ((*pBuffer1) != *pBuffer2)
+    {
+      return BufferLength;
+    }
+    pBuffer1++;
+    pBuffer2++;
+  }
+
+  return 0;
+}
+
+/**
+  * @brief  Tx Transfer completed callback.
+  * @param  I2cHandle: I2C handle.
+  * @note   This example shows a simple way to report end of DMA Tx transfer, and
+  *         you can add your own implementation.
+  * @retval None
+  */
+#ifdef MASTER_BOARD
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *I2cHandle)
+{
+  /* Toggle LED2: Transfer in transmission process is correct */
+  BSP_LED_Toggle(LED2);
+}
+#else
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *I2cHandle)
+{
+  /* Toggle LED2: Transfer in transmission process is correct */
+  BSP_LED_Toggle(LED2);
+}
+#endif /* MASTER_BOARD */
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  I2cHandle: I2C handle
+  * @note   This example shows a simple way to report end of DMA Rx transfer, and
+  *         you can add your own implementation.
+  * @retval None
+  */
+#ifdef MASTER_BOARD
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *I2cHandle)
+{
+  /* Toggle LED2: Transfer in reception process is correct */
+  BSP_LED_Toggle(LED2);
+}
+#else
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *I2cHandle)
+{
+  /* Toggle LED2: Transfer in reception process is correct */
+  BSP_LED_Toggle(LED2);
+}
+#endif /* MASTER_BOARD */
+
+/**
+  * @brief  I2C error callbacks.
+  * @param  I2cHandle: I2C handle
+  * @note   This example shows a simple way to report transfer error, and you can
+  *         add your own implementation.
+  * @retval None
+  */
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *I2cHandle)
+{
+  /** Error_Handler() function is called when error occurs.
+    * 1- When Slave doesn't acknowledge its address, Master restarts communication.
+    * 2- When Master doesn't acknowledge the last data transferred, Slave doesn't care in this example.
+    */
+  if (HAL_I2C_GetError(I2cHandle) != HAL_I2C_ERROR_AF)
+  {
+    /* Turn Off LED2 */
+    BSP_LED_Off(LED2);
+
+    /* Turn On LED3 */
+    BSP_LED_On(LED3);
+  }
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  Error_Handler();
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..d0f83f711
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,202 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    I2C/I2C_TwoBoards_ComDMA/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_i2c1_tx;
+
+extern DMA_HandleTypeDef hdma_i2c1_rx;
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief I2C MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hi2c: I2C handle pointer
+* @retval None
+*/
+void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hi2c->Instance==I2C1)
+  {
+  /* USER CODE BEGIN I2C1_MspInit 0 */
+        RCC_PeriphCLKInitTypeDef  RCC_PeriphCLKInitStruct;
+
+    /*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/
+    RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
+    RCC_PeriphCLKInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_SYSCLK;
+    HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
+  /* USER CODE END I2C1_MspInit 0 */
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**I2C1 GPIO Configuration    
+    PB8     ------> I2C1_SCL
+    PB9     ------> I2C1_SDA 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* Peripheral clock enable */
+    __HAL_RCC_I2C1_CLK_ENABLE();
+  
+    /* I2C1 DMA Init */
+    /* I2C1_TX Init */
+    hdma_i2c1_tx.Instance = DMA1_Channel1;
+    hdma_i2c1_tx.Init.Request = DMA_REQUEST_I2C1_TX;
+    hdma_i2c1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_i2c1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_i2c1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_i2c1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_i2c1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_i2c1_tx.Init.Mode = DMA_NORMAL;
+    hdma_i2c1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_i2c1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(hi2c,hdmatx,hdma_i2c1_tx);
+
+    /* I2C1_RX Init */
+    hdma_i2c1_rx.Instance = DMA1_Channel2;
+    hdma_i2c1_rx.Init.Request = DMA_REQUEST_I2C1_RX;
+    hdma_i2c1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_i2c1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_i2c1_rx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_i2c1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_i2c1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_i2c1_rx.Init.Mode = DMA_NORMAL;
+    hdma_i2c1_rx.Init.Priority = DMA_PRIORITY_HIGH;
+    if (HAL_DMA_Init(&hdma_i2c1_rx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(hi2c,hdmarx,hdma_i2c1_rx);
+
+    /* I2C1 interrupt Init */
+    HAL_NVIC_SetPriority(I2C1_EV_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(I2C1_EV_IRQn);
+    HAL_NVIC_SetPriority(I2C1_ER_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(I2C1_ER_IRQn);
+  /* USER CODE BEGIN I2C1_MspInit 1 */
+
+  /* USER CODE END I2C1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief I2C MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hi2c: I2C handle pointer
+* @retval None
+*/
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
+{
+  if(hi2c->Instance==I2C1)
+  {
+  /* USER CODE BEGIN I2C1_MspDeInit 0 */
+
+  /* USER CODE END I2C1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_I2C1_CLK_DISABLE();
+  
+    /**I2C1 GPIO Configuration    
+    PB8     ------> I2C1_SCL
+    PB9     ------> I2C1_SDA 
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9);
+
+    /* I2C1 DMA DeInit */
+    HAL_DMA_DeInit(hi2c->hdmatx);
+    HAL_DMA_DeInit(hi2c->hdmarx);
+
+    /* I2C1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(I2C1_EV_IRQn);
+    HAL_NVIC_DisableIRQ(I2C1_ER_IRQn);
+  /* USER CODE BEGIN I2C1_MspDeInit 1 */
+
+  /* USER CODE END I2C1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..48dd21a4c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Src/stm32wbxx_it.c
@@ -0,0 +1,206 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    I2C/I2C_TwoBoards_ComDMA/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_i2c1_tx;
+extern DMA_HandleTypeDef hdma_i2c1_rx;
+extern I2C_HandleTypeDef hi2c1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles DMA1 channel1 global interrupt.
+  */
+void DMA1_Channel1_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel1_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_i2c1_tx);
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA1 channel2 global interrupt.
+  */
+void DMA1_Channel2_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel2_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_i2c1_rx);
+  /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel2_IRQn 1 */
+}
+
+/**
+  * @brief This function handles I2C1 event interrupt.
+  */
+void I2C1_EV_IRQHandler(void)
+{
+  /* USER CODE BEGIN I2C1_EV_IRQn 0 */
+
+  /* USER CODE END I2C1_EV_IRQn 0 */
+  HAL_I2C_EV_IRQHandler(&hi2c1);
+  /* USER CODE BEGIN I2C1_EV_IRQn 1 */
+
+  /* USER CODE END I2C1_EV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles I2C1 error interrupt.
+  */
+void I2C1_ER_IRQHandler(void)
+{
+  /* USER CODE BEGIN I2C1_ER_IRQn 0 */
+
+  /* USER CODE END I2C1_ER_IRQn 0 */
+  HAL_I2C_ER_IRQHandler(&hi2c1);
+  /* USER CODE BEGIN I2C1_ER_IRQn 1 */
+
+  /* USER CODE END I2C1_ER_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/readme.txt b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/readme.txt
new file mode 100644
index 000000000..d30f86272
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComDMA/readme.txt
@@ -0,0 +1,134 @@
+/**
+  @page I2C_TwoBoards_ComDMA I2C Two Boards Communication DMA example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    I2C/I2C_TwoBoards_ComDMA/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the I2C Two Boards Communication DMA example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to handle I2C data buffer transmission/reception between two boards, 
+via DMA.
+
+Board: NUCLEO-WB35CE (embeds a STM32WB35CE device)
+SCL Pin: PB8 (CN5, pin10)
+SDA Pin: PB9 (CN5, pin9)
+
+   _________________________                       _________________________ 
+  |           ______________|                     |______________           |
+  |          |I2C1          |                     |          I2C1|          |
+  |          |              |                     |              |          |
+  |          |          SCL |_____________________| SCL          |          |
+  |          |              |                     |              |          |
+  |          |              |                     |              |          |
+  |          |              |                     |              |          |
+  |          |          SDA |_____________________| SDA          |          |
+  |          |              |                     |              |          |
+  |          |______________|                     |______________|          |
+  |                         |                     |                         |
+  |                      GND|_____________________|GND                      |
+  |_STM32_Board 1___________|                     |_STM32_Board 2___________|
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz.
+
+The I2C peripheral configuration is ensured by the HAL_I2C_Init() function.
+This later is calling the HAL_I2C_MspInit()function which core is implementing
+the configuration of the needed I2C resources according to the used hardware (CLOCK, 
+GPIO, DMA and NVIC). You may update this function to change I2C configuration.
+
+The I2C communication is then initiated.
+The project is split in two parts: the Master Board and the Slave Board
+- Master Board
+  The HAL_I2C_Master_Receive_DMA() and the HAL_I2C_Master_Transmit_DMA() functions 
+  allow respectively the reception and the transmission of a predefined data buffer
+  in Master mode using DMA.
+- Slave Board
+  The HAL_I2C_Slave_Receive_DMA() and the HAL_I2C_Slave_Transmit_DMA() functions 
+  allow respectively the reception and the transmission of a predefined data buffer
+  in Slave mode using DMA.
+The user can choose between Master and Slave through "#define MASTER_BOARD"
+in the "main.c" file:
+If the Master board is used, the "#define MASTER_BOARD" must be uncommented.
+If the Slave board is used the "#define MASTER_BOARD" must be commented.
+
+For this example the aTxBuffer is predefined and the aRxBuffer size is same as aTxBuffer.
+
+In a first step after the user press the User push-button (SW1) on the Master Board,
+I2C Master starts the communication by sending aTxBuffer through HAL_I2C_Master_Transmit_DMA()
+to I2C Slave which receives aRxBuffer through HAL_I2C_Slave_Receive_DMA(). 
+The second step starts when the user press the User push-button (SW1) on the Master Board,
+the I2C Slave sends aTxBuffer through HAL_I2C_Slave_Transmit_DMA()
+to the I2C Master which receives aRxBuffer through HAL_I2C_Master_Receive_DMA().
+The end of this two steps are monitored through the HAL_I2C_GetState() function
+result.
+Finally, aTxBuffer and aRxBuffer are compared through Buffercmp() in order to 
+check buffers correctness.  
+
+NUCLEO-WB35CE's LEDs can be used to monitor the transfer status:
+ - LED2 is ON when the transmission process is complete.
+ - LED2 is OFF when the reception process is complete.
+ - LED3 is ON when there is an error in transmission/reception process.  
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note The application need to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+Connectivity, Communication, I2C, DMA, Master, Slave, Transmission, Reception, Fast mode plus
+
+@par Directory contents 
+
+  - I2C/I2C_TwoBoards_ComDMA/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - I2C/I2C_TwoBoards_ComDMA/Inc/stm32wbxx_it.h          DMA and I2C interrupt handlers header file
+  - I2C/I2C_TwoBoards_ComDMA/Inc/main.h                  Header for main.c module  
+  - I2C/I2C_TwoBoards_ComDMA/Src/stm32wbxx_it.c          DMA and I2C interrupt handlers
+  - I2C/I2C_TwoBoards_ComDMA/Src/main.c                  Main program
+  - I2C/I2C_TwoBoards_ComDMA/Src/system_stm32wbxx.c      STM32WBxx system source file
+  - I2C/I2C_TwoBoards_ComDMA/Src/stm32wbxx_hal_msp.c     HAL MSP file    
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35xx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.    
+
+  - NUCLEO-WB35CE Set-up
+
+    - Connect I2C_SCL line of Master board (PB8, CN5, pin10) to I2C_SCL line of Slave Board (PB8, CN5, pin10).
+    - Connect I2C_SDA line of Master board (PB9, CN5, pin9) to I2C_SDA line of Slave Board (PB9, CN5, pin9).
+    - Connect GND of Master board to GND of Slave Board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+    o Uncomment "#define MASTER_BOARD" and load the project in Master Board
+    o Comment "#define MASTER_BOARD" and load the project in Slave Board
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/.extSettings b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/I2C_TwoBoards_ComIT.ewd b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/I2C_TwoBoards_ComIT.ewd
new file mode 100644
index 000000000..a34f64d7b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/I2C_TwoBoards_ComIT.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		I2C_TwoBoards_ComIT
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/I2C_TwoBoards_ComIT.ewp b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/I2C_TwoBoards_ComIT.ewp
new file mode 100644
index 000000000..c65740bea
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/I2C_TwoBoards_ComIT.ewp
@@ -0,0 +1,1125 @@
+
+
+  3
+  
+    I2C_TwoBoards_ComIT
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/Project.eww
new file mode 100644
index 000000000..ea939628b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\I2C_TwoBoards_ComIT.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/I2C_TwoBoards_ComIT.ioc b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/I2C_TwoBoards_ComIT.ioc
new file mode 100644
index 000000000..e7df30029
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/I2C_TwoBoards_ComIT.ioc
@@ -0,0 +1,130 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+I2C1.AddressingMode=I2C_ADDRESSINGMODE_10BIT
+I2C1.Analog_Filter=I2C_ANALOGFILTER_ENABLE
+I2C1.CustomTiming=Disabled
+I2C1.DualAddressMode=I2C_DUALADDRESS_DISABLE
+I2C1.GeneralCallMode=I2C_GENERALCALL_DISABLE
+I2C1.I2C_Coeff_DF=0
+I2C1.I2C_Fall_Time=2
+I2C1.I2C_Rise_Time=26
+I2C1.I2C_Speed_Mode=I2C_Fast_Plus
+I2C1.IPParameters=CustomTiming,I2C_Speed_Mode,Speed,I2C_Rise_Time,I2C_Fall_Time,I2C_Coeff_DF,Analog_Filter,NoStretchMode,GeneralCallMode,AddressingMode,DualAddressMode,OwnAddress,Timing
+I2C1.IPParametersWithoutCheck=OwnAddress
+I2C1.NoStretchMode=I2C_NOSTRETCH_DISABLE
+I2C1.OwnAddress=I2C_ADDRESS
+I2C1.Speed=1000
+I2C1.Timing=0x00400B27
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=I2C1
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB8
+Mcu.Pin1=PB9
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=I2C_ADDRESS,0x30F
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.I2C1_ER_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.I2C1_EV_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PB8.Mode=I2C
+PB8.Signal=I2C1_SCL
+PB9.Mode=I2C
+PB9.Signal=I2C1_SDA
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=I2C_TwoBoards_ComIT.ioc
+ProjectManager.ProjectName=I2C_TwoBoards_ComIT
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Inc/main.h
new file mode 100644
index 000000000..ed33b943f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Inc/main.h
@@ -0,0 +1,76 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    I2C/I2C_TwoBoards_ComIT/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+#define COUNTOF(__BUFFER__)   (sizeof(__BUFFER__) / sizeof(*(__BUFFER__)))
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define I2C_ADDRESS 0x30F
+/* USER CODE BEGIN Private defines */
+
+/* Size of Transmission buffer */
+#define TXBUFFERSIZE                      (COUNTOF(aTxBuffer) - 1)
+/* Size of Reception buffer */
+#define RXBUFFERSIZE                      TXBUFFERSIZE
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..ee44a80b3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+#define HAL_I2C_MODULE_ENABLED
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..2dbb4a3fa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Inc/stm32wbxx_it.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    I2C/I2C_TwoBoards_ComIT/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void I2C1_EV_IRQHandler(void);
+void I2C1_ER_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/MDK-ARM/I2C_TwoBoards_ComIT.uvoptx b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/MDK-ARM/I2C_TwoBoards_ComIT.uvoptx
new file mode 100644
index 000000000..da42bb6fe
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/MDK-ARM/I2C_TwoBoards_ComIT.uvoptx
@@ -0,0 +1,133 @@
+
+
+	
+		I2C_TwoBoards_ComIT
+		0x4
+		ARM-ADS
+		
+			64000000
+			
+				1
+				1
+				0
+				1
+			
+			
+				1
+				65535
+				0
+				0
+				0
+			
+			
+				79
+				66
+				8
+				
+			
+			
+				1
+				1
+				1
+				0
+				1
+				1
+				0
+				1
+				0
+				0
+				0
+				0
+			
+			
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				0
+				0
+			
+			
+				0
+				0
+				1
+			
+			0
+			
+				0
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				1
+				0
+				0
+				13
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				STLink\ST-LINKIII-KEIL_SWO.dll
+			
+			
+				
+					0
+					ST-LINKIII-KEIL_SWO
+					-U-O142 -O2254 -S0 -C0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CE$CMSIS\Flash\STM32WB_M4.FLM)
+				
+				
+					0
+					
+					-U-O142 -O2254 -S0 -C0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CE$CMSIS\Flash\STM32WB_M4.FLM)
+				
+			
+			
+				0
+				1
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+				0
+			
+			
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/MDK-ARM/I2C_TwoBoards_ComIT.uvprojx b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/MDK-ARM/I2C_TwoBoards_ComIT.uvprojx
new file mode 100644
index 000000000..a5e59082e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/MDK-ARM/I2C_TwoBoards_ComIT.uvprojx
@@ -0,0 +1,571 @@
+
+
+	1.1
+
+	
    ### uVision Project, (C) Keil Software
    
+
+	
+		 
+			I2C_TwoBoards_ComIT
+			0x4
+			ARM-ADS
+			
+				
+					STM32WB35CEUx
+					STMicroelectronics
+					IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					
+					0
+					0
+					
+					
+					
+					
+					
+					
+						0
+						0
+						0
+						0
+						1
+					
+					I2C_TwoBoards_ComIT\
+					I2C_TwoBoards_ComIT
+					1
+					0
+					1
+					1
+					1
+					./I2C_TwoBoards_ComIT/
+					1
+					0
+					0
+					
+						0
+						0
+						
+						
+						0
+						0
+					
+					
+						0
+						0
+						
+						
+						0
+						0
+						0
+						0
+					
+					
+						0
+						0
+						
+						
+						0
+						0
+					
+					0
+					
+				
+				
+					0
+					0
+					0
+					0
+					0
+					1
+					0
+					0
+					0
+					0
+					3
+					
+					
+					
+				
+				
+					SARMCM3.DLL
+					-REMAP -MPU
+					DCM.DLL
+					-pCM4
+					SARMCM3.DLL
+					-MPU
+					TCM.DLL
+					-pCM4
+				
+				
+					
+						1
+						0
+						0
+						0
+						16
+					
+					
+						0
+						1
+						1
+						1
+						1
+						1
+						1
+						1
+						0
+						1
+					
+					
+						1
+						1
+						1
+						1
+						1
+						1
+						0
+						1
+						1 
+						1
+					
+					0
+					13
+					
+						
+						
+						
+						
+						
+					
+					
+						
+						
+						
+						
+						
+						STLink\ST-LINKIII-KEIL_SWO.dll
+					
+				
+				
+					
+						1
+						0
+						0
+						1
+						1
+						4107
+					
+					1
+					STLink\ST-LINKIII-KEIL_SWO.dll
+					
+					
+					
+					
+					
+					0
+				
+				
+					
+						0
+						1
+						1
+						1
+						1
+						1
+						1
+						1
+						0
+						1
+						1
+						0
+						1
+						1
+						0
+						0
+						1
+						1
+						1
+						1
+						1
+						1
+						1
+						1
+						1
+						0
+						0
+						"Cortex-M4"
+						
+						0
+						0
+						0
+						1
+						1
+						0
+						0
+						2
+						0
+						0
+						8
+						1
+						0
+						0
+						3
+						3
+						0
+						0
+						0
+						0
+						0
+						0
+						0
+						0
+						0
+						0
+						1
+						0
+						0
+						0
+						0
+						1
+						0
+						
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								
+								
+							
+							
+								1
+								
+								
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								1
+								0x0
+								0x0
+							
+							
+								1
+								0x0
+								0x0
+							
+							
+								1
+								0x0
+								0x0
+							
+							
+								1
+								
+								
+							
+							
+								1
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								0x0
+								0x0
+							
+							
+								0
+								
+								
+							
+							
+								0
+								0x0
+								0x0
+							
+						
+						
+					
+					
+						1
+						4
+						0
+						0
+						1
+						0
+						0
+						0
+						0
+						0
+						2
+						0
+						0
+						1
+						0
+						
+							
+							USE_HAL_DRIVER,STM32WB35xx
+							
+							../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+						
+					
+					
+						1
+						0
+						0
+						0
+						0
+						0
+						0
+						
+							
+							
+							
+							
+						
+					
+					
+						0
+						0
+						0
+						0
+						1
+						0
+						0x08000000
+						0x20000000
+						
+						stm32wb35xx_flash_cm4.sct
+						
+						
+						--diag_suppress L6314W
+						
+						
+					
+				
+			     
+			
+        
+					Application/MDK-ARM
+				
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+				
+				
+					::CMSIS
+				
+			
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_i2c.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
+            
+            
+              stm32wbxx_hal_i2c_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+
+		
+	
+	
+		
+		
+			
+				
+				
+					
+				
+			
+		
+		
+	
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..506c7c22d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/.project
new file mode 100644
index 000000000..7c03db106
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/.project
@@ -0,0 +1,155 @@
+
+
+	I2C_TwoBoards_ComIT
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			I2C_TwoBoards_ComIT.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/I2C_TwoBoards_ComIT.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_i2c.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_i2c_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Src/main.c
new file mode 100644
index 000000000..70695841a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Src/main.c
@@ -0,0 +1,502 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    I2C/I2C_TwoBoards_ComIT/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use STM32WBxx I2C HAL API to transmit
+  *          and receive a data buffer with a communication process based on
+  *          IT transfer.
+  *          The communication is done using 2 Boards.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* Uncomment this line to use the board as master, if not it is used as slave */
+//#define MASTER_BOARD
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+I2C_HandleTypeDef hi2c1;
+
+/* USER CODE BEGIN PV */
+/* Buffer used for transmission */
+uint8_t aTxBuffer[] = " ****I2C_TwoBoards communication based on IT****  ****I2C_TwoBoards communication based on IT****  ****I2C_TwoBoards communication based on IT**** ";
+
+/* Buffer used for reception */
+uint8_t aRxBuffer[RXBUFFERSIZE];
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_I2C1_Init(void);
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+static uint16_t Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_I2C1_Init();
+  /* USER CODE BEGIN 2 */
+  /* Configure LED2 and LED3 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+
+
+#ifdef MASTER_BOARD
+
+  /* Configure User push-button (SW1) */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_GPIO);
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  /* Wait for User push-button (SW1) press before starting the Communication */
+  while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_RESET)
+  {
+  }
+
+  /* Delay to avoid that possible signal rebound is taken as button release */
+  HAL_Delay(50);
+
+  /* Wait for User push-button (SW1) release before starting the Communication */
+  while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_SET)
+  {
+  }
+
+  /* The board sends the message and expects to receive it back */
+
+  /*##- Start the transmission process #####################################*/
+  /* While the I2C in reception process, user can transmit data through
+     "aTxBuffer" buffer */
+  do
+  {
+    if (HAL_I2C_Master_Transmit_IT(&hi2c1, (uint16_t)I2C_ADDRESS, (uint8_t *)aTxBuffer, TXBUFFERSIZE) != HAL_OK)
+    {
+      /* Error_Handler() function is called when error occurs. */
+      Error_Handler();
+    }
+
+    /*##- Wait for the end of the transfer #################################*/
+    /*  Before starting a new communication transfer, you need to check the current
+        state of the peripheral; if its busy you need to wait for the end of current
+        transfer before starting a new one.
+        For simplicity reasons, this example is just waiting till the end of the
+        transfer, but application may perform other tasks while transfer operation
+        is ongoing. */
+    while (HAL_I2C_GetState(&hi2c1) != HAL_I2C_STATE_READY)
+    {
+    }
+
+    /* When Acknowledge failure occurs (Slave don't acknowledge it's address)
+       Master restarts communication */
+  }
+  while (HAL_I2C_GetError(&hi2c1) == HAL_I2C_ERROR_AF);
+
+  /* Wait for User push-button (SW1) press before starting the Communication */
+  while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_RESET)
+  {
+  }
+
+  /* Delay to avoid that possible signal rebound is taken as button release */
+  HAL_Delay(50);
+
+  /* Wait for User push-button (SW1) release before starting the Communication */
+  while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_SET)
+  {
+  }
+
+  /*##- Put I2C peripheral in reception process ###########################*/
+  do
+  {
+    if (HAL_I2C_Master_Receive_IT(&hi2c1, (uint16_t)I2C_ADDRESS, (uint8_t *)aRxBuffer, RXBUFFERSIZE) != HAL_OK)
+    {
+      /* Error_Handler() function is called when error occurs. */
+      Error_Handler();
+    }
+
+    /*##- Wait for the end of the transfer #################################*/
+    /*  Before starting a new communication transfer, you need to check the current
+        state of the peripheral; if its busy you need to wait for the end of current
+        transfer before starting a new one.
+        For simplicity reasons, this example is just waiting till the end of the
+        transfer, but application may perform other tasks while transfer operation
+        is ongoing. */
+    while (HAL_I2C_GetState(&hi2c1) != HAL_I2C_STATE_READY)
+    {
+    }
+
+    /* When Acknowledge failure occurs (Slave don't acknowledge it's address)
+       Master restarts communication */
+  }
+  while (HAL_I2C_GetError(&hi2c1) == HAL_I2C_ERROR_AF);
+
+#else
+
+  /* The board receives the message and sends it back */
+
+  /*##- Put I2C peripheral in reception process ###########################*/
+  if (HAL_I2C_Slave_Receive_IT(&hi2c1, (uint8_t *)aRxBuffer, RXBUFFERSIZE) != HAL_OK)
+  {
+    /* Transfer error in reception process */
+    Error_Handler();
+  }
+
+  /*##- Wait for the end of the transfer ###################################*/
+  /*  Before starting a new communication transfer, you need to check the current
+      state of the peripheral; if its busy you need to wait for the end of current
+      transfer before starting a new one.
+      For simplicity reasons, this example is just waiting till the end of the
+      transfer, but application may perform other tasks while transfer operation
+      is ongoing. */
+  while (HAL_I2C_GetState(&hi2c1) != HAL_I2C_STATE_READY)
+  {
+  }
+
+  /*##- Start the transmission process #####################################*/
+  /* While the I2C in reception process, user can transmit data through
+     "aTxBuffer" buffer */
+  if (HAL_I2C_Slave_Transmit_IT(&hi2c1, (uint8_t *)aTxBuffer, TXBUFFERSIZE) != HAL_OK)
+  {
+    /* Transfer error in transmission process */
+    Error_Handler();
+  }
+
+#endif /* MASTER_BOARD */
+
+  /*##- Wait for the end of the transfer ###################################*/
+  /*  Before starting a new communication transfer, you need to check the current
+      state of the peripheral; if its busy you need to wait for the end of current
+      transfer before starting a new one.
+      For simplicity reasons, this example is just waiting till the end of the
+      transfer, but application may perform other tasks while transfer operation
+      is ongoing. */
+  while (HAL_I2C_GetState(&hi2c1) != HAL_I2C_STATE_READY)
+  {
+  }
+
+  /*##- Compare the sent and received buffers ##############################*/
+  if (Buffercmp((uint8_t *)aTxBuffer, (uint8_t *)aRxBuffer, RXBUFFERSIZE))
+  {
+    /* Processing Error */
+    Error_Handler();
+  }
+
+  /* Infinite loop */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief I2C1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_I2C1_Init(void)
+{
+
+  /* USER CODE BEGIN I2C1_Init 0 */
+
+  /* USER CODE END I2C1_Init 0 */
+
+  /* USER CODE BEGIN I2C1_Init 1 */
+
+  /* USER CODE END I2C1_Init 1 */
+  hi2c1.Instance = I2C1;
+  hi2c1.Init.Timing = 0x00400B27;
+  hi2c1.Init.OwnAddress1 = I2C_ADDRESS;
+  hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_10BIT;
+  hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+  hi2c1.Init.OwnAddress2 = 0;
+  hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+  hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+  hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+  if (HAL_I2C_Init(&hi2c1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Analogue filter 
+  */
+  if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Digital filter 
+  */
+  if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** I2C Enable Fast Mode Plus 
+  */
+  HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C1);
+  /* USER CODE BEGIN I2C1_Init 2 */
+
+  /* USER CODE END I2C1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Compares two buffers.
+  * @param  pBuffer1, pBuffer2: buffers to be compared.
+  * @param  BufferLength: buffer's length
+  * @retval 0  : pBuffer1 identical to pBuffer2
+  *         >0 : pBuffer1 differs from pBuffer2
+  */
+static uint16_t Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
+{
+  while (BufferLength--)
+  {
+    if ((*pBuffer1) != *pBuffer2)
+    {
+      return BufferLength;
+    }
+    pBuffer1++;
+    pBuffer2++;
+  }
+
+  return 0;
+}
+
+/**
+  * @brief  Tx Transfer completed callback.
+  * @param  I2cHandle: I2C handle.
+  * @note   This example shows a simple way to report end of IT Tx transfer, and
+  *         you can add your own implementation.
+  * @retval None
+  */
+#ifdef MASTER_BOARD
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *I2cHandle)
+{
+  /* Toggle LED2: Transfer in transmission process is correct */
+  BSP_LED_Toggle(LED2);
+}
+#else
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *I2cHandle)
+{
+  /* Toggle LED2: Transfer in transmission process is correct */
+  BSP_LED_Toggle(LED2);
+}
+#endif /* MASTER_BOARD */
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  I2cHandle: I2C handle
+  * @note   This example shows a simple way to report end of IT Rx transfer, and
+  *         you can add your own implementation.
+  * @retval None
+  */
+#ifdef MASTER_BOARD
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *I2cHandle)
+{
+  /* Toggle LED2: Transfer in reception process is correct */
+  BSP_LED_Toggle(LED2);
+}
+#else
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *I2cHandle)
+{
+  /* Toggle LED2: Transfer in reception process is correct */
+  BSP_LED_Toggle(LED2);
+}
+#endif /* MASTER_BOARD */
+
+/**
+  * @brief  I2C error callbacks.
+  * @param  I2cHandle: I2C handle
+  * @note   This example shows a simple way to report transfer error, and you can
+  *         add your own implementation.
+  * @retval None
+  */
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *I2cHandle)
+{
+  /** Error_Handler() function is called when error occurs.
+    * 1- When Slave doesn't acknowledge its address, Master restarts communication.
+    * 2- When Master doesn't acknowledge the last data transferred, Slave doesn't care in this example.
+    */
+  if (HAL_I2C_GetError(I2cHandle) != HAL_I2C_ERROR_AF)
+  {
+    /* Turn Off LED2 */
+    BSP_LED_Off(LED2);
+
+    /* Turn On LED3 */
+    BSP_LED_On(LED3);
+  }
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  Error_Handler();
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..b52a4ec8c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,159 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    I2C/I2C_TwoBoards_ComIT/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief I2C MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hi2c: I2C handle pointer
+* @retval None
+*/
+void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hi2c->Instance==I2C1)
+  {
+  /* USER CODE BEGIN I2C1_MspInit 0 */
+        RCC_PeriphCLKInitTypeDef  RCC_PeriphCLKInitStruct;
+
+    /*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/
+    RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
+    RCC_PeriphCLKInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_SYSCLK;
+    HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
+  /* USER CODE END I2C1_MspInit 0 */
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**I2C1 GPIO Configuration    
+    PB8     ------> I2C1_SCL
+    PB9     ------> I2C1_SDA 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* Peripheral clock enable */
+    __HAL_RCC_I2C1_CLK_ENABLE();
+    /* I2C1 interrupt Init */
+    HAL_NVIC_SetPriority(I2C1_EV_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(I2C1_EV_IRQn);
+    HAL_NVIC_SetPriority(I2C1_ER_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(I2C1_ER_IRQn);
+  /* USER CODE BEGIN I2C1_MspInit 1 */
+
+  /* USER CODE END I2C1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief I2C MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hi2c: I2C handle pointer
+* @retval None
+*/
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
+{
+  if(hi2c->Instance==I2C1)
+  {
+  /* USER CODE BEGIN I2C1_MspDeInit 0 */
+
+  /* USER CODE END I2C1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_I2C1_CLK_DISABLE();
+  
+    /**I2C1 GPIO Configuration    
+    PB8     ------> I2C1_SCL
+    PB9     ------> I2C1_SDA 
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9);
+
+    /* I2C1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(I2C1_EV_IRQn);
+    HAL_NVIC_DisableIRQ(I2C1_ER_IRQn);
+  /* USER CODE BEGIN I2C1_MspDeInit 1 */
+
+  /* USER CODE END I2C1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..0458b180e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Src/stm32wbxx_it.c
@@ -0,0 +1,176 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    I2C/I2C_TwoBoards_ComIT/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern I2C_HandleTypeDef hi2c1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles I2C1 event interrupt.
+  */
+void I2C1_EV_IRQHandler(void)
+{
+  /* USER CODE BEGIN I2C1_EV_IRQn 0 */
+
+  /* USER CODE END I2C1_EV_IRQn 0 */
+  HAL_I2C_EV_IRQHandler(&hi2c1);
+  /* USER CODE BEGIN I2C1_EV_IRQn 1 */
+
+  /* USER CODE END I2C1_EV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles I2C1 error interrupt.
+  */
+void I2C1_ER_IRQHandler(void)
+{
+  /* USER CODE BEGIN I2C1_ER_IRQn 0 */
+
+  /* USER CODE END I2C1_ER_IRQn 0 */
+  HAL_I2C_ER_IRQHandler(&hi2c1);
+  /* USER CODE BEGIN I2C1_ER_IRQn 1 */
+
+  /* USER CODE END I2C1_ER_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/readme.txt b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/readme.txt
new file mode 100644
index 000000000..b777fd3a1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_TwoBoards_ComIT/readme.txt
@@ -0,0 +1,134 @@
+/**
+  @page I2C_TwoBoards_ComIT I2C Two Boards Communication IT example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    I2C/I2C_TwoBoards_ComIT/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the I2C Two Boards Communication IT example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to handle I2C data buffer transmission/reception between two boards, 
+using an interrupt.
+
+Board: NUCLEO-WB35CE (embeds a STM32WB35CE device)
+SCL Pin: PB8 (CN5, pin10)
+SDA Pin: PB9 (CN5, pin9)
+
+   _________________________                       _________________________ 
+  |           ______________|                     |______________           |
+  |          |I2C1          |                     |          I2C1|          |
+  |          |              |                     |              |          |
+  |          |          SCL |_____________________| SCL          |          |
+  |          |              |                     |              |          |
+  |          |              |                     |              |          |
+  |          |              |                     |              |          |
+  |          |          SDA |_____________________| SDA          |          |
+  |          |              |                     |              |          |
+  |          |______________|                     |______________|          |
+  |                         |                     |                         |
+  |                      GND|_____________________|GND                      |
+  |_STM32_Board 1___________|                     |_STM32_Board 2___________|
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz.
+
+The I2C peripheral configuration is ensured by the HAL_I2C_Init() function.
+This later is calling the HAL_I2C_MspInit()function which core is implementing
+the configuration of the needed I2C resources according to the used hardware (CLOCK, 
+GPIO and NVIC). You may update this function to change I2C configuration.
+
+The I2C communication is then initiated.
+The project is split in two parts: the Master Board and the Slave Board
+- Master Board
+  The HAL_I2C_Master_Receive_IT() and the HAL_I2C_Master_Transmit_IT() functions 
+  allow respectively the reception and the transmission of a predefined data buffer
+  in Master mode using interrupt.
+- Slave Board
+  The HAL_I2C_Slave_Receive_IT() and the HAL_I2C_Slave_Transmit_IT() functions 
+  allow respectively the reception and the transmission of a predefined data buffer
+  in Slave mode using interrupt.
+The user can choose between Master and Slave through "#define MASTER_BOARD"
+in the "main.c" file:
+If the Master board is used, the "#define MASTER_BOARD" must be uncommented.
+If the Slave board is used the "#define MASTER_BOARD" must be commented.
+
+For this example the aTxBuffer is predefined and the aRxBuffer size is same as aTxBuffer.
+
+In a first step after the user press the User push-button (SW1) on the Master Board,
+I2C Master starts the communication by sending aTxBuffer through HAL_I2C_Master_Transmit_IT()
+to I2C Slave which receives aRxBuffer through HAL_I2C_Slave_Receive_IT(). 
+The second step starts when the user press the User push-button (SW1) on the Master Board,
+the I2C Slave sends aTxBuffer through HAL_I2C_Slave_Transmit_IT()
+to the I2C Master which receives aRxBuffer through HAL_I2C_Master_Receive_IT().
+The end of this two steps are monitored through the HAL_I2C_GetState() function
+result.
+Finally, aTxBuffer and aRxBuffer are compared through Buffercmp() in order to 
+check buffers correctness.  
+
+NUCLEO-WB35CE's LEDs can be used to monitor the transfer status:
+ - LED2 is ON when the transmission process is complete.
+ - LED2 is OFF when the reception process is complete.
+ - LED3 is ON when there is an error in transmission/reception process.  
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note The application need to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+Connectivity, Communication, I2C, Interrupt, Master, Slave, Transmission, Reception, Fast mode plus
+
+@par Directory contents 
+
+  - I2C/I2C_TwoBoards_ComIT/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - I2C/I2C_TwoBoards_ComIT/Inc/stm32wbxx_it.h          I2C interrupt handlers header file
+  - I2C/I2C_TwoBoards_ComIT/Inc/main.h                  Header for main.c module  
+  - I2C/I2C_TwoBoards_ComIT/Src/stm32wbxx_it.c          I2C interrupt handlers
+  - I2C/I2C_TwoBoards_ComIT/Src/main.c                  Main program
+  - I2C/I2C_TwoBoards_ComIT/Src/system_stm32wbxx.c      STM32WBxx system source file
+  - I2C/I2C_TwoBoards_ComIT/Src/stm32wbxx_hal_msp.c     HAL MSP file    
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35xx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.    
+
+  - NUCLEO-WB35CE Set-up
+
+    - Connect I2C_SCL line of Master board (PB8, CN5, pin10) to I2C_SCL line of Slave Board (PB8, CN5, pin10).
+    - Connect I2C_SDA line of Master board (PB9, CN5, pin9) to I2C_SDA line of Slave Board (PB9, CN5, pin9).
+    - Connect GND of Master board to GND of Slave Board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+    o Uncomment "#define MASTER_BOARD" and load the project in Master Board
+    o Comment "#define MASTER_BOARD" and load the project in Slave Board
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/.extSettings b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/I2C_WakeUpFromStop2.ewd b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/I2C_WakeUpFromStop2.ewd
new file mode 100644
index 000000000..9dc975c89
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/I2C_WakeUpFromStop2.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		I2C_WakeUpFromStop2
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/I2C_WakeUpFromStop2.ewp b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/I2C_WakeUpFromStop2.ewp
new file mode 100644
index 000000000..c248f188c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/I2C_WakeUpFromStop2.ewp
@@ -0,0 +1,1125 @@
+
+
+  3
+  
+    I2C_WakeUpFromStop2
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/Project.eww
new file mode 100644
index 000000000..1701f5b82
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\I2C_WakeUpFromStop2.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/I2C_WakeUpFromStop2.ioc b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/I2C_WakeUpFromStop2.ioc
new file mode 100644
index 000000000..83aba0414
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/I2C_WakeUpFromStop2.ioc
@@ -0,0 +1,127 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+I2C3.AddressingMode=I2C_ADDRESSINGMODE_7BIT
+I2C3.Analog_Filter=I2C_ANALOGFILTER_ENABLE
+I2C3.CustomTiming=Disabled
+I2C3.DualAddressMode=I2C_DUALADDRESS_DISABLE
+I2C3.GeneralCallMode=I2C_GENERALCALL_DISABLE
+I2C3.I2C_Coeff_DF=0
+I2C3.I2C_Fall_Time=10
+I2C3.I2C_Rise_Time=50
+I2C3.I2C_Speed_Mode=I2C_Fast
+I2C3.IPParameters=CustomTiming,I2C_Speed_Mode,Speed,I2C_Rise_Time,I2C_Fall_Time,I2C_Coeff_DF,Analog_Filter,NoStretchMode,GeneralCallMode,AddressingMode,DualAddressMode,OwnAddress,Timing
+I2C3.NoStretchMode=I2C_NOSTRETCH_DISABLE
+I2C3.OwnAddress=I2C_ADDRESS/2
+I2C3.Speed=100
+I2C3.Timing=0x0020098E
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=I2C3
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA7
+Mcu.Pin1=PB4
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=I2C_ADDRESS,0xCA
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.I2C3_ER_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.I2C3_EV_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PA7.Mode=I2C
+PA7.Signal=I2C3_SCL
+PB4.Mode=I2C
+PB4.Signal=I2C3_SDA
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=I2C_WakeUpFromStop2.ioc
+ProjectManager.ProjectName=I2C_WakeUpFromStop2
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHBFreq_Value=16000000
+RCC.APB1Freq_Value=16000000
+RCC.APB1TimFreq_Value=16000000
+RCC.APB2Freq_Value=16000000
+RCC.APB2TimFreq_Value=16000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=16000000
+RCC.CortexFreq_Value=16000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=16000000
+RCC.FCLKCortexFreq_Value=16000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=16000000
+RCC.HCLK3Freq_Value=16000000
+RCC.HCLKFreq_Value=16000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=16000000
+RCC.I2C3Freq_Value=16000000
+RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=16000000
+RCC.LPTIM2Freq_Value=16000000
+RCC.LPUART1Freq_Value=16000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=16000000
+RCC.PLLPoutputFreq_Value=16000000
+RCC.PLLQoutputFreq_Value=16000000
+RCC.PLLRCLKFreq_Value=16000000
+RCC.PWRFreq_Value=16000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=16000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_HSI
+RCC.USART1Freq_Value=16000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=32000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Inc/main.h
new file mode 100644
index 000000000..2cfd168a7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Inc/main.h
@@ -0,0 +1,77 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    I2C/I2C_WakeUpFromStop2/Inc/main.h 
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+#define COUNTOF(__BUFFER__)   (sizeof(__BUFFER__) / sizeof(*(__BUFFER__)))
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define I2C_ADDRESS 0xCA
+/* USER CODE BEGIN Private defines */
+
+/* Size of Transmission buffer */
+#define TXBUFFERSIZE                      (COUNTOF(aTxBuffer) - 1)
+/* Size of Reception buffer */
+#define RXBUFFERSIZE                      TXBUFFERSIZE
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..ee44a80b3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+#define HAL_I2C_MODULE_ENABLED
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..fe7949292
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Inc/stm32wbxx_it.h
@@ -0,0 +1,66 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    I2C/I2C_WakeUpFromStop2/Inc/stm32wbxx_it.h 
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void I2C3_EV_IRQHandler(void);
+void I2C3_ER_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/MDK-ARM/I2C_WakeUpFromStop2.uvoptx b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/MDK-ARM/I2C_WakeUpFromStop2.uvoptx
new file mode 100644
index 000000000..728c285d0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/MDK-ARM/I2C_WakeUpFromStop2.uvoptx
@@ -0,0 +1,541 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    I2C_WakeUpFromStop2
+    0x4
+    ARM-ADS
+    
+      16000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          ARMRTXEVENTFLAGS
+          -L70 -Z18 -C0 -M0 -T1
+        
+        
+          0
+          DLGTARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          
+        
+        
+          0
+          DLGUARM
+          (105=-1,-1,-1,-1,0)
+        
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066CFF303337554E43183920 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        1
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      2
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
+      stm32wbxx_hal_i2c.c
+      0
+      0
+    
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c_ex.c
+      stm32wbxx_hal_i2c_ex.c
+      0
+      0
+    
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      5
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      5
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      5
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      5
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      5
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      5
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      5
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      5
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      5
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      5
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      5
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      5
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      24
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/MDK-ARM/I2C_WakeUpFromStop2.uvprojx b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/MDK-ARM/I2C_WakeUpFromStop2.uvprojx
new file mode 100644
index 000000000..899c4a188
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/MDK-ARM/I2C_WakeUpFromStop2.uvprojx
@@ -0,0 +1,552 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      I2C_WakeUpFromStop2
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          I2C_WakeUpFromStop2\
+          I2C_WakeUpFromStop2
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_i2c.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
+            
+            
+              stm32wbxx_hal_i2c_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..ae53e2d97
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/.cproject
@@ -0,0 +1,170 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/.project
new file mode 100644
index 000000000..3351c6ca4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/.project
@@ -0,0 +1,155 @@
+
+
+	I2C_WakeUpFromStop2
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			I2C_WakeUpFromStop2.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/I2C_WakeUpFromStop2.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_i2c.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_i2c_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Src/main.c
new file mode 100644
index 000000000..ad4cccc5e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Src/main.c
@@ -0,0 +1,533 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    I2C/I2C_WakeUpFromStop2/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use STM32WBxx I2C HAL API to transmit 
+  *          and receive a data buffer with a communication process in stop mode 2
+  *          based on IT transfer. 
+  *          The communication is done using 2 Boards.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* Uncomment this line to use the board as master, if not it is used as slave */
+//#define MASTER_BOARD
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+I2C_HandleTypeDef hi2c3;
+
+/* USER CODE BEGIN PV */
+/* Buffer used for transmission */
+uint8_t aTxBuffer[] = " ****I2C_TwoBoards communication wake up from stop mode 2 based on IT****  ****I2C_TwoBoards communication wake up from stop mode 2 based on IT****  ****I2C_TwoBoards communication wake up from stop mode 2 based on IT**** ";
+
+/* Buffer used for reception */
+uint8_t aRxBuffer[RXBUFFERSIZE];
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_I2C3_Init(void);
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+static uint16_t Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_I2C3_Init();
+  /* USER CODE BEGIN 2 */
+  /* Configure LED2, LED1 and LED3 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+  BSP_LED_Init(LED1);
+
+#ifdef MASTER_BOARD
+
+  /* Configure User push-button (SW1) */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_GPIO);
+
+  /* Wait for User push-button (SW1) press before starting the Communication */
+  while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_RESET)
+  {
+  }
+
+  /* Wait for User push-button (SW1) release before starting the Communication */
+  while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_SET)
+  {
+  }
+
+  /* The board sends the message and expects to receive it back */
+
+  /*##- Start the transmission process #####################################*/
+  /* While the I2C in reception process, user can transmit data through 
+     "aTxBuffer" buffer */
+  do
+  {
+    if(HAL_I2C_Master_Transmit_IT(&hi2c3, (uint16_t)I2C_ADDRESS, (uint8_t*)aTxBuffer, TXBUFFERSIZE)!= HAL_OK)
+    {
+      /* Error_Handler() function is called when error occurs. */
+      Error_Handler();
+    }
+
+    /*##- Wait for the end of the transfer #################################*/  
+    /*  Before starting a new communication transfer, you need to check the current   
+        state of the peripheral; if its busy you need to wait for the end of current
+        transfer before starting a new one.
+        For simplicity reasons, this example is just waiting till the end of the 
+        transfer, but application may perform other tasks while transfer operation
+        is ongoing. */  
+    while (HAL_I2C_GetState(&hi2c3) != HAL_I2C_STATE_READY)
+    {
+    } 
+
+    /* When Acknowledge failure occurs (Slave don't acknowledge it's address)
+       Master restarts communication */
+  }
+  while(HAL_I2C_GetError(&hi2c3) == HAL_I2C_ERROR_AF);
+
+  /* Wait for User push-button (SW1) press before starting the Communication */
+  while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_RESET)
+  {
+  }
+
+  /* Wait for User push-button (SW1) release before starting the Communication */
+  while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_SET)
+  {
+  }
+
+  /*##- Put I2C peripheral in reception process ###########################*/  
+  do
+  {
+    if(HAL_I2C_Master_Receive_IT(&hi2c3, (uint16_t)I2C_ADDRESS, (uint8_t *)aRxBuffer, RXBUFFERSIZE) != HAL_OK)
+    {
+      /* Error_Handler() function is called when error occurs. */
+      Error_Handler();
+    }
+
+    /*##- Wait for the end of the transfer #################################*/  
+    /*  Before starting a new communication transfer, you need to check the current   
+        state of the peripheral; if its busy you need to wait for the end of current
+        transfer before starting a new one.
+        For simplicity reasons, this example is just waiting till the end of the 
+        transfer, but application may perform other tasks while transfer operation
+        is ongoing. */  
+    while (HAL_I2C_GetState(&hi2c3) != HAL_I2C_STATE_READY)
+    {
+    } 
+
+    /* When Acknowledge failure occurs (Slave don't acknowledge it's address)
+       Master restarts communication */
+  }
+  while(HAL_I2C_GetError(&hi2c3) == HAL_I2C_ERROR_AF);
+
+#else
+  /*##- Enable I2C peripheral in wake up from stop mode 2 #################*/  
+  HAL_I2CEx_EnableWakeUp(&hi2c3);
+  
+  /*##- Put I2C peripheral in reception process ###########################*/  
+  if(HAL_I2C_Slave_Receive_IT(&hi2c3, (uint8_t *)aRxBuffer, RXBUFFERSIZE) != HAL_OK)
+  {
+    /* Transfer error in reception process */
+    Error_Handler();        
+  }
+ 
+  /* enter stop mode 2 */
+  /* Turn LED1 on */
+  BSP_LED_On(LED1);
+  HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI);
+
+  /* ... STOP mode 2 ... */
+
+  /* Wake Up from Stop mode 2 */
+  /* Turn LED1 off */
+  BSP_LED_Off(LED1);
+
+  /*##- Wait for the end of the transfer ###################################*/  
+  /*  Before starting a new communication transfer, you need to check the current   
+      state of the peripheral; if its busy you need to wait for the end of current
+      transfer before starting a new one.
+      For simplicity reasons, this example is just waiting till the end of the 
+      transfer, but application may perform other tasks while transfer operation
+      is ongoing. */
+  while (HAL_I2C_GetState(&hi2c3) != HAL_I2C_STATE_READY)
+  {
+  } 
+  
+  /*##- Start the transmission process #####################################*/  
+  /* While the I2C in reception process, user can transmit data through 
+     "aTxBuffer" buffer */
+  if(HAL_I2C_Slave_Transmit_IT(&hi2c3, (uint8_t*)aTxBuffer, TXBUFFERSIZE)!= HAL_OK)
+  {
+    /* Transfer error in transmission process */
+    Error_Handler();
+  }
+
+  /* enter stop mode 2 */
+  /* Turn LED1 on */
+  BSP_LED_On(LED1);
+  HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI);
+
+  /* ... STOP mode 2 ... */  
+
+  /* Wake Up from Stop mode 2 */
+  /* Turn LED1 off */
+  BSP_LED_Off(LED1);
+#endif /* MASTER_BOARD */
+
+  /*##- Wait for the end of the transfer ###################################*/  
+  /*  Before starting a new communication transfer, you need to check the current   
+      state of the peripheral; if its busy you need to wait for the end of current
+      transfer before starting a new one.
+      For simplicity reasons, this example is just waiting till the end of the
+      transfer, but application may perform other tasks while transfer operation
+      is ongoing. */
+  while (HAL_I2C_GetState(&hi2c3) != HAL_I2C_STATE_READY)
+  {
+  } 
+  
+  /*##- Compare the sent and received buffers ##############################*/
+  if(Buffercmp((uint8_t*)aTxBuffer,(uint8_t*)aRxBuffer,RXBUFFERSIZE))
+  {
+    /* Processing Error */
+    Error_Handler();      
+  }
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief I2C3 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_I2C3_Init(void)
+{
+
+  /* USER CODE BEGIN I2C3_Init 0 */
+
+  /* USER CODE END I2C3_Init 0 */
+
+  /* USER CODE BEGIN I2C3_Init 1 */
+
+  /* USER CODE END I2C3_Init 1 */
+  hi2c3.Instance = I2C3;
+  hi2c3.Init.Timing = 0x0020098E;
+  hi2c3.Init.OwnAddress1 = 202;
+  hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+  hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+  hi2c3.Init.OwnAddress2 = 0;
+  hi2c3.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+  hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+  hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+  if (HAL_I2C_Init(&hi2c3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Analogue filter 
+  */
+  if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Digital filter 
+  */
+  if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN I2C3_Init 2 */
+
+  /* USER CODE END I2C3_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Tx Transfer completed callback.
+  * @param  I2cHandle: I2C handle. 
+  * @note   This example shows a simple way to report end of IT Tx transfer, and 
+  *         you can add your own implementation. 
+  * @retval None
+  */
+#ifdef MASTER_BOARD
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *I2cHandle)
+{
+  /* Toggle LED2: Transfer in transmission process is correct */
+  BSP_LED_Toggle(LED2);
+}
+#else
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *I2cHandle)
+{
+  /* Restore config: clock, GPIO... */
+  SystemClock_Config();
+
+  /* Restore GPIO configuration */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED1);
+
+  /* Wake Up from Stop Mode 2 */
+  /* Turn LED1 off */
+  BSP_LED_Off(LED1);
+  /* Turn off LED2: Transfer in transmission process is correct */
+  BSP_LED_Off(LED2);
+}
+#endif /* MASTER_BOARD */
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  I2cHandle: I2C handle
+  * @note   This example shows a simple way to report end of IT Rx transfer, and 
+  *         you can add your own implementation.
+  * @retval None
+  */
+#ifdef MASTER_BOARD
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *I2cHandle)
+{
+  /* Toggle LED2: Transfer in reception process is correct */
+  BSP_LED_Toggle(LED2);
+}
+#else
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *I2cHandle)
+{
+  /* Restore config: clock, GPIO... */
+  SystemClock_Config();
+
+  /* Restore GPIO configuration */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED1);
+
+  /* Wake Up from Stop Mode 2 */
+  /* Turn LED1 off */
+  BSP_LED_Off(LED1);
+
+  /* Turn On LED2: Transfer in reception process is correct */
+  BSP_LED_On(LED2);
+}
+#endif /* MASTER_BOARD */
+
+/**
+  * @brief  I2C error callbacks.
+  * @param  I2cHandle: I2C handle
+  * @note   This example shows a simple way to report transfer error, and you can
+  *         add your own implementation.
+  * @retval None
+  */
+#ifdef MASTER_BOARD
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *I2cHandle)
+{
+  /* Turn LED3 on: Transfer error in reception/transmission process */
+  BSP_LED_On(LED3); 
+}
+#else
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *I2cHandle)
+{
+  /* Restore config: clock, GPIO... */
+  SystemClock_Config();
+
+  /** Error_Handler() function is called when error occurs.
+    * 1- When Slave doesn't acknowledge its address, Master restarts communication.
+    * 2- When Master doesn't acknowledge the last data transferred, Slave doesn't care in this example.
+    */
+  if (HAL_I2C_GetError(I2cHandle) != HAL_I2C_ERROR_AF)
+  {
+    /* Restore GPIO configuration */
+    BSP_LED_Init(LED2);
+    BSP_LED_Init(LED3);
+
+    /* Turn Off LED2 */
+    BSP_LED_Off(LED2);
+
+    /* Turn On LED3 */
+    BSP_LED_On(LED3);
+  }
+}
+#endif /* MASTER_BOARD */
+
+/**
+  * @brief  Compares two buffers.
+  * @param  pBuffer1, pBuffer2: buffers to be compared.
+  * @param  BufferLength: buffer's length
+  * @retval 0  : pBuffer1 identical to pBuffer2
+  *         >0 : pBuffer1 differs from pBuffer2
+  */
+static uint16_t Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
+{
+  while (BufferLength--)
+  {
+    if ((*pBuffer1) != *pBuffer2)
+    {
+      return BufferLength;
+    }
+    pBuffer1++;
+    pBuffer2++;
+  }
+
+  return 0;
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  while(1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  Error_Handler();
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..937930f15
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,172 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    I2C/I2C_WakeUpFromStop2/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief I2C MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hi2c: I2C handle pointer
+* @retval None
+*/
+void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hi2c->Instance==I2C3)
+  {
+  /* USER CODE BEGIN I2C3_MspInit 0 */
+  RCC_PeriphCLKInitTypeDef  RCC_PeriphCLKInitStruct;
+  
+  /*##-1- Configure the I2C clock source. The clock is derived from the HSI #*/
+  RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C3;
+  RCC_PeriphCLKInitStruct.I2c3ClockSelection = RCC_I2C3CLKSOURCE_HSI;
+  HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
+  /*##-2- Configure the WakeUp clock system as HSI ########################*/
+  HAL_RCCEx_WakeUpStopCLKConfig(RCC_STOP_WAKEUPCLOCK_HSI);
+
+  /* USER CODE END I2C3_MspInit 0 */
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**I2C3 GPIO Configuration    
+    PA7     ------> I2C3_SCL
+    PB4     ------> I2C3_SDA 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_4;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* Peripheral clock enable */
+    __HAL_RCC_I2C3_CLK_ENABLE();
+    /* I2C3 interrupt Init */
+    HAL_NVIC_SetPriority(I2C3_EV_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(I2C3_EV_IRQn);
+    HAL_NVIC_SetPriority(I2C3_ER_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(I2C3_ER_IRQn);
+  /* USER CODE BEGIN I2C3_MspInit 1 */
+
+  /* USER CODE END I2C3_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief I2C MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hi2c: I2C handle pointer
+* @retval None
+*/
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
+{
+  if(hi2c->Instance==I2C3)
+  {
+  /* USER CODE BEGIN I2C3_MspDeInit 0 */
+
+  /* USER CODE END I2C3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_I2C3_CLK_DISABLE();
+  
+    /**I2C3 GPIO Configuration    
+    PA7     ------> I2C3_SCL
+    PB4     ------> I2C3_SDA 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_7);
+
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_4);
+
+    /* I2C3 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(I2C3_EV_IRQn);
+    HAL_NVIC_DisableIRQ(I2C3_ER_IRQn);
+  /* USER CODE BEGIN I2C3_MspDeInit 1 */
+
+  /* USER CODE END I2C3_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..f0928fbf4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Src/stm32wbxx_it.c
@@ -0,0 +1,149 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    I2C/I2C_WakeUpFromStop2/Src/stm32wbxx_it.c 
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and 
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern I2C_HandleTypeDef hi2c3;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles I2C3 event interrupt.
+  */
+void I2C3_EV_IRQHandler(void)
+{
+  /* USER CODE BEGIN I2C3_EV_IRQn 0 */
+
+  /* USER CODE END I2C3_EV_IRQn 0 */
+  HAL_I2C_EV_IRQHandler(&hi2c3);
+  /* USER CODE BEGIN I2C3_EV_IRQn 1 */
+
+  /* USER CODE END I2C3_EV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles I2C3 error interrupt.
+  */
+void I2C3_ER_IRQHandler(void)
+{
+  /* USER CODE BEGIN I2C3_ER_IRQn 0 */
+
+  /* USER CODE END I2C3_ER_IRQn 0 */
+  HAL_I2C_ER_IRQHandler(&hi2c3);
+  /* USER CODE BEGIN I2C3_ER_IRQn 1 */
+
+  /* USER CODE END I2C3_ER_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/readme.txt b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/readme.txt
new file mode 100644
index 000000000..ab143f624
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2C/I2C_WakeUpFromStop2/readme.txt
@@ -0,0 +1,136 @@
+/**
+  @page I2C_WakeUpFromStop2 I2C Two Boards Communication IT Example on Stop 2 Mode
+  
+  @verbatim
+  ******************************************************************************
+  * @file    I2C/I2C_WakeUpFromStop2/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the Wake Up from Stop 2 mode example
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to handle I2C data buffer transmission/reception between two boards, 
+using an interrupt when the device is in Stop 2 mode.
+
+Board: NUCLEO-WB35CE (embeds a STM32WB35CE device)
+SCL Pin: PA7 (CN10, pin15)
+SDA Pin: PB4 (CN10, pin13)
+
+   _________________________                       _________________________ 
+  |           ______________|                     |______________           |
+  |          |I2C3          |                     |          I2C3|          |
+  |          |              |                     |              |          |
+  |          |          SCL |_____________________| SCL          |          |
+  |          |              |                     |              |          |
+  |          |              |                     |              |          |
+  |          |              |                     |              |          |
+  |          |          SDA |_____________________| SDA          |          |
+  |          |              |                     |              |          |
+  |          |______________|                     |______________|          |
+  |                         |                     |                         |
+  |                      GND|_____________________|GND                      |
+  |_STM32_Board 1___________|                     |_STM32_Board 2___________|
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 16 Mhz.
+
+The I2C peripheral configuration is ensured by the HAL_I2C_Init() function.
+This later is calling the HAL_I2C_MspInit()function which core is implementing
+the configuration of the needed I2C resources according to the used hardware (CLOCK, 
+GPIO and NVIC). You may update this function to change I2C configuration.
+
+The I2C communication is then initiated.
+The project is splitted in two parts the Master Board and the Slave Board
+- Master Board
+  The HAL_I2C_Master_Receive_IT() and the HAL_I2C_Master_Transmit_IT() functions 
+  allow respectively the reception and the transmission of a predefined data buffer
+  in Master mode using interrupt.
+- Slave Board
+  The HAL_I2C_Slave_Receive_IT() and the HAL_I2C_Slave_Transmit_IT() functions 
+  allow respectively the reception and the transmission of a predefined data buffer
+  in Slave mode using interrupt.
+The user can choose between Master and Slave through "#define MASTER_BOARD"
+in the "main.c" file:
+If the Master board is used, the "#define MASTER_BOARD" must be uncommented.
+If the Slave board is used the "#define MASTER_BOARD" must be commented.
+
+For this example the aTxBuffer is predefined and the aRxBuffer size is same as aTxBuffer.
+
+In a first step after the user presses the User push-button (SW1) on the Master Board, I2C Master
+starts the communication by sending aTxBuffer through HAL_I2C_Master_Transmit_IT() to 
+I2C Slave which wakes up from Stop 2 mode and receives aRxBuffer through HAL_I2C_Slave_Receive_IT(). 
+The second step starts when the user presses the User push-button (SW1) on the Master Board,
+the I2C Slave after wake up from Stop 2 mode at address match, sends aTxBuffer through HAL_I2C_Slave_Transmit_IT()
+to the I2C Master which receives aRxBuffer through HAL_I2C_Master_Receive_IT().
+The end of this two steps are monitored through the HAL_I2C_GetState() function
+result.
+Finally, aTxBuffer and aRxBuffer are compared through Buffercmp() in order to 
+check buffers correctness.  
+
+NUCLEO-WB35CE's LEDs can be used to monitor the transfer status on the Slave Board :
+ - LED2 is ON when the Transmission process is complete.
+ - LED2 is OFF when the Reception process is complete.
+ - LED3 is ON when there is an error in transmission/reception process.
+ - LED1 is ON when Slave enters Stop 2 mode .
+ - LED1 is OFF when Slave wakes up from Stop 2.    
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note The application need to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+Connectivity, I2C, Communication, Trasmission, Reception, SCL, SDA, Wake up, Interrupt
+
+@par Directory contents 
+
+  - I2C/I2C_WakeUpFromStop2/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - I2C/I2C_WakeUpFromStop2/Inc/stm32wbxx_it.h          I2C interrupt handlers header file
+  - I2C/I2C_WakeUpFromStop2/Inc/main.h                  Header for main.c module
+  - I2C/I2C_WakeUpFromStop2/Src/stm32wbxx_it.c          I2C interrupt handlers
+  - I2C/I2C_WakeUpFromStop2/Src/main.c                  Main program
+  - I2C/I2C_WakeUpFromStop2/Src/system_stm32wbxx.c      STM32WBxx system source file
+  - I2C/I2C_WakeUpFromStop2/Src/stm32wbxx_hal_msp.c     HAL MSP file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35xx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+  - NUCLEO-WB35CE Set-up
+
+    - Connect I2C_SCL line of Master board (PA7, CN10, pin15) to I2C_SCL line of Slave Board (PA7, CN10, pin15).
+    - Connect I2C_SDA line of Master board (PB4, CN10, pin13) to I2C_SDA line of Slave Board (PB4, CN10, pin13).
+    - Connect GND of Master board to GND of Slave Board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+    o Uncomment "#define MASTER_BOARD" and load the project in Master Board
+    o Comment "#define MASTER_BOARD" and load the project in Slave Board
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/I2S/I2S_Audio/readme.txt b/Projects/NUCLEO-WB35CE/Examples/I2S/I2S_Audio/readme.txt
new file mode 100644
index 000000000..6faeb1c7d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/I2S/I2S_Audio/readme.txt
@@ -0,0 +1,49 @@
+/**
+  @page I2S_AUDIO  How to use the Audio features with I2S peripheral
+  
+  @verbatim
+  ******************************************************************************
+  * @file    I2S/I2S_Audio/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the I2S Audio Example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to play an audio file through the I2S peripheral and DMA-based transfer
+and using an external codec.
+
+The I2S feature is part of STM32WB35xx. 
+
+The NUCLEO-WB35CE board is not suitable to demonstrate this feature as it does not 
+contain any audio codec driver.
+
+The hal library for I2S driver is compatible between STM32F4xx_HAL_Driver and STM32WBxx_HAL_Driver.
+
+You can retrieve the STM32F4xx_HAL_Driver under the stm32cubef4 package (https://www.st.com/stm32cubef4).
+
+Inside the stm32cubef4 package, this I2S_Audio example is available with the following boards:
+  STM32412G-DISCOVERY  (Projects\STM32F412G-Discovery\Examples\I2S\I2S_Audio)
+  You can use those examples and boards schematics for your own implementation.
+  
+The required adaptation from STM32412G-DISCOVERY project, given as information:
+  In all files, rename and adapt include files name to your situation.
+  Copy the system_stm32wbxx.c from Drivers\CMSIS\Device\ST\STM32WBxx\Source\Templates to Src.
+  Copy the stm32wbxx_hal_conf_template.h from Drivers\STM32WBxx_HAL_Driver\Inc to Inc\stm32wbxx_hal_conf.h.
+  Adapt the main.c/SystemClock_Config(void) function to your board.
+  Adapt the GPIO initialization to your board.
+  Create the BSP (containing the initialisation of the audio codec driver) of your board.
+  
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/.extSettings b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/.extSettings
new file mode 100644
index 000000000..1a7569bc5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=TIM;IWDG
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/IWDG_WindowMode.ewd b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/IWDG_WindowMode.ewd
new file mode 100644
index 000000000..d1e351233
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/IWDG_WindowMode.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		IWDG_WindowMode
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/IWDG_WindowMode.ewp b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/IWDG_WindowMode.ewp
new file mode 100644
index 000000000..82b55e4a0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/IWDG_WindowMode.ewp
@@ -0,0 +1,1122 @@
+
+
+  3
+  
+    IWDG_WindowMode
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_iwdg.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/Project.eww
new file mode 100644
index 000000000..2f57e12b5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\IWDG_WindowMode.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/IWDG_WindowMode.ioc b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/IWDG_WindowMode.ioc
new file mode 100644
index 000000000..cd037a247
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/IWDG_WindowMode.ioc
@@ -0,0 +1,115 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+IWDG.IPParameters=Prescaler,Window,Reload
+IWDG.IPParametersWithoutCheck=Window,Reload
+IWDG.Prescaler=IWDG_PRESCALER_16
+IWDG.Reload=IWDG_RELOAD
+IWDG.Window=IWDG_WINDOW
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=IWDG
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_IWDG_VS_IWDG
+Mcu.Pin1=VP_SYS_VS_Systick
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=IWDG_WindowMode.ioc
+ProjectManager.ProjectName=IWDG_WindowMode
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_IWDG_VS_IWDG.Mode=IWDG_Activate
+VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Inc/main.h
new file mode 100644
index 000000000..d3a97f1d6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    IWDG/IWDG_WindowMode/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..5a6ebfc5f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+#define HAL_IWDG_MODULE_ENABLED
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..a990bc1f4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    IWDG/IWDG_WindowMode/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void EXTI0_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/MDK-ARM/IWDG_WindowMode.uvoptx b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/MDK-ARM/IWDG_WindowMode.uvoptx
new file mode 100644
index 000000000..851dcfe04
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/MDK-ARM/IWDG_WindowMode.uvoptx
@@ -0,0 +1,509 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    IWDG_WindowMode
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_iwdg.c
+      stm32wbxx_hal_iwdg.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      23
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/MDK-ARM/IWDG_WindowMode.uvprojx b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/MDK-ARM/IWDG_WindowMode.uvprojx
new file mode 100644
index 000000000..399c265ac
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/MDK-ARM/IWDG_WindowMode.uvprojx
@@ -0,0 +1,546 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      IWDG_WindowMode
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          IWDG_WindowMode\
+          IWDG_WindowMode
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_iwdg.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_iwdg.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..899b7176a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/.project
new file mode 100644
index 000000000..06965b6ca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/.project
@@ -0,0 +1,150 @@
+
+
+	IWDG_WindowMode
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			IWDG_WindowMode.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/IWDG_WindowMode.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_iwdg.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_iwdg.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Src/main.c
new file mode 100644
index 000000000..23c84e10f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Src/main.c
@@ -0,0 +1,283 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    IWDG/IWDG_WindowMode/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use the STM32WB35xx IWDG HAL API
+  *          to update at regular period the IWDG counter and how to simulate a
+  *          software fault generating an MCU IWDG reset on expiry of a
+  *          programmed time period.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define IWDG_WINDOW (32000 * 400) / (16 * 1000)  /* 400 ms */
+#define IWDG_RELOAD (32000 * 762) / (16 * 1000)  /* 762 ms */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+IWDG_HandleTypeDef hiwdg;
+
+/* USER CODE BEGIN PV */
+uint32_t IwdgStatus = 0;
+
+/* In while loop, time to wait before refresh */
+uint32_t WaitingDelay = 0;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_IWDG_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* Configure LED2 and LED3 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+
+  /*##-1- Check if the system has resumed from IWDG reset ####################*/
+  if (__HAL_RCC_GET_FLAG(RCC_FLAG_IWDGRST) != 0x00u)
+  {
+    /* IWDGRST flag set: Turn LED2 on and set IwdgStatus */
+    IwdgStatus = 1;
+    BSP_LED_On(LED2);
+
+    /* Insert 4s delay */
+    HAL_Delay(4000);
+
+    /* Prior to clear IWDGRST flag: Turn LED2 off */
+    BSP_LED_Off(LED2);
+  }
+
+  /* Clear reset flags anyway */
+  __HAL_RCC_CLEAR_RESET_FLAGS();
+  IwdgStatus = 0;
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_IWDG_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Configure User push-button (SW1) */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+
+  /* Initial delay will be 450 ms in order to be inside the window */
+  WaitingDelay = 450;
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    /* Toggle LED2 */
+    BSP_LED_Toggle(LED2);
+
+    HAL_Delay(WaitingDelay);
+
+    /* Refresh IWDG: reload counter */
+    if(HAL_IWDG_Refresh(&hiwdg) != HAL_OK)
+    {
+      /* Refresh Error */
+      Error_Handler();
+    }
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief IWDG Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_IWDG_Init(void)
+{
+
+  /* USER CODE BEGIN IWDG_Init 0 */
+
+  /* USER CODE END IWDG_Init 0 */
+
+  /* USER CODE BEGIN IWDG_Init 1 */
+
+  /* USER CODE END IWDG_Init 1 */
+  hiwdg.Instance = IWDG;
+  hiwdg.Init.Prescaler = IWDG_PRESCALER_16;
+  hiwdg.Init.Window = IWDG_WINDOW;
+  hiwdg.Init.Reload = IWDG_RELOAD;
+  if (HAL_IWDG_Init(&hiwdg) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN IWDG_Init 2 */
+
+  /* USER CODE END IWDG_Init 2 */
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  EXTI line detection callback to decrease waiting delay. That will make
+            refresh being outside window value.
+  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  if(GPIO_Pin == BUTTON_SW1_PIN)
+  {
+    /* waiting 200 ms to be above window value on next refresh */
+    WaitingDelay = 200;
+  }
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+
+  IwdgStatus = 0xE;
+  /* Infinite loop */
+  while(1) 
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..cdd5c716f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32wbxx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..1a3233704
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Src/stm32wbxx_it.c
@@ -0,0 +1,215 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    IWDG/IWDG_WindowMode/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles External line 0 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/readme.txt b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/readme.txt
new file mode 100644
index 000000000..7e61edf8d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/IWDG/IWDG_WindowMode/readme.txt
@@ -0,0 +1,100 @@
+/**
+  @page IWDG_WindowMode IWDG Reset with window mode
+  
+  @verbatim
+  ********************* COPYRIGHT(c) 2019 STMicroelectronics *******************
+  * @file    IWDG/IWDG_WindowMode/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the IWDG Reset with window mode.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to periodically update the IWDG reload counter and simulate a software fault that generates 
+an MCU IWDG reset after a preset laps of time.
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz.
+
+The IWDG time-out is set to 762 ms (the time-out may varies due to LSI frequency 
+dispersion).
+
+The Window option is enabled with a window register value set to 400 ms.
+To prevent a reset, the down-counter must be reloaded when its value is:
+ -lower than the window register value (400ms)
+ -greater than 0x0
+The IWDG counter is therefore refreshed each 450 ms in the main program infinite loop to 
+prevent a IWDG reset (762 - 450 = 312 within the interval).
+LED2 is also toggled each 450 ms indicating that the program is running. 
+LED3 will turn on if any error occurs.
+
+An EXTI Line is connected to a GPIO pin, configured to generate an interrupt
+when the User push-button (SW1) (PA.00) is pressed.
+
+Once the EXTI Line event occurs by pressing the User push-button (SW1) (PA.00), 
+the refresh period is set to 200 ms.
+That will make refresh being outside window value. As a result, when the IWDG counter is reloaded, 
+the IWDG reset occurs.
+
+In the ISR, a write to invalid address generates a Hard fault exception containing
+an infinite loop and preventing to return to main program (the IWDG counter is 
+not refreshed).
+As a result, when the IWDG counter falls to 0, the IWDG reset occurs.
+If the IWDG reset is generated, after the system resumes from reset, LED2 turns on for 4 seconds.
+
+If the EXTI Line event does not occur, the IWDG counter is indefinitely refreshed
+in the main program infinite loop, and there is no IWDG reset.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate
+      delay (in milliseconds) based on variable incremented in SysTick ISR. This
+      implies that if HAL_Delay() is called from a peripheral ISR process, then 
+      the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The example needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+System, IWDG, reload counter, MCU Reset, Window mode, Timeout, Software fault
+
+@par Directory contents 
+
+  - IWDG/IWDG_WindowMode/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - IWDG/IWDG_WindowMode/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - IWDG/IWDG_WindowMode/Inc/main.h                  Header for main.c module  
+  - IWDG/IWDG_WindowMode/Src/stm32wbxx_it.c          Interrupt handlers
+  - IWDG/IWDG_WindowMode/Src/main.c                  Main program
+  - IWDG/IWDG_WindowMode/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/.extSettings b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/LPTIM_PWMExternalClock.ewd b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/LPTIM_PWMExternalClock.ewd
new file mode 100644
index 000000000..d240a6bd8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/LPTIM_PWMExternalClock.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		LPTIM_PWMExternalClock
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/LPTIM_PWMExternalClock.ewp b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/LPTIM_PWMExternalClock.ewp
new file mode 100644
index 000000000..c8a8b7347
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/LPTIM_PWMExternalClock.ewp
@@ -0,0 +1,1122 @@
+
+
+  3
+  
+    LPTIM_PWMExternalClock
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/Project.eww
new file mode 100644
index 000000000..4eabf5565
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\LPTIM_PWMExternalClock.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Inc/main.h
new file mode 100644
index 000000000..36537fbc0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Inc/main.h
@@ -0,0 +1,75 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    LPTIM/LPTIM_PWMExternalClock/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+/* Set the Maximum value of the counter (Auto-Reload) that defines the Period */
+#define PeriodValue             (uint32_t) (100 -1)
+
+/* Set the Compare value that defines the duty cycle */
+#define PulseValue              (uint32_t) (50 -1)
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..4ce3207fc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+#define HAL_LPTIM_MODULE_ENABLED
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..82c07eb12
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    LPTIM/LPTIM_PWMExternalClock/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void EXTI0_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/LPTIM_PWMExternalClock.ioc b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/LPTIM_PWMExternalClock.ioc
new file mode 100644
index 000000000..46ec08b53
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/LPTIM_PWMExternalClock.ioc
@@ -0,0 +1,123 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+LPTIM1.ClockPrescaler=LPTIM_PRESCALER_DIV1
+LPTIM1.IPParameters=ClockPrescaler,ULPClockPolarity,ULPClockSampleTime,UpdateMode,TriggerSource
+LPTIM1.TriggerSource=LPTIM_TRIGSOURCE_SOFTWARE
+LPTIM1.ULPClockPolarity=LPTIM_CLOCKPOLARITY_RISING
+LPTIM1.ULPClockSampleTime=LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+LPTIM1.UpdateMode=LPTIM_UPDATE_IMMEDIATE
+Mcu.Family=STM32WB
+Mcu.IP0=LPTIM1
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB2
+Mcu.Pin1=PB5
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+PB2.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PB2.GPIO_PuPd=GPIO_PULLUP
+PB2.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PB2.Locked=true
+PB2.Signal=LPTIM1_OUT
+PB5.Locked=true
+PB5.Mode=Counts_external_clock_standalone_1X_occur1
+PB5.Signal=LPTIM1_IN1
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=LPTIM_PWMExternalClock.ioc
+ProjectManager.ProjectName=LPTIM_PWMExternalClock
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/MDK-ARM/LPTIM_PWMExternalClock.uvoptx b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/MDK-ARM/LPTIM_PWMExternalClock.uvoptx
new file mode 100644
index 000000000..c163f84bd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/MDK-ARM/LPTIM_PWMExternalClock.uvoptx
@@ -0,0 +1,509 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    LPTIM_PWMExternalClock
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c
+      stm32wbxx_hal_lptim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      23
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/MDK-ARM/LPTIM_PWMExternalClock.uvprojx b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/MDK-ARM/LPTIM_PWMExternalClock.uvprojx
new file mode 100644
index 000000000..0a713c6a5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/MDK-ARM/LPTIM_PWMExternalClock.uvprojx
@@ -0,0 +1,546 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      LPTIM_PWMExternalClock
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          LPTIM_PWMExternalClock\
+          LPTIM_PWMExternalClock
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_lptim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..a0236e6d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/.project
new file mode 100644
index 000000000..43e139ab9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/.project
@@ -0,0 +1,150 @@
+
+
+	LPTIM_PWMExternalClock
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			LPTIM_PWMExternalClock.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/LPTIM_PWMExternalClock.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_lptim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Src/main.c
new file mode 100644
index 000000000..df7e6ab67
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Src/main.c
@@ -0,0 +1,289 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    LPTIM/LPTIM_PWMExternalClock/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to configure and use LPTIM to generate a
+  *          PWM at the lowest power consumption, using an external counter
+  *          clock, through the STM32WBxx HAL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+LPTIM_HandleTypeDef hlptim1;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_LPTIM1_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* Configure LED3 */
+  BSP_LED_Init(LED3);
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_LPTIM1_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* User push-button (SW1) (External line 0) will be used to wakeup the system from STOP mode */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+
+
+ /* ### Start generating the PWM signal ############################## */
+  /*
+   *  Period = 99
+   *  Pulse  = 49
+   *  According to this configuration, the duty cycle will be equal to 50% and
+   *  the output frequency will be equal to the input frequency divided by 100 
+   *  since the LPTIM have to count 100 external clock edges each period.
+   */
+  if (HAL_LPTIM_PWM_Start(&hlptim1, PeriodValue, PulseValue) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  
+  /* ### Enter in Stop mode ########################################### */
+  HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); 
+
+  /* ### Stop counting when leaving Stop mode ########################## */
+  if (HAL_LPTIM_PWM_Stop(&hlptim1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief LPTIM1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_LPTIM1_Init(void)
+{
+
+  /* USER CODE BEGIN LPTIM1_Init 0 */
+
+  /* USER CODE END LPTIM1_Init 0 */
+
+  /* USER CODE BEGIN LPTIM1_Init 1 */
+
+  /* USER CODE END LPTIM1_Init 1 */
+  hlptim1.Instance = LPTIM1;
+  hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_ULPTIM;
+  hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1;
+  hlptim1.Init.UltraLowPowerClock.Polarity = LPTIM_CLOCKPOLARITY_RISING;
+  hlptim1.Init.UltraLowPowerClock.SampleTime = LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION;
+  hlptim1.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE;
+  hlptim1.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH;
+  hlptim1.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE;
+  hlptim1.Init.CounterSource = LPTIM_COUNTERSOURCE_EXTERNAL;
+  hlptim1.Init.Input1Source = LPTIM_INPUT1SOURCE_GPIO;
+  hlptim1.Init.Input2Source = LPTIM_INPUT2SOURCE_GPIO;
+  if (HAL_LPTIM_Init(&hlptim1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN LPTIM1_Init 2 */
+
+  /* USER CODE END LPTIM1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  while(1) 
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* Infinite loop */
+  while (1)
+  {
+  }
+
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..6cf4ad361
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,154 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : LPTIM/LPTIM_PWMExternalClock/Src/stm32wbxx_hal_msp.c
+  * @author            : MCD Application Team
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief LPTIM MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hlptim: LPTIM handle pointer
+* @retval None
+*/
+void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hlptim->Instance==LPTIM1)
+  {
+  /* USER CODE BEGIN LPTIM1_MspInit 0 */
+
+  /* USER CODE END LPTIM1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_LPTIM1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**LPTIM1 GPIO Configuration    
+    PB2     ------> LPTIM1_OUT
+    PB5     ------> LPTIM1_IN1 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_2;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF1_LPTIM1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF1_LPTIM1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN LPTIM1_MspInit 1 */
+
+  /* USER CODE END LPTIM1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief LPTIM MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hlptim: LPTIM handle pointer
+* @retval None
+*/
+void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef* hlptim)
+{
+  if(hlptim->Instance==LPTIM1)
+  {
+  /* USER CODE BEGIN LPTIM1_MspDeInit 0 */
+
+  /* USER CODE END LPTIM1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_LPTIM1_CLK_DISABLE();
+  
+    /**LPTIM1 GPIO Configuration    
+    PB2     ------> LPTIM1_OUT
+    PB5     ------> LPTIM1_IN1 
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_2|GPIO_PIN_5);
+
+  /* USER CODE BEGIN LPTIM1_MspDeInit 1 */
+
+  /* USER CODE END LPTIM1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..10b071fcb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Src/stm32wbxx_it.c
@@ -0,0 +1,216 @@
+/* USER CODE BEGIN Header */
+/** 
+  ******************************************************************************
+  * @file    LPTIM/LPTIM_PWMExternalClock/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/**
+  * @brief  This function handles external line 0 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/readme.txt b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/readme.txt
new file mode 100644
index 000000000..8ddb63093
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PWMExternalClock/readme.txt
@@ -0,0 +1,100 @@
+/**
+  @page LPTIM_PWMExternalClock LPTIM PWM External clock example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    LPTIM/LPTIM_PWMExternalClock/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the LPTIM PWM with an External clock example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to configure and use, through the HAL LPTIM API, the LPTIM peripheral using an external counter clock, 
+to generate a PWM signal at the lowest power consumption.
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+The SystemClock_Config() function is used to configure the system clock for STM32WB35CEUx Devices :
+The CPU at 64 MHz  
+
+The Autorelaod equal to 99 so the output frequency (OutputFrequency) will
+be equal to the external counter clock (InputFrequency) divided by (99+1).
+
+  OutputFrequency = InputFrequency / (Autoreload + 1)
+                  = InputFrequency / 100
+
+Pulse value equal to 49 and the duty cycle (DutyCycle) is computed as follow:
+
+  DutyCycle = 1 - [(PulseValue + 1)/ (Autoreload + 1)]
+  DutyCycle = 50%
+
+To minimize the power consumption, after starting generating the PWM signal,
+the MCU enters in STOP mode. Note that GPIOs are configured in Low Speed to
+lower the consumption.
+
+User push-button (SW1) pin (PA.00)is configured as input with external interrupt (External line 0),
+falling edge. When User push-button (SW1) is pressed, wakeup event is generated and PWM signal
+generation is stopped.
+
+@note This example can not be used in DEBUG mode, this is due to the fact
+      that the Cortex-M4 core is no longer clocked during low power mode
+      so debugging features are disabled.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate
+      delay (in milliseconds) based on variable incremented in SysTick ISR. This
+      implies that if HAL_Delay() is called from a peripheral ISR process, then 
+      the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note This example needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+
+@par Keywords
+
+Timer, Low Power, PWM, Stop mode, Interrupt, External Clock, Output, Duty Cycle
+
+@par Directory contents
+
+  - LPTIM/LPTIM_PWMExternalClock/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - LPTIM/LPTIM_PWMExternalClock/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - LPTIM/LPTIM_PWMExternalClock/Inc/main.h                  Header for main.c module  
+  - LPTIM/LPTIM_PWMExternalClock/Src/stm32wbxx_it.c          Interrupt handlers
+  - LPTIM/LPTIM_PWMExternalClock/Src/main.c                  Main program
+  - LPTIM/LPTIM_PWMExternalClock/Src/stm32wbxx_hal_msp.c     HAL MSP module
+  - LPTIM/LPTIM_PWMExternalClock/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE
+    board and can be easily tailored to any other supported device
+    and development board.   
+	
+  - Connect a clock signal to PB5 (pin 21 in CN10 connector).
+  - Connect PB2 (pin 17 in CN10 connector) to an oscilloscope 
+    to monitor the LPTIM output waveform.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred tool chain 
+ - Rebuild all files and load your image into target memory
+ - Run the example 
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/.extSettings b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/LPTIM_PulseCounter.ewd b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/LPTIM_PulseCounter.ewd
new file mode 100644
index 000000000..c2a39c382
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/LPTIM_PulseCounter.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		LPTIM_PulseCounter
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/LPTIM_PulseCounter.ewp b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/LPTIM_PulseCounter.ewp
new file mode 100644
index 000000000..5d3405ac0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/LPTIM_PulseCounter.ewp
@@ -0,0 +1,1122 @@
+
+
+  3
+  
+    LPTIM_PulseCounter
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/Project.eww
new file mode 100644
index 000000000..ab9dbb81c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\LPTIM_PulseCounter.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Inc/main.h
new file mode 100644
index 000000000..f09880198
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    LPTIM/LPTIM_PulseCounter/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..4ce3207fc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+#define HAL_LPTIM_MODULE_ENABLED
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..ac1f68a97
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Inc/stm32wbxx_it.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    LPTIM/LPTIM_PulseCounter/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void LPTIM1_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/LPTIM_PulseCounter.ioc b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/LPTIM_PulseCounter.ioc
new file mode 100644
index 000000000..521b438cf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/LPTIM_PulseCounter.ioc
@@ -0,0 +1,117 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+LPTIM1.IPParameters=ULPClockPolarity,ULPClockSampleTime,UpdateMode,TriggerSource
+LPTIM1.TriggerSource=LPTIM_TRIGSOURCE_SOFTWARE
+LPTIM1.ULPClockPolarity=LPTIM_CLOCKPOLARITY_RISING
+LPTIM1.ULPClockSampleTime=LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+LPTIM1.UpdateMode=LPTIM_UPDATE_IMMEDIATE
+Mcu.Family=STM32WB
+Mcu.IP0=LPTIM1
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB5
+Mcu.Pin1=VP_SYS_VS_Systick
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.LPTIM1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+PB5.Locked=true
+PB5.Mode=Counts_external_clock_with_synchro_01_occur1
+PB5.Signal=LPTIM1_IN1
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=LPTIM_PulseCounter.ioc
+ProjectManager.ProjectName=LPTIM_PulseCounter
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/MDK-ARM/LPTIM_PulseCounter.uvoptx b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/MDK-ARM/LPTIM_PulseCounter.uvoptx
new file mode 100644
index 000000000..3c5375ba6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/MDK-ARM/LPTIM_PulseCounter.uvoptx
@@ -0,0 +1,509 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    LPTIM_PulseCounter
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c
+      stm32wbxx_hal_lptim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      23
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/MDK-ARM/LPTIM_PulseCounter.uvprojx b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/MDK-ARM/LPTIM_PulseCounter.uvprojx
new file mode 100644
index 000000000..823edddd7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/MDK-ARM/LPTIM_PulseCounter.uvprojx
@@ -0,0 +1,546 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      LPTIM_PulseCounter
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          LPTIM_PulseCounter\
+          LPTIM_PulseCounter
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_lptim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..7e9d664f0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/.project
new file mode 100644
index 000000000..9d9791c1d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/.project
@@ -0,0 +1,150 @@
+
+
+	LPTIM_PulseCounter
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			LPTIM_PulseCounter.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/LPTIM_PulseCounter.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_lptim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Src/main.c
new file mode 100644
index 000000000..a41923074
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Src/main.c
@@ -0,0 +1,289 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    LPTIM/LPTIM_PulseCounter/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to configure and use the LPTIM in counter
+  *          mode through the STM32WBxx HAL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+LPTIM_HandleTypeDef hlptim1;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_LPTIM1_Init(void);
+/* USER CODE BEGIN PFP */
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* Configure LED2 & LED3 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_LPTIM1_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* ### Start counting in interrupt mode ############################# */
+  /*
+   *  Period = 1000
+   */
+  if (HAL_LPTIM_Counter_Start_IT(&hlptim1, 1000) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* Disable autoreload write complete interrupt */
+  __HAL_LPTIM_DISABLE_IT(&hlptim1, LPTIM_IT_ARROK);
+
+  /* ### Enter in Stop mode ########################################### */
+  HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); 
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief LPTIM1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_LPTIM1_Init(void)
+{
+
+  /* USER CODE BEGIN LPTIM1_Init 0 */
+
+  /* USER CODE END LPTIM1_Init 0 */
+
+  /* USER CODE BEGIN LPTIM1_Init 1 */
+
+  /* USER CODE END LPTIM1_Init 1 */
+  hlptim1.Instance = LPTIM1;
+  hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC;
+  hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1;
+  hlptim1.Init.UltraLowPowerClock.Polarity = LPTIM_CLOCKPOLARITY_RISING;
+  hlptim1.Init.UltraLowPowerClock.SampleTime = LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION;
+  hlptim1.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE;
+  hlptim1.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH;
+  hlptim1.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE;
+  hlptim1.Init.CounterSource = LPTIM_COUNTERSOURCE_EXTERNAL;
+  hlptim1.Init.Input1Source = LPTIM_INPUT1SOURCE_GPIO;
+  hlptim1.Init.Input2Source = LPTIM_INPUT2SOURCE_GPIO;
+  if (HAL_LPTIM_Init(&hlptim1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN LPTIM1_Init 2 */
+
+  /* USER CODE END LPTIM1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  Autoreload match callback in non blocking mode 
+  * @param  hlptim : LPTIM handle
+  * @retval None
+  */
+void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Turn on LED2 */
+  BSP_LED_Toggle(LED2);
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  while(1) 
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* Infinite loop */
+  while (1)
+  {
+  }
+
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..629817345
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,196 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : LPTIM/LPTIM_PulseCounter/Src/stm32wbxx_hal_msp.c
+  * @author            : MCD Application Team
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief LPTIM MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hlptim: LPTIM handle pointer
+* @retval None
+*/
+void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hlptim->Instance==LPTIM1)
+  {
+  /* USER CODE BEGIN LPTIM1_MspInit 0 */
+
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct;
+
+    /* Enable LSI clock */
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1;
+    RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+    {
+        Error_Handler();
+    }
+
+    /* Select the LSI clock as LPTIM peripheral clock */
+    RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1;
+    RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSI;  
+    HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
+    
+    /* Force the LPTIM Peripheral Clock Reset */
+    __HAL_RCC_LPTIM1_FORCE_RESET();
+
+    /* Release the LPTIM Peripheral Clock Reset */
+    __HAL_RCC_LPTIM1_RELEASE_RESET();
+
+  /* USER CODE END LPTIM1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_LPTIM1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**LPTIM1 GPIO Configuration    
+    PB5     ------> LPTIM1_IN1 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF1_LPTIM1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* LPTIM1 interrupt Init */
+    HAL_NVIC_SetPriority(LPTIM1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(LPTIM1_IRQn);
+  /* USER CODE BEGIN LPTIM1_MspInit 1 */
+
+  /* USER CODE END LPTIM1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief LPTIM MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hlptim: LPTIM handle pointer
+* @retval None
+*/
+void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef* hlptim)
+{
+  if(hlptim->Instance==LPTIM1)
+  {
+  /* USER CODE BEGIN LPTIM1_MspDeInit 0 */
+
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct;
+
+    /* Enable LSI clock */
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1;
+    RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+    {
+        Error_Handler();
+    }
+
+    /* Select the LSI clock as LPTIM peripheral clock */
+    RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1;
+    RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSI;  
+    HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
+
+    /* Force the LPTIM Peripheral Clock Reset */
+    __HAL_RCC_LPTIM1_FORCE_RESET();
+
+    /* Release the LPTIM Peripheral Clock Reset */
+    __HAL_RCC_LPTIM1_RELEASE_RESET();
+
+  /* USER CODE END LPTIM1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_LPTIM1_CLK_DISABLE();
+  
+    /**LPTIM1 GPIO Configuration    
+    PB5     ------> LPTIM1_IN1 
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5);
+
+    /* LPTIM1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(LPTIM1_IRQn);
+  /* USER CODE BEGIN LPTIM1_MspDeInit 1 */
+
+  /* USER CODE END LPTIM1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..931c53317
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Src/stm32wbxx_it.c
@@ -0,0 +1,220 @@
+/* USER CODE BEGIN Header */
+/** 
+  ******************************************************************************
+  * @file    LPTIM/LPTIM_PulseCounter/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern LPTIM_HandleTypeDef hlptim1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles LPTIM1 global interrupt.
+  */
+void LPTIM1_IRQHandler(void)
+{
+  /* USER CODE BEGIN LPTIM1_IRQn 0 */
+
+  /* USER CODE END LPTIM1_IRQn 0 */
+  HAL_LPTIM_IRQHandler(&hlptim1);
+  /* USER CODE BEGIN LPTIM1_IRQn 1 */
+
+  /* USER CODE END LPTIM1_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/readme.txt b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/readme.txt
new file mode 100644
index 000000000..f2eb6201a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/LPTIM/LPTIM_PulseCounter/readme.txt
@@ -0,0 +1,89 @@
+/**
+  @page LPTIM_PulseCounter Low power timer pulse counter example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    LPTIM/LPTIM_PulseCounter/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the LPTIM Pulse counter example
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to configure and use, through the LPTIM HAL API, the LPTIM peripheral 
+to count pulses.
+
+
+To reduce power consumption, MCU enters stop mode after starting counting. Each
+time the counter reachs the maximum value (Period/Autoreload), an interruption
+is generated, the MCU is woke up from stop mode and LED2 toggles the last state.
+  
+In this example Period value is set to 1000, so each time the counter counts
+(1000 + 1) rising edges on LPTIM Input pin PB5, an interrupt is generated and LED2
+toggles.
+
+In this example the internal clock provided to the LPTIM1 is LSI (32 Khz),
+so the external input is sampled with LSI clock. In order not to miss any event,
+the frequency of the changes on the external Input1 signal should never exceed the
+frequency of the internal clock provided to the LPTIM1 (LSI for the
+present example).
+
+@note This example can not be used in DEBUG mode, this is due to the fact
+      that the Cortex-M4 core is no longer clocked during low power mode
+      so debugging features are disabled.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate
+      delay (in milliseconds) based on variable incremented in SysTick ISR. This
+      implies that if HAL_Delay() is called from a peripheral ISR process, then 
+      the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note This example needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+
+@par Keywords
+
+Timer, Low Power, Pulse Counter, Stop mode, Interrupt
+
+@par Directory contents
+
+  - LPTIM/LPTIM_PulseCounter/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - LPTIM/LPTIM_PulseCounter/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - LPTIM/LPTIM_PulseCounter/Inc/main.h                  Header for main.c module  
+  - LPTIM/LPTIM_PulseCounter/Src/stm32wbxx_it.c          Interrupt handlers
+  - LPTIM/LPTIM_PulseCounter/Src/main.c                  Main program
+  - LPTIM/LPTIM_PulseCounter/Src/stm32wbxx_hal_msp.c     HAL MSP module
+  - LPTIM/LPTIM_PulseCounter/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE
+    board and can be easily tailored to any other supported device
+    and development board.      
+
+  - Generate pulses on PB5 (pin 1 in CN5 connector). (Connect a square waveform).
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred tool chain 
+ - Rebuild all files and load your image into target memory
+ - Run the example 
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/.extSettings b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/.extSettings
new file mode 100644
index 000000000..12711849f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/.extSettings
@@ -0,0 +1,9 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Application/User=../Src/main.c;../Src/stm32wbxx_hal_msp.c;../Src/stm32wbxx_it.c;../Src/prime256v1.c;../Src/SigGen.c;
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewd b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewd
new file mode 100644
index 000000000..4af346943
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		PKA_ECDSA_Sign
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewp b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewp
new file mode 100644
index 000000000..3757db21c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewp
@@ -0,0 +1,1132 @@
+
+
+  3
+  
+    PKA_ECDSA_Sign
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        30
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$\startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$\..\Src\main.c
+      
+      
+        $PROJ_DIR$\..\Src\stm32wbxx_hal_msp.c
+      
+      
+        $PROJ_DIR$\..\Src\stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$\..\Src\prime256v1.c
+      
+      
+        $PROJ_DIR$\..\Src\SigGen.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$\..\readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$\..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE\nucleo_wb35ce.c
+        
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$\..\Src\system_stm32wbxx.c
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pka.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim_ex.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/Project.eww
new file mode 100644
index 000000000..78da88b19
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\PKA_ECDSA_Sign.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/stm32wb35xx_sram_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/stm32wb35xx_sram_cm4.icf
new file mode 100644
index 000000000..6426355fb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/EWARM/stm32wb35xx_sram_cm4.icf
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20003FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20004000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20008000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x2000FFFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/SigGen.h b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/SigGen.h
new file mode 100644
index 000000000..8309ef30d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/SigGen.h
@@ -0,0 +1,51 @@
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Sign/Inc/SigGen.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of SigGen.c .
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __SIGGEN_H
+#define __SIGGEN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const uint8_t  SigGen_Msg[];
+extern const uint32_t SigGen_Msg_len;
+extern const uint8_t  SigGen_Hash_Msg[];
+extern const uint32_t SigGen_Hash_Msg_len;
+extern const uint8_t  SigGen_d[];
+extern const uint32_t SigGen_d_len;
+extern const uint8_t  SigGen_Qx[];
+extern const uint32_t SigGen_Qx_len;
+extern const uint8_t  SigGen_Qy[];
+extern const uint32_t SigGen_Qy_len;
+extern const uint8_t  SigGen_k[];
+extern const uint32_t SigGen_k_len;
+extern const uint8_t  SigGen_R[];
+extern const uint32_t SigGen_R_len;
+extern const uint8_t  SigGen_S[];
+extern const uint32_t SigGen_S_len;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SIGGEN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/main.h
new file mode 100644
index 000000000..1a4b522c3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/main.h
@@ -0,0 +1,75 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Sign/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+#include "prime256v1.h"
+#include "SigGen.h"
+#include "stdlib.h"
+#include "string.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/prime256v1.h b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/prime256v1.h
new file mode 100644
index 000000000..de2fff994
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/prime256v1.h
@@ -0,0 +1,54 @@
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Sign/Inc/PKV.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of prime256v1.c .
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PRIME256V1_H
+#define __PRIME256V1_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const uint8_t  prime256v1_Prime[];
+extern const uint32_t prime256v1_Prime_len;
+extern const uint8_t  prime256v1_A[];
+extern const uint8_t  prime256v1_absA[];
+extern const uint32_t prime256v1_A_len;
+extern const uint32_t prime256v1_A_sign;
+extern const uint8_t  prime256v1_B[];
+extern const uint32_t prime256v1_B_len;
+extern const uint8_t  prime256v1_Generator[];
+extern const uint32_t prime256v1_Generator_len;
+extern const uint8_t  prime256v1_GeneratorX[];
+extern const uint32_t prime256v1_GeneratorX_len;
+extern const uint8_t  prime256v1_GeneratorY[];
+extern const uint32_t prime256v1_GeneratorY_len;
+extern const uint8_t  prime256v1_Order[];
+extern const uint32_t prime256v1_Order_len;
+extern const uint32_t prime256v1_Cofactor;
+extern const uint8_t  prime256v1_Seed[];
+extern const uint32_t prime256v1_Seed_len;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PRIME256V1_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..e9bf557df
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+#define HAL_PKA_MODULE_ENABLED
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..883331307
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+ ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvoptx b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvoptx
new file mode 100644
index 000000000..bede867e2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvoptx
@@ -0,0 +1,533 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    PKA_ECDSA_Sign
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      5
+      1
+      0
+      0
+      0
+      ../Src/prime256v1.c
+      prime256v1.c
+      0
+      0
+    
+    
+      3
+      6
+      1
+      0
+      0
+      0
+      ../Src/SigGen.c
+      SigGen.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      7
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pka.c
+      stm32wbxx_hal_pka.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      24
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      25
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvprojx b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvprojx
new file mode 100644
index 000000000..569b0ae87
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvprojx
@@ -0,0 +1,556 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      PKA_ECDSA_Sign
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          PKA_ECDSA_Sign\
+          PKA_ECDSA_Sign
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              prime256v1.c
+              1
+              ../Src/prime256v1.c
+            
+            
+              SigGen.c
+              1
+              ../Src/SigGen.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_pka.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pka.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/PKA_ECDSA_Sign.ioc b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/PKA_ECDSA_Sign.ioc
new file mode 100644
index 000000000..9bc0c3920
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/PKA_ECDSA_Sign.ioc
@@ -0,0 +1,110 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+KeepUserPlacement=false
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=PKA
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_PKA_VS_PKA
+Mcu.Pin1=VP_SYS_VS_Systick
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=false
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=PKA_ECDSA_Sign.ioc
+ProjectManager.ProjectName=PKA_ECDSA_Sign
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_PKA_Init-PKA-false-HAL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FLatency=FLASH_LATENCY_3
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FLatency,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_PKA_VS_PKA.Mode=PKA_Activate
+VP_PKA_VS_PKA.Signal=PKA_VS_PKA
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..1bd8d31a4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/.project
new file mode 100644
index 000000000..0f764e89e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/.project
@@ -0,0 +1,160 @@
+
+
+	PKA_ECDSA_Sign
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			PKA_ECDSA_Sign.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/PKA_ECDSA_Sign.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/SigGen.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/SigGen.c
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/prime256v1.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/prime256v1.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pka.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pka.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/SigGen.c b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/SigGen.c
new file mode 100644
index 000000000..17e05c36c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/SigGen.c
@@ -0,0 +1,97 @@
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Sign/Src/SigGen.c
+  * @author  MCD Application Team
+  * @brief   This file contains reference buffers from 
+  *          NIST Cryptographic Algorithm Validation Program (CAVP).
+  *          (http://csrc.nist.gov/groups/STM/cavp/)
+  *          1 test vector is extracted to demonstrate PKA capability to
+  *          sign a message using ECDSA (Elliptic Curve Digital Signature Algorithm) 
+  *          signature generation function principle.
+  *          It is adapted from SigGen.txt section [P-256,SHA-256] available under
+  *          http://csrc.nist.gov/groups/STM/cavp/documents/dss/186-3ecdsatestvectors.zip
+  *          and provided in the same directory for reference.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+  
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/*
+  Adapted from
+  [P-256,SHA-256]
+  Msg = 5905238877c77421f73e43ee3da6f2d9e2ccad5fc942dcec0cbd25482935faaf416983fe165b1a045ee2bcd2e6dca3bdf46c4310a7461f9a37960ca672d3feb5473e253605fb1ddfd28065b53cb5858a8ad28175bf9bd386a5e471ea7a65c17cc934a9d791e91491eb3754d03799790fe2d308d16146d5c9b0d0debd97d79ce8
+  d = 519b423d715f8b581f4fa8ee59f4771a5b44c8130b4e3eacca54a56dda72b464
+  Qx = 1ccbe91c075fc7f4f033bfa248db8fccd3565de94bbfb12f3c59ff46c271bf83
+  Qy = ce4014c68811f9a21a1fdb2c0e6113e06db7ca93b7404e78dc7ccd5ca89a4ca9
+  k = 94a1bbb14b906a61a280f245f9e93c7f3b4a6247824f5d33b9670787642a68de
+  R = f3ac8061b514795b8843e3d6629527ed2afd6b1f6a555a7acabb5e6f79c8c2ac
+  S = 8bf77819ca05a6b2786c76262bf7371cef97b218e96f175a3ccdda2acc058903
+*/
+
+const uint8_t SigGen_Msg[] = {
+  0x59, 0x05, 0x23, 0x88, 0x77, 0xc7, 0x74, 0x21, 0xf7, 0x3e, 0x43, 0xee, 0x3d, 0xa6, 0xf2, 0xd9,
+  0xe2, 0xcc, 0xad, 0x5f, 0xc9, 0x42, 0xdc, 0xec, 0x0c, 0xbd, 0x25, 0x48, 0x29, 0x35, 0xfa, 0xaf,
+  0x41, 0x69, 0x83, 0xfe, 0x16, 0x5b, 0x1a, 0x04, 0x5e, 0xe2, 0xbc, 0xd2, 0xe6, 0xdc, 0xa3, 0xbd,
+  0xf4, 0x6c, 0x43, 0x10, 0xa7, 0x46, 0x1f, 0x9a, 0x37, 0x96, 0x0c, 0xa6, 0x72, 0xd3, 0xfe, 0xb5,
+  0x47, 0x3e, 0x25, 0x36, 0x05, 0xfb, 0x1d, 0xdf, 0xd2, 0x80, 0x65, 0xb5, 0x3c, 0xb5, 0x85, 0x8a,
+  0x8a, 0xd2, 0x81, 0x75, 0xbf, 0x9b, 0xd3, 0x86, 0xa5, 0xe4, 0x71, 0xea, 0x7a, 0x65, 0xc1, 0x7c,
+  0xc9, 0x34, 0xa9, 0xd7, 0x91, 0xe9, 0x14, 0x91, 0xeb, 0x37, 0x54, 0xd0, 0x37, 0x99, 0x79, 0x0f,
+  0xe2, 0xd3, 0x08, 0xd1, 0x61, 0x46, 0xd5, 0xc9, 0xb0, 0xd0, 0xde, 0xbd, 0x97, 0xd7, 0x9c, 0xe8
+};
+const uint32_t SigGen_Msg_len = 128;
+
+/* Result of hashing SigGen_Msg (You can verify using "openssl dgst -sha256" or "sha256sum" utilities)*/
+const uint8_t SigGen_Hash_Msg[] = {
+  0x44, 0xac, 0xf6, 0xb7, 0xe3, 0x6c, 0x13, 0x42, 0xc2, 0xc5, 0x89, 0x72, 0x04, 0xfe, 0x09, 0x50, 
+  0x4e, 0x1e, 0x2e, 0xfb, 0x1a, 0x90, 0x03, 0x77, 0xdb, 0xc4, 0xe7, 0xa6, 0xa1, 0x33, 0xec, 0x56
+};
+const uint32_t SigGen_Hash_Msg_len = 32;
+
+const uint8_t SigGen_d[] = {
+  0x51, 0x9b, 0x42, 0x3d, 0x71, 0x5f, 0x8b, 0x58, 0x1f, 0x4f, 0xa8, 0xee, 0x59, 0xf4, 0x77, 0x1a,
+  0x5b, 0x44, 0xc8, 0x13, 0x0b, 0x4e, 0x3e, 0xac, 0xca, 0x54, 0xa5, 0x6d, 0xda, 0x72, 0xb4, 0x64
+};
+const uint32_t SigGen_d_len = 32;
+
+const uint8_t SigGen_Qx[] = {
+  0x1c, 0xcb, 0xe9, 0x1c, 0x07, 0x5f, 0xc7, 0xf4, 0xf0, 0x33, 0xbf, 0xa2, 0x48, 0xdb, 0x8f, 0xcc,
+  0xd3, 0x56, 0x5d, 0xe9, 0x4b, 0xbf, 0xb1, 0x2f, 0x3c, 0x59, 0xff, 0x46, 0xc2, 0x71, 0xbf, 0x83
+};
+const uint32_t SigGen_Qx_len = 32;
+
+const uint8_t SigGen_Qy[] = {
+  0xce, 0x40, 0x14, 0xc6, 0x88, 0x11, 0xf9, 0xa2, 0x1a, 0x1f, 0xdb, 0x2c, 0x0e, 0x61, 0x13, 0xe0,
+  0x6d, 0xb7, 0xca, 0x93, 0xb7, 0x40, 0x4e, 0x78, 0xdc, 0x7c, 0xcd, 0x5c, 0xa8, 0x9a, 0x4c, 0xa9
+};
+const uint32_t SigGen_Qy_len = 32;
+
+const uint8_t SigGen_k[] = {
+  0x94, 0xa1, 0xbb, 0xb1, 0x4b, 0x90, 0x6a, 0x61, 0xa2, 0x80, 0xf2, 0x45, 0xf9, 0xe9, 0x3c, 0x7f,
+  0x3b, 0x4a, 0x62, 0x47, 0x82, 0x4f, 0x5d, 0x33, 0xb9, 0x67, 0x07, 0x87, 0x64, 0x2a, 0x68, 0xde
+};
+const uint32_t SigGen_k_len = 32;
+
+const uint8_t SigGen_R[] = {
+  0xf3, 0xac, 0x80, 0x61, 0xb5, 0x14, 0x79, 0x5b, 0x88, 0x43, 0xe3, 0xd6, 0x62, 0x95, 0x27, 0xed,
+  0x2a, 0xfd, 0x6b, 0x1f, 0x6a, 0x55, 0x5a, 0x7a, 0xca, 0xbb, 0x5e, 0x6f, 0x79, 0xc8, 0xc2, 0xac
+};
+const uint32_t SigGen_R_len = 32;
+
+const uint8_t SigGen_S[] = {
+  0x8b, 0xf7, 0x78, 0x19, 0xca, 0x05, 0xa6, 0xb2, 0x78, 0x6c, 0x76, 0x26, 0x2b, 0xf7, 0x37, 0x1c,
+  0xef, 0x97, 0xb2, 0x18, 0xe9, 0x6f, 0x17, 0x5a, 0x3c, 0xcd, 0xda, 0x2a, 0xcc, 0x05, 0x89, 0x03
+};
+const uint32_t SigGen_S_len = 32;
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/SigGen.txt b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/SigGen.txt
new file mode 100644
index 000000000..35cf1daa6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/SigGen.txt
@@ -0,0 +1,5878 @@
+#  CAVS 11.2
+#  "SigVer" information for "ecdsa_values"
+#  Curves/SHAs selected: P-224,SHA-224 P-224,SHA-256 P-224,SHA-384 P-224,SHA-512 P-256,SHA-224 P-256,SHA-256 P-256,SHA-384 P-256,SHA-512 P-384,SHA-224 P-384,SHA-256 P-384,SHA-384 P-384,SHA-512 P-521,SHA-224 P-521,SHA-256 P-521,SHA-384 P-521,SHA-512 K-233,SHA-224 K-233,SHA-256 K-233,SHA-384 K-233,SHA-512 K-283,SHA-224 K-283,SHA-256 K-283,SHA-384 K-283,SHA-512 K-409,SHA-224 K-409,SHA-256 K-409,SHA-384 K-409,SHA-512 K-571,SHA-224 K-571,SHA-256 K-571,SHA-384 K-571,SHA-512 B-233,SHA-224 B-233,SHA-256 B-233,SHA-384 B-233,SHA-512 B-283,SHA-224 B-283,SHA-256 B-283,SHA-384 B-283,SHA-512 B-409,SHA-224 B-409,SHA-256 B-409,SHA-384 B-409,SHA-512 BB-571,SHA-224 B-571,SHA-256 B-571,SHA-384 B-571,SHA-512
+#  Generated on Tue Aug 16 15:27:42 2011
+
+
+
+
+[P-224,SHA-224]
+
+Msg = 699325d6fc8fbbb4981a6ded3c3a54ad2e4e3db8a5669201912064c64e700c139248cdc19495df081c3fc60245b9f25fc9e301b845b3d703a694986e4641ae3c7e5a19e6d6edbf1d61e535f49a8fad5f4ac26397cfec682f161a5fcd32c5e780668b0181a91955157635536a22367308036e2070f544ad4fff3d5122c76fad5d
+d = 16797b5c0c7ed5461e2ff1b88e6eafa03c0f46bf072000dfc830d615
+Qx = 605495756e6e88f1d07ae5f98787af9b4da8a641d1a9492a12174eab
+Qy = f5cc733b17decc806ef1df861a42505d0af9ef7c3df3959b8dfc6669
+k = d9a5a7328117f48b4b8dd8c17dae722e756b3ff64bd29a527137eec0
+R = 2fc2cff8cdd4866b1d74e45b07d333af46b7af0888049d0fdbc7b0d6
+S = 8d9cc4c8ea93e0fd9d6431b9a1fd99b88f281793396321b11dac41eb
+
+Msg = 7de42b44db0aa8bfdcdac9add227e8f0cc7ad1d94693beb5e1d325e5f3f85b3bd033fc25e9469a89733a65d1fa641f7e67d668e7c71d736233c4cba20eb83c368c506affe77946b5e2ec693798aecd7ff943cd8fab90affddf5ad5b8d1af332e6c5fe4a2df16837700b2781e08821d4fbdd8373517f5b19f9e63b89cfeeeef6f
+d = cf020a1ff36c28511191482ed1e5259c60d383606c581948c3fbe2c5
+Qx = fa21f85b99d3dc18c6d53351fbcb1e2d029c00fa7d1663a3dd94695e
+Qy = e9e79578f8988b168edff1a8b34a5ed9598cc20acd1f0aed36715d88
+k = c780d047454824af98677cf310117e5f9e99627d02414f136aed8e83
+R = 45145f06b566ec9fd0fee1b6c6551a4535c7a3bbfc0fede45f4f5038
+S = 7302dff12545b069cf27df49b26e4781270585463656f2834917c3ca
+
+Msg = af0da3adab82784909e2b3dadcecba21eced3c60d7572023dea171044d9a10e8ba67d31b04904541b87fff32a10ccc6580869055fec6216a00320a28899859a6b61faba58a0bc10c2ba07ea16f214c3ddcc9fc5622ad1253b63fe7e95227ae3c9caa9962cffc8b1c4e8260036469d25ab0c8e3643a820b8b3a4d8d43e4b728f9
+d = dde6f173fa9f307d206ce46b4f02851ebce9638a989330249fd30b73
+Qx = fc21a99b060afb0d9dbf3250ea3c4da10be94ce627a65874d8e4a630
+Qy = e8373ab7190890326aac4aacca3eba89e15d1086a05434dd033fd3f3
+k = 6629366a156840477df4875cfba4f8faa809e394893e1f5525326d07
+R = 41f8e2b1ae5add7c24da8725a067585a3ad6d5a9ed9580beb226f23a
+S = a5d71bff02dce997305dd337128046f36714398f4ef6647599712fae
+
+Msg = cfa56ae89727df6b7266f69d6636bf738f9e4f15f49c42a0123edac4b3743f32ea52389f919ceb90575c4184897773b2f2fc5b3fcb354880f15c93383215d3c2551fcc1b4180a1ac0f69c969bbc306acd115ce3976eff518540f43ad4076dbb5fbad9ce9b3234f1148b8f5e059192ff480fc4bcbd00d25f4d9f5ed4ba5693b6c
+d = aeee9071248f077590ac647794b678ad371f8e0f1e14e9fbff49671e
+Qx = fad0a34991bbf89982ad9cf89337b4bd2565f84d5bdd004289fc1cc3
+Qy = 5d8b6764f28c8163a12855a5c266efeb9388df4994b85a8b4f1bd3bc
+k = 1d35d027cd5a569e25c5768c48ed0c2b127c0f99cb4e52ea094fe689
+R = 2258184ef9f0fa698735379972ce9adf034af76017668bfcdab978de
+S = 866fb8e505dea6c909c2c9143ec869d1bac2282cf12366130ff2146c
+
+Msg = c223c8009018321b987a615c3414d2bb15954933569ca989de32d6bf11107bc47a330ab6d88d9b50d106cf5777d1b736b14bc48deda1bc573a9a7dd42cd061860645306dce7a5ba8c60f135a6a21999421ce8c4670fe7287a7e9ea3aa1e0fa82721f33e6e823957fe86e2283c89ef92b13cd0333c4bb70865ae1919bf538ea34
+d = 29c204b2954e1406a015020f9d6b3d7c00658298feb2d17440b2c1a4
+Qx = 0e0fc15e775a75d45f872e5021b554cc0579da19125e1a49299c7630
+Qy = cb64fe462d025ae2a1394746bdbf8251f7ca5a1d6bb13e0edf6b7b09
+k = 39547c10bb947d69f6c3af701f2528e011a1e80a6d04cc5a37466c02
+R = 86622c376d326cdf679bcabf8eb034bf49f0c188f3fc3afd0006325d
+S = 26613d3b33c70e635d7a998f254a5b15d2a3642bf321e8cff08f1e84
+
+Msg = 1c27273d95182c74c100d85b5c08f4b26874c2abc87f127f304aedbf52ef6540eba16dd664ae1e9e30ea1e66ff9cc9ab5a80b5bcbd19dde88a29ff10b50a6abd73388e8071306c68d0c9f6caa26b7e68de29312be959b9f4a5481f5a2ad2070a396ed3de21096541cf58c4a13308e08867565bf2df9d649357a83cdcf18d2cd9
+d = 8986a97b24be042a1547642f19678de4e281a68f1e794e343dabb131
+Qx = 2c070e68e8478341938f3d5026a1fe01e778cdffbebbdd7a4cd29209
+Qy = cde21c9c7c6590ba300715a7adac278385a5175b6b4ea749c4b6a681
+k = 509712f9c0f3370f6a09154159975945f0107dd1cee7327c68eaa90b
+R = 57afda5139b180de96373c3d649700682e37efd56ae182335f081013
+S = eb6cd58650cfb26dfdf21de32fa17464a6efc46830eedc16977342e6
+
+Msg = 069ae374971627f6b8503f3aa63ab52bcf4f3fcae65b98cdbbf917a5b08a10dc760056714db279806a8d43485320e6fee0f1e0562e077ee270ace8d3c478d79bcdff9cf8b92fdea68421d4a276f8e62ae379387ae06b60af9eb3c40bd7a768aeffccdc8a08bc78ca2eca18061058043a0e441209c5c594842838a4d9d778a053
+d = d9aa95e14cb34980cfddadddfa92bde1310acaff249f73ff5b09a974
+Qx = 3a0d4b8e5fad1ea1abb8d3fb742cd45cd0b76d136e5bbb33206ad120
+Qy = c90ac83276b2fa3757b0f226cd7360a313bc96fd8329c76a7306cc7d
+k = 1f1739af68a3cee7c5f09e9e09d6485d9cd64cc4085bc2bc89795aaf
+R = 09bbdd003532d025d7c3204c00747cd52ecdfbc7ce3dde8ffbea23e1
+S = 1e745e80948779a5cc8dc5cb193beebb550ec9c2647f4948bf58ba7d
+
+Msg = d0d5ae3e33600aa21c1606caec449eee678c87cb593594be1fbb048cc7cfd076e5cc7132ebe290c4c014e7a517a0d5972759acfa1438d9d2e5d236d19ac92136f6252b7e5bea7588dcba6522b6b18128f003ecab5cb4908832fb5a375cf820f8f0e9ee870653a73dc2282f2d45622a2f0e85cba05c567baf1b9862b79a4b244e
+d = 380fb6154ad3d2e755a17df1f047f84712d4ec9e47d34d4054ea29a8
+Qx = 4772c27cca3348b1801ae87b01cb564c8cf9b81c23cc74468a907927
+Qy = de9d253935b09617a1655c42d385bf48504e06fa386f5fa533a21dcb
+k = 14dbdffa326ba2f3d64f79ff966d9ee6c1aba0d51e9a8e59f5686dc1
+R = ff6d52a09ca4c3b82da0440864d6717e1be0b50b6dcf5e1d74c0ff56
+S = 09490be77bc834c1efaa23410dcbf800e6fae40d62a737214c5a4418
+
+Msg = 79b7375ae7a4f2e4adad8765d14c1540cd9979db38076c157c1837c760ca6febbb18fd42152335929b735e1a08041bd38d315cd4c6b7dd2729de8752f531f07fe4ddc4f1899debc0311eef0019170b58e08895b439ddf09fbf0aeb1e2fd35c2ef7ae402308c3637733802601dd218fb14c22f57870835b10818369d57d318405
+d = 6b98ec50d6b7f7ebc3a2183ff9388f75e924243827ddded8721186e2
+Qx = 1f249911b125348e6e0a473479105cc4b8cfb4fa32d897810fc69ffe
+Qy = a17db03b9877d1b6328329061ea67aec5a38a884362e9e5b7d7642dc
+k = ab3a41fedc77d1f96f3103cc7dce215bf45054a755cf101735fef503
+R = 70ccc0824542e296d17a79320d422f1edcf9253840dafe4427033f40
+S = e3823699c355b61ab1894be3371765fae2b720405a7ce5e790ca8c00
+
+Msg = 8c7de96e6880d5b6efc19646b9d3d56490775cb3faab342e64db2e388c4bd9e94c4e69a63ccdb7e007a19711e69c06f106b71c983a6d97c4589045666c6ab5ea7b5b6d096ddf6fd35b819f1506a3c37ddd40929504f9f079c8d83820fc8493f97b2298aebe48fdb4ff472b29018fc2b1163a22bfbb1de413e8645e871291a9f6
+d = 8dda0ef4170bf73077d685e7709f6f747ced08eb4cde98ef06ab7bd7
+Qx = 7df67b960ee7a2cb62b22932457360ab1e046c1ec84b91ae65642003
+Qy = c764ca9fc1b0cc2233fa57bdcfedaab0131fb7b5f557d6ca57f4afe0
+k = 9ef6ebd178a76402968bc8ec8b257174a04fb5e2d65c1ab34ab039b9
+R = eef9e8428105704133e0f19636c89e570485e577786df2b09f99602a
+S = 8c01f0162891e4b9536243cb86a6e5c177323cca09777366caf2693c
+
+Msg = c89766374c5a5ccef5823e7a9b54af835ac56afbbb517bd77bfecf3fea876bd0cc9ea486e3d685cfe3fb05f25d9c67992cd7863c80a55c7a263249eb3996c4698ad7381131bf3700b7b24d7ca281a100cf2b750e7f0f933e662a08d9f9e47d779fb03754bd20931262ff381a2fe7d1dc94f4a0520de73fa72020494d3133ecf7
+d = 3dbe18cd88fa49febfcb60f0369a67b2379a466d906ac46a8b8d522b
+Qx = b10150fd797eb870d377f1dbfa197f7d0f0ad29965af573ec13cc42a
+Qy = 17b63ccefbe27fb2a1139e5757b1082aeaa564f478c23a8f631eed5c
+k = 385803b262ee2ee875838b3a645a745d2e199ae112ef73a25d68d15f
+R = 1d293b697f297af77872582eb7f543dc250ec79ad453300d264a3b70
+S = 517a91b89c4859fcc10834242e710c5f0fed90ac938aa5ccdb7c66de
+
+Msg = 30f0e3b502eec5646929d48fd46aa73991d82079c7bd50a38b38ec0bd84167c8cf5ba39bec26999e70208af9b445046cd9d20c82b7629ca1e51bdd00daddbc35f9eb036a15ac57898642d9db09479a38cc80a2e41e380c8a766b2d623de2de798e1eabc02234b89b85d60154460c3bf12764f3fbf17fcccc82df516a2fbe4ecf
+d = c906b667f38c5135ea96c95722c713dbd125d61156a546f49ddaadc6
+Qx = 3c9b4ef1748a1925578658d3af51995b989ad760790157b25fe09826
+Qy = 55648f4ff4edfb899e9a13bd8d20f5c24b35dc6a6a4e42ed5983b4a0
+k = b04d78d8ac40fefadb99f389a06d93f6b5b72198c1be02dbff6195f0
+R = 4bdd3c84647bad93dcaffd1b54eb87fc61a5704b19d7e6d756d11ad0
+S = fdd81e5dca54158514f44ba2330271eff4c618330328451e2d93b9fb
+
+Msg = 6bbb4bf987c8e5069e47c1a541b48b8a3e6d14bfd9ac6dfaa7503b64ab5e1a55f63e91cf5c3e703ac27ad88756dd7fb2d73b909fc15302d0592b974d47e72e60ed339a40b34d39a49b69ea4a5d26ce86f3ca00a70f1cd416a6a5722e8f39d1f0e966981803d6f46dac34e4c7640204cd0d9f1e53fc3acf30096cd00fa80b3ae9
+d = 3456745fbd51eac9b8095cd687b112f93d1b58352dbe02c66bb9b0cc
+Qx = f0acdfbc75a748a4a0ac55281754b5c4a364b7d61c5390b334daae10
+Qy = 86587a6768f235bf523fbfc6e062c7401ac2b0242cfe4e5fb34f4057
+k = 854b20c61bcdf7a89959dbf0985880bb14b628f01c65ef4f6446f1c1
+R = a2601fbb9fe89f39814735febb349143baa934170ffb91c6448a7823
+S = bf90f9305616020a0e34ef30803fc15fa97dffc0948452bbf6cb5f66
+
+Msg = 05b8f8e56214d4217323f2066f974f638f0b83689fc4ed1201848230efdc1fbca8f70359cecc921050141d3b02c2f17aa306fc2ce5fc06e7d0f4be162fcd985a0b687b4ba09b681cb52ffe890bf5bb4a104cb2e770c04df433013605eb8c72a09902f4246d6c22b8c191ef1b0bece10d5ce2744fc7345307dd1b41b6eff0ca89
+d = 2c522af64baaca7b7a08044312f5e265ec6e09b2272f462cc705e4c3
+Qx = 5fad3c047074b5de1960247d0cc216b4e3fb7f3b9cd960575c8479fc
+Qy = e4fc9c7f05ff0b040eb171fdd2a1dfe2572c564c2003a08c3179a422
+k = 9267763383f8db55eed5b1ca8f4937dc2e0ca6175066dc3d4a4586af
+R = 422e2e9fe535eb62f11f5f8ce87cf2e9ec65e61c06737cf6a0019ae6
+S = 116cfcf0965b7bc63aecade71d189d7e98a0434b124f2afbe3ccf0a9
+
+Msg = e5c979f0832242b143077bce6ef146a53bb4c53abfc033473c59f3c4095a68b7a504b609f2ab163b5f88f374f0f3bff8762278b1f1c37323b9ed448e3de33e6443796a9ecaa466aa75175375418186c352018a57ce874e44ae72401d5c0f401b5a51804724c10653fded9066e8994d36a137fdeb9364601daeef09fd174dde4a
+d = 3eff7d07edda14e8beba397accfee060dbe2a41587a703bbe0a0b912
+Qx = 6dd84f4d66f362844e41a7913c40b4aad5fa9ba56bb44c2d2ed9efac
+Qy = 15f65ebcdf2fd9f8035385a330bdabec0f1cd9cc7bc31d2fadbe7cda
+k = 7bb48839d7717bab1fdde89bf4f7b4509d1c2c12510925e13655dead
+R = 127051d85326049115f307af2bc426f6c2d08f4774a0b496fb6982b1
+S = 6857e84418c1d1179333b4e5307e92abade0b74f7521ad78044bf597
+
+[P-224,SHA-256]
+
+Msg = 2b49de971bb0f705a3fb5914eb7638d72884a6c3550667dbfdf301adf26bde02f387fd426a31be6c9ff8bfe8690c8113c88576427f1466508458349fc86036afcfb66448b947707e791e71f558b2bf4e7e7507773aaf4e9af51eda95cbce0a0f752b216f8a54a045d47801ff410ee411a1b66a516f278327df2462fb5619470e
+d = 888fc992893bdd8aa02c80768832605d020b81ae0b25474154ec89aa
+Qx = 4c741e4d20103670b7161ae72271082155838418084335338ac38fa4
+Qy = db7919151ac28587b72bad7ab180ec8e95ab9e2c8d81d9b9d7e2e383
+k = 06f7a56007825433c4c61153df1a135eee2f38ec687b492ed40d9c90
+R = 0909c9b9cae8d2790e29db6afdb45c04f5b072c4c20410c7dc9b6772
+S = 298f4fcae1fe271da1e0345d11d07a1fca43f58af4c113b909eedea0
+
+Msg = 1fa7201d96ad4d190415f2656d1387fa886afc38e5cd18b8c60da367acf32c627d2c9ea19ef3f030e559fc2a21695cdbb65ddf6ba36a70af0d3fa292a32de31da6acc6108ab2be8bd37843338f0c37c2d62648d3d49013edeb9e179dadf78bf885f95e712fcdfcc8a172e47c09ab159f3a00ed7b930f628c3c48257e92fc7407
+d = 5b5a3e186e7d5b9b0fbdfc74a05e0a3d85dc4be4c87269190c839972
+Qx = 897089f4ef05b943eeac06589f0e09ccc571a6add3eb1610a2fc830f
+Qy = 62ba3f6b3e6f0f062058b93e6f25b6041246c5be13584a41cae7e244
+k = 5b6f7eca2bcc5899fce41b8169d48cd57cf0c4a1b66a30a150072676
+R = f12c9985d454ffbc899ebbbb6cf43e3debcac7f19029f8f2f35cce31
+S = 12fcb848adbd8b1b4c72b2b54a04d936e4a5f480ae2a3ea2e3c1baae
+
+Msg = 74715fe10748a5b98b138f390f7ca9629c584c5d6ad268fc455c8de2e800b73fa1ea9aaee85de58baa2ce9ce68d822fc31842c6b153baef3a12bf6b4541f74af65430ae931a64c8b4950ad1c76b31aea8c229b3623390e233c112586aa5907bbe419841f54f0a7d6d19c003b91dc84bbb59b14ec477a1e9d194c137e21c75bbb
+d = f60b3a4d4e31c7005a3d2d0f91cb096d016a8ddb5ab10ecb2a549170
+Qx = 40a4ab1e6a9f84b4dedb81795e6a7124d1cfdfd7ec64c5d4b9e32666
+Qy = 83aa32a3c2fc068e62626f2dafce5d7f050e826e5c145cd2d13d1b27
+k = c31150420dfb38ba8347e29add189ec3e38c14b0c541497fb90bf395
+R = bf6c6daa89b21211ea2c9f45192d91603378d46b1a5057962dafaf12
+S = cb6b237950e0f0369323055cd1f643528c7a64616f75b11c4ddd63c7
+
+Msg = d10131982dd1a1d839aba383cd72855bf41061c0cb04dfa1acad3181f240341d744ca6002b52f25fb3c63f16d050c4a4ef2c0ebf5f16ce987558f4b9d4a5ad3c6b81b617de00e04ba32282d8bf223bfedbb325b741dfdc8f56fa85c65d42f05f6a1330d8cc6664ad32050dd7b9e3993f4d6c91e5e12cbd9e82196e009ad22560
+d = c8fc474d3b1cba5981348de5aef0839e376f9f18e7588f1eed7c8c85
+Qx = 66f49457ed15f67ed4042195856f052fe774077f61cebcb9efddc365
+Qy = 3a6e3f3423eec7308a69eb1b0416d67cc3b84d24f251d7cbdb45c079
+k = 5e5405ae9ab6164bb476c1bb021ec78480e0488736e4f8222920fbd9
+R = 7b7beaf9f696ca1a8051527478c4c075ab45aa4768937886dbf38618
+S = 93d4cf110a37c5a6f15c4e6024822118539e860dee2f60b8c3f462f6
+
+Msg = ef9dbd90ded96ad627a0a987ab90537a3e7acc1fdfa991088e9d999fd726e3ce1e1bd89a7df08d8c2bf51085254c89dc67bc21e8a1a93f33a38c18c0ce3880e958ac3e3dbe8aec49f981821c4ac6812dd29fab3a9ebe7fbd799fb50f12021b48d1d9abca8842547b3b99befa612cc8b4ca5f9412e0352e72ab1344a0ac2913db
+d = 04ef5d2a45341e2ace9af8a6ebd25f6cde45453f55b7a724eb6c21f6
+Qx = 8d642868e4d0f55ee62a2052e6b806b566d2ac79dbde7939fe725773
+Qy = 79505a57cd56904d2523b3e1281e9021167657d38aeb7d42fc8ec849
+k = ec60ea6f3d6b74d102e5574182566b7e79a69699a307fee70a2d0d22
+R = 2fd7fcbb7832c97ce325301dd338b279a9e28b8933284d49c6eabcf6
+S = 550b2f1efc312805a6ed8f252e692d8ee19eaa5bcd5d0cda63a1a3f0
+
+Msg = 4cc91f744ac858d3577e48813219aa3538dd813b186b42d1e6218376f07cc1cc448ddd6b37240e98bf953f49cf54d65c12878b33c0bf6eb1c60254f0b6fa974f847e53abc56773eef6f29885dfc619e6a48fc15a667ca94001a0c945b6357a53221b0f4b266181456b0d2d25e90708777f1a6f85971c00140c631c1991e0fd06
+d = 35d4bbe77d149812339e85c79483cb270bdac56bbf30b5ef3d1f4d39
+Qx = 7924b1d7f5920cce98e25094e40f2eb3eb80d70b17e14b3d36c3671c
+Qy = 26c5af35f71e61858582b7cc2b41790597c53ee514ffdf7a289d108c
+k = 751869c1d0e79eb30aae8fbfb6d97bfa332123fd6b6c72c9cd3c1796
+R = 26bb1b92b0f01e94eba5fa429271371db527ce857abba13bd1103f64
+S = 836aba9c63e1252c2b2d72a21e6a41b82241ebe32647e7f814652bcb
+
+Msg = 58f43cc1924de4bc5867664adbc9d26b4f096a43aca47c27c52851b006dc2a658919ef9ce5b5ac48372703be15ac51631c2bd84b88f479f113b0569a9a09e230ec1e8e573474c6075284d3e57d973829af35325d9e7dab4a5f9b065155bbcaff3642a82ef4c9b9e127d3575c050721653da3b087d3fa394192897a5519527d19
+d = 2c291a393281b75264c9b8817af684fa86a1cdc900822f74039dc5d6
+Qx = 18cb5826ad60e6696bf07655032a3749f6577ca36da3ccd6e66a137c
+Qy = 194e14820fe02d784fd1363ff7a30399518309765bd3f4412d646da2
+k = e2a860416229dfd3f5a5cc92344ca015093a543943a0d8f73bf2b2fd
+R = 00e300c1ef4a8c4ca5da6413856f8981db49de29bdf03f32ffc3ceab
+S = f250f18a51ba5f63e1584097841099fa6ae4e98ee458c061d1d5aed7
+
+Msg = 113a2806b052fde683ee09453098e402204155afb3776fd1cad3a9103421d327eab8f9ec0dd050ffcc83f93b34ea707705fabeccfe43ab1a71c95298fd3ec769d99ead1066950eee677d225816e0faad19cf69e1b35d16771689e2092cafe16d7c0dd7b0db73fffb8d0f3eaed83004dd21e753530ec939c89ba25578fa5f785b
+d = 831ea25dbeda33d272a1382c5def0e83929170ab06a629eed6ee244b
+Qx = 076518e393940d42dfd09819409d66966d8c9189c83d554a9cc8a082
+Qy = 44d0ceaf4c0f50e46bea4a52e30423ce3ada19edd363ac5694c65cb8
+k = 6be6dd9f6a083915ccba54626caf12d246d3aece0a7eda7d8d85599c
+R = ff1460946e06fb6f5d35e8d2625ca70ffb9b45308e3fabf6ad8351b1
+S = 6029aa3990918e8cb8a388d53b0772e5cdfff49c3405fe0d3a95933a
+
+Msg = 64cbfc8f2e2149a31b3e8a80c4a552f6c62aaeb7990b6e0ee55500a9d17be04213406578caf315951086dff5c2af3b5ce17d425d185101ef26f86396ba3a129a4f3f8e2dd595f59efb6c0f5c2dcc394569d7268695e9ac7daa84203f1f1895f1f9e4b514a5c9cd23baa63454710144fe735ad9b8f42d8c43267aa434a26d7e5f
+d = 70f74c7324ef137318b610ead8ddc5b964e0eed3750b20612fc2e67b
+Qx = 279649e2a2918e683520cde3fc98b0ae58a7100e8de35e7c9cc797b6
+Qy = aa4de6be34be61f02880139787b9038f4554a8ef1c994b887c2974b5
+k = 8e984864f86f7a2a73f3edda17dbccd13fac8fa4b872814abf223b1b
+R = 3b18736fa11d04e27e2614cda03a63ec11a180f357b0b3192920d09c
+S = 2f0f3dbd570727b14fbb29155538e62c930dd51c4035275c1365dc60
+
+Msg = a10a11c8e30fff118d371daf824f16c08200b83ea059436466a4611ccac93b2dea2de8c1006f946196aef7fe9b0c251a391b0340f21797798278b412ff2b53842eec6450728e2bca062f8337a2c204b9ea04ff660cd4d4db559f2f11c4d8ef199021339fcc82396f7a93926cf5f247e37d8067fe50692de54f102bd5ab51925c
+d = 026be5789886d25039c11d7d58a11a6e1d52cb1d5657561f2165b8a8
+Qx = 3fa617c50b177da1a2bdb98b780ad21ad1195c4bd24465f6187de3c9
+Qy = e3fd8d8876dfd03a4a4e31a1acad3a08d983826d286c250c4e5620c1
+k = 0128b8e3f50731eb5fcc223517fc0cf6b96cd1d2807eb4524bc46f77
+R = 3a6b633f96f3d0b6d54f7fb29ac33709e4f0dd8fa0e51606ed9765ca
+S = 63e8c119dfa51784decd864f6911f2210a80f8f02d472d88df10d119
+
+Msg = b3f720bf566ffa369259f4361959ae0641d2755ec264a4c4349981df2b02563275b2b9adb5aee47f7a456760a971991ffed6b17809bb9694138d1677fa916123795239353158fc6b22d10f20d26f5d2dcd8c56c44373eea5b93067dba2d7c5318dac2e9e8714873cb1b37f58c011fd14fa1e535554efe05f468bfc8e11cd8b99
+d = e79c18d935c2839644762867aa793201f96a3cde080c5968412ce784
+Qx = b7ae1e992b1c7fde1141f40bd913358538ca0f07f62b729f13cea327
+Qy = 811252d12120e04805fc171a439d382c43b68a21e1a0bdf5e4ec1da4
+k = 7abedab1d36f4f0959a03d968b27dd5708223b66e0fc48594d827361
+R = d35047d74e1e7305bb8c1a94e8ae47cb1591c3437a3e185e00afe710
+S = d9c425c9d5feb776ac8952e6c4eee0ecd68aef2f0e7bff2e49c9185e
+
+Msg = 0a398a46df7ccc48d1e7833f8bbc67100f1ef77a62dc78bbc115b2a662f9591fbaaa91ad3d788e2fdd1b3164e45293d4f5686c151296901768028ac80ded4bf89c647ad35f0c7c4cb318c0c757c1d83c44d850e5fd4677281b3f13b1ee54de79c8c042813f9d3312dcc6111a68299cb7e829557d7f3d96e702f65aefc6499415
+d = 0d087f9d1f8ae29c9cf791490efc4a5789a9d52038c4b1d22494ad8c
+Qx = cd95cf8fb1cd21690f40d647f2353672a1076cc6c46bddaad2d0fc56
+Qy = 934262f74d9ee0f8a2754f64cb7415923d64bf00c94a39b52803f577
+k = 557d0e3995dc6377b3911546dd7aeaeec62a6d8f2af6a274382fc37f
+R = 56df0ea6afdcc232ceb41729eec00cf906b69b6e28423a36d3c92cc5
+S = f4f70fd948c9a147f55317fdea7b8a84c33e721014552d5800d63edc
+
+Msg = 8c33616821a6038b448d8918668977fcf1ef5aa0cf7c341837b39bbcc9bca875a3757f4b392630e9995b9bbe4eb66978b877586adaa02f99d2344dae082a7603351d8ffcfca081ab403cd0acb90d078dd1d0789c2eb3185c62bff2d9f04cd38e509e3b83c12ed0a5c6808fc42f7ba5b06acdc496c8ad9be648ee6a4505f8560f
+d = 0830aebb6577d3a3be3ba54a4501c987b0e0bb593267b9bbadb66583
+Qx = b88652020e083ccc1c43dc83d1881884dd4c7e3b4e3460b344b1ea64
+Qy = 22b69b517f86d7c26dc37c0f8feb4bb07fe876149fbcc3334fd2805b
+k = e4f4a3280574c704c2fde47ca81ec883d27f2c5a961a294db7cda9d2
+R = b30b8a0079d9a134b5e1618c2ac63e3fbe0e95866b9dbc5f423f2707
+S = 3dc36746610271ef66e0aa52cc2ccadc5c9b08dc769e4dc4f6538c11
+
+Msg = 94d56535fd4edfe67a0daa6579f9d53bf6b7b8830ae2aeb62892ff59f18756ddf2811b449c7d20d65d54f8507de4e7c50eaa084830637812aa4b250a4d61ab67845be36e4a41cdc0a70f8d6e3a63d4514f0dc197e6486015046a316153d5f3a3a4a0ae1ed7ea5fa55e12e73d333333685c02e0eb636234ea7e6d4b76b4b76b5a
+d = 2acc9b97e625263e8e4cd164302c7d1e078bfcdd706111a13ccda5b2
+Qx = ce1a06f82df874dded37cca03b56c0648e4e8917ecd40ee73ee61588
+Qy = ceb6177b8f1ac7c5c6e6e1f7737cc3026952ee392badd2cd7af32f9d
+k = e401fa80f96480d437ed4f61a783888062ec33d530b188fd48016a6d
+R = 28674f447c4742e4087bbccfb522fbad4e18b56031d2ce8f532b078a
+S = a5a7a13d15b423dd17771f73cea98d89dbffa846cc209b45c0e29b76
+
+Msg = 5d8ebdf9eb28b47bdafaa36bf0b66a9eaf99b6c83959da4f2b1151b4f4ecd28fb115a64c0cb9491093a7e9b9c53ec423e4c72e7765bb9c818da0e8c428667e44474a71db4867130c77c40bfd8544b2d7b9d6464d2b8e6a48482153256a32437c3a747231f51134dd14c703407e31146a6fcde23bededcf16950486e90ca69ac0
+d = f4e873d4fb944fb52323406f933815092b7672221de4d1c45917f3fc
+Qx = 0dc2cdddb990341adb1de73f02d87fc3822485a659a15145f4251d5f
+Qy = cf78b2a83c7352eda1af2c74e1804ea04b35f76c04e89d90281dc2bb
+k = 5d1476c682a64162fd2fdc82696fc8cab1469a86f707ea2757416e40
+R = 82982b38ed465138df4018d7cfb835edcb591cb57446ca49d163782b
+S = 8ef1d7b326cabee7f7ab95b7b98d3c27a069c0fd95a1599c0ccb422b
+
+[P-224,SHA-384]
+
+Msg = 25e4416695f77551fdce276355528ccf1ddc2483821c5d22d751d50111ca2fadc6593b52c74f4b5957494f1df25b0b2f86950d0d19229ec6506fee8581d2dd09d48418b146ff16bd84a17ca0dc83b1888eb407376da6c8a88fa1e60b8c2a2471dfde4b3996ef673d5bde3d70c434dc9f2488e9de16ae657d29e5e59ec922a1ec
+d = 62c572ee0d6f81b27e591d788bfc2f42b5105d2663078dfb58069ebd
+Qx = bd6ba605639b98fa8113a16a3bb004ddfaec901c98a931206165f4a5
+Qy = a3190b10ef39e88abd60b2293b4707512b45c6c5ed5794cc11454427
+k = 0f0bb1e428bcdebf4dc62a5278068efc0f8ce75f89e89b3630f102b2
+R = aac0ea27e129f544abcc77f110e70bbdd5aa3e425dc39d5e8887025d
+S = 10e5dd06aee6b8419a04aa33d9d5678b0039c3acc3c4b61fe106bfdc
+
+Msg = 9164d633a553deccf3cbd2effccf1387fa3177cd28c95d94a7d1a3e159c5e5c027758cc26493301b2f4d141d8d07a5fe5fead987ce5f30abeafcb48c302afc6c2309f0e93d9b6818cbb6972d222cb7b01302dfe202ae83b89f53150ae4a0e2b8fc0fd1091f19b4ab2e6ab213ab322d04f2c5f57113bfad3c5675227237abf773
+d = e2f86bf73ba9336fa023343060f038e9ad41e5fe868e9f80574619a3
+Qx = f5d5346f17898ea6bbdfff19c216a8757a5dc37b95315f5481628381
+Qy = ae61fd172ac8b7a4f13870a932dece465834cbd4f50bbcfb802c824e
+k = 35724ac043e3b44b73b5a7919cf675190306d26aa67c27c28c873534
+R = 535147c265af138eec50c7fb570bcc8d2e6f675597b0fcc034e536bc
+S = 743812c188a1dddf9fb34b90738f8b2e58760d6cd20ccceb1bb9c516
+
+Msg = 019df05929321ecea7ee1de4f412aba1c8d3c24437db04b194a68a0a59dd871be10bd3a4be6edf551350ea49fc7155a4d887e1221486291abe77a30633a4c4f7868fe2df24311cba0c73804883954460e122387ed414111ff96ff1aebac8b6a6491d8a0d16e48a63bf3d027c0f68ee4a4b234d73b412196706af8ea022b4dcef
+d = b0a203438e2586d7575bc417a4a798e47abc22aa3955b58fc2789f17
+Qx = dc5d217862a1e5b00c95affa9d8b925a72b9beaeb7a86dc397e788d8
+Qy = 5f05f8e976ae1eb1036eca6d683a82850795bf9127dee5f8b2859445
+k = 408e9c8b1f33136d6ddb93ff3a498bc09d4eee99bf69cdd5af0aa5a2
+R = 1b5a964c8b1fc634c6e2b82322499df1d7f0c12a4d2a77723c816ab8
+S = cf54599a36ca064fae0aa936de5266f87704409d22a15d28c01b7f2a
+
+Msg = 5d09d2b1d3fa6e12c10d8b26dc9aabc8dc02bd06e63ff33f8bb91ede4b8694592a69e4ed4cdf6820069e2b9c7803658949e877ffe23bf90bcf5ce1409c06c71d86885a94048b05ac0ec9db193e489a5a2bfa367caf6aa8ecdb032be366174343f6875d2fe1785e8d77334f5f469cec64998e08d3303e5c9a1923b34fdc105d65
+d = efcfa50fad6fb2065f9a55f28c0c42fa24c809ccb19b6fc6d8ffb085
+Qx = 61521a0cfb72be77ba33cb3b8e022743cd9130ff49e97093b71aa178
+Qy = ce0819aedaf6fce639d0e593f8ab0147eeb6058f5f2b448231584ea9
+k = d1eea821f286eae6ebc1f61b08f9ad4323a3787e94af4c32cd31351b
+R = b37caaa71103752ac559f9eb4943324409ebfa8b585f684dcaa5c411
+S = 7c28e7619e2944ab4b7be022878c8052ebdf2cae5dff4f976c49686a
+
+Msg = 50f6dfc81c6cf189e0a310f992907fe93356cee9dea9a41c7671a8daf3f4cfe0c459ce6122c1e731dbf7593419d7114cb73b46956158a982c5d52c72f43f0f822046093c69aeff1f7e4cd8af00ba655c5baa2e7b6a400b4be1f6fd51b3e4cfb35a69c80a28c5cafb771b6c2e52e0aeef0e3fd045e8d40745f3f8b74fd969f816
+d = 61a17816937987764cdc064dc7b5b4f5b16db1023acdfe25902957dd
+Qx = a7e975c0a8f87c683bb8e31bc160843a7b69c945f4850bd60e1c08c0
+Qy = 8930a454dcc2aa13bed7ea89368b2c9d689d816b2acf4e52585ee9c4
+k = 44b1fdec2629f9075f89c134ac28ff19bfddaa9db02a5d7f853582b4
+R = b0f5635d8bc9c53a1d54a3ec63de59ed66e6b2358d4ab79755414326
+S = 67c68fe265c7e5aba4232deeafb88545a2aa266fb9f2c2bb3f3ae8d2
+
+Msg = e90129ac6672c85bb7b6b18e9dc199c96c81fd65034b53c77818364d512366fb9cd1bc7c82404c451e561fc1ed916c0948f6ac561b33a1ccca093f07684b8c2bafa9e966377bd208556018a5bafb9edcecf70498c7140fe9c8cf3ad8b8c3b0aa489df797944465047465415bb0e24333235fcdd59a98829a3941eaaf62033e82
+d = 79d5367314ec664aa0f6ca36f95549502a05bf8400bf532d669fab8d
+Qx = 3191f0237102dac159032ab2dde53cf56c9ec827b5caddfe9e83c02a
+Qy = b496b1bdcca4434ac0d0d91ea38ff3bc33f9f54095bfe17796d5a9e2
+k = da529c52f5cc1f435d873109cd991d6cd7e1631d9ff1dd9521dd5db6
+R = 8e0ac63903f4921755430572c3f08bc272790639bdf1009fe2a9a714
+S = 6278c841a2d0a270791fe54b36c49d426d67907aa4e4f59c8638ad97
+
+Msg = 3c9a483c9bee33b601549c592a82e95b4319b1e74b777877f0971bcb4273716b268e8f99f876e42f942f4cf08284896bbc1ffbf094ac0956c3cedfc3580cffa8c74fc6db29a371f2da2d05edb9185ece741fe0d3fabfe9d5b4d373755ebed13dc6840cfa3283b9ea46ec8b95c434f253ae86998182e9cc0e95ee64f323fc74b0
+d = 1320eedad4745121793a7eaf732b0b4498f7cb456cac8cf45a1f66f0
+Qx = 9fdd99906ab77fd29e9021bde947d05a7a9eb153612269bfb0899bc9
+Qy = 681b65b9ac8e4c2899bb622dafb253b7bf5a6e38e5f6595f997c291a
+k = 66ed8d8934633f4125f593cf1b1d3745c4db1f15dde60cf46ca1c7f2
+R = 80199485a3a96447b39f7679cd47412a78675ba17dcbd10465dc5b48
+S = a251fd9f136a3cb0dd0bc80659ae032e4a761ba7045da0034553fb8c
+
+Msg = bfc073fdda63c5fccaa0ca8770c293e8154e7aec56128bbac4fdbd541d602216ebf7ca1e02b514d6e396f20683802ba3f334310a9226576926e3bb19ceee27738d13377cbafeb09d091043501702a07aa31d1f29d50ddc55adcf16ffd40578e734a4e6cb6535f26ad48e0c62ad90e79720000e87d419e92dca3e11f943655b03
+d = e18821329447d3f65ba7279e96bd4624ffa1b32b90f6e8331b1e876d
+Qx = 46c9ed837232c47022df2f1a1578fbe65ac9f2e81c98a74cc22ea31a
+Qy = 6fc5e9568ae62b31412a0b0b367242e9fd7e518c83aa06a069e1d90d
+k = a4c1eb402a2fb3af26e0e14a3d2fc8ed3bc1a8b2475270356a79fdd3
+R = d478b68733d8ad44be46766e7b66af782fbdc7ff7ed0b191176da98a
+S = 5eae9160ccf71fd1d359d89cecce72ef8afaeee2365f6ba828aa450a
+
+Msg = 08079955d1a1f33728128c73673ec9f21a6ce138dcab5adc4dc068e6ab57314b9fbd8b013123b2fdafa9524fbdd0288777a233de8055cccfad83046ada6a19f01c47817496667bba8fc8b9456fc0e044a562d931dab1adcb66af8b66325bdf28d83ded3e2937958ccd19da540d70ef2c189f55a506c9c0d63406394c5bd3823b
+d = f73e030d5a696b358986d3efaca121cf71f775f8835a21e6135145d7
+Qx = 9ca2c6ea87ac8dd3a23a5b4010841a7c8af309038882ae44634bcf55
+Qy = b0a347dbd5ded3b8702ac5a457e8b32bd4de06fd315095fa1b7d5fe1
+k = e3cc786c1288ea567836c51d6d69dd0cab5c015987d936ccc3a4beb3
+R = f1234da71761b7a0f49e661a419d2a739bdc4544bf87690e3d2f96db
+S = 096d16bf8020c3d3c233894ad8eb81206010e62c6e692a215e088fd4
+
+Msg = 23900b768f6cd42b8a8df0dcbc9cb5daec8de36b9d5c619adcc1ba2b649103d5af123746cdf19c3fd0665a6fb9338156182aa06181e3c6e37ce56979612af2927440424f89cef43fc754854b8a5c43370808cf5f9929cf47712512ce2f8a2a20d2e9f568c2848b27dfbe09142843c83905ffa5da3b15501761b03dbc2c5398b6
+d = 7a0789323f8741c157a1753ae165ecaf8e8b03a60561f8b80cee467c
+Qx = 101271a9addd4bd1f19d00bf116c8524f52cefd598e85dc381597acb
+Qy = 2f17d14f4d8ccb28b216553718152ba7c104646d8eca986dd9ddea39
+k = d169f04f05b60c625cda864d187938863964dab7bb3b9dfc04b05519
+R = e4a51be686a764b709da23ab48b1985e153c6ee238d945e743907afc
+S = 118a8f1ffe3cd556ce6345bd1a398dd9cc3729b7fd6d8af9bfd82f40
+
+Msg = 1eb28c0bcdd18f73e347f957ece15b4cc83a771b0877e1feaac38e24028fb38ccea8b54ee017dc7c3d5a1327bc6f40b294aa65d7dc487f278846cd101ee84202f14b38aa2c275046aa2577f65ebaea41cd383e8def2fd0b4444dcf426fa75c4082cd7fa035cdb1e0d34a3c79d42130f5b0273eae75bc701dda3aebe7358f41b5
+d = 78e795d0edb11fd9e28dc26b21e751aa89bea0d87932ef11c95c0e18
+Qx = 9edd544107977134bf6360d43ccabb3c94d627c03963c0a04b439627
+Qy = ece4c61d319a0e41f3de7863e7c355bac94395aaa74cdb5f74a87a5b
+k = 36f7c0f76808b826a0a974a1fd6e155e00a73f1d34674a8f88be405a
+R = 3e319444438bc2cc92f323ea842cb402b3c3c2448c89869ef7998edb
+S = 3420cc38f058f41c31e71f4b1ad488f801111c73541de69fcee60695
+
+Msg = efab51855407438fd5c250670366bca3c026ecec4a59394f00d8a4b51746d0c4564366656d507e3e13e62fe7abeb976b8859895848dbaecf6582f1898ea06f00d4247702ed9721bd375aa83ae4c67c2eaa6e080777ea5ecf2cf787d785389560ac91cf63a52f0373c3185e18a3b8a466e21b61a239f1b77624eb1acacc76c4e1
+d = bee02d8bc5bffb3fd3b4c9d6f686409f02662d10150d1e58d689966a
+Qx = 8848f964c847fe9dddc774618d4588c9cd56bbe588d7b1fb369c8bfa
+Qy = ebbb699fbd0dc08859fe9132285fe20dff3b9d561c0640b6e0717607
+k = 59f1450d857b40e5552a4b8cd4ab0df2f01716635d172c1106840f21
+R = a206d8398a16a991bc217f77f23c6f648384f254f255a8a876404444
+S = eb1169cb5b1423dc0bfaffe565ae57f986e00de06405e3e7b605862e
+
+Msg = 31c29ca10279a417f0cc9b1382cf54dbfdfc89f2e6ef08c403c11f580cbf8674b141ed1a417563282d99a55fc616d836421cde9424815c95e7fb7668bf3f137b29937f14882d74e034b732d78d91af7721aac4950734f5fa5d4b4d35534974f8cab6d2e6dca75ddb57e99148c8a59df9fc5bcd723e546e8356f671cf2f65640a
+d = dc0ddf6e501418bb8eafc5d7ccc143369e2aa441df8fc57d5f94a738
+Qx = 063a5d632f4144376e14cfb03ad8ccf1489b613acd184d20dff66545
+Qy = e77727f057b043d8a0f7458196b72e92d11f85b0891c6aaa9d915f58
+k = ff0e5cae2671db7a1b90e22c63e7570bdd27352d45bac31e338debe0
+R = 5bc0b4998481ecbd3b6609184a84ca41d69b08c37138097f559259f8
+S = 0df8828eb1ca85e46405b94e1a2972c34c5e620a54e2f640f04aecc5
+
+Msg = 8db476f92e332519c1a0ece5d8deded6efbd2d8e8784eea0a6b4c3b4296c35f5f8de4317e5c1627b91fb1973fee86c06e4992aa5a20cb7475c8808ff1da354d07a488dffa7838c6ec1e3f99e3acba831f27bee8434eeda3eb36d0c6df3658883cd40068b1bed841310f6eb38d4a3d07d85848770ff7933c054cd8b34662660b1
+d = 229d89b2fcf8441ffc95ebb2ac2ef156e25825782044b2b8bd6a3e01
+Qx = de616848d8044a44789ef1ba3a6dd66fe9257ddc57f7534e59a701be
+Qy = 26cbf74a6d25e5b34b96d30f327abd574cff7f7dbe6686573a7d6c5c
+k = 3b18ca6ec8e8e255ac88f64302745ca0b73ff94b2b2d48be95b4aaee
+R = fa94fd8b827c06115c1eefd50afc02ce5926ee0e789667783c01c34b
+S = edf766a66973cfc33e4159966c07321a7f6549c3c60e8586ef41402b
+
+Msg = fcb272c828fe8fd3c6f8de9410c7b6e2b36717c1b0e5e359e9109bd7fc378978aa98182a9d99961898ed88999b050d3b64d1457d7a899d6d273b9f4dde2aafa36d76329d62509043c338f265fc4c7d938459b7fa3b230a9f6cb632b61489546bb4181a5ad7f0d7369b8caced48eb374b075b2b325bc86add0f3b680cd9e80acd
+d = 97d747068147c0393a0bb5c159e2c9f1bd538f6204823294883abe28
+Qx = 3858a576eef2ce24d01766997fb81b3f3f78b6104cd188610be221d7
+Qy = 95ffc677ac7bfe3e0bb4cffb17355a964c8356a807151b3cba5d1f4e
+k = c1a2ec1ef16cfd5107c892790daefbed061be78bd8576696b60f64d5
+R = 18c908541843fcdac99b9ff6bb397f3f8094d16b42670216e4eaa2d7
+S = c107a8a508ff57c5d4f78f86cc37e129c864d1c44ed5e73909613b74
+
+[P-224,SHA-512]
+
+Msg = 7522492bdb916a597b8121f3e5c273b1d2800ef8c1db4f7dcbae633b60d7da5193ba53a63d7a377b351897c3b24903ae1cd1994211b259be3e6ae2cbc8970e4957fdf782c7d1bc7a91c80c8ef65468d4ef35428f26e2940ae8b0bd9b8074236bf6c00d0ebe83f9ddb2ade0f835138d39f33b59f244e0037c171f1ba7045a96f5
+d = ba5374541c13597bded6880849184a593d69d3d4f0b1cb4d0919cbd6
+Qx = ac635fe00e8b7a3c8ef5655bdfb7f83e8532e59c0cc0b6534d810ffa
+Qy = 1d067aebeba66e79b28ecfe59ac6fdf5e1970dc3a84499c9d90cd8e2
+k = 187ed1f45c466cbafcd4b9577fb222408c011225dcccfd20f08b8d89
+R = f83d54945997584c923c09662c34cf9ad1e987da8bfd9be600e7a098
+S = 4ff2dba9dba992c98a095b1144a539310e1a570e20c88b7d0aa1955c
+
+Msg = 61097114ff855c3e34a62d9b853f8982d35f29cfa4a89893badbca7849e5fb437a1a38d6451bf0ca5a0d528e352b8e4b57f2ea359a7fc8841d49dd3e570f9b016f14156b0bbc4be822e260bd147ec081454969e11cb0034b7450ef4deb7ed6edb977e2f4ed60121aa095fb0ab40240dc329ecc917f5c64b4410612af065ee9dd
+d = 1e27187134d0a63542adf4665fba22f00cfc7b0a1e02effe913ceedc
+Qx = ecaea8ceea55c3bd418fd34a4ff2499e25e66a104eed846bc00c31d2
+Qy = 3933a356ab1f2dabc303ff0a5d076131e77032e6f502336883bf78a7
+k = 34cb597deae9a3b1cada937abcd247161b19b2b336b20e2e42ae01f1
+R = 58177ba46fb291490b39368774accf72736412c1fb5ee0f27b9b1e02
+S = 58337d78b95a080bfcabb5809bee012501b4da84b8ef310a4628f11c
+
+Msg = dd09ae6c982bb1440ca175a87766fefeacc49393ff797c446200662744f37a6e30c5d33ba70cbd8f12277fd6cc0704c17478bbab2a3047469e9618e3c340a9c8caaff5ce7c8a4d90ecae6a9b84b813419dec14460298e7521c9b7fdb7a2089328005bd51d57f92a1bcbeecd34aa40482b549e006bbf6c4ce66d34a22dda4e0e0
+d = 0905b40e6c29bfcbf55e04266f68f10ca8d3905001d68bb61a27749b
+Qx = d656b73b131aa4c6336a57849ce0d3682b6ab2113d013711e8c29762
+Qy = 6328335ffc2029afbfe2a15cc5636978778c3f9dab84840b05f2e705
+k = dc82840d147f893497a82f023d7d2cbf0a3a5b2ac6cc1b9b23e504be
+R = 583af080e0ec7c1ba5a491a84889b7b7b11ccfe18927c7c219b11757
+S = b23700035349df25d839f0973bef78a7515287de6c83707907074fa6
+
+Msg = 37a73e2774d3b274db426c89b945696daa96035031f72cea01894b24508c7f81961ec254d36ed6a0f448e11cf7950af769dc6cd2c47e52c6caf0ea92c270974f0214b4db436c36a60fb722060a6bb544462a82e1714f5906ec32886f7d59ebf289541c3a00ec1e004892ef2b1286a0194f55d083c6ec92c64b8fd1452e1c68ba
+d = afbaede5d75e4f241dd5b53220f3f5b9c1aa1d5d298e2d43236452dc
+Qx = fe83e59fc8ea8b939355d3258fe53a64d45f63031a0716b7cc416173
+Qy = f151d23060f1c856eb7f1f58be72a7228c3af89e43b56e9695b558c7
+k = 0fbbe7b40136c81a8fb894498d5502157a1cf5a89d0643de92cd38f6
+R = 24f3f457c7b72b7e759d5a8afbf330e31c5d8d2e36f92c0e79c5d87d
+S = 36fd1193def34f12a960740fd79fb38bf2b480726ccad540eb42cdf8
+
+Msg = 9dc2046ffdc6804544db964481abe5d2d276a2a9eeec4c7ad40215b1de23561d402db69bd0f6eec2254711eea4487c64d9a6b62c3ebaf5ffa8db6e7e3a6e17154d126967a47a853a6f8339bdca9be306a13c7f992ded7619b0da59909a49b1e0930360e05b47f18628a36d69b2f87f2bfddd6a5d4a72f84dc76dbdd43f3a6a35
+d = 950b07b0c2b7539a21b5135bfede214733f2e009647d38d8b21d760c
+Qx = f43d13bbfcee3b724063b3910fea49fd591b81e86fdb813b1a492d0c
+Qy = 6b4c8d6fa5dc661889e3cf5ec64997a78222837885f85d2fe9b684fb
+k = 83e110d0d1e700d2f36543028737d2a2f1474aa3b4b28998a39e4793
+R = 2685265bc878e85d10ab13293dec190881a57c4a467f8fc2170432ea
+S = 80a347bb49036522369339bd6485a967cdda818915d8eb947302fcf9
+
+Msg = d9c6847fce688c5e7525a1098b545cb6c15dcd21a02761fc82fc664372a667390680135f91c01a2fa5430c634b1a6d1cd6002d8aa021e7bf5956a7901c2f81bc25d502ba5f55a55f30c0323dc68205cbefec0538e68654e7b327ac1743641896c3e740d8f66f400902b304eafaa4e0d8cffae140536f0922444cc3216a675697
+d = 015bd9f5dfef393b431c3c7fced24385d861ccb563542574a5d2a9bc
+Qx = e868690641e2cda13b289a6c5d2fb175940396044d9cf27b4f2240af
+Qy = 4c78c9abdf2b7fc67ed4497001d7bcf1daca1739dc14a661f91d7c40
+k = e2374350f47c08f3c1359d4edf87e61d1ba4e7dd1540d8d9062efa79
+R = e12dc088d2bc032bb214c77d0e0fb749fc8e61ebe1ed72996f1084b6
+S = 0ab58aa31e0bba5fbc76855e6549f1036fba0a589aeab978ab01b8fb
+
+Msg = 69df8a01b66f04930efd2012ff2243874f256ca8758145d2a9e4ecc84d0dbdbd0dc494ae06db0ccbe819918137c90957114558580d6623efbafdd342b38dad9f08708084d32f874fba04782ce26aaab78de2102ad171f8a8f2b30b5bd3d55fdac5fa3acd6f7def7e61c2533938572b331ba6d1c02bd74bfdbf7337ade8f4a190
+d = 0a3c259df933247445acffb6d8265b601d597fb9997dc2a1eb4deef4
+Qx = e67f4385a9da54253cc371ee9bc6739ae6385a4b87669c7baf0c460d
+Qy = 2bb00b6ddd7b67d9ac5653ec04ca8529fbf16f815c04da3c2e58e82d
+k = 8bf5859665b6a23e6b05a311580f60187ba1c4ae89e44877fb48af66
+R = 653675fb993c3fa9e57b32e33029ec230b966e8077c72c1ec90ddefc
+S = 792723bf87e315147cd4303de7f1dfe95cd7658ebb95c38c1a196140
+
+Msg = 927524982b8d60777c1105c86fac05f634abf58c73f84fb95d81ba0b86e1e43592c4fcad2e395a40fbe7005697d86088e2fb3bb7287eb3f917d4f2dc281f5cbe65d05b4f9623bca849b10a03beca6aa2056a12ebb91cf257ac448c5e9a78f8349a6a29b17c8978bef43a443cbb8a149eb23f794844fc41693f2dbb97181444be
+d = a1c8ef463f9e7e3dd63e677412f87cf9ea4ac9a6a2dae629da5b9916
+Qx = 400e5cd4b315ceb309545cd3277acb70bdae2073fda6ad896ea14b27
+Qy = fbe1d2466cd2e116f38248bd5cabaa6cbe6c4a2694d998abd7b0c991
+k = 82f55a25d3ed6e47c22a6eed0fa52ed0818b87d6ea7950281dfefc09
+R = 16305a46a3f6f9e216ef8f6a6f5f0760d064a885657c864e1c1ea035
+S = 58fd97050bfbca6f87e64e1458c4ad80bae26e280356da344ad3b25d
+
+Msg = 5f9042283561e7f19a436d01c7ef5a950a6d77ede5629cd7e43c0a5d58e8c5673c37945a453291d12938253c71dbe12c8b022ba7276eda6be034ef5ec1ec77dbd1e08f0d7b8e7725b7ec671c075e008a20f77f4ab266f97079b0aa6337df59a33b881954084057b21f294dd14bcb0869a4a6f1f597955ec7bf9d19bb3537a66a
+d = fa511dbf6fef7e5e9c73e4555eb75d435f7884322d9faf5d78cacc0b
+Qx = e8dccd706c31f895f2f261ab979cbab51b8ae28196bcc12a42046380
+Qy = ec246be8e71ea3859cb717a59990fe22e4b76858ff49becd70739a01
+k = a37d665fe4314aa4cd03eb8e6a1f366b43e11fdb419c96b48f787b62
+R = 05e4909bcc172ab4140be291aad4660e375032bce2d762b6269ba764
+S = e347a1c9d3670690e1d8d1d4cd9579848f442199c10526488da5cebf
+
+Msg = c2ae5573d3bf396523bfb703db8502fd0760cd1be528f6ddbfb95aad399e0b19f3bd9e0fabdb05d49e3f893dffec5b627c9c2f7ad5f32e92e4e27a38cb5c28657657377fdfa1b66cd7ac3d15c6d49df92d284db99f69744f37dc7cb4e7d52920fdb200a7942623a7057ba82e467dcccaa5da416b48510d8364446a6a5e2a5aa8
+d = a58bd53646400a646f0e4208320dc679a9664d1c6bfb27fdc8eac7ea
+Qx = e22e0dc4ecd96eb0071b72ba4b4988bf784f3fe73cb81bfb93d9ac4f
+Qy = b3e213e518bee1367a4fb3703b9008bac9d95a1fc4aa61225fff9f3c
+k = 42c5b6f87d3bb1ed74f5ee8398d8f8c61e9e50ffa7a1da12d39893f9
+R = 5c0e5c6f057de1e99ef5d237a60d7a07fa9a42b120a82f573d9fb7b2
+S = 2fffc0bf550bd2f650fed085a84501cacfa6a1bb984df1f9237eaa59
+
+Msg = 03c1a1cd30a039d0dcb22fee2450a7fa79495a0d0f4f43d2de4d75bce003c0334a8860f5c164dbd94888a9f751235a3e570d31070e3e1293a7be616af7176600585d36ac013600157d2569d491da4b8a3bf3630c26e0b9925412189f50b0ae6f04c86477932e2ecd8c3546106ae1ebc684cc3adb27ed665eddece886adea4ce3
+d = 64bd4452b572cc95510ac2e572f41136299ff17f6e8448f4ffb571d0
+Qx = 92521fa25c2e034d127e0921efdb167f0b2ff8b20504487ed87fa264
+Qy = e72c770e37375ad7dc2c4e63e5701826f6606f6ffb9461ee61b4e872
+k = eaf76ee4d7e00d13d8a6d03dffd07ad9a8bb6dc8176c9f93059b1b7f
+R = cf5058e2a6cf5e61a138b013eb292f38a1b9f07239ae5941dbce8919
+S = d14198621650d985d270bc997da6e78588fd0ef843b874c66a3de3c3
+
+Msg = 888f6d9bc7c86c0079fbfd42d8c08d6958f40f6e570fb0b1f03d2f8f8a63df4fcc87b379a222cf835820a999d34996e08961f13b86b075e7fd1c303cd3baa44de42168561589012f7e5300da4f8bdf470c07119a5d9f7ba7293568cd7c6a1b7fc1e41cda40bed7d46e5a28af67ae2aabfefe67a86a1c601e6f5ee543e09bd7b6
+d = 7f3edb710df9d982f486233d0c176aa88f5a0ee81efa9b8145020294
+Qx = e7611e013e7b43ff5b8b57ad83333bffcc9e469ad23070b5791dc594
+Qy = 7784da0a11dbe16208c6e0b6d5029e71fbec4dffc9fa046d3eeb71c9
+k = 94db7ef9a232593091eb9a74f289529c7e0d7fef21f80b3c8556b75e
+R = a971f45bab10b1d16d7234ca8e4ec987da20d9e867f28aa063296e23
+S = e38c538d65a7e1a28fd3ec53f015a7e5beb60e9d309f1e3ba4b2c3d2
+
+Msg = 48453340f1317769e6ee6e103153714365731163dc18f84e9f2fa4b120f9c5a9645ee2f9b66c84c26d95912b422b009b64af96aa418b2427a4209f2e7513ba8e43ec8cf20b34e7529b22eb1199545afe9a9f7d9bcb320aec9ee0162f91c0d1dd9674c9c284f25199c5e109f6f84d7ed0d269cc6413edb81bc2c83e37d644d8b9
+d = b569f8296ff1d9cc01fffd9919016e5730c1858bdb7b99527153751a
+Qx = 242f34959516a4706172f7dede23110efa314bff22eb320ab88feeff
+Qy = 45e3227710900a8acfc9bcce728119d042f64ca40876c2b380ee46e0
+k = ae61523866a8f43e6cdd42ba27a34ed06527e8a5842901a64c393f76
+R = c2732a4e0815f9f785500e80147e9486994446beccf8a6a352b97585
+S = 6ecaece6487d7920e398f7f951ab7c7aba5832dabf03704106ad1244
+
+Msg = 4bdfd3b91d83108409ad765b256e0c9b9937ecf647f8e6f9fc807e2e72af8246178b3fe046b4ea10170450d71a4eec790ecb05f03d7077341de26c4db7eeae24d55c9a9093e837dfdb38168fe8230cb9605825a1282fecd741989bfcdb34678fe077477927f66bd26d003e5dda22043341a14dd31841ba483ad5ce2701e0f68e
+d = 41a4dd8eee39232b728516e2f21e66011e7426a6b25986c3ffa237e4
+Qx = c32988171caab178bf50dc7310bc7f604df5a9d19a8e602519c72d8a
+Qy = f8985d112ad9de05969e5364d943c1cc5cd198359f4c62b19da0e117
+k = 827d4999da81fa920c8492ccc1e2d5cdafed9754cf7382a859952071
+R = 89c61da7422ccd676baec07e2185c12e947a2374eede87847304be6c
+S = 2685379624717ea28422e8d001c090405a130b4ef9f1ac726c3ca502
+
+Msg = e6cdee8558bc1eacc24e82f0624ce8d02cc8d925b4dd3dec3a72f4a4e0fb76076bfa3ef2e2c33bdd7c27b322bdc09bbfee8fe46f75dbd7bbd2af09690b7137943efe21706e0a1b6d3089540fc58d85ddb55ea836616db573e36c521be008893f40a0a7c349602cc178ea43be59d31ec6449e7ff2c5379379f7d7645134df1bc3
+d = 67fa50569257c8cc89ac0325db4902003a62f30b917f53e4035a7e04
+Qx = 6773a0436a9c42635730413b19aa4166f08c69c0e5002953da42253b
+Qy = 555138290b093bf2fe79acda9131d920cd1e7ac43fb8775776cd713c
+k = 557cb45fd3a30b3bdbf08c56eabbd4478736024aaa52bf8448096453
+R = 8e92cf7a674aa5f7542dd95c695589a05747431692edd04804299b8f
+S = af4908b41f8180b71a6ff10fd51f3d143147af6ddddf7534d3284ed9
+
+
+[P-256,SHA-224]
+
+Msg = ff624d0ba02c7b6370c1622eec3fa2186ea681d1659e0a845448e777b75a8e77a77bb26e5733179d58ef9bc8a4e8b6971aef2539f77ab0963a3415bbd6258339bd1bf55de65db520c63f5b8eab3d55debd05e9494212170f5d65b3286b8b668705b1e2b2b5568610617abb51d2dd0cb450ef59df4b907da90cfa7b268de8c4c2
+d = 708309a7449e156b0db70e5b52e606c7e094ed676ce8953bf6c14757c826f590
+Qx = 29578c7ab6ce0d11493c95d5ea05d299d536801ca9cbd50e9924e43b733b83ab
+Qy = 08c8049879c6278b2273348474158515accaa38344106ef96803c5a05adc4800
+k = 58f741771620bdc428e91a32d86d230873e9140336fcfb1e122892ee1d501bdc
+R = 4a19274429e40522234b8785dc25fc524f179dcc95ff09b3c9770fc71f54ca0d
+S = 58982b79a65b7320f5b92d13bdaecdd1259e760f0f718ba933fd098f6f75d4b7
+
+Msg = 9155e91fd9155eeed15afd83487ea1a3af04c5998b77c0fe8c43dcc479440a8a9a89efe883d9385cb9edfde10b43bce61fb63669935ad39419cf29ef3a936931733bfc2378e253e73b7ae9a3ec7a6a7932ab10f1e5b94d05160c053988f3bdc9167155d069337d42c9a7056619efc031fa5ec7310d29bd28980b1e3559757578
+d = 90c5386100b137a75b0bb495002b28697a451add2f1f22cb65f735e8aaeace98
+Qx = 4a92396ff7930b1da9a873a479a28a9896af6cc3d39345b949b726dc3cd978b5
+Qy = 475abb18eaed948879b9c1453e3ef2755dd90f77519ec7b6a30297aad08e4931
+k = 36f853b5c54b1ec61588c9c6137eb56e7a708f09c57513093e4ecf6d739900e5
+R = 38b29558511061cfabdc8e5bb65ac2976d1aa2ba9a5deab8074097b2172bb9ad
+S = 0de2cde610502b6e03c0b23602eafbcd3faf886c81d111d156b7aa550f5bcd51
+
+Msg = b242a7586a1383368a33c88264889adfa3be45422fbef4a2df4e3c5325a9c7757017e0d5cf4bbf4de7f99d189f81f1fd2f0dd645574d1eb0d547eead9375677819297c1abe62526ae29fc54cdd11bfe17714f2fbd2d0d0e8d297ff98535980482dd5c1ebdc5a7274aabf1382c9f2315ca61391e3943856e4c5e616c2f1f7be0d
+d = a3a43cece9c1abeff81099fb344d01f7d8df66447b95a667ee368f924bccf870
+Qx = 5775174deb0248112e069cb86f1546ac7a78bc2127d0cb953bad46384dd6be5b
+Qy = a27020952971cc0b0c3abd06e9ca3e141a4943f560564eba31e5288928bc7ce7
+k = a0d9a7a245bd9b9aa86cecb89341c9de2e4f9b5d095a8150826c7ba7fb3e7df7
+R = b02a440add66a9ff9c3c0e9acf1be678f6bd48a10cbdec2ad6d186ffe05f3f2a
+S = a98bea42aec56a1fcecec00a1cc69b01fcbcf5de7ac1b2f2dcc09b6db064f92b
+
+Msg = b64005da76b24715880af94dba379acc25a047b06066c9bedc8f17b8c74e74f4fc720d9f4ef0e2a659e0756931c080587ebdcd0f85e819aea6dacb327a9d96496da53ea21aef3b2e793a9c0def5196acec99891f46ead78a85bc7ab644765781d3543da9fbf9fec916dca975ef3b4271e50ecc68bf79b2d8935e2b25fc063358
+d = 7bbc8ff13f6f921f21e949b224c16b7176c5984d312b671cf6c2e4841135fc7f
+Qx = f888e913ec6f3cd8b31eb89e4f8aaa8887d30ae5348ed7118696949d5b8cc7c1
+Qy = 08895d09620500d244e5035e262dea3f2867cd8967b226324d5c05220d8b410c
+k = 21c942f3b487accbf7fadc1c4b7a6c7567ce876c195022459fa1ebf6d04ffbaa
+R = 2e6cc883b8acc904ee9691ef4a9f1f5a9e5fbfde847cda3be833f949fb9c7182
+S = 2ac48f7a930912131a8b4e3ab495307817c465d638c2a9ea5ae9e2808806e20a
+
+Msg = fe6e1ea477640655eaa1f6e3352d4bce53eb3d95424df7f238e93d8531da8f36bc35fa6be4bf5a6a382e06e855139eb617a9cc9376b4dafacbd80876343b12628619d7cbe1bff6757e3706111ed53898c0219823adbc044eaf8c6ad449df8f6aab9d444dadb5c3380eec0d91694df5fc4b30280d4b87d27e67ae58a1df828963
+d = daf5ec7a4eebc20d9485796c355b4a65ad254fe19b998d0507e91ea24135f45d
+Qx = 137c465085c1b1b8cccbe9fccbe9d0295a331aaf332f3ed2e285d16e574b943b
+Qy = d3e8d5a24cd218c19760b0e85b35a8569945aa857cbf0fd6a3ce127581b217b6
+k = 343251dffa56e6a612fec7b078f9c3819eab402a72686b894a47a08fd97e6c23
+R = 775e25a296bd259510ae9375f548997bec8a744900022945281dc8c4d94f2b5b
+S = d87592ceab773ae103daebbb56a04144aaccb1e14efc1024dc36c0e382df1f70
+
+Msg = 907c0c00dc080a688548957b5b8b1f33ba378de1368023dcad43242411f554eb7d392d3e5c1668fad3944ff9634105343d83b8c85d2a988da5f5dc60ee0518327caed6dd5cf4e9bc6222deb46d00abde745f9b71d6e7aee6c7fdfc9ed053f2c0b611d4c6863088bd012ea9810ee94f8e58905970ebd07353f1f409a371ed03e3
+d = 8729a8396f262dabd991aa404cc1753581cea405f0d19222a0b3f210de8ee3c5
+Qx = 82b1f1a7af9b48ca8452613d7032beb0e4f28fe710306aeccc959e4d03662a35
+Qy = 5e39f33574097b8d32b471a591972496f5d44db344c037d13f06fafc75f016fd
+k = 6de9e21f0b2cacc1762b3558fd44d3cf156b85dbef430dd28d59713bfb9cfa0b
+R = a754b42720e71925d51fcef76151405a3696cc8f9fc9ca7b46d0b16edd7fb699
+S = 603924780439cc16ac4cf97c2c3065bc95353aa9179d0ab5f0322ca82f851cf2
+
+Msg = 771c4d7bce05610a3e71b272096b57f0d1efcce33a1cb4f714d6ebc0865b2773ec5eedc25fae81dee1d256474dbd9676623614c150916e6ed92ce4430b26037d28fa5252ef6b10c09dc2f7ee5a36a1ea7897b69f389d9f5075e271d92f4eb97b148f3abcb1e5be0b4feb8278613d18abf6da60bfe448238aa04d7f11b71f44c5
+d = f1b62413935fc589ad2280f6892599ad994dae8ca3655ed4f7318cc89b61aa96
+Qx = e0bbfe4016eea93e6f509518cbffc25d492de6ebbf80465a461caa5bdc018159
+Qy = 3231ee7a119d84fa56e3034d50fea85929aec2eb437abc7646821e1bf805fb50
+k = 7a33eeb9f469afd55de2fb786847a1d3e7797929305c0f90d953b6f143bb8fc6
+R = 96d1c9399948254ea381631fc0f43ea808110506db8aacf081df5535ac5eb8ad
+S = 73bf3691260dddd9997c97313f2a70783eacf8d15bdfb34bb13025cdfae72f70
+
+Msg = a3b2825235718fc679b942e8ac38fb4f54415a213c65875b5453d18ca012320ddfbbc58b991eaebadfc2d1a28d4f0cd82652b12e4d5bfda89eda3be12ac52188e38e8cce32a264a300c0e463631f525ae501348594f980392c76b4a12ddc88e5ca086cb8685d03895919a8627725a3e00c4728e2b7c6f6a14fc342b2937fc3dd
+d = 4caaa26f93f009682bbba6db6b265aec17b7ec1542bda458e8550b9e68eed18d
+Qx = e3c58c1c254d11c7e781ad133e4c36dd1b5de362120d336a58e7b68813f3fbee
+Qy = 59760db66120afe0d962c81a8e5586588fd19de2f40556371611c73af22c8a68
+k = c0d37142dc8b0d614fad20c4d35af6eb819e259e513ddeac1e1c273e7e1dc1bb
+R = 25dd8e4086c62a40d2a310e2f90f6af5cb7e677b4dfdb4dc4e99e23ea2f0e6dc
+S = 90ad62c179b0c9d61f521dde1cd762bfd224b5525c39c3706f2549313ddb4f39
+
+Msg = 3e6e2a9bffd729ee5d4807849cd4250021d8184cda723df6ab0e5c939d39237c8e58af9d869fe62d3c97b3298a99e891e5e11aa68b11a087573a40a3e83c7965e7910d72f81cad0f42accc5c25a4fd3cdd8cee63757bbbfbdae98be2bc867d3bcb1333c4632cb0a55dffeb77d8b119c466cd889ec468454fabe6fbee7102deaf
+d = 7af4b150bb7167cb68037f280d0823ce5320c01a92b1b56ee1b88547481b1de9
+Qx = cb3634ec4f0cbb99986be788f889e586026d5a851e80d15382f1bdb1bda2bc75
+Qy = 51e4e43bc16fb114896b18198a1aebe6054ba20ed0c0317c1b8776158c0e6bfb
+k = 98edd59fafbcaee5f64e84eb5ed59fff45d14aabada47cee2fa674377173627a
+R = 261a1cdb0fd93c0fb06ea6068b6b03c330a12f621a7eba76682a1d152c0e8d08
+S = 7ca049bad54feee101d6db807635ffb8bdb05a38e445c8c3d65d60df143514c5
+
+Msg = 52e5c308e70329a17c71eaedb66bbee303c8ec48a6f1a2efb235d308563cd58553d434e12f353227a9ea28608ec9c820ed83c95124e7a886f7e832a2de1032e78dc059208f9ec354170b2b1cab992b52ac01e6c0e4e1b0112686962edc53ab226dafcc9fc7baed2cd9307160e8572edb125935db49289b178f35a8ad23f4f801
+d = 52ad53e849e30bec0e6345c3e9d98ebc808b19496c1ef16d72ab4a00bbb8c634
+Qx = 7cca1334bfc2a78728c50b370399be3f9690d445aa03c701da643eeb0b0f7fa8
+Qy = 3f7522238668e615405e49b2f63faee58286000a30cdb4b564ac0df99bc8950f
+k = 8650c30712fc253610884fbba4a332a4574d4b7822f7776cab1df8f5fa05442a
+R = a18194c7ac5829afc408d78dde19542837e7be82706c3941b2d9c5e036bb51e0
+S = 188ead1cdf7c1d21114ff56d0421ffd501ab978ef58337462c0fa736d86299af
+
+Msg = d3e9e82051d4c84d699453c9ff44c7c09f6523bb92232bcf30bf3c380224249de2964e871d56a364d6955c81ef91d06482a6c7c61bc70f66ef22fad128d15416e7174312619134f968f1009f92cbf99248932efb533ff113fb6d949e21d6b80dfbbe69010c8d1ccb0f3808ea309bb0bac1a222168c95b088847e613749b19d04
+d = 80754962a864be1803bc441fa331e126005bfc6d8b09ed38b7e69d9a030a5d27
+Qx = 0aaeed6dd1ae020d6eefc98ec4241ac93cbd3c8afed05bb28007e7da5727571b
+Qy = 2dda1d5b7872eb94dfffb456115037ff8d3e72f8ebdd8fcfc42391f96809be69
+k = 738e050aeefe54ecba5be5f93a97bbcb7557d701f9da2d7e88483454b97b55a8
+R = 8cb9f41dfdcb9604e0725ac9b78fc0db916dc071186ee982f6dba3da36f02efa
+S = 5c87fe868fd4282fb114f5d70e9590a10a5d35cedf3ff6402ba5c4344738a32e
+
+Msg = 968951c2c1918436fe19fa2fe2152656a08f9a6b8aa6201920f1b424da98cee71928897ff087620cc5c551320b1e75a1e98d7d98a5bd5361c9393759614a6087cc0f7fb01fcb173783eb4c4c23961a8231ac4a07d72e683b0c1bd4c51ef1b031df875e7b8d5a6e0628949f5b8f157f43dccaea3b2a4fc11181e6b451e06ceb37
+d = cfa8c8bd810eb0d73585f36280ecdd296ee098511be8ad5eac68984eca8eb19d
+Qx = c227a2af15dfa8734e11c0c50f77e24e77ed58dd8cccf1b0e9fa06bee1c64766
+Qy = b686592ce3745eb300d2704083db55e1fa8274e4cb7e256889ccc0bb34a60570
+k = 2d6b449bb38b543d6b6d34ff8cb053f5e5b337f949b069b21f421995ebb28823
+R = 5e89d3c9b103c2fa3cb8cebeec23640acda0257d63ffbe2d509bfc49fab1dca6
+S = d70c5b1eeb29e016af9925798d24e166c23d58fedd2f1a3bbdb1ef78cdbfb63a
+
+Msg = 78048628932e1c1cdd1e70932bd7b76f704ba08d7e7d825d3de763bf1a062315f4af16eccefe0b6ebadccaf403d013f50833ce2c54e24eea8345e25f93b69bb048988d102240225ceacf5003e2abdcc90299f4bf2c101585d36ecdd7a155953c674789d070480d1ef47cc7858e97a6d87c41c6922a00ea12539f251826e141b4
+d = b2021e2665ce543b7feadd0cd5a4bd57ffcc5b32deb860b4d736d9880855da3c
+Qx = 722e0abad4504b7832a148746153777694714eca220eced2b2156ca64cfed3dd
+Qy = f0351b357b3081e859c46cad5328c5afa10546e92bc6c3fd541796ac30397a75
+k = b15bbce4b382145de7ecd670d947e77555ef7cd1693bd53c694e2b52b04d10e1
+R = 9d086dcd22da165a43091991bede9c1c14515e656633cb759ec2c17f51c35253
+S = 23595ad1cb714559faaecaf946beb9a71e584616030ceaed8a8470f4bf62768f
+
+Msg = 9b0800c443e693067591737fdbcf0966fdfa50872d41d0c189d87cbc34c2771ee5e1255fd604f09fcf167fda16437c245d299147299c69046895d22482db29aba37ff57f756716cd3d6223077f747c4caffbecc0a7c9dfaaafd9a9817470ded8777e6355838ac54d11b2f0fc3f43668ff949cc31de0c2d15af5ef17884e4d66a
+d = 0c9bce6a568ca239395fc3552755575cbcdddb1d89f6f5ab354517a057b17b48
+Qx = 4814d454495df7103e2da383aba55f7842fd84f1750ee5801ad32c10d0be6c7d
+Qy = a0bd039d5097c8f0770477f6b18d247876e88e528bf0453eab515ffab8a9eda3
+k = d414f1525cdcc41eba1652de017c034ebcc7946cb2efe4713d09f67c85b83153
+R = 84db02c678f9a21208cec8564d145a35ba8c6f26b4eb7e19522e439720dae44c
+S = 537c564da0d2dc5ac4376c5f0ca3b628d01d48df47a83d842c927e4d6db1e16d
+
+Msg = fc3b8291c172dae635a6859f525beaf01cf683765d7c86f1a4d768df7cae055f639eccc08d7a0272394d949f82d5e12d69c08e2483e11a1d28a4c61f18193106e12e5de4a9d0b4bf341e2acd6b715dc83ae5ff63328f8346f35521ca378b311299947f63ec593a5e32e6bd11ec4edb0e75302a9f54d21226d23314729e061016
+d = 1daa385ec7c7f8a09adfcaea42801a4de4c889fb5c6eb4e92bc611d596d68e3f
+Qx = f04e9f2831d9697ae146c7d4552e5f91085cc46778400b75b76f00205252941d
+Qy = bd267148174cd0c2b019cd0a5256e2f3f889d1e597160372b5a1339c8d787f10
+k = 7707db348ee6f60365b43a2a994e9b40ed56fe03c2c31c7e781bc4ffadcba760
+R = 5d95c385eeba0f15db0b80ae151912409128c9c80e554246067b8f6a36d85ea5
+S = db5d8a1e345f883e4fcb3871276f170b783c1a1e9da6b6615913368a8526f1c3
+
+[P-256,SHA-256]
+
+Msg = 5905238877c77421f73e43ee3da6f2d9e2ccad5fc942dcec0cbd25482935faaf416983fe165b1a045ee2bcd2e6dca3bdf46c4310a7461f9a37960ca672d3feb5473e253605fb1ddfd28065b53cb5858a8ad28175bf9bd386a5e471ea7a65c17cc934a9d791e91491eb3754d03799790fe2d308d16146d5c9b0d0debd97d79ce8
+d = 519b423d715f8b581f4fa8ee59f4771a5b44c8130b4e3eacca54a56dda72b464
+Qx = 1ccbe91c075fc7f4f033bfa248db8fccd3565de94bbfb12f3c59ff46c271bf83
+Qy = ce4014c68811f9a21a1fdb2c0e6113e06db7ca93b7404e78dc7ccd5ca89a4ca9
+k = 94a1bbb14b906a61a280f245f9e93c7f3b4a6247824f5d33b9670787642a68de
+R = f3ac8061b514795b8843e3d6629527ed2afd6b1f6a555a7acabb5e6f79c8c2ac
+S = 8bf77819ca05a6b2786c76262bf7371cef97b218e96f175a3ccdda2acc058903
+
+Msg = c35e2f092553c55772926bdbe87c9796827d17024dbb9233a545366e2e5987dd344deb72df987144b8c6c43bc41b654b94cc856e16b96d7a821c8ec039b503e3d86728c494a967d83011a0e090b5d54cd47f4e366c0912bc808fbb2ea96efac88fb3ebec9342738e225f7c7c2b011ce375b56621a20642b4d36e060db4524af1
+d = 0f56db78ca460b055c500064824bed999a25aaf48ebb519ac201537b85479813
+Qx = e266ddfdc12668db30d4ca3e8f7749432c416044f2d2b8c10bf3d4012aeffa8a
+Qy = bfa86404a2e9ffe67d47c587ef7a97a7f456b863b4d02cfc6928973ab5b1cb39
+k = 6d3e71882c3b83b156bb14e0ab184aa9fb728068d3ae9fac421187ae0b2f34c6
+R = 976d3a4e9d23326dc0baa9fa560b7c4e53f42864f508483a6473b6a11079b2db
+S = 1b766e9ceb71ba6c01dcd46e0af462cd4cfa652ae5017d4555b8eeefe36e1932
+
+Msg = 3c054e333a94259c36af09ab5b4ff9beb3492f8d5b4282d16801daccb29f70fe61a0b37ffef5c04cd1b70e85b1f549a1c4dc672985e50f43ea037efa9964f096b5f62f7ffdf8d6bfb2cc859558f5a393cb949dbd48f269343b5263dcdb9c556eca074f2e98e6d94c2c29a677afaf806edf79b15a3fcd46e7067b7669f83188ee
+d = e283871239837e13b95f789e6e1af63bf61c918c992e62bca040d64cad1fc2ef
+Qx = 74ccd8a62fba0e667c50929a53f78c21b8ff0c3c737b0b40b1750b2302b0bde8
+Qy = 29074e21f3a0ef88b9efdf10d06aa4c295cc1671f758ca0e4cd108803d0f2614
+k = ad5e887eb2b380b8d8280ad6e5ff8a60f4d26243e0124c2f31a297b5d0835de2
+R = 35fb60f5ca0f3ca08542fb3cc641c8263a2cab7a90ee6a5e1583fac2bb6f6bd1
+S = ee59d81bc9db1055cc0ed97b159d8784af04e98511d0a9a407b99bb292572e96
+
+Msg = 0989122410d522af64ceb07da2c865219046b4c3d9d99b01278c07ff63eaf1039cb787ae9e2dd46436cc0415f280c562bebb83a23e639e476a02ec8cff7ea06cd12c86dcc3adefbf1a9e9a9b6646c7599ec631b0da9a60debeb9b3e19324977f3b4f36892c8a38671c8e1cc8e50fcd50f9e51deaf98272f9266fc702e4e57c30
+d = a3d2d3b7596f6592ce98b4bfe10d41837f10027a90d7bb75349490018cf72d07
+Qx = 322f80371bf6e044bc49391d97c1714ab87f990b949bc178cb7c43b7c22d89e1
+Qy = 3c15d54a5cc6b9f09de8457e873eb3deb1fceb54b0b295da6050294fae7fd999
+k = 24fc90e1da13f17ef9fe84cc96b9471ed1aaac17e3a4bae33a115df4e5834f18
+R = d7c562370af617b581c84a2468cc8bd50bb1cbf322de41b7887ce07c0e5884ca
+S = b46d9f2d8c4bf83546ff178f1d78937c008d64e8ecc5cbb825cb21d94d670d89
+
+Msg = dc66e39f9bbfd9865318531ffe9207f934fa615a5b285708a5e9c46b7775150e818d7f24d2a123df3672fff2094e3fd3df6fbe259e3989dd5edfcccbe7d45e26a775a5c4329a084f057c42c13f3248e3fd6f0c76678f890f513c32292dd306eaa84a59abe34b16cb5e38d0e885525d10336ca443e1682aa04a7af832b0eee4e7
+d = 53a0e8a8fe93db01e7ae94e1a9882a102ebd079b3a535827d583626c272d280d
+Qx = 1bcec4570e1ec2436596b8ded58f60c3b1ebc6a403bc5543040ba82963057244
+Qy = 8af62a4c683f096b28558320737bf83b9959a46ad2521004ef74cf85e67494e1
+k = 5d833e8d24cc7a402d7ee7ec852a3587cddeb48358cea71b0bedb8fabe84e0c4
+R = 18caaf7b663507a8bcd992b836dec9dc5703c080af5e51dfa3a9a7c387182604
+S = 77c68928ac3b88d985fb43fb615fb7ff45c18ba5c81af796c613dfa98352d29c
+
+Msg = 600974e7d8c5508e2c1aab0783ad0d7c4494ab2b4da265c2fe496421c4df238b0be25f25659157c8a225fb03953607f7df996acfd402f147e37aee2f1693e3bf1c35eab3ae360a2bd91d04622ea47f83d863d2dfecb618e8b8bdc39e17d15d672eee03bb4ce2cc5cf6b217e5faf3f336fdd87d972d3a8b8a593ba85955cc9d71
+d = 4af107e8e2194c830ffb712a65511bc9186a133007855b49ab4b3833aefc4a1d
+Qx = a32e50be3dae2c8ba3f5e4bdae14cf7645420d425ead94036c22dd6c4fc59e00
+Qy = d623bf641160c289d6742c6257ae6ba574446dd1d0e74db3aaa80900b78d4ae9
+k = e18f96f84dfa2fd3cdfaec9159d4c338cd54ad314134f0b31e20591fc238d0ab
+R = 8524c5024e2d9a73bde8c72d9129f57873bbad0ed05215a372a84fdbc78f2e68
+S = d18c2caf3b1072f87064ec5e8953f51301cada03469c640244760328eb5a05cb
+
+Msg = dfa6cb9b39adda6c74cc8b2a8b53a12c499ab9dee01b4123642b4f11af336a91a5c9ce0520eb2395a6190ecbf6169c4cba81941de8e76c9c908eb843b98ce95e0da29c5d4388040264e05e07030a577cc5d176387154eabae2af52a83e85c61c7c61da930c9b19e45d7e34c8516dc3c238fddd6e450a77455d534c48a152010b
+d = 78dfaa09f1076850b3e206e477494cddcfb822aaa0128475053592c48ebaf4ab
+Qx = 8bcfe2a721ca6d753968f564ec4315be4857e28bef1908f61a366b1f03c97479
+Qy = 0f67576a30b8e20d4232d8530b52fb4c89cbc589ede291e499ddd15fe870ab96
+k = 295544dbb2da3da170741c9b2c6551d40af7ed4e891445f11a02b66a5c258a77
+R = c5a186d72df452015480f7f338970bfe825087f05c0088d95305f87aacc9b254
+S = 84a58f9e9d9e735344b316b1aa1ab5185665b85147dc82d92e969d7bee31ca30
+
+Msg = 51d2547cbff92431174aa7fc7302139519d98071c755ff1c92e4694b58587ea560f72f32fc6dd4dee7d22bb7387381d0256e2862d0644cdf2c277c5d740fa089830eb52bf79d1e75b8596ecf0ea58a0b9df61e0c9754bfcd62efab6ea1bd216bf181c5593da79f10135a9bc6e164f1854bc8859734341aad237ba29a81a3fc8b
+d = 80e692e3eb9fcd8c7d44e7de9f7a5952686407f90025a1d87e52c7096a62618a
+Qx = a88bc8430279c8c0400a77d751f26c0abc93e5de4ad9a4166357952fe041e767
+Qy = 2d365a1eef25ead579cc9a069b6abc1b16b81c35f18785ce26a10ba6d1381185
+k = 7c80fd66d62cc076cef2d030c17c0a69c99611549cb32c4ff662475adbe84b22
+R = 9d0c6afb6df3bced455b459cc21387e14929392664bb8741a3693a1795ca6902
+S = d7f9ddd191f1f412869429209ee3814c75c72fa46a9cccf804a2f5cc0b7e739f
+
+Msg = 558c2ac13026402bad4a0a83ebc9468e50f7ffab06d6f981e5db1d082098065bcff6f21a7a74558b1e8612914b8b5a0aa28ed5b574c36ac4ea5868432a62bb8ef0695d27c1e3ceaf75c7b251c65ddb268696f07c16d2767973d85beb443f211e6445e7fe5d46f0dce70d58a4cd9fe70688c035688ea8c6baec65a5fc7e2c93e8
+d = 5e666c0db0214c3b627a8e48541cc84a8b6fd15f300da4dff5d18aec6c55b881
+Qx = 1bc487570f040dc94196c9befe8ab2b6de77208b1f38bdaae28f9645c4d2bc3a
+Qy = ec81602abd8345e71867c8210313737865b8aa186851e1b48eaca140320f5d8f
+k = 2e7625a48874d86c9e467f890aaa7cd6ebdf71c0102bfdcfa24565d6af3fdce9
+R = 2f9e2b4e9f747c657f705bffd124ee178bbc5391c86d056717b140c153570fd9
+S = f5413bfd85949da8d83de83ab0d19b2986613e224d1901d76919de23ccd03199
+
+Msg = 4d55c99ef6bd54621662c3d110c3cb627c03d6311393b264ab97b90a4b15214a5593ba2510a53d63fb34be251facb697c973e11b665cb7920f1684b0031b4dd370cb927ca7168b0bf8ad285e05e9e31e34bc24024739fdc10b78586f29eff94412034e3b606ed850ec2c1900e8e68151fc4aee5adebb066eb6da4eaa5681378e
+d = f73f455271c877c4d5334627e37c278f68d143014b0a05aa62f308b2101c5308
+Qx = b8188bd68701fc396dab53125d4d28ea33a91daf6d21485f4770f6ea8c565dde
+Qy = 423f058810f277f8fe076f6db56e9285a1bf2c2a1dae145095edd9c04970bc4a
+k = 62f8665fd6e26b3fa069e85281777a9b1f0dfd2c0b9f54a086d0c109ff9fd615
+R = 1cc628533d0004b2b20e7f4baad0b8bb5e0673db159bbccf92491aef61fc9620
+S = 880e0bbf82a8cf818ed46ba03cf0fc6c898e36fca36cc7fdb1d2db7503634430
+
+Msg = f8248ad47d97c18c984f1f5c10950dc1404713c56b6ea397e01e6dd925e903b4fadfe2c9e877169e71ce3c7fe5ce70ee4255d9cdc26f6943bf48687874de64f6cf30a012512e787b88059bbf561162bdcc23a3742c835ac144cc14167b1bd6727e940540a9c99f3cbb41fb1dcb00d76dda04995847c657f4c19d303eb09eb48a
+d = b20d705d9bd7c2b8dc60393a5357f632990e599a0975573ac67fd89b49187906
+Qx = 51f99d2d52d4a6e734484a018b7ca2f895c2929b6754a3a03224d07ae61166ce
+Qy = 4737da963c6ef7247fb88d19f9b0c667cac7fe12837fdab88c66f10d3c14cad1
+k = 72b656f6b35b9ccbc712c9f1f3b1a14cbbebaec41c4bca8da18f492a062d6f6f
+R = 9886ae46c1415c3bc959e82b760ad760aab66885a84e620aa339fdf102465c42
+S = 2bf3a80bc04faa35ebecc0f4864ac02d349f6f126e0f988501b8d3075409a26c
+
+Msg = 3b6ee2425940b3d240d35b97b6dcd61ed3423d8e71a0ada35d47b322d17b35ea0472f35edd1d252f87b8b65ef4b716669fc9ac28b00d34a9d66ad118c9d94e7f46d0b4f6c2b2d339fd6bcd351241a387cc82609057048c12c4ec3d85c661975c45b300cb96930d89370a327c98b67defaa89497aa8ef994c77f1130f752f94a4
+d = d4234bebfbc821050341a37e1240efe5e33763cbbb2ef76a1c79e24724e5a5e7
+Qx = 8fb287f0202ad57ae841aea35f29b2e1d53e196d0ddd9aec24813d64c0922fb7
+Qy = 1f6daff1aa2dd2d6d3741623eecb5e7b612997a1039aab2e5cf2de969cfea573
+k = d926fe10f1bfd9855610f4f5a3d666b1a149344057e35537373372ead8b1a778
+R = 490efd106be11fc365c7467eb89b8d39e15d65175356775deab211163c2504cb
+S = 644300fc0da4d40fb8c6ead510d14f0bd4e1321a469e9c0a581464c7186b7aa7
+
+Msg = c5204b81ec0a4df5b7e9fda3dc245f98082ae7f4efe81998dcaa286bd4507ca840a53d21b01e904f55e38f78c3757d5a5a4a44b1d5d4e480be3afb5b394a5d2840af42b1b4083d40afbfe22d702f370d32dbfd392e128ea4724d66a3701da41ae2f03bb4d91bb946c7969404cb544f71eb7a49eb4c4ec55799bda1eb545143a7
+d = b58f5211dff440626bb56d0ad483193d606cf21f36d9830543327292f4d25d8c
+Qx = 68229b48c2fe19d3db034e4c15077eb7471a66031f28a980821873915298ba76
+Qy = 303e8ee3742a893f78b810991da697083dd8f11128c47651c27a56740a80c24c
+k = e158bf4a2d19a99149d9cdb879294ccb7aaeae03d75ddd616ef8ae51a6dc1071
+R = e67a9717ccf96841489d6541f4f6adb12d17b59a6bef847b6183b8fcf16a32eb
+S = 9ae6ba6d637706849a6a9fc388cf0232d85c26ea0d1fe7437adb48de58364333
+
+Msg = 72e81fe221fb402148d8b7ab03549f1180bcc03d41ca59d7653801f0ba853add1f6d29edd7f9abc621b2d548f8dbf8979bd16608d2d8fc3260b4ebc0dd42482481d548c7075711b5759649c41f439fad69954956c9326841ea6492956829f9e0dc789f73633b40f6ac77bcae6dfc7930cfe89e526d1684365c5b0be2437fdb01
+d = 54c066711cdb061eda07e5275f7e95a9962c6764b84f6f1f3ab5a588e0a2afb1
+Qx = 0a7dbb8bf50cb605eb2268b081f26d6b08e012f952c4b70a5a1e6e7d46af98bb
+Qy = f26dd7d799930062480849962ccf5004edcfd307c044f4e8f667c9baa834eeae
+k = 646fe933e96c3b8f9f507498e907fdd201f08478d0202c752a7c2cfebf4d061a
+R = b53ce4da1aa7c0dc77a1896ab716b921499aed78df725b1504aba1597ba0c64b
+S = d7c246dc7ad0e67700c373edcfdd1c0a0495fc954549ad579df6ed1438840851
+
+Msg = 21188c3edd5de088dacc1076b9e1bcecd79de1003c2414c3866173054dc82dde85169baa77993adb20c269f60a5226111828578bcc7c29e6e8d2dae81806152c8ba0c6ada1986a1983ebeec1473a73a04795b6319d48662d40881c1723a706f516fe75300f92408aa1dc6ae4288d2046f23c1aa2e54b7fb6448a0da922bd7f34
+d = 34fa4682bf6cb5b16783adcd18f0e6879b92185f76d7c920409f904f522db4b1
+Qx = 105d22d9c626520faca13e7ced382dcbe93498315f00cc0ac39c4821d0d73737
+Qy = 6c47f3cbbfa97dfcebe16270b8c7d5d3a5900b888c42520d751e8faf3b401ef4
+k = a6f463ee72c9492bc792fe98163112837aebd07bab7a84aaed05be64db3086f4
+R = 542c40a18140a6266d6f0286e24e9a7bad7650e72ef0e2131e629c076d962663
+S = 4f7f65305e24a6bbb5cff714ba8f5a2cee5bdc89ba8d75dcbf21966ce38eb66f
+
+[P-256,SHA-384]
+
+Msg = e0b8596b375f3306bbc6e77a0b42f7469d7e83635990e74aa6d713594a3a24498feff5006790742d9c2e9b47d714bee932435db747c6e733e3d8de41f2f91311f2e9fd8e025651631ffd84f66732d3473fbd1627e63dc7194048ebec93c95c159b5039ab5e79e42c80b484a943f125de3da1e04e5bf9c16671ad55a1117d3306
+d = b6faf2c8922235c589c27368a3b3e6e2f42eb6073bf9507f19eed0746c79dced
+Qx = e0e7b99bc62d8dd67883e39ed9fa0657789c5ff556cc1fd8dd1e2a55e9e3f243
+Qy = 63fbfd0232b95578075c903a4dbf85ad58f8350516e1ec89b0ee1f5e1362da69
+k = 9980b9cdfcef3ab8e219b9827ed6afdd4dbf20bd927e9cd01f15762703487007
+R = f5087878e212b703578f5c66f434883f3ef414dc23e2e8d8ab6a8d159ed5ad83
+S = 306b4c6c20213707982dffbb30fba99b96e792163dd59dbe606e734328dd7c8a
+
+Msg = 099a0131179fff4c6928e49886d2fdb3a9f239b7dd5fa828a52cbbe3fcfabecfbba3e192159b887b5d13aa1e14e6a07ccbb21f6ad8b7e88fee6bea9b86dea40ffb962f38554056fb7c5bb486418915f7e7e9b9033fe3baaf9a069db98bc02fa8af3d3d1859a11375d6f98aa2ce632606d0800dff7f55b40f971a8586ed6b39e9
+d = 118958fd0ff0f0b0ed11d3cf8fa664bc17cdb5fed1f4a8fc52d0b1ae30412181
+Qx = afda82260c9f42122a3f11c6058839488f6d7977f6f2a263c67d06e27ea2c355
+Qy = 0ae2bbdd2207c590332c5bfeb4c8b5b16622134bd4dc55382ae806435468058b
+k = 23129a99eeda3d99a44a5778a46e8e7568b91c31fb7a8628c5d9820d4bed4a6b
+R = e446600cab1286ebc3bb332012a2f5cc33b0a5ef7291d5a62a84de5969d77946
+S = cf89b12793ee1792eb26283b48fa0bdcb45ae6f6ad4b02564bf786bb97057d5a
+
+Msg = 0fbc07ea947c946bea26afa10c51511039b94ddbc4e2e4184ca3559260da24a14522d1497ca5e77a5d1a8e86583aeea1f5d4ff9b04a6aa0de79cd88fdb85e01f171143535f2f7c23b050289d7e05cebccdd131888572534bae0061bdcc3015206b9270b0d5af9f1da2f9de91772d178a632c3261a1e7b3fb255608b3801962f9
+d = 3e647357cd5b754fad0fdb876eaf9b1abd7b60536f383c81ce5745ec80826431
+Qx = 702b2c94d039e590dd5c8f9736e753cf5824aacf33ee3de74fe1f5f7c858d5ed
+Qy = 0c28894e907af99fb0d18c9e98f19ac80dd77abfa4bebe45055c0857b82a0f4d
+k = 9beab7722f0bcb468e5f234e074170a60225255de494108459abdf603c6e8b35
+R = c4021fb7185a07096547af1fb06932e37cf8bd90cf593dea48d48614fa237e5e
+S = 7fb45d09e2172bec8d3e330aa06c43fbb5f625525485234e7714b7f6e92ba8f1
+
+Msg = 1e38d750d936d8522e9db1873fb4996bef97f8da3c6674a1223d29263f1234a90b751785316444e9ba698bc8ab6cd010638d182c9adad4e334b2bd7529f0ae8e9a52ad60f59804b2d780ed52bdd33b0bf5400147c28b4304e5e3434505ae7ce30d4b239e7e6f0ecf058badd5b388eddbad64d24d2430dd04b4ddee98f972988f
+d = 76c17c2efc99891f3697ba4d71850e5816a1b65562cc39a13da4b6da9051b0fd
+Qx = d12512e934c367e4c4384dbd010e93416840288a0ba00b299b4e7c0d91578b57
+Qy = ebf8835661d9b578f18d14ae4acf9c357c0dc8b7112fc32824a685ed72754e23
+k = 77cffa6f9a73904306f9fcd3f6bbb37f52d71e39931bb4aec28f9b076e436ccf
+R = 4d5a9d95b0f09ce8704b0f457b39059ee606092310df65d3f8ae7a2a424cf232
+S = 7d3c014ca470a73cef1d1da86f2a541148ad542fbccaf9149d1b0b030441a7eb
+
+Msg = abcf0e0f046b2e0672d1cc6c0a114905627cbbdefdf9752f0c31660aa95f2d0ede72d17919a9e9b1add3213164e0c9b5ae3c76f1a2f79d3eeb444e6741521019d8bd5ca391b28c1063347f07afcfbb705be4b52261c19ebaf1d6f054a74d86fb5d091fa7f229450996b76f0ada5f977b09b58488eebfb5f5e9539a8fd89662ab
+d = 67b9dea6a575b5103999efffce29cca688c781782a41129fdecbce76608174de
+Qx = b4238b029fc0b7d9a5286d8c29b6f3d5a569e9108d44d889cd795c4a385905be
+Qy = 8cb3fff8f6cca7187c6a9ad0a2b1d9f40ae01b32a7e8f8c4ca75d71a1fffb309
+k = d02617f26ede3584f0afcfc89554cdfb2ae188c192092fdde3436335fafe43f1
+R = 26fd9147d0c86440689ff2d75569795650140506970791c90ace0924b44f1586
+S = 00a34b00c20a8099df4b0a757cbef8fea1cb3ea7ced5fbf7e987f70b25ee6d4f
+
+Msg = dc3d4884c741a4a687593c79fb4e35c5c13c781dca16db561d7e393577f7b62ca41a6e259fc1fb8d0c4e1e062517a0fdf95558b7799f20c211796167953e6372c11829beec64869d67bf3ee1f1455dd87acfbdbcc597056e7fb347a17688ad32fda7ccc3572da7677d7255c261738f07763cd45973c728c6e9adbeecadc3d961
+d = ecf644ea9b6c3a04fdfe2de4fdcb55fdcdfcf738c0b3176575fa91515194b566
+Qx = c3bdc7c795ec94620a2cfff614c13a3390a5e86c892e53a24d3ed22228bc85bf
+Qy = 70480fc5cf4aacd73e24618b61b5c56c1ced8c4f1b869580ea538e68c7a61ca3
+k = 53291d51f68d9a12d1dcdc58892b2f786cc15f631f16997d2a49bace513557d4
+R = a860c8b286edf973ce4ce4cf6e70dc9bbf3818c36c023a845677a9963705df8b
+S = 5630f986b1c45e36e127dd7932221c4272a8cc6e255e89f0f0ca4ec3a9f76494
+
+Msg = 719bf1911ae5b5e08f1d97b92a5089c0ab9d6f1c175ac7199086aeeaa416a17e6d6f8486c711d386f284f096296689a54d330c8efb0f5fa1c5ba128d3234a3da856c2a94667ef7103616a64c913135f4e1dc50e38daa60610f732ad1bedfcc396f87169392520314a6b6b9af6793dbabad4599525228cc7c9c32c4d8e097ddf6
+d = 4961485cbc978f8456ec5ac7cfc9f7d9298f99415ecae69c8491b258c029bfee
+Qx = 8d40bf2299e05d758d421972e81cfb0cce68b949240dc30f315836acc70bef03
+Qy = 5674e6f77f8b46f46cca937d83b128dffbe9bd7e0d3d08aa2cbbfdfb16f72c9a
+k = 373a825b5a74b7b9e02f8d4d876b577b4c3984168d704ba9f95b19c05ed590af
+R = ef6fb386ad044b63feb7445fa16b10319018e9cea9ef42bca83bdad01992234a
+S = ac1f42f652eb1786e57be01d847c81f7efa072ba566d4583af4f1551a3f76c65
+
+Msg = 7cf19f4c851e97c5bca11a39f0074c3b7bd3274e7dd75d0447b7b84995dfc9f716bf08c25347f56fcc5e5149cb3f9cfb39d408ace5a5c47e75f7a827fa0bb9921bb5b23a6053dbe1fa2bba341ac874d9b1333fc4dc224854949f5c8d8a5fedd02fb26fdfcd3be351aec0fcbef18972956c6ec0effaf057eb4420b6d28e0c008c
+d = 587907e7f215cf0d2cb2c9e6963d45b6e535ed426c828a6ea2fb637cca4c5cbd
+Qx = 660da45c413cc9c9526202c16b402af602d30daaa7c342f1e722f15199407f31
+Qy = e6f8cbb06913cc718f2d69ba2fb3137f04a41c27c676d1a80fbf30ea3ca46439
+k = 6b8eb7c0d8af9456b95dd70561a0e902863e6dfa1c28d0fd4a0509f1c2a647b2
+R = 08fabf9b57de81875bfa7a4118e3e44cfb38ec6a9b2014940207ba3b1c583038
+S = a58d199b1deba7350616230d867b2747a3459421811c291836abee715b8f67b4
+
+Msg = b892ffabb809e98a99b0a79895445fc734fa1b6159f9cddb6d21e510708bdab6076633ac30aaef43db566c0d21f4381db46711fe3812c5ce0fb4a40e3d5d8ab24e4e82d3560c6dc7c37794ee17d4a144065ef99c8d1c88bc22ad8c4c27d85ad518fa5747ae35276fc104829d3f5c72fc2a9ea55a1c3a87007cd133263f79e405
+d = 24b1e5676d1a9d6b645a984141a157c124531feeb92d915110aef474b1e27666
+Qx = b4909a5bdf25f7659f4ef35e4b811429fb2c59126e3dad09100b46aea6ebe7a6
+Qy = 760ae015fa6af5c9749c4030fdb5de6e58c6b5b1944829105cf7edf7d3a22cfb
+k = 88794923d8943b5dbcc7a7a76503880ff7da632b0883aaa60a9fcc71bf880fd6
+R = 6ec9a340b77fae3c7827fa96d997e92722ff2a928217b6dd3c628f3d49ae4ce6
+S = 637b54bbcfb7e7d8a41ea317fcfca8ad74eb3bb6b778bc7ef9dec009281976f7
+
+Msg = 8144e37014c95e13231cbd6fa64772771f93b44e37f7b02f592099cc146343edd4f4ec9fa1bc68d7f2e9ee78fc370443aa2803ff4ca52ee49a2f4daf2c8181ea7b8475b3a0f608fc3279d09e2d057fbe3f2ffbe5133796124781299c6da60cfe7ecea3abc30706ded2cdf18f9d788e59f2c31662df3abe01a9b12304fb8d5c8c
+d = bce49c7b03dcdc72393b0a67cf5aa5df870f5aaa6137ada1edc7862e0981ec67
+Qx = c786d9421d67b72b922cf3def2a25eeb5e73f34543eb50b152e738a98afb0ca5
+Qy = 6796271e79e2496f9e74b126b1123a3d067de56b5605d6f51c8f6e1d5bb93aba
+k = 89e690d78a5e0d2b8ce9f7fcbf34e2605fd9584760fa7729043397612dd21f94
+R = 07e5054c384839584624e8d730454dc27e673c4a90cbf129d88b91250341854d
+S = f7e665b88614d0c5cbb3007cafe713763d81831525971f1747d92e4d1ca263a7
+
+Msg = a3683d120807f0a030feed679785326698c3702f1983eaba1b70ddfa7f0b3188060b845e2b67ed57ee68087746710450f7427cb34655d719c0acbc09ac696adb4b22aba1b9322b7111076e67053a55f62b501a4bca0ad9d50a868f51aeeb4ef27823236f5267e8da83e143047422ce140d66e05e44dc84fb3a4506b2a5d7caa8
+d = 73188a923bc0b289e81c3db48d826917910f1b957700f8925425c1fb27cabab9
+Qx = 86662c014ab666ee770723be8da38c5cd299efc6480fc6f8c3603438fa8397b9
+Qy = f26b3307a650c3863faaa5f642f3ba1384c3d3a02edd3d48c657c269609cc3fc
+k = ec90584ab3b383b590626f36ed4f5110e49888aec7ae7a9c5ea62dd2dc378666
+R = 13e9ad59112fde3af4163eb5c2400b5e9a602576d5869ac1c569075f08c90ff6
+S = 708ac65ff2b0baaccc6dd954e2a93df46016bd04457636de06798fcc17f02be5
+
+Msg = b1df8051b213fc5f636537e37e212eb20b2423e6467a9c7081336a870e6373fc835899d59e546c0ac668cc81ce4921e88f42e6da2a109a03b4f4e819a17c955b8d099ec6b282fb495258dca13ec779c459da909475519a3477223c06b99afbd77f9922e7cbef844b93f3ce5f50db816b2e0d8b1575d2e17a6b8db9111d6da578
+d = f637d55763fe819541588e0c603f288a693cc66823c6bb7b8e003bd38580ebce
+Qx = 74a4620c578601475fc169a9b84be613b4a16cb6acab8fd98848a6ec9fbd133d
+Qy = 42b9e35d347c107e63bd55f525f915bcf1e3d2b81d002d3c39acf10fc30645a1
+k = 4d578f5099636234d9c1d566f1215d5d887ae5d47022be17dbf32a11a03f053b
+R = 113a933ebc4d94ce1cef781e4829df0c493b0685d39fb2048ce01b21c398dbba
+S = 3005bd4ec63dbd04ce9ff0c6246ad65d27fcf62edb2b7e461589f9f0e7446ffd
+
+Msg = 0b918ede985b5c491797d0a81446b2933be312f419b212e3aae9ba5914c00af431747a9d287a7c7761e9bcbc8a12aaf9d4a76d13dad59fc742f8f218ef66eb67035220a07acc1a357c5b562ecb6b895cf725c4230412fefac72097f2c2b829ed58742d7c327cad0f1058df1bddd4ae9c6d2aba25480424308684cecd6517cdd8
+d = 2e357d51517ff93b821f895932fddded8347f32596b812308e6f1baf7dd8a47f
+Qx = 7e4078a1d50c669fb2996dd9bacb0c3ac7ede4f58fa0fa1222e78dbf5d1f4186
+Qy = 0014e46e90cc171fbb83ea34c6b78202ea8137a7d926f0169147ed5ae3d6596f
+k = be522b0940b9a40d84bf790fe6abdc252877e671f2efa63a33a65a512fc2aa5c
+R = a26b9ad775ac37ff4c7f042cdc4872c5e4e5e800485f488ddfaaed379f468090
+S = f88eae2019bebbba62b453b8ee3472ca5c67c267964cffe0cf2d2933c1723dff
+
+Msg = 0fab26fde1a4467ca930dbe513ccc3452b70313cccde2994eead2fde85c8da1db84d7d06a024c9e88629d5344224a4eae01b21a2665d5f7f36d5524bf5367d7f8b6a71ea05d413d4afde33777f0a3be49c9e6aa29ea447746a9e77ce27232a550b31dd4e7c9bc8913485f2dc83a56298051c92461fd46b14cc895c300a4fb874
+d = 77d60cacbbac86ab89009403c97289b5900466856887d3e6112af427f7f0f50b
+Qx = a62032dfdb87e25ed0c70cad20d927c7effeb2638e6c88ddd670f74df16090e5
+Qy = 44c5ee2cf740ded468f5d2efe13daa7c5234645a37c073af35330d03a4fed976
+k = 06c1e692b045f425a21347ecf72833d0242906c7c1094f805566cdcb1256e394
+R = eb173b51fb0aec318950d097e7fda5c34e529519631c3e2c9b4550b903da417d
+S = ca2c13574bf1b7d56e9dc18315036a31b8bceddf3e2c2902dcb40f0cc9e31b45
+
+Msg = 7843f157ef8566722a7d69da67de7599ee65cb3975508f70c612b3289190e364141781e0b832f2d9627122742f4b5871ceeafcd09ba5ec90cae6bcc01ae32b50f13f63918dfb5177df9797c6273b92d103c3f7a3fc2050d2b196cc872c57b77f9bdb1782d4195445fcc6236dd8bd14c8bcbc8223a6739f6a17c9a861e8c821a6
+d = 486854e77962117f49e09378de6c9e3b3522fa752b10b2c810bf48db584d7388
+Qx = 760b5624bd64d19c866e54ccd74ad7f98851afdbc3ddeae3ec2c52a135be9cfa
+Qy = feca15ce9350877102eee0f5af18b2fed89dc86b7df0bf7bc2963c1638e36fe8
+k = e4f77c6442eca239b01b0254e11a4182782d96f48ab521cc3d1d68df12b5a41a
+R = bdff14e4600309c2c77f79a25963a955b5b500a7b2d34cb172cd6acd52905c7b
+S = b0479cdb3df79923ec36a104a129534c5d59f622be7d613aa04530ad2507d3a2
+
+[P-256,SHA-512]
+
+Msg = 6c8572b6a3a4a9e8e03dbeed99334d41661b8a8417074f335ab1845f6cc852adb8c01d9820fcf8e10699cc827a8fbdca2cbd46cc66e4e6b7ba41ec3efa733587e4a30ec552cd8ddab8163e148e50f4d090782897f3ddac84a41e1fcfe8c56b6152c0097b0d634b41011471ffd004f43eb4aafc038197ec6bae2b4470e869bded
+d = 9dd0d3a3d514c2a8adb162b81e3adfba3299309f7d2018f607bdb15b1a25f499
+Qx = 6b738de3398b6ac57b9591f9d7985dd4f32137ad3460dcf8970c1390cb9eaf8d
+Qy = 83bc61e26d2bbbd3cf2d2ab445a2bc4ab5dde41f4a13078fd1d3cc36ab596d57
+k = 9106192170ccb3c64684d48287bb81bbed51b40d503462c900e5c7aae43e380a
+R = 275fa760878b4dc05e9d157fedfd8e9b1c9c861222a712748cb4b7754c043fb1
+S = 699d906bb8435a05345af3b37e3b357786939e94caae257852f0503adb1e0f7e
+
+Msg = 7e3c8fe162d48cc8c5b11b5e5ebc05ebc45c439bdbc0b0902145921b8383037cb0812222031598cd1a56fa71694fbd304cc62938233465ec39c6e49f57dfe823983b6923c4e865633949183e6b90e9e06d8275f3907d97967d47b6239fe2847b7d49cf16ba69d2862083cf1bccf7afe34fdc90e21998964107b64abe6b89d126
+d = f9bf909b7973bf0e3dad0e43dcb2d7fa8bda49dbe6e5357f8f0e2bd119be30e6
+Qx = f2a6674d4e86152a527199bed293fa63acde1b4d8a92b62e552210ba45c38792
+Qy = c72565c24f0eee6a094af341ddd8579747b865f91c8ed5b44cda8a19cc93776f
+k = e547791f7185850f03d0c58419648f65b9d29cdc22ed1de2a64280220cfcafba
+R = 4782903d2aaf8b190dab5cae2223388d2d8bd845b3875d37485c54e1ded1d3d8
+S = dfb40e406bfa074f0bf832771b2b9f186e2211f0bca279644a0ca8559acf39da
+
+Msg = d5aa8ac9218ca661cd177756af6fbb5a40a3fecfd4eea6d5872fbb9a2884784aa9b5f0c023a6e0da5cf6364754ee6465b4ee2d0ddc745b02994c98427a213c849537da5a4477b3abfe02648be67f26e80b56a33150490d062aaac137aa47f11cfeddba855bab9e4e028532a563326d927f9e6e3292b1fb248ee90b6f429798db
+d = 724567d21ef682dfc6dc4d46853880cfa86fe6fea0efd51fac456f03c3d36ead
+Qx = 70b877b5e365fcf08140b1eca119baba662879f38e059d074a2cb60b03ea5d39
+Qy = 5f56f94d591df40b9f3b8763ac4b3dbe622c956d5bd0c55658b6f46fa3deb201
+k = 79d6c967ed23c763ece9ca4b026218004c84dc2d4ccc86cf05c5d0f791f6279b
+R = 2ba2ea2d316f8937f184ad3028e364574d20a202e4e7513d7af57ac2456804d1
+S = 64fe94968d18c5967c799e0349041b9e40e6c6c92ebb475e80dd82f51cf07320
+
+Msg = 790b06054afc9c3fc4dfe72df19dd5d68d108cfcfca6212804f6d534fd2fbe489bd8f64bf205ce04bcb50124a12ce5238fc3fe7dd76e6fa640206af52549f133d593a1bfd423ab737f3326fa79433cde293236f90d4238f0dd38ed69492ddbd9c3eae583b6325a95dec3166fe52b21658293d8c137830ef45297d67813b7a508
+d = 29c5d54d7d1f099d50f949bfce8d6073dae059c5a19cc70834722f18a7199edd
+Qx = 3088d4f45d274cc5f418c8ecc4cbcf96be87491f420250f8cbc01cdf2503ec47
+Qy = 634db48198129237ed068c88ff5809f6211921a6258f548f4b64dd125921b78b
+k = 0508ad7774908b5705895fda5c3b7a3032bf85dab7232bf981177019f3d76460
+R = acd9f3b63626c5f32103e90e1dd1695907b1904aa9b14f2132caef331321971b
+S = 15c04a8bd6c13ed5e9961814b2f406f064670153e4d5465dcef63c1d9dd52a87
+
+Msg = 6d549aa87afdb8bfa60d22a68e2783b27e8db46041e4df04be0c261c4734b608a96f198d1cdb8d082ae48579ec9defcf21fbc72803764a58c31e5323d5452b9fb57c8991d31749140da7ef067b18bf0d7dfbae6eefd0d8064f334bf7e9ec1e028daed4e86e17635ec2e409a3ed1238048a45882c5c57501b314e636b9bc81cbe
+d = 0d8095da1abba06b0d349c226511f642dabbf1043ad41baa4e14297afe8a3117
+Qx = 75a45758ced45ecf55f755cb56ca2601d794ebeaeb2e6107fe2fc443f580e23c
+Qy = 5303d47d5a75ec821d51a2ee7548448208c699eca0cd89810ffc1aa4faf81ead
+k = 5165c54def4026ab648f7768c4f1488bcb183f6db7ffe02c7022a529a116482a
+R = ebc85fc4176b446b3384ccc62fc2526b45665561a0e7e9404ac376c90e450b59
+S = 8b2c09428e62c5109d17ed0cf8f9fd7c370d018a2a73f701effc9b17d04852c6
+
+Msg = 1906e48b7f889ee3ff7ab0807a7aa88f53f4018808870bfed6372a77330c737647961324c2b4d46f6ee8b01190474951a701b048ae86579ff8e3fc889fecf926b17f98958ac7534e6e781ca2db2baa380dec766cfb2a3eca2a9d5818967d64dfab84f768d24ec122eebacaab0a4dc3a75f37331bb1c43dd8966cc09ec4945bbd
+d = 52fe57da3427b1a75cb816f61c4e8e0e0551b94c01382b1a80837940ed579e61
+Qx = 2177e20a2092a46667debdcc21e7e45d6da72f124adecbc5ada6a7bcc7b401d5
+Qy = 550e468f2626070a080afeeb98edd75a721eb773c8e62149f3e903cf9c4d7b61
+k = 0464fe9674b01ff5bd8be21af3399fad66f90ad30f4e8ee6e2eb9bcccfd5185c
+R = f8250f073f34034c1cde58f69a85e2f5a030703ebdd4dbfb98d3b3690db7d114
+S = a9e83e05f1d6e0fef782f186bedf43684c825ac480174d48b0e4d31505e27498
+
+Msg = 7b59fef13daf01afec35dea3276541be681c4916767f34d4e874464d20979863ee77ad0fd1635bcdf93e9f62ed69ae52ec90aab5bbf87f8951213747ccec9f38c775c1df1e9d7f735c2ce39b42edb3b0c5086247556cfea539995c5d9689765288ec600848ecf085c01ca738bbef11f5d12d4457db988b4add90be00781024ad
+d = 003d91611445919f59bfe3ca71fe0bfdeb0e39a7195e83ac03a37c7eceef0df2
+Qx = 7b9c592f61aae0555855d0b9ebb6fd00fb6746e8842e2523565c858630b9ba00
+Qy = d35b2e168b1875bbc563bea5e8d63c4e38957c774a65e762959a349eaf263ba0
+k = ef9df291ea27a4b45708f7608723c27d7d56b7df0599a54bc2c2fabbff373b40
+R = 66d057fd39958b0e4932bacd70a1769bbadcb62e4470937b45497a3d4500fabb
+S = 6c853b889e18b5a49ee54b54dd1aaedfdd642e30eba171c5cab677f0df9e7318
+
+Msg = 041a6767a935dc3d8985eb4e608b0cbfebe7f93789d4200bcfe595277ac2b0f402889b580b72def5da778a680fd380c955421f626d52dd9a83ea180187b850e1b72a4ec6dd63235e598fd15a9b19f8ce9aec1d23f0bd6ea4d92360d50f951152bc9a01354732ba0cf90aaed33c307c1de8fa3d14f9489151b8377b57c7215f0b
+d = 48f13d393899cd835c4193670ec62f28e4c4903e0bbe5817bf0996831a720bb7
+Qx = 82a1a96f4648393c5e42633ecdeb1d8245c78c5ea236b5bab460dedcc8924bc0
+Qy = e8cbf03c34b5154f876de19f3bb6fd43cd2eabf6e7c95467bcfa8c8fc42d76fd
+k = efed736e627899fea944007eea39a4a63c0c2e26491cd12adb546be3e5c68f7d
+R = cf7fc24bdaa09ac0cca8497e13298b961380668613c7493954048c06385a7044
+S = f38b1c8306cf82ab76ee3a772b14416b49993fe11f986e9b0f0593c52ec91525
+
+Msg = 7905a9036e022c78b2c9efd40b77b0a194fbc1d45462779b0b76ad30dc52c564e48a493d8249a061e62f26f453ba566538a4d43c64fb9fdbd1f36409316433c6f074e1b47b544a847de25fc67d81ac801ed9f7371a43da39001c90766f943e629d74d0436ba1240c3d7fab990d586a6d6ef1771786722df56448815f2feda48f
+d = 95c99cf9ec26480275f23de419e41bb779590f0eab5cf9095d37dd70cb75e870
+Qx = 42c292b0fbcc9f457ae361d940a9d45ad9427431a105a6e5cd90a345fe3507f7
+Qy = 313b08fd2fa351908b3178051ee782cc62b9954ad95d4119aa564900f8ade70c
+k = 4c08dd0f8b72ae9c674e1e448d4e2afe3a1ee69927fa23bbff3716f0b99553b7
+R = f2bc35eb1b8488b9e8d4a1dbb200e1abcb855458e1557dc1bf988278a174eb3b
+S = ed9a2ec043a1d578e8eba6f57217976310e8674385ad2da08d6146c629de1cd9
+
+Msg = cf25e4642d4f39d15afb7aec79469d82fc9aedb8f89964e79b749a852d931d37436502804e39555f5a3c75dd958fd5291ada647c1a5e38fe7b1048f16f2b711fdd5d39acc0812ca65bd50d7f8119f2fd195ab16633503a78ee9102c1f9c4c22568e0b54bd4fa3f5ff7b49160bf23e7e2231b1ebebbdaf0e4a7d4484158a87e07
+d = e15e835d0e2217bc7c6f05a498f20af1cd56f2f165c23d225eb3360aa2c5cbcf
+Qx = 89dd22052ec3ab4840206a62f2270c21e7836d1a9109a3407dd0974c7802b9ae
+Qy = e91609ba35c7008b080c77a9068d97a14ca77b97299e74945217672b2fd5faf0
+k = c9f621441c235fc47ec34eef4c08625df1ec74918e1f86075b753f2589f4c60b
+R = a70d1a2d555d599bfb8c9b1f0d43725341151d17a8d0845fa56f3563703528a7
+S = 4e05c45adf41783e394a5312f86e66871c4be4896948c85966879d5c66d54b37
+
+Msg = 7562c445b35883cc937be6349b4cefc3556a80255d70f09e28c3f393daac19442a7eecedcdfbe8f7628e30cd8939537ec56d5c9645d43340eb4e78fc5dd4322de8a07966b262770d7ff13a071ff3dce560718e60ed3086b7e0003a6abafe91af90af86733ce8689440bf73d2aa0acfe9776036e877599acbabfcb03bb3b50faa
+d = 808c08c0d77423a6feaaffc8f98a2948f17726e67c15eeae4e672edbe388f98c
+Qx = b0c0ad5e1f6001d8e9018ec611b2e3b91923e69fa6c98690ab644d650f640c42
+Qy = 610539c0b9ed21ac0a2f27527c1a61d9b47cbf033187b1a6ada006eb5b2662ed
+k = 1f6d4a905c761a53d54c362976717d0d7fc94d222bb5489e4830080a1a67535d
+R = 83404dcf8320baf206381800071e6a75160342d19743b4f176960d669dd03d07
+S = 3f75dcf102008b2989f81683ae45e9f1d4b67a6ef6fd5c8af44828af80e1cfb5
+
+Msg = 051c2db8e71e44653ea1cb0afc9e0abdf12658e9e761bfb767c20c7ab4adfcb18ed9b5c372a3ac11d8a43c55f7f99b33355437891686d42362abd71db8b6d84dd694d6982f0612178a937aa934b9ac3c0794c39027bdd767841c4370666c80dbc0f8132ca27474f553d266deefd7c9dbad6d734f9006bb557567701bb7e6a7c9
+d = f7c6315f0081acd8f09c7a2c3ec1b7ece20180b0a6365a27dcd8f71b729558f9
+Qx = 250f7112d381c1751860045d9bcaf20dbeb25a001431f96ac6f19109362ffebb
+Qy = 49fba9efe73546135a5a31ab3753e247034741ce839d3d94bd73936c4a17e4aa
+k = 68c299be2c0c6d52d208d5d1a9e0ffa2af19b4833271404e5876e0aa93987866
+R = 7b195e92d2ba95911cda7570607e112d02a1c847ddaa33924734b51f5d81adab
+S = 10d9f206755cef70ab5143ac43f3f8d38aea2644f31d52eaf3b472ee816e11e5
+
+Msg = 4dcb7b62ba31b866fce7c1feedf0be1f67bf611dbc2e2e86f004422f67b3bc1839c6958eb1dc3ead137c3d7f88aa97244577a775c8021b1642a8647bba82871e3c15d0749ed343ea6cad38f123835d8ef66b0719273105e924e8685b65fd5dc430efbc35b05a6097f17ebc5943cdcd9abcba752b7f8f37027409bd6e11cd158f
+d = f547735a9409386dbff719ce2dae03c50cb437d6b30cc7fa3ea20d9aec17e5a5
+Qx = 4ca87c5845fb04c2f76ae3273073b0523e356a445e4e95737260eba9e2d021db
+Qy = 0f86475d07f82655320fdf2cd8db23b21905b1b1f2f9c48e2df87e24119c4880
+k = 91bd7d97f7ed3253cedefc144771bb8acbbda6eb24f9d752bbe1dd018e1384c7
+R = 008c1755d3df81e64e25270dbaa9396641556df7ffc7ac9add6739c382705397
+S = 77df443c729b039aded5b516b1077fecdd9986402d2c4b01734ba91e055e87fc
+
+Msg = efe55737771070d5ac79236b04e3fbaf4f2e9bed187d1930680fcf1aba769674bf426310f21245006f528779347d28b8aeacd2b1d5e3456dcbf188b2be8c07f19219e4067c1e7c9714784285d8bac79a76b56f2e2676ea93994f11eb573af1d03fc8ed1118eafc7f07a82f3263c33eb85e497e18f435d4076a774f42d276c323
+d = 26a1aa4b927a516b661986895aff58f40b78cc5d0c767eda7eaa3dbb835b5628
+Qx = 28afa3b0f81a0e95ad302f487a9b679fcdef8d3f40236ec4d4dbf4bb0cbba8b2
+Qy = bb4ac1be8405cbae8a553fbc28e29e2e689fabe7def26d653a1dafc023f3cecf
+k = f98e1933c7fad4acbe94d95c1b013e1d6931fa8f67e6dbb677b564ef7c3e56ce
+R = 15a9a5412d6a03edd71b84c121ce9a94cdd166e40da9ce4d79f1afff6a395a53
+S = 86bbc2b6c63bad706ec0b093578e3f064736ec69c0dba59b9e3e7f73762a4dc3
+
+Msg = ea95859cc13cccb37198d919803be89c2ee10befdcaf5d5afa09dcc529d333ae1e4ffd3bd8ba8642203badd7a80a3f77eeee9402eed365d53f05c1a995c536f8236ba6b6ff8897393506660cc8ea82b2163aa6a1855251c87d935e23857fe35b889427b449de7274d7754bdeace960b4303c5dd5f745a5cfd580293d6548c832
+d = 6a5ca39aae2d45aa331f18a8598a3f2db32781f7c92efd4f64ee3bbe0c4c4e49
+Qx = c62cc4a39ace01006ad48cf49a3e71466955bbeeca5d318d672695df926b3aa4
+Qy = c85ccf517bf2ebd9ad6a9e99254def0d74d1d2fd611e328b4a3988d4f045fe6f
+k = dac00c462bc85bf39c31b5e01df33e2ec1569e6efcb334bf18f0951992ac6160
+R = 6e7ff8ec7a5c48e0877224a9fa8481283de45fcbee23b4c252b0c622442c26ad
+S = 3dfac320b9c873318117da6bd856000a392b815659e5aa2a6a1852ccb2501df3
+
+
+
+[P-384,SHA-224]
+
+Msg = 39f0b25d4c15b09a0692b22fbacbb5f8aee184cb75887e2ebe0cd3be5d3815d29f9b587e10b3168c939054a89df11068e5c3fac21af742bf4c3e9512f5569674e7ad8b39042bcd73e4b7ce3e64fbea1c434ed01ad4ad8b5b569f6a0b9a1144f94097925672e59ba97bc4d33be2fa21b46c3dadbfb3a1f89afa199d4b44189938
+d = 0af857beff08046f23b03c4299eda86490393bde88e4f74348886b200555276b93b37d4f6fdec17c0ea581a30c59c727
+Qx = 00ea9d109dbaa3900461a9236453952b1f1c2a5aa12f6d500ac774acdff84ab7cb71a0f91bcd55aaa57cb8b4fbb3087d
+Qy = 0fc0e3116c9e94be583b02b21b1eb168d8facf3955279360cbcd86e04ee50751054cfaebcf542538ac113d56ccc38b3e
+k = e2f0ce83c5bbef3a6eccd1744f893bb52952475d2531a2854a88ff0aa9b12c65961e2e517fb334ef40e0c0d7a31ed5f5
+R = c36e5f0d3de71411e6e519f63e0f56cff432330a04fefef2993fdb56343e49f2f7db5fcab7728acc1e33d4692553c02e
+S = 0d4064399d58cd771ab9420d438757f5936c3808e97081e457bc862a0c905295dca60ee94f4537591c6c7d217453909b
+
+Msg = 5a3c80e608ed3ac75a6e45f6e94d374271a6d42b67a481860d5d309cc8b37c79cb61f1716dc8aa84cb309ef9d68eb7fc6cf4b42333f316a5c30e74198c8b340926e340c5de47674a707293c4aa2a1a2274a602f01c26b156e895499c60b38ef53fc2032e7485c168d73700d6fa14232596a0e4997854a0b05d02e351b9d3de96
+d = 047dd5baab23f439ec23b58b7e6ff4cc37813cccb4ea73bb2308e6b82b3170edfe0e131eca50841bf1b686e651c57246
+Qx = de92ff09af2950854a70f2178d2ed50cc7042a7188301a1ea81d9629ad3c29795cb7f0d56630a401e4d6e5bed0068d1e
+Qy = 6135adbd8624130735e64e65ecbd43770dcc12b28e737b5ed033666f34c918eb5589508e4a13b9243374a118a628dd0b
+k = f3922351d14f1e5af84faab12fe57ded30f185afe5547aeb3061104740ecc42a8df0c27f3877b4d855642b78938c4e05
+R = 38e181870cb797c1f4e6598cfd032add1cb60447d33473038d06df73919f844eddd16f40f911075f8a4bacc0d924e684
+S = a58dd1ca18aa31277de66c30c3bb7a14b53705ce6c547ed2cb0e336f63c42809422efffcc722d1155f2254330a02b278
+
+Msg = e7d974c5dbd3bfb8a2fb92fdd782f997d04be79e9713944ce13c5eb6f75dfdec811b7ee4b3859114b07f263846ae13f795eec8f3cb5b7565baff68e0fdd5e09ba8b176d5a71cb03fbc5546e6937fba560acb4db24bd42de1851432b96e8ca4078313cb849bce29c9d805258601d67cd0259e255f3048682e8fdbdda3398c3e31
+d = 54ba9c740535574cebc41ca5dc950629674ee94730353ac521aafd1c342d3f8ac52046ed804264e1440d7fe409c45c83
+Qx = 3db95ded500b2506b627270bac75688dd7d44f47029adeff99397ab4b6329a38dbb278a0fc58fe4914e6ae31721a6875
+Qy = 049288341553a9ac3dc2d9e18e7a92c43dd3c25ca866f0cb4c68127bef6b0e4ba85713d27d45c7d0dc57e5782a6bf733
+k = 04324bd078807f6b18507a93ee60da02031717217ee5ce569750737be912be72da087ac00f50e13fdf7249a6ae33f73e
+R = b2752aa7abc1e5a29421c9c76620bcc3049ecc97e6bc39fcca126f505a9a1bfae3bde89fb751a1aa7b66fa8db3891ef0
+S = f1c69e6d818ca7ae3a477049b46420cebd910c0a9a477fd1a67a38d628d6edaac123aebfca67c53a5c80fe454dba7a9d
+
+Msg = a670fda4d1d56c70de1d8680328043b2b7029633caf0ee59ffe1421c914bb937133d5a0f9214846b2e0b350455a74c4ab434c56de65a17139bb8212bf1c76071a37536fa29348f871dbb26baa92eb93d97e923a6d2ffd9be25cbc33075e494e6db657bd8dc053fe4e17148d8cf6e2058164f2b5766750eb01bbe7b361cdb848c
+d = dabe87bbe95499bac23bc83c8b7307fe04be198f00059e2bf67c9611feaffb2c8f274f6aa50eb99c3074186d8067d659
+Qx = c2aa0a695125279705917e02a4f258cade4c3ff9140a071414babf87764f426f7f36ffda9d5f3394375d24864235476f
+Qy = 8f9808da0ce0227cf453f9e456f557db9752e23b45cce4baad5fee3844ddd7e1112bcec01ea9d67c7a76f3535bd0cb58
+k = 65a0305854033cbc6fe3ca139c40ca354d45801ecb59f4a923c251dc6b25d12d452d99b5d6711fdb5efac812aa464cc4
+R = c7fc32997d17ac79baf5789e4503f5f1a8863872bc350a91f12dd3ef8cf78c254e829217809e8e00b6b8d4d85be3f1fd
+S = 1422e1838a22496df93486bce1142961dbd8478ae844b8dda54e210afdae0d9e930d587c91bb600b0bde7237186d94e6
+
+Msg = 7843f918fe2588bcfe756e1f05b491d913523255aa006818be20b676c957f4edb8df863c6f5f8c15b3b80c7a2aa277b70d53f210bdfb856337980c406ea140e439dd321471407f374f69877b2d82367eed51e3c82c13948616dcb301d0c31f8f0352f2846abd9e72071f446a2f1bd3339a09ae41b84e150fd18f4ba5d3c6bfa0
+d = df43107a1deb24d02e31d479087bd669e2bc3e50f1f44b7db9484a7143cdca6a3391bddfea72dc940dbce8ec5efbd718
+Qx = 76bd4be5d520471162cb5c36f80038301b325f845d9642204a84d78b3e721098932827bf872bde0a9f86383953667d29
+Qy = 415116b8b878f896a5aa4dbbdc21076f27135d8bbcaaca02489ef639d742bd63f377da0c8e8ab36ff19b4a7cc5d4ceb4
+k = 798abad5a30d1805794540057388ee05e2422901c6335f985b9d4447b3ef75524751abfeab6409ad6bf77d4ae3014558
+R = 98744e5c6742fa5118a74a70db4957647a3cc12add4e876b45974a6a8707809f871daadbfc0b865e01624f706b65f10c
+S = 9e256e8da8eff5a0c83baaa1ef4f7be798eba9543bf97adb0fff8719f5406ea1207a0cf703d99aa8f02169724b492273
+
+Msg = caa83d5ab07febbd2e0fe2d63738b9b7b8752594bea7aaf50345b3d2f316653a8c9222f2b7877b64679e9573e81461a426029e45b8873a575094a1d572e0d32a9f0a9c6bcb9a2868543b7d8bbe4a69a09e7321f05f8366cced1b72df526f895b60aed2c39c249653c7839538770d4e5f47d3926ec0d168ab6a1af15bf1dca1f7
+d = ea7a563ba2a7f5ab69973dca1f1a0d1572f0c59817cd3b62ad356c2099e2cdca1c553323563f9dfbb333b126d84abc7f
+Qx = cf4717c5f5de668b785f06bdc9845df5a09e4edd83f4669756407cbb60807305c632bc49f818f4a84b194369aa07736f
+Qy = 7391e4982af8a2218f704f627d01f0508bfc8304992a2d598a420bf2eb519f33bd7caf79380793733b3dba0cc5e2b9d8
+k = 7b9606b3df7b2a340dbc68d9754de0734e1faeb5a0135578a97628d948702235c60b20c8002c8fcf906783e1b389e754
+R = 0d680010bed373287f9767955b5d2850e150b6713b49e453eb280148e45230c853d99ea2d2f8fcbd3ddcba19aeec0af1
+S = 64329763a930ab5452afdb0557fef16ff71810d6343dfc9c6ae18905c3d274db6554cdc69d6078a1ca03284474a94f30
+
+Msg = 594603458d6534974aeeafba919c4d0f4cb6843a3af41204bbb88aeb2fca2772d305163dba863da050aabedbaf89db521955d1715de95bbcef979ecdc0c976181ece00355385f8a8f8cce127c9eac15ce3e958a3ed686184674ec9a50eb63271606ee7fdcb1323da3c3db8e89cad1fb42139a32d08abcfbf0d4ccfca18c89a86
+d = 4cc70cb35b3ddeb0df53a6bd7bd05f8ff4392a2db7344f2d443761484b3a468a4ee3d1a8b27113d57283fd18b05f7829
+Qx = 40e1fe21df34bb85a642a0abe819ebd128f7e39b84d8dcc4a9a599b372fb9588da1484600ec28b1297bb685f9ae77831
+Qy = f3aa69ada57879fdcbe8df19cefabc308add7d03b17b1fac2f7783fece6a8dfe20bc36f518692677d96e3f730a67a671
+k = 8eda401d98f5688c34d8dbebcd3991c87c0442b0379154eaa2e5287dabe9a9e34cfc1305d11ff68781df25d5611b331d
+R = ff2d772786e159448bba26afd8c3281941a4cb0c56fec6f5cccb4c292c4ee0f7af9bd39bbe2d88148732585e104fdb30
+S = 07a1d890770daa949a17797dca7af3e8163da981ec330c03d63d1a8312c152be6a718163205ffa08da7dcc163ba261f4
+
+Msg = 733252d2bd35547838be22656cc7aa67eff0af0b13b428f77267a513c6824c3dbae533068b6817e82665f009560affcfe4b2ddb5b667a644fc1a42d24f24e0947e0dc50fb62c919bc1fe4e7ded5e28f2e6d80fcf66a081fb2763526f8def5a81a4ddd38be0b59ee839da1643eeeaee7b1927cec12cf3da67c02bc5465151e346
+d = 366d15e4cd7605c71560a418bd0f382fd7cd7ad3090ff1b2dfbed74336166a905e1b760cf0bccee7a0e66c5ebfb831f1
+Qx = a143f277ab36a10b645ff6c58241ea67ffdc8acf12d60973068390f06b4d8f4d773b10c1ebf6889b1cfa73ebb90f6ca1
+Qy = 7a17cad29bb507b309021f6f92cb5c10ba535f4a3e317fcc68cfd02d3ccd269f465169c73d30ff308f5350d881b08aec
+k = dbe545f920bc3d704c43d834bab21e40df12ec9e16a619a3e6b3f08760c26aae6e4fd91fad00f745194794b74bb1baee
+R = cdc39b12bba30da66fe9554713c05880ddc27afa4d2d151440f124c351fb9496dc95046516b0921083347d64369846ac
+S = 797d0344e49f9ba87a187c50f664e5015d449e346b1a7bd9427c5be559fc58173651880d5aadf053f81899d3368d6181
+
+Msg = 5a182bd174feb038dfae3346267156bf663167f713dea1ce936b0edb815cd9b8c8e4d411c786ba2494a81442617255db7158b142e720d86c9b56680fb9efd4298cdd69079a28153494c42a24251c7ad42ecf7e97eabc1b3997529b2a297cbad2474269b87a0b1e385f2d7f8b6eb8d1cd75eaf7e91d1acbecd45d7b2bfbbe3216
+d = e357d869857a52a06e1ece5593d16407022354780eb9a7cb8575cef327f877d22322c006b3c8c11e3d7d296a708bdb6d
+Qx = ce9a2185a68d6094aa5849a6efe78b349946f7380f0c79aa9664246cfcc71a879e90ad78a0474f58644c6a208168150e
+Qy = 8354fa47673cb3e07d446521345706c5515584b2602f921c3b9c44dded9e2c3f90ce47adb36d7e5f9f95a8c5ad8af397
+k = 1e77367ac4e10924854d135ad2f2507f39e2bafdbce33ff256bcbe9a7329b8d27185218bcc3550aafbe3390e84c77292
+R = df3182d49ad70959fb0c95bc7312750ce70fc87f1a328d39d9b29ac05d31305ce7209d6c24d13225d9567b489f7a187b
+S = d812b05abab0e96de13291e1f0da6479444ed5cd9d959b76f6cb43d394769035364f7c831a104dc7b5bd9b4a8e64df64
+
+Msg = aaa99fb1c71340d785a18f6f668e898c25cf7a0ac31d13c5b388b7233408493a5a109af6d07065376b96f4903df7aba2b2af671a18772bb0472490d1240cde28967680727dd4acd47e0308920a75da857a6eeedee5b6586d45dff3d8a680599665aa895c89dd7770b824b7dee477ac5e7602d409d3cc553090c970b50811dbab
+d = 745a18db47324a3710b993d115b2834339315e84e7006eafd889fb49bd3cc5a8b50c90526e65e6c53bddd2916d14bead
+Qx = f692578c6f77531210aef55c9e004ce3b66cf268c6900dde31a8bbb76e7562e3fb76242de34ca330d2501030aa119466
+Qy = 40965833b28de926c46de060aa25beaeda98f8415a6b1e3564aa77870cf4c89bd4fde92c8f5d9bf0eb41721586859d8e
+k = 11b9b36720abcac084efdb44c9f5b7d039e3250cb1e9c47850189ba3cfc1489d858b2a44df357772b61d919c7e729c0f
+R = 02b252c99820cf50e6ce060ab55bd4f682276e29b4ae4197417432e6a7bfb8cf0bac89dfe105456af805d822cee77696
+S = 8e248bbf7d7028d63177e565c9d1666ee5be4d1ffbfffc9c7814b0cd38f74b98f3f2cd59be42b9f132bfe5ee789cd96c
+
+Msg = 1fadfa8254d3a0b82d137cfdd82043d5dc1fef195d5297b09cc5cfb061f59c933451c0dc2a11b4037f34f88dacb803251f8880c4b72585c3c196e6fb23484ca43a191f8e41b9b9a37e2e6fcaab6738c3c62d1c98e1c620bb788b7b51a04f998a510efdba0d3418622fe8ce203b3fcd553b9b4206365a39031797ad11e49745ec
+d = 93f20963ea5011ff4f26481e359309e634195f6289134087bd2e83eee008c962780a679784ee7ac6acda03d663ed27e0
+Qx = 0edcde3533ea019e18f1a3cd97b7962e8823dda36c389f8f9287549f796d11376392b8a01c7a80f127a8f75795e04f54
+Qy = 63d7c458dccfc02f5148d755d59f9bbc8e3c3ea34908777928440747795955741296abcdd5386676419ed8049fedb489
+k = 3ad308faf04c42ee5ac69d36bc0aa9a96aacf55ea0f27dac4f52e088f023d206340a6324874ffad169ff80624de24c96
+R = 209b72f9aae72c4339813573c3a8408a9e0be641ca863d81d9d14c48d0bf4cd44a1a7985cff07b5d68f3f9478475645b
+S = f6292e599b22a76eda95393cf59f4745fa6c472effd1f781879ad9a4437a98080b0b07dadad0c249631c682d2836a977
+
+Msg = 9ecb6f5ed3ba666a8536a81ef65012c2cb8b433508798d84708abb06dfb75503886f78384fb8c7a4d2d49ef539d9b8a0b60938c7f07471dda91f258b0d99691b38a8403a2bb3f956bdfd09baba16d9b6877097a9b6213481b47a06e139d23ec7abad5668d21f912fdb70d31bb9adf9b3ce80e308252fa81a51674f88d02db72b
+d = f175e6ac42fd48ec9d652c10707c039c67c4cc61d8c45a373dcda6e4ca6c53e947e49c24e01b48e7cdf92edfe6d316a1
+Qx = a40c64f595491ce15790a5a87fbe64c1800247b42acd08fe5257700719f46afc8acce0e4ede0517a312092d5e3d089cd
+Qy = d565df9dc2f381cc0c5d84f382a43a98018524c0b4708a44b3e2817f9719f29fbf9c15803591ed9b4790c5adaba9f433
+k = 812dcaa6d4f9a43ccc553288065d13761581485aa903a500a690ccafbd330ba4818c977b98c4bb57f8a182a1afacfae9
+R = d000f18d3e4c162ff0d16f662e6703e7a6f5bff7a333ed266fa4f44c752415946c34945c342c20f739677186b1d80ab3
+S = ae7f1271c89e0aaa238710d039ea73a69110cc28fcf426f2fe6754b63a59e417fa84f903cf7dccb5468b43ff083bbfd5
+
+Msg = e55bfca78d98e68d1b63688db12485578f36c489766f4d0bfaa0088433ff12133aaca455805095f2e655940860958b3ead111d9070778ee3bbf3e47e43d9eba8b8d9b1fdf72f793fcde2bcaa334f3e35fa2cca531ea7cf27fe9ccba741e38ac26129b2d612bf54a34e0ae6c166c0fef07fcd2b9ac253d7e041a500f7be7b8369
+d = 46c4f0b228b28aaa0ec8cfdf1d0ed3408b7ae049312fb9eaf5f3892720e68684cc8ad29844a3dc9d110edf6916dfb8bb
+Qx = 13ddec844731b7e30c467451df08ca11d6c581cb64abd8a257671cffd26f5ccad4df7b9ee8924047a88a5d2d7567609c
+Qy = d74ca94f590fd1d13e190cc1e03c3da6c3faab15c7dda034af3deefee8aeec3628fa8b1978c54cfcd071baa319a46ec0
+k = 2a9dd520207c40a379cd4036adef9ee60fa8bc8c0d39b3ad91850ac93fd543f218b1688581f23481a090b0e4c73792ac
+R = 94e08cca20fe3866f643f53ec65faf3f2b4d80cd9bcc8ff8f88bb28da9eada324fc2d048908dd3d08a9e0ebb547731bc
+S = 8e6f82c4d3069b14f4c844b4ca133a9503493265c9f77a7d4775eda67de76798a23dd7ea48e0ac3c337dd62bf058319d
+
+Msg = 02c6b3c83bd34b288d96409162aa4ff114e9d134bf948046eb5ebcc0c7fe9dfceadda83ed69da2fac00c8840f6c702a3fc5e6959d70f7e8af923e99e4937232ae3b841ffefd2e62fab3671a7c94a0281b8ea5bc176add57c5c9b6893fe7f5d48ce7256b96510810c4e046168a3c5be9843b84d5268a50349b3444341aa5490dd
+d = 1d7b71ef01d0d33a8513a3aed3cabb83829589c8021087a740ca65b570777089be721a61172b874a22a1f81aef3f8bb6
+Qx = 8d2721370df8f097d5a69396249a315f6037dc7045b3da11eacae6d43036f779d5de7053d101768b42cc2b1283a3aaea
+Qy = a046039ae662141f9954d278183eaa2e03917fe58583e32d344074d59d60caa5b0949c53066525d5cca923e2f201502e
+k = d1b25ad25581cad17e96f1d302251681fee5b2efbb71c3c15ff035b2145d015d18e0e52dc3187ab5a560277b3a3929b0
+R = d836f52b14c7391744868daa2d5cf27eb9380b9b6176195573d5b04842e9f2fc3794d6cf877feafee63d11b05f6a6bee
+S = 8b89042fef2c04d4bd6c9d66a06a010514321d623a5f8d57ba5ac3686872eaabca9e0ba2d058ae7028e870acf03ca32d
+
+Msg = 94f8bfbb9dd6c9b6193e84c2023a27dea00fd48356909faec2161972439686c146184f80686bc09e1a698af7df9dea3d24d9e9fd6d7348a146339c839282cf8984345dc6a51096d74ad238c35233012ad729f262481ec7cd6488f13a6ebac3f3d23438c7ccb5a66e2bf820e92b71c730bb12fd64ea1770d1f892e5b1e14a9e5c
+d = cf53bdd4c91fe5aa4d82f116bd68153c907963fa3c9d478c9462bb03c79039493a8eaeb855773f2df37e4e551d509dcd
+Qx = 3a65b26c08102b44838f8c2327ea080daf1e4fc45bb279ce03af13a2f9575f0fff9e2e4423a58594ce95d1e710b590ce
+Qy = fe9dcbcb2ec6e8bd8ed3af3ff0aa619e900cc8bab3f50f6e5f79fac09164fb6a2077cc4f1fed3e9ec6899e91db329bf3
+k = df31908c9289d1fe25e055df199591b23e266433ab8657cc82cb3bca96b88720e229f8dfd42d8b78af7db69342430bca
+R = 6770eea9369d6718e60dd0b91aee845ff7ed7e0fcc91675f56d32e5227fd3a4612bbcb1556fe94a989b9e3bcc25bb20e
+S = c43072f706c98126d06a82b04251e3ecb0ba66c4bb6cd7c025919b9cc6019cdc635256d2a7fa017b806b1e88649d2c0d
+
+[P-384,SHA-256]
+
+Msg = 663b12ebf44b7ed3872b385477381f4b11adeb0aec9e0e2478776313d536376dc8fd5f3c715bb6ddf32c01ee1d6f8b731785732c0d8441df636d8145577e7b3138e43c32a61bc1242e0e73d62d624cdc924856076bdbbf1ec04ad4420732ef0c53d42479a08235fcfc4db4d869c4eb2828c73928cdc3e3758362d1b770809997
+d = c602bc74a34592c311a6569661e0832c84f7207274676cc42a89f058162630184b52f0d99b855a7783c987476d7f9e6b
+Qx = 0400193b21f07cd059826e9453d3e96dd145041c97d49ff6b7047f86bb0b0439e909274cb9c282bfab88674c0765bc75
+Qy = f70d89c52acbc70468d2c5ae75c76d7f69b76af62dcf95e99eba5dd11adf8f42ec9a425b0c5ec98e2f234a926b82a147
+k = c10b5c25c4683d0b7827d0d88697cdc0932496b5299b798c0dd1e7af6cc757ccb30fcd3d36ead4a804877e24f3a32443
+R = b11db00cdaf53286d4483f38cd02785948477ed7ebc2ad609054551da0ab0359978c61851788aa2ec3267946d440e878
+S = 16007873c5b0604ce68112a8fee973e8e2b6e3319c683a762ff5065a076512d7c98b27e74b7887671048ac027df8cbf2
+
+Msg = 784d7f4686c01bea32cb6cab8c089fb25c341080d9832e04feac6ea63a341079cbd562a75365c63cf7e63e7e1dddc9e99db75ccee59c5295340c2bba36f457690a8f05c62ab001e3d6b333780117d1456a9c8b27d6c2504db9c1428dad8ba797a4419914fcc636f0f14ede3fba49b023b12a77a2176b0b8ff55a895dcaf8dbce
+d = 0287f62a5aa8432ff5e95618ec8f9ccaa870dde99c30b51b7673378efe4ccac598f4bbebbfd8993f9abb747b6ad638b9
+Qx = b36418a3014074ec9bbcc6a4b2367a4fb464cca7ec0a324cb68670d5c5e03e7a7eb07da117c5ea50b665ab62bd02a491
+Qy = 4ea299c30e7d76e2c5905babada2d3bb4ee5eb35a5a23605cdb0d5133471a53eb9e6758e49105a4eaf29d2267ba84ef2
+k = 935eeab3edeb281fbd4eead0d9c0babd4b10ff18a31663ee9de3bfa9ae8f9d266441158ea31c889ded9b3c592da77fd7
+R = 738f9cb28f3b991335ef17b62559255faf75cad370a222464a492e27bb173c7f16b22100ada6b695875c7e4b1a28f158
+S = bc998c30e1491cd5d60dc7d1c38333165efe036b2a78db9b8f0e85ee68619cfba654e11ae5ca5ee5a87099c27cf22442
+
+Msg = 45e47fccc5bd6801f237cdbeac8f66ebc75f8b71a6da556d2e002352bd85bf269b6bc7c928d7bb1b0422601e4dd80b29d5906f8fcac212fe0eaaf52eda552303259cbcbe532e60abd3d38d786a45e39a2875bce675800a3eaeb9e42983d9fd9031180abd9adccc9ba30c6c198b4202c4dd70f241e969a3c412724b9b595bc28a
+d = d44d3108873977036c9b97e03f914cba2f5775b68c425d550995574081191da764acc50196f6d2508082a150af5cd41f
+Qx = c703835d723c85c643260379d8445b0c816fe9534351921e14a8e147fe140ec7b0c4d704f8dc66a232b2333b28f03dee
+Qy = c5d0bb054053fd86c26f147c4966757aa04b00513a02d427b8d06c16055c607955efdc518d338abfe7927c195dc28588
+k = c80f63e080650c8a21e4f63a62ec909adfb7d877f365d11ee1cb260baf112eb4730c161c1d99dba98fc0d5bbd00dc97d
+R = 81de2810cde421997013513951a3d537c51a013110d6dbb29251410bcb5ba001a9686b8490f1e581e282fd2ed0974b22
+S = 9cab0bbaffe91c7677ec3dd1f17060211a3cc0be574cbca064aa8c4b66ba6e64f3d80e83da895042ca32d311c388d950
+
+Msg = c33ff63b4e6891e00b2349b3f2907c417ca355560544a91e24a7a0ee260d6850aeded29fc0176b6039ca6187e8333391047cceaf14b1077df8f147dad84d36b2dac5666dc2f69dc9b58b88cc73956efdb3b47f91831d5875051c76b0c4e9fc087012a1f03eeee85d6745b46aa50bd9cb0110c2c94508765cec162ee1aa841d73
+d = d5b72cbb6ec68aca46b9c27ad992afd8ffa02cb3067b234fcfa6e272e3b31be760695ff7df988b57663057ab19dd65e3
+Qx = 135a6542612f1468d8a4d01ff1914e532b1dd64d3627db9d403dc325651d3f82b0f6f0fd1dbdeca2be967c4fb3793b5f
+Qy = cbbd40f6d3a38d0dfb64582ff4789d7b268241bc0c36de2884bccfaeeff3b7b2b46a30bb35719804e0d11124b4e7f480
+k = 9da6de7c87c101b68db64fea40d97f8ad974ceb88224c6796c690cbf61b8bd8eede8470b3caf6e6106b66cf3f0eebd55
+R = 17840911ecdf6ae0428b2634f442163c2c11b8dbf0cc7a5596fbe4d33e3e52f9d99e99ad169867b1f39e89c9180cedc2
+S = dd7ed67e480866d0474379ea4afff72870746f4feef2153be42f13bf472b1613d7faa5c0abb7f7464070f94d7cf3f234
+
+Msg = f562f2b9d84b0e96a52532c3b43c39c8018c738bd8dc3797a7de7353971b2729d522d6961b1f2e4df3f6a4bd3653e6d72b74fc0dba92ab939c4b542e994e5db6dd8ed4f56f651e699052e791237ae1f552f990ad156226ae8f7bf17fcbfa564f749604f97e9df0879d50985747d981422a23040fe52f5ec74caf1d4aaad8a710
+d = 218ee54a71ef2ccf012aca231fee28a2c665fc395ff5cd20bde9b8df598c282664abf9159c5b3923132983f945056d93
+Qx = 01989ff07a7a452d8084937448be946bfedac4049cea34b3db6f7c91d07d69e926cce0af3d6e88855a28120cf3dba8df
+Qy = eb064e029d7539d4b301aabafe8de8870162deffe6383bc63cc005add6ee1d5ced4a5761219c60cd58ad5b2a7c74aaa9
+k = c5d39b436d851d94691f5f4aa9ef447f7989d984f279ae8b091aef5449ac062bcc0567740f914624ad5b99fc32f9af0b
+R = 07d5b1b12877e8cb5e0aa5e71eeeb17bf0aa203064c7e98b3a1798a74dc9717252dc47c7f06aaf1d5fe15b868323bbb9
+S = 69428cf101a7af5d08161a9fd7af212e02e33b6062aebdce4c96bf3a0684b5394cb902ca7c2dec6e2f01f40c4576009d
+
+Msg = ace953ae851f571d71779aa120915f27450b236da23e9106f8d0756abdd25861937941228d225d5fb1aa1b1ebf759b1e326aeb3b6cd0cd87edd2ab9f6a7ad67b63d2c501d6a550edb2e7c9d216cc8af78dd33546af64d00abed4d0d2cfc5c9a7b5a055dbe8f7547902d185cf46937314832bc5c602419a82ab83dbd9d3bd5aff
+d = e6ab171f6937c000e144950801ad91023ae8e8476856c2592d9f7d5bb7180fd729211803d39a412ead6c0be761cfa5d1
+Qx = 38bc42b8c9d8866d09b214398d584b1b24a488dfacc3420d1e9506aa825b19fdf1ba74e7b8f547f47b571467fe8c4d1f
+Qy = 5179d62668d3f6a7ab5c8e3761a685e12008fb87d0529a97645f65cfb5364376c1b6682e0ffcddd0bcd995c41d013ad3
+k = 05e9718aea9669c9e434f73866da5f252dec6d24c47a1c4ee3233450b6ec626de9746ebe095b285558dfc89fc1b622fe
+R = df9bab9dd1f22ec6f27116f38831cb2089aa78aa8c073024a0faddd9a48e810a5e8e2cadd80fbf8dbd6088c71fe30b5b
+S = 1e0e8718567d12d18558c57f9e87a755c309e4ffb497335a3adfc8d7475ce8fd882d5dc33a8f5a16274b7ad74bb7862a
+
+Msg = 9635ab832240be95301bedb94c5aec169eedc198cbbdfedcf41e9b586143d829b4597a6b2a81902828332825fd84a785f187a3894e21bd99d22c4f94dcf34453fc052f15ec64d1447c932cb38fcdd30b7be851963409c11881438cbaad7e96f9efbde317f2235d66af804477a5dfe9f0c51448383830050ecf228889f83631e1
+d = 14acd516c7198798fd42ab0684d18df1cd1c99e304312752b3035bed6535a8975dff8acfc2ba1675787c817b5bff6960
+Qx = 29909d143cf7ee9c74b11d52f1a8f3ebd4a720c135612ca5618d3f432f03a95602ee75a2057e1d7aab51d0648ac0b334
+Qy = 404b6c5adffbadfa1b0380ae89fed96ec1ca16cc28661e623d0f1c8b130fbaa96dd7257eae2bf03c2d3dcbc3dbc82c58
+k = 7f623c103eaa9099a0462e55f80519c565adaeffcb57a29993f3a8a92e63a560be8f0fb9d23dc80bff1064bb41abad79
+R = 932ab291950c16b2b19a8036cd2e905714c6229cb190a73b3ea49c48dd8e76063a453c7c3267a57597d2973678216296
+S = d17d4c5ddbb9c27beebf526f113b416c8abfad53d11c4224813c7f351ba41a77dd4e77d6e4a65bef2c9f62cc37a469a5
+
+Msg = d98b9a7d4fe9d0fd95de5056af164a8b7882cd34ab5bde83a2abb32dc361eb56a479a3a6119db3b91dcad26a42d2206749567f0d97c34a981a91fc734921821a429f6a53401743a5c406ba9d560f956203abc9d1f32f1a13e7d7b290f75c95fdbf857ea597021461c06a3aacfa554ede3d69e4ff03bbbee5b7463ec77de2b3b2
+d = 2e780550984f3a00cb1e412429b33493c6eb6cd86d12f9d80588c247dcf567bd04296d2d4b24b889d9c54954b7f38f57
+Qx = 37dac42ef04663238443ef33e8addee2e78c40d50a1751913a7f5c37d1f23a26c7f86e16055c788b8ca9554f06b2f2ef
+Qy = bbed1549652904e3d00c39b01cc0460dbaf3185e6190c2705677a9701de1fe56dff4f4d8418ee15059ff8fc36800982d
+k = b788ca82811b0d4e4841765c71eafaa1e575378beedcd3860d8b92db3d070ac5aef7c425067860fbee6c50cf0c642bbb
+R = 7292b3851870daeb2555a8a2fb198ead78739fcfb75327e5c32a82c6b77d58983e5ad548ccb75dcf9411039c9576d9b9
+S = a378c61802d9f1dd062b6e18f16416a954018f77df4df95ad1b983570377d5cfce4cc7861759e802c52f81abc4f49aac
+
+Msg = 1b4c754ac1c28dc415a71eac816bde68de7e8db66409af835838c5bb2c605111108a3bf13606ed5d8ade5ed72e50503e0de664416393d178ea4eec834d8d6f15039847b410080fd5529b426e5aadd8451c20ebd92d787921f33e147bcbeb327b104d4aab1157fc1df33e4d768404b5ccb7110055c2508c600f429fd0c21b5784
+d = a24d0fe90808aecc5d90626d7e6da7c9be5dfd4e1233c7f0f71f1b7c1c6fd318fafe18559c94718f044cf02ed5107cb1
+Qx = ec8ae1fb9bb88589d27d6f27d790392853396f37bc0c381631d85800fc668eea0886bf1c6cff801147df19778d5b1604
+Qy = 1e1a8336c1e2506f8ee388b55cc648ae73b9295ea78467979d2affb364536fad28120f51ec62a67cbb6ce7784780389f
+k = 755d025509b73cf1ea8817beb772ad150b4c17a52378be187daffe3db0158921e5e552d1ca3c85df28519939f3cb794d
+R = 23ff2ffa62bbd427d49995d9c9950116e0d5a06ef076a4553448bc109e6482c5e87d4c833bc88de0bc722bc98cae2e61
+S = 9aea13d487c3ea6917e16374caafcf0321c12a80d28902dd8cd81909bb04b8c439e2491e504756742d0d0bfb15a9c34c
+
+Msg = 3cd8c053741dd9f974c6c5dbf8a1e5728e9b5eafb1cbcfc3452f5fbbda32a8c7564dee157e8d902c52514361da6d972934a56b3276e2a9379e328e24282e0db697c5bc29090fc489ec46b7b188325dd4e96494c250de0f4a89fe2ccf919eaefcfb50c288113e6df92714feb7f46e0822478c796d0f4ff3447a32997e892693ce
+d = 1c172e25732555afee7ded67a496f3f11babc0875898619f4519c29321e201e8ba1149f2c20b48e5efba235d58fea7c3
+Qx = 13e9e2c8bbcfe26e8f5f43c86268c5980ee693236a6b8777f3a7323718baa21005b482d08aafc6fa6e3667d91353544c
+Qy = 9ba181b3ee505be030f87ecd249b00670a791489b42af04976013483ff95b630c91c01e95757e906129f2f9b4ce719a8
+k = 08aec9a9e58bdc028805eb5dc86073d05fff1f5fb3fd17f510fc08f9272d84ba7aa66b6f77d84fe6360bd538192bf01a
+R = 2b4337c3dfbc886ffad7858ae2480cb62227e12205a70361c42f1a5ca9e658ee30fc3cf4030d85bd065edad83b99821f
+S = 2550cef8574bf17fb3d6b0c9d04ab266962bac3621bac233ff2e4989712d2a4a07171c0aebd3040cd6a32c3bd3efb8b5
+
+Msg = ed955dda6d9650124804d3deb6aeef900e520faf98b1ef6f14efcada7ca2433f09329b70897305e59c89024d76e466b28fe02cb2a9b12e2478c66470259d7c282137a19e5a04ffadea55245c0f34a681593fedc42931d8b3321b3d82e9cc102cd00540ad311ec7bd8c9d06db21bea4ca3dc74d98931ae0d40494aefc2345132c
+d = 5b96555dbd602e71d4d5d3aee19fd1ea084ee23d4f55c10937056762bc2015cbded2e898a487f5482ab7e1e971245907
+Qx = 6e14c17bb831b0112d7f3543c5fd17c78379a516c9e0539b03b8b4bfdead2820343fc84b0382807573ded6c4d97b7003
+Qy = 7f60021d2de77546db666721c9aec84c3e2ba8de0ba77443600dc77e6839bbf9316271adb22d4cb47d08f745ecb1dafd
+k = 7ad6f4ffd2b429ba10c6f112f800cacf1ad508cf8eba880893bb9659c1ddaaec57dcdc093a114500460d457bdde324f2
+R = faea950ca513806bc59028c638d6302ffc86978c3ff1f06db015dd7c4777050186cb8dd871f5e926e1416539c1939c2f
+S = 2c592240eabb8a1f9878e1b5c9d5d3ced7b3a7ae571f5a86494ed2ca567a36eb72e7bea8934bded29594bccf67ca84bd
+
+Msg = ce395b001da2a58e49691605d44af4206306f62f561bf2394060d2a5591a350277166bed043819035f1e60b5b3fb5ae113ddd0473f8ef6b2b050c472c2a264e1d8b3ca82a4f158c40f2d78d9ce5e5ea6de243f2e1f13f47f6c6f403b270912c81c636be35b396ca58468b3fb60aa83911d61441a0528d973bc31f965d4059080
+d = 8df9c3c710a25192f3dea970910bb3784e3509874cccf4334823eb9f7a8d05b067f2d812d61e878e24b093089a0b8245
+Qx = 92c9e32b20cbe6d4ed0727c6c942cf804a72031d6dfd69078b5e78ebce2d192268f1f5e2abce5aaf1f8d6a35f136837f
+Qy = d5167905fa7689e03b9fb1487c566f62b36f2bc1c4a2bfb6a836113b5c8d46f7c1ca51b628b14397fbc06ec9a07f4849
+k = 258dd05919735cd48627c9fe9fac5c252604aa7c2ae0460d7c1149cd96b7bd2ba195ad393bf392a2499f06aead5ba050
+R = 413793bcce52eda0f5b675a8d687cce86d5c9e1659b38a89e96246b5e05f8b0934d17dbba3b2ea44c838aa5fd87125d1
+S = ce7309fc2d6e3438818a1a29a997410b025b0403de20795b97c86c46034a6b02afeed279aeb06522d4de941bfdf50469
+
+Msg = ffefe316455ae4ffdb890bb804bf7d31424ea060ecacff419d0f7134ff76ad434063c0ec0f8bb7059584d3a03f3625bb9e9f66ace1a47ac4b8f3e76fc7c420c55edb1427d1fa15b387ad73d02b0595c4e74321be8822752230a0dcfb85d60bfa186da7623a8ec3eb1633f0a294b23ae87216b14ccee9ef56418dcfab9427371e
+d = 6002cb01ad2ce6e7101665d47729c863b6435c3875de57a93f99da834f73e3e6e2b3880e06de3e6bd1d51ea1807ab0d7
+Qx = e4216e1a20af8e8e3e74653ac016545001066e53e64af679ad1c85841bb475aed3e00ead052ae9955f48d675ff4ace56
+Qy = 8804c17641be21d4c6386902c9c5c888af25d97ca383703ea4a85cf93bbab360c0bbd2993374da499a303778650270b9
+k = 6b9507fd2844df0949f8b67b6fde986e50173713ac03df2edf65cb339859321cd3a2b9aab8356f95dec62460ab19c822
+R = 018891f6381ed358b422f79a299cf0789cee783ba388af4d82cbbe17f3709751b7fd9400e9702820c28b9afc62fdf489
+S = aef73bd590802b2fd2a65c4f7fec89f9b24ecc199a69254785925f334cd1977c5e1f858bd9830d7d7d243ea707b1af0b
+
+Msg = 304bccb718b3a9e12669913490cc5bcc1979287b56c628fad706c354241e88d10e81445a2853e3fc32ece094ba1abc3fdcab61da27f9a0fca739371049fed462ee6b08fa31cde12720f8144a6f00ce9b1a7a6eadd231f126717074b4efb5c72ce673ca5859000a436f67a338d698759f12c461247c45a361fb6cb661fdbe6714
+d = d8559c3543afc6f7b3dc037a687bad2630283757ba7862fd23ed14e2151a4cf5fed3d249268f780e0b96b6b46274a2d5
+Qx = 5f94223918f2ec9f0a08342cb99e724881c92453957c59672860f69daac01b660331a0f5845e50f1f27766b219c89e7e
+Qy = d76d83396130d10d1168d76c7fc83742ffffbe66d9f4da4ca3f95f5ad6dac8cc7bb65d16d317d37aa99fdbf30ec7439c
+k = 4ad5a92b5b8e170b71c8a7ed419dc624c7680004562b8d16a37b6e639f581ce81d5f0d98cce44d54c4e7136229148340
+R = f7baa6a5488ab462ea59aa31a36402b15880c68110b6069f51ede0c3b52a7b1e5bf926fdbe95768931b7d5f87058835c
+S = 28b1c4ef448a432f7c91b98b0c6471691e888211b6af907369a8930859b8cdb2e94f466a44f4e52f46df9b0d65e35de6
+
+Msg = 64f9f05c2805acf59c047b5f5d2e20c39277b6d6380f70f87b72327a76170b872bfe4b25c451602acfb6a631bb885e2655aee8abe44f69c90fb21ffde03cef2a452c468c6369867dfd8aa26ac24e16aa53b292375a8d8fbf988e302bf00088e4c061aa12c421d8fe3cbd7273b0e8993701df1c59431f436a08b8e15bd123d133
+d = b9208cbfd186ddfa3efd5b71342ae1efb01a13ebc4c2a992a2cbee7254b7846a4252ece1104b89d13d835911f8511224
+Qx = 166e6d96cb60d916fd19888a2dd945a3306ff0d7b0a5e30729f47d3dac3de2be3fd5cd7437e9a80d6c48cf960d2d36f8
+Qy = e6b2b70f131092ae210f29cc6bad701318bddb31bddf921695855c6208941100d0cee5d10799f8b835afe3ea510e8229
+k = da706ab5f61531f2378b3c0a2b342108cd119eadaa88b859df64923bccfb0ec2393fd312826f65c15a6587d1d460015b
+R = d9124c42858080c62400e4d4d8136304e03d910cbe9b9b3487f4d27c7e0540a314d34bef8c850045c8746ca631c11c42
+S = bbf6424a3b70166fa799f49e918439d515327039258ef9bd88435a59c9c19659f8ec3c8660720b0c08354ff60e0f5a76
+
+[P-384,SHA-384]
+
+Msg = 6b45d88037392e1371d9fd1cd174e9c1838d11c3d6133dc17e65fa0c485dcca9f52d41b60161246039e42ec784d49400bffdb51459f5de654091301a09378f93464d52118b48d44b30d781eb1dbed09da11fb4c818dbd442d161aba4b9edc79f05e4b7e401651395b53bd8b5bd3f2aaa6a00877fa9b45cadb8e648550b4c6cbe
+d = 201b432d8df14324182d6261db3e4b3f46a8284482d52e370da41e6cbdf45ec2952f5db7ccbce3bc29449f4fb080ac97
+Qx = c2b47944fb5de342d03285880177ca5f7d0f2fcad7678cce4229d6e1932fcac11bfc3c3e97d942a3c56bf34123013dbf
+Qy = 37257906a8223866eda0743c519616a76a758ae58aee81c5fd35fbf3a855b7754a36d4a0672df95d6c44a81cf7620c2d
+k = dcedabf85978e090f733c6e16646fa34df9ded6e5ce28c6676a00f58a25283db8885e16ce5bf97f917c81e1f25c9c771
+R = 50835a9251bad008106177ef004b091a1e4235cd0da84fff54542b0ed755c1d6f251609d14ecf18f9e1ddfe69b946e32
+S = 0475f3d30c6463b646e8d3bf2455830314611cbde404be518b14464fdb195fdcc92eb222e61f426a4a592c00a6a89721
+
+Msg = d768f41e6e8ec2125d6cf5786d1ba96668ac6566c5cdbbe407f7f2051f3ad6b1acdbfe13edf0d0a86fa110f405406b69085219b5a234ebdb93153241f785d45811b3540d1c37424cc7194424787a51b79679266484c787fb1ded6d1a26b9567d5ea68f04be416caf3be9bd2cafa208fe2a9e234d3ae557c65d3fe6da4cb48da4
+d = 23d9f4ea6d87b7d6163d64256e3449255db14786401a51daa7847161bf56d494325ad2ac8ba928394e01061d882c3528
+Qx = 5d42d6301c54a438f65970bae2a098cbc567e98840006e356221966c86d82e8eca515bca850eaa3cd41f175f03a0cbfd
+Qy = 4aef5a0ceece95d382bd70ab5ce1cb77408bae42b51a08816d5e5e1d3da8c18fcc95564a752730b0aabea983ccea4e2e
+k = 67ba379366049008593eac124f59ab017358892ee0c063d38f3758bb849fd25d867c3561563cac1532a323b228dc0890
+R = fb318f4cb1276282bb43f733a7fb7c567ce94f4d02924fc758635ab2d1107108bf159b85db080cdc3b30fbb5400016f3
+S = 588e3d7af5da03eae255ecb1813100d95edc243476b724b22db8e85377660d7645ddc1c2c2ee4eaea8b683dbe22f86ca
+
+Msg = 6af6652e92a17b7898e40b6776fabaf0d74cf88d8f0ebfa6088309cbe09fac472eeac2aa8ea96b8c12e993d14c93f8ef4e8b547afe7ae5e4f3973170b35deb3239898918c70c1056332c3f894cd643d2d9b93c2561aac069577bbab45803250a31cd62226cab94d8cba7261dce9fe88c210c212b54329d76a273522c8ba91ddf
+d = b5f670e98d8befc46f6f51fb2997069550c2a52ebfb4e5e25dd905352d9ef89eed5c2ecd16521853aadb1b52b8c42ae6
+Qx = 44ffb2a3a95e12d87c72b5ea0a8a7cb89f56b3bd46342b2303608d7216301c21b5d2921d80b6628dc512ccb84e2fc278
+Qy = e4c1002f1828abaec768cadcb7cf42fbf93b1709ccae6df5b134c41fae2b9a188bfbe1eccff0bd348517d7227f2071a6
+k = 229e67638f712f57bea4c2b02279d5ccad1e7c9e201c77f6f01aeb81ea90e62b44b2d2107fd66d35e56608fff65e28e4
+R = b11db592e4ebc75b6472b879b1d8ce57452c615aef20f67a280f8bca9b11a30ad4ac9d69541258c7dd5d0b4ab8dd7d49
+S = 4eb51db8004e46d438359abf060a9444616cb46b4f99c9a05b53ba6df02e914c9c0b6cc3a9791d804d2e4c0984dab1cc
+
+Msg = b96d74b2265dd895d94e25092fb9262dc4f2f7a328a3c0c3da134b2d0a4e2058ca994e3445c5ff4f812738e1b0c0f7a126486942a12e674a21f22d0886d68df2375f41685d694d487a718024933a7c4306f33f1a4267d469c530b0fed4e7dea520a19dd68bf0203cc87cad652260ed43b7b23f6ed140d3085875190191a0381a
+d = de5975d8932533f092e76295ed6b23f10fc5fba48bfb82c6cc714826baf0126813247f8bd51d5738503654ab22459976
+Qx = f1fabafc01fec7e96d982528d9ef3a2a18b7fe8ae0fa0673977341c7ae4ae8d8d3d67420343d013a984f5f61da29ae38
+Qy = 1a31cf902c46343d01b2ebb614bc789c313b5f91f9302ad9418e9c797563e2fa3d44500f47b4e26ad8fdec1a816d1dcf
+k = fc5940e661542436f9265c34bce407eff6364bd471aa79b90c906d923e15c9ed96eea4e86f3238ea86161d13b7d9359d
+R = c2fbdd6a56789024082173725d797ef9fd6accb6ae664b7260f9e83cb8ab2490428c8b9c52e153612295432fec4d59cd
+S = 8056c5bb57f41f73082888b234fcda320a33250b5da012ba1fdb4924355ae679012d81d2c08fc0f8634c708a4833232f
+
+Msg = 7cec7480a037ff40c232c1d2d6e8cd4c080bbeecdaf3886fccc9f129bb6d202c316eca76c8ad4e76079afe622f833a16f4907e817260c1fa68b10c7a151a37eb8c036b057ed4652c353db4b4a34b37c9a2b300fb5f5fcfb8aa8adae13db359160f70a9241546140e550af0073468683377e6771b6508327408c245d78911c2cc
+d = 11e0d470dc31fab0f5722f87b74a6c8d7414115e58ceb38bfcdced367beac3adbf1fe9ba5a04f72e978b1eb54597eabc
+Qx = 1950166989164cbfd97968c7e8adb6fbca1873ebef811ea259eb48b7d584627f0e6d6c64defe23cbc95236505a252aa1
+Qy = 41ef424b5cb076d4e32accd9250ea75fcf4ffd81814040c050d58c0a29b06be11edf67c911b403e418b7277417e52906
+k = e56904028226eb04f8d071e3f9cefec91075a81ca0fa87b44cae148fe1ce9827b5d1910db2336d0eb9813ddba3e4d7b5
+R = c38ef30f55624e8935680c29f8c24824877cf48ffc0ef015e62de1068893353030d1193bf9d34237d7ce6ba92c98b0fe
+S = 651b8c3d5c9d5b936d300802a06d82ad54f7b1ba4327b2f031c0c5b0cb215ad4354edc7f932d934e877dfa1cf51b13fe
+
+Msg = 00ce978603229710345c9ad7c1c2dba3596b196528eea25bd822d43ca8f76a024e29217703dd0652c8a615284fc3edcc1c5ad1c8d5a8521c8e104c016a24e50c2e25066dcb56596f913b872767e3627aa3e55ec812e9fdac7c2f1beade83aef093e24c9c953982adf431a776880ae4583be158e11cdab1cbca3ad3a66900213d
+d = 5c6bbf9fbcbb7b97c9535f57b431ed1ccae1945b7e8a4f1b032016b07810bd24a9e20055c0e9306650df59ef7e2cd8c2
+Qx = 2e01c5b59e619e00b79060a1e8ef695472e23bf9a511fc3d5ed77a334a242557098e40972713732c5291c97adf9cf2cf
+Qy = 563e3fe4ad807e803b9e961b08da4dde4cea8925649da0d93221ce4cdceabc6a1db7612180a8c6bef3579c65539b97e9
+k = 03d23f1277b949cb6380211ad9d338e6f76c3eedac95989b91d0243cfb734a54b19bca45a5d13d6a4b9f815d919eea77
+R = abab65308f0b79c4f3a9ff28dd490acb0c320434094cef93e75adfe17e5820dc1f77544cfaaacdc8cf9ac8b38e174bef
+S = 11b783d879a6de054b316af7d56e526c3dce96c85289122e3ad927cfa77bfc50b4a96c97f85b1b8221be2df083ff58fb
+
+Msg = 54a255c18692c6162a46add176a0ae8361dcb8948f092d8d7bac83e160431794d3b9812849bf1994bcdcfba56e8540c8a9ee5b93414548f2a653191b6bb28bda8dc70d45cc1b92a489f58a2d54f85766cb3c90de7dd88e690d8ebc9a79987eee1989df35af5e35522f83d85c48dda89863171c8b0bf4853ae28c2ac45c764416
+d = ffc7dedeff8343721f72046bc3c126626c177b0e48e247f44fd61f8469d4d5f0a74147fabaa334495cc1f986ebc5f0b1
+Qx = 51c78c979452edd53b563f63eb3e854a5b23e87f1b2103942b65f77d024471f75c8ce1cc0dfef83292b368112aa5126e
+Qy = 313e6aaf09caa3ba30f13072b2134878f14a4a01ee86326cccbff3d079b4df097dc57985e8c8c834a10cb9d766169366
+k = c3de91dbe4f777698773da70dd610ef1a7efe4dc00d734399c7dd100728006a502822a5a7ff9129ffd8adf6c1fc1211a
+R = f4f477855819ad8b1763f53691b76afbc4a31a638b1e08c293f9bcd55decf797f9913ca128d4b45b2e2ea3e82c6cf565
+S = 7c26be29569ef95480a6d0c1af49dc10a51a0a8931345e48c0c39498bfb94d62962980b56143a7b41a2fddc8794c1b7f
+
+Msg = 692a78f90d4f9d5aee5da536314a78d68c1feabbfe5d1ccea7f6059a66c4b310f8051c411c409ccf6e19a0cbd8b8e100c48317fe8c6d4f8a638b9551ce7ee178020f04f7da3001a0e6855225fb3c9b375e4ed964588a1a41a095f3f476c42d52ffd23ce1702c93b56d4425d3befcf75d0951b6fd5c05b05455bdaf205fe70ca2
+d = adca364ef144a21df64b163615e8349cf74ee9dbf728104215c532073a7f74e2f67385779f7f74ab344cc3c7da061cf6
+Qx = ef948daae68242330a7358ef73f23b56c07e37126266db3fa6eea233a04a9b3e4915233dd6754427cd4b71b75854077d
+Qy = 009453ef1828eaff9e17c856d4fc1895ab60051312c3e1db1e3766566438b2990cbf9945c2545619e3e0145bc6a79004
+k = a2da3fae2e6da3cf11b49861afb34fba357fea89f54b35ce5ed7434ae09103fe53e2be75b93fc579fedf919f6d5e407e
+R = dda994b9c428b57e9f8bbaebba0d682e3aac6ed828e3a1e99a7fc4c804bff8df151137f539c7389d80e23d9f3ee497bf
+S = a0d6b10ceffd0e1b29cf784476f9173ba6ecd2cfc7929725f2d6e24e0db5a4721683640eaa2bbe151fb57560f9ce594b
+
+Msg = 3b309bb912ab2a51681451ed18ad79e95d968abc35423a67036a02af92f575a0c89f1b668afe22c7037ad1199e757a8f06b281c33e9a40bab69c9874e0bb680b905d909b9dc24a9fe89bb3d7f7d47082b25093c59754f8c19d1f81f30334a8cdd50a3cb72f96d4b3c305e60a439a7e93aeb640dd3c8de37d63c60fb469c2d3ed
+d = 39bea008ec8a217866dcbdb1b93da34d1d3e851d011df9ef44b7828b3453a54aa70f1df9932170804eacd207e4f7e91d
+Qx = 5709ec4305a9c3271c304face6c148142490b827a73a4c17affcfd01fffd7eaa65d2fdedfa2419fc64ed910823513faf
+Qy = b083cda1cf3be6371b6c06e729ea6299213428db57119347247ec1fcd44204386cc0bca3f452d9d864b39efbfc89d6b2
+k = 3c90cc7b6984056f570542a51cbe497ce4c11aeae8fc35e8fd6a0d9adeb650e8644f9d1d5e4341b5adc81e27f284c08f
+R = d13646895afb1bfd1953551bb922809c95ad65d6abe94eb3719c899aa1f6dba6b01222c7f283900fe98628b7597b6ea6
+S = 4a9a38afda04c0a6b0058943b679bd02205b14d0f3d49b8f31aac289129780cdb1c555def8c3f9106b478729e0c7efaa
+
+Msg = f072b72b8783289463da118613c43824d11441dba364c289de03ff5fab3a6f60e85957d8ff211f1cb62fa90216fb727106f692e5ae0844b11b710e5a12c69df3ed895b94e8769ecd15ff433762d6e8e94d8e6a72645b213b0231344e2c968056766c5dd6b5a5df41971858b85e99afbf859400f839b42cd129068efabeea4a26
+d = e849cf948b241362e3e20c458b52df044f2a72deb0f41c1bb0673e7c04cdd70811215059032b5ca3cc69c345dcce4cf7
+Qx = 06c037a0cbf43fdf335dff33de06d34348405353f9fdf2ce1361efba30fb204aea9dbd2e30da0a10fd2d876188371be6
+Qy = 360d38f3940e34679204b98fbf70b8a4d97f25443e46d0807ab634ed5891ad864dd7703557aa933cd380e26eea662a43
+k = 32386b2593c85e877b70e5e5495936f65dc49553caef1aa6cc14d9cd370c442a0ccfab4c0da9ec311b67913b1b575a9d
+R = 5886078d3495767e330c7507b7ca0fa07a50e59912a416d89f0ab1aa4e88153d6eaf00882d1b4aa64153153352d853b5
+S = 2cc10023bf1bf8ccfd14b06b82cc2114449a352389c8ff9f6f78cdc4e32bde69f3869da0e17f691b329682ae7a36e1aa
+
+Msg = cf4945350be8133b575c4ad6c9585e0b83ff1ed17989b6cd6c71b41b5264e828b4e115995b1ae77528e7e9002ac1b5669064442645929f9d7dd70927cb93f95edeb73e8624f4bc897ec4c2c7581cb626916f29b2d6e6c2fba8c59a71e30754b459d81b912a12798182bcff4019c7bdfe929cc769bcc2414befe7d2906add4271
+d = d89607475d509ef23dc9f476eae4280c986de741b63560670fa2bd605f5049f1972792c0413a5b3b4b34e7a38b70b7ca
+Qx = 49a1c631f31cf5c45b2676b1f130cbf9be683d0a50dffae0d147c1e9913ab1090c6529a84f47ddc7cf025921b771355a
+Qy = 1e207eece62f2bcc6bdabc1113158145170be97469a2904eaaa93aad85b86a19719207f3e423051f5b9cbbe2754eefcb
+k = 78613c570c8d33b7dd1bd1561d87e36282e8cf4843e7c344a2b2bb6a0da94756d670eeaffe434f7ae7c780f7cf05ca08
+R = 66f92b39aa3f4aeb9e2dc03ac3855406fa3ebbab0a6c88a78d7a03482f0c9868d7b78bc081ede0947c7f37bf193074ba
+S = e5c64ed98d7f3701193f25dd237d59c91c0da6e26215e0889d82e6d3e416693f8d58843cf30ab10ab8d0edd9170b53ad
+
+Msg = d9b5cf0b50416573ff3c63133275a18394dd4326be2041e8d97e6e4e3855a4a177e9d26dfd223fe8aa74564edb49bd72de19916fb6f001f44530d5c18e2c332bce1b7415df5927ece5f3824f34d174b963136b53aef1fb78fb0c06a201a40b2db38e4d8216fc1e392a798c8ab4b3a314496b7f1087804ebfa89bf96e9cdb80c0
+d = 083e7152734adf342520ae377087a223688de2899b10cfcb34a0b36bca500a4dfa530e2343e6a39da7ae1eb0862b4a0d
+Qx = 70a0f16b6c61172659b027ed19b18fd8f57bd28dc0501f207bd6b0bb065b5671cf3dd1ed13d388dcf6ccc766597aa604
+Qy = 4f845bf01c3c3f6126a7368c3454f51425801ee0b72e63fb6799b4420bfdebe3e37c7246db627cc82c09654979c700bb
+k = 28096ababe29a075fbdf894709a20d0fdedb01ed3eeacb642a33a0da6aed726e13caf6cf206792ec359f0c9f9b567552
+R = ee2923f9b9999ea05b5e57f505bed5c6ba0420def42c6fa90eef7a6ef770786525546de27cdeb2f8586f8f29fb4ee67c
+S = 50ef923fb217c4cf65a48b94412fda430fac685f0da7bd574557c6c50f5b22e0c8354d99f2c2f2c2691f252f93c7d84a
+
+Msg = 9e4042d8438a405475b7dab1cd783eb6ce1d1bffa46ac9dfda622b23ac31057b922eced8e2ed7b3241efeafd7c9ab372bf16230f7134647f2956fb793989d3c885a5ae064e85ed971b64f5f561e7ddb79d49aa6ebe727c671c67879b794554c04de0e05d68264855745ef3c9567bd646d5c5f8728b797c181b6b6a876e167663
+d = 63578d416215aff2cc78f9b926d4c7740a77c142944e104aa7422b19a616898262d46a8a942d5e8d5db135ee8b09a368
+Qx = cadbacef4406099316db2ce3206adc636c2bb0a835847ed7941efb02862472f3150338f13f4860d47f39b7e098f0a390
+Qy = 752ad0f22c9c264336cde11bbc95d1816ed4d1b1500db6b8dce259a42832e613c31178c2c7995206a62e201ba108f570
+k = 7b69c5d5b4d05c9950dc94c27d58403b4c52c004b80a80418ad3a89aabc5d34f21926729e76afd280cc8ee88c9805a2a
+R = db054addb6161ee49c6ce2e4d646d7670754747b6737ca8516e9d1e87859937c3ef9b1d2663e10d7e4bd00ec85b7a97a
+S = fcc504e0f00ef29587e4bc22faada4db30e2cb1ac552680a65785ae87beb666c792513f2be7a3180fc544296841a0e27
+
+Msg = 0b14a7484a40b68a3ce1273b8a48b8fdb65ba900d98541c4bbd07b97e31bcc4c85545a03e9deab3c563f47a036ff60d0361684ba241b5aa68bb46f440da22181ee328a011de98eff34ba235ec10612b07bdfa6b3dc4ccc5e82d3a8d057e1862fef3def5a1804696f84699fda2ec4175a54a4d08bcb4f0406fdac4eddadf5e29b
+d = ed4df19971658b74868800b3b81bc877807743b25c65740f1d6377542afe2c6427612c840ada31a8eb794718f37c7283
+Qx = 33093a0568757e8b58df5b72ea5fe5bf26e6f7aeb541b4c6a8c189c93721749bcaceccf2982a2f0702586a9f812fc66f
+Qy = ebe320d09e1f0662189d50b85a20403b821ac0d000afdbf66a0a33f304726c69e354d81c50b94ba3a5250efc31319cd1
+k = d9b4cd1bdfa83e608289634dbfcee643f07315baf743fc91922880b55a2feda3b38ddf6040d3ba10985cd1285fc690d5
+R = 009c74063e206a4259b53decff5445683a03f44fa67252b76bd3581081c714f882f882df915e97dbeab061fa8b3cc4e7
+S = d40e09d3468b46699948007e8f59845766dbf694b9c62066890dd055c0cb9a0caf0aa611fb9f466ad0bbb00dbe29d7eb
+
+Msg = 0e646c6c3cc0f9fdedef934b7195fe3837836a9f6f263968af95ef84cd035750f3cdb649de745c874a6ef66b3dd83b66068b4335bc0a97184182e3965c722b3b1aee488c3620adb835a8140e199f4fc83a88b02881816b366a09316e25685217f9221157fc05b2d8d2bc855372183da7af3f0a14148a09def37a332f8eb40dc9
+d = e9c7e9a79618d6ff3274da1abd0ff3ed0ec1ae3b54c3a4fd8d68d98fb04326b7633fc637e0b195228d0edba6bb1468fb
+Qx = a39ac353ca787982c577aff1e8601ce192aa90fd0de4c0ed627f66a8b6f02ae51315543f72ffc1c48a7269b25e7c289a
+Qy = 9064a507b66b340b6e0e0d5ffaa67dd20e6dafc0ea6a6faee1635177af256f9108a22e9edf736ab4ae8e96dc207b1fa9
+k = b094cb3a5c1440cfab9dc56d0ec2eff00f2110dea203654c70757254aa5912a7e73972e607459b1f4861e0b08a5cc763
+R = ee82c0f90501136eb0dc0e459ad17bf3be1b1c8b8d05c60068a9306a346326ff7344776a95f1f7e2e2cf9477130e735c
+S = af10b90f203af23b7500e070536e64629ba19245d6ef39aab57fcdb1b73c4c6bf7070c6263544633d3d358c12a178138
+
+[P-384,SHA-512]
+
+Msg = 67d9eb88f289454d61def4764d1573db49b875cfb11e139d7eacc4b7a79d3db3bf7208191b2b2078cbbcc974ec0da1ed5e0c10ec37f6181bf81c0f32972a125df64e3b3e1d838ec7da8dfe0b7fcc911e43159a79c73df5fa252b98790be511d8a732fcbf011aacc7d45d8027d50a347703d613ceda09f650c6104c9459537c8f
+d = 217afba406d8ab32ee07b0f27eef789fc201d121ffab76c8fbe3c2d352c594909abe591c6f86233992362c9d631baf7c
+Qx = fb937e4a303617b71b6c1a25f2ac786087328a3e26bdef55e52d46ab5e69e5411bf9fc55f5df9994d2bf82e8f39a153e
+Qy = a97d9075e92fa5bfe67e6ec18e21cc4d11fde59a68aef72c0e46a28f31a9d60385f41f39da468f4e6c3d3fbac9046765
+k = 90338a7f6ffce541366ca2987c3b3ca527992d1efcf1dd2723fbd241a24cff19990f2af5fd6419ed2104b4a59b5ae631
+R = c269d9c4619aafdf5f4b3100211dddb14693abe25551e04f9499c91152a296d7449c08b36f87d1e16e8e15fee4a7f5c8
+S = 77ffed5c61665152d52161dc13ac3fbae5786928a3d736f42d34a9e4d6d4a70a02d5af90fa37a23a318902ae2656c071
+
+Msg = 45db86829c363c80160659e3c5c7d7971abb1f6f0d495709bba908d7aa99c9df64b3408a51bd69aba8870e2aaff488ef138f3123cf94391d081f357e21906a4e2f311defe527c55e0231579957c51def507f835cceb466eb2593a509dcbee2f09e0dde6693b2bfe17697c9e86dd672f5797339cbe9ea8a7c6309b061eca7aef5
+d = 0a3f45a28a355381a919372f60320d6610cfb69c3e318eb1607db3cadfc42b728b77a6a9e9e333de9183c58933daf60f
+Qx = 832cbb7061a719a316e73dbad348fa67cd17c33f40b9000a3d3b691a2a2cd821052566717c3ead01089b56086af1366f
+Qy = 1e15a048d1dce642d9ebcbfac7f92b1bcee90fd0240cc79abd29e32e0e655c4ee1fd34fb88178bba92aca100e7794ed0
+k = 2a78e651623ba604c42cf094fc7d046629306f508853427ba091448800d1092c041bb2323035fc9d19a8d44950f7dcc3
+R = 0db0cc9a2bda8dd7e565ad36f91b1c5756d78164dc8a72a5bee4b6bc45ea38c7a16b01d05b1893d4e06b62db24c30385
+S = abd383edaeda7d0b8de1b54fcd3c28874fed62ab266f1f84c8ba796a7b54e5e0695fdb43ce7fe90ed00fa468d87bca64
+
+Msg = 4672fce0721d37c5be166bffa4b30d753bcf104b9b414db994b3ed33f36af4935ea59a0bb92db66448b3f57dad4fc67cef10ce141bf82c536be604b89a0bc0e8bca605b867880049d97142d30538fc543bd9d4fab7fdbe2f703815cdb6361beb66acff764bc275f910d1662445b07b92830db69a5994857f53657ed5ca282648
+d = 2e408c57921939f0e0fe2e80ce74a4fa4a1b4fa7ab070206298fe894d655be50e2583af9e45544b5d69c73dce8a2c8e7
+Qx = a2b24a5ad4a2e91f12199ed7699e3f297e27bf8b8ea8fbe7ed28366f3544cd8e680c238450f8a6422b40829d6647b25c
+Qy = 2732be0075536e6519f6a099b975a40f8e0de337fa4d48bd0762b43f41cab8deafdef9cfbb9973e457801e3bf9c93304
+k = b10b6258afdde81f9c971cc1526d942e20cafac02f59fee10f98e99b8674636bff1d84a6eaa49c0de8d8cfdc90d8ce84
+R = be428a8de89a364a134719141ee8d776a3a8338f1132b07e01b28573d8eaf3b9008b63304c48821e53638b6141f9660b
+S = 866181dbef5c147d391bed6adcee408c339982c307adc718c2b9ab9e5642d8dedc36dd6402559a3ab614c99c1e56b529
+
+Msg = 9ae48fdd9bfc5cb0f4d4761e28b2073bda05a3e3fe82c212e66701dc4573cc67a829b0f82d7520b1bf11db0c6d1743822bbe41bb0adbd7222aa5fae70fbd1a31f2d4453a01c81e064d775388468be96f6063f8673b7b8d4455fe1bd4c801ad5e625a015eaa4a1a18da490d2af8642201eaba3c611cbd65f861d8e19ca82a1ee6
+d = 1c285da72a8eb1c3c38faab8d3bb4e68dc95c797082b9a3991a21c1de54759071ecf2265fb1eff504ab24174bc6710cf
+Qx = 11acb1b5cc59a4f1df1913a8d6e91cbdafb8206dc44aff7d9da45906b664fc33194d9935a82aa4d62f39618897c86025
+Qy = 832ed0b9575fff52a3603bfe89f312751b4c396da98324117a61b3f525d27b2266f6cfb22be07e50b6874435e380ed62
+k = 2513075e02cc7fb3cff7b7adde46da31c5493749b5cf02758bd5b098a838bfd4d5e4c7fb8268bdc37e219c30efebe878
+R = b3d638b3be45f14f170da5bdc22d2114deac93ab340a25b3af2b5c18584bb9147e00dc6c67a2274f79aa4838793eb63f
+S = 876112bdca2c725eb2f6dbd76d07710a31f0c16d38430cb0817f320a25a9ecfec8a66137d0304612ae29a6a484fd3319
+
+Msg = 817d6a110a8fd0ca7b4d565558f68b59a156744d4c5aac5c6610c95451793de2a756f774558c61d21818d3ebeeeb71d132da1c23a02f4b305eccc5cd46bd21dfc173a8a91098354f10ffbb21bf63d9f4c3feb231c736504549a78fd76d39f3ad35c36178f5c233742d2917d5611d2073124845f1e3615b2ef25199a7a547e882
+d = 9da37e104938019fbdcf247e3df879a282c45f8fb57e6655e36b47723af42bec3b820f660436deb3de123a21de0ca37b
+Qx = 722d0ea6891d509b18b85ca56f74deb5c3030d2a30433824123d430d03c99279572c3b28ecf01e747b9db8acc55d0ba3
+Qy = 7e2605ea7092214f366f3639037bffd89fe103c646e990839d3a1ced8d78edb5b9bc60d834fd8e2a3c17e920bdae023a
+k = c8c18e53a9aa5915288c33132bd09323638f7995cd89162073984ed84e72e07a37e18c4c023933eace92c35d10e6b1b6
+R = 6512a8a2be731e301dcf4803764297862bbfa0ac8daed64d8e98b34618ecb20520fc5d3cf890b7783edf86e7ea407541
+S = 4ff10301f7b4168fae066361376007c1d7aa89a75c87719d0b54711ffef5ef3726f3eef84f7ebc025c110bde511b17f6
+
+Msg = 464f10ec6fb229a51db5fd0e122f2cb8a9a022117e2987f4007bf5565b2c16aba0714e2e3cdd0c100d55ac3017e36fc7501ad8309ab9572aa65424c9eb2e580a119c55777676ec498df53ef6ae78fd8a988130ee0e6082bf1ef71cd4c946021018a8ca7154d13b174c638912613b0bdb9001c302bf7e443ad2124ab2c1cce212
+d = 0661ab3bf9f7bef51bec7dff758de289154557beb9ce18cc4b8cc09a871e8322af259cf188b593dc62f03a19e75f7f69
+Qx = b4f100558043858efa728082d9b99ad5192b59b0947434f5ba7ff2514508a6d71ba54e7221c31cb0712103272b3f6fa4
+Qy = 34f6df4eeb2da11498044635067c2715ed15ae251c78ffb9030d87909ea8539b66394e93109ca54c0406cf99960c3e93
+k = 84a87137edb6894f96c5a8e94a3765162034feb84dfea94e1c71411170c285a80321ec7999e25861844143209804882c
+R = 4dc9d1b949b36e3c3847ac1c7ed114e1bc9cbe76119cf6fcd3f1b69ee6ee54e3255f1bb288fe2f8bd6d4049a21793c27
+S = 56a561d647b62ccae1e6df818b1a6fbde66c82ef0ff69ee415f183e7daf76be22630c7e02cd3fd729dfa490f26824584
+
+Msg = 4e3e0fb96320ddccde8b463c273654c4f7164920b1d63430921d2e808dee403e6420eedda0a557b911d00736a4f8798dd4ef26673efd6d190988ad4929ec64f8685cfb76070a36cd6a3a4bf2f54fb08a349d44642b6f614043fef9b2813b63457c76537d23da7b37310334f7ba76edf1999dad86f72aa3446445a65952ac4e50
+d = 66e7cfdeb7f264cf786e35210f458c32223c3a12a3bc4b63d53a5776bc9b069928452484f6241caa3781fd1a4109d4db
+Qx = 3c7682de540ab231daf21bf9fc80bda6abf7e17dcc79d476c7b7c3bd4d42d386877fd8ba495c1b0333e04fb5fd2a1505
+Qy = 0a1582e4f4d72abea9d3476aff8369c41261f0c5dddf2ca82e10f7a163f73df09473d9e5e2552187104e4cc7c6d83611
+k = 2fa266f5cce190eb77614933ca6a55121ad8bae168ff7a9043d96d13b5ca2fe70101ff9fe1e2b2cd7413e6aa8f49abde
+R = e7ecda9da0c52d0474a9f70094dc8f061d7d6a22210d3b69a7be8f389aa666f256322099b87d16ad35357ea856574dba
+S = ba348eb40a2830ec5a1130264ac0a8675420b1ae243e808a778135809ece21f42c0c881166321102b4f02df4c5c7ed9d
+
+Msg = c466b6b6baf7e6ffa876ec06105e2d43534e0517c07b1c4c9fb67ba81ce09525a7721ec3c290f2b1f65b6463d41598e7a25b2238501629953a5ca955b644354fb6856733a2e5bb8f5bc21a0c803493f5539f9fb83aab3dba2c982989c2270c61ab244b68bfe1b948d00c2ed975e09c29b5f8a7effcad8652a148cc880d503217
+d = 92c2f7ee64af86d003ab484e12b82fcf245fc330761057fec5b7af8f7e0a2d85b468c21d171460fcb829cae7b986316d
+Qx = ca43a306479bf8fb537d4b9ff9d635bbb2a0d60d9e854d5b7e269d09d91f78c6b90b616e4c931629453645a2bb371e14
+Qy = 356c4d7f10e690614eaf7f82ba0f9dc1aad98130c0ad9fe353deec565cc04bef789a0a4242322e0058b46cd02f2de77d
+k = 6ec81fb74f8725ba225f317264460ee300cfd2f02092000989acbdad4799cf55c244a65c557113328fe20282e6badb55
+R = cd7a4309bcebc25a8e10899fe2eda5f8b2dbcf329cd2f3d65befd67393e83fba2f8a67a15c01a6ac8314f9f5e87a9dca
+S = 6dcfc0426bc148e67e91d4784e3d7e9bc3b7ce3676be62daa7f3f55dfdff6d9dc735b5e3e0bbd0785db1f76f7ac065f3
+
+Msg = feac892b7720af80b3c9eede51e923f18d3d0c5de4c31f4aa75e36df7c7c2fd8f41778851a24b69e67dccb65e159dd5c383243bad7cfedcc5e85c8a01c34b0b94ba8e07e4c024c09d279b3731e8b62f9562d3c4f5042567efe42a9d0eaaabab28bc6f11232fc8ceaaf4518d9f3b2bebf020294496b7f6b879e69503f75fecd3d
+d = 15347caaad1067f1848a676bd0a8c52021ae604b79d02775a0459226e0391a3acd26653c916fcfe86149fb0ee0904476
+Qx = e5a0463163964d984f5bad0072d45bc2059939e60a826ccca36c151460ae360f5d6679f60fe43e999b6da5841c96e48a
+Qy = 30f2dd425a3fa2c95d34124217250b39e3b4a14f3e6e415ae8e5b0409eb72f43f78b64d0ce6f2d49980d6f04cd1391db
+k = 1a2d224db4bb9c241ca5cab18920fad615fa25c1db0de0f024cb3ace0d11ef72b056885446659f67650fdff692517b1c
+R = 87b4de0fb21df38dfc9a4b1e350da67547e307f55b5b9dd6615e408afe7c3553a6e02722847367439e636074faa2182b
+S = 375d965753b9ed6c6c08576726f8308c2f8dbd2737824464e71265d47907e26f615bbeb8203ec617520d4ecd1851dc44
+
+Msg = cf2982e3bf174ce547741b969403cd11e9553067e6af8177d89511a0eb040db924530bdba65d8b1ff714228db0737c1756f509e1506014a10736e65be2f91980a73891496e90ff2714a3601c7565cdcef5a395e2e0e1652f138d90d61eaa9cba993b823245647f6e07cec9b8b4449cd68a29741cd1579c66e548ca0d0acf33aa
+d = ac1cb5e59bda2eff3413a3bab80308f9fb32c595283c795de4c17fdae8d4647b5f108fd0801aee22adb7db129283b5aa
+Qx = bc6b1a718284803553c173089c397870aaaecca579bb8e81a8cfa12473cd2057567fa8726a19ed427cc035baeec2c551
+Qy = 14f82997d1129b669f0015350e47ad561b1b13441af4fb44656f15ed0c5706984d66655accc52f2e943eef39cb1cdc21
+k = 8053a46e875f446056b06d4318fa3e8977622de7207cbf0996bf35b0e9b19aaa507f642bcf0be9f048f1af09806f6946
+R = a994eb15b64114ce8a9342d18b5edda96a6d76314a5ac03da723699177d352a4a9f3b7121b11a91e43a6af4025da51d6
+S = 8183ae33a888e99aa76882da0a6705ad102f2bbd9572fad0d2e4d6d70151970469e00c5220e59c14724d771c1384b302
+
+Msg = bf9fdd4107ef5a6070108771ac9eee4f0c8043bf0d04db772a47294f4137e2439d94b337114b074e57e0cb78d0ccf352a2833e9788ee2a1a9ffeacd34f38fcefb86653d70c7dadd4cf6548d608e70acdef6c7530974b92c813798add659752a8c72b05e1ad9c65c21834ce6fbe49d8a1426b5a54270794436d284364fac6ec1a
+d = 205f1eb3dfacff2bdd8590e43e613b92512d6a415c5951bda7a6c37db3aae39b9b7ec6edd256609e75373419087fa71f
+Qx = c9f1f63a18c761b077a1ec35fbb2de635db9b8592c36194a01769b57728c7755d4c79b3d5b97a1a4631e30c86d03f13c
+Qy = f8c4a38770054d5cc9bb9182e6d4638242c4fd16e869ac22e44c4b9402d594e0c6f5df6a9a7de32a4893d9f6588f1950
+k = ecd395c5d8b7d6e6b2b19644e0d2e6086c912c6a0f5b8ed4b94b7290b65852c9741ce8eeb08d8751ead8a183e17d76c6
+R = e81331d78b438b0b8d98c1be03385ba5d614af182f1677f259126cc3de7eaac6c19b02be955d936b6bf9c27c6796e6f0
+S = 17c2b7a8e0fc93909762aa9f86f9561e759ecb88f02337b2018363be6095d9e4324a6d3296046686624b5efad6b52878
+
+Msg = 5d634fb39a2239256107dc68db19751540b4badac9ecf2fce644724401d6d632b3ae3b2e6d05746b77ddc0c899878032248c263eda08d3d004d35952ad7a9cfe19343d14b37f9f632245e7b7b5fae3cb31c5231f82b9f1884f2de7578fbf156c430257031ba97bc6579843bc7f59fcb9a6449a4cd942dffa6adb929cf219f0ad
+d = e21e3a739e7ded418df5d3e7bc2c4ae8da76266a1fc4c89e5b09923db80a72217f1e96158031be42914cf3ee725748c1
+Qx = 0f753171922b5334f3dd2778a64ce2da8295121939beae71ad85e5344e893be0fd03cf14e1f031adec098e0c4409449c
+Qy = 45c10a0ffc0eb2f1cec5c89b698061108313ee7d449ad580efad344f0e7cf35be8a18fca620f112e57bdc746abdace55
+k = d06bea06b25e6c30e866b1eb0657b45673e37b709013fb28fd7373afc8277cbc861354f821d0bd1927e52ec083a0f41f
+R = e8d4a31dd0e7d2522be62a32608e744c3775ceb606dc897899f0c73f1a40ce9a8be854cd506e65cd81fd7fa2c616cb7b
+S = 8151b681b6b6046d3c36f332d06d9ba7751e740631cdb759f88c50a25a8e950d5023df8a15c77243743733c4feaf21d5
+
+Msg = c9b4ff721b3e886f0dc05856ffff0aabb64a8504b1746a47fdd73e6b7ebc068f06ac7ffa44c757e4de207fc3cbfaf0469d3ac6795d40630bcafe8c658627e4bc6b86fd6a2135afbc18ccc8e6d0e1e86016930ca92edc5aa3fbe2c57de136d0ea5f41642b6a5d0ddeb380f2454d76a16639d663687f2a2e29fb9304243900d26d
+d = 93434d3c03ec1da8510b74902c3b3e0cb9e8d7dccad37594d28b93e065b468d9af4892a03763a63eae060c769119c23c
+Qx = a52c25f2af70e5bc6a992ecef4ea54e831ed5b9453747d28aec5cffb2fcfee05be80c5cbab21606b5507aa23878adee1
+Qy = 2cf2a9afeff83f3041dc8a05f016ccae58aa1a0e0dc6be9d928e97f2598c9ba5e9718d5eb74c9cfb516fd8c09f55f5b9
+k = 13d047708ae5228d6e3bbada0e385afdb3b735b31123454fdf40afe3c36efed563fd2cce84dcc45c553b0993d9ca9ec3
+R = a0203f6f2c456baac03538ed506a182e57a25151802cf4b2557613b2fb615ebd4c50ddc505f87c048a45bad3b2fc371c
+S = 0eab56457c4080400fa3af124761d5a01fef35f9649edba8b97d22116386f3b8b363e97ef3f82616d5d825df1cf865ef
+
+Msg = db2ad659cf21bc9c1f7e6469c5f262b73261d49f7b1755fc137636e8ce0202f929dca4466c422284c10be8f351f36333ebc04b1888cba217c0fec872b2dfc3aa0d544e5e06a9518a8cfe3df5b20fbcb14a9bf218e3bf6a8e024530a17bab50906be34d9f9bba69af0b11d8ed426b9ec75c3bd1f2e5b8756e4a72ff846bc9e498
+d = e36339ddbe8787062a9bc4e1540690915dd2a2f11b3fe9ee946e281a0a2cbed426df405ed9cb0eca42f85443efd09e0c
+Qx = a1ffb4b790d1593e907369b69de10b93cddbb02c6131f787422364d9d692768ef8097970306cce16c97f2b10c538efa7
+Qy = d0692028601ea794d2563ffe9facc7273938fab47dd00b8960be15549a9c2b3f8552583eb4c6cd212fe486c159c79153
+k = 2226f7329378cecd697f36ae151546643d67760856854661e31d424fae662da910e2157da9bb6dfbe3622296e0b5710c
+R = 20dcc25b67dd997621f437f65d78347fb57f8295b1b14453b1128203cda892bcfe726a2f107d30975d63172e56f11d76
+S = 51cff592cbef75ef8321c8fa1e4229c4298b8180e427bee4e91d1e24fc28a729cf296beb728960d2a58cf26773d8e2e2
+
+Msg = dbd8ddc02771a5ff7359d5216536b2e524a2d0b6ff180fa29a41a8847b6f45f1b1d52344d32aea62a23ea3d8584deaaea38ee92d1314fdb4fbbecdad27ac810f02de0452332939f644aa9fe526d313cea81b9c3f6a8dbbeafc899d0cdaeb1dca05160a8a039662c4c845a3dbb07be2bc8c9150e344103e404411668c48aa7792
+d = 5da87be7af63fdaf40662bd2ba87597f54d7d52fae4b298308956cddbe5664f1e3c48cc6fd3c99291b0ce7a62a99a855
+Qx = 54c79da7f8faeeee6f3a1fdc664e405d5c0fb3b904715f3a9d89d6fda7eabe6cee86ef82c19fca0d1a29e09c1acfcf18
+Qy = 926c17d68778eb066c2078cdb688b17399e54bde5a79ef1852352a58967dff02c17a792d39f95c76d146fdc086fe26b0
+k = 1b686b45a31b31f6de9ed5362e18a3f8c8feded3d3b251b134835843b7ae8ede57c61dc61a30993123ac7699de4b6eac
+R = 9dbfa147375767dde81b014f1e3bf579c44dd22486998a9b6f9e0920e53faa11eed29a4e2356e393afd1f5c1b060a958
+S = e4d318391f7cbfe70da78908d42db85225c85f4f2ff413ecad50aad5833abe91bdd5f6d64b0cd281398eab19452087dd
+
+
+[P-521,SHA-224]
+
+Msg = 58ec2b2ceb80207ff51b17688bd5850f9388ce0b4a4f7316f5af6f52cfc4dde4192b6dbd97b56f93d1e4073517ac6c6140429b5484e266d07127e28b8e613ddf65888cbd5242b2f0eee4d5754eb11f25dfa5c3f87c790de371856c882731a157083a00d8eae29a57884dbbfcd98922c12cf5d73066daabe3bf3f42cfbdb9d853
+d = 1d7bb864c5b5ecae019296cf9b5c63a166f5f1113942819b1933d889a96d12245777a99428f93de4fc9a18d709bf91889d7f8dddd522b4c364aeae13c983e9fae46
+Qx = 1a7596d38aac7868327ddc1ef5e8178cf052b7ebc512828e8a45955d85bef49494d15278198bbcc5454358c12a2af9a3874e7002e1a2f02fcb36ff3e3b4bc0c69e7
+Qy = 184902e515982bb225b8c84f245e61b327c08e94d41c07d0b4101a963e02fe52f6a9f33e8b1de2394e0cb74c40790b4e489b5500e6804cabed0fe8c192443d4027b
+k = 141f679033b27ec29219afd8aa123d5e535c227badbe2c86ff6eafa5116e9778000f538579a80ca4739b1675b8ff8b6245347852aa524fe9aad781f9b672e0bb3ff
+R = 06b973a638bde22d8c1c0d804d94e40538526093705f92c0c4dac2c72e7db013a9c89ffc5b12a396886305ddf0cbaa7f10cdd4cd8866334c8abfc800e5cca365391
+S = 0b0a01eca07a3964dd27d9ba6f3750615ea36434979dc73e153cd8ed1dbcde2885ead5757ebcabba117a64fcff9b5085d848f107f0c9ecc83dfa2fa09ada3503028
+
+Msg = 2449a53e0581f1b56d1e463b1c1686d33b3491efe1f3cc0443ba05d65694597cc7a2595bda9cae939166eb03cec624a788c9bbab69a39fb6554649131a56b26295683d8ac1aea969040413df405325425146c1e3a138d2f4f772ae2ed917cc36465acd66150058622440d7e77b3ad621e1c43a3f277da88d850d608079d9b911
+d = 17e49b8ea8f9d1b7c0378e378a7a42e68e12cf78779ed41dcd29a090ae7e0f883b0d0f2cbc8f0473c0ad6732bea40d371a7f363bc6537d075bd1a4c23e558b0bc73
+Qx = 0156cd2c485012ea5d5aadad724fb87558637de37b34485c4cf7c8cbc3e4f106cb1efd3e64f0adf99ddb51e3ac991bdd90785172386cdaf2c582cc46d6c99b0fed1
+Qy = 1edeeda717554252b9f1e13553d4af028ec9e158dbe12332684fc1676dc731f39138a5d301376505a9ab04d562cc1659b0be9cb2b5e03bad8b412f2699c245b0ba2
+k = 1dc3e60a788caa5f62cb079f332d7e5c918974643dca3ab3566a599642cd84964fbef43ce94290041fe3d2c8c26104d9c73a57a7d4724613242531083b49e255f33
+R = 12592c0be6cce18efb2b972cd193d036dcb850f2390fa8b9b86b2f876548bc424fb3bc13c1e5c415fa09d0ecfcae5bf76fb23e8322d7eecb264a2ae6d20ef50d405
+S = 11bc9713be88e3b9912a3e5f5d7b56f20573e979b1a75d04ce339f724bddffa4665d25995fe24d32507d8a07c5e10169f5338ef2827737f7b0291752b21237217e3
+
+Msg = 7ba05797b5b67e1adfafb7fae20c0c0abe1543c94cee92d5021e1abc57720a6107999c70eacf3d4a79702cd4e6885fa1b7155398ac729d1ed6b45e51fe114c46caf444b20b406ad9cde6b9b2687aa645b46b51ab790b67047219e7290df1a797f35949aaf912a0a8556bb21018e7f70427c0fc018e461755378b981d0d9df3a9
+d = 135ea346852f837d10c1b2dfb8012ae8215801a7e85d4446dadd993c68d1e9206e1d8651b7ed763b95f707a52410eeef4f21ae9429828289eaea1fd9caadf826ace
+Qx = 18d40cc4573892b3e467d314c39c95615ee0510e3e4dbc9fa28f6cd1f73e7acde15ad7c8c5339df9a7774f8155130e7d1f8de9139ddd6dfe1841c1e64c38ea98243
+Qy = 17021782d33dc513716c83afe7ba5e7abef9cb25b31f483661115b8d6b5ae469aaf6f3d54baa3b658a9af9b6249fd4d5ea7a07cb8b600f1df72b81dac614cfc384a
+k = 0c24acc1edb3777212e5b0bac744eadf4eda11fa150753b355bf96b189e6f57fc02284bb22d8b3cd8bba7a09aae9f4ea955b382063425a6f8da2f99b9647b147172
+R = 183da7b8a9f9d5f08903359c1a2435b085fcf26a2ed09ab71357bb7634054acc569535e6fe81d28233e4703005fc4bf83ce794d9463d575795aa0f03398e854cefd
+S = 0b3621145b9866ab7809139795cc30cd0404127a7f0fafa793660491009f6c53724fdb0b1ffbf0fd51c131180b8a957fe66e76d2970247c024261c768dee9abbfb9
+
+Msg = 716dabdb22a1c854ec60420249905a1d7ca68dd573efaff7542e76f0eae54a1828db69a39a1206cd05e10e681f24881b131e042ed9e19f5995c253840e937b809dfb8027fed71d541860f318691c13a2eb514daa5889410f256305f3b5b47cc16f7a7dad6359589b5f4568de4c4aae2357a8ea5e0ebaa5b89063eb3aa44eb952
+d = 1393cb1ee9bfd7f7b9c057ecc66b43e807e12515f66ed7e9c9210ba1514693965988e567fbad7c3f17231aacee0e9b9a4b1940504b1cd4fd5edfaa62ba4e3e476fc
+Qx = 1e855c935139c8092092cfa733db1292530506eeb2bbb1687f9602c36d97a6714e998892d5d3b842d1896a6ece9d549e9792881a256256137b3dff180c96cc5d07b
+Qy = 18d83b6e93cd287311f7bf7c1d7f9eeabcf0b69c12f2d8f40e333e81e956d968532a37a4c04d761874df293b484cd7053b03fdbc2fdcd3b4c412d6f272fb7c93fe6
+k = 1d98619bdc04735d30c222fc67da82c069aea5f449af5e8c4db10c1786c0cb9e6f2cc0bb66fa6be18c485570d648dafcd0a973c43d5c94e9a9dacbd3170e53fa2a0
+R = 0bf47fabe107ce0ec03e2ad60a79b058e1bebb18568b6a8cdbe86032e71aa30c15766105b2ea952cfa79bcab046df601159f96e179bbcf252dc68ac73d31481fdae
+S = 1f918fec69cd07d90f9d892b7117e7519c3224947f4262f1fd97077dd5386a6c78aeddff3ee97e59ea353f06029f1336f0d6ef5c0f4b17ca59343a55319b7bfc3db
+
+Msg = 9cc9c2f131fe3ac7ea91ae6d832c7788cbbf34f68e839269c336ceef7bef6f20c0a62ea8cc340a333a3002145d07eba4cf4026a0c4b26b0217a0046701de92d573d7c87a386a1ea68dc80525b7dcc9be41b451ad9f3d16819e2a0a0b5a0c56736da3709e64761f97cae2399de2a4022dc4c3d73c7a1735c36dbde86c4bc5b6f7
+d = 179fa164e051c5851e8a37d82c181e809a05fea9a3f083299b22684f59aa27e40dc5a33b3f7949338764d46bfe1f355134750518b856d98d9167ef07aac3092c549
+Qx = 1857cc7bbed20e87b3fd9a104956aa20c6502192910e0e7598410526ebfe1c99397b85189612a60c51fb8f4dd5cb08a8cd2e702563062dcb043410715c5323a0046
+Qy = 1fce8d135284310d2f38c216030634b32cd223222f0d9d8d2b7c55477c4b8b74fc6c96a6092f34b05ca44d3633a5037c2166c479a032bb4f949f89fc1ba5236d07d
+k = 16d9704c0cee791f2938bb2a8a595752a3635c2f557efeecefd719414b5f2aaf846080f582c76eae7a8fddf81859b49d0131c212524d55defa67dca1a9a28ca400f
+R = 1c9a4e51774384e8362876a87c572e6463a54413c7c6252c552ebb182f83e45ace436ade4ca373d8a7216e83efb62c8b41c4d5132a0afa65078f16d189baca39187
+S = 1e92a7dd5fea29a666398e1df5775cbb5664fe6943fe4c1d2bba516b7543c84df584458e53919c4ffab579a26fb3c892a5d1a77b0a07428c89350f8b559e627b014
+
+Msg = 14c69f8d660f7a6b37b13a6d9788eff16311b67598ab8368039ea1d9146e54f55a83b3d13d7ac9652135933c68fafd993a582253be0deea282d86046c2fb6fd3a7b2c80874ced28d8bed791bd4134c796bb7baf195bdd0dc6fa03fdb7f98755ca063fb1349e56fd0375cf94774df4203b34495404ebb86f1c7875b85174c574c
+d = 13dabca37130ba278eae2b3d106b5407711b0d3b437fbf1c952f0773571570764d2c7cb8896a8815f3f1975b21adc6697898e5c0a4242092fc1b80db819a4702df4
+Qx = 0bc2aebf40cd435bc37d73c09d05f2fd71321111a767c2b0d446f90dd4a186839c694ceb734e027e7ee948f0f63e4d3f1656d3d543df23c342a599306909b347109
+Qy = 1f4c98ac03f0718e58d5d1762c920445b11dbdd60ec7f60095809204e14965a4ecb0be6fea06adbac8ba431d6f144c75c199225df2a619a34be99897125b3a10af8
+k = 0401187c8b89945a1e48cda9ee52167789f4121e67482a7ac797899f5d3d2e623aed31e4adae08a8d43e69028fa074d2650317cbc765f6ed191cf0317b4bae57881
+R = 1e572afed754016fba43fc33e352932c4db65efcb84e2bd159b40fc5925893b161effc40240be28d8c07154d2615f605c6f0451b976522d95afd37f46602df7a12a
+S = 030370c1c5352c2b663ac1858b42f69545b2f58ed5b2c007f303726977d3c756b5d644ec6788f94c886f78269aa190a3d8d1ae10e4fd24d937c4556fb9e1953fd6d
+
+Msg = 8d8e75df200c177dbfe61be61567b82177ea5ec58e2781168d2277d2fd42668f01248ca3eb29ffa2689b12ae40f9c429532b6d2e1f15891322b825a0a072a1c68fa09e78cfdef3e95ed6fdf7233a43cb68236560d49a3278f0b3f47cb08f475bd9ab2f60755ea4a1767de9313b71a1b9ea87ef33f34682efbda263b0f8cc2f52
+d = 198681adbde7840d7ccd9cf1fb82056433fb4dd26bddf909af7b3b99da1ca2c05c8d4560ecd80ba68f376f8b487897e374e99a9288ed7e3645cc0d00a478aae8d16
+Qx = 057ce3777af7032f1f82308682e71fe09f88bf29dacd5018a725e1caa4b1e2bfdd894fe618f9266f31ba089856dc9c1b70e4a2faa08b4b744d1aafcd5ae99e2c736
+Qy = 199bcfef2021bc5890d7d39ec5dc0c26956801e84cae742cf6c50386eb289b6e97754dd25a94abf81f1cb1b36935b5eb29f4b32a6516d2ff6a7d23064a0daec94b3
+k = 19d2d74ad8ee2d85048f386998a71899ef6c960b4ab324e5fd1c0a076c5a632fd0009500076522e052c5c9806eef7056da48df6b16eb71cdf0f1838b0e21715fce0
+R = 18ecacbcffd5414bbb96728e5f2d4c90178e27733d13617e134ec788022db124374bbaa11e2c77fe3f38d1af6e998e1b0266b77380984c423e80ffa6ff2bcafd57a
+S = 1c727f34b6a378f3087721a54e9796499b597ecf6666b8f18312d67e1190a8a66e878efc2367b551267494e0245979ef4deed6d2cbf2c3711af6d82ccfeb101a377
+
+Msg = 10631c3d438870f311c905e569a58e56d20a2a560e857f0f9bac2bb7233ec40c79de145294da0937e6b5e5c34fff4e6270823e5c8553c07d4adf25f614845b2eac731c5773ebbd716ab45698d156d043859945de57473389954d223522fbafecf560b07ef9ba861bcc1df9a7a89cdd6debf4cd9bf2cf28c193393569ccbd0398
+d = 08c4c0fd9696d86e99a6c1c32349a89a0b0c8384f2829d1281730d4e9af1df1ad5a0bcfccc6a03a703b210defd5d49a6fb82536f88b885776f0f7861c6fc010ef37
+Qx = 164ac88ed9afe137f648dd89cdd9956682830cac5f7c1a06d19a1b19f82bb1d22dfeefea30d35c11202fed93fd5ce64835d27c6564d6e181287fa04a2d20994986b
+Qy = 05cb83669265f5380ccefe6b4f85fdf0049e6703f6f378a0b2e52ed0fbbcf300afebb722f4ed48e3819cb976c1d60e2ba05646b478f6dfecfbae730e9644c297f00
+k = 189801432cba9bf8c0763d43b6ec3b8636e62324587a4e27905b09a58e4aa66d07d096dbce87824e837be1c243dd741f983c535a5dd2f077aac8beee9918258d3cb
+R = 0917723f7241e8dc7cd746b699ab621d068dd3a90e906aaf0a4862744b96fd4e5ccdb9c7796c27f7196e693d06ec209464c3ea60ad6313e9b77cceaa14767e6651c
+S = 0957b0ecdc3668f6efa5d0957615bcfffd6419c5e57579b74f960f65ae3fb9e8284322ff710b066f7e0959ac926d3cf9a594bdb70bbec756c96910b26a2486dee9e
+
+Msg = 80aad6d696cbe654faa0d0a24d2f50d46e4f00a1b488ea1a98ed06c44d1d0c568beb4ab3674fc2b1d2d3da1053f28940e89ba1244899e8515cabdd66e99a77df31e90d93e37a8a240e803a998209988fc829e239150da058a300489e33bf3dcdaf7d06069e74569fee77f4e3875d0a713ccd2b7e9d7be62b34b6e375e84209ef
+d = 1466d14f8fbe25544b209c5e6a000b771ef107867e28ed489a42015119d1aa64bff51d6b7a0ac88673bbc3618c917561cff4a41cdb7c2833dab5ebb9d0ddf2ca256
+Qx = 1dc8b71d55700573a26af6698b92b66180cf43e153edadb720780321dbb4e71d28e0a488e4201d207fc4848fe9dd10dcabec44492656a3ff7a665fe932445c82d0b
+Qy = 1920b16331b7abeb3db883a31288ef66f80b7728b008b3cc33e03a68f68d9e653a86e3177bbc00014fa5ea4c1608c0d455c2e2ac7bd8ab8519ebf19955edf1baf8d
+k = 160d04420e0d31b0df476f83393b1f9aff68389cc3299e42ef348d97646f7531a722b66ddfb9501bbb5c4a41d84c78be7233b11489bceb817d23060e6017433fab8
+R = 08077aabd0a342f03f912007c586cfedfc63f93d1118f720d5b62b3ce141a60f86f111dfd8fc2e31a6778981f1a5e28f29a7369bd7897bb41240c8d3a9c170e0ee0
+S = 00abc75fc154b93840579457820957e89d1260fee0a4b9bb1946f61ca1e71afd76bb5e1077b3e38ceb39d1fac5ef8b217c4110617b3ad118e02b3fcc2a39ef38613
+
+Msg = 8a7792a2870d2dd341cd9c4a2a9ec2da753dcb0f692b70b64cef2e22071389c70b3b188dea5f409fb435cbd09082f59de6bc2ff9e65f91b7acc51e6e7f8e513148cb3c7c4664f227d5c704626b0fda447aa87b9d47cd99789b88628eb642ed250312de5ba6b25f3d5342a3cbb7ebd69b0044ee2b4c9ba5e3f5195afb6bea823d
+d = 01a99fcf54c9b85010f20dc4e48199266c70767e18b2c618044542cd0e23733817776a1a45dbd74a8e8244a313d96c779f723013cd88886cb7a08ef7ee8fdd862e7
+Qx = 1912d33b01d51e2f777bdbd1ada23f2b1a9faf2be2f2a3b152547db9b149b697dd71824ca96547462e347bc4ef9530e7466318c25338c7e04323b1ba5fd25ea7162
+Qy = 0bbe9b1e3a84accd69b76b253f556c63e3f374e3de0d1f5e3600fc19215533b2e40d6b32c3af33314d223ea2366a51d1a337af858f69326389276f91be5c466e649
+k = 14fafd60cb026f50c23481867772411bb426ec6b97054e025b35db74fe8ea8f74faa2d36e7d40b4652d1f61794878510b49b7b4fe4349afccd24fc45fec2fd9e9e7
+R = 18b1df1b6d7030a23a154cacce4a2e3761cc6251ff8bf6c9f6c89d0a15123baef9b338ada59728349ce685c03109fcde512ed01a40afd2ca34e1bc02ecf2871d45c
+S = 0a399f9b9e21aeddf450429fec2dc5749e4a4c7e4f94cee736004dcc089c47635da22845992cd076a4f0a01d2cc1b0af6e17b81a802361699b862157ad6cad8bd1d
+
+Msg = f971bcd396efb8392207b5ca72ac62649b47732fba8feaa8e84f7fb36b3edb5d7b5333fbfa39a4f882cb42fe57cd1ace43d06aaad33d0603741a18bc261caa14f29ead389f7c20536d406e9d39c34079812ba26b39baedf5feb1ef1f79990496dd019c87e38c38c486ec1c251da2a8a9a57854b80fcd513285e8dee8c43a9890
+d = 1b6015d898611fbaf0b66a344fa18d1d488564352bf1c2da40f52cd997952f8ccb436b693851f9ccb69c519d8a033cf27035c27233324f10e9969a3b384e1c1dc73
+Qx = 110c6177ceb44b0aec814063f297c0c890671220413dbd900e4f037a67d87583eaf4b6a9a1d2092472c17641362313c6a96f19829bb982e76e3a993932b848c7a97
+Qy = 0f6e566c4e49b2ee70a900dc53295640f3a4a66732df80b29f497f4ae2fa61d0949f7f4b12556967bb92201a4f5d1384d741120c95b617b99c47a61e11c93a482d6
+k = 1a88667b9bdfe72fb87a6999a59b8b139e18ef9273261549bc394d884db5aa64a0bc7c7d38a8ef17333478d2119d826e2540560d65f52b9a6dc91be1340cfd8f8f8
+R = 015f73def52ea47ddb03e0a5d154999642202e06e6734ac930c1dc84756c67bbb1cca9f21f92d61bfdb2052c5dd2833349610f68139393d77250a7662ef7bd17cbe
+S = 155c744a729f83b27d1f325a91e63a0d564fe96ff91eaa1bad3bff17d2abffa065d14a1d20a04dd993f6ed3260b60bcc6401e31f6bc75aaafe03e8c1a9cd14d2708
+
+Msg = ec0d468447222506b4ead04ea1a17e2aa96eeb3e5f066367975dbaea426104f2111c45e206752896e5fa7594d74ed184493598783cb8079e0e915b638d5c317fa978d9011b44a76b28d752462adf305bde321431f7f34b017c9a35bae8786755a62e746480fa3524d398a6ff5fdc6cec54c07221cce61e46fd0a1af932fa8a33
+d = 05e0d47bf37f83bcc9cd834245c42420b68751ac552f8a4aae8c24b6064ae3d33508ecd2c17ec391558ec79c8440117ad80e5e22770dac7f2017b755255000c853c
+Qx = 1a6effc96a7f23a44bf9988f64e5cfafdae23fa14e4bee530af35d7a4ddf6b80dcd0d937be9dd2db3adcda2f5216fecbce867ee67e7e3773082f255156e31358c2f
+Qy = 1e7760190dfbe07ec2df87067597087de262c1e0a12355456faba91b2e7277050d73b924e14c0e93b8457a8b3e1f4207ce6e754274f88ad75c000d1b2977edc9c1a
+k = 18afea9a6a408db1e7a7bb1437a3d276f231eacfc57678bfa229d78681cbe4e800e6065332a3128db65d3aa446bb35b517dca26b02e106e1311881a95b0302d15e8
+R = 01c49b3c1d21f1678bdbe1ac12167e95e06617190bdee1a729c1c649210da19e2e210f6689e1310513bfe2ac6c0f4ee5f324f344b31b18df341eaadb826d07adc9b
+S = 129d4931ba457443012f6ffecd002f2abc3a4b65a58fee8457917ebcf24b29a1d3055b7fc62939a74ebb0c3582172ee7c3c75e0b2fa2367c6e04df63a7a91d593ad
+
+Msg = d891da97d2b612fa6483ee7870e0f10fc12a89f9e33d636f587f72e0049f5888782ccde3ea737e2abca41492bac291e20de5b84157a43c5ea900aef761006a4471072ab6ae6d515ffe227695d3ff2341355b8398f72a723ae947f9618237c4b6642a36974860b452c0c6202688bc0814710cbbff4b8e0d1395e8671ae67ada01
+d = 1804ab8f90ff518b58019a0b30c9ed8e00326d42671b71b067e6f815ac6752fa35016bd33455ab51ad4550424034419db8314a91362c28e29a80fbd193670f56ace
+Qx = 0a79529d23a832412825c3c2ad5f121c436af0f29990347ecfa586ce2e57fd3c7e0624d8db1f099c53473dbc2578f85416ad2ac958a162051014fb96bf07f9e1d17
+Qy = 17c0750f26df0c621d2d243c6c99f195f0086947b1bf0f43731555f5d677e2d4a082fb5fe8da87e1592a5fa31777da3299cede5a6f756edf81c85b77853388bb3ab
+k = 042d7c36fec0415bc875deb0fab0c64548554062e618aee3aa6670ffd68ab579fe620d3a9316357267fd3111c0ed567dca663acd94b646d2ba0771953cd9690ef42
+R = 0d01dfbef126febbdfa03ef43603fd73bc7d2296dce052216e965fed7bb8cbbc24142bfcddb60c2e0bef185833a225daa0c91a2d9665176d4ad9986da785f4bfcf0
+S = 16627e2614dbcd371693c10bbf579c90c31a46c8d88adf59912c0c529047b053a7c7715142f64dcf5945dbc69ff5b706c4b0f5448d04dd1f0b5a4c3765148bf253d
+
+Msg = 924e4afc979d1fd1ec8ab17e02b69964a1f025882611d9ba57c772175926944e42c68422d15f9326285538a348f9301e593e02c35a9817b160c05e21003d202473db69df695191be22db05615561951867f8425f88c29ba8997a41a2f96b5cee791307369671543373ea91d5ed9d6a34794d33305db8975b061864e6b0fe775f
+d = 0159bff3a4e42b133e20148950452d99681de6649a56b904ee3358d6dd01fb6c76ea05345cb9ea216e5f5db9ecec201880bdff0ed02ac28a6891c164036c538b8a8
+Qx = 12d7f260e570cf548743d0557077139d65245c7b854ca58c85920ac2b290f2abfeccd3bb4217ee4a29b92513ddce3b5cbf7488fb65180bb74aeb7575f8682337ef5
+Qy = 17560186230c7e8bff0bffce1272afcd37534f317b453b40716436a44e4731a3ec90a8f17c53357bc54e6ff22fc5b4ca892321aa7891252d140ece88e25258b63d5
+k = 14b8a30f988cefdc0edec59537264edb0b697d8c4f9e8507cf72bc01c761304bd2019da1d67e577b84c1c43dd034b7569f16635a771542b0399737025b8d817e1c3
+R = 0fc50939ebca4f4daa83e7eaf6907cb08f330c01d6ea497b86becda43dfcad47cb5c48f5eb2cc924228628070bcd144088c449a7873242ba86badf796097dbecd6d
+S = 0ccb6463c4301ba5c043e47ed508d57dd908fd0d533af89fd3b11e76343a1cf2954ce90b0eb18cbc36acd6d76b3906612d8a0feec6ebed13d88650ed9c708b28a11
+
+Msg = c64319c8aa1c1ae676630045ae488aedebca19d753704182c4bf3b306b75db98e9be438234233c2f14e3b97c2f55236950629885ac1e0bd015db0f912913ffb6f1361c4cc25c3cd434583b0f7a5a9e1a549aa523614268037973b65eb59c0c16a19a49bfaa13d507b29d5c7a146cd8da2917665100ac9de2d75fa48cb708ac79
+d = 17418dfc0fc3d38f02aa06b7df6afa9e0d08540fc40da2b459c727cff052eb0827bdb3d53f61eb3033eb083c224086e48e3eea7e85e31428ffe517328e253f166ad
+Qx = 00188366b9419a900ab0ed9633426d51e25e8dc03f4f0e7549904243981ec469c8d6d938f6714ee620e63bb0ec536376a73d24d40e58ad9eb44d1e6063f2eb4c51d
+Qy = 09889b9203d52b9243fd515294a674afd6b81df4637ffdddc43a7414741eda78d8aa862c9cbbb618acec55bb9a29aac59616fc804a52a97a9fc4d03254f4469effe
+k = 1211c8824dcbfa0e1e15a04779c9068aed2431daeac298260795e6a80401f11f6d52d36bcee3cfa36627989c49d11475163aa201d2cd4c5394144a6bb500bbaf02b
+R = 1d59401b8ac438855d545a699991142685077a409de2418c7ccfe01a4771b3870e76287a9654c209b58a12b0f51e8dc568e33140a6b630324f7ef17caa64bf4c139
+S = 143af360b7971095b3b50679a13cd49217189eaee4713f4201720175216573c68f7ac6f688bfe6eb940a2d971809bf36c0a77decc553b025ed41935a3898685183b
+
+[P-521,SHA-256]
+
+Msg = 8ab8176b16278db54f84328ae0b75ef8f0cd18afdf40c04ad0927ed0f6d9e47470396c8e87cde7a9be2ffbfe6c9658c88b7de4d582111119c433b2e4a504493f0a1166e3a3ea0d7b93358f4a297d63f65a5e752f94e2ee7f49ebcc742fa3eb03a617d00c574245b77a20033854d82964b2949e2247637239ab00baf4d170d97c
+d = 1e8c05996b85e6f3f875712a09c1b40672b5e7a78d5852de01585c5fb990bf3812c3245534a714389ae9014d677a449efd658254e610da8e6cad33414b9d33e0d7a
+Qx = 07d042ca19408524e68b981f1419351e3b84736c77fe58fee7d11317df2e850d960c7dd10d10ba714c8a609d163502b79d682e8bbecd4f52591d2748533e45a867a
+Qy = 197ac6416111ccf987d290459ebc8ad9ec56e49059c992155539a36a626631f4a2d89164b985154f2dddc0281ee5b5178271f3a76a0914c3fcd1f97be8e8376efb3
+k = 0dc8daaacddb8fd2ff5c34a5ce183a42261ad3c64dbfc095e58924364dc47ea1c05e2599aae917c2c95f47d6bb37da008af9f55730ddbe4d8ded24f9e8daa46db6a
+R = 09dd1f2a716843eedec7a6645ac834d4336e7b18e35701f06cae9d6b290d41491424735f3b57e829ad5de055eaeef1778f051c1ee152bf2131a081e53df2a567a8a
+S = 02148e8428d70a72bc9fa986c38c2c97deda0420f222f9dc99d32c0acba699dc7ba0a2b79ce5999ff61bd0b233c744a893bc105bca5c235423e531612da65d72e62
+
+Msg = c4bc2cec829036469e55acdd277745034e4e3cc4fcd2f50ec8bd89055c19795a1e051ccf9aa178e12f9beab6a016a7257e391faa536eaa5c969396d4e1ade36795a82ebc709d9422de8497e5b68e7292538d4ccdc6dd66d27a3ece6a2844962b77db073df9489c9710585ba03d53fa430dbc6626dc03b61d53fc180b9af5dea6
+d = 0b65bf33b2f27d52cbfabcadce741e691bf4762089afd37964de1a0deda98331bf8c74020a14b52d44d26e2f6fa7bcddbe83be7db17a0c8a1b376469cf92c6da27c
+Qx = 10038bb9a7aea626de68c14c64243150e72c69e2f8a1ab922bfbdaa6f33d24fb4542c0324357b0dd640bbcd07632ecd253f64ca2bfbfbf3de9b24fffd0568ab82da
+Qy = 0faf867d95308cc36d6f46844a0f535dc70f9768eed011a2464d2f308fa1d8e72c3616aec7e70516908183ffce7fdd36984a15f73efaa3858c2edf16a784d40e6c2
+k = 14aeb96c57d99677a1f5e4588064215e7e9af4027bfb8f31ff6126dbf341b8e6f719465e4273e91ba32670feca802549808322b7ee108bb20653cf20f93284d365f
+R = 075ead62edf7d86c5d1bc2443d1aeb5dc034fd999e6ea012cef7499d9d050cd97d262095884e9fc89a42e15bd3dee80fe3c1ba10f4caabc4aabb86347023028b663
+S = 129a992a6ff66d41948d11fa680f732b1a74315b804c982805190ed9d2fae223f2b149980b9241998cdea0c5672595a8a49d5186a0ef7a46c0a376f925bdda81726
+
+Msg = 1c1b641d0511a0625a4b33e7639d7a057e27f3a7f818e67f593286c8a4c827bb1f3e4f399027e57f18a45403a310c785b50e5a03517c72b45ef8c242a57b162debf2e80c1cf6c7b90237aede5f4ab1fcaf8187be3beb524c223cc0ceff24429eb181a5eea364a748c713214880d976c2cd497fd65ab3854ad0d6c2c1913d3a06
+d = 02c4e660609e99becd61c14d043e8b419a663010cc1d8f9469897d7d0a4f076a619a7214a2a9d07957b028f7d8539ba7430d0b9a7de08beeeae8452d7bb0eac669d
+Qx = 0fb3868238ca840dbb36ecc6cf04f5f773ea0ab8e8b0fdcf779dc4039a8d7146a417504e953c0cb5e7f4e599cc2c168deda8b7f16084b5582f89f2ece4cae5167f7
+Qy = 1f90b5c15eeda48e747cf3ee8183166a49dbfac6161cbd09d29d40a6854f4c495e88a435892a920cdaad20d41985890b648badd4f0a858ffcbd9afdfc23134ede18
+k = 1f875bbf882cd6dd034a87916c7b3ba54b41b2ea2ce84ebaf4e393fcf7291fee09dec2b5bb8b6490997c9e62f077c34f0947fe14cec99b906dd6bf0b5d301e75ca1
+R = 07aa70425697736b298233249f5d0cf25c99e640c9ff88035ef1804820e1bfe7d043755f02d7a079494f7fa6dc26740c4e6b7b430c63f29c67bbd3a5c88d2f0e8d1
+S = 0e0d42e4ff11cf5be37a9fda348514d5097a662f214687cbfb28ff42d635b13029871ca4f464bb1fbce02d5da4d5fb61b2a071844259fc863d136197bec3a61e7c7
+
+Msg = adb5f069b2b501a3ebb83d4f1808eb07710ac4a7b12532996855a20bcc54b2f76812915f632163c3654ff13d187d007152617cf859200194b59c5e81fc6cc9eb1ceb75d654050f260caa79c265254089270ccd02607fdcf3246119738c496dc3a4bd5d3be15789fc3d29a08d6d921febe2f40aef286d5d4330b07198c7f4588e
+d = 17c3522007a90357ff0bda7d3a36e66df88ca9721fb80e8f63f50255d47ee819068d018f14c6dd7c6ad176f69a4500e6f63caf5cf780531004f85009c69b9c1230c
+Qx = 13a4bea0eed80c66ea973a9d3d4a90b6abbb5dee57d8affaf93390a8783a20982eba644d2e2809f66530adeeee7f9a1da7515447e9ba118999f76f170c375f621f7
+Qy = 12f9dfaee40a75d8442b39b37a5c19ea124b464236e9b9a31bae6780cfd50f7ea4a700154b5ea0feeb64e9b35a1b0e33e46900cca1f34d13bb17e5017769841af27
+k = 18388a49caeda35859ef02702c1fd45ff26991998bd9d5e189c12c36cdae3f642ddd4a79561bd1d3e1cd9359de8f5c9e1604a312d207a27b08a6033f2741794ced5
+R = 15c6264795837dfea19f91876455f564f073c5c84a3c9d76e67872ae0447ba0d4850d8721302b25bec7ebfedd2721de140b2f3dead547042b24b0876117e7093cc1
+S = 060eb74236c189a28ed20bd0822eb22d75f7d97c9043a3c8e3f6d4c90bc8ca02ac4d37c1171c799a1c7dfd2fcbf83406b5e48c051e0fbf0fd937bfe6c3db4e18154
+
+Msg = f253484d121d1ce8a88def6a3e9e78c47f4025ead6f73285bf90647102645b0c32d4d86742a50b8b7a42d5f6156a6faf588212b7dc72c3ffd13973bdba732b554d8bffc57d04f8167aef21ee941ee6ffb6cce0f49445bd707da8deb35dca650aaf761c3aa66a5ebccddd15aee21293f63061a7f4bfc3787c2cd62c806a1a9985
+d = 0c4dad55871d3bd65b016d143ddd7a195cc868b3048c8bbcb1435622036bdb5e0dec7178ca0138c610238e0365968f6ddd191bbfacc91948088044d9966f652ff25
+Qx = 014858a3b9bd426b678fdcf93fc53d17e7a9e8fe022442aaaba65399d12fd3a6a381958fb0f07ac6088f4e490506ec0f1ab4d0dbd461126f7eb46ff69cfa8bd88af
+Qy = 18c18ce29ecc6d79d26a2de0cd31c4b32e84b5e90f6ba748f86c5afbd89618aceb9079460cbd1a8261ed5476973e61bf1d17ea78b022387443800c9247d21dde550
+k = 05577108f4187a173e5c29e927a8fc8f5ffd37e184254a6e381ff1018955aec91a35f30085e8cee6a7555c10f9efdce26d62f2b4b52dfdbaeafc3a30983e2d50d5b
+R = 0344375ae7c804cbe32ced7a20976efae5d9c19eb88b6e24514d1d0cfb728b0f4601098b18b2e98f42b5222dd5237d4d87767007bf5acb185c5526d72047e2cb1a1
+S = 02de4cfa908c73c1102d6fb7062baf54a056a9517701e036c9c51e09899d60051612d59348945f845dffebec5aa395b2fac7229929033615788777306ccad96d0a3
+
+Msg = 33bab1c369c495db1610965bc0b0546a216e8dd00cd0e602a605d40bc8812bbf1ffa67143f896c436b8f7cf0bed308054f1e1ff77f4d0a13c1e831efbd0e2fcfb3eadab9f755f070ba9aeaceb0a5110f2f8b0c1f7b1aa96a7f2d038a1b72e26400819b1f73d925ea4e34d6acaf59d0a461a34ce5d65c9c937a80e844e323a16d
+d = 03d4749fadcc2008f098de70545a669133c548ce0e32eec1276ff531bcff53533144555728ad8906d17f091cc0514571691107350b6561858e90dbe19633aaf31bf
+Qx = 10fe5986b65f6e65d13c88c4d2aed781a91026904f82129d46779bdadaf6b733c845a934e941ab4a285efdea9c96ecc9dc784d87e4d937b42c337b3a9cb111a9600
+Qy = 077853768a2a4d6f596f57414e57ec60b76d3cd5ece8351cd1f335ebcb8801a3d91fb82c65caaeb5c31eea9918367bb5906863ff3ccaf7a6cee415e0d75c15ac2e0
+k = 1fbb4de337b09e935a6dc6215ffcfcb85d236cc490585e73251a8b8bac37cfa36c5d1df5f4536d33659be1e7a442529a783452f7efda74a4f661b6a127f9248aaf7
+R = 09d8f10eeff6178594c89d6e8184f9502117384813243ddf9ccf3c8eac5dc6502c472dfc1487a5caffc569f7dedd14a8ebcb310e9bacdb79fb6655aba026cdf87f2
+S = 0f74236c7915d638708d17c9f10e39dda358faf9bbb821d8dcda0d151aac143bfb165ad0a23a65cd3de532e32cad928728f5ae1c16f58fc16577f3ca8e36f9e708b
+
+Msg = 08c8b7faaac8e1154042d162dca1df0f66e0001b3c5ecf49b6a4334ce4e8a754a1a8e4daf8ec09cf1e521c96547aed5172ef852e82c03cddd851a9f992183ac5199594f288dbcc53a9bb6128561ff3236a7b4b0dce8eaf7d45e64e782955ee1b690ce6a73ece47dc4409b690de6b7928cbe60c42fc6a5ddf1d729faf1cc3885e
+d = 096a77b591bba65023ba92f8a51029725b555caf6eff129879d28f6400e760439d6e69ce662f6f1aecf3869f7b6057b530a3c6ff8ed9e86d5944f583ee0b3fbb570
+Qx = 0fdf6aed933dba73913142ef8bdcd4b760db8500831cd11d7707ab852a6372c05d112a1e7fbc7b514c42142c7370d9f4129493cd75cc6f2daf83747078f15229db6
+Qy = 0ef91dffb3c43080a59534b95ca585ee87f6145f6a0199b2b82c89f456d8bd8e6ac71c78039c08177184484eb2ebd372f189db3a58fab961a75a18afec1ee32764a
+k = 13aa7b0471317a2a139c2f90df1c40d75e5a8a830fbaf87030fffdb2ef6f2c93d1310c9ed7fe9d7bcd4fe46537ff2495bc9c4f0aaff11461f5e4bebbfbce9a8740a
+R = 1c7a21800962c91d4651553633b18612d931bb88bff8b743ed595b4e869437e50f8e84fbf334c99061db123a1c40b73b07e203790561a37df65a660355ba2017d78
+S = 1301e1782559a38f1ca0eebe9bed0f5c7c33103d506a24f8a688f500ee1fe37f97b6685319279e82e6fe43cfd823ccbc123309974cffa76c4f8d41ec02a3cbc45f1
+
+Msg = ba74eed74282811631bd2069e862381e4e2a1e4e9a357b1c159a9ce69786f864b60fe90eeb32d8b72b099986fc594965a33285f7185b415df58fead7b8b50fc60d073680881d7435609ad1d22fd21e789b6730e232b0d2e888889fb82d6ad0337ab909308676164d4f47df44b21190eca8ba0f94995e60ad9bb02938461eee61
+d = 015152382bfd4f7932a8668026e705e9e73daa8bade21e80ea62cf91bd2448ebc4487b508ca2bdaaf072e3706ba87252d64761c6885a65dcafa64c5573c224ae9e6
+Qx = 00b8c7c0186a77dc6e9addd2018188a6a40c3e2ba396f30bbd9293dba2841d57d60866b37f587432719b544d8bf7eb06d90a8c0dc9c93b0c53d53b2f667077228ca
+Qy = 1dd2e5c73ab908ae34f701689f1cd3cf5186d3a2bc941e208bf3ef970e5e429ee9b154d73286b2e5da423e75b7c7b78c7bdf915da92279db43265a0cdefca51f86a
+k = 0d03506999f5cc9ec3304072984a20a9c64a22ad9b418495ca904f4bbddc96e76d34672cb52763339d3f3bc5b1701c00a675b972797e3a086314da1a8d338436566
+R = 085406c0ff5ec91f598bb579ad8714ad718c3e133d5dcc2e67c5d2339c146b69919cac07f3bc2bda218f4c7c8be04855e2ca6fff7fbdc4fc0fda87c8c3081cad4f5
+S = 1b45f2066e583636215ae135afc202b8bf3f301eccff2e1c0198b9aeddf695fa8179488e7b622fc307f601e2f6551815117cc836bb09ef888f8e64a45d9c84ad30c
+
+Msg = dc71f171a28bdc30968c39f08f999b88dc04c550e261ecf1124d67f05edeae7e87fe9b8135a96fe2bc3996a4f47213d9d191184a76bd6310e1ee5cb67ea7fc3ef6f641a0ba165198040fa668192b75a4754fc02c224bd4a74aade5a8c814adf151c2bfeda65165a04ef359e39847c84e312afb66d4cd1db50d41ef3fe5f31296
+d = 1750ff0ca0c166560b2034bc5760fe0b3915340bc43216e9de0c1d4a76550e8b2036e8b874230f8d29354aed43e183610f24fd4abd4b0be2f111dae942bd7a121f7
+Qx = 1b4b8947192a7c0166c0e0b2791e217370836283e805f3ee11cfb78445aba3c5bc39fe594e01916617ad59e7c8e740d8f2d07d88905d3f33bd5e51aafd4943c5dc6
+Qy = 1175d117232836c28e717ce2a55e59f4ec550effde30d18e3d99e42c6aa2283c7b3e7f2f6ff1fca605dde78c3a5bffa689347b4c93f51ba59a1787bb7d5e43861dc
+k = 023645023d6bdf20652cdce1185c4ef225c66d54f18632d99ccf743bf554d04c214c88ce52a4f71ec75c899ad1b3c07c34112ca20b55c217ff1d72c9528e2774ce8
+R = 1e933f68ce0f8403cb16822b8e0564b1d39a35f27b53e4ae0bcdff3e051759464afbc34998ba7c8a7ee34ef6c1aaa722cffe48356fd0b738058358d4c768b3186c1
+S = 0a67368a305508ce6d25d29c84f552a4a513998990fef4936244f891a2909c30d5fdc9e8a267ecbf3c597138f4a08f7e92bee57d5420eadd700fee864bf78b2614b
+
+Msg = b895788d7828aaeace4f6b61a072ffa344d8ea324962ba6dab5efda93f65bf64a0f2ac6d5721d03ee70e2aef21cdba69fd29040199160e3a293b772ffb961ed694a8dc82800dab79367a4809a864e4aff6bc837aaa868e952b771b76591c0bb82249034e3208e593d85973d3fea753a95b16e221b2561644535c0131fe834ae7
+d = 023048bc16e00e58c4a4c7cc62ee80ea57f745bda35715510ed0fc29f62359ff60b0cf85b673383b87a6e1a792d93ab8549281515850fa24d6a2d93a20a2fff3d6e
+Qx = 0ba3dc98326a15999351a2ec6c59e221d7d9e7ee7152a6f71686c9797f3f330d3150123620d547813ba9d7cc6c6d35cc9a087d07dff780e4821e74ad05f3762efd6
+Qy = 18b051af9824b5f614d23ecadd591e38edbfe910ad6cbebc3e8a6bec11ea90691c17deb3bc5f34a4a3acd90b7b10f521f6ee7b3cfbfdc03b72d5a8783a4a77c3e4c
+k = 06099d2667f06c58798757632d07d8b3efbe9c1323efb0c244be6b12b3b163ba1b7cf5246c98dcc0771665a66696d687af5f28ed664fd87d5093df6427523d4db84
+R = 10dc80ea853064a2ba5a781f108aca3785c5ec0aa45aa05ba31d4de671170797589e863d54a3a986aadf6f670277f50355713dfb27d4ec7e348f787910b3cd668cd
+S = 018572bfad4f62e3694d1f2e6ffd432faed2e2b9d7e3611a07138212f1e79e6c394839f7cfae96bc368422630016fb9346681eadc5f9699e7331c3b5fde6d65e4c6
+
+Msg = 2c5bd848c476e34b427cfe5676692e588e1957957db7b5704492bd02104a38216535607f5d092dc40020130c04a3aaf0f1c52409834926d69a05d3f3188187a71d402a10ba34eac8629b4c6359b1095f30f710219298bf06b9f19bfc299981d7e251ca232a0a85338a7e02464731d1b25d4a1f68baf97064516590644820c998
+d = 02b8b866ce4503bb40ffc2c3c990465c72473f901d6ebe6a119ca49fcec8221b3b4fa7ec4e8e9a10dbd90c739065ad6a3a0dd98d1d6f6dcb0720f25a99357a40938
+Qx = 1b8c7a169d5455f16bfe5df1ba5d6ec9c76e4bad9968d4f5f96be5878a7b6f71d74bfac0076dd278bc4630629f3294646f17d6b6c712b0087e2c4d576039cfdc8b9
+Qy = 18faffd5422dfd1b61432fa77b9a288b2b7d546656c0dcca3032179e6f45ee3cf61d6a447fc51731cb54457343a41569fcf78cef42895f4da5efcb14ea1fc065f8d
+k = 0ac89e813f94042292aa1e77c73773c85cf881a9343b3f50711f13fa17b50f4e5cb04ac5f6fc3106a6ef4c9732016c4e08e301eefac19199459129a41a7589e0628
+R = 05bc7a253a028ee8b7253979b8d689d41d8df6fae7736341f22e28b6faf0cbbdebbd2ef4d73e56d2021af2c646dc15539a7c1e1c4dc9c7674808bd7968d8a66f947
+S = 0fd71575837a43a4cf1c47d0485cfd503c2cf36ebcea0fdef946ad29acb7fb2e7c6daf6b4eb741eb211081aed6207d02569f1518988f275ad94c7fd4735cb18a92e
+
+Msg = 65a0b97048067a0c9040acbb5d7f6e2e6ac462e1e0064a8ce5b5bbf8e57059e25a3ef8c80fc9037ae08f63e63f5bdb9378c322ad9b2daf839fad7a75b1027abb6f70f110247da7e971c7c52914e5a4f7761854432fa16b2a521e7bcaee2c735a87cad20c535bf6d04a87340c229bf9af8647eedca9e2dc0b5aa90f7fea3cdc0a
+d = 0a43b32ad7327ec92c0a67279f417c8ada6f40d6282fe79d6dc23b8702147a31162e646291e8df460d39d7cdbdd7b2e7c6c89509b7ed3071b68d4a518ba48e63662
+Qx = 172fb25a3e22c2a88975d7a814f3e02d5bb74cfb0aaa082c5af580019b429fddd8c7f9e09b6938f62e8c31019b25571aaceef3c0d479079db9a9b533ee8e1670abd
+Qy = 0ff5516223b6cc7c711705f15b91db559014e96d3839249c5c849f2aced228a8998177a1e91177abbb24b57a8ea84d944e0c95da860ae0925f1b40c0e1b7c9e0a46
+k = 0383eda042e06c0297fbd279a2ad40559c5c12ad458f73458eebcc92b308d3c4fcec20a5b59f698e16fa6ea02dba8661b6955f67c052f67b0a56460869f24cfdf7d
+R = 1b9c35356b9d068f33aa22a61370dae44a6cb030497a34fb52af23c6b684677370268f06bb4433be6795a71de570088aec17ce0c9933d2f76c7edce7f406f62fedd
+S = 06f07ea453cfa20ad604ba855332f62834657b0b795684d50c1562a675456e37f4dae45f0df47d8e27e47bc9ce9c9cbba1554c5b94b0b17401b73c8d0c0902c6cc4
+
+Msg = d6e366a87808eea5d39fe77cac4b8c754e865a796062e2ec89f72165cd41fe04c48148068c570e0d29afe9011e7e7a2461f4d9897d8c1fa14b4ff88cab40059d17ab724f4039244e97fcecb07f9ffeec2fb9d6b1896700fe374104a8c44af01a10e93b268d25367bf2bef488b8abcc1ef0e14c3e6e1621b2d58753f21e28b86f
+d = 03c08fdccb089faee91dac3f56f556654a153cebb32f238488d925afd4c7027707118a372f2a2db132516e12ec25f1664953f123ac2ac8f12e0dcbbb61ff40fb721
+Qx = 193301fc0791996ca29e2350723bd9aa0991ddbb4a78348ee72bdcd9ed63ce110ba3496f2ce0331b5c00d4d674c1b70114e17ce44a73c3e16bab14ed1ee924202e4
+Qy = 0aea9b288cfb2933ec0a40efa8e2108774e09b3863b3193d0dac6cc16ccaa5bd5f9ce133aec5cd3b62cbaeec04703e4b61b19572705db38cfaa1907c3d7c785b0cd
+k = 0d0e90d5ee7b5036655ad5c8f6a112c4b21c9449ca91c5c78421e364a2160bbac4428303657bc11ea69f59fb0fe85a41b8f155a362343094456fd2a39f2a79e4804
+R = 1a8c23a2965d365a4c2ffd0802ae8b3a69c6b84a1ba77fd8a5f2f61e8ec3a1dcb336f136e2a997252eaa94caf9b5ad6c9ecff5bf33abf547ca84985bb89908a11d7
+S = 1cc42a2dd97aa42b9df5ea430e0d4cb13106dd6da6e8c9315c96ed7b052db365bbde6960c9a965954a4398c18ea7db9593bbfc3c3b6b3466ff806fccac3de6424ab
+
+Msg = f99e1d272d0f5fb9c4f986e873d070ec638422bc04b47c715595e2cf1a701cdf88bc6c4b20085b357bad12ccba67cac8a5ca07f31ba432f9154ff1fadefd487a83a9c37e49fb70a2f170e58889cab0552e0a3806ccfa2a60d96e346851d84b7de6d1a4b8cf37567dc161a84f13421e3412457d4bc27f6213453c8519a2d7daa2
+d = 0969b515f356f8bb605ee131e80e8831e340902f3c6257270f7dedb2ba9d876a2ae55b4a17f5d9acd46c1b26366c7e4e4e90a0ee5cff69ed9b278e5b1156a435f7e
+Qx = 0fc7ae62b05ed6c34077cbcbb869629528a1656e2e6d403884e79a21f5f612e91fc83c3a8ac1478d58852f0e8ba120d5855983afd1a719949afa8a21aec407516c3
+Qy = 0aa705da6459a90eaa2c057f2e6614fb72fc730d6fdebe70e968c93dbc9858534768ea2666553cd01db132331441823950a17e8d2345a3cab039c22b21bfe7bd3b9
+k = 19029260f88e19360b70c11107a92f06faa64524cfbd9f70fecf02bd5a94f390582a7f4c92c5313bb91dc881596768d86f75a0d6f452094adbe11d6643d1a0b2135
+R = 07f2158e9b9fa995199608263969498923cf918fdc736427c72ce27ce4a3540dce2e8e5e63a8fc7ba46f7fa42480efbf79c6ed39521f6e6ec056079e453e80a89d9
+S = 08e349eed6f1e28b0dbf0a8aeb1d67e59a95b54a699f083db885f50d702f3c6a4069591afaa5b80b3c75efb1674ebd32c7ead0040d115945f9a52ee3a51806cad45
+
+Msg = 91f1ca8ce6681f4e1f117b918ae787a888798a9df3afc9d0e922f51cdd6e7f7e55da996f7e3615f1d41e4292479859a44fa18a5a006662610f1aaa2884f843c2e73d441753e0ead51dffc366250616c706f07128940dd6312ff3eda6f0e2b4e441b3d74c592b97d9cd910f979d7f39767b379e7f36a7519f2a4a251ef5e8aae1
+d = 013be0bf0cb060dbba02e90e43c6ba6022f201de35160192d33574a67f3f79df969d3ae87850071aac346b5f386fc645ed1977bea2e8446e0c5890784e369124418
+Qx = 167d8b8308259c730931db828a5f69697ec0773a79bdedbaaf15114a4937011c5ae36ab0503957373fee6b1c4650f91a3b0c92c2d604a3559dd2e856a9a84f551d9
+Qy = 19d2c1346aadaa3090b5981f5353243300a4ff0ab961c4ee530f4133fe85e6aab5bad42e747eee0298c2b8051c8be7049109ad3e1b572dda1cac4a03010f99f206e
+k = 1a363a344996aac9a3ac040066a65856edfb36f10bb687d4821a2e0299b329c6b60e3547dde03bdbd1afa98b0b75d79cf5aac0ef7a3116266cadf3dfbd46f8a4bfc
+R = 1ff097485faf32ce9e0c557ee064587c12c4834e7f0988cf181d07ba9ee15ae85a8208b61850080fc4bbedbd82536181d43973459f0d696ac5e6b8f2330b179d180
+S = 0306dc3c382af13c99d44db7a84ed813c8719c6ed3bbe751ead0d487b5a4aa018129862b7d282cce0bc2059a56d7722f4b226f9deb85da12d5b40648bf6ec568128
+
+[P-521,SHA-384]
+
+Msg = dbc094402c5b559d53168c6f0c550d827499c6fb2186ae2db15b89b4e6f46220386d6f01bebde91b6ceb3ec7b4696e2cbfd14894dd0b7d656d23396ce920044f9ca514bf115cf98ecaa55b950a9e49365c2f3a05be5020e93db92c37437513044973e792af814d0ffad2c8ecc89ae4b35ccb19318f0b988a7d33ec5a4fe85dfe
+d = 095976d387d814e68aeb09abecdbf4228db7232cd3229569ade537f33e07ed0da0abdee84ab057c9a00049f45250e2719d1ecaccf91c0e6fcdd4016b75bdd98a950
+Qx = 13b4ab7bc1ddf7fd74ca6f75ac560c94169f435361e74eba1f8e759ac70ab3af138d8807aca3d8e73b5c2eb787f6dcca2718122bd94f08943a686b115d869d3f406
+Qy = 0f293c1d627b44e7954d0546270665888144a94d437679d074787959d0d944d8223b9d4b5d068b4fbbd1176a004b476810475cd2a200b83eccd226d08b444a71e71
+k = 0a8d90686bd1104627836afe698effe22c51aa3b651737a940f2b0f9cd72c594575e550adb142e467a3f631f4429514df8296d8f5144df86faa9e3a8f13939ad5b3
+R = 02128f77df66d16a604ffcd1a515e039d49bf6b91a215b814b2a1c88d32039521fbd142f717817b838450229025670d99c1fd5ab18bd965f093cae7accff0675aae
+S = 008dc65a243700a84619dce14e44ea8557e36631db1a55de15865497dbfd66e76a7471f78e510c04e613ced332aa563432a1017da8b81c146059ccc7930153103a6
+
+Msg = 114187efd1f6d6c46473fed0c1922987c79be2144439c6f61183caf2045bfb419f8cddc82267d14540624975f27232117729ccfeacccc7ecd5b71473c69d128152931865a60e6a104b67afe5ed443bdbcdc45372f1a85012bbc4614d4c0c534aacd9ab78664dda9b1f1e255878e8ac59e23c56a686f567e4b15c66f0e7c0931e
+d = 04ceb9896da32f2df630580de979515d698fbf1dd96bea889b98fc0efd0751ed35e6bcf75bc5d99172b0960ffd3d8b683fbffd4174b379fbdecd7b138bb9025574b
+Qx = 0e7a3d30d5bd443549d50e9b297aaa87bc80b5c9e94169602d9d43d6d0c490c0bed8cc2170288b106bdbf4c9f1ce53fd699af0b4c64b494b08520e57dc01ab9a8b0
+Qy = 1d81056d37aec8a75d588f6d05977416e6f24ad0117a7f4450036d695612e7bc2771caed80e580314eebc88c8fc51c453f066e752481f212b57165d67f8a44f375a
+k = 046639c5a3ec15afae5e4a7a418ac760846512d880c359bc2c751b199ce43b10887e861b14127809754dbea47f6cc0140d2817e3f5b9a80ce01abd81f81b748433a
+R = 0f913de91e19bd8f943d542ae357bacc942a0967abc9be6c06239a379db8cc733fa50013e0b0f088bce9d630262feaa33b30d84f91bcf5ce9976e4e740fcb112f84
+S = 08a73a5c9c24235e0d9cecaac653f68ce5a6fb186ce67fa058d6ddbbd4d0a8c4d194e571148e8ad6c8882b4e33d2f60fb23dd7d07a1ae60864e8277918f592b3dc6
+
+Msg = 6744b69fc2420fe00f2352399bd58719e4ecdd6d602e2c80f194d607e58b27a0854745bfd6d504de2eb30b04cee0f44af710dd77e2f816ac3ac5692fad2d1d417893bb0edba2707a4c146a486f8728ca696d35cc52e9c7187c82d4bdb92eb954794e5ad15133f6bfea1f025da32ada710a3014cf11095b3ff69a94d087f17753
+d = 00a8db566bd771a9689ea5188c63d586b9c8b576dbe74c06d618576f61365e90b843d00347fdd084fec4ba229fe671ccdd5d9a3afee821a84af9560cd455ed72e8f
+Qx = 04f5b790cbe2984b71d41af5efed6c6893d15e13f31816d55a9c2926a104eee66f1ada83115d1388551218773b8b9d1138e3e3f027bb4392c90c14fd232580b4a11
+Qy = 0660eb160e9bfc8c5619e70e948e238c6fd37739bc1bb657b8e8436e63628f91992be7e63d9a7359623a1340642777b22026feb51116a6c50c54c3589b9bd39b6cb
+k = 1e7b5e53571a24bd102dd7ad44a4b8d8a4e60e5957bc3c4e5d3c73109f55233f072e572c7892f425ba5e64d3cb7966096bb34a47e26cd5b3e3b44108b310d9f681b
+R = 1a88bcd7e2bdff6e497d943dde432fb3f855a7177c466319cb53b701230c299db030276269685857d1e3f28110e690f2f529c8d18115eb381f313bc891d92ad278e
+S = 146f1984ea879274dfd5e86ad92e564a4de081523ddbb1c397b8f9595911ef2e6501bc081584d5340f7aa47e1af036234ac6f27a5ac31f78dd3b0ff1a62693c630d
+
+Msg = 16001f4dcf9e76aa134b12b867f252735144e523e40fba9b4811b07448a24ef4ccf3e81fe9d7f8097ae1d216a51b6eefc83880885e5b14a5eeee025c4232319c4b8bce26807d1b386ad6a964deb3bdca30ee196cfdd717facfad5c77d9b1d05fdd96875e9675e85029ecbf4f94c524624746b7c42870c14a9a1454acf3354474
+d = 1a300b8bf028449344d0e736145d9dd7c4075a783cb749e1ec7988d60440a07021a25a3de74ea5e3d7bd4ab774d8ad6163adae31877ef0b2bd50e26e9e4be8a7b66
+Qx = 05055b9ad726ba8a48219b0ecbfffb89f8428de895b231f676705b7de9f2022d9ff4e0114ebb52dea342f9bf76b2fb060c020e29d92074ebb1fbfe5290a58c8bc10
+Qy = 0415af7f20a6e945315adbf757316bb486c80780a0a3a15b4b9609f126d7341053a2b726ab63cb46feee527b0bf532b32b477e5671aea23d9b3c3e604b9029954b5
+k = 05a2e92717bb4dab3ee76724d4d9c2d58a32b873e491e36127985f0c9960c610962ca1c4510dba75c98d83beebdc58b1d8678e054640951d11db1bd2d8a4ab8476b
+R = 104a78ce94f878822daaf00ee527fbdbf6cceb3cbb23a2caa485e4109466de8910252f92379ab292cac8d1eda164f880c0067696e733fc8588a27703a3e1f5b8f1f
+S = 1ffe23e8ab5a31668a81161a234ea14879771fe9866f8872eb6edb672e0fe91d2bb75c9767a2dfbac7c15c802211236b22ea41ecd055a0b8b311ffc4255f86d5c67
+
+Msg = a9824a7b810aa16690083a00d422842971baf400c3563baa789c5653fc13416111c0236c67c68e95a13cec0df50324dcc9ae780ce4232607cb57dd9b2c61b382f0fa51fd4e283e2c55ffe272597651659fbd88cd03bfa9652cd54b01a7034c83a602709879e1325c77969bebfd93932ce09a23eae607374602201614ff84b141
+d = 06a253acd79912a74270fc0703ed6507ab20a970f2bc2277f782062092cf0e60ae1ca1bb44dec003169bc25ef6e7123dd04692f77b181a6d7e692e66b09d35a540c
+Qx = 1f15c6b1df156fdd8381cd7446e039435e445f8f36f0247475058da0e371bf72753f6e39f98066bc79370b038c39687ba18e16cb118fe6538b7568c5403c251f6b7
+Qy = 12d2b4f46b854eeae75f1c63f55b76bf0c604d47f870c28a50ecdeb52bba1dd9a0ff12e680804ff864111207652da7dd10b49edf66bb86be00bc06672de91982457
+k = 165faf3727e42fd61345cfa7b93e55fb4bf583b24bdc14ce635b6c99dbd788012f14da9a210b677c44acdd851e672f1a48188d6b8946c0efeebfe8a597ba0090a2c
+R = 1ad9463d2759abd568626548578deefdcd8b2d050ce6d9c7ed05feca20167484b86e89bdcc936fd647e0f8aedd7b6add2b8cf13ff6ff013c2b5540c6c56fda97a0c
+S = 1645a7d0e11015256cfb034adca198695eea6aedd44d9fbf496850ccfed950f43fffd8dbf41e113f2d3837d8a5dd62b2ed580112ff05800b1f73196e5576810e15b
+
+Msg = 90d8bbf714fd2120d2144022bf29520842d9fbd2dc8bb734b3e892ba0285c6a342d6e1e37cc11a62083566e45b039cc65506d20a7d8b51d763d25f0d9eaf3d38601af612c5798a8a2c712d968592b6ed689b88bbab95259ad34da26af9dda80f2f8a02960370bdb7e7595c0a4fffb465d7ad0c4665b5ec0e7d50c6a8238c7f53
+d = 0d5a5d3ddfd2170f9d2653b91967efc8a5157f8720d740dd974e272aab000cc1a4e6c630348754ab923cafb5056fc584b3706628051c557fce67744ee58ba7a56d0
+Qx = 128a4da5fc995678e457ceb3929adee93c280f851abe900fa21f4f809dafad4e33b381e0cd49ce8dd50e2e281cea162bfd60a1d6a1c0ee2228e6a011e171b559ab8
+Qy = 06eb0917cd72256992c49ea527f6bb0315f13d8047794a0f1da1e93737703b1c2a74a00441ef3b47b6a2ff789c49ae32d91cabe7b29247aeec44f6c40a76597a2ca
+k = 03269983a5c2bcc98e9476f5abf82424566b1f08b17204d29e310ece88f99eb677a537f86fe2529e409cfef2c12929644100099e0de2f27c0f0ac11105a4dca935b
+R = 1a5257ae1e8187ba954f535b86ff9b8d6a181a3b95c250d090cb4e9c3bfbd03aa64696a76c569728ef67780d6338d70ce46da40b87a3e49bfe154b93930890dfa93
+S = 05b6ccdfd5c63c7db76d3a0478064a2a376e0e050cb093be795a72a549247c2e4adba9183145c63d46479dbbdcf09986a6f64c09c7e16abc4853f6376c9558b014a
+
+Msg = 09952b1e09995e95bf0022e911c6ab1a463b0a1fdd0eec69117b34af1103c720b57600217de7cd178fef92de5391e550af72a8dcf7badf25b06dd039417f9a7d0f5be88fcd4e9655931d5b605452a667c9d1bae91d3476e7d51cff4108f116a49966fb3a7cff8df1c09734ce5620faf2dccb3dc5d94e7e9ac812da31f6d07a38
+d = 1bcedf920fa148361671b43c64e3186e1937eb1bd4b28cbd84c421472394552889bc05509aa732ef69d732b21b750523fdfd811f36467690fe94e01e64c9d5cbbe9
+Qx = 0d33c151d202a5d4d831348e940b027ee32e4b0b9b48d823a05c67ff3bdaee0189fc6680565f352c062e99968afc643208b4f9c7af185b861658a88c4ad0fcc8ba2
+Qy = 0e4441ddb546468ad8ffa6074f137edfbb81e82e0e7d8f05c4c54598aa996a9cde54cb371f642bfdd4ae7eca5b769696030027129a4183da93567ad142a2dff5183
+k = 046e619b83aac868b26d0b3cbfab55e630e0b55c461985b5d00f94ff3a5ce90ff412cebf46bbd84550d2031d573ca27d924624428360708c8d8491c29eb01d30f2e
+R = 08427c0f0ac0263472cd423c0fb554bf3c851b9c775c566ab0f6878717bd57665830767b05b7789c5c0b078195bd943dc737325552d32877ecb04a7c41bd07cd80c
+S = 10bb6652d6a624c40a7dd06828f15774130d02369ceb1a7d03b553e16e17b7fa5b5401f15885d5e4fc2e55c0c7a1b97871ab02f76386b93a16aa6e7eb65debac6dd
+
+Msg = 0bb0f80cff309c65ff7729c59c517d50fc0ed5be405ef70cb910c3f62c328c90853d4473530b654dda6156e149bc2222a8a7f9be665240e2fbe9d03f78a2356af0bacd1edb84c4801adc8293a8a0bd6123d1cf6ba216aca807a7eb4dca76b493eb6e3dbb69d36f0f00f856222f24d9b93ec34c3b261be2fca0451c00571928e5
+d = 03789e04b3a2a0254ade3380172c150d2fad033885e02ea8bea5b92db3f4adbab190ae423080a1154dfedec694c25eab46ce638be3db4e4cba67bc39f62d6e7db2d
+Qx = 1dbc2cf19627bdccf02432b1761f296275230c150cdde823ce3141ec315d7d05e16b2c29e2a67491078d5316883e933d85b4b10d4f64c477d3c4e0442dc928983a2
+Qy = 07562e720807dd118d3d8b265b3abc61a71fce43e3dce0e7b5ae18b7a4cb01ecc00d39c1f22e150a9a8728997e502144f5b3f6fa9b4cb8a4136212b082ca394e3f6
+k = 0fbccd8d7804bdd1d1d721b5ec74d4ba37603bc306f9fce2ec241853d8e07334e6b4b12c4ecca0c54bd71193dd7146507933a20737c5f3e15085830fab9b30ca57b
+R = 181915a3998d8fa214f9715f4ca928d09c36de168dc15c6970a8a062b5cea2dc969b2437ca17b684f78a1fd583aad8e6c762c8f4ab0c91b86a497145e3ca440d307
+S = 15a6c18c5c77f5470b27d061eafdc26b78561941a3b2ab0f5c81d40899fc053c3d9ed12d7d61e298abbae470009c7b2157731c58d7b16a66fa5abaf5e8a1b8ed394
+
+Msg = 7efacf213382ce30804e78b7256854d759147dba9729c51b2759465715bf2c421034c23dc651c13d6cce95f71fe6a84dfbee5768163ac5789ac0474c5ddf4115684683c5f7c204b33b8bcc0c03ac58f66cef2f53b721fe2fac91ad841126101a88f512a7c2ded38549d9f050d4b7961dda48a1489f026c5d111701762418cfe3
+d = 124700aa9186353e298edefc57bec0c7d0201cca10c1d80dd408d5d71040592b0ac59facdadfa8712445f5977ef8d4854022720c3f02d60e0732dbb2f171fcf1490
+Qx = 0c80fc4cecae5d53348524ddba6a160b735c75b22fdb39af17e2a613d09246e3bb0fd3f2978577f6db5d2118e05c7898024808f8eb8e021d7969cdcf7fc981200bb
+Qy = 1a880c93943fd446d4b3923b574d2221c1bb7b645fb5534dda60e827b497666ff586b77921f7e7f605147947194cffd2fef0678880b89cc0bc7fb74fa96d4b112d7
+k = 01a05238d595ded5c61d3bf6fde257dbf13095af8a5cb3a2e579e8e4c550fe31d12b71cc2dbcb295e6c4fd0fb8c22d1b741c097cc59d826ced1a8771f09983143c4
+R = 132762bc81e9922a8d642e3a9d0218affa21fa2331cfcb9e452545c5981c64a8f7e4cc8e68056023b2aa78bead59061d19c7f646c931163a91e544b106b3be8de9e
+S = 0c3a1b0b000c3169984132add51d611e2cb7069a262a6983d2ae72b459c36e6469509bdb0f473600b8686700b08910779dee9ba83f82e755d4a4ef5f124eb09397f
+
+Msg = 28edff8b9d85f5f58499cc11f492abdfab25e8945975bbaeee910afa2b8fc1295ec61406309ce4e09f4ab4f462959fc2a2786802466eb26d3b01be6919893ae75d0fdc2dc8a82e662550f9fce9627dd364188aaba5c6faa1b2d8a2235adfa5ad0dc140f88a2b2f103f5690e877d07fe8fd30d02d2b2729bd3d8eb5b23a21f54c
+d = 1f532d01af885cb4ad5c329ca5d421c5c021883bd5404c798d617679bb8b094cbb7e15c832fb436325c5302313ce5e496f9513455e7021ffad75777a19b226acfa1
+Qx = 0c0bd76b0027b85bdd879052220da1494d503f6a4bb972105a48ae98e7dda8c2d9fd9336f5646385b961ef68e8464e3a95b00f96614b1a408ceaa2c87b077b6a8fb
+Qy = 17eb7eb5c78db7819af92e8537d110d9f05a5e24f954f4dde21c224d4040f059ec99e051702f390413d2708d18f84d82998c61847475250fb844b20082cbe651a6b
+k = 14e66853e0f7cd3300ebcae06048532e19cbb95bee140edc1c867ce7310637651445b6dfeb1d99d2e32f2ffb787ebe3fe35032277f185d3dad84f95806924550abe
+R = 0c5b3a57161098e2e8e16e0a5ae8ecf4a14df14927eea18ed4925d11dc429dda145159323ba970174b194b9b4608a8fa2373b7a825c5e8bd80574e49698285c2c82
+S = 1a0c038a51796158b42eb5b0dac37aff9ab93b903a47e06ebbdd15946e4bcc9a3b3875b18cf6294c33fc6c3693cef04ed1a43d08951e664c760e2cf3fb4e47490d2
+
+Msg = bae2a8897c742fd99fbf813351cd009d3f2e18d825ca22e115276484bce8f82f8c7c0c21dd2af208404d8ef45bb5a6c41693912b630897d5246801bf0775aa9bbac8be98cb861d172c3563dc59e78a58ed13c66dea496471b3ad0eeae8995293e4ab97373edc1837ffc95ff1cc0c1e90e64ea8680b2ca5f1e09bf86b99b343b6
+d = 11abf508bca68a85a54bc0659e77efad3c86112c9db04db2883e76144aa446918bb4bb0784b0b6a0e9aa47399fe3de5aaecfd8894a0d130bb0c366c40d9d5050745
+Qx = 05c0ea363a3a12633ea39d564587ebdd3a22a175ef32b9ebfc7311304b19cb3a62b5adc36f6afb6a6f7fabbf810ee89fdb72854fefd613e7798e9b9ff5938ea54c6
+Qy = 0bd06a85e47b885c08124b55a3fcc07ca61647cda6efbfdbd21b24d1ea7a4c7300d46cd798e76063aa979adef6f0698b15e5b7ae8a2ab39ab4f50b2d20614db6317
+k = 19cadb8c7eb10565aa4567e0709873918720f0e4b42b4817afb0b0547c70cd1100229deae97a276b9c98ea58b01d4839fee86336d749d123b03e8b1a31166acc110
+R = 0667448a8bbef1c810d40646977dc22f3dfb52a4d80928ded5e976e199cbed02fbd5a08546756ece14548d721a6eb380d0e1a71ad0660dbcac6163c776eedd3e249
+S = 0ae7f0a238daaddb7fb4a1707fe5132daf653f8e19f732347134c96f1dd798f867c479a4a4609a568a15b61afed70790adbde13ac5f68c468d0230852c1a2c22581
+
+Msg = d57a26a9593e72bfc87322524639bcaae5f2252d18b99cdaa03b14445b0b8a4dd53928f66a2e4f202fb25b19cad0eb2f1bfda2ab9b0eb668cdcd0fe72f5d9ef2e45e0218590f7ab9d2c9342202610c698bc786cce108a7d4a6730a13e9ea1b470e781f1237d3f84f44abde808516975546bd89075ef9a9732bfd7ee33b6f4399
+d = 18dbf520d58177e4b7a0627674d220137983f486dd2fd3639f19751804e80df0655db6afd829cdf75238de525e1a7a9f048049b593dd64b4b96cc013f970c05ea1f
+Qx = 18b872690c37995be324ddb5c2bd5462841bb062f8e63da248a853de79c3d6bb9a2eb1e6933afda0998ca43491cc807b08ace2d5336a43d0ab50563a2d3d98755f0
+Qy = 002ff31221aa32aa6546f35e8fe5b9361f938362a5e89e77ae130ba8bce3729e912dfac35a2fd21efe84b45b8be2a340850e4b574e1885b35c2afbe196b57c6cf4c
+k = 098faeb73054639cb2e4442cd68e7b3a13f4b3f397a7b26f303afa40789f8ddd3d918f1ce4f0be53c8cb69c380744e2297d7fc01e2b3daef4ce64dd3a2644234753
+R = 09c0e7649f814f70a8416cb78bc4601472a363fe97f5c587305778169677860dd97f87b5ab07c3a953bc4615fc34634509d6a25621bdded33ed42446d059509c190
+S = 120b90e1cfb8a1b5e530df7b17d1128bc051ca4f1a65dd9c9d9d3c59d2f00c7c1e994c52b8671d40294b4d574d2c04475d5bebeacd3a0d3870a54dc7a4805614f40
+
+Msg = 8fdcf5084b12cfc043dd3416b46274e021bbed95d341d3c500c102a5609d3a34de29f8fa9f0adb611a1f47a97ad981f8129d718fc0d6c709eab1a3490db8d550f34eb905b9e00663543afc5bc155e368e0bc919a8b8c9fa42093603537a5614927efa6be819ed42ececbf1a80a61e6e0a7f9b5bc43b9238e62d5df0571fea152
+d = 002764f5696aa813cd55d30948585f86288ae05aeb264ca157cd09e1d09a10515a849b0791b755ccc656a34707be9e52f5762d290a7d2bcd6de52c600ff862eaf4e
+Qx = 127279c88719dc614db387f102e55104ea1c704ac7f57f3bca936f728439b76556730dd7cde2ac1ad0a4c2c2f036ab6f00cf34cb87ea36113571f300713044106d2
+Qy = 134a0786c31f5f2291b83c50fb579ae4c620b95e5a8bdc0c7e1ee6b996c89d764f1b20403e7faa203f397425ada297045dd8ba0e4b155d4900da249e934faab7991
+k = 08bffb0778cbb06466cecc114b9e89ca243a2b2b5e2597db920bc73a8bbcbe3f57144ad33409ef7faaab430e13f4c42d304d11347360c84972ca20b1539cce3a288
+R = 1f8f504e64a502e51e7c129517931c3b71f0d8a63b19cfe01ff7c951c6525249608b3ef5d00061d77eb6b3d69581adeaa3732c773bbb9b919c3e7c71fdc09f44d06
+S = 058044fc64b340604ffd02a5b2918d76fd6fb59ea895feab7aa218e6f1e8c8f226eb9ee345ef8140183a69272582005077b008006aab11597e808d7ff1e8382c924
+
+Msg = 00669f433934992257bed55861df679804107d7fa491672574a7624949c60049b0533383c88d6896c8de860704c3e6a6aefce83efa57c4d57e9ab253da5d15e1f53ab6dce218b592772ab0bc01fee8e63368e85c0639301456fe2d44cd5396a7f2b22761cd03b80eba7883eede8249a2f5db2183bf00550c5c002f45a5e4fb31
+d = 1b0c9acd3eeb618b4b0de4db402206f0f29adc69d7ad324b6db6601b351f723ac8fe949eeacd34228649bf0126276e5aceb0137d00c30dd858aef2d6b6449de2e89
+Qx = 1811c8884486aaa083ddee1c51cb6e861cb830bd5eaa929f72efadbbd1286566ae7e7ba7fde7e02529900d35ee64591652d28798bfc1bed0d192602a9cf5a7d22e3
+Qy = 06d7fc9dd494816cfd29613d4689af67f7d0a2e6fbad5d4d6e0130189172a1ab601c5ca71deaa8bfcb5a190d49da191672ff6fc048e146cb902acec5eae6d87e60a
+k = 1fdc4f108070af3c66c9ba7b6c1f2603a19ceb4760399df81228cfc7eafde1082b5a0716a3ff82fbe84726f14dd0db3376ca184a78c3c60679bab6cd45f77f9b9ce
+R = 1ec310339ff056faeb341c4499c43782078b04be1725ae9a6cdcb6011c46d1a4eb3d75c358225e4ec142fd1cd344186f5eb597f7ba559ddfa954824365d5b6edaec
+S = 005b679a33fdb7e04834f071cd0ac514c04add9f2614ab9bbd9b407b1420fed3f3e02a108e7e279899e43dcf64ae4083c289a87cd7d2103bdc036a95d36800ac7c6
+
+Msg = 4be81dcfab39a64d6f00c0d7fff94dabdf3473dc49f0e12900df328d6584b854fbaebaf3194c433e9e21743342e2dd056b445c8aa7d30a38504b366a8fa889dc8ecec35b3130070787e7bf0f22fab5bea54a07d3a75368605397ba74dbf2923ef20c37a0d9c64caebcc93157456b57b98d4becb13fecb7cc7f3740a6057af287
+d = 181e1037bbec7ca2f271343e5f6e9125162c8a8a46ae8baa7ca7296602ae9d56c994b3b94d359f2b3b3a01deb7a123f07d9e0c2e729d37cc5abdec0f5281931308a
+Qx = 0cfa5a8a3f15eb8c419095673f1d0bd63b396ff9813c18dfe5aa31f40b50b82481f9ed2edd47ae5ea6a48ea01f7e0ad0000edf7b66f8909ee94f141d5a07efe315c
+Qy = 18af728f7318b96d57f19c1104415c8d5989565465e429bc30cf65ced12a1c5856ac86fca02388bc151cf89959a4f048597a9e728f3034aa39259b59870946187bf
+k = 09078beaba465ba7a8b3624e644ac1e97c654533a58ac755e90bd606e2214f11a48cb51f9007865a0f569d967ea0370801421846a89f3d09eb0a481289270919f14
+R = 19cf91a38cc20b9269e7467857b1fc7eabb8cea915a3135f727d471e5bfcfb66d321fabe283a2cf38d4c5a6ecb6e8cbee1030474373bb87fcdfcc95cf857a8d25d0
+S = 1cf9acd9449c57589c950f287842f9e2487c5610955b2b5035f6aacfd2402f511998a1a942b39c307fc2bcab2c8d0dae94b5547ddccfb1012ca985b3edf42bbba8b
+
+[P-521,SHA-512]
+
+Msg = 9ecd500c60e701404922e58ab20cc002651fdee7cbc9336adda33e4c1088fab1964ecb7904dc6856865d6c8e15041ccf2d5ac302e99d346ff2f686531d25521678d4fd3f76bbf2c893d246cb4d7693792fe18172108146853103a51f824acc621cb7311d2463c3361ea707254f2b052bc22cb8012873dcbb95bf1a5cc53ab89f
+d = 0f749d32704bc533ca82cef0acf103d8f4fba67f08d2678e515ed7db886267ffaf02fab0080dca2359b72f574ccc29a0f218c8655c0cccf9fee6c5e567aa14cb926
+Qx = 061387fd6b95914e885f912edfbb5fb274655027f216c4091ca83e19336740fd81aedfe047f51b42bdf68161121013e0d55b117a14e4303f926c8debb77a7fdaad1
+Qy = 0e7d0c75c38626e895ca21526b9f9fdf84dcecb93f2b233390550d2b1463b7ee3f58df7346435ff0434199583c97c665a97f12f706f2357da4b40288def888e59e6
+k = 03af5ab6caa29a6de86a5bab9aa83c3b16a17ffcd52b5c60c769be3053cdddeac60812d12fecf46cfe1f3db9ac9dcf881fcec3f0aa733d4ecbb83c7593e864c6df1
+R = 04de826ea704ad10bc0f7538af8a3843f284f55c8b946af9235af5af74f2b76e099e4bc72fd79d28a380f8d4b4c919ac290d248c37983ba05aea42e2dd79fdd33e8
+S = 087488c859a96fea266ea13bf6d114c429b163be97a57559086edb64aed4a18594b46fb9efc7fd25d8b2de8f09ca0587f54bd287299f47b2ff124aac566e8ee3b43
+
+Msg = b3c63e5f5a21c4bfe3dbc644354d9a949186d6a9e1dd873828782aa6a0f1df2f64114a430b1c13fe8a2e09099e1ed05ef70de698161039ded73bcb50b312673bb073f8a792ac140a78a8b7f3586dffb1fc8be4f54516d57418ccc9945025ce3acf1eb84f69ceee5e9bd10c18c251dbc481562cd3aae54b54ab618cb1eeda33cf
+d = 1a4d2623a7d59c55f408331ba8d1523b94d6bf8ac83375ceb57a2b395a5bcf977cfc16234d4a97d6f6ee25a99aa5bff15ff535891bcb7ae849a583e01ac49e0e9b6
+Qx = 04d5c8afee038984d2ea96681ec0dccb6b52dfa4ee2e2a77a23c8cf43ef19905a34d6f5d8c5cf0981ed804d89d175b17d1a63522ceb1e785c0f5a1d2f3d15e51352
+Qy = 014368b8e746807b2b68f3615cd78d761a464ddd7918fc8df51d225962fdf1e3dc243e265100ff0ec133359e332e44dd49afd8e5f38fe86133573432d33c02fa0a3
+k = 0bc2c0f37155859303de6fa539a39714e195c37c6ea826e224c8218584ae09cd0d1cc14d94d93f2d83c96e4ef68517fdb3f383da5404e5a426bfc5d424e253c181b
+R = 1a3c4a6386c4fb614fba2cb9e74201e1aaa0001aa931a2a939c92e04b8344535a20f53c6e3c69c75c2e5d2fe3549ed27e6713cb0f4a9a94f6189eb33bff7d453fce
+S = 16a997f81aa0bea2e1469c8c1dab7df02a8b2086ba482c43af04f2174831f2b1761658795adfbdd44190a9b06fe10e578987369f3a2eced147cff89d8c2818f7471
+
+Msg = 6e0f96d56505ffd2d005d5677dbf926345f0ff0a5da456bbcbcfdc2d33c8d878b0bc8511401c73168d161c23a88b04d7a9629a7a6fbcff241071b0d212248fcc2c94fa5c086909adb8f4b9772b4293b4acf5215ea2fc72f8cec57b5a13792d7859b6d40348fc3ba3f5e7062a19075a9edb713ddcd391aefc90f46bbd81e2557b
+d = 14787f95fb1057a2f3867b8407e54abb91740c097dac5024be92d5d65666bb16e4879f3d3904d6eab269cf5e7b632ab3c5f342108d1d4230c30165fba3a1bf1c66f
+Qx = 0c2d540a7557f4530de35bbd94da8a6defbff783f54a65292f8f76341c996cea38795805a1b97174a9147a8644282e0d7040a6f83423ef2a0453248156393a1782e
+Qy = 119f746c5df8cec24e4849ac1870d0d8594c799d2ceb6c3bdf891dfbd2242e7ea24d6aec3166214734acc4cbf4da8f71e2429c5c187b2b3a048527c861f58a9b97f
+k = 186cd803e6e0c9925022e41cb68671adba3ead5548c2b1cd09348ab19612b7af3820fd14da5fe1d7b550ed1a3c8d2f30592cd7745a3c09ee7b5dcfa9ed31bdd0f1f
+R = 10ed3ab6d07a15dc3376494501c27ce5f78c8a2b30cc809d3f9c3bf1aef437e590ef66abae4e49065ead1af5f752ec145acfa98329f17bca9991a199579c41f9229
+S = 08c3457fe1f93d635bb52df9218bf3b49a7a345b8a8a988ac0a254340546752cddf02e6ce47eee58ea398fdc9130e55a4c09f5ae548c715f5bcd539f07a34034d78
+
+Msg = 3f12ab17af3c3680aad22196337cedb0a9dba22387a7c555b46e84176a6f8418004552386ada4deec59fdabb0d25e1c6668a96f100b352f8dabd24b2262bd2a3d0f825602d54150bdc4bcbd5b8e0ca52bc8d2c70ff2af9b03e20730d6bd9ec1d091a3e5c877259bcff4fd2c17a12bfc4b08117ec39fe4762be128d0883a37e9d
+d = 15807c101099c8d1d3f24b212af2c0ce525432d7779262eed0709275de9a1d8a8eeeadf2f909cf08b4720815bc1205a23ad1f825618cb78bde747acad8049ca9742
+Qx = 160d7ea2e128ab3fabd1a3ad5455cb45e2f977c2354a1345d4ae0c7ce4e492fb9ff958eddc2aa61735e5c1971fa6c99beda0f424a20c3ce969380aaa52ef5f5daa8
+Qy = 14e4c83f90d196945fb4fe1e41913488aa53e24c1d2142d35a1eed69fed784c0ef44d71bc21afe0a0065b3b87069217a5abab4355cf8f4ceae5657cd4b9c8008f1f
+k = 096731f8c52e72ffcc095dd2ee4eec3da13c628f570dba169b4a7460ab471149abdede0b63e4f96faf57eab809c7d2f203fd5ab406c7bd79869b7fae9c62f97c794
+R = 1e2bf98d1186d7bd3509f517c220de51c9200981e9b344b9fb0d36f34d969026c80311e7e73bb13789a99e0d59e82ebe0e9595d9747204c5f5550c30d934aa30c05
+S = 12fed45cc874dc3ed3a11dd70f7d5c61451fbea497dd63e226e10364e0718d3722c27c7b4e5027051d54b8f2a57fc58bc070a55b1a5877b0f388d768837ef2e9cec
+
+Msg = a1eed24b3b7c33296c2491d6ee092ec6124f85cf566bb5bc35bffb5c734e34547242e57593e962fb76aee9e800eed2d702cc301499060b76406b347f3d1c86456978950737703c8159001e6778f69c734a56e5ce5938bd0e0de0877d55adeee48b0d8dfa4ac65fd2d3ce3e12878bac5c7014f9284d161b2a3e7d5c88569a45f6
+d = 18692def0b516edcdd362f42669999cf27a65482f9358fcab312c6869e22ac469b82ca9036fe123935b8b9ed064acb347227a6e377fb156ec833dab9f170c2ac697
+Qx = 1ceee0be3293d8c0fc3e38a78df55e85e6b4bbce0b9995251f0ac55234140f82ae0a434b2bb41dc0aa5ecf950d4628f82c7f4f67651b804d55d844a02c1da6606f7
+Qy = 1f775eb6b3c5e43fc754052d1f7fc5b99137afc15d231a0199a702fc065c917e628a54e038cbfebe05c90988b65183b368a2061e5b5c1b025bbf2b748fae00ba297
+k = 161cf5d37953e09e12dc0091dc35d5fb3754c5c874e474d2b4a4f1a90b870dff6d99fb156498516e25b9a6a0763170702bb8507fdba4a6131c7258f6ffc3add81fd
+R = 14dfa43046302b81fd9a34a454dea25ccb594ace8df4f9d98556ca5076bcd44b2a9775dfaca50282b2c8988868e5a31d9eb08e794016996942088d43ad3379eb9a1
+S = 120be63bd97691f6258b5e78817f2dd6bf5a7bf79d01b8b1c3382860c4b00f89894c72f93a69f3119cb74c90b03e9ede27bd298b357b9616a7282d176f3899aaa24
+
+Msg = 9aace26837695e6596007a54e4bccdd5ffb16dc6844140e2eeeb584b15acb2bbffd203c74440b6ee8db676fd200b4186a8c3e957c19e74d4d865ada83f80655323dfa3570907ed3ce853b6e8cc375ed2d758a2f5ad265dd3b47650517a49b3d02df9e0c60c21576378c2b3a08481eec129b2a75608e13e6420127a3a63c8a3f1
+d = 0a63f9cdefbccdd0d5c9630b309027fa139c31e39ca26686d76c22d4093a2a5e5ec4e2308ce43eb8e563187b5bd811cc6b626eace4063047ac0420c3fdcff5bdc04
+Qx = 14cab9759d4487987b8a00afd16d7199585b730fb0bfe63796272dde9135e7cb9e27cec51207c876d9214214b8c76f82e7363f5086902a577e1c50b4fbf35ce9966
+Qy = 1a83f0caa01ca2166e1206292342f47f358009e8b891d3cb817aec290e0cf2f47e7fc637e39dca03949391839684f76b94d34e5abc7bb750cb44486cce525eb0093
+k = 01e51fd877dbbcd2ab138fd215d508879298d10c7fcbdcc918802407088eb6ca0f18976a13f2c0a57867b0298512fc85515b209c4435e9ef30ab01ba649838bc7a0
+R = 11a1323f6132d85482d9b0f73be838d8f9e78647934f2570fededca7c234cc46aa1b97da5ac1b27b714f7a171dc4209cbb0d90e4f793c4c192dc039c31310d6d99b
+S = 0386a5a0fc55d36ca7231a9537fee6b9e51c2255363d9c9e7cb7185669b302660e23133eb21eb56d305d36e69a79f5b6fa25b46ec61b7f699e1e9e927fb0bceca06
+
+Msg = ac2175940545d4fbab6e2e651c6830aba562e0c11c919e797c43eff9f187a68a9e5a128e3e2a330b955a3f4577d3f826529ad1b03d7b60f7ad678f005053b41dc0f8d267f3685c6abe1a0e9a733c44b2f3ca48b90806f935141c842e3a6c06a58f5343d75e3585971a734f4ae1074ce5b54f74bd9342f4bbca738d260393f43e
+d = 024f7d67dfc0d43a26cc7c19cb511d30a097a1e27e5efe29e9e76e43849af170fd9ad57d5b22b1c8840b59ebf562371871e12d2c1baefc1abaedc872ed5d2666ad6
+Qx = 09da1536154b46e3169265ccba2b4da9b4b06a7462a067c6909f6c0dd8e19a7bc2ac1a47763ec4be06c1bec57d28c55ee936cb19588cc1398fe4ea3bd07e6676b7f
+Qy = 14150cdf25da0925926422e1fd4dcfcffb05bdf8682c54d67a9bd438d21de5af43a15d979b320a847683b6d12ac1383a7183095e9da491c3b4a7c28874625e70f87
+k = 1c1308f31716d85294b3b5f1dc87d616093b7654907f55289499b419f38ceeb906d2c9fe4cc3d80c5a38c53f9739311b0b198111fede72ebde3b0d2bc4c2ef090d2
+R = 00dbf787ce07c453c6c6a67b0bf6850c8d6ca693a3e9818d7453487844c9048a7a2e48ff982b64eb9712461b26b5127c4dc57f9a6ad1e15d8cd56d4fd6da7186429
+S = 0c6f1c7774caf198fc189beb7e21ca92ceccc3f9875f0e2d07dc1d15bcc8f210b6dd376bf65bb6a454bf563d7f563c1041d62d6078828a57538b25ba54723170665
+
+Msg = 6266f09710e2434cb3da3b15396556765db2ddcd221dce257eab7399c7c490135925112932716af1434053b8b9fe340563e57a0b9776f9ac92cbb5fba18b05c0a2fafbed7240b3f93cd1780c980ff5fe92610e36c0177cabe82367c84cee9020cf26c1d74ae3eb9b9b512cb8b3cb3d81b17cf20dc76591b2b394ef1c62ac12ee
+d = 0349471460c205d836aa37dcd6c7322809e4e8ef81501e5da87284b267d843897746b33016f50a7b702964910361ed51d0afd9d8559a47f0b7c25b2bc952ce8ed9e
+Qx = 00bbd4e8a016b0c254e754f68f0f4ed081320d529ecdc7899cfb5a67dd04bc85b3aa6891a3ed2c9861ae76c3847d81780c23ad84153ea2042d7fd5d517a26ff3ce4
+Qy = 0645953afc3c1b3b74fdf503e7d3f982d7ee17611d60f8eb42a4bddbec2b67db1f09b54440c30b44e8071d404658285cb571462001218fc8c5e5b98b9fae28272e6
+k = 00eb2bd8bb56b9d2e97c51247baf734cc655c39e0bfda35375f0ac2fe82fad699bf1989577e24afb33c3868f91111e24fefe7dec802f3323ac013bec6c048fe5568
+R = 14bf63bdbc014aa352544bd1e83ede484807ed760619fa6bc38c4f8640840195e1f2f149b29903ca4b6934404fb1f7de5e39b1ea04dba42819c75dbef6a93ebe269
+S = 05d1bcf2295240ce4415042306abd494b4bda7cf36f2ee2931518d2454faa01c606be120b057062f2f3a174cb09c14f57ab6ef41cb3802140da22074d0e46f908d4
+
+Msg = 3de9e617a6868dca1a1432d503f923535da3f9b34426b2a4822174399c73b1c1ee67311410a58c17202ac767844b2024d8aa21a205707d93865693ac25a24fc87034fa3a7a7e27c3344cb03b87602c15180a5fe6a9dd90cd11af4a0f150207bf2d83f55b12c088adae99aa8cfa659311b3a25beb99056643760d6a282126b9b2
+d = 07788d34758b20efc330c67483be3999d1d1a16fd0da81ed28895ebb35ee21093d37ea1ac808946c275c44454a216195eb3eb3aea1b53a329eca4eb82dd48c784f5
+Qx = 0157d80bd426f6c3cee903c24b73faa02e758607c3e102d6e643b7269c299684fdaba1acddb83ee686a60acca53cddb2fe976149205c8b8ab6ad1458bc00993cc43
+Qy = 16e33cbed05721b284dacc8c8fbe2d118c347fc2e2670e691d5d53daf6ef2dfec464a5fbf46f8efce81ac226915e11d43c11c8229fca2327815e1f8da5fe95021fc
+k = 0a73477264a9cc69d359464abb1ac098a18c0fb3ea35e4f2e6e1b060dab05bef1255d9f9c9b9fbb89712e5afe13745ae6fd5917a9aedb0f2860d03a0d8f113ea10c
+R = 07e315d8d958b8ce27eaf4f3782294341d2a46fb1457a60eb9fe93a9ae86f3764716c4f5f124bd6b114781ed59c3f24e18aa35c903211b2f2039d85862932987d68
+S = 1bcc1d211ebc120a97d465b603a1bb1e470109e0a55d2f1b5c597803931bd6d7718f010d7d289b31533e9fcef3d141974e5955bc7f0ee342b9cad05e29a3dded30e
+
+Msg = aa48851af7ef17abe233163b7185130f4646203c205e22bcc2a5a3697bcab998c73a9ffe1d3ea0b7978ce7df937a72586eb5ca60b0d939a7d1c115c820171c89c8116b7e2c7b98cf0f14e4c4df3cb2f319ad3ab0ea25ff14526ddc037469f000bf82100acd4cdf94feb4eba4ea1726f0569336604a473aee67d71afebb569209
+d = 1f98696772221e6cccd5569ed8aed3c435ee86a04689c7a64d20c30f6fe1c59cc10c6d2910261d30c3b96117a669e19cfe5b696b68feeacf61f6a3dea55e6e5837a
+Qx = 07002872c200e16d57e8e53f7bce6e9a7832c387f6f9c29c6b75526262c57bc2b56d63e9558c5761c1d62708357f586d3aab41c6a7ca3bf6c32d9c3ca40f9a2796a
+Qy = 1fe3e52472ef224fb38d5a0a14875b52c2f50b82b99eea98d826c77e6a9ccf798de5ffa92a0d65965f740c702a3027be66b9c844f1b2e96c134eb3fdf3edddcf11c
+k = 1a277cf0414c6adb621d1cc0311ec908401ce040c6687ed45a0cdf2910c42c9f1954a4572d8e659733d5e26cbd35e3260be40017b2f5d38ec42315f5c0b056c596d
+R = 0d732ba8b3e9c9e0a495249e152e5bee69d94e9ff012d001b140d4b5d082aa9df77e10b65f115a594a50114722db42fa5fbe457c5bd05e7ac7ee510aa68fe7b1e7f
+S = 134ac5e1ee339727df80c35ff5b2891596dd14d6cfd137bafd50ab98e2c1ab4008a0bd03552618d217912a9ec502a902f2353e757c3b5776309f7f2cfebf913e9cd
+
+Msg = b0d5d52259af364eb2d1a5027e5f7d0afe4b999cc5dd2268cfe76f51d2f17b541bdd7867e23a1bb897705153d9432a24012108979c6a2c9e2567c9531d012f9e4be764419491a52eae2e127430b0ab58cb8e216515a821b3db206447c235bf44ee304201b483b2a88844abaa18bca0147dfff7e502397dd62e15524f67eb2df2
+d = 13c3852a6bc8825b45fd7da1754078913d77f4e586216a6eb08b6f03adce7464f5dbc2bea0eb7b12d103870ef045f53d67e3600d7eba07aac5db03f71b64db1cceb
+Qx = 0c97a4ebcbbe701c9f7be127e87079edf479b76d3c14bfbee693e1638e5bff8d4705ac0c14597529dbe13356ca85eb03a418edfe144ce6cbf3533016d4efc29dbd4
+Qy = 11c75b7a8894ef64109ac2dea972e7fd5f79b75dab1bf9441a5b8b86f1dc1324426fa6cf4e7b973b44e3d0576c52e5c9edf8ce2fc18cb3c28742d44419f044667f8
+k = 1e25b86db041f21c2503d547e2b1b655f0b99d5b6c0e1cf2bdbd8a8c6a053f5d79d78c55b4ef75bff764a74edc920b35536e3c470b6f6b8fd53898f3bbc467539ef
+R = 1dce45ea592b34d016497882c48dc0c7afb1c8e0f81a051800d7ab8da9d237efd892207bc9401f1d30650f66af8d5349fc5b19727756270722d5a8adb0a49b72d0a
+S = 0b79ffcdc33e028b1ab894cb751ec792a69e3011b201a76f3b878655bc31efd1c0bf3b98aea2b14f262c19d142e008b98e890ebbf464d3b025764dd2f73c4251b1a
+
+Msg = 9599788344976779383a7a0812a096943a1f771ee484d586af1a06207478e4c0be9c200d42460fe837e24b266c8852d80d3c53cc52ffb1913fc3261145fc6da575611efd16c026059a2e64f802517ffd1b6b34de10ad2909c65c2155e8d939b8115400c1d793d23955b15f5d1c13c962ff92b4a815cee0e10f8e14e1f6e6cd38
+d = 1654eaa1f6eec7159ee2d36fb24d15d6d33a128f36c52e2437f7d1b5a44ea4fa965c0a26d0066f92c8b82bd136491e929686c8bde61b7c704daab54ed1e1bdf6b77
+Qx = 1f269692c47a55242bb08731ff920f4915bfcecf4d4431a8b487c90d08565272c52ca90c47397f7604bc643982e34d05178e979c2cff7ea1b9eaec18d69ca7382de
+Qy = 0750bdd866fba3e92c29599c002ac6f9e2bf39af8521b7b133f70510e9918a94d3c279edec97ab75ecda95e3dd7861af84c543371c055dc74eeeff7061726818327
+k = 1b7519becd00d750459d63a72f13318b6ac61b8c8e7077cf9415c9b4b924f35514c9c28a0fae43d06e31c670a873716156aa7bc744577d62476e038b116576a9e53
+R = 183bddb46c249e868ef231a1ebd85d0773bf8105a092ab7d884d677a1e9b7d6014d6358c09538a99d9dca8f36f163ac1827df420c3f9360cc66900a9737a7f756f3
+S = 0d05ee3e64bac4e56d9d8bd511c8a43941e953cba4e5d83c0553acb87091ff54f3aad4d69d9f15e520a2551cc14f2c86bb45513fef0295e381a7635486bd3917b50
+
+Msg = fdde51acfd04eb0ad892ce9d6c0f90eb91ce765cbe3ce9d3f2defe8f691324d26b968b8b90e77706b068585f2a3ee7bf3e910528f7403c5af745a6f9d7ba6c53abd885c3b1be583415b128f4d3f224daf8563476bd9aa61e9c8518c144335f8f879c03696bddbe3ac37a8fbede29861611feaa87e325e2f60278b4893ed57fb0
+d = 1cba5d561bf18656991eba9a1dde8bde547885ea1f0abe7f2837e569ca52f53df5e64e4a547c4f26458b5d9626ed6d702e5ab1dd585cf36a0c84f768fac946cfd4c
+Qx = 12857c2244fa04db3b73db4847927db63cce2fa6cb22724466d3e20bc950a9250a15eafd99f236a801e5271e8f90d9e8a97f37c12f7da65bce8a2c93bcd25526205
+Qy = 0f394e37c17d5b8e35b488fa05a607dbc74264965043a1fb60e92edc212296ae72d7d6fe2e3457e67be853664e1da64f57e44bd259076b3bb2b06a2c604fea1be9d
+k = 0e790238796fee7b5885dc0784c7041a4cc7ca4ba757d9f7906ad1fcbab5667e3734bc2309a48047442535ff89144b518f730ff55c0c67eeb4c880c2dfd2fb60d69
+R = 1d7ce382295a2a109064ea03f0ad8761dd60eefb9c207a20e3c5551e82ac6d2ee5922b3e9655a65ba6c359dcbf8fa843fbe87239a5c3e3eaecec0407d2fcdb687c2
+S = 161963a6237b8955a8a756d8df5dbd303140bb90143b1da5f07b32f9cb64733dc6316080924733f1e2c81ade9d0be71b5b95b55666026a035a93ab3004d0bc0b19f
+
+Msg = beb34c997f905c77451ac392f7957a0ab8b23325bd5c63ca31c109ac8f655a1e3094240cb8a99284f8091de2ab9a7db2504d16251980b86be89ec3a3f41162698bab51848880633e0b71a38f8896335853d8e836a2454ecab2acdcc052c8f659be1d703b13ae1b090334ac50ab0137ddb5e8b924c0e3d2e5789daaef2fdd4a1e
+d = 0972e7ff25adf8a032535e5b19463cfe306b90803bf27fabc6046ae0807d2312fbab85d1da61b80b2d5d48f4e5886f27fca050b84563aee1926ae6b2564cd756d63
+Qx = 1d7f1e9e610619daa9d2efa563610a371677fe8b58048fdc55a98a49970f6afa6649c516f9c72085ca3722aa595f45f2803402b01c832d28aac63d9941f1a25dfea
+Qy = 1571facce3fcfe733a8eef4e8305dfe99103a370f82b3f8d75085414f2592ad44969a2ef8196c8b9809f0eca2f7ddc71c47879e3f37a40b9fecf97992b97af29721
+k = 0517f6e4002479dc89e8cbb55b7c426d128776ca82cf81be8c1da9557178783f40e3d047db7e77867f1af030a51de470ee3128c22e9c2d642d71e4904ab5a76edfa
+R = 1c3262a3a3fb74fa5124b71a6c7f7b7e6d56738eabaf7666b372b299b0c99ee8a16be3df88dd955de093fc8c049f76ee83a4138cee41e5fe94755d27a52ee44032f
+S = 072fd88bb1684c4ca9531748dfce4c161037fcd6ae5c2803b7117fb60d3db5df7df380591aaf3073a3031306b76f062dcc547ded23f6690293c34a710e7e9a226c3
+
+Msg = 543c374af90c34f50ee195006d5f9d8dd986d09ad182fcbefa085567275eee1e742bfe0af3d058675adeb5b9f87f248b00a9fbd2aa779129123a5b983f2f26fc3caf2ea34277550c22fe8c814c739b46972d50232993cddd63a3c99e20f5c5067d9b57e2d5db94317a5a16b5c12b5c4cafbc79cbc2f9940f074bbc7d0dc71e90
+d = 1f0ec8da29295394f2f072672db014861be33bfd9f91349dad5566ff396bea055e53b1d61c8c4e5c9f6e129ed75a49f91cce1d5530ad4e78c2b793a63195eb9f0da
+Qx = 09ec1a3761fe3958073b9647f34202c5e8ca2428d056facc4f3fedc7077fa87f1d1eb30cc74f6e3ff3d3f82df2641cea1eb3ff1529e8a3866ae2055aacec0bf68c4
+Qy = 0bed0261b91f664c3ff53e337d8321cb988c3edc03b46754680097e5a8585245d80d0b7045c75a9c5be7f599d3b5eea08d828acb6294ae515a3df57a37f903ef62e
+k = 0ac3b6d61ebda99e23301fa198d686a13c0832af594b289c9a55669ce6d62011384769013748b68465527a597ed6858a06a99d50493562b3a7dbcee975ad34657d8
+R = 0cef3f4babe6f9875e5db28c27d6a197d607c3641a90f10c2cc2cb302ba658aa151dc76c507488b99f4b3c8bb404fb5c852f959273f412cbdd5e713c5e3f0e67f94
+S = 0097ed9e005416fc944e26bcc3661a09b35c128fcccdc2742739c8a301a338dd77d9d13571612a3b9524a6164b09fe73643bbc31447ee31ef44a490843e4e7db23f
+
+
+[K-233,SHA-224]
+
+Msg = f23f784fe136c9fc0d169503d361e9c6148b0f1fbdcae0a97fae1af7033ddef25cb7489c9963cfcb009a8cbfe44a8510a64a073eb1deae4c324ceb9302008c92c69b2dafcc9077fd3cc3c7c119edc3ced36d176ceaa55ac036bf7f07f6fa215e8bb8196e59a5e1c9af4f98b90ab4970885bd7015fa26a09e03c7cf6b4b23d929
+d = 04c1d414696cc3657dd9df73ace56eda2636769ce7082e064c260be45a5
+Qx = 1f228c0a75b057eb07fe7ce8223ed4163148c1fdab61e0f787271f836a9
+Qy = 0cdfa5655d96ffd5ffb6027bfaa04da7b5d8fbdbb6202c8bb79f056ce43
+k = 058f8511089fcd59324469f6736b92693afe26bd4719e198f1f2287dc5f
+R = 016bafefb4933ffd00bd1db6d6c4fac8a06375603adc0aa2a5664083ff4
+S = 03bcb84b8f1990cfc7b88f2b8cc817105cd8e150808e7c87b310cdc47e3
+
+Msg = 400bcb297552bb37f2f8135a9314a35f5126788bb6fa4dc74152731ff64c5dab4b902103d85443dec20e16b1d6629930cdc2bd183d4099f0e96295a63c2fe266f5e9d050c401a8681b4a438efe53cbd8f2f43e2a31e9f88926a9c82917d873f6e8cd5ff5eb8c1ca36126b0bfc8c2b0e85a7c9e7a45f1875ca9c82019ebedb729
+d = 027cb1d84865a16992476c9e353283d5d6a40c349a8e9179d1b1f403531
+Qx = 1191227d064176f4ab020faea61330df5eb59163ecb4ea59c23e6f1f6c8
+Qy = 12dbfbf85b3624b9f56446f840602f9b839bab1368295b3ae919cb07c07
+k = 01a41af270269be052a62a9879638e3432a1479b05776ce61f45c0c361b
+R = 041a5f1d28b70bfa2925b9428ab8bac9fa174d88ae27d754824c7d16ead
+S = 044d359065672b3d3dfe8389fbc6fc751ca6a46820626c466174fb9b922
+
+Msg = 5f74d4b35c49fa454c97c05fdb6b9f6822cf1a2295f15bd766dbcb413d77c910bd8f4147e8f317fac2300fa21cb80134d1b6f8ae8e50518c1f648a28506e419f5a6e8f05abffdb3dd2587606c7e9c223ecff4f46b121216730ea13202b59128a7616bb2fd23a7e4a5aa08641cc07b669641313febfc88d64d99447353dae3f06
+d = 031b443f46c4b5224237fac1022ee1570173f664aba0c84dbaa4246bdc1
+Qx = 05f57b0e5f2e175006f4058cbb4ca9a0cac912c551ef1b94e97498fcc5a
+Qy = 0f3a554d077b751478f8a2b7c2a9cf15effed958e0ac1a9e3db1e023c5f
+k = 07ff6ef3026c5a960e632beeb7313b3bca0baec76cea1fd9b82cedc3245
+R = 0099741698549c32a4e86aab6194527cea703ff869849c538a938585a83
+S = 02ad706c6f5dcff512498d84f1877eb997dfbe9b3d13b339917632d3cb1
+
+Msg = 8f92096876d9f81bcd992369d42d0b5877ac969004d17c8627c58d8b8b7bbf7a37e8cb6afa962b9b043bbbaa5bef4a5ee38d8bd31cb5866b828265a2f4102a616f87009cd346fcb8af5519fb577c60d8792472232f33dc615655e53d2b715b15a2697b492f108b7906e1e3597c6911f8cc30c7121ae338a6b747ec368f8e4a36
+d = 048f6ca29f35f253a4962734357c995920967b9eeff1ba5fd2080bfede5
+Qx = 12b7ca7c21292f8795b2fbfd63a28c5a4ec8c850d6240f973c903bc8170
+Qy = 1be9855e5c5a5064c27d1862010b2fd0d7be5a0180c861a288ceac89d6d
+k = 07dcb9725323fd7668991ce9a907b7129d53fae9016e253c53d057d195d
+R = 0498c4fca6ed7c2998347b464d3e562a74b0e4f3a6c1dc453aaa61bb710
+S = 03a77a13f011404d5c5341dcd2ca44dc2b08f21f09f524045c281fb221e
+
+Msg = 3d275dbde44494c45fc15fe89e2ae32aa26426a17e923e895c7941a5582fb95df4d49873ab1bde358017f336b911b886b626b744806ab8113418473c441f1964159ded1b12122d53ac56573167588e4b55f36b8bca8c67823883a51fb6e7f204d1c6b07ea49b577bfab9ca6b8d51f72268b022e3a4db6f9d265ee8382f9b7b66
+d = 019b940eabbe682f961d9f3d90432e347fef3910e641656825d775705b1
+Qx = 1efcc9f4576047c43eab1c13e0547b1c5ec1cd2afd2345fda72b5e1b50f
+Qy = 0c7b5968af47e58f4ec15c0cd82ccd0b9f5bfde06c7f86fe5cd0105d693
+k = 03f783a94d1de73e4593f5d6d02238cfa0486e3ddf2bc0b95a528038e3c
+R = 013c467531f3f6508534ad072edb210e4182ce5a798d8a46674e92a0b4d
+S = 0685982aa8e2f3e46ecc03e00e7323f3b891da437235cfe9800139ee8d7
+
+Msg = d2fa68e1f7dad02916b12fa38f1849d6d409dbad0344438520b4dd9b77d62d39ac9ae3cdeab03ccbcfd4de703c6e798873671731c108f322b9f2a68145e3e210c9b15b879798e5c53c5022742e9819b99edabb2f44d89ae221f7a99dc84421a6905695ff91928db608f861745f17584d56e34b75c47281435b1b0b34e490692d
+d = 07a884b22e29fa9fe945e9ba13c0df8d786dc87cef0f77f069e182dd56c
+Qx = 11e831647d0ffd53d75e44abceda753ab470b3cc93b457590617d925a19
+Qy = 03db5bd0aecd6504d904bcf9dcce131abd239aeadb9a64a9811eac823cc
+k = 00241b763c6245b83afe61762b161c41467ef35b7f27a9c1066f02babd3
+R = 0514adca3481ac5f99287e6e966a5c223296b07a9456eb582ec5568688c
+S = 07ff6a2f7cb1d2594a11d8d0adb6fe50b4e740f025e7b4333ee26163d92
+
+Msg = 3830f75cf9df4eb2998c7c1b5fe11c1476bcf849c3a8fa7d3d0b5bc2292e5d07465ab8cc9381c575d909e509c5dac49c78817c04e4bef18bd51bb09aa5897f21634633a5ce6d20bb4638cb6c3927351eaec7b62cf4a33956916045c392f325adafb10a88a5f86d7e41dd77908fa7284210071c22aa40ef40da6339c02da05392
+d = 05da61f881d5a0dc085bb93764f584352882923cd237d878220ec624c1a
+Qx = 18d740441eff1f785a14d04da4ba69540cbb469780ffd36e1dfae4f1de2
+Qy = 18072ab30e999ae26b872ef46a9a0604296d02c08fba9477d9e03f0f75d
+k = 000f95c5678fd08dda790cc60bfa578118f8687228a2ef5f31e71a6884b
+R = 074a6599b8cab75e0cf752e3f41288fbc673d52074950edb14f76524949
+S = 03523804351e3224e816cd4fb7191f332585f68053ddb32a85cc0fadc03
+
+Msg = 65b9fe15e6c35d453caa6bad39ee78a720a04b60d8a0a0f049186d2f777e48ae2d657e174df53edb7beb9f7d8f21904ed674add0cda5b62a7308de76c324a144021e8c6d387daaba4ce48bf7dfe9c8aeee2c64e434ece1fa5ddcafcf3e5d0013a1eeec1742a00d384cc2ec0d7eda83bb4dccfb0e57045ebfc27a4f404d03da37
+d = 03fe9f04647f6d82b13ec1ae5a8c2e49bc66b05649ad778eb16149ad83a
+Qx = 158eecc6b8918e7813ef990217c603b28ed1774c740382a8af5c9af6133
+Qy = 1bbffeccd41107c7e6f83e24c822d634a7ec064fae125dc8a3ecc4fc9b3
+k = 07731edfb3ef523a165a1b5817ab2805a5cf88043c98ea2393898e19551
+R = 01fa44fa18ebafee6f419fdb9de0e8365520617558b57e9ee89f2c8fc88
+S = 053f1b2da4cabad04fea1111d525f341417587823fce71e5bfd2353c2f1
+
+Msg = d26521fd41eb5d46ece6836e188bf9cb1b461d011c41e002a935d256654d01725378e845920ec4a7fd3f379df54772493df50d312c7c6aa4e909e7b83f2442c3a5e85c37d68aa015098ecfb0a5e077370f4576f4bc63bf37e1dee06d780a3b6949af5e21c2a0960fcd20821ef5f17bebf5fd5b3bdda260842cbbfad45667287a
+d = 05ebce648ace4cd555413de6a456fc487d14bf4b0b9a72311ef480d2f26
+Qx = 020b46ecbdc36b4dc01111932090ba185eab2cdc4fa89775f2a6177c592
+Qy = 104cac1c800103c79642321a216bcfae497b037b29888cf9f70c507114e
+k = 027733120626e564b06ba71c4946c9c8bfae43f88511ec6352d2a52f407
+R = 0592de5184510e6ecb7be8a011f862470b918354a1ad82458cf716137fe
+S = 010a9c5fb6e4b70571a35c56744b57baf0108728bea2bf639af1960d1dc
+
+Msg = b778c021b1a92c41dbd09963da07018075d73e54d62df5c2b7bf8abe137151650d1c1c6abce7eebd8f32e8c3e6d1433773f257bb3ba4a4fb6a02c0db1e47d03c27d3a90898ebd1927c21df24c4c5443ca5b81f8ef2cc0f5e8b3d08f472bf07085df737adaedec63d99acd77b87ba98225f198b791124ac2d9b191cb9251b4b00
+d = 056653c2f85593f789a926ba49fa3da9d7f946d8f1020508c5a527ce813
+Qx = 10d65f6f5415dd86a83bb10118abfc1b1670a1664eb6dae99fb68b85019
+Qy = 12c1e673e575086ec1e76b90d59c2cbd2727f726f88298552b678ba7e60
+k = 021e26c098c9f9da9c782857fe640ff6abb21caf20a093f2277845bd10d
+R = 01d67cbc8209494dca1a74cee5d9894f98f03728214f7bbdac29b0c0e78
+S = 02215f758fcf0d8dd603e79658a8061ab45bfe6d854e52ea7074fd5654e
+
+Msg = ec14e07f615960015a489ef999e308b42a4c571473b9bd64b433dabd9a1b1ad02e33eee9100064405175928a94543a80f440040afa2965b4e5f95f768e7fab6d3c0a5f5e1bf1df7822f78384e80f2955ea85f044ac60537d895747979f935bb0cd3673193c4a32dd7803e48d7daf70a71bc2aa97236615b6411e28fc9a652145
+d = 049a91d320783cc70a5952c32036cfc75d41f1aa84127db2dc759fb291c
+Qx = 190528df8fc3ae4db6e12930f176ec9c833d1668ac5808f1046366445a4
+Qy = 1f647d55ce80b18a9add47fd1a8e4aa725297d9da03246f5c1ce503dd56
+k = 01eb80e2596d6c01431e7a4fd9e22903ea85547a31d675ff157a789a137
+R = 04523776d88199ebac2f96f9faa434bd81bde770ad4458ef126fde9198a
+S = 054665f31f92f8897482d34fcb63141a7539577037c84496167e9d3389f
+
+Msg = 89c645339ad0eb850e4e2fe583cee175b35feb02ed7541d7e9aace24cdd3939584f73ad39526de6399c86b36de77a018e2c70b532bd0f032f9137d10480acc30c49f9baaa86f9df0033b77e98b485bf7a69cb5c281e527d3ccd1fce2415f0dda4a268ce68a0a34b16afda54ed922cd6810ac8dc766df2a3a6c5e55972e9786fc
+d = 016a20016602fc7088a60469843e1d29ad67e3c3cb9500b1e2a00d4050a
+Qx = 04f157541dc3a8bc8a2ad4dfb3933039b67e331b7353a2fa9ede322f4ad
+Qy = 1348a7b8c9495bcbecd556870715faf3d543cb8f2368805473bca17b82e
+k = 01df1ee39217d7f0d838e8b2d30a1159d8003b06e50a00d637edf08d6d1
+R = 045d16826bbc425637e7a05b826bc907f7453c70141d1bbd2cda63dd490
+S = 01ae1703cf179dfd1d5407ba2b7324cc7cac15235ee9c3756177444e122
+
+Msg = ace14c4b101d2d8453c2bc22b756af016b5de537df9c3e639d208ad04ae0bf6232dc90b90c33228dc85de956db771ffde05fb4d0b15e4f218ed2771d703ae5bf981252a5bcd60c16f14483131a481cbe04dc0adb1fb8aa32cb48bb5008e8a8e5c7b7465be2fd7afbc811cf5ea6293b1a464669b49f55f57b93a8707e6042fda6
+d = 00ba922149bada2551b7be1c3df076f3f97ce93c13c50c285fef3f42363
+Qx = 12daff2cfab994b9d1d1ba73bd2f8e7883b2d92f760b0d16351ec125fd4
+Qy = 115666f7c65b95ec2d713c5ab1a3eeaaf0f931b1859733416c3c778aa2a
+k = 07fc7c9503fabba0972e0e8892ec6331e0812c6452d211c5561fde79048
+R = 06477ec9d8d8d45418b9efe7ae47c0863ff94c43d8f392c079b870a7cf4
+S = 06b5a5d020b3d980b9d7880130802435ddb4e7362e36a70d193f18a7fe6
+
+Msg = cec2ba0d1772c87e87d5bbbd67220692bea4301aa1a66e8dbdd7e651d45c26dc2a0d45cfc32c34d76ae3e1c61db7b0fe1863457b93937d929e6ece7462ebd16adfd708353d6f7c27aafe06593c76da7149b0cc574a4290b0d8fe219f3eada7082aca38dba3f78ed0d5942d095fa5556fc8bcef331ff0a6d5d1f4e6c51d4ff5af
+d = 02d635e12a58cc6dea44e71e87c37f91e8d08659f0b7955d24f65ab55ba
+Qx = 1dd33d8224ffe63a32f2de5d4fcb0e5f1fca7ca2ade5b35ffbe75cdc658
+Qy = 0bfbe9dfe13f99258c787af82631ce2133dc73207c579b29869c7463943
+k = 04ef333049c575d6688aa04f87a6162185e4a57bb752a7f903e3aff86ff
+R = 01ade04af08ea1c1877779fbf6335156b1a1437f3e449f07458d700c67e
+S = 010fa82467d39e5ad51cda8fcedc72ee6a78dccd0c90544814e53ba9cb4
+
+Msg = ffa13cd0f51ae2643d5d4edecb493ddd653e9faddcffc370e7e958abf726a5d67a2ab36cef42ea8ebe22a6f01b9c31f6ffad01e6894487d979acb5e618f765ac0ec3550ac5dbbcede8f9fdbe52fbaba5c087ff382b6d7a09b2b5084227d324d98ff98793040884799b96d2ca593201f4414f18c43b51c53c5e5059e0641aca02
+d = 0073883e5064e06814fc4de32e15f7a6cf825d2daf6eb1df8c83e25d80a
+Qx = 00d3c79d627ee0d2d88f2de2dd082112c20dbc5ed66089454f7b8fd9f81
+Qy = 1a2580e779753bcb023acba1b0852492b989c767f664c7047de8e6689fb
+k = 020231e05166271f47a91dd883c580ee313e9a07195ae511f0ee62173ec
+R = 0303eb4a0df97577c4cff531b3f54aa282e76669c0c5ebf4c9779c9bb82
+S = 0692432a7dfde09db7743f08130b3d3327dd98cbdc323627603518f70d7
+
+[K-233,SHA-256]
+
+Msg = c73e3dbac9513d0361dabe94071faf03a11cba18c06d131a172d5f0125b01a5eeb6055bf72c7106fe3f4be3bd2b1771cbe7f85366dccfbc3bac20538510c3f51179cc540ddafb2f3b05a0d276899674ab1d7d8fb4f6838f04e4f9e26b8c6af31540f63f4953c85840af4c57dfa78c704f637dfc8dd750fe45e2c1e149986d127
+d = 01532271bfae8d4dfe60f69b88d3006d58e28aacfa701861cde8d624db6
+Qx = 041c1ca965338976b4c45c28b1cb64836b3b4d3e7ba2b1323ea26fbcca2
+Qy = 1a177d042fba7903007db122eabc459e37c2c7fe82e42752b267fafe4b0
+k = 06a54894825644901baf2ec3681ce5aaf93a18757d93ec9cbce7ccd9d65
+R = 03edb77fc7686b520493604db18fc69edb4cad8195a958e27ef289c4bac
+S = 004337ecfac57abb9271909aa43ff4e32851df7818dcd87216d051189c0
+
+Msg = d00dcd0f3212a3167403abed91c20e76f5e7a7678a4fd970f944d11e6a8cd149d0aa6fd3164c5a74c0f55193a4fa3d8ba6f99cabed10544625a7bd92b3e0b46edbd4a269bbc10518c5268c3910a2aea567ccd32d4c7a0cbef09ea42c20b636d1f711d220e23dacdb9d1146e0494401349749e5ed88e38295232a7effbae3aed6
+d = 0550406c0db882c6aee6cf3b6baf377375208c3e90cc44a067cee43efcf
+Qx = 073348eaa8f2885fca3baf31830a2b28bfe983e3046418561f62ac5d247
+Qy = 0033de5aee6d0bd4de286f1de1e80bf72e5e17083032bd4dc24577b6d2d
+k = 05c0e7ad0f9bbd522c862326a5734a766423fff7efbe57c51c315fa574c
+R = 02103f1a0200883850b6476c7d7e7d2b3e2f60923d028ee6f8227b1ec48
+S = 007cbbc3c6295ceafb3d9cf8411f85a045b11ef8472c5ed45346d26192a
+
+Msg = 3d36221f87157ca4db84884b8666660c4e2b6af330480c516cded9f3bfe132543626a39bb6aed1964eb5c33ea0b95b9841665417679fceb95d199d55accfce35dd3f2283c1a7ced57d0c4b9ebe3da6e1ff2f979b6440db27caf9f6a4bbfa47e20d29ae304f4d0551fce9cc4097eb2fbedb9b24680bb17d207bdccdbe799d5b0d
+d = 0257dc63752920b6854d6c2d1cca68589a38418c3d036e73760a12214ab
+Qx = 11a42e9f66ecf030d0446cfb751136347d4df0ee4e031058ebdcc04df80
+Qy = 0fb7161fac8cc5ad7bc4477a39350e419776f76f184e28abce886ae9cc5
+k = 00391d36c4044896ddcd68604d5f677d1df298f46abc00eb12f1165e8a1
+R = 04e19bdc6755a603085b66355256bce98d5fdd49b4f06b628e3e185574a
+S = 07697b29ce5546de969c9c4bbb5ea65f712d6cda3410f3dbfa0cd5b1a8c
+
+Msg = 033d82a42d0eddf58fbe3e91ddff7190e3f9fc2b1e2eede977d2c0473b358b5fce1f981ca6f88fd61ce2f79e453e3a2b77d1baab2b970ed28d5dcff58873a620e195085e61c4b8480d829525a1a944e8a4b63352f0291f0311f1f98ceb262804beec1c74947618f8e3b067866255878c2502966cefcdda4f5fa2b13d92ce7840
+d = 029025352297a7be850f8852411c09259b83219135e0e8949c1bd5b94c1
+Qx = 184345e37f07077cc8df5947c1b1fcd8404b3c31586d6ebd91b240cf42b
+Qy = 19dbc9091a5d282fd6e62c34676a06a425e098567b990c47e61ef14d77e
+k = 02b2663a449ead3f8cce2459e04cf84333376624d994fd9312401ae57f1
+R = 03af223fd3a6b6b240e59dca83ce2477a577494438ddee3fd09632ea67f
+S = 0606576d89f2094572f0bbcb58a15d9a4bf10ae3667d4e35cdd8da32102
+
+Msg = 671a7c81b64b2919722d7b258bdbd90165bb757b53106e0af03d0eef27452942f40cf52bc95cc7f6567df2613cce795f8bcfc723b2735efc35375c001d37c58480d89343697146b524835df3dbd333f7c06c98e36d3c4592ecd1f34ab57c341bb0f4c785f5b8372775f74b4bce60763fad1788e77ea158d735a64861320b36c6
+d = 02dc82d0e69e498528925c0e62a13fda9af8cefd047c10c3ffc2e41da3e
+Qx = 0e5463926235ce53a85b489c3c278320ed986003962a5fc7ad4cbab0d9f
+Qy = 1453e6edde95670a4653186ebd8246c28a94dd84f5a669bd3293176f1f0
+k = 034a8dfbbdc98bb1d9b175600bffd866306dffadcc4bbb6f24e7f918da5
+R = 03cf1407445cf1a619a280e139242056c23c58979f0b3f0aa7e1fc074e2
+S = 02e55f27593f2c76fafccb71493f14daf50073b35cc85f002528cc6d691
+
+Msg = 0ef677f4799298f4aab73b7393598041f56e902ced1726af49657b6601a06186212e3ee8cd4bd33b760dfa2ea3c38884f94358d51dd479f2ccc8b0b352fa4e44fcfdcfbb24919d04e6ee1108527b8e8d60e8d1b467c30c18c5455e5835d483161d3fc26b4a67d6df9e3ddd9331247cb18450188752a1ca219f3396a872cb13d8
+d = 041535fff5d279bcd744b04e643458ce20b81df8a9e01b1181d52bb14e4
+Qx = 021e1227457be78e49db22335139a136ba290d34871f90ab5e6a8db6ac1
+Qy = 0df43b381a4d757864c39ce8d0b64d6a32e9e8be30f92a10a252d46a2e2
+k = 03019bd459b34133dc7331caa8976bee67f76db3a45b1793cb545e26c68
+R = 0025611bd4e3473aaea85228b2bf37eb1b4458d8166012aa098d9c1cab8
+S = 07acd38506e984fb7f1607b50837018f9b4246623dcfc9d7aceb486e76d
+
+Msg = 9290df0cc50c3cab6655f3a6de1f4cf613d9bc06ea7c99f38038369ff2fadefa57a3c7ae7940c1b98bb1d03503cc271f7a891bf38eec93c31dcec7892dfd2e1ab337bedde3e5325ed8d9cb7fa3096f6fafc3beb3a66cba66ba826d1032debfb4908cc9dded8c0099c85072daac4373fbc428fcaa9a6da02181ebc33f0cf926fb
+d = 000ecfe580a624df66c25e87e7689fc3b471d205970ff9ab51a64aa12ed
+Qx = 02ca7b9c98bb8106ae14a87d5f9f7ae1f99a5524992116e68af89da6daa
+Qy = 0a2fbee769eec313cf3c8519d3f96167477f0f06dcc470408e3f637b6c2
+k = 044f065c49bb7ff0772d628104bc2e222f1fde42aaa8b9345d324d7f936
+R = 046301f3f07922d338d5b7d82104597fc50941e4bc0a15ab5e0408f9fa1
+S = 03495e335905b4842b97f00b344313ca7d6a4ff60cfeaa5d589e0a31782
+
+Msg = 855c7be75fda372f062709827f333630acf28954a62a5193ff675f0dfeb63f32bca418f7cbdb346bf388d62315b19a592267ca407120db93d4e3d7125b867c4c4670b7a57a76f61734cead2caf2425eb9ff0a63293e8cd6defc9648257b401463f4533a2425e0024f1ea93365eeee3c6da20d25928602ec8b426f9b39f97f3fe
+d = 013c72c73358ffa168423149ecdd897f0a5f75a641de008649f00134944
+Qx = 1c70e1b6c01477f95e718f193e13c093b101e9f16024082ac699ed6ebb6
+Qy = 1f8013a88264266cb5cc5bd38e477fe0a1aa49ae4a5ff94cb58439a7c1b
+k = 07ad8a117f34bf2fcf7d689b8124e08118e28ebd172f8c220d57d3f0b88
+R = 012bc7d380192f2efe55625e39927ef799993af9451c662b562a239dfe7
+S = 035961b27e88d6731220f70e96d555f63853d14149df7bf6d24fc29441d
+
+Msg = 9c896f800281812ed57d31623d563377a5c725cec84313472b90e73f77d400f5d4fb236255741b73d46f7e5254d04099bec274db8a9af5fc7cc220d42cc172cbd3c3595c49ff74bfaab7b5e46c90855b611f74753ccdbbabf92e011d52e9ba753b83ed2a251a632e1bd5c6d346e38e743950c8ce0f394a837028575fa44bcc26
+d = 00ac60e2e70b7c4cda64071c7738f68773c94df9456a8ec3bbb468fa7f8
+Qx = 00109614a2ca27b7a749e53777e0f3ee2f57013ee83ea539ada6d98d8a9
+Qy = 05668f4b27213a8a024455b398de2cd7635cb620d7401f5deb4fa9ab2f4
+k = 00098489f0966e27555268a94378b7b8685ac610fb0964694aae9aa716d
+R = 06d151437a0aac232a472af038b0fac095d224ce0e5487510e30c31d605
+S = 0563dbfd021c1b77f980530d0120e93c9ee4f1f092a268bd8aba7d3110e
+
+Msg = 139a14ead998d1a962fa47c47ef2953aa136bd912fe940709b8c560bc2a0c4bf8f3aab30a8e21b7d5f487d30b0097e3da723f11b5cb4e8c5724f5a2fe0d68ee4bacbb85e5eacf18094d2a8ec4506cf8497836a4a905059a998ea750adc54c27c69cbd0b0c1f9743a62f3d988f3fa0a9865a73fc071f526623085a2ef12838888
+d = 060bf720052e8b9508a801340c213cf53bbecf4975faee63d4b44fc647a
+Qx = 196e37671def44b35c9e8c719130389b40c7ebc0ed5ae354dc73e0c40c7
+Qy = 0d3fa0a45a3cc5dfb61085290f6d18d710ad5d0d3ab31ce65b0e6915a72
+k = 0729c7e1de10e92634857a65a2ed75103df6bd4bf63b1ad6383c37a0435
+R = 06808491ffebf088476de7daf541bca3fd943d4c2089b848a130abdc0d3
+S = 02c0dcfff06a07e928c15a1fc2aceaa4b4dd6fe8eb67ccd4d01240f249f
+
+Msg = cf4a8e754b23d0fffc1c5c80b0cb11deeaba3064b315bc2cee96db5b9881baf90d30af4b69066f757b3020706def77a5fc1632d96bafba22a9c8cd3b52d535d941b3c7cc02b7fe6b51639d5e2084478ab3a29d2f5e0e16639fc2833a47b58e2c3fb5b2ea1830fe2ff68e571a8f281617a23d9a28db1c64ddfb1083d055030e5a
+d = 07cf3c216592febd8630a478b5b3e3a605084020322adb13ac0a626bc7b
+Qx = 08eee2ea13a08d4e4d71ecd2547f6d80b8f88879c9edfab5a675831fef2
+Qy = 05117c0d8a0442ad7b95cac1a984dfb9efbb7eb3c3866955da60e6cea8a
+k = 038de0be25c23cbde9ed9fb259cd9a06b69bf15dafed723970dfcb91307
+R = 051c9c5fe50eb81a11c8e7b2db145c6b5dbff2c51def56f4981774c357c
+S = 053887c6cc2f21bff461c9182c17f634ee2b301c3cc4af0bb1d3075f74e
+
+Msg = ae64030d4af9b36c8d3a6af0aff34e5ab201df04274691fb420b7d5c40c401ed7f3ade96065d34f2490d17943e27156e7bed83cd7222d0d5a73d167855fbe7ff6c3ed87f20986ad8bbbd80fed5f9705c6c783b423f641d40ff1f367f9648af5a79ea3cea0236997558bd9dcb011ea4dc64d61ea1e1f85b4f696ed586bc7705be
+d = 061eda5999e5a9ed4485d2a0ac5510549b76ca37df858ea5d95aeed571b
+Qx = 1642d56359cc0a5f261fdc405030d45b0d6f9c08a182d354bf2687dd9d5
+Qy = 11bf0dcbf62749a99e4b02b284aa7a6479b59b363d25319a5315423a589
+k = 03094fac5381a1b31e53f43a537d9e22ebe6bd2c149f2f69d792bd56f53
+R = 053c8c4f9a30e0500e01100bb97c00ce98f5cc6578686daa1bdbd679373
+S = 047086a88ea014f06d6345608bd0a6010e650b9f6f984b6efea9a4fb277
+
+Msg = 94a9d9cd9efa3e4ccf2a37f904dd9cab5624ec9393cf8816ea591c5e70cccd2f105388ae133708fb974998ae61d218c71785f9eb808d1c28d953cc7eed00dd9854b6b4568c5ed5ee3df3b58a1e04c64f1c87fee4365ec9aa41b08a6bae234dc43a0bf2f61420acdb891a40f17f246972afee75a4c0b249dee0fc8f9b9c8a243d
+d = 07e7e73171e4d2f2989dc024757c186485435b82544a448f5cfca05f281
+Qx = 181c8cf579d9259020461184979757b097d5a94245a2b9a1f8a6931ee0a
+Qy = 14baf1b761a0af3dd9c0521c6489f9a778da824283c94087698daa7cf78
+k = 02b57fabe6b866fd25ad8802c6b02b680c137ea9b623457b35a24d5a5f3
+R = 07421dbfa83859354345b9c3f1ce6242605094d924a4d38c7bd952e3910
+S = 05ee48a3a5119bb3433b53a625101492216421ce67fc04dacf947ec600e
+
+Msg = 4db998df7b90678b8aa4ec6233c9b4629800ad1f3e2cf8f7afcac62fc6982dcb290e44587015eca8dfe77dbb4a80f9bffe75b11e961e70deed14555db6dae47d49e73004f000eb8677c18f7e8234bf0a5a104266167a05ef07152e7acc2f0368b37efe69c0c2feb51eedf7338cf9ed398f066cf1f66bacd89ab9376d41da35a2
+d = 05f7270764a0444c7159d2db867930fdb0fb9fa6b8fc80ca02e11753095
+Qx = 06806c7164a09e11629e16608b7312d9d988acefa626fe8e34e03203d11
+Qy = 19c4200c9522618dab8a16e217beb3011599ed6cc09291fe9d451f0cf02
+k = 04a8958c80481a18c6e0893da9ab2d48fa6ae30a0f1d0512196e658eba0
+R = 01d301da51eccd15e09ce0bc2d0bdcb215a43ed13792084e2969260d46f
+S = 031f96a2f322d27d0bef23ba7c457fdc45a6e612f7d13e9277d36c8def3
+
+Msg = dbf9b8a4ae316bd2df0c80db1cb5d7038364a2634925ff957d7c03511b57d486274b2ecf191746827c325a14dc94daacd66ad86d369e3f598f176c4f0eadec7e9edd13e34043efbe0a801b75b8186b4a6d89ceae4fb250ab570d65b6dd7c04382738fe3f6f6c867a7d84b35b20720cb0036a5d81a87126f236833831d9ff00b1
+d = 0179b924afa4acf30ecbe2b3c12de533a1f9675687876a7e5e5ddc8e03b
+Qx = 175bf95ac8e768727d3b4a74c2b8a04b221247a3b8386ddf35fc39976ad
+Qy = 122f32f941066150c151b9db92b86f86a10cab0828a77e4f0d5c4026540
+k = 0210c75a63699b424585f65497c6e46988c28eff3e0977e3ade599581dc
+R = 06087e46c0677e3ca64a0cf030236583935d0dc03c896685dc6e446d9e2
+S = 0252e42b8f03b085f38c6849bd420837d985c9fe14750a654b584c4cc5d
+
+[K-233,SHA-384]
+
+Msg = 986d9e5d636526f4deb7545c037fe81b09c74496ddb8e42e61650c74b6fe348593f0cf8f8eca5e839baf62f17bf6ad96ec0c71dc44fdf11259dbfe7499157e402f6bd5076972354150723afb632799a990c44cd0a4fa9609ec4db133e3b4700be3ea4a338e8ba1873d345e80163ed60d0de274d7617a8382980bc2138b0a2a01
+d = 02c9eb4d392d7f2eef606e1861183acb1fc753d666225f0f154d9eda147
+Qx = 0d58fd7b5aa570b1c4b2190ec413fbcc9ef44d33ef191b6e23abcb38690
+Qy = 173e85377bdd8dac58222cd1d0f7ed98d73d6fb6c2eaf34819b08ececa9
+k = 064f9fb13784c99185f334700ccfcc4ff60b7f4d613c3de6dc5d1b8dd5a
+R = 03bff54e3610ade656bbe002867168db1b521c49225eb9662950b01955c
+S = 01da3fd8c08d8e17692059c669da3c7c4c146df6d3cbeaf34598d28eaae
+
+Msg = 68d0be2883598bfb1433886aff118349157708690380c42b8919859d96db069c7fde6e117a3669f2cff94a0f1b66b27b09e3f1b24d26299e11552a084be428446f3174da2e0414655bdceb38e58fcb065b6661190862db39c6545dead34a03584632e988d0459659dc7c7c78d4d00fc2aa10465cf24b2410f14e2a62173c9962
+d = 024661c89b77b2c743cc175a6130904461138ddc4ef771ffb9fc2c8679a
+Qx = 090383de7ca48f1e71a43845565a9f0c53d2c9f8c2e0f6c4ec7eb6437fc
+Qy = 1676582272e7ebc9fd56e1010a570d744ae4fa70eed3e6eeaeb0e0eda7c
+k = 05cc5b36c7300a1cc3f624e9e663861b4e296f7e7a27e8f8f0a2d54eecd
+R = 039c6f5b484411c434ee161ebeda7aa21b7bb26bde0301d9ff92921337e
+S = 02aaae737aedecfd5d53af56ef154ac6430a45ff03a3495a34a5fe0e97e
+
+Msg = f0ba0407485fecd7337f4b22236533a926cc744a5f06dd08276750196f1bf7ea7984278f789f92dd07e36895a8bfe297ea43d4a1177c0368900e3b969d3083cbe626f0e27e7ab38e185c923dff46d9ba187b2acb9cf4b23ec8eedbb8044b96b5263d956e50cd6240c66d5d96517130c743752404ed09473f05d0004dc5971ff5
+d = 0065e20e5ce534576d7c17616cd4ede3bf4f500894850723bcc9f895f4b
+Qx = 01413f6dd5349e94311f1d25e400b69c0f0ea446294eba4bbeb10278b85
+Qy = 066a05055d856621161d4f0e33dac82e5c0cd91ed8aa56e9abba9ec80cb
+k = 07377147b59dba008ed0e6b366e511f94c7f7c9088615c6d46f46736b97
+R = 05515a6bdfde3b4b78489194d39f4bb439f58a6b3c3f9e16c8a71590b14
+S = 00778f79083d11efc8ff959f607c4cee7cc8f38b855028ea248fe291adc
+
+Msg = 3827276694e413c886129c452c9a66e7d09dee84f5f09bf34e4baa308b4627e096c7d45cf6ef45ba1d9a4019a60399feec10fa80e333e2aff1251c85ca48574d9b9e1affb9666828dff5afcef3edaf5e8cae823505a0c73afe76c1bf130399fb06b092ba34ab0ae15ac6c682f9ee8479b065ce75b57213b8aae0f55e4e386de5
+d = 014c85f66fbbd653f1e4e590cffe62c343ba6062df4b271fbd02e5d42f7
+Qx = 18930b4a59a1c0e92febe650347c49e29a4e83cb8c507e30ad835dbc94b
+Qy = 0a237bcd130235e34b4439293f15e7a3913d659089e38e5619fa52e3c0c
+k = 03c1f8d076fb4fbea91a97800607b2db3fb5a45149c0d30dce79f07e963
+R = 04b9d2c66d8cc55b64f3f62dc629ce8e50ae0bad8a4d14e8b6567fc87e4
+S = 00b9dfdbeecb061a455dd052258f3828d4b7174af972c65bd0043a9776f
+
+Msg = d1afb8965b48d66b9acb1ece674d9548f83395275f2d8135554cfcc7ceb96450d850dd874529433883709483d0743798db5e0dee955a4f30ba328c7934b8dd9207f3c336cf89141a175ebe23d2faed629eb4236a8aea8300604c3eb7704512f240fda66acedf1494a85058dc6a31bf9531958c332b93cfe5545046876c6b99e0
+d = 030ac7a78593b570b29f6d3d267abb6ba7e5870ee1c8ee4f1ab2f141051
+Qx = 0a409e90eb4314f95967607ea3de9817a0fdb439cf406135262624e7fac
+Qy = 04b1dd719434e8dfa5861887736f32ecd635878ed4b9e290c423da09059
+k = 027c4987ff872fe499039b4432dc889960ea8e3f07be42e36a5827b3964
+R = 06829b5e02b5849689d152ceacdddbfa8f68d782b3ae8da23ea48b1acbd
+S = 03dba0d2b4400495ee098325ae4450b32b83689349e82a69b799dac2cbc
+
+Msg = 4f95b71669fdfe5dc46d4b951b085e099de349fc740535175337127910acf24e9a0e4b2f23196ad23880da47b740d77d74fe9bcfdcc44dd7d8d1a181ac290de5cf4da22d5034cda3d8020bcc776dde8cef1786c9ce4d2c2cfb035da61406af745efb7ef1a55f2eccc5000319cf1d6380963025dcea641cfd15a3106751fec286
+d = 06d7516aa040f7d559cae248e485834e8d9bb608279ed4d4f7e1dbcd2b3
+Qx = 127a92888fdac8d4ba9c0243c9aca516bcb431911254bc2cf51883623a1
+Qy = 0606c30fbb9958fb1140643f32c5dd582c2319f71bff197d58ba3e598bb
+k = 01104b6ad82327b0445e75cff0efa1281d266a9dfe4019ba2ed22dd6976
+R = 01f247b2850463e362ff8879054d3459b2cbae84b9d4bc005a2ccf4736b
+S = 05b3dbdf04758d546e54c43ca5973bd8ceba646a4dd5d17ae5d2f8ec516
+
+Msg = 2ad9e17780c824c4f2d1e1cbf19ab85638f2f71cb4fa3518f08085b8b358f54d4f08394a5ac29cbb3cab828c5f07f41eec51e6cd61a5f2cf44dbfa46834370cebdeb328fd3bf681e61011b5c2ebc8945ac7a2a8467606051008b15c89390e111999255bfe28634ce9bc2850a2b55a4af1c4c2f94403c78aba1ebc87386ab7b32
+d = 0137050d7b455f43a8dc2516cfff5a91062c1a2727b27df41488f3dcf18
+Qx = 15ccc90a5f3906469e3ecf7a70c429f5b50fd0ce74065d41f1bd6dccc1f
+Qy = 0fe5611b8b1b35a907bc188ad2b1fb7507d1043d148283911af3ad782e9
+k = 04881e879d7c76eb2ee61fe1844567316d7efaef047b96979e6dceb7858
+R = 03799e90bc64cfd7d0246a7fc89a4d8ed0399277cab2af40fa2ec8196d8
+S = 067e8728f4d8398e4e1c25775620865bcc2d4cfe635a1f4c6b7306f6d9f
+
+Msg = 958773c37d3eba003aa5c489f72118b3022c52b93399e9d8001695664918b86893f4922c7b6e55b1855ed0fd1d8de5dc61af403ad660fec60d7c44bd0102c069957ed804d0d416facdc1a95355ef58554606579ef89b1842f1055cfa2ae118abbc485356824cc09dddb77d0671cb3011b33bc86cac526e3f6bb3293c7bdca1ff
+d = 001fd447b33a2ee3595b9f885c290d241422afdd74c3dc4981955a7e9ad
+Qx = 0e706408803188263cb149428c60de57ac757f0776e5b27a2d5a859f58c
+Qy = 153b5e13f17f0178cd90427f7d608a5659b9e03effebc89da65d59698d5
+k = 0339300c00cf7e8c6195ffb71e509613018e6a417782e4f52704026a510
+R = 0227c80e36e3571e1c783358c9ffed237b251332e8ed05a8d3b454c53b5
+S = 0679a32cee8ae001a18d9a9d0ed7e99e5ae67ffcd54de7b48c62e76ac8c
+
+Msg = 9cb2c496b1bc7f040228571e005e7e936e48e8f469e295edf914f5648701249a20bff6b98b5e862603dd9f12bb71c160aafe9df02e2e383e9b8a9a9d700f4425ce408feabbf754be543f52204c849fed6c9d3e36e03dfbd9e35c18d7bb2295f1c484a66e73440a0a5aece5fe80b9ade9321ef18cde3eb2db15e4b18e788b0441
+d = 06a061e10b4a6e7001d95411cb31bdea9c84670a59ed61b14fbbb05c8e7
+Qx = 00ad2b726b805919cabc90d058c78896d2dd8a78484c1fec5bd5fb0e07b
+Qy = 07e048ddb487f667633d6d030338ded21a2ac5f65373ddcfe1e4a3424ae
+k = 013b4a86b70f0e4de6efdafd7ecc993f0d6f231b3d743ee5adf82db1515
+R = 0541c2d3b2c6f0655dd415e327f0ef07b03356f8047117c41e704169698
+S = 00300f45026200b8cc84fd564778281bd1d7e03727c242a249d9ad33338
+
+Msg = 9a4bc0a029e97742ed3bca207d5912cb568e4403cda106b00247520ea02008b14c041b8c9b976294252da835f4ff27456039d79d90315abcb0b9b6958a22352672e229665457ec79571ca80447c8ff2a86e6af3dabe7427c8bdcae65e3c6746a56079ce2cf8d22235180f46646a21cd9e86032cfad874cb9c67f882fb037a13f
+d = 027ec31ca31acb4d2fbacb49fc085f1261b0042cc755cc97f9b199e7a37
+Qx = 1d521f7abc2fd3b0a10732ed641cc1b7fdd7b49cf61909b215220c5253e
+Qy = 019e9095c67af1b89ae6c486c4f9889c3f2994743eafe55bd9eafe438d9
+k = 0151aa44fd97be14578d68f87dbb884c960ab59d950c392e607ecae6bac
+R = 07be427f46958538004186d52aa50a0f83d184a9d2f4da2974163854eec
+S = 029d4ea73ab5b336ed44556f6944e734e531a5c71dc6c929e7253323906
+
+Msg = 8d89e22cf802dc68ff22d43c436c79311e705ff6fd845e77c880f399f403e6d5e9e2b35511553c978171189e288cb2200fd95f84ec5ee9865c0eb9190aff6dacf783ef200e82027fa992741876456472bdf27f2bd8ee55db15408c957a120eb64cd24d299818726a73fbb0697eba726a326719765735b37a2dcff0c853c906bd
+d = 04c6f4d88e5a4f4f83196f2dda9dcf2a66eaf94d50c851f59bfcea1d876
+Qx = 1e2677c1305f545472e373615d195d1f7a315f592e26fbbf44c42558050
+Qy = 1638140f48bad525625a87d0e537db5500f034e71e60e8a8c48eea04108
+k = 02185d8ec6f35d5c3f965cd00597d93caf45bbe186d4128bf877ec304eb
+R = 075199f4d8af090e4666754a7dac0c1599c207735c0f54c9f11e305727c
+S = 008cadf59a224f812d64c2f492e7ad4a923f3463b878dffc75eca5f8fb2
+
+Msg = aa1bf5a79e5339fb9ef6c2817bd95725551d064bc5064d6586c5a879901adf808dc2ef7c78ec3b434b84569988db58b5e8e9782b1cbc2cc7c9b68e66f32d4ac4ebe7e75b345f654c7b8a5e650acc9f170f75b7aaa3957cce248cc69cf93faf8d72abc6fc1cfa9ae2d18a7b31ce720147e88e84f6563b2197882fe302449ac5ce
+d = 01aa169ea84365c22981bb766bfdad27e373440850569957544b0f9332a
+Qx = 1f97d91302c70798e2278348e36bbe01587e0031ac3c422141e3d4c1504
+Qy = 0a95108f6b7ff41546c98f4ea4d1b587a3280e49c6cd0d33abdebf9a1e7
+k = 03c9efc0f72d88168c2b1f7fa1c6e275839303c2bddca136dd19ef446c9
+R = 0639d1a1066465b4b2f443cd9677cfe3bf5bb33e3e9b14cab2d37f4a859
+S = 04582792ba78f782f112711ceaf36f5f0774b92a6fcaee327d687658835
+
+Msg = 475664d5e22cbe0da0d0289ca9a666a37270dc71c81cffac91f6229fa39315c1d55f7e0a89b6a7a07df7d391dbdf8fb7af63d2da46ecc3b60110dbcd842da97f98d2b67f562b0364ef8e1c589519024177c8ea079794f271f6d35554c0e9d0a39062383c95721b72f4e74eaafb6fbfbda02cb670a7c4c94f67b8ebc6442e84e3
+d = 04a665b92c0c33a3f8b9eb4b0ec061d40b603de36c87096455102ffe57b
+Qx = 0f0ac5238553f0cd74e6f34f7f82563cb01138e5c9bac6d5e7b8b7ad4fe
+Qy = 1903e9fd8a5a2aa32913b18bddef20667061f919f8d61a5b3c814ba4aab
+k = 070ef25950a795b5e22fe4cf5402f49029c5d97cf9f57f0806c0bbb5855
+R = 01248dcf1993ac2eeacd062f853ebb4b2072357e728f0589258399ea95a
+S = 069800eb2e2b3a9162196dbaaf67cab4ae123ea817f223acb6e889f6d7b
+
+Msg = 9e5397d94465390a82a3c07e3ebf21b515776d18b4463aa5810e6b2f96ca61e92d13e034fa853c3fa45411f51f79df6f799a2c6906e6a5b7896a4576a4464f9e0be2b529a43e1f503fb640d79db6b68f3a3a7deac1b5832fbe86673784ff6db1f8438f7dd332cdd1e7ad9df8b6731aad1b6a72bde52e6bc62d80b8da57822c48
+d = 00531540d94823e19ab2b95cbc6e7492e1effcbabce875de6ba96f53aa9
+Qx = 031ba225249916a5380235220b9657162eef43d59ccab507639e19bcd6c
+Qy = 062e85d61366a73b62255c741a065708701c8fa024a15401a4cd58640b0
+k = 05375df0a23646e8033ec9e3ad269e7167a663b97b4f52cf18fbb5f50f4
+R = 05bdf7d643ffde5ea191553a9c99eb42fba9a8b6e2013dcc520298d224d
+S = 06cdd9e0d58bd4c5cfe66589ed7c7d15331f3e164dff562b6971af1a41d
+
+Msg = 3cc4c4192f317e52df6f8cefba6d4cd823c942aaee11b9a0ef5de5c2d181073b7085a55805e9554def8dc13eb978e7396044d4f4a14be2c7605998c062095c929b9c23b2b1b2fa73dd19a0c0af44ca4789f9841fa62dee8a5f91b3cc4b3264f5f67334c3f0772b30bd7431c3fbbf1f34318ce1889b6e8a76ce6d42079a451e56
+d = 022a89addd8b85809e87e0aa2c038593ec277054842854de1197833a51c
+Qx = 08e760b282d0ae4eeb2fcbbfdec851468fd8e04c4dec71fc2d5d3a98a13
+Qy = 0849a56b9b0b0a1ede6b9f9522685e7ace3baa57f72709aba705814d138
+k = 05515b025d6196ffdc8bf275479d72b29a752eb3e70ebf07d4c4e7bf74d
+R = 041902f9b7bc81d3a88066b03e4111ad8ff4d99dd868d5608d1f43eead4
+S = 059adb96af9f404d2f04d89fb39cf38ba5689f47bda749ae9aa1ecb097a
+
+[K-233,SHA-512]
+
+Msg = 72cdef5bdf710978e0aa334b86b8ff4a58630da314eabe98b4d611aab56f55c526983d54d19bbbf9ddba30a84b18aa0bae9f9503e9b222f842f084db83aa39625403213ca321cc0d9c8a136c826e6ea4ec108b913dd0a9ce9d5b8c7e3af53c3876e56a2037ebd6d99f037a097111c837647bedfe4c494e4288ed6427c15969e3
+d = 01df252a11ff97b4421b3a2361db94e908e8243cd50d9179f9e03e331f1
+Qx = 129f011fd5fedf3526f0437ae800a110435db907af60e16912d58523202
+Qy = 08026ed86afa7ec80277f322dfc8cf693089968ed9ceb8c95c930415a23
+k = 04fce14bc83be6f862f06680a32e9a51d1a569fdf1d9b10a89eb9fef4bf
+R = 04d7b8d19dd9cabc3c2245a9d2c8431c3151eeb6f49676a865e78c26c2f
+S = 0373e69da1fe35ce41ff344447fa7ffe6fc71e28dc68244372745739fc2
+
+Msg = 8e4eb88c0b2d525b2c58b8e00f32def90e6dd382301de49e0ac053dbc6b61afe926d85193e2c4948f7402a3d7c614cb2c58e060362b0516a1ba4a7425f1b3d09aa20d4c3c8993a387a3248aeec51e6efa8f558dbdcfcaa13ee08413227c8351e3107e9a3e3ac124224aaea91bfe50c11c1c8ae582e718f50bc5d5c06076517d6
+d = 01d7125c299ebd0dbcc050f07de931c7ad0450af590d0a2d0228a66ac5d
+Qx = 13ebde8790a113bdde87c11ccdcbc39e354b193d772921b86657f53f74a
+Qy = 0aae910b0e22f1a2505f55fef2eae47ab6d47db6e49190a5469b4b6dce5
+k = 0113d1737bee59f9f477f71f77a0ac1aea86aa67002c34a1b31c421cd7c
+R = 066f9871da9a22f07c9b2a44fb6c01ac74ba17649cecc33b729afcb488b
+S = 037fad90c288510d0cd8e99e5d930f4fe197df779dfd6088da48986c601
+
+Msg = 370fdd80f330311dbb3959666001bba61cdacf20f72f78953d946fa6cba02d24b5003f5452d535609e489b9434f192011f99f918defe877d51349870e7e75502f61145f7c261dbd2a0840926d824ebe9be3c5a77a3a84340aea930378367ed3615a47e3f792c7773f83f91ebea718a05fc62e9ed1d78629b2c27ae44fe8f8d4e
+d = 021238e66119844b146d40e48341f522f6ac2f9c8a0b33aaf95a3099a41
+Qx = 1dc3ac1ecb670f867337b752cdbf48bed9f32589366f7c6ba7424af1d66
+Qy = 1e3a38ded8148bf45484ab6b77e0beff759812493347e32d2d54a322a2a
+k = 03626adf8e70506e74ea27ce740f7eed1c8b37d50415be6a2681c67ad2b
+R = 07a9c9056b51f1fe3e7733c6f54ed96662aa7f5a08a961f91fd6d0276df
+S = 05e7600e9fda45bb966fbbb5a9404af961058a128824b6d84d9d47ebdbf
+
+Msg = f86c4433787c3ec3cb1663389ccf53d62f9425274ccef05fd14b1b8fef676208867764eb98d16d006ee6ebdc27b8d9a8ddd303d941fdd82b630694cdc698bbe6bd524411907834286c94b24ee199fe6d646064277f244b7df3ea2d9d52a9dc6a33d7c8d6dbc919da0fa987a67621ef0829e48310e0ea2bb86fedcf4effc0b94b
+d = 015e1bdfdacd87c42ed439f3e243abf27fd42e54f3ebdfb47f60dbae5fe
+Qx = 0fb7fa51c1a96baab65fc85c3b769ac84ca7b63a1fe9f507a2ee0c49395
+Qy = 05d450aed449f8f1aeaa9df0131f696c2bcd4528808d2f52b6a73f72811
+k = 070ca3f5dc30c70e576e2d2b30935b05b6e68598eeaafa1bfcb9e156e05
+R = 07e3cdc4207456773aa52b44156801b316a7ac850b3a9e717a9ae7fcdb0
+S = 07ad6de3ba8730ac887f045cae80fe2fb5237a8594e7125c4792d478594
+
+Msg = 4117d593aa92e3eae1124ec7482737cd3573fe5f0f2a5051a7ce86946a2abb9e47a0c6ea75b262689b0b486476d2ab09a20efc2fb921419b1811b51a2e15891ae9e45a17ab4b96c665c6c423fc00e2d66df5804a164f0f3c958df6f25d7da6829b1fe162a0a8cf130858c83f3555d6ad627db70cb41303cc6380f7b3fed2563e
+d = 00e09410548c17bbbf28a68c3963a52d39743a4f1ac28e6dfe7a6ede281
+Qx = 1f5f36a21a3b7fc5ea37528566da695922d7d9b7e6800af9c1a00f68242
+Qy = 03df4e2ba0c8648cb1fa19663f31786b850e6b80068b8c007f41de08608
+k = 03c0a2a4bea270eaf66adfb297c0e3213254cd87b11edcd90cfcd6f3104
+R = 07b684e337d6778f84bdb7a6835e91877b41d6af4b76311258fbb8339d8
+S = 064a0c22057a858b153ecdf4d275cf5523dacafdfcb46423b5613c85691
+
+Msg = 882ecaff3ec8f4023df5397167f238869f78a5c499be19aea85c7486e73f66f0e08e71cf85f3f1b6f6a70796bf46a18e6b555a0a87c2088640ca73051b3dd59ebfef922be0372208fce602d8001681297b285701dbbe24ccb42541b5db4aac1a1c7f407e11c83db15b38cdbc25e930fdc6558f64d9503e214571a435d890169b
+d = 049f5bea6e72d98579b78cb07d89f64503f8759dd7a73cd73713c120428
+Qx = 0974dcd68cd85117f363812a0473e972c89551e31c74c8d99f1073eaafc
+Qy = 0f306c9051cf3b84803307beb3dc0d34a9758a4f535100e846462a49053
+k = 022a5564b468e706762e3ff934aa22d9aea0bf2b116b61182c9f7be19fe
+R = 02e050afb84e1b0591fb64d46dd7d4a939552d68bdb4213f16c5d7ec5ec
+S = 063225df0057d5368b2e103eb2181ff5760e6b2a9c13c83da042722c3e4
+
+Msg = 99b3b8f876f8359bd6369ce84f9261581c52d744b90261a1427ab9e447e6d833b6b3e89af8dc770f1dd55692d01c8bbc4277a729fddfa7cbdb2ec99133201dde44ac691a77904ca816feb0a1aaacbb9fba85048bc63d73506eb908ecd697caf582747051a3a38ac8930c9a4365f407ed94ca7f2d26913c53f4c010c7ed9d7ca4
+d = 005eaa818690d1ca4838f0bc667be5721d178c3869884260fb230277c3b
+Qx = 1f7b3b50167cb2ff7482240bade95f2850a02805742e6e29eabf7f9ad34
+Qy = 0f8038a8cffa0f798a01e333251996662bc3c0ee56d94c392269b63edb7
+k = 064d518f7b8c87325d8edfd42a52793d87ef8db283606dd676be8584562
+R = 07128123004a515e277dd5b571e31bbc877cc966e27ed5b2ab2c16e881b
+S = 051d70485148996ec30f92097e4a12b5edf804e03e312072336bd912268
+
+Msg = 8c1a83023930a85c5b2f9930521b8b8963d5523a3323d87f862a17d3505ccee01246ee1029b8b8c2b608772c4096d1e914cb398f027d91184a8e94e4feeae121eabb504a2a35c8bc9294edd15ddd979946c14c792ad787dc2d4deffa284830fc90b3f8c0ced6a99fc6de7c41b9ed261402a6b3d702ff86a9392731ecc37430c0
+d = 0603d89cd2f741d734587e77554fe6bbb1e5739d5ff73084d4de8ed69c4
+Qx = 122f2b7802917e4164ac2f54033621c78cbc7040217e5ded6b9217f95bb
+Qy = 1f867df743e73806957066c2ab45c04bf1af158e146a9d1eda9e974e0d4
+k = 076850b8ca9e454bdb320da624c0dc63e14ad279185e4f8c9e49905666c
+R = 04bc63bafd5bad022fe5db246680a0a0ccd0b50ff50482d3849c92eec7e
+S = 07b6d8a8446ddfc64392af0aa1763d45877023c0be9ec78db47efd3c366
+
+Msg = f3c9dedd7115339dd3ede7d8d06a44de66bf80b4888ab7bc386cd40a92789042440a13d2cc90dbcacca5feeec1e0e3c51724146e2c4904ed6b05c7b4e9b49d7f458ada695c5d2fc36f1193329b87c1268aa38eda9151430aa0bc004e5d2a61b9390accfc699f2efabfec785eb34f52b1beff1e4c5492e922acc348667d2a3986
+d = 07977b3aba53616dac27b4d74930da23966a88ad98f1769674789c0be3d
+Qx = 0aa61b4bd2fa9c61914ae306d69d3ade7d6cf621399e5791dda8a054dcd
+Qy = 12e8d9274d5593f5074c49ca34a7e2d64f9d9ccdf42df6087134b811762
+k = 03b8ee56bebb59207e107bb0c16938cab707e425f38b70f0bc918fc1b8a
+R = 068502a3e5e51f5481aad31eb6614152f4957eef1becfe3a297b023a94c
+S = 07b6b43be63aa79c10876179703b69caf9b03c5401b999a3c5be4737999
+
+Msg = d878c4ee0bd6c84652d7f9e68df7b90cc78776d8d1b60f3e4d7465032bf401f1527ca7bfd4a3dd916e13e93fadaa5e5f20c9f47d12f8fc922a9a3aaeeeef294c221ca1adf7df85b888faec8002f17ff202da1be837827619904121167bee2d2cd694a263d9a99062cada3399dcbfcb283597a96ebec129c65e0850ec4cb4e2d7
+d = 050cd20e7eabd29008cc977d0a17e1195d79587b8f15ac2447e15daafc0
+Qx = 01ff23ff4ea1f30663b17d8f1c67ea37b8c5df7009d0c0301db483803a4
+Qy = 0ec6bde92921b83d4d84be8a67a23e1718e575101b93d9a800550a20e7d
+k = 041ba36d2e810e47c3de583772e9b5908c257b2aec232d855669d4dae2e
+R = 079e96ed1dfc4e31774159ef311805b5f8001203cf37a72921efaf5cbe5
+S = 00b8abcd623b17357f65ac365301a8823365ab948ae3f7fc6a4a0b8ab5d
+
+Msg = ac3c118cc9cbc8eb3b74d8ccc9ecbd81d1996fb25ca43c8a43bffeb244f722b93c9e969241d45d5b81fda0b399f1e3623687190e428dae077e54cad1eff75ec2f7fbb9434bf716833421bc2634885677579c237340f76787b2eb19b446d56c0f2206099b81493349f4db0ecad0e2dbe85dbff7d7070abb3d3b12ef0cec828af4
+d = 02dbb24fcaf9f3cd5d50d209937f0e2d134fa20ee3c9c2f1fff3dfbf302
+Qx = 0a07240c52e385ecf75525201f9810859123bfd8ce04a5e8f4dc4ec88b2
+Qy = 09bd811196ca9ac45b28031b9f65f9a5c4ec497d995f7dec6eb06dd2874
+k = 05785beb1ff70c7bea89b1fa14be09332ef94b09eebcc9fb1150bfe0d55
+R = 05279bb1b1ad8174e88bec4c723d65eda768c1d08d1c64c332a240a284f
+S = 015a90383c2c40ddcf721067b3435915a843f9c4708cc133fd1ee53f442
+
+Msg = 700313698cdfdcf0044ca07bf9e5f0702ece7cc66e35decb28d5f8cb7e7e5367a95cc1728a90cc9a53a2b5fcd4702028b742538e9b386f5d8b4a2411579ed9553021a95bd00a73f03c4184a6145aaa367e3af76659d677fe7a2e98f9ddf4aa20eb8d1a1db72c3f5590598801be7ebf44255fd7376d89d998b7068bd1296fdc38
+d = 0047142197d3d43fa46545b547968680ec81688589d1ec8d7c7e90eb969
+Qx = 179450d83cd6dd1609830ec78011143eb64d2d1509ed1adfa085a58d786
+Qy = 03ee40673ac564c6b5732868d0f8a57727150a23c484228890d768dae54
+k = 064f8892245a198c9c819152edc168e69dc7b562ef1f54dcc1960cc7db1
+R = 0293f2f989fb6b6e7cf304faf3f63eef61ab89a626cf8152e15f38bf93b
+S = 04948643075cea6413b1c88a9bf11aa176611f56d027f2b165d00d46e87
+
+Msg = 0374673e1a685bdee55504ce3cd333f70084dd4ae685464a16924eccea34531663fda60229166478b30193459a3113253cd6494dc26154156252dc6e822552c7c04d790eb9f8fcef2ea8dd79e72f881f7f20fff93cd73ad303c0918ec27c6486c4da61f82bcd55422d16650cc68bfd4b0132c1e7075bbf17dad919095860d445
+d = 031352b49ecde5434aac05f898e6ce4337304845d748f114c14319fe97f
+Qx = 187ae6bc9167d9c69ce5544ad650055cb9a4e69c1772322d5722e68e7e0
+Qy = 0042187e9d11a921adafc694b5cc8da9226ddad1b65f764274954b17333
+k = 0761189e63fc0c3b5db92b281e5a4bc0d6fdb30bd14f8e69ca85a211bc7
+R = 0453560e6e725a2bfe0383884ba3b3dd0816d8522d9e0762f781f6b6340
+S = 01aaec4bd98c765e4830de6593280779d1222918d4acf08c8fc3d0aa351
+
+Msg = 8b237085f135d6e94592f8d855ca397c8c1028236a3b412adefdac888245874f586d06950ee18118f751bfe26f4c31465ec34b578caa44cf1b7109ac4f6eab7f97ff9699b34271df035d3bf58a2ed4bcbf7577cf8e5792b1945ebb9389b680baeb8518c8fdc5540e192aa4fde0eed0d7c82be2e362b286f582d65752c8db7038
+d = 0176f124c24e4420f6e726a6ca25f09dfa0c5a37e5bf879e7bdd36c3b65
+Qx = 098c37cbd44aac5d5c749524b840fd849652349fb3e02cc8f8fd0a23790
+Qy = 151a9a88da407ae41e52b3dad1ea6031c7a36bd834007c0cb1e2c2f2f0f
+k = 022e299985cf289f2fbe2b1b270fbf12ba818cd2b506f642e659cd541bf
+R = 0686ac0c09f90a077cb446c910e07fdf23e845487d0333efc65b9b84147
+S = 01688b18cb42082bea69f18511b0fd9fa35da83d738763cf13ef92a119b
+
+Msg = e3a086ec15574f7017b3cd5f5a47ab7a73980f11074333490dfe9f8ad8926f9ea7c82271aaa74e77133b1025b0b22a6900fbb71251bb6549341a23d194e79d03462cdad52ee0d1b6f5d0d14e1136026961fa3467ccf0864bf7ae3fcc3b68cb35df7324bd9bbe58fc8aa9f63c19feedf19d935b71bf5981c74fb2a487f84e453c
+d = 0755c48c3dbaf71042c58cb137f3632e3cf9d90b7b9a58fd378feef3d19
+Qx = 0bd9a720553afbfc5349e4a65a21fed0444c30304f7018ec1ff6fc8d1f9
+Qy = 109a1d6b9cc4fbd0e888d0a2b6883fd06a5da347c0d4f7882fd29eabcf0
+k = 04fedf8785c6648798748504b1c9b6a066ab6606bc9a69534f93e908f4f
+R = 001e71744a1b683858444da0d270f43b0d5644424f2b38ef48a639685b3
+S = 07ff8199ffe723abacf1947a828e8596dc49ce655319087e4aca6ca34ee
+
+
+[K-283,SHA-224]
+
+Msg = ef90f85fbda05e693006e4c64e1dac56223becaf0890f73b5274e6e289a5a1de2c141b825c24d595b3fd18ca855b5c1aa60dac6b5356275b11be670692cdbe5f282f93ac7b2e410a96cb9e9f80defcde98f3449f99e192bfd62040421a0ab8f99acb85369f25e5efbf81439efa8a5e1d9cf781355a0f47b037b09fe4086389a0
+d = 1e846c830a8ec04e8572d1a9d2df044ab47352fb346f67403a3bf87243871b164511c53
+Qx = 12e43e20941f2641154bb66a56f2e0428a7ad22d607fb8af658df0b382bedc7d5ae22cc
+Qy = 22f226cd65052071066963b112aa302973fe2b5fdd7bb827d13da7634dd2fb9e3852ddb
+k = 03a76f87ede2b5d40a0f10e15e90e29198fc3a03943efea39ddf7afc37ed4e18832af8b
+R = 1be2c776c707098438fbd0561de578e4b9449f955a25626f2fbea257fc578ffa1bbbb70
+S = 1aeef69983da1a535b10a47e66d890c4413c7a8cd6a2511a1a670a4c573d4808f46e23a
+
+Msg = a3ebc17c867cc9c7c28797f6364f6574b80c7ec5b2d8e1542a6f5db8568c15032f92cfbceefa3fe4ee654f690b0455ee5d38dd84bb8665ffc1ff8c849bdbc4aa0ddfdbbca4eb37972fcbcee8cecc1aae21ec736ef61781716b60247b7551ec4e552d0b59a53cec5964c67cf7988787cedf769eabcc9cd5243f58034d96f0e43d
+d = 101c5ed48231a56ca0ea85eb45de0e395e6df2efd4987a226ae36489dd8b2dfbf7c465c
+Qx = 7011260f504d809baefb54af48c890f94fa5984c8bf228baa4b6ea14d46372390d1a8ac
+Qy = 2bbfabb680659aa2611435c4058ed773467a41cdda8250f3490e4f491f1bbae452c5c36
+k = 12a3c7f0b3d64614ff97133873d75c7c1406e316e8cf60d22139dba462055baffe6c8f5
+R = 0a9933496d60716a39e1c3f3bf22a7da546eafebef80dc6f25d0c109ecbc430fdb3e80a
+S = 0be56197a0098b022a7914c10f40207da58403d6c7d04edaf7efc96de740cd71f67e0de
+
+Msg = 60269efa4d0ffafbbc655f6f00578eadce7fc0a7eb7db923dca49b6f2bf3e13f7f829cc6133e022c3c92143c075ab9ced0531a91e6e79848194ab98bb852f40c84e7aebe71fb8bc0fd1f97ed5bb6bad6783d8dc048df42738e841d978456e055e1b8a781dfecfce2218701c7af77e7894ccac5bfff360aab0b6136b978bc39c4
+d = 019679dc589440b11f82b3716e5b2a2bd42c3b1c83e88a28e304cf5148877faf760b4de
+Qx = 743ae04e4b07d154ca0749a011c97a31ac68d8e1da3491f331136873598896e5320ddcf
+Qy = 776c05891c27fd912267ac166bc9acbaecbf80ccdd887aded2d7b8c2a4a5d139833aad3
+k = 099ad7fba5284e406f6cf200a39e398aa0426448c09b95e691f653d6096a63adbd39965
+R = 0285a82340d9a6d96ed9ad0fd0916216fd20edf979df41a55835ef8fafa00d242ef6f11
+S = 0a8548b405c171d2a428507f7adda4944bade7cda6dc580b1d3f94e15d7e10f0a08e008
+
+Msg = 59d704d5b1f3a0605f1497f22f71b8f45b26138bc86371f00a4517554e7f6e7fa5d35189fc656ce68bd2cb8510fa3e3c3df815dfdd749b2b6ac997d443f3954c7a927e138b579801ffd035cea90840733e7884ccfe43d8d3a4a26b430673274aae312abe4ac1e1d7c67b73580fedf2d8de46572493c9205ebf0e8b4d75ccc88c
+d = 1703c21fb1e09f8947e12fddf166fda6f685221fbd803d75a0ae377a54a1e494e6c5e7b
+Qx = 767564e13ae544dab22c3763c5d330a5571e07ff8f2f5ba3fd729379709b1fb184f990c
+Qy = 27f9e5efbd1ff6ac53a6174670eb463b12f70a603354e25c577ea292b13b8e5f022ac9c
+k = 10d875acb4d0dc211a82e78c0249e74de16768003b53830bf5648cf911fef6a57f8f048
+R = 02af92243b9dadcf21561ce32ca0744810478f8d5be8e0f83d9632ecd8e86ff467268b6
+S = 1f6c50fb3bdea228a6b623be9e2ea2c371dcfeb0e604ef1029b6766c43b193d86c02f27
+
+Msg = 12c8fdba3bc5f68e13f7ff8e7bee876fa68a970afc6924314dae0c2482763ced8d4752cec29ea288d350acd8a06c69289ae41ad345a1b88bcccaac903f2bff39015c289a8ad608606bfd65270a7bcdb5fb10c89bbc2d16dcb91fc9735d66103f6b1f3575622cf4d8209290315b033ee1f79968939410f465a2d37add46af2d59
+d = 071de8eb14cbfb88e61b908990ce08b81e624ef4f2cd9cdf3dd7ca9097d5ffed9ae9a71
+Qx = 136d50e1aa8203a0cd2c2d545b81d00b95c6b43b74b1fba3a6402abf756d38087affd49
+Qy = 46bec77240de7bde85ca4345f27c6df341c72a4eccd2cd495e86376c183ccb34f271cd6
+k = 1d80734927505d8d4818b3bdf1aa2e5c557e5f717a5b3fb856ca9a2161bfd74a130ee38
+R = 07894bf10885a698899b118f57e7da22222e3d187a0aabfb99fac0ce0e134b6b44a5f90
+S = 07b4a87592004d6ef8345415064b4b4672db2943c7e6098a9e6d59ee3324847e753703e
+
+Msg = 26013a3ddf687bb2f37d9700923906f118d5cba5d8ed5113a0e3e84cff00918125108f74f4b243e351aa5d07fa7c6ece29f5700f23e50286447883d2a058c3258a12e4ed8770cabe627ebea7ef6e8c77811ed7d9a19c53287093e39226236587ddbc63b7ad5e7ad9895c64d1d03ee432d45a067afe27d4cca920ae88a7a68db1
+d = 1d156eb15762ed00c4021884adbfc2426e910b18a5bc474268196f4b74e593a8f38702b
+Qx = 0a99b45860615d7caab2f4e9bc01196a61f52f95c6c7fef615a4746d48553692d5fcf13
+Qy = 56f81a0088dec1382f8a3a863901d3443c8792cd13ce13a8f63b02d107b66d9d23bc492
+k = 1999524ce9525d85b562fd13634fd9ac50fb76d83b9d72d6976d6fbc47af7e1f354eee7
+R = 067748d49389c9b87a85b518f84f41b18f52569ba531985b8fe5e1f0cf9cffa958da3f0
+S = 00c44a583c704f69160c6258332f3121b022759b163c74c7c96058fa8e3a9928afee948
+
+Msg = c4dbf70b9a2165e7279122460d05ceb8e43e03fbe2ae7c314007fe2b1d8567cac727a10fba5cbead0ddb167d387da8e8f3d6bc0ad851cc32885809d07a776fd4a95a979fe3833610af89df0f454d9edfabe12495a118fe83add5eabb2acf54ba7ba7c4be20fc77478c0a0f0726c4e60317422a612a234a7567648603b63f1c12
+d = 17d6eb1219cab8577168be86b61f372b27ca70fb1f1a767947895c185344e966db17aea
+Qx = 65d8e43a290a6957230501509b95a208a6c37ddcacd1e882d97c73c38b2a256caef5e8b
+Qy = 02169cefa6ce170ce20a0b5463f5bd146224e0813acff304307da88830b0777b86cd3d2
+k = 1519e37a66b4e665b2e3e59b8e836869a886c879aa1ed47901a6c8a8f365efbc67fb410
+R = 1734a8bc9a13f51d921a297bc6b2d38610c20b32b0adfd5efdd01a4db5084f3b0697904
+S = 0f9f00b25a33b166f09e2a819dfda80d87f6a2419a7b4162e435ee02c0fc10a669df6d4
+
+Msg = b1d53b6af1face9b59af11c726b0099111d1adb3666209ba46b1744a528ed0f72be5a1b82423153b896384faebef0362343e2a4599803c08b8513708938aa8a498145fca1c63ba41aff06d1a18aa2a045fce7fcd7e5552a2b98d0df97b6876f06a9cf52a7a40fb737996adda97c3cedf7fe421235ac6951060eba9c0377e72a2
+d = 10ede9be6615b3b2a294d67da78127ffbf3a15bdba6f4fd78be7a60415b5d1a097c0cff
+Qx = 6418eac385ce94c1982c216ffeb0b26f9c061ccdfd785ded75efc6a329385898331fda3
+Qy = 7d41f9cf1248a37fb8baea7f3545bbca707a903966019ad56e4dc810b6863e243968b48
+k = 134ac4de6ed71106d11fa736960eef2873223aa87b1c5bf5c823de6c78092cba4726ec8
+R = 12a37587ddf224faaf8dab61210310792d4ccef650c98155a227bf468b7f323575115cd
+S = 10982c965331cf8529ef6adfe17dc3fde63dc2a557cab451d7c9408a089229e22b73d43
+
+Msg = e78f538b1ac21602b00a09e3db243ef4803b447329c94a1476cd91a88ff790da71421b60092c8a6e55327c7982e7655eb1fd6e40fa9b9fd2f10107dfc585994dfc5bc2143d18794a39f7f69ae679b27dd11ed22040d5e93aa83f71783525a4db0c3fd7b43e57dafd0033d5317680df19c2ecaadcb37ef896c61a758a5e455206
+d = 14f237cface123b64e8578ff33f86bfd2a8181b9c81f36b9ca31e2a446f0d91dbbe2249
+Qx = 7aa347c03d8845f1566bbc3fa1d66ecb41ed1dab0a402405d8300591a1f3078f9fa532c
+Qy = 63bd10274437c2690ed6df60ea632f3d4faefcc07a72ae8d85c2f999bafd373053265dd
+k = 0570bf3b42aa44c11603d94e14b524b8cb1363306196924082ae71021707c3138503031
+R = 10f7f4af1c1e3f9e8e0c95f991c348bce6725f60aa12ee7b398be64728242088a469a58
+S = 17145a39fa4dd237e31a98daf3974138638b9462a31b87ada3eade6bf7f597195eb28b6
+
+Msg = 8a6ca8ec436d2c706fcbec6486b5665b21c174edee7ebe108211c388b1219a8224179f7438e0bb7d6e41ac4a67337b52d4cd9a069fe6c88960ae20be29c8060efd7c62cb7a9a37136a250e68f253e7f27755df53ce7c570135641ad49b43507e5483e17b919cedffdc0d4913b1d5e0ca0629876c0a551841a0fc2090d2857cce
+d = 08dbecb26587cb2ed7df2404e680fcfa5bf8cf6a58e87a350a1600211b3c844ca86daa5
+Qx = 66610ce348821a77e8a6eb74a675ad9312b2622ad2e1e6d8dcd0be8b27d8384844a7234
+Qy = 014c15776bbd144c0c24bf419237db9401fb7f97a7c4c0ef50a9afd27c3964088f79643
+k = 0204586a9314bc14bef8ccce8b9ca3874572b375d01c6b4a41c743c16502a27e91a9fb4
+R = 0fabfeb17bb8c1a57af7af81d99cfb7b0ecbf4e5e4a6ed483aee4be8ee4c70c2ef23941
+S = 08071e162dfeb068e3cad256c3603e07ae48b35f1bafdb726cf4ce32844e1a2181f23f9
+
+Msg = 95bee02b423d2c6e60252da4632f693a2d8f6597b4f9c6e356f670c3a9e4e80063e92facb6421d0325b99dc150464ed2ec1d0bac72a042b35d56d33d2fda686a75d582d4756522218b4ddd25ed45503d90d3d185cba6cf0ac211b22aa4e1318a8316c369186f7130446dafad64f7966f5414f43af37a87127534060a23c6165f
+d = 191badec2d28cbbe62c072c6b57eb5d4644d0c0b3283951bb66096cd15edd43a1bbde53
+Qx = 020224b00428031056ed370147c51e68ffc02e7fe269ca15b22310a2974d383c6c83fcc
+Qy = 1686568fc4768158e75b4ef0427d8e262cd0638801ab158311749e0f432d5b69a667f0d
+k = 03b1b6ca5e627f00176b599b68fe54e1b5a272c323a06b55e4871875c0e729c4c79326a
+R = 1ade251b9360a6ca1b48c2fce0768a01193a415bd23956fee1e5c4c5076b3571abae082
+S = 0adff25020af4e2b4908a33ce1d75c793934921267b6c4a0542924300fce40fc0031021
+
+Msg = ccd7f7c0e04d1ef9a3c5617d77480bc624beed6582bc28e9e3a369b12144fcd96b735ee41713f4173b64b28c6102d82dcfc7876e06e76fc497d1d238bf6d85bb5feca630bbd0c0f0fa7c0c72e28e9259087698973ac66244bc6e69c04deb22eaeaee7b20da239ab6333576f01349c76f594498620933b8969450ac2bae66db8b
+d = 0ff5e3d66eb57fd35ba4472effd6e7a016ca461e39000a7125e99080f6ab6ef4380dd7a
+Qx = 19d8c1d9aca39de0e627981d21e35a628c35fd4096aaa86f61625fcd078f0400f615cd5
+Qy = 52ba2854ccd64407f6779c5e259917b251c9e34ec0d95c05488f30802b82cf4b25b5389
+k = 16c9cabed653c57676ee46c8912cbc507b246078834f1667d0708e4c666346299c1fc03
+R = 12ac0ec9501ac91a2b57220e9c00ec6e815399ede94a658c36f9e89bbf1674316d65dc4
+S = 0c9480160c4e9db4e82b4ad26cb79e083e9e2056e68a2ea554aca45802bbb188389bc4f
+
+Msg = 65e9124a2606c8784c9489add2999f4cbe6186395df20838d653b263a207ec46995d2685b55d1874e7ef05a6a3bb5b60a7be6751ad568cef1bcea2debfc494d1e2ece0dc8028c88f1b2c6e4ee26b639c5e81f6448bd25b73ec4608a8e8cf4e0155c29b6f0a62781493b03bb7384c9808529d5f87da6564ae196a365bd282f46f
+d = 1f3591eec4a8a3fe6ae6debe230d238a6b73cf3791cb735add1abee64239bb100f15166
+Qx = 483e7e2b8f7ff95b86008c3042ab83a4b6a48f15ce1cedbaf3b586b56ab606e6f23a4ef
+Qy = 287cbc8c609426f1665976e8120afb8de96b43978762ed44bea5aa1418b9af6922c6066
+k = 08165da5f5427b38c447382c8dd0940c3bddf8f048185e6cad260031f7c0a2ffb83027e
+R = 09034633dbd735cec6208bb6f4455b295b7d730c9301bbd1c0e9f101399f2b3425a13fd
+S = 0204ec149b416ca3467e92194449cf2ca0f41ca1fde79145f3af856085b298149a3253b
+
+Msg = e793c60fc725fd537d5fd38e9b4fb52e268722ae6bde5a058de8d20db301f5e8d8e1ad85532198835a04b76f27ca3c972be5617a55677cffa8219eb64fe53ced242efe1b889990979227dbaaa15ed39d3b6be8c5a3237ebe12bd96f333d947f80048463d3859e34f865d83faf03894c2243a06cc96788ed952e606c2d8948271
+d = 05af03cdb45961e7ff35fb0146904ddd6c2bfd3cce814073d3aa56eaa9f13b4f7423926
+Qx = 70bf676b9b0db558eeb8bb94a1248bcb599d1e8975ee13cd37dcb78af19307d1b7e57d5
+Qy = 6ed9bf30c627062b99ff9d05ca03441b6194c34364cbe7b73b46ec9716ad8a9970cbc99
+k = 192c7b1fa8f221edecbeaa51447818474dd9fc89e962e8e87400938ef0dff432a6c4b86
+R = 1df1a4f9578e9cae8102aab5eac70eddbabe4ced99b5bab1b1dee59c41b81e392968c14
+S = 0f2b1319335ee497fe3ebf1891a71cded59704365774e1ed9950f79100e70950783bc7c
+
+Msg = a57682d21cebb48190199e9f57493696eae3a59acd22f64d5ef4729decf6c2615b326817a6bc118bb7234bebfc7276dd998838c009a7348e46431574638dadc48538d6048d572e50d9c5974d2049ebe1837dd857bcd1447b1514b62808a4e7a88162ae1bb08a0f6d3db6f25874c6cd0cd4ca6333f1bd57bd192ef67e4616d182
+d = 1ec9710ada06e6270720692a06d488ae2ba863b905dd2fc323e7ce68dedacb35fc8c7d8
+Qx = 5cda72b5b068f70b3c431def41b8ca1d4381e8c2fdf0821cfc17eceadf5e3eabf7987b7
+Qy = 79ae508354fe31899cda71e01cbc80e5192d24f1f13c954208d2ab8412802407ae3763f
+k = 04f7b9372a8fed536396f0b87d4b20494786bdb8db77200c1aac1896486a05d3c940cb5
+R = 072ecde2a8f506f0fef273c8915a9edc29e440d48fc6cefb50e7117492fb4a13e123bed
+S = 0010dbd6229d770c468f5d8bd20edd6928bd8824b7fc2b10dc45fbd3242191e7557b984
+
+[K-283,SHA-256]
+
+Msg = f646e7334e191c2bf0056d3bfd23f03ef7f0777b923f962519a8399d311b8f68414c689ca34b96871fae99eb7ea534fcd83e788e56eeef817cbfe33677283c736b99bf6a626f9515291e842bf99f694e4e8aa7c9911c591a87d5f112b3d96b064594e2b368e6d1bf1a1cd343d54916a66da22c26355266aa2884120fffb8b94d
+d = 0668de088c6913640fbefbe6d2c44ab26e481802dbf957044a4957c3c5d0a0fde331501
+Qx = 0d3a50cb9d347cfe45d2a313813fec8b928a9b1defca6ff4b89c4787717f275c6b7337f
+Qy = 762e47b0669f625c39c74d50e2b46875ef366b7c3b005c16ede69a2fba161faf6b3d0db
+k = 0b24bf54795fa02eb9527f21ead5497a6db2bcc7849a16d206239f830df313dfb7a2716
+R = 0852d8b6fe93b0b36af5d99530eed08669eb9a25972fbea59f32dafe88b722bada98ab5
+S = 0e5b08d410f2252f724dfcecaedb37b92a6c09cde646ff6237007f4199068f945ebebe2
+
+Msg = a2d7e69ea381d3edfde4664c56c4cb140d01cc4425df757975cedc995b89640dc016ab419b137ff25a6a6d64a309b23890439d2ba157262393cf93d15ca1b1ffd19373ef12367f8898aaf56d5544c2f019a4854f69b3d8d320e03135bb7b675e588a5c3fe4b703938fa0f964916501297cee2fd04af767155c7739419f9dbb7b
+d = 0e6af57cf47de1e6f07041eb5e1a413fb7ddd82f8c7f7ce957eb28a118004930bec4dbd
+Qx = 21e31c4e4d412a261e40483b9106bbc1b0d7e7414e53d7b9fd84175229c8cefbbf6defc
+Qy = 46ff2dc601dd407883af7dc71a6ef4286cd3b1b6ccee4fd861865bff8fb38ad51b63d49
+k = 08f9e2113d0b223c04e678e8ebdd3aab4816681a9ef08b18a38afecc57d79c971421469
+R = 0d2c9113a18bd51008fd327a55c214c9584b6f1b816cf3b95e7346080da2cb07dcef8aa
+S = 19167051872759c36ba9eeb5d620cafd3289e8b7660fc847ff385b5143b3aca38780639
+
+Msg = 7088f60e9375ec6a42f705f851fc76cc833c4dcbb3352adcce9f59197c1b7121e7aa661c4f8ad9f4ef280af3a2981e90c01291f7d1cf7d3ae2d96b37fe6975e11b7c6c02b8ef044d1470b1a26b9c72e8c4e7b1dd83c8acc9542e2fc7d211b87841dcceea2ab8128d0ff7bb622b60faa4a89ea7008f7d55f8f9de675bc4596fd8
+d = 19f9b63fde8c6aa6177f2a38981505d04f8ac62bcc21007b05615d028cfe851ab9cbbc6
+Qx = 5a3e567b227869f948180547c2713703c90698dc04864140d22b24bdf81b3996829aca5
+Qy = 5b2ba535040afed0bf6f9d850713e54013729bc6dcbaa336ebbfb9c461f7ac61af48001
+k = 051e20545a0a98dc3fec59e4ebdf101c6aa2768f344c1e19424c1eaae4aaf7ffeb5205f
+R = 05fb3329f63587e8febcdec49f92de88366a9f75d0b9a0f374dadc6e7a62b833753e990
+S = 12edfabf1ce434c850b58804f1f31f8afb20fbb36ee69b68668e231e4c04fa75e658478
+
+Msg = ffd6044ab991849939e8a29184b4d0ac3e07acb63c7e6b886df9e8254073fa800d5910b9fe34fceb547565a2344eed4de394ce2251ed51ec882ee9207eb7340464c742d9d140fa0964f6bcb1efcc2d13919af4f727953de41b20728ab975c1ae0ce784865f23ed1325c68daa95ed5c932893610179be94f13b9a4149f09833b3
+d = 17704c1f436beb52f7ec97192e23e206ec09f9e8986e06bef71467c192bad6f0066b3c2
+Qx = 329294a36ceae2b2c56bb6e21e52ec32af11aca9ab7785be9c2d79652e7960c0cf7a8ae
+Qy = 658a89a48fb95cb7028252fa9792d91b989d7cef3fda8ba9c8e4ffaf19269f2a69f0a24
+k = 0aa8d2e210ae40ba1f9f051ad85d37f7cdea43aad890ef802519cc5773e9a0984fe5d6b
+R = 1908e3a2740fa04ec0b23c964c4c3cca51c4603e7553461dd02f8319a7ca2ca09d0aef5
+S = 12d7860d7b438df4653fe40fb9e986cb035b1384464e061bc4ee3bb29aec74d16b0a694
+
+Msg = c9f81c9ff7d80011fd41f2de97a6c1e6a22cc2da7b2b9e4c50e1354c3e139b44529ac786ce795fc501dcbf11a935d4728a7bba44b4e86b5e5990fed4d3e24fa5ab6f303e1842918f156e00dccebed6897c852207ae5941c630014a41696882066c2b296d39cd8658cb5830eee78e29a00335a99a0ba90722ceca5a2e9a99a2c6
+d = 0c7d1ac8faa689698f5c6325a3b3f35e7730bdbddabd0693f2bfdc5c838bd62f84508d4
+Qx = 095a930071ce56f28a79a66b751283c756c4f2566ebc2a10770ca60cced6914bc9a0d77
+Qy = 46f70021e7a949c7f55b059d4c8e81ee23b13809a35932d83b8398fc8684c5a90f3ec71
+k = 038ae832c25dcd30c1ee3f5fbe84bd8779c876c0641907695aa598132b0e581ea528332
+R = 0eb27c86d3ca86ef53aef0465d257e6b681f891a6357cfbf51260dc6e35a82799de0e97
+S = 0e8207959e8be94e7407543df80d38d9e662106ed68e1456dd1826602c5b73f27ddc901
+
+Msg = a60de761eb32490184dc1d29e21fa33889295ca587b994746874c7289eb9c83e9c7bacbb4066c761a06b65ecd78d701bd41f305cd7eb258c630f3febfbb0a367ad16737b146fd793dab23562e8001cd113135b1c981d1ca23eb3be0fe3e24fe3fe1089caf9fd8f4f0d1f90dcc7dbea4a9e2357793b65daf342b8e6d109c6dd10
+d = 1a173d158866db0ec665ee632b5fc397893f6a44ee17c348e7452800aadd8ce676e7fdc
+Qx = 6a9369a93e0b5165ac6e692db035495c5cdd6df243d9756098385ad616374ac1e1efee2
+Qy = 32f72a02c36954cd8221126e4eaec02668f454214e4508cf72b6d945e14d9b7c5d404c8
+k = 0200713a78f58c755db4897f9b7e52057a087816a07fc388d66d34ea9e0bcf2f47e182a
+R = 11a26ee24610e705a42329f86aaa80d78934b4bbf19314f06eec46067d85c8377e04d91
+S = 077e35add124574e98e0056bbb106cd28ba8c3bc0c47063ceebbbf2684983a2a0061950
+
+Msg = 2cd0320cc73120ef13e83c8144b270c9a1f2049a9250ef7ee83ccc7584025140a51e2227a5ebb824deff55b3affcda63ecb1fd3f337c67c08054dc82fdace0c4bb9cef1bea9dd792635f655363d05903cd6b5ed50ee669bcd8157509366cd85aa40d19593265da26e5641590ccf04672a6df52badd4b99964a8643d9687b499d
+d = 05523cfacf4ed3b74ebc30f608292e45173001d80cc801f729c5f71fc213b243f041ad5
+Qx = 410751ae7d8bb2295f584ba3d55eda41a80b8520b02bb4e5ca669a1003d6f2829e0a01e
+Qy = 5fe16244f76f0c8b24bd3ca3b53c697097e3ab0e2b44962ea534a655d6c7d80b857c21e
+k = 0a634f4cef0ba37c9ab211c57fe6574c67933280c91c8b175fa4164755bcde867fe1772
+R = 0b9f6946a578ee38433e98478a4c31b67e838939cbf128f023090c4848471482fd1dec7
+S = 157159e15a2d16da2e913c5ef00833a8e5513ee4e7d6cdc849fd822c59886d0ca3695ec
+
+Msg = a743d8337bdefc4753f937e869a36439da1f8c75e1278c3f6a4a969d93787dac93293818b1cbef5b8636e1a6cb3acaac1e15dbe0841c8001512b689292f3f4805997ae26ff52f7fe1842512a020c448ed01af2a061f3638689446ed5f6bed9fc70726ce4104bc11142de63873fa7039830223e8f152996388417c48e0c1fa81b
+d = 09f6bd008c04b8823ccc3ee7d5aca535c211f35e9d9e7cfaec518b98647fbe6d28283de
+Qx = 70019957dac0e9be0fce6abdfc00ca737096ba2d2bea9ba570acab6d73eae2132d7eb06
+Qy = 559545f82741ddd1cbb9dab0cd06454fda8abbd9d1eca752e57ec05498b14e4189f1b9e
+k = 0fe407c226fb15bc63d37cc9840a1a1fb0ac4fc2939fbbcb6e1236831379d367669ffd9
+R = 0e96e301bf1193dfdd2815597e016e0a282d6e8f9d1d67a7f7e7d05288594f1ea92584e
+S = 07488687f13c3a2b9ae90536db7868f2bde1529ccdc0c84eb85c53ea979228d1fda7c94
+
+Msg = 6a7a3ad614a3a09d2dc5a80204815d0c6471057acc0fa73f3cbbf1801902c3e1cba3c1134a79a8ce61994a94a5afa85ae1a44b2cdcf5153f8625713c872da36aba0afcc5c2f26636dc3f60e04c256a5b023e20e2e7a3f7305bd5b3033fcf05368589f19021f8c9096a88679904b657bbe5b9bee67d6e53d176fce1de9e54c64b
+d = 150d2812505c82584201e93f6e0cb875d29dc7bd99d9c0f98e0ed20128886e67e1f1071
+Qx = 12c7750172bea15487a05580891aed51bf81548f4b65c51c6c54b990bae8857a20115b0
+Qy = 3db9e7a17dc8b24ff080d80842f0488f17f7d43a40ce6ffad52c65f5a875b4b33efe3fd
+k = 0c5c52dfb50b210ae13c2f664d958b2491bfa91ced638f925941234bcc4d66de1eeeb73
+R = 03887a270eeb515a59a7387d8acbb4e72dcdf13f317a6a93ace5cc98d69a79c64a9e7ea
+S = 0e922b2d021cd71e213bdb36ce3ebf56a34617d4dcca30fc05f238a1c097e38d7cbcf91
+
+Msg = 65bcd77a3ab345cc99b9c1300755288102a6ccf140bc7d1ad25df246ef01fd57a8614b352033b88cc6ffffe5b38b99ecf03baa365ab5529d6751a3c020d0198561969aade09091434d84ffe13b46df043d0a61e20a08e9c32b646771fea1b29e202d40aae1c7079873c3af494ecf6ef5eda855736c9338b4a5c29a086a8266fa
+d = 1b3fb9e1ff70f94bc9d7742ea535ca982215af3df381b5ebdf1db40c7c849a7978ceb98
+Qx = 769a897a443c41ae7a8c1e45290ef39c40887ab8f4aa3f9ee8f3096921222ed7de45739
+Qy = 72621bfa30973da61fb6d363d66db25daf818ce79dd3268ac0520fc99ca7917fa3a2360
+k = 03fa84ee38587f9c848b65b07c47551e27f15e7a87ed0ab705c99c8b7a4ee9e86a8e4ea
+R = 11b214ebe67eda2bd6e84c33be05c4373d2536e2cccf152e56b1569cc96d261e50910cd
+S = 0e100646cbffa016664bb57c1a67108645238573867c0b595c46e6053f844e5482a993a
+
+Msg = ed1acc360d02ee6c36bbc223d91bc1d2009a3e8f8dfc4c3796cd8555b0d2b46716f4c8058bf34c2d4954e098274ab9c2cbacff46a0578a14e77fe104196cbc6d2753e3bb5422b8b79fd004ac0aa920eea94925c016ece16ed4dea916fd92563ec65692a61b28ee84bef0007120bb1e31bb75b8ecf68406a71af9a18b4edf5320
+d = 147fa46fccf0805d14c1b84ea59bb8b8283d54ca0ceefb29b5585e7141340c55b7232f7
+Qx = 4ace4c65ce07fe5ec22c560bc553bd791434a691c2d865c52b5e38d541ef191ef419067
+Qy = 76250c829de137b6549d22a12f196629d9d34cdd83758e5daf45fae41872c9b15190ce5
+k = 18c4f89cc022236a0da6105f19c6661a8325d36fa285e3ca71c1a4af3dccb016cac186a
+R = 0271b421fd572de8a71d1b18ad2325bc0fb58cabaabacc1f015ee6b14bec49762f1f8ce
+S = 12e679010ccb143b7de0c3f6c82cf99a961a4f154be6c87abb111cde2d721d864d7a1bf
+
+Msg = 2debdb95a21d72b69c545988727366a42b819ca6398a82129c5e3772aea93fac0aae9a27b11969ff0ffb9dc0301132ca2452cd863316cf24ae7696422d4dc68e37316161abc146e86f04b72d9a27a350d8545cca245b2be43c33bb822dd813d13e08a718f784845df8a4ef49b02529871ec76bb3fc1ba31089359f2ede73e767
+d = 0fae097ea56b35a517be5480802f450eb832b244558d0cc922cd4a5b40b84d02ef11216
+Qx = 4f6bda2dcb9560174ffa54f13fa5edf17bebd41399a1dce1fe13e82a2b487eddfe25a19
+Qy = 76dd375f2c5f24c342a8e2491271cebf5b97ac666aacecc8d693a85ebd2a93eaccd4059
+k = 05e3a67091b9e10c7fd20fd70d51162e5d78555059802d0c3b133f49b89f37be6a119ad
+R = 0ddf93ef8797571af3cc9a66660c569445a2b5384f95a12d680c570694bce49bf2264cf
+S = 02f50d68bda006b88798d87c232f5ed1796c841074f063da03a471e0c00f08b10f410b3
+
+Msg = e4e0c6c8fc01244abf81e139c961b6a6e2d95de5dff1083e8a48b40e3e5b9ed909152c92b1cf2263179629cdf76ae553b58bb2e9223ce4f9ffb5f170f5f0c5ec97294c34a7529a897e9397f71198cbcd68bb4055cb8cd6b690290761b3b73303f82788379df145358afe28f2997d191d968929b7a4b9a0f6228797dfaa17c613
+d = 026cd72e6ae19b3f4c53493fba1e8082a8df1fb7da6dc111b47a41f713f49b33f618d0c
+Qx = 1c411f5e298c9b61023fb26765cf4132cc78ed77c07c3e815fd43032cdf0ae8b8920f96
+Qy = 35647b4c0807b287014043560d70c9b14651cddff4bdf6d44ead5e87720294ff8954406
+k = 10e9bc449e8480474afffd20b8acd6dd08344981c4a6cc789c5338ad7e486c526d6c4fa
+R = 0e81594f1064e018aa3504bac75946d77f9e745673043417a47c0c82488e224cc4104d7
+S = 111bf8635b1bc3f6cb7f9b685077b38d67160d143ede2bd8b6ae93327d7f55c5317f00f
+
+Msg = 04710947b7c90855ba4e59107b919d4a1df22b503c5c4c33b286b6b08e451e6fbef8ba40852f9f0ee62c9217abe6156bed46ad6f0e25f70f528f3a73d099338c578bebd6879d810e6e173c2b0af1f7caacb3531ff0e6a7856e4c84db355d110febdb21c683223eb5990ef2038d462ddb7962bc0feea5f850954943d53041f66a
+d = 198e13c7d95bbbb6e226688719639bda988867764ffa9b029018b5547850daecf58fe1f
+Qx = 30b511d719217c485866273ffe2996a19e0a670b7a3fb077944a21f63ca2f22fe5a524a
+Qy = 3a4d9a808e8d77c9dfcec6d033139fc33e67d7c8dfd7329c895bfb77f565391c37c8d8f
+k = 1721f1ad4adf3c32614feb7f8df3374e24f76a32e27854a57dcafcbaaa3082b13e461ce
+R = 14b2622432adcfed7c2ecd2b52e43be7f611680ceb4bedbfa9dd9af54532911a07440de
+S = 0ece991128b10399188b18933c0d185e85d111ad401baee5ac376b84c523f130f70fee2
+
+Msg = c62d07bb1ef756b6b2fad355c66b5be086b6dc387b37cbc4a63c841dba3fce65b09d3de8f239e3649382d172f065b78f8a53e0283cf345de06b4ee0b4b7d8611bfce92a7d993b1938419afe817611bc6df3ef74191e7e39ca2339fcb5b5cfee3166d09cd52a1a7d3779722aec328d326a11bbafb6aa417920225ac453146b9b7
+d = 19098a39956747de24ded56435fa1e6c30cc2b8088fe9a75f5d07b2f5939c7a60db64ad
+Qx = 68cf5a2023753717d89d12d6861c8411e6081c3158339573dc5598b1700148d00b39dc5
+Qy = 76a22dcd4ff4f062eeff83a58d2ce6a1808af8733ae254f5157efa8ea35a85cc744692b
+k = 142e4907ce239cdaba562d1fa7305bacff05a75e2927800c7b7ea322b47c9ea47846e12
+R = 104620d752b73379e1e5d35e5b24a793d7a309685c00f8bdb97bba9876999ed9c763d0b
+S = 059cab3abb0738d8af4ea6dcbfca6d0ef11b6e591ca109b040347d7d4736724953cd9fa
+
+[K-283,SHA-384]
+
+Msg = e4d8d49c9bc566261d9134d5e237d9cbd6b67d2619a9bd06b7c9c139e091aa10682cbede114e1d4777d9cd67a16b7d64278e99eed62bbf25ec5a5a8fabcb0a3468b0e73fd02ac6533e04b1110d29da3e34f33eaa228b78341b357a5d892a61beb2168c3bd5e66bffe3f2080a1e246f55a41ebf9d579e188d16991aa060460d6a
+d = 1636bd2be121e07ee83ac5e880cfdfca6a56f2b9d0badff003e872348368c7c2cd96b6c
+Qx = 007acf46ab68744a9baaa33ebf6be20c1c093242b0056bb9885d93a4a9bb4640f17b2ef
+Qy = 15415c1b671e98f00c1fa364bd69cf998c0ae140485159b0a341994a4e27000e108f4fb
+k = 0d0d4886c3500bff68455c41f5840d0313f33ac0155a693d27c66fbdb12791c2b5f8552
+R = 0256b8ff7d37fff7dcc8cc4461984a9bd9661643fd3a68d07fd30d426d10b8c7f4dfa34
+S = 1f516f8ed4372780380a798d2da04d691aec379483bc0d10560ca79edaab453d3e77585
+
+Msg = 2d1358fdffc14630fbc421b443d3c22ba10ef34f15c6c5bb3c73a9b8714e4c411de69b9cd6628fe2eba5efc4862af66ff916505023e0514f564164b389ea422d0f1beb92adcd65baf43556614eba25e43852ba65af78f62d64b36696519ef8284ef7316ea52c365b99f63a39e6701f81ad520d7445cfc0113c38ecdad4bf5b7a
+d = 15e5f555119c19b055b15b0c0d2813068bfc184f864e250b202384f5728bbbda1cb0f5a
+Qx = 13cae2f0c3ba04d039c42cae27de4cf5842a3e24be35d7a3cc7f05083f02951cbeaa63b
+Qy = 5d69ad5b7d64d6b19772a1794562b1fa5c2fea03909bc509e7d47b0e8144acb3c26fddd
+k = 1b881d95b7de9aed9fb5ff0085ca4da2fbd413b9b947066c98aa0257142c9000bbb30e2
+R = 176f9e3c9e9f98b2f5f352ca74310badf9f598f4d42cd2b26e5ea0999ae31e3c678fad2
+S = 1f2dba4e17470cdf7e1815d30771f352807b38080d44465f86044f5969b017c9059daf3
+
+Msg = d6336faa5c3e838f4fa58626eb353d4cff9ba8f0aa0e6c3d0d850e8b22f5b0f047afc97767f1afe2040b85d4e401ba688a4da7a0caca7fac450899092c4fea789231ba9b07782010720f45d16d353798867dd7fef4a324520014ad5cb32684ec50cab742b750e05db040ff51140e8d740f6774a059feeb493b10d8ac722f23fa
+d = 190c8f17bdd38669e345440d2c7631d67cee9c6548c4e7b9452377adb9303430efeda0e
+Qx = 3235a8b7981b3ff376b6b0959a42cb56631fbb9f82f1694b9e273e6b7131e758fa0d370
+Qy = 444e5747420d7f5ffd6119ef43b998d4ea4a58da13ff6fe7f241ccdfd4b6fd33aa93e3d
+k = 0b2a690793107257d7bdc37c492eca48c4c9650ba0d657e6eb62042b16169fbe27f8984
+R = 168a83fcc67e0c155f1fa2329363729872e254f2e0c3ef85f3b3c84fa3406de4191b6e8
+S = 18c0f8e6b486e6d7d16b4103506d74bb2021232c0b1638858295a63ca35e0d6d26a6266
+
+Msg = 07384a3f650bd270b14ca388a441af201b7767a2d47e9033f50cefd3af8257ecb38f5267e141cbbb2ab7327d8fc78cf27198ca3543d39553e178390bf1b921618432ad895e4f8153783a7ac22f4ca3cad4560e64f1ee4a7bcad05df98ea49a3847dc2143b27c243e48be59c869a547988e2205358e8db98b635ca21b745df4d2
+d = 0dbbc2a0409ca58a9e39e33b95fdd15080443c1dbdb5874bee991bd1b127047f08ec9f3
+Qx = 5a687605e54e49e3c40fc5ee8fc014a62d72e8595280a66ce7d367aac2df4d16b98deb3
+Qy = 30abd03dfc224f459dccd1606287cc30016be317c6207532a0725c957ca5fde692a9c43
+k = 16bc5aa29cea64ce3297172f36fe4ce820c943908c21c9967697db0cd93bb8a12e42348
+R = 1b1fdf26a6eb2d736b8c1ab165af2ac31a4c206c5410f61ac7805a68992dbd62b457708
+S = 14e9a22ce703d942a4fe2e84a4c1c1b44538a33fbfe904bfbb17af6490d372acae4668e
+
+Msg = 824f26dcb4ce0ca020982814d5c727e629cbeeaa818c49668f8f6d743f0d0ad362b24cbac48027898f386889ca5411d7d1f9afc69493b1d9ae4d7b695c9fa0a30bb59e6be2cbff79231767e96cd8bba349fa2f97955d56f05430ab4ebd007064e3d5add94dfe255b6deff19650883ce9966e1a2affaf84d9540f65c87ab1f936
+d = 05495e6c59ca1873f36b756579632fd47f9fb95b64f52589d70f2739aa6a3bf8cf8c198
+Qx = 6df40d8259be64c8ac64a28359290bd52e843f330a68c2b605ba4f777d7bd7a798e9344
+Qy = 458667cd7021b291c3415d64f9b054db71d3fe20f232f2a2286aede89ddaf1ee8c68aa0
+k = 138f05303ea63bad47c4c9a9d43c52c264725a668db5b631d9892daa1b71f62656cbf73
+R = 05e35c1f3b30b43cc9d60bf8779f3b31e053de0a390da50ea676dc9722a17ef00d68aec
+S = 1691ecfb826fef1ea0895242129cc3e9a14e1f84fac49d62ffc0a3455ad9c97becd5980
+
+Msg = 07de1e4bb9be15a710a74806d4447b093bc08ed04392d1bd5abb414f5f4b4d9d43520d0e46fc81c2a97e71086b28e53242449ed37fd7ed1c5772dbabc430fcf82ad20437b38eac15820421e51912325c872894452c3f8a10ddb040b35308e583c155c3707b52df467c4945f4e1071126ed46611a3253c297f5cbca9e27f58448
+d = 1724987c9b698519b6c225cf1261b77d0300045e5fd774dcbf13f285e6bd74512cb7edf
+Qx = 46adc9bd5f0cc0d8bc64f4ba491eae3b7f6fb4229bf94b804807c6137787adc0fed4b2f
+Qy = 41375e2c89da41af84529811ce7aef26b983ea8add6e37c32f2b00bd47f23f25e5fe194
+k = 02ea4ed0e87687a50dc3acc7f4c089040ddd367d1a3f470a711501ccaad63c201b87ea6
+R = 1be198a1b6e91453018513902f0a8a085c76a2798a2a0538ede30dab65afb6b9b0496d7
+S = 16342f87a813780aec006ee218a615c4e1c78c0c759d48d4094639b5b4c32a9658c4d9a
+
+Msg = 1edbbbe71057bf7d0bfda922be21a3a4dff57b017ebf6fa99651246cd173bdc9b11eefd048ea599c1f98e907932aa04f64ed0a007831f30daf186c88807400970904d6090b2cf181e0f65f03b4234aceeb420867812562e47f452152bb1ddaaa48487170d06e47c5e9a7c0faa4fe494663d2fec22f7665ceffffc214b21c6b8f
+d = 1a5489091cfd51a0970508ee3e8449081ed175928ff8386592c83043a7911bbc2f8778b
+Qx = 0aa1562c94bd16a3f8a1d6c465908ce3b83ba6711e7d8b0b9353d3c55d13dee213aba70
+Qy = 103a789854f63a139e31348f1b2608f1e71c88b5d42809f2460642ff46a470ad8573543
+k = 18435a6d3bc02b3019e1b156ddd6f3e1bb9c5af70d1a2cd2089e677cbacc21624ec8947
+R = 031f561b668aeeb4df43a3a34716c4e67232f56959104b7237b26e3c95dd40e15eb076b
+S = 0f2ddb6e6d18a7393425c16b3e5a5aa232cc48198d63e46a601cd3ed221a8427178a0bb
+
+Msg = db5cf1de38a5187af11c1f0f19a36db52f8417de997229e83072fb51a3b7152a3b383e9919c1b8427582e53d4e7e25433d46cdf01492021c237ea0a87d38c71634743115a6b2aba66d3faa8003158340a5078171e0bd55a6e5d8c7fb2631a31c1204e1479bbfe79ac70d5e5823af502922a900576f0088a33e42ec3e26c0089e
+d = 1a45ecda0788fbd7cb7a716dcf4c6e83d4148bf63ed58078690ebd238c00329c462590a
+Qx = 7a1e2fb4e8e79e3946086fa65042362418db0dce51541121c73972a435aecb99f634023
+Qy = 06bb02df9899ac3f207732fa7cdbc36a60c17592af7ce06b8df4255110e26a02b231800
+k = 1c986f88ba3d5109c0afa2c213dda8df462282f024cc8efc758a5342a0de91c40452443
+R = 1efbd9e0d912e170c9c55bfbdfa6106fea4a4e013e7dc26628a1aea4f6b806a51866003
+S = 0b1347f4f85adef612f5c3a436cfa59eaced5c7cfdbb69444936d71812a2ab2461bbb5b
+
+Msg = 4adaa850eec8272d25d76600aacf2cf66e754f6c5efa65c55a2a31b7bc69437d9a7e47c6f51c5da93895a45221f5f92c2e20ee6a95eed3cc7249688261a35d82872284900eb54dd1df6024ec48963ce43e8ed8b8cca8ed22beee8f0aadeae53726cca05443316537840ab824cd1b595f36064e9a19333748d4f4972178e7f5ae
+d = 11461776c33f20b176dc8f2b0cb2446a9b69e55b6c7bc7457a7fb4639116b452b79661a
+Qx = 043ba7157559659954ac58b44f19262bef9e3a00829c70af66d07cef08ad899d7f8ec23
+Qy = 1e8dd9c947b5a6decd1a26fc5d0eecc9605d22abda747fca038571bb37036d9034e8061
+k = 18b231de7fc499b461afed9b80f4405bc005011865cdfeb25570b7c0ff79b6ae94b6ce9
+R = 0fb203f47a4e2e9365ce070ee7fd4540f3f7e9ecf69b4400eeded0f5a7bf6e5a5c6d004
+S = 0e635dc65233f27b8350db22b90a3b8611e6fd1b3e0f515e42fe8788b1376079816308e
+
+Msg = 11d212a99c39fb5e4ca0096bbe6c81ae1490e1b8e07374b4e773bee4fdd24a3c13d653919db663d2c32aa4db140c4ae2d472d4f878946e527ad33b3dc93012d97458f96cb622ddb56f1ce7c2474ad0d5291dc35545de47b7053d137a8e79dabe06757ab53e26eaf751111bd27690e57ffdab5337eb6f81889e9d1b1ac729012f
+d = 025a65f627db2b4d6cf83c5b0c00265b9b63f7656c5e3382139e4992bcdf3cab502844a
+Qx = 5a35e7e0b914a3e01ce3a885192d2ecd27418e09898631de122db0c48e8b58658720fcc
+Qy = 009eab47197d5f56927848855b6ff96db7c36f810ee7c89b305ef780ba8c993d65537ab
+k = 18516ceafb61cf2c7e7c511a8918bfe394c7fb2fbc40fb3052e156cd4020fc674684f84
+R = 1892ac13b86ad00e38ce2427c8c78c93b08605a75ca22b3658132dcf9d9df7c4b5540a0
+S = 0437b33615c16a85ccb8c4769ee7c5f94122d31e2b5fe66291b401fd90257ebefe33818
+
+Msg = 9e4ec74c09528fdf3153a0f6955f20c70915ff524b2e19c991ec4c5b41ea9185e3e876a02ed6f27c9b3479dba951bee8680c4c99be1a626808114408856994be7444ccbd5ef9859fa479b1050bb836034e20c531b4d618f5843fe1d4b613a731895b489a2363f3f5397d5ff964cf037e9b11e3ff5e1c3d403e5a46b8387c1241
+d = 173b28fc29f10245221a907778708b3ee62e0480aa9051d4c3eb4e8d552e6aad5509943
+Qx = 24bb9bdef975af892ddc1bbd31314926a9c81f8f1864829edafdfe2744e793c100c0483
+Qy = 28ddde61b4361ced9c391c86c28ece9b902c48d14c61684962007dfd69d0468dfd65e7f
+k = 199af64f79ebbc5b789d4676a07c224e4f6fd33285e5a555ac90cf65d0b669bc58ced4f
+R = 137d746d515b90890a413685bd9b26a1c05efee4c11a4b40bb621c9fa2580c46c20a687
+S = 1647f70ab7c68a0f522420893a466940ccf79067b323d940369f8b8694ccc3fc0daccad
+
+Msg = 5fe8253d2134c434cb0866796013722e82184638b024a5a30938039929ccd8415c71f71f239c5c5a81f7a9cb493dde209f189bcf766c17c6d9589cd0c7de7f07ff9f24d2320669b589d084f8a8ea71127b9760b7355b162616afb34bcdcd416f1a062035102e29b70069b2b4dbf70179b8d60bc2ee5a455efd40194533bf560a
+d = 0624616adcd45e1fdc6cfeab2b17230d73d91fe0b39f4664f3c6891554f9b8e238257f7
+Qx = 10917ef84bd5c0b36c97cb5586d3057a34f2827f239cab2af2e6081c5bdffd48dccb0b2
+Qy = 78ab47fe1bd3e28055c688c78e617ddcf6c5060123e9d65c562df2e94cac973ab3b1807
+k = 0795e229185bc1b3d6d69b08189fdd7a822cd18ac55971e4b35e51838bf12eacbc50e2e
+R = 185483378a162b8edd6a12f44e3aa4ff829630fe3a1c9ccc66e34775f69bb6a94282489
+S = 01662cde6cd497be7966a0a77b0626ba3c4b82e20bb3f2e839178a31aaf440aa0e059cd
+
+Msg = db49891838fe23f0530abd4a4fbba5ea970afa5747f6a0a10d2cf4d841581ea2178705c1203f00cafec91d0a72d25448072c9cf7d7ca5580b39f8589ec63128faa95cb0689574a6bebd515049a1eb9699922cde0366b5cd58aa8f3d3e847706896f7e1cac667fbfe94b2eca9e7be79a810806ca4bf53f219bb30532ca2254c11
+d = 199757ffaa2c59e198d66824eaad37cc42d49b2e241b6a60382d05e425e800eaaf32470
+Qx = 6ad18bdb3e51cc053f56b9f9c35e2d6eaecbc9749f41a9ffbf54634838d7745ca064890
+Qy = 5dd77c42b31aebbbb46277176df08d81919ee0d9ddf14c3e4c0cccb207bf649c48fc8b9
+k = 109d6332ceec5ea211f642a746a6ce055986b4a2feeed7e847904f7f411bf8361318d92
+R = 1a49fe690a34151056d290790a6bfa7b70958e69e9baeb30c55efc61dc5dc4934f2fc95
+S = 1710a4ba5b404d65f66a8fca2751a920224db0cc0266f7b0bc054069ea4cc51b1f017bb
+
+Msg = 29d385d09c1142a7c181fe4b6e6132e414c15aa8605b44208c0399464613b966edcc2d46cf203a3f85d943d8eae658695dac74366224a0d0348083bec0106f5eb8809ae8d07f792fdd7c48fb1a25d5ef3bb9acd40b20c61c821024a9acb2ede321bd2d0dda849c22d76f421cbd8d51565d3c4266f666455ca1c0c3777aa44107
+d = 06e51381dcf21050aef2e9b97e35303cf3bd91956854ecf9b6b9827871d2efbe8201c5e
+Qx = 52fee805d7938b8b97459b9fcb4b80cbe29f20a9aaebc07ac019539a4a966c5ee41751d
+Qy = 78aaae02974de6530f285b4bbe87fd5d0c9a2ecfde5fdc9a3303e4b988f673c778004bc
+k = 0b426ebda6628125d73efd84e6bbab6c4c8fcf7fa29ffb3c8d6b0a861dbf81cd18d088f
+R = 1270045e963b59e4a4f1237c2240a5b26a7ba8e28ea01326fbec00e5d95d40e859d88b3
+S = 1d721477ee1df1388e1b7f92c048e5759c060ce1291098a2fa647974a62a258a189b4cd
+
+Msg = 774c1cb8fb4f69ecfb5c7857d46415568d88f1f9f05a4bf64a1e1ff6d64aec16e1d09292010d1f067c68dddbcde06ea49be2ad3838053f0b9c0c2383edc451ef0188565118e7b3c66a4fa372b96633dc8a753106283b02d0322df273d58cc9bd061ec219f1e1a9c8ca1400e5e39c1b2c254273377dc98a1a2c44e5c2a5b89167
+d = 018adcc22cb9a2db64bad3d60f1608c353e091637b948914115ebd43679904f955c8732
+Qx = 0630bdd8937e961d5396f9ea5310123a340ba316fbb7d79bf8573f27a0065c6fd6f8890
+Qy = 737a0ac1116e0e2979f973cd705588a71cec5e2a9f22e7e81fc61a4375624f55a6182bc
+k = 10a0c04762d02f9d3014bbff287864743426cee14daa43b22149ce73d1ba609c0ba6be6
+R = 0ac29b041a6b95f9ab685470f50445d416df5f7ee06313185794f2b542fcc00606bed69
+S = 00a4241b97b6ccf0dcd533a15867f5889349ec353395d47e31c9eb6b8785736b3e285cf
+
+[K-283,SHA-512]
+
+Msg = c406aa4295f85c854b4db2de5a7a2defae53a319866921a3673af5b48c85ef22f6eb4cef892c790d8e64530fc20c729b2821b5f5e515560b1ac764106560c3a6a05657e34cd6deadfe2884bd288cef4ca92e1f25adde7d68a30fb0a1b3678156ced62e466718e68e9d67099ad82613b8d06bdda1a7b867c2455422818ae9eeac
+d = 1898276f159c10d92d8d4b6ae214d68c72792a4b5f1f79936ca3c063dc8d9a88be439e2
+Qx = 394cf9bb273923c88be7a1c49412ab8599e0cc5509926102c122326bc0b34243f7d1cf3
+Qy = 72330906f47e8fe95f63d0f0aca1115e77fc702a923c32a16505bcd9021da05fd9cf63b
+k = 058772fbb30227a136de616ace4a0334be0996d60e9772ae9bf672b7c38fe3ee1b24f98
+R = 10e0cd3fccd1728e99e2294efd6dd4797b6492ad95a789aab7fbd177475a047f1e5d38f
+S = 0c5e0b2d1991718355be14bc57e2d6ff9fa63e0812b9adae69f64da610cc6cbe36fe4c5
+
+Msg = cb2809152f8258660933472c06ddcdb65f6d5221fa29d5b0efec9c2a7914dbbf9ce0a468ce146fb333d26f510a87a6bb01bf8816756a1b5df81c5f65360957cae84ba038e37e88777580e91c34e2f5aef4fb55af7b81ad28aeba05e0b1c64a15381a6719fd2c16e38a441516e1b394952d984baf9e051b1dc1bda2e12f8ba5b8
+d = 12ff37c808c3cc029a9cfbb67a5ed21f3bf362b49270d4ed0f1e38fad25ebd79f112a50
+Qx = 0cc00fb36bf62e777a9f6048761e53633b92866158200c43900db95aa1342b576029090
+Qy = 55d7e57221ad939f5639282cbfc203114ee69baab4fdf194f4d2a937d8a57b70b54a907
+k = 163d8eec726d01a1bbb19995777919f68689f7c2920f3549fef966593c4fb012a5c3a1e
+R = 0cbf5c3bf1ee58869e1d3c15a05c23217f1c252da97f79334bc79efe3f5c62164669ac9
+S = 1fd51644f471ea497b0560b65fdfa2fd0a6cef469021303f97753d22ce1993d1ae5b96f
+
+Msg = e060af96d4a7fe512bbf26be9a27bb6a8ff37547d4a7bbbfa710db24cffcfc760dac120f89f642880db2df6307f9ea5441d5932d49762d182b29d8e7fb067a61ab0df622f75cecc917e27d0326085d34581e052c85f50a37713e27518aed7c4434f86970e00a0a4b8503989e72614131b7164c1bdc82d2b6aeac0787f9838476
+d = 02b8c1fef9c6def32b5f4127273ce384b6add4aecec957c1662f52334f5ee97f49852d4
+Qx = 36a4fe1d77bc431012d25ff49fb5468f975353be70e7507d71966a0ef433df51dc32324
+Qy = 58d705cc883a690641f0ab85af4959ef4258a7ba9cde36dab77c125a1de1d395366584b
+k = 0865f59502382b324e1dbd75db150f342336fb19145fb43a733971da555ac5828a3457f
+R = 1ccb2e56c02cbe8038bf78dea256704ee6e51054668ba8c2ba11aef4ac6f9320d46ee8d
+S = 030e662c0e7d47cb3b835c63599d0c9c2e77ca47dbecd7ac834c2babeb039eb630cd0ef
+
+Msg = d235c31f0a82957a087c7597673970aa39321d4c2640685a03df8388b5eae4825d1fee29926f416d5e62a2e9ca1ea7cefffd31607e750fa9675983608e0f8dc895371b190574d065c5c0c23ffdaf49e65362914363a3fffbc2c1bb487cbd4f69ec22dda5c7dc3bbab805c81faa85787cc176bc0e5703924f395d8c9e7e7701e2
+d = 0afb1c45e9a9f02942b8e04da4b815498454dde6643de186625a98b3c1c6993abc8bba4
+Qx = 02fed49c59e9d5c09202a5dc29d8dd527a870a180feded66ea6fc94ee094122ae97656b
+Qy = 3620820bdd5910037f5877649be38db3571a9c6ac632602d2013d0d5abe1f00133f6cde
+k = 1fe749d9916f11100af525ee343b3b74a493f92339e432a482dc8e86ffb5affc4630037
+R = 120f6f13331cd4d1a5b9707483c74dc0722452062cd4534e94cf40840d22ae263244a51
+S = 0bc2e37a481478f879de612cf4a833f7e12b8df33f5b0d6ac5f5aa431678ff053e2bc1a
+
+Msg = 1a2559777a5fd8f269048feda82c4d9fceca95803f84a813789d6ed070422240e443789c5231d63d5268ddebc060dfb99c4eff2ff115d2984d8bbc5c05314562ea6864fd543e7e0a3b8572c017d8ae3563027d79bbe164d40a5bab354720e45094b9b26391ceb55339592fc2f10b97dc9c2649f7227648f5cd2fc46d78d31c0e
+d = 0ff537d73a4da0ae3a4894016b71dccef3bc886f3d24a5abb7dd96cf8fdcbdf0fdc5e51
+Qx = 01bd0537dfb29f727f91fb469c31164e1bb0ee192a5b89b880f3fa40e3e5437f0d2f9e1
+Qy = 6df9bab2f9198494094a63f2ea091f60108449f0741806400694a93702f61fb0351a81e
+k = 0bbc511c6e1772ca6cd1cd308126c18c5db498055a4b3f1cb0dba3285f6d38b083e647f
+R = 1ba756f3c89b732398b90bfa2f92b2a77159c530a8020b75cdb9697c6d75c18d36040b4
+S = 18207cf326bfe97d657ac4197ee5c20c75431ee552681a92a5815db0d984fe597700bbf
+
+Msg = 658c0d3f764bbc952fa55a258bac16a5bb5184bfa76cee06baf9ee6b9ac3f116e08bb2406b1dd4be487b057f3b29c2043ebc33019b2017c4deccb86f50ff15fc9248ea5fb64261120b1960525aec3cc18827c23291722c5add8a3761ff8516c61956c62b8cbb13f3d92bf3eb45a70704c01bb3625d21c38ffa83a6db086ee968
+d = 16000d2e879906d1040b32eb6ba3caff700e5565871ac75f10c5c15b509964bbe5e14c7
+Qx = 2ba89255d1c89e42518662611e2efe3b5e3b8043926ae9c43974ee2986185269246a433
+Qy = 2b87762b9ada81bde958d1f9b81246f49098695391ba3b4b3b9ac5727f19fe42fd07946
+k = 14e837476e628007b2df21b5035a39c24cd4869bb52dbbe13c9666ddd8a7e3eeae29f65
+R = 1b5091fc755c0f908ee13ef9bee40dd16a5710befd1e265a312e595842d52cc135fd722
+S = 0fa25f43c3c074d702e45d216e3704d942e9d67b3c0728645ac6c53b9be7300061e5fe5
+
+Msg = 4f10001e3517c2c1f973b555f4827681e096d860c4db08f1f4aef8000c9c24bebe59f8bf3d7d3cac959a1a5477bb0ea43f2e746b5d14ed48a58ef35484b0ac786d2fec669f945e846ad73e6b77a9e47012a951b398941566330d89125eb3c1fbb2f06adb951ff5f047d102fdf28b5cadb4a3e1a10412eb3474d2ed5c3fce78f5
+d = 019528d505bf0584628d0214bc857150a929d3f59619bf8f3acab545fff0977c9bcdc97
+Qx = 0cc8863e1443e61fedc61abaff87d80450345489728d78c333b36fa28d8754a29cf3ba1
+Qy = 0205ae70c35396c07f9f96aa7c59cf8a28aa2a365b4a1b68e7414d8c4ae5220c8bae9ae
+k = 13d555426101fa3c239b7830fe0b6cf08a1c01f9a991f806c84baae20daddf5dec8f868
+R = 0af8bd9856dfd783217cf81b09b464614aa824b0298f35308e6427c679607853eb66c7d
+S = 0e6c1933d6ce25d0a00effbaf1db2cb2542cbe7521330c34286cf3bdffc20c001cd7722
+
+Msg = c43ec3c3232cae59bdea7cfaf18a4672035dbd2b8b6b1b44ede376b36cc2d8baeb921e416aa177f5977da8bf1d713509e5251278b6622790056271715cd5feac58bee5baf50b216e8eb886279c5a384cdb696470275b7487fe9ac4c506706f6b0f9809d1ccb102546a4297d2017c2a8df9f02f30d3d1bd9aebf6a92a02e0d202
+d = 067795ce117bc0a389397fc22a01cfd9422cfbfb5aa44131938a8c45e48e1d5a718539c
+Qx = 07924de08acfae6260009cc2f02daa2fc2a809e6ab4cd8858a9e9c2c15b17e29f1bc5ee
+Qy = 04f36cc2d36df63474a579b96f6e59b890782ad8fa865efd80abd798ca2938bacbf8212
+k = 1bf3242e75f8331fe70113ec8e14ad0814850bb8cb262c7d0a44ca69de52d32dfcabd0c
+R = 145148d59c5be2b6d39dfa33e904c161456822ec0ad64b9dc52befbd6496c9303fc062f
+S = 0b75c3c404d694e086c0f5aafd534e7d8596601f675b2fac9384fca6084711e35149f9c
+
+Msg = 9b7d675a3d2cdeb280ea28289b5fc2a3ef6b535ebee8ad242fb031e2e1f364e8ee806568b2f8627c5a5b4f51f4f65c71acdc1152c08b9211b81907b551e0ff47f5a6aca45dcfa06f09bf195d19d7b165b52111b601fbd97b192f62465f8ba20773b1599c8041e91448eac7a5763ca0628f40768324c5304e1119ca6a1fdb0778
+d = 19269dbfe4184249952a651a507584746c5b62c64cb3b17e0158aaf4d086a4afb0330c1
+Qx = 6c60a475f2a3635fa523e1b138edc36f51e94a34e75989c2cacdf8949115d96f11ae752
+Qy = 494d5e23ba9071b3e52c58b1d0740cf90cee7b084b9ef7a4a7be8aa47ce7b3d97c8c51d
+k = 111f4dc771b6ce5cc2f42172d3d70fe77c73683bdd2ea331ff711b7e9d8c3e4f2d7d6cb
+R = 027f224c01847c52ebc180ae81009923ae3453be1e0d94b5c2934603577f36653ecfccb
+S = 1e7b771631e5e72b7ddfb9c73f684b93270269ba4216cf3926e43b2ceb49756e7e7e0e6
+
+Msg = f4a08daf8f66ce57a986f14b918099bcadcc4308bcde7c169ce8536a40d94a928cfc0968180a2c2a242c59df73ff79a03687998c421cf9a0e661630378779a4744ae2a6cd24ff61d7fcd6c11a4c8bcaf358075e96f864df0998ee98ee393b37bb38747b70bb7a208740959b45174a60153ee566e0f62528e9a5e4466186fa650
+d = 03835814de0d6441cd80a44e40350cc8bd62ffcc81e939a4410bb9c9259e30463c453b5
+Qx = 5ce9f6c979bc1d6bc41f41095b7677cc184da8918265a7f0e5b9dbece2ca9e0667cfbad
+Qy = 39a395aeaa04f5168de809164285974d306e474a610d89fd401c375c9b73f0d23dbbcf0
+k = 0b714d734d063aa81a389be69c56dcc23bcced3517e330572f79c769645e7dd2fd55c20
+R = 0e4d4494f91e79f2b1d1c0e22ebf744ef448f57c951f1b5f4da3592fe60008ab00f5f7e
+S = 02edaa4d8731b598c24b993dc5bb4888ea3c2dfe2807daf88170982667e69b76a8ecfe0
+
+Msg = 864647405c70939fdb4c026bcad53218ba1d438d82c9138f0f0ecac815dbfb242307cca52c84826cf6556c51082a23f14252dfaea43ba229f7493db2bf8ae9cdb0228dab9e25cf385b504b92cca94f813acceaa1f18de851b8936c4dfe9e4e17002f02dded6b4c231ea5e614ab46fcdd637b8c6193e8d0c2df1b3d883b97e1e8
+d = 0aee83dbed3b703cb6e60d51e373eb20e298ac005fa6a572d02fa1e6da0345558ad2a46
+Qx = 0dc25760af992a8ecc108373281bd0d246f95933ec943f6346c1b2b941a03b33951f622
+Qy = 6e35f02d225ba11d2ed7ea392898f78ca0deb2a47871eba6cd2be7440a410d910097de2
+k = 1df142187f8b27f4888075a3784aebe0fb7d80b0b6d3497a7adbb88cb6bd26cb82109c4
+R = 05a530bf1135ea6d599928cb0383f5d391d19be333b1577ee4eb6f2a78b54e4aac0e09b
+S = 06f3033cf392f698d1a1141cabf138c411f4e20687920f2915e17e805e8657a887c7953
+
+Msg = c87c8f3ad5c28a027b28ae5021dbe8d425f74181d519451f1fead7a1f9dd102fa6785b147b610610cb59bfa91fa363bb79ea602a7d7e1439f874c5dce748e5c320560c2d9676f3a948754c72b6db249478b7e19c9829ab4de2e344535d3e0b7c20c272f82556a280ef491524b255c4fafb9c8ecb87b0149ddd9d7bf6159e3337
+d = 17b65c66514019ff935e9d571a4e68e9ee4463b7b9a754b93f4f7741693f4399879fa8a
+Qx = 5bfb704629596ed05096783e49864a11874f319b4020917f1ba700ddb0606e6e72c1793
+Qy = 69194592be64c33c2f63771af0e4100d060e9750031048002680541815b311ba8f7ffa9
+k = 171b5c698175300b95dfd5ed8d3fd7cf4e19105ed7193b6013103555808743501ee8c46
+R = 13f001f287dd5c7ad9af8d0105b47caed66ede41dc1e121a602610ce20e41af91cbe586
+S = 1433d5263d5233c40c0ca526b3657fcce8cb88ee65105b5f5ec82b26e12bfff11c8812a
+
+Msg = ac7da7611e2ade20aad64b418a16e02e79ab4894d758550210eb10013a9b5533132be701f8843c840807c4167c38d21dff168d3baa65d5bcf285b73dcbb75819f8d7a20a849de335e19bae2aab2ca560b93d340731f291599a5b28afd7737460d291105cbba6d0290e836f6f6c1113d1b2faf90ac5de7c64e25206d79380a4ed
+d = 17d2071f39ba35515a8ec977ddd36ca15983e15bcda626f15af61d87d58114f4c80a8be
+Qx = 6f09c255fdaf78d7d341fde4586526fcdec34a28448c7fe65685a67b6c33564ce9249a3
+Qy = 24ae4483fcbe3f823a7ce53db96ef2f6c68670e107e68cee4f358dfa844112d6b2144e1
+k = 1403078da10f55724fe7b56dfc55990507307386ba82ca8f6340d33769ab1f6ca894bdd
+R = 0a54a35767a1cc77b2332b04694404fe5a31ed8851ccc2abfa5542b0f5acd9be9b1f02e
+S = 0577e0a1937172a6d45177c2b328d72f75a08a8a774a31151b89fd451d531348695d870
+
+Msg = 5757c472fa2f81430dd920f39b61066a28c870b80e6c96f822f8f19b398c3574d159cc22120454dcd7e97be8211916e4bc8db365b2dbb99a6e597d06e6645046a0abdccbd06741e9c0eedf33cb78d78a540c2a390719acc498331e694e6b0118cf4f787b51c7b7237458a6149d6dbd0a08bae8097e919f970fde920485e9a0ac
+d = 11504659e12235855fe55220287a101e511d39a627f8a0d414446385d4a88f31507fe74
+Qx = 192fb9bcd157c7ef385d48470c3173ccf1ef9650da7d680d8473d45ab2064a073232ac3
+Qy = 14ddf872b711157d121b0a61b88a7eeb7cd260f1f82ec5f62fa2681e28c7f2640e305e7
+k = 17e10962721f041946bb5ffcce724c9f284b1c8970f974a069c36dd4391adb8cecb8bde
+R = 1546450d25e2536aa14b8751e3b3e7eeec8a6c1cd967ba0f03e6bfe64c0a59072280636
+S = 0159c8d6499fcfe8ac7b2e84990a714d7888d883c16c016c4b165f36d62c3493afa67f1
+
+Msg = e350383d04af0f4081bf09b95d1d53040e7acc64e56b13b653df31dd119617b800e0cdfeb935dfa5d94f1d7814688d8ce41021810958759cec76560e1e5c0581456acd1a020165849b2203f1c11d318d816697f36a86b59f160faeac7dba71682d3c031d0d547725ef69cbaa28345512e38b75ab011911d8924b2d17a857a96b
+d = 16e4cbabb03215767249ba2a608708b78d7387be9e77f5efd2462467fa05e8dcde2c036
+Qx = 112b7ea5d21df8ce52772a1b76a52ef6f0da62cb7718a467a034618b7ce701a05cd2467
+Qy = 649e0ad181437b4eeec87e202d8fab1c240f9dd9b31311284c24d89160b1895be541319
+k = 120e4bce412311d3e7adb36dc11d4cc1da8a4b9d6cd5219e772b3dc2b2b8ce08833748f
+R = 1ff2d53a8e6c1c23807eee681156a146e8f2cc1a8c262850dc69dece31860bf094e7f73
+S = 1e8906c0bf2a5f922ca271def90d704a1425e5cacc64bc5761b000c7df0f8f9fab51f2c
+
+
+[K-409,SHA-224]
+
+Msg = f153cc61981a46d8a47d17d29ec157fa93fcf644beb84558db7c99c57fb131dcbc5b65581ced5ff0b29bfdc66ff703ecdd4290f7c353c02a3e6d6867f33f3dccd1a0b6752b8a35fa143f8921a5078af9c85b212564c5b795da9858c7955095938fcd10c21e35e1abe905e84c8b4bc05f2a06091ce876d9519b96951d08c7ac9e
+d = 011c6528939672bed3e8c905b7ba594c3ce95f37fb28044f210cccd01dfdb42c10e8e1a0b5d6fc757834ca7f08e98cbc52b0edd
+Qx = 00b570ec1fd09d7b4d102f83cf37129d94c9cf2f982b702c5d1172bae2df558008518493c08dac6f76a6646156f123c4f33e798
+Qy = 0e3cfe1aafbf25a5a4536d6c0cfe13a540b4a3c97d4e7bc6c0346addb4b0c32dce089a7a5385e8a3e67606b45e2062c642bbbad
+k = 027cecbe83853037cf46aa98e1e1e552a96af0bb24e57756d8239fea5d769b51b83f195b7801b562259ee644ab4047764d130a0
+R = 06a1601e07dfdff9d3b4ffdbff124b717403490853099fb4a00ea98f84ddd64e908f99b40a2ba6ab88b2491a8d948fcc2f207db
+S = 0741d27c0dddca3641b56ba1e9bacb0da1fcee46b9e33ecc6990b98cf0db74668ef1009a50e5d55f80e6642ea48689a529c8a08
+
+Msg = 258c91524423b5c876432b1930c7b07b56eb5e3945f1e2296a4e5bfb9b9123f800ad195d6104641b1f1970bca553c2032f83d17252e52403a9381c1fc18eaffdf026f7537aa27d84c5e3d6e39e651a92a41139cec5181fe794457f556b390943093be719acd23fa1ddf7ff0aaf0479484a381a309b4f681af74bf97caef08c22
+d = 07e3b714496dd118d8f3f597961eec5c43d0265bf85723b0b9b0616977e0acc2cf686cb6afa6cdc19114e27ab000e762dfe467b
+Qx = 07dea0ceb73b9bfaff7147a36436cfa7955eab02ce7fe9b60dcff3e088c5c9281be5907de3e06ebb2e21dce8bf3ff85feeed500
+Qy = 1cfa9b30af20612666e5df798f91eb4647d8f5e1747c1b18adc6b73a848d987434c56d13ad78b775c4096e9f20d4878bbd9572c
+k = 028a8353c05129dcaa7caf0343130bf2e2186b9cb5ed0a27a565e1c24eb882617cc299d486be76fe0f8f3c52678b6992288d7c8
+R = 034299ca2aaaad51f12c90e8205da305523713516ba6e7d245eed8ef94a1b2409b98ae93476aed6c9b9aef50406860b4e490db6
+S = 01a1adc76c65d77ea686d769dcd007c0101b4cdd0934402fa47dac22f8ecac28fc05c2f6763a6781655ed5e7d84c41157255a4c
+
+Msg = a16a0d6fd57240fe88c7c36b9f7f9040cfcaa9afc4beeb8300818c5f90cce73b819a12c31d42af33146399cdfa4ed4954d068dbb0f1f342269dd29f1fe357e7224304b67b0f924b794780fe7e6aa9dfa3380252fe7177b43e7b1789718949b9ec1b943c83ed4399491482f0f59d2cb8050ab6f8b5854d76c50651428cd29c40a
+d = 0182d1e937b037bf7f84144f7d4c94c935269c9aae7d500aa459a7a0ec113b232dcf282908eee4c84b8106cd38cdc41db3f89e1
+Qx = 0bd4f1ee6a967123d70d488dbf0fb43aa5e93dee5794b4492277fe559776f740754850477e275cee9f1c375403a4933dc986920
+Qy = 191a544b98ba954cc6e060ba26a52fecbd1f0dc7c15381004cccb799a9f7960a3cedd02d36fcaeb0ceb844bb4683998d776dc5b
+k = 07904af733742716366f8ba07086f924697ac8a01bb4895bdb5715081ee89eaeafbff4cec44eb0ce14e774dba71bb9b091d2594
+R = 0723b2068957c4f2ac1df69378fc013797a3b071de30b514c3e610002dc8bfced32bd2f9e8f692b653e736696cf818b0ecc1e10
+S = 058455b8f9abd5fcc28a4ef839ac0245c3feda1fdcbc3c171b6928c6abc931e8b0ec34382d63e414657e9319d2965fdc9eb74cc
+
+Msg = d02ff569828fd1add21f6bd1c50cbdcd09222e458ee79fd5dfdba3cbb84e9d926fcf196cccedece77d5aa17f8c8cbf3a9facf0f02c71d5c1c8aeda9d75f6fd7b6f2c5c70dff992ef6e02c438fb3c66da5a503b3c39acbe2a069da457595b542190d818015d462670b0807c401e36b1bfe05baff3a8ccf8d1f5f8de7840e87993
+d = 07ed09428f460724c8a5225a31151e031d9949493fff5703369c401762345d002c4ce424294baab22d9e71edc4f854510cf0e6a
+Qx = 07fcd003a8cde5503f5582a42738738ac7efc6cdb3813a00c072fc114006be9881c0a881ca35988dcfb8088f3d07a03943cf230
+Qy = 0e7041e666c1bed3b80a691ecff60ad4afe3a544ce58030bbbcc130045e2c611d65f322ec78aff6757cb5df8ad54ee8a09616ea
+k = 02828c8c4bb1722b0f03262de32ca8a605c4046badb20d8eb9f19aecc5c69f199aa48d09b61f285254425cb4bb5e0763dd471bb
+R = 06c99d796c5d4fa21c5cb7cee0b7570edc9d7e9d7c3604f5ca3766b17e44bc71d8a74ac268b8713cc2ea0adc3dc1971c062b4a1
+S = 075962e0ccbda2280e502559f48c8d37704964f67f8cd3b443b89be740976f1bd929c175560fc8cfb282661c0fa792a5b200401
+
+Msg = 57befce973b225cfce7f996fa5a1a43acd160681b88a87b7de04544eb7b6a719718f1ca7f559b6531bfc18fca3836d2be7f7a6e48387b7579a6845796d30e46f0dda9d82680f8c96c5f0989741adef9762c3db763cae2699cb6c112543635e20ed5cfb4b55ca2ccb32d2d13936085a8ff95ed658a54be73f80c912ccfe5f0ca0
+d = 0390f05b9619c27b800e99aeaf61ef7f6249367d5cfaeae3c7b523a8b29153eb8a77132f6c4412545a842d6deb7b7aea7e2bda5
+Qx = 1cbcfc492a2a6bb8a7341df67ef2bcdcd706afabad5e7ed1d63387ad9b0dbc47ed17b82de6de936752632e43c393a93fc5cec0e
+Qy = 111768994b2dfe9677d9dbc45d4b55fbbafdaaa2b2638ba1605c35301fa557d628a87d0a7febcad9f8eb4b51fc9c807652579f6
+k = 00b8d236a9f8edba7b5207b4c7848807b933b214fa25cfc5a0e73f750d30051264bb9f6702837b0f65a451d4ef24f047ec4e9dd
+R = 076bd4755427fda22a0f177624477c59de12a12621aac274b980b5e1ce5dc700591eec13dc5bb48c5c8643de287a07a48a6a7fd
+S = 065a5b0a00548bcd7f59518f122d79c7552ca6097f3867604b462201add5f326807f0e8779f2177f277e5ed25253885ca81220b
+
+Msg = 4277ba40cb462860ca722cb4ee71c61836d2ceba18bc91f3fad7dea478972c6da0ebc02815eaaada1d1a5e93d7ab353855ccfdfc94a5742fe18daee2328871e06c1ab0a9a989d1239df2d2d27f96c415e7ef9a941f06c6790675361173cc229aac7045f49eaca207f59c497619ba32e932b5c1c6576812ee5b146e2cc7de5e62
+d = 007d18652732596add3db31f7a0ce6020d03f3df58131b0c7c633faf619b8210cd309d6c0c4083aef1a1b6d2a756adad0bfe344
+Qx = 15ad0682962b4dfc8901a0dc77d548ed616286733cd9b3ede937cdf4401ab8b3e3516d466ba43b6ab5356c4e72845767d55d27c
+Qy = 17e4de3288ed44b48e7c47b16e2afb513c9763d5bf4cbf9a357c128c94a758e3ff946957df461531def2b8d8411b81f45f0c2dd
+k = 01a896c30fcfdbe583d6b0119f467f47758ee01d4d601eb698f444ed0f76515c2b8053b11ae7abd0eef7aa61145a53d12d560d7
+R = 053b1cd57dfdd8d1802f3e295e450a155c366bdc2bd222d18a4d08369c25e53f1f633958b22d80755ecaf8362d548b28dff1ba8
+S = 069339fc6058762a99576a96e76f75275f848102bcbc281e59fda26c98fc48a3f1061755e80740a233e03287f510f4549bb1874
+
+Msg = 57ff6792ed4b12220d179bc0ea57ff217f322c85bd3676a681d32d7e4a3e0c8e891fd267df17caba5992f68c35ff670b60b4bbdfff82404f6ed996c30539bc395120f97d4d7a652eaee82bd8f9360bf8bb73748b8bbda9f9480eb54f7eaf2609d4259329e8a5ea020521e7dbd3ec56f23c849932cbdf2875f5d5c774a9d6b0c9
+d = 02a91244ea4623b63403dba807d60b914ca3b901a2523244c322f2f11251446d3f15e869d086ebecfa1a39ce304e8b5c8de23e2
+Qx = 0b7ad8f0a52ec21e54e28ef603d76652dbfecc7dd2427cfaaff3d280f0d1f62187d77effcb433b5bd44c3d0c0d26c38d3f5930e
+Qy = 080641bb0163130be4444f79c500ceb8d6a9b2cac42d21d31b2fb29da075bd41c6613f278944adfe92d3c99d494be9d4714e9b6
+k = 070125c89a1262a88f22e874c55ed149de6d961d6abaab2d13db9174e3cecb8f497529957058a0afe5361ddf9d3a5a3b923c7ef
+R = 01a28cfad13969c6449e5a0f879e01ef7dc1cdcd0bc77d20f3989c588a9cad12a4b52743c12f4f6e2154ad963bf234ec96263f5
+S = 066d7f0b364a640c6c620e3d030448d155cffc9ffd46a6adfa1c13e1b01892463a4724465aba3eb07009fa604f3af18109cb72b
+
+Msg = f85113eda64478f460b60f8084220134933de049200a5f37884da7901471542e26690a5fabc3cbf9e679ade71b6e54d869bc136c3d34cc4a9efcafb777abf046b5ae5429136112a9a36a475121eb1f33f1f43481286fc1ada98a41064a1fa38c89e99a93065bb2a119348a9e452497fd5a0d2b83a66b09da9f47a0583732adf4
+d = 0068c56c6b5d50d1d4e13d3837d8c5e8ba2f825e121b63e97603fdfe78bb6899600ff0dc87b6b3b6868ad0d2f62b7b7a31603ff
+Qx = 0d9a4f5992308013573f97864c23b98d276975d80cd6455e9f0d8a62d6674f3aee3d27dec15903da4e9d5908cebeb765ee02c80
+Qy = 01f61189caacb05dfb982bcccd603a769d0e1be8f9223288b5426e7f88854356fe825f11a88918085692f33b0f4c61ab09a861f
+k = 02ea7f0d81fbe3d4c865ff5315d1cc38f9e9a8653fc91dbdf445b62fe09b30ccddf508783ad87c8a48a6ccd5c9e817fe2977f90
+R = 02d7847479c16c4cba834ce5962724f185be06cc04a9a8d710cc72e6063a7b64fbf2694f5b62de65d3d347d34c0dbfd5a4d93b7
+S = 069e32bb19d20e873d0e62b306db4d5663576e4b2fe75e8ec79b7a63f38c8f1007a817ce30612e8578d48c63b04b1d34904010f
+
+Msg = 42811e9ee6dc509572e1cddbe5baf00afeb0c5c13e3755b922eee9e210001676082bc9edc3d78db2b5bebea7a2c0cd2b369226c2b8f83b28f33fb513407ab9d287d14b112d6c3be2493805ace5cf6fd366d03cfb28f4ce3f0f060880db64d6962e997463ba7c05b6fcd1e66babe4b94afc5c2d38c7050c69571d27b66ef0090b
+d = 03c88084f8b78446db431bd6e240a0c050813d2a763675b0ea869cbe183df697146cf29c03479af3d34587a95cd257027fbeed8
+Qx = 15a09436de00d8d129e297ea60e04b704c0a8183d64a77d1c527189e25e21d6bb62be8ef5eb2dbd833e5f9c7d5c3e69c9c01882
+Qy = 001c32ba376d2e9de28fca644b0d567ce1f4ef0aaddb2adec6213d03bc8cc99f9140005bed3cb6c3c0f5533275734aaec47404c
+k = 0132f4763959863a32919eb591799ffb8613797bd0b617c73654ec9eb32e2fb86631b66e28e1b4cc4aeba65ba8c75aa1cfacd73
+R = 05fe0ccbd430d9459e0093cfe2c1d1d3edff8c1ae7111299d2e04f414c46ed2cc88ce9cc9e23e187e87ef551de993f52214d609
+S = 0557acfe6347baafe031dc16032c45559693e2793d9b6d372670b09757c6f4a3e5ae5e55264137d1859c8d9f8f03c25de409bf9
+
+Msg = b38f76ede7441ae0887e689d556f43155b38dab7cde487ce9ef9a46f2957c830d4d28006873fe2368197a6931f6fcaad755102686a457a7edccc8d344e2d2a9162e3d71d41c09a022539ae6d404955a6ad748231aee1f974d4f159940532fb3b1fa0254bfc5805d2fc68696856fadea386c542d3cefd1be3af04ca595e54be25
+d = 051af7b63bf3297ae20517faaa1552f4fde65819dbbff6a52721611e5b7dc1242ed6e69768cdc37ea8cdfd1a5971f06b84b5803
+Qx = 09cd1280a2a79b182ddbd1712dbfd12cee3345a89636d7673a5fc3e1e51400603176e27d538e90005625aacf5cadcc8a8c25532
+Qy = 08b5aabedce498476b4c65ab3cdc81f819c2db670a7236c0357a86f9087b83e7568cc6e5139fb92f81975756d7dc4f48be87df2
+k = 00bba308a3eee9e3ab6d2482bb728bf44cde9eedde15af7300c57c2c1e6fed2ee4e404aeee3923e7871a2ff4ba6df64f9d01a87
+R = 07a9e69664b7b81edc5d47c014696d194b2ca4705b2e79af692b285ec476169d041dd9eef20f7d496fc49b8597574d2602757ca
+S = 01521d7cf6aeaf1c8dd54a7776cfac02967983083770346d9768a2629d606be90d58ea82377413a0fcc3e4e66f05a0d05d933ef
+
+Msg = 356dc86cef7979148e995fc5abe2b14a7d5e4e42c9b3509b4363bb80c581a66f4e7e4aa53a4bfd37f9a7eccf75fdd726f348f6a3f779e6599f61bd1d668517f40453b39bcf35db0852a6a6218198f52b7ceda2ec55fca5abe8e5d93af9a42b9ae4de9530c5870211bacc27c39aa094013db703de2fd3121f08d7e97dbd4e8946
+d = 03d65bdec48972d03811b78150a06956eb22d337dbec5416bbd8185a6322cd8c0ff8000210dbd1326422289071cab65175f5d10
+Qx = 00c9c1bb0a80c4b4863d78003e21ee60fc553ff72968c165f6eb6940250a6cb7d545c6aed3760e42370df79b0d37c2d1433c486
+Qy = 01a9d994828ac09a86c18b9758b3f6b91a5775931a7a6e4d8b052204c972b993a3b420eb8ff7e91df77253a9f5847c5968b5636
+k = 0156d12708324cd30037753c78225d183723d3f15930f23bae854f121094bfffb5d7dece1fca93bbe7457a2237760aef3db8e3f
+R = 071466e80e2a7cd8e6cb6dfde259a08619f880a71899c58bd4cd33c29f7b321d269533720101f2ef70f5b8e8f05c9cbe1ebc303
+S = 077330e08712ad709f855d92355cfb7d565efd806c6a853712916f7c943bfc79e496366deba79ef7491abad23086db341f339e5
+
+Msg = 06fd39a50bf25e89f1071ff81fec5d1e35b6dd68990414ee403dfdebb792627b6a4ae3d2236c159e4441ff90b61ec87b1592c538515f0486b19e58583394a05e6411e69b4285d6d6589982ac0eeb2c912c4948789cad741183663fc070943389d4e9a1150b8f6088fc50605915e9e24b2d98a1f539024770e4820e14ae42ea8e
+d = 01f1a8b5f35dbbf82c102df550c72216a243f986f0325920f6186a16d1da74228cc02be6024c7411160c183c923c743354f9438
+Qx = 157ae8d90fe2416f70a7ce0669acdc0b5064ba650cb5416e59e6672e45b591774ebb2f793c3a58e953da1ac08272d0b949e7b50
+Qy = 06d49b9784f8423812967b857e25dc3af1312a6ff29579f6acb6e155b6848ffac6fbce51bd2d41a22ef955f690e2487a4bbff00
+k = 04cc45e00847818397c6abb3d176cb8bd77814abfc253e3b0d799dff2c3e09a5195ed5e6232873f2783c8e670b52a839e06bc30
+R = 067b418a5395216b83ab00d5568eeb62ae0693af2b0e4d052c6feb70562dcc06ef852002687099dda114477871b924775e8460a
+S = 061d1e4d713689b2036272ad41571759b52a78e0f8a84d1f3a277aaa33ad558f0b71f3c5a99d403e49df1afab66059db20f9f32
+
+Msg = 6daaa41150ea252a3e966a338377307d909b95080e006f13027f2be5059d9208930c5a329994c0b794ef50eb059bc6c215f68cf42260bd410f9bd86d2ad5ab7179c7c92de4a93a5f6aa17de5aefea815e7c0b78a8cc53c21dc4dee037b29c9df4e12343109283ffd5d8a3b81fba1b5e95506c7e01ac056c86dd0ee23bc21af0a
+d = 031dc621200cd174193d95e9092ffb86189c52cdbb9ed937593f2cde7c4a0264b9100e1b8407336c8dfb5520d28a18dc4e39a89
+Qx = 0904bb904d50bff09bae5dd21f425c808b41001ac917b022f7e1cda6e46504781a69baab4a6f0f100c4fff9ced26f871159cd30
+Qy = 15cc300b0efbac707635c72bf855de4290f1b8b70c16f9bd0cb771ed5c760ada04d0ff648f118d64e0aff6a6de16def15cf7437
+k = 07e32b1fc1cebeec3d84f56a67c8ea2b78723e7010a725ca4745e849e573e8e4a4ce11d1af4ee508b80fb5336de3cb53161bf44
+R = 071cd81dfbacbb67be5903cbcbe402c0420adfa9d14148bea600b178fd06278572d34eb46d857085a2a4f48cd4ee9109d607dae
+S = 0347b1029e67a6ea2a45af1f7410dc951db813eabfd3c7f3e2c294b81e1c54fa8c98569efc580b68007bfa316424ac6eb353ac2
+
+Msg = 6378dd1c12c5197b57d47dc46a67949bdd1e0809004e94d49b0234126a08ad5bf8723ebfd132145813136d8b7dd096f56c34248f09a65c34f60c2f80f9a51b3795f3d2518b11aaeaf6dd45a323794080b78f85d629e5fa719b6ab0b14c78cd908befeaef0dbfaa08cec9318bbcb376d48b11b68735c9554a45293db5e9239ae1
+d = 016e6750245a88340b0f0665b890459f8038e9b1366f2fc1326245a88d4c523ec94429f21869ce3dbf75126e58f77241c99efaa
+Qx = 10184fd47e8e1e4d534ca1cf67f15bc8a80921b07e251c22eb88f25395e08d7a9283774aed204fb5c14aa13c63a94ee691b4ff4
+Qy = 1252ad972bb8c0b286c222f42f7d42ca6561bac5e517921bda53e51043f13e711da8a813bb6880678e4d6a16820bab819d62e59
+k = 07f18539d00152f5b9a75d4f114812b87024e8a8f9c9a8d12139d0a74d87986f4305bde60375918ff2dfdb88b6deda640e17364
+R = 0735a15e7bd1f69f4e90739d42ae239a8e9238ad28b63ce291b57cb5b99922fbd5dbb7f74fcc23117243efbd036eded6ee0f28b
+S = 07bb3dc77cdd4138a02e2d5fd4f6ff8516b4c95b8255c629132ea8705c399fc60f8fb660ed3aae52db283aabc3626a5559dfe85
+
+Msg = b898d0f9bd80e083fa541f457d14d853bba55b120424a95e1d9511c8833f48444329e0349d68204c4b4581ef1c4dee23ed0a4445727a72e1e6cde422f7c10ae132a3fe681f9d741fda263e73f7cdf10759467c9d76164086abf6780ad474772771eee22d195339bb8f6235e0d992bbe282b13ce4fe01417f507a2c4fa155e108
+d = 0788fabdafeebb72f6385301e30024b56639e629a400f9c50d402cfc9b5817844f06a451fbda29c7ece41dc9ffcfc625fe0ff0a
+Qx = 09b2c36d221d18189e1617cb2f2ddcd64cdf8a42ba6acc55f04e9722b11588f7fa861a3940820d9dabbab631d7fd4106c60f37e
+Qy = 0da099cdb10dfe2d7c0a16ed332b459e7be31f44b0b2d595dc948f0b073ac4e439f24f215fba5ed50aef3702731d6561eee1986
+k = 00581369aca680beb705f52b6bef075de83ad29034c3d6b2949b551a0bbd100897a079b49d41d5030e1a6950fdb14d70dbbdb41
+R = 04f62415c99c8e6750f9c41c31cf050eb58f61f62eb0b0023d61dfc30e7879d4f5a87e88faf55522631a29fb69d16e15c354323
+S = 06df238f34b5ae664860b43ea11defe3120591cfa371367096006c03e83d372bfb70da6f789665136b7dd1c59894a2fc5038c4b
+
+[K-409,SHA-256]
+
+Msg = dbe04561ea8579672a2b3afa94426a3cbc274b55263989d41a778bcb082da797d84d930ca847a481789524940701cd5f1d11b460bdac0bffb0b3a3abe1ab689c519700de85a0a571494ba0cfc3c865450eba7a9e916b7fa9df55e8a1c246c992e6a0b44b78274e008472bed8d8411633e6520e1a906c5d0c8aafd572fe6f1f64
+d = 01b8dfd64563dc219d6eeb53f2e3ad1d771140d0960b211dc1f757af5e297dc7548d6133ddb574711d466688f80dbd65a7bbcdc
+Qx = 1ec530638ea0663cd3a9b237dd66402adf50d3094391f2343d7d6c52c1d14145c245464a3b771e4b1894462fbfaf440e53eef7e
+Qy = 18349e244b24c8353811c29a60d8e02caf195a424aeafdfd0361846d5ce5eb83da1901700f00fcb85a0c2543b49a8a3ccbac157
+k = 026a26cd09c9329cd45ceb4c798846dd81af67759794f5cadab84de19a835f8a0ae49b12853b1e92822477a73891f85acce4216
+R = 04d83a5f9dad246717135bec6e386ec6b73be9ea6d1a17334ea2003a723d510914167d136254d6cb64b16ef7eec5044b8f2ba28
+S = 03e81601d0c66b507a491c530075edc5b09d770633a4c2355b3b1c7df9b200ebc7dcb706be1696aab70d4c6e1c4a7e532284670
+
+Msg = 48a8300820fea2ad83c83f7d6b24192715329c3f159d56644e11ed25efcbd3d31600a813b909812987b97d1087e74a63b4494cc031c63492b6615e9d6e5b36f62cb2ef88b9f736595800de465789f43811165a5fc093ee6d776008739de8de2a84e878748641be8bd52e5b891c4145f52bbd46644852a43108e93d86352b2a3c
+d = 0422131829608ff730c24ddf7e8b4a2600eaa9681eaf45432daa7d41fe2fb488fd0199d431a1ed823801ce21f4f01a4dd4248ca
+Qx = 06ff24eb0ab812303bdc9a23719caa789eb75775e686b9511bf6e07d60447d1601a48ae7f3041cef5aaf3ed2adb6feb422fbc54
+Qy = 09a351fdc9422a81ebef5407d0d74b52a348caf3cf6e1c6c2af722c408941de154619a1d54bc23a9dfc0c4964f3936d62daa6a4
+k = 0313ec63c34ed325d770664aed3bfd1a16eb636516eb686e806b0acf6f0d117998b30fd52068a36f03d0db3ec13e6989c6f196a
+R = 0088167f96d807bdd61e65fadaf0c56b623db42b831909d12641e4d00e7bca6077b36cfa759fcbbf087c31f294f20a09e0bdc96
+S = 01cbd06232b4c73cdd13208dd254ebf9351745ee6196e3a94b9213e931f141e4cc71f3d318a67e7b8060e11e88783fca0be41cb
+
+Msg = 276e3a986ce33256014aaa3e55cc1f4c75fe831746b342eadb017676b0cba7c353b3a2b554522c12e6aeaf1364cd2eb765a404b3d0aa61258194a30219d76d2bfa98ad20e7e91756cf65e50d7914157f283f2ba3930c0ad3a97532cc747b1cb9c806fff497f0322025a3d02ff407fc7b5808585b91d95523c9d5864efdf7d983
+d = 0095ae8e4c7e55eb5da01acc05ecfe72a4dcd8ec152f1c8dc165014f70eb4e4a7861aeb2b96c418b2d4db58659e76184e013a49
+Qx = 0a3987d7262dc30e8ec11458ff7091ca993bc61f142ee535d544a2c88a47f9601107619617a5e65cdd6d5e1a034aaa223044342
+Qy = 1fc8af29d5134ca9baf92041b6d6aefabccaca4013c55c1581ac05db6141290235ea09650a289907785d282cef1b9efb381ae66
+k = 066015a77c99015ed6983bb379772bd90e03b9c010e695853ebf8e461a20fc12b20bdda47eef856f162dfbd9fd4fc1ec49105d3
+R = 067c49b96e5bfb6a6d625346c3ecff13b8c8b7e59c764b73b256ac970aa4056460000e599a8195f2d235a75cee8e5634acfa7ed
+S = 03ce25ef1af0784645f0579da381542f5b8aef377e5b79193314f84853e2a07a4f1aaa4d8210f3a3c249a879cfa3ea8af43a929
+
+Msg = 6a4fc1827c3a7256faa8ec6a0f3d23559d6949f8cc20e7f76111dc4ebd59213951cbf0eadacaeb8862d6baa0cb298645e4314b1c303bd0d5e9893304d4b7fbd36ab05fb6a5edc3fef763e3a4124d61539eb616b359c5cb55b5e2bec50c91dd95fc39ddf521aa854216eb5a707819fa6f067b316a17a3b146e7cc2dd517f7d63f
+d = 006f2075bd730f34df111ebda919167b1d3358ada32cd6747cb3353bcfb814a77ac70cd51b31a0e538539453bf9eaf9d8b384c9
+Qx = 0bbc153deaec0bcc36c03d24afd20dacd9e78d104d94c279278d04b597ccccae43cd3e64c9e1e58fb5408f376dd7827ede9dc3a
+Qy = 15ae0d803acf12d9d3fd41f74357b1c93cec0480f2e586d0e18f15e569d27d3d106e192ee0c1c570351eff1f463dc07d3bea933
+k = 0314330098250e38145d11a48f5043190c6b44f8572ae57cf83b1f3c4c03ce38b90ed5e157464c2613c82943d78c938fcde89d7
+R = 0160b20c370ef4b9cca3f7dd3c23f70efe6bd80751ca021731bdfb0f45ae07e5f2144c77795aafdb0c3a92ebbef75fb2d334dee
+S = 045188dd2402ad36ae4278a9910648ed5e71d64737651c133aa89850e3bef2207d58ba4169e471a4737962f5fafd50a37a28e1b
+
+Msg = 4b088199bd8c94775d8ee508377d672dbf50f6d2c7370e99821ec8f9387492fb2eebdbea473ea18465565f79e2af418555f10c4a527e05a9e20c9c00b807dc8b350cd4ccc2d87e91f66addf02ce4f43597aa258ac6fbe9365cc2c8e8bbe5c884abc929710e8423cd6722a8f473bb55804159a92a3d8b6661a536b4fb9293bb0a
+d = 03887d284e9ad17d38bc6da9d83c192a434c509340a7f233cebb032b09ab7c4c6e8730b4a80844898616c9abcd16b753c6bb4c5
+Qx = 12a6d5c5690ebf14ecfa54ac97b73e88e16e757c34c6bbfdc9a3a119f298860d330af295756dec41eedeadc5257b202451faa06
+Qy = 19f40ff28bb72af659d5319286fe21f01819952d471ce2433ade745042a47c2dae798199c364ceb99029c2dd5cf57ef5daa2b00
+k = 035945b45221300f83c5fafbaf0645a7386e209d025b3e1dc367819728f630663fb732b251a019e08dde0f64dd3f60a10065c50
+R = 00c323c86e8cc548123d1337936d4be948bd4bce4631a2194c2bf04e1fd714df2c90e3681e41a21d58d9567a5df9fc478dca8e8
+S = 0493d3f4d22cf8517c301f15bde52cef17c05fed2482f3ef15cdbe32c5f0975e054d45b13faf906896201942f29e5693bfbb229
+
+Msg = 848a13465ddcfb2dc14f7bc0db0756832c22dde1e31e4d8b3ae0dd1aafbdf15e954889e95d3bdfd6e5ebb6171fad62592c23277a89e8ba53978c9b1afedfef7e1c3f6d9f31077530460b47834b30bbd84a4da601be988738aa815d3d7e72043243a5288751ee08b4815a017fb5d9bd55833698a0d526b1ed79da35ef0fac93da
+d = 02ea5430610864257c9dc393c3addcd0d8d5bc8aab1067643b08857210464428aa85cf1ae6c743fd2682255d4c8eaa46ca21e73
+Qx = 1e502d3f47823ac7207861855fe6f6aad1fa4f2149bff2643b079da23fb270599f744669b3c8ceb4cb0989aabd43d26d93c8146
+Qy = 0cdcfc138451bb59f34dc82b8128088b5ae0cb8a77dce1895d5ffdfc8b4be24a206b9856954508b82b80d0163b276683489074a
+k = 0426b90275d720d19c6ef5c8c74c568a636257740530e3ad10de0d518c4eaad8bc58cf4506cf5cdf7f2b03edd1caadb28fa3787
+R = 0123ad87c094c4ccfe4346dadad54a6b1ee1bffaa1b7b9094fe2e6ae785a2b77ce3f5e568e43e8b7fa997206262645f56078657
+S = 00d56cd5cc64736ff7ea0d9840916b1e1c94e11611f93b1b11c2ee98c79d92a8af1a560c9938dc4bdd0b84252e259ae5669d1c3
+
+Msg = d1850545c04ea65528849973c220205c35eae98826d169348970d1420b4d872ce233af1daa9e62f6a562544ae3a0633a954a493e9766dd5d87e47486559fdf86229a7c9e1726de21895abdcf2422d438f4ad98d88b45c56742694ad5e11894253270997c049f0f419842482f21c792fbe5613e2defecd485585f1835b6f4c578
+d = 062c757c92eaef41f5d81169ec4968145b5aa2bc1d2a3a5fd000634777748ecb93677b3da12e3be33272a8f0a52300f4a5a37c4
+Qx = 139660fb8bbba59e8f4e95e5ee5b97227220f0e1b293901fedcc6dab86e7c5a9d20c1a097ee2e926a934cce679fb8dcd8d2ed6c
+Qy = 08ac510ddf735184e8fa9693da264194fb78da5d1cdc0bf5faadb33950ca191fe233eb8dac8adcbfe15b4f7c09d5ddeef6bcd1a
+k = 026868bf1764993d650aaebf117521cd146ea20067cc14a5843f726a3d68e41c3fba82a83d406b2275b3459748b3bd1a8d32f1a
+R = 05b17d13ae4d9535d062a2653bae4d15b9b859a87c33e175adc3ef04781bced888f3e93e9804b2251a40b9344c0f8c6bd5be0ba
+S = 01ec3322c5beba4423b13a0528c71739a6b39f7b0e0e58a8274a8386167cadef51e5560a3e9d97447e3d3c06288459fe6569345
+
+Msg = 421c9784d6fd507c82904e1054edf9bdd1efb58a0b211340086069ad38b7b0dd15c2345fa8767ef71254ed1bd5c35f742b1d3f4765ff9007a5477ba9e5d3d5a5cb5fab4efc1cad73701d4776c6c4343f42b5d94a9eb78ae428dfe5fbdd8e6ece09d5b75cf4346cf27db856352225ab04e6ea56661554fbc39916accebecb3935
+d = 048a313c0c11489939fc0cffc6ccb9f179093c4e13141b92dbbaac441b7ae878c9d412066e95615174a24692555cbbe904a14cf
+Qx = 0677c2d364fa86b8b0c79af754e675ea3e806d5583e62087e01590b824d2730e31326591167f02bdd29f8178787c4e1ba9d2496
+Qy = 0e7f78c423baeebf6defe9feb8ada8874cecab083ca2e71d9d8a3fbe846eda69262a1f5b4a3baccaaa4f2cc87220edb1fa6b6bf
+k = 012b8df87dd935775b80c62ed6c76974fa5772939a9e7372cb74e033fbae4f78d75b8bfbb82240cf91009b5bef4d63ded04cbc9
+R = 000590a9e8de60b5cb181a1c11c2f6115c66b05e71e0c558ae203ee18e54de68016f4c7ed2f01cb0cbaf1bdc45218c0fe2b1552
+S = 0521844eee9168a501e235de5fd19c84f052445fb0e68bba687ace45d8630070ddd3b73034d1d65788a51acf91273fd187a24ed
+
+Msg = 7910bab15b6429947655e33a67f41b76f1d7b71534f8904d6a0472c2faded038565272d0b5f51aa915e0d624e9ff48d50ebfa2f09324864f26c29ab73eb39b436c5c459c7cff4d2b62992e3489cb4ddfc05d7366b161a463aa1b782641d93507de43c8cd0a0a0a9d1c644f4554e3edaf7fd794248110ca9387e73ae5d00d299e
+d = 046e2adfe5d3549e1e6fa1fe69a7cbb4ac9b111c8903d544268f8318b0b47d4b78fe3e56eb5e639ad5382e7cd5bd4b2c3e70ef6
+Qx = 12902439be50c97aae7b40328984934d6c843415f76f3821c8e8323aba96ee41359e2ce5ad3179063ea5e2c7deeda4d728d5852
+Qy = 1eb59fe96b269cc973b1fe1f3720aa9aa6ec4cf303c5cccbaaebe6ef7c9f5356ec5e76b26b09479d9831d9f5aa41ae1d61f4c47
+k = 031893aef1baee0e21b50cff7002435b058d73dc4d8301ffdcf1e0c315d18c2b16f282e5b294dc88369b25e2a1a19abffb578ab
+R = 039281ef10b9a2664b755a2db67b3c410276a424edf7681a5c97244eaac5826368a8095f1b9b76f8e490e2783694d5bcf3565ea
+S = 039edd50721dd35d1704167e8cb609f309b9ed73d3c1eece181f9582aabc647c5ec8bd258e5802fb0647372e4c3929cf59ae2d5
+
+Msg = e6fc96e060b956c25d50ad25443f3c30a12d199a47451a49ce88307201dfb15ed816982e8888a28daa92eaf3c5584ca6ab2ca9e14577f84396de2e0ac214b24a2279f5e7b344fb7387e9afc8f0a2b77a4d024a20ce6183499b17096947444bbb753d9b39e5c694239d28f9c454bb05468d17ab564ee6cea3741747ccb7f108af
+d = 0480103fd6180a431c837643566706e2b9597de0a1346a224d176a5b2c54aa4d064418ed654a5d39f4773fb509f86473ebb373f
+Qx = 1d39e2772ff3d26c5936ab347bd5a2940ece42b1964f030c59ab453acd7f44716ba9d88f0828de1a4e730ab27fe1859915818c6
+Qy = 140b1b66b0a87de29ba2cfa799d944b3b898fe7ac43de68b01fb41464506e2f014e0d11bbc0c24996428c93bc1a5ecee5956bb2
+k = 06e9bd0290548d35168f7db7fc292bc161a7710b78ac49ec6a42c9423afea1310597e5978b22b4dfa192489323b2317e4714d37
+R = 055dbf88b6221dff098345226d59d396b6773611ca6e747d26d5d758760d830693df0f5c602859f9caffd0dc3790dfa08c527c2
+S = 03e679447b622c4b06871f2337f5a24150e76efcef9698c6fd463867508e9d7b803667c32989a881c98a90998944c070aa58b17
+
+Msg = c8a8a0d41f35537e6fd523ee099eb45e1ad6ab54bed4d3e315e20227db03292e39dc1a91bab439c0d20e36e7fea6ef08983f390a6b5551ac3b4f1895220b2867fab95552cef9bd8702962839bd9b2c72772640e7d3be3c5889d226acbefdcb448432bc503e5a5fe7ae9ae7696c720a799f9882c64ae0385f656074dd8a6821f5
+d = 013c489e8311c6bef02c8f58903b2ba2a98a27cb935d75a30d320af9a14fa3cbc6adcce09235a9eaf333dd05f4b2f1694985dc4
+Qx = 046a1c0e7753cb499d19b2805df770ba54f1c6e03611c302c73c72902867c51c1cf9ed154b8f30f72002421029de7ba2d8fad22
+Qy = 02aef9c34c7c8216a805a58dd88185f40493086213cb4c85e4d226bb5e892aa37be353d9123e9900f8b0790a43d55a19d78c48a
+k = 0491dcc881731112ad5e9e1df459c27381a7bf8270f97743466e178bf5ca903971b362b73fdbef8a75d4292e63e225396c7b32f
+R = 048425b76147427b8b1969bba3809dd70f0fda24cfb0e92509a7824f027b61cd38441a691efe213f3c331da8c82f94bbde511d9
+S = 00df36683f22e9e86c88097d75409ea297d391550440e4327f67b7af1b09141a0e7a1db40c4b0bf4d60376a6636dbeeff0b6b91
+
+Msg = 3407cd6d2845197cd7414a30fc3df7184da204222ffd65c4d16a12cadabf603de8043ea14f5e6ddcc22d3572dc06dec1a23cd924e1847ae285ecf01754e2d1247876431eb98e897e47412a2330bb32990f9714122109e94b38f82cfdbbf2eeb4c6f88f5dbf9f0ccb47939df8be321dcd9bfd9bb99cac9f94885fee7d443fbd87
+d = 02419bd2200f8e1d87db848b0379741685e680d9affe693eed49d82931030b6cb05d21a4965f4e1df2045c8513a8f574ca9f2e7
+Qx = 0641a6ac72455ceb142e00d6854acc5f8b86db7bb239a5054c1ed48dffb6d050458ffea8adb68613ad3cf5977ea7330268abaa2
+Qy = 1a954ab7d62796e5aed370285d3bf91ddd34eff3b995d04967db41c2171cb2157d85032c998795ed476c891702d63ff0108f45a
+k = 02e9928f427a86c4491a47b31454ea7d497435af81c07bc96fa61f4507494fbe4ffc1fffa8faadc2a44c7e69c4f976661750f8b
+R = 01e8ff4cb8c58fa48aaf61488cc4118df90e8c06cbd88234cc920e5795597ffdc0ab967fa7461082a49de56f02f84cd9d564316
+S = 06e77ac43fc7af3c126f997fe15011fa87a27479fbd5af48e28ccc2c1bedb6c0695291dd67beeec3f17cbfecefbea46b6325fdd
+
+Msg = ad43f8440071285d01fd79244907803601aff4bc5d14c77483a87cd742144d41c68269d76c9a83c09d2178bbcbdf99f927b378497ffdc907a75a3b0ad019e69758dfffa480871eb6e1e17c8539373de611a557fad120d0bd147f8debe5f09a02e56fb607e9c1253ed592071f042e42fee39775b407225a2b86a950d81bb7d7ef
+d = 0722951879a65bfcb414e11712ee9431eeb32319e0ff28601112f89276ffc2b96eb65c7fd77d023f09914a53e2aae2c84652bad
+Qx = 0a0304caec1b68b34c822a2a031145677fe515dda977f6932ea2a3291c6bb4fe8f297b7d3c632f9b3806a8cd26e32403c27fc7a
+Qy = 0012d4c3231898a4202f3f251802c690353ae9cc28ae5089e259149bce444d31a38927dcb42ed613d4818e235884749057ebd02
+k = 0331611e81d3e6e3a24cc829c1cb9087a8c6f64c286e5f1acfb1ba764eea5ca55be544d3cb95fb98407fb6c8f9eb1b3f7ae7386
+R = 056901f11ec69f91b31f7f41f7856752568b7d34ff3af1a2259fe15ae0b01391eeaffb629976525fce5d182663b7b23a8001bb3
+S = 04e89c3155afda2e64c749536392554cc299b70020362e6701e3a649f0a63ae5a5da4efed5c73b5e8098c0cf47d6f4c45c6fab9
+
+Msg = d61a3765229dcd0b4fa6c57280f851ec2bd54d3ee2436935cd6d94e0120d0844adda163995fbc4cd9d7275da859ad8ebf30af9efbdcfc31c7c9ef42bce9011d37cf9d15fb018e117bbc102f7d05750e5072f73d02c2f45509a55627a78cbd9082cbf36807759d1fe2ecbb92ab30cf28434941712d38bdd100955d611987b5968
+d = 03f5b5a772d24bd5454bf26759dbd433fcc7bae4f5c593664c4d75da0cdf9430d7d9162bce3d7f6e13a344259da5a7d6a1635bb
+Qx = 1ca1441b1f6e13138880196e69743206ce09c439a507a11c0fed069d4ed23676b27a3a337c976c276809ae725229c9001708742
+Qy = 13c47b14e3069af070869c12f0f39e35a6f334d98210d33c9da01ac80057911f5a392fb5c8cafeea01c1953e97d47e744160243
+k = 01484461d02c0337e8113e51aa7d46330f57d423b79b580a544d372524a853db9dac0c0d16f733b273bf888271135a5162e70f2
+R = 0256d7ab133904a792987f8cea69e8e3cc674cd3c577f40ef6f12b31f52ac6366a2a3ea2b2272c7bab8be00ca0d17989b6801a5
+S = 020d82cb9b3b1f25d993fc18b7303db4cfab91c03a97b249176f9bb2aa5ae7f589c74060d25058c7acb6de1e888ff44481185b1
+
+Msg = 1f3c23636414ced48fab6763eed5b22537968e6bf08c178b3d31fb1f6ea773c6979759701d94bc1bee7c354272811edec58eff50c93331b22723d460e56dbee90466b894354777b23b13a37d15a84c762caca70c01518bf34d0c2f072145d274b3b6c932b48bd815fe81161d8507ffbc2f783bd212c29b2887af6d2ffa9d2b4d
+d = 046bb4a141c9099d531dd23ac440eff1f5b10f7cf34920b6b702311d490d25344c665ed5211d401def24986c8094165d10f8934
+Qx = 13db47ac0e33af0cc7d74f6ce647fd80cdc1849b15c349bf501c95893be5a440f85b9b029713339fb888d7a93632ea4e0bd8136
+Qy = 1f26f7009cede02e054d6499c9280794184e212e3e1091032fe0e3c189de26d04aa8a5909569017cf06ac2a20acf579ca81f3fd
+k = 046e55a908f13441bab63e5327ac346781399d5a9035a72aa21df708b814b67e420b455e1410014cb53e6ab00f526ceb396bcf6
+R = 06db7a7b03d6a85069a943fcc332cb8c54ac978810374b12eaed4a5fa5342c8eabaec238bfc6107fd03d75dc2c6d258c218a186
+S = 010a4115161765dd0c22a0915a0d8cc01905de91d3f08c6d2d85a6a92e1dc00904f3be67fef000ce19f57157deb9afba7582b59
+
+[K-409,SHA-384]
+
+Msg = ec69f2937ec793aaa3486d59d0c960ee50f640a9ce98a3becffc12d6a6c1c6c2f255d37d29f9b4d068373a96beadac98fd5203a9f229bfc70bcd449640165ae5128e3f8d057769e28356e73e35d8e9af7876f608390090892c67391ddfcc1c332aa61efbf72d54bc615998b3be8ab0a9d372784bea48c9fab244482c75cb2de3
+d = 06f2c6e9ea8109223d9a349fce14927618fc4fa95e05ecf9aba1546619eaeaca7b5815cc07e97ae8cd1e9973ac603f84d838393
+Qx = 1f5a9824584cbb0d5ed57f677caf62df77933ce19495d2df86855fb16456a50f157d18f35ff79b8a841a44ee821b36ea93b4f40
+Qy = 1a88299000c07a9ad0e57c22fa8f15218cd90ea1de5b8c56d69506ad0fd12b513ffbd224cb6ad590b79c7677a8eda47a8bdc484
+k = 042325aded3f71fc3ff0c84106f80a10af08d76d5e710a35d462e880e015a36d063599573ce2044537b9f62b51ed4fd2ed8b860
+R = 0667c74ee2d632aed13cad47e0b46a5176940652d7da613e4965876e7e22d89994bdeadd6b5d9361c516fd51a4fb6b60b537e9c
+S = 026a01220a1166a4d0172428753e98caf0aaac5b0a09c5a3f11b2645d243991d141f59d6cc502ac44b70e7c48d6b0d7b6ec4869
+
+Msg = 70e11efc78d7f079ae41ac3c31c96d3220f4abfe23814a2a4a78d9b1a25e838c3408bd416062e4b0a5cdadf0c6e16a11e00f59711b417751f5e4b43ecad99efbdb2a81c91a034e89edc94eb552c3eba62808563cdf64453a1db07daff8742aea4a9fa738e1322da316b26dbca2954b2bc0de6da7518d28e6677dec6ba8af4285
+d = 004212b7fd913d794fc6bb33e0276e349c052c969ecbf6afc89b28f75a599a9242acf74dec9f374361ba296ba42a38407f9b7d6
+Qx = 19220ebacedc60762877881262c0c3dc0c8a709fe2ea16cdaad3b680d7cc8aae8617f0acc9b5c9861ede651481f39927a24ecb2
+Qy = 18afd77bc7fe54266275fcadc0fe8d4c0dba7a1264c79bc31479f4bcd02245cde991791a7b7e65fbfa907457fb6d450c0985ae4
+k = 04c01ff477786304b24cb9c95ed70ba376ed6e4f6b3ab2f99ac575c92d3801e7f43bab072268705d61d3e2fd881f754b9c84235
+R = 00987cf8ef2b382fb25a6a542e688aa96c098f5d16be0c7d46e961b4a4152c372cc0683993843bf5a04f81e6068843582fca48c
+S = 036fba32f80cd2e66bf31baf87616027c5b107f72f11fc766b42e2774e29e10e860577c0d3a27a3b49754e6a189680b7a638408
+
+Msg = d922fa515e3bed60b517a2d37cafe4c041e5ab4b5c8d8d4011bf9fc4013dd8abf7add71fcfde5e71d6abe76bd0f749e960cbed55711c87b5629a2c39cff48ed7d0feaf5cc4765e576a4959521f9a45fcba0dc65ae618826447e02ce6e1cab5ce8d6c96c3211adbb0660de7df7453f3aa726016941d00d8ee536cc106a603d126
+d = 06baeebb5ffc89c94c3e8b37b9b0904e7c4b251d204894655bf3b1235710215c29820b9d401c9ca7df1404d2d62d708aafe208a
+Qx = 0a0b2a185ad7ddcaa0d8d21b643a14948d3552e25875506d64e236a90d274ad1ca678e628acc208bfe6b56c02df9f5a36aa94ec
+Qy = 0fef210c7137237da8ecfc2f069cb9390c132d1c6ce961f2bb3ca925ee727c967f8a46727c8811c94ef66f20836c661a5cd1c59
+k = 02185be104ad16abfe4fb83de5db067d37ca58510b786b109514debef56cceb4dd6ebe53b25127b85faf9c28b56d6586c26d60e
+R = 0404831192b4bd453c0a7e850815ac3fad88c7a2da27d29e83ca6f22213635a366018ac0038b1fb1e4c512cac15b614fb69b3e2
+S = 06f677c361547c91428d0e200dd00777262a138afcd828238d132c56b2c232e2b446cc693fdc4013f05ce7021aea5b5b2f1b34f
+
+Msg = 4f64d0f6bfc542a0d4347576935bd68ca88524ead03b8d2c494061d0658e6c3e14576b5bcea5f2f992f54cfb52b5c7cf1dfc517205e0454510eef1b7054a8cd06ab53ed2468193f98ff0dd62faf076549ab2a270f259276d5729996c120792c6f466a74ab65035bf38ff2c055b43e2a8b8e2449a2375ddbfc18242157bd905f8
+d = 008e5f66ba53e7caad1feda122a80c32c82d2c32a7237b8ee8ead44ea8f2f01d77c7056b9dd60b92d051f060da8532c1fd0e8f4
+Qx = 1a3d020a0c7e3f3fe5b3d9fa6b6148cd0c481b4f9e14dc85aeffff35e62545654fc313f930ca2e33dced28ec28d0fce6ceaeaa2
+Qy = 13c1ac166c3c088e8a4a9d44556e3344e52e8741ed1a8b526a45268086e2fe54c24d398553d509439ad4957454eb68af594e683
+k = 0095caaf063abba5073aa7123b2c0e1666d29bfdfdfb0c484e18931d756ed0845ea15dee1e9abcbbe4576113a8806aab9476b16
+R = 04d6e33001933221e9eaa78da5874f639749c7396dae90f2da4ccfca15b50ee9e50521cd84d78a098e0c383fab0186b3dfe1b3e
+S = 001e17cc7baa3e9ff4d882da970caf7d55b4e0fb7f0cdaaaa8290fe2fc9cc31d51b34b5dcc825bf6799ce22fc95382d46f3f98c
+
+Msg = 7047d478ec5282d55db8c19c97af10951982d908c759ff590f27d57e2664f08d526cbb2bfde39bdbb1aa3dca5a8d3feb50b868be6651f197abccc9d8040b623de367e2ea1d20ecd302afb9e273f4be9f3f64f2c2eb3f92d5e0e375db6549da2a589f0604bc7146562ccefd15995a7c4208f640e7a17afbca69cda4e173380523
+d = 04ecb22b44e809f89b16abb10be062c89b41ee34e110403e42a20ce59a99afdc22f6f6dda56e1d9d1b8ce1d057f390db111def3
+Qx = 0dbb4a6ed11f36eb78417269c1b1e9725eba1666591afaffb5582c8b4d5bee1d73922b0164a05bf21a12052171abbdd31305552
+Qy = 1eb385afe8588ceaac9f39a5cb4455e02bca48f3d2242730e0f9e06ff1db24344379f96356531676cd5af234a120f4b61f7e041
+k = 01cc97a718ebeffed4ca7a9a4389d6b0fafb73ab000463b68b5580267aec203b6231cfb5afbf7ad8192f0947c7f40d9e060ab32
+R = 021a29f56c31227daf0dc5dc919434978943b80f4b18748bb5f7d6702153b966a0a4af6f209ecfa3aae0e4f32a1b7c6ae58a55f
+S = 06921b2e2ab81517a0785c4ac3be3d7d4b4c917d7a1e4313b123ae96056a2a4a66d9e00819d8c1cca5bc0d75e4e05477c1fcbff
+
+Msg = 1a8384b4771a410663e56eb36c5d9ede8d161a8fb0e31d3f74bcb017b9e31232bb2e2f4c65a2d85bcd1cedd93ef08d4bb4af0095731574ab3f2762788a1ba3bf0ee46684da8d9dd384432fee99ed3c69213d790a5d81b351063eaf2bda71ca4868ac36be1b571024a8bf09039b347fa996d5d161078314e24b7d073e05cb3d48
+d = 051f9500c15ae73d6d479b9f3d2caccc2039d8d03820befc2aae3bbaf65d59bd9cb3c4e3aa8bed5b3acb70a5566047ffad80729
+Qx = 0ee8ca7f55225760c515bae053ebbf4ab23567f95c7091fee2acfff079eda297ec6a7e9d526e12e5976431f9d7e52a2318ddcd8
+Qy = 185e2c17705a2555fbb8afbe8e41ced8ace95c83e198be3c7dcdeac8c2c5bdd988800f1194e553bd0348ebe6c29c16f35d50895
+k = 073f96451cab2d3ca9810e265b3461e0fbe7f32fd6702f06891b97969b133eafd68e53b526b5e32b0d06ab61ecd75e1bbb21b7c
+R = 067d55e709f6966cb2082d8021a313850c53305a3bcc926b6f9a122181665328fdc8e05a88de812357be85d22c61c919876fec3
+S = 063d5ee4a63b1fae39f266a9f826754f5bca4d7bd414dedd16858b5c6ac2d4162e28ab57215c6713320d3d6960f6b55e3f1897b
+
+Msg = 43513d6dd8bb0af7a6f5a2b35f99957d335a48d54f2c4019ce9518b35441d4935518976ab1df37110b5b53532cd9e2c66d9f87ae7f683d7efdbe1775a6c15eecee84c6f879999d0706f6779dc158c111fe8d7201983883bc8334f51dec60004eb1087347bfdab20f8f2f260556681e05fdbb8a6139857fd3bb2df5bc1f2dc143
+d = 00cf01dc4462cca764f4f8cbef48c51980737b9b98d1384b8de9f4c733829db7718a9b5eaa46a8475c2144fe4454cb8eeb0a443
+Qx = 0806457fbb7fc577497c937600c5a9c4df2c20cf7dad4510e5ad617fb2849bfe6956c3efeab6b805cb7b63bf5d1c94e5ddb456e
+Qy = 0915071cee2094efdcc155f893da8d83d9a5c234d0f04f738b7af5b8fddaf1d3aa152fc11894a13caee0009bc106a64323e9dda
+k = 024968902b50febf13be11821d0d316f2daaa07737af45ce2e855aea6ed58f226d2279ebe4295c5d7674104bff75b899609561a
+R = 0549f18f1d654f26ca134df4707694e5d9b3693bb34ab5123ce4d9e4c2b2d9756ddad957a4169fc9bcea29944903080f6f5d01b
+S = 021887355c6360bc4ee59f1badb5325763e9428e60b31a7abed06ef03bff0b1265662d604dd2e0140c355c70fce1b56ab143201
+
+Msg = 752300bc5066d0efaf807183a41725e349907b7339d77c79921ead3c685b616b0eb97e708f3880fce0136c510c8cb53b22cb424af6f1c34633600939a0647c02d8f9601f9416f1d24a51657241fb559c25dfba91402cea43bca1a13718b3945b048725f3df560e6717cfc6ebd894e29bff1e0c7763f15b8ea93e67385f059598
+d = 063a9a565497974c6dd459bea0d1196d74f263f333c31b7e8591499960e1cd79e2ef4cc8709f6d54713f873b16e7b0be42f71c8
+Qx = 18872e9d9410dbde671fc050ab88101f01d146a72d62b630b29790b20fc02cb62cd0ebb5b453a46c60ec2d2c66de8715c320578
+Qy = 1b6af51db1c42b743b89be0900d23f7da80b15f2e7a2a965c7bc13800bf58589560af4697f873b6155194badf5a19a653e63da3
+k = 01d3278e6e78386146fc15006258d7a62a1345db3c2e44fb8d3bf8101727bef254a9fbff157072326a85b5ef4e17c5b0212bedd
+R = 07bd5b54d9c6d6f9c87f4a66472be2c4bb7f521ae56c1dd71781d95440b0a151d206ddf627e5ed3f9c7df2fc914a78454e97616
+S = 075e39ff66ab0e0d1b46f9679b95d10b692874d45fd6898c569aac28a53569646bb29f8556e529ef83a15c574ad5e1c82878154
+
+Msg = f620603489944769c02e2f902c2299dd5f32b5fb463c841b7e1fc0249a85d2c31684bd3daacd97de8291c5d39e84d6e59d3dde1b30c181bfe8d31b8d8e080bd191690a67fa00024ac8c1b10981b40d4f88789ecc58fc69b15417fff34834e23453bb9933a43d08afab74d056f366b40ad167b51ee5f008db151a12b467d3eaa2
+d = 041074dc186193d30aac7cc6d269b938ab40b257d095e54ba79967a377a91b8f73671470cd07f0a3d1db7cf0a31ba9070625e43
+Qx = 18fe9848dc599a759d90530480a6f11d052d2ce21a7275769ba02a61658c3b69ecc546aa6599e6699353ee1d65ce533c69fb218
+Qy = 192b9c41bfeb2af4f29dcd1c43d3fe72a070b5d085d070acdb8c02f0dba00c9471df1dcca1006709676bc08b8ddad97310e25bc
+k = 036447681292dc781f7f4ed60126945354ad1df5987266038c5049d698b2ae12965b6fc58f3e944c4751406087859973d8afcd2
+R = 0541c22a6cb984cafddb3269ba3ee56af64cb36d03b7cd1693b112a7df20f0422219f85c6820130ad53ef69fb66f3326bb863a9
+S = 00fa66b163ec3582760b048ba9a0fba9443d7e908b67d749d732ac9b6e89c1fcbc6d3ff4e02a43ee41414b15ead0cb83749e0a9
+
+Msg = 5575f610762b42ce4e98d7bcf45a7a6a0d66ec7f27d6b8b17f1961249d905bc7e58e2ce0806d467f106b16285dce4544c72666d08b5e2276cd0c4e13187cbda8aecf57b1855afedf8fad39ee4fe009f204e60bdbec79b123456ec2d85631d382b8a2f2c7634af3992e4707f7b4215e2c9d3b0aa8fb08267953883a4213669d33
+d = 010820db54ccf0226161aeaee79cfd2797f87702b4ee91adf8543b3c9e79579d0df8a889e366ec1e0718e039b87a37c24d620e9
+Qx = 02eb4e313f158ba7497130e2d64804ac45a7db207c55d41f39979e0303dd2641c81050fb7f24f2fd2485b90f60985cbb15d56be
+Qy = 0a190fb6c81c104164578da6bd4f2b193cd11935e1f87f14e824c2bf8c82c39f0be1a6de3dfc6dd68af8cb14f6a78f38773a7ca
+k = 0118e911f676f004fe581d1855e5795e5f4ddb33fb8d409d557aeea87895b7c23a513ca0010f98b3a63f2c65da5e3b6c37cf5f0
+R = 060c7f7c47c16b294867cee3e65eac8fc828229a5d3adf8e68e14dee620e9d4e7b78c8b902b5042b5f19c94e621c52836c95ba8
+S = 008d036087b23319553faf835b793c73204cdbe2c1c2463e74de8f404e66ff15ce9384d26149e7300ed1a109afd1f915edef912
+
+Msg = 81cf067411dde2d0ab04fe5fa1e28e6975cdcc571588de60a35bd956a535fbbda4affd0803d244f3f7e6902a2c9a7ef2488691b6bef7f8ffb33be09ccae4c5285265e4957f7928ea5cbabd6823297f59a7cfc9939a49f26bde74c4c69e2d38c1efbacbcfdef011213843158072be84ed3c1781f67a0e2d4e9ba76a585c17fc0a
+d = 059d2a06e8bfd5e14a9bc8777958b85be5e97af892d2cdeb0ecbd2d5017952b5042349db5fedba2e26e7b85bbb31ad313d99434
+Qx = 0af276952a1216ac88ca7a194f5b27b7c98c78c42f852dfc1a2cd4c1a477ed16eebfdc90f613b6e264576a35c45f49aef8a564c
+Qy = 0639625074b69346dc6c617d624d63ce415a36154a817f4e18c59a3b09e01589407077b19bbbdd57b04ef8fc2cc23c673d52910
+k = 002728f7e9b4772ab790af0be9ed5b3eab697c4710249169d2a5782ab3797b8fa21bf8c1de659e3060af5a286353402ab982320
+R = 02a7027c6f94cc236dc8cbae35f9c38102a663b84f66143e2fbf9a152b1a6478bd803bf3171f933f63509d539a54dd348002ef5
+S = 0549ecf85ca1bae6d9f0038dcef90c93121a654552780f5583a7d44a73a9360c6799e76a632bc8907ce4626c0439f1518e3a250
+
+Msg = 8ea18387940035cff2f37278d321b344231075db43c7fa7fee9bd3fdefe5e8f03e7af9deafa1022eb108e19ec11fae34536a4fbac2e8c8139a081a997c080cbe8f3e2d2a72ff26edcc5338b21372fa1498e439e4d9bb12d51cc539f859047957b1b1f1fc30b90231eb06b365a4d404a1fd5a0e5cef171fc95b04d0b557d78ebf
+d = 0405590893cbbe18f4ad99df28b5f9d17f8f1882269aff0b7eee9392859d68927a99c942a3075269ddec6d69c0df2d76ab9d801
+Qx = 06ce67ace45a9cfa0cb45e8e1d0eeb44e94bd7527fed6b563f1069140a3f36e010f85e1ae5ef14d626c78465cae43230090baa6
+Qy = 1a66a58d87621b63ca662130ea342db029acc2d99bf76cf6ec4e53ba71bde4b00e508d332081055a65fc6f44a96f4e947d729dd
+k = 0035f09e0c15b41c958596ad3f5c4bd4a3685ac94f19fb97503fb5fa29115cb18fdff4bd104535847ff36650b7461550dacf2a3
+R = 051775fe1503ce80b3d581ea3e5ba761665568ce0eb7d6a7163d8d025d76002ca7bcf6d688b6477ae85d09c0d4017aba5ea8019
+S = 035cbe69edfb6fb99c9e45240b7a587c3805ab2ed6b0399c7dd8dd76187363b2ba1def66b2c3dae4bc2e40d164bf0f4837798d8
+
+Msg = 6a253c1aa17b2b1e6624afc8e7456d366ef5b1bd78e740538260f395481148a64da0b6a58cd53d7e06c691beae1a616547cd95c4d259a371e51c2c0e334c8a5311ae31e4c7af325686ff9f7a36f731010ee1a9b8a29169ceac36a060dd23611dc9713c615424888bb574ad5f5755d7311bd169336ae986c977a394bf16487c4e
+d = 062bbb4f565aa0f23b88ab9029d33b995729d10fcfc33ba7c4051e2fbc72f15636a834e3ebfe604b927cdfc89f53c57f36890db
+Qx = 125242acf14c7e08e9f2f0194f734841758b1eea1e37ba80b9855a14100a5f0b57bc52a0200cb640121d96769e9cabc45362f56
+Qy = 0dcf52cb899470943a37d260aa85fe83c3869c862001021660ad09b4d73f7739ad331b3566bffad590534207c6db9acf98399b5
+k = 06095b4ed8d51e37f6c723648af4cd4585d9d250d7519139f58a93c75f197c4bbd1142da59769a5fe178415c677caed1c3da667
+R = 041b212a54d4396ddea2898dadc363ac3ec5385c9b3b8ef1ea17c3d2f751d4f79137238548ad759b5e1700d7d78072df3bf84e3
+S = 0149242afc524b0c3583037da153f539aad85aa0c19c6c70852e3c3923df8c3abd0189a2abba872932eee2e6f45e02f98e810bf
+
+Msg = 0f91d0f0139faf3b90a3d4bebd7e96ff6bb6f90f6c68321fb392637d8ab2a60d649a7b7364ee6e4e274e1a8d342caee36cc11c56c54247fb0a8e8ef81ac4322b454dc9a195dc54567bf47ec8d4fa4cd32e76d78ea2d08bcbce3edbb68fd8597e56d5a9f2df4e47b2701046df89615961db601bd8204584a6a6cfbb627e2a1190
+d = 03fad7031cf8810544a3e4bd1382c0a2e22c5a9fe4804ce67b27591fc516ee81dbac841d399327168aa6abd79e2b5ef85df1528
+Qx = 1ef0f918c683be57eeab95d5d1850bd492ace7f4b37785863647774a028e963ee2c0eea801838aa8217fad75c5780f1c36e8d4c
+Qy = 1d5dfc69bcad46bde5539c58ebc89e1db2a3f65069ed963280cc2cf228b2568bd53c6e0e164d6b63a5d3c2b8e3be9d5139a62ef
+k = 00eb16d784e2aed724cf1e4b72fe76b00dc80948c07f9c7524eb0e83bc59c12a8ed16fa7ff21dffb8bbaa82925848a19c93884b
+R = 04a07e79b4f771363ad4c46cde0aadf3df4a233740a89168c97b54559029c51dc2c79b7cc94a0e4e3d2f94e376fe47993da28bb
+S = 0360f559d37a777119b2aeebf00cc17e2edf04a2cbdf74366f5d34368d2eb2c92958e4dc2b7453d5a509407a4d4643cc0235f57
+
+Msg = 50c17c1fe4dc84648e5c3c3ab8f7c971d4c58d8d56d2b5ddd92e35e6792111ed8dac7644ac8a07ca8bb4e38e071aa47b22ffe495e9083f9bf781ac1b5fba571862c909c7aaa7b8d05ddfb7ef61c99700de734d5658f44ae9fc908c85a2dac8e7f854d6d24be805fcd7f873a91252985c5c73129c60177ba8fd99daa87b25a073
+d = 03db41b4f637fe7977c90e4f1a21799baaddd1826c667102414877138436cfae1b9959842b8097b5276f15f2b982ee59df263c8
+Qx = 18eb25bbdeb41c5d14edc675fcac8a523acbfadd6456632bd593ab5f694a7734b163aceb6e6b3d8ed83fa1cf7b5adb9871a6626
+Qy = 14975abca1cb769a243936e65123167e535279197a37d8c92c7b138f31cad4e95c5f62b06f438f94c1a61634b34be7b96f09fbb
+k = 055fce73c9c385f007256253281c6b9d0930d127939026495d0a30f25f77fdb6b334043c39fad4223852f7101fce72746ea205c
+R = 01d7c26e0236afeac032fc5f3dbffc8c03b04417b514adc26d6a4f697b4e87a008d5ae97544a274c25ff66b98111d7c651c9381
+S = 07954191fad321e7f2de95a87d5a9c4527e658ef85faa6622d5f34f8bc2b84c881ededbe0281456e9b70eaf7a207e253d216533
+
+[K-409,SHA-512]
+
+Msg = 3583a3226e2dc463a462fefa97024e6e969c1b13bdc1d228e2d7823d9f7c09012390c2535baf086588000e908309090daac6e6d2b06d2ede6fae838ed47f30b5b481185f607a3586f6dea47c8f84e9d3b96d5b0ebae2462fde1e49d84d36658e87dccf5e30c0937feefd8862dcdb1a1ca373f6ae41641502ac54df6633a8cec1
+d = 065b76c6093d9c49591293471286df1a4444e60d9d06cfa114e175afb5f119d2abeb273b0596019a0ec5db5b5869f2cc827b364
+Qx = 0266321fd15bf6b1af862496f467069819e3860f74a07825e68f3d023985bfbb838a49b6a41b6515cacf404ebf12ce0bd3d6d70
+Qy = 01593c7a8e629599e63d3282cbea78023518277e6731fe8d88cbe525ded554b51a7f8803ab9e330f210619dd07df8f67e1066a4
+k = 035682af873829e16b72bb86f3ee99b5d9f052e4a631b07f87d3b361c8d8260a877231dbcb3f4d461b4a1d4467824a26a5a6414
+R = 00a483dc2dc6408c256fdf63b04d71d3c58a08db7167da217f466cbbfb2d68444c10e87a9a1bb04efd71135c00226e58414d407
+S = 078acfad2f2492f74b0281d53e4224c7544588ca9ceaeb16bf759b20c2f3d3ed69c64615c247213d51800569dc8b00078de68ef
+
+Msg = 60ca58462d53d074b370127132f4e59f5eb8d15594dc721a94286afd082a8934e52462c9c1c3910f8b50d7aa3671dafa5972958d876d7992467b2fee3795a6f9d8a7bd3003a8582ea8c003aa1e02c08ab6804d85bcfa13a815d75c938671f0af0706c68bc70a6155708ca755cac2fbb68b2952208d63e0e2e3d816f04c61bc03
+d = 07e9993f3fc1fdc4c376ef77ecded96006ac1159740bd1b2dc6ae3d97e15a67383f1fc931e460b9af3fe14a54e47919667ed06c
+Qx = 189b82003b546f94c066963239c7a590e064b88bb4548678853545920e413f2be32125e40efb82d2c9582d2d8269c1d408a7ff0
+Qy = 11583b267727ba6c1e17a244ba7acdcd836986089860ee312b6dc2d88a984b1fa232eb0419730db8fb94a5e077009c1d55979bf
+k = 07574dbe04e1ac2bb34e40f32d6f6db364a95cc5770b79888d72b74bd4dbce9fd91136e9e1152424d76688dc995bbf2bea34175
+R = 009e42a63b41877e200829356a2191fbb6f2a9a234be58c76b0852e4f348ca61e7492f90a37feb8b95a6dd6df9d1a2e61c63b4b
+S = 01499fdcc804fee8193de080b085b7513eb8022503de5f64dc12c04c0ba24af30e30f63f0e3eac2c82eb20c6672336f8732ec5a
+
+Msg = c749f9bb92ca9957ca6d0124206ebf65e860ff38a225e241950bf4526cef3f4fa9184ec83f71f813fe852dc08eca6b45b14fc7f2c6a19296529bfda007efe9d0d26492de2a902b45ed39603e22f0a763dfa5deadd97ef6feb859d860baa2cfd1d066c0be0f9f4e0e2fafa69cc51b12e814ad2e33b0acc0bcbe1df8cf018dcd4f
+d = 00c11e2979498695c660a2bdfd105b115bc4ff8664ea15cfb40c725406c6fc9a13027bd1d72ffff6258f29e4e19b845243444a7
+Qx = 0904a9bfebc23607c7c89b7aa89315343852cb894f54fe42ba4225285e58c6bc318b55691aa6a6ef22eb11f44cbda89f157d7a8
+Qy = 19cc1826280e54832b455f0ce0cf89bdb62e973a8e819fb776b1a202b4f207b8baf9072929c9e3f6a8ff996d6d529de899b024e
+k = 070fe023c9341df9348f08882bef47bd8dd7f13db7215d1cd52cdbe7919031a62455ca969a8cc6db0a05a0b4befb47c142c4f34
+R = 035e7130d59d92ff8c4f264fb2c346e052bc305c7f57549a0fe43cc7cdac6aadf2ce1939222decef4e1f900e3c2fb2c52bf53f5
+S = 0008d5ec1ed2091309ac11eb88157ba5122bb9b5c858a46769a130f7a941818445664ac78325e0b6d2a11bc89d08fe0e87a5bcf
+
+Msg = 4de8414780ea20f7943b1f1adae5e3962d96e828fee43bdbf2831bd71bd25df2976a3be37a7a667c7fbe1200de578920090d131a750c9bc09bd95b261234ea8cc25423c4ddfff5656d6b32da6e2f6f530e6673a8660aeca31273bb9a3a21bbd7031a2fa71ba37c004d3d1c64b2c0798783e47b2efe1a208959ac16e35d444245
+d = 068dfc23c6635bd1fa1076dcbd456ad6e8df7ce7c1370fe275803befc4ffad007fd062a61cf1d50b93aeb9afe1aab47a65af82a
+Qx = 05591f8cb59ccea17bfbcb74e69f05218d16175f0547ab95f507ef8d7426c077b52b82dcd06baf6eae7a66bc72422236e589e42
+Qy = 126a01d5c2331a2d00949e07ea9242ebb50d830b0aaa74bce841d4e43bbaa9e9aaa01ba25db7a8a2f4d72977c0f016f625cdebb
+k = 070682c9659089a703dd9fcdf2f3fa0c1d1ef5fae3f8f1b3dda55d9b611770244f8926898c904f6952c1847d287bca21db4dd59
+R = 02734111e3b736ae795929f835701bf290dd50c0fd625738ab2769242c1403197a3f4dc29ca618c2e292c6bec6dccff71adb698
+S = 0755292cc5363fa74e0193a806879d3a275b4beebc97250fb230efbb8364b2a30098c0488bcc6e20449622d6a5fd2ae24d7abe0
+
+Msg = a081d54232f84bb19dbd52ec3812748e2e6486f6cf1b177b27929504ca878036547eb43531bb5b3edc81bfe105370427e92831d2239cca0106d031d9fa8da9cf89c6fb6401377d5936b6329ccad854e5567181b8f16a37c35f333eaa0ffe91d727d183fbab935fdac2d5670dafb3fba59e4fa2df1746c58dd8360fa08af7f4e6
+d = 040807fb888e1d9fd33604546656a493629d94d4a0a9de2608962225ed158167f9e2438abe2d12a11e2adb6c2b66ed78215b0b1
+Qx = 1787c0e6c55acd69bde9b0a84d6022796d5b5c60fe5357bc0fa4386c16f61b38bfeadb6cfebee7e7701bde24418b8b5642afefa
+Qy = 0d9579d271ba3d5e2327eb863cfdca397070055b97714e385ffc2fc23528f696dac1a4d0e535641f6c876f1819f2672a8c31cdb
+k = 010b8f5356d8a029659492c444876f1d274b82681d4f600cdb5fb2afde13598ddb71676d9ed86e83351c70678886e8237a865d1
+R = 0304f43f9705d189f47ee09a079494030b0756993a93e4c6ee6b5e664f63431f99e505747c24377e5930f13492483e6cd06ebdc
+S = 0580d4707c97f0330f908042a6cb2a2b313f07bab34774ee03bbee63a4ff881b68def47cd300fb49deb49829bf486d1efad39b8
+
+Msg = ea60266f1538565b3ff42fa4bbfe319be070329059c52c8bc04a7da2824f209c1145a05e551ea59ded8ca8439c328f6907da4e81d658937df614be98c7b8648818ea80ef40e49aaa4431f4a211d62acf2611f5d60c446b2b25745078c643859be1b12b3141a09ab765dd63ea1f2a2df015eca0840087a5db378c4c4cce76cba7
+d = 033bda0a02badae08fe40c239b9d59e5bfe1c4d4b9b7a5acda6790bfd77ad08dde5e93a2da80ec54a7f88146d72218bbb88aa10
+Qx = 02dec536832c8acf007daa66a47e4eeecfb6991a359f8c412299ef56c6ca2faaf18c4db708493e84786a7837ab74c5fe0644cee
+Qy = 0906c8f603b579cc2384e0803d31d577f7c91c55406db3b2db91bbca323fdf3cb6d010617ad1aae7bf414c4d974f22e6f05af53
+k = 051e8d027e62db2397e4a807d98a24455a76eff6dc259ada89e794dec1484b44724894eeba842f60b73287642570460896dbe77
+R = 031769e6777444095d934d05dcdf82405c43ae91ad5fa9201568ae2aba25712717f1af2b8f49f6eef373237bd70c34889d0d271
+S = 0023498aa50ee095f33a4081bfd70a9484089c85fc7a4569f560ed67243745c823cc0217d29e2938f06ba9c8790650d10fa5b1e
+
+Msg = 82f38c9405ef0d26bcdd5b3fce4fb0060c3095f61403418e17c337933f0563c03691fabd32ab5e896c593439e7492a9970ae325c67196d9e83fe0f9780409a930326f7e6efae035ef8c321cb9ad12461edd5cde66c04739fe079db65406b3c2d22f2d04b1a4335285513d4ceb901d2ca2ad10c508302266c2cd6079ff14eff4b
+d = 04ff431769d26b8837d3e1295f5464fe82be29edefba76323e92078a6483ea0daa96221549102509a1bdcfd46a5a2e5de10c39f
+Qx = 1beb74d427d849705cf26e26312446f27a7c5ff26ea9dc1aadca763254fe53a622de29cba4fa81ee2f9e0319e752f72be46cc7e
+Qy = 08dfcda35a00ab77c3c47dbc05b0678cf561f575369507097833e86e523dec879e0ae9583b4261f7a73c9dbd417accd4ae6688f
+k = 005aff3ad332af23e0dc38c16853252825076d602ed4c6d947be751af5dff3f59611e6166c31740b5e5a167260adf2a5466289f
+R = 035c4e8e1858b9694cfef3e864ed959638ba309ba2066a28fb9d0e02a66cd4c187dc6fd8ca5fabe68acbc2074168157b685aa6c
+S = 04ec2db89645018f9845b7ae31b8418a767e3570d401f41db18e424fe861bf09114d78606a056617613447d125a283be5bdb6ae
+
+Msg = d8506fab4f681ba4ae86066aed447571eba4fe04e6585fe3be6af2ab1000a3da68c5b0c711a85ddf3a40cb7c8944eef81f2094650459e14f5b848e6add7e580b0198070f873eb3ed5d0728eabd92bc1398764b94cbb4cdd7cc2027b9762dd10782658cd9e8a5022ac062fec535d892198c8a387b3d2b6f7c92b1af6ab7dd9e4a
+d = 03f85ca1169ca7e9df44cbc6bc7d2868c9d94e8f8b699a42ca492dca0914eb5789a9032218dcef7f95f959c9554a1cd83360439
+Qx = 0aa3c77dd4324258bebe7da5338c772d3496e3fd0e57f455459542f1a1c5b47692f51c3815c9549d0c23fdc1ff610fff6847ea8
+Qy = 05e626d6aeb86dc51f3b359b10862cd33ac9927e38127f7f17426f2369d62132a2a62fb6b8354c5ca0b3e5c7c87117b4f777a0e
+k = 0495099cc73c9930333ae3f9d0b7057d7c70e2bc7c805c0c6a44404739b3fb68f9fafa53033b54b7ad7bfaf4bbf7baba0dd5a0f
+R = 005612fe87c6a3a164d269da902aa43c5a4e0333770ea6334f05750be3f31ee758d169291e15b1540d40b60d1bda279599f254e
+S = 011a633bbc058550a597585bbc9f33099eb517795600b019255f649493d4a6dd533be8b0965d9f9d9698677491bf929198ff34a
+
+Msg = b3f30d34f252a4c26f396079e773142bf61c0981d912333ade3de4e27cbc72cd8a16b31807f0c46116f87accb854487d83ec8c6a61565e6fca145eab70048245db08616779d7047db63aabd90dd15acbb05eaa510072c151c0518f1b34582b95f43ec7b9484b2993c176de79e84566764467f72392ef31619426d159c91816d4
+d = 03a97deb36d68f81f50c8829d412ee5de7f9d775633cb69c09dac558182039e275fc258240517a7c4aa592e364765321f27cb12
+Qx = 13f0f4c16a47ec3a46e7a088c1b6a63ef61eaea46aa9b2c532d8df84dbf64991bdc2c81ced3635e562d1403dbcf6aab2f8aa9da
+Qy = 03aaded3b99a454b820fed989dbf6430ddcda67db58e356397d06aa137fbdb365ec43994abd9c0a9fadd2887da9539bb4ab3c44
+k = 06620ad14a5835b9e9e104607c317cc599416683a60ed8865acf78ae1e861246567cf9d91f759c2d4c82cec835a4784d3c231f4
+R = 068faabcb7c716fd73f129ebc6625f5b4660a88e47dc7dbcebab321051a61e46b74409e2b0af420e1671ef4efe04973c43471ff
+S = 06851e5da033da0f28a89dbbdabe93ef11331c55cc03d5b096c0522370be681241fbe71d1349f219ce57761c85fbe208ac36a36
+
+Msg = 0fb13b7c09467ad203852738eda5ddd25b17d330e82c279630b0e1f0c86681f67f6e537fb00da9419114973c8559306de58b0387d86e52d821d982a60769d2f15fd5ac2ee6dc55d8ac04ee247282cb2866b8cb8b4d7b4b6cfb33bfefdff09a73d727193e5fb939ff66ac5fcb644a44f9083a790888cc538c5eb435243c6a34a8
+d = 03b1da0ffed24e1a3b5ba22bd684337f6b08053591620541bdad50c761d66201a2cf21a4cc636426456525b598e96baf97d9851
+Qx = 0116a1790e621272b56cb4579ffe6ab629a2d077b779b73e039d74f58c476283c110bb18b9c9ed63de7288dd678064de68b7df6
+Qy = 122b43afccb88982f2e07ff35468178572bd72b644322d9e1ee68f78880169a83a5bb88c6c994762a7e8d80e09333487ac30fa4
+k = 06d7a24f0fcad549e9c36dbc70ce264a75eb37b74db98b1f6a824ad1e5635be9818f45c7544927807dc0fb3bb5fd38556e8656e
+R = 0232339b50bdb772d15f2cb8973f6dd9397af45cebb69adfc089bb802e9c4029dfb2078a8a26d7197de10638ce512e5904ccc5d
+S = 056add03244174966d53105c570e8fa660ae8c5d53316a24cd26f24e29e4b7459f4c9daef07442247b63665f97a3c07d91a8706
+
+Msg = f9b8124281628cf4e1da0cb4f021c8d19d815644cd80c7c8de4cc62722904ec4cddd26cc4891f30b15098a25ba6923c6abf4774deb6e1883fbb409862f94467e75a725e7154be860fd58347577c83adbf18535c54b102220197afa062cc1c84f6094490ce488af4a08d2c5b808a2572e18a59de96c87162f88413795351cedc1
+d = 040bac7e0d3b54c7753c79d43469e310d876015d948fac4e3a9765444754476af72330e88d79ee6119697aafac8435ab5690754
+Qx = 0bd4fe8daffe47bfdfc43deca20b15da7c999084bee8983c62e3dd33740143c38d8f432cbacea51e6f53994265b2d8f4c393f6e
+Qy = 06d88c33c31f4e143b13bedd5738bc1191fe6815a099fb7b44617fdeb08daa0cb74edab7f9a8c67ac1e9c0f0fb21a9f02ef4b6b
+k = 020f2f6fcb3e471d47f21fb15301784f7cf3632dad3627a9ebfce587c0097871eca580bda051b100f991aa6de5edd3a7684e839
+R = 014f8884b5107e9ee5cf6f5d137ec9d59a85a6fa0431053d58a1400fbf0d518e8910179da1160de2c6cc8ea8ba8f3af8e0e1f6a
+S = 019aa8d55c8d876989f9b9559db0576f91c4610dc9187c74aae2d4f212cd94d90dd81ee4483d88d866aec1ed469c5e3eed7d90c
+
+Msg = 4e3cd6100520db050af0daa69fe3cfe6603a223d4f2a6318fc5836db8640d4c7fb80bb781302036d2d6fb8e552b4eaef3133b98ba2d36b9ef0b86243b0391413c73d48ecbf1d19170f1b3b781b35ffd316afb1d55d1dda8e91eed5553780cb2714a93e7ece698b832e853e2589c5ba2b8a997bbbbf625071ded66762af8cad42
+d = 025b7eb3bdefba3c5134438caf968f615b315204f348006f82e8d61057a8a8a853230cf0500f9d0b8c1551a59b9184862dd2ed9
+Qx = 17d2029cb711e52df416c54b63a95a66602a1d15c3761d91071964e0128c91ea766b3d409f72d9fbb5161a459c3fd7990f87d88
+Qy = 1e71a9c66a4d4dcf199aa329e44b99f80640fc760fa7326f29c273aa13b153df5277feb3c049e407630173fdc9f735d7aee4e10
+k = 0575aade2692534b5a1a17d36c36973d24dc501c75c3b0b497a3d2fec80c67be7107988e47199d4863044fe9176762497b5aff3
+R = 024c6004fa92cad446b8339917f517f04d22db47b3f9bdb83d863dadb5431866ce21b13e780495bd66152ab33eeff8830cf8538
+S = 034aa568aca7be851d276d2235e42b6624df1cce2b97f6413dd3fc506f0f18483f95f911feb0eb220415ac593f2c93dca0808fb
+
+Msg = 5411708381a65bef4381c9e13a04cdd5ba0c15829f7f25ccadf695f635384d8e4704cb562741747831b33852567f42fedbd190d2980f1bc921ce01c17d659d4bdd7eb787b3927fcee659dd3b65132496c687f2249272a473d46326e66b3cb78dafbb522390162c168f73bdec88adb145e6afecd561979846ea4c8cee38dc1686
+d = 0673b3a2985c95904732632e5d988d8d437a60db13215bb6aa880b348f011c609a1e860461427a8cf0d622abc47f910f5c97ffa
+Qx = 0c4f1c0cdc44d867ed38d093eb967bfe285df897868c83ffcc0c53463e3852a1b2039506d9508bf01d0d79ae537e42fa2070a5e
+Qy = 0c2bd9343041c2c4100c5d795ef355c796a6ea7954cd729e11063b14a27fc2c3a9ffdb3647613b44238eee17d9cc49e8c5dfbe0
+k = 019a9509f5f6d947532638a3c80782b556c553edaee9ade91e457f7b5d2c9055572fb116f52cf4d3a2a0eca72fcb32b2f58e952
+R = 02def440e968d17d9904c5640619af2f447f74b7c067537db4a15be87df4fe68f44897047fa8af146462ceed4beae36d54e1aaa
+S = 013d5b00fef639c556d66420090c2cab1edc57b7257dc35addd62a5337300e94ea7ee116e06b744da1b575d90da81e8ae2cd424
+
+Msg = 23757fa60fcabf543e603d8b31ef0cc99b3ed16b4816a84e01dbfc858872fcb79fd03d2f8a1d4f28c25dc42a39e20c34f81ebccda1682ee9bd22fe323e7f8ea90cf4a2a6ebb634cd1153cdc35f7306f28a2efd822bf23131baa1543d0ed5ab4c8168d3199983fbee117085f90550ec3ffa2b06070d3add1d707fc2593285ff58
+d = 00db7dcac414010b816236cad584dabeaec1da76c97182d1b62f87bb7fe2946a64d10430571b2b29ccf2ef72c969a9f045f1f3b
+Qx = 1f2a6cbb9c1fabc8db2848c74d918312267888d822b7dfd1634a543dcca4be7c997239f6281d1d8b5da9adc694706b7b19cfb0c
+Qy = 1bde57a2ac15f4e6b26a373a624588a3379c8eec758f3c68695e2eb1856075d90085f43283d982526c5e57913cca5e2b4169f8f
+k = 05a3d856ad1d6164993cc59e70f8551e2408da92c7e6cd52df51b37dc22e9ebc42fbe6b83c332eedffd4086a382056175ad7009
+R = 0489b0344ae4278a0376dcc64ef9ba8595bc2fd62ad22d42fb431d2863d8ca353cd9e59de4ac10108fc247d6ee9ef643f6bdb3f
+S = 06aa27335e15dc910515385764387798cd4a9b4cd6d99d7c42e07fc04e2bfedf8dfaa7bda396f88253357d3e2545e895d9aa3b8
+
+Msg = b976314d2f066f8893307a726f450dcf2cf865c170e90e6908ce9787eec48e1e2119a731b2bec3c12fd4e6282a393774251bcaef91af6ce57c63a8b45bedd72ab862cd169b7c84b8f6a72084ff823a96f2f8eff3483a7ebfabdabf0998377c5a6836d88135cf61c65a0ca7ca57727da68047dc635c17ad13731035fe9a6402af
+d = 04717efef16e1ae267e155aa1daabafc68515aa391dfeb73c13d01f3132bd22c984228dddc4dff4c39979e7585acd3f730cfcfa
+Qx = 1526c58a3de46c95cb0527869f7d637f9441cb5504e6a01f339907c6df3d079361a41571cf0a0f11996028a41682dab5decf786
+Qy = 1581903be8a19bf8bde1d89bee0d436f061ca1a3ddded4b7793fbc32ff852671103f34e16d469eacdbfa457643d1b18dd1c4107
+k = 05c846bf61c068b421efc472469ab1ff8d9f34847ae0065ba6f4a000be53727b3fcf97a780362566e13ebab84b9ed5f0cbbc225
+R = 00aa138e742ae81eafa820632f31e87bdcfce6b909d85805e46d87d1cdb8b968907470c7ef5806accbf6245628c70d264fdd95d
+S = 04df507115384327f7b8311dfd1227c19a6124cb9bb5901bed45d8d5ca45db0903f53e7bbf136350e66bf2b4f3d978f8bc546a5
+
+
+[K-571,SHA-224]
+
+Msg = 964ad0b5acc1c4db6674e86035139f179a9d5ec711b5bae57d2988456bb136d3aade7ac9ef10813e651ae4b9602308b071d75a934a6c012eb90c5eb9b2947b50fc97b1d36c5bf9eb13a7b06c94212c3dcdab402a563262298defff62b836ead1f78f9d20713710fb48115cc5045ba15140fbb4bdf516e4150d830d02cf30963d
+d = 19cf4f4d06825499949f9e0b442586fe1bfe3459813a2b92cd8de0f775a4735e02655702ead8e60824180761808d9e816d60bdb0238e1e8039ca7bb63c92e1cf8433ef447e64ead
+Qx = 07b9cb1728cba80367b62872a986e4fc7f90f269453634d9946f79b1fedf42ca67af93e97ee0601bb3166e85357e8b044e39dcc19e608eaaa8a0066ffc48aa480c0e1e8d5569cbf
+Qy = 580858ab9223c2b2ea58df506d703d64b387a78ef43846894e7a2e47c02252bd2c1e3d21ada7c21d50a08cef0f9a189c4e850c058cc57c37918251b5aaaff2321d7355b6b555644
+k = 0726d5e317f888dddc94c73acb14b320ff509908052868f8c6b14e531ca467c1f7c8287476674efd0d636ca94c24a69d15210bb43a368a11d3453d69ca80430cbfb8b6e45d8f21a
+R = 04ec6205bdd8f7eab414110ed620dd3fbbda4cb3ad9e5559a114ca9344782847621961a3577cbbe43d94eff6ffc8dd7dd09c049239f026a928301ffcddcc910bf196853edc86d31
+S = 16535b1af98a75b9bc0f122ca3ce23a01800fa33b43584a94fd8a8d6f40077eb739f07c9f0e179a157a28023735fc8da2e2ebbee5f7308925900e657fae7c3b321f14fc45346f89
+
+Msg = baddec4794effa668cde267016dda67bc70b847919a9aa595f93ba9dc27354399ef7a607fbead31e57a8ce698beabb10f313d393980425e67cf95be45d512f00e950c0c5409573ddc3d556f23daf056259ee8914e860562a674311452fed780b3e0317a7fe93baa81fb98df3ae4328b28ad0ac8f8ea33efe24faee658ad026f6
+d = 098521a732e72ed945a549afc92318fef7156ed1d1ed9bab93b581478cb2339eb32bcef705c9bf61cf2873ddbadff8ff3806740a2e30ce67d1807a8179dfd5d952e6f8a583baf81
+Qx = 1e09410bf4f84d53a2abf8d106fc64e643edefaea263dc98c308aea16ec75f083b3e6b442ab261226c59ca5fa622db68f5cb5f2d1d465b01d0048554b0ccbf67c0aaf934d2365f6
+Qy = 361e5b43d313a62c7b3897c7db8a42116127138a1009f0bf9892981fb4fd6ae231b8940e7509f96e2a49285143010dfb4516ff810a91a4d9d2974c522ff343e93e8aad00aaa78b9
+k = 128056de96666acd09b93c5db7ba1b8fabf57251ec480d42b702940b5847d2a59b04eb5101bb3990c3ae2a41181f19a2afcf08424f8b922a95df6b292b1856dc4a9dbb1c717ba5d
+R = 163483a7e0d1012695ce0c113ec8fae3694bccd40fc038d4038f81bd39e71c969cc7f0af8313a9fdd3d028ab24a43279569dcba73fd78ad74897964ae715928b1cf7fcb779b12af
+S = 10aac6929432a6bc7e12ffa86e4d2421e0535fc44a1160fcfbee477c29a987e783a7f753eb2278ce08954c7e90284d2ce7c42de103a9c59d8e4c459b457688ad515cf156cfc56f8
+
+Msg = 7ef7138fc657492d229054f8a50dcafcfcd1dc06f1c16640af3f658907e2969248b54416066eb119adbfa23b8dc578aef18bba79610b9cc109394b900a25e55a779230bb858b2ddd9499a7775d392328db9177aa9571c2f61dd52010b48502154e914a0c55a54edcc04a6713cf7bda8744a893926118b09df877d1a4f3d95e8c
+d = 0336fb21549e397a190beac38a1ee10f0551952da15f71e11dfda415e5ee08da2356f114d450c661f52b2b32cfc7b9be61732672691a079f0927989b7e9f4efe6095a242155b641
+Qx = 316800fa2d8f8f3f9aa87ffb628dd7b2f63d4d8389ee86ed41bd4c3eecd3f3836ba92e2ff7ee5626213f9ddb41b43561c5dc0bcc3df0a872e4b8026c09c7b52b89b4975a43f60b0
+Qy = 207f956df58f75286232967dc1d3e6507634f45c0014c48b42868fecce5b9434463abfcd2b3722a7f5ed25607270148466f6ffad6a8c86e538640ece80e84f7368d33c68807fed6
+k = 1517b3524b6d43dcf3964f7c35c89bf14dd1542c37606452e2035ff0bd0cd1edd6d7b801ecb1f573e957131c0b3f30d5006f6e4748a11b9db10fad41961f4ae53e848c6dc6e1a52
+R = 1ffd4865dae7387ed797c5ffe58a929cffeab521e48284bd7d4427d5856e9d2582b91363f1d353a0ab1aabfc132a778a516d4033c64cbc991d724115d72ff8e94ab4f95a9514843
+S = 10f010aaf1bb714042fb8cf06a9501dfd1ffa598d6b3e68e7addefe00e18f3a5db8414d625e374d9ae70bea43b57c6be4a590c28e50a548cdb2e30dd9d6e3ed1d9cdada9f8b0049
+
+Msg = d58e1ff1d49a471d0567ecf8f29173dab5fe5f6184ab4cdd095c231fa7b82551f99a482994a46c3d8ebc07297fc9e952a5dee7d5f199b119f6f8b250f8fba45701ac252db725e75c4da27ad77d59a4eac448e54a277986740dfee6596811e59afc9755e53d24b826c09e497e29e69a22bbc85be11763064e9ecad7ae66458ca0
+d = 0e287ebfd9ba294128cbd484fc5121d271cd33e685bb1804f09b40aaacf64b5a9f2cde9b30a4a02d3a9bda97d92f46bb8787b3c61f280b1e1a0680f1f0679d3bb34d53725d62e52
+Qx = 52903a7afc17cce078b4b658766a67f2f75ac04e296757fd762fc05d6a7b4e4151598a872eb4618efcd06c43cdc3e54f437c0ef1b091ab5e4927d3ab4227fb24d4413e0327abb84
+Qy = 385e808bee8dad1a1b84d644aa29fec324dac2242709421479fa7a712d18b54db59778724ccaf4e51a27da090c6dd0b7967024db0a8684944b77295c9624ce3aba24ff48c86ac85
+k = 15e8cb22e371965801d99407d96200015ba58fd7eaea52c03269d8a374fc7aef17fbfd4480d29b781292e179936a68ed175802f34043018ed1d6b5a4df667d859cd2ae53ed3cfcf
+R = 0d3a57af73b7504ef18c03ed2c52aefe1d1a3f0e27f78c11d45e9825647d5ff6e97af51a5e366e52e01e5e832e4264a1d5b6967cd9debda59c955568e4c8bf804d843a49a0c5401
+S = 064fd7ecf4470f07b4df3b3046041e49f310a463210571606f00a1915c5220a27bb7a28cd0bcdbe374651aac06d4d9e017e31879b7819301eabfe3a7afe4b53f75ccc465815b4cb
+
+Msg = 4949ba765c14c31f68ee0ca26bb42ba2edee63537de4a6f5c42bbd862c21288d6ff48145260365193c6fd2b56dfb014da26b8a483776b717c6874f627c9a622154b824565b23e178240f53ee9748c45759ba5c035b584df0f09504e95eb9bce0301653aadb860bb25e6ea6b9606e0ec3bdb8089e6aa0d5763d331757490715f9
+d = 149de496fa8f88b2741864d0c35b3df666b87179b7bd06cd426a45f13bc87ea9f50dea85e1fd02a532630e0e3a231cc3e7fbb7c7ba85b40cff1124e72c677c6a3ea6aa40ffc64b7
+Qx = 0bb610e4308e229e4b4ddddff5c4633ef2ab40bf74514433bd068c7d59a6260ac79366dcdc039d5585e660a4cbee990a2cb55a99ea3d26dd9df856b0f3ee5b968bcc349240a9a2d
+Qy = 3e3ef4be63fde6ca09f12f8220e1d9b5016f267ca5aa09a2dca8a0e0feda9647fe0e1f7ecae7147a10ff893f69a4f74172c6e9a62f0c5bd96d49b47379c9c84f5ef8e59dea104bb
+k = 1cffdb963c2c8b8609809e998075299776b44d2808df509773f310124b5f318d7431f1ef8b38fac5cd5580348abc41e6e6396767f4780656361dc9a71dcc8e7c9239d6eec5cdb94
+R = 0982b9989c92e1a5d25dce832bd8a3f602f0eaea69abcfda285cb3841fe3f019503e6faf8a693712380a48a6af8844b6bd718f0edf3b57662a4fe82ee28d036ecc4cfc7310871c0
+S = 1678bec58d69def3fe35a64810b27fd06bc29d165593990f6f42c4c7676fd5d4a965fc92cf20ab8616c7ac7b4b308ce6290c5e8b4edf6859fd6f6f01878f2601e22acaeb5ce1f36
+
+Msg = 5bc63e5c50b1650f0ed4a599960f1e4e11f6c151b2123fd71d9e3c44662312a74b6854290628e20b30eaba81555acb2fb49b640bdab2528619c7fcad0f2a2880c7ea232d427d7c935fba2313370fda8863a7e7e203d63ea15d0cfa083e716ce6068c63fa616ddc225c9e413e694cdf6b355cb1293af5d6cdea51168f5634e878
+d = 17605d7c5873d870462375d741b4bc6375f3d47f7f5e9d998917adf2137a81e63b66917b3dda8968930c4b850f2270eb3187fc756e2beeaa67fe0d73053e6cc0ff0004a21250551
+Qx = 0d8ac3e76c25cdf4902426569763f4ae0638ebb1fbcee6e12a4e0b89d6d451cf420d10441a0a9984710dcac13bfd7ba70370afdfb58e2d982ac367e178f6834b4cd2d232e7f246e
+Qy = 12b5fd5b686e58df08b695fc333937eafad6006be5a7bfb1426206102a79bc32fd9ef46e19869448fed0e917fe059b76c8b5a9c403c3921ad07e6c19ca7bbfeff5491b22f8bb961
+k = 09179b3ea906137dcdbb97b27f3690bbe3bc4f1f57c46ed60b8503cae97602717a0724e055a5c52199ae3f08f1586b87fbbe514667d2eef2fe44092f3c916976c7b71eed67e8fb5
+R = 05b28342703c83ec2df898458fea6f71030e4e9c567d140ab09cc95df29ccfe199837cd58ed00d07241988bf3c863504d065ebbeb8ed11cdcb02da0a945ff38ca58d629f76832f1
+S = 01442a5606791569749b5a9f20ba8eaaedd1a2ceaab2ef55d5d41271ba23f6a5b6a33c76763fc99b291b07283122596a3331fcc9ac038447f3e0cb54872c140300fea65d7809191
+
+Msg = 610f6633718e49d232b3798654095e2efa0de11f41258b27aa01956480c870d901efa77e109d5f95f1f5101d3c90fc51312d9b3019d2e42e0067eed7b457dc7fbe5466923b62c83d7347e4dada571b57813bb9c21d5e308519b8eedb7a7706508ad04aa69698e03636eb30fd9fb363ef3a185756494ee01175b16847f5b68076
+d = 09214dc2da0967912c31995cb8f5bcf4bfa832c5a2d3610f3a9857e5eee7c77100d599d9ed003b4106013155dffd6c48859b846e45e0ddbc5fe24f4891c9b2df51407e9cddbd974
+Qx = 64376a92c1227c1c479260c7497147760c103bfa5be95ca1593f29a851daf2e5c3a5c73c1fe3e6e2506fcea710254ab5eb2daf8aaefc19cbce7b1c4afbaa2fcda1ef85750fc0a3e
+Qy = 70638482e5c7c17a82980b863cde11294c0df717bfa4b9f884cbbbbf80a64dd2cc7c7d89ed21e10561260d372da2fb726de71863f0f60e8ad0fa5e74fb5d29bae0cbe8ad6b32f6b
+k = 0621176102c6ebc2c810eabab9f60feb71083c07751c66f719370713ec2de9ee3957bba8d768b076885db1f226a9d37588abf1b141d81b70f0af711c52edd30e92e34a1d3ed214f
+R = 1a21d460ae85d0703b4b10a2f77547e45135048ffea590ce86e0a1c049f8a4aa7b395f723b7480cc84e33f4772df8f181f3919f3c0b0b4f276b0f855174103a2f7bd757584425cf
+S = 0b56bbdf6e2be1b9e754f9b48b3ba9a13403c17c5cfcc4910112704aceea9a34209df406ee40e0a10cbc26d03839f95e775e80ec5e29b156fa277a5ac68abd99c7005ea6ba2695b
+
+Msg = c548f0546cee0c0400401cd540a0aa9377f27ac64492e6baaf38e794db4df83e64ca3d83b67bbb46a6c269c04c2725287cce0dee984a0d468c9ce495a7e554a6835d72c7493bfe88dbd5a044a148c89001b8087fb03e57c2b7212d0b175d616333a9affd8a1802dd49ba9be3ab6c6d9f99a5578d26cc4707a5860c6c804d69ce
+d = 042f2682e9ac8b76f3c0880e12c292524601dce9ea6982dcf68bfdb0d3fbfb50dc9229e54149ef09b95bbf624eb04ce1427077f30d8536be9f69970ddb449ca22ab8368d2689ed4
+Qx = 116135b273ef876453b9c4c39e4be5a815874857f4a72602f0d03b4ecd9a4ad73b90600c71111e317df0782fc92e6ce2b194c204340bc11e68cc22ced38e99f90dbaf0f917e970d
+Qy = 36dfa65a6e9d0ba521ade7daa2f6b01e1d14fbe7b5abd29ae71c4eff66c390914bf46f09f4ab8a06dc0fad6fa257a85f993d6829b5e0add5086b8fe2ecb8027d08eec1bea981cc4
+k = 0bf116711b31ca347d41a6cee5aa13a74e042ffbf79d2ae9448598e6950d721b3773ae6f25d7b49ca9dbcd62feb011d5d556bb9f8a55a7acc9a3a166a4169351bc31a293db68eed
+R = 11dcb7f4103e814439df22764f776a74aa86ce9717585712b224803f0ff193d5f541d94142812c726b75e8c2c37f2a4c33db6af118af73d3ec4fda49cfc911fef1eda9a470ff200
+S = 15fa4ada3a6e95164aa8972f14ab7572a3b898feb6cde160b8f25094f67343d35e6efdfab18793f77e09e5a42f56bae747b2b66fa9fe1e4a97e5e05ca743c058b1024cc848393b8
+
+Msg = 9431c6c5237f6b4b35682a0c32f68752035c8b295a1763c5dbdfd73466cea64a00ecc11356d02d2a9211dc54548f5db1651e4471898402c887fbf45005a3bda271df0158c98319d4d6751b8ca6b07100182957d5fe0d97c4e2294406f83e9afcae4850bb089f2252490417b5afd8f07f4c795fa84c9c7cdcce26bd97273c0072
+d = 17ed9a9c75cf66528428e85b0f019e3488af8b893b12023ff1b4ca9c3691b74e594539afa0f4d7c3863d15399b862f15e27bb077392d6bbd546ddfd46728c75177338466eb2f4ff
+Qx = 760779389124c702686d8d7c25dccfa74fb333317bdb414965d2c271ca5e687c4cca57e6f6149e1714551761abd4d651e7b04451d8be8e58c0c9e361fe0c6771e3d547d6ac3e8cd
+Qy = 52d5725d14b9aef93b83d638377f5a19e3cd6e3584121fdfc2c3ba1a588491d7e9892be081c9e7585a15b37a9cd4c204054dadf06a9f4ebe98f95f6554941982faf109c2af98c65
+k = 104ba3049a642d9b49c4302e9173a9efaf215b67e060c5e9673521641c9c2a5b14bad25a448e46faf73810979a3a50104ec8c5230a909ae588213161fbc10381d7c75b35c84046e
+R = 1bf3e89fb0beb1ab854a5513278dbd8b9c6b05c94ab67145ceb1ffcd93d1a2aa374db46ef327043518a7f272b957dbbf9d6cbd6708f4c89f05865932b7e816b12a59647d972f6e5
+S = 13a8c121c9c170b244ae3a55aa2d53f4ae5af91b1f72c066207e3f52e44723bd4ae419d24821b83648cd64fa70536605912a5a9319dc446a6b2b639cb99ed2485271acafc2bc988
+
+Msg = 417cd5f60416f17081d2c70e9a510114e08be83573bf9deae75fbc3095dffc8a7f7325f61f9d6565381710eda871388cb17619e4448836076338ee309a2bba5f737319002e259b4a875cce1bb97996101c9a7abe0278dcac203a712f0809eb3c4b85a9c380550ab0bbc5067a8edfa78abf03c09b5c08f21714e1022ebfcada4a
+d = 1bcc09b3f2f1d26ab9955bff7e8c0f85c8a61293511a196b53d7963f4a4503849c96fb4daa68c9852ad9185e01a35f0bf298e34a09ec352cb6da34f89a1f23e8ea27712a8f43aa7
+Qx = 1326341764a4aea222e7413a4a6f7bdc0c35ba246e3c68728ce06bdb19f2e1b9102add88a8511130ff48c0cbe4012ab52de93329670a319f6b1e7e7dbf177667d4a98d3891ec147
+Qy = 7a4aaa73713bf8fb3907d49e5653cf82a9587518c2f8269cd1e556a3be3589dad4c238e4c80681e141be93c318f0efddee3e378cd46512d778b9033dc8706bb843a3c3546e76e4a
+k = 13412a98a2c14a9672ecd42db9c079a689b147ad91869c3d45a7046aa9dfd3f31edb43ce6b84e9edcd7e3ac6b96d89f13878cf5befb052a6f8a4e5577bdf916adb10d908d5e99b0
+R = 11c8a92044a30be397007a71d9af3e4222556a10f3a07a1521c1bcef73b4ddb94fefdebba5944d5bd91313560718a8f520bb5cd5666539756a5e9b66a1b2d18fde5ae72e61d584c
+S = 1ea510e23ccc7596db529dfbea78c99fc78ae53da32ad7c7bdb1df01039310988ea601828fdfc59a0cd237110cfee9de8711c073be44dd4d04bca4b1cbec278b1a9ef175d93f70e
+
+Msg = eced8c412a153a643ccd69596389f83b6a36880286f8aeede503452bef8305942d95734fb5733f37ffeceb1c2dae7b1396c3323de11089082745c28a1756f784423fa7ad68bbfbf0d93ff8b7ad62220500df6d6895788402c1f5c69c06dd9ef55e2401cf297184e411be87c1bba657f847208c0e750f94a3df92f253b377b4da
+d = 0ec52fc3d9c272ca80623e06b15c35f349b13548ef7ee400bbfa04196850b3b8cc7b239238c827f9b0a3160cd97969ce21d66752791f5896e0385b0527d4d77e4b9fc70f04d73b2
+Qx = 5cd2e63dcd48fc793c18776d030398dfe3f8b6978eec6d23f49240581fe1e141f667498421f4c40a9430587fa282441a78bb641894cb79d929c299f1aede218a0078c247f740252
+Qy = 0cd2843ca87d98f6336c0adb97bbb9c5293a03e5b86d5534e2849ebbd73dff837ffa488fad7d134908234d0d7fdac8c7fafb4729ecf0516c42995fc9337f60db2f36eeac69a4e42
+k = 1c40a15fca0c959852afcb4ca6cbcc99fb680950c64ba18ae5388bf783052b6ef3730b1fb1487189ad983b6a68bcfbb707466092da52ea8893d8bc4898eb133fd771e78379b9c13
+R = 14485cb1caf1527350587d6695ee3df2b21c13084df0c093ca5109d7c192e7e5df2232ede11dbe5ff2f46b13dc2dedb709a0fc1641c1f32857040147599d8f179fea6b2f2417646
+S = 1a16ebf12c11d2d0a64b7ea124623ffdfe2650fc9603ded571e76dbd7e3b27cd32fcb709e2ba04aee0e8e1b942a4e829cd0c9683aee67eec27d4244a2cefc36f84f7de209e22a62
+
+Msg = 30e83ea39a92036e22b7bed7639eab5e5be1d00c20b4a9b9afa9a0d1653369cbef363c119cc6f921c8f84663949c8b8dc9b743ac2b1861a480476e9b64c8f333f34b6fa0e1ddf09d49618ee4f3c1f46751b5595f0aea413d4ca46f3c26b974b112cbe99c813a96a4423764c069454946f213c5f066ec38108f947abeeeb02fb8
+d = 06403de7627de22d1dcf6b8da5af62f9ec59ec065cc1ca1311bb98aa439a6d5985619b17c17a70f59e17cf180ea6828ef57f5f1f8ef05680a9fc12ab7faad5af61e4e11fb45d341
+Qx = 5575c329d73f261ab6897153d7261f87e9730eb5dad49c05d782cb02e483fac4a9ddff31d2fb695a62cdc44edef6398be8f4f84aea1d63d0b3a771fe91889dfac4780063d258325
+Qy = 183e63ee783abbd00547567bb99e9b578ad8ce63d229db41c6877534487568c423d4c389154af9627708d8d8f863597bc668e88f9412b21a6696d07bba06fe7aef93b26950c69ed
+k = 0e751a4918643ba3e68bd9406a4386e876d0d66342aefb4ef75bc4dcb8cb2e2d9f8378bd02c388c776535ba85d24b206f5bef4b2f23a1c99fe2f2e8ea201009ca468e5b2e21dcda
+R = 0ad6792fdff4c621219549834cf03808645171d944088f5a6d3cf1bd826b5588544a32f231e8428a03ec02d6c1c1243fb6b79b1cc6d732be5be8f2cedf03c1e5588822eec559b7c
+S = 178b64bc5f9fcedab17822e831fa52d49ed10afef1c5912893df4bd8dc960b474ed25883ddc343341b696fdebd06e177f234ea45553cc83920a8c799ada2deccf1ddf1dd9aed863
+
+Msg = 3ed244dc16a5cb292db4b1433b0ca3226913f07377faa20c6c1402cb4d026de808ca74a6d4ecdd7c4e662105bff6edb9fae0117c50aa053aef677c0750c7a446edbb879110030758912e8fa666489d702d8fceb719963b24a256429bbcc869a1f4ab9de9db89263e3684d4daa1df2ed94bb59dde2abba63793e5f82aa2e4db83
+d = 01fb980aef64254aeb9bb613ff2fc6967503db4bc1f337882f1566cbeb57489cf32e34f310549f41cba1b951f487453c29753a184e33330e90d4b973d2e406c99a239a5c3f96233
+Qx = 36ea761ccc71ba55aeab229aaf874a7c2d1ec15d821401e2988dccf02798c4e7bea80d9fb8d30be213fc80475a17f45d60c53249b66858d29c73e73117162934dd71096d746742e
+Qy = 49bc28f4d45d29c3560915698d03271028f56c29f0ead0608cb72dd0b62490f95bbd67145a6c0adff0d6ef396b4deea6a5e2a33f242bf17e907b136c039c127d6012c88b76aab3d
+k = 0ed404ee6b59ffc445b16f11b9b1471249443f8a7309ad8a662b7cb44c94866828c906fd64784c699cd29d3d972e5db3d42157452630f14536eca23cbbdd1d37e199e5a586fc352
+R = 1056938496df511d745f2cb88acad279ec2d58bb36498fcd8139d426d596de6d145b765a5b3e8366845fceae91d14075356a32515134e577937ce2af7e732b4e89a9164d083adaa
+S = 0d5156c776f2184babd69c1f200b8bd94289d45a2f8b7cd8e8afb1455e8901d8c3ed14b7a23b0976b85a22b86f3ccff4ae91e286f696f39646188b675895684f33f0368098fa7ca
+
+Msg = 40343935d9423ad30f3fb1832bb08a5d20ddb3a55b59057cd275320db4a5835471c96cfb7d67f41ef860cf5879897b8dcf307bd1a52a6226847b768ea38ff1858f59e64cd635b51e6863773cc6c64b363ec47ca39266422406264668415c189e2f92447ac4c63ee5d74e95d1e6af05016917ad237f482ea0b02aecadd370a8bb
+d = 1d96dc09dfaf602789c1dffa5c9ba130832badcf180429660daadf4cf1be5cca92fe9713173861670eebfe3a0ba25bcc76aecac60a756f07b69687e05c7e25984a39556469f62b4
+Qx = 452b1cd70e3c88bec1fd0e4b8f8e9bd5f844ffc12f3d6769eeb1c9ea90e599619908682eb5e43b1d6eea63ba9353fb64b59d6549d19cd95f2f54156c81fba53aa0dc91244e7ab8b
+Qy = 20926ca366dc657d133f0ff9149738738ce68f3cc2f61dad590e2502e8fea714b89543f43d97b46b7075c58375efa379cde208ce769a16be9a377a111a8ac51459840a223f34695
+k = 1dfd064dbe64c25a832faea1819cd836d22583fc40b2ecbc19b1f5173c25f33ca8cb7f30bcd619ef73a4c14c46e610c8996059612728f508bf7db7ab3191ad61955e8b1ba409692
+R = 03cbb0ae5f7c0978ad8c10c4ff099767465ed6fefb7358f3eb58a79366707107cc88b305661526f2972bd16923375dd898ae72e81f290b86cf9a4dec086d7ef04d7a7bba5087f8e
+S = 09f77a86f0da4e35c395978603cbb9c4dcccf126b7cc924cf62732593bb1aff0dabb6d58321debad4410dbfa1fb8fe249bfc336db7669e4ee13485ccf8dbde01ca4cdb9acfe5e74
+
+Msg = 274567f8841183e68c4f6c6b36c5a52fb0e88492e4076b9cd768bf571facf39dad6affeb68941ee326ee461ce1f33c26e4bfb3c9e0cae8241fbcc14cc69c1af68701fd0be3def1e87b7d52b682ebbe1cc225c1bd177b0886e3698a06d0e410a1f92c9bdf7239189f6acde0d0653815a72987671b415d1e8a70e685d6e5b14c33
+d = 09d98b32c8eacd135ffb8e13223690ef02c0c1f29ea8b4da193502c8cb3f39f9eed608c02fd457f2fb685ec4595e8fc8f388d26778d225d2b18c9bc8b199d8b65c0d1a6af33854a
+Qx = 775560724ab7d98407e20af12b03634a757037f8b3854957e11900d58460ca20d93ef06436921f8d4481ff9123a9eff3973e17d441511df3cd88d0d6dfc8016d2cbfb8963378463
+Qy = 3082aa4a81d4e6f0ffc94511327202f2baed72c08026e05a288eaaeaa36a1a4961f400b4712ce68778ff38be43adc2222a986ef0fecde62f861575842429816c8fc77797af018c6
+k = 1f4acd3430931ecba5e9d986c6712467526ed94a0bfff36135da3ba7dd9870ceb38fa0b658dd391ce658774c6725360dc20e5ef41daa9cf52fa863840ca91053e7287ed29ac69f5
+R = 0502abe544fc3262663524cf88a5bc256b20829b7bed3e2779f559506adce3c4f3a89e18bfd31819f78ae3809d9d0710c6591b2fc90039328678aed9df2fae38a74b66f69295d82
+S = 0b2f055248d9633cafa4db3b3cef0b76ee02f6bda3d508e19c68870e76a02c69dd1013a03fd741e854cb34f815432bf48138203177141be7209e957f4db1a958fcd45421a213c98
+
+[K-571,SHA-256]
+
+Msg = d9c99b8da92d3c2e40dea3c4025dc37770e867c4d2746c4d726b6de24250591a586c166c88acb8ed340e161d4c81b9d14c919a1b06f1feb22c5ce5fca2693bdaf4994ac72c8983c87f331473fd094eccb3d5f3528e69d487562fb5a65c150a8217192f8aabfa7adcfd0b6916d5000248fbbddf1ca2f38e3d9ed2b388998b7cfc
+d = 04d873ac744c4f68bb044783ad69e1a733cb8b8f483f2695bbd90c4211282036ad7914a53b25c3e890c6824643cffbdc4138d7ff457e3fbb99387494eb5cf2bdf1ad243a3a1e644
+Qx = 4644456a4e5c543af7a086640fa9ff6627c2d9f17066d255c3e805db31fb1ba895682e94f6ab96d6ca449b0c3f76bfd6593d182f422689b31d9dc3bc0b70df210a96d19af9ec2ac
+Qy = 1d38f8572a06ce22c1586a8329f9421414b334352f1e8b961f7e0732ee01e838eb975bfb2f62132bbfd9acc6ef8899b4fd388c2b59e564fc3670da7a008ca016de678d6dded137c
+k = 0b050aa7266201a42dbee063ae2a21398ee1d2a190de9fbbce2468836e416b3ec18d7340c81fd2a5283713f9aba33e8cbb105eaa2abbf0b687fe2713921bcbc02a4b77df21f762f
+R = 08351115714bc8f29b84a6e3f0a23bdc219d4271a9ee18bdab54c3acc9cb3468beb1f89b0f981da5aa7d7ec7ad451bc5e91bc98440fe20f5877a4e73614820b9ab6f2bad3e2e609
+S = 0c64baaeed68178f5a1d8f095b0932fb73f9a02462df5e8378746ecf17d05971a0a287d5a8e0317db055b02d4f4b5864597d0f9a9cb1ae68577dcaf7db09c55bf3d3575197295c9
+
+Msg = d2b88a01fa17703c99e5b867c645e98feec0d6d1afaa20a97b5fce9c23f0594460142af4e36a5739b8d26d3ba35a0263caa5429b4abba157f359fce701c43372500fd2ae1bc2ed80bfcaf8cab7016ff93d4a27f565b7e67fe7dde22bf02c48be12114fbff2421517c825019c0ccc72d927bef156140d7f0e9b6ee37af78c3efa
+d = 18d2eb947297a054f8a789771dd875b12b26ef057fb91235dff3b062916f85aab3365609bd2a38a861439c8514e33f174c198139354e63766942f605107cb1b9709b782622b295a
+Qx = 3f6454f1dd032a925c6bc3e1c62892c1dfaa700d3badf83f07c1185c31ea817641865a129572f3351340fec331f5ed466db7bea3ffa9723c951b518ce6f3c9263a7bd6866c8b0b4
+Qy = 188877b68c10cd6ee543cc5638bf0f82db25b9327b2d81269dc61250eecb976d6568a9df29277836b97973e3615e0a4345e610b33909c2340a23c61dcc6e2baf2bc363a33381802
+k = 0ec6af799d92ab52c51cebda61ab642d4876f374edb17253a1de3e880048355e58367096d3bc0402e4b93fa6a6c8d55c529b9fd68a27962c19274393ebe1bd0b1197a28125275bf
+R = 095c42b3ef01c0f9ab96693526e903ef3ccf0d843776089d15e77093fa9d010872d65cee1801f821bcce747ddc5875eaa462b00424e6cdf0995b87c6cf33c37d4463848a6ad7fee
+S = 0c4f0edd4b2dff4f9fd1fea5addef6d483bb51c27bf5c7aa13f9482243e5ed5571bbe0a658543c69b731de56b6b34de27795095b3676375cb4686b45d48010fe8c941208cffded3
+
+Msg = a704a1428cc894f958774368979fe075353b56790555386e3b043dc6a2919b94a11c7f85883f46b4d47b324d349c28c667bf9a000daaca1d7191f2a0fd97a4867aa9f72422134a690625408a9ea4b723704690b69152655f9e9dd5fa3dd94814d97dd4f13e85c3f9bca769491c2461fbd17e28afac00bfa81371d5039013da8c
+d = 0594fc0b7a5cc0216d2e78eeeb6394c8225de795f4b73bec48b2f4ede185ba622b59a16dd3eedf8cf2c94f2ccd6dcd205f64c97cf1b7f1e34129e94b5129502909f43940dba0746
+Qx = 271cbd3e0d73ac19b975559450d686ed67eeaab4175435b2801e8989966d7c5ba81ee7d749e43dffa12efba820462bdb274a57d04cd7e92c180cdf555686c78aad58444d5f17129
+Qy = 7c407b46e93d4c2b12c967cd3e41320ea8535a2ff24372a5791fac9e95865e14d545dd3627dcb4aad2350db248ef49469ff4d59a879a84a19d1c0e5d7ad3db432af927c88aa5d48
+k = 1e730d50a9747c7c1ce2918fda7575bb81a74757cf9625d0f0619aab7f1eb6954dbaab749e573290406e599eddd7d3376dcb3fb98c116ed7b65729dd04ece3eab1d7b4bed52326c
+R = 00d59ebcfb30d7b27c87d56ec2fc9286b04b39e68dc49b395f374e19647bcc58f2fdce1c0dc815cb2aad55cf863a4786efd6c3a0ce56c1d92aa20a19245e74550c17fdaf7a08340
+S = 134e80d63c9b328e02ebafb75eabf0fafba886f48b25206cca9086e03658ce2047c94a5222a206c6c5a57ddb8f59c5ba1408fc56668066fef4557124c430cbd1267455e0b31a8bb
+
+Msg = f8a87c4acadee27a908718461e3b45060ae4ebb009b10a15926460bf219cb7e75dc3a993fb9a741b94e2fd71615c50f6df958568f452b2cc284f0516816bc0d2e2d45f663155660a26326f63f4aa42a6e1cc8462a2ec620a365257ec042f55e4047b62af689592a1a072553ff174dd629a4f51837780ca232cf479a68c1ebdda
+d = 0f000631106c5851e8ae0802b01e7a8a8540b427a8a3956a1d36f0600be89318032320cc420931d825cc964e823745c60aad3437ebc1c91d32004472e9677605fb708e5a71a0d83
+Qx = 34136cc7b8e2dcade5cbb9b3d0e0857c485ee791f862273749b5d3757d072bbeccdd8eb81c67fa6927c1aa54d823193c370fc596d0d903214d7967b905292f4b96549b3dbc9b47d
+Qy = 56f69b42b29ea82b9f2fc377e874b58ee785010bb7f5814907fb5531789606810b71613a36035cd257864e414fe0e6ea353f398745df87ccf25b3a25cce1c78f61f5039d66241e6
+k = 009781f5d960870a289cc20f6b1af56602e5e12d9a7353e81b89a90b0a9675686f15511157d9fb70b82e8b2e25534f8ad22e14ed518e62a88f1ae21c56d4ab7763808851762d3ec
+R = 0f3eba5ddbb8c127419fe5e8cc1aae2239bfbcd2ab43a006020b96c9e7db832fb09e0bc887aaf24848491d4de935b78141f426875f7dcf2937748afb303ec5eebd01b6a82a8c4df
+S = 17acc35bd81cf24f983072585ee1e096459b408da909fd82b5ea86b77154ecfbffa7fe97271f50b67ca3c29ce704b28186b831300db0aa0dd6147d2d160e4aff14348ba76e6f711
+
+Msg = 10b5438294a77c7e517ecfe8f8cd58d75297b14116aa93e574996ec4acb21837e6297cc0e7e7b5861e862062f192f2206a01b1caf42c6d7181d02c7d62b76c2881f8479449b02d32c6f792714d8f70f0c75e81c7d9abb996be87f5ad9a01fe42b75855558d5f00df392b62ae0d258f3f67dbeaf07208952e679a2c573aca941b
+d = 1023997206341c6147c536d034a9c38b4012035dc2c9b7ef0bb9cfe65e7d788296f055d508a1fd957b2dc7f9eb10c27790f15f30d81670945e54a508c57b70b46b4a09f4c769289
+Qx = 66bd3f503cf42a20cea4a55cab75940907f38fac7fb024c55245f02d72d80336574a72fb248b1b61e3205b31489ed789ee78d88e487db3f5a1cd48efa1487916b8707e72e4be7e6
+Qy = 10b6e4330af0270abeccf0901dad2f8f64f4993ca93a7c5281dfd71c6ec405f9a9bd78008fd22fef76fb79e20a571df16c4d97244c7356e3ad16cc489d3a9b2e3fdcd5f23b48e26
+k = 09137bd8436dd126924943e8599c87f64564297117766580e6344aa3c02056c811fb996f264ac4f8f0cb33eaed5ef8f120d43a1d2b3e5e34697765ff9db4b4683ce5c1596d74723
+R = 03b684a66e92d352847f63196181160db3de7a304b6e43679340eaa9fc828322b5b9c16a1772c981ff0febb474488daf998d4acd867e78019b61804bb675a98cef24fdad088afcb
+S = 02649a94d2bc243e997bdf27be7d6364459c38845c3bc8d1c8b549ad4689c8a4b4fd55193ac769b1da607dc96458e2f6abc602bb4048cf6b0933da6785795d04d10f22e439748a8
+
+Msg = d83a52d43216fdb16b1b40469863ca8eff4df9fa358deccb5ffd18b3e22a9d654aedc98f3dbdc4f5b4e56b4299e25d8a5a38d01b34eb93de382df1ae4d1c7f966e84b84c393d167aecc6f1192c4b42cae83748b1ee3d9147ce7de74cebd122695b455e8082f86e3e488fb0f51b3b7edcd579940d1cb9d045296e5e38f201b7ef
+d = 11ebf320ecf6a908ea5b868afb8e22246ce84e743e1076d6185ec65dd79043380708bf8da4ba802c3b93b8d15509bb7d7de9dc29f1e9fb0f0f2cb97a26698f955b1f7ef668122be
+Qx = 38b2760315b0999f9629922bcdff65cfdee4938d4aab8cc3d200aa9c1db843fcbfeb9da10afbf10280110c49f0c18f15c2aac4f39af35a79557c68eb6cf6afaab973538b98b0a6c
+Qy = 7da55796396e919f9b5967608af06bd01e8870354317e76bcb8597a379129e35bcb69bbf6b38911a03c3076f7fbbe9b179e078b442c604519e330282f6f6c21aba515d6d73c0257
+k = 1c219274e54a4c5e1e1aee3bf805a7002bbfe1c030cd4c8a1617dcea2a14b1d537a64cb07c5a1385edd76f3e4ea9a38e38b458d2c7bf8eb56a57fd33166bf59a8af2e9639106929
+R = 08677167a7ea1aec4de76d1c5effdb5a1655965850bd6498aaa4fb3fa50f213fa4d99caf4145b4ba87e34797babfe614dce6ac21d9c13dd0fcd9802b1414aa92dfa18318c7e57eb
+S = 048d6161a3739fbb3ee1c223bc82a46255d10a86a605f6c8e1934b13f1a8662f30f8e95f53848119c61f08037ee5a2440c8faa11a6b1800078ed476b2a3f4cfdb25367c8dc2989f
+
+Msg = eddf5553ed4db6e8ce72cbcb59fb1eb80671c884ebd68e24bd7abe98bb1f40806de646f4d509be50a3fabfa85c5630905ce81abfad8a55f4cd80208afffb9056bc67d9dd7f4660a5f924af2a3745eec2daec39a3fe36131fe9eea444b92d31f6a125f12125159ba095f89968a7028549466f41ad45668a861f671050d2a6f343
+d = 0746d5c824d78f42a1fd63d8fcca61f154ba3e75788b7a0b87f53e5420e23a935b02eaf67bace8dd8a8e7c1caee30154c2428e0a437cf12e235f41c416f92fb54528865fd4766d1
+Qx = 63645fd3810e2458d15b43287f329c354b07324c0707f19847c544f129e4de1799996f805fab7dd356567970e10eb21d875e8ee7bbce56c666511f9b4a4cca986683e937d6f0b3e
+Qy = 595485c9a7f2a97fa7f8453df13b75682931fae10f3441042199fedba91a58c105df57b83d2a3911a2d34a2d41e451d0d2549b0a0a65b42aca40aaa618c252baec171da7937d812
+k = 0674788e75eb9d5ceaadad9fae036f129178fde1a584d73cf284acae3b4cbcc208ae7a5d35aa473f4e1201c19ee5bbe685ff9218a8e2188f3428ab45bf09b6b600fcf81fadd8d69
+R = 060d6dc42329687012a93ffc5b846b4dce3df46ad12eb61437832f81f4fcdea7392582fd75e701e106e5b83521759da6a22a21addb63b73783592d3f29347f3d484e05c19db148e
+S = 197f3b2d4f3e10425f4cb60dd1ae84fd8c87f62a2cc822342d5f0be4f0841623227c5cb0f8bf83fef483a061e30ecac86cea0210036083a99fa1247b49e19a7f401a815cb68ab3b
+
+Msg = 3db94335f6d1a125309622c0a9d71bde1da09371f0285a93bd0aac255fa8f10a56074e0f6057f1b1aecf2d86a2319590ead96a2ad1336fe844e09339b456be32374ba2e659fbe9d0f2cdd83444d117d2ce3204ce4b4294dd05405634b84747ffb4227160c4e5c2c9da9815b0c6d20f55705f16cdbaa13d107ae666d707ccbe6c
+d = 00670e72ac2de50dd2cdd975a6cdab10ac45e37ef7a28c685d77447051496b5e161f8b1b93f6c7f32fce8ea05e94ed35fd7cb28c44bf51ea29cbaf5aaa31d6abca30a89430323dc
+Qx = 54db4acd0815aa7ebec4f7661d80465c64f1fd4147507549352bc07dfcc6041ad309bfb1434b60f73b3d61ebde91f849004d55257e98b6ebbbeeabe960f9429a55a36ff75c1124e
+Qy = 5b6f36f76b3b3c780b6a70bb8ea150e9cd6895ff6a6765a3516acbb4f5efa91434def52dd0ab81f618ff28db10fcf39264be8e7ea76e06516335ac5ae33ba5393080f114189110c
+k = 0f74a0ec1a7496043d78891e308c82b4660606642ea669e4406683d44b79dd6e6a1b810292bcd6a9f59bcc2e590518bdf2e9224755654026d85cf2a3d9768d909278448f0d63fe3
+R = 047d808febc1065646e6a5608d62d1445d922084487a64e9ced5fafff2977eb3a7e29984230946e3fc77a766820747122fdbbb9100c591ad7c9dd29d07efa2e8a43357e3c47762d
+S = 04dd6c8ce75bf2792ef227cd5a3102d30a9a31690ff5c21354f8dac9f826c86ebfaa04653f0ead103b1c8ea59f0a78f5d4e8eab597ec6c028ebcc57f4ce4103ac14579bd6e15166
+
+Msg = 69166ba40768d0a3930325405edfd85f3272f7b8e600b0b319f070274c91f9f03d0e6ec4bfc7b4445e91b87cecabfecf5e77c7301ee3c6b0affca2fa02c92216698705eb75443eecc25438db2d2fb4b24f4195d6b9c05c53e0868d3e58477100607ffdc31b18c40b4ad7202bb034e58653daec0f6b33c024d42a3fc84bd8f86b
+d = 0369a3bb96f884983c23281bcd04e24a3e5f6359f81e3c8e46f3f6b865eb6bdf98a630e90646275c587e41b546d3ca7688cc207afda15cf9b25cf83bd6ad27908647f3f9de59de7
+Qx = 0eb02f6e741b3f83a9dc50853828b8a6e0861ffc644162515a264730c662ba388ac0d705f8b36f5388894df5c1bbc3582c85de141abb7712caadd2d616da589bdffdd9258808a41
+Qy = 5dbf831f450da6f8e503c19a7788c1317ebe556a458e2bfbf3137f986c9c966a14ca90344be1b76457159c9d70f13af7fe0013cf605010a8a3b84bc0fe187c7d93e4cfb2639de57
+k = 0ce22f7f2f01355280ba2d2cda06a55771e66f598bf79c65171e08a98f1d954e4beb3ec77ab06ee60c5fd156a7098023558e3d630641579cc179739bda6d860f8ba1d5ef717ebb2
+R = 0ae86b40d10ca45c20bdb3db55a6dc12e9b75754679eccb44c40fa57351c23c062282e1da9e1703176e4b8f7f224982f2474494772a20269c43a18a7a03fd12d8ebb975b83ade0f
+S = 15ff7b34c3316d9e7ee3d7b48ebf97d98453ca32f3fc67fd08761d93cf34cfa5a2314fd0752d263c3eb7cf842aeac395d41ad3c04c1a9d3808b4fb7489e880d130c35a26b702952
+
+Msg = f64cb668b72f1e6dd026a478505c0eb33446ae9a2993bc7648aaed02e172fa9a0e05eeec61e756ba246c1dad7e85d3f01baf734b1905c5bbd1b08d833c2cf1e079eca75b866d705c407eea8618d23ebbaf269c7185984b3bd4117ecfb295ee6b47eecc8d3a78bb96552f6be314656f91caff793838226662c75cd7804b6bef79
+d = 026717b039df834855511815d5665ff9b654facab469390ae257b7f0eb4dfe66ea0dc037242ed0c13bf229b8f7ff26da9b55fe4750d3451c62804aad493c179ae45d08ece5af085
+Qx = 191a6d1ab9cdda2d593d5598a966efff829c04c421804c2297e658adc5c9a6092e146b25c730ff7ee65cb9812ac9ea0c18dc6b60deda948b4b7568e8b8e14411a6969d7764652ae
+Qy = 3744af98387421d958b26971d21928b73bbf5b0f0ef183e9f606d0348fa715f153a60b6c7991dcefead2ebb875d0c1dbd3665dc42a241c565ea0fb0e6349b4319c3de633883a516
+k = 0dcd28cdfe9028a4a6df1d41019bc58e4a1540ca94b717d258f2afe8bec560f3028e15ec1e8bfd422415961516659fa2b006256745e85e488c359e8cbc94cd2592bbb892a19c45e
+R = 07ba5911415a3d21a3d98b400f61eb63ddda689bfff0c8c3ab83668b1e4bf8a703c853d3585b8bdc29aa2fdc41d5e7534850f4656ec949f0a13fd18295b662c9829723e5a7fe3a1
+S = 1b027e38283d74c962fe0e7b58dfbf5e21ce1d9c91651bc98284008f44fddfe4cec9441994e690d72a8ff3ba2b538718aa678e7de046b653403f3b7c064ee07c9c3c6d23e1b068f
+
+Msg = 51ee0b98eb6a3e3c1afcb35a33697c048dbf61374629ac5702a57801fafbea4d6fa5a26c9d1b79d1c58257ac0106387fab2d4a1b7f8c0dadcbe7c830613531b3c209bc17f792bdba1c1fae1b7528aac53dc86c2094b40194577325c05d2258303a2d17c854e7449489c43991b6877a50692a6340a528a6b188440ac0cddd4c4b
+d = 1d642f2d393ed4abea37173e4a79534af87adf534ead4a0a1c46fb047619221e3577e6b8bcc776114d01159c736ab78af3e53feac339d7afe58be8e7a8ed290f1dad960f1b5de94
+Qx = 23d1ea50229b70b46578df6904fd528e9930985426eb2f1ce10eecbc0c1658395948380c4047d67bc4072be2a2624d62a301da41a5265f040642d1937fbbb7cbd205e1db85b8685
+Qy = 625c82ccff6047b1ef4b08f1913f7366c4f6c0312c21e5ab01b598d1a9618cf5c22cddc64a4732b477dd5c06e332b846c8015a2e5a195326bca46c29cedcc2f24d37ebdb7c2eaee
+k = 0c9066831d61a4192ad9de23efcaf578a5d5774960a2b3e3e292e0decaef62d1701b86ec6183d8e17a699d418ef9d084b982c97a55bd76c8b038ac5c639451096ca4d331f070ad8
+R = 005778acb38b1961195d38463abd9c19d9e07dcd997f19676633fa3c44caa44ad1a9bd63435f3138ad8f22a731e749a81161c5448eb462fcbcd69ec2255cc2923ac697ed319316c
+S = 1a1aa90113952608dd17dbf391ed56231ecfa7d649f3274774ed2b6034a2207c05c6d8b6cec480ae27b58495a50b1e5b74a17ce6cf2e43aa273c2b813c0e6c79976882b7e4b1c93
+
+Msg = feee50aeacaccb6b1c3d95c6524044edb78322ee836d8159c4a4c2cc6982480567c4c6cc4806a564876622266e1ebd45f2f4be851b79da025bd57d0e6acce1ec1c8c255eb89713a1e4897d4ee0f7a248b9d4bd3ad5dc0e57f60ebfb65691e164bc908956a019083e923cfd33dcf37c735af3462768a1e14a8051d7aee74d5228
+d = 08cb70be29e83f697a3e2f67d86f1c1ec9a163b5335cb4a06004b6634948bf60b8ad9df9b27d2bedc4975265ce44a7884e57082d521320ca4372d38fc77b18d3fa05ad8aa5c43d6
+Qx = 4c042bde9e90b38b48e60551d832a7c80377a81e8c5b010d0e491cf765c432b5edb0771aaa5f672edf3ba108dc71459d245ad60f3884b8cf33f8cf797f36b20e4be39c8389e66b4
+Qy = 75f2454c41c0323ee1a640755077d36a65be7c2a014db36719ec217e21a9c004bae5befb499bf6be67e82d3da70475abf9dfb751c84c409fe838cf1c6ae109d27f24d75c02cc5b3
+k = 186f16dfdd7a71f20a5e634ffc465356914bb52286d3d5ac00f3ebc02497112fcd592e1ecb2ebbc819e07ea092e465e66f3e58da7a2ddd41c8787f57c135ba4c168539b4743c3a5
+R = 1c2140d294fafe3d9effb33ce73bb7e5485c93c7aa9d33b7535c7053831a1dbe79075713794c87e52bc887ded969d2dfa6a1e2630cff96760310e04cd2a75be6fa020a12fc84d3b
+S = 110aa165707b7de1b3a8e05e4502701abb5ade0a27deb04fd93c6eb24ed2b67ade6c49d78e874d25247e948f704d3c5b925f84c5b07c9b289c4f8507e75d0f8927c6dad6dbce885
+
+Msg = b115f7370d6a93a90fd9dfdfb292956be34b61992ce1fa5627c5e928d74bcdeea66d4040c473306a0070fa8363c4303bea32f73ea3639b5c6676fa5a1d68a2cc1f91f00580d7453a23ae70af4cb1f1657aa82c5b305374effe5d67d559e46a6cee6360503d21070506f1af30bb000d2f2f85caa6465810f89968f33abae81cb3
+d = 1eef463771f9c6285f3257691dea0844687606d4dd00b6020517f190891cc1be97cfad21d147ed8881b5a6e19b22ceeae30e1132476325f2de0e9af2e14c80b8c780a9d2d6c96de
+Qx = 24de3ebe03d2d91b88794a77635aae6743e597410ae10c356a51e3af88fa7f9c4d648c7d1fdb887c8313914ed554eede282b24a2e66aeafcc0cc96907bb2f3877eeb97df491bef3
+Qy = 1ce1f9fd4d7d3870997f34f54f2ba8f08ac94ea94f74a766f2dbc02e4d5149802e3135a2d762e3b8abb01461968f1e88cfc8c7fda49c099e392e80d57f0c14de9c4fa1eea25732b
+k = 026b545702baa340fb6d1bc2bb96f7fb1a77a2428cc122ea380a258c747d4e0625bbf4e3dbc2ca2f15bcfea92f2417cd5d22f2bb5f38a9ba313b3bded506d3e570dcbcb86c2debd
+R = 091c162d040a12f08a416296a43501d92e2ecd6be302b5e1754b9ec119fb8a572626c509855c7c868a07b263f66070ac986f95e4c83150a5a492d5ea8a7f8ebf556c17ad2bcc996
+S = 00c217fee7bb202d6399f6b1ae4e5811d9361573ed4fe1b3fe5d474cf06d0236d59dd3580145dc0bc7632c721b6463c69490a67d1be1fae99e34318af6df939f9f7f36a9bb8d5e9
+
+Msg = 726782eb0d9720daa64e4a77b5d8dd67a1a193f15eb6b5162e3d89c925ba63b7c7e1c4bfc8d6f11915b0e14d16ab53ab015317bd5958b0beb6074199e05181915496575768d026c23e92e06016598de008c3718aaabcda8b68bebca0a73ecfc7327e8d3646106b7d114dabc46cfe56265c326ee56fd2ca87abb5bed8f997c735
+d = 13bd452b0880b101df1aa65724fb60d5d85b37ed5419027481661a3617e0fb37bda1151b9b5b41f908ba832011f7850b75a07b678e5b8cb35c5fc8b94a625e4398cd5ada2b04cc9
+Qx = 31d88b62d2edd5f6ed29258c143bbcb3d29413afd8f86873698a9efb8d2021186415d301599232989a0df5ea91ca222c5781314f200c708de30751feadc277d50e64842dd355ba5
+Qy = 1c76f19ceb1be48f5540265b8b018da62fc225cc0d2d1675bf7df71456cc8e35b002a220e2e80691600a2c1ae31e980d0cd22b4741c25bfbd413f10b375a4d8adf70a65c48ff006
+k = 1b9235221a6df49e39b4cde6650e994f624fcb5084daaa62aef54bc154949f4da9074636c44f50ea40da1a3f01bf67e9b62a725ac0537a4e37ba33fdea8ba8b2286bf82901a933b
+R = 01dffcb5b5eb23694da4978419110ed2bc7961c571a2e68daebe21e598c8b483b34f3178978708db6d78455cc1fb4f73c5ab7607cbb4f05d4d008c7bbeac88562fdaf7a370ba394
+S = 057018fc97d7b16d69af2b7dd4a859f09dc178a6025e1bd6839ec7c75c0383c59eee7079fe61aa6bfb3e2c780d4ac0ee074e6b13223c239aa60ea1187ca4937864f89e2c65056b9
+
+Msg = 1c2418243fcd89c6382b7c3b2a8c341f26d08174a9e9296c4a5c98c5793a0fa48dce51e30811a96b515aa22bf9af89a43de06d696be1e531c5dece1f69fa6ecb7f20be063c602a16454ddafb14385ae3f8246c3f989d0566e06e7ed1864502896ea19df8393259c4dab3b3380a4a80b4103cbef4f38cb69198b7cf74ce94883b
+d = 1288141ec2244e4bb3f62daf4ee588aed09ce22be55e3d42e9085a947c1f8cd16533635d170bd64ae0b417346fa4670c25d41387acb2a8e14407a1931d9f7c5358a14eca40974bb
+Qx = 7ccb7b12a7d6997ed2a11eead3278a3f45ea284dfda8e17f6d926ddd6881a44d02a0f7504dadbbcb0cbd6b85c113aa0d3b4efef1ca151cc38cab1aa8360a6d22e3d6fbc0ed980d3
+Qy = 31b85dc2d2096bbba6c465629ea09ae3421cacc5581770ce3479070f23b3aa938333c7c691d9cb93a4533b2ce389ae34dbebe8f333cef530abe17cd21448f701608febd42d9bdc0
+k = 1e411ab53c48cfc1ef9eda97002dc9181a78352de13fbee3bed86cb00c10e7406033fa0ea97b50764b0eb2dc6eb8ea83e47bb3150ecb9437179c124f15fac6ac19b0c8bc324f171
+R = 14420d78f2f9f1010018848b0442ff6e6203c1dc06a4d523802190f462ed3c11c7aa7678bd03ba27df01cacf4121309551877d3a2bbcfee116c59926daafce55a4e0a7d69c5c938
+S = 16de0b369c28ffa0bd6ed8802a503929cebb5c0a4bf0c0e99b14659b48aabfd08bcb64bc2e39855d7d514d7525b3c4dfd2244f37019b5f86254cdda599bb144c8fdbaad5525cfad
+
+[K-571,SHA-384]
+
+Msg = 1de4b642ec7220c64b91561caed7832044d6e811ac909f3b199cceb0d8a7db91bcdc801412044f5c34b355b95a2c6170fe497f6d5259bc20715a38cb0341c88e93029137e94d895bab464bca6568b852340a5c5d6a225475f6eefe2fc71ffa42f857d9bab768ccaf4793c80c4751a5583269ddcfccf8283c46a1b34d84463e61
+d = 01fe06b94a27d551d409b0eb9db0b163fadcf0486e2a6074bafe167f9a3b4ce8ac11f42cf72f9a1833a126b9473163d29bca2ad139dd1a5e7fedf54798bf56507326fae73a3e9a2
+Qx = 38d4dce42bf8fffc39a5b6583a1a1864de288ef8479449d599115bfa35b37954ab288ffbe81e69d58693e2c8c81639df12e4b36f62b2ab042e92a0715b518c63d0ec630051d4be1
+Qy = 59c72c0bfb0ea1ac5e2fdd4fc380d08037a3d0eeed4990ff02e6cf5a16817ea598085e28f8269da86c547e7b34e16a06724ee73776529c5b5dea4ce3321fb168827ca1cbdf8856d
+k = 0a3b18c8c9f17badd123c674869ff428d533d2ecb8c74f9784220be7a90dda591003df5259c5dfb612ac7398aa04cc9e82863eb0cbe66b6e7f45dd15dad252f74a538d5f4354c96
+R = 09c368c80f697c1718c55482b2c6c5c0edd7257a3a53f7193515629aa40a9716cc889d41c120516b54f3a106a171082364886e5d3a1e9482a103f072988f61de68f034d658bd976
+S = 0e782ef47b250f40c56e3ac4de112347174bd59fd4cc991a2b538ca90cdb222d048fec62e2773492a1d327152d1d6591740706fe2f8e1d65de888d47fdf173b2645813ac0fc3078
+
+Msg = 70279be7d7ac72a32606642ecd81b5d4d0f95fbc3c0b07d85c16adf2788601e44dedb8e55e0f9e0b4ca3ca35f5be7511b0e69224a05204af67aae11ce154af6d594d47f6e3142ad183969544aa95cae1edf42bc699137f60178c12b10a67698e37ab9f3edbfb3acdf1b3513d62fe3db33b16cbb4e1f9dfe732c107f9d0c953f6
+d = 09cdc7e4945c485a41728f83d5188f539e372ff4fe38fffcaacbcb4522428e4f93ef4972556f4398fe17bdd885768f0fb5590df495badc794d4d274e22f2f4a2535555922fa43f9
+Qx = 3c6f046aa3007ba7f883bc1e0bb43a9a0a1daecdea3e2b6c10b2481d11a834af241d60cad7cab27b677c9ac11f2e5b5226c0a3de13029229af00e5a092340af9b230e0ed992acf4
+Qy = 6326ffcd62e1a68b63ac680a743130b1440bbcd3966207dbc8a8f4336eb6a7986aa53cfa4fd7bf363b30706b4fae01568020b41caa70ee3d51db982de66b0ee39777da3fecf5b01
+k = 0c717523a308418eeb2aeb816346b74149d56b9620774cab582f01681bec73adb779bcc7462fff35685a4e1e114c8fba474c68fe2650344fc9cf610908966a9dd1779f76bce0cdd
+R = 0061067f377bff6a9be30c9c79d8abb7f54cc8f09eaacdc190beb27b1e6d297cd32b043b31feb49958745b78e42ac074b8722e1a7653bf03611d87c44fd3891ae410b23a2140b83
+S = 00edbe756a5dc78c8a29baac9e2059154294e3adac9a5adeb7b27ac6e4d4086821cbd55467266946ed8f6f03abff35b59434afe84067c1daa1e0bb62ee7c56b85e7f831eea99047
+
+Msg = 4d7e0ad520445b6a5cb46b7c77fbd367614044ae6004494c2b3a89089287e2836c73b799cd8c90139eac427ebe335804c3788f3728ffb8edd7f49a4bcc76a9e24ce3c2299cea88c04645b82033115380f81b0c1d823e470631008d350cf0c0dba1915519985b8a389ccd8c809dbd5bb5051a79e631916e0d052d9b6cca18e0ef
+d = 02bc753d007c4491cfb8ce0a6c96455acd16d37e02c982db216b8cc1afd6d10c6be4e15a3988b8b8b86b2b5b59a5c1939889024849317f27ee08a06bd8e7524d4ad83a1de208564
+Qx = 0ea922b09e902ce3847f14d3b3afc5562dddf15811cb2e7b9e06e1b919d795f8451a3dffcb92b418d30bbbd1a7ccf827ea0f1f6554387fa2fc51755799040133d7a655c7800b713
+Qy = 1f12439a0c0df9f6ef08e89eb1a62e2cedafc0460030810b2483ad9427c48dc061e4640ebbd9b4a398841c863a6e3d510e5c66934d66b317b1640bd05018a35677c6ac2c7839706
+k = 0385f9caee4731627276875dd8d725fe79626c18841562e8a13fa7531c7be9adca565c22459d519d643ea22478d7c51b4c286920b050bfa54ab7d42966e389c485b52cdb4fa1a0e
+R = 02ac84262fd121bbec43e81021c0f0610fd2fc0b26d66581ddaa78714ce58be46965283851241d792ad6bc79af39f09d2d4bda83996ab41f1fd206b8293cdb6c4eb9d96f39efa25
+S = 1d9c9bc330adeee8f58ebfe8c1ba401d4433efa04a44185b0e8e20b634691bfe058770d074289e636af3e96c118edf31d72b5766c30f6fe84ade42f284fc7f2707bf27b3a309638
+
+Msg = d49903f38b5c9b17542310425e59377f61f5b4f4740cd97371ee2116083f7758e69e7e2c1b0950ec6b76f96e3c91c721d6f2843afde8c7505a559c8a64bca2e665aa1131b75bdf86fb5b90581c7d3b61c2cff88f3fccf356ddf5ed282e27727be061b6925c51ea7f1a495f471dc8a5ca1a88bbe29e92338d3c9361460398965a
+d = 02082c6e61d0d72f040905d8c1c20d47b029f41ec68d6cbf43ce97c3b2a0a770557a33cb803c432cfbd3958fda30ec1bba77a6613c318597a85ad02b26c44bb77ca96d9cc1194ea
+Qx = 59ff339d505b307e05adb45aa314d47f2450e1b1aad840b5550a67c11940d0e78654755a8e28fb651e12e48c66cc1ce0338114bc1ffb00965b342ef3a3caf495f1d73a69c3f3d17
+Qy = 724e9474e6de57b9f8cbf6f6bb4f73f5769e6cb0e006a34c2510b379995c9e054cc4981c709ca85a3aebdf29090ca07dce5bd3c313c6153b551012d72a8f84600350e8754bc4abd
+k = 18d65ca6c2ef1fb32dddfb9ad4603e03c7cb1791a9ec7b41266cb68b6048aa111f5971f3cbef3f0dbb9ce409b59c31cc59bd6f100ee5247f8c36f26ca77cb252331fc3be7346b5b
+R = 12853f9d695b8ac4431c1ccc8498f3fc4916eb6a5e66b3795a3693f3f5a29ad13e58dcdaca5774f1f295e2d2d3c63c69abbcd9f388a3383371028fdcc8bd77f7554d6aa3f0431e8
+S = 0d1c324afdf01ea19e9453d2b7397584d773716d6a08b6e38f9a9fb104122ecfcc9de7bf1e5a6cfd52a08b7cecb002ebc21798d474f035fe7d4554bf632f237bce14aad88b47d4d
+
+Msg = 0e3f4afc3e7b25c1bf2d98098a5a87db1224d9bb45adc6e434732b8722a708ab80a1f3f6ef3c5aa70d2e1dad3e4416b12cc59171f05736c4b58bd084602c344f2f0bf3cfdcfe04c64e87597a99de23ded64b33607f7c273ec321f6462518715b11e91361e89ce5415bfc2ef520bfec378244a3bd2a4b9b6b3d68815f2f75baf6
+d = 0e298c93351323e2c5304015a4878997ae4e79d1c32f1dc64262e534d4f2c4b3e222356ffce746763373fdfb936fd330d3214a18c07f1205b20c9a941331cd676040ba1fe3dbce7
+Qx = 6ee4952a83477d89ea05ae63d5169cb0f7c7ff22f15728c6d69dfb30d1f28158e2667f9342cfd9b32f2fd537dad47c190d82f72c03043f2a9c5d97cd09d07ed4c35b96104042554
+Qy = 26d5935dcebc0ed5a07b7ffa50de3c8aac309dddb61b8c560230379696d81d72bda3c819c46387e7f026b384bb0f7b2ca90c402bb67b5e37d343cc21a8d1a0f822dbb2766030d73
+k = 12d23969d230e0e2712f96b11e196202dd3e6ac755c824f92b9c765e3fc808d4e7236c8a3c06ca2c8272c7ac953fdb936db30d892246cbdcb7f98c43177e1c30afcc162af511364
+R = 022f6dff5bc1eac1ef568588e2e512103cf56ebcb610e124a125fb004064a28291c19e83ea08171bd1b14ac729392c7c46354e795d63e3bb087fd100642465efd817b79924408a1
+S = 1785e1fd773446e3b90b8704cc2723b8da2f99d1d699e817c3c4622015d178b0cebc19b3a6dd972f75eb3828a386973c0a5e67ca192d69f1a84c825d1253f1062a990c3f1a947c7
+
+Msg = 8fe32671f6927272fd3cd8dd4e34d44d27fac8c88b41bf9a48039e914990bf06d1633b38b9200ce1c2a275b9c55498e5da2d0707322c3ea0a0fd7aff598fb801628264e13047c8008153e8595a0dc95d54e70b882ac2ac9314d2b78e7b93922da818d7075215e354708994af66958954c92c074d132dbb2488e5a531c755a8e2
+d = 104f4ad56594c5cec2a988c5596d73adaa5a81802b40110dbae698ddb1f0b271fd1479c38abcdb9b234e69cd0da8a0328d2135c287d5b130a09fa0b899058e7800eb2dfcee95c1a
+Qx = 4e8151aaf2aa6a6159622baad134be41c404982bb0101e820eac8f0a52166546c53927d9b419604e9b025757eaffac526d4fbebde5fba0841c6812dff2e9bab5054d4074a125ffa
+Qy = 4413639ad72d6eba870e1760c71966544f3f881f88880fdef1edeff47cf6c235e8dfef1eb1d8df51f9c48b985912f1f70b61fd3d4b859e052887560872fe6e95db0f435778d5c4c
+k = 0cccd1bf3424d8bb0513fda3db93e81bd34175d84aefafd26b37eda9e767618247bdc94ed2b1882bcae4c83eafc30a7a4a80806fda10a5e70b8827287eed8eac2721939a63c2175
+R = 05b1460e856548287683dfbb93efc869e80333a9ddcf292e2fa3b3c8d430563a01340685c6db1059aaa8b298c8db9e8281f36e3a9664faa17f413cb439ef24cbdc1a4d58872ff6b
+S = 0c6faac191c95738f7c6ad0eceb035e5d22ae85e4bd0e27f2e65ab293717c0491be3d1b5ace80f4cb4bac7e33258706010c2aa48d84c9e39c95e30805fa7669c42bad84386f7754
+
+Msg = a8fa01136a0a78313a5d160c32fe5d1805eeb3730c18ca0c47818e82c48eb4c9e5b2dfe3ee5facef9ec59b68f4e6f3213f77fba9f8ba06dcde546ae348d343233883894f4423331b536f62373a495852977a51cb192cfbec04b5582b4ece69f345979e234de32da7a120138a057a7119735c4cb19099bf48bb202e7ffac04def
+d = 0c4989bf33b3136bcb4ba67906eaff2bcbc6567635aa4b057acb7353ee87ba3cb4cb9838f8f679729d5c6ed98e6c4199cf58605f009c6873a1b8321f83cd3c0973b7a3cfd9dbaa5
+Qx = 3871c7781f2b4f653f0d49a224576bd1e5363d5171bd21da89f590f49fc212d8a57ac8a140d923c2949ca287bea803afd763f15f909c099a07297e8ba1b37c70e1e8f0fd1fe9d1c
+Qy = 5806bd5b4858ba0814da2167d232d55bb5c41ea0a36fb28a0a151c1b79b22cb16613ccd9dbf92174e42578ef88f4da6eb44918acf427fb7e4022da3376243e75410ba6ae012ddfe
+k = 0a9eb767077886c48bc54503a0d2d62f0192d3581bd9ec253107092c22f68a15293d7c3e7aff56282f0cd35e86a2b3c55c9eec079201d99b5f49946780ce6aa18b225c2dfd72cf8
+R = 03eec6ffb390ecb2af4f5ca17fa8a7fd6938667b319f0f61e5c7523efb77afccddddb5114ca8c461b1c28dfe7eb85ab156e24e891cc6f9511d703e8b3c8443d04fd8de80f5d65f9
+S = 10cf3156cf71dafea6a0d6abbd503d72b13e6a684076ac900f390059cf3fc325966b3548b58e14a82bf291d9689783b899db7d4baba524b0b63d31f9900a84fbabc2ccad95742f3
+
+Msg = ba2d83b21c783d6ef2f3b7b10e910a418a9b9f49ae0fd37990335b3a3d15627846c9a12a1f31a3d0e062ad1bec5650606ed4dd06c30e50c1e8761a29f4ea1a20f74635d5dac22e5b787ac10f4ee82b338a641484f91771c128c84d31cdab0a6b9616078c898665655ee9dd4ae73d33b94bf091b064928b959623aa71ff73b4db
+d = 1a96f2ad56e31397e236cafc108087479c9823589a5fbc3dc7488d0e5d1199cf245d7f21f524cc0e8b47feca14c93fb760e631434a91188b32965053942f3bd39b3714f9d6f1a11
+Qx = 0195bfb66e20ae295cd22d59b27b3880a890fc44ef5c720b568bf7f72266293841dcf0572063a96c62736d9d4a9cce31b10c03016305a409858a79070477d3e989481ec555c8146
+Qy = 491122a199176e2492e07fae4ddbf02d2a40a21bbd99b8f742b546db2018cac27fb4b1c03cff55f61b7caf13b0f3b097ffc8e1549eacab89225e0cf1e96b268eab7f9a1a69258f1
+k = 097e28225aee5bc9a970a150502dd14bee900d3b040b0da9cb52f5824e66af46a991bbf6423fe1e089cba47593af555b07b45e47b0f4141b0412ddf6e91153213c5b8645ae7bab2
+R = 1439928b55917e93d59341532cd1f9d09de1f6e0d9a04514bd4b692603f2cfb75a579301b39b8cd92fbfc8832839691c23e0ad3efd3b4c7c3e9a366c1554c6dd13c50dd087b3055
+S = 1fb432e72be6fc524a7106b21d03fa71852c18c67edcb8b265db3b144214e7e6d10caad91f81616e03ae7913fea1e8d11e90d54b17705e8d04c8c20f0f4f46f117cc423ca178ff5
+
+Msg = ea2d5f4e9797bfc2f33f0fccaf530db2bdf8abcec00f09a0338eefdba318221ec0e050cad1a85c3f76b784c6e8c18da2b062f333eeff18b7b781e67d6d0a4368b8231a892e0f4103012348e5df53ac745e4d34e2cd1ee9369f97d4801ff485fc144b2007008036bbc07cb1c302a00054b54f3713919191e1d5052978c9c2895e
+d = 0c08ed8e0e0f8b0d0714b46a2164b933f8147692f18da97e5a108c44d5a5cf221cb50536e41832b83bff4026c6df156386235cf5e3e9a67b7cf9b2fa7707c5e0ff33a91601b8e34
+Qx = 2d516bdd1914c83aec1cb242710ed79efa61cbb31dcf8d238d8f5e089158b2ee2bab407e01996a1621b1a869a98227c12296cc2a71c1ef2d0f26bd6614f2ac77008048abeedafcf
+Qy = 151474bef5965c455eb95ca2ffe1d589107dc251d22635f4a9fc7270358b64e4d2b81666b60c4a5c49902b0fa9963197b22f90a09cab97007842816f64fc49e351710db84980032
+k = 01125bde6086753b3bcf29b7d5a4fb0a8abffa6503b4f0b39960eba226062bdade57e4d73e8c1621792626203e83fd5c231a53b0ce10890881460802788d481f233466060f73359
+R = 199a1e40229786b966592ae6e275874ace23d5605d0c3371a4f9eca7ce4858927958bc1c2780e9f2f79767c1c72117c79c408f972006841cb621837ac002cc6510e0432d99a1f64
+S = 17f4e5e23e494ef149e4abce2d8a1ab10e3e6c2cc93998fc63baed6565ed350b220b282855e2824f398ae76b8679201b43450f62237f6fec643ea659e6c86abc24a63d82d9bf219
+
+Msg = b2293b0a09f41decd9d8e637b1b08c2efe612f33c9c0beebb6e05033c6103b958f8aacd125d7c810b4c287349f5f922d2c6ed554be597fb8b3ba0e5a8c385ed8ae70d5ae19685298f20e8d844fb5ad98db12ba7e5f45baed9045c3e86b3cac9bd55b614b82fd075954fc59bfc6124cbd68edae988596575f379d8921b594c75d
+d = 144090a0ee38cfa21fabcc24d35139a99656911ad4f6dbffb77dbe74e7993edfa9fd63d2c4f6bbdbc8ec21ba13c9f4a3576b5d6e3abeab5af5ac81b1f2bb6d4c42dde645d854d9c
+Qx = 208729b3c7abadfc221cfad8be642588d5d1c20989fea731cfccef25886905e4b1e61cf9548d89c24f5706f5243dc8aa7d5b2675c2c6d2755ce6a12e5b12c28a2cd9c597b7dacb3
+Qy = 3db73ee445ffc0f6c77467f3add3b1e97061117e221687f5589a030f5248bb959bc2ed98c9fb66da8679dea3949b77652dcf83ab9c50a00f6a9c22bd8d16e093b2deca4b0c7596a
+k = 0adcadb26626eb9f8db9ae98c6808840b65d6f886a3f0c45f0b993a8bc62bb5c08dcd87940dfef4f220f5e50234fba3a55e7127fcbb967ff78ce4fd6938a9bb653747116541cb85
+R = 18f7fb6ee028c3dd754d6e7b687560fa269b5a5fabb1d98529e0a27dc66bdb1ed79b7b5c64fb71e767d9497b9255f26b8150b9903caedb25f51594f5b7ec2870515f701bd68faf5
+S = 09ca9519388402d5d96dd9ef2d4ebfd0ebcfa58bf8c1970d04851b2409671c9d5e4aa833555df374469a4d277aab93b8df8d553399908c930f81c2d9769f1b30a13f61c02b16852
+
+Msg = acce54270252e7d9e983c08c993cd6b7e3caf482a9149036afe4665bd3d0662a6818047187872862d5718b8ac063477f693caf1a9baa8bdf2f36d411a796f2b46ab56f66bc94924229f8264016d6769c85d9bbb7d6bb042fefdb8fde1be026b86af2017aacfe38c97309b4689b23fff94f1de880064f1d3ad9d74dc804c41f41
+d = 1df26b672b2e3617b6b6c631d3c6be0cb49c0a690de49643e0f416215bcdaefc03fa9c708471f1d87476d58c8f147517ec8a14aa945ef001fa01984d5c3d81f7083ea500558fef4
+Qx = 767ca8fe8f3a7addf01b230b99499b33c83db95db05e1956fb1891fed60406865291d79b0daca0c307a3ec8b1bf2ac2cbab728c6ec65c013e01775ee21a29305e9403f72883a138
+Qy = 0acfb786b09e5185dbd8abf831d12967107dc57a040d7c800d904b530eed1e19a8e52e653fe8bb824cc424d7254532d0fee62e8ee7ce8e871cbf6e4ca3bc040444585b9a4e397cc
+k = 13e5e47048122c8301258c638bc0f00f8f9646cba927335535f68f4f4f51f23ac5398ecc21eb0bfe8fa6a2084e11fe67587bfa791cfbe2527797a4d98046f9df37662cb7e86a5a7
+R = 164b3500ad14063101b6c5ebabba53dc5acb4d6771d3b05a505e6a67727ca8ff73d996e1329c0f6d8f738237ee0f0be415003e2db515ef93931e09bdd853b9497826929eac9e9a8
+S = 06b65511990c061a6d2a97fe2a5053c775ce2bc5471865abb7261d0436a04b79baf41a0a852a57600cd4c6a114b3a8466f721a684aac2592640bc149980545daa271fa9b146f2fd
+
+Msg = e25274ded4840df0d71d3369007118f002b83e2d375c78f7e29ade067db15cce21842611f3f015db2efec57da77cb9d16eb1e00a8c1444d48dfda569e29fca1ebf40a22fc646a9fd44460f0e473bde487634bfbdac2c312f66a1c2982c6fe76c54ac72b6c8cc9345e47cb319a974b3cc4bb40634df74b4ad7e18adfa9a71ddd5
+d = 189918b832e9fa30161fdd927bfc267f6405335df3d66d225e17173af52a671138883bcb94c4403ca3e001fcf09ef4c6488934d6775af2b1da30a8f331579af2d0fbb530298d8f9
+Qx = 53e6b43c0551f32b7b34467d188985600c5c0ed12448f2e763609f40039f92002bc8e70d8dd3e337c3507fc996a1557d5f2fb3132507e49ce653482cdc86f6ca5903b77fa1619d9
+Qy = 4a9ac78a2c23be0841b96cdb1d55862e4854b530f1fa3f469ba9f7185e3f91c28d03c27d9666345bdbc7a44764595b303f49cc43bc2d0e944862913d280273cfd00e15b6b55f85b
+k = 0b47a185140b583c330c64a10d50748e019134bacf153cb4a23753f140a4d607d5771a8f0f535f9c35baae5ab6c37a55f38acd12f15be18d5bd9662383b30e4d0ce487e8cb553e9
+R = 1a2ae62cc9560590177aa544945377ff6ab1b34e7e32a25140f99996c130e170015636647756a5e8522c936eb1389c206ac74c012941269165f3772373047521f69510c7f3e6acf
+S = 1d86f4a6ab2bba7f6305c2df754652bad40d7c273ba2aadfbbe65c07ede4ac0e65fc0a37a0139a6ecab296f58c6c2532701bb008bd9e1ecac2771d9384aca094537fcab47f3ef06
+
+Msg = d8a4aed87c316012482819b03a1d91691f2ad11a2f46082497ea8f64880d686891f7da550b2ac17199c657d4eb9d04d5cb8eaa180f743b87d23b1c86103f9e9bb60f4e19f0ff9d160f180aed7735130c03adb62502e69be5c624ed7bda2301f30580ae0921b02e103a638f5623c02c186e3bfe6ff134c762a2bcac1f879a9353
+d = 0bdcc175eca3a399b944eb0334ff33c4fd130999c8ac0e7b52ac5b774fbad53ccc3a31024f5262b2eecfeb2104b14bb244307effe3dbe8ed25686dbf46a42c4b6f8e34010ad826a
+Qx = 7ab1a9279a8408828c2bd21ae6c643ad82633d636d36fd91498cfee49c8a635313f56993d02cc46da3f5b78fd243516cd23c14a4c8d79cf27dfcb05f52f0cee59cad5646a9389b8
+Qy = 799beb1ada93a48819ab70b74c36d2dcc3c5cca1f7a57ec58e643924c3ceb7a90c9cd9bf7ec762a2c428d16ef431a45cd5d069cd828601f903cb0a28182af2392b5ad12ac3a24c6
+k = 04ad8d2759df82dd70ebe9f3402d3d533a1b4635dfd0024deeee52b32373550f550b9fd4126aaa6c3a9b1f352c40c86e13f78e259abb17f85f0041e0cca9e2ae59f4ee3ba2fbc83
+R = 1cf9ce41dd5dbc3bee9f46f82e4bef10cefe79a87e8e00d002097045b9acd46364560e0fd27b0be6655e73b5cff272c8764b4c80ce0e1c91a94b8d05209a28b553f589ee2fa1b11
+S = 149fe587b144c37df2c48c2b7749c509421cfebab734003e51383cfb773c3ef5a24fbac0255cb807f5b95607121c5848d3f9656227b61d5a14042351de084d9b88745be242b6158
+
+Msg = acbaa5ffc4eee0850075c0e502a70cc7a897a919f5e7bca4e798385601a26f411fdae5466ba9f6b6d8d7f819a749b799fbf4a3bda9105063e74914e8583ed8b31ea4d22164bee6f14bf53afca269b901c80cb3265be32ffd4ca4bc4ddb83e11eff82ead6d75dc4aec8e5c67f35d58a8a156cd1c0351abdccc0c5396c8fbe6920
+d = 007ab5a55a1d8ecb7f5dca2afdf9ef465569a4b0374716f604ad42a6e0271e934b09655e8e2529784b69b2894bb399b02aeeae30e9e7ae70a2a8e56b9e775bd978a04c728e3951e
+Qx = 2df88e368c8162c1dcea5ceee3a4c52cfc8d6121eb81c31236ba26dfd1874c61586d2daacd96cb5ebc7053be57641bf53bf2651cfacf370cf470db86e1470bf285c7166c197e094
+Qy = 30067763f9fa6a9082ea16dcbf53c2b6f11c9ba1817198e5a4e189dd98141ab682ba4de0b3f873ae54efc080a2a03f755efeba3c0ade8ea67228b1a5a11d730302f1eb7c6bc3737
+k = 0d3dd75ec61e0f87737812fe1ac86ba336b1512bb9f7ceac2c7d1a5b4d5dbafca57a5209028cef9468ebdacb2a35988531baa094a1c901d9650f2c5d8e03a1621fb33ea85e2b506
+R = 184a98dec91b9afe52d4dd6b2d9f2d7e3c42e8e614332080aafd2621136ac7965beb4e8f97b222c1b2e5448b79534db4e710331a2f877f8fc2a9259129f0b24d24289495da22542
+S = 0fa384a04c4b0b0745abea373aabc09404a6037f302e234e7a2840ff39c2b86ae37c814e8bf3f3f7cf743748f2b88d02d66a3adef2028de94013c07075fb73f00555aa900337149
+
+Msg = 9a57b63a4f418404e8f5dcf3052b9bc04a4f6d2c33bde8651506d9cbc5542ffb9023292dea463111fb78913ccdcd182faabbff9164219b8900c7f9fb394f7d9678f77b18f8d58526ec64d7c1328953b983a7c416583e05a069cd76aefe26e5f5687b70abfbf9f58f052dc0863b4fc3bef805cc3bb05bf76a83235af9d6adfe66
+d = 1e7d4da72b1d82e17a066fe387f2a0a7fa4c60ab993ee09710531789186077f2f32b42ddda497d5fb57356383e1f96973df043307f0b6519430c3f0d40d62954032872fceb7dce9
+Qx = 37c59e95132f0027f661511d1bedc3018bffa62aad7f44d7370f5b169d683882fca3dd0c4260fa8f72a47a44fb0fdcf0d7776ff0632378022bdd223753c66f98dc04904344ac741
+Qy = 2d7f19468b8e4f32eeeaabd6e402a35f38dbb9f2476cf07881d8bcff170b0a6e1ff8cb1bfdcaff734a32ae9bf34a909ae7fee689e3f1ae777812a45dd46ce13fe648016353c6bb7
+k = 18ad70fb9c5673e5a39b3a1655ff76eb84519555a6cd88e86a26f9448a54f04516c2449bab3f75e74a8d15c69926ac43fe01ebbe7e1c97e73870e3cc4c0ca431cf614f35659e3eb
+R = 12abdbfb2eb08e326289fdf5615057d912749db4f17848c1ac73bf6a51fbe3e1b2732d4eb656715a6c459c6c3065b67b577f21b8eaca7d657c3b3171e8a4849f55024c69487e50d
+S = 09609da5049092e0aa8ebcf10c204de54c968b09b9bfb3eff90b80bc675d557967b35f52e459f37fd198a83a858e5d7f9f5aff8b2ef7272b236dba5857e88515ed471a60bf6da49
+
+[K-571,SHA-512]
+
+Msg = 97b79c76d9c637f51294369e0bb52c4189f2fd3bd0607f91834aa71b3555605a89ff68e84fb5bda603f502f620e14e8b0c7affefafa2f0b303009ee99653ae4550a05315e551dd12a4d8328279b8150d030b03c5650ed4f8d3ba7c3a5361f472f436b200b321e7863c771e20ddd7bdf739c51de3676f953a5501e4477aed1bd8
+d = 15b7271d4319db5743119c8103a7d4c6d57e9c62f3eb93762156d2ebd159980aa57cea948e416717d715a2e458851f1b2e9ad4172bbcc53861db29c3ee0ba8e82617a5866170847
+Qx = 03a5b9559b2058299161770166766aa65e151ac6a22a90205afd27de5eb99c5b1db369ad52f09141d3bf08884b96414c283b2669ec2a2a60c960a2f03d425dc4c229c0bb369d90f
+Qy = 024f3a9cf3dd257043dceefe6617a98e222e1cc820f3e19e63c64fdcf7ce8d9c7af7323c9aaaef4df02e498597581082fa3767c8a38f508f4ca2c1eed6f298dc8142668a0027490
+k = 0c585e425ae4a34f9b7b9205f095ea07599716f1eab1a8bbd934219ad760c4606ebbeb06cbfd3952e045a040b8ce20603aea4f965d1b6e87eac7a61672823fb2de7767e3466c730
+R = 129162cce6fb05e1fc8630ec6c3a16d108bcd251719d89631497177e6fe6d1373f114ad9dde6e04a4ee0b4747f91c78703012e5a058c132d54f2ccccfc0f9326b27d60322b497e4
+S = 140163edb5f3c4b49228e4614bfc6da9f73674eab82678ad9947b2a635f733dbce99ce3209f613e2a75e62ed84db4d7d13de6d789b7cfedc0cb6a028d8316db8831db66c91791c5
+
+Msg = 564ad0e37c9c37a60872a4780a723d08d1159ddc77bd834d74c1025cdf3cbd5338c3fc07a904fcad9b979b2a2ceb1a0139af35e5112305fd662a57af6312624b9bdd3a64849f95f59a46ca8feb2ed56f87f258518947474c1729275c4d89b7dd286ed65f286cbac76002cc63b92a73ab6bd13c4adef282f32297e441bdd8fd36
+d = 07219ea7917d174a5386df985d0dca798ac9f8e215ab2f0003aee929a2dbd91e37fedead0ed95b1e8aabcf516bdf54337b4aff7ace4c6b3179f2e919a49db50a41c9d4d58d4f636
+Qx = 2fd7f6ea770e0a6f1eeb3318b6b609c0e76ffeaa34e75f56910e8f658b70940cd7a5918328473b279f882816955b2e3702c22e0b3e03863f8d99c64f3a2c9d1c68f59a28eaf25ad
+Qy = 6c2cca84218aa019326cadae9639069dd27df4d1e95a4c8e7d7cb426e70e2d38650b382e325dc3835afa719145d16a29e4ff67de37ac8949641f0d140072f59718450a669973206
+k = 03413376b32f18385cced4549e231e514eadfe05fffa0b252732f5c88d13d9c6e0c35be3dbf72029be5e4573b8f8829f6efbf58a12b5c161bb7055d1944eecc93f82c12c5c56d9e
+R = 1c45c25f3e8eef9b92142f12e4119842122ed7672fdd82c14b3c34ade3243a4c50495c06b5984d0260376c4fa44c60b2e34b0084066d693943071bb663a44884927352668efcc62
+S = 08cdac0f4498173bf4e59de98ac9a26fc2c752cfea7a5b75141d4e1d019e25d70a717ac3ebb82884436ebe1007b0488c4ff29fa31fdf02f77fd99535c99b69c9d4e5f432516da77
+
+Msg = 072ed5b14754fddaf54e20da42432df49bef38f4a3b1841b2db457ff86c44880727aca945770adb41269df41fc17f6a687bcaffaa45a3e59070526ed53b8dc3b78cf9a80a85461eaf4b477e44d5ec4c2bab9c05aa747a5a520b35fd09e8b44539d060ba1c3470267e0dda111b15dbb587614a46e1e477127f963a16cf3a43ee5
+d = 0bc623152253da24bf8d752bd78aedf7d5f6a2f889453ccdec14e10753335ea8bea83fd181a1f3680ed50f2324fbeaadae160cc85831750e021f3e44121ea1b1efc29a7d0069479
+Qx = 003f3a6cc6964ab2f6da95c0a2a7b75afe4f77faff16fa28aa67809afd9495cde1f5dce079ec4e15ec8c1a2095a12e8adc409fe8729d865f50ff31ee75d7d807afd2c15cb142be9
+Qy = 76b15c1ce931ba06dd56dd8e4f544425fba4f37f951a188c8e7eb13a2850c93b8ce60f10b3783647a2d053e2764a957656a184a385e95c2013685d4954a2b2aa20e4a15dbc43b78
+k = 1e091f4febd694879f78e83842572280daa48db65c463e66d9a7ea57b82fda531f116800530a03cef2cf7e5be5eeb6e420213ff757c27b8e8a94513e417f4acc62adc02a76a4fdd
+R = 0264c499f7daa6ccaaf191d3502e86458ef088c9bf2ad989851c221364b24a1a3f4404fbd0eb44a41938ac6ab67002faba0bdde7f44ffe6bc10def8317c4e2807c3ca711cb6cd33
+S = 1b91c18fc55635c5e3cff70503e7a49572ba52b11bac193230c88d6eb65eff6b2d9a01f53ab0eb34f5e208538136811157f872a8255b4d249b6ffe021b0c0763cde4d7a7e72b0b3
+
+Msg = e660dbdf3e61af39b83b95d3f1970f66d616f03273f7dddb98f768452b21cd39604a31cf80590d4a5e4b0d4917519e10fd325dd4ab7a52d70d154506329baefe0d5816f514ae109483122b4fa8fa1ebd7fdf1fc4e21e8d278a50c05d81c8f489596633d949c6c8fea96fe91430c01522a5afbd5042be8aa47da04581b2bd21cc
+d = 0645947d981d258f2954558c31022a3b6ba5fa7b675312f794cb61bfff1d9ce87267e4a1dacb7c8fc58624d31c85ebe22f80d26a620fed5df5bf38515e0903f0b69a606048197d8
+Qx = 2d03e05c4b555943fd69a299249e7148e99633b286da69bbcda64e7b06ce9321d62bead7b8d095a68d9a3ab9e9cf1aeb1d8c4904a073c21806830451a79fe7a907b32df15ea4567
+Qy = 23cba4f6f1815cbe1934734a901206596c6f482011f6cb6d452329f9412d2ef4566429e7d35f2d247eaa7849ee141bb16914b64920fffe6b7923cfb19759fed6e1f80d6c40a0ae5
+k = 18955bb752f0af7d7aaccd0628dcf1f52d836fb91dc78b0fecf21ff5992d9c1f891f0eb3c139803b88736ce10ba4733a523854c4ae9ac35421beff9b20e0c8daf90bece46737579
+R = 110a428aa96277c9a13d4529f58ecc57cd7209a7340b4a78694dd9ec800f36c9c306221fa110e0b3fd65b9dcb67307b7d7678997a3143c04ba96d72be83a1cd6b01ef22acd0f82c
+S = 0b7ae2da5cd36006a92a5b2e6369afc2728a93edc845ccb1500e551be361f8658819f7d3eb82ad41d7f2beea1a1cab6f103238a6025acbf03a2b08339841694022c17db8c6c6886
+
+Msg = 8c9acbdc431565feae60e08bc7da113e12372ed373f1e1fdd581f98c8a7b0c79ac4aa42c7ffbc963fb4970fe26c5b5dd314b7051fe971c1186ebcb5650f7f7011a924de893f06961b8c75da7bff331847feead4abd2e8b9d6ecbedac18f4eac207b948e6e4215e4d5cb483e5c66ce7ad788cb89604d3a3e051539094079e7bdb
+d = 14cf93ca69d94ee8fbea0c8da9d76aea092b73073d8f5385b65c6dd4d567fe86bc2cfb8e8be890c3c6cd9abf7dc3a17eaecee3d7a9455887863e496c48dc3e47821bd3d825b6bed
+Qx = 3dfd1fac02ac4bd3e3017a3d94f29575238937824f80ba0b2eec185ce8c641e9fc72194323c779dde8c4fd6e748e09d66e82c82add75106a0e1739f2b977d40ecd3cb15a1eca420
+Qy = 6a73dd31226adba7ed8d08476b5af10a806fe8de72251400a83f6c9f6edf5e0cd6bd1fa8f3595c3ab32b4c4548729c455e4eaf83230e1335cf181cfea6b6bfa6cd4ad75ac3278cf
+k = 176972d9402d5d6c9753532e5ea907f256a872c100f87bd390c4d610bc00c408a97bd55dff2de1ef2fa8b9716e33a5a39bb6ed2ab541848685040656ad0468b360f42c3742c1fd0
+R = 00be28427524a3b0979cd82fea407463647a77ac45c489744a9998b545a13516abb9213ab0d89a2f5f872d927ad48dfa502de95524f94f34b174933f3faa7b554a1c2c3a688a0ed
+S = 1d49594454516c1876f23f2ba0b1fa4dd8bee028bed5524b7635a2df5b8459f4832b3db5f6074cf07c169cbfd9099a85ec2f5c42043c5b851c81a71c87affba34b11eda67e0ab69
+
+Msg = 53ef87d6ac7b9698f40b3ea9f3442e7b64207b140b7f66f73fb7d5f8f98452d30a4e493b6c0e3268371e88e612b818d4d847f032ed4983817d020411a52d81fd2a17b58ebdec199d817c2a8ba77042bbd747a6fd4bcc7e844ea829fd8461b389aa0b5957d92962b6d4e86385a8fbca90b8fac40944607117e9a4ef6dccb8fc1e
+d = 033feeaaaa28f16bfaf5ea9c7319cf4561ba4fc55327a8477b6cd58ef6ccad3962ee1f3edb243f3a04e7e49c8e23509fa2d63252adb186b8bc7e9255cd61fa9bc45242d42da3a68
+Qx = 6fc62c39bdd41ef7083ae10dad59e38dad217c55864a55a6a80bffe2f5e7da977d79db9ed8c9ac22d6f096129a0c680ac93fd77da4ad96e292a19b48454f91c93a3132559fecf07
+Qy = 66f1f737ad3af3df674637aa5efbb844bbc441966bae73973481628e5c2c67cb74553a7c8f2c5fc478edd8265bd6c99d6ce122a245e46fbfc21992b950f04cbda5eb220261316c5
+k = 0a5b86b76f98310a25111cc3d1b0b70fd0c20208cd0bfd8007cb569a187c3a97edd8e716aac938900c3ad8ed3a0d091a18555ab532b50f25184454d84af2beafadf754862b8ec74
+R = 0de2eade32f537727eeb82dce610b48106b277d15d8fbdb77cd312ab9983ab21bed05f05186a5cb2b530ba72c8c68b768c26d942f9224c6e6b9e7827c48e129833cb679c70aeb29
+S = 15e4fb92190bbf8dcf7548057d1bd5e5ec54a6edf54f6b88f50e96ac87ed7a7b7c0fe1e1174ba3e822fb7e7c083948296cdcdcfbdc4bde036a07f84d210001ded91c554ace71efe
+
+Msg = dca1b7a9a313ead11c2d54739d9017ae27f9d08b3544e418aee862bb57e427636cb6aedda28e10f12aa15d2355f4f8ef112a86fec5dc46e6acef693cb8fc37c3e4885f3be3d3ab31ea4d73a0de904e95c7135a149f77b621d642f9bd8ba192d39cfc58b6f19a797c4f3b4f3a87054298e3ce5eda0ff7f44f8134c9a108285dfa
+d = 05613dfb53149bf5fdc4e08ccc1c752b0b66ab43aef2d008ed40f3df40fcbb2938d2c41e3ea2dd4428aeba9059a97efe5593119673866a19d27a2ee37dd357e22b6bc849e7e22cc
+Qx = 7ef12ccf6b64c7ca64b5da45937281ec770ede572b9a8eb685f3614bc358ce550195e74666af9bb54379c1fe1304b76430d1e51a9976bba02e5781154c9bc187a31201ad99cb48e
+Qy = 43d4ca20f06b26d75be1454e96f0568bd740165a2bc6e5b8429d557a79666bb7b9cfa597d392cc5b8ecd180c37f9fe2088d7908e59ff644ab05568d974ab42ec9e01676e1b24169
+k = 10b4b67007af35942216e9aab1d6561bf7684f334a80c7d909a6154cfde8ef06a148af104d534d7dda59b5cec7949de4086ae669edcc4d68b88347d2445edd3037525c97564ce78
+R = 15bfb47a27c6970fbb3256410d5c2f6c04eb308569a966790636899fdb3122f9e3015455c4b50a6bd8cf519afc22ea845794f51e6994214feacf48322af48590d02cc9812960917
+S = 090c61f6c64381845491dac81d5273d58c59d9cfeed214527a52c8f23b0146431692a25cbfd77abba22d4bc61ef24093c593c827ef645853bc8deef7c3b07bae919152b90c17f4d
+
+Msg = aff61d62c8f5c31bbb7d0a64a6ac589e918bbf2f13e7ad13abb9ac26405e267249a7c9922139bc28140833e10976b87e91cf28285274b2b48b63d24ac94c85c70fafa78f8ad05955c0ce6c02b841ee196dab12306e3e3d6138371217e2b474f7e67a80bbb78a47e374ffe2c9f86292e471c551da50d46e7b5c8331029f369767
+d = 11b92c8b72b86c51903387a65aa206988d443d1988253329ad3a89c902ff1ef8cf73b7f2e4aaa352443bcb833712d94c3e637ec12cbe4c2d4606878576b17fae1512fc77785b737
+Qx = 22440b63bb4557996b63faf19d9f391c5085cdc2cda3755622a6cedc676222ceb5a56ec36e220e507973c0f07e4b2e2d565a69967804ad311f0658a9854b1eddfb5270f4a86b769
+Qy = 50199c9e443555123f153249cf7256dc3e82c5d8cb611adca0cd4fbb0a9a90296bfa770c1b0c0b43e4363b0227273a9ec9f00ecf83afc605b0dd2e5e24f739dd0b4ef6bb11950a0
+k = 0e5ebd85f5fd9a9a81067fdf51b1906023e68672d160ddcedeb35787688dcdc314359ff5347907b685a718ce38a69be17de292eaef189fb9ee8c63271bd6818904cd246503dd227
+R = 051387b0d057985dce86cb962bbca7d9a047f70d96c20539ae7d6b7cb8bffff606f03b8315f15a53049c6c1c227f86d395c2217d32aec32bbd406c790a6cd2706775ed8a0ba1ebe
+S = 0c7f3b7e4a8b65a58c1280110f6c2486cd2d2df7d48b49074e98accdfca4a72fa7d43bc25c6576279f4a70f22c98135ba79158bcc3452940963b556304da8e1ae88973d827bee32
+
+Msg = 721017294f17ef351e41256b57a64a79f3636628c4bcbe676ac9a2d96076b913dc4b246c9945183ec9bd2d251441b5101eac44e2fa1bef59dec03ccd7fa5accf3b7d094d68dcf78c8de4e2f19f56bf0dcb3b66b9421ec3f8b353b9fd74feb2e9affe0bf9aa421b6f03eeba3ffd58fba56b3ebd094880e50de01ee62a108a24cf
+d = 0c3c90d5ce4375a08b85575faa78ee6bbd9e5571ce5a90582042617b807339c282cdc3b003d82006264b1c08c20af4ad4549fbde53d262facb98d923d81b8eb6093374b6a1e84cb
+Qx = 1d900b4f64c07cb959049f2bfa18012f9bc2dccec5a73e9a48a9d5d65499e31ec4a1615c4c50177c032d388263eba1a90e07ea68f081e10272e88a41389bd2626961b646c76ed8e
+Qy = 5c094fedfb5b118accd64d5d46ca2ed92b3123a62042a556ffee9e3bf709092fff88231a26917d368db51d1959ad3285c7faac16ca57677651b070aa0abad96f07d35c5fb8a0ee0
+k = 14d4070307cd269cc1a3c048ec0847edbff46f64c1ba5b734d8a800e50a0a02af57cf24750d292e2c247ef1b860a9d7b5069a32f5b0546fe9e019e04af62316eb79507281fbef6d
+R = 1cda7f743c47ae93a9fa533145feab4c46252afabe3d54990663b5891b4979c645ccaa05c744420ed6fa235952f370f5aa187250d7b069aea1123f19f0f18da18fde98100ff6ff0
+S = 180b4163f2eba6e3769d8345dd8cb003ea120164442efa885eda5bacd75f8d705b7f1bae2976f67cdfe984430e36f93455ee7528fa6febfe92e42a002da165c63dba8fc589e7851
+
+Msg = e2d1f33681759adb7954bb5248b0db3c3885fea0d4c1c0c226eb1e6d2d3ef1b9ac281a0f1c2fe5175b67114b6a501e2426d1454bd5790dcbc4c232cf06b017de8a9bb39e6033f1edb5003e8de3b44cc3d6150c3c952afb442952483cc688908337b7c1a8b5c9da70937ccfa98b2b0098c530ff848010b8e8ee0a8d65283481a8
+d = 10f184c16228d9034271332178ed485d10b6aa76003efc160d63fea26fbbdf5552205ac7df0d8c852a1210cf0ba512f20b798827b36ad56b12a826fa7dc1db45aed264ca6822659
+Qx = 2637543ed8a11271bbbabb2cf72999f65df0104758c2fd6fbf3e1c5132ff1c1111fa5504ee86bed8f219d5025f8ae07055a7849314d2d439408ea2b2ddc40320c57f5d41255d0a6
+Qy = 14e360137ae33ce6930b844d42bcda4050b25f349e9e19fc4fe82f5e4f73cf9bb50212ea875a5735faaa1d5494f1685d6c8177448dbf356b408ffc2ba0726c9befb9de9f0cebe32
+k = 1146574a96394c82972eed1ab7ec98bd08f27653c565f0626fecb431ee4fc6f830554df35fa62b5f82eaad49524d3d4b0598cc7a2181ce9860e271812373d21be9536fc181c3f12
+R = 0dbf465de2c5242fb527f6e4a4188adb96a2030ed8417cd9431365173f569bfdd3e420f86947da10a703370d7f38dc43e2249a2476690829545992645c9c83d82af8adae893780d
+S = 1499782e0163f80de68e3a580ed08fdec8d6552ec69f186a74be89480be28a0df6acdf7c65a72f115f8a59fbc28bb94af64cb3bb3cab20bd25265237a010370d9a5c781c1e26f3c
+
+Msg = 414fc5d2bd56b30040e105cb891788792da595583b11b8fcc7320f40dbf64d9263532dc57344dd17573c95eedf851668b5d552e8796af205f3a0043af1a829fabc2e93d9af9091fdd9e0fcbcc9d6d9ec960aa60e4e2964c29a2f375400366480e513f63d124db7745847310e69a38c8455e4e602056a6a4a14a8694155e0a9bf
+d = 181baf9d497159f837cba58a11ca435c442e5ca792ea559bff9f6a1f562c05bf6bb5914afbd1bcaea75b35f88bdd832314b249a5298622c89462344d3f28a44ba3d059df432fc71
+Qx = 6f3915f884e250034db97327470197d13f0716d1d810e43055757460dc252f5281717b3ef3fdd51085e65a0e073e78b697a21bc33137213981fc05d9b34caf7dca7a4f99be78596
+Qy = 47a96ab5ebec6201b7c65ce7a6e70effeaeea1c095a0172e9e2c7bfc88f7b05ea575076caeab189f810258373cff2484f4fb9c8167989f61aa61ae27113b5140c95f7faa505d2d0
+k = 10e9e6047651362accc816389b26ea6befb0e34fe7363126f8c4ff9333266f46d63c4d45075480da9ebdd0f8da7224b470d914ea1d68cd821f563b574bdeffdd0b3ed73ecb9133a
+R = 00e36644cf0861f45b333092d44fdd99f56e89bf3607f75a06920dfab0ccb1831208296aa2431bdb75c5d50f15bbea2e13d185db6d7175c221858fd2b22afbeca7431c290b15d3f
+S = 023ee3b9ce817eb0a6733c85062cc3bc5f1ae62bdf3a74e3ec704baab05784dbb5ed01a6a2a73c80a3e754c013ba886108d9eed2bc210f29a4774bfe5508ecd876ab47a8527c530
+
+Msg = 3b592cc8972a4782870e079b82a50f84b4c2d8ca90bd500d1ce5678982e266c391c556d8162ac3aab967154d072dbc0ba1dab5545cf2651753dee2881eca5abd412fe624bf3f9d17d33692d21ce23ad15ccffdfd250cb1949e73c9e40a64ebebb03852e92692dad1d7baef97fe109f35b7a492b343d4b643a4a7b1723eaecb64
+d = 083fae86ab96bce99a53e50b7eecff38e4e25b21c4b0f6a4986915de245eae24f16b6a00a4db159ebc27f5a6a072da94ab6be5bf75f5eb3f75c4452bf4ea7014392eb1e02706fb4
+Qx = 78003779e0287bee54df31f64c58951df7999b48b647a6bac416f844485a4cd7a53a64170f9d2d31fdef0194a0c262b90e5bd33a1782d2ad56c210cf80abb5fb118cffd71ad79c1
+Qy = 73f89ebdf0e255205a7525cc12b7e1c58303ac3b3417183179c216ab8e47f33d0af3238e3ae64d418ee89ef3a2cb4bc67a1d2fb1923947b9dbf3f4fa39ff82327d0ce3db24d2324
+k = 13d126fc4033f537b00a81372031026f6a7a2062863a68e36c6909c548833d1a8f5fb5fe25c7d9f2c65b1dfa974630204f71e96d657095b93cb54b00cb88f32adc08eeff4036654
+R = 09be9f4bcd7b8ef111337fb665379509b8b17a2212a80d5fecc685f1f362c45f930acaef9df47c33c6028cf7aae424264575b4635a11edd6b005ad26cf2021051501fdd1b77d2dd
+S = 0dd196343ef76bec527c5929e02fbd5d02d5b0a4b5f2c8561978e600856de56d42943f1d74cb81b67010bae98de0efddfcddea5d354c60c1fa76138801f6cdc5bc932c136309b6c
+
+Msg = 0079a02cbab3dc02601fcb5c8607d555beef7cd71a66911ab6514a4ae21c5a9c0e166f8cf5fb198ec5a49a96e17cf041f35f00406b79270ebfe56dc6b8417d2529fd625686ffbc8f69685aefa2fd30a937c02f25b48be4679e6fde821de928b33b12470867def874bb8c7c8038ab6594346a2c44b39210d3610994ba60a05e06
+d = 1a663efa7bf4d8479bc535fad71e9b5e4f4281aec55967baa008ba17ac2f89cc3398d30573edef29d590fddce8cb157f655e92779f59e7a18d0327d02e7daf4c1216143b3688fed
+Qx = 6b4bb31856dc516be60a0d2d9f42508738edd4f925eca9c72a13cf136720867babb38622fe97df70a1edb35735365f34c74baef9aca539aa1dfdead3324f41a16ca69bdf86b43f7
+Qy = 6c4a91d3fac9e7647a6aec6e4369158bdcca2275866bcdc5a09b2f0f1eba10551da9613eeb1e8d3233316b62a5f4641d6aaf669b975dfc511f2437d43c9eebe53c5115fb4741b80
+k = 0a843d0cf776878fa9ceb163d7aaebd29ba3aea0808c3459036b258b99ccae4e2444bc3211b5898c0769b7d7e036c07803497e13803132b3c6301412af3be8eb4a853e939a247a7
+R = 00356e282c096fe1690fdac4c0c66eda155ec42356dfc4783cff0160e1d76b33a99442d4ee0e3f6e1c5bde4a16c8e18bd18f98a178c3fa4a560d8fb8b4b1d72663576f8baf8672f
+S = 0c5018c1383fc3847819726e1e940028892e1abd164b413293fe50f219f2059105218e4e3b952b912a3258c4ae52dcc03ac5f027fdfa448a8d58e3aa5c21e790b3b47bdfbf21175
+
+Msg = 88573bd94ef50459814806efa868ebf92b066fbc2f7a4be9d2fa06b9dc1a72f72d783a6bcbc107b18a6314511bff217037a2252e7a5cd34cf9d5b2fe9c7846931f0133b2e95876cb800dc4ed7c4a4e4cc4f1195acf99fb0ec224b1f8fa8af71f72d390eca9d6be3879032a318734a63fec336c79035a43f70271def10c4955d3
+d = 0088d1a2c0219696a94337cd56516252b74139ea0733b17fdcbf7692c3e5f6c3989e5da2aaed7468e65a5d578571928ca273ec3b6aa72cd196f560f05095cdc8346e5d31c4c2e0c
+Qx = 357801cec0888461ffde22d83afa9ca008ac88518f4b09074d29a846f5900e024a8e5947bc25ed0e5c980a58fd5e9aadfbfab31db8bec575fe886deda80134d91b3de9625465302
+Qy = 710806c7ed33f6879374c59ea144326f5948980c8013144345c5070122c0ddb7e18e9f752eadf2a9b0854dfb7d9b2f0d80ff0ba46197ce6017885939e9f59b642a8fa41639ea75e
+k = 16940f69013026bafb6f400c037272176b04e35e9f1563d382dc9982968a186e3e1525775d27150b34b8ce5e70b537f0149ce1a521d056b52e75da7e39ee8a529ed987c70b8234d
+R = 199058e36449ee1a3388d7357c9c1020b2e4c02144aea14b041bc584a752c94fb6e474959b24bd2c0c104f5ecfe223ebdede672298c29195033aaad5db1852ce4dc3185ba2409a6
+S = 11f3defd9b442378c461e2c68b239d2e4afaed691238c5ac4e0be46ebd461639a60176f9884133900f988e2d730d34df5e2bd8a14681014c0a213f8d233b3c50ae3064fc38d1a19
+
+Msg = d0e02045ece6e338cc8ab41d4a064c982ccb1748c48fc2fe0a6f10bdc876094358a6a90a45facec798a83cc95c6795cf0f0d7c66b77e22cb114c1432bfdaa1485ff35b6a58107cac3b7e58cb4f6c87c68db60b751e78f1fdfa54b8923b98caad0a4f31226956d065c083ace5f1e9e91944dcca51879d782e40358d58ca758750
+d = 16cc8a0fd59455ed8d4de561fd518df2e008f7dfaa5f7f29ac2489a411e233917b43eb3ebe2596fc824be58871949545e667dbcf240dfb5e0c615ade0179d9ea2a1b1ebb8ab9384
+Qx = 2477e678793593e2abe837961895c7ecef71af1feb882ff27cfbabfa0ba3ed771b79223e7b2d2388efd371d5c325854cd60e48484f818e1a8146fbb780cd6ce06ba63c0db67df8a
+Qy = 01b696114838bb972ec6d536abd809d3a436650191c43b2bfeefab2b400d5921a7eb78e307266acc190e05f3869017f0a66f886bd6556c58aafb1042478cc768a4f86758e9f4c32
+k = 1e1b851bb95d2913d6d35b756d49fba6f4c127dbed80fe4068260cab89c1d42f7a6843f731e83b379ccd8a4915d2e29550f3f6ccde607cd0b066dd5fa41ac2bf37bdcfc26cd4d04
+R = 10d4291346685fe070b267edad91154df83664dc115f058ea036c712929634d53662586bb50cb6473c2170db5d4ee43be0c50532015937202e193d15d5189870691ba65aead7f3e
+S = 0b2a15f1ef00204bcfb5108d8f1da96ac3297aa041074b68989ff5b6b276380de7887753fe3d416ba691ba0b2ad7fc065ace02815b2323fe17f6445b0fa66dba5d99d8e7d557cd5
+
+
+
+[B-233,SHA-224]
+
+Msg = f1b67fde01e60e4bb7904d906e9436a330c5cb5721fd4e0a3c75b83dade868736bb1d21cfb1b5c6407c373e386ee68ec2239b700e763728eb675a153b8ac44cf2a87be85fe8ed6683430cf4b7d718891cbf8d583d0a37cc952cc25fe803a7aa4fda80f05541a2f1f2601cdd0c095f7110f2a84f7d641b8531572269b21cbe77b
+d = 056673197bfeea9bd7a8b820b4ae51a50411bf118a692bb9ed3d304da53
+Qx = 03489be62e53910c20cb508de019c3e326f65051f26749944b4454f156a
+Qy = 0f775ac38baf19499675725e8190aeea16f52346b1c890d9583b38c7521
+k = 0a6c9914a55ef763913273b062475fd0188eb2d5af9c8c1dd97cb3cefc3
+R = 08601a42d7f7eb047e8ed9820ddce665c7277f8ef38c880b57109b7160d
+S = 026d6f50f0508953657df5d753c595ffb8e1c19f8d092f8ce8db54f76d0
+
+Msg = 1d496d96b533c632ed6a91f6e3653cdffaa5b8cc0008b35e49b2dd52fe261105c2ec7ee71a4ad5d51fdc3d36d688a3b7ccb3b3b0c3a65be17b8d8aa172e3005cfbf37a2d1b1a6e268c090c6f318e7e96f9ec9b9f5a8fbcc7558d89e840f7e76e44bed91c26ca48e6f5cbc253ca2fe8cb81c484cabd24070e488f9c00cd96ad4f
+d = 0468f01d483144e514ec257f2e5fdee28a927f2adb19714c1f3524dd0d3
+Qx = 16b3cad89cc42b80bb730431963526e26ae3b415b421575dfb6ed973e17
+Qy = 1acaf7de06e20262efae01fc80969cdc1a281f68e8c8bc0d2d4fbba3a3d
+k = 04d261304678301985f5bb3f6ae465f11c9fe0e5031b31f194969252703
+R = 0878a87b2867c03f55726ea2a6db822788f4aa4e9ef609997940ee8c8b6
+S = 03545153f0554a8f55301d4b948043de3057cace62c8032c8ef8a11dbf8
+
+Msg = 723400655027f474446843645757f7e2cd466bf97275067b4bc4c9d79bb3b19b2421835d69db916f24b77c381fa771fc1e7a19d2b4d09411ae55acccc615b16fd24705762b441ab67083a921fd4ae569ce0de69449aa96f5b977ac7dc022fdc8335656853796f54b3fbd118577f98920624eb0a00204f1ef83827245c06646cc
+d = 074052d027f05465a8083a59cdbf32600224e1f563f653b34314651517f
+Qx = 06999290db440eb5b3291bd4bb4a1af6386654fc4d275ef136c0e03dbca
+Qy = 1fed0b1f9284e488c7fa2a010766c340bc25dc132c7679c2598e423c3c6
+k = 06e38460379ac3fb13f64d4de654d4fa30bd8178da0bfc29fab2a1e2e39
+R = 01b18bafe55e5c24fa2df4c09112b44d24e78dd09557349ceb1b916d280
+S = 0ad7cfa003267a6b7a99894f75720cedc9cbf820d355a6b840709f42f62
+
+Msg = 155860cb31a142082bcc0bad828d747e916392d21f1873b3a3c1d28ca3ff9d45ddb66a712e3856b6afd07c8d2b2a7badab296a9775b03f6fec0befa2d8d6d00fe3938df244ab46e836a3e686c8b4f918da49f0bb3940bba34a9aa22c7caf02df7758b0de01d9f47af6146344b9be3842d9c055eaf0fb399cd8db95c544a62d8a
+d = 01856e7544223f55f80de72a6ef3822fa8fbd68eb397d06e2d76ddd35e0
+Qx = 1a117e52f09080625f85fbaad8ebe0d3ad410f034242bf48365e88ff735
+Qy = 008b8bb7958d191265901a3f15b2919142505efeea13df6e42da8b0dc1d
+k = 0aa106ad1461353865706bee9aa092b00fcf1b0108ecc1266ad5d8b6579
+R = 0bd6fcf49029df32fe0fa47f39cb9428d95d00a84a5afb392d7b4b365e0
+S = 0b17734befefebf03d1c79e59c12ed3c57e7d120dfd993bf276de559588
+
+Msg = cbd6e305cc9f0dc90caee6e65a74582e9357bd25c78e33a7b14e1ac7e9397ff4466f192fb432143e6df6d61a0ab808ec0a361a6d95a357a38cd3e241fe03ed883ccc364b248ee2a08702110745c2688bdcefa33c1a45b9c8b200e45cddf3e3f66b8d37eff07fbb3366ea1558ef304085613c56707095724b3e134c7a7d3f8dbf
+d = 0860aa2b589f2defc617be73e191502e5d9952bf60547fef19eeccbca26
+Qx = 06abc5619422b7d548c612e54df0385c293632d4d97c21e2e15ad98d0c5
+Qy = 06c36c072603681c1b03f6a023c8e987f39d931bc2a200eff82239ee38f
+k = 084fb252dae9a96a44212d18e15cc52d179cd5e3392ab9da57d04cd5a9d
+R = 037cd554e7815699f033ca9187ddb116777ef847b92353f613152c4216b
+S = 05f806dd062043420dd056998bdb9822b3177406a536d766c4aacdeee81
+
+Msg = 812a218ff1ee1472c189f63386e5b8ab341671c3a4dad27a8c6249d1c0f9a29338b471b6179f17a078b6504e804ac55ca3b13e68a623041bc1a092ea2adf3fa1124bbfeb161e6d7c483433f1548763b84da00352a6386e1339f674d45dab13898147ede468e0e01d2c4e0ed66b395a16cc3ded3e952ac739205f35a83376cbce
+d = 0d0dec052a00ccebd0c0c5d9a08272f75744a2582cec7ddd924a2b022b2
+Qx = 16bb8c3d319b93731f1055756e57bd56d50b6b9ffbe42735925cf6f7675
+Qy = 09dad7b87a749df130b45d9cac8011101c15abb7e64bd4fbdd94107fa31
+k = 04098547601430c723ebcb04b23e0f1ce8b1f79ff7ed3d05ba130922b01
+R = 070ea6221c0d62930b019faaa856ad2c84c3989ec54040bffc42d8dadb8
+S = 0aa20fc58beae8ccc880e7fcb48a471faa5baeb36bbe5aee71ed9f8adb9
+
+Msg = 0204b1fca831919e89e108cf140b3770f531a696b1d9a4d1fb68809eb10afccc257cc90cd36717c02b2f3d6d3d1d8a93cc5c48aa7ab9f9fddfe121ce9143376535a0c65e247c6558eac49fd1d6d1bf431ba918c471cb3d536ad485ec51f6471a340ac75f160c4c54cd3ffb9dcc123124b42df1fd2eaa005e3377c5d2d55938c6
+d = 08a017d717d6d1213f2b74c53281b07258738c0c7db649ea1ac46b9a3b6
+Qx = 1eb379e27de6c04c5320cbc18e79ed9e8993710ac70ce823f1ab5762b67
+Qy = 0f552192645d350361762aae79ffba39c33c2c5c0df208219f1b339016a
+k = 00e4822b2cffa327a8396301b21554da6fa52f418d67114bd58e850d935
+R = 0d64dbdadb4ada2d3a8892049f7fda3c733030522b44cd72ab850b77bd0
+S = 06fbae2d8e4fc04abd8a6e9cb011974ac851ec108e38f9c72603f7a04fc
+
+Msg = 2033eb48756638cb56e2cc39a3e775cfa11fce86cf71f04487dcdbc7f262bc8350a30ced54d1fcb697b28a6e96f88f782947c997872307ed963e1d68985f756435af77f57755cacbb4c6b50ed419deec9f39f0a549a13e54254fa0a5832dba2d943ad4aed8688889a2dd29dcb4ea12abd6a6c50eabcb3981c3a0c1ca5f0b9629
+d = 01b56c14442b084cfd22aeef0f8028ec57c8b571c9fc1e43de05c45e47f
+Qx = 0d450c533b13b211b8c91dad0738402a5c811460426ee2f35ae068f2c12
+Qy = 15e1c9f9d398925c619f8aa0bac746eb7907d3d510814cea185a7efe771
+k = 0dca09773730a2758b7f4d9257a8e6bd942c141e46bde5ca54a79468c4f
+R = 0379773ebb7a2860f3422d8f8f714b234e5abd8860defb19c659c9c6179
+S = 0cb9272a27661604425ab84632f586048483b9f9cb80b9697898e745117
+
+Msg = 2986ab1cfe8873009e932dc68d4727d77ccbbf378e43fe4aa7c54416346b036b89c0aad1b82977c9fbc39a00f1dc916c0561d8dd70298c02b6cbfe572e0ef2058641e841c6875e8515f3c1082765e046c90c956d984b76e0e8e6eb433ce26c1757ac5b13422479141971c20102e9621d18f51096ae3173c2753facee2862d66e
+d = 05afce37c5594586ac46a34ae291f591eacb9880a7de92701977f447fbf
+Qx = 02a069ef14f2989d2b715c5006642ba966cc84df88bbc27e713e15c47bd
+Qy = 0f001f60b8a8102a971faa2c42d3ea9cec37b49c7e6ec0cae9f7fb35713
+k = 09756db630ed9b708bf1ab8aae6a7559bc235c4e9f4002ed26e2f019aa1
+R = 06b9b2c1d214373647d9a2d24ba69741218064004614368915d5cfaacaf
+S = 090dd607329c27483fe43b7be137c3f51c23217c939baae40b53e65af2f
+
+Msg = aabf5aa90ceef91c2155f90660adbcb0eedb996f5242cee15468ae217058ebeaad8cd4ff8cdc754a8ab85ba43c59fbab6386686fad5e27ad3848fe52191c7e4b203720841501792a625aef2acb6e36493b792fa55f253effca682946ad8c77e01f44e92ec3c258d0dd98d3183f4dc4a0bd3eca183794abd6232a6f9e4add8f57
+d = 00696df05dc7a54a9908a73eb18416a155cc8df4ab26032539d86eae537
+Qx = 08f9f494ddf8d0030746a8c0b8d215dda6cc2724f411a7ea407629294c3
+Qy = 1ea2e9f85f06412d29c677aecf624a83c2fbd86482dc0d564906a91d97d
+k = 0d62b06628d3884f0a329a7b6b4f832fabea4ebc85ee03e63f2967e7810
+R = 02e39824f272d4b74810594810957963c777207217e53a672010605b9de
+S = 0e64bc44af64b6f879f0d32f814acfbb98795ef7b2f246b3f91cacb55cc
+
+Msg = 29ff209eabbde02b10b3fd559671fa53e418750c32c4a18d31cc0186d1077581bbefb8770ed079f536e866414a07431ae6633955bf42a2389b6f8a565d6e4ffb4444336e0030093876a26d4e3106e9ac697788e41f8a21c755eeb86a7c60f18e5e1069f16408a4c375a6a68d42959f2fab7ac09736c7b37c80c05897d8566ce8
+d = 05ca31e88c5b2e96e433af2023a66095161710628e7bfa428944d6676b8
+Qx = 08232d4bbe25536ea7f83c145a8d2b1cd72c383eefc2adaa1ce72c7dd9a
+Qy = 100b738c6f1551b3240293ee8e8ec29fad0cc485ffc2cfded96b68162bb
+k = 0df9e1b418ca1d41d749ee998446ba1cc54bc8bf72eac6f30929b40b5c9
+R = 0d4248e0bb60fe46abf7bdb2effe804b9d394d8a5514a5791e149d435d3
+S = 0b89a459fb99cccebda754c4b2ae264c9aef7b5b610427f42c35dbe7d3a
+
+Msg = 97765d876c80819f4004a36d09ccba78e600efc71eb7e869d3a00f658d2ace6769c7ab1ef590f41fb070aa8e08615e138df45ffbb6473d4a86ba5fdf17dd6dc9ea9ee19c0332563c99e6a3451c211d286d69102b47bfa6e07d468d9bde82e5c2063fb1ebbbed6086f542cf68ba46d4f214634afb1146dd5a6f3d50912ef5b824
+d = 0ef8fe84727a2ad8bf4e646ef28a492adfaf785a3a2ba6e6f985c649a8c
+Qx = 03435eb25ce9891a78c120098992c666940103eefd80d9bd64f1d4ba37b
+Qy = 0ddd6a4a01e443c92afbc247f634b85f1c858a2aaad35a26f57ad4c9126
+k = 09753a236759eb32e13f19b9d2ad06f7b4db4ac7b1df96813463d0cd557
+R = 08408fc46149dcce0753d7cae0f50c8c5fcc97acf7a1a02a9f68c0b80c7
+S = 0b5ffba104acc6d0cba87523382ff928859718122c4d0d2298e74985d89
+
+Msg = 21cf768d087d1e4eaa8a05e2008020e243116206d675c09be42ef2bc93617ecbb0575c873c6510ede9979215531b62126552738862fc4323d487992754e39d8f0d7e111e165ff254200e05082f59a57ef649bccaef6f980094fad3b7ef93bceb161760e200f0a2e396fbb6b6142dc84d872311bf932b84616b22231747937d58
+d = 03edb94b8c62f9af30c14a790c0f5d65e362a21cd8569b9725916d534c0
+Qx = 065133691b888cd2513964b5a905ed9334cff6367e25c09db1743045d58
+Qy = 1408e1ac721bfe2198086c1834d484b6e5692c037e09928cff87f4b5a88
+k = 01d8f800ba05d8173b0f1bb3aac0aff68c6b24cf98c28f5a69b0b5a52cf
+R = 097c07d4352e39e1878c42fe97ebd4c3ba5098706879fad9be4bb2dc2f7
+S = 0bc669db3a488e613665cd26da7927c6b6a073ba6b0951c00d22ab1ffd1
+
+Msg = 7b8e58eecdab3e40212bba6bf284f9379265b3d2baec3e4625aa08d0ced851da193c292ec793dab42732c07b4e94d8b19c83aed796a7e3a6c2b954a7a9a1ff9b2bd4ca62592c8b68f709f1ad38a5c8033ebb3f33d176945bfc68e9ef2b0cee2d45a13ce89d238a33c09ce2c0c63c4233aba5717b85c4c161dd7648a41a5e39d8
+d = 00a7519be62562318da1b67d22cf8e720353d22641e0cee11c7a352bb93
+Qx = 13b63dd8ca9044a3e518a67999a781a5b62994b6e20454003a9bdb8715c
+Qy = 1a2f9bfaf528b7f5bc8c3b02eccb71666c83e4a598b4077de999d90fe27
+k = 0992ba1a8331bc4d88be7dee06f96098bc2ea56668f345e187f32f38171
+R = 0c55b45bc7bc3092ffa82234b06ad45525b45f8904011f1bd6cd356f0cc
+S = 0e6163e70ab56d43fa27211b98b48f1cade127237bec1c6556020d39990
+
+Msg = f8f268d2b04fe47e5052c8d0d653787384b9654f0bd2138a6f52b80713feeed452b976a90eea4edcfbb62d04f3eafe172ddebd7cdc3701ecd6008e3d82e8eb217b13b5228839f61075159f3bd1e1409c08903874b6dfee2789dd72c208ae769ec8c7d52552a2b1fd73dad24de8b571f88e2184d0ee7d063a121187f97e746f2f
+d = 0264022fd7dc2328a6436b522793ad9406d7a586667a0daaf1bce927338
+Qx = 12d7e7f8519a7e357510adfca2f50182dc5fa12fb2a77409fb781ed500d
+Qy = 0ceaa9a22b7ef9febd8a9962ce21d83fd2a2a938b9d7a78d669dd233974
+k = 026fb8fa6e746106500dd29ee32bbd03b94302ec3a123356b23b3055e51
+R = 0f416418f7aa4d437e7606afedf961b968a67d9a1524d60fe3f6df4d3d0
+S = 08d3afc975a8147fa8230fef4b16e3024180a9768702038f955357ce8df
+
+[B-233,SHA-256]
+
+Msg = d288768cbd066fad4bb2500b5683fa9e4eaedfb3dbb519b083f6b802efda0a022355565c5fc6babeccb22f3adbbda450ce5d633193d1431e40c0fe631a295cf85965cd3f5937b31866bd6a5300eaef9941daf54d49832acfceed90e572ef34ccc94eacd0fd6b903fee3c572b963d21e2881656a214d2a4c125778dbe3bbeebca
+d = 0da43214e2efb7892cc1ccde6723946d2a8248a6b4d6c8872fad525ec3b
+Qx = 0db09738bf0a0dd777f67e82be50dc8c2d8e91598bc0b8d4486f67c04a5
+Qy = 08ef463e2f37ac7c3d276676cbedf17ae11e767ec577da7ccd90cde3b74
+k = 0249cbd55e307a0fd10a0c70b1c0d5e2416f4d7f144779ddc11911f4a08
+R = 04d1c99f9d486fb92b132d68c0173df891ca757572f7acc03cb41d46bbf
+S = 07de2deeb58d55d65fb37f600d916cfa49f889f02ef53dcce412703d1c9
+
+Msg = bf0ab46e0a756c11229b0ea961f8d57218be5b00ab8b0e91d7664cdf5e0341c412c0e992d26ab12115197db39df2d1a6e18ed26a91be461432a2dfc21d98cb16003e339b0b0b1f100e4e6f4824ddac5442f22a1fac26326ed8a89cc91343d7223986d485cc8c64424e84d56be536c57e4dc5faee459b1958efd79e07e90a9811
+d = 0aeafa49d776b61f6a30d66ff64bd40dd8d79891dd5293c1b5cd3b46a7c
+Qx = 1ba1b87b16122e6939da5dcadb8902177a9f9ef09194c8695008b80b588
+Qy = 08f51ee5cea1f4fc9c44c70df57326ff121268bf4e02cd9b2626fe7c1ed
+k = 09d640ede5bb60b9aa78e393ed453b1643f6dade4aa20e994db53e81fac
+R = 0277bbfb7479077d5fb6813670fbc7f46055718199550130b122a7cb8b3
+S = 0f8dd350bc0bd2d84cdd374c56ff2341de4102269a1e80df7e35969d4cf
+
+Msg = c7b1eeb7c19eb16e7f42b61d79e421b71de797a6cab4e0baee522fee7acdb533f7bbf5855316544e1b82b4f2a18ad0a2311e7622549332122171f32fc62a90e408207e0fb90d1b052821dede9c41b15b6e07d84d5d7b9e31e6396a8ed229fb6232b3051298dc5321aa589f4e289d27169f14c8cc93644916d9b72dbc92c43488
+d = 0e95db309f4305b621f51f93588a2678cb19aad0932f365fa0aaa3a3895
+Qx = 1177eefc44b6070e2c41537e75c91e2f08908c0d950bc90cd2f4720b335
+Qy = 0f751312dde55b1bcabf31665deb6c12d043d5ccc89800622a557a7ed37
+k = 00015798ef57a771d62d194389817c93de1b225398fcc0d2b81d94054a0
+R = 0eef7161a167f69a6c89b0f173db2c4a7033b5d801c0d89642ce65e377b
+S = 04043f8985bbe0221fd595f9355c33e1930b5e10a1452e81c31259e1e3d
+
+Msg = a738eb074e1f277dc665118ca055e6328059ab26da188c16f56384c566e43df8cff3d2a10d2d15c3c1406de8f734b20be5dd1ce937a4289f0ddfd7bddabd03586556eb8233b8feefedaa1f49bdec6d45fd562c2a83fa9fcfc2013bdd77900857199e51fa9c7cbeab925ba8f6c3c5fae46bf8e9c574b302f1e5f9c44400152a78
+d = 0d4319cc8e409b8755880827f3200d3f0f1c64d6356fe74eb1f5aa42499
+Qx = 0bf65953f2d08477f7fd0428c31125184e3bad4d5da00c91991949e0562
+Qy = 0f1669d0d116817d625128ae764b3fde956432552d24d98f08a12925afc
+k = 05e8704febc38bb8ea76f3c6433c1f0421dc5e5af959723a5a2f0e9a970
+R = 0307c0b838c65d1a47792cb367253bf7c9f627435f1c7ed74494b318446
+S = 00031a9b35e935be6620243f4878a38d4e617fb25f7a4883893366f39cd
+
+Msg = b28103d77e5457c42e026e713ea6ff03722a36512da17197140117442a976f9e2139c54a759fc26af5811b455e5a0d3a95362d9939c1e738045be9237b469ae2106ceed7e7842b44cc0a475d5af6d781e32ff1dd1f4e1833dbc7f82b27dc7e1562d0e29213fd8911105104a7a16f665b926aa137f70d868c90e72f8ee2c95b64
+d = 09e556c945052e5954915c773b2d47970c521fcc99139269c3ef46093b7
+Qx = 0db68c16ffe64bede4a849812df0b8e202f74500cb7d5349aacf7f3f026
+Qy = 084b5892ea74835e96e9dfb1bb201a4dcaf32da25dc00dca019d806f5c9
+k = 0d0c9e0b6d4526d5f6494d2c72f812fb8d26e17c7a44f6b5e3f9e684cad
+R = 0a379ac253f3aaf94cc49e91fe3f2908107a9e1a4d102e02395eb18cf08
+S = 0854c2f6ecbfe95cfd14045faf71ad47561e365c1dd5f515d8817c3198e
+
+Msg = 463d04c84521ae671bb35c0a7acb3ae509b1b0470f39b8fe7ae5f3c9fbadbeb2bcc3a87e284cbdff07407a351f7ba743aeac50c4a1fef7375b90eb4af8ea2df040776bbf3e4389e7a80bea40530842642b9895ab9ef5ac8ed6c9ce7917d7b3ebcf80b801da845943313988c1970e7748cc306f914c37414f8247d648b580000f
+d = 0becc76f8a77615c4f92ae1f91645bf5bb908e75ef22fd544aae63a3c8e
+Qx = 18cd93bfe8fc8ceef2b9be14fa947b60fb122f5099cb5bcfad0cdc601e8
+Qy = 16de11e673011e30f6fd92025a60d7938412ac63b19d23e45bbf53c6c4a
+k = 04e75a7b92c42ba0581eb1201fa5b3fb2ac82460e953c26ce6bc60e145f
+R = 067bad23ecac0883d218b1368d822b3bf9b82453c0e5f3e336777c6a507
+S = 03788a331249463533384a61c47232aee6f057634c37560ee25895b2a03
+
+Msg = 8b2379b5553ae7db6023cb010e26ae91322bc3f94dbaa369481936f90a886e5d3827d995ccf03ca59f46805fbac0337d31a8f117cc7044218a934d5bf507090e7e21178a7162c8fcb39111e6967803dbf9d752f3ae737ba024d0f4f7627e08be58efbe997a164106bfe37f67d2f19c0fcc7a6c7eebd96a72582a9c7bdf881896
+d = 020572c2a3dc3ea430cd8cde9d642081c21658e8bda165550cd9a5d37d9
+Qx = 16117486794f14d171dfc3ccffef0396cc9fe5aa45d6d39ce0f252c4168
+Qy = 1b6a12fe2adb279dbbefa4eafa273a2ddbafb2c6401067a5ef5e859fdcc
+k = 0edc8d0b64496da309b10630e9e5917c9a807ccd7cc7bab14360873eeab
+R = 0e1fdd3b7849806fe587ad93aef737ba0472409b7239981f0d325785fa2
+S = 0829449a0c39071a832664e8148e762efc36fda9e030e0d062458728273
+
+Msg = 3090bf7373731cc44c00372c1ac59280b0f36e627ccf763fa68a7be37bb0ac8cbd4f70db54fc652566c78ad268f78f015e4bb1e41516fa56ac303a3bb4a52e1fe897d8338db5a6e37cad685e704b994504bd231c7dec0002dbd907a7ebfa809833e32eb23fffdb44fe4a18e11fa19d67356cfd703cf39a75b1a290b8a7c73afb
+d = 0769cfbf2dd8248ea1e0ac9b275c9d6ddcf923fe762079b9ed62ccbaa89
+Qx = 1aadeee0e31ba9505da3e195d883643d260dac9fe5e86102c8ed7f88eef
+Qy = 0d925bd5fd700fcdec60cef9c9fdd304faa102d9d721b4f21291f8c96a4
+k = 0f2e203410107c075e25c4adc2f55dcc277883d679ea307df7d52060fa3
+R = 02fc0975c2e70328da4a0ad2b8bd344a8171c2c500c55b1c92270230c27
+S = 08871b6791f7d03796a3aa537fa820f0eac8f2463c9f918468e7588b784
+
+Msg = c37389cbe3f46eeebdda343e354ccd543e96b0c2a87e057aa6b9c4895a403de706d658bbc9066c140e50fef4b56af2db1f42efb70b8021254649983f1e11d04d6b10169d5a1c2093b6ab89227b88a30537c776bb7575749c3ed87bcb29effd8e4f17915b4d5dff6cab9678d88f33abead1e73dbdc5c3307ff3d3b2d5fd7bfa83
+d = 040ea4a37b388f0cc464f7e2bf92173107b268ff77a8acf5f517b4ec0e4
+Qx = 08acee84d29638a7285654d20f8e0653c7386140aba0bd2fc157d517643
+Qy = 1482ba5ebb82ba46654aa1eaa6a5f01e030177318921a0c99fa3f6eee9f
+k = 0a6fbf938e9cdd009c838196ffeb61f7f545f7e7e9a6cb18d1f595a87b1
+R = 096a80172a7b3b65c0a8acfa8b89cedf9cb19f6eaa5d38436c300b7c0f4
+S = 0b7bb96ddfc9d1324bea96836c557cf88d6ede9a93ada8fbfdfcfe56244
+
+Msg = 8884def8c3b9c5f856b9c2352c85ea71aae3c8d0e84ca74e70e404a21467159fc9826548d16dd1ec5a75dc2c23ca37b30312f25e1194e0f9385a0499db34c855412bbf58979ffce7fc3afeb7b8dbf9898df44023200d809f520db99eae315b5cf85674fab008a20340fae8f6974034fd3e55bf08c5522a460680218f9757e368
+d = 037fc7898df9b37b5390537352f5c0b8de22659166c19d7d4df31c3938d
+Qx = 198674b40d2a68ed94d5b2c51102393d1332404f75187130669b9de0df9
+Qy = 13ee77d854a60f1aa74041ef1fb58727c09f13039bb4b33a818dfe9af2a
+k = 0cf92eebec59605b1d45848f5d06e93ff2767dfa282929208ba801a9fec
+R = 0f7bd93dd4df06219fb974a4e85030840c7d4877f131adccbd98cbd25de
+S = 0c2c4a864459488eb5498a06b0b56ce7fc98fb29b1eb9b6238da8cc8f52
+
+Msg = f1fc154d469433f56c2bd42aa52237a4a4bfc08fb6d2f3f0da70a62f54e94e3f29c629c837e7adf0474fa8f23251b9b349a16848942c0d9cf5db1d0fd99527020dbe21cf0b94a9aa21f376bf74da72d36f87b306b0696771efa7250c6182b426a4500ac14de4a1804b38db8d4f3beefb8c9bb619ac82cb63fb37c2e1d22951f7
+d = 05d5069425e7a9925d2cfc6360a708147b2c1b55ede243591885147ef3b
+Qx = 1f35f161ce0963dca70066b3a6de2a74ea1941a27cdfabd9e433d8084c7
+Qy = 1d5d9cca5b741b2321d8511a777fcc2515c99ff8d13ff20266a163c94b9
+k = 01b9c83d36ada7e9367790ee850163ef4420104e0dd3299ef6d65191d7c
+R = 0dca4e804bf74aa496c15025acb4232c637c9b81e9e26d6f2065d6be21d
+S = 012014f77a4ddb7b266abf2c65a653988ee6f913e700f3f83f3e78c88ab
+
+Msg = 885cd348f7983a0721f96c0e866821223d3e5a95178b16d18652b4062b1b2278aed6f54ab06f7e37ae6ce1020aa3eb812d215194bcd212302da5b971fd86aee1dcb23057dbedb569bd0bbef80df538da69ae2358cb03bb77c64d3ead475c8c5ae5bfbdd75684b421a26f1a7b0c37548fa32d805acdc91230dd70a48232a12846
+d = 0ffe3e7b82ca62b96e057ee072a4718ca20a6cc9a3e51e4fe8ed7b4b9f9
+Qx = 10f774adc83c1893894855366f1db1962bc697b8e1d047a01a08b12da4a
+Qy = 078c6ff634d5dc8ffc4d8b1a53bbf94046023095a8c2b41618c4330a4de
+k = 005a4a50de4e97280d6ed1324214d91b271deb649a2dae18d21a0182022
+R = 04bc8ba9ffbca81b5f19f0d8b1306900ee642bc5cd9a9dc9867a4531b04
+S = 0353567acc062b83459017c70cff4f3b8ef0925032b51d7300261408549
+
+Msg = ca3b0e2f1c7db4e73c699f06e432bb0f63705ba66954bec4a259bf31c161bb4861476e2f2f7dde9d841d1ea6bd0990cc793cd7a10432e38735c3eeda7a0d786e8821239bdd6c4972c96c2cf68ec5b935391f963a50fe16af2719c9029943b539ff0f1f5645962a6ac46c75d2037fa0c7cd46deadcdfc66e1ddcaada3a376acbf
+d = 007a9cb5ce27c763646de414ca2a4dcdb774d69ed2bde7a817baddbc9de
+Qx = 086d4ac1e3d54f7c154c5370f5c9a2d22cbe8f794df68974706bdc9172c
+Qy = 17770a2ccac923423137731a14e97f6ca65a8cb3642eceb4e70c78ee929
+k = 0538b86e0a899281ab56d28f40bf3b7435f9a57e334a3269233766049a6
+R = 007ceaac3aa0e260c371843104f5cb91a057741b38889ee796e69f920e9
+S = 035eedd44b036b843deadb8e8df9d96b16e719ba350a634553457ae71a1
+
+Msg = 4b0a31b746763beee77cecd318b90acf50fac4172cf4bfb354e5a440f651cb89d7a515e09ab19e9850803ab9167c2aee3b395a5da10dc9aff799d73756dfb0a9961d93bc32f15a96bf13962a03d5bd42ddc8b5928def7fc48fb063f42866fc5f96cf88fe0eb125b7c01906ad6a7fdade28ccb0a421ceff50ae03a974671b2c27
+d = 0c03fa9e38dc1c697f70bc6381f2bacaf860bb5632fc837f728da959ac9
+Qx = 195f386c7efe108fd1d580f0a77031e180e45a23911ba983217207a904b
+Qy = 1a6837095a64f71ec53ab1c0d9a3a39d69a514065d83f1af26870e41741
+k = 0d4f48085b367787a614b57c06ee8018b2e95e989c2e8cf355e71db1091
+R = 0391710f815babf07b6287b7aab8b9d2ce04bee2a144f4d4a46fd17cf77
+S = 0ef29cbd771b8a6f414ecb73b7937ffe0a108593ffc6899f28d4030a9eb
+
+Msg = 3011d42792b21c0f1719faf6f744d576f72c5fdfd22b1a520d0e8d47e8c2b06823d853b13c9fa039fa30a6f2e3e27bb2100c6a35f55703806bbf0f79b09d0f629f8042ec63fa04062f15f2edb92b19237980005566f02bb12a40b4ec66e4ba6c599d928b33f72d7437c0e399a8e6a9068d1fef24917fc4f9ab5464ea6684dde9
+d = 087dba00e3fe4802e01718017510094924496bd2785d4ac1a352c530473
+Qx = 1198518db2d1255aef955b9b80471aba60cf6d8fd1feae6d8e048ab1403
+Qy = 1833332a116214e4d9fb37c8e0ab7552b87348434a67a0c41f73972dc9c
+k = 0378578acdfa572b1de4e032158b28bcf00ab7dbaf07b0e772c39603216
+R = 0be2cb45d527a7685139290f1098de975b69957fff2c5c29059ce417950
+S = 06abf4afdcd2990121723b94ab8145d01cc4917cd70416620ef100c67bd
+
+[B-233,SHA-384]
+
+Msg = 05a5d3a3b79f4e51b722e513620c88092a9bb02408f5f52a32e782fd4923f4fd3094fc5536caf4b645d830260eba91b5173f3833dd65600fb9e246aec968b1f6ebdfddb4059fb2de7e636ed60bb7affdb74aefd158e54485d5f26be373cf944c6570daf8fd7e4b77fad57300667d6decf5c65db99ab8763bb4ecbb09fdf47e3a
+d = 05a387e7affc54a8fbb9157b5ebd400c98e2d7bd5c3e095538987d4f8d9
+Qx = 1a97224cafc063967b25cd1a43283daa5411f3eabe9386b8b14c9768c29
+Qy = 02cefaec5141bcb084cbc9aebf28fc59780897ad1424fd439eb43eb911e
+k = 0fb7ec3804654b9c3675f7b3c427f6d01f83872e96de2742e59c93151fd
+R = 0808d829d78e65eea47122c92f8c2cbf5a8d6717a057ef1659fb6f8cd3c
+S = 0ef338e09dac0b12fa6109d15924efb694a0b672afb4ef05f4e6f2f7b88
+
+Msg = 247a101c8196eb93a440280650ad463795690bc620e46e8118db6900a71eb493d03fbcf2f73a79bb47aa8e2d8c87ef70e4cfae36fae5c45fe247d8cd0f7d0718dad106526945014b4f3bec324897d8e1fa2f457b8a68e61873b7fa0350fde3b87b7b001c13953c2050a24f71fb77eb455053e49200ebcbba7299485c0f1a40db
+d = 0adae709a930d6f5a5c0e3d8ef4aab004d741d23f0ffb8287f7059890c0
+Qx = 1541eaf3dca942957c48d693d2eaf2a456646d2fb3eb8df1779b917a9b0
+Qy = 09737958276dc31852e57063119f1d2d061616b6a2fd35b4a1a3f046954
+k = 0390d5ed395f8ee3478c2765525c235587dbf5bb2316df3a1e8c664185b
+R = 0ebcc4f84bf2deb9b3d669158998fc96d7516580675e24348ca58d70d2c
+S = 0b99462b85e6ce6b46e5aca221250ac9de7ccf3e63b38919b61700be866
+
+Msg = a16678c71976a3ce3362ca379b3272b92e8ca7085b43752473db34e4d6b61eeed3875f49f3328366fc9d0644824e0104817de458e4c1036636b18b83dbaf063f2f99818959224906571c7b28873d9c702360888df151e9ad1a7003e6130033203acf8a69889be6ebd90816f2abf0764f10be68653b1e56766ecc3150bef8b042
+d = 035d391411e6d679751092c4ea5a079c591e77ebdcb57c1d9006ae70d90
+Qx = 01298e6f1612f90dbd2eedadfa8ecce22dff1da2d1cf057c41bd37d4b06
+Qy = 073136a1caf7dae2aaaac571a900135a51ef031643e9d5f01934333b864
+k = 09e343003670f61db85aedc0249db21953d232bc45488c3d6ceaa6072bb
+R = 04ac435e88f8e487b9b217e7d68fbba9bdea0b9685769878818f25e661c
+S = 074d8f4dd58c922d7e79f30950bd54c10c1cc52ae3b8d00b675c8e501a4
+
+Msg = bc2f080a7f0b69a6b142b8f3fb481a43bd71d07418df4f3b802568073c1a8d35729ad197f34a4e941a6dd511c63f201d1f6c34a1b66545bd5f43508c10bda1d6ef60ee5bdd25dde975e50c61f76cd36d50ee3bd8dfa2dff59524db9ef12f1e28d109b552cb42f021963f559c843476b5c889fc567b7840297c5a480e18c221dc
+d = 084e79093f1947d6ab9cf399782436e36ef87c59a4c090930c9a74ddb10
+Qx = 08e756774def210e2d6f76d6e4b0b43d86adca0880f017abfc911bafb5a
+Qy = 147e6a20c1aad897829339630c5edd327ef9a7e40795630504318cb71d6
+k = 0ce780ea99a344d67de7921feba6ae062817101068266d5d1a140d2b49e
+R = 0fb2474b854b8e5d6920ed90e69b5b386a1b26a947b1cf28a13f7c5d3ac
+S = 072722017a67ea6754873f833fc51318d41d6ef598d3ec2d3e0eb5bf41d
+
+Msg = ea71cede8b63ddc5648eb244184bae265cd65d50f77a9e25ff93f02b132487c08732544cb88936d4fff7c0fedb39685822dd1c9be1158f647c605c9bb5f6a1ae34722fa08882c14b36b6c93cab33c9a269c7c10f755b6453ed045ea3e56f29e95a9404ba189a0b48848120392b4dcac43148b706c3d9e4c03db410cbe5dca3da
+d = 079b6be015b8006f86fd81c2792bec6b42c08bee2d295cf9dc214c326ab
+Qx = 0e24338d5e33ad12d41eb623ad0905f64d5b75835fec4e693eebf9bba10
+Qy = 101b4297b5b62fcca7c61637a2a57365e911d3bc7eb0fc7adb0a9dc7bad
+k = 0f06b001e5f874d16632e3c8d49f13d70f48ed4eecaff9d3b741f9d02e6
+R = 0de16d8fd7bb1783a2cc4b9ac1563eff3f87e4e6d75e6a32a4aed1ecb02
+S = 040bdb1197ee8ee51e4ecccb8d42dd985913809c131aa9224049425a052
+
+Msg = 319b41d16e18059a1324c37161c937e882192cd949c420ce9c59208a0ac208ebb06f894a7fd78df2a3c5f23f25dee6595d3dacb25a699f115dd482ccd36fc54ba29dda279335424c86b07a1b1fa76a5411bcecaf4d37065b229cdce0bac75b666c6626ec37a716e9841be93c907f87453ad91d36846561f284421a89013b88c3
+d = 0ca9d751a060fde64336cdc88122819f4b3cd1b4e7df42d495197787894
+Qx = 09549785f4f9c71f20133f5a1d409b244df55445beec404cf8cd4d2cadb
+Qy = 1b246647d7570f052840d4cc01182d1dc3bf357b25e5966434e1c3c2a30
+k = 09e99fe741cb23f7eb039f5df8414d069b5c2e3c144dcd6cbc6da56ef43
+R = 0cf00f519c18e7a0fcc84c1e338158399f16929ad89842ba97a4afb5bf2
+S = 05854ee1a6aa5a6a74bec0b4696e80aa275210183c86f45dde7002d7ae3
+
+Msg = aebeee215e7b3d4c3b82db243a47506ffbf2263f6fe9de5b69286e8649d9218367c36ba95f55e48eebcbc99de3e652b0fecc4099714ee147d71b393de14a13e5044b1251e40c6791f533b310df9e70a746f4c68c604b41752eca9ce5ce67cdc574a742c694ada8f20b34d0eb467dce5566023f8533abfa9688d782646420c77b
+d = 01dde4b2d49338a10c8ebf475b3697e8480227b39bc04253a0055839e9e
+Qx = 0504bd3a97baf9852d6d46ef3db78ee7555db752120d020cd056b1b4e50
+Qy = 18dd305f6a15e91fa46d2a6d30f2ec8fbe2baec491e26d9a2ac81155c85
+k = 03b78d2772b8ce01a00ffe2e6be2f9e2ca2c89ea3b29bec6d6cf31afe33
+R = 0c0c51fba155f98900eaa2d2935acd615e917f9dd979dc8d92f1d6e00c9
+S = 08c8354f95e24ed13d8ff3755e1122dbb4117c76b21b3bdc7f4dd856f8d
+
+Msg = 8d353a6b6f35590baef59b638914d3e934d0145b045d221d846517ceddc8ff5e3d28826d3459f8ce1260f705e80923f39abc73d5949aa7aa8ad1734be0e992bff0c9a8f4cc9bdfa430d4cf52e29d3737b0cd3231b72b16e15e1a9040b832e4a920b4a1d94c4964ac6c8abb75bbbdb10825f882ae44c534c7154c446421a04d87
+d = 02c8bea2803fd746c874fa110a716538c179c82712f38d33d0f6d037e7a
+Qx = 0a034560353561cde19db89dbcad5c9dcb74e239efc604e86ff38a0577e
+Qy = 185e0b02c48be2e90c916a7c8ef2b41a57ea8d4f21d8cd3a0878a03875b
+k = 02e39f851c57643bd799c4f3b2fcc5eec8ff7f9e9e279efa647f969cc6a
+R = 09b2ad7efc7ed60d9cd3dedbd4159b1e05f05ce5ec2d2cdf7a0e0657482
+S = 03fcbd4ace6a140c8bfebe36ff30848966bb0d3eec323cc8ddda55faf00
+
+Msg = 847f134b90f10ba3636ec24f36a94111f26d58428fda5bba4501e58c7bb55809f52320cbe9e0df55af1e40bbac9f3eaa26a55d78b60621d4356d090d98363662f406367601eaa9eb9568b1a1b319730bad7bf6a7ddf1b45eb6922faf8d065c540b671c50df758ebf8c4aca6f01878e5e0012dd038c58833e2b13ebdb9a9f3fc3
+d = 0b9119b3b4b30cbfb98ddf0a4f6953417e515fcf0e5a94e83ebc1d1d14d
+Qx = 1be65d340f7e99067bbbf961c2b357e1fd47a74393cae5f93a40c5dc280
+Qy = 0c04cd8ca3ee253b99e44ee6bc0e52d2f016b16f59c738b9f2bd8c1b9d8
+k = 02c851ba0123ff0543808931ab3857b5c15d7c10c343f232913f6e0c92e
+R = 0ba2b33550878e223cacb80e45e382dae84e76bca5a2ef8371b84d08572
+S = 08c370f82506e97cc15837f59e9779448decbd87bde0a463bc14b18edca
+
+Msg = 99d23950493bdd931915e9f9b65e4cd1329866c0071a19d4f7d6fd190689275b7b10fc07503dd1c27a4da274dbeb3aa5cb0e71e9b7b03fc2697729b7be913756e6760098951d7015df181cf14b1e0b954e6260276af553e3e59907794b863e941950718ef154669c5c262946ba120892e0239e05910c2194f712db46e37e53b7
+d = 0f4ab2a573f3771d1e4222e251faf14e06cefed544e804c299c9a8395f5
+Qx = 0b1f973d6495d277e24320622b9b99fccef8eb5c1c6952f35b82d4479ef
+Qy = 161dceea4d3c9caa4f640f51b37fcbd5b8932642a94c8e7aaed5db17fdd
+k = 034ff28a5ed6958514c603b3af5a991e2e9b4cc2c0a7aa73ab2d70bd05d
+R = 01abe4a7b27395a37089f91eab27ccf29001ced1bb3348a6f919d466477
+S = 057449e55d3f2a4004d647ad6e8fbbd516adbb4de40b1a872ad8ecf67e2
+
+Msg = 7bef2487bc2bbbcbcc1570bbd4ed437c0dbcbbf63f666a3355aec49ea6ef593da25aefe9ae0d94db50692475425dee3c88cdea975794ac69142c25732f3541457d68d9101c8be069f2b515aadadea2019dc7abefa6c12cb3f76d9f4b5e46546f77eaf636aa8f2329130922111151a4df913d18b7cf9d0308f01ad84d878adde7
+d = 0f4649cf30d4a5269296a45977de2652cb06d3ca2aff4475bb24517b927
+Qx = 100ddcc8e09ba2122a6535c6a0a2dae83abf9e17687b5f6aae7ec6a2df1
+Qy = 048f5587360ee251925b7ed02de82307ba219a707705623727f98346a26
+k = 0a38b2bd0e9a5044db19d4312ec88d19ce1a9bf0eede8c357f898b0bc67
+R = 0d0ebabc8761ea215808a2c3035b14b614f64be0c2741b3d7789a8659ff
+S = 0f9e742bdca44c11bcab196f910c0d887e90f250817ee7027f6df8207a0
+
+Msg = 87c717eef6dd3c7434b2c91de05723783bef603d170f654b49a04b067b077c405d2d757ce780101b930196ca4261efcfbd3fc1ebb762cc0eecf101072988aca508c41581936526d3f337053000dcf77b16172492c5d654c6612bbd2523a6ad5966d7091697a29ce882fe331f79a7eb59e5a3fe536263083cc59b8133bfd33c1d
+d = 0cca24ad914c24c011f41f80d27ea41caf41fcc8dc9dc6dff5248b2b474
+Qx = 0175b73db13324a678b8afe086944a7ad257cd33fe9538c59b9177d1064
+Qy = 16a98ac9e0ff59de1ad94b50f8c709ccf4342f983c7530be64c3f1548fc
+k = 029c83def3a5c386b0bc3cf2663b8f4b02f26c6e3e14fcb17e9460087f3
+R = 061df783609ceb355aba3b1753d38f42434bd75c8354029966e7a788be0
+S = 01e8a093f53a1d73d5a994b97f2b2f210125ecd3dcdf77c68ea3199856c
+
+Msg = 9bf48c2aebf473b3a4a928b3b6a4d2fb7e9193c9e60bc2067f9f03083a8cc7b892bdbf05601118bcc34dd283e7be996bf19b0bd36727eb9d65276b6517bf0c77ae0a9091e7a9e46182a2586eb22324939801034e5ba94ba30d1bde7d8fed51eb71036fab6224f8ff30a008422efcff7ea239ff23b9f462777e62b41b396c5dc5
+d = 0f5e12d536ef327e3b0ba65ac5fc3f7f4880f5968f3340eb8868c1d47da
+Qx = 0b2910f5de9475486b3975ce91c02187e8803e68586f3a1df14df67648e
+Qy = 0f28af5363ed851c42daaa810afa1fd0d2e001da7764671fd44fb6737c5
+k = 02a018753965bdfda98512c7f9da3e9235a4a77aab9804437b652182347
+R = 0b6fd02b2d84b7baf1a5eb592cde667ed6d4c2c821ca336027a72d9abdf
+S = 02253faa5935885945121a374010b2257123cd5db4c54a2aa0e08c8197b
+
+Msg = 716d25519ae8f3717da269902be4a7566d6f62b68cd0faae94bce98c8a4ac6f66215ebac5407d6f64adf9d53f79f02e50921b6f0e8c805926a839443d30d9294eaa802faa7c5471d81fd1db148cdc621a8dd0c096e06fb0b71943337d5325e1bca77062684873fe904ed9012474ceae5b138e079f941a665a995026d13d7eed9
+d = 08c30d93536b8cb132277645021775d86c2ba8f199816c7539d560ac6de
+Qx = 0d69332763cf533d48e56065e1b5255790f8c0eb23471fac9b945e62195
+Qy = 0292df8c77d9a6803f60bf0722ed57ae2aa3bc816403b000fe2940e02dd
+k = 050967928d6089da5b16c88b7927de210325c8d8f5e727fa1ba3bd95b5e
+R = 02434697cb5c2ad95721943154bc81e2ae16332fa6629788f505bbc1522
+S = 09a5a6792b1b9c2e200ace5a3d50c04f69084dd9222c021ef5fce14d4b6
+
+Msg = 01e76755007b2ee5ac9e1d4c8adabad6d0f9c1c08ac6e2622b7c1ead89bd3ad0921b9525b49a780a262fe8fc0904a80391717ad7cac9607de55f7c744af8a132ec45ce79723f4a4a8c8b9ef658b360bd3890df164c9f1cd74eafb74feea251a34514ff2a57ae7a6d4bec2067cbf6ee4fdaabf13721bf9ae178b9034ac5e9665b
+d = 0fa3f15a506ccf7b50bbbad0a54d3223f5a95eb54f0d1f4e5d0cc21469b
+Qx = 0e797527d57fb3a18c71d1e82e7935e37e719439952d4b972f0c1e0c835
+Qy = 0a345bef4c5015e97a148b8991bed4b7ef48947b12f316b5621e94d49d5
+k = 075afdc12d4d50a7495f5a7d309696dca23e9356a0cab11c3b3d7b8c54d
+R = 0960ef460000fe8c761038bab7e29d665100494d0874b6556862c2808aa
+S = 08d3c004426dde6c18b1c9ae00a44ac947e36755d8c40eecf47bfa963fe
+
+[B-233,SHA-512]
+
+Msg = e95abeeb2c51a8cb75ab74253dbe130b5560cd52e2a63d501d26e1458aa568aca6694be91eee5fdfcf582c47c1c727084ee2b2c810281cf9b095808bf7e7c668eff00a6e48b06df3fe6a445e092c24d5687d7d89acc8063275caac186c441bc697b2f67aa71b03294e1adeb7e557c296dd91304ba0587cda3c984619f1eb4f2b
+d = 06400a4830889115aa88b860b3fb65905b01fd126c4aec2785518c2543a
+Qx = 1a2051662c1681bbbf6bccbd33c44c7c7fc80b81a1bce14caa36a73f7a8
+Qy = 11583d3ba8f22080488471d8103f868100a97af94809b58bff1435b16a9
+k = 0ceac6e5d10c55888b9ecab8d3f6ada7f4d0bde2f109699157d194efa42
+R = 0c148f2337008ccc3e61501dc5df3ec95d3596d97eae96a7ab085a915d8
+S = 036d1debebaaef50243005e25c791b9674cd6fa986dc3d32e089fbfb2ec
+
+Msg = bb8d8515365d240b2071daef0d80558fd3d0e059be9f6abb7b7a0a5f47e2ddca7d1b3b5101d5c583143258520ce8db0a87f877a395615c9bf879ef46f2f20f68bbc9706f82781fad69019396b27f292cdc70fff1772e90205a2225f80889f9daece1d03914d8776ac5bad24d8fb190ba10a2ca17768b918c2e079d83734eb372
+d = 0c7b73c324250f14fac0edc941f79bdbc6933ee8f64bf94b847bee5eef6
+Qx = 1af7266ee56bf0518f2875d4f4d9ec508a01769d9c1fd0a885a48bbd80c
+Qy = 084167ada99502475478465315bf8163870a9ec1b43f15d68f0304ab03c
+k = 03badc9b8098c3b4d7e943a2365093028b579519031a8643b50c0f81eec
+R = 07ad4fc96c21963395f56eb63e1b0b4d2c93d827626e7bd4448697ded97
+S = 0e7504e6a9f662472e3e6f18a40f7645922fad2ef7313d600a5a6ee314d
+
+Msg = cd8b2403435fac9caeffa21b55eaba52d7efee0f89df7142340cdffeb89556303ca01a800429397e2ff6c746743b6bc60a87133274282d4cac02e4ca90ad95d80c93b84163b96296f67d40b2a1124b2b6534ab6b60fdee312fbcdf468d0e84eb85fce4ff360136bb31ced3998d29cfaa3ae685e638ee272058f123c4f35f8b6b
+d = 03db7f28e161abf52ab0adc8c4c8544fc989af081303b8688f22b7b2eb7
+Qx = 0ab94312e53832265b929f3d529bec33dbcc5c17b969e0afbe2d559ec39
+Qy = 1d53b2c1be229e2c224e6e9fcb8bb0f044f3f9f5677c60bc9454f36eb06
+k = 034a8f980896284fe6d28b0b49703f1384d799e3f11a04b1e62da12965c
+R = 0e374fb355f30d7e427bc5db99ed76a914d6e286099c72f28c07302c741
+S = 08d5ffd41f8a1fd3de6c433635fddcfc2b21809d91496ac17571afbb856
+
+Msg = 4bb08eeb202564efb5bda40777d71f1bcc4c7c10b611e803e5c570876f3e319e9e2bc2d32031c56a32fc0d1fcf620d4e4377d881e9e1695bcdb78acba370b849115b86c1c4b83edfa03299da8e7fd14c7cadb81a8e4911c8e427e32c8c9b67e317575331967cf58085cff0c0d48ee0b8e7dc0b49687bb1c70c703a5dad08ec81
+d = 07e9d2fdd017d6da6029e88f78927d9ac9437f542db1f1fa99e32bfcf1a
+Qx = 18429bf08752aa470a8f0801170a7ab96adfb168ee8212d76ab0b994e46
+Qy = 072a5071ce308d7daefb3e8f4da4681842ffe0f35dd8b071f0775c83f82
+k = 0a0f330e011d34714875500b70c881ff6b1c9e96da930eef75ec78ac120
+R = 0439bcdb86d40e8f64db5dbead95d85d6a771d811480c5765ffcbf75422
+S = 06c01f64e2812d18b0946ea4e6599e8cfca0a2b606c3c35c803ef2cfed3
+
+Msg = 0bce683d835fe64e6484328aa13e18b0956f6887b5e4442fce36ff09aed015889794e79da8aa60b4be565c78685674c51e1e7ac60db6a763c777198a56e382a03aff8b40862f961ae23e8b8683b76a5577769422418972ab0049119382edde9e752b42e8b93f403c1ef8665d7ce8530ce4ed9ebf6d397827cba6b7645e177231
+d = 0c94052760fc74c2b405ee4dd5dd2a7d38ebc16df9cc32df706075450b5
+Qx = 1d2a5ee02d97f82ea9c8833b825cc57b0cb51d3f2a2cfa7577eba676eca
+Qy = 149c68d98d0e9cb242962326a26164f3e3cb6d81b51f281474b0f8d333b
+k = 0fdd3ade90da682676d40008cebeadb9b2378d8a821e9e9428018cdc768
+R = 0f6d244daea95002daff2ff6513da694eee58f8b6c2d47ad121be87559a
+S = 0b04788fbb5655a053d0fb7a38c39e1fef68ff17860442ec8b8ad049842
+
+Msg = a6defc770426daad4dafba3bbd2a69881334f7c31269b297e440926db54cdad3fd7ad200f5ada2b72ad221ad99a06ecac9c2563a8deed89f0d0896991d1a652f6fa282affefbdb1c1985652300d1792725071631d75a182b683a48448063c7d2563ec3d430e0fd3acea33a35cd38ec0b5b07af96af71d0bfcd879d9864ededf3
+d = 04076b93487c2da8aeaeb4725fb53b7b41b465315335c18c6ca041175b4
+Qx = 158755fd290910498f6c8eed83bcebcd1fcafef4878c860da118efa250c
+Qy = 1781fdae501c2c147eca2c6c809d9428fff2f853b57c7d6add70fcfaa0e
+k = 07debe933553ba3420aa06e1bc52a1653f8a19b59c0bc9c47212389442e
+R = 09e09c6d96e33c845535468ec7f5b79cf30123538011d0b5ffd935d168f
+S = 0963bbae921317666f5852759e9ebf05cd026a5d9f026942835ff0daeb2
+
+Msg = 7803cdf4758c199962b62943f475c6c31356f5d9b997a12e21146a2399cd0dd3b97a860b2ce639e2801571599136d4a8cdbfb12fd1a5ce22374991e090533ff42823a2c58d2076b772814eea7fd7a1fde68263ef912681c72c7aa3e5a7cc44ee8c65e72228b7631e600121ea35bfbbc783b6ae3c0c8f80198ada218be533760b
+d = 076ddd73ee4fc1f5e6766e229cc7236cdfce312417ea291f7c3328d5ab1
+Qx = 15185e029c0d4eb5102e0fe900ef3c921acc744feb44570a288015d0908
+Qy = 0ed56bf93394a434cd84b521040d40452bb39755da5e273a05e8c0ba792
+k = 084e9e4a9c84a602c18bbb6b183d06969c8b8538e2ff901f1c2794d5eb5
+R = 0fde8e9b1959477ddb3423661df1e7182e4b583849d6d17fafd7dc5406c
+S = 01a12bd30e9c8b74912c670c0845ff5ecc77f29797160bd4992efa61f4c
+
+Msg = e789461e1dad0b6e21abeb6ae2e96385549d1bae39415188c8f833233da6a3328144c97ddb36e0ff4d9e19d84f869e79e609c51b32de59892fb0446dd28cc164a3e53534c950d26f87fb74e682db2038cde778bde06c3ee2eca2a077d8fcc2b0332e352e0e7e6487444a8ad60e78ff213b16fda9faf374dc6d27b7a3c4c6d196
+d = 07e1f8988ad804aae7d09a99be19384cc599e7652c02c391542be74b17b
+Qx = 1fa4751e507740a7345e06a8964022fc6caa901cf0c2077a2c0fb86be8a
+Qy = 0683c593a0bcd123d958deb6b430d49d5a2386d44706f4149dc526ad896
+k = 01d288de55b90dbe72cd8f1f86a3ffbc2902f4b5f0cf4e641d32aec6f20
+R = 0048d16d87dbf4fb8e994dd874c10d5d16846b9ce2cbd43d09df62ca970
+S = 0e2ee47f422095d629c188df97e2839fc6239b9e2dc26baf8161b037236
+
+Msg = 9b58c145d1b6c887f2b25fb672cd49c3a1117224be697c15182d4048be92968a6500f8bcf747fcf33145c13a8d72e891a6e0c4c7310c2b62f3181bf586fe32f1ecf4feee8c2c8bf6c2bfdf9d5f88981ce080095c93e49a772d8e7b59f9cffccec3ca2f212ef4c6748f64e224f4f098334d83108bf6f8c7b43c5eb549f1526897
+d = 09b2292b0244c2aabe8b43d95039984d504ebe05eaff318760e4dee739f
+Qx = 12618d89f50b7f83ac470705dbe9ed81beb03929732a3f2aa7a636eaf59
+Qy = 15f0f70c808e053b112a8c32ee422aac2b926c5b6a279a787fddf819990
+k = 0fb38174a83ceb9236fec8ea39be2b3c77c3dd2cf42d140e27838202d08
+R = 084941856a387a56022727f81a939d77d12b01dab603ea0cdef6d9cd6c0
+S = 0bb9fc30595f94d664a590ed4f163e4526809819baf96bbee629ff86bd9
+
+Msg = 52310a901fe9681a23dd6e02f12974d57f2c4f653322d9a0ff8b338cc6c2bd9f4765c90c6b3c9fb17df3f492e67d204e39d81a8fdeb92c852a1dcc6151ed6c63049037235c6751c9a902748163a567b714725b4d3995e0edbde03215c645b1a1da3147f7406245432800c50f823a1f991c863427ff4c68e4e16d1b106ee40dd9
+d = 07ca463b50fdd92d9163f1c2bdfce2ee45ba1437b79162e3e959b814cab
+Qx = 08eeeb146216c73ccff0096e1100008f8b1f3f0c5754c0abc4ed39f7f63
+Qy = 18c9228b11888edd66b2e661284f583a0e8d3c3e922932cd9fc1568f959
+k = 0025291ec0dc2b0c709c5e69695980564552545c2497636b814aa049ccd
+R = 098dc98457ce6e69f77123d5d2460ff569786dd60fe07e847ed5bc14da9
+S = 0cd320afad2a4247fea5b74d78dc3df8967ab3159b4c8b191814d368dc2
+
+Msg = ff419c011601cfaf833067cf28dbe6e935ebeddf8b5111a97f6eebf3bb28376334f329cd877a134b074790a073db766efe018fce666a34650cbac285ae856fb6b3b8b96877282bc11cd9f9c8e510ed1f69bc2725a44a1d2b35de1edfd8bc9d20c7525ab0bbc27662a7cfc1bbd1e0f4fce5b88411521e3893e027cc8c73acdabd
+d = 0c3844750f63fe0c2e930bc38fe88522f4e72a2fd0db9778ade20e939b3
+Qx = 075acb00b5999f8b272a15a2cbdf8cb630dc3eeb1e78e58f58e467396f2
+Qy = 16711aca424ca335878d273eca75d804d3f009a1f3628568530ef265eaa
+k = 0a63e7a20d100f14b8b709f0a6c383166c2151a36dc471f061b0f20dac6
+R = 04063be9d8e4f0f9afe0c79374c69b36910b5d2b1010e0f4db2e4cd23da
+S = 06a6eb90659aa79e4a2360ea9ffb99a415175dac6c3efef104bef6fd57e
+
+Msg = 05a89c4824c5de66587875011e704bc6e06e991ba8f3aed331cfffe55aa266a08c729f77b8d082dca4d286b2d451ea838d726cc2cf298fddf2d7376714c5e37b64506f353917caec525a1209391449c078c5197a371feade74f8fc8a1a1d67576edfda13c14ad324342fc0b09277941dc072ec0d39434ff1cb91fc59478fcde7
+d = 0a3bea235dea86506be4476eb7999dcb8e584a34238c4a894ad6823b93f
+Qx = 14093a072c21c44d1c4beddc5c8dd9a2845db0935bbb4e1c4edb0aee032
+Qy = 13286ed584deb744c9c35d7ae7eb9cad1c7ba2b670642de0399b230716d
+k = 078eda19f0cced2f84c1a7b354e5a79bec035b8bb279473f32d60f5d17f
+R = 0964e817f0cdc251eede4157a9bd830c476627c3f27d2931b4f593b0178
+S = 08dbf34e597ae06ad92b13900a4944e54a5bf0f16f586baad157da6dc96
+
+Msg = 13e6b5241365d9d0ef9e8b05cabb3248afd221ec02eab92284b98bda3d9272184bfe5251d35705defba5085381430e99b33a3ab77d7870e5102757d065862372df2434a25556b76e54ebc39d4e6c3aba5cd6acf0c335756f7d9385c1068d4cfa37526a9a58c0ccc7f87a8189176c5d4f201499236058ec061357dcdb5acdba40
+d = 09a367cd1cffd8dfcca179e167ea437ee48e9b6f42559dda9224701d3f6
+Qx = 1052d751901f6f8e61858d3b15eb59dedd21e4e997531ef65622d575029
+Qy = 112737be67ec621509d73cd613d7b448035397fa66eb881f90a6d531ea4
+k = 0d8dd8f1cab623ba6a4e840962fb31de97a4d14aa6dd34dd21154105030
+R = 0a8276d0f069f34c60b26a55d47df69e4c9ae2981afc59e14b5bfcaa498
+S = 09351c4b3a06b839eb2e9f450d9c3d15efa45509886ea3f2610ee1dd156
+
+Msg = 139a1a5090b97afb8fecfff8745efacf7dcf91a4393a7b629564e598d58d5be39c05c5830d4c8ca85d29e9e2c31ad0447864e867d0ef4788ac734f8d871daebceda98d449308c2afbe97724c3af8a468f1925065f39e52ba4b7d15728a744b1252a20476dcfff7bcb82aa72c209e72abb3c24419bc26191390ffed340c1b9c6f
+d = 046f4ad2522e78b9b35297d28f361fb0ce82306322aedc119251d8241be
+Qx = 0b976c53a966e0834d5f6bc3af10a5f12cb6d16cb2303a3c6cee7d35f22
+Qy = 1a1097cb56662265f4f2f52df375d70af086264752477c34c6af522f1ec
+k = 06a0d21e5aadcb0c9e3f9fedd2d896b0236dc90e33778fb114e970122bc
+R = 068063fe0a31b7e7925cf8959c3486985d98f58224d5f67cd0218af192b
+S = 0f11a22ced98173040062ff9e69d1b2a1b5a939eda0a6944e96fc62fa4a
+
+Msg = 3315e5cda5f252e3291b61e493ab919c20a8af1286d9660cfa2f5ca38b6defe19ebecf820787fe692d04eae8a5f5d37abfb593309569cedf45efd0cecef6951b718924c8380ba52e8ab8c9bfb2261ed5f01cc5a5f9fc5fcdd269a0f122c597afdd9a836cf8f96838c3e8962c1788c3ce4128719b3ef4fc88569643dcad6da16f
+d = 0ac82137e9c7a5ecfb8b1a7df9ab50732934566a392a6c8915ee8ca8144
+Qx = 00f7f835f8223fa6c49eaf6650e33dc9d09e1d2bb098925d908606570b2
+Qy = 06e659ce8623767e8214b076d7588746bfdcbbed59b75bb19477366cc78
+k = 080655784e3e31c6a498a63d4d84f7e5a353a66641ca17d4e223441bb1d
+R = 07faf31d1d31ef4edac1c63072350536df84c417e0ef808c6be39617e74
+S = 089023aeb53ddd3e475d11c53479863739e62dd64348646581012784689
+
+
+[B-283,SHA-224]
+
+Msg = 067f27bbcecbad85277fa3629da11a24b2f19ba1e65a69d827fad430346c9d102e1b4452d04147c8133acc1e268490cd342a54065a1bd6470aabbad42fbddc54a9a76c68aceba397cb350327c5e6f5a6df0b5b5560f04700d536b384dd4b412e74fd1b8f782611e9426bf8ca77b2448d9a9f415bcfee30dda1ccb49737994f2d
+d = 299ff06e019b5f78a1aec39706b22213abb601bd62b9979bf9bc89fb702e724e3ada994
+Qx = 405030ce5c073702cffd2d273a3799a91ef916fcd35dfadcdcd7111c2315eba8ca4c5e3
+Qy = 75988c6602a132fa0541c5fda62617c65cfa17062a1c72b17c975199ca05ab72e5fe9c6
+k = 2af633ac1aee8993fc951712866d629b43ed4d568afa70287f971e8320fe17b69b34b5d
+R = 165ce308157f6ed7b5de4e2ffcaf5f7eff6cc2264f9234c61950ad7ac9e9d53b32f5b40
+S = 06e30c3406781f63d0fc5596331d476da0c038904a0aa181208052dc2ffbdb298568565
+
+Msg = 44adcb7e2462247b44c59608cbe228ada574ecb9f6f38baf30e42b589fb9b157bb0560e5a2aa5523b71cc0d7f583b502bec45d9b8352f29ee1842f42a17a5b16136feaa2efa4a0ae306402940ecd6b71e57d1467c98e7960de2a97f88b43487e4f4016af1292381d70c18c7e6eed99a14cdeb5b3caf73688658e4c5b54c81e08
+d = 09c2804f8cab768248fb3fff8a055b3f4585c00de5c1615a19f9425b9432ea09afba8f2
+Qx = 2570ff62b03a5124f08f752aa71ddc57944cd94197fd286d5a2a107b116d7b8ff1b0421
+Qy = 37714d9abe9aa0a9668fce89a3fcd5cf2e4548102a181a777c9b3f1008ac6e8d3a31a2f
+k = 0dab5ef658ae3e2ce2bc5c88a8b8022a0ca5eb8524815ffae414327e3afaea5fcb8a7cf
+R = 2d99f82d92c9554722bb793988af0fd0bea776c5608f5939db7c8634eeb24ffd381dbef
+S = 27ceb1d01ec9a3ec0e74d79e08024359e117488020de6458fbbcad28b173918fc7d129c
+
+Msg = cffee6252c7eb6d91d8fe100a1e62f0ad9f862d78ca2b747a6c17b8c9ea8980dc239b3b673310e6e7483582399163e39d889abc1a613fe77849ebc09b4f7f4fe0688b8a9869ae918a88294c7ee199be50ee9460db14725ae70b449d0cb48f30e7d817ec02c0cd586119341dba0b74f0279330807cfccc99c8c340b72c1764a45
+d = 2e625a6bc6d0ce7c06231de827068bdb0abc8ffb57c82b35ee3a0f873b9473905974d34
+Qx = 0458bf39974812a4e0964c31f40083300454104c0d65f22c5688bfff3c256b7ea958900
+Qy = 738dd33e32b9af93ade2dddf4147187a9270543afdfd66a0f2a53d6d3d815ef59795f60
+k = 0a9388815c528fdadcc5d3b125c7a38db57fa8c163ba795ee00e8e307bf760619e705c9
+R = 2481571400ecf9dd31dbd9c905fa1006cd5bc7afae759da3312ead8d5a7dd0c25a37ab9
+S = 13952fa427d348b6347b9e93d4cb2c4cae3429dbea6aafd1e58d5a34805098722b3b8da
+
+Msg = d058ab5dc07228253707ef224897ea0fcd09c3d5cc91fdce9e03c1c59c53fb4596be2ed929c7455e67ac7f4891aed3eb06ad88f2c4aaaabff045b959f900d1019d706b60526375851bb891494e99995928e4cd51c9616aa651ec77bd7e398916bb9ed3156391bf7fb1e29181e2b011dae2edaf803607def2ac6b194929a57f45
+d = 376ac24e1b86f8a55c052d92a0bdc6472fa03acdcdbccbf7c321ec0ccd97aa0a66b4181
+Qx = 7247c755b23bddf944e29348da82495b4f61d02a482c6111d8698cc77e8dda4c341f20b
+Qy = 0f8c199138e1f4f8344facd90ac62d55f3c9a15ba7a672ce40241aa26419af790cf7dd6
+k = 25d07c7afc5a335c2bd7863c1965a48c12f2687b2a365a7c2700b008ee8a0e8e35a68a1
+R = 23fc2837a879b79e470305088acf596eb0159edc2008478cc4c3841a1bd66fab34bbb5e
+S = 0a909b83bf77e74511063366ea1d1308a8a544864783459a60fb2669785ab1af8f4cb06
+
+Msg = c86f2cc7ab5df5cf1a236fd83792769474cef464032800ffe98a44cf29dbfb6f24088160eb31a11a382ff2a49f3e05e983462f5304272f96c0a002b69af3d233aebe867ee63fa46666760a6889d022c18645b491f8d71b6a3b6b4ef058e280cf625198715b64b025bf0449445d3dd7e1f27153926e617bd2c96638345431d1ed
+d = 2b50a6395fc02b9ac1841323de4520292f913519bc0d6a471aa28021322fc4dbcd7b802
+Qx = 696d5ac4bc40e679524e246210b7bb0f93ccfe7dc506ba87be3fd018f829c93e62ad1d8
+Qy = 65953e01d9db8fc5d64516d864a33aa14af023e601d69875ac0f7af92a1e78aff0e475d
+k = 0aa25b43329de4e7739fd9134e4f4b3d68a64e55af47a2f6ccf71f518f19059b68d34cc
+R = 1338a5dda5fa09667604a6a7666b0e54e6b688b98b31c25d037ddf55ee6bee7565dad09
+S = 00aec025232c16e778f90785ded5348f3d5345b8344b2a762480383777328e0a0b11cb3
+
+Msg = c1328d8d2e5b6ffc850a9600bd6482518ddd9cee3fc9140febb72bcd444b0cd7e8074587d51b62cce4b3d4f34ad3355353fabe363369cf790db2df9fdac3a0ec4757e2dfb3b683eaa3e26531691ce765742e1c0bdc0e1028d347b6085fc459df0989c6a144271454eaffe413cae2ad7c8b2371fd2df1afffe56df727009765a2
+d = 24e5889722f6c35e18ca47effa9e415b1ba790066a91fb3c9f7b001ce28fc732b09bc23
+Qx = 7d4a57e6aaec6b51dce5408f6a7fbe9ba9d55f5abe2da55fcf015ca25dd74eb61c1556c
+Qy = 2123390178b2992059151afb51ac652b364f562c65451eccc65d968e9e7210921c93c9c
+k = 320d2a7f48cf3583e8d7e712b330d40ddbe4b6c128be5a43d72bf57d4227603762de7f0
+R = 09806a8e70742c6c4a9ee6f77fe7a36489e1fe8c442ddf9cdcfa61f019ab9b41241d949
+S = 061fda247ba7c198aa532906bc01d509088d6c2ba0f14ca3ecc5ba36f3595db1df3e64c
+
+Msg = 7176b7013ea27e94281977eacb976bb31c753bf80fa09680a29128a6fc15234f79f0e9900aff3217ce9be72c378042c6c34fced0158740073d1a985fa25987fb218002e425868fda5a47de51abfd04de34e2b8634cebfbdc98e80f93d94096193eaa82dc8778fc23f3765c7acdad94fdaa272df0ff0f28190c10a462ee78ac92
+d = 056d15b81f40b6378588a5efe43e21b95e18120d514bfdda0e7759a1d0766a8a35ce5ac
+Qx = 306cb78fa576bdd2f43cf7b71d7e66a98b850d87ac087dd2e1ff62596a2e8d4cfff1344
+Qy = 3b1e3b12db842e00c2faef04d3e39cdb71546e4e3ecf21eacb6131c3501fa30edcc0b70
+k = 1e8969d6cad41a40d8306d2a8db3290d547106eb59f661e0d0eeb163044a92aee4483fc
+R = 06786637c3bd5a95eba5ce015f151d99845255175ebb9e593d912c75cc45723612c4ed5
+S = 384471c17c45ddcf62b588993835bb913be88f7a8e46e52e211972ffb3b7768410bcb7a
+
+Msg = 4c3642ba040a9955b9d50dcd1c936688c17c363854358afa8ca49c6abd906dfdc4d89bb4cab0bbc363fb5b74e1f004d4b09ec9dfeed4c0bfb482a9061a1f487a3d79195ff7b65a0504bced3a28db0ebe8fcf8ab1ee4a3ae91324d15d890ac4c479144dd5538d2e36d3a587769ee9cd2d5c6f85a03362a022fe0efc4a3902b71a
+d = 12fb2fb5bf5f7e42a500154823a174ba2d05af71e3b0cf47fab46e673ea1822f1563def
+Qx = 2414d172d74a6281169835d18bfaae91f1f1cdfa9ed451884466e63160ecdd4a2c7906f
+Qy = 2d892bb19b47a4fd9d851d3b101ba99acf6d11345596635cedd5d7557427a2896a913c9
+k = 20786f42d77195bea5761f86dbed8b452f858b447d2f3775ba2a4865d738122363b50e3
+R = 334507412368f08bd0992a5d56581ea7139e8adc88abe4bd80dfeefdc7a37a481b18609
+S = 0fd8404df06a02618cdbf6c28610d5dfac9907635d9e5f2887f11a7f18cb8b7ac95b5d5
+
+Msg = e471f39c18b081362adc7da47dec254dab8d765f005ac574640d78c14222639245563912d942f3be212ee3cef134407334c8fe3602fa0e1629de5331643d76715dc1b0ffcebd484d86c5211be4b285a31688b205fa988e6c15b36daf396ccdcc209c7dde2a732f5c31c84c7ea041408ebf15e56632583af0131bd7f531b5fc45
+d = 30096c54fd480647e017f8cdbbdef292e799f054e3279d228b09816a757566a744a8266
+Qx = 2d4b28fec18cd888017fd5a27a375131bec3aa7195c0a4f255eeb3616437079e356a6cc
+Qy = 27c607dcf0b068418eaa7de8da6f9707650e8d95aec571f7ec794415fc175061b451519
+k = 36880905a376faa594978713c2de1a90c8e27baee65bc60b1fa6508fab5abf843f66ecf
+R = 295193f1c64181bdf749987bbc8ff2a188126131f8f932bb8ca952ffa201f109762e18a
+S = 381c496b4035bba880225dcfe74fcf101103e38f9518d9427c74a5ec86ebf8f7183694e
+
+Msg = 8a93fe53e83075c4025228540af7e96a588520da34e3eadeb99a4ab2f3dbbb8f85fe63a3b86c1f4ec912e665ca05b43e869985eae3791b91205afb1380e16c25b74e6793fa63e4a55dcf25dc22d03f09deddeb9042b620434111afe08c5657c7d754af66ad91a1b5423301b1e8e6389a1404060d1b6a99fe0f89598482979e42
+d = 0a1b7e9c8c2dc25b494b5ef3195b294e41cd3c2c35235ab42542bd3e2a52d5826662bf9
+Qx = 6232063dbb66a56e2a92dbdfd9b3c136eade9c214d831691d9b49c56a3962d20f14b8a9
+Qy = 1b47b85bc223fde1918abf6308b74dff7f3e686af9c9d7a1855a1b77984d258c1f9aeda
+k = 29b4221eebe151fe758218138535d81182c991c3b7fed93f9a6117e98c1c2f97e546937
+R = 1f8040fad671e2f32a1094413ee955ea5426bc906b8e034d87d7408e63db173b05afbfa
+S = 22a353c431a9e9315ff69facfa4e15f6e6ee1be2750472823db31b49b17fc759e6b94db
+
+Msg = e193a8ef6f454ca1aed38bb67aca6d08280d421b196d89938c0582b7cde74dafd71716f3818940af412d4a7ff3960a8517aee108ae03576b68ee7557d35e6f1ab823d124de7243dd02b542591f62c80d822608572889573e4c9dc62f99d68e07800da6f83cb6f5e03d1f2ac15f90e38b4f25e0a75e354e4b60cc81c0bbe81d39
+d = 059b1a8fb84530bba7a607ee88310e31bc6ea6a6881603567a1081a05a3a9ff87e719ef
+Qx = 0b9a71aa3cb4cff37586b1e522b0e332ad5962eec3dfeffcef3851976baadf611ae5226
+Qy = 6b1bf0b43b406b5edc6782fd391d9fb070fa3570d3cd5b2b66d7a95dbc45ccb1626172c
+k = 00a77307da9845ec4572a24c9e74a17b76b6393da87a9d7b1b8456235473ff39d243ec7
+R = 36721835be490b5ffc4a42bee3c6d231417f7038c367efd9ecaf7fb3618ae8492906de0
+S = 237833bcc3e4a721e2079e579d1aaf2519c01cc238056fe0c0990dac7fe50e75eaf6f96
+
+Msg = 8a99b9db191f6cabc88b430bc2293e6774d5180f019d871839289e25aec29379f14606e742190b7aa062e3b29fe0254146d9614856c5140c7315015abb98ac00da2c7e33cbcc82c24b797366f12767322c4381454d9d1eeaedb616b0ea5c66d1422da459f18081f4f966d05ce279c6ee69b1bf94b8388d38d4b770d9ed69025f
+d = 30ddc2c7a4ce300cc2b75f0f977033f16c1f8bb13aae3d494c381f9a6dc8622499ae4df
+Qx = 47bdfd7c77ae0c53e327c15c30d90ab1c9b670fe2241dc0ffa939fec3cf6d3c1f493f3a
+Qy = 6a286aa2310a4d0468b62f3144a9da2e66d15bf86f60045824278e8986ff87a27611920
+k = 38afc3d11c66eba3441a5ea298fa593eec57b84ea29973c306ac9d46bb8d8e2f4c8b049
+R = 06c830f6c0be99fea4712f1c75f5a4e439800dcf062a16d93135c3255d3cd04bef5bc7b
+S = 1eddfda0d0e02d382ae243e604f76939dc21f3ce106243b2d20aa562b78e620fb456428
+
+Msg = 5c437b331831530aa94623b1736f00b986172699f0a02a5e5df0008bf25341787e2e66046f2c929dfe0058c3cb89fc5bebbe1025bb1edd1ee31522ed568e7b5b4ca3991afdc76a68cbc2c4f81863e27fdaf6a564fab2c6354e5c657de81390f8a4132669fd24a48580c716b5b7961a9c091f614d11cf45dfdaec8946a54a11d8
+d = 07899928922fbfdb5407517725edf231d15a8b62d90b7fb6d8c8d20424850dc44f797ed
+Qx = 614257f54514cf37df2cd78850658a85ee362764ab8186423aa0f9a1ff486557f8f167f
+Qy = 3ceae9d1370df045d20f576931ca63bdba8885f463d5c82e5edca5116ed3d2c2b0c4861
+k = 3395493478e69e6e1088166f622a4f9ec7feb998aa552b54bcf0fc67c06079f45a14993
+R = 3f31ad171dd59c9deb21851e631f223584b17f72a6807d5239ae31373512def954d5ebe
+S = 28f095ae43ba5bdd899573ce6823eccd8e127c6c03cb59dff43c087ca24e1ce5504d1ed
+
+Msg = 91aa08567d8da4c90684dc06068f69deae240212842ff1786f04ec41b40d9187aa92c76401f9fcedced62876a34df82ad7c1e63b68bb2a972257ea8542bda6a7f1a020c9b122943b6d651abda8b8d322a8fb762eee376daa2d3637a71ed6c4f5cf96f61c0da2d6e1dda3370d80e51da2cbd8aef3267168c67359523faf910dfb
+d = 2a2af63d1171930758bd3e5bfdac62cca1a83a3b55a49b3f80cf0d9ee4b2082757beac0
+Qx = 7dd6fd0868ec478e7e5c08965fa4f1efe8db4d0c04f0b6c63b5dfa397607a0d9d5ce909
+Qy = 54ff4fba9058179a2c61951fb4955cb637b01267f8f08b3aad614738c562f602d498f04
+k = 179482dddd033e8849abfd4991304137044d7433d7bf858a794340ea1cd66e736b821fb
+R = 071f4cb000ca1c51c698c867a78961e6d7defbd60109f79d1d165ed045a653ddebabd10
+S = 1e2975f4a1fce0b3b0e13c3f50005fa664ee9319cf774d2e107c406d36158bcecb0e5bc
+
+Msg = eb5297bf408c1a55e400a20a3c10acbc5c2bc6d6ccfcc0941fb7a6fd4d2834415a6df86c3a6c4b867d1215aeb8222153da8cbbb1576c92c07ca2c36d8f243fd911f9a057e39ee25832454e28d7ed52a8d04169b9b9677a16b32d5d211b8573a8986e9bf36d7206417ad2771daa11bc21fd7ee1029b65ff7c9b2705a6dc9cf9cb
+d = 35994e89e13916ad82608f74a639e6aceb756ff913aec440519946d6434af9a60a6af49
+Qx = 1f7805dfc9f90d4f8a1b241dc9d68aa41cb77b63d530cb3733cede23bb87ee5118e5bbe
+Qy = 1c3f1aa3a1218de78a94ee8f88d3f787fdc68674e31792d919dbca681a6db1dabe89b61
+k = 2116684a4307c67a3d8c1014b33b928a962a8daf86c4031b0c1d47315d74bad7dab2aad
+R = 33cab952e9382dc074d666f1f2ab2bd72ba394a404ce2fd02a6f7a4dc096d713827c94b
+S = 33b2886738d882146c0cd715701fe4e8b94b0d28c73a6b79d2899391119ba910bcbe3be
+
+[B-283,SHA-256]
+
+Msg = f415d0adcd533dd8318b94560f86732c262ad2c6dff9dc83e2435543f429a2158cd2fbab0d96c027f71008c4895ecc644c2ceaefa80937f6cc6338d15d36e459a16bd9387a361a6d800acfd834ad5aecf442e30b70f5bfa164747cf9f89325b80976052a83a5e896c00c54f81472b14329cf23bec10a8e693005de2a506ba83d
+d = 29639da33f48e4fb0d9efdf50bba550e739f0d2476385cba09d926e789191b6fb0a73ff
+Qx = 770f9693777e261db9c700eb1af0b9e9d837ce5eabd8ed7864580bfb7672ced8ffca598
+Qy = 68aef01c8126889204aaca8f3ccb089596f85e2aca773634bc5775ee4d27c77f2af83e7
+k = 32a930fdb1ba2338554a252d1bf7f0169d18750a4ec4878d2968c5e735f98b9d0c25edb
+R = 30cd65f1097d3fa0d05e1d6072675f1377a883b683c54b8a1f4960f90d68f3ee8c7bd98
+S = 15c61ddf43386a2b8cf557760200ac06a480797e21c92e45e6a311e1a508b03c4d9632e
+
+Msg = b178d86c9335b85e02178fc4551769db589ab91d823fac219c7e14e2f029753b203962389476723832f8d9631dd7764e6dd35da290afa42a794476f5c7727b3688aced848dabc9954201578cc7b25801710931f45cba1199d3788d64dc0188412e70723fb25b8ecb6718358150c4037b5b81466dac1686cb5270bb1c72d34bb1
+d = 0583a7ecbf2a975a32d07428d27ac82e5dc13d1466c4fdfc1e6a05a8d9a289f1010617d
+Qx = 3775ec793ee4bff15027c70d9bb5dedfb7d2e41af8895faddddd4589cc5a00bd222b3bb
+Qy = 300f7cd572d82f2f0a2d99a83977ed2034e03fdd76a0267455a524bd8199424ae5b81ca
+k = 1e58b1f66c927f4ae16143856d67193d889debdac8eb03936f1b36d550c2f2639e13f8f
+R = 0f897dbc8ea12f4370fcd08e8700e5e4c68dff97495f401d01b782f2ebbe259bc0dcf25
+S = 3c32424fdcca39f411663284658b8f0c1f950f0cea4354f02f4b359f18e3fefac0976e1
+
+Msg = c8bfe9fa7c848531aa2762d48c153cd091100858aa0d79f994fd0e31b495ec662209a9c8761cd1d40c3d8c4262cf4dc83c4a2549a5cd477726ab6268b4b94a78b1c4a7e700812872d7f41912a723dd9abc305420ea1e1fb1fee41bf643f3a24abd6e8fbf6fde2475e290527724a6f99fd75374bf7cb01b34d3e60d8db33c4de1
+d = 0f817ab1b49131fb9bbe8c112c25a36f064efa85de7506fb9cd29d81b326bf276277f7f
+Qx = 2b3a06e07fce1848494d3227ff77d1c43f4ec3c037ad73ffebfebeeae87d3bff7f7e59a
+Qy = 75df52e6a34229266ff28b1c217538ae23b3912e4bae8de5cad9b57b7c1c9ca8aabb2e8
+k = 0ac57fbb899193b88fbf4ff2c502af72943b133e8d40459a833275212f6644f566f5c58
+R = 3e13307d5fc2b7ad24e9422355150578c78e1c99a6f9a24f9ca2e8bc6856936c5c4af2d
+S = 05e8b77b580cdacc2660e6f8a1877d93c5983d135d63ca0e0b06aa8daedf855c9f661fa
+
+Msg = 9a5f563d0f9fd1f31f3a822de628ae970954f4e71292492d727109036491c29e66b9b0f2c90c26abe94c08502f5e923a9ddaf6a7d91e9541ce90d0a49f03ce4e4769753d5b7d922e1ceaac4b4cfa4262732a09550aa076b8ff9d46a50fa17de17e3b6bd606698464d116fcd5f1ae11bf45b0c48d3b738427cb47b0d1272b03cc
+d = 2782af76ffebf3e2bfc0576b70e4f4bb87c762e2bb230d278ce776310a14f5b678f29af
+Qx = 00dc21b3be7efaba5c7f9f22591327f0f97083d4d844415d3148d227931256d026ec9d4
+Qy = 1276f1d9e131f13bb129a1192fa24602fb508c9679ad2124e49c70a891777cd601955fe
+k = 0255972b5329863f380de945574793beb0430dc416a8f2543330a125ce8d69f72dbdddf
+R = 25bcb54e188aef6e362a62fd88daaacc8e697dceadc8a6b6f804ce4a36856c8da6de97b
+S = 1e12e18e1e281606c16ed1f49804f8cfb33c29b0ae92c072d5c41ee3e6836cf1813d722
+
+Msg = 3d6b065721da9de82cb33ec2c27107eb399b1e69ac8fa51145ed4147e20d72e27434104e76af988a3bc94f55e36677a05182fe2376dbe38195fc6a30673a4dca87336c7304f3f31d49216fbdfea00fd1e105d8b0c13ab11f8892e0045e915c17dfaab07b24ed21b06af5a8cad4f45fbee5a25bb6e87466a7bc422c0bb896440b
+d = 31b827b88f14d3822244809096157df3c0aa99da90c00cd9f0b18dfe306f6881834e6b6
+Qx = 7b3ed076a2901ab2625bf05fa6db10a8c156412fd2d26741738f5eeb6a9189157526946
+Qy = 6a8cc2061352c36f264d23dc2857fbe02af34397ae5130c582e885f50f2c112f141c07f
+k = 0b36f5d6da409c4a27f38ff9686cbf5f4714f4e17234fbee6e6deec97c9f0d4c585d42d
+R = 356911114c9ff9ae4f3a4fcc5379c987b9d298554cdd39ce124f04707e7fd1ea25231e9
+S = 13c0a321c4c5a1e89dacddae38a9b3dda32a20627e53dcdf28ee26a550797c255eefe6c
+
+Msg = d125f0e2e6135567adec9e77da2afc6862e28d618416632ced829d14ee8b61116da59dfb44098a40a0b927731125617e3d2f32cfbd1546a6e758c1ab6597e75db07add52ecb61d37da2e9ed04df95b36ac249f4cbd794cb561655cbbe4b34834c497b3d392d78ed0db8db683aff0076fb6e43acba3fa2b91210cc6cf3fa594b0
+d = 27da4916f1c471cff80bfa14d12aa10270fc3b26caed010c0111f6e5a40d914a3927763
+Qx = 7d8202c88fb915446c521884fb756375a2b8d178f6a87306c1c8b67b926e830c8285c15
+Qy = 224dcebb8a7c46902532870ff855c780b2884dbce2956cd34dd6ffef8dc365b96753449
+k = 3fcb1e759418e4539f9be76354cc1914ccf9a111338890eef723431925fa132ebad8695
+R = 0d4d4f23408db58a72495aaec6dc335ce85309fedccb6ade053c23347abdc9e77a81aa1
+S = 129b6b322573dcc79704d08921cb54f31c571573da78cb09d0aab40c4036ee8f195d88a
+
+Msg = b380f97687ba24d617a42df1b14e5506edc4b62dfec35ed9fd886bb769832cec7f9adae10c21b7cd9152588797b4efc6b2b30a873d3f25e683ea9be070dd69731949a51121e534fabfa3a2eae0ee90a454182248bedf2595cd47ad08614177d58f7a773f5023b538f5f568682c83fb60e3fb1aa859948d01bf7b214e7f2dc719
+d = 10608eb51dc0ee97d6e488a23c582ecf0ea1df9a24db77094d87b3fb6ca98507280a934
+Qx = 399b3e571caecdfa1efb243323159a45618702600b870954cd614e494bccd70e381f68a
+Qy = 2e2fc57721a500611badf48fb435a6e399cea356d281e853f55ef2cf9fc5f70dc8b3da2
+k = 0a8045b4f55115dedd8d742545f9f2bd6e5ab81cdbd318747aebfe9f74b0cbc964b6040
+R = 2d022631bb7e05d316a1b130faaca5af5eac67dd25ad609e6e2a067ff74fd4ba534db2b
+S = 04595f184068433962d250394680701fbd2e2bd613a47e5de68fa1eb83cb08fb425571f
+
+Msg = 3f9ec57e4228e1a6ec49df02c58d756515305e48763ba1dc67298be9a1548576c28c82b4e9b3f62357d9b3c522b16d5c496a39effbdc8290edd2cadc0019e6b9fae1e61238b13b6265ad2ff413a5a0684babdb0013e7632051455e6fd943815213c555dba96cba8911e006bfddec6c3353065004538f37e48df9e339498d85c6
+d = 123f9eb8babed548df08cc3afc1d3b3bbed52b538d4654f2088fe76062fbea75b85a560
+Qx = 3b2e980ae7a847394720a9cb982fc1e41f9381b0f2e08b87fdff1bf891b9637cb22485e
+Qy = 4a367d593edfaa4e17113b6b1ea3ad185b3155b1bcbd9f00f4482e509b43bf7eb67a448
+k = 2adaba166d703d4d2d431a26200acea7fb47216fd04882f91c5730a55c349770d58a452
+R = 2c83e6a7b4fd48e1ba4fda8ed7891425213764078926d8862d0eb64765ee2900b3deccd
+S = 3561a949d583b7de9263d07ac427bc175b75dc52f43f3ebedf996218c94e51684ed5f9f
+
+Msg = bdbd7b7bf3337bd9d21a3c6db379f95408c17e49dd394e94737ceae889f45dc0ff5d48cadc53703a16b5589939506b548f8dfd34c577c084f372166cbea320c8fd07c809b211e0749ea639e68f890affa1569b66bd763c7c710989e491011371eb1d93ed9479ff0216b7f79c901a2023e2cf80b565d1c0517e73117190cd2f02
+d = 06a18e626452111922e02e31d662f4301319946a204ae8a34f06b91dd1b5b96456365e3
+Qx = 77c1fbe6a645b85fa0316ae412e8dc558c7c066d9aba900650749eb7b14a149ee57a259
+Qy = 1b2f3002ff4936653412c8ccb8a67dcae18d78dcf6dcaaa75061013d2134af2c3fa0e69
+k = 21bf4ca10d03a93d4675baa26285aaa554836bd0bab6e7fe42600ffe9137d5e304847e1
+R = 20702aa5b5cb45cbe8025b4ddda0a42a1ab746117d45382d018b2055b62791ad91abf54
+S = 12c31f9bdc096236d3ec46c4e6cdbcea47e4fba0e28d4df0fbc19e8740ce6dc0577b242
+
+Msg = 436b288512ea57bc24f84fdd117da9dc1858bae8c11637f99295d88fa9d05e3c053a2584a6fe200ad190b3077d9a1608f660349dda405066c1562f6897ef69b6b674d6bc11fa470d0b96a7cf8f6e098c9ac03b0ef415aa045867ac7c11d16cee78ecf08850ccabf70f761682b561d0d0e4a889d840dc74932648ca2fb58259f7
+d = 3307fd717015b12a2dc76ada21442ac1d97519f66898b214c2ea317ab0f0905e819e4e9
+Qx = 4ff9b8d60ed177df635a3953c0f5f5c0254224bc48d34329136706d6e8fa1b16ba0916a
+Qy = 2e50ef73f43ea9a5ad07c6bd68a82b7239534e195ee929aae7788c073dbe9e968c2828b
+k = 14d8339f610b348f4639ac20dfe2b525517218f0c71b1908d407603b25f19971a1b5b4d
+R = 2acf3dc4e3569e5038fe97920de626ddb36bf213afa0f939785dec8319eb8321234c574
+S = 01db40fa416527266a3949211fd9fec158412c447c392ed6a7c7f159a1129da864d33be
+
+Msg = 672faa156dc188bf16bf8933d65e091c633f294486049ce96a4a403dca28a149f4f840e8bef47412285363e9e89006614b013a41baad9885f1d9980cc897ffbd5f8a7d0e63feaeb42c07776efb307ed680ba1cebf470dd9bd8a2a9efc2b1daa569524394f9a50398add1a5bd2f7c263f9e63c2d49461acf98444fd23341ce78d
+d = 14f9f412e3c7d770626e800d43cfcbba3ae6aec8563af748e8a97b67d244334b6e6d2b3
+Qx = 2293b37c84e7514564635e517bbdb9bda0b4a41217ca64c38e94a4bd00753255b4cc389
+Qy = 088c10bd909964ecfe10c373214544c6f60ab85b8f5545afb0fd2ac03d036db7ea9e67a
+k = 19b21a4d73012dd2a2ec3ee280a9b855b89e6ad53438431cdb5d2cec0e5ba21300e9bd6
+R = 3baaac69d182bf1a12a024dbc9a52ba244a654716e2756c36ddf8ca634129cf9d2b23b2
+S = 13ed92730d0a6d75f2a4a56b39f82d063e1be988dc58f0ba5f553fa88b6510116005727
+
+Msg = 4321334cc8ee44f1cb392a4b280a95561809dd3639ddf43b6e11cb73067597988d95b8643d86c76c3c6b932d9262b9b8b55a04fba0666dd8b8ff1e8fdf799ae3945b6e30d3af3966f1a6d634d5e012710d66cb447fc3375130968a2e1e647780aada2609d87247c90338dd71c3bcc3902311caba27d5d4ea4d73ccea960d4bfa
+d = 3091a6a8bdac1e43542dce752694972e734dca31c061c7d1000754296d0748055db3f09
+Qx = 5c0761d01020a30c478617313c67008a1332a0e6f295c5a9f01b3411eef585a9dafc693
+Qy = 0eadfc6f7bb9986b0dd221b77b54287042ae8d1ae5788706b79a354fe785c66145bfe81
+k = 0afb2e2e29b26a686368b127e38c2f5726fd55a13e9f87cf00e831d3fe19d9511d07e81
+R = 2685f634a8c16ee79acf62b7a1fb3acaec0db47c6ff5f2c97a804e9550494b128b2287b
+S = 12b545bd76b8d2cdfc5452291d5e4748a5e981c400daeb65c20812a65bbe936bc613219
+
+Msg = 2087e22094570d39fa937f15a3ef0601709a66666344186a33b487d041793fbb9709a95af250b1df0762ea98e911aeb3ff1fa19f0aca53fd4179e454e0e91636e55cc5b17cad9e1575c82ad265dc34c4a66b7a31ecb9ef9dc756f2ac1d9dab35369a6bad4a0f47e629daab91addc6d297d1e5d81477b3966d8c3b607ed194d88
+d = 1195921b91353db9bcd00510efffe009c94f6bd8d790f5fb3e5a0101c9ca5d21c6ef2eb
+Qx = 5dd8aa95e24c054d508bc5081546677b9a8e8dad40d3f8a184af7cf07cdb09ffa2e0498
+Qy = 5032f208dc3bbad6aaab63211e13e17656c750c6c2a6e3caaf55a7c30ae5ba241d8641b
+k = 3223c6439db7255e89c28aeb046e906ba79f4e9b8222ba5ec201b964d3666301f74967b
+R = 0fb7e194dae6420ac447e7d4f882da3c4859f53a948833a0a08f918acbe03c2e915d1eb
+S = 2336f1206b46b3166b28918bdc1c817b22ab16b355030cfd635ab3dade20d2dbde08b6a
+
+Msg = 15c7bca449a73b03bbfa783f5a91ca0b7916889a5d99d541e2e8593c3b176a5b634ba20b34407fbd94ae1c1398f5313cab7402f3bcd7ad277a8c66d09a6df5dd086b20a0a3823fbbb80980cd86bd13e527eee15656cc977103e80113539e26695addd9eef6a1f56986168d9a53f8b5de833f8962c3826cca106ae9e8c00208d2
+d = 29dc20446e9abacb43823e12a83737b46e6e577466b5a3925e0f9d496824dadb4d4b50c
+Qx = 4b3c1d41d8172ba15fc92d9586f29716821ea82274ac8e4fb3452ccca3e34925f1e736c
+Qy = 23e22cec962d759bc659841f259de954911aa289e9994bd76a30149a73711bc41b29904
+k = 0931ef56f08c379d1ddce0649f45ec21eccf3dcfa178616f45b200a06f82172b91bffe1
+R = 178348d533217543af694c8d3cee8177e22740b657bc6ce6df9e57f0c1f14fc9407c440
+S = 3eb25dc4ed42495b54679653ab1cd4d61c854207994a7318026afdfd44c89cda9247388
+
+Msg = d12fbb82ee7a57eaf76b63fd6bc6c0a65c85f135f019d43ff7bc295cad15d53729d904fed63d69d3ffe8b82c0ebaf0399e2717ece40e011f710b5db46aa457c23b85545953398b814816a1e7a8ab5b0b14c4a0451b0bda9d0d2ec4a374bcaae208b7fe8056bfa17d6b7ffd4ba2e9179f49b9cd781b0c06f6ce3eec26cd428cb6
+d = 3b9b77d19a42e9a555da8ab70aa5638890b2ed21daefa28ca6323fc658662dabcbfaf52
+Qx = 632fdf8ebbb755c960ebf8fa5d6b679416e488faeeb021c0782352279a7ae00eed33094
+Qy = 41aa517eff6854ba04e2de6794848823e53ca580353f2b25e45fd4efd3a369cf80fbe57
+k = 2450beeca6f1ebac3e82e3aa3239a5031f54ffe65fa6a45e2bf2ccbda448a2cf6988141
+R = 28664212774e23b6513f73a9b2da97f5eeafd10efe742e314f6913a6d0c0e3e581cc6cb
+S = 025bc733edffbc1330689e7aee0dc121b64a72dff19e1d7c5990206d6daae5bae75d0b9
+
+[B-283,SHA-384]
+
+Msg = eab0a37915c6b43b0d1e3ef92e6317b3afc8b8301b22f6059da8271fc5fe0e419ca6097daba213915855631af64e10d8382d70599d903d1535e25cbf74da3a12ba2f13c33a8562e0db03edce791f1d39af8850fd1feff0eb25f9ad0a86dfab627b96e65831bffc5f6d9693d20493bc9dd6eb3e9325dea50b055768e8aa30d49c
+d = 0b9f8f3e89e9c1ef835390612bfe26d714e878c1c864f0a50190e5d2281081c5083923b
+Qx = 542ea231974c079be966cf320073b0c045a2181698ae0d36a90f206ce37fa10fb905186
+Qy = 7e6eccfe1303e218b26a9f008b8b7d0c755b3c6e0892a5f572cdc16897dcf18433f9a10
+k = 31789e96e2ae53de7a7dbc3e46e9252015306d88af6bd62508554f89bb390a78fdbaf6b
+R = 0fba3bd1953a9c4cf7ce37b0cd32c0f4da0396c9f347ee2dba18d636f5c3ab058907e3e
+S = 15d1c9f7302731f8fcdc363ed2285be492cc03dd642335139ba71fbf962991bc7e45369
+
+Msg = fdb93afd5dd1e3eaf72c7ea9a6cddb07fc2054499ffe152cb2870163eee71ace5bd420b898cb4fa80ea53fbbaece2a1eef6427b632320e9c97e38acb16b62fdbf6585b54fabf0a703307ca50f86387bed1815a05b0c8991e0743d10cdf49c8facfd7ddeb8d4a7b706b5a29e1d00ac88b0ee88b3153185495ac8388cc70104154
+d = 3a30a1c15b9ed71e102341f97c223a9b5ea3e6a335861c3cf407ef691a18cc639dbe74c
+Qx = 40937b263c87461eb5d409008255d4e14c54d7a86d6e3eaf2ad9c559f7a6b9d2582542b
+Qy = 7562e3a04f22ad37a1df0250215c163b45a6bd04a4b96c30fe2e2b7ded5486b172ef09d
+k = 13e745c76b33e6e91f47f8423653b0056014841f4df890121655ac2044f3a6d58b9e213
+R = 22467497bf1b5d29476f24aaf5f88d905be7900406c64033913fc88601c62063a924456
+S = 19cb024c7d6be51d15337a207e66fb0e473956932faf6d755393dd5a899bf63610ff887
+
+Msg = c78e35d1a5b1bbb0ec21e7ba7b7c74c859d88f3e100e40ae34128cf093885dae4e87cd09f3239dd8e79e25305220880dd352a650225d9bd193b9b84e488c458b0b5fde1af941c0c9fdf952d2fa41f665918dccae27ab7923da4710f8c27ac8ed424992568dd6f0a6c3ecead21650ed162e0292104eef3c2d8551be866a88d279
+d = 083330123cc64c11888c1fd388629d0b329a50ef31a476b909a182c930ff02d0c389b93
+Qx = 2e3a3e712676bede22893a8911ad6a683306e86487d24585bd6fe4f2657281f0bae2dc8
+Qy = 773889a95e9bd579be379fbf84dc8d26d47335253356e5b01c09eb8ed57474d6c0b0491
+k = 0d630f20623e93c274239200393cc552d03da6bb9e74f4a44a518e2642e84e761dff7a9
+R = 27b8997fb98ad04488f5dc8ae5dc88b2a3231fca76d7320550c74cc540110c0cee5d8fc
+S = 1824f1050e85d527847faff236b7195965e7b93343ebac889b23425dc27226d50a5266c
+
+Msg = e05435f695997229cce314e50065f3c5f71981988dddccaae6efb81f936b22cb48813f506d1edf5ebd69b0be34f278592c5935f0f6db0cca1ef9d62834fbf3c4c03f4da0596cb4d67b7b767e85dde7b7c6fbef7d89babe6f97b876b33594a9e36ab87079861ee556fb03274ad4af527342a4794192b8933f28c6220f954c77de
+d = 1dc2b656c207eabc9e0d6272099babca8d149c9c4258b779c2f06de75f76d77505271c0
+Qx = 2b03407b65809825a32ab50f1b556a65c3bbbd65cfcec898514637ce606182517fa1a4d
+Qy = 21c97e293ec74dee17c89b962356b7bd50c7b23fcc30ec7fdd0a629d11373e28380a8c8
+k = 2d0dc9317a2af5a7d0a23c00d126b7fae4c06bda0a5c50462ba26bddf575adb091d0e50
+R = 211c396875b5dc71ba87ff2483b0ffbff60cc3656132fda7422a81964f1bfbcb5ecca23
+S = 0a0ed7bf1ca853b9b19924c706eff373b97585b692b4b535ad71cc4362073caf8f61a3f
+
+Msg = 0f9f36477076c4b5a7d1ceb314a397fb14646695b0803e36e98908c8a978770269f165a1fed8f4b655d4efd6ad283d7f5d51b6e1e302d360e8ebf4e887c7523a757ffd55384e114bbfc6b7a0ec8511079507b919065ca018573418f9e394854c5704227772161707b4d0246ebceb91192f0eb2ea994ce61fd98a6d14cc8246c5
+d = 0081772348ff2d7a3fd57fe703555ab2e14f5d203c4cf0292f944e827e884d95f3b1d83
+Qx = 3f7174e88ffa8bc0a770fffa4bc30a436fce331dbe7154f6e2fc0cdd09e76840f089b3f
+Qy = 561e6aa3feffb2033ea716ae94b9a7402bccfed1fc4a137cb96fcdfe4685314f73a8bb5
+k = 3a8c40754ef7ddd0e289b2cdac5e06c72dc3d6ae9d0351d9295aedfd6f0e88809674bae
+R = 1443b46c0e6bce31642dcf3037e25b6ba2b42daa9a83f5c0bbfb2487ce717c37b91f46b
+S = 3f59d5a925fe19c795b4992c265a3c61b2452237eb34efb9aba30208ce07d1ad47e2279
+
+Msg = 1d38b1c342b6611dbaf412a66c1c0b8397692755f576df33b31c2bd12b7f0707cc423376391f7b00aa4e7b7fe54532e2b39c3c5284b9c8ccce48eaf9308ed338992f1d4ecde6cbe352e46339d7d602942158387881d9b493fd40cc59d4f9b53ee4191d42352c6f7bf32c331f0c5afbd44a92901a4b713c7cf6ccddf7de4cc6e4
+d = 1eb6bf2ca1b5ffe6f6a795733eaeed12de6e87c53571e702635b9dbd0d96b47df4a005b
+Qx = 0e64dbc1a08acf6ff0e820593cad79a46e3bd818ddef5ca0960fde799abacc7b840eddb
+Qy = 6115d3de2bdd011ad053550471368581a5f125eb0d32090646fe4407980a42988e551aa
+k = 3b28fc6d0e4a7fc449b811b78900fb9f89885f4d4f70cb5a2b3d4f8ab87bd5448f4bfd2
+R = 2601923909c8c953087b0c0acda57d8c01f814dc9722171d8409d0acd2fa4d9c1314693
+S = 3eb316cacba93bd473a4b4acae4f2b5a5b2ac9856519032e63a0c718698956e8f35673b
+
+Msg = 3353ad05ef90e9762bcfedd6ef44a1e8ea0392ebef30cffd48ae620f3e567e1cd44882d514e7c6759200d4bcab18afd3038c3d3f8c50f7bba32a04eee5a4b1cfb8c349939e4efe0a46fd047d02ed000d8fa1b98b0af5586f120d9ad174b3aea33905b979ece1eb3660b1e070c8821b32df41904ad68bbd8ed247aabd94066f16
+d = 3b2a3e65e5a306bf8e3955b60e856dfa9bf68c1275a678ca056207a0ec67c96eb3f8309
+Qx = 2c542cef892b06372af7d9c321ed5309995c1cbbf1a466e70bd30f3856ab7c5d18f4e3d
+Qy = 2a8acdc12a7cc0b54f4dec9cf61c484a5cf86c4cf6cb5ed615479123ef1c6ecbb6c7ae4
+k = 09bb5e49188621466440a0841b007525000c2203d9821f4c6afab63ac2b97cb5e2e3dcf
+R = 00a09da1c4bedff47945898f4f4ee9a0857bb56be535544aff9d729ae44e23d678fc71f
+S = 2390be08ba0861b32ca35ba27a0c8dd1a4e96d28cb007133a096b52afa0126bf2a2abee
+
+Msg = e7ec162185fe9a5803c6b03d98041422315ccdac67e48fbd07a1ef3c5661158710abc6791bd0a75d56791b4ac0e7695d53c5989d9fa6a3b037583b2a80d2b154b024f1c36b63548be9afe1d51f2f68b2ba94d4ca1e69a35ac10e15ba72242aac20f7526b12ff9d3cde9a9bfd70d55adf9bd92c66d092d7d08e9764c84bf7f329
+d = 1fd4d1af0bb7c79ed5fea7bb45574e46534387bd916649485ef15207352d7302e81dc01
+Qx = 77057d3f93011440a78718a3cfded73e4196e7fde96e794465c51be8b679f912c10edcf
+Qy = 59873441c590c43e0f00f80afad5b0166f94b62214ea45da29174874e44356b29eda6b9
+k = 3f224b35737e78ec5bc9b081a601d8fe19e33b4787449d3353d2ad225358211cf9f7f0c
+R = 1a7bfe92c30ed1af478282786bdf7b5b89cd0fdba5e534bdf13899dab5af108803d73f6
+S = 2ba14810de4f5cf48b56e94bd6c439d230dfced3cb698c77627f59faff0ac5a42c43067
+
+Msg = 87c8f2e3f4fdebce0ca9300fc1ebcaa934f51a12b6b8f2cb6bb6eb77965468663044afeb2a1334cb5a81e74b8427267f8b34b5e9ff0cf157a9f18be2b1942e32ca61dc23ea13c3f9fcfa16df8fe05e067938b6994982676463fb12842d4ec532cb904cf222aa805dd0d86ab9a33a83e294c6d81e8dfa273835e62e9041dc8ff6
+d = 20380b1136b5283e9b7f54b7535ebda33b129ceb177bf5d3d07b1daed5edd9fb3862530
+Qx = 5e7d0931db006c6abe04671d1aede760f2b1ac5c866570f8e5a24ed356fdab49cc5cdea
+Qy = 7004920fdb0a744cc545068bf82bc5d7a46edf9265fd7c5979b9559f5421c9a98f6db89
+k = 3cfbb1204caf6011fceb8d4be987d9a41b81bcdd95b94919b220647d0e7a18feef4cd01
+R = 07096beda28c20d2e62d9b0750142d3d21b54c38c7fad1ed65e4f9b386f3dcfcc43a3c2
+S = 3d0af02aa39e329e4c39f2a1d6797f0e3d14554dedbcab9abbd158273a3c7116225abab
+
+Msg = 2ac53e8a50c4afe3b38904255b7cbf150c5f79dc15932dc0ac9aa631521f68a0d4b6bc5a04d55c99a36531fd4886a23a8d99f262ecd2a9feea925d7a96ebe9b6979a207b7f9378afbe404fc8e959b0333572a2c911f8743c0ba64eebc7ef12fe5435d2cb0e5091ae518b6e4233489efe3c16c6f21abf4e2c6808b733914e5a7d
+d = 19f815b98836948e0a0dc9c30828c31b13e175f1e79f23d084ae1bbe64823f4866214b5
+Qx = 5109d8ce934972f5520101730d0a14b99213ea17772e3e7637d622a5de13fd2ffe3bffa
+Qy = 502927e0c7baedc4bb3ed2bd1b15fd2d06dd43424393b246dd530d5d8598b56dfcb3cb7
+k = 10359d5cd8a9b7532c9902bbf1cb83d0d34bf37e73e7c0f5729b62a10bd4d8faa0f53a3
+R = 3503410a6feec71fde2feb14375d50f99ff9a2c8bef47e676bcc6c3045efa9948891ab4
+S = 159b1f65fd566ecfdc08b87e4ecf99ceea3088a750e2c3c9d868bb432de6a61f289d06f
+
+Msg = 0b201469cac4c078f587edecdcdb6efd5752cb4a3f43ab540463c4d908c27527aa3592f2f9acad85dd94a3c056bd28618317ebdf2e7dd6c5ad26fa3c31dd8e5c50c60418d91c93bcbb59ec1adb1db791f485ded78a5cdcddd23dd1cfa4f13443468d8a5f2d648059b9c4470d0f4fe7733d56a28a2c24456b6923703ef32cf0b8
+d = 01854e954654e726cf4bebc0e5a840e8809fd716059211c6ffeaed36829808363164684
+Qx = 7a6e7c542860e815d3fa24fbaf99989e8b9c812b08399056ae4f9a850a6711a7385b622
+Qy = 0dde6bff33891a64744dce6456600f5a6a11049906608e77f8afc38b922972c805af258
+k = 2c9cfd376903122625c7fdca50e93d4c216f0c7d07f33b3b51e54e666e13b67dc89d290
+R = 18321f9ee35d47648060213df1275ae89c2ec7d17abe8093d8a431ced23aa61d3f8df4f
+S = 09e5a05a62b006a7787c97be38df6fb9fbc1433aa2241b5a788fa727229a18e07d7a8aa
+
+Msg = fc5e4dddf4c4a328b685035ee79069770fbebcc56c14e31afb4bbcdd5220e025f31eba794fd6c05e64f19678dab33ce4f084bc32790392f14bf35669d75b6466b4214ec30d58ca90ae285c9058f5804a1fc9d7a995958f2a0e84ee52e8a78b601bec04ab607ffc2091749cc548c6754ed14e2e5f92315bdacaa7a12823ef76bf
+d = 3548f8020819588b3202f4c1ac62eaec6a47c2a19b2900c5a3cf5b4ba5804231141c647
+Qx = 38563f2482a399bf1c13f42f8b85ef64a3599c22da9688b97530718bfefdabca3ae8637
+Qy = 5c4aabf6d8a90af345008d5a244d0671cbe1afd08000c4eb37702a9bcba6dbc058ba6da
+k = 32649876d776117003305f0ec9cdab5cd84bbdc747d3dad5d8d54a8fdc84d519d50df45
+R = 1f5160851981772c502088eef209f7f89a7c8ab35e630d16330bec7723e398fb37c84b1
+S = 073a7333a7037e1257d4d70be87c30bef770f9d728dd7e2615d47b399ec650aedc867c4
+
+Msg = 284cad790e6207e451a6a469cee3befc3ec43e047cf91b9dff1485718aa29de36a43f7c51eacd8589f0c3a96ec18e8ccfa92941b50b2132e3612d5b45e16f60d411d1c53e373e1ba451352e28970ada9dcb9802102518a385dc571dcf6900971b00346098a58042e0d1d129bd6801fa640a895a458a45b31318fe63ebb30c6e3
+d = 3cc4505005c41142308f1489226b7b542e2e7f24f1d3089ff6b92a4b0013f490ad52e60
+Qx = 280b77ddc6648d9cc3f5557d406ea2a089c8179d4320781b2eb76ab07fcafd2535b91de
+Qy = 05f23bf4171aabbf0fd50049aa017c0dae70b065964c685bc03b958cee2fc3249149d31
+k = 2ef488215648524f6caf85233736eddcd9d1d838c6a2799c3a68580492d40f9800bd119
+R = 3e8e13db22c97281307edd4037f0a75d2c70a070614e94e02c860f36a53aa738fa0db2f
+S = 356f2651b51a6be0c697300a8c2641bfaa1795397eac208385c3729248e36baefc173ae
+
+Msg = 6d46e57abea9d115deda48b69fe8e0b36144df2f6a659509ce1b514c8cc4769d46e5f71df2a084f1db4a22fdd3ef0c2f90394f2898ce291b9f279c0664aa01419f5f6bee1fc1299871b27ecd57a5ac548f99d01871b8c238a6b46044c953b2e78e22346a0c7663af4db62799038ffb5c21ee512e26d01e70a4ed967377ab8405
+d = 144a2fc8e0aa63506e14e4307df36416f963dd9da78655832f5b991af8c3eb97df78efc
+Qx = 3fe8867b560bfb21dda517b8f4d50578a11e1d0ab7ed4ab3796580d31bdf710e8e22284
+Qy = 5a302baa3795e2d132c55d90858d14d4b17aea0ab70632b135f94bb23112d163357f8ca
+k = 0b5225132f19419715170f5a3f26919b4127a05b4f0406f895af1e4bba95786daf95259
+R = 0651d17b00ed9a06bfc6a913883b5cdf51bd5f2dd22307cc5ad3bb545f623516232bb6e
+S = 01128d4784fc0fc050af0b97f859616d764b22f40734ba65aa15e2cf80e7bba3d15f42f
+
+Msg = dd750b39bd8753f4e473c4484e2b36ce2da7576813ebe05861c339ffae1d029bc793173ed394091c00685ad82f0550cb21ed1c68f0c27cb7396922239cfb886647af204e88a9101b7453a8ab662e270b87a8a13f2fe61d695597382cabeb781933bebfd7d0dcd33f77266e43e32d937f2dc89f67525e522977ce73e9ad36c8e1
+d = 24ffeaf139043ff25a395e4c560c7680c1c2155191378917eb25194136b4a69597dc277
+Qx = 0402bf61c0e36385e5fa8371a553ed8652466fdc3ed9d4a3ce1bcc567d1f451f6703dd1
+Qy = 4dbea6f67e1117116f30fe42e84383768b0da770f8a2b4cd8a4fec330a0034554a13808
+k = 3e4e78f012eaf1778c086a3bbd9e996da0ddde651236ebdb6348062f56b36f63a901561
+R = 1e2312720f6fbf44d7a6449a7f30019c38e69f2e6424d4bd1054f40798e9fe58d080b86
+S = 379d1b610a976730dfdf3300280f1c61109ad13c788e8f8f9a8d5e0130ca9482ee417da
+
+[B-283,SHA-512]
+
+Msg = 4736e59fe5812f63737eed57a570182c065538abd9fb0a1c9c2059199e7052ba57d84b5fa1cda2ad9f216610361ce1dfb9334816b6bea509283756a03aaae2e5b0597f492d078b6b015a40c9785dcc5d2ae266176980db04f5cffef40e16661a50ef871c5f531d73fd5d114fa19bae9dd2da4267a131fc31849da38c2b78d1af
+d = 1d1f2e0f044a416e1087d645f60c53cb67be2efe7944b29ac832142f13d39b08ac52931
+Qx = 10b2d7b00182ee9666a6a2bf039c4358683f234ae41a9e5485fd6594e3daa880c0dfe0f
+Qy = 0a419b2f40e573dc2dae4b22e6f56e842e50d631b6126153178585bd05a8b9e6e87e4c8
+k = 3e4d36b479773e7a01e57c88306404a46b6e62bf494b0966b4ed57e8a16169b9a1bbfe3
+R = 30513169c8874141cdf05a51f20273ac6b55fe12fa345609a2fede6acbeb110f98471af
+S = 33fd50b214f402deed1e20bd22eba71b156305e4f5a41ab9374b481ee344ab3f27f4bcd
+
+Msg = e573fa7d4bf5a5601e320130de91f4ad87eb7ca6b8998488afcef69c215b0cccd221b8b66eb0af9d699af9ad6c4b4a580e82941f31e4c0a9bd83995dd076c5ac9bebb34481061e7cb1b26f6e8c6b26ee4bdf9887f7ae2eb9fad3115a21dcc96acce85d23a040c0ebbe0a56e75714dbfa803d6e279b2f4280bcb993f96ba321e1
+d = 1337362609df74d25f7adee382225e6a04dd6ee4c6b45fa31499ce9edb0ec046325caf9
+Qx = 287b288ce6f65fed9f95c99fa4b8c1aaf6de65ca563df30ac67c1066d2ba2f5a554e09c
+Qy = 25567fe183dd400d256c333da92dda2e364afe84492ede9fa0e913ca7f12069b5a44b48
+k = 31b84ec438302155f2e84dd118c0d8479267f8d19c8c5d96d21177e20b23e0180dd6d33
+R = 08133e49644044bf9ba3b4c8bdc3973647d650c58fae4a7ea5a5fffabafed56e759010a
+S = 1d8cc410cd04b188418b20cebc8f66ab0dc29a42f9067aa2926dbadee39abce79deb396
+
+Msg = 7862864d0d78b44e2a28af44a0a16d8e9b1b8c4b794db0410c0a863ba011018ef43e1e11f2fcda2f56fdb2a69cc817df425c9cb3b458922ba00d710190cae16d61af3c304a42fbb3d0c4a74a297253fccd70aca414865b41f68b01c561be281265fa89f63f975d3101334886e85929a5a47fa8dc459b663548faf8ed7484958d
+d = 1be00aa0afdfe92e24a2536594d4b41701ad4dfb223aab35ff49310bdba7566057fe8ac
+Qx = 13583d8cd163fdef7c11e91f36c1d3eb2f7957d219244db883708a7c5777611b0066812
+Qy = 7a1f4df45073b838277d8da7daa7147b0f10aa98b5ec02fbbf97c89ee17f3a7ab4f3f27
+k = 26b42f369ff9b2740147914a2698cf1ec9bab44caa3b5f05957ceb9a32073729aef0fc3
+R = 37640dcfa11483b3754ea027f5f239500894dda4f4c8308f0623db256eba2113c41ae61
+S = 2096767a1f8210b175334fad61b4c7fb4e2d6c7811b5d22521af7750f101077e2fd4e44
+
+Msg = e73c96d1a84cf7cc96065b3c6a45db9531cd86a397e434072a38d5eeb9a90f62bf5d20bae22b926cfe967647d2bbb5dd1f59d6d58183f2cf8d06f4ac002ead026409ca6a1f868b406c84ff8887d737f65f9664f94801b2cd1f11aec336c0dbd4ec236d1cc4fc257489dc9709dfa64eae3653ac66ab32344936c03eeb06d5852d
+d = 12ad0aa248db4fbc649f503e93f86104cb705d88c58e01d3ae0099590a69aa006aa7efb
+Qx = 08d262f57f9528d55cc03c10bd63ded536bee9ecc617221d9892ae1a75b7cdee175cb33
+Qy = 754e40e8823e89fe23dd2748fb74e9e93c3b33f188f80377a32bc66f6a92da1804c04cd
+k = 2405a351a3bf9a6dd548e8477452c4d9d719e32762754cd807a90abddd3ad380e197137
+R = 28c5d807ea1c3ddb7f2c90f3af644c5d6a2757336ae46c2c148752a2fc150e8183cfd83
+S = 397c8c52fd67b99792229194a787518db5be8e8c291b1a30e105b00f108ce41f8ec8fa9
+
+Msg = a73fb0aaec838d011110d49c5e94395ce07408917bacf7689d2cfe0948c582214b263c6b80e0a55f1e159086817605723740569eeaa1bae96b979679165c5c35ef2142525e943e595e6b4b160acd7ebe41de19775346363f779b1f80b6d5f0785b92a648028e456af8496102d19dc6526247a654bdae3368f075fa9ee92b2f4a
+d = 2cfbb8f340cae8e2e2322829148981cd9e509b0c65497fd8d9da5dee9dcfd39b0f7556c
+Qx = 260bb17da74429f049f3a7eb73fea9cbeb5b14ce553d7772a365376d0114ed2ef3087d0
+Qy = 5889e41bca54c09be20dd406a6e1f11f9d31d720e0c4e2e88f381ba89a97f12fa9faff0
+k = 3fd7cb455cd97f7f9cb888444f39569114589612b108657ac59178ffe31a33569c9f0bb
+R = 048a10915fd3bf9ffab1cb13632359466ccc539128cd98c6273d5d8d26c64d57520394a
+S = 2d0f67f9baffbb34094c5fce36f47cb73a537ff984c89e38d073678c21148056bdd6893
+
+Msg = eda775984c7c9f7db47af30dab314d070fb77e9b623baa6b73e2cbda800f167b20fdc2e7219391efacf908f4ceed9b9b6bd3541b52ea087177e18c97391214758cf6455311fad336ab56cfdce57a18add8cf85b0a0bd6fa7297dbaa34bfc8585b0f06a0aae055186658c227e19cddb65de88d260f09f805c2e8854dcc524189d
+d = 070e82a1f3fa6158d15b7346dd56150faee5c98c9d07c996e01a06dc9b211b12ff62d60
+Qx = 3d3ca5fe316a0820e84a8bb5d231bb14c810a87c7392d7f960e7cecacc56c337f88b0ea
+Qy = 27ac0ded5633a98ec5734db9de1399c83a181d522037266d856c83e5c8047c4eff2c4e3
+k = 311b23487750c3c4b23b28424c33328c39d6f594d2a9b459a883508b985d8aca039a2b5
+R = 1465736c3c9e30e895b1544690e05108ca221cf2352ee4af1b5ee4130029a82b277b076
+S = 2819b94dca3a58cc5a96790871640fe0fae38883de6fb4712126c1c1cbfcb0c005c5af0
+
+Msg = a4a13e0bfa761b9bf37fade6570d41c161e20558874911ff3bee38e5649849b159beccf321c6bc7243f99c01a2fadbab9e157e9952ca65d8ea676c74fdc976d00501c626b8465c6cf0e4fd1a7d1260aea987161b821528b0b423e62ecc5193a0a49442b0c3e4ec9c4786a3a86b199c07dd3a17033d430d2c83c100f54e0a7c31
+d = 0b471bbc5f7a07996e370da4a09e71e2119ab3a562a273f079401951fbe4df39a4493da
+Qx = 333e9d5e077bc64d022e49d5d207385a19282aff1b73b307523b0f861b4ce4219308c82
+Qy = 5414e431f3b90a2d4a454d073cdd81f8b224180ac4139104166ec33ab33d079dd147ebf
+k = 3e431c39ef6f4b7674a1bf414460b58998ed7aa5b1af7ddab746cbcd2ed9f42ae3827d8
+R = 151df78c0f453d396d71528032933566e176eb7f6910fa9df2e9b2f5ebb6038777ef209
+S = 08a1c4a1e21cc63fc15a78f0a11a1bc7a59a5a31f57091a12896fa670dfdc05c04053b7
+
+Msg = 7ceda7a7248640f7055309ae712c19d741375d6a7e0608e07f0135bb830dc3e8863ee9e7a75331a5e1bd38c42cdd484d4f45a26c2c1d4e05ce0d0ca941f4e94ecc6b371102f31633629e9861de558bcb6407d66eb91f1062ac0e0409db68b9f2855296a7f42fc92359a7dae16c73fd2dddea52bd866a4d501aedd8fe3b3ea733
+d = 3c65cf80bfb507dff52f9bf2f93df0642020d41619b3990009409e7210fd7130ac44ffe
+Qx = 3beb5b9b8785c5601093086b709c0a05955be42eca3d217e625349e5a875efa82d75ed4
+Qy = 07cd4e64475d628e6f562f0ac9c3f91075626063a52c2b621796e557799ab2f1ebf8dbb
+k = 16212ce91eed7153fef806d2561912be1d988410641d5eb72d586cd4e6782deae4538a0
+R = 26ea04dded2cbeca81e75503932982c7fb5cc7d38a45a3fff8c4ed7f844dc759d8da302
+S = 061d3756e3da1c7816f0d72a8c84dd1f3b93624b631f5051c801af4e472fcf82d896c18
+
+Msg = 609815edfd58c0e26a4b06dded831d2f33466a130754b96d8d7c3b4d99fd4b0789ec719bc25338d0ae8c5880560c02687d352d77c291e406eae865c3b26d00f2e63dc644ce7e01d6e96ceeac8bc1eeb257d36cbb25d89b5fff6e30b6051506a0ae54cfaf6214f30985d54cab78f708029c1fc0175bc58e888db89dea8d300abc
+d = 0f4d33a9c7e6744ab3c441828bf0f1866ae1c042cc54abc754e3801263a96cbb3955dfc
+Qx = 4b925b97bbe67adbb6e918acbcae0ced8dcf11d012e1a97875b750bbb7d01945bd64df3
+Qy = 4591cc9caabc0db8fe9047e6b1f8d850ac4389fe67bb84f6846b631dc3524c8dbe6a06d
+k = 0483aefcad5e382351125b333dcede8ef50914b1d1f1843b075f242acba18c290c742cb
+R = 1fb791c288e2cd52d3837c56b02fc99f53a6ee27ad6dd9c0a31ca08d8fa64eefccc5c87
+S = 0a041ca35422d8985c1c706dcb0b8ece64b65285bd0a934cdb41fc08223885147281869
+
+Msg = 82d8ebba707b72655497320200ce719520c1ae7f46f38122958fd99322c25c9f4d4344bcb77a6658df0eece5df163412ecdca58475d56b0c2d14a0361e4cef458df146925d473a43692b15e9bbec550f1bde3444f2a5b2ecb55d2abd273ae999f16a32333529d94455e485ca4585e6b07bedbfc2bd1eb766abf0d28bdb1ae6ec
+d = 3a4824bdcea6a144d85f1b194431724cc49849b6cb949b4766d641ae95477d1ec3d1464
+Qx = 2c9eb36eca01dc2fe921933f4cebe8046b3679abed80d2f8fbcf8f254bf17be3d551a56
+Qy = 34c836aa4e946425fc9f49f3f62e33d8a0afd320292a34d0ef8bde8ad79a10e3f95f2f1
+k = 23d8725af57d835018e8737fb4e8b2eed3ec5a83fda137c710fc1df875416ff82fba90a
+R = 0d9f57ba8b6a9a1cbba67adfbb938211ed2d267468f79ad39ea1eca7271d135bb67c18c
+S = 0f09a600d97c69ab521bd1ed6bcf0c0f69255c334e0aea06c68bba81d53e810cc553c9d
+
+Msg = 9c6fce18a6a96349b10c9f2f5f1505c8ab727a650b44bc0782a5f39fcb48b45fc7c1b82180d5f229b8abfc807071f931d333d265fc940c93fae7520d8d40ef59d7c6e3678c6a2ecde52b6a8827b1ffc6ed269cb9832feb20e593a7e3d4708309342875199eb2ffceba7ecd707b122516c815e83e27872eda812e3ea52ee3c4a8
+d = 27ba543ea785df1d53d4ae4c1bd0a3a994cddf0c25d2b4e8ff17ea7aa00619e858da1a5
+Qx = 7d375a9e78ccee85fd795e3fe6bc07f50af3456edda1ab00303f6de6b5b02fe09859c63
+Qy = 08d0d54ab9a239b5ff955452b32bfd2372fe095751bea4b56d52f79b4fda0fa635f57f9
+k = 00ee7010af4a517502cc5d5433d98916f6750e8a9009ea04b8132268673d4a02a3e2031
+R = 3c147b66efa47a842eb90371eeae907f0c813ca0937e488da95ff8ee16d389f3ab902ff
+S = 01469d005eacd9ac84a140c93ed0aee09083a4822730a28df35058cad29267eacf03968
+
+Msg = 5eac15a64c7653d125605869012b8f036804817aedacbb5a5248a595ee0c12329f91e8179c187192d3ed0d4ca2e202d8d4d9c93ad3f3ed931121c193af5b47a8a5dc39775b6c2d702708e5134f77a31bd62eaf87e39e6fd3f2b9f782c3057e162dd53b3addf92bf0ab99835c7f6649abd1c5322a1ebb2ba313df9464a74c14d3
+d = 0708d0907d14dcd5f40e2903e1e90e48a0ffaa6d4d9b84ca14df4e985c294f74eb9f2d2
+Qx = 6fb0fe1c3d5bfee5399c98518bc3ff135e0c351243fa0540717a9b1f7990eb8cf43597f
+Qy = 5212fd4d6a50c08cd99ee5988103fa639b1123c878d416cc553639bdcee1f8e927bdc8f
+k = 151465f40204d76f3bfc2e4052549869c19da82c678c332f536ef24567ea034358866c8
+R = 0803d3e8c876d46a9198f2f769faa76c4f66bc5ff4298b9640ccb8e67ff8d10f86342c4
+S = 00da3344354114d163d14d4c288785adbf9a8b31371c6e4420383c80ba0a430019c6acf
+
+Msg = df735a7e60bc267b18f313ad56bff830be5ef119baf43ce27c6368ff1dd89f010afd4f48740b11c12101c5903bfa71d6cb3d6462cf875bbd55a570ffedf3564088dfe8c8d3148231b78b5adaa6c53696737d4704daa59eab8d986fc6e519e81540f201e77b923a6a4af65d7173635b3b19b2023022186a7b8e869e1ed51717ab
+d = 21fb0a6b94080da8b8299b87457dc09d21bc430ba5f3359d92aacc1151be9941739567e
+Qx = 179831c55ead3d11844fea2e18d25cd4d658822e626550aef1afe37d88aadbcc9bfd666
+Qy = 75f8087d759ede340157667c1bb12be272b8318aedf2e8f8b487f4bcd12a50ca66f9281
+k = 37833e9aab843a6b967264fdb705b419ed63fbb09c12170491019acc7c21b9ee28a00ba
+R = 1c9601440d109a3f4eb69a1a669bdaab9f4222a34a04ace8ae313b10bbb66811bea7d5b
+S = 3d2f9ad7595dcff69b65f035ce600f2667f8499d3bd25f789d3f3c1bf83d2855f68eafc
+
+Msg = bb107b0eeaf175a786a61db923bc6d51dad5e922e85e57536118e032167b197b1a1f62d9bbcde04922fde781665c1094181c16ac914cf6fbbfb27bb8346b2134f05c55a8c6b9b481273758e380666d6e22c28577c29446cecc5c3df9ed9f1be060ca55ab2b7fda36a147aeb46df0275bb923e0876b703452fab42f6b7ad2ceb0
+d = 2c80151f91301fb6b0c7685bd172f20515b46bf94dbc4160d0720fbaedd40ec00084447
+Qx = 4a62b0c9749ae9ff00dc1d50d2b4a4941741abfdf13c8e416549ea27fc26b14f191f243
+Qy = 2c9cdab7c6512c322bd200167eb9657f8e8c84864b57480a80a3c6efbaa289ab8cbe4d8
+k = 3df951f8c4490fc7c2d50a72a93e0e82c5a20be8d91afd890d6846bfd146169ab58b382
+R = 1f2accc7f7c4b5f877e12cc17b227e1ba110577c9f4e1785e6dacd8491bc6017129d798
+S = 27a167e6f2b43ce9663b810ed4f8ef15029fb6f2be2ddf25c014d844953f501d1dcf6d6
+
+Msg = f47e49ae30b09b7666600b7a95e81b0afa1553da5e01fd917e4ce1b58dfaddb8dc8c03c0f5591f533610deb6a7bb5faf5dd1ec4103a587a1a4c58a110a706b0f301a5c408b3d984c210d5b4a0b347d2b5447271f25b527b3c7864f7cdfa735dfded47c63b723fa0f0413c57a24ffde9a95c35f743f892ab1ed1df704cde82d9c
+d = 1538abd7ce8a6028d01604b1b87db3aaf720e04220edf4d1d28c2d731aa25f509e58f2f
+Qx = 3076b5c3a12b8a2e1368c7e3458458dd7ba6c5a6dda8c82cc6b30d1ef767d36e015207f
+Qy = 369c7a80cf01e9f32c08f9924db08a7d0dfa5e9a8e0e29b57f5eea8506841e6e3da04f0
+k = 3f0052ba6ae6bd7a7aeb077a764d21caced6b241f63616ae4e4f0d98d2bfc0e44dca592
+R = 01281bc0bd36ba1f3e1c262d98ddf4e9bf1d80dbf97db02089fdf1d2e625abb5733ec3d
+S = 076db2215d9f33054efb397c449f05db198d38a24749f046ee20032f5899dc142052e37
+
+
+
+[B-409,SHA-224]
+
+Msg = f2380acb0d869d1cf2e25a6bd46ebe49d1c9270624c5507be4299fe773749596d07d10f7c2be1c0b27e86f27b4a6f8dff68cfe5c0b4c58dad1b4ebec7bd00ab195fdd635d9fa8a15acf81816868d737b8922379648ed70022b98c388ede5355e4d50e6bc9ec57737d8843fabda78054e92777c4b90466a5af35dd79e5d7a81ce
+d = 0beb0df3b0e05a4b5cf67abef2b1827f5f3ada4a0e6c3f23d698f15a3176cb40e85bf741c9fbc78c9e207fa7302657527fd92fb
+Qx = 1da1761981a65cb5c77ec50ebf7acc11eaf44bdd2f70242340ec26ffada7a4b5f661e13d6e7ad341cd7dd1ca491cb7a0b580be3
+Qy = 19ba11e4c4f2f5507d6bd2aa2f96b03510a03d5f8c38bcc8acd08080d9effd1f8ae5a5586603b2e112964514c831bf786b2fcb2
+k = 091e575fc79444fd2d9021bc267a1a076438d73464726bd0fe4ac2884a374e71bd462b1516b3e97c3202854bd0a286214b9e92c
+R = 057ab9d5cf4d18f05eaf17d3b5a4af96c3eda8ee48acf5e02eefdfe2f542cde32a37c04f285794ddccbb14383a645db040bda81
+S = 05275de4157b32723366a0d63831e6512241e3e4416f3af02e22da8faeabbddd761160304927a71cfff4d6e8937347c9b78cd3b
+
+Msg = 22a97fc0a9694dabc6f274ab52eb592dbbe8beeb646ebe6cef60eff341a13017eef980aba6d24ab3afd976e2f6a84cf652654d4a54a36b2f2f62fab8858f8b0479a48fe9f47f8fd5a4a1f3141a91cbca186507b2bbfef5e4c4d2df525f04ef7c4720fb443ccad540f03a2be468d88c9545d1dad579fd7cbcd103bbebc9e9f961
+d = 0504865a30984a9b273d1bc289d734d10e0aa56e93ab14720f1a42a27d8cc932cb8804b963175de6fe57d8eafa8ab7ea0592dfa
+Qx = 02de5872c40a79d5238722fcb94d5158009e28fb41ea012e92028dc3c87855fba71f50e6d0dff709867de185f9a9671e7a91e2f
+Qy = 0fbf607f69609ae96982bda3f0317fe46ad1e0207030fdca702cd97fb5d5732f3abab24b10669875a64bd2a74c8603897c78d22
+k = 032d0f950d10d028db6e9115e9944e7c768e2da731df49dc9128bf145a747662de08cbe0517fca6fa185abdfcc4e3ab604e196f
+R = 0e7d16daa689ddeb08074285f5293bd9f1c051ca5589e69e4b62c32af110b6f3981d9624df15c7cac0ddd62aee9c41c7b6d690b
+S = 02f6bdcc551aef0e4e8da2df38288dcc29fe600de2f8b6cd8149f88146150790915148f069372151c3bdc4d719526eff252e610
+
+Msg = af36c04af0e3fd64bf52dedf52fb788d2d1bd67fe05d98880cc7ad3c20436abf02f637fcec209fbf888903fdec8682717299f8a4386768153b7faeb6581db57fb9aaf4615b4ea8d924198fdd158363a1f40312527d6bd14c13d19985b668c6b88a7548104b1ff057d07082eea421f50062a315bc3866378f2d2d634f03fbc0cf
+d = 0cc08a4ea5ebe32027885a8c212870e7c45b6c610117994d6a42a284c05199414a3a0e8e6645ac5c2ebf21c505a601f69c62b85
+Qx = 09d2beb607f2bab64451327e1dc67f04f7569ffc0c67b410c6db06dc04edddb1362ce8d8b8220be77c447640e7d0c676e5ad1d5
+Qy = 0ab813e800e75b6012faea43be56fe9d5a22cd46fb1f4f1ba65eab19f75f2ce9d8187e4940fddc485c42cd18d40d47415a80b02
+k = 0cfcc307f847eb696f16af32502690711ffbaa2e60e75f80cbcf7704152d5eeb9ddeb701952dd58fefb159926a83245fefa6196
+R = 068d1c646dca56393caf3239d9fb30d1dc56f991a8dfdbc0a7b69d273aec69a53056d9553e105c7917e522ffe446cbea23227c8
+S = 01db30aceed2b126cf45163b9d878a6590e9ac8284a31ccb0faeba2202679f181eaebb664b5537f408b693800f24da590082dfe
+
+Msg = 6bd6f52a6204b60f37929aeff28c87ef61ddeecc231e52a7772275f9329add899c130956f8c50ac2698aad3654fdb49b74a6427a62a11eca0a8ee8b719b8c0df7b9f0bb0af5fef4918a8c83367d29fddd04b6a1ecad904471e5b59c8fe3cdb06b4f8f96419518dda960845d83c49a49f1b1f2fd1d2682a9d60c25fe3ce982cf7
+d = 07156ef0a74ee1119532a2a7e8c02be1559c3c21897af9d5b34553c3d0feca4a8d5929d1945df824478e0c0b92a6fac8c84f639
+Qx = 01df419310cf133408e9bdb32fd85f8f0950263e1886f2e2e108a596e7e76153ec47bf9b33f69c1128dfbf52557f3c382de85f1
+Qy = 16a15517a811c77cc67ec4fe2bcba1290e4981880c071318aee28e30854692ed2d6bfb71e6e74fa97af750889ae8d010189733c
+k = 063f127c38160e85acdd4d5dee1db1c32cd9da6075b2d2f46b010636e374e0262a0453394aaa8bbb5fe7b2dbcbcd62ad601cf51
+R = 0250cf50d52a5950999b9c0ddef219218f76dd9f22a2213def9ba98d258c2f8359d08d0efc208e23ea3614c9e27b2e4576b9c12
+S = 063479550873dea8a3ec0306ffa9252739c34c87bbac56d3d9138764347d5220bea9c27d6a308dc2ec53724d6d3ac4862d1735a
+
+Msg = 0eb8de25f63abc9cba16823270e9b6f3fdedf0fb90f6652a34688970932e3ae98f6d3bf0fefc5f247f72960a6975bff1f1acc2188a1775fe8974b2bb2b4c8d226ceb735113a14009e8ce66d58808fada4e6f697fd016829913352c0f659b6be354a067df00cf74919580750aa6064f21264d89dcb28b3b2d4d699115c36d1310
+d = 0a95c7abffa92e2c637611ccba66ff9d2ab121b40a85c5b71454cb0dca1f098ce1be8d9ea4933d1a91bcd270c5a33687835d6e4
+Qx = 048e6b8614c0c7156dc41884e17e36ef528a493c28c9e6275c3454d83beb939ccc74952732c18424ba21b8ea9c528966c692141
+Qy = 00ef9efe1145029d8d60d14dcf079d43e3cea0e18010f680bddc2729ffbff9a981cef2cb595a69142b25a0a39863a929adb635a
+k = 0f43af45b0dd631bfe38d85979ff1612140b9cf80b4504857df17279d9d8ea12d5bcd2920fcec81326f15832df6774b9c4bf5b9
+R = 099f403ced566fde4d9755258445b6d6c2a4e234f99425aaa78ef118321f8579fb513ccbb71cc2732e31668a6a6bb0fdc7f4018
+S = 0d8568971a4f219d6d3d8bea6aecb4bf7de53886d2e6bbb0f71d054c63768c34d4d1883000019c59168fbb32f4317330084f979
+
+Msg = cad58ca7a3b9967dc0ab62a43037764f8074ef9177d60bd98f623d693333971c24a575ed03cb61f4dc2e3d6285fb1204502a540f3c0bbbf23f5bbbd1544f322ce35d949d8b1d8edeb82e90927ac67ad49c91007056bf5096bd690d15ac00e1874fe33293d8003a4a2b094078cf09af799dde384143350c54a99e1f99cc31f2d1
+d = 02c438b07c6e0685d1f94a4bbafc013f8f21265d893f54e54c3ac2071606ad1ffacace0b8367aad724b1d9508c65ce52282e397
+Qx = 1fca66bdddefcc3c2072ea32f026c975a2c392dd7ed7e93e94a810e1125ec161bed698d8305830eb66fca5eeb71934ab3fd79b1
+Qy = 189c22a2c9f1fd7624f805fdf4faeeb931709d745a3feaa3cf04824f5fa58bbda144d4e96d83ce1e3282bd5fc9c50bcd68f5408
+k = 09230aa7b58505e2dc2f205b70a09cb9f4d8272f465b7380195ede0f7770af2a33f7623c310a0520e7436835cfcaf32467f154e
+R = 013d0e70d8f4b1563efbd3c46feee15b88358562f769046f39df6d00477815e6b8763c023807eda87a86338c7b64214784fa2cb
+S = 0662f43fabd03a0c05ebba700203fa2188e16504f8655bfd0fd090b109e68220122dff7a6cbb8bae08612e0d516e9f95ac15368
+
+Msg = 281ce2643799bbfacc7d5993683a4fa656040517854f3c2dc7c4f8848dc305382e34e894d433caf12d8b493020a6a08d1fa05b08bf6c53127ad5f33bbe75b9db0615e3dd94408d028dcf3cb7598f6e7cb4c787681dabac7cba2cc06fccb7506fece6c7c1c1bf622d525ae9737085ab4ac578905950002024f30159cf0d99f50c
+d = 09e8658f8f9e6cd98c0f4f0fd20d64d725653aeba339504def17f3ad12a63dc6157d80804e5f43f4ff48fc5573fde2c615ed31b
+Qx = 15088531d914113a25f1598ba1d3cc611e27ea92ce8dc807fe8d446db14ef62ae2f06c293bcdd739f916cfedfc481fd941b4feb
+Qy = 0a9135dc1b0384e7169fb4648973559e508319235a3f41ba174d5f58307448671cf22a3649168495c36b0bced09ac6df98f14db
+k = 0d398fbed52228fe16d32a6ef539e4ee3858a1df327bec999ca25cdbc357de5a75903909973bbb0a5d0269862a74623a38da515
+R = 0e38910abb3d84b2b26ed17d2124f4787dc5612942e98521d9f94baac3d14159eeef9e09b9b20c807b479ba84640730a4ced4c8
+S = 0e370e575302ab0d8d08d5270fe89ba524b5bf21e43e70c4d335ec1525ff5696ced37f0de17e109fd833e5d179bcd4df42d7882
+
+Msg = 0c061da1a16f2be130ae3b20b89745e840bee09633fb49671db28ec9a051545f57ee07e2410ae7ebc61c9af79868d3047705bfc64ac0c04ef0b286e579b650c7165443631e49e6a53c84cefa5625b1e1035a6ed89b8e839540040151132a937666524265e099272c1849f806db0fdf2be64960d5b5853965099459968e5beb32
+d = 0c4c13f65eacce85a51881caa6f82d9e48ec2ac574947d2751823a7f072d38bd9da0cdf30b6f19084a6d291052e7bbc2e1349e1
+Qx = 0af93430dd77e6016d1b076a52126a729f77e34bb3db11328d9edd56e29a7a09a7b6a54f72076fcba886ea78ab6ad81de43a821
+Qy = 1419e1bc339c03a8b4413ff009d76f9a19e201876ebbfbb3dc771b7df07bc19eb893ce23e40c679d7909c33af2bcd7d6306c0bc
+k = 0889be0918e7ef34d3ed226f967301a10fc30111b3559e37f5fa5a57dd5c73ff672c5279d096c5b04c68b71d55e549d019281a5
+R = 0a4bddba9b7a402b584ceb82a54baab61e81973b7347e6dc9e3ce0f1e50dc21c9569d8ecf8a7da97c38e92e52636eb13d3b4c02
+S = 063c7291656466f7bd647073a50f410a2cd9e8c938aa1fd3b28ddc1cbdd7b78b757689dd661f5173f79896780ac3fdd4f3171ac
+
+Msg = 74ac2e1303297efc3ed8e624722df505df55b7f33964cc0d270604cc48b58205d8a11952232a8feb0079baa30d7d33660268b56a5a3dd90105f0703abef8f6636a99bc63bd47d9df100351bee32d8205dab0dbd2af36fd173409ff8d1fb7b24570f3c1e968458f58aea5aa2f46731ee91ffd6d3a060af6b3d5020daf1362af3e
+d = 0da591461791ae7847e6d8dd8df46a63d3021644abe9520e158406c96540d8fd82ecfb1c3f6f5cfd7688c7656cc3e3dc94e586e
+Qx = 1f48c95301956c62e2fd931df49953519b88ec3915c8de495dcb4ccba97bee023b1a6cd9a66dca29aeef8f4f1117eb954e47cdb
+Qy = 10db6bf78cfeb92d29a922c4b05daa3cdff3917ba6978fe738296956ed141c749a938ca9f8f13f711aec930e0f1948ce7daf9f6
+k = 00576a91862cd63acc067563626977fee6f074d5726cf4f68e80d25029d4b8efe5ea845745c45e4cd42879e52854c3f385a10b1
+R = 0806435400248ec38a6d362e8b2cafc3f3bd46ba5baf538cd97683f76a733ba2b4ca85fa7d13b99f4076e7616e68d66f05ebd8b
+S = 00ecae395fb324b4366f238f0df22d011bde5db6b0cf4189e3ad47101067ba87336ca47d637f09f7a40a1bc64de8c4aef7f497c
+
+Msg = 2afd17344552ccc577b0118caeb7dd56a0766e25f84df17c0505f9798931374b48df89a48c64e199108c36e00c0bf00a97ccde55787bb97c6765601765ab5417f3e75e35a9fe5e0f85a721d9f08440ed617afcdc200b318940a1e496040a6ad9090476b0fb4fcceee77b3fea11de09e7fb14853d1fff8ab12d66c101257e2d4f
+d = 0b5eb943f0dd390b737510e2bb703a67f2dd89dc9f6dca6790bc7a260cb2d0fb8e1a81ad6009ed51010e7686d5b48233c6c1686
+Qx = 01ac00da454bc329f7c13950c848392cb4f31594fb7837f0986f61601fe244eca3db6c4f92accc2fbd1a4b8597b70e72d88b103
+Qy = 09a364065a9f67a0aa7518b75a0b4a9140787a67f852fa31342d6275c14713d484dec3116b9dbbb8af1d4945639997ded09cbc7
+k = 049176093dcde8549f95a8f1d1c87230046fd4b18a73243c3599815d4df8387a843bc8fe1fd67f3c6bbe394547e11866f41acaf
+R = 09d7c4ddee55f61c5c4c2ac6efbba6164900344004976381c7b18c1de541a97cb58e14d14b6e433c4eb6d4bfe6d3e0a4e457469
+S = 0a9acf355bad544b3b120522365bcaa1e1dc6f1d3df1e30d3beb94f639e26147a81d154a684bbafac965bc39974c505fd0f811d
+
+Msg = 174b2b083541f8284645a810801e72631a11bd7bb805f684a7159e055afc44357f2c80df2b7853678d34a04144e0ede2327d03db6df23769ec41194a8d9d86af74d51c5bc11ea878c6a80689af71d3fdaf1c651003385332a512e03dd040c33d9c328ca89ec7ee9026bbacf30a7f3a68e0d894fb9f7100ffbc64bf17679dedd1
+d = 09cc63f32152284fca27ab2837bf1343144336a1fdf15b9727c47e877ac69ac9cf4c97b4bf42f1ab10d73de8597a554ed099efa
+Qx = 044e655ad66ca9af330c33bc6d00ccbe4533a4c6a44a3f23c921b62eeec8cc1918e19956f3ed848fed93a7fd7ddea57096d1f23
+Qy = 03a71b221c85607821cd864af6f533f216b641ceae104b8e16dbfdfe7edcb2cf9ee0dc1679b696149ff42a051c51c861a3c7530
+k = 0db9bfe4c2e659006d31a7b44eb7bcd6dd23810f27c74dd587ab9af23aa5962dd18aef1e95da4ebf4aabfd558cbf72d2951bd44
+R = 0c3b91bf0794eca7faf227c4ee4085eac6d6918803242bff4da9c5dbac2e23fc32a4d4a192d7737be22810812558f820b0a2c13
+S = 03120a558c0edb58ae7ba36e886084801e7604558238c85a199af6c9e7506ea4e748791b04f3a92354a4f1407837d87faab66ad
+
+Msg = 758df71a952cdcffdc417b9fffdfb57582ab5c5473a8bdf0c2101953b023b77824263353dea0e2ede1f800a5757ec6ac0e1e4e3ab5a4cd85567d2d19acc6b7069a6e7368401cba2b6e642373654bec0ddd19fbf032794c15b7ef7e714e13e36875262c01e77766ed53cbcf735936dc9b33eaf2152a396349c82ca0297dbae4a5
+d = 09950355e8667bea8bbe3a2c4988436ab5394551b375e27fdc0c1a1d1b07ae957932f428f1aca0a486e54cd0b5bb0a5c5650641
+Qx = 02f623f81fb9a299b71ea8c58d5bd7d89e7be66ed8cfd7370de515eaceac90364438338a3fcf9981f1b6f0b30bc61c4b7c15791
+Qy = 16130b7c4061422d70b21251fa9c3d4e9636f5a08cea794a0fddf74ff5ab1b750cce0f2768d54fb2fb75e2851c2296b39c0ddd2
+k = 038e8c70cd35591012f45f27980095c4bcbb3bd36bec594927968d3747618c7f5810ea9e0a126e4d3e1e08185b031dbe0b37e5c
+R = 0cf957d59b03aed0e48189d2b9256b5472c8a48b4911f9cec14adce5c6b4aa22d093a116364bcae01c1a739a4023da12a29c058
+S = 04cc2c22b243064758f52264ed84e757ff67c4f6596edcfe956b70f777d865d01e529f0a8a9a6e1895168780ab60950a62d2d2c
+
+Msg = b96d9f66b2000e9408d602096f032b112f0e05ea874229ab9daf6e05bee49b4722e4f2d8bf2eeaab9dad94438c76b7cc64dcbb59cb4e03f9ac70487a1d24d8d6b72d7462fe738a17edf381d52179b3acc0c0177c113eb4d10e8e78041deac1d56abda0ddf892edb8be956d285e7236bc6794168f8a180f622dd5f2b9e690c275
+d = 0a995493d6971c2d7e8fac3da9f8c0b5afd877cfb94924cfecc167f9d87002136ab253e3a4f9ddf5c9c99bb1dc1af0c6a3a3c4c
+Qx = 0ac0e558dbca0fa6f013b7282e02717e91eb73304b4f7ac5e04f12f55824c441faebe5bb5af82189044827007bffb1e26557941
+Qy = 1178bb726242c718b416b21cdc9fd90b31ba6a8350f9b4ce3a188b1b5dffd0e8894ae6a417c4d74c920fda585624eed4c1d3f99
+k = 0d581293ab1e509baa50852bd3f21f6493cc524a2c16206e461e320c7f2c1c201b9d2a1dd4207227592a6457670a67cb72eeb58
+R = 022624cbbae5214d2c29e273c334b9ea78e10c7efff3611574d5fdf6f67a81472b606e0236aa47106097b9147fc1b56d062966e
+S = 08895d107ba789d88a17c30a537402591ed788206487697a72f69285ee5eb4f03cdad6c2604e174ef4b9bb919d8b39bee6231c7
+
+Msg = e7ae60ac55e6ba62a75d5328bbc15269d4638764169de0bf0df043d15f9152bed909b1fb8c7a8d8e88ac4f552c1092b62db00958a3a827f64896f6de4bbd8fa5258d6c36e3904d82d3eacf6eedba50b0242eb6b01212288448c3a9821c4fa493869c01149ff1850e8115cf9de1618cb8744626b1951d1de305745507c8b21045
+d = 070daf435cdc26ad66c3186267ad12d10f28d32d863f950cbfcf042fe9dfce553750ad098f82f7f1650c1126b3e4451bee6e11f
+Qx = 19b41af3b557c274cf117d501ce7ccd04d8bff2dfc737d7efcd7888f2dda24737a6788f16b3b6cd589d3f65bd95194799d65659
+Qy = 11983077a2c371fcadbf47b10494f6ffc7ca8873b3d812c45a87c48e1b49edacc0ac37e5038cf1aba20360b74c0903c23a62331
+k = 043fb8cb87591747d12f4897dfbbc79644b87907bdefdbd7ff0f6f2e7970c7d40bb2fc08c17443d029a92487869f640607af460
+R = 05ea3493a8c04723de9de2cbd523481e3a8593ae8f010ecbd5add6db5a82d9b13ee7d24ecb417419639d0e9f4e68d14f6799829
+S = 0a9bbaded0a2894e384184e166bc06e1b2fabdc70536caeb3d0cd46b955743cfa8ac6edd03760d1b613fb445367734fa4270139
+
+Msg = 666b0dc2ddffaa7ffd57ea3b2768f02d4b77c16fa007c6d1918400d195f068cae2dcaa69817e6e4c70d5b29c5598efe2d957bd12d0fafdcf5ac52dee80a2d46e77fc18cce2a49bfd787ff77b942c753974d22434742bdb494590d17c42af725b1309e54566276af3bcfbf5e174d3cf191b85903faafa1583282c97e66c5da6c4
+d = 0f8121980dfbe9ad0bf92383c7cab95fb72d5caba96e1de7772c6a179e85414802fbb86d725401451329287305570ec7fdd873a
+Qx = 0c62f4e7eaf3f1bbae71734c86b8a40ed1297b9ba1151729f9363824425193e8605c2bcd6094aecc9d7ef2a41aa6b12877291cd
+Qy = 1882a45555b68596dbc8bb093dbf1aab9900cf46653c58f5656f3688fbc72c5236297be2f0586a4031279b9014f2d3655adef41
+k = 0b4b5b19922bf6a34a00454374589f9c89745eb194b0352061a79401e23c0c0e1fecd7597b5a7cc1c463b76cce7ab921867de00
+R = 0f1fcb80a4fb49348fb326e808d8ed8c21c376f0713429a22bfe16d68cab0295b21d44029083769761c4fb853662d440eba4cfa
+S = 0252a94a40008cc2c1a69113d8e14e989e7fe13918a2852de6930973a91784eb35e20d8ae150a88c459167f8ece998cbf6c5eb7
+
+[B-409,SHA-256]
+
+Msg = 3e967cbc2bd936e0b6125dc5cf885735bdcd2d95b2f764de6931c4578ac8e0e87abdf96375481df67dbe1b6c43537e84ec62bfca6672cc5f3ea4125abd4a4119edffe04e42411d338e8b10abb1f1f818c50a9631a3f89feb5be5367bdcb0a8a82c96a427ba6ce99f9631d4411a2b7f5b14d32cb3901dc9d285e4cf5508940942
+d = 047682b2e3bcb5800a531858e8137692a9b1ee98ea74e929ce4c919c26ae3b3f1d4122d07fd9a70d8315fab727ccb67004187a3
+Qx = 17ffffc1d2009e844f8e625a3bf11749a8b4ea0b0fe3532d124112edddf72d518ef577f160962b88ee38b11445fdd356a26bcc5
+Qy = 0ca356fa8e90325aafb1826a694a55a80b2af52e70ad8d507d48946392da8b9fa27b8ff6927fe5130c69809d9a2c4b1d7eff309
+k = 058edc8f3665ff9166af55e69aab9d468f576bcc8f652e950082a48224b4923cb9396ed4ae06f05bcf7797352035484fdc501fe
+R = 09b46600fb3b8204d4cb63ddfaad1482dd8cf8652f63c926895b8b8ebfe27295c052b3bb81dddd8687f4864f258a433010c89d0
+S = 0832f7674eea791b5f17db7cf9e2ab13253d870c6ab46ad01cdda30e78db8b8f51fd377dd55ec7786ccc92b17364a3c17ad5be4
+
+Msg = ca1c90012eba4e7c5f01d8cb3814c58f48c03a16be6ed86934014365eee547070b870d1d26a872cfd28b60d9ee0a66dea223e9eaa90ee28076188d6091f26f665684f4b486af70669555db9058d485c677b2a34d4a98aa8d6f43bf6f44aff2a23c5d765e98f0438ab81be0585a5be29daece5d4116f44ce6062753a3ddc505f3
+d = 040cd1a06233ac27f3ddd108de7c6c0982793ee620d71982697713be9fd5143658929924cc88747a680779bb00da8a44e1e7d3f
+Qx = 164e518a6719b1ad61a38a214ebb06dfb0553bc760799e668b1d0d098ae3f06dffd9b84c16de90db19043d72bed2601fda14b1d
+Qy = 18e022ceb850eb1db59e6cf63c4a7c73bea0b70448a7dea77d5ee8a2e1a36cbc46454bacd5954792de82f3ec21ca6a509b0c7aa
+k = 04a936fccec003bd9e8eb45d27c0eaedbd452e6fe99abaa62cbd0739bcf259cfb6884d1e60b82522c6146f081663f6f863576c9
+R = 0dec1635f2698d4666df2c217fbe3e644d27592c5607a5549c877257cba7bee29a8cac75a044e72d039747d0d18de1c34acf072
+S = 0138493216ffc3b8aa2e0c26f4fafaccd6609e6b15f767da7c907db64b5181bfdb447d73ede786144c70ddce7df7eff46dee4f2
+
+Msg = a54c4351ebdb075d6a42a787647390f864b2bbfd8bb3d0e0ea9d767200fa344d1a9ff091bddb186acd69bcaecd767068efe4d752d185bfe63f6674279d0e7192d2077c400bbc0d5599ee28507c1253f05eae0687b965a015e1f3a292b4650106765266f5c95b77ad2d82a6a6e012f233169eb6b8d83576901cfd4a927c54d7f4
+d = 01ca6f752aae4eb7fc9c73a08d6fbd96bfde5030d759a2507bd45b6e1d1487e53abbe98fad4f41976364e0a1d830910ccf97abc
+Qx = 0f6b7220bd24652572b37a0ff25e75f72d583c71c159857482ca9944b956a117a6b2ff96614898757b8a587e3c2b78d9943003d
+Qy = 118fe425768bbf3a4acade281c41c745c9ac946c2f8b95d65787fb6b64deb71e6b38fd8c721e01c87efc7c2a6d8066fe3b35a0c
+k = 04963aa161b5ffbe5d7e5058f0b1457ca1b9cd61d731a0470beefe5f8998904cf4594f98dcb41283f66e2b07c5c5d6a6c587826
+R = 0abf824d43d993107b552d7ded13f49ea0ae7bb845e56ad7e53cc5f9d64f99f9f250e4305ccd9f6594c92defa7f6860fab1c349
+S = 090a541f1844357f618e5ea34c0398ccbdab0cb363e266980ad304dfd675bc81c0345a4d723fbcc76ab5ed4cb0ba0af1b71bcd9
+
+Msg = 6723dbddc8720feeb75e2a061b7fc49079f999fbc79ec8a8e01ab8d35b438b7049da5a23c49a58101742791f84f45d5f5cf551cd7de6926a0e2c4ffa1e378f038da597368c62df8cd8349bf046de46d02183dc05b3a3575f5f232dd2970057200e2c9cb60eaa6b4d72f8b73d4d40b98d1cc801d1a69cb5ed780a75a4064623b2
+d = 0fb9b1a9597d216028902abf743d25944258b48c9762d4589fe660396130b75f6006cacfde60f6204463cb8c18b032de1dd68d2
+Qx = 19b07f7f4ba100aa9e749bcf93a2c9955c442730c5e1f6f72c1b1d132b780d92f414a533282f7b66677c8cc8a3d5ba8b3cd3cf7
+Qy = 06ec6e9c495ccf600f8c19597e9cfdb639406b04f57a29dcd1a7a843c2c44e8321bb8508953e9c0503f77d36bdef24d5d39f85b
+k = 0757f6acf74eb02b7ff3161b476dfd8349854154186c959179f11b9a15da3dface40ae6ed771096e053976866433382e640283a
+R = 08fe276e7f63ce5f85fce19d1739a8a9986cd3c3fbe26fd59324efd98826f9db3b228321b3ad1d96145ca23cc02616d9e9d7aa6
+S = 016e06de8e3e0abf4a4f52bd2f827ca4c57412adcce3271fb4014069713f3723a038bf560788d8dd48430d3b30faf15ad9c0d69
+
+Msg = ed53cec5e5500d62d38c829002916c657674ede4439c6f405ba672327ec677490e656bdd698f114c2ab5e6a1fc94a1a8d64466cfe9eaabd23a8b5c37f76a3c0decdef73b3e7b751cbf3b0817f4079560b5ea34cead88ba374201236bffc48eaf289bbaa4e828afa7d732473c228ad00588c9b443d65b998f21c3d7a9e9196c08
+d = 032109202d754da290c266f74f47805a06e6b5c3f721a72fc97a3bffeb8887e0c642d49a6bd034847d0a5ba09239c5dfdf0772d
+Qx = 0f4dc8b94dfe0a27d4d41399005b242c3e5b14bc7cec55ff3a1561c894d73f365fa8fa2ccde1fd7bf3760b96ab2db78d2d50b03
+Qy = 13ac66e95c335b71fd1a98f101a392dd4696a806239fbdd0708acc69333febb48d4b649f14f42841d66ce03f1fb557a361c12c1
+k = 0b010ef786c13ece3a10eaff79b93ef3899aa385dcc1914e16abba90de0ca6389d664082fa727fa7c7907dc4c88bd621e6124c1
+R = 0488b8956c5999c317830206fc8b9f6760845c31bc4ba77584925dfe25c05a1e7d298a62e9748c7278eba622713df59accdd78c
+S = 082701053ddfaa376c99cc42ad4587d84a358d9d8a9533888cc382623114aef51170de77ecf64af02e09bee203851abb22f5d11
+
+Msg = 13829401bd41e9fe01329e9f5a002f90f1a6ecbf25fc63e7c1345f265ff02e496230f706c6ab377ea52d8707b54f8fc5c7f089044e2bec1dfc66a07da76ee12fb9ea0697d87706b0ebf677600bd2fe117f6cdefb8bd636a1b6b97549ee78f992c24acdf3a946053f06fd012a9c703efb8bd929a66aa74b05d61bff0395232b00
+d = 080536e820fac59b3203aea928475043b2576446619001647e35693a9e65d15236c3cbc12e1bbe0eb305973535c882b70197a92
+Qx = 16d7448c0afe992f8c59b19d6cec64d8fc5b10026a806760bbdbbf0012063f46d31e521a34771f826669c4d1ddd58d3aa13ebc9
+Qy = 1a3742a6f231546f0704345b9b83c72d5036522449cf60c1b3bdfa4c8d36e499d4ce62e6e7bb05c6132bed1ae44eed17414d2da
+k = 042753a515e607cf9992dd1f249820dafe53993b59b1e57d8f2f9100f609cc15713d27f5dff4007e078d6da1061ddd36c169c21
+R = 07eeb1cc19ac45f52c0b63ff8ecf4f4f35958e86cc3e3a071a35446d490a426b48b6c287027b003488573a4834a06dad48520c3
+S = 01410d85f3f2adf065b60a126170c43e34e0883338118cd33b0b3eafea1d142480b236ce49d35fefd1ce4ad3d25e0cc9268b1d2
+
+Msg = e696acdfcc96a6c088069b7595ea9516a36d8fe04dedeb789fbd965db0cc64b7017a821015f6210b6989e515def5a9605fec0d337e4ac59f3101a505168bf72ab6d98ec62a71d2f94071fc05b95e98d4efc59fedc138e3e49c5d0b44d1f48f7b1e7c1944ee189b242950d2bc804d31c7eeb45283c84638f043ab9533976433a4
+d = 0b05e5f0dad9583ea18fb8fc4d8c75fd2e3cf9e92cdd9b737485c953620d345006c31c288b380258b6500b84f729ce6730e5303
+Qx = 157c083ad9789966905c212dcfd7c049a8ba3863fd4886e4b118b3f06445fb0d4745c2a8a1193dc68915722089d0d382253b675
+Qy = 0867e8efb575800f834c978ee2ecf0f84f72e75dbbac86926b73fab8b47f38eee17a63baa02e3edb9d4f6b2fd2afc88b6de36bb
+k = 0c72eb08acb1d422999ee8d51f9ddef9f897dccfafd886998edd3ddf30a638dbd0ed59d68885ce242fb838f022bccd4f3b5f854
+R = 01f4dddcacb088f6e24d331e8b111e390735a41e1fc29da8f5ffdbf7342f4b9056786f2a67159d1e57570bd69d69235ec562416
+S = 0809840df1ef8fce9b2edf8f970c07bdb5fb755e9d5bacd7996275c4f890173142c39299ce9eeb51d21a32acfc7761d5a2cd7ef
+
+Msg = 4058b9a8cc15ac148909eb97fa32aafbb6077b168dde91a411dbc973df7db056dc57ff78f0abcb70f70f800bd752197d681f44df4a7817c0e7f60f8f65489ecb6167c14b525e91fd2cc5d8b80ba380a83d031d5827c8b1262c687c90ef0e62723d9b565557f9f6fed0db48f3799274c2cd60a14303406c35802cba6261121296
+d = 0be1d277813e79051ca1611c783d66003ef759b9e104f32298017fb97667b94dcee1ce807dc6b4d62416e65d4120523bf6a4edc
+Qx = 1fed0171b5b3c6d9092a6592944680a08a0d4f99f08a3ad1c22b5bbf11c0e4ab3cdae9526b0ca2b1bbd961362faccd5caeb1d37
+Qy = 1ae7d57db848e5c86c31f542f1995c76e916dea9aba882865febca630bc6a10ceb6732bd5f07f51bf2f37ecae7b7fbbca618ae0
+k = 09e3585213c6d6706524e3c8e753a2eb0edced626498eacd842d44a73c602d801a079f94b781ae1ac5d44209e8e3c729ed4e820
+R = 01098d98cf83c705515494cdef8c3f50ea8316d95b3ca5f9a1296f09021de57930184ee4b9f563aebf5fd0d5abc0885cd24c0f2
+S = 0d9706f4474a8fb0c701505516699025fde546a21a3fe519a173a3ac01f683d40b4db2642330bcdfe188693b15a476cd9339ae7
+
+Msg = e793237d46e265ab84ba9929b196405faa3b0e4686e8693567e53f68e6991e57677974677682a2510c4c35b1968a90b32c4941af7813775c061c008a60f9f671cf7419c94253d6106b61e65034497f2d273a5058379bd986e3d917f708f0a2bebdba150f6d78a3af9c722a2430ab0f4bad602e91e18aaf258e3785fee78e4502
+d = 073c807bd7e07379782ab790720de4ae5106f16d34e80ed70da5b1594e660c9b775db94066b93e74f855f57d88b6ecc6228aace
+Qx = 0301526b630ac3fca5085f633deadec27af353233e6f241772c7fdbfa42e47a04b0d3ae38c04eef2109390a71fa9fda652343cf
+Qy = 137eacd97a8449ce83f19a13a248af52e512cfab3e2ce1ceb789874cb08757dd9e47ac21b5c0846498d8d7cd90122c437602d52
+k = 09245ba1873114ee2a3e642c5b15049a3566a2f003cb3d25250028655fba98203feef5f307a9f4c77f232976d83723f2621eaa6
+R = 0c8136d4b998ca0544ca1430abf55601f259aac7756c75d1371de63d1471053c789833c5cc257e323a71f80e21783df4efa169a
+S = 0e2ecc6f0a418bee5de7c2418c4ad85d981b18048f94865821de696488ee19291912ae7da1cf5fe9708e2beb18e6cad4e3f7849
+
+Msg = ffb8bc80e7619a562d8506eba7658bef0c25ace3dc1d01bdc2ef00933d4fa07b80364e5e5826074edd46a707dbc3b0ab19eec7ea8990839d7fc0a80b70661204c52bcbef57c1a7bdc861c10766033a82dafbead283d911a9502d5f9ef0a39d35ef26f3616212d4bafcd413ffd18b424fe09b48ba02ca5d97ec996205cd49d22e
+d = 0a68379b2296a6c944ad5dacb593b302d8ef0b05873ce12bbc371d705f308c739d21f343349524aa72f05341e64f7435daef112
+Qx = 07fa0f698535b011833dac1ac96f3739ecf0c29f7fc1f8bd635f4f98daa70a39310611ef51b2fdc8b37eee3573dc34cd2528d39
+Qy = 0be1a9dc30dabee3403da4f2dac6622e6fb8496e72f3f17c169e7b554efd84ac655e727ae9520feaecc752601d5391270cf0cfc
+k = 0630547017103c3f97de48ab6b942db94b2db9ed7dab0391ea9e71c1b788c547abc90088de5b3e36c9ee4280bb454c7c3710999
+R = 0916aac91ad329d6f330cb051941c781b9e59bfbfe45c4d4f6ce0d1aca982e1c612952bcea06784c57c121b14cc0dcca783d0c2
+S = 06a83d93f9bb81c61ac290906d74e2d3b964c39b4e96370f19cfb4a55a3f7901bca3deef4bb79ca6a798fb9b3a9b0137c5a9324
+
+Msg = 946bde90a5b903dd281a51d7fa93d80f3fed07eaf50c18fe9fac5acf67326bb18effa3144e25c151efc006a50a274ec6c6a5d573051c4e2d117ceb0fa125acad07a10fb6534a8e5f5b3da2a1136779c51377bf76c3a4a93c0c6158f729f2293e414fcb952c9509f228c804f0adc1daa327a8991d48ccf4f3957c5f8ccbe3ad4a
+d = 026046bbb269ddb1ec14ade56175482343a21b7c265026cef3c7d6a1ae0f6a68166b9e6c49a6e733ad2ad64df7137ef230038fb
+Qx = 0d09d8118519f9d00df7514d2ff99483473f680b750604580b61017513870a3cf1c403495cba488309e2c084079d53139a36953
+Qy = 0d25e41038c18e4ba6f4e9d14f210b71f27b8ef2c1d4cdd5f63edf8fe11d548d070177e9ddae382fed2b163ff2b58546f10a99a
+k = 0d6b0e5d83155a035248ccea95feb0b4d1af818e5ac6d5f41f1a255dd8b482a94de0f4e037b10339d1805dbb6b22af6ba834219
+R = 08059524790304a37f2a0d57bb2b93cec79a827b1fdc9ce2d7dfd4d277e0f71844d335314a30bbec5598a399e197a852b5528dd
+S = 0e7870e2a0ed16cf340a04fed4d2048e4e231cb8918345e1852bcd3e30413a2219864851121a34fc98dd99976e2b20cf1d1bf2e
+
+Msg = 07f3fe1369ebfcbcacd66675bd4ab22edbbff72e68709cb57d4f590e49440f01691f490c58b5117bd24aa2fe2101b59c61c417c918ea08ea34bbb9b8aa17491ae5d9329affe894f42d7586017877fae3ce35bb80c97f92a004380374ec91e151995166e14ac00505fd1fa810cf02981bacbcebf5f81b2e633d3a3db6737890f4
+d = 0bbcda66978ea526f7bd867c3303b625f11b94dd9ee6e2c2f8688ff07f2bba83c662949d47ad47fa882cb7d203a7f0ef5dbc52a
+Qx = 04cf5bc624553e833ffbee05ab863e5def062e0d57c28e71d758d6ffd3839504d7ed9d3b1a040bdce8e187ae0b4ca23aa565b01
+Qy = 0fc1a15b4f273737eb92a56928395f6518e05bf946afb65ebca3787f7f8bb3d946dfd26c4831cfd171b4c66c2237409ebf224d9
+k = 0a2cd205d957a20c79699e91684cd22746c476a79245f11e7cdf7e6b74f07cf2fd9eea65eda97e8994aaf51942e15695545abc3
+R = 0aa1da120fc19523e8162e6018e4ee053eb680ebc7e31d00db34f7b177c74c5e6ea344bba3c39ab7ebcd92996a1c156180b7dc9
+S = 071aa4588741208344b323642fe03f1cea73865ba645169df9c84bdbf7488829b83b8da172f1927de1c8cc318ede545c748c782
+
+Msg = 3a1cb13438e3bac9ad4ab1d319e90e2c9f118dcf1eb54d6333c674a665d41451f93cd4a9334cd057a44c010edb668254517a63700a31eb0ca474c84873e486f2f8e158a1a7735362ea0cff8ef17d959ffd851b21a91412709b3c729474d2cb40f6ca0e397030eb2611b402916e4b656f0fd868247d80be3ce33d52054b7661f0
+d = 09be3dd3442e0330750f0a6252bf9cb317f32f942ae516a4038dea2c40ca6484fb33611bef016cc64baf166c122e87c15466fd8
+Qx = 0f05a6fdbe6f80c0f5ef3322d8accda4b9ae28c91b6198b888be713afa5e652e907e5ca9aff5fe77b6546115b4c732bbd4010fd
+Qy = 00923d07aeb8c947688e7d3dcb16ca69440e2a89539a41b8fbb797523d3b766b46d257b87472f5084992422cebdc4e45556f5e4
+k = 094fe051a13ea8dbc89c4cc5511881a48ef5554de265f0badf8741ae5027eef25c617bb6a3f454a992fc68f5a548903809de09f
+R = 0162687730f0ab2f57e348476d1fa4eaf13199ee44f44dad5807bbea4e5ba79e92556f287cacbbf1fdec9a8b78f37e78e52dc1c
+S = 01acc734e2d0c81a56ee8c0465661c365edae56228ca43184ea1d7503da3d38e7607b1590f59f5190e5c7264cd0d7a39be71069
+
+Msg = e58e7b881a563d54772125b2863718690a5276c93d9e1c5feabbdb5d6f7c7293ff0f89805b53663bb417fdd46874b8e6a466e7e3ff6737930a0662af1d5879b071b0dc4d014778dff26a2eca5992e763bf4c4698c382ac947215aa116515876008a56e5bf547857049c38a2d3737ed3393705fd346897c3beb80caab88e5b8cf
+d = 0ed321fa283c662e87eaab99b7715e6cdc9b42e14fa5bbe2c56fdfb381369191a42da7e574839f90a85577485f19446fccaf6cd
+Qx = 1bbb34e6bfb1c1335c48e8b44cddd8a46486fad4313581df216002b382db1d58adcae74af0d38445cac2f6cd9e2b439d106f595
+Qy = 084473a5da9f910b4807ec5ff450be353a187af6ace821b18e096c47752b6336dbedfc4b481e356e689fd9c03ffcdbf3e4ea39f
+k = 06ae69e55ac1f7b0f844f5ee0b583e652e0e5bbfa4eae85c59eea1485148e34f4d33c9ddd7ac071a28ac0a6191d5ed03e88bb86
+R = 0c3509b6c0356e4a30a82fa7411d1fe17ed190b7eebf9310c44fd568494c894a4f4a1a09e58a4d030d47227e54f7220f3f79f4d
+S = 0d44ccff47d9fe82627393c03f882d4b98633961a897381ce8b2cd18f38d69742802d18e6c988a23eb425b294f2c1b84cf42cd1
+
+Msg = 8889ea1da1cbed98963941f6ac24f47253ff6af52de920765214f2024aeb04f7ad46936830a8eb04d95aba64ed7cda6ef242f454b67bc2de38a46b6524bd5c96739c4b580e89829a61a8249ec8dc27a50f43b8554cfb6f4fa4ca6875983d4b60a1c6b49f32ddff6fac0cafb64d55c6f594b195c207a9bd920dcf20e0080920bf
+d = 0396b805073f3c3b552b1024dcf35559ac44f255b688871a3c6657f727a4b09f3806cbb75d26a00ae1728be632387e804775a8c
+Qx = 09957f897a17241eec5b8415ed7ec1bde5df11583255e0a8136d076d72ef377ab3f553d6f56c054332a24098aed6d12878abbd3
+Qy = 1f58eee295765e8a55e388e235e833bc5cdc5d51a1d98e13429bcb7891b25487b7fd8ed804b1856cb6071cc28756bf00924bf1e
+k = 021959970a6ad070d1ac518493e309289f3d9d6e2a8933bca715f53cee4ab9000ba2d0147282495e15e63f258dca87a5db7eaca
+R = 0d1ca34413341c115f780e647519547602e0361ed4d70402f42d735353696eac6e4024ed2eacf9577252d40c27297e9389d1f7e
+S = 08cd5bd43794b32d5bd2ccf7ae4deafffa0e0deb92b1eef9d3ef807d456e459f92e9f10627b7e7574ebe3c2faa858bd3e62e187
+
+[B-409,SHA-384]
+
+Msg = 55053af9370901e38622734a5bc5589f6a20e258627f381fb0c366f3dbe58394e5997e978eb7ebbc530f6e6186f48294149b8594fb551c31c50521a8c4d67e5862921695604afb23977b6a69b21abe75966fdd11bfbdb6b51ab0a474c5fa07c4de7872a3bd81acc417655090558dfcd5af449b3347e61fa9e839bb9457de64c1
+d = 0a8fe323f6736bcabe971c7d964e75dece70cb54561da48a11c40027ebddb23e41c7b48600f569500fe8ea2abebdf480171dde4
+Qx = 020f2dfee967949643b6cb8a3810524044a4b873a4984e9795e4dd7976536a2d748b8cc636ef5c8fc92aba5677c4a0951a33327
+Qy = 0956ec5433d73162c9683558f0dfe8870cfe66575f2c34c765372c7c3bc3b291e95c4e3665e4ec5e72131975f0b1f5f30b0c844
+k = 013f26e13d43ba05e01f92457374fe2ad1ccf94ebf22334447f9360f7f9748bf3665ec3058ff6184fbfdbf7de9e1e2131cd3991
+R = 013c4c290cf89789bd6dc523deffa20c94e92e88a76eebe88457e30cddb066c7a43aadeb0493b264cdae67532db7dadf879d991
+S = 043bb7a8db3d79938beedcd6ce02f375e26ce807a2afd4fc446f372fb09a69fb34734df5dc8f6393f86577a8d29014494379624
+
+Msg = c4264330534a6c2bbd8a3b757e0912558302ce302f835ad8c5474993832fd30036fdef40b10ee37293e871db5b0b149654f9e543e22111f9709ef45732125f713c031ccfbc9a2f3aba160c241d27be4dab87ab2fa9a795752ab2daf20f9d06a98d90d01c07133adfe83cb11d5176525e1bba6a9ba70ea48b224d46ddd8103f65
+d = 0105938ba9f25034da3e032dee121bdb192ac2128b50a2ed4bca042e96cfaf4660c9d35f3e67bafd4c99f9447e6dc408e0c4471
+Qx = 0f1a9243920d7cc26741eb828bb55e34c140b0e52837792ed6274a9aa6b5534cdc5c596a1141a746dee380c0d9c2f77094c36ef
+Qy = 1393ed8c609751550ffd077347712f3b27a869cfb1b532c5b19c381365ae5dc8fbffcb2182777a17690616d71c66524017d861b
+k = 0fc52aa8c590aa28c5353568c9dc69734adfae840f1e0642b57863dc7f4faa37bf3ca789a3d7afb32c57f66a61780e253f50af4
+R = 0c45b1629bbf3273c0e785a28cb8187ef387502ac4438a3372a5c72206a15d7c5ecf9203ecfd7e0ac910b6ceee3be50c6664f81
+S = 0a0c2d31a47ad5f9dc2d42dc36714cdce47666f6e2f05ce0e7136f166647540d1e5fbdc7c9fa0def8962f44f2f8bc9addc10057
+
+Msg = 3236f1ad164e1b25d828f5202e3513c80c72a577aa9af56f041fd96cf5a3363f4b827723b1511a2f16360e32eac90ac55f4ee1146791420ef9e2af333c17d157b00e43992ef6f2be2d2f211361e468413dd93fb69232f0a0d110bc5fff361c0410344aa0636bf809062c73a7ac7c142063912b6ad7e1626fd2a384f35faffaad
+d = 0ce11677ca818537dbaeb880fc967dc8bead203a2538a55e756679c4a9e7975b9b3e6aba4e6c6eab4152d0c0939027e9b0bd92a
+Qx = 023c78eda396efa28c92b120c4ca1e19dc6c467234f9f73701d8966bd0826c20122af5f7c9ad5a5b855b6dc517c22131fb0b5af
+Qy = 1ea47619f91ed4a010dd49ece7ec78c5e98297220b4c239ff4a8c29aaec008011acbf7e4f985c02311ca703bf4ce4ba43412ecd
+k = 0dae763fced0e498e3efa1c6c412a25774c9bd6cd4bce25ab0a7266705cdd54040ec55bd7e6708e71b09ffe9c19af9a1ed9c878
+R = 0a70694fe5da7646184b23b4b434bca1b754257b8e7fa9994dce4a7a92b7ec8c7f8cc69f18d17915c6bbca24f6621f9563f7c35
+S = 009e6ba97ac2be8537afe7f8f8b9cde8841323b5cc63cf2ed46a7913096ff8d96040296a1bf9aad691b60e1f18233964a421fe1
+
+Msg = 6c400ed098d8369dab6fde3553afbbd4d47836d0d12dd16015f15cb8d067a39391c85ca4e78c62b8b72c1592349ff8dc52db8ccb7fd80c085fae456dba6f4a2378e184dd59238c92cf04e40d43a66b342d2a1325a0bab12b1ac857f0564c27b35e6abed02ff5bbbdc3770ddbb2ee0513df48bcba925da6d61583076cd3129603
+d = 05a239ae0f40d76d8d3589f1662b5ca12176a4b2784faa8339b54e96a1e1294433a4d83bf904196f939bd8b33bdb4be340ec703
+Qx = 09d03b7985647027a17c06b30ce9fa1b43d0484195f584fc347f7003802613b524cb5641db3425ab4b3839e12c012853ea83843
+Qy = 0818f5e270baf5a771627b098a6f9ad8a8262e331c299fa0722a0df6ca09bdb9c92d22d72a73567cd5497d06639aa47349df207
+k = 0c22251c73998a3a49b3fc65acf01438941a8885d1c5072a5d41d779af70c044153fed4080151b524af402a4e8ede4448b717d4
+R = 02d3a7ebe5de23e0e601c6e41616bf2a9a7fb6193fef8e3f0a7fb8128a925f7bec3833669d1a304652b7bb1af5186b2f612da1e
+S = 0b7bb17155068a8d9b3412d04d407556ee133e1a704ec5da87ed19dfde60517501af345e2e744d35d844f8ac8ad08b13b17c498
+
+Msg = 039a149eaef2de30b0ae457b376ce6fbf88afd4cfdec02d3c5e00400d3b0484c1cd6ba74db5de65d6f2fe39871349b30fdf1ef29bcbb9e182eb3ec5629d07d98354a5dfa82d7f0db3dd10d1510c0dce086848a198893ca5ad24a663494f0596b4eee86199ea85e7e8f2f76e7a6bd4a052c54287f61b391f1e52f96b606151c34
+d = 0077390c62ac41aca995640fde0c79c76f4ea8a8dbb22323ed812bee837ab8798c5d0ba976c7aa634d4b1c2c155de2709e7352c
+Qx = 1a9357770270c528f2af991c447bed86194d458f693a871ca38f271a9e6a566f5b9ba3ef3d2f9bde959e42934c95867b280e9d1
+Qy = 01f3a0516fed36d3622fae3f44d87c4bc67cee0a995cea242e530451d43781f2ebd163f6f521497fd7a1a6c7b93d33b77083a5c
+k = 02555cc113c8516d741b47ca41f53ed07d509845f140dfe7dffbd01a3f751ea9f22e12c939a2ecb1827c0e56b1b1c5459b66aa2
+R = 0e88333875a507520d0b62b35146e37e7ce4e2f2478a61adfcbc6e1aa9fd0195a4960c633d9d6aa9a79323b7ee00ab802768436
+S = 094595255e8862d14980893c095608113737f42b05b561771f56ac1d54eb521bcefeb3928917c07c1bae74cb9aa80dbd34962d0
+
+Msg = 08617d04fffd6644c40f7dd57919f7dcf3c888f4147535d12ca658302305bb8e220bb17ccdc480254004b9035b357120580882ef86aa5a061b2850100285b7d61588a664dd4f5394f5478e68a80f610c9204d056009c1c9e902161eda33ef61aa902e96b6f094a9f053135692182943d38b9763055a38739a2a2d133c5dbee89
+d = 08bf23b09fbbed1b55769907aafb97f4759cec98649b2c9da5157517d4f85bb70157076b5e4aaa7a940af042302f8be06a84ab6
+Qx = 0883c31c474333f74ab2b86f3eac865c4b2b54975ce19c5cfd23682d041ef3deaa43c9f9e2c194ccd3add6677de31fc9e07dfad
+Qy = 0a5a36b54f4eea6b300491ca22054280b3f09b202b2a6b55df9e3271c763b6d8360a330c16f936d69fa463bc0c4071707c9cf95
+k = 0812c83aa9dc4139f8c3f7c55509f9e10e6cceed30e16afc028b1904b4d260ed0e77acc26e711a7a8e24c75fd780ed893c0bbca
+R = 0fce07c6f791a05de29609b59d55b7062e82fb554341b2b2a8187baecb9c95b01ca5dbf8ac88c60babe10af2edf5985b35e10db
+S = 02bd026a3e45ac439647a483261107829411c1b4a9ab603c080b92f605cf742754b654981460cf7aa72b5186b59d224dd015314
+
+Msg = 34c959f549a307f21b850ae105f41299b8bc94fc292aefc61aefbe0a1bf57576ba8d9b80caac635e4edeb22530163fa9629665fcd43959f68eee32482f1845a78ed7278e6e43d09ed6fedf465001afc0d61f1d2e1d747623e82a762576b879c7024e34f43104593cdd691d53bccaeb8f212dc29bec6bc94cf69d0a8491db124a
+d = 0082ad05d19b8e16f80e53a4cccf6869ab5128c5e622ed146fa8555985ccd2aa3b9957dd374586115d4d75b1c01cf98ecfc3646
+Qx = 04428d05366b0a46e6578fc7528d185a3f85da06c4179e9c9055dc0a7fb4afbc53c94954f268e36d2ba8731882bdd27d9684c81
+Qy = 136ba6048ec672601987e9b7402fea24f88c1a94717ed5a83794add0f31680592d6cafdec147dfbc400e73a6ba1d23d4cb0d707
+k = 0c00c897edea7bbfe1913e3da303d64d0d657a83c1eac9c111722b17c65391f2cf67b78219e748ceb269d6c65f01e92e6952979
+R = 0624c5bcfd8e0ef22ee6b34a8b26bc051912cabac102cbf56c364a743e8150195fc55a3fec90a8fabed5eacc1799b565745bfd1
+S = 0cddd4937da8176ddf0de7f52a4babb1f6fccf861533f796a487f35d060ad9ed4435e5a67166782b53c20bc06fd1b36c265c1b0
+
+Msg = 514f4de08a6f49edbb6797c9dad6d33bfa367cc1a1b58a5becfe646c7f3352d5c5d95f7456e7112c4ddc746b9076b9756ae3916c07bbe6d3823895774a42d25d44b3309d18bfe7e3ccb1f85dacfec1654778c19e2981a853c1f40a7eafd16d331093110698c957fe9f1d86582706a6885543248b944bb70cdf9d2ea89190cb02
+d = 0af7e581aa4f9be5815f0c447e39de00da9194eee5e5f609668b9b69930b5b48a948614c2250260d1917f0ebcb00ebda4bb52f8
+Qx = 044703e0b49437315a64e397085ea2ba3f2e2c383b168f31a922e5916d590344906bd2a911074b7481aae7f3f8f4807b110f2e1
+Qy = 05a13607a3bb89a2a88e27d5eb5cac4eb498d34e6ea861c80271ed0c73e1fa893adce0c1982b8a8af6a0249796e5276d369c3f7
+k = 08e7fcadc844456f14ce9354b218d519d86c0c5211d62904c937d6fbe8cb16264d7d41d98a15e9f73a636ac3739770738d6b46d
+R = 07aebfd1681bd5a2f995ad4a709e8681da742649c0530684fac251494263e98d67247e1e4fc174b409e7e24a7b055500920cc82
+S = 07b83b9b5133aec165316021472307b8b481e6381754a9d0b4f9d683c2ee7cac94ed4d8a72cef61fa1f6349b6c4a54ec38975cf
+
+Msg = 4e5d16cb1dcaa1abab1e371e1de02f31ef4e0944dfe1fdec45ab64326435b2af9aaf1a6ed8fdf1a6ab1182bb53a844c7cfd66da30aec0d41757f5988ada0017c4ca752597a9fd3637668bc1a92bb1556553f28d66805bb47f1ef91908ce098d452872da9800e77e1fbd43ffb0ed6fe6a62185d4be73ae96c9241b82cefb2da22
+d = 06d14107b08354e6a41d7d7d50c004419db8bdc50db43428df5e86084551237223c498bce71a17e25695bc438c5c09e009c60e2
+Qx = 088c1517355cd417a698b648508fd07a457ac13a49d1bad17dbfbc9735ee58343316e3eca570bca130c753e17a69fe5bd7baff3
+Qy = 1397a697d2113d94daefe6be491ed3edce9449c707a57af3a164d172cafece564d686fe0d25725c2919c60889af4d0354b05117
+k = 0f3bb2dd9eece25c56159f501af8b619a8c279d7ecbc08ee2af6b82ead80375e9c07227b73a10918d8c89d1a2b12cb76427a7b4
+R = 0407b224d8d9c0f11a8e09ac8d654dc6e1119e2c2804510a84ec61f9017899f9613e37d8166e0fcaae16c3cc11e9f739968c687
+S = 08c2bd7d02c4c537a308fa40db786ec64fbc2dd4c142b18cf9bcad66199afd4f44cbf221adb3837e84173d174e9c0d534720ad3
+
+Msg = e29e75269754ec1194270f5c9e8267dfdd8c696008b5ebc92bb840981fd065672f07f6a0f1b19841adfc51b478371e1a0db9c3346a9f0a4ccbdecb7040191a00ddfd0a8faa0e69fcf544319c0155d02797eeef99fabbc55078f9d852927c23fd931685424249b87ed0c70a4a3e2d3b9a2f92830e7d8f7650c0bffa8f8986b7d5
+d = 099d96d2dc9c79549f031bd5346cf6a8544c312a3fbfc560dc8e378efdfe025b0e6e61e09c04c8bf4133396f993b0906c33dd30
+Qx = 0883e00d72c60f22ab085a90901ba3e8a510f19c3d62dcb3ee5066e0be094cceb30bfbed7068d0bfdf634a53e2fd002dc9e454d
+Qy = 194baa5d7ae2399965fc4009ea83273676e66a56fd35a5939c26ccaf85633adf78b33dbed6da305979077418c625354c7fb6283
+k = 0c213540a452c4f2ef275dd844402dd5ea590f7df41ad35523edff09b7fbb096f8ae8a4baee95428fee03a9e6f6a14ceb90e289
+R = 071779b477245007ba1ef5f05446c4a08d1c2eab550db9c053e4588c9935f07ba87764f0fce14d4a7b982ebba89cb056aad8cec
+S = 08174bb56cc85ebe7bca1de1f44cf93cf478d7fe59001c5947c66b837bd3a6d116f99dc4f9acb4f378b0321228518e1ba0057e2
+
+Msg = 1a538eb447c18494ad5a5ad27be67fa60eb2c5cb2404eec1dbd7244cd802b17ca5497e779d5f779b981b165dab53ad19fd7bf2ea7dbb9b4baea782a43d758202f147e59d6b6b8ed54f4ea084bc18519943f6894d603e253ba3e8e339a6933bc3a0a47126087038e1c813c3f2997aae321b7c95a802b4b73fc7db95897b7c91e3
+d = 049f347dfd361a65910e97fcefbf60013a54837f2ae657d65e02397f59dc6bca27704fed3affdc3d833fdc621cc5e5f99b92a63
+Qx = 17942b58d42da750a366d7e4cf4cf465c856cd911e5352b50bc8a12704c1ac6ad54f9465e4fc5402b373d8bd4e4f8519341f133
+Qy = 10abcea49c66730ddad7734eb1311b2626b75ebbb299a28c9d60937e6833a9b3dda052379fbcf7875f18680924274fa1764158c
+k = 0134c70f031648bf470ccca4ec19c837051bf700c851df564ef3ceb99d7d41439293bcea0c656c0e5361db92a03def51d7e4f26
+R = 06c0f9935abc5034a8b0a05e8d04de699b5916cb367e834f13642f0003510bfb68714be75c9e35b5e593eba45fe151d1df56d40
+S = 0930baf426b33eb4afbed64869a22712591db11acee7c4d3a221a1e98048f05900fe14816006854cb90631de5797f91176fdcd7
+
+Msg = 7502c755bbd385079a4001b8cd653287dc3054f3b57de19d0ff8f63c0308c64c56f035117a8971d43654f89b52e923947e4760ac72be073136da70c5ad7ca1658cc0a2d2a880d3a0c0fe636fdb27b77ff260c4c1ef8a18da8e9fd777d732a37ae9906e6c4f381f0a3d941048d5a1f6f2cb8593873fa4bb1621a44bc2bebfbcd1
+d = 0dd226de602af4e9f8e25784bd1bbd4cadb0a8aef525d5e2d57b9f3555feb698765672c5099a7d6dd5faaded69d8d68b4804f26
+Qx = 07ee34cc7a24e2e693f9409f52796427ed86fa71bf88c923db305ebd5a83bf3b6f7612847f16d00f4a25614299a2df92bb693c3
+Qy = 1f63f177b54f8dd5c907ff318b66c2bfc1cee09348c035a4413fa3cf5acde0db1c8af4fb8deaaf8a3a6f8f06b0acfd20c6f0049
+k = 0e19c21b05c82dd8c873e5f30c1e3aa9348327f959a4dbd9c741e233c649a426cf7bd9d8e93232e496d0b93ce835f80fbcfdb2d
+R = 042a3907a480329a6169b439a6945cdbe8e4572779c43fa6cd1f15062559dae9eda2712402ccbdf03d88a8a68b691f1f16f8f52
+S = 0d09fa4966d171a662a9ba6827fda830b5404f96f635edd8482ee009ec5c7b64a2a6c17793993610ae8297efa9fe4c35ceb5001
+
+Msg = 95eca932d03f1df2e8bc90a27b9a1846963437cdafc49116ccf52e71e5a434cdb0aad5eccb2b692ca76e94f43a9f11fa2bdf94fe74af5c40e6bfd067a719523eea6b4e65730365ee498ac84c46e1588b9b954f1c218920cbf71b167fc977ee2a89429590f43bf637eecd91b0ce3be2d66bac5847205f76c06b914a970f543e59
+d = 0b6fdbc9c8c76cb2b822a940d8675889ca6f5132429da795462381ce29313a23bc132976fbeb346ed4c691e651028f873ce7971
+Qx = 147647d267afb4bdadf54baa3f5131e79dae8103f5b2ddf70e4652f9fc5495123be97215b811554241c53023a247936053288bd
+Qy = 15205cd5bf0c5154b2dad8367e1b487689b898acbbf44f9ed67a37babbec739804dfe737b324ad663cd2cad79274344397099e7
+k = 07321d12d616dd2ee5f843d6ed7e92d18968b3a76c0e4ccc167790afabad1b7c0dd53d82aacac93d98679b203bad88d5ef0cd75
+R = 0672c5607acc646c67456ee77f2c02117cabd241f728ace5117626bdf91662323e7565438f46a3e25c048a8e2130e27fa1fa2d3
+S = 064aaebf9f2fcbc843ae1128eb6c7e7d1fce2b9901dae0f60afbcb08c7f2ea1b550e159947deb87dd8959921846e2923880db6c
+
+Msg = 8ff68cb00d03e730dddb05fe0b2344689529096c3da6eeecaf097f22c7fa340593106b1f6726f06b7ce7358edbcf801ead959438a42f94cdb467b3cd5b17fbbcf75739805f9eadc869c33c604cc58f81591b0b8bf4d42bd53a801f0f829a31af6c129fb4f20f1250f959754eff8c629b85a716b6a18465b6495798c0c5166c8c
+d = 0203d77fac64591eb9a18de20a9d5eacaa1c3ec58a5ecdb3008c2d642e197141d16b3a9fdffe61429264f5b420f5e9926659a4c
+Qx = 00f66ca09d15d0991b48ce7afde9a148565b73807e435ae0f16c14cd439454745f8ae153786d7c40cce3f43a8aa4f0564cdcbc3
+Qy = 00f4c919b7a97beba2559a8ad0f85dee40e8df28e23732d7de655262209a5170f94791e255e77e8c8cd64c8c9900092e0ff9d5c
+k = 0859bc752300d4ba5014e302aa4cd2a979b3097dcfde5c59f4bafc5bc8a99411174d2ef3f7377df5a09269e3d9461be61801942
+R = 0691ea76acbd5e8137924bee13326ceac8231688af8595718e210bb857d6619c152e1fb46e03fa83bd6b5d81e2463f9260407eb
+S = 054df52eb86c679d8f8514a09f5a3062d2424cdc19fbf6927f744aaa8c444223f1c28ddc84b1d135a886eb7ac7eab3c7b0a42e7
+
+Msg = 01451c4f09720cd53377a5ed04c907a735477378ed960235a833049d6bad6e6e89958b4c4249bf0f6d4f043530c9e5426deb0ec3a12b7feb4860757b41bf602ca95655155356ec35a2db8e2657998f56529be4b714364f83a140846308a2973907ed7b08e935173ebbce5e29afe1444cd51c92824ede960056439555e7e74450
+d = 057a2e6a59d4871c3d547690237dd9846d6d5dc4ec0678aafc9c8669af8a641eed67bfea4b05fd6b3b5357ec4d0caf352691ea4
+Qx = 0351aaee4207bdac826ba17e3b08dd7f94c0c8ba0d9829d7bf0eeee7e6375458b5457bd787f0ff38564734b3a0412bbddd7c371
+Qy = 0e09c4dfbc33d61d69b5a8517baf5e4e1614920cbdd89bb05f0420be757253fb92308dfe1de8db822f57b67b393d8a70d989b26
+k = 0fbe560003dc220e4c966b21c874b828874a33a93bb69c49909376df67e5df1652fd91a1d73c7733f26c121e7a3b2d1246c9a61
+R = 08b85cf3a14fdfc69cd42750baf362286940994479f6ed7ce1d87af12c5ae075b311754f1d37d8ed10bea092bd3d9f7afd2f1e2
+S = 02360bc1f7a98cc87ee2a4feadb98554cce59aa0fbfc087747c7253e54c38815cf91c8517f5692f95bc7c3a713fb6ac43a34f7d
+
+[B-409,SHA-512]
+
+Msg = ccd494ca005ad706db03a3df6d5c6e876ef859ec77a54de11fe20d104377df1900b6b192126c598944d19a2364b2ae87ad7fd32265d59e1f22be5833f20767793677b628f18e9619f8ca32f3af3b41c31e87a98d1527e5e781bff33c1a8be3a82ea503e76afec5768d7f7dd1f17dc98a9e7f92fd8c96fca0db518bd143d82e6d
+d = 00a3da7a6633608fcee9ce4253bbcec08d41ee6b00178ceb017de74e24d48fd89107c9f2db3556063abe3cb011938f4b4871795
+Qx = 0a6123b122d7d0d766897b15ba6b18b3a975d3d8058c9d359c6c6594cc0dc07d9ef6033224b4aed63d319cc2747c0660e38897b
+Qy = 1ab5fad5e78f380aeffca8d15e60731720184ed456800967b2ca47d482957d38409ca07ea798bd892b529774e44080eb8510e6a
+k = 0da042642b3117f30ea5f4b354047b164bd128696b8c00cc6fcc767246daf7483284e411009e05218246830940178cb4ebabf1b
+R = 0e4ce613e6976e9e1c30c0c93214a0a37f0632de85eaa25464b69a251d592560b2039fc59b15ed7045c29c268693d7c9e06d8ce
+S = 0ff3ad5ca70aac94facd842fecdf6a28afbceab80b549507954b7dea6da06d1facd11e0a88e9c2a549e6971a08d1af75aba8363
+
+Msg = 5719e50d939a8d74efb444eb5a77cda48cbb59e7f976cdb2ea2848bfc558718b39ce27b893c229db94bf77992222d1746f8f52f858f85124a28193ae0da039c53d484681785f3367f6516fbb8a86560aea9e3428551facc98cdb1e9df8e2f37db823a7abc589f667b5c93c4c47061400220a2014197d514217fc252cef5a2433
+d = 0384723c8b4a316b450d1fce0b2645912b8acaeb3cad50860cca43bdc0206ed5b3b60ebdc29b3eda305d0d60eeaec261edc24d5
+Qx = 0fb89d87ca4282ccd048606e4d321e7ca73244b4d0c9d3df87d54e038a14939138bff33c81a9ddd64abdfd698bf103e45c96f97
+Qy = 04ff7e1706688a53a5544f4ed0f3f5e1f0fbd6f21174166d25a690f260766646cc6fb39020de9327199225e44f3d95c5984fda9
+k = 03a9f5f26eac81dc8ca0a17acc44322d43bfd18edcbafe24113f5e5fad0ef0a3db75ad1b2422c7321593e41e76eb2a767a14268
+R = 0c311000c27539247059e4a8d789ed4db93fbaea021272a90045bf6fdd70f4f32cd1e195b99ee6f03f4fb57c3a115ffeb459af1
+S = 00db8bb46fe0f99b4e6e1394a5db283e310b24d6006319986dd2c4cc169c775c89d4ad98d0fdbc3c0bef6b7fb6b43ef21049bd8
+
+Msg = c84e5702a339259a61b5ba8ec1957f23ffc4f1eeef3a58f383d3731bbaabfcf49ce2ebb597960ac5115a2af1c62b193d4ab6c24433d5f168a1752e40145f19aeb6dee889a53a4fadd13eef60e28fcc7ed6a9b8b0ca286c1b3d66a4b2c327a629d15c148049e3a0ccdccf05cf22c31956014595e417060627c8125bd7c00f8850
+d = 0bd3136647572fef3de51b12e64b36460bd3a27dc660c164fc705417339cab21f9e1f9be0f3da926df459c5ba58b701d306e67a
+Qx = 0f45e18834d1933a2a26e95467b6db85d8c3da372e607907798745cd9847bb8f8b51f996c7293b51550144f227933ba26722685
+Qy = 05d8b108eb3591b164745d116c80afdd4870187061c75af9b0c3e87dc8262586af14f4d6b1504d274c07c8e89247196d8ce8166
+k = 047a494645b99a3469369b72cc918708ebf453957b49ac4e209f2edd7a4861d014543754e37e1d1a0f477951a0ac2b5826a470a
+R = 09de9e0147e1a268f80836d7db43779ce12e7947caa851d109273ba7e7dc7fc52c601f5bf69cffd5adf0695cd7db8de2a64781f
+S = 0561aa76e1e9f2c1d4aaf6e2da143f67166f09199e1705b631d650528e94d643768cd611467284a9f543e50520e3e738e5d56b9
+
+Msg = c90bf11d04a708e64b6f94d4cca64b92463eae878c377b188c82c1c5f05a038be20eca2e18034d46f00d9a6fc73c4084981748ee9d2915d87aee4e2321f4f9e11c176f01281913e324700d9cb474b7134fcc408fb4a7006acd9e63d4578ed4c2729d8e0d01b1e6174a43a024ad261eb644ae98979c3cdab75af357f6dbdf5db1
+d = 0495be0b0a9d357f6155fac008cec90442200bb842d89292fde38b7256e4117284a60249b3101b3f19f778b680c0d1d7422b84a
+Qx = 11119cd910d4e962f54c9776c9180e7eac2f71cb9748ace4b7dfd2d2b3caef4964c7a55caa9763e008de600b727068eda9b9865
+Qy = 000b48246cfb7c86e9dff4ba77a3a53dbb1cefa168026b8929c42c3b0251fee5746897916e50f07dfe8b57baab7964447a2fea9
+k = 0ad4ab5ecb84118c33a4b06d1a9f5d2c4f1f3dd1cf71af596eea771f851d0371d2d72593c926d7b69b39cdf72931f6bb11d10cb
+R = 0e959201622673d81ca16ed94e9e5be3f38bb8db48f9c09a585aa31ff39f14128d79d604a5f93c80aa961c85bbf99e276937f4d
+S = 083099697856c780936ac01aea5e3a4d9b6e183639cd200464a5cc05232df30ff5220dce4e2af714c580d561b72dc4969166a6a
+
+Msg = e9b2a33906a1079280100039787377c2971c378b92e70a38ab41dc23979d6fb0c41e53a21b37632407adac6f212341cf6af8605b4978c85c9c16960e1674247f1795cd73b99ff28cdca024f5078490513c77114c2f52288f5376872c331151d7b2c08f7794f2c1f9e0d849d32d73636f0aa899988ca561a76f74543b37cbf3a3
+d = 079626354dfc4eeeb51fcf232ee9e6b0130c9bd40f15ed45606bb7faeca8f359e0c3e18bf12769254522fd4077eb24bd5454871
+Qx = 07ad047bb38bde6ae2593e1e41c36b7efbce1e0ad08def9b23d25b7ea9aa336eaf10217df16d32ada4af03dc193d44e6c77e677
+Qy = 0d2b9466ecf321605b9f4f9528124108007203ac32cfdc7cb87e1790ebf4bae497fb87011e0a81068e66a840d29583bb970e24c
+k = 0074548d1a3df580e45babda6096f4c78cd70945ff190d9da463fbb03a511c45d45dd1c46dc0b9521579fb506bf015f8b835680
+R = 09e04e9ffc2cafdefb600cf61e803eb78cb416304210165fa7c93c1bfefb02cd4a255512622d524141de02c2cbd193991dcef67
+S = 01a7960232455f27768acd825b8ef91d4efacc38684d05a900a8512682ce19787033cd08c1f2412b481b88ad02dacc0ddaa0ec2
+
+Msg = 672db3fb8cc8e5f831be700498d3ab3aef14b7548e8011b21351215fb6dfa09460d18f52c02c8815baf396d856a429bb9afd602a10c213af34db80447f4c06ab4bd28873c88eb9639b199042d4b2cb13cc364f734fd4ab7bebede7dd4da63decc0cc1f84e34d760013f66d71641073f16c08078880b67230f2d6c6bfe17d206b
+d = 0ab42bc7d0e3c23f8bcf928e25f9f027b56f270398a1d37bea0ee5426b944a9c9ba6d0d7796899543feedb470f70b2ab148234f
+Qx = 1415fe81100f208ec8afd5e882e5773a0c1d46e44627732900c7e1722cd77b3ae24438a8463bf571fd6bb422d7c583439c07cff
+Qy = 19c3ef3688ed397640e873dcb20cee9755437d0023646d05612e8c360717a2e80e80f2b85860d71f9876f3a68548da7099f601d
+k = 08b44ec25214602de46046b2c94a45f64e9d0903f6148dfedb76a80b8e6314e87bf7dce8e73b14bb274a88fa39136a00537779b
+R = 00ec4c5bc88a959a1234413026700bf5d4287a0263fe75daa16693bf74cb5071a64eb18778da0a31210347aaa33130602f6b597
+S = 0b6c29b9177e89880f3eee3aff204b866020b3bf77d7c31204af383d9770804660711a8579a3f1ffe325f225fc7e7894ecc601f
+
+Msg = d7fd06b89226cfd66671ce5b4b656228c52d986afa7f6f30161680eb0c9cca177992a8a8c40167a64165c518c55f678702125709361b536bd928567c97737bd750d0e2e6e0c00296a6ca565f7c05cc8c54ae7a4e0c334c6a968fc18a959c18ebbd924457701316a4e999fb11084520dac68dc2d69187134c40891af0355ba89b
+d = 07f7aa2216164ba689459ee5d5ca29e70ef75a5b2a4416ab588df1dcb9164330c0b405a9d80c3acc41c19f58e24e17ecbc0fa7b
+Qx = 1decae837c7258ea9d90314ac87c57aa6d49828787054cc068edc1955245271acae72dce5c9cba422bee54f22e11810721c1ed5
+Qy = 024cdc9e1b27e5d4bd024654df000bc9a0181f7c0f4a90572c75e16b679f4362446993f9920e2244527801e8f6b1e9398bd8382
+k = 0463202dff25e6b9c633b60a3edcffc1a22031cff44dc1b0a5769214693ba02038fe5dcfb4a48db7ec49b33068061616daf2fa9
+R = 08c06b72b73dc2655645892447fc0c0f8055838b194e8fad99fc6bd50774e1ed08313eba4141018af33af95a3faa20b69bcc0bb
+S = 0958f104326df6008135bfbaf5c2980cba2833af1b4f04b5918bb51ab0a0df637d6a4af902a5e07db3022c134c72315f25972c2
+
+Msg = 83b7e9d3ec638fef51d2885fff5490c94e2509c126608f82660e5fc523032f3e85d69d9b76af145f6bd916dda35775abbb6d1902bf38880f8b9259822055c5b1bc726c51029972cf7474cf2a812f3251aa71813476bff55598d079f075a40c6c41498bd865ce960c518bef75a873b9d010965f342dc4b35ef5c5972efe6fdd18
+d = 021d84f070c6823a70f1a74225a472118c93ce9dc509aa6064051ca4574939dcfa96be862069424bdf1a23f62f2868326422e64
+Qx = 0f568f018b0dc4400bca3e9e4b0e5bd5245f15dc7acbcf4360b0be2ea5abbb87a3cd76aa653d32858438051cbefbcc4feee6f6b
+Qy = 1fdf1e1bd7a2d3825df14f8bf8d5de825095663c3014f2eeedb9bed3c3416d56f805b623f40b847090d6b4b3bd5abc98ea55e48
+k = 03344dc1cd950a9c3d039b6fb6af8c5745395d2a3343d86dc6670580e331d59f6c0034367a6df52423a625d70292893961ceddc
+R = 0fb010ba41d651fcc854762fa1437262eadfcabb95b9502a40b50f20cb34fa19ec570dad2e0521809ecdb2bff3f4e7055c02bec
+S = 05a9c2dc0c1f946ce33f2f434c156c236b09098365a7f31e238b4685e7cd8c86a0b2455e5c83907167c1324bbb37e66e0b2768d
+
+Msg = c62c7bcc860f0e175128e1127dacf935ce62ae794cc4a0ce7966bceb023ac0498641d7281fbc86f9ef470bbc77f608f83f8d0dd6299cf08f2cdacc7a9642e4246df131820220e5c05d0dbfceda7f16b86add4793e9b6244d96b5c07cfa23574ceb43e8e8b5483192a92b301aa3b37702b8f94f0129d8af1617896b34990c9b02
+d = 0b6645344d17528968c719091b6e2072388881dc10bdb4c7fbf41906cadf3699b30f9c1dbfb4796d009480664e6276c0359e5db
+Qx = 0b164b075b80fc8b8ec785d5c2ef84d49f2f4d276546c9cf2e17ea4d367828e9aaab985c5cd0882204e293dba0359d47d9bdc05
+Qy = 0a0c61f181d5d06ff20d0c41cf6d6cf7fea860075cdcbbab2efa0950e2276dafd4258a39c0fe4c45f3c04f76efa7d41392b4d34
+k = 0c497c621c5cd230fb1e4a4cb3af1cc9d8edf4af5c4af7f15c4ad0a8835b54de52d83bdb3433808a67628912a85c5d00aa222c9
+R = 00b22e5773aca4d97d2da846c3947bf9cf2474101a6f0d39d31629a6aa2a4c3a77076a671e37aeb4cee0a94e82e914c8c553e04
+S = 06ccd79ab93e344e6f112c1e4a39e8505a2aaf5cf85595cadc6ddd1afb0b1583d9334cf1c48f26e5baa38e05b6b52f9f12c141f
+
+Msg = b5bf38fd9e822925254418475a1ce762a94e336f12b156b1625a4574fee11ee472d537ef94b4a4b1c0a73b0140d0b818cd06636653e6c07f0f100118242a7703756f1cb1119b3477c4ced99cf45e07e83b7f2749c1a5f8d8c9272d221fe17f7c6a5fb0f8a16af46f232ce406aaf565c6b2766a2f6528c82e74fa1c0a7fcfd49e
+d = 0f8c2f770cf5f8e1f900e996ecdcd84fcff5cd959777fd005d721a419123221a3237e39834b270d37752470deaa6cea023c5058
+Qx = 1f861984fa06f15b801216a1c33672cff43740f0f736b4f4abed5656a1bee33a2aec431680942f2b0b0dce9a9196b49263fe183
+Qy = 18633f4e057bb6d70a434f919b9ce4b7d9e61fbf46c1d9638100d77881755fe9829a69d696d555b1a26e25ac1a1c27b40f909a2
+k = 0bdd99022dd964306955c57b226aef036527eca481622618fa7395f53e60aa95a275f1f2d6e7354d8b55d3e83c85819e818199d
+R = 02f1330f41a86c09205004215c24f42fe582da189906fb23fbcc52136fcb4970a33b896113eeabcec8151cf3b150eaf1ec2dd88
+S = 0439507edbd36ebe4fa5df34d220c1441e1a4175c9b0373fc85669facebb5bda7a4b415c269a7add207b461525c6cc94b7f7b22
+
+Msg = 6d3474770933ec01b76be789304b6fda423b12a0ae8c87a5ea8d7ee9f71300f39440e1c7f5aa4b47c1a8628cfc3a490b15ef292a741344f40a8fcdd02cf3863bf3e32d53031f503703deab17fc52b3d4032f4e237dcc27231b85d3fd60b49ed7ee40c3344948d87c3f47564d20a11d50e4e520bd16c8701694fc70901a5da625
+d = 0144adae951fe897d5812ee4a16c0be4c86c5e57e615c398f5768a1223a9be20fa82ceccf8a16a31432bbfd17e594a4cd8a6a07
+Qx = 0bce072255f7cbaf565f82db122e9c582ffcfbefadab6d79680b2506792028b200ca7732a98322c290916c66c8a8ef77df6a2e5
+Qy = 1b4b6f65e678223bdbe5f8ecb68573ae3d7f111dac37d4fe3c0eb768c461187fc5859b13452381fe676257aa445bc7f38b4919d
+k = 0128c12479b7f0630374880b214aa26e4e8626deca57148a6c6a0e37a97e89da8acbadbbfe7db28a0c5bd17303e1342af711f25
+R = 0a95124ec95e35747fb568e6659ff31867a4cb7c00985b36584201d1bac0775653e0a8b54cd9a9067ab3de434bc2cdf29ae287b
+S = 0257e5410a6f0bd94fb3b5b10500fb45b501a3734f0c718035a9a1516d2f88e10d1e38b70c791028e262e0c3128cb84e6064ea3
+
+Msg = 92ba7aaf71f625f7a2e024058dc8739da3567c306da4a812ed9e1542b7d1e982c16082166a59720203f4524c3bd463a662c26a82ec7b4376545206e650eed0d3dd7909dfe3810981393070d15c45dc4a75a8c5bdeba533cad1ec34fd20466a61e4cde3b25af9a80a9a54afdd7de1cf2a74ba32d4ea0082a037775413c61a8d1f
+d = 0a51f065fb32c55bf4ff6f18ba9d488d35d9f8da593adb0ab1632533284e0adc43ccdbda9d9507b9862ac63b5ae7b0f78b479bb
+Qx = 080e2f7ef17a11ae66172cf1c18eab12aca4c2ae06b8106aa1066677a93538e3dca0626e836249eb884a382c3b726736565c3c3
+Qy = 1e98d37a17ea736ae58eab093fa7dce3f10791ee9ef5ec00bfb27bf3c705dd633badc94642c385dcc276f9b1fd5e01dd76ce944
+k = 0d5cf7b3d28459db8dd69c314f6464f770c31f239a12656368c84c64693f23733661081d20dca9bec9c9659a8124b57a71ffd55
+R = 072ba8c1b4bfeca62e96a5649e851e9a311d7685603a11c1c299f5ed8605adaf27cae656cd31335a7ae363cbae5dc7a39512c1b
+S = 01bb9819d25a211548461de4ff973ffbf475230baa161558d9cb7ee6f2e682dad21a465fc2ae058121224f8680296d30e3692cc
+
+Msg = b3fb9e48c333201324755a81f3ae5d4f0e2ae7cd24238fcc66d858e3aeb1ee03328660d6399676eb1b7d8285ba571e214d935bb45516fccfab57b8eb4c3d5f1d7357c768eb7b5e7b5710f599614bd4e92706eaba31f8a5e7e57af7ed13066af50b4540ccdc126b677789920cef8543907f0ba9dc92aae343d3425bd784ef483d
+d = 095351c0bc07acfabe6477fe85f97eab520dc96bdd58b44b036328ceadaa56a1904d2217c5fd25155ff2aaf9005a3e2687fec81
+Qx = 1c1311230cfdf5824323448c68ead5e5885ba540a21ff90b951f85d84d78e26da035bfd99341b5901e1ebb18648a8dbb996fc9d
+Qy = 017a037929496e560cd1c936d9eb15f79fbff737201dd880a69dfec31209faf5bd2846e3e664c668ad3d6500c5ed620f1bcc970
+k = 02234bafb54cad0d0d51f4b8508dbc8d014c303d90d21bc3f749ed7acc42f0335c5ab6d60002d3bb57cf07018e9c13b92c0a39f
+R = 04d0609f06320d69870a3e66f19cd46a2e0e3e13fb8b7785163a7b567bf2c0f437b4e30cc67da288a3b34ce3110f6d87affe0f5
+S = 06c46d0248f7c309c1e5b80ac4b1459bf897e42f8f037031f5bbce0fde50af50cfdc4f60d5ad3d1af152298cfe77dcab287874d
+
+Msg = 9ec5f7d65082264b8a50be772c44277a73ed19199eb275fe5976f9799d8629fcb4a59a8d55074cd2eb2a0e02062d3f7cdeb05e62931a24fd1aaf14c257944d1b42eebd52726d6fe281211b39038e52baae077ea4df89675d860d6ba5a0f998d049614201b872e134367acc90066ac602e478ac3e43c3ddf4b0ca0aac1a68591a
+d = 050245c1682344fef23bd549ac8d1e8e44b2840c43eec1cecd33daa4e9ef6b53f496104d7432e14248682cfd6f5b4853b65adac
+Qx = 0d2f8fe524b2108e375c9603598b555d6c4c7724c7d11039178037b3a4dc82b66c3aeffcccd89cc34dc2b2f6695892323bdd805
+Qy = 1f98df95fc1837ec4d5239cf55e97d6b489b0a8d7bf12c1ccf95f689ad23e46dcf20dbb531f5179e754f0c29c8757a1dc67493b
+k = 0c683f98253406c6587d87c57991fe5caa3f43b451875859feeb81176b732f1c1eed0ee44d1905d41922878617e03dac53562a7
+R = 00cdc9bc7d670a1b6794fd7da82d2ad1a0e92b82ae32656ddec3aca4de75f407f20fe782daa0004317fa3f12cefc48518298d5d
+S = 03ee7c75810c2c05946b53e2f24feaa697af35174402c069b9fb03d89d73964c997eca4a5d6f9482cb23c8ce337a374ffc3e186
+
+Msg = 61d657bf472676301503f6784b7286fb39fb4186bb88abf1edacb4a2693d0a1e2b77bbf2758c84f2cbfd1753e20841b1cd4b456400d53f4d686e666943f9b6ffcdb77f510be97536e9698fc84ae347d483bc8984548d1cf86b9b40d360f9c0dc5bd1c55868e26fce1460ba94ef5e94eb63c9f0776a0f446c0cfd4106d9f36352
+d = 08d3b0277f0e9fe54581d3a9499ccd7f015c08339591326859af969d2a26284e3b3beac4a0b74d324ce5cb5f38c7995e4e3a41f
+Qx = 0ae18564ac04b54769e17df84aa54903df58decb870591dad73dbd712693d901f3f9ad43a71f23b77705de2b4ec1c3bc616356f
+Qy = 19810f92e80560979ac6e72bee505dcdef15b4146185d2f8f5a955a4555523d982c34bbfc1326024410dbad3349e4c4e01c242d
+k = 0e52dea77fc59298cb06fb1401d11c662a04500f0470965c4cfaded13b339bde52f4fa04c76a955faac16784f443b1ad9dfa0bc
+R = 00c917d487d2aae1651d76147de2a706a01c8b3d223afde7d20c9dd77cc2329bd3e0e4fc01255b7c4ed1baae7d26667bc2e9ec6
+S = 0058c766fd514a405de91a4b9e99fc0b0146d954dc2e2decc2f3f066d0fe192832ad37a940949ca4e9abae0602248b3b56100ce
+
+
+[B-571,SHA-224]
+
+Msg = 8e14f713a2c427b1f79491033994f76acbead614d12e73ac6f3f518f2052a10c1273aabe628ab38e0d3d5f8ff254802e9f44a51367bf80325b6fc39d907a37f731372864747b10749ea5cb3d3a83da39c21a7b02885a8c1770e4397cedc958e4baa21d5007569dc9dd1e45d2181709d900a394454090badbd0cd9c2cd2369aad
+d = 0f42afce7f7b3d45f3f925ab29fc3882a89c9f585177887584703cf8bd8fc572e677adfa55b402446fe1e90dc855358d92c3267c35be9674b40c2ad5ce8dbe6a533c44b0ad8d2b2
+Qx = 63dbcfc2d9171a7cc1835c1f56ecadcb59aa6d5852fde264ab25603f06817a20f2787446445be8b2ba05c70fa25d9b9e34d5374febffeb536facd3da52d43d69fa7af4d4792c792
+Qy = 7686e0629de47916af19f9013f65fa3b5f9d196916cab2f765aff31adb5a959515e83fe3e00e91843c532041ba15f047e978bf2fc69627bb5cd7f3ecd74cdf1a8d623c1efd23fc0
+k = 3fae665eb7a54f51c522ad5721d9e2648f13f3d84e3d64c8148d59c662872b5cb7d911c27bf45884f2ef717d72bd0569d9901f2308d9a68d128c042effea148cc963a8252f1426e
+R = 1df705ef13ce900ed61babed02e121dacd55a881ae32bd4f834fa8e362d059223b29ff3db835fa2b2db8fdb98c21dda5ef744cf24d0a798f501afa3a720a238ebd4fe3976a179b8
+S = 1b1e98db422fd48f1dfa049f38865f8bf9ec5618fdbfb50f21cc838051a1493e4b1e4f9ea81156481e5fd84124fbab740421173862c63920e3a833aebf0762e7b5b39a1591d27c8
+
+Msg = 38b60d27ff08fb191811036dbfd5b39e1cc3427ff70efb67c851e9cb407f9fac6f348d289df98d055eec73299fcac068bd0fd9ffa3c5d244659e4f714a58d79f6727f323a7ee26369000e90e34e106f99f5ae2ae1b64ee89e5a1d304ef20c071a7773e9b977ed3d49f467d300a881c8371041394910f9c366942449045568f01
+d = 2f36613043cbf53ad36e2b38998bb867503359ae082d07d040e5a10a43e06ba9c91e7c73308e41e2391b65e634f83b162cbdf4e7a44ad818fb93a978af00f06be06731d8c5886c6
+Qx = 0fe1afd356670e1dc6bc195f9513f1dc6b03017416b5252c7b56153da538422e557d9918298ba6c78283efa0288c0ac61298846a6f8adf74df21747cbe7c18a2b825a330e843cd8
+Qy = 18b7659f0a7e8e7ae5d636ea4d1d5f3a1f846d4bf3dfbd96c6ae874354db6faedf02f75c4d1d8bd6a3b61e70ce58e38ea5de8cc16828f87a0667614f6640a3023b7f4aa93fba577
+k = 3fe351ff6ddf50752f7dfd8e5a72c9faad77dbea303fd97dc939eaad3aa7fed466fc8939a7a6bb7abee63455284a5338e59dc067236dd699bdeeae1424d993a9c76fb2fe9595423
+R = 04a0e13a9fde9f2fef417199f8584d0f60b2f04aa6b7524cd2a2826d63043b2188ca977c9567fc1ff292ed480dabc01589db8734c15aadb4ff54a552a7d9e66829fec1dc919dae6
+S = 01bc7d2c4ca9300d7a3001755ef25231d2852a7b9a3e91baf21f2a2bd2ff305be8a9de1d1bcd7bd9eac4ce12ecf8a91c0a409726085382fb8d2428adf1b42b37b50c9e8e0535d7e
+
+Msg = 21709eeaf9e1953822294a478dfacfb205fc25f447a73a76a32601c00784cbf2f9ebd41c22721d70cdb3842dcaff4a4f208d41c0816990e421cc4b8538ac2f347cdd0aa2a39f1aa26ace8cb6a606b23f6244894d4594a0f6a5b8f6a695fd66e1a41e2eb6a377017177fec56bb58c837e311cd04c5b50575faee32606b9636ec1
+d = 2e74948c46930cbcd9dbe2325539c7dfdd910f309fd610e6599d425aad9ae230a8d4681970a14f2a71fd08030d0a40ff40dade7de1b06a80441bbf7e2fcf1809cff39c7ef88bf9f
+Qx = 1b75f2d281592c288fe6d5479a4e21ef626471819850cbbdf814593bae7e6ce2a35a978aea354649d979f161543fd4c12dae0efcdc2d95e82ae5874b9c04a2143535097b8a17c68
+Qy = 0c7160c2efa3aea1d18afc1a00b47209dfc750a5317ddebff04bc4d181f238d339a7690c24e55be2cb0c01719d34ec986a07727f2e412aa72434efef4d64ecf7c16e2e75ebd7ad8
+k = 0d3ae3d8e5e01ad838a7cc9a4d9b3e41eaf9894aed1d1ba597458391d4a2ae38c5d6efdb4d91761a415812d77fd9ceaebbf1ad49c282e693d71d89f0e2d1bbd94698a47f1f30890
+R = 1e2e9e2633885c85f70208de30ae9b7f72950e2de980607f6d0e73fc1fb2a4a8afc6388206c11b081540bb528a94e5386ce77a2d5c7830fca19223d57c1efe7ac488e69ae07e660
+S = 1250d1b920324919ef81865513db461409f6f8ad82f658dbfccfae4425906da306ba10cac84cf5379b6c1d8b252f3c6f86439413c617deadfad38a234bf2b0050fdabf7719bcc9e
+
+Msg = 3a131fabf3dc97334f212fce41c44300440d16de1d6060450875f7276f53c026e2a511681b5a8d75fc0d578546339542833145f7ee13c708df33e584445a75a5538829286480d339be7c777c03c998a6d3f037b25799ab2d541021502a0b02a9b9c337a8b176c4f30e5b186485a6103b1d1563ad4ae73ca806a5e4daa92e9100
+d = 1b5fab1d36f6f6d559f65d8b01edba610620fc3a38307b1fb1c5bd63e7ffbd4a9098cb8bdf50975a873f5d047ee2b627b090897a7fb5f56d3f4a0f3528179e7c969926fc0d3b0e5
+Qx = 5eb8c5a2bfc86aa9a82830d665296f74aeffa9c5b38750d0ff51d01c2dd0fb6f2209f8ba89ff07297ab9b1b06168757f48cb6eee618a7b44f1b3902187c33208288f35a06665920
+Qy = 5334c203f4ee44fdfd5f99686b18696b3433f203dd148324dcfaa03a0a250cf606486ef11ebcc1ed1839a76ad70909d835a4b30a014104a6ecbb284b33f50bfec33d8b5ede85ac5
+k = 243889e7ad32076a3ea436356eb572c1b4ae402d0218d3ee43927eca0b4fc21a19926eea35c37f09de4766f54e6079c34fb3c174afb953be1aac46d675bd300e717dfc2d0c3fae7
+R = 1d87b52dde9f502f02a502e7a331ca6dfc6204922fb94886efbe3013446d08240f6dba1210a76eaf804562aa92a14d220d59b6310d6caea0274a5e1e8aa3c6b57f239191a71fe3d
+S = 2a5342df6908841b719f80ff905cee0ec3fd8be46396922c3f2f142393714b97128e083907a3a2343f0cf9aac73313279ed29eb44017e2a1cdd0fc86e4b7c536e9f7eb1bbd192a7
+
+Msg = 679d85a762f2574b0b31b516270b7d33d5e166c83e91a0f48e0f3db20b52f42f9e6ee9648cf58267ffe3b713723cf3df52b5fab5c14db1e7189f7cb7170bc6ec7cc71946745e152b39180f828688a5b6c0b2957ab94283b90052a3c6e36843c391aa8810f9253b639a8d5a69aec10070603ad7a99dcedb544858d057a1d66b89
+d = 383e70c71b431eedd4574f65d01fb0304f7744d668408c847f7899eae44770a7f3243109740f177d7146a27748886b7b77ecf3792b512e8d8e37c3bf4ecef2b1253df7066498f01
+Qx = 769dd91fad550980225877d98f7c86963c88be141f91f7a3f1607e0cc6dab767aaa6ceabaf46b65a7c80b6a494b0dac1da5d2fc8c5b07ef7085ed1bbdf4273da3665a6517ea1e5a
+Qy = 282fb94b4726472248f01ee43607f7ef969446313e849998fbf0058c8ad5e24457006b84fc0460b74d86ca281caa174e69fbb68673e1d28ccba17eae045eabc1839870831246a14
+k = 336909099a1540e6f69172d55e0c88a1afa99808005bf09cc803ae1e4e4fbeac2f77f984bddb482f1f13e4430e25e36962b1a4cae00f1fcd7f2c7a17372c91673d8286f9829bbdc
+R = 290055d578012a5b7d88fe2f70581a0fff976756b4581875cf5db07e01f09c0bdf6ab70ffb5839567583d53c68e31a27c3fde12bd4f1e1315af2f742746277b1fb1349141ed3043
+S = 1480c63c8b90c7b51e092597fd8391a237b07f0ff7dbf615e6bdddd5aa880db29c9b9add5bde7e0e81d9a37f852c26f21d750cd2f95520d16da7404c2c3feee1489aff09f298d7f
+
+Msg = 236152ad31ce2ffc0dead3c142cf6c770672cd2e75af4a82fda1a72e1c775cec9b481c6f3e411644df7e7ee901c501405620af4b6e9667dfd46091788daa95ef2c6c9f5c240c06b15cb0df51f5f058d8a7934bd7845f007a35f99fa97200b20f3b5b14fbf1e372507f3b2f377e8d07d30fd3e222f398f26d8f428e320327f901
+d = 02261d4ead21f02fab19bbb0da8c272286704c8f0c6842ba47ded121e5cddef79fb34e6b9694f725ca502949faecfb21e3cc062a2b4c654bd542d9a1fe8d97bdd0905c510aa0999
+Qx = 3ef03980ea9b754b655948da63469fe526ff0ba2c0f572981d02f5693bff620b55b8e9e9f9d553a78a0138072369775c7976f028631e65887cbed62fb447c9f41da86022f4b41ef
+Qy = 4446eed90f2716a7aedefa1385db9f5f803434517fcd80571adc9b7f086c9787b76306380a375668b05fbed30922746fecc0cc16f189dddab676516ed1fe4d02855a34a90975389
+k = 0b309f6c53dee8a8956358df45e72126ec76266d38babff185d4db1d449c8fa9baa4b0651af5f5b0aa70dee3dd55623060097e2f94ed12636961a7c0744b38f2f137bca239f974b
+R = 2b42395206ae79bd9df1c729856101ec3c4a719616701f836c9d69b542b59ce973d91951853f89a0717abd4b929bc69e59cc379c941349dfb4f98d49f9dff572c614242fd370e56
+S = 1ecad482a8eadec6800a9d876a382125eafaa7bbd950fe5f0588126764126eb1b384424015c52ed6a335668506f25124aa78d98ec5739fe282af0c143c07da0fca53b9733e159b8
+
+Msg = ba3f02c4847fae035d747db246fe4e82fb9224ff9cf568a6ae548f5dc2befb2079541d2cf9aaa6b18c281a05e7ddfcdbcefb25f41dd91cb3092b3343e16985e91c912215cd99ae4a099baf628e33a7b277e3c36a13aaef85418fca99f64d73b789f23ecbb76c3095ade0a5f7f34836a98c5be933b44a94a2eaa3f99b1d8e7937
+d = 316c78f289e1860bb623082be9d9238b88e38c5e978a868bb90f776235bdff4eff591877b7f350cf14c40356922b2b6aa51d64990360b2b0e44d6941b5dd9492b4f4e1f42ca163a
+Qx = 6f4137a2c63b6b79138027464135021b034f97bcb2493943df6be844f1657a97632ac80541a3b43ccc828789517efdd9f86ba171c1262a07a6b337bdb0c8d5f018302a8046a1a8c
+Qy = 425cf553554d18f6cc97f0caca2a7eebbf266d57030014273f701562d5b1444240b9d22060ac9bebb37deec393cebdad21ec7f13fe5c7f1752b4261cc2feddeb737284a6eec3663
+k = 1e0321344bf364f1ede39a49c8051f36875ad78e4b080ece9088111739041b121f3f334c6e923777fd716a52be669d6e45f381da11262fb4d09ad66dea74ca115838e19fe94b7f9
+R = 04f24ec978c52ffc7675a09334a895e044eb8eaf04d26c094d7607b77ac4168a02a972f577880a0d0c73f218815e3a7a70c91c50734c08d374a15fb42fd13367dbbe08fe9c2d4b5
+S = 060740270df0e1fdfb8e829c9601b9901223b19d07e9d7d422b9bade88a50fd6d4ec96842afc45900a0107ce85ea6d083d66ae202dba3a32e50c7c3af951cac7acdc6f4c406740b
+
+Msg = 6d0372b40559e075af56af853cbe18ba2d471b0fc8917764abcc69102b03d5bbe1fc12458215be66409c26c89f67c72a8933677a07f88993af6918acb074fa915fe883b24bc3d191ff1b08852f07eda98977e70eba072d8bf189cd545230f59559ac05f1fa3f4e65886d0bc274a6e02e2399812b2bf91abae81e21279c5de996
+d = 2c1bc13f8320d97a82f3d9354e195481902214e16a4fd89332a0499208e91d50e5cabeb4927ba030cb42f5bc53b10f500fa646a8c88508cb0d63ebfce5c4bd574c527d686c735ce
+Qx = 2210791ca48aafed20de84ef9896a9c7584081f850b75884908c7b3dccc94e221401a6ffd982f292a9d5f9c1d066ed493da948ac7e93977dabd7b820bfc0fd21cd8d99c072bb69c
+Qy = 33574c6ce7da749ceb480b4e00bb1a58203bbbca5c16923992cc9767aba5483e4d46ed39e71000a1fe920a4c1c211a14e63ace03635a2d77e72808e0664334890b819b3caff64a3
+k = 2e3db2d82c4b9de2bc0dd0a93c1c5b385f75ad03d0da527a034da2876b42e43cd88dc64833efef54af902d85c568bb8e71684bb16b28c32d80bb3e9911cb1b74be6ec520d99b381
+R = 065f4715e87ca3541ea695878ed5ccb7d2ea6eed5d6fc5ec29f9aa8deb4001cc7c06185d6ab2dde4347344d44f8300a1e92513af4690d713762336d2e6a94d3324a224f06eeadeb
+S = 20104e0767530ce2f4351af4977b52339f34d13e458de0482bcd58ab38ee041c9adc7b05650260d919b2648e2f820407fd60a8d6b4b991b86eaf29c2c4d12d3b0b45cac2ab22c5a
+
+Msg = bbfe66c82bc060bd14fd0e40769d9b3a026eb447550dd9f118c30d8448f725f8366edef042447962ba7f7f833b9e9094d0ff600714697e632626e7d12a592e040bdcee166dcda93952323191021bd12f3b1647d0f25a41739994659dcbb19333ca30f46f539c6f0a5c354cda8969a1eda572a309950c84c7607eb8ac20163912
+d = 13bd80eafa67663e75d7ae139bf285d2b9f1e03d8e32153c73e26d06e86d7acad22bde9f121a3f1ea674dcc1fe67bc7f5398d5e92555056bc046a02b0ba86c2a0dfe32e91add5b6
+Qx = 4c01fef7f2fd8ee61726af1a2d046c7ac67716403b99e021082e96d733368c6c64d046986fb01a6b55cc930517762387eb2fa4a8eda23c700d88065bced8595188760170881a329
+Qy = 189bfdc8e7a710522ab5416182c9579ca255c5009e6ee6604ab033c1388639c0f7aad84642290954db9f4f7fbffd17481eabed38151160457d68ebdfd8695b5035e4e6e06532c0d
+k = 3c5868345c5314aad5ed3a74488a85b2f049396022cdd1de855a0b33c2877f72e871805af3ed8fd7e7a392c4ff63acac6a6f0c431ce7af680984e8c81d0350abe491a01f0f9268f
+R = 0c7e96b9e9a5935ccd51b901aadab6e01ebde44f57e6f0b84e7b58ab4f62ffc0f3f3f980665c581ee3de233ee49d11599529348f1ad3d362837c041cf98192bb324f577e973e1c7
+S = 2226922271fe8307bf597742618ea9c1c271c22c25b49aaa7c9292a81ecce2a55250415ea2ec8ffec54bf0508e64426cb9cd7177265fecc40e056e96cab661485e789f0c435b72b
+
+Msg = b35e9bf686717ce3b16a59963a32a2116130453b161a4e7ceb27b755856add836d779696edcaee3b5c986523891c8836109d431e55c23afbca022437ad19e6777efabb6da3bba1f5f44f905395b4cc7c9210590fd38da621582d059598e5e4569e904358e0dfc0dbfda4ce75538aa97480912852bccd433a9b96c9c66e9597d2
+d = 30834b0a4284097cdda2ada6947c6c281f7290a49b56becefea1e2788ea3ef78fb96807633c47c25138341768b241164ce0d42f7301728b928be2c047f2eb60fc2f844ab77306d2
+Qx = 03a21f0d8e01a64b235cc455c291e3fec8de12682f05544de207d910c7c24c4cd56f3354500d994380ebaa0b49a7604c6233a9aa24934c550c0e609f65fd4073cd6c1ee4170d77e
+Qy = 67c83513e4acbdeb8343b3add40261edbf7c8fe0af7417264830edabfc40200283b92484630741378b997c3f8bed7285decc6ef8633aa804b3846d3b4517e5ad836dbb1df475818
+k = 0031afb24fbc52b01480754837cd84a5165d5f2ad1a1d572b92ab546c049413806f0f5239a77c751af4d57a84786ed1c11bc76123a82e7db3c0495b2fdc5fb9c8720eb7afb640c1
+R = 07a222cddfaea617f1190a0bd88af4d1983d2543dfba25c5036fe24529bbe2e382de89dc1e36c1f6df59c8291d1c4277198084902e5619b64128c265bcf03b7d8cd6b663c225f11
+S = 1ca84c146ebbd16300b813621d503d8c754e4b11446d5ee31cbebc71f4b85ed09c5c94bbdfc3570e8882ef790393234c5ee9e52f7d5b74ff4171d930af817eafc40ef203a1ce613
+
+Msg = 57b5ae7e95c638b258d1e09b3fcb4341e203f5706862e199b103c8fdac72cbc5155e5cf8b300a0b3fb0ce1f897c45f7aefcc528182f73dd450cd84d5fe9eadff3f704dc2a01b4e847c22df430efd1c66b0199f3e5b59348af5386962a5ef25204fd230b54d58d7fae801c086f8f405d3d0aa7a9a9da15c22b868817cd897d853
+d = 0c81a79ced1eaaafc31b69a40d9939f4e484d625db6364a8e589b6b4d336d458b44287ea6c6aa7661113fc07806b147ff98216fa0c08708dc9d651821b922741deda522b4e436ad
+Qx = 25f9b767b8796466c1cc8a1fe6286d591c04a0d115133fc7910640032b898a5c86547f57794e5aac0148996151d3ecbe0d5939dbff5722679ecff378e3f21bbf1354b1eb294d1a3
+Qy = 074c2b91ef3472e60426d2fe182ccc678aa0abb8dda15a428e4f6f1ac401b015b2b7d83535a0a92770cff7666659e1cd33941bea1168cffde82db0ea83668c2d387e6f4bdf28cc5
+k = 27b407a29553203b829a87eb25d6d140e41184634ae1c64c6ec38e9012d0b06a1f4ad9877d7ac4236a22145095990233e6c102a0052ba18cf6e47e289cce4f2ca21514d8868bd68
+R = 02416e11fe2f8e4738ecff1710dc827f4e03c8e7f04a4f52e755f0c1676abbd122eb9751ec1fdf6c7ba04b4e29f8dee52bff7e9e726e28cb3de6f9abf2dbf58c0519ccc7d70f076
+S = 0b96f107a26097a468c1d410bf90e223cd72c5ec98d4ee4ec2e32259d7670d7e7689e62d36549086139f6111884530e20f908d7be1edab75180c81a70ece341f7eda6e4a43a5ad3
+
+Msg = daebfef74b452f039c999ba0528be3bd9e16deb5f46f6eae87b63db8b89952c949fd7db08311871eb2596865eed107aa065f030226ea675ee3256c31a3f85ddf4c21760582144e07af208f33c5f47cc026db5403186a65a47940691ea2d74ffb1245676260ef5717dd879d8b5b72d96f87fef5f762d4fd17454cb5ed83d8a11f
+d = 2f24670c0f77d2ca0266a743023d2c7413d56d0b5ec77b454ac59087efc4ea4d46179e10278e4ba416ffd8c3f9786ed202faf8251c0ef5a9ea5371fbb35b7afe3d15a9cb4bad975
+Qx = 2da72b8ae64c5ee717c33758ec26153a342936f9d41dcbb136590e1303b0e220ee84c8a06b83d4d9fc924b8808de94dbd780cc8243bc4448efd27dfaa1572aae6abe574be664939
+Qy = 3b3a95d962c48a81c48713247801e4ee630ec7956c9989023ba16f02f5bd1ef2edcdd1c8d314be933225c64b7f8a80542b209b944e1f3fab95795ffa134e7e28e82307dc62c2962
+k = 2bbb9abd2732994011c8d294c5342e8b1f7f3c1f5718187e9f75832604b43bf75abad5ddc85e8d92cdc42656cc9f3349afad3f9022ccbb4937d9ffa9cf48314b604e82bda13475e
+R = 3986059f2e096a3675215698e23b53f471c578891f6d721a34a0d231d16348d5bf9853c79c4f4aa94642ad06cb7bfd11f724800cb5477636b6fc0586fb6efb8eb9bbef62329a884
+S = 2beda064eb3ffa1c3b5336613704b3bc3d4ff7b0e977df16477c7e33d480d678804bbdc08088186fbc4764be398a26c13f88bdd23e844be0d7ce598bb87c1b3430da02ae96b3767
+
+Msg = 62af0493ae79d71b552c4647d1fb7ab2f282a91cd44aebd8ef344dfd77b521b0c0a3f72e4513c8ecc0e4b84efef3df9482a07ccc1b740c571c5e69cb913740a792aa231b9dc87edfb72bac188293c6c6e788cb3dff32e8f483f8f34e21ee7efec71302cc3bdbfa47908a135f6ef3ff179dcef26d1a3987f7be967a6c0f799b0c
+d = 20985f2c6fe3ea04bdbab66a8b6167e5969c073b9d53cf3c77cebbf73f4dbf75e601620ec9c3107bf3fbfc6c79f8f063409bf8fe1d14b19e323d857e23dc05157d270c7514137e4
+Qx = 010712d50ba7752962b140cfb943d9e8dc3bfa497bfe81c42606f4da5157656fe2ba5cfd33ddffa0f27fabef8e267688943514df45e642ee0454e05b49f7c00f5785777897d225b
+Qy = 1a2c7db6595c6d4c55110210c564cf102739760e7f5a29706fcb2515d99ca00949d5b4f291716d0aa1e3a47efb9632410f60e2fee1ada47171f902f632bee85da75c7f3c895c24e
+k = 2f26eaba6452e687af452d5e1208fa011e4c84ada92a38f0a204a254641c23ffe1c184fa8bfaff047db590ab40accda408717e4f30811b75cf3a5877ef99279476ab924d92565bf
+R = 1280adcac1c79352635f4165f9c5c1b6e1e6e33bd74d781773f483f637462f80340f8d22cb24c9db5e49ace95a676df3dde53c8721f672006382ff806410bfcdbceda50e53285e6
+S = 07dd52973ef30dbd480047732622fb1b695fe3cfd080264d2aa30a6ff3dab4ab362518c4f3de4fae042fce78c0c8fa0e763eb187eae2ff8f2e79b3f38cc3c1aea897e1f28b71a19
+
+Msg = 566f17851951777ebea3f8285610cd8ee5f882a68e7a4205e6fc9e2d66d210ee2505ee73d6503169f7b903012d43e7e99efa493a8e6ef926b16b9ad8f52156840ab561fc6b680120a88714fd66d1d0742189bf06c155e1138ee5314707173f7352e2cea0fc26e1553643f2490428718e44afd8372cbb7bf5b88234318ebf4355
+d = 2b3d641607b8a141f876f6d285ee46aea543880e772dadd5dd83d595b9643191d9597218e1d6adb081df133304037bcd2c05c24a54e6c4cca64fb2cc4569d6882315360059496d8
+Qx = 42f2bffe25142ac6c1af26643b0f1c317b34950a8a0f112a0cd4ea4131303674328e0bed5d9bc7ffcbb9712387cf67129365b4fa8a9e785b787c170463b24f6a7962c1e003c8732
+Qy = 070962ac4d3220f367f18caa7ceaadcb82fdba45cd2c034a97aab71f7f7546c09736cb080c10d9a95a5f984aa4a3ed32d22636a7b3d5ab29c86d85db59f6f17ba29eb220bb141b5
+k = 23d7021f5376e7b11be07288a0e47b4326c026df80d7e08c9a0fff11deccdadd479dad503ef2d4fa3f0ab2aada604b57fa7e09dbf5c8d493070b5faebb27cf68ad0b78bb6f3a9aa
+R = 3059720e7a2dfff03789e7a514f75f2af5ed18cf1568fa2a5354dcddc9d3c7a90605e9b9a3d0d6fbfebddd615cdd52845ff922873079e06c4f349f7798410ee18e0c69045193668
+S = 1cc40209692cf5f8ed8b82372c95033e4199d378a28b9edcba516820ba21af1bcf5c5df2ef4146b91fd37dff89ec8f9962eecce5c5e285d76a5f03eaf99fa132e98cc40ad66c296
+
+Msg = 25155825fc4f9a1c4dd1db837008e7e2594a879052431f5bfc76d0d2565b8fa726008befaeddceef73f3c60fa2cdf6d9a70e56d27210bd013034b38861ae49640ef208d3fe294ac4362f8eea44f58af3af8a9167a36b5acafb7ec95652d5885a0e08067ce1dfbb45a0c89ad1acb53eb404bf88fa5c3c463a0f912b5a2522a0d9
+d = 1afeb5ca87c81025ddf09c2b2c5ee22ba0105c0e619b67a324467485bd839030d149fee44d8bac6f5902a1245a50c3437046b7c89a84116b2147cddc645b6d2fd24d68e8d53bf5b
+Qx = 119c46988a79e3ae8833ef096b0a1e2886c4b114ccfe881886859abc031df2b1e75818c82be8c5abafcbc5d7b3b8344e98e3f413d737938845e6eab5aec7e507f7baf0d339a362f
+Qy = 3190912dfb5a1a31fbbbb50784b18051489a3cc0f44c42c71d3a54886ecf40507c3240395e8ced37b5253b915fdedd38f75bb26df2a0a8edba865f898a15f2d96f632f7f0638864
+k = 1facccc127c856db1994c4d9e9c76de6bffff81a88d7aa0ca1645e250e07674fba73447911c5b47a1aae815d5e96164854636d3168d0344b2d2d913127011b6434d5a5e545d3bcd
+R = 21da49326f39577ee9f65cee64006525de88a834365a00f4f8cfb9a01dcfd6349a3d06bf95990a2c17b7e95cc0589714b7a795c7016b29bc844ae9031488ca354548976eed68415
+S = 3364def38a8ee3116cbd971794c859776107154234d8b198efb19655647bb9228c7c6be2e703672f795ed37481e994b6764d0b7c1bbeb2bd1db90b34f460278a54bd480bf4e9adf
+
+[B-571,SHA-256]
+
+Msg = 29acb0fca27e2a10d7b9e7e84a79af73e420abdb0f80dd2665696638951b52dd39ca028166b47a3b6a2eaeceb1a11c152383f0bec64e862db1c249672b3770909f775b794e0b9b28a5ec8635a996d912d837a5f22471b40ec2e84701a8804127a9f1a0b3c96ff654700bad3167240c2518fb5dedcc1be9f56a807083e587bc56
+d = 32c97639b69c7cdbf419286d0a1b406d9b1f2886521a8b979a36118d2a368aace5b02dd8c515f2041e6fb9f026d1e82e789dc826a56d2ef732b1bb0f49be2b696ab5d3d5694a2de
+Qx = 0087ff1d8a4644edebd43c2d43d49e140940d215f272676fdfb72ccf58a12021de3d668f2766848044ac404fb45cf6e18fc6700f87aa53b4fac1e35e1731814f8a9d0233e2942d7
+Qy = 29fad3638177541d8392111064837bfa77b4455c21c5f7652e3fb302f4bff4a35b74de8aff3806538ef9ac86964cff755a81cb3002b6fb241ffcae8ac9621b8e034967d650836ee
+k = 16a06e3d25873f6dae16bb2e569720ee9c6ae7b5ba36854c321a80be8b4be502b895e1a3d161b001f6cbcf53d164b5485d8a5efa0476f581f9c79b3a291025be01a435e2fc5ded3
+R = 347138a43f3ed1a1a26f5f11549eb8a41f64aad302b6383879886216ebb6d08a4ce270d07a5bec6018eb313430ff017c1bbf78556436d9255e97aba1481f0f16b85e7320df79d69
+S = 28f35e1aeae288122b043deff9ac87d39478607da60cc33d999b6add6209f452f631c6ce896afd92ab871387f5ea0eae5f6d5cf532e7a6ab44dcf44acb1fd1daafaf1ad5423d8e8
+
+Msg = c92d67cf6536f5046e15b02158da698bcbba4ff1e4e9e9c882cda67f817210402ef917ae93682c9c3dd817b21b73c6c00b7bf92ea80ecbbef2e67f4f4379d078a2b0f297742b2bb9c3fa3297a7e8079f488555bd37715eec92b4b1cbf897640ae8a1d2a0fbcee5423ab31a37629f98630275e35094a896cc574be0a449bb1bc3
+d = 0f93672159276c5a293582b9f49607bbdb970112f6c63b2b3b5d32ad3c8240c86b1af13a8dff6502c6b6a17712cfd988f8cd23a60693d64104143b3f91adb37f852e9e11a0ef110
+Qx = 19dda59a839aa2ed28f69a62a3e3a753c6fc789fe0d8551bf59095f009d0327386e6df5437846c6803df2442e0359a367d04f117e3965397576d4287398b4b8c92ad278df4a447f
+Qy = 4159ced60503f7cfcfcd587bb3608699f54693068101a838d575715de02fff81058d025dbdda430e176f60e423e6fcbba889914f6409ce51d51e89e4cd7bbde6d24404e5b043e79
+k = 10dd216d4b3da2fa6a75de60f722f1f128776741cba002c055d1445581242a175318291fae313eea11fd905b20d26cec845f57a3d5bf23ae4dc93d886c0594f1cf7be4f59f3e3eb
+R = 128d5c00a48c7352eb980d9c80781f8abcfdc1ddae415b7ac94b4d85c3d7d4f7316e2b3344ca50c6ae82938bc728e640e59e2d733f0c7f7025e66c15c81e98a845c1ed4843b589d
+S = 1ab59ce5e54bffc68fda96c920b839fe03d1976ab36978bedd973715ed631bfc8e3edd100043ac527aeb5ca121da848bce4ec9799f55b22454e9af32848943058b257e815b04056
+
+Msg = 15413f614c4551e3b138b64f66d15f8964c40326a42b0afce820778eee4a88edb127fbf575da5263e5a2627b5461d311813ea868e6417615e7c4938313675009caac28bc7a2f4c0bc37572d9bf36a3b1794294e09c0121ceecaa4b916df45b0dd31225415e6c87cfeeb092a008fce2c543cd62365779ae28f29fa02a15d9dcd5
+d = 3db080bc99c5fe7e06d5032167af56783cb423fae59fb5b3c6bce5fbedf56b7b39b17810e48ea9a172881aa1f42f5e267349b60294d4a208b4437666b44abcfee5a1829e9467908
+Qx = 59d1b3f680da784b49dde3b361eee819d67339447d7bdf7965550264eb63bcc7674b0921f02e15d45466dee52b4c0a50c2bbbdf226af1662086476a9eb1236e3d4c2b6219af1bdb
+Qy = 4e3466200dd6ecbc268cdc1937ac5123cbe33f32110cfdb8b7536987ddf5c9ef2464d2334f315b9b489cf227a6300b6e054fe40d36c057a692f2fd3e762624069e2adefb65d24d7
+k = 37fb32a902eae0c5d7cc9f9018a5d1a906a3d1b9adf5bfb696ff63f105cb2e736d9bc1961677fc897fd3a9e9bedd370be6f25a03fad425b5a293c66180df78db33aec4a188d3db6
+R = 3aa8ab9fc9073429e52469088aea91f00cfba271b9dbb84818460883effa0c51d6a48c1905d6f58d1312af073dc8735c29957f30324b467797acf86e028410de016338b972013ab
+S = 198a746411333172daef76359e7ad23035a0f5d14c283cb268828bd876b96b5f767e0c1e2796def7a51429f39ab2332ac25d8e4f263f8dfb9c4c98da2ccc398fb3bb9a6b28ca28b
+
+Msg = 9f901557451ae2f8ec79b6d4adc794cbfd9b2e6d28f19409532d91682820205308b41498a4e1ca247a2baa8da93de95e3c0f7afd6ca46bafdbdcc6d3374a12684676a50988b86a960a82180648c8c1e38f8fd9af604c7be3be4b24799f4544ac96d6360cdb83d1d0847fda21642934fd6cf65385b50d86d4656987901fb88d0c
+d = 06ee767f6f36bb8f364f324d8346455c899a49237d759003dd52cfa13b9baa4c71347b134b24ecaee32d247c34e3787a0c64bc5d299b55c86f64b47521d22f2c09db225b0c84cc6
+Qx = 3f971125860f4598fa310eb7a8c6b4e0c31bb721fdc17ce6df9af557beded6006b8eab10ebe7f3c4f3d759d4a87dcfc1fb767ef87beb1f5c845e3f41503a33b28b2b5aa1644dd1a
+Qy = 3296062514d4e89d2105dda5bd65a315b9770c45afe4050d8c3d15001405b1e32be5867ee90cafbe4e239dd44d030b4fda855182f1fcf80963c1300cb842459aaa8c2827371876c
+k = 2b247e2dd0024f534ed2797110df6ea4ba166c34d91c94e43b045c0ff80f124bfec1cf3be3da7c58389d352c8c5c1bc2a2e876a7e56301b1e688a085ea0222697fc63141564365c
+R = 2858eadd14373aeca65ee5a2cbbaceae4b54a50e0941a696406dd86d05c07c5599379c066b2288d01b2a43c9ae34bcb8c36f59d490aa8d066fd3d7e539ebc620a7176507ccfb232
+S = 33c20d26dca20af2c56982fcfa6f085bc5c317d01f3b1dfe0ade1ef6e3e960b18b626d17d6696c936f04090ecd9606c2a6ecea1cd1883bbbca8b3dce3b0acb2688fb2834aaf922a
+
+Msg = 959fe5a19d7aea2ba611c7203e19f8e3f3cc101e03a98f91adfef602c424c580d5a868659368a930f9883d699fc633bd07f6cf8de474937db0bea86fa7cd140ec2f202663813033a757b93bd72afba15be5e47a4eb93e8a666aa1c72c241ca3922547d63fa3732fec54afea7ade84302e2f044275bb67433fb6b125b7913143c
+d = 38e2571d9f22309a636586d62863ed67a70538287f3ef88b88c3c2fa1a2900d48c342b6f15c26b8e7fb4875cda4093b7de7ceda48fe1e2cc2975afe958040881de61f309931e48d
+Qx = 5a221634ca85059543e2caf8bdf79c43bb78deb35e9c89e07d553bafb6b31750a1d85ffa7689e528c11d8a3dae442b4fb2a4a21238d636eb04ccc04c8b5d794b0a213fe0480b1d2
+Qy = 225ff457b6cbc12d152b08025cdb7e1e921ee553add9cbf83228d678d5a9f5d3d1fb4327a74c1dcb5d69a5b98f3ed1aebef0af09bd49d253a903636ef5a66844c500fa221470f2f
+k = 3b4de49d57040141f3584ff596eda457e2835085d350b75391d90abe728723e1d1ac6413979d4fc3eba98d72a01248e6510c722df15df876da881ad50539e4248facafcf311b464
+R = 00f259038b4d3d036bde101aab29f4558e88e604c62f967bc7a35eeacc6a56294268f8ab00a34f9a0319b07754f502c98718e8b5c91093cdbff2c8496fd63d6fc2c50a35f87f423
+S = 2350d5406922e8822a91f7c95cfe8524f017a14cf7174ce534c60aeb351510d06ac20dc1249129247b21c72c14b02b710c26c10899bcf995143aee632e294176e903645b660e998
+
+Msg = 97b9688d9ed5101b8cfb19e84b89cd644262ca1c7ee18944e29ddd3b4cca78e06338b270385b00a5e8b91ca5e628de3bba50e36ecc695b3ea737a9cf8b36871c473a54ba17819f49e730c0f253b0c769aefa6c16366fd2dd612f330e95fb119fcf3bf7f3e254438c0ab635ec04a8b2424a05b483ecf65b74a93636fbab7bf1d8
+d = 0c8f5736f1ae65592f3ca850f43d06441aaad8c03820f3b08d8a6db46488dcfb828459f8b3f34af73cce8dc7a5e3834e085a64523d890028e194214cef4003210e6eb530005b01a
+Qx = 667ce3db45b8772f717ce20755ffaba968aa1314d75c84073042436823fb54bf8dda34a6bb45a61d610745b1fc10eb0eef71c4f55b26acceb442d822d6e2a27761c73b740f47289
+Qy = 56035da1adaae894e361f5283b3ea07b7d9f64a298be11de9fb487c2479b120381f1c60cefe5d32d37e4644ac86a170f82b1c4443eb71b940b21c7a016b559c6c79835532c276fd
+k = 190468668989a607a3aa966cad071ca8e8eb152b0dfca9205bc9417a3d612ca1105c7b90340b04acd96a5223658adda16bf6b598ea9f32a2f8d1b61c2c2bdc08d6a49de246240b3
+R = 291e1fb18edb7a93badd6fab6f56ee0d390f3b6d298e97312d5277358511fc7621534ac035f3518cb140fa4ad5ef7d889c0d5f3f52a4e4d06bc9f647f99695531f85a4b76cb1184
+S = 2d916734e02b0a98406bb5a9723486a7ed40bdd0b39c4cb802af4bafd519803d23c6bed59a80c256a14eb878229942f67e0b8159d5cbf24b719043171b3958fd669adfc72eb7289
+
+Msg = f08b250bf4a3980cb455338b3f4173723b3f44c97bacc9cf550149794a71426e398cb4a74bde141d8b7b4a72942f1c069676a9918e27792cb8f085ee037c78e3c468adea5123c4c64d8ca6a39f2f90140c5d2d80b669cbf0d1ccb466b18ded83a1d5f042c36188a04111c34ff769abba9aedda40a87be1e24b700225e2078056
+d = 1ee68c3994adaaa9e0d61bfcd3bc1cdf198d3fbfe28a44e5dd518867ea04b20e795eadacc48bfcf8e8216dceeaa069b756e8e99ed87b6b1d31154cc9310bc3b4555162a890b0c6c
+Qx = 3efc83ad15d9bf889c9afbd769bdd1dc8925b0462c93868d85ca7554b540d8c3ef7b9a63becc85981972eee8a70b7f948098ac050ad594ef2ec249cc3b557844bae9cb2cacbf397
+Qy = 42a012b3a1d9e46cece4fc3460a2bedc9af4ce0289e95f69550eb3544f7c105b5769fa52234ac88f9045ea5cdd4937664846d26deecf511ba6996ce4072e763e8ebdfe709660888
+k = 031df03a6cec2346b92d9ae7d3d983edf577d9a1bb88098f886f38536d8d8cf25def57726790604e674d036cbcb864bdedf8475ba9c850d510ef93b844c037e04348d5f48098c20
+R = 112dcafb63bb125d9610e59883df481bfde43589e46656b5952cdd72238cfbcfee79e9165e3c9b89c9ffed12d303225ba2af19e00048e20e4edd3968807e4885003d148403321ef
+S = 2ded1456df54a24214d8c1d3fb314db52b046ca31458bed69bb3aeb6a9ece509ee521fb8046ed43accc7e605440a09fd96db659c98a7dd606758c0c47e47acfa326b9ed73ba4b28
+
+Msg = 1cabd16fc29d7d919622810dc8b23c770b790b98b119eeab1b20900fa94fc2ebaf76be4f5eea91fc5276c5621c8677d4d117c4a5a782ee2ca1d5b0db997fdc8a05b6b3fbb833d7a7b81c3c615c2a662929760a96feefcf89e46b563314c9b77c86bf34438458b43b694ceba741b97dfcdacc0ed57652ae62856ce10ed2690770
+d = 3a6fbf66ebc1365ea7699c72cdac2dd85907ec59cd26e2d18713354b619ccb83b7fc0db9193aa8493c1855f1a83fd987cbbb65de17c59fbe79256aa5392f4eba045346e9ba26592
+Qx = 559dd556241f9b11d0f91c5458ef6adb783f9f5051bc12cac9f0b214f836f7b149d00ba8218e873410a50445da9fbf68673f3282d783988981fb221d0579341892ba6824e0cf4a5
+Qy = 05dd0e594ce41122882538e51e9bf29d159fcbb8b29b97c5546582390ad5c59c975271c58ba1e75d70c3898fea929ef7316ee830eeefbdc69bd80d7b0e8133b977cd573a3b422ee
+k = 1c5a193179ab859ec1166575007c3cacb30d31f341a0e82ed6d4ddb32da909dce08acfa10fb14183258caa743010fac6f7d0fb1f8c8f55c246e49a97f2bf571129144c23de8d68c
+R = 2625d0bdf37396585d22811a12ae7e0c3f512ffdd0bf4d048379434af46c03c6067dbe7c271c417ac5307123bf58a9f2064bd2b3a2d4b4efa3027959bfe63e13a851f46a21da6e6
+S = 13f16b211b314a7e9918f3254da2f1aceb5340713985610f03ec1d0a33ecf9217d61076eb153d8f27aa31aed3c9b165be52f8d857de362b2c88db5dccfd708a996a46b76b4ebd09
+
+Msg = 7bc8bbf5ebeacf40b3c82eb6eba5d994dcc6a3f2e12ef741f90f90e176d20c21e006ecdaf14cb5beef35bff46b2c374d9ee224516679b1a9e9255cd8ad8e60ed234f8ee7e0fc53c9021488158217d4b4369cc597d6053746efa1e73340bdd73c1bd2eed57b92426fd4d278d6a86e8be0f0a66ab3dfadefca8831b2f488636251
+d = 145748871a0b5c1cee628de04a12fd68ff2b154fda96e47afaa96389d66d22802968584f6753d36618d49ed205260f09d3f5ccc2b27a34390ce58179b9834ff92a86d66ea0a97ca
+Qx = 6cc7ce2782dd67cf1fc16f1b24ae46fd085b969d936fefc409a9bde354cfd33a154a3113e837cfb88284d75a96f5fbe85274fdd0990af4a033a6c40b904a5e0f666e4d8b8bc3532
+Qy = 7adfea166087502657bf9e2c437beb2f62dab041553a06411f6c9dae83a2a2749a4e5a2a36fbe23d40816b1b8d206b9f5cea20ef200b9150061ca22fee2076e31c88d60a006ef4c
+k = 26c820dc92f97dbf545f51db7d5ba649333dde38eaa47d8a7edad9a3cf3e6780442db234632458ff17e1d7b70019916708c128601ff547ac84dfb0173cf0a3c5d69ac96c3d7d395
+R = 338c88d1bbd0b93f3f1fe1ccfcbda65fa1667ec471730a40eda87f57b3eb63d979d8d6d819b974619799c90b09f33c051b8b522c3a1acede101857265ce1b58cc7eb5698049f494
+S = 3637bf89f9b66c7ebd8f91a8324eb70a510284b39f0f2e45578f26f5f1e4504ad70a389427f4d58960cbd918c2f8279de52096e25a1b0b0c3929fd5ef56bab6cde7c0d8e9d2fb30
+
+Msg = 0cd2a45392871c0c262e7e6f036946354bb41f9c2187b8c4d399231280682f3e0a09731fbfd52c76ee63b9828c2d731f4cefee0a8c46419c398205b2ff80c67d7756db300a0a8385fa287dd37d9126f75998ae1cbab5136560592118db52fbf102b7ff0a1ed45b8a91a7d99d13a0f7fd4366392264aa1248d7324901467457ca
+d = 3c71911d24ad19c20fc1d8a044d63c9bb417abc3778d7e6234c6af79b898cbfc2f2787244708d2fe203be786edbdc4c9b12b413156b7b0bab0be8af895d191d853cd58aafe1ccce
+Qx = 6cc47aa586a73acddbc91398ff5782457e6da2b10e265153c678789d3d7fcfc485b03b089eb67e6d6955d5c8c7ed5f933d84853576e76fc60332e5f0a62c3ab23690317bf1b423e
+Qy = 15604d94ab9f2ae1d74fe46b1a070160513709de2ba8e74fbf9922e9bbe7f6e743b25701a13f73eae0db0c98dc80c5f8528e16610fcf18f60eda3357ad5878add2554a6befc9d39
+k = 3681fcc5fc1f0d7d413abf2e44cb5cce9a4a252ec449ec4f550df4a172305eecc072454efe2040aabaf4fee58ed19c9090061d3c4835c5fec38996f013e5512c0147cb14a4f0fe7
+R = 0d3c26796bb86b1a20ed4935bc3824bcb9742513ce91a66dd523a3c0d8a5abe63488aabb806b5b113e90d3f3c80e3ffa01ad051e6b0d4edfc641689953ed65fafbaf3e554be31ff
+S = 2e3129ff95b06c274f7ac08882dc1da6660269f3dbd21a3e48377a628f6d81326084bbb8d32b794fcbde8e574f853636fbbaba480fb36960b0994210bea319a99a46e29b79217b3
+
+Msg = e97092625b09c9ae6e152e1cbee207d83361f34cb9b0e727c816a5ed851f12f91fbf88ad9d4c8f9d07350f5d828fd8574eafc768bc72a2b18aaf4d2b48fb10f7c3431137b51850154de9706487d69a40a8f4cb2c799f48c5d8f518aff752500de93cbb94ab04ae1e0c7183a32d79a27291dd07b5fb6e6a4fab76e85c3a8607e2
+d = 18bd74698bac36ef11add6b3e3fad227ecd868f370ec04569462565d2f0af2340bf793486953a7b79ab04f0ab1f0e4fd16bf6b576cce677d543e73aa8edb0e50372f24ddfbff966
+Qx = 231f891e63bc1c43377faa56c5799eb1c877954ca2cafdeb4883ae40bd78816ca5634f48f5ef5c22dc7d3d0df208bab4149815274d7b134cadb700d166a5e3fc73e9be1bab72522
+Qy = 469ea29ef860adf24afdd386347763008ef6fe2488d902c4d513bc0183fc52742782a6fe500d6b581902ccd4f9bf077f975bd5fa89bf240723b99f726c9fab4f953380745ff9e17
+k = 1590570de563ea96eddd900e4a0a7efa2e4a0b389854e96af32bb7555f098a8cb52d160abcfbde65998c34f91338a40d40cc03e4a9a241d3b16b0e893d3f7ffdbf8912f35c7f538
+R = 32402fbee4831b16d762ea2cb218279f4db5e20bc8b6e2e53e89a2ef3646cfb0abbac36116c8c708a1342db2fa0abd39d149e09db57aef65ad8092f37f7962f98c28331f0f20b64
+S = 2d1e38f40965e2697abc7df5896cf051ce5646f135d1ea0bb470a43250af8df0abf2a04ca1e0f1f31013025b4136a8a6bdaa474bf50752c571f883829bc3a5482ec20e2b4a72c90
+
+Msg = ae6723b8df5d6ab5fcfaa22d32fdf106d211514cb1892c7c43ca6cd85c2532f85929c8a259ed251215063cf92e1502528d1e22d5cf67efa0b8ef21e8eb2f5dff881ba1433e8bcf2b6af8742ecb2bccde081e534615a305562cc22d3398f61f277d8ca785842bda85d8a40438d9bf1aceaedcfc22c85533794a69cfc320931d3f
+d = 335699bfd058ee2e6163f55d1816bf3669acea8b73be9c4ddfe775230925e6093cff7a66813adf22222c8376faa106d85ac9f3c67929bc58d8986795b6d35d5b9fa546dceabbedc
+Qx = 7995e02dd3d40f9bc2e6f4cb1c0d29923c9022169e64532d1b357f36264d18059c44a8617a6f1136e72648c9051a27714a0dc833428762275a1b5635a3ad91e65d2713236c20f50
+Qy = 6167d5839cd4476a638c50db218979a93da44dbf97281d90daa8b9b530960c689279fff6c342af97880db1e9c5ae57b91d7be727fd1c6210ec59416d1b675f4dd666e0b121d144b
+k = 3f037ebe0e4c3910953e123becc09c0862490e7f590245c4cdf9ea5fce930a7d7ca5d17f5689edae1ce706b90efdf84cd82e06e4ab95e9e2368db91d50110eb91cf44e50cdce2cc
+R = 2baaf025290897a5d68c5e63543256523fb086a6f1166ddfd3d50fb307e0f0cf78b5fa895f8b71944a7b67b8afe5f3e10f2d248aedf573860c42cd7aff258055ee7cce472e8efb1
+S = 0f4d239f5af023ff6c94ad7f66d43201c7e40262cd92467c4ab54be8d2b8e6577d14375064fbd00a6327da62f03f75262392add0ec119d820205065aa6238433fadc8d1734b8481
+
+Msg = ee20c6b61886e02ed94359dff3559522ff550ca126fed4b2240ea7d999a182b7bb618c50528fcbd261d5e497a991fbac0cf4c105c0f664d6a00a9001c1ed522962fb44dd4159677ce8f1531019f86457c055c9cea6247086cdfe0442485cbbc4386ad002b4bd39a1a187752437f04569705cb7adc0c68f0fd059d946deb63f0b
+d = 2c3eaf801330b3f1b0504f2399f1d24455db29911f750c246ba0a134c3b59da8b3562911197764699a92ea1d95a2aac587e24f743df1dad3e1cf7edf955203e24a0225717f8d2df
+Qx = 703d69e2dfb13fb6e695b0b30b31d89c8789e8523a7eea15673aeb4f1909192c06c27558eb55f0315f395b1f3ce84d9c304905cfda1d119bec33af9ade4420de2edbe75cc5460e3
+Qy = 75e35b2d6a8550969d49ac5d656afacf68d3a1dc6d17666f46ce3413c855b627f0891912e373af2ba91211c20f067d66056e6bbc0814ff3921d944008b25d8772cc8d696bfe1d09
+k = 0a9ebaea478893aa0e3bbfd5d007bcec5ad787d9bb5a8e9b8b79865c584966f0bf040d36f62a8e97c123d2adb7f38eb49a86e9c2ce1294d04fef1b6fec7908c4ca1a70bd1699a9e
+R = 2d495eb5f6fb187a0ee1fa772ccefbb969e854abb445ec19ac3860f40ee65f53b92f6a797003574bccf0b9de8014ad4e5745ed264eb3ae88040ef6518809b4c66f691d496a85d51
+S = 1840b2977ff137f2a8f2f7c25e347cf1262fd128e008e30e4752315deb5231098c65e9a585496a9d6b5b56cd0b6d7dcb7150a077fd199be2d2de0262aa84dad414e100ac6162346
+
+Msg = 734a9eb8288e32f5a67cc1d88704523ca2c68b798d90e188d871d9f50d2da2063baf1ee6685c45832a1818aabc9afc0bc935e97969dc983a484f16d2bedb3c7c0b8221408be2480a5562d5d1e5d8763d1e474bf2826aa93a68c3b870e3bf34f4941cf590d88e1f5a8cd782a33992213f3f6b4b4f6dbfb3c3c8f21f5eaf4ef609
+d = 1c3ff067497e5d387f31f0ecc9c67b3c0dd6ec8c81318c492aad83c9dec6c99e4fa47447f6f7082d636c2591d0df940b947d0a4ae3778e2b7cc8fb92214638399def894ada276b8
+Qx = 2e56655e37b3e753f35eedca95f8ec07b7a3d3e14e365ec041cd9003bdb78a7a8b8ad277a67da5d63dcdeb0ee8d8efb68fe61aad9b1fbef4373ab13c44efacf68cc499faf5b5dbe
+Qy = 47bbec643d74874b77f0fdbbd2df3f3ff0d35f4b3e1534b2c4d5c76b8cc51693a70e17d1d4cd64713c5c05966c826458fb5411ac840ab5998bf3cd64a0769c3e075259a70aaf94d
+k = 149848f4534eeeb45fc38ddeace59e8f83f0bfb4cfcd2b8b7acd0bf19303051a6a8fe75d4cdec1be036645beb075c772aef4a58785c16d984eb43b9b0317446bc3b3abfe7ec2cb7
+R = 17eb68556224f995733077501ed295088cc1184fa3872f5f11e97cf67c7bc1febebd31206a406c4479b60246a517cada5859d4f1aeb98dfc108e96e9898c6e71e59e39b6284895e
+S = 22904497dc7a98fbe117e4427d74f4ecfc4e14d4467c99227427e3abb8d3dcc406f3704a7783d822ec1118a1d91d5945d5b902a2ad325bcc9c17c68ddf8b5323df9c2bde392710d
+
+Msg = 68e27cc72fec8f3f1f3882c6efa08efdf21d74d13be5171da35ef2855666ad2ea6919d21dbc1cb6d296663dcbceeba2fe47a2c6507d3d4a67a61b55b0f81c93412d7e1fbe15a590e342a05f55daa55f8591171303154e615e81189a523b855829a5c96621ad118f522e397e2eea05c2603eeae6e3591215e29b2289bc384d8d4
+d = 04b4e04281b210fe78d516a5b69f878b7fa058941ee9ae8cc63b061d1eb9e12c3e0ecb8717ff4623ff5bbbcdb53c48adbd9c69636506ab929c5507d7ebafae5654aad65a263e48d
+Qx = 538049d071158c62f0102fb664a47431afe320474a173463819d5f83f6737b43880ed378470d774d32ad59cd9d75e5bb06b118f1297af3f6fa910f40aaffe11e46cd56cbd29aa51
+Qy = 0a4a843af9841e2427357bdf26817656637bf4650e443ef303dd458ed092dca3cacf2857d10aa190c256467ff834bc804f8557f6c3bdde89927a5f2bd55bb9d9f1f08a044cbc208
+k = 1191110485f56335f0e65fe04b9ad8fac1c3573cb4690db3e9f62086312d394b0e354890c0f74e3df7c43e718ecf18caf6904e03bd6c0912f906de1d2bb4c49823bc6c0dbfe37f4
+R = 0dff371ac365cb7de248ddb2b2fdee624c527c6c1908dd287a294bb43a4be94c130bfa83710b0655f21695dd91703acca64fe2e7927eaf9c2b9b230de8002798224f9505379bf34
+S = 2f30f31c863bdd68fae16f97fba756e033eada18cb0a23d7d4b2c9ea3c832e61b52185fcd654d9eb281b92a9b102c3b17ebf02422a0e4a7a56a73974208371ef65434c38f4d7d1d
+
+[B-571,SHA-384]
+
+Msg = e67cecedf35058b80787589514a9c81c6b9f4bced4260411d2af75bc46b8b2c962dc9d260dc99ebbf8ee64950766efc0e394184bdc8e2891d66bd3300ecc880e9d6a3d0eb615322378afc3dba89938704e9a8d0c949d4bae9838805c00377e3fe5ec6a1a98ad7eaaba6b500973dac48b26b7fb2e1b9889f8c387de535d4b2363
+d = 30f2849a713aeac95fde5ce3af853e9d070ee60709eccf35a076567be2c43f0fa34420b0fc097ff577221275a3a56e759efc32183be2d76058a7d20e5dd59f00415114d73a15b8f
+Qx = 6d4ed3cf180e0e307745faa49247f269c3fa0a69042b3b78ad645f43eaa50d479622e27429a6b6b1889944f85975fec8018d3321ed38f6c7d91f2efc98467a027ba4a02c7f231b4
+Qy = 5f2ebf6abf7d53fa32865a9b6ada9bee51c1fe26cad74dd6ef78f13872f340d64170031becb5073001fbca373be4e32ac3425d705ee942e6c4e639bf72379e34776680a387a0c6d
+k = 0da9d8647d0950f558a3831b47858168b3379656e603f2bd44046ac7546892d1a7318c5a9873c6ff85683edd3881a0f1af5501d17939f0825ed37bfc9a2d95faf43d3be92b237ef
+R = 0fc7eaeef74806606fe51882c6928a06bf552d18dcc4d326d44a540abb728146657048b20e5fe2868beb5f04f32d43e9ac23a7f22c6bf325bca24f5e3161c868911ee61baa8a3c6
+S = 33d63693268f3762635373fc901fd72e525965ac17e2cc009177f03bd3524107b30e4c6d80bbc4f87fb1f288ed56812994541fe063f1d91afa7213bed8be5693dc6c17ec9a0714f
+
+Msg = 2baa1ac3f07e34b67b6af087400f261e138b070c8475378063286c16fa73578303380236a4af2484ea01ba56c1c619f6ae4e5e6ac2594c8e5aae7e7f196f96fc5d0f507bebedd4d818e77b9120e5b4bc01c7ab6339e88b71d0886631cc7fd89659bf513faf149c61eb14d55060c8dfc7e6e4c2b4ec8edaaa6bc36eca50a6feef
+d = 2ebb73d04e6e5361e20629e3ad119b33db5163ed91fd9a8aec4b774898784b6822a08992118a8fe6013094bad0be1e9bf01b27c069e4335bff7e0abd28a10443818f6b825e9cef1
+Qx = 01710eb0167e8c948d381e3a75aa1e036b70c414f69260aab434ee20b6724dd7393fc487b5b3822e5e8065b06d0785a4a7be7193352d5b9eee66755ba106ba6e40f98a08c730a0c
+Qy = 6006f98fc25a641a7c6e67fedd37aaad77a9102be3e1e7d32dcb4c68029e623a42f4ca7d1ea725bfd475756b80e18904107c460fc03b9bd68aa46f9dfbd60618670c4d9a68a3287
+k = 1861e2a356a6fa8096418cde7fa17f1b893a7b63810f3fd807a82bf4c745aafdc4963eb7a0ad0488a776e915b64d2b684e46d244703eb63b77835167908f2d6b06a2ed7b53f0717
+R = 046688e12d26cd96bb05d3f418d8ec34f4426f594acd2bfd8e9abd79405e612d60737007440424bc4f546c54b7402d11880f68edd996f49277b729450f7dda5d05986b014b5244f
+S = 341a80e74f3a69b966ef81ae95dbdd60ed5a0446416653c4df431ff7c4b4272665a523379d76725e9fbe196018f0e747100084c823b95d7c7b1785d3623e52e9adbe773b81b49d3
+
+Msg = 0e640581f573068d8ebd2899a6aaeed0bf987ee11e22b05d25e88e9a1c3451f45ee3800d976f4603c18a041febef07a01086832a6f7ecd5d498d52e796a9d90758c87c36f4a5b704a39c456aaee2d5278183d5815d619c193da9fbc427d701bab0874bded848cb4bb066f56e119b637c78aeb6eaa387c41bec6cdd4bf7b2061a
+d = 1bfab717d6f6e16d9bc6e89d2ffac7cbe0f808cc8ca2eb515af7ecce5f3b230303775710a21bd25c2cc4566bb53c78c78e3774a9f306c751cc6e149929e45eef60f56c1d2388c6d
+Qx = 6935c3e8b58f7bacd045e745054c227687800ddd86d6e0c8b1e426f4df0e4b71feedefa9172c43becebbeee8ee382a75396fc5f29ef3d2cc55f8afa9232038609b5034513b222cf
+Qy = 138463efe3b32259dd90b759062f848deda84f2bcc0d687c410f1ad2dd745517c96c3451432b1e490902208cabb68bb872ec493eabdf1f3b07595d23a54c53e512777abffb7fc65
+k = 00025bd48e2dbbf1ed8bd9c1514303dc503dd0799c7815870b902249cd1d7368380853d36f7fdefad973700ded1e0d66950181b0aeac73eb622c880571315f09504ed26e28e85a1
+R = 1b9d6ccb19b208022d3a579a66957429682517e84a71be42fd571fbbd0247609d0b5b33808189efb52d21e6421d3b08821d82900577791b1c54e239b0d908bfbcdc060cfedaefb2
+S = 3356320389ffde577496c5b46a0de6d53005f5ae3489c0d292c5f460a3b7adc5bd204bc50a3bcc8538e0f8319c79b9024b065223b7ed9b0f211c5c224d363f5bdfe04db97f99e19
+
+Msg = 51a2a560ba226d629127ce1ea7e812219ceaddd23561256331458c9f11fe73990f21d0dcd974a3773040090cfdc8e0f01692d951a0cbb60f8448a016c67abf46a9c150466ac77e656ea827b0ea7d1e77ea32071ba8314fc8a2edf69008f498bd1c18061d7d00f3340a7e2cd73e9766862378d8702e804a1870b442beb2d0aa14
+d = 00cc53bf7f1cad5e3dede4b4f4b082831604c92dd2b147869cdf1107259305b1d50359647f9f3d7d4e1e608865c65dc7c9ea46bc324dcb8423b554dc369d621743cbfb592b70eb5
+Qx = 20187d7de90652caf1210703ef65cada3b88f978e14ce6055847be7127602ba7a5391cef0fc9b009134105da7b09b49beb7ba2f961b84e6d66bd818ea99ec106c6e8428b17394a6
+Qy = 197aef36e47b571ccc0b41f948392d6061060063137d8c3b999ae507b76132fea1563775be555616cb5816b9b19e42b34f9673aab833f4beb9d1a0848a4bbf2f6f44cd03982748c
+k = 08acd0f8f9660d21d62f391112908be73a4342767328d3375a8806dffd2598b6d77fcb4793e69f2390389a78c2b11866cf0f03666a60ad088d2c77bbc49fff6efc5b7283d02bf36
+R = 1004bfb78dc0e4fc0f2624bec6893d717a476fc76bb5c1d94c1dbf157aab5d1dc80f98a3aeabaac94d9cf9e26e1dd172f5d8fcd5b2d48cb3b7f0a4863813357b5cf8eae84478e44
+S = 30b1c8857977181d12c53cc2efc53a427801cde2890cf2ea2c99c6958b6869d0ac78ee2c846c241362c885835af49c47d20c30f3cbfab27d9cfeaa6d858694bab059229e30bf845
+
+Msg = 90eeecff0a2e37df318c441df220dfea013ef29774ee92a56b213e13a798858f31e52b6ccb7599e7314f12b48a89884b113c1ba0526a54f3e9a33c940944319e084bff320cf5f391c02c731c4c4f8b05afa273374a1705d6c85337782ba7d36b9c00767180cad6422c11c581672ff631fa4c49d41b02481568ec87ea97220400
+d = 2b009530cb9d586e35dd8951ccb686833afb7a37ec253e547e85b253ba999f0f186b6d4ba41091615fe57678e9801b4dc94fa683511da25637b2acc9fe60936be15af16234c4ee7
+Qx = 5913ab6a2287d946b5b6d1e6c3d64117e085da7cf6388e333cf58d22494f4b067c684dca770ddbcea5db73f048b296e9c17284a8912b3cb722d9eaa17b6b1209311fb8e8757cbf5
+Qy = 007124ac6c48ac56746563db247bcfe6b20215ccc5cfb1d43c923daa07d429c8f0513bd1ff1180ef0f7927fa23fda1af25d20b22c935c426f9ccb402c358b57b812516c43111779
+k = 27a80a19e9c320b57146845fcf97d6debcffbcae877c33c62aec62a3351ef40bd90ef4c2ca39f9e51086931d82eec4ee7870365cb14e9c54ae735069801ef12c571bf1c7c1cf6e6
+R = 1de22c8984c593a0948164e6cc8631489133972482f6a7fb1c3c13f97e4584604930d369224850a1d24f267f41bc6fca04ad79326aef61f0d429e0e1b9e9d9686ee10f2bc52b104
+S = 085c6b34687081e280a180cd0c4ffe95cebbb0ad6d3b20a7341e467812f88c23973701cbf3cd2bcd2811415d0bf0cd9df229a88754f4cb0c225a2d11f57369a29edfd7b04639055
+
+Msg = d3740cad41e2e365d80ae81da97fdf06d8b6c278b505e34cb683fb55ddc5189da543540914c0accd405dbf0063f6222885fda4b316dad4a83fd03e8d7b7e936f87fc0a5b095defc8a4b22fa97f00b394e672d5efd3e0a230c7e44dfeebda88641143502a400ed62e2a51f9561e5d652a43d616f16699e875deb9610c77de8e1c
+d = 2cc2d0d7189cc8fb3565a039aee7633ddc00ff427cafad32fd2010b10fe249c9724d91785e7080203626038109158e3a61a3970aa3e51688aa7f5184b22f63af63f80d3540ec023
+Qx = 5fe95a030efac2e5d9522680da58606e3e7544a317a3f24d726b69238367d30fa586864d8c143c3695126ce8dffbc7e7fb789f956dbf53aabbc38af988ce50f1fb30294ea3e2d48
+Qy = 193d1e745d82781ae5c3b3d2233e502959d6862fa7987c6416584504f65639ca765578378b75d3844df179cefdeccff3c4c43aeb8865063e176fd43a27c93e329f8d4f6fd5bad21
+k = 02df3920fe4d328315353ff11b0264045248b32f48e860dc59d931ad65f39e97e3a683c7b5c64b21c3fa50a9685fa11f49df9b14ddaae03eb02754b01e03f60fc6aef1e5d6d7d3c
+R = 1b91c4217b1580cfab56812c16bb5aefc1534ee8d049aa2e1d52a5bfc11519ff89f0d36ea2bfdfce8b5d3cf1527dcf700c0208a70595e9ebe4feafd0eb597e05df54212fd6eca3e
+S = 21ce52440267fb16e713eabb8bf2d502c81939799f9d09cf48a50dce5da999f3b457dcd73c212d5d070056b1f373b07ad06e90d96febb7f8cdb4c423ef946f0799c038a3ee68ff4
+
+Msg = 5eb53b5f92121396c5ff30e0c92da48db4fbbdbf27297f9bc82614ab78f7fd863e34096c615a02e349d8bc7ae4b0700130704bedf32756b5ee6af10da1cd717d624fadc57a9aa6db4a6c5d6254c0e8f8c3c0d4d03c264eeeafd52cac2c1968d9d85b106167a49d0ccdbefb20bdc10a2555f8149203af52853169a02db94e5e2a
+d = 3d8936c00c131e38c6566d2464c4e207c878070bbf681695a6cd98cab2c6e80fe98cda80c66a5cf584e90a071144dda59c07b8fc7bb42464dbee5b6f739b0f2ee5fdff7e5a4e7cf
+Qx = 0fc3a8a320e816305772bd5116cec2795d58633a9f490be8a1a360f21d2aebed6038ca4a5081288b6bdb1066307c26897ce38c24f8ccc98a63e371ff6b54f6016917b430c267af7
+Qy = 69719c868d8fd25a38a7338811904e3330a7b2289a8384bf24f6dad5312160f0093bf556fa061ca5e52d6676a8f1a3e4656740c82d3cddf0ac4f903ea885d42610bf1b45d9e57a1
+k = 050da632cd7aa58340adeb20389a2cb9897b8ec944c47e7177da65d9386a9dec5d63be7bb2d0f5b4943932e1fd7d87d5d7a80bc50a63dfd101a6a28005c894c6a6fa4c652dc519c
+R = 0e6152b9050127bf306662f6beee81d024492b91efe87a56e70596a4a72cd02dd2f10b970c9a69909f85bf4783dcd3c32505d7c148166ab43b503ab098b6d95ef09a7932359f60e
+S = 1f7d68d53ba161b61eeb17139eeae1587a6bd148e288c1f73a6bfb3a0d1f6dd8f9cdc27fa9e8c7a681410500c097ad01f320303421f1239b4a9c4d5446562b5b3cb2fc45a6fe239
+
+Msg = 5aced64f702a57ed7fabd045a40c967a485d2a70b0a5e82561d5141ef329469b2da5964a34df203a980111a77adca376c643b9030aa74516f054648c1534d912ea66582adf3c655dbd71ca55e47412315df5e2893e43b2e2dfe6e4dedf426f11846ebef34a99f5615460ce0475f7bc54b4a4fd99e83c982097c3136ac6188a5c
+d = 3dc7de970bce28a943d7599f2a9010fc99435b93bc4ba884d42503ac2941aa63fd07db34bcbb1127d56d6a4e277d6ca32051ea3467e376f74f98c3999d2f276b282ef8a28cf0cbc
+Qx = 2066a50b9f961a58620f473fcf7d5eb635da47f4ce362f428669ea578d50d1c1513c145adcc03ba98f3d67bb422141c73e2f94ef9559ccfdc0be20eb206d3d114a5db302bd0751f
+Qy = 4437e655bd255e7f013d197210bed70c5c1a6cc1daccb96145c9c438c8a44b4074629830d8df9914166c9378b33040d71918cdd0f47fa64b7c69f43eee0f34414b8f64882f90ac3
+k = 3b2e20f4e258b7f0cf69a460fece9b4794a12a37c0f8e7aa6f4f51dbfaf508f6f1e0160ab4388891efb09f0ca1f73178f0e8598750c9debd3ff856cb3a2872762ef9e16487a9513
+R = 2f265aa99ff806ffeacbf9ef7be575ce5300d3cfd4225b1835774ee075d7e530c9fdcd681584223f84a497119b4eb1fe34cd31d654c2fa262d7549acc251cece9530b26cfa3ab35
+S = 2c05ce4b35544bd1f20a68eae7f3483e0a0628dbb53f0466166257f69a7a110d2838a76d204e7a955a8977508e65f2ef6d7deee13e4e2ec0f2b9a8b4bedc26b3502813b0334a1b0
+
+Msg = 43c24aea343d4e088bea25be69a332c631275c36677093e057de69cc83a4c5e70ab270e5a8930f55846f1a22ec10e03007dcf0942c6761e89c65c6a4f032eed97dc3a2c7f7ed1e82552fe48828a132ba16c41f6bd82a49335428a24fa1679522000e6a1d12c646e0e4b4c584398577ea9493bb334fa3cee8bfdb6c2e66f46436
+d = 2de6ee12eefa7a4a736484b19b42a513dfc059a060976edc3b0aa4b50e98d72df6506fed0499ff8480986748e938289e54a5e86c0c29733a9bcf5985aa63d8a2b57933a04a8e8e0
+Qx = 073fa1b62d469f2991d54f1472b60da87ba51be0a9dea361d417b91a4a75373695e9f27b3c672322315d7b566b1f22b96c54adce3e958080fa8a02836955f6264dad3a87fd11f06
+Qy = 452c0a07ff65fff741c96851657a5afc7eeca239622e1260414ed736a04e487157c52da98a7845bcf6f311e0f2e59bb92248b6d47dcb93da6f7e0af644b7aec7603a01950293d8c
+k = 1c87653066057636f9a98a7c69a84e103df480a92739abc4d5ba53891591e3aaaef6ef3ef5e89213abbf71af9c84d3b30898580e782f557a03694446492afb05ab801d7dd631c8c
+R = 086d539546c61e82d74319f0180411172acaf08b5296dc6435d4ed7bd50cf23d3a071deb3be01f74408e64ad244f069cd41227ba127145df5a357489f944b61606ec75e8377db81
+S = 0a34d9975fbd601614d04aa41506b03fc15189ee8102c0431272d691a322f3e77bcfd19d8bddd19b307012b6c6349f5ecf88b5a69e83588b0e18096117f207304b38c16a9a8592b
+
+Msg = e89210565959d93b483659e62cf41f0a0147ea23890c2f1a694c377a826165e363860e4b084016cda878a43eb68465f81f397ecd50087a25215ce7c4ededa3552218071fa3acd7ae380655fc8fa884998209ffc8a2c26f1ca19dfcfee455dad35a4e72caecd8da47eb9ee21b889162f5d3032724abfd1a31e68612e18bfa9006
+d = 05468f0df2c9854f5f655743e79c750fd8812db28b096d97207bae7f5aafc6b6090c9c636ead9e0fde32a1ff8d539b53813733ca812b41b58ff85a941abe4f128d59fdf9847baa4
+Qx = 6591750fbc104f82c213fe88aa620e8a960fd6140598e2e6282e0d5c5ecffd09d22ed94166109561a7f4f694e171189056d8b300b54c8134485500effc7123aaa23862e89791242
+Qy = 05bf8ec10a9ac6a92c54e7fb2135e2aa4f84da571d33227bde0aa2e6c1532074882235f3103d9a51e80b7a9a19067f35047ddc52462db7c634c291e8fc5eb2154f6913bd0846b88
+k = 242308c430de514be1b9084a7e6c96894cd5615a7c71ea22316e539986e9702080ff6ceef2980144c55d9749830c20c9ea90b93dfcdd28fd862b6a15748dbb3d982e4a275129c75
+R = 361e1b7a0f981bcc65480b370c5e09b1c2e2a67cf41646f6a3d829f663c09115892237400317601fcee78a04269411d267dad3e8fc6f069529fbdf0bcf9b5f13c9c6de1681e8b0a
+S = 2620c29f86cbf698cca5f79de364ae131345a802c0cccfaefdd7375dcc9ba6ccac91f70943eb606506e51e2ced50491eb8f48769810b6dc178d56702838f1c2f0930f2a9e4f1db6
+
+Msg = 48629ec97f56273599cd9903f8a84ac2ba74275b40e1e42fa47649568babe05cf63c8417d828251acc2eec525b56dc9082b68d51b0c2bbaa7389fbee15d058cf482993b2bedc5a9101f1afdc79989a812478245d191550109fc17215679553c508c84e3d4cfdea377088d09eb214e6f92410facee4790beeecafe72b2e3ed192
+d = 3d3c6a7ab9450c94aa3b8a1ffb678e5b647af24cbfd66ee3944e6f264f406295b803767471fc67936fdfed1714b4b8761a07eec86543b7c4da6bd2fcb33fa8cda4077737f398e18
+Qx = 42d536f1b15a22f4ba80066798d8d1c2704988eeb9423319c1850a1ae6bba4097307b515640ed3112e93f1f6ae67c60a4b0d2b6634aa7038a60b52b2b447fd1651857b71711c975
+Qy = 79eb18cc7493a1c7f2f9b621969b9ce9ee37fc0701f6cf56f5d5dc6efb13a384517a387f253aae1e93bb0a919b0c22e4d6cbc79b449b268a068b7eb2853324b96715d75b8c26f27
+k = 23ce112d60a2f7c29d77d64acd9f587e0eb75ef8e739b8548e154681efc24243594eef5e33d845b1e4e89bac56f2e9586e042e0fff38bcf79c73fc9aa5fc908261df5cd2c6cb821
+R = 3a770df8a2bc35e122c1bd551c38400be47f2499ff57618ccd01e14a2e35e87a67b0e40f9a10eee7efcc3d37b474f2840fb8c24a9adf93734680ae6b25818369c8608a2f8f338f1
+S = 0728a4eae5f5638a51579e224a24ecd4c997001bb8681e23a7476fbf78b4fab84497000f20c1e67e8a4e4116498bcee49ff00026009af31c1037172188aacd264fde8db15c97167
+
+Msg = aa3a9fe467b1ca638dd0622c9ea235a418b39b2e15ad81fee01b6892b240783d8db3c72e16c13df8016dac6addbfb85232158325bd7432fca3b8bf5db3abd0b4c5ccd0999609dc42199ca4680692a0805cdd68108bcb493a558ab507cec0a2782a9e976928985352edb2abc0c07078b59d2fd86fda7fc76cfe573181d934c46c
+d = 01ce010ea8e6e1a0c26ab22eb90f0700dc73b232c429d36371e68e429792afb7223f10327708bcff779ea55fb5f22ad87aa054e84d10f5450f1bc9a89279062ea2173f55ab0f76c
+Qx = 4b2b5acef5921e691f10ade81b91ba8e68e73b33a2494cf4ca6617707861f334eb07ca96dfd681dd63f78102f8d792d66102117b739d477e431d9a3efd79bfcc18cea156db58a0e
+Qy = 7e421337d4cb7a98cf9c9c6fdf9fa242904d9906d8a6759ef64a82cbf923b2a57073ea0eabd14aa4295bec84d50a1722fecad3e5f064bd3171facdfff45b170e49f185a3c193f2a
+k = 326b62065b7c779dc398ee03a8332cfb940b0f24a7d3de4a90323d9e390ad3fb1f0036abf6f525d8d88ab6641302d10db447b78780d366f32ce36ae571e323124b21984c48aea7d
+R = 3d2b207b428829ed5100a92f7276e16978e374c734834b0d627cddf6aff5cab72dafefc6c038a91426e35ee0f2c1acc11c55a34a89874100b89588aba7b02e19490e66eb49ef6ed
+S = 3259fef5c2a0779ae408b26e6c7d581fa973156cdb07c329dde0c12b6c498e7a94577719865b7fcc0db078ba72a27bf338ec6b8aa41c15963538c329c55dee67833faebe3b643ad
+
+Msg = 6c3937014361799f1461f652841b5137eb0dcaf01dd293298d002f27e9a770b9e1a30367e35c04603881f0c814cf8ecfbe1619cc49cd516b1d60d27de37ed52a5e1cc300e2face4669f308ebe6747255a3d386f16778e494a7cdd10b45171b2bfcdabd91b805bf24857708c1b75e368edb2874321324f83a19154d3a1578c767
+d = 1e7410d012aeef02b3723346d24ebafd684c99087ecccaea1cf3735d52c4c81dda41812c09f1e874dc964d858ca240a19963d5dc89451f5dd6764426ae41cb23f19cbfdca0fc562
+Qx = 400a3bb3ff07a339ff98f7c45fe032cf42c0e25de8dee2934ce42dfb0c9894f4fce27fef299b41beb8579270efc7b01c0663c3f72d7bdd9f6ff5186eca9c42d15faaef8784211a5
+Qy = 06fe998f7a0db06efed050d178865a2b7de6ca7c789cedff7f2158a5e07ac1d335ec0dbd213fc9465399028fad8b7f4d2cd16fb8ceae4d3d53abefd2b4037efd7f7245296bfdf9d
+k = 2bb0fb9c428e42482d5dbdb35157ad0fa713fe732dac8604c0194e3f9738fac5cf3874bd863718712a3da45b7c4612c8685465ecaec0930d9fec32ab25818d2f25fad580009b698
+R = 1062386d3e77043298eb88be46bd4e6f33c83a7358926b30ca06a6b7139815f6e1630f73d352a2cb9bc0619d08a89d4bde1636c74b6580543ed743073eec2ae0037bea2b3c9228e
+S = 1ceef759d804ff7de526559636d0bc7930c096c7b959f04f8fec5d7e96129fba14c8341b0ed84a64c6cce7cd5b058fab7f44dcf3e714544c9b6f9c1d46ce512870deb51856e9dec
+
+Msg = 12fea55ffda15db902aa6a4388b9807c89c193cbf75b5d2a4c95206fa43dedc45974c80079933451bdc5b3ea015ed3ca2c54156dc61afb1bc82adefed1491302a48b9d3d2f474ab45343c611677d360515b93fb36da7a1c1b2341c9cce185c881c0beef33d43967134a190c09034ae3261f3295b79aebd3fe123616f73cf2089
+d = 2139839ce38eb879d266065dde5e5ea227244323b330e3ad5a0bc690f3c210f794cf18f0d730693887548bfbc434f48ee10ed34cb41d52172b06e448df938170a5e17311cab8e88
+Qx = 2ecf46b90616b534ea25cc9993942fd7576a1c4f2f443d3b1f56d4490bf0af669c9eb9d110fe2a65609875e1a924bc4b9ed2ed2315047bbaeadaa1029b38a7a87dd8751d4128e80
+Qy = 2aec3a2f2557c7152a4907af68aa39485274f20927b2da70823440fbd09cbc308d46e30bd6b705f615b7074fe5421ca36b4aa53861983eceae9a69649495952e75b0f060b5d26e4
+k = 2e3412b61eb23d33ca2910dc25dd14c04d2c8b403d8077a72b9511d71ee9da6d7e1db093b92287f8fb00aea0576f6712c56d80cc4e3554e0faa9c7d911e3d17682de831bf649bd9
+R = 06a3075efec81a86175cd1dc2bfe82e83aff1db640184a6a3ed7a0dcdef51aa0be0005c54ac05f9b65af265af7f2ec3d1d7c137184b0d695d701ff1aed194faf2efa98ce6c5e502
+S = 237d7ff92480fa7d6d1f5a0564a2608afe5e95ce2c29dd88853d1ad9d4d2beb8d1f0423edb883faadd592394f52048bf2dc26d2dc19279477ed86621c7a5960ee3c3e2d345fda29
+
+Msg = c8395546842ddb545d8ea3db4efe970453dcb06025ac3b7a25aa5ef62070f3021b9a1fea91ff7055b6c398073e7886a6f71afe53c82c47b71377dfe291972503bbeb25bd477bf0e7adc8a5d3f8b34ccd0080d61e121214e1b29802b711cdd8a6bb2275a2395c467ec2c1571952992e448d736d8bd70ee629c75b5e32b8323a00
+d = 274f70fe69e4dbb55c5d404e39f5196335047113087f8711f2f67f2be4964e4fbcb865680758df1c401cd677b0971654b7a6aeb7bee0d6d80ac0de14d4f46f356b2d5545c185aa6
+Qx = 2b2321e0a1df083919628dd8b4c318b9ded8a3e660ce5585b21e46843228b4d32da765a3776c181654aad0ce90724bf85b01b051d236342b48d41a1dbda1e9904d659c98a039a97
+Qy = 20227182fcf099d46d9882c0b0f26b0595a2a3166248898df2f3fd27c78e7c0b8b59ef0ed6745660c0dea1acb567f9d943928864dd1e94f8eb6b5b8473c0c91485643189cf679d2
+k = 2f234066c936625fca10dd080cbbb1228c4d2054cbdeafc8a0a248c0d22807fc92c661b4f69586ecf9469bc4c22895cc73ecf492fb2165a12b027194d409677e7185de24f6870a3
+R = 3a48daa8e379b3b2f377049a4d462530c9ea67019752f4af4b4192b02d6e028386dcb9ef95c8019e90e09dfc8dff5e6f6812df491906ced39befedf16caef614d8c174e7ea95fc1
+S = 33f18738cb26d88c8c048c58a210c7be70c71636dc62c022df1bd7747d8c67bfcf5ff2fb3990ed35becf6c77755ac62aed480df55efea578671bd8d50536a10e2c0192bd42d78e2
+
+[B-571,SHA-512]
+
+Msg = 10d2e00ae57176c79cdfc746c0c887abe799ee445b151b008e3d9f81eb69be40298ddf37b5c45a9b6e5ff83785d8c140cf11e6a4c3879a2845796872363da24b10f1f8d9cc48f8af20681dceb60dd62095d6d3b1779a4a805de3d74e38983b24c0748618e2f92ef7cac257ff4bd1f41113f2891eb13c47930e69ddbe91f270fb
+d = 03e1b03ffca4399d5b439fac8f87a5cb06930f00d304193d7daf83d5947d0c1e293f74aef8e56849f16147133c37a6b3d1b1883e5d61d6b871ea036c5291d9a74541f28878cb986
+Qx = 3b236fc135d849d50140fdaae1045e6ae35ef61091e98f5059b30eb16acdd0deb2bc0d3544bc3a666e0014e50030134fe5466a9e4d3911ed580e28851f3747c0010888e819d3d1f
+Qy = 3a8b6627a587d289032bd76374d16771188d7ff281c39542c8977f6872fa932e5daa14e13792dea9ffe8e9f68d6b525ec99b81a5a60cfb0590cc6f297cfff8d7ba1a8bb81fe2e16
+k = 2e56a94cfbbcd293e242f0c2a2e9df289a9480e6ba52e0f00fa19bcf2a7769bd155e6b79ddbd6a8646b0e69c8baea27f8034a18796e8eb4fe6e0e2358c383521d9375d2b6b437f9
+R = 2eb1c5c1fc93cf3c8babed12c031cf1504e094174fd335104cbe4a2abd210b5a14b1c3a455579f1ed0517c31822340e4dd3c1f967e1b4b9d071a1072afc1a199f8c548cd449a634
+S = 22f97bb48641235826cf4e597fa8de849402d6bd6114ad2d7fbcf53a08247e5ee921f1bd5994dffee36eedff5592bb93b8bb148214da3b7baebffbd96b4f86c55b3f6bbac142442
+
+Msg = b61a0849a28672cb536fcf61ea2eb389d02ff7a09aa391744cae6597bd56703c40c50ca2dee5f7ee796acfd47322f03d8dbe4d99dc8eec588b4e5467f123075b2d74b2a0b0bbfd3ac5487a905fad6d6ac1421c2e564c0cf15e1f0f10bc31c249b7b46edd2462a55f85560d99bde9d5b06b97817d1dbe0a67c701d6e6e7878272
+d = 2e09ffd8b434bb7f67d1d3ccf482164f1653c6e4ec64dec2517aa21b7a93b2b21ea1eebb54734882f29303e489f02e3b741a87287e2dcdf3858eb6d2ec668f8b5b26f442ce513a2
+Qx = 36f1be8738dd7dae4486b86a08fe90424f3673e76b10e739442e15f3bfafaf841842ac98e490521b7e7bb94c127529f6ec6a42cc6f06fc80606f1210fe020ff508148f93301c9d3
+Qy = 4d39666ebe99fe214336ad440d776c88eb916f2f4a3433548b87d2aebed840b424d15c8341b4a0a657bf6a234d4fe78631c8e07ac1f4dc7474cd6b4545d536b7b17c160db4562d9
+k = 378e7801566d7b77db7a474717ab2195b02957cc264a9449d4126a7cc574728ed5a4769abd5dde987ca66cfe3d45b5fc52ffd266acb8a8bb3fcb4b60f7febbf48aebe33bd3efbdd
+R = 3d8105f87fe3166046c08e80a28acc98a80b8b7a729623053c2a9e80afd06756edfe09bdcf3035f6829ede041b745955d219dc5d30ddd8b37f6ba0f6d2857504cdc68a1ed812a10
+S = 34db9998dc53527114518a7ce3783d674ca8cced823fa05e2942e7a0a20b3cc583dcd930c43f9b93079c5ee18a1f5a66e7c3527c18610f9b47a4da7e245ef803e0662e4d2ad721c
+
+Msg = ba6be551bc60653192401ed8ff9e1acd9013d8811a7a1389528bf07438366f5772cd7aedad010c19c47622cec03a4d35b8003b39ed901b720629ab59de55a03c1ca50a62987f8da159e356245df58d5ae1936e65f3cd3acbe03ad1d0fcab4aaf2a7a947549ae776772201efbc6fab1aebfa1d99994d4f43dc28f39c0f279b992
+d = 2a69bc1df069c6e89722521a63675f318252be629e7558f3716917998e660ac960b0b750562846fe6c12ef492951e51e224754bab84a6eacd4147a5f26ae85ee4381bb14ec2a8c7
+Qx = 4685c0358ca31883cdfd7d609afa8b1e47540a97f473e0ebe98b0aaaab9418877aeead3a26fb01a4725fda20e7223a4fe7de0df6891c0812555b8b146918d3b80edd11615d95b77
+Qy = 67c92736447946c7577965b613e18950d813a4df049a6000895f9dac34d73ea46a83c6a4e7c83831af0d33026825664c44090953521175b9da2a7ac563a0fc5e13c85d34aaf49f2
+k = 1700d9ac00a987ff3a1d0be4290979317fe60f4f8ce1e0e72a026fc89e28c0070b76ada14f7a1a66ac2e8aef17eec18b568ada4fd59c05414e55356fc17d9e5079e6cabfc1f220d
+R = 23a279662efec48f6cf8c7334862525b52ac37a9b03da6a063da2849f87801563242783434fca02fa23e32249666ddc6f596e07750ed21de303f4f10de56f1d37101cb0826bb8bf
+S = 3b449467b150cba0d7c2b44280c5ac452f1217384ce121c979625d313394f6cef501b81980a02567ca55da2bc313dc0754b5256b08d8e3b63ea033253b205cc5dcb014574b8e9a0
+
+Msg = 295720a79ac8201f40a66b06ae5d970afb15f36582897eed25cd92edcd00f70ac8e31c556eed4375ea044c2e8b227a8e02c0a3e996c9272d52ac7b3ad43b80f217295dddc84b177cf1e800ad08bf7fdd021fb2f49b54162092f8d628679c4ee335abbc90c027264c8b288c6e16eca3172eaa297ba50626b00fe0a0ad3a9dbeeb
+d = 0d11ed1b78b22b3420df4ddc4acc7c2286d9569dd6dd88e0fa3ecae69bcced68bb81bbb4ca6e9b54e67856e7fdf39155aa27aecb9cc827ccb9cdcf9ac633561b27d8eebfc261aee
+Qx = 1868a1335058a69e3ce24ea4e6e8dc25851777bb28d3a5da67b741ec9c46e26f2d2ae70a48c3e4feabb3b15b3c3ebd561f667ef3b95a587621de6073b9c8a904755566c5f7a3b42
+Qy = 6365a03c3f3066eca1af17bbbd08cd52e89f8095075b415cd4b82f3364cbff008fe3642fe71e8a8c634ad0e5d9979251e6cedd42cb97c2203f743210051f5ee1b70c861d2a72c00
+k = 075e49d2ff6f2aa8b44fad90446474ee0e72323a3c39e731b6c2b075cce0cb9d193bc3356f8fdae0e0143603a57028836ee6451cab101a6eb550042cb41b5c4233d3ad3e87034d1
+R = 207a8eed0b87efe65ec558a0ccbecb13b9215e176abd93c1a4803fcae713927ece70ec6c41c621357d78a13a950958871a52621f1de7ab74befd964a0e8f4820b84af3e0811bc67
+S = 2f02017714f54089652e02af36ac5165e44ac4a83747c805a9e003fde4bdb29561dcead2c76b02c195074396a2dcc1b93a256c721716f8eeda8dae443c3eea446118fec3cebc4dc
+
+Msg = a9cff41c6dfdc4a12f31dc375a5455950077ae323d0b7a3d9a8dde73b76e9d7b94ddf9c88ae8e6c262d704052ac47681fc35adfc56c904baaa6e146eb653984369d76a85596cb744941aa7b558c945ff2e81bd5ef7f00ecb4f43af23b4cea3bd4ba7b1899f1868a0c0ecfc62ccb1d588955597ffbbaf34cab2838efc2b866669
+d = 2c36ef754b5bd065e9eadde684750acc52795be80f54dd3d7a7d743d968a18f7e404bd71f8a76eb0395f396df5a7c2ff7e0ab6de35df34282fda6ee01fe5b9b68ecb4e378dbe32e
+Qx = 4805e1a23b6eadcf91647b40903bc1fd3b9921861c942fc24d2c03d0544e7c01f004caeed04b5c4ebbce366a098a878c322cbebe7910bfb0f91b284ac1aef344152fc5831669b79
+Qy = 4f589ddb4da482ba1e9a59241b1dfbc7e9b9b69e8f69f8e90460ad58fdecc48a56842ea6aa0537abec0a605ebfb713e588685a98f62e05a7d52082bfd57e3d68fb7851b37ec5567
+k = 2f2002bdde0c0b0fd92e96abe76c0858e42fd7d94a181c711fc6753572539e18effa8155cde7b1e9ceab2394f9eba874b7ea257d7c308c8ac08500f4944af5f33057650608db8fe
+R = 27f9109799bced42730faecdeea68259383a45033c6d5dc8d87adf994b46beb34177e013700b13f1253cf756a8866218e9c8adc180f3c242c56b3de28405b36940d53c2aab24f1a
+S = 20a762ffb2f5a88b0e1356964fb558b555c424946109d16c7548f41a33cfe41da1f483276a27b188faf948a56670716ddf3b187570c9f514869c4492d7773d6ce453a075f9bc64f
+
+Msg = efa6c582d7fcf5e431aa89b3b00180c0e78efd7ccb0384d90b80e59a115a13e55001d951528c42860132531c9b8ab29dda7a657c53c2ce96fd85549f6f1810e121eb89961295335eaa0e40532d85814a4206e6fffdf9bff76599da9b2e71a22ed572910b0e3bae38ad72c7042579f106739a8628dea5a745168bd918736e488a
+d = 19ffee50be5496507e3ef5c40ee88a49625e46d1dd1686a52b09ad4a8e3ee9ef364f953bfcd97c52104eecb6138067192997cd4ebadaccb73c7b2560879289a46353a756b73cc43
+Qx = 77dca410e722009ef11b37742c2c003ab3015d0ca0328a70d9d41aae04cb64f7746f1c348b08458eb3bb1788f9ffe7d0570a9b689a9b7aca43e05400bace7630d598f5b484d13c4
+Qy = 7291f74cddd9ff69470cf0d92afaaddcc4c8c274d4a7a64fd94292ddc8bf080606795376bb725ab4d32c72ef77dff34cfedd34aff2f463d635bfcd7e1fd002d84383dc5bf8d5d23
+k = 2ea37750fc3bbdeec100694068d55f92fdf35bff9ed49251c4b8bbfb2dec2dd4446999af8848e05c7b819aeb1864430ab4e8c1d684e1cf78947a71b04d5ab8ad61cc7e3e4e24205
+R = 12ff1852eaff37fee997531039adb1fb2f9b4f4199670c022e8534625fff1fa93390ee9bc7204ad2ba3efc2233260943f1d2381a3cc025b78c6d1f660a7bd6f42e5ed3c123055a9
+S = 1b4d8abb28ef1a9d77066921ed50eba64b8433cf00c66b8467269a4a914f568cdb86c766a7a6a52437c5d98cfc9a2130dfaba20f3c2001f31bba7071647d51fb9fbd5fc67ee120f
+
+Msg = 211acebfaf13bba33a9dd16722ec53baab92a140127d61372cbf1850f2fc894e942e25d780778235f880743953d04eca7a9205602e388172aec2abf35412b483490751f93b51239b6701cb0aab14e5179b0d7f55d8586358381dd83e3e436bf69a6820317d1701750cb1fea1293467ba589eec5f5779c2dbf2a9b8f28c4dc239
+d = 3129e96fd28c4198cc5242c1e3531a3979fae643d527044e98d7721aa56b5b4b45dfddfa17a4115e10a2b4f46d92f81cbdd7e86e588a4c6d8c2b3a83f54cebcee1d1dd33e85d81a
+Qx = 73a92abcc991e3f89d82c47fa0fec48e3e7c4d97e2525f8dc2d24da39f616af4a5a804d2603703f6db7cc9324c5b56a21009373f6605f561c8503394e7746e51273b5722ffbc23d
+Qy = 0684c842f03a53a60cce087f4fcdbf23b7a28c48b6b6544f583342a65d97dd87037c6fef176a1f00513713468273494a5be683b68c5e75bc08995fde763bb6f965da1acb7e894f1
+k = 0165e52640fcaf8cbdbfe73cb8058c53045e7670aafb2def28d2c9eceb5ed1634b5339cc47ba981eb6eb03ba714c7717e9ed5acc15c8f304702a0409bd4508015d4626cfc5484b1
+R = 27dcdf16b7156a7a05a752da28b5bd6b233e8a7c16eb7f9030f29c4352e6508f8424d1b5ba789dac4152ac4812ff7975cce69908371a81a4d7d9dd70a8dabebdc4e3af27234f0d0
+S = 32a654a31f09a9803e502a1440c2bcf122780f4f47aa37e15991d9a548583fdca48800804712816b212cd3c657e6bd4cb7443a0288592541473c5086e1277250612c21346538374
+
+Msg = ee592e20e0a45c18089c2e41460e65a7d22ed9714379f095d43a308bdd383128aaa6fb24e9d35fd28fc95c5b792ad75c980d2cdf0f460ac60b12c5919d3cb28dac4d488196be6c2dfe462b1b0ce59f8501692255840f5215c0fd8b74b1996a267a5e3b22d2841cf0a0b6315ef4ec7180f1c8494f4c07d5869c01fa2711739efc
+d = 3d723d2697cd07dd8444f992f2ab4a063db334034c25ea9be99fd7a1f495e3a644e5ea033a41264e0d24a911e55741d0cab80a0bd678eaec2bd1e60424d4491eb86d664900d907e
+Qx = 0c7a229b5fb9fc774c1b6250f3bba2f0972d1aada7080641c014d012db0637a0656a43024ec0ea25ff70012646dc19eeb1033aebcc96a001ba876b2f5def6e198b8d4a53f7c7f4a
+Qy = 09228a68eafaac214fdfa19923a0c19629de31ac0967c9d02c53dbf221f9affb735d3bad732f381f1ca414d70920231a78f742254d895a33ffab492f8e6094a542e77962a324ba4
+k = 3b3724a5933353bb9ff5f742f59385e780caa517a963590b7fc89882bed95cf90ca6365ce8b882f2d96e56bd866a5c437733b681308c570c51ec893ea95fede66c7aaf4561173f7
+R = 2a487c1fc29426e8e85f0a35c177cd168a444959b2f5cd4519b9edd52af3ea829cfe964ac2b59198af8e2d3859ebdf9885ebf57bdf5767da1611d3958de286f91ef397230d65599
+S = 10fc01efcb22b982f992efb71887bc79c3f32a9088bc2011c269924cee0f47c36452399d499f2933587081b872e9fd2191c20cd5cd94927839228ebcf22cf7acdf4608a2fa66310
+
+Msg = fffca41927debbd53455821441d9115db99fb31bfc69752a382f57bc7abe021f148346ee29e17512c64b4918ab2391d12d6e5643bee6b5682885dc28177b292e23a37ff99b359b9cf7578432af56e0ad1028a6cce7428980654c145af8daf09addbb3be11228d3c742defca9d3b1667f48c63091fe3307ecf72667b02e008f24
+d = 1999ab45d66cd1d3a0fe6aa43bf5ef1e2a67637d53674f6fbbfb9b582be91fc42a12cdcad94b50b0fc7ac55030de24a0b99fbc4314fa743ef4b5198bcc5f54d8b669fbed78e2e91
+Qx = 0cbf3b0bb4a2e6c225aa922bea3b233da4661df5da7e0a1cd343a9b6655ee87fc60cd763dee21eaa2b81c4dd5af6f4fadc3ceea643b37a6b17a6501e1b9b689fb0c4716911c1f10
+Qy = 14b5a9ae025f09066fffa6797ddf95f27eeade06b8ca5be5738f770362d5213c46ecfca58e3c60cb2bae1f8ab1bf0577c80b4fdad02819fc174cafb33df64fc0ec79713f7b25209
+k = 253b533d3ad1c7095363e3fc80cb32471061e44dab3f9ae0ea6252f6ef169cee8badd3eccb77096ae9224f89baeee7e183058579680661655fb689419e36a61e8573de5ecb4cd09
+R = 3ba94f7682fb61de725a35caf1d4d799c4b05a1d1c44eb1c251dd8efab6b7d713c3fb917776902a1bb202f9226558f4c1e75964349717e6dff938d0befea07a9ca1bbd429dd6318
+S = 226f43be8e24062180c726b5cb721cc04ffd3acd82183925523ff9e8631aecbec2c224d5a291bb225f0da726d256aa822ee7cc2c7d69df3f2a5beb21132d91bea22e4c5db900cec
+
+Msg = a2f71619ea04f7057e6943c2cece8594b341ec3b96c3915d924f94ba13fd7aaeed41ffa0e842ade414784f1ef825fcf2dbcf7bd8263b802def45f94de596aec0c121fc06558c7bb06b9f27a9bf56c42090b5dc344e82b69c4f528d33be166764a593483f6fda0cf56e6000ff363ba220f5ea0ea2c3191615c7ae3bb4fa575324
+d = 2ce1cae0716205330d730e6bc6dbfb6b951dc83ee3b4a7dae75d057e32e8a46e22be75b5f09135452b29c34dfe81a9be2e8dcd243fbd946a0ed14a832a7802e20cfe1abfd3d6e4b
+Qx = 75971399fa621ce535144ec1d57f544d798a0a59207166c3d657e5a80ac00e8f5b643448e3546064d68ae624aaabf36face3016561a248256ff9131950ab8b04710551e12222d0c
+Qy = 224a50f321647f47de3db4fbe1bf1e3a3dce8a834312779f66037315e3326721e3fd63d4d6ef92b7ba1fa9aeb70f92e2a6701458ac8da49ac386491f2306adcd8dd781fe75e99e1
+k = 0ad95aa69cf9f40e13f8a72ed6d93388168abc8001670ee4d95fb4b726b1f958205ab2f458df8bb9ccf2405680d0e6951abbb922cc11d47cfded93c0efdb70caf0c54e7ae96d7e5
+R = 09ce019161bf29eeaf323933045f59d2efc372904ba50c4a6602b8305234a851d95f06a5b56193ad5d28488102ec25e3f421a5f5c4626b435b423d612e6ab60e0a4fe5d4952e2c5
+S = 04f7b7ac787b361c2bdfa767da9c22152e402184a7ac133f651fdcd928239215dc917401122a6d41e78299b4235e085399e594465b7f8dbfaae9bf302d83470b4295ea06bb9bd1e
+
+Msg = b60415a831eca2cf60c79a334ef2f327a76d290846ee588d5d33d0a826bb0c7ec3e11dbb384a7f89c8d180425dfae7463e0ea6497d2eec1dde112f1c1efccb532a2e2b66a28e2d36d4252a4c3b12850d465fe21bddc441b92e6a7b0f67744f7f6e7812a0603211a26518b311a5b190ed890ad852bed4f6ed13377cab3eebedf4
+d = 2c9d0fcfcee7e75c3245ba955ae04188b1033c55ec9c821d8de7685276bda3e9a93c3ae1b003e5ea722913e7b169d67b1aa2dc8cd42adbd9368672a3f81a6817bf3e5529dcb0c8b
+Qx = 19cba4c8ddadb596d7303331f2a22461849ebfbc78ea69277f72dcfe23d08397025ff6691c61ed9958d68a9c5dd8a32048a89a2553afb9077ec43358763756b1473ab2cd8f25b53
+Qy = 319eeaa78444b7cc5d8cff4e9199ddd2c6dc7bd935a1be1d8b1c657dd5ac49bc92b0cd91304ef44ddb7ecac05518301bfa0e533402043533f99549621e31dcc282a52186478df2b
+k = 385e12170ed0b23c9c65ff7edd413145fd343dd841e85c498fae5f36e57764168899902817d4dc39127010faa1da68000a511ac69f80708be5afe1631432f3bab7aaec2bdeb11b4
+R = 231ef400c6a3a0c7b26ba1b92341b72e138ca62d04ea2172854631c40c48081a18a57e9f055748245d3e83d10d21af39935b0e50c9c86956ac46c1ea03ac4ae023d84b24f830973
+S = 24d37d67afafb0676cd7b5da2960cabfc804b0b3244b5e6739f8fe43d0841693d28c61b8e76181f8aa24940d76fc5ea8ef3a95f72f67303e1ed85ad6e83cd2c44fd0e0f3f2f44f4
+
+Msg = 5d15a08226cc74cf495be681b795d0bde26b19f29aca1a8c6ef77d50271ebdcb4e5fa2df23961fe11620b1c6580183f6ebdceb2c09516c8127be576496fb71449bbbf0a9d3d1c48a25024619b97c3e0d8b165897db96ae9758d13ac28441d7cbfb75b23cb423e0002046358bb6d64779974a5995dfe54b398f95f7d64fc52d96
+d = 10c057bbaa44ef0f565edc288bfe66d4f6acd8686899359bca418ba89fb690429489a37bd3c6c9f3a8714b2ca225868c6a45fee360e378a676f7ea39321790f32a4b005b81dce43
+Qx = 43b1e7d7b2aee3563813a6692f0b4b61ba82b801697c3e23724a2fbab2af80a2c56be55af41def0a90cbfce7a45ec61629906055a8b2a5013740e96859e580c444ae9f0ddf73afe
+Qy = 6742f13244f1bf156d321eab2c3095ca548c3182c405187c3de2fbcb01d0e16e1fef246012c87d4d32378629a75b694572ec8583ae0cc813ac64f10bb05a9e52e4805590482f289
+k = 2b8076102a6448bd4c4e192e93cdb96ea9a6c7f6753818267ee9e67644df1a4a6c9ff64bbe9f64904648cc640fb7f0cce69f9e02878ee950b91ad559a9ec0ae15b676d933f1620f
+R = 1ad97f4997037adfe306f3859d550f9fd89bce8b566e657d5742feb17466b6b8d507d5810a8cbba44d671b043ddb557df084bf5d1de74ef8bbd6a93690459fc16a17b80dd6c0f28
+S = 3262ef6e4175e7afe095d18157f67b3d12564d54954e9964e991c31bcfe1dee7e86b35491ce818400cc0f83b819f478f2f2c2d21c6c7a6be43938841559e09bce70b0d61fe51245
+
+Msg = 9eca4bd88200baf61b901fca53dc1f1e7e3f83b94d58a6cc6a2adbc9b1a35fe3f8ec61787c76ed9a0d696167cd4fe46e1a0883fda564666131753c576a720125e0b712db1da0278067cb899bdb14eec08737e864544663abb1d62f34a2114be07e8e3cf56e2d17099299ce6b6d83b1a34e6153d7c6a32a72c7b1bf4583fcbcf7
+d = 2c182df7976ea93d996f3ba5d2221f3cb755cc7847bc3fe9e022fa4285046f5bfb426bafa3580beea206de36f87593ae561b4b74a03fcd61fbd0e8d6fd5668f2148819a88a650aa
+Qx = 6004b26a184ed710a5fb67e9d042f7fb9c8f5584b1f70a91b0b3be41c3fd2cd1a537e962fdac8756df33f80fce2bb1bc7241d325bfc36dbaef7cf625918d589b6352fa744718910
+Qy = 36a29b04a494abfe809d956c3cd6f84ea51a7fa28cb39a52f16137a13f72f0726a84f6ae53ae24f5b468733f4cbfa0ce5bbbc1cc7b348fb996d33a45ff656a6a7557619f598a6b7
+k = 2ab349232bcb4f4816b26bd0049e130fffc90ca0b9308edd50fb9055358a87fe798d00140b0ae01ed8b1f6bb9bfb726b253c3d4949ce9eecaa6c7fa84d1ef812669fa929f26be0f
+R = 0bbf2f9765b12742224ba7d064358c0305fb63e9b54a831e302a4546aa02cace798d82a188d2f536d78544c1571f481289d6ec69d117648026490e781f1eb9fca59bee05234ba7e
+S = 27e07ee0a1a99c90753cdc8c0291da25a82c116e62ec58b93f91086ac1cc039b35ce7d8b53cdaa92a5ade65a7684b6e7ab79873dce33dcd467c39d0c764ee390b7fb25ca18912c3
+
+Msg = 707450bd84141f3b61beb12ffa5ae89d812dd11badcdf6a88a2d50fc70e23f6d822ff4477047abc58cdfa28f97ad7f4911ae0773c04ebed1f51bb2308cf6e5712c4aaed461edd6987fdd1796aab70198276b601241f6a14225dce575830ff60f935fd9f567d1d210652e4710922fa793da78c8fdc30c273cb08365c9fc887f50
+d = 2d3a65bbe133cc98cf0eb56ee1362195968b4eab960a1d55d8b762f1361fc21348d6f275d4bea1de7158fb97c995e20b92a9c887a3e332d154667ad167acc632eb88a0ead6113a2
+Qx = 34355b54d00c3df7c2762ee2982cb777491aaf78e550c4d2ff5d5a893416eb3517671dbe522b8c553fd71edfe0306cd7628324f4f748091fc5d84ad8af33b896985674649a6f4e5
+Qy = 7e322a04eb600a3faf3e045959f1e9f798e1c965ced40fd4c0383c0d4e79a96bf693a91d7662780990d0c9dfca77a9bc0e13551d2ab35af8a153fa34ea903961fe66996ca053b64
+k = 0a59ac1240bcefc52456486ce23b780cc92c8b89314b8442a6898c373bd0adc3725e3ebac580546d1ec82ebfb2e04c608441d962d759ab5f5af1596c6623487e1347537a3c35bf4
+R = 0c47ef55d93ac36cee537160bbe39c3d4504184188533edfe589a5ab6e5a3e06ef413aa48710d304f0b2bc380fd69a34aa0b8e2e9466fd8a131cb056dffe4b809a59fd83e594483
+S = 2d8de1e8e2a52dd1be08435cda69e673b328573edeb1767849536e6f2d5fc8f18f7bfde936d8c32ecbfa97bf976133d65641320ca1c41e81c388fd6088884bbd89274b1976470fc
+
+Msg = d5ce9d59391cdc47ef942dd2a818d024ae3917deea8a5a4214e4db6a0c5e6b0936f3e632fdb68a3f0006e05c44b7232013e1da5f877cd197f44fd6f60c1fd2378995e9a47534948c5a09e33750f07a7165072ab38095373b07a50bc1391eb6b650ee13acd63d0352e7d9c31695ea1ec6323f9b5f57b426ace56aa7fdbf419be0
+d = 2a920e8dc928acdd56e3655b2340d4371c793e66f67405fb7a90f31e9c4ef466cc44331d1d2fe3ff7391d2576dc6640772166ef8c154a5ff1808f5dab2f03061070ec8b3f786c36
+Qx = 5edc0fb974314e21ad40d73524d5620b7279084e3ecb9e58b06340ae53d2383efd206b8b1eb3dd60c38f593efc05e2ba5fb8989472bac7db60fcada2d18d4108ab36e8c20cc710d
+Qy = 0444cf65175f6bbaf647739cfd8407e7036fc6cc6208ccb9d776eb13e13b377136c683e108775d85b6bc5638926432a17344de965d45e042a0a8e0b63c7fc3a36fc15cf718f3baf
+k = 35a0215892d0c52ece29559ebfa061011da8d597af6b3d1ee988ea4819be194c79a42681476140738b1b5dc191485bd20c96c282ab38ddbc3987343155366b6a5d1ce7053efcd83
+R = 1a69a9a51f6b0dc196b2a8db2e8bf61764d4c65b038f43b5ed6b5dc2673971c32928606f92b7caafb4dab3cd61ee724bba71a0d5c788cde4b96ef6b453f2a69126dafc20dbc7c82
+S = 13b5463636b8462cd9f479de8d114e29e7011489bcb9735ffe9ca0707a07df3c0aba05043eab387bfedd9fe982fbf04968f2be200e9e052cb4b02223b8579913d713acf94e7dc80
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/main.c
new file mode 100644
index 000000000..2ca840611
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/main.c
@@ -0,0 +1,290 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Sign/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to configure and use PKA through
+  *          the STM32WBxx HAL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+PKA_HandleTypeDef hpka;
+
+/* USER CODE BEGIN PV */
+PKA_ECDSASignInTypeDef in = {0};
+PKA_ECDSASignOutTypeDef out = {0};
+__IO uint32_t operationComplete = 0;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_PKA_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* Configure LED2 */
+  BSP_LED_Init(LED2);
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_PKA_Init();
+  /* USER CODE BEGIN 2 */
+  /* Set input parameters */
+  in.primeOrderSize =  prime256v1_Order_len;
+  in.modulusSize =     prime256v1_Prime_len;
+  in.coefSign =        prime256v1_A_sign;
+  in.coef =            prime256v1_absA;
+  in.modulus =         prime256v1_Prime;
+  in.basePointX =      prime256v1_GeneratorX;
+  in.basePointY =      prime256v1_GeneratorY;
+  in.primeOrder =      prime256v1_Order;
+
+  in.integer =         SigGen_k;
+  in.hash =            SigGen_Hash_Msg;
+  in.privateKey =      SigGen_d;
+  
+  /* Launch the verification */
+  if(HAL_PKA_ECDSASign(&hpka, &in, 5000) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* Allocate required space */
+  out.RSign = malloc(prime256v1_Order_len);
+  out.SSign = malloc(prime256v1_Order_len);
+  if(out.RSign == NULL || out.SSign == NULL)
+  {
+    /* Not enough memory in heap */
+    Error_Handler();
+  }
+  
+  /* Copy the result to allocated space */
+  HAL_PKA_ECDSASign_GetResult(&hpka , &out, NULL);
+  
+  /* Compare to expected result */
+  if (memcmp(out.RSign, SigGen_R, SigGen_R_len) != 0)
+  {
+    Error_Handler();
+  }
+  
+  if (memcmp(out.SSign, SigGen_S, SigGen_S_len) != 0)
+  {
+    Error_Handler();
+  }
+  
+  /* Deinitialize the PKA */
+  if(HAL_PKA_DeInit(&hpka) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* Success */
+  operationComplete = 1;
+  BSP_LED_On(LED2);
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief PKA Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_PKA_Init(void)
+{
+
+  /* USER CODE BEGIN PKA_Init 0 */
+
+  /* USER CODE END PKA_Init 0 */
+
+  /* USER CODE BEGIN PKA_Init 1 */
+
+  /* USER CODE END PKA_Init 1 */
+  hpka.Instance = PKA;
+  if (HAL_PKA_Init(&hpka) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN PKA_Init 2 */
+
+  /* USER CODE END PKA_Init 2 */
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  operationComplete = 2;
+  while (1)
+  {
+    /* Error if LED2 is slowly blinking (1 sec. period) */
+    BSP_LED_Toggle(LED2); 
+    HAL_Delay(1000);   
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/prime256v1.c b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/prime256v1.c
new file mode 100644
index 000000000..ce2dc5e3c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/prime256v1.c
@@ -0,0 +1,96 @@
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Sign/Src/prime256v1.c
+  * @author  MCD Application Team
+  * @brief   This file contains reference buffers containing the description of
+  *          nist P-256 (ECDSA-256) published by NIST in Federal Information 
+  *          Processing Standards Publication FIPS PUB 186-4.
+  *          Additionnal buffer are provided to be used with PKA like abs(A)
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+  
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+const uint8_t prime256v1_Prime[] = {
+/*0x00,*/ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff
+};
+const uint32_t prime256v1_Prime_len = 32;
+
+const uint8_t prime256v1_A[] = {
+/*0x00,*/ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xfc
+};
+/* PKA operation need abs(a) */
+const uint8_t prime256v1_absA[] = {
+/*0x00,*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x03
+};
+const uint32_t prime256v1_A_len = 32;
+
+/* PKA operation need the sign of A */
+const uint32_t prime256v1_A_sign = 1;
+
+const uint8_t prime256v1_B[] = {
+    0x5a, 0xc6, 0x35, 0xd8, 0xaa, 0x3a, 0x93, 0xe7, 0xb3, 0xeb, 0xbd, 0x55, 0x76, 0x98, 0x86,
+    0xbc, 0x65, 0x1d, 0x06, 0xb0, 0xcc, 0x53, 0xb0, 0xf6, 0x3b, 0xce, 0x3c, 0x3e, 0x27, 0xd2,
+    0x60, 0x4b
+};
+const uint32_t prime256v1_B_len = 32;
+
+const uint8_t prime256v1_Generator[] = {
+    0x04, 0x6b, 0x17, 0xd1, 0xf2, 0xe1, 0x2c, 0x42, 0x47, 0xf8, 0xbc, 0xe6, 0xe5, 0x63, 0xa4,
+    0x40, 0xf2, 0x77, 0x03, 0x7d, 0x81, 0x2d, 0xeb, 0x33, 0xa0, 0xf4, 0xa1, 0x39, 0x45, 0xd8,
+    0x98, 0xc2, 0x96, 0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a,
+    0x7c, 0x0f, 0x9e, 0x16, 0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40,
+    0x68, 0x37, 0xbf, 0x51, 0xf5
+};
+const uint32_t prime256v1_Generator_len = 65;
+
+/* This buffer is extracted from prime256v1_Generator as its first part */
+const uint8_t prime256v1_GeneratorX[] = {
+    0x6b, 0x17, 0xd1, 0xf2, 0xe1, 0x2c, 0x42, 0x47, 0xf8, 0xbc, 0xe6, 0xe5, 0x63, 0xa4, 0x40, 
+    0xf2, 0x77, 0x03, 0x7d, 0x81, 0x2d, 0xeb, 0x33, 0xa0, 0xf4, 0xa1, 0x39, 0x45, 0xd8, 0x98, 
+    0xc2, 0x96
+};
+const uint32_t prime256v1_GeneratorX_len = 32;
+
+/* This buffer is extracted from prime256v1_Generator as its second part */    
+const uint8_t prime256v1_GeneratorY[] = {
+    0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a, 0x7c, 0x0f, 0x9e, 
+    0x16, 0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40, 0x68, 0x37, 0xbf, 
+    0x51, 0xf5
+};
+const uint32_t prime256v1_GeneratorY_len = 32;
+
+const uint8_t prime256v1_Order[] = {
+/*0x00,*/ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xbc, 0xe6, 0xfa, 0xad, 0xa7, 0x17, 0x9e, 0x84, 0xf3, 0xb9, 0xca, 0xc2, 0xfc,
+    0x63, 0x25, 0x51
+};
+const uint32_t prime256v1_Order_len = 32;
+
+const uint32_t prime256v1_Cofactor = 1; /* (0x1) */
+
+const uint8_t prime256v1_Seed[] = {
+    0xc4, 0x9d, 0x36, 0x08, 0x86, 0xe7, 0x04, 0x93, 0x6a, 0x66, 0x78, 0xe1, 0x13, 0x9d, 0x26,
+    0xb7, 0x81, 0x9f, 0x7e, 0x90
+};
+const uint32_t prime256v1_Seed_len = 20;
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..fa706dc26
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,129 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Sign/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief PKA MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hpka: PKA handle pointer
+* @retval None
+*/
+void HAL_PKA_MspInit(PKA_HandleTypeDef* hpka)
+{
+  if(hpka->Instance==PKA)
+  {
+  /* USER CODE BEGIN PKA_MspInit 0 */
+
+  /* USER CODE END PKA_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_PKA_CLK_ENABLE();
+  /* USER CODE BEGIN PKA_MspInit 1 */
+
+  /* USER CODE END PKA_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief PKA MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hpka: PKA handle pointer
+* @retval None
+*/
+void HAL_PKA_MspDeInit(PKA_HandleTypeDef* hpka)
+{
+  if(hpka->Instance==PKA)
+  {
+  /* USER CODE BEGIN PKA_MspDeInit 0 */
+  /* Enable PKA reset state */
+  __HAL_RCC_PKA_FORCE_RESET();
+
+  /* Release PKA from reset state */
+  __HAL_RCC_PKA_RELEASE_RESET();
+  /* USER CODE END PKA_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_PKA_CLK_DISABLE();
+  /* USER CODE BEGIN PKA_MspDeInit 1 */
+
+  /* USER CODE END PKA_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..754560b3f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/stm32wbxx_it.c
@@ -0,0 +1,206 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Sign/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/readme.txt b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/readme.txt
new file mode 100644
index 000000000..c9e7d43c2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Sign/readme.txt
@@ -0,0 +1,86 @@
+/**
+  @page PKA_ECDSA_Sign ECDSA signature example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Sign/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the ECDSA signature example
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to compute a signed message regarding the Elliptic curve digital signature algorithm
+(ECDSA).
+
+For this example, a test vector have been extracted from National Institute of Standards and Technology (NIST)
+ - Cryptographic Algorithm Validation Program (CAVP) in order to demonstrate the usage of the hal.
+This reference files can be found under:
+"http://csrc.nist.gov/groups/STM/cavp/documents/dss/186-3ecdsatestvectors.zip (SigGen.txt)"
+
+This test vector has been choosen to demonstrate how to sign a message. The inputs and outputs definitions are included 
+in SigGen.c. The output signature is composed of two parts called "R" and "S". You can refer to this file for more informations.
+
+The selected curve for this example is P-256 (ECDSA-256) published by NIST in 
+Federal Information Processing Standards Publication FIPS PUB 186-4. The description
+of this curve is present in file Src/prime256v1.c.
+
+In case of success, the LED2 (GREEN) is ON.
+In case of any error, the LED2 (GREEN) is toggling slowly.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+PKA, PKA_ECDSA_Sign, Security, NIST, CAVP, ECDSA verification
+
+@par Directory contents 
+  
+  - PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - PKA/PKA_ECDSA_Sign/Inc/main.h                  Header for main.c module
+  - PKA/PKA_ECDSA_Sign/Src/stm32wbxx_it.c          Interrupt handlers
+  - PKA/PKA_ECDSA_Sign/Src/main.c                  Main program
+  - PKA/PKA_ECDSA_Sign/Src/stm32wbxx_hal_msp.c     HAL MSP module 
+  - PKA/PKA_ECDSA_Sign/Src/system_stm32wbxx.c      STM32WBxx system source file
+  - PKA/PKA_ECDSA_Sign/Src/prime256v1.c            Description of P-256 (ECDSA-256)
+  - PKA/PKA_ECDSA_Sign/Inc/prime256v1.h            Header for prime256v1.c
+  - PKA/PKA_ECDSA_Sign/Src/SigGen.c                Reflect the content of the test vector from SigGen.txt
+  - PKA/PKA_ECDSA_Sign/Src/SigGen.txt              Extract from NIST CAVP
+  - PKA/PKA_ECDSA_Sign/Inc/SigGen.h                Header of SigGen.c
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35xx devices.
+  
+  - This example has been tested with an STMicroelectronics NUCLEO-WB35CE
+    board and can be easily tailored to any other supported device 
+    and development board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following:
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+ 
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
+ 
\ No newline at end of file
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/.extSettings b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/.extSettings
new file mode 100644
index 000000000..7921b64cc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/.extSettings
@@ -0,0 +1,9 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Application/User=../Src/main.c;../Src/stm32wbxx_hal_msp.c;../Src/stm32wbxx_it.c;../Src/prime256v1.c;../Src/SigVer.c;
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/PKA_ECDSA_Verify_IT.ewd b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/PKA_ECDSA_Verify_IT.ewd
new file mode 100644
index 000000000..bd1724e31
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/PKA_ECDSA_Verify_IT.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		PKA_ECDSA_Verify_IT
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/PKA_ECDSA_Verify_IT.ewp b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/PKA_ECDSA_Verify_IT.ewp
new file mode 100644
index 000000000..1554de83f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/PKA_ECDSA_Verify_IT.ewp
@@ -0,0 +1,1131 @@
+
+
+  3
+  
+    PKA_ECDSA_Verify_IT
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        30
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$\startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$\..\Src\main.c
+      
+      
+        $PROJ_DIR$\..\Src\stm32wbxx_hal_msp.c
+      
+      
+        $PROJ_DIR$\..\Src\stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$\..\Src\prime256v1.c
+      
+      
+        $PROJ_DIR$\..\Src\SigVer.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$\..\readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$\..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE\nucleo_wb35ce.c
+        
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$\..\Src\system_stm32wbxx.c
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pka.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim_ex.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/Project.eww
new file mode 100644
index 000000000..974b4cd9d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\PKA_ECDSA_Verify_IT.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/stm32wb35xx_sram_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/stm32wb35xx_sram_cm4.icf
new file mode 100644
index 000000000..6426355fb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/EWARM/stm32wb35xx_sram_cm4.icf
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20003FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20004000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20008000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x2000FFFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/SigVer.h b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/SigVer.h
new file mode 100644
index 000000000..c83985dd5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/SigVer.h
@@ -0,0 +1,49 @@
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Verify_IT/Inc/SigVer.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of SigVer.c .
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __SIGVER_H
+#define __SIGVER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const uint8_t SigVer_Msg[];
+extern const uint32_t SigVer_Msg_len;
+extern const uint8_t SigVer_Hash_Msg[];
+extern const uint8_t SigVer_Hash_Msg_False[];
+extern const uint32_t SigVer_Hash_Msg_len;
+extern const uint8_t SigVer_Qx[];
+extern const uint32_t SigVer_Qx_len;
+extern const uint8_t SigVer_Qy[];
+extern const uint32_t SigVer_Qy_len;
+extern const uint8_t SigVer_R[];
+extern const uint32_t SigVer_R_len;
+extern const uint8_t SigVer_S[];
+extern const uint32_t SigVer_S_len;
+extern const uint32_t SigVer_Result;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SIGVER_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/main.h
new file mode 100644
index 000000000..1ed1cc8b6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/main.h
@@ -0,0 +1,73 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Verify_IT/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+#include "prime256v1.h"
+#include "SigVer.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/prime256v1.h b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/prime256v1.h
new file mode 100644
index 000000000..44394c803
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/prime256v1.h
@@ -0,0 +1,54 @@
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Verify_IT/Inc/PKV.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of prime256v1.c .
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PRIME256V1_H
+#define __PRIME256V1_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const uint8_t  prime256v1_Prime[];
+extern const uint32_t prime256v1_Prime_len;
+extern const uint8_t  prime256v1_A[];
+extern const uint8_t  prime256v1_absA[];
+extern const uint32_t prime256v1_A_len;
+extern const uint32_t prime256v1_A_sign;
+extern const uint8_t  prime256v1_B[];
+extern const uint32_t prime256v1_B_len;
+extern const uint8_t  prime256v1_Generator[];
+extern const uint32_t prime256v1_Generator_len;
+extern const uint8_t  prime256v1_GeneratorX[];
+extern const uint32_t prime256v1_GeneratorX_len;
+extern const uint8_t  prime256v1_GeneratorY[];
+extern const uint32_t prime256v1_GeneratorY_len;
+extern const uint8_t  prime256v1_Order[];
+extern const uint32_t prime256v1_Order_len;
+extern const uint32_t prime256v1_Cofactor;
+extern const uint8_t  prime256v1_Seed[];
+extern const uint32_t prime256v1_Seed_len;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PRIME256V1_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..e9bf557df
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+#define HAL_PKA_MODULE_ENABLED
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..bb77b782f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Verify_IT/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void PKA_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/MDK-ARM/PKA_ECDSA_Verify_IT.uvoptx b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/MDK-ARM/PKA_ECDSA_Verify_IT.uvoptx
new file mode 100644
index 000000000..77c2cd0d8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/MDK-ARM/PKA_ECDSA_Verify_IT.uvoptx
@@ -0,0 +1,533 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    PKA_ECDSA_Verify_IT
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      5
+      1
+      0
+      0
+      0
+      ../Src/prime256v1.c
+      prime256v1.c
+      0
+      0
+    
+    
+      3
+      6
+      1
+      0
+      0
+      0
+      ../Src/SigVer.c
+      SigVer.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      7
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pka.c
+      stm32wbxx_hal_pka.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      24
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      25
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/MDK-ARM/PKA_ECDSA_Verify_IT.uvprojx b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/MDK-ARM/PKA_ECDSA_Verify_IT.uvprojx
new file mode 100644
index 000000000..5f5da80fb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/MDK-ARM/PKA_ECDSA_Verify_IT.uvprojx
@@ -0,0 +1,556 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      PKA_ECDSA_Verify_IT
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          PKA_ECDSA_Verify_IT\
+          PKA_ECDSA_Verify_IT
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              prime256v1.c
+              1
+              ../Src/prime256v1.c
+            
+            
+              SigVer.c
+              1
+              ../Src/SigVer.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_pka.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pka.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/PKA_ECDSA_Verify_IT.ioc b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/PKA_ECDSA_Verify_IT.ioc
new file mode 100644
index 000000000..da6ffca63
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/PKA_ECDSA_Verify_IT.ioc
@@ -0,0 +1,110 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+KeepUserPlacement=false
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=PKA
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_PKA_VS_PKA
+Mcu.Pin1=VP_SYS_VS_Systick
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=false
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=PKA_ECDSA_Verify_IT.ioc
+ProjectManager.ProjectName=PKA_ECDSA_Verify_IT
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_PKA_Init-PKA-false-HAL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FLatency=FLASH_LATENCY_3
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FLatency,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_PKA_VS_PKA.Mode=PKA_Activate
+VP_PKA_VS_PKA.Signal=PKA_VS_PKA
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..6a7831b25
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/.project
new file mode 100644
index 000000000..27c3971bd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/.project
@@ -0,0 +1,160 @@
+
+
+	PKA_ECDSA_Verify_IT
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			PKA_ECDSA_Verify_IT.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/PKA_ECDSA_Verify_IT.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/SigVer.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/SigVer.c
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/prime256v1.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/prime256v1.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pka.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pka.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/SigVer.c b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/SigVer.c
new file mode 100644
index 000000000..0da224a1a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/SigVer.c
@@ -0,0 +1,94 @@
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Verify_IT/Src/SigVer.c
+  * @author  MCD Application Team
+  * @brief   This file contains reference buffers from 
+  *          NIST Cryptographic Algorithm Validation Program (CAVP).
+  *          (http://csrc.nist.gov/groups/STM/cavp/)
+  *          1 test vector is extracted to demonstrate PKA capability to
+  *          verify a signature using ECDSA (Elliptic Curve Digital Signature Algorithm) 
+  *          signature verification function principle.
+  *          It is adapted from SigVer.rsp section [P-256,SHA-256] available under
+  *          http://csrc.nist.gov/groups/STM/cavp/documents/dss/186-3ecdsatestvectors.zip
+  *          and provided in the same directory for reference.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+  
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/*
+  Adapted from
+  [P-256,SHA-256]
+  Msg = e1130af6a38ccb412a9c8d13e15dbfc9e69a16385af3c3f1e5da954fd5e7c45fd75e2b8c36699228e92840c0562fbf3772f07e17f1add56588dd45f7450e1217ad239922dd9c32695dc71ff2424ca0dec1321aa47064a044b7fe3c2b97d03ce470a592304c5ef21eed9f93da56bb232d1eeb0035f9bf0dfafdcc4606272b20a3
+  Qx = e424dc61d4bb3cb7ef4344a7f8957a0c5134e16f7a67c074f82e6e12f49abf3c
+  Qy = 970eed7aa2bc48651545949de1dddaf0127e5965ac85d1243d6f60e7dfaee927
+  R = bf96b99aa49c705c910be33142017c642ff540c76349b9dab72f981fd9347f4f
+  S = 17c55095819089c2e03b9cd415abdf12444e323075d98f31920b9e0f57ec871c
+  Result = P (0 )
+  
+  The hash of Msg is not part of PKA processing. It is provided directly in SigVer_Hash_Msg.
+  For reference, this buffer is created using SHA-256 hash with Msg as input in Hex bytes format.
+*/
+const uint8_t SigVer_Msg[] = {
+ 0xe1, 0x13, 0x0a, 0xf6, 0xa3, 0x8c, 0xcb, 0x41, 0x2a, 0x9c, 0x8d, 0x13, 0xe1, 0x5d, 0xbf, 0xc9,
+ 0xe6, 0x9a, 0x16, 0x38, 0x5a, 0xf3, 0xc3, 0xf1, 0xe5, 0xda, 0x95, 0x4f, 0xd5, 0xe7, 0xc4, 0x5f,
+ 0xd7, 0x5e, 0x2b, 0x8c, 0x36, 0x69, 0x92, 0x28, 0xe9, 0x28, 0x40, 0xc0, 0x56, 0x2f, 0xbf, 0x37,
+ 0x72, 0xf0, 0x7e, 0x17, 0xf1, 0xad, 0xd5, 0x65, 0x88, 0xdd, 0x45, 0xf7, 0x45, 0x0e, 0x12, 0x17,
+ 0xad, 0x23, 0x99, 0x22, 0xdd, 0x9c, 0x32, 0x69, 0x5d, 0xc7, 0x1f, 0xf2, 0x42, 0x4c, 0xa0, 0xde,
+ 0xc1, 0x32, 0x1a, 0xa4, 0x70, 0x64, 0xa0, 0x44, 0xb7, 0xfe, 0x3c, 0x2b, 0x97, 0xd0, 0x3c, 0xe4,
+ 0x70, 0xa5, 0x92, 0x30, 0x4c, 0x5e, 0xf2, 0x1e, 0xed, 0x9f, 0x93, 0xda, 0x56, 0xbb, 0x23, 0x2d,
+ 0x1e, 0xeb, 0x00, 0x35, 0xf9, 0xbf, 0x0d, 0xfa, 0xfd, 0xcc, 0x46, 0x06, 0x27, 0x2b, 0x20, 0xa3
+};
+const uint32_t SigVer_Msg_len = 128;
+
+const uint8_t SigVer_Hash_Msg[] = {
+ 0xd1, 0xb8, 0xef, 0x21, 0xeb, 0x41, 0x82, 0xee, 0x27, 0x06, 0x38, 0x06, 0x10, 0x63, 0xa3, 0xf3,
+ 0xc1, 0x6c, 0x11, 0x4e, 0x33, 0x93, 0x7f, 0x69, 0xfb, 0x23, 0x2c, 0xc8, 0x33, 0x96, 0x5a, 0x94
+};
+
+/* Add a false hash message by corrupting the first byte of SigVer_Hash_Msg */
+const uint8_t SigVer_Hash_Msg_False[] = {
+ 0x00, 0xb8, 0xef, 0x21, 0xeb, 0x41, 0x82, 0xee, 0x27, 0x06, 0x38, 0x06, 0x10, 0x63, 0xa3, 0xf3,
+ 0xc1, 0x6c, 0x11, 0x4e, 0x33, 0x93, 0x7f, 0x69, 0xfb, 0x23, 0x2c, 0xc8, 0x33, 0x96, 0x5a, 0x94
+};
+
+const uint32_t SigVer_Hash_Msg_len = 32;
+
+const uint8_t SigVer_Qx[] = {
+ 0xe4, 0x24, 0xdc, 0x61, 0xd4, 0xbb, 0x3c, 0xb7, 0xef, 0x43, 0x44, 0xa7, 0xf8, 0x95, 0x7a, 0x0c,
+ 0x51, 0x34, 0xe1, 0x6f, 0x7a, 0x67, 0xc0, 0x74, 0xf8, 0x2e, 0x6e, 0x12, 0xf4, 0x9a, 0xbf, 0x3c
+};
+const uint32_t SigVer_Qx_len = 32;
+
+const uint8_t SigVer_Qy[] = {
+ 0x97, 0x0e, 0xed, 0x7a, 0xa2, 0xbc, 0x48, 0x65, 0x15, 0x45, 0x94, 0x9d, 0xe1, 0xdd, 0xda, 0xf0,
+ 0x12, 0x7e, 0x59, 0x65, 0xac, 0x85, 0xd1, 0x24, 0x3d, 0x6f, 0x60, 0xe7, 0xdf, 0xae, 0xe9, 0x27
+};
+const uint32_t SigVer_Qy_len = 32;
+
+const uint8_t SigVer_R[] = {
+ 0xbf, 0x96, 0xb9, 0x9a, 0xa4, 0x9c, 0x70, 0x5c, 0x91, 0x0b, 0xe3, 0x31, 0x42, 0x01, 0x7c, 0x64,
+ 0x2f, 0xf5, 0x40, 0xc7, 0x63, 0x49, 0xb9, 0xda, 0xb7, 0x2f, 0x98, 0x1f, 0xd9, 0x34, 0x7f, 0x4f
+};
+const uint32_t SigVer_R_len = 32;
+
+const uint8_t SigVer_S[] = {
+ 0x17, 0xc5, 0x50, 0x95, 0x81, 0x90, 0x89, 0xc2, 0xe0, 0x3b, 0x9c, 0xd4, 0x15, 0xab, 0xdf, 0x12,
+ 0x44, 0x4e, 0x32, 0x30, 0x75, 0xd9, 0x8f, 0x31, 0x92, 0x0b, 0x9e, 0x0f, 0x57, 0xec, 0x87, 0x1c
+};
+const uint32_t SigVer_S_len = 32;
+
+const uint32_t SigVer_Result = SET;
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/SigVer.rsp b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/SigVer.rsp
new file mode 100644
index 000000000..4ae1a27ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/SigVer.rsp
@@ -0,0 +1,8032 @@
+#  CAVS 11.0
+#  "SigVer" information
+#  Curves/SHAs selected: P-192,SHA-1 P-192,SHA-224 P-192,SHA-256 P-192,SHA-384 P-192,SHA-512 P-224,SHA-1 P-224,SHA-224 P-224,SHA-256 P-224,SHA-384 P-224,SHA-512 P-256,SHA-1 P-256,SHA-224 P-256,SHA-256 P-256,SHA-384 P-256,SHA-512 P-384,SHA-1 P-384,SHA-224 P-384,SHA-256 P-384,SHA-384 P-384,SHA-512 P-521,SHA-1 P-521,SHA-224 P-521,SHA-256 P-521,SHA-384 P-521,SHA-512 K-163,SHA-1 K-163,SHA-224 K-163,SHA-256 K-163,SHA-384 K-163,SHA-512 K-233,SHA-1 K-233,SHA-224 K-233,SHA-256 K-233,SHA-384 K-233,SHA-512 K-283,SHA-1 K-283,SHA-224 K-283,SHA-256 K-283,SHA-384 K-283,SHA-512 K-409,SHA-1 K-409,SHA-224 K-409,SHA-256 K-409,SHA-384 K-409,SHA-512 K-571,SHA-1 K-571,SHA-224 K-571,SHA-256 K-571,SHA-384 K-571,SHA-512 B-163,SHA-1 B-163,SHA-224 B-163,SHA-256 B-163,SHA-384 B-163,SHA-512 B-233,SHA-1 B-233,SHA-224 B-233,SHA-256 B-233,SHA-253846 B-233,SHA-512 B-283,SHA-1 B-283,SHA-224 B-283,SHA-256 B-283,SHA-384 B-283,SHA-512 B-409,SHA-1 B-409,SHA-224 B-409,SHA-256 B-409,SHA-384 B-409,SHA-512 B-571,SHA-1 B-571,SHA-224 B-571,SHA-256 B-571,SHA-384 B-571,SHA-512
+#  Generated on Wed Mar 16 16:16:55 2011
+
+
+
+[P-192,SHA-1]
+
+Msg = 0f6be792b3525f87712a85e6ca8113641ca236b1e7b2446edfc081d08e9c28a7bce507d61caa6de3e66002a6ddc020e257353fee70773ee38381cd82e5014ea446777a25bc141da38bb74d922c61cde6c3d43116cff5d67564476e6de0366a99fbba4b811c66ff851f51b25f1db87a2b6a33da0d3e94335b00620754a20bf19f
+Qx = 1de0280fbc9fecb9852b43e5ad9afe9e7913785c0dd26281
+Qy = df29c3aad5cc12e09c92dd90f32ee05f2b2522ded35bac18
+R = 5094e6e7982856996dbdd8c2fbec21992426213852d2f772
+S = c44050cbc64b739f0c37851da5c47e3177054ea0b843fdba
+Result = F (3 - S changed)
+
+Msg = fb4f3db57655aa3016d07985c77eb95ffb256cc50d661fb0f30a31aef1ac9968353d6a5d7fd1a3930b88a9297e4d0e744106faa900114b67204d315d7052df8e34991926ca36e9a9933d0cf9f328dfe03b8dea1261962f6a9c6c895f16349e9af319b61390e892abf2326e4ee148ba16f75fc4744f021598f3c09f0c07fa8f66
+Qx = 70ef83c08dff35f0184fa5cff46c182c40c91766e527c624
+Qy = 06fbc81ed89fd491a83fd0da13e50ffe17ba97c404ea12de
+R = dc848500dd3825c8d5990536e78355a1318f1a2c7713e7cc
+S = b1c2660a11652181c78fea1720b366cade205356bec12b3e
+Result = F (4 - Q changed)
+
+Msg = e3225e4675dd7f95a127c6efce7dd6e6882cf6650776ab0d3dc10a0d1af817b57932422a3282a4b3745197cad609c32834b58b5fb9626035a590664f30c8bb2dbcb78f5b6865f28614763399235ddc2dadc3d41d938008fcb1ee161ab7c5e027c9bcdc78a0fa7c4c674660a03723b38f203490b22876c3fc316710a681e9db70
+Qx = 1a1ac87e30b5d4a66817ca61373bd3e92f0b76508f5af2eb
+Qy = 22c6ced9da726112cadd5f521314fda7dd795590348dac7d
+R = f9f9b48cee34fbaddce974dc219a70edba13f27781c33a17
+S = 066fcaf44d85fc1a462f1ccc8ac2eec7bad3fa63505722ae
+Result = F (3 - S changed)
+
+Msg = a71f34071adf6f2423e431bb89c0ddf886b9e845ae8086fcfeb4f2f92c8160a5f7f4a5a0fcfcfb3dc4ec2203feabe5d7bfeb5796e4b05a434e7f1969895ab5b6e14fd9f378d2ba6838fb22b60c30848041db05fa0637916ea3367f91ba22e4491f2bc39692af0d2779df1fcadcbec27427216b4ad365a7354d0ea29ca7405902
+Qx = e0639c2bcca7d6ff0a461fad25a308068281a7a766594505
+Qy = bba2c15abbfebbc07d56e7e7938b852e55bd4156cb8bb485
+R = 56bd4daa093dd0aa7553e6484c551d3d59d9c297a9b48ed2
+S = b9dda8aa39d6be8064a916186dbe91fde9e9343377f01b10
+Result = F (1 - Message changed)
+
+Msg = bf826447a665165a837ed32a13c49e3b57a9e9bce263d1492bcc418b0eefd4093032b62ecd27f1a2031af454077f7858f1e3970050e9b44b98b388b27f3487fdf27adcaae07dc7ab1913dd7983a9744063dd01e976cb818cc7c3a838b50bc55588d41240d97b714d2c2dab550814724250a5a478ad445e154bc8950f8f1aaa37
+Qx = 72a83b1ee3f83034324db4377663c933b4799564b2335bea
+Qy = 76b0c9874b94daff7e78881d22e5fcd53a3ea2afd0d118f4
+R = 161e7d162dbeeb5f8d3393df65fb6a136ad867ddd3b85ca0
+S = 301cdf1284766043f9a0cc1eb2f2a21538dd8e618cc46ff3
+Result = P (0 )
+
+Msg = f3b53719057f9834234133022f7cb2dccaa8adbfd3ad5e2fb0f7c1ae2a1f8dc2f1b57563c23c438cd78da6d4e7ee601d38fe2f856deb735406d52a4a3159c5e25583497521a2ff3ac59af9e6c530f2ff0f89fa06bbef69df84f0a0f75ad1c437fbd40026ee96b3eef840b5f1db0b9dc8626c76d6f49cefa2cbbb7914f2eced0a
+Qx = a523a664117b5df1b9a5c8c6207e38734e71271d0de424c3
+Qy = b4f5ba413184d4fb6e9f91dfb17a0c0915a60c7892ca76ee
+R = e49f9a94c4154847d76250e382c48e08e8e844b71a6f0426
+S = 72a40febae3dbef7e2502af9a0d1680099593f86ead4ab39
+Result = P (0 )
+
+Msg = 5654ae47eceee7ebc310b5a0f2cf6415d18a8a032f6d8291c57728c39b0d99f80509898c78383f23ee424d6c2435483bcdc5dd33c5584e071c26b7ee3699f8902f3de876c528fa61c9e7db4e104324efae99143c78c8d105a65844eac8e367562d47f656dc73b73c4ec8fd1d2cbab57bcafec7b28aaa812bd21054db8cc63fc3
+Qx = 512c2d323afae47d86b970e620d643a6ec4b0357e21fc321
+Qy = 391f2c6530adda5f2c3b6f168ff81229b026151c1abeeb62
+R = 83a1434e4b2f71e5a0c3c57587b6e94e391f8a8306d018de
+S = 9709214e1724a13c37c080d4ec6ea44cff339869731f08e7
+Result = F (2 - R changed)
+
+Msg = 1087e5ca344f89933472316b1c5f2e96f2ecf02814b1ad3842996969485e87ae83cec09f93e98bd008f2e49ee61ff14991fd41cd93a8df2daa95245132b759d4370cc2fa594e70aaaa70fa178474dcaa105e239ecc92f07987926b08cc2004e0defd2268811f66fd08355e559f5298def1cedf984c2d52de2205df4117b04a2a
+Qx = c43d6da5e4a58bb05a0ebb50f5bb3c3128bc31e07ff95c2b
+Qy = a8815058936487d59fa756abd024f44f5f349ffa9a6caa2b
+R = 2190ec68223d6a88d43b5ad840ed5a9a8ecc4c622ecbee6a
+S = 9542ad83d0508c358b5898cc375d288525a06496a571cea5
+Result = F (1 - Message changed)
+
+Msg = 6d807ed1c714b046588a57e4e755708f04ecb879730c49f2621a679e0c9a50230a0905873eba8cbd42bbe4b5ca085a3a0f14017bbd9f2765764e551180c5472b4c21d11bbc1cafeed5a8765202d81de2c4178793f797a08c3b5601526aa16e252260f067bceab1ed6468d4795bf96574dd6971321fb275a5a6855e8659b64ffc
+Qx = bb3ed558d840e89336e9d69ee294eb91801d66e3af7acd00
+Qy = 17b991605489d6a0154bb944db68c4731aabe3efe8e8e4aa
+R = 1b5e8edd1ea737d270757571a22239444e8cd6e8f801d7ba
+S = 10724a626fb874608ddf350336036a5a5823e975fb0f8938
+Result = F (2 - R changed)
+
+Msg = 8b44f92646e6ec2e7c60422f5c78080f7448d0fa639ad91042039082fa3711b4515b9d10e8384485533a1ac3cdf77fa45c435c4790fd94f589a76a1805bfab1259528e9734ca1cf206c5c430934fa2c30971384bf6c109ac43c7f335086a618f6fc93bcf976f12fcf66e627275594cfe3044382276f5dec0c0cfc1d84c65a08a
+Qx = 09b987c0b19cff63059833750db6a43c6ec9ae043d6183a0
+Qy = 489e72e62d78f20d53c8e86f4bdd7270113c92a09fa16b45
+R = 26aebb41860e18925e1fb56daff89160e6378a00cbc7822d
+S = 6e4761dac179ec2d1307ffe93e55381225e5ad8506cb3aae
+Result = F (3 - S changed)
+
+Msg = 22a0c4a4bd59810da36b0765a74fe3e4dbc042eb1df3e8ae916e97c4db4687f085645471f53189d33bf0ce63c7f6d0f65f9b510db4189ecb17d5b0e49f7eaae2d3ad2c7f40af1ac0196873a6b2867acd594f7fa227b8cf72eda770fb15037ce46ddc47ce4d870f26a96523e6f52f6fe5ee6bf64a6546cdc6455e97db099d5ae3
+Qx = 0cfc734884e0aaff06a65ab398003f516828e801207d820e
+Qy = a9e38a6a3025f782d1c12b0522e0beb6c8667d2679025526
+R = 8eb9b1ed1781e0fb2f6f167ce21b2401165b9f755a3ca4d3
+S = 79d6461f36d9604b04e8c570ec2690b135b2efe48f5b9cd2
+Result = F (2 - R changed)
+
+Msg = 79f284dec0c329b2f48e534324e51eaf1f1c32a17159a55f2b1387f0df46bd7f9e9f48bd96dc0efee06d0400b65bfd683c8a231fb22e3c6fb417370d1d0291ec2949d33c4a0fa40037451c42029c773092df2652f9d8baab312ba120a61ad75cfe3dce779a8a8df90738999b9da203e65f72a95ba122e17239e164345cdfc89e
+Qx = 3db70ceec7d35c4af73ea364c1b192887c76feb75f3d8a4f
+Qy = 92c94044326a6e6877a58b2800e66c9708e168f8456789d6
+R = f205a1f23dc9dd4e4c4019c44cd42628eb825ecb3161db4f
+S = 2be21a381e023b9fde00738e3514ad7e2a42139040970934
+Result = P (0 )
+
+Msg = 374b93bc6b6f40ee4d741fbb8b2a0b807611267a4f8f1ef2fc1d263a4d68dca534ed70451ecdcda3d849101386f5ac332fb557d935fe07e20f3e51db0e3497faa2bfee5a6d02ea956d09f70e1b562cd12d675ae943b37939b753b593aea78f767bec0ba0249eb71490e1ad17d7261c8816b8140d77b2144bcd5b24fe3773f20a
+Qx = 27d4d2c617add5ba36d003f4441b60b8021131eda49d0d4a
+Qy = 789835b870bef5db4921eabb36d84847ae7b6828b6d38165
+R = 867cc808d9502b6294a7ab3e8f389cb8a10d5cf2f241d482
+S = 7005408173103c62f2c8e2ea9b5c2d71f5855c51b8afb45f
+Result = F (4 - Q changed)
+
+Msg = bbb9cb23e26f2548bfe5630e191be33efb0ecff0d13f3794c050dc07761364fdbfe601aeaea68bc85757a0e564d833984611a9b1d0a82b8305f857cdc30c53f218c8a4ea566c5a159d81095b109fc83f013d0e62f77b608d6565465d228cd29028153e977f4f52252ef6b54c723b15ae7cd975d499f471f073e356a20e5f7576
+Qx = f8b9560f3a17e6488ce0795f8ae4be916b54bf4285363c60
+Qy = 93c97a1f837f2370857af7b8a1567bd0d9ad2db1a5c3f1a8
+R = db31361c14ae97e40764cac900632b77de81f9262f130584
+S = 8154d879e81ccda96624aeee8c264d0208d4d81d695d14b6
+Result = F (1 - Message changed)
+
+Msg = 867e68b6924140b1355e945e13949e2a6cf53696a117612f8834681514b7048a8f8ad01c479b2c3897cdb96df792f33369ee7bb4fd0621897a2132853debc4ed153aff071ece96e379b1082a1a625ad1a69f1e01e773aa1229563afa038e841ce9933b5fa0f0201d3f12d05ee9c96e6101c7d2ca38db117ab2e0d97bb3991d51
+Qx = c33c7d40ca5ac462ae4a373f07a2470e6b3c4c46c7878847
+Qy = 5d34e0869a57d0a502576f81558a462da82610cc68186bb9
+R = 678d84cc22a740371ee41e9d7cea508f52642d9fe5b9188f
+S = f5dfe56c5cc6593f99444a96396b0586d89f8d2836775a36
+Result = F (4 - Q changed)
+
+[P-192,SHA-224]
+
+Msg = 448c9b35d6a3c01c048b7faaf7d92be7ec115c52488272c8e106edb4613467598d018085eb2e3ed44a811f6758801987d41089b424fbba1363d329ecb42722aec4f6d3b564c567fff84c717cf4d3d28072132302b96769515b5b21e21ce3ffcab51787490f7a0e0d6680465aa8fa082636df80aeea1b86ff5f1722c732228dfd
+Qx = db451fd9249d57e49e7baed41c20208d8a02e466bde80ebf
+Qy = 6deaa3380aa37bc6206b69ad79e9b863d9bb50970ddd8250
+R = 4cb5a63d5d058a4ec5cf6fab413d9d56037e323e0b34a262
+S = b28a9b101d74a518ac7196701320c18921013bbf2498782b
+Result = F (1 - Message changed)
+
+Msg = 82b24590d32dabfb64299e54c11f017c77a3c148899d09b322ccb642aaee7546d420a1db33660fa58df8d36ab0ad2d5fde43c91723e7f40969011431f98a2571f941eaeb2dfb57e6b13998bf44736f7154c26b8cd07c8b085b028828d4afbf7a7920c4ac8178d42dbb976657ac4286b30946da1d32d06e19c7be2ed5549567ce
+Qx = 07a0a7bf4089f58c77e883701dcb4a1ece3ffce62e1a110a
+Qy = c1233449b78d098636a8c94202edc7a564b98a5970b96c51
+R = 6917190e7db2c23d67b49932d2f24cc2757ebdf60c79b7b0
+S = 140b660e7b8447467b725c2b9c8f2df1d65ed4925f9b60b0
+Result = F (1 - Message changed)
+
+Msg = c249c142ec49d38fdedc33cfaa58b025c0ab36329794d8db65bb9ccbaffb930a9003ba70d07dd2d96b9e263c002013a34bdf02884e40267c07b2a6203374eab04182b57d19885b193be288cb3394b2be1d13fe3a613c3ad5e4dc15503573bce0ade1637fa7f60c72e90e399ecde75492774366a68451f8d65b9a2c37d3a7e74c
+Qx = d1648aa094db4f1549561dffa7215007bf81739581fbfa46
+Qy = 44d9f9bb70ff41d86d474ee1e5c6bc561632bf082c0be9cf
+R = d20dab7444a2066aa93815217ea0b0d0c2558680e77829b3
+S = f635ffac94144753fa062ec393a795cc9323c4914a3023e5
+Result = P (0 )
+
+Msg = 3b36a25d15c00bd3258f33bc9f5929524a2f5de3cdc2108d56caea9274e7b78036d34a198139f267a34b7997842e65a348cc5127bc3190944932e9c50559779bb2acb82645a9c29b044971b0a7245e4588db5e4f6e07e803ea5d7156a4445f6a26e625fcb55bd3dbd63d00cf9808ab601b8caaa5691bd254319433cc2381d66d
+Qx = 7d0149399a41cbe032c352be3e4cd24ca8d2490abb5c6934
+Qy = e59a784d4037fc756921c23a9ceeefeb8b086fcd5086fd81
+R = 07e94f8f3b21196d18037d66d62ba58d821a02ebc00bc900
+S = a54e5eaf65479dd8d2d670ae46be3a985b6c6882d990bf1d
+Result = F (3 - S changed)
+
+Msg = 126b03e7f9db71dc963fea83f50130b273ed0197fbde2e1019b10c0f8d4443f7960dcdf834b04c25a46d5bc178342c28f23e8c13ab404cd59a721f91cb56d6d7d8ee346259f7f65eb54a8117c2a37f89a0a0829bbf536194c21142f095a8a15caf5e26a8200f39419179e89b1531b5dc5954457f7d74f9990a607d0b1e60dfd7
+Qx = f63a2183941303f40049372b9b4162989db4d00efd7075cd
+Qy = 39513f00897532519441629bb73e0a818263a802c145fa6c
+R = 3095510a8b800aef0dc41cbb1791c6be17c72c5906beeab6
+S = 9df7906fb7c979a2776efc64c67d9943c51a0521a3f3475f
+Result = F (3 - S changed)
+
+Msg = aec4a1f2f6d9d14958f9d367aac5a197aaaaa3170e771b16a375c9c77ab6101f36d9c1834ac27662bebe89828d84aaef76a88195d947312e0ae629ce2012ea090a2347c6a973398bf4bf98a6920b651fa37aef07a5defbdb331f9ca11ebb2378dc9e37e528c49bc184e6f1a678c611f39126d1f97454f9c0ccf74ce71111fa85
+Qx = 71c89736fbf6a64ccc3326b6c844b4d9a56b0ab88a40388b
+Qy = c17e3424f5cdbcf06bc014cc0a037ba9eae42c8028aec6db
+R = d74a3034753be92cf8430579538ad4ed29f1df16bdf42a48
+S = 030d316891c6f724baa9bfbf7b439dcef05ac937072fc007
+Result = F (4 - Q changed)
+
+Msg = 1b3a955979e2048964cfe18a624af4bf00bb054095d6fa2cfda2ee90f393b8eb27e3150f89ddf8697aa13a9a012eecbd3a995a24f789c0c464ff645fd2fcb0bc75e90c8c85948b96d3b178bd4900b35625cf43165ecbfed9cd20f050b1475bf94f2a858c867e276d2cc0b62f765a7d8915df41b9c0202faa6a60db81b2dc9a2f
+Qx = 98972a473ca9f447da595a7477f424190305d9ede65055bd
+Qy = 517459f0779289d5f2d21b0d84ed22f5e6b57bba0f754ee1
+R = 4061ada746f4a0c9cb34da5ca26ac1906ae415389adfec4a
+S = e73c7d210a139c44238b08e5767e6ec0058b6f352f600255
+Result = F (3 - S changed)
+
+Msg = 2d4bb1a2afb768d2290ec18087aca4e0bd407c2a7fa8dbcd2711bb3e9f92c7b130c542763ebbe83e42461b4f59691bbcd9a78bbf295eb52dae65293b3d2cd74c30e6d3ba844f7b2a19d8630e01bcbccd2756329d95d7f74758e1dc2c19b3b24aee73e2f8dfade69926ae6715f2ad60096e12709053b4455b511d3b785c036d38
+Qx = 9846a96e6039ba7e4737a6efcff0fb4b536801d87b54cbd1
+Qy = 6a9e837d96227c39018de3d706de4d0717d731ae703a621a
+R = 915ac6ea1207e165460819489916469d5616b97b4a66bc3e
+S = 10e0b2930f94f766c9a49bb815d4e9f72bbe3fdbab95b685
+Result = F (2 - R changed)
+
+Msg = eec0e75e31df03f10f6b785f4f6234d5ed27f2a12c424ac25cfec496c43a57e72596d635a44d80b37647ab067567393235abe2a62e481f3b8956b51ab4d6f86f172800b53ecd042862c47b75e23ebf58a0884924fa5036d7b53981c4e1382f48de7d8242feb6496691801aafa7222ebe472b158672249f8c7aa34f6121c51bd6
+Qx = 257deb2da2f0fe306d907951589180e887f19745227bc1f3
+Qy = 047cf30280eb70d26e305dcc78307e8d9cbf1081ceffcdfb
+R = 9dfc742c5e268b8ef109d4aa6a8b7a4c87a71dcd25898711
+S = d3727ecb086a3b9547c569cebb5105c1030e456761764229
+Result = F (2 - R changed)
+
+Msg = 1768c2c83be6c872bd7b805ed9ebf6e862a2fd7c543cafabb9c6e83cd68a265a553231924d1c2ba27a696e67296904dfdd020ed60b24f7272c88ddf6ca93dbc668424dbdf1cfdd91bc09d69068360e49c1de4efa38a6104ded5d67d7f498e6d76e3af80803bfe946cf15c9e4397c416b9116b792e021bff457dc25c4fd23036d
+Qx = bff5d34be222cba05fc318407ba3efec0c5998bc1d0bc52f
+Qy = ce02778e1ee64a23ad3cdf4ae72f0f1e4e8ad34cae1c364a
+R = 3f4df6fad5697d3f93dfe00f631e13808a0f2f2e93142328
+S = b970f78ee94138ff4d2ac04160c8e2807f39586096a76064
+Result = F (2 - R changed)
+
+Msg = 89a613bc3e8e534327db9b89d42137bd95175dde5f967e53398dbd98997455e882c3c9188927ecfd41a2d5b7863e18c24cbabb102164dc6077224938dfb3f15acbeaa254b0e537032d48d015c01689b47bf5305034838cf3d233c9adbc41316ed0f1ea56fe8605351e49ee87a2fb5f5a0e94fadccf0e153b2ec24346723aed44
+Qx = 0e141cd6d7a5b34e58a264e465d135172075ce18fb5fc3e7
+Qy = dc96df20da2666987038615d6e83bcdf0d3dba1fb81f8f5d
+R = a2648400ebda75a7c5887e2470da675949a6a953f403f0da
+S = 50b64dda591105085f1261af389165929ff83d8e0b353260
+Result = P (0 )
+
+Msg = 410cbffed21edd0a167d974749d288b1320a638bd08d43f7fad338952e371ad7840d20909c1d6fdd82afad20ed0aaf87dbcbf2bd1ec9795b82d87a40e1781a7aa9d28d4dc1d3bb95f08a124c77d7f50e4be54ccebb16eab551cc41adfcf48cb435502a9417f9ad9bfdeb4b47cdb99b2b062699e4475e27aae4e6a1056a511cae
+Qx = 8c5f8edcd0ff9d916934b7efbbbe0e1f67abacb96902963e
+Qy = 82d197e317b65787aad7095603e9b55cc8007f2b060cb799
+R = 107c929ef457541673abfcfa14488d68c3a82a97982221ad
+S = c19dcada426e4504b55cab20c5e7bf3b618e9a6860e784a6
+Result = P (0 )
+
+Msg = a1d75f51bd2afb919c1c466f828ed79c70e32630606d4d92b0d741eea462a82bf4576ebcf2d9f1222829d38e24b95103db72d085c7f9e592a6f47b099c3502edcdb8425f5c61f199d2daa93f1d86fb93fb087d3142caf7ac62751cc864ee3a34de23713fc762941bc72b19423dc0072516ccb267a45d1e839197d8fcbc50d6aa
+Qx = a720dc2f4ccd9e97b2a360adab75c4abc91cb411e2d48915
+Qy = c93cf8378fc323bcd0334e9707d9d57b9c46cc21b8c1b32a
+R = d59f6109852693e188fc35d2dff6174b5515955d0beaef6e
+S = 793f4dddec07ff016fef28334ce80d061dd7b9b40c098cd3
+Result = F (4 - Q changed)
+
+Msg = 3f8ea9c33aec03ae7593772e792dc6e2eab652f26ecda64c96df9f6e67f0af76a1a1256394c66ea20d2a0793fa2c839fb22d58974b1dc34ad19a6cb6718836bea9c4729b7dd3ef2d0458c2ada4d967da5477624e6d7eabca5967ff4881d86c4b01df98835b2cb78748aa93f6835729cd0e1b6f949575469e8c2a2d153540e9be
+Qx = ba4bfd9877e572bba92797b118d469043eb6aa2f0d283a7d
+Qy = acf6dba3f95d666de9f5c9dd5f0d45072d1d4a025c49fb34
+R = 170c50a89346c63192d892f083b91dcccc9fdf1929c3bfd7
+S = b102ca878728ecb321b406090f12bf584b3242810fc7bf17
+Result = F (1 - Message changed)
+
+Msg = 82cddd0a7b5f4be10273cc8137359f17ce2c3be76d486948aac7e4c6d4d694f8d362cc09b4cf7ba699f79b3e96cbcd13b004956745ab8e136db995abe560eb619ebd0804acf8c83ae399e545faa8e2502231626c4627a7933ff61f6f7f6451e3973bafe731715a0aedd2239afdcd844aa7d545c1f641c12a5139a788139a3b8d
+Qx = 8bcb523fd30bd0bf6bc053d1704d7669f175bfc3059a6b21
+Qy = 275df9b83f36c268aa760364b9b940558d94a5c5e6724f96
+R = ba4b932eb5083865a22bce03448e7d72b18df3185cfe2239
+S = f03cec955a946e342d7a5b0c9d040398d1107ddcc43b879a
+Result = F (4 - Q changed)
+
+[P-192,SHA-256]
+
+Msg = b15b9c059c4cfb771e717d72bb1d79578fe58296bf20497105ca099feaccbe0c1283db5d78799f3db39dcd3591c8ffbaf096c84a864d10d9bed843b479a433893de945bc7b4b6f15a28e86f83875a9a223e785af3467d8efda2342a916d183bf30ee33fc4cc688b74a196ee0e318990fc09afc3471a131b240d128c6a28acfe9
+Qx = 001e75261da06eba07f3ee911276b4b6e25ee37abf54fa41
+Qy = 5da176ff885ca3345508bc4c917128b2c87f6ab182113505
+R = e5e6bb6133dc7dc8926d3705cbced15d5820a29e7ac2de8d
+S = 46a6e3818a7286818250cea5a023be5b401b1026ea316843
+Result = F (4 - Q changed)
+
+Msg = cdf195592ed3a8d5a0924934efdf2c33c2b0f5d8c2e675633aaa4ec740a8b2861a90fa4e34995dfdc978b3e02cde5d8d63857cf091c926a3d9d15a5e61febc2977825272be1336e8c967989ffdbdaf5e1a23626e189c574251634fd894e344e11bb1ae39962a799a402101e24acb64e51555bc20feae97ee8f1a3d0ccc22bb71
+Qx = 711bdec50f8409b10fd2cfeb30e9e69c9aa27e3a535fb39a
+Qy = 3e90f90551e7eb7eda11fb016b0a386ebf48b4b2f3e8f272
+R = 5e61c8445f402c0c16ddfcd050d2a9fbfe495537c3d76ffb
+S = 09d0219f34b46c528d81d3d9c838253f942528e8f53329a2
+Result = F (1 - Message changed)
+
+Msg = 76f44a2dbb96d50840a37bcdb23f0d56e159bf4663c22c116963ada3df2431450019aa8ab922612dbe80f2d35b5096de41273f648edf09929a698c7e9028565afd16bd976e76a5a96360bf89a0908ce379c9f69c508c6cf6811e1cf5946e09a0d2d5a92387bd5a95aea5e1229b7810b5757bf88381ad2d3075e85cd47d28eec4
+Qx = b870597b4b8dc8fc07ed59b6f079e87936d56d0326c17249
+Qy = e54c404920cd530f0680d8aa2a4fb70b5f8605e6ebbf2751
+R = b53dc1abd4f65d5e0506fa146bee65ecb6cd5353830b67ea
+S = aa44232f2fa6613f85fda824ded69e4137cdf5688c6b3ba9
+Result = P (0 )
+
+Msg = df5437f01e4921f9c3c4d7bc59bce4090e73d08d7388077b3fe0c789374e917dc5bb0d2577703f5ae5bed27f26da6353b9ceaf694ded6576925edf2e8ca4fed2a14974a6a6550beb6e5478e90d221edd4bcad8368fb9f1aa42722f740fa9e9308d9aa14e34bcc177c60e32b0fcaef7ac8724335e746ce839b8c9c48593793cc1
+Qx = 795bbf28b86af380c2b080e622f92f81de6d2af41a39bc39
+Qy = 3d3bcfcbe704426e95d0edbf40eae25a259af239b00158c9
+R = 5a3fd911aac408cce41e0eaf42761cce155c5a6efe03df11
+S = 605ffbb146bf787888d9c3e45f79d0bc6959dcfacfaea437
+Result = P (0 )
+
+Msg = 5135c1548ed1e3bf372a535eb60d156620a8aec3a93b6624a7a4543375678f29dd179f4f5f1f1657a61d487d039e5b81e2b7170a9a5299f8b2de495a4757589ec338a2a49a27edb88267c31bdbd31e50d609e936fba520068c71659ccad7f198e0e78bc418f015f27b7c474053db811b35fbc48b5c08a448e2e7687140769da8
+Qx = a4649bc7409284af97e8d78d3a71fc4c8fd2371f02735ac5
+Qy = 38cc4e81ef00d74d4e80d111bcaa492b57e7f981239bd842
+R = 3ca2c26d18e20f9ae00b9a00ecf6e435d456473e0636df6b
+S = d2f3df485bba0e1049e7968cc19c88c7681f5acd6a98a217
+Result = F (4 - Q changed)
+
+Msg = ee934fdc29b8eb22eac4a296528068bed89adddade1c47c46dd328ac14858fcc8534aa26bffc611307d93b102e45902f795926aee4b362e1d07814f8ecb2ee46e486afd6577848f20d6a946f5b60d2533ef01cd7c77cb855a8786bef737f380a0580a579e58d07ded99e53f0ab385cb177bf8adf63a4d78b6afb18b4f610d5e8
+Qx = 8698b9f47ce024b0a139d1aee610c1d549aa3512a990b211
+Qy = 998be4c51c70d4fea9b2b2e274dad47175f9d68c8a1c28a4
+R = 13d7c9f471863cd4ee3ce5458f1fa436f12f50f965ee40bc
+S = 8cce6c1787a66f30679b92de51cd3b04a0c1900bc1008133
+Result = F (3 - S changed)
+
+Msg = 2746f2ea08742059818e313ccf78256b33ed46ffc344163b99ad705ccdb2d9289582d5d324ebfe687c6f9454cb720ac91e533b6df12abb55386194468ca67b0d4679f7d0cb6d935fddbb92b3153588e02619510982068fabb86f065c6512fbb7d18c4b9f521e993217d451e05fb4dfaf757075870eb813ae8c634864d628be73
+Qx = 49a5fbbe214a0ff9e9294dfb9859351c70a9c4f5c2ba04b9
+Qy = bd96de36fc10d369b52daa08931dfbbe9f814ceabc3157dc
+R = ed3b86f05b80274e7e437b365b7b5ae7af978b7014f76795
+S = 4fa8d7e87c9c2cea7b1efeb698c78c6a1233cd6abc2fa0ff
+Result = F (1 - Message changed)
+
+Msg = d8ec0aecdcc7b92ac84941740ceadd176a0684cc291decfa9189a7e4522d5bbe4691fa22e615676ff945be54cbdcd7f67c4d7367b35cfe7461803be61580f7510bcab22c78d829cd119eea2a93f52ceac369fa4e211f9bbb49540b5f6c6fc47d47b9e48657433f96b15148441be0867a426ce5f14aba749f70850be630c5c691
+Qx = 22a848cf9716cb1cd0d9ca50cc9369c93ffb830642861e6f
+Qy = 759ab99598b7d91540d456344c66a9742d8768a3ed2d90cb
+R = de2d383f3498108b8096fd70f2cffc163dc25878c7f46ac3
+S = e20a35b3d4ed4df57aa3b3cd7b21ef6de04e378a47c410d5
+Result = F (4 - Q changed)
+
+Msg = 7dc617288592c896cf0ddebeca21d00ba759a1113b607e8a1c499b4c3dcd1a16f26af747ff0091b0200cf3947b0664476c93d33c0c9f303981c07d13dec34fa4e01642e9a581a32f6e5acf5e1a483b6611a32bd51193d80786c75271c6a6af013e980c8f39edb8efe2164d8a793f470a33428a3be281139e75cd26aecd8517d6
+Qx = 390ca1526943a85332c96aab75a10ec30fda9fb197ded9aa
+Qy = 1260266139849659339e3cbb83a9ee3a63f45ff7b96266bb
+R = fdbe0c0864213e258abbedc29dd359a4c58e060c351b15fd
+S = 3dc705de56f9c1d6e7774dbb70dd48d34c891bcffbcc30df
+Result = F (2 - R changed)
+
+Msg = dfb645308073ac30fc353037da4aab7655366b4b3b5e29e212415aa120b93ab3963f5a4d907dc5e6d75b8987db635422715602e6219e68459d2e935aeb1e90766d5a68981cda9c7809cc41aeb26fcfffc99dd658c45697614858369062c0f91a66172fae9ee73f1fc18a201099e95a5aa978bcdf91adfca344f0fd068e6ef104
+Qx = 94f19bada578f6659eb3790b5a914b38d68084659ecbbb0f
+Qy = d69cbc24b2f3cc074fb727bb74bfb52d6fcc00959b5c7aaf
+R = bef73286b737e5cad10c56e5166596c0007009dbe5773c99
+S = 3836d1676d8c9879d29cb164bb8fa6e003aca7c877500637
+Result = F (3 - S changed)
+
+Msg = df7ad85e1ce15317a2a7387799d46bb3a1aea6393ebefa7a706db33ec254c1b928de0ed5d91b18049976c9b255fe03a299d33a9a5ca1a21eca138e9f9514b3711722b95fc04d63cd212fb3473077729eb6c9a1dba1b00dfbd54490a02a618ca1418ef50e117ebe750ff48cf5593d6a4cf183a0f52f44a22be848b7b095ff666c
+Qx = 6fb2a2b4bd1e07ff8bdd00aa5058e40261eb5f9ce0e23a41
+Qy = 6d26fec06f841e7604d1ae630754d958fd9a1bfd9c995eba
+R = 0900c78216384c24a4bde4a2f520f922cef98d74c936dd98
+S = 75be2d206170358d50c486b7dee02c028ed5ad0a2d2cc79e
+Result = F (2 - R changed)
+
+Msg = d9d640af97f8d495f4d4bb94669dc51f31d6fb1855ff5d9b36cfd966c60c0ac521fe0fef00d15ee7560c03bed240c15e19cf6bb43fddb95f201392020ce0bf1f2baafcb7c6561d501a55873ac0fe0838027e12b6c09f2809b39692dd19dc69ece1a36409a2eb11304e202fae854fec2e8a09c5c7bb251462b69022c3d23f9ee4
+Qx = 8109731205bd9e363c0521cddf94af58129af3f38d276f2a
+Qy = 9fcf7695165bafb39c2d53b61c4ccfed3891abc6db1fc22c
+R = cac3fe60f567724f7afb825aeda68c3b345b44ef3879dc70
+S = 4544b7d4457b61b66cabfd6174f2c5a594b2c0f300b0e8ea
+Result = P (0 )
+
+Msg = 67eb2fb28d6883a44f346129096f3462ca6376ac0e3d80d938335c02c445a4641de6b25f2beabeb74030c05f0693ed3f7a9e523bc7653dc2abeb05577f0b89feed0005500cb3cac2a18d127a9b4603945198aa3f1f5a722e29eadd91db13ece9bc9689372f889af9d3f88001f6db9134f023dc08efa5d625adec4d27a0f4010e
+Qx = 671500a8ede439b9cd742c8794fd499ef2bca403c59c9bc8
+Qy = fd34570186c86181b938d415dba827bc1cc6be2da584bdf2
+R = fd14760df3c592d4b9296aad0c52c531c36b432316343de4
+S = 3df1065f0c607ced37f64b1f2c3d1bbabf82e40e2600c931
+Result = F (3 - S changed)
+
+Msg = 097e2ff20999ad70fb9856ac432499e47cd0d811e4455fec205b4e720b08fa91ddbd3a3b74113b4dc79ce8fb14bf4ff5d116fddefedfe637a0e1d8e392a82c36381acd15157ec61f5578ae4205cec3299573b0f280859c8d5d37ab117d7f3a1c38446c781400df8f74026b0f0d0e63e9295bbdcc6c2124becd2388b1d5c64049
+Qx = a49a7cb0672ee7420e06b09faade3cfc07183f50f91bd498
+Qy = 8a630afe02ead1036e0810938a77f56c9310c4ec6d275b0e
+R = 6b4b1470700f7d568ac08d094747725e269dd76bdc2aa012
+S = c7054d95245290978e591e69c2bacf3f530a8600adf5e3fa
+Result = F (1 - Message changed)
+
+Msg = a4d66967721d5b0485931397d3befadc2f7924b9c1457513e2f528014a36b218b965f3fc2c2b30383fa1e9291189fef3e9e0517f6a67bb83972a6576e06ee205e627ba052d2d0609553f6f17733a6ae788c8302d9782df81980450ad7519aad9af963fa8853fffe91fac4bbd9f59f0756b03ce2dc1234f5d8b3157cfa1ca3b64
+Qx = 459c430e054519c7eaf38c8240e7a186239cb2c8569473d0
+Qy = d67c199ece1f0a25cb861d491036c2f3770675abd909e195
+R = 237295b61f0af811c327f41426ac7269850460fe4393e216
+S = c93cc5e9e2460b3dc62274ef58057e6327ac2d8459527fe5
+Result = F (2 - R changed)
+
+[P-192,SHA-384]
+
+Msg = ec44388857a8c460707eb73fc6f11bc6357fb09a3586ca0f56e05b9a3c875194cc438a0bb5c7979a5d04ccc79912883438756cfe79af7fe59934d7f0f6fe800dbe516816ab8a1fa786965716d520e47620cff233667fbed9c605630349965117584b68285eb3d93ae965ef63102d98a8da1c5d043894cc391ec542f11cb83938
+Qx = 3be73b07659d052424e46e60f4fda52eb41f076e34e16b34
+Qy = 4f3f1e7e1ecc83bd90e71add8dd98a20223895e4cfc7cdf6
+R = be419234049bd75217b3fdf2c92a8760880931c2fd4b482d
+S = 07eacdccdcc7233bec37e4bea1c4c018f041e11592e5327e
+Result = F (4 - Q changed)
+
+Msg = ce29634f6379fe471377d8b91060224c89e6e8fe2ec3f0adb0879a6861a46002a0ede258eed1d6a962dc8873281128abb032b24e4dc28269f70c8708b3da822579287ccc7b057f8dc6997c5780c888172d356825d0b1d81c6b1db3e075fd0840cae0b0780c4b8cd0c4cd21da4de3a5cbc0e3cde7bfc0b80162c9b93a6ec490d8
+Qx = d94863aa85d995664c3b0e1efeeda533f1951176faf70c1e
+Qy = b9404ddba252047ba0476bc7a13bd4a638176e88c116247c
+R = 821ea159d7adb606b67e81c430d3102d66d3adfac6979656
+S = 01b4df62071c38e2bd810b267b10d37f5bbd0d9fcf235a01
+Result = F (3 - S changed)
+
+Msg = 8303b131df6c0092d737d0c061c4524011288220bcc3b904146c164af727023bce05a79a53a1e1112d7bde4260ac8ff04b68bbe6afe5f9a8da079322643cc4ff53feae747eff685c3c36da51dc23fca899143b59a4a6dcc110249907babd60ff4c4f9fc2d86ceb7a4f1bdfb05bbc03e1f456b82b5297e6c7610c9b50844a4021
+Qx = 6df97b643f9695b2d93a6a859eeb337c6985087a4ae7b910
+Qy = fbf79a786e1d37524b36caedf93c176cdc9a8dc5bc372af0
+R = 784aa5df684092d70e2ddc3c57c99705446ef416c552d24b
+S = ac19927337f2cd3e76ac022e4537062ba252b5f68554bd71
+Result = F (2 - R changed)
+
+Msg = 755c8ef02263dcc3873c04b4383f1ff1e7e8327418a42c9d5eff66d9c0e5f02a3557be9b69bc307307c4d8d16398126684e33f5c942728a2dc11ddedb2d374a3a0bdf9aaf20291479bcefa5ee77f8e9965cf749b6dbdfb5a22f842c714605092f8ec4cfb887766b31abb10f1d996bc280a2d912e1c38ac6e33f978e8557c7161
+Qx = 9b17e7fc0dd000b0d5e38e111c3dd7df98584c18fa996dad
+Qy = bc80a114e4312951a0342149e750241cf1f35fc994a54600
+R = 8c512f9a24cbf71bab2dafc565834112d655e7bd9efeb86b
+S = 47661c172de68d177a5042f1a3661e7a91d6462576ecbfda
+Result = F (2 - R changed)
+
+Msg = a00bf5ff49fb300d145a1aac00406c8cc07d510928f764b067a61a954ccd99f731e90a154563d6f7ff0c2a539f21c1620975f71decc17a0f52c5cf4c02eab34f7733fc14ed2f6829580acd240e1aeaa0630c110597c9863b49aa1fae6b489a3b2b1875c66de3e4568a176e30c7e54b53f019de3bfa5e76b857cacfa85948b24c
+Qx = e5c8fcaaf51ef1c8b53c9978b316194f8e976fb836ea559f
+Qy = 68a2a989d96db13fb87f55a44c037e3fb8d21d3966338dcb
+R = 6a4792f94a5d2ba478703c8bb42514f7f2d771422ac8ff6b
+S = 882edb5651224887207efa169fb8fcff96a50ee5165c3642
+Result = F (3 - S changed)
+
+Msg = 7745e768f3e70f180efba44948af91bfc35b2e84414b574dd917635b215b44749c13361092770bdba88d7b09c2dc958591868480c4cce117b7084da8677d9a469d27e9b668ded176e13958ab1ae413ee1b1b4ee355a5b07cd36132cb921e5177a79f2d35323634bc102459af0786cea1d6caa215f5b62f49f5eb9b453457eb81
+Qx = 722f246e140ad90de47f246b16ab946009a9905bc0d04ffe
+Qy = 6e39a7e61e420c5260c82e45dc1608eb559e6a2ea0951522
+R = 41bbbd31d210a844487024060f769e2abd9624da50fdb990
+S = ca868ce943762770615b1218dd1b21e3d2cc93b5e97e2479
+Result = F (1 - Message changed)
+
+Msg = 448b0076730e95aacf91f1d82764747d9a5a9accd8327d6d5bd9338c024a2589ad09f7216bb187ad3e22a7e146952d77fc09918a159187b9e2d8e45866f07a0092c7484a47915ee4435959d5e6662acfe1290b1ee6229f9ef23c05a07ab8a1a6e06b07a84c20001d49ca931641d68f7c415902b0b2213bbb7df77dc2dead0d0c
+Qx = 059b41befe4d089dd852fbc567806bd0a43e232a2ae0922a
+Qy = 6279770311f4b57363ef27adf7bab7f273828a3a4c93ae83
+R = 07e81b35313ec53c627d1d1d01bf6fb9efabdd6be58b0b09
+S = 89f5ba7167373be6628ecf6efe15f4a756b4d829f9e7dd43
+Result = P (0 )
+
+Msg = d140e1a4d5f92a41433cd5a5ff293740943ea700f07e2e9e3e80502bae76c2c4115de9c3d30dcc1e89ad2fb41f18be09124e9170af756cfd9698a077e5f50f205b37e3919da3790846a10c1ec9a56fa6870bee7f6b9ebca0a60e085b31edb0884726196aa1945c8f1a69a8aedbf5f36a45c9b6a31f7dcc720c6aa578d6c538f0
+Qx = 85f9d1376f78a82b4044fede433026876ab2f75312132b77
+Qy = c4c6d34efd2513d3fb98ce600d6375b29ab606e6b3f9463e
+R = a6c86865c55fac4945cc3d37099e8c575fdf963a27c780c3
+S = 765e85a17f07b8eacf958057c14fa0e5b954726e0106f41c
+Result = P (0 )
+
+Msg = 4bcbaa7bd910e4fabaa93cf5b1fe486783b9bfbe4841dcfb2416704284d27a35392f876d32b852fc6c57370bdbdd4a702ccbd8394b361ddde2fc87acd6b35e25f2ba539a0c563b8b172e70dd4599cdb268264f63c976f77901389d38afe901f7f03b7882ea2f0a3e6658fc9f23e551954fb7aa406e1b52168f73ce157c654bf0
+Qx = 01f658da9f2606c87ad252165914d8b5d22e1f0510cdb6c9
+Qy = 22e8bd164ce92dee67c5ac6f59bc7d035d66056249e9d52c
+R = c247339c92be20e85e1996be105abc5709ae9cdf960e9c34
+S = 5073b70b80a1306c86967619fa4e25462975a25aacce23d0
+Result = F (4 - Q changed)
+
+Msg = e7d491b751e25a6aa88274be09df04b7c16f9a8b773985c21222154b8671ac15eb4c38a29029695fc115a8b4b9a31cf248172b8130de52cd724d5a0c7e893ebec6c18476632ee26a3d0c9792f645992598107f23152bbb47b4879d332ad662762daade9ccd11b1d224a51250cd156e9f048ce3cdb45e02b3ddb8daa6c9c27e90
+Qx = 1ff048bae5af17b794717df4824c8f077ee602ae03e0c0f3
+Qy = d2ee41f4ea89816b8299c5e7cbc142d5cd212411c28a7ae9
+R = 85cf87d8e26949500b3a494e726a700fb84ffab30448b8ab
+S = 5800ab6761708108b192b0e94d21856a87ab576bd58fa4d8
+Result = P (0 )
+
+Msg = d7d651cea073f94fff84fe5117a8154a9792011dc49bd1f0edb9641fb4597c2b2a629d25061f98e6317e0a075ee9238fd72a056e8135b42dc90e6ec06d12956ebc9e669bdb2e89cde8fde759b06d0e9df23f23362cfd002d250fbc64f32cbbf2102180611b92dba6d05661b77689f0506978a8f8f0c3a91ea316b86ededb44d3
+Qx = 9903c60be9fd24456a28fb3f42a9ffee14f1242dffc94428
+Qy = 80221d3994c35fd237a088f61abbb1ff21186ca84ba60337
+R = 35fdc9d4f212103e5c6284737e54bd6dd392cd03fea0aabb
+S = c29a44f08835e892179413c5a1edb6a3d0c1b9312f201175
+Result = F (2 - R changed)
+
+Msg = 89c87b4597f226458b0e688d06ba9e1743d5044275fbd03a37906cc062e9c24a2674867aba2335cc4c3780e32ee2c96059ef6992b81667bbd32666586955664343fbd6f7cb9fbcac9c8be060058d1437604e89c08856063ae3858ade95b17a53c299b8eafc9549f3bd964f837b657071c40abc44c0d169b6c7f228affa458507
+Qx = ff26fbd1e86a6904de3d8e2a5ec14c46e6e2211fd5343178
+Qy = 5579caf82a1c9c435e34266ece22b072e1caf388ffdf31b5
+R = 0180c5766381598fa484401ce3e6a751a7ca0121dc6512ea
+S = f73e518a857c88aa2617d5f8f3671179a6ef9b2476837c2c
+Result = F (1 - Message changed)
+
+Msg = b40ebfa518e173da4494c47b2975e8fbe2ba5f8d44ebe613af657a8fbba8e241393a547712b944edceb1b5cc66c4be1742bcb9127649089b46e1adb9c54b891b31603f2a7335b74c9163e69674b03d52e828cf8f365d3c4345d5893d1fc5de9fd008dfc40ecd49b54511d87badb407567532b17b3f820cf9710ed103808c700b
+Qx = 8d936e46f3b7c3cf11a8d14c5c5ed3e158781619090d0ce8
+Qy = e0c22d973390dfa002c223f6e29aef2e2899fe92b74f2841
+R = 79e347e5c0a58ec86282672dca2bed3b179adaf80b790c4d
+S = d4192c2f17daa781e3abe65a2fad6bf93676ed0237d7143c
+Result = F (1 - Message changed)
+
+Msg = c24f536aa5768a8de22ceab1e133f463c4fcbb8125fb2328d555720a8379f96c4381e08980b4cb1ccadfe9b3b07e1d7059ecc1d5760d62b0db7d82982248667849a3ad584216c9b5734fc49220112be8476a27e5b05c675e17222df28adec6b5bd54aa8885a51578a4ce0a63c1be19f0ddad798c174273e93e2ef18263def337
+Qx = 82d7c815f6eb67df4085bb367dd37cbca765ba8dfe53766b
+Qy = 6a775f59771c17dc7913b99d1e494011e5f70e07fac5391f
+R = a2313ee8296616bbf43fa6a4cb264527e2b1c6b5f1edc56d
+S = 99e28bcce86207969349d3e5dce69e15e6676697176bca99
+Result = F (4 - Q changed)
+
+Msg = 50f1fa39adf968e79c3837de5655cb05333510fdfcb3b31d108989685450d56ef4e8e4ba6638776458df27003915fc481d2623dcbbb819d467c314a31b62d2f7d0081e3b664c581cce759924e3547ff701cf55c49ad506735d1cc4e01bf282bb74e97c0a60f4404c0e9198e108d2fa6282ab5293dce8675ff3a29b29bd91d15d
+Qx = d66647b504641814dc4799f3a10ad87b732e4b21448c3165
+Qy = dea92efe05cbffa93891d1bcf1c7bc66c2f4098eeff9ab56
+R = e926d720f48877191eb1ae9283259e16313d1c2cb805c196
+S = 01339d3bc7a7a21cd6facf352cb79320a4daad7f9a4d4170
+Result = F (3 - S changed)
+
+[P-192,SHA-512]
+
+Msg = 522b006f47a4448fb2b9ed691b9ad50eedf1b427381ef2b7ac84c5dc1e0b5751936413fa95ec474f19b5ec704cd02f5c3320a05c24556bad2ba91ba4047fa4fdfabfb823aa3e3b4b2d7f25887a6ce70641c708e47a2a6a6e5db88e7dccc37dea30c51b3943049bf49a2b57618ae885dcae2c24985f1a72ffb89ae00a267cae0a
+Qx = d008c455eadcdb98234cb6ad2d9876b82c5b0c8867ba86d9
+Qy = 32c009ec81f8eeb99859af65e246d089d3a0c0cdaecef798
+R = 79f619e30cd68028263f107beab00ce2375c570a4be16487
+S = 82257c9eaf1e7ace39e2804e535d7df86158cf1c40425f50
+Result = F (1 - Message changed)
+
+Msg = 03efd1c7aeeda6bd391e1d9e2027a804ee217cff480e7ead7230774b12588c3f3464fe0ddacffc46f59af9b8330cb736ab7d73f96015a857afacdeea5831ba185c8cc21ec379ffb735b87a4b1332c3d5b0fcde4e4358275e5ccaa71319a2e4ccc13549111996988a4c4106b7817f7aa715cee1b83c77014183722d5755e1b563
+Qx = 28f4063b8f808a9642f2b04f794d61739b883897495cf057
+Qy = 9be6fde04d687ea2778f845f881b059488f916c3218f42c9
+R = 15f3e034340d6763ecd73515ddf0b92e383b539c97f78b37
+S = fa77e58f64141876845f438ac6da7bd4bf8dd3097a1f27e8
+Result = F (3 - S changed)
+
+Msg = c04cc98af74aa7a0af13c3491b7c02af7ce2ede05d652601f66a4c94275368551e2b512602cc8fda386d3dbe7c7d686b283cc700403b72adcf9cab1363659516d71d88528342fc8471c262f904961d6704117d20c0f693a75853a31dd4c661d2e7c4d29130f3ac490f505c8fa3ef378035c0e191c92481b0e03f33b117f04c72
+Qx = 8a3939d2b4b4a5b251d383fdb6450d818f6319bd91ee1b70
+Qy = 88c934f7625438d118ec95085851d56e4504e553c6701be3
+R = 4677fb00515485c96be8cd8556984868697edcc1170b2605
+S = 7a5c09c4c65085b9a25d4a2578aac167fe31404cf8dc5858
+Result = F (2 - R changed)
+
+Msg = f7f188240f38a1649324cfdbe91a45bc09655f3c99354730a87392b0af766bac56c5a90497ab1229236a3292b4b4ce5394fc3f8388d825ab842c05ef757631fbfa8f75730fc4b4264a880ae4a4f4b96fd3753591359818d8f4f4408b33e9886acfdcae287adf78fb44d0e247b325df6d3057148c941c8fc78ab138d085e46210
+Qx = dea419cbbb2c7be3b59d6eb4db9ca48efb4835eccf8d0a48
+Qy = 88dde250494bb6b910e979c5fb3a2fc44d41ae3e761fe85d
+R = 302648f3a89aec847742ec72209ac02d6232fe2363f72fac
+S = a1895dd201f022c17cd69dab9c5438d2b25f9368aa8b9cc3
+Result = P (0 )
+
+Msg = a6d2102a68068e2648ded68d12caa6c04b956ddd5c1da911f43741eb03ddd77aedbd5a795fe8c92a2def697502805120ffc11d9ca3a3c64beb8f66dc9a75e0ab31e02dffa7a0876f68ae2932a91c7327d455d4a3441b72b33e4e9a8d2e59b3ca0a1f5924e574039e1b32434e38bda6887c879b62e960b7070c8118fd502d7c30
+Qx = 890d1844df633cfeb3f55324d37d0a8889f938e165069f72
+Qy = a24a3d5e31071b0ad8d77c9345fbecd1fbdafbbc4d015ec3
+R = 41e771f5e4ec73cd72cbf5bdf5bb466344af8a53f883e72d
+S = 7722ad2164d5cd356e395efd26d715418142088e0d04ff70
+Result = F (3 - S changed)
+
+Msg = 6edce3582fdfdce10f33094cb68ff9814a69d7eb38e35685149d468fd8f4206a832633527a7b9203b72b00b420284fb4df351ed146e25dcfe9a2993c35c7f20c046df783a1d5e983ce0cfd0b02cc73a595b8d44df272f1cfd4accf7a6826b988f1639fed07dd6bb35c191a371f2f7ecbdb60d6405b66532bccd3572b8597c174
+Qx = 48798d2cd5e974efa4e4b341f04db38035ee7ca96141722d
+Qy = f220ea8ecae76c7bac076209e0b87bb5709de17f9d02f712
+R = 4b402663499aa0d0dafcb1a7e57c7bfe13b4953875a47e3c
+S = 317e518685fb7d5b801be9fa92587b6cba6b938e05eff266
+Result = F (1 - Message changed)
+
+Msg = 4b34d6f3f75888f88f0d912f39d83d35cea3289e865d3ce5580f746cb60dbf0316fa12a3ed4ebf7ce7e5908f30e27a21426ab1f1cd278d2e0f0b72f36da91efce343fc5f0c71373b4def3200928779832a20e64a6c4952609e3f1ae589854ef6542360edb4085eb7155c10e57103c0cbc785fb7ee2d1bb568b7bdaf2bc30b584
+Qx = 3e64f302334d85913234703619381bb0ee8d68e40334dd0e
+Qy = 38e6ef6fe5c364f17ff3947e294613bd07fd25e46be9ee29
+R = eea898e0fd6b8dea2a316cdd03a2f1a9adf0dd5beb004372
+S = 0bd969fcc0f08281367b0b94dac13aa4737a0861e046d93f
+Result = F (4 - Q changed)
+
+Msg = eee695dfb06970b80dc25e33b61332ba96c673492df994f776f17dcc40c47be1e6be3170b83771a677d2714fb374a7ee373b1633a3e22be19ffaa59741bc643cf854c211b7e3070fcb8f5ee1b605c6c85b6bbc5b6912302d3c2027bfd96bf6f6388af97cf54f279a366cf4a49f9eeae15a91049a57f35aa62f5e116d501b524c
+Qx = d9524bbd5226618b144b93a5638f1fcccded467d835dee99
+Qy = ad88b84962b039f4dd895d296c10776d0802d12c19e5b750
+R = 3cefd5c3d18a124bdcf052219e684cde9c0e6afb0bb957ba
+S = 12ea2874848061b39da617c7ae26edd5b2079a5b12ffd6d4
+Result = F (1 - Message changed)
+
+Msg = 43b6d9aee332c6dfadc52f39e2c66b68a1e63bb59dbd0c375668d49ac16345fb973008408fc9ed8ef7bcaa19430b0a3720d7a4f0c85fae55dcff4ff49b5aa1e7c36265329cbce8c8303969c05b6ad5ff2af0c7509d94a3aa57cd11492b87a4d009cf3fa1ae7d819886e6f6a08ee9f62e5e432f4852f52f175b1c37a7c427f6ce
+Qx = 246560e2e5d4ebd6d8bb932fc5fedbe516159c1c7ee1cb8a
+Qy = 3bc0a5c3b260ffbc7a89e8691a854800e249140767db821b
+R = 7e4737cbe7fb028d44bb77c5d05cea5ca021a9711a08540d
+S = ea0ca36333c1c273c649ab7f8a8216a9da22f9f35fd2ad0c
+Result = F (2 - R changed)
+
+Msg = b16560c4aee6699872330bea44404cd0ecf9ba12fbed66386b78be5bad1db07fc5ce2c6a52cd9e0bd7f240cf75a149f0844d5bb5fb17fc4fc2a8c965ca2b6e3a4cdaa648f3fd479ef58eb71c4ed19de33fb35b79b0956ba2a17e2674dbf054cf3da30d4bf43af0088c584c636bf084ff9c4fed43fe922a9c31a618decce8a866
+Qx = 2d3cffc6aac703d224029d243036cae359af89fb24801481
+Qy = 00346a43ccc3cdcc37cb9b2757d5f88fede01a5ac160f253
+R = 3a844183d6a2a59255ef9105a6b8dbbd0662c227ee04be0e
+S = 4f322c112b5cbdc7c23138ac51fb975cff8277676105e5f1
+Result = P (0 )
+
+Msg = d8fa24457233aa834febf3bb109e6b0f9de4a4e095225dbae2f0f5d14513710188026057480cb30f2c2ee1bef25e86cb505128ac57cdd61c420363cd44acc2e87741afa74b1a239cc0871ee2dbb77609bc7ea42f883afb9088bdd46b3b887aed38e85a1a30a8b7d9f87cd17293c262f470686b236190c76606ecc0e94c28b305
+Qx = 74740b536f42018b2af5725ae02dbcecfa05bce69b71f7c8
+Qy = 67246d3970cc05ae53e77edca979032f97969f47a2ed7f29
+R = 6e6e9d0b4810e13502589df7a162557435c7dd93f0ea1252
+S = 9643777c24c7faadc32697e9d61039783974d6f75269a764
+Result = F (4 - Q changed)
+
+Msg = ba399e3d2259670289b099ebebce13ac6e4809ae9f17fac4a1acb4bcff3746152de31d4c197eb814930326fc501fe43270c7482f6d883fad829bb69eb463ea22ac4be74f58881ebe1266d6fa2a3ea67965d2422611b2c4b05fc43f2d4494518265f862063485531976bd6385f4f98c9781db4d0793233199cd58685913c8d186
+Qx = fce011d181c4d3c75043ab6936e2e9a7d6964ad47851e290
+Qy = 71b52d04ca114434be936d9518f05ef9791997e240da0740
+R = ee9a4782853080a2cb2415914dee9bb4245def81ffa83491
+S = a701084db2870488d00a5886f872b81c53552ef31f09addc
+Result = P (0 )
+
+Msg = 048aea24ac7ff5510a055f9e788979b6b6dc9f586583fb3fc6d0829b00fcbaeaef8688d46a97ace68772d8f127c2798d01d33e5affd5dcb12880680631a07a83d82d69eae255284695e7aa0d55b12518ef7a7ebbe13830dd891cce0f8b0eba7f4942900015f1495c0488b206c065f19c2b8fe85cab678cad6dd1f13c813d6b87
+Qx = a18849ec9c5cc10f8fa60ae614ddf2d2471cd2ed67f5e194
+Qy = 8a7e1a3741c91db9569b33f826807a072509791915f5ed9d
+R = 828ab4e555665f34c68157a1c8ea0488a9f9fea50fd9d18f
+S = b1b1753159967149f60c9692faa36083cf8033e3f5812715
+Result = F (4 - Q changed)
+
+Msg = f3d2d5b1f472d9f326bba6c1af594179ad3eeeff5009997dcd06209fad3a387b7005ddbdaae95ee0dc8d49e60552d0bef251caaa23b64510b14d2a13bb343c6715878aad13b71ec128a2dd947103117f2b1a1a5861be74510279be6e8752e2a159f25801c28acbb1795b8d12e787db85d1934664594052a7354091c2e5dd13f1
+Qx = dd63ce69012860466d3c65716928cb303bd9290e795d7e3c
+Qy = aa79ced99fafac92050355d6ae261cbcf82e325559df0470
+R = 6e384621469ce1382811d25ca47cd222b1651947dd015d8b
+S = 3b74dad20133a9eaf3e749af9fc89fad2a966b3bfcfaae42
+Result = F (2 - R changed)
+
+Msg = 58f30a4bedb114933c51e74eb75156ff213a6764cd65fff4fc6930879f7b631aa96436a1f5b6089ded7f3d6daadad4f63ac3c895d42f1f030f88adc5590e445998a632a600a70583fb63caf76f74802a3d7c7ee3ba19b7b29b73f5d6af37e983c61c14b7183e5e2451c7350f51e760da3aae1971d46e35386c74a6f0d89e8063
+Qx = d751fbe56dc3c814dc9322c9b4537675c7a3dd00ef48b596
+Qy = 8fddf41a1dbfce973d182576bd673ca9ecc124745bd436ab
+R = dbf13e2cab03e0e3f9c5073b94c8957c8d4f9007065a5eee
+S = 4b388402594f5b1dcd7d9510e44dfd10a385cdd944660e7c
+Result = F (3 - S changed)
+
+[P-224,SHA-1]
+
+Msg = edfb1e8f6d45345d23b194f9b25c4ffdea45277715363fe47b964a52020cfc4e2021445ca850836340a2826efd84ed7424a2c09ef02871e5594dafe25d5631d6b32c385d9be2017015c17fcfde20a9cb2ba2250ca356bdec1770c810c22c647e8343f3748087759954258d856d6e2e5f13d8df4a07b3ea036cbf215c3099224c
+Qx = a100d410ce497e991070285c439cd361a1a9c6c973fd6f5e1ba9ec66
+Qy = 0a8c3a2f909f212c84441b8c0030529cbd731304d86f771d89d7cc29
+R = 1bfcaab01e47addd4733369320364ad208169ffb15e6aac33c2d7c06
+S = 07fb33465e7b7b373feda2ea35ab7cc9477156a1335ecad942f99627
+Result = P (0 )
+
+Msg = 492ca55d9259e7f277871d5380cbb2ef6afdcc3d43c13dbf2097ef01812cf1596294a9c4ebceb3d8879ab10eb767e38dc53a26f7e7cfaeb9cd9662514dfd3cf33bdc6f4050b76ac997fa1ad6b74220bd2ece8d6041e2d0ba58a76fcf18d1ac56d5574bd4964cf2cd76e419d02da74d08ff32d49e96e2e7aefb8b551490512599
+Qx = a6cd3d14cd5eb188a9f59d9c32e93d890558de382f6fba5ff5c6e395
+Qy = 7a76734a0afead9e5e4aba65f1ae353d6445b1689b5ea402de5f9af9
+R = f0f670963c3d2a3281d639f850f3781c6402d99a1bf07cd9f35b2975
+S = 758e84920c1b744502cd787cdd64ec58364ccc6917258a2580097492
+Result = F (3 - S changed)
+
+Msg = f7427ab6ee8be58a40de72ba0080cb12e140832b94ebb75942ec4520f424e363de10a450e56cde879ec9ec14a59976729378a56fd85da39b23f709f7fde308eed2aa5a4106716df5f2535a1b90da4e21bbe42101a7ae42ab238e5fa8da67b830d32650db6edd570d05ff72a02cd5bb1fd8a83051fd6446cae1b63d18f35ea186
+Qx = f5fe7875a517207f1336ec2bb4fe5cc7eb80ee2b0f8ebeff4c56e620
+Qy = 0b7ac24ea9092d03b28904d89714b517be023235abc9cffa297cf4ad
+R = 88617e694e361d2cfef6b0658d444607fba030ad31fe8dead14db22e
+S = 5b0bf37c4a583dd75d99aec20943ea02617cecdbcd295d35ed01cc32
+Result = F (4 - Q changed)
+
+Msg = 11bf93a16222dfafd6a0d440ae55a7c3e452a7997ff9ab26915ace29fdb43eb3fc7c4973eb134eb0fbab0bd3b5decb349f9a68a5467a028ee6da6e128dba88c0477176ab2e35e4b3f78686006b0fa0d27eee4d652d6094ec883ccce18472c3e66b59184b79d50e70acb15e479e91dac8be2fb691d370fb8507742796f38f131c
+Qx = 8a6a77179ffc0ff5d412cf859cc82aa19cd18e5224ab997e9c2e46b0
+Qy = 3d67c177ca7cc12c7b05a3bf55fb78549ef5400a566efe8ae3580c9f
+R = 107b7442e6569ddde54b5da55a9dac9bd348079358047a19a3de0b91
+S = 92359be39353cb263946294fb728eecf1880f50a43637f391d3e7824
+Result = P (0 )
+
+Msg = 40e373d67cb0adc131ad0889d37cbc21ab60f4628cef59737596c99613d880b467bc2054f5851011a47b561ea7933a0ba8e8912b37f01e326cdea82165d6853bbd82cc28135095e705c83c9b1048d6f715832371bd94d1b59225809495e6237324ab5e9927673b38113b35220fc973f16cd7e2c69b619c11d1f592eb16a8aa96
+Qx = f9f23388d573562f29e7e7c9a98f27e7a1ff02d2d66e177c6506466f
+Qy = 4545937caf1878fbacc34ca38a0e5e1f6ad2b25ddd796d06c8d12351
+R = bc1db32e437c67439c27db1dc607e3c505210c984bf707a8e87abb70
+S = b760f4943a2397311e54e888a1ad379ad9c45d1fd09b5389ce1a00ee
+Result = F (3 - S changed)
+
+Msg = f9000b4b5edc593d1880ecb1b65e33bd011ce1bd64fc6310ee0a29ec2d3bce4dd62c42f66c5be97d02ccf562a2f108be312bd51f7be2b01b508f09c288e411d1b733309d7955c978a65f6ef0a4219d9f4131414226b9b4d8609728c772c0c5a0dfe950f51b16255471437ec73a9c8281d0c6a5cb9d93229c689d60f6326e4376
+Qx = 8781e5a98950092570d685964e9ed27760fb7dcff8d3b6f3c8f77151
+Qy = 9207cef64b7c2ed181c57337001f45f1e800e0d1bc8adac296e454b5
+R = 79826ae5b0297b9404829df0f02bbb7b8acb35459e13a4045c40f242
+S = 2a629dab19c9e5cd0a551a43851fe6d8409469f86cbcf6204b41e5b5
+Result = F (1 - Message changed)
+
+Msg = 882669d8b6ebdd3cba351fe3e3c81b32d168e8a672e087e94eb5942764e2f88e9702ee68ac73300cf68bde9b20e8aa654a3e13a23a07a361f6ae73759cd89e8e9243241c50c55b93b538140361af3c8d9e1e6892a53ea1b0acbb140597b03710e920904849119e62a042ff124c705cc0c8ee55adaa07032cfae698aacb979815
+Qx = 03c78c532b8767784fd45e75027abce3371181f8f54914811588cbb2
+Qy = 166c7b70e98fa11ac361d827557676ec07e553370a462b4fe502dedb
+R = ff18b493b166d832c9c25ee491525e4c188ff2b804e38b5964941c48
+S = bbf4291db484b4e4143c01a284c03543bbdaa2db1f1c571f1e5a5e2e
+Result = F (2 - R changed)
+
+Msg = 6d09ccfbe8d2f193cc86a18b54cf21aa8e43c9f930d411bcd6fa92a1e9689b7cdf2b4accfee9b001ad73f25b285048e2bcedff9f244623d1e7eee1ba3090da00af0c1c84e7a10e788cbf639637a29f6f5d722e633a6f725eb30b75c92a7d9ec01059ac2f6c71e93c967d4c83f1e6386825fed2f9b0f73975fc964cecced862c2
+Qx = 99fab11464484cee96d72dfcf0327d671787a2f6ee32f9b184c48fec
+Qy = fe8ec3d660cfa3f3e09e5cfc2c3298d4de2f464416deb5b4a27ac062
+R = 714c48c143cb259408c04f77a38d6484e788cb268fc9789d5e871491
+S = 542793d5dbcabcebc83a809cca02b8e95189c93fa4e330d66d5a62ef
+Result = F (4 - Q changed)
+
+Msg = 392bca8a136f925b287541605b9e1b1b9f6f3f8df7668d366569363bcc5818df90bd34d60ad58e06f60b54649f2022e7a02cb30cf9341d546ebf9fdde594096b40f0cc172900c6caf76b413c4a49cbe38f91ac26ae969acb3615eadc2307bb9e1a1a7021f32016ed3a79323c69ce4f0baa78d11e456d2a2156bfd7e9e4dd4ed0
+Qx = 014e8e57388eba32ebdce80df60c481e5c7758374f90a92e0a82f1b9
+Qy = d1aa8418f992283c5b6bb0461f05dc9103050dc55e0265e1c99b935d
+R = a159b83e80e656f54f614e8437821bd87f6f13264ac8eca1b3ddde29
+S = b77b7bc8cf374f012ee15f9f9224a46a560a5b689cfc92ca4fa03459
+Result = F (2 - R changed)
+
+Msg = 4e4ee24112a40b75ee1801e66050d7de82b28c7eca99fb5f0f58a06deda310625d1ce0313e2fabffb45b553db6ca710f109b42f10cab843f8b7f8bea84097f3c2bd5726d9653aaa152a4f60bc823bfa0d2e6e39e48a8cbd14973a671f331f6d5b0a94aa80018810fc7a8cd13a48412c716951e8e3047b13258ca1920a52084ba
+Qx = e0b9e3cadca81311923d6d6adcfc326b62fac9c4b8d61c5f960c88fa
+Qy = be505338108f8d3f0ee80aefa304d51dd4a4035477934a98a6111403
+R = 8dba585dc3312056a7be61161c7af8ba8b538f0c125c80cf9af2682e
+S = 1b5b1adac4d66c7045f3f79c3aa154a0274c4a994ac7a093e2482eeb
+Result = F (4 - Q changed)
+
+Msg = 0acdfd131b2104c0d4304b7535490266df18e6f40645260fb7db86952b2fb40500a3aff55643cced61cfe48d5fe417e5f69fc402dbc55f19db19cbb06b243bd90fdc0b88bd1a4193e6b9cd8f936de1eb447a83ac9c98a0b664f0978811ac00d7fdec1637b9eb3b24d3325c9abb7f09f1becea8f3b1db4593ca4758b96b5a9b08
+Qx = 29197e94a3617e62d9999c859640871a4537a073ca4f12a4c324dcad
+Qy = fe198969ac7cbe49df2c61c4cc6fa502c2207a7da10acdccec7b1cad
+R = 261670b09afaeee71c590c5658e3f57d859b18a887f70fdeb90e57ea
+S = d1d12c11cf7f4a9dd015ead4bd245793cb37ffee1f4cf109b7b68394
+Result = F (1 - Message changed)
+
+Msg = 2f10bc907f9c5a3c4da0a3a2dcef33ce6b5d43621b5f97c8463a7315bd7d46ce799a5d119a6dab8812d3791b00c10025c0f0a1c6ed9f1aa97c2ee1caf1eaf4b6ed66b66f8c2ad323422f0a03ca2ae5d6103f6bf85c87388a981a5799e7a4b3019753196321aaa93f84e4a52b2722e20e9ba945c11af4ed2b97f952a2178ae57c
+Qx = 0fac352c1c444435e6aeb1d60f28ac773b0170ae902afb0944ef0a12
+Qy = ac3ca693a7c5347a074808b43edea94059e2b1d0571d935fde3f5841
+R = c33c7a4de313ff856d2f51cd9e3d173bd10668c296f0e6b208c036ef
+S = e562d30822b5cc69713a57ce8c70f83827add85a06c88109505ebf7a
+Result = F (1 - Message changed)
+
+Msg = 93a97bd8466a817495187644018c223a61cea5f461172726667d84f823eedbe942aa9f3d96925a3c83a5e5d7354e38c9692c61ea78bbf4fee6632fff0390741d60663670d2c3c4cc7bfba9c1a2e942ad54af36cbb11733fe4cab60fc156830b91231c6b195554e80a0562ccd04d829ddf85233313047bf2362629a8a6913262b
+Qx = b0d4298e998b7d9d4509322a1ac974c6180956533debafd3d9e7f2fc
+Qy = 185a64ca840d4b6a2800e72433f26dd523f97daadc18d6d01533f0ad
+R = a5155ce53050cbfe84b67d62ce118c6004564087f2fe1cdf44e9c945
+S = b6894b050d77a3ff4d191ddc0c9fc7009a7472e31739949193d7cceb
+Result = F (2 - R changed)
+
+Msg = 736264099844aca80bc72c838372e3ec12729369ddd60ce832994b55e8aebe4426db33618b10afe54368c58efa8348ecb9e790a4f07221336dd05f8a7ef55d45b4fb0c9ccbcee7299d43f9713d54576b7a774878fc8d5252b323d9cfc9af21d750e9b3efbf7ba7c81e7c33f25f6b6464c489b19513301e81140ca4af64f2a56d
+Qx = 59996a4a06658e553fc2993f0f55e3fc8ca2cb52d30f882a37729be4
+Qy = a5f68f26ea6608fd1f350d8da7c187c7e70f23363177a5aa41508fce
+R = 704ef49e0a43c61ef5b325899acb9d12287883a849976c8b9c950634
+S = 73da6e3a26d5c512405fc09fcfdf650dd8da748e6c3dfc05032d7a9f
+Result = P (0 )
+
+Msg = 888dc59ddd83b86f2f55c7e18050f06e1829a117e0447a2ecfbdec0680e6ef05461b4ba7d37555284ea63b02c4d2927f8737d3e659fd9f94e273c846f2524fd9adfb5b6ee31ca427f36adf429dee9d14c56cfa83bf9753b97b66659b61fa6a8a2beca250b279c1ce9721c8b0636cdfa5bcec493bc01e5c93fe9d910396d8a395
+Qx = a0cfdfc5a096b0b23ba6748ebaad17e60228b204aebdc01057a7154b
+Qy = 9f6bd5369d21d88d7b5c3ce221af530fb9a8fb91e751cdb855ff32a6
+R = d68aa9048e84b8653b8ff3ab31bc73884c6ac7df1fd1bd3c38c16b0d
+S = 38ce58afe5fbc6af892e06a4ddd978c745d5ec700cab825c11dd8fd1
+Result = F (3 - S changed)
+
+[P-224,SHA-224]
+
+Msg = 2dad0fdc03e9617e0de30b3108e0ef155e4e6c3169cec76622c16dc55fcac39a5fb002472072754e7885cac0e318b3ce0588559152a37e6e55effb6b8e19c45ac8aaa91fbd8cad41fd2a2d5af03841ba13f405b20a04585ac0e456502b9686e72e87e8ad7257d3d65781766c3752c6aa9a24d6f49052e753e2e31e155a35b7ec
+Qx = f1eb36b3e1c96a18d87878d5fa8b79d77afce9d2ce40d26199f33482
+Qy = ae819af474f3efbd62401a407036505c5a2d60449274593865de3374
+R = 003122e976bac378c06ec95fd73290b067e7ff022d23493c40663ec9
+S = b99eb4220146a282c7a34f98a9a4fa38ed3f48ca2c7983cde2d3235f
+Result = P (0 )
+
+Msg = 26b7a6da0a0099c0ed3b297e994765cee13a77fbb5ac13c5cf3cea4ea7bb66ddcc58f85e7b65787a40df26a475f9e47b1ef92db42afdb3ad37a52d773c90f2f0d6e0d2549a2ad5de26bcedcbe6b7629d727216b89928b873841d31c7ffcbda4bd3055eba8e66416c3601eab01e3ae8cffa20d9a9e79eb31cf1084354f0a25f25
+Qx = 3bdcc7c6112cde3c0522f1a4863f1d7b6727c5bff67598ba2f1bafc1
+Qy = 47acb6b254e0e8747e0039de471d0dda443cb09a592c678717d83200
+R = a5aab7768f549f8fe3c7e650154c865b71ea5089bd6303bfdfd19316
+S = ee4989c4b96bcc802464fe44b2adeb1b3506755a3f4fb3f9252bf21b
+Result = F (2 - R changed)
+
+Msg = a8423353b1fa176490dce5e9bdfc412ee795df653a746f04857ccc21e571037a3ec5ef9f89dcc8f733240d69965d1f7ad52a1a7b33692b5792f8ffc2b168efbaa87e4a5ee4ffa8f627a61f64105bb1f870d17eec20b6ea66719fde5659a7e6995985e38eed976c8442594631d345b58c084b203ce3d1869c2856f861d342c509
+Qx = 6d5bacf458cee3ded627d0ff14fd2aeb54fe1455d6daaf7bb43faeea
+Qy = caecc8d3967ca1c8889607e9ed975b8a335a17c0acbcfbfed721ee1c
+R = 80e7024bf30ecddf7a658785ae51cd6e5a23963c89ee96a82346d889
+S = 561252dc8d9280fc54da0046da494fa5e4b7aed213923e8b894a1ae3
+Result = F (3 - S changed)
+
+Msg = e9859a4fb2fe008ef14e8eb68dd00e06eb458483e54c3206385faabcc036f6e5aa5e0f28c0fb8a6cc345a0842e4cfb3240e9880d40665ddb75e893e9148cd0c11667f6abcbab2abfa63dbbc32dceba439a36bbefb12a5b242bda3ed58b7f00100fa4e0f8012f7d17d3e4d3210f0685817cd5584de4ae43655d9389bd70ace150
+Qx = 7f9789c729355516588a5c75cb2cbcf85a14c35e14a5d03b4ef920d7
+Qy = 49e95c49e62dd20f02ed16594f35ebf3415ed50e6efdc0c548101a9d
+R = 3c7b664413c2a0e4682a9d1c88243a96196fbd03f72cb873b9bee8b9
+S = 8f7f81ee9d3a2660ab1d666bac6cc434143ca9b04ff638ca7b4aa1ea
+Result = P (0 )
+
+Msg = 79a8fe06daae39eb45bb989dfa6fd802e4d693d411d0afa264d4717e59d93b042e9d1755f759e92557c397fe3ceec807d65bfca69ffa749a559e9d5e54824d9fd75db8f63229f8c2ad0698c7cc556256042a02884bbe44ff71a54ded2247bd9121242cc2d3aaff5061e8f2e1d56bc5af682ef2739839ac31f6a6ad3ba47ae05c
+Qx = fd3efc7108edbe155adcd8686d8605e811fa79756c7e2dc8c1c04212
+Qy = 59edea73a4e5f91541fb4cabce539afffa85b6b0113289f049ce60a0
+R = 4907884b8b7d0eb9a7b24420f69c58e3a17314e101da0280c0ceb130
+S = f7629bed92e5c40f35d7731912fb45a3cee06eab3d409a62997f2282
+Result = F (2 - R changed)
+
+Msg = 251a4f8663c4b225a4dd9333a173257e2534498479ecb3f7ea7f506d6bcc762c6afd07da938280ac132dd4dfa15d27468daa2a3c0779c29eeef5f5b88cc2333444c5c24a4362c0c5394d3898c4be9276debbf47faa1981b148899ec44fc7a4e9b09258062adaa18248908b2a5fa7ecb4ae0549d4b369ccd9176140f673db8239
+Qx = 8b3f3e31d9c8408a39997455ffe0240fe128a5f1be9b3a33a97b0910
+Qy = d74ac6ad8de2407887c335bd66f684454dee175a2af713bb334cb3fe
+R = d28ae763c22f50ae9ee9fbe5bab682fd8d820b99ab70677cc46624f7
+S = d9fa54d0300a6ac74936e7a47fbacadcbb4b25ae3a5b550aaf53991f
+Result = F (1 - Message changed)
+
+Msg = fd5d8331e5cdd7f205bdf2a8fe39c5dc43c5fd40c65d49458c82c39c779df0b8cdb003b0f54bdaf03c18739c477cb7c0eaa96e658b3fa5f580f2a524d944195b1644c3629f289a74a38d709be8e5d7dbc2ebae309bd0fc9afa69627ba185c9c9358ea772895a2837b950915ba46e88636c941dd1245d4baac6e132e7e09d7956
+Qx = f4fd02f3d224727e156a2cd7543483f3e35eb65219e32c7923f93ecf
+Qy = e7aa734828ef326259f98e0e8c3f30b62bd3295c6d1af2c429a087f6
+R = 9f57e28f69d2ebd96f6d98903156a4e795730e09fb67963771b0a851
+S = 8cfe716488479e04500c8eccdc86fdd54ff00258639f7177169e2030
+Result = F (4 - Q changed)
+
+Msg = 0f05382e2df4484620756f4021557ff5e886ff2681a7c2902a8175a990aec3c3c9846f102deca2cbb192d15938f12f3f3656dc4f8201de114a742f94e79d48191c5080c2321243dbc97fdefc078080c3adc3dced963c67fdcc2f8a6ff4e678cd102de3f083743e82a126d41cfdd01b219b8b586786ea389a12b19223feb1c1f8
+Qx = 0fdb8faf52d8f46229cca1e0f22e869a91bd56eb6dccc547151f9c68
+Qy = 96c8d1946528bdd2c14c3a0a9c17a088d3f0599752d095ba9de9ffa6
+R = c53c0ce7d408278552a5fe5854c05641cbe93b1dc18eff1c68af53c1
+S = be7453a12693ce7812fe58746323882bc14eff972480b49431cb10b3
+Result = F (4 - Q changed)
+
+Msg = 826ca168835f0d8b3005f43adbbd6166160f7cea503836591a34601ce08e792f4efb9a856d88db5f668fc10662d58d5d391fb2ab35c446ef1559b23b896a2943feab303b5fc6b0b730c9a32569abe05cc4218d6bb9b47c33b1a0adc7f4e410d75691717abd395c18479fd3a0b6d172d1e39e8b792e7d1f4319a948318b18e2b5
+Qx = 240431da69703b32ba2ae501d2458b355b66170725806b45996db195
+Qy = 13beb5198ee00abdcfb2cc5454416d4f7c795e97a14bd93cec3f0a56
+R = ad03bdf64e3450407a2a977e1985853d6ea41568c3a394d696de6739
+S = 7b55db9abf2045e2dc7ccfa2e8fb501883c494662d400590c74d100f
+Result = F (1 - Message changed)
+
+Msg = 36806354413189fcc8f2055352feb2920dfad22fbde0851c41a98cf8fbe77b2f5b9da656a6f3ed91b1ae01216ff856e0d7fc0e6bc3788cdf1815b4aad069500ba71bf106aa51f04186f68ac3dadf8b446a3f1c6dac5d4ff7139f9d3ed50f332e8aee278e17e1916a9df165ce7a2ee48333cfaf13d02f0e5939a3c00a6aeaad38
+Qx = 8c80c86f91b1e330f86f5177fdba839e625a27e8531f232efb10a484
+Qy = a24deab8978dfe7398f7a1da0633ff7cf5aa7b7365ce2d840ce81c80
+R = 0c422b292308f31af78b1261d12765cced1cf96a83a6bc3bd90330fc
+S = db34f4462d0bb1927cc99273dc92d3fe654c85a3b53c6d74ed900621
+Result = F (3 - S changed)
+
+Msg = 2f266b2f7e52351c2b9bde5a10723e0a6c06c4f2ec459dd1e71cfebd8873d132c0fd721ab2009b6f7cd0f8e59f19cba0ba6249947e5da6047236a26cd06bf056b6e86440d5fd9189a462f0dbc2c9b2f6c203f6a14d44d4a16731e0ec5fbeb4e4510e8985fe02c37942df2edabe3c76901638d9d847274eb74e1e7740fe633a33
+Qx = 3a5d1b7ee6749630c9619789b256f6bad5bc4b09950cd53b78d5ef30
+Qy = e85c7ee707df680eeb5fd78451f7302ae653f96721443826096f62a3
+R = 671ad280609364b0e26c92b13891f677db7c83499d0a3d7b6d80affa
+S = 7c4b9c5a3937d540ed8bd59e340c13f02313445e06b2bf7525f5726a
+Result = F (2 - R changed)
+
+Msg = f72749aa1af0e818f82dfe5ef75ff693e8a9461fb035bc08181d42f372a69dd88075451f32857d255413923aa5df50f9599611683cc64d7841f8b98b2ac0941ab51c89f58191ddab16229a9716b9c0e2930f9520289215cda715d89a64655b23a71dd778685ef0e114cf952c1122a3fbb40d81ac7554b846158b6ec748257a22
+Qx = 350f59509abc9f7f9b35a8b80065258727a8ffc27e6dac635ed68900
+Qy = 634fceae493b200cc7680297fd940dd86a5111da14bed68c797ef254
+R = 13a302b200555a0e80584e6ede32c0f9c5a199125b219c3e8d0fbf96
+S = 13f1d7b0c87acea6290cd9d36f1820f546f83dd8d7d9abe9da5812a9
+Result = F (3 - S changed)
+
+Msg = e7275a54b159b1084d45a785be5e69f3e0105f730c67940865af20522e617513fca5d1d4a6ccd4cc7828802c17322e7e77548ec724696b1d18eb8167bb62d7d53a8dd5567faa156eedc1d71b1e13cd2bdfa376dfb456a9851467a660a9993ed5be5a72ca8d44eb47333f0c42c3cf8dafb17249a1877942ab0e40ea36413665d2
+Qx = 1fdb820003a2fe61deef2b68b92ac711abc76200c534ec3abc99a187
+Qy = 32f87d0554b6b5e389311fd3c86825fcd42654a0b6f5d4d5ba73031b
+R = c03e551abcb12eadbc291b2d5fdd53bf725b785933e0766969f0355e
+S = 94826a8753cb949e0199be3220b4f90318f1c835cdd67efc50df7fbd
+Result = P (0 )
+
+Msg = 2ce84eef2991e5e467471dc558cd3fe8d838fcc47b3464a402d4d26b20fadc7f2d3c58b4b00b9b307412bfce55e31952a84edf19c21fb6d978f5aaf0db90c9d90519a59e9e8990874f65113902d89141f7c849030eecf78065344240609002635d9718e658da3f62783b32299b54c63656da3d391cd29a117dea1109f0383e29
+Qx = 208dcc6c87e7c38bd914bc9b350602ff62ac62fa4fd633c1af5b8cd7
+Qy = 0263587c7692c8be1f78de88ed6dc99ce1198ecc53a77ae6cf98a323
+R = c12d3b396e1a894dfe4a28971ce4983547596879956504e1a3aed75c
+S = 067b729ca23be6cd520fbe9b972b9bb3d00c9ee96832a5c35e20e0e0
+Result = F (1 - Message changed)
+
+Msg = 1dac9f1469ab84155753c7fff9d1c4e531aecdba9f9e10c8dacdd74750cfe47d498920c8c9c187de9b31deeeac09f735d2ccfe64b097349b0f3b870973593dfcab84e16ef7e6276f2c45238e49a96330a2cf7e8e5813c5f9484356b9d72d38e7c3e6f87efb7737ae1be70ac315d9b10758c40dbf43768dab9374116f50d8df6f
+Qx = a66a652fa36413dccd72c83febedda051182dc5758a1466366197f5f
+Qy = dc813a79e0fc647d8892dcf4f2132c90914a520cbbad65f458ee0fae
+R = 809d1b4557eaf36b6eab3449dad56e61d572bd8b63d51b63af1b0bc6
+S = 8bf88226a463606ab57c27ed78f1b71ccd61732fa58b62ee845fd3dd
+Result = F (4 - Q changed)
+
+[P-224,SHA-256]
+
+Msg = 2b0ae1a73f7169ff23d1b8c4804484434f06ca2d6b9e65630bd8c6692b85bcf4556b880bb574ab4f538410e9a535b2054896ee817b8c8412e82cb785444ad042725d01b9ce7dec1a821d9bf12d60538ac93a1b6e1251b37e62ecc15c92b7823cf08f0ca5665fcd84cb2c26509cfec97103af02f5a34a5ebe7ab43297af3ca273
+Qx = 8856fb8b81a4eacd971a954560018f33cbb71cc1fc243d03f63cabcb
+Qy = 28afa26baf31b4d89de1dadd2289006f836f23a11383817ec7e4e799
+R = efccef331805e71bbf876cbbc2342a6bc4508aea7c691029c8396aef
+S = bed544d09e28dbf01a30b2cfb61b98ad6201a9818f22b4f543f3e7f5
+Result = F (4 - Q changed)
+
+Msg = c8b10d4e5a1f5f6a3c0f4c15dc2dc84f0f36b219076e27bae6d26e3b4a414473186472ec793527bb8704f69285b96eaf9473085060603584bca5f1fce4e909203dcf0eb50cf05adaf89804c420e91d1226d9449bebf2e9b3ea7cb23bd094a0bb04b579789c800f58831489d25179db015d751e470c0b21c7ae03fc0e4a949970
+Qx = 34c5ff3de565b85bfdd9f0a8b3fb0d46f924c57b276bcc830a1ed580
+Qy = 609d22200ef38b410da77f7a8ff2f58448188042978fd9ae1b2b4477
+R = f0138024fe0516738f3bd0e0fec10defaca8c3b89c161a77489cf2b7
+S = 4ae0934266d9e3d64c2a12f546b132ba0f33ef50abc90e7ef5974805
+Result = P (0 )
+
+Msg = 530cb88a9204aa1eb11a100edf1849d3cde94f52d03b5727cb6cf2e56647e61ae933131fc7017d4d1176c5fd637d40b93e04540ebcc24c429115246d51b412993444800ca5443bbfde39134e97c106c48a4f3316f5f4d9a6ebe134a10eef14ade3971d7c37e9331a91a394355c9521c415d03c550e28583ac95c06fc222c094f
+Qx = 465afb14f4bf85022ac1f635f46c0b2f6548bace9352d32f74eab012
+Qy = 036371a3246dbf1069d2d268ca431553d1f2bf0181225145881b7be0
+R = 9bcd57a2fec2518903e4b13dc0a7b84bafed5c4908546e94ffae87ed
+S = a337e06582f6b3973df38b93a0fb2a63f7774b62db50dba557e5cfcc
+Result = F (3 - S changed)
+
+Msg = 28cc72daf7b4ecd0f2156035576113279c8f80f07e9ed65786d2bba896e4b5f67a08a8beef9150c9fcb97f21b25f692a19f8f68a2ee8a2446181394f3f0acc5f3698a9a89384e7b05dfd6b7f8eac214447a4a6ba8fb27756d70b34ea2d0cbee9aefd9279824bb33dc15894fea29e5c84b3281addea013d221bf8e5cda1833a24
+Qx = b8b7f923c05ec95ebd484db7c58d219cfd26ee6b66149631f25ffe4c
+Qy = 6bda5f4f988784555a80b5494eca51ad2c7f88ce94d2090ee0c76fba
+R = ce4d86bf5a7543d1cba8e4470a297e9a48d0096d7788c6284b1c0af3
+S = 229eb0636ee62508ce3719396d7577ed892cec70a66857fdee0d1fa0
+Result = F (4 - Q changed)
+
+Msg = 125092718c72614452a7a36425b759243d6d9995776bd2d85c7eb1d5f53f9293bd1d758331dd5feacd5769a666e3b284326610500c75345f20327689e21a37721d31c6c981372ad3f3ce816b9ae58f3ae9acdc47a8abd558b6790bf75d38b1db2c20d3378c15ef98dd0af35927bfc000a38ac901ea1b77868222d5d8de1871bd
+Qx = 13e84ec2eb993818d7d78330855ee2fbe8ddb548a5e4198e2087b3b2
+Qy = c95dff249e10c506fb547a92ade53c61ddbb667c760e4127a1a7f806
+R = ed26f00ed696e114305c546ed04db5fc35efa43059c0d8bbcd418d0c
+S = 6e16efbe9501e3055d74966a49232cd76b5d1241468788b4cc7378b4
+Result = F (2 - R changed)
+
+Msg = f883a957c5a3616645786844de4b0befef1c08539a5cf52de2e50934c5b01c0c2c5b2ff9fbcf4e8c3ec50dab9afd3cb6eabe231dd0af3ae0754cd7976e9c8ff7d9cb3337ad535e50e50ff792d4d50a455d6ba857ba8504256626b5f28109fc57af5331b043e12cf8992a73d7f8a1f71eb9e7c542f8622c8629b9b18f07adfac1
+Qx = 16c23c93699cf665a5da8b2d4baa72c36158d3433b1b945e47204b0d
+Qy = 12023703e1b59ec9054ff22d15567b9f74058b47cc13f2ca08ab77c1
+R = ada849b673a1bd2949a8b4d8fdfc239ec53524a356d37da3c9d17ae2
+S = 698de3a3d8697c2e8e5b2c85fceb8796750c5b44154f01ce86d99e24
+Result = F (1 - Message changed)
+
+Msg = 2346f531399ec2a809645ed85ef7026f9387afe2dc3daa89ace4954061dfa071d8e80676bd3a83af54920c3546edb91f72d0292b0c782062af5c52ae81d14babe9bfeb26de723bce79488495321ac0ac0e00f121384edfcf4e6482b866bd784425aee5112a3d7750b87e132b2e895c74aee182f82b73a36c5de5ce2c94064146
+Qx = a580f9a0cd15abff8e1e712f16b0fd4142d0d773af3c657abc06c2a6
+Qy = 22c6286340dc072e64274209eda60503047700571caee64b4a2306c2
+R = c6fae06274dc052e482102520b49d4ccc4cb7eb8a3ea41bd3680ddad
+S = 50d66b75a2bbd0468be1f9e61bfda85b6329505b0134d60846cbe4b7
+Result = P (0 )
+
+Msg = 092124dbfb916fb529166b7bf32a5bb8f60138f0ef03e7eae7d98819b0f824e17564c4e9e44c58e7e36f58738ea5296721054c52fde1bb575ac48c38deca47fd6717628fef8af57e005ea19b6ce2f3100d2680b94bf53dd0e853ec62a7cc13de51d9b379858ad0ab4af9642c3d59e722f88503a02964570e0769d6a054370a7a
+Qx = 0b4fb6fe5f6cf6adc7d28683628d4b9c569d21d2397533f5bd121a23
+Qy = b44d60a3414b9b7b6e4ad735ce2f9cb05593b0874ada5e65acdead4c
+R = ab5ac2039b49690c6436793decb1a6a58ac34833a8091005312a93a7
+S = 98fe955cd836501cef78c7a05fa27edf2fb3afea80990028ff64e984
+Result = F (1 - Message changed)
+
+Msg = 59f731d3e4f276440ca3376ad71b23fd92b71d802a92254eabaa5da196c9aac6cee1f396b72f24ff2c8612534cebc1b154673a5964109d80b8844e99971370c478bd7db7f9f006715f6209361dd7f33cead36c74652850bd1f5b8bbea5e6cedf30c63d38a890e8d5c985057857379690abfa6726e588b61506cfa77f541039c8
+Qx = bae2b3634c7854c932551ece8dced2139a51705059503881a9239c78
+Qy = 094d5e455bc9296202618d7022512b0f9ce53d796c7294e6eb076a29
+R = 2fbdc7e9e98aed5dbbcc5b034e17a95209e2fe1b01515426b8b372c3
+S = f2b19226528f10be6ef0d27ec3703db690261206b7e42f93a691192e
+Result = F (2 - R changed)
+
+Msg = 8c68a69665f640abed4c56656a5127b77708e43d1cf922d52bdfb94d71b6ab3cbda6c5216f1a8559c780d9313ece7cd9cd2535f7342b6f45c0f84e55c630e59145f1079817b880061592ef645b9efb7c29483a9548b5ff74ee9123e872484232c16bdf6cd3c074e8bc617dab26629b3eeb9bf8fec2970cd467caffc1c89d2a3e
+Qx = 49d9ff4f4bbd4320b6806a7fbaaedd962283c766a6c130e4b62139dc
+Qy = 06dbe8e7fb8fccf9758101ae46939c6fd4d3afc526ba6c8156c6b013
+R = 2d83aa59bcfc8a0237884826e08dbd78a56733598e379f2a9d51e9e2
+S = 485036c74618d0e665775fbe2d614a313c550f9826b955d3e5636fd1
+Result = F (3 - S changed)
+
+Msg = 57a2c4a14a3633e06077990e53e5f3af5e0c7779974d2bc0700001e5f43b5d9fda167973a38ec288bec26f8de3f7a601d1f665f854256059a3ea07e9213afa3039987d8501976b31473b434d449850642fa89e9913cd1ca445ff3d3e98936073da31524d265fe0415a96a39f0ad920ef60de0e83d12a73551d23b5e0474ae367
+Qx = 78451cca49655978b65d8ddd45ff367c47f321f5d55ddac7969ab82b
+Qy = 25b77f820aa9ec93ec89d7fc84285f3f3deed496e0cd3fb9ee4a5c99
+R = 998789490e008ed11febdfe2981a55c733eb9739d7f37fd5c2a7ec96
+S = c3ec8afade81860ff23cc1e7d759d32d9a5775886ef17bfb719df4aa
+Result = F (2 - R changed)
+
+Msg = 2aefee3eedbee09edcb8e125e047f0470bf50ac140b35e14b5108b4b227950617d01ce8c5177b3e0c60907c6100a7498114209e9c65a734bae3276a9a52d9c30e85446f04bbb2636b3b96d30a5a8455bdc90fd9f90f1afa8d943518e87cf8c378828fd972cb5b7cb67746b05fd1648ccdd6bece5b75435c4647efaae935d12dc
+Qx = 18ced60b7fd9ebf76c3aa5976dcbdef40bd3e36033c013553043dd84
+Qy = 30398582dbd2004064f8055e7fe0fe8df11b2c9d9e2931ad12d09628
+R = f880143960e812464810c175001b5d39592fe63aab544deb9ca301a0
+S = 1e0657df071a25dd791264b411c8964688f4fe17ce024e659836ebe1
+Result = F (4 - Q changed)
+
+Msg = d79750680a4f6864cceb1e920b42424702ceb50d3a5bba9589f34f91659b4b366c4b332587363ac5d9e27431c1c379f6bd26738eec0f24b567b65a0147fcb6534cce0f6a30a5ccc277a1a34d4cd5d6d2034fc26a3d9c4e2fad5d388cee9ef0f895e8bcd5572459065079a5b6e954a19f621db3240bf6dd89368887d691244aa5
+Qx = 5d67c1fca848ba7f3d9de5b1894d3993ac4ebe68cdb0b49553b3b0e9
+Qy = 07c219a8323273c81f5694306d0dd1d133a49efce5003bc90f05578f
+R = 767cb6b2efa7a40739830659b0cc24fe3de771d00104b3dcc0f640bc
+S = f2e7268bc011d79d33f3551d2edd3c95f324955479b8e29e8aba629b
+Result = P (0 )
+
+Msg = effa3084fd4887512050c276441c4a6d4cc26e12135f34057d51e23143d8463abd00e7961fc17bfeabc2e759e803f4d0aa8ef2d390ab709e4c08d215028ff6557a76e5a60f8c27d5879c704cb05aae46b1bbfc4f4016aba8ff562840b59b2183dc21878ce2402b98d35564e4bec84f6fe699fb5a399f5cf357a5980f0c28f579
+Qx = eac72b399cb791b3ed25cb0a49eb157e69603197e0327eac5448680d
+Qy = bdab3a2270066e74e8210eed7b5d43fba1e26845b6c037a8a7e2a13b
+R = 55485947e9e3c194a29c8ecaddb18eefd16fb6919aeb0bbbd8c12369
+S = 6309a2cc7fdd9eccb32b86d5577aa54ada79899a9645f2e299630d31
+Result = F (1 - Message changed)
+
+Msg = 625a25287c4a928fd34f138b91fc61dc5b6fc73416c77cffac9239d85c98fbabeaaf75e4534ce486cd700c69a6361c62f52d0e8da0dbc26954b63b4cc10a8170e9ebc1ac69ccd399338120e7a81ccc41f179fb92279cecbb6732b1473cd51758e7296fffafc114071c11909dc456b37791e62ad0400e142bb7df7fa6c3862d07
+Qx = 17f741267bf3e8143046707d41eafc9555953fe5f57d6c035452b232
+Qy = c667554d9a55fc8ab1062203dcbcd2bf9769c696a295350cb28aa01a
+R = 57408bfcc68e60ad000eddbfe6eccbe5f87b98c95de0e0a2e065da92
+S = 51249bddc149f0942be001b2f3d6f6d17a0cc36fefce147058944667
+Result = F (3 - S changed)
+
+[P-224,SHA-384]
+
+Msg = 3571050a4f57432393c59b90aa8ea1cc545952ae5ba682d26e53bee0c988e6dbe2be0ac9b125d6b80542f55aa0368f445efa81da7309883329250d37b3a383c6327e473a6f74c952883a0e5d7909611daa7d56f7e0065fa3b535d4415df7c11fe6105adf8a3e846167b1a61984f79cf6f02306bb1ca5a20f0934f7b16706544f
+Qx = 3297edac34cb802df263f8d366f62a8b746c316adfb1c84a1c79c58c
+Qy = 79fe82e87ef5879c12eda6adda198a662fd77afa6a1fb5696cb7da9d
+R = 9993defdcf83965723c03e04ce6c33b3972cef3c449cdf1bc69990db
+S = 553b22a4164549f16aa1a928eee74548fc141fd3c16f213318965974
+Result = P (0 )
+
+Msg = 9ba60dc6e2cf092d7be9aed3596d6303d2e5e07fdb1c7cdf1d7f5de252d44000572847e49e50dbbe4db545a54d39b466d0dc8539887fd371ed23a4e6370577594f119cdace807e22283f8d036b0732fc3e8cbc5c4589e6c1e07e2dbe6b93fe79c8ccb5e5d11d7e49d03bf3d909754771a3c2ee23fa434574b4a91c0b0334632d
+Qx = 2bc010527ea7427cedd213aeccf0c62dc513785888c6373740139d8b
+Qy = 2e9eb7ddf027ff7678ca880511be147098b34d8e77acb4389fbc6e50
+R = 70a7cb04295a53b4a3a695ccb5d87856fe9152fce11987d4c43207bd
+S = 49f4094368f2de9327ca2913ef940e17c5801e8f589413838831083f
+Result = F (2 - R changed)
+
+Msg = b6ff3652e52d108a7592b3f0518d9f4533873f5b6239abe53a1b31928ff210ac337fafd96c2e804cc4782c1d1660378d706a91a9cb7af17226319a2354dd7b151d2103daa6bc6e1d924cf178b88a2b334b74f8a70a2318c595301cdeef883187d4aac43d60040818ba1c846524f7c79c48d8702c2cc25aae2c58082dcaddb03e
+Qx = 55c6217adbefff6e21bfb5d1b75213ce7b20c900d514ee094f27ad0d
+Qy = a68ae9f86eb9c10de3e7d9b03868518f33f571f85c3529d2902575d3
+R = c073fba87267b45853e693910c1de791908ca7a25c1716ec2d3cec71
+S = 6138c86daf1021ae4af0faaf0abd5958f93944d5b0d82c40214bacca
+Result = F (3 - S changed)
+
+Msg = b80b5bd76363deba633311a9a10e4fbfbe332291acf309de9e2c81c678184691e1d3af65af94f735edf655e7e6ee8668762bbb1b32d322fe6b63d27a6dbf726d7f9948ddd90096d0f64de96e5219f83126a98e32925845968863236661739618252a3deaf67558729cf1e35f260daba73d20a9589d3642df95e3c3cd50f07ae7
+Qx = 4d0cab0dae88fa0cf53a2a6562934e0cf0271cc7fe54a30109a232be
+Qy = 70835833cf9e1f989a18d419e7bee9eb5cef1fd145cf62c4411c372c
+R = 3b8548eab4dc123e236133d826f2badbde96f92249f456e33ccc9739
+S = c82b2e41b9e2b21594cc03b1c0de216f183403c6025e18bb29bff421
+Result = P (0 )
+
+Msg = 51ef637af24c3b1a8b4f9db24fd1c719c39e64f916002caae973375771b8be0b9d3059ca89e46fb7b9c4bb2150151412068a70f143a83d13144003b06ae8220f24d7ffe081222a6582d3c84acb30e2545a4700a40b9021bf14744997e707f3168e9f493064f40edfb4b3b8f96a94dcdc2f0a5662b704b466ee888ee3239a52a9
+Qx = f55a53b818b3ec4b4402a2c63429c1d78f2cd0d8d202e33812878a03
+Qy = 5a2b1a00615c56b4313828bd70526b12f402df1d40fa4900c994af8b
+R = fa934f9fdb765fabb5693ccb1de4177f172a8de108805a48f4bb989c
+S = 12994f2a26252742667044a01b509b0f315e8141629f760267b850e1
+Result = F (2 - R changed)
+
+Msg = 27b35786b40866c4e4a6e964db74bffbc95b8dbe985d1e01d0235796c3c9f757117ca5b2e5c3b9f4d556e9a4b4c8103d45180b269300f502dac26809010fa249bc433d82ed8ca05e12246b531c1d331c28aa7e2ef157dd94d4c5865ff9e8ac349c2db446287fc4c9e0f2ef8fe6a75f98f9af122de87b0b124c79cafbca31322e
+Qx = 40a5c52dda7de858a2c17d12856c552ab820023336b9b4fc196bcd67
+Qy = 301e5368f59c00f15e6f3a91510444fb75a4ead8efb0778b4419e7db
+R = 0fd8773fac425a2761b954c946020615336d3e350ae40743641917fe
+S = d59f2b806ccecc444f9387f511c7f9926fe7f045c0ea633a51b7db47
+Result = F (4 - Q changed)
+
+Msg = eedc96f4e0e5a5112e807b441c259db053ac60d2147fc613f49e97c918e1dddb13159da9a5baaf236662a8cf5af2283a06784b1ac0fa1ba3dfd5bdfdfd2ac071aaa242e76e6e2f8e869c68de5fad18a35c1b4002d6f48ad85eb4aa6e31460b66596880455a0ca8215acc15915c529f161670b060478cd5d2886ebf4e006780c3
+Qx = 372a134eec0dae3322de8836b89dde11a69e0379a60b10343abd478c
+Qy = 65921970ca8cf5a75f044db0e29802afe1726d18b3e07b61c768c242
+R = be6474845a42fd4e85b91238f1e3ba11cc88e216d295c1b07d855987
+S = 2724242ffb5775f614ee06eaa4c985358f64869ce4ae4bfb16b5271d
+Result = F (4 - Q changed)
+
+Msg = 99d534c64e46c3008474358dee11e35c8c720893dc346bb15eb93fb14ccfd29469922c8b7c003d9dc6a553d1bdc1abbcc5a7f5ce9615bbadd943be0a10ddd797d7f1535e2e9fd95823b258fe18bcb901bd8ad4e969592ec7dfdeb71fa72d49bc6fc049acd0eb1ff986bf45f84515e2dbd9064fa5ee5ac22d69c77c9ab573a349
+Qx = 9ad2cee0d92b00b11157a18fcd752f43e772ede7a46475a50e7ad8d2
+Qy = a6edfae6c5589dc0db6353b8655fe3b0f7dab2aa8400cbbd72d1a572
+R = c31a40b6c245572457a19efac0da0db22b2a0818de716b6fdc5bdb32
+S = ed8204de94f1d92ae3fa6e10c727eea38d0e12b58133fda1a15559bb
+Result = F (1 - Message changed)
+
+Msg = 51305882b8622e331c5f9ca55ac8c6b3fbcc7989a1e48b6b8b2356b34d79bc9b234e5b7d50964d312aa6a6995408f8f6bf095ae253d5209f19ca8c9adf5e16d30e0a382b86e37bfacc92cb5c4be46578a6f57e76f7674502828f6dffed63e2b17a3dd7064bb2e32a42493bc887d5cc271390a94592a5c7bfe494a148cc27f0c3
+Qx = ed071a20d76f81c776875f8d3307841d33b70523ea40abd691d55d21
+Qy = 34ca47d8ba0a984d0d728c4d8c6b9aacdded03c6070616680aac162c
+R = c7a5dce4733a81bd738e0a6e0667dc1fade86db119e7f3cde57d6dc6
+S = dfb7f43343941cce331be27047b131617910f68393630fa53d137df4
+Result = F (1 - Message changed)
+
+Msg = bc60ea2bb76ea1cf892a7dcf93358f01504f874d2bd00773e0d754369bc6bad6b827ec90e4cbef34381d71f91619a646dad6d8a4ddef7e027124790383f85ee7a12dd59e007b8b1c656cbc1cb36e615608877724bc71fe1fef9ec1ef512c0c3612455150ad1db6e3b9a8f79441ceea95d33018f7639773c2367472c4d1d86a5d
+Qx = f51097e1e4b4f3b32e92fded0b4c8b7240a62731292e615a4cae0dcf
+Qy = 0549003f18e67076bc68110a75252072fc29b6d4a336d152dac2c3d1
+R = 6875a118dbf586a51af2212d5f32908c9f31110e9e9a7e4cdf7494c5
+S = 1542ab4260459e82070bbad405193a1894ce717af158daf1d096bc01
+Result = F (3 - S changed)
+
+Msg = 6cb6c545e73e783e9bb03f7febc23fc8b0d2fea207bd66795262dd9f994eb87ac2cdc0597c8a41b2340622c36723f50655686c5dbe651421f8be87d37bea1c50cb5fc76ae502ce7793f89e79d441cefbe378055026cf0642f9384c6438da3ae3bf1b418c998617860700d0eca41fc278b34c770bb6fcaafb484264b22daccf46
+Qx = 5255e4fdc816044389e9c6f5e09b85aedbe1c85b1cf9b7190ef7c2cc
+Qy = 683c8cb6f31e4cc1e2a5361eb47e305d5d8bfeaf94e261a341aedde6
+R = f1b0f8a3fbf7d4de19cc1d3b4c525c31bd97c2e2a94eb8a27c7c197d
+S = 936d3f49a9aa58935cfe227b22db83314ffadcc4751c8e26853d8cd0
+Result = F (4 - Q changed)
+
+Msg = e57f4a280c8aacd5d571b2c39e5c44f19ea4294496dc12eddc061bb283045e2dd46326f833330f3b178e3dce2e25919becf94b177bf3ed54a608f708d9a5b99b22ad7d4d8d4423637ba4fc62f2e770b8544982593c500f8c4e8745b224d66af01147b097e2a86dea996f320f7b6cee321c88cb447933ff746b8f3cb147546d5b
+Qx = 7cdaf519f6b1254cb8da4668a2dd2015857ceec17f838c15d7d34b27
+Qy = e29f80fa4f830af7737126d4454b6498905e2c633fa61ad6acb30823
+R = e640f3e676a11007e73efd00b23087adefc9b9407ae8b79b47c397f3
+S = 66b7860a0ca35c2f1c65d50f99def9f2bfc0a6cad2008dcc38d6b3d7
+Result = F (3 - S changed)
+
+Msg = 43dfc1ec78731cb4f0e467141f46c684f5cc946a4f0a40451d5cc46c549597ed23c44ca468f59815885a50b747b6fd95ea3b76671acaa977f556d49305935a64737f3ce25b4bf970574323fd4f2e9c32c179ed1b38b7232a2ab0ce3ad90c2ca872965cb6c480a14851c0375eb0f35c19792cd581408e5eb1ea4ca0fc297c12af
+Qx = ca1a04f08708ae714b7dfb3db509970d30b7e01be7fd6181613894a7
+Qy = 1d90a2fcda7dd6ce8b207eef48340e58cd439a3ce17658f6f82be778
+R = 9e810ec2a0bc205df6a75bd6410e0c8ea1c738e71af060e2eb271aa6
+S = 9d05eeb46258c468b0398cb6e421149bbea5ed936be3fde3380111cb
+Result = F (2 - R changed)
+
+Msg = b5b0f24bc9515e37fe24e296484ad4209c513f98ea5c45f8e3f6f7572ef78b0d6191517236ab31d25f8b3911b953396ff1bdd34cd5a19b229ea37b6c881ce03fdbd58aeb7e40f180349d119abbce5a2ddd0f73a871b09482c5a2370f71d502ea426d719ca282bbe482b20570c18e58b833df46c1fd616d49bc766504c5559412
+Qx = 558c323d8259e055a025fbbe6ba8b525b02f32caddfd31e5b08219d4
+Qy = e1d6398b1c47132632cd3f3fae14fc3ee3092faa619074fd951a5870
+R = 05d8b0bcedf287a4740bfc548570b1c1fff71058e0a9d88476bbb6a1
+S = 769321d50e34939e622a727855501e25a7ad44ec979985e7389aa3f9
+Result = F (1 - Message changed)
+
+Msg = ba5eefa903c9aca4d3c7660207580c4903f8ed6e10e623d45eb8ed3db63407f6c0f88d3d0f8f2a5b418eb0bbc781e99ef251b829c8cb1a408dd3cc145c9be054238f9cb8696cdb8f640cc19d3c7c1200011fb9be673cd79c5818c39e4ff84d88c005e54497aba793afaf21ce39f3836a80824df05edfe4c3b1e70ed27b9e2648
+Qx = 9237e61ad9ffafc61cc1c72b6d2f96d69b588c8feee4074359f694f7
+Qy = db25a18f1eee72734c640313f5c6c0441358611406cc62619113b4ba
+R = a58225b10080dab26644f10d8a817ffc4ed4535011729491b6ad5d00
+S = ddbc010e295882e0731ff240f15ed82fa3e81b7552c690cc5b40be03
+Result = P (0 )
+
+[P-224,SHA-512]
+
+Msg = 11c46138692c1373b296d209dcc0abb71920570d064d077437256d4458e9348901db046a62533b24c84e3ae7572596f1c1315c99ae82233c4445ebf504b48b847b3209ef617b6961bf302a328c95fce7c268a5c3350e51bc270a4eaf83267299ab852f8ae607e9424d161670bae5dfdf98235b36a8e2bcd9abafe14d710f5b9c
+Qx = ea7efb9a7e7bf693dc0249504ead70dd422ec86806cd649ed57a7ffe
+Qy = 33dfb17b1cb244279990019286ab477a2aff2b55c08959deed0b1a28
+R = deab574de1f971419b7ba9e169866c3a6233fc627c13dc6a8cb88bdc
+S = 8d4c542bb0046da1b3912652a2c84542668cd89920808785d04e4352
+Result = F (3 - S changed)
+
+Msg = 0bfabd6b152c3b095a4f19f15acb386ebd987b4dce986a10872a509bf24b2fc68b4412fd14cb74e04fd9b9dc2453cfcdce64340b860c14bdfdd65ad0908e942c2685f0f7a5b95b38183657456ed550d42a5604ca3450f209783b3968c4facc2931dd09ec0541df300a3f73f93bd5b1962b42f565277f043a22d04cc2bc0f17b2
+Qx = 6fce4d789b1240f2ab1c23051aa03e219da99943a18864e7876d4d11
+Qy = 3e84a6bddea4a28cf8151ae73aa7b1964c37e654241353a9fa723f67
+R = 2d1b4f1ccaebc0a929598b650ee364abfd6091a542ba426886d75f38
+S = 44f3d7afe84ae33ab5f9426dfc85248ebc7e0df434d35980ddec75e0
+Result = F (3 - S changed)
+
+Msg = 0a667edb6b991e48b2db87a982fe0e853d4611a0332b4861b133f0a091e2b9e6f0de895d69a9793dc6e54d37d4af2d696c28886f905449e0b7b178648c8ee82bd8695cb96ec6df240d2586bb5049eef307d0ea9dbd23c98c0df35cf816ec19bb273ae529a5aa7e006ea7a207d7b25d375cfbf765ec86f7d5e1b82f5d023c714d
+Qx = 72013dd6f5b1eb709b3b7da234987f9a36c6f0b095620b8c31f02381
+Qy = 319d54c719b59d91900b3c20d963ddf1a10d80d6601ac155094b075a
+R = eb38db9b757b3cf04020f09188c789bf0258cd0467cf7d67368e8703
+S = 7664e85f01e67881712b24083f89e838c8b818de4d665494e7016833
+Result = F (4 - Q changed)
+
+Msg = cc4f7225790159324dc40a729ffb161f26bb624c4c8ef8495bdf79c1181ecafdb6d4cde37d08ab12667526ed89d582b60e9769be68569ed58dc3e801fe607c85126ea7d7922b31c99e4f3c61da6705ffb6ceeac796dcf1faedf02b7afdda3c1bb7dff99401524eda662b82c67ca77b20778c965f9e25e78cfcc9bbd28af36987
+Qx = c6a65011926eb64e02bf472d5ba37841d49cfb7f17a20fb9f59355de
+Qy = 386ccb33d944fd7be6b8531863d2b6200cd602d300d7e7681537e53f
+R = 9e7c637a699dd52512faea847079f0ad41b20cd7a5461c36d01e857e
+S = dec6e9ef361de3f6ec7d87de3129eaac5fd0b43b5f7f58ce46c29173
+Result = P (0 )
+
+Msg = 00e66766c3f3b32ea084f951d0242b17808246b045c8d20806c69c5a36b14707633525b1478819f9464d79d769b189aa1e88af2e08396072deb36b7b7aad481843da0a0f7fe70348c7af50fde2b3a56b64a5fbdc17e9aa5bfcae1dbb7e9fc81fb3996cb38546383e8c0c8ed367922d4ca39343aa7dde01504f62afefe69d4b21
+Qx = 5bcdbaeb2f6c57e8a9dffe94804e74daaf9db8452d13c6a8bc2a4966
+Qy = a564072356c5d86200e979291a19d5e73d8bcb701cf84d9012824bf6
+R = c58436fb77aaa4468dee284e1220141ce9ff4426f75daadf5a898a6f
+S = 87aeee1229a50921d8e77e7e3478061f5c051097defb104a0455ed81
+Result = F (4 - Q changed)
+
+Msg = 04639e5e0f9ecc1f67c112e9b928e365ca4b7167b7b189406670d3d856f034c252b8d006349a0142b0da4eaa15b061b02b9702a6a9e198b4f013eb094ba9619b8985154f2ea422f627ffb2ac9df1c4f942d559bbae8b5342ba717d5aeca6c245869afed38f550c4f0ab6d59929691b960799784461c813d3bb48024d78ef0c59
+Qx = 6c6a7deef8b3dee2eaa98d8ec877dddb460365968e63ffe5c249a421
+Qy = 1ad1715797b5e47c4be24d7ecb8141f1772344a2f643cc66fbcf3f9d
+R = f778faa2dc2cee7de2af0bbc4339239dc240907e59ac034464ce986b
+S = 2ac929588a8dc8785808c9d4366bd7b1a81e0fc5be0c63e62344c251
+Result = F (2 - R changed)
+
+Msg = fd43b5f491d0e9e9cf6008f9fcb144c4c05da64fb363a43e03a99f0d3ea816ac6a2450ace86b33b445cf07ba15e5a3b897cd5f5374a880683fa49d3869128f0cd8de681d0281c50f68dc1b84c48a8fdbb21649a8b0c328797c6dbab5d0aded032433353c06a40fd3a27a1f2efa3338abff208914c2a78f70b02a383bdcd4180c
+Qx = 0ee33a134feae6ee1488bf10edf7cf7c318a2d709080a24818619b91
+Qy = d7d39536e42652baf55159847f475ded075385a3c1af5c3dcb17ee6a
+R = 34bd0407f80cb6fc759036e6d4522eb6da94874c92ce0f02d8f5f2ad
+S = 3a2dd970050ff990162e5702b06905d03e3c7bb2771050de6d84eece
+Result = F (2 - R changed)
+
+Msg = 8a5cefe2295015c4986894882f2c2a9b13cf0d97c00e2ac892c311d9bc75ea4099000ce8702e310ddbdee08df0a7c5a18a2932a912c09e4d00744923f99de473aaf20acfd3a6a8d01369665b1721f6bebbee709d36cb16d3f85a07e9f551169acdad42e54fa68420f49ddfd366aad886442360bf41c93b96fb859e5c21dad587
+Qx = 31d3c62a4305c37a15e9102072e287a8e0ac027f9189cb9d87ecbea2
+Qy = 26449ca391af6a2a9f8daaa036f2c9044b336773ee48bcbd9cad59f0
+R = dc33e8f7b52f584aa3f091aba10c2a9a23be6835e1551092652e1bbc
+S = ae84a6d19f6bad3f9886930c0a1406016fae813673db1516b31b638c
+Result = F (3 - S changed)
+
+Msg = cbcceabbba6f423d1135a4981923e9dbf35db41926310e863015799597c628ce82a97beb29a6222aa300b7d79e04aa55971f8f5f5a95047eff79748babf2214c5aca26208f8cf3521dcc9a15904b532ea18e8f678d13ba3ffdfcbfd68f7f8871e23bcdd41bc90ab51d4178e5a9e0eef2b40beb2984390185b582cd11ca435feb
+Qx = a6e4470712df583d0c795237ff46c9df5718ba2aa24139a2d99721b4
+Qy = 9edb403a8c10807e8736af665dbcf6052bd4b43bcdc8b9eb8d4394fd
+R = 4e9ba5bc4f4fc4e507c1e5cbd0d688da4237385b16ff06601436d8ab
+S = 4e0450a57d802d0ea7b0fb57eb162267195bc4248a831a0ee8b0380d
+Result = F (2 - R changed)
+
+Msg = 51e739cf6242de802172e21425a804d0512da361ca34ac9a9dcbd65995e50da9fcfaf04cc6794af4816ca2da337220d0e471df7145d0abdd3e609805b71a8b380a360eed3f3cbeb93b6916917ed4b12033110bcc4f7e01bb877d0561bfd8f772eb675290cb885b20985cd89f1adad18285eeacfdc55bcb1a329ae9292ec8fcd5
+Qx = 350fa782e1cf7254b18cde30683e54edf2c1b4782525fd081bed5920
+Qy = a77de5b4139ff63e108b6fbd3a7e6c09c3d2ea8720860a7db1c1b5c8
+R = fb7073865646bd92f882f8224503ac1f340cb7a5d6319102c31fb544
+S = aed3ca77d23c78ec76f748e84483c536d447b0f8e186dbd0774b1214
+Result = F (4 - Q changed)
+
+Msg = d9a8a63dab8ccd95e7cbb989d3ba034a0d4710b2c247acc7800ac00f49c60ced88d17e7165ba5a56658a57e4d957dd6c1da4faf0d76de9e2ac27688ac40bfca099aa304c068d0a9fd105a38210cc39549807e7a419a83878d48dba4985f62236439fa2ffa82e05fba5814a58b41d5922e0cca7b4f621559532dbf2a6122a97bb
+Qx = f10652c3c2c30a765564f5e393c6c202d436c81fc7d71b88857bd458
+Qy = 42979ba5e6c8cd044e262c73e6aa918d8c3e0e08e4bf98ec2d5c6f57
+R = 072e0b130267d8e124dda2d0604f4c575ef4007628fa61f66bcd8f07
+S = 6276475fccda3bee2af7816c7b3ec222e408cec36d0409e672af23b5
+Result = P (0 )
+
+Msg = b0465efd2a6dd512f3dd6e9fb1b929470387de4c75d7215d7d3604bfe3accc6b7547586128add45eeacef182be2700329ac0061299ac2170db4c1714be6387d9f31af12fb9e0ebf12ffce8c2b4440bb1c1f708c2aa9104ff1a27addd5feb779373a4a80c80a248e315b05144b1b82ad62a56747318146f8c25e743e4396ffb98
+Qx = 89cef29515f1d30fdd283625eb59e682023bdf2eb0497288ff700b27
+Qy = ca0a3f7ee4853ae8454fff6e926c7a85dc7852fb4d01cc3de861c53d
+R = 0ff5dba589454d0ee5bb391a4dc8446b1ffd1cf8d66c9fc0f05a8a89
+S = 987c32258cd12b6b9cdcc5915eea5eb79a30ead442179a126b97fa9e
+Result = F (1 - Message changed)
+
+Msg = 29f8a8112f8e4eec4339e4067ef06055c87d81445fb659fbc7e76a1cb800f513e1c98a533821c86a8ccc14aba76124183cd1613cd115d0286f510339f7f1936ff37df717788eba0e81fff66173e49df84d7d39960bdd282d2e5b368bf724d5810e1783261513f59fdd9064a9da997a92c20d3767761d50ab607354b410ee60a7
+Qx = 086d892340057368ca47a3762735519a4316f005ed8a18a9edce3b4c
+Qy = e15f4c9a0d240fb94e05192ce4296c532b549af577c26de861dd3452
+R = 8d1e13fdf36eeea06a837cb22d17601081df6ed2815ea9da79894a75
+S = c19713a132a562bf2abf8c2d8cae95ef3272824db63edb0776ffc1ce
+Result = F (1 - Message changed)
+
+Msg = e5b02a9ef5806a52c300354dabb0d0fb2373d90eb7a47df396a25b0a377e1e4d4baffe8dff5e3527ad35819c867e9507c6d2b3dc58c9b314e279d273ff1450e3143768b902d32912e0babbe79c559c4ac8d1b376d5249b9246b4fd2b079ed44142f925461d791d4404d6d4188e5c85b22403808ac4f0fc5f542d11f4417b3c34
+Qx = 6c8aea044d4f0b9699eaf398dbb030db4d6c68e0786068fbc2094974
+Qy = 426e743008febd8597594e7247ed1cbd40561bbabe1031963591ec6b
+R = 3041c36b8456d65f4564597c65aa880fa8bc455f2c35de0fa2298cc1
+S = b87a516d1e2dcd862c6e5fcfc363e9f36bb06ff2c0333e95221e7f36
+Result = F (1 - Message changed)
+
+Msg = 4f00725aa241ba6f1d1f8211248d9dfad1a5790de68dea2857626a74ba03181f65fdcea0bacd8a74319102b075e4864bc8eb4cc0c452dbad8b976b0fa5d2c2da7b58c00972260c6d22b2036aee079a382df841b0d9d8172860f312e76bd3abd4aaff6d61a85bf596a08e063cc4b18cc2da3ba8aba2cac8f80e4e7ab617035e6c
+Qx = dc85f6701bc95a60ea52f1c476dcb211e5e3eeba5b35dc3a3786113f
+Qy = a52b364fb7c4b4c9155e4ee2d8841386b8a96cbeed1e5c9957214a50
+R = bdc7b4d3266e54a19f030f3055f83460ccf30fe8f5368be013076081
+S = 82a0e3a21a8d5e9cfcc5a673385cc2d4159498b6c1ef5791b2b02f9f
+Result = P (0 )
+
+[P-256,SHA-1]
+
+Msg = 2d9c344f6877877290ad536c9eca2cfb92f3973b208367b90eaa73320326025663959b0d165ab88902c891dc1bf61a96a76e4488d6c299698e94f36b198e1f2b0d243d184ab145eb5c2253ff7ad10fd2df710e15015493f1b2fcbb28d5cd734b638d8d123bde9ff03027ac7345b5928c1963645b80f0e8dfa53fb3f694cc8bda
+Qx = 1198b3c409a8b47edb1347e0982d533cb1813e5cb2a92c824b2881b3cd2f3f4a
+Qy = 0bdbac5fa02e41e775f8d602446d58ecb2209b5a3d79ae69eef399016e992e87
+R = 9206d435f148f88c15b2effbf3c506e41b2c620102022b801e371d0767b54bea
+S = cbc4e1674ae1af69873946ccf6275946e59e0107278749b2d0010795833d80fa
+Result = F (3 - S changed)
+
+Msg = b6f46b2a2e9e8ab9ab1927ff7c86ea3df6e8dc391248644bded191af47e53ff6eb251e3b724feaa704c59ee9c99973ef83a4d38f7c2f0297d6f8f43bb33b672ccb4aa1b48bb8977f31e494a3236fed1ed5f2ff7e895e3edb55fb0e1410eb8e858ec037e09076256dbed71aa914e4c8af63fdd4b69832bb69019ad841e15b35d0
+Qx = f7c6280aecd6b936513b0ca84e63346333dc41437a15442e605d46bba93ae101
+Qy = 3c834cecc16167b07866a9478f9f2d882de7ef937da447cd837e60cb5ed65d81
+R = f615af212ab030c4bbf9362d9815a1462312df4beb4358a7ce80d820355420bf
+S = d12ed715ef65cfe6fe6bf348364088a0e7f70927bbafe4c12fc4cb65c0cc51bc
+Result = F (3 - S changed)
+
+Msg = ef1e60767413eb9c0e24e578c78b3b14613047f9217901996dfa6f61e2f6f953fd7ae253e6a3a1e12754aa4e2b2251654b861073f5db8615f783813c686547ffe9457a30fe86ab4a6cd5c5c05e23f7407f21f6413efdfe84bcc0d0b2852675c07aa579296d8d7a08d0b9bf863c8e2fb106741d977272ab8d307f31824a693dbf
+Qx = 0e7632dbc4db879e10d1d80f2789d9fa414c1fe77a6c1e56d6667af43e36e610
+Qy = 6f0dd2a5840e5a6f6ff7e23f656f5c945b7a493fbb0cfd5b9b531bf04435b1ef
+R = 2b0b9ab4a575732a168f28494b66a855fc1a757fb1177864bf3e4f0a000c4a86
+S = 54901ce2f92f55ac112afa0f8b62bc00b44c8c10fe0c863675bfd305d6dc0cd8
+Result = F (2 - R changed)
+
+Msg = 3b9e4ed5930c37f2dd52ae3dd938aa2d4f265839b31b986e04eb6cf6b1f35743a3ef8260aadee414c75e13900b2e35ffa4fc7cbee8a8b4f14354eb2a5510e483c62ba74723803e802df4f3d6dc24017ed86772fe964c49ad7ac3b6f218a5752c972be718824f85a42e71269c187494d5a52258c3e9059d962132b9ae8aa70bd8
+Qx = 1613f12bae8e98d09b4bba53f5229596a0d417d2c625f41bb15f923b3c1e4b57
+Qy = 411319fa85227997a4cf3b1756161485124d2cedc38c9c30d82f42dc2647d545
+R = ed058d476a77be99c1b0fc8502abe545541b4c0ff3eed3f558133ae2f02042b0
+S = c571b4895712a4f64f7220b0694cab767379b09f1824fe7874acd127deb2371e
+Result = F (1 - Message changed)
+
+Msg = 06a04290ea6f64ff0ee5f59b325c9108a9acc4f70af32092a321cd9dd14115e48ad5e4f1ec5cc1cbd05a29d06cf8f5c4a7101301c117fcd62b18e081156a1049d0a11545647d41b16e4edc2aa51460853283c8411cfd8a45172ebe540c06881c85f3a84718440cc7835d5128b63e3e158f30ac4e284757996958b2905b06c8d7
+Qx = 88bb041dcb1733a676a7f4ae8d3e407d72d5396547f07db77078485c1d5db077
+Qy = 72cf2b55e596cd140c58228f1b0a19c34fca26ffac043528a417c5abb6fca9c9
+R = 87208734deb125dca68f0d33f9d369cf1b79cf5a021391b9c6c1727d2efe663a
+S = b984f722de18f1ce407104342948f03f2b55413a096c4b5fca1e032a2c814a4a
+Result = F (1 - Message changed)
+
+Msg = 6e7047fefb707b9f8c1b645ea78958f7136519a3cb111485979c318637fd7247fe093ea93c02c78dbb590cdfcb3e9702ed7bef95ed3000d6a5b7ea9014f6588b10985f105b4e53494adb23b7ebadbb844fa239c02e3781776b9a6ce476d1078664f226d280615af80c4ecff2c718e57bfc4ca5da4aeb7bfbda021cf48603d723
+Qx = 811eb5180def7fb60d632f8cb2cba831b88cee778aa2a82ec3a5fc3d80ff7fb6
+Qy = db88d65b0fc35d9ba1f1ced0400434979ae895d371d1441d7c7a441a9fb1709b
+R = c329fa28dac0018276c5af0cd770e60be50bc14e2562d5556991971edc7d4916
+S = 2d111d13837a02fa279fe835a7dc59a521864d92b26649ca4e24b36ae93878e8
+Result = F (4 - Q changed)
+
+Msg = 3779c87fe0fd8d54e7a677a3610851611d1953ecb50b2919d76233ced63fc8b5a92ae278ebabfaac3eb59684217445ec240c192e1956b24bbabd80a6a7871675634f1149465ba90f8fc4d68182798a4ea86596747a29f8d10555f35752d891678a62b86036b68bc118138cf684e9abb843bcfd3e1c899bc490354525dbecb824
+Qx = 4a6f1e7f7268174d23993b8b58aa60c2a87b18de79b36a750ec86dd6f9e12227
+Qy = 572df22bd6487a863a51ca544b8c5de2b47f801372a881cb996a97d9a98aa825
+R = 4a800e24de65e5c57d4cab4dd1ef7b6c38a2f0aa5cfd3a571a4b552fb1993e69
+S = d9c89fb983640a7e65edf632cacd1de0823b7efbc798fc1f7bbfacdda7398955
+Result = F (4 - Q changed)
+
+Msg = 485f372d91b762635d3fdbc6d80c5263fafd5f5908cab548a78a74ea6bf07657a12a61c8714dd41d6c670bdb700e315b483f83efc1821ab19e56810ff36aa8c462a1a0f56e269e121ef56efef1bb83c64941e5cf33894fabb821557f8cfe71cdb8e6015df4df41e85d8ae936d9cd54551045ed404e79a69abbd909071475c6cb
+Qx = f3033d1e548d245b5e45ff1147db8cd44db8a1f2823c3c164125be88f9a982c2
+Qy = 3c078f6cee2f50e95e8916aa9c4e93de3fdf9b045abac6f707cfcb22d065638e
+R = d4255db86a416a5a688de4e238071ef16e5f2a20e31b9490c03dee9ae6164c34
+S = 4e0ac1e1a6725bf7c6bd207439b2d370c5f2dea1ff4decf1650ab84c7769efc0
+Result = P (0 )
+
+Msg = e1214be446927e95011ec806444ce37ddb21a1a1d14e939b5a4c834991f85ba84bde22d9afb093c20752cca101cf6d0aefc8fb4593c18ac9dd9d838a1d7f28bbce1e9a20b08226152eb03590e37078c444f91ed24c7934c3c19b7316cf0f3183821df6cc0743c0f3b233eb70359981db0e19be05e135834d4f76bcad4b862961
+Qx = 0ea0a6bb6c70966fad1a2307479c12de2322795bdecb70e4b286bd6200ba9c1a
+Qy = c40eda3947021348db691ac4086fb6c06b587ce37c155bb0a7d912b93226de81
+R = f5509deff7bfda3f3759800fa4033af6a84466b114ecb48eac37eff48d2ae1b3
+S = 8c4b62dce2082f80caf220cdbb1d02567bbdfab40564b90ef31d86e3e10ce80a
+Result = F (1 - Message changed)
+
+Msg = 7d0853cca7bf29d22b02c49bc19091c3c4a067999fefefebdcfd5998563b5aebef3b6e779fc665ba0954077f63d0608ce4d16ee9edea3646e34dc38f198ce0b25760360a422a3a1946a8e9903fcfc951733676d3b27d6b9c5f73af0ff098da920121bfb06a8741dc52bc1b01c73a1b0d8c517c2904e16fb7cf63306fe2e2da6e
+Qx = e7a57e0f6ec0fa9c7c34978034cf82f039f8fd62804070ad943573fc8efa5775
+Qy = 87b2cc85dfff2dae5620fbe3e6256bd728de28fc9dc1b5eb6b5d7bd5d29186ad
+R = 97642038932fdddbe2021ec1af53ae6b9af00ef9c8b9f26aea582892e80e6285
+S = 9cb14918359338041cf795cf6781e4905837fa5ce3b3e50ffafb5f13c73b5bc8
+Result = F (4 - Q changed)
+
+Msg = d2491a19cc2c114f3b42d9da78e27364360b4e59fdb5b4f0aa330fa22798a34d2356de0123b6b459a386a3ef8eae30738149ea3742c53b5fa195f390fad647ea1b7a09d8ae312f5d3bebcbd3e756ff831e9010a078ed663588f555a39122a6e9786b7a5b709c634e86b88f41a0028e5151cdc6d11874d184c2093c48682f4289
+Qx = be7a651be0c87278569987cf62d7fa1dd1b3d6e1b868d8f4dfb56135a9960eec
+Qy = b7a62c588a987760b915edbd7f95506870c60f042471de1d8b2d4cd9d6563391
+R = aa889fb608b6939f6eeacf2f64c3b2e3a6061f2834058c7e724321720b737a63
+S = 6cd6d0ef2b93a760daa914e11b9b414bd4d72457405f00a62ab63f36d76efb73
+Result = F (3 - S changed)
+
+Msg = 546138ac0fc0c031eee621e5b8779abb728c15c6a71369f644bbc56e36e61f91e91ccd80b15d9bd75fe46493c928c7a3c0eadc2bb9acce0a173e41eeb5957cf232f744116ef875fb708b42fe8e3b184bea118ce06741bd6bc8e0842024ad67eadf811d37a37f7d572cd4ea76184f61e08f81c3b664c46db4fa797d08f9de61a6
+Qx = 76ddc46d8db8d7ce2ce837f60cdabcee92b7c7817ee41c8f066f1ae65f85c318
+Qy = bea47191f1c584c87250370ce337a1de1583bcfc20ccc23b7a82e83f19adaa88
+R = 84a42efbf7ec04166ad144d19cd98c120aa2e79d483b5eea6fbdfa7f1222e07b
+S = e41531205e691e65668f69f518abc7b60f32c373434872a043b7358462babf83
+Result = F (2 - R changed)
+
+Msg = 41e6ef0cae4eb07fbb5cc0d381029072974fb68f92a7dd5fe9279fcd86949ef5777e8e555ae5d90966de5decd00ec8894b2d8ae2b227789ef6a0697444b40bfd3e5880b97dd993131e2de92853a6f402cff1bbf1e0071d2c66c581ff1727d38ca486e0456dcda16d82a67b46a2f48786e902754016cf3c1df2152aea907de65c
+Qx = 2f71b932f770ba9daf7c1dd47444ab6cb8881f71a1c597e719845b15cb84ca35
+Qy = ab928625b40ec0738d0fc8dbc4df4a1f65d20bc0447b69cfa13bb20b95bb41d4
+R = 63fca172bbca6197cd2802a9cb61d74c2b47cf35f6d35203e67ffbaa838be775
+S = e70ec283cd212df6ba3723e26b697501f112d7cf64e4f45185dae76055e09f1e
+Result = P (0 )
+
+Msg = e2bb35226f7ac77b652c98993b4a0d45f7f25513d66b7a0a25b6a2ccdb2772d7423d034aca445cc4e5332e53c580d1fd48dabbf09f6010fe251efc4ff9f6c09a121d5718d4ce5b26ec35fb5360f4ed9b70ff0cd8fb015cb96f8246acd697be78046ea3906cb0614b50691336d7990f23994a96e0975492524438384e71166048
+Qx = ce775648b928db82ac5edb3b009d32959a73b86c45e96d4b8d5b6e640b7c2790
+Qy = 52455caf08ee94d86f0984e9ec9268d74823f2102dd97fced59638055f6af18e
+R = 2a64b29146588f3153fee1029a0131ac0a8a25ba2ecc494f697c166c7c91fc08
+S = 7b429bc12a72ca3d76c119eea9f4098633cc31c87831e54d5d93afd6e8d20f4f
+Result = F (2 - R changed)
+
+Msg = 27500d3ee8bc458633114e09e4fe23fc5a6e2a10f2d32865b55b0dce15f9738366fd0098d7f482923f7fa22d360261a272b5dca94218bae2f88700045a645cf21b23e815170343a4c192a336ba79934d022be0b7104e68bc5c79e411bd3b2c6fca529b19a78df6d901f54cfd39138bf83a6e6c1a4b665e596ccd71a3fe42917c
+Qx = cd2f29a53f0ce57e0e4a542c3256e65ebbdc30415f4de771d5d706d3aeacc852
+Qy = dbbf2c129f30d11fe77d7816a24187764eae3fb2ff70c1ec745e876e26f5232f
+R = 2454c5ee84e4f77b554acd368dd412389db8c78429590a092f24db2da43cb761
+S = 63e870ce2fa4085d4ff1e360f7a5c101a1f8b288abe71cca56887e613ad034b7
+Result = P (0 )
+
+[P-256,SHA-224]
+
+Msg = 3a9fd6b13337d9fd995d6e011e41c0bd24a7b068e8caa2f8ba10cb5b852e4f82c2d5176542a87668df5c6dda62ad47067e3bf7bf7f0defa57d996a1b40b22416bbb009532b5e29d995c74defdd3824847e7ce473353f9825331fbd0aed174f6ec2c8c4c7f05d7c66304f09745acee5708e31770d9edd997753c74dff1b0507df
+Qx = 843f6d83d777aac75b758d58c670f417c8deea8d339a440bb626114318c34f29
+Qy = 83e0c70008521c8509044b724420463e3478e3c91874d424be44413d1ce555f3
+R = d08e9a5db411019d826b20ac889227ed245503a6d839494db1e8d7995a6b245b
+S = 8d46a204054125d0dc776ab1055302ec4eb0f20b90bca6d205f21d3cefd29097
+Result = P (0 )
+
+Msg = a122dd3120879b6d288f1a4fce115899fa5a4a273621b022429284df2905a5f00eeceb4c3d57d17f1092b8bd11aac2768f69e82d4698170a028fe8b01625656eab963d07409280ebeaa12222adeab1e068015347fcf208d50d409c40913a85e6d0b8b8b65a70c10077e79be52286ee767018d9b1528e92014f5c8e11b4be9042
+Qx = f08b56f73f7a0e098444f6f0a02ad81ce0b914a11cafa15893d1c84704e1c564
+Qy = bbee9aeb91cdc2d1d1437b4168df73acfd64e8b02962b14c85e67187e1ef80a4
+R = 71b3ec982725a007ac18a5cf60587e1fd1beb57685a1f9df3cddd9df25dcbc18
+S = 407e41217325f92f8a031cfcc4eb64c1a4b17b0a7459c254af754a7ea9eac997
+Result = F (3 - S changed)
+
+Msg = f8c9f5e424bc4fd18b6d103ad110f1c33976c337b0f8bb98ac936ce172bf218256c5f71a08d3365ee3498193d916065033c323827a0acb1cfc1f09ce40005b9cecc316f3cedd3da420c90a41a27c49f060588000ff2d26c77d830b46bcb6d4a5ffdb4702f575691b6b75fb1fbb73b5a03cd773c97ff7aff33d90a6ab9a4890de
+Qx = 0b688e761e1ddda2305e002809da65bf5916dfe1356a5b99b61f5576a9b90efa
+Qy = 90ec958e2e3a676e7bbf8e9394f72742875836125a317b0ae38374953f746a91
+R = ef89df3bbf079fb250f7e882c4f85c0023fc3804e862d9ef4d9530a15f1013f0
+S = 4ba985e900e6737b8e07eac638f7b38277ead4faee6d2076a2eee90fd2a6bf0f
+Result = F (1 - Message changed)
+
+Msg = 45a7186fb5a3b99dbb2f68bbd7f0afd1f49dd904a0f2a7899bc570f52b1f6434db43242cffe43b9053fdaac409c6be10d7c0ef64d7530b34948209c76aefca42c5c4ece230640dd98da353261a34268a47aebf39f7f2b5ecb96bbcba3d6416a80124c6008f2c4dfc4f071d033228b9054a58c501a827bac237e8f92e064df60b
+Qx = 0b64480783e260e1e9caef37b4cc9c650d2d57e2c594b1106314843d8d7ab74e
+Qy = 29d373d8522deffe40055aef539f53f38937eb799b44f05a8d8c0b381f12907f
+R = c5c26b0b21eef0f7a0f1cff38d0079d890376759369b01d8d8e959c1c785e203
+S = fecc400bf0deab99d87da168b9d0dd31d2dfa3435b0fe9d38b5fb8efd45195a4
+Result = F (2 - R changed)
+
+Msg = 5201328490b8f88a1bd31e16359e9a0770691313da5140575ca460d398f3d26ae4fa32fcc4aa522c9597333a20bbc0986235410f861522584a382b7c197a9f90a6742e18cd091f68106024b5beba0a67fa4699f7d0310c9c6d49ce37ce1e9653b3b77eb7a17a58676c2d9c765ec5077a7562d3c697cbc9a6f5e50e0819405afb
+Qx = 7f78a8fd880c509940e2b83de67c9ab553ab91489bae75cdc1d5b523b06ab7f5
+Qy = 7786aee7032c373cdfad7d9ddb6fa09a026f6da30fd477ab014d30a289d542a1
+R = c93ada69db326f76b1362d610cb8bcc6e7ef1dc03d3d11367e153c0e39d5dc86
+S = d0c02c71b14ef7a4af4e23bd207ce98449f5d6e7e5b3ec8cbbca9549e97d379d
+Result = P (0 )
+
+Msg = 2c3af4a121b896c59437abf6e58c21ca6cc45af7a405515a7a253554264735dbd6139cf27316c6d0454c5729ee770116c267844e4a4e72bf6d3a4a050cf274bdd9730235a6bf26e6731b2e72afe81046849706f55f8d3baccb6b321123f176d6e586daf01d903843b396fe7f3e4015c464363f54aeaff6e719267392110b37d3
+Qx = e58cdc207c56f62e0bb7c0b55b7f7236a6b308f8fc4de3e61cdb3bf20ad2f62c
+Qy = 6056c0ee827e85ba284838954d0c6cc096df03b4611b1e0f7f9002bac86856d4
+R = 2df3906527ad322000285bccdd11dd09130d633cf43534f5802604639eb847e0
+S = adaaad19b7c66836ef0f4afeff8ac5e898cd2523246a74a1a291a3a1ff583322
+Result = P (0 )
+
+Msg = f7afb86bb6943f7c0108c31185102a323311011529b95ffc0a9a22b63e310f50a94813089c2541d4f864ba1e9dd275cf5abfa79d5126e8164f1c1f78fecc0d24808cf519a6e93648b0fa4da4cbd2888c5e02867653287de8a7cb4ae6a7a5c8dcbef01bf79d31f22d7d933e5bf25bec1d773f7a5ae67fc5bd58069d3debce16c1
+Qx = 70b4bba10b7bbc6d4175ada8d485f3685b13916d0c992301f47e45b629c63d0e
+Qy = 257a93be31b09ff4cd22e3375e30b5a79f3bf3c74c80dde93e5d65e88c07c1c4
+R = 6e714a737b07a4784d26bde0399d8eee81998a13363785e2e4fb527e6a5c9e4e
+S = 94c0220f0f3fa66ff24f96717f464b66ae3a7b0f228ab6a0b5775038da13768a
+Result = F (4 - Q changed)
+
+Msg = dfd611caa868f764527c54f144dcabcab1fa7722882bfe293a15b35b0250d3936466df4eb1f87e053295290ba34390e6efcd64677a8771d48cf8aefb59951d47149c95f90e7cfab53b996f53b4a97e6696e6dcb4b0c8282e5405e98fa5da1ad7536a018ccb5b921873d89f957386e9aabeb8cbdb908d49d4cce97a63268d8863
+Qx = 8b11b48d2397355000a5289d816b9892ae64dffc842abec02a2fb2db2bb34310
+Qy = fc1a42528a0473cfc2c2e184b8bc5055096350fe1549d24b526d6536681026e8
+R = 61a91dd1c80049e70dc4aea84bda0efc6ec9c7b9dd16ecbccf687244c51184ce
+S = e381e7b32bab49578c7e7ce7784ce19263e4a7dab4b614df411d20eaebfc391c
+Result = F (1 - Message changed)
+
+Msg = 6707e3bb71ce50247337cba8b70a684fdd1d2c7bb677b999e0766e31f380ae658bba06094d89a0c344cbc7425a093c1382f1d2d3670ee4292928a472126a9c7e48acbe3f5fe3176e76e62668b4f8c01fc8194509e4aef12722d626d932e6c8e1972c9d9aeea5b862ea13121664d900dcaf6d4c8ce5b06c6585af8424b3df5cc1
+Qx = 7bad1b3d8bad4355a44511d2eb50daeae793af99418ada118327359936aa0e1d
+Qy = e7eff40334b7a5455f6b0d0ecdcdc513702857bb5bbb73c910c86746092bcd7d
+R = fd961b60b21be32b47abafa77e22197dc99af6825dcca46e0e3b1991a90aa202
+S = a0477f97b94a1c26a3b2d186791d7fc9dfa8130bbae79c28fa11ec93a3aeac0b
+Result = F (1 - Message changed)
+
+Msg = e166218ec72b1c41c436305949417c607c02607318fba65659b0c6e484f2ef3a814b056b1f4ac3d8bfacce79c1d21fe0f9e76714a540dab55c9a22b5d4d2877cdd8f9ef5a259fe2724b9e4ecf9c20e34f0da8dbec1496f4442010b138e915ea4a71c7eed4b8ff15679b82d4c45e01b53aeb7b2f07c8baa08e1cb0d95c4f29755
+Qx = 407d92c9b28723602bf09f20f0de002afdf90e22cb709a8d38e3c51e82cba96c
+Qy = 4530659432e1dd74237768133e1f9808e62d0fbe5d1d979d1571baf645dcb84c
+R = a7dc65293ee3deb0008ae3e2d7ef9e9a4ebb8bf7b10d165f80ab8bed58d6fdef
+S = 3e8300a3ee603a8d8234fe265c628e705015bf1903eb74c943323050626f701f
+Result = F (2 - R changed)
+
+Msg = bd808ee61aa7f2cd405366f7bed152e137c427123ddebc73264b2df06a780a47ebd28f4c5cdab2640be9e7a0d2f75a8782998d73e44ca6b579892590abc70b34e33c8495e9c4ec7416f3530193f04f7bf9d7b3477af693619141a6a24dfc9ea9f0ee795cca8c9b418db2716456e3fd5dbee55f22aa8c9986673b1a4b631fdfb7
+Qx = 26aea3dd5c53f984dbdaf415c7f26e1e73048658a548eb3b59dd5f721899919a
+Qy = dff15f57bd9b08644d49cbb214403647195725cd4d4511bc8a48b0770466ae9f
+R = 726af92afe53e8125b0b9f3659745be401a37ae658b7b1aa88c3cb97e9de22c3
+S = 794484c5837a419efe11a4e4293341a6fa36d21230925a0e5e135887302acca9
+Result = F (3 - S changed)
+
+Msg = 71755d628e025a37c0659b208907d64cf984f6f18b60ba74fa172595ca4a92552bf93f37d800b2777fb7f97cd94e256a203b8046c40ae2236fa7ade88e339ce42a6e976d17575ce4617b017b890ac24cff2a1ea4283c923133ae5eb393400a431ae6ed650e67c5cf9fb1f7d7e47719d8a3462588bd5980a4325097fdbf12494d
+Qx = e73418677ce044b331a6d60773cbae199221699d31e1bec4b68b9bc0b87e4cd0
+Qy = 37215db4e3d9161f3351b385a61ddb2fcf1cec469d1659e7574610ed27fe879f
+R = ac469290a8f61a2a8c6adc7533dd5cfe804e2e7bf101cc74e5f624f301bccd23
+S = 4c328c3bc259316641fff44753743afebe89b8627f904df7245e42adcff2dc76
+Result = F (2 - R changed)
+
+Msg = d2d44d06dae06355f7d9e09077a742a16755254812b671fd7535653ed5acade929b138e72a678b6f9deb5ed407d60b67cf1db10b3bb15b97a1c2946abce915d281c5a1bf498388bc13c61e735b1800e26919ede5236cfcf3628284120dc03438ffed8cd192d651207638e482ca7bb6ff2f6f935462035f7c48328329ea68a8fc
+Qx = b0892b19c508b3543a5ae864ba9194084c8f7ae544760759550cc160972e87ff
+Qy = 9208e9b0c86ad6bc833e53026f233db9a42298cdb35d906326008377520b7d98
+R = a62dd0d1518c6b9c60de766b952312a8d8c6eaa36a68196d2a30a46fb17dc067
+S = b9ded660e978129277f74c1d436003d1e6d556dc8eed9d505bbaf4c67cb13d21
+Result = F (4 - Q changed)
+
+Msg = 0a04ccd0555acac9e47faff6b6dea1f422e4aec83029795d8b9063bbd2e5306e0977cde1b9d78e005f0e3f3d004e95c87ba5b526f1eb9843e1de8cbf3f2d31b41eabc2ffdc317840804216a2b6127040336cca086734f8d757362fe8736bf0e7e4fdf4aded8e9ceb76d20b9829588b4145afdb208c551407e65d7de955619250
+Qx = 8c5c41cb07d828a6a86be4533aef791d3a70a95cb285aa2956b21feeac2f8c49
+Qy = 84101581cad7a48b7d0596df7ffed47085d22e8a4af685cddbeeb32ea69ae190
+R = 9812449df0a51f7a2a8f78aa9a589ca9644dce285f1e69658daaea759fa5bd7e
+S = beb4c27c748a7944e37afe861576f76b5a749a8ccbbd7dec00838ba250ddfe1a
+Result = F (4 - Q changed)
+
+Msg = 7b11d09b5e7971ac07919f902c59e4490c70d1ecc3f56b625fa836b056187b2a95f752e60546c871b509201e9109085c1fd607d677cfc96780f12c3c2640b36d03b72dffab156592a462abac041ca7996906baf4d51d55753b3ea3ab985f30fdb698338bb336644a02203ed839e7a4a7f23c2e04e33a787a92aaba834fb507f1
+Qx = 788d7e54ab03020e4954f41259052ee5af68361492b180da31fbbe68d868aa95
+Qy = 982a3ababa6d351649e56da3faeb7160b9de74e22fe93a06ead1bd9a8dffdf7e
+R = 3ddea06bf8aa4a1b0c68674a2c4796def0bfb52236f4efb3332204a41fd8ea89
+S = 871237039431a41aeefcdd08f67848b2b09067e3a1344c8ed9b372d1b1c754a6
+Result = F (3 - S changed)
+
+[P-256,SHA-256]
+
+Msg = e4796db5f785f207aa30d311693b3702821dff1168fd2e04c0836825aefd850d9aa60326d88cde1a23c7745351392ca2288d632c264f197d05cd424a30336c19fd09bb229654f0222fcb881a4b35c290a093ac159ce13409111ff0358411133c24f5b8e2090d6db6558afc36f06ca1f6ef779785adba68db27a409859fc4c4a0
+Qx = 87f8f2b218f49845f6f10eec3877136269f5c1a54736dbdf69f89940cad41555
+Qy = e15f369036f49842fac7a86c8a2b0557609776814448b8f5e84aa9f4395205e9
+R = d19ff48b324915576416097d2544f7cbdf8768b1454ad20e0baac50e211f23b0
+S = a3e81e59311cdfff2d4784949f7a2cb50ba6c3a91fa54710568e61aca3e847c6
+Result = F (3 - S changed)
+
+Msg = 069a6e6b93dfee6df6ef6997cd80dd2182c36653cef10c655d524585655462d683877f95ecc6d6c81623d8fac4e900ed0019964094e7de91f1481989ae1873004565789cbf5dc56c62aedc63f62f3b894c9c6f7788c8ecaadc9bd0e81ad91b2b3569ea12260e93924fdddd3972af5273198f5efda0746219475017557616170e
+Qx = 5cf02a00d205bdfee2016f7421807fc38ae69e6b7ccd064ee689fc1a94a9f7d2
+Qy = ec530ce3cc5c9d1af463f264d685afe2b4db4b5828d7e61b748930f3ce622a85
+R = dc23d130c6117fb5751201455e99f36f59aba1a6a21cf2d0e7481a97451d6693
+S = d6ce7708c18dbf35d4f8aa7240922dc6823f2e7058cbc1484fcad1599db5018c
+Result = F (2 - R changed)
+
+Msg = df04a346cf4d0e331a6db78cca2d456d31b0a000aa51441defdb97bbeb20b94d8d746429a393ba88840d661615e07def615a342abedfa4ce912e562af714959896858af817317a840dcff85a057bb91a3c2bf90105500362754a6dd321cdd86128cfc5f04667b57aa78c112411e42da304f1012d48cd6a7052d7de44ebcc01de
+Qx = 2ddfd145767883ffbb0ac003ab4a44346d08fa2570b3120dcce94562422244cb
+Qy = 5f70c7d11ac2b7a435ccfbbae02c3df1ea6b532cc0e9db74f93fffca7c6f9a64
+R = 9913111cff6f20c5bf453a99cd2c2019a4e749a49724a08774d14e4c113edda8
+S = 9467cd4cd21ecb56b0cab0a9a453b43386845459127a952421f5c6382866c5cc
+Result = F (4 - Q changed)
+
+Msg = e1130af6a38ccb412a9c8d13e15dbfc9e69a16385af3c3f1e5da954fd5e7c45fd75e2b8c36699228e92840c0562fbf3772f07e17f1add56588dd45f7450e1217ad239922dd9c32695dc71ff2424ca0dec1321aa47064a044b7fe3c2b97d03ce470a592304c5ef21eed9f93da56bb232d1eeb0035f9bf0dfafdcc4606272b20a3
+Qx = e424dc61d4bb3cb7ef4344a7f8957a0c5134e16f7a67c074f82e6e12f49abf3c
+Qy = 970eed7aa2bc48651545949de1dddaf0127e5965ac85d1243d6f60e7dfaee927
+R = bf96b99aa49c705c910be33142017c642ff540c76349b9dab72f981fd9347f4f
+S = 17c55095819089c2e03b9cd415abdf12444e323075d98f31920b9e0f57ec871c
+Result = P (0 )
+
+Msg = 73c5f6a67456ae48209b5f85d1e7de7758bf235300c6ae2bdceb1dcb27a7730fb68c950b7fcada0ecc4661d3578230f225a875e69aaa17f1e71c6be5c831f22663bac63d0c7a9635edb0043ff8c6f26470f02a7bc56556f1437f06dfa27b487a6c4290d8bad38d4879b334e341ba092dde4e4ae694a9c09302e2dbf443581c08
+Qx = e0fc6a6f50e1c57475673ee54e3a57f9a49f3328e743bf52f335e3eeaa3d2864
+Qy = 7f59d689c91e463607d9194d99faf316e25432870816dde63f5d4b373f12f22a
+R = 1d75830cd36f4c9aa181b2c4221e87f176b7f05b7c87824e82e396c88315c407
+S = cb2acb01dac96efc53a32d4a0d85d0c2e48955214783ecf50a4f0414a319c05a
+Result = P (0 )
+
+Msg = 666036d9b4a2426ed6585a4e0fd931a8761451d29ab04bd7dc6d0c5b9e38e6c2b263ff6cb837bd04399de3d757c6c7005f6d7a987063cf6d7e8cb38a4bf0d74a282572bd01d0f41e3fd066e3021575f0fa04f27b700d5b7ddddf50965993c3f9c7118ed78888da7cb221849b3260592b8e632d7c51e935a0ceae15207bedd548
+Qx = a849bef575cac3c6920fbce675c3b787136209f855de19ffe2e8d29b31a5ad86
+Qy = bf5fe4f7858f9b805bd8dcc05ad5e7fb889de2f822f3d8b41694e6c55c16b471
+R = 25acc3aa9d9e84c7abf08f73fa4195acc506491d6fc37cb9074528a7db87b9d6
+S = 9b21d5b5259ed3f2ef07dfec6cc90d3a37855d1ce122a85ba6a333f307d31537
+Result = F (2 - R changed)
+
+Msg = 7e80436bce57339ce8da1b5660149a20240b146d108deef3ec5da4ae256f8f894edcbbc57b34ce37089c0daa17f0c46cd82b5a1599314fd79d2fd2f446bd5a25b8e32fcf05b76d644573a6df4ad1dfea707b479d97237a346f1ec632ea5660efb57e8717a8628d7f82af50a4e84b11f21bdff6839196a880ae20b2a0918d58cd
+Qx = 3dfb6f40f2471b29b77fdccba72d37c21bba019efa40c1c8f91ec405d7dcc5df
+Qy = f22f953f1e395a52ead7f3ae3fc47451b438117b1e04d613bc8555b7d6e6d1bb
+R = 548886278e5ec26bed811dbb72db1e154b6f17be70deb1b210107decb1ec2a5a
+S = e93bfebd2f14f3d827ca32b464be6e69187f5edbd52def4f96599c37d58eee75
+Result = F (4 - Q changed)
+
+Msg = 1669bfb657fdc62c3ddd63269787fc1c969f1850fb04c933dda063ef74a56ce13e3a649700820f0061efabf849a85d474326c8a541d99830eea8131eaea584f22d88c353965dabcdc4bf6b55949fd529507dfb803ab6b480cd73ca0ba00ca19c438849e2cea262a1c57d8f81cd257fb58e19dec7904da97d8386e87b84948169
+Qx = 69b7667056e1e11d6caf6e45643f8b21e7a4bebda463c7fdbc13bc98efbd0214
+Qy = d3f9b12eb46c7c6fda0da3fc85bc1fd831557f9abc902a3be3cb3e8be7d1aa2f
+R = 288f7a1cd391842cce21f00e6f15471c04dc182fe4b14d92dc18910879799790
+S = 247b3c4e89a3bcadfea73c7bfd361def43715fa382b8c3edf4ae15d6e55e9979
+Result = F (1 - Message changed)
+
+Msg = 3fe60dd9ad6caccf5a6f583b3ae65953563446c4510b70da115ffaa0ba04c076115c7043ab8733403cd69c7d14c212c655c07b43a7c71b9a4cffe22c2684788ec6870dc2013f269172c822256f9e7cc674791bf2d8486c0f5684283e1649576efc982ede17c7b74b214754d70402fb4bb45ad086cf2cf76b3d63f7fce39ac970
+Qx = bf02cbcf6d8cc26e91766d8af0b164fc5968535e84c158eb3bc4e2d79c3cc682
+Qy = 069ba6cb06b49d60812066afa16ecf7b51352f2c03bd93ec220822b1f3dfba03
+R = f5acb06c59c2b4927fb852faa07faf4b1852bbb5d06840935e849c4d293d1bad
+S = 049dab79c89cc02f1484c437f523e080a75f134917fda752f2d5ca397addfe5d
+Result = F (3 - S changed)
+
+Msg = 983a71b9994d95e876d84d28946a041f8f0a3f544cfcc055496580f1dfd4e312a2ad418fe69dbc61db230cc0c0ed97e360abab7d6ff4b81ee970a7e97466acfd9644f828ffec538abc383d0e92326d1c88c55e1f46a668a039beaa1be631a89129938c00a81a3ae46d4aecbf9707f764dbaccea3ef7665e4c4307fa0b0a3075c
+Qx = 224a4d65b958f6d6afb2904863efd2a734b31798884801fcab5a590f4d6da9de
+Qy = 178d51fddada62806f097aa615d33b8f2404e6b1479f5fd4859d595734d6d2b9
+R = 87b93ee2fecfda54deb8dff8e426f3c72c8864991f8ec2b3205bb3b416de93d2
+S = 4044a24df85be0cc76f21a4430b75b8e77b932a87f51e4eccbc45c263ebf8f66
+Result = F (2 - R changed)
+
+Msg = 4a8c071ac4fd0d52faa407b0fe5dab759f7394a5832127f2a3498f34aac287339e043b4ffa79528faf199dc917f7b066ad65505dab0e11e6948515052ce20cfdb892ffb8aa9bf3f1aa5be30a5bbe85823bddf70b39fd7ebd4a93a2f75472c1d4f606247a9821f1a8c45a6cb80545de2e0c6c0174e2392088c754e9c8443eb5af
+Qx = 43691c7795a57ead8c5c68536fe934538d46f12889680a9cb6d055a066228369
+Qy = f8790110b3c3b281aa1eae037d4f1234aff587d903d93ba3af225c27ddc9ccac
+R = 8acd62e8c262fa50dd9840480969f4ef70f218ebf8ef9584f199031132c6b1ce
+S = cfca7ed3d4347fb2a29e526b43c348ae1ce6c60d44f3191b6d8ea3a2d9c92154
+Result = F (3 - S changed)
+
+Msg = 0a3a12c3084c865daf1d302c78215d39bfe0b8bf28272b3c0b74beb4b7409db0718239de700785581514321c6440a4bbaea4c76fa47401e151e68cb6c29017f0bce4631290af5ea5e2bf3ed742ae110b04ade83a5dbd7358f29a85938e23d87ac8233072b79c94670ff0959f9c7f4517862ff829452096c78f5f2e9a7e4e9216
+Qx = 9157dbfcf8cf385f5bb1568ad5c6e2a8652ba6dfc63bc1753edf5268cb7eb596
+Qy = 972570f4313d47fc96f7c02d5594d77d46f91e949808825b3d31f029e8296405
+R = dfaea6f297fa320b707866125c2a7d5d515b51a503bee817de9faa343cc48eeb
+S = 8f780ad713f9c3e5a4f7fa4c519833dfefc6a7432389b1e4af463961f09764f2
+Result = F (1 - Message changed)
+
+Msg = 785d07a3c54f63dca11f5d1a5f496ee2c2f9288e55007e666c78b007d95cc28581dce51f490b30fa73dc9e2d45d075d7e3a95fb8a9e1465ad191904124160b7c60fa720ef4ef1c5d2998f40570ae2a870ef3e894c2bc617d8a1dc85c3c55774928c38789b4e661349d3f84d2441a3b856a76949b9f1f80bc161648a1cad5588e
+Qx = 072b10c081a4c1713a294f248aef850e297991aca47fa96a7470abe3b8acfdda
+Qy = 9581145cca04a0fb94cedce752c8f0370861916d2a94e7c647c5373ce6a4c8f5
+R = 09f5483eccec80f9d104815a1be9cc1a8e5b12b6eb482a65c6907b7480cf4f19
+S = a4f90e560c5e4eb8696cb276e5165b6a9d486345dedfb094a76e8442d026378d
+Result = F (4 - Q changed)
+
+Msg = 76f987ec5448dd72219bd30bf6b66b0775c80b394851a43ff1f537f140a6e7229ef8cd72ad58b1d2d20298539d6347dd5598812bc65323aceaf05228f738b5ad3e8d9fe4100fd767c2f098c77cb99c2992843ba3eed91d32444f3b6db6cd212dd4e5609548f4bb62812a920f6e2bf1581be1ebeebdd06ec4e971862cc42055ca
+Qx = 09308ea5bfad6e5adf408634b3d5ce9240d35442f7fe116452aaec0d25be8c24
+Qy = f40c93e023ef494b1c3079b2d10ef67f3170740495ce2cc57f8ee4b0618b8ee5
+R = 5cc8aa7c35743ec0c23dde88dabd5e4fcd0192d2116f6926fef788cddb754e73
+S = 9c9c045ebaa1b828c32f82ace0d18daebf5e156eb7cbfdc1eff4399a8a900ae7
+Result = F (1 - Message changed)
+
+Msg = 60cd64b2cd2be6c33859b94875120361a24085f3765cb8b2bf11e026fa9d8855dbe435acf7882e84f3c7857f96e2baab4d9afe4588e4a82e17a78827bfdb5ddbd1c211fbc2e6d884cddd7cb9d90d5bf4a7311b83f352508033812c776a0e00c003c7e0d628e50736c7512df0acfa9f2320bd102229f46495ae6d0857cc452a84
+Qx = 2d98ea01f754d34bbc3003df5050200abf445ec728556d7ed7d5c54c55552b6d
+Qy = 9b52672742d637a32add056dfd6d8792f2a33c2e69dafabea09b960bc61e230a
+R = 06108e525f845d0155bf60193222b3219c98e3d49424c2fb2a0987f825c17959
+S = 62b5cdd591e5b507e560167ba8f6f7cda74673eb315680cb89ccbc4eec477dce
+Result = P (0 )
+
+[P-256,SHA-384]
+
+Msg = fe9838f007bdc6afcd626974fcc6833f06b6fd970427b962d75c2aeadbef386bec8d018106197fe2547d2af02e7a7949965d5fbc4c5db909a95b9858426a33c080b0b25dae8b56c5cbc6c4eec3dbd81635c79457eaef4fab39e662a1d05b2481eda8c1074ae2d1704c8a3f769686a1f965ef3c87602efc288c7f9ff8cd5e22a4
+Qx = 40ded13dbbe72c629c38f07f7f95cf75a50e2a524897604c84fafde5e4cafb9f
+Qy = a17202e92d7d6a37c438779349fd79567d75a40ef22b7d09ca21ccf4aec9a66c
+R = be34730c31730b4e412e6c52c23edbd36583ace2102b39afa11d24b6848cb77f
+S = 03655202d5fd8c9e3ae971b6f080640c406112fd95e7015874e9b6ee77752b10
+Result = F (3 - S changed)
+
+Msg = b69043b9b331da392b5dd689142dfc72324265da08f14abcedf03ad8263e6bdccbc75098a2700bbba1979de84c8f12891aa0d000f8a1abad7dde4981533f21da59cc80d9cf94517f3b61d1a7d9eecb2fcf052e1fc9e7188c031b86305e4a436a37948071f046e306befb8511dc03a53dc8769a90a86e9b4fdbf05dcdfa35ab73
+Qx = 1f80e19ffeb51dd74f1c397ac3dfd3415ab16ebd0847ed119e6c3b15a1a884b8
+Qy = 9b395787371dbfb55d1347d7bed1c261d2908121fb78de1d1bf2d00666a62aed
+R = 249ca2c3eb6e04ac57334c2f75dc5e658bbb485bf187100774f5099dd13ef707
+S = 97363a05202b602d13166346694e38135bbce025be94950e9233f4c8013bf5bf
+Result = F (4 - Q changed)
+
+Msg = d2fcaaede8b879c064b0aa46e68efc278a469b80a7f7e1939ec2ebc96c76206f23395967279c181fea157ebb79dfadc68e31345f07f13305c80de0d85e4330d3a45f957c5c2526b945838ce5a9c2844b6b2a665c0f70b748b1213a8cf20ba5dbdf8cab231f433da522104a5cd027d3e36bb373c4ed404d9af0cbec6f85ec2193
+Qx = ce4dcfa7384c83443ace0fb82c4ac1adfa100a9b2c7bf09f093f8b6d084e50c2
+Qy = d98ae7b91abee648d0bfde192703741ac21daad7262af418b50e406d825eb0d6
+R = 597e1e04d93a6b444ccc447a48651f17657ff43fb65fe94461d2bf816b01af40
+S = 359fe3817963548e676d6da34c2d0866aa42499237b682002889eaf8893814d2
+Result = P (0 )
+
+Msg = 06cd86481865181cef7acdc3202824970ec2d97662b519c4b588dc9e51617c068282b1a11a15bf7efc4858a2f37a3d74b05fb5790eb68338c8009b4da9b4270514d387a2e016a99ee109841e884a7909504ef31a5454e214663f830f23a5a76f91402fca5f5d61699fa874597bdbfb1ecff8f07ddbd07ef61e97d0d5262ef314
+Qx = 1b677f535ac69d1acd4592c0d12fac13c9131e5a6f8ab4f9d0afdcb3a3f327e0
+Qy = 5dca2c73ec89e58ef8267cba2bb5eb0f551f412f9dc087c1a6944f0ce475277a
+R = df0b0cd76d2555d4c38b3d70bfdf964884d0beeb9f74385f0893e87d20c9642d
+S = 128299aabf1f5496112be1fe04365f5f8215b08a040abdfeca4626f4d15c005b
+Result = F (2 - R changed)
+
+Msg = 59ad297397f3503604a4a2d098a4f00a368ad95c6101b3d38f9d49d908776c5a6c8654b006adb7939ffb6c30afa325b54185d82c3cc0d836850dce54d3408b257c3a961d11fafe2b74ba8bddfc1102fa656d1028baf94c38340c26a11e992aab71ce3732271b767358671b25225926f3a4b9ec5f82c059f0c7d1446d5d9e4251
+Qx = 7ffc2853f3e17887dda13b0eb43f183ce50a5ac0f8bba75fb1921172484f9b94
+Qy = 4cc523d14192f80bd5b27d30b3b41e064da87bfbae15572dd382b9a176c123a2
+R = 3156176d52eb26f9391229de4251993a41b8172f78970bb70e32a245be4bb653
+S = 62827a29e12d2f29b00fb2d02dd5f2d5412e17a4455f4431a5c996881fdfc0ee
+Result = F (1 - Message changed)
+
+Msg = 8215daca87e689a20392646a6511bb7b5a82d2d995ca9de89bd9d9c0b11464b7cb1e4e9a31e3e01ad8c2cd613d5a2cb44a2a8df6899fce4c282dea1e41af0df6c36be1f320036567f8d0d32aaa79c95fe53b16668f7e1a9e5d7d039ea260fd03711b7d1c177355fc52244d49ca5b238556a5541349014683cb7da326f443b752
+Qx = 5569f76dc94243cde819fb6fc85144ec67e2b5d49539f62e24d406d1b68f0058
+Qy = 1208c38dbe25870deab53c486f793a1e250c9d1b8e7c147ea68b71196c440730
+R = 706f2ba4025e7c06b66d6369a3f93b2fec46c51eceff42a158f7431919506cfb
+S = b4e75ac34a96393237fc4337789e37168d79382705b248051c9c72bcbac5f516
+Result = F (2 - R changed)
+
+Msg = a996b1fb800f692517a2eb80e837233193dd3e82484d3f49bd19ee0db8f7b440876b07e384c90aa8b9f7b6603ca0b5a4e06c1da0edb974a2fb9b6e7c720ddf3e5c0e314c2d189402903c08c0836776c361a284db887ebcc33e615de9720b01dadade585eef687b3346468bdafb490e56d657a9e7d44d92014069005a36c1cf63
+Qx = e4b470c65b2c04db060d7105ec6911589863d3c7f7ce48726ba3f369ea3467e8
+Qy = 44c38d3ae098de05f5915a5868c17fee296a6e150beb1f000df5f3bec8fc4532
+R = c9c347ee5717e4c759ddaf09e86f4e1db2c8658593177cfda4e6514b5e3ecb87
+S = baae01e9e44a7b04d69c8eaaed77c9e3a36ce8962f95cc50a0db146b4e49eb40
+Result = F (4 - Q changed)
+
+Msg = 1a6e49a377a08e992353d6acc557b687b1b69a41d83d43a75fadb97b8c928cfebadebaaf99ea7fb13148807f56ea17384a7912e578e62b1b009fefb2aafca5ac85539433619b286f10643a56f8dfa47ba4d01c02510deaec18029ea6b9682022b139dcb70814164c4c90ec717ad9d925485398531cdd5992a2524498b337f97d
+Qx = 96050c5fa2ddd1b2e5451d89ee74a0b7b54347364ddc0231715a6ef1146fe8dc
+Qy = e0888a9e78aeea87f6e1e9002b2651169f36c4ee53013cfc8c9912b7fd504858
+R = 2353d6cd3c21b8ea7dbc1cd940519812dbe365a3b15cd6aebba9d11cf269867a
+S = 85f560273cd9e82e6801e4cb1c8cd29cdac34a020da211d77453756b604b8fa7
+Result = P (0 )
+
+Msg = 3e14f737c913931bc82764ebc440b12e3ce1ffe0f858c7b8f1cbd30fbbb1644fa59be1d2cca5f64a6d7dc5ed5c4420f39227516ae8eb3019ef86274d0e4d06cde7bf5e5c413243dfc421d9f141762109810e6b6a451eeb4bd8d4be1ff111426d7e44d0a916b4fe3db3594d8dd01ae90feecf8f1e230b574180cd0b8d43a3d33b
+Qx = 0c07bb79f44012299fbfd5a0f31397aaf7d757f8a38437407c1b09271c6551a0
+Qy = 84fe7846d5d403dc92c0091fbd39f3c5cbca3f94c10b5cae44e2e96562131b13
+R = 49e9425f82d0a8c503009cead24e12adc9d48a08594094ca4f6d13ad1e3c571d
+S = 1f1b70aaa30a8ff639aa0935944e9b88326a213ab8fce5194c1a9dec070eb433
+Result = F (1 - Message changed)
+
+Msg = 4000106127a72746db77957cbc6bfd84ae3d1d63b8190087637e93689841331e2adc1930d6df4302935f4520bbee513505cdcfca99ebc6f83af7b23b0f2e7f7defba614022ceeae9c6886e8b13f7ea253a307ac301f3536720cbe3de82ba3e98310361b61801a8304ffc91ff774948e33176ddcddf1b76437b3f02c910578d46
+Qx = 71db1de1a1f38f356c91feaff5cfe395d1a5b9d23cf6aa19f38ae0bcc90a486d
+Qy = ecdd6ffb174a50f1cc792985c2f9608c399c98b8a64a69d2b5b7cdd9241f67e2
+R = b0443b33a6f249470d2f943675009d21b9ccbead1525ae57815df86bb20470bf
+S = 316dbee27d998e09128539c269e297ac8f34b9ef8249a0619168c3495c5c1198
+Result = F (3 - S changed)
+
+Msg = b42e547d0e7ddd5e1069bb2d158a5b4d5d9c4310942a1bfd09490311a6e684bd3c29b0dcef86a9788b4b26fed7863f3d5e5439796b5b5ffe7aa2545d0f518ad020689ca21230f3a59e7f8cca465fe21df511e78d215fa805f5f0f88938e9d198515e6b9c819930755c6c6aea5114cd2904607243051c09dd7a147756cbc204a5
+Qx = 8219b225aa15472262c648cac8de9aad4173d17a231ba24352a5a1c4eea70fad
+Qy = 0fee2b08ad39fbf0db0016ef2896ca99adc07efc8c415f640f3720498be26037
+R = 134fb689101aaad3954de2819d9fbd12072fe2bc36f496bbf0d13fa72114ab96
+S = e65c232bd915b59e087e7fd5ec90bf636cfa80526345c79a0adfd75003045d6f
+Result = F (1 - Message changed)
+
+Msg = aa563223a7d5201febdf13cab80a03dce6077c26e751bc98a941196a28848abc495e0324013c9a2094fb15dc65d100c3e8a136a52c1780b395f42588900b641b6d4361432e2173195a2f60189f3fcc85f4e9659cae52576f20d1852d43c2b400deea3144c8e870e1906d677425d8c85037c7a42a9d249b2da4b516e04476bd45
+Qx = c934195de33b60cf00461fc3c45dad068e9f5f7af5c7fa78591e95aeb04e2617
+Qy = b588dd5f9965fdaa523b475c2812c251bc6973e2df21d9beaace976abf5728cb
+R = 71f302440eb4ed2a939b69e33e905e6fdc545c743458d38f7e1a1d456e35f389
+S = 54eaa0eb9cd7503b19a9658f0a04955d9f0ab20ebc8a0877e33c89ee88ad068f
+Result = F (4 - Q changed)
+
+Msg = 98e4babf890f52e5a04bd2a7d79bf0ae9a71967847347d87f29fb3997454c73c7979d15b5c4f4205ec3de7835d1885fb7abcf8dcde94baf08b1d691a0c74845317286540e8c9d378fefaa4762c302492f51023c0d7adbb1cc90b7b0335f11203664e71fea621bc2f59d2dbd0ee76d6597ec75510de59b6d25fa6750a71c59435
+Qx = 9e1adcd48e2e3f0e4c213501808228e587c40558f52bb54ddbb6102d4048ea92
+Qy = 34eff98704790938e7e0bdf87ae39807a6b77dfdc9ecdfe6dd0f241abae1aeb2
+R = ce4f0d7480522c8dd1b02dd0eb382f22406642f038c1ede9411883d72b3e7ed0
+S = 8546e1ee3b77f9927cdaccbc2f1cf19d6b5576b0f738bb1b86a0c66b39ca56fb
+Result = F (3 - S changed)
+
+Msg = bb6b03ad60d6ddbf0c4d17246206e61c886f916d252bb4608149da49cef9033484080e861f91bb2400baa0cd6c5d90c2f275e2fabc12d83847f7a1c3ff0eb40c8a3dd83d07d194ba3797d27238415a2f358d7292a1991af687bcb977486980f9138b3140321485638ac7bd22ecda00ffe5009b83b90397eff24ecf22c5495d67
+Qx = 93edbecb0b019c2cc03060f54cb4904b920fdb34eb83badd752be9443036ae13
+Qy = b494e9295e080a9080fe7e73249b3a5904aa84e1c028121eecd3e2cf1a55f598
+R = eec2986d47b71995892b0915d3d5becc4dcb2ab55206d772e0189541b2184ddf
+S = 8a6c1edeb6452627ad27c8319599c54ac44cdd831ea66f13f49d90affe6ad45b
+Result = P (0 )
+
+Msg = 33a5d489f671f396c776bc1acf193bc9a74306f4692dd8e05bcdfe28fdefbd5c09b831c204a1dec81d8e3541f324f7b474d692789013bb1eca066f82fbf3f1cf3ba64e9d8963e9ecc180b9251919e2e8a1ab05847a0d76ff67a47c00e170e38e5b319a56f59cc51038f90961ea27a9a7eb292a0a1aa2f4972568669246907a35
+Qx = 3205bae876f9bd50b0713959e72457165e826cbbe3895d67320909daa48b0ebc
+Qy = d1592562273e5e0f57bbfb92cedd9af7f133255684ee050af9b6f02019bbcafa
+R = 0124f3f1c61ec458561a4eaa6c155bd29e59703d14556324924683db3a4cf43b
+S = 688a5c5fc0c7ba92210c50cce5b512a468a880e05acc21ca56571d89f45f603a
+Result = F (2 - R changed)
+
+[P-256,SHA-512]
+
+Msg = 273b063224ab48a1bf6c7efc93429d1f89de48fc4a4fa3ffe7a49ebba1a58ff5d208a9e4bff27b418252526243ba042d1605b6df3c2ec916ceef027853a41137f7bfb6fc63844de95f58e82b9ad2565f1367d2c69bd29100f6db21a8ab7ab58affd1661add0322bd915721378df9fa233ef0b7e0a0a85be31689e21891ec8977
+Qx = 484e31e69ef70bb8527853c22c6b6b4cd2a51311dde66c7b63f097dbb6ab27bf
+Qy = e1ff8177f4061d4fbbacbbc70519f0fc8c8b6053d72af0fe4f048d615004f74e
+R = 91a303d8fe3ab4176070f6406267f6b79bfe5eb5f62ae6aeb374d90667858518
+S = e152119cefa26826ea07ec40a428869132d70812c5578c5a260e48d6800e046a
+Result = F (1 - Message changed)
+
+Msg = d64ea1a768b0de29ab018ae93baa645d078c70a2f7aa4acd4ae7526538ebd5f697a11927cfd0ddc9187c095f14ad30544cb63ede9353af8b23c18ce22843881fe2d7bde748fc69085921677858d87d2dc3e244f6c7e2c2b2bd791f450dfdd4ff0ddd35ab2ada4f1b90ab16ef2bf63b3fbe88ce8a5d5bb85430740d3744849c13
+Qx = 8b75fc0129c9a78f8395c63ae9694b05cd6950665cf5da7d66118de451422624
+Qy = b394171981d4896d6e1b4ef2336d9befe7d27e1eb87f1c14b8ddda622af379dc
+R = 17e298e67ad2af76f6892fdcead00a88256573868f79dc74431b55103058f0b0
+S = 881328cd91e43d30133f6e471e0b9b04353b17893fb7614fd7333d812a3df6b4
+Result = F (4 - Q changed)
+
+Msg = 1db85445c9d8d1478a97dd9d6ffbf11ebcd2114d2ed4e8b6811171d947e7d4daedea35af6177debe2ef6d93f94ff9d770b45d458e91deb4eef59856425d7b00291aff9b6c9fa02375ec1a06f71f7548721790023301cf6ac7fee1d451228106ef4472681e652c8cd59b15d6d16f1e13440d888e265817cb4a654f7246e0980df
+Qx = 76e51086e078b2b116fd1e9c6fa3d53f675ae40252fb9f0cc62817bd9ce8831d
+Qy = ca7e609a0b1d14b7c9249b53da0b2050450e2a25cb6c8f81c5311974a7efb576
+R = 23b653faaa7d4552388771931803ce939dd5ee62d3fa72b019be1b2272c85592
+S = a03c6f5c54a10861d6b8922821708e9306fd6d5d10d566845a106539cbf4fadd
+Result = F (4 - Q changed)
+
+Msg = 918d9f420e927b3e0a55d276b8b40d8a2c5df748727ff72a438c7e6593f542274050dce727980d3ef90c8aa5c13d53f1e8d631ebb650dee11b94902bbd7c92b8186af9039c56c43f3110697792c8cd1614166f06d09cdb58dab168cc3680a8473b1a623bf85dba855eace579d9410d2c4ca5ede6dc1e3db81e233c34ae922f49
+Qx = bc7c8e09bd093468f706740a4130c544374fdc924a535ef02e9d3be6c6d3bbfa
+Qy = af3f813ae6646f5b6dbfb0f261fd42537705c800bb1647386343428a9f2e10fc
+R = 6bd7ce95af25abfbf14aef4b17392f1da877ab562eca38d785fe39682e9c9324
+S = 6688bea20c87bab34d420642da9bdd4c69456bdec50835887367bb4fb7cd8650
+Result = F (2 - R changed)
+
+Msg = 6e2932153301a4eef680e6428929adae988c108d668a31ff55d0489947d75ff81a46bf89e84d6401f023be6e87688fbcd784d785ca846735524acb52d00452c84040a479e7cc330936441d93bbe722a9432a6e1db112b5c9403b10272cb1347fd619d463f7a9d223ad76fde06d8a6883500fb843235abff98e241bdfb5538c3e
+Qx = 9cb0cf69303dafc761d4e4687b4ecf039e6d34ab964af80810d8d558a4a8d6f7
+Qy = 2d51233a1788920a86ee08a1962c79efa317fb7879e297dad2146db995fa1c78
+R = 4b9f91e4285287261a1d1c923cf619cd52c175cfe7f1be60a5258c610348ba3d
+S = 28c45f901d71c41b298638ec0d6a85d7fcb0c33bbfec5a9c810846b639289a84
+Result = P (0 )
+
+Msg = 2f48ec387f181035b350772e27f478ae6ec7487923692fae217e0f8636acd062a6ac39f7435f27a0ebcfd8187a91ef00fb68d106b8da4a1dedc5a40a4fae709e92b00fcc218de76417d75185e59dff76ec1543fb429d87c2ca8134ff5ae9b45456cad93fc67223c68293231395287dc0b756355660721a1f5df83bf5bcb8456e
+Qx = e31096c2d512fbf84f81e9bdb16f33121702897605b43a3db546f8fb695b5f6f
+Qy = 6fbec6a04a8c59d61c900a851d8bf8522187d3ec2637b10fa8f377689e086bba
+R = 1b244c21c08c0c0a10477fb7a21382d405b95c755088292859ca0e71bab68361
+S = 852f4cbfd346e90f404e1dd5c4b2c1debca3ea1abefe8400685d703aea6c5c7f
+Result = F (4 - Q changed)
+
+Msg = fd2e5de421ee46c9fe6290a33f95b394bd5b7762f23178f7f6834f1f056fa9a8831446403c098ff4dd764173f974be4c89d376119613a4a1890f6fc2ddff862bda292dd49f5410d9b1cfe1d97ef4582b6152494372fc083885f540c01f86d780e6f3e75a954af2190fdae9604e3f8ab32ab0292dc0d790bd2627e37b4b4885df
+Qx = 633c2ee5630b62c9ce839efd4d485a6d35e8b9430d264ffe501d28dbace79123
+Qy = 4b668a1a6d1a25b089f75c2bd8d8c6a9a14fe7b729f45a82565da2e866e2c490
+R = bf2111c93ec055a7eda90c106fce494fd866045634fd2aa28d6e018f9106994e
+S = 86b0341208a0aa55edecfd272f49cb34408ce54b7febc1d0a1c2ce77ab6988f8
+Result = F (3 - S changed)
+
+Msg = 4bc2d9a898395b12701635f1048fbfd263ec115e4150532b034d59e625238f4ed32619744c612e35ac5a23bee8d5f5651641a492217d305e5051321c273647f14bc7c4afab518554e01c82d6fc1694c8bdbeb326bb607bcaf5436303bc09f64c02c6ec50de409a484f5237f7d34e2651ada7ec429ca3b99dd87c6015d2f4b342
+Qx = f78dce40d1cb8c4af2749bf22c6f8a9a470b1e41112796215dd017e57df1b38a
+Qy = 61b29b0bc03dff7fa00613b4de1e2317cfbf2badd50dee3376c032a887c5b865
+R = 4a96169a5dea36a2594011537ee0dc19e8f9f74e82c07434079447155a830152
+S = a204eaa4e97d7553a1521d9f6baadc0b6d6183ba0f385d8593d6ca83607c4d82
+Result = F (2 - R changed)
+
+Msg = d3356a683417508a9b913643e6ceac1281ef583f428968f9d2b6540a189d7041c477da8d207d0529720f70dab6b0da8c2168837476c1c6b63b517ed3cad48ae331cf716ecf47a0f7d00b57073ac6a4749716d49d80c4d46261d38e2e34b4f43e0f20b280842f6e3ea34fefdddfb9fa2a040ffe915e8784cfdb29b3364a34ca62
+Qx = 3fcc3b3e1b103fe435ac214c756bdaad309389e1c803e6d84bbbc27039fcf900
+Qy = 7f09edd1ec87a6d36dc81c1528d52a62776e666c274415a9f441d6a8df6b9237
+R = 1cac13f277354456ae67ab09b09e07eb1af2a2bf45108da70f5c8c6a4cbcd538
+S = 5d83752e540525602ba7e6fee4d4263f3eda59e67df20aac79ca67e8899fed0d
+Result = F (3 - S changed)
+
+Msg = d7f5da9f4cf9299b7f86c52b88364ce28fe9ada55dd551a1018790f9e1205e2405ac62429d65093f74ec35a16d9f195c993cd4eb8dc0aa0dabb70a503321d8a9649160d6b3d0a0854bb68c4c39693f592ef5dd478aa2432d0865d87d48b3aea9c7d7d114165c9200e4e8d7bd02a7895ec4418e6f2fed6b244bf66209039e98a9
+Qx = 5ec702d43a67ada86efbfc136cf16d96078906954a3f1f9e440674cd907e4676
+Qy = 05a62044fed8470dd4fca38d89d583ce36d50d28b66ab0b51922b21da92c56d9
+R = 75f3037298f1457dba55743999976a1c2636b2b8ab2ed3df4736a6d2934acc83
+S = 19d43ad168dda1bb8ac423f8f08876515234b3d841e57faef1b5ab27359b27ef
+Result = F (1 - Message changed)
+
+Msg = 68f4b444e1cc2025e8ff55e8046ead735e6e317082edf7ce65e83573501cb92c408c1c1c6c4fcca6b96ad34224f17b20be471cc9f4f97f0a5b7bfae9558bdb2ecb6e452bb743603724273d9e8d2ca22afdda35c8a371b28153d772303e4a25dc4f28e9a6dc9635331450f5af290dfa3431c3c08b91d5c97284361c03ec78f1bc
+Qx = f63afe99e1b5fc652782f86b59926af22e6072be93390fe41f541204f9c935d1
+Qy = f6e19ce5935e336183c21becf66596b8f559d2d02ee282aa87a7d6f936f7260c
+R = cef4831e4515c77ca062282614b54a11b7dc4057e6997685c2fbfa95b392bf72
+S = f20dc01bf38e1344ba675a22239d9893b3a3e33d9a403329a3d21650e9125b75
+Result = P (0 )
+
+Msg = e75be05be0aaf70719b488b89aaae9008707ca528994461db7130c4368575a024bf0981c305d61265e8b97599ec35c03badd1256b80d6bf70547ad6089b983e3bcc3481828f3259e43e655e177fc423fd7e066bd3ed68d81df84f773c0f9e5f8bf4469960b8b4d7b2a372fd0edd3521f6be670908f2d90a343f416358ea70e7e
+Qx = 6d11b09d2767cf8d275faee746c203486259f66dd2bfa3a65c39371a66b23385
+Qy = 4eb05c73e05261e979182833f20311e5366f72f4b949665ff294f959375534c6
+R = 15a697cdb614e11c0810e1e764cd501fcabc70874c957587bc4883d9438e177f
+S = 7bf6244f92bc768063cecb5336c8eaacd23db930b28703560f241c7d93950dfd
+Result = F (2 - R changed)
+
+Msg = 0dc4a3eab66bd2e703a8fff566c34d466f9823ae42bd2104f61a6b051c0b017833fcef4d609d137ad97c209c80eebe252857aa7fafc35f16000a2bd4b4be0fa83b6e229eddfd180101f1f40d0453148053d8306833df64d59599b90194b55541d7f22dd589da9f7be519cbbb9db416c71bfe40ec090b5b7a600eec29bfd47306
+Qx = f3899caba038efb534c4cea0bd276814ffd80194473c903b81af11c8c05cb6e6
+Qy = 6ea6b17402fcf2e8e737d11ffc7c2ed3b2d0bc3b8f271a381f4294cff62682c3
+R = 57b99380452e1d37b133c49b9ba493dee8630940477ca3351a43d90b99871e6a
+S = df599c3a37105af3ecc159b3b685ccb3e151b7d5cf2d97147974ae71f466b615
+Result = F (3 - S changed)
+
+Msg = d55e5e124a7217879ca986f285e22ac51940b35959bbf5543104b5547356fd1a0ec37c0a23209004a2ec5bcaf3335bc45e4dc990eacd29b2d9b5cf349c7ba67711356299bceab6f048df761c65f2988803133d6723a2820fefb2654cc7c5f032f833ba78a34d2878c6b0ba654ebe26b110c935abb56024bd5d0f09b367724c07
+Qx = 1fd6f4b98d0755291e7a230e9f81ecf909e6350aadb08e42a3262ff19200fbd2
+Qy = 5578fef79bc477acfb8ed0dc10c4f5809c14dc5492405b3792a7940650b305d7
+R = 97a99e96e407b3ada2c2dcf9ceeeb984d9a4d0aa66ddf0a74ca23cabfb1566cc
+S = 0ecac315dc199cfea3c15348c130924a1f787019fe4cd3ae47ca8b111268754a
+Result = F (1 - Message changed)
+
+Msg = 7753c03b4202cb38bc0190a9f931eb31858d705d92d650320ff449fc99167fb3770b764c8988f6b34ac5a3d507a10e0aff7f88293f6a22c7ed8a24248a52dc125e416e158833fc38af29199f8ca4931068d4ccaa87e299e95642068f68c208cb782df13908f950564743ed1692502bafafaff169dc8fe674fb5e4f3ffd578c35
+Qx = 2dcbd8790cee552e9f18f2b3149a2252dcd58b99ca7dc9680b92c8c43aa33874
+Qy = 5dbc8bb8813c8e019d80e19acdb0792f537980fecde93db621aaf1f6d0e6ee34
+R = 2bdbd8b0d759595662cc10b10236136ef6ce429641f68cf6480f472fcc77bc9f
+S = 7e7df0c8b86f7db06caf1610166f7b9c4c75447f991d5aaf4dea720c25985c8c
+Result = P (0 )
+
+[P-384,SHA-1]
+
+Msg = 222638def3abc9e846fa506fa6e05ca6bf35a13947147fbfaa20bd0c3c7fa836bac8a0c257573d32f05b6387eb3913af4d14d421f8b3ab6eb182542a48be0fef76466c7fe4acf7de2af7ccb82caa1a37f8be08db46f455f9b3ed7d006b0cda1f0a99e9a09e4caa00d11b143fd645cdcd402af41536eb89c9a77b0ff47d46baab
+Qx = 6881154cfe3f09affbee04cd387b27b7854326faf8906c4b9c9e6ac2c632e0d59717b3f33f6d747d7b7cbb4e4dc01fb8
+Qy = ba295ae0966f06ad9d84b3bb4da7f99b56044c99f88d71082cfea6964ea3c63bb79806a6a41fcc314b55b3f64f82b68a
+R = 2112385a75d4edda89ae2bc3c74524dc792544a3a52fdb588da3f0feaee6a11623db275e2ab8abdd998cc42a29c60856
+S = 8d308a3987b81c595f8cec19898b1a42da8eda97496af280033b0f915283f171fed7e2a221fa9c78927962189333f437
+Result = F (4 - Q changed)
+
+Msg = 7fda17a3d3bdaa614f5a180211867fc08cf4a6de1fa407498b990e6730589e6eee8bcce705b15a67be22df10d58e62199e6480efca7878516a92020b0544bd04bdfa05f74ec61c43ba392f933a9dca5490927532b775d300ae4171ca9a842f15973ba98a4edd2211340d6c9409649329599f38123c02441340959fc1b5d73173
+Qx = 2f2f43f244ae027c3d2ec5c900393f80a8ad0e9b9a12a047195d29a39f2b7026b071688dd9a6764379d02a5ed8035ec1
+Qy = e43d45851bc76c37d34dbed996a65ffcfbbaf0e2cbfbc9f62d2116bdf3b330bbef5acdbcd0aa6d949f771daa17cda1e3
+R = c011c52e9cb02048957a233704ff9a2c1d4c56e08ebb083aa8ba351f041a23a7d0da19088ac6c60ea2ca117531c7cf35
+S = a66ca9bf06c35d129a8253a0f793acf681e482d9994868b275a230b215286e03a66a0de77c7a53174375137fd4688556
+Result = F (4 - Q changed)
+
+Msg = 053329a0b61466a6198e05d23c287a9f8b4cef88bcb5916da9a50b89b67a659430f46183d28463d397b1f10056a911debf00acc99df49451e146458332517ed7b862fe41f008dd381d7ee2c8e78942c56a147dacccb966ab803725e6d423505e027786baa13fc0c7cd5efb268e3dd8b0464629eebf88e487b8901d22c0b28863
+Qx = 9a5e1932d318bfa7986f0dac4489c6f55775427bb60fb24bac7646b9994bbc3a9b5cd15e818cc4e832afc1c3fca9abae
+Qy = 64c89e7c3399c136b2718ab675944207157f0bf23d9e2a807ae7ac3bef81da7ec3c56c2d2c08afc53301af2a3cc71861
+R = 4cf6c63fea6c80efc105cd99afe2b53da05ae16566ddb20b9d40a076575ffac419b6807fa336fc6e7c7416c59775ef09
+S = aec2d96054b4b23c49faaf9903ccf63bc96281fb7c1b9d14daa54bba51bb2b2f4d3a901f3b0b9cb2b62976459219350c
+Result = F (4 - Q changed)
+
+Msg = 33602a6ec9d3807a3bc3bac1a4429865d64d1c1d3715d62cb5f22cdc46770dc991b70075691fe4243cb6a8633b517635b08ec442b1c6ecac08efbe54e7c1e7911852a5189833b0bc7be99c2ea94337f86cc295f2c9c83d0b50e494908e6e4519052f7aa1d905a1867a1b6dffa62760b6bbe26e3cb88878b50a17ed5fa8e1ad1e
+Qx = b3aeff27b65540c6da10a88008404b1d49239c87fbf47932518fb87a9bb132403d1f310f531d086340bb4a68c3e64b9b
+Qy = 567e75f442fcd81017b8adc4cce634f5ffa3cd497d38221d34dc1f43aef99133131ff1b197f7b9f37beecae5c438849a
+R = 3b94a2514eb915b71e18c867ad7f508a35375c5bcd4b797b86054798569870b2477e2ac14406628017d829400efc63b2
+S = 179a10441a0beea3b375248e697e0d19e24bb68184c373fe4302839b97dd7353a5a25929c2733796b0c0d8211bd67c51
+Result = F (3 - S changed)
+
+Msg = 3f0783a58e66f3d2c0ccfb5fac3f09db6f8609d0592bc77fdffed9cf0e137d26a867057665f3ad81beebbbdb723d5a47c580828f10f7347ab8a9c24d195f736dfae6eae37d88fe3b4735e7c669a80ac1913e5c24c8c1d5cdb15f994f3ec2f1c774752e14f596b38c2fbf037616d608244d3da7d4badf351330f947e04cc350e7
+Qx = 0874a2e0b8ff448f0e54321e27f4f1e64d064cdeb7d26f458c32e930120f4e57dc85c2693f977eed4a8ecc8db981b4d9
+Qy = 1f69446df4f4c6f5de19003f45f891d0ebcd2fffdb5c81c040e8d6994c43c7feedb98a4a31edfb35e89a30013c3b9267
+R = 8d9d3e3d0b2b2871ea2f03f27ba8699f214be8d875c0d770b0fff1c4ce341f0c834ac11f9ec12bfdb8320b1724c8c220
+S = 62150dfba8e65c0c7be7ef81c87241d2c37a83c27eb31ccc2b3c3957670a744c81be6d741340b5189cc0c547df81b0d2
+Result = P (0 )
+
+Msg = 66ae60b818e65b19c0efab7223a38dd7b8ed1888494bb01dee42d0f0c913ff9f2e16e146a5533956e28af9e8c46faaa0041cc74469e639257b971ddfb17100ab78363439ff2b3883bd17d54adb48a58b75202b4cd5aa82493417bf230436b65cfc3ac64a8e1e874b7b64ca68bcac1cf30e6f363fb2f736502d3e41940ae248af
+Qx = b4b92211edbd41c5468d2ba70810bc37b5e7c954c7bd0db80c4fa89ccba10bf07cdab953828a068bc0104d28e4040c14
+Qy = 93ed318efce3dff98fc782b788d78658ea5ecde4f716e2d5d0ec2d87a2e761daa1f1658cfb857762caa567baaccf9924
+R = aa3978eabd196ddf9cab2815cc9cbab0b61cd639deaf70e093a10a58ddf9f410ee1ab965ff8fbb98efbe812421a613d3
+S = 02761a2947e1855806b8a25b9ebb0762be9f5517461a371e5783f34b184f32c4ea684b362119b1a2d8a3ff439f10291f
+Result = P (0 )
+
+Msg = 11bfe43227da93f9ef79a85c243da7e5893a720724f12f9a64da942ae1ad232e158847c6817983e70325dc4ad7a9ec5e3780d4f376a7cec331f33a8b4171e1ee4b613f8de1608cf9b72fd5621ca36fb7aecb27bb432d21845d8b05e3a4099ad2e458409e8de176d5187af0d06f9f2fe2b9ac9d609ba1206f49a88b2d11e3adee
+Qx = 63b4cc14f9efd3b8f29e65806591d1e9c54f34a3f5231339bcdbfa4109c42d946a59cdd7bbd2591fd1b2383a0819772f
+Qy = 55ab3d208109da6ef039c23cddd52a5af619266d8fe066dcabb1af885ad5501401a78c44ed3b5fff2892fdcb2a3ac8b2
+R = a3f9b840fd7201356f35b5dde39027410aad26ac61919c14fe7b0535bb74e7218cb3312bfa60aac63f14166f32ceff26
+S = 1b1bcbcb0237fad4e406c8d4e3e39b55642d8535afa9ccbc9c601cb4e01891df79f1bc792687cb3a5ee7703565c4a13b
+Result = F (2 - R changed)
+
+Msg = 766c86593bd80ece725a75108a2fa8bb9ee5d13d4d89d0e95ca3105816280d2a82c4f8bc6d2977a34699b37bd7ec4fd5237ddd09ee894ef5311128487ec1cd8387ac24dffd62515bd1fe46087c6f0fc1c37f84aa822fcff167af5c93a2c6e2811c9375a940735d639f856061fdbd28bc400302112b9ce7ed45f2045d9a03ff9e
+Qx = f82f82f8f7454ce7a94a040ec0bbb52d49e3b9f8ddd095704973c760ee6067a5c28369656f22d70d8bb1cd70ef9bfea0
+Qy = 0e36e256d02870ee5646a17aac4b280c9d1d2e1d4803eb3cb32e7f754cc889522120efd7c4d8a82e509a4d8f266d3ce4
+R = 27a2332f3c59464f5dfe7bb1201a3936248d375bde603724c048eb8f7c0c2be3ed4b56c14b51d7d68bd2554526b36d9e
+S = e1f90367b0cc530c545f95163d9ffb1208c943685d5ae221052b83ee40953397be581e5979c9855b20246e9d26d57acc
+Result = F (2 - R changed)
+
+Msg = 1eae9b93f81846153ba466ce52b83c1ee8f2589f88c50b01552cacf14a6bf825b081a3f558005c35f65171b730f33efd38d33dbd898dab5315e9c8005e8d8ad6c026b37b480d04245b3030fbe3fd44141f8a015d45e9772b327cf9f3f3836a9bdede73a1ba0f8236dc17727bc7f26c32d6328531df081fceeea80aa573524f35
+Qx = 7d40b51127cb1642dd8538d4124138a2f49c41b4d12f702c1b0cec8deba50c3712e01c2e1e693e00438af0e86025da33
+Qy = e734b5939b673c45dd32baf20d234f01b7124b391d14beea231e9c604e813fc83b3a77b0cb1f2ce4873a69b0165e369d
+R = abf16821b6657e0005071f78c679cbbb130bee6e7ca63526eef0f747fb721feefe6258dae1aa02064a700e963bd9dedf
+S = 3f7e61c34a30cc5ff7a8be375fcc9c38a76dbc0c30a4356843421ca37a7bcf24edcd41d8235903bb522fb6e5a8033885
+Result = F (3 - S changed)
+
+Msg = 8e25d2238f24f2b9c3600eb6ac8de5f8c42accbd27939c0039430a2b656d5af7d287f83f139b367cc0d1fff2269ab3912199a70a6af4236e0079d2f22c3a22594a030b40445663c787a5ad0e2107b8280538e02267ea4e36d1f3a93df06302572b93eb0d5928d842cb2cc30a4f5bb319ba274d3abe905a0596a655d76e839feb
+Qx = a5b59d59599c105e39f61354da99c7c9135c749cf996cc2252eb83b008299cdafbcb44227d2d2c4a5ffa44823922893b
+Qy = 0399fb0edcbfd0b76b524f22b7b87ddbb4fa02f510661615312a4492eb3f2001e0fc0e479f77c33a88f9a7e20757373c
+R = a4c9cac2409a9bfea1ebe28fec4e19545f08cd18fdd31048f52a3f2d32b2ed859dcae4dc12fb2fecabe542c4f03191ba
+S = b4d83f927ad1980d96cbb0ccc36aa640f786293b8b19e4dd97a797d192b420f630a5e42ac42d8736e7d42008f445dbc1
+Result = F (2 - R changed)
+
+Msg = 9b128ae06a780515c734a7f98e4c17adac89bdcd60fcb0a1d079d856c69440d6cad4952d73f0b3fc399638af1e9eb3944fce8dea9d3de7f91730e11b0662287616dec1137c191a06e628dbec01a99eacc494db055edc54ebff99f7161d8d04aa5afa9244a1adbc87d8d7de67681310a42c9c232aa51632562b0bcd52b6dcd0e1
+Qx = 29178ce9127e1048ea70c7d435439e9ff9915387e51b7e5ca10bfdafe53565978eb3784d9a4226f443d4834f4d451685
+Qy = 5cc2970589a453488649711bdf3cdac9a200519aae65b1c6bd54fed0d965755b36b74d978d674275bd71a03e8f054b0e
+R = 5d6f5e9a94d9c92a0890c558bc0408b3405cd04e33f663df16701e80520e4394f1c54d3c8225d36f4753a799aaf6ff90
+S = d895b1cc522ceec6a7867867b8f603245c6e4d48945dfc43af721ebae4683d40a3c21b905ca3bd4b974d36806825b2cd
+Result = F (1 - Message changed)
+
+Msg = 8d94d7b6b6e16b863be09b9217ae9488d8cf1f76aa344dfe12cd32a702c2ee7f2f5802f97c041aa377a365193aacf05c8aecb505414fae1c88a2954545134d78a7fdec43893ec98ba7584a018815c869c22219a816c4dd70a48e24e78d08a3681fe63548810b5f0c31415f6d2b16a141de875c262b81ba95872dde37bb21c75b
+Qx = 9f03569f8c6ca2c16d707f0ca36a8a8cf214a9d5c14034829d709e283cd675eb4e3090c6b973429efdf476c0782e0a7c
+Qy = e1b842536731e91596782787d57af17db85dc92fd2fb95ac65339174aee66775ce0a4721d1faeb29da968ea5eb705e59
+R = 31ccbe22a360b1786dac89394c6ef4ed6604943e50837395f96052821f6182914840096e90f2ad650917bd91d7bd4cfd
+S = d97199a6b952dcaefb1defe23def92bf2ee236ad18046a2ccf8924d42ee10a62e70ffe7f3c909b11112278f160d98b7a
+Result = P (0 )
+
+Msg = c3221ec7fa1ad3f33665614e9e2512b853c7b9f515ffa78a2405f1b29f91e87acc2a69564d25977411dd3441120c6c14fa5d479b1526de21667c696e692112563d9a8ab7146dcfb042a33bd5184deb581ed80ad22e059b7b5ed8c5fb51789b82b2e87915b947b8ed452c2d8b0c62f80e15791a7f7cc3d7f47d2437412a6d4c1e
+Qx = b85e78a935d169dd5ba8f558f964b21c07804464816f9231233184675f557463a8b00470ac0ca8278cd008f4642e7962
+Qy = 8edf7be8584c5f207939d479e65173e2e69673090a8538fa93efb4432127895d92b4e4cf13b7632a830e9a33b37f75e1
+R = fd2876b250a94ced71734aa7a0d32423b2c6f039c926c557e748f38e23bbdb46e17d1204832c6f76c3ea854e1da23979
+S = 76409e381799502c81194ba87540aec0b89fc4680dd683780d49f82a46a7191b40f5f06ccb02e45e704c31fcd59382b9
+Result = F (1 - Message changed)
+
+Msg = 6485b69626904d88f55350dfcc3dbb46bf71e1c59a40be5b8c9e52c491097839d5849dba67920d866d8494231d67b36b0cec035ced20a47e679ffdad4918e566bfbae52ff34f2c74a0c79aa82a62e0bbee8c8a10fcaf915d864c8febb905ea2e0bd1e671e0d365667143f8a564828b975f3d797c65f1811a487833006876701c
+Qx = 0c74aaa0527524cb6171ab741896b405a6ac4615e474cdc09c9457b18bed33c6383e1b92f2fa1306e8e5dcd1667e45fe
+Qy = 7b00d934dfd876f6e07dc0582b20ed650be104fa603a5a1255c62b6059d2685aa9773f1ba31254d213c815d0efc8ed93
+R = 832c62b0f34986eda9d1ace5068a0c5318051b0d0166d3dacf137ac072cc359f109ad6e17059e700bb1958bcf4101246
+S = 6bb56f4eb550688ea66e5dd09aebe7e0b39e2716b4697ebb68f113e080f0ff26fd0fc947a34f3c5a8a2f10e07dc1405e
+Result = F (1 - Message changed)
+
+Msg = 83170d2ea8cab8ca6da17af60d596c59af3dd9d8ed319930c0c328fad7a7a12a8127fcbd6a19f64e5bb2e26f1ce3ca1848df3a5b20d220b21410c010dff89f271b816942bc7fcd63c3de218775c46b9090a67fd4c64e2e8447aa755e68db28084f99a1393092ade8f72ed00e61c28e9a262093fce6f75b8e28341687b1aa4162
+Qx = 4104de08b4108ee26ee239e0a5d340c1b1aa48b1b3b40717debd6ed3ff0d777923c106f857a3830ce7f3d08d0d6d7908
+Qy = 00498c38393e6393edcf254804558f86e461df1f5a6557bc5144f8d2f3806413d372b6ce417d531c08a52d1e38e8b949
+R = 9924a3273248db20db007309560a0e616572ac799d773529a5215786cf4a6e03cc73bea81d4810c1eee4b5e975652eee
+S = 6cc8ea4c4c56da87c25946a198e86917227bcb90da7be1dcde7b6547bc45a98e8175dd54af15bb6ef955b4cb48b7bb0a
+Result = F (3 - S changed)
+
+[P-384,SHA-224]
+
+Msg = 97d4b3bf67908217a78e5b7817a40b56acaf6febc774dc563f34788fc7c01288378d28ed6dd7cb6174a72e64a663fc155f5f9d41f7dbb647996a84d07873fb789052187f7b8ce446489ea94439297b78f6095a96733aa305bbed66bc8cc98f87a32d14d87231350e167b65a9f7f25f75eab41a5dc24a66c1c3fd9dedfdc570e2
+Qx = b6bc9418f3da0cce38a65f1b52bb3a9d22a0368e02f5f12fa1f1303ac67df1cffa55d049a782bf5bddb5e841b125aed6
+Qy = 3b578a0560280a2958a14286e10faa7f5dec77fd8d90123aff5780efa8a636cee833fc9f10d7a164f1254a483b613746
+R = 6602090aec001c16e5f6e7e3e488bed5d1702d36b258b6a8a2d8392a5ff30a6af12fbf4308d67eed6aaa8b7be8b831c5
+S = 65d0c3bb1910ba0b7cc108ae1ccaae63405ff01a8df91021e17cd46aa6f8ca8f4eaeac6d6fc26fc816a3ea537fd9576b
+Result = F (2 - R changed)
+
+Msg = 5ad75a561dfbf320a9c0ea8d51caa9268aa855020f16c2f99dd46e42142a5a3b930f5f7a7f76ac9aca5bf659bddf096c94ab3b2a43dad7f97e12803bba79a396a1782e3b72891ecb18d3e37caed5481d3f8ee32af62a3d3ac8a50ccf855b398fcc7930d1ec201494f5357254aa4de5f27de6261ed0c45e255c420ebc3c7cd4f5
+Qx = b4ab83a4ded7d76aa15eaecb1bafe59427d3cfc38564af9123cb707da2405184acd40a6c093ba29e321ba0f67c1e0c6a
+Qy = 26e2902499495f8550e798617a44ac9990c4c1cc3527dc0dd003a15aee3cbd3955151f7863de1692a94aafd3730e7665
+R = 61e48d5a100049578e820768ea57f30f27ffd1a1f839fabc55e8f4816c9b95d042619cd3bcc7180fd99834e344f53e7f
+S = 977b81d43216f31d8bedc3ffe873047817de3441df8b80a321aa0a80931f25a15c6628f43cf8e48d5c6aeca7626b0a18
+Result = P (0 )
+
+Msg = a183efd409ee179ff142421d133b2f811e49c8fcd3091c187d032d1ee5a7ca18b4db7e4a7ce582c42cdbd7caaf57f5aab2686edefa7028b31198e7ea349a507e71b3bba38f3fbd96ea2f8e2c1d11ba3b2f9f2bad23a255831ef0ea5a4b1caab8580fb0ec6e072fcb49d8dc466c5d47030c98f26d512f2f81ab2f60754c165771
+Qx = f886f36fcf34e8df2a7e09220051b9981a3a6f693ec5999f28864e012c13896d633c9564f0118a95631cea8355b25b20
+Qy = 746f9a77835325f18338dee5dc88a9b086b858ce15b4e4462a98844bb01811195f4fae0bee8f457c32823e142210dbb8
+R = 665390653ed280b8f6bd3718d8423f26cb38d2d7faa10fc0f094295677d9dafad45fc64cfc22ded56afdd86a77cf3c33
+S = 864f0eb3a8d93c388d987cfcb60bba76098039d46bf4ff4be083961f70a29e724c25cf56685802b7b5be048107ad52e3
+Result = F (4 - Q changed)
+
+Msg = 036a7c7faf2cf08f55a1a841ba49f8222dd3a04a95736deb02c2cc7317bde1dac98eb2934ef608886889c5c7bcb5ebc97f76141ec1c3adfdb7bba7e3cd49634c3f4c478bf4d4b5e89df33a9817c5fbb6862493c1185bfca9556bd340d80db521f39ccf911bf6be6351313e22c2f7dab3de90dd83a0ba00241ef1cefaf8f9f261
+Qx = 5fc835a2f5429adb719ed22f11dfcb02731da6759a8ea75c21d1af9631187626c31e191f4dcdc183df01c48e13dbbce6
+Qy = 9ed2d03df1cbeaefd4478b8106e90f92e0b6e958145cb81b9648aef0b96b71d1d55918564694b1987d68cc8e7cbd7dd1
+R = 94d9dedd27f2d014ba84ea58d2e88d68f3e86ba88b93750e50255211effe88b0a0e2f62017f22965726cdc77c55bca4f
+S = 14814bd09d9b7ba81b2485777cc588b5c0a4064df95c63f18a8bfd57494cd0f40c5bda9dc6c01ea72540f57a354360ef
+Result = F (3 - S changed)
+
+Msg = 4df76be123a2fea6ff22da2099e1d6a6d69083f5e536155d96008eaa25523e5e500b770da5d1d73189b64eba6cfb7eb942e6da31f9349c5cda966038192f25e5c7762458ad9e5302b4663b34c53e1b30ee10109dd05f2bdde6204f0a7d0c454b791772ab5f36af13ce70fcf914333e0840d71749da7c7049c448b37d679873c2
+Qx = 0b86851d7c19f0f04a16e5e2903a36d09bf1863e152d87936fb2d74cf916bcf6dedf3c066d242f7dd327df0fcb42270a
+Qy = b0c93480740bb635e6c25fb61630fdfcc462a1418366a51b1265656f721e18ba89ebf754c7dfdad865a252c884a6c4fc
+R = 33fa5fe3e495076e90f4b62753d3cdc7603aa7f5b407dbf89a854b9521d15e6c381d3cf28f103035dc4291ae318c5f82
+S = 30919a2a3fae71e1afe8378aedcaa08fadfab6c6bf954031452d4fe514969ede2acf0347a2f1e81abf1bfb9d8bd55a36
+Result = F (3 - S changed)
+
+Msg = 8291e5acf7a86f9003c1c8e962efc862a69445ce76f65ba6f861900c7b69b2d711715cfb6cac0f757d3bd5d7af2cbfd7f0283f21f43f12c54af4234a1f28e3a326d14465e991f5e5a4e9fe80aea34324024ce34becf4e9ca56cf5fb66601ca53e20fdfdf353d5356be4c9919f0f7eeb0783d8c7c5d86e85ff39e42f016fa9313
+Qx = 6f8f2fc40d1db28309c8850bf94d77c01c5449b4fc556e6bf50e5ee805209c4489d8ff9bd781699eb0e42f6a962d56fe
+Qy = a4c7c77271dbbe7e00d1c6e4287dddc5463c6803a577a18f89a5eea01c6addc12404353abbc128cb9cf2496732312d65
+R = 327c4642019a635d80dab82f7dc22e3102a3c1ba684c2b6de67d3d3009a17d39ae3d58ca2caec9f6f03f5ba3b406178c
+S = 6b1af807cc7265cc6d3049959cd7779ae0de819036647f9510b0e9f7e4c0e3fece5fc3741b68881145a2c944dc5c54d1
+Result = P (0 )
+
+Msg = 1266b69134087b06d6bd8b34aaf56093bd0fbec845a34e25b3d9e9f81897403eba3e59ce5a17317aecec8678b8f1322448b1fc98c99edd20ce085e42833f848035c80ca4427d672d4aef75cd9d0b87030b04472ebe816b6fd3ea86910099e8b89ffff8796712aebbef874b7ef546c32a7c5bcd5a70c2751c7751b346139f67e4
+Qx = e98ba8016a976dcc3c50127d2af792969835b1096b1644b37c004d1786f4fb1026233f33ad56cd9444ba0a332c92efb8
+Qy = 54bbcb78ffa3c855dd24bf182376ff5d28dd7b7551e4b05a19549c9f59c83dcc12a43092d63c5967fc0256612475b7d4
+R = 3b76a0c0ece2348085f3554fc92b9e5b0fe84801ab2adf1d239d7c81c9697b62285e8e5667774559d1bbc6e86f2ade64
+S = 91d929e42f8223ccc74d4cb09ee7eb619d3a348886c21091ec55d36164ad3cc04e1da6edd88ad89710a908ca4bc00333
+Result = F (1 - Message changed)
+
+Msg = c8dfc2e32c6c77a6260ba03b204601245dc999e8915ab0d8878e71580ba47e5f57ce74f42a8ee3ae0fcaab8adf7a10a5c46213b7a63c98e614ab211be1498524cf032c5bf3738b73cb6cbfdcfd08984dbf6aea2ab0b8cad764f6a0668a6a9536f24b341dee19cb74ccac9d7a131e3eeb20fc1b51d4620c33285fa81af13d1820
+Qx = b8d7a836715635a8b095d3712817aa9e6ffdd98d24be2db751bb0c1fad42b082542500ea255cde17525ec159afca7002
+Qy = 1a526c876d4771157b4f66e3056485c95066d4bd1e73e991ce6d5d3642807efe80015c52ef3cf8c86e57ab9a510ec86a
+R = 9e36f47ec1b7ffdc6e3472f3cbec913494c0bbaa0c073f597e01845b5a3107c0e23a4575de4f2b582e1c2fe3067ec048
+S = b013cf51008a89b379a2a6b519b8d229ff0374401eae21a8da350fe35756b94168e7fafbd81f0f681f21c056941a82eb
+Result = F (1 - Message changed)
+
+Msg = 374d67f9a9ad3861d283b333192d92ba9b261defbb42e86c348c94ad19cc292f81131be674c3d82d5f5bbeb1c2203249244f6f6b9aff3713e00726419657bd0523e823811a8298b36a0e0c1ca89a580a99d1d7e0e53ab7c572099592bfd78526fad344723fbbfd31dda66bccc8201ce3845371e4d3c5bb761b9f84a7d003ad3b
+Qx = 4ffdecf5d5f7c1164297a93742c8a685bb425b97fdfe85f630dab2064ab29e52a0df34629c2531048c288216723fc9bf
+Qy = 84fcff3e7e478a6932ace6f6b0ab70e61d8a5137b76886c59e721d938e0e252e2f7e57c2ab7dab90493446ad85c3fe4c
+R = 7d909d9aacf064c32d070c3149ace8b8f5d83b2006e8460b84c4bce664fc20e91c61ac8b415965b6155eddbe9238fe3d
+S = 19d909e358e71985179dab9113941ecad21e4f3608cb3a32dd065868af1657df8e06aa86855ac7ad757a7f8fb568a953
+Result = F (2 - R changed)
+
+Msg = b8b8c4c83472ed63cdc2b4eb4bd2fe1d6d9989ca15369391a3cb6151a997d69f219fb60c335cbc602b1d87ad2fa084bb98571de7189be6e28b025e1e76eddd218e2c370ea9e232ef466f9807660d0d86a35d8aacd707a581f962baeed6f5df2e657dc3b93db5a265f81f17a4fa9ff20911dd9c7236cde5a1446562f0821f48a0
+Qx = e805e0733fc156bd582faaf794e58d4630ce73fc383cdc964dd337728f774e4989a697d79665a3282ee6e0ee343d6c7b
+Qy = 43821b7b9a6ce1ddf0c59ada552668a0cfc85a87a610b5c36b7a691947116b49a4099340306e53494fc6b496cb8d12b0
+R = 3d4fa4ec95b55feac607fddc618d6f4eed71da65dc49d732e64460e5c80c57dc4421c64bacf3ef1e22995fd19c2a3cf5
+S = b11898ba475f2b28402d038afc15f171b99aab93437b35a2f8a3b89f42fdb7f93a0469d9da7652882000dd5bb1e8b9a8
+Result = F (2 - R changed)
+
+Msg = 5fff95e8e8217950e0a1d33a48d22802ced612a4297b4208422312254632c8141bab2f6217d2c881430e4c778d413f8fa44ea3d386414eac99865fa68ebef645bb65b436296647f61ef8956a92c7ca6a25e85230b08d16423aaec9917736b2e0a4449c0e38618c08ddd36d6d5f0c63cc7ed0527564e023a4afe8ca00219306a7
+Qx = e15c7ef9791b9392c3e97389f2597ee161545c267e584b94262870ef25fda348f72349f396c27ac884fa8d776387fdd8
+Qy = 107b4a7da8be564a14f9c45e4df5cc9b62f0671b3f2c0573c33fa37f985fefd1ae3ff2640947ebb12dffda72757db6af
+R = 9d715fd1a3668283fa83c407242e8d2a4f3fa1bf41919ca4101114bd0e0ac1b16c4379edb11de5210eee8618d42e9ed1
+S = 2dc37f453c8cfe01ea80c56d1865daf0f28847b12970132a1853c3ed80da6693e0da47a2476207947f29da34d68d604a
+Result = F (4 - Q changed)
+
+Msg = 019e8ffecf34a14b9a3157911badc6732d7035c4e789ebec4d731b3758a42f23e90645ba6410c3f84e7385418a30ad16d5c7d9971b4c05d17a5a4a2aac93bfb79ffcbe80245b0772adc0be7fa6bf92f27f2a4cb1e37f379a305fd4f2b495bb052ac9a0a64a0f29e18302dd6091cd009dbf30d9bb5e2bf43a20e08bd0e39a0382
+Qx = efcb97dd73106b0a2be4f665c496352f6938da9d0fa97690dc0e8d018b06dce2ba8d19b93ddfe889d549a33e64497c31
+Qy = 66a0cb7e64f40470b6d09b9e12f217b59e9e6615af52fbdc4ddcb379e77809361eca2093a3e24c7103e971567018400f
+R = 4ea5d4faf8ee52540db2f4c6283cea5302a3540a56e14c8a7533441c248465be99e10f23bba85be9634efaba7a8b172e
+S = 4c98a2142ecaba7db44c78658efffc1175f810a147306ba2e6498553526adb1507d7a99a372e0f84c8dbd160ef7fd5bf
+Result = P (0 )
+
+Msg = cad0ae6215c97b946a7082d5c17c5304237d75e06256e355b0cb481022633825414a7315e50ff33ed0d8fbc52797eeeb418f47e1bf2b748681f114c1cdce606c6d425974ecb10ee4261afa9a47bc0ff9d0aa191a9f4365a56ee182515cd6bb12bd21750908a5585f4e90d857a5ee342c42434d285b2340a09810049d0665b001
+Qx = 4e916a3cf2561580b49ecc52321db7103292fd2fcce8dd4d6f86be6035808e0df51c3c4ac1894f0b08ef6ebf953e0d18
+Qy = 4e6f28895d024b4c71220b27052ddd4bf6115a260825acade48c043b3e06d2b6b8e4ebdf465980f3b013cb575d475bbb
+R = efce00544ebe0d98ba6015c07e3e9d09af808d49a0820c22ef572a3ef9c8a684b377bef1f8b3bbddb734b9b0bd0b1cd4
+S = e80d0e183b3f00098308e20e5b4ae393a07f1d1a8defda9a9d10f19b3e5236e42f593b1dc57f6718dd8d4583f0175ff7
+Result = F (1 - Message changed)
+
+Msg = 7e666122d2a943cd6c0f3af2418256e746bf0099a59a0185cf7b63e2dc2bd16331d8cef0b2dc6eb23febb87b3f012f4e0f3d9f5eb7abb3f23852e7c650facd5453a1311ce13cf7cd4f31744a91090342ab16996e9702f4df3a75d30f91463ebd1e64fe5eea4d28867ee4ccbc07e72ad77c32e5258103fa7118a2132bed32aa7c
+Qx = 3c6528c82d9d5e8dddf41a211c70f78604d81f49853bdc746270f1340a2a645dca3bc7844c3680268fa5973cd1758313
+Qy = 4b9e697f1caf83d3224486bb0a8cd6a7c56e47c91043d8cba3aba51b6e504441d37abcc9b7b2d49b9126463703e514a0
+R = 848814c01c3d18534f39bcd53a8736db16f0f77a015a0e578cbb2f831739723e83b29cb6d4eee7822c76ff056d0f467d
+S = 05beb19f766bd1d4ec5e65786042258298a2dc617e3f13d8e2f0f4b50d934565f3162c737fa791a81897397f29305943
+Result = F (3 - S changed)
+
+Msg = cc84215ee2fb8b76fed16c27b12d7226483dc1eb343682baf341e643896ccb86372de512ad00b91d47e76d9a3ee78235121af0ad791d624a07bfd977f513dfe08aa3248104f43f719259240d8348b849280d7df855e9f4778b9f9529028a9e9af382b6e3f2d619d6887deb335c54ec1ae36b438eae121a4cb300fc817f7a1b99
+Qx = 80c3f6488dcd76f33cdb75e30f8452ab9a3bd6110f14e25179b0aefe4c19c60a07b4af10844b130b0b75a7024e341298
+Qy = 6c85a17ad4bbefb33910250e05ac02a17c892c3380712d06dd070843dff0d040e219dae78679b774cd5eff0adb67189a
+R = bc444deb0c7dd9f96f20a7ffd3ddb35a1189316655531860c39b5f87f09992106985e5562e083ee9f538c8e2d5363c52
+S = 91adde5d47eae80a98661f4347fd6e4778478c3d4aff3cff8aa92e2345a8e03cd4ab64adfd38e461bb98b496516439e7
+Result = F (4 - Q changed)
+
+[P-384,SHA-256]
+
+Msg = a444216c9072caf87fa57c1f04aff9cb83dc2ede9968bda41c9d918825e526c2397cb7d771a7e120582424bbea8ecd56a69bb468cd61437f5a65f04953f9d4018c599afd9edbd4d26e861f86829b9496f829f2b601df73e931fff96559e091417c0d8b8c8129443f7efb985d286c7167b66d2b4d5903583a928db3ed6a883117
+Qx = 97c3f446803a61a7014f61cb7f8b3f36486c7ea96d90ee1767f5c7e1d896dd5114255abb36c74be218c1f0a4e7ebba3d
+Qy = 553ed1fed72c62851e042f0171454f120029adba4ee26855ab881d9470355f1947aa1d2e806a7ff2583660fedbd037a0
+R = 7b06d6c2b63f1cc3bfdaa897d07dc15a83bdf35d979f70c34578332b3f4920422bb24867c51bde10831324df424e04ec
+S = 4bef715161f400dc98d4b63bd13ff4ad4a6c981ead44bfc662fe9bca4b56cd790698e4deddf9a4bd69327f26bfe801e6
+Result = F (4 - Q changed)
+
+Msg = 43c5ffcdf6f9e21aba1b065596745e8738f7b39e1db486a6ae52218d66ce8125fdb155ee281e01b27fa20d0e37d6468a2daedc5fd30573e44b256c5af13df27dea56fd81aef689aad7c022cea77ac3c40a1d64b8c0cf7fb5a128d6a1799da7b8d95308613ceb2260e10b37530edd42925fa5abcdad5d0646ba5bc78c330346eb
+Qx = 08bd5c6cdc1f8c611df96485090e20e9188df6abb766bff3c1ba341ed209ad5dfd78b628ec60998ddfdd0dd029352fbd
+Qy = d9831d75dec760e9f405d1aa5e23aac506dc019fb64d44bd57f6c570d017e6609f8fdbb2dc7b28ca9e00e37cd32a3b73
+R = 8b372c86ed1eec2163d6f7152e53696b4a10958948d863eb622873b471702ac5b2e75ff852149a499e61510905f98e4c
+S = b2ed728e8b30787a28f2a6d3740872e47348686c7cb426411379411310241d25f08a026b853789b1157f1fc1a7f6ff49
+Result = F (1 - Message changed)
+
+Msg = 5edd325885296a829b50b16b17e3c4fc3491f1d53384103f1c09a21a169329e07b3758d55c52e9d578fb9e35e8754bfab9fa5e319d0c7fdb45444eda6a2a0a9aaeaa9b7702cce742047146228f9f687e7684d9b4aaa3be03813c004f0418c1a2fe3aa8ddb3658137d7e954e3683a08e0eaad26c0cc3ae0031b191909a3ebade5
+Qx = 10a784abb3c549444a62c28df1c926b8aabb20c8d9aa4b1f7ca830258857cbe9718dbc9845fa9cbb78587a373baee80d
+Qy = a1ad0c10b5ab6780cad49c8cd3eebd27de8f1b382ddd7a604458cef8e76ca632a7e44e1c63141a742426cec598029e2e
+R = d9e52be2a3f7f566899cf6daaa38116d092473066f3a1bf91f3df44d81bca1deb438d9d25ce1632599c1d3576a30f128
+S = 0cad30bce4b3d7f40b3eef762a21bb1a3bad77439838b13024b7b2c70316875a99e80723a74a9e7a404715ca06a5d673
+Result = F (3 - S changed)
+
+Msg = 4fb73e9e8cbc3e829f99472671ee8719f796dbed096b3cbdf1080ad7f5c410a4541e3526de816fe35ab9e664bb1c1d1e9add2522b9a91eb461b45ae4426e1dfbab7dad03a1392706b9314c03104ea7b40f3632577b0b7c991d2b92460638707572b3387add6ab0f05f6f553fa1fcc50fefe74783cd8b781a35de5ae0e7fc5a58
+Qx = 8760182393132d69011edfa127e36f92eeac8272641c27f52f3337ef8af7451e6d14f4e4590c7eb9fafb76e8c92865cf
+Qy = ebc2b123ed871ca570ead40ae8f6f32335393c569b21b38f626d09c064a3c8668e9fb10a4667e0f0c68bf25ca98fd6dc
+R = 1db957e5c2d294035d7f476a0cbc28a4aac2614d8212de5017076cd836bf04ffe237dce8fec91f2fb5ef82449ff1c65d
+S = 3e3b9058d0a9c5b417f9c6f86557b9d50e7a902694a7012a1be6bb70708497e4d39fc1f6d6bc60dfa52d23cab173385f
+Result = F (4 - Q changed)
+
+Msg = b66ca1d77adf6b2b20c6ef68e50d353a9f5cd0be422f5f6fff8f74506280a55d7923cf047dfdb9147b916f6df6cad8c52257360f746b77edb9949ed4ae9a63d08a7da07c4cf32836574a34f316292b8cc5a6b057129a6baa1182be8a5be1c43739e7d9b0abe07801c2d4343a235037b9aaff14694c051fde4b545931ff9e9a3b
+Qx = 2b1f98d2acdda8347b9a68c75174408eae7de3d6b9c08c26e73ce9ed2ac147b8d90cd82e30ab43909d63f6b457de2071
+Qy = 33f5e6f5f5793201991e014cce0045d04adc352298e32f45f4e374450111c8456b5c2efaec43d157949b5c191b2bc934
+R = 23d046402cbce807d232bcf0dc96d53c72992e0ba1ffce0d79050c0f4c5ad9bfbbdc1c96c730d67ff3aa3edaa3845da9
+S = 2cd46a4fe5d120b3af3a6d9ea63cc78f4079e8b5520a8fa96828334a4f182ff4d5e3d79470019e4eb8afc4f598b6becb
+Result = F (4 - Q changed)
+
+Msg = 862cf14c65ff85f4fdd8a39302056355c89c6ea1789c056262b077dab33abbfda0070fce188c6330de84dfc512744e9fa0f7b03ce0c14858db1952750d7bbe6bd9c8726c0eae61e6cf2877c655b1f0e0ce825430a9796e7420e5c174eab7a50459e291510bc515141738900d390217c5a522e4bde547e57287d8139dc916504e
+Qx = 86ac12dd0a7fe5b81fdae86b12435d316ef9392a3f50b307ab65d9c6079dd0d2d819dc09e22861459c2ed99fbab66fae
+Qy = ac8444077aaed6d6ccacbe67a4caacee0b5a094a3575ca12ea4b4774c030fe1c870c9249023f5dc4d9ad6e333668cc38
+R = 798065f1d1cbd3a1897794f4a025ed47565df773843f4fa74c85fe4d30e3a394783ec5723b530fc5f57906f946ce15e8
+S = b57166044c57c7d9582066805b5885abc06e0bfc02433850c2b74973205ca357a2da94a65172086f5a1580baa697400b
+Result = P (0 )
+
+Msg = cc0aac1010fad8555f81423ac25203720853dbe6a465c244388df90839113d59ea3d3521a8a9cbef649f8abe8d6ff8b0cf17ffc199dddb2997511c4b50e944d41cbcdf5d2102dc98d6f9355b211f130d4e89983f63e5dfe6e1b4ffb3caabd1ad96563fb5c0e5905dcb738a59ec2e5d47684707191ff32746a0cbc65b02be7841
+Qx = 9e7553eab8cc7e2e7396128f42ab260c6dbb5457cbff2070ea7c0db21def1537939e3f02699e5dd460eca3798d08bd6d
+Qy = 892c0c8e47dddf858e89099a8fc1026e8b8333532b22f561f7647f63f9c79dbf5e8dd18fbfe6ff34902233119c5d5aa3
+R = 2452da6a48c3749b66e576e0f1f768d51728be17aea149164c4e1654c5ce27f625a4610c4a2eeddb3a0626d3abc6c37c
+S = 499504fb58c9db24a7ff5f7921e1312f8aa583c08a308e080f5ef1acf5cdae7927c4101573db069ab0b6de7f4f1cab38
+Result = F (1 - Message changed)
+
+Msg = b9d8d5d47edaa2dca7d7d687f98264b6e21a8e1eeb20083efedb71c116d13150d95f62a369a79f0f45233d2751a4b36432c7c12e19c8bef37568fa1a347929398b7ee69046e11911e3db472c3bccbd68653d99e461b4e5cfa617f94d59798f333ccf13abf426ca8be0f6587a453632a50c159d96695ad03dbaac716e811a3586
+Qx = 0cf4dc51e71185a29c0c6fa3c075d9da5bd7ede085053344dce5dbbe8329e8ac9045f7246c9d0efed393b8e113c71429
+Qy = fdb7917b73974b355cf9f3bef6a0a460c2d39fdf1fe32a7744be0a54ddd1cfa8d03914cff4b5ca536b40707ff2629aa4
+R = 3812c2dc2881d7ef7f621993b161672329b261ff100bbd19fb5826c9face09aec2017b6843d69336b813b673c5402527
+S = 5dc102fab9d6325131c556ec00309c2959d1031a63fbc1e2d5d04996d3234ed33875c0ab98e5878e9bc72742519ed398
+Result = F (2 - R changed)
+
+Msg = 6d9cf30d59cc9d6e560e9c52f8be325d19eb3cea592e43bd9584411d76064729c03ad54feb4dce435fb662ff069ca3e19bd16c312567f05018feb8f913caf7553ac728ac787ea3ca073a328633441d7c5cc4d30ec194f248c0701119f7dd80c99e44f469f37cc6726601c97e7d94dc8e549261b46d219a7ea36bee650ccd15cf
+Qx = 6c590434988155236b43147389c6dbfdd27dcd3387e9b4c2587ece670753a542a13a736579887791cf53d31e5ce99994
+Qy = 35a20194ff3f1b55f7ffb2758ddd4b98dd0d9e0cc213e10ed25e8e0430fe861066c1d4423c67f0c93f7ebd87fd3c561e
+R = 89ff866889245e797926509e563b1746920b78c9370a6cdae52663730d131e558e327d1f5fef8faf9e6c802fa29504ed
+S = 8dd68e2de2f788e598b3e5a60c18d81849a0cc14b3b0e3c931910639f3125e5d6045f00330b1fa989252a80f95419b04
+Result = F (2 - R changed)
+
+Msg = 2de0c0671213bd4326ffa5a1070ca605733961b11e9f939f805d2d6974d5286e1b1c00adac360f32bd58432629f8c932e241ffaae742c9336f4c95782d4b73255cac0644c8c2d7099c2ba1fd0cf4243344dd8dc0f77004730f5078479955c385959e06303ef2fda8df81e7237251e3e84a03515505e448aa1330a9a1cd4822a5
+Qx = 499cbdf18ec4e69b88051543c7da80845fa2de8be2b9d9045fee7f104a8b5b7d04e69142de9955c5ab18c5a34ebff075
+Qy = a29cb8d28836b201a389922b6f8f93870f09c80a00242d00d32656a43ac1440fc55bcb123551a73290f603c3469be9ed
+R = 25d4d243da6fd9b439a9242c3656fade7acb7a306e8cf23ea89e3ff4f9330be19c61aaa42d7b426d12c8e0f96b80dae5
+S = e7a99cf4b269bb4a6210d185e9654602523b5cfa1cddc94b1db92018aa557ecb6adda44c816975f5ec1756b6df3c44fd
+Result = F (3 - S changed)
+
+Msg = 69de70edec5001b0f69ee0b0f1dab6fb22a930dee9a12373fe671f9a5c6804ee1cd027872867c9a4e0bdfed523eb14600cfed64fca415188d56eb651d31731cd3e0efec7251c7defde922cf435ba41454a58d2abf5f29ce5b418a836cab1671d8cdc60aa239a17a42072137cfdc0628715c06b19a2ea2e55005701c220c0924f
+Qx = 9a74ea00203c571bd91ae873ce0ed517f8f0a929c1854d68abd3b83a5051c0b686bb37d12958a54940cfa2de23902da7
+Qy = 6f20ccf8fa360a9ec03d7bb79ff17ad885f714757ef62995f824908561dc0c3dffc49d873627936a2fff018b82879ced
+R = acc1fcac98c593fb0a0765fce35a601c2e9570d63ea1e612fff8bc99ac2d4d877750bb44cfb1014e52e00b9235e350af
+S = 7f53de3afa4146b1447e829ebac8f5645e948cc99e871c07280cc631613cfdaf52ccaeccbe93588a3fd12170a7ec79fa
+Result = P (0 )
+
+Msg = 383ab0251157e645e678100ad3431b9ad96c6279e237ada71d85db0ce3a96fcd4805b2e7676e9a395f1d2f14f24535b77160b22d3d1c7d2e02ec4bbd82058f397db468f4d9ff0ab8306f9becd234f7a7b9c5a4ed44b7474913fe984b5b9e995fae9a951e6e8f2975df67a0180cea81fd4c97eea60a25c15e2ba21092ab0eebd5
+Qx = e22f221809fb7a054ac799a70b3d24744eb7c5096c8671770399527c88ccf9ddaea0257a0ae9430d927ff5d9f109c533
+Qy = af4101d60df9b306ae92da7592f4faf3df422a3e33f1c2ed2973b2b900eefc346b4cf024de650abf537cecd12ac77618
+R = c39a8e79f0560b9f26504469a470c7b2230c0d25de07c206e87dfbde9aff0a5d85322f56dfb50d4c1fc67c67d615dad7
+S = 2ad94dd13a39cf4f4cb24c2c81d4c1181652363addd856dc9ba7455458e40ed047cd113129bc87f43949d5a98a0d5205
+Result = F (3 - S changed)
+
+Msg = b23e83d372422cad7bf633ff84468b5ca0f1902eea801bb2e6e89b45d2f75ef9e08c47e010decdd2cfbd9280b01511164e00bd8323fd06a019e83d3dd23c8aa0313ad5196925b5b7d5c25ff8fd198ac2a234dbe0a13fbd04c4002ea89856e91e789e07e25d56690e0481cdb776a3035a64f4bd571097ef07bd49994f95d8323f
+Qx = fa8ebc3682d90ac7356f0b75b9e3376e76518676e0bedd176cfa7fa57fea4b3a399dbb2bf735ec90b9c1705cf9fa6f57
+Qy = 18c3fbca0150ec10696b3851f31fb3ba62c0b6be509d249e0d4b374c7a08e49338e0922e2a8a9319999e6569ab8d292e
+R = fb58ab09b8a7ef7a6ec05b854eae11af9b713f7c7540e25115f609846e636ad4f88dcf4dd61e311273df23ccda474f03
+S = 485be4c21b7c3a9c6b39ffc9f0c39f4050f76d2a6b3fae203d016318c541c1b4ad6cfc0d0950636ff6883895dd49e4e9
+Result = P (0 )
+
+Msg = eeef70ae23d95330a71bdde1feb196d599481e057bdbd5ef519ce445a9b5acb46ede325a9caad720e4fc49c198ff5f0910c56a06d0cf76f450da1ad35fecccdb4442f64daa6149ee6b67ab1307ffb5c4b6ca3e72a644d36d9e71c4dd3283d12041e73e6d20ec19b3b20654593a4cca4b2fd9aa12f17d5b00b7ed43df74548010
+Qx = e5f331536a2940cd67234bedf813c12e15aefa9a1a68429f8754bf2769a47c9c2efb5c42135e7b01a110d7302e097eac
+Qy = 63b2398612c863febd482184e834d3acb51408c49aacbbd35d8719746f37cb13e013c9505ce034cd815aacd10d2f7a0d
+R = 96c35f22d036785a392dc6abf9b3cfb0ad37b5c59caefcc0b5212e94e86739a2674020ff79258094d90d7d59f09d47a1
+S = 373cbc865384734c56952f7a35a1fdecd88e8b343ee3aa073d30f5f25b73506f1e5f5857f668b0080dec6edeb5e1be96
+Result = F (1 - Message changed)
+
+Msg = 7875194a0c3261cf414652cd9970219e3bf8185ad978affebd92ffd40c209a0d17dda0d5b79fefaeba3400088720598cc757aea1fb31ce976fb936726fd4b48d396a35cf4b78d16ddda56067ddc64728dc80b874c5286128b7b5da88808c7df5c3323791720e7ead8b50144dedc15590530b89cd022fd7291c97a4b9889d0568
+Qx = c53ad865beb1e2b92764065f1a6bb465ee94aacabe43426a93c277d02e00fe36be1c859ba08a031fc518a0d007668979
+Qy = 6728d42bae9bc097151748ffa0982964bdd16076fa0e7cc15837c1f773b08d02c3dbc57339091ccc34105b84781150b4
+R = d4f0dd94fc3b657dbd234767949207624082ff946de9ce0aeb0d9993b8c7d7935760e1bf9d8b233bc7d6cd34928f5218
+S = 0941df05062aa8849610f4b37d184db77ed1bc19ad2bb42f9a12c123017592bf4086bf424b3caad9a404b260a0f69efb
+Result = F (2 - R changed)
+
+[P-384,SHA-384]
+
+Msg = 4132833a525aecc8a1a6dea9f4075f44feefce810c4668423b38580417f7bdca5b21061a45eaa3cbe2a7035ed189523af8002d65c2899e65735e4d93a16503c145059f365c32b3acc6270e29a09131299181c98b3c76769a18faf21f6b4a8f271e6bf908e238afe8002e27c63417bda758f846e1e3b8e62d7f05ebd98f1f9154
+Qx = 1f94eb6f439a3806f8054dd79124847d138d14d4f52bac93b042f2ee3cdb7dc9e09925c2a5fee70d4ce08c61e3b19160
+Qy = 1c4fd111f6e33303069421deb31e873126be35eeb436fe2034856a3ed1e897f26c846ee3233cd16240989a7990c19d8c
+R = 3c15c3cedf2a6fbff2f906e661f5932f2542f0ce68e2a8182e5ed3858f33bd3c5666f17ac39e52cb004b80a0d4ba73cd
+S = 9de879083cbb0a97973c94f1963d84f581e4c6541b7d000f9850deb25154b23a37dd72267bdd72665cc7027f88164fab
+Result = F (2 - R changed)
+
+Msg = 9dd789ea25c04745d57a381f22de01fb0abd3c72dbdefd44e43213c189583eef85ba662044da3de2dd8670e6325154480155bbeebb702c75781ac32e13941860cb576fe37a05b757da5b5b418f6dd7c30b042e40f4395a342ae4dce05634c33625e2bc524345481f7e253d9551266823771b251705b4a85166022a37ac28f1bd
+Qx = cb908b1fd516a57b8ee1e14383579b33cb154fece20c5035e2b3765195d1951d75bd78fb23e00fef37d7d064fd9af144
+Qy = cd99c46b5857401ddcff2cf7cf822121faf1cbad9a011bed8c551f6f59b2c360f79bfbe32adbcaa09583bdfdf7c374bb
+R = 33f64fb65cd6a8918523f23aea0bbcf56bba1daca7aff817c8791dc92428d605ac629de2e847d43cee55ba9e4a0e83ba
+S = 4428bb478a43ac73ecd6de51ddf7c28ff3c2441625a081714337dd44fea8011bae71959a10947b6ea33f77e128d3c6ae
+Result = P (0 )
+
+Msg = 9c4479977ed377e75f5cc047edfa689ef232799513a2e70280e9b124b6c8d166e107f5494b406853aec4cff0f2ca00c6f89f0f4a2d4ab0267f44512dfff110d1b1b2e5e78832022c14ac06a493ab789e696f7f0f060877029c27157ce40f81258729caa4d9778bae489d3ab0259f673308ae1ec1b1948ad2845f863b36aedffb
+Qx = 9b3c48d924194146eca4172b6d7d618423682686f43e1dbc54ed909053d075ca53b68ae12f0f16a1633d5d9cb17011ec
+Qy = 695039f837b68e59330ee95d11d5315a8fb5602a7b60c15142dbba6e93b5e4aba8ae4469eac39fa6436323eccc60dcb6
+R = 202da4e4e9632bcb6bf0f6dafb7e348528d0b469d77e46b9f939e2fa946a608dd1f166bcbcde96cfad551701da69f6c2
+S = db595b49983882c48df8a396884cd98893a469c4d590e56c6a59b6150d9a0acdf142cf92151052644702ed857a5b7981
+Result = F (3 - S changed)
+
+Msg = 21eb31f2b34e4dde8d6c701e976d3fbbf4de6a3384329118d4ddb49adb2bb44465598abf6df25858b450c7767e282ccaca494088274e37353674eef58f583937d3d184ef727317d3672397a74c8fe327919a3df8fd65af0bc8cebbc40095adf89f1bf2c5e6dc6ba44633fd8433b25f065f5e3eb4840af23cc534415406745a31
+Qx = 5140108b93b52d9ad572d6129ed6564766f8df3755e49fa53eba41a5a0d6c1d24a483c90070583a66e3cfa52b6fb1f31
+Qy = ff52498446a40c61e60c97554256472625633eda0c1a8b4061481fecfbe9c4503e99dfc69e86c9e85c8cc53dca6b8dc4
+R = b2726b2ba9da02de35e9953fc283d1e78700860d4c33dce8db04dd41499d904866c1b8debb377f6c0dfcb0704252174f
+S = 0775b027068d7ad55121a278a819f52099ace750d5e996eaec9dee7be72758736cf769650148fbd5c411beb9b88f979e
+Result = F (4 - Q changed)
+
+Msg = 58ea3b1e82f97708053d0b41441d0aa9619050e86ac6c4f7781164e5da3019c47a839366509fa95812e4f64afdc62b627c7a98f633dd05db45c1d8954fc83bdb5042679378bb7e4c7863aacf2026360ca58314983e6c726cf02bb347706b844ddc66aee4177c309cb700769553480cdd6b1cd77341c9a81c05fbb80819bc623f
+Qx = 31f4fc2fac3a163a5796f5e414af6f8107ab5e4a98c755d81efa9d5a83c10128c16c863190112fc29d3d5f3057a2edf1
+Qy = fe208743f3e96c3a34b5fff78c9716c074a1ce3dc01c3f0e471ddfae91cd88e7dda38dd0e5e1f91b00b8539da3cc10bc
+R = 706911812ec9e7370234efd57b2855975eab81e9c2fe783aa8e442dc6e7d681dab2dc0dfc6765f87ab67001108e3facf
+S = 42c89efa22d853d32f619c9fe13e9852889ac98a9fed5d4fa47fed238e1cbe70d7970af9f7bdf84e51176af4885f2490
+Result = F (4 - Q changed)
+
+Msg = 188cd53097ef3e64b78b9260bf461708c836f25f2bcc98b534af98b96ee4b324e2203a7e62dbc396966f56419fb5135cb124369aaa025f396eac72f05ab45950d9e02cd5a2357eafab9f816117b7f1de192468895327802ec79f5d6b5a3d44d7afbed7b4a308e365655b8db2bde75e143062ee48b7c51688ac5db0bc7c83ec9c
+Qx = 1f7911dcfe63a6f270cf75b8584d9b1b4a00afc1fa43543c945945b8a821ebeb37fbc705a000f9cc7c35f7d27027b7bb
+Qy = f11835ec80c4ac06d99247e73bf72522109ac255e6109262de4dfbf9619244f74fb6c9ee57694537d7e79c248db34dc4
+R = 3587c9c6885adf3be1086825f9a41ccd2edfa0bd95e7fc4dba5a9710f41d539132de7772f14c18e318f8992b66d2a86c
+S = 73a844d729599d4e3e3c1b63e9c4bf5a73d1f69e0160857fe63a56c381c051f5c37ea6b4cc4caacb6ff26ef9699efe30
+Result = F (4 - Q changed)
+
+Msg = 6462bc8c0181db7d596a35aa25d5d323dd3b2798054c2af6c22e841b1ccf3dc3ee514f86d4a0cef7a6f7f566ae448b24dcc8d11eb7a585d44923ea1a06c774a2b3eb7409ab17a0065d5834ab00309ad44312a7317259219543e80ddb0cc2a4381bf6e53cd1bb357eba82e11c59f82e446c4b79314119182c0de96a1b5bae0b08
+Qx = 2039661db813d494a9ecb2c4e0cdd7b54068aae8a5d0597009f67f4f36f32c8ee939abe03716e94970bba69f595fead6
+Qy = e2d5236e7e357744514e66a3fb111073336de929598eb79fb4368c5bf80814e7584a3b94118faac9321df37452a846fc
+R = 164b8ac2b34c4c499b9d6727e130b5ef37c296bd22c306d1396c6aa54ca661f729aa6353b55d7cf1793b80b5a485115f
+S = 4e7187f8f735b7272f2c0985315b5602bb9b1a09f32233aa10570c82d1ccedef6e725800336511e47f88ddbbbdc08f54
+Result = F (1 - Message changed)
+
+Msg = 13c63a3cb61f15c659720658a77869145ae8a176c6d93d3a8aa9946236d9fb0463db9e48c667cba731afaa814ba0d58357524f8de28d4c4bbe2691dac9b32632a7dd0f99fd4cb240290878305011f7d3e37ecc410cc1fed601e7901e8be6414ea44317584843a2d2ca2e15103e1ea49365bc384355b3c6fa6ccdd452543e9769
+Qx = 46dcf8ee848c6459fa66d1cae91ccd471401a5782cb2d3b9b9264189f0e9ddf7197b05c694931bde3306240cf9d24b7e
+Qy = 79d9508f82c5ead05c3f9392f3b1458f6d6c02f44420b9021d656e59402e2645bf3ba1a6b244ddb12edbb69516d5873b
+R = 5ffba3b5bd7c3a89ec40b47884b0b3464e8abb78608c6d61e1e62c2ca98d44fcdf61825d69dffee8408d0849d0623bac
+S = 0d2597b5fc3842ffce1957172253a8c9c0e4dbe770ce54f70f139e0545dc34ec639d609e14175bdb2b812ccfda00c9d4
+Result = F (1 - Message changed)
+
+Msg = 6939a9118adc307107aa6b0057c280d10fa44a64700c7bd23e1f33a478ad2cfe596c05f72b540cbdb696aac6ab98d9ca8c62f33e182657130b8317a76275a5996333a5d3547e2293b401d0adf60f91e91d2137e34f3336e017c3c6dba6bf5b13dd0de288f9b20a896a92c48e984fbc09f920fab82f3f915d6524b0c11236aca4
+Qx = 097cea75f685cf4d54324ad2124ce3f77b1e490bbaa1ffacde40dd988f7591e1c5d158e6f232500d958762831914af7f
+Qy = 716d8bc056daf69ca2edd21b89a6ae9923cfcae87bfda5f9a6e514dd4b9d28d164fcc613ca2afb9660adfece59f09b66
+R = 1c5d4561d2a3af8835839b543098c101c715c545eb7d00300c5cb05bb08dac29e732ffdc31c50915e691999ad505104c
+S = c3442f2fb1498fd47c2f959edff37a19783e3ccee80dc6955ca64db087fd188e67358e7b9223535bbb858d21ba6a978c
+Result = F (2 - R changed)
+
+Msg = c82071e42c45ac3597f255ba27766afe366e31a553a4d2191360b88a2a349ee077291454bf7b323cb3c9d7fec5533e4e4bf4fb5bc2eb16c6319e9378a3d8a444b2d758123438dbb457b26b14b654b3c88d66838adfa673067c0552d1b8a3ade3a9cb777986c00f65cace53f852c1121acf19516a7cf0ba3820b5f51f31c539a2
+Qx = d2e2b3d262bb1105d914c32c007ea23d15a98197f0ed90b46a17f3d403e406a76c8f752be1a8cd01a94fd45157f6511a
+Qy = e585fba180017b9983b4c853ad3a5dd52e079c5f0ef792d1a0213b6085e390b073de1a4b01749ceab27806e5604980fe
+R = 49c001c47bbcee10c81c0cdfdb84c86e5b388510801e9c9dc7f81bf667e43f74b6a6769c4ac0a38863dc4f21c558f286
+S = 1fb4ff67340cc44f212404ba60f39a2cb8dcd3f354c81b7219289d32e849d4915e9d2f91969ba71e3dd4414f1e8f18f7
+Result = F (3 - S changed)
+
+Msg = 137b215c0150ee95e8494b79173d7ae3c3e71efcc7c75ad92f75659ce1b2d7eb555aad8026277ae3709f46e896963964486946b9fe269df444a6ea289ec2285e7946db57ff18f722a583194a9644e863ae452d1457dc5db72ee20c486475f358dc575c621b5ab865c662e483258c7191b4cc218e1f9afeeb3e1cb978ce9657dc
+Qx = cd887c65c01a1f0880bf58611bf360a8435573bc6704bfb249f1192793f6d3283637cd50f3911e5134b0d6130a1db60e
+Qy = f2b3cbf4fe475fd15a7897561e5c898f10caa6d9d73fef10d4345917b527ce30caeaef138e21ac6d0a49ef2fef14bee6
+R = addfa475b998f391144156c418561d323bdfd0c4f416a2f71a946712c349bb79ba1334c3de5b86c2567b8657fe4ca1f1
+S = 1c314b1339f73545ff457323470695e0474c4b6860b35d703784fbf66e9c665de6ca3acb60283df61413e0740906f19e
+Result = F (2 - R changed)
+
+Msg = 93e7e75cfaf3fa4e71df80f7f8c0ef6672a630d2dbeba1d61349acbaaa476f5f0e34dccbd85b9a815d908203313a22fe3e919504cb222d623ad95662ea4a90099742c048341fe3a7a51110d30ad3a48a777c6347ea8b71749316e0dd1902facb304a76324b71f3882e6e70319e13fc2bb9f3f5dbb9bd2cc7265f52dfc0a3bb91
+Qx = a370cdbef95d1df5bf68ec487122514a107db87df3f8852068fd4694abcadb9b14302c72491a76a64442fc07bd99f02c
+Qy = d397c25dc1a5781573d039f2520cf329bf65120fdbe964b6b80101160e533d5570e62125b9f3276c49244b8d0f3e44ec
+R = c6c7bb516cc3f37a304328d136b2f44bb89d3dac78f1f5bcd36b412a8b4d879f6cdb75175292c696b58bfa9c91fe6391
+S = 6b711425e1b14f7224cd4b96717a84d65a60ec9951a30152ea1dd3b6ea66a0088d1fd3e9a1ef069804b7d969148c37a0
+Result = P (0 )
+
+Msg = 15493aa10cfb804b3d80703ca02af7e2cfdc671447d9a171b418ecf6ca48b450414a28e7a058a78ab0946186ad2fe297e1b7e20e40547c74f94887a00f27dde7f78a3c15eb1115d704972b35a27caf8f7cdcce02b96f8a72d77f36a20d3f829e915cd3bb81f9c2997787a73616ed5cb0e864231959e0b623f12a18f779599d65
+Qx = d1cf635ca04f09b58879d29012f2025479a002bda590020e6a238bccc764478131cac7e6980c67027d92ece947fea5a6
+Qy = 21f7675c2be60c0a5b7d6df2bcc89b56212a2849ec0210c59316200c59864fd86b9a19e1641d206fd8b29af7768b61d3
+R = 6101d26e76690634b7294b6b162dcc1a5e6233813ba09edf8567fb57a8f707e024abe0eb3ce948675cd518bb3bfd4383
+S = 4e2a30f71c8f18b74184837f981a90485cd5943c7a184aba9ac787d179f170114a96ddbb8720860a213cc289ae340f1f
+Result = F (1 - Message changed)
+
+Msg = bc5582967888a425fb757bd4965900f01e6695d1547ed967c1d4f67b1b1de365d203f407698761699fec5f5a614c21e36a9f57a8aaf852e95538f5615785534568811a9a9ccc349843f6c16dc90a4ac96a8f72c33d9589a860f4981d7b4ee7173d1db5d49c4361368504c9a6cbbaedc2c9bff2b12884379ba90433698ceb881d
+Qx = d15ca4b2d944d5539658a19be8ef85874f0c363b870f1cd1f2dc9cb68b2a43a10d37064697c84543e60982ab62bb32c8
+Qy = 062fb7dfc379fc6465302ac5d8d11d3b957b594c9ef445cfe856765dd59e6f10f11809e115ac64969baa23543f2e5661
+R = e2cf123ce15ca4edad5f087778d483d9536e4a37d2d55599541c06f878e60354aa31df250b2fc4ed252b80219552c958
+S = 696707a7e3f9a4b918e7c994e7332103d8e816bbe6d0d1cf72877318e087ed0e230b0d1269902f369acb432b9e97a389
+Result = P (0 )
+
+Msg = 4f31331e20a3273da8fce6b03f2a86712ed5df41120a81e994d2b2f370e98ef35b847f3047d3cf57e88350e27b9ac3f02073ac1838db25b5ad477aee68930882304fc052f273821056df7500dc9eab037ed3ac3c75396e313bf0f4b89b26675af55f3378cf099d9d9a25a4887c1cfd2448f5b2188c41d6fa26045c5e974bf3e4
+Qx = c83d30de9c4e18167cb41c990781b34b9fceb52793b4627e696796c5803515dbc4d142977d914bc04c153261cc5b537f
+Qy = 42318e5c15d65c3f545189781619267d899250d80acc611fe7ed0943a0f5bfc9d4328ff7ccf675ae0aac069ccb4b4d6e
+R = b567c37f7c84107ef72639e52065486c2e5bf4125b861d37ea3b44fc0b75bcd96dcea3e4dbb9e8f4f45923240b2b9e44
+S = d06266e0f27cfe4be1c6210734a8fa689a6cd1d63240cb19127961365e35890a5f1b464dcb4305f3e8295c6f842ef344
+Result = F (3 - S changed)
+
+[P-384,SHA-512]
+
+Msg = a594969c379cb9e26a7f8db462d2382699b2a6212bc7aab15e768093b2c3158ad5c725c3680ae1f8099e3045a77e744a5a3fc9c15f118ec5a04e186b4b6ca46027737305fcef397257c46cf219d7a1612a93bca36b1e97148caffe0b21fd5d69e572f823f995c0fb8784c8920b6d0353eefb31abbe578f5b5c0b503dde205049
+Qx = d4e93c4bafb54c06814011309e9f3d8e68b76a5452e364ef05ccc3b44b271e576c9028106b1584f09271c886d467f41d
+Qy = db730ccfdeb6644362f4fb510d5254bfe6f23e891e936132f90f1913e93baa8b1f8c0613a0f0c61a760ce659f22babc6
+R = 8d0fd14a59c24b0c2a34b438e162f1f536fe09a698cacfe0760d026d1593265d02f2668d2a5e49ac0b21e93807aa9c18
+S = 3162ffd2adc9dd5ec1bb1d97d2b0c27b8ae234235ffb374878d0b76382002ea505e885c178d56a2d7809bd1d83117ef1
+Result = F (4 - Q changed)
+
+Msg = d497dfe02aa5e4fa13178dc1ebda8807f9ef1656c1abc448619f2e22a809d05551526a0e9706febd9e0f7ec9b791bdabc5989cb1957377110cc53006bece1a025c5bc7e9e64eb1517a6fbfff058e0ae85d67adee20fe536caaaa9928bf7afc52fe8cc662037dcafcdae4e57630b0c15aa1552372b5bf22f500cacfdaf52e7b89
+Qx = c665feccf51e6bca31593087df60f65b9fe14a12022814615deb892eedb99d86069a82aa91319310b66588185282dad6
+Qy = 1e6e25bb8ae7714415b94f89def0f75dcb81d4af6b78d61f277b74b990c11aff51bd12fc88d691c99f2afde7fbd13e51
+R = 0e18c4063137468fe864fdc405ad4e120176eb91b4538b28ce43a22ae1a310cc22a2f7a2b3a0f3d15e0f82038b4a4301
+S = 5a1620e42041ce4357daf824befbb2ed65596bcd8214e88726149b26b1f416b9472a8877413f1c3705fc2edf4731943b
+Result = P (0 )
+
+Msg = 047bb55e59e957f9a8d038a8160fc9e078d73d1cbea39297b8028245b23734b05a6a5f231b729f3697fa3e4d19f6d1c5274ab56c4319dbd4bce742b65d31dbe25425c1c382f48681a243b85a725ec5d9fb1f6cb3d74284de0e8fecd7fe3abbaf2e1cdbefe07893f54e7685eceef8f827ab705ce47d728befbbda5809008adfb9
+Qx = a6bbf85e8068151482ce855ccf0ed22988fcf4b162c4b811cb7243b849299e3390a083147fbd68683203ba33588b13ae
+Qy = 5c837ec9f2eda225c83ab2d5f10b1aa5bfb56387deebf27ecda779f6254a17968260247c75dd813ea0e1926887d46f86
+R = 9c11879e59659848274fc1ef5a6a181af813d23708b09a24dc06c089b93b918828dd938a75a34d5a681b0af362dc19a0
+S = 9c362231962ba7579c4a874e87bdc60dc15cb2e0677149c8ea31162963e05a6614616f67a5269616071cf095be7ff44b
+Result = F (1 - Message changed)
+
+Msg = 67caf5a42a7150b0e4905067aaf2828ded4aa245f195dd793984b9feb76c9e2fcffc2326b0af42450b9e0ea13481aa4dc979bed8633dccbf40e1a3b821a674408dd80d14d8aa411080619b7536c72a4685fb93273428aafe490915f0734387c2a956d7d20a1d93c28c64fe3913cf367705366bca6693d2d22f6c6fbaeba86be3
+Qx = 9c1eb5cdb1a873e4c275b7ded8712b9058ee0d9ded06c96a2a8d7c652b82e894e2f918dd8e18138e5c34821744b97952
+Qy = dd474c93619f02b5d4fe30ea7805c1a13fb80008a81bb5f3eeb95cd11f38841b8e34d64f2c6cc2d6cc2587365eed6b6e
+R = f17b2f2fa3b5c8e9c62a633e5d417139ddf3dafba75b464fa156c99b3948a0aca532c7fd3e14a266eb17e7fa80881da2
+S = 01c246866983fa74d6dff38b1ea091f8afd218b5a42467761b147c19a3bb20cd24be8ed1f95f1e61863a709d2d0148e2
+Result = F (2 - R changed)
+
+Msg = ef353a0ff016e6618ee11a09203ef5a8c1eb6089478ba3042c5002acae01a2f4d99abe37b10f35c1bb03de8b8a6a443cb0d8140f86e64a905f72ad7371f6c3e20a4962531b8dea2a34764909e743885659a9998aaa0db5830913d22697a54c5313af9115c3a66bebe2909b110fdae6fcd4181b6b414e53816504c35d99a367ea
+Qx = 20622a293edc96d83fee77cf1ee8077c61d6f8ed0073d53cfb5ee9c68e764c553fa4fc35fe42dade3a7307179d6fc9c2
+Qy = 710fa24383f78cc4568fe0f4ecbbe6b11f0dce5434f4483712a6d2befae975a2efb554907aa46356f29bf7c6c2707c65
+R = 45a6cf5cef06256139caa709292d1e0f963d176add188572e9c7be29af21a95853a98e23aef0a0850e58d44d60b6d780
+S = df8d71cd5ab22fc718070078103483e5258734872ab935435f21ea199018e49a69c064a63801beb0759fde6e2c4a85b8
+Result = F (1 - Message changed)
+
+Msg = 2fc5392afee78db70368ab391d7d765ea656f13b1f71e5f7550d77443d1091b0df7efc9f4e4fd568827040e3fa7a4b07b6f8eaacaa640711c7d65b04122f7dfc4deba77736382e47a36dda3f379cdde3773a2c7f101825988f13a6b6b64259615c5b6897ba2866d0a0924b4626a0e8db1a97696dd506273a2fb0914283b3d8af
+Qx = 83a4fecc0bf0a353b0acf6f54094b822f2b12564e172b296f3461cafa7315d7d31d0089b1b4c18ad3c86bd18f539774a
+Qy = e4fd57c5b2937e6fba1e7d72fc3f02352bd79c13611931935f4dfd073b9379f862f2277585137e996e212b5b6533dcba
+R = fb02804010a570d702ebfbcf3d6cc9d55ddac2bd4b4de56d325e9790571b1737f91d3fa1d4caeec6eea806195aed3187
+S = 1fd20fe383e907e77639c05594642798619b2742090919bedeefb672c5700881baf0df19b9529d64bc7bb02683226103
+Result = P (0 )
+
+Msg = 9a6e7e81429fcdf0cff8343d31f4db2a3d9c44457e6935d30e72d7f5d4d9d1bb6a68311db4fe3eeace1274fea67d81e066f6a4e7bd78699d25c7a89d7ad65b02fb994b265c8f52a182c1df8fdc2822fbd265b362df886d72bec90b78bfd8f73fa74dc615e6e026b9fee64672af86aa3df458159b6d6bbfd6c74dd2849104a24b
+Qx = 208a8c5a6b59458160c5b680116c8b23799c54a7ee8954a4869425a717739facfe4fe24540505cdc133fde8c74bfca78
+Qy = 22aa7aba797bde1e8389c3c3f8d8d9aa2a914f4d2d7aaf7187ebed9b2761975718ef97660ba0b8a71dee17f2b982e2cf
+R = 0b4e835ed83151d2bde96e201c54544ba5f301aca853957d3c538c9858fcce796b60fc50f5600a48dcdf13e5bc029827
+S = 0270adf02d31d5428d523e13d7d315c1929a1d89bbd0f61eec0b1186abe1c307cbba6b1067a68bc3947e6196d49719a0
+Result = F (4 - Q changed)
+
+Msg = 0b1c2410d8b0cb48defe7f363d163c6de740dd81c9995ce689b22c4276aa2de84d17ed5604b41aca0a9b65a1c00ca2db5cbd49898dde92a52bd8c370c9fce268aca4a1d0ec130cbd7d20f9d2aff8e9e9f24c4a7c48211609427a5177e001e75fab90de23ede74f974dbdef1b04233b9eb0a71baaab7c864a6b46db00eae4cecb
+Qx = 80ae47e99107d6148b1088c6694df5c1273ff336b66e45b68a7c65fed735129dadcaf2b900e9f8ec50eff70a5ba89ea3
+Qy = 47450efb5669bfacd7cbff1f801aafa0812ff88a6ae7b5a1f85e88e19129ed995f509fbf8dec15ce42bbbbd33814c09e
+R = bae6fba7b1485ecdca48219ead3c39295fa9c196b1f0941445b1ac768e33962f68d37f1f1749eaad7200064aa202fb41
+S = b411a38d02deb42d1015a7837b033c89d2f37d92c70fa8bb1f592223f7750520b950f30277abfb4155a3ab194b3beca0
+Result = F (2 - R changed)
+
+Msg = 869ca9414de82de07f22f7844d8677f62a92a5bd236173ddc3b2b91f927de15cc64f87694c02b0e212267d70cc65c21d02ebd202366d7e88b292785f0ab49436df50f8d631fa0f0969009ab28c98af2a6d4ce79b7ad42228958d772ae693a4304704b695e82c7b905fd97a484a18a2e32f61e961508389936d7b984e2d6b2e54
+Qx = 45cb6dcca8d2e80ac04536a22f9d68ea2313245550108ddcd32799d154c0a55492e49463e826275bd9bf0d5e380205c1
+Qy = 6fd124f5a6c745751ccfb3ba4dd9144ea8fd41a4d9a4b34820434da66aa7385e73ffe71e6c11ed1beb6c7af22ce00edf
+R = 2c782c4263eeee63657fbf20fa287a1a81fcd14b1d3bae333928ba4fc31abb20edebc130714380608e38ea74309eca9d
+S = 716113d95bc9dba532bfb470112b0d43d9cd6560ad15e0de2e514994801ff339bcf19ad4ee2b8af573f57c038fbd70f0
+Result = P (0 )
+
+Msg = 6c702f33dc562b5771abe12fd776e766f2328402538b99ee2059fc0c561622c5b9171b753e5dec6a6b5de0f2b8e8edc573293ef21344fb03acedb7047737e2b2284738bba243aafae8af1c8b6827fce77013b80c71990fcd517f0c19c65e7a501d4495e1bdd2c7fbbcd38aabe8a2db205b6fcf70331930551bd925e7e00c26a8
+Qx = 36c1459d9e9f7b6c1598778c784cbf94661a2b11370c02ee092f6ea0ca20acf81f1ed5048a28a1466a91689df26bc291
+Qy = d1367418c7b216bd32c6dafc8b2be99d02cab68df990758b2ddd543b7eb6ff6e285b649ffe588b1811b549cfb5f0289b
+R = 40c338adeb504193444bdb95336177362031aaadc5b7e151e42030df9dd8687f3cb8fe2292fd4f9206989c089d966dae
+S = be4b2ba251094c24de006c89af2b5c77e6937f36d7bb703b4f8edcfe65d45f4b2fd2486222163ae0ed9e215c0a96f488
+Result = F (3 - S changed)
+
+Msg = 75fc1d1be05faddbb5bbdd05bb5efa45fc8967b62af04f77bae1e737f0ea5fd84407b299a774cdd38f3697be8d9fc241ff4878856765dda9891a47cebeaf5eff6df79ca9e61c5624775dbbd7643fca27c1ec9cd537063f2b778d1302c4428898e06dd647acaf6d091394db9c629847850ce2bada79eb741c89dc1e38c7829d9c
+Qx = b5eb6670bb0b0d3aef10e533d3660756b7372a2a081d9d920130034f48202cd43b9e2d1e5893d0cfb322db65ab839716
+Qy = e28444770396041b489b302786a57fca9a98f19685cb4b455d219151e64645ad30dd3149ec96f3bc90879834b65e58aa
+R = 0887a13df940907864b425ec0d8f91ac719abcc62b276fa08c5122b38831c8930abd3c8454e98182bb588fc72843717a
+S = a380284eacaa36a34e35f04fbf6e28ffb59176f41ea52d9c9bc1362eccd8e0d699c2e08111d93e9dc2785637b1f4f09e
+Result = F (1 - Message changed)
+
+Msg = 141723104f09367f4b02c187ce292861d445d462d3adc5eb67649633d3c24f132149d12db67e498b98da8d7d7b0cbed2f67459bf40ccd6f629d98d30bd7b414d3b8502b08237f867e013d7369fc9b7f505f67e6a14f1e57ee0170391007c30e4892acb0e8d1490f0e6c20b4721000f08060fb86580a339691e45d140e2d704c5
+Qx = 700e8f65e052e918a63a96fa57f4eda849f9f9faca3302d6ead66ebf85838f8145a6d6718a681b7bef73170d7254958f
+Qy = 9e9e10357658913007803859165926cd1e5e92c3a644d834098cb1cbfab466349bf4238a5154cf50ed77c77a78263e81
+R = 59be870e0fd684b000cce95c616d9f34674354e9d20db15d204b8a6285ff55258e4eeb49da1573ef1030cd6b2626dcfb
+S = c0bbbf71d87479d82575458be9f4d686921db7ea458d620271f51ec3f4d1afe3bf25ef9c0c400eb7b92cd7058fb17346
+Result = F (3 - S changed)
+
+Msg = e4622318a8a04eea5288cd81100e60b224f16a2f4344f77bfdb40a1c4c263d1b73da80c1fbf30d13aa0c05be31267c77c802162a7be7488b5d9fcafde3cfe073fdd5c7a05208e10cf9ede811effb8bb72cffb0c59335ebce348b805a7ddb431911d6991a5a914172d6b8088e8dfec2cee36a52b7e12a63c6732abb476b5a2bda
+Qx = a9de6f029445fffcf16349b44095cc83b11e3d0d9f08654b158014803b1cc31b8dfe00b1a8167c6f704d69cdd62c6512
+Qy = 27336a503a669ba1d1f3619f51dc8aa2a44b2075c682a36f071be486e7dafba9adfac2ce74be0442b7251e99304ffc05
+R = f93a4d2eb94d087f28572847e0099ae2ee944efacdad392ec268c9c1e632e6ccd670c36584e58aba52a4c2b07127d55a
+S = 941ee89cea6e7ed20213a95482fae134707ddf4d292ab1952ed5464f1f1138669dedbfc9998b696eaf469be5fb240c80
+Result = F (2 - R changed)
+
+Msg = c2c34889861d29db3742763a00e42bfbf4e160537ccafe3d2f1d64557835d35c155c19fa2924f735dcf848cf35eb2880dafc2e8b6980717112f11533bd072ec1e4665aa934b56012eb6cde0f6af3d6d012c4ddb10344f2e08254835fae6ea8555f6c9ab7c451b93d816255dc2911d0275719b4187a1e9cecd435ce85b5165d91
+Qx = e63500d6d13069c01fafc4518f1d429661c5bb6ad1ff0383037ca6a469a5c20c453dce03bf6e4164f7e26f849016b3d0
+Qy = 83b7b731c2531c3ac61b194cf3db6dc02ccdfa16d9eb49f97bc4ec3fe6c8bd865ea27f1538531ad07dc44fc5107af8e6
+R = eb78733e73fd64a6a1f23eba5311af23d26816fb8847671e01fdbd8dc7d5fce1a0823b080ee99e8d75edb3f100e16077
+S = bcaedfe599f98b51542c0f94ae1010611c6767ac3abb2bd887399d62fd0f1b3a0e97deb24c95a76de44521bf24c8645e
+Result = F (3 - S changed)
+
+Msg = 17aa6d371c82c58cd209a96d374733e53d41eecba295f4d5e9c4ec0ea0d7a6d268947999ec64b39957153cea7549595e177ce530d60e7613075a378b2012a16485e7ce7fd0f8e9560ad3490c6be17c13edeb60f3f7391a54353f7ddd615e4db831763d645101a60d2bf208982c4af2d082a95e42a2ebe436c0ec5b9de80a61a5
+Qx = 3ebd869be687f82d844416e6816d698d82e1e22a1f451d50b6c146134deb07f05204c0b04e7dc07ebdcfd916531dc7c3
+Qy = 6e4d7bde063edb7254a82b9d9249d2a2b9ad8988c37a84ac9f7c09daed42b1fd28f7cca1ea8b4f91a66e878224800bdc
+R = 575f87a8a7980555a198cfdec279cbb2f89551b5271d242397c29f6bc4bf413dc30312a7e626ef7fc77a9124a79bf9be
+S = f0b7d759246ad36ba8240c537b1eeb5d148c38d324f48028c598eaef6e49d79ff3f6cfe3a32fbbf6f3ed3aaaec31d572
+Result = F (4 - Q changed)
+
+[P-521,SHA-1]
+
+Msg = a2b07a8c08cf0bf146cd11882553147831c118d9adae78dbc1700555842c5758c553751b88da75b8c6f45315db85b1d147519bffb49fa5024219054123f0925c7e715a040478aa3a5d24b4ecf1c49033edafa6622dc7e47fcd0311c54b1e3229d9caa9ba3c3dd8ea9501018a7d4a3b45b865696c94a366d818f1285426944f1d
+Qx = 1939b25d13ee8e04203643ba3709526a92912b0e98f06962fb217ed18d1ba52bff192640f980d3f7f92c116b5d94dfd48c25a26b72acb9425e316b3d2ac130a6943
+Qy = 122d0809c5de123c6e5373c1680a4d566c565408b6750d942c024d56c0d6761807adf9dab454b84254671dc68f6917f09a442643e6db1bb35e6796816dd3e5c6a7a
+R = 144c1a1e075aced5e10f50ab7ab0f795bac07439c953ca0c749dc12d50a7e4dce21850dac1fd773e46576335a555f20d266842a8bb47fb464fe3fe297e9ee356e48
+S = 125f3b6f1cf7eb704bd37391a43034df9260c4d5fdccd583bf65dd5ab4b007c8f837a31a0b7c5a0be3743a187b2569841fc4c69f816c8234d8ae845b92fb9263242
+Result = F (3 - S changed)
+
+Msg = 69638c3ce737f19ec3492f5cf0428f0ed411aa86254c0808810b03ffe041b3cfafcefa398de1e965da22739145622378bb439cddd76dbe4d8cc66005bd5acdb819412bd7bc8358eda95f628f431199e0cc400befcf3f518eed60f986c1b710442454a71918a240db6a9b48122bb4ee5fa1f96a916cb640413b26d0f43a32e1f4
+Qx = 0882e2cfed1286668e62699ab20c6c40068b460917b306e51ce7f72a4d760e19b3f6cb5897de599cfd84ae70c26d1a39144772b90f8ba1ec2d0f09395265f0308cf
+Qy = 020b80b99778dcdd3dc47da42b279cc289eaae369b9e2c4b0322d2eee9b1a76eed6b5b70d03d83f1db81a67ad6bea98ce71b120e9f83f0178cd6fa3f109a87b1fa9
+R = 13ec7124331d896832b77440854c043cb605ae9cc7d20cb358513a5bab26371903c6abc6e4860a0b4940bc5429755341a10251195e5f8af42494c002340ccc57bc9
+S = 1460bda2fd76ef05dcbe1cd17b9c5663b03551cce586c56e103179069fbef6ecae47f6555db755860f0b06eb1bf247312ae0f9d64c5cf13fbc42b923d6bee151b5f
+Result = F (2 - R changed)
+
+Msg = 3f1b870323330de661aac0ff50a0426ed28a99b97b2d5221587c15a2ed6203d8a83ecab3d65dca6df1baad2adab24e7a5f71f9180ff2a28a98ade4fc054c3ef4c88aa8a61174e2399c06d336141d17b27d002cfcd34600585b4efa37131fbb80a0d3ebb5878c8bc3ae8e5db9083210d8318302a2e584fbf147a9ef4a3c0315a2
+Qx = 11a5a6f7166fe435c5cc4238daf92a2d1af483543b7f505785ec4e2d93b2ca1d1eed3bccc31761aa60f7dadc97629475d2712998c2eccb82a78d6da7b0524662e9f
+Qy = 0c66d54768f5daf947cd414a1296a54c90e2b65a14cb94aecf0ba51c280676c160c39539955f2a8194357a983a1311845f8cac51cdca1e209bbac32cc809f0e4e10
+R = 10f45ccf0b4de7d2af890d65395c715043dc5ca1489c79b820347d51848f599ebd4aa558c62ce8769c5d5a294679f9aa74414ca6a1b82f183f23558b0a8dc6cce68
+S = 1adaf876dc35310ac592d1e3ba89f148c3b76417799f43aa1b24c1d2e3f544c018f066ed7baef480f7488820593bcbb25ce08183fc14c6c12fce0c118743f04e281
+Result = F (1 - Message changed)
+
+Msg = 14ab6196185df9ed556cd0ea664fed60c4e11cd77293497cefeca1973d291727aef380918747e1b986badd1f7835c7cbac2a1260dfd4d3c27c03fa4089dda56806518b60305041c95c78096aff537a5af1e73c674b13b536bc1256810d136530ba49d1dacc0b4d8f2a56b46c1df148673d73635790fb2afd8050a8d8174c6b0a
+Qx = 0f3bd2590cbf620991d990b84efee86073f6c789deb07b89a1f278e6cc9ea573d8586ac395958ce4e1b09bda73af1b1e6f2a8c09ecc697c021974c024564ed87165
+Qy = 0514871935c187e57d1aac376aeb018acf57c4d005d85cc939a6c83256f38b2c9ecb1a0ec8d132e0f5169843faca4ae664459124bf5f30309fa86f87a2604058150
+R = 083e6155dd97bf9ba7c60dbcdcba7824b125a73df1433fcb46f57c51f63ae161ce67393d327d174aec7f0b552decb8131a192ae940deb84acc3b45be61917fc580c
+S = 01fbfe61d75dc3fd814eeabdececf361a0a066b8c06c40f0e057faf8e4e7b206dfbbd3a99ef55df67234a29fb1a618620d2e27636d35bb98eb7535d1749c4b7e7d2
+Result = F (4 - Q changed)
+
+Msg = 22edb41beb81e6f9479f11cf76cc67fd7177e2c452d4672aff8351737829656991e0649f1845c5a4484a81f16afcb96e9571717b2eac63e747b98421147f77a5b60b45437640a57d0fc5ef37d0d4b1fa3c7cb0091d5618f1d188c3d8aa9bcb37cfb9f7925d3b4a5135f43b104833ff1359854103cb391f6352ba9c362d2e8e4f
+Qx = 13136c4e5dee983f761955bce7c196a000cb26863a1dea762884bb041e45363a1ab1665c0ca69d1167e555bd63bceba08f6ee14571acd06eea3e1e5d9c11a036984
+Qy = 11c830e1fd29ee4e10d7c6db7e90d6c1319c9858f87a944542c28679d83680747eaf71a29362ea2c22a89d78e2ce020dfbba74448d2f46b3f84b99f22604075b22e
+R = 124b3bcdae17413de84721e6ebe64409d80ac07a3b6c9a603ef19c5162566076108d30ec79426d24c72ac12af6fa1caa4830d55b4e6fcee900b0e4b20cdae0eaf70
+S = 03e0724d156c3fe5cb799a17972fbb891f0e11cfb650a1c524f6f2aab134c70fb114084a7821e0e12054fe071c516cbfb393fe9d98c840e1cc9e8475d3add81e0c7
+Result = F (1 - Message changed)
+
+Msg = 63b738e1619d533997f0e558699c5dfaafe2f5f330c4a12e9d9401db1d8767d044f543214ce9e65b9363702017a114f81f57e3f607a13268282dc4a6ef0e99862008d7da6e8b19807dc0671bb4d36045afacbe1f337663e6c06edea24b16aaccba6119e55ebbaac28cf3fe0082faa9a9e8cb0e038b45b05d7e65bbb92e264caa
+Qx = 19eb73393f070160d871cc396cd8d6973d828d6f3c17bcec7168843f0342c1b54f3c02a1b11348da1035833df6fa469d75692ecaa2feddce9210a813bdb0e1f9936
+Qy = 0e030c5a11e2317ba10a20ec373cf69c96660b434445235efff0a9d23904c5d3ef49efdf0897222e51624f047b567ed61814f3f9e8c62f16ac27160897d5a09f476
+R = 0ca41bcf9e80780687ba70d7f5ffec7da25542dc22144d9f6843889e941cad2fd8d8771755f38c0ef77909416371726b066464d1d41f888efa39456dee859f0ce98
+S = 1770961a369ca70f9d73b61aec34662735cf228299a7c668aa24afbc9d7f621cb3acff79cee19d107361614c1e71ff1f32ae4f02b7bf94486f0fcd61b6f76f304e4
+Result = F (1 - Message changed)
+
+Msg = cf18ce9521ce1c6e99000b03a92fe1b13df5b2b1d37f5f97e83fcc49473fb3188739810e51f85c2cac73294daa80c9f36dd6704cb0e7d14ab21328935f5a5631d5a8172349155a3d945b4b36110cf8bef096120e6dad4164176c6b8d168c83cc5619c764819eb966aeb67a5bdd3a525c3ccd7e6e322e42c7e17ffa27eae91e03
+Qx = 00c12d47011ed272aaabcb0fb6c12d8627f33bda02b2b3c3ec7b5ed60eaa577add4205d222b8ba0485b1d98ade9df18ee1e1ad9e0a9e78242322201e3c664bf8c9f
+Qy = 0d1b86d4a1171bc80822e0e1094a96bdf7e031201ec212ab7d0e7b55394cad8335050701327a0a1a17181b586b89ff24a658e4b0ee16b8418dfcac122f2457f67b1
+R = 0e4678311d0c068eab2118fc0a59014ec32c89cfd1e0273b966634b87783011b58a99204d266014d0236bd6f276f49c693a4d62b0601c307c936252cf718e239dfc
+S = 149f5cc02a6aaa126a99a59b83ae34f405f8076b597540625fa76e27dd29a85b6a4b0fc3e73a245a91d64a8f2b13ac345553b7a40835af76a9528cb48ac8d0be364
+Result = F (3 - S changed)
+
+Msg = 9bbbbe8a72130e1f023fb77be4648c80e1722d98bd478882383026c5c4e8748873997c5a38e0a173ed461546422d7691393dc2aceb0c0775068bc7145e33bf6a9e34f7fc6acc8f079a265168e54d3cca8d40aa04c1afd0909aa3df50908d7324aa7861b50f471fbfa5d615b0d718132c81957b178ad936deb89fde37147f8ae6
+Qx = 0f50a08703250c15f043c8c46e99783435245cf98f4f2694b0e2f8d029a514dd6f0b086d4ed892000cd5590107aae69c4c0a7a95f7cf74e5770a07d5db55bce4ab4
+Qy = 0f2c770bab8b9be4cdb6ecd3dc26c698da0d2599cebf3d904f7f9ca3a55e64731810d73cd317264e50baba4bc2860857e16d6cbb79501bc9e3a32bd172ea8a71dee
+R = 01e7cbb20c9a66abf149c79d11859051d35cfddd04f420dd23bd3206c82b29e782453cabfefe792e4e3e68c9bf6bf50d5a00ba5dd73b41378fb46e91ca797dbb250
+S = 0f1e9252573c003cb77f22c8c6d56f2149f7e8d88d699983da9250c8edfd4b9f864a46c48819524651886e3fd56492f4b6c75fb50a1d59e8bfc25f9fd42dc4e1d37
+Result = P (0 )
+
+Msg = 0e75709c7f795f9dbebd482fb5a71de2c7ef01fa74a64292324491cdcfec7ae6bf315a030b81096eab2fd0142fd3dae77b703554b0fcf0561d8bc2b5ce3a63c31600fa1c5ee469c9cbcd4f16523b1e5c26a24af1ac0fa2920d8c0ce2b9be11a6e818ea7ab1683eabd08e249281ca83f322594c1a47862a226f80bcb75e51e12a
+Qx = 0fc6486a5cc9a366b2c25d57f3f1caadf93659223c7eb38c310916cd44bc49d3ecf1cfbd429b57e329e1eab5f552abaf828ad9cfbc2f7534dc8c87f54d252e7b69b
+Qy = 1c0010af6c5cdfe26b068990cf44b1bcf324d0940bce1e953f7366c757aadaf25ff7dee4947879f305d3deb1e9a849db3cffb83bc1c7e5e82777be140931d58d177
+R = 0a58843085162864b2246c619d6cd38626657eb8f13ed5921b73071b6bddd56640ec9a55e7f2190481ef5e356425749e626a4b988b811cc12dd21c61cea89640095
+S = 19fbd1f9b108aad0208d1a27735ead4685f04d01882ed18c217d8e0e0fc71d8a98d3c45c471327e4dfa631cf4b826ead3bd5fd4bc0426fcc95b58bd354d012cfcd2
+Result = F (2 - R changed)
+
+Msg = e2f17dda2941ce1909c33f3e1076f42957d8d9db8cb7f8ef5e2a6a2d7a03d56c5247c08b58727d40009c91458c818687ca060bb724a061b72bdd2e55988094a99d89c618bc099429e9f2bd2b47771fd116d4227e7d368c5fda34597d74f2ccc3bbf618c53f706d761ccb658dcb8434d9c4c11b0e0ee6fed9a0cdbcf308e5a64f
+Qx = 00933ee70d1470acaea66626394023020ed521d5b9a52e068b827d23af283bdbbbf3999b0c2ced0abf607b467fa86ef89bee3852d4e993df3c2c73a49488740cabf
+Qy = 10231bba67cba896274e7af7f9c65403e48c56356fba772120aa8781611239d0f50b8958ec8709a301078379b59123b47c5edb87bc2327cf607f876154904b93e92
+R = 16f79df89a498ac65bb39d62e1ce82e5578eaf778084ec5926a638d50ee5943c87955c8255340a90f800fd43d4dca125b68dfe957d148533126d5761d711412bcb9
+S = 175198228ce2eb0222d64eeaa403c0571989046e638419ef96612a90094a26fb819ff1addd823f8912e07ff32ac72790c38c601505b45dbb9cafd1b46f352aaea0e
+Result = F (2 - R changed)
+
+Msg = f3278fbf2cd7edb7c0667eb911210cf3599d7322b15c053d1a3a8bf3fc6445fd7c6e68cffa765b8911d93eda77c0a3ce8ccdfed6bb07c9aebaac8d1245f0e02c044ca04b12f45670c97d96db7c36b80c0763a4c2fe93bccc6ccffa91e228b095bd2ef25b111c89aaf05d811b4625d343aa787877e8bfde0a9f432719473cee96
+Qx = 007a5694d537eea406d753532b307c5b86e8823d31e81f6e7371e6def61f31c8f706c1b89f8655e54f68e6821096e6b96a7c3752e47d8d3ef5da135f881927ed92a
+Qy = 05810620b7d83d3e7e48f7338b18e03c2e97dde5dacdd5d54e4c7e75d736f159dc45431d5d3c07153a334fa60567307271bfb85cb0fcae142cbd7baaddcbdfdc018
+R = 02cba23e78a1f9c6c18bd26321cec0c26db4f1100b986d37a0f24fc42c75ce4731a2876e8865ae21700289734ad5bae3611418ea37a13fae67db2d1a58a86f85422
+S = 0c438e76249b5016e0b83ddef5447420fd13aee6f099a0b9ffafcba4e7227f70cc5dd5abba03532ebc50424fefdd4f6d258ffe044573aa51b8a5d1d5c6e5dbf318a
+Result = P (0 )
+
+Msg = 047876e08961d6855a7f11010caa839e506ec89d6e8e007de36a1f3355d0c7bdf90f0ae8586fe73108869d1d0577a9ee0395706f69bfc0c8c3e17f53fc78fda86290cd3fd63a06bbf1255667a33da0ab50100c239de0c036d40835a317dd9f054543b6ce25f84b1df261a92d5415c2f5bd19eef1b1d6eac37117b53939b792b1
+Qx = 0a00f34f4572450d93607d3ffb1fffe7c86334426ad60fda27aa647e67c34b2cb1f0a12f4707336f1f708b3ba1f3cdd599ae92a2be92f9ae5526eba9d4adc052fa4
+Qy = 166808273466ec1ef2865e92b263b897131c5ea97fce1adb1ef88c8ac2e63eab97567d82db9c0825510812db1b2e4cba705ba64d33ffdce676b7f3aa2e343f7834e
+R = 18ada7d95f4d05350ae95494b7c81e233168ec88c5ebffa2d2a3ac74cf90b6d9f80407276f92bd9b3ca949e5d5cd51166e29678aae58a284b9e6ceda3a550b08c15
+S = 1ff12f5e9b12efd941e8a445ac036d735e7bf64237972002568e8eeb0dbb887709b53cfa67186f4df215e2a9f7b9feb045270c72196e19335a9c554a19cee0a8397
+Result = F (3 - S changed)
+
+Msg = 774c1af085bd44543f933f6db8d8c0cd07a25cd1517e82ee5a0ca3d1c54ac09e0addeb8b32bba2b1d67f86fcddd747a818e693668cf4569d9c25bd69b5e2d350986b1479fa03c1605c4691938e6bd9f505b9995e77469436b8943e9ada77351614314abaa05343f6b5f2a67dfbc0d61606cb97cea5b2277649bc21e5b076b289
+Qx = 013a5c825a9ffe6179cd106b4a2343fd3318d83cf3be58d971704d0328486738f7536041cc69e6f9548851cf591ba080c4a1c4b4f5d95d216138d72bc56eb63779d
+Qy = 0e79075f5acb9f52b67f8411f310c02aac5a98dcce0275438e59f8a2a3754ebe57815247a00d3506fd342d3d43607ba67d4cb608da3a9296d57619223c02e0c4f8e
+R = 1ad988418099c6483e6a8d62fc16a9fe571ad35c8cf111c3f35e680541a2f5ed96896715efa4943f8b46d20a0abb228852bdd5cfce1787c150d01231abc065718e3
+S = 095c1e7dcd09375d1760700c5351ab23618b1fdf1b2b02e918c0ec341e5156300b602f7960e0eee2c027aa0076b194080e63155dc56a81699e8aea36ddfe703b94f
+Result = F (4 - Q changed)
+
+Msg = bc59b04a384e79b631f0f401ba990b8d48606cd6a1d4aecca8673058b283ee97aea6362b49ad52ffa533fc089a926f7d0c99b56483ecf0618046ce173527c1ce8648d17a45da8c9376bfe081df57ae9fb09c1e7193d41f359b2164b056737cef4b88a256db2939fbb1f143473e45b0976c964b78447abcd85c66c5d8366fc011
+Qx = 092bf4245f0ece3a8c3a723de152c6413526c333a64f4f2455e7b45396c1614c473460246f49c65e957dcf779af0b675eaf5ed7800539d3619a6fb131f1bc610968
+Qy = 047689692e52baa835ee9c49793bca7b01ed3bc4d4c396a54eaefe0520840a31fa3c35cc0d2317ce367881a15a3c06e7c26b192e90fe16c10e84c92233910d7df7d
+R = 141f936c6a5ca580e5a18caeb85fc13e9ff57d50d89b8447c8645ff66202e71eff4303d57c28ee6b68915de6767a124f3652c22940656f4227d61ff30b17c2b9aeb
+S = 1c7bb4c22e68920bc6b9df0626b09ac79e5b76ba29d0b632c0b892c8661087461c4131771a2b3a9834ea4b3d3bddac9910331774643ae22b613bd0b2464a12cfabb
+Result = F (4 - Q changed)
+
+Msg = 2df095b1f48341c352258afc19240c805a72a7662c38362a81fd3f788120bddd86fc10a99cfcb4855a0f64eeb9c6f75d74c145cd6b3d938e325a9f154a36305e1a213165e83e51b0122a48553d26c9352182fba98dfe8fbf1d64a7e0ae637d855084b2ef5117028d8226af607ed6f6e86065cc3715613289976deea128af123d
+Qx = 194cc7f51d9caff692137190541f5aea160977bedb0d3b67c3deed6669bff160696a96550934b3dba4129e204f068901c84c821523bec91ec40336dce0d2673e794
+Qy = 0709279f85ef54164fd7347afcdbfe42d8d14e6808002b3e0b59bcbed80ce0c16e2db1b320c1d98ccdd75efc50fcd6ce91df6baaa99ecbee6df41da9c142a74386c
+R = 0d2542223b0a5322249e8f1af6d559a87c39aa5c3c7e595b07fb7be4d3bd0184a419651f96811f3e8c9c578a4be68188a8a3a1ff0ccba4af5429ef95c64f34d645b
+S = 1ee3123fd300cceabe2ad99bd1975c4594005ac9ec31d44ee4b9fe325d39049a5a83b4ac2a7f0b603c82dd88d136507bca2d383c7e8375c36eda82a169b3e4b4034
+Result = P (0 )
+
+[P-521,SHA-224]
+
+Msg = 149f206f82c9cf916a5da5bdce214398b8165121488b590651a7203efc046b1ff107badcc7c38046f7d035a74325df26e70fc67e67b735433d2b8192d93fbfd3ef32117c1dabed11d7e64a2804e3ad20566975a5c689333283c982698c7164ff491588e4cc12d3e5f940a53a75f445f284899a2f01b96851171731de7008c660
+Qx = 145896c96ede10f5b049edc0475870c0c6a09ab9cc47667146deca1729d98c124bbe009e5e161b88c7ff61e79d6f85b9c4673c0664e039dab852e8f99fb0ae70a64
+Qy = 05afb810a0a9c7f008850e8ecc67d907a74ff9e58f6d60ed14b3ed31e4751077a60de444a43d4d9a9b944905b79ff0c0ab431b21e0fb160cce8f08784677fb58bbf
+R = 12f63284068bb815ba935833f382ee2a8a5f64e2dbc9869be281ec7d3a28e2d7d2a84e214d79598213f82217d95ba9868da4dc3a3ec7fcfd7c8c457a053e8b0ce5e
+S = 12b62183c893455324b94b7cea2fa2e1c912362f99e5159e229ce67a80f45c7c0d27340e57b4a8f40b80a4d572345df083061d311b578a73c8faaba4e6a194b4726
+Result = F (2 - R changed)
+
+Msg = 6a491cfce7f5012e870b4aa5791b7cb89db1e7b95014748a20d2952836843ad9d013d53618418ce89c651b6749fd034c8b75a2eb1bdde0ee75ff2857d6f23581fe9eb2b133ed5e614ba83acd211b959afcee2bb02eecdb813b44a33ba83e98a83f52739d212483a4c389b49a0bb6fa05045c76216ef7a28e597b752bd9c65a8e
+Qx = 113a72cee148a7428065d8f8e89dce2dc7e1bffad46a130af8f6fc8d0fabf26ad76bb64ee078ee66fbf0212987e363e176f0106369eb1e43297851ff409e935e216
+Qy = 1a723ee3f44aa68e1b43185a50bfca99f349ad47d848dba8f9dfbd773f9f53bc0298bf43130e19ccb8021be39ed70c7b1f7295cfd034e713878f47d7508059a4f81
+R = 010b883cb3b76612b6cd8f9288459d373d58c2e0366f300623ff6b28224036ad1df47d1d9df8037a18e774e0bcb42910e96dc7d7fee0b53686d5d3af13485453c66
+S = 0a29c87d9be8e91da4333089043693425892f50333c7f93ab27dabfa5cf89697f366573621a86d523e850caf31a4c26051e76b91ad3e20a391ba724d4e58641cc00
+Result = F (4 - Q changed)
+
+Msg = fc3d9cad349b8922e69115db085bf851cb9f7c6be6a668e4f6403da6a30db996220b59ccd24ffbc52a1e61da79b97979ec5fa59a914483df6f3781abdca679bf1bda15ac86362170c9f93c30cb2ea028d6999a9c714803017041646dfa1cb5423c90d24a40298c60007f55dd0a7461ef441a2357bcb370cef2d6bde3862bfaaa
+Qx = 05766da7e6d9ebbe7cbb5b9bcdd657edf36fc4a7d4a173b99bd1caa804e35e937289e05cec2cedf86f0f7a8de42958e6052500c8a63b496ebea88252cf1b44ee5da
+Qy = 0ad35038ce07b53148cd7d0b4ee8c8ad6d89a2c68c0458d0d694036120893ba24a52792e0c8097f86591dce015151659908829f323a5dfaecfc51470779f8e5a5fb
+R = 11c5357042c1d98133e76f0a696e27a22738c78ff17c903d8a5190b3c5fb186374fce58fe47d9933c2b361cb20546d730bb5602fab6c8d14e0114a64f9d2b1d892c
+S = 115ece7d8ab1b578b0e870faa8139d009f6cc3cdacf3172c047bffc1a31e2c66b198ac1ab8c90e826af291de58990e32b18e71b26fe01b6bcbaf86db6b1a726f51b
+Result = F (4 - Q changed)
+
+Msg = b202512796d18e8e6769dbc286c15048d0d6df493d1c383d4f86fb83c0d6b2b309c103184856b7cd777cea25952a8bb0f828ff6a74a88198dead963f45880d5e77fb423d8f649d1f5df3f4e5326555f38bf79271573c819d9b8f4a1c49288a4b5383578840fd94e7f46b2c488d7c48df03b0be0058708c3a8c2444d0b6af61ff
+Qx = 0ea4254c3111118d3d859c704474251fa951b0cfbfd2f249bd32f70cecd80526e8fb72c1258c994d8067539e478890d5637ad925ef43e2caf297fd1eb49d9acac77
+Qy = 1ed78a277869d8bf7f2d5eb9c2753aedd89197fbfcaf36a633a4f3b2bdb5e706983641156f0aa6e13d38e907546a2603bb1cec785bc334fb03033600a77fed391f2
+R = 127570a0c0141bb4c2ababef5fa879e55c1637407686b49535fd17b3b911452650e302e9186d539782cde4d48ee43c258572ec299ee63d961def2333a4f1f8d2af9
+S = 12ed61b0b4c889bb36ff9ba648318a2b11604be6fcff858adbba8e59fa49fa30e2e20df5f2d26a8b9e6d989ab4e50586732adfdd4ca49ddee11cd889f0176a59ca9
+Result = P (0 )
+
+Msg = 9ae2ddbbf7b9f9d7cbe9f02050edcfcc55ab1f41b874407a0fd18a9584059511f474f964deb82c81aa8a902c4b3867c0b189cb3e1d6c2b417ceab2e857cb2f58e7c08178d8f3b2649a279b853fa9e1916adbb48c0995e3fa124a97a077e34a2b65e05f60f2645547c71ed3a6a909aead345b986d32f57792afd53d13d669414e
+Qx = 0549a23bf1b24fba2e921c5c2ba78809d6b0623fb1b92a506690b668c946daa393ec42ddb113f10a34f1b11475ac1250f119e83149d5211791dbf6cfe4f591b6f44
+Qy = 1ecdd45de1ee27f6abc1270fe11f770d4e26d5dd12d0a7baae6f3fc9c7f074541bb05ff0137c3923e1f858d643ec63f7c50f776f45009f2998a0b4f37c192210ce3
+R = 12bf2daa304f162454686f98330f526a21d066b430969547ccb0ace347cadb4af7bf62b473e33aa1f62b5959b7c431451913d5b1ad297b4c1f6bc5f3afc9e052794
+S = 08c7c58e4703f46fe0885f353f97bfefbecf5f10b95a02d4ac7764a0a713919004a153ff443ce417d24db60d325357408b59dbe7ad043e7fc7c1c23cda14a867d83
+Result = F (1 - Message changed)
+
+Msg = 71e7828fe247439e49ed9f048810967f6b3e012f14aa5bc5b66f1cc4d4c716735cea76b65fcd77f013a7ff57f3f64c80f46bab49a51dad2ef45b2573ecb77ea6bb75b95e9ff4362f505a7d997064537c132611eee43847eaec58aa2d13178bd5a3a58b672aaa899515e1ce0aed0f654a5e08304cd458e02f8c233e0ab9b72baa
+Qx = 087784b171cb62451eec46449a2a1ab769225288a092d833aeb823c99de8542ebef8c290f96636a45e2a9cab678a2c55e10283ceea6780c8d61d341952643903f51
+Qy = 14a9315a888dc2f774633ed1c5ba95e09b6898764dc5a9d568d727b56fb50d3b288eb77c9db3b1cd31aa204ebf0f2402fa513b782527ce5c5652a97df6bb05e35c8
+R = 137a47e2f3e1c2916a4a590adea04e93b4d18f2d548a3cf832401bcc42b1b35ad820e88a7efbc15d1462f518342cf81d41a40abd68651bef73816f58d1ace55e338
+S = 101e3233d8da91e092a6ed4db279c594494f73bd8d6d7bf5f6a8437146a29b1ba78fe3694502ca987cf108af9f461b6341735b8c2a21653d1b52010bf2ee02e02b6
+Result = F (1 - Message changed)
+
+Msg = a40e61cf7b4672c040a29575e4e1d5d1dc8c1d41f9361aff5837437e3839a400eec06f8170c47b5db76032ce1309ad44293383ae8232e060bf0345806d9ee5514c27d479c498399f84291ee849b48aa008b8b841465021dcaba9139b7de26e8ba14b82e0bfb5b9a17e50b0e050a0694ab785601fbab08dc2deb4cb9fb68a5e87
+Qx = 0b97948459489a548f94459fdbcff544e87f5b93c3ffd8baaa997f616eba75187f7a8fb13d848ddf427aaefc3cd001553c213bd1b1c5d892847eaff2d2663d90637
+Qy = 00eb07b08b69af1f15260ab6a8eb84f9337d9d3f99148e61f5ee06c5a031f1eb467e897b65c0d14773018929d9da129d3cd66b8f9c11ddede32bf9f339e3de57b13
+R = 1a31ea52171394839ce630bb1c2912b42b045c5143c3bb1c04a5b97a738887f8367c9607971b00964d5d9fc5d921877cd6b099a84e19024cd77249d263e729e7f7e
+S = 07600944031efbf27face352b6267349f3cb72eca5679d74d4a0d47fa6e84b391f4743cf2f4704afcbb9dcf7b522d812d268a1ff393d0ff1b44b11b6d75fb84d750
+Result = F (3 - S changed)
+
+Msg = ed9b577e7fcd10391222ab021780a97747367d830684c6062b4444544f65586a1bd9b07319a1c06324c59e954fac25ddc0e23d858c33493f27650de85a31807fe51db9aa4537d53f739592722280258fe6065412eee62db2c4d9bd6290a0b287dd402400e4ef81f72554d13c48bfeec95018600837afce1c4fd40643e9623607
+Qx = 0edc8ee8d40918ab15122d92522bd862e9d46bbb6550ef22a52de0e4fbb6e4a4635be48406bf54bfb24dc385f506086c0a6e1297cea60ec847007e798a632867cab
+Qy = 03e92534bf025440635fcd4d40e4b97c5396f33eb16fb1e3390830f24737b6b1645262b0336fe74284afdb99ed6b8551f82a449d80911b0c0f02592c7d210958b94
+R = 0a1f835da9b892687201294cf15769d7390e62e46efe1f61ce7ddc80fc47dc83c86db35a5096cee41289d66d7803f7e8e11fb9c9ca867123027af343fddf2b1b89d
+S = 00b5b9653b2533da8e52292f37b86aaef201743c6d12352470656ca165092d74a8f97ab1772299c62b93d61ec097c957ae231d3c80ef1b9dad1f40b06e0c92ece2d
+Result = F (1 - Message changed)
+
+Msg = c20d47b3e80bcec0e8e462bc8947f45abd17b57d4ffe4cdb634cd1ac0acca967f07753fceaa316301b113ad5ec97976d8d928795fa754adbc2db2a5ac4488757bd5e044a7b48e02bc9a49c74c45b45500924e218704e13c9b5279955279425ab35f5b20690bfb51cbee9e05d2185edd98a56d5aa4905e6d5de78f58c73c688f1
+Qx = 1f1464035dcc9c6dbc5e32c318b6b3e9def33cd2feb02b7d4b7249155078915034ef823a4d55fcefecfe6a10603891a4a9c3e6ccc1a05809bc510032d5fd30030e5
+Qy = 0ec160b9da57cd8e55630ab9524301ae7f0f53be5d55f7e7b99270272f6e6a33d6fa5fba73195d242e7ababa5cb69f6bfe9165ae3fcc1645df5ca4b6254460029b7
+R = 13489e2917236dce23e929f8c1ed0057b0d70c68762073c7b1787bd3cbdd084174f24aef0af10d09c77530c3f76099ce53b63598c0d8f8ce53df83a9af11b7e173d
+S = 111e1868e71f5e83eb5e38f97fbc466a9e729e19165169ad81cfd214a1ad1e56fa47bc97ef47a93511397c849e9da3f7cee68bccfca4c5c60762d99b8c41393b879
+Result = F (3 - S changed)
+
+Msg = 722443efc091e76b4469166c943f6c7f2f0338d08646f0f7e77212023ae13052871ba8a1aef96c71cb6bb4c376addee14e7d4941ca7a5caf903716266c4f98c777227546b13ca5d5a2b9eba8e6c7c2b07ad917cf39df89e0958e9b72a6ecde8e67438d3b69456be061b44c02c243d51b29a03f49cff39907bdf3093bd424abe5
+Qx = 01248e0953894616aa4b5573644bf4c0b1f45a5c0a47a193c3ebd2215b29dcd387d76ac98183894bed359f06c6de7bb94e975c3e6f9c1be3fbe3b763e2501b524cb
+Qy = 1971e69438e24b67baa6203ac5904159763202c16d6afa91298fb43eafc867bead0e61be1601a3fd70219af962f7140cd0a29cc26ebf765c22b895ad0f91aca7500
+R = 0215d8b547b0fcb9d18eeb5acf277f90d97ab6371aaa6e8a3c1dfe66d2c6ba5fef45260028d25cf600bb24560e599238b285a823a0dec5e014db4cddfb89ce64aaa
+S = 0bc5c4dba8bea55b73866c0b4bf739c764ba67121b9b1fb261b282fc1882f22eeaecb5c89edbedf90318ae8537554dd8604930bb893d21ba36ea445d0cfeaa28664
+Result = P (0 )
+
+Msg = 34497d9a8db31ba1edde4b48659895c8db6f22ebeba4765874b9dfec3a2ff4ea0e9aee89bd6d41eb6ef5cdbfa066319e48aaf8877629680c3deb9c23beb19f81e08b97ae4a61eadbde300bb7ee504294ef6401123a97425da8b3a981a5a0bfc2fb2327b773f27f2180646ab333740d4289bbb769a40f181e86ca0885ad5433ec
+Qx = 0bb34185d844a096f7f673f86b317c27e84fbd6938c1e22e4afb1120489c38508dc643a92ecc963b694dd6f2c7d0958966d49b20883daad4b00a8d0107f2b8ea2ed
+Qy = 1e5d3adceda7ed7c7177040b1845fa8064e187a16b9336294c1402ea2eb89e6c14bdd392bbdd2ab516aa7ff3987bc44f6dda8109452db403b39cba9536a39f1ddeb
+R = 0d1f2dd7534f9f093a281fb538660324fef9cec2dbabd3527b1482f980dc08cc84de25f83b062ee5cfe1d3372555b7bcf618c71fc464caeef5a8bb141f39531f15c
+S = 1a1be81c9379abd578ae9663cad8fdc892ff46144f77da469b832fec4e5eee8a6465be3f211f26e3b72de5a9e45aafa064e24d501fc1963733388af20c7b9c9959f
+Result = F (2 - R changed)
+
+Msg = 293f0b9a48e992e0c7e292c7de27e5af655f8bdad9c68bf68cd667be86691c2d5b54551a415aa41643e5f8c384db9328bcf726537fe8a4d3cb916a95e1a81740f5de6f0849645f36825e2b16b9d31dccaaaef6547a53d7d56b9fb8737b2e229f70f13583f5b1f6be85b63b54c43d8e812f4d1c29d263d139ec1f5c28b452def7
+Qx = 12918b48baedcb53edc782cef70d772232d1d9e1f5e995f70c76b510f3effcd5c239625e3ec5e37d202b37e4e6047a28d70b489b44bf5bfc2b2cf03c8abaabcc4fa
+Qy = 15ada9031e346257778a7b6a7d8285b9d66cbb27b1686ce3de3490c08a3d0a64495906f0ed6e1e4b7edf1ff657091f97bcc383e16f2ddb3c723c53d559fa0c5ffac
+R = 074cc58e3fdbee1b3b09fd82621bd593118fd4fb372adfedf8895f1775add9bb38fceefb42298c16cacff33af75e38443388b448ae251ff8c049a09fc7af3cf6ad6
+S = 0c51622876dadca150cb6be19dd5de70446cffd2bcaacfb8dfae4e1c7d58c41defa4589668b45958cb5f164bec71353ee57817e0a882c8643fa7bc6339dd88480ac
+Result = F (2 - R changed)
+
+Msg = e5f04509a8c69f4a37260c14193e32201a10ab3e2f77ae34e4b645fc98ed53a6b5ded8dfa53280d868972606471152ea371f98fd2fe0749bf4d16bb356c1d401a69f448069adf565b6938b513512c45e6516f58ee1635d7afe34fa1daa1e7a417a66899ac9bfeb9144f93cda44e9ffc9247f7d841319db0c43b17f1c91ec7c64
+Qx = 15f8a3371c14a76d932a83f242c56097843ca370385db632fd91e05939ce0f87a94028f9f197c435e89525da4624db332ab1b36a1a59cca8c1ebba281ef5ea48bd0
+Qy = 1bdd578714cab38b3d07f28f286a55659cb4de6bdbf13ffc149f0cdf71be6be2d11ef800614a1ab97731886179f50360bb98a8c74ec5a222dbc9b6762a4f56734e7
+R = 0c15e0d1c06abac899b90c86ba6e37c8b8cc982780262e303c94a0c9a1ac52554423257dfaedb70760e6ecd66f9b74913a283a2e44d05dc8eb85e5aaee5a4323015
+S = 014783e744895c7b6084d536a58e9d05a1a53a4ab96321d09cc4c89a908f75f01515c45df3c471ea02cca0bf9f07d1873bb3404d3ba5b51dcccf30e9a5ea0bb151f
+Result = F (3 - S changed)
+
+Msg = e4f2712161d03f16b6d67753130df063b8570d86c445c9100bca9e315891a9d531344d0ac0ca330bcade268d7515ed48ceeade40a8c334fa971a6f08f5181bd01fcbfc57c5ea58ced8aa2ee72a434ebb93ad0efc1e4a78795853edbf43bd668ae7094444e4736802b5e01120bf17ea6cd0a200523f2714927e5756a4f44584a3
+Qx = 0af896543430ecf3b22534a1a3c1c84fa0ae28f1cc659432417426fcfa814faef9397801f16da3bd610206c2ad62f775ca01ebaf380fe64e928cfcb48213a268cdd
+Qy = 1bf669b84b415f99e8e997b4e67d0b9f359823e0df92688c760ca99c08350f0375b301c404eee80d86af5de31e95d64ca95d9494e2d8622edda97282732e7e2757d
+R = 191e914f1520532b8b3ccc536b103e4eaf2aceda838117b7090de8b3c2ea03fbfc1f54d15d6fe8e6d2cbb794d0206ae3387e808661518bf5c6dd608b5a40756e24b
+S = 152e95ec2ba49b5e4d65a3f50a29d140b144f10d2eeba729e439f34ecd7b97dbe672dcc25647446a49e43f5710280d79fe01c0a7b7956fd80bf35cb6d7e560cc983
+Result = F (4 - Q changed)
+
+Msg = ac3afa28b5932d68d84d2359cb3042c42b3530fa10e7f2c9101f93c2713f64ac22615e406dd7642b39f7621722600b4e1d260faf6c30d33ffd53930c8eb9c4ae22735b41f661a2fdefe809b67740809e01cea82c0b0a8913f6cf9754749266e1e9058ac644464b1df77447e35f7f9300e1771429e32ab326145b757026352bf1
+Qx = 1ccee36646013645ac83b532106a9d78828cb387819bdec3f7d982ad2744292281a00d59cd4c1290365d5b821cfeccdbaa8ebd5f10aa1b4b1342bbca27e7619023e
+Qy = 171cfb6c2a95aae42458b6bb582d8efbeaf7219594dca5904b2b3c22a203eac193068e603acf1afd10125306595d0056e2bdee05aeef2d4b774498619cd5f1a3664
+R = 04347e5389a6b4a3de2e543d7474c28e5fa284f5268e474f8998395a7dd154fd0c09253b8160f9bae840189161bc3c85db268d500d6aa82a3c383aa025553fc25c9
+S = 10623dda9d2c39d5e6d463d96dc1ae91f0c3f34df698dec0de2e1840467aa54a5bdbe7815426b175f6c19d1a5f09cec6f5270658a80ccbfcf58a30e10cb342e9e01
+Result = P (0 )
+
+[P-521,SHA-256]
+
+Msg = 93e6fa311b9cf278babcd49a6739d312e5f12e05bc9dfee9bb37ccfb2f9ce57d2a3c0336674e094834a9fb80143c3c8ca82b34949596ad17ae6fc7592d1d93f143e7e7c842e17a7d230ace2d2be15c757c37ba0b1f34810c6e51786af718136db22c1f8336540cae5e2fc762ca43cd94c4babb1b11f8fd93a2ac9525324bab88
+Qx = 15bd9bf7a35cc60147b32b64e0e4e54bf9ac2173cc6784b3d4ebd076aa5d45c1e3d0846b20b61d6342341a8801a2f63028c991831318245c2fe31f8acde6bf2003e
+Qy = 1afb67c9c700ed332b47a2d148e6ddd3571e138f02a81c3cfe6d4dee0f512d92e76574fe5797c5566c05b3239fabb212c735615e719e718fb40fa6783c964357f72
+R = 1a341d0e8906239faace79554b90d1445bd28f703d7c7cc8eb163337ad3d4bfb3725cb06e618991491534d399866df5c5bdef897c889947b21148d89c657e64124d
+S = 05c5b728837d44b7b6935efb2b721b4f45c1675d803d87f70158e451434176d9682034c9b356b5f9181e07599bdcb55e5bc808fdd36fef9c19ddb6342c975262024
+Result = F (1 - Message changed)
+
+Msg = 8a3206879e6e463c6d19c4037c12c66ae26e23e09fa96e3b26d32bb41810cb9b02d55333733fad583ca5d24614c23071ee19e4dff9e4d958fc1de573e198eb6964cfc464ce97e69642c19c0ec75aeb01f93361b9df37cd2b1bc2602d967f3f508d1a9f3155a07675e8b1b53e79b608dffd6c4e0f0711fd0b8c6012eacd8e26de
+Qx = 09f21a6e7295b183656709089b3c647140c81f71b0b3812e6de22c52245335599ade6a3116cb70277dc2485f91c7b1f46d62afb60fc17a110358c9a02e02e010960
+Qy = 1e914284cea47dd6836e7ce899d0c9a88d67fc9d039ffa9fa5bee58d247e0d0dc9251be8b82afd3add327f98c5570bdcd8ad8827820032774d19db09232aeba190a
+R = 0ce4b2ac68afd071531027b90d4b92d9b0e1044b824ccebb2c9ab241d5b909ead1ffa2dc3d330f57187efbea7374bc77c4f7ce7ee689aa5a1e27aa78abc3cc1e751
+S = 0aa85d84f9c7fecd25064dbae69c16d6fcff38040027bf476c7f913746272b5d4b9bd34d2482e27730522df724895b99253aed86011139928fa9a272892f8c99d8f
+Result = F (2 - R changed)
+
+Msg = a2555db3870730ffbafd007a8b565e3c79103751b9c634a40e9ce79098fe74bb43b4cd990c50a80a50f8426893f03998e617a74c8997bd7acee599c24770da781502011747fa55b9215c245f5d36edac311640029663b44b01a50c9b8c5e53f09c11fd73609ce665c066dbee92a749847805c26039089b94f80521e1ac94317c
+Qx = 1098be00de7b2ee7390f26eff82ba5b6de8f04d7f11909193923866d2feefad9b01c5d78b699ce0a6900dc2a3073a03505ae946aa6f384ab0573ec9d17fa775dacd
+Qy = 106e122e7148b547a0314da646b6f834e66c2ff7f64f39da9dc7983e80e84063e23c8ce12994e8495b7786c2b3180d7f22bd2d2becf1e1ba2029cbbe8d4801b65b1
+R = 1092e5ccfc4f966c3281a3924cd527606ce8e64cfd78f57373cfd702f528368beb71eb1a2cd64005bb172cb35b4ea61af88cb06bc8f1a38e2d75b235d23947dc209
+S = 1aff29a28d935d0e10bf8015f38ec128e0ec047f04020d1474366807b140e4d4a6d069aefc8dce723fcb4fc803df30b3880cc6d0dfc75c291d848d89e06ab7e24d1
+Result = F (2 - R changed)
+
+Msg = 58a98d6740bcae94d49817a49edcec1bfe9799f22fe7bc7c46933ec74db0679a34dd8057b71c439d00da2dab80711b943a9f4560d4b5e7f58b79a77f84eb7ac3b9e88c8f13b7ea5568b8612c22e4e5ff6f83c36649917e7165be0f3c759b06ba44cfd6b6d54ad996ac2cc9054e8d3d077386f4835cd024116462257907c1b496
+Qx = 01ec67de63455605b31a460d4faa664697cc505885577c0844472842dee78fa6d522e4b942d3c7e2de684e6399f6a44a328ccaab5e678cd99d49f015e35a934cdd9
+Qy = 19b41da41e7506cbcb7c31d39751669cda166fd045c86e1fac68d39d2ebb0f1ed50b8a923511e1306952888e068092b19130181c2de5f25c5e1fc4fd9ea202258d6
+R = 1e1882a3d98c236189a35ffddc9fecdb7cb5fc5e3d0784eabb69d9c37862dbb38eed6c5567a0abc4f74099329681b9a0921515f1df83ba8948b51d3871866a8f7ce
+S = 025ff707889678f7cd05665c941a2bbe13622a1e75ab986cc86778658c62e527f55804ab27d0643f6bb8adaab0614eac47f33f0e1fba109c63b28fa6732a5afbe49
+Result = F (2 - R changed)
+
+Msg = 77bd3d86c52fe8c327649ce44ccb313cf34d6eee9f6074fd60a9ee3dbf3a84dc680c91703632d6f4ff39b8ea3d13090054d186b4a928b1052caee17dc9bee7a5905ca9bcbcd065be4160c4dd25639f2b23d1ce4837598917d7c86425679de1b33e922e331c1f3f748d3cbd8fc6aec68b73978f5d25d730c8a7fde247edd32822
+Qx = 0defff5ef7cc5de0e1ac32261e7a74e8c434c0b51f76df7566b612cc5b8201e7b38c51aa6118b6307f436394bf452a72224c977e37e410eae9525df2ee00a8123bf
+Qy = 0263b7db73558ddc783824f0b19776802aaf5e46ccb1b1d1dda07d2d6c5843f5036ae8d381b235ccd2ed04eb90c5d51e32cbd7acdc7031cae63c06797556fb66fe3
+R = 089bd129a537840a52ef434d5a8ba4add952f72f22a84ac4523ea0bc02cbfa8b681ab0ed3fa2bca24ae575f23fce7efbb9bfd28e465174158a5ad2b08fd9e0b7132
+S = 004ed533337791e05f8d097eabdf4be96b3fcc9f876d47fb8c5c7a05cbddba398cded2edf5ec9b7dbb4e32c1374b46953d66a193c211ef12de4b9d73adc369d5e95
+Result = F (4 - Q changed)
+
+Msg = 12e796e7b92085ce16fcb9f420ee18bb0b5b985cfc47618d7b28a9e2ceae5d526c9dab015c33ccadb05185f8b205875b20323edc7d0a53a6a35f7061ce823244c6c73de20a38650fe6ffad79bfae8a54dbb611eb55a76fa7400ffddc6421e58efad93f43db1b7aedbd63ba94ea12c39c686dc335c7205f05f6b3e1d12fb508ef
+Qx = 180f1e933054473e81ac82aa458094b7cb95d4b8d399600420cfb082e37980414909a133d5e42ebb7d2defddb34a9fb51fe4ab72e88526fc28608e152aaaba3ee5b
+Qy = 1c5cee9fd322d1c3af1726366e8a1e3f22099d9246d4bb02708eed89ecef1fc73926dc97a5c263afa235edb39a9e63d9690608846abc482397a2d8673c5d472c970
+R = 17f1fd4df519ef432f68b5f426ff23a8f36b5729fdf7c8363d73f4e707d9800c7b50174fc3d66d89813a5265f8734602e5c998c2d7b51bdef6e90ee5a527e1357e0
+S = 10560ed68f152d649493c02c1e32bf4138aacb5f2d7f449e7685336edde24e5ce1cfaa2c54530f1419593614971896f1a877dda7bc5d56ccdbab18e770647287979
+Result = F (1 - Message changed)
+
+Msg = 3c06bb2421c7ebf060b9da78403a3ef87406cbcc73eb350a2e0a33d20f6a59572d282091654f98b5ed4b41411edfd216704c44a3e295bd7174cd51818b021cb37bfc3f644023ba69fdc081dac3e5f6bdd7c7bc1f71549882566fc4cb30114a1f02f9c0e7610feb0fecde666eb94f5e43245473ea56bd6256610b08162dc2eb36
+Qx = 06d8c16536b17cab6ff41f5df4038fe416c05ccb601710909708dc561b02ceed9cf020441d9daa075e8fd604531ff58084035b1c19a498b82582f5b20f9cedf61f9
+Qy = 0e89d71c66e55c4f5bf245413388bfe9de83944b11d1abdb4692db7da8a086442965ee512f7089f89464dda5d7786e52cc26a8a30bc8824cc56a289fefcd42bdfd2
+R = 087f86cf4bd36e8253097ac1bc8500dedafdbccbe5767ec25e53c73c4f053f3b37acd1d5ea4c16e4058919b61d2a67393220ffefe07535d53923ace6815463c4c31
+S = 1def2582fd0df89fa28c9ce882f5c3846135f51bdf7f4b2497b190136ef04618eaa22a8c5a117b0adfc6425eac3111b6558df145a8b14ad39524b98659e01d51c21
+Result = F (3 - S changed)
+
+Msg = 08f3847e8b10f18a2f33abbec099f764215aeec9ce64c33fc1c6ae6e7dcee8eae995885dd91a354ccd2ac9bf8f9924a375b6387696fe415a08f7ee429318f045b9394f4d6e75ad099ebde5ca94e69414155f4dc271cdfe4bdc318122ae469f9a4b5f44550fef6d4e09925eeb579d61299578d6d84d99c4260ccae583e042b0b5
+Qx = 1c7fb4747a409a3723177c38c9943b81b2d0aee867b8f424e227f3a664f1877c560d37953e7cc09390e05599292bde1ea345073ec365834d99ac59332f6e5bd29d7
+Qy = 1b7485b454d5ed5d581c7897a7e68f425d8c23cd89b934747d90765a5fda1cfc3d997af61728f328cc8bdfca8a3ae1b3b90be13cf164c343d199b8e16b0400f3e33
+R = 1552ac2dfbe67c6abad8d3325713c1e28537eae620d805a73dbaa4e5e04acff6ae0498346d6e41df1cbdb20b70d8e548564da8fa239fe6c6f28b6c2a6ef57973097
+S = 0cc9e60b694d792f36cbe9adff8dc79f0f75b3ec11ff2d54419227c7566e0bd441655eb30b558c78a55ac613c1bf3c3058ea7a4bb70adbf5b49fcae15e54defd6db
+Result = F (3 - S changed)
+
+Msg = a1c88c643303f293bd918e30ac00964e52f78585be9ed920c579c48fa0276f749c04ad73e3a86697e393e7172d2459cdc30e0f1e2830e5e6952fb23c6a6e3eb61cfcb15a59cd6e11c3c2e080e78da3e0dc206ee9e1e5aed87d7b61d14702c59a116473f386faa21dcc97328f966771fc3e5ff72af66535f41e3daa4ebadd5624
+Qx = 16c0e1d1fc81e5069e9c02794fdfe1f5a8ac5008305d9ac2234eb0117e565203acc6777c570f41661c5db1adb26097d7f5f2a1762c4f8039f1b68caad75915baab8
+Qy = 00b3690995d6d881dc1564f792ab174cdc1a0fc6f12d69a21088d5e82de4a7d56947a2dad0ce64d9ad0675e72b6da755e3ef82c9cc6d532378c23112210236889d6
+R = 1316e9a934cad1aa0f7dbade1c9ad942d61bbe1bf41b7b95e3b25b761b9899f6125790369277aa09fa57340a2b8c3c609a08ae7be5a3c09dd4d081e6cb54d9f3061
+S = 0d6b285f91c3c8d6192af624336caf793ad5300d96262f5e25228dfb60896c4e28e61be22e92ca7d6e11a02f36655441032bf291f895aaa117f6bfdfb422286f255
+Result = F (4 - Q changed)
+
+Msg = bd980fd69fb9e1344540e5bb12fd0aab8199a16ffec416edfede8084b7cabff5891f8f04fa72a3260403adf5ee286efe9dc128b06466b21915c394b21ded8d468ec1f2ff82d6e4306c61b3315c8b131131c1ee8d093f5aa47b56dbf388cb935900c4d3413dde92cdb7d6b8c35440ed962d5ef036b241f2bc51842fa64496aaff
+Qx = 06194b1780a2416dde8c9402e3ddbf310c51ed87fc40530ad5c97931b99336c00098337fcca7b01c634e56a7874309177364e6d4c24c2ab33d6a1a09a84689ad0b5
+Qy = 0c5bfcdf640c0a7573ecf4a9dc1aa75db298ddf1a679609e0669182a594b9b9a8186ee961b902d84fe998e3b380c304a0be98974514966965bfef9971f05a57c162
+R = 18051118c2d8b841c6d78e2e5068c7305039cbae1f8b5a479b9bba559ebc45d8c8ac18d1f6033713871e656fa4eba9c1c0892e7263bb22c46ec3c72aae92afe2c79
+S = 0de0db6a6ba5e6a953a126be3b87d6c895f4bc2db27be223109dc67cf115bbc8c566e1c9a1bdf1a87e632f8a0e4b31331a086caeb60793e87f03b404140aba206ae
+Result = F (4 - Q changed)
+
+Msg = 961c9451bbb298e17f503680099244d969a0ff3d0ce6cf15b5bcc73d6edc3e8c8535a18531d885664612cad97da174f1daee6aad95220f6e2fd8c734c57747e46db21e169a03dd673df07aff30848e8370c0960d732e74f9b1d8b53847b69d2cad80f346b50e89d7993cb758fc218668c771422f804d3c9162da98cb30821912
+Qx = 0397714abcc503eaa0c18abd1fd26586d28ec1b1035d37ac710f2823911ec9afa429b41ea89cec13d5bcae9d6d7147794407e409f3b267cf4dd27e8c77e7ccf4d36
+Qy = 0a3a4b749d19b84708e42b59e9faa5a99ac0f0a01121655fab87785fca38c8cd4277c8c2c9a0024ff608c3cce954596315dfe0e3b133aeab08bb5389eb2a4f1fb42
+R = 19da96a866db12948e0aec7231f797061f345739d439bdaaba63e4d03e0bb52c3fea2fb593347d983f24a3afa6a77f476e6bb49a5de843b4c4755cddce97b8b909e
+S = 01bb442f428b2ca445a75ad88ed49d965d6659d748d02cebf78faa1ecc187b606f284d11d47791d585dc371c2d91848a55ca7b092f06d561efcf64e0de0814e1db4
+Result = P (0 )
+
+Msg = b9afbe0d18f798d2992740c35217eec0552f0812c607ef823f74dc2eb2ce58a9abe1c683ed193245a81b9f1eeb68d57c721f052f926b1ce3d79751bccf007375715e70b52c9bce92a6ccad24c205d43a4355d084dce3db2f50ab7d4dc3c6c400db8db47a48dabf295801e960232383480f029c7111bf8d5d7a0c9d64c9465644
+Qx = 1af06b10d357fc3c807854b4be235f81d5036da4df1af6a054a03ff800c1aa2d59c2ad5c0e25ed25c002057cae4b4adb92b95c36cf422a46c8833fd8968e0f32441
+Qy = 18432172be0e535a3f3a5f6d6927dfbf6a00051cc1983ba25410ee3598a60dd1f7c38526de7ee23f8e9ee973ffddff49eb3edb28adc7d094cd95b63d52ba45ecb58
+R = 1396b4f044919d0ba5ad43004cd37b8bb0626ea5549d57c532339358ee1794988a7c9eab91a9340dc2aa0f18e89b236a6c20d03a6e98f35c011430fc4213cd65dbd
+S = 101e5a788a867d9b5a4444554c9651173f9f8e15c0f39f9adb66c18ef8075243f23b95d5229ccf5f56b87f5c50920b01b22ab7476ecf4c865a3d6d8f2242d422d8d
+Result = F (3 - S changed)
+
+Msg = a6c421bfcf95f7dc2f3721c56eddd2bf58bd8a2717396441d95e265c8a3c85b031b80e5f90786126f578affecfb4fc2dcfb3adb96a33cd0953b109970d218a6e59a688b6bc7d51e64eebab69929fac48f45fdccd2a27c1e1a48f19bbd36e5f8f8f0d8ab3f4e2cca2301893f8c373794582eda7b700f57d092d1662b929a2d43a
+Qx = 176f1276918fed24a098d6d03077f3c33ae543316df1b6b06ce877e74b69b2cd4131fdf797e77e5f6391b0b32411120d03c0c59ba1721a7187d18708121d6f3a86f
+Qy = 10f9d38b30a2da1a745840de7c9994578e32bb10f9334b46f533b6eab550aa55048e4ac601889564ac8314e01b61613fc7b8e2bd3f1a188c5c5e869af16a8d61d9b
+R = 19cb5639a321e95214c90a612d29c9ffd5ae5aaa2a814ee2d66ac1ce1d2ab3229009129ec9d472061444cbfbf50c7e4cba09aab65299a42740bce7af3fddf2a1f46
+S = 0082ce6bf1d809d3bb4f9f09a95590bb64b0c41bcee5fcdd332947a9b59618da5da897fff44968d92635e7833dec1e91d8d99bd8b527609393b446c83d109a32243
+Result = P (0 )
+
+Msg = 1e8824c203e8915e62f5304b021a3a1cd027f5dfed3366e123ba28273b1a63956006aceb45a03b5995f14ef08e430131fe93123a4f91683cb0074280b525f7342963e98280d63ae179cdc908a191fed000239f1e56b012b7fecffc1d1a5883a29a78149d507205308170460da5a7d5ade323bef2c9ec4b9a336cfb8b1b7ae473
+Qx = 089565cf5838658fd36b70cf5246cbe999a394562c46e9d8057928e0aa9e04ade6002cfb83f315e06790e58ea833b3bd64fba8e93c5fdba8319c5d38be7cf25a21a
+Qy = 08faeff531e683d28d817045a03b2dd22e50e6168f1e5fda5b5abc71859effc5e5c45b88705b62ca090e3362a8313dc472ec2ed970bbb5029200318e7582643d613
+R = 06b5237ad17da6037aef116532b3aaa70172d0ca0eebdc478c35e6f8bd0f9a6472d052c5a18a23dcced7be6e5e7b6d0bcb5b3cea707000e7d114b6f41084d6f5620
+S = 05e2556425b35e6495b137f7dab522c7e7b812004c87a002f6ce4f4b6cc5f967b8f5b7d3786a17d5f717d3ac467b73e176e90cdd8c5151a6e62fc4604cbeab7e717
+Result = F (1 - Message changed)
+
+Msg = aedf4e8089c90d95f870457561df7fe825138073e867fe13c39a0d0bcd77dfa2abcd635ca40bbb71eeae2b674075bfc5d5fc7d489dfd8f34ed30050631238af2122f7d45cc0634ae8a2efca5cbcc4f967ae55c290f77d53f2c03163f532f31097bc34f531823d23de7e5a9e09a1d17cbd9383a4381f3f6986368a6014fba8b96
+Qx = 0aa42473f80d9d81f6d41ed05c8ba35c005f90e2690f71dfdb12555b7590c7a8e95b618368c39f4e84d6cba25f522c9bdd256c60d3f8c8425ad313701225a9cc9c4
+Qy = 1992b7966b925f42c91f810eb05d602b804301849ea278466a68e5b616e3a0bce110fc9250db14f9c8f5929347e1bb8727bcf8072c6aebc26958954fe96df04e139
+R = 0cbb35513420f206bd26b568712503b66e159a54e154c8d4e9c661aa954e0bf425871275fff5e8f368c8ccc77ffe6adf84ba88a84483d8ba5cc862bd408f6a192c1
+S = 02ffb4e461e3161c801ad217a0483045181013deed29eec29cca94776139ddf5fe9d7771e5ac7b637a4bf7e5276940489bd8ae36f41ef6be93cff4b96bd0e1f3e59
+Result = P (0 )
+
+[P-521,SHA-384]
+
+Msg = 4db7b4e0b8c91130fef9bd8fc4ca9c1b2970103cd20366371b1f0d4a00885cec613f5aa54d723289f4ce252d446b8c213f9ee207196f88029e66641673b0ed5cc5a2700219ad5dd6c35486c04f637ba15c77dd2a5b53b1bdcc7c5efb194de1e00adc53bf78ee5b7bf69e9efb337d9f24d697838ca5ad56b08903c5891b84c096
+Qx = 0984cf3de2bbaf1b37ad4e9121a1294a0128d8a031ddfac7a8c5d7c9db83699de26c50012d42223d902cbd4be7e6fb611f4502ce8444d43d3eb0685aee07349d0c5
+Qy = 17165e8feaada26cc599ee394dfb5de7e2201004f755ebecb92ffda0a24be55aba88ab9b3c7a575884ffa7b78b631806f54e01ef875c5819fd2d52dd6369d649615
+R = 036c8554602661d9d8f4bfecbb099f01e9e314136e50c6d026de2297bbaf66213ea72fce13b73bb07e6e333523f19d3910983ea5842a1b634b3e3ec8157d270b496
+S = 129b439d3ba2d66c89c34be2a674013128dccfcef33f5d3844c4465381453c361ce80e1b52b6a611749bc70933655caa56da2c5dd6b04defcd8baeb2d9be06f3caf
+Result = F (4 - Q changed)
+
+Msg = 66fadb3dc27fe2a0057eb1e0aa3d49cdb93da4a07bb5c4c01719f8deac82fb0066d9c1466ae5ef67d1fee3e2cccf3185a24c8cb58c18df2bf0ca0caadcdc0ed63107b14e3627a9db7efc88544a91774fed34e335dde43a67ca44581bc9757932414a0fc3970b091e94dc52d39a9815a4aed5d27683d8c537c37e140e8f512750
+Qx = 0f976d58a015d3015a14997fa3f59ca8d762a6541861be923d6110c9e742a0a2a77d59a6a9335c67f13a626d9545b27c072349c3d20b80c35b0a9490f3e6c5c1b3c
+Qy = 0425c22ac0755c58fe3497c1f1a9f537d5e26127d9b031359c2378fd4b13f83691a854444eac3fa346bb5a63bb9567c122945ce99d2aeb0bb1b956ad348f7c9c461
+R = 1ca7346a2efe39e03e627ee9480a9b7c925a6677dc80932ffd67ca52b7e46acd2063402545d678d218ac579a64cf1fa4eff4f32f92d3fa4510eea22472dbd3daa72
+S = 0893d86a6502d5973f6c766413e7c7ecbc4583577c58672ef36a76c83755a0ab65af0e0af0ad0f3e6cb8f9ef67669132ce7e996d6122cbbe1dec710a7ba9c9d1ff9
+Result = F (2 - R changed)
+
+Msg = f209ba5871f0a05677c7ddfaf93d39dcc69467fb6dd99b09c7685958aa155838779f9df0f2ff04b6b80275d2e9abce8285333c18cac19a42a6227ea1ebac521110d393e4e43bdeefdda0b3f9ceb2f3da6c5364d44d2a18795327668624fb8dd8c9e33dbc810f4c24edbecdfaba6ac632f5b2831f42121f1330930902452fbbc5
+Qx = 066ad5c073425bbbe3a1d97ce6e1a9f2c298392c5afb95c60eee1393f7cd5c9a12c283258b1a53f2ed4abd13ba1287f3a1b051a09cb0f337cb6cf616dffd16aacc2
+Qy = 09d2b2afc181bd82043b13b8222cd206b9264d73b229c71d9abcf74a478a7f7088bc8c7bb1e54882fee693340a3cf1aa56ccc2fb81d2675b19bba754dae0c2f00c3
+R = 04e6f08380c43f225169acb0e9f3ff61cdd2e9b713d149f63b5b6a4510d381409648fc1d442fa1bbbce2a8fe1ff7d1de0597f72d7681c79d3a876db6d3ef89ed192
+S = 11745ab4dec3542cbf37d10090d6038bd1ef9cce8216a4069b21e4a08075e7e8502ec97b99d3b18fd314d6ab6826bbbfaa2343ada1abc7c3b551c0b854dc45ffa75
+Result = F (1 - Message changed)
+
+Msg = 978116ee2d7fcbf1f5013fc84153c5fae7c1785a2fee2c7bcacd962aef6dc201ac62b04eab505b6a5288ea21d41b64114ce01a0a01c617ffd20d1e70babf1af1523a285494a3fe5bd8619bcf87370cafe1188d9843ce805db9adad563d0d2832833a8898bca03965a2dde6f94d2be5a653eb389b6539ec78844cff4d4df532a8
+Qx = 068801cdbb1e07f4b72218c52aa24bda872f1b2ab4e0c13b686cb8b10096ff88018e82196769359227192752a1c4c884f08cfa7f947ac428651f528bd41d1034073
+Qy = 1aeb335cb89ecae3cbc05681e2170870dcf40d486db4011c4d7bd84c58c6b3204161d9ca3516760b0c42466605077c96c0540939c635bf5d7d11e1407b6da30c094
+R = 1ce67a3509d59f8a0f171b86559f1d84589ff2693ff7d3ad3ae64b0e5af85db2fd99bfd7eda6e8f984a87f16767231cbd9026bed0a9a49d74ea5047201227c98f41
+S = 032b0e4c043df8e81ff22c9bead36f704c992ec160d6be7764640200e1307002421b5d73154eccde012b463aeefd11138c5b9b705623c2c849736da23c122df06f9
+Result = P (0 )
+
+Msg = 0784227d3d40bf646f7402cef305863d59d904b16535bcfae67e4e2ffd79d26103c4d3f096493ad46c09a0cbeaf61269d49df46494a860b25c8e5cb40227eb8aa76e6307ddc47e5297393bb5afc946fbae5f8de0069ccb62889df88560a0dce85f888f83dcf80ccc6617a51466eb9d9cd450cdfa75acba6f3ea43cba0760dd0b
+Qx = 01dd34056fd2ff3009bca2d0bbfa70ea0fb678597d41dc545358263ce2cef9a2efc016622c12099c2a50257609d6a14f3c5ffac8a52661e4a34689a3aebdbe86163
+Qy = 17926740659acf72f7c7a147a3a320d501efadef8519bb289ebc33e348d6b9efd65fa516048101678548898619d311b8ef2a0d4a6f59f86810e9e6534176a24faf9
+R = 19043db42f44b957784a0e1f09d2e0a0dd548b865947f93b516f249ef1757402544ce5dc402cf8c1f180e9a3be01657258a1dfc14b25ef564805651763d6f609d43
+S = 1e0b45e00bde9c4e8dfe094f9bcd7af5a19b631db850a69bf0b6291fd3df6e26f4c712e3b5d4b7b8572f637874057d5652fa2bcd1977065a695d26a80669a23f0e9
+Result = F (2 - R changed)
+
+Msg = c1c9b8b123b5680b07669c285d3cf9e82e96fbf5c9cb7409265b2c57036137ef73460263b7a279f363bd7a0c7f72318b8fdad4a2d5f8f2d74b4964e54a1409554bec5e3e36d7e594b3af9b4f5cf28e59382f56c1c01a9a6c5c12b4abd127726a7fca24f2aa8281d7e86d6e61b460f2436e23493e83bf99acee860ef609ff919b
+Qx = 16e5b4f4ff81c1b1e7956103c5cde951c56b37259fb8bf735b386e4d8b3d44063ef062d6e179f618a506ec8ad9773cfe99044748e2c8ae229a51bca6262aaefe2f5
+Qy = 00069bfdb9123885d8ce4ce67c63311055aa9a1a5150197717a853d0549bd17d2683e427fc90a0b78af5dc96465ea3f2862cf98e8f3ee2a07089e8837aa8d09d97f
+R = 11550cb365daec01901b5a5cabe7930c10d79128c5e510d58b7593c88647eee811e6fa736b26351558cbe7f17d7c882bfd1ffa72ca3bf4bc1cf1c05f31f5e8bc057
+S = 0d6fc97ad14639a5157c92b39cfd1315d7e940a454f1289c8e95c8cbbce8731ad37180554e7a91565d86cffb3f5caf4ef883184d717e03eb776af714a32234e3f5f
+Result = F (3 - S changed)
+
+Msg = 8d2f5ad1abb9f5cc9a981e24ecdbc6f2fd50d52b848e872c579465121151341c1ec8e01165a0365a2e36a26f119b283485e3e385141b4c4d03bab2894211595d46839699c36db0551bf32aafa658d819ad8ae0cc013570487f2d4c6de5c4e4df311f4cafdfa47cd6495d99453bc6fbd0ae538917f6f49a961551fb0c6497b15f
+Qx = 0202896ccf6710cf780bef8908a2783b3c8d5b8356f1546a1b6b909b0d65ffd7999a16112d8d68c837597656e520a56c2f6578e322df6dd794d2c08bc5d8f9f4c37
+Qy = 0576152d30218c941e83080a502cdfbf9de7ca2c394969e779b76c359ffcb84902ff89e37125dea7dcdea0ba928ce2305c619b1906955e6be5ce40d087c5245eb45
+R = 0bc6a7f5d77cb6ebb36a261e80d739f42b67ddc7a6496acc0ba7804d14b4850cf3fe4d8b56cdd8c019ef9f0d33aa26746018fbb4c69f4587b6da1adcf2feee2b438
+S = 0f09c6a94a8550a2781e70b4542096407fc07617f537cd27f1a1ddd15c599d5a9e3fa41da57094456277b44b89d40b26f2cc054fbe657788fa9d71659008d0d698c
+Result = P (0 )
+
+Msg = abe8ff2cc3397f3a914d6b026ed01dad7dc33fc11a736060a217ed20dd89a4458f8ee0a670a2f489d0e00599f5aab560fed8405496ba51548a07a722a3ff3546b94572b4c0abbd6503a46cbc7a38dfc9322b702c6b17a38a06e3736749801adc08f6200f06d3bc5fefb9ce72f82af2d68f55e1607602ce6670346b93ac1280d0
+Qx = 06ee95783b768c895e2af569bb84b0b1b00c8b72eec022df255892527987ffecdd81bd8afe267408a8912cce80982bad79c30610571a37d2a0e027e73ad23923b8d
+Qy = 1ca3f60a37b18bd8b08529da1e39f93d518ae3feead5d00e07150d80d641b20e887c62e8e910ca1c2f64cdcfa678c89b2e3012e3d9b96088ae31dd660dfe6369cb6
+R = 06823e8f6514e42e79d50a112f0f320ecd53963729038ef0d66d5fb59e1c664fda493027678a02b139fcf290657fffd7a529f4f38ac73542f316e1b0b25b3b88cfd
+S = 1b3bf9e54b0f48bfcc7289d187e831d94d165949db3c660cb63106be1b933e10614e3673bb8078bd8b80ba052c63d566899e618ea31e2a37e0c9c10da111ad11560
+Result = F (2 - R changed)
+
+Msg = 84508e6d7c687b7425b212230a1754393156c5643b80ac3c4023783938ed972f6644658e0f4538248adbf08533a10f75f21081dce9636611461cf8bafff496b984cb933d337b1b8405cd2e4626cee1cd9fe9acac22efd1c434eeebbeeef02f2a1c4a5083dd8651adee80aeb41d1e45029eac3dfa2967e76589fc5edfad49849a
+Qx = 1ba73e2af308df78d4f2a9e552c3b9fd35d35bf20126fdf751d8ad9917cc58d734fb9de27553cd07c02eabc077f16ad4532871a8aeb59bbec82e46ef1581e4abac0
+Qy = 0cf888c75582fb50bd0de724a9f4834ea127a1eea437b9a05935d1ec06815bace3464c230314b7f796423ba9fa983b2e6d1eb0260a32cf2f163a5ff46a9623ff149
+R = 1df7e724658f1666aee8d5d75609e3f5215228ac32b978ea53434b7d154dd4edf661c688083d0937e43836c3611526c75f6f26b08f7844a95113ea4a6f1ab824a0b
+S = 19d40a7e03bd69ca568f70a066a4a57c0e6ab82dc8c2c8aa52b00c3ee4c327a87eeb7d837b0c4de68e25f7ac7cf6c0d8bbe0393b98dd61ac4961c7f8c70b40082e0
+Result = F (4 - Q changed)
+
+Msg = b4b1372e94253cdcc6af6139b12dd61fa559299e80e24c900416fa79f9eab738512c7c381acdc2fa4d0393c370ff38d371ac96a6bfa47c4b8fde12402cd27c704059cfe1cb7c3b5fd009f415b4827c7ec0ff32501ebf4dfb179b278f013a16746f52cb5005d902c3cdb5a241a462fb9b1c86576c3a18d21793b0f2403c32f793
+Qx = 1419bc65174998ac21026f81e6807d8b42f0477396e7ff8a330e17c1d84bdc9b39b2a310767b46c41711f3f2fe503504350c86bf3d2b39473b64822ee32dec526e4
+Qy = 184c968f6ad79bf0da00520e5339751cd9c50e41e7cd21ef37756bd0e36e23a8071e5f0240988b73acb3bb2b6002002e09bc7ef70ffcfc7cf42d6b7c65110f54ae0
+R = 0d785b38c5283466f796988242aba08398ed2493aaabf959ed0e8b7b915cbb711d7694f94206db74641a518642d43c843ea7f43b8354a956a3695764021cc5d2774
+S = 12c20c6ab988ae911c7cdea0549de2e40e3e68c47cfe58fb777ebc204641bbb44f2c8b6a0196d330ea2ffa1d8cdc1dd9be353f1c657e43f7fe3c094898a569c45b6
+Result = F (3 - S changed)
+
+Msg = b96387edb83eab72ea30c323a7871fb0704ea23b21e20cdda697823b33fdfe31ff8b1e7b991b1cad074d4dee15ead4b298b56aa62477167d40350f864f3db57a414e75ba06223ca29b42676cd57cedcd8031e76de66949ffa933f3b8cf717baf0d7fe21b84bcfe7dbeadd99d665d1ae90c8f74cd6050038e32920aa04c0820c9
+Qx = 10f3bb1c96a753d278ddf6435e7a79a53bc2855d26d9f8d5c1337b0fd7d70bccf204377a02a1cbe95cb63e21a9e8a3ce8ee7c8d4ade16ff4083dcacbc6c4b2a350e
+Qy = 1f98a0273c48fa78a91c0f8c1a43f59c7bccb74780fa38b08989d334f2ba0353a3619e6d4a1072e4e052720ed10e4f2c07e12d0c81a062fe912708dc51d4cdba97c
+R = 14c4b9e23f51df21b4e02ed7611a8530466d1ed799b50b34b5fcac3bd1d63fa345925122414119cca76d22c167c18ad0fa8e1b47b53ab0f201bd4ca7ea25e011965
+S = 0ce91a050938119f80b5f584a9d9515c998212f6e122780f1607cebdb9b538dceb2d4039ab5e1b13736f4166e73d86c720516f20ad8f24e4b9fadd459c2988534ed
+Result = F (3 - S changed)
+
+Msg = a56d82d65841bee94ad279a0c9bb3354caf8471ac11bac1e6b445ee0415b9933ebda8d54d8500e132a3f5b3e9aab72c4fdd0048b9e84ab2b1d4acc3df4003481a33cb7243e72005a6fd1e15995d7b3251fa47605d220ddb1e24571187bcbb67392c94f0b308406f5ee4115d5f18227c98124a087bf06c4c31a93a558bfc6d937
+Qx = 0819178ace7bf1e6e942fd6ed69193386f6c90cf65b42e9204d34ec96a0ce8fb92552ca57a7ba658422dc8b53bee150170362e6e74bdda24fb458271602aaa9b832
+Qy = 14af772624921f61b3d1275591ec2d68702fbf348382e9e552a9b6c110eebf6e93f20c8bff287d504fa08ae3628e611fc1262736916fa9edd87db1c78ed2426cab2
+R = 12c45d6ac0b5dbd9647211f770c3cca4411666aa39b6988a968bab345129237597b6c9b3bd788c5f9f39a38463a8afb159ad72f19e7e33e7f9ce8d67d611c3d9b46
+S = 1684000b3d7381aded85b18576832c4a89b4faeea0515454677e29e3f072097e786fef11f72f229b63defa1c2fd3c07090b34f9147647035854cf2950c12a8b16d8
+Result = F (1 - Message changed)
+
+Msg = 9e49b40d074d5e899060654ff081fc11ea9cbfa5904e00b49d5c0a0166b61e302ea0dac2ab5567b7fb1f5e116abc48305ba3013ce957aec0f239f7538fcf4f26dcb03540837c4bf8a3338700306e3c6aae6b27c73ce8948856f6c2120e96faf0b52a5954d9134a9b4b9d5395bbbfab3505acae48b30fc58e7676b522908b44b7
+Qx = 11f8e50ed6905b029ce4b16c8acb8ed9136b1c5adf6f11bfb5f3dd8bb1e208ca8329a0aff9bf286e3be90e4d61d5147bcaf2293f934862cca6aead51d6e0a083093
+Qy = 1963e84a2f06a9cb273a424ee5fa1ae5900fef348371cc91c99323f58bbcd8742a4495a4f7ef52677501a4d5d663658c1f6c8f6edef8b7880e6894ff9e52bb617da
+R = 12fc3e0c18c4edbcda4f82b5136c893a6307c3f60affa15d0d99fc0e4a3576b7daefa363b3a362014d14f631c35619f6861bdff9a7b503825bf9f027fcb9a31fd8a
+S = 1a138d6b02fd2a7ba45f7f952b2f329ba6a8e25697379330dddd91d1d6e865d3df1541bc4717d3e09b10a57cf38dcef587ac31b4a8abedef43e4f6cdf6ec3f49eea
+Result = F (1 - Message changed)
+
+Msg = 036fdf92f353c2a55a33f54d4f731db18e56a5339e731bd09d0b8554806cfbfe36d3c43395c70505866a5659c246fb14a845635d73e222bfbdfad011669d2291fdf88461cd888fb32e5d7f63935dc536d390dc9a9d3f4a67ac1435b89002b4348d80a601b61bfb8f95dbfcee4fec34acf0af907819e2be2d3b68d8eaab4789ec
+Qx = 1efc81c1efc7a9bc36ed49a5ef6fa1ba641360fa5c0f96cc1e4a3f4d973c95e86935d979fc2101370777637ab210a56fc4173a50a758725d60e9f925f2066d2bc00
+Qy = 108225fc94ab33c74aff785dcc68c45cfc3cbbdfa3481fd2a3f97308be671fb32fc8d268c129d97f140210def188dceecc9d712ac397793dbc39c5cac332671ec54
+R = 0480c48a24e7a7ef832547d107769254fcdb4e7982d0e6abd16822837fd4f3b66d81e1d4a018606881abebd220ed8ca865d7e00499ac9651a98c65502baebf34a98
+S = 0ccd22d1b44a1701c99f662535aea9abff7e27f73628101f42708737db8b07effdc2b0b05d4ef233c5910b6261ae9d9c540115f27d2af766c0494c33d31bd56b3db
+Result = F (4 - Q changed)
+
+Msg = 9ce982c91af08a21d405f96abd6204588bb0ef1c8b78305b06f36a12d1914cae9dce6a1f1a0b4c42b067667c457c3e90e56f34cff0116bbd350d27882dd6e47997c944dcead9cb945f7c691078c1b533960a55f93d241970a1fdf4441107d8bc8af5aa8e088ea3aa82c7f3286e815dbb85d5cfae0aeeeb093468cb55201eeffb
+Qx = 0a15c8040f94235b8b444f7a74ca293ed1b718449911eefbdb74332687850a644395394c690aa98e8064f6eca600fc3f659208c0f8a21a1e7113bed0c6e00e3176e
+Qy = 04bebea7037b731d175043dec3630b2ee85c680a81256921a89407c14507c10ac043deb5d474602211ad58cb569a8b805686bdac3ef7ff62a4d25b27200706b603d
+R = 0c1a70919025aceb29dbabdfc2a43715192cc60fc3d1ceababb40f91e3110b2cdd8f6e9c1bafe7415a26fa4179f8fc261b143ddb094fe61117afb13adae9db8943d
+S = 0197d7f87aea8d6ccd2178614b147b290ec780c8075f8439137803c0e9a589e415d84fa23f5f31d61c1674f87142d4ba4f8473fc92d7715c281dcf3f1ee5c2f1390
+Result = P (0 )
+
+[P-521,SHA-512]
+
+Msg = a0732a605c785a2cc9a3ff84cbaf29175040f7a0cc35f4ea8eeff267c1f92f06f46d3b35437195185d322cbd775fd24741e86ee9236ba5b374a2ac29803554d715fa4656ac31778f103f88d68434dd2013d4c4e9848a11198b390c3d600d712893513e179cd3d31fb06c6e2a1016fb96ffd970b1489e36a556ab3b537eb29dff
+Qx = 12a593f568ca2571e543e00066ecd3a3272a57e1c94fe311e5df96afc1b792e5862720fc730e62052bbf3e118d3a078f0144fc00c9d8baaaa8298ff63981d09d911
+Qy = 17cea5ae75a74100ee03cdf2468393eef55ddabfe8fd5718e88903eb9fd241e8cbf9c68ae16f4a1db26c6352afcb1894a9812da6d32cb862021c86cd8aa483afc26
+R = 1aac7692baf3aa94a97907307010895efc1337cdd686f9ef2fd8404796a74701e55b03ceef41f3e6f50a0eeea11869c4789a3e8ab5b77324961d081e1a3377ccc91
+S = 009c1e7d93d056b5a97759458d58c49134a45071854b8a6b8272f9fe7e78e1f3d8097e8a6e731f7ab4851eb26d5aa4fdadba6296dc7af835fe3d1b6dba4b031d5f3
+Result = F (2 - R changed)
+
+Msg = 2fc1140a7414e33ab469799f9432b30d29d1e4451b28a756a0f24a7f7f90cb284fb443c074267a7600b370eefffea23078b4016b59cbeb95fab3c6f37a72e92271b29ee2382e1106f8dfd3871ef9bf045f78d378acc8d16c983d54c7bc0b0cb46bba0de78630f6d0796c2c275e46ebc88e6e6c0e675ebd849f02e47f51abd215
+Qx = 1d6aef44370325a8a5882f4667c21172cdc8fa41d712562883ececff53883ac8ee276124e825088c79d6c9d96323cb7b8c0b7ea44d3f0026e2538f4b62d785bb1af
+Qy = 027203959a6e944b91fe6306debe74dc5dde9831fd0ec27e8be2d0b56807d63151b15f6495b8632e919e1e6b015f5ae5f2b6fb8cf75b5f848f00cf4ee457cebed3a
+R = 04417ff74889dde6bb1820b5d13da5c81dcf9b0723ee89bb1ff0d3faa90d497685709f315b2cbe55481dee43ebb6d25b1501ae69494dd69e7bffb72f987d1573b93
+S = 0fd7aa027c665458c7ac11d54d4f32cb4a1e727b499ce27b08d3d647c636cc3222a4f0a6057732249ddc22574d7cb80c3769c3ea9de3d33db3edd8ea90cb3f8dc8a
+Result = F (3 - S changed)
+
+Msg = f69417bead3b1e208c4c99236bf84474a00de7f0b9dd23f991b6b60ef0fb3c62073a5a7abb1ef69dbbd8cf61e64200ca086dfd645b641e8d02397782da92d3542fbddf6349ac0b48b1b1d69fe462d1bb492f34dd40d137163843ac11bd099df719212c160cbebcb2ab6f3525e64846c887e1b52b52eced9447a3d31938593a87
+Qx = 153eb2be05438e5c1effb41b413efc2843b927cbf19f0bc9cc14b693eee26394a0d8880dc946a06656bcd09871544a5f15c7a1fa68e00cdc728c7cfb9c448034867
+Qy = 143ae8eecbce8fcf6b16e6159b2970a9ceb32c17c1d878c09317311b7519ed5ece3374e7929f338ddd0ec0522d81f2fa4fa47033ef0c0872dc049bb89233eef9bc1
+R = 0dd633947446d0d51a96a0173c01125858abb2bece670af922a92dedcec067136c1fa92e5fa73d7116ac9c1a42b9cb642e4ac19310b049e48c53011ffc6e7461c36
+S = 0efbdc6a414bb8d663bb5cdb7c586bccfe7589049076f98cee82cdb5d203fddb2e0ffb77954959dfa5ed0de850e42a86f5a63c5a6592e9b9b8bd1b40557b9cd0cc0
+Result = P (0 )
+
+Msg = 3607eaa1db2f696b93d573f67f0359422101cc6ceb526a5ec87b249e5b791ac4df488f4832eb00c6ec94bb52b7dd9d953a9c3ced3fb7171d28c42f81fd9998cd7d35c7030975381e54e071a37eb41d3e419fe93576d141e36a980089db54ebbf3a3ebf8a076daf8e57ce4484d7f7d234e1f6d658da5103a6e1d6ae9641ecac79
+Qx = 1184b27a48e223891cbd1f4a0255747d078f82768157e5adcc8e78355a2ff17d8363dfa39bcdb48e2fae759ea3bd6a8909ce1b2e7c20653915b7cd7b94d8f110349
+Qy = 03bd6e273ee4278743f1bb71ff7aefe1f2c52954d674c96f268f3985e69727f22adbe31e0dbe01da91e3e6d19baf8efa4dcb4d1cacd06a8efe1b617bd681839e6b9
+R = 04c1d88d03878f967133eb56714945d3c89c3200fad08bd2d3b930190246bf8d43e453643c94fdab9c646c5a11271c800d5df25c11927c000263e785251d62acd59
+S = 12e31766af5c605a1a67834702052e7e56bbd9e2381163a9bf16b579912a98bebabb70587da58bec621c1e779a8a21c193dda0785018fd58034f9a6ac3e297e3790
+Result = F (1 - Message changed)
+
+Msg = 307bfa6a2764591bc31537fcbc7275e258f158f4b7ac5cb03761aafee8ff0c58a933cd28a38fcd1a29a7c907050c273bffb249303ea0007d16c8c4aaaf145afe9cc97285d33a8bd42f566b1bea7a5ef77844e3d7c3b55132ac7407da04f1a7e85ec7f2d03b667d9c3c52ebeb1d25b392fb4aa210aff2dac00ffd1b14b0e2112f
+Qx = 1d9020b8e6717254eebe619d46dd5a9dda7ba5491a7d1b6820fba888e236fafd71179200437f4d61284fb5a3dfbada66bac3e6909ccbeee03c2b93a8bebe41a73f4
+Qy = 048a5f09174fda12704acdd8ed560695dec42864b6300a030768a0be7f09d25f82d7b126125e41417a145641937807ed8d1af7a53f5bc3fc3c57427d755dcce3e25
+R = 092df2dcb457fc7578eaacc98ffd73ade07d764e9553506f3dc958cdb3f65d37665528cb2f5f8bded0db0a57e6fa73bfad1aaf94718379d1655db4f32d4c505a785
+S = 10e0c31479c2b29dc2726fe9f75b397d9e37a17619e96bc631c62e9ece71f05b199804cc803940d43ddee41171dd7787668c7db05049dd5b63e4f63562aa700ca81
+Result = F (3 - S changed)
+
+Msg = 3629ce6137cffaf0a485594cd47049e7866fa81bb56dd66168567542c6b8fdf7dbafe693c919a7288a03f2483b09c9cd2b3f91670264672967e4542d5bb6c87e861115ff3ec2ec2e96535148623e80525abae8d71f296a4e8947b48bb64074ebb7e0c7a586f57b35da910704f44b41151ac6db350c47e81805fc6932f435a98a
+Qx = 007067d2cf7b7619b9fcff2c898246ae0950439b8bab92d809624970eda18456cb99953ce1ae45ee5d36ef02fcd5caa4d951de8581f0c21e572caad56d6dce60da3
+Qy = 1913c59007a309005f226b6a30122828d60b4d0390359e1977f88b5347dacf2056dd362648e8b1d6fc038a3bd3fde6f1140c740efa9075ab8b4a64b334c5cd43f09
+R = 12aa4a532c108aa3cfb1753f95ca626bb72bd96a423d727656d4ebdc3f406d6cc6c44d3718f9abae8a0b46be9b57f8fd3a540326b63d0d4a8a93165715920437787
+S = 01badaf38e16efd75915f4806f054d40abd2d11e402039bd48c832f66cbfd145e4dac93357d476b7e608d7b75a017374ae76eee86c505f2cc16eaa19075827ccd60
+Result = F (4 - Q changed)
+
+Msg = 27383a923d22292dacff105f00d0433eb719cc5fdf0d555f05a75fef392eb9a2b10aa7984ff8cfcc1425366578d138d193d735706e9689e1f2590374075c3b0143cf2a6f0d2108dcc3d6682c060e036c399774a3bc7800c7f34cba204693a42803df6592165fa19e34b6c1872ea11aa13e7a6648a4f0d56a5bf41dffd8f03aa4
+Qx = 0365388d9589c18ae608124b4cf746ff488183a912e07d26b6e867c5defb552a5a0df5a16b6342014dd1b0b6760072bcd60045d6a9a514fc74d16047c2e8765636d
+Qy = 1a5319b26fd555f2a12e557418f6aa65a3461aeaea5c0c6d8698ceaa5495eed7a7d2fed0b76e77b5be11834f36e413d5288e47231c0eb0e9007d4b042bb7a1b6014
+R = 1d9ef377063a592cf81e27815a2c20789ff9b60f7f125e618b52d90b35abdd41cd7f437cfad337953ab0314fe8e79a2f2d27fa08597d4b28313358f714a737321fb
+S = 0f01d4f150e0a174674a6a61a58a4ba781406024f6dd1b5252e04807b8a807a4ff8d52883eaa258286e506ef4b04ca890e6f81a79ed9a0cd5ed585094fea0bc5c43
+Result = P (0 )
+
+Msg = 2235705a18ad2fc1940d6f1641ef3b7019e56e1cad01aa4c6da18150d622551206dd00163e71b9c2b133f29507fdef144c6fa4a1110a30eb309b04b3f3f9d7f5d6649ec3cf9416c8145e12a0934db1e48ff14800b238a4abe1e2b95ae6984a47aba11408b5f4dbc2cba858d52d58022b66ba2721573b83d5b62f07f38c4c58da
+Qx = 0fd0cac24aeb75ca50c50a72340256b43649050e0fa155f72342877bf49c3d57ac2b51b828385ee6aea94bae38587e63390f5ef4ac5540a9e6fc6f1c1e79b524693
+Qy = 107b227bdd307efd7a8d4034f733d150c41601215e76eea2bac62ad2427dff52f75f46da3d5fe31bfaedf071d2a8bb5e3c82bf6c84ecdf89ca233c92d599d376309
+R = 1c00196aa5dcbc4c4404fa76504a5eacbc96aa66c3ba531a3a679f3fb675ce58f863e08b0d2bdeae74d96ad93a39a78ed4bb3749e26567d0ca5c48a71079925b617
+S = 0f1188eba4f0943f4003ddad6a54606c13af26014db2eb8e60534fad3dae8f07c021cea0990987f1e02dce03fe53360472c3dee3c305bb3ef4b0b53ea6625bf152a
+Result = F (2 - R changed)
+
+Msg = f1f3b286307569704538c97c680abd5bb892b421463895c74aa8e1c4a46213f21a95941b8629af8117c2a00cbb71f44d79917357d529e486d8d5b8640f809960973fe9e28b34c6e4082f3b3b0689fd44d3afe5b71bf4349d32b7d80ef5e22d58f19a138e1b676addf384b3e54795c6cee53264f883d080630bf48f498761e6aa
+Qx = 104a96beea09d88ea6789a9925880c8a9ece8d764be931675640c1bf847ac8e7a8b14f408ba6722c2bf6295db9132d6ad2fe287fa6e6855f7c58ed238148a896944
+Qy = 1b5e8e643fae552261427ea7d521f380adf605579462315c75e9203203ebdc9ee33dd7ba885b6cccccbd2327462988223c4b31485311c935a341ee87ba1ee820ce0
+R = 0ba2c57827baae684d2c637590275c782a6db263a5358c8e1a08b5460ca3cf0f5ff8d4119a6b0d55fc68a75c793098e0a5622a0b4e2fcb0f17943440138d751797b
+S = 1594beb73b2ebb7c573ff07b5c43e722dc05979df0eef53587e9fe06a920f61d2efcc7671e6cb875df4e4d92cd4d37cc3eadcb9b6aee8f2097790ce24d6dcda8706
+Result = F (4 - Q changed)
+
+Msg = b6fd672065774d5c252a6a596d0373b898465af6778c7219011db482fd94a4e260df7fb7bd3703da7293e96e5324c12f5b8e1cd2c27dc3062007b6ea08e1fcc819ca099033eeb0a88ae28fe49be330a1b727d49fbff8f497edb45b8e0fa1553c33e26ff9b4c35b729b85a6e98654ec3f46a2089b6f863033498e1e4aac3690f9
+Qx = 10d587aa82a4d8e690672c00e3fd71826d892862d14dc4fbad4935aaab86924dc7ee6f7fd3e2bbe86a8652589448494dab83d363d1d623cbae59f6c2670706a0576
+Qy = 1a9734c99b6ff21267050738937c30971d0f6fe07e29794748a5017ea1036c975c9a52e6d3739ca0e8d70e784529cc1a7437aac5d75c69121b69020a95356137f1d
+R = 188dcb840dfc573a97117009226d58dbb930ba8ec848931786abc770611f3519c8ba73cceb5b489170805bcf04974672fe66c908ba379aca99fa67fec81a994c2d1
+S = 00b1a185512dc6a65e454ea2bdb8049ef8f012a53ae87b759fb5d9edba51ea32e254e80545a99eb4b7c58af96b7c433535fa3f009cc644b1c97666d88355af9fc19
+Result = P (0 )
+
+Msg = 297660ae8a7038969a7f0838cd95ed1885bd20c5a69a24f5fc8a63918c2167868ade4e372390b0c5ff198315ca1ef947d9c85036e38ba1277f1e6146723bd8f9ad1db6de80dce053c4c9e4597630a02dc514683310d3792a4831df7e8fcc77298f2a2fc4c071412219482a6e218c916719c613cd249a336f823632aeccff486f
+Qx = 182c957a62e2e27aa28acee2e2f7b1ed6aef81c68001d2648da47d2b621e8b8bd18d991cd1e3fb9afb84f639fbed1050584428cd2a1d50f877532ffdefdd4e6f7ba
+Qy = 05fadeef58cc0d79362b599e94636f9c70e3e5580c085b7ea52a5fd24fe4a892120b8f28ba53ec249c42d6d3b36268b8ca8464e54b72d37327d7504d9b7ce534d95
+R = 1e3a78e973fef6b6de8a0356401e89f435ae5f49c0173f073c4dbb9c91463e420f5265eade8305f11d30fa8d97e5b4c5ab33975f73385aea81fbdde2f7ddf7fdf16
+S = 0efeca10b5362e05a8f2e3df6661d0d536b32ca1e0a62515df2d94eb314aadb5eb40468483e24b16efe85c503d6c231ef860aabe674b72ed1ddd93853338e5e4e50
+Result = F (3 - S changed)
+
+Msg = 5d058ae533538ad5f6122e8cc4f5c6dbba56c9b9e49d7eac506874683b7b20093552db5ccd2d819ad554eadedb9b2cf613b73429723caa9f21b9fdff20d575f17b02bbedaa9e2c6b788ed90e239d9def9d108df3cc596fc5e975c59f1d78b9be3fa41c4fe86d1dcaa2d4876c494e14bc167736fef07563d2db0506b24da891d1
+Qx = 09911b41f9af525c874e05bfdf050331bf830296911bcb18eec16275027d63fa106c8989b07921c7e58b02711b5b5880cc4e6d9174e0d31060548cf643bf7ed4f0c
+Qy = 184fc0fac3c2c80c69c1c0293f4e5e22fa08c267b1f36ac5ad6dfdf4da1754f7942f48cb56f56cba05e22b91508fe4db3703066e8f697aca56f974f3fe530c9640c
+R = 17b8a22fd8f73112310867909f234fad6aa82999c28ea5a2e74b4b4bc79b2f89008b4d361ef7e797c7656f7d9317eff3e5a4982799b8cc0db82618bd2aa3959f617
+S = 1edacc6d1c0004b2090d2025d615de1fd53a96e826a3930c7cafaf3c87f34b2583997534cfa127485600a7ae04e6af4a2e98c77fd04507195e520e80014aa982a3c
+Result = F (1 - Message changed)
+
+Msg = c805a07a01e3806dc81454ee64b3afb33f302dbf65062c1c31169bb501fff4c4a1905729a4d0ff463f2349fd74596b7d51414419e3c92767ebc9db52dae4df2a83cee45486dc1296c6422000699c72137178ffd666d2f1d1a105972bef6eef74e704d8c815bea269512a32fb1b8dd82174e04b2d0d5beaa0401284a7e2bfaca5
+Qx = 06da3b694e3123ef96b3fd2ab964f85a36110590720dc1724a5d50d3050498957211c6a1535032cf1f31240bfab967cc0cf3b442c35a1bfa3e72470df1863d2593a
+Qy = 17d0a5dc460c85d0365c7bdc2e9300e276b8aa97368af9972744f4422442afc601ecfe7903a33b0354c901c7b61f29d2d3c5610192cd188291c5651754b385b87a8
+R = 1f9cb1f4e2e65282a929acd8b685ab34da176f5c73bcb374fd1b09bc995385ce3902d6c5496b02916fd5a28f6f8bb662828a76aa0ad14b01bc24a63b328c7bb949b
+S = 01d6b3a2f34e3b7bf63d06b11ace172ca61ac5a911a4b408d766eb586c9ab820d42f555e546d892643e12a6752465427c213e3839e4f8cb3a7e4fd83642843e8544
+Result = F (1 - Message changed)
+
+Msg = 05f1b975f4f446a1b8aef50dfca608b03574a83a7c78d5c2efe1660a034994917455b9c8a774ae381cbfdfff162d36b9a17bbc6ddef34517cf8fa54bb6901f42def4b787a83d3285eaf04621c58267ae6d2bdf20b3bb4cb6c4bd8ee5105eb3f049c44df4cca39f6015a3d316f08af97eda47f92a53600cb2304a2724e40a9361
+Qx = 0b7e03f0d623a0998add5360dfb0bfe836fcb0a46b0d6f697ba6b3766bd8698ac8c7af62f50511c6aa5e613f4a99fa28f70b220ba1cddb22482be74c969953ae6e5
+Qy = 0d4ee40ee4441dc85356760f87ba32e2e7c269a2e53a2e8425d5ff02f5e4fe8d65cefe20e162c3915d2eb9ad1354bd28595a86dbdc94a5d40c5b44b1e3aa3965455
+R = 1fcba4781de6506f7c3f26521f0e036b5225f651e69e115d6784b2176a666edf69d759627468400a73a136f599fb8db4643fcc16bdeeef6384a1875e1c81c36b962
+S = 0a21cfaa7e1ee0eff7efc3d7e936378500283b00687363070974483ad474c58c6b55b77f678d78e7cb44d9745f79394659bdd26b72663608384b5ae9cac1c888d13
+Result = F (2 - R changed)
+
+Msg = 3a8d8066c0bfc287e1434c2430261110e33d0ebf69d35b65b0a2d70763c7fec993decf883174f216a6c0ff622ef777c078cae5c6724f9a020f8ec07041dfcca3689a8abcce10efae0a2da949b87459586fd012805c54f0807d927d0b64595c6b18705b49d497cc2ee8b867f9e58b1382e25065500d1d7442944283346657a835
+Qx = 01bb7c623fde41beec7ddfb96f65848c2f52b50b39576bf06de6ccf157b8ec49889528728480928236300447da7171f58c8f0e0ba8fd3e2cf378b88619aa6c1e0bc
+Qy = 1f8b20a1a7df319bf78c2cee03581a1ffe8ca5107fbfd40760fbd5ef5247e2df1092d5caf504a9ee653ded2995f0cdd841d6af29c9f720770056ebbc128705f68e6
+R = 000db4c31f316912295c5b9506aabc24b0b2dc2b2358e6b023148889d9200bcf44762e88575e359b4868b2d93ba7bdb24800b09fc22eade0744b9832b71ee784e9c
+S = 18c84437fac7cd82099a2a4230084ac27ec7ea9c92e1c9d9a71290df9b37dc881f9ba59ed331c22dca4b2cbb837cd916e0a78398d2b7aaf8e88f113a942beac48c0
+Result = F (4 - Q changed)
+
+[K-163,SHA-1]
+
+Msg = afd1324e877bd73ddc2ea040fa6fe0e70f10837c4d41ffe67b2f4f3a7bc41d24dc90c159ecd28b401cca36e9b9c31ec0f2ce09471d8dab50273cd7a4cea721455ea4318131e4c55396a089f4280a2bef234005d775046929c6ff784caaedb5559dca9e6f1800ce61fc2399dfd0fe71f49c9668d71cfd942b85dd59ec94ab543e
+Qx = 33ecd8f31b2a4528692e8d6a64da3b1c4a5bd03a0
+Qy = 2b0357df509db56d5b58d9de7968e5b44a822e311
+R = 2fb6f4f62727870a1b2cfe3d7405aa2f4a1882718
+S = 3d70d8106ca04c2c2a3ecb4f36df1756b7b685f39
+Result = P (0 )
+
+Msg = 942ce31971ff206f3457bc318819eb8c0855b3114fa08da1f8957919db02d477ee7f85f2c95377ac085ece0e8cdd1d0ea6a2c53e72c2ce1b7aa17d22687e08fbad96119450d837c324a3ab9408831b5bfcd73da2cb95687bca3438d364d5db7bca248f7ef99377925a300e02c6838412a398757b29f0da0531cfc549222b131f
+Qx = 069b337f2903942473650163a3469dc40171f9f26
+Qy = 3ab5150bf75fe1f74fa7da7185d402c59f1dcdf86
+R = 052491b94083f675d9f809045cd15a8ee03c51591
+S = 22ebf942ac6d825bc35de8528c7f7280e120670e2
+Result = F (2 - R changed)
+
+Msg = 21d738272430edb754051e653a636c9594418f993b5dd9d2eca795c5b542b59e485f8791d1ed4a0d0c78209e7e4301a532141295a7ac4d496153fd7dd0ac89482392b44cd6e945f8ff8483e633c4ad08aa3b9b5d7b2c4b1214176e65c78483656bf6c86099d569e41cc05ce1951e5d6ebf5e1ab4873f2f6139a41183d3faecbf
+Qx = 1fd28958ccdbe15f3e8b06382cdfeb84b6da216ba
+Qy = 785dc6495e81807d4ed785d5d75fc665a786200b5
+R = 35c1803549f650a4e6f70b8842cb4bef2cb738869
+S = 3f5de8ff3886e3fd55fa4b252f4f8635ae50f5f5d
+Result = F (2 - R changed)
+
+Msg = ae3130f431692a4085cccd79ed6d29d5d78cc82f14b63ec6b3b4320795bd5c83b60837e3c8c30e5afb3b1cd0f41530654d3f3a23fd80af9bf0b159b256e28e39f7599209ea0a6591b066bc72c5e65ea1639ba72ad7f4b111cfab892edc1ced5b33cfb829fb5e8e13bb4dbf6ef5558c0c28712d1f4807e49b496287d438e1ac61
+Qx = 22bac9a38527a690277d91a2ba53725bed24d950e
+Qy = 5286c5817107e55030776f8284bc0dface6285b8d
+R = 2a8f5a6f33f2540a82313ce64a0b981e3cecf7fa9
+S = 377efdd4acb1bdbec7b5415c3d43b6b1c244e53da
+Result = F (3 - S changed)
+
+Msg = 51bcd47c27cc88f8b246858c9214808dfe37544d6cadf5928fb0c7f4c47240e6a2868ba42dbafb4a0d55ee5bab5d607c87c735507a3a0ff2f8a8f528eb31466130ba1b5841ff7f16309db52734a672c2adf2e9fcdc3c30cdf3f5d32d3b5edfc39b77b8dc5ee7215e93ce602fba0f66e38004b6b5520a2372a24d886a50547078
+Qx = 744a92bfeebb7f0f9b530f53c15bb3a8a4b3242c3
+Qy = 0e8cdffeafc748813d57cf69f5d6b42f81988b154
+R = 0ffd0a6e8fc7e7b30fbbad722f7fd142918ee8223
+S = 1400a45137e9b02f1a486879af01d8545112d4f83
+Result = F (1 - Message changed)
+
+Msg = e312a2a8fdaad5d479f089a52ad8bc02b3d32f3013926d74a37c5eb34545903a3add5820b3bf48b9113ddf0f3f4f87b49dd024d577d4e6e4b26a28453852bf11cd745cbbd0fe6e916e356db0e7dc8beff237c4bb96cf2ded9b589b78bc63e7a70b213081bc77badc7bcc4f59b005dd7da9088e64b8c3ffda4569cfb21ccd5204
+Qx = 435c2680e772064b7570968c3f1b1bd4888145db8
+Qy = 1e28987868629a95ac57c15da77244a69c8206c53
+R = 3ef0b18adda1096a48fdb0534f0fa8bdffb414857
+S = 2e4f1cf52e815ea1aa15be254122754b57de3691a
+Result = P (0 )
+
+Msg = 772cb7a6f0ffef1dee9443b12f32d33294a760c08191c5998b24db84ffb743bb59d25b2e28175b587711879896fa55ce04f6403519b5c95869523a41fe13170a010477195ae142581b20667ce5dffac8e18718dae26bbdfac947258473f7ea21998046e0b7bf15e93e9db2f957f9e6e3639eb01a4fd974c527e19f531fbe9f60
+Qx = 3b8a2cf0c4b7a687b883269b4e85e33dc1f3f882e
+Qy = 07f13021145c0322fe9138822d508af71ce7795d9
+R = 1663e57ce8894055e34b7636b9b1db78c7d8ee2ad
+S = 175b29bcea846f76158a08de0af1853944cde6cb1
+Result = P (0 )
+
+Msg = 5fc741ed0e37cef6b62431fb093d0c666ac21b18475f66b8f5859e4dacd7b60956211fdb7f73ebdaaf76894d7c5108a62d8585a333f8e08ce50a7a7cb3a4a550382ea929437c4f17793ecb3b8c929c40f6161ebdb8a2e9a4d87acfa5588dd3b962c3935a58c345369ab9765e96cc0e8ade83408548ce61ecadab589928492414
+Qx = 4586228a5ed3055d55ad404dc0d791df3c37999f1
+Qy = 1240f103233bd427c451b800b19f63c0c7034701e
+R = 36e351e409ff0327d25f908f6a03db2f697309398
+S = 03a85a06e0af615d71da81fef5617cdd264847950
+Result = F (2 - R changed)
+
+Msg = 242f0429356ef141d85b0f73cf873022d641d08475a33c5725bd5a44ad0cbbbee0e44f004c11b72bef82b24be321c820c01e866b34da3c6d56bce8edb77f273795b3f6abcb955f22893840809cf11f5b38e5c8b19a678c2b0c7d1e374201af16789b101426807e82c5b55ef1f40684fdccee5ddf2d00e1c63f3094d30710d3db
+Qx = 060c3f73534694117c03966d6bf097ee5e722a3c6
+Qy = 3f5dcaa44046de8df154d2795746a62472aa42f42
+R = 22da77d2f4be01abeff507718733d5583a3a7e192
+S = 3d3def91382a4d46297491af9392f87c04edfe25f
+Result = F (4 - Q changed)
+
+Msg = 05ab88f92bc9b072caccbab9ca80f68068d82d6887b5cbc6861b6c723e6a0297d360568fdf85be6880936a6f53b16d2b0dd0fd3c9e9a4984db5e61fb6ba58278b124c2c776a89e46d514c33d07a7d5a9dddcaaf0dd10caf93835a830988e14105c5528cdbfe7f7bbaffbedd9a7c06f954af4018cfa1d10fa92e3297cc23f68e1
+Qx = 57df1aaeb1dc9ca7cc707e84f46493bb2135a7d98
+Qy = 20733ea8b0d04d1ca4c1ba761754d41c93a8658d9
+R = 3cb4180d4daab23e9e3aa9dd2c6e99c9e458f287b
+S = 335c68e4610b99eebaf07d345722610f9852b0937
+Result = F (4 - Q changed)
+
+Msg = c078a5206f05c77a4d50639ead4d1807940ddcfb368d7f1a777ec11f3d0b5e3fb9799dff84f2b410a04b2d2f61226ddf3af6b6afdedcc26bb1a328749fda490d0cc220bc55be469e9add1a89a2d868d4562c2463ecad9cf1d7fb3d5e2555d2a6139d55c72bf5fdb0f5d4b1fede8be926badb3ac4c856bd3b5c21b41beea3eaee
+Qx = 36482240ddba3a04f37849aa4c38739c518e028ec
+Qy = 5afb2c63e69ec1a19997d40f7d8175be66c861297
+R = 156d9f733038c102403c24c293e02f0009246886f
+S = 1c5da656f92db88e55fbd3cef4fd7bd444d1295f5
+Result = F (3 - S changed)
+
+Msg = 8adae1bb09497a760ef3bafe7e391fb22334293279795ec5eafd183f1f706d352cb16d4bb33fae3863717aa2ee21b4eaf44a1f105480f68453552a70713c834765e82c08df24f52d95517b0a54886b2b7fd562f2e88b7ca94824f95e2c6c1c8aba04d21110514c8b09c9810f5a70f7e3e3a363fcfce0d53f4aef58c69c3875ed
+Qx = 2145ec8e43939c61981373f3013366496e2106327
+Qy = 2eb7ebc4fe2f3b44566d898e382c24c2bcd562158
+R = 034d815677a1f1b1aa55578ee3a753f1ba858f9e8
+S = 3562df0654fe5ceae7d1b03ce2f0c090c0051c3d8
+Result = F (3 - S changed)
+
+Msg = ae6f29decf1d8225630b0e347e1db6c5ce25fbd3e1b107746f1bd8b781e12154fd257a1b26e70c19def8691b7cd47b293b7c9bc386f6aef9243c897ea16a07b9d753e380565fb1959f05284c1c61adcecc5c199a8be1655719f1a453c1b46251df71c36faec50ccf49cd3bab0121dba3c1c6572d7686a47653ec5d4fe92dd031
+Qx = 3265f508cb6d87f452d52556412c55d7bbca908aa
+Qy = 56be50cfc347e781416416b3c137c454da4b964da
+R = 3f38b03aabcacc98411567f95c4c667def55c5ec5
+S = 32697f804c727370a1e987f5f15ed4040c4b83422
+Result = F (1 - Message changed)
+
+Msg = ad955ef0396a43b669c68a16b4342e53a4dfba0d397a0d0c121d0721bf252d3298f0d67630569ba8a1c34369578871ed9619d41f76f5fc6ca835411033c4bbfeb86076fac388aa5dfcbad5969ae043df6110dbdd7a33cb3f3188097cf5e11865aafe290e17a8d917c67967d7341f844e7455a9f8274122a8a63a111ba5ded82a
+Qx = 270041e1508accb9d60f65db7f29eab0eda63829a
+Qy = 5a958fa9effb8e43cbf35362f8de75c51554a4720
+R = 3b130fe34005c325bd44f7b86e2e2c9726be1f891
+S = 3ebaf6b82f4a2a47f6b10f78bd4d9d41a3b88419c
+Result = F (1 - Message changed)
+
+Msg = 8d7ad83308772c591c5b577973e99bca4499a853359a1d8d038df2b9a45e127eb9c244138dbe9819e3f95553ea96201ee2c5898ccd4d3f2453624ed86a2e5e628dd14e2b87035dbde2255223a396f2cff880dcc7d8482e96b9d50db8a5a35e408d0ee72c729ee7f94dcb9eee3c63dc4a237d9f51138fe149d5f9fb56e093f182
+Qx = 29c26b6986e2f1225bce07a38bb741d07b63830f3
+Qy = 771785d4e32db0c7f0863ea33ae3a00c929e7cc29
+R = 077a788d8dd97ba121d9e319f5a2359808fafa1af
+S = 009d2516b35705c81f0c80228e2e02f6d936f3f92
+Result = F (4 - Q changed)
+
+[K-163,SHA-224]
+
+Msg = f7016b4da0406dfea655d178eff155caba0a1d93863fc8ea24462f8167b42809c638f892cab5c1b6a1626ca9c684f100d16d4d9b0d6fd90a43dafdf8b6be6c793e724c05174159be24f0426556df1f71591561222813013a175fd713dccda1ecf7f39d5efd45aca860351a38b6f07bb41b1fcacb2548539c2072a54f7747722d
+Qx = 389d925968c5e0639e8dab9279ba863a70df5a5ef
+Qy = 63eae5a665406ed191f6df15265fec0e455e2e9c1
+R = 0f755617aa6e4cb39ffaad147818e26d119ec2fac
+S = 0f3d0d8acb53e9b2e66613c4c2c130a777190045a
+Result = F (2 - R changed)
+
+Msg = d59e1347ef158a812fb3a9536d42fcd4724c04ef0e80882d57fc9f7b7de32fad8c1289e777ac7849170c02790463aeeea6e5fd6722313fbef75ae3369f792308bb59ba6d13cbdf73b383c12636d52fd9cccb9e5c6890f55ef54a9c865f590517d9db6bbd7173b738a4b940e8a10600a664aae475389a614bbd78ac68c9220bdd
+Qx = 661068be45f1a1a75438166ba0f30fc5d76934dd6
+Qy = 59f5a42a66ecc94fd49879303ec1112ce84e33751
+R = 30929f68bf34a94708ef376369b8694573e70dfc7
+S = 0ad9cfb7ef1b1d934d7597416b115c2ee824e8a3b
+Result = F (3 - S changed)
+
+Msg = 7ef2cb3a222802edf3b0f60ff935519637dc5cc62db543720258f1df899b0ae09259a3bdf25586c8d58d0155f48652905f40bd1a5247810aac31faf93cacb6dc2a3bd12dbe1569745dcb2d20a1fda543bd537ce89980b2e028a76e349a8f45206d76e50316859317c70f1980377297d1d158a64c22f782d46cd99ef3bc7f2a1b
+Qx = 7f86b09c9cb2e80f041c9e1bd86b0875aaeb42ac0
+Qy = 56894d29d17aa768be48f18763cf368ea0b037d51
+R = 0df81ccb48127291a200e0c35d79556d0e6c4cea6
+S = 133008d83f5194a2b3471a9faf22a8b5a77c0dd49
+Result = F (1 - Message changed)
+
+Msg = 674e8d46d4a31422dd81d3abd5014b2b8bc22a28ba76359f451a8c39d7201b2a050a92ad03367d0bd3aa634e0518889c8992aa898e0972dad4a0330f452fa2de02fa8c42352b9b26c751ad581e9d3ab242aa2fbd5c2f69880b8ca6ff5ad1e5838f30921d2e5af95bb83cfc2c4389df9430ae74a63bc55e3b615679741dd26d17
+Qx = 64387465794698b5ad84b471e1cbeb3caf113f1b3
+Qy = 5c1b044af75cfcddc45b17995ef79b2817adc1110
+R = 3ea2871e2637896b6b9915eb672783f601f983034
+S = 26787ce8489b5801de588f7b85a5d30db6a8810f4
+Result = F (4 - Q changed)
+
+Msg = 3d588d6f8f77426f6f3130a35afe8b95a77273e46023ab6ac5608b2d80193e172b3451ae291d16f1b8283ab9465effd09ba1c7fcf00b2c996f1068e899ce2b2c14c1bf282a414bc97f7dd38324f2323ca0c28724bef5dcb17fee6579e0e4093205b5469c2af1839898128c652b1c94d66a9184aa2b2eb05ca53846c7655eb405
+Qx = 5f03c98efd07658828a75f29af95bb883225cd170
+Qy = 0dcba47bab292ad7eeaead11c0f735286a2c407e3
+R = 13fcc1956656db068fbf704715d4a1aa59eea69b3
+S = 38c722438a767507d10759dc4934f87e3ce25adc1
+Result = P (0 )
+
+Msg = 52598c2e846c91079682d4d9641a88cbc78eb73569d42b5a6c20a731405b7d07c0121fc690b080d7b472181a05cc700cc3e39134b4364c777bc5aebc459ece4b8a3e5c1ab16c7df63a166353f7e4b21981d817b5db7b8b0986aa84a14c62da6fd1121e0660246f221b5c63577c30d1a2fb5c2a5a5f61fe67ec19214e7c89eca8
+Qx = 45dfa6274d726ff9e627d04114aea124e14f99a6d
+Qy = 6cc4862f41c7bf92e4ec4af2d22ad1763063c949f
+R = 19ba121e1357845d9c9c6e8c7c975d32aa69f7e28
+S = 0cfa06e312b55fd472ec964e093442d524ed7db6e
+Result = F (1 - Message changed)
+
+Msg = 75a06692365571f5f49de3269fa6543de398c56a1bbddb510e575eab0c627e9a3cc62502581d1807ed034a2c614ba89a5461737b6975ddfcf6fe262ee8ab5162bb0d16db15e4bad302eadd409d1cd4e2a317f92197ea661581ecf7d8d99ec88221a8ec25db8304d98fc5da6f1f7b30043d27f05e6c00be372c84efa167883111
+Qx = 5e67dca24ba1aaf5303ea9701126a4acb42c06504
+Qy = 6d177af939825ea6607e96a7cba4e3ce6db0c9f6b
+R = 233c79dd1f6a65381f9cadf4b55e080c1ddd4b705
+S = 0eda18a0564e7688bace40e0240cf5b2ec3a83cf7
+Result = F (3 - S changed)
+
+Msg = 1bf6f143eeba2b482068ba04ddebee3ef10209ae115f4da5c7d7b25a7a60153583b14c314936525d326918093710dca5e85776d00fa7f20097ec64324c5305b3c37bc4e48d9f6f772bf2294cb1a6fc5f902fc3379c901cb4da39553e0241ad4a5672d13838f2a1e23c2b1d533598f54b59fc7e0994e4b887f6a912c57dbe1290
+Qx = 1be8cc969defa342904ff0cab3c54700ebf694ca6
+Qy = 4b451c3ba78e6586cbfcb8883c00d28c22f6e0260
+R = 2926f26156775b2140e7aa052e2680b58e3b57a6b
+S = 0802fd3ad812b310f6a93d633552264f881a97fc5
+Result = F (1 - Message changed)
+
+Msg = b785b24defd0deb0e930adb3b0895ee1223f07d192bbe17d218c2616768bb0ff31272726c34a61e1e0806e06cbc2b9d48d7cc448b5383412bff35684007b6a2200d508703fbb25cfe0867e28e87ff3b67ee52d822f29cd02f7e1a91883d89c4e030475cb8af24a77331935dd6fdd94337ec19f5cd0ef834dc162d2cf5c2c6071
+Qx = 344ac6fa6b95ba7fa60ca01b7d5042aebe06f01f7
+Qy = 13d126306a362273950013bcf3a60488bec0a1b65
+R = 2c3c99d6687f1ab76ca328ef1321e124ab334c964
+S = 15d225e1d5e0088be34157d2e80a98225beab93b8
+Result = F (2 - R changed)
+
+Msg = 33e794e2a7e2f35964f33785114cd8d42a1ba14e4679b24075fe19486cd7557d66f42bb3df7b796fbd06a707c314bca8e7ca9395ffc2e2365f49af37b91a210fa12ffaba439c141d377666846c2e3550a55e451115716e73f51f8f1a38eb41cd4732be4ede7347b9a6ef21540808b3518167ee1472d1d02f40918daa113a2263
+Qx = 0fd2e532f7f851015d247fae7f10a9dbd05f10acc
+Qy = 200d90f1dc0b169b0b32c396edc3d88cfeed6ae65
+R = 3afd056542cb8c09b299f2907ed585c3bf1abbc70
+S = 17ff99a79ab2067e9d310f8654594d970575ee1f7
+Result = F (4 - Q changed)
+
+Msg = adb4b70986d9c06b4f877ac58767b2a3d7b01043edd5d079bfb81a683fe3fe8d64730f3fcfc66eaa35435af12d079e4e34643653c250d946708bd3a0284673b4d36146c7dddec1831baf99d6551a744dd92f6b2f0a1796479445c62ed5b8f8d0fe6c229245947219ba18370abb7b551b28bdd350cde6ec2a494a8fed4e768291
+Qx = 015f996e2abf0eb884bb1dc1590fd4b64f2b249f5
+Qy = 5a02183c0e81d8f3230877f2066b3f324387408cd
+R = 0798a8dad7d304b438c6be33cfec68fce140452a9
+S = 3ef7e9c9a5479661e13475ef66cc888853cb6320d
+Result = F (4 - Q changed)
+
+Msg = 98f582b03c3be722f4657ff7d980afb96166a5066a8815d847b16daf4f4782060ca2d8133b48f25aa156f58656dc6553632354eba5f820c624d9f7b79622902e7bd452936857d5e72651e0dfbb9c26235c291be8cfa776d496f34460652de6bd2c7e7cac910f6c2bf912811da9d6972602d68578803f7a35f1e073b4f469dfa6
+Qx = 3c88480805470eb5065cf518a538ad882042c4fef
+Qy = 0209eb73b2e564c8c98754d7967095dd55e4d4d14
+R = 0879065c3b64627773f205fb9d729f079361ec3b5
+S = 1e0d4525675fb72764de61b7504a15da8905086aa
+Result = F (3 - S changed)
+
+Msg = 08d665b9ca15fbaa2047768574bb92d063ed7ca0e762cb05986b491657b686183724799f5576f05d160e548a23b4c84117fc7e449a7765061f7389c2e0522da0d83b1f12468f915ba25e542adf146a41b6b78fba76029bf586930e2aa4ccbe39def58d3087ff1df1ab0b3868f34367ef0c36d38be2ad37266965724ca1ddcc09
+Qx = 61252855af1ab96ddaced6635943de206df770ba9
+Qy = 1b0064bf2577a5fe4655b6c1e8efa0bf8de2e4fc0
+R = 04e0bd3cbca1d6b28f22d4abb96c597e512e990e7
+S = 1cc9ec2532784feb9f13f5f93f7699a3f003b4d51
+Result = P (0 )
+
+Msg = 28401498d7d6a75b8d0eca8fa35d7d6dd344162641c2fe13a0e611a182c772f7e440cdf63a2b268671bcebd41af1c985a5d67ee4aefd0fc26b10969f35c3b6b10657eed6b9d57325bb034ea261869452a9da95c511890455f7e3db3489990656270e613428283f24a4384ee3127f886c9f1bd047aac507f09439c089f3aab8b1
+Qx = 3484bacf926b4a5bd516a8374801695391596352d
+Qy = 352a0c71c5becef3241009b1831f5ada798cb6e9d
+R = 3375751da88e19aa3d26a862624f171d81e9bd75f
+S = 065180010508bde92f5c159f12222f26ca702b344
+Result = F (2 - R changed)
+
+Msg = e883c9144b93e272ec14c223d155e46459a228a8f10f37c4c8476d4fdad2d453e092aaf4ba4b2e4ad405c7d7f86a7a89ea62003ce0c1ce13c6b0cc05d051e188d7249eac9f43838608e12073744759cbcb342b72b5bac10872de5ad9ef0b2fd9a42fa44e79779c953e1e512bc4269d9a922faf1e46edc4359079a87974a79380
+Qx = 60ec9dfb7e73c267e7b3054bf0cb4962f92982ea5
+Qy = 7de7decea83f84ab1fcf080bb241023fec0edd8be
+R = 0e3a24abc77c7bacd339fe1669914c49e896f0d42
+S = 2dd55657948233e84c4aa6c6d351b3589455894d6
+Result = P (0 )
+
+[K-163,SHA-256]
+
+Msg = 36c6b824012460b73d9a1cce453eae5505d952d34f28e2490a8f082e5d6f445f8aec031e15edda57c0b364b248cdf84b2043c4845e2e81ae09486ebebfade2850628d36e04f52077b2cd0746914aa8b7216df1e9a9342f59b4ed2157fe7a812187defa456a3d64c47e42d6bdb9844616a1b3a15bbdfb8828622e39ca0aab7610
+Qx = 76c3013015e54a355f44f119dc69ff79a6220ea24
+Qy = 43312e3dd36371e6e6028d29654c5050829532643
+R = 123cd916b9d0e681d2589b4f69dd158fc763b3cbd
+S = 34eddf7c7b19a5fd1b90f421de1094f1afd5932fc
+Result = F (3 - S changed)
+
+Msg = 480b24b8d46a7b023516b37b302df8c5f113a13844cc146f3f4a78e102a1a1d475554224efb2577ccc073e64ea2288ce31ab230a0faae0ad0819d2d007b7b4607018f5a486274162c30b0a0a581ae798cbbe46eb38b78a8096b70e20e844ef74de37466c2f9d7e30c9397e692ddcc78373b28b25b945e91a6cdbe218ce94b5f6
+Qx = 09e59b792cbf290b1a5558eb2bff0d050cdc94e55
+Qy = 23e83acee2ce8cadfba7d558b09bb60b8df01bf6d
+R = 23f53c4eeb57843ff82f3d087081f7c858de51c34
+S = 3afaf8b91edd1900e57dae40afe1414a78e8c0a1a
+Result = F (4 - Q changed)
+
+Msg = e1ffa02b8359a049765196823c140a82defec326ddaff88fd9e47189e8734c086de84b8335b6a655a26a4a6185f8aee426e458e22c4d3caf3127f64ae9a2ad2181c7dd3b9dd9adc29c2624ccc32e0ea441f6524b915f03d736f4be65b268d5bf3c409937c0ad6087d951701c7867d2585a2b9c3d4fb149041e1ef12f534d61f8
+Qx = 33fef189d89620780b3b7d093ae2ed9075c4339bc
+Qy = 49b4a6acb23f0e8ef899982d6cc7438521761a07a
+R = 22466c273a29100b1916d0f2968e8434df20839db
+S = 1920f30c82972b8de69589bb231fd793cd52f154a
+Result = F (2 - R changed)
+
+Msg = 2a4d77289ed9184fe22833aa6716073cec9278dc373b558d857241335ccbd617eb1d6db7a9682bd132f2ed8a27b44f5f2d0d5f41f7dfc86bcd5e02607d2c3e23056b8b4acc430fa91cdfe9ff5bd8bed0c64b6197752e759746086fbcf6f5997bbaae221ea66008721c66abe55f9f0e6109372911f2223483132cc938ddb66c36
+Qx = 2dfcc77d88454d56f6554964046c9ab3063b5d2b1
+Qy = 50662c61f46ab6697d5aa1b9811f88a1671715f3a
+R = 143a9219f6f5f50f16c0bfe1573cdb3d5e903c491
+S = 222dc0a774dd4a81599ef8ef0d6fae11513031f85
+Result = P (0 )
+
+Msg = e75a3be7a8a7104577d72891338f5580e57ee5214f29ae43891efb6ba87055c3a3145ec11f2c790f949bb2f9f61b63e02c8237d0389af19db11b8dd2a2da46e1d4bc390a1dbab226d3a9f7fefe209a1ef152428e9c2b99361090efbb9472df76a694720497dec63f82184ad39c282354846fe2acf6068e05894dc729f044ca2f
+Qx = 373c4f4353f923c578ca2539c6552bd4aef2d92d6
+Qy = 649727c39aa3cce9cb693e4c6e416619846f511b0
+R = 222ce5b6a2a993c2f3d533e1276a11ac04baf098b
+S = 0a6cbe7929c6555d86d48eeadc62197895ed107af
+Result = F (1 - Message changed)
+
+Msg = 6113e9623c289b500bd42878aaa261905dffbddc4bbce957799561b53a42e19980187b2eac6053fe080e33ecd2171eb5f90239fb36f140c59615a97d18c13cad3e4b69885c038c0a0cbe0e3f2726fcef7204e11739b30d8b1b0d40ed44b931c6116aa1264bc631a6ebf54ff4354aa855edcad319d33500940b34943104560ee6
+Qx = 4e167afdaf35555bd5ea7df37d2368539de2f41ec
+Qy = 08008d831d6cde1753fcd52b2c901a6365c4d0d98
+R = 2a6885861ab21ab6f8c3158404b2809ccf19d6c16
+S = 16688fa011b736f10f5bd94111bfb01a30b84f43a
+Result = P (0 )
+
+Msg = d58033f8fc7d76a9a9c05c0f9df7f825d2f38fdc7f61a62f7d05b30e65d38060c08d5605aaec3867484e5f047a456c8b143f3cb6624969d2d7d8d5ecca79d3bebb8f441c8f5bf3a9530b92526f3b030171725f3665dc36d936722fb4f35f5faad6ce53995ad6c38cf2a7216afa5e0fc1f62f5bfcc002370bfe6aeba1f8b1e49d
+Qx = 5f2c87f0ed73dec394bc9cabd06bb1d559a7062f0
+Qy = 14419a9697afbf8a48be41bc39a54622d1fd7d95d
+R = 0089046a096e18e5fcf647218be706a7fd53be4a4
+S = 39868eaeb01b73e26725da43e69e45dbd809e8d2c
+Result = F (4 - Q changed)
+
+Msg = 5e29caec586d58dc9ea0e70a643f7e8fb6724e878aa892db0d7029c929ae3c3b62318448d52286b10cdad8b7295d3e1852b790093b0f370a37a402b2cbe04fbe7fd9682c3c1314ab9af82c40fae806afa83b754b523ac43429e64e8edf9bbb96b88db46608a18883d09bb18b307ea7da0edcdbb9ab6ac4dea4ebd5dce049f37d
+Qx = 7d05cd872b3bb108546a26ca46606917a01eaf645
+Qy = 52941401fd2a2d3b6bce67bed2b4187b8ac7ffd26
+R = 3661f6196bcab4e020f44f64f82d5e0e1fe57f595
+S = 2dccb91ef4621e1f9459ba3afac68cd08714c4e42
+Result = P (0 )
+
+Msg = ef3ca1be5c2a0449c09a344a7fcf9e9b335029bad56cceca72863374d9afedb3bc68f1a69d9a1a1f7b797530a47ad7a34cfa68a9601a74863224be6afb3207a9022d5a193dd9e8db7b09ca3339f32ac33490afd5807fa56aa2acfd56cf6373ac527f05b0b4641bca00776ca1f5b68e06680406d4e1e6abdf3d6d8cefb55639e1
+Qx = 1999d3daaeddad83d88af4fcf9c3daf2a846fac2b
+Qy = 627a8f8b10caf0342f3905dd35f17f6d1cfa0a0ca
+R = 1422948e7e46049ca42c0ab863db2a9ae7b17255c
+S = 1ab478155f05eaff5094a619d5992d9a53f92f095
+Result = F (1 - Message changed)
+
+Msg = a52507451cc6345b14e662f9646e26baeaadd7a115fecacf30c79b555dd53e2a0d2c5a8e0acc73a13f86ea9cbec68e373c69ea43fc39708f89e3580443ea8fa950aacb8e1a413ace79319a3553833def9deb85463b640c385b55977c206dd48aae16a94da5f7d0c9092c38c60c4ba35d32c8b554899f615d962a5c0003156ad7
+Qx = 0b2abd329b93b59673fc2062beee93c4eb5506f90
+Qy = 6ba250ef99a76fd17412b74b7f1f2c880eb9cd31e
+R = 21da9919ad92e5fd3dcb6264bf50368f5155b8e77
+S = 005d0ef885e02f1d1a56e7cf68a3e77601cda6d55
+Result = F (2 - R changed)
+
+Msg = f9ab9620bac1f529590f636609181cfa4440e2405452bf52d0537b7d7deb24ffe4084d38ecccdfc82a317e9acacaa8f3d877d96344ae2f30f26bf6eebda3ab84bd9eca7dc15726bcea74dacf225f9b08617a523feb74dbaa091cb5274d787630df01c88bd8c8f92b115c418071c6c837a1b48ef391b0cea0589aa2fbe1a88a50
+Qx = 50941fb5d8a06d7adb0247ae8f05e57d945dba82b
+Qy = 37eb54ee6256a5bbba6fee5e787eda480a194896f
+R = 0a5663b2f8f716a26eafe1355e1e2a1415ba9eade
+S = 0955643a446a1515ad474d0c89d2199302ae4af2c
+Result = F (4 - Q changed)
+
+Msg = 0eae123c5a24f1a13d5db1af1f74e8942b1666fcb324625be1135caac6dc928ab0f3bcaa336b8b82ad1ccd00871112508830cb08fe5c9dee3f1efa409ceac2fbca49d3f1c2367efcbbd5bde0d6269256c74ad0f1b2fca3a12ad78d1dcb3ab6438aeaab06147978db0297c8e2893f512aae32bf418a8764d6731b8d23c4daf034
+Qx = 30c2654fc28a5810568f7a12ab7538889a58c707f
+Qy = 12ff689203f39018b483f0c3bf2cb3f1426295f59
+R = 2ad84dcee156b8baea144caf6aefabc94a8073540
+S = 0a16cb7237714876720a5077c248dd869b325fe82
+Result = F (3 - S changed)
+
+Msg = 80bd4ffa9cd2f46479279c71e4a8960573e243d02ae955c1e2b66ec9e94aabea0752d69e1dea663bbff2e0d8ced18863bc64390a0a8343936e318374bfe86e3bcbb732fcb53a44c87cd6bcc5b8db4a3f6518963515de8fb8a31449c666ced3a1d278d6ed04d541d1055c540065e3d2e5343b661cb13555ea3a4bb5b91121d21e
+Qx = 55fec16ee93d12009cc43af62eca57ad9ff3800f1
+Qy = 0afd0adda200e0933cfeb393a6ad10b0b3b5a2244
+R = 0a0e16229fefa5589b56f4ed4f50fa99419036f02
+S = 170abf3a55ccd031f073340fcedfd4a34170357aa
+Result = F (3 - S changed)
+
+Msg = 727e77409d98682b01ffe2ef12642f36b5b0b1e4c918ad2ca613c6de40564332db6147ba58b5e29aa68715a8f25376b336eda670edd87ba5151ab42ec66c6e41824e8d59ece3586533bb4c64ea783ea40dc39d40aefc526f8cc80f97f03cc8e070f3c243c52e31d7680bfe570245d010065d25701b046f9c1192c377f638ffd1
+Qx = 5661912251b9dc51713a7965ef7262094fecc9420
+Qy = 7bca37ad53e19e128f0b372ff9491b4df55ad99a7
+R = 1b1d172d272ffd6c2e6c7681c1bb9a194c02d2125
+S = 0d542020f115c1515673f90bc2b62f7c7b9fbbb24
+Result = F (1 - Message changed)
+
+Msg = 197b71ba9a5cbbf307c5e9e59c79d6863518bf48a655a5ab55f9edba46ef2fd05fd4bacdb52ab09302b772d6983095315cbdaca16b0108b7bf8a3b6f26e0c050316034fe8b53f7885787b92c17c790f20a4445517c974bddd68fbf3819d3c39acba8c4dd0a674b48931f76c7ef586a985f780870a7b5b5d9c30deaf0b2d60386
+Qx = 7c6dd5be903fe1e45d87ce2152b0d94d9b461948b
+Qy = 1ac2b0e7ea6393256b65cb0ffe8064f091d91a454
+R = 386a0da595a1262fed828f558f462f1b757d300fd
+S = 3b1a0fab7d24535de8bb5b9c1aeaafcbbfadada29
+Result = F (2 - R changed)
+
+[K-163,SHA-384]
+
+Msg = 257dbe64f65d630b8ec48f933421ae2bba997d00cf5ade93dda9b15b14dabfc9527b06d5180f36288d281a72abca5424ad2f1f68f3115167070289f0153bf39c19ebb395cfea2c9abe3b7773ef3e813089f2bb552ca3d571ef4a3695c50c252c4a05312cf4ecb598307016171e88435004a16f56127b381ac1573f9b8d92c58e
+Qx = 47dc4ab6eb1142612bd0699f647a4992ec2b4d17c
+Qy = 25d0e38173c3988c1d96d66fcbe11ce426bcefda9
+R = 3d63cc8283d690a030c2ab11b26cac3e79360fe51
+S = 0f26893150754618bfee44920194bfcb4a9abbd95
+Result = F (4 - Q changed)
+
+Msg = 755c9edef70b85b10ce3b760a3fc6de4db5823d6c4d202adcb95fbdb3c24b0d2bdf34a36a01152e0b63d9725cec9c61fdd990df161ff21bc55dc834238082d72df5cb2127518e46cd17c63c6574e84cbded7bf769b4ee1f17e7010d535d5eb70997086f1f554ebcf5410ba41eb2f049b4ccc6e0c8a76ce065c52bfd8e968ca76
+Qx = 6bfe070e7a062b62ffd7e10abe2d5f43c6c8e9b08
+Qy = 2cb58bfb1843d7b6dba67c11bab68f922e5b1c749
+R = 27ec7a456305ebb4f04a4a12893e39b0febc45319
+S = 1f5a42fab3dd3e792b7ae03007d216725cf010334
+Result = F (4 - Q changed)
+
+Msg = beaba3c9dfdfd090ba08657e545f6fcedda8986600eb52d8dc7444a3eea868cea122e1880c56ab0a921e7033601cb5487a9e03505b0f21d0d5e21b75acb526ee19d3f1ab776e5a47fb98f819a101f02354552cb29d45749d4b8292dfb7c7876254de4b196e89e0b2ffcd96846ba91f7a06474087832559e9ebc69d529fac086e
+Qx = 023b2f02c821e2b546667cf07a2071709aa7d0362
+Qy = 04f044fe2d146362562eb9b11b540a240ac0a8d97
+R = 1d3bfe668ed2b4005490137a386313a4793e78a6f
+S = 319cd3fb0bbc434f9bc40b18bb5ba248c0a7f1974
+Result = F (1 - Message changed)
+
+Msg = 8a9bf361a8765020adc9610bce62c6f131b15b393f7e378343b72860620c516f37ebfc4d2ca4d29f8f0337e1d490e90254cbffac7ac57127db2b1f1e2ddf47e0c403c61c3820c53ef4f33cecc99f03af1eb2afd0264b27d5317c011aca828eb88c44f033f8141636d5558f9a10d957daf058ba8bf1d1a84a7c6f32f5d7fb8ffe
+Qx = 1c02f7056611078217bd9ca435acfdfa191180f75
+Qy = 1529fadf5fd94516ab1ea5c9beffa78fdf8054d6c
+R = 300939301c5103d8e670877cefbc56b0c1a54ce07
+S = 1ebb67580825e42d349acc41cbd1ff7b6310bef99
+Result = F (4 - Q changed)
+
+Msg = c7891686c0b16ef736846655e9da2b17b58ec537fff80c678287756de6b148a2dc43269bf8fa65fc3b3026f6162929bd03bc22a5359139808b0cc41684b84abb0614b5552a9f901ccf72923262fed65530696172039fb76d72d7dee9c411b5f81472dd147b16ea722ab6352a53b748d848c6829eff63751762f40f01c53fe48c
+Qx = 74373b5f8245e9c20348216556bf97620ec46f2b5
+Qy = 4ebe3ea3028f9f2493c9acba45da0214a72c6ae0b
+R = 023d05d5136f5e9d39401511f4b6bcf8bbacea1f4
+S = 38980afe51489896b05b28821124c15b7cbc5d886
+Result = F (2 - R changed)
+
+Msg = 85e8e6a6acc785b0e12fd156a3c083df9caa1b8c5d8e179524d50728c16a25db0ecafacbf8e5e7cc890d51e1b581ef363341b9b24233a73dbe000ad0262a8a710a446623c34294fe6de9351eb4503080a9dbc061862a28e9e67dcdfa0178ee153207fe900abb8ab6d4b5f09e7d3a42935c892e6313c4e84751a1bf53d1011077
+Qx = 6cc97833bfc94ac8c51086fd87592feeb72bbefa9
+Qy = 459a7abe1d4fb0595a0575c7e648b39bc72a4fa0f
+R = 3b2c8fa6f4f9ccf9ceaf24d40045e950a44cf3953
+S = 3616df75db902a7ef81614be0384edecd24c76d71
+Result = F (3 - S changed)
+
+Msg = 9594f51c8ccf9ae1247711cc6e0e3c48d949dc27ffb508450684480c1eb30462ee7a2aba309bb24571e05aa09ad0d7b8cc3b36caff77bd653e405c2c6f8485c7ffa8a94a4f63e429c83dfcad8e9b2bb2619afaf54393eae8707cf03362a8fc38bad41051ac051d09da708c848de61b4695566cd65d8934f77db8fd54d53eb60d
+Qx = 3e92362f37493ddaed8310a4912386099e65f755e
+Qy = 777925bae02fb9fc268ba3e8c8515886b428f1d70
+R = 2b6e3e8a72be128f98a80362b30d24c28ce126a26
+S = 2d1702f90a008da3e920c52a506ae01596765b9d8
+Result = P (0 )
+
+Msg = 71fb659737da12e53ae75705047e2af9c8265363f02c30359e738ee058a74e845af8c71766466e5f3abb931cd9589f22494b5394a2985da36dcf1807fc8c2bcf38fb28951aa0b97c8845d0c5f5f619df80402bcab96d23036b2b013f4d4d7fd38a8cce38e16bdbf2fa3bf87e69b8c3226477de04689745e234d67df388588e42
+Qx = 76798f8460740bbc0ff4533d714d02d561711ab7c
+Qy = 2fe9f24a5b0037bf3c57a24229a51ae5943cb858a
+R = 01b7d8cc2a5be5404d9cfde720b7fa5038efeb490
+S = 344bfb611787c025c81e9afd7d4b9075ccc142aa5
+Result = F (2 - R changed)
+
+Msg = 8f80e7bf7f3885627782b5933d753c4a9ee5be66957ad874340b4d1447c3869fadb7574a84009d164e8a0167ed08e6751193273e273aff7a43794e8b3cb5492c0aadc12193ae232f9b96bd6a2e3bda708051a6a670545f451ae614a828bea42dfa9b5d2a88de4e23a25fbbbcd0709e04f75abdbe95d5a77d201b40807b591c43
+Qx = 22b4355c5efb83fe013fb899b1a81c7ec13ff901a
+Qy = 4381e42526f0ea551d6934f9e97d57f82ff35d846
+R = 36450514a1eb31ebf43468f263ac8c52af49db738
+S = 38f37054e20a1523ccee5a9fc03bcfb5b1f286e43
+Result = F (1 - Message changed)
+
+Msg = 042f929400b07a48121da12d53fbadf7a93243bd0b4cbb3a650086e4b1ac5a361bcbe0532f5b2f5af55baf6e08840cdd07485b8da7c103e7280872150d62dae13fb7116e870bfe7de21acb8b87a82e510b3f3ece367a86236c099077601fed7b5db22dd4bab897bfd2112835cf5217709f157d4f36bf42c73ba48d1a98849ce9
+Qx = 68ec67a9c9367b4d77c44e2a7fc615ba4ee45a8d9
+Qy = 2019aa77a2cf437583f7fa8a8940fa527206498ca
+R = 2e706118aa86952b19d358e0284e24a63d2224731
+S = 0754983731e37f031a9e6c85f68e4c536b73cdaa7
+Result = P (0 )
+
+Msg = fcae4cb00544c56bf683570a257042c58f69be8176f7e76a69b12bdc8a94bf20af3c91f3f03c40b932b14007eababc539b5f29b3eeaf06f014bbaa8f7ea7c1d9b9b7e7440a6da574b26a15d8cb81a7295034bd70d4f7b598f1052c5f402f869df7f134740536433d3c9df7fe73fe9faa9cf3f8615800f4a0f6ac84fb11245fb4
+Qx = 2d9eb41717a9b6c12c5de7dacf4f5aa18a01eea55
+Qy = 6aad9a784cb7e3cc421c0943f9ae17ada6eff0108
+R = 24cf80f36ddbaf3b6c2a389f6f897f648fceea936
+S = 2b62047b422bb1ed503d890eed4e2c1fc2973f2df
+Result = F (3 - S changed)
+
+Msg = a510bdf99a2fd0900eb7efb499cd3d11f843ae524fa1d51aee32eb8cdc004212416c342549438b4a116bca8b6a98699e03f46aab7c8cb0bf5bfd1f2f11782a3f54cf8a896e522770ade076c11d3ab3a55df096fb9621bd3cac506567bcb30c40ab651a541050e363c6f8f47156ec0c058af721d63c2eb6ae8dc4a2880a5bd24d
+Qx = 3c7cf2bce87d135adafdfc7a1b62cc3d80a9be827
+Qy = 75cde5c0fb05dea17e6253175899b85a624a5ce62
+R = 0e7e0ce2fdb58fd22f68bb5a3e723874fbae40744
+S = 1a658a7bd9e4af051df49b7bb6c51f1a56292ebf2
+Result = P (0 )
+
+Msg = 46b849b8b81eb091f2682b9f5bcd736782693766da42f421c29bbeeb7ccea56494b0e5a2e767f80a3ea1b373321f939a5007701646aded0e149b728494787554b81e386bd88d7f700bbe8828f76420318c4f1bd28d6f68dda8d7686a3416128dc788db55be0da433d84fb55434a054531380a3cebdc819e9fd12500afa8bedc7
+Qx = 1ebbcb5d28be4c63b63691e90c0f7c371fb856148
+Qy = 311040edb9c5f4533c9879ac83284793be4a2d105
+R = 14d5e53655c03c12e0087b1210ce0f048383f18db
+S = 14e8c03a71daaba3acc4986617e165c9116792c0b
+Result = F (3 - S changed)
+
+Msg = 1323930ccd800ba0601c6f0f992dda11f2becda670ab93870212a4cf50bb2d5c4292a617202e713fdb3110d976ea87cfeb3c029f91bf293903916ffc7e61b475a415d158b8345ddf6dcadc57bad72bc2703b687f8a9425547781430e94794888dc2dad1250f0e3481480dcb97ed1fe0a21346050baef1b472ea4ae4b76113304
+Qx = 4a6328ebbaf25a02f641c7b07f04f6b9e48012b38
+Qy = 412342a367ea453b07fd91241d36e97535579e755
+R = 033c579b37e7ef7d1cf211bb99a510b3cb4c293a8
+S = 03ebc3d335f8b0db42f18300aec2adc0a8173a271
+Result = F (2 - R changed)
+
+Msg = 4d34443f12dde0deb503d88de4bd84b73c8ce9183ccad11e8aa223fb60e8162d60f88e3c20124b75f85cb063b6e4df98d3a32718532d74b267c4dbe28e1fbe73f388a08da477da9bae80afe7828fd35db1cd9202b7256d311e49792d142d7f576ea8c509811780621a35c9dd56397699cc6d5349586fa36867321cc9a6370eed
+Qx = 4a109cc5b8d003c8ec61582f7f9c22e9429641d18
+Qy = 04626eba91b1d5368a29a6bc9cb2815e12f080b29
+R = 029e2b1952d28cbaae039588201d0e9def5495064
+S = 2401fad0efb80cf37e452032370df42c1980fff38
+Result = F (1 - Message changed)
+
+[K-163,SHA-512]
+
+Msg = 410589d6dc79e3a1ca51c9fb84a3f1cc4c4a0d74e8d539b10e1d03aa8d0a9304ac388e7ec378cea99e93c411c79ceae8990dfcde8383fcb1dbf8612a49af0936507df3603f25fb866363e472c91a50df4b00a43803531777ecc0fed8c6be0e1b403d1647e4165f2dfe58d6deab4b9f01ad1ff429c458d9991fe3c94219d98076
+Qx = 13b710e91e2faec1d2e34a4a0a32d944531dfe2c6
+Qy = 6d2f8ddca633ca0c52c3438bdf99c18d35e66de06
+R = 254412da587080f5e911461e96256ee1477f9efe1
+S = 2f8e1cee60a2c4d6f75f8765bf20c882cdaed654b
+Result = F (3 - S changed)
+
+Msg = b87af93bb05463cbb6d61c4c696290f8ab40771f4a9dcc7052dc7b031eb57c68e33e933426d89624c4eb8a604438a8ef7e094357a54b80c9bc70bbcac3609a930c456edaf366b7fa1e70d0d7f15a2462178548277d11b74e5e9188e220edb6ad46cc9ca3e6019323d8806f2bd6af6b2ccea5f491f4642c69e651c218a584b9ec
+Qx = 0af0f24629c1fc5f0e968ff923757c4857430df4c
+Qy = 7dbb6e661caae47a78e50ef97d65eea9cfc37ad7a
+R = 315141e67772d3658b76777998f457e1fc8d53f69
+S = 35a129f92d1996f4ae04df5f092de41c41490b205
+Result = F (4 - Q changed)
+
+Msg = 014855603ca35d201fef46ed17161d7110d133457877e862e66f0e9e0e10773e217089dfd728924ec5849c1801b5a85c4623fd8e357fcf6c778e5614e6817ccf435640bf6d400b3694e7255c3c855872ca3bc79f3bf38c805cdaa20e1e0cfbc437c891a2687c4254462c02f20d2a5b8110daa86e5bfeeb0acf262773c2ef2c29
+Qx = 27b272f13549466a930e59cf28039b6275fbecbc4
+Qy = 3cb630a44f888a520dbeb35e29879ea445306fdcc
+R = 36682aa4d99d8d90629456812eda01eb1afc5c30d
+S = 02f83faa2e844a8005ae32e6ecc9202984133261b
+Result = F (1 - Message changed)
+
+Msg = 00c724ef48283d768b1ec0d2de238c5787a1abfad0c75dda1d070ad361dd00827a2c55ce626c505a3fd984f8bd1590af9546048f9251440139a44fd14b2b5b7975b2f1cf1041ea9ad76685f39f02af4f6b7a1a88dcc47764f5bbf0a7813603d7496a913287773654226956f80be2bbfcce486e4f606f3b0f747c45a314eae681
+Qx = 0bc9eb8daa9d1bbc80ea479ef923d96fb5b29f50a
+Qy = 1d60172e81f2b9e967c1f96c9688a7a8b32a8ac96
+R = 29817562328d26f02658dc85fec2bfc223fc32e6d
+S = 0539afab0e94a8d7d6882060bf207957676ff45ed
+Result = P (0 )
+
+Msg = e7192ba1662aaf55cb253fefd76777405d755f8069a064ad6a4d461b39ddcdb1c6beec4e7d28716a1f2b302aa10036c07322e744190934718b8760405994ca146e8b61427acdb22f004245a97ad9801894081b4890ef5c3b810e651f64e90ad39227163d9fa9d0ca181e4d84c9a08c6138df5764acd2409ce7cb331b2ff9b2b8
+Qx = 19645356b58efd5a0c0316c27a5a6a772fb8b63b1
+Qy = 03080853fa9881b07f60f48368f42a6822b48de17
+R = 153347f2f04a34a35bba1f2de5632fe2c5de90537
+S = 1d68f6da4538d0f6290dc0113141098fed4a9ccdc
+Result = P (0 )
+
+Msg = 79ec5ca3472b96a1ed0a43c07e45357eb08ac7e99582d1310622bb9894f0ccc9dac0c4a6188bda796d7773ea6f33fbc203aefe89a43639f7484f677265684e74dc7e63e360b30aa21db354769dfe218a582e93a7232c4ea3098f17b55cc33137fcd9223e2d019748c18f1f4c6a50eba649019bac386e1449c4aa2f77640901b5
+Qx = 6a47b48b7ff7ab6fb8cb59ba4f03d15ec4eff7662
+Qy = 56fc1c22bb33b50468342d50ee23c520031d43606
+R = 0bba125de5e1115ae3f9c85023ebfa6ae9fec4f4f
+S = 3a272566cc8fcbd8137e0e698120d1568b155c34e
+Result = P (0 )
+
+Msg = 7ea69aa563ef94e2beba6834c1a4c63b3a75d4cd5a4f86da9b8d263aaa0e5e48b97a022a9ba4657ac005c5f9b8f77b1bef1b2467ce319bd5194d490908a7e78dd078c6c4fb366591d917def82ce80583f91fa1e38a91d2957c03fa6ed92be5009ce3d8b80cecffdf9b87cfd5d454008748b296dda1356c2cdd158ce365276d02
+Qx = 3c6ab701863d6f1e4181db35295352b36b9b0298d
+Qy = 203f37cb5f86b44e6cb1f88104f64e81297f2d148
+R = 23650659888c4f4149b7db4876306235e9d0365e4
+S = 1c566e9639e9b607a618c206a498c9f153e82c611
+Result = F (2 - R changed)
+
+Msg = 979fb7bc4a1c093585bc5e4ea8d199dc7ef4915c66f216453a5f68d8c044841a1efe0cfd11e268ac520d54f6e12019267594a425fdc18ddcd00430ed94831eaad991f296e55790d11b97e3e6b0c347def0dd1651d4f30c6d7ece51c4d6a36d29c5a15df8f1853de744405b20f3a9dd49be45a85c8cbd83c44b221c744973dd0f
+Qx = 50065d1b441bfcb1bfa69d13ca53f9f1877b401dd
+Qy = 18f6c71048cf2bdcac3159d0333cb5d66c1d71dc5
+R = 23d5906f7837ea38a4ee0f60c2ae14da4ed61cfdc
+S = 1c82df612de124d20459ed2afd00d3bf5ad84cd48
+Result = F (1 - Message changed)
+
+Msg = 754abf7a77d73515a45b736757825a136041e4537dda15101843635d5680eb0c06b80a0185a951f56a1fcc0a1bba61364b0dcd605eb20e9d3cf4afc0a9cdb9064ff359f07ca580415b7d12038e78d4eb7039893d08bb65d0d536d74068ab653200d1b4ee4b40c7aef85d0cc4eccaf77a3b559565f8f3af410fc9a6237d637f10
+Qx = 7fc82a493e34311108ffdfbdb4d40a2dad95022fa
+Qy = 4ffa0ade159562eca8c379e5bc4e4b9027968e527
+R = 2264201525ec2d1e27e9547868420e215732ca9bd
+S = 26ccf9178b9969fd696f145435a4f3affab98ecd2
+Result = F (2 - R changed)
+
+Msg = 88899e0c17e196ad17485d79920d8d7db6ab1a4029d43b8821dedc3f19ddc96688d867a5c712ce6748ab5065211c1b26e3760b9d2ddc823643e1083204c3beadee42c261e9c5930f16edce393645cdb31c88cd3cd50804f405baf1d467c340040bd28644f97d9981f1be9be3ac33a6bf068f6fbf27cc6e31e6cb1015beea9f0c
+Qx = 78a1029522bd1ab697025427e3dff96520cc4fa75
+Qy = 61fe7d75b4197d2d0c297206d5d496b485681ac00
+R = 18845c274a2918c4989e7524f34f66a9b0d293c86
+S = 129b2943a8e1f5307a0160fa625ced90b9828f577
+Result = F (3 - S changed)
+
+Msg = 7c0041a0f9ab0cf8f13e7935c69a655244c9cacacb007d757103867b29c0ac45d15da2955585d93bbc12f07cf9f61e127188719c8738c2d1eea9ce4413f5cd9c8722212b64385af88619773f007e3c8976424578de2b9d2df81fc390ac83aa4c0afdffc8eda41cd75d05acf780676556da9221824a0b5ba640718befe1ff1e78
+Qx = 1c0a2c22ecb15e3168fc960c0de6a099259bb925d
+Qy = 1d9217146f946cf40fbf43207d190899beda154f8
+R = 0e5c367538369e45c0e6a7f6f8ab5985f8ae5de39
+S = 34a74b010caea8dcbd80c8d37f26b0928afd21fd7
+Result = F (4 - Q changed)
+
+Msg = bf83da620de7a74de4e31f34732b1179b15a2b9c460d7c76aa933af058cd731eac32774fe3c0e2523b8faebc9120c55efc459d930013dfe4f51894e9d792ba30ff27114546eba10b9e72b65a136e7750965cef1db72c0902d891a8e54868bd9bb31695a543c96ef568ff4977c24cf00d34d6a0f6e6303c4ffaf3a7adc92aa8f3
+Qx = 073acb866d82ca519f835574ee7a137cd133168a8
+Qy = 02cf51d1f6f4a51194716eb51d30d3a333d7f7e74
+R = 2b3a5ecc52434b0a6aa6e65e530c3696d7fb1a7cd
+S = 04702b9753bcbc40e7ffb37800f24e554cd6ca981
+Result = F (4 - Q changed)
+
+Msg = bc565b3ea1e773f7118b14ab82420007f43ecba2043d5c6331fde7e683db3b0f6660d925b5ebd14503501fdd0dea3310b3ef913e13bf0d89da3824a8d6734a8b9abdc89784c093eb9dd9a541cf2ce1c7a3d338759ad5c88aa04b736984ea94504ebbcf08a7d06029c47d2d4dddf0c8318d683686589b838c08ccfaf6f6a7d9e0
+Qx = 1c716d19322956b08622f359d1d8cbf93ede0bbcb
+Qy = 3f210ce01ad63cc1319f0e039860d3b22e205a425
+R = 1efa106928a67ae5ab764aa2f4d729e88ff0f80c8
+S = 23ff0896ab5963491a7e02cc174cd632357dc8023
+Result = F (3 - S changed)
+
+Msg = cf05733ab76e2ef6e52974541f42e89a6f64790c76e2b5ef824d04aab1251bc96ff218d52bb99b33ceee6fc31bcc415261014d05b3144c536be66a3d2c3fdb1a98cc03f4ce0c5fc2e5a28251d42656bc360aa036b042bfae6d39c9aa0cdb40b30e03ee9161b4f6cc5e24fe40c7721659aed8b8b44083cec0f09a807610e4d47f
+Qx = 0729ea095ee8dfc4be2333f41a0d9d38b57b0a738
+Qy = 4b7c7248d5e62a4779b39add6297b1e58c2cff5e1
+R = 20aefd06e95edbe8ce663874513f78c8b09c432f2
+S = 342edfafe63bba46509a0ecf5a5163404625f00b0
+Result = F (1 - Message changed)
+
+Msg = d3cf40ec78292a1beba229ebeac58d889d03c4bb36914da3e94a4d92946b4ba9811817c949af1df53115626f8ff90000974c9dfe3872d3231c91a03a6526f4413acb2a61828ff3932ebf92cbeb681f1cc65cf4ac5238b789aecbd1d4afdf4e0ae623e230646efd7896619cb3b20f5eca4ac63a0c45d0bc13316e5155563a794d
+Qx = 734180a5bbba49f47434db4420fc2652d5027fb10
+Qy = 5263fc6bbd3d1afa86a543b0a7dc044b766939d18
+R = 36369e8af4686422f1dfb351997d09a4a207a92b2
+S = 333861b1eb923d7dfd851b2a2bedb69fe99aa2eda
+Result = F (2 - R changed)
+
+[K-233,SHA-1]
+
+Msg = 82a4da2741ec971c42cf873c69c0cb54059c7975f96536deeefd6c414f7b9b24009caf6a95a34a3757c75cae615b7b34bb5e2759341f59eecf08ee5771a837bab41ed6018a69d9ee7f3f1b619b7d9227ed9af58345df1d17e2b383cf7d158a69ddbf8b7051b0e3b367d42d1d5e9748095961a52c90c8a820e7eeaaf5ac341d33
+Qx = 090d347615e437a38718081754277bc467b0b209048882c9d6964579caf
+Qy = 15af61c298066bfbc47b574d8b892a2caa055ad2f54eea50f90207f5e63
+R = 05406c84dbdfcbe3fb6d537fed38b612cbfdd9fad21bfff203f412eb706
+S = 0225e7e4649de30519b414a2291b5f084df84ab84601788c59acdf7de30
+Result = P (0 )
+
+Msg = acf035eb1d27f9fb2b38281560d3f75113320b7f747630bb9d7d0bd740514a9611de8291ee88a316fcbf3bbf208301f6e6147c8d705014ecbcbf4438b614bc789dea90da1c4f5f85488c91cfbb131effaabaf2493f9d9e07deba9e5456cc3f6b394bf12be5d18bd614251f745a5614d1144ba544ff1bea19c8af367762c6a435
+Qx = 032660861a79b461b8e2cfff0c12e2026d141d85f042220d7af016fe39a
+Qy = 16e4d31cc852bab40f42e3650ddfa86c800a988675cdd311af0540ba677
+R = 02d8a32a7e61837306c53e8e8b33c13b5c1cf238594dac94455e5cdc70c
+S = 02327008de25b63685eb7201150fa570695c60214a946aad6046a8bf3f2
+Result = P (0 )
+
+Msg = c6e7da47c9767ce4ede2c861c256cecfc88105a48b1c7650795abe2dc5b3cb8837366dda5bc235a2cdca0dd53c51421d375e5e446d95e5234c5261e7784733d8053892de2f308d47a57c951b6b07db1fa09dd4678512222484ca224092c15165cebeebd1d101f5ff59ffb2d4df538b9e42a0336458b60ddc7172ebfd5c048efe
+Qx = 1b9e14d2eb9878077d2049b976bc065d09cbd854c440f0e13fe0826700e
+Qy = 0694547f07e4f5b9bbfa080290add778ccfd251e1b6d0423021af449cf1
+R = 0266403b85240de4169caa4ac32486573b5ace853e68702ab703588afcb
+S = 0205a6c76a6f0b12892e56053e42e35ac0b5118b03561b42e3304f59730
+Result = P (0 )
+
+Msg = 24ede25405a014e1bdc088d380fba5383ebd9f336b28c5317b88db04d2281bce7332ab23471e258a594dc219078cf2faac93fb079903bb78b5ab14e39939ac64955afc74493cc56bfbc1b20593e59b4d2bed2b78100e2cfe1d886e232ccd23eb8671baa6e031891ec9feb00e1e9bc1dec43696140fd008d61c201f2269f934a7
+Qx = 0c0b06974383f1ce530d3f35a4a007ae87d0edfbbd9e40f7b1d5ac9efb5
+Qy = 19a37f2dda74e77fb5a2a44c26e879853edf702c8d5aab7235b96c4945e
+R = 064219ddcbe9943411485a76424254661f387690c1b98a9d4eeba35d2ad
+S = 033fae62cf58940ce68761786af4fcc4792654548ff319bad7a1775d9df
+Result = F (1 - Message changed)
+
+Msg = 4a3d4b2d9c6bd7817440f6556edcc92c8ec4343c2fbb33af6be78105533f4f7c61003c241f85dd10eb58e7d4fba0e3fb25a77f4a8fe8b644816bd1974ec03cbdbf6f4bd6026b05bf7df3c4c1ddfa8ac495f84572331680db4fe5593921458ac9003964484bcf7b9c1d698fe0937e0ffe17dd79e86499c8211f22c1e3987ff4c1
+Qx = 09f99d832e07abf4640ce10bc14494ec1f308ed12988785bd62af2a4d49
+Qy = 0362798346e64c5046929dc21e2cd2a9854a20ec9ac5641de34f45488b4
+R = 0012b4b82177c277acdafc5f9b894a9c8c57d68e590edebb224f3333efc
+S = 07944e04e9ca4e42376483e1e525b98384643670749def710e838dbeff0
+Result = F (3 - S changed)
+
+Msg = e5910568833ca5cd3d8825220af6f63b90f85c031342a0eae9f09b6a929e8660194723a7b0ded8ec795eb52b666b42edb866e26a7a38c1ac000ebb4be76ff05b94150f91056fe5cdc4b05f48e7de121c21a3362bf2dae9d8c5dfc674ef6febab86ded2fcc300cfc674d56c08b2afa5187d14fe21bcfef1fc74ca6258d56129c9
+Qx = 131499eece1668047eb5c72c1efa847b7f283ffcee179daa881443b6d20
+Qy = 004624a14d6f03b0269fcb49d8049195e3fc2e7b2b93529d5a129bd6eb3
+R = 011941a6e892ecf120eff86048427501f96c3ba5e4f711b04183fdf6642
+S = 06eff8f5d52f343ef17a84ce9df4156634cd8a1b30b8c87067f75b1f85b
+Result = F (2 - R changed)
+
+Msg = c8949cf5697500e75e1c7d297ad01d6be602d9858979de18f2983944704aadf1997e52269e23d90cf626842f4016c13aad7b00a859cecc122d88349cc30fcc9af571e9f71ac107868be7ba6f922d22a86309b78cd158919bc7e432fdc31387654337f579bb6dabae1a12a027f061da78b68fdf282d4cc11ceeb997dfd03a5f20
+Qx = 1091d399c10b9b57ba7ecbc772b28757bcfe584407a79eb162a01e353c7
+Qy = 11969e49d0d4ce984b2c7040413018864eeb5bdaaaeb5ffa6bd0680c5bd
+R = 02e664806e10d43e53f3d91adc18b2b97d46d7cd75709c345263b8881e6
+S = 04f103365926b9ea787bfc21aedeafb2503311a4bf053d1a87203788705
+Result = F (2 - R changed)
+
+Msg = 1ccbb195e98a2010a56b0856c9d55e39edeb83b091cdd49dd9f1d651358e02b18bdd887e9aefac4262cd7c8322b81bf26f6a9710942c7af7ea5b9df2914724841adb0906e707f1da51f4a8f29a6e572c645cf0f8700f0045336c3b77761d35beb882b7f28aeedaeea3b897082f8611d5835dea174c06640c55a38b5dfaf9b762
+Qx = 0372e90f686d415bf6a862e896396fd37bd79eb96917fe7bf1d6a5d51bb
+Qy = 019444fefa0c3834f67557a43f7b96e3e0c886a6ab84af076b0d58ff5b9
+R = 01abd6cc5d25711c9abe0df22c9d82926c56a19cc21b83b636f63e2dd7c
+S = 04f0d6a11265bcf37efd5be5c17f06291899539c6ade61527a9d25256dd
+Result = F (2 - R changed)
+
+Msg = 04632c72b2e03d5d31d15ac34e6e46d6b8b0347841ba6bee3014cc4e203e4b022096699d46a4b1e70fd06ccec74fdf2deb7eecf51b58e32e055c75511b744bee4b84a6be10929446a0426b0753647378aa7897bb6d87325e2c7de0f9c048f8a63eb861f753f88f25db2a4fcfc609c4ddd1255e6953b72f66e32ec50b76926f81
+Qx = 1b80412ccfbb3a36ec113667eae777322f41c061e402ac33b45eae2d03e
+Qy = 0189390af920c9ce2451fbd4f5f4862b07af8c9182fbcb048f996ec6fcd
+R = 0306cc9e534e65287febd1099812efce6f8da61477c07316e79fae76be1
+S = 03ac5639206b7cb8d73695b9b5af5cfeea5008d5d55229c04344f0a73fc
+Result = F (1 - Message changed)
+
+Msg = e6ea434b392bb4ad1d330512b40da2c07b5a19763987a3229abbf4929f614a5ce3161d805aadccbd7ecf160f0ac573ba1447da8dde616d792ecc46f7c3ab471fd87298c388ebf2be11c2a935d8733dc43ae0b38599f5158cac1170ab0238df70ee8867f0687b158650fcfe8bc61452c60b7a5b9df15f2709578582f8852c63a3
+Qx = 0ce0d5dcc990363c8ad844fa9c0acb0954eae58be1e7a245c5a26ef9181
+Qy = 1e9ce85e90ede8d8e437ab99753af46521cf34a8fe82ac938f6fc16514e
+R = 01799ee34ff282d28c6c74e25941eef748aa3288c31dd4203812a3f1642
+S = 0303ebfc4b395d8378ba2ff035b06f036a69a476c01bca76ee7c768e8b5
+Result = F (1 - Message changed)
+
+Msg = c523d6864fe87159d3fa3d76e4984ff5685d7bb5816687cbc8e1cf81dc8f8434f6278b4662481751601d14af7289210d1d4cdf9664235698c39dacb0f165b4b8a6d340d4928bb6fb8fbb9d185f3ec9e831f044d45ce82d5caac28c4b1b436fffada9e98b9ed26d0c998982e61323f1f89fd942aaa600f1700bf74c351e0c1bbc
+Qx = 1767cbc3b592732602fad42cd76808f241b0e832896d6fdea13e4152f6d
+Qy = 079472851b0b0d609e4fc17b5eed14643fe47778341b66a1df28f5411cf
+R = 02f72f8c494b5608e80aa56220518d685c3776da84b981d7dd215f34406
+S = 06daade0cd6952fd43f4ed8cd177ae58dcabbce20f17069159987dd14ba
+Result = F (4 - Q changed)
+
+Msg = 8273ab3888edca37bc6b32c1ca200453f98a8de80ca425098b582fc70eaeb9cbf66f1825a839bdc7e4fc62ac91bb740e29b6daf6e9a171375ef1a4f2a3085bb1ce704e2e06d92556390de2cc269b186edd440219ddd65fee927af3d867f1533789167f28aecb5873030a99f4d96d2831b391a8c10b5ffdeca31734cdbfd84b69
+Qx = 074440ccc72aa5dbf5dcf768154ed6159cdc9c28cc1bfcf5f84ae1cfa1d
+Qy = 1aeadf591d430f06ffc7ad17ed2160c243be99025d5bc4947e275d40e6b
+R = 053db98c98752ed41d5da46b6e3d3882ba300b7d011337f39e3a21e4f77
+S = 05dce91fd5d1bea8fa5d789388d970b93b1f2e1bac92de2e028a5f47792
+Result = F (3 - S changed)
+
+Msg = 59ab671a99d3a34a2dc46c9d8a68de6389073008e3acd17521a5bf006d9fdf868caf33f251d3b766c72462f8a62ccca5fa83f91073b38ce8e9be46ca8a1f5ab24d1850ffe0215a9a550c9b5b34b4d720ad3b583177e8e5faf8bf03cbb944f01575f50e426c78242b0cb0104dbee5685e96a177360e9e7f2bec12eb9d575cef93
+Qx = 1e4e5b6c85f4a750e9ee7451e04985e1d90ee6c9f388daf3dc6a300037d
+Qy = 01d5dd5950c5920e0d9e9376ea1ae918a5728393ba95a43d42ff74ec956
+R = 06e666a16262bd80bd51e42a8eb767ffce24bf4ca022153c90603b6fc0d
+S = 0343f88ed312ec26b48f80d4ed49cc9b7139cd1af54ab6713c496be5211
+Result = F (3 - S changed)
+
+Msg = f281ec71488ba9005100554c295db177411090f4d44d7a11f2077cdbebb232f90dacd42fc9bb87809d3a48fecbeac8c026efa014807d71af381b900ea0f2edea258abc024a72b21c54ff92fb49e1b0ba6918ce398693e1176f5c4d3bc20e70259d216207b7b284d2600b3a161db34ebd34ea3926318fd25feaa8c2dec493b3d1
+Qx = 1eb68701a3782a3c7173867735f2c76d2197dc07fc9184e6d67523b0420
+Qy = 10374dc4d6e30997aa83bb412734f46b21d6e488c576d39293b2db2fdc1
+R = 03fa446bb5eb167b5ad4e352304767f2654599b8277b424d308def77e73
+S = 0566c410cc1dd8bac7e0ef206d2498b1270d4dec6f94579e05b7331b3bb
+Result = F (4 - Q changed)
+
+Msg = 7814143655d66fc35206fdefeb9699e8bbf856bfcca56860774521ad084fa7dd0d2ad18578ad1a53a996f84039ee2cdd9c103b6d164ad7935df2bf126501085e33c80ae2a3831a751711a53ddf1b4d0b357f1da3917c4496d720d94256a613c189fb67c3af79af7c1b019a27daaa91003044877e4137d54a175c434fa0e05d41
+Qx = 170fa20fb7138402dd1a2974f38e34aa40887675f6e82f72de6c93dd707
+Qy = 143fc0024ad4664b5bc4554faf43b62b1000bf00f407fda2eb3d69cb5d0
+R = 04f6ac584ac6456379e83931225e7257a60f24f644758cacc3721883d3d
+S = 035afb55c774416aead6c2d75c45a4d2422facfd39447357bfa24c78aa8
+Result = F (4 - Q changed)
+
+[K-233,SHA-224]
+
+Msg = fc4cb7b52cd8a0350bffa51eb28875b9bf4eeb12dc6a84c2c5f18f7e98b92b77a8043f89a7aacdaff26cd2a2ab1562fd197357bd098b74f1c08f347205c1dae9e30e4ba4864e6a309b180b3de0d57196725744b7d144cf265f56739359b51135f9c058b0a801fa44a4846772dd7112f3b822034be4150e6d769de70ceba6ad59
+Qx = 09519e08532fad399f3d69a57e248bbead22fd2e5dc784feb3bb61ae22d
+Qy = 069bd883bdd1dc1c3b04e6ab7ebb765097712741dc88bafc7ded26affb8
+R = 067b025272a74077e9675ebde9348b53904a1baa8df5e98f3161cccf5d3
+S = 07737820d0037c7de9c577e4f9256384401071bb925a184913259232ed9
+Result = F (4 - Q changed)
+
+Msg = 219613d4194afaa7b2c5be656d44a0e8b7215b9444ec1eec4d226fadd9d353c4829792d96dd33a994839ec1b47bc74110f2f5bfec3eafb1ee6ab9ed95905b5c25b03a116fe8c9d652b3f501d4a94d6e6dba0969e341a39e9b92a1d5959beb14581c1b93ac4dc4b96236c699723c3a2ccc927711997d498c6d71fd74e127c37ab
+Qx = 0186322fda5ae71ef8e159cd335702238e7296f27325724a6f3453b3c1c
+Qy = 0d45e90c61ac44c7666ceca04b7070faffa8facaaa7c116f6d8cd7b2f28
+R = 01779c66f38af478092998989ade5d9a96e269a9e24d06fcbf73c5cb5c9
+S = 026866e2ee7f1e2aa8a327130a611b05b201efe9ef161d50a4aa71fbbde
+Result = F (4 - Q changed)
+
+Msg = b4a4659a5c20f3af085cf047d9bc50870bfc44f001ce6d0e0d44238f1f61af245bbfc013f15860369d619973f59a39baff6f211a4cd0d44061705524241bf1a815705d270ea43dd8299ca4b57199e88fc492a5315f940a1eaa6205b69d67c55148237fd2940bf9e7e9e1002487b10175116735e37fd2ae5ca5da670eb1865d37
+Qx = 15e948fb47fe493ab59b1b03c8f06ffe635e9d95e532a6b9736fee039ab
+Qy = 08186b0907c69e2856ef55f575644ad185afa400380f631cb1bdaabaa7a
+R = 003b6d091b7504d7bbe3156bd30b68cf89c69e3417004c12bf8fab9419f
+S = 0042b8bd930b72c983e781780ad553113160b1e88c1420ae555031e0cda
+Result = P (0 )
+
+Msg = bc85ff0ff9e412031c7e8b63fa04a84800ca692361cbf175bb1cffb8547c72c4bee1fcd4566ec5f61339cbaf9db36192eda6d667e4ac1fe785a0a8a3ef674748a1035f3115b82c65723e3da4f6bd480b6ad19f26ebaebaf128ccfa0e19912298cc6a321295e4f360625c4a0d61af8578119183f63ff9c3722e9effb438f4488e
+Qx = 14678e29ae776d7b9e8f4160a1b63dcef28d3f9fc23f973b728e4953873
+Qy = 0863a1e9096c0a197bb837dd47da73dca585b292eae7a0a2992b0fa21be
+R = 077d2546d931b48628feec96e5880044023cbc9dce4ee02ebc62fd92079
+S = 07da348ebaa314f85ae01efb6ae974db34198f1a71c069756674233271d
+Result = F (2 - R changed)
+
+Msg = 02dba4b579ef0169c8bf8403689ec078e36a5280db9abb3711f9b04e4ccdc50a0a3876951924e14f5e534ecd8e8a90344dc8192402e3dd6c19e45a258776a6e1eb5aaa87f7d770fdf62e0f13c9d2807de2c75b109425a98de03ccfc98e90ccd4ea6b2cf68d9b17dfd04abe46ac8f730ed8b396bd2773d98f648041df9b6946e8
+Qx = 12c76c6da3baf752184c9412ac37b62d698bd64f652f1c7b905287296f7
+Qy = 1d1e204433fbf51386311daf06a4a627bfe8c2562e563ea9310dba05e3b
+R = 006debf5f2f63da931d30036c51ea1b51ed56944372f4168ba4246c0db9
+S = 06fc4aa020b649e9cbaf383ba1691f0b7e7d5c247a99e31c901c7ec14bd
+Result = F (3 - S changed)
+
+Msg = 72c0c6cf5b2a694575c5474bb65e3299a12d4776de2f10640cd90432099b6fdad29953f0ac178d518e6960b0a29ea74960021109779434c5e1e7c6d5c830b2d9c0e9d639e8cae0d69cd671b4924b5e98ee44f9bdb550a1b7bae3350ab5ae7898de7bc70708832b1ae9f80626272a9644d2b024b5c2bd6be69cc036b7704d8e73
+Qx = 1e9ad4d8b620c93cacd4c7015eeae2f205150d64e2e448751f62999f1d0
+Qy = 13bf50d5bc502bb374d0a3636aebdb68ae255d3c25e4e6a5c4a594b5a4f
+R = 04ed80eae781ab5b734d378c45a3a4ae4e4b7e9b914c412854f9753ec49
+S = 057ad619c566ceb5b2f7da556934da53c4e0d08f1a882a2d37669889584
+Result = F (2 - R changed)
+
+Msg = c42ba8ac202ac92f98ddf3737667824bda7571132e4c5e3ec38b3dbb6cd817d4e66ecb12817b3d677229f41c1533e3073e72a5c4e24611d2551220e7c092d0a1d8fdc4cd8be021f9477f8267de0d83f7d27ee20cd7952ab5a8a960c64da5b90d620e20d294b251f743829b9ad8cc88b3b114ddf8694d5f178b91fa9ea2122bb4
+Qx = 1fd74f03f9eb9d36b569c9ff949e3950eb3d7d4fd36db597d605259bf2f
+Qy = 1c1c90dd569e56dfa66c448762e233864f2a20f54ba6d1957de912a8962
+R = 0007c992bdf9f151c2bf78497b8f131ddf896a0374cc4af040b78aa4367
+S = 04722eb85b9405195f49404ad6849643a417e5183c7b7c6473a7e9268a2
+Result = P (0 )
+
+Msg = cd5be74dee439bee65f92512a7f401708110d52b6894a193073e75ffa0c149d93c3dbf05a7c813b19a8bf6337769fa0a515723a3faf93996dc41f2585d223342fc474c0bdc487e62f6f60bd95f7c538ed879edac6db50d18597489046cb1e026f8783e6ca2dcc2006bb767cce232fc55a6cd99d2359bfd219f77ebcba1273627
+Qx = 19a348da33f7c6770adcc8a842a068b3503540a829a3c74aed1b87998d5
+Qy = 1707dbe4eaeb63637b07dcbf87aa4e9459f7359ff67b5b5aa1cb1ce2845
+R = 02e4ac218b97e72e54e366ede4d68984b07dbe3b4b69a04e73dbc480a8c
+S = 058cc7d79144b21f42e2415e928dba2e0912bada96833972722089de5c6
+Result = F (3 - S changed)
+
+Msg = 64f09b749201d28e2bc38fbe0fda95766a0864b5a82c9fbd66f468ddbaf59c6b8852d5ceed19f979fa500d2fa116cc6533c21d5fc078da92d7991dacba9fb9209779c99beb32eb4f597b33ce9cfa9c51601f0a386e185ba6c570f1a1eb5554e60cfda17b0f5383e4b615a95ee4c1103bfae639326ffbd96b8eaf8e11fe700748
+Qx = 1fe409a5b5aad5eb0f9bbece61eb90dac280010cbca19ea77a452777e05
+Qy = 0bf1af9c1b8487f5ce321607a39abee27eff8e520137f20edfc920f5bf5
+R = 0342b6f86d70141ff4ef84bbe78ae6aa32e0356ef638cc6a31415ca9ba1
+S = 0606fd254cbd9114c437b4fc7ff95a9830299145a2f24969a44efeeead0
+Result = F (3 - S changed)
+
+Msg = 833eba7a24620e1b1f6242dbf2f3f0ebd5b73148377440f580f7baa94de8920d7d8f3ae1b3c4aaa6fc7d24c5bf8d651238798ad60c227c5e8d4f220151f35ddafbef85e87529f6ed035b57fb87ecda13ebedf320631a5eed5def2d5b2adc383fb22c0801058a8d3d81ffed2bbdb9406d1d530854b6751013bc7286d4332429a8
+Qx = 06631290e67b486103254cf20daccca10e8023186a8d5031d4a1a3f1b9a
+Qy = 064b56a70a13abe171edb8cd9e69974cab156201035b72178b1aba4ad43
+R = 0333a0e205008a960c1b4a5a37670c7d81d96ad20bef7ba609c0f26821b
+S = 07c8b8c5de2d3c9885c6dbe48721fb5d762739bf82be3e1c2079ae28e4e
+Result = F (1 - Message changed)
+
+Msg = 7ff2abc05a9b3f81944f7a76a0753d398cd7a554723cc66c5416ff067e4a8491db53a18a9a41a0eeca8582301c6b32a3c31dce88bfe4f128714598d24caf909ebb412e7d33e6a1c50dc030fc35102a0a351a56572d066b5423fcfde79fe6a63af9e5fc79cffdc98309a6f128907f66e3acc189ec12d5cf858ea19cb946bda022
+Qx = 1d8c2283e9c15a775c16a466cff7f0f59fbecb25e57a75ef6cd975b4378
+Qy = 1881f8e1c93d3d8084ea1455e090e1d29bb520b3512001d6a3bdfba6367
+R = 01b84300b65707ae148d8a766f764de9a3b485d556b3003804de9321af9
+S = 0124848e90f5e30f05089c67ac23eea36fbed5af476f2875588af407beb
+Result = F (4 - Q changed)
+
+Msg = 4934fad84315335562965c5ec0bf46e7d2d26fc63db226291e55103f12b72344ee0b5d3ec4a11f5a078ba16cb874127eb6df3694b390dbb49913b085e845be6d8318a65cd7fc3469aa603a02a364fd51ee705cec68310df4b0d28e31dc464355c0d76bc866660cd7fb52ab850c85d2e691fd130b010069457df533cba6dad607
+Qx = 145d379c89eb90efc1a30c2d1d82be3c5facca0575c07358e331bdee852
+Qy = 1f07a591b2e4cc17a42c814777b4b6d48e0a4e4807526efac528f73a2fa
+R = 01303f8a4275e889c60aa02cd4cb92e07f12e255d7ffd63ed1af2ded678
+S = 07021b2a5240ccdb0bb553ed58f44fd73ab627739eb26c39d195c060858
+Result = P (0 )
+
+Msg = 490d6d05b3210f572cb1109fdefddb10a9d71d5506d98f8ef22e83bdd21ad05a55bb3dd66b089f291c0687960e1f7e2798b0d9336a0d67402d17306bdb53a092e8982d8e693588f3c1dcd31757a0159369b912ae50dac9261d141e6af50e4a767689e643c0a9ec84be7f93b73223f368345b9110f7cc6fe5d6866262b27fe1a7
+Qx = 169e62a270bafddaff5b762d68b724677647d178ec34b2185e53e10110d
+Qy = 19c662b5a5e27198d1e2c7a2e581eaaf4df640cee56f0663c98ac2e8802
+R = 000a4903da0224778b34ba7251553e2277c5cb2d387ad1008fd452845db
+S = 03057b8bad69940f3d0ca55dd554123ca0621224c1b48346502ab3e0d97
+Result = F (1 - Message changed)
+
+Msg = f91681cd281c13c35d3dcce65ff355e075d8a90b2d6434417f6cd8d4261591001aec2f92e4fc5c794a15675d7ddd22d294edac99a29e044ba03058facc773e1943fe143a538fa8fe123f6cdaecd12c9878a11ba3a1ea023a08195babfa2d76d41b05a7f424e0147e7ee3e0ccef85ecff42dc3a7beb8444940c43b5e4a8307d35
+Qx = 0d03301a31b767a95d0fee0b9ccaa817f2ab36d847a7172461b934b852d
+Qy = 1cadaa0c20250ce3553e92bb253aaa10663a903cacc243323b7b2e4d043
+R = 0721dc1a94d71fffdd89db1d078a2b4c3c81f487e4054380733314b06a9
+S = 0499945deec7c7670b859042bb4221af31a6798a7596798e8d7a080b4ed
+Result = F (1 - Message changed)
+
+Msg = 8b54fe64bb8cc7ccb38b76a70e4efec83753bf94064e7c7e1e8f28d37d58c59f6689d74c69e34fc84579e41427d829e2f6e522e3ef38cc672985c6dcd21cb41f22ed74f466e8f3af6b8ef5f222331dd421946a099f77b0e3b5407e86dfca64d9b2a26cb7209c15ef7b3f28d16838b945972b4e036782dcd89c4d1c283108878c
+Qx = 12d70bfd8f7de9773fec7f2bca5932d50cae168150589d5c65dad370ead
+Qy = 09d36638edb034273b9b0acab1fc3243f651e91380b87f6578558f4c340
+R = 0247a5d0e37b9601df394035a1410f73c263dd0440fcbb0577da499bcf4
+S = 051b1fc23dddb05dcbd42012f4a12002fc55e518bae3d85a60d0a1d7992
+Result = F (2 - R changed)
+
+[K-233,SHA-256]
+
+Msg = 6719cac1ec6900ff80ba613a7db7b68442ecbe21603d1d25fc766b6ef1878f7cd86a3bf6e17d53ff987ab5ac07a6a68d64b60f9acd548e327ce73b8ab611cc7173c28f524ff5d654234b1fa23e05b417938e19e5efeb757a2e5daf7229414dbd1a100212ed7d2561eba567729ffb0fe70ea7df638b071bd7c3aa9f6c2dfc6c6b
+Qx = 18fda2de3ee40f8e9562d773ca9bf9559dab84511c73d4131a71cb31cd6
+Qy = 14e314e03df5a8df9f88462dcc428e5e28312557b3dfac0913f46da3075
+R = 044b852007552c79edb55d396454dd96efc6d6bcb9f11a462235b4db14d
+S = 02f06a4c5550c45811ae890e316b9ee791a42c7079fc7d787cfd4c2db9c
+Result = F (2 - R changed)
+
+Msg = 34cb6198e4cb52ecd1d43a118f6c80858915de2520b8d794964611c2571367a3ce5166e4be07115840551a159a6f79b2776c571178c1ee2ff55f0de117fec86bc69d441e66a8f78ed0b1ef8118bc41a9faf132a037cf2276b3858ccf4fcd7466a37e6ee560034c4f09fb29115802eaa09ebbfbebc7e542e09448ac54d1ef33ac
+Qx = 19b47eb656b98537519fbd2ab2cad8a3bfccbb113fd61fb1a516f956533
+Qy = 1c4882d84aaee097bbbf7624fa8e527810999469d4d9eacb805d6466c9a
+R = 0064dc97a6f310c2b2778d4c6be45ed7f7d999d9008712afe0bc32c7e97
+S = 0225bf3fee7f182769303d046ec332d9f2c1f3688715686a3539b22775c
+Result = F (1 - Message changed)
+
+Msg = a619e588d2fd8c8786db7e1c25a076a636df59b6f38c69873a13b471148e43d00a9e475d470ccf8dbd38825d07f0be0a44577e38d269631494b2dd2a0de31f67cb21ea3d05a018ccb3a94b5a1a4d554fce474add7821da75633d3729a5c1756e945d84538a3b7d4b69d3167b7bcbcd9394bcde15cdd3701e313cb0a3b86522e4
+Qx = 03d027adc776f02dc61b73bb6e024ac3a56d38783337a7b45582ce2f875
+Qy = 14d11fef06300982b9f154ab7f43005a827dcea84a7101a1a2ea952373f
+R = 067c8d76b8855e32772937fafb6217e327e3e0e654c53c429d533692e23
+S = 0786b8df13f51d0730ebe26c8f9c6ac29bc83da55935bee28a8b3eb2188
+Result = F (4 - Q changed)
+
+Msg = e0f37dfd7ffc8a5466f1356785a9a6a61e0ef635d950ad5eedac89ed081513ece425fa03276abe29046af6a6b3cdda9c162fef94def80912f01bfc7e58ab71fa0f1472d634c9f39210fa91533c95e676985c12adb894d462f3cdceb9ef6df01c13807729da76564d22af1c78e174fb0ea0e1ef366690c0baa7c7c953220b620e
+Qx = 056da4469a2f0854b92262db4dbab70d213670d89b54136ad433b59a3a0
+Qy = 039c1e06929da10ec9e5494c94a09e859bb368635e8ec5bdc8c3823e283
+R = 0449d9c77c32b6d5af2eaa2f73bc8f70de98e2492fa9f199419cdd7649b
+S = 03284813f43479c614cab540c2d4914151ac0d0e134432c29d689371c5c
+Result = P (0 )
+
+Msg = 0a8bc1770a32d6f2c4c270ad0e5346565e22a791dd9e5294d7e6d6703a954b6b25d6ca2382d15e552a81b3aa492f52d5c6cd7f82a9acb617b6fa9bcbef3378d4d5cbf715efce670ffab34aadfc43a723b0f99ed6a31d91819f8d3aa31fe5b0a092d0f0b23ff18e6efb5df70e591fdb7ff194d5ea8a25002c2f6066bc1ad498c5
+Qx = 1c074a511d481f52dfe6b3e72b59961c51bf1318c226005f852520e3676
+Qy = 1feb16fc854c98006a7609b4c7a17300c3cc6d4b41d014a57af45522924
+R = 0361d76bb3e8422205dd90ca51208d9cb5922757102f320454b59ed13d6
+S = 076f3370d8e7661ad3119903373ab1370a5cc6c4bb53fc9af1f9bd7d473
+Result = F (1 - Message changed)
+
+Msg = 5f4d0eb047e4361d7c393a2cbfda7d72b17b08a909f1e0c8999426c1c04791d3ac005dcd25de7fd820a9a7b1f317a3298edf5f2406545a20a7e97c399216a26e061e8337102644c386ead4a823b25c3d62506c783e8678c2e9a42b1bc162bc197cbbf162f774721212991f40c2f90b471ecfaef9c5d7556b6d3528d2c012c35b
+Qx = 164bc13e11ff04eb12b7c1a067f4acc950cf6dbe7e30ea2adc5f0b5c22c
+Qy = 0b9e341ddb661df0ef77be5ebc16b268a6fbe0f21ff6a541420c1ac4592
+R = 0062d7b918fa0c99dd61c1eeaa8d3399e10fadffba8945d5804d46d6e4a
+S = 0725017995752baa424124b019324e6502d126d8315a9aa6f47fe7477c8
+Result = F (2 - R changed)
+
+Msg = a0b81f1b5f04a9ca471f3301fcf708a716826597be3ba3b6c698798d166a1615c027ed1b73539241283e80390c91df60af10b427c34919317c33cbd49ccec88070c810240c2fef15625d7d5bcb9a7177e4d7dcbacef87386eb8fd8f5592c241a5d4e9407e0ee84d66648681a33ee8c391a936619984b6109b11d7533a0270873
+Qx = 102c55e3e684e1bdea4614d0b5d364212040f3330d08a274857dc91ef2a
+Qy = 0caf9e7fde8452abb690da59f5e8f2e0e039287e107228e0256582ff019
+R = 0333a64d45141c7e994c0c4e1266a65331dcf9df357cadc022bfb0d2a2a
+S = 071460f8d5062eb8ad7bb006859526e33d7e8ea32bd3b4906364bd45da1
+Result = F (4 - Q changed)
+
+Msg = 67031e1fccf41b7da12bdfbce8161b0462ddf093814337cdc1a9088ec1caf134767ebce3067d1ea40cbbfc702da895d03d6a698db1571a076e77524952b20413c19f469ff8b46b12778fd1cd22f411533b34b189c0473f357b4ea5b2cee1c251cb83406d55169ab1e1fde0d7ca8a687cf873aa752999b82e9333dcc5d4f418f1
+Qx = 1cb4a5c38749c9da80a90d2cddc2c78b622f6f91018480175756d783f61
+Qy = 1eedc516e4753d90eecb6a8094291bea895284d241ee4189042c54ad3d3
+R = 024236890007420facb1f1101d0e28678c4afbb865f5355b8f30f0b8ec6
+S = 04e0ffbc132d0ee38fa62b77355f579b1c6ae476b48309dc9c0f9b7abbe
+Result = F (3 - S changed)
+
+Msg = 6235cf6dfcd4ba92ae97ac72a3f3518eed7fdab06f7254bbccaa41bdc86ce3ca1415669fc1c2078d5593307ba24ddd2e2008893c5858395486e1136fa1dce8540263351d6cc538156efbeb27053906eb4648b7ed078c8a1b1277b21747bacd5be192a1f20384e90c0d70011068d983838fd67e89c269f09c785c0f7ef715519b
+Qx = 1206c8794bc425d499cf55bfdb9edcdc8cc97419f4ddf99cdb66a90b4b7
+Qy = 0664cac8332370ffd39d4c53b6582b0daf5fa38c74a2c7a9756f8e527b3
+R = 03ec868cfa67a7522a77dbb81162fe5ce656c1f65278020ac1860f3e108
+S = 02f94319ce4415061c3407a1c693f1a884d19c6f0e3be5971de014b42fa
+Result = P (0 )
+
+Msg = 62269bc8a227d64dff8fd99cf18db25826b4d4e7099851b4c8412142813150299e7291687832c2862cbfe14b156404c3b19921abddc24a77407dff4f1beaca721d3ecf06ed9b1e2443a44e219bd9a52886b14f4786d6198fe0057c21b8962715e124ef5d1c4ccf9ce595e0ef72b2371e61843776da8624a1d623f93ac532b003
+Qx = 073916409b59965337c8a06805a760a1278bd2f1b54e78c52dcc2fee1cb
+Qy = 08d45a2114f211761f83097a249e97b2df92b5d0eac48ac9e86440f1153
+R = 0148b5ecf334a114ea92796da7925e19c220a5d496f0547878ae4a5ca31
+S = 0628aac56de338bd45d2950bdb1b2a1a55e58d3dba8cbc86c225721323c
+Result = F (2 - R changed)
+
+Msg = e985eaeb65db74f123c53efd8b8e14aa293e22fd48b460db9382d1ea5f1306b6ddd1fd8130fcfc1977011920caf89d335bb5191b107355234fe796e66ba57daee5378638212999f7fb68bf547c36cd733369983a0a152bb92da1f77874e3340b003a78b4310848b513870f26acd9a5ac4e10395676a7aed66152977d9f81b5dd
+Qx = 18798e1ce85a5d518d526da132b5e8d8aaec253fc4c0e78082a7fa1ea0c
+Qy = 150d42227102dcd566d3f6ec89ad23544cdc64144f5d4964903fb26f2f0
+R = 05bc9f065b79d07c92a3eea0b093a3cf5f19069c11865f6fc2a3771311f
+S = 01db6e64d17f8232f27bd87baa38adebb53777f218101dc2bd9cc22c4b4
+Result = F (4 - Q changed)
+
+Msg = e9cdd1aa971756a81c0b8cf88d0435503b31a64a03162b993c7739fcc20bfdd61ac733b75ef7c55a58be55aaff56e31998a24066facb1535e49bdf65dea473f113ec05a4e717374dd60753dc54d9acf774cb63cc69b42e5d45d56fd17c9db36437834ff5e5e6d7c3934f90f5f5490cb6d8dce1bdf6668bd629a678d9a0d7b106
+Qx = 10ba3efb17e3eeb01a7f359964ba9a90ce6f724ca6c3e1822349fe88c41
+Qy = 149222cd827d8325252daeb55e1dcbb071e9da32efbb9bc9eefbcaf17a5
+R = 019a16fb8600ef8b99eb043c8ee3e01c730f67880d6bd2e84f250f7d2db
+S = 07eed1ecc674bcbc4c8ca8de326f9471514a00d01bfa1bbe197b1ceb0aa
+Result = P (0 )
+
+Msg = 4eb7e581704d04816e1feacef66a7262b927af684789d19e8f6cb497a3941f4795e099838753b9227f17746b3b3d1fddeac5255063b8b8fe067bf958c12fff1f1049c1749bfce8d76b05e4e493ce456b5356554e803ece1a870fd3ad262c19a61c206d8d4a5ee0a58a19f47d907883ef7145c5edb9e59670daef2a1e1232b7ee
+Qx = 0b3800eb76da8fffd02cd624c6818fa9368896d9c44d565bb41d9c2ca27
+Qy = 1d91851b71043fa3826b8109fbb6d9f200fc4138690e1b29a7f5e3d8a19
+R = 077e7fbb4afd61c7d71edd2aa3c2856f8d130301e64e1c76976b9966002
+S = 0362fd609cc924f5889fa7d5d5afa7040633d5fcac0267fdf77364257c8
+Result = F (1 - Message changed)
+
+Msg = b7b87cda91314737b3b272a9453534a6db5c6085646870b0e6635021d924a5ababb03a42de9ffa5b2c532199ec5279b81299d3ad759e108e4228123b20711fb56a974ffdbd384b05e7417efbc65e8bef3555e4582542f845d9c64ec0ba88597e194af086c606a0c4916dfba08932ca5f81513ca63c64383e0d35a88855c1dd48
+Qx = 09cde2a71d84d92ff188d569327f8ef2c148fcf5eaa6899d37bc4eb7a6d
+Qy = 1a8aec970adea24479ae476a8f957fe65813019f9ee3edb30be36bd6ef7
+R = 01ac5d299143080ad45a088db0f40a51e7ec61963ffb67a0933cccc076d
+S = 036c371035deb662bc3f3e5a2ca72f53b17c851493fd8c6f35aa5760c6b
+Result = F (3 - S changed)
+
+Msg = 8dbe6d44b6c67f0884dec2393e57d928160c7656e2b1b2a946684abc4cdc3e50897eb36ff662e15ff42634e27730007fdb5eefb1150894670eacb28c4599b3d2d2304281288980731d8c09e5ee54c469675f355b1c3f7866c590765d7c2191638c905f6635f50843f6f515a9af0f261a7f1c6315bae701ed230cc7bc4ec350de
+Qx = 0aa0a114ed50c41ee7e07b9310aaef8c4b81b291083f7c68fbb8b642b7e
+Qy = 079e00265639c77dd9975946a6e8fbd2d80e703d570fafe896789256ea2
+R = 0013039ef8dcf6eb27c5f27860ad4a906f99a432589f892d3bf4206d532
+S = 062fb5668c5e3e04ce9b1249b91dec25068e6034321ed5da93c6eef778a
+Result = F (3 - S changed)
+
+[K-233,SHA-384]
+
+Msg = 221e5d22c5973ac250f61d65213fa8fa9f1aa2df07f3337b7b099da28a6de6b52abd00fc63acbc0b21badd8f49db380b2150c180e16282fd9febb78930c5775848d0024968610b3ee26dc0d5002041a92ff27bfa61af9842dbaea99735ccdb07628424793f56244cfc873c105cd9344cabca4475e8c9251b4b5c86a705e2fbdd
+Qx = 1e482fc0f34564c09fc7465e9b28d8a269715a0acf432d9c0514c693394
+Qy = 1e7f42861175b27ceba98ca850c004b9355c9cb0fd2256809f7095892d6
+R = 064b4d31aa645458b4ea811783b395ccee744b493916346079217afdc0b
+S = 03e1b71c660b363335fa738e70bf88459c8d7db546edcb1d888c3308502
+Result = P (0 )
+
+Msg = b95b99ce4039315745a8f744e896671e978e3412a82b14ed6c5172e9010ee31a53771e6108d1aeb6484f75bccb3be3c2e947bb901a436a927e95abad2b46580a0094cb2ff36a548bae67e304ea43bb3bb7779aabf96aa9ed782c97503e5d33347a59c656394424c101b16372995e0cc63445f0c39a2672c638d689c31c377ae4
+Qx = 109e71393c6d17b40467917d1aa9feed716dbeaae71174a36304213929e
+Qy = 1f368b4589e24c334f7dd1e1e9c337cd022fb023e93e263ba492f5c0b6c
+R = 05d7db9502a2204dd7e223cd3e5c51a0650a4bb911586817e6979aa924c
+S = 0652eba54363f84e7b4e33e2aed54cf15ae16f50a41ad3fd85288e13599
+Result = F (1 - Message changed)
+
+Msg = e99ca119d6e061ff793acd1524b8b75a9b4dbfaccd47d59ba271609ac0016659a1db3680453dc938bc16278b8fe15dcb4d8d1cbe1d347b8e9d7b9af12f2b033e4dea2dfe692b7d216a260f658bd43d9a56ce52a1702dffbdf3f09a54b4c0f8a06341cea692cfe8add28ed05c2308fedc428a21ce16ad902443b5f417df4af6bf
+Qx = 1a1e93ca2f3db58e4234da0fb6bcd184b5f23a954629e80c417cd02557a
+Qy = 15e3ce533f8e8e2eec385347989294cf997d5933cc515ec92d3b6ab515c
+R = 035caf7e5257f16a57c0fda70b1373fb7a77ac0a027d847562e4ac15506
+S = 0557fab4d8d5403d3d14527b96dfe258f54f3c3999e8da0763f0ef3281f
+Result = F (4 - Q changed)
+
+Msg = 916114a913f4a7c1a4130dfd0e463a131c327640fe276be0bb65157411358871f61cb3b1dca7935515fbaa9cf5e939ee71f8b43af93fbdcd6722c81fc9483baa776873b8e4099e01c6a69c3db887742ac1237cb0bf8f1552d2a010e5bdc4041c32453b5235effb730d0b07c36dd0b0aeaae04a320fb32a43879c4597aa5b1d30
+Qx = 01d25beec251cca84b0e0d56a1dfea6fc5d94187bc4f2ee53db4a313abf
+Qy = 16aef62d690a8039b7d9235bb097215aa29d751ea31862446d923646d40
+R = 026ff3e2cfbd7e05524a1f1d4b67dadbc5e564871358dcf993caaa689d2
+S = 02536437178af0111366607e566fe463f77339fa0b973c331353f19d0ed
+Result = F (2 - R changed)
+
+Msg = 4df912d1c135f66b275ee8a0a3c63db42e099c3518e8d2f83551ee3dbf719f900020a7166b8bfc2ddf3695f4db7e245886b3a5b0437bf70dbfce272317e86d4540035bdfe898483503518ea9e0ae9a27ec6a991038492677b2133e4c3455dec00a58f6750ec7818629b4e05b4e8452bcc9c32656c4227f769e58a1479c81f338
+Qx = 148ce2cdb6147d1ec50a130ebd852f1c0130ae3f1db12f2af4e1d2fb481
+Qy = 03a0a01c580ba0f7d6cbaa70b5cf68d36a6e75a5172b8be94e0e30f2f4d
+R = 04b03501df0eb75d354a042fb92007f713563bc42bc068f7b0fff0d44c4
+S = 03d501ca9c4932b8d67e3e7d4d68b1df9630318a08c78d8e62816a6353c
+Result = F (2 - R changed)
+
+Msg = 55806df1ea152ce5d418cb8af0bb6a687687347dd909ed855e6053d277d9ee796699d04e997e134dcf6bda95e85e640ca769ea2bae8ae3f512ea9374a45f1f8bafe600be4d9dbd0d65b3f256d4f01f37d8053faa50a620ca0eb7a8b403f74fddef27187fc28260ce20d9b6a2ff28c75fdd3f1d00ef3babb3fe58e2ab0c0f80c1
+Qx = 0e6a13cbcce0dffa2c3fa8713e9ee83c36b0da514ec386eae66d4f4cf45
+Qy = 08ca41aad1a91cb676fb76f66ec7f2126e64d0b79434e5fdce565880531
+R = 00a699bb8b7316a25dc3c0370a06a6f46c146afba607aac352619df0f3e
+S = 002c3d39e7edd0ccd21244d72e05f36e483a36f5110ae483f6ede0ac3dd
+Result = P (0 )
+
+Msg = 4f8fa6cc8bfb0b6ad2893deb821d8385a40983e457a3f6231a64b06f999bbb2d9efedd851b044f3b5d86d3302d934f85aff7931d5cecb31755bea5d5a0a7d3cf21abed663c73beb387904f461bdb3c0cdbad95486d1cc0ebd124ffdec2e451d7fb0b764d3baca7c7d46cf3f6e35d012fc33f409830e083b58ce648f3e82ecb07
+Qx = 0a30e76817366e016cddfc06e03d888a04e609a0f856c6f9c42144a91c1
+Qy = 1bf23bb79f0673daaf443db08b743213be8a85e886dcbbf8acabe18e804
+R = 001555814b37ff61d8f041dce54e6bf19c934b26b0f5cca4f4a4af2c917
+S = 065a31d70975b27185388ee745a0e6fe82b813e0921ec5afdec4372bd75
+Result = F (1 - Message changed)
+
+Msg = 3004d740bc47bb728652491f13af25e8dbef4c2b817d4ad071762afdee5ae020db747cd7407e3f0ec67b47f101742617d9588ad838da53cbc99810a84e020d3eb4d158cd431e2198002b9d392dcb89491260b6da1287be60baab860abe78afaf5ea6e8cb08e23af78eef56209250a64388eefa6f68cb124ba711efb83f0bfa0d
+Qx = 05e167ce05c2045a5806bebcc234cced2169036ffae085e10d08b7ea578
+Qy = 1d07656d00361d294e943fc35862b86d1f1f113f37f8478f152f166e991
+R = 02949cf45e580bf4571e426344cd8984aa5ca8995249f69a581c0ea2043
+S = 0160cc911ac20b5019457bc920cd494d53dc5393738674335b97091dde2
+Result = F (3 - S changed)
+
+Msg = 238e50fb15fb9733705c16fae8d7d88cd6dc1ba1ce370e56842c764229d1ea46c5d5a531e9e29f36f7c8fa92a074273de4c939d4b9f4f5c7463b24765ee19ae6b16d8157a7829cca51e2d0d9e487d3e7986fc3525f88b9135f98713a0039a09d058889cea5be3c0ba8dd241f35d875357981d3af7e63f158e7c2920c00ab30e6
+Qx = 13bd601a0ecf1c480c8c2b78fec29c81f1b578f01e2687d8affeca01665
+Qy = 0727685858720312d347cd3177c3c20af8f04eb370545c14d0c4dc833af
+R = 0476c79489f579087d0f3b39eaaf313e126f906356517722b0844e9b800
+S = 0375a317a2121329adc430581bfb45a3425ed9dfd9b777d04c2a00d18c3
+Result = F (1 - Message changed)
+
+Msg = 8fb281ba15c85d23549adbf554216563b12fa967c496c8357411e647a84ee02b8cbcb9bd83c2d627201ccb3a3fb92e4c048df2bef34d91d1cfcd757c2dcacfa80558032fd5608292ed3024530ceb4f4679a4935e0c174a9381c7cfce18d4e9647f342f10b10c67823740da0f675d1016daeff2d2aff422784ceba0e397c4578e
+Qx = 176dc867eca6a0379e40e7cd78036761918d28d0f662fde3c494fe3b33a
+Qy = 01ce0f6fd75dd0f931313b146d159a12a351ed3456ee6a8dee9d77179d3
+R = 051c7bd7f5f75eb58b87f983fd79b517bd5e8906c4c2ba530cff906b92e
+S = 019faac5b91daa19866de65560e4f2ed855e7ef78394446457c6d4a1362
+Result = F (4 - Q changed)
+
+Msg = aea09ccdf4a2fd1244b42b279c3f9efa3e59d98986373ce26afbe7565c1b157f9f7de4482c67a3ebeb9dab1a982d11c3db26a43e500e11d14bb4d5ff9a24c47a1bb3301b1e605369d279c293f079bccd7196e9c3d49a15d7f0aa9457396a70a8f1d387b9832d2027758f1c3181f9b052dfe05bf39eb74235a627c44569683acc
+Qx = 1b347f32bc29188d60a1476b3c4c02d481387c0b87e8679bcd3930d6d26
+Qy = 03411791dad5b373cca363221995e055631602459a0383e354f878dbc00
+R = 05025488ccca1992d995bfa88621f997effbfe4cb527747c10d70b4121d
+S = 040d94c650bf941f53c49697964d1196533eeb24d4ed8d019c2aa4ff21b
+Result = F (2 - R changed)
+
+Msg = 0ba4f5b6dbccb0c573d878fab677145697647b76987ea85599e49e06afa3dccac537156b849948967847e2e8a4a7c96e3013c71b9dbb14e4fceabe673c07ed95b10ace976e6cc7911b593b9358eca3cf34936baa2e12e94959dc41533571658569e7f896431eadbfbf79394e3d74aa1b383d9713b4bf8539902a1bac1bb6d40e
+Qx = 14a5cba616431755436b1c3d4f5029e8955948a4585868e993c4d867749
+Qy = 0ab95f266c5c0dae603ae8f638b70456a634b0f2ab6bf03a253b80bf40b
+R = 049048789cd370a0596c0acd9c702d0ddaa0469b869e35cde6ac81f7d98
+S = 0167c4c563924123bd227d5fb9b88a35235d5fe5572562e4e7e7f45f42d
+Result = P (0 )
+
+Msg = b5d8094cd5c2ccb5ee5d353b9f2fe39fdf58c7dd258767b9f4d606abc81cfdc0bc30b008ce277aef8984eb0a014db3b5519e85296be1de9b18c5bc99ea1b9457978e80a301a95e39bdb9bf3450d9a824be531d1ee51bb1f29192392333e1c41be178f4c32eb9c47db64f07e3acef9769bdbace9b28b4959ff201167b88185a33
+Qx = 0a72951bae00184ead3733be3cdabec78079914138b834f5449878d503c
+Qy = 11e483dbe4ea1bd7d62ea943454b32bef2ef4b0d0da89cb17add90c8860
+R = 06cdebbbf3eaf18a56298a4a741a637bdaf930dbb8a07486178273eacae
+S = 0623445251667d0b1a61048d549fcec71fed0893f1c95a8b938d43346d9
+Result = F (3 - S changed)
+
+Msg = b28730f7d0b1f28b384b337189d4520a71b32bbc37f6398055b23bbb3e15b3a27b1c5ab40e40befaf70615711fae4f1801ff32368954878f6b2d06f2c108c91f06e7422815f0c01e2c4a973825ae8028bce19f414f401718c05b7a64d1e24792afe30fcd29fb9fe389b3931abb27a4fb60582de71cd3ffc7972024589ac068e2
+Qx = 1148c82d81491bfbdaf10553afb45549e18583f19e7ef92549fb198b382
+Qy = 0d0da8dd592651268968e486485f8f514d7a60f83ea46f6d7091882bf92
+R = 027eff204c5513a868e6d58041b08e162c0faff4d6f3c92f9113c47c658
+S = 06f4ec3e55b0f10021be9f89cfd7146dca2fb5432681ea94d68104ed5f3
+Result = F (3 - S changed)
+
+Msg = 17591a787d5d2f8e0787f4317e0bad2593abdd313bf027584feb4bbfd84a62aae157a0a7c6714957bd8efbbba94cd4f844a9ba05360a25848da6a5c8325fa662823e4d4319708a8d532f2e5ea9d50c9abbf1dbf0dfd144a13ff177778cc6483614df810d814b74d5adb7eeb00490278e489d14209398c6a9f88c89191e92e52c
+Qx = 16af70666405abc3e3dc8d5055cae90d74f5db425293fb2c2a8326eae3f
+Qy = 02f0a5e4dfaa41128a67761bf6b3faed34dc5a2e08a7ac9bbedf674b335
+R = 003b32884f4a90a601b1753380e97c5369a742c6083ee6e8a9cc1860774
+S = 067e429f058521cda0a1c4a1c42ed4598ffba58cb071bee9315d9efdabd
+Result = F (4 - Q changed)
+
+[K-233,SHA-512]
+
+Msg = 50419e9d72795709c8b4ad022d9759bdd75f1d4b8073846f9963c58c7ef95c4c3a4e5cfcae58c7ae189e762606d491745d974888f1e88025afa854c5fa9172bad1890b601c305303a1cdeb1af9a8c8e6b44fcdaf9c0542448dbb4c43f2b88a2423e43cd54b42e015de1f2d74f922efd4f3a6eee9af710763b56087fcfd7ff30a
+Qx = 01c9ec25ec3b5f15d7b4e4c648edec6a99edc2c778cb9fe967b90d639c2
+Qy = 1b6d548db3bbcb58a69b158d3f877f807ebe105f0c5afeabc31ede82ce0
+R = 062025fc1e934d995e085473aa72e189f76a28d2406f00f081c69d5be6d
+S = 058aace75cdc7790e8105db271be8eb7f616c562a269cc7596f6b6a66ad
+Result = P (0 )
+
+Msg = 6f070dd72909fadaf8b877648439a3c459bcd7b36fd57b98e3ca5142d8ac2a7ed86ef744c69e1f7dc71075c457a5db32829d7c8b7c284cbddd7e81d895b900b6521aa8a9f7cb07d3c6e1d180d639408491623e01c8e55e5be64b607c1f1a843a6fb7297009ca57f7640c6da5f090fafe297c55dc8748c5893df4608663ffbe29
+Qx = 0acc739e1fd89ad5f065d0e8c9c533701c6b2de944fe14f8b6e2995fe6c
+Qy = 00a03a032f58ae89e07476a874359cd0c1c04d5793e1b4460310c09b759
+R = 02c4658ea9b78d91832376b83738a6b4f8940dc3435ef7a382130e76d2e
+S = 0249f5ad688c9d211674d9195dd4a3cf0606b8bb5360beae3901828a230
+Result = F (2 - R changed)
+
+Msg = e82008b1fb25ff14278e6674cc72bab5d654065a1fdd19ea64bceb698a5dd997a6da9cf3671881e519cf3c190a9656eda9eea042b5711d42a02b060ff6f28c7cf8e80ed37c1a7fbc428661071fe9e6eebdc4693658798dcf75c01c796991f6ee97394bdd94c609283f10670be4ce9c96c6c2a09e22e78d50a20d851d8ec17b6a
+Qx = 1720bd7b3efa58d14705b46e21f6a1f3eb47bc6aea5482104ecf94d1124
+Qy = 0f5bb8a128d932002f8b10c2a260a110ef3a3f5d78e80d7d5591e6f3789
+R = 058ab365c45488c0bd4c776ffdf3cb8354b6fb2196f062e702ca0f6e775
+S = 07ec979e1d4ec6561666b11417bfa9f978abb7b341888f98dee6c5a677c
+Result = F (1 - Message changed)
+
+Msg = b0a62c69bda964b7f130593b7ea3df7eeec30de6b7ac5f3c011ec061daf1f007edd0f5f397cbf51fc98b4742b82ca8ea07033dbb9b71358f7ed800ce456072204d765c76865cfcc072fb89513bcae46145b51f21951c4580f2c27f9f66d797c57d5f87ae0543e82e9212b6cc2b178199e9362283af27391b5efe5ac2b46cebb9
+Qx = 07200ef032d3e9b502bdf9843fb090d7d5c39d7723c136ada857bbcc2c5
+Qy = 139acd2f37a8fc3a051e7a3ab916ebbfca44ff9bdf98da552806d5aa8e8
+R = 011dbec7640cf52c1a706cc51a9e058b87e779d47491f1913ce54a6eb3c
+S = 02ce5955c8acd858c7a62f845f555bd909033b421056d8f95675620461b
+Result = P (0 )
+
+Msg = 687dd66ed30c077d084fd7ab9dd9073b1a258d175e4d6a576fa15fb47dcf40e7fe6ad31807e536aa8587f0a62ba538d732d5f5bee8133dd2376833a31c349b14a5997782c06f156a54da3dd4a76dce6d0cb685047fbeae682e2b20f1db46e6fe55f4d167127c4f6947b626eff8ec9a150c057c49ea3befba8d92f38621c7ba95
+Qx = 151a77b631a4ab66793965404a61633c136732c3c13da8f6e669d4ad7d1
+Qy = 087ed4476550373713b2669caec70330bff7d158c4bc996ec18b7e48b09
+R = 060dc9fdfd15fa8184d88c7b2bd91a3390417f1ead264f91442b25ce244
+S = 00e6cab05dfeee0d0b823f2e496dd6df1a2cc774508952ff6394979af7b
+Result = F (4 - Q changed)
+
+Msg = 9021b84d81c5b6b68a6fe639f911edf127e866b713b370f85a38445df570d6f466746d0e115e808099839a73ece23511f3868b27d12e3ddf5189a1e6f34e4d67fd2a6260cbd58547677ea2f038bc95cd78f2c7b434819a833e4873c462fb7923bfc5bd869429db03d62b6d40631a9a65a31d794c53646e067d12c7cd25d39e75
+Qx = 1a5699dd5bb437e240ec5f33be6677faf967ceb71364a3371d510568da1
+Qy = 16bd9bd8bd63e37d273b08d625bd9d8854c4ec4f9005266d64e170efb86
+R = 02ba682dfe04a62fc5ebd36e338dd7f09b123a2136cf71e77a961cbd3c7
+S = 045632329f456312c738470cabb93f38658c54f4ffa81bbb83699b1fb8a
+Result = F (3 - S changed)
+
+Msg = 18e4a1bafce9eb4b7d9af67d83b2bd62beaf9648089cb0e5b5ae7e8e0159a194b5cf7e634c7e67d03bee8544aed16ef6fc0415ce77dd8deeb6396648310a4ef6ea5874c0fe925b09b997a37a4ecbfd241cf3a01310e5a3561877d2729651a5f068242ba9395a24b4a6b2f1017163d21d647df5a946bcf8e5ae37c4905b24f239
+Qx = 07a6fe61c50c7cdb16d94d8802776e3a5ce1bfac0d65dc95a3cf8eae577
+Qy = 14f305a067c592b709728a5b103df07ce6f107fd8a2f87fe18610e5decf
+R = 058f942b4596b715790204f39a7db5badd8b136a0fffa23d9556874a9fa
+S = 062154e880b26cc73926859ee7bf12d21c4f400707796a39e15c763e238
+Result = F (2 - R changed)
+
+Msg = 735dc1588c8bdd94f079cd9325533d8998ae3e4fb75d3d4aefc067ce10bcf1d71e281f45f966736c6b896a8ebb87aba66b8d4e19b7ecd7b7914fd9ec87e59d97050041cc83c6c1c5042e3b4019c5c3533e90972910ac0ba0d26171132c7081ec43358cc08472dee6323d52322b4f46bbffdabc6de9774f6b83764d8cf7004848
+Qx = 13957abe32e9f51fdc0825fe23fbddfdf2a8f09c49cc2b3213e7f438e6f
+Qy = 10174a2ae315c673bf3891df35285469c273a7fb4d3f24498224bc47c81
+R = 0361c00996d9ce2e9d682036f21b5f809f8f24d2851894f7ede29623827
+S = 05d489c17a5a235bb4005ed6a48ba4c950d6fb76c76db107d89149fbd6d
+Result = F (4 - Q changed)
+
+Msg = fa829f1417be99b5d66f81c6a703f4d77b0c5551f6c038be64f7e0b9cfba1263bdd56d1c9019f6e9da2f4ded8d8b9a9b097aafca0c96e251fe07c77839d3315302931610659c48d002ef871f8fce681958d474286618c5ae4c8c8e7ee00f18f4d1073f4cd220670b169de5f3c49e4c278625b6bc3d89a4223c52e3068d64cc1d
+Qx = 10a5d34c5ab8614ee0e0aaf706e7f003d3bb27da39b798b415b2394c458
+Qy = 18e16ac02111c39f6b58f8a504d2ee2db5b7ed41592f1ed500ffc417231
+R = 0014f11ea85402e22cfc2765d58c8ab9ad143073512d56fb9d100204c88
+S = 040b3b0ad2e725d5fadf9ce6fd7aa9973f2d020dfb0f1fc3ed27a58f35d
+Result = F (1 - Message changed)
+
+Msg = 2cd96c2757ff2b8e30ed5f933cc66bca306f3167a9e92f97dc15339a0754655277575737bce79d9dc75991927cf00b4b8ee9fb5e7ebdc81dbc03eb965beed1e1c28502d15ba519e58088ff52e9243de460c7ad05aa793a2181e90d7dca5e2d5cef49d8a7cfb8dcd679e7d51cc23626bff5c57333527a0dd9b82926f6a333be0a
+Qx = 0ff665cad5d9c1d3e48e719c75a7c5bc89850150f96c0ad8a75abba9a2b
+Qy = 13d69e43ec8f3e412af94aea2c27291fc3d58e4d35a2af89346c06ade4d
+R = 007843fdb8c0ddce540930f7d68f94949ce8f6ba7637f0bb0dfc24b3053
+S = 0329da532a340669b680d5ba89531a319436b7f58e867b293ac02dfeec7
+Result = F (3 - S changed)
+
+Msg = 538ba4ab1be668fb4291d51d5a682dca33408a3bdd6dfbd0f95b49980600851b7e3b467d4a44214870901bfd7a2cb49c8f16b457ce9bda39a027a6ee286a487b0c377716e94e4c73041fccb1c0e77e06418bbab642610fbb1c601f3d076e38496cc627107487f877e9088cb48e5ad94651ee8c43433d55546b592db4159046cc
+Qx = 1f6c0ca42dc7bca10d1b401b409a3bded8657f42dd2e2990f7f55a3ea7d
+Qy = 00c92ccabdaea6c07f017ae07f370776e02b459b82bfd9a8e5527647266
+R = 0198f241276170a641b1aaeffe65cd1bac189d411d9edc9ca9dea39a4df
+S = 066d7e7f2b296003f307ff388847c45c8b8f24fff8ab1f277e167796625
+Result = F (3 - S changed)
+
+Msg = 5e2953df888db3a03febb6668235faa85f2c2bef4d1292459fe017ab7cb9b604e09410eec394697c0def66edc7977088584d4cba7d52755e31a4af4ab803408ed40b5bf130869626726dd50f7b5aa07825bb456c3521a33d27c4f9aa825388a0d15b2b795f017764e1e90ae17fed3fe50031896b04a74b707914da7437f2aec9
+Qx = 12a26d521adaa33d3a965f5c3b8cf130233494f6193fae84dcba070fc5a
+Qy = 06cc6d06245a504a38ee8ef3a689d33447fdf2b784df96cd145b68845fd
+R = 03fa11c3069107077007b599db904f5e190a882f111fa83d30aef5f49b0
+S = 047b678a0b8fa957a8193aad2336221060cb718846e9aee5af0c9b0ff75
+Result = F (4 - Q changed)
+
+Msg = 21de28d256f05d23cb8831c6968b9f14b6fa307eb10602e8b751842b5094bfdbe26e5fc2cf859a023b55b1b8e546d9c30763319f18a08afa45cd8cf7e0a710449abed39ec1a7c811390cfbc8f970b470359d9dfd8aa10db40c16e73706eeb37387dbbec3b8f19da6ca9cdeb60abd65a0f941931e46b78a001491f8de59aa6304
+Qx = 14d90b1d90fb030d1c5b8c8ac240f7f6d04fc376817ed62e223aab8561b
+Qy = 0b86647b6815fbfcd2494ff7a23e5ceb396deb0579b6a6f650cdaab15a6
+R = 0507da1bde36f568f433430dfe9f18c5d2c5d313ac6c684604504557c82
+S = 034d5fc874d443d9e3f245bb64459048c97fdafde0747d50fa99e7233d8
+Result = P (0 )
+
+Msg = 306d4071cb554e21d1c512116348072b26cd82bb5ddab4fee80fffb77b2765680787bb927e585d2f4ce7e7d56732f6b41aaf518e0faf00ed105135f76342c10e96df717ec4bfb743522b0b75ab8af5d782cf04e20221ab16cafc6ea674fe247953380fa52b3195db8d7d896ae531f27935a868cb8edc2e5b812d9e88fe070fd5
+Qx = 1defa3382818b6aefae77a5af9dc7e3720bc4ddecb940628f418d0bec4e
+Qy = 0d5ddab59cc0bcd2a8b57b4ecbf48b4c191a133d84d94f43f3a0a1e1e40
+R = 0167f6ae2d50f5171060de8d1b9213a32e6b0c770bd07b58984b3f3d2d0
+S = 071a72c972ff6819a0205b3c7c8bf1a743823c34e6595681da6a235987b
+Result = F (2 - R changed)
+
+Msg = df8a05c049ea00015954ee9339f6a281141943980a2c6b88eafe9dcb16d97239a1c92ea8043a31d9abc3aa6c0817f369a11b512dcf72bd8ff98e60c25f773df7ddb9613f40ad91979ec08c6f37fcf2cc02fdd17548e3713ebf17307796e4cf4175046f7d58abe5be60fb5aa0ab3036075357417d2214ecbb801b0f83f07bfa6b
+Qx = 0e6321c21df87e66701d66463df80a557a157e4a63ee9c3dcc93be86bb3
+Qy = 079b6597a59c4b106be91ea7b3ca8fad49dbeab776b90322088310565b4
+R = 0662960710594319f2b8f352de54e806bddc2b3f7527dcae90f2e5d89d4
+S = 0660f34748cf57f95d67ff4eda2527e7d9b9d1d084ae5c7bc17f3eb8714
+Result = F (1 - Message changed)
+
+[K-283,SHA-1]
+
+Msg = f9e8ec5d1d7ef8831533aa90ce70cf4bd128744767076f613e5f4e5e16d3301d10047db3f82327b6f984c38784df36812f863d979e4eee6c340037ce8cfd08af5af4f6691a48ed047ac1fdc5c51385b88bde3876e68e7bdfb10e6bca84106b75c0dcdd08c3f91f80a954cfb3744b9e9668503d781a8add92643e023de7d6eb5f
+Qx = 38d49e96d6c2aad7644f74ca6e3618753f8bf650ab61e8e4864cc2d2728492505d7d846
+Qy = 7e49060d0f8c73d351e95c4e8a693adecd17ffcc64c14d0e01da080f15e16add0fd357e
+R = 128b3ba6f7a39e1a21e5f8c553c911e62c316fd935b0ea12027c5484a3d037a9c652ae3
+S = 02c97d9bb87fc5285b096ec48e20e26acf793a86d9cd33d22d4d2588b9473135db85fa7
+Result = P (0 )
+
+Msg = aff8e0cabe993d750e1113341ce98c5a79f7a278d20db2821a83d7b91922920dc808080a165ec5696f6f1d3ea18bc0c542efe93143b6aa1cbe328500d3cb0d8558707ee4dca2a716dafa79ebc335bde742dce8b817f245af435f948518e2f58b751edf2d75461abf823ae78ea08229d132e7840ca4a3c5510c77bc4d19adedf4
+Qx = 3466fea747fea41728b29faf87a53d14dbba135bada6fc9f46f0bbf7de907c4ca1f6630
+Qy = 557542bd7dbc7ca35277746e6157044d714940a53de0e0eb5cf074523deebb2dd6426aa
+R = 1b09027e5bc0d288a77b6d7f4d3901b9f31634843345946f5a7a731c26a5284b20dccc3
+S = 1a6d64695c16d79dd2a4a23ee645374196d9b5d8b07ed9195d4e43aeca46b45c35280cf
+Result = F (3 - S changed)
+
+Msg = e1d7a8b5f2960e7861923ae7f43b28ea7101d77b0da2fd4e5e709df635211b27ef3c967a6f74d6d73f88cdad47c1d151b6292d7e10ab91b8a07069f4e18a49e127504663ea05e5ded8c9991e31d5bfe8f9a45eef16201d2cdaf2022adb408b52862d902c2c8ad21c2e9c5a3f42773a09d3b5aa3843166ebb5e655b56eceb699e
+Qx = 1197ba1a59872c4d239857a66171e5af94af08af2bf18100858ea3bf2b8a127d4f18aca
+Qy = 32c6cec59a6de103494bae07266f1fbea7e43bb1c86e1ddf01f63207b16ec03cf4d67c5
+R = 129c7533f52c92d929b6bc57b4dd54282bb0b544cc3dbd7a5100c43ff450f77e3dd179c
+S = 0681c3ab96fd49ca51e1570947795e31267432648c31de07331f118919e63f9ee12f9dc
+Result = F (4 - Q changed)
+
+Msg = b333ba8ebac1eb5c0d016bc2049e2a73b546ae0ce46d3253d8322f9df7eec6a019545791073fa8daaa3fa444c83971abca95cf372524f14a10aaa4b0ed189fd3ac1c01ab99af71fd761659d097eb279362765e9cb128a76c71553d2478199903ffcd2571008043ee8b0dfd0a06553e76fea38ee3c7dfe498c9d413b2033e47b4
+Qx = 287ba1e09453dd0a1b1febe2d17bb2b36cb8600b213e488b1c5ac560159b16248f2bb69
+Qy = 30eb597ecbff205cc276d37e96050da7fcd20e4ef9e3202ae383712eb1a0b7c838ae1e0
+R = 1f51eaf9fa4fb2a3b5afa5405915057a5a4053b9aa81f62741e10eaef49a655f0ebaf38
+S = 1667ed9e38af86602274c63515a463ac7e93a68246824983d6885661cf26c2b228890f2
+Result = P (0 )
+
+Msg = 4b1ae21781ac92595bd7d77dbdca50fd15b556bf451d5ff95d3c8b78b2e7221b7e94cdc975070778f8948df011528dfe42c2b39f638019d3ddea0c096466e55e70947fc0a500552e8fbf7b9b4a20cde29f3481a2211663cfc9063976d65401f81c39bec31480572fc2e1103480e9fad2336e87a6ccee6cdfb96a20168762ec8d
+Qx = 3fccb55f406b8dd8ef262ea045c3b3d07bf75a02310577ad6cce68efaf41adfe5a57999
+Qy = 777dd5a1a1935d79b2a1f3b84ef3045ce8a4894e738a10fa72539c268922bb3c9490b89
+R = 061784a4ab614c2ac91c7819f8ce3bdca6ad51d20cab3c14c574164a8fd53e5a90da88c
+S = 1997ff2b99e708524087782a9185376ea4665160437bc71fe030c0fb6c2a73343308729
+Result = F (4 - Q changed)
+
+Msg = a8f677a27e87c164b73e595f8001490cd22abed242f31c699258a893fb7415077e61cd2d0fec14732917037c5381c45074c1231096a1bcf799351f95c57aa6a2e5fac2265970c491e791cbc11e0a74159ec960def1a8b360657ba9ebae061a69d7f83e9373ade4cadfdda866a1c0d4f39d0c7f8fb1deb8dffbd4f0453d814a3f
+Qx = 0bae5833558b1c257bbbee2b4350e833cb7e638db39debacba5cf2bae1856e1b936ed49
+Qy = 10e4b75fa1cde7bd71e09c60ec8473038d6a467921cf0642b25fe1f4a548440394d661d
+R = 1e57976f27b0cef9f6ce04c51ef33675bce2e36e609a0379f61d01c666bafcc0e69c852
+S = 002b1d115db34e59ca6c9f5d3085210781a411d0ccb9748dd3c64e801d57d4d78cc0747
+Result = F (1 - Message changed)
+
+Msg = 7110b0dc2b3c8017406d60f5d37d8b7e68c78831e2dd80e1e3ff31881eaecdb990126e8101c107917669534efada982d9fccdb0aba72cfd9ccc01a439b889027598cf51850c2ddcb487821372d6e3b3fc55975fef244617c60c875d80cefbed812bd174412db5d4c7b8f3e0c1e0f6d89ba531524c17177b3d0f7c2df14efcaed
+Qx = 348f1627eb182024fb8fe21baa62c7e97e00be97f5cf55c3a5f6c78b86683cf4df542d5
+Qy = 352bed45af0fbb902368df7007a2c12fb729fdb51d740dfa1017497fce9c782880212d7
+R = 15092ca929e97eda199af29ed55fd81889a26735ddaae990a8fa0db751731cf2b7f0194
+S = 0fdd2fd8e9bdca2571062780eb5591f30132f0d49f45ce0b8cb7d83682935106cb496dd
+Result = F (2 - R changed)
+
+Msg = de7f8cb78f95fadb78277199e07c301d5b223bb0b3c2949741a1380e2c56183f879f193a00e9c851994be6f10e6587c6cb413067405ddcb5185d3213b7518307c991e36cc09859d618905abde194fd2c2e69d77d69934ba6d8070fa9e7b03fc7d7d61063cb768a120daa59a638b69477674d49902521407da5e6eb390097fc00
+Qx = 1fcd3a381e7e622d09142ebb2693f77cc9ccd6eba855dc22d84d880dc23bfdc367910d5
+Qy = 06256c6d6099a3ebf70a35f54601cea7c5625344c2d13bfc78488adcf0252db96d9cff0
+R = 043224ef2c07e706223bb8a41e58d12163762224a23caebe667e6f52955730cd2da9787
+S = 10d979b06638d5147d309d0f7dbad54ac06383518f607919b36d345f4418c2e35351fa5
+Result = F (2 - R changed)
+
+Msg = b6b066edf19e0838fc826c01801c28ca8d2f7150ff05c23cdee74ebb892a65eeb057184ab21731882dc8a89eed21055f19ee4894db91aae0922330cd401afd93991c9d5888df2cf0bdfa4bfe14e6cd1bd1b057a61adf7777e0a0cd2f25f4461d8ded62f6046a1f32d2fd7edf8a19ef040bd71eaae1a1ba4d61d209f8e5d00a8f
+Qx = 619475438f90ae1954351ad8016c4da97410bc3a8eb06b4194dcbf0fce66df0223acbec
+Qy = 1899f0bb6e2a41affeed5d3e6b19c99859e3ee86aa78caa38a9512052b468c3f1bb4590
+R = 06855ac7fb72e285442123e97e1344828b991f0dd9cbb369bf95132b4760dfee74a9eff
+S = 10ba241adefff5ee8a1fabdcba192fd4cfdaf1f564bb62eea98c5b37c7fc9621162bb35
+Result = F (1 - Message changed)
+
+Msg = 841f26c10ac5e75e81fdac34431153bc0224a7aa2f5688df6672693d6d2d847e3175dd46d11414e73758ab8c26296785eb7154e3b4adca8b8573eb38d2dd2540a70c67e03f99ebfa459540b7d6f06676b04bcf2c8a9e34cf59d3db4d93660edc729fec31f966aed4f40cd747786e5bf7aa48a06bbb0f37ff929e8c264a5b310a
+Qx = 050438f9d67ccdf28413ebcb829c4aa000fa5738bfed995b15e7b82c808d1fb535fe358
+Qy = 1a3d0f665dead14aeb1fcc63d7c28720e367f6fd00a529803806ba37b38d67cd7ef73aa
+R = 11cd5ed271698955c80ffb8351afbc469cbf38e6236e101b81f7ff5d08409b174082a70
+S = 0113e44ff734fa6388e07e4f6ead43bf045af2c889b2886b02b23aa6b8558701740017d
+Result = F (3 - S changed)
+
+Msg = d2d55f98240ae5918c1121f18de550a3aad7377676105d287a311d80d59c660ebb28ea2d1c58e11d891ca1f79504fc5b697ac5d52f1199938281f07f7889504e8a3ca843a5c3f81d716f182fec227d5b349482b051de4f613ecf76dbc9f7c1018c9e5f8b347eb128fa6349091138e4716657258c7b961df264bbe6bda46f51f2
+Qx = 18e9f05f501c117db1cecefe444bfc2e3feeeb6df9e1517c3751f80e345189f0a7518e9
+Qy = 45efa6d2ada522644f9b4bc6fddd4a7654cc01550201a5e8db7ca5269086ce6e7bc4cf6
+R = 1398aad1628c4157ed436f27b3bddb41bab8eaf5c4d6b3153b019389ca210374ad301ec
+S = 0046b8c0d5164bd7efdb4618154ea2437abc825f7eb46ce6e735d56621586d3ee1ce170
+Result = F (4 - Q changed)
+
+Msg = 09dd973543e433dface1642c147aee29878fddc99508599a78b108e622c2d5da46716fccafa4c82e101a565ca0f04a77095b82d9a1c8324a31e7a01d104beae2e2f4cf144dc07a5fe547e25455bce5036289eccc673232385904c7ed69fecbe7b14100e8a63280f427419c221be1804411df4327ab50456dfd408d45af69cdf2
+Qx = 11330187b39d066df8ed1911906c0da8d17701982c63c802005d6fff01d896253d91e3a
+Qy = 1f17b2962ee886768d68760eb405092a20585b098c79c1274e3346fa6b053590f002e6a
+R = 19c17d27f9646a3fad858edc7e20913c19af4fc6d2dc025dfb9c735522ebd9dd338a7a3
+S = 0e2239027b2ad9f7ce318916d1a440a7796c0c4398981bd78a0d176b73563d3b183c4b3
+Result = P (0 )
+
+Msg = 44556d5112165beaa5134eb0105225c54358a018a0d09ffefaf7ba40975cd50f6d26ac79deaeb392ac4a9225b9e134ec358220ecc3fcf5af7a2aa32b84bed8950d3f70ca0161d0943a103f5972fbbd63e64504976aeb6c5b07b0407a779cd19d79bd18e634679b8f6cfd6d44ff83f4994931c030c0581187935079e360a53a4f
+Qx = 6a53dc8d80f0d57de6630f043a4f893145a14e23e4e0dcdf77386334c06c93e29de9d52
+Qy = 495e596bdf9b8367b0400379dbe5bfd4a65cb7adc85910e01ea5d3da6c3fd08e0789ae2
+R = 18389318a4359b4bdce4eec54d1191919e457524adb2dd1bc9cff21a5a91275bc40a32d
+S = 0cd0c8a895d7420c9947b4a1398323bb1c80a49cea0e79e64209fd35fef79a10f2a11af
+Result = F (2 - R changed)
+
+Msg = 02dd98f15a5e25109ad8d3a3feae06e1dc168c11c83694822ba58008030db0a3a64c9638fdea4b9481fb0cf580fcf8f7b9efc8e81ca37435dce84d6bbdea7c74095a90e64e84248a889916a42ca6565715de6c61d3432e7c18405606a84884d8585959ad2eea735a3dd219ba2ecfc3c2820c94e1b21392679255a84ec05b35dd
+Qx = 3a861ba0c865233b145e614fbf0555a5d8d128b0cd802f12c4317212366de4f5a3c3a6a
+Qy = 0057749cf0421170c0d3bc0f4bd9e89ee3141a662f1c0ebb8e1b7d78ea1e7fc8a24856a
+R = 1934a27c95593e74c8b10471baa30055ec4747cf01ebf1990cb9edaac80b5f6647744e3
+S = 13cbd71d15e7f0e2ed4031f49b52924d3976c1e16e85767c3d16ef3d9da6d24aff77813
+Result = F (3 - S changed)
+
+Msg = c6bc2a1ac8a20f487d8184cba8323be24af000ea703314a4b296ae50cfb4c705486c3e7f6877ef54e2171ab0e48601f0ed655086edd42216c87db69c84802d30590e525612f9f0f03756d6bd1f43700375e0671bff0b745d64161d2e1b294a8fb3044654224b4a528eb3469d14b5856c47a66604211fd09302e62a6c232bf545
+Qx = 511854178a0f8302ff4a181d5cd8c2929f2a26f39781add4db674ea32cbfa3fcd7b95b3
+Qy = 4a1d8318d11a2e096b2b6d6fcdccc05ca6aacfc5f8ab601bef901d89ad9e0d2c58f6655
+R = 01b6b377e8b2b646fedab1e7eb679314b3c82bef412a7982bbe73b4519464aa69d9f0e6
+S = 110e40c5f18f2439d549c8141070f24bccee198b0bb9633cd0f3613bf1007823dbc03c2
+Result = F (1 - Message changed)
+
+[K-283,SHA-224]
+
+Msg = b1d9ff0e0371c6b63b37c7de4324ff55c12fb63a7b22ed148fd9b2905d272b1095e4249a40eb9640851d589cb5a5ccfcd4959d967a0f985059904bbb832db2711afb8bfdcf3b31ed6614eef91792b84452f3211db00aa5a2a09aebbbeb519391b965c1591fd6308b684bd630d585d46607705a2b279a6396a8e643b5bbbdbbe5
+Qx = 2236dc88620c626644e1577302521da2a0c216495cc3f7b76050ec658eac9cfff178cec
+Qy = 7dc546c57e63eef7faa541789f2146a687f99d8ebc5a64624073a1f7ee07cb299f93419
+R = 0e159ef5c6f0e8d5927e6d9686dcfc6123283e20f0be0ff1ae444c0eb15ac95404415a6
+S = 1e6973bb227114b684c5c539a12f3ee8946f89bce40df378b99641a80bc963509724748
+Result = F (2 - R changed)
+
+Msg = 956c593e5a0a26c2900a2c7ac31ba2cbc662dcddef96cfa73dc601a2785170d9ea7b930c684b81c8fe5863022230c11f64fadec7762c8c21ad7e5dea5ef0bc3eab7f5f6cda5114188123a02cf08827e107ba989583bc9d7d5cbfa8b2a0a651ca40e875b1f6bf9626ef61e6b1b6b52ee7bd94997f1f3a04df39e398927d3bfe6c
+Qx = 600e9f7099d126b23313719789ef878ebde0e1bd60474d8cd20b5a50cbde5eb45029177
+Qy = 0b82b914dc0664656a0d939221166b8bfe083dd1c0c8585afc8e659b5cea4308a617e5b
+R = 0899eef029dc2748a60bd591d577868e69e1628e3edc69499a177eef0e494a2d4d72a62
+S = 14a55fc93974a1e80a352da3fafa708f42d802557583d5342d8d379246900cfe1724887
+Result = F (3 - S changed)
+
+Msg = 9b5c0ff0d126c57d013156243d2121166c6bc41b800cb238029ede2726734ac735eac93743464fe5e4496b287a8ee2d4b21c01fb6f3b7c451c3d4e035ba963794e263bc573305438554025cd0459b664db449ee88ad793468e6be04ab3b4d5134806c40ab23a70fbd53de0f960743303c983f869a2ec9f6c8ba557b3647ad0d0
+Qx = 7cdada7e3e196e29f80dcd96cf40b6130bef40d5a6b12c7362abf88e94b68689ca02cad
+Qy = 63b82d5aea6c226f76748bac7df07f7699ebecd125edc108b38b0a7623b728567d68382
+R = 18233532522daa25cd165e5904fcb43ee83f3382bcb86888d6b76569c69bafdac88cf2d
+S = 13935429630c007cb3a90eeda0e133f246f14ab5563af099fe1bec2890c3e2bbbdd999e
+Result = F (4 - Q changed)
+
+Msg = b32623a81911b1346d40aa23d1821de3bead78ef63f269ad44a137f53db17f1f311c82055646f306d4b850be8cd2cb79938b13768d70c85e03bb8782d51d8be0fa5797761f92e68421067bae9c0b011b7e28217575e86d53b39e6abf5ae4184092be0457e2aea9e43cb42edd35ad68420326914f0f0e9a5a652b6fd1f8ccae75
+Qx = 1c67e69ca0083e4f6eecfdbefd42a6fcb8c92354bf645d7626165b41e0b40a1fba28788
+Qy = 1167bcea83b343f37809dc6118587a5ec7ea1a0772a0cecacd98155733e26461add7460
+R = 185ee266ff5a5db751883c40f39a87d53f385882b93cffb93a9cf45cea34ea6608b47cb
+S = 1fcdb3313c8807c2856c366604efcba090b0213e550ea58b36b3d68982aa3039187b018
+Result = P (0 )
+
+Msg = 6610c6914d4a933d96b66ec019bdbec21d22eaa78b336732c958d80e650b6dbfb3d735d3bbe3546ec41f80732d69b20493f0aa9a7086c8364d8ac39a286df929ba4f100cf5ae90b3247d8a5521af4dbac4aa2a35676b30d85171b3ecd59319999012c0544c94c3c694d9c2e696e572c32934bdb91a71cc643e130438bb23f67e
+Qx = 00635564f4fb3ad2052a1a69ede425d87b45771343ec1c0bc812fd9b32bbf0ec38bb95a
+Qy = 1cdea0b07435c1da24d0535ed97b505cbbeb6f2db2e88d07de29b7d7f0dbff14d7ee5fa
+R = 1d1ece23e99c30bc7d2177a716940225be7a5b7f69688b09ca67a54d56c3b31105b8fe2
+S = 1c11fc902854c79e308da16c68cb6610459f3567572f2db88656c3c28b8b8dc24a7ce28
+Result = F (3 - S changed)
+
+Msg = 8e148ae01943a585f379677da1517ac1aa6d2d39e9815753daf6d445e0b34ec1816c18f78e99bcae899d4f18b96b1223fbfec20dc753b1505298f9eff303a12d2542fdb1766602db0664b660f917ff8dafccc0dd92d161a3a7d3db2c6bf768a292bdf5149f7f596f4bbeef93e1cf0811dc33868b64c6087c9b3b8658516283da
+Qx = 729143a34efef53df83129a7e8865395bc8a41eb8adbc7e06fd744833266579f9c0a952
+Qy = 58ae101c470418208b4291d393f4e0ece17946bd0d8dd185b38d6b4a8ecb609ac647b79
+R = 0d83a64984d56cc5590764d4c9a00047daf69513265b5f6859006ef6200a404e613d8b2
+S = 1310f4ae88e47253b25a958aa22bd2f212855f77b56afdd23b739f6f9d1173e68fbe171
+Result = F (2 - R changed)
+
+Msg = 173ac06aa758d7557127f7aa8cf7f07af4acd2843462a683d3f2fe06e3483c1459460b4aa270170e5ed7c0b8dc0c83e36805d0fe67a9dd6f95f0af5ba2a8647013e293e246cdbd42eae71de569a3e302aba9f648cca1f8b79569511cff42b404315b1d329dba0702cfc0fba9ab58f37e63efca43bb6f5c9afb676c5c5480d585
+Qx = 7af6c0da0630c18fa0bfe4321d4f3cb8af83a22ba65dfef1c62955ba9366ab7871f87a0
+Qy = 480bb54124eabf57ca5564d8d596c9072d8d00b786436426f7e919e307d926576dd90d4
+R = 1021f77d3318825b475b83070c0fd6a845025e5ea1021abfe95c7a93ad827941ba4017c
+S = 162bb904b77b02f617a81effd334a627f2d81a2d0efc9ea9c1de05336183dc633fc708e
+Result = P (0 )
+
+Msg = 40ca7e16eb860bbd71c7ad23800f5c6a574dd332ddb1e215c8c62f451ba06a2332d71f21e3bf5673fe54cff3f68c7c9a48428f09958e5b990bdcb1c5bb0c781da3792f48e6a55eb01c8aba08abd87dd667f63a9c47a4e055adaeb0f8e7c62fd1847a48cc8e158f9d7d36f0151cd7cb47ce48351bf493d050775c17db4c315f48
+Qx = 39e5ace44ca8801ed5bc4ad3f7a5b520cf5d502aa39ef75ced001f0fb4ad6a951934926
+Qy = 6abcecdfa8c77173da58246a5af5405b3435c96501814b2262ac16bfaf0fdba4dd59110
+R = 13e64cb199307f6faf23168694356d997fa44a490f576bef91dcd9a1d20feefe9bc2050
+S = 03daf86a7c0e1a1f91727dcbc9f221d9941bd49ea051394b207cb4998c0a7b699895033
+Result = F (1 - Message changed)
+
+Msg = 755d62b1e040e605325c4eb749a58419c9d5b422264874089ec1133e88c816f0cf44e76a7da79c5600f06405dc05c4788704373dcfbbbc853acb45af7868f540e561da29e397507d13baa90248f9bc3b09352d4d071171189d8bb0cbb7dc8a7e854cc2f020f94e320f7ef89004f5af38ec2ef20a790ff97c9469af8b16581cb6
+Qx = 17c127419daf4beb059fd0cb633995ed271e7ea03c22f8fa9d73be3aaadc0492b19a932
+Qy = 3d1621a40c04098d40535b3a45f87384bd42b96d2b12487abd89378afe7b4a84b42c28a
+R = 1c80dc4c9f777e7c05cd451cb4efd270b3dc828532bb06e51f17246a3f58e2ac42c7ca6
+S = 1adc988914cf9cdc1bb4390b20d1d3de53dd6ba396e79f766b1fa330e589bdb7d7ae8a6
+Result = F (1 - Message changed)
+
+Msg = 4586865318efc99dcb05eda786a64e6c63a28eb6baea7894ab40085fe089719e0e1023cd95cd2b50433d5c05a1ed5b02b57b35bbf50d1ada270d29da1d706ad3661e1dec3347acfe1c77395be373a766dd71f48324ca8f6ee1798ed5a692966b4ce7d6b323e9eddb43f5bde2f8be49f795f076360ed8a17b760279e92624e952
+Qx = 40609f6d837bd868c99461a99840ad0567734b024ca95592207c9eccd7e9cb49cb8990a
+Qy = 162eb4cf1eeb48620a9f284c2622976adc663f40c4492e0b895849d78271714d699ba0d
+R = 11cbe4a9ce3b05c8c8d1ed4c7870c6f076ee4f6b480f1e037393d44e9b1095a16838870
+S = 1a207657541145db1d79ae167e9355c2005db1b3df3d9cc0b3096137a59ccd6ac2a0f2a
+Result = F (1 - Message changed)
+
+Msg = deffd202a7df76699bce6790dc4289d21e61b849a154f872a8ceca7035a3c438d846ccd2be3eebca718410f77a4370b37ae6f7e351e2cdb9dbf69cfae6f033a3efe1e87d27cf12906a266d440535529f4fda7da0a3a600946fedcefa3c3081ed5edd841489d8c76d3dc7a04867816c9c0ee60e620cbd043d5af92570fe807110
+Qx = 5fdc6cd42e13cf5d853651993facff3a7aaa64b17840e14082b1ba2ffe360d5624939e7
+Qy = 5946bf632f36204b21fe70ffa83a7e9c8eff8e20c19941b54eac3567c03fbbc3161dd52
+R = 10aab796849a26f96288a4729f0aa9a8f78fb23874f9267dd123aabcc547b65fd780c30
+S = 0ea6a8bb263db16554c227bd5fcb16385605e2851303336717473b12c832a74da6e94a3
+Result = F (4 - Q changed)
+
+Msg = b8c166a9dca81d5f81a0f6919823ff2e8490979a299558282c6cb704f8bf11e8578b0bb995ee9188ebd67a8f2eed82a1f01bfa4b978c67a05228f2419067c49318bb0c09874d1b1a89299c4cbcdba26bc87247bdf183293f5f47f9d3f52f1f252939d2dee29cd61912a9917169c9280781d36ca85d971d60a9aef90b74d13a47
+Qx = 6272c5749ee8dc1b210b9366d8ae5236df359b9ff071d8768dc01ce23eb50869b933fc6
+Qy = 3ffd36d6da3638506a2c40784ed6f56ced899331322fe669c8d81be24fb89d22cd80cab
+R = 1dffff13f0ccaf9104163c1a573caeececdf315560b631c1306544f312488fa4d0f9fa0
+S = 1813869f51ba5e5cab6cd6b5047b7c05bb9f96aa7952ca8d70b77ac16bff60d2297573a
+Result = F (3 - S changed)
+
+Msg = 902a2b1d8e4ea480c52805bd44e820d07918113e19aa9801fdf3e0d97de67e7004cb00fb88031c7d341d4ef9daad612d530bae9b3044659dac8850b7a29ac8630349a11293ecd55a7858739cdd34e80766ccc1bc61e97375b75d674064ace2826085cb18d400c4cfb790b6d0445b176bb3e9214e9644f4e2200d0a62da7e0bf1
+Qx = 14593869caad01146bf5bad5c9563c9261bdae0be7a2d9cf745089dbdac958802c96e61
+Qy = 6fd0fb2e3f7ad43d4a03c2f6bfc47beacf40e900463f4e05607684fe285f3b83e2eae24
+R = 0de5f5d33c44c31d11f3544c40bc2a0b2981f4ae503b58c1b4a60bbbcbbf7b9552931d3
+S = 1856b7b85d2c36632ad508c87c2b3ea19a3706a1f0bfdc797ea9b5081fe786bb8906ac0
+Result = F (4 - Q changed)
+
+Msg = c6c9cc3f35843e6f035d5722a3aad3e52364b2b08b26643547276072ff489dc31ff1fccd095f284ce95954ab4eddc115b573fbaf2456526077408cd08826c986e2abcc5ec6a61017a6cb04935f948ac693f2a857a1617942d71bf849841657f386f6b5f4cc768ee5d4f66f03bfafcb3851b6b07cd11039bc917bfdeeecd8d1f9
+Qx = 3c9f702d771985db453a5c0c930458fba25b5180a92392fd8d5f900d1f53f36456ecd89
+Qy = 56241254dbd654802a35e5695e9fb7463d4903a610cf0e2a02696485c2691b2d59e8f62
+R = 0f4a0b6768cdbff071b8146f31f1ac32b5474fb9f711cafba10317ac664d7d77bb99e1f
+S = 1fc8a57176e09fa9d1507c18b5acc34aa412b04f0709433aa89b80bf376d65c37cdc3f2
+Result = F (2 - R changed)
+
+Msg = 05b6bac260754da6ddbd635d36e3d125a6dfb7e84b8823d09268c7274ac0021fca86894289e3df1fb4b8fadd1d462700f4b79e0493dcc244230d203160ce7d4b5b73a4571642e4da15affbcc7428a40abd79c4e45ea6fc835d549b699c62dd642fbb2c8f84038a14d69f76f4b31ece90327001a5ad7804d5a25520cc6a77d799
+Qx = 780725b220533772fcf564c3f3bb3723b3c8e85c4d544ebb995d809ffa42c1457598ad0
+Qy = 77173d960c0d2dc1ac1e31688b918c6d755fb906e76420c38fb9d3be7929eeaf72c98b3
+R = 19929cd1c8be4481938c9f7475e9ee831d08b5c048591957ba7dac6c7bfbe60c4a009d0
+S = 10f4bfdd22e7dd452d5b9f543c8f00449054e6932cbaa22fbf3ac9600141a24cae448ee
+Result = P (0 )
+
+[K-283,SHA-256]
+
+Msg = b884abe9ab8cc7f80022a1883e49c0a45a7d2c0e378ce72ac6dd37bfd05ffe69dc8b815c41d63484755827511223ab1d1302684bf81b1f2356263e06138f9a2e341a1da5b020a8a46a91673bd27139ca9fcb2a355da5ce2412c82fb57d9aad1742ebc09b4b3ea1509715fb7787f72dd6523a07f54c4c8a285b3789df5f882b7b
+Qx = 0d7e249a93742faf10bc417a71d29ba5bf2c64856c1c1e82a033b8abbad471d1527e123
+Qy = 362eb55cd5b254667a165af27c6f1ad8ceff78a1d3eb24227ab16c02233aec7d055ad0d
+R = 18e914222a04e787c9fb971e0996460358071c90e00fb54df79a7ca4130ce87d9be5558
+S = 16d7c46ab425f49f2270f31e2584fbe0c23cee2d8bf1f65112cc5838d8650a49d39b2ce
+Result = F (2 - R changed)
+
+Msg = 34c261c3acce0ae5967f0fc91bdeca732fe85a5ed5bcf407be74838dcbd59d69a653ab606e642329947555817ed3f21135c5a750e1f98a338c800470972e4a1f86052a3726e612575a8121c1c0b401cf8637c37d440432bd2b34da292a6dc4a07cd2a962ecc54c687250606457a72dcb2c760fccf92e694468f07920563f9c9d
+Qx = 015383b920b5fbff65b08563ac2daabe757e36c0179ec9cbef4232ffde8faa3b4e4be3a
+Qy = 5771cc9aa6fabd6846d9d3efc2a6e754791028e1555f54f1fbffae77d15a8c019ed4dd5
+R = 059f0f77452464478a574a36b419317ed6e1cff78501c10caf6f705aed186bb7a17c72e
+S = 0d408f78e5cd8449ea389e571f3f76de98537e61ac66308c4788868e9fe0fdd6bac6a8c
+Result = F (1 - Message changed)
+
+Msg = b3438f656d29417f4427f55020e9ed455947314444fc90bebc20f523e40c59cc7d4caf48b4377dbf339a9730476ade5e779d38cf5002abdcef4725d8d367d9dd9823f189002e0e869dcede62983410162df77f454d0b6b59a277f0f419767ad4dc7672d754c6fbedfb4e51e4e2c73ea40976286f94a0dab75b4135180e2cd732
+Qx = 2d1c51f3e926f347f56df45f0ae13f1bb711daef34c3f8cacba660e3810c34061899429
+Qy = 1d9b743b54b389fa01a14f80ac2b0ff587fdf200785a63199b83de0b107830ae76d932f
+R = 1186c48674b431b7e8f89a14772add063c7610f03fb55d1d89cb1dfa0906eb63038ba25
+S = 19929947b6f44986a0b73b06dbd8c872948d724addb5a04ffe8c12e8394a8c2ddf8acff
+Result = F (3 - S changed)
+
+Msg = c566ee609212dde2ed2084a1978f6766b703cc033aa8fb4c707327fad41372a1defad4d5666102f787592bed342227d4130f3fac6a6ccce0e883f43893019b1286b3c11f3cbe08249e86eb0818f692474ae01646cccce3173f9ea66f09604dd4b15d730b0a51062f77ff106d83267d7aa38ac61c99c2397197b39da8768ac178
+Qx = 68483242383ed4ff57abaa6dff858e24dc217893f7c4a798169cc77a58f9e2c0146e5cb
+Qy = 48914fbcb7974555649ba45bc230c03c625734c21fcdfaa980d5bb65989f19460e2c0f7
+R = 0593129cdeaac4e04821d15bb9c0c942d1a3b27d4d29663308ae807561aa7613279eb3c
+S = 1f65d5995f000075ddd2c9f858c9efaf8f818ba0780bf0c4de7e5239915337c14519969
+Result = F (3 - S changed)
+
+Msg = ea2bf1062045fe799a33ecd899d0e63598325d00400004117baa99a90ee63f5eeeab19e5293fb2e5ab9c23f4a585430b2cbdd91c26cc4cba0ba4547dd27b6a730a5c0549cd5f1b5fac8aa0022b7a2b28454d143411dfae999a137b11ecd68d303abbe625c679acaa1d54488a336eb0cc9d1758884549fe10c37cde81c5b69fd7
+Qx = 5176d69c610481c8d49b06e517475da3940c9e4270e2ed9821ea21f4d96297fb05f39ee
+Qy = 79087740a5925602ae7773d1bca9cbb5f824fb1f5791f66ca37e7046ad39ee50787ecff
+R = 03bf4c5c61f95b0b5e298a91a3b2e2dca3ad66340696c608d6cf5cc22f67e1938bea8fe
+S = 049776b29390c2eb64357a920088001b47b74a514121f693971f657516acd5d884a1851
+Result = P (0 )
+
+Msg = e967b60cc05f56974fe9be448396e1333fc5f3cbb8977b09028cfb6bd1341f2deba7c94f537f994d660e73253f87fdcb5286a4ef7b682a92d58d5d7d13e999ad597acf313f54d594baffc94e41a50431a175dc1e3219fa05ab7c4d43bff9d035c47d1c1f0536c1d1694a632c0bab6865c1066235a2afd690decd22608b67bb50
+Qx = 6e0dc4abc31d7ff279fe26ac83c9e7e6ed185abd7d000e348e63c0c91de95c2a6cc4d65
+Qy = 6330d3d6859bbbcb125fc88d4d1a0f50d57e40a128979f5fbd261df1552abdcdc65ade5
+R = 0b6c837402c00272d0dad9ec9d01ae1725db37d8aed07b8c3fc99c019b21dc7836bef31
+S = 1f3f6f6966893bb5a4645c87ffd4e89cb57932fd223c5e2653ccb27837624a29d550b40
+Result = F (4 - Q changed)
+
+Msg = 4d3f69430ceed38003e0e1b70a7b9bb1c5fca3a7010d8b13e4db02433f5850608969618d3a986010cef5be77fcab263db0131ab89face589a667e81c3fcdedd3d9ea8ce04e512dce30fe8ada46a811456a1efafd87a9a215fe40b125433a62f639f7e95b40bbde84638e084f6a02ea367d51ee0128f4b5f0c0f03b26b551fe77
+Qx = 36fc3ece725ab5e4529f92fde8d90b89480fbd3e76e287f91c85a44baa49fd2c74887dd
+Qy = 702bbec9bb279ee5d20b15e7b9c30192fc691136f8eb9dc6fd2ab4af20492a30f0ee17f
+R = 0e0733b88093dc7f0a3e81cf14d5d796db69ba02c1d3fb7e26590c709dc426f2c008824
+S = 006757785f1e55be43069d37884be11c536d90199a8c9d2d4c0b3b21e646a13c7fec1b4
+Result = P (0 )
+
+Msg = eece425dddca21aff6f2e6bde513d762cd47f3c26a0a9cec1516e9d092b0aa576431540479ee8be26a73d244c521b7844d7647cb6adf837047c2dfaaca4d3183ce296bf2d5569118167342b0dde8ff822a1ccd69fecc1cae1b97eb054bdb93b6864120a6ada5e7e4d07921d7af090f89496e393dd206ef87b45c133ab5b48872
+Qx = 53ca497bf91fa1e10a5f19b1b1426d39543ee9f14a004be255777b4a26b007dc7113829
+Qy = 0aa5c877b89c4744a9895ec9238c561162808b7bcb0a6bf574a16c6f7e1409f4a160faa
+R = 144946785be2f3afeee93b77711a7e52b925281687b41bf79f7404485bc7c4412fa39a4
+S = 07b315403d7d8ae6b05c64fc115a1e44046f6723eff5826c0d9759118c2cb0f50235437
+Result = F (4 - Q changed)
+
+Msg = bb0e561bafb490c5d63a6800a303b6ca2572008834f424335158c0364417f0463ad5a8bd66167f3d55e10dd521fa40ad5b507d1948a10db7666eb08b4ccfd4caad9de5ec5ea30fed0c07189e368ffa4ab184ec0221bb7801081588fed70d0f1df1b224740816abf931c6afef62b243c5e4115d94ce59f1e0072e376ae7bdd072
+Qx = 50da838370155e67fb241ca7758ab5d778f74c9b9c8a9b7a9bee8abf3791d60ed644801
+Qy = 356b8f8360ce542710927c7e324120aaeb68d378e732aac99b800c4ecfa7f4a3e050d6a
+R = 027e1209c65a19dcb158cc8124e2bc9af6d8c2898c6863cd0e59be054d77786fdf83187
+S = 04182873c73f84e8aa3744f614af11c3cd86f105095911548ddd20b77f744e877a57f8a
+Result = F (1 - Message changed)
+
+Msg = fb2807630505d6770982aa72abbf8a42efe2c5cb1eefaeae6778eba45959977bf50f186c47640e8634a73fc290b9e81360021b3540eaa172724ace7dccbb024568aec504948bf78b9e2fa7ad402cd8ccfca169b611503f99b2325507b603365f12bf2b77a73569aca30e530beb11c742d501851cbb168401c103563986838f0b
+Qx = 0f8052c723a008731f6356175aff46e389f749f484511d98bf01c2015282ec582911096
+Qy = 6b1608ff9c543a4e18627531e6b52ecd70bf53af8a260fd173ad03fb26c508a0c217ec1
+R = 0acc5838d77ac499c6ea172846471dd77f0e615d9242bbc46d77b4d737cc0997972cbe7
+S = 0d30aed16c93e8e9c3d1c17636c800d7610565060cdd9384a9b388f2e257d26a1097239
+Result = F (4 - Q changed)
+
+Msg = bc3ff6abe43b899a182c2c56fbd5c8556de9d7ac6b61e3543d478d66ee2c8fd33d2ee63ec5631a2396e9dec254c47276d1c24e7ea5af5a77e0c0bb36a7fa08bd06c10b6491918adeae41715215d452e30c5bef15bdc8a5d17aa2ecc3b2d3dfb44aae9b642ef655ecad785a01f147a119e13beadd5be183ca7e5531a2e0e196fc
+Qx = 7e48e56d4bd75410703f3975ae3a0092261349b0f551a819ceb10bf1ab42f4d943b9849
+Qy = 17fc256498e61fbeefa355ee31a68efb477c4e6f5612fe9537f6a11e32d8c1dd097954a
+R = 1accd9c7a65b7601e72f981cde1fb0843cfbfef9eb5a867ae690565d4a47132bd85a38d
+S = 01a8ac39573fad971fd84546e7d044c9f6c0e3f2eb0699e55479f86d33490971e231df8
+Result = F (2 - R changed)
+
+Msg = 8371847ef04ed96c093166963db2da8d61eaf10558cc0da4ff2a7793b1e417c4ec4270f57d684c595cea7afd42683013f5cbdf1748f56b0c3a41d508e1a00540b97229f6d5d15c4ea121b0190a6581d9962358dc7e9cc7bfa33c05a65ab0c465a8bf8b8b161e9e3f12353310aa2f4a66ebad3c748cbc09fe132c6519e2ab7fb5
+Qx = 77eefccd7b8ea213c69d15761fdd52ef0305676a2f37ca83b3406a300c0c2cd0af71b7b
+Qy = 053b1c487853241fa2c2b69f10c48aef3bd67d886eb2b07dc788f8b164973512781f6b0
+R = 0c8ced570044759c9af7ccf26a7dd7d3d136b194d5d3422ae37c8563a741efa992800b1
+S = 029574c88a062aee5e8ca6d913a7107652d2d0c90b1a8d12b032630f275a4660798ffc0
+Result = P (0 )
+
+Msg = bc52973edd03558371c70878419b21b846e4c8c20dd92b5244c6074f707354bbe292a630a6c9026a14abe220143d13563c2861a240eee3062e5fe33e68b0fc90f01639ea6d3640ab7d86c87890c5da7b17c9020119897f43c332aa2ad25bcd169a606ce4ac334dd010bc0f26cdefbadd3e6799689e783a0c43011ba425240d68
+Qx = 58be59abcfcf562ddc2b47bdff736e233702321ec6e1e87f476bff36d3f0e9c349e18b7
+Qy = 358c7b379be92d9cfa8ebb33975643b34861324cc77cf79153cd0e1f08aa91431b1920c
+R = 1a6c38c275596c6f071670ceb21c8556e71c3190faea9f2785f002c93327e209f267206
+S = 127e431963d0e24915b5c588ee1d515982b52b8a2d13e3c8f7db3aea0ac44117620ea76
+Result = F (3 - S changed)
+
+Msg = e4c6020db4d5e9aa6f2763c8593b8941a0f7a0df99e8145b3a807830ecc60d354e0cbd4513bf0f7d4a9861da836de949bcecf97c7a6b86bb98675528cb2f21ae86d150d6b80aa84ad6bc373a9cc1c6adfb1c3cad02c2b9414069d105e3eabf5f096d7c09f5b1c5de5585cded47149f0597bde32f7293b6b5b7ca97a88286cd69
+Qx = 5a50364be908a2dcc31d1ace649b7c1681d6d2069cf3bc04cdda878e7492b7cc0490512
+Qy = 0343b99aac7f7d2d8cb5e453feefda3b166c84bd466211cfc344542c723d833c864befb
+R = 1bea936b2e697d53f50dfa3e120013d96e634a6e552e9d26cec5523bfda0426d29b9d81
+S = 0a3c5d383f4d322e23aef345b6f16079f44c37ad050654607c4cb90c908340f307ef127
+Result = F (2 - R changed)
+
+Msg = a454af54c133f330c63c5285ff2e8767628476bee6d1cc10e1ef5403e1eaaa62e488e62730e475f50892b346fedd5fd76e45b21bd1ba515c198740ab70464bef1221ced680ed9f7d4e3be36cfea8caf4fa3225761730dafcde12bc5a009fff2c0455fe8964e8252bc9c6b8735de02c0c87af91cf37d4d9b87d1568bc757ab7c5
+Qx = 798e0a29f5c0ddf329fbe3b7958d5b4a2f629616bc876ebc1512abe9136b56edb6ec36d
+Qy = 585b1d692468b1946de176a5ae387d7878f4c856dcaad9c9b74934755ad57f49250666f
+R = 0594348edb5bef2c8dc76de856baffa15b9a35cee52357195ea8a9fc3a96fff3fb7d6d6
+S = 1f7072e27d89b238013313564e34f0e221284f5fd2424b0473294abf1abc052f96a9b76
+Result = F (1 - Message changed)
+
+[K-283,SHA-384]
+
+Msg = d1a75368b6b83238b66a1dda85ab85ac264b28862dc3f8439f0b9c7314b7127627fc4b9e60c6eeb94c85ead7035379e47290683747af74b05398ba44a1bc3f9d1375e4bea1fe5721e104969afc0ca08033fff862174b8ccd59271ef20da0234a245d4e151f98ae1ae3c1db7a638575a4567170e1e342800ddcb56dbef95c43e2
+Qx = 30557ec31f7abb062a4af5207707a7ecd810341514668afea2818b5cd12daed0714594a
+Qy = 71a7a1b4e88ed37ddccd6d7c660d57211ac403d53f6119dbd56d914fd8eba3ecaa57b87
+R = 0e6d687b3712a2a850aa771c408167f978c7e8cef500e12dd889da81d2c6288526cb82c
+S = 0fa0119781a0961eb7b23ef184bbe6863c47d8361619df2972ea3cf41e3d5f7b2cf41c0
+Result = F (1 - Message changed)
+
+Msg = 8f5bc7a2d18b8b40d16304958ffaae2fa69804059758e1e19ded24181f98d9252398daa2f813bfa16b18abff691ab74b38f6b05b8a826d5cfb4f7f0e0b0ab03c7cee4b451a2edccf5056f5f91844dc670bffb2ad59800844cb31b3cadca085ea6a82143bef7d892087ef3d8ac943ca190b727fcf567d547d900d0f39a08f6e14
+Qx = 0349ac26acdbc9f4660914d318e5467b250aa7e84b93f0f762dfb6187120f76259dc251
+Qy = 0158ee9fd35e7f2f8023d9664be045e826ed2ec2700e57565189dea65dc7576861848b6
+R = 1fdb9b070048aa65dbe5a3a070ca1d02e5d07bdada5a82fe021fcfca7d952af2df418a6
+S = 0117ca22541e8fdb2babc84b11e74c4271454dce8337e908f8f167d15ef23333c3db858
+Result = F (1 - Message changed)
+
+Msg = 78cab3cae32427d516eb3b14828bf8e4fdd8469a258bda29999f73bac5c5440dfd3440c7ea31910f0384194448cd19c310f897fc8562168ec0bc526c4db5872f9ad7fda930928eb83039c867fb14eb3207a5438ad01cf39bd58081a06fb10c51568d5eb4d02a6e04f09539c8051321fae3f167fb95b9a8a70ebe44df897880a7
+Qx = 1829e6a31eae6aa373a69b1102a8a4a2abe7be65d06e37dcfde686349c29fe0046130ad
+Qy = 214724fb16beaa7b421546c9fdd03591cd48e0c5b6d36252a3490ae699aa6c61e9715b7
+R = 09c6fa3bb3e9e684545af7d4f0833660acdc9fb464b9122c36cefc03a374114bc38b3cc
+S = 1390899d78b97f7ecef9f33a82fcc25605df0b6d16b31787b29d8a1e5fb444935db427e
+Result = P (0 )
+
+Msg = 148c6168897394b736c5995137e9e96e507a8904f155c2031a9c5bff8fe8cb8279d77088c99cbd40c607266a87221594f42104f92c81dcb465834bb44558af09cc16f565e714c8962fbc06cce3c350a626deb11509c61cb25284a4d7de6bfea1ef759d451b5df045f9279a8b7e694a628873ac03fcf61e4bf502a763c1b9184e
+Qx = 40378e0cdbd410c8b21d604230979a605ace72244a14011ae54629eb13fcb0d7d92f93e
+Qy = 3c112322dfdca3c9c7e0323ab6433aed8ca06e17dc34fec3f5ccd3db883825e5672b9ce
+R = 1df22e4ec6d4e9d5ee2b868f09e438ba935c21a4de1d749e975d319212ddc95201fb255
+S = 1b146c9bf6908810761dd98a308b2228538c3ef72e2f47410c843dcbde23ea411b80aca
+Result = F (4 - Q changed)
+
+Msg = 98fefe886b57e112e1002fdaf9e3e4fd8eb9a6ede3f11799eb55a4b00c3f05396c9c9e2aa1ec17570c67578faa1d54acba2bc7d6d4bb6af3b8c2ecdd9ba76c41ea59b7f486bd631a0321a1cdc625ed2bfa4c847ecf6f02f72054122faaff13e69d33347bc2c3ca06ea0fffef30cb2aaff086594a4804453745146250e41536a3
+Qx = 0e8e125d91e223c6cbcf6b33c7763bea02fd3e3a2c9821c58e009ffca8995e6ff2dc76f
+Qy = 2cd0a3bd7b643d2c3fa7d5fb3cf78a33bac95909a9df677fd1237a269c6e8876d1c5ed1
+R = 0346f7c261442232b1245f5a9297c55a63ce5dc07c89dd49a7057680797f554f87a9056
+S = 0400e3f16ac6436152443970981fb23ea9b445f3d7de5ba9f861ff5bbec34c7c0b7cafe
+Result = F (2 - R changed)
+
+Msg = 520c1bf5a07246f2ba26b0c860b66253ac5723b0cd9c9f9614587d30837de4b7b16feee0c3c3cb17c231105c59b2c2e636d7d967505f5d0ffc85891d41df6a830d83ca67cefad3b2f3784293b3470f1f632246aec106b4552396a45525e5f4f30dce87cbcd0cbeef8a871d1bf8862387d5e8d43e1d219d5ed46665e2815f67f7
+Qx = 1954ee87c63d94c82e77d6d490a9677948e2a91f1d910f3f63cbe48b4cc4150002d5932
+Qy = 53fd6934f5377b024863e3b6b05bd284ce720fdbd308d914bf5722ae90b798a5af01b65
+R = 0758ac0a7e88c5228d8e109e8eb6b38803ae86c8dd67c1afe2656ba82c3d67ffff7a08c
+S = 13eaa3d077c97a3a11784d48b6a0097f58baa775cea1741be272e60b2eaa186c09dfc4d
+Result = P (0 )
+
+Msg = a4edca2a2fa77f6ef6d10ea6f5e770b86b3fe3f271a01c0170f13ee5a5211f118ef0b7896aedad8c2657e1b9118098ca04e917a8fe64e6f49e0b545675bdfc982f260003a0eeb7056472ae7dbafd8047acef09a2855d5e64eaa3e344ff370c41c5d2f0b76fd96e15ed8a4e3bc0a99cdcf4b9db04c1a6cbc752ea553ce2b1efc5
+Qx = 40bdca3ee5d7e41f9cdb4dcdfc1446fdb9f9ebfb2a8ad0724624ec62cee37ff70d24fd5
+Qy = 76181a1b3fa9762f1174f057f5b42c9941702782338ad63789968de8294fb15e19ce79d
+R = 12295a98dca2b687c9e3a14649629e68958336a507bcf932c1cfd1730bfe0491acd6f54
+S = 02e9b3fdad36c917c4e0106020f943831014534be805292da6a76c24adf5e824e65c071
+Result = P (0 )
+
+Msg = 8a730b9accafcf0c2685406107e49a7d72a5df478ce7d162020011333d246fbaef397345b1047b47b75fd295df4e403c01bd884c2a0b087632b979a73d42000e31a096e4a6e3b866b8e5c96eafdf59a667d3fb94d575d48137a4fb925c72eb09dafaf5f522bb7189f621f841ce219d729e4b4794bfd99f0f1547ee8f5f70c79a
+Qx = 4bde1e852ff69469440ed6484659ec8d142851784822624a3514ef3ad5180923c963a85
+Qy = 4e5e4a1a4946c0e33e7f06a0e8b1f1ed2c50c62e092e98cc98846d9f769b57df104ea93
+R = 0f3a5e4992c24686d7bbea0305706bce7590bde32ed40843ddefe363fc0512c96aab596
+S = 05361f79ea9a90d0e11e86b2a770f3d5577b67e8291b6fb9d4112093309722e2d4aeff3
+Result = F (1 - Message changed)
+
+Msg = 9cf50ac032dc20e90e735e9ab3149a450fdf859beb30827f73a5a5032dcea813d2afe2d78efb1562020e06167f3d202c3a75cd8672e752fbd8effd024aa6e87e37b4ca3fc60177a858a372c7130ef6eff59be8138c9840cf9bb4a671c312a4bf3acee0681df117ec43384e95f7b80c03b4b373d2926f09055736470961664689
+Qx = 32521b42d3048f0982c0300952f02d8248d5a09200ea80d840a2b1fea184111b5dd0de6
+Qy = 23c62bf31b40bcb5d1f606fe618e5c0b3a79808c8983565e9b98969c97ad800dcf5c6e2
+R = 108516a71fb5f592b02385e2f05014ead513cb08a872508ec3938f9ef577398cfad7b12
+S = 1ca2a9233e0add629a078970d9fca2ea9cf485ed8797895f8f418feb216380bdb735298
+Result = F (4 - Q changed)
+
+Msg = 696d0c6466516ea9cd8367bdec6b81a9c48f72b21a2211acd24c5296d15ddd58cc5894bfcc20fa28813ed8a44517b61fa534c24af70c924db3322d5973778184e4f21d965603295622434d4d32922691f87a09d69e08cc4730ba455ca3a7273d760e5b56aaa97ef9d1026f3e0eec407fdce3f6a33438c08649f242fa2c1fec50
+Qx = 6618acc848b5e86d08011e6da3cb3b826fa3610659db871eca2875db625c73d0f7d8313
+Qy = 6e9f212c3619bc53c1281b4800c2b56c1f7b5b266c0314e25d4b87156771cf2a0cc18b3
+R = 18b3680961db5de70adb4018d7f4495fae7745dd8734e3c67c53db165539bed8faf9c57
+S = 17a1fb863cf580f94205aa8c87b764497c0c45ef7d5ea1d08e8abc94615196c3bfff39b
+Result = F (4 - Q changed)
+
+Msg = 448eb0495f0145cf149bc25e53c0b54f87b6836037097b0aa693dbf1c873b686e2e07675e37ceea83d30dc4573507ffe27bf7e21984a8d13315899b030022ceea3ea7a34b22c100130a5bddf01e7f7f36ee295f095299bc7e7d47611d4723ee3a0be4c6a48d4258604acf9e48f3f01e8f69abaf2890644b2a79b4447c3cdb608
+Qx = 66d8fdf50c52bcfdbba7f29218e5aef881d2954fcacc89d64bc2b02c22e80907f3e9f45
+Qy = 200826852975f54fcd57687fbc2925cdd59be774a17ae901ecef88ec36cef8239df2145
+R = 1df3d8a08e178c998e9892ddd48232599d3e02c843a80f9e3e0bc5a5e843e4334c58b57
+S = 12f76f39df51f1a895fc716775ae90030c8d89e35f61cc374bf1ec2efde3db395f7b773
+Result = F (3 - S changed)
+
+Msg = b24d4e8d40d1dfa2c06f2c91334cb4c63d67b8f776ebf4acafc9547b557bdf57d8fca82b10884d4dd29ec43b53fbc193b70faf40b8fd22ad76a91bf1fadaafd6b98d414678fb0069323a9e4cc47879e9a38aa5c2470fdead43f10f8bf0f3a7e7dd8bde83db19a7e16dee244235f86b3748dd191f404b54dc76f77937deb72245
+Qx = 28d8012843eeb4cda86e7276c8a0cd07d9138ca48d736a71557ee7e95cd64cadff694d7
+Qy = 74e6b3d52a2c119e18be93a04c43a23022445479d55d3c6352654226eafe6e5eda98ee3
+R = 05bd25c51c3e3436c76c36e985a9a09262d1c0271e06272bdf4a9e7a6e153df56d45ee9
+S = 07df9928ad3deba83ed3817ae7172bcc2eb140405dd81da2c39efa4732d71dfee444d64
+Result = F (2 - R changed)
+
+Msg = 446dbd9beed82ecc5ecb5f059e547e890fbc0ab3c9a91e0662739b1d9a8ea219f9ac21f01a33267b2d5d3faeda7c9bd26d168dd143b957ecef8e066a22560c0dadd3ce3a79cdcaa32fdf3d9038c4f721218d206c3138341d09ab6b360bb029977b825c9b141d459cc513824b9bc2d5ae2428bb0cb6cefe0887a7fb5f8029868c
+Qx = 053c4c03c234a8e30849364eab7c6dab79aca5fabce8d499cea00d6afec321512f7a01f
+Qy = 27d5d966c90eff85937d4a0a5103ecc4f6bb59d3d22b55e16ca432b0dd7b7899c6684e8
+R = 032ebbbeef4b6a73851885272ef1d77ccd45543fe0f5734b8bda09f98c88e1e48b4a619
+S = 159369325310421eef84a47225ab6420ba1056d93b41a9e55fff10dabf8641ecca8893c
+Result = F (2 - R changed)
+
+Msg = 42de09342cb337cfa2befc76098a15db82769ef31237c68fe80fd438d3028656adca6d8e7120fcb308cd23f00158202645c735a81a8288b4e0895d0dac83fb9d4c35d482092a7ffaad3072b727a48e68ff92794871a935598e4ad0499fdd25f35147f057e8734a152dfbe1c8311722d2b2fd86fe3f143f1e24f7bdb34cc02186
+Qx = 199b2c1bd0e4c39711227a739c1dd8fb0afdec0c166ed0fef51f08b81180b4379850a07
+Qy = 4b7ac17e8068d9e877f803c5060fa72b262f0e6faba9bd04980e708db035e65b7a58003
+R = 103eaeb8b91d6c32e7ec1bce3955f063f1c81263433d17f87abf32b1768cbcb920d359a
+S = 0bd803fc57dbcc3bac2f02d436dc3f8a554249c443779da946dcdc8558513c2893d63bc
+Result = F (3 - S changed)
+
+Msg = f119c2f765b0a15c0265897076d8f4ba30243306623801f8e353f87cb495197b7dac9cf2b1d2a276d546bfee29c007d74150c1b8e81c9d4fbab0ddf733853918535512f14c02ae7cfe595d502cbcf0589bb8eb516e4dfd0f631c39f3618c33552d44ffb02f381e9ba2840eabf19efd14c12bc37b0bea5ee4d348ab2f509555c8
+Qx = 45ceacc5d65e3c5f4ec7714c1ab260f5d1585e800cc4860a45ca33fd8d2fc8a40fc8d65
+Qy = 3aec357abacb19c74444ddf0b18d26d7c7640224e5e87dd8f74cd7313cda0640f8f6b86
+R = 0e7567f732267628744edff67fc1b611a6761daa78bb3c99fac6deb1abf4c7ed17edae6
+S = 18052deca4bc73c7d6466209f957730739904526686359db9e41799272f54c0fa0a6257
+Result = F (3 - S changed)
+
+[K-283,SHA-512]
+
+Msg = 990cc5cc2c6d5b4f686d577333c0022974d47da0a9c90f0760bbee17ee953549fedfe2c387e957c8b90ca8587f9830df117dd187d4923a0cd7e747fb12f7513a61f70dd789f6a852e6ffc40aed1fbda2815934e42c4daa95803a1e0c0c68f5282e01c76c535699911b2c67da1d68d2571c5c090944c25bf00379a4d239847b25
+Qx = 01a5c92ded0ccb9e88f41bc08002fe6e079444b6bb74b83108792a65623c50e17ece234
+Qy = 1f50d0233378c3a8f5970e75c57b46b8d49a8afb2097c7690915097956c962b4dca9bec
+R = 118a55b8a6116bb37ea09833713801902cbb3a4ba42e85e8573b51067d8a162c24956fd
+S = 0054bfb90543fff32981bcc6984971d46efdcb0e7b8fbdbcba21427d884b8fb3ea9e266
+Result = F (4 - Q changed)
+
+Msg = e8cde5a2a751771730049beff69bb6f89c51b264a6083ad6764ec2332292db46262011cdd17cd733234a364bf10d7f6282cf32395f94fc28f886bf07322c6fc522433b070c041ef067902101f8eaac00b0b40ad5ac22aff3c07d6816036afa019d930d0f839ab9efc4e7f3ae822d57c9c91b014242366d99bd15ef87c642fd36
+Qx = 0b894bb3a92a465c5b7b8fd6a84e4cb285e7b2775ee3ea2c5fd9500dd06959f58eae6b3
+Qy = 66e00013412d948fd5848235ba12f800efb3e03e6367c7c72ef3b7a97f5ee25be55ef79
+R = 045a4fa5cd1b50f01a71659d6f46a15b5acfaa61253dac39adb767e00b21049111816dd
+S = 078bf32db3ac337db094e706620a3b10be26479a92a36bf57381370e4fd62e8e2679a59
+Result = P (0 )
+
+Msg = 69865ae03fe7ee7c032c9b0afb717620312a381842f4395ea248cc0e99f455e64bfb50c4e45a72373f2734e9361476b2516ea16820ce6e642284a241f1d1ee403addceac3b34e407d8d7f5b41f15066bf17a152c47380e10e2e1f4aa1d95080cdf20998b4f5bbca38a4f145bdcea0fe879118829d593ee2494fd270a1c54d066
+Qx = 3cbd86a96a5bbed7d67d9b67512d1ed9427f0ee0b664429506f1f7487999a1936633ee5
+Qy = 33f5e6f7727d21793a82e4eeb2348fde5d345275a95b676c4bb29d526611e83be4eef89
+R = 152adb127d9542cd6e26bb7cf9845a09406ff6da1769c277ed5b50c7f508240f36f39b9
+S = 17c52a3d3ba4ef891377314ee6cff884745d9e8bad79da9d85240de2b6322cf615b7c7e
+Result = P (0 )
+
+Msg = d130461bc0e03dff6485d64af558d125f9ef0544f8e7d65e058fe85578d4ccc025fd1611977a2047763295ab66fb0fb580ef1d3e477d7504620c71700278710cf928597c2bf1b64d36db42c32b1e80bd60454870e1888947334e8c9f41ee49bd6ddd2822496071a64025b702fd535e2375f26614a1798796c7969f2ea454b20c
+Qx = 0ff1766822e4c519990419e5bf9d9ff0fc1eff5e3f8dab14ecbce1eeabe11219ef5c820
+Qy = 1616c546b7193478eca63cafcb8a838a81b15fa245fd4e45c41fef58487309ad92cbe15
+R = 1a8fc989638797d19ab5da69dc5fdfd549e93a8cd149220758189e8679b25cac442d391
+S = 10019e98315562e43ae52029620d2535d10f8da5d432daa20d09807395d6be74d973efb
+Result = F (3 - S changed)
+
+Msg = b9711192421411e65b03027c71eaba73cd113ff7faddd2f5601e75b17086da14844222bbf197d54cf5df0eaf0df8413808de73abb1e599fc5aa3c4a2084176cc04dde5acf117c4ff65b87028266f8e18b223199c32f8b2b6d6e647eca10b490e9bbc604a5f8aded9eda1d49545f0ebd6372b4fc477b832396cdd6cc4531fb4b7
+Qx = 305483d00fe98d3b42e65aef3e31eca75ca53473fd94fa137626b661c84e05545b2390a
+Qy = 5eeaeca6f1352e0acb13dbaf8621d0f5554ebb6ed7984fe6f0bf43df5b2f4abaef6857a
+R = 01e76d04f1dbefc702b853b6b1035fbad8db216530b900347e7472b834f9b448c5dbdc6
+S = 198990fdf9e03e3aa426ff93cf6df10780cd8c9a8fbed899784e0241d86aa9e63ec456e
+Result = F (4 - Q changed)
+
+Msg = 3760e43ca16e46f54745a04c77d4ed3f5f55e018aeff72ec58b02b087ab1be0e49e6dab39143c06eff64139bab88270043ccdbdf4f20d4e586b1413d462b26d7f8ec24cb8b1a37e50076530c9c6d4203c9fc79727312e79481d4b2b2f36eb9a12ef435a0c1bd3e97bd004c4f3abbc6d30cf3d9c65ad7d5add406993cbac0625e
+Qx = 385bef8e2c36d8784382e52bc44e4dc74d30175e2ca8999c18ca940d06eced9456cd5c1
+Qy = 1e34892a9c071089599af1c062ae655ab67f46bc1963c33153d980ffcf386dd95e6ac2d
+R = 092a7aaba00e51161e923463c24f83dd35879275e8e93143e24db213448942d8a09dd1c
+S = 02fd4aba19a83e41ced454add1b5946b52d1e0726107b121575b4732b43a2504e666467
+Result = F (3 - S changed)
+
+Msg = 65ab07adba917b72681a139e3d5668cb44a26c2d04c8d24bc616344d025fd092f5b783d951780460102d68edba0cbdf2430f0d87f5d4ca1b1b054af2c165b5befbf414eacc5fbf77d36cd4d66eb147e15b177f5826a35dd59fd66221700801fddf02da9a18624d65ae6edd6337db8a065fc29fd5b35161efd2bea08a15c2e95d
+Qx = 13714496c9c8d8ddfec9bc913b03e4835720b4f4b22171308a838b5053e9f148fe09b54
+Qy = 73efc3684177cd1f9cb04b67ff2abf27af51807b1a4f56ad49a42c2ced1b75d76df2cd0
+R = 11943e5bad38c88a2fe24af61544b10dd50841f4148dd27e6f91a3c4222b269245afdf8
+S = 0cfc496f1f4fb68cd726a7083a1533d849ceacfa3c261b6c478ccc225353d4492329e45
+Result = F (1 - Message changed)
+
+Msg = fbf42228121d85e17e9df4ef34bc1722d08df5f7309b1a777d6b58f66d4751e89c7e3d0a086c7d414b7ee091bdeac677d056b161eb3207c1f29306b91740a34eae91987eb19c82db6ff33fa36fe87d374226e9355229194a6d6cfddabe8a24892df41ff2850c702cc607f3ccd76190ec6552aed2dd57821fe5302971475d1335
+Qx = 10edb988c06586a77e2eabbbbe037715e2bd21ff3c215b3052251af1e16f48e878d82ed
+Qy = 02a53edb4c78c213a4b0d428b253fd9316def502f83b4b2b5c1e28547c899f4d8ee6eaa
+R = 1b5b500ea6603dc8d9f3a35dd8b833c81d5de906a1ce33151d86ccdd7bc7fdb134d45bf
+S = 04273057670681df3c01e0a06476eee5410c93ba03a24c32dc44d349d0f3ed0e2b2d531
+Result = F (1 - Message changed)
+
+Msg = 48345da99219300a319288ef98158f5068bc5194fae802d3631ddefcee11eb28b401bc70e132291534ed9f816cd69c296702e5cc76a284f2369196b3cd487e2a6830e4b3b8ffbd073ec5c0ec9d0b9915f1cedee11f3da015cd209ddd38f0fa56bdaf5e1e973a3a1a52ae16e4b8e0eb440750ececc03ac0deacba7ac5a7f0d50f
+Qx = 41658f68a6318c5073c5a0e587951988337295346816da0c0755ab4d8d901a6807c2a4a
+Qy = 7eb2e2c3caeb11262e1a6c7effb1aff9fb9acfc7c5f1d20f38921d275c4884aa515e69d
+R = 00d26ec94628ed68f87ac0b11b03fe17033a8f3fecb952988350fd23280dfee46567f50
+S = 13def1d0f6ba28fdc001d01b6b27991f10cae2ae28823f5026749a2d2d8e12879f8ea44
+Result = F (2 - R changed)
+
+Msg = 6b4817979bb26af3e78c7beeed2d862d42bf6d0d448f66d825ddd1e0531b2c8c1f7afc91d7882c8f1525b8e75816b8cbe22df4937b29d7d61289303613380a759c5385414c3ef6a78f9a6ab2739a9bf77b1a7b9153a537fda1ecd2bd9bac9cca07b6cd673a0558a0c02ed5880e3a15f227ce0123db33d50071df8f03cd582981
+Qx = 6159a70218e5196edb03321a933e33a7be9235b26fed416f0f4ccc5df6a78c0b384ebf1
+Qy = 6cfdac5b61bae55eef71502ad573b37f0483135e4edf7b9ae4d828d725be6038fadf569
+R = 156d538718115119cb6cf5c1feaed301d0938cb3d9d4447289bca23da72556f6fb419b7
+S = 073bd6b29349b78e19823699121eddef1ea7ed00b6323e881793365df7ed9b5601735f2
+Result = P (0 )
+
+Msg = 0f4249e450388aa6c9f22730742d124193a7fb93a18f349be339ed04ad1074389d8670ca5a898194fde5da0ff0b674e57de7aafe47a7c00d631156baf562aec83feb4f18a151f508c0e96e71b3835c3a651b58e6d7a525d4185ed0e76b0a88cad78ca50913756b459141bef42fc4aab37f581222a1164ca8497eea28e8f27a56
+Qx = 0aba31d52badf2792ab950973f20b3a8856e0d275dc4bcb9fdce1453a3c11b00beb8f17
+Qy = 2fbdc1597eb64ca5bb6eb4d962870021a34a12865c700c6a27b977a8dbdf8fdacbdaf2e
+R = 1eda7358b97e62cf4f31caa16df33df30381842b2e4c8b80db2a1b46ea14b68d85c05cd
+S = 0d833572370bc01ed57b9830871c7c4f4a2b61e3771b7ddc4d1a2f467d2c681cb21ecd4
+Result = F (3 - S changed)
+
+Msg = fd23f96e2e95722f8c13333148022d8b9119ed9077396aaa2fdec50804ff6571363210b91063b72349756f2e0969ef2b6f40404169c401e0763faf3d1252a0de30c497e3faafeb0ce405a36918a13a158e2144d14368b47922e682d48a5d6eb41ef1406463ca007803c5f3b5ece0e8bc2a78a1d97bb6f4df4b7f817c93e07603
+Qx = 2969f3daa3d5be3483e6996eca16151ffd3553f47db56f43134a3322e0295f986c04789
+Qy = 08fda40fb3d3b50334cdcbc519075c28d5e5df4e77667ce29ecd678922632175ee5761f
+R = 07b1457633a4c69a173bc731272eebc904b7ca3a1edeb3e11e9b2a3ff09bcd1a8a4a000
+S = 0220dd9d9be61589eb5d95940db13807896d05c161e8c414159258219573d2bb59715d4
+Result = F (2 - R changed)
+
+Msg = e1df6e110c92507d3995a48e71d276a310f2d06959a74c272cff40c2ecca5f8579315616dacc121a544e7fdf1370287bc3e1bc793af8b584d5060c151fed5e94db7ae13f65a29616987c36bfff432f188ebfe1206cd5bd3711c44afbe914fee2c4253282d14e577010275ec0b6d4989b3b533e1dc54adaf718dee03ef9245bcb
+Qx = 4702512f991c687491df8b2e67a0040a392f8829b71aa3379696a29fef5c2f833085bec
+Qy = 19160fe39a275d91188d2201cb05e41a90bd0b1a4a87719ae4174095bbf3ca948298f4e
+R = 1b9b7fb91d17c2b3f7d7746eabb0834d9b14ae5c0df4de48227948aba725ec5b99278a7
+S = 0c3cbcd832c0d871a5a61a9130083444129eda930d60578e2b3711f34da15750e8500a0
+Result = F (2 - R changed)
+
+Msg = 02b2390f8986b925a180ca42755755198a8b4887aeca50fd7d2f025b3b9f8f2821b55440985e758297de5e794e0b2155340c7b593fed7d0d926c2f3079d7e9de85cb3590e8babfc23173086ccec261ec6748510343ade0e9b078c6bc50ef7934be44b578ede32be05dfe7efed1a8fe0bc374fd0c6f4f6e27ebb523c12e436af9
+Qx = 4adc5f01ddf4673ef3f40ec231cc31a32dabea0155d377be2830b7541f58b021965952f
+Qy = 2f8dabb50b78006d4aae8073084bcd000c5839f3caa3025145f8a9f523f36eb00c16066
+R = 0f4b4d9a15b1b824eb9282368cccff9bb4daf82a2a68cded062c930537a0e453e819f7d
+S = 1a9404cb8e614942ab3ceea07ce8a27f65919a4e8e68b71fc261064f0c067132191bb1d
+Result = F (4 - Q changed)
+
+Msg = 59b673954c72d0c6b750fb8c6e8608cd9fe7616ff4850855843143ac809fd4b47b5608b209451c1416827d26b71941e13b94aa4563808e9125afa7b2992d17e9917e4fa003bc9ef6ff8ba287bc1034ec486459f4c1ae1ac968cf333c82005b28c7bb421419d627c82e0bc01d946e57334115b235191cb2c339e11f57d61fe1af
+Qx = 7d459e3cea8af1d9f7ca6cb1eaada2c27274517ee1e6bd6330a2f11f28f46cf3f9d0e8e
+Qy = 68240c0c769779165ffc0e56b95183f82f6d4cea8728eaa3a6eca7b7a03919476f880a1
+R = 058145206640d229dbbc3e1a762e2d85e3d8a57e29de748a73ccb336a8515e31a4f010d
+S = 1da5dccc770a815bce7e3a9c117840b7461ee528ea70bc50fac2138606e58696490e0b1
+Result = F (1 - Message changed)
+
+[K-409,SHA-1]
+
+Msg = ff96031b33980b3a2c1f887db90d8da8f63a6ea784e0ce511a9d98610abf9ed847ce69f22bf0f924fe6ec5ac5c8fbb72cecbafc4209fed1391e6d2b3d8836462ce4af7da4b5d65d6fc6b495e6e16bac597ed06ed06c6f9dbcbbf70df60aad3413311dd25d851693db5da8c6fa92e51851cd39ae9303b851734d4a29e95b6d435
+Qx = 1827098c818ab246c69c4fc1fdca01ffd3190927f69642b2bfaed205cf2a63ff9bcf5fa0a767df5f82580c03459726cc076505a
+Qy = 134d5d2336a3499a5a7648c0ca07347a5cba976a8717a9790d5c7de59c840d9cd0b54b9dca92797eb6648362f4a42e54b46bb61
+R = 02d7266219dfd9e1e6a86601412e5e63dbb5754c78ac9a3b13114af274026ab45293fec6856deccd02e661d2b1495b3f35658ed
+S = 02e7f4066b768ec1fff2abb608a0b57996a4b857bb2084717c7edc43ba6c451e029f26781bcfa2b43cbaf1bee08b955b3d1f328
+Result = P (0 )
+
+Msg = b70f9998a167fa400cd7ea326e265f9c9659aedb82ab15a4cb5634a8b2affceb151f38b83fabce7ec6d4060db40753a33172b5ac583394d717e324023052a519274fb3344f8cb7730ccfd403bcd33cac63a459e6af753ebded4d9045b0ec6c5fd6d9b8f00c177b4313a7c2e5288dd3cc8665507c1be43f00e8d5c4bae83d04f3
+Qx = 0fad83e6b385547cb07ed51f10ba23327616de2ad5d53c6be50ada35d6c59adbc21030ad0f591aa906d802ce2d7e7832f111d78
+Qy = 1eb0a050df99802e5396ac87b9f4799f85dd5dab68d115763c8598e0a93f2fce8402986dc36abeac3a1e44cf0502582cb089f8f
+R = 017f2c52483651a0e5212624448dea67e32a89df1ce4f107d61d99c878f0dfb14f661d6c5a73938f9e52b2c0eb2d9054c748dcc
+S = 061def59adaeae00358e28f19f305856b29de6521a1e5942744528a3063e1570df4c7601c4171fc699dc141307b50f35fd062d9
+Result = F (2 - R changed)
+
+Msg = 698301ccf01568c974b82bc50679929bedb336e7fad24df896c6dd2de4bd6068fa05900aae91192c68b9f0b508cff93223668937f23a9615828ea172f33789a21f73708398177dfc913a984b185d3a5a326ccb1f3748baa87bf0ccceb87945682892ffe117dce017e75dc5419c1242e017f931277f54817f70374acb55ee081d
+Qx = 12a4407f06fbd673e1da11932cabf3c9f28b5481e9fdd2b5cc5c0ac0b302ba0c36edcc4f835016545cc4d2de8da6108186fdb82
+Qy = 1efde2f8fb0f9f34196b666c3dcdba4aae57723a0aa6920c7d77659e1dec42695340637a633614644d301033d9dce9e7d8df987
+R = 007f1a253402813dd9ea99ee2504c46ed70748600762c4111110ce8d6769265773c5ddb1aec12476c80aec5d6c737d499dab183
+S = 02f03c89452341be4c9e9ef3a3541c6584c95f21c9621b5c250e624f5e99de7ab30418704eee3b27c0f6d55ada05c554ecb416f
+Result = F (3 - S changed)
+
+Msg = 36aac2c59727a43f349e1f705d8e380aa7732c16c4031eac558fbc3cde303ade2c1b650f5df925f53d372f1aabbd1f08e98124aa281e64cdf58ba1d45ab235d8192573d008fe76099ef61c777ef9a1ff4423fad63c34bfe62a0a24a4b540d35b02198154a4aaf69529eed9d1a39186551fda0c30eaae0d41555aca2e3984323a
+Qx = 0f28b056b5190cee2b657ed33c23c5f20b35456407e674c4bbf528e92d9bfab95d1f953072b58fa884b6f2554f807d85175ec28
+Qy = 0f7612f46bdf0f4de756626262e3975aa10ef3db3b469af5efc1e2ac14eadbf28ceef116e66a532e45ddadb7d92e14e4f685970
+R = 01f2c7f584d82b94a07c2a1f4f574bce280260859a7219ba97cf2bfcb52a0ba54695a4b9f734d94424acb373f256dba1ace3c15
+S = 00754fdaec8086bbaed94563c3ffa5e06b5ce25c69158a1afc035a0cdb1bac6328e9e39df28b6001dd306f48f19486f4321a3d5
+Result = F (3 - S changed)
+
+Msg = 34b674db060179772c46a3a920ee70a406a97d86648a124e766f58c0b08eb0a532317e9a21133c9b4fea3abb4c61642fe0213193a8d9778304ec90f185097424adbbb5406dff13ceaa657610daa2e1c1f02b32ee3efc5300175460eecdbbdb415645bfbd26f76d8713b2b3be068d47ee41f8fdf0ab81257e1006084d42c5a197
+Qx = 13dbf71abf20338b921dc18a6d3f61aa5275fc96225372cc7ac1d379040aa5b5b567c6a82c38503d4af6c222b0b5b17361e3596
+Qy = 050686ed315dee34fd39a136b96263399ccc605d589b55e08ed1310745bee83a254bc36273b076341b7dc0d0ecff653ec7c7896
+R = 042d1888533b5712376314f76630f361cbd9b8e1bc9cad1d1a7e50af2dcb882224df668fd1edb77344d01a253a8245deb56b825
+S = 03594f818301dd2ee4698eeaaacce4bf2b837531fe0418ceacc3cea95af44d3f8ea4a3d50635d51a6b06c0541153655064d0fa3
+Result = F (4 - Q changed)
+
+Msg = 1174dbba45864fe0c0800d0953022baeff5e94ee8625f7039a9ff066eae95961811cdfb73a4167ffdbfcb9c16acfd8bd9f4b486caf7b3c4ecb37316756ae78537c3315bbf8ace90bfd1c549f0ca0eddfc685a0bd2a5e3c2a53c6826247fa036068ce50ab4640a4ca31743b0e111190e79c586e53f0d159b40d65e53d45c5f498
+Qx = 12efb486aaf8036a0d8ccb9e79332e482f5832aabc6f8762cb223761941c74c64a6aff7fe930d1c89e79a2b31748b04563e68fc
+Qy = 112c596c688c9a58e2907dca089d2f4e239d30a1457eb88d32cc4a8cb6cd9f24aa20891ae957dfa56a777f2f1962b043d49a2c3
+R = 0025552ef3f956de4a9b8f97537c7912820829be58a4ce40f7afd3606c8c96c2d0155221e45187245c5c1a9a2dcfd6d7ebb737d
+S = 05b998b6f74a7f01a054be6aa5c7c2069ce327db542ce386a1c1b2e8db97ab984f7aa21f6a24593e7ff6f26e7211557f4a840d0
+Result = P (0 )
+
+Msg = 4bc2151f6c4927948d4d92f51360cbe365851e67af36ebbda3251ca99b6dc3b10ad2d565a9e52b48622b6a935b47b1da77ebd5469a09a8598668e833659b3cb2beec62d3b6af02aa55c5e960a41dac02a6cd48ac0e7f0fd522447e551e032b1a9f151dcb89404ec3f60a35c12bfaa469a00cba4183c639b482fccfd8945fd979
+Qx = 1d8edb626cf7fe16c3f14ed563a0ecbf6a9f0b223aacaa2fb3d7e34855b1b4a4e3e62768e1a3d954d1a11604c1522f8db71641a
+Qy = 1baa3906790f7638bdf0bdaaf85bde94c555f98a018b9927e562c8493ddb8c4e17a689b4e6252b09289441bf253efe12f057044
+R = 058c30ccd5dc0d4ca57ec5bf06aa06477287a657d9b06dbb97bed2caf2501025ea73d867a287efc72a2e504f6770e74e3e2706d
+S = 02b6fb00a55e553d9e773f450618100519d5b519a66a1def20139d17e738f90e583fbcc9574c130e83703f2bc033e3e66c775bc
+Result = F (1 - Message changed)
+
+Msg = 19fafa0e1399467ba259153fe9b38e1b556b737b343f0b2a016e75191836b2d4be891227739dc0970886563e0d82785f40d2e9dcef19b9f6cd52ef7a34f065b058c6c4d3f04d4dac707b4bfd957939551e11742f5b708b09e385c38a6180325e5b1cbfd88eb0e51e2db2228a9b97a6f42df07aa1894b2b35f98184433c38522d
+Qx = 10980df1b0b15ed925c62d8dcd9597484e166017e1bccc87e30615782d51cab5eeb71b45c24abdd42449b5a100e5bd49bee4584
+Qy = 1b679618f85364a55dc9b92f96f126fbf9d1ba23c212f1508780135f897ff4bf1e0e26346f5994242ca30048a6e3010e744bdaa
+R = 05696e4f300f50de70c77c47b0fcd0f0e99217ec7117e7c622f0490f3be56e009f6d75a3d3f2218e4d162644a72d543683a9e63
+S = 0682412bf4d4f7e618f840447743395abece61eb4c2d1dc17b32a69656e8079acf94f97bdf0c4d3cc336ff6b321ebaa69c1c128
+Result = F (3 - S changed)
+
+Msg = 7fc93b0d50037b8b8f3032c0d23828b8d110b6de3ecc20a9ad408baac1c0581be8ee92eebc9c100220be58e91038f45229f54fc0e0f81297bd271b183e5bc2aa8772c99a9292251d89d096079bef17a1bed1667e64d1cd8fa981c860eb46a2ccf2642dbbe1b3a1d6bbf4ae72a1f7e474d83e8cdf0f20d89571bf2b3d9076f5e8
+Qx = 0e71fb4a794661a4caa91e68149b0e578fcefd857ca4259513c1ddfa26594ea1652ab46fe5390a6572636af948793cb0e4c81ba
+Qy = 08d20329d7f2144fcdd85fead29c928d038413b1874f4014febf5344ea988ab128a00258a665acce4f79e8127acb73b5ba20511
+R = 010d109232facd3ecaa45bfcc7f986cb151c2dc76634804309fd4f5147da3987696698db3056962c27b6ac8005e8d32a51f8b65
+S = 0308858187722e98d6bc85ff088ff9f01f0f91b4e6536ba48176a4d0a7cdb963f54befed71a750429dec0f4a068721bbd69dc4e
+Result = F (2 - R changed)
+
+Msg = 4cf404245caa6fee1614a3e9ca4cf86e7476cf341ab5b86c3c5aab7d50d309fc210c3e0846f7727494af9c2ec805b630c824cc80e242c2cef68dfc72b9d6be3fd403792ae61e9b736a742bcf9b327056ab400c3834fc7dcd0a4a45b47aef83b6f9c919ee4279a32d7de7d602c293415efe7f01e8c6dddd1cb415ab657299b095
+Qx = 1cc74168f51cf3b5076832fcba31aece9893dcef20ea7baa186313fd8316475459f378d4107bdfab1c9f8ff53b5ba7abd77fc7e
+Qy = 012aee5bac842fd6c76f33cf61a4fb4c56548ad9ffedeb239ca55f73d659b7b3ea0a4e1538ffecf3118e330f25b6108670b6fac
+R = 01fffe004c2a4d191e86485ebb70cf5eb31af473bbb7f6bcc97466a7ceda5a160af1b018eb94afff3b84fb9bc42a5560c1c7ee7
+S = 009b6746bd33bd1c82a1406295bed21248e3ec04faf124baeb17b7f44f8c2b1d1dfad0d4bdff78a3b17a7f9871b7624a39be215
+Result = P (0 )
+
+Msg = 2221f7741856ce9a673c4c6b6bf7b7a8242c452d40ac40a2a1dce9f5fd937baec4159de0915fdd9418c1ee60a81d14e1b1414de7af3d93c850f2649b171fa2814227991a4f337a55ca06546d4eda5936769df0566fdd8483fb0c82d45562bb9bfe2a5c204157b7bed0e199e8c61fce8e050411d0f4eddad147688a760e7f268e
+Qx = 1e2241fd22007b13c0140119b05ea667cd93c7f8eabb1b219408c2b2770e18ce9436371d95c50c3a9d26554f2707b255007f728
+Qy = 1374c49a302b2ce57baaee5f29f82e912b128848de40efb4ab2ce38ef05ff5387e0e923dba7775cea18ca2777183610e4054008
+R = 0131c1f4ec7efe39c6b6aed9fcc585dc49921656dae29a50d41722c56bf4a40b6266355d85d57a8a9227815c4b6e78b24b34dae
+S = 07ae438541f657dca05c8d20ce1519661d698c989759d514ec10cffff85bf12319585aeee0249b20bffd6b8223148cca774119b
+Result = F (4 - Q changed)
+
+Msg = b711587dbeeadb88f0033310bfc0b0665072314c409a15e0fabe7d5b41c389a87467b2dfedb128e73dd5839bd4b0eb40846e37c0a059c1308a6376f243f417cd28dd5c4aa63c2ac71725531f4bd62483fed6c002e90c9190967d3e5e7464d53c07d19c41eef052e4992a88e0c2ccdeab5e12bb39def97434353bab2f3b663907
+Qx = 117e63458bb8c3980589e9781ec2d7a674a93071b2146b49b62236037688a08eae510fad5101b9c26c442f193a524f1aa9da488
+Qy = 1bc9c50cd0bceae8319656f52c2e8fd6898eb5da470923b22618640f35ef56a65df2339d6da70ac4ba723d1e5cadf27bab60fbf
+R = 070145f2ddb32c5e7475ba810edec79ccfced1a0c9b387992cbdc11239fe0d8cb431809a7b412488afb7422ef1c16e970f82af8
+S = 028ad78a89cf01e3f63a7c1506f8be2206a877d968b49121af7cfc8538cccfbf35638bd1c5b017a65c9a7e115a7466462a96c7d
+Result = F (1 - Message changed)
+
+Msg = 3ce1007265a280bc8e199b9e3acaf69c2dc70b8f098ef61d6be6b25e1ccc773cdb1a931e89f954375d84c2ee9e225a2457c708d8503b6092d2dccbbade7cb00e8e89e8c6ea8b5f2bdc26b83c598c119a382f990c05118bacf373187edcb28f7519860ae00aa617078c29d3d2630dbb09273c054c508b709382fc3beb5ef62704
+Qx = 15388c89f2a2024b1989feed0f1831f27d10998f4388d560ae6b7394041138c8ed88ac8bec9e6c8b5830747722a05c975b7c3e2
+Qy = 1cc91f052af018b8a5f7ec95797fedecd40b63d8cec1f3869c68768c4d30d2b3fe453d669a315621355d1ba99012f423dd33184
+R = 0784de0f66b5b6b12388205b40db59f7050e1f45bf8bdbecfc06008939892f2745de81825ec1dfe2a261b26f08c73cfc17b796d
+S = 035430979b041d8314e94c782dc09797a55f85f11988af6d47a4eecad955610007cf64bebe322741118fa3e3823b07e48356477
+Result = F (1 - Message changed)
+
+Msg = 999f4f26935ef6689ab166842fa80af698dc0c9509e388d2f165c84f8f33977bd5cb72a83f38ccdd1ebc77824106edf714362a4df6af5b3fbed8578fc217e2a725790e2d69ec0abb2a4f566793b4302011ffc11c2eb5bcb6f88c51d608c6d274b108aa69b7897c07f0514b093639c710696e7af28ba6ddc21b456ab522eb905b
+Qx = 00f3c16b73303713cbba473f59b01328510f6c4b10752865ca1219b9ce1970cf1ca543a2d281fc845c21abd2cf0751e16bdb62a
+Qy = 17888eb61b5f70bc0ff5b68505ee290e127202304112ea775ccf26bc2e8b5bb32eaedb17ebcd4af64ad0fa79aa8d37c80b06458
+R = 0547f955a0c54a13e3eb7ea3efc4ca0e37ec2d4f30b024f46ffd127dec8b6ef2558770abc98e905ba4f5df8114a5849b7469afb
+S = 001be8451aa2049598c17aa09e88d38c723f5a634486c5b0d294a5dc038f594fb663743c564c8012f07a74d3ff8d16743560f6c
+Result = F (4 - Q changed)
+
+Msg = 64c663c715707fdd52ee61398467818aef7359ce3a37364357eaa5a656e1009e46e7bb7d400c7f1932d13d453f5cec1e0a95cfe2c873821ce63946bb03eb6b79bd0ea247af3d75caa7c2e9b0e71e9188ccaa0bf6db1ca5845d2d469a822ad680ad0725d15cbc5cc11d9e2175e4cd77f79a330eabb346314bf0a2978a9b53b93b
+Qx = 0f5383301a7dda1c90bd4c399884c4db494c3fbab762727ecba5fca846e6d3013d3595059235ddf444d383bf8b9951cf6ca0c8c
+Qy = 0d67b7952444753c73013b80a98d810a18615ade1f49dd3a3c2f7af03e19d7e29a0054e02a123c22892c6297826adcee1693ef3
+R = 00afa56237fff0c4ee0df71d50caf4cc53d40ec89caeacfce77a41396f0195b90392956d9f1f95a99ebd688aced3caea795eec1
+S = 02bdf6eaed7224f3ad8a723a15924fbc30e84e687066deb05623fa268dfc2261a47a659d2a70158047a4fb1c22d893cef582154
+Result = F (2 - R changed)
+
+[K-409,SHA-224]
+
+Msg = 25e73452b0c271dfc6bbf3e1a8cfac82a8b5b81d36f5f52a863de78437855b51b22e501637837bc826a7014ea83ac30a4b16354764e63b8f3bd5dedca0e65ebcb3be5ce8ed19a357404eaa0fb05315da514d4054f1aaf4126a6d09860b82ecade29aa91aa1b710114625ed06f66e038c4019ff4598caa5d3687aff4317afbdde
+Qx = 1a51dde14b9e7bf6241a944d98d8043b694f9eb5067eef94147fa74be4b86f4de5ef03e9cd712698689530f921662abaab4df58
+Qy = 1074c551309aea23b1f2c07ed77566a4d107a03a3af191cb970982f91834dbfc7029dca52d841ecec6acc1fd004342f31fad521
+R = 002e80a754f5da39ca65527d301120b599cf813e63e01da7e9ad654e485ba0be1fef518580190d1eb2e1e0c792fd1d8f8fdecbc
+S = 028347336474be299fdb950c5a946b5dac4455bf99fed14f0b2e97cd00665271186cfb926025d256bb914a4fca19cc112810faa
+Result = F (4 - Q changed)
+
+Msg = 28fcd402fc1bacf7bb54e3521c8a02f49440b5bec52b40a5086deb3ae19d763185657a0b321e5d43fda1cc9da30646ab61897644123ce0f1f456d6af0df180c210f1037e4f85d6fa2a043eb42259fe1930baf9a1de10a78ec034593aa3b51b098c0e9eecc84dda0482c1f60175e5bb440202da52316f794ed5ba4d7ffaae0f57
+Qx = 06fb08f4180bef0a636e2668ae606b42760348e1c602c197a14a674e69cfe9f65af4b3e42582aaa88c261976887564899d5acb8
+Qy = 1b96da1f41e5d8c1330d2473c252134639e7e6d8755b37f3f8ae856e64636ba773f8363c99cf30d2b18d8ae4a7e1f5f63086290
+R = 054bbfe6336a7912fd612453e75e4f6eed10694cba3a4fb7df62d4b85102cf7e97005d503925d3bb30706a261dde7497708d376
+S = 04e7fec9c66e4d7590b32af2500158b57900b6cd36c6743d234ba150b110290f74eceec2b3a85be82bd8db2f0317ff9ef504eed
+Result = F (1 - Message changed)
+
+Msg = 82c8b6304b8e3edbf11e98094f6a1a7eb462cdc09ab9eb1ff71a657ad8996113fa94ddf6174e03ecaa22e2d6dda3573510f5fb0e5f0e5f43bd3632ad5a25e8018fc0d03d0aa77694abef668cb757f88ba1d08eb4ce7189c2b188069f9901f44b6cbfba9befefe71122840d15e96d4cc5cf7e7f817cb8c43f4160b275381011cc
+Qx = 0cfac69a763a4f59f4b40f97d42889cef65f890837961d1f0b00fd8812cffc5f836e4e224b9bdc5597e5038d6c32428e49ca796
+Qy = 0dd5a7f7bc81d0dc82759c67cdc988a3286f311aefe646f0a0daca098ba0a9986877d4ea41130826844dd0bc7481ad84aa389b2
+R = 061180aabac8350a33c80dc576eb18d15546d6504c78f3fa9880b5ba046652cb5aca70171300d940c6ffa6c2a7b49d4e38f87e8
+S = 06b5d053e5566576adb8e6ce001d9e66241d35a859bac2c903dc8686283bd7003b8e41384371c775189e50164270b5ceb82c569
+Result = F (4 - Q changed)
+
+Msg = c777aa6b3ca339a4799f20b9f951ab82c432df0ebe80aaf5ef0e72bdc8ed888f18c44ad7c41bf7bbe0c8f627a530763907b1b2bed6c8bbb01a2c52bbc5c51b2fd0d6f0eaf206c2942973fa3d6aef2dcdbc7330345b449accd7a58c02713041401f37006eabc5a060b3e587cffb20423394429acc9b300f83c3057df05481d42a
+Qx = 0c3c52cc679be17bd044a9029074093c3302415fb025a39fdc88291a87ae4d0127e6622aa6f77fba9eb33fb75d7bd2563c3d5c6
+Qy = 008cc865822434e0aa50b6c1d7621cbe973a9ab904e36260d6e0d45ed783fe4d8aff639f6aeb0f0269c2f4911f376c89d876d5a
+R = 046e06ca1df5d90ba4a26ee8369f3c93b25e631d408649d7ae80c033ff159b1c0b97c47abdc4d7dd769304c13e862fdc3c80a43
+S = 04329df027685eed1695321689be8811b1f308e037c88b9b7a73c72ef56bf01fdb707c1b33d5ad747f65bf5371b9489c843e3cc
+Result = F (3 - S changed)
+
+Msg = e670a3b76de2dcd84b6f8c41180a2e90610402ad3d51297233e2a2c10db38185c386c8cd77a95f997fbbab1a851b7394edeedd66a7f97c1ee8513084a409c5c37836dce97b43b441d65587a4c766627b0c13cb1dde3bb21007a8fa0d7ee989cc132677ea09cb3cd9f88ebd6d2a2249a803b6a42cf8d1edb5058f6c16c5a4897e
+Qx = 0ce761c7cd5cfc7038212e5c1900e054706806d4d9ddff81b59f0f74be02b124b29d84dfd1608786a91cad9b1c466b19184b5f8
+Qy = 02232371918cee9812fcc9ef0e2a468c8428bfd14dd6eb85cd5b0dab7c21819d21e294c15cdf80904f3784c76bc7b12317991b7
+R = 014d47f013275de5a70421c3b650df712bcff550eccb52f9c803e1230d04d8f4a918e149f61091a16d71472d4772a7cb3701573
+S = 01018a75b75017aa19da183a384da985fe3cf16b4c2ccabc1b2eaae03f8ab25971342f288c1d4d5d64f5f9bae232b583a0d7359
+Result = F (1 - Message changed)
+
+Msg = 20dd31f8383c2f00ddcde7b4d601acbd50359e6e2917d08be83482dfb88a27ba3c8fb52d200db19b02bce9a40900e929215f0b0b30f85bd2b5f6f9499bbdd44b286f313b7ef3de4ef95dc3f6596c5ccb0e65f4e5e2523e7b86b39c5364b9be36d7d5da81869e481a744ba94e9444cee7eca0f4a35c03881b8a3c2f1b1671590f
+Qx = 09376167aeb5849d72fa65268567ccf479206f5a4b0c11ddb73dc3a11b1e8b49b27b1a1c8c5b7b087c5fc5a8d1046aa83a6725e
+Qy = 11e617b776856bd55ff8350173a3b0f3aa84e9a4fbf703570388bd4d22e8357a1fdd42c1adb2ee91bef62c24ba3b4d062a2d58b
+R = 02ed6ff1c6864ff85ebcb5521b525d4c51e0e363f1be99b0d84bb42b5373f8a61c31685ad7ac675b83b44d71a1f359a2a6d2666
+S = 03a5c81214ef2914d6fdea3f85b89b2034d3a62c0c144c0d54706814be9b62b65398d2aebd3543092d349bf72d5470973c6469c
+Result = F (3 - S changed)
+
+Msg = 52638aebf7fa01e6b588e2b3cacd0192b88cc0726941f2ce253859722cf1b26eae13b8eead1ca04a8636dde0ff64fb628a062c01df44a64337ef2141d5cc9bb47b700a301c073cca0ab888d5973f90b068cd8ebe7f447b3b3366c495c685a9a02bb35e4af65c0bcb942caabef7e352e119156688b11edd20a213d6c5d2671b5f
+Qx = 015367ffb7aa168d676604584fb690d804c702533ebf5d8b47d323af53a5ee367cdcdeee5061349ae912b3fdace30ba890e690e
+Qy = 1a065c08db546ef584259f46670f2ad166c8067955b36dbf0b62084d121b2bcecb0cbcd61a4ca05dae707605aea1bc76ee8a8a7
+R = 060a9b4db7ad064d0966ad2f2f6ac7884024e2c50cd536eb9c50e66a957bafb02ea8c49fa070f157644f099816f003173e38155
+S = 00ee3a73b7202bb9d7cb62d2f97dd88409fc6f37c462a08faa4076d00eaea91506c29ef4204d3d6c7b8d9ed607365d2b21f139c
+Result = F (3 - S changed)
+
+Msg = bab02a9e4d99fa0a07471065fb2338f3ea0bf363f0b28426b6705d68af53b5815261c5ae48c65d4a688c44146f91230722ed6303e4946b0acf5315c3d0e4a0380f083d270dedea2ff2e5404bd49da9232b2b10ee7e6a573f29456bfee106939a606fcc8a3cfdea88627aa5a0f783cb09c480bde75f72e1dc68dca5e5a19443f1
+Qx = 00a5ca0f24e0d49e77503463d340a82cff9852da7cc3882a907dea4cb11836dcf56235eaf221e7c6691cc1e05c029a90b9bb29e
+Qy = 04b8eb90b5b72dfdc1174af19429b5f926f3aa4da8e9bc7eead6bf5b6ceaf48247499b71973b5bdd687d488855edb2ad01b79f1
+R = 042ad6e85525707c2d09592960c6e8d65bf1bc10ae8df901ef949b582a9aa845c9691d5fedc1687d871853fefa23b69a2e6f381
+S = 025b222542b3d9f4cf8ac989e94d4ff302051769ff8ba262fc1d867de8691704eb495df6792b74f8e597b593998b003560b1fff
+Result = F (4 - Q changed)
+
+Msg = f877425513c79280a30ad6ab3be8459db81de7aa5ce44c28f9fcf3e9b3538a8541963ab9126b5033746a1d6e6cc124b6c7b461eddf502c812e646440c29dbb851e7870c126aafceab1f400442c4432ba4c7a8a3f5c5f6c6dcb98f88cc40961ab02193b6f4bf521c2990fcc004777a3f9f5adcb18ab849dccfa6fdc5065f2e006
+Qx = 0e66722aa3620d57e8d297f8491c31815736d4a8d1f4b81c560c05d79a6cd6ead77577f2475dfcc3726c21240bac0a9f9426abe
+Qy = 171a3d1ad3f0a542ef6b833c87548677f280d5a7473a9ee11307013abfb96edea03bfa4457b62ea1d35b40bde4ca4c4186801f4
+R = 051d4ce29992e72b778616bbb33a6a144657d2219ac26803d7ac20afd0265664b8dccb10cda10540de64d3e6dcb6f5ead94428b
+S = 003444cce2b928fbbb29d86defe599e36ad5dceb9c6f1c514b4513c73cf6d321d4624427da55ae6f7f72fde4b3b0e29e4786c64
+Result = F (2 - R changed)
+
+Msg = f92f40e1a7b64197430d32d80c38f80b03ba86b09fcf95c5e9906eff7781b651f990aafb573f0a688cd159eb5c1014f08c45cd718722d4f20ad2b68dbb9ea6c3eaa7527ff827355fd033ec146ffda46b982157ded724bf724c63830c8c9b03636b497c8629f8ff01e3eba9f080cb7a29cddcf881416c0353b7fb8026d3de59c6
+Qx = 01fcd89187c98f0e079f78287a0d16a166e19e61eb18d14056c88d8435185f3303a4038b5175bf6f5e8b856669cf6c0b3275dbe
+Qy = 17308944137b303cbe6822b8a8e2c71cfd24e5abf8e85dcb914a2f0844178377def874189ff45ea9818cd530861ac27052f1298
+R = 01549121d2e0e44ec3ebfee626fd4746469c654f03673bd52998f4d1f22888affc8e2b12f2f5f7e19a6207eea459500299fbfbf
+S = 06c56331f0e31abec84d5693836ad869eaa9c17f206937bb9e7e5f0eb8bb468cd25e6bf14cb6fc403aa17f33d099c3cf6b3b51f
+Result = P (0 )
+
+Msg = ae4ab6b8a592d67289526da60f22c4f92b0efe612746248e117ba83ba0beb4e24e718441242e882f9e82d751e4cd0ff30d906585fcc8143b2dc4899745db35e57d38d6d041830fb87ba50a7e82541c89483ed72d1dc406a2ff415fff536148eb7beb4a5161b6365509e91a22a195ca89840f0d6b2ab240044fdab9c0e659c7fc
+Qx = 1f61ceb27606f95bc6468e0bf0cf6ef52afae188c428f6ca29b8e5d6ca7068e6e5a6dae4fe255fd5c1b3f17ffef33d404c05962
+Qy = 050a23356640b92371ae6092e41e4a0844615c1f43fb5f8db96c22f284c7e0f5485350d92baaa41c00857cae7db1750edc7e8ed
+R = 0487c2ea8430b13e6ce1efae70006f06796b58efb382aba3fdd096b24a0f4419d59797e481ead362af62e0f04705d5b79c12418
+S = 03def98c4bf52eea5b38f2fca761ec83c1540caedaea90f01123691b49d0c86d68697ae674b95275394d2165f906bad94450924
+Result = F (1 - Message changed)
+
+Msg = af0fd6359b62428675fb48d89b0b5b2bff9cbc591b5d39e9849c7beee96e837d09fb65e15ad3e5ae2101ebc51ae7cde771afb37ea1736e32c59ae03bc628e5cf0db159e39770d3d2bd811cc0348ed142e59385aa3ef26478d95ece3e95623cb05b320fee964c1da0c1758b31c2e40893d203657c4f20373ec6ead52b868745d9
+Qx = 0cbf2658aab29eab6cde6fc8f224ae41b8ce95f5f466e8974ee3e12f1d68185adbc1bbb5ca990a6794a30ffa99d449c3daa0a4a
+Qy = 14dac0776a4956b4f0ea671e981d5065a9dda030d0b720216bf104295880b7499814a327eb20295d4f2cc931cd73b2898d3c06b
+R = 03cdbb42e49facb2437303a7fa799cce3b8f4659042d3c0fb7de96c3d221e9360d099b0c546e490cde4e2d13c2911e4fe91ce4c
+S = 009491ccd5add2c906e5bd78cfdb751cb7d383b56ba6d1d1f79f8d2ad7497d5d7ca7a784fdbb4faaa7355160a80dfd97283e2ba
+Result = F (2 - R changed)
+
+Msg = 2c34e969ff6ebf0b6c4b3f1806329ca272aa1fcbb8e07281f9c923822d6d6aa4e257499e39449ca26ad93db8e1e4572f4edada2aa8428f17c9bd0259551a80bda97304d38c7324936b72ccb0449476036553556414b81c28a5e599de3e5458ca4b14d8c840a0306e74959ae509ce05210e09c4166cf489bc5329ef1c0263bf43
+Qx = 0b55ab78acf0705566cf5d45f9a56492cbe47ce4ff23c1558ff1fb98ae7e68fe0f4221680c1bd4dedbdd5511fee8cb43c5ff888
+Qy = 08e66bae2db75717eb635fa211acbabbdc5077864caff65d04802b3cb9aab9fada21279d7ca5a983223f39a772ae9678a104c5a
+R = 03ae184bf66a0991ba2f5560ff43dcdcde7dda69db5ece674ddaacccb38be52df6d10cf771a4d51d0dd4c85a2527be147003bfe
+S = 026fb07f158e4be060ad96ddb7110b84751fdfefff88e6d6d9e909397074b1593b5bc0485c6c5f446875ccbbc8a70a8ce724e63
+Result = F (2 - R changed)
+
+Msg = 274aba96988dccef3457089c99ce0e47cb37ac6e7548bf959d21983de26c3f0a256b4b58bce166c1439e8365d19c3cb870c4f8d8e1693da56ab9ea32ff7456ef317a75e7158b12e31f9d90c8d152b2215bcc89a32399d43fc6358adc331df0f4092771fdc98cef43c618880e3e725c5d54c060c79209671e12d58041a0b0ea35
+Qx = 19b86473a6c776650c4b9f24b2828c2f5aa48b0e7f07e7491b5641c5a336a1fd33ff62cddb2f2e370916a8e3d1f35c8bf6bda86
+Qy = 0b8cdafa5eee67fe715feb8a29e46291fddbeeb1a347171577f36c568cb248830d9b0db476828332201238cc7202e2167010e15
+R = 073bd1a1936b163b6ff80a492c80107f9471c85b901b4ee6fef869efb15e85574957ea20ebe3f6dcafac4ae26cca55d75a8522a
+S = 027b817c87edaccc9bdf18b88e899ac6e74084212dcac6d9b8207d3a914ec839fb1d4f546ad347bbb9c949f7bc86081eb4b21d7
+Result = P (0 )
+
+Msg = b4cd2d31e6b256564eb1c29374194402b9b463b46925ff69f00e5e0200a78fcdf98bf1cef9fb9b54a954e0ccb96a8486f1a5a143c511f952be4c9e928425cc967cd7e6c7c48357797608ba49806e0d90d116333972e4b045dd122048370124c46809f5104d2075fc2d53033d254b3e335063a86e53c56dad8d9d5030840d9e75
+Qx = 100fb187fa798634ada8d5f7dd61a8b18c5f8cca08be3d3e40efbc3aca63e6b506260b4b94fbf0a0d7faa2e75ebe46fb58c1c5a
+Qy = 1428f99a262363236b0ab6d7458dc879863782af5a23475b08b0411b91c557609878d4d62008a2972cc0b38611933818786b7df
+R = 012e95789782f35d1ef47e0403332af6c46b2f8ae2a8f4bee042ee03922b75340d250e216599058f97a1e3edbcf974a6c7fefdf
+S = 023d5516bd31f49295931608fdddda66bc9a57ddc084934c8dfb3fc1b22e0dd353115c6f5942364294b1111732f34d2cb23a83c
+Result = P (0 )
+
+[K-409,SHA-256]
+
+Msg = 4e6b1975022764fe16417ccb9a9513dd2a60c1448626d5bec7b9c6a6266d12a9ec3eb7242cfc695b086c5a179e741fb773165c6bf14b7a96f7e6263eb1b81ec10325c5406b19833b01fbd1dbfee4a5b31eb1d5f0fdfc84c6118d9f6588e7bca04cb2e1b17daea3d87e0abba86e2f33adab4e5ca0de394f26b41ef66e963a21d3
+Qx = 1f6e283273c627ecda2f69081a7472de9bc2bba93412f2ebecdda4c983e35012f4289f278ef1bbf9a480e82f7480bbfb9799386
+Qy = 0a9d3ceff2a4acbfa4413351cfc60506ddcf878a1fce8b194942a221e166bd0aea1b6204e8130c00e819d689ca18b1c08665fcb
+R = 01b3d90bc9df4a607818b9f6352d952c8f670797e67be2b04c53222076d46d533afcdd5fcc897a657c7db98d2c7452fe579d460
+S = 00c8a8655fc26ddfea3dae42862d7797840b765c75eefafdbfdb747948fa4add8cc219a5d4173d454537c12c4331c8f0b863c27
+Result = F (2 - R changed)
+
+Msg = f8e9604307cf7bca2122c7ac4afcef38ac501b35238f11a5a8f12ced823d833318e039f043b37bdb7c6cae73fe44a7ee9142c1da07819f0d45a300590d8affdd74d47f175e77c93dad7bac5c3f15f1414b97222c1ed76bfd13fd93746dc79fbb12be5475d7e1893e5fed8fa8d813e7e726e60491e98079509ec8709186200ca8
+Qx = 1a42a2fc34ae1c62eac5fec8e7cb012ba676e0f2733ba6f4921e55ac4a556a0d46dbc952c95fa66277973bd35448fcd092869b2
+Qy = 1c4bd0a23ce527980efd9e9af4b49204299ec62bfc53aa2c4df5c4dc9d8e06b32aed0d23f315200333b432ba59ac9476d2bf63c
+R = 037e7387ac0cfe5b34389e6fda5637e02c9c2dcb479eea30db9b769cba8340b1ed11878d8e42fc2af988d99078af20d9cdbb5cc
+S = 04872c15a507ca091e5fb9579ba87637efad745db54d1d18ddb24f004fd402752429b68bda20c488d5143c5de95759d0b5983ca
+Result = F (3 - S changed)
+
+Msg = f0fe4aa41c6f5e6fe883a2df3c64c84afc7e00dde677f9d28c7d4d8896d6480c942d6cee2f7f3ae0f8c8b49455c1d1d75bf0b21e5c65c8eb2f3c57395a4133055490dbec08393973943d9e3ea25f08474c9fc4276033adea4022251b7016ae7ba5e18138bb2b7d4baa69cae339e96a705c060d7f97ea617a9496a108e768dda1
+Qx = 0f063a250b677d6d4933d62b89614b5ab184fa8d52b6fbb5a45e935478d202a0c00af3eea93ad2d650fb2dcd91c166772ee6432
+Qy = 1396fc91817862792be962eb45c9f4889905ad5ed1b136b441f3354f3801b3c98f13e282b95d39662d9e914d23bd67e2a1aeb7e
+R = 04db1b7c59de49a91528f71b269f62c81d4bb13ad95b34fc358f7bf7afcb399ac4096e7742e04df8cf48292b39fbff53c429b84
+S = 01714263e993c04be72ba2412963492e3d9d0d66f2325f25049520b19662b2ee51d7f7cba4952c1b5f9cd79dfc06aee09e27823
+Result = F (1 - Message changed)
+
+Msg = 4b5482770df140a8588ddabbdf2dc2176b5aeb0838f800c424f5492e34414a0bb801ef5c90b2afedfcd3d96de0f098f3de3bf3c1a7d301822e19554ed338a6a58221042c8ad5bf5816cad9bde2427674435380ed7f17c38a4b2ac98a967f34e2b56a3d835e560ea5b8bb48e161afa06dd9e8c17322f5a8cd7b4e5877e4305569
+Qx = 19db5e3be49beab0a03ea672ef15386f9416eafc0d495aedcd3c76fd4c60826df8bc346b5006555dbd9c8263c124a311a8dfb0c
+Qy = 0ada764893e2b3b6cc96e138b2c8f0176aeb84d4dbe7f495432fe3b92849cc30fafd125e827c88d41f5bf3b60babac362605ed4
+R = 03694726bc2cea70f6875ce61c35bd0f98fbb97f7080c591c3b55be8eedf2db35d49767532a2f99ae0034632548c6f314693d23
+S = 034bec44167238c60f94b6f6ec81a99138a54654e036450f85e65bf9c63c00b5d6e1a187ad1c092575defa3f7775d6621892385
+Result = F (2 - R changed)
+
+Msg = 20a9e879f3a1a82a60c9aae5422fe017c36fde89604e23bbc0498b275df54076fab9286875cffd8a6f571a8d5eef1b8708a8e4b299c3ee9665ae2c4c8c90ea2277b63d88b2d8134bf5f8cf4f2af47c016387fb617380c8a8477e2a60f8c0197a477fffde173aa6814542dc33805436273f258a63605934d416f0119cf5c4bf29
+Qx = 1c66a20f3f23401f6ff01551d2fb8dd5e1189f878267846f69c1970986b3b6efa04e2ca3439d1605cd947a088f29274c56c840a
+Qy = 10d54fde54e77005cbc97276f71b58b1dd38b0eeeffc7c7dc2ba2453608f9e7c585f77bbb7cb3bf012ba359446cbd07051d6bba
+R = 043b50489fc45049c7f3218263c5e14360fbf7aa45051ba9aa088f700032ca71f9ca4924dccc7cc4d027186c411483045c1f522
+S = 0460acfcb0c195bce3edc9e68f2718df328db2ace6d9117467ebf3ebb3ae64168966f3ac2ba6493d475c0e1bdb924af6a2dcc14
+Result = F (3 - S changed)
+
+Msg = befaeeb0171d529c983fb3431d05dd473b4e2319c1f4db7b93c6f1275ad1ccb8dcb938521f935113283e225f3bd17c047868ae27405917e46fe93b8c3cd4cc946c4c3215730f691bd0d43478d764d772c0b4f0267c6d721aab3096b1fb3410ee4de0e5c3ee7b0923069d03a5596c138f7e1930932bae195039ec4074c8a9579b
+Qx = 15d46b0b61111479a386806d9446a4a4db0b183be5c0fe2b7a2b64b308dbd03955ff257190f601fa3c18071a782a3fbb9e9fef0
+Qy = 172f22515cf3c4a98bdd6e8854f5edcae4f54fbb9fc66217464b1ebe97849666aca457c2d58f40173a2713a61757b36de4a07d2
+R = 0447b297df9f6d38a932126d029398ddfb521eb112c78dc4b09c22240b06aeca5982fc1ad2a701244e616a953f88365c47a7c91
+S = 01714ff8f6018ef552f0ea3fdec65176fda2b4c9bc94a4e922083ac97f0c5754e43e92373b2a3a9e5c14dca7caea90a4a527ec2
+Result = P (0 )
+
+Msg = c102cb7cc816a903e1a5af198c369641cb11433cb58e16e68dfa6e859432fdeccbd1a56371276292ac8350d0aaf7991ddf424041a90209b82c74a8de5b9557e5b3b9f2241431bafb29187d289f8dc45b22a260e01b249d9ac3fe90671535335037ec2d8c798f37c0f06e4056bb829386e02314b3d02995f28148e5b2cc1ac562
+Qx = 1ea708ba4bd5d915f897f95d4d5007af49f8f19564fa82f12d091244defaeac8d396adb0bec5350c5574063946513ef4a48395e
+Qy = 0a0408805d33ba240e8e8cf7535c167f9afc7ef9460777385bf273010b2c672e046ef0f34f1148397a193b9d6c9ed2431cb5658
+R = 03ff6120070664d097f84afb1e88fd93c10378621deae6df2e31de393437ec8f5b8995b63c0138af2425cd5ba5155b02b46865d
+S = 05347e9f468ccf646dd3d01084537ed8d01f8930643cb1f4448d0914e8b8ed3091bf7f9b7513d24270de637d44bea5e16ccace8
+Result = F (2 - R changed)
+
+Msg = 9636ab96a379d452231fdf8ed99e42b9cedf8183eb810329f994b01286aafd19887b347711482de94bcf12b8f02194102a9efe2b593c43ea396233a77edecdedcf884e0bdd2e8b546bb4bcdedb4866150ddd573d7d34e3e345771b5ec3b3814d96b7d92ae0b977cbcb496b7b5a733c5ab2c7252e1f2d948995c202d125cd6bc5
+Qx = 03a67447b7a6fe71082595eace14335714046ce8fbab880cca441d55721a9639a5cfe3b64a5db146973740eca25cb4156929148
+Qy = 0a58161ffc25fa2a57aa11722a6164c4a0ce5ef61718e8f84740d7fdf59aabbbe9af438110beb01f0801fc810952e5cf4ac45c6
+R = 054c5012d77ac38a4161250148b51a5e12ec3f172fbddc1fc20d9d23b8ef48ec5705159b4e204ecd5ce95e21589682a22debf5d
+S = 010b0ecbb778e2b359c40399ac95df951fceaed5395350dbd85a1dbdbb353bdb388169bbad453bae2aa39fb419a7dcf253a5ab2
+Result = F (4 - Q changed)
+
+Msg = 71c969fd30efaee51c04041930e8b5ea2b856f8e1718b3697a5c2280b4c2ce790331e376844f5138556409509adc76cf556d2ebb09f374e611621536dfdc9d7b82775de74ce6045aa43e235cdea8d0406a96084eda4ad5da2837d0323a1b064cfd23f6fec47cefbbe666745a86f76ef268ae485a531f0fdab845864932f6ff13
+Qx = 19bd39737c83926c7f390b8927cd626ebd05c690309d521829947033a03c8779f25c3588295fd09067cdc303285a58b8768e348
+Qy = 1c698cb1cfbaaabf9b8bfd172a4c9523035535a5c6ba6a7576ad15938c3ec925a5312935b0ba0c4aaf6ec6016e3357f618b8325
+R = 04d9d06936ccb952940c4796faccf2f6decef1d1703e5c867675fc84c0a1d121222fe2f45baa71109b4e4f453890c8fd7e1458d
+S = 006592ce8377cfcae372d3ef2ed3f2a373c471fd3489c857dcb98194cbb1cb245508af4f56861fe7984bad20226b960fc5ac717
+Result = F (3 - S changed)
+
+Msg = 3ecd70a383f47f7c65641fb86842b3346f32166367296fe1a06604fbd5744f230cd9745cb45ee0b18a510e7e77f3db91e319abd82fb42d05f8326a64e73c964c45debbde9de2cdebfbdac5cb19cfba01da56169567ae411ca7c3590ba7b6e011f2f8c4a98f52d49d9d4e2d22046ed0c74587a8c129ff7aa24873649155109804
+Qx = 1be644cd87379a46b3c2d7575e8ea187626089a5cf6e6732a47913202f12595bd9d2c194f2ce71e2a7fa0f8c53eb616a530a20c
+Qy = 1de1227c868e029ba29ae4b08ee4eab64e9db24dab39e3e24464e626dc44975a7865aa3cf953116143d6d24d90143485345e77b
+R = 03db5fd9ecf4aaa756db3ac58b3fbaea9888b69dc3440df686256e2b782104609e1b4ba86e448814fb370a2457fd1601698887e
+S = 076b9043fa6e47c5a5a7cdebfd9e52f06ccb8959e56cd5dfcaaa9edcad94ce4bd936fd45ab8fef4873928151d19e2a9f7337c31
+Result = F (1 - Message changed)
+
+Msg = 6998564eb37fd0f84608a026d40ee5bd3d6089365c818b9aa0cf67d331f1df4657cc7820ca45ceb8b96615e2ba9fa4874ef7a3afa69eb20ee93ef9551bda21d5809bf33d6a6450710aeb36eb9014473c861e363a03a7d9901005f639a927ca778edeadd90440d96b1f411ccd665c215cc54d0a9ed6c4c573611f05fba98bf8d0
+Qx = 06caa25859862964d7294a903159742279d079824a08b800be1faf8ed251c3904d5e181eab2a8f13d8742a281d51eaf2edbfc04
+Qy = 022edc714dff9a0b207a38da0bcf2b699bd2d56f4f536340a05852cdf5e337ca83755d6955fc46bd7578ac73aa1c918f896d23a
+R = 02b6d403b1014bb2bd8fe4cfdfd7dee1ac39db600eacd7bf320144092978d0547249e4c656059f381ef65ca0071be58f306c719
+S = 021c4ba6c7fdaf60bd027ac0ee6c7ff170b189e51187f33d71e8102de14f97bed8642dcc687848503d6c7d3119ca157cb577068
+Result = F (1 - Message changed)
+
+Msg = 50c0e9dff96ce29c6b485e885c90b10626504e6f089fd8b00b4e6ea425510b7fe34e796c71b1ce561b552958e00c17cb1b3d80542f5adb3b2bad804dbaa458d8f853a7351416616f6dd3a804f26ce2995c95331a6f4c2f7ff1b0b1691e3c90db6c15e602fe98643c7d84d09ca817e7d5144261d376300141627e1e5691f33ca8
+Qx = 10a6fc4edad0f3fd48d8babc527a6fda8ac11ec79bf5a0448d76880189552f8fe3ae3de01d9d5e63021db7db60f75e73431f06c
+Qy = 1cb860126ee31c807186141a4de5be25afee780e1349ef9bbaeb0dc68649e3b3bbc3ae828c05b457c0017f2d809a3d8f177ffdb
+R = 0501e10ea55ab1ba74d208b9857881f846397ec6860a1802d889ffcfbb2f0a4c9d7e73b142767a603674781114ede99819f8236
+S = 011012810e1fdc0a299d8b2d5724f849cad241b992015f209ea11f0816921217c6e4fd2bb8fe4943fa9ce2735e91c359e73ecc1
+Result = F (4 - Q changed)
+
+Msg = a29b6dde91d631e3af6769e75a5bb664ae95fd64be0342cc2f46edb53ef020a552b74e4bf1b03d80946106216db9f0535bbc5899783dd77dc4fbcdc959d8368d190e423d59ca41d84e15bcb277b790281b43211e43b7825eb3c18a78abe7de6a1253768c7e56f2bc732e0b7d1b999b7d0b18a1d0a6138d80eee241cfea9a7eca
+Qx = 1c632ab4587444aa3481d62249fe020f64fa6805407ec9a6b08636d75efe843f63131b330ce459788a078d798eb2a9e8cf90f32
+Qy = 0becc3ea65663c54678fd59bdee3ace71b2795b87d5194db4abf9c01c5ef1be74d373739f44c5182bdefa57fad26b8491be9606
+R = 058beb756ca9c631584e127ff17079f9d7cf1547e283f816bd4ae4ef74c4531f29a60468396124a292205fc4f666b911a67eb78
+S = 0484f9eda2cf664cf98ce2ce4dd1abcfb2518f00077d3f98d4cec0e16ea8428ab8afe212123615b4fdcad4f54e3cdc796613c06
+Result = P (0 )
+
+Msg = 9cca8d5d8efd4a815e1c410f846e1642efa8640f7f29cc60be4b6be1128f81677a7cb34ef0e407bc8d38c97e07af6e74c3928cf4b47129604b05f38461c4ffe400063687534936846aadf8e777d4e52f7066e3abccf2c8917d69f7b858860737fc96f5d2a3c68aeec61f657ca6c34254572c53c16fd5dbc8d31f01a19379af20
+Qx = 04fe27d48fe88d71766755819895d710292be5b04e83039626cc4efec4eb118c461fc12f9715abf19568505cecaa167378ff122
+Qy = 0abe19f36a4018b0f7fa477648d9a7732a040eea749cf3aaa91680d63fa8239765150397f97578cbd28d9c1dff4006265b7f25a
+R = 020b87c06cfe3d05da015fb4a53ad05aaa0737cdd25086ff05241b4021c7b443490d252bc01bdacf0db8af36b361a7f6f50475a
+S = 01623cdcdea9837b86406e2bd64af45ffe04820c2d460292806a2e25ae65827734acdd09b5b93d9ae261a6b07f355abd2daa36a
+Result = P (0 )
+
+Msg = bf3bb473df712924bbcbeeee6fe38d290405fe1a2beab90b4ce31babc5ac2a1d4fdb2c32cf9c0877042e140c0bdc84c12f9f98e7af17e74509a4ddd1d6769c27eadf491555ea6ae0c577d8405523605cebcdb3e3b83fcb07e38fae1c96ad583331f445d53dd6a2ca2a2f47b577881f017497d19ea9608e83048829e01c5107a7
+Qx = 1dac61d7c3501dda729b6164db89fda3182dfeee3f5ee3fdd97c1c1b8900e47d9e1385a59cc55c2070d55025e3e949d9e9752d8
+Qy = 18be39237a6296a7288d6674ca944a4c00565fb247c9d6781ce3f7405f3f8bb6ed5f54ebd497f12070c030509c55f1704e0355c
+R = 021ee09ff4a77ff639f86e772814606ec78251b21eb96b5db795345631e5812b6f9779ca70f12e34384a29dea2cc15162ebdc51
+S = 05e98b64f078e1601db4905c90b56eab332f726c2ccf56c12964fcd3c11b3964c997072155995c0798dad5e688d8c1bc351494f
+Result = F (4 - Q changed)
+
+[K-409,SHA-384]
+
+Msg = 2a79cd9b399e272b6f047b93f1d97c4d2895c6a26f43788e8696fe531d3b2a65661532357127396420e88e5b0099d0a08d466a02abced4b3f07831b242490e69bd1495f6d517ce6b335a5d82b1a64584cd468e4988a932458033b82001f05319cb71c4ea1e8c2973867e69383a659a8ce122c7e8016b2493da6352c99192730b
+Qx = 0c2b2a3de502427f2c48b9a078187cf511d117e6e1c0bb6b4a7d06dd9f28e2741257b5a6a8da6272d038961275f6c470b5bf33e
+Qy = 01b22d4544e479a197f6543a98fe1b75d3b70dfe0b51fab7040593b1f0ee6464dc2665a7eac6354344f7dbcec9122e0ef0b8a0c
+R = 078f850c7fdf351f9258e0b8d140333fc180460368659c35421d5646491a2c870c82b455f1595d8c2fdf2b4180d149e7956e5a3
+S = 0125e37e45a4b55bf40b5752b42f4f9d250873c06e569716e944431cb2245a84bd4f81570b556f796561357efd62a85d6088b63
+Result = P (0 )
+
+Msg = 18cb0d5da751779b563c4748f913c568054ec029129766f775f5d8f6c114e5d9a1a64ea65a414ee3df8ac08cde4f2320b91fe039232e2b2f2c42bc2cd7c0c6fb3354e4bf9fbea4ee756ccddad981c348c21d471ba79520ff18e99561524350e9e455df01e1d23e7c2217384184f8f0478097f8dc836c4b97c3144efd00601883
+Qx = 15b559a8de781d2037c28cfec048503ddd2db3c1b4fa3ba3a865d29af54e8d55b69d02105e6576f36e787530167dd6cf246df8a
+Qy = 05936b463cbf13c0174a04419d858eeb446c10e78e178118fe6ec98c3c2e9f29163974a9f04a9fc47b4007aeec778fcc80423d5
+R = 05af10cfd3ce0f76f3d745164ff974de778060bb1436c5f6842b64e76c07388f6db0f23eaf60cef30558c32e33b0143056a03be
+S = 07c73c351cd11504291d0802300442a9fa578355e5790b5907ff1dd1a38fabfe3bc0fc67698fb0bd0d4724cbc824d04e6625b95
+Result = F (3 - S changed)
+
+Msg = 54296c5607762ef00a84de19da0d7cdd5ebf63eaac8215be8e4af5a430ae8896d4f8cd559b1ec31a8959a4705d8766c40b984bb5423d09c993b1c96e1dd0b0579ccb691b6482b3ad7ea2c9448dd944b9fa0f0c4f6a1dc185e4859c6764f0f7d60479626fd57ea2aa6925b8470253b1fe27edc587a9bba99aef9525794841de09
+Qx = 03983e811335d6c5fc2a2bdc893e6d1e75a2adefa06be68ff6b8ce97555eb1d2cd2688c188ced5dfb291b0e29a0493aada22ac8
+Qy = 17bed3888fe98a103c4ecaf923aef32c01eec178dd309ef17a8351153b4f4557d96cf4ba0e10d142cee135cf02fcdf9fcc27119
+R = 0497e449c58fc5f70c6779bb84204fc9c0180f5b834503e7fd8b2eeb9acaa9944822aaba5d57b0c5ed5dcec7908b5c3eac124ec
+S = 029ee8c456cd1f40360c2b0a83e88c3cad34b0f4bd0615f45e38cf6a66301d9c2d3222b8947c19e088434c6d460c37a0d5555f5
+Result = F (2 - R changed)
+
+Msg = f787b582112b44655828e5bc247899aba204f80c0daa4ec75147b47412978228ec303a37ed16f2d1706b6493dd3d8aefdc6920844dbc59a1c9d2d1826c844c5f5ecc9ce8be6b913eada2ff8e198733b27a2bb3614e5563b98596c7eb4c9b0802400225d75de1dabc6d8e83480285a1c51b11631ce30ef38f9580f17a13ca375a
+Qx = 0223bde9502db7d2bbc5aeaf53e9f73e99ef26d2e5986a759f09f1cb9f7de0fa1c6d60c407e799e30fc6ee3198dbcf341f055c2
+Qy = 1f3f40a985fb508451741abbc224339692df6d3990b3a4cad641a3198a010bbb854a7026fc95559b6e60afeb29932b61dbf2912
+R = 06890bcf57c5673db99eebe3ddaf236bb6cbfc9dcab8ecb40cb305ab76fa3de7de75e4c92b5ebe66fcea0b6e8d210e90c2e8063
+S = 0322aadd7aacff765dc95cc46fde591926cf9289f9f5a328dc2e89f23a46bd4f542ffcd70f0a42711a719343a5f11b715615b84
+Result = F (1 - Message changed)
+
+Msg = bd51f104b3d348062b614c4f59b783d085d1f515a84c7ed35f61df443fa658269518f44ba5043f99e189512a19c72fab52db3e0f92d9192938adf42ecf114a7ee25d9d8986d72aad0c251d9c0cefe9a2f439737d89717eec92060afd4ae6890845a6fb7558c1b1e9c87a39f2382e364f755129b82f2f28dd8c3667039f9145cb
+Qx = 0dbe4289c0f7731ab886d7ec92e78470d464ecba1716d1bdf6a555e3a7c2055a5cc584be46bf6c5f5b2bda1e356471e1703e858
+Qy = 1d64e1131239a9b0b3f4b494a26e9d06bc69d923ac5f03acdec87f65182421146d37987479c1499a899cfede6f11b2951b610af
+R = 069b31f63f4ebf2a180fcfe0151cfd07e0aceb91d66e79504750a6fdf0378c60daaa13cffea4ffa887adefa4bb122dc3ea1b1ac
+S = 057404d8f443bae9617ab90234cc2b475c0be7a0805dd503d2ac0def26b6f25a24ffc87a0edcd9ad06c1250d51850755961d008
+Result = F (3 - S changed)
+
+Msg = e1471cdba8e551ebc4ec954365d73c5d94bd1549ee8b9ece034c551de2af8ba56cbcfa4eae07bd833216aa079242da41d471974a3422923fd970d4121cf76596ec88651f2f4eb79c7541eca0051fbd44967f7b8ae916c65333e219bb7171dec141440f294a24301f0649428e6604205a5320c8efc05aa15474bcdb1d3da842f0
+Qx = 078c118a622f883876dd430bcf9a74f8c34bf3f684c0fe472da216d77c4b646a5da1ed193baa09b82760cca5bdda22ae115a520
+Qy = 0dd9f76d399490872913f68eb6d1cbe0618ae6b31bb0c620d07cace2cb5d1343544f744b246f9d4fd335cf43c16c2aac024123c
+R = 07d6efe9836e1ee9e9f3f6b8e60c348826227e5ff3d6f3c737c2105a8efa487c59702335b43c6cd72c83878e1bf38bf10804c9e
+S = 02e6ccc6cec0455239ca2f86f9ad83f06d095154390a7ec1a0d8ef13d5b568d5468061f7f270eb004182dde0989d6751c0468e3
+Result = F (4 - Q changed)
+
+Msg = 697c9565caa1f34a177a73401ea36da08e362b1aaa146cb141a638dd4e178e85d614918bcf1d77d4ade925879b7dd0e3826dd9edfdc7dfd5253de67469c2afc2388f82f27ef3043ec7ed7c63c299c8821a7055649c787e6f5f7a0f5ed9f075d019ad7815f7cb3572b8b99ef6f739257151df2817fb07b8b9622af8b977d1dd72
+Qx = 1ffc263b85ff79fd9641e2b6431cf10b863c2dcabea2c9d9fcb45c6a72fa1ab5f7feab5e2e7e6b168546c0348ae7790de0eb78a
+Qy = 0e55e2a6244db40212d5ecd0ddc6ca78e1bf0cda5e55fe2c27369b6a8f7ebf7e28dc953abba1495773fd3be817cab106fa698a9
+R = 076bc502f4bb6a4d2813cf2f2528bd852cf091276db67176e525ed85538dbc77e303544fa1d842c00d06e548ec753fd78be66f2
+S = 050741d64039d91f7eb960709720cd28071740792d9d9d8096ed3613cb80079cd2e5341cf4996794ce1900b071017f05b335f2e
+Result = F (4 - Q changed)
+
+Msg = 0b2fcb09bf5fccfa59373b6c662ee650d49e4a5cb1e0a4ea9e10ee13cdb83c424e3b5da6ca58abf30d5f210715e94556e186c1a7625313a0bad38b7c2085518a1ff33a330a1979c5af6eb2128d03a6593caf3c21e755defb0fe3383134d570769eab6d710a5b359a9e9f793a51b4bd0e47de210b70ef11e7fc418c26ea8da4db
+Qx = 00c30a469b9ccd20590b1545b14f120f083ef49ca950ab8955784787b8761a3267e39a577aef9ff99204630bd0ea1f7654512ee
+Qy = 1c0f563f5469a9530efcbe809d6716c52abd4c273ad971918b953ea473b246416328f0c8ee19ce208dd4d5e5577da063c0c79fa
+R = 038bde5248a1b99fec905047276ce0ff03dad77832a8907622abb62cdc8d4e1fedcc7a357aba543ac9a2716db6b447de0633442
+S = 028efdc8d213bcb206937c224999e2331fd48b3a0ee7a4475648aaf62ab73a0bc699d11d688052339410465dc314afe238e4b42
+Result = F (3 - S changed)
+
+Msg = 2a81f4d434f1c01dc41f9118716ad077277c5973486075b8870627548999e05973f1b5e65bacddbdfb7d6dca6812fd817b8748b09d33c7a55cbeaf547ba4d3448d4c218590c0fed06c70c7b6e1edea9553f244b7e7b75b23a9eb734387c8b35eb96169f5bb75dd2a6c7e43ddc11827ee809a03a90b076c49d5b0ebabb70702f6
+Qx = 0a52b6c9458b48b54066440d2389610602f6a6b90135f9f8e370946655358681e0ea4c1af5e113f6712f2a2c3f5653fbd9e3cba
+Qy = 07d790c77c855c030237f2b4bf292e868ebd581f7d90437ea9f8c683b428d7c11ad62dcc942184778bc27a4692ee7098c24f934
+R = 0347b88a5a5aaac8ecc3cb3c287415f6609d321d07289a185c1c4b8e224af01aa64544754e1e7525ff786edea253bb056e28f92
+S = 03def1855454ac7f063ec908de443fce975d4459c01dd4363442b2565b9d376e9a5b3faa1970b34e1ef631d279cb33776c5faa2
+Result = F (1 - Message changed)
+
+Msg = c9df3ef3acbcc08f8f188b694e53171ba568fb9486fc8c04b4196843eb70b46099641ffd83a23302526945038eb58c70ae2883c1857a494d5ea2c508dc84b6186b36449f72e26672e76046b7fa2843ebdfcd59b69c80353c84214ce3e4deafd7734ebf0e67c1e8cf145dac716994a17e7d5dd4ab0d5a31863aa17d122e21d0bc
+Qx = 1e6c37baba66630847b9d81f3f8800048ca2c705df68b6ee0c38a6beef5775409e6f1a44e7d695cb1c7ac4800d6136b450f1868
+Qy = 0bfcde2176248717148c9ae7f430adc79cbcdb59a9e388563c2912f18a7edf0c0b2e316b9f7e62b03c7e126e8eb23d12295be86
+R = 051a057dfb27434abbff14d8d3cd7f34409cc2f3cc78d0c9aa3fa323ffde6ca5ad4a5aefac31027290bea941c1db2f3ead73dbd
+S = 06a1d93476249e23d8a9263397b41bce8b5ec015bc960bd2d7fb538236348093252411b8f3d9f549f59b84b7a2b952a3eb3ed33
+Result = P (0 )
+
+Msg = d5bcd759e66addadb12512b52e5bce09dcb0306f43a177e084c2a2db0a2e078408efc849f775515a98169ef1dce69b716bb59fac2f485cf01029a7f75c82c34e9de9dbf685afdbc8647f883ccbdabc1f0f0282b93b0fd00d5db12269c2c4676a2f18ea4c631a8cc83b785dc5a768eda8dd71599da59e0f367dd83d1dc0cb688f
+Qx = 0c1ecbac854510a8509e705639ee4f7f31d7ed10c98f143137dfd2884b8f5316be0808ec35f0ea3d2194a9bac0168e13d6f26f6
+Qy = 12292e8f884504221d305d482d9c33dce54701d4ddcbfacf0c2825d285cd4b287efde39cefd28ed0359cb0c974a449987cd5592
+R = 07f26f594aa855da604ed2f6d51015b587a964bf32e8f88fc3ccec8c2262e2a7aa569b33f957afc8049c7dc1baf8a6382c3e853
+S = 011c1bc339b3ad9496115da3c82bc4e7ad50f14b8c725251b36cce488560983d7f64cfa509711aa80f24bd4cae54ffe613ad272
+Result = F (2 - R changed)
+
+Msg = d4610f13387f80330be5153cdb6caf7449bb0a93c51e0e70ef7bd75931982cc61edd4f33ab5c77e539d4af3c847f0e2997ba6d53c64b7418e4ed1924c09342c91f3ae502aa6989dd4696b196bd6b81baf704a9e14052d350feb81f1a1c19a9faa89aa343a692b26411927676ec58461b35207eaf074740c3f75b387893fe12cc
+Qx = 18efa586111d97c455a553fdc5ef4aad8227e3955cd2f67fbe295a742c1bf5e3a84d5ff55964c1b56ee257e4870ea6dda806b00
+Qy = 1b98a3a8d6325c42cf643bbae7b857a013b6bbda26cdd16e8bd2a2a3321661dd30acffee20d7fc18294782cc659ebc51f7cb773
+R = 002ac884badc29ff875f89a8b6ad4b70cf61c284b110da796b588f6e7292c57a5c11e222c10956bc8d7ecd72f578cc571280b0e
+S = 078aa041c7be2623f880d382f4771ce511a7b55918924019a771f788221bbd7f89a7999475ff9e6683b9384bdf91bc974bb6703
+Result = F (4 - Q changed)
+
+Msg = 350731ff6d7b8b8ec9169ad13623e60aa08ebd5cee2ca1fb993f668ca2132d817e827c5cec014a9f695baf39a57c718e95d4a4a3f3dac6526cca20a4f17afc65043a3ff92736996ef1b1b02439af7b1a61207b8b5ff8df4d26e482f77280da6a2b8072094db7c71e55b160fa18002305465d7c094f8f6ef90e0c05fbbd0b7902
+Qx = 1f0d3e905ccbce6068315d2346c048d190dc30aea24130116d474a46d0834c5fb91c059e78fcaf53a582495be3856d3a139ab20
+Qy = 0c63a778733de1f7fec213dcbd55472eb205cf6a7b63e8639f1a4538d1a5b1b768997d68c3ab7f127f5c006db09c55feb82c386
+R = 07fd288b1282d66ea916b7d3b0c19e6d132a02c593b8158bf16e8da41acf14db18d365fec2b434de9693f8477831d3884159c92
+S = 0782992fcd4729417c40786302b8b5d5fba60beb2963f9e5c83f6de54a9ef8d823c58aa1efcaee88c9c563932235c1b83a5af53
+Result = F (1 - Message changed)
+
+Msg = 8208d60aadcdd4e3ddc7fbd04d9f81374f658c485847a122fc30cf9ffa9d5d281bb623d096793d8abb5989ce8983d6effd34048cb979c945fe3f727042a4d61c87c44ad71c2c06a9ebcf937462e58bf40be67701048d3698ea40488436eefbd5fe47964d5d7475bcc6829afd53cdcbbd7f8d4263ad08303109e6d730476ba51d
+Qx = 1ff5c13e54e416e3207c04770e504dd590abe5b51cdd2485d9744b36c63bc2e2ecdf77db1bc761ccfeb5748a1de69ff53bb2712
+Qy = 117db3b49b6a783fc13e8024973829a1a92618e620fa4f09d573572cf1cd96a82b4c874c736c338664e487b17d82de6c0a713b6
+R = 042edd4f4d385da4b7d7433b419834916f264a4b714ff6c3de6847813bb62fc5ebaa7c6f15f10c1bb30fb2556414268d70aa9fd
+S = 0686b4ba7942b08872f964e425affbc2ff386682b16a542d4a3a80e8d6672ff5296d441bf49e20132aee02870bc8a4bc42eee5a
+Result = F (2 - R changed)
+
+Msg = a0ebef3d35d901c81e1ffc52f5b45be9bcba0dd5e08307b7c5b4e9e9ca03f4c30451d3a12810f0efca48dde9a76269e658b9a623a590dd6c1190c70518790a9ed7ed5772850b49848e87966228517432ef7eace11b33536b17a49470c5c09d311b3545f2f739c077a7fdf3be270e4015f341b0f4dd3f92361dcf1532d7cb4f78
+Qx = 007062fd86930d24aee29feccbe0db8328285932463740d3f6379dfafc929663a8d0df85f0cde4337454c228980c8cee6ab37ec
+Qy = 0e34b65657692f38dd7fbcc78b66bd748376b29a5970b553031e4303ba6c7c39c3e13d7202e34a621a86293a2bdf7081878bd64
+R = 022d1f3b8c1a14af47d0c1382d8fd7f4d5d82b0ec47a0660be700fffeb6f822b91e56f6bd0123497aa81876ee8b775afb155dd0
+S = 029a2f611dacc030c1efbc627d8e9a5d3efac838d2d5a57025ff327e45e507f2581370af9b88429b35bd53f02b01f96528c4bfd
+Result = P (0 )
+
+[K-409,SHA-512]
+
+Msg = 31d67b0e21f37dc3af6f29cb0e2e91e07c2436d8f0283449b7c30d81271a799c13b352a68087adb396d3ad64ea990eb0349ce5339bc9f675f60a0065e4497d71fbdce4e8ab39552a520d5296a60fc469557c71e98b03ca77864da4118b5f1691149c7ad251aaa8ff1f1669f57972d27fec3e13ce53df812276ecf7eac0bf691e
+Qx = 17da5afbbef582bf455e5854e52850c9fa59e8a203fc8d4303f6c2552b68e0494a4ac6e81575e00e9450ac331425e7b24ee8cd6
+Qy = 125c33670f9789cbe503215bbd5f05a3750c6888a3974ab23acef890725cf90a86db4d3a91e9f047bad6d5238b023c7e02d9c09
+R = 04016061ce56d01f15e1243b49b58141f3e83b0b0fd4ece786d2fc966d6b46a5b2b929fd5b264e912cbd3b25b920e86c172d975
+S = 01c267ee7e1c39379972a4b98b3eab1ab9d6ceda38016595a08a9bc624e984becd0f5d07d51d955319a649d2896e6cb8016c332
+Result = P (0 )
+
+Msg = 123e5543dc835dbf6db0dea42eee46b86f9b27a611d170cbbb3d30305ec36bd02a2e378082e97e6e6d6a05b86a54102d6a6ac87a4d1700723780358a5e3a97b5cb9d9ef5bf24c8bcea963e83f416d33346c655af29fb6ab2bc105bbeeac9a9ce3c2e56f3e15112416ad5258571ba0ccf6e5374e0c8206580d24423e3098f48e2
+Qx = 193aaeb5a88f338cbcf7886fa6963301f6a6fb6b27ef9da31dd58763fcffad92f90f6df7bd4c97d41ac03ebaf4aec144520119a
+Qy = 062b25a583450ed906ce92473716bcdaaabf12bd9671c06eaf9db7645210688211aade7479656b82bf0b6c235d990161a228881
+R = 008c0f6af47e8abd6cc14b3c15edbbd78d1041ae17db909c5017ad9d5864a6fd2f630f3f6e36db6416fdfd4e1798ca071fb76dd
+S = 0549440edb7ca9bb888a260406b6409e10f4844beee48336d9dc4fe086e1da0dcde5af02a66ba932619733ded8b0bdc132a16d2
+Result = F (4 - Q changed)
+
+Msg = 67cf8b910ae3edf98bee404f2dadaa90ceac0583fd3addbba312a9efe6deb4ac2da95b18e9781467274ef78b8ff4320cf552f4c00d3bba87bb4725554584f115667437ff5984e4f3063990f9dcaeb1888a8dba5f2ca8420730c9cf44314d6c2145b988480c04e89c305aee3b54ee2f82acf85fce5df8af1c5dafeb9d32372bc1
+Qx = 151dda5210ff162550384440fee4c1e3be0eedf6b037ce731b1f0e98431b3c02d83ec930ff12e66f108061bf6505f2a3b70606a
+Qy = 0adf2411ca3b9df89e1c7a268b11073a7bf7df93bf89a11f521b67af146ca346279c6c053e0ee4bcbc959145d9174ebbd1e1d9a
+R = 061fb6152e1f9471938f126fd72b3ad3e8b0cc128e41f747c4f1ff4ff6c5243d597d16e3642a5453416b64d5ca092baa67e8bda
+S = 05e869282a16724efaebae6b0fee66191fa581d09247d435fd4c6ffc0ff8c820f6d243b2a89694b8d266ac4b8da0cb150a26018
+Result = F (4 - Q changed)
+
+Msg = cd106ffa63211039d3c52670272b24388839bae5f38a40e9f26733511d8106789546a95cbde3355fa9fa18ca1c900a897d407d146242042c6df1c10afa795b97a780ae8a0989ae5f652c27104fefea346ce3e777263161a80ed84486834679a6205908ab145901017ef3ae7fccfa2541dd0effdc27cd98b63e0593d89a5abdc9
+Qx = 0a4b0b97c6d4b0d484a41136bea96716ea94a23d7c1112af6963c76f93355b5ecafdf586b244e18d1853f154908b1ac162313be
+Qy = 01b076df86fe05b33308ec1a3840c0b3b6414a10d08c3c31eeb70d0b834670da6aeb86c10fb04691e16c6f51ce9178931b67808
+R = 004069a0979ba1b0d49e79ec5fe19649d0ea48197297e1bf73abf2dea21a98b58c611683b750161a39bf1922c8da5e5dd01cc72
+S = 07da2ec6e82ee62afd87bff99b644da3aa758c11534227257af62c46118c8cf6ca4faac28b9e4790555879cab1eb12bd7a3a73f
+Result = F (3 - S changed)
+
+Msg = 809ffab50bd4215ff479a8c8bc9f3b7832441936a323d9c029f761e511777b5fc8156a765b1d15989860eb848207701ed774ae343c4028287ad4e7d6906904d32baae28352e9dcbdc6346cd2c80b6ac5b86104fd41fbf56d4e0cd6ab9eae22f673b6cd3044c8c256d0dcae0e9c4f8ee980ade06f54f2076483d73927d15ca57c
+Qx = 0be87838485ad753e1cec23e3b7ba12bcb97f8bb5d0ac862f0551f2796309f6197f567d036a604092bf648c614c4634876f49ca
+Qy = 0153e56ce9d14a2857b3c0b19a7616a521d6fbdaf63494e77791421ada4944e141b1609841773b2b1d6bf2242c3b8e122eada5a
+R = 0393b0bb4c228b8742bb175b3a32f75a2b3d2fe9cb20da0b2e5e4144b849c683f18db427d95e386512bf31de49befbbab89680c
+S = 0233dd4391e81a6877e25f0bf69435e43d0e3db6c06bc5d1dfd5132a7688abaf57396a54e44aa262627523f5385dd03eae6f8a9
+Result = F (4 - Q changed)
+
+Msg = 0e340e00657e79990adcac50624a241e96158c9580b5b363c589532e2ebab435d983b4ec9e9106d056eedb2027499854be6460e56f177787809a5cb8df9da51ec9b173a3498659de4bc94bf5a88b093a639d014d116efbbaa89b9316d597a8ebbc6a38ba7d88fea12fa6c2fa7d773f35827e0cef91c58202a4a516787d6027b8
+Qx = 12a3e99a8f3ee2a058898863458aff7d4f57103cfe9256c126878edde5536f8e52aa9d0e044c1b2ce394ecf53b0fcf862c28420
+Qy = 190a9d564eacc913c3aff4a1651930bfdd62752eba9259a0c3cfe8654fad4c7e78dc25429821818bed9a704a1e46059520467d3
+R = 063828dcff96c1d5dbf35019b74efa528292caf56800dac3502d173085bd60c28f35198e2a4199c4a3c3e392c374955e9a6fd58
+S = 00cdfad4e8c6343847892eae6e8d88fb836e90d0e73b037025b14bb084cc1d2044c79ed0abef5203c5e5086913d1c58c42d2716
+Result = P (0 )
+
+Msg = f593867e251a32b4fff21a5ec2057e95c1c137a062d1eab550b9cd81e2e1628f39eee18e12269ed154c536ed8417ff759a912f214aec3a8a41529622ba325145aa076e57f3348dd30e597839b32071081098e79434582ed5731490278b32cede1d8cf1ad62fd87523d8e8d62fea8870ab884e828e0d0c598acf5a90a87f59093
+Qx = 1f4e94dd5ca2ce9bbb97977e01485fa4ece539fda3bed8029a716c5f96203623201ea3f76c8ead9c726f2672db83b35b2db7008
+Qy = 071c8ca3fe236de06959100286067ce9361e4baf38142081472c828818cead94cde80f13d2759467a484bd43d7b745d23d9f180
+R = 0539da6b14383ef1deea14462ef2f772fed4b80aa03721a2bca178332c41eabe1346c1791dd337da16e6c7083de1f38497fd6fb
+S = 011a813011acc459fef99133074dbc5d5e93c995288dc689fa8e46b569896ca0e36cc8767de1ff72ef5e06844c67ea732c15c5f
+Result = F (2 - R changed)
+
+Msg = 4d2bf759c15b32719fbc2c29c40ac5dc54b74efcc07d046594b94dfcba346fd8c63cd1bfe924ef52574fc2d0cc6a71154930944a350ed36010e2ecb4b71cd0c115cc25b402e9e8c6769eb4839e509e3e77c5e13f4cdca1cda60837e328df03c11a4ea23d6e6f7a19cf17e387c14ea9b7aa93b96ec0166d0746694078a1bbd254
+Qx = 1e1cc53b58098758383de00013f76d220767b4d0e4de71843a7bb6e65aea23d2b1d86f762963a6a678c5245a69d1aef9779c410
+Qy = 119a72adf120e11ff700714b6c7e20c8632cac20c2d13bacbb0a793c3df02ef1b40c73b65a24f6973f763fdfe0a91a06b8d851d
+R = 04b4f952a47f59a4985e5702b8ad8fb05f7fe58567417be360b8a28015400ca958853dbd3d36353658a94307c104d0656694b82
+S = 01359ec54e34de2f679f067d9ac37f5947c508c363eb8fd5089fd9b16b098fe9edbd648c26fc58a913b2aa67c23e1adc401c896
+Result = F (3 - S changed)
+
+Msg = dbb4fb874b14b8822189545594bdd265cde8a20e5d1bc73d636a50b6398b76708f45311fc38f82603e251e48087028650980bbdbc99200f0a0b5fc1d0a6bca5766f3f7c71df33461ae1284f9827ea8bf92fcb47b9533c334318392dc2ad68976fbc566492fe6c2d98f55dbd76c5e63a47a2cb5d7e1bfe2a24f596996df186032
+Qx = 16f17c45d6c3a2325c880401063c27346644a5e957cb315bbb286909a86cf2a322a62d07cc2a8764068c75d76fec4f94d6ea3de
+Qy = 05a8930a8201837304ba0100a9b21dd4d1c9a519b8cff9782feee328d7acf20dd967c84153f8abc480a0a2cb033b38ccbf7dc37
+R = 05114d2b7f14779355263880e05920960f4df4435312000f340b3cad8c08c52272e384d0adcd97f133bd86bcff79d88c78fca66
+S = 002ded29852bc2bc10686cc45261506420e5ca962ecf2cb55134e8a21bec2b2ddbbeffe725f43c53c9754ff2e632efbf7ba4145
+Result = F (2 - R changed)
+
+Msg = bdb67e832e002be0bf6ad4b4d482c07a1b2d9b54d1aaca0cc0d0c6e372b1eb67abb29d4393e6a6ebca9e435dd39fb73ab7898af34276c001d3d834d507f8e1efe99f60c9e61f82178cd99366c3bb65c11ce089ba1d2a96bd81f29c3e95247e7becb236dd50f823abdf15e782c037ea77973066dcbf7080a131f80bcff6e18fbe
+Qx = 0bafe72a8a89f32aefaf4cda5349946619cd80e7b267b061a18dfd9889fa3b6dc58b1f6ad7c2e327fc85edae5e2461caff67f6a
+Qy = 16dd89a73fba01c9525c82c0adfec7b78d8a472458ffe07934e1a2267f04b7fff86fc825476f644a3644614cf8a4c156d8b6da7
+R = 048ee0fe12e99267fe6acf7151f10a16bd4598a76391f4ab151ca877f5d05a31f1ea050551d210dde032cbfd43f096132a575e2
+S = 011a963100bb72b601a91b2e4d669df39db340dc9a2f0d7076ae6fc12c999fe923a201e2b4b30f5eb4049d83c7036537ca0ce49
+Result = F (2 - R changed)
+
+Msg = 840a1d792e021479e572b7f63ce342e51f256fc92d76d22544bba811402071dad577dfe0c44a82cbe7a504f79d0e86beb640acc2fd19c8508546a936b5d1e028dbca0d5de92a8eb73b04e41d55da2991fdc8f1bbd7fab969ba63b3d926cbf8d1bce6c72d0394b4e3a59c1177fa3db79cec77f37c99a9a3b54a5fb4d996d51f0b
+Qx = 06ff94a75be9726e61acda152a32fb2e3cd8d3de914b70dcd187963fc7186f8393e8f2eb26f2b8fcff250dcf3bd212b6aa8fd16
+Qy = 089d9ddf33c17273556419763e9fb5f4fff47fef7902284c56a3b86c0e9b68c1ec38329b0757bf0d5c4bd99754ba956ad36e75b
+R = 0162df9f543e32e8729019dcf1fd5e79654429aa076229892bf73c3d3671fe2afb477bca34ab9e8e0cc1aa621dac83a9838eee8
+S = 01268a1336f8546043aeb46e33089ec5e0cb165a525b19c428971439a1f9ad3906fba8e9258281c05d399f12e114eba234b8160
+Result = F (1 - Message changed)
+
+Msg = 423bdff735d6f79f96ebbdc2f5e9325e0cfd3d8f26fa60ba285e1458dd5a720ae4607f2e3098cbf86d564e23747b04bc7bd1c74116bc737705dbefd394a600072788b516757a5b7a519a7af6c8178986b26d0b795832bd0c75199f820a3a97ad64cc5cdde81d2ace7d7b5255c0ae86dcfb48125b480c3851d288a2d70c89f63b
+Qx = 038c0166237dc03d28dd8990dae8cf2b186a5262a20438726fd4925f380f13b3a6cbd772bbb056df2de943cdde18493bf057ab6
+Qy = 11e3c416e8b7f941b99599bc05087790cd6eed6d378994db41ebf710a85507c5b660cc4e6cff5104cfe83660b8072a2944d5d2f
+R = 07bfaa7dea618256ceb422dbdf6ec91271815a71396ed3511cd41f295abb1e96df350e1ad6fa6a50686c8fe73c1c34de5d13c0a
+S = 0130aca6b726d2ba94edbf260e8f5b0e06834f785308ac12f5b84837195b675ada300e4b7c0d9589f094a7ba6ae22693edb9435
+Result = P (0 )
+
+Msg = a24ce25d432d3d6653f70dd7495c9f861a5e15785c11e49cd050dd9e2ca75a63507c98b89f72db5f587c6e1184cd933c62519c42e36fd286c6ee9c598603aa4a5bd6b603184e1cbd5cddfe8c7bbae61230f4758a145e3b149627b9f9926af1b39aa6d62f0e94d03deeb6597270f9a476b94ba4bb73eec8a311d5ae56f455fa1d
+Qx = 069587845d7c3906c82141df1bf67d68fba4e949ca7ba4080e76f2c8077a2f9799c5312bf7be670578f0e18daebc43679fb519c
+Qy = 0749e8a584c16560ee16b26ca1279e44ba5f8a5c05cee30decb93f7b5239476536f7a403f03158ad8bb36ff5b449025cc8e1455
+R = 0162346db59d206fe625c884ab42b58cfe0c1115039a902427365b5f4380c84b0bc7181b371c6b8f4960ac8fc77ea033c4dfac9
+S = 03903be60924335f45bfa5c8976edda29fd99e0497c8a9c2265d7d94316c55268adc56a27a1a5d4172b69bdd859106a572fc75f
+Result = F (1 - Message changed)
+
+Msg = 5fedf8038b64c5b3e432f307705e5c5efdf89b7fd6b6e9babdcd7759ca4590265c9d841c681232f93b9e794ea45cc21789f43ae6bff7d153d5decd59fbd49bda6c58d66c483b6afb6d7cbfa8e0d3a144f65a9154d60af07d895351de7799e839e58cf0b0bc6084317727232e54d265d8eff97897018cf906acd36a3a4156740b
+Qx = 0b3eab1951e6cea0fda96f4ae1f1d3e4ac6b413550dc5afb53a623fabe049687930fcfac03050f57c90c58c5914991efd286f12
+Qy = 0541cf5fd5fad1e08beafb7f95ecba043fcfe3a913af97b3f3d6de6de88353a450e57f75ec935349a25f6c1d153d0f6649f0c95
+R = 0147a8ad42fb5955e31ce409485d26a9162fcf48800336fda27a570418616a84d9f7a725975f755186c2dc02f13a52c3f315763
+S = 07cd563e31b8b4e7e45df34e8033ecd3cd534416f7d17c29dfd046a6d11a3f7fae88b895f173b537307944dd9fe9ed3e43bf889
+Result = F (3 - S changed)
+
+Msg = 46cf346187232bb8c302ce62117da0d5da12407b3ed58f0f84951956559bc903c6c5a17a9eef5df391eaf1ead44ed02f9e4071a7f8ed6893002fd35ce819f87da4c8ec660c58af1c3ed3547232b4865fa8f3f56c5088ccce8989b654e779a19be473f7235f8e168bb186bb0c64aa4c9bbf5c055317b76bf60342a2394eda816f
+Qx = 02067200425a87319be7d56502e33010fc8c62bee611ceaf696ac4c23db2d4eb6db9ea6bd0f05a0d9fb90cde161bfda8cac628a
+Qy = 13f23f863285f568816a6f9a83f30afaa3a06b246dc05464bbf47c6516d885b28bdf06f42b4656154f5ae02cfd1e401d67f35d2
+R = 00d766274abe2a240b46ee2cfa7bb79e4d601dfa5821726f3df38c5c94b369fc259510633b873cb6adb9dfebd0f04a109491a45
+S = 07abb1207fe5a7e72dcfe81095bfd1748d89ed165781e33b88d0db28001d84d75fd049e541aec90843a84bdfd239a708d6319a0
+Result = F (1 - Message changed)
+
+[K-571,SHA-1]
+
+Msg = f2a0dd77292c5f2b8b33a6518c76840e85c6ec548e9a9068b3428a7b373c340dc68b1ffd699092765082bc680d5ad5246a7f9af7f5e063416cb319d678b57ea9910422360c05b7bdc29105145d9007ce89166df623f317ff1522443ec3dd2395c3d83b39a2814358896060e7f0617716196700c937145c69fb2eb730486eb3d5
+Qx = 3a1cf63f6f23425677e8a98d39b1c17979edea6960ec6d45aa39c679f1a64307af20982aace72b655f511c04ad98da5cf0d6cb3f3d931751fac13932e9b96e7dd06feca488478b5
+Qy = 5096ccf1dbeffacdf0a6b18622e708549c0662011c4ff529940a9203373f28f3cdca5c0c7f4aad30cacd92dd525c881ca28b500c19c3bbc8692c109d8f41e19159096b2afaca3d9
+R = 103189f9abda55b247700a1bea6fc8c8cbf17035e66749519723cde44e36eadef20813b530bae3375c4940f22ba67b2f542457d6b1984b2670d6d9d3a613e341471ba705f46e41e
+S = 18c53211cf01354150b06484031ab7c42e2b6f5356a41ab12521344c462f6a777d7b2f8241c9c82fbd44959a44cde0b0535d0112d57d46b592f4a2a72932fff1a6ef5989eb1c67a
+Result = F (2 - R changed)
+
+Msg = d0751d7c2305c40ab4b40ed19538530f53195f765fefbcf0d7ec304cad8c0fa5ed544243fad83eb47f3ffe8e9c14df5c75a226967db89ffbb0ac60e1d324dda875780463a94ac520d7656ce5e74b38820f33987dd216ea40c6449875b5c48785951c208ee3a0e0568eb04d600f1a90556a691cc5b6ac32edfb4c9124f0f76c8d
+Qx = 2901572ee1a014acfb3e69f08ada986bb559ccd4d429951016f0e461cd75cdd7283d33b56e995ec7621cbff48fa3ee523c8eafe4aec953e4196665598a86b00efb5bd2801b94aef
+Qy = 62a2d97176667703e8cb1081d6c28c977df1526fee1b36c4567d3262c081709ab464de3171c5c413a14e23e68136603dc5af2816f80918da13dad0b1e1d3fcfa6daa1cd30c0d48e
+R = 073882e1fcbcd7ff44a6aed53d0846d02d2c97b43acb20173f05f4a795187cf496342cbe0b7d86267d0204e29fc6d43c52b251827232b07ac882ccd95f23a1a1e416e7fd931b1a5
+S = 0820ee8282c5c58a930efe4a9e2674e2f861390d999de03c3347cf4f63949c582dc93359a65d915d3387cae1f01eb7a503f3e1a5c0c52870f0a27c7132fa89bbaf949d4abb75b45
+Result = F (4 - Q changed)
+
+Msg = f67bdde8fbf38c98dae0c600f6d22c8d99cfdc3b8ae7b1db666d6a30efeb50a1b5cfee4e251f8e6d74150787399c89d99a588a9a48b4323ef2c21e098d75c894fd828350ad3224ed472a6eb2bc5d5dfd944ec5f9169d40ab037597e1fa6ace67198227441d4b010ccfb7879c3db75b02ee36f7c58079fce8b067137618274856
+Qx = 34578aa77aec9a9b3f789b2cf915ce71698f038ad1d202caf10ee0af2aed19d02aaafb9fcb957fa523f0cacaeeb08a193e0d43a22feb42ac9e6eaf896f7f1db8c7576d6031d0369
+Qy = 262c540ac933e86ea56b03029d54eeff784347fe99f3e9e988d46ae2c50ff1f3e0d683ada1b653135d064729480b644612aba3f0f3307cd5cc9259503fd54e7dc812c001375c5ec
+R = 1a839bffe2c811cc09f5f36e257e1a793d63c2913cc5eab1ae273c3b36a595225ed98896808d75b8faf815cec4da0a462b59aa68e91f3387de8c7f4f9607a116a058919dfa6b614
+S = 1bdab449dad356b2570f42e354bd04bc3bb1605964a04562f3f218be68521bf2bc5b17aeb4a3d3d3940b6116fdeb456e0eca224aa62ac3ad7d2035da3e2c0719a47cc7cf6b4800f
+Result = F (4 - Q changed)
+
+Msg = c11fe7016c2eccd75db4586f95f4395909f515fd08eb48974114a4186fb847552a1eb04e8170a5d2ad2ef6ffad911bf106a903459f0effab74f44abf55307b0048c6c67cf19fd4e5d9ebebe568afd8a55a4c36e07b3f1f8db31b32c799fbebae19ff1a893bbc56893d7a482ae761e7bea59067765fd71378678398d77f5b399f
+Qx = 6148c4efa7c244f3493d2c4aef920c025e1288f1e25b1ac20a6407fdc5d5d3c44894a18db1e68271e382e9cc25ad83724ef68c86df09324650ca4cfd4b7c5f467903eb7a6f74ec5
+Qy = 6fba84f0bf03bdb239a1637ce3d0cb92b29c32c9c10b7e3fff2b369876499f77ba8723bab4abe1979575e650c51d5098ca28310c5af4dc8eba8c80026a76da006113e1943654cdc
+R = 10c6072c0de068bd3ffe6541810f79643a8cab298eddaf8b7df0bc360f8c8321e1515832a286d32bdc22195a339ca37c5fb4858aabac7ee3df7c5fdc40f0b08447cf84654f7a65c
+S = 1c8001b73adb68525eae1b3ac4d3a87d52bdf983f247645ba7b6699433e3933d17013fef2ba7ee1ae4921dfadfe66141aa783937f1106c66637d4fa67ba0499e083af69259c2319
+Result = P (0 )
+
+Msg = a266f8539bd048f3c282686c7d2c9b3f1977f9a9772a6274f84d8bc655c0b43eb9dc1b56b332daf0ae3dabadc12960f01948609deb1df2a57ed796593b4a3c54af33d122c0aa9d4c533129fdf095e8decdd7f7371a6e2707eac2ee3c273f18404116c6eab8e7d481c9fd79f95828ab217c336a5981b00499a70d34dec6d67d07
+Qx = 01518627fc3abd9ce4907796d14733157af11c2dda4df9409f2474be2cbfb755be92531a6e6859a94f41162a323c963206902c1aa304ca6fba4a5f54baee6746fff71ba6174e5a4
+Qy = 72608619ef30a18d4c749e501400af2f3d64202a0f290cc28850c9e369e817c036781851c04af2e67b063f73c9301b4bd9fcb0ae57097eb1d64f11f8a2204bdada1c0e9079fa07b
+R = 08f31f246b544a9c4c675eb053f2416ed901220338e31b34ca6fc2fe3bf9bde77e349ca80add6eb9d1af04d1a4f0b93b02d789bc5219272e779bd4c12796e9fa4c58e7965e524bb
+S = 03dc7713ca20adfefadf1e84abcbe73b27fb28cb3906a49f582d84c18c3c6d20cece0c5850f5efafc3856d211cdffdfd2272cf3f13f8b3bb61b18b3b69566136f987e644227af7e
+Result = F (4 - Q changed)
+
+Msg = 62087f938492d1394d7fb56d9fde8d702df6c9ad9909bd655280064bb712fc6198f58838a321b535f6efb815b4e3466aae86d8fb416fc719810518a001f69e91be58f1338ffaacacf2e31b3f442f150797f4d0ac28a802215447cfeb742c1cb5af003b9818723d68bea11fb30bbc349666a4c679a35f0ce027f2696e8774b7e5
+Qx = 1f18a9d2f1d81b39391b14253d7926ff5371d772fc902c410dace371a2379c12090edb0ed97bb01dcbf4ccdde947bbc544bfb5b45112c87677236519427f9a41df1dff6a7159882
+Qy = 08582aa45d3995c3d7cbafc4e18198facf9c19adff525f3e8ed24932b9372bc074f46a04517d76e1899f20c2df3d17194ac72e6aa802ff644b5a5c0a705e87c7ffc85bd902b5b47
+R = 1b6da5bae0eec003d2c8939ab1a847a12df84e75d7996dfd22df84a6c0bf7dd51cbdb4f8277b4ec81c17f48c5dcded507935feacc015d774ef1ef5fbe0ec06fbbcafbf6d139c642
+S = 1f527aab5e68941a0aed644d970b9b55241e234007dddf68bd544504cf6932fa0fa4731962d4c74011df8ff44f5ef64c87110bd951928be23a2a6097a139eb209c711008c6897ae
+Result = F (2 - R changed)
+
+Msg = e86099e1425d07c54579eb60ad8822e5481c31715125cb107b99a3643d6f0eedb600312fb1c907cc3b2993702ed1a89b7ce1158075120a6e75535d564ebcf737b3e1e355e07fd852070a3af212d6b7fde1a7db4b47f48b269914fb013494d4a124981a309356ecbe80767369df5e0b724607e1f310597fdb79f736fdf012cfa9
+Qx = 25c6899824915491c77cc849a0da706f8104448301608ca143341cad0af02b3884d84a72f542296e56cea4e6606b312186d3ba5226e898d8a7b4336eee4e55987551794236eba9b
+Qy = 14034ee694801289e947aa3fd0dea4170ceedb907725c548575edaa7524dbab9286c23ef9c5a36d30f8642758aebf23a047bce720206921cb2d964c39342a477349e1cbb06cac65
+R = 1b14c9929bd045c63252a9763710f9c4da5609b15f5683f366e4bd7ab8cab2dd109ef005da9096062550b56017a34af55f1dc1d81c3b0aad20dc57e4ff208eee7216715947f66bc
+S = 12ceff505fc5d565e3e571ab9f701bec1d8742be6092aa40c3c1c70bbabb3ad8d576d0a8686c7206526ce113d48664645bfbbb8a8c577d97c2fa6e5ffc646d30dfb1d67c135b12d
+Result = F (3 - S changed)
+
+Msg = 5d62937e5b38335280d9217cde834db2316765b2d2b251f291530dc69580196fbc066f7c0f201b1269adb835aa1ecdbb62de45dcc221da2d447d85d62dfd57abe6af559397f59c7b72d4ca6323834da6c04fd0e12fe61de0a348ff78079c52f8c5a6993fae2b892327cec9bb3c9d68e654110156a6857a898dbda6d1c02229cd
+Qx = 6761b27cff4fb87d1f4c8418ccc29d617e9586fc33f19c8c48b4f963943aed59e09e531e55f595e2fbf93fe805c1f6a893c2bbab6947033450e82bbe42c6a092b21c31652fe3576
+Qy = 07e922e2eab78dc1966317ea31f37dd45e8f76939510c3516438ff340cf5e7cb413ff7292d9679e65da7e0a01de83b8115761879a015f17ae986f88ade419f6fbfa536ffcd9d769
+R = 0e3286325c26d6998f817eabdb74283e21319a35632473aa0353bdb699b25900a3b5567dfd04767f5d1ba482c4156ae780d494a12e9540863c136e1deda7430e076490e78a9c23d
+S = 08a9dec4520bd14d68865192ce453752333f57cca8b80c4c74501e55b6f478c243570487bdd49ca481ee78a9624df1c7b9e81da793dc7704046cd19e80e3e03db8c06b078509295
+Result = F (1 - Message changed)
+
+Msg = a4e2d157489faf5752ba7116325fecc8cb64621a48347849fc7209d5679264088945fb9da4814d56e2a7c4847a39049405299c7ab004a8d21cba8120c7af59e5be33f11f67fdb7e855249c365b51e1039e8e78abdbee0102c72c9f3feff8a18e5afcf9b8d4b9f0409a772529bf295d4fbbbb50759d6316f7a55aaaaaf2d6feed
+Qx = 3551d74bfb2bb5966d42900b1411a32a4411b724f24ceaabb386968b521bbea6daba4023fbad0f8d9f7c637b2526f04d38ef18d49d789df5c376a0a74ec4cb9d100e5b6832ce8e3
+Qy = 7fffd1d3f8487aecf8f62dfc908350937429a54807bf93a66dab185d1d68e3a9b5f94ae5c40511ad7381b9088640ac8161ec4cde1838e55f68c6552b38ed1d75ec105907c331606
+R = 198e8e6ea7882e61b583e7f38ce1c54513c16748d039512f0af63a7fc8798adb80a219eb6d380162b8c4420fc2ce784dab983826dbbada52c902f16731a4904ed60ed07ea909af8
+S = 1b28d532e77a04b0a12e0ead8990fb1f5360a1db6e803cb0710af023865d8a07561490b92990432c10ae7e079e6e66cf6de23cc9de56c8ffeedea3958c07f2b4b05e58cc5229a1f
+Result = F (3 - S changed)
+
+Msg = b7586c760226de0354be355b04d30f2048473e7d12d87f7d1a643311f3b0b7a3e1f91f67364177368ee1f76301f6d9b137600f7d379765858e089f84fed141ac8500fcd29ee8d177c988f7dcf6a800d302b1b49b57bfdeef78b10d845b1dc255a6869080e33a6ba6daa328a453eb0cbb6b435d06189236c22cefe026396fde41
+Qx = 073a704351555fe2c3f5013031ea4ba55af8f2db056afdee0cd3a71577dabdcb8a2c8b9fe20c80da284c8759c8ffbbed9fd3ac80eaf626d9a18dee89a9aa8f863c3f37d06b6b2af
+Qy = 45a927f886a690fe521ad347f7929a43397c1d52c0a01926dbcbf2c3d319d8073b986d422c3db232dcc1201bb78bf5fb031a36b1a6d4d208b75136086a86bd1c6af612855945983
+R = 11b2590a571cb4d1b2cf7a1f46c3a0cc00ed2db1989b5c9b886fd4d1a7a59bace932f0d80411bf992a6f76f3f05a30440121e01d1f0c21218d10e1e881740397899b8539ec5420d
+S = 07fe4df66a9306b6f77702121faeb2420872673c216195e585893173055728f27b0ba992b9c9ac2729b17091435404a54a3ab9e42d9f9b32269a8b31931acb48868808fdb4fd167
+Result = P (0 )
+
+Msg = dd6fcf16a11ab7040fc3b1c012b7a2e98e3770e03a1382f75f8e554e09a86bc768c81fdafc141afaddb01059d266ccccb8e8fe6d89ec73a6fbca47dadf42c6a27944e046dea054596479df25857c9b5562bed2e20183cec0a4e7a6f46c48506f6df14adb5083e1d4c018a9ba5e77b48f5cde1221ce11b02894f8474c44d3d2d0
+Qx = 34453b18b0132eb5ca9fa76534721de2698816ae3f36281eebb31b4c2bae9a932d5de5018cb9f7edc870a3471e56be561f74f1b5b76d3e8910c43e2ec6b172c2aa774a2021d0f95
+Qy = 0361d9ac0e926878393b3e29d3850acd9685192ce0e02a03bd966acc966921c2e7dbf310c07de73f556bf2e9e2dd80ce625877465ea51b2aeecf9d669dd3db6707e8ab9c54376e5
+R = 07f55816110ab11d9b993a65ad9b208c255833b5c05ccf5704ea5b2294737556bbb26461df8280eab76db465a5cc357c9c7389ad622766e2eeeb2fc599e66dbf575bcda95ce5ca3
+S = 0130be52c1f0b3059fd4e5f1d1d2f0b958bc90a76e141234fcf1e27a1ccebaf4230ec2aec5116304ef75967eac4f69c144509157e5decbccb83d43c045be65e939bd4d0c1679321
+Result = F (1 - Message changed)
+
+Msg = 006ebd67a3322a081afd2f6529e8af8f7ac7364a27194db15e50d23e3d1a6ecbee292083c612a4b74924adae3e5e56e43960f1eba4f9ed13ac1d8b96643e2c41a3c67b7d798471cc653ec939eb203647ff04151eeae8136a3ca6183e13f0544f675e9dd1c42b88969a3fe4f8651f432e316294bc6ae1319b46e941bb759cfb7e
+Qx = 4500008b2a5301751dce307b0fe9d632add85fec1af94a2cd6ec98d813dc047a36664e9514c7ccfd87e5c11adfd6b5e0473eb0e3cc2712d956a221f8d9788b6de69d37ac79a9e28
+Qy = 06a77ef79c513a54f0a8d77ac74c4dd923a4e76326b7aae616d67cfb2bd05d2ac1928c1680585d3b6ffc0122c744a4170b9d0de88596951333c99b77ea74766a7707e36ba1e9552
+R = 17cd33868cc4aa9766e106c2729140de85efab68fb6fffbe3534d35ef700b7c4b59ae0369839cd04f6c13360c4db0be9829801d03dc7e7bb4dd7b21afcef9a3f551d60cfa87034d
+S = 06ed974cf512d2afec226fa2ee22353ff7c381b07dafcb3fbbde037c69d421a05d2b5b21d5fd67a153c7c1738d60b7924fb06f8b4173927b6702251dbb6d2f1f88d3aa211147361
+Result = F (2 - R changed)
+
+Msg = a1449ed8653be9aa885c3f2ff71df312848d5e25aac48a4d70447639252b6c9528539e5e175bd45bd4d21ce8750d506c1d2fc226f41a191dfc24589ed2c278c298bf5194653feeb9bd210d3c8c5fa2d8597a3384cd522b1e227e22d9cd5bfd6157f1fd40ed809bba14dcd467e063c8090ae2c70677025ccf95ed0753c7b125f0
+Qx = 4142f2b8058cd0cb849f4a6c367d149b4022fb10898510b0634050f821871310051deeab671ad3ce6338009edb2b5ff53cbc6e3e19f585cf7f3a91983457e9115dc65cb4543cc48
+Qy = 5e07fef0f629b9725840992f46609adc6c7d78aea53687a412aafbb0f0102e95eb10cbdbcbc98d12dd86700dd06619e8bc1d5923bb782c4eba0663d2a216709c9325490157737c2
+R = 0fe5b3d12497fa5a25901711c39048128e4741709d6b52f06bad7e666c6e56f5e40138d202a935b84b2db51a1bc67991945de3a6bd64937909316100bddb063e3d76c541d625aeb
+S = 13e950b3c8f4b750b749d8282b95b3fcc3f001e232478b43793e03e1a88b56e070078211d4276fc0462f83f599592491a393873832331d7e63b6168f0590a7f869cde2b6671addc
+Result = P (0 )
+
+Msg = fbcf9c1df104e747f1017a45694b4746f459285ad031eafa4be7f638aeb89f0aa2f04e96ce01709d33f162150312f6e90b56d75d5032feeb7601c4b7678f01cfe36072c0029b0ed9814508c4d2525513665594659f52f8049eb81f55e70a83caf8195ca00088009d04c6f09515f73c37ce219d5b9212444acb163bd02ccfa3e6
+Qx = 05b47e43cbf715fc10c25b8e6613e4759541b9db58c9be4d8888bea1f0e45793e9eb6f2993a6e780407a0f2ab9e74e193dfb76e7884c0f596b30bd42aa8a62911d48c205ae3ea91
+Qy = 4b4db74faf05de258f7345e723f414dad574e3d0bf189fe374f220a4ec6f098f1497673ff5bc490ca083531a170a84859b2bdfdcd12ff8eb62737665b71d20831133008fde0f7da
+R = 14b749efb0e147567c62aaa005ed6c0fb2b4167309f903912bd63ce9c7f83236b5d5b2f2f810f7e048b75cfd806920837f5706dd8c0c69435aff17f81fd48f58525511ec35d2c99
+S = 0eb373b32bded9adc24b2fdac6d9752d5e71fc025806011e4219e4cb9a3f0fdd1e3cc146a15423310ed39ed4eea6c6d7524cc0bd96f933bbb96a13dbc61dba1c20f2b27097c215c
+Result = F (1 - Message changed)
+
+Msg = f22b7be9f616a3cf7c7b403c4f7cbc2642a3d3310834d9cc43263c74422a492f0e05d1a6635b9726a4ec2ee7e20770fc3319d6a2360eefa8d71f0a99c97708d5a85c39d3142cca7eca0d186a010d8f53b5313b82e95d8742acfe7577cae27c85a82cbbfbb716c672a8e1c1a4ab7ed98b96b8445043a585e09a56eb9e27647643
+Qx = 764f0a90a5d4ecbac706ad32bb0e9297a65e1c760228f55df4df85b1f0804f9d7eddc6e25ae878b395f0b10cb497dd44607179d626b843f0da81e695f0117b668d6c257c7b53a8f
+Qy = 772bd088eef788c4ff350753640b02d7aaebe3a82776f9297a97e4ee25dd3e28eaa3918ae9d804ef32594af8198082bfd4acece4cbdb06ed14bc6bc45816f950312bf8ef4d0db43
+R = 1c79e43631ffb37adc3362e684f2064550858eb28be0083a35691f3d168ff908d060d2d18247d0ee1883497f7b1085cd33e8155b5b66671adaabcaee439eb377bc1c4ed7c854381
+S = 1ca3e0c9145fb2ac64add1d76763cfdfaf7a7128c4aa2b92bcb388641a26f572f53de708b769647ccd2c333429ebd45c6fa4eb741d4fa8f866241bd940459b23fad15c1ea60d0b1
+Result = F (3 - S changed)
+
+[K-571,SHA-224]
+
+Msg = ecd95f6d79d303fe87209b71e9e93e1a6e75c720765c5c55d9b65960d2bb8bf0134daa15feb15075433a381855f497193d6e9ec3d5e249a469f6dcba2752c68fe7f81d137fdfb95619a5d188174509bb3dab9bd1b471474645a96a40e3dced38f922d88d2947eca05ec16865f0c296d09386e2307a187360db7fba1fc97b92ac
+Qx = 3b545264b60be53ff27ca7f2ffd005df64aa1fcae3e1c5b2f42abcabd35f698bf8276d7be83a540872729d7de12343775d6204f132810b18f1fdd19f4e03dd14e7bf98d64133e15
+Qy = 4e9b1562ff211a82ae5aa52c307bdf4e6cb58354596d1e58cb4267dec5cdc89248016e6c9b3f8a7bad1ab9567b165630dcc4eec78531f5fa8c0b2cdd6f25a83a3f0789a46316258
+R = 132382ac5f1067a1e8a249f95ff97e5fdef38541e158e8ee7561987aad846f1dadaf7b9b97b4893b58e0aa5e204e0c7ebd7c515da172b533b1f100ee87e8b04017c91f56b014263
+S = 0f84b28d006c3c103529df38c3150d0ab9adcd3effc52096b2e7a96693ce3c75f241bc851f896d8b9a2d5472e69faa9d9a39301f78fc42c5bd57edb6c5df9360214b8f757d27986
+Result = F (1 - Message changed)
+
+Msg = 1aa42cc95c48368ee47b77ddc28f387b7c0cd915135d3a2ba08c848b81f371fa4069e5886a4331db67c62983b625c318123410d83b0e39b01f0746b5b885bdadfce9ced0c990e4ac6cb4b88e83d73fc6634b23ac2b08158d196718d0df6584d76167504cba09620f0c41990adea68e2a296fd4bd41f12c154efab32a970045db
+Qx = 1c713796eb5e275d76f7f84b8c2376faa1fa62c9c0c133332b37916c53b8b65ed10339976cef47af1463e27c1d60fcbdb46a9a77022c55f4250f1082b3c52ba25fd622612f4efd9
+Qy = 2e7bc6e95b47aad0c94550b7e8a951d7c480b35c1f6feeee3884ed04d4a16539989b615e892ba088e44cf125d02a98b172f7ba67a44c5049fbd4ed8d29f4d277ff1bd25d8c76306
+R = 14d9d6fce9e096675892fe933d2ee7834e849523589cfb2fefd3aa4d5b324ee0a5df733361d3d743ef92f493e0b9cbd800207b6ed407820573c0b2adadd67def812fa3ffa1c15ec
+S = 0ad48a7059760f55940389182a98000b7a8f641bbc1cc2fa47295c44c8e2f67cf9ded17513ff860cebeea8a16a67a491b4db376e50d94a602125625281927c01c42969d1e8d445a
+Result = F (4 - Q changed)
+
+Msg = dd54ccb42b96185fd7fc49bd36a3d302b3b1c9497d7c947a4b0a503b2e6e1b1b31e6305f3849eed58a3c33e36305cc135305fda80bef54d136470dda4b1a84ff15f62ced87b24324043a14476d41c603abecb45cea6f65e6df8a898d197fb6a520027d5dee056ae2dcb373def91313d2ce8a14105e221847bd561a1545a62a02
+Qx = 570945fc0714d698b2f7dcce60ee4704a75c54c724708bb1aacee31b05f8bd7543686804559549168a6f6c70efd95907b27fa59db5c7847a156e9eb6c09d5f004bd05138cb3606e
+Qy = 3b89882eebc269cde0e4f31fec0241f4e216374fe8d063be5456e0b25cc6e3a00633a96c122ccb0b9c2a17a41e55f3f25fc847c8bfa0e3bc9ef778cb5b5eb79ea699b3cc8882928
+R = 0a7d55e95da5317bcfea3c673f6ceb92fd77593912cd622f7575bc7c2b7f0fcd710438d93c9dfd2ac07acc5b600e51ff0eec130cc7cfd7be396a93996e55a16318b2521878fb8a0
+S = 0f4a9a429bae5140557c0984bae81211bf6b5d0d8394bde5992d36f4af2929e770446061efbf98d16c9bf75665cdcf7be5500c614a1536f7aa638f676735d8b4150cc776b9df266
+Result = F (2 - R changed)
+
+Msg = 13e493e15004f37a6878cc0f7e450265a59390ef97337729a1ceee8c8396218390c5c0c3dfd8e7f373d893103b84e29b48bacd203aafcb4d8933c4b23454a438cf73763cd00f5fef28598aa1b23d2c515810674d6419b19fb86ef850e9c74735bb2c99d88868ef0541c4200e40d03b5530f04a52363a5b26b9c02243af580905
+Qx = 4cb6eb90b44b31f2d79e9dc3d29c100d48e5ae3a565e8960ad60ce338545625f38bf42c88fffa8e622cf143323d1d76c2d97316bd086bbf4c723c56601ad8c750d4cd0dd8d42ea5
+Qy = 405d74ede964a4d6d87b6d41e4002e22bf18abbfc09e3513d022ca4f4f68ab430a30864f2d086cf7c5ffe9913c4842d0c72ff379d9de1b1cd8defc8bbb149285a14cb4e19c6a4ba
+R = 0e1f215d2cb8ccde79b0e7970cef329e373ab5120f0a767e9da620227e25b04024461f4f355cc7287441b0105fc650a785c83eb43f7cba11df91643c9ec492417dcadb848ca42ca
+S = 0422d084875197fbf08de7ade52ba6367b320a633256852336ddecb64d42177420d84e646b56a23f39b56b4a6580e1498cac720bb120669d17434c9cf0cb0db540b2b10968f5a8e
+Result = F (4 - Q changed)
+
+Msg = 82718873f9957ea3f7c89f8fd63e64729a5c85ff7d6c6c049a0271fd9790bc8acb3faf6e068c27272d45a0077ce899917b3c0aba6d95f960edacdaef4c44019ccd5dda35a4fae9bbb2a71979395f5cfdbd548bbf3724a2de0322d7bc318b0b01d81bc034458909c60f819fa6c08509a0e718632d19a743aadfe13ec218b43c50
+Qx = 334caa5a76249dccbd3b275c567b5b50a2428a4727fb5e85b73d5f82394c1d0c540a899303d111278365d602869a483d87fdc840550407f196f318558169467ad05a79d897aede1
+Qy = 2902df5d26582284e38995713d7e793d97d425965846c92d56481a1261eaaf91dd04c430453ced727ae603e2348805d637615c8b700780f246232268d8eaa98f915031476396cea
+R = 17d47a855a0c270f08acd9ac5600a3bf76da4986afff7bc125d0f0da446c64fe2d77e2d94f767de3130d86e01c06ca62038a6f91b173a6c3002f90fb97f540b297660e27109db3c
+S = 05d34459f1a5fb774816ed3ce1bc7dae14d5a130515256f79d244bea642a76f3d58a3eaa9d52a4ff3e6f3c326d4689318adf90d7f8cbab832c952d83387a353e3518c574bb72225
+Result = F (3 - S changed)
+
+Msg = 25621bffbe11e080afe845602e03ab9d2aa3c215229e4747efd4397bb629a997dfb0bf37cc5d704911db57a34fd14ac5f88b0d19509c90ffe21afb3117a8af04b83c7b081209a2c7c1517e97f5ecf774a112b2131a0b9bfcacf6a2888d0cfff36e9298a4a0582a106abf665da00d97d46a4f89f2d9015c851bc3849f6b4bd051
+Qx = 1c85fe5e52cd9e6b41955128f68bf3eeb71ed07ec10750b2b93ee0b98eced32611ba9f7cebbe9281852a47b728c55fb005bd132ee7e416eca373cc3cf29a5727b6e3d4bdc3f31a4
+Qy = 7186ef302303f07bf1440d06a04db5c3d88f7f8e566d6357867c3e70e8fbe5edb4fd09c32e68260e38456667bbb4e289cceb6e2bdeadc69e688f1e799050e01f2efd22f615076aa
+R = 0795caacc936fd994fa13b3ee292ca818ae0d7af07ceedd16406d431ab5466286ab2e6a69753a53beb1d929cea1ace36cfa8f9938e53190a6b25b8dbf50072cb4560d05fee60c59
+S = 0f03aea3b5ff906b739a178d986c98930f5b405c91a24c07bcdd6d468c07e8343007e7b3058afc2c16155c9c35700faf5bd5a0974baae0d8c2648771713e5376bb39dc9003f1826
+Result = F (2 - R changed)
+
+Msg = aac9f8f2777ffb02201d1f115bf2c8a5b0188110da9c1f7ab1693586dcc106c00939bfea7029bdf6ccc68a7690f42178d9acc32ee887286b132667f554c0d0c7ecb1c27a09b3ed569bae2e9dc34acea3b17a9e2f8fa9f1c259b8dbfbb42f6dec20ac0d3059daff3be2d4a02096b4956cf7d47ec1200bca3fbddb0736ad300a58
+Qx = 50f5c2d1dc6cc1eed4af35b787d9d3e4a70eb28a3dbf4e5f92703abddccaf950730c9ddc45c9129f9a216aea016ea71264995124900c756e991abb0174e42c87b809273e003bac1
+Qy = 1a0f73d178ae24d84e6a23cc3bc3618ce235fb98e8423b2e1fa3fa0eee87ec2360b12c409545780184008be7dc1b4881834b32315d5e55c68add7ecf945680f43641c4b2ef80321
+R = 080a1d20918ff85fac391c6388f22ab68c4b765ba11a8b2cf69f1ecc153026b164d3901911fe2564648a1e355ff668fed5b507cc2bf47c7f5882e89beb4b82799a699eadbb5f0c0
+S = 1353953435aa7f970a4e9dea048b27291ff48d835d4cfb39ee0a0305e1c323306cb69409f386e79512f4701b67ae3ea5e4c54d45403bcd08ec6cbb9fae864369fd7fb145ad4a5f1
+Result = F (4 - Q changed)
+
+Msg = 3960001807228dffd727432473ed3efcfc97d30b92bfbc02411b64ad4a65b2737b39ed06c071334c94b1f98aa7a05f94fbef556f7fff619eac47a01288a43581fff3eda79fbb2bdbdebf00619db2896bdca0a3246503bece87ac26b8b1866754824ad03fddb86f922210716eec2664465b34c327359c8cb2c3402701a24a4ffa
+Qx = 0f1ecdc52dd3c93db86b2076f7c3a1f42b1988197a0a7adb261cd83e201b5a34a7eb45029635f4fb41c997944cb4c85a4e14826120e19e5d5909a0dfe2473c57cf90ac85f28ce7e
+Qy = 238c72d7de36564b9e695fd080d11ce417376495176a486c98f939bf639767e586110e18fe651ffcfdd5e3f6afcf1452498d3b9ad1775912f8c086098073056d865ee6cc1607fc9
+R = 19f94499833e46f9eeed3c49e6a1b2b57ac1c0d916cbbd0a9c2a710f903fc2c5c8e4a328a5c7fd2b8ad1901f51fa02dc95453db4052c14f533172f617039798cffaefa5e45f6b31
+S = 00b9153b9aef95dfc975441782cdd510adad4f60e4b4be411c13cce5f0448ad38674093ee59f6247f58ca9937c7bee2e6c9f434ebe53146bae8bd13574a78fc0871d193d052ab32
+Result = F (1 - Message changed)
+
+Msg = e286998b189672588c8df83d2dd2abbf6ce8b23a65eb90e08281563c40f2afe717ce114451f73b8f781c5a1e059ab7610a6b0380c050cd028ce892ddc2e42cd9fbb4dc4048052c9d68e5c486f95a573db8a1f1f2daf3186023c3d9568d4cae57777e8919726e906e42850959e463445a604c316fad71793c45e467cdead3fcba
+Qx = 30e833df19269b1dca7c714dc94f3cb9e35ecf4fc2212c4f20aab610e813914497ec03b392335bbed358f1fd2cc23fa78433a52a241ea8d7e5055256b40e53d8deeb2c479ceeb2e
+Qy = 2931ce960092be649d293bb8cc76333868cf346e0242bb75474acb62176fdfcea4a4ddbba6fb4b2cca9c01457a0ac7457c628fe4f5e5e5ec100c374944ab9aa7adeb349d9b37f33
+R = 094a94e2595d8a2edc6eb5ba16af13afe47ff0279670e99128846102331bf3c30512d681da392814b336aebe65647f79d1cfdff78723251192d1c93b03a6b1453e5f51f7525e154
+S = 05c51bddeb6d32f713d8bf18279002a9510fdfd87ab25f03aeb7179916d9f0b789228fe44a4d84e65147c584ff7d8b86cebb2e8d9283b625efc09f84e7fc144db6ef2897e65f617
+Result = F (3 - S changed)
+
+Msg = da9adca07858bfaceec7ae20259d6e866257bc593f44a24885161e2caa819171188894726c0a9eca56cdc455eb4ff197294392a29f7328d312ded6f91fa3cc8ac077591cabbd1cc601101635214ba57c5fcd9195f14eca3361483daecccbb58870b27511dc4fdcde6854c6aa1aaed8fca6f41edbd9cf281c853a1995a6874d59
+Qx = 27d39bec7efba264c01be32fdd0867d45e0192af0357331a90ba7e9744c3d8a2ecb81be303195e0502d4c80ad927d067e1c9f3395e488de526682c38aeaaa3ee6fc9ea76f59a705
+Qy = 22cb62cdafcde9da4d1ad03e5e57d441a0720e56622db7edbac2cae74e9acef1b53bf1375fbdc556372572b70d74ead32fe1baacf6e03cadd655dc26e22d520bba4a6285a336b79
+R = 191d88403a0a4774ef96f53dee121ca2873963a3d6cfe8a105602d95c661bcbbd6198e7bd23c55302fc019433457f13c000971ae94f92011433ea830e2b2cdfae7c45e039b79d52
+S = 03fc07747d5c9cda2f2ce8e26448aee8f5788a1d303417fc8ed9fc5b685b1506960ce5426875745d2edc0d5e8c706e7342d55cb2fc9bcff09fc32db1f027988e593b76021aaaa4c
+Result = P (0 )
+
+Msg = 0549bbca9aa9d93f02fcbfc16d604db872cefe72cf0438cca8ea80b5f241615a9261f94b2ee588cd4907b2750a1c4b0b32ca5ca3408b6369513d420f727be73ec63cfb332b2f799d05d5b08b63066bc528959ea616f0ec745b28c667b85e69bfe4646a864b4affba2aca761287275fd7cc0a0e30b05ea00a79e9874d6649b084
+Qx = 1fc8d390267cdf1f0674284f86c8da0c85b6c2a69a04ef9812770aa681728815d49a3b7b67ecafb9c41de32bbff6229d9d1b45806bd42bcf8170161b800a63e216378189e39a5f4
+Qy = 4a5682d20b9c20d6451ccdeea96a85ba01f11bf1d3207bb16aba35b5d5d9e333f9a069c40dd924ed4bb6d6752018e356e83fe24f0ec4d8844b433d01c84cdf1a185aaf048cd16db
+R = 00f31fb66a668a3ca1a78703c7b30d0d511b5c69c9b36a61d83bbc97eae2fe4a3666453a5a65a113c16c14c077aee76ae6009f8ab3a203760c3d5125e68f18bd23901da157083f5
+S = 09eb7a0581bf2317023aebb3bb9ba9b4caf067b55115697eb784f4ebecadf77e4e4a49ebe4e7d61be593f571cc1b9bc257a92a357eebdfd572de292739c152b064f8ec89d7017e0
+Result = P (0 )
+
+Msg = 62a1cd6b512172c304d3a2ebadfc56221ec8b5e7d48b1b8f8cdbfd15d330c625dc7b09a0bc0f12949ebbb206ea282f072b22a06c69b90c61947afdbbd08c9f3a77d945ee68dfe6567b7b616174e4c45943c4f5bc7343cd6006856c1fff6cb745d7d8a187c0243e37b078599c680f2a0a1d96d3337eb872c668e0aa038ea8808e
+Qx = 0b02325c7830d3134f473a1a447c208b76c0dd3d721389b71d0b8fe74c4a2b88f031fb7eafab271d440c2c5c82742fb50babe46620a1fee41236959fbfc63ec5c0c0ed1adfdf96e
+Qy = 594bd6e0e703ba096768195608c25ae893958a0c76f44e9aae920a50da5ebdbb119bd67c03e7f225733890d090cf0717720980d70498a40a122ce1ab3d9cb85d0c32b17114f36f9
+R = 1cec8a00f2fbfeb456bcef62e96b7b9da152363430616df57340d18b2dbc9baccb559d8ee870b22004c9d2d0e3b53b42023ee400b4bd56dce63fcebf36ef83e9403bed7afadd8ab
+S = 1235aca3b7adc7ccddddad9ced6b3d2b80f69cfc07bb5d71abd6f5c5e7940447e7358bae182aec7cb919d9900fd333f2cb494a5368d4440b27636fe1bc5440fab8008d2fdb6156c
+Result = P (0 )
+
+Msg = 0e567f30906fe84d83b3ae03fbfcda02d1d4996c41f4920c4d00eae7ce9a4a4804f608b5eb01f16f254ec23cf2f08454e7e4a1327f3b495bba70e0744515d8f126575c3171cd3f7a41079d99970219e16e12b9c5ad167c1a478f5e25fedabbb61d90288da6145cff21b6a5e835b29c31e21e7bc418a72e5f8e485c7b6ab2df5b
+Qx = 17503beb4e2cc2ac2b649d8c38d0f9c02cd888ef0586d2757239393fcd2b9f1c3bef32fada01ea555fc04c976637993926a9b0b12897b6220819b48a9a17363f8c400e17e957b36
+Qy = 4031a5af0a3617b27aae6ef45ab6dc01be8246a996cf43dfefc2726235b080bcca6a52df5265b51260edb3cb4099425d051f0116eb0e64aa28aacec6a617a0435369138e7e2a97b
+R = 0541af5654c6f6a307575d621dc07bfe95a2b3a020e5a84b895bce917677d43e8e08bb27fd5bd1efff2d4f0acfd2d24077a17f424ff240d4054a828930ab9ccdd20cf9e50856ba8
+S = 01fcb95646641da9cb05d2987fdbf3595ae5a1a1b97449426ee66360f93669dce17f6a98fb3f61cb5a0602ebe9ddf3aed819fdc5a892b335f348459ceb48aec2a84a046e279cb86
+Result = F (1 - Message changed)
+
+Msg = 2c85f57125be7eb27d416bda8363fec25b68d32661344125d5aea9e20cf003cf3ce01a8c977d21b44239a25247f82e13289d9c030a9c358dfb92cef07729d6accadd286b22b26fff34b3ac45cc4735d62534cc155c1e2eaabd10cf30b9913d923226e545522ec213ac5fc5fb6a2e8741d874d706d54d3a06dd8e3ab0af978d61
+Qx = 48b4432f72ba3d0398c541b24570de076096a5c3e5a490a8de52b3a994abf7b2e8f7fdfb02841599718d9de400a4ebf1772ffda1cfbac6d8da88ac37ac8b131a53236e844e56341
+Qy = 6cb540d7caf926ae1e00c85f9cf30d8e4ac113cedb33e87e08a5a247350a99643c6e8e887a4b95e7eac8e3de1254175cba21efbff2d1a8b108ab10b053eeb423f6fe1d2c19ecbab
+R = 148452e32a5bbb04cf14baec5c7658ccfaf73af6edf373f58d975fafed27e3822cdec1a615e291ceb66f5e71cbcb78afbe967565bd4a4191d5e1f4d4d759d5b2c9a6b1af5d81dd1
+S = 06a8fe3036cf46d01827833576a156b8fdfd047a8a42f855f6abe71e2a22e0b2b6edaf161236a99015aa7608665eccb2a6063497ed47056d9d7c2f713aea8da26ddda55ca4567da
+Result = F (2 - R changed)
+
+Msg = e58f7a387f55727547c6b21746b284b9f01b952a082cd3c31793ce32f3d355716560b70b6b94e22929de088f3c1a5af5330c8f68b5575a70386e6cef3ac44e73423e7ccef68bf4e437cb966f0db221e580e78fcc2b2334fab819c03369674b6f44a38a9922fb39aa0174bb1cfc0e0225d4b78506256c9a4661005e1ad1eeb635
+Qx = 3afc11fdbeb442f457be67f2ca4f58b4c83c1d79688c7d195945581eb2f4323abe8f98925a77f4ca58c13049b2f38117d704ab043ae72f74ccdc251f1b27f41091189c4b4a95bde
+Qy = 5bfd460103bcc8a5d2293778c0b735aa6e8889e771d5cff373c6f8a6a4f43336dd7b859f6939a692da4fc2f9e00de5b969f9a894078a9fa2bd19e306b84d4de7d67555ed4352c93
+R = 053a6a1b6ae2e4b5c77364bf169ee0eb132a3018dc647b8f6c86ec1600f357d8da40a3fc3e6cb48be77228df94926571badeac2de01806c126419d82f9d9e8e7b9b4fe46325c0ef
+S = 010021dafddcadb93d8c2520f71cb28d40d19b12bfd38af9debdf7b5bfa25ce18f2335aef6c6148bacf6113b0f2665373379c6487e9c1b8cc695b915eb6cd52f115ede6c5a840d3
+Result = F (3 - S changed)
+
+[K-571,SHA-256]
+
+Msg = 460bb7a8161f9f87b2e3b9c4a90ea3883a8e4a0d147f10faf571a67270b5b48d313bfc4c0bf0a198a0fc39060657d0c63d8d76a448fd8b9834b12b061bb6bd8f943b7f0b6dd63290f294a0d92aac14f911db221c5deb674dfe8e2fba3bf660ff9b9b29864727817c7ac2bd6b5f7bd6e671b6c5e06011f6da6cb4ba2a6bdbec09
+Qx = 595e4bf949376b9f84e25f1cf748b1c1206e99caf36b5488ddb54acf06f31a2ec0092f6faf2d31b33b573894b74fec3c701cef543484fc5abfaaea2f44737e7dc369de7077fa54a
+Qy = 53a0970af043fa733102ea8e9154c206aa4db46fc2bce45066eaa23bca2425a669b4e25302ab7417113897c21c6d4813faa55a9263a2ae921145d9db36fcd839743f3bf2e6ea17a
+R = 0e6b97fb4d12474c86a385ff9b9b51b2847192185324c2afb2720dc48d902488215a7a22ac171e8f6ba15a079ae7c85074844b2f5d1028c8d50008d7a544add9af48c29bd07e865
+S = 06e50bb209279ae5cb1f782c3d3eee07984d56de353fc9af1ad56725e2a826acc9839d8756fc3b18aa69b06caa269e6fb8ca34f2cfd675dfdc5aaf490aca53d3e3247c75b3ce1a0
+Result = F (4 - Q changed)
+
+Msg = 2fb114a4900b7df5e4bf05ff6ca78029c406c529dd4e1058ee9e87271e666d81adea6860f92fb70ea2f327be1925e15b5d3eaa1deacf2608beadd01066cadc07069c1d1cbf7b41626c14695f93cdbfebf3f216994fba1f4d70fd2d18607713ee94a986dbb365eaf5c66bd9057dedf3a401d85cacdba123f55afe6681673aeb29
+Qx = 6dae0c6788053d15f6facdd10a8ee8b69247c9db64fa806e2d1b63efc8577459111e53c2c72dddb2244109c8439e02b4f45e16ae7a28422174cbd96e106a791389841da0f14e134
+Qy = 1b103e819471c38a02432374d96a018a568d793c20812a15dbf9e1eb6f531c0b653a3c91f7e67a2d0df196edc3f5c0f50742c57c7ed77eb864b9ae221fd40d973fa7e2341bc55c7
+R = 02af273554ed8e7d5c6d1a0c995528bb9961c7d0019a68886711a863b8583e5d08e0e926b3318bf4668f44257a39092e662e5324e44d63883100690da7094199fabc1a2d731ff9f
+S = 03af1e0d4733aa4b1e3819ad8215e39b3ce0e6f850039c1df574f6d2edb4f31800900c61b9f7625c218e3a7e066e259f6ebfec63a50fb1b75aa65507347a3e92ca756e5e8360ac1
+Result = F (4 - Q changed)
+
+Msg = 8a7a83f0677da8a71ac6452b350197eb608c12673d402468f4c16395f68ac08a253ab36f9879f56a6a8c49219a845a977c3b7cb3002c8f162d1fc4cef07808ec90dc4fd418e4f85b0bc62f58e12b4c5ab3f62d4675eda40a207188edb112242a385f199680ad68794c997a1126e4fa4cd349d41ade9a95a9f229d35b90e9feba
+Qx = 1d5bbd653a4025ac1953df168b367294d3232c278a35e2b5800ff5aed26879be1719eed0982a04014c7e502430624a6c0fe279761f433276ef26752d29a2d961e8b932c49267e42
+Qy = 2e1188d57111fe94f2229a5f49093dea227ddcd154ca5eada47e9b60b1b2e59783562710cbefcb8955eefdf8f08484aa9ec676bae0bc0355d5a3618e2ea74c9a025ce4b5a4324de
+R = 1248630a22b0f9e6d4986fce399d0a8bb4bd0c0b4620c0b64e30e54f118d666a462f5cafea58958211de51554f4ec35a798e676c9b8109d8ee6903b59e1c3f0e2729ac2ce57d95d
+S = 108271fa245dd7e45d19c7ae13f075816d1394bf883f75e8997b78881b51c6cc8f2be9271eadec84d664dbe91dd80bdf39f82da549568ca7583e383e8805173a533a1ace755107a
+Result = F (2 - R changed)
+
+Msg = 03a3753f1ffa98be3851717993b4d7e5e33992770fafae7f998a6a40195bd49b82c0135c2fe28c2f91a3397cd8e9f0b285498bfa0a5f31eaef9c75e294b37dca7bf259e81ff034b8d1e7e5495997a461de1c523f0ef4c78e49db832cc93eb50230934e6b58d9ba781d3e9db24c6274d1e2b4b4ec8aa2735acbf9f67e1be57a74
+Qx = 5f941e075552856ac66139c47e98136d7c18ec71413e17de33347921f0b06575269597a0e7481179d549eba832fa7285bd76734aadb16864758673aece6ebaf37aff1f6091052ea
+Qy = 067b6329dbe147bd596e90465ea977039712ee9bb14dc7aff0ce4aabd0cca5e5f3fa7ce75d123c78d40acb063cf512528e0c0644d8de797fcc4bd3b03d2fefc625ba5d543f19c19
+R = 145e3234ba0a2848dd22fac5b2faf246f10068452ba71e9b9093e0b7815633f27d447bbff61a9ae277a90dbab46fdf5467bdc6bae84adc09ca9ce45813b03e3a3103c49a209c435
+S = 19100cf49dc725b06e7ba5eb6619bb2520908c658298af884576f05c4e7bad26b769ecfc5aa130c901f8ac86619c002f44465733435cf81e8cd6eda8e249ad25804f3fbadb14ffa
+Result = F (2 - R changed)
+
+Msg = fc86ead346f281ced3bce375c7923d0c404123169e2c2ad56280b002a25e69b1e52bbd69fc26b17922b20db067d3387e7f254e09b23e979681e0eb958146dddb3db2676a833cd3d0abe29a8fdcd6d52bf75db230f6bcae5edcfdda61ed6961c8cab02a4d1aaecaf0661deb1b51fafcc3b845f34158bbbc93a31009ac83b979af
+Qx = 5365da6587be2996c33ce94afdd87f33e0fad5aa52ad2c7d6b80c7a5155fa16634f0b1a6ed7208fc650d3c162e7f007dd66b9584e9048bea101f00ee2f567b5a73623b6e20f9443
+Qy = 6a5274e9b78ba5e06dab3a5b5f3819ea87e3c4ea998e667dce7149b255eea477e9073ce1cac58f0daac14aa493b9a1aa9153a7efb8a4f95b7e70771f30728eb86fab0256f0c0f0a
+R = 03ee00a4c861ffa71be6ee34711e66f3a55a63dac3a929899da99e4a4832bfce8f069f71b2cafd76ce7777aae57324cdbe817e370f5961e79336b49b491ffff49015c9e67e6215f
+S = 1a6db0c90e310b9602ab198d617c68f263cef3dd70907b4d17ed6111048d3d479449f0e91e682f808f99fe2f0639093fef04e69f3386fc3cb6cc85788f960a963352fe821a1f653
+Result = F (3 - S changed)
+
+Msg = d8759160235db45630bdec695fbf3e8547438735f0de07f96ebbbf95b45fde331642ae6e54a33d22c21d2aa5ad4a896dab5d6559095818b6202a77560eafb350c80d8d85b68c1335bf2388f9537cb10efe7a10460e19995e02d16be8ce1e43b2db4d4c6d7d132740f1eca1edbeaff5e8cee0547fcd835d873324548fe71a8282
+Qx = 5ce78c7d4582516e07c33bf39c93be1c3e077c0d9dc5613de592dd77894399fe10a4fefffe410da2b726946e5e80a4271d3e7c80f0599eab8c519ecff983d4a77e5f2195c1d2f57
+Qy = 6102058df8c9f6ead0320474f6166660a3e3be908bfb5bf6e0b1a13c7ed568e9f310b8564dee034b5893eee91674c307e7fc02d82d3aefda579370f260fd95557d0317468194877
+R = 1d289ac62551aa5b854fe0a7aadb4135c41f44bb5fa0fa9f892fbf217ffdb17a9de2c25ee201307be20722dc8c21a3192999ab3ada367df745d783822a2dfe68e00ddfb8cc47e29
+S = 11fe19ed0f0eaa4674bdf5c747a8b6c8fc1d457d318a35ea7f1610dbee22fe48e2f2a5b92349a362e243b00f4732f74fa8f09dfd2d5170783b88ec5c06d2fab65f31442d6278dd4
+Result = F (4 - Q changed)
+
+Msg = fde80778a74102b55dd940e4b95674a5c20e99423c5d54d9a6d4d6b7057eff692e3090dfcd0bb12c2ebd394ea9eeb76e4dafb4ee041a53ee89fff8f5cd7d238d1508491de977218c06e3770189666584954bb0ad4b1bd031877e5ba7a33115b279983785331c5821ef2c82ea0b92061d06d596bdb8d1a9f3c3e609fc254ecae3
+Qx = 1a743317856b398f30dfaa274ff5feef4b0715e786884d181ad26b20297f94ea28afc22da39b146af125358c4c4f6da692315cddbe4f348f35b9241a0ee4d80b2558bccc59105cb
+Qy = 75ffd0dea267210708e0a8cd8e56b5f8dd32e4980ff7783c2a3129fde5cc7d588e16fb5e93f524f3a404e99a54997a322bef73c56a524f1e1c6ef9281dcaf8e300a96ff8b8e1c0f
+R = 1f72219b172c395d58f4b686bc92b209c0205bfc417d4035c46ca179e47eab48897c50014818c334e16c11d9312246c3b3a024038ac2e56fb15b402e4687e6cb61fc39e03642c1b
+S = 1e83b52feec9680a4f6759957e96e0a399f919bb537985dd7e2f9ad38a65819cdc7a5fc66f89bb0f47efdcddd560f37a3c4887e7b1cedda1726d46d51bce58da8a270e6e315f699
+Result = P (0 )
+
+Msg = b8af402e458ccb633adc72285615540202a8f912fc66c8bf5f3e7e0a16c660450cb155122fd1b4565a4e83396da7fd50a1dbb760ab14dd26684bd05ede120c04edf684b44ed4a02a04a7807b8acb26733010de35c8778c72d61bcd80bd13e4a4de7ca0f4dbf5a681cb883ec6b9820f2d0d3aa7f9d1c5e266ddadbbc1edb0e75b
+Qx = 07460a566c81d801735add1e306d10d081caaf63781b7a71ffb7fafd95c6c79c3b04d246271aa52352ab2c8aa0d309c6927acc0093cb2b3f58971962cdb9b418d5f5ae728224780
+Qy = 7ac64890bfcb791d3955c13919acddf3b451dfc4e507bf4b9b511a0ba28d8368289fa64c20c3f475ce3ec0c578bcd2f7605c0f71b6fe826dbba972fd1adc3a39042901a8a87d4bb
+R = 07ee8d85a19ab2cf9d5a3e1d16620c5fc2bd7b6d66abbc469cb6223577c18020043ff6caf02b361a23af1d052b0619625d001668af1d8d114ea98d988d3623b5271cbb23e2e95f9
+S = 06f6394a06e4d63d1db8a3ffd9d589ed45ef8d630ca2c303a1eefcc9abb9771a5759a4c080dea6901317ed8d06195e0a0078dffed282cea5b45c0606d087c03ac1f4c2c6cdafa1d
+Result = F (3 - S changed)
+
+Msg = 120b41ed651be54b531de971a0a6522b7df5595172f51a72f77da48b06db4beaecd1644dea0f5dd7e07d6917f19f4be8c7c48d1fd13bf86f2768e2e21b6014f0bed8459f994f32d75925b640234174cef306f80870e8fc4598fe4bbfcda39ca9d6179f57d6a99487af64c383f6fb579f5e04c5151767fdc7c87f9bb00285da2d
+Qx = 553ef19f58c014a5384bf5c9bde8be189da61b8f865fcadeb5fdc76c3a36278d2e6a1ca5bbe6c2a8f5a65f2125690703b792ab7c0ce63a16dc8326667a2acc593fd07bc9e8509d7
+Qy = 4037a7af7060e764a3f5c4d0706552a8206161d27a45325797ffdb027317567bef5b6508b6ab8b379612c23b8b13195d190fbd52349fc2d04f0442dae1a0fda04f2b988cc2a5238
+R = 16ea329b3c9fd74fce05ccc16b748a9a91b6d9abbf4eae6dd9b0c229f68311207f8407ff5a4611cc15e0ff8485a35800fb648ee56e1d85ec0a40af93d50de5207cbd2bafafb0ee3
+S = 01103adefaab95f1bcbfc4021395a7571704bfae395c260bd9efe54cdfabf56c3400151a107f8d81c7238f38998c58ad5b932e079dfd33d201b4e24630b8170548aa91a6e4ed934
+Result = F (1 - Message changed)
+
+Msg = df8c251459a4e82ad98bd9a635649c3782b1dd8ee11b3369c60fc7f96887be887f7b405ea965df4227880d071c2ccf952ceddd5a63a8dcc04e15d48a9c727c5db8d84e63d08f6933b4a50a4565f6f29077049ffc10330170e97391f61b6e6eeab6fe0378933b1d2d1bf6a24b3309ed8d998887bde242aae62c87337551a47d0c
+Qx = 121d53c6961a37ccdebab849dc0f14068ed48f6b4031e741b56ee8dfd5fa71ad414a8bb4d7f84721b473e64ea0eb5c3406eb2ab558dd40a5f209fe3f5b3507fcef8948e267d26da
+Qy = 6017d8b466757470c45af29908c8346e6f22c2916e99d1cdc271b16192485b29a1049bede83627efce8be4248692e21e7e299dcf20820f6e9e11280b6b402fa48ff9d03818b2c90
+R = 0f654d937d6d8235d3b818340b2d8ddcb4fa3bb41a09a109af8801e1aeb681cc27948c6f0bc11cec204ae7ea487061f2e06ab63f011b78e931623a03a8f6dbe0ccb72267e5f478f
+S = 1b376bbbeac1549c85601000e7ee16df2426209a9b42b55158d2482373659a78a0c9f1a66edcef57777dfeaf573c5060d8db9453e15b305801aae176b1845157002d6e1644276de
+Result = P (0 )
+
+Msg = 1ddf937e12b016eaaf996b76e51fe8837a74e9a9fea3e636143a4ce5b9fb71e0921db2b168e2d7973a8c25bd28e236bff7e9a8ed8f1d992945252ea21387648bf66685e38213b1e80061eb1789363fe8623673f25864dbadac85e762039cf38c7cd550e980449b01e4b7a349f699c74cbeded3a32cba4ba4815381797a0bd42d
+Qx = 0a42c9c44c49be8f5068309dae43b7d9ff90cf22783381c3062bf20365b406e41ca8082b1876ebb996feb7735b1c094ac4b85afb0ae701dcf7eb94c561521fcb309c3675d2fdb48
+Qy = 23e45e76183b80e2cc8d4806cdc437195a038a6f8dd0eee132d13f204f4aa8c5567e18ea2b17e37d6a83d594f985df30e4aad3fd408a11e6d85e7aa5db63a71d27fe7d0daf6d4b7
+R = 0b483db2088b49dce0dda82befac987c10696f38f3aa24cbe7b0945a2dfd6a1ed4d09ee47b3b19d2145229510a0ea215fb3abdcddf861dac142666025fea8e0de77af9145353d1b
+S = 0d367fb5d396cabcd0370b8cc00640672cf4ebf83a18af3fcd20a75274b00ccf83aab20bae4f644f20537c675ce72d5abab1b9ce2ab2c5b6d7cbecb10ce3e8946d5d85586a5d237
+Result = F (2 - R changed)
+
+Msg = 08de9f8fdbced59d31c8f89a2252a1fcfa8bd2e82df5533d9841a9e05e978eb8ee8c347e02dd22a0fdbdfb69b3f98e5649b8140b61fa4cd63e295aa6e33d8b3f4242b295d7a6cc8b072e46bb6e9da8c95d12e52dccdc01111f425186ecbbd8e065989b791176cf569708fa8c99a8445f8abe3f9aef36bdbf9672b3d3d4f53c7d
+Qx = 17136f5842b3d543c84b234dfd6a0b91bb2431366da9675932db5ca2563777e05dc9b317c5247c78f92dadf2fc1ab87f85740ca0e52a48ab247d2984300bcd77c7a8d701daced46
+Qy = 103683cb309b14d662b96e8555459b40de829f10370ca7747e93acb193141b60c26a631640992f686d94ab8f0e044b46608d756af192a0608fb262245c5224d3c077e84eec3998c
+R = 0df63d107b3548c00d4e1a5ca241489205fc2b8834c91932c087fa2414206199094f9b6001c681a8115ce72e2bfcaa74755c427912ece182cc923171596ae37a0bc18ddfa28be81
+S = 15f755f6870ebc54abba2f05f9da5f0ecc48c0b0eb57d7c92406d0b1591395f8d41453de0d77d2784b1fe40ff832f7dfcabd4bca06b2dcad43a49ebd0196c60b5ca9ad9138a100a
+Result = P (0 )
+
+Msg = 2f8e19f1e5d5cd35b93af2e9c5dd6a6c50286ff907486b482788f75dcddef0fcb24203897c6bf30fcc8b4cf65fe992138eb60d957f2dc7f85fcfa6a9041cd0632e809a21800c1f1e32760f1fc74ee2eeb93b93786ef7695e48dae5c94231e6b184a981153481b400f4a6691299e4b7d99cfc5d158ab6ce614daa64f14c69d20c
+Qx = 759af6f994ab199741bb78ce76a71f012d17728d363afd4b170a0a556f5938c76ec91d47f7059024392ea8c51161bb34755a27b2105fb2118bd25e3062130607fdad1be4d3dcbed
+Qy = 4a2b2befdc3514999450a6d7c50a54d72900313ffc4e204b12999569b70cdb5da5f6790515c39b2692d3a1a210e92166e5112aa6cdba02fb777baa9f21be20a4712c004f83c98be
+R = 01dc96f14e408fd8b5a69c782986c324c8e38d9f4992b6f431572e58a08347806fe18c441f9c9cf5359b1b8dd0bb6023990a1433611e68df793053dfa5be9d61455f0e8d13c0c40
+S = 0cf712c5429d6967a45bce70d69fe282814b6133de15cb85237bf98796350366cd6fef55a659653d0058ed853d4ae0a27dd5d7b8822d7b389698e8703e7cca3c3c88fcb2081faf1
+Result = F (1 - Message changed)
+
+Msg = 3cf870d3412633b5757c1abac181b82a261bdee39d49d19bd05956d54c0c347278da72d101fa5b928e260440857895ac8f2616513167c943dbd50eef6007a23d10b42bae22b2ca80c09ebb113c32d3ff144c70326e4ec15d4586d4382536c164bbac4cf4dfe282333dfbb19fa826c6d68e286d6f16f72b7ae577c2eddbc8073b
+Qx = 7397f0a36839e8e37782f2b29cc2cb35308df50b7cf2e7d671d2023417bdfe7099c1373aa7efe5391e28c33e3a515f1dd3e47b21ef4788f0ec7a4a5ea7a024549358c4486051d21
+Qy = 2bcec8e94917b4560ee1c5e9db05930d5fee9830fea72571a5c99a7e12f916f80c22830e59309f11a7b211e4ce16499f3e0a9fac2cdf4c9cc627e116ad5dc02cdb53664a7639647
+R = 1c58d0c22d83ec4c7aeb802a16f06ced0f9f34476dc6757b445200fb0eb6290ade23cb674152f3bf4575ace8d1e2485c8f2e5f9dfca965fbdcadcb61bd420aa7556b854fe11dc3c
+S = 1a8febfd48965a5cb2e5fee457b32b979bae6b74cc36e1586d9163e80d56785ff754d4cfaca990ac07b4a21b1dd6ea772f1f0b8931cbf058221a76bf73bf6d9babfd41da2cbb7e0
+Result = F (1 - Message changed)
+
+Msg = 0fbf25af2f74b491683bf78e6b2ae087e17e2b8309c44d9d0f039262f00043604ef006d766cd65c112da0f2478b04dca7aed11b3865bc0c8adeaaf7990636c82fd4b5c8b514926510d3a7117038caaa2ead35fdfc143f025e547d89b3dca18cb4d714da56dcd7ae7d93d4859f787b003fb681df53a9e1cd0fed262c49d5300ae
+Qx = 437931895169a5da9a2d0dbea0e16d7e33875a1425d4a55bde3184de48657ed44c8a3655931bad97da21de3d3e29638e5dfd82ad95043f6f5ab4ee18b507e0e0cb3458ced63524f
+Qy = 357c41e21cc68a40eaf4407fbfe323693e84195f3e6f6bc8c222d86894f41ab5b2ebfb994aa92dd751b44fec407d2a9eaf8123d0058f4405859be21e5d46a65fd4509dde835309f
+R = 17e90ceb1d371c32158d1be04f6752884f3b3e50ae47e2f61130d888f7040022d712c9352e47488fddfee1abfbc5f833104f869b397116e8a00ff51b884a7400d09ad09ce0c547f
+S = 0594c914805f822225db8ac42944017a71618cd778ed798bb92078d6d675f9e9e80f97a4e4704af70fb8f9b908032a330f7841b2a2ce8b19e2ce1e21ea4f22f28112a6c19d424f6
+Result = F (3 - S changed)
+
+[K-571,SHA-384]
+
+Msg = 1ff5b900ef55f88e15bc9dccf7c438a96a2fb3f222355f0a15f2ab101d8517fa0de484263b803bf0e8dab2e9f5aa8247cdeee96e4f21508f0312d7faf8ae6723d015177fc64251ccc7d09386fda020e8f3ef39925eea13f3a52336efb1292b294e10283161008dd2052743858d8a4566289054e914099184c6c91f694aaa58d6
+Qx = 670daf52374c10a3a6d0ab0a4cf54c366f186acd683c22278935e30ffad95c673e39a3e2696c601ef0f2ee44a9dbae599e20cf447f2be5993e2ddd0ce69a9a46fdaf7d9b717400b
+Qy = 3f5a6d140bccc48e301b32b24063e9ef4e283098cf4ca097181a0c331d35bc6ebb2dfbe7c394db0fd3ee1e44120cc16bc8718e6c4f398595fa048ba8f4687b723713dce59bf4979
+R = 147a0e30ccd25c13b739f1dd382be2e2c2d5d3402228730df67b6b8da8264be8cf609b76a1cb0cc93e4dbe27bfafc8c5d3389f8b2f0077fbbd884a218f7b3abfebfc20f1787bcff
+S = 031d00428add063c01ccd003d001fbc02f6c3b377d64ade7ffc68c8f3c4c0789dbc03e4139587815701937c118242b8b41d57e38faa06eca3bc23eb246c424fb1cfadf1daa9658b
+Result = F (4 - Q changed)
+
+Msg = 8ee7ef50c0d5100ae8a62b67c519fe358f437c977cfcf53535d436fe74a8d9125ac777aab05f15613b066bd51d61bc46cc31f261de4fac8866571575c0be01f5015b320199e002178c07a4d43ab0f459cd7f7a701c061242abe8d304b85ae9446c9cebbe511695c8e776a5d2fee6d440d2bb07d4f84da3420cc6543b7b1cda95
+Qx = 1d38cf3f5ed5f2ae8563548dba8b9799a5e5620ae8455e9f7c7f73e8ddedb68f93d7e463693907dec5bea1eaca43f6774c52474d295f78911b4ff5e659ed470dfdcaa832a99f46b
+Qy = 22d6d4129dc641eb80e7f62aad06dcb2df22b1cce086d50cea6cdf6f80c7c5e4b6c7d637bce372f6e907b875b5f9434e64517245cb782bc9970fee80d171d70731181d156d4aa94
+R = 1f1a29c3894c66eefdd67874e0615c4d314ea922d25308e2ea008a4a78006fc0b057d4a576f6010981b0d5d20164738ede0cfb9151fdab759b222dd41b6ca5a2f44818a8a4252d2
+S = 18f47485f03107030100ce6e11d48035decfab5c214fec4f9e8a84deadb0b0d554f45e58e82bb83448c9e2f84c271e69c703dc5dd9974fcae7a9026c27b402c1f88b266d67ac565
+Result = F (1 - Message changed)
+
+Msg = 3c9440241dae1a68be4ed383001ae432b8b305152e48e966db1879a34e60075326d324a376969613955958a4712e4609307796cb6ba617be3d2f6610fc965cc9edd132816068a8c76e5c32330f5f9a189b099d9a6a5305cdf2c672d9ffbd8549899fed3cc73f4e739646b4fdb3d3ef817292fdd0dd62714288e42f91f0b562fd
+Qx = 41cd837e624c156a1c2d7b16ecb20938be4d0b56a0a2aa1780319b0d807acbb039398f41c90eb2def60c71428b59b3aaec19b9ea67d97f479f1e30840c81d93133f76a52c90c832
+Qy = 2c047a4ff425ecfe4da8b98abbebacff0bd86d1e33f2c9dbc9e627da44d75e98f5d28c8d9f0c581c5ad13a67069bd7c3c7a79ea656bf05ca4c46c759c0cabc70da8b1097f503229
+R = 10aa8c6e6b8a6f778eff5f85734b5be4886583e06a21a85abc0c1c7fd27f76dc28c8da069439b52a596d16a9e41d9509636e34ef959ac655163abb774484269bc78bd96d07c6515
+S = 032b260d2131beaa037f40725b00702aaad9a7633bc51f7096f956ad62d5f31425b036b26fa5552515461b47325eea3f1a66e13c8a2142b21e0f500ec621d1c9a2bb7d6bbdd64ff
+Result = F (1 - Message changed)
+
+Msg = 9cf3d1a5516f48152ed1e7b4123c599f25b17b7ff617507b0b4bc49f340a2c593b59166a40095035fe51ae0d125ad93c95fdbd3dfbb3e6bbe2716b2e084269fd40f84d19221c81e28b20d772423091da6721c35692183bf6410d9029fbfcf7390c1e84a1bd709b48012266a175d48baf768038ba10df3181a3946ca270c701fe
+Qx = 3322efa2f345a4486b45938187937c10b7320d0948418e4d0e34266c2845b8500ea1832858d6189a2c44a22406eea9310225a96402fe308f97fb54bf7611683efc41b515a839a20
+Qy = 25824562ae2068577c5190b387041ac27e8db18654e67edaa9928f8fe3b0d04373333cf49a78fa456427badda22e11eeb4c77c157d19433a25b83bfe3316af582dd3c2b2986c4a1
+R = 0575d8836f0f906f38f6dea6fdf14e50eca432e5754b26fb07585ff5aac970b1d75295cc1b7bb1f076575fbd6a845f292bbc00648c6d146c98707ddd4989914af09fd790f58678d
+S = 0fd416b4321197653ce896d623873c12e4adb9431cbca3cd311db40aff374221374a3ab03320795c1748e834e5aeee665c7b20115490d1383ff5953ab279ca2a343264af07a9839
+Result = F (3 - S changed)
+
+Msg = c169a8bfedc8a1c773c913ebe996c8fa7bba9435b8ed65c4db7202b3dc79b3d1548cb2cc08695d6a7ff4d848404a46ea84f0157664d8daf1d6b78a034681b465a26ef36575a6a53be5b0f9c858dc218e8dda39dc3f4c8db55673ab5cab237567e8131653d2abbab89013bf5999744c5c2a598479716b514f4c8e123cf90e1fe1
+Qx = 1c23b36a7a7e8edc2383c2f7fd07c0caac8d76da668ddd73e518983bc334cad22d3e3aaa59edc88fc168bc0fa1d886a9a8a67d62f693fc6169379a39bda93c8fd1e2d251f3e84ab
+Qy = 529420b6c157fb51eaae5c0441a70ddd4be6e8c874834a486b20c529fcbfd35236f68ead9cfcc5c378fce3c337551a06fc5d14cfec917a3fa8f9c9e269939d9b9fce03d6b798cb1
+R = 15ee5f9185785fa1f7820f7f1a5e0aba87cd4a18af61cadeb03e3e35146f7add8f296f6d8f9aeec7fad7f0511652c01912e3b6ec51f4d22bdeb56d909c9bf0a0ff6c199dfc7526f
+S = 1c3d00825d0dfbae281ca9e856aea4a0856e65620510f08185b3334eb2e7b757dfc1278436c31ced87abb5406ddf4c2e709feddf26f9dba078212a078364c99a82e7d843a270691
+Result = F (3 - S changed)
+
+Msg = 298a1286bf8f086ba726c57641d27f52f4ffc543b1f476043042bffdba33affb30ff3a8b678c657158d1842f76e8535d23ce5dc9692c02f5480731bf8903f981115a8b57c65f2cd4ab2b5a4e8bedba87ddc513eab1d9f86780a3fbfd837cf9ce5a007579560dfa1ecb279112feaa6ebb8a0798d14399629a1edc974e0965ca3f
+Qx = 05fb5499f2466bcb41a63db142d762c36ac806bea6e3c9fe02bbc9b6a611abe78e7b9f7f48c876ac624db6570c38162045e8e6a20f698068fc1da1d806a691328d13d1a050efca1
+Qy = 71d761d683203f871e2ea785be6c2087014ff74a52237b02497cd951c39cd72386beebae06a127a2dde320ed4d7bb1ae2f12fd161b2369145a4bd8bd82df13c49518065b5762a72
+R = 1188ee33a1516fa802dd6e24297d60fda394c7ff046c86924823eb547b36beee248a4440734459a326241408d32d29fd06b480b4497b722aa1906b184b82e08355b0060ce7f1c4a
+S = 1ce0bf85d76f732573507a6184249934684fb57ffb0711d74f216c60c81644d5da7c8940ccbb363a3004285c96d1f2d0b7b3604afd94e3b10f790f2a1f9b4e86ac76a039903a49c
+Result = P (0 )
+
+Msg = bc7fb14557cb3891951d93eb88a284fa5d78aafb46d559ed2881c495d627d2dfe3e7a8c801465e4267ca6f7a15311e186fb2e82aae5e691eff22a1d5202d1ad0d6d21e05ff4a918d3947628daa0dcfb1e4d6781eba259d0909003e7ef8c5df92773d7bd2d8b4e32dc5841e2aefb4b8bb093353bbeafc6815c71b3eb2f60f5fcd
+Qx = 49f71e39b9186e225e2699ef160a5df514be285b71b00e90fb8a5bb6fd5ce397343186a8233099a448f167ac55d635ef8ac2531ed8c06f8d66c4b44b899f9e0df387c92132bf0f7
+Qy = 4337529f501e9037f8b05d3a309b639afcf2d64c0ebf83e2b9e2cdcb6a3f3e4ec65526272828f33207b26d1fcdab51a3ca07d84d87447a712eb3b310303ea520e44e6a3ada36dee
+R = 055fd93bfd37b3a7086862df1fc653eeeab817942f80193e85c14f67a41dc5e2b3191af157fbeb32618cd431f431b0315a4a894fbab9f02c7d061b7d11e86af996a1fbecd7dddda
+S = 053cd1537214cc8652deca6f7b0730bdbdb84816021aaf16dae358e9d580653a57a98f82c46cbc5d556196f6a44e31688e5a18bdb102733778d8a0506f9d625a600bddacba582d3
+Result = F (1 - Message changed)
+
+Msg = 8a9540c6df089a6d4b2b5cc00fc9036a84a1f83321848d1dd0b7a69d0dee2bc619b7333a4b273f7c315271322982338d4ba09f951a692c964decf323ab251d7ceab327ed1dc56a45c8e0757bac8be5e0667352974153c96effa520b3eb0e3bac47b8fd67a5e0c20f723c6955d6bf4070ea24dc83252e96d3c6a4eee7e8e70fbd
+Qx = 5ccdd7e5bb9e678ba6a2c7c207f9e3f30de352bdca399e61504e972ec5bcf79f819c9ae7cec11d2a59143c5b6a3b262d407568ceaf350e81b4c15d2660913c3b095626021fb28ca
+Qy = 162826946b2dbc494d735833117047478fe78bc4217c4b3cdaf3edebf654bda4076e8b7aaf773faf67abd9d6023e63d291d92ab3e9d60bb0c3151cd98264b2dc79d70ee5c101b24
+R = 1142e950350d4f8fe208f5bbfe3f49a990349c2a1f2643fd15b400cb501b0164793af8218e33368541994d233ba5f02cdd94c0b02e7794ba13c397ba8976333e886108a812f15aa
+S = 0a2e62c64436f77c35c4c8bc662b369877a72e1b08133813c9e096555169c5a28da3ca1a054f860862cdc3f27ce7997bac59d99f7bd28166b3dc6d63261c4b1f203fe21e6a99b5a
+Result = F (4 - Q changed)
+
+Msg = 8f0ab2997b27fc795fd73af5971cc395b46364f735ff2a92afeb19a124f30273da8d2d848acfd548f365b6f13e239e74f49241ae6afa26aa3bd530351b6777da5a2b46071128adec65ab2b2b94e553c9fd3d9860753d35a49221b3b02e4794a8b5521c5ea17fdae2291928fc1fa8ac338d6029375ef5d611ee2c8e79e9dbffed
+Qx = 1b0aa79f7c5b46c65a5a0a0561c7edc9c48838f3d36e939a9c5885ff6f0dfc7f54fdafa152917728c291bd553522a03a677136853958a3010e1daa96ac047ceaa5c7cb428f74fc6
+Qy = 3c65a0e5b617bae456e5838a4c5368798ab0f3c7b4eb4a716bcc18b50372460143bd50e9287f3fa8aa7d16392d191e2776c7701d7692e217f75e1eb816ae7b676b88f7685613a50
+R = 19b2ed178d33512dd8ffd8ee4a9aad4e019d84aafc89aeac23771adbaacf3d4cd8fe548317a6099164d2d7bda327738f1ca1917342529ee99e97f2f344d373b8340a6c7544abab0
+S = 10f046162a60eadd5e9560485e5c8cabc87b0de87f5846fbdb22fa33052c61173cb94aab51119ec467fb3020c051846245c5a45b04f1d619f1e52a46bed1415f4746417f0605497
+Result = F (2 - R changed)
+
+Msg = 542c85f3351a79e4dd068dd82c5e463b7c8bef55095f341fca93fd29e9b11dc97556a515b4d2dccdb5b81c225e7bb884e72594002d3d75453261cddd387581766f9831a1d5ce5676ffafe595fe4436af095079cb9aa7b8e966574cc08627bdff277aa54d5540bc06bf9ded22cfb4024218400c4eebcfee57b89c7c5ea157491b
+Qx = 3f2eade801efec8ff500d62538b10a6ce0875aa4306652f50141eab355d9e26c7434dd2a426a3a3fdf1350dd32284a7c9ef54751441aa55c1e3f5fb8795e67be26554ae54035422
+Qy = 7f7877aed1bd14b70026384eadf8d559370e2d0777c1acd2e1f5505457dfbf059805c29d50a6f7fd53613a2677798e0f2f5a9a094b8f0e78bf517c5496811a2e910ecc11df9057b
+R = 05794f294272045b9b7ed93c8643434b1646a85bba0db90ea5e452dc7714e51ccb3571f6236bf4ca0cf3adfa2dadc49ebf08a342e0bf8105f593940c6cf09ecf3cee93c3d1b6ddd
+S = 07583000c324dd07122b0b71d424222de47c90ea90093b445961c16175b8863840c0b830f4f995d642d75dd8f01c870cb8c82dcd0b8ff56ce52e40ac66bfb3d708c077e5b7a5f31
+Result = P (0 )
+
+Msg = f823bb6c05ecf8af94c04b4dd827dc5ff1c2f4d3851c654893580227b72cf8468f4859e854bbc59d9b70c81f830b5df220ae3e807e550b10937fc99c1592b9f1866ce8213e37323d75e7da326e8f2fb8c7988fef496bdcf2ae2d9b2ed3d7da05a9252eba03d642c2a388b1e2422b63b220f26540a394f5f34fcc594a4b981855
+Qx = 6e9c75186cf5a151e34a2064fe758fd135b7ee85379ee0dc44da62e9a55402cc21216430345175a4e129b4401a5609ccaf095feb07726abbb881def109e027326b8a12310ecc789
+Qy = 05da8b654ca0c561d0a668e5bd1a26d27f641643d5bcbc0795af9cca47c608390909e0253380a441088b7ede8493b6ec3f01172b50afe71d172c375b18b95fb36cf98422c6abf4c
+R = 072d3034642ce93f3bc0ee9087b23dbbef0e4252ccac03a8703c9409b295ae8aed7f670cf2b4e7e9c210a831ceee6cdbe974dbfb37081468c4c4809346ff67afc82725396a8d36c
+S = 0bb34efef31d4ea845ebacdd7bcaa6803b473fa79c5f05244d713ff7723a89e8b85eab132faa746b397fdf9c20e9192b93799d7e3769c626e3f0eaef37eec26d8bb7776ea63b725
+Result = F (2 - R changed)
+
+Msg = 74f559f69162905905dd3a7e15ba118ff16ba96a7387f93991db04ec0d84f8344d4cdda08b504dd8c9f7f21d64e622d17c69bd474e62c51d415b0db55f921f032e39ef10a96748cbdf2defcf9c0b89e04ce593eead759f12c2ebd8df83ebeed09f4f6c20162c318ac84320232d8e94f7893788b4ddf39a0a500dcdc5777ab45b
+Qx = 44579c6625fb4d3d1ea84c3695187bdce7f9a0fe6b2202c202993061fe3e6025e7f13f1c5dc328c6017995e4b026a0bd819140b5eaadf59b38f7000255a37e935a4537e6f851186
+Qy = 254ee7b3de1078606327e7a1f22e4b51db26326553f725906923dd3bfa7a13c3aeb6d93ec02af8970f697f286564a330f6dea6c2729c510325ba3a437bcd6ac251da3e45a2268d3
+R = 074bfd1fabb735a66c5cd10166984f72a41f1c3386fa8d05ed35e4c7716398df1a2bdcde53830a679d4aa2be60345055869e503285386c02a3fd38d8aa0159307e1c798a2a29042
+S = 081a3fedb68e8868fc6949f544ea84b033ed9701670055c26828bfbb25b3809f0f97c8891f54b4e8b150ae29b2799dd127b235c3865a5d13488e5f38583efda93ff14907dc0151c
+Result = P (0 )
+
+Msg = fe67202261eb1fe6e6fc5d2c41773dd1c22b5c919bee2876600c692054abbcd566e5e2c645cf7d94c878cb1588b0f9743001f810e8ccc35fab0a449ad58784946456007c5065a5e37fb3c2b7af9ac0779a7c0c7904756ec561863782d0c509399f41632a06e0afeb9e0740a68c1d3dba336e935a895bbe668ccf826548d51923
+Qx = 5398f9d63b98b13a29754b7c4969ecfbe40648ace03747f4352e3466eb6c2c3e3f6f107ca33fcc92cabd606d97eab594720821bf2623e0fe1488aef3396f46bef79dbca845c89b0
+Qy = 31df242b0009a92d2bb84c176415c617cd593d6b2e26d14375fe5f4090d3b39d7b114dc093499f16bbc051e954db7109662cc868b6a110eec76af1eda5dfabd72f1c47c70a3cbd6
+R = 108813e42d4f419ab5770dce45511b2efccdb65f26b18629627b89c752b0d2f32b4264b1335afab6e15138f20e6e856064796588d3a115e085c41c5ccbfe49b449c1b8d59c5dff0
+S = 1242a636a61daa49beac63528f9ead119808ecd4b4cdc69f82b8391172af7cf3839c275380f49923f8c2976994d1de35ecf1949d3fcf280826f8bb64e1572356310b9bb150239a6
+Result = F (3 - S changed)
+
+Msg = 7b9ea5cc083e45fe0307c7c3d365cb17a2feca744428303fb17ce2420aa7cb406ea5f50a746bcfd0494e88e950f293f777012d8cfe710047b8b3e48783bfe723e4bc41ef7be2de4448ee2cccbd06ba983ea75d9f3e9414c5860ea2011b05b39f74f4b66edf399bc4cab7d4a94b6a5de275108de2d65357e08caee845abac6ec9
+Qx = 3e1a1554291852a4ebc7a698b93980a6e6fc943d09cfd43aa6e74ef896b028f9dfcc3670e69a362ca510729c5ea2337a7f82651b4a5eecd518420a465a1d587b4ae75b9e0a03333
+Qy = 5312712f63b6107d3220503221b4d9d1b8a77e096a54ce89004b3b086a3de41f15c41f05f6bc7ce06de8eb23183638be30d2e0e6ae7ca222f4fd116fe1ca5c6168d04ae3ef08979
+R = 06a77db2e3f7cbc831c214a8e88d2b2ad1f5ee8c22c5bb51ed7bd47624b4ceb4bd8fb82795dffb116302a51a066e1c0683166281e65a20cab8d25720797350d1bd2668365a8e4fe
+S = 02bf59ae01e7e693d55c314e909e810769a11c08b17b1077b4c25221fabfbccb32a8f5e522f8210d5799c1a5d110cba8d95e99a30c707181fd9232ba600575aae9af2c76577abc8
+Result = F (2 - R changed)
+
+Msg = 918b744bd595729ba14a54b03b897a3341e4f67e701fcd17f58480c3477afa41cb99f1081a66cc8d0c1e59575d97a5e8279c1ce8a5dc1bdf1512ea7d6f3431307bfec9651c95729d922f46f42cbd6d0dbe7bb96b2a187e204ec5d32ea50d9b16c973f637f76b4ac94a4505675420f0ab9c227130595bf74c57a1cc84cbb6b6dd
+Qx = 53ae552f4c4e9e118f42bb67aa855b5a3403f422e215b3735cebda3036a73a35d4e99121f8982f8d586dff5b96a0a6553ddd4cc40f85584141ffe5546c7c5733f3a0f10e0a46311
+Qy = 0b18724a45f1a1cde683e1d9dd7a9984a537b9cdde593ec975220821e4ef19c0817d1c7f3d8b9e399ea0cf2267083ce63ef55edc3d86f43e29bd791475dcfd0924acf2c90bf6c28
+R = 19b0628fefc0f085c40b5ac00ab7ccf46298e57b7c0bfdc40c79c72b23b814b6a095df1827a5c4b29c443ba44d92b12330116e024229914de218c7c0ecbc46f9d2cb2aebd70ee55
+S = 1807fdb0b1bd0ebb502b425de82363945d91e743ff19d3a4c4ecdbb6ad4209e35109ef5e5c95cd1d6da30f8fddb5d88bfbf375056bff3c81cf1bb5b014606cf5c18de9554d46192
+Result = F (4 - Q changed)
+
+[K-571,SHA-512]
+
+Msg = 9f8837c3cd79cf6560ba58d2976dfa5821b1241c4f5010dc51bcc779d2b1c3914544de60125c73492c0b1093a3addb6d008433b95c91fb28497658421cb226b4942e95dcbfb858964d978fa074e940a7d4757844e167c051773977f397b0ec421efa2e8eb4cf583573a41365a9add334dfcb89a2719eb43dc3f030f19e62772a
+Qx = 6264f9fa45f65beb6a5da6eabffc3669197c8361936cdfaf5df1bd17b13912eeaa8bbdb183ab157cadf23a834fd961eec71f9bef0e427fcfcaceaa38ea513a75bb9103e069c98b6
+Qy = 1d5d56ec96891327bc220282ff97b3f178d3d3e79f2efb934c589f096edbf78fdfb0b1a4b1e1ef24f7660ae84a4c2fe11842f2a6f6c5061f34058ced96ef122247283a36b5f624b
+R = 11dd8d39f35f7bdc3c0b2750966f77c0ec275985f9a0a803c8c82d9e281b7bc41cce0446f3b10f55b076453a1758b78485f175c9a31e87986186a583763a77716fd7672cdee329c
+S = 1fb18599f3cae969a34bbe2488437eba02112fb19f99fc2303c26b123ca2c7ebe56885ec33b7cd299ced022a3023cf38a5987a9833df799c0ee5ea44d717ca14e75c79567aa4b6b
+Result = F (3 - S changed)
+
+Msg = 650215ea6ca332ecec2681c630f44bc096ea2e7331bfb0afa2d5cedaa9a9185a3e4e33f5fbfabd53e34791c6118ea917b7f3f84ac6b46976179438f59fc48665d3d4ea4e42412b70be7b171dd25d5bb52dd0e360125d44a460d23ec05896bfa2eadefaf10e765ed1bd0fda982061028d6dad54b6a0439d7a64c90a500ce94497
+Qx = 49c4523d6bc85692198ed75a9c8d50ffb9621930ea7c8db9cc219db602bfb87b543e26401a802c3c07165341eacee2bffd62bcfe9ccd2b6fd402245e0b43ceef84116eb943bbb54
+Qy = 6242ced250f763680c232bc7c890fc04f21805357202786802a6c665df525d6c7acd07daf85e9a59567a069ff418dc23c61fc36b0215ff7fd09de1d955a7d2fd5941f35d85fc1a6
+R = 072468e0297af88caa29adf98896b2e47933e0c7de5b8d59682d335015d58bf922f163499a0ecc8fc9e57118ac49c82e0e441ec117b6f06d1902f40e5fcb1a264dd718d3d3a4105
+S = 03bb1d4ae149464362942e9232c36eaac2229f27b90575d505eb4d74cc764de7975b50cf082da3c98f9d4a6efad0c72a07cce492bc7ddbf6bbd0ae1939d62ae947c60c3cd5cd0ba
+Result = F (4 - Q changed)
+
+Msg = 7eede0cfe07fcb63ffe755e6850f51bcac8bb021b6cca4d0f74e2bb94f6e25db03dc9caf1000c12bc1c9a58cbfa6b3f3a2715682d9de53a0c2688deff0402a684cda5801281afb9519b002bdc26bfadb1a676ccad338d2e94a331c8bc61bf642b3f42e09adc3cf6c9fc8cee32c3bc9df5fa4efbc95d2aae043b5c532eed91993
+Qx = 58a268f8f6acbf1e6eaf768b41fea5f3fe1de955d217b38aa0a0d177f38fb5555959dfda2c4a5a07017c630a63f1f12b932b49b3f4c63b88df940cc0057be9f751574d411a75911
+Qy = 685aa85a9acca6202ea39a4ac707e7c71a7d68654aa66877f59d201e027c05c798783a3d249ff7ce5e4ce702f62f83e5d0e211fd549f9e9547175d072a4c69f1f7e6f2fee79a03d
+R = 156de73d8f47245ff8a48f8a6ea83304e103a95a04b685a9970e13b8e1da8aa4f014fae3779364f9d48509ecc084d8e92b4539296e2fb648519ef517a06fb44cef98aac27336b49
+S = 038c43641aa56f02d511ad64fdf64f18622380ef0d23cb2fcd58e80c8d29e3511764ecde6bcf837f4f51b55a261b5525420602dd00b12c313357b7f88a7d5e0adc3b63cc3543fba
+Result = P (0 )
+
+Msg = 9d3cfc9bb655ade2053a01e18e4b09ea7efc70f4826c3aba47d89d10dd1f87624fd37d3dd72dd8f44b9aa590123bf5a8b0919b8db79e0a6ef29ec76d72b83804db87dcf371a15caa2687e5ec638602623735b575e0e2694625a4523f185c6ead2c9c2c6c9af91656239e11e9e3a67b54ce87062b62a14c4a42dd9eb38dc431ec
+Qx = 4a40715ac2607c7990ca2c5955068550fb6763672ac357bbf6607db4a9482228a00d9e5102fc16dffd1169182a95136db51738733032d645b88d484e9ca6d3943955e3108ab889c
+Qy = 06dc468d96902bbd40343f97f9fa06b0fe522a5f02bf6aa209034e4526f3d6acf52c3adad16cf0c19244699c4d9a13ad9198167b51ab7e52803fc467be78ae9e33247125c61a791
+R = 0b63aa01eb8d319cab96807870e31bd6844137472b6fd37eddd22834f6dd50dd36f98e0db573560696e49d307758d1cb650af00434680dc03195dbfa037f6896789df391bb47651
+S = 09f6be893285e402fb52d7ef861386f05f8756b03982e06ed55577f2f42fe412442c2ac50a2560fead9bf6af1d9a3c9a312f6c7cd339e4a1eb2348ef32e866d712ca8e402760133
+Result = F (1 - Message changed)
+
+Msg = cc0e30bac67568edda2f6ed2dbbbeb2b03770474710a8db2694603a41053204c26c0e7d728a0bc80564e8d3738fd25967348807204892f41fe36bdf68b886ed43413f4a603f5964595235c62c24462a219efcad7624bbd8bd87717239ce3e4fb1b631dc0abbf858423573aa8f14453c8ea9d280558a9933dca94d96b917c8d61
+Qx = 3a9a23f439980ac6b73b62195584dff7cc164d7b596992eab1c1f5ad8923bb2f68fdb28e613ea88423503e32ca2b082396872084941c3282ec8a0029118dc830819c863930b5ce7
+Qy = 3912e88af1210012695457ccb1a14463ede520336f7d5f36bb1046e7ec5699698937826cbbeff8e0696a4a21a70797ec5cafde8220b3ea858fc75fd617369bdb29335032f5f0e6f
+R = 14b15f0c881f3f4e2b70230327a4dfdeded3c3046143a5480eb390e80a6ad0bcc0cbb148d6e202bd7f82f4b68ab4172a6b86c6d8c9baee2f701ddf2ba484c4bc0348b8ce71b209e
+S = 119fd2bbcd86354c03ab2aaabeedd63637bfa8790bd75deff14699bb2accc39a11ca92c1c7d98a7b6d438c3295ad6baf900632aae2e228ab983080da729fc2ee2f591cd0339cd7a
+Result = F (2 - R changed)
+
+Msg = 66b09923fa0f544de8bec9be1f41d4ed8fca1fbeb949798129a412e40be9aa9fdc51fa971280aeabd38cb238dd4f5df829a9666181cfac35c94b9e557e4c55a2d974e7999f79c91958d60e3a08821982e22d622b5f4e11f62965ec0425a006e8f3aceca8c518e56e5013eeafe9aa43f9e87bdb809eb92db1e9fb138103521050
+Qx = 24f18f3d60f4ea5dc7f8e12f280a886a586117ee299bde40ab53787fdf7e0190dc4e68f23db3964f8b584b879f66a8a03e99ebf203b2c1a2ab6e7f2a17bc4c48d86424f4d1176a8
+Qy = 368abfa7a40007b24a64b7150960a782e1c609a1d645c0314008a349e6c79bb6961923f09d755ed97bf032b9a32e451558ac9b46c96b8db9b371dcf3f92c86dba434c1e9b7a5895
+R = 179790c89b7f96ad125fd7aca27fa2f168ae962244a2414a88e1f40f5ccd70593a36b1514e67e0959881d66a2fc7e151aefbeebd2a8ebe60490203ab447412d0125c1cb47b90d02
+S = 03d9570da5ce18b797c0153e42ba42c5b6267b47c7a5f09a36b2724e7206327fcdf6189061792b0b49dc8611473514ad19f5329689e1a4da43230ff070a8747760d110fc9c2732e
+Result = F (4 - Q changed)
+
+Msg = 4d405c2322864b350283661c24b74a8360da1a0408372adc62da16c816ce04df3edbd7fb68d3fa122e6ccb2209d12268f90181971badae3d87b43545699ff9fd9cca9e2a6dae1e00d1f3e398f5aef7ffdc0a9ea6d46c4b5ea49670e3b3c833fd0910d5d050816b117d65938bf6b4de949d14d1bace9bdb4b33d13e976ff9961a
+Qx = 418deb9b835a6c9bdac09035b4bddfa4bcc5ad359a75ac31368760d03baef30ccdc663f2c71ba2e84021042d53474d8b0aebb7845a226b18f89cc174d6fe30cf42a51ae1a5cedd4
+Qy = 4d8bec4147321e65558e350f32a93745fe956aa911807b6948e4641356c27c60f196891fb228a991d246771da297f07d9aa39689ac23eb2239f5d8510ca03044553726b1ec5dcaf
+R = 0908db10d084dd29e34435c7c5670dcd457a6b22bf6023c625e12889ab40fa2727a7a14eae06773806f785623728dadbf944ef2a5bceab92e36760563e6e97f2bbbf2e39020dc92
+S = 0b836d3c2cb3578f6f861772e9a3dfe3a0b9612836d9947aa270972bc1c25b166d357b2e82597aa96d8f8e8809467376b2e051cbe74a50088798a89a46ca39342fe12377a5e9638
+Result = F (1 - Message changed)
+
+Msg = 6b7341dfeef015038e5b0da24fa9236149a378fe9d78a6f0d94051c24341755e441c04cdbab15ebfb491a9ad814e7778606b17c4da40c202adc86c35b525ce30cfb160b68ad9fae5e990419dcc2aeb3742d4503d7251926400a310c763cb783a58c9285ba46f50a18bb919c2144a3e1f0f11609aa4d21f9237846ea4bfedbd04
+Qx = 197e499b984e90c899916c4137a3e953834d8b02c8199e80debac857afec69e693a496d516dc054aade700379f98cead1d6122d26f84e9a0e3049d13b7f543caf76b3bea401c1cf
+Qy = 4fd01b0aa758deabb0c6a8c94c6062df0f5af87c12cc4d9791737bbd2dade8f1edf3570232047ef059296685c9e92c14439e78434cd9cd1007adb4af7072abeba3ba2a1a1564b5f
+R = 11cdda397cc101d04e01bb7f30afc0d0bd5a1182bde9c697747c350579f7a1bf9ce55b3bab1a79ce567bb4fc88623a1fc59f5e42210a55a4388f31a87ff6b9b52e7c9d306baf923
+S = 0cd35ef24e6aae750c867b954df759ffee0acd5477b9ce8b65aff5698d261a59d05e852fe5decd524caa2130a26ab7ce45cd48ac9df5f8cfefa12e11b0410dbfdfeb0f0a3517690
+Result = F (2 - R changed)
+
+Msg = d6c03d0224cd6ee69c625134aa342d5dcb483ab3ad5bde4a2a808f1b34ea363df41cd2809c49cd0b461779cd795310376e3f74f63a6fb5767f5e7e45e6dd5ecb653ecdcab3b863df4c2268ced5fd63b096d0cf6ed1ea884be62f9218bbdff5f7d3e2c25f3234612c60f0cf3aed69006496c7383004c74113e0b8fc6d51417aa4
+Qx = 144cad226ccea7038c30695780d66b88fceae45b2eca249b29c8da827e2f70b44be47d6faa9fc6641f4c822e0c17a04b648594c3fab485d7d2fcff73b34af7ea02d7fa809eb6ca6
+Qy = 5ea5b58630f798ab76d3c73a6d5bd9b99a57d06c167889da83027032b855ac63a6b3d9921fedd2f65a52d804554123effc885a986b3644c044bc1763a4b59a2ccb24951cc6367cd
+R = 00406b6a388144ff058363d792e27cc710ab76586e83abe1d8369c0a487346d39bb1dda42e4f1b94b3619a5a72b0753b529226277c5357280336ddeb04808a07d293184be500108
+S = 1b49b422c0cc37e99b13260c7a704d9c810a45623c16d95c791a906594e28cce110cad644a10d4048c4539803e714dcb8f54570736d67a659f9f8eb43d7c1ac2ec3f1d486d8d7d9
+Result = F (4 - Q changed)
+
+Msg = 4966108e23e98119225898d2fd23f2754b0a5ddf9ef91d9bd42a561e53310f14b28a6becb06f6b1ebb29d6bf7d39ed876f7f39524c3cb6f1655a5a2f9cf7dca3a2ae5dba08f0843f138b423af769d8c36967e408e6707ebf46a0c2d97d0bb3689dbbf76de78cefde7dcf6bd2f48c752fe888ac99b43be26a60b762536da306c5
+Qx = 757ca451a17a1a2646b25d5664a84615f0a5e0938690d5e47c10344ea07fffac390a18d6357098c31e85e88278e70a88d87b2f442a89491bd0637d2ca14aae6058154749b6ca976
+Qy = 7744cda5483c13fdc4dea3135b1d91731a261e678483c4ccf1cb167c4f6c5f2bcc8669b8f10471286e201f1d8e06c2ebf2cf88815e57bda8f4a10836456ab68cd039f68fa00c431
+R = 15e05857457c692c5088be8a7e821595ab82e85fef5791ff4f9a5a88bc54c2d05bea6def12c9372e2af871c2add0b5f34f5d90dfd3e042aaac0656bb2c01ac4ac8e555f8d5a6061
+S = 089ab7743636a397c878dd167c46739150d87e1054a81d402c952dac6400af04b92c2494483eefc7e7cf480c6ed24765cc0046f178f9f31cccfbd00d57740c3ee1e0df083d3cc01
+Result = P (0 )
+
+Msg = bfb302063a4def88552c75881998ff6d2f471567d077ba192a9626bf726147f9dbb8186cd97a7a957cf721a00f618ec81bd18e439b76459c8a471e72aadeedcffd570c6c217e86a8da92885e88bbcc255319eee2b1e30dffea1ea63de4302ca4171d65a857744f35b3414e5ca747dc9ebd933cea9f81d39118bda8d1857f00d9
+Qx = 086e881b51fdc7f7ebee15570095aa5e35f608a3d1673ed1a6b7cfab08b35e975526a1d3a236b39038d7c87a9d2f3cf4f75752f31ce6f7b99cb79d089f1f6093978eb5a18198c33
+Qy = 55a1867b795d67dbc2289b79f39318a0946cce3244db6cf7c7c3c843c92468df65b0b0230736499c231362af72c141df08c58be03c66dc043ae964280f4f4b1e712a2c311d36053
+R = 1b9e83d39d09214482b412d4c88246add95ef1278bb9de1cc5455aa123a5d72f5aa2b57b288608f6b5f9802fa93ced4eadada493b2078d3b1f381b200d3bbd9c93316a2aac177b0
+S = 06693203b314f4d3a85204c45ca6642c1bc79d96ec2fd1ab5aba237afb2a26c820c7e6bbcbe0edf7de8e7c2039f367d7b9ed41c636b6842060c3633e180907a47e665be4876ab32
+Result = F (1 - Message changed)
+
+Msg = f9dbca02104460bfa337fa27c8892c95b5c6b429a33961e2c0971ff94676ed0f62f6b0e463a0a0ef89eede3be3a6a91983e075b049d4e34d9b359ee42e20f20cdb6fbffdad9ed9fc85c950273e0244f7c731538dd3896e2315eb85b467bb71900e323c3d08c34bc107371962c104d8fb5fa440bf85d9b938ab1b5914fb712352
+Qx = 3ee3d98aaf90f758bd7e1a9a5a4285f31365e93118770591957e30c91f882d024fe2405c83115003d3013ec8f58dca5bef0d3c77081d3950be54da9816afa2cf2127ed72708c6cc
+Qy = 2a04b8809bad265e644f1e344fd2c5b4d9bd41a5229e2cc6c23eead68406adea8d9903b4a6116b525316be78dd2eee308c859126e61159c53d6cd0b81e463769d19db15539c507b
+R = 0070553e2b3438cd8923f11cf6791203a6d61667ff1cdeac9d89c755125ee76f3521f8a9343283c51dcc3b2bca5bc9a5ec6c512c117ac24fad978a0bb720a73644ec72fc7eb2805
+S = 183c7aa16b8dc196619f8d26b0f5466b1f608112b16b7770a10effc06882a936f7e3c8b30c9e54be50e859c712be3d0beb338eb28a1590c12836ab2ae8331612d0cddcd7d0efc50
+Result = F (3 - S changed)
+
+Msg = 60d62e648bea0827e8b942be0f7f7467ed5ccb5a2b88d9e4a64907da6b691e7cba647167dc90b1845c55019c2e4dfe1a1c2afabe451394e15b63f9e4b050ffa2fc979a599c789b1a39bd62736ad2137e3be553c62c17e894405cf2bb83e544eba7761f3e8a646b80eb2ea01a681e5def1cec2820fb75c755660258dac20d8751
+Qx = 6ed08c85de4bc403a55b89c4c8f4c5fa6deedef481e57f3fa45bdcf44127216ffdb1ca131f6031053ed381d7914547c6f5275d6b6f98862dbc572cb67e377f9184b82ac2f8c772b
+Qy = 0804964839a2c33c1bb28777814aebc4a9f7aad3a79b64e6b92daac5e7ef042cbaed7fc7e4316066064293d039fcb18b24c5967d44b9067a22630b6b5bb2392fbcadee8f3667f7c
+R = 02c6eca73b4618f51713c9d050c67927baa66338f6ee731710d2c1025a76bdf13e4b476dda22b77a027ddf71a00b582dd84266b078ed9877325ee86aebd71b1d774e5df6391c876
+S = 166f4b228d1c7b6386dfb68fc58c80dc1afa4069e5883dd90923af493988972b54b8cea50918e3a24067eee8e364f2efd626b871d48d5f9358983f724e68f709859fdb24a223819
+Result = F (3 - S changed)
+
+Msg = 3f57d1209b18b0ca7e292cf294dbc54171da17364e86bd1b06f31c288472105c5e2f26052926962ce2e889b3b4e9887800a0fdba01d443523562f0e053da81a9688fab6260b4e2bd1258f764710383b1cd6d271451125a82c6499abce89334ea03293ab757056d9d1f1df811e538dde99f17798daabdb622184e2df3df604e80
+Qx = 5a53b989f65db734f87789b6727998d5d1cb5ad7a04d8b5e72aaf13b08fb6977bcfcba534e0db330793c73e4d4594b635e8a60754cab7b442009de08a2925c459422a91335575b0
+Qy = 2b789f866b90668a024606978200c3ffee152d41c6b51bb6594924bffbfb7681b0e6f821f59fc4dab55bbe1b19c535e25f36cd5b360862d785f4ae0802614c342c2910a9dc27720
+R = 0fdc2e4bc89d842bfb207ac21753aa3ae65e9144ae1db8fa2ae96964be15f4ddf4df3e6c34ac4caf56cd441fa7e806bb3ab3af539b401ca7cf1ea743f80ea6f1806971c20924a48
+S = 1ffb3214354b87da861a1367837ac908c73b3da317a9ad304aa627663aa77effa43761163898768978b88c15b67debffd5f1186089940e7962591ce144a51baa4bc2ab63a27ae11
+Result = P (0 )
+
+Msg = 5f20e5e6efdda404db6cbd40297580806d8cfd334cde6b7d967421db79d4400827f824da89c9a35fb2d84334afdfe8a42efc175fd529855a5213794ef9a4fe2738fd9f5f13f94a25961e113dd30077b4a00b2a926d121775a424ab163c0d18970ec0464a2462d2229d03a1d1208d1496424ed295edfb8fb63f4ea2219e9333fd
+Qx = 41c5fbf3e3893e074f8278a1ef806ebbe8bc7bba7d6996cdfe091d1e0c5a0f634ffa75ae1ca850e980b065b02ca1687c7c6ed5fe93bdc163e4dba449b3242a06f52de10093cac4c
+Qy = 0b4e3d2f9cd75d975de2daf35adba83689b6bad53b40a774f6945984c141e539593cda46219aa256b0c33b1dbead24dfb26c88d1b209081b121516ca7cf0168b700f667a60ab4f4
+R = 13a0618ad2072fcace54926c778355bf0537670f094a491bc6c75bb9acab7c1f6c6177c8459897128b91e759db5a00068b6dfdc908a39ff01b31ee206ea4018cd1f31d7a7583f60
+S = 1cd09a35124f6d4fda407d9067578511522db5496a1f728250f2f58605484ffc123c476d57eaddedcf6e27c147cece6c602362f2bac28c90232436f273d2781a6a803a23eb11aa2
+Result = F (2 - R changed)
+
+[B-163,SHA-1]
+
+Msg = 72bb3d1b6c484b7fa901e494a6ac2529e0f5b62c6d95c7d07396fe7cb6af1205bfbed936a73a2c48c49e797582b03ee16d8309e41df6a394087685214f06453d9a58cd1e5364eb739e07222922c7ffb1f308ccb5124c2a0bcd3dd19a449f5b6a19ce33e1dc7629fe2fc954fa4c8f502ea2e2e762a119668c770a4a08323724e6
+Qx = 5eec9ae860e02bfdd99b738850aa416bacf3d6aaa
+Qy = 0ab40e936a121092ff66037474d35dca05c7a8982
+R = 2baa523c6cda5ca114027db1ca943879aaabdbcd5
+S = 1048653729a5f6f990c29a1d78a5d29fb40c7ef53
+Result = F (1 - Message changed)
+
+Msg = b4ebd1bf667784588dfea5e71e8935ce83b71de479304d99c71ee0efa054d520cb39904dc4995fd901d6abe69cee1493bb306c442651ca96e22d485471342196952771a953984d44fa3c912071b7363a361e0de4068d7142f8285a9b1fbb1a26cebc05acc6dfb447ab1f084d73260459a362396c7e2e0ed3a51ddd043d64db4d
+Qx = 1cac1ca426fad2038ebc042227ab21f414ca95aa1
+Qy = 5801d025ae9bff93390d06f6f2be43e0e81288946
+R = 019e12ee51bab5ebc96f63a755be30d076abb9a16
+S = 36c5b44bcff98064c2239f64ccddaea8089c488de
+Result = F (4 - Q changed)
+
+Msg = 6323a6f76ada9be61e6e78e2134ecc1dcf39b84eb863ba8379740a1d753b1617713a46d9a57b91161677365b46e3d7b6cfc463818dd3df705f49eb1b422e7b2fdc192012633160f7ba192b779bf081e9588a42acba449af297f78d0adf4619643c7e7c9b8f9de9b0c9c929f9c6c79176b9c3fe2c715e43219bb1ba5e9b8a1682
+Qx = 60657087e87924a204a8ceac89c8ed16372aa712d
+Qy = 4f30aba97437fcb17194a43a6101006388133b4bc
+R = 20ecdc8c53e992619d94b515a97968c8bd63011de
+S = 08d397f221821e48e75a21a233e0c0813a16d93ff
+Result = F (2 - R changed)
+
+Msg = 4d87fe7ad7c677a00e6b2c995a1f41dd09e038369b278245b80e826e155d537291d2cf9c0966082159fb920c72f50da6d5ab5396e5af55901cc692816c780bdac05cee5871fd0a072f17fa0d86658f7700d036eb711b5143912586c642dc5c3ec3ba258898ddedc63aea0e4746d301d056d036cfb6fe5ad079fbc7e1cb620f3a
+Qx = 70b44f783dd3924d7c285463b5536ee166f466ac3
+Qy = 76b58416582720c751fab857fc13e06cc106ec9de
+R = 22a6bea700d49ce485a43d843d7462cd632b81717
+S = 052c7fe1c21052d67fa52cd8bc63a22b0c2e553b6
+Result = F (1 - Message changed)
+
+Msg = ec14c2d17fcaaa1ed256e883bd0359c2d44a82d8e1ecdaf2cb434f9118d6f3fb6ce376012f9086747928b3956eff4228abab43ba6d17c1a5b88596b47edcd1d6792781c3f9c6e216aa29611260cf9b985c3fbfbdd9c6d2af8239d36af416877a01d54476c947ed708c605b7d525774145f3d6946d87adb2c5e4595ee5714c999
+Qx = 6665cbc7a66c4028e76addf47f66e5675a0dcec24
+Qy = 01e5674afac10b235d0130b7e3434ffebc3ed3ca9
+R = 013f9fdfbe434a144fc3cb8d4766a74a1bf248037
+S = 29e5f8dcf3e94f9330f3655c8759bc56fec2ccedb
+Result = F (3 - S changed)
+
+Msg = b72f09158e501ba42d48d3726f291aa3f404c2270d2d0109dac5f3f61f5338b5d9f568807e7121880cf70740e9af881354edc82fbe536c0ed14d17da5b28c46200284747b94d4d5db2e6f1f62eb8f26686b1ce763490938d4917676e13e8a5476c7b73bbc7520aa786dcca34958c713459f9504047f82bbdea0fa3bd75d89803
+Qx = 5849076055f51bd1656fbce3fde65e6cbf3fdef95
+Qy = 51a818ffe587e25182136ec797443be027cbbc48a
+R = 190a2a051c398a7b614913e3d4bb019c6122d0f45
+S = 21548ac35e0c147d3ade61cfeb59492f5df320d98
+Result = F (4 - Q changed)
+
+Msg = 6d5ac5588da26e16857e603721712af97bbcdf0bee6c31acaa221f8a21911d02eda02bdc4ce45fc7b890ede3a2b0e8e7c1dd672c9783ca8a32f1ac026a71b9540bbd418fbd413365ba953ec3beae59738d7564abf9768c34587fa38978bcf54e8b840075f37433a62c4f36c484c660c3a7983625cbaff1afa210536dfe6d3e3b
+Qx = 6cc96d6f6f6c627815ef00b5257e7be771bd70f3b
+Qy = 1579ee23de4e414968688c5dd0f1fae24ad5d9486
+R = 3ba3b2bd63bcf4587f2da902549d4c3232c5c04ec
+S = 2033627edebca4b50ce7fcc601454bdbbb2d4301e
+Result = F (3 - S changed)
+
+Msg = 21511fdf6eb605dc495540c6a255c089c41029f2793ff501c215efd266dedfa3c94931c8773b4c3bd453f56f933f2ee04371ddc6a560fac8a4731f4f84af630960a5bb2cf3df99d5dfc9f51cb270d43e15d2a4ea6e56696a74ad6cf494b814fcd56e5bc53cea5f2fdc9b2a6758a6727627ac856c8b697cff4af9251687a40917
+Qx = 67a8dbfb975727acc97f0b6ee69871a6fb502aae6
+Qy = 773f3453492fa0079757ce3ced6d19a62770c0ea9
+R = 1573ad2152ffbed8d732837cfa22d969e1197b184
+S = 0b7cad7fd59cc9ef8b663b9d3eb5a0ff51a85b50a
+Result = F (2 - R changed)
+
+Msg = 619df18ed82b8aec682508bda14d71cb4926ac8878a7ab694d4249163d3202668ea918480a94eaefdc918c556a0d61ff9cfa6bcbf73113271b3b8fc75146749e7245ab9c1e21cc02dd39c77bf73c5fc57f1115f660b158089fcbb323637ea9429cef9b6171325a5d081788bf67a505c01a081a7c6d881ed848317232a61474fe
+Qx = 34aa4dda692c6ad9347d60755546e3a1aa9ab3279
+Qy = 537ca8c5cbabec8ed83668436fdcc5ab43937756d
+R = 1f3ec6cf9761fb8ea00474337ee4b19c3fd2a3bdc
+S = 0d3a5486b189df1d86cd5e22c7e090fac71d6ca1e
+Result = F (3 - S changed)
+
+Msg = e0bdb69ac2a7280021dd21574d5b0eccb9c685dc3179c33801a07b7e7350396e0652c7ee5a9a9a98a61fd3cfad418d9baa138d6373b8775dec4a39125d68cad5029bada2a780b74e59632a88678b1bf3001900146542ae06b9b4e2248a76d3b60c9f00c465840116a0e9a1adb09b84480989b94e565e45ff3e24af80d1dae7c1
+Qx = 5a34d80836fc9e6c9f0836d0a1a9f4d5df4ddd4f8
+Qy = 214281701f0934592fa1db180e632079ecea7ef69
+R = 26fd2a40521ea6b9d44ef0f8567bb3a05ffd3c9ab
+S = 1f4a865880b3852c6f4fca1ad5eb475b991ffdb92
+Result = F (2 - R changed)
+
+Msg = cf595acef2afc0dcb73729a99485611e553625bb6f95111241df2e05a694365d35005ceb7a27e6ca58817c6ff94872b6c0c1cbce121d37d8a01a468787e6337d9402f935b68b70835df8a5d72de847d7c37e62a282095002d3bb8e03866b7fa81d00202c7a60e1604943b3947bd6b60c1a44c71897bed9bf07ac448d30469346
+Qx = 524dbd975aa32058697369ee4bf7d4235d3119bca
+Qy = 2ef5b1dc73c3b4fe92d9df5d1350c4f00b60a7f84
+R = 2a97d1c5e39c96d027b62306c0b9ecdc6d0005b49
+S = 1ac3d253190ad17f3981ecc34cf4dd04d9444f1c6
+Result = P (0 )
+
+Msg = e6e3a774d2bd64ce9ef2f114259335f99f80765d8ae47de18eb4bcfc3241b2c78d2bb2c3a8954ff4959a3dbb9d6f39b1c82836991e005d21d39a4dedd8ab0da26e4db8cef26305873570ee3ed8ef67bb4f017573b58947f9c0c6b777d6b03a9b17c0067dc0cb9351e09db3de3746a2b0a2804ad9dd0a35f8e2383a81a2c7deed
+Qx = 4d6553672ea655b5cdf8f4102a56a4bd5cb9fcb67
+Qy = 707e1a944f0bdde34d270561065e1986718e49473
+R = 300940d55f78cb4092da2d7106c1fa41f375dc467
+S = 11e5046f7bb75eb60f0ed163ae3f5b470d6f4ff25
+Result = F (1 - Message changed)
+
+Msg = 5f8a328003fb66a42280ccfd95e979c27cb8e273b9b88374786335f2193cc17657c8e91d17cf550ae412850568b24c6296bef7ea0bac4bd369b24a59d7b5db6621b95be1532fd2cf78962f77c1250128e44d38b773ac47ba354da2db258491c65bb3575ed6cadd62c6c0a23b3e94ea47fdf9dbabbdc225fb97b61a0b43916340
+Qx = 4c17763b41b908d5996b2ca81948e8ad0ce1a9b07
+Qy = 623eb1eb594618fd2b8bdfc634c0d6a6178d42f95
+R = 19430563f1d4f9cb15a69a518982bac9a33615406
+S = 153b8d92893fdf3d5464fc5f809759be68a559efe
+Result = F (4 - Q changed)
+
+Msg = 1309fafcf634cbc1630bd4dd017ffddbbc9e83ece114ce0cbe4ad0115fb52502cb7eee6bb77ebc0c8fadf7ed5043281c1ed667da240592a00c1296c0d3f27e7e277797f47f9bb82ab02dfa8f26ea4561235c4901b44cd153071d91026f93fd6b19c9db7e3f144421be5a125661ba9e86591a998062129ca627ce9a5af0ecd6fe
+Qx = 081caf4d56975505b0ae50c9f398d79aaef3a8177
+Qy = 2516f2244945af77e4ae4b3bcde6f3bb7a22d26c1
+R = 1fc0fd53cb1ae2abbe7cf5bd309e9789bfced2001
+S = 10e4b562df87af3c0b0e2b157497666572c6bf9d9
+Result = P (0 )
+
+Msg = ce34fea8bce6a06ce1a0363813c01536e3879c406781bb26f044c6a3c31f7c18594287293a64e999218b1c8cf28a75da8e5013ea29befb7a814332454fcf2e3c60ec42f8a9f852bb1af00fa109790e5067c0e2fd27b3be44540f8233386e8a8c2b07293b5deee103561ba8b4198bdd51543312f040d40f4049c16f74939963e3
+Qx = 6aeb6b49c6a4a7a6b43d72cec614ae5cd026ed302
+Qy = 7cf6c8bb20d3a16ba5e59a736588d6c34667a337f
+R = 0dc41b52acc2cf13513014c6752aa888f69aeb399
+S = 1c526c6fc1a77e2d739829e2be3745f43dfd9a66d
+Result = P (0 )
+
+[B-163,SHA-224]
+
+Msg = acf027d3c1311a4c8ea3299ae6020e609935b7ef88bb773556e9ab87138dccc32f481d6e5e81506b7ac7e8e07b72539139c168485c97b657d40f0505a105107cf6d4de486bddc6b6b83e994daa1697092761c129b4c6bb1833576463749c038beaa59c07b0b1ee70c3b5876643cc03cb6223c87fe813db8d207c4ac6498a2e3b
+Qx = 6fe8047f2dc25759b67d5b236916912da9cd67b6e
+Qy = 4863f665b6b53adf53217abefa61afb9a8a256a6d
+R = 06175c7394168abf588b710f6a06d8075a08c2d48
+S = 1200a7e035c35760fb859e757eb7d460852407f8e
+Result = F (1 - Message changed)
+
+Msg = 8aafa4f2af53d60d020a65a67c4ed8590eb1d8b254c130bf3532fed269c4d613c01ee3024db3ce229c5e4981ff74fba890cc8c375d41b2d5e3c09aea63b554b0f9c0281b38798b3545c148bb219309a85c6be5e5577f69a4b8e4bb2216722ef7485d9addd9aaa51e02d0d62f593971467e7a44f680584213d2cd4b041d9d196f
+Qx = 585e1c1e4c7e15822870d1c244dd6aa34db541765
+Qy = 1f1b25e8ab7b47d5bdcf697dbb231458bc9dfd7c3
+R = 1b456c42970d38c8958929556b14623092dcb0960
+S = 03f93e8a1224f5f389094447fccdbba90ecbb6f07
+Result = P (0 )
+
+Msg = c075913f562b8eae3a4f9c00e1116ea713b41bc202ee365f5af5da19324965930f721a625c3190e7c73b20c3139a883b0087d7ef919bb2b3e64c76cb4b982bc5bc474283a2322df8013d2340e80b4ae554fc0bcb9b053b06b37fee2372e5728c35a383731fbc84c88afeeb99c5562b92542dabc6504772d22448a37a4360fdac
+Qx = 66c143900c0048a4917f1710682b94908639a12e8
+Qy = 3010601f3f396c80c80f3513fd4aff8df20d776c4
+R = 21da8250a00dda93d798a54342f6555d28c7d1146
+S = 2c475ebf4586d8cdfe85ed8eac9de10064c55ff85
+Result = F (1 - Message changed)
+
+Msg = d335620d13e049b7f1f53d6e5274892e7ddd7d300f6704048c4a8fa08bfd95f9f497418fd229db8890ea09506b3ffb208254ccc33c4bf944f998b5838ef89a42de0e94f576321e7bc4863cf04c134a99a043c401f33f0d9d2e9b331e6cc9b7abe6e1956f9228096c64057bd675527bc1003de11fa0698e12ee35783d03d99d89
+Qx = 468fae3f21387a8f137df18ae4844928ebd52c184
+Qy = 7bf3cd58244ebb1c59eb5b6d55a4984718fc804d3
+R = 3c58343bd0c929ae571ce43aea1a2586e50cda3ef
+S = 379a6fadb3578e4eeb87a7ba5a29ba52bf84a94af
+Result = P (0 )
+
+Msg = 420ab6c8cc2a92e1e24a0b0b20a70ef4e4b156ea4ec58f6b4fe1054f10038eb28d3e748a7cd393c8d6d373a03843acf2bc130b9ece304b2acf5acc58b459c1b9f3f455bc1c98095ce4619f8bb897a0d8fcc77ae91a30ad7928fb42bc35954fb432eab3945d9ad1706f72ef457d64976ea5dce2bab6c01e6c98cde9ec3ef152d0
+Qx = 29f2a350ae651af381b86ec7c72634b4a39b204f3
+Qy = 347f160e02195337ae111c27354e4e67d481e5028
+R = 0e2128ca5b787e8909a7e0f342b1adfd44bbe27e4
+S = 100e6e5e8e785fb2352bffde55817f0daa7a1a124
+Result = F (2 - R changed)
+
+Msg = da73372e2e4764fe985e3b9d1f17ce512ddefcb503436e06ba06daf1c5a1d8f6d1d658c17f56f2724c65e60f4c61717a8be388e45dcac84dfa292a2c5a82a8ca1472c52eed853af19eb697b2da7aef9fe59c341d04bc7e32ec2d2cee496dc2a8b911018e17393c52f28fa5d41d0ec4f9b0eb32fec1f6eb2884b19c7a2660bc78
+Qx = 3f5d3c13badac97a74eef137bd36d045bccb8ab86
+Qy = 3e0b1353af0bf5d4de7a70cdaf3c6ade3dce6c729
+R = 0a35a12b30b158c37ac907a3572bcd06734137233
+S = 31ae63de5655418304fdbee3f1a0b650b5afde732
+Result = F (4 - Q changed)
+
+Msg = e235092aba8f9947f76d4a4f7bc4484a1a43a7411a9522f4293ce5dfae284f30221e54ebc32329efdea1b6228ff09b2e9eca2750f2b0c79b6a577cc1ff78685e7e574c90c77dfc66821d191e4a61f036a5488c276edbd77a22fbaea39523a4d9f949dd7b02ba7a526853881d32adfae69e7078d5160c55a70a5474d71fc0e748
+Qx = 234089bfd0d482a1da11158468ecd817b577e1f36
+Qy = 027abdfc8aac4317584e8539ae641118bc0b1548c
+R = 0c7927d608e2dc26cf5beb632e4178473eeb50780
+S = 1b16c05f341a9a23db46fb52e87672da5c1a3a882
+Result = F (2 - R changed)
+
+Msg = 3e5b5a406c0b8644c1c6e2c59a7c1a08b6c01c53be1f2d866868599097789967038c3bf46a8ce6354400304b0df207e4a87512a5e206f39fcc842b3abbf7cd7e2ad0f16ed740f3bcb1f37a7a7dad364679f489019f8f9786952ac1e0cae6b15dd2a36050a74e5babb51afd9be943afbc0b13883999db4c6078a10a860cef61e5
+Qx = 093d0108e94d00ae2f090254ba53e6b4b72feedcd
+Qy = 159f81390e7908e18ce79ae615dc5cd1ffa158d93
+R = 3116a0b14018918354ec5503369a06e2ddf441d6d
+S = 3121e8a1812d6302aae0b06b4a2a194738636d83c
+Result = F (2 - R changed)
+
+Msg = 1a3e41de7e864713f32b264a699ba3e30370d7659c2c3e60aa20cef8e2ce5b46e033a099b4602bdcfaa7cafb2382e1b6ad22bb66102097290be62732fa62832126ac984ff98ccf3f55bc55335cb960b6e5d2d52144ddbb840bc7cb68384b2ebd5af9b3e07e2a61512cacdbee958e46ae089947b7702f3e1cbf9fc9ab7b2246bf
+Qx = 52a1b5cc5d4cd903d68aeaab78b1be421a552ed30
+Qy = 26e11b9d52a2e841108790a8e0dfb922b2bd68a01
+R = 0a11cf771690e3fd0e5f76b41db0dc74305cb8273
+S = 2d61fb8e06dd2797b34ee57bd609e19b27de727fc
+Result = F (3 - S changed)
+
+Msg = c0503893b09f917a64cd4d7325320b57a1680e6e222a6579b9723dfb063f4386e139e7297e33d61aba7a75637eaa0c601480c38e21344640d282ff3deb715b710474a8463a5ff04d0c80f26fa6bb56453691641469027dd249b18ea7af6acd40af15195dd124fb74f50ea120f837c6d28139a7ad144782785df2a1be980a73c4
+Qx = 280d1bc7ef1b3bb08d99ec0849e93f4372705402b
+Qy = 013b61471b3ffb706449d325edfc012479d650091
+R = 0e08068f060b29aa45bfe97b3657c6256722e8140
+S = 27027da469fb939e28ccaf11725c4a206470f94d3
+Result = F (4 - Q changed)
+
+Msg = 49ec726975a89d920199295634b9e4409ff5db8529d63a8b475a2520c5760799f53dd444714f72b4c9e10bda99d376a1ccaceef31101c12bea3085c29216ea4ef59e13e472524d48a7e64738fd404b9a1219e7f5915d0bd3c9475f35e82124bebc46b6cdb876fb155806da10dbed53acef38248bac23e9e66b069056825befeb
+Qx = 3c3df85144cfb4309a94962fdd8210ade4403d59b
+Qy = 18865efadd0c2e2bedfbbcbe2249f8f9a6ebfe0a4
+R = 2321c234892c0f618ab3b2757f2d6cfcd373026ae
+S = 3309b1d25ba0d7732eea3f5d9941a2243ae92613e
+Result = F (3 - S changed)
+
+Msg = 324fe92d287501308d18ff3621d414259483633ddbdac0f5904a795d57b48c4f60ee295b008705017ec2340df9574235cfac2428bfc48543204b279ba069b347a1998855f9b3b98f99e39abfdd1658460bed72d4a1c6f13012eda44762942ae2c1afb2d82eee1d9e500446934e0ff1301063cfb1912b548877f8ed0eb930a059
+Qx = 1d6d4d6f4393f678ece3e0e52893f8563747d8615
+Qy = 57188602a6ba66c578382508f21952f993bbddda2
+R = 1f723bfff1041ff5acba45b84fb55b40883e62d63
+S = 178ef00f9d82c3410961c9d7dc8be88bfb27e5b79
+Result = P (0 )
+
+Msg = 954f4744e4d8be4e69399a2f9548279a9fe8b2e2ae0cf9030cf77207b8b6af38d17fe494346496f6547a3295b14c7f16a1207dca0c5a608b604663aab055ffbd91155b5b250be1f1af9cebb30b7c5ffaa31d88e51d38013a28655e08973e61ac0f72e72d35c395b0329c832053c9a711ecca21c3ae23826413ca3f9bff33ca06
+Qx = 7977a0b221c433e5a30b862de529ccb2c00e63273
+Qy = 5dd585aa2266db228767735ff2f28d3cadb4bb763
+R = 09c21576b7f6faf8d4b27376a446eb9b7062a699b
+S = 391abb0805fb2780f1c580f185a2336d59f83cb52
+Result = F (3 - S changed)
+
+Msg = 3456cb8ae7be9f6c901afe431c1835c111b90e3fee2566640a4f77f2112ac985911bfcd73fe919e81efaeedbaf98cb0b4f6b19c2c7ad8959dd833bf02ade65e930fae67c23caefdf59157b3d0a30f10f7ad846a6c42d7b1fd23c996c7b91e3483f6e6b78230ab321020fab14786d904bc3f92a00476128719548a3fed0ec7309
+Qx = 4be24f26af640a46f65847c2d9ef4d0fa02c05850
+Qy = 5d984f9d002f5a23bcca794184c45cb82e512699b
+R = 2a4a821e781a0958794417c72c4b8cb4ddb406cfe
+S = 0c319f196643f1c244a213a1b9acc4ea46117411a
+Result = F (4 - Q changed)
+
+Msg = a2e74c77b3150463bcc334427b5c59262d79a7f14c0867bc16783a00829a0049c3d4eb580ec5578fabfb30063e0e5ed16f417367b771b20c387a2693691ba9fa184304e3b1b3010d5e16b688f7aa7ed746241181543004bb60d466c92501c4fa3da6e1466b050d97cbc08ff426633b2291280c2d78b845fdd25c1034c0b2d921
+Qx = 05d53394f99480bc36aa9773de6c7b595bc3d7a09
+Qy = 446db1ea34aa7e7d514b4c6a1d9e9c6892d7a994b
+R = 2f18f965286ea44272113c47e69424310c7292750
+S = 37403c94ad93c4d4467647f73bf6ea2fad8930e16
+Result = F (1 - Message changed)
+
+[B-163,SHA-256]
+
+Msg = d71e28f1d38eea0326154d78109b907e59d8fc679ffb730819ae144f8c04ab21e35f937a5568f1b9b657857ab9d21cb63466b769fcdc06ef3961116f6c09a81d56586a08ec7572d87da579b0fa743196b5724f5f883ae4e7747c6dcbdfb332734d2229e842951d79beeb5bffdc72941d6d0c474db4ceccefd2d215028143f85d
+Qx = 28c5c9d46450ea9c267f8510ef0c37702b93210a9
+Qy = 5fa5f4acb8c345e228477db5f51b2860aa4f1aaf9
+R = 17df984f390f689ae4556217f12da4c282ab70f58
+S = 2ef66dab9a2753d66e818d9a0afbc81cd21ec5677
+Result = P (0 )
+
+Msg = 99dc739aa0e8af7604247b23e0d07d6a98f22cbce297d9845e78371e2bfb96cb47e483aefb55178e5f64c4ff9f8b110eea3e60a50656233b55793b6017e864f2610e343410f9ce56aade90aa9901e40b76c03db277620faa83e029df1a6562b524f5b170cd5873cbb9c9049277a00baf82d00639dd9ababe3fe632674fd68270
+Qx = 4c50a24fa97a9da834582b87afdf1e2ab468c16a3
+Qy = 6ed3f30ce8ac92fc9bcff8e8cde607771121da9b6
+R = 0ae9a37a8ec2997bb94a770eed842e128c0dd7370
+S = 08638b7294cf664b3f380887330f853a8eb9242fb
+Result = F (3 - S changed)
+
+Msg = ca4512c164d2a3b935afb09325d185c36ccfb2a806751803e5575566f6d42433432d30eec11b39a9951ff73cc17c13f886c17a8adb38afad04b35859aa239f048f0c5028b9130b9f394f416ec59bdc1d6fc207c639c65840652ccbf41ad2c8c313c45e5e7b4ed7d102ccc4f8d8fd372b752fc0464241feb00e65b30029949600
+Qx = 2ecebd10ff8c2a609bc61e9d7adf3ede1df72c3e2
+Qy = 1420a63ed0100621ac66e5a091e0fe15a21ce5899
+R = 0afe8835d758a3dc23730edf2665d367d5054269e
+S = 3b4fde9a5bab82459ba1dc97d1d4a7dd4d74cec9e
+Result = P (0 )
+
+Msg = 609660735332c3e556c46e433ea7ee4640392899b9dcc13596bdd9c934ef8dafeb7e4ce343f75b8fc64f197202e097abc3435e63b367944129154078d6397c54b71bea92db386db36f435e7e59dff76d3611ed1badf9d1f851aca456802d97ceb318a71dc4ea174dcd1e5edf88afebde118a29b2ae25314d10f0ac0b720aecce
+Qx = 0560aafbd210bba079c91d8baaa32cb567f99a611
+Qy = 5d888f7201729477b6a19e711d030e092fdf28189
+R = 28e4f9aae1cf5269fd2e735a019d89a6cc9290d0f
+S = 2fb89046189838cc3c5bf1a06a467cbb99a95f37c
+Result = F (4 - Q changed)
+
+Msg = fc0b4e94904aaa0d1cc7c01a257cdf76c556f2a6256f706d2b410dcb8f3f435ea1a96af30dee343c1cddf0a471a2bf004701545334f15b0c259ad97ee3e69743c41050050e20925d410c79a01220654bb4ae39564212ac40761b8df82e95d4b268ae12c4ee804e49149b07227199700cdcf354ead172884f68985001f84ac1c0
+Qx = 3213e001611bb966bfc0a140879087fe04d9166b0
+Qy = 696ee474d446dfea208bb7ed7d9a86025469ff570
+R = 3b323594ba62bbfd9f2627ed68ce778e7aa227f0b
+S = 14111ddc38eef82c1b4396d23f279d3e84293bf07
+Result = F (4 - Q changed)
+
+Msg = b0b4fb49c2f768f9cfb80465b872793abe68abe6c6bba81c67df25967816f275915a5adff2dd0c3536a92066b35517f6fc83c9a155e57a66cc618f789d3d6712d4ab83ff2ebdb545cbf50e3b3b9549d68692827b15dd31d3aa957e7fb37e2617069913c0bf3382c441b08d9717f777bc2f9d5de7cc8966b91afc5ed30b21fc1a
+Qx = 4b85b07a0fdb9644185cb83b1b54e2e813ec02898
+Qy = 5e212a6df2851ff7a60eaac9d301086a0f954c967
+R = 019f18ff6319c5f11fc2dff2f2ddb54d4c35f1f44
+S = 1dc7592aa20f675e2a6548e27bc6a6df86f71a8a7
+Result = F (4 - Q changed)
+
+Msg = 0af238aa403fc1f854f3ab403005ab3137a40e6a53bbbbf978f4ff24db4a69ff0f2be2457e6cf745632f79de671f0d293577c44327f08255f0eb5d1e46048c894d0094be8cf283477a2824bd83045d7bc675be25492180d8da4d2b113d1c730167bebba8dfb14d332befdd069a55ae4f9e2d19468f08b56a2e0e72126adfbff9
+Qx = 3b29bbd06235d89dbce629e0bd3c86c5dd32fe93e
+Qy = 6e1283667175d1eead7441c56970ebc9d0f414af0
+R = 23ec9f6e3050f90b0d8612d3730d085769901ab05
+S = 3209a58469ad4830c33e5e2471ca5e07150f02025
+Result = F (1 - Message changed)
+
+Msg = e24d41cf967a127d251f0127a6a5b316de530a56b8e9bb805fe760ec561f21dc89cdeae9a46968595b6287c102d97185441123a09b47624fba4d2b99a430c8e80fb5976b8467da82849790985c3c61ed81258a603f776dba84b9c83563ea2c1e2387d060eee6ebb426c17b673cf7973a81fe4cf958d1018c4730c9b394c00832
+Qx = 181c4b29c8aa9612861002149c2460820e2fde921
+Qy = 78ccb7d57a2d41c89b948a286fff6b460ce394c3a
+R = 1f068c3a2146347221d2d3078e834c52f5063c228
+S = 2a652a37c61fc3f998d78a581439f8a985e8d731d
+Result = F (2 - R changed)
+
+Msg = f1bee575e7a9de83594c7050c87e453a9c6f86f3a77d939fa5f9972a0c4651dc5c5579c38336c69459775ac8f82bec868407060c80ea03126a26266ad5062b13421d025728278c762de6308901b88ef1a80a6afa84a74bf95f4bb7439fdaea255b201de6c7886794f03326352e92d8ebe7a44c6c59b95524d2eb31cc4777c070
+Qx = 592a9c71fd0b0056ac9bdefdae6a6265443d75931
+Qy = 6b07367af2a3a232e6d3f8b5803a0076ef55c5ef6
+R = 3d39d0d73ebc1909eb13048244fa23cace85072a8
+S = 1df8b09d6a4e40b25476337e30ae4d7fba0c22e06
+Result = F (2 - R changed)
+
+Msg = cf0f2adf9d558d1a3cb15324ef900c57194f8c8719e1210e1cef743d752c7b0b38a2b2b28364e4a049f40fd34ded493ceeaf59435550116670f87f59f99889b57e5920528b1c02bb4bf77e789a97d83ce11c049c8cf010ff5a16db234e1aca0de8a1112e28465bc3ca6fdbd4f651d82c286fad3d390e996679e3273712cfd62c
+Qx = 77634b385146c3baa0e125e42ea94d5a85ccf68f0
+Qy = 1b86db5b1bbf830c01c9612569564e526ef4e4d6a
+R = 0c29ef36f870d815638bb7c04ca9e53906a2df631
+S = 0df6d065f07e569c2e683061efd5a175394c4868b
+Result = P (0 )
+
+Msg = fd7df224f8fb7c77ff194718ff9084475f87650eb04f477ddaafa8216362fe36f06dc0da84eda385a14ba27c9b6a887782ad3a4fd2dbd9943000a38d4b0e040997c441d12c112a5e98b77993c338cc1e1bc432102072166d3edc8ec41a684d62d647791f5c02a1efd5d169bec56dd661c4281f8f2ba583c137dbc544f3e65fef
+Qx = 05fabff0e6e22541abfbecebe9babffd12455c33f
+Qy = 033f5d04df7a718048f964054ba9f9c6529a7415e
+R = 1dd0cb5c7e43fab0008857519b691f3573d512646
+S = 246094f9f2b7160230f5613a7b9f1277a7d411249
+Result = F (2 - R changed)
+
+Msg = f8bc24400d260a04c3ece39e53f06ec1211f1d1519ae25f0430c7f1bf37d6f7de729f3f867437fd0d6e28ce220eeb580bc27abc796e5bc3a466207691a7627a2aa268f43d70c69335fc5bb73ebc9e9ba9010f8a0833cf36689a114dd23d3430297920f47328313bb4899c68d84aa1dd8ad1246937bb44b3633b21ea45ebd2e74
+Qx = 11fed6cc62eed604f15afd49d9cf299c0a126566b
+Qy = 199a308c7f1091956c06386e6be8b8dd0fc73cd52
+R = 14b78f4319e1e904e97f6e827f02d8657951e6312
+S = 3fdf9583f518f2a97da666e059d5365f1c1c78f84
+Result = F (1 - Message changed)
+
+Msg = dcd171a1aab4a4a359cda388d60ab8c828632f749e74f70fc0087fd2ad2b7d1c221da4b3a2ecd5269566d171b5cb0fee32268a631474c6404df221ba4a16c9a9b100a6841df3c399b0453843613ba8dfe71ff8daa77bb4a327239f8cd8d7218edca425f683a88582c3a999738b2b7dd52e842deae5f8cb5aa6d1e22935d79bcd
+Qx = 40c8984fed2038ba0fb2e013c372f611428d3c87d
+Qy = 5bd85bd23ff28f781386696cf4bb53ad0bdbe8381
+R = 38c52ba04c18b91cf02b014d5203d22b010d8162c
+S = 0e205797913f6afc3d1ef543029c6bff1e2321b13
+Result = F (3 - S changed)
+
+Msg = 108c5584450c0a99b3cce79e7e69719213775d0d1aaa124e95261d44876bdbde3fd498e5f092fa8bf2e79e03cc05d0a2ebc304c09f86e938177b6c5fd2fc3cfd77af66910b020e8281fa14af52f740711c5f6e1dfebf267981c0ae4d780e755cb58585aaab8a0d27168be9d01979ac85d65395a2279abd0a54e33988d5e888ce
+Qx = 2436c4c6fe51ff18ecc3fa3c5a5f9646926efd549
+Qy = 18f4cdf08779a84c512d6f36201fa793e0dfd446f
+R = 2fc563b0b7e8851e48a21475e20a72b4d1a2e4246
+S = 3b7cd8b9453282e01f31c92a2dafd81f292eae4fc
+Result = F (3 - S changed)
+
+Msg = f28f9187dac174a8771b1b89cdce4d0b2025454171b73e2fbed16499db8d59d77842c31a4e490d916b68dcecb722af6c4163642ed3531371c4a05f748fc80f78326662f44ed9c2ab390ccd31ff4f31b16ae836ee3d63285b57cc5ef127112b810dfc7e15a057b22a683f4e2f6c095684cb8bca2a1319a43bd51a940418394d28
+Qx = 5ef882d624dc2dd155f8d894b8a84711aefa54bc6
+Qy = 397b2a2bf24ae0123d2bb7c5fdf289a3765840075
+R = 39a35e2a297904e4b7fd1a811f895dc47385889f1
+S = 3aff0672c0d0f6fd5b7e83d7e1985cba2b9b44ec1
+Result = F (1 - Message changed)
+
+[B-163,SHA-384]
+
+Msg = f71b25d76e5926dcab67faba84580e54f0884055f59e864477274b1cfde00666a9156ef2570fa0e3ffbd1e41fb39479aa0e27e77830c76e209a200040a3bd649b326dcd7b8df65ce81dde679a968ab357f2709cee9252830d8b9a81b5d5bff8c3d8c42b23e7bfb87b9d03c5106be003ab4fe474e1e628e0632820a337ec03999
+Qx = 5454b7db786688ed04c418126d7406f18c0dec0af
+Qy = 6c7fa751461477950ae090f420db11ce7101e7a5c
+R = 0dfa87361051ffa7f226abc2e20df2c7feedccd96
+S = 1c621e13b983723288b57888ad6a93b9229211a73
+Result = F (3 - S changed)
+
+Msg = 26eb55b622125b4ad309d1ea13dd9e85fc82e849eb0a261c9e961559b34646dbd051166bc12876aee8f7cb13d6f7cc3b29d8832ecef294a87499efc1eb3f42f9eae6db153f5a4a691ce3ae918a9897f7b8ec38fdd87847a04e371db00595abfe3fc5d2ba3109ed4736e5ee48a721fee04ed2d98e78bc1bded9920eb75b441d76
+Qx = 70394dda5b4a859eeaa9334b974422fd8ca1d8c65
+Qy = 5a7fc827ff93f9b848f6e1ef1f369f7dec1519e2e
+R = 242d506bd38ebbaf8122b692e1147b8dd2f40a3fd
+S = 197c19f4034a4473a0323ff49b5a2b891c3adc438
+Result = F (4 - Q changed)
+
+Msg = 5649fe8392b05acc167d2a680b8b004bbd336d6bf5c0c58d4ec1a490104f4de2656cd9724e0eb1b90fd7d9e57bfbb871bf609268c34fc98551af54098fa50d15c4b237c2b953febb6caba87662b01191ea139ea2ea67c6a5a39b375038a14601a535983de3d2b3f020dbefdaea114d3b75f8c292c3ad0c96bfd728c8c092dfa1
+Qx = 4d836ca474b201d55e7404af8bb87d1e18d0f795b
+Qy = 08548321c0b863fba3bc81fa3489b75a34b4cdfd5
+R = 3a706344252c12693cef5ea5816bfda6ca522d1f5
+S = 16e176079887c335202823ff61a3e7f0ff15bb14a
+Result = F (2 - R changed)
+
+Msg = cf71e3ffb9d5aa2b2cf486c60ed9a6f8925b5a70230e3205a1b3590b926c6edc971088a41cf7c741cad11cbff58982dbcd9d162a602071571bbe69ac429d94a6cd95603c7ae0d9ef5829671dd2f5a0d094190c7bc81f71be648fd811041af92420cff68df83998cee914700a37bf844b5835b774fa16eb8f282905270a0ed3b0
+Qx = 73553b9813f20967ea43e1db0accfe6650afc47ce
+Qy = 424a2c4e363ea25746e13543c68d11be9bd1aa075
+R = 353825002d905e77b39bb7be5f7cd1f168ecb4e9c
+S = 026b3c0a0201a8029cb3ef8d9cda4ba83be4bfa60
+Result = F (2 - R changed)
+
+Msg = 552d4877bde7ff57bfc59dbe4c26adf70487f5f916961f710928f9a4e1355abb88a765a008126f7b23d6f0877204b1a409b117064e319e6f46bd2baa473cf64b589ca4ac7d9bb04195ec590661697aeee760b0631aa1cac0ec20531c79147ad9cf1530676a930ba215fa7f2583ec651ca427dbaab137c4a48aff025c27459701
+Qx = 5bf20d693ccd5ec2a5aec29ebcf43882614af4250
+Qy = 2bfef3ea1d61679481a8242b5fd8bccfba1e9a8d1
+R = 121bfc9d067c83be1d30ea7f85aaf4802bbe835a0
+S = 18fedd877f2be503b3a07332b8ab40b340bbdbe63
+Result = P (0 )
+
+Msg = 0204851dfd17c1fb6f049f43eade2931d746f68dc89a92563e412fd7e424b71cc1d9b047efa672b010d63ae35fe325af841c7a47bf782ec40e9c1307845ec442345208d4339aecaa029a6706b14c880ba91acb7b03a96d51a7fb3837e84ef8ab1f33bc17329974b5bf5fdc6624720ec8a3e64dee4c9695959b62a2fcae6ee55f
+Qx = 6638717c3bbdb55e3d1e2f8af4e1ac6a96e716204
+Qy = 0242a160b7395d2a768a556828150a8ff2e49c30e
+R = 1f9beec4e1013a92a382db68b0fa157ccfdcc8a3a
+S = 3c19468b1362a73651c68a4117e88e52c1452cbf9
+Result = F (1 - Message changed)
+
+Msg = 2468f6c0fbd9af1a3dd1442082d7a3939f9f89f5e260ab427d46afd3f3731e1a611307b0f9b2ca03b5faf3f31ef511efd01564538005f4378c88dea71ced1476854b0f2a480bd482b5ef6efee1c053828e211ed0a55c8aeadffa89cdda329660bbdae7e1aa36945e61a375136282f03b8168ba2dc4ee808ae4534d437e6a8b97
+Qx = 266ae51a5d30dbc1ee3afdd6f1d17915102cfcafc
+Qy = 3f66b1af32f69260bc6b7465984a9fefccef47124
+R = 04a77b80e0e5c92526de57700615c9b29d98d40d3
+S = 3bd72bea88e4f8e97b8df06d34bae4bb2f37aa3ad
+Result = F (4 - Q changed)
+
+Msg = df7280dd142da7e4c7516527b319815554ee9e559f7e6210f52c30a8f87f954c8cc4b96cf259f9bccabce4eae4a19b7f403983a30a4c250a639d47fda6a7acee178959726769ba7a9dd7de71f331fbd9deca514e5e87f9eb22814a0e1afa7c995d41ba88d739afd035bda85f330c5831264d41029f631ea6602f1b48ddf89f9a
+Qx = 35e95775a337e1055b87e3b01d2d35c1c885e9197
+Qy = 526728cc4820bfe2d1c630922baff77cd612c6df3
+R = 0bb1185cb02a89ac7a57a9d5daa5c953632f87bdb
+S = 3b11c0e3ec76f79036373dbff38add2ba90d9acc0
+Result = P (0 )
+
+Msg = ef674a1d185bbb3f94dee6cfb74a4e0982f6f7277d62086ae2b691bd1435106c9c8b195e8c16b304b436c6b00c2dbba1eb81a962b9cb96949c43b123cccbcff2e1fee5f2bba29a6bba50f16f1228060ca39ab46696a3cb45868ed727a86328c76c06909e19ed331fe82e034830a7bb5016bc277addf3173b4b8bf84e48c59bfb
+Qx = 34a224c1cca69b45821697085b1bc721411ef2779
+Qy = 117543d6404976e5f70e228d403322374f2477fd8
+R = 38e2437f2ba29ea131546dc032916856aaf6f63aa
+S = 00762c3670c4b3f8a59faf0974ab9d87dbc540212
+Result = P (0 )
+
+Msg = 092a21fa1d17961e4859c20896867834d40e8b27e41be44beca6ae2862a997bede72a68086af82f90de511b995287e9d7c151350ff4e3e4b45cc3bd35048f7a784f92c84f0c1fb6d45d5c77ef4c4ae11b0d67a7f5a89d0021fdae1d74fd5a0aa3b5889fb0c226e5f2d0c4bbd186408d7a20f1c0c85080adae26e3ebb81fbaadf
+Qx = 037cfc839a24a54e24187853d759b38aa92f6dedc
+Qy = 6af5ca2d5bcc470f3eba96d1e0352e3a8b8ee6051
+R = 27292b9e84e4f09fe9220365184f9e45f9e634d1b
+S = 06504ba151db9291e610da5d1bf86a60b67c65819
+Result = F (3 - S changed)
+
+Msg = e27a08c388ae3f5dce49519a07878efd09c9b5a4204a21b7f68002198bc0a7cd4f8c1b3d952d92e9cfff33b264a6bd339da823aa221337d1ec787989b40b5df4f6ccded1c9cce871072c58227e6be755afaff21e50fc2885595cbd93bcf3e055940a6d4dea93079f3ec8d460303ccaf9c415f6c3c95ad89c9a898c1e9a7fef9b
+Qx = 7c89d4f1ee998a6421e5d71458fb1f74a888af0bb
+Qy = 6885ac1e318fdec1dd8fadc057c06e350af9efc85
+R = 19573942feec6901937f92b3a31a335eeab80600c
+S = 1443db45308ed7b9148bd680587a1420428ef53fd
+Result = F (1 - Message changed)
+
+Msg = 1089be0b4b7531840e84921b5de6514ccd29612c9ed7e687fb994da0b1062394fd06d30c8c3f425cc3a05e9a46e055d044ab15e08f8658fae65ca91fac592c0c5ea76ca93d64418ece4270e5cacebbb2cc3c6a1126764dc822af73c12f3c8e089debc088517e2a14559c0bb80c26e0a405b7e827a43280381fa9236fa146977b
+Qx = 1dcecfc3ae4ed750eb6a564f0f25393ac655e249b
+Qy = 000f5c4c076cfb2ddc4a2ac066b1fce1f823a94d0
+R = 082eedfce7fd389742000af370dabc812bc5a8659
+S = 16a6176e093b35f6c6483804bce328dac23224ab9
+Result = F (1 - Message changed)
+
+Msg = 7ee2d79c2a2cb56312d200208e0e5bcc8ea023171a15ec619e59e176a0d8fca44ea6b39f04a9663f1db12aa642c7c3991c1bbb2213980d68f1035d2882843774e1a7ade6b13b1d90ff099f96b516a8c494bc4b7373bf48e6cddef28ee7bcb62d23b1ad03e33f925ce78af321f7397e6e1b0912ad7935c30aff1dfcbddc2f0966
+Qx = 38cf4ec226adfef8c89bc29d82c44e5c844d5a829
+Qy = 0c9e1057c6cfcf33b9db2806e5e009f6448e03541
+R = 2c3327d89af3ca1627e80c5f1f0f7cd3ff837e0d3
+S = 36246e19a9a7dd5063a54292a003d945933afb739
+Result = F (3 - S changed)
+
+Msg = b114132efecac3ee7e1015dfc4442305a57a6fe28bf80299faaf66b0366ee9e95ed8ca3ab322b2b82752f7731c1e629e5318db4a7ff9dc7d26139940562ee9cd7a37c5d0f4f16ec0e622ff46328fec6839709c17ba85f2797e6c621add0bce6a64e7644eac3476ff9f6596e9c4945b91b1caa3191c4086c934c12b68193e3d8a
+Qx = 5ef214d347433c5403e0b624f16380f2f97bec04a
+Qy = 444103759ecc9bc972a351fef899cbe7a68e54394
+R = 384a416ce259a8a3b89187d530e5abc772c915598
+S = 2659137fd4966f3aea9676b1a4be244fbc634ba2a
+Result = F (2 - R changed)
+
+Msg = d195a831e7a10b1dec5728d4d156e46cf8d7eb569a44803a3d1bad3a44cfce9bee69b5a7aff34a0512d00db0ad6d3c93ed68c35c0385859b3e34a017f216bf7dfe3888b5335dd4fbd72c7d17ef228fdd635df8b57b65123f14adf8db4ce70c122adf7400ddcb918be836ed05985f2136de357a2d6d47aa19090d2db3850d844d
+Qx = 7658dcd142307ada8c050e28b153f73188db5ff86
+Qy = 166a54db18ba4de4742940068860f383bf920c361
+R = 2cdaa5ee37657aeb777dde64feca6271a414f8545
+S = 2c8e57a75cf3d3bbe7c86112f86f383af5eec3131
+Result = F (4 - Q changed)
+
+[B-163,SHA-512]
+
+Msg = cb8b18686b4b107ddc3af6b22cfb49a7f90ac7204b0da7d1801eb9f96cfa96085bb3805c56171dfe0ea1c03b8e2c8c9fdb1761fe9ec94006be35efd3f3a2849a6516eaae9a433033f9008546f4a02f23b06f15455b6ccbf48d720578054318e50921d9601f79fbd197c9d0348063be3b992eb853eb6cf399bd409d49d0c7f853
+Qx = 7dffb2183e217003bb9ed5f74f1146d38bc3b91d5
+Qy = 3cb671a581d207d46bb7bd91c779054adf0110941
+R = 12b3c02be2e0010cd78ea038b4f12405628ffd759
+S = 11ec80dc4f4f66aa8dc716c290d540da0b3333169
+Result = F (3 - S changed)
+
+Msg = 93c2fc1dacce2f5fbab158990f810da3e23728b855393acce022dcd118dad50abd0cc34dc226b83cbdf69ff71b973d33d1b24c643cf6db04c99a2c36fe56050085d3d07daa8a11169aff8b9d24f8d3ebeaca7d24113530dac40f2e3729691342432fd97481b164ec391210296fe1195f0dfa6075f2aaeb8d7716ee0e3b7552ff
+Qx = 0517a5482a07705505f94c52a48ad68d09d13ef8d
+Qy = 7eccf66096d3faf30113624e5a0fad2bec42224c5
+R = 05861e4dcfc8948daab674e0505e2fee70aa9f806
+S = 180c9b07c384af365e3f7a92fec25fbfc00d7fced
+Result = P (0 )
+
+Msg = a4bc112bbebfc49099c9711a92cb8a7d2452ce6291e40feb585379711f16ae97fe0e895bb78cc836fabaa1efcfef4d8e29aea49b8c0c592917b911f67cd73463b317545e556d4d9a3ea1b641b7efc90fbbe83e05c9c79912157fd7f828a62bfc1ba9cac050b48c5f3cd3c7d6c3d86c619e28c1ecf934a03841ba41c2b66bf861
+Qx = 58ab1399ae7bfafd82374cc218ceab1ece0c4e09f
+Qy = 12120175c9c86dbb2840e1ad0bd52569194aa2c0f
+R = 1224d438c4bf6c5918900d1a887c37bf51532ffd5
+S = 2ce70218e1e9f4f27c7246bdd8483fde394a1575b
+Result = F (3 - S changed)
+
+Msg = 537efe1202c80df23d5e223a282eed633b2868c7cf1c4271ad26e2aa983c77ce3c56fd2b958821d69d7d745cb90cb1edecc5da05cf2dd1393f0fec13ee8fff83d27d225aa439c3699944b9ba8f36be7937b7777b0ff783cf99c4fdf3883aca2a47ba36a4e38ee5fdc59c8ef627a2a009fafca5ec82dc1186c3600234f11ec8c2
+Qx = 0f426072404eb6ef20ef55cb89af34a4fff2be7d0
+Qy = 5a1a5622f4a2ea6da84309987a9d85dc3979d4aac
+R = 29544134caff1f057a46c28db716701d6ce032a9b
+S = 215a980d609529a5a99a8511c073b15e985ca560f
+Result = F (1 - Message changed)
+
+Msg = 6aa008a0d951bba4e4860d166b988e87bbff11cbeb7dbbbdeefb7ad3d25b5c4954abba6908f2656d704befe3dcebb6007feed8c9c8571a68987b99b620e7f5fea361f2bfd1ca228f720710627d9d1c479833afd0aed8578d2a6a23bb60161324198f823452992773ee365bad2b04119d6016925843548adc1afa9c9e1dea01e5
+Qx = 212d9e4403984f8aa068f513a78407a34e5bee705
+Qy = 75a79942fdbb0eb611cafa6bf59338c067642041a
+R = 16031c9591efa6a4c41fcb8714981c33fcb835fcc
+S = 300e7699188dd529adb9f02055297e5b48ed3b6c3
+Result = F (2 - R changed)
+
+Msg = d6c695bc1198608da12fb6c05ced78eb19ef545af5a1bf2a91984d7a858922dfa265457e945c0f654e2ddae7dd46d2a76fd9f1dee31e838deef49169d4c229e9cbbf0372be69b2c0c06d43979c308a3f31dfbb3833c400d693bed7ee2bd37e6c418fd2b31ac7f3f1f4a6c168e107e53c42beaea250225addedcac9d5f0500455
+Qx = 0ea408b3e8e2559af25126835f3d8899311813288
+Qy = 57c0efe6fbc4923037185ebd1af06114b02d493d8
+R = 0ff152ff504c59181438c2bb901075110cd2331f6
+S = 328543010125ad76100eedf981d3e8610de1fc370
+Result = P (0 )
+
+Msg = 6445dddab08e2ed69e7ebc91073f11bc72a4779ec4afa777d819d8c6fa4fb6dcbe75a075d6d838874f757f65651db92337a190b19703f9e76decfba94ea2537b45a9bf4e5b9100a5aa935473f7df0621504c32a3582de227659cb0c51e1921222f6c4ed4f63a88c04706d78f7b63967e2de6f169b18ee158f534f15767e8a69f
+Qx = 059dcf2d322bb7cd0b3b4c6250dd20ea246b8796f
+Qy = 7e3821d0d2166bb7a8897fc02b86ce366f3fa11ed
+R = 1f935e5ed7881bedb2ab1b9b2a656a138166a50f0
+S = 28b784b8f43f88441d5f968617be96f92e94fab0d
+Result = F (4 - Q changed)
+
+Msg = 7218352c1392f733a1a57352b7e65cb4a806e0eaea1d9aa49e8c9cce62ad3017c055d7025ea50a319317c74933305a0c41e0463bb4d93a66620146eb7168a1115d0c4f068d8ec182301e09a389bec912c924267445423c7a2776927254c92b7158420e9efaf032e143fa40a93930080c96d51e8f1630af8097e5b9c4eb9839e8
+Qx = 0ff212bc5ea4fbd99fcf4276569e306f6b890b47c
+Qy = 1f5e561b8d7a2cc0f3fc5bf0424d8b58ccf392231
+R = 1e297af8b65fe65b8cbcf535704a3660a34231d19
+S = 3efab6d594195902984f62e6d9b7e94954db3a59f
+Result = F (2 - R changed)
+
+Msg = a16f81430d2b6e77f6cb38cce537d5e6a17555619fc51a53b43e0aacb6d96ac2f7bcdd57732534c9330ffc8cdca069c689e83820012f5db8918f9eb0be1480da2ec29a74c67982110b871e4e05d3f44dc35a68d148158dc705b34b508d1c8a49e5ce17789977546ccabad228980a06f3477153fafdfad2dc951df9b2dfd536dc
+Qx = 434e6a816e2a313cd6a95457aa2ff6decb5d687d8
+Qy = 190357e7d1f7c5fe836a8fef14352885c8c26d747
+R = 0997a25715c7d4213095679cc081fad6cd49eb242
+S = 160788247bae837e21eb19033d68b204217124b63
+Result = F (1 - Message changed)
+
+Msg = 0b2cf8cd4d27a0ad3ad7c2fd11004390ecdd49ae32611b283f090a18e3caa47b5bb043d0ca43b725a8a06505be770eadb648c578711315703286c585e75401069fbaa4efaba245692ac876c61bba4b4a40f902cbf0511c942a95e69d5dfac0502227d3ce29597d2a77407baa6d2078f45aabd0107b4fde1d1775f23b866c0907
+Qx = 0fe31a3025770a2365c15657027c493bc64120098
+Qy = 0174a69e2d15c7a8c1ae57c7373a22402bc31cf9b
+R = 22b36ca239e60d67a9c69f8fa154346a8aa4d233a
+S = 10e51c73ba7b9ebab2cdfab1afbf759e4c2270664
+Result = F (1 - Message changed)
+
+Msg = ceaf51fac48a93fffdfd066269565f87948eddb9da3a1592b28e8cab3fef6ebbf9df658b803d02882acb94f3c0d7c384413b6f0383d48c3944da7c3859d194bc887df974a107a62060c2bf6d6c343415817dc3020969ccfdde150f0f62d79a6a15b2e25d575b156de061e57ae073d411445f221b2a55f55140017da0de261cc9
+Qx = 6f2a651535746305a1434afee39314321c65d0e7e
+Qy = 40f1edf0f3536872d55bee073b5fc99421042cde2
+R = 16441798a2421dfa103114bc58b0b2f86e047f850
+S = 1399e3169e10ab2c987b8425c9a2f68338581ba22
+Result = F (4 - Q changed)
+
+Msg = 66f0d6342210bf0d95a2b97b4918d711359ff5cfab21d4509c15784b207e55894cbc73647055b8a8e0f103f1f86ace3dceaf06296418c9344917d05a9361224c8cf8ea477a838ac71acc26c83035cfab2c92f3f0f884617b749f512d41bc7b8acc729d810ae3a5f39f373f15c32e67c9eee8ff6614ed2301ca0772e489257feb
+Qx = 7a27cc680b70313f26c3a1ee68a8722e0b682f8a6
+Qy = 70a430191bab1d0efee6e6eb5b16bc5d49ba00edb
+R = 2cfe51c2719cd3350dc8d3b5becb36905aa4c7ebb
+S = 103aa37429163a543f0a91a8acf9418d4655b66b6
+Result = F (4 - Q changed)
+
+Msg = 8e8527032efe39ad0918f03738f6a29b695234b3fa5cfa2d17d91c16033291a8326ed4c69540d6ebecb6553c4cab1399fe8eb4aed3cf9085a0fb92ea8e561ba1bdc4c95568f71e6025c5e723fe66212becbd47967bea34bec20ed42727e997b49b3cf848f34bdf86d2cd273bbc754eb68a1ada14692e817d132c03aae63c8643
+Qx = 3f3bf0ca1fd81ff2903de75537630b11802d044a6
+Qy = 09548857a0728729e5f6423154da33d415ac4876c
+R = 2b83775986b8480da5ec381ecaafd1e4194efc956
+S = 08694a493bd4a01cf30964468bad3e5c7177b287b
+Result = P (0 )
+
+Msg = e3944b54a743a63e403fd644976a8a12a012f3918a1bf89c81441d2c3c9eac783eee24e7dd863683576596566a6e34a98d474dd58fbd8f177c9c588166024ff179dc9cb69fd37b0d8593332bbed79769cc8933c8ec8cd964224858a701d175a1e0819c9055bea8f54d242fd1e4dce613a9424b96b53a30b4976eac9903e630e1
+Qx = 1e7786adf872033a200005b25dc6dd526e432928e
+Qy = 4042a8e8c21256934c9f1f0cbc0040a3a5271ce76
+R = 2943396bc27268c4decfe70b20e33a0b1d71b60b6
+S = 3d86b56c99d905f64cc3856011ea29749d4e69aa9
+Result = F (2 - R changed)
+
+Msg = e6515c7decf8fbefe253d55f351481e981fc7e0ac2745101ef6e69c06e3d84d6b712375088a74e557b704dae4c4da3d8cfdc1e46fe9da54461d5b61c37fb082cafb115916f3e85995cfba5f37bcfc2f7bf7793a6db423e305f8cb4a61a96eccdf557e4498978b7ffa3f89499a77e76813012cf39f714d2daf0c093af74280cfb
+Qx = 485aaa6bd0b741625d6b2f007468ba4d9383959eb
+Qy = 2bdbd9ab14bdfd6f6d23c50cd61afe688d05448d4
+R = 2429d8fb3115afac83d3882e1ae544c749a410433
+S = 3d88abd7a723807fd7fb5992194698ef5482361cf
+Result = F (3 - S changed)
+
+[B-233,SHA-1]
+
+Msg = 744a77fdea6c14f225a88feb9efe631b01585293fd37cf5fa47794876b331ae48fe9100a39d22c465b40783c1f7dc167f088379eaa22d5aca0b1a04684a1b956b6944fed4dce640d893ae6a1172a357c86a5ecfcaa06a9f4e13688c173134b4b7f2b6b2f19df365a28afee863b7a8cb090081cf74bb7349de622aed640e8b308
+Qx = 0ca0345ec8fc76852dec14020148e206b8b68d1969290034b9aeb2ca860
+Qy = 0fb1f1ec816048bd52d8ee78a8bf4248beced050e4a019a2dd3bac39abb
+R = 08a4602d4c394fc5a5035fdcfba2b4c5c8f2ed750314beec41c483baec0
+S = 0cd334f1a839ea39e9e96da0f98dd7f3fb1b563fab547770cefb9460d2f
+Result = P (0 )
+
+Msg = c20b46e76d666830e2c66a1e83402eb647a0e3077ce76854a9fa98b917ee81839887165afd80be2f6d7954be63f1d98eef645ea224b03b8cb2f0d5b16eae163bdfaa4f81c059c1c83509a4a0b3b2aa54e89cb878eadf5dee3406e1b5641484d7fa5430b597c1d719a0ced8f452ffa76ea22ce3f009fbd76d7455291cd04e14c0
+Qx = 0741b05943e0c1b3d3704fd9fff3679097db57185008d6ea6431f210a01
+Qy = 0c4bf756686564dc6f561fffecd69c42f3bc0ede57a02c656fe471c4d0d
+R = 0ff6ce024c264fa7e54b80318b6d1f4d8c092f23905b625e3d8b506fed0
+S = 0e6e84e605b9783810516a9066e0a372a4706f54ed2302493aed1713333
+Result = F (2 - R changed)
+
+Msg = 38bada9a64f708642923ef8fc5c2acedb02b5f7d1714319a8753ea45c89d00ff725fa9fa3e9780471715aa17d0af7d16fdd2636cc466fedd8540c3229977f3e8c73d9932fc4e79e857fbac862eba0b0c92910ce57561b8cda03a57cf3a1b0293ab1a44a28a82dd2c52e3de3d41e1c631b9e15558e74f1c9f9f5247a085434e41
+Qx = 14f0830b3f22466a6ac8ffff040d0e16b11b57c51988142d79cdf637ef0
+Qy = 029e931a762fd04f3cb00391718367492cfd30fde71e816f202f2bcfbec
+R = 0eb60b050d0254008bcf3ad49658dd3d059725705ba47b605feacfb21b4
+S = 0b132577bbe5c4f9be6c343052337f4f19e550332c2974e80af6726b8f3
+Result = F (3 - S changed)
+
+Msg = b249aab0e994709f836f5d9847eb369ff88416ddc099eea66b4e8328f5e8f3e1ac3e3b799083d02dd43343cb5213810cd122a031dd6d271dd21f1af96cbbf00e26b09ff5dd7f728b74485ff37349fe06b2798b39cf3f15299e4cbcab4b6a1e686a354bf9ab70e3258d4992d8bb3dfea4f4e32a750ec366bbecca6dc042633249
+Qx = 16856542f8b99cad35a30b9aeccd1eb7a4f4d23e71fa4f57acd58015b4d
+Qy = 1f0f56513bae5879d18432483d532eb299397f2831adc8f143d8608fbb4
+R = 000aaa206b2c8704085c3b520cfd6e6fbe9c559331416ba3c81f82579a4
+S = 0e4960e3ef27e40a332038981720a83194f8394f762b7d175360c5435fc
+Result = P (0 )
+
+Msg = 02d30cd64c298f92254c1c4447da275c524c4ceea08678c8220ac681b0b748f3419aa65252482b3607c0e41d37412eac2a0318d4c8a3e40b2e543cb74b27d7a67d842f8452d3c587ae46254666e98235766e0a1850b5a294fa3980ee3a7ca0e78bdd6998f0b3e5223107f73ae40742027b64e6621ad4ba9866d1c9983780b303
+Qx = 021906fc3338dad97a51dc99ab6df0ea7ace8ebfe4b9ac244b08249734f
+Qy = 0221fe6df9297a19cdce70ceadf2f5b20b244fd9fe8be08e16057dae8d6
+R = 0484f1bfc85cfa4667a553ada1b5f365bc3ad014b229f8992ee2e82d0ad
+S = 0238d73b791b5821b5591b7c274a5f682fc77057f1b4404b1a34f8907cb
+Result = F (1 - Message changed)
+
+Msg = cbf7cfa38dd35d1b246b9516489f82d886b46a6a7a478bbf8acbc7ca9ad67a9f1b0fc85e42ec24d9858e4c081a48153fe8af78022ed7aad436868baf611b3f2aaa957abe77b54014eb53893ab5743c0b4efac0b83e4c12c55720f3618455ce187415ab698d0f23dbc79e338e10b01f488bcca8bbf83b6461d0424a6bf63772e2
+Qx = 04477b42ccb25b2f8378de7b304812422342aeefac99b5a72fc4a60e286
+Qy = 0dc131f566ca62831d2eb35642cd745f6af1bc0b97cd9c13cc0f5d035d2
+R = 0671c5111321aad4ea520b567fd8d169fdebc8ad6eae82d71b97dd26e88
+S = 09b0287967ae607075deedf0ec2589dfe22fd8d7fd332b169fed9d7a0f0
+Result = F (2 - R changed)
+
+Msg = 90928807edde21f7b30258e2164c949e7c7ac4a60875bad735e0640f913fe9da07a8d0d5443ba41317cd4cc872c5448175d2d95c9bb407dac027d29f9a82e08b8674cde0d6d9e4d43a89e61c7c5c412a9d1bfd41f3e42506b3f27e11f5c250990b6373037fd8597f10c026e84444694250f39564b02b12479fafe770e2ff7655
+Qx = 1712c14e0f22792dcaf7d1a76fd727cf1306cefe6702f92e875be177f77
+Qy = 1b3b5049f11206a1228ba6d2dd038c7dfa8c0b182b829dd935c8da3e62b
+R = 0f233bf6c387b8948b0c7f9e12928f354547f58bf4f77b07ba54569198d
+S = 0be3608d29b81b1d3185ba6e51a8ec1d2b787f7a5e3d0e5b78604691357
+Result = F (4 - Q changed)
+
+Msg = 3e56a556f8ebb8501431c0d8f3cb7077d7a006af8663ad1c518007cf3774f1129b2062637fa572e9b4c00a233cd88deec0d1652d8e4aa8adf83df17159b72596b62d105f3d72c5bd2cdcb6d0e5b28556f8aead0230f3f5404ccfd2a452f11aab9bd1adb8b27a0e6f455ae485433b38ff6ce953f8a7a7e5e096249596fcb2e04d
+Qx = 0af676069a4bf1ac421aa518725164a40a304a21b7d06b3450f6ff8f920
+Qy = 003dc1f261c6726216c3aff4f20291b9f1ffa6bbb90451b7b52efaef28c
+R = 0993dacc6b565bef33e786d5326fa5de98950d23c4a00809727d8f67f86
+S = 0282afd17f70cebf3538739e5038a374d6502c99ca75d3313138faae8c4
+Result = F (3 - S changed)
+
+Msg = 03922726dec89eef7ca00bb2c7b311833ca7e84bd7b64c4ab7f70b278904760d063e62e8f0339f4a2d735371493e4bce986c38894978cc3869f0863565b8cd30957041049fe94992b5aeaf31938caad9b142aee37cc4a0538e802a32e4140187f780de924a812224450ae570e5493f03c604703f4125f60b82c34218676067fb
+Qx = 14cef63545e96e7471ca39d4c146c5cb124f555b5b2958a7442cc28f7c2
+Qy = 0b43b9ab99d2bfbf2a109e92b502b5ca579daf6a0cf76ce33e4a75536ef
+R = 04cf3f3c51cbb6c57d15700ab100204cb7e772e3fe1decf2a714d119000
+S = 0e14b144dd4267a41af1336b0e91d7b26e2536d955fe98137bc4fb9f274
+Result = F (4 - Q changed)
+
+Msg = ce623433ff82330a9503a716ae1379b95a98e09a4aad9cf394f4860a7034b4e1bf714f9a2749e9a23eef67a3a445294ebb365e110165d8b03b9c5f044b7d26399cc682b83ad8562f688991d26c6ddddd18310ad2eec8d2c527d5e947631d759348e63862b2859d29885d7131e27d4d4e43cb27b35679745613a8384ce630e228
+Qx = 130a76ee3ee7f14d74327bd5fb1370d22c0a170cef693758750bbe3d735
+Qy = 1967167bca4892ec69e84d0340a5d534c570db67f6cb4347184dc29efb4
+R = 044096e2dc59f9482f2d56c2b86672451384fce0748c9c6dc3690587879
+S = 0f1c3a39d69bd86493a8e12e2ad88eb00bf077ebb7891efbc7f42686afc
+Result = F (4 - Q changed)
+
+Msg = 0bd992b748b62d87c08c8203f72239410c18867a80acf33b5b9ad632a1117b72abda3021cd56673caa0d092fb3ba4bc86c47620d4789cda3efa2c774304881be42c2986df3a2c3c8769a8946d571c09ceafc1fd56827c18442ded3a53747f6dc58d389016485919eaf536fd5c52e9e4c453883fe7a09354e9ecec99ef160528f
+Qx = 03c9c8715cea7e6e443fa496c1a7bc09d8bbb5c32e060bde77bbbac5e8c
+Qy = 0dbebd9ea2e53acc29178a69db9760d929a9cf02c953950a25599a92352
+R = 0fff2645537f4a1e6564836d93cb366eb60645ca008f3da9839243e715a
+S = 05046e8959c70b864d47ebb1801a1772d86ab1bcefe9ae8e5d311e81dc0
+Result = P (0 )
+
+Msg = 694b75d242df4b8e8bd770125cb496032708943355e2ea3779cfcf3f4560fb1a4a6e905106f1179de0b75030dd1554361cd189e9bf252e9046673103e5caf7aa76ee703e4d50b9250e2920a8cdf51c93c14b4b9df69439d0c28edd0766640b8f7b82d5501c8b1e093e81bacc55ae418d8e8e8662ecb323b23164159038af6f8a
+Qx = 1a71024103bb130e984107ee81d354c56b83217fdcacdb2e64d41655243
+Qy = 012666874fdb6bb2b596cc1be9f33beddd4b2e1cfc5a57011d0b9a53523
+R = 0b855f3ea51e216e682b7023492c7d8eb30b7e10e00d31ebbb35ea4843d
+S = 04d814555d3e8b6390f9bd41915c6be9272ab688fbf98f421f811c30c9a
+Result = F (3 - S changed)
+
+Msg = a93a7822dc0867b6253f0f57d9121382937f6a433519894adfacfb521604c6539bdb456b32a18f9d8f545cac693cee1575c18fd37b590b5ba59333c0f2ab91085ff73023d7c2ebbaac01b24b3283ad49591fb3f47b65a80ded38f131019da4a5ce471523e3ffcc7accafb9b7dbea41cfa0b8fb4d1110cdf0298cc6c1e43e9a6f
+Qx = 0b05596be5a71ae568d80bb89744d153b01ec8a2d7d6f13b9cf985d56da
+Qy = 1d053cf34b1f85825f5d35c5d4103420f6efec41c8d795fe625a8ae5fc4
+R = 039f0a81042bf15d2731dcaf3ed4f09a5454d671c5628ddbdcd64e6ef64
+S = 0ddee73a50f4a0a9ac4b33d583d5f04870498c7cd3b6d8b013a830de7ad
+Result = F (1 - Message changed)
+
+Msg = 96cdc7c47ea27d3fb8dc4f730a6bd7cd6aa8510f15bbec39bfb6b93226f451bf95164ae46a2941a3df455a723f9aa05d9b05ed5858c33b82c81f4d5693e3f55880ad9ffcd5ddaa6b9e0dfbde3082e51d84dc6b69f8122bf5781928ae6f6e16232925a5f0e7acbaa2e7e7e8605f0da05a17807c878724ce9f66d8aeca73e9975b
+Qx = 13fb7fa5942c91da6ca27f0e734c6198c1853b40fe45d12ce2119bc1463
+Qy = 00b389049d65fde06f704583be3747c8036b36777d69d45f3fb9e013800
+R = 0b7315b780a13f828fe297c0554492ef50f48bfa486f0f55e173f975dbf
+S = 06fb683b2be20f48003515a5cbf710c92f8d1cbb84a5fe3aa74b75641d8
+Result = F (2 - R changed)
+
+Msg = 88681654fecce3507227e8fdeb9dc7d971f9270b556162f62d9311193762e8c181f26c1627e5d25820bda10a2fe1c1a053059d53da62a67f2be07d0763493034b0632e9cbbec062e20dbd61fd32f2430d51106d4981733a2118828b1847cbcb4fe710dc469f26e8837cd4024946bf7642526827a18da82cc927c7197855d4a7a
+Qx = 0eae871ba9999523d12680d9cfeeb90e9e63ed451b65dcc6cb46e00f1b9
+Qy = 15fd52f75d25368a82da3182f655f19de082794561b03b0d45fa0a4fe80
+R = 0d2bdc26c6d8b9e500ad7611c444d16f114bc028b678d8c92e5fb392b39
+S = 0e738f4b607cc6f44da38c90028cf90ad6b63aae0f44cb07a8bd7dc369b
+Result = F (1 - Message changed)
+
+[B-233,SHA-224]
+
+Msg = 7243e6a8e966e138fac8f4a757aba92b96baaaebc05e665ac3b2b391da505e80f1e957a1e17f8a1a39756eb5b666eeb6344457e90c60921f863795a791708b009562b72334520b533be64af343c344fd73ee8f59de16146ca3b417e6430980ddf2e47f04f1b169c1de5a5932ed576ab67c4e11202a3639fdac63b5046b976675
+Qx = 1b57c565a6954dfa86a0b14787b156951fbf9e57d38decb6023b91b6609
+Qy = 10e7f602ea0af12fee22cb3b49577c32ea9aa1607e95b0c33f17d2855f1
+R = 00bd52ecfa95f6b4e3a338193aca06b6e26f5933e483f35d16954a42385
+S = 0ca6ec1f6969358a6847d99bc417817ea4dcb6f769889959d155de6662e
+Result = P (0 )
+
+Msg = ae16bc56a2407296862eaf9d95a04126d951de6513f1556eb4c2f7a3b55aa8445465a170665b1564380241192747df99e144e1d0d4167d666ae3fe663cd4f812001329bc3694e8486ed143c29e1d7613955a151537855964e3d1d44cc230d1a2d23470d249be9d2edcc21cd09696f2e258d6bb9b762218d59cc1d8575ea2ef87
+Qx = 0f66fb03145c469d8e66f4652ba46d2fd0b69933beec68d0772cc373493
+Qy = 048ddf8bc2a63e909f7e0faf70401aabc71124ece2dcd8b669145be56d8
+R = 04606d0ae4aa16786981816976e9a70b2229bf26e3f3a9e7fbbe0b94e73
+S = 0ca233a85ef4eac46ebcd211c1f96aa29dfdadfde4036c0fe94e16b8683
+Result = P (0 )
+
+Msg = a6b7ab0bdb0b964a4f8ff03bb5936fd80e6e5945af5909299b8337952a6a84f4efc8c32ea11508b49b8c618b8ee7dbae03edd3178dc504c57a2d321ba29a740022d8e51e7d85fb2d238794e3667748917aa52724c6cdacadcc47f88364cc23f11b0f147ec7148fc700ba8e10edaa976a2c2e607e59e7c0098c33b3043c6c25ba
+Qx = 0108c663d999dbab7e0e93feda239401a3a4dcf9e77197f16d16ed7a532
+Qy = 064d34c29825b92f7e279cda8adb684a2c27bae41c73e1bdf011cdf0ac6
+R = 055bf87f72c289541c2229c13e595c16b032b335d2e089cb62f2930e2ac
+S = 091b6d7a779b5c7b44fd545ac6ffc8261b4202606189d82feb91383bb64
+Result = P (0 )
+
+Msg = e6324c1e54d4c2c2595504541cee67036fd16e0b0aae7456995c0f5a56b6508e08c296d45b61d0f5c4a42fd16ed0c88acaebce05b8709ef0b0e5050984bb95987abc592ae5e8a3016c941ee78646f2a7b137b97c9cb8eb60a9d5bd4290850f45d5339a861486456ae03fb0711dd2cc09d7decdf852a8034323d7ad730a0d27cd
+Qx = 07bfed9d0ec15bb4ef10c9c50b0cda5086361213524ead8a0fc91fbe05f
+Qy = 0f3fa90f7d3d2c64e7544bc5ecc98f573987a063fc7bde66f7200e1128d
+R = 00ec3186fbbd08f0957d64440edeb6a195b3d2d1a0d516eaf88349939bb
+S = 0f162c94f32865b1f2b89600a5896cc6bbd9a2c640bdb229c829dd092dd
+Result = F (4 - Q changed)
+
+Msg = 2c7f61cc29d24432c3b61a6a90ae84322d75e6c9f14dfd7d924a7dac6d430157648cd909372ac142e70ad371b3205881fa006f3f14983ccddd7f4e0bf57ef12c5aba582f055f793efab775c026091779d89a8294795a80768cd360433b39ecd7cae3f6bc093a21d20b3fb90a5eb379b6ffeb76b103560d777ea071431c457d3f
+Qx = 1733c844ae203484c9047eacba786cd82455334bc3bf996338aa366f419
+Qy = 15c2e37144be4fff0a03f75c957b0f1a7058cc5f0986c9dbbebf3bf2184
+R = 0b227e523c3bdf8d6debdd41fd68e193173cb50bab173bde3887196b004
+S = 0b9f964568362a1c2af5dc3326d8a42abbec0d0abc7cfe6d01ff13d99bc
+Result = F (1 - Message changed)
+
+Msg = 87b16033c4874b884e11051fbbce08c97ad7d6daafc495f6ea3503326b6dcc217b34b28f470427eee75b961635f3bd707632aabee0446f6ee605156a2369513578672a2482f5c10fcda7bdb84e8cd7a1eee594e3e1a5bd68b401b94a90ffc837f511d040b49f2afe980e1cdc3d576f66aefbc7e2ecc2ffa947afeffc9fe601fc
+Qx = 077f22052638f483f29a138c869eb65d109f6a0d3da0fb9d472bc9731b6
+Qy = 1c03b654c391b23abe9c8751cee5f9d797673458d019e74e221fa6092f3
+R = 0e5b1a4331aad4fecfea03a02e9ec6aa5f20a4711cb49105768511a2a4f
+S = 0ec56e2b4f924793bc0796a8e06aa2f44e52962006264fbf73a4ca1d9e4
+Result = F (2 - R changed)
+
+Msg = ab779a94b2be05a4d74093a3481e2ad6c87a9b1304101b56e4ce299ec6144d63bb5ca5f27ec2553647945c58e5e531d16eec9780efaac043220a2bf6d1f6ebfc0d034192148570d835b06720fa1d4b99501ef9250a0f68e75dd6f99d896f03bbd27b361abefa4c61a21b5700a6853ee75f5c2718ebc488904b85f7895997f5b9
+Qx = 03ea1d537682e7024639b20c555c14cddcf82938186cdd356422ba4c438
+Qy = 13442c08bb03e434203de53af9b01d6e186f0d3fbcc6e9cafbfb44a35a4
+R = 044ada3ab5013e12cf9d166baa39f334da30d3c41040b429715836b8c31
+S = 0115a8dd2aa2cfe85dbfcad17824ff3efce339ab49155182d8499aeaf4f
+Result = F (3 - S changed)
+
+Msg = affc926eb645f29306ebb5eaa51a917ce56b3b8adff3b7ffefe4af4d07c3ea72f271c0f2b3969bc6681acd12e1713f7aa8ad138d14667de0050c78c669bd67711c21a64fc52c355b8cc50f8ea13bec7137a5938c340130ee9aeddd1d1f284db672e4f9e77a37f28554d0be1e71e215a7a28eafb53bab15e5461d05e67c242cb3
+Qx = 1747e62b14156b8da5a6f977e0ea3e3f41e513d1b2f47b825eb74e35449
+Qy = 18e73f9f22b79f0eddf8bd3c77b17cc0e19f0036b72b66cc9171b2bfbf4
+R = 01f80d137dc4106e38936f838f14250d1b3a4affdd187470ba6222338cd
+S = 008b010b94f2407649d53ee4f8d577201c99826684400ec91f7a90f8cb8
+Result = F (4 - Q changed)
+
+Msg = d2874c47f2b41a072a8896c10f5bf92a7eaffd34bbc125ea3f6cfde46007fc6b0564686690f0d644ece05978c54c319df570028475b45dc65dc2c122c89dedf6337bcd32ede39a9c6902cfd7705e83ff41add2905501c33f1748c503cf892b069dbabe6b2b8eec76f140f006a00614d0408ad4f8b21b7238991760925fc21ace
+Qx = 0ccebab719c3e7444515834fb6ce8e3443036c01de8e80780826d38ade9
+Qy = 0e4ca763458837a9067efdf5e2b5b1361d9e391dae4c42ac3a7fdf5f63f
+R = 0762c2ddff3ac06c2a78d5b6120d62eab47e8eaa09ce8b935843bee8e2c
+S = 0180b7ddee31934c85c5449359f8837acd8fd4f9bcb3115e7dc07f833f3
+Result = F (3 - S changed)
+
+Msg = 5ef80748c21a4588d4f65f563038c52400213eddc01f2975c97a6c8fdc07ceba9a3b0dae323668ffb7ac11a60174ab27354849637759393aa26689bf85f7a99d9dc58877f8952510a2005387ea3b94a4d3558b0c0c75615a5886d144a09606d336585bc738951a8d00d0d9156d870a8e45377bfdd379d594061ca2f04dccfaac
+Qx = 184a3169a750908b6ff1ab0d33d6a66ea8fec9fd3d209c9a0a7d38096d9
+Qy = 12dcf8ff71a18d2b986f60497f302d39c73dcd3de06d718d04762165e1c
+R = 07a0b412f221b07f37a25b32b4117e50af926bd7f62d77e7b61f26255f4
+S = 02fa36137a458739b7434b3377981d3a8d7c7d52ad660f2d15ce53cf400
+Result = F (2 - R changed)
+
+Msg = 4ce4f7713f08ba708787a248d8a6bf8af40c0eb034cbb5f2a7fce7f1aa76dd2b6e272762794cba5351af09ea98140915126908cd1b175db1db8b3a7dff49c4ce6190c201d326c000d552a864197d98c3e03635f59abe3aa862ca8dd0fd9b2c7eab710a4ac4476409df603d01810e031f9e4c8243fc6f8f5e66b629c58880960d
+Qx = 1690727d24272006da1d47f593a2f0daf3521e44ecd8ade5d8c1a6d3d48
+Qy = 0704e3c9be2db685228c010974ff51247d3f1f1aa3be451e12995918d3f
+R = 047865c687a491a81e6452632e83691ab07a52a5f53ce2d662eb86e7145
+S = 03e12721f962c9594160306167b1fb0dec472667036c33b6dd1a17d8431
+Result = F (4 - Q changed)
+
+Msg = 1689be1092ca3b2c1bc0a1c3a45d0c71e6695343800ef900a7b5bc06d5364282440725690f3707161d5ef44817cfc30a31f1d933f165e436367cfd3b8db617cc4c8645b471f50aaa72d473a8019c212fde067338920b90176870b2e1cbc298dd115c8c3aab05bc66f635ec50d6c47f77a4f91a3d796cc48b7ca54cb75c36b99c
+Qx = 1e81e4633e5174488130d086082a935b706f2034c31ae2b3a56fdbb2639
+Qy = 07084e6222fb541e80a518b0ede3577b171ac2d458eed5ab36b49ea5964
+R = 0de88df65c00aea91ea019436b9ae8644e35e1616d9d38e3141cbbc2eb7
+S = 05976664f5c5d314dd0eaa9ad46cef898d6a72399b4b5273a59d04775a6
+Result = F (2 - R changed)
+
+Msg = 7c61602c427e48bfbf1345a918b47fe4b564e0ed01f95a648731e838da381ae4fbbe23c3ba18805e5a3f055fe6bc86d3d545275d569375158c3a50de5ddb8c1f911cddc47924439e8b2d847291ac7bc3507eed3fc28afb3b29f7e9994e9e6a5e65233673e4d5022c46e2db916974e584eb0cecc5062b36a14dc6451452eee661
+Qx = 1d256dfda6d9733e650d2ca811064113bc9bf1c97993424a7143f4b30b4
+Qy = 1d07d6caad37a8cd00215f5eee28b280243a2c4b8366d9681dddfb88412
+R = 01c5c092dbdaf163efa37ea625817b442dbdbcc93d260d8fcf609f717eb
+S = 0ed166f03d7da32b95abbdede361a64e68dda39f30ce773cac570272f2d
+Result = F (1 - Message changed)
+
+Msg = 4923449c2eeeb3946fbd5035aa499035a172202a011bb9435c88b10f3d5db327b440d944d41f9f13fde7a531801c107b36e246c27c752c35eaa451406e00a0141d66d46bf05900db7726c16959ab1b2013fc6f4751b05f77eef80e0267d97ecdab1ab788598fb86b43aac850f70832a93045f19b3f08f2a8d92c49bf47bdce2b
+Qx = 1d1ca664ecd0c9c7b90ab1cb709c13c5c134d99cfbfdf176a0395947f22
+Qy = 1f8939dcfe4b1d009a4b44bac72bc809b9d1abecf4615649e8c06913975
+R = 0a906efd5b94ba85a7569469a507cc28103c391baba0f378161d147b5be
+S = 043e7c77785eba03bec0c2f4cd65bd37009ccea520cdcdacc8863f03c60
+Result = F (3 - S changed)
+
+Msg = cf053a40f7b715470226b65a1a37c32f068ca10258470b7cf1496654db4fe26408a6e5dd845cf7c9bb09649f3e852ce39d2e94bb5a16085beea9399dfc2500e543d37543dee82db06328a48b747ecdc2a9e0724047ef44c6d7ec6f49349fe685dfbdc3bc49d15c79b46d723e58606cc2bfba4f6791454135654f9e3b1f417cdd
+Qx = 0342c7eee62695c659c125daddda1bd8a1f042c3aa37bec98b80bdac35f
+Qy = 0ab7570d4ad5ea3dc8a3a7406ce672de989b1885d122bd8024eb7ea250b
+R = 0200b9f5c3f77006eaa7bb71ca3f3354eb9de78ecf7b55553d376e12ba4
+S = 0122183bc636b2984ebcced82fa3752eef226423805a6987c1e0060580e
+Result = F (1 - Message changed)
+
+[B-233,SHA-256]
+
+Msg = 14dca9cce04604ca01214fdbeb87389559350957b14dbb175a35c705a8969664a2138d72d99a973bfc85d95408086140588f1e7eef8fcd70e37983d1ea1e7987b2defcba6f13e50c6db72819207d05448e2f5a49d0f136acfa5d440331b4dab0967da7dbc9a77ca5ea1c6577af97218235b302b7e1f8fb07c8f601795556da32
+Qx = 151cd1573ea0e5de917effa185747517598db76ef15ee32e22a3630dc96
+Qy = 1ddf0918097dbed1897af3f96ce389183d77ba368d4f63e196410e3e4b6
+R = 08dd34c080b4be097a378fc6274c776ebf61021f3dfe8740b94e17da7b6
+S = 0404dba4f3ad89e02ffdcc9e30f751b0e4dda8b633becd75d99d04209c7
+Result = P (0 )
+
+Msg = 31747f44907160d70a8a9343c41929f52b62d1b804a58026db905b865ce28bf37eaa6824870d2d43163b502d718364d3e73363b66b1d4cba22972825aca4a6375ee5aa2300dfe29f9eb746a463b755ff06bef80338e1315fcf6aa484f8f21ac71f806ec6565fbeee68a59832709e7fb0af31feb0b96da991283f8fcde78b1285
+Qx = 0e1ccad4fd82ed18668766b88cc42ceb350325dd874566821fe6d0b9dbf
+Qy = 079f26e92b27ecf34b36c6d39156253564301e22d491b861eb150b8507e
+R = 070eafed083b96a9b454c500667d4706fc1936beb04d8660f3d04cdf0dd
+S = 0c2b4934d736345f9de221511eac69eeb6ba878883740d8f0b4a21daf2b
+Result = F (3 - S changed)
+
+Msg = 360433af8697f5b7de1348921036d7c6ae54cb48cae7d130fc4e4de2118126cf4f0e80257a1e40abe2d611ec01322ef7669d80c04d3d14ef2170f819f1fa39e5b029a2bc1a690634b502b58df982aef454b4a2b9b764303b6cf23c3f77a50345f3b57dba1974d52d1a30c3e16cbea20920b03ccf694a97cdd240411da27911e1
+Qx = 0c6f27d7811d072bfc26f2df079f1e8ff75fb8100ae0e86ab56bb6009bd
+Qy = 1c7275cae098a1d7c358a980fb0c902b06522929d126594ed0a1219bc34
+R = 0ae602ac70b400f1ca00a429749f05869da2b3c0d96172c166207f23134
+S = 013319ddff93a961703c2a4610e30ed7ed902f483fccf15520b5db37d30
+Result = P (0 )
+
+Msg = 83df74ba748adca8aa68671f2b8868462f179f2599afef4e6fdcb4515bae37b1e9267b4046b33f985ad8ac72af02ecb4c2decf1a243ec3e15da8a83744ee018ce66e6881a3f288880f488a7e4061df412e405970a5b9b026207155599ad7fa3051f339b0f522188a85ca64babe677490bba91bd5f1147f393a798314a80fa78c
+Qx = 05a751feef7932f9c0131030e9ccccbd173f55d2b0ca011aea0feba15d1
+Qy = 102aff4dd99376d423f1b49d820df10da97dbd3aca3a1a393fdc3933df0
+R = 0f9099ad19c9ac15c25091b0f6cbaae636e52701bbe9be5957de7b9f32e
+S = 042ce02855977863f2f2e4cf6f3655b388f012ed272bb29af5ecc077e49
+Result = F (3 - S changed)
+
+Msg = b0dd49bac9e30a869d828fa00d7669f3b593606d035033b6c5da9a3609dc356bd93b119961e9bdef51874652d836b18bd2517569b387b61921ff27ca491f72dd5940b4e2bc2f558d22ea7ff2a2be982d9e92e6715a0e078fd7907fd94a161f49357a3bfea2b61431ba146883a9146d15cc00199a78f896bdc87685592ffc9f90
+Qx = 1edd7e3e4462d17cf7fb101214f788951ac84be5fd7e7a9b0270ff7c746
+Qy = 1e0bdb080806c8f5af778790a9fff487c507e49b371835c41c2dca2b8b7
+R = 0ec94ad40d68e0229869473d5cb2c385be359bfb0030ae2162ee4a7abe9
+S = 0787dc167c8ae5a0708d98aa89c546448b93f0c4419ab52b9260991d0d2
+Result = F (2 - R changed)
+
+Msg = 38e732845f8c37b0c1397f26f2ae319d860bf367213801ba9a1bc1687002234ee45f30783ded466422bc7dfa1d36d6020216abc02458e4c4385f1e9f497abc31fd27a0a1eb34812d8a08413ec956ced52be483c16fa99670769629eccaaf9da9059e26abe0357201a6ac49df8c4d78cd67ba5576643595ef412981c0917319e5
+Qx = 048cb415b977f9fe531eed005217c72942a4f20400d796c4d79ff2fa77a
+Qy = 08148f826e03fa03f113189338df5b5bad3629758014550a39d2fa6b553
+R = 0483f0b92cb0dd2df9a51641502dc617dd3f4de54a5837165efd56b9121
+S = 02bb28c281189bc97bc76d743c78de394e864fcf5f7863d693537fc878c
+Result = F (2 - R changed)
+
+Msg = 6eced222042b022934dd1fe7fe91fe256f4e73c7b36b0dfd1baeaacd59642759df76a396354a61d4b9a9a1052b5c0848d8f80a0d698cfa2561ff7711ecc2c3088bde255b729432340a1888a7d7c09403503a8438d9cb8c3db165e776d3784a3803acd10c2446320f9b15939f8b9d23845f2dcf0a68adb4357498fb392b2bb139
+Qx = 1249f7554df301c3c9636b4d1aeafd479d35fa89d422452b6fe7bb52483
+Qy = 02560b664412c12d594ff0d315d5dc2e393ffb25edfd89f8e8b64fce32b
+R = 0e35dd8687951bbd934ee7e097ded8944f23b116819092aa737aa2652de
+S = 0356c3cd129828cc44964b258877ae835b38c887363515476fdc12ce455
+Result = F (2 - R changed)
+
+Msg = 7831d59ba11e3df8e09d957f94b731f14fa57bde7426dc19a55fb23bcc6c2a89659e7171b4ca92f9263d76d6489c74e91abcc9dde7ea8822d3746cc912b061b5290e8eb85629535c0f66b5a94cc8de4b23b2f60d7a0dab91e557f308b18accbaff9d9d365cf65a9c8f81d05ce5073c7deec19439792dfeb08d808afe850bebae
+Qx = 155831e6a962f9321fea3c8bcd8ab06559cea3db4b88f702e5980b1fc3a
+Qy = 0d4fbefe427565cc8424a33ddb0cd773c2c30e276400e93759875bfae6f
+R = 011e76e35c036c23a7c9ae16d20d366eeb08bead606c6c49a8b62156e2a
+S = 099b96b5f5730cdc90294ddd9da65356bcb1800f1149a78495cfffbc78e
+Result = F (4 - Q changed)
+
+Msg = 6fea571b21095c6b3a31f4f07f3fa3c0c05834e450e98c3ebf1eeb2a9dc0b44b793c6d1f46a604bad953114ed652434e5ee7c4d573d786f0e3a0c499ed46637ea93ccf243b947f4087af0d8714293931978c41f2e664a1870bd054d017d963764fd4863a59095a48a4df954f1eee49f7f2d17d795594905f5b47bf97a2128079
+Qx = 1f50b2038ce4536421c03569f27565f473e5bb17195ee7035c84c878eff
+Qy = 0462500017e0c991faa3d67bf0af3e8a6385cc8724bf792d4c31cee9408
+R = 02cda64a4c9c4fa59bd6b8d28f80e55706be4bea6fb358feb73b44fac8a
+S = 0a3a256cd449827efd8bb97900287004fdcbe0e434f15fd046daef5f3e7
+Result = F (4 - Q changed)
+
+Msg = fc237728722d9fe8d6ffa9b6db965ddf1623c3f53a1cf58847b2a07f147b93076ea443b02f8c6d6f91b384ca74b41bb065d701182e1108c1160ad0aa2964213dd7a0f256e97404fb088b854467a68a3522100d92edac4435063769b2628a6d64aa189671ab5fda7acd21fac97110193ba8dd913f4e6a9809529369e09604838c
+Qx = 09bc5423e4cc76e88ec52c1c87edc9e3e40948f956b465987556584b805
+Qy = 0083e3d67df6fd813065010c1ae7a711698e034c938daa897e4a18111fe
+R = 024b588a198795e3fbfeeb0d7cfc32c97c6abe09941964a5a1c8939c7df
+S = 05c0f4210dc5fa4fa0b25ab04aaa56bf0fb1dc84cd6af997856e0617cac
+Result = F (4 - Q changed)
+
+Msg = 149b965f3ab1674d81c5c24471f31712164f842bc87d92cf3f53fe179d431f516aa1b3b22df3e622cd873c5c719663b12a94c4b8b0c0766cfd3fd4b1ca58a0bdf118f5016fb5acb3b1baffb5264537c339e370dc92574947a531a2598cddb687b0725c3b4061a73d22520a18af18bcb528d40297026fa26ac2f750115ef2cc35
+Qx = 1bb6566399b8e2cf455f9250d3761eccc3d1a37b998a3dc67421749df04
+Qy = 1351ee94abfe7697469b7c121e86f7afb4b5be100ebb2e6b2a010483bdd
+R = 0b5b78b971fe2e53037c5b6ac6a90a9ef7735e7956bdb98a148978d1adc
+S = 0bb4ff80b3b38caafd48b5ccc4ee140d9ec17f0c5f028b8d804d5394ca7
+Result = F (1 - Message changed)
+
+Msg = d3f769987aa7ea90f50a0a3858c672a40a46c2199b1efcf657fdd14f830408626e5d1924f18f7803edf65d90fdfd9f7762e08842dc9b70febf2f0d144765c94b1e175a931c84d99a14ef70ed65ca7d005ca3c59419188e2c5cad0a41394efed55fa85726a44394e065870a64d20b2037a45553ce1862cfa733c2743d3830f911
+Qx = 00942822bb7be5325e0f0cbffe69a379350e31a7fee9500d9d28cd6bf2c
+Qy = 05901a92cb745dd6cdb76cd8c35cd6b4dfbab3457c82b1faa94d71e78ea
+R = 00d170f9a44dbfeccb64b6b59c834765f4861ad40d7724a29267e36b64a
+S = 0351946bde68c3be081bcb722a480b2b362960e94d9935035600b1aac58
+Result = P (0 )
+
+Msg = d21e1bcbc007e087f0d0feb7ba101b540ba80538014192a733a0b416530be1b444f3ef791eeae4984b5dfde6fbfcef30b83a57b4e892d59db0df574049eab30965626899cf77bc1d1e57738b598b7a7c1e8ba0be6d9715dfe7c61124af4b196150616e6331fed3b9967d5748279b100a139c1e4a5f63648a11416a2742ce390e
+Qx = 1f4b4cbb41d6740361daabd87a839506e88336aa632e8af1ae1f5e40fa2
+Qy = 18e4d984610b400d893fbcf5943a7998a1385e957f167c0f8e87c3f245b
+R = 0b6e2504df1b50e0f5c9fbda515213e3a418a26b1025e517344f6f93eeb
+S = 0aefcaf4e4ea6e9114666a92c9f8d5f4eecfa9ba4a04050c36bd916a79a
+Result = F (3 - S changed)
+
+Msg = 46ee26fe1bd96f634e65344b6fd2a44408d8138a7b47b99f55a78bdbe67e8e4d006d54e32972d939362bf1b8cb292b22f691de05142aaf30f11d42a6268c7420576094b48b110816c5012908480be9f712254ace06eca523d387309a72fa153f66fbec3c6104f8cec3e2ff2aa9140889f374f4228563724f59cf09f675f0c796
+Qx = 0d1206f262fe54d3b755439edb90f1a255d1553e797941265fbeb899e0f
+Qy = 0b610c46b025e7c492f72f5ba8f2317f50e1b271071be320186a5e7377a
+R = 07826dc75442fee0df95ed0585a90dd9ab77e1cd71a46d1e60fe9725dc0
+S = 03e6de945914e07051b2a3a6a872896ecec85389d7fe6a84dc92dfd785f
+Result = F (1 - Message changed)
+
+Msg = b4a89366074c924560ac597435aa9fddb2cac32fb64082e1d13cf26c39fc25194e4e4911fe9767e1321dee425d2e3e34f8cdb3e53aaa989a5d9b24463db4a6d9b4a795eaad237e661494d7332a0603b46126b28aaf38e191bf2b9f6b85086c5c65b741d7d39667c9afc58dddccbd706103b2635d6b5508758162f3fbce793b9b
+Qx = 029790b11fda08399b2a2344605083bae47e245db1021d7a6222ee9c34c
+Qy = 14626621fd310a7f30425a41fae66c5c6ca678c48f20049144fa19c95be
+R = 00deefbea44d10b171986f843c66174717fcfc94dc30562bbb6ff04a094
+S = 02c3d81fb610aacb33398d3744e4d427be5c5c03d53d58f397b524e9b48
+Result = F (1 - Message changed)
+
+[B-233,SHA-384]
+
+Msg = 8d4d5b4480bf600f6f4f069428b540534ddbbe99476684c0b9e95214b870c8a956a2dcfe0d62b4d5e314f8f1db8e6021a37619f6cf338f11d5ee29a813727e0813a2b0a18e7caf1e11828250e7d9d04179090f6de8f2d0cf7519960658c05f6e13a1479f3543e4cf26029f572af0902a5f1a72bfaed1373a43ef601e339e2b7d
+Qx = 048a5c8beb2c9f46e3db3e4c03a706ef08f875581e09d173f831d6c7a7a
+Qy = 0a38906d60be8866fdb611be5e3d1263032bb0bdfcb312389f58ee6e043
+R = 0877e1b7f0a77ad6639dfbb65f37ea53527a3ae03dc3508366aa098d1cb
+S = 07f5a1df84a6631c834eb5daa5de288667e824bd3c4ff075e1e6ab30752
+Result = F (3 - S changed)
+
+Msg = 91d68757fbd02af491752aa911b8ece157ed1e0b768c610435f903da3c831a10ee8cf6b1241243de6107fa253ac81100042ec745a600a7997e5414f2dccdb40ce0359827cd0cba9cca52eb5bba60f9ad988d04b3bb21533463f8648f9049d033951a8c989eed028da419c76b1330c0ae3b904b5292e9a3f82b880fa3f9e249f8
+Qx = 128bbe64650581535ccab9860c30024c26a71d345cac37f7eea0d001776
+Qy = 0eb4596da8a5b1b080ad590876f0006c991d656d896398dfc10915d911b
+R = 06cdfe7877e9425e555082c7671b0b64c5920b2b6729dd49eb4ff502933
+S = 0c09b3e9c0fba03c1822341aedde08ab70dd13e1dd2b027cd4e6e7c76d4
+Result = F (4 - Q changed)
+
+Msg = 385e85c2e92133a2a5f591aed85ec739c484e551c18a3a989f0028331a57e5c8709db582c6fd666c10ab64804b6131dd280ac9e3013a1bc025f8aeae9e915b52be17196e2ccdd556edaa6f445b8f1174e4c1994788cc1f9005e0673ac660398f0e2f55f76da22df01e570b8041d45dab5d37fb3e75358f9acf709d0aae0a5497
+Qx = 068caf30607564d5fc0f6b9be1aef78efe4412f031640f84a595ff8572e
+Qy = 07e538d22d10c522807aae9ee7240eff81f933256d803f69203ca102965
+R = 01d3f2d9970ed721236ef643d7eb299fc5ea5e3e5b7496b8663b9d9e5ee
+S = 0a6cfa065ee6385a739e16eaad801eba75e7e0393d9acb1632d0af8e71a
+Result = F (2 - R changed)
+
+Msg = bc14d4b95fbad65684e2c3f92de906648d5ef7f7f779a3563040fc9ca813d81079c2c0140904aaedb21f376e9581d101d801ea7d451042e2fb4360ff473746a950b6302dcb392640a9dbc1d5347ee333c651c0f25f76cda7c4e4f7706d84afb0cddee84d94e7ffac8d678b72cda8e082f36d7a59836c0d414dbbfeb3a0c2fa26
+Qx = 0b0875b543b76c90ffa8d5be9b2492cec2e918ebbb6301f5047b65fc608
+Qy = 0fda3417b4416fdb9f5bb3c9abed2876e6fdf38bff4b53ec06ac4b05378
+R = 0307ce2f97b73dfd06e7a219450fd3fda6f9de63934ad7c406a1285643d
+S = 052980a81d6f55af9cf28ba8e8db99298b2e08f65bdea107c683f42d8b1
+Result = P (0 )
+
+Msg = 9f75e0f86dc66ac66c76ff33a28efc866ae54cc308164841e07264f8cac6e39acf4cb05e61f39804847047aa06283bccf3941a9a265f00026062c7be17414a761931d84134068503aae18be5876f24c6f30832cb7c583c22bf06cd0f823547d633a89a773528ad665e4779f4b72de384aba9b951e5f7a8274ea586fff7aa69a0
+Qx = 0a93cb5b35d36fd65dba88db02e236a77db4d65aca3c80fcc16312258b2
+Qy = 0820bebb70aa571e5a70c861862aeac17dc5de75ef93654b2dbe0944d4c
+R = 09ef6d4caf5cb0d65aec443bcd3b9679b254b7ec43c593f7bea444a3923
+S = 09c3f0669377dfdcaca274387bd5323756da1701723065e718a0a5c05eb
+Result = F (2 - R changed)
+
+Msg = c3fe44f42e58d7127347904a4a36b37cc90bc5767559f54ac8434efcdcb023a8bb8deb2d5cc9c749ff4f3a31aff52cda42f7d4da6301863d97c27d2c4d159e2793ab93cb05de06ff53fdd1ace6aa8c3440558f7547f993d35a66d8e464c8ca29aa8d9ba0a111541b77d9d54d4ed597d045578f15f36a6c9003fe05ab762ccf78
+Qx = 1bb7c0eeac7136e3014ad778c661973d76b3b2c239ce08502d4abc136a2
+Qy = 1dd573e62e6cdfdf46e7c5ecf7042cc13ec70cf30e9f7378d1bbc270f3c
+R = 0ebf3a897d71b3f537cd9a20447ded371a491d37b7fce45e0dabdb82e73
+S = 086098ce635cd93f5e001d2fbc3075ab4aa24ac2daaf75a78ddbd1bd4fa
+Result = P (0 )
+
+Msg = 7cdb24ff860d3e2f5c2abe3ecb8e80a8834bc8b0df0c35919a568a620d584b8a1b4a15a80c21ba226bd7e1e3c993a2dc3545993de30fa94e4e66263659adf9b621bd3bbfde7e73697ade6ceb4b66db081a3142003f84cbad790a759f1e8b0dc984cf9244a7b27c4efe68f1c1b4053acf1acf296f07c912711d7ef04560c129b1
+Qx = 0d1d8188e4b0b51c4680c183c63142b5d51a2119f4c5bb41f64dac18c71
+Qy = 0acb8ecc4f438a045da20d26afc1c593d1349865e34e36a4ba00ef3bf14
+R = 01a28ae24a1109ec841b38ff6ee065b65ce1f6dfb7f8c320a347c66834a
+S = 04fdeee6189bc3b50645e498182f801a9e2077f208638af639863957c0b
+Result = F (3 - S changed)
+
+Msg = b60cce2a8dc19e7a6f6596c7995ebad272d41a6eca574ca59073fc02c63327852e00fdbf6dc4f4a35f7e8bc666da6699d6a673a48221689df443f8d038cd16c8591888beb5a8a0e67cbc21f75edead54a1e58b41a94e8872f670f86535d2195fae135cec04163ef8b54b6447852f63ee93fdc807c228869923770936cc08f0ce
+Qx = 1e27168d90e74e65572d088bc6ff63e6fda30451799b1cf1003c591e3a8
+Qy = 149ac866dde4b412653a960f08f58e5961cd9f7820421e9093ed01c8de2
+R = 0459bc46e2d9fb2cfb79ea217b0e1c4f48507bebd71fdde14946b87dfd3
+S = 09c0a8c33c5b6556c58787da1118922a2d36fc96dca18d2710b2b5b45ae
+Result = P (0 )
+
+Msg = 0f916d43642a8a858a9e01329cf2440521adee2d9928a6dec989e16831b070a2f32ebb190c890eae28befbafe26c1fd99750932b44b9a6fcad4d959960cc42ca9e0780baac4e6ecc29e5d4fdb71157ea32e28d54afad50d168626a687716e50ff56edd9a4e7e88ee387eb6df5d12da690844fddb0ee743d19c207e9f3b138e6e
+Qx = 109e868a6d588bd21834ae591adcdf95f0253ebcf1e4f54fdede5eae0a1
+Qy = 06a3859600a30303655335df2e8850a89ab6350abd715427dad9dc9050f
+R = 0633d3ea6fd06f355258321e549f630ea37f907a172929bc81c63e45320
+S = 0fab769c1f072f42877a4c2783863e222a029f1c241d53d15a9f9128588
+Result = F (3 - S changed)
+
+Msg = a89cabd94bec776ed2100ff753d651cb365d50e1d90185f9b278faffba316948958af55092dcd31cb294c02b5623099a1d014ca2a89476c832161309754252f74ad53162712fed36065110659be22b4a416aed8df0ad47fa07ae8aff198522c8d0f4b02d8047fd459abb57d7aa0b6dcf3ec524f6181eb68a04efa78597fc55ef
+Qx = 064e3229b0f62bc9108ee5619e996761c6bb0f6cc9774e71efdc1e53012
+Qy = 1b2713b973f9c5b522dcd38ebbe65021d0b31f1ca230523287143d83ff5
+R = 0fbed8ddce993db52180bd21ca42aec4308cdb6f8971c0361f855246bc8
+S = 0f07eca9208c2878ea8915192c905bbcb7a09ef830dfcb5779298def221
+Result = F (1 - Message changed)
+
+Msg = 154da53af0487bf4d793c9271afb84ad157ede4e78aff3fe94ae308bc6e53209419be51917b05efa19d3dfe8a748f974a529d1f1566118bee84b4e2fa329b3ea771eae32982d147af925e63943aebf7e648d200df70dbcb1880c945d55569ad354c80a0867e83e29f8d3a5edc69290dec283a19c96e5ee4620f7aa013d0ea168
+Qx = 1bf0c16fc313df5334fbf7319f8a182297e774a422b60441aa4f088d8ee
+Qy = 1ed9d14b9e0f35c264ef78333ed2123fb4d1cb1fcffb732c830f2671773
+R = 0002f5dba7fbe135f45b947058d1ba4cb961ca5c9a91425bcd3d68f1fae
+S = 0104b5a4326c33c208817ecbaf578453a20051025505c1366202fd1269f
+Result = F (4 - Q changed)
+
+Msg = acc7bcbaed4c2f507e15255a36c0dd4ad05fe0254f4d8078eabecf1062c0c11d29a8edf70ba6d31644d5aadd1e14844eb18a99de9a02bc25fe3502438a3d9fd84011ddb0a010b872ff70c540ba39479f3ed2bbd00dbd664f8fe10350b9a3e6c3f968a65a2a71706682d9246228164e77ed0642de1dfdfaf86775c6a4b1a1ea45
+Qx = 091fb85e4bb07934fb9d9764824bb7b21b6339342b34f6fcd621fcb2dfe
+Qy = 1e552e7415b5c40b618e399a9c31ba8e5ebeaa56d975b05b01ed8749823
+R = 09cbba60299c72a2074aa6c945ed51964cdc0b03582d305b45118358536
+S = 0408267e47edf65200c4d6ba95de6a09cb2f033f38d67030163ee9161c2
+Result = F (1 - Message changed)
+
+Msg = d8dd68c55f072151cc832486093bd93ce8419f61269e4c696201693f109e1d725c81b712c9afbd41e814049a552ce3c2b9a6d070445f9179362639c76efa2be633a4d0404547011516e1b0694dd9204e1d5f9cd3f3a1c2b1bb943c8d335aae9eb6bc8fe751f3280b2dfe568ab6a1a3070dec7c9f28b9bb879f7103cf66fb0e3a
+Qx = 1f3907fbb5a8c615af6962389afc86d1c9791ab630a9544ba04522b613c
+Qy = 1a8c260cc3b1b7a2041763c6dc8bdd60db386eb65683499041e0b4886dd
+R = 0265c4087828ce031cab67f5f77c5963ff97750d190501657d8d9d0cddd
+S = 09160d47a2fb24f21396dc4110238c58bd6ee2b032dfe64699e9f7f4cd0
+Result = F (2 - R changed)
+
+Msg = c14edb2d79f93bbcc22b89759cfbccfb9d0052a20208195245e6e2a7466100806d7ed97e6821f7c77dc1bd2c026324a21aad4dac8d751361a25916727d042a245d873058ce0a2b3d2fb4d53119bc6bfe25d062d19f28c2251b2d40a1c255a01b32133713f39ce57304924bb115aa1a313886c391e167ec1231828455c8f5e3d9
+Qx = 021871e59b3cc0d90bbc5a447e815de2b0010ca9544c1bb389dbcd4fe74
+Qy = 1bbc21ee4cd7d290257b57f91adef2891afadc327d34f5144acb7dad4be
+R = 035992165f2c64991383fa1141a9b6ffd15e68b5ab2067284e198319c97
+S = 08f04a839bc3b33b1378090b0c371c3acffea2b4dd462ca43ce75fc4009
+Result = F (4 - Q changed)
+
+Msg = 27c332abac3675adc39163f1c37b4a53fe156108b36b44b6f41e4077105821987b0b6bf592c0f77a8f042b4d29122ee01889f7d25861f9199d047efdd617ed0598179b768072fee43c8ef1891ec898b72bce986e98a3495e0776e28d714f1ea1ddcf919ac20fff105a57362551c0a2fe4d8cb359c32ae5f8d609b719bee643f4
+Qx = 16b797c6b2481fb8807e4f40ca6c7b3b4a348220ee9248a5eaca4567f82
+Qy = 0b813efe0225dd57105212c75612c7300bfbf3f7fbd6e3d84636ad963b8
+R = 0b508a4e1a1ad16e6a67db96ee4bf8e3f337cbfc2fbeaed280ebd1f936f
+S = 0939032b77a16ce8c6fed3611ec3d2c9a42abf9bfcfc737863c0685a3c2
+Result = F (1 - Message changed)
+
+[B-233,SHA-512]
+
+Msg = 7861570574cca866a7452debc199dbc8e5841388396194006dc1a55991a9156d1cc512454efa8b30fa29daf080ce964fa2b4c7f35f7a975f069a3b43edee373f07f2a9da5d71594072906c992a7eea6e37f2388838506c7785c1f955d6715e596f307d103b544caf58e8c71c604b57e30fa9e02a2e0c5cab600e6f490e47e22c
+Qx = 1cc73412ef5ee9bb62a4ceaa61f0b0ec3738c1b9bb6eb749f1a9eb92993
+Qy = 059b8d5a98defd8c812a6e20fc89b7aaf840aa2f3c2661e24c0a7713b65
+R = 0d40b25aac8d97260e3689e766e9cb3470c757982a1c7cfb4fec2432711
+S = 0a2ab64ddda5582e3c2a0d100b45013500a30a2f9b0092cf9f208e1ac1c
+Result = F (1 - Message changed)
+
+Msg = 0f5941da2b9f8115263a3e332bf013e3e11829c9f2bbedfb6ade3e052785a9e351b7e5e723d2739cab124e0acc86c2d44f32ceb7bdc76dcf3511a69be316ea7de78b2b0298de974e3feb23e0963890b0e0e5a874642ec22a055d9daa9256b19ccb00519add7218fcf97ce6582b0348a653e9ea048f68cb0f542baf7e545d005c
+Qx = 0fe994b1583eb56dc1df2fdf459547c99bdb61a212df5d9ca4de61ff4f4
+Qy = 0a1fc56a6155a7bd09552cbabc479fe0e495d762c79a1226686f270e4d3
+R = 0bd32bf317349c976028bd6fa335edbce25459c88de0e4295c913885cf1
+S = 0e74d27fc5f99ce24ae02d088fff249ad681aec823d6c72f6caa3f62b1e
+Result = P (0 )
+
+Msg = ae8e3a0e7e0cbbe33d8ee50514fb7f624b125b4be37534fce1b916a206772efbeb3e5ccaf69692a5e09fe277a9097a65b2e8a2c1fa067e2b1387c885da9b364ad3e488eddd29cf104fbffe025f0f9e1cdfffaa5dbd795286d83e3adfb91ba5512d78a1a5777918f5d268ca74db18e6339f3d597c5221fbffbf313c9df15dfcbb
+Qx = 08076abb3559bcaf54f42de0c5987fe999f02147607a7ac53b4099d917f
+Qy = 1d4bef325785dca546660629c29b0e07f9ffcecd287ec7cdee0afddc42e
+R = 09c531bfc87bf74d09af6808886fc14885be7818b6ce6a9a8636180cc12
+S = 09ba74446f4505abc59324b8aa752c6e7c7c34c3ec6077b1df19ca4c378
+Result = F (3 - S changed)
+
+Msg = e884102e08cc78a1e5fc5feb2afe701e5bb32fea061b82a5e27ce07365b9fb6f31bd84f0a6cfc4ded99657a825f2718f6c13662cb11111dabedea271d2f090d57c37102aa2e75baa91bdfeeca65c49757ed23bad4884ef339b940c6b4a2b6ab801bd902524851a4461a17f9ea6dd62af16a3e0ffbffc9bd05632a8bb3478eb8a
+Qx = 151151d61510ef23a9c206cc8451bff1c71f39358b7c62c7eab82b9795f
+Qy = 02fef05a5d45b49aa521a9aff9cfaf432a44a0c819682c016a2a21d8478
+R = 0b3fd7aaf49f7440bf925fcf3342f86b265fd923c27b5ef64b15368c150
+S = 073d0a1abe05ab0e0c281a0e124ef4dbf0055927bb7fdc994bf0ee052a5
+Result = F (2 - R changed)
+
+Msg = af05b2686ebbc573f982be8dc5e3527be761d47359893741f02ff46de5544675eb4e542c28040488358e19ef4e2e489c640d8463c91f17e32feea8f3f6f55fee2dc2eff1bb246e2e37d7685e86effb5dbfc1f10cdf93d910373fc182842cab6e539944ac15fc8e9337d9d48e74424b63820f16c197dcb2a2a5bcb52416d4eb1b
+Qx = 0767383883792211bc119e6f123c6a82d51fb811b96b08e91920d0bc0a7
+Qy = 02aad93f3db7d799e321d879bdeb2ce6e7008edb33442d54f91c6a10f26
+R = 07e7d1ec464751acf817213c24f9d967a5ab99ec34195ab9f7c9aab37a6
+S = 09c377f88e2ca3af7fbeed1a88428d58acca00043fba4f6679d8f8036f4
+Result = F (4 - Q changed)
+
+Msg = c04128ac25d88a23a578b988b26f6602d4bec68ffb860995a714f9f52751b9d1b2301588e72f49cea9a4b94a4fff8e0249af7354ee3b82a67cb72a55fb9463c5939ba92217bb218a5523fe90dbbfdc3122b8ab40b42960a36122f8cd963b0ca599485dddb4f2fd24983ae51cf0204385540e1f81064b7e23769ca3eba1915c29
+Qx = 055c90aa63841bd7f635dd0d323bbc05a0028852c7f7ca07ab1af0547e1
+Qy = 0cd81aa8a2da6e561dbda0e86a8fbf256b501f4729dcc945fab3600c093
+R = 02becef30ebb2e9c3dc2f8071dcad61a6d2e4c4fa2da7629e78c91e310c
+S = 0baef1a1f4044660ac0f06030b5eed3023fb1a115338a850e002ecc7cbf
+Result = F (4 - Q changed)
+
+Msg = d4810f16002f09de55f44133e53532df34c985d8efc260d4f1a35f148b3441fcb2dd1028e2b6883cd5275e2510c566a0b1045c985001d83c1af34b2cea5b60213c11d8b4914a5247c8c83bb348fe8ade111c251fc237fccf06aa5064a5417f2a6e3c7d0130e0a965a57d81888cd9afea93549fefa63b277d1bfa2fed82547df0
+Qx = 1eca3eef311a8bf4ddf0321066ce437e75384b6418d4bb2ceb104201cf5
+Qy = 02bdfa2ed5fef7ee8fadcf3689a84bf2e79132cf2ee4da1296471cef30e
+R = 083970b205b8ae9335ed4d2024bb51d63538cf9487715f7e3be12188e07
+S = 0e77ad1b663688ea793752e4b2025828436c1b650fb7b45a33fdd331e30
+Result = F (2 - R changed)
+
+Msg = 9e7c707a94006c81aeab34e6354a03259b57574cc4a32189a37f3fc3d60dd9aead74297ae1220e4d183489a5dd7d904db3e29d15175e1e8e89e7e4033711ad908aa8baea255be589f3196bb0c30eced84ea8727954ef80458d4d708b8dca0ecadab58b7bd18e65c84ac988aaee5e377746a82cf142faa9473728bc9e02a4be78
+Qx = 1983d4d7760a953a2316fe2cc1a420a26b213cf0cf3d5617c2093d9eb5d
+Qy = 0d18de34082f025dad15c77999f8e2dea9a4592cf8bb21931de81095bac
+R = 0f668fcfa17a9e49a054eaa97e9ddea5586d1c33f14560caed208a592e9
+S = 00c3b3e5974f66e0731fcc166e63df5ce41c02a678a8b5c19e5dce1c7c3
+Result = F (2 - R changed)
+
+Msg = 42576e118c64583dcfda31ce2d586cd673cf87684fe588b999ffe35dcb144f10247fbbfbb2af65a6ec22c9045aa0f7d7cdd4c3a012a7fa9451ef71e9de409bc1182d79f8787715bbbebefafccbf2c945ee979336d368c002c0ae4e017ebe4e23d30bc5360bc5c4c56dea6106bb7d12c0b1877f4a4a5148dac4dd7e50565b5257
+Qx = 0675382277849b6ec61bcef8b834680979cec2ce3c2988db0f3eba601d2
+Qy = 000b6674698adc29d6f84ffe2b8608b9b53086ae25eb0b5b5cc9717b61e
+R = 08b9a5f1c89aa47faf4b1c18f4b7b8ad1896f56564c21e0031d8330973c
+S = 0529d8fd216c23ab98896154a8bb7d5e57370173c92360765770dd6bb57
+Result = F (4 - Q changed)
+
+Msg = 7d3263ac9b2e5d62fdf0540944f46366e80fd3742233ff1638bfb9d4924189c30d2b405256abf6887437dd111bdae0c18e7147ecafce88efbc87111eda2b803a4c02221139068672f50eb152fdea0ab51ac6ec8f6c0edda070be28f246f94b9042f305fe4fd766db9928b69a992874b72d36938ef65dcd29b328db610bfe5ed3
+Qx = 05e2328a93bfd7e2bfce5ce216a4283997588a6966b747df1a1785f2d80
+Qy = 1de7f72ae87bd7a4da66114f40e9dcd37362c5d9a70371172316d8db402
+R = 0c8eb205d8a3c6a5d91d13cdcf9f9db16e244b93f075a0736256a630e5c
+S = 0248f46ec8ad63bb493ca2b4bd0dd32a7372aabe9bd337cf61365606401
+Result = F (3 - S changed)
+
+Msg = d28f9c7f44c68f6db7a07a9b63219408ab526c066ee0c49526da76514883433e846d6e69c617c16d1cac1133378f10d09f1b7cda2a12198de7430533c1851b93786b992746c190f84c9125e0372ae15f2fafe20f823b0c9d1aaa111b00322435c9428d1fef4ac0f27ff15f3cc646e58ef4456cc0536683d0cdb9284f9dbd5b59
+Qx = 0b6d3cfa7464d76693596775853b2cbbcf927840ccf4d21987eab1ce476
+Qy = 1bc60d1683f49a1517fd005a390fbbbcc39d4c624386dd2fec1d8933c57
+R = 0d3484a36bf916430aedf37988a41d2bdc9703f22424e322f6385a4cb8f
+S = 021c6a2923ad4ceeecec232075ac891260c9e7246aae1606009a18ede8b
+Result = P (0 )
+
+Msg = 86ef8706138fc8c8557131259ef400c6e7d01e115cbbe0a15185a59bdfd7060fdfe2593932d93dcd60d1def931200f4eee38c43395586dd49530e2dbd73d0712da9641de5dca4c0150333df73bbddd32eeb8cf5007b2f055d6700befa303b14c549835982fd154778c813da3384d7b4f88e3facff7930634f29d6f408a45d3f7
+Qx = 16c59b7b3dac7e0a5891c3dc98016c60f8b837188d3f667b47881e8e601
+Qy = 1baeedca9003ac7052f1ae73c598b26dd9c3571db762027a583957aa763
+R = 0a844818b446c83779148c275e84a73c41e88582cf0930bbea1ce7c32b4
+S = 09a30bd8772dcb70f770f2fb8be1f748eb2c5f5e1051ffed4840f47be4a
+Result = F (1 - Message changed)
+
+Msg = cc4cf5eb34dc920887bde3353d17de36489cb06fe4cc84252b43313c996aa2f0a007237d386bdbebea5a25241ea31412e620cccc9c62e78b3d8c1869c42a851a3796848e18ac42f9f278054d8088726a65931b52e9b0649cbf1a8cdaea8cacadd848f5c36804c6bbcf4119112f9db932d03a71f5d2cd9f5dfda9c9562072b596
+Qx = 00466df5519321bac519359c1d28952b1d56661b12630c83e6513d1e7f2
+Qy = 1e01be832d0b5ed14d33a0a7a32d572d1e0a66cf5dc0963b501a59c6bfd
+R = 018fedd7682ca1c28bcae7a274a5f23dcb78dc962a497d50a4df6e2ca1e
+S = 0bdaab988678e5c4189f8b6c700bd2759631a26487733546fb4fa397ab9
+Result = F (3 - S changed)
+
+Msg = 38ec537319d27e9e40d8c42a13ebe06d06f7447ef3c39db660931e9828991d9ec38cd6e7d1995d680fd995648fb7e86e47b929c9b025bdba426eb1ae0859ad32d6db3772cb1ac8cd13a0a7e2eefa00f7a77873e7fae96d8a235fdc47729c68c54d1e18abe4d898a6100f097c5feee1c911552dc03d4664007b2a0b020e8565e6
+Qx = 0555d4e7eb25e6889443cd65f0c1e7242cb57c731b061d7c6c925d9d62d
+Qy = 1439dd73d2ac5e6248f937f8dbbdea02840ea5be2d86bc9302bcc265f4c
+R = 0221ece1642687516d9b20723e321492a760b11a45c7d5cad70f799cd50
+S = 0522a2efd7c5b653f92e09f5542d8c203737acde74420c354d962aa58e1
+Result = P (0 )
+
+Msg = 69ae177179b01ab547801f301f80ad2f4ff4c61e26fde8b765cf32a556a8ba2f40c0dde9d5b67b71b29def8c373cd5ada775053b518c260d99524d8ba09c422a97947732487a4d3a6d607acfd4374516a4fe4ba1bf97dd415f39f3b776ad1fa046dbf0d7f3c403e366cd997352ba84928c849649c49f6b9420c73d2215eba08f
+Qx = 0928a50e066c9d1aeeda3c26df31850ce02c2a58672c0fc2ac5d79e64bc
+Qy = 0d6e6ebea59a1780071b569cdee762a4dc877e6078b2f2c165da21d8041
+R = 0d1f8a4240498fc3eefd558e1170fc7a6f0c54632d4d01ea02445c389d9
+S = 05cdde853dd35929179d9542da109ed91e466f1ab04f30e1d670358631d
+Result = F (1 - Message changed)
+
+[B-283,SHA-1]
+
+Msg = 2330e0f276b091ea164ae54b123a0a0d48736980a149e713d768f11b5b444678d9303cf2d0dca570e22be1cc2ffd3dec6fc8faee763a88106ba5ae296bf27999202ad03e4dcaa3b0d5a592a7905f587e3c0469b4c14e55d3d4aa9d1e5f959c7df8def820adb91481bd31e8e0719267b9621513c177db0b5e2ca51dfafd43a149
+Qx = 20c60866cedae33974c82359f07a475b307f0a2f203d335dfe97abc2bbfa569e5489d1f
+Qy = 055e921849703534ef06939e4b3a6959e94cc212e447e3f9606142c92d46257b9439da8
+R = 0780e5b0f35188c0b4c260255fb80df72911e7b166bc77ff219520ffebe0ca09e47f411
+S = 30a60b0fc3354023350613f0f840fb094ab110bf759b39cca618c1d70e7b347715676ac
+Result = F (3 - S changed)
+
+Msg = 85718480653f26ac9f6359ee8bf37a55b879802007d8227e67a856ee2a86073d3a13fb987ab8162e6e3be87bffb09a40bbd08639f776f2805cf23f3022c14581d45bf27b035bb2d8c15d8d9702f29875cdf90755e209a1f850748207b0efc90dfcd41b083dad9ed4cd50ded8f818e41d3f3c73afcfd8845f84b8f68971054979
+Qx = 1103f59ec68b62590780386465b8abeb607deb6b9279632cf9c4e5eb4a410ba39e3ffd5
+Qy = 0066772c290f700b1392675c2ab453d5f804e3fb76f2a535bf10a0a456019f9dda991a6
+R = 3abcbc2b80d69f7006d9d0ea6062916a34a666ced800431b19e0972e784d3f9fd5bbc6f
+S = 18b24afa7b04e70becd57a453d20a9ed5d23914eec86c5a3b780b2be1b842bcf4367bdb
+Result = P (0 )
+
+Msg = 8f7c80abe5bc058724d343fd9e09e3836a5815cb629bc8ab5723b0d9b52eb36df8f2b1c8b0da9fdb37e6a392098b1164a1c0dfc51c10c73ffc3e418283b0c2489c5422559235b444faa58b797eeb860a8d1f0432561e8265839b2d32e18fc5f2eddac3d8baba579b20bee10dfe2b75ab2169222acb5e10a40465ad5bcc104f04
+Qx = 6841707ae4aaf6db09b7b9824c29ac5ed340d173fcb7625abd679a9acedf9f59cd69303
+Qy = 2283fe0aa2335e7ef8affd942c370cb03b06cb0399af28c91a4e47e048611755425cd91
+R = 1e188367a3dcf45c479b776e050d1f17814bb15dcae5325c881a94bae441dde843a6c9e
+S = 11cd337c977239f267c3d78f951bef500df2fda97e500b9038ab7512e83428d98fbf477
+Result = F (2 - R changed)
+
+Msg = 7a4f90e390a3382ee7d56cb38e29e640f0b0303b68c7d182b9aeb4c15e5326d84f9023cf2013efcf3838e7f0217bcf8bb8960b866ac1f565a705ac005b7dc143582cfee1cb3637c8ce46b9b2a2331502a8fdd2bce8b010894c863c51d1c06f46108f24064fdefb19f2b4e14bf1cc11d93ce8eaa8311dc81002b8f21c2694ac9c
+Qx = 395f672634890336aa0849423870a6ac7871d9d504ac8c7642b055291e6aea10d9ebbca
+Qy = 48703b08219de8ee8a6c3653ed581f04b8e3b58b7f90bf956c501c6238bf14c5b3490f6
+R = 0aba0068fe09e71a2551eaec72e9101e72b1f7697fa1c9432d72eb23fe5f8bbffb5eb8b
+S = 1c77c6d588d04b9288f7f7e37dda2844d17ad2484c1208b8e31cff420b07fd91cc29367
+Result = F (1 - Message changed)
+
+Msg = 64faf311a3846a6e2b8ff9015d689b7e03e836dc708e970b17a5ee4d90462ce96765c5b1c1eb2e7976b4245580f5b1c12686f52fd3776d43f6af43d532a39f83bfcc8887b2c45732486d8ad7575197caae5a82026ad94124453fafbf9a5fad003faea6fa5a8b07d000fa6768532db32c2645cb611fb8ff39473eba909f7f5918
+Qx = 646618df90878e0cc097a7ca28757dfada00dedd06b1e3a9c9bbd21025fb2294ac26f63
+Qy = 48d293a93ff6abe371e131720c971fe4c0c42c1e1a0e4c23d31878b24db8d28aa0f031b
+R = 21b2008d39f99e62011e3007ba70120d72399f7cd918c2befec73edaa996eda888fce8b
+S = 07df09f95a14f3a7c0860f89da4ffda811b7e0ea0ce8ea55a67d75de31f4851c71526ce
+Result = F (2 - R changed)
+
+Msg = 768a7fc33e4fa682bb97109232f651a03f8a718dab361f8c1c0bd65d3a575e98c0aca9288c151457b819a3573dfeb16ca4f2aa861c230a82d1525285b8e75d8a36dbce1750c07b1e4d964b19640c7164599855e5d1d7b5faf9dea1987eb54e3532151f84f79a2a4afe62bb55ab6c0a21f01cc9fe98deb5bb092c89b8ee8b40ae
+Qx = 551e3fca50df3f00706d0048c0c784554039532bc63d70f38d7db969490fd238beab288
+Qy = 6c50ea43a35e9066e3494d5ad20e3b3b661273b38d336e3a710b4c763c7565b78a97d92
+R = 2111ff79df1defba76c7d472e31268a45edeb2d7d0f3960705f4ca18bd83b0a587f2a12
+S = 3bd16c5c7749f9dbb9cb132d813f37faf73356b52b4626756a717cff2e01ff98bc48bf6
+Result = F (3 - S changed)
+
+Msg = 19fceb719b751917201926f2775a8afbac4a867ebf5b3ea1c8a1e4f83e99294ab1c2e4fa9f929eaf2252949461903e3360e43a2dc49658c39be93aa707ea96ea7895f4353289f166f2a3dc8c3e85ae67f15d67078a1def4eb5e303bf23d5863b9d4496044de77c1354578694e39baf478479d136b2d6cd9755cf12fb2a5c03b5
+Qx = 336a65c8a332790bedb9d333e8a0b5eee95ff46665a846a9799042c9fccbd6b19cecf7e
+Qy = 7eb05b7fef53359e2b21698dc648ec31852e36f6308809ac815047538d31e1d86f935e6
+R = 0424e4d33600b9c83b0699d3bd59b8e05f10f39d167452f90f8169761dfec334ab8d667
+S = 05b3b73b169741390fc68483ae1b487ad649b6008e43291afe5bb5a592323d9b61c2e5b
+Result = F (1 - Message changed)
+
+Msg = 2dd1a4becdbf5b68e479dac00fe535ab79c815ca66f4b8e9d91ac929e5332110c363441a928506735e7c5717592f2d2efaf4cbfd0ac680b89fc74e8e8d7520a93645b68904f2d83abcb7050abf1f4a8d45b1952df109201cd1e8189e724e690ea3a5930727821e8d561a13831545732a1e3029c029aca243095936bdeb6bad63
+Qx = 11ca81662707f50ab806396b9c717df96f4b0b0281efbae6a8d4b8cff06d776c5a2e054
+Qy = 3537944a57684c6873731cd45a30a0478e1a170c30bd2784d44b1f56fcd3b7c5678e4b1
+R = 02ac18f8f4c965f3c5dd4dc90e3fe9344c4bf718fb32e0697d144684fa96f01506d48ae
+S = 2fb7e3e878c0a014f308ed9ebd0466630fca2b1dda0a1fcfd6ae5f98b1b8f1a8babd448
+Result = F (4 - Q changed)
+
+Msg = 3f08ce153dae9c60b59e5193ea364e41ed2c9005bbb06ab6138a06f0488d836014cd975f6e6485d2c7a6cef54db2d51f49a363b72ae457d94bb15b2ce433e03f6f73ca27f0e74ed224fcb6bdf645364e3370999bc7cde1936cc47646465f185560be0f69bfa3668b2a348c2e7f4aec3093c0d1bee3bed5d1daf34b15ab3e2d6d
+Qx = 14e9629a13844aca76c014bfce8c19359b5b9bb388a908c0cb205c5c950c0793877ae24
+Qy = 45a9008a97fbac2eab827cd790d92d6b6e24559e8eb92ea1cb57f840452a1d82b1a93e1
+R = 006f8ef4d6116f32f146ba02c1038a83ad074f386198e1d111105e9194d82b0635a9869
+S = 385e188a7771b4616ba999f938a6a03281caceaa39ad7870837d2aa5c37c7468f19f2c1
+Result = F (3 - S changed)
+
+Msg = 871fe523dc901a07310363931d3f5c64bee41634481a19c050954a95f446b9d467858dec40fcbf2c3701fae8e9720f769f8cdef37a65e361e6e2f8820e7049829e64ad03ddd793d59456d085b4554da2f1e5e5a1e30efbf221c0ce597d88d82ecea89328404af444f9c230e7c29889f864beb1fb0170d103d4e31db9e1d66e30
+Qx = 5cf8a5153fa4101ebc09669856973ff594fa3be22d95dd063496bcb3b05c37132e564fa
+Qy = 3bd26a828c21b6b328466ac5a8db9338896131c0224f3c378e30978577f76b2e0c6b509
+R = 06558b3cf21fffcb5bbdcc487f8a386bc8bb909c137fab7421ddf86d003868536bfcc46
+S = 09d2b9c997357ba8d100fb430904efab999c8baf6a04c566db9f69a079d7153f231c6bc
+Result = F (2 - R changed)
+
+Msg = dac254b0856e692ce2e5c0f931897166659cd5917ad1371b16e0403753cc880a8cdf65e4242738cd9da438affbff30f48e394b1fc2e02d841e1c2ddb56f5d9adcfff8071203de63fa1d94859c65ba99d5be5e861682210a699b348ecb06447e31f20af6679f344117be2fc674ececd29c9aa96ab5cea35a67ca32304101810f4
+Qx = 0116fb5959ca1f0b9efb63d291ea7736307e540fee06967a540c9c5e7a43019929da139
+Qy = 3f5d570bf385d1e2757c631b4cb1579cf0bbb3b031a8aec53ddb53ce73747447c7db390
+R = 3e208a35d93b4cc52b816fd4b68e6baa66b9e797adf810c43a7932fcc65bbebcb791e35
+S = 30a414b6b68d393f7656d1cd34903fe528b64b380bce4e95f850c48722c5a10333dda82
+Result = P (0 )
+
+Msg = 54f8b4c90fb85ed335ceda974a02d541e4cde64ae5af46e4bf307b0571b547ee2ce49a54e31d3266371835c0111d866e81025f8e6246cf0db6e5230228a819c55095340d9a9e2e14d3eb945af8a11e7861d4f17c34389cc11b66ac026f9c530a50ac2333b2638b65d6609b11e69a0fd0f50df0bfbe84bb06e79e93ef8a496e68
+Qx = 38db616ea5069c75b2f62c5cebfde053ff8f00ebcb00b3e4c543b7ad60f63dee1c15e48
+Qy = 3aa742a74756b2b6632d820b9ef3715557df11f1366b6b32e2c1dd32f92c0392b61d762
+R = 0fc15abfc4876ae096c8c724b2055403d334b974cf179c86b9ec39bf87ff4d8a1005572
+S = 26a9076aa3366d7695ac680a7b5581b0f5e37d2bbfac4e68d5e9c671ba929cd41b53675
+Result = F (1 - Message changed)
+
+Msg = e17e33e5e2f9956202441ed1160a63d69bd596c085ba35678bfb70b35388108f05cca1feb862263df84deb470543af75f715877f1ef3b844e1e5e19c255235c47f7db2328ad7fcfc5f7b040f1a80efc0846770b4b786c8f433515180e9bbfe967e9efd6d04b7c68eee3c31b63d9b2bd983c4d301c89f7e9cb87edfe165e5798d
+Qx = 68a92fb43abd0c82c0f448527d6afd3a930ce4d35a53d772ab18051e50d812c058824ac
+Qy = 5345c824421867ffe87d7ba2370d39ed3aedb3a92753339befc1f6b61777b8714e822dd
+R = 197ae1f39684651cf53aeb8f2b1ded319706e66ebb98eae15fc75b5a292094877537920
+S = 1c3882136b244d7208a4c35c459c098ba619ed3cc3edf2a7c35cb4e0513ae3ca304e075
+Result = F (4 - Q changed)
+
+Msg = ec53cfefae2ff9ae6bac370ba08fad0ca1fe145b8a1d5400787b5dd9443c429419ce0f8ba81b8c96239f1bdc1e9162a60c66289773afb16d1630be295ca829f3930a1ead10a0f85de3aca614996508b9d37cdf594a20ebbc983e6f8a6061f30fcfcc8694650fb320a41b7e264f680c3af6f7f7f835ea74af4a3d58b02dbc5cb1
+Qx = 6581e62861a6b6eff0cd4c3b2bc93326ee31e204009c67f4fb714c4d27c3a17c2693191
+Qy = 245ff59a6b538048f0b08b99a68699f0fb80ba3a51b6dba74cbe90ef7bf565c07301b4e
+R = 0f38e318ebc4161afa5567d972de1575daa9c65dda27e8192aac3f25e06bcf64b421a68
+S = 0619df346b6b350805b71551a854722c80ac3b6056232240df50ba2477ce95e4476581f
+Result = P (0 )
+
+Msg = aceea63941c68f1317d24516aefd7214ffd301602284a9e45cc30a8f9b90b2280ba507a6f9f9e8072ecfd0dc2519d6a4ea905f5e067eaa30b485c7195a55a44938a22de127947d65c0b1d3b18a118db9162dcf85e8067d01d45145d7567918bf7e475ad213ecfc47f95c77ee3d7e86985076e2e3b788fde6dd7beffefd06d239
+Qx = 229102f7ba7fc7942958eeaee3fb9d1bbf998bff021aa9528e9b4f63829d23380d021a1
+Qy = 27a182456befcb5860ec9d7fe3b39e2ddf7f6c505934a5a6f5d312d8da55665cbdd2509
+R = 22e291d5e1289a1fa33ebe153e3feae9439fcd12ffd01f2e0366ee8944e4f6925da4eb9
+S = 32892cc530dae376c4a4fe56c26b71432d965199d13ad9b963087094b172155ae8fe876
+Result = F (4 - Q changed)
+
+[B-283,SHA-224]
+
+Msg = 0dd767308ccf801ec2f47369a947061b557a016a71d31cb2a38a00b4d1e82f920b25df8418c8c4aa3667d4fc4d70aa9433bc63536e500a9ab191a286b05fec722f453fa23d132509f13e357a46c80de324b8e3161f770e4919752f5fc9cbb717412124841248652fcbfc3abe27383cd6bca9817e0088ca6f15bfb5b9b9dc9a98
+Qx = 4fe80ad2063d61e1f0e160bc47b1587239c7e752728b053c0c5e266593adbf9d9dfe3ce
+Qy = 1a487045a1d08f9590f8e427bd12237dc7d0599e15cc18a6e2aa8ee7e28120b2f5d9d2e
+R = 13d187b0d12b1e72c55f556d1d4900cd44c4c09d3c5a0b89c9699a39b39032988a03a95
+S = 070e1f7e661ca6b255f9ccc148fdf815ed475eb70a8ee8c45ebbbb562db89a89cc55e55
+Result = P (0 )
+
+Msg = 232eae9c4ef6a876ac648cad3057a7479a8ba34910e6b0a1d8a3bbcb5228179c73f31bab5705a4d73e9efebd83b58a14168b511ccd28c452fbacc41b9bd9c00132e7b67920a0be000c95ac4f5737be55f3f1f5eca44866b00b76afe8f7726fde6fd24e877ddee1aaa038c5d84ea105579e8a360affb25d70a7f684f95cd9c690
+Qx = 7d37991831e6a498c903678765fd3c3f5aedcff2515aa1e640b566218c1d36fe55608c1
+Qy = 1a8c8962aa50146d6af01746c08392e3cb1abf6324b32a66fd4a0d571860ce52bb7ad61
+R = 07903ce0d8b33d6bdb3a1cad5d0b8fff9d71d2e21e05897a33a62cc004c6c27afdfc6aa
+S = 17bd7587de265fbb65415a5cdc5084c275cd51048b98269c8ac5aa5d642a2c37971cbf3
+Result = F (2 - R changed)
+
+Msg = 8b461bb79ea2157425e73e02e27de331fac2a6bdaa4cb27cae8715b0986ff95f3ea1d3b3619db835774f21cbc3a2448fcf18188fac10af29c18ae91567e0848c9307d7f982325de8c9f62181058d762d2e3284b603d6d786a2664cd54c742de4d07debbe8d9d61def6ce58747f4e17b8a2163bc0c3738c769f02e8be4a420bf8
+Qx = 1953a05c75e5abd743f3072436aff1c9ba5afcbd2130a37c2cf7b8dd79bb84034d4cf41
+Qy = 253ce1bb02d7b3cc000915ba029d9087b5498194153abbe855a669466f20934da55f0ba
+R = 3932916b41ece83900d95f153ecf1ff1d314199ed854e34b7b77118bbf46d03d7cf5c45
+S = 372cc3cb9d47890b60603aaad010ddf85fe0ad885fbf19b3e22a9843bab30456e58c590
+Result = F (2 - R changed)
+
+Msg = e5935c2389dc8eb6dd66956f9748f94355062543c0f590e4504dd896dc3dc1220624a1af8cf3f54ab0532600f7a110d1f89b9be155557837bf792360df0dbdef16b0f70ddbd2c64cc0f492dd83634ddbaafbe435e61647fc334875e87653de2c5cfe9b8a3a7fea4c336507eb0086d8c6386217bbbf322c6973f7d956fce7bef9
+Qx = 25c245c06fe462fd06705cb42fbb5f027ae9ff79d86669cf125376f4f38fafd939ceedd
+Qy = 632adf476bd68cfc6ce28927da3062ea95032bae9cbae501b078e5b11c6a86d052828c0
+R = 3e43f501039c20d78d0cb014eeb403a37d7560565a9d560dd1bec74142c712ae8d41348
+S = 29fdbb659ae300b76cdf7777410d49e8f260bfe3fbff8567cb95545bd467fb289c4427f
+Result = F (1 - Message changed)
+
+Msg = 62239b7ce4c645682d65d7a830509aac5d841283ecad956d183d92683f4ec5a90afad5ea48a8787f52653c270e83c0771d7347b8c84d179dcd3ce87d8d7dc72394b5d54c9dfd6a39f172c8e99fe8e769cb0844e67ed300e810ac045e74aebb5fe8da6a57e6a3e5b91e487507c4458bd4c7f69e931d397c95ee5cfd065907f9d3
+Qx = 6f53635ea33bc3b19b130b33e0cae43cc23f62bcd02f6d6bad942d4ae907072acfdefd7
+Qy = 1bed7e1f61ec1ae56227f2888fa3c74ccdf057b09a010091640f3d3a8ee686d986640f4
+R = 36c6b2439d46b9807a43fbdf40efce6237c03acacbe3646fae34a552a07565dd0b3e349
+S = 3a59e45c32cd73d988a9f79a10d8fee69d4adbdf36c4b69c322764c4428be54d612eb19
+Result = F (1 - Message changed)
+
+Msg = e47b3132da51b40f6289525159777d35dc46aacedb1266ac2c631cf6997fc4bd5642500e6b8256d8f2cf90da39f199e5d6ffbce97d29ff87e494107331ebfb8f2574ebe7b01fe802d939d7ae0613685f4084c8e3cecd7453fe8d75dec5933f1151ba3eca6e9d7757df11241578d31120d71b7c46ec74cd04a1a3710280cb91ad
+Qx = 5beb2de53def238ad495c84a72166107914606bc508d5c81d4e50aadbb7da7c76f3f9b8
+Qy = 00973f417f672e0a8305665f1aa727f5a90de4e77e62fc18aa80b988f148874cb954e53
+R = 399fc0d8030205035262ccad9f40badff7cef5c368202a3b463c4773d1c056083cb890b
+S = 25ab4e66374358b38f48b470530114255ba1e5da7b3c320c2b8d9c147c04049c77dc471
+Result = F (3 - S changed)
+
+Msg = dc880def1ca8069faf68bda88287d7e174d2b9633519185e6395c83d22c512009c2a42f8951d1ba98295ace53ea0c865e1d3fe39b65ff76b459020ce88b807aa3de486e42cee59d25e9f1fe4af7b70d87238b1b092fae69d92213b6c7439fab292a835d3d769fff611872873bc844198a8e82674b7f99b1dc49f32eeeda140a3
+Qx = 0952a8991a782a1bee4ee03e068985cf98345ab4cf1733f294698f9001be85447161f5f
+Qy = 6fb7d4f06dc9c9a2a6f130c0917c61e30b24eaac3e9b5a40b4145f8ea202bcdff912094
+R = 32d3b0e4270098d167c387e9f85a48ff86f28295794664b7738242e6c07369fbecb5f79
+S = 1c1505e4911e0cb36fd473b4938d32c26413426265a4742e00b3585d61b63a643320e24
+Result = F (4 - Q changed)
+
+Msg = d87a4b312a6b3c02e84ec59a1b146d28f58fc914af07b631a55d01e22d29c4039f4c27a88c8cd416820d5b43b64340fdc4d5f8cf33179f52514f5c99300e26dba2ef62d1ffb9b6b055facd3f8812e2138612d5ed6d327a47098be37100d553b79f75e0077c27bb94a0274265c3e62090eb7fb2396145c117500ae4f9fd05cb55
+Qx = 6b3b7b8555bd3fa0ac4b11793b2c89b6e4b34abcf7541cf48d85377dd854e5b77448018
+Qy = 16e3854caa9e11d8907f92c1c4a36df08eb642693cedbe34a8d9c544b6ef65b22cc0f71
+R = 30cf4c508940cef07bfeba616f3e752c93ff7754a3e2f288f2e7379258ba402ea78b3c3
+S = 3b0d752ea3f703ab2046166d3519dc05fa1fc01d061711a06de759968f21dea563dc5ca
+Result = P (0 )
+
+Msg = 1a0cbe202d1694284c33217eec24fbe8d9c528ee346f3c4cc04f7c632bba1212dacabf5fcb665b49f255d8a300c31f501b1e19dad437d19d7be28e6df961b8eb905ea3e6f17d05094ea32b081c4327e0ccc5b76ab8112ad723c1e125391efd72571447af4e9a5b5ec92febc4918532d05b39d8f15813d2ea00ae179845082a81
+Qx = 2cf1b71ff037631e77ee4a6348d53cf7cf7defe9d92070d68257d80c0121eac4cb9b011
+Qy = 00fe74925b64f64f47ff7f56f17d494804619ca46bf47200a548dc112659973ca448b60
+R = 361765d8f61a47d8e00159a18431f9b29d9ec5424027b64d1fbd0e6d9efaf25d8dba9a9
+S = 37d7e179908192644b801c1c639cb2abe5484d7553585b71cc22eb5be1c004d6d13b1e5
+Result = F (3 - S changed)
+
+Msg = e549a4c90ddd2c4484d5a5d7ef014de108f9d5bad038c866f759442426b08ef1c4b52e3a2331362a4b7a65b5664eb2b2fe376be3935f19b2c799338577e9e80030f5bc5087156fc0242bacd2edaa2b5db58c23a096b1eba29ccfe0e36e97f19d647a5748134d00b485f0d62b902da9f1d3eb532ec77351316bb2dd3a2d1caca6
+Qx = 2cbf311d011dd20c7619c61bdbca06ab6490a567d455db264c4f1e29005d31bceebe3a8
+Qy = 54093852a1b57df1d690a66c1c7a9f7624e908fced1991626ea2a665dd56b83d5e64cbf
+R = 2905007ce59f216fd06d89cbb50efa3c44d3753cd5f5d73696bd1e4558da213e811829d
+S = 1b5fe4b24bef35d0ad982ff434cf1510ac11ed14f0f52e488f69443c4a84c9cd51b317a
+Result = F (3 - S changed)
+
+Msg = d3b98a8375042487ee8a34a84c011f4afe2345c7b6d45fac22932bf42831d16f6afa72d433b6b0857d0015a2988635f86cf90119240537053cb893ef200ed8a5ae457ff47d97d3ec97d0beea2c9e14a2b79ac38f87dc1383ecae740423340ef48886ac453e9e9004d233d20472cbd3075db85d27447bc69a7bd1af1bfe476a9a
+Qx = 522af09657ab212c6e5fb54dd0c78bcaaeac381762ccb163100b1c1397daa47c7544d9a
+Qy = 1f212d2b88e08535d89d75e16c1c966ef66b13675cc47d7d44306f362456fa19ad9ed30
+R = 3c868b0de0cd5273bcec0e9c2389466ce5d64b5e9f680a0d88b9d3e2adfd70463ddf8a4
+S = 2572c096e42b73dbc43490ee340192b999212abc506e51c398b0401fc902743710acf3d
+Result = F (4 - Q changed)
+
+Msg = 6e89559a324d357ca94b9f5c6aeb19242f8f9bd4b685769da58da2aa3365fb4ba8ac7fd38a44fdaeca1cf91bd2ec391d2ae9101c13c324a889528cb4de1a4a5c0fa13b617c43d2bb107dad6b7ee9eb74ce8baa85e9915531a9b5d021ff88a781256bc15bb2e13071d52f909b6310329b75cee8f3866f8721cc0d5c671c30852e
+Qx = 15acd6b7d702e30525eff0019a7dd914addb5b587f92148ffd5c093a09c7f5858d1b5a6
+Qy = 486b3c4be893b13ec566ccaf0e47ac6c9ffdd22136607f86efc1b52f8b2d2fd0723b16c
+R = 3adeb83126621f06453b2a3db66177a2d4ee2551c0b4868b1e16b0f9a4fccb2ffc3064b
+S = 3eb959c16bed98a025323a24110e8ce92f8d9e7402333c845d3dcc108fe521f6fae48ef
+Result = F (4 - Q changed)
+
+Msg = ad524aacf0c5ffb941c9e95c43664f557ee85471766ad07c8a211c8555715edfe57491b83b0176d7943da8b1f01a4ffbd2561875798c1275d72a0c669bbff61d740782bb7c4aab4468d8c4d5f481e43b201bc6e4dc4f13228e9d46044061c2609e4ff38086598b7dba6db32e1b05d9f5aea1453a234758c9e06a97abdad64878
+Qx = 5d65c31aaccdaa1c59e11e9f8220efac7ec63cfcf9deef939b380bc23d8d05a79a556af
+Qy = 6be9b5f0c642b518f2c6108073d2acbef804e96752b6cca453514b8610ce09d2822e4ce
+R = 38e9e684ff5d36ad0d728f047c3f15bb54ffa0ef278e480a666f1b1dd13e5e4dd67b911
+S = 342101bf540cb8594ab0f09c2a036a12cb8faf1ec866bbbdcd9231fd5875693b2174e42
+Result = P (0 )
+
+Msg = 86c5a7d5bbafb154ebcdb2cb1f273de430255bb33df5d8dade71f891d8980ead16a54e934317c1ff59979147e6f24dc97206bf8dde85b87afead663f98f5f41800e0ce7b57301117657fc7602fdbcf9eb20f0067e70f953b0f87d7736f1fc2ab4a3fde9829e46d48930510ecd28a3c0ad69afc4963d4bc8449661549414f9763
+Qx = 71f6c5d7a1e58a377dacafe30637583e7e4e0dde7a4e105836bbd8f8db92bc00f4e8a17
+Qy = 7c9fe390e370560aac86a4fe663904e3f9b20e85980dfd0ac226ecd076ecf4e15f4e593
+R = 124d0db4c170e12900fb63d9155993cc89d82af3157683a0fc6838408104d1b34070215
+S = 1e396b6854c5dc16d914caafe5e4f5191f1c0e478cc9fde2712314c5b36b5350d2a9bfd
+Result = F (2 - R changed)
+
+Msg = 16e74feb56a3604b61dc56036df5a4cc82ec6a9d75084eda881e0c163fb463fc2614f8d412644f25ca818a016e5d18c6edea0cc4a97af9ab9d6b9dd23cfe95fea09fd0989cf4919650c706faad0f4c998627b793a59e704b1b419074331e572cbde2429a40cce3200b77717fc5d8fc1f135691fd43688ec9318ee43ccbaf22ce
+Qx = 524e7aa93df1ae5f6471789da5d7484dc7033289e26468d9ff33be38d13e469ec4d7a60
+Qy = 07e4622fb725d388600f5baef2dd3262f731b8b83a9155909a8e7a9f6e8e65f8e59c092
+R = 14f64f7ce645b5829615dce94b3de9efeb04d0a6a69af6bc17f5708d2664b4ac1544c7b
+S = 334e6c6f3d8bc3b1bcf6897406be2d4212567915aa6708b25e0d75b1a9de56d6a8f1f29
+Result = F (1 - Message changed)
+
+[B-283,SHA-256]
+
+Msg = d2b50c380d65ae3a7d51dce08879158893e211fd1dfff9257e0fc665510e97a665233889f052d2951545f26540884bbcfb9604c677c2ec19db0695911859ed96479605ba51f7354018f2e4a75dddaada8bbc24bf0fa992532f2a369a1b8c63b13dc696a5c1fe656786a06554d4a5e0901d0f2c4ead6a692c162578257d62919b
+Qx = 1fe136787469bfbed60b0939a49ccc1846e767671708686ef45604ed2d077b38ae53867
+Qy = 416aa765dc5cc2f32539f77c3d7d2715c6a20753cb6411c96347c0d451bb1af33057f10
+R = 2f90683f7f41b871bad9a0b5fe58c40f1cbe391134b5bde2658dc4eb766051da8b63735
+S = 1dd10fde799b187827d86a750ed64f991520efd137181f95234fd15734d41e8499ef7ab
+Result = F (1 - Message changed)
+
+Msg = ee0cb76f8107836222bf2cab38f9e63189a76737f1a3c0714cabf18115f7548dc8db5e3029e321495774d472403c94584bd11a8036a4287e8096f3871b5c0b37426acd5cba6c65ce40e1e71d6c700acbf4d59e01af59f48f465cc7df46740131ce9b541e2576d08e29ce7e757a6c5b4844ababc46b0d48a1a3d4c618aadbebbf
+Qx = 6f2d1642bf9e9819f1a35960787d1bc3d83ecd7fff2123139fd03d8110a086c7878d444
+Qy = 578414d960307b719a76841147b645b4aac29bedc3702995084b6314fb80b9324f19bd4
+R = 33299bc17a7855f2fe909304b5bf6424e66699f360ef823c3d9de213635e3e929fb5e65
+S = 379040cb6191352cf75006ccc87aaaa6f0ade2aa8d7bdbecd03f65832f8942f48b33a23
+Result = P (0 )
+
+Msg = 5f663647eba953d2c9b740684770117ad174ff2fae6b76c84b4d8a3c6c709b678548f82a42141b598bdad06946537336532d36e8130a503295ef94619398865566f93895d1f3391148e711799190acde9c6e34355dcd1dcee7fd0612a3fde42a8270fa4f09be83d06b8ddbb62f21fcbc8a43f388edc8e801d770c34cfd4fd3be
+Qx = 704854a3f8ebc1f83d13f1be9e5db37ebb53b090d5e36b1f54ac23fa45f68d5a4688c80
+Qy = 0270e6166ad949697be018dc985368014d3bb73f3e67a614c7155c74e52aa07d208f750
+R = 056042dd4b68831521cfd60760a7315cf13829a0945fd8fa427b5839ba8107489e60252
+S = 0e00e434c83dc8e0187d85a9f9cd03b47c53006d523c581578caa498fc7d60577e69eee
+Result = F (2 - R changed)
+
+Msg = 3c66481ad9df0159110f5eafb2b9e481eae134e184f16b9b331bac6ebf36181408e262ab2f91490c7cb5afaa1c9aa169dfbdbdee7857d013d27273118684e84b83e0ee3896a6615770984e76f9e8b8b115ae64c92fb246de13ffb776fd093b28289149fc2fae5c1252814b6c4e6ec3dd5f4a69d14d9ced4f95610f8834409b69
+Qx = 3a79e8b9ae4c9a9746849c57f35dd50154173844e358028ae8e0fc19001deca29abe98a
+Qy = 7f7ef402276cfba1b8e1305884d06ac3faa756deccfe3556e10e724768386e236a02009
+R = 39d910eb526eb0abf5322a8351f195ffd0a8e0e09c53e006a0bf991ba15a039c396fe4a
+S = 2f087af0e5d5b99fed98e7bed7a95a53ccf1a5f11ff082c53f60502d35defd339164d71
+Result = F (2 - R changed)
+
+Msg = ecb2be93e566a69a3586c546fac0e8b378e706222855a1b25d52797e7d3784ada91acd9b6f0497d0c4e1013f04c97aa100ea6c3f461d3233ac7de528fce4a3cb5577a021ccc90c1d51a8aa77fa230f19ea6dfdfa42e9462a5f8c05803ba9b5e15b875619b8fb8621198c6db08fdb608d9b6c7175cad71c4b63544bc249584a99
+Qx = 79ff0caa4a418e4cc35f9f1707809fd2f5d1d551f7b1279aaabb0361ef546baa8ca5a72
+Qy = 5c66f8fbbd649d205a5b50a9e28302628d08698166c9f038270431e624360652112a1b3
+R = 34e9bde1315fca64324e1f574f278450238924b19413346d4b7505c24b4eb7d6a287f12
+S = 1c4ed810637d8745ef742231bc96bff95c06df31b7cd2032bae55750668b9309cf41d65
+Result = F (3 - S changed)
+
+Msg = b92e4dc45e0186df192238dad90ec5631d0d84d7cdc200c6377e6cbfee40bf4d338c978217574df4f8f5c531546b8d06f82e1e2c1c936b225c3c62fbee89e5d9b1e70976ca1253f38d64fbe6388c9309b9436c49dcaf6969996317a058d99a4b87b0d4be6754342cbf6dc37cd1b8c81035ec1b38090fc2e40b77ed15556101c3
+Qx = 6d3fa2726532e66844cdd1fd502a240d1d5f76a50001a9f5a4c4b3efab5af72994e3576
+Qy = 4832b71ce0199c4432c6dd5cdaa405e8e4731e0c7056c4df7da14d00ba494451dbe6c61
+R = 0d0305cc32fda18c8c06404468c5cd95fb6aebfa72baec9c60ed91ef8764ebe93a250c7
+S = 2b382de9d7dce6fa940a57d67a3e4b40da067677c2d248b0a8367eabf350cf3612d85b0
+Result = F (4 - Q changed)
+
+Msg = e0b912c9b927053929d90d8bb234c7c0d3bf30d1b3912d98e6a530a1aa072412c90522bc4d34bf3134637e8dd365672a2b95f754a07a9adeb69f49da381e6b8f73892696b51b97a0dbebb529a24c479adc748c25b81535505761c47bb5ec1e9f44ac5300cb9d3223c795cfaa0a4ce7ba4f251beb87b9bb4130090d5308cfa9f1
+Qx = 6e7dbd16d4dece0019a2b0385842f2fddf714a3a2a239bc542c01e1f09609d4c843b874
+Qy = 797805be9a986bfba846d04ecd9bd19da4d5b68cdd9ab8850f4b7d0158de49da6cb961f
+R = 3078b8926b89d197ea0d70317e06772c3c1f0c306900de3c2f0e3880f2ef8dbad04bbbc
+S = 0a8eaa21596fa3b23e6ec3829227a8934158f6df5a3664bd2c642c1445bf833626c6676
+Result = F (4 - Q changed)
+
+Msg = f13a89d933693e27b5a5e237ae54f6ac961de123b3df658948dcde807057b16f1aa20a84dfaa4548f3432d46a1baa2e594485695ffe1200c902f95e766d5cbd8cf23bbaa60db471e6648674e81d300f55a5d25ce5557ed31f81275033b8da45f65639fd45f11ea26a9a2525f760db9d36e674c1e5362b34909e6f1ec78805517
+Qx = 38403d4e2bb36546a6f520312ecacfcd1670c3ef105d90e6883c460476b4ec778ed9dad
+Qy = 5f3ca4294b3ee148fd02e99325e6cff56fe1d98ebc1fabb1001c553a739770eb48768ba
+R = 1e6b75e5759f50a6646848b64257d0c16e1ec05741384f7291b7baed8c3e9f6d13ba749
+S = 0f1030cf9d7628eec62fdc61013dfb18f95e3bffab5ee4aff22c0971cb026cc3dd940c0
+Result = F (3 - S changed)
+
+Msg = 035025e1374d69a0a66dda34253221c75b2374405643949a12055c0d43a97b843107354d305715e011712c92bdf4c256b6e2ee49f5094b6334ab972d04745955cffbeb6ca2b026b7c55ac80f492b38dff524e6c718144c74adb2ceae525a7265642422707c5f83a25060692c33a7ce0d6d3101b98ad6eda51580e544fa834aa0
+Qx = 0f9b7ba81ab38341d49231dfa90ee7eebb6c588dc559d4cfda9c6f16fd26d87ddffd5f6
+Qy = 52a6579c505271bdba277fce49662d26774818881207f526d94293286e95e515b608f51
+R = 23afa97f50d157c69f1e88dfc8e08118177025205b813ff656c3120b2a624d64ee6f829
+S = 18c66f46dac530916c4de364120f00ccbe070ae29fd7422f7b53c3bd8d85b2fbc5b9df4
+Result = P (0 )
+
+Msg = 4cb62cb8fd3ccee39b10e1880548bd0fd1a01d67909b7874f0542701b85359518a75a7d8a2509ea0af604c36bb3bd97243dd57c0f33c39bd499b20e4b4bc74d1915fbfea26058d483c04056003ecb0cb87b3ee737e496dea9a474518a87b735374fef05a98fa05a5308ff80705e871160f3c94b4b612c1139f310d2b0352fe26
+Qx = 055513c60f9e4877d2c7c35de03f273ea7185da3748a5136ac11c1cc13527f263b3498d
+Qy = 47b6536839c065b958ec7ad6fe93473d768206804beff1d9d76a4f2d1be3d2327281aa3
+R = 1e0d32582fde6c833182bf575b27689537bd7153055a3362976abc673ecb93d6bcbf97d
+S = 33b44fdbdccd0875f632692fb87bc9992d532f41c0589355b670dfaf9be148418c327c8
+Result = F (4 - Q changed)
+
+Msg = 03078fcf021ef121fb16f9ff3a70fb8d2b7b331a9936cd79f8a19918d61760eba2145f6b74baababeb59032dccf7efdd81a0e5de15901469e261f4383edb9fa75116c052453d049650573856caf6df9a4948eab4ba40cb0fc6c146eb70b42a517ced40da34825e91b0f1e4f1b827f801eff645768f29d8da6ce843131d6cce1c
+Qx = 15718dc8d8b9d0228b4b30bf957954c521cfefe91b5921d2e8b17becddffc16e8433f43
+Qy = 0150e6d0daee8386f33dbab649843b387865d4dee102ecb1e8a36b574b42a9048841d0d
+R = 13f33bb7b6a9658947f9adfa79a0f05940029a9a82a027341776d7fd8767f3eb104d796
+S = 356f1d70ce4c739eb1853f90a5c5d105c7f18685297440f8e3443ab72cd1da9e8e52817
+Result = F (2 - R changed)
+
+Msg = 13058472dc6e8172734ba4e6bdb0c43057ee304c07117cb5349c88f56cc32ce115b7a681b0fb952da8fdb0f6a999dc50812371131e3e88dfedd1e1f8d5cf50b3bfa11ac5d7af094d5600bdc21c603bef59962c07fe1be6b88c0a9948f9ca1b63c8ffe6da43692bf07b82d11ccfb24bc6feedf968b7d3fe9953a2fcedc6b6fe1a
+Qx = 765699660705b006ed80e855c011a43a53f30bbd2df9cb7d83dd4db16fb7f54ecac5c43
+Qy = 7e88a7b166e127961f53de1006f10a7bd20bef7bf6c0224c8ed782a6759c5b3d0ee927a
+R = 1594d6a69144bc3eeeb1f2d82b3e4c3ca61cd6f66213492fedbbfe873bd22570d2bafff
+S = 1bae72d58bc3616db21600b3045eb89912211805a1209e4d7e5f29662dcedb5febb87ff
+Result = F (1 - Message changed)
+
+Msg = d65ad6512bb347a12ed5308a20dc2eef3f96b5c258acef8dc2ce3898ab7c57d666aae10aff4d28db8d35d9e220b9bf62dd346b37b9aff5370001a923914ce34b55c86ed970aa73cedc66a5c53b56ba3543fdbc39d0b6830f15db9e5b3946f87b10f305d3e3b11d819ffbe228cb938c8ea443ee0767ae1f8d9f5adb438824afa8
+Qx = 29ff10503c81945b2dccd48568d99a39cf7d78a54a216f77cc9da0aa2a49bf2b7de66d8
+Qy = 56cccc401c239176b70a9fbe137903d47f2382c440adda27293921c7dbe4b2342a17a68
+R = 1dc6705360e3e406716e7450731e776e9bdf073e526b036850437a22b7cc76261f47154
+S = 2a28ceda25288ecdd8d9d5248004c5270cdcd6b8a10389eeb29483e360cbf5810da974d
+Result = P (0 )
+
+Msg = 7c90c2d6df7a5faa10a1fd37d49539f75f8186d654f61755026623daae9aff1685ed4fba398098f14fcaba96ea38f1a4fe9cdd568b1dd0b9233acba7c21617c4dd05ceef6a7c12dfb18c73ff57eb0415bb87b15cbd0d842c4cf091e50906b3c16abfc09798b4a3ecbc0f0279744cf52b4eef4a555f794613ba8cf1238cd11316
+Qx = 56aedccfc260bb2bf4c30654d7639f495035d59835c5063451b8b313523ea579204291e
+Qy = 2d8744cac3461a0aacf04d7d4ea7c84277de0aaa7ca926da282dcdeb2c9b8b939fa11ee
+R = 37842f1c9c14cd89842cf35423f14dc1ced260f92340206c97a74ca051a90b44aef0635
+S = 1e22101b8adf5b35ed8cdce05552dc136c1a5d478967e04d7f00b163ad0281ad24b2015
+Result = F (3 - S changed)
+
+Msg = c2aaa9afcb27edc33302600b1aae24d9200d38d45e7956267bd9cc8159ee4b4e3dc4cf857752465d0d40449d843e0a509947ef69b2d5313547e0fa619ec34c699cec0fe28dee3a7fd7865bb0aaafad73a008ea8e96c2dd1f41bd989a2ad8e82adac98d5bcb606540a9b82e55130fc8a623372e5b77522f91c5d72c1d03d7b2ee
+Qx = 4f967db127dab2c25c67987559682ba970b9cb6d8d6d4d41111af55623bbcb1f0bc2a8f
+Qy = 7e4347e25ee884c2dd4846c8ec3bea50a0fda880502adf9abeef173178076047a2ee585
+R = 21cbe19e0d15fa88e4a280044d33b8d57fa855e0a91ba61741d194fcaa94d31be4e5a72
+S = 1a1734259af5dd4a74337c41f559a702b951628e080c33565cda65d73b70f06015090cf
+Result = F (1 - Message changed)
+
+[B-283,SHA-384]
+
+Msg = 0cad10ce8aedccbd65c5ad1f91eba1914f3f527fc7cc142d7d82ea460df87bf274135d84cdb139838d010d51519a42808f8bbef6eda9187753d6f935860d25cc627435bfa14a928fe1a439a379c079c6887ba3b884044308b3e11831011f6194e83d7d7b1e8e94403090ef42dcaa002aa335cc4363f65af7992e9082f5711c14
+Qx = 01c1035bdab52d8e73c00778e20e4c010d9d6aca680256608bae0ef2fc59cc444a2902b
+Qy = 5f50d87cffe65e11e340c6b3a7a1d36dcd78ec00acc697116413fbb35e3d23d3ebed1f3
+R = 3e3c1a2b40487faa8e07a020920e703df486ebd1a5b5efeb4c7b697ff2deeff5fd5628c
+S = 055dc20bf694448c1045bfe423da1ad0bbff7dabe3afc7117eccc7028e1799c0204f81c
+Result = F (1 - Message changed)
+
+Msg = e6ff1637c6bfe72475a086fe48ba77b970b566c4cdbeb74284018d00f28003191cb6a8c49b7fa12c945e3e00d5b858ffcae96f8ebfe057a5e0587cdd1b623420554fec383b654e5b41b5ea9f1573949bfb0c0f436aa3352de4653ec71614f78fc5bcc6430c4bb732bbf11e44be86fdb4c45bc562a5045e26cf13fb381540f4e0
+Qx = 7d4f2e5b2bed6336654d02a219bd0c7a34a3990f490d8dddfdcc20fe27e55ecf296aa20
+Qy = 20aed46e1650f52b18784bf847af5ba180ff6b83f9048e11f8b18bb59bdf0882158fa22
+R = 0bac571e4de7481df0236aaaa6b83d5590497436a691eafa7d59ecc687d1dfb14c7bf50
+S = 17255b13f74db2cb67dbc5617d8cfd9b877afa6d8bcfc675cabf097f928a7bd96740200
+Result = F (2 - R changed)
+
+Msg = 09cba889bf8594fcd57b4e10a8be0ba2628a9b904bfdc38d41617e30298ad447e4b20a14b37334ec791ce251300edda4b4d73a22d74f2634f2989385755468685ff1ecde957ca804ade3598eced217cba28e978399c2cc34462cbce78c7f53ffaea3bd4f30b592c06f658f9a587a701851328858403c9e817922425f411bf870
+Qx = 58549012fb02ceacef63c75a4f23e6d2de749d83ed936da49a8c455478c5062bdb800f9
+Qy = 3385ca738df7e56ba2e35167aa0bdaddcb7221370a6eaa1196885e11f7b4626b970eb4a
+R = 0db0d340b59af49ff78d09088148055f15df0e4aec1b23409b97c3870dd9276894ca9a6
+S = 022b746ee1c71ffe777853500041ab5534bd230ebdee9b2a370b55a44efb57c9b916ae2
+Result = P (0 )
+
+Msg = 72512cfa1e26e37118dc83a1606be07cd3804856d12ca14eec454ed6511028ef2631c3808cac017fc71eab5e4c3da60aafaddcb93b9103f802b269df9fdc3fc5f8e99c7ae49ed592297a885c65f8bb8e7dfcf3040f6f7b2d3416eed5639c4d3c3e2960f20e9d9561e9a6dd015304555d6515d29ef744c24a69bafc5356a5fb9b
+Qx = 3612a196a33c8ed12cf980b840951582b3a86f552ab54559eeb122f588706a16070b95f
+Qy = 3487533a8d9c60cd10fda8d141e43fb58c7b57288c5ccd38a1e6c012c5aae9694005a38
+R = 36c1558ed5be4f7a9eb964722f8ea9cd4b18ccd62eecbf88e76d5a54124a18241f3c273
+S = 2b7e1c813d53f3c575f6c298e7370f03aed5f53a0890d7f3b4a6664540ad2c5fb6a3a38
+Result = P (0 )
+
+Msg = a5d0b829f01d1fceaffce094db5ba515976b08212d5921b87385856ab993702d4440eb54b441fa8e4d1528d8c2cece3ff0cace5c17c1c8e30287801f64b8b593eb4598a5325540c3328249f74b594ffc879b9f07ffc57fb78de19f8f813fbf5dfd1ca80bc8d67072fb8d8e76c4d986a91ede3496e8b98872511032d2af2f0bd9
+Qx = 7c25d45d83b336b4d6b36369daafa6c3cef09f0870caf30ec8f6f8514b85de2276346e3
+Qy = 5f48b89e1120c649ddcc7f1a5533d0b9df16bc8c8c1364c2d512dc4e258cfcfd3296e12
+R = 0f26061bf7d6f5a7ca3e5762a04cc8e2cf4b435f43fe995e0a331dc69dcbd2896110a87
+S = 29c809462df986c68835db5b30c804f5e8a04371467fc2330f8f30d85b5fbab51b268ea
+Result = F (2 - R changed)
+
+Msg = bfc3f7bb6c58122f3d5ca2ddedc12933c2953f97024213eea1d1251a58220d8345b86c9793d62997a2d8b8b43c10aafff78af5e769d9e05a9155a84d90bccc00174af89bc9c93cd54b9994ed7c59e43c62bd581b097550c2f67300e45ff39a680e9eb0d76ed0c5e2b177fdb587f4770bc6f33b3d6b618b99672b8939dbeeb1cb
+Qx = 3c74781d9c78f1229e5e1501f2ed9ad8658241f63fbf2b7dfac0999a370a5dbb704eb3d
+Qy = 5bfc96ba37e54773a12099e5ed633015d3a5723c44159870fee6befb4fc8f8f513a5e9c
+R = 35b51f0b2da1a9e143ce4f1d4441e43743fb2fa6b77c00a77415a54951c6cbe4da01871
+S = 15fb4871ed50614b24975fc1fc815f8d8a271161b8696544a58d0a3f39f157e7945aca5
+Result = F (4 - Q changed)
+
+Msg = 99be17572e057fd4d59612f45aaaf598e5c96fad870220a374904679892094a692c6a968c8ed4c483052bd3e687111ee87b477dc80fd4aad5dc59cf9ebae96a5d2863fa4e4f7e9d45e441a7fa9cf6fd0692a52b0468c2510471f6d5d1d85c2b40dbdbc85ae51c2e958bde6994e99bff0541a7387917b4c34ac84a44c3cba3ccb
+Qx = 2377427fb3b8767d900ca949d319531ffa6638e1d5ffb13d79c88116a926e1a62413983
+Qy = 0fce70520014c3cd70b40fc0e96859715d1fb3252897b0927b92fd5f0e7bf480330c6eb
+R = 3cd69c409b8b813cf8646d93ee9aef6fdeb58cf80f2bd1bcdc17a98937e98be7b46d960
+S = 28c4918ec3b7175c9a444209b33d4f28df4a1022a2a15357d0cd57c4187671c880f4235
+Result = P (0 )
+
+Msg = 3f9700ba932f4dd0dfdf6abfd99181a5d233197e66d9edd6bfb0785acfba3f988f53134d6b62454ed1ed53caf3c58d4f58029b6bdcc72f1977038a460acae58c504249492633af48297c1a751e8258aa6daf0a5ba3e75d5d14a8ffae87103d9f68e588496c736e1a872a3f01330b7e09a4c477f05a629e67ce50ab52a4d66755
+Qx = 731eeb3655827f1bc537c4999a1a689fa04670700cfd462b87bd183e04cb55886884dc8
+Qy = 40d79178089c998eab14dea5f3b32a60e5b049236a28b5b77803b8fe05b05edcf436428
+R = 0e226078cdb21b77472be6f63afd255e3135bf1438489dc92f3dd4c8c6e12bbdc4c6d39
+S = 0d9ea4df4ce27e55d85b2aa2c7ae5a6b9812bbb62f5afcc13bbb76a912b54255a519d1d
+Result = F (3 - S changed)
+
+Msg = c95558c9deb339a2a6fef48a03168484c167ff539c89391ace6a1ee821ef4f2ea1e7eefd05b94ff9c84b8aacf86310ebbe90354f7faadff81bf4ff95c5bc89dc82c074cd41d0ea6562652cf1846ca471f2ee03ca38686c1f91025435a4d6fcd29d3c0050dc27abfb652ebb0315c13e295b2da79827b596dd1522c9b87bed20ca
+Qx = 556d793d06a883f152755f2b9a856eff7dcafc5637637d1ee4853199a1440528a37ecc8
+Qy = 396fc96c9b3886d6f7f6dcc23a43d3b2023646166d5673c3e52abda67a841f3940146c4
+R = 0bf19e8e440074b33a0825d64165ed9d913a42893af24c92a856a4601aafd78be10b22d
+S = 35bcf5c1abbcb5883e58eb6ae39d5598810fe2f5709843a358a422f2b25a6ce165486db
+Result = F (1 - Message changed)
+
+Msg = a31560ac1fde2a35fefcd4a145c66ad7e5aaf0f6b8f7b964bc0686cdc229a675475081642ce33c2aa5f4d2daa786a7c6e81877c2ad0e7cd8c5d6e421f78aff45f2d652db4630c65b7c8531ca8f6b87ee9282754cb03a7268276aac44f1c01139d4e26b2a46e372868814572759f64ca504d6067bb5e513390e74d27850e1fcb3
+Qx = 4c8ddd08fabb91a746012d92b5e1b08a1660f6fad7077852040ee3249a3406b60104864
+Qy = 556d785a2be3fbf7fcafc6dbc0b33131b8a852867c2385e49d59cc819a8e05f5b5a0671
+R = 24d170a91fe2a91e57ef38722166ef8d61114a3b06c315fd7cacb7fe8b2e78c250017bd
+S = 3fa47973b5ace7b730313dc3ecce99978c14388335fccca585ab1bae3d9b8c54c6dae1f
+Result = F (4 - Q changed)
+
+Msg = 8ff26db215e4378632aab34f2d6c5caa6b3ce3d5ec33e34b37d55f80e5baf64917c62979f6279dc77049e8c0e94a42295d12a77b380a759cd7d05bae9275be803fb8de350f9690c2907d2edea4182c9ae85a5924fab5bafd3ea297d089d76dd2889f467633ab40c6e28ca62909e48d021218bf6c7c8c566a03d1198e1b29f226
+Qx = 1f8801bcb86ab56ed53de11e43cf7887ca314aaa995127e0aee12cee016208e34d96892
+Qy = 178921d659aa51ed0ade89ac6f8ca158a5be308b3cc2877d4971766f41d76ec912465d7
+R = 23908ad5ef1529277d5265880a7072531b4642f391059cbfc694d25b44ea214c9455d80
+S = 0673118217e439041b2d2c57f13bc1e6be0a9d1333fbad3b9797467dbdfd620f22a234a
+Result = F (1 - Message changed)
+
+Msg = 0ae95eb1ca6696fa0031a127e6bc985307f35a621bc4640fdaeb0b0baea671be5df1d241c43c1411c64d55b19bf3fdf35e69250732afc329b448013ff9588eaa6a57643e68ae520195aad965d08bcbfb8a8834cb335396fcd01fa2e0683edb0d686f34e4316fbb992ec5b66ec8aa82ef89d239a85384eadb37e78b90dcfbc593
+Qx = 407a331ee9f2798100d303a71460318a9d5f5796c8df58da34143d6e96b9961aacad42c
+Qy = 0fd8676116e1ac5e2cd852b768854277cf48b214f13cb471f8f74376df4a31cb4e35f58
+R = 2d41986184a5623768eb3da2332f50dc56c44982c919f0c6bac35c48921823e2caade39
+S = 05b70a188133d739ad521d4e34eaf938e8e367cfad441f6787234099f59aa3358a8e716
+Result = F (4 - Q changed)
+
+Msg = 03f62cb19615cc10b61823ad98bb5619f96fbb4a9f694b4cbfa15f631dab810e4c4b1a3f78b36387d6e1d4fe6dc06783c44d8cad2e8f5083074f669e49829c328f0cc999a434250c9ed23ef20e30384a69d5b76a451e84b6c6f2e6d8d1c3dbb7dd5a0efc2fb16b72037639d8b2ef96f242991dcee1355fc9eea75da6f0e53408
+Qx = 07ca25f183792c94b6000d84231605e25ed0832b062d9050e62dee4baf7da8f6cbaff10
+Qy = 70e9d3581aebc58484583e46958f7798255175900ceee19aa18de2266213027c2740ca0
+R = 1b6b49ae00af7448a04cea7dfb3fbbeaed31c80b2aa58301319163111a099a9d0db3518
+S = 2ce7b39de55929ba974bc1f2f93509505bfb2e81ceb2ac079173819385849201dfde5c6
+Result = F (3 - S changed)
+
+Msg = b8eb25e82008ebf3d4fd85f70ecf2fae30fb5025b70a9193597f5f83eac978e102fcaf53694be6f581c46b8950352b6909c4563c853da2468af9ec98cf07610e95cc63eab28859385ae66bd47937ec7fc84e9efde89a7d107dd5f9606207faa1ffe8aa8279a2e59dae17ed6e00517bfda06b0c44002e249145986edf1665a9dc
+Qx = 5c9f1161606bae20e82e1646a15c1b44d5bc3119ed074a0fa38510d63b320e56d55967a
+Qy = 039c50fd857f0afcd2dbd0a82143c779c63e1f6b190073781ee99362b4c12bd3e265469
+R = 02a0e383a8f259a4a121a482fdeed8ff6aa48027071413ec41844ee077aeac27fc1a8a9
+S = 157df8af5c7084d1f8d3cdde76b640b409252b8fee11e21561d6c8bb512f35fec9906a2
+Result = F (3 - S changed)
+
+Msg = 45d46fc532bc816500719a9ac911f74e2dd4dc60674ec22237c4dd289489d93f586c7ca767502cb789641889031b9325e5e4b497729ce5434ef2c51086e48ab346ce8b34e7c05c2aadc3625e7a75b301ba22aa4ee9a2982f80bdd30577c1ccd1e031bdfeebc4e3c0c3886c8c4a3aca182d0f6927e124ee9e53b681eb0f3cadf7
+Qx = 6bf2cc13a20edfb4f17a3bcb485465d2077d98024c0ca654d1797448d3f443aa203a92f
+Qy = 15548d03a4a264bc99deba123bcda0662de1f9641772fbf2df54b2199a499a1d3973225
+R = 2263aa31f15607fb37373460962e627c32cdf7adf2a18ace9bb41ea72efe9e311c75577
+S = 0b6b80e258d140267de0459d17e51351d05618f9192430b4d39ef5e67c962555aa62f31
+Result = F (2 - R changed)
+
+[B-283,SHA-512]
+
+Msg = 301c21f2737adb58cfb5e47d423edd8fc0be72428031eb4295e6e12cb536ab550d43e79e56c5eb0602345b3771b9fe18e1a84cc234028cde7359f31f836d5a01214b4eca69a3e1c85907486b6561c38244ebaf1bea59cd10537fd6c82913dc54e4cef96298dc3f28f7ba31fdd13cd840db273a31811dfe5948a1d520239a249c
+Qx = 6f0fa13a66fa086cc39d7a2a80ba0c98eae4d7de02981ff3752061cf87c1ba7767d9706
+Qy = 0f821f65be3f2252045aa549009da7348e3ff121a3b88a56c58f045e635a8665a7781f6
+R = 2f2d858958d168ef9af3e991a526a70610970f3744290379d1cea53e163b93bdf297083
+S = 1f6a2b6d709e06b4bda3ffebd2049ef7d84201e1c705cd194ba13691c19e53a8544e2c3
+Result = F (4 - Q changed)
+
+Msg = ebcc0dc1d270538fe5a24b51de5d898a4bf57f185e293b6e69ade6559e56fadfee3a56ceab98dabc54d709fac57c4bb394e4b278881755b42a85a7e3c4621df48e99836e55fce882476bb9ccc5c5584f984d0be383a4574d82cd9244b1692574804062d23df336af1deee086b4f23048dbb1137409384a6df0b8662d4c1fefc2
+Qx = 074ac8714589827a008e20c3bd7dac91bab22089b499cd599dace37ead6ec15d087ac5e
+Qy = 2bc1317b9daa523126abbd7e2d854fcdf629796367a17c8301a8478944fc742fab57375
+R = 19652040ad9a1669c26547685fe4b2b3a956594cdc32301ab5049d1de8bccd4c5f8b8e9
+S = 0c31ed316e8a5f93417514070563beedd53274283d61c029edaf6b086e39af66bea105b
+Result = F (2 - R changed)
+
+Msg = ef89a38e38336aee87450426299ce683220716ae8f38fe495ea99849bd45c42c389a834d44361f481dc9e8eacd5bd5d60cd6b9174e5ad547d5da898f090064e7f9627adc115297ed88085d1e638c7c9474d8ed6fcc44cff60b79be819ef842aebd6d7faaa299d74640130170b25c3e0f20284ef3542c1d07ad4e09b2e64bfa9c
+Qx = 73e695da5d4497455caa6a1d3965196f542ac6038d7eb2ba08cc5d754e7bb6692054219
+Qy = 7d3ef6e55d1ca1e26db5e522e500c08649c57a0c85cf41de54e018ad01fda972f56369c
+R = 3fce80cfbe80a820a76e775c7d67d86e8299061aef296aa297c37a217b4e1ad07f1662b
+S = 1e82a1e29cd9ccce472df6b5d4874ca79f162eca320ec090c8cab7182522978462c6226
+Result = P (0 )
+
+Msg = 570ec8b0418bf99366ad2d0bba9262d4bc8271ad46123ba2d280e253fca622c304bd8472486e8fe0e86da89bf472b1de90d7fd64bc5e9087f828ff14bc3cb10cb9a5ab069dc11866860b916fcb1dc27fa699046989299078e4e50cb403140ec7391e6e4a067bd3f88c69f01db9a2b55edb43bc6ecfa1fdfd6d9e61b0958a3db6
+Qx = 1854b9c970a57e5f6b1efdbe43ed306ea59dbf65e72c814cf4f151a32bdd9fe7c24376f
+Qy = 6a3d0507cb7625e07977970d1e5ad43ce7988a398f418f4e03afe5958cad3dc11b30132
+R = 1f62c8e75df7e54a48482947cddf76e6644d95d1c668c7cb76714644367c8aa3a72081f
+S = 046f066970d78fd2b40fb19d517b576aefb693f2d7352619a5bf99ce3348d6bcf35ab86
+Result = P (0 )
+
+Msg = f467a1260526e4aae76bb95a5361e9c2c1b568da8a4d47de09d84d018b3fd030fe0f4ac26765246bf0f48e6853bc5586e43f53d044bf6d3489d487a1a526e6d5fa54b3cdfcbdb6c3709cbcbdcca6018db539efaff28245357755e01c22ce0f1b5411930ed53b7b2b13a784214e6559afb16e3639c4f5259c026859166f0fd37f
+Qx = 17df7dfa196bd8550af0852273e0cfd599b49a91af23384df4c823046445aea7cb57cbc
+Qy = 23361df2f18c4cf3dbe7307470dab5433711b40713f5bf9bcdf1a43494bed46f7caf2ce
+R = 0e7e9bd468e66f88be704dfba59348c320ec15faa346f23ddbce5393d962e85910938d4
+S = 3f5d7622a20a96b48bf8cc1a59a3ee90565fcc6f47dd1dac1cd41603ef858a9c70eaa98
+Result = F (2 - R changed)
+
+Msg = 4cfa1837209d2ebcb9ec326a75b26b60595627271150be1bd45e7ee8eea9f3ce7adfe9adbce67ad86f29ba6d314429b561cf11714ef7427458403975e1c3fa358a10458265066e6aadcf0f4ec3361f1b92f45f779ac1cd376efd74019c79a7c530f14873760624c1b05cf66fc7af109808a9312a2c90ef52d403b4ae15ff56ba
+Qx = 3110356e7c27d4bb7a009d8d8e18165fa51a6e620afef4d3963db930d6630ee5030166f
+Qy = 371dafe018591eb3675012611149ae849c78ad2b15c71776383feeda66ad32aa2e0f3be
+R = 320931fa29c34fa6813e6994e3f4aab6abb526dcfe2e3cf74440230a1cd91caa6f02b64
+S = 28881ad71ebb9478d86fce0991b7d3c9cf974dabbca47fab20b5f52c87a44a233840a7a
+Result = F (4 - Q changed)
+
+Msg = 24474dcd8054f618a1c9bf0a3fbd9de075954aaa077e793914929fd04cf9dc7fe883aebadbd0734b97d0016fd0bc3e489919f871058d6d49c75ed8fb1004f59b7cd5e5e415497d6d56a76d0c186597157d4b140a2b6974d13770429b9d45ee14727b01c52c9b38a1385265cde6436073d8c781f8ff4a0242f93828efc537cfe6
+Qx = 6a0c350bca44b1431e5eb35194dda9c96e8853e21c6877f6319c49d5ba2393b107bbee2
+Qy = 56ed5704f59bc3f4201bc80e110f50eab0bb1394cfb849b5a45e962a459d9bb1b9a381e
+R = 225a83f91fddc2a05bd95969b8ec6b21ea6371b55038fe4e563927fb80f21dcdfb78f2c
+S = 3773d2d5b1ac44b8f4532a2d1d36875cc523a964eb918054500830a2adb0905fcece8ce
+Result = P (0 )
+
+Msg = 5f0355a0467c2606d3e83697076a6169c902b0b59de1991661ab9a330a79d3be14434522d3160484a6bf3b3668595ac7023681ccc64e51e125762ea7b887b6fc83c608de7f0f6da9407a2831d3c6a277b3a009cfaffebedb31715e797ca388c47880c5d7a32afb51cd7f3ad75d60f88b797f3dbb501582cb2e9d1a99306b58b5
+Qx = 5144a0ee024309021982a2d412e9ccf4476600b440aad908222f44520f22cc6d6ec9417
+Qy = 2837d483d06b1af12e89b2544c37d54697b44fb3f20fc5724c7bc98c1c450fe1cfbaed3
+R = 079615a9947b3ac5ddd09369ddc91bc97d5403af6eedc447cf91536d9be802739ef5bc7
+S = 31ccb39e79010fdf0d6574a291b66c756aeea9c4d7d3e23247c94b711aad4108ee9d0cb
+Result = F (1 - Message changed)
+
+Msg = aab11b5ce38f8adc44802162737bfb959a602c2a0042b6b2655ccf796edc864efef20f337b33325ea38ff5d7d384b2e1b8183e3ea9f99bebbefe2e08537245dc6d8a263f34dcfc7ba87bdd9e5bb090ea2794b26592577af55add124f146118390b627e4cdb52fcfd52c5df09b01bea6e09bf2beceea4ef6ffa8a9d6455894499
+Qx = 1c95f45121c91098ace51d3237a3dcf821067860fea39b84a2dbb83d95ad47808c1fa79
+Qy = 2cd3850183caefd44dc35685e75590d2cc1bd3387e2ec00d19dcead96392109b6a4e1b4
+R = 3e7add0e76689091f9a308b3f0f4a9b99b60ba3244550d68177617b44c7bfa2138bf622
+S = 0ba0e0bcda9acd97e462b8785389367c66b990cbee3180892b9c311983383d9c9df52c5
+Result = F (4 - Q changed)
+
+Msg = 80adfb2790300182db403c81cc49a505fbb0263dbb277a10e0d2dcaba8f2afda668c11c1067686a54e2812f9c4b6535a768518dba9739940c1c24e0532ae983e9693b6455064a58ab7886a08d82eb163b3c3c560877aa7da6c2f4eecba6c3f132ea4b94806de2457eecc8a5486af0cc0d0ed08b11f4a0c4e08ba64571b8d9dcc
+Qx = 71c9e9753721e89e06016e37a5436af2d78a3fd4a37e14e1920db15bd2690707f00a7da
+Qy = 3c43700ed8451ab90a641641cdb60181aa2ba67d451249b10669c9fc4d51984c4857501
+R = 1b012becff7fbccd45bfaf3ca533e7d1b81cc6ccf32b16888080e6694525d91cfdbaa3d
+S = 1e9929bbd3f10879081d589ad037cfe89ba7eca063a883d77531ce8b6e42eb983704535
+Result = F (2 - R changed)
+
+Msg = d23b4aa9e2ffe02945948a303a7ae9f7dbc8d8c72a059f7a6c77316a0013056ba356b33731f4a303765a0396245e60442d1577e272e9d1990587618accaa0c2f193d78f59253c65b008b8b6ef08e47eefddf60ffcdae6fdce5fdc4e071f2e055e136063445b130054204869e5b6afd2bb4df32e486f6002a1af7499fd7b4d9cf
+Qx = 3c65372677abf7e1559168e163cd34d44bd24b3c7d519fe4f97776ea875411dd1502df5
+Qy = 5c254d97c7e1f3acd8fa61a5e7ffc56e87ba878749faa993baee3cf01ed829bccaeec83
+R = 06f9092a2cbf847ecc2b3ec162fd6baf0b263503a4abdbd9967b8482bd83d2a220c7939
+S = 05a3f7396d0118fd64a20aec5fb47f6ba2c477fb2f27e26fe4d1716999ebafb811c20c0
+Result = F (3 - S changed)
+
+Msg = c3399fda43bc148d8680393fd34645946fcb7f1a06afd976c424ecbfe4e970b462645de1f7a2883851b454cf405198af088226a952494561793da1f993f9fc6d11b03fa8467ee17c237e4aa8fd56e3ce19a0dafa784bc4b5ff6c97a73fc3827c6468955dfc2de3792e4fe1d9aef00be2a619f19ec5c2c94a5a1636b45d04984e
+Qx = 3203fe3a09afde5491916ba3ac47c6509a404c94b3be342b2c107873c7bb384c407fd67
+Qy = 13a509bb559548f28e2066f04996478bf78d6729e261f6de792f659308307f7b016326c
+R = 0aed76324472c8207572be5928872b8d5057b2443abc7f0e1f5192dcbd7a41c95959c93
+S = 34c4d7ef9866c2f94e07074a90ab67a59740a8f2999e38472a95764a93594aa53ab8ca7
+Result = F (3 - S changed)
+
+Msg = 806379144a16b7698b2b78d896e1766d4eed79bcb1bc92aa93a458b840d49df4367d5e551f122b5dd59636fecdb5832580dae062d903bb6fd4666b9afa787bbf943139a76a214d218f4d771901bf5a2628e9b2b91e26bd683b3b529c0b7ec345cbdf86b60e56f0ec8f5d0d7649660b2a239db2b757e18833cb17f2ae38dbcfd0
+Qx = 5f25074b3b930c8be4b1a2b6019d79e505b69e9e0e8d9a19167eb0779a236214cbeae05
+Qy = 0f4a8c8309f2d22b7a43376a89ebaf88d4613829717e65935064ac19e6b9957f178b953
+R = 1460bcb5730261acc8987c39e85f215a61d8a2ca87effe7c57f7041245c4b083085c63f
+S = 1e765593d3556aabb3c2af4549432883cd8d5ccdfaf19ad619a04f5d3409fbe8bf9437e
+Result = F (1 - Message changed)
+
+Msg = c97257db3a9f6b7427df85f4d5fff3117135fa647ca3234498209245a9cecd1040774de4fbb2bc1765c64428e79896da3be74267a9136f10aa8b8427bba623058b930ae0a7e9106e6fbe30e31db93e18a16669a6190e9027051a43c26a68078c9692b495396b4a5d9a8965dd3e7a3a06a1df3fd0c12fae4f71591e9f448673a5
+Qx = 034d94608329dd4bef38dae91499805f0d25456a4e880dad385a0cf04107fd4fb75af5c
+Qy = 65538785cae65a3565a622502ab55867c187591f2e84319b09bcda678afb6ea0bd07f46
+R = 1ef7e81ea4ce18956ae9f9da3e1b7a6d31a34b9211bbaeeaf5137e3e7376ed5bce0e3be
+S = 38ae4a0f9014938bbe690c2b6f7916ae0f5f65f8946d088ac53d68db86d4af7d75778f1
+Result = F (3 - S changed)
+
+Msg = 68c7d3d67efb0bf0e1c8ee27b1ab265e92fe24278f040b369349cf364be586c7a631ac64521fb2e14a1fe74dec8e42d84b1790d23bd2f7a44a575fc15eb5d56dfa4e0f08b7213e935229205865ad043cefcafa372b12433deb4b53ab5d31d1048adcd7acb99b940361e9312a747c6231cf5f9809d1e5d4199d318df97e304e58
+Qx = 57473de6d4715463fb17fcf04e82ae6cba0330ead7868beb21608526dac8d1cd0a51903
+Qy = 43255f75d7a274f0af1fe5ae926d7327c660d7b8fcfba7d68a72a462b03b3827cf99c7b
+R = 2e3c4e813d1a332d57096955f3c84353d337c815cb6cd84053407ddb22a61a5e2cf898e
+S = 045ae8b38d261750dc91f2f8821c41e4134a56cc50ffedf8417d18c4fe05437a8d16f2b
+Result = F (1 - Message changed)
+
+[B-409,SHA-1]
+
+Msg = b1de8a40517e6df3366c6db5e4bd01492985604f45d465e5e7eabed7c1ad41a124bc7b43f90e7260f73b4d013e48a3b508ade286a4d77fa92e8587862f5b8b4fe5ffe9e2037a00b32323ad0fab531e32293ccbbc0f94f7f28860d56133a646a13d4559e062cd8a40ce69a1fe57513c48e16c6b8a291e2d791a405b15f1de29f3
+Qx = 1fc197d5eda713412bdd07be3fc5fb0da925da4263f6144bd5634841e5ec8eb95592cc5e2003dbe0a4c73de833a3b233874b031
+Qy = 0d004fa7f31f7e4f34e791ec5c8d6024298372939cd16a3cdb6609f898765ca8264dc581fc5be3fcdfe71d2c81d0d3d93f17044
+R = 0b65821ac987721e483e2a3403b9fec391ab8768080b53bd13678d3611f5ec7d79771ca75125008b816029ecf713979302a46ea
+S = 04d1a793e5b81c26b18f93e76902abe54cba2efeaf378f41a7d626d4370c72d1b23eb8dc5467ea8714cbe6b38fd42a704d3b454
+Result = F (2 - R changed)
+
+Msg = bfc95ff16b708e0cc192341d435f0bc05988819cf28bb7071c75054d939d55654a4241bd5448146cdb2a22f0de928241d8f54b3e253dcca0055ab6b1f3157a93d3b8f5e71d040a82e5166f015641da8a5748c104a79afafbccae73638c6814b34ee5a3a1b08ba842466f6d8d6637d64993d7bc9a14e70863e1e7c3c84aa049de
+Qx = 01303aaa17025a03ab2d3cf9edea9150552dab7698157267be3c0967e416b1bd7160a6c2cf58d9e5c6bad8bc9818ce5dc7013db
+Qy = 0849c3f3f23b97390021a0206c45d0ecac9cf1a442d1a07f6596a50c996eb92ab7148a068814cf776e27f8114524d113aaf4c2c
+R = 0fb27f96f79ffb416066dc79bb16dcccb350765993724f15a85f8481c1356f04e3265e762cd185f1ec2924422879bd16491e878
+S = 06202774ec35ce2eb5241fbdc7fcbf40eebcb602a9514efc84b7166e0cddcab9af9a89fee6d2a213572bffdd797509157e44551
+Result = F (1 - Message changed)
+
+Msg = 3e791f391354c896c29320f7f9098c2b227b931d9948d521a8534b00f68a1b0e9d04940f94ead0e48933082bc8dfe6fc1177d7f5c0df160414230e799e8e2cdb7c3d4a1fdaa80d1c5014ee83dcf195c24609dc48a4ff8e987e60cad2b17c9e1a66d31d1d0e10f8ae384f964daf1da408582aca392b41046984d7e70dc74b56bf
+Qx = 04b724d23de2a52f7019a4cfc9495ba49a82c86bd27b85da03d6242ab159047ec028536eddcfb8147e890f238276ae982c92edf
+Qy = 0b2207ec251e7c784d3ed5918ebb3d123f00b5f11ce9dbd580334ef35b0e278832136dd4e60b997848b57b8f57a8514a46fcfb4
+R = 02dc92487529cb525edffaaf08b8139db0e3cfa0a979bed486f9352a86b345d2dc3064170b59d44b8b02bebec94ebbc022c7ad7
+S = 0308b6f2918148cd5962a92cf50e9dffffe16a89da89e72c133818c2b055da6bf5bf11419b503431947bbe1651cb3f09a1fe793
+Result = F (4 - Q changed)
+
+Msg = b4626b2954716ad518154f02a83163669f0f616ac9977ac7deffc504221abc8416b06c46c3bf1ad84d150661203a6d8416480b14b10893dc3858513746cb2ba28b96b4bcdcdc30c75cfbac3a9cf0c4f98f55e6cbc2d430ca64d68882b86adfa88d081533a1eb1fabfaae763bf81ac74f2ef1930c137c54521c083dc96b72b1ae
+Qx = 02c3bdc458ef796b9755fa3393f4502b4fa95a8542699128ee76617248fa33acd2b86d4a777056537385e9f8dfde007ab6f7f8f
+Qy = 007d1062be51d255717d1142c5cbce59cf72f1c456515d666a1f3594f5d2454f908ba9b82354497368cbd4a6c95b6703e7cd0e3
+R = 029b4d7a0e95456c21c6f6b59de9adb415e725114c6dd981d8473fe69852922e1a15909b4fad11b23257d1f4ca4fb32065100ab
+S = 019497b34be56fd4c240e3f4a8a602566d294a5ebdabd1db46fbf49c2ddc8a4dd6211f63538bf4b4caf29f1ac5320e792b591b9
+Result = F (3 - S changed)
+
+Msg = 48902465b97151112b8026661c7eaccb9ae29e5378a6769191801745afac77121dfc512891b22e09bcdb2014029ea2f5b2606c9b637534a6efe0c771ead4ca4803f73f155100110c078bfb523e517428108b5f1e2428e1e662fc7e8a0cc5777cb775ff6c2159d3fe4fd36ef856bb1a4668d3a40643c603d758ca4a62815ad127
+Qx = 10a37faaac718d658685781808f4fdd2759032f3769fd5a07cf132860cafde05e5725abdeea848a6d774c77d669e273a88c5ff1
+Qy = 06dc33ded545509febcefaca40648a9f778d2ca6d4a1a7c1e4fad85acdf79c6bf785dfc83da3cc8bbd66e28dd92a35272e445a3
+R = 07326634f6920c59a804bb8a85b24a3d20a16051f3da8387fe65078417b16ee28894f8439e94c4bd69eb6233c7d583700f8565d
+S = 09fc9a53fc15d7f0c9032464de8d930faf598ae0d0b2a52d982bab17d2b77bf8bb3e1869466a1a68aef875413f53aabae7cf966
+Result = F (4 - Q changed)
+
+Msg = 8465266b8ae5e1e7b142c6df980dc8bd8fde556e3d1ff2ad527d57f0cddae03573ea775a0101fad03e44abafa7f2bca86e2599ee5cd33066fc619f0e1d58434343968125369a56bcaf3a3eff9afbca7d18946a821c8852f16aa35ff9ed3a968a37bee7e885b0480f48edefd96c9107ddef63b5b123d4cba959d338b544fb9160
+Qx = 0192bbe71de0fca0ef92fedf231775ede19e67d3334c19bca02c2e55ef113d8e9441f6bb8a33ecbb523acaf5f1d5e520ae43171
+Qy = 1fcbfc31c175d2580e2bf0b63629b79e323d78f86f21effcbe38a68aca3fccd785c439aa588f57f26e71dd27b07fb4f67551812
+R = 0ef76c7cf85998f8c1badc12ecf3f6161856174a194dce64a763fe9e920d30cefd4255c5f209abdc4d9baccd41af6962ff5b2fb
+S = 0d027e1e9db5f2deb98614b9f7ab0953e01b4c43011727a9104594efdbc0a451d41ff8b6500951ae0bd1d60e6df962cd0f9067d
+Result = F (1 - Message changed)
+
+Msg = 3036da2fa56650429ee90c189888c37c5ae10ff42087e26454ef436a8717522980313db5c49d26ef9a18bca19c35f04b22e67f4d3c5d4a94a4846377f2e9e52ddc8659b03de9716366d36dd9107b607360a9a7bb3645b76bbecef229241828c254f855f19e4c47834caa54eb64db07717d80422ab050352dfbc0d8f9c1b2b0d2
+Qx = 0e0e4fa090ab0cddaf24f6cc519b6d4dbfea0dbb697fa9b16bfbe2e3e3f160ac37ebc4fd886ecb0a0671f885227a796cb7fa00f
+Qy = 15e44beb435ed5b625df0fc0a74376b185cad91ccf8d9c92981f7b0fde6e2a7f4fadf301f1ad3a5df62dd477e2871c4a9ea74f1
+R = 01a1ef5fff035efad063640c75eefc985cd29d2d42dcfb387ab461f70108d9b367091097dd6a36983abbbe39ffb11ab12c9c108
+S = 095fa5a326613fcdaf44555c62d1a08c5b937ac1c774f05992da7d10f254d00df109ef194b72b250ebc04c6819220411d9be44f
+Result = P (0 )
+
+Msg = 00261f8edbd62dd42f6f78e184b9f41488bc363ab133cc87bfb77e18bae739fe67ad4f6693e30b68c02c9fdac16d4b6599b47e0ae0e6226210651be62b8f13802e904ba9ac670b45bb2b315eeee888eabff4703010058750760b430441ade63dd41874a3ae04a8369a414930ce447275887b70b6e8e41476f9f9b15364897dce
+Qx = 0738f21bee2f5be4aee94126cf87f9f92a35966c417f15c72181c003caa5d9642ed343f16f7e722f2766c86491d87f9853625c5
+Qy = 192e1bab9ca8514fa31b38e500553c406be903fc56afbaf5420163112c09b3f46fbad969949271f542331124b043502835bd08f
+R = 07d2f77e4c5a650693c41cffcffb6b57c893794569911a4a08c889a3ee8e2f8e809e7fba19e1fe52bd07817362d301b153c4338
+S = 0ce23ba26dbf3357a0440e455f5c8f67880947e39ff80f0421a6c66f499b42b1b74918bf630105cf0b3075c06dc32df0b7f75dd
+Result = F (1 - Message changed)
+
+Msg = f3ee6b05633e608cfc9c9b11e379fa3a90c74fdbbd103cea20e6f50345aad47c8e44e0155627c8d7799cc9edd2ad164074da9c1c124b266df3c8e6b5fb01775c92178a7c0413fdd1d39dae5f17a2fe19d8ae020ee868c5988adb625c77fe5a8b8e3529b5434bc8285eed8fcbbf6d0e0c8320161110be8b66ebeb9aa579ad1564
+Qx = 16ba00f76f40502052be0b46653a3668d16e67aff83137a322b5faf716fa30f2b5edf7b90657a3c6d9ab5bc1ab0d5a3d6558d2b
+Qy = 0cb6ca740379e9ee0e8b44beba3b521d84d42c6f363ef5f9c4a46bb7961d5ed1192f2928a9f2d9322f1b9bc14b9af5b531bc596
+R = 081cee9521b7e6cf0232490c4a758626c71cbcfc7e1e6fcbbfa0970c15ccb3adcd8b407d165823d77c65da205a167f7bf9a4f61
+S = 0090eb653f659bf3637593034a5fc419807cf86be34ee62c25459e4f77ec966a712ec42d287f16b7db28b78f80629062e3bacd9
+Result = P (0 )
+
+Msg = d9323db65bda5e62cd833d67492f9c1e36923f9e634b57c180b8d9443a02dc41c49b5539552ceffed38ce75e87dfe2b75f3fe850487c62069765523a411ecdbff58af3e395659f4be77f7e1e4c7afa732122856042a3081e7c27664cf1a0ce23c1e8d521f3176b6e932a1f35c35d3972c1db4eaaebdd3b0bdea9f69b216122f6
+Qx = 1f6b96eca9ee55eb5e2743e3053c6e2d4fc98844f0c23f5a4f3b780500592d870f55343c8692171110834cadb9a1ceda956a933
+Qy = 109759dd8a3b0c17b2e376cd3277c70ed71d4a610913ad881b5552330a68cccba436021f300383d74c1098217efb868bf8f08b5
+R = 0d412080d88e2529f96f9ead30c4e4412c29afcf9dd8e7cf11eabf1d78c3009c2d2d766a928c4fdb02daa8d558fbb42d6002e4c
+S = 0f050ea34b7dfbd7dc7021f0ec1a08c8bcff0ebbafecb1df7e880e9ae0ed43d1e8c67abe4a1353ff5bbd2f6608ce9684b7f941e
+Result = F (2 - R changed)
+
+Msg = b1f57b35991413dce15648a4814c15a5dcb4dc21866cca2ee6e3379bc94f0d6a02c30ee9d99fa7ec06e97365c461ee1c87c2787b717ed8c04afbaa638442a2c735b42e0abc41bbed178a452a41dff163a878fb79d382459adcb93773b7d024528dec9c067df7f030dedd452a255285173a5acb148383076d06fc4280d6c0f875
+Qx = 0ebbce40a2dd95f6402b332dbfacb697c31c532e3fa4439d98c7b400dad95679e41424989e146761b6f8a51356037cdda083647
+Qy = 0ded3f9de7f2cc133837a593d6e212c4ea3714aead97bb11a6d5f5a217a5eade1a8e29b3d6a5b0116628276754ca426c79bc3a6
+R = 053a70de21f3a34f3ee8ee30813dd86018dcce9ea6619949fa9bd52bc8c4b0a63667da43586ccfdfa1ca26192541a0e6725c935
+S = 0fbf656502e51262c74d03e2f7621500673ff85df44555e3cf779886735e539231581cc61bd9d42e3a0be15282dc1bd464b256c
+Result = F (3 - S changed)
+
+Msg = 86161f332437ce69a746a623b6585a285cefe2c811bad409c3ff54ff5c15379ec33ed84cd68ccf290b2b1b2f6612c7e00763cefc615a4309c3a72f25bb69ce1ec3c8e2df509341b1e0aba5ea95eb2561808620975254d47ce5f61040fa47f5b43a7b791f046e02fa2deb4cbb85cf8ab3c50478d179353ddadcb079b418dac4a6
+Qx = 16a18b9df30445be21eb939a2657a65c3fb693c40bde976a20af30242ae6717d2125200f2227fbddb3cddc65189978bae58e061
+Qy = 1685551ce2acf1a4c16b93c05e1298eb3da7ca0629386c3a72f5fbd7f7fc84c9577b83b419d1be8d6a5121feede6d1ef95a1777
+R = 04647ef942fc7c99034f1a6743325bf8e1196355a7baea23a58c00a20f424731ea4c37e055873bc21e96fefac5235a8f20313cd
+S = 006ea2cb72d198eb427a3d90bc24b46fe01807272ff7b38801d8ec89a5b372f76a3421b4faa7f3e8efb176d5aa5b217f3e7b519
+Result = P (0 )
+
+Msg = 891b3d806ea07653dd8453eca63c45774129391e2156b28c9f09c646844ce753268214bf24333913a6143b38eb714543886f5fd1005d3817761a8789eb39805e059f6233992ecda283d316bb23d23ccf4db0cfd3523a0e3089a79785254737e61e165c594b7e284d859430b76c237ccc74a4e729454e89d0721fa042143130d7
+Qx = 096ce499a6d45410ec284f7a3951dc5894da59efb40410ae980d68cf72119a8b96e4d2a17bf82668640220a8355c4a6f6679a6b
+Qy = 034dab336f363d2869f101339d93342590e211acc04c1f6a5608ba3198357e6921cf6ba7e49334316f929cab847fb04ebac4e94
+R = 00e893179c72998d28b508fd4d5d05bf2e002493e4e30813fb0c1e901683afd1742e6712b758ef9e1772505a3a929fc1c28e5aa
+S = 0139ab1beccd0ef5f6b6ed48e582dca880cebebfc6a03a6b7f17ad5c5b53dbca539456eed1a6ff3a623f6790a861b887f2775fa
+Result = F (4 - Q changed)
+
+Msg = 4aa4d84076807f83f283bd1d8a53d91fb6d95f320be0574cb9bb9f023fd51391b87024e6496cfff73703f2db62b9a643ba742b78ab0996179799d6b5ce127c87c86f09546335b3e58b86fc83233b3d7531a6cabb86efbe0b53c02621a7bf478edf41d83073df094808fd711f0e4d4b1a114cd7c6db2a63d7ba7c14ae25989c1e
+Qx = 0e3a34cdcdf8008a8676fc9b1a15cb5c58432777f31cf7a6ac57550a3844de084f839509b08ba526e8d3898e58f213f26c953f3
+Qy = 12a84ddc4de7513f4e77e2cb6260f145e48ccfaebf2ecbcb3852a5d5e7c9b595973aecdf5d3d9a4c9a8110a5842fb30ee1ba9f9
+R = 01ce6287196b725f2bb7fd062d02a3e0141d19a2b05198f42e419e3085d66d582dda78b2c5bb72b1281238803ffe0fb0d644352
+S = 0df2c2e0a9a528440ccc8c2bea8251bbad0b48bf9eea454a64e29d64a07034ee2c5d015e1bcd483000c6c2d11ee36009361bda8
+Result = F (2 - R changed)
+
+Msg = 8cfb0ca32d4cbf4b26617becb51c3286b7e1b729090cbcbdda75141ca65576f05f22a33749a6e6799634eac3283dffe1d27aabd3edc93741af0b3c70f3f7fb3ffdf9af412f2e15b307be4287b6477fb8658ec6bfcf990f91f1fb0b2f8217b15bd13f1a6d676c34c4edabf1522cf988d1b72d9dab432fa33e4b3887c5bc0c8041
+Qx = 130cdb3308450019284f5abcdf5dd15eaa036ce078fb43c00649cdc24958b698329961036b012e4a8237e1ea06210178deb2ec3
+Qy = 1c05d08274e2e97f7b03922b33fb4a4a88ce2a844d9f84709548fb95f8f3e30068c0646b565a4ac3eb6a6176cca1f49c079bb2f
+R = 095f6dfbdcd6d0599847e53674f8a5650797ce5b8a5b674892b475cbdbdbd000cf6ecc3891953a6b6353d9b6551de638778039e
+S = 03e27955ce75491d9ca7bdbada03b45e68ce445e53a35becef6169307a6de75dcc3389d16ef7487c509e7f9c22d3726cf9044a5
+Result = F (3 - S changed)
+
+[B-409,SHA-224]
+
+Msg = 595693d25e9e77001b2026fe8ef2789c69345327fab72c73fb03ca75a75e4ddd3aeafc5b96d58e306fe90005887ab802cd71f47784932f58b5be24d237377634103c9b8bb5e166f47a562f5a38c385186e6a8e6c39b3aa06b1edaee2a20878942695a714b2e5a1e45733e0819df524daca346125ea69ecd78c47281ebf7a9c8e
+Qx = 01643484c60a1010eb431cf6850ad2c2e49da641b52b4bbfb16df9ec8c7d8a8efb074b33a666df1d73d3a7ccb899b06596c15ed
+Qy = 15e910e03c94a32986b721b3646a5443d839fb95b6adc783bc1a2a91103edad863aa268d3f61ce9298ae2bd27fe67669cff7798
+R = 0f3a26b58061cd32406eca24b34e5e1006edecffc718c93ee13f22d6e4c51cd15f3ea66dadebe68c9ef08e2e39cc10057ce26d5
+S = 090e98961f7821a93f2a5133403b795def86531fa89bf3d4fbcc2b1a9d4279c81c729332cf64d450f2cd10021cf506de63230a0
+Result = F (3 - S changed)
+
+Msg = 182015c7ef4b7a553f1f6cf095a7bca48f172ee36d50b6347b691c83731046e480c751fe3ce95a7bead6d95b3c67b6764481cdc9bd247dd08e66f150257944cc0c70b46be7b0f6898553b56323f0ed6c8f58621a60f2ba82bb04baef092a42c018fad188fd925a070a06362646118170c73667991afc13b2996f3a6383d97221
+Qx = 1b1f842007291c2c4bc7f42739c24a0462f9bc495cc352fd89936617f73de7c1a95e5f75ef1dcd48c93b2dd775d393835b890f3
+Qy = 1aecc1ea8ed94565350f28f4d667bcf37be72d7dafb31a644bd7020d9d53c0c2c2c334ecc778325fffe94632366f114c0e4ed8f
+R = 05e1d127b5793e8416b62b3c5d8f633cf8ee61805491a26cd17ed464e340698d8b502605bd2cc821fc070152a28eac3b9733473
+S = 04d7cf31e36e9e1d1e0ce91aeb8781e5d04766e530abf4d63cc2b329d53f8278fa4fd2bedb3856d72eb6fb9521af584fcf91483
+Result = F (1 - Message changed)
+
+Msg = 55d68960ba62bdb7e7444e068631464eb76c74b769841c27b972619882a9c07d540e052037f47bc10fad0f6524d11507c17d4f959e5a1523ec3832d525c6fe35260ef5347d06c52efa6a642cb38bc616badf78a58a630f357249037e97beb23b8f23e9e3037ed2e4d9b6f4d127179a94c8af906af70d8ce516c805637b9e0244
+Qx = 12a5d407385ef20c96dbd7dd217b47a67ad416afeb6d6d1fa2a6b28444fbb35efb3ec9dd901ba5b4137abeed08429fb2aaeef93
+Qy = 1b06352e179ec2bb57c95d8f42d4614ff1097a402f5a50650196f3fd3760b2afa7eaa664b310b41dca8d47911b7bc194f92a989
+R = 04e03f8ffab0c15e3081868f3cf455a5033af42119cea892cd573400f276e210ef84bc01fcb78ef3ec3e1c0d3295b99d604ca69
+S = 04a48cb89c924f0253878e8a78eabc047372ac0a2a506a5b2bd37375d84304a221d82a3498fbebc74e8215ce417c50898707253
+Result = F (2 - R changed)
+
+Msg = d91cbd159f89562bd2edab1cea12a55993c643da6b7d46ef5a8a059906f4d0e709cc1a56ea53a860ce666ce85ec16c34d3563cb9c766fa99abdd5bc77099508fe28b0b7a81f37abde433b95a2cb363cfc615e845db9361c0f03f07839c40cc0149420bf173cfe9bda5299fd922ade6a97af1aef8778767021513cac6a2686655
+Qx = 0c4e272973a4a6e2ef1985f4c1e8af375e492aa9fd8bd9e590411d910c69151a059ef5ee41845be90725b596531de620c410a95
+Qy = 1ffb23e0b8c251b9a6f524b98c5790ed7217bc13b0909660647ed0b4808768c31f1bfe6b62ab7cbfa55fcaa497084b618756eed
+R = 0c998f3a9704571a6aa21ec2d0b049f6b413944753e032025a1db75f8d25e2923df69a83940cf91062e2265c736d10981dcfd37
+S = 0c3886b9277fd1f806117550b8b5186d27a260496c84a8318d2f9a95991cbbee8234a391afce37564d0300cfc72714c09d11117
+Result = F (1 - Message changed)
+
+Msg = 77f0add350c113c444f71c7a20522b47f2c46ab3a98c5cbadf85f8479b991b91d3108aee49c82290196ab9f8690e0c8f48bb27e7c342e1c1a73aaff8cff14f47bc2a9105b8c47b2e6e856a1539daa613c09bc03210b3ad4a50c04683a1f02a8c5120e7cd54bdeeb27ed745eef55c1a3556e19a8057192521a3914e36717954ff
+Qx = 01e431e558774630cee0f9d3514543980354d53dcb3df864ae786307e0e05928c8d4259f87097e4bb2b2ddc7b16adadcf9eb4b5
+Qy = 10049ca445d5d29faef788d1a3809e1bba96f0717891f90daf0597d5798502e0cf425e1a74172955bd27cd8c9132f77ab3e7a76
+R = 04fdfeadaa6b98230c025390daf30c168726240bb0df3709be75ca91ea3a2c801b9b69be2345d65a92cc08d78688871acc065f0
+S = 0959b3255b52a3b3ad7e77b3dfaa28b512b1f2de351ec3d2dae839140c6778e3721377c3a0af419ea3f5fc321870922a6bde022
+Result = F (4 - Q changed)
+
+Msg = 32c26f7a53cbf8eeca77d9b043bc0e2dfef3134eab243dba0468718cf5b021618b59e477d1cad68e531732321d2ccd3392558531ce639c9318ca42c6999d57399bd1452e5c38d31ebf69b4f13d9d953262fccdd2d32753910540bd19551795ae8b6e8b96a0f62b23eed1f9c5fab937b6bbef79dd2b1020b9cc90cb2acb287cbe
+Qx = 0c720b7b09620987b13715efee33eab00ff3a8e5fe93b6d58de928bfa3c95714a7905d24cde7e06481c54c8d7908e9b5cfa9bd7
+Qy = 01be58f3c2da4534d6ce49f429138ac5ae66604fe33ccf8f457d8a7c51826932e37df08bc954a0af443807f6d4ca57f5e1d9f0a
+R = 02a5ffe77509be45b000ec7f92222617b919d56dde834b767765c9ebe3de644ee010f8eca83b3fc2d5bf937e4fbebaf3b8947aa
+S = 0c594c2960a198e1af01a4ae0d6625c59995a0f6edc29f8e581e2dd953782455a93136aabcb3caeed26684ea89cd70757c978a0
+Result = F (4 - Q changed)
+
+Msg = 7de1e93479e743b2ee11232717e898a60e02502edbf4546808c01b0ca7dc0d33b990558e57aca3bb82df86fe2925e78de081e0a4152fba1e3c52073c30aa907fc7524186cc154e557399dabc1bd27e502a71fbb9ca516094232a0efabf8a159725bd4a9344c35c07740f493c0059be438a797ea07835089445546210f4d0002f
+Qx = 1d5cce20358216d8f70646d315033641ebe5cb4abeb764e1246e7887a5ceaaf6833256658643d2a2831bd51b7ec3d3628cf98b7
+Qy = 12257415c6e9e2768cbef78ba6ba3f4597534865cd3821435495cd0ebd9ddf79c05f1efb6d35c2afd0bbd27bafe896a239c8557
+R = 0fea23f7dcc03129f263847cc68fa0fdf692d60166dec57935a0764d3e82a8c67eda5614cd5dbd667e13db31aec6fc1e79512cb
+S = 0594b3b072de183963f26b9467a3a7dc3a9d44bb2b6174f1a40e9684e5afb701c13e97f16d1565b1602b1ee0b048bf89b8fc7db
+Result = F (1 - Message changed)
+
+Msg = 0612da735d109d3c46f661e3ab4439ffd80b7c4af895f0a0d6d18b3d764e67da9be365bfe7cc6af2fa2062365d0661112c55ed752f186d42f7851f209eca176d579e66653a1cdfe2fa8a04b99d488a377b8500e990cd423db766d361ca131c5d001a4bf8e4ea050c5cfac2b7babb782ca13d9071c8f3a231ad2bbcff3aa25dfd
+Qx = 1d598c6870e382fec832bf870b2065ddf9f00b95fb8f637e87fcd96c21b3e8bc62d757cce7129fe6620977277135b29b16b91f7
+Qy = 1f941bedbc6974276b48c7a47ac6304bddf4cf5fe444c8d137e8c0b1b30b2c43879454bcaaae00a4af6843fd64c36f7a65da5cc
+R = 02b500ad7f4c4b9b9e7f4b2be61a6738d3586f691332cbd3231d9befa26b63c0d297ed17fbc0debb11e446b8a1e24773b252ab2
+S = 06166a03a156876c2f8f0060644992096b206f40d7880195e6fa3e7442de0d773f61c1fdd7d0343b1fc521a2a5adcd6191cf1c6
+Result = F (2 - R changed)
+
+Msg = 47efb937a7d0edb83b454e21b5e383f6c8499b3fe8c490c4c7f8453db55aeb54d7d6295edd70a89f1fe095fb4120ded48d1e9c8c99abaf6e49e9bb1035d7af7f185509aae6d64e456c9f16a9ec40662afd9fcf1c497e3377429524beea9498bdadf945cfeb8192db5bb9d3e96baf4a3d283cb8014e873b7550c0c2fbc752e9cc
+Qx = 173b7e070d672cce754e1273c62dfcbf3e9a16f2350cf34fd80510c9dfb083495453cb155a80064b8342e00218f07402abb4e3d
+Qy = 0a1a772d95f44731103c5eecd684180339264b18b77c5f1e4c7827e5d29da2d22c6a9178f06384a72a9d9b1bf51773feaf7830f
+R = 025d7e29795016221b35d22253ae6adea1f20c6cbd564ab3569fd928548d7a1a249d8ec7bf3abdbd5ae3578f8073ccd322fc337
+S = 07afffa89511ca49caca3e3493821f30edd5b55c1e7fd900ea99924b3e7e76144096f8d0ad1cc9f5a8e9f248c36c1963e799b21
+Result = F (4 - Q changed)
+
+Msg = 48ca0a18d8f9dd57bf7896b91f25164f2b659904fb4a32a0bbb0403cb5953d1acb64d4a500d93d0d33b847a3788e6a320e7b24fd551111defeae976db8431d48fa91e87162fa0eb5e8981df6a8df5964fc06005a44a2e7789b94b5fe2ea4a46cb4002e962ab1043ecb2fbdb7d1e8afeab1ebb6b3382ade59f5192ed104fe621b
+Qx = 13af00045e1dabc22437998f3d65d20c7e22ef0fe927c16f6a153f76ff43662236bcfd7f0d35fee24ab999d17d84ffcf21d2e85
+Qy = 17f9b31c143ebf40b44aa1391beb2f9986f86cf082ab0c3564da653111953adc8259387c4efdbd1b792027b1843ad85415ae146
+R = 029d28100b7ff49e69e65f28606f8520ee82bfa44a044152fa1ac54af4b77c954c7333680a83b6b1a90a1ded9e53048176bd997
+S = 07e22bfeb468098420b6515fad41479819af90dc60b172b956693479690ec253b8db5953fa7ea512bdd142d696ccfb40d2923de
+Result = P (0 )
+
+Msg = 94f772b3a081df4f4e72cc53f5c8582b8ae54e33a9ff31531dc5720f9126fe0c346bfa25335c9bc515b53d903f3c48a56d193040676009b10f35f559e3eb0d52d36ba358430302a7668e71cdb3477e995556478c6623c1f9e64a31703c9a93715cf55364499a673a77e8153e052a8c89304a89e401f096586d1e4feea6448e27
+Qx = 0f1d45531d92516dd10afe8f90b4adeda7f40ae391690d3cf3fb76170f102e3c292f1381b00caec6d055a0d5fdffd3568ad4ffb
+Qy = 11bb4d71767958e5d4ae5c7a976e35d2be2e98df48bf0d0677d6e8a376b88ff1445c0ab7a6ea2ab1fdce0f6d867d6d851b35839
+R = 017a5aa04a5f916f83e9f3c52d0ff5a07ee93bd4fd7795cccf9068abb42960fa23833724d0ad63358383f86a2fb2c793a0102f6
+S = 0ad562a59d5e90cc3eff572cdcd72fa520d0b4756c160b9ac4482306a564605ff031c6875af028acd2562f7c5b66c0355239d47
+Result = P (0 )
+
+Msg = 6215eca1cc58c8421c92f7c54d2d21d4a5ae4c82074780ff75eaca40f07798dbfeaab28d5c3d91d9578501da3594fc11a57ff8d10bdfe25d1d44c28f1309a0b7919abdfe54d4aa5fa1615e6792f52479d7b83aaa0069b98e5debd2cac82a47370effcc8e56bcba0bc810a2aa9dc9dff51ba9979bac77c5c938cedabfc90d5113
+Qx = 0a69b652da68d88cf909971a5a1e426912637826e03057c23d0cffb3d50b6741fb2d04a4bf109cd97836587278d44bda7b91d85
+Qy = 1bd37bb38ef9b29815afda2b6f2de40ed9155c4bffdb893509f7c834625fd8d232ef514837fffbeb1c9cf0cb78facd8451a54db
+R = 058a21de76d438063cbe0b63f4ffe27f08fe68b6d874c226de33b3a99972b75b0ea2305b831a58cfcffbdcfe105a677a9409a7d
+S = 045517c76d3845d86b3580f026068bcbba02fcc269420aecfd5b59f270dffcad3ea67745e271b7505a448266f8ea2141efad7b7
+Result = F (3 - S changed)
+
+Msg = 6081864123200c15f6acdeb078d5044cbf08e95f2dc26c4d7ccbf860561e6dcfeac1c2aa55857c3a4c5c1b1585e90763b4a279086e4b377d68f2680d56de6281cd5f6f173a5a818033e73dffb2fb46fb903da567a7b24848e3ec93c7d175dad8473107808ff9ebabd6148f82f6730ca02160e17409f5876353c0739e35130948
+Qx = 0db899a2cb5c20eb3bbe4d4c96c946f37bfe1a34d7baeb0d671586a10be6a3921bbdbbdeb57e5651a24f6624d355c9e4dda2949
+Qy = 0009947cf5b846124cb90101a484b8946158b4f1e4ce6a1ffd17348ecc416b8923ef3308deee292ac61697fbc2e7901967594c6
+R = 0569162ad4da27e874cf8b074593f0d3c9b29bef9259f8cbb61462b623e2f721e98a06e08fe4e2b14c4fdd1523f660ff388284b
+S = 0bf600af66dc69e7cdfb6dc829196ab14c893dad7c2657c5e03595a41bec441f2ee69460a3229386bc6275a69b882ed4662a815
+Result = F (3 - S changed)
+
+Msg = 062d4809cab209ff46c54f8a7853366470854464b89432b1c0d93af838f45393893b6f94f29a2dc9a8b502da03982eee80e3deb17dfbdc90da50c669d3fb571b29965eaea994072890cf55e28cc084be9cce4c2c15cbc460ec77ed44f62d16b9fa45d4dad70409e184fb47687f7feb07072b37180c01a65da6d46b84c429c69c
+Qx = 08865cdff5cb9213a702ce0cd055a88b88d705d6c40322c305872f835facf2169914b26e513fb34003c7d1eb1e457ae35b565a9
+Qy = 0128e4f815edb39359c8c2bde514fb260ad44f245fc2c9a87a456e5dbd91c54cc0ef977b909a8b6fb537acc7788bbe050bb9764
+R = 0f71a253fe3040042390e24a82c3838ef079aa2ad377921aa389dbcade8109484b74bb470c56415ee12236c1928022bbded3722
+S = 024d4e0380015eddf01ccfd36bd0567c7d74a9fffd3629e2f5a99f5f8f16a39606619e267552f91e8d000a239b7e7d2ca187df6
+Result = F (2 - R changed)
+
+Msg = a1c4715f758d6213729329ae48f793be7253d21c12af81f74c28113eed169dcf3ab877555bae72e395cb11057d5d985e0ea5fc036df9095f20d337fc97cf931d1896d3425438a80c67da03c74c1040128ece6276edb0d138c940d1db6bc8fe169fc2179a318eb857435d24ce45d9488bd720588d74e48ad12d79687afa05d2d0
+Qx = 0c467a14e35730d9684a8837c63953c3bb4b5b34e105cb97beab025395481a931f86987e6d56045ee5f79ef24fa4f1c6c7cd623
+Qy = 1584c2a605a22c96c2184f055ed49a9a98c0a7af3921e8dbaada6e3e4dbe11bb15aadfc04607c940e871f2d8d363cc81018e79f
+R = 0c0b29a4a10f05b56bc572298a8004d82c2d277a4a028897eb759eb6fcf9dc8ea759c8c0f5b8188d19b21230626d7021cf11156
+S = 00f52457dfac8b9a4a12b673efe5de438eab969904e6b104ed4c98ab7bc50c6fee94c545ace72b8b08881cb8d42ea464f32b972
+Result = P (0 )
+
+[B-409,SHA-256]
+
+Msg = 856a44a335591da41c75015379f48254adb57c8989512a1d9babd7135adc43b4b3ca8e27c0dc98724f371352cbd5be0e34110c17df8f3f630045f504fb421bae8e4b914e03b8b85958209ab8cff9884f52514ec582532c39c54bb8cd0a50afe2be57f12d0dd5346ef5ec4fee88aecaef723808896d4777e540386d94dcf00cdf
+Qx = 06ba2b539430896d341eaa2f0655b3a13f0563baceed76d4d4f98b93c83ec071ec697061370f6fd8fe998cb194207172ea113af
+Qy = 036f4b8332f972348a7540d3b87ef02d57a74be8b02e47ed3becb59d56061ba64eb349578ba70e4ac08a9e3fb4cbbbf7c9dcce4
+R = 0a419619b91bdc0405e58fcc5899ab7d1384878e73714afaa1b186f5cf8ddce14e50e98fe1fc88ffba0c8380025b0793f898c8b
+S = 0bffcb0aa5fe71b8338ea7d05f881b131556c467b092f616edd3a2a8fb6939184d4730a99b8921bba295f4965280a2decfb1226
+Result = F (3 - S changed)
+
+Msg = 0414e7b17f19486f404e0efee3295aa5e2c2defc6481eea2950ae52fc34a355aa4c365c36ec3d4cd6cd90c7214c8f82ee9b465fb43c311b9c0dcdd7a6c76bac318fcd3d0ada26fed8b2ade4379481566262cc1bd51d2eaf8af7057b39cfad98756e971afde585216ec84940e5e5f51f120ef20d6f6c7b4910bd87878112df256
+Qx = 04363c9c1a9a00f7f583bbc3d1ff1bf554a7c58c02f6f8143726dd10c57b558054efb098d322ed2ee1322eb9e22e8dd0f76dbff
+Qy = 0dc4eb0b7ba0141f680f34e3430a263a26aaa22288b3b91faf327176460b49babd5cfb73eb800f7024949ccdfbfb749f147a40b
+R = 032f257b7aeaef8fe6da86b39e309918e33045063c2562056ed4382abc820b0b6b5c1d49554dd6dd881fcbfb7fb3e3bed5832ae
+S = 098579ad00f7f23d46873edadd5daf8d354ca7b9fb31c050b12a153cf9d964e6adc3acc4d1f320b42f27a5c926db05fb134fa1a
+Result = F (1 - Message changed)
+
+Msg = 7ee18af2b9966016bab65d9951889d6313e89318a969d6e805c9ca6d2f242fe5affb71bb6ac2c4290adeae714e6bd9fd37fa7b9fc3fa1faf8d81cf222fd14d0c82dc573a6760e46a2221992db55c1ac2043c34c1fc7e665ff677ded061a6da123e276c4c7cb02beb0bc1c7836348dd8e9dc0ff6b3a95d83d6b774475bb24412a
+Qx = 14f2feb4dcef360defa578cfa692a15dc97bfb98d2488f1a0fae06b0e99120cfcf9234b2572b4f5413c3c131a8855f2b01a8f81
+Qy = 1669c2e7cf3d4e56acddbafbb7c40ef9c16abdfb7c3ebf7fdecc17537ad3b0c59c65509a1c6cba1ccd21de9e1f3e9abb11d6988
+R = 0ca0d58e05d0f1bda37493bf710f46db297a7fb1df07596d20333b4d46623ba5930fddb939667fe193ffc421f1d0c49b52ac2f6
+S = 01df926b6c413edb545cdb37b202a0fd68ef6f4498cd4c936081bc1db2df1c75d7adff2172e480d210b89493c1ababfcea37a1d
+Result = P (0 )
+
+Msg = 874387cf1e20749493defcfcae95c49435546426df34a8ba66c305085d684a137a1d481ad210f14973c91cead8f585f2d83d48a2314e58a8723c82120f28d95707920db4e01f6606a38a34bb9c6c36e5df675b3368a0f0337b6268f2cdfffc07eff230bcbc1107dfa34e2093e12911e69596792f63d641de57f9bbd6a592d420
+Qx = 1fb40a0cd4e1b5d535477675ebd5304d3f5020982ff2d80eb1ff5e2cfdc92d688b61e09e304b32af8a3467f34e9dd4fa2f71369
+Qy = 12e6603819844ab9ba35b29a3eec9f4198bda5fe0b9dd9a89a8519d01cf639dfff88bc75c914227e721069d8f27381b4d173c61
+R = 0d799c39b309c589d4cdd8fdf469e0067989e2b7c077a021603098da1ea3d31e5f8b4a783016a1bb2fb52bc74dd5a4883e5451e
+S = 054693269da88b3186a0c87dc2469bba646294f8f277a4e5accb7a0b2cd39c3412b272db99fd35a65082504faad15a3f2eb93c8
+Result = F (1 - Message changed)
+
+Msg = b04122e3c94348c755ea17ac6cdfe2ccb549d9ec92304341d4d5fd0978df102ec0ab3508cc2d92e1de167542e597a7d80bfb31fcb97ad184c83f24e5dd1f15ae853f493a9af1e0722439fe2e4eca0c1ae31ad662446377c5ab4e8abd027e139654fe94c3c60f5d6448c6ae98378700df1396bbd7fe8081c09e644e938aef9b32
+Qx = 06decc245e7dfbde1d27d3ea74e5a4cbafcbafc32b38ea014a60dafc8ef45f4b00692e605ed5fe8c9640675f98b39f2fe08207b
+Qy = 006192402290accc3a831ee61e5891384320631545c71e2dd09bfb89877bc27d5e38d1449f313e9939a2ca1602f7c739276f702
+R = 06a2ee6257ac7b00ac6b980845437a69d91ba21f35295601e84f46a03225ce053ed454a593ca13ac30e7fadd73e47d6d1c19f2f
+S = 080b9a2e207a49bb328f5842eaf1e9bc4d01d22bb8b26df92a930f1c2857b2ea0a8a51b43ef887caf5f14ed413d4b1f1d8db991
+Result = F (4 - Q changed)
+
+Msg = e375c09fc60bfd51f5ac9e9cfcd44cfafe3fbf79f071d3ad8a2ef456886ef7eea099a9c405de1b8711db47f20ff9c2a47b8f9f0b0eba707c39b0eeb25b1e3172d8fd025dc1dbd626d4357c2391a7c05868169e428e0a5ccacd2b73161a2a964bf7f5be7e743788c45568a031fe6238a8b0f816b17f61e4cffdb52be4e6417799
+Qx = 1227a7be491fb697af4d8e29366e6d4e9fc4510d3808c82c6c07b87ca11e18b4d92b01d7b61711f59a2f6957555b694a342a9e5
+Qy = 062cc77b66ec97e8d1c4a8d2aca038b3a05d49dc5612a04e64385e378c4c43554a96e91ac760a82b1e91234bcc9edef43968a90
+R = 07aeb214f26622badc3afbeaf5573429cd263c225c1bc44acfac46b70d527489efa5cf2a6caa9df21538a8e027410fe68f064a6
+S = 01ca4c317fc098956c8190536d07835b992f1d3a996f6854838ac45a75a67ed6c075b30e6dded7c555b3b2b5477f175eaa1f146
+Result = F (1 - Message changed)
+
+Msg = 2fe892c28e6f5d807c9cfaa23a8f7f316b2ba6e8d91790796290a77a70e0d2eea60ea53d9e91107b0da7567090efa6320e80277f2336e6f946a1ac4a53193d441c2434737e82bd03adce9b3ba51d649cab1a202d13997bbe4ba6a50bfde654829c64efca21445faf0f0296befad3f628d74cd4a60a5d22ce25d4233221af8eed
+Qx = 018295bc581d38a8c3f0eeca4fa7e4d289e84a09f6b510ad626f7ad7acaf028f0b589239e459b530e1fa509b4c37b0fd553d0bf
+Qy = 1ae9c3d6afc599634ed55d5d9c383ba6e5ce55f9b869b1a1d46521bdfc84f5ec77ba2fc1287aa4441d75d6f870a7cbfaba16a6d
+R = 0de09aff902097c0a24c06e64cb8dcc77daa596efc666c60503e90f0a6d6b6f844b993c60f624489f14fff5a6e5b0b0887046bf
+S = 09b0b479a19cc4e716c98cd01ffd9e20b40ba1edb5e203f3d40c0e3c5e5da0bed256f24e0f718dbac464ea2fd79d1eaa8ce3d91
+Result = F (3 - S changed)
+
+Msg = 9b71ac6d8f7eec02a5fc51711f444ed42462c3b7908b808c95c5e59fbbb1b8c63d0b1b3c27e2a518e536a07e895fde8bd214d5bcf38fb72b821c82653298e75123222c095b2094c1eb2487a855d7f9829f522c1f4d6b75e34e33ec1988a8a03328dcd6d7d6011ee84034899c39f7d15237725eb7a491de71caff917d8da80027
+Qx = 122c438a9c28eb032790c8b7955f55009aa766acc1e7db1f42258492049fb4e428655969c55b01c44c85153dead638ad402dc15
+Qy = 0b05ed292bf07f6712abfb3f97b46b470e8627a3c7497f2b067c2a68cb07dd6152b73c5a60975ae759b861cc2e1079a8fc0af0e
+R = 0ba329a18fc2fbef8706beb1067f3e55eb5362b8748d7c12c578d922f9c8aa8845717c4b357feb7446863369ef27e8936fbde56
+S = 0587ca1f4829b646c4b1befb2912d5e6c270f8b18f85ffcaca04eab6a3ea0562b901f54bb92c3039fd60663327a0dbf8c0e6765
+Result = F (4 - Q changed)
+
+Msg = 76dffd7ce42005c06feb20fddbc8718f18cabe5eaecd03321748f17e4b0bb8802bb2743e51260585b679bb7c694e0e3c53adce69270a590609ebb24304166a26d6bec5bb09a376e232931440b4fe44ffc48c972e839027c3ed483c44868a4729e3d50bc1441beaa41ba2da3da1311f32fc73ec4dd65b6f2aeabf1854b43e04c1
+Qx = 1361960653e6247c68774fb2014de501c155e5c856a5d4dc1432d87e3ba01bab9aad677b8e1b98c42e2003e7e3423005c78d343
+Qy = 1824158302531d41039ba3ee420fb436f3552aab746d13e12e41fc5712fad0520fe38eee83481da6de845b66f6a0d06d1c92ca1
+R = 05bb839f94dde778cb06b951e871fd53b8029afd21d7afd35ab887f6d5413e80e7ed7fbc0ba1978e842d4d3925c193724d95177
+S = 0a7c23cdd0d0d5ed10da75af7821c39baab38b83d86dd72113faa2d36e947050d2f238d8a0cab77c46e1fff64a602d3f9048952
+Result = F (4 - Q changed)
+
+Msg = e7fe36f14fec6675334ce5789acf11f913a3125a9d8fd7dd17d2407272709e82d20cd56bd057bec503c648bec860361c032f7aff66f2f92599104e458f0be199b87703716987970659fbe038b50bffc6a5cad7c75a6ef02bf3f4d56466e8b4f41d10427ee4e4351384987d1ad4ad3486b46dde2135d3619f66d9fe14ba67c038
+Qx = 0374339e807a5039f40e5cce1431e647acab612d800b751fc3520563b75e3aff321a8998d3aea7c7d5536bb742986da8774edc9
+Qy = 13a4c6f2fb8c57596241e9cb9c24d9409ba07ee4096248e43ebf9925978fd6584543387714b4db4a991ad665401996e2b71e1ab
+R = 00c2d122419c3e4b16adea83f58af7d590788b647260d84ae8f5fca2644d2b20ea6869a783f769bd5fd09f9577c511a7a0f321b
+S = 06db6d383832c45a5b73b367d34dacebc55a96d226ba17a12f1ba27f2d7b6c0c9d4a7210fcf87689d46e86c8b851fb2fce757b2
+Result = P (0 )
+
+Msg = 29cda4b1f10dce64a886a94a50a1de6765ec9ad865bb1a02d671e0e7d0a7e332ef0600df9dddfc0b35ffc82aa0d214997edb70a36a64c1bf667646b8fb177700d7a7aa0a3010609e89a49fef28d475e514a44d5c6f0e7418b6e0b4fd4965ced5ab546b35a2a9dcb5964bef9d860adbe29361ff01a6c39d8b65df2d9a25260eef
+Qx = 0d769528fbfef25f18263fdce446dbfdbb384cfefefba9708f9cc8de21660fb7ee0ec4ee8b9e0ebb4cd98837258bec22a9da1e7
+Qy = 0cd1c24efab336f2182b9aa4409c8bbaecd6cf683c6cd9d3d73938477dbd7632db330fecc22c1a7a3cb7a0e7e7bfa6b1a152964
+R = 04604044a42b8d9a13dc475ec22fbd9b1d728f969193fbf42328573ab541a7146c91ab59adf2ab0745083e8a0790784ca3d31ff
+S = 05a54f4a2624cbc887683c85ffb143381734b834ad69e6db44b0267614f05d8218df038d5312be4637820454fdb48e27176a2e1
+Result = P (0 )
+
+Msg = 95c0dd2aed9986f4a254cb14c6afa856e3b652513df80909e86d310d57e58387b30935228f5a9de864eda199ea5e0a10f4b8cd23aea31a8fde7b538af3649a1ec71481b420e8e0f990eea951f6dc81679a8e07a9f0de7405ead09d35f8d0e4f38aeecc0b5aa047a457f7c46aeaf6e3bb36df632c213398d883c1f8e2ba57a964
+Qx = 12e33e8695e51f3c6e1bcd41fce47fbf1c47539b58b4041ff3222e0f3d04de3caf8e0030f01b22782980cc691821dcf86d88187
+Qy = 156a14691effdf1998c877998204acc8da6f703bf23ca0bd58af25b0ce2d94a366088644107fb043650d62d8b90844d1fdd302a
+R = 031b5044ace69b5cda8af25c584f2d0c0404e99f15a7374b5bc5e6d0e98928283375654b53af92485c9b0a263c55572101f0f2e
+S = 0463ec16792aaae5cd2b678d65c5a1b1a657695d4b7451cf3f919d9f1cd1dae614d09abdd57667f48d85a239eecd0bf12b86c7d
+Result = F (2 - R changed)
+
+Msg = 1d35a9e7efc7d6706528ac6ebf2cb8e4723d8dcd091edb5fccde4827d09353f1a1c69e2d03606d473e5eb3add7029555426d33d49428705395f64f6b5f9efc70725a0348a0e2ae52cdbf1b52d96b89e4cf7451b800352bb42cdf98bd20d6a29f84f7b09af21ee8b2f86d3b160fc02def7eeaa60d73d15bb5e38a38de44595a59
+Qx = 0b6885f5d2935a9c24cd052288e8162e0039d6800479b93fe24125769d709ee4211fab2c141d147b6a6c23c7bc9f863b5a61625
+Qy = 04291e2af5193b82d9415535455149223b985d9b06d664bcb9eeed273c24d9ae9ff906ddfdc0c51e91cddedc047749e74a3bb2c
+R = 06b1f5090f7300c8fd4de8ccd62fecd5f345bd4138d17f706ce369a122c5f1ec9d179bfc9e9c8a70b0089d952b96a52a1b019a3
+S = 0b6edba8616b6cea15ffb5c1c74d8eee07570c8616b1e73f7ed14ee6692b9f793826895a04611721348eb64c479e95e9e583346
+Result = F (2 - R changed)
+
+Msg = 99deaca1359dc8e21074245602e1024771339063e3cc1edc81ee40b91aeba2f5d242cd0272299d531839747988a0e3f93191459fdccd78e3e8e6893d4ba6594400fc551789772ec809d9dbe45fa5bdb4d30925bc376cac1556e14181fdb784ef3febbd88b6e2b2a08f6059c4cc15176ad5d4e72baa10fb19cba56c87fecd4afe
+Qx = 057e3ffc517e96b4b71b774a5743ec05147fe9aa9642ba32eeeec363a29a357e4c296b2f8e6ced2102d4ee29599be8d475e7597
+Qy = 0d7ef64925c9f7ef35c88cc8d4984741cf37b63bb7a1d4f5ac8acbd34e28b6da96492552b6063dd628846cc3f8d97b1fff643cc
+R = 0f9688e2cb0f4401a5a07465afed8e98aa891ead540a5e6f7aed62df3de86654e1b765c22af694112e08e62c44c620ca83609da
+S = 0b04b5b9590c7bb01be7541f535836ec24d09c9ede7a66f225003e8719674ec82a162664bf13f70c3e685b5120d0c3ec45d7b78
+Result = F (2 - R changed)
+
+Msg = e770bb7857eb3ec881ae602f74073be0e3779e258753ba1201a90c8bc54fb3f2f6e37f9edc109c86b00523f56aecc27e3c5cc2a1d471244c84155390cf0586503936b113ad2fbb42952a56b1cd82dbe937ef62970fbfeb7da8e110d41ee878b5e40f7f6bc10baf96b3fd54ef4e6e176f6c0deaa4c1ad6015ea93e8a2743213bd
+Qx = 151f2a3374e05d9845f5ece2e68827dc9ff3c4063b7cc2c1e99dcdabf58145fba6a40d3e91efba7ab8c7455972ccea5a5dcfec1
+Qy = 1048bb2fc1d3625f6b63a2d5139cf734f350901ed95aee261c949eee191eba4f1892da3d6a0f1598c1ad5bb958308f158fda621
+R = 0cb12ec484e104074ccd6e1e595a84b193dcbd7af03c8d6102ed0f20e97afc8836cce6e73dc1ebc183fbf526688401646dfcfb6
+S = 0da19fd55bd21715660fed94ea7b32e9704229c47d12b46fb10760b3324502bc0016095d6b8eb45f5fc5a7e00aebac4c4db6ce2
+Result = F (3 - S changed)
+
+[B-409,SHA-384]
+
+Msg = e9dd7258da72c0014698e74230950cea7f25d6d135e643546cb32205f465c3faa99e676476170c3c67cbbb54ba2f77da0fede73ff7933433fae7d9ae87062c44d761723a9214c40e527456cede952c0666a157a9a6e54e7c6aa30b3f4205130a8bb195bbe12eb9344bba3df57f7a111381a1a2349e569d11c46deb04b0e59e37
+Qx = 13d42243184f51f02c717b89ce7567069aac19e13d8b6308a4a1e1a6acafa2709ac4f7799ebbbf791db0cdfd72c5f9dab3e032f
+Qy = 1ca1058823ec4c85c22621c33fa5d954cb0094ba7e6d6df120613134e5b56d81cddac5632a2b271a8722b4a1a5e28b1efcf6105
+R = 0b1cdd1aed728b9b74f03d25554d3beb9b60863fd938259fff107790113288201158a5bdfc4fa40f27786c84bab02bc9e233074
+S = 0ee14df6268acd71a53a307f6999ddd77c13930733100b12d33f03c790cd4b62ce65de353f42e9ba324f88340d08bd5caf4d04f
+Result = P (0 )
+
+Msg = 514564888c729a0e35b811666c177a418f2a904107b28cd5ff1a835be696cf8e6fa6e239ec3a059ce9519c998774cece8c08242cfe49f0e680b108b9eda4110e62f10a285e26402aeeb04472794c717f47a0946444f8b3e8b981a6fb7e322cf3dc9a3f45593b15d9676ac130769a46768da78dca67c6faa28ee6da22641ed931
+Qx = 023391dd6ab6542fcd676366f33a65773bf1f1d8db7ba6bb20ac40aabcef63ff907a3bdb5481f41102511495a96f131e1a3901f
+Qy = 1c8f6ebcb061dcc2af123f5a5df9e72877ef793c7e4e4b19ad7498dfa8c20307af5d0185fecdf83efc7eaacf871aa47d7d13c40
+R = 07d9d0d09a6b5c1390ef904956276725519eb2f9ee86dbf97a0a47c0d033b9a55b0610230422cf3e908074cf9c2956ef7398804
+S = 0751b7ea944c31ba082f2435671357f406149f0ab2b815c2cd4d8c2344e0e17bcba111d734a2a90975caab0f482f0bea6288c44
+Result = F (4 - Q changed)
+
+Msg = 102cbd6ad4084084876fbf72e368c5d148bd65dfa8326ab3bdbf3cf2410813e9abecc2c6a94991bac75244192d6a40248f5f6c89038371d26bd9f5a34f228da990f711dc4c7fc9f3a96ee94a393b356f69c98597755d2cdd0fa0f6897c34f4983700297ce6f53b8bdcef61573d430fb297671aaacdabac738b8dd879e51d647f
+Qx = 03007a79d4eca0884831db7f7e0dcdcff8c918bd244b3bf357b855d47d6e6673cb66e1fec8127e1fc5dbb3d9cd3b1baa34284bd
+Qy = 121b2475bd414d2875e8146e2f8513af2ea95b99b4ad8d7b7f4cb753dea01716ffe83c44ee98cc0199b82aee356ef97da76e102
+R = 08d7f5b5c3851b601d2123ed0d3331f9380024f9a988faaf64761387207188b6ed1bc783ba405711b4f301101023fad9892c0a7
+S = 0efaf9fb4cb186d7e23134841bff25c499e2cc0d3a8a9b773581e346df5488394830e63a3c3d1d3a8f6f16596a1d8a63d15ba7a
+Result = P (0 )
+
+Msg = 43d1c8b133d6647c70c9db96e7a69e060b0fa6cacc98bbb55fa2414539b847934a88c704cc526e47a68a24f5a9016e88ab89414b4add38bb84c8b9574c1f38a39b6a11675e3d75902818269113f57b821ebed8ee01b3e27ff63700f8c9048ec2ad414d2ca160682576260cb85c396f16061ccb71f3809ba0d5629dc7fd21b910
+Qx = 07f714d34149128fd0f2a98bfd431198d14389df968bf48d70ad85832bd8ca8cdb496da393f42a89bdbf9af4370ff97091b9751
+Qy = 1db75b3f2a7de7fdbd4422d988c9b0f4ea613cfb297539c0b183a78780cbf240d63e4c3523e20deb1b13e515c6fee51c37e7b7e
+R = 038149ca31fb992fef053c5b83f3ecde95f15bbbaffe5c3eb5b965977d5296f13c6b5668961e365a327f702de920fc7dc11295a
+S = 0b8d785c88d06e0e71e00bb14a7f4d8e026be90387b3c2186fe1b80b38185748d40172cd021d4ecc58258f9e820cf52b15b45da
+Result = F (1 - Message changed)
+
+Msg = aa0d0e12545384648d600a9970f2f27e88fde43a13d0e31a500c6ff99f5939d521ef06e2d63c768b42272d98e0047927573328674793ce9a723fa143376d318e7225e1f75d83006a9a1c7217748018cf13f8ea705c730ac7c9caf7daf62319c94539e9355fa8c6dda28a7ffc38f1a8e15471e4556b6a0b3020f23b1f5d9ecd7e
+Qx = 1a85bc3384757d1ba78a42dfa96135d2b47e730c184950aff1b656bc1b147372d659ecb706d39da1e65e44a45db26110009eb75
+Qy = 19be085a4d697663b6bf7ab6aeacbb26e3f1a09a715992e243d3d24ee0ebb330240fc1ada98a0504dab9b1b12038827c30c77c3
+R = 09d1c80e79bcac38c1a3b4842e86d78af39001011f2cb8f3d3140f72a506f1cd5ef6d385b0aa54ce08477f6a91e0fd67b080cfc
+S = 073cd3c8fd4e1d224c05cd8ba6b9fd1ab5460233b77a23adadb7d0a7c48364466c0d9e6b4c035312ca4e91b726e963b99243118
+Result = F (2 - R changed)
+
+Msg = c91a2002607c890929acbdb2785bc36c3916b74c85e0e666c64c9719a8b1ba92ba1295e1c6f4dbe4992b4e2eee0d9689de9a5ffda2ad98ed4b3dbdcdcfe4df83a61759de3970428aa8a539f3c0dd60f3d3e96a136145a9d08c7798370711f81f7d773b589d9002ab412e5b05cfdf234dd5c6fbb22150abcb1b3c4d46a8faa7a2
+Qx = 14bf026a050b320036d21df25c1c5b6d585166d4a55801f94e158ab3713d94802db5221f44ed87d0b3fe94682ed0ea03f163415
+Qy = 00e3c494ba69d6ef0c46c0db5d5e9db1b2d102839e30d60deea241fd7dd7f03180367afe1dcbb9c9bea8a5c3ddd22085404a781
+R = 059659a8c1ccd32e459e6fabaaf243a440dae46f686a013591757efd1a69301cc2622bfd2b53d58eb32946ea74047f12a990f4a
+S = 09fcca1163152979531dfa403cea0ae6fd9bd074df532a9f1858ca0e3653c0cca4e6c17952032b23b4c6e21223a5e6cdab58e1b
+Result = F (1 - Message changed)
+
+Msg = de7a4fc916dddf4b204a1ed5f7b183b8525874e74bf46ee0c1a33da1965f58f8d91883f217715ef282136c0a63954f0bb994c7e05a949dd87a34f096bfc1ffe6e4a9578072f6990f4a74b666a7468adaf7d8221202928a2f563977d04514d41bdc30fb105b414b26f18819e98ab3423565fc81ad360f798c3d35225d72c0f4d3
+Qx = 103d2d95a007dcd13a7dceb5b670e24ef0cfe134ef99f317002b81f06fe3dd97577ceae917847633538012c57a02b538bd3edf7
+Qy = 11000b9a3ebf81609370a1833b98d9962b06abfc32eb6b8e43abec86d68bb0f16222e928b72e7defc4e7a62cdb2cd37d46bdb7b
+R = 076c8dc25697c2ed358486c741023cf9ac723de3b1b1108754b09912cf33403ff512494484092e53f07fa5ecb4d65731f3fec08
+S = 00da28b0183b3ddedc71ef36d439b12bd32d5e6ace91dde6222965d41820eb04835a2448c5e9e3a5c9a4d0eeff2616d57f3a459
+Result = F (2 - R changed)
+
+Msg = ef199dcbd584d547a897f41b1a722cbeaabb54d71a5e59e8c443df35247f1018c3e6236ab99e95c54a29bd28482056126673047af0641a94920fa38edff111061379f719392df12bdc4462671e3585e63d12b81246d2cd86bb907b0faeee1d21dcc67fba621e62d8ccffc571df65bab95b4a55fcfd9d7278cd33270b9579d099
+Qx = 187b5e8f39b9c9306e8ae26d212c1161a47ba6ca9a68641fabfd4a88d31cbf279d42f5b727e5fac2555e3c93b72c6947204cd71
+Qy = 103cfd0e4d124aa55abdf98bca1dd5e35400da18496f46163291e1495f73aede6961333063c2b8f435f62ff5e0aaca4f576acc8
+R = 0a872468e5230b7896871b53ae62162fd8dc0a0848577522967c071a7b0a9bdf7061b21b6e40b743f94d94d520d046a1b5d9b59
+S = 0b652b24f054019e7651e9f1dc33ecb968d07bbc470bffff3ad49b0f19e423412a69bdd6c0ab150bba9b42a2cd3e27a8b60f556
+Result = F (4 - Q changed)
+
+Msg = 5e365db1e4e04561a15090fd5344df0d50cf10f556f13bc9b9912d38ff04371ff56f1664b7f9937270a96745b7bfc81f6f146b3181d6f0edc5ad4c3c459f580b92a0cf176d2eb56c256acf4d24a93a7672eb7a2fb6774d7cd3111fc62822b9d0d3794e105541680b640b60749e59d1bde5c4b743c84abd4c5f159da8b94bbbc3
+Qx = 1ca7cf38c57dd400c8dee34fa01f45f551dc0aac005aee207d03f7b3a93fcf58416bfffec5bde70cbfef5c264886b424cd64d1f
+Qy = 0681d31127e95dbc983100b92cfe964e2b0dc86684f6c7bcf72a47b45e1a81dab3e5a087036528aa335b83f3baa3571a09f7ba0
+R = 09293eed260d99553dd6edc28cfcd26173ff272d54cdd13b999a136eed383c670f70fa9117d06479059bb21e7bc3aac4ec473df
+S = 0254e2664e30f29d5f52960240a01d0df61a750695c9301a7f5dc07ad037b9a3f0ae46ab0047cfa0f2b6a2d60966b3b2bc6c534
+Result = F (1 - Message changed)
+
+Msg = ea5450a2a85783574ed981a77cc9c1766389ae02295e922802de1c71f17455f205eecfac4226d4f11b36881a312fa753aed2c957bb0c04dab82cb2ccf3da71947310e61036179bbaa852306f9f26beca9cfa9162ebd2f1914ecd09ed014a0ea5cfde91a61ab85022a31e9f22ddc8584b5d57457a04f4a46d2cfd5b44bb26eea9
+Qx = 12bb4e6c73844e7d61c63ba67422da6f40519dcbeb7c22ecd373d69a9d5b266d63e0599659be8b51de71ca4a4e31d807105bde9
+Qy = 19a06edbc425be2dd12b8745099250fd7f752423fff5168fbcb5464ffb0a2e26a1d9aeecdcde7242d9dcf3a5ba31129db0e78dd
+R = 034c62e2d2817cddea615376d072891dfb8c4c57e30738d7cc83f7de1903ecdd7f5ce6812d2ba0d4c31f4c27586ba2dc899e097
+S = 0062aaadaa76eb9b61191796558846371a44f6b5a6075f9840cba6205bfbe6532b20885967ddf77a65c6e35a962bc3284fcf88d
+Result = F (4 - Q changed)
+
+Msg = 1228a46dbe852e9380c381146d92554db17063cb82fbb7573fcb9ed054870391b41e098bb21e8c0c5346c7680aea52777713e1457ba5aed6bcaab0d0c11c2fb1be55b2891d9bb611d3a20b64fcb0b1f283d0604af61944efec441055653efd04856677404bc92b7333f15f4d886d58636ad7e246078d74c62e72badef8115b78
+Qx = 07121984a9628d85606f16abf8fdbb8a7415fc9584a9fee2cc0d7e4065462891827e8ff23b5546ace3d42e62e28c9499d9200af
+Qy = 18be3aafff3f63916a0e8cd15c25a6ad0c8c16be5008f34265e606f660dec4eee0afb856f96bc2e4b20670907bbe90fe76d6da7
+R = 0c28aa00212c00864fa4a50d2a04f93a1685a4b3adc85f94eb0d9b4b91232ac809c3f9a770a120924ff2049f86b679b449c9334
+S = 09fec5f7dadbb27e6883eaa57ee90b5fc7ac63fcc5bec97cfac91c119b48cbaa3f37aa6857a09cc7b6d956a07ad525e9373c5f4
+Result = F (2 - R changed)
+
+Msg = 19aa9ec4896232032a32dd589e2fa51b9534107003f4d24d9fd8c30da5d85e92d3c6f53982bf3df942c849ff01dd987a953bcad8e6e8a26ac268ba04d00f7846f9ee64a3351bf2a58bf48a4a0eb36005a9c2496faa2ca3a4d3b2e7dddf2158767a0d2d8405e00adeb1ff7709a5ae9d7a038af2a7bc09bc8d68a00b50e96ecb85
+Qx = 19e1338dffa5ce79671fea187e127a33e1ab8b03008f2e07f832700061832c99027ae67f328fa1d5ee78a74d4cd049face90607
+Qy = 1ed0543c04004a0a2ed28c752cca68bde6ddc1cefba90172411c1b12bbf6106cdbf8efec7c2bd9c5a385fbc2fae01962efee041
+R = 01196365b0cca203dd3d57360b8c77ae3adae52e5c5118c28f91f9fbb0cb06fee223c8e6a60fdff51ddc5f0cab635e192ab89c3
+S = 0206f85cff82ea056085b58e8907a3d8e373d64d78712426eaed4211f70b4f9ad335740040a849c461918d54380ca353bdac9f1
+Result = F (3 - S changed)
+
+Msg = b82d16e9329ec90e4fcd1feb717f3e11ecbf40aa7948687332954901bde091a87d6b7d9c56c0f958996b7b221ea17398e0b0dbb007ac5cda110e4b0ba42f1ec01e377a81bffc0004a23180bfabc402fe744980d5ec12be7621375d28f61729807714f5aa025614efaf662f833bf999eb82c956bf02e6a1bbe74f13e25ba4a300
+Qx = 0de747b42622af0f0b30a9a8d36ef6c9772c1ad1cce3325bcdebfdc61ec1a4f3f23ce1a9b9887f0cd2402e647c7bc12339fec53
+Qy = 169dbe1859e722c9f6640dd45a8f4a75a5225c6f03441bfa4aba07ae55a704e07471f8434c8063e090de4c567135a8ed2366454
+R = 00f171313204b5911e25a74b75b04536b9ebd03633ab20e1fee0df79ff294beb06d3223524402f5f8aa2b5b9726fcf9a79be9d1
+S = 06536cc247325bd139c9bdfd9b30de2656b982116895f883d86e6abb6a0d2c3d2ad0af8e86edee52aaea58bbe00a1153db0bce1
+Result = F (3 - S changed)
+
+Msg = 36d0277976a6f3f61d54b39c04579d6cfcaca6b0cc60c71cadc2234c5cb941bd93b5f7f01d77fbb8eff8fa731e8ab183945b08ad52b4216216e89d950786ddc90abc2890e696c8d12ea388b875eb76d190d8534bf1fe02a17f287b75f5e840e372adf507676edd55374e4776cbf0a860f27414526bef8cf797b7cfb2864f48ec
+Qx = 09595b07ab2a9628065f49c468672a1ad509438fbf318300ec024fcc3857e69103f7a893ef60224e60f05a4b7ef6dafca56f161
+Qy = 09b7b9936172729a5ec2b5daec296c3c7f5ecd150ab2ef1db2a73ca7821f5081809d775e2288ac0eb7847a67a348e97ea830c74
+R = 0a701e37e60ef38d024e6869d48b58eba301c7b9bedf478b743c9adf9b9bd8978a2c96275d469749720be57da541f3d012a9e0d
+S = 03980cb763f543b44443ab4f30eb39792e7726e94935fdf25c225a16f04687003eb6b55c77c0e0e957f303d1a65a04d12c1ff2c
+Result = P (0 )
+
+Msg = 103193a7da38896a53389a0d522268d62c602fa00716355f6f986ad560bf6a45ec5afe45db96bec1b6c61e128e5edf5821c7f985d1497ca5670e62e3ac60d02ff62ec3d5565e0bbd382d931c50898d90b5e991c170224c2ebc2a33445a7bd067afa03a5d2550fe340e653aadde62a5f8469fdada8f08be6c3e84ba842a90a461
+Qx = 1e25ade0039bb05d30e017789d68aaece02d504975e5a380dca85ab178a6d54a08532c3e21d5593f2734fe60fc707912781f9d7
+Qy = 04068e4b7d87011b8a85eee780a6c88cd0407cf3b956eb1c394c28e1f3cba5b707ce3cbae17f1e7fc3414f8f05d834197ecc863
+R = 0fedf12a9fc6f9d9b665be6f399ab50e17fb744d1cce2a69a99cbea5b0c81ab9c526b928d57d5142fd2b950b73ef3ed774bacee
+S = 0554a70d6770fcc41a328dfd55adec6b7a0acb246425daead32f32ff7290e70ce7b0ae87d91aa5380e7369d35090c353d487242
+Result = F (3 - S changed)
+
+[B-409,SHA-512]
+
+Msg = 8dbe5bda443eb307b101696b465d668ba148a7425995567ac6b54a66502aa7d0241eba723f9a5626b8f20b928e45b681fbf27da13c1bbf8564876c207a0cf1a99a4602574d14cb5b1df1813876f385515c9d653952e1c97aaa1bf684d984f45f0adb797b89e8ca7f67daeaad77830d4a3127f1ad810faf3419c7e21c2f072a9a
+Qx = 1c9c142354fb25ff79e609840b872224f0536e215243f652b69681eb33fcffe55fbff093c67e146fd50566b0cfbec338b51f827
+Qy = 156fd088e5032478b5f7f72ef3320d004574eb3817db8cef6a62ac226d0e3bb9419536f85550c8f9112a674a53188a6dd0a531e
+R = 0f209b2032ab3081912e8156de54e6aeae44aa1528a3457365b1e2f6019acfe2ebb4ff4dcd4edbfbe45ad749691a0b8964d3a1e
+S = 07923da133846ecae257f7acfeaedddb59776ae4f79e633572a6a3b82b5d4550d10c41dd67d3f94e33e17b1c13ceb25fe3a7e47
+Result = F (2 - R changed)
+
+Msg = 8b2bdfc1b7ee9315372721254382204010e8d130613e082614c379f0773d190ce5476aba704f0c114b769e41ac00445756f566c1f8870ad8ff2a4b5a554ca3e4964eb963b5fc74290a51232003c25392c53aab2b1410760686124a9ef7b66e1c602cce2a7ab1cb54d7fec2ec3cd806c33654d398bb87e89f8c31454add624384
+Qx = 1bcfda449a8bdc030a2f650b8c7641590396ca06b26a489bbc3727016678ab8888c6aef361cc80e3aba5ebd49516c35cf736331
+Qy = 1ed418524d8eaffe2a746383defbe1511c77d13221f4c23cc927e45e3eb7887fbd343806557827a774a9f484549f19072c74259
+R = 07ec071d00fbad729610d557009c6b7335f217c13bb94545e0ff4b12ee43c5531c058a1c546a95ac98c1f35aef9b174dfc30aa1
+S = 031d589fab4524d0fef66c9f93341a855706ecce54781c2f7b3335ce512c7138483826cd666f997e76d64c7de4165a301d77583
+Result = F (4 - Q changed)
+
+Msg = 205b2710b2a9691050cfc1a48187bbc16e9c878d4639f1b6514c0ddd55e1acf457f19682a6fa8682d9a4cec87e8090bad87c1b58a96bb5529c71cffa7fd9c2b689f1508e20522e325ec077e1ee2f0c70095090b06b04ad3e14bd98584860a030e835def2e0410c591422f75841f92cf48e66beb19d4fa82e1ffad6546882eace
+Qx = 13d96e91911e2b48d0b848181b64bc3530bc17ab993ee3f5a0a23481ca2c7b9f696f353ccae4064e07bad6692e8facb97f085b5
+Qy = 1af27231206d896f68df288fc31ea600f3e8c33f222250d2c9150286f8b4bea8f0f320e34e82a0b33dd78628ae80d41f28c80ce
+R = 0791e6b13f267d10c832c72082db5c1aa72d913107cf24e85fe06c17afe5eb2172d551313e36095dc51cb661ec85d811dd77eb3
+S = 0814a827d34d77a8417bb556dce63d864f1fc7bc1f8026a545da747bdc62192ed2ea75b7784849e32f17011eb3ad840c1963bff
+Result = F (3 - S changed)
+
+Msg = 03777daeb5fcc8d148c17d844098e8ce89611fa8fe9f21234a84c6b8bd52530f86223260be2ff3b94d9dd89b15494d64d827f14e4bd7798bdc21de1ad4a9a9d4a2b74f7a8c7c078689fbb170d6b69fe1d70ce8f72651657a4b03945f99d5997863004d06d4c3833b5167f5f81d4f74d0b22f4bfe259e7bc73db83c5ed834ac68
+Qx = 10a62f1cce8276bc0264b1dd421b0754f3346e40c158471056ee453e0528810dd232881059d360b291c6ee5a97c5f8d040bd1c1
+Qy = 18db2f51b68bb5196b535e81506cbcdf345cad7ca37d66473e897236875198aeca0389504d3282848a7f48f3cd71c8f26f5d325
+R = 04d878c47f23b80ba3f0ca031ba0917d89c0003ed02cfb17866ac6865a39705331b07eb95718125649df9d98233564b9a0f2d7f
+S = 0b37a550a20399d7e1ad8d9a803a6f5f41fcc7f9e5d291f93c13b35d27d1f5a2d251560979a01f102e218f20e5f4ac2aafccdfc
+Result = F (3 - S changed)
+
+Msg = 31aac653d0b46687b011943e081deaf3b180e448d6909316a165580bd854a9188d1b8a0bd977dd17f49a87f7427aa7ea04384dad8a788ecfe602b483fbb68fcb68997fd00964458d447babf565906687f21efa5018ca63d18c58271cd8194ab9aeb28d5e2406bb3f9899e2b930c17bd4b2a2b3a0f0cf87777f502e923044746c
+Qx = 1c63be557162ab06718dddac59d307a5e89f115f80b8d0ece41ec3b9cceb9cb6ed74d1b0b37f4fc3692edba0c8fbd442ffd7fe3
+Qy = 13d1a9e8bf9857a6c0e9c93d37a49f65e464edf6ff38e1223cc116aae08018b65b5441367bc84aadb08df83a4e8a4ebe57cacfa
+R = 0f2355c6d8361114b48cc3d299f5b4cf632e4c6f32b799595d4ea9cd2fd87ba5c9ddeb60511ca2b4af0b1d85ad8f755a6e29c27
+S = 07f870ec88109c0c47aa0614d5a26b7686328b4f2f9e52d90bc70c2ac84223898f22d0688708dd8870d4ec07dcaf8d47a531a71
+Result = P (0 )
+
+Msg = 2af042fabef92f5a9435f9ec93d302ca7f50614224689d706eeff6602826d1a3edd2d744349951fedd7f033525785ee4be5d32b34114bf215a81c2079c0e7fe6b9f4e9baa5dff19c4cc6990bcfe8902b8d5458ad25a103c5f28219a1ddb424781084053d775c9f9737c9bc3c3e091e3c168e9d743f10453ae29aa4d85e84df02
+Qx = 16937b1b2eb6cd174516da3203c7a9de3e7817632416f84aa511cf2d600ffccb98fb22caae1c815d33dfa621af7f2bae27dd125
+Qy = 0c8b08ecce11fc16b6e23206d8a697702a80613ebb03e0a9d26f1cb9edb79923c1ccdcb80faaf9292cbef158fb7462474fb1ac3
+R = 0bdd2aa555af41a9a7e2ecac053a481db363bc1385b7ec96ee342b878f49ed4b5e9958ca371324a8985404b8e6bb82ef1980d02
+S = 0be1296d108fbdfbbd4dc2c4e5cc267d65d8316e1eba597341e773a6fecbe707215035f98f581ba592df2cc96da7b5c2cd73b37
+Result = F (4 - Q changed)
+
+Msg = 791c060363eda07eb1fe12582cb09338ca11415e041ddaf8f9ff7b6340da53e237623da4dfb8797440cb3fac8eab38df814f48aeabd70863565add309e35133930bcef88fe04b0db5cfcc3fbfd755a18a88eee2075fc2e7c8324b73696c46bae5f80be21d4bb2a1e4a17e916f1f05dc93853f4342a1c6c145acbeb8e4a6a4393
+Qx = 0dd9be522a18b03943ed9240750bfc997a87a795ed7160e6bbeb661e7a8f31997595b1b26465cb37135b62f96efc725041fde13
+Qy = 0a43231bf9a51bb63316bb58147a194eb489712013db8a70bcc66ea04f9720c5e138234c221c82853d98f4fd66a799e46a18877
+R = 031de4bdbb20d9cc0c65d16b90faf777003bce7a28470563382516a6dc42f5ec9040403a48557eea8263df1435e689809ebba3a
+S = 044c786cfd5db6505424b9723a73bef773a8cf91f2e3ac1d1b4bd722111698ac17a2b660d7aa7337b1c1d2ed4708cd708e3cad2
+Result = F (2 - R changed)
+
+Msg = fc06a4d4c22a25d936f3b5fecea43ed7beb14791b6800e9c644a85b27e17f01627e000f5c61cae81d1c4d06caa671b1e7960da01a6fe1abdbd50dc09f7628028453640e1e17e35dfecd28d588fdb42b5f22fe6077259e2ea242ee1eff3161219b20774c0fff1462e92853ef6794182072f8767a73b71cdbe63197c8f2013a3ba
+Qx = 15776ca485b0d035632424fbe35a3e6ea6be3a105cbbae74516dd45ebf9e09a662b977f3dd55f70b9e5728523426c954fb1db01
+Qy = 19394d6fcac721bbc47746fba248f6dbe99dbc5f17515cd22cbb07add0b875e3360336a41db7981479a83f289bde30de4a87ef9
+R = 0544ee05ec1b4da941f65859f53c0a623dfaa69b4ac4d9f3c3ce26fe0265ba7b16aadf602636497c3ddcf46914f5030f269fde7
+S = 0219376f5f5f88f8184270352c3f976ca9fc29ad2bd2eecabdaa7d34a7c04eb84b746d2c0ff2f608a86503e91fe0798cad0bdf1
+Result = F (1 - Message changed)
+
+Msg = 1b815dd41b50eeba8cc8eb9b726ce17425933777897b6630cbae2e143bdc555791d8e1665d83607c256e197f0992deab3830c04c8a66640bd67ddd1a81c705c7741bf5e0464c84e6efa78a9785023df3f63d5483e6d0e31f4a69ac87e5ed569052d57b31ac894b07247be2d346ec2041966242f9c5dd85e3786dd366bdbdd02b
+Qx = 149a32d46b2fcca40df5abbb582d079e07c7515f564ba6eec041941b72e5b24e7735a99a2ab3dc45e504997f61463e96b3f0cb7
+Qy = 112a19dcb1091e1daf033b60d0ac14f839ee68cb617f832778ab1e52c2ea59167a860550458505d7842a7730df84b1f92e371a9
+R = 0b348abfd6268d38d782c1c7c04bcb80ea1a8d37cac4769d962875830cc3cb714f887b5a001277514706e396b8c013d2177e278
+S = 0fdece10f6cfe9949d70171fcebf5df0ee585bb275812916fc6082cdec7cfeb8fe8032f4ed80cc94dcbec2a018e7720710ff9b7
+Result = F (1 - Message changed)
+
+Msg = 35ef47033a54c3c510951190afc173b24d0b4d3aa93ebe3dac82d9ce89573b0c765293b902087db72ce045a81002fbc0b41f318ee191e10c07ffc4681c7e098e0b8623bbbd4723ddc4727849682517c7027802968092454118cfc3cf8360696faadf431ce3d889587b3605af8525378e1e7ae4ceb2eb9d40305e2cacb972a9e3
+Qx = 03e324fbbf815ee1bf9296ebc02751c96f5d537b259d18d1c121ca807beb57a88a0c5e0a086aaa5f64f2ec063c5b67fff996553
+Qy = 1678d838a38c4769c97bf67114ab6b235ff5954aa57b9bf6c7f9a3a063ea2b3ff40ef932aff22b6a2cee0166be2e524c39ecf99
+R = 0f366821be6d1df277ff5e9cbc1a8491363cad8122b3451cfa391c366e0ddfee51909f392c16aeded9530f32bf02fd7007b5a02
+S = 0c0c408b74fc9b49ac4608838403ac216291768311f4130ac012c62ecf14f3e1e5432c09fbacc312c26243356df97a08b534845
+Result = F (2 - R changed)
+
+Msg = 8bb3c769634e699550add23e1d8850a6ea2c5a9b8fec4275d148524b8c19f0838925f67b4b76cb800a2661268e2ede5ddeca286f957b5e1a81631d78f7a2153ed904de28825f44d84aa71ffc5b6eb28988d4d1fd99ff56a24544f9f31bea77c100e380698b83f746be0188bd2960e4d35f3616dd486ddb6e80870926be29a54a
+Qx = 0bd20348adc5b626a8e212759a0e503c206de889cd92d9c7b33b38748550b5f190f35c28f7cc1ccd3398241d5ecf1090e728025
+Qy = 1d761e046b8c3f5b7a2880711da94aaaff3151c992373e6bac6ec6e5f3e874b02b02e587199d4d2eba6050ddb2157644dff3199
+R = 0314e1453db186f61458efce1ef14b538e32f458c8b7dae2ff25a6fe49fb35b13b26ff2499de9783f9adf20c9dd0fe268f2d6ae
+S = 07714e2aec75953dafaf3cec8b4fcfec6a5350729c4d1f4b812b6ee7c410d8537989364d1573af43cf07171bd12dbd06906d836
+Result = F (3 - S changed)
+
+Msg = 32ff61427868c3848d66635e44a7e6581f6eda146fe82c2460bd3ef771beb78ee9770946e5bba8d1162ef0d45f25efc444b1cb6999afb35b6fbf38d6ea1f6313e8cd33833cf457b34d88859102237ade789ea6b7f41193f42ef82ecd2ff82269c956d974613d35b3a6c5420227c2a19b67558f5d807e21a27725729d75b46f62
+Qx = 1fdc1b64473508de89e5948022c499f8f6d3a0f371f3b78919dd45def13a0f966e00bd9656313928edf71cda76a08a3682dfe53
+Qy = 03b934660bffb9e64e64f5678bf23c4a06baca85aca7fab1c3ce2f671781950b9e1df85bd6674e1a38b82c98f425a10efa06f04
+R = 01e4c89b2ca3a6c1e7f6c246d38d6b387db37fa91bec6741250ae39ec5d531424c8e7b75640b6c2598edf142dfa9f3691a1cf48
+S = 0a88f367f68949fa6571e6ac23587be60140e42232a0d333e3f6b68753a3cc74fbdf4f90d726a97acea5b2a26849b83b5aed757
+Result = P (0 )
+
+Msg = 97e0563d9f5340aa2e8f230ef7d98d15903abb869fecb89b64b3eec1cb300da881547e59e4ef360aed67bc96d3aff52aa2f5e1e1daa7bc88b9adbaa561bb2d53aeba3ad7904a379e1115d7ee9287006dfafe4d6a79a878c2582be12bcde24dd49e566d0dc5795deea022baa5b60e10749483312587e56e768d159b3b12103eb3
+Qx = 0cf4a0e5e3822f24105485dfbc23ca206870d695bc78556a49d9a18ad1dea1adc69d57252a0aad6fc77bcb49a5680f2b3b2bad3
+Qy = 04ca079d5387c63760e262c4f0f401f36362f8718f98bb6a1b9cc185500762e33497e273d57223463588c627373f4001c5a1623
+R = 0b5b13bfbda55732f81be488bc9c3aa3328dbe34fc1f1ae733367cfa7db439578acafc4f7af4e416b3210beda14dafaf9776788
+S = 03217f1fbee53bab7e637ca2181a97a2877a0f499d42bebffa743928cf1e1cbf14168d3189cc264b52980e6487160e91f50bf18
+Result = F (1 - Message changed)
+
+Msg = d956253939e9f3db446963e3848a477e1ec01bce0aa7ec9c6d31eda45be04e2cd615603bcb3ac0942aea2525a1abf74be762ef06715ed21dbc57a667d873ed9bd8dda381a073cc0f3776db5421492ce26f89554f63be78c26d73eba5ea8cc62dcb011deee92f2c50d4814d3c820b597c86b473a95158c80dff352cf76618010d
+Qx = 1d1a10e2a378861e1c45d91a347c74dd532d7b1c81372e9f285ba2337b1afd6e7076f4407a73e56bba07b7434c720a42c9acbfd
+Qy = 12c0e8ced4b59bf57802f8e3e61ce6aba91d07b3bc18f43781470c5cd1375bd844c42abcc4370b46d921139e4373b6c824e982a
+R = 0ae655264ba3b633daae1e94da41712af387969f2f0cab1d09be0addea950356b3d20d46a0dc46a037a5c0cf695ad1f07a313b3
+S = 011ba2a4afb714ab84fca4e04cf076afd7588c2a4ba853df635822e2d147aca5a38392e11d0f217a6a88bd55758bb6dbc456d92
+Result = P (0 )
+
+Msg = edb511d810d9aafdfb8bdd03821f2bbcc441243d77db33b5845fd9d2291cc82eac2b24bbe4b5463c499349d14c9dfa994bbfc278b2fa3c959b366ca59c0f414c58d9491722debade1f3aa31b81245c065c3af2fca49d94ef2877f730f37ac8968d1057d1db52ae456023ead22e66da4c2703e2dd947dfa00096248fc27cc11d2
+Qx = 0a7db1a8c72c56adeb2967a46aa81e97e85ccde8ea092280c9f653e4d8b8819117ba6cc5cc949abde4976ed19a853ffd1af4e17
+Qy = 05b5eb048e1acaba6524e9ae1a2fbff2641c013d9260c13bb1882c6fc336b54c18602812e0741958c9cf46d05e995f6c4152459
+R = 021a256bc0a6def21ede7d5891a94c530801b6bcf795dd38266019fa7af7d8a9fe0e8ec1d8c6bf12f7f32e3ba2f7dfa2befb99a
+S = 0c16d634e14187b70e08dc4079fa68d0d1659b1f08978ba8f519789fa5b79cd040e38031aa3d8024c29ee50cf66dbf3fe6a1ba4
+Result = F (4 - Q changed)
+
+[B-571,SHA-1]
+
+Msg = e7822cdd238ccf58ff343fbf61895fa50dcc6fe3170094368bbf7b1552a7c406ea54fed69a1b84ff582a78409f665da1560a79d9925d98dc16cda10083b6f707ab05bdad47aab84790f88550a02a56f07c2dc4d3884df8cfc4c019252c6122fb30f539268742b77e2b9d50575441834542727f2e983f7cdfb7327a0b0c3c7c73
+Qx = 2d7bb1f66eaec470fe4c68a867e2d315328182d22230154b2d77226bd820b4a23e9d7b9c2df04cde63ea4d64fa9ac63d1af17bf4cc5f529a7ead164304bbb46d36ef4142bafcf29
+Qy = 65039196f74ffbe3908377263cd0c6656080eb640013039b8f2b5c9ee7a5c3155518d1c5ce32c11e05a3b6b7b489997add843e81cbb9e8411e2fba372c160359cd9113709c6d235
+R = 21920d9ce54bbe8fd6f4c6edf79cbd6f6eaed206f63ae63ba4eeb801052fa82dc0d12ccb0d47e5abbb02580c50969e7efcccf70d7f2875f9e5d9cac0dcc44f41e7ee0542d6c1b66
+S = 10fac7c8bbcc4aeccf17e3365c53836d379f8d7bd21520f093c8bc79ae363803b9237b70430e644f8ee4f3f7f964fca5c3229a5f87f7d0942ce3cd8673d3f0c92360fd2fd84a0b2
+Result = F (3 - S changed)
+
+Msg = 025455c120c093d80e2becf10f3fbbb7284e996fcedb0e146cc4491f4bdb1256bbeabc0ce9fa4f031c1de0bf0515d5e84ce6eb40a2b7c60d21a9792c7c4a1ad1c1a0b6c2557001f2f1054ee2e171772441854a4edb4889b45e1ce4f95bec2a67c8dce4a4cf1243e0548649a9137827d162b670fd9719c8c956d5b45a4513a790
+Qx = 14e5a36bf938bd95d001cc52ad0cad4000a7b36430970978072a2eeacf5f48dd54da4b78e1e5cb59c38eb50a1ac38877add8a7185bc471f04d429d68d5f7e143aa5e5fec6d18780
+Qy = 452720342c4e1881e3e19cbc1a4ebb0d87d2f179ef25d08da5909f24da20103428c5ce964deece702811bd4e46d6fdfc0e4691c70eb16ddd1143a746462a4a94a5f9993a4494991
+R = 1033b5c5aec97d01cde7513cb16e105bd899cfcf0f6f5779219887340b1baa3e5acb7228460cae35249b47968c34fd45e775f9e2aec57d4f3ed8ca0641bb4c6c489fa9423cd3f9a
+S = 31f4460f12175155169c6d9d34cfa3966c5904dd15fb90ef70175de20a82b25cec27032267e94dc847e5630639067674dee6689caaf5eb622eb42cd666975b27688a33338c8ee70
+Result = F (4 - Q changed)
+
+Msg = 1f36d45de7f7d187e308e804d5111ffb9edfc46c9f2e3f17a9067f9e793fc889d43ed355c09945d82be9696c1a00c12d8c3d7e40f7f35ba0c214ac4baf23775191f0b1833e20f56d0fa458a9e0e0e50c9f3229f1ea999fa5e1453f78c6a47f1f7b678e8d4f0d42526eee61eb5dab778d7d49d9938b92a8b3b6a9a3651805b01e
+Qx = 3b72a8dd6a7d9094c04ee2f737cae267766aa9421df62365f5b5fbdfb50ce3bd51439ad83ca00d9e954eaa2209b98e0e79679db8e0f9290a609f33be9b4a7344834494a5f794729
+Qy = 141f52ccb96268a8c7baa65ddbabfcfdb4eb986a518bad223992506bf6865146db509be585773694c291558cdbae9bd482e95f9f010dadd0e9243f8d7fd5eea3c2b9da78bcb774f
+R = 1fb54228acf86f107d9855211a5f252cc6307bbf5a74e00291e7dc8b8a8cfd59da9794ac3f72599cabda81eba872fb0fe0eb0cd5b145d12b7eb6663ea6ba87111a7ee824d837f27
+S = 080497aa22fc272078a9b2ad5099ba40063d13790ffc4197829449457a4078e443831db0147f9861df49fc52de7794a4f937a793c619db69755838c464861fda206b6f60a2720f9
+Result = F (2 - R changed)
+
+Msg = aeb6c05628a113cdd7f65773e6e40f8479d6c6790e55871d5942ca19e1725f2504d4240b9d57593ce31cdb42a0f30246655fb654060c072240eee3f0fdf13a9181b4d45f861448ee5b1ff1b63a2c119ef2d7832b232b2835cc792d19c1138287e83a7925f7fda9f66ccfeb1b3ad25384513fa6d5038c713aaf13b0a4b1ca05c3
+Qx = 4b8b3e3171cccfee69f16e3be9e60c0622a1e43b80f6d891c84771972496b1816cae0c658c90433ad11e524ff3166a999da98c0dbcd768a8971bf0c4d818b48841c82387325474b
+Qy = 7902fc24e053ee5bfb23773a4a630f9b41126e445dd41424d2a38bac68dc8ae9003dabd7d4a98e2b79417e749114206bae46eef24cddf629e994be1475d7495e61e095981c64029
+R = 0888cc77f6fdd07442a1fe9d7a5dfefb0c46ec20129452631b3a70c8067769ca396d6cb6f1f8752dd38ebaf4e7b904c1441cb116f40035bd4a891855c6447b4943e61c14531e036
+S = 12380bbfee04830195c45135309867289d91d709cff1fe3f2407085d3dd82eb10b6ae0a8fe63a1311a32f59ddd79a1f90f8e8498b67edaccde1306e63a65f01941e879c1a8a6bc1
+Result = F (3 - S changed)
+
+Msg = 188fab6788a134eae93b62c3e3556d6047123b7b273907512af4d61777f408dc50585a9eeb41c310f4e8d7f26a3c562cf65250c42bfb4c4e5c28170ee79566924f9af46936c635fbc5128c1d3cb46b3f2ee2f6c967a081e345f561bc9c534c77901ad238cc60355e1e04691bf0a66dc71a51dea507af6775408a30dcd1c7fff6
+Qx = 796e57aa6bca619785b91240aa10ff57ae0c73f807f156546639e045e4b6f54a293b133d8f3955e1e380cf60cfa622f897b74e8a06baa03fa54857f8bc4a4f50b5f1fa74ac6b64b
+Qy = 78f9d3f66eb67579b6ad73fcb0f34402e462e05275fe584e709f1a2fb6f9c9f590adeb72dc9bcef306150d207c7344788312e73647491b3ec4d35334130c7fc42e01548e2eb654c
+R = 2691c347cc3efabb7216fb96375f1b3130bde054089b3891a52393307acb5e9f405bea8ecf3a4edae775511e72075c65fb04a47b9f6518c2541fa6902a513ac69184f8297c9a72a
+S = 0133375d15a1017a62b6912470c88bf74c4ebab65d4754bd1bf419e58e5f8610a92349c82d8a5811243081d4ae1762206096619f50327f608910d40f0868726eb3f9369bfd1d37c
+Result = P (0 )
+
+Msg = 18b88f5ba72273193c70aa0aa89a4e6487d5d8d729c62acf76778c77a96689f28ceb5014df1aa4bce77c7c715ac2325e1f0be0c2982f70c1107f9a7566bfd49b72e32326c6f2759d2116d64b36972cd4f94e271b568f4a5539640c00b8358962526a97a6f29ff8bc875ac0227c15120628f0324bc5468a4b9d57e2c1741dda40
+Qx = 4ce9312fa7ad4a36789fb66c8bc54bd599473d1c0eccfaeca2be7361f1c1b8afe77941a0b3eed19c91ae143175a28a3952fd99fcbca7333cdb7d143c32085af94504c8cd8919ba4
+Qy = 7e2627effaae2367f1415be9820243099cc2c69e2bf4241214a207574ed9fb10d6ca694d401e8a7f977e60eb68100c2f638f969b1926099c8134b093563f3d81f91a25145934d89
+R = 178c9ee452693294fc637a3fc7cc847249b48aed982d7d7496db9a7269a02850b6900e1df789ade36574b298912ad8922ea99dd96dd8e540416a8075784633e5ff617ef9fa26041
+S = 13ad81cc6498269304d9daae781439faee62bcae8e05961e88e1b122c37c5daa1fa25ea91e0d2eacf693c690dbad0625f29fdb9cfe10205640a080b932b91c9ce424d0cc860575c
+Result = F (4 - Q changed)
+
+Msg = 634f856e9420349ac81a2cfa327b7436a1333c71f9450177cea60dd4ca3f55f72a51e3cafd357a9c46e5f9937bb87a2f02135dea1321bb99917d22164a90f88aabe19525fc13310bb16192712a9e350be4fad1ad447b210d91b13ed4d08c4d0ba8564d43dca6e8ba0fc595c67a12dc4460334585e61b08816dd16919d1a137d1
+Qx = 1c760b596514c9fa342ce767ac725e823161924ed393bfb6ff19a6797725a4b54252906af0e823e726b3c51a0b4507d68888e730f865c1edbe960d84918919272b1e370c97e83c2
+Qy = 4b1a6589ee0f976b1a35987d19f62235986228f198d3e831b7a06fd5fb1545af4bba2c330d8387002a64aefd84c69db5d158b8b4419282df475ca8fcb9584da7eb4370ef459cdaf
+R = 395e43f880734b7486e2e1eac1a66b091333e3ac40388e5dab5c6b7e30ce2576214890c55fd69f2dcfaff3dd6521dd158467c32c5a5bdcc4052c5abaf9b1da9d7240931fcb8ece3
+S = 2d85018b3ac46c4fc87f7f78e47b574a46136b82ca2e69c91705b5467649e0e501fe189b5de61671a72828393d2e66f4b21b108030edddd0b62868c24906dcb1942859073a4a3f8
+Result = F (2 - R changed)
+
+Msg = 25767f36a6452b3fa66ecb1000b5de6a09aade6a4a30fa8252c4faa0a43274fcd3eab1a0d3e2f082d72e2b610d25a87fdaf38f8bef6ae7cc5a80144e35b6cf6b47f0aafadf9574e806bc412b9484b9a1cb2ff78f78bc1e08f6f46532fac2b62c380c10f1e65b0f73b0f80d0a9f200d3674699b368f52d5c4a1a57eb8b280fa53
+Qx = 6f47c77627a3b70cc5f875430a9d3a5a1e8517388b65bee673e18c7cbd65a467bde28ec5c25baa6b0d5fb58e466fe90516cc5c9e5ad59aa6ff66ef4853cb3000f89e7969a0f048a
+Qy = 092f7ee61f0706c2f0296602171b6f23ecaddf8e0c0910bedfbd558c5d63b5d36c0a23ba8773efe14a1c77b66931581f916ca13155fb501841ced30bee84080c390ce7f701199ff
+R = 3dde6221857d6d7d7ea3d12988f2ca7cc47d7f86faf8e97fd375458e6573ef4e9fa460e6ff742f8772ff7b66d8f40f537684998cd4c43d77907cce70e9a62657ffe2e9651aa2da9
+S = 141866b5310571e54f26791fdafff128d747dc7cd6008f963d14e4687ffa66a12e62745d7c8d3007870298b701e23390d34a7cfc33b9b7ee0ef2305b93eb577364081fc5f1f66b9
+Result = F (1 - Message changed)
+
+Msg = 26f23fb2be95ca177a6e3505cd3939335eec89387ce4f3178f0e814317f670865b63f5192a4cf81cc3f748e5d94e09aa9ab0802e6768230f0d0e0256bf3342f9697a869ae90044e0359db633713d8a6bb8806f3e244b804bccf884426e8b5d457d1195ad5f897ef40654d786ea23b200040839a95e4cc567f9580a0301d024b4
+Qx = 0df11559b96c8267afb10e7e0aefcf5a3596865f265af38b0c2b874f605cb9f71e7e03cd997d05e907cd67efe7fda2f1a9791436f913d20ebfc6cbc6b1a455f8b497a919b57a7da
+Qy = 1f35895a6dd337e0e8ac051f0d6d1a6c356e1241f0931593989e8c8de038419161c00f39bd7284ff8f704589c3b0dac8348db6e6f29eea7ff998077c4294187f332fc1282834be0
+R = 15af9b8901e8d63fd577e55061c5c339391e527956b5abf9668580647e6ffaf07bdb9a1d85c67575f41f6545e60e3b28d71671aabe8b40c55d3a08e970d5b0a5938373f2dad13de
+S = 291bfbfb0c552b2037efe0f16544d61501688574a1f1065a42d33917e058181f9e46e2f5e961723f22fca2e24b7c717ea2a5bce9d4f8ff7f73be1da3bc824d1c49e7d5899add1f1
+Result = P (0 )
+
+Msg = f222f4724f628ddf6351b377b626a7a632fc031b3fd3231a31b96f755f8a543f0740e05bf4a3aeed709e7e6be0ce14ead13b9e59268bdc073af2ef231966083422f6431178597eb9ffcfc6aba3f3ec8b1ef2b692d0c98652be3d9e3e8854541fbd167032f08302eed9579295eca89a7f07c86fc5f071d95c6d0dfe31448a827b
+Qx = 44ae9435c8844607e1faa008120d77392ab83cd3011629d34e4d7a7584f1744b4c7906b8939878635f273eb0a4ed014cde364fdef66b7395ff33a38b0e2eaf880915bee5513fd08
+Qy = 672149f76cb211da993592e69f271dfe269747e1135170f12929062185170ab76bd1f600d348b094047031f81b0a0ea4618b171c73a58dcb339c24fbda893e0cab2034180a21a6c
+R = 040185daa887814b0715d5c4796a7c35e494e0258fc006f8d4a93115e291489e8cc4a3df83377a578d8e731e46dafeb706373d14e0b456731d67bdef6e0c25aa56621c592a79985
+S = 3d9ca3887767125459bb18463b64e11a971d9bed160f1644f346c19484f350d2ec784bf49cebfc480a1ab3bd4edd97d144762c7a22dc5ab80101d7796c6fd91dfa35d0204b197eb
+Result = F (1 - Message changed)
+
+Msg = 781b1d369000561db71995496db6fd6d7b6dea1fa7f20496586698b86b5a946e0b592d28ed3fd6d1f537658dbc0c7a40ed4ffc2133b45590553d869ea5bf7b4f8636bf5919e0ccaf3fa9ff1a963247dd26f8002b85e692cb450aff9d44ceb75f2dd54c5b49eb9f2a00818e947b87628a9061d39de93545762086cccdcd891d18
+Qx = 1ec37bf3f724179244db9de4009bca27d3e765262f673202201abe5e1d4d4dbe71209c44b12afe30fdc452522ef544fa0e18ad6d6e9d4d807bfe3a44271d9b83a47ffb17dcb4397
+Qy = 37140c9caaa13a266dbb698b6f7e21e7a77015c68fa02aa3a701fa7f69e1e94b069f48c709d76d2c4bbff5bd8eac62279671d77c6a36cd7b3170e7421d695adf1f1956fa15ed96f
+R = 04014da4ef9de6bb5beb63c4cb5b884ab0998ada7bac1922cef96db571599c79a6b5aa6a7a2917d9a2d97af6c190465701127bf8d241eb44bb6fd894758888a84605950c6c0e210
+S = 06c5118f62e54041e608b2d39d63ed5ec259dbb122162f20302701d48ac950760586bbcf454f01b07b54e7385e8f638a3603a7aeec3029de2b313c2f7f8e744a82ed17c91b09cab
+Result = P (0 )
+
+Msg = 125480e5cd9710465f10ae5110fc62c44ff8db4caa407a03ae0d51205893f84f7ca94005b57534a7df0b5f44a5cd042ba8a65eb5be3c29a10062aeac91f15837d67e344e74a72c718030fde1f5cea68e0d04c46fd4c33a98f146ba92f3312a43fee26062513c664f53a01cfa0f5c21f46fd8a503da1e2e8298447e5b205e8930
+Qx = 31ab4282205fb7439d4560f9a7d48e1ef853ce6456e810e9b1285f0d267b8ebc0cdbc0fafa406b6d89313a2877dc23dff3fae48d550deb894b1d6bfdb7f268b7c90d4a8bfffed17
+Qy = 5537053e494be03bfb90f446817ea825e46559b252bf8a2da0043159fc25207561d9b2ca5391915a19b194fd85ae3986edab1e6d2bb21a8b7bda91f2fea2c8e89cfec255f1b084f
+R = 15bbc15ab779f82876b749444e13da34cede3f93ca0c8f4d273bb1ad31fcc46274b7a206d553826d95ac1dbf09dbf94f96f13d6f2b8105dc1eaf4a8e584ce6b707959e67d9b7a7b
+S = 272560b9e75a7c589bf02a00bf4efd987e7915d06f1ef579f2bafe00424459bac4dba3a2674c62c1225ba7171ea3458c119407788833dbe92ce96e0576476e50d64c9c40495e770
+Result = F (2 - R changed)
+
+Msg = 6ef0e2bee7d3dee85357744ae27709e2e88f002eb779949ab01dd185db57e39fa1899a2221fafca73ea7c2bdd3527475810de1b69af6736f1b4410277e4fe1c1b95d67c1429eb7aa5bb5a9214f0ae13595aa6cc60f6bbd767a7c8ef29748d8c7a3d325759d52270f8e692be15c4d2e3599d89c10784a86841f9c5ab20f0e41a2
+Qx = 0e53851541b4c1f124abcec77d60ae14dad1a86a0dc1b4e8dc53a7ba792cf72c403c4e1575844af0d69232ed065b572e7fc84d06213682f55f7ee80d209893a1dc39c76ef36efc9
+Qy = 17bf15bc668972ca91ee863265fde2c70e58ee81397d481a7b0f0c87707565351217d3092c57906e3a74b33be8e7b76356804a1bc153839a76160a18266088fd95cb5807c112a0d
+R = 03b39852b23986dc67b189bd18066f06588575bb6af2a3776d1597812a2715e14ba765c45bbe886a8c1f67fcad3943af9ec21746df2126959233bc7405a65e4d2dfb26c0f369a81
+S = 2c12880cf225eb56c550ce63c32609f94c988acee3985d937e4f4871891160fb2d968072461da2d4532b8370a1e7573b417641b03be502b1ef0187d1b7870956d1c8859b1d31efe
+Result = F (4 - Q changed)
+
+Msg = a68044446fb04a46775f87aec63f9aac030cb65a57c9497a0edb8a941594357285896c5c6b10a14afcb3bc8b40cd51bfc91fd0d210ffc25d1f430a7dd94efeff98d4a07a8f7293f899708790db95e4fea0e69fcaea08eae2ebc6c1abd541c372ae8a1d5ad6280fbe83d479b14989c99cef0f08067a71061cb1cedfc64af17bbb
+Qx = 51803c71a0b4578efb27abc7b969c22a594ce5e55207c8bcd00129c63e6963ad2b827f5e0fdbc0ddefdd91a5bcdf0f5e9c85a27da38911124c27c2665bdcb1fc42d7911614c7e7d
+Qy = 4d5ec5c995795475ad8478847cda8385c7f4bfd8d230e174cd25fa436034824a2790346e538bd7706c360b949199551a7820b28cf7b58e3aade15c290e173185eb73a0a84bff24f
+R = 0dbaa0689325e5455bd775815e28d1b7ca4f9d86261d9544380b3d0454e7513c5d1ac261def3cc5c4c49b38f8bda54060de322c359596aed5d3c24efe2840caf099ec8f955bee84
+S = 163a05d70e8dfdae82fc1da90eb6c0d2aea34e2f3926a724ec723172da77d09ae348b5bc1d45a14abf71b16a0bd602d96c8cd9f7226249c85350d2603d484ea3eabc467ce3034b3
+Result = F (1 - Message changed)
+
+Msg = 1a4711d85dfd2f02db6fb40216d31b91a5d0f2aeb26c0b4d74fd7715d10e1bdb4f1abf72b1c900708be072f23c0a3c33de4c807bac038ae548c83edc9308595544ee87cdf6b9e3bdf71350c5f16f0cb43d6e185fd11635f2b5631645a942fe6fa8f324f51d0d9a467eae52ee612bc895ed36d8307f780f5c1237936e6241f898
+Qx = 0cb2e78395bec956c1f938b9eb182ac68d75b34e2a1fd20e46d459c038859a382958eb937aa8c739010ffeed895174656cf1a45980a005eca9b254d97ce0a5d3923ebb8f9756e26
+Qy = 662b54acd62210b94dbb7a873bcf8c5651327ce9609655c2276bc42f7165c4147096f2e02f5f2753b7019f6aaf6ad3ae0aa22b5d5514b96548b2e2b235135a413e860fa270e913b
+R = 15e604eb8f4be78388da4c5c85b2b041f28197db1f2329f5c5519f384acdaa3f4a9991a52f206f365daecdcea508355844b8bfdeed83e3acc4a1f5dc317d93994614cd1e9e63697
+S = 0517936d60a9b546e9cdfc02a7bef51bbcecd462108ef4ae2d8068988c787596e390e7fc9393e8546e65a58eae5d8e23a076ad71ba4df5f2518e32bc93788a3f96ce76728ea690f
+Result = F (3 - S changed)
+
+[B-571,SHA-224]
+
+Msg = 5dbce8583895e376426b4cb552bf2ecfc3040d543c2f1a60063be4afcc2690c49b7546c4903d1f6938245af6688117ae004dd63b30acb177dad96a5a51b1fc34fae3839f93afb1f95b546133788151d2a78792b18606e21ffad2b55dab805b6a367891a6fe1816c74fe9dd6cc84df7d78378739514ec456df472bf6745c09043
+Qx = 2bf67a590c6501776fea359c41f14d8821279f84bd3c41a518fecd433dd4ec31d98f91f59c49d0e3f4840fd45272e8fe9610c317f26e10b3d39937bccaf23c5ec5d83e5361b26b3
+Qy = 1b538cd862be62c1dc72614a946b810ff101cd26c02e6fd6738a57f6633a2ba861700d3a2b837aa08d13295989bfa69bae51179186bba4e9443b1436f6ad49f27c262fa026f02e8
+R = 05ba1223b75887e36369c6d7e37390afefb3721bbc6e2c4d7998ee5bca2c3661947a9742cba2aa8a8b0820f0a2867a5344a814dea5d0b781138ce687e4ca9481e090f8e490c555c
+S = 0fa850d7057b4c8dffa6c0089eb81aa072c0a09176e4f0a8c83ee1a66af820125b71f72ed4028bade65e8e90d9963012000f7c1fac911c80ed71aa91f323f4b529c0152d704fa2c
+Result = F (2 - R changed)
+
+Msg = 05de98a5bb3d99162d7825beabc130c350da76cfa243d43cb5d4688a4ff064c9709f47beb57fca261314de50914f97d61e8474a95f291232e6cf170edf6e63fdbc0b81d77745bc3e3a5a135f503314aae7e88c619d8b1d36a13fe0fd97229c3c12e0309c29855557317f65a1b5a23fb87df44bf60623e1d3a0ea89789beb8de3
+Qx = 1e17037b2202424cd15e0d7ff26498b5d80085bf27f5a8cbbc2f71e4b6c558caa697a248192bae182dbdda8cc79bc22e1b52e043e66b5ba06d98db17f8c372a09aa1cf75e8c3367
+Qy = 6f100338d90aa83e8c644ccdaf04b34418f99cd4a3f2c8a853938d755efc020bf6c0ce92127e766578b802518fab556d62ed1520ae434e9619ec83927c570d79e144be2897f1156
+R = 0ff67db9a902859b8aed900df1c36c37ed3038b1c00a2ba7baf83755e21b0a361bf42fef2cbd8c102cd208f3dbc3d0386960031cb95908cf3224ee84f0700cdf5d3d76ab21ef640
+S = 2c675bd9d2ee8132cb42b20efd4a20423f6baf01778c0718ad1a60191c1cdf0d600d98ecd5f4aa0d4cf9e8d840270fcb9d5feb34c46a84cba759ff62c1b0234b878466428ae455b
+Result = F (2 - R changed)
+
+Msg = 04c0be3d6ec57b45b84f67affa4a3e944f4e0ffce61e07b038053a171459fc986093effa0e95855a3ad656d91ea23a0208e4fc42121d91bb2805f3cd1edbbfd215c0619b3bb21e1b1b374cad2fb3443d19ab2f92353484313ea7627ba45a1887b3992a58484013feafe6afe7fb69fa39cafb4733503903c800aa07e5f74bea9b
+Qx = 1c67f95236a2e5cbc2295877b3260a4e54529a9fd29e7a5aef1fc6b6ad1e34598710317c1d3bf9a7ab4511bf7ab19a5e58989e00b9cf4f59848c452823577e3492ff4b88eb014f4
+Qy = 08090427f3a462edc627001e280e7812c424546799c1415a9f8f09d3a169f5fe4d61154af533c5d106b63d83f215c53bc029643425e590060e97651f230b39ad31f06153603e4b6
+R = 39904e43bc08f19173bd7975ec44c72200762fe6da72eeefbb463814b072daf3f8192a3fbae641afe929082e6c8754eb0a57e3d45427b5870b5342cd66ccb542afbbff33ca0e417
+S = 09a4e60bb17a409172845207e3c8e15c430f240bf0599d82bffd7ca54ae0007de187bc86cd8d0b09c865e9e848a883c15713b0e9f94ef474fadf145227a38c7a2d8b452ac8d2ef3
+Result = F (1 - Message changed)
+
+Msg = 7b7241a48eb15c29a352db321c020280c51eb4534d1e107b7b529d09a9213d6a6d0657ade6dff70746ec9dfe1ebdc0efe45f1ac5516bf865f2fbd3a01852e63c5d7e4d6207951d11b0a4ed480b7edd40f602ad6df2b98521ce526b9c3006b24ec78b7f74bdea70943f360668f97553c75c28a0662891d2208259b49a7b6ceb6d
+Qx = 1cde73e1c96bfc39a857162c4e54186a870591b7189fcfa66f7e1b9830791ce25594fc9ff5fdf4d3c6adb6bd7b09622fbe4921d54e4b358263f45c9f0165d0b1f5a98eb13fc575b
+Qy = 5256c6652917810613cd54ec39710a6197323165f2c8373371ef581249245b9ea5479a202cdd7070f32147fb85755cb284a1c85a52add765f0a9e54bbd41d35702f4b785f7edaef
+R = 1f72174824f585080c2c954b67c6d6ed5c715e9139a0267ff8d1c9e5ea6d6a8ea021456dfeaefc35cc4d48d83c60d0f61baabbf4ccbfba2aa40ca8a40d64b7adb266628cd39123f
+S = 13e0aca1b3105f3819c6eec970e186f1f27af64acfbd3fc2ef3b2428b4fab842454e9a85dca650fddc654d1aa76c612a255754248f93d49525c6f4f566736257bb06c63dae11adf
+Result = F (4 - Q changed)
+
+Msg = 4b0b800e104c66699101b128b7a6ca49b2cc0506ca674f7aa2c5aa7a757e17736dd8fb604922ec0dae816304ef8d71a0bd33fc29f6cc52bf8ecf533b0a40d5bdfb5a40a7af33b23c3e4537807e5f90ce89efde1874a080c35e001bdc081c7e6126039e0200f805596d29d2642fa973c02384f69ea60792a519929aa23ee561a9
+Qx = 73152c86fa55e93184371300b9fb1afcf3b5a1aed2027a250fcc5f161e235e4322f759f5ff38afd2bf52c3b59af1660fac9d81bd910e2bed5f8abf594b4861dacef34e38aa142b2
+Qy = 22466d4d583859ace2689df92cbc410ce1ae0e30262d6649a874a1c05c60a4e2cffd4867af6692b31e7efdef6228700dd8ba94dffde2e5e9f6692a9a378317f8e30dfae7dfcab3c
+R = 282d939f2bcd6881a3ba5e89d703073b05937b8c69205fa92991234e71d60c55673065a19d8680669b3f6a0ede7bde6a165a8e479d4064f0c7c231f9468c61be7eaac31c91a91e7
+S = 0e009ed4d81908abc39d6fe4f7bc5a8ae59d6267bdf3ef66b9b26555e342462f32ca809904841b4f0a88e3be355e3671debd43385ced034f0c8435a7a68fb5053d4ebd988ca7fc5
+Result = F (1 - Message changed)
+
+Msg = 7e9dbd2d6e82351bcf6923e3567b81f3a22d35537abe4b0231a5cd512c0131a61ede2c8b784ced443de7560bfe6914cb610b2547a001c9ac036e66088d7a141d8d4ba33305fb78a109956a70fde098ce8c3dae91b7c5be713b6d440ad98cb6e0d213421a585bd6336d88c499ed30deda44f03e5cb3a05f73a7dac4537a2b94ec
+Qx = 0b49bd7b939931ea9796eb3e768b5011f25fca1a6b6f8bc3708f2c70f620265e5b8f0b205ab4bd3421e68fcad951ba704bca36c201f25286ab97d17f6eed6e543c04870373967d5
+Qy = 690c9324024c2a88b2a315e4714716bebd5cf454816664663adb0d350ccf5d71533f5bbbbbb533575bd0533a0f945f2144e73d22ee9a0edd25b32ec0852402733500cc55aa8920e
+R = 117ef5046a7a0936e2f1fd3dd4c464b8378f0b30ce4fe96e75f4430cf7c15236986abe419eeb23116dd0288303f9fe7adc554d8b734aaf9d6082db3a397f5566ae881f28021f3d6
+S = 157007d99eead376ef4cef001813548481ae185eb575d933404f8af961c788dc6ec61121357e19957dc4006b523efc1db59b241b8df75b47ea5cd6232c245184c318d0004c5d376
+Result = F (4 - Q changed)
+
+Msg = 335e59e1269f80a4fbfcae5454c66da8b8a88106d06dbc8e9bd77b576adc9cff2f33aa6fa8768d08e140a79b56e2516d6c49626d0552429fe028cc371b21d18687c07e94f39efb044ec61a7c512557afadfd29b0f92e3b766d3fbc7045903bc2d69b28f5f1761b59e1eaf1dfd086431343574c43040766b77beeadaafb60a395
+Qx = 6df6c514e81a2b812169db7bee394dd25d89d70871ba40d308da48e583a5a62392bdb09486a4a82ec73552564766303ad4ff65aca128469234cb70424722f42321b2eb3cecd0501
+Qy = 7a821f82f8cd39c1d5e25e4564cad6f84bb5d2714aa14e0bdb3c37dc9e00ff9ea0273097d8bd3e687fde2bf77d4d80c5a22ae92f97d675458a84538398bad6475f1d1b15c6fbdb9
+R = 2ec913369393007e5efda02b5d42efc510075ecbf8058c2f45ce295cbc2b72fc4d8b5daeaff3313d34f27ff3e40979c87d63619f5743ff1ce21a43428820a8238ed3c96acafffbf
+S = 274e198fd241fe299fb72971451ec941e59a6d1308323cd993a651440c1cd44f0c475d7bc5b488f5ba74b4944b4be0f1717b6ab509ef55e3feacf19347139f5b775f98886849330
+Result = F (2 - R changed)
+
+Msg = 00660c40471a20a17b5648774f5353f1dcca6e13e924e1fdb74a1ca9caf99a66f2f0c48248be4411fe6a166c23c719409202c0a08dc5c071f33850aca42f8d246358129137516b8685d799555623e6cd08858b2dbd1b7d5729ef728fbea8f94811d0777d9fa0c95183b49ff7d1553e122d5ca0ee60d003c1bb6b7e04f800813e
+Qx = 0124cae29e608fbd8fd4e64ac9a5c08ead16d317cc7317021d0c5cea6fdc653bedd5f6acd73520e1fb85c2987c247110e4e0ae9498b9082355e9e01e1ec03802f79762c168f6034
+Qy = 4eb5174f8b9de11542903df647d37705995ca858f736abf2fdc50460d57e2216c9ef0db429c23366f7ad4da32a5cb4d2f683c7a409c73554f7e86fd67c6a28d1f0e589e40f26c91
+R = 2a10def3d5b378dd153c04173a7d901674c8e16714d0b481d34bc22fdf9f8f5eaaba06ec58bb09c0a751ac0e1bcc7f222742b0bb7e758bbe4fabfa3a97aa96d82ce504a35fccbea
+S = 07bbdd436be4a60eea1674c7e4096742e35116ffcd906bbf1b6e4d608d2f1c20cf68948955366c8a1d73ff5733440dc11046d38c744d496cea93d89dafd8162689766aaa352ab03
+Result = F (4 - Q changed)
+
+Msg = 73392d5479234b31df45b30ed6413fae33bcca1ae583f6c336550a45bff77da242c34fd888ff99804b629c8498e0037a46831dcda24f4885bedd63523ab19dc2796076b4cd17384a189ba796e00f67d5e0fd38625e28e75afe628a86df3bbb532a492c4dcac1b9c18d70249116462d05902521cb64f7b2c80da60652ca6215f1
+Qx = 2c2743db8f77de364fc6d7ced83da0e0082f632f8bd4907ab8c7af421d3ea99a560866dd949ea3c656f47428c4a2b7e1ca580d1aa636e29b7699b9bd38e6a78e885f57da66af80b
+Qy = 1a391879351e2adc6a2325f8ac5b9f52fffc15d7a52a41f1ea4b9edb4acdcae78503f7241216cdb8d31fc2fdd8e931693859a342b4512c4ea2824a9886bb0fb190a6ce73d06ac7a
+R = 1f50f96d55413778f3a209d33e3315fdb8dcd29944b9c9166dc14eaa0ac92457a210f826b78334941de673bb4d8349cddfa42589445dccd8717e192598adcc4f3cc26ba9f4f9c32
+S = 0ecbf74a25c4d5b891f10031d5ce27afc0348556bc4ebd0ec5cbd40b75ad51b6d6cce879a5ef3cfeb74ac6eb6429cffa2def715a7d4da5f6b6a69ccb01a47ebb247f882a9841764
+Result = P (0 )
+
+Msg = 846bd204c05ab107951eab15801f06a72ba6345474aee8fab20b5c21d178469e731a3c043a15edcf3990c59fdb44ac049440ee120dae28e26275c0699c7b901e04c3ce869b33349a337cafb85ce83cd415ca3ffd0ea5eb6b6dbeb1581ec0ee1cb8b826ac67f8e699b60dc8e3bcb6e967efaa1230fed72e59af4e94e2b8290aef
+Qx = 1c6ad5effd1375c9b458e3a712945a34030b45cd669ea044d4332d517bdb8351c8df3775ab988430ee9a48d84e99765bcfea3fd65ed966bb2989e174c77cb30637a0b00a3ddb634
+Qy = 0cf7fa8baffa6f3f0eaed6cb2adafa7ea826cf3fb1e0d469473197437fe9192ae6163c205d440f51479c1364b26303a790af783b70e39be93bf47374d39eff395eb5eeb10b9632e
+R = 0cc9778e556c97803dfd17d271a012247d6d190f6e6eefd349f1138239adb5bd53a4cae5fceb8e3dc13adfd6b7e0dfe735f031558166fe74b7e02c80c6ffc09dee1475550cab39f
+S = 0d1db9f117e49a324a202db07dbf91424c19ef5755fe61419fc72528988a56f1ce3415bb5a246f308312c1883f7094f366759e500e613368f49f3516cf110e9361f2b5a8ff47532
+Result = F (3 - S changed)
+
+Msg = 3d7220873a9457653e143def23df3cbf12c1bebd0cb9da6ffb4f7938ef9a78fb83a1757a4d42d621f8230b427453fec21e71830deaf8e80492a478a2690c2b8eaa5730e2b5898ed675e72440c0c67b6e28bc066c9fadc7111a045247ba3bcdfebc5527eab7e4b4909bbb5fa0272c4c5d21655217d9324e2942cc081c0bd03aec
+Qx = 3f2fda60951f267611d17cfee3769b32cee066e77f256fe1745d45e11acb283063ef85b2787cc31ca1c6e34ba414df78bc57f107eaf183c5233afbc67870981451821fff181c1fb
+Qy = 4bd566edff441b295bab62614b2a1fcd7f0bc7514d682d8f3f6b2493ac5de3c6af3d087af57fb6bff59b77d279ba131dd52718da131daca479947d24bbde250037a4e1dee3a93dd
+R = 1b7fe79616f2a69b2cf1a4841569c257d8bde44815d29576b022fbc8293ab99ebd1bd3b9e3baa7bdaf168c5f4b06ef206216e3150aca3d12b6c029bf4d5c449055204bfd9b83a40
+S = 270783eeef933569b884838c0e9d081b82295585dfcb9ed0bef507aa0cf34addccb14bbe1152d561ab3ebf807c06e9b2838db45db25d1f0af54d24b8a0b7a334f0fecfa58dfc6ec
+Result = P (0 )
+
+Msg = 0f2f1b0056d5d5359d8be12acc1dd9897df21f9906eb03fc28ef96ab6574a7cd9a177ac117376f825581b2dc94e4de08c2bb185111a03d848ff3a21ad5e43337f8059d44a508db58d478cfcd2c98248381dd9cd1f9fb7b45bf93a3f6afc2c1957419911bb810dfc2fc2576e85caa9849ce6c4d49703e97a8a4b7ee4fe5b26a11
+Qx = 3f26ceaff107fa0e522ca78981372ea7bc57db8e4e7d9ed6f6f590a262b3bd4bacd57a52cde8bfe6a3ffde022a5996902cbee9b708e1c9156adc04693f73060e65de55cc4aea705
+Qy = 7122f81437f185b6768006087ca1fbc9ee4f588e4e2c729eb38954e347895a76d9d99a995ba271688d538adec1aa00ad297e23433b5bb7ccdad5aaa652b4badf1880fc2c19ed542
+R = 27da582d9432b44ecec02dec266d3d3eae2f3836fa66b093b3b1ef18072c851a24a3788d554ff8fc5a04fe712f86a3500adcb339a3cddc7ebb75ac808e97eeaa0af3e4facaf3b8c
+S = 372c6363aebc311e9ae98c43a56e4a750190813020a606826a6bf86b08f4eb47c8760b14581c3788435291e2bb3e325fe961f1dab012dc475edcf31cbc34f8225b52a52ad1acde5
+Result = F (3 - S changed)
+
+Msg = 2d1f76089b83a5bcf356ab4eb301e24ce212b81b8624881731717daf63c115bae14f0422dafc5bd6760088b5230e36f4c60000e07202e620426cb62e5865e9603563a84f47129826681510f678ada2e473ef71d081f88b02f449d57b8b4b629ff7b45cca19b986baa4596bb60af82d09e26f1d519b7f0d9eef0ad1f34986fb49
+Qx = 43f2677c3b3dd035233097f2bb64200730e1aeed81469f4037790d3ecaa67345ce43eae1245304eec793e13ce1847af2c5a0d3f423663a23d0e248bc1933be2d7a622dc73366566
+Qy = 6ddaf10c4f9fb5a45d5edc5fc82404af8fd4c9a6d6fb91c8b194e089573b94cab94e49b259301bc85ab3e7b7e77c3dc49e0c1057410545f391d1e8f3eca1b4f724c4e053d15c958
+R = 321cbddde213e77d9b864a5368772cd80e1ef11c5a8e774007d5096d5ac2e043072ea93dc9d247fdd1716ed6e4c2a2e90150b2021119eb5cbfb0ab3b14198f309e888689c853fa5
+S = 3ccbeaab20dc91bce38175c8dd859a5a04f7172ee2a25af76031506ae9791b30e23b9c52059e9fc5a022ac3841ce32beaf0178e9bc1a45364ba56df6cbe352d8fbadc381ec8eaf2
+Result = P (0 )
+
+Msg = 3762b3117047303ab1d3e298bdf57ead1ed5d5cb631867c7953bbc3bc8805f27e7179cb8088ed6e1c71959ecbae30e6c1882b0561c6995039f6da7c6a93036471bbfa8208179916b9e37e47443673231455dcd4779ba5b458dde58114ee37b0050da851ca79d23465bdeb49a0ae5b27d63a1b3f97a7d76783dfd04ffe42f4e76
+Qx = 49e469f6a32587ee53a8853fff1c3bd3f98b77519408f8f8568eef9277b81f5224f0cc028444d30abbc4b0407209e75f9b1e5d7885a48168a7b760bc699cb99c5b1a5bbb485da24
+Qy = 47faa0aaf3d0f160f1aa1e523aa59304e492dd15ce7027ae3f6d72f8a91a669dc772f2d1d0cd8fc34e8e9701cf801d3de0fefabb217b5dc915b8cc82a89909561faf1bf3606b78b
+R = 1840ef3c4bfc721f004a295ea053d4a41f8a1fc8e04a99fe83cacf799ec2c84f4b4ea7b916f4fb19ee58852b3444d001557875be5b9a808cd9f02b65455a4e769553246a914bc56
+S = 2486c4a783c730bfafbbc16e4a5951d4cb6af1b78b3992139daf049103ad53d6376e4c880ef86fb9d854afa9c9cad9cd25081b087d84f6e0f752b89d7fa174f95ec64b584f78e37
+Result = F (1 - Message changed)
+
+Msg = d32cb4303cfa1921cbd07aa5f63968e8e0cd4e370d350887b954b628915fb9163fa1d51d7cb3d8a1d8c69be616c9695167ea9ff4761c5c29565747f47b46b86aabd6ee1b23ce750c0f056a728a4e67ed80faadcad910eefd337675a65e1731324e6fc259c72214ad6970409fa0d16c97c304037f9204fb9563223376e257b728
+Qx = 4f8a33df2754034de7b3dd6d82098296e796c47af6d56c21edd5e55fb404902b12ba6154193be1d637fb7da2aad50e93878669ca5cb80962bc1247aa074e6831704358798f426ff
+Qy = 456d845de5765964f9e94e4633ef961a345050d03b47c65aa6bab0272f9a59e55ba271f7eabffbb07b74690b0204b8ddff34878d7ee21b66e7bbb438e6722d0cd293db83afbc4f4
+R = 2d1b8426f71b9405e466b1bd1e93eb36c0b1f2bc3422566224c5799ac843cd0b6401e6c75a0075cbce36b63333efb2517e595c9648a74cd75c25f41d4d88628caeb2f77ad208e63
+S = 1c9063a462088fe41f0ea295bc345ca708f1c733abe0fd37db5699d4c12e1eb1b996636ee090d24bd948228a161e083236951aaeb89812ced300e3a9a1a0f8f2a502c272c221643
+Result = F (3 - S changed)
+
+[B-571,SHA-256]
+
+Msg = bf07dcb385ae20da3f1a8a0adf74869c24d82914d2e4fe74e7fcd7f4cbb472b423ed666a92198854cd4ebef1d9196109d5d2fc1192ed944aabc3ccb9047c825a6883715af5c1b743e35914d7602bebd14d660ffd8b831d19920a5ca52aeab5dbda4c91de111751c98e8a9d56d2183788d9339c560a433b97ac74d69542bf0126
+Qx = 5bb2e10f9cd9af96e9b5bd88d566a113545e36f889753057c512c5153278f510531edc7d55b6965e453c5060d9163144c293fd7e227d8a66c955213d0502fdc94ad704bd26289a0
+Qy = 41bceab518fcb510e9793ab6299fe7983080de839a008e14cd6469863cd553791abff495abf1fe13c030a1e01c5d6e3415030335f3a1529f63d82358a00c48592475cffa15aa69a
+R = 1b99d25a65dfc89e213caae622fb295d39e8a24c6a16c1dbe8676e3330a2bad24b85513602878d583723ed3c75abc9050312c3ea17b4bb066994f1242326a49a0c0d19c2d0087c8
+S = 1093f0ace74d0a5b90d2ab1810306f0745c460a655cf8794a4b50d8e1bc9a4aae8a48e234b95b24af81eaddd5cccccf65dff2313bf99e2ee8917eb754902d00f78de84f68ad5f21
+Result = F (1 - Message changed)
+
+Msg = 302c512ed65659d1232ad7e261a12420127a38a363bd99b44b3d536e7b6cd203b5e958eff82a6bd6c316c5fa8708a849a6d1af537c744b13ee916d8659d722b8a3d63d7aaffb40e4523c20855810352292739b2bf98282920ea85c820abe2fcaccbc6af79e22ee6ead8aad2660017cddbe66b512c602976ce6deb62c87291428
+Qx = 75f97be8421f9a07cb1d2f97e43b968d848c4a7544bb0ff92a27848d8be7892678a30c3655d454b7900b0ab636bdee87e1ba639d6ff7b84da5d457174ba2aecfd8d8a9d5ce27bbf
+Qy = 27305372b7a8da8559eff0ab02ba8411d64771805428408faed5782f11d85fc5a09a6dafcc37469661d44aab5fd108b64d41173a2672219bb98383005d9446071f7e3fcdd554b11
+R = 1826fd21024ba03f2b11d4403c4728235275a4294639b0c7315ea244a337f8941987ef3d132835bed67348f495f0acf319015dedcbc7500e6cb5076663c6383e995f00987c69e55
+S = 1fa7c1d7c0f3585e906580fabc2fd5ca6feca5f542b87d6b1726648e0895374814789686da78bb9081a12c8c6ec5eba8f565f0af52a4cb31df63c9f46f323ffcbbabf913735d314
+Result = F (4 - Q changed)
+
+Msg = 1d574de360a603b7f47f47bc7938ba2c3eb7707d01cc81e2b60a18634c8fe2a7cfeedc527b188e443e678aa1b8a0968411ac014db4cb6401bfabe99a0b0a5d5a6ba352d0ee5f3bb72b8be9ca47adc0723abdde47de0f6c837cf5738a7041ce53ce14f435975ff512815bc0eb299c9129164a58b5a04c80cf62ef008658caa7b5
+Qx = 59d2861601b3774375d10bd2ce9b88800038bb2b88dc0c04ec36301314187c7ecfd9bc9e1c9d4fc61e2ca13bb4faa973941b5b29a2d286d4b48bdc15487f66fa8f9c7d3d3e0f4d3
+Qy = 51e84f6ab89adda71f0240e24d4c3fced67a26fa2adc50f8628a2ab86cdfe2e442b12016ab731a632e2cf2588c0952d99f61f11ff28449c806e260ddd1cf960b92421e13cbcd8c2
+R = 058ac43efa7d70152e68735833db235ef7108e8bbb703610a53a54f27a1703396f44df6b0e12fb6a99d92dfe29be62bde72b150bf6ffddb379bd581b9a21a07801629042e213637
+S = 142cf20025cfb10e3a4b8b77c1ec8469778f8d91416d659f2bc63ad53885a0775b78b71f00436f40a28c03c37fa5d97b4288ac08de7430bc2fddec2abd74bcd3fac3c88eb8e9114
+Result = P (0 )
+
+Msg = 619a570eb2f07d928821a6b6df49278b923d2cbf3edfbb06aa3c64bd3c2e8103c10650641d7f065b8ff45181e8a898f65c304be3ff0ec93c30725a1567800e5b1b10a55864c9b20061fe31592e5381887f5023469eaeb6c8b2ebaf516fd4b692ce7ccfb1d90cd0624559676a53be266528facbb9c6533daf8055f108cf88ac26
+Qx = 08e4d35e2f574bd907f7b84c0943bdbe671341421489966bf110f966184ce917a7a56cb0512a77446bce2898e7d6f79fd19d97dde7f9c0e3908eb5b5afa60e68dd4716f2e9f1652
+Qy = 4f86e765f1dd149a989d37751dd64ae1617c59eabe6c2b3e87d424bb8359f914254c63bf06bfcaf8a712ef1fe72fdfd2badf079daf2b17edb752d26f1dbd44b9018124a55dfc7cd
+R = 3c4c59e8d2c22e0aba396a19418b57a67c35a069064f48b88d4d87e61e52369aec680137235fbace6699033d98cca192e9be7c1b2e4153ecb50ed8c02814c7bc779eff8a2793c20
+S = 19a9444c1a80cccc78d85b6c0c174f88ded43a7ffbce9f32185a8f2d3b7dc783cc72e08edf04095c105ffe396b3b162a44e031158b53a067caca00976d689e256b4090653a801e8
+Result = F (4 - Q changed)
+
+Msg = ddf075d4c26e5f7b0134efff74eba5a68af0321d4e435273949bcf5c8b4b75cb0a70ceb755aab3290c21b98eb7a2b94c6bb0fca5a479e9738502a3ae4a0cd790cd70ca16beacfb26f62c4779b8c57c5db41a0f0157a870914feb00237f6b30d96bf5f0d15607835dd47b30acdca54aad5a851da67c41d5efdd87506666f83be4
+Qx = 1d7abed352456ddef59c9b431dce332b60f52523082510c76ed13967bbb5e58f969217800bd218355f15feb699b7dba57ef36e967d355cf0940e94a5209b2921b48b1c7941897e4
+Qy = 3f114f0d19e03d97df177205e022034c733b09072eeda272a577d6edbf2a049f7d1cd041dbc891d28bfa99eacb026634d5866787ff7092a0149eaa1a3e41113cbb425ad364d24de
+R = 10f4883368ba79be39d4ee91bda61f4db7625271516ad570b4eb4a753264645b6726e480cb8c5d60de803ee942acae56181c947167b62558f83be24526185f64d26f2d13bde6b7e
+S = 129dfe3ae1d447f46b50bcced2bf91f936df7f35abc5438c1a0de7efb97ea81ba0ef5590b578338c82221a4ff2a73fac5e6a0a0e90b6ee6e0c43de787d66509441be8eeec1cfa9b
+Result = P (0 )
+
+Msg = 924df92fce4407ab2434cf263ed0a2a4284d0439eca784384d0b7238a544bd6f2af9befaaa23dc26a128361ba346fd944ddf90efb7af1d2d8b20e096e1bbeee683862f2c3f116e17070c94082413cfc583e0da75f5fabf23730ca4b74c5420a113ee500acdeaf2717362918fd2df601d0d8fa0dd4d9fa7f94c4878ccd5c388b3
+Qx = 21d6c9f1d70d8063045c90bca07f751d8de6713181661312ddeba02068ce9e4228c5ae7fdd32422c4c6f66b455b949bd6aef8e02822c3eafb32c0498d15d0c6e25c86f6345177aa
+Qy = 23f8b84aa275d1d7f3d764da09d6d08139d2e16c71c7da257ac6118d6409296dd251ed49dd6cdcf2b9dabcf46d99f9b02dbc7ea3d87bd92954ab3d09882c736c6c7012746be830b
+R = 3da75247665c96a7eec3fc60328864cc4dd6c7c378320bd4da11d3974325b08bb601eee449386d4df3e4b90d4c5904227d381b445b35894b54202400b6e05764a90c415d78fe748
+S = 132c4cf4b3f8be9fbdc6deeef0dad5bbe168ce88ca17ebe0ea711d0f8fadc7c35334c8a9cdd91f80eec7bdfa720884796f20b6bedabbe46283f2c37f370bb10882891ad5ed65a03
+Result = F (1 - Message changed)
+
+Msg = a716c4c4c0b61387d02a88924d28bdfe0c3ef962747ae062ab861f00098a9668dbc9d6fec2ef16286ee5023cf2ea080427599a93349a1c3e736868145177790e44817730696b445e3fe1b149651aa7fd87328ccf5399038878607c69fb2d664b96a40061043b464e2f8b573e12f67392e5177e4001211a11f565930370023629
+Qx = 2b533ae737b3a8718f1764cb091ec23aac438c0c79ec7445b67cf1154f3e05d5062f978e72b0029d16df63432072f0440a3cb3c2d92c4ce4441382ccd04005ea7a2b8607dc6bf58
+Qy = 2aef71dd46a6ffad75b435c406dd8470c6c88b5184efdb9e76e19469a73651ac596b34afcf0ca51f4d2d564055b247326ee7fb0ce2292f0608fa91be3de6f6391726a5670643b4a
+R = 3dbc775cdeea6428afe0f1476c9100021784a21cd4df1360a9768d2e1ad548dd1f34337ac3e68a85a32131f66946cd58a4b5cd6aa59ce6f159053b3ca3c54c42b694f777ea101a6
+S = 3d85b3064f7fe05b59adfbdeba1a66b3ad3a81b623d451622b114b22af3e5f443a86b287be0738cc881e88b7913afaa261c7617e238354463909afb9697dea978bb49c275fceaa2
+Result = F (4 - Q changed)
+
+Msg = de896ca0aa03bd540259ef75e7551a8e6080890153d63d19ae14ec67af43b17923836839115fed04a4a3c6f4336c5561ae31f1fc691eeec4070a790a00796c194d26540be9fcf639bdb8ecec875181d14b77be708afdf0291b60ac10f0ea688a8023f44bb18aad601a9decc30dec51168cc60548beef5220750a7db4675efcbd
+Qx = 6d14a7c559f35f2fbfac6c9abf07df9e11700b42e0d6a9632f0bf7a45163322bcc3abcc90a3cc1877e64aa601d5ad692c1a9e7ef24421d49b09d48fb77fd046b35e0a9e29970a88
+Qy = 2e327635069999a834b62cfb2abacea947891dcdb7cf10fa5ae402ae50fcde7da0a9b1fdd0efa5a965a24c6516e3207a0558e1e063915cd247f648fb21036f4bc342abdcdc9e2bd
+R = 29f3ecc8586955e27092c20809154efd00891f417a800b0de978c643b2472a26ba2d1b9aca3001b2429d981c15b7bd20369848f35e76a800ca9d4d307a1cdaf63d4d0075c598b39
+S = 27a4650f39a0020c0c17126efeef5f72d2800bb59db5f674d627d688c090c840487d7f18a3e5ca7ba084359a55e592f55ed4c6865f73cf433f9dfa080682ea7866b84744fdbc6aa
+Result = F (1 - Message changed)
+
+Msg = 7b5f961721ffc8fc968e682f15b37d30887bd754cdc4ec3c8447a71eebcb68166d0669e702e28c2c6e9a43bb2746c9d0bc1f7b0b965f70e0c3a1e789fab91fb458b7e22817290acd7f2b09569093723622c0e937fe390aebc84137c531e09ad23312ba5e66ef701b5cab1c509be8485a08c5222f4aa420214d37e48ce9aa127f
+Qx = 336bb3db0b386bd2e2c5c71da79168997bf1cb655df8bac601c51ff52b7107062d80c728e07c3c995a94bdeda8d2175cf043552a36fe515bd3b6e19e26a6823c33697000a942bf7
+Qy = 662db8734ea015b52febc4679d3caff646f4cf765c9dc82824a937e36d73e5e66ece9062ef0c686695562ec50334c57a3fd741d3f2de17bea56b6a491b6002463e66d24eb26254f
+R = 3d31b548fd07e0d620a81c12427faa705b120592be17c56e2b9e2dab6e49dec65ec39f4cb3fb075a95526c82ef02a58aa0e61f8db7dfa545cbe346140215d0f4279ee64a9f1bea8
+S = 2ca15fb9cfa34c33e77fab033f2c1d6b79611d3e2da271fe7bc8f0e8439c3a3d1ec99b5553b141b03d6d42a5c341180e590176a74f16e0d998aad53c9d7db92ba9f0d1ad7d80f25
+Result = F (2 - R changed)
+
+Msg = f5c1d140826322df9821f4dd996e7fceaf4ef8d85e4a897b8792c9fab5662326f82cef6346241d943cd3c5893da559eb72d1d51fcbd15fa1770ba6f4717809d2e5e55c57010bcdb01b86a1be3a6499a5518577de5232230f41ccbf8cd86cde46a1c2be2be74f664156e3e14ddb1533180ae91ee65191bb655491810979c4b064
+Qx = 1ababc406eb7f29e7a7c5ba7cd80fd732c5ef713417b78aa648086a99dc7f750e164f8f4fc4516fce57e9806c2b4e5dad31e0af59da0b89a02fe28c20a195be7504ceeac1284700
+Qy = 5498a58f8aad8362f469c58b55e2dd4350bd410b9561e35329180bebb8304679304cd60e33ba8271024a6b9487e3158b1c7646e42cd4529d8714f5c01d4add701c7e89133b61eff
+R = 2d80593e25f4729e2530c122ae7a7c58f68811e2f607812c471120e0eb81d1f592dbc3db8c28a26913ea948740b846d15f8286d598d7a5f2be43f16de1af06653a0012775773ba1
+S = 0f477e08b174cb3f9241d9ea704f00dbe2a3f7eaab4d6665c65d871526bfb658e757f0663218b9416549f925afefb334d019a5b241d0f0ff26f283465392c3776690c794927285b
+Result = F (2 - R changed)
+
+Msg = 98d8e8d1af0dc83a84b421dc248bf90f40f36d3cd2510148a1219f85d0de4a04f3a3cf7a0b941ca09569d71e2cf402eee7a267444287fd4075e219278600c44ad6e4e52ca76f8e179977805c1ad5711c06db6b5012392404add4f7702ea030b2bdf20e7aa31b3d39a9a9d73ca0ab0eb2ee3bc7dc6146467aad5194c2239491a8
+Qx = 2c91fcc5a4cf545b6788f9d8463c6f85f647d6b768d7a7783186b96e5c1055ac0ffaceba66b6c0cb456840ae214511a17ae3f0fd4cffe8cbaf3fb8903635966782ff8fa1950e8ac
+Qy = 244156657709cd518e8773d92a57d1c7068215adc96ddbb00c9060aa77c459fa6f1b11bff2f444f790cd8a567caa981d492a3d18d0382dc7d60d5433fc4c119d3562656f0b61cb3
+R = 18c15a8ad00277de3589bb9a062771de32d8527997f3610a63bee85c771d8dbfba4f54177b38953c7ccb0d031ef16aebd56720a456106e567fe32d5885c8598c80967dc4d6fc7a9
+S = 06a7bdc846f198a3d74db31efd5369e0b7d13dd9e664ce53371641a9cadc357133b1aae7d1473be29c69dde50e0c182f05486c63a573d05878a6edf4b046cfbf7fd5c033ea939fb
+Result = F (3 - S changed)
+
+Msg = 05a8f8cea281f62a00a718724b77826965f19550526930cfd6575ee0612fa8b8f2f5cc776392415751e63114346344bcf4bb6aa6d065b9e1d067d7df5bc444dc1041dcd5489d78dfae5971c7fc7c11e5e54bfd1cd24bb365b8758c3a38854fe3778e0c2f5fb9f4bcc8007a9112717eb9dcf773ca31e0ef6f29ad1e57cb52d5f2
+Qx = 41578252421247e4fa6134dda6829b8e0a5e86e2a72d926bdc7ebd7717d6c7d5dc1406c40b987564ded43144b9cad26b2d2e955e3982db4083d8540def43c01eaccfc07f3a4d16f
+Qy = 195fdfe5c0aa57ecc1214b91561321870aa05fe55902159ce73f2aa635940e6bbf53d0f017cd9fc2d0a8036f6d9ec417f077d2c80a31c1221137e1387245a281a7580a63dd00fc3
+R = 35dd38a257fdc160a8e86813b263fbc85a20ad8ba14505990c1b50f4f57b3062636cac8bfec72b622f85f87592742e1d9063b4ee7bf3a47fbb63b1044d337ec0fa54b1af82363e0
+S = 116c6e802ee39f7d2d2a31fa3278548387e0531139db4c2478d834f05cf7c77e4295d1ece85af2a159d7116e537e83a1fd57616427c447ee5b13587211c3a9b5781fe5ebc759b1b
+Result = F (3 - S changed)
+
+Msg = daa8fd2e440ba44ffa80d166fa6370087d71e6dbe48bff352b41bfd2d96d2f6e43b0e25fc55ef7c39865ef0786924a835073444bdebc71a1710008759762d3dc6fff8df370369011fa135f1dd078e963c85eeddfd9cefc33fe31d863ade8b68633e6a2553a8759e83101e8757c7a17e21756fac876a3a9d6fab52e704e406d29
+Qx = 15fba931e52b25edb0c6660fb464ed4221099289e3f4781900ddb655b8ed05831930f039af4dab646a1276c2e70b06ebbcc9ced1928e762eefac4b32dc6e460d396364dbd0a1296
+Qy = 2007dc4b11a12101c03f7d77eb4bb2aa20f83254617ed8adc5276d173ac3f410977822b370ee188b403e72bf9b26633d7e83ce9230b88d0fd95f0f0b37f1a5b56e22370cd1be29c
+R = 0796cace36d5079d4c3013fd6c7c47fc8cc1d356acbc1e8316e708bc33e12ab70aebe25761242557b22dccddc241c06b2774e184cdaa730f7b727265917692f0a04503290ef20a8
+S = 390d149e7f276697f61953309606501f68b117dbc4617aae83009b722c632446965d9ff77db647494ca871f8aab1d69230bd137b4ce38f24935635caef197275343801f57c6d837
+Result = F (2 - R changed)
+
+Msg = 4f3ff8f77f0d09d4ce5ab11a96400a4624d213efd6a1ac2d4c548dee1ca446421e06f8ae5dc9abb4bb975cd0189ad8d3430ac3fb4c4b1f25f492c3cd5c65ca61c3e889dcd2d144812c18e25ab5cc9d294c2f19f3b98d07167c9af29c15800fa4b4a6047ab8471a22971cbeff2458006644362f06bbdd114b4ed0988eb96f8d79
+Qx = 56c2926e133253f36f47a134aabf7ba03a44f279603ec9189cb481d0f463f04e50dfaebee7e47fcf6943855f451b2faa56cdb6d8a8ffd89965a358f01bf74daf5f76c8c7e22742d
+Qy = 69a86837f2150956a4a0ec8eaf15962cbb79a4e95e5528a15307c8a0d670a714fb22dbf708c7515f2c8b2ad512a8559f1dbfc8aa470811533848d7b99fe2473ea824c1e11af3a24
+R = 3f098d1fcf5eb129e2eec142733510ebc35536f93aaa2a08c1945ff701751661edbc4f96243b6126f263ea762de985b9b056cc41160f372162130dfa3c0b95c8e384baf7419247e
+S = 2dc5d8b9a9ea96c66805ed24e4b5d9ff5c4dad5922bb5ac1793cd6ebabca1d2d722e01ad60b4a19fb8f7700e178799ec6ca86c5c6fb9a07d7bcbe3a6ce4f6cce72834ea6a9f35a8
+Result = P (0 )
+
+Msg = 15a87fd98795b558c4c83cf095b448dcaed11c3c404f6e13eef8ff7a8323f9d94685081a184c4a59e707b7722f05706d4cfc31639e3df7af298d25f24c48e0bf1f1a639742ed89aa107a9b3287a711220740cbc46a74b72031e4d0c56e017c06a9f714db98d88a4633e543160de2b57dddca0004d61f097d5bc6610fc9beccec
+Qx = 56185fcbfd8787bdb12d0e484b01742b2a7877b9c5b349543a0dea74a18f138e7b68b5ba2aab4578c48b66a79d1056414ed5609b2f1f7f31fb1728c637f89d33bdcc74969828c61
+Qy = 327f4c6a7c08095de1265aa927f2546358507b540ab4ccb3fe4c5a2f00a33f199de1f8ef9c37b4dc6a72860cb2d47db9162e29ad76036148645f9e3b0da6e2b2bf6eab26af908e3
+R = 1ff21288d1894721011d08dd3527184dc9c8ae717fc1a870a0e83b1ab0b4fdb24a8db0d9244bfd5f69f7889329c9f3483744f5e4109d3b6e763c7f65480389a5e65382c6a9ab246
+S = 151b84af762c39d8510c98d976d032bd3eeeb9e70e733d2f130197a2aeaa2827f23fb5bbf3041c9ffd84f53c0627756aa883b0f6d684b6bd7c03ed1d48feb5e821b110fbdf9f60e
+Result = F (3 - S changed)
+
+[B-571,SHA-384]
+
+Msg = 4d9e5842e43e22ee96fc6c2be361d9a75d81eeba8ec139dbef72335d3b6056e643e282c64d5f0e06cee964914629b8f634fb5c7ecd30deb5704d565bfbadfba012f1ab3139a591c8f140e649a5bbadeafe5db18135cfd6ce65aa8fff0fec4d8154502cda52e5c5ed1c2d3db334707f5d1142f231bfd41b21181ab61fedad2a11
+Qx = 4657b98e6622a97808eb6d45485e9d3670390d944711b732d48bb10bbd28c05f4c2a3fb736256466abb269ca3eb4f8693781ae4c9ef7995cbe35ae898ea9c519cff86a04df99b13
+Qy = 3b24adfaa5781380d5f241374b427d485f4838d5b3e755d6587c28690c3e0e459394694fbd6d4ecf92bfc89fe60b02127ec7c9003b28c865ca7da255a7290072327ea5fedb1b5ee
+R = 2094965269d21d4d0ab9072e2df9b1ad556272f06d8469fc49b256c30c26f8d9b971dd8407a82108aaa14f3efc269b6ae13c63bf8037ca413e121fda6199e580514c3709831a58b
+S = 2ee07ab49d7814f67774821584bd28b1135d73d9e35fc7c2b2b39adaf5951b9f465c69bed18d2512af15fc3401d6e42a3a406896cdb07cf7ad02dedf64b54b9f1db52d5f2f32653
+Result = F (4 - Q changed)
+
+Msg = 9c090bd9cbf2dcb27e6ef7502cc7152b1bdb771b3ec0c34eedb2a6794085b1dca97ee504376ec07a6100f113c345b3f8d22c96fa0b3664cabb307d81264789efc66f5df7705d84cf25b84eb9c9106f92f114aa131d866bf7434a8776c72b72898bb52a34cb449c7ace287e91e0547c6e52c39ecc4e3aa531d338c154f40ed37d
+Qx = 1ee34816f502fda732b2fe4f35aaa060890f2d51b1449f7f2d3e7918680eb9c510cae00ac0095e25a67baee8bd841eab79b11bb923b32389bb2c8b91c778d0df497304f47de42e0
+Qy = 0f7c89f970aa7c89d0019831fb39738d30b037ad1adb78a19d0ebd098dbe071ff1ddb477050fc0da6f5cecf3a0061de794dfa8b3726f4b6e303a378b7baea2599e6711fc19d9f6d
+R = 2ff332ecfeb1ae2c4c0688ca2e936bbc869dc0acf3439e511990064209a2774086c701dca52bba445614693f9305b7fb114f6493769cb330915c37511aafdcd297b58ce4d5d17f2
+S = 23d36cbbbf089d0d395e3807f40ed90696d6f1de577c31eddc01a229a4f34650fcafec259b0dc2bceb07e7e2287f4babb430f4eedbba18a9efd94e76b49010d9e1daa9a351f7060
+Result = F (4 - Q changed)
+
+Msg = 529a6e7f5987e551134f7ab6c84ab258e9e5cc6ab51226a99287a1f730d25f9fe835b732243897d3ed00ca5e8fbd5755adfa6bac9a4be217176e9b56cfffbfd73891401256d39b47364b64a6e80db1654934dcd6332902c392911d4804f583fb52e51a353acd2b547640af5be0b4e597d805a03253facdbc99897c89108b206b
+Qx = 73d0115eeab88d747e89afbf49b42c173d6073066290ee0b94b479cf77ca69f6f67c5ae2583805d083195d9d7aa83b2a08fd578fe1291f7a5c743a016232728f4aabb388da2c72e
+Qy = 277907a9476a80a4d337c3c322f21c5f1160f83c4015f0775aed4d95750fef764ad88df31c1d7edcd92b80395c911928b9325f16b011e0c2e0364d3b8ab42a4aa57b9719f050e3a
+R = 3f01d4596ebe6e72945cb99a115869edc860247fabd46cf46272b26bc7871546ce553208ffa1332904412515a4f9108c915a1a58bddf33c3d8c9fa642c635fe0d2bd38e6a0750c2
+S = 090ecd521b6db5ef5de4d81d3b53ada5ba8641b22577dc92a76dbf79bec0da99f407655ddf4e96faa004d0af2dbcdfdc5fc96e4c0c35f4bf553b1401fcc71347df23ee9b6d13f49
+Result = P (0 )
+
+Msg = 798a5c97e56270af1f37d6192a1fc2e76989201f03de7fd1274079c3238fbb21d09df02999282dc2b4766dc708e0dd1493da87fe79e4b8747f94b61716bec352a81b4c438e334b10a00c31b8f197c158781675d881aef170eb290ba2f163881083447b70a0b4bbd713b19f78ecd9a20c4cfb80def30e181ce7398460dde86c2f
+Qx = 6e548c1e3290dfe27cf2c30bcfc65a245cc0495052cbf289b285126b9ec60a853924d290c68bb64780a31ffcf3084e0d3958ef724f7acdc0a726e906148df7372036c9eebb82ad0
+Qy = 08e5b78610025a49ba9345f1c7a9d32e59ae68cb9575770ffc12890d6383eee29cc95781b66ff5779a3eb1d63c7f28542d77f048a9c82eebddb1e94e16d0268303f7454997ed8ea
+R = 037ff4dbee6639d1b2f637e181112d35f8cd38844480327eab7d6eb8bab53c5e6df9efd4b05351c5d3478431aa5d209a2aaa67bca2e1a25cef86d33289fe109d7a358fa9c4736cd
+S = 250d774d2971c9174ed11efba9f1a26c798a1b64edeb2c199ea2aeeaf00c4af1d559ad0e595891ccd6502d677acac0e918934147d18ddb34214fa585472bef6ce59e1e1b853fce9
+Result = F (4 - Q changed)
+
+Msg = 753020fcb72f7ae59f15bde04a7dd96a86d46e2c9e5f9d7ad0e20128026c148fd3061757eb146d3be35f9f2dc49be553769790072c7ef7d0a1f8beed39d19fba2c8f3debed4d87722f22714a7a4520fdd8762a35a0aa5bdecdd8134ffb11c5198a7999a7017e9877ac9351e8d435f02add3e6125c7a49b3d43bffb564a61df0f
+Qx = 22bdff789ebe8ee74bae9c3eb08f4c0ed4479d4771718b5e2ad1b4aaf27dbf6193a86dddf3d2d1ec24c5c1964a8c4af530f20950aa28d083278abd8478a499a5f88698b34bc7109
+Qy = 3382bd071611f53c9ba2cb8000e05f4c83d860aa0decd7225fd734504ab2a93eb2160e5d329e764d476ddc7fbb5b3e1a6265667fb6ddd51108c2c8513e984845665a995c9f2e33f
+R = 0ec4634dbc6f3d7cca89f824845767d550821e3a9e4d5b4dd5300a08d2ecd2fda608ccf3aad23a7f33637f01ec5f6f7a4e6c91ab4a70235d7a5fe45155ab0a7ea44961f31cd910f
+S = 3df9218e85de6aca5e6a8a1254748ccd4fb77f364a41be2be42fb20e0ac6eb811c3c5b01b5ccdc29ca36f88313dfb3e9a923129f5b93fc3949ce7e3cce9ddacf28a5cde4a6f15f8
+Result = F (2 - R changed)
+
+Msg = 7566f8106c6c0995f0388e9273df46d59d252d962896d63b049ac662619e16e50cc6ffa1e5ff31cc967fb18c6c91523f40f93f15d0fe3d543d16cd6ba6c58119130082d89b9d09db200c215f1d92a38fb76a631e53950d71d8593c5328007b0710cb00f96fdecbefe11d56acb677bc0d9989a2f12369c5f550207b2b9dbc9288
+Qx = 5fa5bdfdcfea1cb4b1be1cc0840dd374dca181e2d89cbd51a2d8d30ba53febe7d850d505973a47dfbf1f001154b7dbffaf4a0e242ca5849326ec691e671fdd41e84af93df79dc90
+Qy = 0a33bb3e48240cfa7ee44c15f93df48bfd9b298587d1de0f778ebcb8bc48d75264dd0ea686a4711ae3c20795b127ec8bada382cbba47ad9c6516de58dd670d77e8ce8c2c4b110b5
+R = 0ab47b7bd6eefdb37ae2ef2b90eda7e84e1321d157656670d62b052bcf4555df4c8a1cf3364928843cfcf79507d253f7332f9e452c4d968d0ce76743f9ef012c62343b0985312cc
+S = 2564f32e696bc799fccaee721806f94e6bb063fcf7ad2c0f53c7c8b50ba3f65548670a30744c74187341351ed2264395620dec50fca8592eaa8df1addaabc908670bd530295c19d
+Result = F (1 - Message changed)
+
+Msg = df7e807e9f523870bf16b16b58d12e2cf91372d1fa92e245160033f553a2996a8c7ac23ba6a64fd0bfe4b3b7fd569c5f5fcba0a193fd47b04ee29ca8edb8b53f00e7dfc07bebdfd92f576b06a37d6abce3f452a437d764f2f53a06bd2490d049bc4d28a0025c65b1194e865e2ef537f73d76dfe702e87591cefb4493514e96cd
+Qx = 7b187e2fee5e316c8cbfb88ec17ba5b4b4ed4c6599634c9f9234a1586dc736ff7ef803b77f6d214e5040a8a68acb3920bf7ec4a900471b3be074e200acd45bf521281cc6cda36f8
+Qy = 56630cdfec8f5cc22b8b7eef6ab02b261a3ebacc57b072d60a4588f846050f35ad40733dae9fffbc81f9d1ccfa165bd711c7bdd4ba100adcedfd7db8e0ce8c0ac8320c453ef740e
+R = 2e39680bed616bddd60d5dee1794a3b4673cdf6d08589b7911b38566ccacff8769d3bd677b6aadddedbc7896e2a6fc32dc0a5bdf854d15132dcf8cfacfcd19e4fe8349be419d57f
+S = 331d599823e82c08347bb7c458115c68f4aeed19fee208a9d2a54f6a7cf88494d30523b726af6be5f0dc4a7f79e4437f7225431e98c995fdb17d44089aaac20e87a84c638c81718
+Result = F (3 - S changed)
+
+Msg = 1842397df04b5243b41096454bad6923e5726fda83ea070b11ec5fae740f7acd14006a6516ae88c164f0d8b5aae1257023211e7a08b1dbe3373428ee02e202728aeb768a634e5aaa8f7cc882a5c4354b38a97e5967a3a17f9c8ec456642e18e1e1a9584d13325ef40245cf38883ce788a21320013c40f450a77fea5d96753535
+Qx = 22f77c57442e718ab3b1f86572bf77ac369c21d3798b32cc5a14b627c8a548a2253b871b4f17b2ebe79dbaca762d1022d22556e4235bf313d535f92d825eeb5a06fa6ce99b43fff
+Qy = 3ee721142cf05abb3a2b7ee890c6b0bab7cb71b6850e68c3e63c24c4a133d195546a50bf3bf887136da690cc1b5106545c72a62b5ba30f255d8d9ba85443264632f56ed55fef7a5
+R = 20599422e0317985b1117c2d58b3f944975d22b08698faa0ed781b11118494ccd6f3daed898255d0da6f9c361780ec667bd8b56dc19c49c74d0a14a5423aa4f73108d856231d2be
+S = 38228cf0c20455e5fb1cec717cec13438aad9e07725c94b0f46a9bb04ded32bd39319c7a76c90d190c1b27c45c75cb66b09dd2563f63ad0e97dd8f228dffd6132ef143fea97a6fa
+Result = F (1 - Message changed)
+
+Msg = 52b4b3538c636e8bf607b426eeac86683736d4c7b5b26c9082de01242878aa392b28efa904b65b37727998dc2f183bddad4a52b51f788132f2a61692a64167fb384782de20dd3da71f9d4e391e44926ab756979deff217e05626a32651ea9e6f989d39acb67e5064bf9beca71aa0f1de13cf73994d5d57d003b2153ab86ead30
+Qx = 06a79790325d5b95634a2a9f11fa604501fbb0ef4b08c5f48322f0a481560f9a627a9679d088e7ed5b11724c6ddc9d21a04f8efcb481182b8e6f35e3ff796ab99f17ad2e06e6d5a
+Qy = 3ba5e83b02e36ccdb935b88f4a25518698d92bdf3cebc42e911e6c70c17b889e659fdb5a27218e8d9781844314d94e08773e71a1a98c68f51ffa849305b864ea61f4839a7124e86
+R = 098535be18b216f85a3cf367f42b9ebb295023bd584c1d5c26d5683fddd7a6dc2338b496838397cc0a549d89cb4873e3aa663deec1d4d2177d073c200f8e9b157eb06dbc44c7a0f
+S = 3b48ce1d61c3e8cfaad8b821a39c548666c00269708223934f9b8aef9ddb985fe6a3b3d81d4b3b6c8aae9e49598ddccc95e38658457499cbffc29d9947f1fa7e42981a3bbfebe08
+Result = F (3 - S changed)
+
+Msg = e906b4cef7f5fba32cc0a5498ad1281f8f19c809a88728c9240ad2131f05fd59b7c97ced31a55eee25918ed8720142eb56ce8db7d9abcb6d65e61e4b5391be2644211cd7606d0658680b0a7c3ce4ec018141918f9fbd6f973786dc1d6faabe059a756bab5ccd255f7c70c4b0ca256cfe7c1364813a8c4dbe55ce313a4948e00f
+Qx = 34eb4bcd8cbb48a2abb42503119d23f33df9ff15cc6e542504d715fc8a8cb77dc79f332c423e9bc3f3f44c247ebeed8278593e6fd6b88ee16a24d72a420081a0dabbd35ccbc3983
+Qy = 21f99319326e668473bb7501f478be2e143f1d16572d5845b4e67f48c7f2e1617f92989d6bca07170e5e4424a993265dd4deee91ebfdb0cf6e98b2398e6cb3187a97a0a34a961b2
+R = 02e8bddbc17209604d948455bc92c8affc8d87d914c53a471f69418c173245dac633d874fdeb448f95baf9d349772a89117e36efd5da64a52db21943fbb4453e44c9d49d418d39b
+S = 05c64a8f9cfdd10cc095c1d6415c1371ed1a7a760561ec884bca5861f4f3ea4fbab05c12191c93aec2502c7f849ec2fa85bb01ac9bc64cb3edc2c149dad0bd9624ce6dd4ff6b9a4
+Result = F (2 - R changed)
+
+Msg = 0d51a83bdfeef48937a92b60a8e2c14832fb732623c36379cdbf108837b39a2496751c19342b94adc2cb343ef35263fcb7da9a96a91282b97f45550c2f204cd1dca1dd367c86e81744e8942b383e1caaa93ed94c1c31d08d950dfe2fc7cf5475ccfabd8e6668a8842dd3ba2c7f3951334ca63f6e56133e80d1e42f3ccc6a8865
+Qx = 7e8590ca0d5638d623d3e68726755ef5c4c1bae54e246ae29fdb1a6015fb22cc49911630e43f040d5933d6bd1057543c208ffb009c1850604acc3d6ee433fe7dabe6d2b1a2e9b0c
+Qy = 1e651a240c390ab42484825a7d2eb7811d171cae1af9ceea00f9798721c1b623d7813854e6885fe560e6775f2ca42826c1821c172714fec02ad210ee68674dc7b305a6a63548bc3
+R = 306769ef019857d26f423a3d211bc1929501c62fb9d3055d50c003e6008595572894350dcfce930601bfa26cc027d074fce875d7cb7ee2f70c5e279f03e11c414897438f1c9dd1a
+S = 21a3a417665a5970e68af6ddbee6723a4bc3a4ff457c5b734126cef0018eaf6a1e6492418a645d5edf4181add6cf1f8195dca15b881d2763f6fe553ad0b595b763bb3838f0a2415
+Result = P (0 )
+
+Msg = 736a7acbe46da40e5d9ca1c7fb787c4a9c1dfdbe87ed64704c9b78baa3edbfee0f12fcf77920afa6451d47357a22f365841403b2c4b1439b92056f70da18720941aa8bc7e4111dfb4885a43e61549e9ad7f856c427bc318f0de2cf5bc842d33fd5d737c53171b81c86ce7e7aad01b25ac3d2ddcfbee448bd6cf787e02140083b
+Qx = 3c8859ee7d923bd7f90f9ce33934f5751e846e7049f86ab9600db7a74d06dc5c50a0a1b3ead67874e064ec87aade3b8041994225884871d0c5010ba11d5d83de87201262b3ff43c
+Qy = 3ad0a37a72d80d9a5dac591a55850faeaf316162a651453b3202aeaed29f3ce2a48c51c59cd8bfe013a47d731d751cddbbd9c5a4d89b6f0e5929dc683f6c439754ec4c9e1e7bace
+R = 2d9b45dbb5c483f831df1478a7010cafce1ad8306746a797c27c35f669db400a61e02aa70d4f435c73fe8acd09e2060167811267fab870425f8dce4608f47aadc6aec467ed68cb9
+S = 108e6466141eb0208cd77f358ebc81404ebc703c5ff24f03cb2cce17dd0cc53a1189b0d55e0283f62eea87a62989fe71125988b895a98604852622d2ccd545da25e80e2b509cdbf
+Result = F (3 - S changed)
+
+Msg = c7db000395834b8a7dbaa07e6b9f15232a5018c0457ad25aecded9254ef50647b1d3f72b463850a9fdfb360cdd557688a42e7cd6f19bbdba73917d063b4cd79cd790432084151be6fb5694e79150b2c4f81d05e49bd4a8de4446f686e2b5f08ff70cccf696595f79f3b790d0b0bc791ff66da8289279c421c7123381b5416d36
+Qx = 42df3a6b89d0f5511ee97e6ae2a9e09e1c9c4801e52b099d838c0905780551df9263c9a83e49027a6250825722913bd961e90ce696b62b58e1f626386e31bba3fe9aa0f443e4051
+Qy = 7d8d9b75027c57161dac9c67722e2620ea1e52815728d8aa4c1c374476f8cea506c9d7d1260a5ab6a8caf4bf81ecda932fc2adc9a8524f22ae0afcf092da736007d9698af9bb0b8
+R = 352e8634862aa62439eab3b8dfb26ba8a17a0736463e603dd8bf6b00f718676e6cc498d07bd5f240b5ccb0791be0d153cdfa3fcfb197d1dea0438f871644f719ef76644e1c1f104
+S = 03716777f6827c99d2566033648c5910c9c5780ff07f2da0682bc0ec30eb1adff0912fb0a836b2239165e715d8a608363cde44c58bdce5133ab6e906d33326f94209e5343e97f6e
+Result = F (2 - R changed)
+
+Msg = 053e1beeb3b077403012f706abe55cc6b05bc0e424f74941fd6db5f42c2d31215cfb837184b9c21d7366c2b2c4001cec3dad6ad2f3c0487e72ccc0774938c3a9f371414e70bef2fd29982fdf152978da4c836beb2dc9f9fb4a28571a134337f753fae129563baad7d0b5dca838e85c79d4b5c1f4b94d24732a2762c79781c90f
+Qx = 72c0fd8768937d28f5b031ca7a27a78506658b4a837f5db8008514e70ba342e5e7462796e5b507d8554fb14009e74858ca60354b7974b3d3b668e6578bf91e1f60351a76145c6a2
+Qy = 2f4c138f4d1d9cd6a811edac98cbef3a98129472811dc3c560b7c646096886b2b83fc7e7c3d6b0b5145d7e26e00c0efdcce833accb92c6fdda23d3d19feabac261301031c20b565
+R = 111dd7c5207ba78c154d8b122bbabffbcaa6b1a9b67cb02e13c6e94abe5b6da7398f1c8bc0cc483bfdd696a31e362255d0aa4e86c819ad9fee27c190d93677076626b2529e2137f
+S = 03c1fd5997b32ede7e73a67068a6a225b01bcc0521eaa4db3536daa769e548c6ac307ef01d153e30e0c5e1e76280e05a72af5e72ba631a1089cf74d78020ce5efecdcfa846384a7
+Result = P (0 )
+
+Msg = 3873460ff20522ac13be0c18d49b4158d5ec13736906bc66f80eb6c7a6c86f2f1f85a1178ded104ce1a1c7fee2c243668a513d07bbd6c68458156eb6b56048b98a6a9ecc174119eefb1e7a7d3038461f198a49b926fc842eb68615e84a36d377316c4ff2fe0d1ed8c4538d003c6017bb3f694b074c32b0b2c40cf7201dacea00
+Qx = 6af8ebd00e40343ebbe9aa47a8683147aed952f4f1e5bfb722c4023d979e780df96cfabaa2db73a064d14b6309e762a56091ba6b47a68c85e919b58f7a8a56a0a1f1fdd392d5987
+Qy = 58322d667ba3577a74c8a8460d6edfd7d65aaf3260665ebeabce3a194bee9c8678633e1ffbc7d7aaa94a021b4ecce55246e373aac068435cb8b4a8f0b1eaaf9675022b708bfd8ea
+R = 285639d14198fb8838b3ad37da446d6afd372fb064d4fafcf35035669453371fa48068b28ed6fb8d6d136cd8b801db33db384dfa7a52c96afd08410e07ab5a75db01a7cf80da100
+S = 12b0f3711d2fcbe50b282918df5c43b2647d87c597af4f870d379a22403bb6d3c1c3863e1b9ab8a32144180cc5b7c938b712485eb4f6694bbc3969e96a8f5c2d8999f6bff615f90
+Result = F (1 - Message changed)
+
+[B-571,SHA-512]
+
+Msg = 1e10f08ae677e1263855345ec635fd19cc134da08bbf9e95ef459ff3e35c556d83d3fe943bdd9ce474bb93199743b6ea45766f7190994aa4554690ec084ff54c83bbe5c09a609043308b06af172c7225f833c52330da850ba1932a0b8ff9c0e558b0e89fcae5465bda2ae9cf59bb366c4e90ff7e23d76b01e5f82415e5de673f
+Qx = 44ea73e0d3ac889be474770207ea6b9a0e056c991be02aa9ca6e00c16ef8a472533ec0d2539faf1753f4d69cc18fbec171ef7b3fcf81ac20e28a180f564d4149cb650b085efe2dc
+Qy = 79f5f20f4c7b2c8467dddb21032f473eaeed3338e5d0eebf13704487f3e2d9de81e575103256f3e7813bb2d7c5c98524c534fb0a4fee962e5ee7f141b54831ef7af80eee664319b
+R = 05318a21a178a46be52f3a3f0888458a11798c4f26c632ffbfe68596a434f438df74d3461fdff32f4c797c5bdc84768b772545a57b89283fb2a51e97406e4113a4e7bee32fcf1d5
+S = 2f0423e77ceab4d524ac9e3b83e27e3dfecab9382512b3d543aff00582ba0ff871e7e82c23a90bf672c7ff1c4e9fc84450e8cac5eced46a9b3ba4b65cbd37ce0fd2fcc8d9eb3fff
+Result = F (3 - S changed)
+
+Msg = 83b7cc897eb53d55a27c89740f7ce966cb93bea8cbe502b6ef12b2fa8c2f566d6ae980c4350bc9c5bc9041d638e58fc267f7a6a2f4cb398dac22fd04b065d5e9b08b0d4b9befe951f0ddb424d74788b46f3dd57bce999a2cb7e27fc2828e9482c9220d942512dfc5c0b92b35c49c00b2255e55bfe99c3563ea800cf8e5d71dc3
+Qx = 08817901a73539e642fd0f53b7a91646f041f78a3734cec37d7b64daf64924afea8bb876939deab9224d4e8c1b730e645758bd0b9cb18410514b6089b881eabf664b05b01f9b81f
+Qy = 77c3db446be59f90aeba82322a5bada5d88bdcbe998a6c06c74ad18565b480d0d17aa367e6edac3788422b2e87a661e0ff3bea3af981a2f33c576da135136654ca7cb63ed996416
+R = 31494dee5039dce288f7d723efd7bf6bdb942b733b79b7998cae52675382a0e021995d70d023a2fc6e7f076c0aafb411183b1718e684e76dd995c092d90064bd6b97a043312bd1d
+S = 1b9ae7731a1a3eca578c90c259f84435028e2940b797e899d2929d708b6f6d8ce2c582ccc9d4dcbd5955a88e82302e911560ec5317bafbe11acc87e97e316b83ba350e9bbbd44bf
+Result = F (1 - Message changed)
+
+Msg = a1667155af0721443cf5b6ffc356e14bd40a0e8ac23df4f18070fcc0ad21a81f874b91d4a34b6f6102bf2a287a04f1c5bc0e53932e7ce0a142b4630d13cbfbaa03f986e6563c6a8d4366a7e3d0261abe396631187411e2c435ccea390ae480d3fa1ccc9a4224c7670da2a7b7d0476486b018e915cd8e22fb6133b04c4d7a929d
+Qx = 1d304181297022a6e8948dbcf207c06c2133e58baa407ce5b4e74f1eb8bd57a8eea907c859038b2ee42447e111d13d2e3e2e366c1d2a3d3d34ef92eea40d017fe2175e7c7b70462
+Qy = 758b210531716fd3f0451057f7813bf5d08d34012d6fcee34ed246462e8835dc5c3c8ca0bea3711bd9d93864b723be8b9cc2335b62994b6ee24c091e4f231e0738336cc30907d65
+R = 23c44d462453f832b5b80e32be216cc07b2c3ecef0d756af89a5015edebb7632e55e34f46172495592b2b1b22bc22e349e1123eaec2a8916d58f2b6c8ec7d4507b720c208570a09
+S = 1d7ab9f2a33fd1c0bdaccc9f39ea08efcdbcdbb649d2550a5df321a98cfad0c4fc1614eb4b834b386fce2030cf3d648b351a7ad1a630895460d3b4b9c7b973b64e0abcf9064a502
+Result = F (4 - Q changed)
+
+Msg = 75818da1e359eefe60e5d8c065d6735527b3dc07264b134d19a905d003ad438544bc24e5d662b6176b1ac50b8f0520459e091312fce69ef9b622948142faed67aa6d5b345e8da6712e223fdcefdec22b784e2858282cbf6e30997971d121f9e5363f7620a518e490a0e916d9da70e61836b0c8c5b0d86c0a80ab6b4fad30a8f7
+Qx = 35b8b217a4615a03ad0cc6e4ea1c05be493c2775084ee0bccd494e32d6c353b47c1557e027f14b2ca83580d0afdfc352c4b7b614264063e7655587c0e26d3b7bead526647d682ef
+Qy = 35cf96abc4b3eadf43a3cce37da07b23769139bff7f6ab71afcbe326b51f474bb6fcfa616be3f588111864aba8626e80e6ade7011ada38b1ad78548773ccca1a58f435354ca4222
+R = 1db0c7749d8ed8aef22b58329ecab603e279654596d8b448a120f4077a125cc029cdfcb986a60af73b166e9c8bcabceefbfaf23540d877e2890bc4a1df067784d0228988348e012
+S = 16a283b2ea23532ae5b08b2fbff44fd0cfeb4f34624d089832ac9c9f02fd1a440f5323d3ec01ac37b61a8a1b3ceb9bc299eab4d7076a7ac5540a1dacc0c5405043ab45319fb5483
+Result = P (0 )
+
+Msg = 83975ac6be5bb03ad248d2852030887863a631b3fccf978fd28ef5068dc997de8fc6f0a8cbd001ce94788d12f04488b8e31073fd6b267b196a4e3cdc9464368962490e0f204ec968cddadfdcd0590fb04b7b5d6eee81d73ee1ed2476a4d88a6cea747134856cbc21e642fec611ba3005d1765f5d7a91ecfb9a6882d084d923a3
+Qx = 1c6005ef2047af0484dd0845ae2af9500e6084f139d76626ae3205d624a5982311949206bb02d603c78802c64d1438cddeea7e00003c13cc44622a83a15b07e51d9c6b28baf21e2
+Qy = 3d6ce796517b30e31cd40094f3d3e6ce3a2701c917c146ccb465168fe3a9f71b0529873da057a52ff0b4e70642900b9bc4fa9af56be2ab6abb509338b418230eeded3fb058c4ddf
+R = 3f494cf16101f10b75634f7e7f72b6888d910cd5dbd666acd12c8997a581470b4fcfa4d4c5e2950d43a7b772016f94ff28413775d75fea001f25c585d73e8db123025155453531e
+S = 10b17a614498de6a9f7e17954dd3ed78d4b0ba43f32fe2a30a5d01df480fabdd56b99f28fc20e62932583422a81226399973f63bdc960f50895d1313e2653484068a80a626ccc8f
+Result = F (4 - Q changed)
+
+Msg = ed359734d2fff0591629c83d595d5eded07321075a9a28d072306532ff714e92107c7ec6971435a5faabe16e2928e638d1ff89ad990c33e436f9c6b8a211173a094599ddbab0fd1b66f4a46660a570e9d5564ef8d8a382006368cf960cde9ab9d999f84a0eb82df204c976d960ca0c21db4c1568b2077421d4b7f200d5c7c38f
+Qx = 65d40a3d9cbb58fe8461f97024fa1517ecc2fa899236eb88209659e6a64722093f98a138255957adb74c9625c3f8b438aba7e796f1c51c72429885c6491d667e0f0d5d17698def4
+Qy = 2ef7d9fa84404282fc358091b1ee52bb0c3197d00fd80850585e58cd553292753139a364c12616bd73bbd54099ba1959eb13f17abd45d467524860ffec4c7cf2e69243fe564885f
+R = 3e631f431da5905ba5147a12d869b706e76bb189df183f1e1c3d7379e305718a0ab339234c801a9d2ce7c87e7ee5f99e05dda79632278e8d0814ab337f32efc1b1533691dbd47b7
+S = 1753b6bb862953f2b5dee484d986e7cf6017dbdb906d688ac87db5b33d5f0dd3369e443d26e0d029ff295f05b459bdb4b1489c2aa3e5c8c3adaa7013a1a782c2599eb12c621bc84
+Result = F (3 - S changed)
+
+Msg = 471ef630ef02f809ba5abb0778cb6c3901a15693562d283548714ea5b5ec7b34623c751938fa7438488e148f8a8a58b5393c271c7035fb2dbfafe15fa5f96576e3d7f07d46e0e553bd534d3f587e288ba27df64513cec351ea10446bd207152189d2a559728c578cb81035a5543899a7d5b8744ed203f01c7c12ddfbbe99a5f6
+Qx = 5adb9ff3cd0b9021aed2ec7f4810a3b1b2e9db1ad487d8796c629aaa96452a10b27370ea755ea3b20c0475e70b48d04c2e455ddaea4ad52c1078cea3d569f11edc2fff252c4a8cd
+Qy = 496bca62178550e66d623b05c10d866f76937aa6fb68bfe44baf0dae9bf58b2f81d680f0c735be3e85419e23c62d828d183522d7ca1f641503ba4d580f33fb8771ceaf3013a2e11
+R = 22358cdfd48834b39ab82ee562f316d016a1618c68b347207eb8952479680062ed4a0a695caaf43fb3d45a9d7e25a5ca9e61a76e9b099187847a00e0b85ab926082d4d78e252fa6
+S = 0161f6e566241d2c516111ac5b44100100edfbd977bd506ea116c3bfd364acb36a33e7c7b406ddfe04b20db57d933957dfae0c193e13a783e4e00fe89a09fc156a73d17a143e3d8
+Result = F (2 - R changed)
+
+Msg = cbc795079985aa7eba9bafc59b60e0e3e3167d23f373096af25d5be2a476211f073d5badf4d3dce63732681c5b5b59f789e050bb73d4118d3fe10579cddf406ae00c8e3c67ad2416e2304a3a07087a0c137fd5470316cd5f0ca98269ad5a6c0dc40c71dfa8e1b3e6e7c272fe71f4e10b7f31e5a8e548692aae603147c862e173
+Qx = 658c28e26bcbd462993cb62ce77b89ddbad3ef2295b3b75ae48de3130c86945177e71a71914bb05de5498223cf349a826897db1c161990e1501086c0a2a216d783ba980e4c1a8ba
+Qy = 55d7f2e720a1ef8b92aec86d4c2d94245ed2ba4bcff561c6571c9902e7b34dc341842651c9927f434e17fa4f4c658934c7d1595fddf4a3f1d2b2a5dfc923979bd46f031b27417e6
+R = 27be1f06bb5dbb81b5dfd610bb4ed3a99c8b3f2df78afe90f734883952088e8be98da1a961edf2c8c6656f71a32014dfd1ec75b47363cd314492f524e7c7a7503521047aa1d26bd
+S = 149f42edf8cc9ab2081b1456fa2ffc1332769efd83ffb3ac1ff978ba3d4f3bcb362582f101ad3e648081b76d3ff7cd5fa99d6b85d7f4cfa0b0abbcd2d50de61f7c40d9a5f496e2c
+Result = F (1 - Message changed)
+
+Msg = 607e5118f7e390c713d3c2e6ff39a6b6f728c56c1540a59b9751d7aed6e13f2081ff496dfc375a41bc1819824d34a01ca8afa33be7862f1e987aedaa8fca8a1fd8810ebda4f1b7e46c936505e16d3e2dc995f83fa49eeed7dddb77f0f100b36e4cf58cad60025c15775d3d06b00adbed7b232c3fa298664bafb35542bf6bfcaa
+Qx = 158e5c22c7442b795569d02a0b25a675622744f861573525240aeb5c432cf25e50670eec0ec631415789d90631c9689ccf4254b198ff99fc60860315eb953e1d36fa3368c8283d3
+Qy = 193e22d0188b22b7102a139dc5866883748a4bb04db6adb6b7b1cbf43acc0ed8c9537c1dc4b909b70fdbc8a5f4fd85be6b77eb981d76c183c32e242de7373eed17ed113655660e9
+R = 00966f3e2cd03073cdff88735750c15d0c6ec23719450ecba2d46d97208d9a220fc4746ca8e251e9b96107196ba9e6e906d0dabe86f76e3a77b1949474fdb014c106737ecce8b3b
+S = 172549514a48ed6cb0d9da5c8482d0fa56e8a05fd23245385b13fca8e1e265bac3b2d6feed85d26b90d5e885fc7acca1664c4b680f139b8e215a2ec01130fd94c5944b1326f97b7
+Result = F (3 - S changed)
+
+Msg = 73c052e4b71c2596407f83e74854d1115b57d1d19808618028b3abd88e6b6982b2f5192359bd85810fad30e9a3edeaf3ce0c8a6a87522059d633a66556bacd2b4bbd577b8b1a5c94aecb1ebb36d171a4bfd0f0e9b32c7fa25f724803561427eaca89bfb7774e3757dc2b4cd2c7b531abd7fbc054a871a92e1a9bd9e06349c8ee
+Qx = 2bcdf60627ff923af68817c31b52a39ae7d744bb32e604a2211d9673633eb359300050fb05e89c3dca5ca8f561869c176e6905bdb278863b4a4c58561d4e175e4c05f73e92e0808
+Qy = 54f84e724e16b07acce042d02aec2fdaba599c69088085eec87b7c8e23a9297cf41f4217265109227aa055ba2986b8db520ed0fa8aa70233818a550b8acf3d956c7781a97f41d53
+R = 19c4e2f7b57ce8ed897023547c11c34f65fbd23ee7d38d6a0e79f0d3c6ddfb4cc8ab26a39a500f417b777a2a14668da0c132b85bab46ac26c8dec479285eb7d2a4baeeb898502e8
+S = 08d7cb2142ffe0e827eb8e47b1f11e126826fdc45b5b4ff9c85ca762e201804bffed3378697b38403d5afaa8cd6737e6e0c3d423e3a8b07a0619a123177958561c5c43b8a79d76d
+Result = F (2 - R changed)
+
+Msg = 66b79c6d8f58fc3ebf41aa6fca31334f66bd3c4ac2e8525310192aa38371ff26f272d29cc31cead37c5d6570a0236270510d4c699e0baabea0c0ae96d55ff0748805f2c18a23e8ccb84aab4da7934c13437a82c33baa5ba58dc6ac25df39784e1ead849064a445502c07072c1b5a5557e26d00ddd8114a642e2a76a069be9919
+Qx = 72aeee7afdb0599c587b027644d940f7753360527d6cfa8b9f960eae246070d7ceb4c320aad4f663d174090f5ca26b9fe98a03438a73b84adf1bc161d1968d758d198f87c02d6e5
+Qy = 663f0cb8afa910cdc37728d768368d8a9080c33b82754f7e7110a4cec4961b0674d47f800ff62dc89da3f98dc776b5d786c3d6e7dd1b59b9221fb5c3e805d4fef0afa0b72b48fdb
+R = 1b3fb5ba9d7ff1c29746249c32f9a43ec34c1fda14783e22b1babf1f58c568a8b40d1ee7cb15ef8f70fcf61b181240fe4d7cf41609b524a98eec8b59ee868ef3417353038f5c2aa
+S = 13b18837a254834b1ed722a5fca5806648717a056dd5220589d77098c4e40069160e4581c664323e1a8e29c6a8cd2d3add4d80613de5a414246fb0a8b8db35a8f71e72202bb9735
+Result = F (4 - Q changed)
+
+Msg = 632d4fe28e7842a0429fe994b7aaa32e107817179b999bd722d008e0862527791a929edfe5265b1520219cf3fa447fb602265bc02e2e03e496bb9af4e058b1a5568992deb1a5932a9639f4f8c5ed6d43c7d47d9fde8e5565ff61e9af60317fa836071d0d51f9a4130eb2af03f7f30dd8907ac1fa3c6833b36e3c54ace9498cd2
+Qx = 0fac94e2eadb629087a5a8d9e05cbdb9d198ed4fd986d2d5353fe1ee953c3ba2bec2f57d8f10217b3a0b5fcc3ead5811d966ac3cba6f5621a5ff4d278a0d881ba6defc889e42156
+Qy = 7933356bfda3f30277ebbba8c73c00f0f5f02dbfe56dfa4d95f6e8412c2ea0496e62fb80d0b74ad913b035b8c4cea637822ad6105448e804e38c2f8de4331d4abf8544235545052
+R = 06f9fafdf5c48d64413ddcc709fe1617f5f8f8f7c9bf34b8699ca36560c360fd0ac696ff631f2d6fff3956d6af81c28b835a42211f5b3ebf33ad5c43c69b2d519c0ad7331cb494e
+S = 15453e11e5f2574f04173a2b332fb27fc51c390838fda75b59a16bf6ea9c8b019ed94936adf33a864099139b241e993de913b2d43f3816a1d000f9e3a94721ae56e8a53521318ca
+Result = F (2 - R changed)
+
+Msg = 711d0a0fefb1ee93936b0a5b3914e71dccf6650ebdbdd2b225fe2b19ba3bc22dcc781688bcf96f1820b4f7df39dadd0c25dc568a999b2a0d6ef51dba64337060dc2926386d129e53d933b7a768be2945bae94305f02e23461e92a428640bd8dfb7b333b5919b9450a61aad05578ead36bccbdc7442d796722e824fd8de32b7a6
+Qx = 2f0cb609ea855eacef2ecd191811f8b6a988c54de11ded6547d2c1456b45b9aa673b757d89e75c63da113fb761decb9dc11587cc85654553512b83095884fe7624c6118b27866e8
+Qy = 4060024002e9a671cc6048dbabf2c5c3372c672f772e8988c2875c0aa9a2c02ac292f0e283972fc22a36a628b197838faf133218c5c432e0790a6f207cab78745eb36a4e53f52de
+R = 353eeea4a09bd3aefa455662197a1886637bf55936592f7c2f62e7c9e756c7424bcd17aec774aea46caf13408dba4b1cb4682dc5a858b68875afff6b060b7a8907316585edd5dce
+S = 3ead9fc822afff273185c335b7d2800a4a0c839aca33f76d24fc6e542785f91d3fd905922e7e19b01a01d3b1f36297be25646ff40193ebe8b5d4ff4117fe2827d7292d533c9ea70
+Result = P (0 )
+
+Msg = 2b6cfcbdc804c1106a7a0e2a6cf4b18825cd5c93de00b2f5b8b452e81c8611c8c7c8a1dacf78b07572a9162fc922ea02c2524460cb9250982a5b9844771d669a277f557ba640a5482bf40d60fd8cd9bb52445dffe77ebc1bf2c8c17f0dae5e7ab8cb87f9a8a8430dce4f8c3e4f91b77b2d1d8e5555bae6ab84ea22b57f3a1ecb
+Qx = 23b179938bff4f6ad62741d27a028c776182e05afaf810610f17b25f11fe80fcab1142e87a7bd21d41b6916e361cd0ecad2a53f84df50c0dc608af2a90501e6d311bc47939ca73f
+Qy = 1eeadfd2fa53a1ad51a52b42e03bec28456722a55cf163746e8a884476cfc1f9e04ec4fbda25d69cf7b0d301f1384649a5cfdb2181e6526ede9ef48f09810eeec6f1f3bd65aea10
+R = 20a3377ab20ecd9599fc8a2d8a04721f58ca94267b0802fdb8b86e572a30067a388ed356e2226792d7a2e7e1be9aa9f4f1895bff2d7420f9981bebec6b99ac09e4941dd7233602c
+S = 0c20ddcde703dbcd61beaf19f4f46f8cfae7bb5a8c83384e9acded50af50d26d491e3cb8c3722c7181ca11b2d854dbda39be19bf5286f5028173c9d1c0939af38cb17921d7fa8d7
+Result = P (0 )
+
+Msg = 0b876efed1df838407653180f79e0b79b1b8ee18fc4cf163c8825e5e4b8924e2c88963e3d3048d11c1eaa6f31d6dec87a98c3f4a3aa6c135b9db8361fb9f795df77be21aeeed1d04dd04625d0cdf0b392702a54556579abc9e6fc65e0d0f466a65e94df4f35c9f0e9a7100fb9009e7357ee9953b26d9e6f5e84c9a16938ce262
+Qx = 3f19be2ae145e72cebddb7bf8ba7bc94bd72c671da1adc7007b5fed078be42206fe5f82ce70d7343f8c4f4251a704d3903d956d8f54623ff3e163d1de4e0090a1adcb095f011582
+Qy = 0a7912b0223ad5eaaf83ed73a9a03ce53ce07e6d889e48d435b41ee7ec2169ac37a81d1ffaa97efd64baa1356e95a1ae9b7918b35caf10e804510bbeadbd012b061f3f186dbbe14
+R = 17d1ca30ee6ef07c7d274e5520a94cbe10d5dd34d3a3e4bbd44ed822db4c2ed4b969595bb35d83ef522cf05eb153974ed501cec11957e42adf6633c13049151435d7b229ed942ff
+S = 156835fba7c3c258b671e2f6af557c3f7f971ef932f963751016998919c6a9b3b5f603756651dafc14b81ed954b534bdf68fcbc6d71b5835cc084fbfbdd9e5f804a825dcdb89f87
+Result = F (1 - Message changed)
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/main.c
new file mode 100644
index 000000000..886b8a357
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/main.c
@@ -0,0 +1,317 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Verify_IT/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to configure and use PKA through
+  *          the STM32WBxx HAL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+PKA_HandleTypeDef hpka;
+
+/* USER CODE BEGIN PV */
+PKA_ECDSAVerifInTypeDef in = {0};
+__IO uint32_t operationComplete = 0;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_PKA_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* Configure LED2 */
+  BSP_LED_Init(LED2);
+  
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_PKA_Init();
+  /* USER CODE BEGIN 2 */
+  /* Set input parameters */
+  in.primeOrderSize =  prime256v1_Order_len;
+  in.modulusSize =     prime256v1_Prime_len;
+  in.coefSign =        prime256v1_A_sign;
+  in.coef =            prime256v1_absA;
+  in.modulus =         prime256v1_Prime;
+  in.basePointX =      prime256v1_GeneratorX;
+  in.basePointY =      prime256v1_GeneratorY;
+  in.primeOrder =      prime256v1_Order;
+  
+  in.pPubKeyCurvePtX = SigVer_Qx;
+  in.pPubKeyCurvePtY = SigVer_Qy;
+  in.RSign =           SigVer_R;
+  in.SSign =           SigVer_S;
+  in.hash =            SigVer_Hash_Msg;
+  
+  /* Launch the verification */
+  if(HAL_PKA_ECDSAVerif_IT(&hpka, &in) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  
+  /* Wait until the interrupt is triggered */
+  while(operationComplete == 0);
+  operationComplete = 0;
+
+  /* Compare to expected result */
+  if(HAL_PKA_ECDSAVerif_IsValidSignature(&hpka) != SigVer_Result)
+  {
+    Error_Handler();
+  }
+
+  /* Simulate a wrong hash message verification */
+  in.hash = SigVer_Hash_Msg_False;
+  
+  /* Launch the verification */
+  if(HAL_PKA_ECDSAVerif_IT(&hpka, &in) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  
+  /* Wait until the interrupt is triggered */
+  while(operationComplete == 0);
+
+  /* Compare to expected result ( must be different from SigVer_Result as the hash has been altered! ) */
+  if(HAL_PKA_ECDSAVerif_IsValidSignature(&hpka) == SigVer_Result)
+  {
+    Error_Handler();
+  }
+
+  /* Deinitialize the PKA */
+  if(HAL_PKA_DeInit(&hpka) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  
+  /* Success */
+  operationComplete = 3;
+  BSP_LED_On(LED2);
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief PKA Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_PKA_Init(void)
+{
+
+  /* USER CODE BEGIN PKA_Init 0 */
+
+  /* USER CODE END PKA_Init 0 */
+
+  /* USER CODE BEGIN PKA_Init 1 */
+
+  /* USER CODE END PKA_Init 1 */
+  hpka.Instance = PKA;
+  if (HAL_PKA_Init(&hpka) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN PKA_Init 2 */
+
+  /* USER CODE END PKA_Init 2 */
+
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Process completed callback.
+  * @param  hpka PKA handle
+  * @retval None
+  */
+void HAL_PKA_OperationCpltCallback(PKA_HandleTypeDef *hpka)
+{
+  operationComplete = 1;
+}
+
+/**
+  * @brief  Error callback.
+  * @param  hpka PKA handle
+  * @retval None
+  */
+void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka)
+{
+  Error_Handler();
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  operationComplete = 2;
+  while (1)
+  {
+    /* Error if LED2 is slowly blinking (1 sec. period) */
+    BSP_LED_Toggle(LED2); 
+    HAL_Delay(1000);   
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/prime256v1.c b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/prime256v1.c
new file mode 100644
index 000000000..90f329ea7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/prime256v1.c
@@ -0,0 +1,96 @@
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Verify_IT/Src/prime256v1.c
+  * @author  MCD Application Team
+  * @brief   This file contains reference buffers containing the description of
+  *          nist P-256 (ECDSA-256) published by NIST in Federal Information 
+  *          Processing Standards Publication FIPS PUB 186-4.
+  *          Additionnal buffer are provided to be used with PKA like abs(A)
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+  
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+const uint8_t prime256v1_Prime[] = {
+/*0x00,*/ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff
+};
+const uint32_t prime256v1_Prime_len = 32;
+
+const uint8_t prime256v1_A[] = {
+/*0x00,*/ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xfc
+};
+/* PKA operation need abs(a) */
+const uint8_t prime256v1_absA[] = {
+/*0x00,*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x03
+};
+const uint32_t prime256v1_A_len = 32;
+
+/* PKA operation need the sign of A */
+const uint32_t prime256v1_A_sign = 1;
+
+const uint8_t prime256v1_B[] = {
+    0x5a, 0xc6, 0x35, 0xd8, 0xaa, 0x3a, 0x93, 0xe7, 0xb3, 0xeb, 0xbd, 0x55, 0x76, 0x98, 0x86,
+    0xbc, 0x65, 0x1d, 0x06, 0xb0, 0xcc, 0x53, 0xb0, 0xf6, 0x3b, 0xce, 0x3c, 0x3e, 0x27, 0xd2,
+    0x60, 0x4b
+};
+const uint32_t prime256v1_B_len = 32;
+
+const uint8_t prime256v1_Generator[] = {
+    0x04, 0x6b, 0x17, 0xd1, 0xf2, 0xe1, 0x2c, 0x42, 0x47, 0xf8, 0xbc, 0xe6, 0xe5, 0x63, 0xa4,
+    0x40, 0xf2, 0x77, 0x03, 0x7d, 0x81, 0x2d, 0xeb, 0x33, 0xa0, 0xf4, 0xa1, 0x39, 0x45, 0xd8,
+    0x98, 0xc2, 0x96, 0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a,
+    0x7c, 0x0f, 0x9e, 0x16, 0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40,
+    0x68, 0x37, 0xbf, 0x51, 0xf5
+};
+const uint32_t prime256v1_Generator_len = 65;
+
+/* This buffer is extracted from prime256v1_Generator as its first part */
+const uint8_t prime256v1_GeneratorX[] = {
+    0x6b, 0x17, 0xd1, 0xf2, 0xe1, 0x2c, 0x42, 0x47, 0xf8, 0xbc, 0xe6, 0xe5, 0x63, 0xa4, 0x40, 
+    0xf2, 0x77, 0x03, 0x7d, 0x81, 0x2d, 0xeb, 0x33, 0xa0, 0xf4, 0xa1, 0x39, 0x45, 0xd8, 0x98, 
+    0xc2, 0x96
+};
+const uint32_t prime256v1_GeneratorX_len = 32;
+
+/* This buffer is extracted from prime256v1_Generator as its second part */    
+const uint8_t prime256v1_GeneratorY[] = {
+    0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a, 0x7c, 0x0f, 0x9e, 
+    0x16, 0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40, 0x68, 0x37, 0xbf, 
+    0x51, 0xf5
+};
+const uint32_t prime256v1_GeneratorY_len = 32;
+
+const uint8_t prime256v1_Order[] = {
+/*0x00,*/ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xbc, 0xe6, 0xfa, 0xad, 0xa7, 0x17, 0x9e, 0x84, 0xf3, 0xb9, 0xca, 0xc2, 0xfc,
+    0x63, 0x25, 0x51
+};
+const uint32_t prime256v1_Order_len = 32;
+
+const uint32_t prime256v1_Cofactor = 1; /* (0x1) */
+
+const uint8_t prime256v1_Seed[] = {
+    0xc4, 0x9d, 0x36, 0x08, 0x86, 0xe7, 0x04, 0x93, 0x6a, 0x66, 0x78, 0xe1, 0x13, 0x9d, 0x26,
+    0xb7, 0x81, 0x9f, 0x7e, 0x90
+};
+const uint32_t prime256v1_Seed_len = 20;
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..b5801c871
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,131 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Verify_IT/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief PKA MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hpka: PKA handle pointer
+* @retval None
+*/
+void HAL_PKA_MspInit(PKA_HandleTypeDef* hpka)
+{
+  if(hpka->Instance==PKA)
+  {
+  /* USER CODE BEGIN PKA_MspInit 0 */
+
+  /* USER CODE END PKA_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_PKA_CLK_ENABLE();
+  /* USER CODE BEGIN PKA_MspInit 1 */
+  /* Enable the PKA interrupt */
+  HAL_NVIC_SetPriority(PKA_IRQn, 0x0F, 0);
+  HAL_NVIC_EnableIRQ(PKA_IRQn);
+  /* USER CODE END PKA_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief PKA MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hpka: PKA handle pointer
+* @retval None
+*/
+void HAL_PKA_MspDeInit(PKA_HandleTypeDef* hpka)
+{
+  if(hpka->Instance==PKA)
+  {
+  /* USER CODE BEGIN PKA_MspDeInit 0 */
+  /* Enable PKA reset state */
+  __HAL_RCC_PKA_FORCE_RESET();
+  /* Release PKA from reset state */
+  __HAL_RCC_PKA_RELEASE_RESET(); 
+  /* USER CODE END PKA_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_PKA_CLK_DISABLE();
+  /* USER CODE BEGIN PKA_MspDeInit 1 */
+  /* Disable the PKA interrupt */
+  HAL_NVIC_DisableIRQ(PKA_IRQn);
+  /* USER CODE END PKA_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..d96ddbe9a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/stm32wbxx_it.c
@@ -0,0 +1,215 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Verify_IT/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+extern PKA_HandleTypeDef hpka;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles PKA Handler.
+  * @param  None
+  * @retval None
+  */
+void PKA_IRQHandler(void)
+{
+  HAL_PKA_IRQHandler(&hpka);
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/readme.txt b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/readme.txt
new file mode 100644
index 000000000..b7afb4f8c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PKA/PKA_ECDSA_Verify_IT/readme.txt
@@ -0,0 +1,91 @@
+/**
+  @page PKA_ECDSA_Verify_IT ECDSA verification example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Verify_IT/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the ECDSA verification example
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to determine if a given signature is valid regarding the Elliptic curve digital signature algorithm
+(ECDSA) in interrupt mode.
+
+For this example, a test vector have been extracted from National Institute of Standards and Technology (NIST)
+ - Cryptographic Algorithm Validation Program (CAVP) in order to demonstrate the usage of the hal.
+This reference files can be found under:
+"http://csrc.nist.gov/groups/STM/cavp/documents/dss/186-3ecdsatestvectors.zip (ZIP SigGen.rsp)"
+
+This test vector has been choosen to demonstrate the behavior in a case where the input signature
+is valid. A second input is provided where one element of the hash message has been modified to 
+demonstrate the behavior in a case where the signature is invalid. Their definitions are included 
+in SigVer.c. You can refer to this file for more informations.
+
+The selected curve for this example is P-256 (ECDSA-256) published by NIST in 
+Federal Information Processing Standards Publication FIPS PUB 186-4. The description
+of this curve is present in file Src/prime256v1.c.
+
+In this example, the PKA interrupt is triggered at the end of the operation. The interrupt handler then
+call the pka callback where a global variable is used to notify the main function.
+
+In case of success, the LED2 (GREEN) is ON.
+In case of any error, the LED2 (GREEN) is toggling slowly.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+PKA, PKA_ECDSA_Verify_IT, Security, NIST, CAVP, ECDSA verification
+
+@par Directory contents 
+  
+  - PKA/PKA_ECDSA_Verify_IT/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - PKA/PKA_ECDSA_Verify_IT/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - PKA/PKA_ECDSA_Verify_IT/Inc/main.h                  Header for main.c module
+  - PKA/PKA_ECDSA_Verify_IT/Src/stm32wbxx_it.c          Interrupt handlers
+  - PKA/PKA_ECDSA_Verify_IT/Src/main.c                  Main program
+  - PKA/PKA_ECDSA_Verify_IT/Src/stm32wbxx_hal_msp.c     HAL MSP module 
+  - PKA/PKA_ECDSA_Verify_IT/Src/system_stm32wbxx.c      STM32WBxx system source file
+  - PKA/PKA_ECDSA_Verify_IT/Src/prime256v1.c            Description of P-256 (ECDSA-256)
+  - PKA/PKA_ECDSA_Verify_IT/Inc/prime256v1.h            Header for prime256v1.c
+  - PKA/PKA_ECDSA_Verify_IT/Src/SigVer.c                Reflect the content of the test vector from SigVer.rsp
+  - PKA/PKA_ECDSA_Verify_IT/Src/SigVer.rsp              Extract from NIST CAVP
+  - PKA/PKA_ECDSA_Verify_IT/Inc/SigVer.h                Header of SigVer.c
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35xx devices.
+  
+  - This example has been tested with an STMicroelectronics NUCLEO-WB35CE
+    board and can be easily tailored to any other supported device 
+    and development board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following:
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+ 
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
+ 
\ No newline at end of file
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/.extSettings b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/PWR_LPRUN.ewd b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/PWR_LPRUN.ewd
new file mode 100644
index 000000000..1741baab6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/PWR_LPRUN.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		PWR_LPRUN
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/PWR_LPRUN.ewp b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/PWR_LPRUN.ewp
new file mode 100644
index 000000000..d0bd0d00f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/PWR_LPRUN.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    PWR_LPRUN
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/Project.eww
new file mode 100644
index 000000000..ebae7ea93
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\PWR_LPRUN.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Inc/main.h
new file mode 100644
index 000000000..296848c65
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_LPRUN/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..19d12a61f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..92e7c7e0b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_LPRUN/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/MDK-ARM/PWR_LPRUN.uvoptx b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/MDK-ARM/PWR_LPRUN.uvoptx
new file mode 100644
index 000000000..5405580fc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/MDK-ARM/PWR_LPRUN.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    PWR_LPRUN
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/MDK-ARM/PWR_LPRUN.uvprojx b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/MDK-ARM/PWR_LPRUN.uvprojx
new file mode 100644
index 000000000..b66e0c285
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/MDK-ARM/PWR_LPRUN.uvprojx
@@ -0,0 +1,541 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      PWR_LPRUN
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          PWR_LPRUN\
+          PWR_LPRUN
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/PWR_LPRUN.ioc b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/PWR_LPRUN.ioc
new file mode 100644
index 000000000..41f5dee3d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/PWR_LPRUN.ioc
@@ -0,0 +1,106 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=PWR_LPRUN.ioc
+ProjectManager.ProjectName=PWR_LPRUN
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..e167311a9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/.project
new file mode 100644
index 000000000..e6c029f09
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	PWR_LPRUN
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			PWR_LPRUN.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/PWR_LPRUN.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Src/main.c
new file mode 100644
index 000000000..1621c7daa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Src/main.c
@@ -0,0 +1,294 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_LPRUN/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use STM32WBxx PWR HAL API to enter
+  *          and exit the Low Power Run mode.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define LED_TOGGLE_DELAY         100
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+static uint32_t TimingDelay;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Decrease(void);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+  /* Configure LED2 */
+  BSP_LED_Init(LED2);
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+
+  /* Re-init LED2 to toggle during Run mode */
+  BSP_LED_Init(LED2);
+
+  /* User push-button (SW1) will be used to exit from Low Power Run mode */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_GPIO);
+
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    /* Insert 5 seconds delay. LED2 is toggled in systick callback */
+    HAL_Delay(5000);
+    /* Reduce the System clock */
+    SystemClock_Decrease();
+
+    /* Set regulator voltage to scale 2 */
+    HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+    /* De-init LED2 */
+    BSP_LED_DeInit(LED2);
+
+    /* Enter LP RUN Mode */
+    HAL_PWREx_EnableLowPowerRunMode();
+
+    /* Wait until User push-button (SW1) pressed */
+    while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_RESET)
+    {
+    }
+
+    /* Wait until User push-button (SW1) released */
+    while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_SET)
+    {
+    }
+
+    /* Disable low power run mode and reset the clock to initialization configuration */
+    HAL_PWREx_DisableLowPowerRunMode();
+
+    /* Re-init LED2 to toggle during Run mode */
+    BSP_LED_Init(LED2);
+
+    /* Configure the system clock for the RUN mode */
+    SystemClock_Config();
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  System Clock Speed decrease
+  *         The system Clock source is shifted from HSI to MSI
+  *         while at the same time, MSI range is set to RCC_MSIRANGE_5
+  *         to go down to 2MHz
+  * @param  None
+  * @retval None
+  */
+void SystemClock_Decrease(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+
+  /* Select MSI as system clock source */
+  /* Note: Keep AHB and APB prescaler settings from previous structure initialization */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+  {
+    /* Initialization Error */
+    while (1);
+  }
+
+  /* Disable PLL to reduce power consumption since MSI is used from that point */
+  /* Change MSI frequency */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_5;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    /* Initialization Error */
+    while (1);
+  }
+}
+
+/**
+  * @brief SYSTICK callback
+  * @param None
+  * @retval None
+  */
+void HAL_SYSTICK_Callback(void)
+{
+  if (TimingDelay != 0)
+  {
+    TimingDelay--;
+  }
+  else
+  {
+    /* Toggle LED2 */
+    BSP_LED_Toggle(LED2);
+    TimingDelay = LED_TOGGLE_DELAY;
+  }
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  /* Turn on the LED2 */
+  BSP_LED_On(LED2);
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..9a8c656b2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_LPRUN/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..de8a4bb6e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Src/stm32wbxx_it.c
@@ -0,0 +1,207 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_LPRUN/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+  HAL_SYSTICK_IRQHandler();
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/readme.txt b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/readme.txt
new file mode 100644
index 000000000..1f68b3a51
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPRUN/readme.txt
@@ -0,0 +1,89 @@
+/**
+  @page PWR_LPRUN Low Power Run Mode Example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    PWR/PWR_LPRUN/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the Low Power Run Mode example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+ 
+How to enter and exit the Low-power run mode.
+
+In the associated software, the system clock is set to 64 MHz.
+The SysTick is programmed to generate an interrupt each 1 ms.
+
+The User push-button (SW1) can be pressed at any time to exit from Low Power Run. 
+The software then comes back in Run mode for 5 sec. before automatically 
+entering LP Run mode again. 
+
+LED2 is used to monitor the system state as follows:
+ - LED2 toggling : system in Run mode
+ - LED2 off : system in LP Run mode
+ - LED2 on : system in error
+
+These steps are repeated in an infinite loop.
+
+@note To measure the current consumption in LP SLEEP mode, remove JP2 jumper 
+      and connect an amperemeter to JP2 to measure IDD current.
+
+@note This example can not be used in DEBUG mode due to the fact 
+      that the Cortex-M4 core is no longer clocked during low power mode 
+      so debugging features are disabled.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+Power, PWR, Low Power, Run mode, Interrupt, EXTI, Wakeup, External reset
+
+@par Directory contents 
+
+  - PWR/PWR_LPRUN/Inc/stm32wbxx_conf.h         HAL Configuration file
+  - PWR/PWR_LPRUN/Inc/stm32wbxx_it.h           Header for stm32wbxx_it.c
+  - PWR/PWR_LPRUN/Inc/main.h                         Header file for main.c
+  - PWR/PWR_LPRUN/Src/system_stm32wbxx.c       STM32WBxx system clock configuration file
+  - PWR/PWR_LPRUN/Src/stm32wbxx_it.c           Interrupt handlers
+  - PWR/PWR_LPRUN/Src/stm32wbxx_hal_msp.c     HAL MSP module
+  - PWR/PWR_LPRUN/Src/main.c                   Main program
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WBxx devices
+    
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE
+    board and can be easily tailored to any other supported device
+    and development board.
+
+  - NUCLEO-WB35CE set-up:
+    - LED2 connected to PB.00 pin
+    - Use the User push-button (SW1) connected to pin PA.00.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/.extSettings b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/PWR_LPSLEEP.ewd b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/PWR_LPSLEEP.ewd
new file mode 100644
index 000000000..dda7491eb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/PWR_LPSLEEP.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		PWR_LPSLEEP
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/PWR_LPSLEEP.ewp b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/PWR_LPSLEEP.ewp
new file mode 100644
index 000000000..79522b9dc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/PWR_LPSLEEP.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    PWR_LPSLEEP
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/Project.eww
new file mode 100644
index 000000000..5c43367e2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\PWR_LPSLEEP.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Inc/main.h
new file mode 100644
index 000000000..851c4dc5b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Inc/main.h
@@ -0,0 +1,73 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_LPSLEEP/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..19d12a61f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..0aae36697
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_LPSLEEP/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void EXTI0_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/MDK-ARM/PWR_LPSLEEP.uvoptx b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/MDK-ARM/PWR_LPSLEEP.uvoptx
new file mode 100644
index 000000000..d2edc46e3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/MDK-ARM/PWR_LPSLEEP.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    PWR_LPSLEEP
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/MDK-ARM/PWR_LPSLEEP.uvprojx b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/MDK-ARM/PWR_LPSLEEP.uvprojx
new file mode 100644
index 000000000..677c60b8d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/MDK-ARM/PWR_LPSLEEP.uvprojx
@@ -0,0 +1,541 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      PWR_LPSLEEP
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          PWR_LPSLEEP\
+          PWR_LPSLEEP
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/PWR_LPSLEEP.ioc b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/PWR_LPSLEEP.ioc
new file mode 100644
index 000000000..b3363ba55
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/PWR_LPSLEEP.ioc
@@ -0,0 +1,106 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=PWR_LPSLEEP.ioc
+ProjectManager.ProjectName=PWR_LPSLEEP
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..a0f37db09
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/.project
new file mode 100644
index 000000000..2088fc516
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	PWR_LPSLEEP
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			PWR_LPSLEEP.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/PWR_LPSLEEP.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Src/main.c
new file mode 100644
index 000000000..dbaceb44e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Src/main.c
@@ -0,0 +1,304 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_LPSLEEP/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use STM32WBxx PWR HAL API to enter
+  *          and exit the Low Power Sleep mode.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define LED_TOGGLE_DELAY         100
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+static uint32_t TimingDelay;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Decrease(void);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+
+  /* Configure LED2 and LED3 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+
+  /* User push-button (SW1) (line 0) will be used to wakeup the system from STOP mode */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+
+  /* Enable Flash power down mode during Sleep mode     */
+  /* (uncomment this line if power consumption figures  */
+  /*  must be measured with Flash still on in Low Power */
+  /*  Sleep mode)                                       */
+  /* Note: On STM32WB, flash power down mode is effective if CPU2 is aligned  */
+  /*       with CPU1 low power state.                                         */
+  /*       RF stack should manage flash power down mode for CPU2.             */
+  /*       In case of RF stack not started, flash power down mode for CPU2    */
+  /*       can be set using functions "LL_C2_PWR_SetFlashPowerModeSleep()"    */
+  /*       and "LL_C2_PWR_SetFlashPowerModeRun()".                            */
+  HAL_PWREx_EnableFlashPowerDown(PWR_FLASHPD_LPSLEEP);
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    /* Insert 5 seconds delay */
+    HAL_Delay(5000);  
+
+    /* Reduce the System clock to below 2 MHz */
+    SystemClock_Decrease();
+
+    /* Suspend Tick increment to prevent wakeup by Systick interrupt.         */
+    /* Otherwise the Systick interrupt will wake up the device within 1ms     */
+    /* (HAL time base).                                                       */
+    HAL_SuspendTick();
+
+    /* De-init LED2 */
+    BSP_LED_DeInit(LED2);
+
+    /* Enter Sleep Mode, wake up is done once User push-button (SW1) is pressed */
+    HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+
+    /* ... Low-power SLEEP mode ... */
+
+    /* System is Low Power Run mode when exiting Low Power Sleep mode,
+       disable low power run mode and reset the clock to initialization configuration */ 
+    HAL_PWREx_DisableLowPowerRunMode();
+
+    /* Configure the system clock for the RUN mode */
+    SystemClock_Config();
+
+    /* Re-init LED2 to toggle during Run mode */
+    BSP_LED_Init(LED2);
+
+    /* Resume Tick interrupt if disabled prior to Low Power Sleep mode entry */
+    HAL_ResumeTick();
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  System Clock Speed decrease
+  *         The system Clock source is shifted from HSI to MSI
+  *         while at the same time, MSI range is set to RCC_MSIRANGE_5
+  *         to go down to 2MHz     
+  * @param  None
+  * @retval None
+  */
+void SystemClock_Decrease(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+
+  /* Select MSI as system clock source */
+  /* Note: Keep AHB and APB prescaler settings from previous structure initialization */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; 
+  if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+  {
+    /* Initialization Error */
+    Error_Handler();
+  }
+  
+  /* Disable PLL to reduce power consumption since MSI is used from that point */
+  /* Change MSI frequency */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_5;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF;
+  if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    /* Initialization Error */
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief SYSTICK callback
+  * @param None
+  * @retval None
+  */
+void HAL_SYSTICK_Callback(void)
+{
+  if (TimingDelay != 0)
+  {
+    TimingDelay--;
+  }
+  else
+  {
+    /* Toggle LED2 */
+    BSP_LED_Toggle(LED2);
+    TimingDelay = LED_TOGGLE_DELAY;
+  }
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  
+  /* Suspend tick */
+  HAL_SuspendTick();
+
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  while(1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+   /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..02ae5b10a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,83 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_LPSLEEPS/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @version $VERSION$
+  * @date    $DATE$
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..359957813
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Src/stm32wbxx_it.c
@@ -0,0 +1,216 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_LPSLEEP/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+  HAL_SYSTICK_IRQHandler();
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles external line 0 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/readme.txt b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/readme.txt
new file mode 100644
index 000000000..a1eb2b89d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_LPSLEEP/readme.txt
@@ -0,0 +1,99 @@
+/**
+  @page PWR_LPSLEEP Low Power sleep Mode Example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    PWR/PWR_LPSLEEP/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the Low Power Sleep Mode example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to enter the Low-power sleep mode and wake up from this mode by using 
+an interrupt.
+
+In the associated software, the system clock is set to 64 MHz.
+An EXTI line is connected to the user button thru PA.00 and configured 
+to generate an interrupt on falling edge upon key press.
+ 
+The SysTick is programmed to generate an interrupt each 1 ms and in the SysTick 
+interrupt handler, LED2 is toggled in order to indicate whether the MCU is in LP SLEEP mode 
+or RUN mode.
+
+5 seconds after start-up, the system automatically enters LP SLEEP mode and 
+LED2 stops toggling.
+The User push-button (SW1) can be pressed at any time to wake-up the system. 
+The software then comes back in RUN mode for 5 sec. before automatically entering LP SLEEP mode again. 
+
+Two leds LED2 and LED3 are used to monitor the system state as following:
+ - LED3 ON: configuration failed (system will go to an infinite loop)
+ - LED2 toggling: system in RUN mode
+ - LED2 off : system in LP SLEEP mode
+
+These steps are repeated in an infinite loop.
+
+@note To measure MCU current consumption on board STM32WB Nucleo,
+      board configuration must be applied:
+      - remove all jumpers on connector JP5 to avoid leakages between ST-Link circuitry and STM32WB device.
+      - remove jumper JP2 and connect an amperemeter to measure current between the 2 connectors of JP2.
+      
+@note This example can not be used in DEBUG mode due to the fact 
+      that the Cortex-M4 core is no longer clocked during low power mode 
+      so debugging features are disabled.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+      
+@par Keywords
+
+Power, PWR, Low Power, Sleep mode, Interrupt, Wakeup, External reset
+
+@par Directory contents 
+
+  - PWR/PWR_LPSLEEP/Inc/stm32wbxx_conf.h         HAL Configuration file
+  - PWR/PWR_LPSLEEP/Inc/stm32wbxx_it.h           Header for stm32wbxx_it.c
+  - PWR/PWR_LPSLEEP/Inc/main.h                         Header file for main.c
+  - PWR/PWR_LPSLEEP/Src/system_stm32wbxx.c       STM32WBxx system clock configuration file
+  - PWR/PWR_LPSLEEP/Src/stm32wbxx_it.c           Interrupt handlers
+  - PWR/PWR_LPSLEEP/Src/stm32wbxx_hal_msp.c      HAL MSP module
+  - PWR/PWR_LPSLEEP/Src/main.c                         Main program
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WBxx devices
+      
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE
+    board and can be easily tailored to any other supported device 
+    and development board.
+
+  - NUCLEO-WB35CE set-up:
+    - Use LED2 and LED3 connected respectively to PB.00 and PB.01 pins
+    - Use the User push-button (SW1) connected to pin PA.00 (External line 0)
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/.extSettings b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/PWR_PVD.ewd b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/PWR_PVD.ewd
new file mode 100644
index 000000000..c113ae2f6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/PWR_PVD.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		PWR_PVD
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/PWR_PVD.ewp b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/PWR_PVD.ewp
new file mode 100644
index 000000000..e6a9ad0e8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/PWR_PVD.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    PWR_PVD
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/Project.eww
new file mode 100644
index 000000000..37719c791
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\PWR_PVD.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Inc/main.h
new file mode 100644
index 000000000..c9340ea66
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_PVD/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+  
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..19d12a61f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..43e0a9357
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_PVD/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void PVD_PVM_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/MDK-ARM/PWR_PVD.uvoptx b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/MDK-ARM/PWR_PVD.uvoptx
new file mode 100644
index 000000000..d2705f286
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/MDK-ARM/PWR_PVD.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    PWR_PVD
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U001D00263137510133333639 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/MDK-ARM/PWR_PVD.uvprojx b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/MDK-ARM/PWR_PVD.uvprojx
new file mode 100644
index 000000000..507c81646
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/MDK-ARM/PWR_PVD.uvprojx
@@ -0,0 +1,542 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      PWR_PVD
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          PWR_PVD\
+          PWR_PVD
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/PWR_PVD.ioc b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/PWR_PVD.ioc
new file mode 100644
index 000000000..22c0a5f3f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/PWR_PVD.ioc
@@ -0,0 +1,106 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=PWR_PVD.ioc
+ProjectManager.ProjectName=PWR_PVD
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..8b09de27b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/.cproject
@@ -0,0 +1,171 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/.project
new file mode 100644
index 000000000..9f0f9e539
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	PWR_PVD
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			PWR_PVD.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/PWR_PVD.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Src/main.c
new file mode 100644
index 000000000..ee945a1aa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Src/main.c
@@ -0,0 +1,249 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_PVD/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use STM32WBxx PWR HAL API to manage the
+  *          Programmable Voltage Detector (PVD).
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+PWR_PVDTypeDef sConfigPVD;
+__IO uint32_t uwToggleOn = 1;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+static void PVD_Config(void);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+   /* Configure LEDs */
+   BSP_LED_Init(LED2);
+
+  /* Configure the PVD */
+  PVD_Config();
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    /* LED2 toggles when the voltage is above the target threshold */
+    if (uwToggleOn)
+    {
+      BSP_LED_Toggle(LED2);
+      HAL_Delay(200);
+    }
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Configures the PVD resources.
+  * @param  None
+  * @retval None
+  */
+static void PVD_Config(void)
+{
+  /*##-1- Enable Power Clock #################################################*/
+  /* Note: On this STM32 serie, Power Clock is enabled automatically */
+  
+  /*##-2- Configure the NVIC for PVD #########################################*/
+  HAL_NVIC_SetPriority(PVD_PVM_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(PVD_PVM_IRQn);
+
+  /* Configure the PVD Level to 3 and generate an interrupt on rising and falling
+     edges(PVD detection level set to 2.5V, refer to the electrical characteristics
+     of you device datasheet for more details) */
+  sConfigPVD.PVDLevel = PWR_PVDLEVEL_3;
+  sConfigPVD.Mode = PWR_PVD_MODE_IT_RISING_FALLING;
+  HAL_PWR_ConfigPVD(&sConfigPVD);
+
+  /* Enable the PVD Output */
+  HAL_PWR_EnablePVD();
+}
+
+
+/**
+  * @brief  PWR PVD interrupt callback
+  * @param  none 
+  * @retval none
+  */
+void HAL_PWR_PVDCallback(void)
+{
+  /* Set LED2 on */  
+  BSP_LED_On(LED2); 
+  /* update uwToggleOn global variable so that LED2 blinks when the
+     voltage is above the target threshold */
+  uwToggleOn = (uwToggleOn+1) % 2;
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  while(1) 
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..c9282fd07
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_PVD/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..a4464823f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Src/stm32wbxx_it.c
@@ -0,0 +1,215 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_PVD/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+  HAL_SYSTICK_IRQHandler();
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles the PVD Output interrupt request.
+  * @param  None
+  * @retval None
+  */
+void PVD_PVM_IRQHandler(void)
+{
+  HAL_PWREx_PVD_PVM_IRQHandler();
+}
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/readme.txt b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/readme.txt
new file mode 100644
index 000000000..ac1e6686e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_PVD/readme.txt
@@ -0,0 +1,79 @@
+/**
+  @page PWR_PVD PWR Programmable Voltage Detector (PVD) example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    PWR/PWR_PVD/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the PWR Programmable Voltage Detector (PVD) example
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+How to configure the programmable voltage detector by using an external interrupt 
+line. External DC supply must be used to supply Vdd.
+
+In this example, EXTI line 0 is configured to generate an interrupt on each rising
+or falling edge of the PVD output signal (which indicates that the Vdd voltage is
+moving below or above the PVD threshold). As long as the voltage is above the 
+target threshold (2.5V), LED2 is blinking with a 200 ms-period; when the voltage drops
+below the threshold, LED2 stops blinking and remains constantly on (or appears
+to be turned off if the voltage is getting really low); when the voltage moves back
+above the target threshold, LED2 starts blinking again.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+Power, PWR, EXTI, PVD, Interrupt, Wakeup, External reset
+
+@par Directory contents 
+
+  - PWR/PWR_PVD/Inc/stm32wbxx_hal_conf.h     HAL Configuration file
+  - PWR/PWR_PVD/Inc/stm32wbxx_it.h           Header for stm32wbxx_it.c
+  - PWR/PWR_PVD/Inc/main.h                         Header file for main.c
+  - PWR/PWR_PVD/Src/system_stm32wbxx.c       STM32WBxx system clock configuration file
+  - PWR/PWR_PVD/Src/stm32wbxx_it.c           Interrupt handlers
+  - PWR/PWR_PVD/Src/stm32wbxx_hal_msp.c      HAL MSP module
+  - PWR/PWR_PVD/Src/main.c                         Main program
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35xx devices
+    
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE
+    board and can be easily tailored to any other supported device
+    and development board.
+
+  - NUCLEO-WB35CE Set-up :
+    - Remove jumper on JP2 connector.
+    - Provide power supply (DC voltage) to JP2 connector, pin "VDD".
+    - LED2 (GREEN) connected to PB.00 pin indicates the behavior of
+      the test software as explained above.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/.extSettings b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/PWR_STANDBY_RTC.ewd b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/PWR_STANDBY_RTC.ewd
new file mode 100644
index 000000000..6ba099ba4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/PWR_STANDBY_RTC.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		PWR_STANDBY_RTC
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/PWR_STANDBY_RTC.ewp b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/PWR_STANDBY_RTC.ewp
new file mode 100644
index 000000000..c012f0ff5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/PWR_STANDBY_RTC.ewp
@@ -0,0 +1,1125 @@
+
+
+  3
+  
+    PWR_STANDBY_RTC
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/Project.eww
new file mode 100644
index 000000000..d12cfe8c2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\PWR_STANDBY_RTC.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Inc/main.h
new file mode 100644
index 000000000..576d79a8d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Inc/main.h
@@ -0,0 +1,73 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_STANDBY_RTC/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+#define RTC_ASYNCH_PREDIV    0x7F
+#define RTC_SYNCH_PREDIV     0x00F9  /* 32 kHz RC/128 - 1 */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..03d5d81d5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..8af67009a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_STANDBY_RTC/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void RTC_WKUP_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/MDK-ARM/PWR_STANDBY_RTC.uvoptx b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/MDK-ARM/PWR_STANDBY_RTC.uvoptx
new file mode 100644
index 000000000..c01b4b84d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/MDK-ARM/PWR_STANDBY_RTC.uvoptx
@@ -0,0 +1,521 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    PWR_STANDBY_RTC
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+      stm32wbxx_hal_rtc.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+      stm32wbxx_hal_rtc_ex.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      24
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/MDK-ARM/PWR_STANDBY_RTC.uvprojx b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/MDK-ARM/PWR_STANDBY_RTC.uvprojx
new file mode 100644
index 000000000..d1ccccebc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/MDK-ARM/PWR_STANDBY_RTC.uvprojx
@@ -0,0 +1,551 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      PWR_STANDBY_RTC
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          PWR_STANDBY_RTC\
+          PWR_STANDBY_RTC
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_rtc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+            
+            
+              stm32wbxx_hal_rtc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/PWR_STANDBY_RTC.ioc b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/PWR_STANDBY_RTC.ioc
new file mode 100644
index 000000000..58813f071
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/PWR_STANDBY_RTC.ioc
@@ -0,0 +1,115 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=RTC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_RTC_VS_RTC_Activate
+Mcu.Pin1=VP_SYS_VS_Systick
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=PWR_STANDBY_RTC.ioc
+ProjectManager.ProjectName=PWR_STANDBY_RTC
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_RTC_Init-RTC-false-HAL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+RTC.AsynchPrediv=RTC_ASYNCH_PREDIV
+RTC.HourFormat=RTC_HOURFORMAT_24
+RTC.IPParameters=HourFormat,AsynchPrediv,SynchPrediv
+RTC.IPParametersWithoutCheck=AsynchPrediv,SynchPrediv
+RTC.SynchPrediv=RTC_SYNCH_PREDIV
+VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
+VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..d10009c31
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/.project
new file mode 100644
index 000000000..80e455de7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/.project
@@ -0,0 +1,155 @@
+
+
+	PWR_STANDBY_RTC
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			PWR_STANDBY_RTC.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/PWR_STANDBY_RTC.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Src/main.c
new file mode 100644
index 000000000..40263f4b5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Src/main.c
@@ -0,0 +1,343 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+
+  * @file    PWR/PWR_STANDBY_RTC/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use STM32WBxx PWR HAL API to enter
+  *          and exit the Standby mode using RTC.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define LED_TOGGLE_DELAY         100UL
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+RTC_HandleTypeDef hrtc;
+
+/* USER CODE BEGIN PV */
+static __IO uint32_t TimingDelay;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_RTC_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+  
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* Configure LED2, LED3 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_RTC_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Check if the system was resumed from StandBy mode */
+  /* Note: On STM32WB, both CPU1 and CPU2 must be in standby mode to set the entire system in standby mode */
+  if(   (__HAL_PWR_GET_FLAG(PWR_FLAG_SB) != RESET)
+     && (__HAL_PWR_GET_FLAG(PWR_FLAG_C2SB) != RESET)
+    )
+  {
+    /* Clear Standby flag */
+    __HAL_PWR_CLEAR_FLAG(PWR_FLAG_SB); 
+    __HAL_PWR_CLEAR_FLAG(PWR_FLAG_C2SB);
+  }
+  
+  /* Insert 5 seconds delay */
+  HAL_Delay(5000);
+  
+  /* The Following Wakeup sequence is highly recommended prior to each Standby mode entry
+    mainly  when using more than one wakeup source this is to not miss any wakeup event.
+    - Disable all used wakeup sources,
+    - Clear all related wakeup flags, 
+    - Re-enable all used wakeup sources,
+    - Enter the Standby mode.
+  */
+  /* Disable all used wakeup sources*/
+  HAL_RTCEx_DeactivateWakeUpTimer(&hrtc);
+  
+  /* Clear all related wakeup flags */
+  __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU);
+  
+  /* Re-enable wakeup source */
+  /* ## Setting the Wake up time ############################################*/
+  /* RTC Wakeup Interrupt Generation: 
+    the wake-up counter is set to its maximum value to yield the longuest
+    stand-by time to let the current reach its lowest operating point.
+    The maximum value is 0xFFFF, corresponding to about 33 sec. when 
+    RTC_WAKEUPCLOCK_RTCCLK_DIV = RTCCLK_Div16 = 16
+
+    Wakeup Time Base = (RTC_WAKEUPCLOCK_RTCCLK_DIV /(LSI))
+    Wakeup Time = Wakeup Time Base * WakeUpCounter 
+      = (RTC_WAKEUPCLOCK_RTCCLK_DIV /(LSI)) * WakeUpCounter
+      ==> WakeUpCounter = Wakeup Time / Wakeup Time Base
+  
+    To configure the wake up timer to 33s the WakeUpCounter is set to 0xFFFF:
+    Wakeup Time Base = 16 /(~32 kHz RC) = ~0.5 ms
+    Wakeup Time = 0.5 ms  * WakeUpCounter
+    Therefore, with wake-up counter =  0xFFFF  = 65,535 
+       Wakeup Time =  0.5 ms *  65,535 = ~ 33 sec. */
+  HAL_RTCEx_SetWakeUpTimer_IT(&hrtc, 0xFFFF, RTC_WAKEUPCLOCK_RTCCLK_DIV16);
+  
+  /* Specific procedure on STM32WB, in case of initial power-up and RF stack no started */
+  /* Note: This procedure is required when user application wants to request  */
+  /*       a low-power mode in the particular case:                           */
+  /*       - RF stack not started: On STM32WB, system low-power mode is fixed */
+  /*         by the deepest low-power modes of each sub-system (CPU1,         */
+  /*         CPU2, RF).                                                       */
+  /*         Standard case is RF stack started and managing low-power modes   */
+  /*         of CPU2 and RF.                                                  */
+  /*         In case of RF stack not started, CPU2 low-power mode must be     */
+  /*         forced to the lowest level. This allows to require all system    */
+  /*         low-power modes using only PWR for CPU1.                         */
+  /*         low-power mode.                                                  */
+  /*       - Initial power-up: In case of power-on reset, CPU2 low-power mode */
+  /*         has its reset value and must be set.                             */
+  /*         In case of system is resumed from low-power mode standby         */
+  /*         or shutdown, configuration of PWR parameters related to CPU2 are */
+  /*         retained and must not modified (This check is required in case   */
+  /*         of RF stack started afterwards and not to overwritte its         */
+  /*         low-power configuration).                                        */
+  if(   (LL_PWR_IsActiveFlag_C1SB() == 0)
+     || (LL_PWR_IsActiveFlag_C2SB() == 0)
+    )
+  {
+    /* Set the lowest low-power mode for CPU2: shutdown mode */
+    LL_C2_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN);
+  }
+
+  /* Enter the Standby mode */
+  HAL_PWR_EnterSTANDBYMode();
+  
+  /* Program should never reach this point (program restart when exiting from standby mode) */
+  Error_Handler(); 
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief RTC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RTC_Init(void)
+{
+
+  /* USER CODE BEGIN RTC_Init 0 */
+
+  /* USER CODE END RTC_Init 0 */
+
+  /* USER CODE BEGIN RTC_Init 1 */
+
+  /* USER CODE END RTC_Init 1 */
+  /** Initialize RTC Only 
+  */
+  hrtc.Instance = RTC;
+  hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
+  hrtc.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
+  hrtc.Init.SynchPrediv = RTC_SYNCH_PREDIV;
+  if (HAL_RTC_Init(&hrtc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN RTC_Init 2 */
+
+  /* USER CODE END RTC_Init 2 */
+
+}
+
+/* USER CODE BEGIN 4 */
+
+
+/**
+  * @brief SYSTICK callback
+  * @param None
+  * @retval None
+  */
+void HAL_SYSTICK_Callback(void)
+{
+
+  if (TimingDelay != 0)
+  {
+    TimingDelay--;
+  }
+  else
+  {
+    /* Toggle LED2 */
+    BSP_LED_Toggle(LED2);
+    TimingDelay = LED_TOGGLE_DELAY;
+  }
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* Turn on the LED3 */
+  BSP_LED_On(LED3);
+ /* User can add his own implementation to report the HAL error return state */
+  while(1) 
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..55332e45d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,160 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_STANDBY_RTC/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief RTC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspInit 0 */
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
+  /* Intermediate configuration in case of system resume from standby mode:   */
+  /* RTC clock source disable before modifying its configuration afterwards.  */
+  /* Note: In case of user application requires RTC clock to be uninterrupted,*/
+  /*       an additional mechanism must be implemented in function of wake-up */
+  /*       status from standby mode.                                          */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_NONE;
+  if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    while(1);
+  }
+
+  /*## Configure the RTC clock source ######################################*/
+  /* Enable LSI Oscillator */
+  RCC_OscInitStruct.OscillatorType =  RCC_OSCILLATORTYPE_LSI1;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+  if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    while(1);
+  }
+
+  /* Select LSI as RTC clock source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+  if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    while(1);
+  }
+
+  /* USER CODE END RTC_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_RTC_ENABLE();
+    __HAL_RCC_RTCAPB_CLK_ENABLE();
+  /* USER CODE BEGIN RTC_MspInit 1 */
+  /*## Configure the NVIC for RTC Alarm ###################################*/
+  HAL_NVIC_SetPriority(RTC_WKUP_IRQn, 0x0, 0);
+  HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
+  /* USER CODE END RTC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspDeInit 0 */
+
+  /* USER CODE END RTC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RTC_DISABLE();
+    __HAL_RCC_RTCAPB_CLK_DISABLE();
+  /* USER CODE BEGIN RTC_MspDeInit 1 */
+
+  /* USER CODE END RTC_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..aed227144
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Src/stm32wbxx_it.c
@@ -0,0 +1,216 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_STANDBY_RTC/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+extern RTC_HandleTypeDef hrtc;
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+  HAL_SYSTICK_IRQHandler();
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles RTC Auto wake-up interrupt request.
+  * @param  None
+  * @retval None
+  */
+void RTC_WKUP_IRQHandler(void)
+{
+  HAL_RTCEx_WakeUpTimerIRQHandler(&hrtc);
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/readme.txt b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/readme.txt
new file mode 100644
index 000000000..b95421d83
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STANDBY_RTC/readme.txt
@@ -0,0 +1,108 @@
+/**
+  @page PWR_Standby PWR_STANDBY_RTC example
+
+  @verbatim
+  ******************************************************************************
+  * @file   PWR/PWR_STANDBY_RTC/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the PWR Standby RTC example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to enter the Standby mode and wake-up from this mode by using an external 
+reset or the RTC wakeup timer.
+
+
+In the associated software, the system clock is set to 64 MHz and the SysTick is
+programmed to generate an interrupt each 1 ms.
+The Low Speed Internal (LSI) clock is used as RTC clock source by default.
+EXTI_Line20 is internally connected to the RTC Wakeup event.
+
+The system automatically enters Standby mode 5 sec. after start-up. The RTC wake-up
+is configured to generate an interrupt on rising edge about 33 sec. afterwards.
+Current consumption in Standby mode with RTC feature enabled can be measured during that time.
+More than half a minute is chosen to ensure current convergence to its lowest operating point.
+
+After wake-up from Standby mode, program execution restarts in the same way as after
+a software RESET.
+
+Two leds LED2 and LED3 are used to monitor the system state as following:
+ - LED3 ON: configuration failed (system will go to an infinite loop)
+ - LED2 toggling: system in Run mode
+ - LED2 off : system in Standby mode
+
+These steps are repeated in an infinite loop.
+
+@note To measure MCU current consumption on board STM32WB Nucleo,
+      board configuration must be applied:
+      - remove all jumpers on connector JP5 to avoid leakages between ST-Link circuitry and STM32WB device.
+      - remove jumper JP2 and connect an amperemeter to measure current between the 2 connectors of JP2.
+
+@note This Standby example doesn't preserve SRAM2 content. 
+      In order to preserve SRAM2 content, RRS bit of PWR_CR3 register must
+      be set in calling HAL_PWREx_EnableSRAMRetention() API.
+      
+@note This example can not be used in DEBUG mode due to the fact 
+      that the Cortex-M4 core is no longer clocked during low power mode 
+      so debugging features are disabled.
+
+@note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select 
+      the RTC clock source; in this case the Backup domain will be reset in  
+      order to modify the RTC Clock source, as consequence RTC registers (including 
+      the backup registers) and RCC_CSR register are set to their reset values.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+Power, PWR, Standby mode, Interrupt, EXTI, Wakeup, Low Power, RTC, External reset, LSI,
+
+@par Directory contents
+
+  -  PWR/PWR_STANDBY_RTC/Inc/stm32wbxx_conf.h         HAL Configuration file
+  -  PWR/PWR_STANDBY_RTC/stm32wbxx_it.h           Header for stm32wbxx_it.c
+  -  PWR/PWR_STANDBY_RTC/Inc/main.h                         Header file for main.c
+  -  PWR/PWR_STANDBY_RTC/Src/system_stm32wbxx.c       STM32WBxx system clock configuration file
+  -  PWR/PWR_STANDBY_RTC/Src/stm32wbxx_it.c           Interrupt handlers
+  -  PWR/PWR_STANDBY_RTC/Src/main.c                         Main program
+  -  PWR/PWR_STANDBY_RTC/Src/stm32wbxx_hal_msp.c      HAL MSP module
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices
+
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE
+    board and can be easily tailored to any other supported device 
+    and development board.
+
+  - NUCLEO-WB35CE Set-up
+    - Use LED2 and LED1 connected respectively to PB.00 and LED1 pins
+
+@par How to use it ?
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/.extSettings b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/PWR_STOP2_RTC.ewd b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/PWR_STOP2_RTC.ewd
new file mode 100644
index 000000000..7ec9f49e6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/PWR_STOP2_RTC.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		PWR_STOP2_RTC
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/PWR_STOP2_RTC.ewp b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/PWR_STOP2_RTC.ewp
new file mode 100644
index 000000000..7708378ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/PWR_STOP2_RTC.ewp
@@ -0,0 +1,1125 @@
+
+
+  3
+  
+    PWR_STOP2_RTC
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/Project.eww
new file mode 100644
index 000000000..62a1a53a3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\PWR_STOP2_RTC.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Inc/main.h
new file mode 100644
index 000000000..cb048648f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Inc/main.h
@@ -0,0 +1,73 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_STOP2_RTC/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+#define RTC_ASYNCH_PREDIV    0x7F
+#define RTC_SYNCH_PREDIV     0x00F9  /* 32 kHz RC/128 - 1 */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..03d5d81d5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..41584be8c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Inc/stm32wbxx_it.h
@@ -0,0 +1,64 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_STOP2_RTC/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void RTC_WKUP_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/MDK-ARM/PWR_STOP2_RTC.uvoptx b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/MDK-ARM/PWR_STOP2_RTC.uvoptx
new file mode 100644
index 000000000..d25a93f1f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/MDK-ARM/PWR_STOP2_RTC.uvoptx
@@ -0,0 +1,521 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    PWR_STOP2_RTC
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+      stm32wbxx_hal_rtc.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+      stm32wbxx_hal_rtc_ex.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      24
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/MDK-ARM/PWR_STOP2_RTC.uvprojx b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/MDK-ARM/PWR_STOP2_RTC.uvprojx
new file mode 100644
index 000000000..8ec40a35f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/MDK-ARM/PWR_STOP2_RTC.uvprojx
@@ -0,0 +1,551 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      PWR_STOP2_RTC
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          PWR_STOP2_RTC\
+          PWR_STOP2_RTC
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_rtc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+            
+            
+              stm32wbxx_hal_rtc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/PWR_STOP2_RTC.ioc b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/PWR_STOP2_RTC.ioc
new file mode 100644
index 000000000..c493f10ce
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/PWR_STOP2_RTC.ioc
@@ -0,0 +1,115 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=RTC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_RTC_VS_RTC_Activate
+Mcu.Pin1=VP_SYS_VS_Systick
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=PWR_STOP2_RTC.ioc
+ProjectManager.ProjectName=PWR_STOP2_RTC
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+RTC.AsynchPrediv=RTC_ASYNCH_PREDIV
+RTC.HourFormat=RTC_HOURFORMAT_24
+RTC.IPParameters=HourFormat,AsynchPrediv,SynchPrediv
+RTC.IPParametersWithoutCheck=AsynchPrediv,SynchPrediv
+RTC.SynchPrediv=RTC_SYNCH_PREDIV 
+VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
+VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..f04e9b097
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/.project
new file mode 100644
index 000000000..1aa9ee8bf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/.project
@@ -0,0 +1,155 @@
+
+
+	PWR_STOP2_RTC
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			PWR_STOP2_RTC.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/PWR_STOP2_RTC.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Src/main.c
new file mode 100644
index 000000000..e8b3efcd2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Src/main.c
@@ -0,0 +1,330 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_STOP2_RTC/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use STM32WBxx PWR HAL API to enter
+  *          and exit the Stop 2 mode using RTC.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+RTC_HandleTypeDef hrtc;
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+#define LED_TOGGLE_DELAY         100
+static __IO uint32_t TimingDelay;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_RTC_Init(void);
+/* USER CODE BEGIN PFP */
+void SYSCLKConfig_STOP(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_RTC_Init();
+  /* USER CODE BEGIN 2 */
+  /* Configure LED2 and LED1 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED1);
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    /* Insert 5 second delay */
+    HAL_Delay(5000);
+  
+   /* Turn off the LED2 */
+    BSP_LED_Off(LED2);
+
+  
+    /* Disable all used wakeup source */
+    HAL_RTCEx_DeactivateWakeUpTimer(&hrtc);
+    
+    /* Re-enable wakeup source */
+    /* ## Setting the Wake up time ############################################*/
+    /* RTC Wakeup Interrupt Generation: 
+    the wake-up counter is set to its maximum value to yield the longuest
+    stop time to let the current reach its lowest operating point.
+    The maximum value is 0xFFFF, corresponding to about 33 sec. when 
+    RTC_WAKEUPCLOCK_RTCCLK_DIV = RTCCLK_Div16 = 16
+
+    Wakeup Time Base = (RTC_WAKEUPCLOCK_RTCCLK_DIV /(LSI))
+    Wakeup Time = Wakeup Time Base * WakeUpCounter 
+      = (RTC_WAKEUPCLOCK_RTCCLK_DIV /(LSI)) * WakeUpCounter
+      ==> WakeUpCounter = Wakeup Time / Wakeup Time Base
+  
+    To configure the wake up timer to maximum value, the WakeUpCounter is set to 0xFFFF:
+    Wakeup Time Base = 16 /(~32.000KHz) = ~0.5 ms
+    Wakeup Time = 0.5 ms  * WakeUpCounter
+    Therefore, with wake-up counter =  0xFFFF  = 65,535 
+       Wakeup Time =  0,5 ms *  65,535 = 32,7675 s ~ 33 sec. */
+    HAL_RTCEx_SetWakeUpTimer_IT(&hrtc, 0x0FFFF, RTC_WAKEUPCLOCK_RTCCLK_DIV16);
+  
+    /* Enter STOP 2 mode */
+    HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI);
+    
+    /* ... Stop 2 mode ... */
+
+    /* Configure system clock after wake-up from STOP: enable MSI, PLL and select
+    MSI as system clock source (MSI and PLL are disabled in STOP mode) */
+    SYSCLKConfig_STOP();
+
+    /* Re-configure LED2 */
+    /* Note: LED state is controlled in function "HAL_SYSTICK_Callback" */
+    BSP_LED_Init(LED2);
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief RTC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RTC_Init(void)
+{
+
+  /* USER CODE BEGIN RTC_Init 0 */
+
+  /* USER CODE END RTC_Init 0 */
+
+  /* USER CODE BEGIN RTC_Init 1 */
+
+  /* USER CODE END RTC_Init 1 */
+  /** Initialize RTC Only 
+  */
+  hrtc.Instance = RTC;
+  hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
+  hrtc.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
+  hrtc.Init.SynchPrediv = RTC_SYNCH_PREDIV ;
+  if (HAL_RTC_Init(&hrtc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN RTC_Init 2 */
+
+  /* USER CODE END RTC_Init 2 */
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  Configures system clock after wake-up from STOP: enable MSI, PLL
+  *         and select MSI as system clock source.
+  * @param  None
+  * @retval None
+  */
+void SYSCLKConfig_STOP(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  uint32_t pFLatency = 0;
+
+  /* Get the Oscillators configuration according to the internal RCC registers */
+  HAL_RCC_GetOscConfig(&RCC_OscInitStruct);
+
+  /* After wake-up from STOP reconfigure the system clock: Enable MSI and PLL */
+  RCC_OscInitStruct.OscillatorType  = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState        = RCC_MSI_ON;
+  RCC_OscInitStruct.PLL.PLLState    = RCC_PLL_ON;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* Get the Clocks configuration according to the internal RCC registers */
+  HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &pFLatency);
+
+  /* Select MSI as system clock source */
+  RCC_ClkInitStruct.ClockType     = RCC_CLOCKTYPE_SYSCLK;
+  RCC_ClkInitStruct.SYSCLKSource  = RCC_SYSCLKSOURCE_MSI;
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, pFLatency) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief SYSTICK callback
+  * @param None
+  * @retval None
+  */
+void HAL_SYSTICK_Callback(void)
+{
+  if (TimingDelay != 0)
+  {
+    TimingDelay--;
+  }
+  else
+  {
+    /* Toggle LED2 */
+    BSP_LED_Toggle(LED2);
+    TimingDelay = LED_TOGGLE_DELAY;
+  }
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* Turn on the LED1 */
+  BSP_LED_On(LED1);
+  /* User can add his own implementation to report the HAL error return state */
+  while(1) 
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..6a2a4321b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,161 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_STOP2_RTC/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief RTC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspInit 0 */
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
+
+  /* Specific procedure on STM32WB before setting RTC clock to LSI1:          */
+  /* Need to clear LSE ready flag set from previous program run.              */
+  /* Enable backup access */
+  HAL_PWR_EnableBkUpAccess();
+
+  /* Reset backup domain */
+  LL_RCC_ForceBackupDomainReset();
+  LL_RCC_ReleaseBackupDomainReset();
+  
+  /* Disable backup access */
+  HAL_PWR_DisableBkUpAccess();
+  
+  /*## Configure the RTC clock source ######################################*/
+  /* Enable LSI Oscillator */
+  RCC_OscInitStruct.OscillatorType =  RCC_OSCILLATORTYPE_LSI1;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+  if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    while(1);
+  }
+
+  /* -b- Select LSI as RTC clock source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+  if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  { 
+    while(1);
+  }
+
+  /* USER CODE END RTC_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_RTC_ENABLE();
+    __HAL_RCC_RTCAPB_CLK_ENABLE();
+  /* USER CODE BEGIN RTC_MspInit 1 */
+  /*## Configure the NVIC for RTC Alarm ###################################*/
+  HAL_NVIC_SetPriority(RTC_WKUP_IRQn, 0x0, 0);
+  HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
+  /* USER CODE END RTC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspDeInit 0 */
+
+  /* USER CODE END RTC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RTC_DISABLE();
+    __HAL_RCC_RTCAPB_CLK_DISABLE();
+  /* USER CODE BEGIN RTC_MspDeInit 1 */
+
+  /* USER CODE END RTC_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..9cec0a1fe
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Src/stm32wbxx_it.c
@@ -0,0 +1,131 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    PWR/PWR_STOP2_RTC/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+extern RTC_HandleTypeDef hrtc;
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+  HAL_SYSTICK_IRQHandler();
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles RTC Auto wake-up interrupt request.
+  * @param  None
+  * @retval None
+  */
+void RTC_WKUP_IRQHandler(void)
+{
+  HAL_RTCEx_WakeUpTimerIRQHandler(&hrtc);
+}
+
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/readme.txt b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/readme.txt
new file mode 100644
index 000000000..0a1a418e0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/PWR/PWR_STOP2_RTC/readme.txt
@@ -0,0 +1,103 @@
+/**
+  @page PWR_Standby PWR_STOP2_RTC example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    PWR/PWR_STOP2_RTC/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the Power Stop 2 RTC example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to enter the Stop 2 mode and wake-up from this mode using an external reset 
+or RTC wakeup timer.
+It allows to measure the current consumption in Stop 2 mode with RTC enabled.
+
+In the associated software, the system clock is set to 64 MHz and the SysTick is 
+programmed to generate an interrupt each 1 ms.
+The Low Speed Internal (LSI) clock is used as RTC clock source by default.
+EXTI_Line19 is internally connected to the RTC Wakeup event.
+
+The system automatically enters Stop 2 mode 5 sec. after start-up. The RTC wake-up 
+is configured to generate an interrupt on rising edge about 33 sec. afterwards.
+Current consumption in Stop 2 mode with RTC feature enabled can be measured during that time.
+More than half a minute is chosen to ensure current convergence to its lowest operating point.
+
+After wake-up from Stop 2 mode, program execution is resumed.
+
+Two leds LED2 and LED1 are used to monitor the system state as following:
+ - LED1 ON: configuration failed (system will go to an infinite loop)
+ - LED2 toggling: system in Run mode
+ - LED2 off : system in Stop 2 mode
+
+These steps are repeated in an infinite loop.
+
+@note To measure MCU current consumption on board STM32WB Nucleo,
+      board configuration must be applied:
+      - remove all jumpers on connector JP5 to avoid leakages between ST-Link circuitry and STM32WB device.
+      - remove jumper JP2 and connect an amperemeter to measure current between the 2 connectors of JP2.
+
+@note This example can not be used in DEBUG mode due to the fact 
+      that the Cortex-M4 core is no longer clocked during low power mode 
+      so debugging features are disabled.
+
+@note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select 
+      the RTC clock source; in this case the Backup domain will be reset in  
+      order to modify the RTC Clock source, as consequence RTC registers (including 
+      the backup registers) and RCC_CSR register are set to their reset values.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+Power, PWR, Stop 2 mode, Interrupt, EXTI, Wakeup, Low Power, RTC, External reset
+
+@par Directory contents 
+
+  - PWR/PWR_STOP2_RTC/Inc/stm32wbxx_conf.h         HAL Configuration file
+  - PWR/PWR_STOP2_RTC/Inc/stm32wbxx_it.h           Header for stm32wbxx_it.c
+  - PWR/PWR_STOP2_RTC/Inc/main.h                         Header file for main.c
+  - PWR/PWR_STOP2_RTC/Src/system_stm32wbxx.c       STM32WBxx system clock configuration file
+  - PWR/PWR_STOP2_RTC/Src/stm32wbxx_it.c           Interrupt handlers
+  - PWR/PWR_STOP2_RTC/Src/main.c                         Main program
+  - PWR/PWR_STOP2_RTC/Src/stm32wbxx_hal_msp.c      HAL MSP module
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WBxx devices
+    
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE
+    board and can be easily tailored to any other supported device 
+    and development board.
+
+  - NUCLEO-WB35CE Set-up
+    - Use LED2 and LED1 connected respectively to PB.00 and PB.05 pins
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/.extSettings b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/Project.eww
new file mode 100644
index 000000000..8ec595d22
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\QSPI_ReadWrite_DMA.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/QSPI_ReadWrite_DMA.ewd b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/QSPI_ReadWrite_DMA.ewd
new file mode 100644
index 000000000..d199a2b02
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/QSPI_ReadWrite_DMA.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		QSPI_ReadWrite_DMA
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/QSPI_ReadWrite_DMA.ewp b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/QSPI_ReadWrite_DMA.ewp
new file mode 100644
index 000000000..d5e7aaa38
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/QSPI_ReadWrite_DMA.ewp
@@ -0,0 +1,1126 @@
+
+
+  3
+  
+    QSPI_ReadWrite_DMA
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        30
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$\startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$\..\Src\main.c
+      
+      
+        $PROJ_DIR$\..\Src\stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$\..\Src\stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$\..\readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$\..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE\nucleo_wb35ce.c
+        
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$\..\Src\system_stm32wbxx.c
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_qspi.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$\..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_hal_tim_ex.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..09797b971
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb55xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB55xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Inc/main.h
new file mode 100644
index 000000000..38385221e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Inc/main.h
@@ -0,0 +1,138 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    QSPI/QSPI_ReadWrite_DMA/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+#define COUNTOF(__BUFFER__)        (sizeof(__BUFFER__) / sizeof(*(__BUFFER__)))
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+/* N25Q064A Micron memory */
+/* Size of the flash */
+#define QSPI_FLASH_SIZE                      22
+#define QSPI_PAGE_SIZE                       256
+
+/* Identification Operations */
+#define READ_ID_CMD                          0x9E
+#define READ_ID_CMD2                         0x9F
+#define MULTIPLE_IO_READ_ID_CMD              0xAF
+#define READ_SERIAL_FLASH_DISCO_PARAM_CMD    0x5A
+
+/* Read Operations */
+#define READ_CMD                             0x03
+#define FAST_READ_CMD                        0x0B
+#define DUAL_OUT_FAST_READ_CMD               0x3B
+#define DUAL_INOUT_FAST_READ_CMD             0xBB
+#define QUAD_OUT_FAST_READ_CMD               0x6B
+#define QUAD_INOUT_FAST_READ_CMD             0xEB
+
+/* Write Operations */
+#define WRITE_ENABLE_CMD                     0x06
+#define WRITE_DISABLE_CMD                    0x04
+
+/* Register Operations */
+#define READ_STATUS_REG_CMD                  0x05
+#define WRITE_STATUS_REG_CMD                 0x01
+
+#define READ_LOCK_REG_CMD                    0xE8
+#define WRITE_LOCK_REG_CMD                   0xE5
+
+#define READ_FLAG_STATUS_REG_CMD             0x70
+#define CLEAR_FLAG_STATUS_REG_CMD            0x50
+
+#define READ_NONVOL_CFG_REG_CMD              0xB5
+#define WRITE_NONVOL_CFG_REG_CMD             0xB1
+
+#define READ_VOL_CFG_REG_CMD                 0x85
+#define WRITE_VOL_CFG_REG_CMD                0x81
+
+#define READ_ENHANCED_VOL_CFG_REG_CMD        0x65
+#define WRITE_ENHANCED_VOL_CFG_REG_CMD       0x61
+
+/* Program Operations */
+#define PAGE_PROG_CMD                        0x02
+#define DUAL_IN_FAST_PROG_CMD                0xA2
+#define EXT_DUAL_IN_FAST_PROG_CMD            0xD2
+#define QUAD_IN_FAST_PROG_CMD                0x32
+#define EXT_QUAD_IN_FAST_PROG_CMD            0x12
+
+/* Erase Operations */
+#define SUBSECTOR_ERASE_CMD                  0x20
+#define SECTOR_ERASE_CMD                     0xD8
+#define BULK_ERASE_CMD                       0xC7
+#define PROG_ERASE_RESUME_CMD                0x7A
+#define PROG_ERASE_SUSPEND_CMD               0x75
+
+/* One-Time Programmable Operations */
+#define READ_OTP_ARRAY_CMD                   0x4B
+#define PROG_OTP_ARRAY_CMD                   0x42
+
+/* Default dummy clocks cycles */
+#define DUMMY_CLOCK_CYCLES_READ              2
+
+/* End address of the QSPI memory */
+#define QSPI_END_ADDR              (1 << QSPI_FLASH_SIZE)
+
+/* Size of buffers */
+#define BUFFERSIZE                 (COUNTOF(aTxBuffer) - 1)
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..5b4722231
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+#define HAL_QSPI_MODULE_ENABLED
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..230736637
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Inc/stm32wbxx_it.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    QSPI/QSPI_ReadWrite_DMA/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void DMA1_Channel5_IRQHandler(void);
+void QUADSPI_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/MDK-ARM/QSPI_ReadWrite_DMA.uvoptx b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/MDK-ARM/QSPI_ReadWrite_DMA.uvoptx
new file mode 100644
index 000000000..a8ef892a5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/MDK-ARM/QSPI_ReadWrite_DMA.uvoptx
@@ -0,0 +1,526 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    QSPI_ReadWrite_DMA
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+        
+          0
+          0
+          72
+          1
+          
    0
    
+          0
+          0
+          0
+          0
+          0
+          0
+          ../readme.txt
+          
+          
+            
+          
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+        
+      
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      2
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      4
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c
+      stm32wbxx_hal_qspi.c
+      0
+      0
+    
+    
+      4
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      4
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      4
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      4
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      4
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      4
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      4
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      4
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      4
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      4
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      4
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      4
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      4
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      4
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      5
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/MDK-ARM/QSPI_ReadWrite_DMA.uvprojx b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/MDK-ARM/QSPI_ReadWrite_DMA.uvprojx
new file mode 100644
index 000000000..2c7ac06e0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/MDK-ARM/QSPI_ReadWrite_DMA.uvprojx
@@ -0,0 +1,547 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      QSPI_ReadWrite_DMA
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          QSPI_ReadWrite_DMA\
+          QSPI_ReadWrite_DMA
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc; ../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc; ../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy; ../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include; ../../../../../../Drivers/CMSIS/Include; ../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_qspi.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/QSPI_ReadWrite_DMA.ioc b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/QSPI_ReadWrite_DMA.ioc
new file mode 100644
index 000000000..130131a2a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/QSPI_ReadWrite_DMA.ioc
@@ -0,0 +1,162 @@
+#MicroXplorer Configuration settings - do not modify
+Dma.QUADSPI.0.Direction=DMA_PERIPH_TO_MEMORY
+Dma.QUADSPI.0.EventEnable=DISABLE
+Dma.QUADSPI.0.Instance=DMA1_Channel5
+Dma.QUADSPI.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.QUADSPI.0.MemInc=DMA_MINC_ENABLE
+Dma.QUADSPI.0.Mode=DMA_NORMAL
+Dma.QUADSPI.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.QUADSPI.0.PeriphInc=DMA_PINC_DISABLE
+Dma.QUADSPI.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.QUADSPI.0.Priority=DMA_PRIORITY_LOW
+Dma.QUADSPI.0.RequestNumber=1
+Dma.QUADSPI.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.QUADSPI.0.SignalID=NONE
+Dma.QUADSPI.0.SyncEnable=DISABLE
+Dma.QUADSPI.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.QUADSPI.0.SyncRequestNumber=1
+Dma.QUADSPI.0.SyncSignalID=NONE
+Dma.Request0=QUADSPI
+Dma.RequestsNb=1
+File.Version=6
+KeepUserPlacement=false
+Mcu.Family=STM32WB
+Mcu.IP0=DMA
+Mcu.IP1=NVIC
+Mcu.IP2=QUADSPI
+Mcu.IP3=RCC
+Mcu.IP4=SYS
+Mcu.IPNb=5
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB8
+Mcu.Pin1=PB9
+Mcu.Pin2=PA2
+Mcu.Pin3=PA3
+Mcu.Pin4=PA6
+Mcu.Pin5=PA7
+Mcu.Pin6=VP_SYS_VS_Systick
+Mcu.PinsNb=7
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DMA1_Channel5_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.QUADSPI_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA2.GPIOParameters=GPIO_Speed
+PA2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA2.Mode=Single Bank 1
+PA2.Signal=QUADSPI_BK1_NCS
+PA3.GPIOParameters=GPIO_Speed
+PA3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA3.Mode=Single Bank 1
+PA3.Signal=QUADSPI_CLK
+PA6.GPIOParameters=GPIO_Speed
+PA6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA6.Mode=Single Bank 1
+PA6.Signal=QUADSPI_BK1_IO3
+PA7.GPIOParameters=GPIO_Speed
+PA7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA7.Mode=Single Bank 1
+PA7.Signal=QUADSPI_BK1_IO2
+PB8.GPIOParameters=GPIO_Speed
+PB8.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PB8.Mode=Single Bank 1
+PB8.Signal=QUADSPI_BK1_IO1
+PB9.GPIOParameters=GPIO_Speed
+PB9.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PB9.Mode=Single Bank 1
+PB9.Signal=QUADSPI_BK1_IO0
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=false
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=QSPI_ReadWrite_DMA.ioc
+ProjectManager.ProjectName=QSPI_ReadWrite_DMA
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8.32
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,1-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_QUADSPI_Init-QUADSPI-false-HAL-true
+QUADSPI.ClockPrescaler=2
+QUADSPI.FifoThreshold=4
+QUADSPI.FlashSize=22
+QUADSPI.IPParameters=ClockPrescaler,FifoThreshold,SampleShifting,FlashSize
+QUADSPI.SampleShifting=QSPI_SAMPLE_SHIFTING_HALFCYCLE
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..703ee16d3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/.cproject
@@ -0,0 +1,170 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/.project
new file mode 100644
index 000000000..8a47870fb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/.project
@@ -0,0 +1,150 @@
+
+
+	QSPI_ReadWrite_DMA
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			QSPI_ReadWrite_DMA.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/QSPI_ReadWrite_DMA.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_qspi.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/P-NUCLEO-WB55.Nucleo/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Src/main.c
new file mode 100644
index 000000000..f3c0d3387
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Src/main.c
@@ -0,0 +1,602 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    QSPI/QSPI_ReadWrite_DMA/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to erase part of the QSPI memory, write
+  *          data in DMA mode, read data in DMA mode and compare the result in
+  *          a forever loop.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+QSPI_HandleTypeDef hqspi;
+DMA_HandleTypeDef hdma_quadspi;
+
+/* USER CODE BEGIN PV */
+__IO uint8_t CmdCplt, RxCplt, TxCplt, StatusMatch;
+
+/* Buffer used for transmission */
+uint8_t aTxBuffer[] = " ****QSPI communication based on DMA****  ****QSPI communication based on DMA****  ****QSPI communication based on DMA****  ****QSPI communication based on DMA****  ****QSPI communication based on DMA****  ****QSPI communication based on DMA**** ";
+
+/* Buffer used for reception */
+uint8_t aRxBuffer[BUFFERSIZE];
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+static void MX_QUADSPI_Init(void);
+/* USER CODE BEGIN PFP */
+static void QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi);
+static void QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi);
+static void QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  QSPI_CommandTypeDef sCommand;
+  uint32_t address = 0;
+  uint16_t index;
+  __IO uint8_t step = 0;
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_QUADSPI_Init();
+  /* USER CODE BEGIN 2 */
+  BSP_LED_Init(LED_GREEN);
+  BSP_LED_Init(LED_RED);
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  sCommand.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
+  sCommand.AddressSize       = QSPI_ADDRESS_24_BITS;
+  sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
+  sCommand.DdrMode           = QSPI_DDR_MODE_DISABLE;
+  sCommand.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
+
+  while (1)
+  {
+    switch(step)
+    {
+      case 0:
+        CmdCplt = 0;
+
+        /* Initialize Reception buffer --------------------------------------- */
+        for (index = 0; index < BUFFERSIZE; index++)
+        {
+          aRxBuffer[index] = 0;
+        }
+
+        /* Enable write operations ------------------------------------------- */
+        QSPI_WriteEnable(&hqspi);
+
+        /* Erasing Sequence -------------------------------------------------- */
+        sCommand.Instruction = SUBSECTOR_ERASE_CMD;
+        sCommand.AddressMode = QSPI_ADDRESS_1_LINE;
+        sCommand.Address     = address;
+        sCommand.DataMode    = QSPI_DATA_NONE;
+        sCommand.DummyCycles = 0;
+
+        if (HAL_QSPI_Command_IT(&hqspi, &sCommand) != HAL_OK)
+        {
+          Error_Handler();
+        }
+
+        step++;
+        break;
+
+      case 1:
+        if(CmdCplt != 0)
+        {
+          CmdCplt = 0;
+          StatusMatch = 0;
+
+          /* Configure automatic polling mode to wait for end of erase ------- */
+          QSPI_AutoPollingMemReady(&hqspi);
+
+          step++;
+        }
+        break;
+
+      case 2:
+        if(StatusMatch != 0)
+        {
+          StatusMatch = 0;
+          TxCplt = 0;
+
+          /* Enable write operations ----------------------------------------- */
+          QSPI_WriteEnable(&hqspi);
+
+          /* Writing Sequence ------------------------------------------------ */
+          sCommand.Instruction = EXT_DUAL_IN_FAST_PROG_CMD;
+          sCommand.AddressMode = QSPI_ADDRESS_2_LINES;
+          sCommand.DataMode    = QSPI_DATA_2_LINES;
+          sCommand.NbData      = BUFFERSIZE;
+
+          if (HAL_QSPI_Command(&hqspi, &sCommand, HAL_QSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+          {
+            Error_Handler();
+          }
+
+          if (HAL_QSPI_Transmit_DMA(&hqspi, aTxBuffer) != HAL_OK)
+          {
+            Error_Handler();
+          }
+
+          step++;
+        }
+        break;
+
+      case 3:
+        if(TxCplt != 0)
+        {
+          TxCplt = 0;
+          StatusMatch = 0;
+
+          /* Configure automatic polling mode to wait for end of program ----- */
+          QSPI_AutoPollingMemReady(&hqspi);
+
+          step++;
+        }
+        break;
+
+      case 4:
+        if(StatusMatch != 0)
+        {
+          StatusMatch = 0;
+          RxCplt = 0;
+
+          /* Configure Volatile Configuration register (with new dummy cycles) */
+          QSPI_DummyCyclesCfg(&hqspi);
+
+          /* Reading Sequence ------------------------------------------------ */
+          sCommand.Instruction = QUAD_OUT_FAST_READ_CMD;
+          sCommand.AddressMode = QSPI_ADDRESS_1_LINE;
+          sCommand.DataMode    = QSPI_DATA_4_LINES;
+          sCommand.DummyCycles = DUMMY_CLOCK_CYCLES_READ;
+
+          if (HAL_QSPI_Command(&hqspi, &sCommand, HAL_QSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+          {
+            Error_Handler();
+          }
+
+          if (HAL_QSPI_Receive_DMA(&hqspi, aRxBuffer) != HAL_OK)
+          {
+            Error_Handler();
+          }
+          step++;
+        }
+        break;
+
+      case 5:
+        if (RxCplt != 0)
+        {
+          RxCplt = 0;
+
+          /* Result comparison ----------------------------------------------- */
+          for (index = 0; index < BUFFERSIZE; index++)
+          {
+            if (aRxBuffer[index] != aTxBuffer[index])
+            {
+              BSP_LED_On(LED_RED);
+            }
+          }
+          BSP_LED_Toggle(LED_GREEN);
+
+          address += QSPI_PAGE_SIZE;
+          if(address >= QSPI_END_ADDR)
+          {
+            address = 0;
+          }
+          step = 0;
+        }
+        break;
+
+      default :
+        Error_Handler();
+    }
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief QUADSPI Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_QUADSPI_Init(void)
+{
+
+  /* USER CODE BEGIN QUADSPI_Init 0 */
+
+  /* USER CODE END QUADSPI_Init 0 */
+
+  /* USER CODE BEGIN QUADSPI_Init 1 */
+
+  /* USER CODE END QUADSPI_Init 1 */
+  /* QUADSPI parameter configuration*/
+  hqspi.Instance = QUADSPI;
+  hqspi.Init.ClockPrescaler = 2;
+  hqspi.Init.FifoThreshold = 4;
+  hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
+  hqspi.Init.FlashSize = 22;
+  hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE;
+  hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;
+  if (HAL_QSPI_Init(&hqspi) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN QUADSPI_Init 2 */
+
+  /* USER CODE END QUADSPI_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel5_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Command completed callbacks.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  CmdCplt++;
+}
+
+/**
+  * @brief  Rx Transfer completed callbacks.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  RxCplt++;
+}
+
+/**
+  * @brief  Tx Transfer completed callbacks.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  TxCplt++;
+}
+
+/**
+  * @brief  Status Match callbacks
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
+{
+  StatusMatch++;
+}
+
+/**
+  * @brief  This function send a Write Enable and wait it is effective.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+static void QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi)
+{
+  QSPI_CommandTypeDef     sCommand;
+  QSPI_AutoPollingTypeDef sConfig;
+
+  /* Enable write operations ------------------------------------------ */
+  sCommand.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
+  sCommand.Instruction       = WRITE_ENABLE_CMD;
+  sCommand.AddressMode       = QSPI_ADDRESS_NONE;
+  sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
+  sCommand.DataMode          = QSPI_DATA_NONE;
+  sCommand.DummyCycles       = 0;
+  sCommand.DdrMode           = QSPI_DDR_MODE_DISABLE;
+  sCommand.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
+
+  if (HAL_QSPI_Command(hqspi, &sCommand, HAL_QSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* Configure automatic polling mode to wait for write enabling ---- */
+  sConfig.Match           = 0x02;
+  sConfig.Mask            = 0x02;
+  sConfig.MatchMode       = QSPI_MATCH_MODE_AND;
+  sConfig.StatusBytesSize = 1;
+  sConfig.Interval        = 0x10;
+  sConfig.AutomaticStop   = QSPI_AUTOMATIC_STOP_ENABLE;
+
+  sCommand.Instruction    = READ_STATUS_REG_CMD;
+  sCommand.DataMode       = QSPI_DATA_1_LINE;
+
+  if (HAL_QSPI_AutoPolling(hqspi, &sCommand, &sConfig, HAL_QSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief  This function read the SR of the memory and wait the EOP.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+static void QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi)
+{
+  QSPI_CommandTypeDef     sCommand;
+  QSPI_AutoPollingTypeDef sConfig;
+
+  /* Configure automatic polling mode to wait for memory ready ------ */
+  sCommand.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
+  sCommand.Instruction       = READ_STATUS_REG_CMD;
+  sCommand.AddressMode       = QSPI_ADDRESS_NONE;
+  sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
+  sCommand.DataMode          = QSPI_DATA_1_LINE;
+  sCommand.DummyCycles       = 0;
+  sCommand.DdrMode           = QSPI_DDR_MODE_DISABLE;
+  sCommand.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
+
+  sConfig.Match           = 0x00;
+  sConfig.Mask            = 0x01;
+  sConfig.MatchMode       = QSPI_MATCH_MODE_AND;
+  sConfig.StatusBytesSize = 1;
+  sConfig.Interval        = 0x10;
+  sConfig.AutomaticStop   = QSPI_AUTOMATIC_STOP_ENABLE;
+
+  if (HAL_QSPI_AutoPolling_IT(hqspi, &sCommand, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief  This function configure the dummy cycles on memory side.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+static void QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi)
+{
+  QSPI_CommandTypeDef sCommand;
+  uint8_t reg;
+
+  /* Read Volatile Configuration register --------------------------- */
+  sCommand.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
+  sCommand.Instruction       = READ_VOL_CFG_REG_CMD;
+  sCommand.AddressMode       = QSPI_ADDRESS_NONE;
+  sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
+  sCommand.DataMode          = QSPI_DATA_1_LINE;
+  sCommand.DummyCycles       = 0;
+  sCommand.DdrMode           = QSPI_DDR_MODE_DISABLE;
+  sCommand.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
+  sCommand.NbData            = 1;
+
+  if (HAL_QSPI_Command(hqspi, &sCommand, HAL_QSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  if (HAL_QSPI_Receive(hqspi, ®, HAL_QSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* Enable write operations ---------------------------------------- */
+  QSPI_WriteEnable(hqspi);
+
+  /* Write Volatile Configuration register (with new dummy cycles) -- */
+  sCommand.Instruction = WRITE_VOL_CFG_REG_CMD;
+  MODIFY_REG(reg, 0xF0, (DUMMY_CLOCK_CYCLES_READ << POSITION_VAL(0xF0)));
+
+  if (HAL_QSPI_Command(hqspi, &sCommand, HAL_QSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  if (HAL_QSPI_Transmit(hqspi, ®, HAL_QSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  while(1)
+  {
+    HAL_Delay(100);
+    BSP_LED_Toggle(LED_RED);
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..d06563d52
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,191 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    QSPI/QSPI_ReadWrite_DMA/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_quadspi;
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief QSPI MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hqspi: QSPI handle pointer
+* @retval None
+*/
+void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hqspi->Instance==QUADSPI)
+  {
+  /* USER CODE BEGIN QUADSPI_MspInit 0 */
+
+  /* USER CODE END QUADSPI_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_QSPI_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**QUADSPI GPIO Configuration    
+    PB8     ------> QUADSPI_BK1_IO1
+    PB9     ------> QUADSPI_BK1_IO0
+    PA2     ------> QUADSPI_BK1_NCS
+    PA3     ------> QUADSPI_CLK
+    PA6     ------> QUADSPI_BK1_IO3
+    PA7     ------> QUADSPI_BK1_IO2 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* QUADSPI DMA Init */
+    /* QUADSPI Init */
+    hdma_quadspi.Instance = DMA1_Channel5;
+    hdma_quadspi.Init.Request = DMA_REQUEST_QUADSPI;
+    hdma_quadspi.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_quadspi.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_quadspi.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_quadspi.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_quadspi.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_quadspi.Init.Mode = DMA_NORMAL;
+    hdma_quadspi.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_quadspi) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(hqspi,hdma,hdma_quadspi);
+
+    /* QUADSPI interrupt Init */
+    HAL_NVIC_SetPriority(QUADSPI_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(QUADSPI_IRQn);
+  /* USER CODE BEGIN QUADSPI_MspInit 1 */
+
+  /* USER CODE END QUADSPI_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief QSPI MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hqspi: QSPI handle pointer
+* @retval None
+*/
+void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi)
+{
+  if(hqspi->Instance==QUADSPI)
+  {
+  /* USER CODE BEGIN QUADSPI_MspDeInit 0 */
+
+  /* USER CODE END QUADSPI_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_QSPI_CLK_DISABLE();
+  
+    /**QUADSPI GPIO Configuration    
+    PB8     ------> QUADSPI_BK1_IO1
+    PB9     ------> QUADSPI_BK1_IO0
+    PA2     ------> QUADSPI_BK1_NCS
+    PA3     ------> QUADSPI_CLK
+    PA6     ------> QUADSPI_BK1_IO3
+    PA7     ------> QUADSPI_BK1_IO2 
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9);
+
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_6|GPIO_PIN_7);
+
+    /* QUADSPI DMA DeInit */
+    HAL_DMA_DeInit(hqspi->hdma);
+
+    /* QUADSPI interrupt DeInit */
+    HAL_NVIC_DisableIRQ(QUADSPI_IRQn);
+  /* USER CODE BEGIN QUADSPI_MspDeInit 1 */
+
+  /* USER CODE END QUADSPI_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..9ae851312
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Src/stm32wbxx_it.c
@@ -0,0 +1,235 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    QSPI/QSPI_ReadWrite_DMA/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_quadspi;
+extern QSPI_HandleTypeDef hqspi;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles DMA1 channel5 global interrupt.
+  */
+void DMA1_Channel5_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel5_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_quadspi);
+  /* USER CODE BEGIN DMA1_Channel5_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel5_IRQn 1 */
+}
+
+/**
+  * @brief This function handles QUADSPI global interrupt.
+  */
+void QUADSPI_IRQHandler(void)
+{
+  /* USER CODE BEGIN QUADSPI_IRQn 0 */
+
+  /* USER CODE END QUADSPI_IRQn 0 */
+  HAL_QSPI_IRQHandler(&hqspi);
+  /* USER CODE BEGIN QUADSPI_IRQn 1 */
+
+  /* USER CODE END QUADSPI_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..6a847a91e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/Src/system_stm32wbxx.c
@@ -0,0 +1,351 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/readme.txt b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/readme.txt
new file mode 100644
index 000000000..7927e63fa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/QSPI/QSPI_ReadWrite_DMA/readme.txt
@@ -0,0 +1,82 @@
+/**
+  @page QSPI_ReadWrite_DMA QSPI Read/Write in DMA mode example
+
+  @verbatim
+  ******************************************************************************
+  * @file    QSPI/QSPI_ReadWrite_DMA/readme.txt
+  * @author  MCD Application Team
+  * @brief   QSPI Read/Write in DMA mode example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2018 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to erase part of the QSPI memory, write data in DMA mode,
+read data in DMA mode and compare the result in a forever loop.
+
+LED_GREEN toggles each time the data have been checked
+LED_RED toggles as soon as an error is returned by HAL API
+LED_RED is on as soon as a data is wrong
+
+In this example, HCLK is configured at 64 MHz.
+QSPI prescaler is set to 2, so QSPI frequency is = HCLK/(QSPI_Prescaler+1) = 64 MHz/(2+1)
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note The application need to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+Memory, QSPI, Erase, Read, Write, DMA
+
+@par Directory contents
+
+  - QSPI/QSPI_ReadWrite_DMA/Inc/stm32wbxx_hal_conf.h HAL configuration file
+  - QSPI/QSPI_ReadWrite_DMA/Inc/stm32wbxx_it.h       Interrupt handlers header file
+  - QSPI/QSPI_ReadWrite_DMA/Inc/main.h               Header for main.c module
+  - QSPI/QSPI_ReadWrite_DMA/Src/stm32wbxx_it.c       Interrupt handlers
+  - QSPI/QSPI_ReadWrite_DMA/Src/main.c               Main program
+  - QSPI/QSPI_ReadWrite_DMA/Src/system_stm32wbxx.c   STM32WBxx system source file
+  - QSPI/QSPI_ReadWrite_DMA/Src/stm32wbxx_hal_msp.c  HAL MSP file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35xx devices.
+
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+  - NUCLEO-WB55RG Set-up :
+    Tested on memory Micron N25Q064A with following connections
+    - Connect PA2 to S# (Chip Select)
+    - Connect PA3 to C (Clock)
+    - Connect PB9 to DQ0 (Serial Data)
+    - Connect PB8 to DQ1 (Serial Data)
+    - Connect PA7 to DQ2 (DQ2)
+    - Connect PA6 to DQ3 (DQ3)
+    - Connect NRST to RESET# (Reset)
+
+@par How to use it ?
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/.extSettings b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/Project.eww
new file mode 100644
index 000000000..6d4a93048
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\RCC_ClockConfig.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/RCC_ClockConfig.ewd b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/RCC_ClockConfig.ewd
new file mode 100644
index 000000000..7ccf2f7e3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/RCC_ClockConfig.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		RCC_ClockConfig
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/RCC_ClockConfig.ewp b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/RCC_ClockConfig.ewp
new file mode 100644
index 000000000..128a8bc3f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/RCC_ClockConfig.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    RCC_ClockConfig
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Inc/main.h
new file mode 100644
index 000000000..be9daf9de
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RCC/RCC_ClockConfig/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..19d12a61f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..58929fcc6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Inc/stm32wbxx_it.h
@@ -0,0 +1,64 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RCC/RCC_ClockConfig/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void EXTI0_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/MDK-ARM/RCC_ClockConfig.uvoptx b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/MDK-ARM/RCC_ClockConfig.uvoptx
new file mode 100644
index 000000000..173139413
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/MDK-ARM/RCC_ClockConfig.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    RCC_ClockConfig
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/MDK-ARM/RCC_ClockConfig.uvprojx b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/MDK-ARM/RCC_ClockConfig.uvprojx
new file mode 100644
index 000000000..3c61c3f07
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/MDK-ARM/RCC_ClockConfig.uvprojx
@@ -0,0 +1,541 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      RCC_ClockConfig
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          RCC_ClockConfig\
+          RCC_ClockConfig
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/RCC_ClockConfig.ioc b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/RCC_ClockConfig.ioc
new file mode 100644
index 000000000..1ad9658c8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/RCC_ClockConfig.ioc
@@ -0,0 +1,106 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=false
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=RCC_ClockConfig.ioc
+ProjectManager.ProjectName=RCC_ClockConfig
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..5ce0f4c94
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/.project
new file mode 100644
index 000000000..36ba46037
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	RCC_ClockConfig
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			RCC_ClockConfig.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/RCC_ClockConfig.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Src/main.c
new file mode 100644
index 000000000..f128e5cb8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Src/main.c
@@ -0,0 +1,489 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RCC/RCC_ClockConfig/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to use the RCC HAL API to configure the
+  *          system clock (SYSCLK) and modify the clock settings on run time.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+__IO FlagStatus SwitchClock = RESET;
+__IO uint32_t  ClockSourceStatus = 0;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+static void SystemClockHSI_Config(void);
+static void SystemClockHSE_Config(void);
+static void SystemClockMSI_Config(void);
+static void SwitchSystemClock(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+
+  /* Configure LED2 and LED3 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+
+  /* Initialize User push-button (SW1), will be used to trigger an interrupt each time it's pressed.*/
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+
+  /* Output SYSCLK  on MCO1 pin(PA.08) */
+  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    /* check if User push-button (SW1) has been pressed to switch clock config */
+    if (SwitchClock != RESET)
+    {
+      SwitchSystemClock();
+    }
+
+    /* Toggle LED2 in an infinite loop */
+    BSP_LED_Toggle(LED2);
+    HAL_Delay(100);
+  }
+
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  EXTI line detection callbacks.
+  * @param  GPIO_Pin: Specifies the pins connected EXTI line
+  * @retval None
+  */
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  if (GPIO_Pin == BUTTON_SW1_PIN)
+  {
+    SwitchClock = SET;
+  }
+}
+
+
+/**
+  * @brief  switch in system clock out of ISR context.
+  * @retval None
+  */
+static void SwitchSystemClock(void)
+{
+  if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)
+  {
+    /* PLL source is HSI oscillator */
+    /* Set SYSCLK frequency to 64000000 Hz, coming from the PLL which is clocked by MSI */
+    SystemClockMSI_Config();
+  }
+  else if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)
+  {
+    /* PLL source is HSE  oscillator */
+    /* Set SYSCLK frequency to 64000000 Hz, coming from the PLL which is clocked by HSI */
+    SystemClockHSI_Config();
+  }
+
+  else if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI)
+  {
+    /* PLL source is MSI oscillator */
+    /* Set SYSCLK frequency to 64000000 Hz, coming from the PLL which is clocked by HSE  */
+    SystemClockHSE_Config();
+  }
+
+  /* reset global variable */
+  SwitchClock = RESET;
+}
+
+/**
+  * @brief  Switch the PLL source from MSI to HSE , and select the PLL as SYSCLK
+  *         source.
+  *         The system Clock is configured as follows :
+  *            System Clock source            = PLL (HSE )
+  *            SYSCLK(Hz)                     = 64000000
+  *            HCLK(Hz)                       = 64000000
+  *            AHB Prescaler                  = 1
+  *            APB1 Prescaler                 = 1
+  *            APB2 Prescaler                 = 1
+  *            HSE Frequency(Hz)              = 6400000
+  *            PLL_M                          = 2
+  *            PLL_N                          = 16
+  *            PLL_P                          = 7
+  *            PLL_Q                          = 4
+  *            PLL_R                          = 4
+  *            Flash Latency(WS)              = 3
+  * @param  None
+  * @retval None
+  */
+static void SystemClockHSE_Config(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+
+  /* -1- Select MSI as system clock source to allow modification of the PLL configuration */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    /* Initialization Error */
+    Error_Handler();
+  }
+
+  /* -2- Enable HSE  Oscillator, select it as PLL source and finally activate the PLL */
+  RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState              = RCC_HSE_ON;
+
+  RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLM              = RCC_PLLM_DIV2;
+  RCC_OscInitStruct.PLL.PLLN              = 16;
+  RCC_OscInitStruct.PLL.PLLP              = RCC_PLLP_DIV7;
+  RCC_OscInitStruct.PLL.PLLQ              = RCC_PLLQ_DIV4;
+  RCC_OscInitStruct.PLL.PLLR              = RCC_PLLR_DIV4;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    /* Initialization Error */
+    Error_Handler();
+  }
+
+  /* -3- Select the PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+  RCC_ClkInitStruct.ClockType       = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource    = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider   = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider  = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider  = RCC_HCLK_DIV1;
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    /* Initialization Error */
+    Error_Handler();
+  }
+
+  /* -4- Optional: Disable MSI Oscillator (if the MSI is no more needed by the application)*/
+  RCC_OscInitStruct.OscillatorType  = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState        = RCC_MSI_OFF;
+  RCC_OscInitStruct.PLL.PLLState    = RCC_PLL_NONE;  /* No update on PLL */
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    /* Initialization Error */
+    Error_Handler();
+  }
+  ClockSourceStatus = 1;
+}
+
+/**
+  * @brief  Switch the PLL source from HSE  to HSI, and select the PLL as SYSCLK
+  *         source.
+  *         The system Clock is configured as follows :
+  *            System Clock source            = PLL (HSI)
+  *            SYSCLK(Hz)                     = 64000000
+  *            HCLK(Hz)                       = 64000000
+  *            AHB Prescaler                  = 1
+  *            APB1 Prescaler                 = 1
+  *            APB2 Prescaler                 = 1
+  *            HSI Frequency(Hz)              = 16000000
+  *            PLLM                           = 2
+  *            PLLN                           = 16
+  *            PLLP                           = 7
+  *            PLLQ                           = 4
+  *            PLLR                           = 2
+  *            Flash Latency(WS)              = 3
+  * @param  None
+  * @retval None
+  */
+static void SystemClockHSI_Config(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+
+  /* -1- Select HSE  as system clock source to allow modification of the PLL configuration */
+  RCC_ClkInitStruct.ClockType       = RCC_CLOCKTYPE_SYSCLK;
+  RCC_ClkInitStruct.SYSCLKSource    = RCC_SYSCLKSOURCE_HSE;
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    /* Initialization Error */
+    Error_Handler();
+  }
+
+  /* -2- Enable HSI Oscillator, select it as PLL source and finally activate the PLL */
+  RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM             = RCC_PLLM_DIV2;
+  RCC_OscInitStruct.PLL.PLLN             = 16;
+  RCC_OscInitStruct.PLL.PLLP             = RCC_PLLP_DIV7;
+  RCC_OscInitStruct.PLL.PLLQ             = RCC_PLLQ_DIV4;
+  RCC_OscInitStruct.PLL.PLLR             = RCC_PLLR_DIV2;
+
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    /* Initialization Error */
+    Error_Handler();
+  }
+
+  /* -3- Select the PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+  RCC_ClkInitStruct.ClockType       = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource    = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider   = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider  = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider  = RCC_HCLK_DIV1;
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    /* Initialization Error */
+    Error_Handler();
+  }
+
+  /* -4- Optional: Disable MSI Oscillator */
+  RCC_OscInitStruct.OscillatorType  = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState        = RCC_MSI_OFF;
+  RCC_OscInitStruct.PLL.PLLState    = RCC_PLL_NONE;  /* No update on PLL */
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    /* Initialization Error */
+    Error_Handler();
+  }
+
+  ClockSourceStatus = 2;
+
+}
+
+/** 
+  * @brief  Switch the PLL source from HSI to MSI, and select the PLL as SYSCLK
+  *         source.
+  *         The system Clock is configured as follow :
+  *            System Clock source            = PLL (MSI)
+  *            SYSCLK(Hz)                     = 64000000
+  *            HCLK(Hz)                       = 64000000
+  *            AHB Prescaler                  = 1
+  *            APB1 Prescaler                 = 1
+  *            APB2 Prescaler                 = 1
+  *            MSI Frequency(Hz)              = 4000000
+  *            PLL_M                          = 1
+  *            PLL_N                          = 32
+  *            PLL_P                          = 7
+  *            PLL_Q                          = 4
+  *            PLL_R                          = 2
+  *            Flash Latency(WS)              = 3
+  * @param  None
+  * @retval None
+  */
+static void SystemClockMSI_Config(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+
+  /* -1- Select HSI as system clock source to allow modification of the PLL configuration */
+  RCC_ClkInitStruct.ClockType       = RCC_CLOCKTYPE_SYSCLK;
+  RCC_ClkInitStruct.SYSCLKSource    = RCC_SYSCLKSOURCE_HSI;
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* -2- Enable MSI Oscillator, select it as PLL source and finally activate the PLL */
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState            = RCC_MSI_ON;
+  RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM            = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN            = 32;
+  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV7;
+  RCC_OscInitStruct.PLL.PLLQ            = RCC_PLLQ_DIV4;
+  RCC_OscInitStruct.PLL.PLLR            = RCC_PLLR_DIV2;
+
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* -3- Select the PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+  RCC_ClkInitStruct.ClockType       = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource    = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider   = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider  = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider  = RCC_HCLK_DIV1;
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* -4- Optional: Disable HSI Oscillator (if the HSI is no more needed by the application)*/
+  RCC_OscInitStruct.OscillatorType  = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState        = RCC_HSI_OFF;
+  RCC_OscInitStruct.PLL.PLLState    = RCC_PLL_NONE;  /* No update on PLL */
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  ClockSourceStatus = 3;
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  ClockSourceStatus = 0xE;
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  /* User can add his own implementation to report the HAL error return state */
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..26322c832
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RCC/RCC_ClockConfig/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..506d09ae2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Src/stm32wbxx_it.c
@@ -0,0 +1,129 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RCC/RCC_ClockConfig/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles external line 0 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/readme.txt b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/readme.txt
new file mode 100644
index 000000000..bf1a93cc6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RCC/RCC_ClockConfig/readme.txt
@@ -0,0 +1,98 @@
+/**
+  @page RCC_ClockConfig RCC Clock Config example
+
+  @verbatim
+  ******************************************************************************
+  * @file    RCC/RCC_ClockConfig/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the RCC Clock Config example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+Configuration of the system clock (SYSCLK) and modification of the clock settings in Run mode, using the RCC HAL API.
+
+In this example, after startup SYSCLK is configured to the max frequency using the PLL with
+MSI as clock source, the User push-button (SW1) (connected to External line 0) will be
+used to change the PLL source:
+- from HSE to HSI
+- from HSI to MSI
+- from MSI to HSE
+
+Each time the User push-button (SW1) is pressed External line 0 interrupt is generated and in the ISR
+the PLL oscillator source is checked using __HAL_RCC_GET_PLL_OSCSOURCE() macro:
+
+- If the HSE oscillator is selected as PLL source, the following steps will be followed to switch
+   the PLL source to HSI oscillator:
+     a- Switch the system clock source to HSE to allow modification of the PLL configuration
+     b- Enable HSI Oscillator, select it as PLL source and finally activate the PLL
+     c- Select the PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+     d- Disable the HSE oscillator (optional, if the HSE is no more needed by the application)
+
+- If the MSI oscillator is selected as PLL source, the following steps will be followed to switch
+   the PLL source to HSE oscillator:
+     a- Switch the system clock source to MSI to allow modification of the PLL configuration
+     b- Enable HSE Oscillator, select it as PLL source and finally activate the PLL
+     c- Select the PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+     d- Disable the MSI oscillator (optional, if the MSI is no more needed by the application)
+
+- If the HSI oscillator is selected as PLL source, the following steps will be followed to switch
+   the PLL source to MSI oscillator:
+     a- Switch the system clock source to HSI to allow modification of the PLL configuration
+     b- Enable MSI Oscillator, select it as PLL source and finally activate the PLL
+     c- Select the PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+     d- Disable the HSI oscillator (optional, if the HSI is no more needed by the application)
+
+
+LED2 is toggled with a timing defined by the HAL_Delay() API.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note The application need to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+RCC, System, Clock Configuration, HSE bypass mode, HSI, System clock, Oscillator, PLL
+
+@par Directory contents
+
+  - RCC/RCC_ClockConfig/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - RCC/RCC_ClockConfig/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - RCC/RCC_ClockConfig/Inc/main.h                  Header for main.c module
+  - RCC/RCC_ClockConfig/Src/stm32wbxx_it.c          Interrupt handlers
+  - RCC/RCC_ClockConfig/Src/main.c                  Main program
+  - RCC/RCC_ClockConfig/Src/system_stm32wbxx.c      STM32WBxx system source file
+  - RCC/RCC_ClockConfig/Src/stm32wbxx_hal_msp.c   HAL MSP module
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35xx devices.
+
+  - This example has been tested with NUCLEO-WB35CE
+    board and can be easily tailored to any other supported device
+    and development board.
+
+@par How to use it ?
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/.extSettings b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/Project.eww
new file mode 100644
index 000000000..21727f757
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\RNG_MultiRNG.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/RNG_MultiRNG.ewd b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/RNG_MultiRNG.ewd
new file mode 100644
index 000000000..2dc682be4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/RNG_MultiRNG.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		RNG_MultiRNG
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/RNG_MultiRNG.ewp b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/RNG_MultiRNG.ewp
new file mode 100644
index 000000000..3c933c89b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/RNG_MultiRNG.ewp
@@ -0,0 +1,1122 @@
+
+
+  3
+  
+    RNG_MultiRNG
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rng.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Inc/main.h
new file mode 100644
index 000000000..319beeb3e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Inc/main.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RNG/RNG_MultiRNG/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..e8af380db
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+#define HAL_RNG_MODULE_ENABLED
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..e344234d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Inc/stm32wbxx_it.h
@@ -0,0 +1,66 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RNG/RNG_MultiRNG/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+void EXTI0_IRQHandler(void);
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/MDK-ARM/RNG_MultiRNG.uvoptx b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/MDK-ARM/RNG_MultiRNG.uvoptx
new file mode 100644
index 000000000..d07621c8f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/MDK-ARM/RNG_MultiRNG.uvoptx
@@ -0,0 +1,536 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    RNG_MultiRNG
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          ARMRTXEVENTFLAGS
+          -L70 -Z18 -C0 -M0 -T1
+        
+        
+          0
+          DLGTARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          
+        
+        
+          0
+          DLGUARM
+          (105=-1,-1,-1,-1,0)
+        
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U0667FF303337554E43181419 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        
+          0
+          1
+          aRandom32bit
+        
+      
+      
+        0
+      
+      
+        0
+        1
+        1
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      2
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rng.c
+      stm32wbxx_hal_rng.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      5
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      5
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      5
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      5
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      5
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      5
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      5
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      5
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      5
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      5
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      5
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/MDK-ARM/RNG_MultiRNG.uvprojx b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/MDK-ARM/RNG_MultiRNG.uvprojx
new file mode 100644
index 000000000..80942823b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/MDK-ARM/RNG_MultiRNG.uvprojx
@@ -0,0 +1,547 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      RNG_MultiRNG
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          RNG_MultiRNG\
+          RNG_MultiRNG
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_rng.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rng.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/RNG_MultiRNG.ioc b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/RNG_MultiRNG.ioc
new file mode 100644
index 000000000..9846af2cf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/RNG_MultiRNG.ioc
@@ -0,0 +1,110 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=RNG
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_RNG_VS_RNG
+Mcu.Pin1=VP_SYS_VS_Systick
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=RNG_MultiRNG.ioc
+ProjectManager.ProjectName=RNG_MultiRNG
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_RNG_VS_RNG.Mode=RNG_Activate
+VP_RNG_VS_RNG.Signal=RNG_VS_RNG
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..18b6f73eb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/.cproject
@@ -0,0 +1,170 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/.project
new file mode 100644
index 000000000..5a3670f80
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/.project
@@ -0,0 +1,150 @@
+
+
+	RNG_MultiRNG
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			RNG_MultiRNG.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/RNG_MultiRNG.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rng.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rng.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/.settings/language.settings.xml b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/.settings/language.settings.xml
new file mode 100644
index 000000000..28038a915
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/.settings/language.settings.xml
@@ -0,0 +1,27 @@
+
+
+	
+		
+			
+			
+			
+			
+			
+				
+				
+			
+		
+	
+	
+		
+			
+			
+			
+			
+			
+				
+				
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Src/main.c
new file mode 100644
index 000000000..0acb40943
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Src/main.c
@@ -0,0 +1,276 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RNG/RNG_MultiRNG/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use the RNG HAL API
+  *          to generate 32-bit long random numbers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+RNG_HandleTypeDef hrng;
+
+/* USER CODE BEGIN PV */
+
+/* Used for storing 8 Random 32bit Numbers */
+uint32_t aRandom32bit[8];
+__IO uint8_t    ubUserButtonClickEvent = RESET;  /* Event detection: Set after User Button interrupt */
+__IO uint32_t    RNGStatus = 0;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_RNG_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  uint32_t counter = 0;
+
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* Initialize LED Error on board */
+  BSP_LED_Init(LED3);
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_RNG_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Configure User push-button (SW1) in Interrupt mode */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+
+  while (1)
+  {
+
+    /* Wait for event on push button to perform following actions */
+    while ((ubUserButtonClickEvent) == RESET)
+    {
+      __NOP();
+    }
+    /* Reset variable for next loop iteration */
+    ubUserButtonClickEvent = RESET;
+
+    /* Generate eight 32-bit long random numbers */
+    for (counter = 0; counter < 8; counter++)
+    {
+      if (HAL_RNG_GenerateRandomNumber(&hrng, &aRandom32bit[counter]) != HAL_OK)
+      {
+        /* Random number generation error */
+        Error_Handler();
+      }
+    }
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief RNG Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RNG_Init(void)
+{
+
+  /* USER CODE BEGIN RNG_Init 0 */
+
+  /* USER CODE END RNG_Init 0 */
+
+  /* USER CODE BEGIN RNG_Init 1 */
+
+  /* USER CODE END RNG_Init 1 */
+  hrng.Instance = RNG;
+  if (HAL_RNG_Init(&hrng) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN RNG_Init 2 */
+
+  /* USER CODE END RNG_Init 2 */
+
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief EXTI line detection callbacks
+  * @param GPIO_Pin: Specifies the pins connected EXTI line
+  * @retval None
+  */
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  if (GPIO_Pin == BUTTON_SW1_PIN)
+  {
+    /* Set variable to report push button event to main program */
+    ubUserButtonClickEvent = SET;
+    RNGStatus = 1;
+  }
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  RNGStatus = 0xE;
+  while (1)
+  {
+    /* Toggle LED3 */
+    BSP_LED_Toggle(LED3);
+    HAL_Delay(500);
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..70d5eea80
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,153 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RNG/RNG_MultiRNG/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief RNG MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrng: RNG handle pointer
+* @retval None
+*/
+void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng)
+{
+  if(hrng->Instance==RNG)
+  {
+  /* USER CODE BEGIN RNG_MspInit 0 */
+
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct = {0};
+
+    /* Enable HSI48 Oscillator for USB/RNG */
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
+    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+    RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+    {
+      /* Initialization Error */
+      while (1);
+    }
+
+    /* Select HSI48 from USB clock as RNG clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG;
+    PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_CLK48;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct))
+    {
+      /* Initialization Error */
+      while (1);
+    }
+
+  /* USER CODE END RNG_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_RNG_CLK_ENABLE();
+  /* USER CODE BEGIN RNG_MspInit 1 */
+
+  /* USER CODE END RNG_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RNG MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrng: RNG handle pointer
+* @retval None
+*/
+void HAL_RNG_MspDeInit(RNG_HandleTypeDef* hrng)
+{
+  if(hrng->Instance==RNG)
+  {
+  /* USER CODE BEGIN RNG_MspDeInit 0 */
+
+  /* USER CODE END RNG_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RNG_CLK_DISABLE();
+  /* USER CODE BEGIN RNG_MspDeInit 1 */
+
+    /* Enable RNG reset state */
+    __HAL_RCC_RNG_FORCE_RESET();
+
+    /* Release RNG from reset state */
+    __HAL_RCC_RNG_RELEASE_RESET();
+
+  /* USER CODE END RNG_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..cb555b953
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Src/stm32wbxx_it.c
@@ -0,0 +1,129 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RNG/RNG_MultiRNG/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles external line 0 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/readme.txt b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/readme.txt
new file mode 100644
index 000000000..0730038a1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RNG/RNG_MultiRNG/readme.txt
@@ -0,0 +1,75 @@
+/**
+  @page RNG_MultiRNG Multiple Random Numbers Generator example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    RNG/RNG_MultiRNG/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of multiple random numbers generation example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+Configuration of the RNG using the HAL API. This example uses the RNG to generate 32-bit long random numbers.
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz.
+
+The RNG peripheral configuration is ensured by the HAL_RNG_Init() function.
+The latter is calling the HAL_RNG_MspInit() function which implements
+the configuration of the needed RNG resources according to the used hardware (CLOCK, 
+GPIO, DMA and NVIC). You may update this function to change RNG configuration.
+
+After startup, user is asked to press User push-button (SW1).
+The 8-entry array aRandom32bit[] is filled up by 32-bit long random numbers 
+at each User push-button (SW1) press.
+
+ 
+The random numbers can be displayed on the debugger in aRandom32bit variable.
+
+In case of error, LED3 is toggling at a frequency of 1Hz.
+
+@par Keywords
+
+Analog, RNG, Random, FIPS PUB 140-2, Analog Random number generator, Entropy, Period
+
+@par Directory contents 
+
+  - RNG/RNG_MultiRNG/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - RNG/RNG_MultiRNG/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - RNG/RNG_MultiRNG/Inc/main.h                  Header for main.c module
+  - RNG/RNG_MultiRNG/Src/stm32wbxx_it.c          Interrupt handlers
+  - RNG/RNG_MultiRNG/Src/main.c                  Main program
+  - RNG/RNG_MultiRNG/Src/stm32wbxx_hal_msp.c     HAL MSP module 
+  - RNG/RNG_MultiRNG/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+     
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+  
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following:
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+ 
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
+ 
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/.extSettings b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/Project.eww
new file mode 100644
index 000000000..aa4c4e04d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\RTC_Alarm.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/RTC_Alarm.ewd b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/RTC_Alarm.ewd
new file mode 100644
index 000000000..efe80312d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/RTC_Alarm.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		RTC_Alarm
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/RTC_Alarm.ewp b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/RTC_Alarm.ewp
new file mode 100644
index 000000000..ebe405f4f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/RTC_Alarm.ewp
@@ -0,0 +1,1125 @@
+
+
+  3
+  
+    RTC_Alarm
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Inc/main.h
new file mode 100644
index 000000000..94ab612c7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Inc/main.h
@@ -0,0 +1,86 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RTC/RTC_Alarm/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+#include 
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* Defines related to Clock configuration */
+/* Uncomment to enable the adaquate Clock Source */
+#define RTC_CLOCK_SOURCE_LSI
+/*#define RTC_CLOCK_SOURCE_LSE*/
+
+#ifdef RTC_CLOCK_SOURCE_LSI
+#define RTC_ASYNCH_PREDIV    0x7F
+#define RTC_SYNCH_PREDIV     0x0FF
+#endif
+
+#ifdef RTC_CLOCK_SOURCE_LSE
+#define RTC_ASYNCH_PREDIV  0x7F
+#define RTC_SYNCH_PREDIV   0x00FF
+#endif
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..03d5d81d5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..00250a7dc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Inc/stm32wbxx_it.h
@@ -0,0 +1,65 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RTC/RTC_Alarm/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void RTC_Alarm_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/MDK-ARM/RTC_Alarm.uvoptx b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/MDK-ARM/RTC_Alarm.uvoptx
new file mode 100644
index 000000000..c6fbbb420
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/MDK-ARM/RTC_Alarm.uvoptx
@@ -0,0 +1,521 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    RTC_Alarm
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+      stm32wbxx_hal_rtc.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+      stm32wbxx_hal_rtc_ex.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      24
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/MDK-ARM/RTC_Alarm.uvprojx b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/MDK-ARM/RTC_Alarm.uvprojx
new file mode 100644
index 000000000..c5fb547e9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/MDK-ARM/RTC_Alarm.uvprojx
@@ -0,0 +1,551 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      RTC_Alarm
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          RTC_Alarm\
+          RTC_Alarm
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_rtc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+            
+            
+              stm32wbxx_hal_rtc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/RTC_Alarm.ioc b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/RTC_Alarm.ioc
new file mode 100644
index 000000000..fba3dd32b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/RTC_Alarm.ioc
@@ -0,0 +1,147 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=RTC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_RTC_VS_RTC_Activate
+Mcu.Pin1=VP_RTC_VS_RTC_Calendar
+Mcu.Pin2=VP_RTC_VS_RTC_Alarm_A_Intern
+Mcu.Pin3=VP_SYS_VS_Systick
+Mcu.PinsNb=4
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.RTC_Alarm_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=RTC_Alarm.ioc
+ProjectManager.ProjectName=RTC_Alarm
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_RTC_Init-RTC-false-HAL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+RTC.Alarm-Alarm\ A=RTC_ALARM_A
+RTC.AlarmDateWeekDay=RTC_WEEKDAY_MONDAY
+RTC.AlarmDateWeekDay-Alarm\ A=RTC_WEEKDAY_MONDAY
+RTC.AlarmDateWeekDaySel=RTC_ALARMDATEWEEKDAYSEL_WEEKDAY
+RTC.AlarmDateWeekDaySel-Alarm\ A=RTC_ALARMDATEWEEKDAYSEL_WEEKDAY
+RTC.AlarmSubSecondMask=RTC_ALARMSUBSECONDMASK_NONE
+RTC.AlarmSubSecondMask-Alarm\ A=RTC_ALARMSUBSECONDMASK_ALL
+RTC.AsynchPrediv=RTC_ASYNCH_PREDIV
+RTC.Date=18
+RTC.DayLightSaving=RTC_DAYLIGHTSAVING_NONE
+RTC.Format=RTC_FORMAT_BCD
+RTC.HourFormat=RTC_HOURFORMAT_24
+RTC.Hours=2
+RTC.Hours_A=2
+RTC.Hours_A-Alarm\ A=0
+RTC.IPParameters=HourFormat,AsynchPrediv,SynchPrediv,Format,Hours,Minutes,Seconds,DayLightSaving,StoreOperation,WeekDay,Month,Date,Year,Hours_A-Alarm A,Minutes_A-Alarm A,Seconds_A-Alarm A,SubSeconds_A-Alarm A,AlarmSubSecondMask-Alarm A,AlarmDateWeekDaySel-Alarm A,AlarmDateWeekDay-Alarm A,Alarm-Alarm A,Weekday,Hours_A,Minutes_A,Seconds_A,SubSeconds_A,AlarmSubSecondMask,AlarmDateWeekDaySel,AlarmDateWeekDay
+RTC.IPParametersWithoutCheck=AsynchPrediv,SynchPrediv
+RTC.Minutes=20
+RTC.Minutes_A=20
+RTC.Minutes_A-Alarm\ A=0
+RTC.Month=RTC_MONTH_FEBRUARY
+RTC.Seconds=0
+RTC.Seconds_A=30
+RTC.Seconds_A-Alarm\ A=0
+RTC.StoreOperation=RTC_STOREOPERATION_RESET
+RTC.SubSeconds_A=56
+RTC.SubSeconds_A-Alarm\ A=0
+RTC.SynchPrediv=RTC_SYNCH_PREDIV
+RTC.WeekDay=RTC_WEEKDAY_MONDAY
+RTC.Weekday=RTC_WEEKDAY_TUESDAY
+RTC.Year=14
+VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
+VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
+VP_RTC_VS_RTC_Alarm_A_Intern.Mode=Alarm A
+VP_RTC_VS_RTC_Alarm_A_Intern.Signal=RTC_VS_RTC_Alarm_A_Intern
+VP_RTC_VS_RTC_Calendar.Mode=RTC_Calendar
+VP_RTC_VS_RTC_Calendar.Signal=RTC_VS_RTC_Calendar
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..f788c9f75
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/.project
new file mode 100644
index 000000000..e033c98ab
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/.project
@@ -0,0 +1,155 @@
+
+
+	RTC_Alarm
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			RTC_Alarm.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/RTC_Alarm.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Src/main.c
new file mode 100644
index 000000000..4ddd6cdc1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Src/main.c
@@ -0,0 +1,320 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RTC/RTC_Alarm/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use STM32WBxx RTC HAL API to configure
+  *          Time and Date.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+RTC_HandleTypeDef hrtc;
+
+/* USER CODE BEGIN PV */
+/* Buffer used for displaying Time */
+uint8_t aShowTime[16] = "hh:ms:ss";
+__IO uint32_t RTCStatus = 0;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_RTC_Init(void);
+/* USER CODE BEGIN PFP */
+static void RTC_TimeShow(uint8_t *showtime);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+  /* Configure LED2 and LED3 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_RTC_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  RTCStatus = 1;
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    /* Display the updated Time */
+    RTC_TimeShow(aShowTime);
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief RTC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RTC_Init(void)
+{
+
+  /* USER CODE BEGIN RTC_Init 0 */
+
+  /* USER CODE END RTC_Init 0 */
+
+  RTC_TimeTypeDef sTime = {0};
+  RTC_DateTypeDef sDate = {0};
+  RTC_AlarmTypeDef sAlarm = {0};
+
+  /* USER CODE BEGIN RTC_Init 1 */
+
+  /* USER CODE END RTC_Init 1 */
+  /** Initialize RTC Only 
+  */
+  hrtc.Instance = RTC;
+  hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
+  hrtc.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
+  hrtc.Init.SynchPrediv = RTC_SYNCH_PREDIV;
+  if (HAL_RTC_Init(&hrtc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* USER CODE BEGIN Check_RTC_BKUP */
+    
+  /* USER CODE END Check_RTC_BKUP */
+
+  /** Initialize RTC and set the Time and Date 
+  */
+  sTime.Hours = 0x2;
+  sTime.Minutes = 0x20;
+  sTime.Seconds = 0x0;
+  sTime.SubSeconds = 0x0;
+  sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
+  sTime.StoreOperation = RTC_STOREOPERATION_RESET;
+  if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BCD) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sDate.WeekDay = RTC_WEEKDAY_MONDAY;
+  sDate.Month = RTC_MONTH_FEBRUARY;
+  sDate.Date = 0x18;
+  sDate.Year = 0x14;
+  if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BCD) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Enable the Alarm A 
+  */
+  sAlarm.AlarmTime.Hours = 0x2;
+  sAlarm.AlarmTime.Minutes = 0x20;
+  sAlarm.AlarmTime.Seconds = 0x30;
+  sAlarm.AlarmTime.SubSeconds = 0x56;
+  sAlarm.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
+  sAlarm.AlarmTime.StoreOperation = RTC_STOREOPERATION_RESET;
+  sAlarm.AlarmMask = RTC_ALARMMASK_NONE;
+  sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDMASK_ALL;
+  sAlarm.AlarmDateWeekDaySel = RTC_ALARMDATEWEEKDAYSEL_WEEKDAY;
+  sAlarm.AlarmDateWeekDay = RTC_WEEKDAY_MONDAY;
+  sAlarm.Alarm = RTC_ALARM_A;
+  if (HAL_RTC_SetAlarm_IT(&hrtc, &sAlarm, RTC_FORMAT_BCD) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN RTC_Init 2 */
+
+  /* USER CODE END RTC_Init 2 */
+
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Alarm callback
+  * @param  hrtc : RTC handle
+  * @retval None
+  */
+void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+{
+
+  /* Turn LED2 on: Alarm generation */
+  BSP_LED_On(LED2);
+
+
+}
+
+/**
+  * @brief  Display the current time.
+  * @param  showtime : pointer to buffer
+  * @retval None
+  */
+static void RTC_TimeShow(uint8_t *showtime)
+{
+  RTC_DateTypeDef sdatestructureget;
+  RTC_TimeTypeDef stimestructureget;
+
+  /* Get the RTC current Time */
+  HAL_RTC_GetTime(&hrtc, &stimestructureget, RTC_FORMAT_BIN);
+  /* Get the RTC current Date */
+  HAL_RTC_GetDate(&hrtc, &sdatestructureget, RTC_FORMAT_BIN);
+  /* Display time Format : hh:mm:ss */
+  sprintf((char *)showtime, "%02d:%02d:%02d", stimestructureget.Hours, stimestructureget.Minutes, stimestructureget.Seconds);
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  RTCStatus = 0xE;
+  while (1)
+  {
+    /* Toggle LED3 with a period of one second */
+    BSP_LED_Toggle(LED3);
+    HAL_Delay(1000);
+
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..11ad442b0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,191 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RTC/RTC_Alarm/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+#ifdef RTC_CLOCK_SOURCE_LSE
+static uint32_t RtcClockSource = RCC_RTCCLKSOURCE_LSE;
+#elif defined (RTC_CLOCK_SOURCE_LSI)
+static uint32_t RtcClockSource = RCC_RTCCLKSOURCE_LSI;
+#endif
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief RTC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspInit 0 */
+    RCC_OscInitTypeDef        RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct = {0};
+
+    /* Enables the PWR Clock and Enables access to the backup domain */
+    /* To enable access on RTC registers */
+    HAL_PWR_EnableBkUpAccess();
+    /* Get RTC clock configuration */
+    HAL_RCCEx_GetPeriphCLKConfig(&PeriphClkInitStruct);
+
+    /*In case of RTC clock already enable, make sure it's the good one */
+    if (PeriphClkInitStruct.RTCClockSelection == RtcClockSource)
+    {
+      /* Do nothing */
+    }
+    else
+    {
+      PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+
+      /* If selected source was previously the opposite source clock, first select none*/
+      if (PeriphClkInitStruct.RTCClockSelection != RCC_RTCCLKSOURCE_NONE)
+      {
+        PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_NONE;
+        if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+        {
+          Error_Handler();
+        }
+      }
+      /* Configure LSE/LSI as RTC clock source */
+#ifdef RTC_CLOCK_SOURCE_LSE
+      RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_LSE;
+      RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+      RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+      RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
+#elif defined (RTC_CLOCK_SOURCE_LSI)
+      RCC_OscInitStruct.OscillatorType =  RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_LSE;
+      RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+      RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+      RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
+#else
+#error Please select the RTC Clock source inside the main.h file
+#endif /*RTC_CLOCK_SOURCE_LSE*/
+
+      if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+      {
+        Error_Handler();
+      }
+
+      PeriphClkInitStruct.RTCClockSelection = RtcClockSource;
+      if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+      {
+        Error_Handler();
+      }
+    }
+
+  /* USER CODE END RTC_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_RTC_ENABLE();
+    __HAL_RCC_RTCAPB_CLK_ENABLE();
+    /* RTC interrupt Init */
+    HAL_NVIC_SetPriority(RTC_Alarm_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
+  /* USER CODE BEGIN RTC_MspInit 1 */
+
+
+  /* USER CODE END RTC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspDeInit 0 */
+
+  /* USER CODE END RTC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RTC_DISABLE();
+    __HAL_RCC_RTCAPB_CLK_DISABLE();
+
+    /* RTC interrupt DeInit */
+    HAL_NVIC_DisableIRQ(RTC_Alarm_IRQn);
+  /* USER CODE BEGIN RTC_MspDeInit 1 */
+
+  /* USER CODE END RTC_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..771677f91
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Src/stm32wbxx_it.c
@@ -0,0 +1,135 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RTC/RTC_Alarm/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern RTC_HandleTypeDef hrtc;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles RTC A and B alarm interrupt through EXTI line 17.
+  */
+void RTC_Alarm_IRQHandler(void)
+{
+  /* USER CODE BEGIN RTC_Alarm_IRQn 0 */
+
+  /* USER CODE END RTC_Alarm_IRQn 0 */
+  HAL_RTC_AlarmIRQHandler(&hrtc);
+  /* USER CODE BEGIN RTC_Alarm_IRQn 1 */
+
+  /* USER CODE END RTC_Alarm_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/readme.txt b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/readme.txt
new file mode 100644
index 000000000..f376ff2e1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Alarm/readme.txt
@@ -0,0 +1,97 @@
+/**
+  @page RTC_Alarm RTC Alarm Example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    RTC/RTC_Alarm/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the RTC Alarm example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+Configuration and generation of an RTC alarm using the RTC HAL API.
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz.
+The RTC peripheral configuration is ensured by the HAL_RTC_Init() function.
+This later is calling the HAL_RTC_MspInit()function which core is implementing
+the configuration of the needed RTC resources according to the used hardware (CLOCK, 
+PWR, RTC clock source and BackUp). You may update this function to change RTC configuration.
+
+@note LSI oscillator clock is used as RTC clock source by default.
+      The user can use also LSE as RTC clock source. The user uncomment the adequate 
+      line on the main.h file.
+      @code
+        #define RTC_CLOCK_SOURCE_LSI  
+        /* #define RTC_CLOCK_SOURCE_LSE */
+      @endcode
+      LSI oscillator clock is delivered by a 32 kHz RC.
+      LSE (when available on board) is delivered by a 32.768 kHz crystal.
+
+HAL_RTC_SetDate() and HAL_RTC_SetTime() functions are called to initialize the 
+time and the date.
+HAL_RTC_SetAlarm_IT() function is then called to initialize the Alarm feature with 
+interrupt mode.
+
+In this example, the Time is set to 02:20:00 and the Alarm must be generated after 
+30 seconds on 02:20:30.
+
+LED2 is turned ON when the RTC Alarm is generated correctly.
+The current time is updated and displayed on the debugger in aShowTime variable.
+In case of error, LED3 is toggled with a period of one second.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application need to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+System, RTC, Alarm, wakeup timer, Backup domain, Counter, LSE, LSI
+
+@par Directory contents 
+
+  - RTC/RTC_Alarm/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - RTC/RTC_Alarm/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - RTC/RTC_Alarm/Inc/main.h                        Header for main.c module  
+  - RTC/RTC_Alarm/Src/stm32wbxx_it.c          Interrupt handlers
+  - RTC/RTC_Alarm/Src/main.c                        Main program
+  - RTC/RTC_Alarm/Src/stm32wbxx_hal_msp.c     HAL MSP module
+  - RTC/RTC_Alarm/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE 
+    board and can be easily tailored to any other supported device 
+    and development board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
+ 
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/.extSettings b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/Project.eww
new file mode 100644
index 000000000..263d427ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\RTC_Tamper.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/RTC_Tamper.ewd b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/RTC_Tamper.ewd
new file mode 100644
index 000000000..3b301cb1b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/RTC_Tamper.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		RTC_Tamper
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/RTC_Tamper.ewp b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/RTC_Tamper.ewp
new file mode 100644
index 000000000..350fa67c3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/RTC_Tamper.ewp
@@ -0,0 +1,1125 @@
+
+
+  3
+  
+    RTC_Tamper
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Inc/main.h
new file mode 100644
index 000000000..c15d52f48
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Inc/main.h
@@ -0,0 +1,86 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RTC/RTC_Tamper/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+#include 
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+#define BACKUP_COUNT RTC_BKP_NUMBER
+
+/* Defines related to Clock configuration */
+/* Uncomment to enable the adaquate Clock Source */
+#define RTC_CLOCK_SOURCE_LSI
+//#define RTC_CLOCK_SOURCE_LSE
+#ifdef RTC_CLOCK_SOURCE_LSI
+#define RTC_ASYNCH_PREDIV    0x7F
+#define RTC_SYNCH_PREDIV     0xFF
+#endif
+
+#ifdef RTC_CLOCK_SOURCE_LSE
+#define RTC_ASYNCH_PREDIV  0x7F
+#define RTC_SYNCH_PREDIV   0x00FF
+#endif
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..03d5d81d5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..90535dc61
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Inc/stm32wbxx_it.h
@@ -0,0 +1,65 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RTC/RTC_Tamper/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void TAMP_STAMP_LSECSS_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/MDK-ARM/RTC_Tamper.uvoptx b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/MDK-ARM/RTC_Tamper.uvoptx
new file mode 100644
index 000000000..32b52d638
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/MDK-ARM/RTC_Tamper.uvoptx
@@ -0,0 +1,521 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    RTC_Tamper
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      2
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+      stm32wbxx_hal_rtc.c
+      0
+      0
+    
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+      stm32wbxx_hal_rtc_ex.c
+      0
+      0
+    
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      5
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      5
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      5
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      5
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      5
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      5
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      5
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      5
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      5
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      5
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      5
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      5
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      24
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/MDK-ARM/RTC_Tamper.uvprojx b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/MDK-ARM/RTC_Tamper.uvprojx
new file mode 100644
index 000000000..423d24df6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/MDK-ARM/RTC_Tamper.uvprojx
@@ -0,0 +1,552 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      RTC_Tamper
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          RTC_Tamper\
+          RTC_Tamper
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_rtc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+            
+            
+              stm32wbxx_hal_rtc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..71fef549f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00040000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20008000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/RTC_Tamper.ioc b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/RTC_Tamper.ioc
new file mode 100644
index 000000000..41b099ef4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/RTC_Tamper.ioc
@@ -0,0 +1,125 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=RTC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA0
+Mcu.Pin1=VP_RTC_VS_RTC_Activate
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.TAMP_STAMP_LSECSS_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PA0.Locked=true
+PA0.Mode=Tamper 2 enabled - Input Enabled to TAMP2
+PA0.Signal=RTC_TAMP2
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=RTC_Tamper.ioc
+ProjectManager.ProjectName=RTC_Tamper
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+RTC.AsynchPrediv=RTC_ASYNCH_PREDIV
+RTC.Filter=RTC_TAMPERFILTER_DISABLE
+RTC.HourFormat=RTC_HOURFORMAT_24
+RTC.IPParameters=HourFormat,AsynchPrediv,SynchPrediv,Filter,SamplingFrequency,PrechargeDuration,TamperPullUp,TimeStampOnTamperDetection
+RTC.IPParametersWithoutCheck=AsynchPrediv,SynchPrediv
+RTC.PrechargeDuration=RTC_TAMPERPRECHARGEDURATION_1RTCCLK
+RTC.SamplingFrequency=RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768
+RTC.SynchPrediv=RTC_SYNCH_PREDIV
+RTC.TamperPullUp=RTC_TAMPER_PULLUP_ENABLE
+RTC.TimeStampOnTamperDetection=RTC_TIMESTAMPONTAMPERDETECTION_ENABLE
+VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
+VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..e0afc48e3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/.cproject
@@ -0,0 +1,170 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/.project
new file mode 100644
index 000000000..1c6e34d31
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/.project
@@ -0,0 +1,155 @@
+
+
+	RTC_Tamper
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			RTC_Tamper.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/RTC_Tamper.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..eea98ff9c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb35xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB35xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..4ec95844d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,159 @@
+/**
+ ******************************************************************************
+ * @file      syscalls.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..4665417ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,58 @@
+/**
+ ******************************************************************************
+ * @file      sysmem.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System Memory calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..349b5224d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 256K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20008000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Src/main.c
new file mode 100644
index 000000000..f171f779f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Src/main.c
@@ -0,0 +1,355 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RTC/RTC_Tamper/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use STM32WBxx RTC HAL API to write/read
+  *          data to/from RTC Backup data registers and demonstrates the Tamper
+  *          detection feature.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+RTC_HandleTypeDef hrtc;
+
+/* USER CODE BEGIN PV */
+
+__IO FlagStatus TamperStatus;
+__IO uint8_t RTCStatus = 0;
+
+/* Backup registers table */
+uint32_t aBKPDataReg[BACKUP_COUNT] =
+{
+  RTC_BKP_DR0,  RTC_BKP_DR1,  RTC_BKP_DR2,
+  RTC_BKP_DR3,  RTC_BKP_DR4,  RTC_BKP_DR5,
+  RTC_BKP_DR6,  RTC_BKP_DR7,  RTC_BKP_DR8,
+  RTC_BKP_DR9,  RTC_BKP_DR10, RTC_BKP_DR11,
+  RTC_BKP_DR12, RTC_BKP_DR13, RTC_BKP_DR14,
+  RTC_BKP_DR15, RTC_BKP_DR16, RTC_BKP_DR17,
+  RTC_BKP_DR18, RTC_BKP_DR19
+};
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_RTC_Init(void);
+/* USER CODE BEGIN PFP */
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  uint32_t index = 0;
+
+
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+  /* Configure LED2, LED3, LED1 */
+  BSP_LED_Init(LED1);
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* Configure User push-button (SW1) button */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_GPIO);
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_RTC_Init();
+  /* USER CODE BEGIN 2 */
+  /* Clear the Tamper interrupt pending bit */
+  __HAL_RTC_TAMPER_CLEAR_FLAG(&hrtc, RTC_FLAG_TAMP2F);
+  /* Write Data on the Back Up registers */
+  for (index = 0; index < BACKUP_COUNT; index++)
+  {
+    HAL_RTCEx_BKUPWrite(&hrtc, aBKPDataReg[index], 0xDF59 + (index * 0x5A));
+  }
+
+  /* Check Data is stored on the Back Up registers */
+  for (index = 0; index < BACKUP_COUNT; index++)
+  {
+    if (HAL_RTCEx_BKUPRead(&hrtc, aBKPDataReg[index]) != (0xDF59 + (index * 0x5A)))
+    {
+      Error_Handler();
+    }
+  }
+
+  /* Reset flag after writing of backup register in order to wait for new button press */
+  TamperStatus = RESET;
+
+  /* Turn LED1 on */
+  BSP_LED_On(LED1);
+
+  /* Wait for the tamper button is pressed */
+  while (TamperStatus != SET)
+  {
+    /* Toggle LED2 with a period of 1s */
+    BSP_LED_Toggle(LED2);
+
+    /* Delay */
+    HAL_Delay(1000);
+  }
+
+  /* Deactivate the tamper  */
+  HAL_RTCEx_DeactivateTamper(&hrtc, RTC_TAMPER_2);
+
+  /* Check Data is cleared on the Back Up registers */
+  for (index = 0; index < BACKUP_COUNT; index++)
+  {
+    if (HAL_RTCEx_BKUPRead(&hrtc, aBKPDataReg[index]) != 0x00)
+    {
+      Error_Handler();
+    }
+  }
+  
+   /* Turn LED1 off */
+   BSP_LED_Off(LED1);
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    /* Turn LED2 toggles */
+    BSP_LED_Toggle(LED2);
+
+    /* Delay */
+    HAL_Delay(100);
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief RTC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RTC_Init(void)
+{
+
+  /* USER CODE BEGIN RTC_Init 0 */
+
+  /* USER CODE END RTC_Init 0 */
+
+  RTC_TamperTypeDef sTamper = {0};
+
+  /* USER CODE BEGIN RTC_Init 1 */
+
+  /* USER CODE END RTC_Init 1 */
+  /** Initialize RTC Only 
+  */
+  hrtc.Instance = RTC;
+  hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
+  hrtc.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
+  hrtc.Init.SynchPrediv = RTC_SYNCH_PREDIV;
+  if (HAL_RTC_Init(&hrtc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Enable the RTC Tamper 2 
+  */
+  sTamper.Tamper = RTC_TAMPER_2;
+  sTamper.Interrupt = RTC_TAMPER2_INTERRUPT;
+  sTamper.Trigger = RTC_TAMPERTRIGGER_RISINGEDGE;
+  sTamper.NoErase = RTC_TAMPER_ERASE_BACKUP_ENABLE;
+  sTamper.MaskFlag = RTC_TAMPERMASK_FLAG_DISABLE;
+  sTamper.Filter = RTC_TAMPERFILTER_DISABLE;
+  sTamper.SamplingFrequency = RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768;
+  sTamper.PrechargeDuration = RTC_TAMPERPRECHARGEDURATION_1RTCCLK;
+  sTamper.TamperPullUp = RTC_TAMPER_PULLUP_ENABLE;
+  sTamper.TimeStampOnTamperDetection = RTC_TIMESTAMPONTAMPERDETECTION_ENABLE;
+  if (HAL_RTCEx_SetTamper_IT(&hrtc, &sTamper) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN RTC_Init 2 */
+
+  /* USER CODE END RTC_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Tamper event callback function
+  * @param  RTC handle
+  * @retval None
+  */
+void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  RTCStatus = 1;
+  TamperStatus = SET;
+}
+
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  /* User can add his own implementation to report the HAL error return state */
+  RTCStatus = 0xE;
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..6252478ac
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,195 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RTC/RTC_Tamper/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+#ifdef RTC_CLOCK_SOURCE_LSE
+static uint32_t RtcClockSource  = RCC_RTCCLKSOURCE_LSE;
+#elif defined (RTC_CLOCK_SOURCE_LSI)
+static uint32_t RtcClockSource  = RCC_RTCCLKSOURCE_LSI;
+#endif
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief RTC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspInit 0 */
+    RCC_OscInitTypeDef        RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct = {0};
+
+    /* Enables the PWR Clock and Enables access to the backup domain */
+    /* To change the source clock of the RTC feature (LSE, LSI), You have to:
+       - Enable the power clock using __HAL_RCC_PWR_CLK_ENABLE()
+       - Enable write access using HAL_PWR_EnableBkUpAccess() function before to
+         configure the RTC clock source (to be done once after reset).
+       - Reset the Back up Domain using __HAL_RCC_BACKUPRESET_FORCE() and
+         __HAL_RCC_BACKUPRESET_RELEASE().
+       - Configure the needed RTC clock source */
+    HAL_PWR_EnableBkUpAccess();
+
+    /*  Get RTC clock configuration */
+    HAL_RCCEx_GetPeriphCLKConfig(&PeriphClkInitStruct);
+
+    /*In case of RTC clock already enable, make sur it's the good one */
+    if (PeriphClkInitStruct.RTCClockSelection == RtcClockSource)
+    {
+      /* Do nothing */
+    }
+    else
+    {
+      PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+
+      /* If selected source was previously the opposite source clock, first select none*/
+      if (PeriphClkInitStruct.RTCClockSelection != RCC_RTCCLKSOURCE_NONE)
+      {
+        PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_NONE;
+        if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+        {
+          Error_Handler();
+        }
+      }
+      /* Configure LSE/LSI as RTC clock source */
+#ifdef RTC_CLOCK_SOURCE_LSE
+      RCC_OscInitStruct.OscillatorType =  RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_LSE;
+      RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+      RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+      RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
+#elif defined (RTC_CLOCK_SOURCE_LSI)
+      RCC_OscInitStruct.OscillatorType =  RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_LSE;
+      RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+      RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+      RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
+#else
+#error Please select the RTC Clock source inside the main.h file
+#endif /*RTC_CLOCK_SOURCE_LSE*/
+      if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+      {
+        Error_Handler();
+      }
+
+      PeriphClkInitStruct.RTCClockSelection = RtcClockSource;
+      if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+      {
+        Error_Handler();
+      }
+    }
+  /* USER CODE END RTC_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_RTC_ENABLE();
+    __HAL_RCC_RTCAPB_CLK_ENABLE();
+    /* RTC interrupt Init */
+    HAL_NVIC_SetPriority(TAMP_STAMP_LSECSS_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(TAMP_STAMP_LSECSS_IRQn);
+  /* USER CODE BEGIN RTC_MspInit 1 */
+
+  /* USER CODE END RTC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspDeInit 0 */
+
+  /* USER CODE END RTC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RTC_DISABLE();
+    __HAL_RCC_RTCAPB_CLK_DISABLE();
+
+    /* RTC interrupt DeInit */
+    HAL_NVIC_DisableIRQ(TAMP_STAMP_LSECSS_IRQn);
+  /* USER CODE BEGIN RTC_MspDeInit 1 */
+
+  /* USER CODE END RTC_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..763a64bb2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Src/stm32wbxx_it.c
@@ -0,0 +1,138 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    RTC/RTC_Tamper/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+
+extern __IO FlagStatus TamperStatus;
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern RTC_HandleTypeDef hrtc;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles RTC tamper and time stamp, CSS on LSE interrupts through EXTI line 18.
+  */
+void TAMP_STAMP_LSECSS_IRQHandler(void)
+{
+  /* USER CODE BEGIN TAMP_STAMP_LSECSS_IRQn 0 */
+
+  /* USER CODE END TAMP_STAMP_LSECSS_IRQn 0 */
+  HAL_RTCEx_TamperTimeStampIRQHandler(&hrtc);
+  /* USER CODE BEGIN TAMP_STAMP_LSECSS_IRQn 1 */
+
+  /* USER CODE END TAMP_STAMP_LSECSS_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..4cb9e0e42
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx) || defined(STM32WB5Mxx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/readme.txt b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/readme.txt
new file mode 100644
index 000000000..85a334e2e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/RTC/RTC_Tamper/readme.txt
@@ -0,0 +1,102 @@
+/**
+  @page RTC_Tamper RTC Tamper Example
+
+  @verbatim
+  ******************************************************************************
+  * @file    RTC/RTC_Tamper/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the RTC Tamper example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+Configuration of the RTC HAL API to write/read data to/from RTC Backup registers.
+It also demonstrates the tamper detection feature.
+
+At the beginning of the main program the HAL_Init() function is called to reset
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz.
+
+The RTC peripheral configuration is ensured by the HAL_RTC_Init() function.
+This later is calling the HAL_RTC_MspInit()function which core is implementing
+the configuration of the needed RTC resources according to the used hardware (CLOCK,
+PWR, RTC clock source and BackUp). You may update this function to change RTC configuration.
+
+@note LSI oscillator clock is used as RTC clock source by default.
+      The user can use also LSE as RTC clock source. The user uncomment the adequate
+      line on the main.h file.
+      @code
+        #define RTC_CLOCK_SOURCE_LSI
+        /* #define RTC_CLOCK_SOURCE_LSE */
+      @endcode
+      LSI oscillator clock is delivered by a 32 kHz RC.
+      LSE (when available on board) is delivered by a 32.768 kHz crystal.
+
+HAL_RTCEx_SetTamper_IT() function is then called to initialize the Tamper with
+interrupt mode.
+
+The associated firmware performs the following:
+1. It configures the Tamper pin to be rising edge, and enables the Tamper
+   interrupt.
+2. It writes the data to all RTC Backup data registers, then check whether the
+   data were correctly written. If yes, LED1 is on and LED2 toggles with a period of 1s,
+   otherwise LED3 turns ON.
+3. Apply a low level on RTC tamper pin PA0,(connect a wire between PA0 (pin 34 CN7) and 3.3V)
+   the RTC backup data registers are reset and the Tamper interrupt is generated.
+   The corresponding ISR then checks whether the RTC Backup data registers are cleared.
+   If yes LED1 is off and LED2 toggles with a period of 100ms, otherwise LED3 turns ON.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note The application need to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+System, RTC, Tamper, Reset, LSE, LSI
+
+@par Directory contents
+
+  - RTC/RTC_Tamper/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - RTC/RTC_Tamper/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - RTC/RTC_Tamper/Inc/main.h                        Header for main.c module
+  - RTC/RTC_Tamper/Src/stm32wbxx_it.c          Interrupt handlers
+  - RTC/RTC_Tamper/Src/main.c                        Main program
+  - RTC/RTC_Tamper/Src/stm32wbxx_hal_msp.c     HAL MSP module
+  - RTC/RTC_Tamper/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE
+    board and can be easily tailored to any other supported device
+    and development board.
+
+
+@par How to use it ?
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/.extSettings b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/Project.eww
new file mode 100644
index 000000000..5ac7c8a9b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\SPI_FullDuplex_ComDMA_Master.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/SPI_FullDuplex_ComDMA_Master.ewd b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/SPI_FullDuplex_ComDMA_Master.ewd
new file mode 100644
index 000000000..394ca3127
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/SPI_FullDuplex_ComDMA_Master.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		SPI_FullDuplex_ComDMA_Master
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/SPI_FullDuplex_ComDMA_Master.ewp b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/SPI_FullDuplex_ComDMA_Master.ewp
new file mode 100644
index 000000000..240e56566
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/SPI_FullDuplex_ComDMA_Master.ewp
@@ -0,0 +1,1125 @@
+
+
+  3
+  
+    SPI_FullDuplex_ComDMA_Master
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Inc/main.h
new file mode 100644
index 000000000..557232d1a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Inc/main.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_FullDuplex_ComDMA_Master/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+#define COUNTOF(__BUFFER__)   (sizeof(__BUFFER__) / sizeof(*(__BUFFER__)))
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+/* Size of buffer */
+#define BUFFERSIZE                       (COUNTOF(aTxBuffer) - 1)
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..afd5aac3b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+#define HAL_SPI_MODULE_ENABLED
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..58a3d9afc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Inc/stm32wbxx_it.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_FullDuplex_ComDMA_Master/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void DMA1_Channel2_IRQHandler(void);
+void DMA1_Channel3_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/MDK-ARM/SPI_FullDuplex_ComDMA_Master.uvoptx b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/MDK-ARM/SPI_FullDuplex_ComDMA_Master.uvoptx
new file mode 100644
index 000000000..256572829
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/MDK-ARM/SPI_FullDuplex_ComDMA_Master.uvoptx
@@ -0,0 +1,521 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    SPI_FullDuplex_ComDMA_Master
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+      stm32wbxx_hal_spi.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+      stm32wbxx_hal_spi_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      24
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/MDK-ARM/SPI_FullDuplex_ComDMA_Master.uvprojx b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/MDK-ARM/SPI_FullDuplex_ComDMA_Master.uvprojx
new file mode 100644
index 000000000..3e84a98e7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/MDK-ARM/SPI_FullDuplex_ComDMA_Master.uvprojx
@@ -0,0 +1,551 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      SPI_FullDuplex_ComDMA_Master
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          SPI_FullDuplex_ComDMA_Master\
+          SPI_FullDuplex_ComDMA_Master
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_spi.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+            
+            
+              stm32wbxx_hal_spi_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/SPI_FullDuplex_ComDMA_Master.ioc b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/SPI_FullDuplex_ComDMA_Master.ioc
new file mode 100644
index 000000000..3148c71dd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/SPI_FullDuplex_ComDMA_Master.ioc
@@ -0,0 +1,172 @@
+#MicroXplorer Configuration settings - do not modify
+Dma.Request0=SPI1_TX
+Dma.Request1=SPI1_RX
+Dma.RequestsNb=2
+Dma.SPI1_RX.1.Direction=DMA_PERIPH_TO_MEMORY
+Dma.SPI1_RX.1.EventEnable=DISABLE
+Dma.SPI1_RX.1.Instance=DMA1_Channel2
+Dma.SPI1_RX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.SPI1_RX.1.MemInc=DMA_MINC_ENABLE
+Dma.SPI1_RX.1.Mode=DMA_NORMAL
+Dma.SPI1_RX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.SPI1_RX.1.PeriphInc=DMA_PINC_DISABLE
+Dma.SPI1_RX.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.SPI1_RX.1.Priority=DMA_PRIORITY_HIGH
+Dma.SPI1_RX.1.RequestNumber=1
+Dma.SPI1_RX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.SPI1_RX.1.SignalID=NONE
+Dma.SPI1_RX.1.SyncEnable=DISABLE
+Dma.SPI1_RX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.SPI1_RX.1.SyncRequestNumber=1
+Dma.SPI1_RX.1.SyncSignalID=NONE
+Dma.SPI1_TX.0.Direction=DMA_MEMORY_TO_PERIPH
+Dma.SPI1_TX.0.EventEnable=DISABLE
+Dma.SPI1_TX.0.Instance=DMA1_Channel3
+Dma.SPI1_TX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.SPI1_TX.0.MemInc=DMA_MINC_ENABLE
+Dma.SPI1_TX.0.Mode=DMA_NORMAL
+Dma.SPI1_TX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.SPI1_TX.0.PeriphInc=DMA_PINC_DISABLE
+Dma.SPI1_TX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.SPI1_TX.0.Priority=DMA_PRIORITY_LOW
+Dma.SPI1_TX.0.RequestNumber=1
+Dma.SPI1_TX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.SPI1_TX.0.SignalID=NONE
+Dma.SPI1_TX.0.SyncEnable=DISABLE
+Dma.SPI1_TX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.SPI1_TX.0.SyncRequestNumber=1
+Dma.SPI1_TX.0.SyncSignalID=NONE
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=DMA
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SPI1
+Mcu.IP4=SYS
+Mcu.IPNb=5
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA5
+Mcu.Pin1=PA6
+Mcu.Pin2=PA7
+Mcu.Pin3=VP_SYS_VS_Systick
+Mcu.PinsNb=4
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DMA1_Channel2_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.DMA1_Channel3_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PA5.Mode=Full_Duplex_Master
+PA5.Signal=SPI1_SCK
+PA6.Mode=Full_Duplex_Master
+PA6.Signal=SPI1_MISO
+PA7.GPIOParameters=GPIO_PuPd
+PA7.GPIO_PuPd=GPIO_PULLDOWN
+PA7.Mode=Full_Duplex_Master
+PA7.Signal=SPI1_MOSI
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=SPI_FullDuplex_ComDMA_Master.ioc
+ProjectManager.ProjectName=SPI_FullDuplex_ComDMA_Master
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_32
+SPI1.CLKPhase=SPI_PHASE_1EDGE
+SPI1.CLKPolarity=SPI_POLARITY_LOW
+SPI1.CRCCalculation=SPI_CRCCALCULATION_DISABLE
+SPI1.CalculateBaudRate=2.0 MBits/s
+SPI1.DataSize=SPI_DATASIZE_8BIT
+SPI1.Direction=SPI_DIRECTION_2LINES
+SPI1.FirstBit=SPI_FIRSTBIT_MSB
+SPI1.IPParameters=TIMode,DataSize,FirstBit,BaudRatePrescaler,CLKPolarity,CLKPhase,CRCCalculation,NSSPMode,NSS,VirtualType,Mode,Direction,CalculateBaudRate
+SPI1.Mode=SPI_MODE_MASTER
+SPI1.NSS=SPI_NSS_SOFT
+SPI1.NSSPMode=SPI_NSS_PULSE_DISABLE
+SPI1.TIMode=SPI_TIMODE_DISABLE
+SPI1.VirtualType=VM_MASTER
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..245e9d03b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/.project
new file mode 100644
index 000000000..c941aab42
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/.project
@@ -0,0 +1,155 @@
+
+
+	SPI_FullDuplex_ComDMA_Master
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			SPI_FullDuplex_ComDMA_Master.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/SPI_FullDuplex_ComDMA_Master.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_spi.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_spi_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Src/main.c
new file mode 100644
index 000000000..667a7e784
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Src/main.c
@@ -0,0 +1,397 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_FullDuplex_ComDMA_Master/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use STM32WBxx SPI HAL API to transmit
+  *          and receive a data buffer with a communication process based on
+  *          DMA transfer.
+  *          The communication is done using 2 Boards.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+enum
+{
+  TRANSFER_WAIT,
+  TRANSFER_COMPLETE,
+  TRANSFER_ERROR
+};
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+SPI_HandleTypeDef hspi1;
+DMA_HandleTypeDef hdma_spi1_tx;
+DMA_HandleTypeDef hdma_spi1_rx;
+
+/* USER CODE BEGIN PV */
+/* Buffer used for transmission */
+uint8_t aTxBuffer[] = "****SPI - Two Boards communication based on DMA **** SPI Message ******** SPI Message ******** SPI Message ****";
+
+/* Buffer used for reception */
+uint8_t aRxBuffer[BUFFERSIZE];
+
+/* transfer state */
+__IO uint32_t wTransferState = TRANSFER_WAIT;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+static void MX_SPI1_Init(void);
+/* USER CODE BEGIN PFP */
+static uint16_t Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_SPI1_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Configure LED1, LED2 and LED3 */
+  BSP_LED_Init(LED1);
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+
+  /* Configure User push-button (SW1) button */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_GPIO);
+  /* Wait for User push-button (SW1) press before starting the Communication */
+  while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_RESET)
+  {
+    BSP_LED_Toggle(LED1);
+    HAL_Delay(100);
+  }
+  BSP_LED_Off(LED1);
+
+  /*##-1- Start the Full Duplex Communication process ########################*/
+  /* While the SPI in TransmitReceive process, user can transmit data through
+     "aTxBuffer" buffer & receive data through "aRxBuffer" */
+  if (HAL_SPI_TransmitReceive_DMA(&hspi1, (uint8_t *)aTxBuffer, (uint8_t *)aRxBuffer, BUFFERSIZE) != HAL_OK)
+  {
+    /* Transfer error in transmission process */
+    Error_Handler();
+  }
+
+  /*##-2- Wait for the end of the transfer ###################################*/
+  /*  Before starting a new communication transfer, you must wait the callback call
+      to get the transfer complete confirmation or an error detection.
+      For simplicity reasons, this example is just waiting till the end of the
+      transfer, but application may perform other tasks while transfer operation
+      is ongoing. */
+  while (wTransferState == TRANSFER_WAIT)
+  {
+  }
+
+  switch (wTransferState)
+  {
+    case TRANSFER_COMPLETE :
+      /*##-3- Compare the sent and received buffers ##############################*/
+      if (Buffercmp((uint8_t *)aTxBuffer, (uint8_t *)aRxBuffer, BUFFERSIZE))
+      {
+        /* Processing Error */
+        Error_Handler();
+      }
+      break;
+    default :
+      Error_Handler();
+      break;
+  }
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief SPI1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SPI1_Init(void)
+{
+
+  /* USER CODE BEGIN SPI1_Init 0 */
+
+  /* USER CODE END SPI1_Init 0 */
+
+  /* USER CODE BEGIN SPI1_Init 1 */
+
+  /* USER CODE END SPI1_Init 1 */
+  /* SPI1 parameter configuration*/
+  hspi1.Instance = SPI1;
+  hspi1.Init.Mode = SPI_MODE_MASTER;
+  hspi1.Init.Direction = SPI_DIRECTION_2LINES;
+  hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
+  hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
+  hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
+  hspi1.Init.NSS = SPI_NSS_SOFT;
+  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;
+  hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
+  hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
+  hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+  hspi1.Init.CRCPolynomial = 7;
+  hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
+  hspi1.Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
+  if (HAL_SPI_Init(&hspi1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN SPI1_Init 2 */
+
+  /* USER CODE END SPI1_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel2_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
+  /* DMA1_Channel3_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  TxRx Transfer completed callback.
+  * @param  hspi: SPI handle
+  * @note   This example shows a simple way to report end of DMA TxRx transfer, and
+  *         you can add your own implementation.
+  * @retval None
+  */
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Turn LED1 on: Transfer in transmission process is complete */
+  BSP_LED_On(LED1);
+  /* Turn LED2 on: Transfer in reception process is complete */
+  BSP_LED_On(LED2);
+  wTransferState = TRANSFER_COMPLETE;
+}
+
+/**
+  * @brief  SPI error callbacks.
+  * @param  hspi: SPI handle
+  * @note   This example shows a simple way to report transfer error, and you can
+  *         add your own implementation.
+  * @retval None
+  */
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+{
+  wTransferState = TRANSFER_ERROR;
+}
+
+/**
+  * @brief  Compares two buffers.
+  * @param  pBuffer1, pBuffer2: buffers to be compared.
+  * @param  BufferLength: buffer's length
+  * @retval 0  : pBuffer1 identical to pBuffer2
+  *         >0 : pBuffer1 differs from pBuffer2
+  */
+static uint16_t Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
+{
+  while (BufferLength--)
+  {
+    if ((*pBuffer1) != *pBuffer2)
+    {
+      return BufferLength;
+    }
+    pBuffer1++;
+    pBuffer2++;
+  }
+
+  return 0;
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  BSP_LED_Off(LED1);
+  BSP_LED_Off(LED2);
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..9aedac899
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,199 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_FullDuplex_ComDMA_Master/Src/stm32wbxx_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_spi1_tx;
+
+extern DMA_HandleTypeDef hdma_spi1_rx;
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief SPI MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hspi->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspInit 0 */
+
+  /* USER CODE END SPI1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SPI1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**SPI1 GPIO Configuration    
+    PA5     ------> SPI1_SCK
+    PA6     ------> SPI1_MISO
+    PA7     ------> SPI1_MOSI 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* SPI1 DMA Init */
+    /* SPI1_TX Init */
+    hdma_spi1_tx.Instance = DMA1_Channel3;
+    hdma_spi1_tx.Init.Request = DMA_REQUEST_SPI1_TX;
+    hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_spi1_tx.Init.Mode = DMA_NORMAL;
+    hdma_spi1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(hspi,hdmatx,hdma_spi1_tx);
+
+    /* SPI1_RX Init */
+    hdma_spi1_rx.Instance = DMA1_Channel2;
+    hdma_spi1_rx.Init.Request = DMA_REQUEST_SPI1_RX;
+    hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_spi1_rx.Init.Mode = DMA_NORMAL;
+    hdma_spi1_rx.Init.Priority = DMA_PRIORITY_HIGH;
+    if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(hspi,hdmarx,hdma_spi1_rx);
+
+  /* USER CODE BEGIN SPI1_MspInit 1 */
+
+  /* USER CODE END SPI1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief SPI MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
+{
+  if(hspi->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspDeInit 0 */
+    /* Reset peripherals */
+    __HAL_RCC_SPI1_FORCE_RESET();
+    __HAL_RCC_SPI1_RELEASE_RESET();
+
+  /* USER CODE END SPI1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SPI1_CLK_DISABLE();
+  
+    /**SPI1 GPIO Configuration    
+    PA5     ------> SPI1_SCK
+    PA6     ------> SPI1_MISO
+    PA7     ------> SPI1_MOSI 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);
+
+    /* SPI1 DMA DeInit */
+    HAL_DMA_DeInit(hspi->hdmatx);
+    HAL_DMA_DeInit(hspi->hdmarx);
+  /* USER CODE BEGIN SPI1_MspDeInit 1 */
+
+  /* USER CODE END SPI1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..567bb7a7b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Src/stm32wbxx_it.c
@@ -0,0 +1,177 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_FullDuplex_ComDMA_Master/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_spi1_tx;
+extern DMA_HandleTypeDef hdma_spi1_rx;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles DMA1 channel2 global interrupt.
+  */
+void DMA1_Channel2_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel2_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_spi1_rx);
+  /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel2_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA1 channel3 global interrupt.
+  */
+void DMA1_Channel3_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel3_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel3_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_spi1_tx);
+  /* USER CODE BEGIN DMA1_Channel3_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel3_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/readme.txt b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/readme.txt
new file mode 100644
index 000000000..7b3b4eae5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Master/readme.txt
@@ -0,0 +1,136 @@
+/**
+  @page SPI_FullDuplex_ComDMA_Master SPI Full Duplex DMA example
+
+  @verbatim
+  ******************************************************************************
+  * @file    SPI/SPI_FullDuplex_ComDMA_Master/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the SPI Full Duplex DMA example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+Data buffer transmission/reception between two boards via SPI using DMA.
+
+Board: NUCLEO-WB35CE (embeds a STM32WB35CE device)
+CLK Pin: PA5 (CN10, pin 11)
+MISO Pin: PA6 (CN10, pin 27)
+MOSI Pin: PA7 (CN10, pin 15)
+   _________________________                       __________________________
+  |           ______________|                      |______________           |
+  |          |SPI1          |                      |          SPI1|          |
+  |          |              |                      |              |          |
+  |          |    CLK(PA.05)|______________________|CLK(PA.05)    |          |
+  |          |              |                      |              |          |
+  |          |   MISO(PA.06)|______________________|MISO(PA.06)   |          |
+  |          |              |                      |              |          |
+  |          |   MOSI(PA.07)|______________________|MOSI(PA.07)   |          |
+  |          |              |                      |              |          |
+  |          |______________|                      |______________|          |
+  |      __                 |                      |                         |
+  |     |__|                |                      |                         |
+  |    User push-button (SW1)     |                      |                         |
+  |                      GND|______________________|GND                      |
+  |                         |                      |                         |
+  |_STM32WBxx Master________|                      |_STM32WBxx Slave_________|
+
+HAL architecture allows user to easily change code to move to Polling or IT 
+mode. To see others communication modes please check following examples:
+SPI\SPI_FullDuplex_ComPolling_Master and SPI\SPI_FullDuplex_ComPolling_Slave
+SPI\SPI_FullDuplex_ComIT_Master and SPI\SPI_FullDuplex_ComIT_Slave
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz.
+
+The SPI peripheral configuration is ensured by the HAL_SPI_Init() function.
+This later is calling the HAL_SPI_MspInit()function which core is implementing
+the configuration of the needed SPI resources according to the used hardware (CLOCK, 
+GPIO, DMA and NVIC). You may update this function to change SPI configuration.
+
+The SPI communication is then initiated.
+The HAL_SPI_TransmitReceive_DMA() function allows the reception and the 
+transmission of a predefined data buffer at the same time (Full Duplex Mode). 
+If the Master board is used, the project SPI_FullDuplex_ComDMA_Master must be used.
+If the Slave board is used, the project SPI_FullDuplex_ComDMA_Slave must be used.
+
+For this example the aTxBuffer is predefined and the aRxBuffer size is same as aTxBuffer.
+
+In a first step after the user press the User push-button (SW1), SPI Master starts the 
+communication by sending aTxBuffer and receiving aRxBuffer through 
+HAL_SPI_TransmitReceive_DMA(), at the same time SPI Slave transmits aTxBuffer 
+and receives aRxBuffer through HAL_SPI_TransmitReceive_DMA(). 
+The callback functions (HAL_SPI_TxRxCpltCallback and HAL_SPI_ErrorCallbackand) update 
+the variable wTransferState used in the main function to check the transfer status.
+Finally, aRxBuffer and aTxBuffer are compared through Buffercmp() in order to 
+check buffers correctness.  
+
+STM32 board's LEDs can be used to monitor the transfer status:
+ - LED1 toggles quickly on master board waiting User push-button (SW1) to be pressed.
+ - LED1 turns ON when the transmission process is complete.
+ - LED2 turns ON when the reception process is complete.
+ - LED3 turns ON when there is an error in transmission/reception process.  
+
+@note You need to perform a reset on Slave board, then perform it on Master board
+      to have the correct behaviour of this example.
+      
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application need to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+Connectivity, SPI, Full-duplex, Interrupt, Transmission, Reception, Master, Slave, MISO, MOSI, DMA
+
+@par Directory contents 
+
+  - SPI/SPI_FullDuplex_ComDMA_Master/Inc/stm32wbxx_hal_conf.h   HAL configuration file
+  - SPI/SPI_FullDuplex_ComDMA_Master/Inc/stm32wbxx_it.h         Interrupt handlers header file
+  - SPI/SPI_FullDuplex_ComDMA_Master/Inc/main.h                 Header for main.c module  
+  - SPI/SPI_FullDuplex_ComDMA_Master/Src/stm32wbxx_it.c         Interrupt handlers
+  - SPI/SPI_FullDuplex_ComDMA_Master/Src/main.c                 Main program
+  - SPI/SPI_FullDuplex_ComDMA_Master/Src/system_stm32wbxx.c     stm32wbxx system source file
+  - SPI/SPI_FullDuplex_ComDMA_Master/Src/stm32wbxx_hal_msp.c    HAL MSP file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+  - NUCLEO-WB35CE Set-up
+    - Connect Master board PA5 (CN10, pin 11) to Slave Board PA5 (CN10, pin 11)
+    - Connect Master board PA6 (CN10, pin 27) to Slave Board PA6 (CN10, pin 27)
+    - Connect Master board PA7 (CN10, pin 15) to Slave Board PA7 (CN10, pin 15)
+    - Connect Master board GND  to Slave Board GND
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following:
+ - Open your preferred toolchain 
+ - Rebuild all files (master project) and load your image into target memory
+    o Load the project in Master Board
+ - Rebuild all files (slave project) and load your image into target memory
+    o Load the project in Slave Board
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
+ 
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/.extSettings b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/Project.eww
new file mode 100644
index 000000000..0d55f54ef
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\SPI_FullDuplex_ComDMA_Slave.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/SPI_FullDuplex_ComDMA_Slave.ewd b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/SPI_FullDuplex_ComDMA_Slave.ewd
new file mode 100644
index 000000000..eb7a4ffb6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/SPI_FullDuplex_ComDMA_Slave.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		SPI_FullDuplex_ComDMA_Slave
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/SPI_FullDuplex_ComDMA_Slave.ewp b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/SPI_FullDuplex_ComDMA_Slave.ewp
new file mode 100644
index 000000000..b99968e4a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/SPI_FullDuplex_ComDMA_Slave.ewp
@@ -0,0 +1,1125 @@
+
+
+  3
+  
+    SPI_FullDuplex_ComDMA_Slave
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Inc/main.h
new file mode 100644
index 000000000..a2f170398
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Inc/main.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_FullDuplex_ComDMA_Slave/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+#define COUNTOF(__BUFFER__)   (sizeof(__BUFFER__) / sizeof(*(__BUFFER__)))
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+/* Size of buffer */
+#define BUFFERSIZE                       (COUNTOF(aTxBuffer) - 1)
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..afd5aac3b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+#define HAL_SPI_MODULE_ENABLED
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..ccbbc848f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Inc/stm32wbxx_it.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_FullDuplex_ComDMA_Slave/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void DMA1_Channel2_IRQHandler(void);
+void DMA1_Channel3_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/MDK-ARM/SPI_FullDuplex_ComDMA_Slave.uvoptx b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/MDK-ARM/SPI_FullDuplex_ComDMA_Slave.uvoptx
new file mode 100644
index 000000000..d8961b757
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/MDK-ARM/SPI_FullDuplex_ComDMA_Slave.uvoptx
@@ -0,0 +1,521 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    SPI_FullDuplex_ComDMA_Slave
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+      stm32wbxx_hal_spi.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+      stm32wbxx_hal_spi_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      24
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/MDK-ARM/SPI_FullDuplex_ComDMA_Slave.uvprojx b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/MDK-ARM/SPI_FullDuplex_ComDMA_Slave.uvprojx
new file mode 100644
index 000000000..85780b03e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/MDK-ARM/SPI_FullDuplex_ComDMA_Slave.uvprojx
@@ -0,0 +1,551 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      SPI_FullDuplex_ComDMA_Slave
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          SPI_FullDuplex_ComDMA_Slave\
+          SPI_FullDuplex_ComDMA_Slave
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_spi.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+            
+            
+              stm32wbxx_hal_spi_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/SPI_FullDuplex_ComDMA_Slave.ioc b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/SPI_FullDuplex_ComDMA_Slave.ioc
new file mode 100644
index 000000000..b569e0a5c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/SPI_FullDuplex_ComDMA_Slave.ioc
@@ -0,0 +1,169 @@
+#MicroXplorer Configuration settings - do not modify
+Dma.Request0=SPI1_TX
+Dma.Request1=SPI1_RX
+Dma.RequestsNb=2
+Dma.SPI1_RX.1.Direction=DMA_PERIPH_TO_MEMORY
+Dma.SPI1_RX.1.EventEnable=DISABLE
+Dma.SPI1_RX.1.Instance=DMA1_Channel2
+Dma.SPI1_RX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.SPI1_RX.1.MemInc=DMA_MINC_ENABLE
+Dma.SPI1_RX.1.Mode=DMA_NORMAL
+Dma.SPI1_RX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.SPI1_RX.1.PeriphInc=DMA_PINC_DISABLE
+Dma.SPI1_RX.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.SPI1_RX.1.Priority=DMA_PRIORITY_HIGH
+Dma.SPI1_RX.1.RequestNumber=1
+Dma.SPI1_RX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.SPI1_RX.1.SignalID=NONE
+Dma.SPI1_RX.1.SyncEnable=DISABLE
+Dma.SPI1_RX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.SPI1_RX.1.SyncRequestNumber=1
+Dma.SPI1_RX.1.SyncSignalID=NONE
+Dma.SPI1_TX.0.Direction=DMA_MEMORY_TO_PERIPH
+Dma.SPI1_TX.0.EventEnable=DISABLE
+Dma.SPI1_TX.0.Instance=DMA1_Channel3
+Dma.SPI1_TX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.SPI1_TX.0.MemInc=DMA_MINC_ENABLE
+Dma.SPI1_TX.0.Mode=DMA_NORMAL
+Dma.SPI1_TX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.SPI1_TX.0.PeriphInc=DMA_PINC_DISABLE
+Dma.SPI1_TX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.SPI1_TX.0.Priority=DMA_PRIORITY_LOW
+Dma.SPI1_TX.0.RequestNumber=1
+Dma.SPI1_TX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.SPI1_TX.0.SignalID=NONE
+Dma.SPI1_TX.0.SyncEnable=DISABLE
+Dma.SPI1_TX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.SPI1_TX.0.SyncRequestNumber=1
+Dma.SPI1_TX.0.SyncSignalID=NONE
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=DMA
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SPI1
+Mcu.IP4=SYS
+Mcu.IPNb=5
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA5
+Mcu.Pin1=PA6
+Mcu.Pin2=PA7
+Mcu.Pin3=VP_SYS_VS_Systick
+Mcu.PinsNb=4
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DMA1_Channel2_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.DMA1_Channel3_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PA5.Mode=Full_Duplex_Slave
+PA5.Signal=SPI1_SCK
+PA6.Mode=Full_Duplex_Slave
+PA6.Signal=SPI1_MISO
+PA7.GPIOParameters=GPIO_PuPd
+PA7.GPIO_PuPd=GPIO_PULLDOWN
+PA7.Mode=Full_Duplex_Slave
+PA7.Signal=SPI1_MOSI
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=SPI_FullDuplex_ComDMA_Slave.ioc
+ProjectManager.ProjectName=SPI_FullDuplex_ComDMA_Slave
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SPI1.CLKPhase=SPI_PHASE_1EDGE
+SPI1.CLKPolarity=SPI_POLARITY_LOW
+SPI1.CRCCalculation=SPI_CRCCALCULATION_DISABLE
+SPI1.DataSize=SPI_DATASIZE_8BIT
+SPI1.Direction=SPI_DIRECTION_2LINES
+SPI1.FirstBit=SPI_FIRSTBIT_MSB
+SPI1.IPParameters=TIMode,DataSize,FirstBit,CLKPolarity,CLKPhase,CRCCalculation,NSS,VirtualType,Mode,Direction
+SPI1.Mode=SPI_MODE_SLAVE
+SPI1.NSS=SPI_NSS_SOFT
+SPI1.TIMode=SPI_TIMODE_DISABLE
+SPI1.VirtualType=VM_SLAVE
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..3046df2cd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/.cproject
@@ -0,0 +1,170 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/.project
new file mode 100644
index 000000000..32c54d1ae
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/.project
@@ -0,0 +1,155 @@
+
+
+	SPI_FullDuplex_ComDMA_Slave
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			SPI_FullDuplex_ComDMA_Slave.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/SPI_FullDuplex_ComDMA_Slave.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_spi.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_spi_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Src/main.c
new file mode 100644
index 000000000..e04d7f6de
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Src/main.c
@@ -0,0 +1,386 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_FullDuplex_ComDMA_Slave/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use STM32WBxx SPI HAL API to transmit
+  *          and receive a data buffer with a communication process based on
+  *          DMA transfer.
+  *          The communication is done using 2 Boards.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+enum
+{
+  TRANSFER_WAIT,
+  TRANSFER_COMPLETE,
+  TRANSFER_ERROR
+};
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+SPI_HandleTypeDef hspi1;
+DMA_HandleTypeDef hdma_spi1_tx;
+DMA_HandleTypeDef hdma_spi1_rx;
+
+/* USER CODE BEGIN PV */
+/* Buffer used for transmission */
+uint8_t aTxBuffer[] = "****SPI - Two Boards communication based on DMA **** SPI Message ******** SPI Message ******** SPI Message ****";
+
+/* Buffer used for reception */
+uint8_t aRxBuffer[BUFFERSIZE];
+
+/* transfer state */
+__IO uint32_t wTransferState = TRANSFER_WAIT;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+static void MX_SPI1_Init(void);
+/* USER CODE BEGIN PFP */
+static uint16_t Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_SPI1_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Configure LED1, LED2 and LED3 */
+  BSP_LED_Init(LED1);
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+
+  /*##-1- Start the Full Duplex Communication process ########################*/
+  /* While the SPI in TransmitReceive process, user can transmit data through
+     "aTxBuffer" buffer & receive data through "aRxBuffer" */
+  if (HAL_SPI_TransmitReceive_DMA(&hspi1, (uint8_t *)aTxBuffer, (uint8_t *)aRxBuffer, BUFFERSIZE) != HAL_OK)
+  {
+    /* Transfer error in transmission process */
+    Error_Handler();
+  }
+
+  /*##-2- Wait for the end of the transfer ###################################*/
+  /*  Before starting a new communication transfer, you must wait the callback call
+      to get the transfer complete confirmation or an error detection.
+      For simplicity reasons, this example is just waiting till the end of the
+      transfer, but application may perform other tasks while transfer operation
+      is ongoing. */
+  while (wTransferState == TRANSFER_WAIT)
+  {
+  }
+
+  switch (wTransferState)
+  {
+    case TRANSFER_COMPLETE :
+      /*##-3- Compare the sent and received buffers ##############################*/
+      if (Buffercmp((uint8_t *)aTxBuffer, (uint8_t *)aRxBuffer, BUFFERSIZE))
+      {
+        /* Processing Error */
+        Error_Handler();
+      }
+      break;
+    default :
+      Error_Handler();
+      break;
+  }
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief SPI1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SPI1_Init(void)
+{
+
+  /* USER CODE BEGIN SPI1_Init 0 */
+
+  /* USER CODE END SPI1_Init 0 */
+
+  /* USER CODE BEGIN SPI1_Init 1 */
+
+  /* USER CODE END SPI1_Init 1 */
+  /* SPI1 parameter configuration*/
+  hspi1.Instance = SPI1;
+  hspi1.Init.Mode = SPI_MODE_SLAVE;
+  hspi1.Init.Direction = SPI_DIRECTION_2LINES;
+  hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
+  hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
+  hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
+  hspi1.Init.NSS = SPI_NSS_SOFT;
+  hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
+  hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
+  hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+  hspi1.Init.CRCPolynomial = 7;
+  hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
+  hspi1.Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
+  if (HAL_SPI_Init(&hspi1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN SPI1_Init 2 */
+
+  /* USER CODE END SPI1_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel2_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
+  /* DMA1_Channel3_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  TxRx Transfer completed callback.
+  * @param  hspi: SPI handle
+  * @note   This example shows a simple way to report end of DMA TxRx transfer, and
+  *         you can add your own implementation.
+  * @retval None
+  */
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Turn LED1 on: Transfer in transmission process is complete */
+  BSP_LED_On(LED1);
+  /* Turn LED2 on: Transfer in reception process is complete */
+  BSP_LED_On(LED2);
+  wTransferState = TRANSFER_COMPLETE;
+}
+
+/**
+  * @brief  SPI error callbacks.
+  * @param  hspi: SPI handle
+  * @note   This example shows a simple way to report transfer error, and you can
+  *         add your own implementation.
+  * @retval None
+  */
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+{
+  wTransferState = TRANSFER_ERROR;
+}
+
+/**
+  * @brief  Compares two buffers.
+  * @param  pBuffer1, pBuffer2: buffers to be compared.
+  * @param  BufferLength: buffer's length
+  * @retval 0  : pBuffer1 identical to pBuffer2
+  *         >0 : pBuffer1 differs from pBuffer2
+  */
+static uint16_t Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
+{
+  while (BufferLength--)
+  {
+    if ((*pBuffer1) != *pBuffer2)
+    {
+      return BufferLength;
+    }
+    pBuffer1++;
+    pBuffer2++;
+  }
+
+  return 0;
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  BSP_LED_Off(LED1);
+  BSP_LED_Off(LED2);
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..99239d2b9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,199 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_FullDuplex_ComDMA_Master_Slave/Src/stm32wbxx_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_spi1_tx;
+
+extern DMA_HandleTypeDef hdma_spi1_rx;
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief SPI MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hspi->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspInit 0 */
+
+  /* USER CODE END SPI1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SPI1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**SPI1 GPIO Configuration    
+    PA5     ------> SPI1_SCK
+    PA6     ------> SPI1_MISO
+    PA7     ------> SPI1_MOSI 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* SPI1 DMA Init */
+    /* SPI1_TX Init */
+    hdma_spi1_tx.Instance = DMA1_Channel3;
+    hdma_spi1_tx.Init.Request = DMA_REQUEST_SPI1_TX;
+    hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_spi1_tx.Init.Mode = DMA_NORMAL;
+    hdma_spi1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(hspi,hdmatx,hdma_spi1_tx);
+
+    /* SPI1_RX Init */
+    hdma_spi1_rx.Instance = DMA1_Channel2;
+    hdma_spi1_rx.Init.Request = DMA_REQUEST_SPI1_RX;
+    hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_spi1_rx.Init.Mode = DMA_NORMAL;
+    hdma_spi1_rx.Init.Priority = DMA_PRIORITY_HIGH;
+    if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(hspi,hdmarx,hdma_spi1_rx);
+
+  /* USER CODE BEGIN SPI1_MspInit 1 */
+
+  /* USER CODE END SPI1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief SPI MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
+{
+  if(hspi->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspDeInit 0 */
+    /* Reset peripherals */
+    __HAL_RCC_SPI1_FORCE_RESET();
+    __HAL_RCC_SPI1_RELEASE_RESET();
+
+  /* USER CODE END SPI1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SPI1_CLK_DISABLE();
+  
+    /**SPI1 GPIO Configuration    
+    PA5     ------> SPI1_SCK
+    PA6     ------> SPI1_MISO
+    PA7     ------> SPI1_MOSI 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);
+
+    /* SPI1 DMA DeInit */
+    HAL_DMA_DeInit(hspi->hdmatx);
+    HAL_DMA_DeInit(hspi->hdmarx);
+  /* USER CODE BEGIN SPI1_MspDeInit 1 */
+
+  /* USER CODE END SPI1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..3dd515c99
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Src/stm32wbxx_it.c
@@ -0,0 +1,177 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_FullDuplex_ComDMA_Slave/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_spi1_tx;
+extern DMA_HandleTypeDef hdma_spi1_rx;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles DMA1 channel2 global interrupt.
+  */
+void DMA1_Channel2_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel2_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_spi1_rx);
+  /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel2_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA1 channel3 global interrupt.
+  */
+void DMA1_Channel3_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel3_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel3_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_spi1_tx);
+  /* USER CODE BEGIN DMA1_Channel3_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel3_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/readme.txt b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/readme.txt
new file mode 100644
index 000000000..f7f981635
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/SPI/SPI_FullDuplex_ComDMA_Slave/readme.txt
@@ -0,0 +1,136 @@
+/**
+  @page SPI_FullDuplex_ComDMA_Slave SPI Full Duplex DMA example
+
+  @verbatim
+  ******************************************************************************
+  * @file    SPI/SPI_FullDuplex_ComDMA_Slave/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the SPI Full Duplex DMA example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+Data buffer transmission/reception between two boards via SPI using DMA.
+
+Board: NUCLEO-WB35CE (embeds a STM32WB35CE device)
+CLK Pin: PA5 (CN10, pin 11)
+MISO Pin: PA6 (CN10, pin 27)
+MOSI Pin: PA7 (CN10, pin 15)
+   _________________________                       __________________________
+  |           ______________|                      |______________           |
+  |          |SPI1          |                      |          SPI1|          |
+  |          |              |                      |              |          |
+  |          |    CLK(PA.05)|______________________|CLK(PA.05)   |          |
+  |          |              |                      |              |          |
+  |          |   MISO(PA.06)|______________________|MISO(PA.06)   |          |
+  |          |              |                      |              |          |
+  |          |   MOSI(PA.07)|______________________|MOSI(PA.07)   |          |
+  |          |              |                      |              |          |
+  |          |______________|                      |______________|          |
+  |      __                 |                      |                         |
+  |     |__|                |                      |                         |
+  |    User push-button (SW1)     |                      |                         |
+  |                      GND|______________________|GND                      |
+  |                         |                      |                         |
+  |_STM32WBxx Master________|                      |_STM32WBxx Slave_________|
+
+HAL architecture allows user to easily change code to move to Polling or IT 
+mode. To see others communication modes please check following examples:
+SPI\SPI_FullDuplex_ComPolling_Master and SPI\SPI_FullDuplex_ComPolling_Slave
+SPI\SPI_FullDuplex_ComIT_Master and SPI\SPI_FullDuplex_ComIT_Slave
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz.
+
+The SPI peripheral configuration is ensured by the HAL_SPI_Init() function.
+This later is calling the HAL_SPI_MspInit()function which core is implementing
+the configuration of the needed SPI resources according to the used hardware (CLOCK, 
+GPIO, DMA and NVIC). You may update this function to change SPI configuration.
+
+The SPI communication is then initiated.
+The HAL_SPI_TransmitReceive_DMA() function allows the reception and the 
+transmission of a predefined data buffer at the same time (Full Duplex Mode). 
+If the Master board is used, the project SPI_FullDuplex_ComDMA_Master must be used.
+If the Slave board is used, the project SPI_FullDuplex_ComDMA_Slave must be used.
+
+For this example the aTxBuffer is predefined and the aRxBuffer size is same as aTxBuffer.
+
+In a first step after the user press the User push-button (SW1), SPI Master starts the 
+communication by sending aTxBuffer and receiving aRxBuffer through 
+HAL_SPI_TransmitReceive_DMA(), at the same time SPI Slave transmits aTxBuffer 
+and receives aRxBuffer through HAL_SPI_TransmitReceive_DMA(). 
+The callback functions (HAL_SPI_TxRxCpltCallback and HAL_SPI_ErrorCallbackand) update 
+the variable wTransferState used in the main function to check the transfer status.
+Finally, aRxBuffer and aTxBuffer are compared through Buffercmp() in order to 
+check buffers correctness.  
+
+STM32 board's LEDs can be used to monitor the transfer status:
+ - LED1 toggles quickly on master board waiting User push-button (SW1) to be pressed.
+ - LED1 turns ON when the transmission process is complete.
+ - LED2 turns ON when the reception process is complete.
+ - LED3 turns ON when there is an error in transmission/reception process.  
+
+@note You need to perform a reset on Slave board, then perform it on Master board
+      to have the correct behaviour of this example.
+      
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application need to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+Connectivity, SPI, Full-duplex, Interrupt, Transmission, Reception, Master, Slave, MISO, MOSI, DMA
+
+@par Directory contents 
+
+  - SPI/SPI_FullDuplex_ComDMA_Slave/Inc/stm32wbxx_hal_conf.h   HAL configuration file
+  - SPI/SPI_FullDuplex_ComDMA_Slave/Inc/stm32wbxx_it.h         Interrupt handlers header file
+  - SPI/SPI_FullDuplex_ComDMA_Slave/Inc/main.h                 Header for main.c module  
+  - SPI/SPI_FullDuplex_ComDMA_Slave/Src/stm32wbxx_it.c         Interrupt handlers
+  - SPI/SPI_FullDuplex_ComDMA_Slave/Src/main.c                 Main program
+  - SPI/SPI_FullDuplex_ComDMA_Slave/Src/system_stm32wbxx.c     stm32wbxx system source file
+  - SPI/SPI_FullDuplex_ComDMA_Slave/Src/stm32wbxx_hal_msp.c    HAL MSP file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+  - NUCLEO-WB35CE Set-up
+    - Connect Master board PA5 (CN10, pin 11) to Slave Board PA5 (CN10, pin 11)
+    - Connect Master board PA6 (CN10, pin 27) to Slave Board PA6 (CN10, pin 27)
+    - Connect Master board PA7 (CN10, pin 15) to Slave Board PA7 (CN10, pin 15)
+    - Connect Master board GND  to Slave Board GND
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following:
+ - Open your preferred toolchain 
+ - Rebuild all files (master project) and load your image into target memory
+    o Load the project in Master Board
+ - Rebuild all files (slave project) and load your image into target memory
+    o Load the project in Slave Board
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
+ 
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/.extSettings b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/Project.eww
new file mode 100644
index 000000000..33fe9517a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\TIM_OCActive.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/TIM_OCActive.ewd b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/TIM_OCActive.ewd
new file mode 100644
index 000000000..fb43459b2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/TIM_OCActive.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		TIM_OCActive
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/TIM_OCActive.ewp b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/TIM_OCActive.ewp
new file mode 100644
index 000000000..c850fb4d6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/TIM_OCActive.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    TIM_OCActive
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Inc/main.h
new file mode 100644
index 000000000..7683da210
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Inc/main.h
@@ -0,0 +1,80 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    TIM/TIM_OCActive/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+/* Compute the prescaler value to have TIMx counter clock equal to 10 kHz */
+#define  PRESCALER_VALUE  (((SystemCoreClock) / 10000) - 1)
+
+#define  PULSE1_VALUE       10000        /* Capture Compare 1 Value  */
+#define  PULSE2_VALUE       5000         /* Capture Compare 2 Value  */
+#define  PULSE3_VALUE       2500         /* Capture Compare 3 Value  */
+#define  PULSE4_VALUE       1250         /* Capture Compare 4 Value  */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..3e4ba1426
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..cb82ff5c0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Inc/stm32wbxx_it.h
@@ -0,0 +1,64 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    TIM/TIM_OCActive/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/MDK-ARM/TIM_OCActive.uvoptx b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/MDK-ARM/TIM_OCActive.uvoptx
new file mode 100644
index 000000000..b0aa828b7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/MDK-ARM/TIM_OCActive.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    TIM_OCActive
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/MDK-ARM/TIM_OCActive.uvprojx b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/MDK-ARM/TIM_OCActive.uvprojx
new file mode 100644
index 000000000..fedda097f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/MDK-ARM/TIM_OCActive.uvprojx
@@ -0,0 +1,541 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      TIM_OCActive
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          TIM_OCActive\
+          TIM_OCActive
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..7bbc8d6db
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/.project
new file mode 100644
index 000000000..05b644edd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	TIM_OCActive
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			TIM_OCActive.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/TIM_OCActive.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Src/main.c
new file mode 100644
index 000000000..34f8a5512
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Src/main.c
@@ -0,0 +1,321 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    TIM/TIM_OCActive/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example shows how to configure the Timer to generate four 
+  *          delayed signals.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+TIM_HandleTypeDef htim2;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_TIM2_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* Configure LED2, LED3 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_TIM2_Init();
+  /* USER CODE BEGIN 2 */
+
+  /*## Turn On LED2: use PB0 rising edge as reference ####################*/ 
+  /* Turn on LED2 */
+  BSP_LED_On(LED2);
+
+  /*## Start signals generation #######################################*/ 
+  /* Start channel 1 in Output compare mode */
+  if(HAL_TIM_OC_Start(&htim2, TIM_CHANNEL_1) != HAL_OK)
+  {
+    /* Starting Error */
+    Error_Handler();
+  }
+  /* Start channel 2 in Output compare mode */
+  if(HAL_TIM_OC_Start(&htim2, TIM_CHANNEL_2) != HAL_OK)
+  {
+    /* Starting Error */
+    Error_Handler();
+  }
+  /* Start channel 3 in Output compare mode */
+  if(HAL_TIM_OC_Start(&htim2, TIM_CHANNEL_3) != HAL_OK)
+  {
+    /* Starting Error */
+    Error_Handler();
+  }
+  /* Start channel 4 in Output compare mode */
+  if(HAL_TIM_OC_Start(&htim2, TIM_CHANNEL_4) != HAL_OK)
+  {
+    /* Starting Error */
+    Error_Handler();
+  }
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief TIM2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM2_Init(void)
+{
+
+  /* USER CODE BEGIN TIM2_Init 0 */
+
+  /* USER CODE END TIM2_Init 0 */
+
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+  TIM_OC_InitTypeDef sConfigOC = {0};
+
+  /* USER CODE BEGIN TIM2_Init 1 */
+
+  /* USER CODE END TIM2_Init 1 */
+  htim2.Instance = TIM2;
+  htim2.Init.Prescaler = PRESCALER_VALUE;
+  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim2.Init.Period = 65535;
+  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_OC_Init(&htim2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigOC.OCMode = TIM_OCMODE_ACTIVE;
+  sConfigOC.Pulse = PULSE1_VALUE;
+  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
+  if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigOC.Pulse = PULSE2_VALUE;
+  if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigOC.Pulse = PULSE3_VALUE;
+  if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigOC.Pulse = PULSE4_VALUE;
+  if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM2_Init 2 */
+
+  /* USER CODE END TIM2_Init 2 */
+  HAL_TIM_MspPostInit(&htim2);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* LED3 is slowly blinking (1 sec. period) */
+  while(1)
+  {    
+    BSP_LED_Toggle(LED3); 
+    HAL_Delay(1000);
+  } 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* Infinite loop */
+  while (1)
+  {
+  }
+
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..28fd9716b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,157 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : TIM/TIM_OCActive/Src/stm32wbxx_hal_msp.c
+  * @author            : MCD Application Team
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+                        
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+                    /**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief TIM_OC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_oc: TIM_OC handle pointer
+* @retval None
+*/
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* htim_oc)
+{
+  if(htim_oc->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspInit 0 */
+
+  /* USER CODE END TIM2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM2_CLK_ENABLE();
+  /* USER CODE BEGIN TIM2_MspInit 1 */
+
+  /* USER CODE END TIM2_MspInit 1 */
+  }
+
+}
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(htim->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspPostInit 0 */
+
+  /* USER CODE END TIM2_MspPostInit 0 */
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**TIM2 GPIO Configuration    
+    PA0     ------> TIM2_CH1
+    PA1     ------> TIM2_CH2
+    PA2     ------> TIM2_CH3
+    PA3     ------> TIM2_CH4 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN TIM2_MspPostInit 1 */
+
+  /* USER CODE END TIM2_MspPostInit 1 */
+  }
+
+}
+/**
+* @brief TIM_OC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_oc: TIM_OC handle pointer
+* @retval None
+*/
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef* htim_oc)
+{
+  if(htim_oc->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspDeInit 0 */
+
+  /* USER CODE END TIM2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM2_CLK_DISABLE();
+  /* USER CODE BEGIN TIM2_MspDeInit 1 */
+
+  /* USER CODE END TIM2_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..6e8a977ce
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Src/stm32wbxx_it.c
@@ -0,0 +1,120 @@
+/* USER CODE BEGIN Header */
+/** 
+  ******************************************************************************
+  * @file    TIM/TIM_OCActive/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/TIM_OCActive.ioc b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/TIM_OCActive.ioc
new file mode 100644
index 000000000..1d79d9bd4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/TIM_OCActive.ioc
@@ -0,0 +1,165 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=TIM2
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA0
+Mcu.Pin1=PA1
+Mcu.Pin2=PA2
+Mcu.Pin3=PA3
+Mcu.Pin4=VP_SYS_VS_Systick
+Mcu.PinsNb=5
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PA0.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA0.GPIO_PuPd=GPIO_PULLUP
+PA0.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA0.Signal=S_TIM2_CH1
+PA1.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA1.GPIO_PuPd=GPIO_PULLUP
+PA1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA1.Signal=S_TIM2_CH2
+PA2.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA2.GPIO_PuPd=GPIO_PULLUP
+PA2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA2.Signal=S_TIM2_CH3
+PA3.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA3.GPIO_PuPd=GPIO_PULLUP
+PA3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA3.Signal=S_TIM2_CH4
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=TIM_OCActive.ioc
+ProjectManager.ProjectName=TIM_OCActive
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SH.S_TIM2_CH1.0=TIM2_CH1,Output Compare1 CH1
+SH.S_TIM2_CH1.ConfNb=1
+SH.S_TIM2_CH2.0=TIM2_CH2,Output Compare2 CH2
+SH.S_TIM2_CH2.ConfNb=1
+SH.S_TIM2_CH3.0=TIM2_CH3,Output Compare3 CH3
+SH.S_TIM2_CH3.ConfNb=1
+SH.S_TIM2_CH4.0=TIM2_CH4,Output Compare4 CH4
+SH.S_TIM2_CH4.ConfNb=1
+TIM2.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_DISABLE
+TIM2.Channel-Output\ Compare1\ CH1=TIM_CHANNEL_1
+TIM2.Channel-Output\ Compare2\ CH2=TIM_CHANNEL_2
+TIM2.Channel-Output\ Compare3\ CH3=TIM_CHANNEL_3
+TIM2.Channel-Output\ Compare4\ CH4=TIM_CHANNEL_4
+TIM2.ClearInputSource=TIM_CLEARINPUTSOURCE_NONE
+TIM2.ClockDivision=TIM_CLOCKDIVISION_DIV1
+TIM2.CounterMode=TIM_COUNTERMODE_UP
+TIM2.IPParameters=Prescaler,CounterMode,Period,ClockDivision,AutoReloadPreload,TIM_MasterSlaveMode,TIM_MasterOutputTrigger,ClearInputSource,OCMode_1,Pulse-Output Compare1 CH1,OC1Preload,OCPolarity_1,OCMode_2,Pulse-Output Compare2 CH2,OC2Preload,OCPolarity_2,OCMode_3,Pulse-Output Compare3 CH3,OC3Preload,OCPolarity_3,OCMode_4,Pulse-Output Compare4 CH4,OC4Preload,OCPolarity_4,Channel-Output Compare1 CH1,Channel-Output Compare2 CH2,Channel-Output Compare3 CH3,Channel-Output Compare4 CH4
+TIM2.IPParametersWithoutCheck=Prescaler,Pulse-Output Compare4 CH4,Pulse-Output Compare1 CH1,Pulse-Output Compare2 CH2,Pulse-Output Compare3 CH3
+TIM2.OC1Preload=DISABLE
+TIM2.OC2Preload=DISABLE
+TIM2.OC3Preload=DISABLE
+TIM2.OC4Preload=DISABLE
+TIM2.OCMode_1=TIM_OCMODE_ACTIVE
+TIM2.OCMode_2=TIM_OCMODE_ACTIVE
+TIM2.OCMode_3=TIM_OCMODE_ACTIVE
+TIM2.OCMode_4=TIM_OCMODE_ACTIVE
+TIM2.OCPolarity_1=TIM_OCPOLARITY_HIGH
+TIM2.OCPolarity_2=TIM_OCPOLARITY_HIGH
+TIM2.OCPolarity_3=TIM_OCPOLARITY_HIGH
+TIM2.OCPolarity_4=TIM_OCPOLARITY_HIGH
+TIM2.Period=65535
+TIM2.Prescaler=PRESCALER_VALUE
+TIM2.Pulse-Output\ Compare1\ CH1=PULSE1_VALUE
+TIM2.Pulse-Output\ Compare2\ CH2=PULSE2_VALUE
+TIM2.Pulse-Output\ Compare3\ CH3=PULSE3_VALUE
+TIM2.Pulse-Output\ Compare4\ CH4=PULSE4_VALUE
+TIM2.TIM_MasterOutputTrigger=TIM_TRGO_RESET
+TIM2.TIM_MasterSlaveMode=TIM_MASTERSLAVEMODE_DISABLE
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/readme.txt b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/readme.txt
new file mode 100644
index 000000000..66470b19d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_OCActive/readme.txt
@@ -0,0 +1,128 @@
+/**
+  @page TIM_OCActive TIM_OCActive example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    TIM/TIM_OCActive/readme.txt 
+  * @author  MCD Application Team
+  * @brief   This example shows how to configure the Timer to generate four 
+  *          delayed signals.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+Configuration of the TIM peripheral in Output Compare Active mode 
+(when the counter matches the capture/compare register, the corresponding output 
+pin is set to its active state).
+
+  The TIM2 frequency is set to SystemCoreClock, and the objective is
+  to get TIM2 counter clock at 10 kHz so the Prescaler is computed as following:
+     - Prescaler = (TIM2CLK /TIM2 counter clock) - 1
+   
+  SystemCoreClock is set to 64 MHz for STM32WBxx Devices.
+
+  The TIM2 CCR1 register value is equal to 10000:
+  TIM2_CH1 delay = CCR1_Val/TIM2 counter clock  = 1s
+  so the TIM2 Channel 1 generates a signal with a delay equal to 1s.
+
+  The TIM2 CCR2 register value is equal to 5000:
+  TIM2_CH2 delay = CCR2_Val/TIM2 counter clock = 500 ms
+  so the TIM2 Channel 2 generates a signal with a delay equal to 500 ms.
+
+  The TIM2 CCR3 register value is equal to 2500:
+  TIM2_CH3 delay = CCR3_Val/TIM2 counter clock = 250 ms
+  so the TIM2 Channel 3 generates a signal with a delay equal to 250 ms.
+
+  The TIM2 CCR4 register value is equal to 1250:
+  TIM2_CH4 delay = CCR4_Val/TIM2 counter clock = 125 ms
+  so the TIM2 Channel 4 generates a signal with a delay equal to 125 ms.
+
+  The delay correspond to the time difference between PB0 rising edge and
+  TIM2_CHx signal rising edges.
+  STM32 board LED can be used to monitor the example status:
+  - LED2 turns ON if example is OK.
+  - LED3 toggles slowly in case of error.
+
+@note Delay values mentioned above are theoretical (obtained when the system clock frequency 
+      is exactly 64 MHz). Since the generated system clock frequency may vary from one board to another observed
+      delay might be slightly different.
+	  
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note This example needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+Timer, Output, Compare, Active, Signals, 
+
+@par Directory contents
+
+  - TIM/TIM_OCActive/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - TIM/TIM_OCActive/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - TIM/TIM_OCActive/Inc/main.h                  Header for main.c module  
+  - TIM/TIM_OCActive/Src/stm32wbxx_it.c          Interrupt handlers
+  - TIM/TIM_OCActive/Src/main.c                  Main program
+  - TIM/TIM_OCActive/Src/stm32wbxx_hal_msp.c     HAL MSP file
+  - TIM/TIM_OCActive/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE 
+    board and can be easily tailored to any other supported device 
+    and development board.      
+
+  - NUCLEO-WB35CE Set-up
+   Connect the following pins to an oscilloscope to monitor the different waveforms:
+      - Use LED2 connected to PB0 (Reference) (pin 33 in CN10 connector)
+      - PA0: (TIM2_CH1) (pin 34 in CN7 connector)
+      - PA1: (TIM2_CH2) (pin 32 in CN7 connector)
+      - PA2: (TIM2_CH3) (pin 36 in CN7 connector)
+      - PA3: (TIM2_CH4) (pin 38 in CN7 connector)
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+You should see these waveforms on oscilloscope :
+
+ CH1                                                            ________________
+ _______________________________________________________________|
+           <---------------------- 1sec------------------------->
+           
+ CH2                                   __________________________________________
+ ______________________________________|
+           <------------500ms--------->
+ 
+ CH3                        _____________________________________________________
+ ___________________________|
+           <----250ms------->
+ 
+ CH4                  ____________________________________________________________
+ _____________________|
+           <--125ms--->
+
+ LED       ______________________________________________________________________
+ __________|
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/.extSettings b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/Project.eww
new file mode 100644
index 000000000..19604344f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\TIM_PWMInput.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewd b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewd
new file mode 100644
index 000000000..4ce078a32
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		TIM_PWMInput
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewp b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewp
new file mode 100644
index 000000000..b59c52501
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    TIM_PWMInput
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Inc/main.h
new file mode 100644
index 000000000..1ef843837
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    TIM/TIM_PWMInput/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..3e4ba1426
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..418724f50
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Inc/stm32wbxx_it.h
@@ -0,0 +1,67 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    TIM/TIM_PWMInput/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void TIM2_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvoptx b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvoptx
new file mode 100644
index 000000000..080cccca1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvoptx
@@ -0,0 +1,529 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    TIM_PWMInput
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          ARMRTXEVENTFLAGS
+          -L70 -Z18 -C0 -M0 -T1
+        
+        
+          0
+          DLGTARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          
+        
+        
+          0
+          DLGUARM
+          (105=-1,-1,-1,-1,0)
+        
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066EFF303337554E43183717 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        
+          0
+          1
+          uwFrequency,0x0A
+        
+        
+          1
+          1
+          uwDutyCycle,0x0A
+        
+      
+      
+        0
+      
+      
+        0
+        1
+        1
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    1
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvprojx b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvprojx
new file mode 100644
index 000000000..2008d157c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvprojx
@@ -0,0 +1,542 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      TIM_PWMInput
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          TIM_PWMInput\
+          TIM_PWMInput
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..82470cfe8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/.project
new file mode 100644
index 000000000..0d04fcea3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	TIM_PWMInput
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			TIM_PWMInput.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/TIM_PWMInput.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Src/main.c
new file mode 100644
index 000000000..50025acec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Src/main.c
@@ -0,0 +1,356 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    TIM/TIM_PWMInput/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example shows how to use the TIM peripheral to measure the
+  *          frequency and duty cycle of an external signal.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+TIM_HandleTypeDef htim2;
+
+/* USER CODE BEGIN PV */
+/* Captured Value */
+__IO uint32_t            uwIC2Value = 0;
+/* Duty Cycle Value */
+__IO uint32_t            uwDutyCycle = 0;
+/* Frequency Value */
+__IO uint32_t            uwFrequency = 0;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_TIM2_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* Configure LED3 */
+  BSP_LED_Init(LED3);
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_TIM2_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* ---------------------------------------------------------------------------
+  TIM2 configuration: PWM Input mode
+
+  In this example TIM2 input clock (TIM2CLK) is set to APB1 clock (PCLK1),
+  since APB1 prescaler is 1.
+    TIM2CLK = PCLK1
+    PCLK1 = HCLK
+    => TIM2CLK = HCLK = SystemCoreClock
+
+  External Signal Frequency = TIM2 counter clock / TIM2_CCR2 in Hz.
+
+  External Signal DutyCycle = (TIM2_CCR1*100)/(TIM2_CCR2) in %.
+
+  --------------------------------------------------------------------------- */
+
+  /*## Start the Input Capture in interrupt mode ##########################*/
+  if (HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_2) != HAL_OK)
+  {
+    /* Starting Error */
+    Error_Handler();
+  }
+
+  /*## Start the Input Capture in interrupt mode ##########################*/
+  if (HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_1) != HAL_OK)
+  {
+    /* Starting Error */
+    Error_Handler();
+  }
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief TIM2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM2_Init(void)
+{
+
+  /* USER CODE BEGIN TIM2_Init 0 */
+
+  /* USER CODE END TIM2_Init 0 */
+
+  TIM_SlaveConfigTypeDef sSlaveConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+  TIM_IC_InitTypeDef sConfigIC = {0};
+
+  /* USER CODE BEGIN TIM2_Init 1 */
+
+  /* USER CODE END TIM2_Init 1 */
+  htim2.Instance = TIM2;
+  htim2.Init.Prescaler = 0;
+  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim2.Init.Period = 0xFFFF;
+  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_TIM_IC_Init(&htim2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sSlaveConfig.SlaveMode = TIM_SLAVEMODE_RESET;
+  sSlaveConfig.InputTrigger = TIM_TS_TI2FP2;
+  sSlaveConfig.TriggerPolarity = TIM_INPUTCHANNELPOLARITY_RISING;
+  sSlaveConfig.TriggerFilter = 0;
+  if (HAL_TIM_SlaveConfigSynchro(&htim2, &sSlaveConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_FALLING;
+  sConfigIC.ICSelection = TIM_ICSELECTION_INDIRECTTI;
+  sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;
+  sConfigIC.ICFilter = 0;
+  if (HAL_TIM_IC_ConfigChannel(&htim2, &sConfigIC, TIM_CHANNEL_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING;
+  sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;
+  if (HAL_TIM_IC_ConfigChannel(&htim2, &sConfigIC, TIM_CHANNEL_2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM2_Init 2 */
+
+  /* USER CODE END TIM2_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  Input Capture callback in non blocking mode 
+  * @param  htim : TIM IC handle
+  * @retval None
+  */
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+  if (htim->Channel == HAL_TIM_ACTIVE_CHANNEL_2)
+  {
+    /* Get the Input Capture value */
+    uwIC2Value = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_2);
+
+    if (uwIC2Value != 0)
+    {
+      /* Duty cycle computation */
+      uwDutyCycle = ((HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_1)) * 100) / uwIC2Value;
+
+      /* uwFrequency computation
+      TIM2 counter clock = (System Clock) */
+      uwFrequency = ( HAL_RCC_GetSysClockFreq()  ) / uwIC2Value;
+
+    }
+    else
+    {
+      uwDutyCycle = 0;
+      uwFrequency = 0;
+    }
+  }
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  while(1) 
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* Infinite loop */
+  while (1)
+  {
+  }
+
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..96bdefad7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,150 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : TIM/TIM_PWMInput/Src/stm32wbxx_hal_msp.c
+  * @author            : MCD Application Team
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief TIM_Base MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(htim_base->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspInit 0 */
+
+  /* USER CODE END TIM2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM2_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**TIM2 GPIO Configuration    
+    PA1     ------> TIM2_CH2 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_1;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* TIM2 interrupt Init */
+    HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(TIM2_IRQn);
+  /* USER CODE BEGIN TIM2_MspInit 1 */
+
+  /* USER CODE END TIM2_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief TIM_Base MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
+{
+  if(htim_base->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspDeInit 0 */
+
+  /* USER CODE END TIM2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM2_CLK_DISABLE();
+  
+    /**TIM2 GPIO Configuration    
+    PA1     ------> TIM2_CH2 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1);
+
+    /* TIM2 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(TIM2_IRQn);
+  /* USER CODE BEGIN TIM2_MspDeInit 1 */
+
+  /* USER CODE END TIM2_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..bd715dcec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Src/stm32wbxx_it.c
@@ -0,0 +1,162 @@
+/* USER CODE BEGIN Header */
+/** 
+  ******************************************************************************
+  * @file    TIM/TIM_PWMInput/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern TIM_HandleTypeDef htim2;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles TIM2 global interrupt.
+  */
+void TIM2_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM2_IRQn 0 */
+
+  /* USER CODE END TIM2_IRQn 0 */
+  HAL_TIM_IRQHandler(&htim2);
+  /* USER CODE BEGIN TIM2_IRQn 1 */
+
+  /* USER CODE END TIM2_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/TIM_PWMInput.ioc b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/TIM_PWMInput.ioc
new file mode 100644
index 000000000..0d43fc60c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/TIM_PWMInput.ioc
@@ -0,0 +1,134 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=TIM2
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA1
+Mcu.Pin1=VP_SYS_VS_Systick
+Mcu.Pin2=VP_TIM2_VS_ControllerModeReset
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.TIM2_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PA1.Signal=S_TIM2_CH2
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=TIM_PWMInput.ioc
+ProjectManager.ProjectName=TIM_PWMInput
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SH.S_TIM2_CH2.0=TIM2_CH2,TriggerSource_TI2FP2
+SH.S_TIM2_CH2.1=TIM2_CH2,Input_Capture2_from_TI2
+SH.S_TIM2_CH2.2=TIM2_CH2,Input_Capture1_from_TI2
+SH.S_TIM2_CH2.ConfNb=3
+TIM2.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_DISABLE
+TIM2.Channel-Input_Capture1_from_TI2=TIM_CHANNEL_1
+TIM2.Channel-Input_Capture2_from_TI2=TIM_CHANNEL_2
+TIM2.ClockDivision=TIM_CLOCKDIVISION_DIV1
+TIM2.CounterMode=TIM_COUNTERMODE_UP
+TIM2.ICFilter_CH2=0
+TIM2.ICPolarity_CH1=TIM_INPUTCHANNELPOLARITY_FALLING
+TIM2.ICPolarity_CH2=TIM_INPUTCHANNELPOLARITY_RISING
+TIM2.ICPrescaler-Input_Capture1_from_TI2=TIM_ICPSC_DIV1
+TIM2.ICPrescaler-Input_Capture2_from_TI2=TIM_ICPSC_DIV1
+TIM2.ICSelection-Input_Capture1_from_TI2=TIM_ICSELECTION_INDIRECTTI
+TIM2.ICSelection-Input_Capture2_from_TI2=TIM_ICSELECTION_DIRECTTI
+TIM2.IPParameters=Prescaler,CounterMode,Period,ClockDivision,AutoReloadPreload,TIM_MasterSlaveMode,TIM_MasterOutputTrigger,TIM_SlaveMode,ICPolarity_CH1,ICSelection-Input_Capture1_from_TI2,ICPrescaler-Input_Capture1_from_TI2,ICPolarity_CH2,ICSelection-Input_Capture2_from_TI2,ICPrescaler-Input_Capture2_from_TI2,ICFilter_CH2,Channel-Input_Capture1_from_TI2,Channel-Input_Capture2_from_TI2
+TIM2.Period=0xFFFF
+TIM2.Prescaler=0
+TIM2.TIM_MasterOutputTrigger=TIM_TRGO_RESET
+TIM2.TIM_MasterSlaveMode=TIM_MASTERSLAVEMODE_DISABLE
+TIM2.TIM_SlaveMode=TIM_SLAVEMODE_RESET
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+VP_TIM2_VS_ControllerModeReset.Mode=Reset Mode
+VP_TIM2_VS_ControllerModeReset.Signal=TIM2_VS_ControllerModeReset
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/readme.txt b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/readme.txt
new file mode 100644
index 000000000..f7113d6d0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMInput/readme.txt
@@ -0,0 +1,91 @@
+/**
+  @page TIM_PWMInput TIM PWM Input example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    TIM/TIM_PWMInput/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the TIM PWM_Input example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to use the TIM peripheral to measure the frequency and 
+duty cycle of an external signal.
+
+The TIM2CLK frequency is set to SystemCoreClock (Hz), the Prescaler is 0 so the 
+counter clock is SystemCoreClock (Hz).
+SystemCoreClock is set to 64 MHz for STM32WB35CEUx Devices.
+
+TIM2 is configured in PWM Input Mode: the external signal is connected to 
+TIM2 Channel2 used as input pin.
+To measure the frequency and the duty cycle, we use the TIM2 CC2 interrupt request,
+so in the timer IRQ routine (via call to function HAL_TIM_IC_CaptureCallback() ),
+the frequency and the duty cycle of the external signal are computed.
+
+"uwFrequency" variable contains the external signal frequency:
+TIM2 counter clock = SystemCoreClock,
+uwFrequency = TIM2 counter clock / TIM2_CCR2 in Hz, 
+
+"uwDutyCycle" variable contains the external signal duty cycle:
+uwDutyCycle = (TIM2_CCR1*100)/(TIM2_CCR2) in %.
+
+The minimum frequency value to measure is (TIM2 counter clock / CCR MAX)
+                                         = (64 MHz)/ 65535
+
+In case of error, LED3 is turned ON.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note This example needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+Timer, Input, signals, PWM, External signal, Frequency, Duty cycle, Measure
+
+@par Directory contents
+
+  - TIM/TIM_PWMInput/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - TIM/TIM_PWMInput/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - TIM/TIM_PWMInput/Inc/main.h                  Header for main.c module  
+  - TIM/TIM_PWMInput/Src/stm32wbxx_it.c          Interrupt handlers
+  - TIM/TIM_PWMInput/Src/main.c                  Main program
+  - TIM/TIM_PWMInput/Src/stm32wbxx_hal_msp.c     HAL MSP file
+  - TIM/TIM_PWMInput/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE 
+    board and can be easily tailored to any other supported device 
+    and development board.
+
+  - NUCLEO-WB35CE Set-up
+    - Connect the external signal to measure to the TIM2 CH2 pin (PA1) (connected to A2 (pin 3 in CN8 connector)).
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/.extSettings b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/Project.eww
new file mode 100644
index 000000000..124800a6f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\TIM_PWMOutput.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/TIM_PWMOutput.ewd b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/TIM_PWMOutput.ewd
new file mode 100644
index 000000000..6971e2b17
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/TIM_PWMOutput.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		TIM_PWMOutput
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/TIM_PWMOutput.ewp b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/TIM_PWMOutput.ewp
new file mode 100644
index 000000000..368075f3d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/TIM_PWMOutput.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    TIM_PWMOutput
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Inc/main.h
new file mode 100644
index 000000000..b8a04517f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Inc/main.h
@@ -0,0 +1,120 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    TIM/TIM_PWMOutput/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+/* Compute the prescaler value to have TIM2 counter clock equal to 1000000 Hz */
+
+#define PRESCALER_VALUE     (uint32_t)(((SystemCoreClock) / 1000000) - 1)
+
+/* -----------------------------------------------------------------------
+TIM2 Configuration: generate 4 PWM signals with 4 different duty cycles.
+
+    In this example TIM2 input clock (TIM2CLK) is set to APB1 clock (PCLK1),
+    since APB1 prescaler is equal to 1.
+      TIM2CLK = PCLK1
+      PCLK1 = HCLK
+      => TIM2CLK = HCLK = SystemCoreClock
+
+    To get TIM2 counter clock at 1 MHz, the prescaler is computed as follows:
+       Prescaler = (TIM2CLK / TIM2 counter clock) - 1
+       Prescaler = ((SystemCoreClock) /1 MHz) - 1
+
+    To get TIM2 output clock at 24 KHz, the period (ARR)) is computed as follows:
+       ARR = (TIM2 counter clock / TIM2 output clock) - 1
+           = 40
+
+    TIM2 Channel1 duty cycle = (TIM2_CCR1/ TIM2_ARR + 1)* 100 = 50%
+    TIM2 Channel2 duty cycle = (TIM2_CCR2/ TIM2_ARR + 1)* 100 = 37.5%
+    TIM2 Channel3 duty cycle = (TIM2_CCR3/ TIM2_ARR + 1)* 100 = 25%
+    TIM2 Channel4 duty cycle = (TIM2_CCR4/ TIM2_ARR + 1)* 100 = 12.5%
+
+    Note:
+     SystemCoreClock variable holds HCLK frequency and is defined in system_stm32wbxx.c file.
+     Each time the core clock (HCLK) changes, user had to update SystemCoreClock
+     variable value. Otherwise, any configuration based on this variable will be incorrect.
+     This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+  ----------------------------------------------------------------------- */
+
+/* Initialize TIMx peripheral as follows:
+   + Prescaler = (SystemCoreClock / 1000000) - 1
+   + Period = (40 - 1)
+   + ClockDivision = 0
+   + Counter direction = Up
+*/
+#define  PERIOD_VALUE       (uint32_t)(40 - 1)              /* Period Value  */
+#define  PULSE1_VALUE       (uint32_t)(40 / 2)              /* Capture Compare 1 Value  */
+#define  PULSE2_VALUE       (uint32_t)(40 * 37.5 / 100)     /* Capture Compare 2 Value  */
+#define  PULSE3_VALUE       (uint32_t)(40 / 4)              /* Capture Compare 3 Value  */
+#define  PULSE4_VALUE       (uint32_t)(40 * 12.5 /100)      /* Capture Compare 4 Value  */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..3e4ba1426
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..68c8ccffc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Inc/stm32wbxx_it.h
@@ -0,0 +1,66 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    TIM/TIM_PWMOutput/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/MDK-ARM/TIM_PWMOutput.uvoptx b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/MDK-ARM/TIM_PWMOutput.uvoptx
new file mode 100644
index 000000000..a3731fa2d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/MDK-ARM/TIM_PWMOutput.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    TIM_PWMOutput
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/MDK-ARM/TIM_PWMOutput.uvprojx b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/MDK-ARM/TIM_PWMOutput.uvprojx
new file mode 100644
index 000000000..2d1ee2ded
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/MDK-ARM/TIM_PWMOutput.uvprojx
@@ -0,0 +1,541 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      TIM_PWMOutput
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          TIM_PWMOutput\
+          TIM_PWMOutput
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..f18219d26
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/.project
new file mode 100644
index 000000000..8afe1e2ab
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	TIM_PWMOutput
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			TIM_PWMOutput.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/TIM_PWMOutput.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Src/main.c
new file mode 100644
index 000000000..02805274f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Src/main.c
@@ -0,0 +1,317 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    TIM/TIM_PWMOutput/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use STM32WBxx TIM HAL API to generate
+  *          4 signals in PWM.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+TIM_HandleTypeDef htim2;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_TIM2_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* Configure LED3 */
+  BSP_LED_Init(LED3);
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_TIM2_Init();
+  /* USER CODE BEGIN 2 */
+
+/*## Start PWM signals generation #######################################*/
+  /* Start channel 1 */
+  if (HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1) != HAL_OK)
+  {
+    /* PWM Generation Error */
+    Error_Handler();
+  }
+  /* Start channel 2 */
+  if (HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_2) != HAL_OK)
+  {
+    /* PWM Generation Error */
+    Error_Handler();
+  }
+  /* Start channel 3 */
+  if (HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_3) != HAL_OK)
+  {
+    /* PWM generation Error */
+    Error_Handler();
+  }
+  /* Start channel 4 */
+  if (HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_4) != HAL_OK)
+  {
+    /* PWM generation Error */
+    Error_Handler();
+  }
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief TIM2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM2_Init(void)
+{
+
+  /* USER CODE BEGIN TIM2_Init 0 */
+
+  /* USER CODE END TIM2_Init 0 */
+
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+  TIM_OC_InitTypeDef sConfigOC = {0};
+
+  /* USER CODE BEGIN TIM2_Init 1 */
+
+  /* USER CODE END TIM2_Init 1 */
+  htim2.Instance = TIM2;
+  htim2.Init.Prescaler = PRESCALER_VALUE;
+  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim2.Init.Period = PERIOD_VALUE;
+  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigOC.OCMode = TIM_OCMODE_PWM1;
+  sConfigOC.Pulse = PULSE1_VALUE;
+  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
+  if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigOC.Pulse = PULSE2_VALUE;
+  if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigOC.Pulse = PULSE3_VALUE;
+  if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigOC.Pulse = PULSE4_VALUE;
+  if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM2_Init 2 */
+
+  /* USER CODE END TIM2_Init 2 */
+  HAL_TIM_MspPostInit(&htim2);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  while(1) 
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* Infinite loop */
+  while (1)
+  {
+  }
+
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..f1362a451
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,157 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : TIM/TIM_PWMOutput/Src/stm32wbxx_hal_msp.c
+  * @author            : MCD Application Team
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+                        
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+                    /**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief TIM_PWM MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_pwm: TIM_PWM handle pointer
+* @retval None
+*/
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
+{
+  if(htim_pwm->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspInit 0 */
+
+  /* USER CODE END TIM2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM2_CLK_ENABLE();
+  /* USER CODE BEGIN TIM2_MspInit 1 */
+
+  /* USER CODE END TIM2_MspInit 1 */
+  }
+
+}
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(htim->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspPostInit 0 */
+
+  /* USER CODE END TIM2_MspPostInit 0 */
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**TIM2 GPIO Configuration    
+    PA0     ------> TIM2_CH1
+    PA1     ------> TIM2_CH2
+    PA2     ------> TIM2_CH3
+    PA3     ------> TIM2_CH4 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN TIM2_MspPostInit 1 */
+
+  /* USER CODE END TIM2_MspPostInit 1 */
+  }
+
+}
+/**
+* @brief TIM_PWM MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_pwm: TIM_PWM handle pointer
+* @retval None
+*/
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm)
+{
+  if(htim_pwm->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspDeInit 0 */
+
+  /* USER CODE END TIM2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM2_CLK_DISABLE();
+  /* USER CODE BEGIN TIM2_MspDeInit 1 */
+
+  /* USER CODE END TIM2_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..b4fcb55b2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Src/stm32wbxx_it.c
@@ -0,0 +1,148 @@
+/* USER CODE BEGIN Header */
+/** 
+  ******************************************************************************
+  * @file    TIM/TIM_PWMOutput/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/TIM_PWMOutput.ioc b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/TIM_PWMOutput.ioc
new file mode 100644
index 000000000..6d9470194
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/TIM_PWMOutput.ioc
@@ -0,0 +1,169 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=TIM2
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA0
+Mcu.Pin1=PA1
+Mcu.Pin2=PA2
+Mcu.Pin3=PA3
+Mcu.Pin4=VP_SYS_VS_Systick
+Mcu.PinsNb=5
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PA0.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA0.GPIO_PuPd=GPIO_PULLUP
+PA0.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA0.Signal=S_TIM2_CH1
+PA1.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA1.GPIO_PuPd=GPIO_PULLUP
+PA1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA1.Signal=S_TIM2_CH2
+PA2.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA2.GPIO_PuPd=GPIO_PULLUP
+PA2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA2.Signal=S_TIM2_CH3
+PA3.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA3.GPIO_PuPd=GPIO_PULLUP
+PA3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA3.Signal=S_TIM2_CH4
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=TIM_PWMOutput.ioc
+ProjectManager.ProjectName=TIM_PWMOutput
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SH.S_TIM2_CH1.0=TIM2_CH1,PWM Generation1 CH1
+SH.S_TIM2_CH1.ConfNb=1
+SH.S_TIM2_CH2.0=TIM2_CH2,PWM Generation2 CH2
+SH.S_TIM2_CH2.ConfNb=1
+SH.S_TIM2_CH3.0=TIM2_CH3,PWM Generation3 CH3
+SH.S_TIM2_CH3.ConfNb=1
+SH.S_TIM2_CH4.0=TIM2_CH4,PWM Generation4 CH4
+SH.S_TIM2_CH4.ConfNb=1
+TIM2.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_DISABLE
+TIM2.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
+TIM2.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2
+TIM2.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
+TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4
+TIM2.ClearInputSource=TIM_CLEARINPUTSOURCE_NONE
+TIM2.ClockDivision=TIM_CLOCKDIVISION_DIV1
+TIM2.CounterMode=TIM_COUNTERMODE_UP
+TIM2.IPParameters=Prescaler,CounterMode,Period,ClockDivision,AutoReloadPreload,TIM_MasterSlaveMode,TIM_MasterOutputTrigger,ClearInputSource,OCMode_PWM-PWM Generation1 CH1,Pulse-PWM Generation1 CH1,OC1Preload_PWM,OCFastMode_PWM-PWM Generation1 CH1,OCPolarity_1,OCMode_PWM-PWM Generation2 CH2,Pulse-PWM Generation2 CH2,OC2Preload_PWM,OCFastMode_PWM-PWM Generation2 CH2,OCPolarity_2,OCMode_PWM-PWM Generation3 CH3,Pulse-PWM Generation3 CH3,OC3Preload_PWM,OCFastMode_PWM-PWM Generation3 CH3,OCPolarity_3,OCMode_PWM-PWM Generation4 CH4,Pulse-PWM Generation4 CH4,OC4Preload_PWM,OCFastMode_PWM-PWM Generation4 CH4,OCPolarity_4,Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4
+TIM2.IPParametersWithoutCheck=Pulse-PWM Generation1 CH1,Pulse-PWM Generation2 CH2,Pulse-PWM Generation3 CH3,Pulse-PWM Generation4 CH4,Prescaler,Period
+TIM2.OC1Preload_PWM=ENABLE
+TIM2.OC2Preload_PWM=ENABLE
+TIM2.OC3Preload_PWM=ENABLE
+TIM2.OC4Preload_PWM=ENABLE
+TIM2.OCFastMode_PWM-PWM\ Generation1\ CH1=TIM_OCFAST_DISABLE
+TIM2.OCFastMode_PWM-PWM\ Generation2\ CH2=TIM_OCFAST_DISABLE
+TIM2.OCFastMode_PWM-PWM\ Generation3\ CH3=TIM_OCFAST_DISABLE
+TIM2.OCFastMode_PWM-PWM\ Generation4\ CH4=TIM_OCFAST_DISABLE
+TIM2.OCMode_PWM-PWM\ Generation1\ CH1=TIM_OCMODE_PWM1
+TIM2.OCMode_PWM-PWM\ Generation2\ CH2=TIM_OCMODE_PWM1
+TIM2.OCMode_PWM-PWM\ Generation3\ CH3=TIM_OCMODE_PWM1
+TIM2.OCMode_PWM-PWM\ Generation4\ CH4=TIM_OCMODE_PWM1
+TIM2.OCPolarity_1=TIM_OCPOLARITY_HIGH
+TIM2.OCPolarity_2=TIM_OCPOLARITY_HIGH
+TIM2.OCPolarity_3=TIM_OCPOLARITY_HIGH
+TIM2.OCPolarity_4=TIM_OCPOLARITY_HIGH
+TIM2.Period=PERIOD_VALUE
+TIM2.Prescaler=PRESCALER_VALUE
+TIM2.Pulse-PWM\ Generation1\ CH1=PULSE1_VALUE
+TIM2.Pulse-PWM\ Generation2\ CH2=PULSE2_VALUE
+TIM2.Pulse-PWM\ Generation3\ CH3=PULSE3_VALUE
+TIM2.Pulse-PWM\ Generation4\ CH4=PULSE4_VALUE
+TIM2.TIM_MasterOutputTrigger=TIM_TRGO_RESET
+TIM2.TIM_MasterSlaveMode=TIM_MASTERSLAVEMODE_DISABLE
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/readme.txt b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/readme.txt
new file mode 100644
index 000000000..ec4eeeea8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TIM/TIM_PWMOutput/readme.txt
@@ -0,0 +1,109 @@
+/**
+  @page TIM_PWMOutput TIM PWM Output example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    TIM/TIM_PWMOutput/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the PWM signals generation using TIM2
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+This example shows how to configure the TIM peripheral in PWM (Pulse Width Modulation) 
+mode.
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+The SystemClock_Config() function is used to configure the system clock for STM32WB35CEUx Devices :
+The CPU at 64 MHz 
+
+SystemCoreClock is set to 64 MHz for STM32WBxx Devices.
+
+    In this example TIM2 input clock (TIM2CLK) is set to APB1 clock (PCLK1),
+    since APB1 prescaler is equal to 1.
+      TIM2CLK = PCLK1
+      PCLK1 = HCLK
+      => TIM2CLK = HCLK = SystemCoreClock
+
+    To get TIM2 counter clock at 1 MHz, the prescaler is computed as follows:
+       Prescaler = (TIM2CLK / TIM2 counter clock) - 1
+       Prescaler = ((SystemCoreClock) /1 MHz) - 1
+
+    To get TIM2 output clock at 24 KHz, the period (ARR)) is computed as follows:
+       ARR = (TIM2 counter clock / TIM2 output clock) - 1
+           = 40
+
+    TIM2 Channel1 duty cycle = (TIM2_CCR1/ TIM2_ARR + 1)* 100 = 50%
+    TIM2 Channel2 duty cycle = (TIM2_CCR2/ TIM2_ARR + 1)* 100 = 37.5%
+    TIM2 Channel3 duty cycle = (TIM2_CCR3/ TIM2_ARR + 1)* 100 = 25%
+    TIM2 Channel4 duty cycle = (TIM2_CCR4/ TIM2_ARR + 1)* 100 = 12.5%
+
+LED3 is ON when there are an error.
+
+The PWM waveforms can be displayed using an oscilloscope.
+
+@note The duty cycles values mentioned above are theoretical (obtained when the system clock frequency is exactly 64 MHz).
+      They might be slightly different depending on system clock frequency precision.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note This example needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+	  
+
+@par Keywords
+
+Timer, Output, signal, PWM, Oscilloscope, Frequency, Duty cycle, Waveform
+
+@par Directory contents
+
+  - TIM/TIM_PWMOutput/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - TIM/TIM_PWMOutput/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - TIM/TIM_PWMOutput/Inc/main.h                  Header for main.c module  
+  - TIM/TIM_PWMOutput/Src/stm32wbxx_it.c          Interrupt handlers
+  - TIM/TIM_PWMOutput/Src/main.c                  Main program
+  - TIM/TIM_PWMOutput/Src/stm32wbxx_hal_msp.c     HAL MSP file
+  - TIM/TIM_PWMOutput/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+  - In this example, the clock is set to 64 MHz.
+    
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE 
+    board and can be easily tailored to any other supported device 
+    and development board.      
+
+  - NUCLEO-WB35CE Set-up
+   Connect the following pins to an oscilloscope to monitor the different waveforms:
+        - TIM2_CH1 : PA.00 (pin 34 in CN7 connector)
+        - TIM2_CH2 : PA.01 (pin 32 in CN7 connector)
+        - TIM2_CH3 : PA.02 (pin 36 in CN7 connector)
+        - TIM2_CH4 : PA.03 (pin 38 in CN7 connector)
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/TSC/TSC_BasicAcquisition_Interrupt/readme.txt b/Projects/NUCLEO-WB35CE/Examples/TSC/TSC_BasicAcquisition_Interrupt/readme.txt
new file mode 100644
index 000000000..5f2ca7426
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/TSC/TSC_BasicAcquisition_Interrupt/readme.txt
@@ -0,0 +1,46 @@
+/**
+  @page TSC_BasicAcquisition_Interrupt Touch-Sensing basic acquisition using interrupt
+
+  @verbatim
+  ******************************************************************************
+  * @file    TSC/TSC_BasicAcquisition_Interrupt/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the TSC basic acquisition interrupt example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+Use of the TSC HAL API to perform continuous acquisitions of one channel in Interrupt mode.
+
+The TSC feature is part of STM32WB35xx. 
+
+The NUCLEO-WB35CE board is not suitable to demonstrate this feature as it does not contains 
+any touch-sensing button.
+
+The hal library for TSC driver is compatible between STM32L4xx_HAL_Driver and STM32WBxx_HAL_Driver.
+
+You can retrieve the STM32L4xx_HAL_Driver under the stm32cubel4 package (https://www.st.com/stm32cubel4).
+
+Inside the stm32cubel4 package, this TSC_BasicAcquisition_Interrupt example is available with the following boards:
+  STM32L476G-EVAL  (Projects\STM32L476G-EVAL\Examples\TSC\TSC_BasicAcquisition_Interrupt)
+  You can use those examples and boards schematics for your own implementation.
+
+The required adaptation from STM32L476G-EVAL project, given as information:
+  In all files, rename and adapt include files name to your situation.
+  Copy the system_stm32wbxx.c from Drivers\CMSIS\Device\ST\STM32WBxx\Source\Templates to Src.
+  Copy the stm32wbxx_hal_conf_template.h from Drivers\STM32WBxx_HAL_Driver\Inc to Inc\stm32wbxx_hal_conf.h.
+  Adapt the main.c/SystemClock_Config(void) function to your board.
+  Adapt the GPIO initialization to your board.
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/.extSettings b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/Project.eww
new file mode 100644
index 000000000..f8b9eb150
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\UART_HyperTerminal_DMA.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/UART_HyperTerminal_DMA.ewd b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/UART_HyperTerminal_DMA.ewd
new file mode 100644
index 000000000..8ec2654d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/UART_HyperTerminal_DMA.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		UART_HyperTerminal_DMA
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/UART_HyperTerminal_DMA.ewp b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/UART_HyperTerminal_DMA.ewp
new file mode 100644
index 000000000..64e4db27b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/UART_HyperTerminal_DMA.ewp
@@ -0,0 +1,1125 @@
+
+
+  3
+  
+    UART_HyperTerminal_DMA
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Inc/main.h
new file mode 100644
index 000000000..43979e815
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Inc/main.h
@@ -0,0 +1,77 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_HyperTerminal_DMA/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+#define COUNTOF(__BUFFER__)   (sizeof(__BUFFER__) / sizeof(*(__BUFFER__)))
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+/* Size of Transmission buffer */
+#define TXSTARTMESSAGESIZE               (COUNTOF(aTxStartMessage) - 1)
+#define TXENDMESSAGESIZE                 (COUNTOF(aTxEndMessage) - 1)
+
+/* Size of Reception buffer */
+#define RXBUFFERSIZE                      10
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..7353fcbbb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..3bde0e591
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Inc/stm32wbxx_it.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_HyperTerminal_DMA/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void DMA1_Channel1_IRQHandler(void);
+void DMA1_Channel2_IRQHandler(void);
+void USART1_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/MDK-ARM/UART_HyperTerminal_DMA.uvoptx b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/MDK-ARM/UART_HyperTerminal_DMA.uvoptx
new file mode 100644
index 000000000..26ad69032
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/MDK-ARM/UART_HyperTerminal_DMA.uvoptx
@@ -0,0 +1,521 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    UART_HyperTerminal_DMA
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+      stm32wbxx_hal_uart.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+      stm32wbxx_hal_uart_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      24
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/MDK-ARM/UART_HyperTerminal_DMA.uvprojx b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/MDK-ARM/UART_HyperTerminal_DMA.uvprojx
new file mode 100644
index 000000000..58061b581
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/MDK-ARM/UART_HyperTerminal_DMA.uvprojx
@@ -0,0 +1,551 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      UART_HyperTerminal_DMA
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          UART_HyperTerminal_DMA\
+          UART_HyperTerminal_DMA
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_uart.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+            
+            
+              stm32wbxx_hal_uart_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..bfc193d9a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/.project
new file mode 100644
index 000000000..2600ce53a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/.project
@@ -0,0 +1,155 @@
+
+
+	UART_HyperTerminal_DMA
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			UART_HyperTerminal_DMA.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/UART_HyperTerminal_DMA.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Src/main.c
new file mode 100644
index 000000000..0ad2a1746
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Src/main.c
@@ -0,0 +1,397 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_HyperTerminal_DMA/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use UART HAL API to transmit
+  *          and receive a data buffer with a communication process based on
+  *          DMA transfer.
+  *          The communication is done with the Hyperterminal PC application.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef huart1;
+DMA_HandleTypeDef hdma_usart1_rx;
+DMA_HandleTypeDef hdma_usart1_tx;
+
+/* USER CODE BEGIN PV */
+/* Buffer used for transmission */
+uint8_t aTxStartMessage[] = "\n\r ****UART-Hyperterminal communication based on DMA****\n\r Enter 10 characters using keyboard :\n\r";
+uint8_t aTxEndMessage[] = "\n\r Example Finished\n\r";
+
+/* Buffer used for reception */
+uint8_t aRxBuffer[RXBUFFERSIZE];
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+static void MX_USART1_UART_Init(void);
+/* USER CODE BEGIN PFP */
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* Configure LED2 and LED3 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_USART1_UART_Init();
+  /* USER CODE BEGIN 2 */
+
+  /*##-1- Start the transmission process #####################################*/
+  /* User start transmission data through "TxBuffer" buffer */
+  if(HAL_UART_Transmit_DMA(&huart1, (uint8_t*)aTxStartMessage, TXSTARTMESSAGESIZE)!= HAL_OK)
+  {
+    /* Transfer error in transmission process */
+    Error_Handler();
+  }
+
+  /*##-2- Put UART peripheral in reception process ###########################*/
+  /* Any data received will be stored in "aRxBuffer" buffer : the number max of
+     data received is 10 */
+  if (HAL_UART_Receive_DMA(&huart1, (uint8_t *)aRxBuffer, RXBUFFERSIZE) != HAL_OK)
+  {
+    /* Transfer error in reception process */
+    Error_Handler();
+  }
+
+  /*##-3- Wait for the end of the transfer ###################################*/
+  /*  Before starting a new communication transfer, you need to check the current
+      state of the peripheral; if it's busy you need to wait for the end of current
+      transfer before starting a new one.
+      For simplicity reasons, this example is just waiting till the end of the
+      transfer, but application may perform other tasks while transfer operation
+      is ongoing. */
+  while (HAL_UART_GetState(&huart1) != HAL_UART_STATE_READY)
+  {
+  }
+
+  /*##-4- Send the received Buffer ###########################################*/
+  if (HAL_UART_Transmit_DMA(&huart1, (uint8_t *)aRxBuffer, RXBUFFERSIZE) != HAL_OK)
+  {
+    /* Transfer error in transmission process */
+    Error_Handler();
+  }
+
+  /*##-5- Wait for the end of the transfer ###################################*/
+  /*  Before starting a new communication transfer, you need to check the current
+      state of the peripheral; if it's busy you need to wait for the end of current
+      transfer before starting a new one.
+      For simplicity reasons, this example is just waiting till the end of the
+      transfer, but application may perform other tasks while transfer operation
+      is ongoing. */
+  while (HAL_UART_GetState(&huart1) != HAL_UART_STATE_READY)
+  {
+  }
+
+  /*##-6- Send the End Message ###############################################*/
+  if(HAL_UART_Transmit_DMA(&huart1, (uint8_t*)aTxEndMessage, TXENDMESSAGESIZE)!= HAL_OK)
+  {
+    /* Transfer error in transmission process */
+    Error_Handler();
+  }
+
+  /*##-7- Wait for the end of the transfer ###################################*/
+  while (HAL_UART_GetState(&huart1) != HAL_UART_STATE_READY)
+  {
+  }
+
+  /* Turn on LED2 if test passes then enter infinite loop */
+  BSP_LED_On(LED2);
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 9600;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_ODD;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+  /* DMA1_Channel2_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  Tx Transfer completed callback
+  * @param  huart: UART handle.
+  * @note   This example shows a simple way to report end of DMA Tx transfer, and
+  *         you can add your own implementation.
+  * @retval None
+  */
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+}
+
+/**
+  * @brief  Rx Transfer completed callback
+  * @param  huart: UART handle
+  * @note   This example shows a simple way to report end of DMA Rx transfer, and
+  *         you can add your own implementation.
+  * @retval None
+  */
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+}
+
+/**
+  * @brief  UART error callbacks
+  * @param  huart: UART handle
+  * @note   This example shows a simple way to report transfer error, and you can
+  *         add your own implementation.
+  * @retval None
+  */
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+  /* Turn LED3 on: Transfer error in reception/transmission process */
+  BSP_LED_On(LED3);
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  while(1);
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..8ffad6b43
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,194 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_HyperTerminal_DMA/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_usart1_rx;
+
+extern DMA_HandleTypeDef hdma_usart1_tx;
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspInit 0 */
+
+  /* USER CODE END USART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**USART1 GPIO Configuration    
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* USART1 DMA Init */
+    /* USART1_RX Init */
+    hdma_usart1_rx.Instance = DMA1_Channel2;
+    hdma_usart1_rx.Init.Request = DMA_REQUEST_USART1_RX;
+    hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_usart1_rx.Init.Mode = DMA_NORMAL;
+    hdma_usart1_rx.Init.Priority = DMA_PRIORITY_HIGH;
+    if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmarx,hdma_usart1_rx);
+
+    /* USART1_TX Init */
+    hdma_usart1_tx.Instance = DMA1_Channel1;
+    hdma_usart1_tx.Init.Request = DMA_REQUEST_USART1_TX;
+    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx);
+
+    /* USART1 interrupt Init */
+    HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspInit 1 */
+
+  /* USER CODE END USART1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspDeInit 0 */
+    __HAL_RCC_USART1_FORCE_RESET();
+    __HAL_RCC_USART1_RELEASE_RESET();
+  /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+  
+    /**USART1 GPIO Configuration    
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
+
+    /* USART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmarx);
+    HAL_DMA_DeInit(huart->hdmatx);
+
+    /* USART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+  /* USER CODE END USART1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..0f85158b1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Src/stm32wbxx_it.c
@@ -0,0 +1,193 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_HyperTerminal_DMA/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_usart1_rx;
+extern DMA_HandleTypeDef hdma_usart1_tx;
+extern UART_HandleTypeDef huart1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles DMA1 channel1 global interrupt.
+  */
+void DMA1_Channel1_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel1_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart1_tx);
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA1 channel2 global interrupt.
+  */
+void DMA1_Channel2_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel2_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart1_rx);
+  /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel2_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+
+  /* USER CODE END USART1_IRQn 0 */
+  HAL_UART_IRQHandler(&huart1);
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/UART_HyperTerminal_DMA.ioc b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/UART_HyperTerminal_DMA.ioc
new file mode 100644
index 000000000..addd2fa56
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/UART_HyperTerminal_DMA.ioc
@@ -0,0 +1,175 @@
+#MicroXplorer Configuration settings - do not modify
+Dma.Request0=USART1_RX
+Dma.Request1=USART1_TX
+Dma.RequestsNb=2
+Dma.USART1_RX.0.Direction=DMA_PERIPH_TO_MEMORY
+Dma.USART1_RX.0.EventEnable=DISABLE
+Dma.USART1_RX.0.Instance=DMA1_Channel2
+Dma.USART1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.USART1_RX.0.MemInc=DMA_MINC_ENABLE
+Dma.USART1_RX.0.Mode=DMA_NORMAL
+Dma.USART1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.USART1_RX.0.PeriphInc=DMA_PINC_DISABLE
+Dma.USART1_RX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.USART1_RX.0.Priority=DMA_PRIORITY_HIGH
+Dma.USART1_RX.0.RequestNumber=1
+Dma.USART1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.USART1_RX.0.SignalID=NONE
+Dma.USART1_RX.0.SyncEnable=DISABLE
+Dma.USART1_RX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.USART1_RX.0.SyncRequestNumber=1
+Dma.USART1_RX.0.SyncSignalID=NONE
+Dma.USART1_TX.1.Direction=DMA_MEMORY_TO_PERIPH
+Dma.USART1_TX.1.EventEnable=DISABLE
+Dma.USART1_TX.1.Instance=DMA1_Channel1
+Dma.USART1_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.USART1_TX.1.MemInc=DMA_MINC_ENABLE
+Dma.USART1_TX.1.Mode=DMA_NORMAL
+Dma.USART1_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.USART1_TX.1.PeriphInc=DMA_PINC_DISABLE
+Dma.USART1_TX.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.USART1_TX.1.Priority=DMA_PRIORITY_LOW
+Dma.USART1_TX.1.RequestNumber=1
+Dma.USART1_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.USART1_TX.1.SignalID=NONE
+Dma.USART1_TX.1.SyncEnable=DISABLE
+Dma.USART1_TX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.USART1_TX.1.SyncRequestNumber=1
+Dma.USART1_TX.1.SyncSignalID=NONE
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=DMA
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IP4=USART1
+Mcu.IPNb=5
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB6
+Mcu.Pin1=PB7
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.DMA1_Channel2_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PB6.GPIOParameters=GPIO_PuPd
+PB6.GPIO_PuPd=GPIO_PULLUP
+PB6.Mode=Asynchronous
+PB6.Signal=USART1_TX
+PB7.GPIOParameters=GPIO_PuPd
+PB7.GPIO_PuPd=GPIO_PULLUP
+PB7.Mode=Asynchronous
+PB7.Signal=USART1_RX
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=UART_HyperTerminal_DMA.ioc
+ProjectManager.ProjectName=UART_HyperTerminal_DMA
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+USART1.AutoBaudRateEnableParam=UART_ADVFEATURE_AUTOBAUDRATE_DISABLE
+USART1.BaudRate=9600
+USART1.DMADisableonRxErrorParam=ADVFEATURE_DMA_ENABLEONRXERROR
+USART1.DataInvertParam=ADVFEATURE_DATAINV_DISABLE
+USART1.IPParameters=BaudRate,WordLength,Parity,StopBits,Mode,OverSampling,OneBitSampling,AutoBaudRateEnableParam,TxPinLevelInvertParam,RxPinLevelInvertParam,DataInvertParam,SwapParam,OverrunDisableParam,DMADisableonRxErrorParam,MSBFirstParam,VirtualMode-Asynchronous
+USART1.MSBFirstParam=ADVFEATURE_MSBFIRST_DISABLE
+USART1.Mode=MODE_TX_RX
+USART1.OneBitSampling=UART_ONE_BIT_SAMPLE_DISABLE
+USART1.OverSampling=UART_OVERSAMPLING_16
+USART1.OverrunDisableParam=ADVFEATURE_OVERRUN_ENABLE
+USART1.Parity=PARITY_ODD
+USART1.RxPinLevelInvertParam=ADVFEATURE_RXINV_DISABLE
+USART1.StopBits=STOPBITS_1
+USART1.SwapParam=ADVFEATURE_SWAP_DISABLE
+USART1.TxPinLevelInvertParam=ADVFEATURE_TXINV_DISABLE
+USART1.VirtualMode-Asynchronous=VM_ASYNC
+USART1.WordLength=WORDLENGTH_8B
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/readme.txt b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/readme.txt
new file mode 100644
index 000000000..e734aea1d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_DMA/readme.txt
@@ -0,0 +1,141 @@
+/**
+  @page UART_HyperTerminal_DMA UART Hyperterminal DMA Example
+
+  @verbatim
+  ******************************************************************************
+  * @file    UART/UART_HyperTerminal_DMA/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the UART Hyperterminal example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+UART transmission (transmit/receive) in DMA mode
+between a board and an HyperTerminal PC application.
+
+Board: NUCLEO-WB35CE (embeds a STM32WB35CE device)
+Tx Pin: PB6
+Rx Pin: PB7
+   _________________________
+  |           ______________|                       _______________
+  |          |USART         |                      | HyperTerminal |
+  |          |              |                      |               |
+  |          |           TX |______________________|RX             |
+  |          |              |                      |               |
+  |          |              |     RS232 Cable      |               |
+  |          |              |                      |               |
+  |          |           RX |______________________|TX             |
+  |          |              |                      |               |
+  |          |______________|                      |_______________|
+  |                         |
+  |                         |
+  |                         |
+  |                         |
+  |_STM32_Board_____________|
+
+At the beginning of the main program the HAL_Init() function is called to reset
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz for STM32WBxx Devices.
+
+The UART peripheral configuration is ensured by the HAL_UART_Init() function.
+This later is calling the HAL_UART_MspInit() function which core is implementing
+the configuration of the needed UART resources according to the used hardware (CLOCK,
+GPIO, DMA and NVIC). You may update this function to change UART configuration.
+
+The UART/Hyperterminal communication is then initiated.
+The HAL_UART_Receive_DMA() and the HAL_UART_Transmit_DMA() functions allow respectively
+the reception of Data from Hyperterminal and the transmission of a predefined data
+buffer.
+
+The Asynchronous communication aspect of the UART is clearly highlighted as the
+data buffers transmission/reception to/from Hyperterminal are done simultaneously.
+
+For this example the TxBuffer (aTxStartMessage) is predefined and the RxBuffer (aRxBuffer)
+size is limited to 10 data by the mean of the RXBUFFERSIZE define in the main.c file.
+
+In a first step the TxBuffer buffer content will be displayed in the Hyperterminal
+interface and the received data will be stored in the RxBuffer buffer.
+In a second step the received data in the RxBuffer buffer will be sent back to
+Hyperterminal and displayed.
+The end of this two steps are monitored through the HAL_UART_GetState() function
+result.
+
+NUCLEO-WB35CE board LEDs are used to monitor the transfer status:
+ - LED2 turns ON if transmission/reception is complete and OK.
+ - LED3 turns ON when when there is an error in transmission/reception process.
+
+The UART is configured as follows:
+    - BaudRate = 9600 baud
+    - Word Length = 8 Bits (7 data bit + 1 parity bit)
+    - One Stop Bit
+    - Odd parity
+    - Hardware flow control disabled (RTS and CTS signals)
+    - Reception and transmission are enabled in the time
+
+@note When the parity is enabled, the computed parity is inserted at the MSB
+position of the transmitted data.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+Connectivity, UART, Printf, Baud rate, RS-232, HyperTerminal, full-duplex, HyperTerminal, DMA,
+Transmission, Reception, Asynchronous
+
+@par Directory contents
+
+  - UART/UART_HyperTerminal_DMA/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - UART/UART_HyperTerminal_DMA/Inc/stm32wbxx_it.h          DMA interrupt handlers header file
+  - UART/UART_HyperTerminal_DMA/Inc/main.h                  Header for main.c module
+  - UART/UART_HyperTerminal_DMA/Src/stm32wbxx_it.c          DMA interrupt handlers
+  - UART/UART_HyperTerminal_DMA/Src/main.c                  Main program
+  - UART/UART_HyperTerminal_DMA/Src/stm32wbxx_hal_msp.c     HAL MSP module
+  - UART/UART_HyperTerminal_DMA/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+  - NUCLEO-WB35CE Set-up
+     - Connect USART1 TX (PB.06 (Pin 35 in CN10)) to RX pin of PC serial port (or USB to UART adapter)
+       and USART1 RX (PB.07 (Pin 37 in CN10)) to TX pin of PC serial port (or USB to UART adapter).
+     
+
+  - Hyperterminal configuration:
+    - Data Length = 7 Bits
+    - One Stop Bit
+    - Odd parity
+    - BaudRate = 9600 baud
+    - Flow control: None
+
+@par How to use it ?
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/.extSettings b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/Project.eww
new file mode 100644
index 000000000..79e40fb7a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\UART_HyperTerminal_IT.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/UART_HyperTerminal_IT.ewd b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/UART_HyperTerminal_IT.ewd
new file mode 100644
index 000000000..ea06f2738
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/UART_HyperTerminal_IT.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		UART_HyperTerminal_IT
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/UART_HyperTerminal_IT.ewp b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/UART_HyperTerminal_IT.ewp
new file mode 100644
index 000000000..9630dc088
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/UART_HyperTerminal_IT.ewp
@@ -0,0 +1,1125 @@
+
+
+  3
+  
+    UART_HyperTerminal_IT
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Inc/main.h
new file mode 100644
index 000000000..aa70503e7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Inc/main.h
@@ -0,0 +1,77 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_HyperTerminal_IT/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+#define COUNTOF(__BUFFER__)   (sizeof(__BUFFER__) / sizeof(*(__BUFFER__)))
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+/* Size of Transmission buffer */
+#define TXSTARTMESSAGESIZE                   (COUNTOF(aTxStartMessage) - 1)
+#define TXENDMESSAGESIZE                     (COUNTOF(aTxEndMessage) - 1)
+
+/* Size of Reception buffer */
+#define RXBUFFERSIZE                      10
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..7353fcbbb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..90ad9b40c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Inc/stm32wbxx_it.h
@@ -0,0 +1,65 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_HyperTerminal_IT/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void USART1_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/MDK-ARM/UART_HyperTerminal_IT.uvoptx b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/MDK-ARM/UART_HyperTerminal_IT.uvoptx
new file mode 100644
index 000000000..6ff27010e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/MDK-ARM/UART_HyperTerminal_IT.uvoptx
@@ -0,0 +1,521 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    UART_HyperTerminal_IT
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+      stm32wbxx_hal_uart.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+      stm32wbxx_hal_uart_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      24
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/MDK-ARM/UART_HyperTerminal_IT.uvprojx b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/MDK-ARM/UART_HyperTerminal_IT.uvprojx
new file mode 100644
index 000000000..9c492e2f7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/MDK-ARM/UART_HyperTerminal_IT.uvprojx
@@ -0,0 +1,551 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      UART_HyperTerminal_IT
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          UART_HyperTerminal_IT\
+          UART_HyperTerminal_IT
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_uart.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+            
+            
+              stm32wbxx_hal_uart_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..34125ec29
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/.project
new file mode 100644
index 000000000..a0859122a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/.project
@@ -0,0 +1,155 @@
+
+
+	UART_HyperTerminal_IT
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			UART_HyperTerminal_IT.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/UART_HyperTerminal_IT.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Src/main.c
new file mode 100644
index 000000000..72551ecd8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Src/main.c
@@ -0,0 +1,377 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_HyperTerminal_IT/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use UART HAL API to transmit
+  *          and receive a data buffer with a communication process based on
+  *          Interrupt transfer.
+  *          The communication is done with the Hyperterminal PC application.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef huart1;
+
+/* USER CODE BEGIN PV */
+/* Buffer used for transmission */
+uint8_t aTxStartMessage[] = "\n\r ****UART-Hyperterminal communication based on IT ****\n\r Enter 10 characters using keyboard :\n\r";
+uint8_t aTxEndMessage[] = "\n\r Example Finished\n\r";
+
+/* Buffer used for reception */
+uint8_t aRxBuffer[RXBUFFERSIZE];
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_USART1_UART_Init(void);
+/* USER CODE BEGIN PFP */
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* Configure leds */
+  /* Configure LED2 and LED3 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_USART1_UART_Init();
+  /* USER CODE BEGIN 2 */
+
+  /*##-1- Start the transmission process #####################################*/
+  /* While the UART in reception process, user can transmit data through
+     "aTxBuffer" buffer */
+  if(HAL_UART_Transmit_IT(&huart1, (uint8_t*)aTxStartMessage, TXSTARTMESSAGESIZE)!= HAL_OK)
+  {
+    /* Transfer error in transmission process */
+    Error_Handler();
+  }
+
+  /*##-2- Put UART peripheral in reception process ###########################*/
+  /* Any data received will be stored in "aRxBuffer" buffer : the number max of
+     data received is 10 */
+  if(HAL_UART_Receive_IT(&huart1, (uint8_t *)aRxBuffer, RXBUFFERSIZE) != HAL_OK)
+  {
+    /* Transfer error in reception process */
+    Error_Handler();
+  }
+
+  /*##-3- Wait for the end of the transfer ###################################*/
+  /*  Before starting a new communication transfer, you need to check the current
+      state of the peripheral; if its busy you need to wait for the end of current
+      transfer before starting a new one.
+      For simplicity reasons, this example is just waiting till the end of the
+      transfer, but application may perform other tasks while transfer operation
+      is ongoing. */
+  while (HAL_UART_GetState(&huart1) != HAL_UART_STATE_READY)
+  {
+  }
+
+  /*##-4- Send the received Buffer ###########################################*/
+  if(HAL_UART_Transmit_IT(&huart1, (uint8_t*)aRxBuffer, RXBUFFERSIZE)!= HAL_OK)
+  {
+    /* Transfer error in transmission process */
+    Error_Handler();
+  }
+
+  /*##-5- Wait for the end of the transfer ###################################*/
+  /*  Before starting a new communication transfer, you need to check the current
+      state of the peripheral; if its busy you need to wait for the end of current
+      transfer before starting a new one.
+      For simplicity reasons, this example is just waiting till the end of the
+      transfer, but application may perform other tasks while transfer operation
+      is ongoing. */
+  while (HAL_UART_GetState(&huart1) != HAL_UART_STATE_READY)
+  {
+  }
+
+  /*##-6- Send the End Message ###############################################*/
+  if(HAL_UART_Transmit_IT(&huart1, (uint8_t*)aTxEndMessage, TXENDMESSAGESIZE)!= HAL_OK)
+  {
+    /* Transfer error in transmission process */
+    Error_Handler();
+  }
+
+  /*##-7- Wait for the end of the transfer ###################################*/
+  while (HAL_UART_GetState(&huart1) != HAL_UART_STATE_READY)
+  {
+  }
+
+  /* Turn on LED2 if test passes then enter infinite loop */
+  BSP_LED_On(LED2);
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 9600;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_ODD;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+
+/**
+  * @brief  Tx Transfer completed callback
+  * @param  UartHandle: UART handle.
+  * @note   This example shows a simple way to report end of IT Tx transfer, and
+  *         you can add your own implementation.
+  * @retval None
+  */
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *UartHandle)
+{
+}
+
+/**
+  * @brief  Rx Transfer completed callback
+  * @param  UartHandle: UART handle
+  * @note   This example shows a simple way to report end of IT Rx transfer, and
+  *         you can add your own implementation.
+  * @retval None
+  */
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *UartHandle)
+{
+}
+
+/**
+  * @brief  UART error callbacks
+  * @param  UartHandle: UART handle
+  * @note   This example shows a simple way to report transfer error, and you can
+  *         add your own implementation.
+  * @retval None
+  */
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *UartHandle)
+{
+  /* Turn LED3 on: Transfer error in reception/transmission process */
+  BSP_LED_On(LED3);
+}
+
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  while(1);
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..c67b1f3b8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,154 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_HyperTerminal_IT/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspInit 0 */
+
+  /* USER CODE END USART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**USART1 GPIO Configuration    
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* USART1 interrupt Init */
+    HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspInit 1 */
+
+  /* USER CODE END USART1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspDeInit 0 */
+    /* Reset peripherals */
+    __HAL_RCC_USART1_FORCE_RESET();
+    __HAL_RCC_USART1_RELEASE_RESET();
+
+  /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+  
+    /**USART1 GPIO Configuration    
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
+
+    /* USART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+  /* USER CODE END USART1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..fbc37509d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Src/stm32wbxx_it.c
@@ -0,0 +1,135 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_HyperTerminal_IT/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern UART_HandleTypeDef huart1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+
+  /* USER CODE END USART1_IRQn 0 */
+  HAL_UART_IRQHandler(&huart1);
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/UART_HyperTerminal_IT.ioc b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/UART_HyperTerminal_IT.ioc
new file mode 100644
index 000000000..dad01f931
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/UART_HyperTerminal_IT.ioc
@@ -0,0 +1,135 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=USART1
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB6
+Mcu.Pin1=PB7
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PB6.GPIOParameters=GPIO_PuPd
+PB6.GPIO_PuPd=GPIO_PULLUP
+PB6.Mode=Asynchronous
+PB6.Signal=USART1_TX
+PB7.GPIOParameters=GPIO_PuPd
+PB7.GPIO_PuPd=GPIO_PULLUP
+PB7.Mode=Asynchronous
+PB7.Signal=USART1_RX
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=UART_HyperTerminal_IT.ioc
+ProjectManager.ProjectName=UART_HyperTerminal_IT
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+USART1.AutoBaudRateEnableParam=UART_ADVFEATURE_AUTOBAUDRATE_DISABLE
+USART1.BaudRate=9600
+USART1.DMADisableonRxErrorParam=ADVFEATURE_DMA_ENABLEONRXERROR
+USART1.DataInvertParam=ADVFEATURE_DATAINV_DISABLE
+USART1.IPParameters=BaudRate,WordLength,Parity,StopBits,Mode,OverSampling,OneBitSampling,AutoBaudRateEnableParam,TxPinLevelInvertParam,RxPinLevelInvertParam,DataInvertParam,SwapParam,OverrunDisableParam,DMADisableonRxErrorParam,MSBFirstParam,VirtualMode-Asynchronous
+USART1.MSBFirstParam=ADVFEATURE_MSBFIRST_DISABLE
+USART1.Mode=MODE_TX_RX
+USART1.OneBitSampling=UART_ONE_BIT_SAMPLE_DISABLE
+USART1.OverSampling=UART_OVERSAMPLING_16
+USART1.OverrunDisableParam=ADVFEATURE_OVERRUN_ENABLE
+USART1.Parity=PARITY_ODD
+USART1.RxPinLevelInvertParam=ADVFEATURE_RXINV_DISABLE
+USART1.StopBits=STOPBITS_1
+USART1.SwapParam=ADVFEATURE_SWAP_DISABLE
+USART1.TxPinLevelInvertParam=ADVFEATURE_TXINV_DISABLE
+USART1.VirtualMode-Asynchronous=VM_ASYNC
+USART1.WordLength=WORDLENGTH_8B
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/readme.txt b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/readme.txt
new file mode 100644
index 000000000..db4746c04
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_HyperTerminal_IT/readme.txt
@@ -0,0 +1,141 @@
+/**
+  @page UART_Hyperterminal_IT UART Hyperterminal IT example
+
+  @verbatim
+  ******************************************************************************
+  * @file    UART/UART_Hyperterminal_IT/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the UART Hyperterminal example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+UART transmission (transmit/receive) in Interrupt mode between a board and
+an HyperTerminal PC application.
+
+Board: NUCLEO-WB35CE
+Tx Pin: PB.06 (Pin 35 in CN10)
+Rx Pin: PB.07 (Pin 37 in CN10)
+   _________________________
+  |           ______________|                       _______________
+  |          |USART         |                      | HyperTerminal |
+  |          |              |                      |               |
+  |          |           TX |______________________|RX             |
+  |          |              |                      |               |
+  |          |              |     RS232 Cable      |               |
+  |          |              |                      |               |
+  |          |           RX |______________________|TX             |
+  |          |              |                      |               |
+  |          |______________|                      |_______________|
+  |                         |
+  |                         |
+  |                         |
+  |                         |
+  |_STM32_Board_____________|
+
+At the beginning of the main program the HAL_Init() function is called to reset
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz for STM32WBxx Devices.
+
+The UART peripheral configuration is ensured by the HAL_UART_Init() function.
+This later is calling the HAL_UART_MspInit() function which core is implementing
+the configuration of the needed UART resources according to the used hardware (CLOCK,
+GPIO and NVIC). You may update this function to change UART configuration.
+
+The UART/Hyperterminal communication is then initiated.
+The HAL_UART_Receive_IT() and the HAL_UART_Transmit_IT() functions allow respectively
+the reception of Data from Hyperterminal and the transmission of a predefined data
+buffer.
+
+The Asynchronous communication aspect of the UART is clearly highlighted as the
+data buffers transmission/reception to/from Hyperterminal are done simultaneously.
+
+For this example the TxBuffer (aTxStartMessage) is predefined and the RxBuffer (aRxBuffer)
+size is limited to 10 data by the mean of the RXBUFFERSIZE define in the main.c file.
+
+In a first step the TxBuffer buffer content will be displayed in the Hyperterminal
+interface and the received data will be stored in the RxBuffer buffer.
+In a second step the received data in the RxBuffer buffer will be sent back to
+Hyperterminal and displayed.
+The end of this two steps are monitored through the HAL_UART_GetState() function
+result.
+
+NUCLEO-WB35CE board LEDs are used to monitor the transfer status:
+ - LED2 turns ON if transmission/reception is complete and OK.
+ - LED3 turns ON when when there is an error in transmission/reception process.
+
+The UART is configured as follows:
+    - BaudRate = 9600 baud
+    - Word Length = 8 Bits (7 data bit + 1 parity bit)
+    - One Stop Bit
+    - Odd parity
+    - Hardware flow control disabled (RTS and CTS signals)
+    - Reception and transmission are enabled in the time
+
+@note When the parity is enabled, the computed parity is inserted at the MSB
+position of the transmitted data.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+Connectivity, UART, Printf, Baud rate, RS-232, HyperTerminal, full-duplex, HyperTerminal,
+Transmission, Reception, Asynchronous, interrupt
+
+@par Directory contents
+
+  - UART/UART_HyperTerminal_IT/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - UART/UART_HyperTerminal_IT/Inc/stm32wbxx_it.h          IT interrupt handlers header file
+  - UART/UART_HyperTerminal_IT/Inc/main.h                  Header for main.c module
+  - UART/UART_HyperTerminal_IT/Src/stm32wbxx_it.c          IT interrupt handlers
+  - UART/UART_HyperTerminal_IT/Src/main.c                  Main program
+  - UART/UART_HyperTerminal_IT/Src/stm32wbxx_hal_msp.c     HAL MSP module
+  - UART/UART_HyperTerminal_IT/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+  - NUCLEO-WB35CE Set-up
+    
+    - Connect USART1 TX (PB6) to RX pin of PC serial port (or USB to UART adapter)
+      and USART1 RX (PB7) to TX pin of PC serial port (or USB to UART adapter).
+
+  - Hyperterminal configuration:
+    - Data Length = 7 Bits
+    - One Stop Bit
+    - Odd parity
+    - BaudRate = 9600 baud
+    - Flow control: None
+
+@par How to use it ?
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/.extSettings b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/Project.eww
new file mode 100644
index 000000000..c213e83fe
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\UART_Printf.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/UART_Printf.ewd b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/UART_Printf.ewd
new file mode 100644
index 000000000..6369e230a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/UART_Printf.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		UART_Printf
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/UART_Printf.ewp b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/UART_Printf.ewp
new file mode 100644
index 000000000..a885cc05d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/UART_Printf.ewp
@@ -0,0 +1,1125 @@
+
+
+  3
+  
+    UART_Printf
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Inc/main.h
new file mode 100644
index 000000000..cf429bf64
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Inc/main.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_Printf/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include 
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..7353fcbbb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..6fd7c23b3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Inc/stm32wbxx_it.h
@@ -0,0 +1,66 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_Printf/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/MDK-ARM/UART_Printf.uvoptx b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/MDK-ARM/UART_Printf.uvoptx
new file mode 100644
index 000000000..48ea2a5f4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/MDK-ARM/UART_Printf.uvoptx
@@ -0,0 +1,521 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    UART_Printf
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U0667FF303337554E43181419 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      2
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+      stm32wbxx_hal_uart.c
+      0
+      0
+    
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+      stm32wbxx_hal_uart_ex.c
+      0
+      0
+    
+    
+      5
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      5
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      5
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      5
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      5
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      5
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      5
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      5
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      5
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      5
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      5
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      5
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      24
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/MDK-ARM/UART_Printf.uvprojx b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/MDK-ARM/UART_Printf.uvprojx
new file mode 100644
index 000000000..cb4221a73
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/MDK-ARM/UART_Printf.uvprojx
@@ -0,0 +1,552 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      UART_Printf
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          UART_Printf\
+          UART_Printf
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_uart.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+            
+            
+              stm32wbxx_hal_uart_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..8638da532
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/.project
new file mode 100644
index 000000000..f0e7bedbb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/.project
@@ -0,0 +1,155 @@
+
+
+	UART_Printf
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			UART_Printf.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/UART_Printf.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Src/main.c
new file mode 100644
index 000000000..ecd9da7a5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Src/main.c
@@ -0,0 +1,292 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_Printf/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example shows how to retarget the C library printf function
+  *          to the UART.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef huart1;
+
+/* USER CODE BEGIN PV */
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_USART1_UART_Init(void);
+/* USER CODE BEGIN PFP */
+#ifdef __GNUC__
+/* With GCC, small printf (option LD Linker->Libraries->Small printf
+   set to 'Yes') calls __io_putchar() */
+#define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
+#else
+#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
+#endif /* __GNUC__ */
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* Initialize BSP Led for LED3 */
+  BSP_LED_Init(LED3);
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_USART1_UART_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Output a message on Hyperterminal using printf function */
+  printf("\n\r UART Printf Example: retarget the C library printf function to the UART\n\r");
+  printf("** Test finished successfully. ** \n\r");
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_ODD;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Retargets the C library printf function to the USART.
+  * @param  None
+  * @retval None
+  */
+PUTCHAR_PROTOTYPE
+{
+  /* Place your implementation of fputc here */
+  /* e.g. write a character to the USART1 and Loop until the end of transmission */
+  HAL_UART_Transmit(&huart1, (uint8_t *)&ch, 1, 0xFFFF);
+
+  return ch;
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  while (1);
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..f4fc9f083
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,147 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_Printf/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspInit 0 */
+
+  /* USER CODE END USART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**USART1 GPIO Configuration    
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN USART1_MspInit 1 */
+
+  /* USER CODE END USART1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspDeInit 0 */
+    __HAL_RCC_USART1_FORCE_RESET();
+    __HAL_RCC_USART1_RELEASE_RESET();
+  /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+  
+    /**USART1 GPIO Configuration    
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
+
+  /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+  /* USER CODE END USART1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..44339f569
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Src/stm32wbxx_it.c
@@ -0,0 +1,149 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_Printf/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/UART_Printf.ioc b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/UART_Printf.ioc
new file mode 100644
index 000000000..24a5f0766
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/UART_Printf.ioc
@@ -0,0 +1,136 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=USART1
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB6
+Mcu.Pin1=PB7
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+PB6.GPIOParameters=GPIO_PuPd
+PB6.GPIO_PuPd=GPIO_PULLUP
+PB6.Locked=true
+PB6.Mode=Asynchronous
+PB6.Signal=USART1_TX
+PB7.GPIOParameters=GPIO_PuPd
+PB7.GPIO_PuPd=GPIO_PULLUP
+PB7.Locked=true
+PB7.Mode=Asynchronous
+PB7.Signal=USART1_RX
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=UART_Printf.ioc
+ProjectManager.ProjectName=UART_Printf
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+USART1.AutoBaudRateEnableParam=UART_ADVFEATURE_AUTOBAUDRATE_DISABLE
+USART1.BaudRate=115200
+USART1.DMADisableonRxErrorParam=ADVFEATURE_DMA_ENABLEONRXERROR
+USART1.DataInvertParam=ADVFEATURE_DATAINV_DISABLE
+USART1.IPParameters=BaudRate,WordLength,Parity,StopBits,Mode,OverSampling,OneBitSampling,AutoBaudRateEnableParam,TxPinLevelInvertParam,RxPinLevelInvertParam,DataInvertParam,SwapParam,OverrunDisableParam,DMADisableonRxErrorParam,MSBFirstParam,VirtualMode-Asynchronous
+USART1.MSBFirstParam=ADVFEATURE_MSBFIRST_DISABLE
+USART1.Mode=MODE_TX_RX
+USART1.OneBitSampling=UART_ONE_BIT_SAMPLE_DISABLE
+USART1.OverSampling=UART_OVERSAMPLING_16
+USART1.OverrunDisableParam=ADVFEATURE_OVERRUN_ENABLE
+USART1.Parity=PARITY_ODD
+USART1.RxPinLevelInvertParam=ADVFEATURE_RXINV_DISABLE
+USART1.StopBits=STOPBITS_1
+USART1.SwapParam=ADVFEATURE_SWAP_DISABLE
+USART1.TxPinLevelInvertParam=ADVFEATURE_TXINV_DISABLE
+USART1.VirtualMode-Asynchronous=VM_ASYNC
+USART1.WordLength=WORDLENGTH_8B
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/readme.txt b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/readme.txt
new file mode 100644
index 000000000..92e43e0c0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/UART/UART_Printf/readme.txt
@@ -0,0 +1,111 @@
+/**
+  @page UART_Printf UART Printf example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    UART/UART_Printf/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the UART Printf example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+Re-routing of the C library printf function to the UART.
+The UART outputs a message on the HyperTerminal.
+
+Board: NUCLEO-WB35CE
+Tx Pin: PB.06 (Pin 35 in CN10)
+Rx Pin: PB.07 (Pin 37 in CN10)
+   _________________________ 
+  |           ______________|                       _______________
+  |          |USART         |                      | HyperTerminal |
+  |          |              |                      |               |
+  |          |           TX |______________________|RX             |
+  |          |              |                      |               |
+  |          |              |    ST-Link Cable     |               |
+  |          |              |                      |               |
+  |          |           RX |______________________|TX             |
+  |          |              |                      |               |
+  |          |______________|                      |_______________|
+  |                         |
+  |                         |
+  |                         |
+  |                         |
+  |_STM32_Board_____________|                      
+
+LED3 turns ON when there is an error.
+
+The USART is configured as follows:
+    - BaudRate = 115200 baud
+    - Word Length = 8 Bits (7 data bit + 1 parity bit)
+    - One Stop Bit
+    - Odd parity
+    - Hardware flow control disabled (RTS and CTS signals)
+    - Reception and transmission are enabled in the time
+
+@note When the parity is enabled, the computed parity is inserted at the MSB
+position of the transmitted data.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Keywords
+
+Connectivity, UART, Printf, Baud rate, RS-232, HyperTerminal, full-duplex, HyperTerminal, 
+Transmission, Reception, Asynchronous, interrupt
+
+@par Directory contents
+
+  - UART/UART_Printf/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - UART/UART_Printf/Inc/stm32wbxx_it.h          IT interrupt handlers header file
+  - UART/UART_Printf/Inc/main.h                  Header for main.c module
+  - UART/UART_Printf/Src/stm32wbxx_it.c          Interrupt handlers
+  - UART/UART_Printf/Src/main.c                  Main program
+  - UART/UART_Printf/Src/stm32wbxx_hal_msp.c     HAL MSP module
+  - UART/UART_Printf/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.   
+
+  - NUCLEO-WB35CE Set-up
+    - Connect ST-Link cable to the PC USB port to display data on the HyperTerminal.
+      A virtual COM port will then appear in the HyperTerminal.
+
+  - Hyperterminal configuration:
+    - Data Length = 7 Bits
+    - One Stop Bit
+    - Odd parity
+    - BaudRate = 115200 baud
+    - Flow control: None 
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/.extSettings b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/.extSettings
new file mode 100644
index 000000000..271dc2368
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=TIM;WWDG
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/Project.eww
new file mode 100644
index 000000000..00ad00f07
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\WWDG_Example.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/WWDG_Example.ewd b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/WWDG_Example.ewd
new file mode 100644
index 000000000..9f142cdcc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/WWDG_Example.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		WWDG_Example
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/WWDG_Example.ewp b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/WWDG_Example.ewp
new file mode 100644
index 000000000..8629a1d38
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/WWDG_Example.ewp
@@ -0,0 +1,1122 @@
+
+
+  3
+  
+    WWDG_Example
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Inc/main.h
new file mode 100644
index 000000000..bd6c7c912
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    WWDG/WWDG_Example/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..dcd450854
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..cf8e3bef1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    WWDG/WWDG_Example/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void EXTI0_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/MDK-ARM/WWDG_Example.uvoptx b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/MDK-ARM/WWDG_Example.uvoptx
new file mode 100644
index 000000000..a1b3c54e0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/MDK-ARM/WWDG_Example.uvoptx
@@ -0,0 +1,529 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    WWDG_Example
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          ARMRTXEVENTFLAGS
+          -L70 -Z18 -C0 -M0 -T1
+        
+        
+          0
+          DLGTARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          
+        
+        
+          0
+          DLGUARM
+          (105=-1,-1,-1,-1,0)
+        
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        1
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      2
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c
+      stm32wbxx_hal_wwdg.c
+      0
+      0
+    
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      5
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      5
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      5
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      5
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      5
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      5
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      5
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      5
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      5
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      5
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      5
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/MDK-ARM/WWDG_Example.uvprojx b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/MDK-ARM/WWDG_Example.uvprojx
new file mode 100644
index 000000000..0825c2874
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/MDK-ARM/WWDG_Example.uvprojx
@@ -0,0 +1,547 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      WWDG_Example
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          WWDG_Example\
+          WWDG_Example
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_wwdg.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..44b4b38b4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/.cproject
@@ -0,0 +1,170 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/.project
new file mode 100644
index 000000000..c3c652c71
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/.project
@@ -0,0 +1,150 @@
+
+
+	WWDG_Example
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			WWDG_Example.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/WWDG_Example.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_wwdg.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/.settings/language.settings.xml b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/.settings/language.settings.xml
new file mode 100644
index 000000000..b7c4a944b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/.settings/language.settings.xml
@@ -0,0 +1,27 @@
+
+
+	
+		
+			
+			
+			
+			
+			
+				
+				
+			
+		
+	
+	
+		
+			
+			
+			
+			
+			
+				
+				
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Src/main.c b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Src/main.c
new file mode 100644
index 000000000..477ee7b0a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Src/main.c
@@ -0,0 +1,313 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    WWDG/WWDG_Example/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use the WWDG HAL API
+  *          to update at regular period the WWDG counter and how to generate
+  *          a software fault generating an MCU WWDG reset on expiry of a
+  *          programmed time period.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define WWDG_WINDOW    0x50
+#define WWDG_COUNTER   0x7F
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+WWDG_HandleTypeDef hwwdg;
+
+/* USER CODE BEGIN PV */
+uint32_t WwdgStatus = 0;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_WWDG_Init(void);
+/* USER CODE BEGIN PFP */
+static uint32_t TimeoutCalculation(uint32_t timevalue);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+ uint32_t delay;
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* Configure LED2 and LED1 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED1);
+
+  /*##-1- Check if the system has resumed from WWDG reset ####################*/
+  if (__HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST) != 0x00u)
+  {
+    /* WWDGRST flag set: Turn LED2 on and set WWDGStatus */
+    WwdgStatus = 1;
+    BSP_LED_On(LED2);
+
+    /* Insert 4s delay */
+    HAL_Delay(4000);
+
+    /* Prior to clear WWDGRST flag: Turn LED2 off */
+    BSP_LED_Off(LED2);
+  }
+
+  /* Clear reset flags in any case */
+  __HAL_RCC_CLEAR_RESET_FLAGS();
+  WwdgStatus = 0;
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_WWDG_Init();
+  /* USER CODE BEGIN 2 */
+  /* Configure User push-button (SW1) */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+
+  /* calculate delay to enter window. Add 1ms to secure round number to upper number  */
+  delay = TimeoutCalculation((hwwdg.Init.Counter-hwwdg.Init.Window) + 1) + 1;
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    /* Toggle LED2 */
+    BSP_LED_Toggle(LED2);
+
+    /* Insert calculated delay */
+    HAL_Delay(delay);
+
+    if (HAL_WWDG_Refresh(&hwwdg) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief WWDG Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_WWDG_Init(void)
+{
+
+  /* USER CODE BEGIN WWDG_Init 0 */
+     /*  Default WWDG Configuration:
+      1] Set WWDG counter to 0x7F  and window to 0x50
+      2] Set Prescaler to WWDG_PRESCALER_8
+
+      Timing calculation:
+      a) WWDG clock counter period (in ms) = (4096 * WWDG_PRESCALER_8) / (PCLK1 / 1000)
+                                           = 0,512 ms
+      b) WWDG timeout (in ms) = (0x7F + 1) * 0,512
+                              ~= 65,53 ms
+      => After refresh, WWDG will expires after 65,53 ms and generate reset if
+      counter is not reloaded.
+      c) Time to enter inside window
+      Window timeout (in ms) = (127 - 80 + 1) * 0,512
+                             = 24,57 ms */
+  /* USER CODE END WWDG_Init 0 */
+
+  /* USER CODE BEGIN WWDG_Init 1 */
+
+  /* USER CODE END WWDG_Init 1 */
+  hwwdg.Instance = WWDG;
+  hwwdg.Init.Prescaler = WWDG_PRESCALER_8;
+  hwwdg.Init.Window = WWDG_WINDOW;
+  hwwdg.Init.Counter = WWDG_COUNTER;
+  hwwdg.Init.EWIMode = WWDG_EWI_DISABLE;
+  if (HAL_WWDG_Init(&hwwdg) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN WWDG_Init 2 */
+
+  /* USER CODE END WWDG_Init 2 */
+
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Timeout calculation function.
+  *         This function calculates any timeout related to 
+  *         WWDG with given prescaler and system clock.
+  * @param  timevalue: period in term of WWDG counter cycle.
+  * @retval None
+  */
+static uint32_t TimeoutCalculation(uint32_t timevalue)
+{
+  uint32_t timeoutvalue = 0;
+  uint32_t pclk1 = 0;
+  uint32_t wdgtb = 0;
+
+  /* considering APB divider is still 1, use HCLK value */
+  pclk1 = HAL_RCC_GetPCLK1Freq();
+
+  /* get prescaler */
+  wdgtb = (1 << ((hwwdg.Init.Prescaler) >> WWDG_CFR_WDGTB_Pos)); /* 2^WDGTB[1:0] */
+
+  /* calculate timeout */
+  timeoutvalue = ((4096 * wdgtb * timevalue) / (pclk1 / 1000));
+
+  return timeoutvalue;
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* Turn LED1 on */
+  BSP_LED_On(LED1);
+
+  WwdgStatus = 0xE;
+  while(1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..a6955784e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,101 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    WWDG/WWDG_Example/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief WWDG MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hwwdg: WWDG handle pointer
+* @retval None
+*/
+void HAL_WWDG_MspInit(WWDG_HandleTypeDef* hwwdg)
+{
+  if(hwwdg->Instance==WWDG)
+  {
+  /* USER CODE BEGIN WWDG_MspInit 0 */
+
+  /* USER CODE END WWDG_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_WWDG_CLK_ENABLE();
+  /* USER CODE BEGIN WWDG_MspInit 1 */
+
+  /* USER CODE END WWDG_MspInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..d47f72ee8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Src/stm32wbxx_it.c
@@ -0,0 +1,222 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    WWDG/WWDG_Example/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+* @brief This function handles EXTI line 0 interrupts.
+  * @param  None
+  * @retval None
+*/
+void EXTI0_IRQHandler(void)
+{
+  /* As the following address is invalid (not mapped), a Hardfault exception
+  will be generated with an infinite loop and when the WWDG counter falls to 63
+  the WWDG reset occurs */
+  *(__IO uint32_t *) 0xA0003000 = 0xFF;
+
+}
+
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/WWDG_Example.ioc b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/WWDG_Example.ioc
new file mode 100644
index 000000000..b39bb0498
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/WWDG_Example.ioc
@@ -0,0 +1,116 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=WWDG
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.Pin1=VP_WWDG_VS_WWDG
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=WWDG_Example.ioc
+ProjectManager.ProjectName=WWDG_Example
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+VP_WWDG_VS_WWDG.Mode=WWDG_Activate
+VP_WWDG_VS_WWDG.Signal=WWDG_VS_WWDG
+WWDG.Counter=WWDG_COUNTER
+WWDG.EWIMode=WWDG_EWI_DISABLE
+WWDG.IPParameters=Prescaler,Window,Counter,EWIMode
+WWDG.IPParametersWithoutCheck=Window,Counter
+WWDG.Prescaler=WWDG_PRESCALER_8
+WWDG.Window=WWDG_WINDOW
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/readme.txt b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/readme.txt
new file mode 100644
index 000000000..43dd3679e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples/WWDG/WWDG_Example/readme.txt
@@ -0,0 +1,109 @@
+/**
+  @page WWDG_Example Window Watchdog example
+
+  @verbatim
+  ******************************************************************************
+  * @file    WWDG/WWDG_Example/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the Window Watchdog example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+Configuration of the HAL API to periodically update the WWDG counter and simulate a software fault that
+generates an MCU WWDG reset when a predefined time period has elapsed.
+
+At the beginning of the main program the HAL_Init() function is called to reset
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz.
+
+The WWDG peripheral configuration is ensured by the HAL_WWDG_Init() function.
+This later is calling the HAL_WWDG_MspInit()function which core is implementing
+the configuration of the needed WWDG resources according to the used hardware (CLOCK
+and NVIC). You may update this function to change WWDG configuration.
+
+The WWDG timeout is set, through counter value, to 65,53 ms.
+The refresh window is set in order to make user wait 24,57 ms after a wadchdog refresh,
+before writing again counter. Hence the WWDG counter is refreshed each (24,57 + 1) ms in the
+main program infinite loop to prevent a WWDG reset.
+
+LED2 is toggling at same frequency, indicating that the program is running.
+
+
+An EXTI Line is connected to a GPIO pin, and configured to generate an interrupt
+on the rising edge of the signal.
+
+The EXTI Line is used to simulate a software failure: once the EXTI Line event
+occurs by pressing the User push-button (SW1) (PA.00), the corresponding interrupt is served.
+
+In the ISR, a write to invalid address generates a Hardfault exception containing
+an infinite loop and preventing to return to main program (the WWDG counter is
+not refreshed).
+As a result, when the WWDG counter falls to 0x3F, WWDG reset occurs.
+
+If the WWDG reset is generated, after the system resumes from reset, LED2 is turned ON for 4 seconds.
+
+If the EXTI Line event does not occur, the WWDG counter is indefinitely refreshed
+in the main program infinite loop, and there is no WWDG reset.
+
+LED1 is turned ON and remains ON if any error occurs.
+
+@note This example must be tested in standalone mode (not in debug).
+
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate
+      delay (in milliseconds) based on variable incremented in SysTick ISR. This
+      implies that if HAL_Delay() is called from a peripheral ISR process, then
+      the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+
+@par Keywords
+
+System, WWDG, EXTI, update counter, MCU Reset, Timeout, Software fault
+
+@par Directory contents
+
+  - WWDG/WWDG_Example/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - WWDG/WWDG_Example/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - WWDG/WWDG_Example/Inc/main.h                        Header for main.c module
+  - WWDG/WWDG_Example/Src/stm32wbxx_it.c          Interrupt handlers
+  - WWDG/WWDG_Example/Src/main.c                        Main program
+  - WWDG/WWDG_Example/Src/stm32wbxx_hal_msp.c     HAL MSP file
+  - WWDG/WWDG_Example/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ?
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/ADC_AnalogWatchdog_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/ADC_AnalogWatchdog_Init.ioc
new file mode 100644
index 000000000..c1d9b2db6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/ADC_AnalogWatchdog_Init.ioc
@@ -0,0 +1,154 @@
+#MicroXplorer Configuration settings - do not modify
+ADC1.AWD1HighThreshold=ADC_AWD_THRESHOLD_HIGH
+ADC1.AWD1ITMode=ENABLE
+ADC1.AWD1LowThreshold=ADC_AWD_THRESHOLD_LOW
+ADC1.Channel-4\#ChannelRegularConversion=ADC_CHANNEL_6
+ADC1.Channel-IN=ADC_CHANNEL_VREFINT
+ADC1.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV2
+ADC1.ContinuousConvMode=ENABLE
+ADC1.DMAContinuousRequests=DISABLE
+ADC1.DataAlign=ADC_DATAALIGN_RIGHT
+ADC1.DiscontinuousConvMode=DISABLE
+ADC1.EOCSelection=ADC_EOC_SINGLE_CONV
+ADC1.EnableAnalogWatchDog1=true
+ADC1.EnableAnalogWatchDog2=false
+ADC1.EnableAnalogWatchDog3=false
+ADC1.ExternalTrigConv=ADC_SOFTWARE_START
+ADC1.ExternalTrigConvEdge=ADC_EXTERNALTRIGCONVEDGE_NONE
+ADC1.IPParameters=Channel-IN,ClockPrescaler,Resolution,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,DMAContinuousRequests,EOCSelection,Overrun,LowPowerAutoWait,OversamplingMode,NbrOfConversion,ExternalTrigConv,ExternalTrigConvEdge,EnableAnalogWatchDog1,WatchdogMode,AWD1HighThreshold,AWD1LowThreshold,AWD1ITMode,EnableAnalogWatchDog2,EnableAnalogWatchDog3,Rank-4\#ChannelRegularConversion,Channel-4\#ChannelRegularConversion,master,SamplingTime-4\#ChannelRegularConversion
+ADC1.IPParametersWithoutCheck=AWD1HighThreshold,AWD1LowThreshold
+ADC1.LowPowerAutoWait=DISABLE
+ADC1.NbrOfConversion=1
+ADC1.Overrun=ADC_OVR_DATA_OVERWRITTEN
+ADC1.OversamplingMode=DISABLE
+ADC1.Rank-4\#ChannelRegularConversion=1
+ADC1.Resolution=ADC_RESOLUTION_12B
+ADC1.SamplingTime-4\#ChannelRegularConversion=ADC_SAMPLETIME_247CYCLES_5
+ADC1.ScanConvMode=ADC_SCAN_DISABLE
+ADC1.WatchdogMode=ADC_ANALOGWATCHDOG_ALL_REG
+ADC1.master=1
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=ADC1
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA0
+Mcu.Pin1=PA1
+Mcu.Pin2=PB0
+Mcu.Pin3=VP_ADC1_Vref_Input
+Mcu.Pin4=VP_SYS_VS_Systick
+Mcu.PinsNb=5
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.EXTI0_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA0.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultEXTI
+PA0.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
+PA0.GPIO_PuPd=GPIO_PULLUP
+PA0.Locked=true
+PA0.Signal=GPXTI0
+PA1.Signal=ADCx_IN6
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=false
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=ADC_AnalogWatchdog_Init.ioc
+ProjectManager.ProjectName=ADC_AnalogWatchdog_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-true,3-MX_ADC1_Init-ADC1-false-LL-true
+RCC.AHBFreq_Value=16000000
+RCC.APB1Freq_Value=16000000
+RCC.APB1TimFreq_Value=16000000
+RCC.APB2Freq_Value=16000000
+RCC.APB2TimFreq_Value=16000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=16000000
+RCC.CortexFreq_Value=16000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=16000000
+RCC.FCLKCortexFreq_Value=16000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=16000000
+RCC.HCLK3Freq_Value=16000000
+RCC.HCLKFreq_Value=16000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=16000000
+RCC.I2C3Freq_Value=16000000
+RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=16000000
+RCC.LPTIM2Freq_Value=16000000
+RCC.LPUART1Freq_Value=16000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=16000000
+RCC.PLLPoutputFreq_Value=16000000
+RCC.PLLQoutputFreq_Value=16000000
+RCC.PLLRCLKFreq_Value=16000000
+RCC.PWRFreq_Value=16000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=16000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_HSI
+RCC.USART1Freq_Value=16000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=32000000
+SH.ADCx_IN6.0=ADC1_IN6,IN6-Single-Ended
+SH.ADCx_IN6.ConfNb=1
+SH.GPXTI0.0=GPIO_EXTI0
+SH.GPXTI0.ConfNb=1
+VP_ADC1_Vref_Input.Mode=IN-Vrefint
+VP_ADC1_Vref_Input.Signal=ADC1_Vref_Input
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/ADC_AnalogWatchdog_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/ADC_AnalogWatchdog_Init.ewd
new file mode 100644
index 000000000..a2dde8a09
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/ADC_AnalogWatchdog_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		ADC_AnalogWatchdog_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/ADC_AnalogWatchdog_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/ADC_AnalogWatchdog_Init.ewp
new file mode 100644
index 000000000..88d94730e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/ADC_AnalogWatchdog_Init.ewp
@@ -0,0 +1,1089 @@
+
+
+  3
+  
+    ADC_AnalogWatchdog_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/Project.eww
new file mode 100644
index 000000000..7c4ef1c09
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\ADC_AnalogWatchdog_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Inc/main.h
new file mode 100644
index 000000000..a10337ce7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Inc/main.h
@@ -0,0 +1,113 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/ADC/ADC_AnalogWatchdog_Init/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_adc.h"
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* Define used to enable time-out management*/
+#define USE_TIMEOUT       0
+
+/**
+  * @brief Toggle periods for various blinking modes
+  */
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW  500
+#define LED_BLINK_ERROR 1000
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* IRQ Handler treatment */
+void UserButton_Callback(void);
+void AdcAnalogWatchdog1_Callback(void);
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..089cd565e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,74 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/ADC/ADC_AnalogWatchdog_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void EXTI0_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+void USER_BUTTON_IRQHANDLER(void);
+
+void ADC1_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/MDK-ARM/ADC_AnalogWatchdog_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/MDK-ARM/ADC_AnalogWatchdog_Init.uvoptx
new file mode 100644
index 000000000..0e0eee8a5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/MDK-ARM/ADC_AnalogWatchdog_Init.uvoptx
@@ -0,0 +1,357 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    ADC_AnalogWatchdog_Init
+    0x4
+    ARM-ADS
+    
+      16000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      4
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      4
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+      stm32wbxx_ll_adc.c
+      0
+      0
+    
+    
+      4
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      stm32wbxx_ll_dma.c
+      0
+      0
+    
+    
+      4
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/MDK-ARM/ADC_AnalogWatchdog_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/MDK-ARM/ADC_AnalogWatchdog_Init.uvprojx
new file mode 100644
index 000000000..fcc98a0c2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/MDK-ARM/ADC_AnalogWatchdog_Init.uvprojx
@@ -0,0 +1,482 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      ADC_AnalogWatchdog_Init
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          ADC_AnalogWatchdog_Init\
+          ADC_AnalogWatchdog_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_adc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+            
+            
+              stm32wbxx_ll_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..9f1bfb866
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..6196d7aea
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/.project
@@ -0,0 +1,90 @@
+
+
+	ADC_AnalogWatchdog_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			ADC_AnalogWatchdog_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/ADC_AnalogWatchdog_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_adc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..eea98ff9c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb35xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB35xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..4ec95844d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,159 @@
+/**
+ ******************************************************************************
+ * @file      syscalls.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..4665417ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,58 @@
+/**
+ ******************************************************************************
+ * @file      sysmem.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System Memory calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Src/main.c
new file mode 100644
index 000000000..771b96a9c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Src/main.c
@@ -0,0 +1,645 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/ADC/ADC_AnalogWatchdog_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to use a ADC peripheral
+  *          with ADC analog watchdog to monitor a channel and detect 
+  *          when the corresponding conversion data is out of window thresholds.
+  *          This example is based on the STM32WBxx ADC LL API;
+  *          Peripheral initialization done using LL unitary services functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* Definitions of ADC hardware constraints delays */
+/* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */
+/*       not timeout values:                                                  */
+/*       Timeout values for ADC operations are dependent to device clock      */
+/*       configuration (system clock versus ADC clock),                       */
+/*       and therefore must be defined in user application.                   */
+/*       Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout     */
+/*       values definition.                                                   */
+
+  /* Timeout values for ADC operations. */
+  /* (calibration, enable settling time, disable settling time, ...)          */
+  /* Values defined to be higher than worst cases: low clock frequency,       */
+  /* maximum prescalers.                                                      */
+  #define ADC_CALIBRATION_TIMEOUT_MS       (   1U)
+  #define ADC_ENABLE_TIMEOUT_MS            (   1U)
+  #define ADC_DISABLE_TIMEOUT_MS           (   1U)
+  #define ADC_STOP_CONVERSION_TIMEOUT_MS   (   1U)
+  #define ADC_CONVERSION_TIMEOUT_MS        ( 500U)
+  
+  /* Delay between ADC end of calibration and ADC enable.                     */
+  /* Delay estimation in CPU cycles: Case of ADC enable done                  */
+  /* immediately after ADC calibration, ADC clock setting slow                */
+  /* (LL_ADC_CLOCK_ASYNC_DIV32). Use a higher delay if ratio                  */
+  /* (CPU clock / ADC clock) is above 32.                                     */
+  #define ADC_DELAY_CALIB_ENABLE_CPU_CYCLES  (LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES * 32)
+  
+
+/* Definitions of environment analog values */
+  /* Value of analog reference voltage (Vref+), connected to analog voltage   */
+  /* supply Vdda (unit: mV).                                                  */
+  #define VDDA_APPLI                       (3300UL)
+
+/* Definitions of data related to this example */
+  /* Definition of ADCx analog watchdog window thresholds */
+  /* Value of ADC analog watchdog threshold high */
+  #define ADC_AWD_THRESHOLD_HIGH           (__LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B) / 2)
+  /* Value of ADC analog watchdog threshold low  */
+  #define ADC_AWD_THRESHOLD_LOW            (   0UL)
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* Variable to report status of ADC analog watchdog 1:                        */
+/*  0: ADC conversion data into AWD window                                    */
+/*  1: ADC conversion data out of AWD window                                  */
+__IO   uint8_t ubAnalogWatchdog1Status = 0U; /* Variable set into analog watchdog 1 interruption callback */
+
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_ADC1_Init(void);
+/* USER CODE BEGIN PFP */
+
+void     Activate_ADC(void);
+void     LED_On(void);
+void     LED_Off(void);
+void     LED_Blinking(uint32_t Period);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_ADC1_Init();
+  /* USER CODE BEGIN 2 */
+  
+  /* Activate ADC */
+  /* Perform ADC activation procedure to make it ready to convert. */
+  Activate_ADC();
+  
+  /* Disable SMPS: SMPS in mode step-down can impact ADC conversion accuracy. */
+  /* It is recommnended to disable SMPS (stop SMPS switching by setting it    */
+  /* in mode bypass) during ADC conversion.                                   */
+  /* Get SMPS effective operating mode */
+  if(LL_PWR_SMPS_GetEffectiveMode() == LL_PWR_SMPS_STEP_DOWN)
+  {
+    /* Set SMPS operating mode */
+    LL_PWR_SMPS_SetMode(LL_PWR_SMPS_BYPASS);
+  }
+  
+  /* Start ADC group regular conversion */
+  /* Note: Hardware constraint (refer to description of the functions         */
+  /*       below):                                                            */
+  /*       On this STM32 serie, setting of this feature is conditioned to     */
+  /*       ADC state:                                                         */
+  /*       ADC must be enabled without conversion on going on group regular,  */
+  /*       without ADC disable command on going.                              */
+  /* Note: In this example, all these checks are not necessary but are        */
+  /*       implemented anyway to show the best practice usages                */
+  /*       corresponding to reference manual procedure.                       */
+  /*       Software can be optimized by removing some of these checks, if     */
+  /*       they are not relevant considering previous settings and actions    */
+  /*       in user application.                                               */
+  if ((LL_ADC_IsEnabled(ADC1) == 1)               &&
+      (LL_ADC_IsDisableOngoing(ADC1) == 0)        &&
+      (LL_ADC_REG_IsConversionOngoing(ADC1) == 0)   )
+  {
+    LL_ADC_REG_StartConversion(ADC1);
+  }
+  else
+  {
+    /* Error: ADC conversion start could not be performed */
+    LED_Blinking(LED_BLINK_ERROR);
+  }
+ 
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    /* Note: LED state depending on ADC analog watchdog 1 status              */
+    /*       and status variable "ubAnalogWatchdog1Status"                    */
+    /*       are set into ADC analog watchdog 1 IRQ handler,                  */
+    /*       refer to function "AdcAnalogWatchdog1_Callback()".               */
+    /*       After analog watchdog interruption, press on push button         */
+    /*       to rearm ADC analog watchdog to be ready for another trig,       */
+    /*       refer to function "UserButton_Callback()".                       */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  /* HSI configuration and activation */
+  LL_RCC_HSI_Enable();
+  while(LL_RCC_HSI_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the HSI */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(16000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(16000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief ADC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC1_Init(void)
+{
+
+  /* USER CODE BEGIN ADC1_Init 0 */
+
+  /* USER CODE END ADC1_Init 0 */
+
+  LL_ADC_CommonInitTypeDef ADC_CommonInitStruct = {0};
+  LL_ADC_InitTypeDef ADC_InitStruct = {0};
+  LL_ADC_REG_InitTypeDef ADC_REG_InitStruct = {0};
+
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* Peripheral clock enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC);
+  
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  /**ADC1 GPIO Configuration  
+  PA1   ------> ADC1_IN6 
+  */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_1;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN ADC1_Init 1 */
+  
+  /* Enable GPIO Clock */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  
+  /* Configure GPIO in analog mode to be used as ADC input */
+  LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_1, LL_GPIO_MODE_ANALOG);
+  
+  /*## Configuration of NVIC #################################################*/
+  /* Configure NVIC to enable ADC1 interruptions */
+  NVIC_SetPriority(ADC1_IRQn, 0);
+  NVIC_EnableIRQ(ADC1_IRQn);
+  
+  /* USER CODE END ADC1_Init 1 */
+  /** Common config 
+  */
+  ADC_CommonInitStruct.CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
+  LL_ADC_CommonInit(__LL_ADC_COMMON_INSTANCE(ADC1), &ADC_CommonInitStruct);
+  ADC_InitStruct.Resolution = LL_ADC_RESOLUTION_12B;
+  ADC_InitStruct.DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
+  ADC_InitStruct.LowPowerMode = LL_ADC_LP_MODE_NONE;
+  LL_ADC_Init(ADC1, &ADC_InitStruct);
+  ADC_REG_InitStruct.TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
+  ADC_REG_InitStruct.SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
+  ADC_REG_InitStruct.SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+  ADC_REG_InitStruct.ContinuousMode = LL_ADC_REG_CONV_CONTINUOUS;
+  ADC_REG_InitStruct.DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
+  ADC_REG_InitStruct.Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
+  LL_ADC_REG_Init(ADC1, &ADC_REG_InitStruct);
+  LL_ADC_SetOverSamplingScope(ADC1, LL_ADC_OVS_DISABLE);
+  LL_ADC_DisableIT_EOC(ADC1);
+  LL_ADC_DisableIT_EOS(ADC1);
+  /** Configure Analog WatchDog 1 
+  */
+  LL_ADC_SetAnalogWDMonitChannels(ADC1, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
+  LL_ADC_ConfigAnalogWDThresholds(ADC1, LL_ADC_AWD1, ADC_AWD_THRESHOLD_HIGH, ADC_AWD_THRESHOLD_LOW);
+  LL_ADC_EnableIT_AWD1(ADC1);
+  /** Configure Regular Channel 
+  */
+  LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_1, LL_ADC_CHANNEL_6);
+  LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_6, LL_ADC_SAMPLINGTIME_247CYCLES_5);
+  LL_ADC_SetChannelSingleDiff(ADC1, LL_ADC_CHANNEL_6, LL_ADC_SINGLE_ENDED);
+  /** Configure Internal Channel 
+  */
+  LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_PATH_INTERNAL_VREFINT);
+  /* USER CODE BEGIN ADC1_Init 2 */
+
+  /* USER CODE END ADC1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_EXTI_InitTypeDef EXTI_InitStruct = {0};
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTA, LL_SYSCFG_EXTI_LINE0);
+
+  /**/
+  EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_0;
+  EXTI_InitStruct.Line_32_63 = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct.LineCommand = ENABLE;
+  EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;
+  EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_FALLING;
+  LL_EXTI_Init(&EXTI_InitStruct);
+
+  /**/
+  LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_0, LL_GPIO_PULL_UP);
+
+  /**/
+  LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_0, LL_GPIO_MODE_INPUT);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+  /* EXTI interrupt init*/
+  NVIC_SetPriority(EXTI0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(EXTI0_IRQn);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  Perform ADC activation procedure to make it ready to convert
+  *         (ADC instance: ADC1).
+  * @note   Operations:
+  *         - ADC instance
+  *           - Disable deep power down
+  *           - Enable internal voltage regulator
+  *           - Run ADC self calibration
+  *           - Enable ADC
+  *         - ADC group regular
+  *           none: ADC conversion start-stop to be performed
+  *                 after this function
+  *         - ADC group injected
+  *           none: ADC conversion start-stop to be performed
+  *                 after this function
+  * @param  None
+  * @retval None
+  */
+void Activate_ADC(void)
+{
+  __IO uint32_t wait_loop_index = 0U;
+  #if (USE_TIMEOUT == 1)
+  uint32_t Timeout = 0U; /* Variable used for timeout management */
+  #endif /* USE_TIMEOUT */
+  
+  /*## Operation on ADC hierarchical scope: ADC instance #####################*/
+  
+  /* Note: Hardware constraint (refer to description of the functions         */
+  /*       below):                                                            */
+  /*       On this STM32 serie, setting of these features is conditioned to   */
+  /*       ADC state:                                                         */
+  /*       ADC must be disabled.                                              */
+  /* Note: In this example, all these checks are not necessary but are        */
+  /*       implemented anyway to show the best practice usages                */
+  /*       corresponding to reference manual procedure.                       */
+  /*       Software can be optimized by removing some of these checks, if     */
+  /*       they are not relevant considering previous settings and actions    */
+  /*       in user application.                                               */
+  if (LL_ADC_IsEnabled(ADC1) == 0)
+  {
+    /* Disable ADC deep power down (enabled by default after reset state) */
+    LL_ADC_DisableDeepPowerDown(ADC1);
+    
+    /* Enable ADC internal voltage regulator */
+    LL_ADC_EnableInternalRegulator(ADC1);
+    
+    /* Delay for ADC internal voltage regulator stabilization.                */
+    /* Compute number of CPU cycles to wait for, from delay in us.            */
+    /* Note: Variable divided by 2 to compensate partially                    */
+    /*       CPU processing cycles (depends on compilation optimization).     */
+    /* Note: If system core clock frequency is below 200kHz, wait time        */
+    /*       is only a few CPU processing cycles.                             */
+    wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (100000 * 2))) / 10);
+    while(wait_loop_index != 0)
+    {
+      wait_loop_index--;
+    }
+    
+    /* Run ADC self calibration */
+    LL_ADC_StartCalibration(ADC1, LL_ADC_SINGLE_ENDED);
+    
+    /* Poll for ADC effectively calibrated */
+    #if (USE_TIMEOUT == 1)
+    Timeout = ADC_CALIBRATION_TIMEOUT_MS;
+    #endif /* USE_TIMEOUT */
+    
+    while (LL_ADC_IsCalibrationOnGoing(ADC1) != 0)
+    {
+    #if (USE_TIMEOUT == 1)
+      /* Check Systick counter flag to decrement the time-out value */
+      if (LL_SYSTICK_IsActiveCounterFlag())
+      {
+        if(Timeout-- == 0)
+        {
+        /* Time-out occurred. Set LED to blinking mode */
+        LED_Blinking(LED_BLINK_ERROR);
+        }
+      }
+    #endif /* USE_TIMEOUT */
+    }
+    
+    /* Delay between ADC end of calibration and ADC enable.                   */
+    /* Note: Variable divided by 2 to compensate partially                    */
+    /*       CPU processing cycles (depends on compilation optimization).     */
+    wait_loop_index = (ADC_DELAY_CALIB_ENABLE_CPU_CYCLES >> 1);
+    while(wait_loop_index != 0)
+    {
+      wait_loop_index--;
+    }
+    
+    /* Enable ADC */
+    LL_ADC_Enable(ADC1);
+    
+    /* Poll for ADC ready to convert */
+    #if (USE_TIMEOUT == 1)
+    Timeout = ADC_ENABLE_TIMEOUT_MS;
+    #endif /* USE_TIMEOUT */
+    
+    while (LL_ADC_IsActiveFlag_ADRDY(ADC1) == 0)
+    {
+    #if (USE_TIMEOUT == 1)
+      /* Check Systick counter flag to decrement the time-out value */
+      if (LL_SYSTICK_IsActiveCounterFlag())
+      {
+        if(Timeout-- == 0)
+        {
+        /* Time-out occurred. Set LED to blinking mode */
+        LED_Blinking(LED_BLINK_ERROR);
+        }
+      }
+    #endif /* USE_TIMEOUT */
+    }
+    
+    /* Note: ADC flag ADRDY is not cleared here to be able to check ADC       */
+    /*       status afterwards.                                               */
+    /*       This flag should be cleared at ADC Deactivation, before a new    */
+    /*       ADC activation, using function "LL_ADC_ClearFlag_ADRDY()".       */
+  }
+  
+  /*## Operation on ADC hierarchical scope: ADC group regular ################*/
+  /* Note: No operation on ADC group regular performed here.                  */
+  /*       ADC group regular conversions to be performed after this function  */
+  /*       using function:                                                    */
+  /*       "LL_ADC_REG_StartConversion();"                                    */
+  
+  /*## Operation on ADC hierarchical scope: ADC group injected ###############*/
+  /* Note: No operation on ADC group injected performed here.                 */
+  /*       ADC group injected conversions to be performed after this function */
+  /*       using function:                                                    */
+  /*       "LL_ADC_INJ_StartConversion();"                                    */
+  
+}
+
+/**
+  * @brief  Turn-on LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_On(void)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Turn-off LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_Off(void)
+{
+  /* Turn LED2 off */
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
+  * @param  Period : Period of time (in ms) between each toggling of LED
+  *   This parameter can be user defined values. Pre-defined values used in that example are :
+  *     @arg LED_BLINK_FAST : Fast Blinking
+  *     @arg LED_BLINK_SLOW : Slow Blinking
+  *     @arg LED_BLINK_ERROR : Error specific Blinking
+  * @retval None
+  */
+void LED_Blinking(uint32_t Period)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+  
+  /* Toggle IO in an infinite loop */
+  while (1)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+    LL_mDelay(Period);
+  }
+}
+
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT                                               */
+/******************************************************************************/
+
+/**
+  * @brief  Function to manage IRQ Handler
+  * @param  None
+  * @retval None
+  */
+void UserButton_Callback(void)
+{
+  /* Rearm ADC analog watchdog to be ready for another trig */
+
+  /* Turn LED2 off */
+  LED_Off();
+  
+  /* Reset status variable of ADC analog watchdog 1 */
+  ubAnalogWatchdog1Status = 0;
+  
+  /* Clear flag ADC analog watchdog 1 */
+  LL_ADC_ClearFlag_AWD1(ADC1);
+  
+  /* Enable ADC analog watchdog 1 interruption */
+  LL_ADC_EnableIT_AWD1(ADC1);
+}
+
+/**
+  * @brief  ADC analog watchdog 1 interruption callback
+  * @note   This function is executed when the ADC conversion data is 
+  *         out of analog watchdog 1 window thresholds.
+  * @retval None
+  */
+void AdcAnalogWatchdog1_Callback()
+{
+  /* Disable ADC analog watchdog 1 interruption */
+  LL_ADC_DisableIT_AWD1(ADC1);
+  
+  /* Update status variable of ADC analog watchdog 1 */
+  ubAnalogWatchdog1Status = 1;
+  
+  /* Set LED depending on ADC analog watchdog status */
+  /* - Turn-on if voltage is out of AWD window */
+  LED_On();
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..0a60da6a7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,248 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/ADC/ADC_AnalogWatchdog_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles EXTI line0 interrupt.
+  */
+void EXTI0_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI0_IRQn 0 */
+
+  /* USER CODE END EXTI0_IRQn 0 */
+  if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
+  {
+    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
+    /* USER CODE BEGIN LL_EXTI_LINE_0 */
+    
+    /* Handle user button press in dedicated function */
+    UserButton_Callback(); 
+    /* USER CODE END LL_EXTI_LINE_0 */
+  }
+  /* USER CODE BEGIN EXTI0_IRQn 1 */
+
+
+  /* USER CODE END EXTI0_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/**
+  * @brief  This function handles ADC1 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void ADC1_IRQHandler(void)
+{
+  /* Check whether ADC analog watchdog 1 caused the ADC interruption */
+  if(LL_ADC_IsActiveFlag_AWD1(ADC1) != 0)
+  {
+    /* Clear flag ADC analog watchdog 1 */
+    LL_ADC_ClearFlag_AWD1(ADC1);
+    
+    /* Call interruption treatment function */
+    AdcAnalogWatchdog1_Callback();
+  }
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/readme.txt
new file mode 100644
index 000000000..6ac9433d0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_AnalogWatchdog_Init/readme.txt
@@ -0,0 +1,94 @@
+/**
+  @page ADC_AnalogWatchdog_Init ADC example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/ADC/ADC_AnalogWatchdog_Init/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the ADC_AnalogWatchdog_Init example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to use an ADC peripheral with an ADC analog watchdog to monitor a channel 
+and detect when the corresponding conversion data is outside the window 
+thresholds.
+This example is based on the STM32WBxx ADC LL API.
+The peripheral initialization is done using LL unitary service functions
+for optimization purposes (performance and size).
+
+Example configuration:
+ADC is configured to convert a single channel, in continuous conversion mode,
+from SW trigger.
+Analog watchdog is configured to monitor all channels on group regular
+(therefore, including the selected channel), 
+low threshold is set to 0V and high threshold is set to Vdda/2.
+ADC interruption enabled: Analog watchdog 1.
+
+Example execution:
+From the main program execution, the ADC converts the selected channel continuously.
+When conversion data is out of analog watchdog window, ADC interruption occurs.
+Into analog watchdog callback function, a status variable is set
+and LED2 is updated.
+LED2 state:
+ - LED remains turned-off if voltage is within AWD window (analog watchdog not triggered)
+ - LED turned-on if voltage is out of AWD window
+At each press on User push-button (SW1), the ADC analog watchdog is rearmed to be ready
+for another trig.
+
+LED2 is blinking every 1 sec in case of error.
+
+Note: In case of noise on voltage applied on ADC channel input (due to connectors and wires parasitics),
+      ADC analog watchdog may trig at a voltage level with an uncertainty of tens of mV.
+
+For debug: variables to monitor with debugger watch window:
+ - "ubAnalogWatchdog1Status": analog watchdog state
+
+Connection needed: use an external power supply, adjust supply voltage and connect 
+it to analog input pin (cf pin below).
+
+Other peripherals used:
+  1 GPIO for User push-button (SW1)
+  1 GPIO for LED2
+  1 GPIO for analog input: PA.01 (Arduino connector CN8 pin A2, Morpho connector CN7 pin 32)
+@par Keywords
+
+ADC,ADC channel,ADC analog watchdog, conversion, single channel, single conversion mode, interrupt,
+
+@par Directory contents 
+
+  - ADC/ADC_AnalogWatchdog_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - ADC/ADC_AnalogWatchdog_Init/Inc/main.h                  Header for main.c module
+  - ADC/ADC_AnalogWatchdog_Init/Inc/stm32_assert.h          Template file to include assert_failed function
+  - ADC/ADC_AnalogWatchdog_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - ADC/ADC_AnalogWatchdog_Init/Src/main.c                  Main program
+  - ADC/ADC_AnalogWatchdog_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/ADC_Oversampling_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/ADC_Oversampling_Init.ioc
new file mode 100644
index 000000000..50249a53e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/ADC_Oversampling_Init.ioc
@@ -0,0 +1,148 @@
+#MicroXplorer Configuration settings - do not modify
+ADC1.Channel-10\#ChannelRegularConversion=ADC_CHANNEL_6
+ADC1.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV2
+ADC1.ContinuousConvMode=DISABLE
+ADC1.DMAContinuousRequests=DISABLE
+ADC1.DataAlign=ADC_DATAALIGN_RIGHT
+ADC1.DiscontinuousConvMode=DISABLE
+ADC1.EOCSelection=ADC_EOC_SEQ_CONV
+ADC1.EnableAnalogWatchDog1=false
+ADC1.EnableAnalogWatchDog2=false
+ADC1.EnableAnalogWatchDog3=false
+ADC1.ExternalTrigConv=ADC_SOFTWARE_START
+ADC1.ExternalTrigConvEdge=ADC_EXTERNALTRIGCONVEDGE_NONE
+ADC1.IPParameters=ClockPrescaler,Resolution,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,DMAContinuousRequests,EOCSelection,Overrun,LowPowerAutoWait,OversamplingMode,RightBitShift,Ratio,TriggeredMode,NbrOfConversion,ExternalTrigConv,ExternalTrigConvEdge,EnableAnalogWatchDog1,EnableAnalogWatchDog2,EnableAnalogWatchDog3,Rank-10\#ChannelRegularConversion,Channel-10\#ChannelRegularConversion,SamplingTime-10\#ChannelRegularConversion,master
+ADC1.LowPowerAutoWait=DISABLE
+ADC1.NbrOfConversion=1
+ADC1.Overrun=ADC_OVR_DATA_OVERWRITTEN
+ADC1.OversamplingMode=ENABLE
+ADC1.Rank-10\#ChannelRegularConversion=1
+ADC1.Ratio=ADC_OVERSAMPLING_RATIO_16
+ADC1.Resolution=ADC_RESOLUTION_12B
+ADC1.RightBitShift=ADC_RIGHTBITSHIFT_4
+ADC1.SamplingTime-10\#ChannelRegularConversion=ADC_SAMPLETIME_247CYCLES_5
+ADC1.ScanConvMode=ADC_SCAN_DISABLE
+ADC1.TriggeredMode=ADC_TRIGGEREDMODE_SINGLE_TRIGGER
+ADC1.master=1
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=ADC1
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA0
+Mcu.Pin1=PA1
+Mcu.Pin2=PB0
+Mcu.Pin3=VP_SYS_VS_Systick
+Mcu.PinsNb=4
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.EXTI0_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA0.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultEXTI
+PA0.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
+PA0.GPIO_PuPd=GPIO_PULLUP
+PA0.Locked=true
+PA0.Signal=GPXTI0
+PA1.Signal=ADCx_IN6
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=false
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=ADC_Oversampling_Init.ioc
+ProjectManager.ProjectName=ADC_Oversampling_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-true,3-MX_ADC1_Init-ADC1-false-LL-true
+RCC.AHBFreq_Value=16000000
+RCC.APB1Freq_Value=16000000
+RCC.APB1TimFreq_Value=16000000
+RCC.APB2Freq_Value=16000000
+RCC.APB2TimFreq_Value=16000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=16000000
+RCC.CortexFreq_Value=16000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=16000000
+RCC.FCLKCortexFreq_Value=16000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=16000000
+RCC.HCLK3Freq_Value=16000000
+RCC.HCLKFreq_Value=16000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=16000000
+RCC.I2C3Freq_Value=16000000
+RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=16000000
+RCC.LPTIM2Freq_Value=16000000
+RCC.LPUART1Freq_Value=16000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=16000000
+RCC.PLLPoutputFreq_Value=16000000
+RCC.PLLQoutputFreq_Value=16000000
+RCC.PLLRCLKFreq_Value=16000000
+RCC.PWRFreq_Value=16000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=16000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_HSI
+RCC.USART1Freq_Value=16000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=32000000
+SH.ADCx_IN6.0=ADC1_IN6,IN6-Single-Ended
+SH.ADCx_IN6.ConfNb=1
+SH.GPXTI0.0=GPIO_EXTI0
+SH.GPXTI0.ConfNb=1
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/ADC_Oversampling_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/ADC_Oversampling_Init.ewd
new file mode 100644
index 000000000..df843f224
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/ADC_Oversampling_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		ADC_Oversampling_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/ADC_Oversampling_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/ADC_Oversampling_Init.ewp
new file mode 100644
index 000000000..6d5e6afd8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/ADC_Oversampling_Init.ewp
@@ -0,0 +1,1089 @@
+
+
+  3
+  
+    ADC_Oversampling_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/Project.eww
new file mode 100644
index 000000000..96c810b0c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\ADC_Oversampling_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Inc/main.h
new file mode 100644
index 000000000..2c658e105
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Inc/main.h
@@ -0,0 +1,112 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/ADC/ADC_Oversampling_Init/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_adc.h"
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+
+/* Define used to enable time-out management*/
+#define USE_TIMEOUT       0
+
+/**
+  * @brief Toggle periods for various blinking modes
+  */
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW  500
+#define LED_BLINK_ERROR 1000
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+/* IRQ Handler treatment */
+void UserButton_Callback(void);
+void AdcGrpRegularOverrunError_Callback(void);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..6add51f0f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,74 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/ADC/ADC_Oversampling_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void EXTI0_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+void USER_BUTTON_IRQHANDLER(void);
+
+void ADC1_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/MDK-ARM/ADC_Oversampling_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/MDK-ARM/ADC_Oversampling_Init.uvoptx
new file mode 100644
index 000000000..e7efd8ea0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/MDK-ARM/ADC_Oversampling_Init.uvoptx
@@ -0,0 +1,357 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    ADC_Oversampling_Init
+    0x4
+    ARM-ADS
+    
+      16000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      4
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      4
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+      stm32wbxx_ll_adc.c
+      0
+      0
+    
+    
+      4
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      stm32wbxx_ll_dma.c
+      0
+      0
+    
+    
+      4
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/MDK-ARM/ADC_Oversampling_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/MDK-ARM/ADC_Oversampling_Init.uvprojx
new file mode 100644
index 000000000..2da1d9b82
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/MDK-ARM/ADC_Oversampling_Init.uvprojx
@@ -0,0 +1,482 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      ADC_Oversampling_Init
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          ADC_Oversampling_Init\
+          ADC_Oversampling_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_adc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+            
+            
+              stm32wbxx_ll_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..61a560c26
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..72fa3e7f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/.project
@@ -0,0 +1,90 @@
+
+
+	ADC_Oversampling_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			ADC_Oversampling_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/ADC_Oversampling_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_adc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..eea98ff9c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb35xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB35xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..4ec95844d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,159 @@
+/**
+ ******************************************************************************
+ * @file      syscalls.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..4665417ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,58 @@
+/**
+ ******************************************************************************
+ * @file      sysmem.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System Memory calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Src/main.c
new file mode 100644
index 000000000..bfeb06afa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Src/main.c
@@ -0,0 +1,813 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/ADC/ADC_Oversampling_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to use a ADC peripheral with
+  *          ADC oversampling to perform automatically: 
+  *          several ADC conversions and average computation.
+  *          These actions are performed by ADC hardware and therefore
+  *          off-load the CPU to do the equivalent task.
+  *          This feature can be used for the functions: averaging,
+  *          data rate reduction, SNR improvement, basic filtering.
+  *          This example uses 3 configurations of oversampling,
+  *          for comparison of final data to evaluate oversampling benefits.
+  *          This example is based on the STM32WBxx ADC LL API;
+  *          Peripheral initialization done using LL unitary services functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+
+/* Definitions of ADC hardware constraints delays */
+/* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */
+/*       not timeout values:                                                  */
+/*       Timeout values for ADC operations are dependent to device clock      */
+/*       configuration (system clock versus ADC clock),                       */
+/*       and therefore must be defined in user application.                   */
+/*       Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout     */
+/*       values definition.                                                   */
+
+  /* Timeout values for ADC operations. */
+  /* (calibration, enable settling time, disable settling time, ...)          */
+  /* Values defined to be higher than worst cases: low clock frequency,       */
+  /* maximum prescalers.                                                      */
+  #define ADC_CALIBRATION_TIMEOUT_MS       (   1U)
+  #define ADC_ENABLE_TIMEOUT_MS            (   1U)
+  #define ADC_DISABLE_TIMEOUT_MS           (   1U)
+  #define ADC_STOP_CONVERSION_TIMEOUT_MS   (   1U)
+  #define ADC_CONVERSION_TIMEOUT_MS        ( 500U)
+  
+  /* Delay between ADC end of calibration and ADC enable.                     */
+  /* Delay estimation in CPU cycles: Case of ADC enable done                  */
+  /* immediately after ADC calibration, ADC clock setting slow                */
+  /* (LL_ADC_CLOCK_ASYNC_DIV32). Use a higher delay if ratio                  */
+  /* (CPU clock / ADC clock) is above 32.                                     */
+  #define ADC_DELAY_CALIB_ENABLE_CPU_CYCLES  (LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES * 32)
+  
+
+/* Definitions of environment analog values */
+  /* Value of analog reference voltage (Vref+), connected to analog voltage   */
+  /* supply Vdda (unit: mV).                                                  */
+  #define VDDA_APPLI                       (3300UL)
+
+/* Definitions of data related to this example */
+  /* ADC unitary conversion timeout */
+  /* Considering ADC settings, duration of 1 ADC conversion should always    */
+  /* be lower than 1ms.                                                      */
+  #define ADC_UNITARY_CONVERSION_TIMEOUT_MS (   1UL)
+
+  /* Init variable out of expected ADC conversion data range */
+  #define VAR_CONVERTED_DATA_INIT_VALUE    (__LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B) + 1)
+
+  /* Init variable out of ADC expected conversion data range for data         */
+  /* on 16 bits (oversampling enabled).                                       */
+  #define VAR_CONVERTED_DATA_INIT_VALUE_16BITS    (0xFFFF + 1UL)
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+
+__IO uint32_t ubUserButtonPressed = 0UL;
+
+/* Variables for ADC conversion data */
+__IO uint16_t uhADCxConvertedData_OVS_ratio16_shift4   = VAR_CONVERTED_DATA_INIT_VALUE;        /* ADC group regular conversion data, oversampling ratio 16 and shift 4 (data scale: 12 bits) */
+__IO uint32_t uhADCxConvertedData_OVS_ratio16_shift0   = VAR_CONVERTED_DATA_INIT_VALUE_16BITS; /* ADC group regular conversion data, oversampling ratio 16 and shift 0 (data scale: 16 bits) */
+__IO uint16_t uhADCxConvertedData_OVS_disabled         = VAR_CONVERTED_DATA_INIT_VALUE;        /* ADC group regular conversion data, oversampling disabled (data scale corresponds to ADC resolution: 12 bits) */
+
+__IO float    fConvertedData_OVS_EquivalentValue12bits = 4.4f; /* Calculation of oversampling raw data to the equivalent data (from variable "uhADCxConvertedData_OVS_ratio16_shift0") to the equivalent data on 12 bits with floating point */
+
+
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_ADC1_Init(void);
+/* USER CODE BEGIN PFP */
+
+void     Activate_ADC(void);
+void     ConversionStartPoll_ADC_GrpRegular(void);
+void     LED_On(void);
+void     LED_Off(void);
+void     LED_Blinking(uint32_t Period);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_ADC1_Init();
+  /* USER CODE BEGIN 2 */
+  
+  /* Activate ADC */
+  /* Perform ADC activation procedure to make it ready to convert. */
+  Activate_ADC();
+  
+  /* Disable SMPS: SMPS in mode step-down can impact ADC conversion accuracy. */
+  /* It is recommnended to disable SMPS (stop SMPS switching by setting it    */
+  /* in mode bypass) during ADC conversion.                                   */
+  /* Get SMPS effective operating mode */
+  if(LL_PWR_SMPS_GetEffectiveMode() == LL_PWR_SMPS_STEP_DOWN)
+  {
+    /* Set SMPS operating mode */
+    LL_PWR_SMPS_SetMode(LL_PWR_SMPS_BYPASS);
+  }
+  
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* Wait for user press on push button */
+    while (ubUserButtonPressed != 1)
+    {
+    }
+    ubUserButtonPressed = 0;
+    
+    /* Turn LED off before performing a new ADC conversion start */
+    LED_Off();
+    
+    /*## Step 1: ADC oversampling initial settings  ##########################*/
+    
+    /* Perform ADC group regular conversion start, poll for conversion        */
+    /* completion.                                                            */
+    ConversionStartPoll_ADC_GrpRegular();
+        
+    /* Retrieve ADC conversion data */
+    /* (data scale with oversampling ratio 16 and shift 4 corresponds         */
+    /* to ADC resolution: 12 bits)                                            */
+    uhADCxConvertedData_OVS_ratio16_shift4 = LL_ADC_REG_ReadConversionData12(ADC1);
+    
+    
+    /*## Step 2: ADC oversampling modified settings  #########################*/
+    /* Modify ADC oversampling settings:                                      */
+    /* - ratio: 16                                                            */
+    /* - shift: 0 (no shift)                                                  */
+    /* Set ADC oversampling parameters */
+    LL_ADC_ConfigOverSamplingRatioShift(ADC1, LL_ADC_OVS_RATIO_16, LL_ADC_OVS_SHIFT_NONE);
+    
+    /* Perform ADC group regular conversion start, poll for conversion        */
+    /* completion.                                                            */
+    ConversionStartPoll_ADC_GrpRegular();
+    
+    /* Retrieve ADC conversion data */
+    /* (data scale with oversampling ratio 16 and shift 0 exceeds             */
+    /* ADC resolution 12 bits, data scale expected: 16 bits)                  */
+    uhADCxConvertedData_OVS_ratio16_shift0 = LL_ADC_REG_ReadConversionData32(ADC1);
+    
+    
+    /*## Step 3: ADC oversampling disabled  ##################################*/
+    /* Modify ADC oversampling settings:                                      */
+    /* - scope: none (oversampling disabled)                                  */
+    /* Set ADC oversampling scope */
+    LL_ADC_SetOverSamplingScope(ADC1, LL_ADC_OVS_DISABLE);
+    
+    /* Perform ADC group regular conversion start, poll for conversion        */
+    /* completion.                                                            */
+    ConversionStartPoll_ADC_GrpRegular();
+    
+    /* Retrieve ADC conversion data */
+    /* (data scale with oversampling disabled corresponds                     */
+    /* to ADC resolution: 12 bits)                                            */
+    uhADCxConvertedData_OVS_disabled = LL_ADC_REG_ReadConversionData12(ADC1);
+    
+    
+    /* Turn LED on at the end of all ADC conversions */
+    LED_On();
+    
+    /* Restore ADC oversampling initial settings for next loop:               */
+    /* - scope: ADC group regular                                             */
+    /* - ratio: 16                                                            */
+    /* - shift: 4                                                             */
+    /* Set ADC oversampling scope */
+    LL_ADC_SetOverSamplingScope(ADC1, LL_ADC_OVS_GRP_REGULAR_CONTINUED);
+    
+    /* Set ADC oversampling parameters */
+    LL_ADC_ConfigOverSamplingRatioShift(ADC1, LL_ADC_OVS_RATIO_16, LL_ADC_OVS_SHIFT_RIGHT_4);
+  
+  
+    /*## Step 4: ADC conversion data evaluation  #############################*/
+    /* Expected raw data: */
+    /*  - Data of initial oversampling configuration (ratio 16, shift 4)      */
+    /*    should be on the same scale as ADC resolution: 12 bits.             */
+    /*  - Data of modified oversampling configuration (ratio 16, shift 0)     */
+    /*    should exceed ADC resolution 12 bits and be on scale: 16 bits       */
+    /*  - Data of oversampling disabled should be on the same scale as        */
+    /*    ADC resolution: 12 bits.                                            */
+    /* Expected data comparison: */
+    /*  - Data of initial oversampling configuration (ratio 16, shift 4)      */
+    /*    and modified oversampling configuration (ratio 16, shift 0) with    */
+    /*    SW calculation of equivalent data on 12 bits with floating point    */
+    /*    should be similar.                                                  */
+    /*    This SW calculation is equivalent to the ADC oversampling           */
+    /*    operation "shift 4".                                                */
+    /*  - ADC conversion data with oversampling enabled should have less      */
+    /*    variation than with oversampling disabled: oversampling is          */
+    /*    equivalent to an averaging (average on 16 ADC conversions with      */
+    /*    settings of this example).                                          */
+    
+    /* Note: Optionally, for this example purpose, check ADC conversion       */
+    /*       data validity.                                                   */
+    if ((uhADCxConvertedData_OVS_ratio16_shift4 > __LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B)) ||
+        (uhADCxConvertedData_OVS_disabled > __LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B)))
+    {
+      /* Error: ADC conversion data has not been updated or is not valid.     */
+      LED_Blinking(LED_BLINK_ERROR);
+    }
+    
+    if (uhADCxConvertedData_OVS_ratio16_shift0 > 0xFFFF)
+    {
+      /* Error: ADC conversion data has not been updated or is not valid.     */
+      LED_Blinking(LED_BLINK_ERROR);
+    }
+    
+    /* For this example purpose, calculation of oversampling raw data         */
+    /* (from variable "uhADCxConvertedData_OVS_ratio16_shift0")               */
+    /* to the equivalent data on 12 bits with floating point                  */
+    fConvertedData_OVS_EquivalentValue12bits = (((float)uhADCxConvertedData_OVS_ratio16_shift0) / 16);
+    
+    if (fConvertedData_OVS_EquivalentValue12bits > __LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B))
+    {
+      /* Error: ADC conversion data has not been updated or is not valid.     */
+      LED_Blinking(LED_BLINK_ERROR);
+    }
+    
+    /* Note: ADC conversion data is stored into variables:                    */
+    /*       - "uhADCxConvertedData_OVS_ratio16_shift4"                       */
+    /*       - "uhADCxConvertedData_OVS_ratio16_shift0"                       */
+    /*       - "uhADCxConvertedData_OVS_disabled"                             */
+    /*       (for debug: see variable content into watch window).             */
+    
+    /* Note: ADC conversion data can be computed to physical values           */
+    /*       using ADC LL driver helper macro:                                */
+    /*         uhADCxConvertedData_Voltage_mVolt                              */
+    /*         = __LL_ADC_CALC_DATA_TO_VOLTAGE(VDDA_APPLI,                    */
+    /*                                      uhADCxConvertedData),             */
+    /*                                      LL_ADC_RESOLUTION_12B)            */
+
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  /* HSI configuration and activation */
+  LL_RCC_HSI_Enable();
+  while(LL_RCC_HSI_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the HSI */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(16000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(16000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief ADC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC1_Init(void)
+{
+
+  /* USER CODE BEGIN ADC1_Init 0 */
+
+  /* USER CODE END ADC1_Init 0 */
+
+  LL_ADC_CommonInitTypeDef ADC_CommonInitStruct = {0};
+  LL_ADC_InitTypeDef ADC_InitStruct = {0};
+  LL_ADC_REG_InitTypeDef ADC_REG_InitStruct = {0};
+
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* Peripheral clock enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC);
+  
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  /**ADC1 GPIO Configuration  
+  PA1   ------> ADC1_IN6 
+  */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_1;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN ADC1_Init 1 */
+  
+  /* Configure NVIC to enable ADC1 interruptions */
+  NVIC_SetPriority(ADC1_IRQn, 0);
+  NVIC_EnableIRQ(ADC1_IRQn);
+
+  /* USER CODE END ADC1_Init 1 */
+  /** Common config 
+  */
+  ADC_CommonInitStruct.CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
+  LL_ADC_CommonInit(__LL_ADC_COMMON_INSTANCE(ADC1), &ADC_CommonInitStruct);
+  ADC_InitStruct.Resolution = LL_ADC_RESOLUTION_12B;
+  ADC_InitStruct.DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
+  ADC_InitStruct.LowPowerMode = LL_ADC_LP_MODE_NONE;
+  LL_ADC_Init(ADC1, &ADC_InitStruct);
+  ADC_REG_InitStruct.TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
+  ADC_REG_InitStruct.SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
+  ADC_REG_InitStruct.SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+  ADC_REG_InitStruct.ContinuousMode = LL_ADC_REG_CONV_SINGLE;
+  ADC_REG_InitStruct.DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
+  ADC_REG_InitStruct.Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
+  LL_ADC_REG_Init(ADC1, &ADC_REG_InitStruct);
+  LL_ADC_SetOverSamplingScope(ADC1, LL_ADC_OVS_GRP_REGULAR_CONTINUED);
+  LL_ADC_ConfigOverSamplingRatioShift(ADC1, LL_ADC_OVS_RATIO_16, LL_ADC_OVS_SHIFT_RIGHT_4);
+  LL_ADC_SetOverSamplingDiscont(ADC1, LL_ADC_OVS_REG_CONT);
+  LL_ADC_DisableIT_EOC(ADC1);
+  LL_ADC_DisableIT_EOS(ADC1);
+  /** Configure Regular Channel 
+  */
+  LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_1, LL_ADC_CHANNEL_6);
+  LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_6, LL_ADC_SAMPLINGTIME_247CYCLES_5);
+  LL_ADC_SetChannelSingleDiff(ADC1, LL_ADC_CHANNEL_6, LL_ADC_SINGLE_ENDED);
+  /* USER CODE BEGIN ADC1_Init 2 */
+    
+  /* Configuration of ADC interruptions */
+  /* Enable interruption ADC group regular overrun */
+  LL_ADC_EnableIT_OVR(ADC1);
+  
+  /* USER CODE END ADC1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_EXTI_InitTypeDef EXTI_InitStruct = {0};
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTA, LL_SYSCFG_EXTI_LINE0);
+
+  /**/
+  EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_0;
+  EXTI_InitStruct.Line_32_63 = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct.LineCommand = ENABLE;
+  EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;
+  EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_FALLING;
+  LL_EXTI_Init(&EXTI_InitStruct);
+
+  /**/
+  LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_0, LL_GPIO_PULL_UP);
+
+  /**/
+  LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_0, LL_GPIO_MODE_INPUT);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+  /* EXTI interrupt init*/
+  NVIC_SetPriority(EXTI0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(EXTI0_IRQn);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+  /**
+  * @brief  Perform ADC activation procedure to make it ready to convert
+  *         (ADC instance: ADC1).
+  * @note   Operations:
+  *         - ADC instance
+  *           - Disable deep power down
+  *           - Enable internal voltage regulator
+  *           - Run ADC self calibration
+  *           - Enable ADC
+  *         - ADC group regular
+  *           none: ADC conversion start-stop to be performed
+  *                 after this function
+  *         - ADC group injected
+  *           none: ADC conversion start-stop to be performed
+  *                 after this function
+  * @param  None
+  * @retval None
+  */
+void Activate_ADC(void)
+{
+  __IO uint32_t wait_loop_index = 0U;
+  #if (USE_TIMEOUT == 1)
+  uint32_t Timeout = 0U; /* Variable used for timeout management */
+  #endif /* USE_TIMEOUT */
+  
+  /*## Operation on ADC hierarchical scope: ADC instance #####################*/
+  
+  /* Note: Hardware constraint (refer to description of the functions         */
+  /*       below):                                                            */
+  /*       On this STM32 serie, setting of these features is conditioned to   */
+  /*       ADC state:                                                         */
+  /*       ADC must be disabled.                                              */
+  /* Note: In this example, all these checks are not necessary but are        */
+  /*       implemented anyway to show the best practice usages                */
+  /*       corresponding to reference manual procedure.                       */
+  /*       Software can be optimized by removing some of these checks, if     */
+  /*       they are not relevant considering previous settings and actions    */
+  /*       in user application.                                               */
+  if (LL_ADC_IsEnabled(ADC1) == 0)
+  {
+    /* Disable ADC deep power down (enabled by default after reset state) */
+    LL_ADC_DisableDeepPowerDown(ADC1);
+    
+    /* Enable ADC internal voltage regulator */
+    LL_ADC_EnableInternalRegulator(ADC1);
+    
+    /* Delay for ADC internal voltage regulator stabilization.                */
+    /* Compute number of CPU cycles to wait for, from delay in us.            */
+    /* Note: Variable divided by 2 to compensate partially                    */
+    /*       CPU processing cycles (depends on compilation optimization).     */
+    /* Note: If system core clock frequency is below 200kHz, wait time        */
+    /*       is only a few CPU processing cycles.                             */
+    wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (100000 * 2))) / 10);
+    while(wait_loop_index != 0)
+    {
+      wait_loop_index--;
+    }
+    
+    /* Run ADC self calibration */
+    LL_ADC_StartCalibration(ADC1, LL_ADC_SINGLE_ENDED);
+    
+    /* Poll for ADC effectively calibrated */
+    #if (USE_TIMEOUT == 1)
+    Timeout = ADC_CALIBRATION_TIMEOUT_MS;
+    #endif /* USE_TIMEOUT */
+    
+    while (LL_ADC_IsCalibrationOnGoing(ADC1) != 0)
+    {
+    #if (USE_TIMEOUT == 1)
+      /* Check Systick counter flag to decrement the time-out value */
+      if (LL_SYSTICK_IsActiveCounterFlag())
+      {
+        if(Timeout-- == 0)
+        {
+        /* Time-out occurred. Set LED to blinking mode */
+        LED_Blinking(LED_BLINK_ERROR);
+        }
+      }
+    #endif /* USE_TIMEOUT */
+    }
+    
+    /* Delay between ADC end of calibration and ADC enable.                   */
+    /* Note: Variable divided by 2 to compensate partially                    */
+    /*       CPU processing cycles (depends on compilation optimization).     */
+    wait_loop_index = (ADC_DELAY_CALIB_ENABLE_CPU_CYCLES >> 1);
+    while(wait_loop_index != 0)
+    {
+      wait_loop_index--;
+    }
+    
+    /* Enable ADC */
+    LL_ADC_Enable(ADC1);
+    
+    /* Poll for ADC ready to convert */
+    #if (USE_TIMEOUT == 1)
+    Timeout = ADC_ENABLE_TIMEOUT_MS;
+    #endif /* USE_TIMEOUT */
+    
+    while (LL_ADC_IsActiveFlag_ADRDY(ADC1) == 0)
+    {
+    #if (USE_TIMEOUT == 1)
+      /* Check Systick counter flag to decrement the time-out value */
+      if (LL_SYSTICK_IsActiveCounterFlag())
+      {
+        if(Timeout-- == 0)
+        {
+        /* Time-out occurred. Set LED to blinking mode */
+        LED_Blinking(LED_BLINK_ERROR);
+        }
+      }
+    #endif /* USE_TIMEOUT */
+    }
+    
+    /* Note: ADC flag ADRDY is not cleared here to be able to check ADC       */
+    /*       status afterwards.                                               */
+    /*       This flag should be cleared at ADC Deactivation, before a new    */
+    /*       ADC activation, using function "LL_ADC_ClearFlag_ADRDY()".       */
+  }
+  
+  /*## Operation on ADC hierarchical scope: ADC group regular ################*/
+  /* Note: No operation on ADC group regular performed here.                  */
+  /*       ADC group regular conversions to be performed after this function  */
+  /*       using function:                                                    */
+  /*       "LL_ADC_REG_StartConversion();"                                    */
+  
+  /*## Operation on ADC hierarchical scope: ADC group injected ###############*/
+  /* Note: No operation on ADC group injected performed here.                 */
+  /*       ADC group injected conversions to be performed after this function */
+  /*       using function:                                                    */
+  /*       "LL_ADC_INJ_StartConversion();"                                    */
+  
+}
+
+/**
+  * @brief  Perform ADC group regular conversion start, poll for conversion
+  *         completion.
+  *         (ADC instance: ADC1).
+  * @note   This function does not perform ADC group regular conversion stop:
+  *         intended to be used with ADC in single mode, trigger SW start
+  *         (only 1 ADC conversion done at each trigger, no conversion stop
+  *         needed).
+  *         In case of continuous mode or conversion trigger set to 
+  *         external trigger, ADC group regular conversion stop must be added.
+  * @param  None
+  * @retval None
+  */
+void ConversionStartPoll_ADC_GrpRegular(void)
+{
+  #if (USE_TIMEOUT == 1)
+  uint32_t Timeout = 0U; /* Variable used for timeout management */
+  #endif /* USE_TIMEOUT */
+  
+  /* Start ADC group regular conversion */
+  /* Note: Hardware constraint (refer to description of the function          */
+  /*       below):                                                            */
+  /*       On this STM32 serie, setting of this feature is conditioned to     */
+  /*       ADC state:                                                         */
+  /*       ADC must be enabled without conversion on going on group regular,  */
+  /*       without ADC disable command on going.                              */
+  /* Note: In this example, all these checks are not necessary but are        */
+  /*       implemented anyway to show the best practice usages                */
+  /*       corresponding to reference manual procedure.                       */
+  /*       Software can be optimized by removing some of these checks, if     */
+  /*       they are not relevant considering previous settings and actions    */
+  /*       in user application.                                               */
+  if ((LL_ADC_IsEnabled(ADC1) == 1)               &&
+      (LL_ADC_IsDisableOngoing(ADC1) == 0)        &&
+      (LL_ADC_REG_IsConversionOngoing(ADC1) == 0)   )
+  {
+    LL_ADC_REG_StartConversion(ADC1);
+  }
+  else
+  {
+    /* Error: ADC conversion start could not be performed */
+    LED_Blinking(LED_BLINK_ERROR);
+  }
+  
+  #if (USE_TIMEOUT == 1)
+  Timeout = ADC_UNITARY_CONVERSION_TIMEOUT_MS;
+  #endif /* USE_TIMEOUT */
+  
+  while (LL_ADC_IsActiveFlag_EOC(ADC1) == 0)
+  {
+  #if (USE_TIMEOUT == 1)
+    /* Check Systick counter flag to decrement the time-out value */
+    if (LL_SYSTICK_IsActiveCounterFlag())
+    {
+      if(Timeout-- == 0)
+      {
+      /* Time-out occurred. Set LED to blinking mode */
+      LED_Blinking(LED_BLINK_SLOW);
+      }
+    }
+  #endif /* USE_TIMEOUT */
+  }
+  
+  /* Clear flag ADC group regular end of unitary conversion */
+  /* Note: This action is not needed here, because flag ADC group regular   */
+  /*       end of unitary conversion is cleared automatically when          */
+  /*       software reads conversion data from ADC data register.           */
+  /*       Nevertheless, this action is done anyway to show how to clear    */
+  /*       this flag, needed if conversion data is not always read          */
+  /*       or if group injected end of unitary conversion is used (for      */
+  /*       devices with group injected available).                          */
+  LL_ADC_ClearFlag_EOC(ADC1);
+  
+}
+
+/**
+  * @brief  Turn-on LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_On(void)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Turn-off LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_Off(void)
+{
+  /* Turn LED2 off */
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
+  * @param  Period : Period of time (in ms) between each toggling of LED
+  *   This parameter can be user defined values. Pre-defined values used in that example are :
+  *     @arg LED_BLINK_FAST : Fast Blinking
+  *     @arg LED_BLINK_SLOW : Slow Blinking
+  *     @arg LED_BLINK_ERROR : Error specific Blinking
+  * @retval None
+  */
+void LED_Blinking(uint32_t Period)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+  
+  /* Toggle IO in an infinite loop */
+  while (1)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+    LL_mDelay(Period);
+  }
+}
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT                                               */
+/******************************************************************************/
+
+/**
+  * @brief  Function to manage IRQ Handler
+  * @param  None
+  * @retval None
+  */
+void UserButton_Callback(void)
+{
+  ubUserButtonPressed = 1;
+}
+
+/**
+  * @brief  ADC group regular overrun interruption callback
+  * @note   This function is executed when ADC group regular
+  *         overrun error occurs.
+  * @retval None
+  */
+void AdcGrpRegularOverrunError_Callback(void)
+{
+  /* Note: Disable ADC interruption that caused this error before entering in */
+  /*       infinite loop below.                                               */
+  
+  /* Disable ADC group regular overrun interruption */
+  LL_ADC_DisableIT_OVR(ADC1);
+  
+  /* Error from ADC */
+  LED_Blinking(LED_BLINK_ERROR);
+}
+
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..5b727f5c6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,248 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/ADC/ADC_Oversampling_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles EXTI line0 interrupt.
+  */
+void EXTI0_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI0_IRQn 0 */
+
+  /* USER CODE END EXTI0_IRQn 0 */
+  if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
+  {
+    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
+    /* USER CODE BEGIN LL_EXTI_LINE_0 */
+    
+    /* Handle user button press in dedicated function */
+    UserButton_Callback(); 
+    /* USER CODE END LL_EXTI_LINE_0 */
+  }
+  /* USER CODE BEGIN EXTI0_IRQn 1 */
+
+
+  /* USER CODE END EXTI0_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/**
+  * @brief  This function handles ADC1 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void ADC1_IRQHandler(void)
+{
+  /* Check whether ADC group regular overrun caused the ADC interruption */
+  if(LL_ADC_IsActiveFlag_OVR(ADC1) != 0)
+  {
+    /* Clear flag ADC group regular overrun */
+    LL_ADC_ClearFlag_OVR(ADC1);
+    
+    /* Call interruption treatment function */
+    AdcGrpRegularOverrunError_Callback();
+  }
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/readme.txt
new file mode 100644
index 000000000..a7eee0672
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_Oversampling_Init/readme.txt
@@ -0,0 +1,110 @@
+/**
+  @page ADC_Oversampling_Init ADC example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/ADC/ADC_Oversampling_Init/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the ADC_Oversampling_Init example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to use an ADC peripheral with ADC oversampling.
+This example is based on the STM32WBxx ADC LL API.
+The peripheral initialization done using LL unitary service functions for 
+optimization purposes (performance and size).
+
+Description of ADC oversampling:
+Multiple successive ADC conversions and average computation
+are performed automatically, by ADC hardware, and therefore
+off-load the CPU to do the equivalent task.
+This feature can be used for the functions: averaging,
+data rate reduction, SNR improvement, basic filtering.
+This example uses 3 configurations of oversampling,
+for comparison of final data to evaluate oversampling benefits.
+
+
+Example configuration:
+ADC is configured to convert a single channel, in single conversion mode,
+from SW trigger.
+ADC oversampling feature is used with 3 settings:
+ - ADC oversampling enabled: ratio 16, bits right shift 4.
+ - ADC oversampling enabled: ratio 16, no bits right shift.
+ - ADC oversampling disabled.
+
+LED2 is blinking every 1 sec in case of error. 
+
+Example execution:
+At each press on User push-button (SW1), with the 3 oversampling setting:
+the ADC converts the selected channel, software polls for conversion completion
+and stores conversion data into a variable.
+When all ADC conversions are completed, LED2 is turned on.
+The 3 ADC conversion data corresponding to each of the oversampling setting
+are evaluated (refer to loop "while (1)" of main program):
+ - data validity check and SW calculation of equivalent data
+   on 12 bits with floating point.
+ - user can evaluate the expected results of oversampling:
+   ADC conversion data with oversampling enabled has less variation
+   than with oversampling disabled, calculation performed by ADC HW
+   is equivalent to calculation performed by SW.
+
+For debug: variables to monitor with debugger watch window:
+ - "uhADCxConvertedData_OVS_ratio16_shift4": ADC group regular conversion data, oversampling ratio 16 and shift 4 (data scale: 12 bits)
+ - "uhADCxConvertedData_OVS_ratio16_shift0": ADC group regular conversion data, oversampling ratio 16 and shift 0 (data scale: 16 bits)
+ - "uhADCxConvertedData_OVS_disabled": ADC group regular conversion data, oversampling disabled (data scale corresponds to ADC resolution: 12 bits)
+ - "fConvertedData_OVS_EquivalentValue12bits": Calculation of oversampling raw data (from variable "uhADCxConvertedData_OVS_ratio16_shift0") to the equivalent data on 12 bits with floating point.
+
+Connection needed:
+None.
+Note: Optionally, a voltage can be supplied to the analog input pin (cf pin below),
+      between 0V and Vdda=3.3V, to perform a ADC conversion on a determined
+      voltage level.
+      Otherwise, this pin can be let floating (in this case ADC conversion data
+      will be undetermined).
+
+Other peripherals used:
+  1 GPIO for User push-button (SW1)
+  1 GPIO for LED2
+  1 GPIO for analog input: PA.01 (Arduino connector CN8 pin A2, Morpho connector CN7 pin 32)
+@par Keywords
+
+ADC, ADC channel, ADC oversampling, ADC group regular conversion, conversion, interrupt,
+
+@par Directory contents 
+
+  - ADC/ADC_Oversampling_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - ADC/ADC_Oversampling_Init/Inc/main.h                  Header for main.c module
+  - ADC/ADC_Oversampling_Init/Inc/stm32_assert.h          Template file to include assert_failed function
+  - ADC/ADC_Oversampling_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - ADC/ADC_Oversampling_Init/Src/main.c                  Main program
+  - ADC/ADC_Oversampling_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/ADC_SingleConversion_TriggerSW_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/ADC_SingleConversion_TriggerSW_Init.ioc
new file mode 100644
index 000000000..ce2a96113
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/ADC_SingleConversion_TriggerSW_Init.ioc
@@ -0,0 +1,145 @@
+#MicroXplorer Configuration settings - do not modify
+ADC1.Channel-10\#ChannelRegularConversion=ADC_CHANNEL_6
+ADC1.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV2
+ADC1.ContinuousConvMode=DISABLE
+ADC1.DMAContinuousRequests=DISABLE
+ADC1.DataAlign=ADC_DATAALIGN_RIGHT
+ADC1.DiscontinuousConvMode=DISABLE
+ADC1.EOCSelection=ADC_EOC_SEQ_CONV
+ADC1.EnableAnalogWatchDog1=false
+ADC1.EnableAnalogWatchDog2=false
+ADC1.EnableAnalogWatchDog3=false
+ADC1.ExternalTrigConv=ADC_SOFTWARE_START
+ADC1.ExternalTrigConvEdge=ADC_EXTERNALTRIGCONVEDGE_NONE
+ADC1.IPParameters=ClockPrescaler,Resolution,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,DMAContinuousRequests,EOCSelection,Overrun,LowPowerAutoWait,OversamplingMode,NbrOfConversion,ExternalTrigConv,ExternalTrigConvEdge,EnableAnalogWatchDog1,EnableAnalogWatchDog2,EnableAnalogWatchDog3,Rank-10\#ChannelRegularConversion,Channel-10\#ChannelRegularConversion,SamplingTime-10\#ChannelRegularConversion,master
+ADC1.LowPowerAutoWait=DISABLE
+ADC1.NbrOfConversion=1
+ADC1.Overrun=ADC_OVR_DATA_OVERWRITTEN
+ADC1.OversamplingMode=DISABLE
+ADC1.Rank-10\#ChannelRegularConversion=1
+ADC1.Resolution=ADC_RESOLUTION_12B
+ADC1.SamplingTime-10\#ChannelRegularConversion=ADC_SAMPLETIME_247CYCLES_5
+ADC1.ScanConvMode=ADC_SCAN_DISABLE
+ADC1.master=1
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=ADC1
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA0
+Mcu.Pin1=PA1
+Mcu.Pin2=PB0
+Mcu.Pin3=VP_SYS_VS_Systick
+Mcu.PinsNb=4
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.EXTI0_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA0.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultEXTI
+PA0.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
+PA0.GPIO_PuPd=GPIO_PULLUP
+PA0.Locked=true
+PA0.Signal=GPXTI0
+PA1.Signal=ADCx_IN6
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=false
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=ADC_SingleConversion_TriggerSW_Init.ioc
+ProjectManager.ProjectName=ADC_SingleConversion_TriggerSW_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-true,3-MX_ADC1_Init-ADC1-false-LL-true
+RCC.AHBFreq_Value=16000000
+RCC.APB1Freq_Value=16000000
+RCC.APB1TimFreq_Value=16000000
+RCC.APB2Freq_Value=16000000
+RCC.APB2TimFreq_Value=16000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=16000000
+RCC.CortexFreq_Value=16000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=16000000
+RCC.FCLKCortexFreq_Value=16000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=16000000
+RCC.HCLK3Freq_Value=16000000
+RCC.HCLKFreq_Value=16000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=16000000
+RCC.I2C3Freq_Value=16000000
+RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=16000000
+RCC.LPTIM2Freq_Value=16000000
+RCC.LPUART1Freq_Value=16000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=16000000
+RCC.PLLPoutputFreq_Value=16000000
+RCC.PLLQoutputFreq_Value=16000000
+RCC.PLLRCLKFreq_Value=16000000
+RCC.PWRFreq_Value=16000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=16000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_HSI
+RCC.USART1Freq_Value=16000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=32000000
+SH.ADCx_IN6.0=ADC1_IN6,IN6-Single-Ended
+SH.ADCx_IN6.ConfNb=1
+SH.GPXTI0.0=GPIO_EXTI0
+SH.GPXTI0.ConfNb=1
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/ADC_SingleConversion_TriggerSW_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/ADC_SingleConversion_TriggerSW_Init.ewd
new file mode 100644
index 000000000..f38ef5977
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/ADC_SingleConversion_TriggerSW_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		ADC_SingleConversion_TriggerSW_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/ADC_SingleConversion_TriggerSW_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/ADC_SingleConversion_TriggerSW_Init.ewp
new file mode 100644
index 000000000..c62613774
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/ADC_SingleConversion_TriggerSW_Init.ewp
@@ -0,0 +1,1089 @@
+
+
+  3
+  
+    ADC_SingleConversion_TriggerSW_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/Project.eww
new file mode 100644
index 000000000..5d4550e51
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\ADC_SingleConversion_TriggerSW_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Inc/main.h
new file mode 100644
index 000000000..2ec84910d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Inc/main.h
@@ -0,0 +1,112 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_adc.h"
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* Define used to enable time-out management*/
+#define USE_TIMEOUT       0
+
+/**
+  * @brief Toggle periods for various blinking modes
+  */
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW  500
+#define LED_BLINK_ERROR 1000
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* IRQ Handler treatment */
+void UserButton_Callback(void);
+void AdcGrpRegularOverrunError_Callback(void);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..a191c2f17
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,74 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void EXTI0_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+void USER_BUTTON_IRQHANDLER(void);
+
+void ADC1_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/MDK-ARM/ADC_SingleConversion_TriggerSW_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/MDK-ARM/ADC_SingleConversion_TriggerSW_Init.uvoptx
new file mode 100644
index 000000000..5140a8fb9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/MDK-ARM/ADC_SingleConversion_TriggerSW_Init.uvoptx
@@ -0,0 +1,357 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    ADC_SingleConversion_TriggerSW_Init
+    0x4
+    ARM-ADS
+    
+      16000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      4
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      4
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+      stm32wbxx_ll_adc.c
+      0
+      0
+    
+    
+      4
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      stm32wbxx_ll_dma.c
+      0
+      0
+    
+    
+      4
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/MDK-ARM/ADC_SingleConversion_TriggerSW_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/MDK-ARM/ADC_SingleConversion_TriggerSW_Init.uvprojx
new file mode 100644
index 000000000..6d3c27652
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/MDK-ARM/ADC_SingleConversion_TriggerSW_Init.uvprojx
@@ -0,0 +1,482 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      ADC_SingleConversion_TriggerSW_Init
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          ADC_SingleConversion_TriggerSW_Init\
+          ADC_SingleConversion_TriggerSW_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_adc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+            
+            
+              stm32wbxx_ll_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..179a8445e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..d4f177094
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/.project
@@ -0,0 +1,90 @@
+
+
+	ADC_SingleConversion_TriggerSW_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			ADC_SingleConversion_TriggerSW_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/ADC_SingleConversion_TriggerSW_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_adc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..eea98ff9c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb35xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB35xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..4ec95844d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,159 @@
+/**
+ ******************************************************************************
+ * @file      syscalls.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..4665417ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,58 @@
+/**
+ ******************************************************************************
+ * @file      sysmem.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System Memory calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Src/main.c
new file mode 100644
index 000000000..b99e2e686
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Src/main.c
@@ -0,0 +1,741 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to use a ADC peripheral to perform
+  *          a single ADC conversion of a channel, at each software start.
+  *          Example using programming model: polling 
+  *          (for programming models interrupt or DMA transfer, refer to
+  *          other examples).
+  *          This example is based on the STM32WBxx ADC LL API;
+  *          Peripheral initialization done using LL unitary services functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* Definitions of ADC hardware constraints delays */
+/* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */
+/*       not timeout values:                                                  */
+/*       Timeout values for ADC operations are dependent to device clock      */
+/*       configuration (system clock versus ADC clock),                       */
+/*       and therefore must be defined in user application.                   */
+/*       Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout     */
+/*       values definition.                                                   */
+
+  /* Timeout values for ADC operations. */
+  /* (calibration, enable settling time, disable settling time, ...)          */
+  /* Values defined to be higher than worst cases: low clock frequency,       */
+  /* maximum prescalers.                                                      */
+  #define ADC_CALIBRATION_TIMEOUT_MS       (   1U)
+  #define ADC_ENABLE_TIMEOUT_MS            (   1U)
+  #define ADC_DISABLE_TIMEOUT_MS           (   1U)
+  #define ADC_STOP_CONVERSION_TIMEOUT_MS   (   1U)
+  #define ADC_CONVERSION_TIMEOUT_MS        ( 500U)
+  
+  /* Delay between ADC end of calibration and ADC enable.                     */
+  /* Delay estimation in CPU cycles: Case of ADC enable done                  */
+  /* immediately after ADC calibration, ADC clock setting slow                */
+  /* (LL_ADC_CLOCK_ASYNC_DIV32). Use a higher delay if ratio                  */
+  /* (CPU clock / ADC clock) is above 32.                                     */
+  #define ADC_DELAY_CALIB_ENABLE_CPU_CYCLES  (LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES * 32)
+  
+
+/* Definitions of environment analog values */
+  /* Value of analog reference voltage (Vref+), connected to analog voltage   */
+  /* supply Vdda (unit: mV).                                                  */
+  #define VDDA_APPLI                       (3300UL)
+
+/* Definitions of data related to this example */
+  /* ADC unitary conversion timeout */
+  /* Considering ADC settings, duration of 1 ADC conversion should always    */
+  /* be lower than 1ms.                                                      */
+  #define ADC_UNITARY_CONVERSION_TIMEOUT_MS (   1UL)
+
+  /* Init variable out of expected ADC conversion data range */
+  #define VAR_CONVERTED_DATA_INIT_VALUE    (__LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B) + 1)
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+__IO uint32_t ubUserButtonPressed = 0UL;
+
+/* Variables for ADC conversion data */
+__IO uint16_t uhADCxConvertedData = VAR_CONVERTED_DATA_INIT_VALUE; /* ADC group regular conversion data */
+
+/* Variables for ADC conversion data computation to physical values */
+__IO uint16_t uhADCxConvertedData_Voltage_mVolt = 0UL;  /* Value of voltage calculated from ADC conversion data (unit: mV) */
+
+/* Variable to report status of ADC group regular unitary conversion          */
+/*  0: ADC group regular unitary conversion is not completed                  */
+/*  1: ADC group regular unitary conversion is completed                      */
+/*  2: ADC group regular unitary conversion has not been started yet          */
+/*     (initial state)                                                        */
+__IO uint8_t ubAdcGrpRegularUnitaryConvStatus = 2U; /* Variable set into ADC interruption callback */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_ADC1_Init(void);
+/* USER CODE BEGIN PFP */
+void     Activate_ADC(void);
+void     ConversionStartPoll_ADC_GrpRegular(void);
+void     LED_On(void);
+void     LED_Off(void);
+void     LED_Blinking(uint32_t Period);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_ADC1_Init();
+  /* USER CODE BEGIN 2 */
+  
+  /* Configure ADC */
+  /* Note: This function configures the ADC but does not enable it.           */
+  /*       To enable it, use function "Activate_ADC()".                       */
+  /*       This is intended to optimize power consumption:                    */
+  /*       1. ADC configuration can be done once at the beginning             */
+  /*          (ADC disabled, minimal power consumption)                       */
+  /*       2. ADC enable (higher power consumption) can be done just before   */
+  /*          ADC conversions needed.                                         */
+  /*          Then, possible to perform successive "Activate_ADC()",          */
+  /*          "Deactivate_ADC()", ..., without having to set again            */
+  /*          ADC configuration.                                              */
+  // Configure_ADC();
+  
+  /* Activate ADC */
+  /* Perform ADC activation procedure to make it ready to convert. */
+  Activate_ADC();
+  
+  /* Disable SMPS: SMPS in mode step-down can impact ADC conversion accuracy. */
+  /* It is recommnended to disable SMPS (stop SMPS switching by setting it    */
+  /* in mode bypass) during ADC conversion.                                   */
+  /* Get SMPS effective operating mode */
+  if(LL_PWR_SMPS_GetEffectiveMode() == LL_PWR_SMPS_STEP_DOWN)
+  {
+    /* Set SMPS operating mode */
+    LL_PWR_SMPS_SetMode(LL_PWR_SMPS_BYPASS);
+  }
+  
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* Wait for user press on push button */
+    while (ubUserButtonPressed != 1)
+    {
+    }
+    ubUserButtonPressed = 0;
+    
+    /* Turn LED off before performing a new ADC conversion start */
+    LED_Off();
+    
+    /* Reset status variable of ADC unitary conversion before performing      */
+    /* a new ADC conversion start.                                            */
+    /* Note: Optionally, for this example purpose, check ADC unitary          */
+    /*       conversion status before starting another ADC conversion.        */
+    
+    if (ubAdcGrpRegularUnitaryConvStatus != 0)
+    {
+      ubAdcGrpRegularUnitaryConvStatus = 0;
+    }
+    else
+    {
+      /* Error: Previous action (ADC conversion not yet completed).           */
+      LED_Blinking(LED_BLINK_ERROR);
+    }
+    
+    /* Init variable containing ADC conversion data */
+    uhADCxConvertedData = VAR_CONVERTED_DATA_INIT_VALUE;
+    
+    /* Perform ADC group regular conversion start, poll for conversion        */
+    /* completion.                                                            */
+    ConversionStartPoll_ADC_GrpRegular();
+    
+    /* Retrieve ADC conversion data */
+    /* (data scale corresponds to ADC resolution: 12 bits) */
+    uhADCxConvertedData = LL_ADC_REG_ReadConversionData12(ADC1);
+    
+    /* Update status variable of ADC unitary conversion */
+    ubAdcGrpRegularUnitaryConvStatus = 1;
+    
+    /* Set LED depending on ADC unitary conversion status */
+    /* - Turn-on if ADC unitary conversion is completed */
+    /* - Turn-off if ADC unitary conversion is not completed */
+    LED_On();
+    
+    /* Computation of ADC conversions raw data to physical values           */
+    /* using LL ADC driver helper macro.                                    */
+    uhADCxConvertedData_Voltage_mVolt = __LL_ADC_CALC_DATA_TO_VOLTAGE(VDDA_APPLI, uhADCxConvertedData, LL_ADC_RESOLUTION_12B);
+    
+    
+    /* Note: ADC conversion data is stored into variable                      */
+    /*       "uhADCxConvertedData".                                           */
+    /*       (for debug: see variable content into watch window).             */
+    
+
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  /* HSI configuration and activation */
+  LL_RCC_HSI_Enable();
+  while(LL_RCC_HSI_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the HSI */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(16000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(16000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief ADC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC1_Init(void)
+{
+
+  /* USER CODE BEGIN ADC1_Init 0 */
+
+  /* USER CODE END ADC1_Init 0 */
+
+  LL_ADC_CommonInitTypeDef ADC_CommonInitStruct = {0};
+  LL_ADC_InitTypeDef ADC_InitStruct = {0};
+  LL_ADC_REG_InitTypeDef ADC_REG_InitStruct = {0};
+
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* Peripheral clock enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC);
+  
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  /**ADC1 GPIO Configuration  
+  PA1   ------> ADC1_IN6 
+  */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_1;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN ADC1_Init 1 */
+  
+  /* Configure NVIC to enable ADC1 interruptions */
+  NVIC_SetPriority(ADC1_IRQn, 0);
+  NVIC_EnableIRQ(ADC1_IRQn);
+  /* USER CODE END ADC1_Init 1 */
+  /** Common config 
+  */
+  ADC_CommonInitStruct.CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
+  LL_ADC_CommonInit(__LL_ADC_COMMON_INSTANCE(ADC1), &ADC_CommonInitStruct);
+  ADC_InitStruct.Resolution = LL_ADC_RESOLUTION_12B;
+  ADC_InitStruct.DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
+  ADC_InitStruct.LowPowerMode = LL_ADC_LP_MODE_NONE;
+  LL_ADC_Init(ADC1, &ADC_InitStruct);
+  ADC_REG_InitStruct.TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
+  ADC_REG_InitStruct.SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
+  ADC_REG_InitStruct.SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+  ADC_REG_InitStruct.ContinuousMode = LL_ADC_REG_CONV_SINGLE;
+  ADC_REG_InitStruct.DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
+  ADC_REG_InitStruct.Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
+  LL_ADC_REG_Init(ADC1, &ADC_REG_InitStruct);
+  LL_ADC_SetOverSamplingScope(ADC1, LL_ADC_OVS_DISABLE);
+  LL_ADC_DisableIT_EOC(ADC1);
+  LL_ADC_DisableIT_EOS(ADC1);
+  /** Configure Regular Channel 
+  */
+  LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_1, LL_ADC_CHANNEL_6);
+  LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_6, LL_ADC_SAMPLINGTIME_247CYCLES_5);
+  LL_ADC_SetChannelSingleDiff(ADC1, LL_ADC_CHANNEL_6, LL_ADC_SINGLE_ENDED);
+  /* USER CODE BEGIN ADC1_Init 2 */
+  
+  /* Configuration of ADC interruptions */
+  /* Enable interruption ADC group regular overrun */
+  LL_ADC_EnableIT_OVR(ADC1);
+  /* USER CODE END ADC1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_EXTI_InitTypeDef EXTI_InitStruct = {0};
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTA, LL_SYSCFG_EXTI_LINE0);
+
+  /**/
+  EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_0;
+  EXTI_InitStruct.Line_32_63 = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct.LineCommand = ENABLE;
+  EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;
+  EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_FALLING;
+  LL_EXTI_Init(&EXTI_InitStruct);
+
+  /**/
+  LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_0, LL_GPIO_PULL_UP);
+
+  /**/
+  LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_0, LL_GPIO_MODE_INPUT);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+  /* EXTI interrupt init*/
+  NVIC_SetPriority(EXTI0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(EXTI0_IRQn);
+
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Perform ADC activation procedure to make it ready to convert
+  *         (ADC instance: ADC1).
+  * @note   Operations:
+  *         - ADC instance
+  *           - Disable deep power down
+  *           - Enable internal voltage regulator
+  *           - Run ADC self calibration
+  *           - Enable ADC
+  *         - ADC group regular
+  *           none: ADC conversion start-stop to be performed
+  *                 after this function
+  *         - ADC group injected
+  *           none: ADC conversion start-stop to be performed
+  *                 after this function
+  * @param  None
+  * @retval None
+  */
+void Activate_ADC(void)
+{
+  __IO uint32_t wait_loop_index = 0U;
+  #if (USE_TIMEOUT == 1)
+  uint32_t Timeout = 0U; /* Variable used for timeout management */
+  #endif /* USE_TIMEOUT */
+  
+  /*## Operation on ADC hierarchical scope: ADC instance #####################*/
+  
+  /* Note: Hardware constraint (refer to description of the functions         */
+  /*       below):                                                            */
+  /*       On this STM32 serie, setting of these features is conditioned to   */
+  /*       ADC state:                                                         */
+  /*       ADC must be disabled.                                              */
+  /* Note: In this example, all these checks are not necessary but are        */
+  /*       implemented anyway to show the best practice usages                */
+  /*       corresponding to reference manual procedure.                       */
+  /*       Software can be optimized by removing some of these checks, if     */
+  /*       they are not relevant considering previous settings and actions    */
+  /*       in user application.                                               */
+  if (LL_ADC_IsEnabled(ADC1) == 0)
+  {
+    /* Disable ADC deep power down (enabled by default after reset state) */
+    LL_ADC_DisableDeepPowerDown(ADC1);
+    
+    /* Enable ADC internal voltage regulator */
+    LL_ADC_EnableInternalRegulator(ADC1);
+    
+    /* Delay for ADC internal voltage regulator stabilization.                */
+    /* Compute number of CPU cycles to wait for, from delay in us.            */
+    /* Note: Variable divided by 2 to compensate partially                    */
+    /*       CPU processing cycles (depends on compilation optimization).     */
+    /* Note: If system core clock frequency is below 200kHz, wait time        */
+    /*       is only a few CPU processing cycles.                             */
+    wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (100000 * 2))) / 10);
+    while(wait_loop_index != 0)
+    {
+      wait_loop_index--;
+    }
+    
+    /* Run ADC self calibration */
+    LL_ADC_StartCalibration(ADC1, LL_ADC_SINGLE_ENDED);
+    
+    /* Poll for ADC effectively calibrated */
+    #if (USE_TIMEOUT == 1)
+    Timeout = ADC_CALIBRATION_TIMEOUT_MS;
+    #endif /* USE_TIMEOUT */
+    
+    while (LL_ADC_IsCalibrationOnGoing(ADC1) != 0)
+    {
+    #if (USE_TIMEOUT == 1)
+      /* Check Systick counter flag to decrement the time-out value */
+      if (LL_SYSTICK_IsActiveCounterFlag())
+      {
+        if(Timeout-- == 0)
+        {
+        /* Time-out occurred. Set LED to blinking mode */
+        LED_Blinking(LED_BLINK_ERROR);
+        }
+      }
+    #endif /* USE_TIMEOUT */
+    }
+    
+    /* Delay between ADC end of calibration and ADC enable.                   */
+    /* Note: Variable divided by 2 to compensate partially                    */
+    /*       CPU processing cycles (depends on compilation optimization).     */
+    wait_loop_index = (ADC_DELAY_CALIB_ENABLE_CPU_CYCLES >> 1);
+    while(wait_loop_index != 0)
+    {
+      wait_loop_index--;
+    }
+    
+    /* Enable ADC */
+    LL_ADC_Enable(ADC1);
+    
+    /* Poll for ADC ready to convert */
+    #if (USE_TIMEOUT == 1)
+    Timeout = ADC_ENABLE_TIMEOUT_MS;
+    #endif /* USE_TIMEOUT */
+    
+    while (LL_ADC_IsActiveFlag_ADRDY(ADC1) == 0)
+    {
+    #if (USE_TIMEOUT == 1)
+      /* Check Systick counter flag to decrement the time-out value */
+      if (LL_SYSTICK_IsActiveCounterFlag())
+      {
+        if(Timeout-- == 0)
+        {
+        /* Time-out occurred. Set LED to blinking mode */
+        LED_Blinking(LED_BLINK_ERROR);
+        }
+      }
+    #endif /* USE_TIMEOUT */
+    }
+    
+    /* Note: ADC flag ADRDY is not cleared here to be able to check ADC       */
+    /*       status afterwards.                                               */
+    /*       This flag should be cleared at ADC Deactivation, before a new    */
+    /*       ADC activation, using function "LL_ADC_ClearFlag_ADRDY()".       */
+  }
+  
+  /*## Operation on ADC hierarchical scope: ADC group regular ################*/
+  /* Note: No operation on ADC group regular performed here.                  */
+  /*       ADC group regular conversions to be performed after this function  */
+  /*       using function:                                                    */
+  /*       "LL_ADC_REG_StartConversion();"                                    */
+  
+  /*## Operation on ADC hierarchical scope: ADC group injected ###############*/
+  /* Note: No operation on ADC group injected performed here.                 */
+  /*       ADC group injected conversions to be performed after this function */
+  /*       using function:                                                    */
+  /*       "LL_ADC_INJ_StartConversion();"                                    */
+  
+}
+
+/**
+  * @brief  Perform ADC group regular conversion start, poll for conversion
+  *         completion.
+  *         (ADC instance: ADC1).
+  * @note   This function does not perform ADC group regular conversion stop:
+  *         intended to be used with ADC in single mode, trigger SW start
+  *         (only 1 ADC conversion done at each trigger, no conversion stop
+  *         needed).
+  *         In case of continuous mode or conversion trigger set to 
+  *         external trigger, ADC group regular conversion stop must be added.
+  * @param  None
+  * @retval None
+  */
+void ConversionStartPoll_ADC_GrpRegular(void)
+{
+  #if (USE_TIMEOUT == 1)
+  uint32_t Timeout = 0U; /* Variable used for timeout management */
+  #endif /* USE_TIMEOUT */
+  
+  /* Start ADC group regular conversion */
+  /* Note: Hardware constraint (refer to description of the function          */
+  /*       below):                                                            */
+  /*       On this STM32 serie, setting of this feature is conditioned to     */
+  /*       ADC state:                                                         */
+  /*       ADC must be enabled without conversion on going on group regular,  */
+  /*       without ADC disable command on going.                              */
+  /* Note: In this example, all these checks are not necessary but are        */
+  /*       implemented anyway to show the best practice usages                */
+  /*       corresponding to reference manual procedure.                       */
+  /*       Software can be optimized by removing some of these checks, if     */
+  /*       they are not relevant considering previous settings and actions    */
+  /*       in user application.                                               */
+  if ((LL_ADC_IsEnabled(ADC1) == 1)               &&
+      (LL_ADC_IsDisableOngoing(ADC1) == 0)        &&
+      (LL_ADC_REG_IsConversionOngoing(ADC1) == 0)   )
+  {
+    LL_ADC_REG_StartConversion(ADC1);
+  }
+  else
+  {
+    /* Error: ADC conversion start could not be performed */
+    LED_Blinking(LED_BLINK_ERROR);
+  }
+  
+  #if (USE_TIMEOUT == 1)
+  Timeout = ADC_UNITARY_CONVERSION_TIMEOUT_MS;
+  #endif /* USE_TIMEOUT */
+  
+  while (LL_ADC_IsActiveFlag_EOC(ADC1) == 0)
+  {
+  #if (USE_TIMEOUT == 1)
+    /* Check Systick counter flag to decrement the time-out value */
+    if (LL_SYSTICK_IsActiveCounterFlag())
+    {
+      if(Timeout-- == 0)
+      {
+      /* Time-out occurred. Set LED to blinking mode */
+      LED_Blinking(LED_BLINK_SLOW);
+      }
+    }
+  #endif /* USE_TIMEOUT */
+  }
+  
+  /* Clear flag ADC group regular end of unitary conversion */
+  /* Note: This action is not needed here, because flag ADC group regular   */
+  /*       end of unitary conversion is cleared automatically when          */
+  /*       software reads conversion data from ADC data register.           */
+  /*       Nevertheless, this action is done anyway to show how to clear    */
+  /*       this flag, needed if conversion data is not always read          */
+  /*       or if group injected end of unitary conversion is used (for      */
+  /*       devices with group injected available).                          */
+  LL_ADC_ClearFlag_EOC(ADC1);
+  
+}
+
+/**
+  * @brief  Turn-on LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_On(void)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Turn-off LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_Off(void)
+{
+  /* Turn LED2 off */
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
+  * @param  Period : Period of time (in ms) between each toggling of LED
+  *   This parameter can be user defined values. Pre-defined values used in that example are :
+  *     @arg LED_BLINK_FAST : Fast Blinking
+  *     @arg LED_BLINK_SLOW : Slow Blinking
+  *     @arg LED_BLINK_ERROR : Error specific Blinking
+  * @retval None
+  */
+void LED_Blinking(uint32_t Period)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+  
+  /* Toggle IO in an infinite loop */
+  while (1)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+    LL_mDelay(Period);
+  }
+}
+
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT                                               */
+/******************************************************************************/
+
+/**
+  * @brief  Function to manage IRQ Handler
+  * @param  None
+  * @retval None
+  */
+void UserButton_Callback(void)
+{
+  ubUserButtonPressed = 1;
+}
+
+/**
+  * @brief  ADC group regular overrun interruption callback
+  * @note   This function is executed when ADC group regular
+  *         overrun error occurs.
+  * @retval None
+  */
+void AdcGrpRegularOverrunError_Callback(void)
+{
+  /* Note: Disable ADC interruption that caused this error before entering in */
+  /*       infinite loop below.                                               */
+  
+  /* Disable ADC group regular overrun interruption */
+  LL_ADC_DisableIT_OVR(ADC1);
+  
+  /* Error from ADC */
+  LED_Blinking(LED_BLINK_ERROR);
+}
+
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..bfaa07758
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,248 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles EXTI line0 interrupt.
+  */
+void EXTI0_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI0_IRQn 0 */
+
+  /* USER CODE END EXTI0_IRQn 0 */
+  if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
+  {
+    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
+    /* USER CODE BEGIN LL_EXTI_LINE_0 */
+    
+    /* Handle user button press in dedicated function */
+    UserButton_Callback(); 
+    /* USER CODE END LL_EXTI_LINE_0 */
+  }
+  /* USER CODE BEGIN EXTI0_IRQn 1 */
+
+
+  /* USER CODE END EXTI0_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/**
+  * @brief  This function handles ADC1 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void ADC1_IRQHandler(void)
+{
+  /* Check whether ADC group regular overrun caused the ADC interruption */
+  if(LL_ADC_IsActiveFlag_OVR(ADC1) != 0)
+  {
+    /* Clear flag ADC group regular overrun */
+    LL_ADC_ClearFlag_OVR(ADC1);
+    
+    /* Call interruption treatment function */
+    AdcGrpRegularOverrunError_Callback();
+  }
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/readme.txt
new file mode 100644
index 000000000..6f4ebc9aa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/readme.txt
@@ -0,0 +1,88 @@
+/**
+  @page ADC_SingleConversion_TriggerSW_Init ADC example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/ADC/ADC_SingleConversion_TriggerSW_Init/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the ADC_SingleConversion_TriggerSW_Init example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to use an ADC peripheral to perform a single ADC conversion on a channel 
+at each software start. This example uses the polling programming model (for 
+interrupt or DMA programming models, please refer to other examples).
+This example is based on the STM32WBxx ADC LL API.
+The peripheral initialization is done using LL unitary service functions for 
+optimization purposes (performance and size).
+
+Example configuration:
+ADC is configured to convert a single channel, in single conversion mode,
+from SW trigger.
+
+Example execution:
+At each press on User push-button (SW1), the ADC performs 1 conversion of the selected channel.
+Software polls for conversion completion.
+When conversion is completed, main program reads conversion data
+from ADC data register and stores it into a variable, LED2 is turned on.
+
+For debug: variables to monitor with debugger watch window:
+ - "uhADCxConvertedData": ADC group regular conversion data
+ - "uhADCxConvertedData_Voltage_mVolt": ADC conversion data computation to physical values
+
+LED2 is blinking every 1 sec in case of error. 
+
+Connection needed:
+None.
+Note: Optionally, a voltage can be supplied to the analog input pin (cf pin below),
+      between 0V and Vdda=3.3V, to perform a ADC conversion on a determined
+      voltage level.
+      Otherwise, this pin can be let floating (in this case ADC conversion data
+      will be undetermined).
+
+Other peripherals used:
+  1 GPIO for User push-button (SW1)
+  1 GPIO for LED2
+  1 GPIO for analog input: PA.01 (Arduino connector CN8 pin A2, Morpho connector CN7 pin 32)
+@par Keywords
+
+ADC, ADC channel, conversion, single channel, single conversion mode, interrupt,
+
+@par Directory contents 
+
+  - ADC/ADC_SingleConversion_TriggerSW_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - ADC/ADC_SingleConversion_TriggerSW_Init/Inc/main.h                  Header for main.c module
+  - ADC/ADC_SingleConversion_TriggerSW_Init/Inc/stm32_assert.h          Template file to include assert_failed function
+  - ADC/ADC_SingleConversion_TriggerSW_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - ADC/ADC_SingleConversion_TriggerSW_Init/Src/main.c                  Main program
+  - ADC/ADC_SingleConversion_TriggerSW_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/COMP_CompareGpioVsVrefInt_Window_IT_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/COMP_CompareGpioVsVrefInt_Window_IT_Init.ioc
new file mode 100644
index 000000000..4d9abe812
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/COMP_CompareGpioVsVrefInt_Window_IT_Init.ioc
@@ -0,0 +1,136 @@
+#MicroXplorer Configuration settings - do not modify
+COMP1.BlankingSrce=COMP_BLANKINGSRC_NONE
+COMP1.Hysteresis=COMP_HYSTERESIS_NONE
+COMP1.IPParameters=Mode,TriggerMode,Hysteresis,BlankingSrce,OutputPol
+COMP1.Mode=COMP_POWERMODE_MEDIUMSPEED
+COMP1.OutputPol=COMP_OUTPUTPOL_NONINVERTED
+COMP1.TriggerMode=COMP_TRIGGERMODE_IT_RISING_FALLING
+COMP2.BlankingSrce=COMP_BLANKINGSRC_NONE
+COMP2.Hysteresis=COMP_HYSTERESIS_LOW
+COMP2.IPParameters=Mode,TriggerMode,Hysteresis,BlankingSrce,OutputPol,WindowMode
+COMP2.Mode=COMP_POWERMODE_MEDIUMSPEED
+COMP2.OutputPol=COMP_OUTPUTPOL_NONINVERTED
+COMP2.TriggerMode=COMP_TRIGGERMODE_IT_RISING_FALLING
+COMP2.WindowMode=COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+File.Version=6
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=COMP1
+Mcu.IP1=COMP2
+Mcu.IP2=NVIC
+Mcu.IP3=RCC
+Mcu.IP4=SYS
+Mcu.IPNb=5
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA1
+Mcu.Pin1=PB0
+Mcu.Pin2=VP_COMP1_VS_VREFINT
+Mcu.Pin3=VP_COMP2_VS_WindowMode
+Mcu.Pin4=VP_COMP2_VS_VREFINT12
+Mcu.Pin5=VP_SYS_VS_Systick
+Mcu.PinsNb=6
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.COMP_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA1.Mode=INP
+PA1.Signal=COMP1_INP
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=3
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=COMP_CompareGpioVsVrefInt_Window_IT_Init.ioc
+ProjectManager.ProjectName=COMP_CompareGpioVsVrefInt_Window_IT_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false,3-MX_COMP1_Init-COMP1-false-LL-true,4-MX_COMP2_Init-COMP2-false-LL-true
+RCC.AHBFreq_Value=16000000
+RCC.APB1Freq_Value=16000000
+RCC.APB1TimFreq_Value=16000000
+RCC.APB2Freq_Value=16000000
+RCC.APB2TimFreq_Value=16000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=16000000
+RCC.CortexFreq_Value=16000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=16000000
+RCC.FCLKCortexFreq_Value=16000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=16000000
+RCC.HCLK3Freq_Value=16000000
+RCC.HCLKFreq_Value=16000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=16000000
+RCC.I2C3Freq_Value=16000000
+RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=16000000
+RCC.LPTIM2Freq_Value=16000000
+RCC.LPUART1Freq_Value=16000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=16000000
+RCC.PLLPoutputFreq_Value=16000000
+RCC.PLLQoutputFreq_Value=16000000
+RCC.PLLRCLKFreq_Value=16000000
+RCC.PWRFreq_Value=16000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=16000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_HSI
+RCC.USART1Freq_Value=16000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=32000000
+VP_COMP1_VS_VREFINT.Mode=VREFINT
+VP_COMP1_VS_VREFINT.Signal=COMP1_VS_VREFINT
+VP_COMP2_VS_VREFINT12.Mode=VREFINT_12
+VP_COMP2_VS_VREFINT12.Signal=COMP2_VS_VREFINT12
+VP_COMP2_VS_WindowMode.Mode=WindowMode
+VP_COMP2_VS_WindowMode.Signal=COMP2_VS_WindowMode
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/COMP_CompareGpioVsVrefInt_Window_IT_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/COMP_CompareGpioVsVrefInt_Window_IT_Init.ewd
new file mode 100644
index 000000000..3a70aa900
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/COMP_CompareGpioVsVrefInt_Window_IT_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		COMP_CompareGpioVsVrefInt_Window_IT_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/COMP_CompareGpioVsVrefInt_Window_IT_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/COMP_CompareGpioVsVrefInt_Window_IT_Init.ewp
new file mode 100644
index 000000000..7109ddcfa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/COMP_CompareGpioVsVrefInt_Window_IT_Init.ewp
@@ -0,0 +1,1089 @@
+
+
+  3
+  
+    COMP_CompareGpioVsVrefInt_Window_IT_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_comp.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/Project.eww
new file mode 100644
index 000000000..9fc0ff71d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\COMP_CompareGpioVsVrefInt_Window_IT_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/stm32wb35xx_sram_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/stm32wb35xx_sram_cm4.icf
new file mode 100644
index 000000000..6426355fb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/EWARM/stm32wb35xx_sram_cm4.icf
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20003FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20004000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20008000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x2000FFFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Inc/main.h
new file mode 100644
index 000000000..6a37389a3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Inc/main.h
@@ -0,0 +1,100 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_comp.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "stm32wbxx_ll_bus.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+void ComparatorTrigger_Callback(void);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..f8aa74609
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void COMP_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/MDK-ARM/COMP_CompareGpioVsVrefInt_Window_IT_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/MDK-ARM/COMP_CompareGpioVsVrefInt_Window_IT_Init.uvoptx
new file mode 100644
index 000000000..f84317ef6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/MDK-ARM/COMP_CompareGpioVsVrefInt_Window_IT_Init.uvoptx
@@ -0,0 +1,357 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    COMP_CompareGpioVsVrefInt_Window_IT_Init
+    0x4
+    ARM-ADS
+    
+      16000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_comp.c
+      stm32wbxx_ll_comp.c
+      0
+      0
+    
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+      stm32wbxx_ll_rcc.c
+      0
+      0
+    
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/MDK-ARM/COMP_CompareGpioVsVrefInt_Window_IT_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/MDK-ARM/COMP_CompareGpioVsVrefInt_Window_IT_Init.uvprojx
new file mode 100644
index 000000000..df4509edd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/MDK-ARM/COMP_CompareGpioVsVrefInt_Window_IT_Init.uvprojx
@@ -0,0 +1,481 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      COMP_CompareGpioVsVrefInt_Window_IT_Init
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          COMP_CompareGpioVsVrefInt_Window_IT_Init\
+          COMP_CompareGpioVsVrefInt_Window_IT_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_comp.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_comp.c
+            
+            
+              stm32wbxx_ll_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..d59732a8e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..c621e5b65
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/.project
@@ -0,0 +1,90 @@
+
+
+	COMP_CompareGpioVsVrefInt_Window_IT_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			COMP_CompareGpioVsVrefInt_Window_IT_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/COMP_CompareGpioVsVrefInt_Window_IT_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_comp.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_comp.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Src/main.c
new file mode 100644
index 000000000..a39a9c945
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Src/main.c
@@ -0,0 +1,446 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example shows how to use a pair of comparator peripherals
+  *          to compare a voltage level applied on a GPIO pin
+  *          versus 2 thresholds: the internal voltage reference (VrefInt)
+  *          and a fraction the internal voltage reference (VrefInt/2),
+  *          in interrupt mode.
+  *          This example is based on the STM32WBxx COMP LL API;
+  *          Peripheral initialization done using LL unitary services functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_COMP1_Init(void);
+static void MX_COMP2_Init(void);
+/* USER CODE BEGIN PFP */
+void     SystemClock_Config(void);
+void     Activate_COMP_master_slave(void);
+void     LED_On(void);
+void     LED_Off(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_COMP1_Init();
+  MX_COMP2_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Activate pair of comparators */
+  Activate_COMP_master_slave();
+
+  /* Lock comparator instance */
+  //LL_COMP_Lock(COMP1);
+
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* Note: LED state depending on COMP status is set into COMP IRQ handler, */
+    /*        refer to function "ComparatorTrigger_Callback()".               */
+
+
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  /* HSI configuration and activation */
+  LL_RCC_HSI_Enable();
+  while(LL_RCC_HSI_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the HSI */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(16000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(16000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief COMP1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_COMP1_Init(void)
+{
+
+  /* USER CODE BEGIN COMP1_Init 0 */
+
+  /* USER CODE END COMP1_Init 0 */
+
+  LL_COMP_InitTypeDef COMP_InitStruct = {0};
+
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  /**COMP1 GPIO Configuration  
+  PA1   ------> COMP1_INP 
+  */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_1;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* COMP1 interrupt Init */
+  NVIC_SetPriority(COMP_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(COMP_IRQn);
+
+  /* USER CODE BEGIN COMP1_Init 1 */
+
+  /* USER CODE END COMP1_Init 1 */
+  COMP_InitStruct.PowerMode = LL_COMP_POWERMODE_MEDIUMSPEED;
+  COMP_InitStruct.InputPlus = LL_COMP_INPUT_PLUS_IO3;
+  COMP_InitStruct.InputMinus = LL_COMP_INPUT_MINUS_VREFINT;
+  COMP_InitStruct.InputHysteresis = LL_COMP_HYSTERESIS_NONE;
+  COMP_InitStruct.OutputPolarity = LL_COMP_OUTPUTPOL_NONINVERTED;
+  COMP_InitStruct.OutputBlankingSource = LL_COMP_BLANKINGSRC_NONE;
+  LL_COMP_Init(COMP1, &COMP_InitStruct);
+  LL_COMP_SetCommonWindowMode(__LL_COMP_COMMON_INSTANCE(COMP1), LL_COMP_WINDOWMODE_DISABLE);
+
+  /* Wait loop initialization and execution */
+  /* Note: Variable divided by 2 to compensate partially CPU processing cycles */
+  __IO uint32_t wait_loop_index = 0;
+  wait_loop_index = (LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000 * 2)));
+  while(wait_loop_index != 0)
+  {
+    wait_loop_index--;
+  }
+  LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_20);
+  LL_EXTI_EnableFallingTrig_0_31(LL_EXTI_LINE_20);
+  LL_EXTI_EnableRisingTrig_0_31(LL_EXTI_LINE_20);
+  LL_EXTI_DisableEvent_0_31(LL_EXTI_LINE_20);
+  LL_EXTI_EnableIT_0_31(LL_EXTI_LINE_20);
+  /* USER CODE BEGIN COMP1_Init 2 */
+
+  /* USER CODE END COMP1_Init 2 */
+
+}
+
+/**
+  * @brief COMP2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_COMP2_Init(void)
+{
+
+  /* USER CODE BEGIN COMP2_Init 0 */
+
+  /* USER CODE END COMP2_Init 0 */
+
+  LL_COMP_InitTypeDef COMP_InitStruct = {0};
+
+  /* COMP2 interrupt Init */
+  NVIC_SetPriority(COMP_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(COMP_IRQn);
+
+  /* USER CODE BEGIN COMP2_Init 1 */
+
+  /* USER CODE END COMP2_Init 1 */
+  COMP_InitStruct.PowerMode = LL_COMP_POWERMODE_MEDIUMSPEED;
+  COMP_InitStruct.InputPlus = LL_COMP_INPUT_PLUS_IO1;
+  COMP_InitStruct.InputMinus = LL_COMP_INPUT_MINUS_1_2VREFINT;
+  COMP_InitStruct.InputHysteresis = LL_COMP_HYSTERESIS_LOW;
+  COMP_InitStruct.OutputPolarity = LL_COMP_OUTPUTPOL_NONINVERTED;
+  COMP_InitStruct.OutputBlankingSource = LL_COMP_BLANKINGSRC_NONE;
+  LL_COMP_Init(COMP2, &COMP_InitStruct);
+  LL_COMP_SetCommonWindowMode(__LL_COMP_COMMON_INSTANCE(COMP2), LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON);
+
+  /* Wait loop initialization and execution */
+  /* Note: Variable divided by 2 to compensate partially CPU processing cycles */
+  __IO uint32_t wait_loop_index = 0;
+  wait_loop_index = (LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000 * 2)));
+  while(wait_loop_index != 0)
+  {
+    wait_loop_index--;
+  }
+  LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_21);
+  LL_EXTI_EnableFallingTrig_0_31(LL_EXTI_LINE_21);
+  LL_EXTI_EnableRisingTrig_0_31(LL_EXTI_LINE_21);
+  LL_EXTI_DisableEvent_0_31(LL_EXTI_LINE_21);
+  LL_EXTI_EnableIT_0_31(LL_EXTI_LINE_21);
+  /* USER CODE BEGIN COMP2_Init 2 */
+
+  /* USER CODE END COMP2_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  Perform comparator activation procedure of the pair of comparators
+  *         for window mode (COMP instances: COMP1, COMP2).
+  * @note   Operations:
+  *         - Enable comparator instance master
+  *         - Enable comparator instance slave
+  *         - Wait for comparator startup time
+  *           (required to reach propagation delay specification)
+  * @param  None
+  * @retval None
+  */
+void Activate_COMP_master_slave(void)
+{
+  __IO uint32_t wait_loop_index = 0;
+  
+  /* Enable comparator instance master */
+  LL_COMP_Enable(COMP1);
+  
+  /* Enable comparator instance slave */
+  LL_COMP_Enable(COMP2);
+  
+  /* Delay for comparator startup time.                                       */
+  /* Compute number of CPU cycles to wait for, from delay in us.              */
+  /* Note: Variable divided by 2 to compensate partially                      */
+  /*       CPU processing cycles (depends on compilation optimization).       */
+  /* Note: If system core clock frequency is below 200kHz, wait time          */
+  /*       is only a few CPU processing cycles.                               */
+  wait_loop_index = ((LL_COMP_DELAY_STARTUP_US * (SystemCoreClock / (100000 * 2))) / 10);
+  while(wait_loop_index != 0)
+  {
+    wait_loop_index--;
+  }
+  
+}
+
+
+/**
+  * @brief  Turn-on LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_On(void)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Turn-off LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_Off(void)
+{
+  /* Turn LED2 off */
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT                                               */
+/******************************************************************************/
+
+/**
+  * @brief  Comparator interruption callback
+  *         This function is executed when the comparator threshold
+  *         is triggered.
+  * @retval None
+  */
+void ComparatorTrigger_Callback()
+{
+  __IO uint32_t COMP1OutputLevel = LL_COMP_ReadOutputLevel(COMP1);
+  __IO uint32_t COMP2OutputLevel = LL_COMP_ReadOutputLevel(COMP2);
+  
+  /* Set LED state in function of comparator output level */
+  /* Case of voltage above comparators thresholds window */
+  if (   (COMP1OutputLevel == LL_COMP_OUTPUT_LEVEL_LOW)
+      && (COMP2OutputLevel == LL_COMP_OUTPUT_LEVEL_LOW)
+     )
+  {
+    LED_Off();
+  }
+  /* Case of voltage below comparators thresholds window */
+  else if (   (COMP1OutputLevel == LL_COMP_OUTPUT_LEVEL_HIGH)
+           && (COMP2OutputLevel == LL_COMP_OUTPUT_LEVEL_HIGH)
+     )
+  {
+    LED_Off();
+  }
+  /* Case of voltage inside comparators thresholds window */
+  else /* COMP1 output high, COMP2 output low */
+  {
+    LED_On();
+  }
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..c417f1fb3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,233 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles COMP1 and COMP2 interrupts through EXTI lines 20 and 21.
+  */
+void COMP_IRQHandler(void)
+{
+  /* USER CODE BEGIN COMP_IRQn 0 */
+
+  /* Comparators are in window mode: manage flags of pair of comparators */
+  /* Check whether EXTI line 20 (from COMP1 output)                           */
+  /* or EXTI line 21 (from COMP2 output) caused the interruption.             */
+  if(   (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_20) != RESET)
+     || (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_21) != RESET))
+  {
+    /* Clear flag of EXTI */
+    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_20 | LL_EXTI_LINE_21);
+    
+    /* Call interruption treatment function */
+    ComparatorTrigger_Callback();
+  }
+  /* USER CODE END COMP_IRQn 0 */
+  
+  /* USER CODE BEGIN COMP_IRQn 1 */
+
+  /* USER CODE END COMP_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/readme.txt
new file mode 100644
index 000000000..9273b972a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/readme.txt
@@ -0,0 +1,96 @@
+/**
+  @page COMP_CompareGpioVsVrefInt_Window_IT_Init COMP example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the COMP_CompareGpioVsVrefInt_Window_IT_Init example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to use a pair of comparator peripherals to compare a voltage level applied on
+a GPIO pin to two thresholds: the internal voltage reference (VREFINT) and a fraction
+of the internal voltage reference (VREFINT/2), in interrupt mode. This example is
+based on the STM32WBxx COMP LL API. The peripheral initialization
+uses LL unitary service functions for optimization purposes (performance and size).
+
+Example configuration:
+Comparator instances COMP1 and COMP2 are configured to work together
+in window mode to compare 2 thresholds:
+ - COMP1 input plus set to a GPIO pin (cf pin below) in analog mode.
+   COMP2 input plus is not used (connected internally to the 
+   same input plus as COMP1).
+ - COMP1 input minus set to internal voltage reference VrefInt 
+   (voltage level 1.2V, refer to device datasheet for min/typ/max values)
+ - COMP2 input minus set to 1/2 of internal voltage reference VrefInt 
+   (voltage level 0.6V)
+Comparator interruption is enabled through EXTI lines 20 and 21
+with trigger edge set to both edges rising and falling.
+Comparators are set in power mode ultra low power.
+
+Example execution:
+From the main program execution, comparator is enabled.
+Each time the voltage level applied on GPIO pin (comparator input plus) 
+is crossing VrefInt or 1/2 VrefInt voltage thresholds (comparator input minus),
+the comparator with corresponding threshold generates an interruption.
+LED2 is turned on or off depending on the pair of comparators output state:
+turned on if comparator voltage level is inside the window (between VrefInt
+and 1/2 VrefInt: between 1.2V and 0.6V), turned off otherwise.
+
+Connection needed:
+A voltage must be supplied to the analog input pin (cf pin below),
+between Vdda=3.3V and 0V. Otherwise this pin can be let floating (but in this
+case COMP comparison level will be undetermined).
+
+To check comparator window thresholds, you must use an external power supply
+to set voltage level below, above or within comparator thresholds.
+
+Other peripheral used:
+  1 GPIO for LED2
+  1 GPIO for analog input of comparator: PA.01 (Arduino connector CN8 pin A2, Morpho connector CN7 pin 32)
+  EXTI line 20 (connected to COMP1 output)
+  EXTI line 21 (connected to COMP2 output)
+  
+@par Keywords
+
+Comparator, voltage, analog input, channel output, 1/2 VREFINT, COMP1, COMP2, Vdda, interrupt
+
+@par Directory contents 
+
+  - COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Inc/main.h                  Header for main.c module
+  - COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Inc/stm32_assert.h          Template file to include assert_failed function
+  - COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Src/main.c                  Main program
+  - COMP/COMP_CompareGpioVsVrefInt_Window_IT_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/CRC_CalculateAndCheck.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/CRC_CalculateAndCheck.ioc
new file mode 100644
index 000000000..58b8edd17
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/CRC_CalculateAndCheck.ioc
@@ -0,0 +1,121 @@
+#MicroXplorer Configuration settings - do not modify
+CRC.DefaultInitValueUse=DEFAULT_INIT_VALUE_ENABLE
+CRC.DefaultPolynomialUse=DEFAULT_POLYNOMIAL_ENABLE
+CRC.IPParameters=DefaultPolynomialUse,DefaultInitValueUse,InputDataInversionMode,OutputDataInversionMode,InputDataFormat
+CRC.InputDataFormat=CRC_INPUTDATA_FORMAT_BYTES
+CRC.InputDataInversionMode=CRC_INPUTDATA_INVERSION_NONE
+CRC.OutputDataInversionMode=CRC_OUTPUTDATA_INVERSION_DISABLE
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=CRC
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB0
+Mcu.Pin1=VP_CRC_VS_CRC
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=3
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=CRC_CalculateAndCheck.ioc
+ProjectManager.ProjectName=CRC_CalculateAndCheck
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-true,3-MX_CRC_Init-CRC-false-LL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_CRC_VS_CRC.Mode=CRC_Activate
+VP_CRC_VS_CRC.Signal=CRC_VS_CRC
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/CRC_CalculateAndCheck.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/CRC_CalculateAndCheck.ewd
new file mode 100644
index 000000000..d2a61b578
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/CRC_CalculateAndCheck.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		CRC_CalculateAndCheck
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/CRC_CalculateAndCheck.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/CRC_CalculateAndCheck.ewp
new file mode 100644
index 000000000..6f6d8c91c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/CRC_CalculateAndCheck.ewp
@@ -0,0 +1,1083 @@
+
+
+  3
+  
+    CRC_CalculateAndCheck
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/Project.eww
new file mode 100644
index 000000000..e6e76c8e7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\CRC_CalculateAndCheck.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Inc/main.h
new file mode 100644
index 000000000..0d447bf51
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Inc/main.h
@@ -0,0 +1,110 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/CRC/CRC_CalculateAndCheck/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_crc.h"
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "stm32wbxx_ll_crc.h"
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/**
+  * @brief Toggle periods for various blinking modes
+  */
+
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW  500
+#define LED_BLINK_ERROR 1000
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..7236aeb5d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/CRC/CRC_CalculateAndCheck/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/MDK-ARM/CRC_CalculateAndCheck.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/MDK-ARM/CRC_CalculateAndCheck.uvoptx
new file mode 100644
index 000000000..5c200a2cd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/MDK-ARM/CRC_CalculateAndCheck.uvoptx
@@ -0,0 +1,333 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    CRC_CalculateAndCheck
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/MDK-ARM/CRC_CalculateAndCheck.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/MDK-ARM/CRC_CalculateAndCheck.uvprojx
new file mode 100644
index 000000000..8e0ac969a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/MDK-ARM/CRC_CalculateAndCheck.uvprojx
@@ -0,0 +1,471 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      CRC_CalculateAndCheck
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          CRC_CalculateAndCheck\
+          CRC_CalculateAndCheck
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..49503cfb9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/.project
new file mode 100644
index 000000000..63ea761a3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/.project
@@ -0,0 +1,80 @@
+
+
+	CRC_CalculateAndCheck
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			CRC_CalculateAndCheck.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/CRC_CalculateAndCheck.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Src/main.c
new file mode 100644
index 000000000..a2288a72c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Src/main.c
@@ -0,0 +1,371 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/CRC/CRC_CalculateAndCheck/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to use CRC peripheral for generating CRC value
+  *          for an input data Buffer using the STM32WBxx CRC LL API.
+  *          Peripheral initialization done using LL unitary services functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define BUFFER_SIZE    39   /* 9 u32 + 1 u16 + 1 u8 */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* Used for storing CRC Value */
+__IO uint32_t uwCRCValue = 0;
+
+
+static const uint8_t aDataBuffer[BUFFER_SIZE] =
+{
+  0x21, 0x10, 0x00, 0x00, 0x63, 0x30, 0x42, 0x20, 0xa5, 0x50, 0x84, 0x40,
+  0xe7, 0x70, 0xc6, 0x60, 0x4a, 0xa1, 0x29, 0x91, 0x8c, 0xc1, 0x6b, 0xb1,
+  0xce, 0xe1, 0xad, 0xd1, 0x31, 0x12, 0xef, 0xf1, 0x52, 0x22, 0x73, 0x32,
+  0xa1, 0xb2, 0xc3
+};
+
+/* Expected CRC Value */
+uint32_t uwExpectedCRCValue = 0xA9866043;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_CRC_Init(void);
+/* USER CODE BEGIN PFP */
+uint32_t Calculate_CRC(uint32_t);
+void     CheckCRCResultValue(void);
+void     LED_On(void);
+void     LED_Blinking(uint32_t Period);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_CRC_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Perform CRC calculation on data contained in aDataBuffer */
+  uwCRCValue = Calculate_CRC(BUFFER_SIZE);
+
+  /* Check if CRC computed result value is equal to expected one */
+  CheckCRCResultValue();
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* MSI configuration and activation */
+  LL_RCC_MSI_Enable();
+  while(LL_RCC_MSI_IsReady() != 1)
+  {
+  };
+
+  /* Main PLL configuration and activation */
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 32, LL_RCC_PLLR_DIV_2);
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the main PLL */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(64000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(64000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief CRC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_CRC_Init(void)
+{
+
+  /* USER CODE BEGIN CRC_Init 0 */
+
+  /* USER CODE END CRC_Init 0 */
+
+  /* Peripheral clock enable */
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC);
+
+  /* USER CODE BEGIN CRC_Init 1 */
+
+  /* USER CODE END CRC_Init 1 */
+  LL_CRC_SetInputDataReverseMode(CRC, LL_CRC_INDATA_REVERSE_NONE);
+  LL_CRC_SetOutputDataReverseMode(CRC, LL_CRC_OUTDATA_REVERSE_NONE);
+  LL_CRC_SetPolynomialCoef(CRC, LL_CRC_DEFAULT_CRC32_POLY);
+  LL_CRC_SetPolynomialSize(CRC, LL_CRC_POLYLENGTH_32B);
+  LL_CRC_SetInitialData(CRC, LL_CRC_DEFAULT_CRC_INITVALUE);
+  /* USER CODE BEGIN CRC_Init 2 */
+
+  /* USER CODE END CRC_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  This function performs CRC calculation on BufferSize bytes from input data buffer aDataBuffer.
+  * @param  BufferSize Nb of bytes to be processed for CRC calculation
+  * @retval 32-bit CRC value computed on input data buffer
+  */
+uint32_t Calculate_CRC(uint32_t BufferSize)
+{
+  register uint32_t data = 0;
+  register uint32_t index = 0;
+
+  /* Compute the CRC of Data Buffer array*/
+  for (index = 0; index < (BufferSize / 4); index++)
+  {
+    data = (uint32_t)((aDataBuffer[4 * index + 3] << 24) | (aDataBuffer[4 * index + 2] << 16) | (aDataBuffer[4 * index + 1] << 8) | aDataBuffer[4 * index]);
+    LL_CRC_FeedData32(CRC, data);
+  }
+
+  /* Last bytes specific handling */
+  if ((BUFFER_SIZE % 4) != 0)
+  {
+    if (BUFFER_SIZE % 4 == 1)
+    {
+      LL_CRC_FeedData8(CRC, aDataBuffer[4 * index]);
+    }
+    if (BUFFER_SIZE % 4 == 2)
+    {
+      LL_CRC_FeedData16(CRC, (uint16_t)((aDataBuffer[4 * index + 1] << 8) | aDataBuffer[4 * index]));
+    }
+    if (BUFFER_SIZE % 4 == 3)
+    {
+      LL_CRC_FeedData16(CRC, (uint16_t)((aDataBuffer[4 * index + 1] << 8) | aDataBuffer[4 * index]));
+      LL_CRC_FeedData8(CRC, aDataBuffer[4 * index + 2]);
+    }
+  }
+
+  /* Return computed CRC value */
+  return (LL_CRC_ReadData32(CRC));
+}
+
+
+/**
+  * @brief  Check CRC computation result value.
+  * @param  None
+  * @retval None
+  */
+void CheckCRCResultValue(void)
+{
+  /* Compare the CRC value to the Expected one */
+  if (uwCRCValue != uwExpectedCRCValue)
+  {
+    /* Wrong CRC value: Set LED2 to Blinking mode (Error) */
+    LED_Blinking(LED_BLINK_ERROR);
+  }
+  else
+  {
+    /* Right CRC value: Turn LED2 on */
+    LED_On();
+  }
+}
+
+/**
+  * @brief  Turn-on LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_On(void)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
+  * @param  Period : Period of time (in ms) between each toggling of LED
+  *   This parameter can be user defined values. Pre-defined values used in that example are :
+  *     @arg LED_BLINK_FAST : Fast Blinking
+  *     @arg LED_BLINK_SLOW : Slow Blinking
+  *     @arg LED_BLINK_ERROR : Error specific Blinking
+  * @retval None
+  */
+void LED_Blinking(uint32_t Period)
+{
+  /* Toggle IO in an infinite loop */
+  while (1)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+    LL_mDelay(Period);
+  }
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..41c1bb1ea
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Src/stm32wbxx_it.c
@@ -0,0 +1,207 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/CRC/CRC_CalculateAndCheck/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/readme.txt
new file mode 100644
index 000000000..2202e5b4a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/CRC/CRC_CalculateAndCheck/readme.txt
@@ -0,0 +1,77 @@
+/**
+  @page CRC_CalculateAndCheck CRC : CRC calculation and computed CRC value checking
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/CRC/CRC_CalculateAndCheck/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the CRC_CalculateAndCheck example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to configure the CRC calculation unit to compute a CRC code for a given data
+buffer, based on a fixed generator polynomial (default value 0x4C11DB7). The
+peripheral initialization is done using LL unitary service functions for
+optimization purposes (performance and size).
+
+The CRC peripheral is configured to work with default polynomial value (32-bit long).
+Normal representation of this polynomial value is :
+ X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1.
+Generated CRC value is then 32 bits long.
+
+Example execution:
+After startup from reset and system configuration, CRC configuration is performed (use of default Polynomial and initialisation values).
+CRC code of a given data buffer is computed. 
+Data buffer length has been chosen as not an exact nb of u32 (32-bit words), in order to illustrate 
+use of offered API for feeding the calculator (u32, u16 or u8 inputs).
+The calculated CRC code is stored in uwCRCValue variable.
+Once calculated, CRC value (uwCRCValue) is compared to the CRC expected value (uwExpectedCRCValue),
+and if both are equal, LED2 is turned On. 
+In case of errors, LED2 is blinking (1sec period).
+
+
+
+@par Keywords
+
+Security, CRC, CRC Polynomial, IEC 60870-5, hardware CRC, user-defined, generating polynomial, CRC Calculate
+
+
+
+@par Directory contents 
+
+  - CRC/CRC_CalculateAndCheck/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - CRC/CRC_CalculateAndCheck/Inc/main.h                  Header for main.c module
+  - CRC/CRC_CalculateAndCheck/Inc/stm32_assert.h          Template file to include assert_failed function
+  - CRC/CRC_CalculateAndCheck/Src/stm32wbxx_it.c          Interrupt handlers
+  - CRC/CRC_CalculateAndCheck/Src/main.c                  Main program
+  - CRC/CRC_CalculateAndCheck/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
+ 
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/DMA_CopyFromFlashToMemory_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/DMA_CopyFromFlashToMemory_Init.ioc
new file mode 100644
index 000000000..194eca174
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/DMA_CopyFromFlashToMemory_Init.ioc
@@ -0,0 +1,132 @@
+#MicroXplorer Configuration settings - do not modify
+Dma.MEMTOMEM.0.Direction=DMA_MEMORY_TO_MEMORY
+Dma.MEMTOMEM.0.EventEnable=DISABLE
+Dma.MEMTOMEM.0.Instance=DMA1_Channel1
+Dma.MEMTOMEM.0.MemDataAlignment=DMA_MDATAALIGN_WORD
+Dma.MEMTOMEM.0.MemInc=DMA_MINC_ENABLE
+Dma.MEMTOMEM.0.Mode=DMA_NORMAL
+Dma.MEMTOMEM.0.PeriphDataAlignment=DMA_PDATAALIGN_WORD
+Dma.MEMTOMEM.0.PeriphInc=DMA_PINC_ENABLE
+Dma.MEMTOMEM.0.Polarity=HAL_DMAMUX_REQUEST_GEN_RISING
+Dma.MEMTOMEM.0.Priority=DMA_PRIORITY_HIGH
+Dma.MEMTOMEM.0.RequestNumber=1
+Dma.MEMTOMEM.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.MEMTOMEM.0.SignalID=NONE
+Dma.MEMTOMEM.0.SyncEnable=DISABLE
+Dma.MEMTOMEM.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.MEMTOMEM.0.SyncRequestNumber=1
+Dma.MEMTOMEM.0.SyncSignalID=NONE
+Dma.Request0=MEMTOMEM
+Dma.RequestsNb=1
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=DMA
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB0
+Mcu.Pin1=VP_SYS_VS_Systick
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=3
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=DMA_CopyFromFlashToMemory_Init.ioc
+ProjectManager.ProjectName=DMA_CopyFromFlashToMemory_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-MX_DMA_Init-DMA-false-LL-true,3-SystemClock_Config-RCC-false-LL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/DMA_CopyFromFlashToMemory_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/DMA_CopyFromFlashToMemory_Init.ewd
new file mode 100644
index 000000000..0d19a66c6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/DMA_CopyFromFlashToMemory_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		DMA_CopyFromFlashToMemory_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/DMA_CopyFromFlashToMemory_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/DMA_CopyFromFlashToMemory_Init.ewp
new file mode 100644
index 000000000..3f3cb43ae
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/DMA_CopyFromFlashToMemory_Init.ewp
@@ -0,0 +1,1086 @@
+
+
+  3
+  
+    DMA_CopyFromFlashToMemory_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/Project.eww
new file mode 100644
index 000000000..e345eb8a4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\DMA_CopyFromFlashToMemory_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Inc/main.h
new file mode 100644
index 000000000..6eda44124
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Inc/main.h
@@ -0,0 +1,102 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/DMA/DMA_CopyFromFlashToMemory/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* IRQ Handler treatment.*/
+void TransferComplete(void);
+void TransferError(void);
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..47f44e2dd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void DMA1_Channel1_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/MDK-ARM/DMA_CopyFromFlashToMemory_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/MDK-ARM/DMA_CopyFromFlashToMemory_Init.uvoptx
new file mode 100644
index 000000000..cb21b5940
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/MDK-ARM/DMA_CopyFromFlashToMemory_Init.uvoptx
@@ -0,0 +1,345 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    DMA_CopyFromFlashToMemory_Init
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      stm32wbxx_ll_dma.c
+      0
+      0
+    
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/MDK-ARM/DMA_CopyFromFlashToMemory_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/MDK-ARM/DMA_CopyFromFlashToMemory_Init.uvprojx
new file mode 100644
index 000000000..8f6ed33a0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/MDK-ARM/DMA_CopyFromFlashToMemory_Init.uvprojx
@@ -0,0 +1,476 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      DMA_CopyFromFlashToMemory_Init
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          DMA_CopyFromFlashToMemory_Init\
+          DMA_CopyFromFlashToMemory_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..40b9ab2fd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..1ff0357cd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/.project
@@ -0,0 +1,85 @@
+
+
+	DMA_CopyFromFlashToMemory_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			DMA_CopyFromFlashToMemory_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/DMA_CopyFromFlashToMemory_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Src/main.c
new file mode 100644
index 000000000..a2fb26582
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Src/main.c
@@ -0,0 +1,403 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to use a DMA channel to transfer
+  *          a word data buffer from FLASH memory to embedded SRAM memory
+  *          through the STM32WBxx DMA LL API.
+  *          Peripheral initialization done using LL initialization function.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW 500
+#define LED_BLINK_ERROR 1000
+
+#define BUFFER_SIZE 32
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+static const uint32_t aSRC_Const_Buffer[BUFFER_SIZE] =
+{
+  0x01020304, 0x05060708, 0x090A0B0C, 0x0D0E0F10,
+  0x11121314, 0x15161718, 0x191A1B1C, 0x1D1E1F20,
+  0x21222324, 0x25262728, 0x292A2B2C, 0x2D2E2F30,
+  0x31323334, 0x35363738, 0x393A3B3C, 0x3D3E3F40,
+  0x41424344, 0x45464748, 0x494A4B4C, 0x4D4E4F50,
+  0x51525354, 0x55565758, 0x595A5B5C, 0x5D5E5F60,
+  0x61626364, 0x65666768, 0x696A6B6C, 0x6D6E6F70,
+  0x71727374, 0x75767778, 0x797A7B7C, 0x7D7E7F80
+};
+
+static uint32_t aDST_Buffer[BUFFER_SIZE];
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+/* USER CODE BEGIN PFP */
+
+uint8_t Buffercmp(uint32_t* pBuffer1, uint32_t* pBuffer2, uint32_t BufferLength);
+void LED_On(void);
+void LED_Blinking(uint32_t Period);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Set DMA transfer addresses of source and destination */
+  LL_DMA_ConfigAddresses(DMA1,
+                         LL_DMA_CHANNEL_1,
+                         (uint32_t)&aSRC_Const_Buffer,
+                         (uint32_t)&aDST_Buffer,
+                         LL_DMA_DIRECTION_MEMORY_TO_MEMORY);
+
+  /* Set DMA transfer size */
+  LL_DMA_SetDataLength(DMA1,
+                       LL_DMA_CHANNEL_1,
+                       BUFFER_SIZE);
+
+  /* Enable DMA transfer complete/error interrupts */
+  LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_1);
+  LL_DMA_EnableIT_TE(DMA1, LL_DMA_CHANNEL_1);
+
+  /* Start the DMA transfer Flash to Memory */
+  LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* MSI configuration and activation */
+  LL_RCC_MSI_Enable();
+  while(LL_RCC_MSI_IsReady() != 1)
+  {
+  };
+
+  /* Main PLL configuration and activation */
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 32, LL_RCC_PLLR_DIV_2);
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the main PLL */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(64000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(64000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* Init with LL driver */
+  /* DMA controller clock enable */
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1);
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
+
+  /* Configure DMA request MEMTOMEM_DMA1_Channel1 */
+
+  /* Set request number */
+  LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_MEM2MEM);
+
+  /* Set transfer direction */
+  LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_1, LL_DMA_DIRECTION_MEMORY_TO_MEMORY);
+
+  /* Set priority level */
+  LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PRIORITY_HIGH);
+
+  /* Set DMA mode */
+  LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MODE_NORMAL);
+
+  /* Set peripheral increment mode */
+  LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PERIPH_INCREMENT);
+
+  /* Set memory increment mode */
+  LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MEMORY_INCREMENT);
+
+  /* Set peripheral data width */
+  LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PDATAALIGN_WORD);
+
+  /* Set memory data width */
+  LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MDATAALIGN_WORD);
+
+  /* DMA interrupt init */
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  NVIC_SetPriority(DMA1_Channel1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  Compares two buffers.
+  * @param  pBuffer1, pBuffer2: buffers to be compared.
+  * @param  BufferLength: buffer's length
+  * @retval 0: pBuffer identical to pBuffer1
+  *         1: pBuffer differs from pBuffer1
+  */
+uint8_t Buffercmp(uint32_t* pBuffer1, uint32_t* pBuffer2, uint32_t BufferLength)
+{
+  while (BufferLength--)
+  {
+    if (*pBuffer1 != *pBuffer2)
+    {
+      return 1;
+    }
+
+    pBuffer1++;
+    pBuffer2++;
+  }
+
+  return 0;
+}
+
+/**
+  * @brief  Turn-on LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_On(void)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
+  * @param  Period : Period of time (in ms) between each toggling of LED
+  *   This parameter can be user defined values. Pre-defined values used in that example are :
+  *     @arg LED_BLINK_FAST : Fast Blinking
+  *     @arg LED_BLINK_SLOW : Slow Blinking
+  *     @arg LED_BLINK_ERROR : Error specific Blinking
+  * @retval None
+  */
+void LED_Blinking(uint32_t Period)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+  
+  /* Toggle IO in an infinite loop */
+  while (1)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);  
+    LL_mDelay(Period);
+  }
+}
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT                                               */
+/******************************************************************************/
+/**
+  * @brief  DMA transfer complete callback
+  * @note   This function is executed when the transfer complete interrupt
+  *         is generated
+  * @retval None
+  */
+void TransferComplete()
+{
+  /* DMA transfer completed */
+  /* Verify the data transfered */
+  if (Buffercmp((uint32_t*)aSRC_Const_Buffer, (uint32_t*)aDST_Buffer, BUFFER_SIZE) == 1)
+  {
+    /* DMA data transfered not consistency */
+    LED_Blinking(LED_BLINK_ERROR);
+  }
+  
+  /* DMA data transfered consistency */
+  LED_On();
+}
+
+/**
+  * @brief  DMA transfer error callback
+  * @note   This function is executed when the transfer error interrupt
+  *         is generated during DMA transfer
+  * @retval None
+  */
+void TransferError()
+{
+  /* Error detected during DMA transfer */
+  LED_Blinking(LED_BLINK_ERROR);
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..aa36d0117
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,229 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles DMA1 channel1 global interrupt.
+  */
+void DMA1_Channel1_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
+  if(LL_DMA_IsActiveFlag_TC1(DMA1) == 1)
+  {
+    LL_DMA_ClearFlag_GI1(DMA1);
+    TransferComplete();
+  }
+  else if(LL_DMA_IsActiveFlag_TE1(DMA1) == 1)
+  {
+    TransferError();
+  }
+  /* USER CODE END DMA1_Channel1_IRQn 0 */
+  
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel1_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/readme.txt
new file mode 100644
index 000000000..3d836ee19
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/readme.txt
@@ -0,0 +1,74 @@
+/**
+  @page DMA_CopyFromFlashToMemory_Init DMA example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/DMA/DMA_CopyFromFlashToMemory_Init/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the DMA example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to use a DMA channel to transfer a word data buffer
+from Flash memory to embedded SRAM. The peripheral initialization uses LL
+initialization functions to demonstrate LL init usage.
+
+At the beginning of the main program the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz.
+
+Then the LED_Init() function is used to initialize the LED2.
+
+Then the Configure_DMA() function is used to configure the DMA1_Channel1 to transfer the contents of a 32-word data
+buffer stored in Flash memory to the reception buffer declared in RAM.
+
+The start of transfer is triggered by software(LL_DMA_EnableChannel()). DMA1_Channel1 memory-to-memory
+transfer is enabled. Source and destination addresses incrementing is also enabled.
+The transfer is started by setting the channel enable bit for DMA1_Channel1.
+At the end of the transfer a Transfer Complete interrupt is generated since it
+is enabled and the callback function (customized by user) is called.
+
+Finally, aSRC_Const_Buffer and aDST_Buffer are compared through Buffercmp() in order to 
+check buffers correctness.  
+
+NUCLEO-WB35CE's LED2 can be used to monitor the transfer status:
+- LED2 is turned ON if the DMA data transfer is successfully completed.
+- LED2 is blinking every 1 sec in case of error.
+
+
+@par Directory contents 
+
+  - DMA/DMA_CopyFromFlashToMemory_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - DMA/DMA_CopyFromFlashToMemory_Init/Inc/main.h                  Header for main.c module  
+  - DMA/DMA_CopyFromFlashToMemory_Init/Inc/stm32_assert.h          Template file to include assert_failed function
+  - DMA/DMA_CopyFromFlashToMemory_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - DMA/DMA_CopyFromFlashToMemory_Init/Src/main.c                  Main program
+  - DMA/DMA_CopyFromFlashToMemory_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/EXTI_ToggleLedOnIT_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/EXTI_ToggleLedOnIT_Init.ewd
new file mode 100644
index 000000000..1835701d6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/EXTI_ToggleLedOnIT_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		EXTI_ToggleLedOnIT_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/EXTI_ToggleLedOnIT_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/EXTI_ToggleLedOnIT_Init.ewp
new file mode 100644
index 000000000..87654ed30
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/EXTI_ToggleLedOnIT_Init.ewp
@@ -0,0 +1,1083 @@
+
+
+  3
+  
+    EXTI_ToggleLedOnIT_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/Project.eww
new file mode 100644
index 000000000..53f43f2d3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\EXTI_ToggleLedOnIT_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EXTI_ToggleLedOnIT_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EXTI_ToggleLedOnIT_Init.ioc
new file mode 100644
index 000000000..d05007b9f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/EXTI_ToggleLedOnIT_Init.ioc
@@ -0,0 +1,120 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA0
+Mcu.Pin1=PB0
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.EXTI0_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA0.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultEXTI
+PA0.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
+PA0.GPIO_PuPd=GPIO_PULLUP
+PA0.Locked=true
+PA0.Signal=GPXTI0
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=EXTI_ToggleLedOnIT_Init.ioc
+ProjectManager.ProjectName=EXTI_ToggleLedOnIT_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SH.GPXTI0.0=GPIO_EXTI0
+SH.GPXTI0.ConfNb=1
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Inc/main.h
new file mode 100644
index 000000000..9e658a512
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Inc/main.h
@@ -0,0 +1,101 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* IRQ Handler treatment UserKey_Callback*/
+void UserButton_Callback(void);
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..a6c9736c5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void EXTI0_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/MDK-ARM/EXTI_ToggleLedOnIT_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/MDK-ARM/EXTI_ToggleLedOnIT_Init.uvoptx
new file mode 100644
index 000000000..734e1ee97
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/MDK-ARM/EXTI_ToggleLedOnIT_Init.uvoptx
@@ -0,0 +1,333 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    EXTI_ToggleLedOnIT_Init
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/MDK-ARM/EXTI_ToggleLedOnIT_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/MDK-ARM/EXTI_ToggleLedOnIT_Init.uvprojx
new file mode 100644
index 000000000..890aa28fe
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/MDK-ARM/EXTI_ToggleLedOnIT_Init.uvprojx
@@ -0,0 +1,471 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      EXTI_ToggleLedOnIT_Init
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          EXTI_ToggleLedOnIT_Init\
+          EXTI_ToggleLedOnIT_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..6ebb54e8c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..124da6bd8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/.project
@@ -0,0 +1,80 @@
+
+
+	EXTI_ToggleLedOnIT_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			EXTI_ToggleLedOnIT_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/EXTI_ToggleLedOnIT_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Src/main.c
new file mode 100644
index 000000000..b81946121
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Src/main.c
@@ -0,0 +1,257 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to configure the EXTI and use 
+  *          GPIOs using the STM32WBxx LL API to toggles the available 
+  *          users Leds on the board when User button is pressed.
+  *          Peripheral initialization done using LL initialization function.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+/* USER CODE BEGIN PFP */
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* MSI configuration and activation */
+  LL_RCC_MSI_Enable();
+  while(LL_RCC_MSI_IsReady() != 1)
+  {
+  };
+
+  /* Main PLL configuration and activation */
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 32, LL_RCC_PLLR_DIV_2);
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the main PLL */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(64000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(64000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_EXTI_InitTypeDef EXTI_InitStruct = {0};
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTA, LL_SYSCFG_EXTI_LINE0);
+
+  /**/
+  EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_0;
+  EXTI_InitStruct.Line_32_63 = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct.LineCommand = ENABLE;
+  EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;
+  EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_FALLING;
+  LL_EXTI_Init(&EXTI_InitStruct);
+
+  /**/
+  LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_0, LL_GPIO_PULL_UP);
+
+  /**/
+  LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_0, LL_GPIO_MODE_INPUT);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+  /* EXTI interrupt init*/
+  NVIC_SetPriority(EXTI0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(EXTI0_IRQn);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT                                               */
+/******************************************************************************/
+/**
+  * @brief  Function to manage IRQ Handler
+  * @param  None
+  * @retval None
+  */
+void UserButton_Callback(void)
+{
+  LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);  
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..e3cd4dbcf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,229 @@
+/* USER CODE BEGIN Header */
+/** 
+  ******************************************************************************
+  * @file    Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles EXTI line0 interrupt.
+  */
+void EXTI0_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI0_IRQn 0 */
+
+  /* USER CODE END EXTI0_IRQn 0 */
+  if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
+  {
+    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
+    /* USER CODE BEGIN LL_EXTI_LINE_0 */
+
+    /* Manage code in main.c */
+    UserButton_Callback();
+    /* USER CODE END LL_EXTI_LINE_0 */
+  }
+  /* USER CODE BEGIN EXTI0_IRQn 1 */
+
+  /* USER CODE END EXTI0_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/readme.txt
new file mode 100644
index 000000000..637d36f1b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/readme.txt
@@ -0,0 +1,70 @@
+/**
+  @page EXTI_ToggleLedOnIT_Init EXTI example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/EXTI/EXTI_ToggleLedOnIT_Init/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the EXTI example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+This example describes how to configure the EXTI and use
+GPIOs to toggle the user LEDs available on the board when
+a user button is pressed. This example is based on the
+STM32WBxx LL API. Peripheral initialization is done using LL
+initialization function to demonstrate LL init usage.
+
+In this example, one EXTI line (External line 0) is configured to generate
+an interrupt on each falling edge.
+
+In the interrupt routine a led connected to a specific GPIO pin is toggled.
+
+In this example:
+    - External line 0 is connected to PA.00 pin
+      - when falling edge is detected on External line 0 by pressing User push-button (SW1), LED2 toggles
+
+On NUCLEO-WB35CE:
+    - External line 0 is connected to User push-button (SW1)
+
+@par Keywords
+
+System, GPIO, Output, Alternate function, EXTI, Toggle
+
+
+@par Directory contents 
+
+  - EXTI/EXTI_ToggleLedOnIT_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - EXTI/EXTI_ToggleLedOnIT_Init/Inc/main.h                  Header for main.c module
+  - EXTI/EXTI_ToggleLedOnIT_Init/Inc/stm32_assert.h          Template file to include assert_failed function
+  - EXTI/EXTI_ToggleLedOnIT_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - EXTI/EXTI_ToggleLedOnIT_Init/Src/main.c                  Main program
+  - EXTI/EXTI_ToggleLedOnIT_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/GPIO_InfiniteLedToggling_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/GPIO_InfiniteLedToggling_Init.ewd
new file mode 100644
index 000000000..337f324b7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/GPIO_InfiniteLedToggling_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		GPIO_InfiniteLedToggling_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/GPIO_InfiniteLedToggling_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/GPIO_InfiniteLedToggling_Init.ewp
new file mode 100644
index 000000000..eee5a5da3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/GPIO_InfiniteLedToggling_Init.ewp
@@ -0,0 +1,1083 @@
+
+
+  3
+  
+    GPIO_InfiniteLedToggling_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/Project.eww
new file mode 100644
index 000000000..84a1260b8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\GPIO_InfiniteLedToggling_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/GPIO_InfiniteLedToggling_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/GPIO_InfiniteLedToggling_Init.ioc
new file mode 100644
index 000000000..f617fa54a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/GPIO_InfiniteLedToggling_Init.ioc
@@ -0,0 +1,111 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB0
+Mcu.Pin1=VP_SYS_VS_Systick
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=3
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=GPIO_InfiniteLedToggling_Init.ioc
+ProjectManager.ProjectName=GPIO_InfiniteLedToggling_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Inc/main.h
new file mode 100644
index 000000000..5aa29b35d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Inc/main.h
@@ -0,0 +1,102 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..ebbedc6fa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/MDK-ARM/GPIO_InfiniteLedToggling_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/MDK-ARM/GPIO_InfiniteLedToggling_Init.uvoptx
new file mode 100644
index 000000000..74572e890
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/MDK-ARM/GPIO_InfiniteLedToggling_Init.uvoptx
@@ -0,0 +1,333 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    GPIO_InfiniteLedToggling_Init
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/MDK-ARM/GPIO_InfiniteLedToggling_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/MDK-ARM/GPIO_InfiniteLedToggling_Init.uvprojx
new file mode 100644
index 000000000..abdd10341
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/MDK-ARM/GPIO_InfiniteLedToggling_Init.uvprojx
@@ -0,0 +1,471 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      GPIO_InfiniteLedToggling_Init
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          GPIO_InfiniteLedToggling_Init\
+          GPIO_InfiniteLedToggling_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..00a20c618
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..5d1ce1a2c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/.project
@@ -0,0 +1,80 @@
+
+
+	GPIO_InfiniteLedToggling_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			GPIO_InfiniteLedToggling_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/GPIO_InfiniteLedToggling_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Src/main.c
new file mode 100644
index 000000000..b5cf74bda
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Src/main.c
@@ -0,0 +1,232 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to configure and use GPIOs through
+  *          the STM32WBxx  GPIO LL API.
+  *          Peripheral initialization done using LL initialization function.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  /* USER CODE BEGIN 2 */
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+    
+    /* Insert delay 250 ms */
+    LL_mDelay(250);
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* MSI configuration and activation */
+  LL_RCC_MSI_Enable();
+  while(LL_RCC_MSI_IsReady() != 1)
+  {
+  };
+
+  /* Main PLL configuration and activation */
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 32, LL_RCC_PLLR_DIV_2);
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the main PLL */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(64000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(64000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..bb8dbf89a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,207 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/readme.txt
new file mode 100644
index 000000000..d9bab2f09
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/readme.txt
@@ -0,0 +1,59 @@
+/**
+  @page GPIO_InfiniteLedToggling_Init GPIO example
+  
+  @verbatim
+  ******************** (C) COPYRIGHT 2016 STMicroelectronics *******************
+  * @file    Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the GPIO example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to configure and use GPIOs to toggle the on-board user LEDs 
+every 250 ms. This example is based on the STM32WBxx LL API. The peripheral 
+is initialized with LL initialization function to demonstrate LL init usage.
+
+PB.00 IO (configured in output pushpull mode) toggles in a forever loop.
+On NUCLEO-WB35CE board this IO is connected to LED2.
+
+In this example, HCLK is configured at 64 MHz.
+
+
+@par Directory contents 
+
+  - GPIO/GPIO_InfiniteLedToggling_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - GPIO/GPIO_InfiniteLedToggling_Init/Inc/main.h                  Header for main.c module
+  - GPIO/GPIO_InfiniteLedToggling_Init/Inc/stm32_assert.h          Template file to include assert_failed function
+  - GPIO/GPIO_InfiniteLedToggling_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - GPIO/GPIO_InfiniteLedToggling_Init/Src/main.c                  Main program
+  - GPIO/GPIO_InfiniteLedToggling_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/HSEM_DualProcess_IT.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/HSEM_DualProcess_IT.ewd
new file mode 100644
index 000000000..006474b05
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/HSEM_DualProcess_IT.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		HSEM_DualProcess_IT
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/HSEM_DualProcess_IT.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/HSEM_DualProcess_IT.ewp
new file mode 100644
index 000000000..237751f21
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/HSEM_DualProcess_IT.ewp
@@ -0,0 +1,1083 @@
+
+
+  3
+  
+    HSEM_DualProcess_IT
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/Project.eww
new file mode 100644
index 000000000..5e99dad75
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\HSEM_DualProcess_IT.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/stm32wb35xx_sram_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/stm32wb35xx_sram_cm4.icf
new file mode 100644
index 000000000..6426355fb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/EWARM/stm32wb35xx_sram_cm4.icf
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20003FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20004000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20008000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x2000FFFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/HSEM_DualProcess_IT.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/HSEM_DualProcess_IT.ioc
new file mode 100644
index 000000000..01289d2a2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/HSEM_DualProcess_IT.ioc
@@ -0,0 +1,109 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB0
+Mcu.Pin1=VP_SYS_VS_Systick
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=3
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=HSEM_DualProcess_IT.ioc
+ProjectManager.ProjectName=HSEM_DualProcess_IT
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-true
+RCC.AHBFreq_Value=16000000
+RCC.APB1Freq_Value=16000000
+RCC.APB1TimFreq_Value=16000000
+RCC.APB2Freq_Value=16000000
+RCC.APB2TimFreq_Value=16000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=16000000
+RCC.CortexFreq_Value=16000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=16000000
+RCC.FCLKCortexFreq_Value=16000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=16000000
+RCC.HCLK3Freq_Value=16000000
+RCC.HCLKFreq_Value=16000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=16000000
+RCC.I2C3Freq_Value=16000000
+RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=16000000
+RCC.LPTIM2Freq_Value=16000000
+RCC.LPUART1Freq_Value=16000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=16000000
+RCC.PLLPoutputFreq_Value=16000000
+RCC.PLLQoutputFreq_Value=16000000
+RCC.PLLRCLKFreq_Value=16000000
+RCC.PWRFreq_Value=16000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=16000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_HSI
+RCC.USART1Freq_Value=16000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=32000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Inc/main.h
new file mode 100644
index 000000000..e05036a38
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Inc/main.h
@@ -0,0 +1,116 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/HSEM/HSEM_DualProcess_IT/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+#include "stm32wbxx_ll_hsem.h"
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* Toggle periods for various blinking modes */
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW  500
+#define LED_BLINK_ERROR 1000
+
+/* Process identifier */
+#define PROCESS_A 0xA
+#define PROCESS_B 0xB
+
+/* Semaphore identifier */
+#define SEMAPHORE_ID 0x2
+#define SEMAPHORE_MSK LL_HSEM_SEMAPHORE_2
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..4b02e6c4f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Inc/stm32wbxx_it.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/HSEM/HSEM_DualProcess_IT/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+void HSEM_IRQHandler(void);
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/MDK-ARM/HSEM_DualProcess_IT.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/MDK-ARM/HSEM_DualProcess_IT.uvoptx
new file mode 100644
index 000000000..fe4789cc8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/MDK-ARM/HSEM_DualProcess_IT.uvoptx
@@ -0,0 +1,333 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    HSEM_DualProcess_IT
+    0x4
+    ARM-ADS
+    
+      16000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/MDK-ARM/HSEM_DualProcess_IT.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/MDK-ARM/HSEM_DualProcess_IT.uvprojx
new file mode 100644
index 000000000..0164889f0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/MDK-ARM/HSEM_DualProcess_IT.uvprojx
@@ -0,0 +1,471 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      HSEM_DualProcess_IT
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          HSEM_DualProcess_IT\
+          HSEM_DualProcess_IT
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..8e45cf41b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/.project
new file mode 100644
index 000000000..4175a87ff
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/.project
@@ -0,0 +1,80 @@
+
+
+	HSEM_DualProcess_IT
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			HSEM_DualProcess_IT.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/HSEM_DualProcess_IT.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Src/main.c
new file mode 100644
index 000000000..56c2fdb48
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Src/main.c
@@ -0,0 +1,302 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/HSEM/HSEM_DualProcess_IT/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to use HSEM peripheral to lock and unlock
+  *          hardware semaphore in the context of two process accessing the same 
+  *          semaphore using the STM32WBxx HSEM LL API.
+  *          Peripheral initialization done using LL unitary services functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+/* USER CODE BEGIN PFP */
+
+void     Configure_HSEM(void);
+void     LED_Init(void);
+void     LED_On(void);
+void     LED_Blinking(uint32_t Period);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  uint32_t lockStatus = 0;
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  /* USER CODE BEGIN 2 */
+  
+  /* Configure HSEM */
+  Configure_HSEM();
+
+  /* Enable the interrupt for SEMAPHORE_ID */
+  LL_HSEM_EnableIT_C1IER(HSEM, SEMAPHORE_MSK);
+  
+  /* PROCESS_A takes the semaphore with success */
+  lockStatus = LL_HSEM_2StepLock(HSEM, SEMAPHORE_ID, PROCESS_A);
+  if(lockStatus != 0)
+  {
+    LED_Blinking(LED_BLINK_ERROR);
+  }
+  
+  /* PROCESS_A releases the semaphore with success */
+  LL_HSEM_ReleaseLock(HSEM, SEMAPHORE_ID, PROCESS_A);
+  
+  /* While PROCESS_B is not locking the semaphore */
+  /* (The lock mechanism is done inside the interrupt) */
+  while(LL_HSEM_GetProcessId(HSEM, SEMAPHORE_ID) != PROCESS_B);
+  
+  /* Disable the interrupt for SEMAPHORE_ID */
+  LL_HSEM_DisableIT_C1IER(HSEM, SEMAPHORE_MSK);
+  
+  /* PROCESS_B releases the semaphore with success */
+  LL_HSEM_ReleaseLock(HSEM, SEMAPHORE_ID, PROCESS_B);
+  
+  LED_On();
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  /* HSI configuration and activation */
+  LL_RCC_HSI_Enable();
+  while(LL_RCC_HSI_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the HSI */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(16000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(16000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  This function configures HSEM Instance.
+  * @note   This function is used to :
+  *         - Enable peripheral clock for HSEM.
+  * @param  None
+  * @retval None
+  */
+void Configure_HSEM(void)
+{
+  /* Enable peripheral clock for RNG */
+  LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM);
+  
+  /* Configure NVIC for HSEM interrupts */
+  /*   Set priority for RNG_IRQn */
+  /*   Enable RNG_IRQn */
+  NVIC_SetPriority(HSEM_IRQn, 0);  
+  NVIC_EnableIRQ(HSEM_IRQn);  
+}
+
+/**
+  * @brief  Turn-on LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_On(void)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
+  * @param  Period : Period of time (in ms) between each toggling of LED
+  *   This parameter can be user defined values. Pre-defined values used in that example are :
+  *     @arg LED_BLINK_FAST : Fast Blinking
+  *     @arg LED_BLINK_SLOW : Slow Blinking
+  *     @arg LED_BLINK_ERROR : Error specific Blinking
+  * @retval None
+  */
+void LED_Blinking(uint32_t Period)
+{
+  /* Toggle LED2 in an infinite loop */
+  while (1)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);  
+    LL_mDelay(Period);
+  }
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..c2668df71
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Src/stm32wbxx_it.c
@@ -0,0 +1,221 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/HSEM/HSEM_DualProcess_IT/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/**
+  * Brief   This function handles RNG Instance interrupt request.
+  * Param   None
+  * Retval  None
+  */
+void HSEM_IRQHandler(void)
+{
+  /* Clear flag */
+  LL_HSEM_ClearFlag_C1ICR(HSEM, SEMAPHORE_MSK);
+  
+  /* PROCESS_B takes the semaphore with success */
+  LL_HSEM_2StepLock(HSEM, SEMAPHORE_ID, PROCESS_B);
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/readme.txt
new file mode 100644
index 000000000..8fa7d48f8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/HSEM/HSEM_DualProcess_IT/readme.txt
@@ -0,0 +1,81 @@
+/**
+  @page HSEM_DualProcess_IT HSEM : Hardware semaphore
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/HSEM/HSEM_DualProcess_IT/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the HSEM_DualProcess_IT example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to use the low-layer HSEM API to initialize, lock, and unlock hardware 
+semaphore in the context of two processes accessing the same resource.
+
+Example execution:
+After startup from reset and system configuration, HSEM configuration is performed.
+
+Two processes are used to demonstrate the features:
+  PROCESS_A with an identifier of 0xA (This can be changed at will).
+  PROCESS_B with an identifier of 0xB (This can be changed at will).
+
+The hardware semaphore used is 0x2 (This can be changed at will).
+
+PROCESS_A takes the semaphore with interrupt enable.
+PROCESS_A releases the semaphore with success.
+This trigs the HSEM interrupt where PROCESS_B takes the semaphore.
+PROCESS_B releases the semaphore with success.
+
+After successful sequence, LED2 is turned On. 
+In case of errors, LED2 is slowly blinking (1sec period).
+
+Additionnaly, this example demonstrate how to:
+  Retreive the current process locking a semaphore.
+  Retreive the current core locking a semaphore.
+
+Remarks:
+  As this example uses two processes to demonstrate the lock/unlock mechanism, it is not
+  possible to use the function LL_HSEM_1StepLock which does not use process identifier. Those
+  identifier are set to 0. This function is only interesting in the context of multicore where
+  the core identifers are used to determine the owner of the semaphore.
+
+@par Keywords
+
+Hardware semaphore, Semaphore, HSEM, Lock, Unlock, Take, Release, Process
+
+@par Directory contents 
+
+  - HSEM/HSEM_DualProcess_IT/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - HSEM/HSEM_DualProcess_IT/Inc/main.h                  Header for main.c module
+  - HSEM/HSEM_DualProcess_IT/Inc/stm32_assert.h          Template file to include assert_failed function
+  - HSEM/HSEM_DualProcess_IT/Src/stm32wbxx_it.c          Interrupt handlers
+  - HSEM/HSEM_DualProcess_IT/Src/main.c                  Main program
+  - HSEM/HSEM_DualProcess_IT/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example and observe the LED status
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ewd
new file mode 100644
index 000000000..748ad4de9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		I2C_TwoBoards_MasterRx_SlaveTx_IT_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ewp
new file mode 100644
index 000000000..7bb8eb6ad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ewp
@@ -0,0 +1,1089 @@
+
+
+  3
+  
+    I2C_TwoBoards_MasterRx_SlaveTx_IT_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_i2c.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/Project.eww
new file mode 100644
index 000000000..db05e047c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ioc
new file mode 100644
index 000000000..9b7ecf352
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ioc
@@ -0,0 +1,137 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+I2C1.I2C_Coeff_DF=2
+I2C1.I2C_Fall_Time=10
+I2C1.I2C_Rise_Time=100
+I2C1.I2C_Speed_Mode=I2C_Fast
+I2C1.IPParameters=I2C_Speed_Mode,Timing,I2C_Rise_Time,I2C_Fall_Time,I2C_Coeff_DF,OwnAddress
+I2C1.OwnAddress=0x5A
+I2C1.Timing=0x00300516
+KeepUserPlacement=false
+Mcu.Family=STM32WB
+Mcu.IP0=I2C1
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB8
+Mcu.Pin1=PB9
+Mcu.Pin2=PA0
+Mcu.Pin3=PB0
+Mcu.Pin4=VP_SYS_VS_Systick
+Mcu.PinsNb=5
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.EXTI0_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA0.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
+PA0.GPIO_Label=USER_BUTTON
+PA0.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
+PA0.GPIO_PuPd=GPIO_PULLUP
+PA0.Locked=true
+PA0.Signal=GPXTI0
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PB8.GPIOParameters=GPIO_Speed
+PB8.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PB8.Mode=I2C
+PB8.Signal=I2C1_SCL
+PB9.GPIOParameters=GPIO_Speed
+PB9.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PB9.Mode=I2C
+PB9.Signal=I2C1_SDA
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ioc
+ProjectManager.ProjectName=I2C_TwoBoards_MasterRx_SlaveTx_IT_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false,3-MX_I2C1_Init-I2C1-false-LL-true
+RCC.AHBFreq_Value=16000000
+RCC.APB1Freq_Value=16000000
+RCC.APB1TimFreq_Value=16000000
+RCC.APB2Freq_Value=16000000
+RCC.APB2TimFreq_Value=16000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=16000000
+RCC.CortexFreq_Value=16000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=16000000
+RCC.FCLKCortexFreq_Value=16000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=16000000
+RCC.HCLK3Freq_Value=16000000
+RCC.HCLKFreq_Value=16000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=16000000
+RCC.I2C3Freq_Value=16000000
+RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=16000000
+RCC.LPTIM2Freq_Value=16000000
+RCC.LPUART1Freq_Value=16000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=16000000
+RCC.PLLPoutputFreq_Value=16000000
+RCC.PLLQoutputFreq_Value=16000000
+RCC.PLLRCLKFreq_Value=16000000
+RCC.PWRFreq_Value=16000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=16000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_HSI
+RCC.USART1Freq_Value=16000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=32000000
+SH.GPXTI0.0=GPIO_EXTI0
+SH.GPXTI0.ConfNb=1
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Inc/main.h
new file mode 100644
index 000000000..180dfb2b5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Inc/main.h
@@ -0,0 +1,130 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx.h"
+#include "stm32wbxx_ll_i2c.h"
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+/**
+  * @brief Toggle periods for various blinking modes
+  */
+
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW  500
+#define LED_BLINK_ERROR 1000
+
+/**
+  * @brief Slave settings
+  */
+#define SLAVE_OWN_ADDRESS                       180 /* This value is a left shift of a real 7 bits of a slave address
+                                                        value which can find in a Datasheet as example: b0101101
+                                                        mean in uint8_t equivalent at 0x2D and this value can be
+                                                        seen in the OAR1 register in bits OA1[1:7] */
+
+/* Uncomment this line to use the board as slave, if not it is used as master */
+#define SLAVE_BOARD
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+/* IRQ Handler treatment functions */
+#ifdef SLAVE_BOARD
+void Slave_Ready_To_Transmit_Callback(void);
+void Slave_Complete_Callback(void);
+#else /* MASTER_BOARD */
+void Master_Reception_Callback(void);
+void Master_Complete_Callback(void);
+void UserButton_Callback(void);
+#endif /* SLAVE_BOARD */
+void Error_Callback(void);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define USER_BUTTON_Pin LL_GPIO_PIN_0
+#define USER_BUTTON_GPIO_Port GPIOA
+#define USER_BUTTON_EXTI_IRQn EXTI0_IRQn
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..56acdb0fd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,77 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void EXTI0_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+#ifdef SLAVE_BOARD
+void I2C1_EV_IRQHandler(void);
+void I2C1_ER_IRQHandler(void);
+#else
+void I2C1_EV_IRQHandler(void);
+void I2C1_ER_IRQHandler(void);
+#endif /* SLAVE_BOARD */
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/MDK-ARM/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/MDK-ARM/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.uvoptx
new file mode 100644
index 000000000..0e876de0b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/MDK-ARM/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.uvoptx
@@ -0,0 +1,377 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    I2C_TwoBoards_MasterRx_SlaveTx_IT_Init
+    0x4
+    ARM-ADS
+    
+      16000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          ARMRTXEVENTFLAGS
+          -L70 -Z18 -C0 -M0 -T1
+        
+        
+          0
+          DLGTARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          
+        
+        
+          0
+          DLGUARM
+          (105=-1,-1,-1,-1,0)
+        
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        1
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      4
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      4
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_i2c.c
+      stm32wbxx_ll_i2c.c
+      0
+      0
+    
+    
+      4
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      stm32wbxx_ll_dma.c
+      0
+      0
+    
+    
+      4
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/MDK-ARM/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/MDK-ARM/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.uvprojx
new file mode 100644
index 000000000..9c7132d26
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/MDK-ARM/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.uvprojx
@@ -0,0 +1,482 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      I2C_TwoBoards_MasterRx_SlaveTx_IT_Init
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          I2C_TwoBoards_MasterRx_SlaveTx_IT_Init\
+          I2C_TwoBoards_MasterRx_SlaveTx_IT_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x40000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000004
+                0x8000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            1
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_i2c.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_i2c.c
+            
+            
+              stm32wbxx_ll_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..130839bd0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x0001E000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20008000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..c31c94691
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..21a2cf7e1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/.project
@@ -0,0 +1,90 @@
+
+
+	I2C_TwoBoards_MasterRx_SlaveTx_IT_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_i2c.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_i2c.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..eea98ff9c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb35xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB35xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..4ec95844d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,159 @@
+/**
+ ******************************************************************************
+ * @file      syscalls.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..4665417ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,58 @@
+/**
+ ******************************************************************************
+ * @file      sysmem.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System Memory calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..349b5224d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 256K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20008000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Src/main.c
new file mode 100644
index 000000000..8e466ea1e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Src/main.c
@@ -0,0 +1,560 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to send/receive bytes over I2C IP using
+  *          the STM32WBxx I2C LL API.
+  *          Peripheral initialization done using LL unitary services functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/**
+  * @brief I2C devices settings
+  */
+/* Timing register value is computed with the STM32CubeMX Tool,
+  * Fast Mode @400kHz with I2CCLK = 16 MHz,
+  * rise time = 100ns, fall time = 10ns
+  * Timing Value = (uint32_t)0x00300512
+  */
+#define I2C_TIMING               0x00300512
+
+/**
+  * @brief Define related to SlaveTransmit process
+  */
+#define SLAVE_BYTE_TO_SEND       (uint8_t)0xA5
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+#ifndef SLAVE_BOARD
+/**
+  * @brief Variables related to MasterReceive process
+  */
+uint8_t      aReceiveBuffer[0xF] = {0};
+__IO uint8_t ubReceiveIndex      = 0;
+__IO uint8_t ubButtonPress       = 0;
+#endif /* SLAVE_BOARD */
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_I2C1_Init(void);
+/* USER CODE BEGIN PFP */
+#ifndef SLAVE_BOARD
+#endif /* MASTER_BOARD */
+void     LED_On(void);
+void     LED_Off(void);
+void     LED_Blinking(uint32_t Period);
+#ifdef SLAVE_BOARD
+#else /* MASTER_BOARD */
+void     WaitForUserButtonPress(void);
+void     Handle_I2C_Master(void);
+#endif /* SLAVE_BOARD */
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_I2C1_Init();
+  /* USER CODE BEGIN 2 */
+#ifdef SLAVE_BOARD
+#else
+#endif /* SLAVE_BOARD */
+
+  /* Set LED2 Off */
+  LED_Off();
+
+#ifdef SLAVE_BOARD
+#else /* MASTER_BOARD */
+  /* Wait for User push-button (SW1) press to start transfer */
+  WaitForUserButtonPress();
+
+  /* Handle I2C1 events (Master) */
+  Handle_I2C_Master();
+#endif /* SLAVE_BOARD */
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  /* HSI configuration and activation */
+  LL_RCC_HSI_Enable();
+  while(LL_RCC_HSI_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the HSI */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(16000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(16000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief I2C1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_I2C1_Init(void)
+{
+
+  /* USER CODE BEGIN I2C1_Init 0 */
+
+  /* USER CODE END I2C1_Init 0 */
+
+  LL_I2C_InitTypeDef I2C_InitStruct = {0};
+
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+  /**I2C1 GPIO Configuration  
+  PB8   ------> I2C1_SCL
+  PB9   ------> I2C1_SDA 
+  */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_8|LL_GPIO_PIN_9;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_4;
+  LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* Peripheral clock enable */
+  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1);
+
+  /* USER CODE BEGIN I2C1_Init 1 */
+  /* Configure Event IT:
+   *  - Set priority for I2C1_EV_IRQn
+   *  - Enable I2C1_EV_IRQn
+   */
+  NVIC_SetPriority(I2C1_EV_IRQn, 0);
+  NVIC_EnableIRQ(I2C1_EV_IRQn);
+
+  /* Configure Error IT:
+   *  - Set priority for I2C1_ER_IRQn
+   *  - Enable I2C1_ER_IRQn
+   */
+  NVIC_SetPriority(I2C1_ER_IRQn, 0);
+  NVIC_EnableIRQ(I2C1_ER_IRQn);
+  /* USER CODE END I2C1_Init 1 */
+  /** I2C Initialization 
+  */
+  I2C_InitStruct.PeripheralMode = LL_I2C_MODE_I2C;
+  I2C_InitStruct.Timing = 0x00300516;
+  I2C_InitStruct.AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE;
+  I2C_InitStruct.DigitalFilter = 2;
+  I2C_InitStruct.OwnAddress1 = 180;
+  I2C_InitStruct.TypeAcknowledge = LL_I2C_ACK;
+  I2C_InitStruct.OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
+  LL_I2C_Init(I2C1, &I2C_InitStruct);
+  LL_I2C_EnableAutoEndMode(I2C1);
+  LL_I2C_SetOwnAddress2(I2C1, 0, LL_I2C_OWNADDRESS2_NOMASK);
+  LL_I2C_DisableOwnAddress2(I2C1);
+  LL_I2C_DisableGeneralCall(I2C1);
+  LL_I2C_EnableClockStretching(I2C1);
+  /* USER CODE BEGIN I2C1_Init 2 */
+#ifdef SLAVE_BOARD
+  uint32_t timing = 0;
+  timing = __LL_I2C_CONVERT_TIMINGS(0x0, 0xC, 0x0, 0x21, 0x6C);
+  LL_I2C_SetTiming(I2C1, timing);
+
+  LL_I2C_SetOwnAddress1(I2C1, SLAVE_OWN_ADDRESS, LL_I2C_OWNADDRESS1_7BIT);
+  LL_I2C_EnableOwnAddress1(I2C1);
+
+
+  LL_I2C_EnableIT_ADDR(I2C1);
+#else
+  LL_I2C_SetTiming(I2C1, I2C_TIMING);
+
+
+  LL_I2C_EnableIT_RX(I2C1);
+#endif
+  LL_I2C_EnableIT_NACK(I2C1);
+  LL_I2C_EnableIT_ERR(I2C1);
+  LL_I2C_EnableIT_STOP(I2C1);
+  /* USER CODE END I2C1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_EXTI_InitTypeDef EXTI_InitStruct = {0};
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTA, LL_SYSCFG_EXTI_LINE0);
+
+  /**/
+  EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_0;
+  EXTI_InitStruct.Line_32_63 = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct.LineCommand = ENABLE;
+  EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;
+  EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_FALLING;
+  LL_EXTI_Init(&EXTI_InitStruct);
+
+  /**/
+  LL_GPIO_SetPinPull(USER_BUTTON_GPIO_Port, USER_BUTTON_Pin, LL_GPIO_PULL_UP);
+
+  /**/
+  LL_GPIO_SetPinMode(USER_BUTTON_GPIO_Port, USER_BUTTON_Pin, LL_GPIO_MODE_INPUT);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+  /* EXTI interrupt init*/
+  NVIC_SetPriority(EXTI0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(EXTI0_IRQn);
+
+}
+
+/* USER CODE BEGIN 4 */
+#ifndef SLAVE_BOARD
+#endif /* MASTER_BOARD */
+
+#ifdef SLAVE_BOARD
+
+#endif /* SLAVE_BOARD */
+
+/**
+  * @brief  Turn-on LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_On(void)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Turn-off LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_Off(void)
+{
+  /* Turn LED2 off */
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
+  * @param  Period : Period of time (in ms) between each toggling of LED
+  *   This parameter can be user defined values. Pre-defined values used in that example are :
+  *     @arg LED_BLINK_FAST : Fast Blinking
+  *     @arg LED_BLINK_SLOW : Slow Blinking
+  *     @arg LED_BLINK_ERROR : Error specific Blinking
+  * @retval None
+  */
+void LED_Blinking(uint32_t Period)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /* Toggle IO in an infinite loop */
+  while (1)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+    LL_mDelay(Period);
+  }
+}
+/******************************************************************************/
+/*   IRQ HANDLER TREATMENT Functions                                          */
+/******************************************************************************/
+#ifdef SLAVE_BOARD
+/**
+  * @brief  Function called from I2C IRQ Handler when TXIS flag is set
+  *         Function is in charge of transmit a byte on I2C lines.
+  * @param  None
+  * @retval None
+  */
+void Slave_Ready_To_Transmit_Callback(void)
+{
+  /* Send the Byte requested by the Master */
+  LL_I2C_TransmitData8(I2C1, SLAVE_BYTE_TO_SEND);
+}
+
+/**
+  * @brief  Function called from I2C IRQ Handler when STOP flag is set
+  *         LED2 is On if data are correct.
+  * @param  None
+  * @retval None
+  */
+void Slave_Complete_Callback(void)
+{
+  /* Turn LED2 On:
+   *  - Expected bytes have been sent
+   *  - Slave Tx sequence completed successfully
+   */
+  LED_On();
+}
+#else /* MASTER_BOARD */
+/**
+  * @brief  Wait for User push-button (SW1) press to start transfer.
+  * @param  None
+  * @retval None
+  */
+/*  */
+void WaitForUserButtonPress(void)
+{
+  while (ubButtonPress == 0)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+    LL_mDelay(LED_BLINK_FAST);
+  }
+  /* Turn LED2 off */
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Function to manage User push-button (SW1)
+  * @param  None
+  * @retval None
+  */
+void UserButton_Callback(void)
+{
+  /* Update User push-button (SW1) variable : to be checked in waiting loop in main program */
+  ubButtonPress = 1;
+}
+
+/**
+  * @brief  This Function handle Master events to perform a reception process
+  * @note  This function is composed in one step :
+  *        -1- Initiate a Start condition to the Slave device.
+  * @param  None
+  * @retval None
+  */
+void Handle_I2C_Master(void)
+{
+  /* (1) Initiate a Start condition to the Slave device ***********************/
+
+  /* Master Generate Start condition for a read request:
+   *  - to the Slave with a 7-Bit SLAVE_OWN_ADDRESS
+   *  - with a auto stop condition generation when receive 1 byte
+   */
+  LL_I2C_HandleTransfer(I2C1, SLAVE_OWN_ADDRESS, LL_I2C_ADDRSLAVE_7BIT, 1, LL_I2C_MODE_AUTOEND, LL_I2C_GENERATE_START_READ);
+}
+
+/**
+  * @brief  Function called from I2C IRQ Handler when RXNE flag is set
+  *         Function is in charge of reading byte received on I2C lines.
+  * @param  None
+  * @retval None
+  */
+void Master_Reception_Callback(void)
+{
+  /* Read character in Receive Data register.
+  RXNE flag is cleared by reading data in RXDR register */
+  aReceiveBuffer[ubReceiveIndex++] = LL_I2C_ReceiveData8(I2C1);
+}
+
+/**
+  * @brief  Function called from I2C IRQ Handler when STOP flag is set
+  *         Function is in charge of checking data received,
+  *         LED2 is On if data are correct.
+  * @param  None
+  * @retval None
+  */
+void Master_Complete_Callback(void)
+{
+  /* Read Received character.
+  RXNE flag is cleared by reading of RXDR register */
+  if (aReceiveBuffer[ubReceiveIndex - 1] == SLAVE_BYTE_TO_SEND)
+  {
+    /* Turn LED2 On:
+     *  - Expected byte has been received
+     *  - Master Rx sequence completed successfully
+     */
+    LED_On();
+  }
+  else
+  {
+    /* Call Error function */
+    Error_Callback();
+  }
+}
+#endif /* SLAVE_BOARD */
+
+/**
+  * @brief  Function called in case of error detected in I2C IT Handler
+  * @param  None
+  * @retval None
+  */
+void Error_Callback(void)
+{
+#ifdef SLAVE_BOARD
+  /* Disable I2C1_EV_IRQn */
+  NVIC_DisableIRQ(I2C1_EV_IRQn);
+#else
+  /* Disable I2C1_EV_IRQn */
+  NVIC_DisableIRQ(I2C1_EV_IRQn);
+#endif /* SLAVE_BOARD */
+
+  /* Disable I2C1_ER_IRQn */
+#ifdef SLAVE_BOARD
+  NVIC_DisableIRQ(I2C1_ER_IRQn);
+#else
+  /* Disable I2C1_ER_IRQn */
+  NVIC_DisableIRQ(I2C1_ER_IRQn);
+#endif /* SLAVE_BOARD */
+
+  /* Unexpected event : Set LED2 to Blinking mode to indicate error occurs */
+  LED_Blinking(LED_BLINK_ERROR);
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..1704e8f25
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,367 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles EXTI line0 interrupt.
+  */
+void EXTI0_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI0_IRQn 0 */
+
+  /* USER CODE END EXTI0_IRQn 0 */
+  if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
+  {
+    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
+    /* USER CODE BEGIN LL_EXTI_LINE_0 */
+#ifdef SLAVE_BOARD
+#else
+    UserButton_Callback();
+#endif
+    /* USER CODE END LL_EXTI_LINE_0 */
+  }
+  /* USER CODE BEGIN EXTI0_IRQn 1 */
+
+  /* USER CODE END EXTI0_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+#ifdef SLAVE_BOARD
+/**
+  * Brief   This function handles I2C1 (Slave) event interrupt request.
+  * Param   None
+  * Retval  None
+  */
+void I2C1_EV_IRQHandler(void)
+{
+  /* Check ADDR flag value in ISR register */
+if (LL_I2C_IsActiveFlag_ADDR(I2C1))
+{
+  /* Verify the Address Match with the OWN Slave address */
+  if (LL_I2C_GetAddressMatchCode(I2C1) == SLAVE_OWN_ADDRESS)
+  {
+    /* Verify the transfer direction, a read direction, Slave enters transmitter mode */
+    if (LL_I2C_GetTransferDirection(I2C1) == LL_I2C_DIRECTION_READ)
+    {
+      /* Clear ADDR flag value in ISR register */
+      LL_I2C_ClearFlag_ADDR(I2C1);
+
+      /* Enable Transmit Interrupt */
+      LL_I2C_EnableIT_TX(I2C1);
+    }
+    else
+    {
+      /* Clear ADDR flag value in ISR register */
+      LL_I2C_ClearFlag_ADDR(I2C1);
+
+      /* Call Error function */
+      Error_Callback();
+    }
+  }
+  else
+  {
+    /* Clear ADDR flag value in ISR register */
+    LL_I2C_ClearFlag_ADDR(I2C1);
+
+    /* Call Error function */
+    Error_Callback();
+  }
+}
+/* Check NACK flag value in ISR register */
+else if (LL_I2C_IsActiveFlag_NACK(I2C1))
+{
+  /* End of Transfer */
+  LL_I2C_ClearFlag_NACK(I2C1);
+}
+/* Check TXIS flag value in ISR register */
+else if (LL_I2C_IsActiveFlag_TXIS(I2C1))
+{
+  /* Call function Slave Ready to Transmit Callback */
+  Slave_Ready_To_Transmit_Callback();
+}
+/* Check STOP flag value in ISR register */
+else if (LL_I2C_IsActiveFlag_STOP(I2C1))
+{
+  /* Clear STOP flag value in ISR register */
+  LL_I2C_ClearFlag_STOP(I2C1);
+
+  /* Check TXE flag value in ISR register */
+  if (!LL_I2C_IsActiveFlag_TXE(I2C1))
+  {
+    /* Flush the TXDR register */
+    LL_I2C_ClearFlag_TXE(I2C1);
+  }
+
+  /* Call function Slave Complete Callback */
+  Slave_Complete_Callback();
+}
+/* Check TXE flag value in ISR register */
+else if (!LL_I2C_IsActiveFlag_TXE(I2C1))
+{
+  /* Do nothing */
+  /* This Flag will be set by hardware when the TXDR register is empty */
+  /* If needed, use LL_I2C_ClearFlag_TXE() interface to flush the TXDR register  */
+}
+else
+{
+  /* Call Error function */
+  Error_Callback();
+}
+}
+
+/**
+  * Brief   This function handles I2C1 (Slave) error interrupt request.
+  * Param   None
+  * Retval  None
+  */
+void I2C1_ER_IRQHandler(void)
+{
+  /* Call Error function */
+  Error_Callback();
+}
+
+#else /* MASTER_BOARD */
+
+/**
+  * Brief   This function handles I2C1 (Master) interrupt request.
+  * Param   None
+  * Retval  None
+  */
+void I2C1_EV_IRQHandler(void)
+{
+  /* Check RXNE flag value in ISR register */
+if (LL_I2C_IsActiveFlag_RXNE(I2C1))
+{
+  /* Call function Master Reception Callback */
+  Master_Reception_Callback();
+}
+/* Check STOP flag value in ISR register */
+else if (LL_I2C_IsActiveFlag_STOP(I2C1))
+{
+  /* End of Transfer */
+  LL_I2C_ClearFlag_STOP(I2C1);
+
+  /* Call function Master Complete Callback */
+  Master_Complete_Callback();
+}
+else
+{
+  /* Call Error function */
+  Error_Callback();
+}
+}
+
+/**
+  * Brief   This function handles I2C1 (Master) error interrupt request.
+  * Param   None
+  * Retval  None
+  */
+void I2C1_ER_IRQHandler(void)
+{
+  /* Call Error function */
+  Error_Callback();
+}
+
+
+#endif /* SLAVE_BOARD */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..4cb9e0e42
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx) || defined(STM32WB5Mxx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/readme.txt
new file mode 100644
index 000000000..5827261af
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/readme.txt
@@ -0,0 +1,129 @@
+/**
+  @page I2C_TwoBoards_MasterRx_SlaveTx_IT_Init I2C example (IT Mode)
+
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the I2C_TwoBoards_MasterRx_SlaveTx_IT_Init I2C example (IT Mode).
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to handle the reception of one data byte from an I2C slave device
+by an I2C master device. Both devices operate in interrupt mode. The peripheral
+is initialized with LL unitary service functions to optimize for performance
+and size.
+
+This example guides you through the different configuration steps by mean of LL API
+to configure GPIO and I2C peripherals using two NUCLEO-WB35CE.
+
+Boards: NUCLEO-WB35CE (embeds a STM32WB35CE device)
+SCL Pin: PB.8 (CN10, pin 3)
+SDA Pin: PB.9 (CN10, pin 5)
+
+   ______BOARD SLAVE_____                       _____BOARD MASTER_____
+  |        ______________|                     |______________        |
+  |       |I2C1          |                     |          I2C1|       |
+  |       |              |                     |              |       |
+  |       |          SCL |_____________________| SCL          |       |
+  |       |              |                     |              |       |
+  |       |              |                     |              |       |
+  |       |          SDA |_____________________| SDA          |       |
+  |       |______________|                     |______________|       |
+  |         __           |                     |             __       |
+  |        |__|          |                     |            |__|      |
+  |        USER       GND|_____________________|GND         USER      |
+  |___NUCLEO-WB35CE___|                     |___NUCLEO-WB35CE___|
+
+The project is splitted in two parts the Master Board and the Slave Board
+- Master Board
+  I2C1 Peripheral is configured in Master mode with EXTI (Fast Mode @400kHz).
+  And GPIO associated to User push-button (SW1) is linked with EXTI.
+- Slave Board
+  I2C1 Peripheral is configured in Slave mode with EXTI (Fast Mode @400kHz, Own address 7-bit enabled).
+
+The user can choose between Master and Slave through "#define SLAVE_BOARD"
+in the "main.h" file:
+- Comment "#define SLAVE_BOARD" to select Master board.
+- Uncomment "#define SLAVE_BOARD" to select Slave board.
+
+The user can disable internal pull-up by opening ioc file.
+For that, user can follow the procedure :
+1- Double click on the I2C_TwoBoards_MasterRx_SlaveTx_IT_Init.ioc file
+2- When CUBEMX tool is opened, select System Core category
+3- Then in the configuration of GPIO/I2C1, change Pull-up to No pull-up and no pull-down for the both pins
+4- Last step, generate new code thanks to button "GENERATE CODE"
+The example is updated with no pull on each pin used for I2C communication
+
+LED2 blinks quickly on BOARD MASTER to wait for User push-button (SW1) press.
+
+Example execution:
+Press the User push-button (SW1) on BOARD MASTER to initiate a read request by Master.
+This action will generate an I2C start condition with the Slave address and a read bit condition.
+When address Slave match code is received on I2C1 of BOARD SLAVE, an ADDR interrupt occurs.
+I2C1 Slave IRQ Handler routine is then checking Address Match Code and direction Read.
+This will allow Slave to enter in transmitter mode and then send a byte when TXIS interrupt occurs.
+When byte is received on I2C1 of BOARD MASTER, an RXNE interrupt occurs.
+When RXDR register is read, Master auto-generate a NACK and STOP condition
+to inform the Slave that the transfer is finished.
+The NACK condition generate a NACK interrupt in Slave side treated in the I2C1 Slave IRQ handler routine by a clear of NACK flag.
+The STOP condition generate a STOP interrupt in both side (Slave and Master). Both I2C1 IRQ handler routine are then
+clearing the STOP flag in both side.
+
+LED2 is On :
+- Slave side if transfer sequence is completed.
+- Master side if data is well received.
+
+In case of errors, LED2 is blinking slowly (1s).
+
+
+@par Directory contents
+
+  - I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Inc/main.h                  Header for main.c module
+  - I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Inc/stm32_assert.h          Template file to include assert_failed function
+  - I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Src/main.c                  Main program
+  - I2C/I2C_TwoBoards_MasterRx_SlaveTx_IT_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+
+  - This example has been tested with STM32WB35CEUx board and can be
+    easily tailored to any other supported device and development board.
+
+  - NUCLEO-WB35CE Set-up
+    - Connect GPIOs connected to Board Slave I2C1 SCL/SDA (PB.8 and PB.9)
+    to respectively Board Master SCL and SDA pins of I2C1 (PB.8 and PB.9).
+      - I2C1_SCL  PB.8 (CN10, pin 3) : connected to I2C1_SCL PB.8 (CN10, pin 3)
+      - I2C1_SDA  PB.9 (CN10, pin 5) : connected to I2C1_SDA PB.9 (CN10, pin 5)
+    - Connect Master board GND to Slave Board GND
+
+  - Launch the program.
+  - Press User push-button (SW1) to initiate a read request by Master
+      then Slave send a byte.
+
+@par How to use it ?
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory (The user can choose between Master
+   and Slave target through "#define SLAVE_BOARD" in the "main.h" file)
+    o Comment "#define SLAVE_BOARD" and load the project in Master Board
+    o Uncomment "#define SLAVE_BOARD" and load the project in Slave Board
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ewd
new file mode 100644
index 000000000..43f991b3b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ewp
new file mode 100644
index 000000000..6b39f52d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ewp
@@ -0,0 +1,1089 @@
+
+
+  3
+  
+    I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_i2c.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/Project.eww
new file mode 100644
index 000000000..5e87802d0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ioc
new file mode 100644
index 000000000..7b536d181
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ioc
@@ -0,0 +1,174 @@
+#MicroXplorer Configuration settings - do not modify
+Dma.I2C1_RX.0.Direction=DMA_PERIPH_TO_MEMORY
+Dma.I2C1_RX.0.EventEnable=DISABLE
+Dma.I2C1_RX.0.Instance=DMA1_Channel3
+Dma.I2C1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.I2C1_RX.0.MemInc=DMA_MINC_ENABLE
+Dma.I2C1_RX.0.Mode=DMA_NORMAL
+Dma.I2C1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.I2C1_RX.0.PeriphInc=DMA_PINC_DISABLE
+Dma.I2C1_RX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.I2C1_RX.0.Priority=DMA_PRIORITY_HIGH
+Dma.I2C1_RX.0.RequestNumber=1
+Dma.I2C1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.I2C1_RX.0.SignalID=HAL_DMAMUX1_REQ_GEN_EXTI4
+Dma.I2C1_RX.0.SyncEnable=DISABLE
+Dma.I2C1_RX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.I2C1_RX.0.SyncRequestNumber=1
+Dma.I2C1_RX.0.SyncSignalID=HAL_DMAMUX1_SYNC_EXTI4
+Dma.I2C1_TX.1.Direction=DMA_MEMORY_TO_PERIPH
+Dma.I2C1_TX.1.EventEnable=DISABLE
+Dma.I2C1_TX.1.Instance=DMA1_Channel2
+Dma.I2C1_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.I2C1_TX.1.MemInc=DMA_MINC_ENABLE
+Dma.I2C1_TX.1.Mode=DMA_NORMAL
+Dma.I2C1_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.I2C1_TX.1.PeriphInc=DMA_PINC_DISABLE
+Dma.I2C1_TX.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.I2C1_TX.1.Priority=DMA_PRIORITY_HIGH
+Dma.I2C1_TX.1.RequestNumber=1
+Dma.I2C1_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.I2C1_TX.1.SignalID=HAL_DMAMUX1_REQ_GEN_EXTI4
+Dma.I2C1_TX.1.SyncEnable=DISABLE
+Dma.I2C1_TX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.I2C1_TX.1.SyncRequestNumber=1
+Dma.I2C1_TX.1.SyncSignalID=HAL_DMAMUX1_SYNC_EXTI4
+Dma.Request0=I2C1_RX
+Dma.Request1=I2C1_TX
+Dma.RequestsNb=2
+File.Version=6
+GPIO.groupedBy=
+I2C1.AddressingMode=I2C_ADDRESSINGMODE_7BIT
+I2C1.Analog_Filter=I2C_ANALOGFILTER_ENABLE
+I2C1.CustomTiming=Disabled
+I2C1.DualAddressMode=I2C_DUALADDRESS_DISABLE
+I2C1.GeneralCallMode=I2C_GENERALCALL_DISABLE
+I2C1.I2C_Coeff_DF=2
+I2C1.I2C_Fall_Time=10
+I2C1.I2C_Rise_Time=100
+I2C1.I2C_Speed_Mode=I2C_Fast
+I2C1.IPParameters=CustomTiming,I2C_Speed_Mode,Speed,I2C_Rise_Time,I2C_Fall_Time,I2C_Coeff_DF,Analog_Filter,NoStretchMode,GeneralCallMode,AddressingMode,DualAddressMode,OwnAddress,Timing
+I2C1.NoStretchMode=I2C_NOSTRETCH_DISABLE
+I2C1.OwnAddress=0x5a
+I2C1.Speed=400
+I2C1.Timing=0x00300516
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=DMA
+Mcu.IP1=I2C1
+Mcu.IP2=NVIC
+Mcu.IP3=RCC
+Mcu.IP4=SYS
+Mcu.IPNb=5
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB8
+Mcu.Pin1=PB9
+Mcu.Pin2=PB0
+Mcu.Pin3=VP_SYS_VS_Systick
+Mcu.PinsNb=4
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DMA1_Channel2_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.DMA1_Channel3_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PB8.GPIOParameters=GPIO_Speed
+PB8.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PB8.Mode=I2C
+PB8.Signal=I2C1_SCL
+PB9.GPIOParameters=GPIO_Speed
+PB9.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PB9.Mode=I2C
+PB9.Signal=I2C1_SDA
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=false
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ioc
+ProjectManager.ProjectName=I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-MX_DMA_Init-DMA-false-LL-true,3-SystemClock_Config-RCC-false-LL-false,4-MX_I2C1_Init-I2C1-false-LL-true
+RCC.AHBFreq_Value=16000000
+RCC.APB1Freq_Value=16000000
+RCC.APB1TimFreq_Value=16000000
+RCC.APB2Freq_Value=16000000
+RCC.APB2TimFreq_Value=16000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=16000000
+RCC.CortexFreq_Value=16000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=16000000
+RCC.FCLKCortexFreq_Value=16000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=16000000
+RCC.HCLK3Freq_Value=16000000
+RCC.HCLKFreq_Value=16000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=16000000
+RCC.I2C3Freq_Value=16000000
+RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=16000000
+RCC.LPTIM2Freq_Value=16000000
+RCC.LPUART1Freq_Value=16000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=16000000
+RCC.PLLPoutputFreq_Value=16000000
+RCC.PLLQoutputFreq_Value=16000000
+RCC.PLLRCLKFreq_Value=16000000
+RCC.PWRFreq_Value=16000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=16000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_HSI
+RCC.USART1Freq_Value=16000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=32000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Inc/main.h
new file mode 100644
index 000000000..5d03590c8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Inc/main.h
@@ -0,0 +1,143 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx.h"
+#include "stm32wbxx_ll_i2c.h"
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+/* Define used to enable time-out management*/
+#define USE_TIMEOUT       0
+/**
+  * @brief Toggle periods for various blinking modes
+  */
+
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW  500
+#define LED_BLINK_ERROR 1000
+/**
+  * @brief Key push-button
+  */
+#define USER_BUTTON_PIN                         LL_GPIO_PIN_0
+#define USER_BUTTON_GPIO_PORT                   GPIOA
+#define USER_BUTTON_GPIO_CLK_ENABLE()           LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA)
+#define USER_BUTTON_EXTI_LINE                   LL_EXTI_LINE_0
+#define USER_BUTTON_EXTI_IRQn                   EXTI0_IRQn
+#define USER_BUTTON_EXTI_LINE_ENABLE()          LL_EXTI_EnableIT_0_31(USER_BUTTON_EXTI_LINE)
+#define USER_BUTTON_EXTI_FALLING_TRIG_ENABLE()  LL_EXTI_EnableFallingTrig_0_31(USER_BUTTON_EXTI_LINE)
+#define USER_BUTTON_SYSCFG_SET_EXTI()           do {                                                                     \
+                                                  LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTA, LL_SYSCFG_EXTI_LINE0);  \
+                                                } while(0)
+#define USER_BUTTON_IRQHANDLER                  EXTI0_IRQHandler
+
+/**
+  * @brief Slave settings
+  */
+#define SLAVE_OWN_ADDRESS                       180 /* This value is a left shift of a real 7 bits of a slave address
+                                                        value which can find in a Datasheet as example: b0101101
+                                                        mean in uint8_t equivalent at 0x2D and this value can be
+                                                        seen in the OAR1 register in bits OA1[1:7] */
+
+/* Uncomment this line to use the board as slave, if not it is used as master */
+//#define SLAVE_BOARD
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+/* IRQ Handler treatment functions */
+#ifdef SLAVE_BOARD
+void DMA1_Transfer_Complete_Callback(void);
+void DMA1_Transfer_Error_Callback(void);
+#else /* MASTER_BOARD */
+void UserButton_Callback(void);
+void DMA1_Transfer_Complete_Callback(void);
+void DMA1_Transfer_Error_Callback(void);
+#endif /* SLAVE_BOARD */
+void Error_Callback(void);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..f14ebb110
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,80 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "main.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void DMA1_Channel2_IRQHandler(void);
+void DMA1_Channel3_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+#ifdef SLAVE_BOARD
+void DMA1_Channel3_IRQHandler(void);
+
+#else /* MASTER_BOARD */
+
+void USER_BUTTON_IRQHANDLER(void);
+void DMA1_Channel2_IRQHandler(void);
+#endif /* SLAVE_BOARD */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/MDK-ARM/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/MDK-ARM/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.uvoptx
new file mode 100644
index 000000000..3fc98818c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/MDK-ARM/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.uvoptx
@@ -0,0 +1,377 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init
+    0x4
+    ARM-ADS
+    
+      16000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          ARMRTXEVENTFLAGS
+          -L70 -Z18 -C0 -M0 -T1
+        
+        
+          0
+          DLGTARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          
+        
+        
+          0
+          DLGUARM
+          (105=-1,-1,-1,-1,0)
+        
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066CFF303337554E43183920 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        1
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      stm32wbxx_ll_dma.c
+      0
+      0
+    
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_i2c.c
+      stm32wbxx_ll_i2c.c
+      0
+      0
+    
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/MDK-ARM/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/MDK-ARM/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.uvprojx
new file mode 100644
index 000000000..afa002e55
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/MDK-ARM/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.uvprojx
@@ -0,0 +1,482 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init\
+          I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+            
+            
+              stm32wbxx_ll_i2c.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_i2c.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..640a03c5c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..d477a926b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/.project
@@ -0,0 +1,90 @@
+
+
+	I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_i2c.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_i2c.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Src/main.c
new file mode 100644
index 000000000..3d85ab5dc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Src/main.c
@@ -0,0 +1,808 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to send/receive bytes over I2C IP using
+  *          the STM32WBxx I2C LL API.
+  *          Peripheral initialization done using LL unitary services functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/**
+  * @brief Timeout value
+  */
+#if (USE_TIMEOUT == 1)
+#define DMA_SEND_TIMEOUT_TC_MS               5
+#ifdef SLAVE_BOARD
+#define I2C_SEND_TIMEOUT_STOP_MS             5
+#else /* MASTER BOARD */
+#define I2C_SEND_TIMEOUT_SB_MS               5
+#define I2C_SEND_TIMEOUT_ADDR_MS             5
+#endif
+#endif /* USE_TIMEOUT */
+
+/**
+  * @brief I2C devices settings
+  */
+/* Timing register value is computed with the STM32CubeMX Tool,
+  * Fast Mode @400kHz with I2CCLK = 16 MHz,
+  * rise time = 100ns, fall time = 10ns
+  * Timing Value = (uint32_t)0x00300516
+  */
+#define I2C_TIMING                           0x00300516
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+#if (USE_TIMEOUT == 1)
+uint32_t Timeout                             = 0; /* Variable used for Timeout management */
+#endif /* USE_TIMEOUT */
+const uint8_t aLedOn[]                       = "LED ON";
+
+/**
+  * @brief Variables related to SlaveReceive process
+  */
+__IO uint8_t  ubNbDataToReceive              = sizeof(aLedOn);
+uint8_t       aReceiveBuffer[sizeof(aLedOn)] = {0};
+__IO uint8_t  ubSlaveTransferComplete        = 0;
+
+/**
+  * @brief Variables related to MasterTransmit process
+  */
+__IO uint8_t  ubNbDataToTransmit             = sizeof(aLedOn);
+uint8_t      *pTransmitBuffer                = (uint8_t *)aLedOn;
+__IO uint8_t  ubMasterTransferComplete       = 0;
+__IO uint8_t  ubButtonPress                  = 0;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+static void MX_I2C1_Init(void);
+/* USER CODE BEGIN PFP */
+void     LED_On(void);
+void     LED_Off(void);
+void     LED_Blinking(uint32_t Period);
+void     UserButton_Init(void);
+
+#ifdef SLAVE_BOARD
+void     Handle_I2C_Slave(void);
+uint8_t  Buffercmp8(uint8_t *pBuffer1, uint8_t *pBuffer2, uint8_t BufferLength);
+
+#else /* MASTER_BOARD */
+void     WaitForUserButtonPress(void);
+void     Handle_I2C_Master(void);
+#endif /* SLAVE_BOARD */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_I2C1_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Set LED2 Off */
+  LED_Off();
+
+#ifdef SLAVE_BOARD
+
+  /* Handle I2C1 events (Slave) */
+  Handle_I2C_Slave();
+#else /* MASTER_BOARD */
+  UserButton_Init();
+  /* Wait for User push-button (SW1) press to start transfer */
+  WaitForUserButtonPress();
+
+  /* Handle I2C1 events (Master) */
+  Handle_I2C_Master();
+#endif /* SLAVE_BOARD */
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  /* HSI configuration and activation */
+  LL_RCC_HSI_Enable();
+  while(LL_RCC_HSI_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the HSI */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(16000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(16000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief I2C1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_I2C1_Init(void)
+{
+
+  /* USER CODE BEGIN I2C1_Init 0 */
+
+  /* USER CODE END I2C1_Init 0 */
+
+  LL_I2C_InitTypeDef I2C_InitStruct = {0};
+
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+  /**I2C1 GPIO Configuration  
+  PB8   ------> I2C1_SCL
+  PB9   ------> I2C1_SDA 
+  */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_8|LL_GPIO_PIN_9;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_4;
+  LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* Peripheral clock enable */
+  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1);
+
+  /* I2C1 DMA Init */
+  
+  /* I2C1_RX Init */
+  LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_3, LL_DMAMUX_REQ_I2C1_RX);
+
+  LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_3, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+
+  LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PRIORITY_HIGH);
+
+  LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MODE_NORMAL);
+
+  LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PERIPH_NOINCREMENT);
+
+  LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MEMORY_INCREMENT);
+
+  LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PDATAALIGN_BYTE);
+
+  LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MDATAALIGN_BYTE);
+
+  /* I2C1_TX Init */
+  LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_2, LL_DMAMUX_REQ_I2C1_TX);
+
+  LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_2, LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
+
+  LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_2, LL_DMA_PRIORITY_HIGH);
+
+  LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_2, LL_DMA_MODE_NORMAL);
+
+  LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_2, LL_DMA_PERIPH_NOINCREMENT);
+
+  LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_2, LL_DMA_MEMORY_INCREMENT);
+
+  LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_2, LL_DMA_PDATAALIGN_BYTE);
+
+  LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_2, LL_DMA_MDATAALIGN_BYTE);
+
+  /* USER CODE BEGIN I2C1_Init 1 */
+  LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_3, ubNbDataToTransmit);
+  LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_3, (uint32_t)LL_I2C_DMA_GetRegAddr(I2C1, LL_I2C_DMA_REG_DATA_RECEIVE), (uint32_t) & (aReceiveBuffer), LL_DMA_GetDataTransferDirection(DMA1, LL_DMA_CHANNEL_3));
+  LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_2, ubNbDataToTransmit);
+  LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_2, (uint32_t)pTransmitBuffer, (uint32_t)LL_I2C_DMA_GetRegAddr(I2C1, LL_I2C_DMA_REG_DATA_TRANSMIT), LL_DMA_GetDataTransferDirection(DMA1, LL_DMA_CHANNEL_2));
+  LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_3);
+  LL_DMA_EnableIT_TE(DMA1, LL_DMA_CHANNEL_3);
+  LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_2);
+  LL_DMA_EnableIT_TE(DMA1, LL_DMA_CHANNEL_2);
+  /* USER CODE END I2C1_Init 1 */
+  /** I2C Initialization 
+  */
+  I2C_InitStruct.PeripheralMode = LL_I2C_MODE_I2C;
+  I2C_InitStruct.Timing = 0x00300516;
+  I2C_InitStruct.AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE;
+  I2C_InitStruct.DigitalFilter = 2;
+  I2C_InitStruct.OwnAddress1 = 180;
+  I2C_InitStruct.TypeAcknowledge = LL_I2C_ACK;
+  I2C_InitStruct.OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
+  LL_I2C_Init(I2C1, &I2C_InitStruct);
+  LL_I2C_EnableAutoEndMode(I2C1);
+  LL_I2C_SetOwnAddress2(I2C1, 0, LL_I2C_OWNADDRESS2_NOMASK);
+  LL_I2C_DisableOwnAddress2(I2C1);
+  LL_I2C_DisableGeneralCall(I2C1);
+  LL_I2C_EnableClockStretching(I2C1);
+  /* USER CODE BEGIN I2C1_Init 2 */
+#ifdef SLAVE_BOARD
+  LL_I2C_EnableDMAReq_RX(I2C1);
+#else /* MASTER_BOARD */
+  LL_I2C_EnableDMAReq_TX(I2C1);
+#endif /* SLAVE_BOARD */
+  LL_I2C_Enable(I2C1);
+  /* USER CODE END I2C1_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* Init with LL driver */
+  /* DMA controller clock enable */
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1);
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
+
+  /* DMA interrupt init */
+  /* DMA1_Channel2_IRQn interrupt configuration */
+  NVIC_SetPriority(DMA1_Channel2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(DMA1_Channel2_IRQn);
+  /* DMA1_Channel3_IRQn interrupt configuration */
+  NVIC_SetPriority(DMA1_Channel3_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(DMA1_Channel3_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+#ifdef SLAVE_BOARD
+#else /* MASTER_BOARD */
+#endif /* SLAVE_BOARD */
+
+
+/**
+  * @brief  Turn-on LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_On(void)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Turn-off LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_Off(void)
+{
+  /* Turn LED2 off */
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
+  * @param  Period : Period of time (in ms) between each toggling of LED
+  *   This parameter can be user defined values. Pre-defined values used in that example are :
+  *     @arg LED_BLINK_FAST : Fast Blinking
+  *     @arg LED_BLINK_SLOW : Slow Blinking
+  *     @arg LED_BLINK_ERROR : Error specific Blinking
+  * @retval None
+  */
+void LED_Blinking(uint32_t Period)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /* Toggle IO in an infinite loop */
+  while (1)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+    LL_mDelay(Period);
+  }
+}
+
+
+#ifdef SLAVE_BOARD
+/**
+  * @brief  This Function handle Slave events to perform a reception process
+  * @note  This function is composed in different steps :
+  *        -1- Wait ADDR flag and check address match code and direction
+  *             -1.1- Enable DMA transfer(before clearing ADDR FLag).
+  *        -2- Loop until end of transfer completed (DMA TC raised).
+  *        -3- Loop until end of slave reception completed (STOP flag raised).
+  *        -4- Clear pending flags, check Data consistency.
+  * @param  None
+  * @retval None
+  */
+void Handle_I2C_Slave(void)
+{
+
+  /* (1) Wait ADDR flag and check address match code and direction ************/
+  while (!LL_I2C_IsActiveFlag_ADDR(I2C1))
+  {
+  }
+
+  /* Verify the Address Match with the OWN Slave address */
+  if (LL_I2C_GetAddressMatchCode(I2C1) == SLAVE_OWN_ADDRESS)
+  {
+    /* Verify the transfer direction, a write direction, Slave enters receiver mode */
+    if (LL_I2C_GetTransferDirection(I2C1) == LL_I2C_DIRECTION_WRITE)
+    {
+      /* (1.1) Enable DMA transfer (before clearing ADDR FLag) ****************/
+      LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_3);
+      /* Clear ADDR flag value in ISR register */
+      LL_I2C_ClearFlag_ADDR(I2C1);
+    }
+    else
+    {
+      /* Clear ADDR flag value in ISR register */
+      LL_I2C_ClearFlag_ADDR(I2C1);
+
+      /* Call Error function */
+      Error_Callback();
+    }
+  }
+  else
+  {
+    /* Clear ADDR flag value in ISR register */
+    LL_I2C_ClearFlag_ADDR(I2C1);
+
+    /* Call Error function */
+    Error_Callback();
+  }
+
+  /* (4) Loop until end of transfer completed (DMA TC raised) *****************/
+
+#if (USE_TIMEOUT == 1)
+  Timeout = DMA_SEND_TIMEOUT_TC_MS;
+#endif /* USE_TIMEOUT */
+
+  /* Loop until DMA transfer complete event */
+  while (!ubSlaveTransferComplete)
+  {
+#if (USE_TIMEOUT == 1)
+    /* Check Systick counter flag to decrement the time-out value */
+    if (LL_SYSTICK_IsActiveCounterFlag())
+    {
+      if (Timeout-- == 0)
+      {
+        /* Time-out occurred. Set LED to blinking mode */
+        LED_Blinking(LED_BLINK_SLOW);
+      }
+    }
+#endif /* USE_TIMEOUT */
+  }
+
+  /* (5) Loop until end of slave reception completed (STOP flag raised) *******/
+
+#if (USE_TIMEOUT == 1)
+  Timeout = I2C_SEND_TIMEOUT_STOP_MS;
+#endif /* USE_TIMEOUT */
+
+  /* Loop until STOP flag is raised  */
+  while (!LL_I2C_IsActiveFlag_STOP(I2C1))
+  {
+#if (USE_TIMEOUT == 1)
+    /* Check Systick counter flag to decrement the time-out value */
+    if (LL_SYSTICK_IsActiveCounterFlag())
+    {
+      if (Timeout-- == 0)
+      {
+        /* Time-out occurred. Set LED2 to blinking mode */
+        LED_Blinking(LED_BLINK_SLOW);
+      }
+    }
+#endif /* USE_TIMEOUT */
+  }
+
+  /* (6) Clear pending flags, Data consistency are checking into Slave process */
+
+  /* End of I2C_SlaveReceiver_MasterTransmitter_DMA Process */
+  LL_I2C_ClearFlag_STOP(I2C1);
+
+  /* Check if datas request to turn on the LED2 */
+  if (Buffercmp8((uint8_t *)aReceiveBuffer, (uint8_t *)aLedOn, (ubNbDataToReceive - 1)) == 0)
+  {
+    /* Turn LED2 On:
+     * Expected bytes have been received
+     * Slave Rx sequence completed successfully
+     */
+    LED_On();
+  }
+  else
+  {
+    /* Call Error function */
+    Error_Callback();
+  }
+}
+
+/**
+  * @brief  Compares two 8-bit buffers and returns the comparison result.
+  * @param  pBuffer1: pointer to the source buffer to be compared to.
+  * @param  pBuffer2: pointer to the second source buffer to be compared to the first.
+  * @param  BufferLength: buffer's length.
+  *    - 0: Comparison is OK (the two Buffers are identical)
+  *    - Value different from 0: Comparison is NOK (Buffers are different)
+  */
+uint8_t Buffercmp8(uint8_t *pBuffer1, uint8_t *pBuffer2, uint8_t BufferLength)
+{
+  while (BufferLength--)
+  {
+    if (*pBuffer1 != *pBuffer2)
+    {
+      return 1;
+    }
+
+    pBuffer1++;
+    pBuffer2++;
+  }
+
+  return 0;
+}
+
+#else /* MASTER_BOARD */
+/**
+  * @brief  Configures User push-button (SW1) in GPIO or EXTI Line Mode.
+  * @param  None
+  * @retval None
+  */
+void UserButton_Init(void)
+{
+  /* Enable the BUTTON Clock */
+  USER_BUTTON_GPIO_CLK_ENABLE();
+
+  /* Configure GPIO for BUTTON */
+  LL_GPIO_SetPinMode(USER_BUTTON_GPIO_PORT, USER_BUTTON_PIN, LL_GPIO_MODE_INPUT);
+  LL_GPIO_SetPinPull(USER_BUTTON_GPIO_PORT, USER_BUTTON_PIN, LL_GPIO_PULL_UP);
+
+  /* Connect External Line to the GPIO*/
+  USER_BUTTON_SYSCFG_SET_EXTI();
+
+  /* Enable a rising trigger External line 0 Interrupt */
+  USER_BUTTON_EXTI_LINE_ENABLE();
+  USER_BUTTON_EXTI_FALLING_TRIG_ENABLE();
+
+  /* Configure NVIC for USER_BUTTON_EXTI_IRQn */
+  NVIC_SetPriority(USER_BUTTON_EXTI_IRQn, 3);
+  NVIC_EnableIRQ(USER_BUTTON_EXTI_IRQn);
+}
+/**
+  * @brief  Wait for User push-button (SW1) press to start transfer.
+  * @param  None
+  * @retval None
+  */
+/*  */
+void WaitForUserButtonPress(void)
+{
+  while (ubButtonPress == 0)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+    LL_mDelay(LED_BLINK_FAST);
+  }
+  /* Turn LED2 off */
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  This Function handle Master events to perform a transmission process
+  * @note  This function is composed in different steps :
+  *        -1- Enable DMA transfer.
+  *        -2- Initiate a Start condition to the Slave device.
+  *        -3- Loop until end of transfer completed (DMA TC raised).
+  *        -4- Loop until end of master transfer completed (STOP flag raised).
+  *        -5- Clear pending flags, Data consistency are checking into Slave process.
+  * @param  None
+  * @retval None
+  */
+void Handle_I2C_Master(void)
+{
+  /* (1) Enable DMA transfer **************************************************/
+  LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_2);
+  /* (2) Initiate a Start condition to the Slave device ***********************/
+
+  /* Master Generate Start condition for a write request:
+   *  - to the Slave with a 7-Bit SLAVE_OWN_ADDRESS
+   *  - with a auto stop condition generation when transmit all bytes
+   */
+  LL_I2C_HandleTransfer(I2C1, SLAVE_OWN_ADDRESS, LL_I2C_ADDRSLAVE_7BIT, ubNbDataToTransmit, LL_I2C_MODE_AUTOEND, LL_I2C_GENERATE_START_WRITE);
+
+  /* (3) Loop until end of transfer completed (DMA TC raised) *****************/
+
+#if (USE_TIMEOUT == 1)
+  Timeout = DMA_SEND_TIMEOUT_TC_MS;
+#endif /* USE_TIMEOUT */
+
+  /* Loop until DMA transfer complete event */
+  while (!ubMasterTransferComplete)
+  {
+#if (USE_TIMEOUT == 1)
+    /* Check Systick counter flag to decrement the time-out value */
+    if (LL_SYSTICK_IsActiveCounterFlag())
+    {
+      if (Timeout-- == 0)
+      {
+        /* Time-out occurred. Set LED to blinking mode */
+        LED_Blinking(LED_BLINK_SLOW);
+      }
+    }
+#endif /* USE_TIMEOUT */
+  }
+
+  /* (4) Loop until end of master transfer completed (STOP flag raised) *******/
+
+#if (USE_TIMEOUT == 1)
+  Timeout = I2C_SEND_TIMEOUT_STOP_MS;
+#endif /* USE_TIMEOUT */
+
+  /* Loop until STOP flag is raised  */
+  while (!LL_I2C_IsActiveFlag_STOP(I2C1))
+  {
+#if (USE_TIMEOUT == 1)
+    /* Check Systick counter flag to decrement the time-out value */
+    if (LL_SYSTICK_IsActiveCounterFlag())
+    {
+      if (Timeout-- == 0)
+      {
+        /* Time-out occurred. Set LED2 to blinking mode */
+        LED_Blinking(LED_BLINK_SLOW);
+      }
+    }
+#endif /* USE_TIMEOUT */
+  }
+
+  /* (5) Clear pending flags, Data consistency are checking into Slave process */
+
+  /* End of I2C_SlaveReceiver_MasterTransmitter_DMA Process */
+  LL_I2C_ClearFlag_STOP(I2C1);
+
+  /* Turn LED2 On:
+   *  - Expected bytes have been sent
+   *  - Master Tx sequence completed successfully
+   */
+  LED_On();
+}
+#endif /* SLAVE_BOARD */
+/******************************************************************************/
+/*   IRQ HANDLER TREATMENT Functions                                          */
+/******************************************************************************/
+
+#ifdef SLAVE_BOARD
+/**
+  * @brief  Function called from DMA1 IRQ Handler
+  * @note   This function is executed when the transfer complete interrupt
+  *         is generated
+  * @retval None
+  */
+void DMA1_Transfer_Complete_Callback()
+{
+  /* DMA transfer completed */
+  ubSlaveTransferComplete = 1;
+}
+
+/**
+  * @brief  Function called from DMA1 IRQ Handler
+  * @note   This function is executed when the transfer error interrupt
+  *         is generated during DMA transfer
+  * @retval None
+  */
+void DMA1_Transfer_Error_Callback()
+{
+  /* Disable DMA1_Channel3_IRQn */
+  NVIC_DisableIRQ(DMA1_Channel3_IRQn);
+
+  /* Error detected during DMA transfer */
+  LED_Blinking(LED_BLINK_ERROR);
+}
+
+#else /* MASTER_BOARD */
+
+/**
+  * @brief  Function to manage User push-button (SW1)
+  * @param  None
+  * @retval None
+  */
+void UserButton_Callback(void)
+{
+  /* Update User push-button (SW1) variable : to be checked in waiting loop in main program */
+  ubButtonPress = 1;
+}
+
+/**
+  * @brief  Function called from DMA1 IRQ Handler
+  * @note   This function is executed when the transfer complete interrupt
+  *         is generated
+  * @retval None
+  */
+void DMA1_Transfer_Complete_Callback()
+{
+  /* DMA transfer completed */
+  ubMasterTransferComplete = 1;
+}
+
+/**
+  * @brief  Function called from DMA1 IRQ Handler
+  * @note   This function is executed when the transfer error interrupt
+  *         is generated during DMA transfer
+  * @retval None
+  */
+void DMA1_Transfer_Error_Callback()
+{
+  /* Disable DMA1_Channel2_IRQn */
+  NVIC_DisableIRQ(DMA1_Channel2_IRQn);
+
+  /* Error detected during DMA transfer */
+  LED_Blinking(LED_BLINK_ERROR);
+}
+#endif /* SLAVE_BOARD */
+
+/**
+  * @brief  Function called in case of error detected in I2C IT Handler
+  * @param  None
+  * @retval None
+  */
+void Error_Callback(void)
+{
+  /* Disable DMA1_Channel3_IRQn and DMA1_Channel2_IRQn */
+  NVIC_DisableIRQ(DMA1_Channel3_IRQn);
+  NVIC_DisableIRQ(DMA1_Channel2_IRQn);
+
+  /* Unexpected event : Set LED2 to Blinking mode to indicate error occurs */
+  LED_Blinking(LED_BLINK_ERROR);
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..024be71b5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,274 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles DMA1 channel2 global interrupt.
+  */
+void DMA1_Channel2_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */
+#ifdef SLAVE_BOARD
+#else
+  if (LL_DMA_IsActiveFlag_TC2(DMA1))
+  {
+    LL_DMA_ClearFlag_GI2(DMA1);
+    DMA1_Transfer_Complete_Callback();
+  }
+  else if (LL_DMA_IsActiveFlag_TE2(DMA1))
+  {
+    DMA1_Transfer_Error_Callback();
+  }
+#endif
+  /* USER CODE END DMA1_Channel2_IRQn 0 */
+  
+  /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel2_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA1 channel3 global interrupt.
+  */
+void DMA1_Channel3_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel3_IRQn 0 */
+#ifdef SLAVE_BOARD
+  if (LL_DMA_IsActiveFlag_TC3(DMA1))
+  {
+    LL_DMA_ClearFlag_GI3(DMA1);
+    DMA1_Transfer_Complete_Callback();
+  }
+  else if (LL_DMA_IsActiveFlag_TE3(DMA1))
+  {
+    DMA1_Transfer_Error_Callback();
+  }
+#endif
+  /* USER CODE END DMA1_Channel3_IRQn 0 */
+  
+  /* USER CODE BEGIN DMA1_Channel3_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel3_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+#ifdef SLAVE_BOARD
+#else
+/**
+  * @brief  This function handles external line 0 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void USER_BUTTON_IRQHANDLER(void)
+{
+  /* Manage Flags */
+  if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
+  {
+    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
+
+    /* Handle User push-button (SW1) press in dedicated function */
+    UserButton_Callback();
+  }
+}
+#endif
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/readme.txt
new file mode 100644
index 000000000..3a376fef0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/readme.txt
@@ -0,0 +1,131 @@
+/**
+  @page I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init I2C example (DMA Mode)
+
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init I2C example (DMA Mode).
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to transmit data bytes from an I2C master device using DMA mode
+to an I2C slave device using DMA mode. The peripheral is initialized
+with LL unitary service functions to optimize for performance and size.
+
+This example guides you through the different configuration steps by mean of LL API
+to configure GPIO, DMA and I2C peripherals using two NUCLEO-WB35CE.
+
+Boards: NUCLEO-WB35CE (embeds a STM32WB35CE device)
+SCL Pin: PB.8 (CN10, pin 3)
+SDA Pin: PB.9 (CN10, pin 5)
+
+   ______BOARD SLAVE_____                       _____BOARD MASTER_____
+  |        ______________|                     |______________        |
+  |       |I2C1          |                     |          I2C1|       |
+  |       |              |                     |              |       |
+  |       |          SCL |_____________________| SCL          |       |
+  |       |              |                     |              |       |
+  |       |              |                     |              |       |
+  |       |          SDA |_____________________| SDA          |       |
+  |       |______________|                     |______________|       |
+  |         __           |                     |             __       |
+  |        |__|          |                     |            |__|      |
+  |        USER       GND|_____________________|GND         USER      |
+  |___NUCLEO-WB35CE___|                     |___NUCLEO-WB35CE___|
+
+The project is splitted in two parts the Master Board and the Slave Board
+- Master Board
+  I2C1 Peripheral is configured in Master mode with DMA (Clock 400Khz).
+  And GPIO associated to User push-button (SW1) is linked with EXTI.
+- Slave Board
+  I2C1 Peripheral is configured in Slave mode with DMA (Clock 400Khz, Own address 7-bit enabled).
+
+The user can choose between Master and Slave through "#define SLAVE_BOARD"
+in the "main.h" file:
+- Comment "#define SLAVE_BOARD" to select Master board.
+- Uncomment "#define SLAVE_BOARD" to select Slave board.
+
+The user can disable internal pull-up by opening ioc file.
+For that, user can follow the procedure :
+1- Double click on the I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init.ioc file
+2- When CUBEMX tool is opened, select System Core category
+3- Then in the configuration of GPIO/I2C1, change Pull-up to No pull-up and no pull-down for the both pins
+4- Last step, generate new code thanks to button "GENERATE CODE"
+The example is updated with no pull on each pin used for I2C communication
+
+A first program launch, BOARD SLAVE waiting Address Match code through Handle_I2C_Slave() routine.
+LED2 blinks quickly on BOARD MASTER to wait for user-button press.
+
+Example execution:
+Press the User push-button (SW1) on BOARD MASTER to initiate a write request by Master through Handle_I2C_Master() routine.
+This action will generate an I2C start condition with the Slave address and a write bit condition.
+When address Slave match code is received on I2C1 of BOARD SLAVE, an ADDR event occurs.
+Handle_I2C_Slave() routine is then checking Address Match Code and direction Write.
+This will allow Slave to enter in receiver mode and then acknowledge Master to send the bytes through DMA.
+When acknowledge is received on I2C1 (Master), DMA transfer the data from flash memory buffer to I2C1 TXDR register (Master).
+This will allow Master to transmit a byte to the Slave.
+Each time a byte is received on I2C1 (Slave), DMA transfer the data from I2C1 RXDR register to RAM memory buffer (Slave).
+And so each time the Slave acknowledge the byte received,
+DMA transfer the next data from flash memory buffer to I2C1 TXDR register (Master) until Transfer completed.
+Master auto-generate a Stop condition when DMA transfer is achieved.
+
+The STOP condition generate a STOP event and initiate the end of reception on Slave side.
+Handle_I2C_Slave() and Handle_I2C_Master() routine are then clearing the STOP flag in both side.
+
+LED2 is On :
+- Slave side if data are well received.
+- Master side if transfer sequence is completed.
+
+In case of errors, LED2 is blinking slowly (1s).
+
+
+@par Directory contents
+
+  - I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Inc/main.h                  Header for main.c module
+  - I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Inc/stm32_assert.h          Template file to include assert_failed function
+  - I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Src/main.c                  Main program
+  - I2C/I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+  - NUCLEO-WB35CE Set-up
+    - Connect GPIOs connected to Board Slave I2C1 SCL/SDA (PB.8 and PB.9)
+    to respectively Board Master SCL and SDA pins of I2C1 (PB.8 and PB.9).
+      - I2C1_SCL  PB.8 (CN10, pin 3) : connected to I2C1_SCL PB.8 (CN10, pin 3)
+      - I2C1_SDA  PB.9 (CN10, pin 5) : connected to I2C1_SDA PB.9 (CN10, pin 5)
+    - Connect Master board GND to Slave Board GND
+
+  - Launch the program. Press User push-button (SW1) to initiate a write request by Master
+      then Slave receive bytes.
+
+@par How to use it ?
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory (The user can choose between Master
+   and Slave target through "#define SLAVE_BOARD" in the "main.h" file)
+    o Comment "#define SLAVE_BOARD" and load the project in Master Board
+    o Uncomment "#define SLAVE_BOARD" and load the project in Slave Board
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/IWDG_RefreshUntilUserEvent_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/IWDG_RefreshUntilUserEvent_Init.ewd
new file mode 100644
index 000000000..68e7737fd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/IWDG_RefreshUntilUserEvent_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		IWDG_RefreshUntilUserEvent_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/IWDG_RefreshUntilUserEvent_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/IWDG_RefreshUntilUserEvent_Init.ewp
new file mode 100644
index 000000000..e065c86af
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/IWDG_RefreshUntilUserEvent_Init.ewp
@@ -0,0 +1,1083 @@
+
+
+  3
+  
+    IWDG_RefreshUntilUserEvent_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/Project.eww
new file mode 100644
index 000000000..4a89566cb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\IWDG_RefreshUntilUserEvent_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/IWDG_RefreshUntilUserEvent_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/IWDG_RefreshUntilUserEvent_Init.ioc
new file mode 100644
index 000000000..b14085db0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/IWDG_RefreshUntilUserEvent_Init.ioc
@@ -0,0 +1,129 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+IWDG.IPParameters=Prescaler,Window,Reload
+IWDG.Prescaler=IWDG_PRESCALER_4
+IWDG.Reload=4078
+IWDG.Window=4095
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=IWDG
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA0
+Mcu.Pin1=PB0
+Mcu.Pin2=VP_IWDG_VS_IWDG
+Mcu.Pin3=VP_SYS_VS_Systick
+Mcu.PinsNb=4
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.EXTI0_IRQn=true\:3\:0\:true\:false\:true\:true\:true
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA0.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultEXTI
+PA0.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
+PA0.GPIO_PuPd=GPIO_PULLUP
+PA0.Locked=true
+PA0.Signal=GPXTI0
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=IWDG_RefreshUntilUserEvent_Init.ioc
+ProjectManager.ProjectName=IWDG_RefreshUntilUserEvent_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-true,3-MX_IWDG_Init-IWDG-false-LL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SH.GPXTI0.0=GPIO_EXTI0
+SH.GPXTI0.ConfNb=1
+VP_IWDG_VS_IWDG.Mode=IWDG_Activate
+VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
+boardIOC=true
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Inc/main.h
new file mode 100644
index 000000000..612819f4f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Inc/main.h
@@ -0,0 +1,111 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_iwdg.h"
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+void UserButton_Callback(void);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/**
+  * @brief Toggle periods for various blinking modes
+  */
+
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW  500
+#define LED_BLINK_ERROR 1000
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..2da100d30
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void EXTI0_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+void UserButton_Callback(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/MDK-ARM/IWDG_RefreshUntilUserEvent_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/MDK-ARM/IWDG_RefreshUntilUserEvent_Init.uvoptx
new file mode 100644
index 000000000..a36207281
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/MDK-ARM/IWDG_RefreshUntilUserEvent_Init.uvoptx
@@ -0,0 +1,333 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    IWDG_RefreshUntilUserEvent_Init
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/MDK-ARM/IWDG_RefreshUntilUserEvent_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/MDK-ARM/IWDG_RefreshUntilUserEvent_Init.uvprojx
new file mode 100644
index 000000000..8814ba400
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/MDK-ARM/IWDG_RefreshUntilUserEvent_Init.uvprojx
@@ -0,0 +1,471 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      IWDG_RefreshUntilUserEvent_Init
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          IWDG_RefreshUntilUserEvent_Init\
+          IWDG_RefreshUntilUserEvent_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..061abda77
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..e40449f29
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/.project
@@ -0,0 +1,80 @@
+
+
+	IWDG_RefreshUntilUserEvent_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			IWDG_RefreshUntilUserEvent_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/IWDG_RefreshUntilUserEvent_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Src/main.c
new file mode 100644
index 000000000..d8c9276ca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Src/main.c
@@ -0,0 +1,347 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to configure IWDG down-counter (without Window)
+  *          using the STM32WBxx IWDG LL API.
+  *          Peripheral initialization done using LL unitary services functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+static __IO uint8_t ubKeyPressed = 0;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_IWDG_Init(void);
+/* USER CODE BEGIN PFP */
+void     Check_IWDG_Reset(void);
+void     LED_On(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* Check if the system has resumed from IWDG reset */
+  Check_IWDG_Reset();
+  
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_IWDG_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+    if (1 != ubKeyPressed)
+    {
+      /* Refresh IWDG down-counter to default value */
+      LL_IWDG_ReloadCounter(IWDG);
+      
+      LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+      /* Note that period used for Counter Reload MUST be higher than blinking timing value*/
+      /* This Counter reload timeout period is a function of this value and the 
+         clock prescaler. Refer to the datasheet for the timeout information  */
+      LL_mDelay(LED_BLINK_FAST);
+    }
+  }
+
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* MSI configuration and activation */
+  LL_RCC_MSI_Enable();
+  while(LL_RCC_MSI_IsReady() != 1)
+  {
+  };
+
+  /* Main PLL configuration and activation */
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 32, LL_RCC_PLLR_DIV_2);
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the main PLL */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(64000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(64000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief IWDG Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_IWDG_Init(void)
+{
+
+  /* USER CODE BEGIN IWDG_Init 0 */
+
+  /* USER CODE END IWDG_Init 0 */
+
+  /* USER CODE BEGIN IWDG_Init 1 */
+
+  /* USER CODE END IWDG_Init 1 */
+  LL_IWDG_Enable(IWDG);
+  LL_IWDG_EnableWriteAccess(IWDG);
+  LL_IWDG_SetPrescaler(IWDG, LL_IWDG_PRESCALER_4);
+  LL_IWDG_SetWindow(IWDG, 4095);
+  LL_IWDG_SetReloadCounter(IWDG, 4078);
+  while (LL_IWDG_IsReady(IWDG) != 1)
+  {
+  }
+
+  LL_IWDG_ReloadCounter(IWDG);
+  /* USER CODE BEGIN IWDG_Init 2 */
+
+  /* USER CODE END IWDG_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_EXTI_InitTypeDef EXTI_InitStruct = {0};
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTA, LL_SYSCFG_EXTI_LINE0);
+
+  /**/
+  EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_0;
+  EXTI_InitStruct.Line_32_63 = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct.LineCommand = ENABLE;
+  EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;
+  EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_FALLING;
+  LL_EXTI_Init(&EXTI_InitStruct);
+
+  /**/
+  LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_0, LL_GPIO_PULL_UP);
+
+  /**/
+  LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_0, LL_GPIO_MODE_INPUT);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+  /* EXTI interrupt init*/
+  NVIC_SetPriority(EXTI0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),3, 0));
+  NVIC_EnableIRQ(EXTI0_IRQn);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  This function check if the system has resumed from IWDG reset
+  * @param  None
+  * @retval None
+  */
+void Check_IWDG_Reset(void)
+{
+  if (LL_RCC_IsActiveFlag_IWDGRST())
+  {
+    /* clear IWDG reset flag */
+    LL_RCC_ClearResetFlags();
+
+    /* Re-Initialize GPIO configured peripheral */
+    MX_GPIO_Init();
+    
+    /* turn Led on and wait for user event to perform example again */
+    LED_On();
+    
+    while(ubKeyPressed != 1)
+    {
+    }
+
+    /* Reset ubKeyPressed value */
+    ubKeyPressed = 0;
+  }
+}
+
+/**
+  * @brief  Turn-on LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_On(void)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT                                               */
+/******************************************************************************/
+/**
+  * @brief  Function to manage IRQ Handler
+  * @param  None
+  * @retval None
+  */
+void UserButton_Callback(void)
+{
+  ubKeyPressed = 1;
+}
+
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..85d0955c0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,230 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles EXTI line0 interrupt.
+  */
+void EXTI0_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI0_IRQn 0 */
+
+  /* USER CODE END EXTI0_IRQn 0 */
+  if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
+  {
+    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
+    /* USER CODE BEGIN LL_EXTI_LINE_0 */
+    
+    /* Manage code in main.c.*/
+    UserButton_Callback(); 
+    
+    /* USER CODE END LL_EXTI_LINE_0 */
+  }
+  /* USER CODE BEGIN EXTI0_IRQn 1 */
+
+  /* USER CODE END EXTI0_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/readme.txt
new file mode 100644
index 000000000..a92ca737e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/readme.txt
@@ -0,0 +1,66 @@
+/**
+  @page IWDG_RefreshUntilUserEvent_Init IWDG example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/IWDG/IWDG_RefreshUntilUserEvent_Init/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the IWDG_RefreshUntilUserEvent_Init example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to configure the IWDG peripheral to ensure periodical counter update and 
+generate an MCU IWDG reset when a User push-button (SW1) is pressed. The peripheral 
+is initialized with LL unitary service functions to optimize 
+for performance and size.
+
+Example Configuration:
+Configure the IWDG (prescaler, counter) and enable it.
+Infinite refresh of the IWDG down-counter done in the main loop.
+LED2 is blinking fast & continuously.
+
+Example Execution:
+When User push-button (SW1) is pressed, the down-counter automatic refresh mechanism is 
+disable and thus, reset will occur. After a reset, when re-entering in the main, 
+RCC IWDG Reset Flag will be checked and if we are back from a IWDG reset the LED2
+will be switch ON.
+
+Waiting a new User push-button (SW1) pressed to re-activate the IWDG
+
+@par Directory contents 
+
+  - IWDG/IWDG_RefreshUntilUserEvent_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - IWDG/IWDG_RefreshUntilUserEvent_Init/Inc/main.h                        Header for main.c module
+  - IWDG/IWDG_RefreshUntilUserEvent_Init/Inc/stm32_assert.h                Template file to include assert_failed function
+  - IWDG/IWDG_RefreshUntilUserEvent_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - IWDG/IWDG_RefreshUntilUserEvent_Init/Src/main.c                        Main program
+  - IWDG/IWDG_RefreshUntilUserEvent_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/.extSettings
new file mode 100644
index 000000000..274652791
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/STM32WBxx_HAL_Driver=../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/LPTIM_PulseCounter_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/LPTIM_PulseCounter_Init.ewd
new file mode 100644
index 000000000..a469df6f1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/LPTIM_PulseCounter_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		LPTIM_PulseCounter_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/LPTIM_PulseCounter_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/LPTIM_PulseCounter_Init.ewp
new file mode 100644
index 000000000..c9de1b2e1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/LPTIM_PulseCounter_Init.ewp
@@ -0,0 +1,1089 @@
+
+
+  3
+  
+    LPTIM_PulseCounter_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lptim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/Project.eww
new file mode 100644
index 000000000..1b4382415
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\LPTIM_PulseCounter_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Inc/main.h
new file mode 100644
index 000000000..88941d4e0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Inc/main.h
@@ -0,0 +1,100 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_lptim.h"
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+/* LPTIM1 Autotreloead match interrupt processing */
+void LPTimerAutoreloadMatch_Callback(void);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..16a190874
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void LPTIM1_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/LPTIM_PulseCounter_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/LPTIM_PulseCounter_Init.ioc
new file mode 100644
index 000000000..5d9802c26
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/LPTIM_PulseCounter_Init.ioc
@@ -0,0 +1,125 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+LPTIM1.IPParameters=ULPClockPolarity,ULPClockSampleTime,UpdateMode,TriggerSource
+LPTIM1.TriggerSource=LPTIM_TRIGSOURCE_SOFTWARE
+LPTIM1.ULPClockPolarity=LPTIM_CLOCKPOLARITY_RISING
+LPTIM1.ULPClockSampleTime=LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+LPTIM1.UpdateMode=LPTIM_UPDATE_IMMEDIATE
+Mcu.Family=STM32WB
+Mcu.IP0=LPTIM1
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB0
+Mcu.Pin1=PB5
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.LPTIM1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PB5.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PB5.GPIO_PuPd=GPIO_PULLDOWN
+PB5.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PB5.Locked=true
+PB5.Mode=Counts_external_clock_with_synchro_01_occur1
+PB5.Signal=LPTIM1_IN1
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=3
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=LPTIM_PulseCounter_Init.ioc
+ProjectManager.ProjectName=LPTIM_PulseCounter_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false,3-MX_LPTIM1_Init-LPTIM1-false-LL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/MDK-ARM/LPTIM_PulseCounter_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/MDK-ARM/LPTIM_PulseCounter_Init.uvoptx
new file mode 100644
index 000000000..c9a6313b4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/MDK-ARM/LPTIM_PulseCounter_Init.uvoptx
@@ -0,0 +1,357 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    LPTIM_PulseCounter_Init
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066DFF343339415043142608 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(0BE12477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+      stm32wbxx_ll_rcc.c
+      0
+      0
+    
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lptim.c
+      stm32wbxx_ll_lptim.c
+      0
+      0
+    
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/MDK-ARM/LPTIM_PulseCounter_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/MDK-ARM/LPTIM_PulseCounter_Init.uvprojx
new file mode 100644
index 000000000..6dba00efc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/MDK-ARM/LPTIM_PulseCounter_Init.uvprojx
@@ -0,0 +1,481 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      LPTIM_PulseCounter_Init
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          LPTIM_PulseCounter_Init\
+          LPTIM_PulseCounter_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+            
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_lptim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lptim.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..48d099486
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..786578f5b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/.project
@@ -0,0 +1,90 @@
+
+
+	LPTIM_PulseCounter_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			LPTIM_PulseCounter_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/LPTIM_PulseCounter_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_lptim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lptim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Src/main.c
new file mode 100644
index 000000000..2a421471d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Src/main.c
@@ -0,0 +1,350 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to use the LPTIM in counter mode
+  *          using the STM32WBxx LPTIM LL API.
+  *          Peripheral initialization done using LL initialization function.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_LPTIM1_Init(void);
+/* USER CODE BEGIN PFP */
+void Enable_LSI(void);
+void EnterStop1Mode(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* Enable the LSI Clock */
+  Enable_LSI();
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_LPTIM1_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Enter STOP 1 mode */
+  EnterStop1Mode();
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* MSI configuration and activation */
+  LL_RCC_MSI_Enable();
+  while(LL_RCC_MSI_IsReady() != 1)
+  {
+  };
+
+  /* Main PLL configuration and activation */
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 32, LL_RCC_PLLR_DIV_2);
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the main PLL */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(64000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(64000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief LPTIM1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_LPTIM1_Init(void)
+{
+
+  /* USER CODE BEGIN LPTIM1_Init 0 */
+
+  /* Select LSI as LPTIM1 clock source */
+  LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_LSI);
+
+  /* USER CODE END LPTIM1_Init 0 */
+
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* Peripheral clock enable */
+  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1);
+  
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+  /**LPTIM1 GPIO Configuration  
+  PB5   ------> LPTIM1_IN1 
+  */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_5;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_DOWN;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_1;
+  LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* LPTIM1 interrupt Init */
+  NVIC_SetPriority(LPTIM1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(LPTIM1_IRQn);
+
+  /* USER CODE BEGIN LPTIM1_Init 1 */
+
+  /* LPTIM1 interrupts set-up */
+  /* Enable the Autoreload match Interrupt */
+  LL_LPTIM_EnableIT_ARRM(LPTIM1);
+
+  /* USER CODE END LPTIM1_Init 1 */
+  LL_LPTIM_SetClockSource(LPTIM1, LL_LPTIM_CLK_SOURCE_INTERNAL);
+  LL_LPTIM_SetPrescaler(LPTIM1, LL_LPTIM_PRESCALER_DIV1);
+  LL_LPTIM_SetPolarity(LPTIM1, LL_LPTIM_OUTPUT_POLARITY_REGULAR);
+  LL_LPTIM_SetUpdateMode(LPTIM1, LL_LPTIM_UPDATE_MODE_IMMEDIATE);
+  LL_LPTIM_SetCounterMode(LPTIM1, LL_LPTIM_COUNTER_MODE_EXTERNAL);
+  LL_LPTIM_TrigSw(LPTIM1);
+  LL_LPTIM_SetInput1Src(LPTIM1, LL_LPTIM_INPUT1_SRC_GPIO);
+  LL_LPTIM_SetInput2Src(LPTIM1, LL_LPTIM_INPUT2_SRC_GPIO);
+  /* USER CODE BEGIN LPTIM1_Init 2 */
+
+  /* Enable the LPTIM1 counter */
+  LL_LPTIM_Enable(LPTIM1);
+
+  /* Set the Autoreload value */
+  LL_LPTIM_SetAutoReload(LPTIM1, 1000);
+
+  /* Start the LPTIM counter in continuous mode */
+  LL_LPTIM_StartCounter(LPTIM1, LL_LPTIM_OPERATING_MODE_CONTINUOUS);
+
+  /* USER CODE END LPTIM1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  Enable Internal Low Speed Clock (LSI)
+  * @param  None
+  * @retval Status
+  */
+void Enable_LSI(void)
+{
+  /* Enable LSI Oscillator */
+  LL_RCC_LSI1_Enable();
+  
+  while(LL_RCC_LSI1_IsReady() != 1) 
+  {
+  };
+}
+
+/**
+  * @brief  Function to configure and enter in STOP 1 Mode.
+  * @param  None
+  * @retval None
+  */
+void EnterStop1Mode(void)
+{
+  /* Set low-power mode "Stop" */
+  LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1);
+  
+  /* Set low-power mode "Stop" of CPU2 */
+  /* Note: On STM32WB, both CPU1 and CPU2 must be in stop mode to set the entire system in stop mode */
+  LL_C2_PWR_SetPowerMode(LL_PWR_MODE_STOP1);
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  LL_LPM_EnableDeepSleep();
+
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT                                               */
+/******************************************************************************/
+/**
+  * @brief  LPTimer Autoreload match interrupt processing
+  * @param  None
+  * @retval None
+  */
+void LPTimerAutoreloadMatch_Callback(void)
+{
+  LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);  
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  while (1)
+  {
+  }
+
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..1d11ed7c0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,230 @@
+/* USER CODE BEGIN Header */
+/** 
+  ******************************************************************************
+  * @file    Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles LPTIM1 global interrupt.
+  */
+void LPTIM1_IRQHandler(void)
+{
+  /* USER CODE BEGIN LPTIM1_IRQn 0 */
+
+  /* Check whether Autoreload match interrupt is pending */
+  if(LL_LPTIM_IsActiveFlag_ARRM(LPTIM1) == 1)
+  {
+    /* Clear the Autoreload match interrupt flag */
+    LL_LPTIM_ClearFLAG_ARRM(LPTIM1);
+    
+    /* LPTIM1 Autoreload match interrupt processing */
+    LPTimerAutoreloadMatch_Callback();
+  }
+
+  /* USER CODE END LPTIM1_IRQn 0 */
+  /* USER CODE BEGIN LPTIM1_IRQn 1 */
+
+  /* USER CODE END LPTIM1_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/readme.txt
new file mode 100644
index 000000000..5638187b9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPTIM/LPTIM_PulseCounter_Init/readme.txt
@@ -0,0 +1,75 @@
+/**
+  @page LPTIM_PulseCounter_Init LPTIM example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/LPTIM/LPTIM_PulseCounter_Init/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the LPTIM_PulseCounter_Init example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to use the LPTIM peripheral in counter mode to generate a PWM output signal 
+and update its duty cycle. This example is based on the STM32WBxx
+LPTIM LL API. The peripheral is initialized with LL initialization 
+function to demonstrate LL init usage.
+
+To reduce power consumption, MCU enters stop mode after starting counting. Each
+time the counter reaches the maximum value (Period/Autoreload), an interruption
+is generated, the MCU is woken up from stop mode and LED2 toggles the last state.
+
+In this example Period value is set to 1000, so each time the counter counts
+(1000 + 1) rising edges on LPTIM1_IN1 pin, an interrupt is generated and LED2
+toggles. If the external function generator is set to provide a square waveform at 1Khz,
+the led will toggle each second.
+
+In this example the internal clock provided to the LPTIM1 is LSI (32 kHz),
+so the external input is sampled with LSI clock. In order not to miss any event,
+the frequency of the changes on the external Input1 signal should never exceed the
+frequency of the internal clock provided to the LPTIM1 (LSI for the
+present example).
+
+@note On STM32WB, both CPU1 and CPU2 must be in stop mode to set the entire system in stop mode.
+      In this example, CPU2 is not started-up and CPU1 configures the CPU2 stop mode.
+      If this example would be ported to another application, user must manage CPU2 entering in stop mode.
+
+@par Directory contents 
+
+  - LPTIM/LPTIM_PulseCounter_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - LPTIM/LPTIM_PulseCounter_Init/Inc/main.h                  Header for main.c module
+  - LPTIM/LPTIM_PulseCounter_Init/Inc/stm32_assert.h          Template file to include assert_failed function
+  - LPTIM/LPTIM_PulseCounter_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - LPTIM/LPTIM_PulseCounter_Init/Src/main.c                  Main program
+  - LPTIM/LPTIM_PulseCounter_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+    
+  - Connect a square waveform generator to PB5 (Arduino connector CN5 pin D8, Morpho connector CN10 pin 21).
+    If the frequency of the signal is 1 kHz, LED2 toggles every second.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/LPUART_WakeUpFromStop2_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/LPUART_WakeUpFromStop2_Init.ewd
new file mode 100644
index 000000000..ae10649bf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/LPUART_WakeUpFromStop2_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		LPUART_WakeUpFromStop2_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/LPUART_WakeUpFromStop2_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/LPUART_WakeUpFromStop2_Init.ewp
new file mode 100644
index 000000000..82f4fec38
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/LPUART_WakeUpFromStop2_Init.ewp
@@ -0,0 +1,1092 @@
+
+
+  3
+  
+    LPUART_WakeUpFromStop2_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lpuart.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/Project.eww
new file mode 100644
index 000000000..9bd541def
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\LPUART_WakeUpFromStop2_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Inc/main.h
new file mode 100644
index 000000000..b20ea542c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Inc/main.h
@@ -0,0 +1,116 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_lpuart.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Toggle periods for various blinking modes
+  */
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW  500
+#define LED_BLINK_ERROR 1000
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+/* IRQ Handler treatment functions */
+void LPUART_CharReception_Callback(void);
+void Error_Callback(void);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..fe80ae230
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "main.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void LPUART1_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/LPUART_WakeUpFromStop2_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/LPUART_WakeUpFromStop2_Init.ioc
new file mode 100644
index 000000000..84789154d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/LPUART_WakeUpFromStop2_Init.ioc
@@ -0,0 +1,141 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+LPUART1.BaudRate=9600
+LPUART1.DMADisableonRxErrorParam=UART_ADVFEATURE_DMA_ENABLEONRXERROR
+LPUART1.DataInvertParam=UART_ADVFEATURE_DATAINV_DISABLE
+LPUART1.FIFOMode=UART_FIFOMODE_DISABLE
+LPUART1.IPParameters=BaudRate,WordLength,Parity,StopBits,Mode,OneBitSampling,Prescaler,FIFOMode,TXFIFOThreshold,RXFIFOThreshold,TxPinLevelInvertParam,RxPinLevelInvertParam,DataInvertParam,SwapParam,OverrunDisableParam,DMADisableonRxErrorParam,MSBFirstParam
+LPUART1.MSBFirstParam=UART_ADVFEATURE_MSBFIRST_DISABLE
+LPUART1.Mode=UART_MODE_TX_RX
+LPUART1.OneBitSampling=UART_ONE_BIT_SAMPLE_DISABLE
+LPUART1.OverrunDisableParam=UART_ADVFEATURE_OVERRUN_ENABLE
+LPUART1.Parity=UART_PARITY_NONE
+LPUART1.Prescaler=UART_PRESCALER_DIV1
+LPUART1.RXFIFOThreshold=UART_RXFIFO_THRESHOLD_1_8
+LPUART1.RxPinLevelInvertParam=UART_ADVFEATURE_RXINV_DISABLE
+LPUART1.StopBits=UART_STOPBITS_1
+LPUART1.SwapParam=UART_ADVFEATURE_SWAP_DISABLE
+LPUART1.TXFIFOThreshold=UART_TXFIFO_THRESHOLD_1_8
+LPUART1.TxPinLevelInvertParam=UART_ADVFEATURE_TXINV_DISABLE
+LPUART1.WordLength=UART_WORDLENGTH_8B
+Mcu.Family=STM32WB
+Mcu.IP0=LPUART1
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA2
+Mcu.Pin1=PA3
+Mcu.Pin2=PB0
+Mcu.Pin3=VP_SYS_VS_Systick
+Mcu.PinsNb=4
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.LPUART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA2.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA2.GPIO_PuPd=GPIO_PULLUP
+PA2.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PA2.Mode=Asynchronous
+PA2.Signal=LPUART1_TX
+PA3.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA3.GPIO_PuPd=GPIO_PULLUP
+PA3.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PA3.Mode=Asynchronous
+PA3.Signal=LPUART1_RX
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=3
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=LPUART_WakeUpFromStop2_Init.ioc
+ProjectManager.ProjectName=LPUART_WakeUpFromStop2_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false,3-MX_LPUART1_UART_Init-LPUART1-false-LL-true
+RCC.AHBFreq_Value=16000000
+RCC.APB1Freq_Value=16000000
+RCC.APB1TimFreq_Value=16000000
+RCC.APB2Freq_Value=16000000
+RCC.APB2TimFreq_Value=16000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=16000000
+RCC.CortexFreq_Value=16000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=16000000
+RCC.FCLKCortexFreq_Value=16000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=16000000
+RCC.HCLK3Freq_Value=16000000
+RCC.HCLKFreq_Value=16000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=16000000
+RCC.I2C3Freq_Value=16000000
+RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=16000000
+RCC.LPTIM2Freq_Value=16000000
+RCC.LPUART1Freq_Value=16000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=16000000
+RCC.PLLPoutputFreq_Value=16000000
+RCC.PLLQoutputFreq_Value=16000000
+RCC.PLLRCLKFreq_Value=16000000
+RCC.PWRFreq_Value=16000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=16000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_HSI
+RCC.USART1Freq_Value=16000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=32000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/MDK-ARM/LPUART_WakeUpFromStop2_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/MDK-ARM/LPUART_WakeUpFromStop2_Init.uvoptx
new file mode 100644
index 000000000..c55f00591
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/MDK-ARM/LPUART_WakeUpFromStop2_Init.uvoptx
@@ -0,0 +1,369 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    LPUART_WakeUpFromStop2_Init
+    0x4
+    ARM-ADS
+    
+      16000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      4
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      4
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lpuart.c
+      stm32wbxx_ll_lpuart.c
+      0
+      0
+    
+    
+      4
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+      stm32wbxx_ll_rcc.c
+      0
+      0
+    
+    
+      4
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      stm32wbxx_ll_dma.c
+      0
+      0
+    
+    
+      4
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      5
+      12
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/MDK-ARM/LPUART_WakeUpFromStop2_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/MDK-ARM/LPUART_WakeUpFromStop2_Init.uvprojx
new file mode 100644
index 000000000..4260ca574
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/MDK-ARM/LPUART_WakeUpFromStop2_Init.uvprojx
@@ -0,0 +1,487 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      LPUART_WakeUpFromStop2_Init
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          LPUART_WakeUpFromStop2_Init\
+          LPUART_WakeUpFromStop2_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_lpuart.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lpuart.c
+            
+            
+              stm32wbxx_ll_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+            
+            
+              stm32wbxx_ll_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..4d3c33012
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..986821f57
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/.project
@@ -0,0 +1,95 @@
+
+
+	LPUART_WakeUpFromStop2_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			LPUART_WakeUpFromStop2_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/LPUART_WakeUpFromStop2_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_lpuart.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lpuart.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Src/main.c
new file mode 100644
index 000000000..631512f16
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Src/main.c
@@ -0,0 +1,532 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to configure LPUART peripheral in Asynchronous mode
+  *          for being able to wake from Stop 2 mode when a character is received on RX line using
+  *          the STM32WBxx LPUART LL API.
+  *          Peripheral initialization done using LL initialization function.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/**
+  * @brief Variables used for charcater reception from PC Com port
+  */
+__IO uint8_t      ubFinalCharReceived = 0;
+__IO uint32_t     ubReceivedChar;
+
+/**
+  * @brief Text string printed on PC Com port to inform MCU will enter in Stop 2 Mode
+  */
+uint8_t aTextInfo[] = "\r\nLPUART Example : MCU will now enter in Stop 2 mode.\n\rEnter any character for waking up MCU.\r\n";
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_LPUART1_UART_Init(void);
+/* USER CODE BEGIN PFP */
+void     LED_On(void);
+void     LED_Off(void);
+void     LED_Blinking(uint32_t Period);
+void     LED_Blinking_3s(void);
+void     Configure_PWR(void);
+void     PrepareLPUARTToStopMode(void);
+void     EnterSTOP2Mode(void);
+void     PrintInfo(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_LPUART1_UART_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Configure Power IP */
+  Configure_PWR();
+
+  /* Start main program loop :
+     - make LED blink during 3 sec
+     - Enter Stop 2 mode (LED turned Off)
+     - Wait for any character received on LPUART RX line for waking up MCU
+  */
+  while (ubFinalCharReceived == 0)
+  {
+    /* LED blinks during 3 seconds */
+    LED_Blinking_3s();
+
+    /* Send Text Information on LPUART TX to PC Com port */
+    PrintInfo();
+
+    /* Prepare LPUART for entering Stop Mode */
+    PrepareLPUARTToStopMode();
+
+    /* Enter Stop 2 mode */
+    EnterSTOP2Mode();
+
+    /* At this point, MCU just wakes up from Stop 2 mode */
+  }
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  /* HSI configuration and activation */
+  LL_RCC_HSI_Enable();
+  while(LL_RCC_HSI_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the HSI */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(16000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(16000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief LPUART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_LPUART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN LPUART1_Init 0 */
+
+  /* USER CODE END LPUART1_Init 0 */
+
+  LL_LPUART_InitTypeDef LPUART_InitStruct = {0};
+
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* Peripheral clock enable */
+  LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPUART1);
+  
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  /**LPUART1 GPIO Configuration  
+  PA2   ------> LPUART1_TX
+  PA3   ------> LPUART1_RX 
+  */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_2|LL_GPIO_PIN_3;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_8;
+  LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* LPUART1 interrupt Init */
+  NVIC_SetPriority(LPUART1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(LPUART1_IRQn);
+
+  /* USER CODE BEGIN LPUART1_Init 1 */
+
+  /* Set LPUART1 clock source as HSI */
+  LL_RCC_SetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE_HSI);
+
+  /* USER CODE END LPUART1_Init 1 */
+  LPUART_InitStruct.PrescalerValue = LL_LPUART_PRESCALER_DIV1;
+  LPUART_InitStruct.BaudRate = 9600;
+  LPUART_InitStruct.DataWidth = LL_LPUART_DATAWIDTH_8B;
+  LPUART_InitStruct.StopBits = LL_LPUART_STOPBITS_1;
+  LPUART_InitStruct.Parity = LL_LPUART_PARITY_NONE;
+  LPUART_InitStruct.TransferDirection = LL_LPUART_DIRECTION_TX_RX;
+  LPUART_InitStruct.HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
+  LL_LPUART_Init(LPUART1, &LPUART_InitStruct);
+  LL_LPUART_SetTXFIFOThreshold(LPUART1, LL_LPUART_FIFOTHRESHOLD_1_8);
+  LL_LPUART_SetRXFIFOThreshold(LPUART1, LL_LPUART_FIFOTHRESHOLD_1_8);
+
+  /* USER CODE BEGIN WKUPType LPUART1 */
+  /* Set the wake-up event type : specify wake-up on RXNE flag */
+  LL_LPUART_SetWKUPType(LPUART1, LL_LPUART_WAKEUP_ON_RXNE);
+
+  /* USER CODE END WKUPType LPUART1 */
+
+  LL_LPUART_Enable(LPUART1);
+
+  /* Polling LPUART1 initialisation */
+  while((!(LL_LPUART_IsActiveFlag_TEACK(LPUART1))) || (!(LL_LPUART_IsActiveFlag_REACK(LPUART1))))
+  {
+  }
+  /* USER CODE BEGIN LPUART1_Init 2 */
+
+  /* USER CODE END LPUART1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Function to configure and initialize PWR IP.
+  * @param  None
+  * @retval None
+  */
+void Configure_PWR(void)
+{
+  /* Ensure that HSI is wake-up system clock */
+  LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
+}
+
+/**
+  * @brief  Function to configure LPUART for being ready to enter "Stop 2" mode.
+  * @param  None
+  * @retval None
+  */
+void PrepareLPUARTToStopMode(void)
+{
+
+  /* Empty RX Fifo before entering Stop mode (Otherwise, characters already present in FIFO
+     will lead to immediate wake up */
+  while (LL_LPUART_IsActiveFlag_RXNE(LPUART1))
+  {
+    /* Read Received character. RXNE flag is cleared by reading of RDR register */
+    ubReceivedChar = LL_LPUART_ReceiveData8(LPUART1);
+  }
+
+  /* Clear OVERRUN flag */
+  LL_LPUART_ClearFlag_ORE(LPUART1);
+
+  /* Make sure that no LPUART transfer is on-going */
+  while (LL_LPUART_IsActiveFlag_BUSY(LPUART1) == 1)
+  {
+  }
+  /* Make sure that LPUART is ready to receive */
+  while (LL_LPUART_IsActiveFlag_REACK(LPUART1) == 0)
+  {
+  }
+
+  /* About to enter stop mode: switch off LED */
+  LED_Off();
+
+  /* Configure LPUART1 transfer interrupts : */
+  /* Clear WUF flag and enable the UART Wake Up from stop mode Interrupt */
+  LL_LPUART_ClearFlag_WKUP(LPUART1);
+  LL_LPUART_EnableIT_WKUP(LPUART1);
+
+  /* Enable Wake Up From Stop */
+  LL_LPUART_EnableInStopMode(LPUART1);
+
+}
+
+/**
+  * @brief  Function to enter in "Stop 2" mode.
+  * @param  None
+  * @retval None
+  */
+void EnterSTOP2Mode(void)
+{
+  /** Request to enter "Stop 2" mode
+    * Following procedure describe in STM32WBxx Reference Manual
+    * See PWR part, section Low-power modes, "Stop 2" mode
+    */
+  /* Set Stop 2 mode when CPU enters deepsleep */
+  LL_PWR_SetPowerMode(LL_PWR_MODE_STOP2);
+
+  /* Set low-power mode STOP of CPU2 */
+  /* Note: On STM32WB, both CPU1 and CPU2 must be in "Stop 2" mode to set the entire system in Stop 2 mode */
+  LL_C2_PWR_SetPowerMode(LL_PWR_MODE_STOP2);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  LL_LPM_EnableDeepSleep();
+
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/**
+  * @brief  Send Txt information message on LPUART Tx line (to PC Com port).
+  * @param  None
+  * @retval None
+  */
+void PrintInfo(void)
+{
+  uint32_t index = 0;
+
+  /* Send characters one per one, until last char to be sent */
+  for (index = 0; index < sizeof(aTextInfo); index++)
+  {
+    /* Wait for TXE flag to be raised */
+    while (!LL_LPUART_IsActiveFlag_TXE(LPUART1))
+    {
+    }
+
+    /* Write character in Transmit Data register.
+       TXE flag is cleared by writing data in TDR register */
+    LL_LPUART_TransmitData8(LPUART1, aTextInfo[index]);
+  }
+
+  /* Wait for TC flag to be raised for last char */
+  while (!LL_LPUART_IsActiveFlag_TC(LPUART1))
+  {
+  }
+}
+
+/**
+  * @brief  Turn-on LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_On(void)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Turn-off LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_Off(void)
+{
+  /* Turn LED2 off */
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
+  * @param  Period : Period of time (in ms) between each toggling of LED
+  *   This parameter can be user defined values. Pre-defined values used in that example are :
+  *     @arg LED_BLINK_FAST : Fast Blinking
+  *     @arg LED_BLINK_SLOW : Slow Blinking
+  *     @arg LED_BLINK_ERROR : Error specific Blinking
+  * @retval None
+  */
+void LED_Blinking(uint32_t Period)
+{
+  /* Toggle IO in an infinite loop */
+  while (1)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+    LL_mDelay(Period);
+  }
+}
+
+/**
+  * @brief  Set LED2 to Blinking mode during 3s.
+  * @param  None
+  * @retval None
+  */
+void LED_Blinking_3s(void)
+{
+  uint32_t index = 0;
+
+  /* Toggle IO in during 3s (15*200ms) */
+  for (index = 0; index < 15; index++)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+    LL_mDelay(200);
+  }
+}
+
+/******************************************************************************/
+/*   IRQ HANDLER TREATMENT Functions                                          */
+/******************************************************************************/
+
+/**
+  * @brief  Function called from LPUART IRQ Handler when RXNE flag is set
+  *         Function is in charge of reading character received on LPUART RX line.
+  * @param  None
+  * @retval None
+  */
+void LPUART_CharReception_Callback(void)
+{
+  /* Read Received character. RXNE flag is cleared by reading of RDR register */
+  ubReceivedChar = LL_LPUART_ReceiveData8(LPUART1);
+
+  /* Check if received value is corresponding to specific one : S or s */
+  if ((ubReceivedChar == 'S') || (ubReceivedChar == 's'))
+  {
+    /* Turn LED2 On : Expected character has been received */
+    LED_On();
+
+    /* End of program : set boolean for main loop exit */
+    ubFinalCharReceived = 1;
+  }
+
+  /* Echo received character on TX */
+  LL_LPUART_TransmitData8(LPUART1, ubReceivedChar);
+}
+
+/**
+  * @brief  Function called in case of error detected in LPUART IT Handler
+  * @param  None
+  * @retval None
+  */
+void Error_Callback(void)
+{
+  /* Disable LPUART1_IRQn */
+  NVIC_DisableIRQ(LPUART1_IRQn);
+
+  /* Unexpected event : Set LED2 to Blinking mode to indicate error occurs */
+  LED_Blinking(LED_BLINK_ERROR);
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..4d4ad1e23
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,237 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles LPUART1 global interrupt.
+  */
+void LPUART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN LPUART1_IRQn 0 */
+  /* Check WUF flag value in ISR register */
+  if (LL_LPUART_IsActiveFlag_WKUP(LPUART1) && LL_LPUART_IsEnabledIT_WKUP(LPUART1))
+  {
+    /* Configure LPUART1 transfer interrupts : */
+    /* Disable the UART Wake UP from stop mode Interrupt */
+    LL_LPUART_DisableIT_WKUP(LPUART1);
+
+    /* WUF flag clearing */
+    LL_LPUART_ClearFlag_WKUP(LPUART1);
+
+    /* Call function in charge of handling Character reception */
+    LPUART_CharReception_Callback();
+  }
+  else
+  {
+    /* Call Error function */
+    Error_Callback();
+  }
+  /* USER CODE END LPUART1_IRQn 0 */
+  /* USER CODE BEGIN LPUART1_IRQn 1 */
+
+  /* USER CODE END LPUART1_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/readme.txt
new file mode 100644
index 000000000..fe495857d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/readme.txt
@@ -0,0 +1,78 @@
+/**
+  @page LPUART_WakeUpFromStop2_Init LPUART example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/LPUART/LPUART_WakeUpFromStop2_Init/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the LPUART_WakeUpFromStop2_Init LPUART example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+  
+Configuration of GPIO and LPUART peripherals to allow characters 
+received on LPUART_RX pin to wake up the MCU from low-power mode. This example is based 
+on the LPUART LL API. The peripheral initialization uses LL 
+initialization function to demonstrate LL init usage.
+
+LPUART Peripheral is configured in asynchronous mode (9600 bauds, 8 data bit, 1 start bit, 1 stop bit, no parity).
+No HW flow control is used.
+LPUART Clock is based on HSI.
+
+Example execution:
+After startup from reset and system configuration, LED2 is blinking quickly during 3 sec,
+then MCU  enters "Stop 2" mode (LED2 off).
+On first  character reception by the LPUART from PC Com port (ex: using HyperTerminal)
+after "Stop 2" Mode period, MCU wakes up from "Stop 2" Mode.
+Received character value is checked :
+- On a specific value ('S' or 's'), LED2 is turned On and program ends.
+- If different from 'S' or 's', program performs a quick LED2 blinks during 3 sec and 
+  enters again "Stop 2" mode, waiting for next character to wake up.
+
+In case of errors, LED2 is slowly blinking (1 sec period).
+
+@par Directory contents 
+
+  - LPUART/LPUART_WakeUpFromStop2_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - LPUART/LPUART_WakeUpFromStop2_Init/Inc/main.h                  Header for main.c module
+  - LPUART/LPUART_WakeUpFromStop2_Init/Inc/stm32_assert.h          Template file to include assert_failed function
+  - LPUART/LPUART_WakeUpFromStop2_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - LPUART/LPUART_WakeUpFromStop2_Init/Src/main.c                  Main program
+  - LPUART/LPUART_WakeUpFromStop2_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+  - NUCLEO-WB35CE Set-up
+    - Connect STM32 MCU board LPUART1 TX pin (GPIO PA2 connected to pin 36 of CN7 connector)
+      to PC COM port RX signal
+    - Connect STM32 MCU board LPUART1 RX pin (GPIO PA3 connected to pin 38 of CN7 connector)
+      to PC COM port TX signal
+    - Connect STM32 MCU board GND to PC COM port GND signal
+
+    - Launch serial communication SW on PC (as HyperTerminal or TeraTerm) with proper configuration 
+      (9600 bauds, 8 bits data, 1 stop bit, no parity, no HW flow control). 
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/.extSettings
new file mode 100644
index 000000000..302b44c8c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Application/User=../Src/main.c;../Src/stm32wbxx_it.c;../Src/prime256v1.c;../Src/SigGen.c;
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewd
new file mode 100644
index 000000000..e141a43a6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		PKA_ECDSA_Sign
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewp
new file mode 100644
index 000000000..8aa1c4cea
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/PKA_ECDSA_Sign.ewp
@@ -0,0 +1,1092 @@
+
+
+  3
+  
+    PKA_ECDSA_Sign
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/prime256v1.c
+      
+      
+        $PROJ_DIR$/../Src/SigGen.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pka.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/Project.eww
new file mode 100644
index 000000000..78da88b19
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\PKA_ECDSA_Sign.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/stm32wb35xx_sram_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/stm32wb35xx_sram_cm4.icf
new file mode 100644
index 000000000..6426355fb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/EWARM/stm32wb35xx_sram_cm4.icf
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20003FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20004000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20008000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x2000FFFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/SigGen.h b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/SigGen.h
new file mode 100644
index 000000000..8309ef30d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/SigGen.h
@@ -0,0 +1,51 @@
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Sign/Inc/SigGen.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of SigGen.c .
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __SIGGEN_H
+#define __SIGGEN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const uint8_t  SigGen_Msg[];
+extern const uint32_t SigGen_Msg_len;
+extern const uint8_t  SigGen_Hash_Msg[];
+extern const uint32_t SigGen_Hash_Msg_len;
+extern const uint8_t  SigGen_d[];
+extern const uint32_t SigGen_d_len;
+extern const uint8_t  SigGen_Qx[];
+extern const uint32_t SigGen_Qx_len;
+extern const uint8_t  SigGen_Qy[];
+extern const uint32_t SigGen_Qy_len;
+extern const uint8_t  SigGen_k[];
+extern const uint32_t SigGen_k_len;
+extern const uint8_t  SigGen_R[];
+extern const uint32_t SigGen_R_len;
+extern const uint8_t  SigGen_S[];
+extern const uint32_t SigGen_S_len;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SIGGEN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/main.h
new file mode 100644
index 000000000..61ad1aeb9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/main.h
@@ -0,0 +1,109 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/PKA/PKA_ECDSA_Sign/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_pka.h"
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+#include "SigGen.h"
+#include "prime256v1.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* Toggle periods for various blinking modes */
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW  500
+#define LED_BLINK_ERROR 1000
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+void PKA_ERROR_callback(void);
+void PKA_PROCEND_callback(void);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/prime256v1.h b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/prime256v1.h
new file mode 100644
index 000000000..de2fff994
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/prime256v1.h
@@ -0,0 +1,54 @@
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Sign/Inc/PKV.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of prime256v1.c .
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PRIME256V1_H
+#define __PRIME256V1_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const uint8_t  prime256v1_Prime[];
+extern const uint32_t prime256v1_Prime_len;
+extern const uint8_t  prime256v1_A[];
+extern const uint8_t  prime256v1_absA[];
+extern const uint32_t prime256v1_A_len;
+extern const uint32_t prime256v1_A_sign;
+extern const uint8_t  prime256v1_B[];
+extern const uint32_t prime256v1_B_len;
+extern const uint8_t  prime256v1_Generator[];
+extern const uint32_t prime256v1_Generator_len;
+extern const uint8_t  prime256v1_GeneratorX[];
+extern const uint32_t prime256v1_GeneratorX_len;
+extern const uint8_t  prime256v1_GeneratorY[];
+extern const uint32_t prime256v1_GeneratorY_len;
+extern const uint8_t  prime256v1_Order[];
+extern const uint32_t prime256v1_Order_len;
+extern const uint32_t prime256v1_Cofactor;
+extern const uint8_t  prime256v1_Seed[];
+extern const uint32_t prime256v1_Seed_len;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PRIME256V1_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..647bd3679
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_it.h
@@ -0,0 +1,73 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+void PKA_ERROR_callback(void);
+void PKA_PROCEND_callback(void);
+void PKA_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvoptx
new file mode 100644
index 000000000..66e3035f8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvoptx
@@ -0,0 +1,369 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    PKA_ECDSA_Sign
+    0x4
+    ARM-ADS
+    
+      16000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/prime256v1.c
+      prime256v1.c
+      0
+      0
+    
+    
+      3
+      5
+      1
+      0
+      0
+      0
+      ../Src/SigGen.c
+      SigGen.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      6
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pka.c
+      stm32wbxx_ll_pka.c
+      0
+      0
+    
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvprojx
new file mode 100644
index 000000000..dfe0588f6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/MDK-ARM/PKA_ECDSA_Sign.uvprojx
@@ -0,0 +1,486 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      PKA_ECDSA_Sign
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          PKA_ECDSA_Sign\
+          PKA_ECDSA_Sign
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              prime256v1.c
+              1
+              ../Src/prime256v1.c
+            
+            
+              SigGen.c
+              1
+              ../Src/SigGen.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_pka.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pka.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/PKA_ECDSA_Sign.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/PKA_ECDSA_Sign.ioc
new file mode 100644
index 000000000..83edeed6b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/PKA_ECDSA_Sign.ioc
@@ -0,0 +1,112 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=PKA
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB0
+Mcu.Pin1=VP_PKA_VS_PKA
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=PKA_ECDSA_Sign.ioc
+ProjectManager.ProjectName=PKA_ECDSA_Sign
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-true,3-MX_PKA_Init-PKA-false-LL-true
+RCC.AHBFreq_Value=16000000
+RCC.APB1Freq_Value=16000000
+RCC.APB1TimFreq_Value=16000000
+RCC.APB2Freq_Value=16000000
+RCC.APB2TimFreq_Value=16000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=16000000
+RCC.CortexFreq_Value=16000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=16000000
+RCC.FCLKCortexFreq_Value=16000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=16000000
+RCC.HCLK3Freq_Value=16000000
+RCC.HCLKFreq_Value=16000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=16000000
+RCC.I2C3Freq_Value=16000000
+RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=16000000
+RCC.LPTIM2Freq_Value=16000000
+RCC.LPUART1Freq_Value=16000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=16000000
+RCC.PLLPoutputFreq_Value=16000000
+RCC.PLLQoutputFreq_Value=16000000
+RCC.PLLRCLKFreq_Value=16000000
+RCC.PWRFreq_Value=16000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=16000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_HSI
+RCC.USART1Freq_Value=16000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=32000000
+VP_PKA_VS_PKA.Mode=PKA_Activate
+VP_PKA_VS_PKA.Signal=PKA_VS_PKA
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..659fc6b38
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/.project
new file mode 100644
index 000000000..ae0f6dd45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/.project
@@ -0,0 +1,95 @@
+
+
+	PKA_ECDSA_Sign
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			PKA_ECDSA_Sign.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/PKA_ECDSA_Sign.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/SigGen.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/SigGen.c
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/prime256v1.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/prime256v1.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pka.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pka.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/SigGen.c b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/SigGen.c
new file mode 100644
index 000000000..17e05c36c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/SigGen.c
@@ -0,0 +1,97 @@
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Sign/Src/SigGen.c
+  * @author  MCD Application Team
+  * @brief   This file contains reference buffers from 
+  *          NIST Cryptographic Algorithm Validation Program (CAVP).
+  *          (http://csrc.nist.gov/groups/STM/cavp/)
+  *          1 test vector is extracted to demonstrate PKA capability to
+  *          sign a message using ECDSA (Elliptic Curve Digital Signature Algorithm) 
+  *          signature generation function principle.
+  *          It is adapted from SigGen.txt section [P-256,SHA-256] available under
+  *          http://csrc.nist.gov/groups/STM/cavp/documents/dss/186-3ecdsatestvectors.zip
+  *          and provided in the same directory for reference.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+  
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/*
+  Adapted from
+  [P-256,SHA-256]
+  Msg = 5905238877c77421f73e43ee3da6f2d9e2ccad5fc942dcec0cbd25482935faaf416983fe165b1a045ee2bcd2e6dca3bdf46c4310a7461f9a37960ca672d3feb5473e253605fb1ddfd28065b53cb5858a8ad28175bf9bd386a5e471ea7a65c17cc934a9d791e91491eb3754d03799790fe2d308d16146d5c9b0d0debd97d79ce8
+  d = 519b423d715f8b581f4fa8ee59f4771a5b44c8130b4e3eacca54a56dda72b464
+  Qx = 1ccbe91c075fc7f4f033bfa248db8fccd3565de94bbfb12f3c59ff46c271bf83
+  Qy = ce4014c68811f9a21a1fdb2c0e6113e06db7ca93b7404e78dc7ccd5ca89a4ca9
+  k = 94a1bbb14b906a61a280f245f9e93c7f3b4a6247824f5d33b9670787642a68de
+  R = f3ac8061b514795b8843e3d6629527ed2afd6b1f6a555a7acabb5e6f79c8c2ac
+  S = 8bf77819ca05a6b2786c76262bf7371cef97b218e96f175a3ccdda2acc058903
+*/
+
+const uint8_t SigGen_Msg[] = {
+  0x59, 0x05, 0x23, 0x88, 0x77, 0xc7, 0x74, 0x21, 0xf7, 0x3e, 0x43, 0xee, 0x3d, 0xa6, 0xf2, 0xd9,
+  0xe2, 0xcc, 0xad, 0x5f, 0xc9, 0x42, 0xdc, 0xec, 0x0c, 0xbd, 0x25, 0x48, 0x29, 0x35, 0xfa, 0xaf,
+  0x41, 0x69, 0x83, 0xfe, 0x16, 0x5b, 0x1a, 0x04, 0x5e, 0xe2, 0xbc, 0xd2, 0xe6, 0xdc, 0xa3, 0xbd,
+  0xf4, 0x6c, 0x43, 0x10, 0xa7, 0x46, 0x1f, 0x9a, 0x37, 0x96, 0x0c, 0xa6, 0x72, 0xd3, 0xfe, 0xb5,
+  0x47, 0x3e, 0x25, 0x36, 0x05, 0xfb, 0x1d, 0xdf, 0xd2, 0x80, 0x65, 0xb5, 0x3c, 0xb5, 0x85, 0x8a,
+  0x8a, 0xd2, 0x81, 0x75, 0xbf, 0x9b, 0xd3, 0x86, 0xa5, 0xe4, 0x71, 0xea, 0x7a, 0x65, 0xc1, 0x7c,
+  0xc9, 0x34, 0xa9, 0xd7, 0x91, 0xe9, 0x14, 0x91, 0xeb, 0x37, 0x54, 0xd0, 0x37, 0x99, 0x79, 0x0f,
+  0xe2, 0xd3, 0x08, 0xd1, 0x61, 0x46, 0xd5, 0xc9, 0xb0, 0xd0, 0xde, 0xbd, 0x97, 0xd7, 0x9c, 0xe8
+};
+const uint32_t SigGen_Msg_len = 128;
+
+/* Result of hashing SigGen_Msg (You can verify using "openssl dgst -sha256" or "sha256sum" utilities)*/
+const uint8_t SigGen_Hash_Msg[] = {
+  0x44, 0xac, 0xf6, 0xb7, 0xe3, 0x6c, 0x13, 0x42, 0xc2, 0xc5, 0x89, 0x72, 0x04, 0xfe, 0x09, 0x50, 
+  0x4e, 0x1e, 0x2e, 0xfb, 0x1a, 0x90, 0x03, 0x77, 0xdb, 0xc4, 0xe7, 0xa6, 0xa1, 0x33, 0xec, 0x56
+};
+const uint32_t SigGen_Hash_Msg_len = 32;
+
+const uint8_t SigGen_d[] = {
+  0x51, 0x9b, 0x42, 0x3d, 0x71, 0x5f, 0x8b, 0x58, 0x1f, 0x4f, 0xa8, 0xee, 0x59, 0xf4, 0x77, 0x1a,
+  0x5b, 0x44, 0xc8, 0x13, 0x0b, 0x4e, 0x3e, 0xac, 0xca, 0x54, 0xa5, 0x6d, 0xda, 0x72, 0xb4, 0x64
+};
+const uint32_t SigGen_d_len = 32;
+
+const uint8_t SigGen_Qx[] = {
+  0x1c, 0xcb, 0xe9, 0x1c, 0x07, 0x5f, 0xc7, 0xf4, 0xf0, 0x33, 0xbf, 0xa2, 0x48, 0xdb, 0x8f, 0xcc,
+  0xd3, 0x56, 0x5d, 0xe9, 0x4b, 0xbf, 0xb1, 0x2f, 0x3c, 0x59, 0xff, 0x46, 0xc2, 0x71, 0xbf, 0x83
+};
+const uint32_t SigGen_Qx_len = 32;
+
+const uint8_t SigGen_Qy[] = {
+  0xce, 0x40, 0x14, 0xc6, 0x88, 0x11, 0xf9, 0xa2, 0x1a, 0x1f, 0xdb, 0x2c, 0x0e, 0x61, 0x13, 0xe0,
+  0x6d, 0xb7, 0xca, 0x93, 0xb7, 0x40, 0x4e, 0x78, 0xdc, 0x7c, 0xcd, 0x5c, 0xa8, 0x9a, 0x4c, 0xa9
+};
+const uint32_t SigGen_Qy_len = 32;
+
+const uint8_t SigGen_k[] = {
+  0x94, 0xa1, 0xbb, 0xb1, 0x4b, 0x90, 0x6a, 0x61, 0xa2, 0x80, 0xf2, 0x45, 0xf9, 0xe9, 0x3c, 0x7f,
+  0x3b, 0x4a, 0x62, 0x47, 0x82, 0x4f, 0x5d, 0x33, 0xb9, 0x67, 0x07, 0x87, 0x64, 0x2a, 0x68, 0xde
+};
+const uint32_t SigGen_k_len = 32;
+
+const uint8_t SigGen_R[] = {
+  0xf3, 0xac, 0x80, 0x61, 0xb5, 0x14, 0x79, 0x5b, 0x88, 0x43, 0xe3, 0xd6, 0x62, 0x95, 0x27, 0xed,
+  0x2a, 0xfd, 0x6b, 0x1f, 0x6a, 0x55, 0x5a, 0x7a, 0xca, 0xbb, 0x5e, 0x6f, 0x79, 0xc8, 0xc2, 0xac
+};
+const uint32_t SigGen_R_len = 32;
+
+const uint8_t SigGen_S[] = {
+  0x8b, 0xf7, 0x78, 0x19, 0xca, 0x05, 0xa6, 0xb2, 0x78, 0x6c, 0x76, 0x26, 0x2b, 0xf7, 0x37, 0x1c,
+  0xef, 0x97, 0xb2, 0x18, 0xe9, 0x6f, 0x17, 0x5a, 0x3c, 0xcd, 0xda, 0x2a, 0xcc, 0x05, 0x89, 0x03
+};
+const uint32_t SigGen_S_len = 32;
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/SigGen.txt b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/SigGen.txt
new file mode 100644
index 000000000..35cf1daa6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/SigGen.txt
@@ -0,0 +1,5878 @@
+#  CAVS 11.2
+#  "SigVer" information for "ecdsa_values"
+#  Curves/SHAs selected: P-224,SHA-224 P-224,SHA-256 P-224,SHA-384 P-224,SHA-512 P-256,SHA-224 P-256,SHA-256 P-256,SHA-384 P-256,SHA-512 P-384,SHA-224 P-384,SHA-256 P-384,SHA-384 P-384,SHA-512 P-521,SHA-224 P-521,SHA-256 P-521,SHA-384 P-521,SHA-512 K-233,SHA-224 K-233,SHA-256 K-233,SHA-384 K-233,SHA-512 K-283,SHA-224 K-283,SHA-256 K-283,SHA-384 K-283,SHA-512 K-409,SHA-224 K-409,SHA-256 K-409,SHA-384 K-409,SHA-512 K-571,SHA-224 K-571,SHA-256 K-571,SHA-384 K-571,SHA-512 B-233,SHA-224 B-233,SHA-256 B-233,SHA-384 B-233,SHA-512 B-283,SHA-224 B-283,SHA-256 B-283,SHA-384 B-283,SHA-512 B-409,SHA-224 B-409,SHA-256 B-409,SHA-384 B-409,SHA-512 BB-571,SHA-224 B-571,SHA-256 B-571,SHA-384 B-571,SHA-512
+#  Generated on Tue Aug 16 15:27:42 2011
+
+
+
+
+[P-224,SHA-224]
+
+Msg = 699325d6fc8fbbb4981a6ded3c3a54ad2e4e3db8a5669201912064c64e700c139248cdc19495df081c3fc60245b9f25fc9e301b845b3d703a694986e4641ae3c7e5a19e6d6edbf1d61e535f49a8fad5f4ac26397cfec682f161a5fcd32c5e780668b0181a91955157635536a22367308036e2070f544ad4fff3d5122c76fad5d
+d = 16797b5c0c7ed5461e2ff1b88e6eafa03c0f46bf072000dfc830d615
+Qx = 605495756e6e88f1d07ae5f98787af9b4da8a641d1a9492a12174eab
+Qy = f5cc733b17decc806ef1df861a42505d0af9ef7c3df3959b8dfc6669
+k = d9a5a7328117f48b4b8dd8c17dae722e756b3ff64bd29a527137eec0
+R = 2fc2cff8cdd4866b1d74e45b07d333af46b7af0888049d0fdbc7b0d6
+S = 8d9cc4c8ea93e0fd9d6431b9a1fd99b88f281793396321b11dac41eb
+
+Msg = 7de42b44db0aa8bfdcdac9add227e8f0cc7ad1d94693beb5e1d325e5f3f85b3bd033fc25e9469a89733a65d1fa641f7e67d668e7c71d736233c4cba20eb83c368c506affe77946b5e2ec693798aecd7ff943cd8fab90affddf5ad5b8d1af332e6c5fe4a2df16837700b2781e08821d4fbdd8373517f5b19f9e63b89cfeeeef6f
+d = cf020a1ff36c28511191482ed1e5259c60d383606c581948c3fbe2c5
+Qx = fa21f85b99d3dc18c6d53351fbcb1e2d029c00fa7d1663a3dd94695e
+Qy = e9e79578f8988b168edff1a8b34a5ed9598cc20acd1f0aed36715d88
+k = c780d047454824af98677cf310117e5f9e99627d02414f136aed8e83
+R = 45145f06b566ec9fd0fee1b6c6551a4535c7a3bbfc0fede45f4f5038
+S = 7302dff12545b069cf27df49b26e4781270585463656f2834917c3ca
+
+Msg = af0da3adab82784909e2b3dadcecba21eced3c60d7572023dea171044d9a10e8ba67d31b04904541b87fff32a10ccc6580869055fec6216a00320a28899859a6b61faba58a0bc10c2ba07ea16f214c3ddcc9fc5622ad1253b63fe7e95227ae3c9caa9962cffc8b1c4e8260036469d25ab0c8e3643a820b8b3a4d8d43e4b728f9
+d = dde6f173fa9f307d206ce46b4f02851ebce9638a989330249fd30b73
+Qx = fc21a99b060afb0d9dbf3250ea3c4da10be94ce627a65874d8e4a630
+Qy = e8373ab7190890326aac4aacca3eba89e15d1086a05434dd033fd3f3
+k = 6629366a156840477df4875cfba4f8faa809e394893e1f5525326d07
+R = 41f8e2b1ae5add7c24da8725a067585a3ad6d5a9ed9580beb226f23a
+S = a5d71bff02dce997305dd337128046f36714398f4ef6647599712fae
+
+Msg = cfa56ae89727df6b7266f69d6636bf738f9e4f15f49c42a0123edac4b3743f32ea52389f919ceb90575c4184897773b2f2fc5b3fcb354880f15c93383215d3c2551fcc1b4180a1ac0f69c969bbc306acd115ce3976eff518540f43ad4076dbb5fbad9ce9b3234f1148b8f5e059192ff480fc4bcbd00d25f4d9f5ed4ba5693b6c
+d = aeee9071248f077590ac647794b678ad371f8e0f1e14e9fbff49671e
+Qx = fad0a34991bbf89982ad9cf89337b4bd2565f84d5bdd004289fc1cc3
+Qy = 5d8b6764f28c8163a12855a5c266efeb9388df4994b85a8b4f1bd3bc
+k = 1d35d027cd5a569e25c5768c48ed0c2b127c0f99cb4e52ea094fe689
+R = 2258184ef9f0fa698735379972ce9adf034af76017668bfcdab978de
+S = 866fb8e505dea6c909c2c9143ec869d1bac2282cf12366130ff2146c
+
+Msg = c223c8009018321b987a615c3414d2bb15954933569ca989de32d6bf11107bc47a330ab6d88d9b50d106cf5777d1b736b14bc48deda1bc573a9a7dd42cd061860645306dce7a5ba8c60f135a6a21999421ce8c4670fe7287a7e9ea3aa1e0fa82721f33e6e823957fe86e2283c89ef92b13cd0333c4bb70865ae1919bf538ea34
+d = 29c204b2954e1406a015020f9d6b3d7c00658298feb2d17440b2c1a4
+Qx = 0e0fc15e775a75d45f872e5021b554cc0579da19125e1a49299c7630
+Qy = cb64fe462d025ae2a1394746bdbf8251f7ca5a1d6bb13e0edf6b7b09
+k = 39547c10bb947d69f6c3af701f2528e011a1e80a6d04cc5a37466c02
+R = 86622c376d326cdf679bcabf8eb034bf49f0c188f3fc3afd0006325d
+S = 26613d3b33c70e635d7a998f254a5b15d2a3642bf321e8cff08f1e84
+
+Msg = 1c27273d95182c74c100d85b5c08f4b26874c2abc87f127f304aedbf52ef6540eba16dd664ae1e9e30ea1e66ff9cc9ab5a80b5bcbd19dde88a29ff10b50a6abd73388e8071306c68d0c9f6caa26b7e68de29312be959b9f4a5481f5a2ad2070a396ed3de21096541cf58c4a13308e08867565bf2df9d649357a83cdcf18d2cd9
+d = 8986a97b24be042a1547642f19678de4e281a68f1e794e343dabb131
+Qx = 2c070e68e8478341938f3d5026a1fe01e778cdffbebbdd7a4cd29209
+Qy = cde21c9c7c6590ba300715a7adac278385a5175b6b4ea749c4b6a681
+k = 509712f9c0f3370f6a09154159975945f0107dd1cee7327c68eaa90b
+R = 57afda5139b180de96373c3d649700682e37efd56ae182335f081013
+S = eb6cd58650cfb26dfdf21de32fa17464a6efc46830eedc16977342e6
+
+Msg = 069ae374971627f6b8503f3aa63ab52bcf4f3fcae65b98cdbbf917a5b08a10dc760056714db279806a8d43485320e6fee0f1e0562e077ee270ace8d3c478d79bcdff9cf8b92fdea68421d4a276f8e62ae379387ae06b60af9eb3c40bd7a768aeffccdc8a08bc78ca2eca18061058043a0e441209c5c594842838a4d9d778a053
+d = d9aa95e14cb34980cfddadddfa92bde1310acaff249f73ff5b09a974
+Qx = 3a0d4b8e5fad1ea1abb8d3fb742cd45cd0b76d136e5bbb33206ad120
+Qy = c90ac83276b2fa3757b0f226cd7360a313bc96fd8329c76a7306cc7d
+k = 1f1739af68a3cee7c5f09e9e09d6485d9cd64cc4085bc2bc89795aaf
+R = 09bbdd003532d025d7c3204c00747cd52ecdfbc7ce3dde8ffbea23e1
+S = 1e745e80948779a5cc8dc5cb193beebb550ec9c2647f4948bf58ba7d
+
+Msg = d0d5ae3e33600aa21c1606caec449eee678c87cb593594be1fbb048cc7cfd076e5cc7132ebe290c4c014e7a517a0d5972759acfa1438d9d2e5d236d19ac92136f6252b7e5bea7588dcba6522b6b18128f003ecab5cb4908832fb5a375cf820f8f0e9ee870653a73dc2282f2d45622a2f0e85cba05c567baf1b9862b79a4b244e
+d = 380fb6154ad3d2e755a17df1f047f84712d4ec9e47d34d4054ea29a8
+Qx = 4772c27cca3348b1801ae87b01cb564c8cf9b81c23cc74468a907927
+Qy = de9d253935b09617a1655c42d385bf48504e06fa386f5fa533a21dcb
+k = 14dbdffa326ba2f3d64f79ff966d9ee6c1aba0d51e9a8e59f5686dc1
+R = ff6d52a09ca4c3b82da0440864d6717e1be0b50b6dcf5e1d74c0ff56
+S = 09490be77bc834c1efaa23410dcbf800e6fae40d62a737214c5a4418
+
+Msg = 79b7375ae7a4f2e4adad8765d14c1540cd9979db38076c157c1837c760ca6febbb18fd42152335929b735e1a08041bd38d315cd4c6b7dd2729de8752f531f07fe4ddc4f1899debc0311eef0019170b58e08895b439ddf09fbf0aeb1e2fd35c2ef7ae402308c3637733802601dd218fb14c22f57870835b10818369d57d318405
+d = 6b98ec50d6b7f7ebc3a2183ff9388f75e924243827ddded8721186e2
+Qx = 1f249911b125348e6e0a473479105cc4b8cfb4fa32d897810fc69ffe
+Qy = a17db03b9877d1b6328329061ea67aec5a38a884362e9e5b7d7642dc
+k = ab3a41fedc77d1f96f3103cc7dce215bf45054a755cf101735fef503
+R = 70ccc0824542e296d17a79320d422f1edcf9253840dafe4427033f40
+S = e3823699c355b61ab1894be3371765fae2b720405a7ce5e790ca8c00
+
+Msg = 8c7de96e6880d5b6efc19646b9d3d56490775cb3faab342e64db2e388c4bd9e94c4e69a63ccdb7e007a19711e69c06f106b71c983a6d97c4589045666c6ab5ea7b5b6d096ddf6fd35b819f1506a3c37ddd40929504f9f079c8d83820fc8493f97b2298aebe48fdb4ff472b29018fc2b1163a22bfbb1de413e8645e871291a9f6
+d = 8dda0ef4170bf73077d685e7709f6f747ced08eb4cde98ef06ab7bd7
+Qx = 7df67b960ee7a2cb62b22932457360ab1e046c1ec84b91ae65642003
+Qy = c764ca9fc1b0cc2233fa57bdcfedaab0131fb7b5f557d6ca57f4afe0
+k = 9ef6ebd178a76402968bc8ec8b257174a04fb5e2d65c1ab34ab039b9
+R = eef9e8428105704133e0f19636c89e570485e577786df2b09f99602a
+S = 8c01f0162891e4b9536243cb86a6e5c177323cca09777366caf2693c
+
+Msg = c89766374c5a5ccef5823e7a9b54af835ac56afbbb517bd77bfecf3fea876bd0cc9ea486e3d685cfe3fb05f25d9c67992cd7863c80a55c7a263249eb3996c4698ad7381131bf3700b7b24d7ca281a100cf2b750e7f0f933e662a08d9f9e47d779fb03754bd20931262ff381a2fe7d1dc94f4a0520de73fa72020494d3133ecf7
+d = 3dbe18cd88fa49febfcb60f0369a67b2379a466d906ac46a8b8d522b
+Qx = b10150fd797eb870d377f1dbfa197f7d0f0ad29965af573ec13cc42a
+Qy = 17b63ccefbe27fb2a1139e5757b1082aeaa564f478c23a8f631eed5c
+k = 385803b262ee2ee875838b3a645a745d2e199ae112ef73a25d68d15f
+R = 1d293b697f297af77872582eb7f543dc250ec79ad453300d264a3b70
+S = 517a91b89c4859fcc10834242e710c5f0fed90ac938aa5ccdb7c66de
+
+Msg = 30f0e3b502eec5646929d48fd46aa73991d82079c7bd50a38b38ec0bd84167c8cf5ba39bec26999e70208af9b445046cd9d20c82b7629ca1e51bdd00daddbc35f9eb036a15ac57898642d9db09479a38cc80a2e41e380c8a766b2d623de2de798e1eabc02234b89b85d60154460c3bf12764f3fbf17fcccc82df516a2fbe4ecf
+d = c906b667f38c5135ea96c95722c713dbd125d61156a546f49ddaadc6
+Qx = 3c9b4ef1748a1925578658d3af51995b989ad760790157b25fe09826
+Qy = 55648f4ff4edfb899e9a13bd8d20f5c24b35dc6a6a4e42ed5983b4a0
+k = b04d78d8ac40fefadb99f389a06d93f6b5b72198c1be02dbff6195f0
+R = 4bdd3c84647bad93dcaffd1b54eb87fc61a5704b19d7e6d756d11ad0
+S = fdd81e5dca54158514f44ba2330271eff4c618330328451e2d93b9fb
+
+Msg = 6bbb4bf987c8e5069e47c1a541b48b8a3e6d14bfd9ac6dfaa7503b64ab5e1a55f63e91cf5c3e703ac27ad88756dd7fb2d73b909fc15302d0592b974d47e72e60ed339a40b34d39a49b69ea4a5d26ce86f3ca00a70f1cd416a6a5722e8f39d1f0e966981803d6f46dac34e4c7640204cd0d9f1e53fc3acf30096cd00fa80b3ae9
+d = 3456745fbd51eac9b8095cd687b112f93d1b58352dbe02c66bb9b0cc
+Qx = f0acdfbc75a748a4a0ac55281754b5c4a364b7d61c5390b334daae10
+Qy = 86587a6768f235bf523fbfc6e062c7401ac2b0242cfe4e5fb34f4057
+k = 854b20c61bcdf7a89959dbf0985880bb14b628f01c65ef4f6446f1c1
+R = a2601fbb9fe89f39814735febb349143baa934170ffb91c6448a7823
+S = bf90f9305616020a0e34ef30803fc15fa97dffc0948452bbf6cb5f66
+
+Msg = 05b8f8e56214d4217323f2066f974f638f0b83689fc4ed1201848230efdc1fbca8f70359cecc921050141d3b02c2f17aa306fc2ce5fc06e7d0f4be162fcd985a0b687b4ba09b681cb52ffe890bf5bb4a104cb2e770c04df433013605eb8c72a09902f4246d6c22b8c191ef1b0bece10d5ce2744fc7345307dd1b41b6eff0ca89
+d = 2c522af64baaca7b7a08044312f5e265ec6e09b2272f462cc705e4c3
+Qx = 5fad3c047074b5de1960247d0cc216b4e3fb7f3b9cd960575c8479fc
+Qy = e4fc9c7f05ff0b040eb171fdd2a1dfe2572c564c2003a08c3179a422
+k = 9267763383f8db55eed5b1ca8f4937dc2e0ca6175066dc3d4a4586af
+R = 422e2e9fe535eb62f11f5f8ce87cf2e9ec65e61c06737cf6a0019ae6
+S = 116cfcf0965b7bc63aecade71d189d7e98a0434b124f2afbe3ccf0a9
+
+Msg = e5c979f0832242b143077bce6ef146a53bb4c53abfc033473c59f3c4095a68b7a504b609f2ab163b5f88f374f0f3bff8762278b1f1c37323b9ed448e3de33e6443796a9ecaa466aa75175375418186c352018a57ce874e44ae72401d5c0f401b5a51804724c10653fded9066e8994d36a137fdeb9364601daeef09fd174dde4a
+d = 3eff7d07edda14e8beba397accfee060dbe2a41587a703bbe0a0b912
+Qx = 6dd84f4d66f362844e41a7913c40b4aad5fa9ba56bb44c2d2ed9efac
+Qy = 15f65ebcdf2fd9f8035385a330bdabec0f1cd9cc7bc31d2fadbe7cda
+k = 7bb48839d7717bab1fdde89bf4f7b4509d1c2c12510925e13655dead
+R = 127051d85326049115f307af2bc426f6c2d08f4774a0b496fb6982b1
+S = 6857e84418c1d1179333b4e5307e92abade0b74f7521ad78044bf597
+
+[P-224,SHA-256]
+
+Msg = 2b49de971bb0f705a3fb5914eb7638d72884a6c3550667dbfdf301adf26bde02f387fd426a31be6c9ff8bfe8690c8113c88576427f1466508458349fc86036afcfb66448b947707e791e71f558b2bf4e7e7507773aaf4e9af51eda95cbce0a0f752b216f8a54a045d47801ff410ee411a1b66a516f278327df2462fb5619470e
+d = 888fc992893bdd8aa02c80768832605d020b81ae0b25474154ec89aa
+Qx = 4c741e4d20103670b7161ae72271082155838418084335338ac38fa4
+Qy = db7919151ac28587b72bad7ab180ec8e95ab9e2c8d81d9b9d7e2e383
+k = 06f7a56007825433c4c61153df1a135eee2f38ec687b492ed40d9c90
+R = 0909c9b9cae8d2790e29db6afdb45c04f5b072c4c20410c7dc9b6772
+S = 298f4fcae1fe271da1e0345d11d07a1fca43f58af4c113b909eedea0
+
+Msg = 1fa7201d96ad4d190415f2656d1387fa886afc38e5cd18b8c60da367acf32c627d2c9ea19ef3f030e559fc2a21695cdbb65ddf6ba36a70af0d3fa292a32de31da6acc6108ab2be8bd37843338f0c37c2d62648d3d49013edeb9e179dadf78bf885f95e712fcdfcc8a172e47c09ab159f3a00ed7b930f628c3c48257e92fc7407
+d = 5b5a3e186e7d5b9b0fbdfc74a05e0a3d85dc4be4c87269190c839972
+Qx = 897089f4ef05b943eeac06589f0e09ccc571a6add3eb1610a2fc830f
+Qy = 62ba3f6b3e6f0f062058b93e6f25b6041246c5be13584a41cae7e244
+k = 5b6f7eca2bcc5899fce41b8169d48cd57cf0c4a1b66a30a150072676
+R = f12c9985d454ffbc899ebbbb6cf43e3debcac7f19029f8f2f35cce31
+S = 12fcb848adbd8b1b4c72b2b54a04d936e4a5f480ae2a3ea2e3c1baae
+
+Msg = 74715fe10748a5b98b138f390f7ca9629c584c5d6ad268fc455c8de2e800b73fa1ea9aaee85de58baa2ce9ce68d822fc31842c6b153baef3a12bf6b4541f74af65430ae931a64c8b4950ad1c76b31aea8c229b3623390e233c112586aa5907bbe419841f54f0a7d6d19c003b91dc84bbb59b14ec477a1e9d194c137e21c75bbb
+d = f60b3a4d4e31c7005a3d2d0f91cb096d016a8ddb5ab10ecb2a549170
+Qx = 40a4ab1e6a9f84b4dedb81795e6a7124d1cfdfd7ec64c5d4b9e32666
+Qy = 83aa32a3c2fc068e62626f2dafce5d7f050e826e5c145cd2d13d1b27
+k = c31150420dfb38ba8347e29add189ec3e38c14b0c541497fb90bf395
+R = bf6c6daa89b21211ea2c9f45192d91603378d46b1a5057962dafaf12
+S = cb6b237950e0f0369323055cd1f643528c7a64616f75b11c4ddd63c7
+
+Msg = d10131982dd1a1d839aba383cd72855bf41061c0cb04dfa1acad3181f240341d744ca6002b52f25fb3c63f16d050c4a4ef2c0ebf5f16ce987558f4b9d4a5ad3c6b81b617de00e04ba32282d8bf223bfedbb325b741dfdc8f56fa85c65d42f05f6a1330d8cc6664ad32050dd7b9e3993f4d6c91e5e12cbd9e82196e009ad22560
+d = c8fc474d3b1cba5981348de5aef0839e376f9f18e7588f1eed7c8c85
+Qx = 66f49457ed15f67ed4042195856f052fe774077f61cebcb9efddc365
+Qy = 3a6e3f3423eec7308a69eb1b0416d67cc3b84d24f251d7cbdb45c079
+k = 5e5405ae9ab6164bb476c1bb021ec78480e0488736e4f8222920fbd9
+R = 7b7beaf9f696ca1a8051527478c4c075ab45aa4768937886dbf38618
+S = 93d4cf110a37c5a6f15c4e6024822118539e860dee2f60b8c3f462f6
+
+Msg = ef9dbd90ded96ad627a0a987ab90537a3e7acc1fdfa991088e9d999fd726e3ce1e1bd89a7df08d8c2bf51085254c89dc67bc21e8a1a93f33a38c18c0ce3880e958ac3e3dbe8aec49f981821c4ac6812dd29fab3a9ebe7fbd799fb50f12021b48d1d9abca8842547b3b99befa612cc8b4ca5f9412e0352e72ab1344a0ac2913db
+d = 04ef5d2a45341e2ace9af8a6ebd25f6cde45453f55b7a724eb6c21f6
+Qx = 8d642868e4d0f55ee62a2052e6b806b566d2ac79dbde7939fe725773
+Qy = 79505a57cd56904d2523b3e1281e9021167657d38aeb7d42fc8ec849
+k = ec60ea6f3d6b74d102e5574182566b7e79a69699a307fee70a2d0d22
+R = 2fd7fcbb7832c97ce325301dd338b279a9e28b8933284d49c6eabcf6
+S = 550b2f1efc312805a6ed8f252e692d8ee19eaa5bcd5d0cda63a1a3f0
+
+Msg = 4cc91f744ac858d3577e48813219aa3538dd813b186b42d1e6218376f07cc1cc448ddd6b37240e98bf953f49cf54d65c12878b33c0bf6eb1c60254f0b6fa974f847e53abc56773eef6f29885dfc619e6a48fc15a667ca94001a0c945b6357a53221b0f4b266181456b0d2d25e90708777f1a6f85971c00140c631c1991e0fd06
+d = 35d4bbe77d149812339e85c79483cb270bdac56bbf30b5ef3d1f4d39
+Qx = 7924b1d7f5920cce98e25094e40f2eb3eb80d70b17e14b3d36c3671c
+Qy = 26c5af35f71e61858582b7cc2b41790597c53ee514ffdf7a289d108c
+k = 751869c1d0e79eb30aae8fbfb6d97bfa332123fd6b6c72c9cd3c1796
+R = 26bb1b92b0f01e94eba5fa429271371db527ce857abba13bd1103f64
+S = 836aba9c63e1252c2b2d72a21e6a41b82241ebe32647e7f814652bcb
+
+Msg = 58f43cc1924de4bc5867664adbc9d26b4f096a43aca47c27c52851b006dc2a658919ef9ce5b5ac48372703be15ac51631c2bd84b88f479f113b0569a9a09e230ec1e8e573474c6075284d3e57d973829af35325d9e7dab4a5f9b065155bbcaff3642a82ef4c9b9e127d3575c050721653da3b087d3fa394192897a5519527d19
+d = 2c291a393281b75264c9b8817af684fa86a1cdc900822f74039dc5d6
+Qx = 18cb5826ad60e6696bf07655032a3749f6577ca36da3ccd6e66a137c
+Qy = 194e14820fe02d784fd1363ff7a30399518309765bd3f4412d646da2
+k = e2a860416229dfd3f5a5cc92344ca015093a543943a0d8f73bf2b2fd
+R = 00e300c1ef4a8c4ca5da6413856f8981db49de29bdf03f32ffc3ceab
+S = f250f18a51ba5f63e1584097841099fa6ae4e98ee458c061d1d5aed7
+
+Msg = 113a2806b052fde683ee09453098e402204155afb3776fd1cad3a9103421d327eab8f9ec0dd050ffcc83f93b34ea707705fabeccfe43ab1a71c95298fd3ec769d99ead1066950eee677d225816e0faad19cf69e1b35d16771689e2092cafe16d7c0dd7b0db73fffb8d0f3eaed83004dd21e753530ec939c89ba25578fa5f785b
+d = 831ea25dbeda33d272a1382c5def0e83929170ab06a629eed6ee244b
+Qx = 076518e393940d42dfd09819409d66966d8c9189c83d554a9cc8a082
+Qy = 44d0ceaf4c0f50e46bea4a52e30423ce3ada19edd363ac5694c65cb8
+k = 6be6dd9f6a083915ccba54626caf12d246d3aece0a7eda7d8d85599c
+R = ff1460946e06fb6f5d35e8d2625ca70ffb9b45308e3fabf6ad8351b1
+S = 6029aa3990918e8cb8a388d53b0772e5cdfff49c3405fe0d3a95933a
+
+Msg = 64cbfc8f2e2149a31b3e8a80c4a552f6c62aaeb7990b6e0ee55500a9d17be04213406578caf315951086dff5c2af3b5ce17d425d185101ef26f86396ba3a129a4f3f8e2dd595f59efb6c0f5c2dcc394569d7268695e9ac7daa84203f1f1895f1f9e4b514a5c9cd23baa63454710144fe735ad9b8f42d8c43267aa434a26d7e5f
+d = 70f74c7324ef137318b610ead8ddc5b964e0eed3750b20612fc2e67b
+Qx = 279649e2a2918e683520cde3fc98b0ae58a7100e8de35e7c9cc797b6
+Qy = aa4de6be34be61f02880139787b9038f4554a8ef1c994b887c2974b5
+k = 8e984864f86f7a2a73f3edda17dbccd13fac8fa4b872814abf223b1b
+R = 3b18736fa11d04e27e2614cda03a63ec11a180f357b0b3192920d09c
+S = 2f0f3dbd570727b14fbb29155538e62c930dd51c4035275c1365dc60
+
+Msg = a10a11c8e30fff118d371daf824f16c08200b83ea059436466a4611ccac93b2dea2de8c1006f946196aef7fe9b0c251a391b0340f21797798278b412ff2b53842eec6450728e2bca062f8337a2c204b9ea04ff660cd4d4db559f2f11c4d8ef199021339fcc82396f7a93926cf5f247e37d8067fe50692de54f102bd5ab51925c
+d = 026be5789886d25039c11d7d58a11a6e1d52cb1d5657561f2165b8a8
+Qx = 3fa617c50b177da1a2bdb98b780ad21ad1195c4bd24465f6187de3c9
+Qy = e3fd8d8876dfd03a4a4e31a1acad3a08d983826d286c250c4e5620c1
+k = 0128b8e3f50731eb5fcc223517fc0cf6b96cd1d2807eb4524bc46f77
+R = 3a6b633f96f3d0b6d54f7fb29ac33709e4f0dd8fa0e51606ed9765ca
+S = 63e8c119dfa51784decd864f6911f2210a80f8f02d472d88df10d119
+
+Msg = b3f720bf566ffa369259f4361959ae0641d2755ec264a4c4349981df2b02563275b2b9adb5aee47f7a456760a971991ffed6b17809bb9694138d1677fa916123795239353158fc6b22d10f20d26f5d2dcd8c56c44373eea5b93067dba2d7c5318dac2e9e8714873cb1b37f58c011fd14fa1e535554efe05f468bfc8e11cd8b99
+d = e79c18d935c2839644762867aa793201f96a3cde080c5968412ce784
+Qx = b7ae1e992b1c7fde1141f40bd913358538ca0f07f62b729f13cea327
+Qy = 811252d12120e04805fc171a439d382c43b68a21e1a0bdf5e4ec1da4
+k = 7abedab1d36f4f0959a03d968b27dd5708223b66e0fc48594d827361
+R = d35047d74e1e7305bb8c1a94e8ae47cb1591c3437a3e185e00afe710
+S = d9c425c9d5feb776ac8952e6c4eee0ecd68aef2f0e7bff2e49c9185e
+
+Msg = 0a398a46df7ccc48d1e7833f8bbc67100f1ef77a62dc78bbc115b2a662f9591fbaaa91ad3d788e2fdd1b3164e45293d4f5686c151296901768028ac80ded4bf89c647ad35f0c7c4cb318c0c757c1d83c44d850e5fd4677281b3f13b1ee54de79c8c042813f9d3312dcc6111a68299cb7e829557d7f3d96e702f65aefc6499415
+d = 0d087f9d1f8ae29c9cf791490efc4a5789a9d52038c4b1d22494ad8c
+Qx = cd95cf8fb1cd21690f40d647f2353672a1076cc6c46bddaad2d0fc56
+Qy = 934262f74d9ee0f8a2754f64cb7415923d64bf00c94a39b52803f577
+k = 557d0e3995dc6377b3911546dd7aeaeec62a6d8f2af6a274382fc37f
+R = 56df0ea6afdcc232ceb41729eec00cf906b69b6e28423a36d3c92cc5
+S = f4f70fd948c9a147f55317fdea7b8a84c33e721014552d5800d63edc
+
+Msg = 8c33616821a6038b448d8918668977fcf1ef5aa0cf7c341837b39bbcc9bca875a3757f4b392630e9995b9bbe4eb66978b877586adaa02f99d2344dae082a7603351d8ffcfca081ab403cd0acb90d078dd1d0789c2eb3185c62bff2d9f04cd38e509e3b83c12ed0a5c6808fc42f7ba5b06acdc496c8ad9be648ee6a4505f8560f
+d = 0830aebb6577d3a3be3ba54a4501c987b0e0bb593267b9bbadb66583
+Qx = b88652020e083ccc1c43dc83d1881884dd4c7e3b4e3460b344b1ea64
+Qy = 22b69b517f86d7c26dc37c0f8feb4bb07fe876149fbcc3334fd2805b
+k = e4f4a3280574c704c2fde47ca81ec883d27f2c5a961a294db7cda9d2
+R = b30b8a0079d9a134b5e1618c2ac63e3fbe0e95866b9dbc5f423f2707
+S = 3dc36746610271ef66e0aa52cc2ccadc5c9b08dc769e4dc4f6538c11
+
+Msg = 94d56535fd4edfe67a0daa6579f9d53bf6b7b8830ae2aeb62892ff59f18756ddf2811b449c7d20d65d54f8507de4e7c50eaa084830637812aa4b250a4d61ab67845be36e4a41cdc0a70f8d6e3a63d4514f0dc197e6486015046a316153d5f3a3a4a0ae1ed7ea5fa55e12e73d333333685c02e0eb636234ea7e6d4b76b4b76b5a
+d = 2acc9b97e625263e8e4cd164302c7d1e078bfcdd706111a13ccda5b2
+Qx = ce1a06f82df874dded37cca03b56c0648e4e8917ecd40ee73ee61588
+Qy = ceb6177b8f1ac7c5c6e6e1f7737cc3026952ee392badd2cd7af32f9d
+k = e401fa80f96480d437ed4f61a783888062ec33d530b188fd48016a6d
+R = 28674f447c4742e4087bbccfb522fbad4e18b56031d2ce8f532b078a
+S = a5a7a13d15b423dd17771f73cea98d89dbffa846cc209b45c0e29b76
+
+Msg = 5d8ebdf9eb28b47bdafaa36bf0b66a9eaf99b6c83959da4f2b1151b4f4ecd28fb115a64c0cb9491093a7e9b9c53ec423e4c72e7765bb9c818da0e8c428667e44474a71db4867130c77c40bfd8544b2d7b9d6464d2b8e6a48482153256a32437c3a747231f51134dd14c703407e31146a6fcde23bededcf16950486e90ca69ac0
+d = f4e873d4fb944fb52323406f933815092b7672221de4d1c45917f3fc
+Qx = 0dc2cdddb990341adb1de73f02d87fc3822485a659a15145f4251d5f
+Qy = cf78b2a83c7352eda1af2c74e1804ea04b35f76c04e89d90281dc2bb
+k = 5d1476c682a64162fd2fdc82696fc8cab1469a86f707ea2757416e40
+R = 82982b38ed465138df4018d7cfb835edcb591cb57446ca49d163782b
+S = 8ef1d7b326cabee7f7ab95b7b98d3c27a069c0fd95a1599c0ccb422b
+
+[P-224,SHA-384]
+
+Msg = 25e4416695f77551fdce276355528ccf1ddc2483821c5d22d751d50111ca2fadc6593b52c74f4b5957494f1df25b0b2f86950d0d19229ec6506fee8581d2dd09d48418b146ff16bd84a17ca0dc83b1888eb407376da6c8a88fa1e60b8c2a2471dfde4b3996ef673d5bde3d70c434dc9f2488e9de16ae657d29e5e59ec922a1ec
+d = 62c572ee0d6f81b27e591d788bfc2f42b5105d2663078dfb58069ebd
+Qx = bd6ba605639b98fa8113a16a3bb004ddfaec901c98a931206165f4a5
+Qy = a3190b10ef39e88abd60b2293b4707512b45c6c5ed5794cc11454427
+k = 0f0bb1e428bcdebf4dc62a5278068efc0f8ce75f89e89b3630f102b2
+R = aac0ea27e129f544abcc77f110e70bbdd5aa3e425dc39d5e8887025d
+S = 10e5dd06aee6b8419a04aa33d9d5678b0039c3acc3c4b61fe106bfdc
+
+Msg = 9164d633a553deccf3cbd2effccf1387fa3177cd28c95d94a7d1a3e159c5e5c027758cc26493301b2f4d141d8d07a5fe5fead987ce5f30abeafcb48c302afc6c2309f0e93d9b6818cbb6972d222cb7b01302dfe202ae83b89f53150ae4a0e2b8fc0fd1091f19b4ab2e6ab213ab322d04f2c5f57113bfad3c5675227237abf773
+d = e2f86bf73ba9336fa023343060f038e9ad41e5fe868e9f80574619a3
+Qx = f5d5346f17898ea6bbdfff19c216a8757a5dc37b95315f5481628381
+Qy = ae61fd172ac8b7a4f13870a932dece465834cbd4f50bbcfb802c824e
+k = 35724ac043e3b44b73b5a7919cf675190306d26aa67c27c28c873534
+R = 535147c265af138eec50c7fb570bcc8d2e6f675597b0fcc034e536bc
+S = 743812c188a1dddf9fb34b90738f8b2e58760d6cd20ccceb1bb9c516
+
+Msg = 019df05929321ecea7ee1de4f412aba1c8d3c24437db04b194a68a0a59dd871be10bd3a4be6edf551350ea49fc7155a4d887e1221486291abe77a30633a4c4f7868fe2df24311cba0c73804883954460e122387ed414111ff96ff1aebac8b6a6491d8a0d16e48a63bf3d027c0f68ee4a4b234d73b412196706af8ea022b4dcef
+d = b0a203438e2586d7575bc417a4a798e47abc22aa3955b58fc2789f17
+Qx = dc5d217862a1e5b00c95affa9d8b925a72b9beaeb7a86dc397e788d8
+Qy = 5f05f8e976ae1eb1036eca6d683a82850795bf9127dee5f8b2859445
+k = 408e9c8b1f33136d6ddb93ff3a498bc09d4eee99bf69cdd5af0aa5a2
+R = 1b5a964c8b1fc634c6e2b82322499df1d7f0c12a4d2a77723c816ab8
+S = cf54599a36ca064fae0aa936de5266f87704409d22a15d28c01b7f2a
+
+Msg = 5d09d2b1d3fa6e12c10d8b26dc9aabc8dc02bd06e63ff33f8bb91ede4b8694592a69e4ed4cdf6820069e2b9c7803658949e877ffe23bf90bcf5ce1409c06c71d86885a94048b05ac0ec9db193e489a5a2bfa367caf6aa8ecdb032be366174343f6875d2fe1785e8d77334f5f469cec64998e08d3303e5c9a1923b34fdc105d65
+d = efcfa50fad6fb2065f9a55f28c0c42fa24c809ccb19b6fc6d8ffb085
+Qx = 61521a0cfb72be77ba33cb3b8e022743cd9130ff49e97093b71aa178
+Qy = ce0819aedaf6fce639d0e593f8ab0147eeb6058f5f2b448231584ea9
+k = d1eea821f286eae6ebc1f61b08f9ad4323a3787e94af4c32cd31351b
+R = b37caaa71103752ac559f9eb4943324409ebfa8b585f684dcaa5c411
+S = 7c28e7619e2944ab4b7be022878c8052ebdf2cae5dff4f976c49686a
+
+Msg = 50f6dfc81c6cf189e0a310f992907fe93356cee9dea9a41c7671a8daf3f4cfe0c459ce6122c1e731dbf7593419d7114cb73b46956158a982c5d52c72f43f0f822046093c69aeff1f7e4cd8af00ba655c5baa2e7b6a400b4be1f6fd51b3e4cfb35a69c80a28c5cafb771b6c2e52e0aeef0e3fd045e8d40745f3f8b74fd969f816
+d = 61a17816937987764cdc064dc7b5b4f5b16db1023acdfe25902957dd
+Qx = a7e975c0a8f87c683bb8e31bc160843a7b69c945f4850bd60e1c08c0
+Qy = 8930a454dcc2aa13bed7ea89368b2c9d689d816b2acf4e52585ee9c4
+k = 44b1fdec2629f9075f89c134ac28ff19bfddaa9db02a5d7f853582b4
+R = b0f5635d8bc9c53a1d54a3ec63de59ed66e6b2358d4ab79755414326
+S = 67c68fe265c7e5aba4232deeafb88545a2aa266fb9f2c2bb3f3ae8d2
+
+Msg = e90129ac6672c85bb7b6b18e9dc199c96c81fd65034b53c77818364d512366fb9cd1bc7c82404c451e561fc1ed916c0948f6ac561b33a1ccca093f07684b8c2bafa9e966377bd208556018a5bafb9edcecf70498c7140fe9c8cf3ad8b8c3b0aa489df797944465047465415bb0e24333235fcdd59a98829a3941eaaf62033e82
+d = 79d5367314ec664aa0f6ca36f95549502a05bf8400bf532d669fab8d
+Qx = 3191f0237102dac159032ab2dde53cf56c9ec827b5caddfe9e83c02a
+Qy = b496b1bdcca4434ac0d0d91ea38ff3bc33f9f54095bfe17796d5a9e2
+k = da529c52f5cc1f435d873109cd991d6cd7e1631d9ff1dd9521dd5db6
+R = 8e0ac63903f4921755430572c3f08bc272790639bdf1009fe2a9a714
+S = 6278c841a2d0a270791fe54b36c49d426d67907aa4e4f59c8638ad97
+
+Msg = 3c9a483c9bee33b601549c592a82e95b4319b1e74b777877f0971bcb4273716b268e8f99f876e42f942f4cf08284896bbc1ffbf094ac0956c3cedfc3580cffa8c74fc6db29a371f2da2d05edb9185ece741fe0d3fabfe9d5b4d373755ebed13dc6840cfa3283b9ea46ec8b95c434f253ae86998182e9cc0e95ee64f323fc74b0
+d = 1320eedad4745121793a7eaf732b0b4498f7cb456cac8cf45a1f66f0
+Qx = 9fdd99906ab77fd29e9021bde947d05a7a9eb153612269bfb0899bc9
+Qy = 681b65b9ac8e4c2899bb622dafb253b7bf5a6e38e5f6595f997c291a
+k = 66ed8d8934633f4125f593cf1b1d3745c4db1f15dde60cf46ca1c7f2
+R = 80199485a3a96447b39f7679cd47412a78675ba17dcbd10465dc5b48
+S = a251fd9f136a3cb0dd0bc80659ae032e4a761ba7045da0034553fb8c
+
+Msg = bfc073fdda63c5fccaa0ca8770c293e8154e7aec56128bbac4fdbd541d602216ebf7ca1e02b514d6e396f20683802ba3f334310a9226576926e3bb19ceee27738d13377cbafeb09d091043501702a07aa31d1f29d50ddc55adcf16ffd40578e734a4e6cb6535f26ad48e0c62ad90e79720000e87d419e92dca3e11f943655b03
+d = e18821329447d3f65ba7279e96bd4624ffa1b32b90f6e8331b1e876d
+Qx = 46c9ed837232c47022df2f1a1578fbe65ac9f2e81c98a74cc22ea31a
+Qy = 6fc5e9568ae62b31412a0b0b367242e9fd7e518c83aa06a069e1d90d
+k = a4c1eb402a2fb3af26e0e14a3d2fc8ed3bc1a8b2475270356a79fdd3
+R = d478b68733d8ad44be46766e7b66af782fbdc7ff7ed0b191176da98a
+S = 5eae9160ccf71fd1d359d89cecce72ef8afaeee2365f6ba828aa450a
+
+Msg = 08079955d1a1f33728128c73673ec9f21a6ce138dcab5adc4dc068e6ab57314b9fbd8b013123b2fdafa9524fbdd0288777a233de8055cccfad83046ada6a19f01c47817496667bba8fc8b9456fc0e044a562d931dab1adcb66af8b66325bdf28d83ded3e2937958ccd19da540d70ef2c189f55a506c9c0d63406394c5bd3823b
+d = f73e030d5a696b358986d3efaca121cf71f775f8835a21e6135145d7
+Qx = 9ca2c6ea87ac8dd3a23a5b4010841a7c8af309038882ae44634bcf55
+Qy = b0a347dbd5ded3b8702ac5a457e8b32bd4de06fd315095fa1b7d5fe1
+k = e3cc786c1288ea567836c51d6d69dd0cab5c015987d936ccc3a4beb3
+R = f1234da71761b7a0f49e661a419d2a739bdc4544bf87690e3d2f96db
+S = 096d16bf8020c3d3c233894ad8eb81206010e62c6e692a215e088fd4
+
+Msg = 23900b768f6cd42b8a8df0dcbc9cb5daec8de36b9d5c619adcc1ba2b649103d5af123746cdf19c3fd0665a6fb9338156182aa06181e3c6e37ce56979612af2927440424f89cef43fc754854b8a5c43370808cf5f9929cf47712512ce2f8a2a20d2e9f568c2848b27dfbe09142843c83905ffa5da3b15501761b03dbc2c5398b6
+d = 7a0789323f8741c157a1753ae165ecaf8e8b03a60561f8b80cee467c
+Qx = 101271a9addd4bd1f19d00bf116c8524f52cefd598e85dc381597acb
+Qy = 2f17d14f4d8ccb28b216553718152ba7c104646d8eca986dd9ddea39
+k = d169f04f05b60c625cda864d187938863964dab7bb3b9dfc04b05519
+R = e4a51be686a764b709da23ab48b1985e153c6ee238d945e743907afc
+S = 118a8f1ffe3cd556ce6345bd1a398dd9cc3729b7fd6d8af9bfd82f40
+
+Msg = 1eb28c0bcdd18f73e347f957ece15b4cc83a771b0877e1feaac38e24028fb38ccea8b54ee017dc7c3d5a1327bc6f40b294aa65d7dc487f278846cd101ee84202f14b38aa2c275046aa2577f65ebaea41cd383e8def2fd0b4444dcf426fa75c4082cd7fa035cdb1e0d34a3c79d42130f5b0273eae75bc701dda3aebe7358f41b5
+d = 78e795d0edb11fd9e28dc26b21e751aa89bea0d87932ef11c95c0e18
+Qx = 9edd544107977134bf6360d43ccabb3c94d627c03963c0a04b439627
+Qy = ece4c61d319a0e41f3de7863e7c355bac94395aaa74cdb5f74a87a5b
+k = 36f7c0f76808b826a0a974a1fd6e155e00a73f1d34674a8f88be405a
+R = 3e319444438bc2cc92f323ea842cb402b3c3c2448c89869ef7998edb
+S = 3420cc38f058f41c31e71f4b1ad488f801111c73541de69fcee60695
+
+Msg = efab51855407438fd5c250670366bca3c026ecec4a59394f00d8a4b51746d0c4564366656d507e3e13e62fe7abeb976b8859895848dbaecf6582f1898ea06f00d4247702ed9721bd375aa83ae4c67c2eaa6e080777ea5ecf2cf787d785389560ac91cf63a52f0373c3185e18a3b8a466e21b61a239f1b77624eb1acacc76c4e1
+d = bee02d8bc5bffb3fd3b4c9d6f686409f02662d10150d1e58d689966a
+Qx = 8848f964c847fe9dddc774618d4588c9cd56bbe588d7b1fb369c8bfa
+Qy = ebbb699fbd0dc08859fe9132285fe20dff3b9d561c0640b6e0717607
+k = 59f1450d857b40e5552a4b8cd4ab0df2f01716635d172c1106840f21
+R = a206d8398a16a991bc217f77f23c6f648384f254f255a8a876404444
+S = eb1169cb5b1423dc0bfaffe565ae57f986e00de06405e3e7b605862e
+
+Msg = 31c29ca10279a417f0cc9b1382cf54dbfdfc89f2e6ef08c403c11f580cbf8674b141ed1a417563282d99a55fc616d836421cde9424815c95e7fb7668bf3f137b29937f14882d74e034b732d78d91af7721aac4950734f5fa5d4b4d35534974f8cab6d2e6dca75ddb57e99148c8a59df9fc5bcd723e546e8356f671cf2f65640a
+d = dc0ddf6e501418bb8eafc5d7ccc143369e2aa441df8fc57d5f94a738
+Qx = 063a5d632f4144376e14cfb03ad8ccf1489b613acd184d20dff66545
+Qy = e77727f057b043d8a0f7458196b72e92d11f85b0891c6aaa9d915f58
+k = ff0e5cae2671db7a1b90e22c63e7570bdd27352d45bac31e338debe0
+R = 5bc0b4998481ecbd3b6609184a84ca41d69b08c37138097f559259f8
+S = 0df8828eb1ca85e46405b94e1a2972c34c5e620a54e2f640f04aecc5
+
+Msg = 8db476f92e332519c1a0ece5d8deded6efbd2d8e8784eea0a6b4c3b4296c35f5f8de4317e5c1627b91fb1973fee86c06e4992aa5a20cb7475c8808ff1da354d07a488dffa7838c6ec1e3f99e3acba831f27bee8434eeda3eb36d0c6df3658883cd40068b1bed841310f6eb38d4a3d07d85848770ff7933c054cd8b34662660b1
+d = 229d89b2fcf8441ffc95ebb2ac2ef156e25825782044b2b8bd6a3e01
+Qx = de616848d8044a44789ef1ba3a6dd66fe9257ddc57f7534e59a701be
+Qy = 26cbf74a6d25e5b34b96d30f327abd574cff7f7dbe6686573a7d6c5c
+k = 3b18ca6ec8e8e255ac88f64302745ca0b73ff94b2b2d48be95b4aaee
+R = fa94fd8b827c06115c1eefd50afc02ce5926ee0e789667783c01c34b
+S = edf766a66973cfc33e4159966c07321a7f6549c3c60e8586ef41402b
+
+Msg = fcb272c828fe8fd3c6f8de9410c7b6e2b36717c1b0e5e359e9109bd7fc378978aa98182a9d99961898ed88999b050d3b64d1457d7a899d6d273b9f4dde2aafa36d76329d62509043c338f265fc4c7d938459b7fa3b230a9f6cb632b61489546bb4181a5ad7f0d7369b8caced48eb374b075b2b325bc86add0f3b680cd9e80acd
+d = 97d747068147c0393a0bb5c159e2c9f1bd538f6204823294883abe28
+Qx = 3858a576eef2ce24d01766997fb81b3f3f78b6104cd188610be221d7
+Qy = 95ffc677ac7bfe3e0bb4cffb17355a964c8356a807151b3cba5d1f4e
+k = c1a2ec1ef16cfd5107c892790daefbed061be78bd8576696b60f64d5
+R = 18c908541843fcdac99b9ff6bb397f3f8094d16b42670216e4eaa2d7
+S = c107a8a508ff57c5d4f78f86cc37e129c864d1c44ed5e73909613b74
+
+[P-224,SHA-512]
+
+Msg = 7522492bdb916a597b8121f3e5c273b1d2800ef8c1db4f7dcbae633b60d7da5193ba53a63d7a377b351897c3b24903ae1cd1994211b259be3e6ae2cbc8970e4957fdf782c7d1bc7a91c80c8ef65468d4ef35428f26e2940ae8b0bd9b8074236bf6c00d0ebe83f9ddb2ade0f835138d39f33b59f244e0037c171f1ba7045a96f5
+d = ba5374541c13597bded6880849184a593d69d3d4f0b1cb4d0919cbd6
+Qx = ac635fe00e8b7a3c8ef5655bdfb7f83e8532e59c0cc0b6534d810ffa
+Qy = 1d067aebeba66e79b28ecfe59ac6fdf5e1970dc3a84499c9d90cd8e2
+k = 187ed1f45c466cbafcd4b9577fb222408c011225dcccfd20f08b8d89
+R = f83d54945997584c923c09662c34cf9ad1e987da8bfd9be600e7a098
+S = 4ff2dba9dba992c98a095b1144a539310e1a570e20c88b7d0aa1955c
+
+Msg = 61097114ff855c3e34a62d9b853f8982d35f29cfa4a89893badbca7849e5fb437a1a38d6451bf0ca5a0d528e352b8e4b57f2ea359a7fc8841d49dd3e570f9b016f14156b0bbc4be822e260bd147ec081454969e11cb0034b7450ef4deb7ed6edb977e2f4ed60121aa095fb0ab40240dc329ecc917f5c64b4410612af065ee9dd
+d = 1e27187134d0a63542adf4665fba22f00cfc7b0a1e02effe913ceedc
+Qx = ecaea8ceea55c3bd418fd34a4ff2499e25e66a104eed846bc00c31d2
+Qy = 3933a356ab1f2dabc303ff0a5d076131e77032e6f502336883bf78a7
+k = 34cb597deae9a3b1cada937abcd247161b19b2b336b20e2e42ae01f1
+R = 58177ba46fb291490b39368774accf72736412c1fb5ee0f27b9b1e02
+S = 58337d78b95a080bfcabb5809bee012501b4da84b8ef310a4628f11c
+
+Msg = dd09ae6c982bb1440ca175a87766fefeacc49393ff797c446200662744f37a6e30c5d33ba70cbd8f12277fd6cc0704c17478bbab2a3047469e9618e3c340a9c8caaff5ce7c8a4d90ecae6a9b84b813419dec14460298e7521c9b7fdb7a2089328005bd51d57f92a1bcbeecd34aa40482b549e006bbf6c4ce66d34a22dda4e0e0
+d = 0905b40e6c29bfcbf55e04266f68f10ca8d3905001d68bb61a27749b
+Qx = d656b73b131aa4c6336a57849ce0d3682b6ab2113d013711e8c29762
+Qy = 6328335ffc2029afbfe2a15cc5636978778c3f9dab84840b05f2e705
+k = dc82840d147f893497a82f023d7d2cbf0a3a5b2ac6cc1b9b23e504be
+R = 583af080e0ec7c1ba5a491a84889b7b7b11ccfe18927c7c219b11757
+S = b23700035349df25d839f0973bef78a7515287de6c83707907074fa6
+
+Msg = 37a73e2774d3b274db426c89b945696daa96035031f72cea01894b24508c7f81961ec254d36ed6a0f448e11cf7950af769dc6cd2c47e52c6caf0ea92c270974f0214b4db436c36a60fb722060a6bb544462a82e1714f5906ec32886f7d59ebf289541c3a00ec1e004892ef2b1286a0194f55d083c6ec92c64b8fd1452e1c68ba
+d = afbaede5d75e4f241dd5b53220f3f5b9c1aa1d5d298e2d43236452dc
+Qx = fe83e59fc8ea8b939355d3258fe53a64d45f63031a0716b7cc416173
+Qy = f151d23060f1c856eb7f1f58be72a7228c3af89e43b56e9695b558c7
+k = 0fbbe7b40136c81a8fb894498d5502157a1cf5a89d0643de92cd38f6
+R = 24f3f457c7b72b7e759d5a8afbf330e31c5d8d2e36f92c0e79c5d87d
+S = 36fd1193def34f12a960740fd79fb38bf2b480726ccad540eb42cdf8
+
+Msg = 9dc2046ffdc6804544db964481abe5d2d276a2a9eeec4c7ad40215b1de23561d402db69bd0f6eec2254711eea4487c64d9a6b62c3ebaf5ffa8db6e7e3a6e17154d126967a47a853a6f8339bdca9be306a13c7f992ded7619b0da59909a49b1e0930360e05b47f18628a36d69b2f87f2bfddd6a5d4a72f84dc76dbdd43f3a6a35
+d = 950b07b0c2b7539a21b5135bfede214733f2e009647d38d8b21d760c
+Qx = f43d13bbfcee3b724063b3910fea49fd591b81e86fdb813b1a492d0c
+Qy = 6b4c8d6fa5dc661889e3cf5ec64997a78222837885f85d2fe9b684fb
+k = 83e110d0d1e700d2f36543028737d2a2f1474aa3b4b28998a39e4793
+R = 2685265bc878e85d10ab13293dec190881a57c4a467f8fc2170432ea
+S = 80a347bb49036522369339bd6485a967cdda818915d8eb947302fcf9
+
+Msg = d9c6847fce688c5e7525a1098b545cb6c15dcd21a02761fc82fc664372a667390680135f91c01a2fa5430c634b1a6d1cd6002d8aa021e7bf5956a7901c2f81bc25d502ba5f55a55f30c0323dc68205cbefec0538e68654e7b327ac1743641896c3e740d8f66f400902b304eafaa4e0d8cffae140536f0922444cc3216a675697
+d = 015bd9f5dfef393b431c3c7fced24385d861ccb563542574a5d2a9bc
+Qx = e868690641e2cda13b289a6c5d2fb175940396044d9cf27b4f2240af
+Qy = 4c78c9abdf2b7fc67ed4497001d7bcf1daca1739dc14a661f91d7c40
+k = e2374350f47c08f3c1359d4edf87e61d1ba4e7dd1540d8d9062efa79
+R = e12dc088d2bc032bb214c77d0e0fb749fc8e61ebe1ed72996f1084b6
+S = 0ab58aa31e0bba5fbc76855e6549f1036fba0a589aeab978ab01b8fb
+
+Msg = 69df8a01b66f04930efd2012ff2243874f256ca8758145d2a9e4ecc84d0dbdbd0dc494ae06db0ccbe819918137c90957114558580d6623efbafdd342b38dad9f08708084d32f874fba04782ce26aaab78de2102ad171f8a8f2b30b5bd3d55fdac5fa3acd6f7def7e61c2533938572b331ba6d1c02bd74bfdbf7337ade8f4a190
+d = 0a3c259df933247445acffb6d8265b601d597fb9997dc2a1eb4deef4
+Qx = e67f4385a9da54253cc371ee9bc6739ae6385a4b87669c7baf0c460d
+Qy = 2bb00b6ddd7b67d9ac5653ec04ca8529fbf16f815c04da3c2e58e82d
+k = 8bf5859665b6a23e6b05a311580f60187ba1c4ae89e44877fb48af66
+R = 653675fb993c3fa9e57b32e33029ec230b966e8077c72c1ec90ddefc
+S = 792723bf87e315147cd4303de7f1dfe95cd7658ebb95c38c1a196140
+
+Msg = 927524982b8d60777c1105c86fac05f634abf58c73f84fb95d81ba0b86e1e43592c4fcad2e395a40fbe7005697d86088e2fb3bb7287eb3f917d4f2dc281f5cbe65d05b4f9623bca849b10a03beca6aa2056a12ebb91cf257ac448c5e9a78f8349a6a29b17c8978bef43a443cbb8a149eb23f794844fc41693f2dbb97181444be
+d = a1c8ef463f9e7e3dd63e677412f87cf9ea4ac9a6a2dae629da5b9916
+Qx = 400e5cd4b315ceb309545cd3277acb70bdae2073fda6ad896ea14b27
+Qy = fbe1d2466cd2e116f38248bd5cabaa6cbe6c4a2694d998abd7b0c991
+k = 82f55a25d3ed6e47c22a6eed0fa52ed0818b87d6ea7950281dfefc09
+R = 16305a46a3f6f9e216ef8f6a6f5f0760d064a885657c864e1c1ea035
+S = 58fd97050bfbca6f87e64e1458c4ad80bae26e280356da344ad3b25d
+
+Msg = 5f9042283561e7f19a436d01c7ef5a950a6d77ede5629cd7e43c0a5d58e8c5673c37945a453291d12938253c71dbe12c8b022ba7276eda6be034ef5ec1ec77dbd1e08f0d7b8e7725b7ec671c075e008a20f77f4ab266f97079b0aa6337df59a33b881954084057b21f294dd14bcb0869a4a6f1f597955ec7bf9d19bb3537a66a
+d = fa511dbf6fef7e5e9c73e4555eb75d435f7884322d9faf5d78cacc0b
+Qx = e8dccd706c31f895f2f261ab979cbab51b8ae28196bcc12a42046380
+Qy = ec246be8e71ea3859cb717a59990fe22e4b76858ff49becd70739a01
+k = a37d665fe4314aa4cd03eb8e6a1f366b43e11fdb419c96b48f787b62
+R = 05e4909bcc172ab4140be291aad4660e375032bce2d762b6269ba764
+S = e347a1c9d3670690e1d8d1d4cd9579848f442199c10526488da5cebf
+
+Msg = c2ae5573d3bf396523bfb703db8502fd0760cd1be528f6ddbfb95aad399e0b19f3bd9e0fabdb05d49e3f893dffec5b627c9c2f7ad5f32e92e4e27a38cb5c28657657377fdfa1b66cd7ac3d15c6d49df92d284db99f69744f37dc7cb4e7d52920fdb200a7942623a7057ba82e467dcccaa5da416b48510d8364446a6a5e2a5aa8
+d = a58bd53646400a646f0e4208320dc679a9664d1c6bfb27fdc8eac7ea
+Qx = e22e0dc4ecd96eb0071b72ba4b4988bf784f3fe73cb81bfb93d9ac4f
+Qy = b3e213e518bee1367a4fb3703b9008bac9d95a1fc4aa61225fff9f3c
+k = 42c5b6f87d3bb1ed74f5ee8398d8f8c61e9e50ffa7a1da12d39893f9
+R = 5c0e5c6f057de1e99ef5d237a60d7a07fa9a42b120a82f573d9fb7b2
+S = 2fffc0bf550bd2f650fed085a84501cacfa6a1bb984df1f9237eaa59
+
+Msg = 03c1a1cd30a039d0dcb22fee2450a7fa79495a0d0f4f43d2de4d75bce003c0334a8860f5c164dbd94888a9f751235a3e570d31070e3e1293a7be616af7176600585d36ac013600157d2569d491da4b8a3bf3630c26e0b9925412189f50b0ae6f04c86477932e2ecd8c3546106ae1ebc684cc3adb27ed665eddece886adea4ce3
+d = 64bd4452b572cc95510ac2e572f41136299ff17f6e8448f4ffb571d0
+Qx = 92521fa25c2e034d127e0921efdb167f0b2ff8b20504487ed87fa264
+Qy = e72c770e37375ad7dc2c4e63e5701826f6606f6ffb9461ee61b4e872
+k = eaf76ee4d7e00d13d8a6d03dffd07ad9a8bb6dc8176c9f93059b1b7f
+R = cf5058e2a6cf5e61a138b013eb292f38a1b9f07239ae5941dbce8919
+S = d14198621650d985d270bc997da6e78588fd0ef843b874c66a3de3c3
+
+Msg = 888f6d9bc7c86c0079fbfd42d8c08d6958f40f6e570fb0b1f03d2f8f8a63df4fcc87b379a222cf835820a999d34996e08961f13b86b075e7fd1c303cd3baa44de42168561589012f7e5300da4f8bdf470c07119a5d9f7ba7293568cd7c6a1b7fc1e41cda40bed7d46e5a28af67ae2aabfefe67a86a1c601e6f5ee543e09bd7b6
+d = 7f3edb710df9d982f486233d0c176aa88f5a0ee81efa9b8145020294
+Qx = e7611e013e7b43ff5b8b57ad83333bffcc9e469ad23070b5791dc594
+Qy = 7784da0a11dbe16208c6e0b6d5029e71fbec4dffc9fa046d3eeb71c9
+k = 94db7ef9a232593091eb9a74f289529c7e0d7fef21f80b3c8556b75e
+R = a971f45bab10b1d16d7234ca8e4ec987da20d9e867f28aa063296e23
+S = e38c538d65a7e1a28fd3ec53f015a7e5beb60e9d309f1e3ba4b2c3d2
+
+Msg = 48453340f1317769e6ee6e103153714365731163dc18f84e9f2fa4b120f9c5a9645ee2f9b66c84c26d95912b422b009b64af96aa418b2427a4209f2e7513ba8e43ec8cf20b34e7529b22eb1199545afe9a9f7d9bcb320aec9ee0162f91c0d1dd9674c9c284f25199c5e109f6f84d7ed0d269cc6413edb81bc2c83e37d644d8b9
+d = b569f8296ff1d9cc01fffd9919016e5730c1858bdb7b99527153751a
+Qx = 242f34959516a4706172f7dede23110efa314bff22eb320ab88feeff
+Qy = 45e3227710900a8acfc9bcce728119d042f64ca40876c2b380ee46e0
+k = ae61523866a8f43e6cdd42ba27a34ed06527e8a5842901a64c393f76
+R = c2732a4e0815f9f785500e80147e9486994446beccf8a6a352b97585
+S = 6ecaece6487d7920e398f7f951ab7c7aba5832dabf03704106ad1244
+
+Msg = 4bdfd3b91d83108409ad765b256e0c9b9937ecf647f8e6f9fc807e2e72af8246178b3fe046b4ea10170450d71a4eec790ecb05f03d7077341de26c4db7eeae24d55c9a9093e837dfdb38168fe8230cb9605825a1282fecd741989bfcdb34678fe077477927f66bd26d003e5dda22043341a14dd31841ba483ad5ce2701e0f68e
+d = 41a4dd8eee39232b728516e2f21e66011e7426a6b25986c3ffa237e4
+Qx = c32988171caab178bf50dc7310bc7f604df5a9d19a8e602519c72d8a
+Qy = f8985d112ad9de05969e5364d943c1cc5cd198359f4c62b19da0e117
+k = 827d4999da81fa920c8492ccc1e2d5cdafed9754cf7382a859952071
+R = 89c61da7422ccd676baec07e2185c12e947a2374eede87847304be6c
+S = 2685379624717ea28422e8d001c090405a130b4ef9f1ac726c3ca502
+
+Msg = e6cdee8558bc1eacc24e82f0624ce8d02cc8d925b4dd3dec3a72f4a4e0fb76076bfa3ef2e2c33bdd7c27b322bdc09bbfee8fe46f75dbd7bbd2af09690b7137943efe21706e0a1b6d3089540fc58d85ddb55ea836616db573e36c521be008893f40a0a7c349602cc178ea43be59d31ec6449e7ff2c5379379f7d7645134df1bc3
+d = 67fa50569257c8cc89ac0325db4902003a62f30b917f53e4035a7e04
+Qx = 6773a0436a9c42635730413b19aa4166f08c69c0e5002953da42253b
+Qy = 555138290b093bf2fe79acda9131d920cd1e7ac43fb8775776cd713c
+k = 557cb45fd3a30b3bdbf08c56eabbd4478736024aaa52bf8448096453
+R = 8e92cf7a674aa5f7542dd95c695589a05747431692edd04804299b8f
+S = af4908b41f8180b71a6ff10fd51f3d143147af6ddddf7534d3284ed9
+
+
+[P-256,SHA-224]
+
+Msg = ff624d0ba02c7b6370c1622eec3fa2186ea681d1659e0a845448e777b75a8e77a77bb26e5733179d58ef9bc8a4e8b6971aef2539f77ab0963a3415bbd6258339bd1bf55de65db520c63f5b8eab3d55debd05e9494212170f5d65b3286b8b668705b1e2b2b5568610617abb51d2dd0cb450ef59df4b907da90cfa7b268de8c4c2
+d = 708309a7449e156b0db70e5b52e606c7e094ed676ce8953bf6c14757c826f590
+Qx = 29578c7ab6ce0d11493c95d5ea05d299d536801ca9cbd50e9924e43b733b83ab
+Qy = 08c8049879c6278b2273348474158515accaa38344106ef96803c5a05adc4800
+k = 58f741771620bdc428e91a32d86d230873e9140336fcfb1e122892ee1d501bdc
+R = 4a19274429e40522234b8785dc25fc524f179dcc95ff09b3c9770fc71f54ca0d
+S = 58982b79a65b7320f5b92d13bdaecdd1259e760f0f718ba933fd098f6f75d4b7
+
+Msg = 9155e91fd9155eeed15afd83487ea1a3af04c5998b77c0fe8c43dcc479440a8a9a89efe883d9385cb9edfde10b43bce61fb63669935ad39419cf29ef3a936931733bfc2378e253e73b7ae9a3ec7a6a7932ab10f1e5b94d05160c053988f3bdc9167155d069337d42c9a7056619efc031fa5ec7310d29bd28980b1e3559757578
+d = 90c5386100b137a75b0bb495002b28697a451add2f1f22cb65f735e8aaeace98
+Qx = 4a92396ff7930b1da9a873a479a28a9896af6cc3d39345b949b726dc3cd978b5
+Qy = 475abb18eaed948879b9c1453e3ef2755dd90f77519ec7b6a30297aad08e4931
+k = 36f853b5c54b1ec61588c9c6137eb56e7a708f09c57513093e4ecf6d739900e5
+R = 38b29558511061cfabdc8e5bb65ac2976d1aa2ba9a5deab8074097b2172bb9ad
+S = 0de2cde610502b6e03c0b23602eafbcd3faf886c81d111d156b7aa550f5bcd51
+
+Msg = b242a7586a1383368a33c88264889adfa3be45422fbef4a2df4e3c5325a9c7757017e0d5cf4bbf4de7f99d189f81f1fd2f0dd645574d1eb0d547eead9375677819297c1abe62526ae29fc54cdd11bfe17714f2fbd2d0d0e8d297ff98535980482dd5c1ebdc5a7274aabf1382c9f2315ca61391e3943856e4c5e616c2f1f7be0d
+d = a3a43cece9c1abeff81099fb344d01f7d8df66447b95a667ee368f924bccf870
+Qx = 5775174deb0248112e069cb86f1546ac7a78bc2127d0cb953bad46384dd6be5b
+Qy = a27020952971cc0b0c3abd06e9ca3e141a4943f560564eba31e5288928bc7ce7
+k = a0d9a7a245bd9b9aa86cecb89341c9de2e4f9b5d095a8150826c7ba7fb3e7df7
+R = b02a440add66a9ff9c3c0e9acf1be678f6bd48a10cbdec2ad6d186ffe05f3f2a
+S = a98bea42aec56a1fcecec00a1cc69b01fcbcf5de7ac1b2f2dcc09b6db064f92b
+
+Msg = b64005da76b24715880af94dba379acc25a047b06066c9bedc8f17b8c74e74f4fc720d9f4ef0e2a659e0756931c080587ebdcd0f85e819aea6dacb327a9d96496da53ea21aef3b2e793a9c0def5196acec99891f46ead78a85bc7ab644765781d3543da9fbf9fec916dca975ef3b4271e50ecc68bf79b2d8935e2b25fc063358
+d = 7bbc8ff13f6f921f21e949b224c16b7176c5984d312b671cf6c2e4841135fc7f
+Qx = f888e913ec6f3cd8b31eb89e4f8aaa8887d30ae5348ed7118696949d5b8cc7c1
+Qy = 08895d09620500d244e5035e262dea3f2867cd8967b226324d5c05220d8b410c
+k = 21c942f3b487accbf7fadc1c4b7a6c7567ce876c195022459fa1ebf6d04ffbaa
+R = 2e6cc883b8acc904ee9691ef4a9f1f5a9e5fbfde847cda3be833f949fb9c7182
+S = 2ac48f7a930912131a8b4e3ab495307817c465d638c2a9ea5ae9e2808806e20a
+
+Msg = fe6e1ea477640655eaa1f6e3352d4bce53eb3d95424df7f238e93d8531da8f36bc35fa6be4bf5a6a382e06e855139eb617a9cc9376b4dafacbd80876343b12628619d7cbe1bff6757e3706111ed53898c0219823adbc044eaf8c6ad449df8f6aab9d444dadb5c3380eec0d91694df5fc4b30280d4b87d27e67ae58a1df828963
+d = daf5ec7a4eebc20d9485796c355b4a65ad254fe19b998d0507e91ea24135f45d
+Qx = 137c465085c1b1b8cccbe9fccbe9d0295a331aaf332f3ed2e285d16e574b943b
+Qy = d3e8d5a24cd218c19760b0e85b35a8569945aa857cbf0fd6a3ce127581b217b6
+k = 343251dffa56e6a612fec7b078f9c3819eab402a72686b894a47a08fd97e6c23
+R = 775e25a296bd259510ae9375f548997bec8a744900022945281dc8c4d94f2b5b
+S = d87592ceab773ae103daebbb56a04144aaccb1e14efc1024dc36c0e382df1f70
+
+Msg = 907c0c00dc080a688548957b5b8b1f33ba378de1368023dcad43242411f554eb7d392d3e5c1668fad3944ff9634105343d83b8c85d2a988da5f5dc60ee0518327caed6dd5cf4e9bc6222deb46d00abde745f9b71d6e7aee6c7fdfc9ed053f2c0b611d4c6863088bd012ea9810ee94f8e58905970ebd07353f1f409a371ed03e3
+d = 8729a8396f262dabd991aa404cc1753581cea405f0d19222a0b3f210de8ee3c5
+Qx = 82b1f1a7af9b48ca8452613d7032beb0e4f28fe710306aeccc959e4d03662a35
+Qy = 5e39f33574097b8d32b471a591972496f5d44db344c037d13f06fafc75f016fd
+k = 6de9e21f0b2cacc1762b3558fd44d3cf156b85dbef430dd28d59713bfb9cfa0b
+R = a754b42720e71925d51fcef76151405a3696cc8f9fc9ca7b46d0b16edd7fb699
+S = 603924780439cc16ac4cf97c2c3065bc95353aa9179d0ab5f0322ca82f851cf2
+
+Msg = 771c4d7bce05610a3e71b272096b57f0d1efcce33a1cb4f714d6ebc0865b2773ec5eedc25fae81dee1d256474dbd9676623614c150916e6ed92ce4430b26037d28fa5252ef6b10c09dc2f7ee5a36a1ea7897b69f389d9f5075e271d92f4eb97b148f3abcb1e5be0b4feb8278613d18abf6da60bfe448238aa04d7f11b71f44c5
+d = f1b62413935fc589ad2280f6892599ad994dae8ca3655ed4f7318cc89b61aa96
+Qx = e0bbfe4016eea93e6f509518cbffc25d492de6ebbf80465a461caa5bdc018159
+Qy = 3231ee7a119d84fa56e3034d50fea85929aec2eb437abc7646821e1bf805fb50
+k = 7a33eeb9f469afd55de2fb786847a1d3e7797929305c0f90d953b6f143bb8fc6
+R = 96d1c9399948254ea381631fc0f43ea808110506db8aacf081df5535ac5eb8ad
+S = 73bf3691260dddd9997c97313f2a70783eacf8d15bdfb34bb13025cdfae72f70
+
+Msg = a3b2825235718fc679b942e8ac38fb4f54415a213c65875b5453d18ca012320ddfbbc58b991eaebadfc2d1a28d4f0cd82652b12e4d5bfda89eda3be12ac52188e38e8cce32a264a300c0e463631f525ae501348594f980392c76b4a12ddc88e5ca086cb8685d03895919a8627725a3e00c4728e2b7c6f6a14fc342b2937fc3dd
+d = 4caaa26f93f009682bbba6db6b265aec17b7ec1542bda458e8550b9e68eed18d
+Qx = e3c58c1c254d11c7e781ad133e4c36dd1b5de362120d336a58e7b68813f3fbee
+Qy = 59760db66120afe0d962c81a8e5586588fd19de2f40556371611c73af22c8a68
+k = c0d37142dc8b0d614fad20c4d35af6eb819e259e513ddeac1e1c273e7e1dc1bb
+R = 25dd8e4086c62a40d2a310e2f90f6af5cb7e677b4dfdb4dc4e99e23ea2f0e6dc
+S = 90ad62c179b0c9d61f521dde1cd762bfd224b5525c39c3706f2549313ddb4f39
+
+Msg = 3e6e2a9bffd729ee5d4807849cd4250021d8184cda723df6ab0e5c939d39237c8e58af9d869fe62d3c97b3298a99e891e5e11aa68b11a087573a40a3e83c7965e7910d72f81cad0f42accc5c25a4fd3cdd8cee63757bbbfbdae98be2bc867d3bcb1333c4632cb0a55dffeb77d8b119c466cd889ec468454fabe6fbee7102deaf
+d = 7af4b150bb7167cb68037f280d0823ce5320c01a92b1b56ee1b88547481b1de9
+Qx = cb3634ec4f0cbb99986be788f889e586026d5a851e80d15382f1bdb1bda2bc75
+Qy = 51e4e43bc16fb114896b18198a1aebe6054ba20ed0c0317c1b8776158c0e6bfb
+k = 98edd59fafbcaee5f64e84eb5ed59fff45d14aabada47cee2fa674377173627a
+R = 261a1cdb0fd93c0fb06ea6068b6b03c330a12f621a7eba76682a1d152c0e8d08
+S = 7ca049bad54feee101d6db807635ffb8bdb05a38e445c8c3d65d60df143514c5
+
+Msg = 52e5c308e70329a17c71eaedb66bbee303c8ec48a6f1a2efb235d308563cd58553d434e12f353227a9ea28608ec9c820ed83c95124e7a886f7e832a2de1032e78dc059208f9ec354170b2b1cab992b52ac01e6c0e4e1b0112686962edc53ab226dafcc9fc7baed2cd9307160e8572edb125935db49289b178f35a8ad23f4f801
+d = 52ad53e849e30bec0e6345c3e9d98ebc808b19496c1ef16d72ab4a00bbb8c634
+Qx = 7cca1334bfc2a78728c50b370399be3f9690d445aa03c701da643eeb0b0f7fa8
+Qy = 3f7522238668e615405e49b2f63faee58286000a30cdb4b564ac0df99bc8950f
+k = 8650c30712fc253610884fbba4a332a4574d4b7822f7776cab1df8f5fa05442a
+R = a18194c7ac5829afc408d78dde19542837e7be82706c3941b2d9c5e036bb51e0
+S = 188ead1cdf7c1d21114ff56d0421ffd501ab978ef58337462c0fa736d86299af
+
+Msg = d3e9e82051d4c84d699453c9ff44c7c09f6523bb92232bcf30bf3c380224249de2964e871d56a364d6955c81ef91d06482a6c7c61bc70f66ef22fad128d15416e7174312619134f968f1009f92cbf99248932efb533ff113fb6d949e21d6b80dfbbe69010c8d1ccb0f3808ea309bb0bac1a222168c95b088847e613749b19d04
+d = 80754962a864be1803bc441fa331e126005bfc6d8b09ed38b7e69d9a030a5d27
+Qx = 0aaeed6dd1ae020d6eefc98ec4241ac93cbd3c8afed05bb28007e7da5727571b
+Qy = 2dda1d5b7872eb94dfffb456115037ff8d3e72f8ebdd8fcfc42391f96809be69
+k = 738e050aeefe54ecba5be5f93a97bbcb7557d701f9da2d7e88483454b97b55a8
+R = 8cb9f41dfdcb9604e0725ac9b78fc0db916dc071186ee982f6dba3da36f02efa
+S = 5c87fe868fd4282fb114f5d70e9590a10a5d35cedf3ff6402ba5c4344738a32e
+
+Msg = 968951c2c1918436fe19fa2fe2152656a08f9a6b8aa6201920f1b424da98cee71928897ff087620cc5c551320b1e75a1e98d7d98a5bd5361c9393759614a6087cc0f7fb01fcb173783eb4c4c23961a8231ac4a07d72e683b0c1bd4c51ef1b031df875e7b8d5a6e0628949f5b8f157f43dccaea3b2a4fc11181e6b451e06ceb37
+d = cfa8c8bd810eb0d73585f36280ecdd296ee098511be8ad5eac68984eca8eb19d
+Qx = c227a2af15dfa8734e11c0c50f77e24e77ed58dd8cccf1b0e9fa06bee1c64766
+Qy = b686592ce3745eb300d2704083db55e1fa8274e4cb7e256889ccc0bb34a60570
+k = 2d6b449bb38b543d6b6d34ff8cb053f5e5b337f949b069b21f421995ebb28823
+R = 5e89d3c9b103c2fa3cb8cebeec23640acda0257d63ffbe2d509bfc49fab1dca6
+S = d70c5b1eeb29e016af9925798d24e166c23d58fedd2f1a3bbdb1ef78cdbfb63a
+
+Msg = 78048628932e1c1cdd1e70932bd7b76f704ba08d7e7d825d3de763bf1a062315f4af16eccefe0b6ebadccaf403d013f50833ce2c54e24eea8345e25f93b69bb048988d102240225ceacf5003e2abdcc90299f4bf2c101585d36ecdd7a155953c674789d070480d1ef47cc7858e97a6d87c41c6922a00ea12539f251826e141b4
+d = b2021e2665ce543b7feadd0cd5a4bd57ffcc5b32deb860b4d736d9880855da3c
+Qx = 722e0abad4504b7832a148746153777694714eca220eced2b2156ca64cfed3dd
+Qy = f0351b357b3081e859c46cad5328c5afa10546e92bc6c3fd541796ac30397a75
+k = b15bbce4b382145de7ecd670d947e77555ef7cd1693bd53c694e2b52b04d10e1
+R = 9d086dcd22da165a43091991bede9c1c14515e656633cb759ec2c17f51c35253
+S = 23595ad1cb714559faaecaf946beb9a71e584616030ceaed8a8470f4bf62768f
+
+Msg = 9b0800c443e693067591737fdbcf0966fdfa50872d41d0c189d87cbc34c2771ee5e1255fd604f09fcf167fda16437c245d299147299c69046895d22482db29aba37ff57f756716cd3d6223077f747c4caffbecc0a7c9dfaaafd9a9817470ded8777e6355838ac54d11b2f0fc3f43668ff949cc31de0c2d15af5ef17884e4d66a
+d = 0c9bce6a568ca239395fc3552755575cbcdddb1d89f6f5ab354517a057b17b48
+Qx = 4814d454495df7103e2da383aba55f7842fd84f1750ee5801ad32c10d0be6c7d
+Qy = a0bd039d5097c8f0770477f6b18d247876e88e528bf0453eab515ffab8a9eda3
+k = d414f1525cdcc41eba1652de017c034ebcc7946cb2efe4713d09f67c85b83153
+R = 84db02c678f9a21208cec8564d145a35ba8c6f26b4eb7e19522e439720dae44c
+S = 537c564da0d2dc5ac4376c5f0ca3b628d01d48df47a83d842c927e4d6db1e16d
+
+Msg = fc3b8291c172dae635a6859f525beaf01cf683765d7c86f1a4d768df7cae055f639eccc08d7a0272394d949f82d5e12d69c08e2483e11a1d28a4c61f18193106e12e5de4a9d0b4bf341e2acd6b715dc83ae5ff63328f8346f35521ca378b311299947f63ec593a5e32e6bd11ec4edb0e75302a9f54d21226d23314729e061016
+d = 1daa385ec7c7f8a09adfcaea42801a4de4c889fb5c6eb4e92bc611d596d68e3f
+Qx = f04e9f2831d9697ae146c7d4552e5f91085cc46778400b75b76f00205252941d
+Qy = bd267148174cd0c2b019cd0a5256e2f3f889d1e597160372b5a1339c8d787f10
+k = 7707db348ee6f60365b43a2a994e9b40ed56fe03c2c31c7e781bc4ffadcba760
+R = 5d95c385eeba0f15db0b80ae151912409128c9c80e554246067b8f6a36d85ea5
+S = db5d8a1e345f883e4fcb3871276f170b783c1a1e9da6b6615913368a8526f1c3
+
+[P-256,SHA-256]
+
+Msg = 5905238877c77421f73e43ee3da6f2d9e2ccad5fc942dcec0cbd25482935faaf416983fe165b1a045ee2bcd2e6dca3bdf46c4310a7461f9a37960ca672d3feb5473e253605fb1ddfd28065b53cb5858a8ad28175bf9bd386a5e471ea7a65c17cc934a9d791e91491eb3754d03799790fe2d308d16146d5c9b0d0debd97d79ce8
+d = 519b423d715f8b581f4fa8ee59f4771a5b44c8130b4e3eacca54a56dda72b464
+Qx = 1ccbe91c075fc7f4f033bfa248db8fccd3565de94bbfb12f3c59ff46c271bf83
+Qy = ce4014c68811f9a21a1fdb2c0e6113e06db7ca93b7404e78dc7ccd5ca89a4ca9
+k = 94a1bbb14b906a61a280f245f9e93c7f3b4a6247824f5d33b9670787642a68de
+R = f3ac8061b514795b8843e3d6629527ed2afd6b1f6a555a7acabb5e6f79c8c2ac
+S = 8bf77819ca05a6b2786c76262bf7371cef97b218e96f175a3ccdda2acc058903
+
+Msg = c35e2f092553c55772926bdbe87c9796827d17024dbb9233a545366e2e5987dd344deb72df987144b8c6c43bc41b654b94cc856e16b96d7a821c8ec039b503e3d86728c494a967d83011a0e090b5d54cd47f4e366c0912bc808fbb2ea96efac88fb3ebec9342738e225f7c7c2b011ce375b56621a20642b4d36e060db4524af1
+d = 0f56db78ca460b055c500064824bed999a25aaf48ebb519ac201537b85479813
+Qx = e266ddfdc12668db30d4ca3e8f7749432c416044f2d2b8c10bf3d4012aeffa8a
+Qy = bfa86404a2e9ffe67d47c587ef7a97a7f456b863b4d02cfc6928973ab5b1cb39
+k = 6d3e71882c3b83b156bb14e0ab184aa9fb728068d3ae9fac421187ae0b2f34c6
+R = 976d3a4e9d23326dc0baa9fa560b7c4e53f42864f508483a6473b6a11079b2db
+S = 1b766e9ceb71ba6c01dcd46e0af462cd4cfa652ae5017d4555b8eeefe36e1932
+
+Msg = 3c054e333a94259c36af09ab5b4ff9beb3492f8d5b4282d16801daccb29f70fe61a0b37ffef5c04cd1b70e85b1f549a1c4dc672985e50f43ea037efa9964f096b5f62f7ffdf8d6bfb2cc859558f5a393cb949dbd48f269343b5263dcdb9c556eca074f2e98e6d94c2c29a677afaf806edf79b15a3fcd46e7067b7669f83188ee
+d = e283871239837e13b95f789e6e1af63bf61c918c992e62bca040d64cad1fc2ef
+Qx = 74ccd8a62fba0e667c50929a53f78c21b8ff0c3c737b0b40b1750b2302b0bde8
+Qy = 29074e21f3a0ef88b9efdf10d06aa4c295cc1671f758ca0e4cd108803d0f2614
+k = ad5e887eb2b380b8d8280ad6e5ff8a60f4d26243e0124c2f31a297b5d0835de2
+R = 35fb60f5ca0f3ca08542fb3cc641c8263a2cab7a90ee6a5e1583fac2bb6f6bd1
+S = ee59d81bc9db1055cc0ed97b159d8784af04e98511d0a9a407b99bb292572e96
+
+Msg = 0989122410d522af64ceb07da2c865219046b4c3d9d99b01278c07ff63eaf1039cb787ae9e2dd46436cc0415f280c562bebb83a23e639e476a02ec8cff7ea06cd12c86dcc3adefbf1a9e9a9b6646c7599ec631b0da9a60debeb9b3e19324977f3b4f36892c8a38671c8e1cc8e50fcd50f9e51deaf98272f9266fc702e4e57c30
+d = a3d2d3b7596f6592ce98b4bfe10d41837f10027a90d7bb75349490018cf72d07
+Qx = 322f80371bf6e044bc49391d97c1714ab87f990b949bc178cb7c43b7c22d89e1
+Qy = 3c15d54a5cc6b9f09de8457e873eb3deb1fceb54b0b295da6050294fae7fd999
+k = 24fc90e1da13f17ef9fe84cc96b9471ed1aaac17e3a4bae33a115df4e5834f18
+R = d7c562370af617b581c84a2468cc8bd50bb1cbf322de41b7887ce07c0e5884ca
+S = b46d9f2d8c4bf83546ff178f1d78937c008d64e8ecc5cbb825cb21d94d670d89
+
+Msg = dc66e39f9bbfd9865318531ffe9207f934fa615a5b285708a5e9c46b7775150e818d7f24d2a123df3672fff2094e3fd3df6fbe259e3989dd5edfcccbe7d45e26a775a5c4329a084f057c42c13f3248e3fd6f0c76678f890f513c32292dd306eaa84a59abe34b16cb5e38d0e885525d10336ca443e1682aa04a7af832b0eee4e7
+d = 53a0e8a8fe93db01e7ae94e1a9882a102ebd079b3a535827d583626c272d280d
+Qx = 1bcec4570e1ec2436596b8ded58f60c3b1ebc6a403bc5543040ba82963057244
+Qy = 8af62a4c683f096b28558320737bf83b9959a46ad2521004ef74cf85e67494e1
+k = 5d833e8d24cc7a402d7ee7ec852a3587cddeb48358cea71b0bedb8fabe84e0c4
+R = 18caaf7b663507a8bcd992b836dec9dc5703c080af5e51dfa3a9a7c387182604
+S = 77c68928ac3b88d985fb43fb615fb7ff45c18ba5c81af796c613dfa98352d29c
+
+Msg = 600974e7d8c5508e2c1aab0783ad0d7c4494ab2b4da265c2fe496421c4df238b0be25f25659157c8a225fb03953607f7df996acfd402f147e37aee2f1693e3bf1c35eab3ae360a2bd91d04622ea47f83d863d2dfecb618e8b8bdc39e17d15d672eee03bb4ce2cc5cf6b217e5faf3f336fdd87d972d3a8b8a593ba85955cc9d71
+d = 4af107e8e2194c830ffb712a65511bc9186a133007855b49ab4b3833aefc4a1d
+Qx = a32e50be3dae2c8ba3f5e4bdae14cf7645420d425ead94036c22dd6c4fc59e00
+Qy = d623bf641160c289d6742c6257ae6ba574446dd1d0e74db3aaa80900b78d4ae9
+k = e18f96f84dfa2fd3cdfaec9159d4c338cd54ad314134f0b31e20591fc238d0ab
+R = 8524c5024e2d9a73bde8c72d9129f57873bbad0ed05215a372a84fdbc78f2e68
+S = d18c2caf3b1072f87064ec5e8953f51301cada03469c640244760328eb5a05cb
+
+Msg = dfa6cb9b39adda6c74cc8b2a8b53a12c499ab9dee01b4123642b4f11af336a91a5c9ce0520eb2395a6190ecbf6169c4cba81941de8e76c9c908eb843b98ce95e0da29c5d4388040264e05e07030a577cc5d176387154eabae2af52a83e85c61c7c61da930c9b19e45d7e34c8516dc3c238fddd6e450a77455d534c48a152010b
+d = 78dfaa09f1076850b3e206e477494cddcfb822aaa0128475053592c48ebaf4ab
+Qx = 8bcfe2a721ca6d753968f564ec4315be4857e28bef1908f61a366b1f03c97479
+Qy = 0f67576a30b8e20d4232d8530b52fb4c89cbc589ede291e499ddd15fe870ab96
+k = 295544dbb2da3da170741c9b2c6551d40af7ed4e891445f11a02b66a5c258a77
+R = c5a186d72df452015480f7f338970bfe825087f05c0088d95305f87aacc9b254
+S = 84a58f9e9d9e735344b316b1aa1ab5185665b85147dc82d92e969d7bee31ca30
+
+Msg = 51d2547cbff92431174aa7fc7302139519d98071c755ff1c92e4694b58587ea560f72f32fc6dd4dee7d22bb7387381d0256e2862d0644cdf2c277c5d740fa089830eb52bf79d1e75b8596ecf0ea58a0b9df61e0c9754bfcd62efab6ea1bd216bf181c5593da79f10135a9bc6e164f1854bc8859734341aad237ba29a81a3fc8b
+d = 80e692e3eb9fcd8c7d44e7de9f7a5952686407f90025a1d87e52c7096a62618a
+Qx = a88bc8430279c8c0400a77d751f26c0abc93e5de4ad9a4166357952fe041e767
+Qy = 2d365a1eef25ead579cc9a069b6abc1b16b81c35f18785ce26a10ba6d1381185
+k = 7c80fd66d62cc076cef2d030c17c0a69c99611549cb32c4ff662475adbe84b22
+R = 9d0c6afb6df3bced455b459cc21387e14929392664bb8741a3693a1795ca6902
+S = d7f9ddd191f1f412869429209ee3814c75c72fa46a9cccf804a2f5cc0b7e739f
+
+Msg = 558c2ac13026402bad4a0a83ebc9468e50f7ffab06d6f981e5db1d082098065bcff6f21a7a74558b1e8612914b8b5a0aa28ed5b574c36ac4ea5868432a62bb8ef0695d27c1e3ceaf75c7b251c65ddb268696f07c16d2767973d85beb443f211e6445e7fe5d46f0dce70d58a4cd9fe70688c035688ea8c6baec65a5fc7e2c93e8
+d = 5e666c0db0214c3b627a8e48541cc84a8b6fd15f300da4dff5d18aec6c55b881
+Qx = 1bc487570f040dc94196c9befe8ab2b6de77208b1f38bdaae28f9645c4d2bc3a
+Qy = ec81602abd8345e71867c8210313737865b8aa186851e1b48eaca140320f5d8f
+k = 2e7625a48874d86c9e467f890aaa7cd6ebdf71c0102bfdcfa24565d6af3fdce9
+R = 2f9e2b4e9f747c657f705bffd124ee178bbc5391c86d056717b140c153570fd9
+S = f5413bfd85949da8d83de83ab0d19b2986613e224d1901d76919de23ccd03199
+
+Msg = 4d55c99ef6bd54621662c3d110c3cb627c03d6311393b264ab97b90a4b15214a5593ba2510a53d63fb34be251facb697c973e11b665cb7920f1684b0031b4dd370cb927ca7168b0bf8ad285e05e9e31e34bc24024739fdc10b78586f29eff94412034e3b606ed850ec2c1900e8e68151fc4aee5adebb066eb6da4eaa5681378e
+d = f73f455271c877c4d5334627e37c278f68d143014b0a05aa62f308b2101c5308
+Qx = b8188bd68701fc396dab53125d4d28ea33a91daf6d21485f4770f6ea8c565dde
+Qy = 423f058810f277f8fe076f6db56e9285a1bf2c2a1dae145095edd9c04970bc4a
+k = 62f8665fd6e26b3fa069e85281777a9b1f0dfd2c0b9f54a086d0c109ff9fd615
+R = 1cc628533d0004b2b20e7f4baad0b8bb5e0673db159bbccf92491aef61fc9620
+S = 880e0bbf82a8cf818ed46ba03cf0fc6c898e36fca36cc7fdb1d2db7503634430
+
+Msg = f8248ad47d97c18c984f1f5c10950dc1404713c56b6ea397e01e6dd925e903b4fadfe2c9e877169e71ce3c7fe5ce70ee4255d9cdc26f6943bf48687874de64f6cf30a012512e787b88059bbf561162bdcc23a3742c835ac144cc14167b1bd6727e940540a9c99f3cbb41fb1dcb00d76dda04995847c657f4c19d303eb09eb48a
+d = b20d705d9bd7c2b8dc60393a5357f632990e599a0975573ac67fd89b49187906
+Qx = 51f99d2d52d4a6e734484a018b7ca2f895c2929b6754a3a03224d07ae61166ce
+Qy = 4737da963c6ef7247fb88d19f9b0c667cac7fe12837fdab88c66f10d3c14cad1
+k = 72b656f6b35b9ccbc712c9f1f3b1a14cbbebaec41c4bca8da18f492a062d6f6f
+R = 9886ae46c1415c3bc959e82b760ad760aab66885a84e620aa339fdf102465c42
+S = 2bf3a80bc04faa35ebecc0f4864ac02d349f6f126e0f988501b8d3075409a26c
+
+Msg = 3b6ee2425940b3d240d35b97b6dcd61ed3423d8e71a0ada35d47b322d17b35ea0472f35edd1d252f87b8b65ef4b716669fc9ac28b00d34a9d66ad118c9d94e7f46d0b4f6c2b2d339fd6bcd351241a387cc82609057048c12c4ec3d85c661975c45b300cb96930d89370a327c98b67defaa89497aa8ef994c77f1130f752f94a4
+d = d4234bebfbc821050341a37e1240efe5e33763cbbb2ef76a1c79e24724e5a5e7
+Qx = 8fb287f0202ad57ae841aea35f29b2e1d53e196d0ddd9aec24813d64c0922fb7
+Qy = 1f6daff1aa2dd2d6d3741623eecb5e7b612997a1039aab2e5cf2de969cfea573
+k = d926fe10f1bfd9855610f4f5a3d666b1a149344057e35537373372ead8b1a778
+R = 490efd106be11fc365c7467eb89b8d39e15d65175356775deab211163c2504cb
+S = 644300fc0da4d40fb8c6ead510d14f0bd4e1321a469e9c0a581464c7186b7aa7
+
+Msg = c5204b81ec0a4df5b7e9fda3dc245f98082ae7f4efe81998dcaa286bd4507ca840a53d21b01e904f55e38f78c3757d5a5a4a44b1d5d4e480be3afb5b394a5d2840af42b1b4083d40afbfe22d702f370d32dbfd392e128ea4724d66a3701da41ae2f03bb4d91bb946c7969404cb544f71eb7a49eb4c4ec55799bda1eb545143a7
+d = b58f5211dff440626bb56d0ad483193d606cf21f36d9830543327292f4d25d8c
+Qx = 68229b48c2fe19d3db034e4c15077eb7471a66031f28a980821873915298ba76
+Qy = 303e8ee3742a893f78b810991da697083dd8f11128c47651c27a56740a80c24c
+k = e158bf4a2d19a99149d9cdb879294ccb7aaeae03d75ddd616ef8ae51a6dc1071
+R = e67a9717ccf96841489d6541f4f6adb12d17b59a6bef847b6183b8fcf16a32eb
+S = 9ae6ba6d637706849a6a9fc388cf0232d85c26ea0d1fe7437adb48de58364333
+
+Msg = 72e81fe221fb402148d8b7ab03549f1180bcc03d41ca59d7653801f0ba853add1f6d29edd7f9abc621b2d548f8dbf8979bd16608d2d8fc3260b4ebc0dd42482481d548c7075711b5759649c41f439fad69954956c9326841ea6492956829f9e0dc789f73633b40f6ac77bcae6dfc7930cfe89e526d1684365c5b0be2437fdb01
+d = 54c066711cdb061eda07e5275f7e95a9962c6764b84f6f1f3ab5a588e0a2afb1
+Qx = 0a7dbb8bf50cb605eb2268b081f26d6b08e012f952c4b70a5a1e6e7d46af98bb
+Qy = f26dd7d799930062480849962ccf5004edcfd307c044f4e8f667c9baa834eeae
+k = 646fe933e96c3b8f9f507498e907fdd201f08478d0202c752a7c2cfebf4d061a
+R = b53ce4da1aa7c0dc77a1896ab716b921499aed78df725b1504aba1597ba0c64b
+S = d7c246dc7ad0e67700c373edcfdd1c0a0495fc954549ad579df6ed1438840851
+
+Msg = 21188c3edd5de088dacc1076b9e1bcecd79de1003c2414c3866173054dc82dde85169baa77993adb20c269f60a5226111828578bcc7c29e6e8d2dae81806152c8ba0c6ada1986a1983ebeec1473a73a04795b6319d48662d40881c1723a706f516fe75300f92408aa1dc6ae4288d2046f23c1aa2e54b7fb6448a0da922bd7f34
+d = 34fa4682bf6cb5b16783adcd18f0e6879b92185f76d7c920409f904f522db4b1
+Qx = 105d22d9c626520faca13e7ced382dcbe93498315f00cc0ac39c4821d0d73737
+Qy = 6c47f3cbbfa97dfcebe16270b8c7d5d3a5900b888c42520d751e8faf3b401ef4
+k = a6f463ee72c9492bc792fe98163112837aebd07bab7a84aaed05be64db3086f4
+R = 542c40a18140a6266d6f0286e24e9a7bad7650e72ef0e2131e629c076d962663
+S = 4f7f65305e24a6bbb5cff714ba8f5a2cee5bdc89ba8d75dcbf21966ce38eb66f
+
+[P-256,SHA-384]
+
+Msg = e0b8596b375f3306bbc6e77a0b42f7469d7e83635990e74aa6d713594a3a24498feff5006790742d9c2e9b47d714bee932435db747c6e733e3d8de41f2f91311f2e9fd8e025651631ffd84f66732d3473fbd1627e63dc7194048ebec93c95c159b5039ab5e79e42c80b484a943f125de3da1e04e5bf9c16671ad55a1117d3306
+d = b6faf2c8922235c589c27368a3b3e6e2f42eb6073bf9507f19eed0746c79dced
+Qx = e0e7b99bc62d8dd67883e39ed9fa0657789c5ff556cc1fd8dd1e2a55e9e3f243
+Qy = 63fbfd0232b95578075c903a4dbf85ad58f8350516e1ec89b0ee1f5e1362da69
+k = 9980b9cdfcef3ab8e219b9827ed6afdd4dbf20bd927e9cd01f15762703487007
+R = f5087878e212b703578f5c66f434883f3ef414dc23e2e8d8ab6a8d159ed5ad83
+S = 306b4c6c20213707982dffbb30fba99b96e792163dd59dbe606e734328dd7c8a
+
+Msg = 099a0131179fff4c6928e49886d2fdb3a9f239b7dd5fa828a52cbbe3fcfabecfbba3e192159b887b5d13aa1e14e6a07ccbb21f6ad8b7e88fee6bea9b86dea40ffb962f38554056fb7c5bb486418915f7e7e9b9033fe3baaf9a069db98bc02fa8af3d3d1859a11375d6f98aa2ce632606d0800dff7f55b40f971a8586ed6b39e9
+d = 118958fd0ff0f0b0ed11d3cf8fa664bc17cdb5fed1f4a8fc52d0b1ae30412181
+Qx = afda82260c9f42122a3f11c6058839488f6d7977f6f2a263c67d06e27ea2c355
+Qy = 0ae2bbdd2207c590332c5bfeb4c8b5b16622134bd4dc55382ae806435468058b
+k = 23129a99eeda3d99a44a5778a46e8e7568b91c31fb7a8628c5d9820d4bed4a6b
+R = e446600cab1286ebc3bb332012a2f5cc33b0a5ef7291d5a62a84de5969d77946
+S = cf89b12793ee1792eb26283b48fa0bdcb45ae6f6ad4b02564bf786bb97057d5a
+
+Msg = 0fbc07ea947c946bea26afa10c51511039b94ddbc4e2e4184ca3559260da24a14522d1497ca5e77a5d1a8e86583aeea1f5d4ff9b04a6aa0de79cd88fdb85e01f171143535f2f7c23b050289d7e05cebccdd131888572534bae0061bdcc3015206b9270b0d5af9f1da2f9de91772d178a632c3261a1e7b3fb255608b3801962f9
+d = 3e647357cd5b754fad0fdb876eaf9b1abd7b60536f383c81ce5745ec80826431
+Qx = 702b2c94d039e590dd5c8f9736e753cf5824aacf33ee3de74fe1f5f7c858d5ed
+Qy = 0c28894e907af99fb0d18c9e98f19ac80dd77abfa4bebe45055c0857b82a0f4d
+k = 9beab7722f0bcb468e5f234e074170a60225255de494108459abdf603c6e8b35
+R = c4021fb7185a07096547af1fb06932e37cf8bd90cf593dea48d48614fa237e5e
+S = 7fb45d09e2172bec8d3e330aa06c43fbb5f625525485234e7714b7f6e92ba8f1
+
+Msg = 1e38d750d936d8522e9db1873fb4996bef97f8da3c6674a1223d29263f1234a90b751785316444e9ba698bc8ab6cd010638d182c9adad4e334b2bd7529f0ae8e9a52ad60f59804b2d780ed52bdd33b0bf5400147c28b4304e5e3434505ae7ce30d4b239e7e6f0ecf058badd5b388eddbad64d24d2430dd04b4ddee98f972988f
+d = 76c17c2efc99891f3697ba4d71850e5816a1b65562cc39a13da4b6da9051b0fd
+Qx = d12512e934c367e4c4384dbd010e93416840288a0ba00b299b4e7c0d91578b57
+Qy = ebf8835661d9b578f18d14ae4acf9c357c0dc8b7112fc32824a685ed72754e23
+k = 77cffa6f9a73904306f9fcd3f6bbb37f52d71e39931bb4aec28f9b076e436ccf
+R = 4d5a9d95b0f09ce8704b0f457b39059ee606092310df65d3f8ae7a2a424cf232
+S = 7d3c014ca470a73cef1d1da86f2a541148ad542fbccaf9149d1b0b030441a7eb
+
+Msg = abcf0e0f046b2e0672d1cc6c0a114905627cbbdefdf9752f0c31660aa95f2d0ede72d17919a9e9b1add3213164e0c9b5ae3c76f1a2f79d3eeb444e6741521019d8bd5ca391b28c1063347f07afcfbb705be4b52261c19ebaf1d6f054a74d86fb5d091fa7f229450996b76f0ada5f977b09b58488eebfb5f5e9539a8fd89662ab
+d = 67b9dea6a575b5103999efffce29cca688c781782a41129fdecbce76608174de
+Qx = b4238b029fc0b7d9a5286d8c29b6f3d5a569e9108d44d889cd795c4a385905be
+Qy = 8cb3fff8f6cca7187c6a9ad0a2b1d9f40ae01b32a7e8f8c4ca75d71a1fffb309
+k = d02617f26ede3584f0afcfc89554cdfb2ae188c192092fdde3436335fafe43f1
+R = 26fd9147d0c86440689ff2d75569795650140506970791c90ace0924b44f1586
+S = 00a34b00c20a8099df4b0a757cbef8fea1cb3ea7ced5fbf7e987f70b25ee6d4f
+
+Msg = dc3d4884c741a4a687593c79fb4e35c5c13c781dca16db561d7e393577f7b62ca41a6e259fc1fb8d0c4e1e062517a0fdf95558b7799f20c211796167953e6372c11829beec64869d67bf3ee1f1455dd87acfbdbcc597056e7fb347a17688ad32fda7ccc3572da7677d7255c261738f07763cd45973c728c6e9adbeecadc3d961
+d = ecf644ea9b6c3a04fdfe2de4fdcb55fdcdfcf738c0b3176575fa91515194b566
+Qx = c3bdc7c795ec94620a2cfff614c13a3390a5e86c892e53a24d3ed22228bc85bf
+Qy = 70480fc5cf4aacd73e24618b61b5c56c1ced8c4f1b869580ea538e68c7a61ca3
+k = 53291d51f68d9a12d1dcdc58892b2f786cc15f631f16997d2a49bace513557d4
+R = a860c8b286edf973ce4ce4cf6e70dc9bbf3818c36c023a845677a9963705df8b
+S = 5630f986b1c45e36e127dd7932221c4272a8cc6e255e89f0f0ca4ec3a9f76494
+
+Msg = 719bf1911ae5b5e08f1d97b92a5089c0ab9d6f1c175ac7199086aeeaa416a17e6d6f8486c711d386f284f096296689a54d330c8efb0f5fa1c5ba128d3234a3da856c2a94667ef7103616a64c913135f4e1dc50e38daa60610f732ad1bedfcc396f87169392520314a6b6b9af6793dbabad4599525228cc7c9c32c4d8e097ddf6
+d = 4961485cbc978f8456ec5ac7cfc9f7d9298f99415ecae69c8491b258c029bfee
+Qx = 8d40bf2299e05d758d421972e81cfb0cce68b949240dc30f315836acc70bef03
+Qy = 5674e6f77f8b46f46cca937d83b128dffbe9bd7e0d3d08aa2cbbfdfb16f72c9a
+k = 373a825b5a74b7b9e02f8d4d876b577b4c3984168d704ba9f95b19c05ed590af
+R = ef6fb386ad044b63feb7445fa16b10319018e9cea9ef42bca83bdad01992234a
+S = ac1f42f652eb1786e57be01d847c81f7efa072ba566d4583af4f1551a3f76c65
+
+Msg = 7cf19f4c851e97c5bca11a39f0074c3b7bd3274e7dd75d0447b7b84995dfc9f716bf08c25347f56fcc5e5149cb3f9cfb39d408ace5a5c47e75f7a827fa0bb9921bb5b23a6053dbe1fa2bba341ac874d9b1333fc4dc224854949f5c8d8a5fedd02fb26fdfcd3be351aec0fcbef18972956c6ec0effaf057eb4420b6d28e0c008c
+d = 587907e7f215cf0d2cb2c9e6963d45b6e535ed426c828a6ea2fb637cca4c5cbd
+Qx = 660da45c413cc9c9526202c16b402af602d30daaa7c342f1e722f15199407f31
+Qy = e6f8cbb06913cc718f2d69ba2fb3137f04a41c27c676d1a80fbf30ea3ca46439
+k = 6b8eb7c0d8af9456b95dd70561a0e902863e6dfa1c28d0fd4a0509f1c2a647b2
+R = 08fabf9b57de81875bfa7a4118e3e44cfb38ec6a9b2014940207ba3b1c583038
+S = a58d199b1deba7350616230d867b2747a3459421811c291836abee715b8f67b4
+
+Msg = b892ffabb809e98a99b0a79895445fc734fa1b6159f9cddb6d21e510708bdab6076633ac30aaef43db566c0d21f4381db46711fe3812c5ce0fb4a40e3d5d8ab24e4e82d3560c6dc7c37794ee17d4a144065ef99c8d1c88bc22ad8c4c27d85ad518fa5747ae35276fc104829d3f5c72fc2a9ea55a1c3a87007cd133263f79e405
+d = 24b1e5676d1a9d6b645a984141a157c124531feeb92d915110aef474b1e27666
+Qx = b4909a5bdf25f7659f4ef35e4b811429fb2c59126e3dad09100b46aea6ebe7a6
+Qy = 760ae015fa6af5c9749c4030fdb5de6e58c6b5b1944829105cf7edf7d3a22cfb
+k = 88794923d8943b5dbcc7a7a76503880ff7da632b0883aaa60a9fcc71bf880fd6
+R = 6ec9a340b77fae3c7827fa96d997e92722ff2a928217b6dd3c628f3d49ae4ce6
+S = 637b54bbcfb7e7d8a41ea317fcfca8ad74eb3bb6b778bc7ef9dec009281976f7
+
+Msg = 8144e37014c95e13231cbd6fa64772771f93b44e37f7b02f592099cc146343edd4f4ec9fa1bc68d7f2e9ee78fc370443aa2803ff4ca52ee49a2f4daf2c8181ea7b8475b3a0f608fc3279d09e2d057fbe3f2ffbe5133796124781299c6da60cfe7ecea3abc30706ded2cdf18f9d788e59f2c31662df3abe01a9b12304fb8d5c8c
+d = bce49c7b03dcdc72393b0a67cf5aa5df870f5aaa6137ada1edc7862e0981ec67
+Qx = c786d9421d67b72b922cf3def2a25eeb5e73f34543eb50b152e738a98afb0ca5
+Qy = 6796271e79e2496f9e74b126b1123a3d067de56b5605d6f51c8f6e1d5bb93aba
+k = 89e690d78a5e0d2b8ce9f7fcbf34e2605fd9584760fa7729043397612dd21f94
+R = 07e5054c384839584624e8d730454dc27e673c4a90cbf129d88b91250341854d
+S = f7e665b88614d0c5cbb3007cafe713763d81831525971f1747d92e4d1ca263a7
+
+Msg = a3683d120807f0a030feed679785326698c3702f1983eaba1b70ddfa7f0b3188060b845e2b67ed57ee68087746710450f7427cb34655d719c0acbc09ac696adb4b22aba1b9322b7111076e67053a55f62b501a4bca0ad9d50a868f51aeeb4ef27823236f5267e8da83e143047422ce140d66e05e44dc84fb3a4506b2a5d7caa8
+d = 73188a923bc0b289e81c3db48d826917910f1b957700f8925425c1fb27cabab9
+Qx = 86662c014ab666ee770723be8da38c5cd299efc6480fc6f8c3603438fa8397b9
+Qy = f26b3307a650c3863faaa5f642f3ba1384c3d3a02edd3d48c657c269609cc3fc
+k = ec90584ab3b383b590626f36ed4f5110e49888aec7ae7a9c5ea62dd2dc378666
+R = 13e9ad59112fde3af4163eb5c2400b5e9a602576d5869ac1c569075f08c90ff6
+S = 708ac65ff2b0baaccc6dd954e2a93df46016bd04457636de06798fcc17f02be5
+
+Msg = b1df8051b213fc5f636537e37e212eb20b2423e6467a9c7081336a870e6373fc835899d59e546c0ac668cc81ce4921e88f42e6da2a109a03b4f4e819a17c955b8d099ec6b282fb495258dca13ec779c459da909475519a3477223c06b99afbd77f9922e7cbef844b93f3ce5f50db816b2e0d8b1575d2e17a6b8db9111d6da578
+d = f637d55763fe819541588e0c603f288a693cc66823c6bb7b8e003bd38580ebce
+Qx = 74a4620c578601475fc169a9b84be613b4a16cb6acab8fd98848a6ec9fbd133d
+Qy = 42b9e35d347c107e63bd55f525f915bcf1e3d2b81d002d3c39acf10fc30645a1
+k = 4d578f5099636234d9c1d566f1215d5d887ae5d47022be17dbf32a11a03f053b
+R = 113a933ebc4d94ce1cef781e4829df0c493b0685d39fb2048ce01b21c398dbba
+S = 3005bd4ec63dbd04ce9ff0c6246ad65d27fcf62edb2b7e461589f9f0e7446ffd
+
+Msg = 0b918ede985b5c491797d0a81446b2933be312f419b212e3aae9ba5914c00af431747a9d287a7c7761e9bcbc8a12aaf9d4a76d13dad59fc742f8f218ef66eb67035220a07acc1a357c5b562ecb6b895cf725c4230412fefac72097f2c2b829ed58742d7c327cad0f1058df1bddd4ae9c6d2aba25480424308684cecd6517cdd8
+d = 2e357d51517ff93b821f895932fddded8347f32596b812308e6f1baf7dd8a47f
+Qx = 7e4078a1d50c669fb2996dd9bacb0c3ac7ede4f58fa0fa1222e78dbf5d1f4186
+Qy = 0014e46e90cc171fbb83ea34c6b78202ea8137a7d926f0169147ed5ae3d6596f
+k = be522b0940b9a40d84bf790fe6abdc252877e671f2efa63a33a65a512fc2aa5c
+R = a26b9ad775ac37ff4c7f042cdc4872c5e4e5e800485f488ddfaaed379f468090
+S = f88eae2019bebbba62b453b8ee3472ca5c67c267964cffe0cf2d2933c1723dff
+
+Msg = 0fab26fde1a4467ca930dbe513ccc3452b70313cccde2994eead2fde85c8da1db84d7d06a024c9e88629d5344224a4eae01b21a2665d5f7f36d5524bf5367d7f8b6a71ea05d413d4afde33777f0a3be49c9e6aa29ea447746a9e77ce27232a550b31dd4e7c9bc8913485f2dc83a56298051c92461fd46b14cc895c300a4fb874
+d = 77d60cacbbac86ab89009403c97289b5900466856887d3e6112af427f7f0f50b
+Qx = a62032dfdb87e25ed0c70cad20d927c7effeb2638e6c88ddd670f74df16090e5
+Qy = 44c5ee2cf740ded468f5d2efe13daa7c5234645a37c073af35330d03a4fed976
+k = 06c1e692b045f425a21347ecf72833d0242906c7c1094f805566cdcb1256e394
+R = eb173b51fb0aec318950d097e7fda5c34e529519631c3e2c9b4550b903da417d
+S = ca2c13574bf1b7d56e9dc18315036a31b8bceddf3e2c2902dcb40f0cc9e31b45
+
+Msg = 7843f157ef8566722a7d69da67de7599ee65cb3975508f70c612b3289190e364141781e0b832f2d9627122742f4b5871ceeafcd09ba5ec90cae6bcc01ae32b50f13f63918dfb5177df9797c6273b92d103c3f7a3fc2050d2b196cc872c57b77f9bdb1782d4195445fcc6236dd8bd14c8bcbc8223a6739f6a17c9a861e8c821a6
+d = 486854e77962117f49e09378de6c9e3b3522fa752b10b2c810bf48db584d7388
+Qx = 760b5624bd64d19c866e54ccd74ad7f98851afdbc3ddeae3ec2c52a135be9cfa
+Qy = feca15ce9350877102eee0f5af18b2fed89dc86b7df0bf7bc2963c1638e36fe8
+k = e4f77c6442eca239b01b0254e11a4182782d96f48ab521cc3d1d68df12b5a41a
+R = bdff14e4600309c2c77f79a25963a955b5b500a7b2d34cb172cd6acd52905c7b
+S = b0479cdb3df79923ec36a104a129534c5d59f622be7d613aa04530ad2507d3a2
+
+[P-256,SHA-512]
+
+Msg = 6c8572b6a3a4a9e8e03dbeed99334d41661b8a8417074f335ab1845f6cc852adb8c01d9820fcf8e10699cc827a8fbdca2cbd46cc66e4e6b7ba41ec3efa733587e4a30ec552cd8ddab8163e148e50f4d090782897f3ddac84a41e1fcfe8c56b6152c0097b0d634b41011471ffd004f43eb4aafc038197ec6bae2b4470e869bded
+d = 9dd0d3a3d514c2a8adb162b81e3adfba3299309f7d2018f607bdb15b1a25f499
+Qx = 6b738de3398b6ac57b9591f9d7985dd4f32137ad3460dcf8970c1390cb9eaf8d
+Qy = 83bc61e26d2bbbd3cf2d2ab445a2bc4ab5dde41f4a13078fd1d3cc36ab596d57
+k = 9106192170ccb3c64684d48287bb81bbed51b40d503462c900e5c7aae43e380a
+R = 275fa760878b4dc05e9d157fedfd8e9b1c9c861222a712748cb4b7754c043fb1
+S = 699d906bb8435a05345af3b37e3b357786939e94caae257852f0503adb1e0f7e
+
+Msg = 7e3c8fe162d48cc8c5b11b5e5ebc05ebc45c439bdbc0b0902145921b8383037cb0812222031598cd1a56fa71694fbd304cc62938233465ec39c6e49f57dfe823983b6923c4e865633949183e6b90e9e06d8275f3907d97967d47b6239fe2847b7d49cf16ba69d2862083cf1bccf7afe34fdc90e21998964107b64abe6b89d126
+d = f9bf909b7973bf0e3dad0e43dcb2d7fa8bda49dbe6e5357f8f0e2bd119be30e6
+Qx = f2a6674d4e86152a527199bed293fa63acde1b4d8a92b62e552210ba45c38792
+Qy = c72565c24f0eee6a094af341ddd8579747b865f91c8ed5b44cda8a19cc93776f
+k = e547791f7185850f03d0c58419648f65b9d29cdc22ed1de2a64280220cfcafba
+R = 4782903d2aaf8b190dab5cae2223388d2d8bd845b3875d37485c54e1ded1d3d8
+S = dfb40e406bfa074f0bf832771b2b9f186e2211f0bca279644a0ca8559acf39da
+
+Msg = d5aa8ac9218ca661cd177756af6fbb5a40a3fecfd4eea6d5872fbb9a2884784aa9b5f0c023a6e0da5cf6364754ee6465b4ee2d0ddc745b02994c98427a213c849537da5a4477b3abfe02648be67f26e80b56a33150490d062aaac137aa47f11cfeddba855bab9e4e028532a563326d927f9e6e3292b1fb248ee90b6f429798db
+d = 724567d21ef682dfc6dc4d46853880cfa86fe6fea0efd51fac456f03c3d36ead
+Qx = 70b877b5e365fcf08140b1eca119baba662879f38e059d074a2cb60b03ea5d39
+Qy = 5f56f94d591df40b9f3b8763ac4b3dbe622c956d5bd0c55658b6f46fa3deb201
+k = 79d6c967ed23c763ece9ca4b026218004c84dc2d4ccc86cf05c5d0f791f6279b
+R = 2ba2ea2d316f8937f184ad3028e364574d20a202e4e7513d7af57ac2456804d1
+S = 64fe94968d18c5967c799e0349041b9e40e6c6c92ebb475e80dd82f51cf07320
+
+Msg = 790b06054afc9c3fc4dfe72df19dd5d68d108cfcfca6212804f6d534fd2fbe489bd8f64bf205ce04bcb50124a12ce5238fc3fe7dd76e6fa640206af52549f133d593a1bfd423ab737f3326fa79433cde293236f90d4238f0dd38ed69492ddbd9c3eae583b6325a95dec3166fe52b21658293d8c137830ef45297d67813b7a508
+d = 29c5d54d7d1f099d50f949bfce8d6073dae059c5a19cc70834722f18a7199edd
+Qx = 3088d4f45d274cc5f418c8ecc4cbcf96be87491f420250f8cbc01cdf2503ec47
+Qy = 634db48198129237ed068c88ff5809f6211921a6258f548f4b64dd125921b78b
+k = 0508ad7774908b5705895fda5c3b7a3032bf85dab7232bf981177019f3d76460
+R = acd9f3b63626c5f32103e90e1dd1695907b1904aa9b14f2132caef331321971b
+S = 15c04a8bd6c13ed5e9961814b2f406f064670153e4d5465dcef63c1d9dd52a87
+
+Msg = 6d549aa87afdb8bfa60d22a68e2783b27e8db46041e4df04be0c261c4734b608a96f198d1cdb8d082ae48579ec9defcf21fbc72803764a58c31e5323d5452b9fb57c8991d31749140da7ef067b18bf0d7dfbae6eefd0d8064f334bf7e9ec1e028daed4e86e17635ec2e409a3ed1238048a45882c5c57501b314e636b9bc81cbe
+d = 0d8095da1abba06b0d349c226511f642dabbf1043ad41baa4e14297afe8a3117
+Qx = 75a45758ced45ecf55f755cb56ca2601d794ebeaeb2e6107fe2fc443f580e23c
+Qy = 5303d47d5a75ec821d51a2ee7548448208c699eca0cd89810ffc1aa4faf81ead
+k = 5165c54def4026ab648f7768c4f1488bcb183f6db7ffe02c7022a529a116482a
+R = ebc85fc4176b446b3384ccc62fc2526b45665561a0e7e9404ac376c90e450b59
+S = 8b2c09428e62c5109d17ed0cf8f9fd7c370d018a2a73f701effc9b17d04852c6
+
+Msg = 1906e48b7f889ee3ff7ab0807a7aa88f53f4018808870bfed6372a77330c737647961324c2b4d46f6ee8b01190474951a701b048ae86579ff8e3fc889fecf926b17f98958ac7534e6e781ca2db2baa380dec766cfb2a3eca2a9d5818967d64dfab84f768d24ec122eebacaab0a4dc3a75f37331bb1c43dd8966cc09ec4945bbd
+d = 52fe57da3427b1a75cb816f61c4e8e0e0551b94c01382b1a80837940ed579e61
+Qx = 2177e20a2092a46667debdcc21e7e45d6da72f124adecbc5ada6a7bcc7b401d5
+Qy = 550e468f2626070a080afeeb98edd75a721eb773c8e62149f3e903cf9c4d7b61
+k = 0464fe9674b01ff5bd8be21af3399fad66f90ad30f4e8ee6e2eb9bcccfd5185c
+R = f8250f073f34034c1cde58f69a85e2f5a030703ebdd4dbfb98d3b3690db7d114
+S = a9e83e05f1d6e0fef782f186bedf43684c825ac480174d48b0e4d31505e27498
+
+Msg = 7b59fef13daf01afec35dea3276541be681c4916767f34d4e874464d20979863ee77ad0fd1635bcdf93e9f62ed69ae52ec90aab5bbf87f8951213747ccec9f38c775c1df1e9d7f735c2ce39b42edb3b0c5086247556cfea539995c5d9689765288ec600848ecf085c01ca738bbef11f5d12d4457db988b4add90be00781024ad
+d = 003d91611445919f59bfe3ca71fe0bfdeb0e39a7195e83ac03a37c7eceef0df2
+Qx = 7b9c592f61aae0555855d0b9ebb6fd00fb6746e8842e2523565c858630b9ba00
+Qy = d35b2e168b1875bbc563bea5e8d63c4e38957c774a65e762959a349eaf263ba0
+k = ef9df291ea27a4b45708f7608723c27d7d56b7df0599a54bc2c2fabbff373b40
+R = 66d057fd39958b0e4932bacd70a1769bbadcb62e4470937b45497a3d4500fabb
+S = 6c853b889e18b5a49ee54b54dd1aaedfdd642e30eba171c5cab677f0df9e7318
+
+Msg = 041a6767a935dc3d8985eb4e608b0cbfebe7f93789d4200bcfe595277ac2b0f402889b580b72def5da778a680fd380c955421f626d52dd9a83ea180187b850e1b72a4ec6dd63235e598fd15a9b19f8ce9aec1d23f0bd6ea4d92360d50f951152bc9a01354732ba0cf90aaed33c307c1de8fa3d14f9489151b8377b57c7215f0b
+d = 48f13d393899cd835c4193670ec62f28e4c4903e0bbe5817bf0996831a720bb7
+Qx = 82a1a96f4648393c5e42633ecdeb1d8245c78c5ea236b5bab460dedcc8924bc0
+Qy = e8cbf03c34b5154f876de19f3bb6fd43cd2eabf6e7c95467bcfa8c8fc42d76fd
+k = efed736e627899fea944007eea39a4a63c0c2e26491cd12adb546be3e5c68f7d
+R = cf7fc24bdaa09ac0cca8497e13298b961380668613c7493954048c06385a7044
+S = f38b1c8306cf82ab76ee3a772b14416b49993fe11f986e9b0f0593c52ec91525
+
+Msg = 7905a9036e022c78b2c9efd40b77b0a194fbc1d45462779b0b76ad30dc52c564e48a493d8249a061e62f26f453ba566538a4d43c64fb9fdbd1f36409316433c6f074e1b47b544a847de25fc67d81ac801ed9f7371a43da39001c90766f943e629d74d0436ba1240c3d7fab990d586a6d6ef1771786722df56448815f2feda48f
+d = 95c99cf9ec26480275f23de419e41bb779590f0eab5cf9095d37dd70cb75e870
+Qx = 42c292b0fbcc9f457ae361d940a9d45ad9427431a105a6e5cd90a345fe3507f7
+Qy = 313b08fd2fa351908b3178051ee782cc62b9954ad95d4119aa564900f8ade70c
+k = 4c08dd0f8b72ae9c674e1e448d4e2afe3a1ee69927fa23bbff3716f0b99553b7
+R = f2bc35eb1b8488b9e8d4a1dbb200e1abcb855458e1557dc1bf988278a174eb3b
+S = ed9a2ec043a1d578e8eba6f57217976310e8674385ad2da08d6146c629de1cd9
+
+Msg = cf25e4642d4f39d15afb7aec79469d82fc9aedb8f89964e79b749a852d931d37436502804e39555f5a3c75dd958fd5291ada647c1a5e38fe7b1048f16f2b711fdd5d39acc0812ca65bd50d7f8119f2fd195ab16633503a78ee9102c1f9c4c22568e0b54bd4fa3f5ff7b49160bf23e7e2231b1ebebbdaf0e4a7d4484158a87e07
+d = e15e835d0e2217bc7c6f05a498f20af1cd56f2f165c23d225eb3360aa2c5cbcf
+Qx = 89dd22052ec3ab4840206a62f2270c21e7836d1a9109a3407dd0974c7802b9ae
+Qy = e91609ba35c7008b080c77a9068d97a14ca77b97299e74945217672b2fd5faf0
+k = c9f621441c235fc47ec34eef4c08625df1ec74918e1f86075b753f2589f4c60b
+R = a70d1a2d555d599bfb8c9b1f0d43725341151d17a8d0845fa56f3563703528a7
+S = 4e05c45adf41783e394a5312f86e66871c4be4896948c85966879d5c66d54b37
+
+Msg = 7562c445b35883cc937be6349b4cefc3556a80255d70f09e28c3f393daac19442a7eecedcdfbe8f7628e30cd8939537ec56d5c9645d43340eb4e78fc5dd4322de8a07966b262770d7ff13a071ff3dce560718e60ed3086b7e0003a6abafe91af90af86733ce8689440bf73d2aa0acfe9776036e877599acbabfcb03bb3b50faa
+d = 808c08c0d77423a6feaaffc8f98a2948f17726e67c15eeae4e672edbe388f98c
+Qx = b0c0ad5e1f6001d8e9018ec611b2e3b91923e69fa6c98690ab644d650f640c42
+Qy = 610539c0b9ed21ac0a2f27527c1a61d9b47cbf033187b1a6ada006eb5b2662ed
+k = 1f6d4a905c761a53d54c362976717d0d7fc94d222bb5489e4830080a1a67535d
+R = 83404dcf8320baf206381800071e6a75160342d19743b4f176960d669dd03d07
+S = 3f75dcf102008b2989f81683ae45e9f1d4b67a6ef6fd5c8af44828af80e1cfb5
+
+Msg = 051c2db8e71e44653ea1cb0afc9e0abdf12658e9e761bfb767c20c7ab4adfcb18ed9b5c372a3ac11d8a43c55f7f99b33355437891686d42362abd71db8b6d84dd694d6982f0612178a937aa934b9ac3c0794c39027bdd767841c4370666c80dbc0f8132ca27474f553d266deefd7c9dbad6d734f9006bb557567701bb7e6a7c9
+d = f7c6315f0081acd8f09c7a2c3ec1b7ece20180b0a6365a27dcd8f71b729558f9
+Qx = 250f7112d381c1751860045d9bcaf20dbeb25a001431f96ac6f19109362ffebb
+Qy = 49fba9efe73546135a5a31ab3753e247034741ce839d3d94bd73936c4a17e4aa
+k = 68c299be2c0c6d52d208d5d1a9e0ffa2af19b4833271404e5876e0aa93987866
+R = 7b195e92d2ba95911cda7570607e112d02a1c847ddaa33924734b51f5d81adab
+S = 10d9f206755cef70ab5143ac43f3f8d38aea2644f31d52eaf3b472ee816e11e5
+
+Msg = 4dcb7b62ba31b866fce7c1feedf0be1f67bf611dbc2e2e86f004422f67b3bc1839c6958eb1dc3ead137c3d7f88aa97244577a775c8021b1642a8647bba82871e3c15d0749ed343ea6cad38f123835d8ef66b0719273105e924e8685b65fd5dc430efbc35b05a6097f17ebc5943cdcd9abcba752b7f8f37027409bd6e11cd158f
+d = f547735a9409386dbff719ce2dae03c50cb437d6b30cc7fa3ea20d9aec17e5a5
+Qx = 4ca87c5845fb04c2f76ae3273073b0523e356a445e4e95737260eba9e2d021db
+Qy = 0f86475d07f82655320fdf2cd8db23b21905b1b1f2f9c48e2df87e24119c4880
+k = 91bd7d97f7ed3253cedefc144771bb8acbbda6eb24f9d752bbe1dd018e1384c7
+R = 008c1755d3df81e64e25270dbaa9396641556df7ffc7ac9add6739c382705397
+S = 77df443c729b039aded5b516b1077fecdd9986402d2c4b01734ba91e055e87fc
+
+Msg = efe55737771070d5ac79236b04e3fbaf4f2e9bed187d1930680fcf1aba769674bf426310f21245006f528779347d28b8aeacd2b1d5e3456dcbf188b2be8c07f19219e4067c1e7c9714784285d8bac79a76b56f2e2676ea93994f11eb573af1d03fc8ed1118eafc7f07a82f3263c33eb85e497e18f435d4076a774f42d276c323
+d = 26a1aa4b927a516b661986895aff58f40b78cc5d0c767eda7eaa3dbb835b5628
+Qx = 28afa3b0f81a0e95ad302f487a9b679fcdef8d3f40236ec4d4dbf4bb0cbba8b2
+Qy = bb4ac1be8405cbae8a553fbc28e29e2e689fabe7def26d653a1dafc023f3cecf
+k = f98e1933c7fad4acbe94d95c1b013e1d6931fa8f67e6dbb677b564ef7c3e56ce
+R = 15a9a5412d6a03edd71b84c121ce9a94cdd166e40da9ce4d79f1afff6a395a53
+S = 86bbc2b6c63bad706ec0b093578e3f064736ec69c0dba59b9e3e7f73762a4dc3
+
+Msg = ea95859cc13cccb37198d919803be89c2ee10befdcaf5d5afa09dcc529d333ae1e4ffd3bd8ba8642203badd7a80a3f77eeee9402eed365d53f05c1a995c536f8236ba6b6ff8897393506660cc8ea82b2163aa6a1855251c87d935e23857fe35b889427b449de7274d7754bdeace960b4303c5dd5f745a5cfd580293d6548c832
+d = 6a5ca39aae2d45aa331f18a8598a3f2db32781f7c92efd4f64ee3bbe0c4c4e49
+Qx = c62cc4a39ace01006ad48cf49a3e71466955bbeeca5d318d672695df926b3aa4
+Qy = c85ccf517bf2ebd9ad6a9e99254def0d74d1d2fd611e328b4a3988d4f045fe6f
+k = dac00c462bc85bf39c31b5e01df33e2ec1569e6efcb334bf18f0951992ac6160
+R = 6e7ff8ec7a5c48e0877224a9fa8481283de45fcbee23b4c252b0c622442c26ad
+S = 3dfac320b9c873318117da6bd856000a392b815659e5aa2a6a1852ccb2501df3
+
+
+
+[P-384,SHA-224]
+
+Msg = 39f0b25d4c15b09a0692b22fbacbb5f8aee184cb75887e2ebe0cd3be5d3815d29f9b587e10b3168c939054a89df11068e5c3fac21af742bf4c3e9512f5569674e7ad8b39042bcd73e4b7ce3e64fbea1c434ed01ad4ad8b5b569f6a0b9a1144f94097925672e59ba97bc4d33be2fa21b46c3dadbfb3a1f89afa199d4b44189938
+d = 0af857beff08046f23b03c4299eda86490393bde88e4f74348886b200555276b93b37d4f6fdec17c0ea581a30c59c727
+Qx = 00ea9d109dbaa3900461a9236453952b1f1c2a5aa12f6d500ac774acdff84ab7cb71a0f91bcd55aaa57cb8b4fbb3087d
+Qy = 0fc0e3116c9e94be583b02b21b1eb168d8facf3955279360cbcd86e04ee50751054cfaebcf542538ac113d56ccc38b3e
+k = e2f0ce83c5bbef3a6eccd1744f893bb52952475d2531a2854a88ff0aa9b12c65961e2e517fb334ef40e0c0d7a31ed5f5
+R = c36e5f0d3de71411e6e519f63e0f56cff432330a04fefef2993fdb56343e49f2f7db5fcab7728acc1e33d4692553c02e
+S = 0d4064399d58cd771ab9420d438757f5936c3808e97081e457bc862a0c905295dca60ee94f4537591c6c7d217453909b
+
+Msg = 5a3c80e608ed3ac75a6e45f6e94d374271a6d42b67a481860d5d309cc8b37c79cb61f1716dc8aa84cb309ef9d68eb7fc6cf4b42333f316a5c30e74198c8b340926e340c5de47674a707293c4aa2a1a2274a602f01c26b156e895499c60b38ef53fc2032e7485c168d73700d6fa14232596a0e4997854a0b05d02e351b9d3de96
+d = 047dd5baab23f439ec23b58b7e6ff4cc37813cccb4ea73bb2308e6b82b3170edfe0e131eca50841bf1b686e651c57246
+Qx = de92ff09af2950854a70f2178d2ed50cc7042a7188301a1ea81d9629ad3c29795cb7f0d56630a401e4d6e5bed0068d1e
+Qy = 6135adbd8624130735e64e65ecbd43770dcc12b28e737b5ed033666f34c918eb5589508e4a13b9243374a118a628dd0b
+k = f3922351d14f1e5af84faab12fe57ded30f185afe5547aeb3061104740ecc42a8df0c27f3877b4d855642b78938c4e05
+R = 38e181870cb797c1f4e6598cfd032add1cb60447d33473038d06df73919f844eddd16f40f911075f8a4bacc0d924e684
+S = a58dd1ca18aa31277de66c30c3bb7a14b53705ce6c547ed2cb0e336f63c42809422efffcc722d1155f2254330a02b278
+
+Msg = e7d974c5dbd3bfb8a2fb92fdd782f997d04be79e9713944ce13c5eb6f75dfdec811b7ee4b3859114b07f263846ae13f795eec8f3cb5b7565baff68e0fdd5e09ba8b176d5a71cb03fbc5546e6937fba560acb4db24bd42de1851432b96e8ca4078313cb849bce29c9d805258601d67cd0259e255f3048682e8fdbdda3398c3e31
+d = 54ba9c740535574cebc41ca5dc950629674ee94730353ac521aafd1c342d3f8ac52046ed804264e1440d7fe409c45c83
+Qx = 3db95ded500b2506b627270bac75688dd7d44f47029adeff99397ab4b6329a38dbb278a0fc58fe4914e6ae31721a6875
+Qy = 049288341553a9ac3dc2d9e18e7a92c43dd3c25ca866f0cb4c68127bef6b0e4ba85713d27d45c7d0dc57e5782a6bf733
+k = 04324bd078807f6b18507a93ee60da02031717217ee5ce569750737be912be72da087ac00f50e13fdf7249a6ae33f73e
+R = b2752aa7abc1e5a29421c9c76620bcc3049ecc97e6bc39fcca126f505a9a1bfae3bde89fb751a1aa7b66fa8db3891ef0
+S = f1c69e6d818ca7ae3a477049b46420cebd910c0a9a477fd1a67a38d628d6edaac123aebfca67c53a5c80fe454dba7a9d
+
+Msg = a670fda4d1d56c70de1d8680328043b2b7029633caf0ee59ffe1421c914bb937133d5a0f9214846b2e0b350455a74c4ab434c56de65a17139bb8212bf1c76071a37536fa29348f871dbb26baa92eb93d97e923a6d2ffd9be25cbc33075e494e6db657bd8dc053fe4e17148d8cf6e2058164f2b5766750eb01bbe7b361cdb848c
+d = dabe87bbe95499bac23bc83c8b7307fe04be198f00059e2bf67c9611feaffb2c8f274f6aa50eb99c3074186d8067d659
+Qx = c2aa0a695125279705917e02a4f258cade4c3ff9140a071414babf87764f426f7f36ffda9d5f3394375d24864235476f
+Qy = 8f9808da0ce0227cf453f9e456f557db9752e23b45cce4baad5fee3844ddd7e1112bcec01ea9d67c7a76f3535bd0cb58
+k = 65a0305854033cbc6fe3ca139c40ca354d45801ecb59f4a923c251dc6b25d12d452d99b5d6711fdb5efac812aa464cc4
+R = c7fc32997d17ac79baf5789e4503f5f1a8863872bc350a91f12dd3ef8cf78c254e829217809e8e00b6b8d4d85be3f1fd
+S = 1422e1838a22496df93486bce1142961dbd8478ae844b8dda54e210afdae0d9e930d587c91bb600b0bde7237186d94e6
+
+Msg = 7843f918fe2588bcfe756e1f05b491d913523255aa006818be20b676c957f4edb8df863c6f5f8c15b3b80c7a2aa277b70d53f210bdfb856337980c406ea140e439dd321471407f374f69877b2d82367eed51e3c82c13948616dcb301d0c31f8f0352f2846abd9e72071f446a2f1bd3339a09ae41b84e150fd18f4ba5d3c6bfa0
+d = df43107a1deb24d02e31d479087bd669e2bc3e50f1f44b7db9484a7143cdca6a3391bddfea72dc940dbce8ec5efbd718
+Qx = 76bd4be5d520471162cb5c36f80038301b325f845d9642204a84d78b3e721098932827bf872bde0a9f86383953667d29
+Qy = 415116b8b878f896a5aa4dbbdc21076f27135d8bbcaaca02489ef639d742bd63f377da0c8e8ab36ff19b4a7cc5d4ceb4
+k = 798abad5a30d1805794540057388ee05e2422901c6335f985b9d4447b3ef75524751abfeab6409ad6bf77d4ae3014558
+R = 98744e5c6742fa5118a74a70db4957647a3cc12add4e876b45974a6a8707809f871daadbfc0b865e01624f706b65f10c
+S = 9e256e8da8eff5a0c83baaa1ef4f7be798eba9543bf97adb0fff8719f5406ea1207a0cf703d99aa8f02169724b492273
+
+Msg = caa83d5ab07febbd2e0fe2d63738b9b7b8752594bea7aaf50345b3d2f316653a8c9222f2b7877b64679e9573e81461a426029e45b8873a575094a1d572e0d32a9f0a9c6bcb9a2868543b7d8bbe4a69a09e7321f05f8366cced1b72df526f895b60aed2c39c249653c7839538770d4e5f47d3926ec0d168ab6a1af15bf1dca1f7
+d = ea7a563ba2a7f5ab69973dca1f1a0d1572f0c59817cd3b62ad356c2099e2cdca1c553323563f9dfbb333b126d84abc7f
+Qx = cf4717c5f5de668b785f06bdc9845df5a09e4edd83f4669756407cbb60807305c632bc49f818f4a84b194369aa07736f
+Qy = 7391e4982af8a2218f704f627d01f0508bfc8304992a2d598a420bf2eb519f33bd7caf79380793733b3dba0cc5e2b9d8
+k = 7b9606b3df7b2a340dbc68d9754de0734e1faeb5a0135578a97628d948702235c60b20c8002c8fcf906783e1b389e754
+R = 0d680010bed373287f9767955b5d2850e150b6713b49e453eb280148e45230c853d99ea2d2f8fcbd3ddcba19aeec0af1
+S = 64329763a930ab5452afdb0557fef16ff71810d6343dfc9c6ae18905c3d274db6554cdc69d6078a1ca03284474a94f30
+
+Msg = 594603458d6534974aeeafba919c4d0f4cb6843a3af41204bbb88aeb2fca2772d305163dba863da050aabedbaf89db521955d1715de95bbcef979ecdc0c976181ece00355385f8a8f8cce127c9eac15ce3e958a3ed686184674ec9a50eb63271606ee7fdcb1323da3c3db8e89cad1fb42139a32d08abcfbf0d4ccfca18c89a86
+d = 4cc70cb35b3ddeb0df53a6bd7bd05f8ff4392a2db7344f2d443761484b3a468a4ee3d1a8b27113d57283fd18b05f7829
+Qx = 40e1fe21df34bb85a642a0abe819ebd128f7e39b84d8dcc4a9a599b372fb9588da1484600ec28b1297bb685f9ae77831
+Qy = f3aa69ada57879fdcbe8df19cefabc308add7d03b17b1fac2f7783fece6a8dfe20bc36f518692677d96e3f730a67a671
+k = 8eda401d98f5688c34d8dbebcd3991c87c0442b0379154eaa2e5287dabe9a9e34cfc1305d11ff68781df25d5611b331d
+R = ff2d772786e159448bba26afd8c3281941a4cb0c56fec6f5cccb4c292c4ee0f7af9bd39bbe2d88148732585e104fdb30
+S = 07a1d890770daa949a17797dca7af3e8163da981ec330c03d63d1a8312c152be6a718163205ffa08da7dcc163ba261f4
+
+Msg = 733252d2bd35547838be22656cc7aa67eff0af0b13b428f77267a513c6824c3dbae533068b6817e82665f009560affcfe4b2ddb5b667a644fc1a42d24f24e0947e0dc50fb62c919bc1fe4e7ded5e28f2e6d80fcf66a081fb2763526f8def5a81a4ddd38be0b59ee839da1643eeeaee7b1927cec12cf3da67c02bc5465151e346
+d = 366d15e4cd7605c71560a418bd0f382fd7cd7ad3090ff1b2dfbed74336166a905e1b760cf0bccee7a0e66c5ebfb831f1
+Qx = a143f277ab36a10b645ff6c58241ea67ffdc8acf12d60973068390f06b4d8f4d773b10c1ebf6889b1cfa73ebb90f6ca1
+Qy = 7a17cad29bb507b309021f6f92cb5c10ba535f4a3e317fcc68cfd02d3ccd269f465169c73d30ff308f5350d881b08aec
+k = dbe545f920bc3d704c43d834bab21e40df12ec9e16a619a3e6b3f08760c26aae6e4fd91fad00f745194794b74bb1baee
+R = cdc39b12bba30da66fe9554713c05880ddc27afa4d2d151440f124c351fb9496dc95046516b0921083347d64369846ac
+S = 797d0344e49f9ba87a187c50f664e5015d449e346b1a7bd9427c5be559fc58173651880d5aadf053f81899d3368d6181
+
+Msg = 5a182bd174feb038dfae3346267156bf663167f713dea1ce936b0edb815cd9b8c8e4d411c786ba2494a81442617255db7158b142e720d86c9b56680fb9efd4298cdd69079a28153494c42a24251c7ad42ecf7e97eabc1b3997529b2a297cbad2474269b87a0b1e385f2d7f8b6eb8d1cd75eaf7e91d1acbecd45d7b2bfbbe3216
+d = e357d869857a52a06e1ece5593d16407022354780eb9a7cb8575cef327f877d22322c006b3c8c11e3d7d296a708bdb6d
+Qx = ce9a2185a68d6094aa5849a6efe78b349946f7380f0c79aa9664246cfcc71a879e90ad78a0474f58644c6a208168150e
+Qy = 8354fa47673cb3e07d446521345706c5515584b2602f921c3b9c44dded9e2c3f90ce47adb36d7e5f9f95a8c5ad8af397
+k = 1e77367ac4e10924854d135ad2f2507f39e2bafdbce33ff256bcbe9a7329b8d27185218bcc3550aafbe3390e84c77292
+R = df3182d49ad70959fb0c95bc7312750ce70fc87f1a328d39d9b29ac05d31305ce7209d6c24d13225d9567b489f7a187b
+S = d812b05abab0e96de13291e1f0da6479444ed5cd9d959b76f6cb43d394769035364f7c831a104dc7b5bd9b4a8e64df64
+
+Msg = aaa99fb1c71340d785a18f6f668e898c25cf7a0ac31d13c5b388b7233408493a5a109af6d07065376b96f4903df7aba2b2af671a18772bb0472490d1240cde28967680727dd4acd47e0308920a75da857a6eeedee5b6586d45dff3d8a680599665aa895c89dd7770b824b7dee477ac5e7602d409d3cc553090c970b50811dbab
+d = 745a18db47324a3710b993d115b2834339315e84e7006eafd889fb49bd3cc5a8b50c90526e65e6c53bddd2916d14bead
+Qx = f692578c6f77531210aef55c9e004ce3b66cf268c6900dde31a8bbb76e7562e3fb76242de34ca330d2501030aa119466
+Qy = 40965833b28de926c46de060aa25beaeda98f8415a6b1e3564aa77870cf4c89bd4fde92c8f5d9bf0eb41721586859d8e
+k = 11b9b36720abcac084efdb44c9f5b7d039e3250cb1e9c47850189ba3cfc1489d858b2a44df357772b61d919c7e729c0f
+R = 02b252c99820cf50e6ce060ab55bd4f682276e29b4ae4197417432e6a7bfb8cf0bac89dfe105456af805d822cee77696
+S = 8e248bbf7d7028d63177e565c9d1666ee5be4d1ffbfffc9c7814b0cd38f74b98f3f2cd59be42b9f132bfe5ee789cd96c
+
+Msg = 1fadfa8254d3a0b82d137cfdd82043d5dc1fef195d5297b09cc5cfb061f59c933451c0dc2a11b4037f34f88dacb803251f8880c4b72585c3c196e6fb23484ca43a191f8e41b9b9a37e2e6fcaab6738c3c62d1c98e1c620bb788b7b51a04f998a510efdba0d3418622fe8ce203b3fcd553b9b4206365a39031797ad11e49745ec
+d = 93f20963ea5011ff4f26481e359309e634195f6289134087bd2e83eee008c962780a679784ee7ac6acda03d663ed27e0
+Qx = 0edcde3533ea019e18f1a3cd97b7962e8823dda36c389f8f9287549f796d11376392b8a01c7a80f127a8f75795e04f54
+Qy = 63d7c458dccfc02f5148d755d59f9bbc8e3c3ea34908777928440747795955741296abcdd5386676419ed8049fedb489
+k = 3ad308faf04c42ee5ac69d36bc0aa9a96aacf55ea0f27dac4f52e088f023d206340a6324874ffad169ff80624de24c96
+R = 209b72f9aae72c4339813573c3a8408a9e0be641ca863d81d9d14c48d0bf4cd44a1a7985cff07b5d68f3f9478475645b
+S = f6292e599b22a76eda95393cf59f4745fa6c472effd1f781879ad9a4437a98080b0b07dadad0c249631c682d2836a977
+
+Msg = 9ecb6f5ed3ba666a8536a81ef65012c2cb8b433508798d84708abb06dfb75503886f78384fb8c7a4d2d49ef539d9b8a0b60938c7f07471dda91f258b0d99691b38a8403a2bb3f956bdfd09baba16d9b6877097a9b6213481b47a06e139d23ec7abad5668d21f912fdb70d31bb9adf9b3ce80e308252fa81a51674f88d02db72b
+d = f175e6ac42fd48ec9d652c10707c039c67c4cc61d8c45a373dcda6e4ca6c53e947e49c24e01b48e7cdf92edfe6d316a1
+Qx = a40c64f595491ce15790a5a87fbe64c1800247b42acd08fe5257700719f46afc8acce0e4ede0517a312092d5e3d089cd
+Qy = d565df9dc2f381cc0c5d84f382a43a98018524c0b4708a44b3e2817f9719f29fbf9c15803591ed9b4790c5adaba9f433
+k = 812dcaa6d4f9a43ccc553288065d13761581485aa903a500a690ccafbd330ba4818c977b98c4bb57f8a182a1afacfae9
+R = d000f18d3e4c162ff0d16f662e6703e7a6f5bff7a333ed266fa4f44c752415946c34945c342c20f739677186b1d80ab3
+S = ae7f1271c89e0aaa238710d039ea73a69110cc28fcf426f2fe6754b63a59e417fa84f903cf7dccb5468b43ff083bbfd5
+
+Msg = e55bfca78d98e68d1b63688db12485578f36c489766f4d0bfaa0088433ff12133aaca455805095f2e655940860958b3ead111d9070778ee3bbf3e47e43d9eba8b8d9b1fdf72f793fcde2bcaa334f3e35fa2cca531ea7cf27fe9ccba741e38ac26129b2d612bf54a34e0ae6c166c0fef07fcd2b9ac253d7e041a500f7be7b8369
+d = 46c4f0b228b28aaa0ec8cfdf1d0ed3408b7ae049312fb9eaf5f3892720e68684cc8ad29844a3dc9d110edf6916dfb8bb
+Qx = 13ddec844731b7e30c467451df08ca11d6c581cb64abd8a257671cffd26f5ccad4df7b9ee8924047a88a5d2d7567609c
+Qy = d74ca94f590fd1d13e190cc1e03c3da6c3faab15c7dda034af3deefee8aeec3628fa8b1978c54cfcd071baa319a46ec0
+k = 2a9dd520207c40a379cd4036adef9ee60fa8bc8c0d39b3ad91850ac93fd543f218b1688581f23481a090b0e4c73792ac
+R = 94e08cca20fe3866f643f53ec65faf3f2b4d80cd9bcc8ff8f88bb28da9eada324fc2d048908dd3d08a9e0ebb547731bc
+S = 8e6f82c4d3069b14f4c844b4ca133a9503493265c9f77a7d4775eda67de76798a23dd7ea48e0ac3c337dd62bf058319d
+
+Msg = 02c6b3c83bd34b288d96409162aa4ff114e9d134bf948046eb5ebcc0c7fe9dfceadda83ed69da2fac00c8840f6c702a3fc5e6959d70f7e8af923e99e4937232ae3b841ffefd2e62fab3671a7c94a0281b8ea5bc176add57c5c9b6893fe7f5d48ce7256b96510810c4e046168a3c5be9843b84d5268a50349b3444341aa5490dd
+d = 1d7b71ef01d0d33a8513a3aed3cabb83829589c8021087a740ca65b570777089be721a61172b874a22a1f81aef3f8bb6
+Qx = 8d2721370df8f097d5a69396249a315f6037dc7045b3da11eacae6d43036f779d5de7053d101768b42cc2b1283a3aaea
+Qy = a046039ae662141f9954d278183eaa2e03917fe58583e32d344074d59d60caa5b0949c53066525d5cca923e2f201502e
+k = d1b25ad25581cad17e96f1d302251681fee5b2efbb71c3c15ff035b2145d015d18e0e52dc3187ab5a560277b3a3929b0
+R = d836f52b14c7391744868daa2d5cf27eb9380b9b6176195573d5b04842e9f2fc3794d6cf877feafee63d11b05f6a6bee
+S = 8b89042fef2c04d4bd6c9d66a06a010514321d623a5f8d57ba5ac3686872eaabca9e0ba2d058ae7028e870acf03ca32d
+
+Msg = 94f8bfbb9dd6c9b6193e84c2023a27dea00fd48356909faec2161972439686c146184f80686bc09e1a698af7df9dea3d24d9e9fd6d7348a146339c839282cf8984345dc6a51096d74ad238c35233012ad729f262481ec7cd6488f13a6ebac3f3d23438c7ccb5a66e2bf820e92b71c730bb12fd64ea1770d1f892e5b1e14a9e5c
+d = cf53bdd4c91fe5aa4d82f116bd68153c907963fa3c9d478c9462bb03c79039493a8eaeb855773f2df37e4e551d509dcd
+Qx = 3a65b26c08102b44838f8c2327ea080daf1e4fc45bb279ce03af13a2f9575f0fff9e2e4423a58594ce95d1e710b590ce
+Qy = fe9dcbcb2ec6e8bd8ed3af3ff0aa619e900cc8bab3f50f6e5f79fac09164fb6a2077cc4f1fed3e9ec6899e91db329bf3
+k = df31908c9289d1fe25e055df199591b23e266433ab8657cc82cb3bca96b88720e229f8dfd42d8b78af7db69342430bca
+R = 6770eea9369d6718e60dd0b91aee845ff7ed7e0fcc91675f56d32e5227fd3a4612bbcb1556fe94a989b9e3bcc25bb20e
+S = c43072f706c98126d06a82b04251e3ecb0ba66c4bb6cd7c025919b9cc6019cdc635256d2a7fa017b806b1e88649d2c0d
+
+[P-384,SHA-256]
+
+Msg = 663b12ebf44b7ed3872b385477381f4b11adeb0aec9e0e2478776313d536376dc8fd5f3c715bb6ddf32c01ee1d6f8b731785732c0d8441df636d8145577e7b3138e43c32a61bc1242e0e73d62d624cdc924856076bdbbf1ec04ad4420732ef0c53d42479a08235fcfc4db4d869c4eb2828c73928cdc3e3758362d1b770809997
+d = c602bc74a34592c311a6569661e0832c84f7207274676cc42a89f058162630184b52f0d99b855a7783c987476d7f9e6b
+Qx = 0400193b21f07cd059826e9453d3e96dd145041c97d49ff6b7047f86bb0b0439e909274cb9c282bfab88674c0765bc75
+Qy = f70d89c52acbc70468d2c5ae75c76d7f69b76af62dcf95e99eba5dd11adf8f42ec9a425b0c5ec98e2f234a926b82a147
+k = c10b5c25c4683d0b7827d0d88697cdc0932496b5299b798c0dd1e7af6cc757ccb30fcd3d36ead4a804877e24f3a32443
+R = b11db00cdaf53286d4483f38cd02785948477ed7ebc2ad609054551da0ab0359978c61851788aa2ec3267946d440e878
+S = 16007873c5b0604ce68112a8fee973e8e2b6e3319c683a762ff5065a076512d7c98b27e74b7887671048ac027df8cbf2
+
+Msg = 784d7f4686c01bea32cb6cab8c089fb25c341080d9832e04feac6ea63a341079cbd562a75365c63cf7e63e7e1dddc9e99db75ccee59c5295340c2bba36f457690a8f05c62ab001e3d6b333780117d1456a9c8b27d6c2504db9c1428dad8ba797a4419914fcc636f0f14ede3fba49b023b12a77a2176b0b8ff55a895dcaf8dbce
+d = 0287f62a5aa8432ff5e95618ec8f9ccaa870dde99c30b51b7673378efe4ccac598f4bbebbfd8993f9abb747b6ad638b9
+Qx = b36418a3014074ec9bbcc6a4b2367a4fb464cca7ec0a324cb68670d5c5e03e7a7eb07da117c5ea50b665ab62bd02a491
+Qy = 4ea299c30e7d76e2c5905babada2d3bb4ee5eb35a5a23605cdb0d5133471a53eb9e6758e49105a4eaf29d2267ba84ef2
+k = 935eeab3edeb281fbd4eead0d9c0babd4b10ff18a31663ee9de3bfa9ae8f9d266441158ea31c889ded9b3c592da77fd7
+R = 738f9cb28f3b991335ef17b62559255faf75cad370a222464a492e27bb173c7f16b22100ada6b695875c7e4b1a28f158
+S = bc998c30e1491cd5d60dc7d1c38333165efe036b2a78db9b8f0e85ee68619cfba654e11ae5ca5ee5a87099c27cf22442
+
+Msg = 45e47fccc5bd6801f237cdbeac8f66ebc75f8b71a6da556d2e002352bd85bf269b6bc7c928d7bb1b0422601e4dd80b29d5906f8fcac212fe0eaaf52eda552303259cbcbe532e60abd3d38d786a45e39a2875bce675800a3eaeb9e42983d9fd9031180abd9adccc9ba30c6c198b4202c4dd70f241e969a3c412724b9b595bc28a
+d = d44d3108873977036c9b97e03f914cba2f5775b68c425d550995574081191da764acc50196f6d2508082a150af5cd41f
+Qx = c703835d723c85c643260379d8445b0c816fe9534351921e14a8e147fe140ec7b0c4d704f8dc66a232b2333b28f03dee
+Qy = c5d0bb054053fd86c26f147c4966757aa04b00513a02d427b8d06c16055c607955efdc518d338abfe7927c195dc28588
+k = c80f63e080650c8a21e4f63a62ec909adfb7d877f365d11ee1cb260baf112eb4730c161c1d99dba98fc0d5bbd00dc97d
+R = 81de2810cde421997013513951a3d537c51a013110d6dbb29251410bcb5ba001a9686b8490f1e581e282fd2ed0974b22
+S = 9cab0bbaffe91c7677ec3dd1f17060211a3cc0be574cbca064aa8c4b66ba6e64f3d80e83da895042ca32d311c388d950
+
+Msg = c33ff63b4e6891e00b2349b3f2907c417ca355560544a91e24a7a0ee260d6850aeded29fc0176b6039ca6187e8333391047cceaf14b1077df8f147dad84d36b2dac5666dc2f69dc9b58b88cc73956efdb3b47f91831d5875051c76b0c4e9fc087012a1f03eeee85d6745b46aa50bd9cb0110c2c94508765cec162ee1aa841d73
+d = d5b72cbb6ec68aca46b9c27ad992afd8ffa02cb3067b234fcfa6e272e3b31be760695ff7df988b57663057ab19dd65e3
+Qx = 135a6542612f1468d8a4d01ff1914e532b1dd64d3627db9d403dc325651d3f82b0f6f0fd1dbdeca2be967c4fb3793b5f
+Qy = cbbd40f6d3a38d0dfb64582ff4789d7b268241bc0c36de2884bccfaeeff3b7b2b46a30bb35719804e0d11124b4e7f480
+k = 9da6de7c87c101b68db64fea40d97f8ad974ceb88224c6796c690cbf61b8bd8eede8470b3caf6e6106b66cf3f0eebd55
+R = 17840911ecdf6ae0428b2634f442163c2c11b8dbf0cc7a5596fbe4d33e3e52f9d99e99ad169867b1f39e89c9180cedc2
+S = dd7ed67e480866d0474379ea4afff72870746f4feef2153be42f13bf472b1613d7faa5c0abb7f7464070f94d7cf3f234
+
+Msg = f562f2b9d84b0e96a52532c3b43c39c8018c738bd8dc3797a7de7353971b2729d522d6961b1f2e4df3f6a4bd3653e6d72b74fc0dba92ab939c4b542e994e5db6dd8ed4f56f651e699052e791237ae1f552f990ad156226ae8f7bf17fcbfa564f749604f97e9df0879d50985747d981422a23040fe52f5ec74caf1d4aaad8a710
+d = 218ee54a71ef2ccf012aca231fee28a2c665fc395ff5cd20bde9b8df598c282664abf9159c5b3923132983f945056d93
+Qx = 01989ff07a7a452d8084937448be946bfedac4049cea34b3db6f7c91d07d69e926cce0af3d6e88855a28120cf3dba8df
+Qy = eb064e029d7539d4b301aabafe8de8870162deffe6383bc63cc005add6ee1d5ced4a5761219c60cd58ad5b2a7c74aaa9
+k = c5d39b436d851d94691f5f4aa9ef447f7989d984f279ae8b091aef5449ac062bcc0567740f914624ad5b99fc32f9af0b
+R = 07d5b1b12877e8cb5e0aa5e71eeeb17bf0aa203064c7e98b3a1798a74dc9717252dc47c7f06aaf1d5fe15b868323bbb9
+S = 69428cf101a7af5d08161a9fd7af212e02e33b6062aebdce4c96bf3a0684b5394cb902ca7c2dec6e2f01f40c4576009d
+
+Msg = ace953ae851f571d71779aa120915f27450b236da23e9106f8d0756abdd25861937941228d225d5fb1aa1b1ebf759b1e326aeb3b6cd0cd87edd2ab9f6a7ad67b63d2c501d6a550edb2e7c9d216cc8af78dd33546af64d00abed4d0d2cfc5c9a7b5a055dbe8f7547902d185cf46937314832bc5c602419a82ab83dbd9d3bd5aff
+d = e6ab171f6937c000e144950801ad91023ae8e8476856c2592d9f7d5bb7180fd729211803d39a412ead6c0be761cfa5d1
+Qx = 38bc42b8c9d8866d09b214398d584b1b24a488dfacc3420d1e9506aa825b19fdf1ba74e7b8f547f47b571467fe8c4d1f
+Qy = 5179d62668d3f6a7ab5c8e3761a685e12008fb87d0529a97645f65cfb5364376c1b6682e0ffcddd0bcd995c41d013ad3
+k = 05e9718aea9669c9e434f73866da5f252dec6d24c47a1c4ee3233450b6ec626de9746ebe095b285558dfc89fc1b622fe
+R = df9bab9dd1f22ec6f27116f38831cb2089aa78aa8c073024a0faddd9a48e810a5e8e2cadd80fbf8dbd6088c71fe30b5b
+S = 1e0e8718567d12d18558c57f9e87a755c309e4ffb497335a3adfc8d7475ce8fd882d5dc33a8f5a16274b7ad74bb7862a
+
+Msg = 9635ab832240be95301bedb94c5aec169eedc198cbbdfedcf41e9b586143d829b4597a6b2a81902828332825fd84a785f187a3894e21bd99d22c4f94dcf34453fc052f15ec64d1447c932cb38fcdd30b7be851963409c11881438cbaad7e96f9efbde317f2235d66af804477a5dfe9f0c51448383830050ecf228889f83631e1
+d = 14acd516c7198798fd42ab0684d18df1cd1c99e304312752b3035bed6535a8975dff8acfc2ba1675787c817b5bff6960
+Qx = 29909d143cf7ee9c74b11d52f1a8f3ebd4a720c135612ca5618d3f432f03a95602ee75a2057e1d7aab51d0648ac0b334
+Qy = 404b6c5adffbadfa1b0380ae89fed96ec1ca16cc28661e623d0f1c8b130fbaa96dd7257eae2bf03c2d3dcbc3dbc82c58
+k = 7f623c103eaa9099a0462e55f80519c565adaeffcb57a29993f3a8a92e63a560be8f0fb9d23dc80bff1064bb41abad79
+R = 932ab291950c16b2b19a8036cd2e905714c6229cb190a73b3ea49c48dd8e76063a453c7c3267a57597d2973678216296
+S = d17d4c5ddbb9c27beebf526f113b416c8abfad53d11c4224813c7f351ba41a77dd4e77d6e4a65bef2c9f62cc37a469a5
+
+Msg = d98b9a7d4fe9d0fd95de5056af164a8b7882cd34ab5bde83a2abb32dc361eb56a479a3a6119db3b91dcad26a42d2206749567f0d97c34a981a91fc734921821a429f6a53401743a5c406ba9d560f956203abc9d1f32f1a13e7d7b290f75c95fdbf857ea597021461c06a3aacfa554ede3d69e4ff03bbbee5b7463ec77de2b3b2
+d = 2e780550984f3a00cb1e412429b33493c6eb6cd86d12f9d80588c247dcf567bd04296d2d4b24b889d9c54954b7f38f57
+Qx = 37dac42ef04663238443ef33e8addee2e78c40d50a1751913a7f5c37d1f23a26c7f86e16055c788b8ca9554f06b2f2ef
+Qy = bbed1549652904e3d00c39b01cc0460dbaf3185e6190c2705677a9701de1fe56dff4f4d8418ee15059ff8fc36800982d
+k = b788ca82811b0d4e4841765c71eafaa1e575378beedcd3860d8b92db3d070ac5aef7c425067860fbee6c50cf0c642bbb
+R = 7292b3851870daeb2555a8a2fb198ead78739fcfb75327e5c32a82c6b77d58983e5ad548ccb75dcf9411039c9576d9b9
+S = a378c61802d9f1dd062b6e18f16416a954018f77df4df95ad1b983570377d5cfce4cc7861759e802c52f81abc4f49aac
+
+Msg = 1b4c754ac1c28dc415a71eac816bde68de7e8db66409af835838c5bb2c605111108a3bf13606ed5d8ade5ed72e50503e0de664416393d178ea4eec834d8d6f15039847b410080fd5529b426e5aadd8451c20ebd92d787921f33e147bcbeb327b104d4aab1157fc1df33e4d768404b5ccb7110055c2508c600f429fd0c21b5784
+d = a24d0fe90808aecc5d90626d7e6da7c9be5dfd4e1233c7f0f71f1b7c1c6fd318fafe18559c94718f044cf02ed5107cb1
+Qx = ec8ae1fb9bb88589d27d6f27d790392853396f37bc0c381631d85800fc668eea0886bf1c6cff801147df19778d5b1604
+Qy = 1e1a8336c1e2506f8ee388b55cc648ae73b9295ea78467979d2affb364536fad28120f51ec62a67cbb6ce7784780389f
+k = 755d025509b73cf1ea8817beb772ad150b4c17a52378be187daffe3db0158921e5e552d1ca3c85df28519939f3cb794d
+R = 23ff2ffa62bbd427d49995d9c9950116e0d5a06ef076a4553448bc109e6482c5e87d4c833bc88de0bc722bc98cae2e61
+S = 9aea13d487c3ea6917e16374caafcf0321c12a80d28902dd8cd81909bb04b8c439e2491e504756742d0d0bfb15a9c34c
+
+Msg = 3cd8c053741dd9f974c6c5dbf8a1e5728e9b5eafb1cbcfc3452f5fbbda32a8c7564dee157e8d902c52514361da6d972934a56b3276e2a9379e328e24282e0db697c5bc29090fc489ec46b7b188325dd4e96494c250de0f4a89fe2ccf919eaefcfb50c288113e6df92714feb7f46e0822478c796d0f4ff3447a32997e892693ce
+d = 1c172e25732555afee7ded67a496f3f11babc0875898619f4519c29321e201e8ba1149f2c20b48e5efba235d58fea7c3
+Qx = 13e9e2c8bbcfe26e8f5f43c86268c5980ee693236a6b8777f3a7323718baa21005b482d08aafc6fa6e3667d91353544c
+Qy = 9ba181b3ee505be030f87ecd249b00670a791489b42af04976013483ff95b630c91c01e95757e906129f2f9b4ce719a8
+k = 08aec9a9e58bdc028805eb5dc86073d05fff1f5fb3fd17f510fc08f9272d84ba7aa66b6f77d84fe6360bd538192bf01a
+R = 2b4337c3dfbc886ffad7858ae2480cb62227e12205a70361c42f1a5ca9e658ee30fc3cf4030d85bd065edad83b99821f
+S = 2550cef8574bf17fb3d6b0c9d04ab266962bac3621bac233ff2e4989712d2a4a07171c0aebd3040cd6a32c3bd3efb8b5
+
+Msg = ed955dda6d9650124804d3deb6aeef900e520faf98b1ef6f14efcada7ca2433f09329b70897305e59c89024d76e466b28fe02cb2a9b12e2478c66470259d7c282137a19e5a04ffadea55245c0f34a681593fedc42931d8b3321b3d82e9cc102cd00540ad311ec7bd8c9d06db21bea4ca3dc74d98931ae0d40494aefc2345132c
+d = 5b96555dbd602e71d4d5d3aee19fd1ea084ee23d4f55c10937056762bc2015cbded2e898a487f5482ab7e1e971245907
+Qx = 6e14c17bb831b0112d7f3543c5fd17c78379a516c9e0539b03b8b4bfdead2820343fc84b0382807573ded6c4d97b7003
+Qy = 7f60021d2de77546db666721c9aec84c3e2ba8de0ba77443600dc77e6839bbf9316271adb22d4cb47d08f745ecb1dafd
+k = 7ad6f4ffd2b429ba10c6f112f800cacf1ad508cf8eba880893bb9659c1ddaaec57dcdc093a114500460d457bdde324f2
+R = faea950ca513806bc59028c638d6302ffc86978c3ff1f06db015dd7c4777050186cb8dd871f5e926e1416539c1939c2f
+S = 2c592240eabb8a1f9878e1b5c9d5d3ced7b3a7ae571f5a86494ed2ca567a36eb72e7bea8934bded29594bccf67ca84bd
+
+Msg = ce395b001da2a58e49691605d44af4206306f62f561bf2394060d2a5591a350277166bed043819035f1e60b5b3fb5ae113ddd0473f8ef6b2b050c472c2a264e1d8b3ca82a4f158c40f2d78d9ce5e5ea6de243f2e1f13f47f6c6f403b270912c81c636be35b396ca58468b3fb60aa83911d61441a0528d973bc31f965d4059080
+d = 8df9c3c710a25192f3dea970910bb3784e3509874cccf4334823eb9f7a8d05b067f2d812d61e878e24b093089a0b8245
+Qx = 92c9e32b20cbe6d4ed0727c6c942cf804a72031d6dfd69078b5e78ebce2d192268f1f5e2abce5aaf1f8d6a35f136837f
+Qy = d5167905fa7689e03b9fb1487c566f62b36f2bc1c4a2bfb6a836113b5c8d46f7c1ca51b628b14397fbc06ec9a07f4849
+k = 258dd05919735cd48627c9fe9fac5c252604aa7c2ae0460d7c1149cd96b7bd2ba195ad393bf392a2499f06aead5ba050
+R = 413793bcce52eda0f5b675a8d687cce86d5c9e1659b38a89e96246b5e05f8b0934d17dbba3b2ea44c838aa5fd87125d1
+S = ce7309fc2d6e3438818a1a29a997410b025b0403de20795b97c86c46034a6b02afeed279aeb06522d4de941bfdf50469
+
+Msg = ffefe316455ae4ffdb890bb804bf7d31424ea060ecacff419d0f7134ff76ad434063c0ec0f8bb7059584d3a03f3625bb9e9f66ace1a47ac4b8f3e76fc7c420c55edb1427d1fa15b387ad73d02b0595c4e74321be8822752230a0dcfb85d60bfa186da7623a8ec3eb1633f0a294b23ae87216b14ccee9ef56418dcfab9427371e
+d = 6002cb01ad2ce6e7101665d47729c863b6435c3875de57a93f99da834f73e3e6e2b3880e06de3e6bd1d51ea1807ab0d7
+Qx = e4216e1a20af8e8e3e74653ac016545001066e53e64af679ad1c85841bb475aed3e00ead052ae9955f48d675ff4ace56
+Qy = 8804c17641be21d4c6386902c9c5c888af25d97ca383703ea4a85cf93bbab360c0bbd2993374da499a303778650270b9
+k = 6b9507fd2844df0949f8b67b6fde986e50173713ac03df2edf65cb339859321cd3a2b9aab8356f95dec62460ab19c822
+R = 018891f6381ed358b422f79a299cf0789cee783ba388af4d82cbbe17f3709751b7fd9400e9702820c28b9afc62fdf489
+S = aef73bd590802b2fd2a65c4f7fec89f9b24ecc199a69254785925f334cd1977c5e1f858bd9830d7d7d243ea707b1af0b
+
+Msg = 304bccb718b3a9e12669913490cc5bcc1979287b56c628fad706c354241e88d10e81445a2853e3fc32ece094ba1abc3fdcab61da27f9a0fca739371049fed462ee6b08fa31cde12720f8144a6f00ce9b1a7a6eadd231f126717074b4efb5c72ce673ca5859000a436f67a338d698759f12c461247c45a361fb6cb661fdbe6714
+d = d8559c3543afc6f7b3dc037a687bad2630283757ba7862fd23ed14e2151a4cf5fed3d249268f780e0b96b6b46274a2d5
+Qx = 5f94223918f2ec9f0a08342cb99e724881c92453957c59672860f69daac01b660331a0f5845e50f1f27766b219c89e7e
+Qy = d76d83396130d10d1168d76c7fc83742ffffbe66d9f4da4ca3f95f5ad6dac8cc7bb65d16d317d37aa99fdbf30ec7439c
+k = 4ad5a92b5b8e170b71c8a7ed419dc624c7680004562b8d16a37b6e639f581ce81d5f0d98cce44d54c4e7136229148340
+R = f7baa6a5488ab462ea59aa31a36402b15880c68110b6069f51ede0c3b52a7b1e5bf926fdbe95768931b7d5f87058835c
+S = 28b1c4ef448a432f7c91b98b0c6471691e888211b6af907369a8930859b8cdb2e94f466a44f4e52f46df9b0d65e35de6
+
+Msg = 64f9f05c2805acf59c047b5f5d2e20c39277b6d6380f70f87b72327a76170b872bfe4b25c451602acfb6a631bb885e2655aee8abe44f69c90fb21ffde03cef2a452c468c6369867dfd8aa26ac24e16aa53b292375a8d8fbf988e302bf00088e4c061aa12c421d8fe3cbd7273b0e8993701df1c59431f436a08b8e15bd123d133
+d = b9208cbfd186ddfa3efd5b71342ae1efb01a13ebc4c2a992a2cbee7254b7846a4252ece1104b89d13d835911f8511224
+Qx = 166e6d96cb60d916fd19888a2dd945a3306ff0d7b0a5e30729f47d3dac3de2be3fd5cd7437e9a80d6c48cf960d2d36f8
+Qy = e6b2b70f131092ae210f29cc6bad701318bddb31bddf921695855c6208941100d0cee5d10799f8b835afe3ea510e8229
+k = da706ab5f61531f2378b3c0a2b342108cd119eadaa88b859df64923bccfb0ec2393fd312826f65c15a6587d1d460015b
+R = d9124c42858080c62400e4d4d8136304e03d910cbe9b9b3487f4d27c7e0540a314d34bef8c850045c8746ca631c11c42
+S = bbf6424a3b70166fa799f49e918439d515327039258ef9bd88435a59c9c19659f8ec3c8660720b0c08354ff60e0f5a76
+
+[P-384,SHA-384]
+
+Msg = 6b45d88037392e1371d9fd1cd174e9c1838d11c3d6133dc17e65fa0c485dcca9f52d41b60161246039e42ec784d49400bffdb51459f5de654091301a09378f93464d52118b48d44b30d781eb1dbed09da11fb4c818dbd442d161aba4b9edc79f05e4b7e401651395b53bd8b5bd3f2aaa6a00877fa9b45cadb8e648550b4c6cbe
+d = 201b432d8df14324182d6261db3e4b3f46a8284482d52e370da41e6cbdf45ec2952f5db7ccbce3bc29449f4fb080ac97
+Qx = c2b47944fb5de342d03285880177ca5f7d0f2fcad7678cce4229d6e1932fcac11bfc3c3e97d942a3c56bf34123013dbf
+Qy = 37257906a8223866eda0743c519616a76a758ae58aee81c5fd35fbf3a855b7754a36d4a0672df95d6c44a81cf7620c2d
+k = dcedabf85978e090f733c6e16646fa34df9ded6e5ce28c6676a00f58a25283db8885e16ce5bf97f917c81e1f25c9c771
+R = 50835a9251bad008106177ef004b091a1e4235cd0da84fff54542b0ed755c1d6f251609d14ecf18f9e1ddfe69b946e32
+S = 0475f3d30c6463b646e8d3bf2455830314611cbde404be518b14464fdb195fdcc92eb222e61f426a4a592c00a6a89721
+
+Msg = d768f41e6e8ec2125d6cf5786d1ba96668ac6566c5cdbbe407f7f2051f3ad6b1acdbfe13edf0d0a86fa110f405406b69085219b5a234ebdb93153241f785d45811b3540d1c37424cc7194424787a51b79679266484c787fb1ded6d1a26b9567d5ea68f04be416caf3be9bd2cafa208fe2a9e234d3ae557c65d3fe6da4cb48da4
+d = 23d9f4ea6d87b7d6163d64256e3449255db14786401a51daa7847161bf56d494325ad2ac8ba928394e01061d882c3528
+Qx = 5d42d6301c54a438f65970bae2a098cbc567e98840006e356221966c86d82e8eca515bca850eaa3cd41f175f03a0cbfd
+Qy = 4aef5a0ceece95d382bd70ab5ce1cb77408bae42b51a08816d5e5e1d3da8c18fcc95564a752730b0aabea983ccea4e2e
+k = 67ba379366049008593eac124f59ab017358892ee0c063d38f3758bb849fd25d867c3561563cac1532a323b228dc0890
+R = fb318f4cb1276282bb43f733a7fb7c567ce94f4d02924fc758635ab2d1107108bf159b85db080cdc3b30fbb5400016f3
+S = 588e3d7af5da03eae255ecb1813100d95edc243476b724b22db8e85377660d7645ddc1c2c2ee4eaea8b683dbe22f86ca
+
+Msg = 6af6652e92a17b7898e40b6776fabaf0d74cf88d8f0ebfa6088309cbe09fac472eeac2aa8ea96b8c12e993d14c93f8ef4e8b547afe7ae5e4f3973170b35deb3239898918c70c1056332c3f894cd643d2d9b93c2561aac069577bbab45803250a31cd62226cab94d8cba7261dce9fe88c210c212b54329d76a273522c8ba91ddf
+d = b5f670e98d8befc46f6f51fb2997069550c2a52ebfb4e5e25dd905352d9ef89eed5c2ecd16521853aadb1b52b8c42ae6
+Qx = 44ffb2a3a95e12d87c72b5ea0a8a7cb89f56b3bd46342b2303608d7216301c21b5d2921d80b6628dc512ccb84e2fc278
+Qy = e4c1002f1828abaec768cadcb7cf42fbf93b1709ccae6df5b134c41fae2b9a188bfbe1eccff0bd348517d7227f2071a6
+k = 229e67638f712f57bea4c2b02279d5ccad1e7c9e201c77f6f01aeb81ea90e62b44b2d2107fd66d35e56608fff65e28e4
+R = b11db592e4ebc75b6472b879b1d8ce57452c615aef20f67a280f8bca9b11a30ad4ac9d69541258c7dd5d0b4ab8dd7d49
+S = 4eb51db8004e46d438359abf060a9444616cb46b4f99c9a05b53ba6df02e914c9c0b6cc3a9791d804d2e4c0984dab1cc
+
+Msg = b96d74b2265dd895d94e25092fb9262dc4f2f7a328a3c0c3da134b2d0a4e2058ca994e3445c5ff4f812738e1b0c0f7a126486942a12e674a21f22d0886d68df2375f41685d694d487a718024933a7c4306f33f1a4267d469c530b0fed4e7dea520a19dd68bf0203cc87cad652260ed43b7b23f6ed140d3085875190191a0381a
+d = de5975d8932533f092e76295ed6b23f10fc5fba48bfb82c6cc714826baf0126813247f8bd51d5738503654ab22459976
+Qx = f1fabafc01fec7e96d982528d9ef3a2a18b7fe8ae0fa0673977341c7ae4ae8d8d3d67420343d013a984f5f61da29ae38
+Qy = 1a31cf902c46343d01b2ebb614bc789c313b5f91f9302ad9418e9c797563e2fa3d44500f47b4e26ad8fdec1a816d1dcf
+k = fc5940e661542436f9265c34bce407eff6364bd471aa79b90c906d923e15c9ed96eea4e86f3238ea86161d13b7d9359d
+R = c2fbdd6a56789024082173725d797ef9fd6accb6ae664b7260f9e83cb8ab2490428c8b9c52e153612295432fec4d59cd
+S = 8056c5bb57f41f73082888b234fcda320a33250b5da012ba1fdb4924355ae679012d81d2c08fc0f8634c708a4833232f
+
+Msg = 7cec7480a037ff40c232c1d2d6e8cd4c080bbeecdaf3886fccc9f129bb6d202c316eca76c8ad4e76079afe622f833a16f4907e817260c1fa68b10c7a151a37eb8c036b057ed4652c353db4b4a34b37c9a2b300fb5f5fcfb8aa8adae13db359160f70a9241546140e550af0073468683377e6771b6508327408c245d78911c2cc
+d = 11e0d470dc31fab0f5722f87b74a6c8d7414115e58ceb38bfcdced367beac3adbf1fe9ba5a04f72e978b1eb54597eabc
+Qx = 1950166989164cbfd97968c7e8adb6fbca1873ebef811ea259eb48b7d584627f0e6d6c64defe23cbc95236505a252aa1
+Qy = 41ef424b5cb076d4e32accd9250ea75fcf4ffd81814040c050d58c0a29b06be11edf67c911b403e418b7277417e52906
+k = e56904028226eb04f8d071e3f9cefec91075a81ca0fa87b44cae148fe1ce9827b5d1910db2336d0eb9813ddba3e4d7b5
+R = c38ef30f55624e8935680c29f8c24824877cf48ffc0ef015e62de1068893353030d1193bf9d34237d7ce6ba92c98b0fe
+S = 651b8c3d5c9d5b936d300802a06d82ad54f7b1ba4327b2f031c0c5b0cb215ad4354edc7f932d934e877dfa1cf51b13fe
+
+Msg = 00ce978603229710345c9ad7c1c2dba3596b196528eea25bd822d43ca8f76a024e29217703dd0652c8a615284fc3edcc1c5ad1c8d5a8521c8e104c016a24e50c2e25066dcb56596f913b872767e3627aa3e55ec812e9fdac7c2f1beade83aef093e24c9c953982adf431a776880ae4583be158e11cdab1cbca3ad3a66900213d
+d = 5c6bbf9fbcbb7b97c9535f57b431ed1ccae1945b7e8a4f1b032016b07810bd24a9e20055c0e9306650df59ef7e2cd8c2
+Qx = 2e01c5b59e619e00b79060a1e8ef695472e23bf9a511fc3d5ed77a334a242557098e40972713732c5291c97adf9cf2cf
+Qy = 563e3fe4ad807e803b9e961b08da4dde4cea8925649da0d93221ce4cdceabc6a1db7612180a8c6bef3579c65539b97e9
+k = 03d23f1277b949cb6380211ad9d338e6f76c3eedac95989b91d0243cfb734a54b19bca45a5d13d6a4b9f815d919eea77
+R = abab65308f0b79c4f3a9ff28dd490acb0c320434094cef93e75adfe17e5820dc1f77544cfaaacdc8cf9ac8b38e174bef
+S = 11b783d879a6de054b316af7d56e526c3dce96c85289122e3ad927cfa77bfc50b4a96c97f85b1b8221be2df083ff58fb
+
+Msg = 54a255c18692c6162a46add176a0ae8361dcb8948f092d8d7bac83e160431794d3b9812849bf1994bcdcfba56e8540c8a9ee5b93414548f2a653191b6bb28bda8dc70d45cc1b92a489f58a2d54f85766cb3c90de7dd88e690d8ebc9a79987eee1989df35af5e35522f83d85c48dda89863171c8b0bf4853ae28c2ac45c764416
+d = ffc7dedeff8343721f72046bc3c126626c177b0e48e247f44fd61f8469d4d5f0a74147fabaa334495cc1f986ebc5f0b1
+Qx = 51c78c979452edd53b563f63eb3e854a5b23e87f1b2103942b65f77d024471f75c8ce1cc0dfef83292b368112aa5126e
+Qy = 313e6aaf09caa3ba30f13072b2134878f14a4a01ee86326cccbff3d079b4df097dc57985e8c8c834a10cb9d766169366
+k = c3de91dbe4f777698773da70dd610ef1a7efe4dc00d734399c7dd100728006a502822a5a7ff9129ffd8adf6c1fc1211a
+R = f4f477855819ad8b1763f53691b76afbc4a31a638b1e08c293f9bcd55decf797f9913ca128d4b45b2e2ea3e82c6cf565
+S = 7c26be29569ef95480a6d0c1af49dc10a51a0a8931345e48c0c39498bfb94d62962980b56143a7b41a2fddc8794c1b7f
+
+Msg = 692a78f90d4f9d5aee5da536314a78d68c1feabbfe5d1ccea7f6059a66c4b310f8051c411c409ccf6e19a0cbd8b8e100c48317fe8c6d4f8a638b9551ce7ee178020f04f7da3001a0e6855225fb3c9b375e4ed964588a1a41a095f3f476c42d52ffd23ce1702c93b56d4425d3befcf75d0951b6fd5c05b05455bdaf205fe70ca2
+d = adca364ef144a21df64b163615e8349cf74ee9dbf728104215c532073a7f74e2f67385779f7f74ab344cc3c7da061cf6
+Qx = ef948daae68242330a7358ef73f23b56c07e37126266db3fa6eea233a04a9b3e4915233dd6754427cd4b71b75854077d
+Qy = 009453ef1828eaff9e17c856d4fc1895ab60051312c3e1db1e3766566438b2990cbf9945c2545619e3e0145bc6a79004
+k = a2da3fae2e6da3cf11b49861afb34fba357fea89f54b35ce5ed7434ae09103fe53e2be75b93fc579fedf919f6d5e407e
+R = dda994b9c428b57e9f8bbaebba0d682e3aac6ed828e3a1e99a7fc4c804bff8df151137f539c7389d80e23d9f3ee497bf
+S = a0d6b10ceffd0e1b29cf784476f9173ba6ecd2cfc7929725f2d6e24e0db5a4721683640eaa2bbe151fb57560f9ce594b
+
+Msg = 3b309bb912ab2a51681451ed18ad79e95d968abc35423a67036a02af92f575a0c89f1b668afe22c7037ad1199e757a8f06b281c33e9a40bab69c9874e0bb680b905d909b9dc24a9fe89bb3d7f7d47082b25093c59754f8c19d1f81f30334a8cdd50a3cb72f96d4b3c305e60a439a7e93aeb640dd3c8de37d63c60fb469c2d3ed
+d = 39bea008ec8a217866dcbdb1b93da34d1d3e851d011df9ef44b7828b3453a54aa70f1df9932170804eacd207e4f7e91d
+Qx = 5709ec4305a9c3271c304face6c148142490b827a73a4c17affcfd01fffd7eaa65d2fdedfa2419fc64ed910823513faf
+Qy = b083cda1cf3be6371b6c06e729ea6299213428db57119347247ec1fcd44204386cc0bca3f452d9d864b39efbfc89d6b2
+k = 3c90cc7b6984056f570542a51cbe497ce4c11aeae8fc35e8fd6a0d9adeb650e8644f9d1d5e4341b5adc81e27f284c08f
+R = d13646895afb1bfd1953551bb922809c95ad65d6abe94eb3719c899aa1f6dba6b01222c7f283900fe98628b7597b6ea6
+S = 4a9a38afda04c0a6b0058943b679bd02205b14d0f3d49b8f31aac289129780cdb1c555def8c3f9106b478729e0c7efaa
+
+Msg = f072b72b8783289463da118613c43824d11441dba364c289de03ff5fab3a6f60e85957d8ff211f1cb62fa90216fb727106f692e5ae0844b11b710e5a12c69df3ed895b94e8769ecd15ff433762d6e8e94d8e6a72645b213b0231344e2c968056766c5dd6b5a5df41971858b85e99afbf859400f839b42cd129068efabeea4a26
+d = e849cf948b241362e3e20c458b52df044f2a72deb0f41c1bb0673e7c04cdd70811215059032b5ca3cc69c345dcce4cf7
+Qx = 06c037a0cbf43fdf335dff33de06d34348405353f9fdf2ce1361efba30fb204aea9dbd2e30da0a10fd2d876188371be6
+Qy = 360d38f3940e34679204b98fbf70b8a4d97f25443e46d0807ab634ed5891ad864dd7703557aa933cd380e26eea662a43
+k = 32386b2593c85e877b70e5e5495936f65dc49553caef1aa6cc14d9cd370c442a0ccfab4c0da9ec311b67913b1b575a9d
+R = 5886078d3495767e330c7507b7ca0fa07a50e59912a416d89f0ab1aa4e88153d6eaf00882d1b4aa64153153352d853b5
+S = 2cc10023bf1bf8ccfd14b06b82cc2114449a352389c8ff9f6f78cdc4e32bde69f3869da0e17f691b329682ae7a36e1aa
+
+Msg = cf4945350be8133b575c4ad6c9585e0b83ff1ed17989b6cd6c71b41b5264e828b4e115995b1ae77528e7e9002ac1b5669064442645929f9d7dd70927cb93f95edeb73e8624f4bc897ec4c2c7581cb626916f29b2d6e6c2fba8c59a71e30754b459d81b912a12798182bcff4019c7bdfe929cc769bcc2414befe7d2906add4271
+d = d89607475d509ef23dc9f476eae4280c986de741b63560670fa2bd605f5049f1972792c0413a5b3b4b34e7a38b70b7ca
+Qx = 49a1c631f31cf5c45b2676b1f130cbf9be683d0a50dffae0d147c1e9913ab1090c6529a84f47ddc7cf025921b771355a
+Qy = 1e207eece62f2bcc6bdabc1113158145170be97469a2904eaaa93aad85b86a19719207f3e423051f5b9cbbe2754eefcb
+k = 78613c570c8d33b7dd1bd1561d87e36282e8cf4843e7c344a2b2bb6a0da94756d670eeaffe434f7ae7c780f7cf05ca08
+R = 66f92b39aa3f4aeb9e2dc03ac3855406fa3ebbab0a6c88a78d7a03482f0c9868d7b78bc081ede0947c7f37bf193074ba
+S = e5c64ed98d7f3701193f25dd237d59c91c0da6e26215e0889d82e6d3e416693f8d58843cf30ab10ab8d0edd9170b53ad
+
+Msg = d9b5cf0b50416573ff3c63133275a18394dd4326be2041e8d97e6e4e3855a4a177e9d26dfd223fe8aa74564edb49bd72de19916fb6f001f44530d5c18e2c332bce1b7415df5927ece5f3824f34d174b963136b53aef1fb78fb0c06a201a40b2db38e4d8216fc1e392a798c8ab4b3a314496b7f1087804ebfa89bf96e9cdb80c0
+d = 083e7152734adf342520ae377087a223688de2899b10cfcb34a0b36bca500a4dfa530e2343e6a39da7ae1eb0862b4a0d
+Qx = 70a0f16b6c61172659b027ed19b18fd8f57bd28dc0501f207bd6b0bb065b5671cf3dd1ed13d388dcf6ccc766597aa604
+Qy = 4f845bf01c3c3f6126a7368c3454f51425801ee0b72e63fb6799b4420bfdebe3e37c7246db627cc82c09654979c700bb
+k = 28096ababe29a075fbdf894709a20d0fdedb01ed3eeacb642a33a0da6aed726e13caf6cf206792ec359f0c9f9b567552
+R = ee2923f9b9999ea05b5e57f505bed5c6ba0420def42c6fa90eef7a6ef770786525546de27cdeb2f8586f8f29fb4ee67c
+S = 50ef923fb217c4cf65a48b94412fda430fac685f0da7bd574557c6c50f5b22e0c8354d99f2c2f2c2691f252f93c7d84a
+
+Msg = 9e4042d8438a405475b7dab1cd783eb6ce1d1bffa46ac9dfda622b23ac31057b922eced8e2ed7b3241efeafd7c9ab372bf16230f7134647f2956fb793989d3c885a5ae064e85ed971b64f5f561e7ddb79d49aa6ebe727c671c67879b794554c04de0e05d68264855745ef3c9567bd646d5c5f8728b797c181b6b6a876e167663
+d = 63578d416215aff2cc78f9b926d4c7740a77c142944e104aa7422b19a616898262d46a8a942d5e8d5db135ee8b09a368
+Qx = cadbacef4406099316db2ce3206adc636c2bb0a835847ed7941efb02862472f3150338f13f4860d47f39b7e098f0a390
+Qy = 752ad0f22c9c264336cde11bbc95d1816ed4d1b1500db6b8dce259a42832e613c31178c2c7995206a62e201ba108f570
+k = 7b69c5d5b4d05c9950dc94c27d58403b4c52c004b80a80418ad3a89aabc5d34f21926729e76afd280cc8ee88c9805a2a
+R = db054addb6161ee49c6ce2e4d646d7670754747b6737ca8516e9d1e87859937c3ef9b1d2663e10d7e4bd00ec85b7a97a
+S = fcc504e0f00ef29587e4bc22faada4db30e2cb1ac552680a65785ae87beb666c792513f2be7a3180fc544296841a0e27
+
+Msg = 0b14a7484a40b68a3ce1273b8a48b8fdb65ba900d98541c4bbd07b97e31bcc4c85545a03e9deab3c563f47a036ff60d0361684ba241b5aa68bb46f440da22181ee328a011de98eff34ba235ec10612b07bdfa6b3dc4ccc5e82d3a8d057e1862fef3def5a1804696f84699fda2ec4175a54a4d08bcb4f0406fdac4eddadf5e29b
+d = ed4df19971658b74868800b3b81bc877807743b25c65740f1d6377542afe2c6427612c840ada31a8eb794718f37c7283
+Qx = 33093a0568757e8b58df5b72ea5fe5bf26e6f7aeb541b4c6a8c189c93721749bcaceccf2982a2f0702586a9f812fc66f
+Qy = ebe320d09e1f0662189d50b85a20403b821ac0d000afdbf66a0a33f304726c69e354d81c50b94ba3a5250efc31319cd1
+k = d9b4cd1bdfa83e608289634dbfcee643f07315baf743fc91922880b55a2feda3b38ddf6040d3ba10985cd1285fc690d5
+R = 009c74063e206a4259b53decff5445683a03f44fa67252b76bd3581081c714f882f882df915e97dbeab061fa8b3cc4e7
+S = d40e09d3468b46699948007e8f59845766dbf694b9c62066890dd055c0cb9a0caf0aa611fb9f466ad0bbb00dbe29d7eb
+
+Msg = 0e646c6c3cc0f9fdedef934b7195fe3837836a9f6f263968af95ef84cd035750f3cdb649de745c874a6ef66b3dd83b66068b4335bc0a97184182e3965c722b3b1aee488c3620adb835a8140e199f4fc83a88b02881816b366a09316e25685217f9221157fc05b2d8d2bc855372183da7af3f0a14148a09def37a332f8eb40dc9
+d = e9c7e9a79618d6ff3274da1abd0ff3ed0ec1ae3b54c3a4fd8d68d98fb04326b7633fc637e0b195228d0edba6bb1468fb
+Qx = a39ac353ca787982c577aff1e8601ce192aa90fd0de4c0ed627f66a8b6f02ae51315543f72ffc1c48a7269b25e7c289a
+Qy = 9064a507b66b340b6e0e0d5ffaa67dd20e6dafc0ea6a6faee1635177af256f9108a22e9edf736ab4ae8e96dc207b1fa9
+k = b094cb3a5c1440cfab9dc56d0ec2eff00f2110dea203654c70757254aa5912a7e73972e607459b1f4861e0b08a5cc763
+R = ee82c0f90501136eb0dc0e459ad17bf3be1b1c8b8d05c60068a9306a346326ff7344776a95f1f7e2e2cf9477130e735c
+S = af10b90f203af23b7500e070536e64629ba19245d6ef39aab57fcdb1b73c4c6bf7070c6263544633d3d358c12a178138
+
+[P-384,SHA-512]
+
+Msg = 67d9eb88f289454d61def4764d1573db49b875cfb11e139d7eacc4b7a79d3db3bf7208191b2b2078cbbcc974ec0da1ed5e0c10ec37f6181bf81c0f32972a125df64e3b3e1d838ec7da8dfe0b7fcc911e43159a79c73df5fa252b98790be511d8a732fcbf011aacc7d45d8027d50a347703d613ceda09f650c6104c9459537c8f
+d = 217afba406d8ab32ee07b0f27eef789fc201d121ffab76c8fbe3c2d352c594909abe591c6f86233992362c9d631baf7c
+Qx = fb937e4a303617b71b6c1a25f2ac786087328a3e26bdef55e52d46ab5e69e5411bf9fc55f5df9994d2bf82e8f39a153e
+Qy = a97d9075e92fa5bfe67e6ec18e21cc4d11fde59a68aef72c0e46a28f31a9d60385f41f39da468f4e6c3d3fbac9046765
+k = 90338a7f6ffce541366ca2987c3b3ca527992d1efcf1dd2723fbd241a24cff19990f2af5fd6419ed2104b4a59b5ae631
+R = c269d9c4619aafdf5f4b3100211dddb14693abe25551e04f9499c91152a296d7449c08b36f87d1e16e8e15fee4a7f5c8
+S = 77ffed5c61665152d52161dc13ac3fbae5786928a3d736f42d34a9e4d6d4a70a02d5af90fa37a23a318902ae2656c071
+
+Msg = 45db86829c363c80160659e3c5c7d7971abb1f6f0d495709bba908d7aa99c9df64b3408a51bd69aba8870e2aaff488ef138f3123cf94391d081f357e21906a4e2f311defe527c55e0231579957c51def507f835cceb466eb2593a509dcbee2f09e0dde6693b2bfe17697c9e86dd672f5797339cbe9ea8a7c6309b061eca7aef5
+d = 0a3f45a28a355381a919372f60320d6610cfb69c3e318eb1607db3cadfc42b728b77a6a9e9e333de9183c58933daf60f
+Qx = 832cbb7061a719a316e73dbad348fa67cd17c33f40b9000a3d3b691a2a2cd821052566717c3ead01089b56086af1366f
+Qy = 1e15a048d1dce642d9ebcbfac7f92b1bcee90fd0240cc79abd29e32e0e655c4ee1fd34fb88178bba92aca100e7794ed0
+k = 2a78e651623ba604c42cf094fc7d046629306f508853427ba091448800d1092c041bb2323035fc9d19a8d44950f7dcc3
+R = 0db0cc9a2bda8dd7e565ad36f91b1c5756d78164dc8a72a5bee4b6bc45ea38c7a16b01d05b1893d4e06b62db24c30385
+S = abd383edaeda7d0b8de1b54fcd3c28874fed62ab266f1f84c8ba796a7b54e5e0695fdb43ce7fe90ed00fa468d87bca64
+
+Msg = 4672fce0721d37c5be166bffa4b30d753bcf104b9b414db994b3ed33f36af4935ea59a0bb92db66448b3f57dad4fc67cef10ce141bf82c536be604b89a0bc0e8bca605b867880049d97142d30538fc543bd9d4fab7fdbe2f703815cdb6361beb66acff764bc275f910d1662445b07b92830db69a5994857f53657ed5ca282648
+d = 2e408c57921939f0e0fe2e80ce74a4fa4a1b4fa7ab070206298fe894d655be50e2583af9e45544b5d69c73dce8a2c8e7
+Qx = a2b24a5ad4a2e91f12199ed7699e3f297e27bf8b8ea8fbe7ed28366f3544cd8e680c238450f8a6422b40829d6647b25c
+Qy = 2732be0075536e6519f6a099b975a40f8e0de337fa4d48bd0762b43f41cab8deafdef9cfbb9973e457801e3bf9c93304
+k = b10b6258afdde81f9c971cc1526d942e20cafac02f59fee10f98e99b8674636bff1d84a6eaa49c0de8d8cfdc90d8ce84
+R = be428a8de89a364a134719141ee8d776a3a8338f1132b07e01b28573d8eaf3b9008b63304c48821e53638b6141f9660b
+S = 866181dbef5c147d391bed6adcee408c339982c307adc718c2b9ab9e5642d8dedc36dd6402559a3ab614c99c1e56b529
+
+Msg = 9ae48fdd9bfc5cb0f4d4761e28b2073bda05a3e3fe82c212e66701dc4573cc67a829b0f82d7520b1bf11db0c6d1743822bbe41bb0adbd7222aa5fae70fbd1a31f2d4453a01c81e064d775388468be96f6063f8673b7b8d4455fe1bd4c801ad5e625a015eaa4a1a18da490d2af8642201eaba3c611cbd65f861d8e19ca82a1ee6
+d = 1c285da72a8eb1c3c38faab8d3bb4e68dc95c797082b9a3991a21c1de54759071ecf2265fb1eff504ab24174bc6710cf
+Qx = 11acb1b5cc59a4f1df1913a8d6e91cbdafb8206dc44aff7d9da45906b664fc33194d9935a82aa4d62f39618897c86025
+Qy = 832ed0b9575fff52a3603bfe89f312751b4c396da98324117a61b3f525d27b2266f6cfb22be07e50b6874435e380ed62
+k = 2513075e02cc7fb3cff7b7adde46da31c5493749b5cf02758bd5b098a838bfd4d5e4c7fb8268bdc37e219c30efebe878
+R = b3d638b3be45f14f170da5bdc22d2114deac93ab340a25b3af2b5c18584bb9147e00dc6c67a2274f79aa4838793eb63f
+S = 876112bdca2c725eb2f6dbd76d07710a31f0c16d38430cb0817f320a25a9ecfec8a66137d0304612ae29a6a484fd3319
+
+Msg = 817d6a110a8fd0ca7b4d565558f68b59a156744d4c5aac5c6610c95451793de2a756f774558c61d21818d3ebeeeb71d132da1c23a02f4b305eccc5cd46bd21dfc173a8a91098354f10ffbb21bf63d9f4c3feb231c736504549a78fd76d39f3ad35c36178f5c233742d2917d5611d2073124845f1e3615b2ef25199a7a547e882
+d = 9da37e104938019fbdcf247e3df879a282c45f8fb57e6655e36b47723af42bec3b820f660436deb3de123a21de0ca37b
+Qx = 722d0ea6891d509b18b85ca56f74deb5c3030d2a30433824123d430d03c99279572c3b28ecf01e747b9db8acc55d0ba3
+Qy = 7e2605ea7092214f366f3639037bffd89fe103c646e990839d3a1ced8d78edb5b9bc60d834fd8e2a3c17e920bdae023a
+k = c8c18e53a9aa5915288c33132bd09323638f7995cd89162073984ed84e72e07a37e18c4c023933eace92c35d10e6b1b6
+R = 6512a8a2be731e301dcf4803764297862bbfa0ac8daed64d8e98b34618ecb20520fc5d3cf890b7783edf86e7ea407541
+S = 4ff10301f7b4168fae066361376007c1d7aa89a75c87719d0b54711ffef5ef3726f3eef84f7ebc025c110bde511b17f6
+
+Msg = 464f10ec6fb229a51db5fd0e122f2cb8a9a022117e2987f4007bf5565b2c16aba0714e2e3cdd0c100d55ac3017e36fc7501ad8309ab9572aa65424c9eb2e580a119c55777676ec498df53ef6ae78fd8a988130ee0e6082bf1ef71cd4c946021018a8ca7154d13b174c638912613b0bdb9001c302bf7e443ad2124ab2c1cce212
+d = 0661ab3bf9f7bef51bec7dff758de289154557beb9ce18cc4b8cc09a871e8322af259cf188b593dc62f03a19e75f7f69
+Qx = b4f100558043858efa728082d9b99ad5192b59b0947434f5ba7ff2514508a6d71ba54e7221c31cb0712103272b3f6fa4
+Qy = 34f6df4eeb2da11498044635067c2715ed15ae251c78ffb9030d87909ea8539b66394e93109ca54c0406cf99960c3e93
+k = 84a87137edb6894f96c5a8e94a3765162034feb84dfea94e1c71411170c285a80321ec7999e25861844143209804882c
+R = 4dc9d1b949b36e3c3847ac1c7ed114e1bc9cbe76119cf6fcd3f1b69ee6ee54e3255f1bb288fe2f8bd6d4049a21793c27
+S = 56a561d647b62ccae1e6df818b1a6fbde66c82ef0ff69ee415f183e7daf76be22630c7e02cd3fd729dfa490f26824584
+
+Msg = 4e3e0fb96320ddccde8b463c273654c4f7164920b1d63430921d2e808dee403e6420eedda0a557b911d00736a4f8798dd4ef26673efd6d190988ad4929ec64f8685cfb76070a36cd6a3a4bf2f54fb08a349d44642b6f614043fef9b2813b63457c76537d23da7b37310334f7ba76edf1999dad86f72aa3446445a65952ac4e50
+d = 66e7cfdeb7f264cf786e35210f458c32223c3a12a3bc4b63d53a5776bc9b069928452484f6241caa3781fd1a4109d4db
+Qx = 3c7682de540ab231daf21bf9fc80bda6abf7e17dcc79d476c7b7c3bd4d42d386877fd8ba495c1b0333e04fb5fd2a1505
+Qy = 0a1582e4f4d72abea9d3476aff8369c41261f0c5dddf2ca82e10f7a163f73df09473d9e5e2552187104e4cc7c6d83611
+k = 2fa266f5cce190eb77614933ca6a55121ad8bae168ff7a9043d96d13b5ca2fe70101ff9fe1e2b2cd7413e6aa8f49abde
+R = e7ecda9da0c52d0474a9f70094dc8f061d7d6a22210d3b69a7be8f389aa666f256322099b87d16ad35357ea856574dba
+S = ba348eb40a2830ec5a1130264ac0a8675420b1ae243e808a778135809ece21f42c0c881166321102b4f02df4c5c7ed9d
+
+Msg = c466b6b6baf7e6ffa876ec06105e2d43534e0517c07b1c4c9fb67ba81ce09525a7721ec3c290f2b1f65b6463d41598e7a25b2238501629953a5ca955b644354fb6856733a2e5bb8f5bc21a0c803493f5539f9fb83aab3dba2c982989c2270c61ab244b68bfe1b948d00c2ed975e09c29b5f8a7effcad8652a148cc880d503217
+d = 92c2f7ee64af86d003ab484e12b82fcf245fc330761057fec5b7af8f7e0a2d85b468c21d171460fcb829cae7b986316d
+Qx = ca43a306479bf8fb537d4b9ff9d635bbb2a0d60d9e854d5b7e269d09d91f78c6b90b616e4c931629453645a2bb371e14
+Qy = 356c4d7f10e690614eaf7f82ba0f9dc1aad98130c0ad9fe353deec565cc04bef789a0a4242322e0058b46cd02f2de77d
+k = 6ec81fb74f8725ba225f317264460ee300cfd2f02092000989acbdad4799cf55c244a65c557113328fe20282e6badb55
+R = cd7a4309bcebc25a8e10899fe2eda5f8b2dbcf329cd2f3d65befd67393e83fba2f8a67a15c01a6ac8314f9f5e87a9dca
+S = 6dcfc0426bc148e67e91d4784e3d7e9bc3b7ce3676be62daa7f3f55dfdff6d9dc735b5e3e0bbd0785db1f76f7ac065f3
+
+Msg = feac892b7720af80b3c9eede51e923f18d3d0c5de4c31f4aa75e36df7c7c2fd8f41778851a24b69e67dccb65e159dd5c383243bad7cfedcc5e85c8a01c34b0b94ba8e07e4c024c09d279b3731e8b62f9562d3c4f5042567efe42a9d0eaaabab28bc6f11232fc8ceaaf4518d9f3b2bebf020294496b7f6b879e69503f75fecd3d
+d = 15347caaad1067f1848a676bd0a8c52021ae604b79d02775a0459226e0391a3acd26653c916fcfe86149fb0ee0904476
+Qx = e5a0463163964d984f5bad0072d45bc2059939e60a826ccca36c151460ae360f5d6679f60fe43e999b6da5841c96e48a
+Qy = 30f2dd425a3fa2c95d34124217250b39e3b4a14f3e6e415ae8e5b0409eb72f43f78b64d0ce6f2d49980d6f04cd1391db
+k = 1a2d224db4bb9c241ca5cab18920fad615fa25c1db0de0f024cb3ace0d11ef72b056885446659f67650fdff692517b1c
+R = 87b4de0fb21df38dfc9a4b1e350da67547e307f55b5b9dd6615e408afe7c3553a6e02722847367439e636074faa2182b
+S = 375d965753b9ed6c6c08576726f8308c2f8dbd2737824464e71265d47907e26f615bbeb8203ec617520d4ecd1851dc44
+
+Msg = cf2982e3bf174ce547741b969403cd11e9553067e6af8177d89511a0eb040db924530bdba65d8b1ff714228db0737c1756f509e1506014a10736e65be2f91980a73891496e90ff2714a3601c7565cdcef5a395e2e0e1652f138d90d61eaa9cba993b823245647f6e07cec9b8b4449cd68a29741cd1579c66e548ca0d0acf33aa
+d = ac1cb5e59bda2eff3413a3bab80308f9fb32c595283c795de4c17fdae8d4647b5f108fd0801aee22adb7db129283b5aa
+Qx = bc6b1a718284803553c173089c397870aaaecca579bb8e81a8cfa12473cd2057567fa8726a19ed427cc035baeec2c551
+Qy = 14f82997d1129b669f0015350e47ad561b1b13441af4fb44656f15ed0c5706984d66655accc52f2e943eef39cb1cdc21
+k = 8053a46e875f446056b06d4318fa3e8977622de7207cbf0996bf35b0e9b19aaa507f642bcf0be9f048f1af09806f6946
+R = a994eb15b64114ce8a9342d18b5edda96a6d76314a5ac03da723699177d352a4a9f3b7121b11a91e43a6af4025da51d6
+S = 8183ae33a888e99aa76882da0a6705ad102f2bbd9572fad0d2e4d6d70151970469e00c5220e59c14724d771c1384b302
+
+Msg = bf9fdd4107ef5a6070108771ac9eee4f0c8043bf0d04db772a47294f4137e2439d94b337114b074e57e0cb78d0ccf352a2833e9788ee2a1a9ffeacd34f38fcefb86653d70c7dadd4cf6548d608e70acdef6c7530974b92c813798add659752a8c72b05e1ad9c65c21834ce6fbe49d8a1426b5a54270794436d284364fac6ec1a
+d = 205f1eb3dfacff2bdd8590e43e613b92512d6a415c5951bda7a6c37db3aae39b9b7ec6edd256609e75373419087fa71f
+Qx = c9f1f63a18c761b077a1ec35fbb2de635db9b8592c36194a01769b57728c7755d4c79b3d5b97a1a4631e30c86d03f13c
+Qy = f8c4a38770054d5cc9bb9182e6d4638242c4fd16e869ac22e44c4b9402d594e0c6f5df6a9a7de32a4893d9f6588f1950
+k = ecd395c5d8b7d6e6b2b19644e0d2e6086c912c6a0f5b8ed4b94b7290b65852c9741ce8eeb08d8751ead8a183e17d76c6
+R = e81331d78b438b0b8d98c1be03385ba5d614af182f1677f259126cc3de7eaac6c19b02be955d936b6bf9c27c6796e6f0
+S = 17c2b7a8e0fc93909762aa9f86f9561e759ecb88f02337b2018363be6095d9e4324a6d3296046686624b5efad6b52878
+
+Msg = 5d634fb39a2239256107dc68db19751540b4badac9ecf2fce644724401d6d632b3ae3b2e6d05746b77ddc0c899878032248c263eda08d3d004d35952ad7a9cfe19343d14b37f9f632245e7b7b5fae3cb31c5231f82b9f1884f2de7578fbf156c430257031ba97bc6579843bc7f59fcb9a6449a4cd942dffa6adb929cf219f0ad
+d = e21e3a739e7ded418df5d3e7bc2c4ae8da76266a1fc4c89e5b09923db80a72217f1e96158031be42914cf3ee725748c1
+Qx = 0f753171922b5334f3dd2778a64ce2da8295121939beae71ad85e5344e893be0fd03cf14e1f031adec098e0c4409449c
+Qy = 45c10a0ffc0eb2f1cec5c89b698061108313ee7d449ad580efad344f0e7cf35be8a18fca620f112e57bdc746abdace55
+k = d06bea06b25e6c30e866b1eb0657b45673e37b709013fb28fd7373afc8277cbc861354f821d0bd1927e52ec083a0f41f
+R = e8d4a31dd0e7d2522be62a32608e744c3775ceb606dc897899f0c73f1a40ce9a8be854cd506e65cd81fd7fa2c616cb7b
+S = 8151b681b6b6046d3c36f332d06d9ba7751e740631cdb759f88c50a25a8e950d5023df8a15c77243743733c4feaf21d5
+
+Msg = c9b4ff721b3e886f0dc05856ffff0aabb64a8504b1746a47fdd73e6b7ebc068f06ac7ffa44c757e4de207fc3cbfaf0469d3ac6795d40630bcafe8c658627e4bc6b86fd6a2135afbc18ccc8e6d0e1e86016930ca92edc5aa3fbe2c57de136d0ea5f41642b6a5d0ddeb380f2454d76a16639d663687f2a2e29fb9304243900d26d
+d = 93434d3c03ec1da8510b74902c3b3e0cb9e8d7dccad37594d28b93e065b468d9af4892a03763a63eae060c769119c23c
+Qx = a52c25f2af70e5bc6a992ecef4ea54e831ed5b9453747d28aec5cffb2fcfee05be80c5cbab21606b5507aa23878adee1
+Qy = 2cf2a9afeff83f3041dc8a05f016ccae58aa1a0e0dc6be9d928e97f2598c9ba5e9718d5eb74c9cfb516fd8c09f55f5b9
+k = 13d047708ae5228d6e3bbada0e385afdb3b735b31123454fdf40afe3c36efed563fd2cce84dcc45c553b0993d9ca9ec3
+R = a0203f6f2c456baac03538ed506a182e57a25151802cf4b2557613b2fb615ebd4c50ddc505f87c048a45bad3b2fc371c
+S = 0eab56457c4080400fa3af124761d5a01fef35f9649edba8b97d22116386f3b8b363e97ef3f82616d5d825df1cf865ef
+
+Msg = db2ad659cf21bc9c1f7e6469c5f262b73261d49f7b1755fc137636e8ce0202f929dca4466c422284c10be8f351f36333ebc04b1888cba217c0fec872b2dfc3aa0d544e5e06a9518a8cfe3df5b20fbcb14a9bf218e3bf6a8e024530a17bab50906be34d9f9bba69af0b11d8ed426b9ec75c3bd1f2e5b8756e4a72ff846bc9e498
+d = e36339ddbe8787062a9bc4e1540690915dd2a2f11b3fe9ee946e281a0a2cbed426df405ed9cb0eca42f85443efd09e0c
+Qx = a1ffb4b790d1593e907369b69de10b93cddbb02c6131f787422364d9d692768ef8097970306cce16c97f2b10c538efa7
+Qy = d0692028601ea794d2563ffe9facc7273938fab47dd00b8960be15549a9c2b3f8552583eb4c6cd212fe486c159c79153
+k = 2226f7329378cecd697f36ae151546643d67760856854661e31d424fae662da910e2157da9bb6dfbe3622296e0b5710c
+R = 20dcc25b67dd997621f437f65d78347fb57f8295b1b14453b1128203cda892bcfe726a2f107d30975d63172e56f11d76
+S = 51cff592cbef75ef8321c8fa1e4229c4298b8180e427bee4e91d1e24fc28a729cf296beb728960d2a58cf26773d8e2e2
+
+Msg = dbd8ddc02771a5ff7359d5216536b2e524a2d0b6ff180fa29a41a8847b6f45f1b1d52344d32aea62a23ea3d8584deaaea38ee92d1314fdb4fbbecdad27ac810f02de0452332939f644aa9fe526d313cea81b9c3f6a8dbbeafc899d0cdaeb1dca05160a8a039662c4c845a3dbb07be2bc8c9150e344103e404411668c48aa7792
+d = 5da87be7af63fdaf40662bd2ba87597f54d7d52fae4b298308956cddbe5664f1e3c48cc6fd3c99291b0ce7a62a99a855
+Qx = 54c79da7f8faeeee6f3a1fdc664e405d5c0fb3b904715f3a9d89d6fda7eabe6cee86ef82c19fca0d1a29e09c1acfcf18
+Qy = 926c17d68778eb066c2078cdb688b17399e54bde5a79ef1852352a58967dff02c17a792d39f95c76d146fdc086fe26b0
+k = 1b686b45a31b31f6de9ed5362e18a3f8c8feded3d3b251b134835843b7ae8ede57c61dc61a30993123ac7699de4b6eac
+R = 9dbfa147375767dde81b014f1e3bf579c44dd22486998a9b6f9e0920e53faa11eed29a4e2356e393afd1f5c1b060a958
+S = e4d318391f7cbfe70da78908d42db85225c85f4f2ff413ecad50aad5833abe91bdd5f6d64b0cd281398eab19452087dd
+
+
+[P-521,SHA-224]
+
+Msg = 58ec2b2ceb80207ff51b17688bd5850f9388ce0b4a4f7316f5af6f52cfc4dde4192b6dbd97b56f93d1e4073517ac6c6140429b5484e266d07127e28b8e613ddf65888cbd5242b2f0eee4d5754eb11f25dfa5c3f87c790de371856c882731a157083a00d8eae29a57884dbbfcd98922c12cf5d73066daabe3bf3f42cfbdb9d853
+d = 1d7bb864c5b5ecae019296cf9b5c63a166f5f1113942819b1933d889a96d12245777a99428f93de4fc9a18d709bf91889d7f8dddd522b4c364aeae13c983e9fae46
+Qx = 1a7596d38aac7868327ddc1ef5e8178cf052b7ebc512828e8a45955d85bef49494d15278198bbcc5454358c12a2af9a3874e7002e1a2f02fcb36ff3e3b4bc0c69e7
+Qy = 184902e515982bb225b8c84f245e61b327c08e94d41c07d0b4101a963e02fe52f6a9f33e8b1de2394e0cb74c40790b4e489b5500e6804cabed0fe8c192443d4027b
+k = 141f679033b27ec29219afd8aa123d5e535c227badbe2c86ff6eafa5116e9778000f538579a80ca4739b1675b8ff8b6245347852aa524fe9aad781f9b672e0bb3ff
+R = 06b973a638bde22d8c1c0d804d94e40538526093705f92c0c4dac2c72e7db013a9c89ffc5b12a396886305ddf0cbaa7f10cdd4cd8866334c8abfc800e5cca365391
+S = 0b0a01eca07a3964dd27d9ba6f3750615ea36434979dc73e153cd8ed1dbcde2885ead5757ebcabba117a64fcff9b5085d848f107f0c9ecc83dfa2fa09ada3503028
+
+Msg = 2449a53e0581f1b56d1e463b1c1686d33b3491efe1f3cc0443ba05d65694597cc7a2595bda9cae939166eb03cec624a788c9bbab69a39fb6554649131a56b26295683d8ac1aea969040413df405325425146c1e3a138d2f4f772ae2ed917cc36465acd66150058622440d7e77b3ad621e1c43a3f277da88d850d608079d9b911
+d = 17e49b8ea8f9d1b7c0378e378a7a42e68e12cf78779ed41dcd29a090ae7e0f883b0d0f2cbc8f0473c0ad6732bea40d371a7f363bc6537d075bd1a4c23e558b0bc73
+Qx = 0156cd2c485012ea5d5aadad724fb87558637de37b34485c4cf7c8cbc3e4f106cb1efd3e64f0adf99ddb51e3ac991bdd90785172386cdaf2c582cc46d6c99b0fed1
+Qy = 1edeeda717554252b9f1e13553d4af028ec9e158dbe12332684fc1676dc731f39138a5d301376505a9ab04d562cc1659b0be9cb2b5e03bad8b412f2699c245b0ba2
+k = 1dc3e60a788caa5f62cb079f332d7e5c918974643dca3ab3566a599642cd84964fbef43ce94290041fe3d2c8c26104d9c73a57a7d4724613242531083b49e255f33
+R = 12592c0be6cce18efb2b972cd193d036dcb850f2390fa8b9b86b2f876548bc424fb3bc13c1e5c415fa09d0ecfcae5bf76fb23e8322d7eecb264a2ae6d20ef50d405
+S = 11bc9713be88e3b9912a3e5f5d7b56f20573e979b1a75d04ce339f724bddffa4665d25995fe24d32507d8a07c5e10169f5338ef2827737f7b0291752b21237217e3
+
+Msg = 7ba05797b5b67e1adfafb7fae20c0c0abe1543c94cee92d5021e1abc57720a6107999c70eacf3d4a79702cd4e6885fa1b7155398ac729d1ed6b45e51fe114c46caf444b20b406ad9cde6b9b2687aa645b46b51ab790b67047219e7290df1a797f35949aaf912a0a8556bb21018e7f70427c0fc018e461755378b981d0d9df3a9
+d = 135ea346852f837d10c1b2dfb8012ae8215801a7e85d4446dadd993c68d1e9206e1d8651b7ed763b95f707a52410eeef4f21ae9429828289eaea1fd9caadf826ace
+Qx = 18d40cc4573892b3e467d314c39c95615ee0510e3e4dbc9fa28f6cd1f73e7acde15ad7c8c5339df9a7774f8155130e7d1f8de9139ddd6dfe1841c1e64c38ea98243
+Qy = 17021782d33dc513716c83afe7ba5e7abef9cb25b31f483661115b8d6b5ae469aaf6f3d54baa3b658a9af9b6249fd4d5ea7a07cb8b600f1df72b81dac614cfc384a
+k = 0c24acc1edb3777212e5b0bac744eadf4eda11fa150753b355bf96b189e6f57fc02284bb22d8b3cd8bba7a09aae9f4ea955b382063425a6f8da2f99b9647b147172
+R = 183da7b8a9f9d5f08903359c1a2435b085fcf26a2ed09ab71357bb7634054acc569535e6fe81d28233e4703005fc4bf83ce794d9463d575795aa0f03398e854cefd
+S = 0b3621145b9866ab7809139795cc30cd0404127a7f0fafa793660491009f6c53724fdb0b1ffbf0fd51c131180b8a957fe66e76d2970247c024261c768dee9abbfb9
+
+Msg = 716dabdb22a1c854ec60420249905a1d7ca68dd573efaff7542e76f0eae54a1828db69a39a1206cd05e10e681f24881b131e042ed9e19f5995c253840e937b809dfb8027fed71d541860f318691c13a2eb514daa5889410f256305f3b5b47cc16f7a7dad6359589b5f4568de4c4aae2357a8ea5e0ebaa5b89063eb3aa44eb952
+d = 1393cb1ee9bfd7f7b9c057ecc66b43e807e12515f66ed7e9c9210ba1514693965988e567fbad7c3f17231aacee0e9b9a4b1940504b1cd4fd5edfaa62ba4e3e476fc
+Qx = 1e855c935139c8092092cfa733db1292530506eeb2bbb1687f9602c36d97a6714e998892d5d3b842d1896a6ece9d549e9792881a256256137b3dff180c96cc5d07b
+Qy = 18d83b6e93cd287311f7bf7c1d7f9eeabcf0b69c12f2d8f40e333e81e956d968532a37a4c04d761874df293b484cd7053b03fdbc2fdcd3b4c412d6f272fb7c93fe6
+k = 1d98619bdc04735d30c222fc67da82c069aea5f449af5e8c4db10c1786c0cb9e6f2cc0bb66fa6be18c485570d648dafcd0a973c43d5c94e9a9dacbd3170e53fa2a0
+R = 0bf47fabe107ce0ec03e2ad60a79b058e1bebb18568b6a8cdbe86032e71aa30c15766105b2ea952cfa79bcab046df601159f96e179bbcf252dc68ac73d31481fdae
+S = 1f918fec69cd07d90f9d892b7117e7519c3224947f4262f1fd97077dd5386a6c78aeddff3ee97e59ea353f06029f1336f0d6ef5c0f4b17ca59343a55319b7bfc3db
+
+Msg = 9cc9c2f131fe3ac7ea91ae6d832c7788cbbf34f68e839269c336ceef7bef6f20c0a62ea8cc340a333a3002145d07eba4cf4026a0c4b26b0217a0046701de92d573d7c87a386a1ea68dc80525b7dcc9be41b451ad9f3d16819e2a0a0b5a0c56736da3709e64761f97cae2399de2a4022dc4c3d73c7a1735c36dbde86c4bc5b6f7
+d = 179fa164e051c5851e8a37d82c181e809a05fea9a3f083299b22684f59aa27e40dc5a33b3f7949338764d46bfe1f355134750518b856d98d9167ef07aac3092c549
+Qx = 1857cc7bbed20e87b3fd9a104956aa20c6502192910e0e7598410526ebfe1c99397b85189612a60c51fb8f4dd5cb08a8cd2e702563062dcb043410715c5323a0046
+Qy = 1fce8d135284310d2f38c216030634b32cd223222f0d9d8d2b7c55477c4b8b74fc6c96a6092f34b05ca44d3633a5037c2166c479a032bb4f949f89fc1ba5236d07d
+k = 16d9704c0cee791f2938bb2a8a595752a3635c2f557efeecefd719414b5f2aaf846080f582c76eae7a8fddf81859b49d0131c212524d55defa67dca1a9a28ca400f
+R = 1c9a4e51774384e8362876a87c572e6463a54413c7c6252c552ebb182f83e45ace436ade4ca373d8a7216e83efb62c8b41c4d5132a0afa65078f16d189baca39187
+S = 1e92a7dd5fea29a666398e1df5775cbb5664fe6943fe4c1d2bba516b7543c84df584458e53919c4ffab579a26fb3c892a5d1a77b0a07428c89350f8b559e627b014
+
+Msg = 14c69f8d660f7a6b37b13a6d9788eff16311b67598ab8368039ea1d9146e54f55a83b3d13d7ac9652135933c68fafd993a582253be0deea282d86046c2fb6fd3a7b2c80874ced28d8bed791bd4134c796bb7baf195bdd0dc6fa03fdb7f98755ca063fb1349e56fd0375cf94774df4203b34495404ebb86f1c7875b85174c574c
+d = 13dabca37130ba278eae2b3d106b5407711b0d3b437fbf1c952f0773571570764d2c7cb8896a8815f3f1975b21adc6697898e5c0a4242092fc1b80db819a4702df4
+Qx = 0bc2aebf40cd435bc37d73c09d05f2fd71321111a767c2b0d446f90dd4a186839c694ceb734e027e7ee948f0f63e4d3f1656d3d543df23c342a599306909b347109
+Qy = 1f4c98ac03f0718e58d5d1762c920445b11dbdd60ec7f60095809204e14965a4ecb0be6fea06adbac8ba431d6f144c75c199225df2a619a34be99897125b3a10af8
+k = 0401187c8b89945a1e48cda9ee52167789f4121e67482a7ac797899f5d3d2e623aed31e4adae08a8d43e69028fa074d2650317cbc765f6ed191cf0317b4bae57881
+R = 1e572afed754016fba43fc33e352932c4db65efcb84e2bd159b40fc5925893b161effc40240be28d8c07154d2615f605c6f0451b976522d95afd37f46602df7a12a
+S = 030370c1c5352c2b663ac1858b42f69545b2f58ed5b2c007f303726977d3c756b5d644ec6788f94c886f78269aa190a3d8d1ae10e4fd24d937c4556fb9e1953fd6d
+
+Msg = 8d8e75df200c177dbfe61be61567b82177ea5ec58e2781168d2277d2fd42668f01248ca3eb29ffa2689b12ae40f9c429532b6d2e1f15891322b825a0a072a1c68fa09e78cfdef3e95ed6fdf7233a43cb68236560d49a3278f0b3f47cb08f475bd9ab2f60755ea4a1767de9313b71a1b9ea87ef33f34682efbda263b0f8cc2f52
+d = 198681adbde7840d7ccd9cf1fb82056433fb4dd26bddf909af7b3b99da1ca2c05c8d4560ecd80ba68f376f8b487897e374e99a9288ed7e3645cc0d00a478aae8d16
+Qx = 057ce3777af7032f1f82308682e71fe09f88bf29dacd5018a725e1caa4b1e2bfdd894fe618f9266f31ba089856dc9c1b70e4a2faa08b4b744d1aafcd5ae99e2c736
+Qy = 199bcfef2021bc5890d7d39ec5dc0c26956801e84cae742cf6c50386eb289b6e97754dd25a94abf81f1cb1b36935b5eb29f4b32a6516d2ff6a7d23064a0daec94b3
+k = 19d2d74ad8ee2d85048f386998a71899ef6c960b4ab324e5fd1c0a076c5a632fd0009500076522e052c5c9806eef7056da48df6b16eb71cdf0f1838b0e21715fce0
+R = 18ecacbcffd5414bbb96728e5f2d4c90178e27733d13617e134ec788022db124374bbaa11e2c77fe3f38d1af6e998e1b0266b77380984c423e80ffa6ff2bcafd57a
+S = 1c727f34b6a378f3087721a54e9796499b597ecf6666b8f18312d67e1190a8a66e878efc2367b551267494e0245979ef4deed6d2cbf2c3711af6d82ccfeb101a377
+
+Msg = 10631c3d438870f311c905e569a58e56d20a2a560e857f0f9bac2bb7233ec40c79de145294da0937e6b5e5c34fff4e6270823e5c8553c07d4adf25f614845b2eac731c5773ebbd716ab45698d156d043859945de57473389954d223522fbafecf560b07ef9ba861bcc1df9a7a89cdd6debf4cd9bf2cf28c193393569ccbd0398
+d = 08c4c0fd9696d86e99a6c1c32349a89a0b0c8384f2829d1281730d4e9af1df1ad5a0bcfccc6a03a703b210defd5d49a6fb82536f88b885776f0f7861c6fc010ef37
+Qx = 164ac88ed9afe137f648dd89cdd9956682830cac5f7c1a06d19a1b19f82bb1d22dfeefea30d35c11202fed93fd5ce64835d27c6564d6e181287fa04a2d20994986b
+Qy = 05cb83669265f5380ccefe6b4f85fdf0049e6703f6f378a0b2e52ed0fbbcf300afebb722f4ed48e3819cb976c1d60e2ba05646b478f6dfecfbae730e9644c297f00
+k = 189801432cba9bf8c0763d43b6ec3b8636e62324587a4e27905b09a58e4aa66d07d096dbce87824e837be1c243dd741f983c535a5dd2f077aac8beee9918258d3cb
+R = 0917723f7241e8dc7cd746b699ab621d068dd3a90e906aaf0a4862744b96fd4e5ccdb9c7796c27f7196e693d06ec209464c3ea60ad6313e9b77cceaa14767e6651c
+S = 0957b0ecdc3668f6efa5d0957615bcfffd6419c5e57579b74f960f65ae3fb9e8284322ff710b066f7e0959ac926d3cf9a594bdb70bbec756c96910b26a2486dee9e
+
+Msg = 80aad6d696cbe654faa0d0a24d2f50d46e4f00a1b488ea1a98ed06c44d1d0c568beb4ab3674fc2b1d2d3da1053f28940e89ba1244899e8515cabdd66e99a77df31e90d93e37a8a240e803a998209988fc829e239150da058a300489e33bf3dcdaf7d06069e74569fee77f4e3875d0a713ccd2b7e9d7be62b34b6e375e84209ef
+d = 1466d14f8fbe25544b209c5e6a000b771ef107867e28ed489a42015119d1aa64bff51d6b7a0ac88673bbc3618c917561cff4a41cdb7c2833dab5ebb9d0ddf2ca256
+Qx = 1dc8b71d55700573a26af6698b92b66180cf43e153edadb720780321dbb4e71d28e0a488e4201d207fc4848fe9dd10dcabec44492656a3ff7a665fe932445c82d0b
+Qy = 1920b16331b7abeb3db883a31288ef66f80b7728b008b3cc33e03a68f68d9e653a86e3177bbc00014fa5ea4c1608c0d455c2e2ac7bd8ab8519ebf19955edf1baf8d
+k = 160d04420e0d31b0df476f83393b1f9aff68389cc3299e42ef348d97646f7531a722b66ddfb9501bbb5c4a41d84c78be7233b11489bceb817d23060e6017433fab8
+R = 08077aabd0a342f03f912007c586cfedfc63f93d1118f720d5b62b3ce141a60f86f111dfd8fc2e31a6778981f1a5e28f29a7369bd7897bb41240c8d3a9c170e0ee0
+S = 00abc75fc154b93840579457820957e89d1260fee0a4b9bb1946f61ca1e71afd76bb5e1077b3e38ceb39d1fac5ef8b217c4110617b3ad118e02b3fcc2a39ef38613
+
+Msg = 8a7792a2870d2dd341cd9c4a2a9ec2da753dcb0f692b70b64cef2e22071389c70b3b188dea5f409fb435cbd09082f59de6bc2ff9e65f91b7acc51e6e7f8e513148cb3c7c4664f227d5c704626b0fda447aa87b9d47cd99789b88628eb642ed250312de5ba6b25f3d5342a3cbb7ebd69b0044ee2b4c9ba5e3f5195afb6bea823d
+d = 01a99fcf54c9b85010f20dc4e48199266c70767e18b2c618044542cd0e23733817776a1a45dbd74a8e8244a313d96c779f723013cd88886cb7a08ef7ee8fdd862e7
+Qx = 1912d33b01d51e2f777bdbd1ada23f2b1a9faf2be2f2a3b152547db9b149b697dd71824ca96547462e347bc4ef9530e7466318c25338c7e04323b1ba5fd25ea7162
+Qy = 0bbe9b1e3a84accd69b76b253f556c63e3f374e3de0d1f5e3600fc19215533b2e40d6b32c3af33314d223ea2366a51d1a337af858f69326389276f91be5c466e649
+k = 14fafd60cb026f50c23481867772411bb426ec6b97054e025b35db74fe8ea8f74faa2d36e7d40b4652d1f61794878510b49b7b4fe4349afccd24fc45fec2fd9e9e7
+R = 18b1df1b6d7030a23a154cacce4a2e3761cc6251ff8bf6c9f6c89d0a15123baef9b338ada59728349ce685c03109fcde512ed01a40afd2ca34e1bc02ecf2871d45c
+S = 0a399f9b9e21aeddf450429fec2dc5749e4a4c7e4f94cee736004dcc089c47635da22845992cd076a4f0a01d2cc1b0af6e17b81a802361699b862157ad6cad8bd1d
+
+Msg = f971bcd396efb8392207b5ca72ac62649b47732fba8feaa8e84f7fb36b3edb5d7b5333fbfa39a4f882cb42fe57cd1ace43d06aaad33d0603741a18bc261caa14f29ead389f7c20536d406e9d39c34079812ba26b39baedf5feb1ef1f79990496dd019c87e38c38c486ec1c251da2a8a9a57854b80fcd513285e8dee8c43a9890
+d = 1b6015d898611fbaf0b66a344fa18d1d488564352bf1c2da40f52cd997952f8ccb436b693851f9ccb69c519d8a033cf27035c27233324f10e9969a3b384e1c1dc73
+Qx = 110c6177ceb44b0aec814063f297c0c890671220413dbd900e4f037a67d87583eaf4b6a9a1d2092472c17641362313c6a96f19829bb982e76e3a993932b848c7a97
+Qy = 0f6e566c4e49b2ee70a900dc53295640f3a4a66732df80b29f497f4ae2fa61d0949f7f4b12556967bb92201a4f5d1384d741120c95b617b99c47a61e11c93a482d6
+k = 1a88667b9bdfe72fb87a6999a59b8b139e18ef9273261549bc394d884db5aa64a0bc7c7d38a8ef17333478d2119d826e2540560d65f52b9a6dc91be1340cfd8f8f8
+R = 015f73def52ea47ddb03e0a5d154999642202e06e6734ac930c1dc84756c67bbb1cca9f21f92d61bfdb2052c5dd2833349610f68139393d77250a7662ef7bd17cbe
+S = 155c744a729f83b27d1f325a91e63a0d564fe96ff91eaa1bad3bff17d2abffa065d14a1d20a04dd993f6ed3260b60bcc6401e31f6bc75aaafe03e8c1a9cd14d2708
+
+Msg = ec0d468447222506b4ead04ea1a17e2aa96eeb3e5f066367975dbaea426104f2111c45e206752896e5fa7594d74ed184493598783cb8079e0e915b638d5c317fa978d9011b44a76b28d752462adf305bde321431f7f34b017c9a35bae8786755a62e746480fa3524d398a6ff5fdc6cec54c07221cce61e46fd0a1af932fa8a33
+d = 05e0d47bf37f83bcc9cd834245c42420b68751ac552f8a4aae8c24b6064ae3d33508ecd2c17ec391558ec79c8440117ad80e5e22770dac7f2017b755255000c853c
+Qx = 1a6effc96a7f23a44bf9988f64e5cfafdae23fa14e4bee530af35d7a4ddf6b80dcd0d937be9dd2db3adcda2f5216fecbce867ee67e7e3773082f255156e31358c2f
+Qy = 1e7760190dfbe07ec2df87067597087de262c1e0a12355456faba91b2e7277050d73b924e14c0e93b8457a8b3e1f4207ce6e754274f88ad75c000d1b2977edc9c1a
+k = 18afea9a6a408db1e7a7bb1437a3d276f231eacfc57678bfa229d78681cbe4e800e6065332a3128db65d3aa446bb35b517dca26b02e106e1311881a95b0302d15e8
+R = 01c49b3c1d21f1678bdbe1ac12167e95e06617190bdee1a729c1c649210da19e2e210f6689e1310513bfe2ac6c0f4ee5f324f344b31b18df341eaadb826d07adc9b
+S = 129d4931ba457443012f6ffecd002f2abc3a4b65a58fee8457917ebcf24b29a1d3055b7fc62939a74ebb0c3582172ee7c3c75e0b2fa2367c6e04df63a7a91d593ad
+
+Msg = d891da97d2b612fa6483ee7870e0f10fc12a89f9e33d636f587f72e0049f5888782ccde3ea737e2abca41492bac291e20de5b84157a43c5ea900aef761006a4471072ab6ae6d515ffe227695d3ff2341355b8398f72a723ae947f9618237c4b6642a36974860b452c0c6202688bc0814710cbbff4b8e0d1395e8671ae67ada01
+d = 1804ab8f90ff518b58019a0b30c9ed8e00326d42671b71b067e6f815ac6752fa35016bd33455ab51ad4550424034419db8314a91362c28e29a80fbd193670f56ace
+Qx = 0a79529d23a832412825c3c2ad5f121c436af0f29990347ecfa586ce2e57fd3c7e0624d8db1f099c53473dbc2578f85416ad2ac958a162051014fb96bf07f9e1d17
+Qy = 17c0750f26df0c621d2d243c6c99f195f0086947b1bf0f43731555f5d677e2d4a082fb5fe8da87e1592a5fa31777da3299cede5a6f756edf81c85b77853388bb3ab
+k = 042d7c36fec0415bc875deb0fab0c64548554062e618aee3aa6670ffd68ab579fe620d3a9316357267fd3111c0ed567dca663acd94b646d2ba0771953cd9690ef42
+R = 0d01dfbef126febbdfa03ef43603fd73bc7d2296dce052216e965fed7bb8cbbc24142bfcddb60c2e0bef185833a225daa0c91a2d9665176d4ad9986da785f4bfcf0
+S = 16627e2614dbcd371693c10bbf579c90c31a46c8d88adf59912c0c529047b053a7c7715142f64dcf5945dbc69ff5b706c4b0f5448d04dd1f0b5a4c3765148bf253d
+
+Msg = 924e4afc979d1fd1ec8ab17e02b69964a1f025882611d9ba57c772175926944e42c68422d15f9326285538a348f9301e593e02c35a9817b160c05e21003d202473db69df695191be22db05615561951867f8425f88c29ba8997a41a2f96b5cee791307369671543373ea91d5ed9d6a34794d33305db8975b061864e6b0fe775f
+d = 0159bff3a4e42b133e20148950452d99681de6649a56b904ee3358d6dd01fb6c76ea05345cb9ea216e5f5db9ecec201880bdff0ed02ac28a6891c164036c538b8a8
+Qx = 12d7f260e570cf548743d0557077139d65245c7b854ca58c85920ac2b290f2abfeccd3bb4217ee4a29b92513ddce3b5cbf7488fb65180bb74aeb7575f8682337ef5
+Qy = 17560186230c7e8bff0bffce1272afcd37534f317b453b40716436a44e4731a3ec90a8f17c53357bc54e6ff22fc5b4ca892321aa7891252d140ece88e25258b63d5
+k = 14b8a30f988cefdc0edec59537264edb0b697d8c4f9e8507cf72bc01c761304bd2019da1d67e577b84c1c43dd034b7569f16635a771542b0399737025b8d817e1c3
+R = 0fc50939ebca4f4daa83e7eaf6907cb08f330c01d6ea497b86becda43dfcad47cb5c48f5eb2cc924228628070bcd144088c449a7873242ba86badf796097dbecd6d
+S = 0ccb6463c4301ba5c043e47ed508d57dd908fd0d533af89fd3b11e76343a1cf2954ce90b0eb18cbc36acd6d76b3906612d8a0feec6ebed13d88650ed9c708b28a11
+
+Msg = c64319c8aa1c1ae676630045ae488aedebca19d753704182c4bf3b306b75db98e9be438234233c2f14e3b97c2f55236950629885ac1e0bd015db0f912913ffb6f1361c4cc25c3cd434583b0f7a5a9e1a549aa523614268037973b65eb59c0c16a19a49bfaa13d507b29d5c7a146cd8da2917665100ac9de2d75fa48cb708ac79
+d = 17418dfc0fc3d38f02aa06b7df6afa9e0d08540fc40da2b459c727cff052eb0827bdb3d53f61eb3033eb083c224086e48e3eea7e85e31428ffe517328e253f166ad
+Qx = 00188366b9419a900ab0ed9633426d51e25e8dc03f4f0e7549904243981ec469c8d6d938f6714ee620e63bb0ec536376a73d24d40e58ad9eb44d1e6063f2eb4c51d
+Qy = 09889b9203d52b9243fd515294a674afd6b81df4637ffdddc43a7414741eda78d8aa862c9cbbb618acec55bb9a29aac59616fc804a52a97a9fc4d03254f4469effe
+k = 1211c8824dcbfa0e1e15a04779c9068aed2431daeac298260795e6a80401f11f6d52d36bcee3cfa36627989c49d11475163aa201d2cd4c5394144a6bb500bbaf02b
+R = 1d59401b8ac438855d545a699991142685077a409de2418c7ccfe01a4771b3870e76287a9654c209b58a12b0f51e8dc568e33140a6b630324f7ef17caa64bf4c139
+S = 143af360b7971095b3b50679a13cd49217189eaee4713f4201720175216573c68f7ac6f688bfe6eb940a2d971809bf36c0a77decc553b025ed41935a3898685183b
+
+[P-521,SHA-256]
+
+Msg = 8ab8176b16278db54f84328ae0b75ef8f0cd18afdf40c04ad0927ed0f6d9e47470396c8e87cde7a9be2ffbfe6c9658c88b7de4d582111119c433b2e4a504493f0a1166e3a3ea0d7b93358f4a297d63f65a5e752f94e2ee7f49ebcc742fa3eb03a617d00c574245b77a20033854d82964b2949e2247637239ab00baf4d170d97c
+d = 1e8c05996b85e6f3f875712a09c1b40672b5e7a78d5852de01585c5fb990bf3812c3245534a714389ae9014d677a449efd658254e610da8e6cad33414b9d33e0d7a
+Qx = 07d042ca19408524e68b981f1419351e3b84736c77fe58fee7d11317df2e850d960c7dd10d10ba714c8a609d163502b79d682e8bbecd4f52591d2748533e45a867a
+Qy = 197ac6416111ccf987d290459ebc8ad9ec56e49059c992155539a36a626631f4a2d89164b985154f2dddc0281ee5b5178271f3a76a0914c3fcd1f97be8e8376efb3
+k = 0dc8daaacddb8fd2ff5c34a5ce183a42261ad3c64dbfc095e58924364dc47ea1c05e2599aae917c2c95f47d6bb37da008af9f55730ddbe4d8ded24f9e8daa46db6a
+R = 09dd1f2a716843eedec7a6645ac834d4336e7b18e35701f06cae9d6b290d41491424735f3b57e829ad5de055eaeef1778f051c1ee152bf2131a081e53df2a567a8a
+S = 02148e8428d70a72bc9fa986c38c2c97deda0420f222f9dc99d32c0acba699dc7ba0a2b79ce5999ff61bd0b233c744a893bc105bca5c235423e531612da65d72e62
+
+Msg = c4bc2cec829036469e55acdd277745034e4e3cc4fcd2f50ec8bd89055c19795a1e051ccf9aa178e12f9beab6a016a7257e391faa536eaa5c969396d4e1ade36795a82ebc709d9422de8497e5b68e7292538d4ccdc6dd66d27a3ece6a2844962b77db073df9489c9710585ba03d53fa430dbc6626dc03b61d53fc180b9af5dea6
+d = 0b65bf33b2f27d52cbfabcadce741e691bf4762089afd37964de1a0deda98331bf8c74020a14b52d44d26e2f6fa7bcddbe83be7db17a0c8a1b376469cf92c6da27c
+Qx = 10038bb9a7aea626de68c14c64243150e72c69e2f8a1ab922bfbdaa6f33d24fb4542c0324357b0dd640bbcd07632ecd253f64ca2bfbfbf3de9b24fffd0568ab82da
+Qy = 0faf867d95308cc36d6f46844a0f535dc70f9768eed011a2464d2f308fa1d8e72c3616aec7e70516908183ffce7fdd36984a15f73efaa3858c2edf16a784d40e6c2
+k = 14aeb96c57d99677a1f5e4588064215e7e9af4027bfb8f31ff6126dbf341b8e6f719465e4273e91ba32670feca802549808322b7ee108bb20653cf20f93284d365f
+R = 075ead62edf7d86c5d1bc2443d1aeb5dc034fd999e6ea012cef7499d9d050cd97d262095884e9fc89a42e15bd3dee80fe3c1ba10f4caabc4aabb86347023028b663
+S = 129a992a6ff66d41948d11fa680f732b1a74315b804c982805190ed9d2fae223f2b149980b9241998cdea0c5672595a8a49d5186a0ef7a46c0a376f925bdda81726
+
+Msg = 1c1b641d0511a0625a4b33e7639d7a057e27f3a7f818e67f593286c8a4c827bb1f3e4f399027e57f18a45403a310c785b50e5a03517c72b45ef8c242a57b162debf2e80c1cf6c7b90237aede5f4ab1fcaf8187be3beb524c223cc0ceff24429eb181a5eea364a748c713214880d976c2cd497fd65ab3854ad0d6c2c1913d3a06
+d = 02c4e660609e99becd61c14d043e8b419a663010cc1d8f9469897d7d0a4f076a619a7214a2a9d07957b028f7d8539ba7430d0b9a7de08beeeae8452d7bb0eac669d
+Qx = 0fb3868238ca840dbb36ecc6cf04f5f773ea0ab8e8b0fdcf779dc4039a8d7146a417504e953c0cb5e7f4e599cc2c168deda8b7f16084b5582f89f2ece4cae5167f7
+Qy = 1f90b5c15eeda48e747cf3ee8183166a49dbfac6161cbd09d29d40a6854f4c495e88a435892a920cdaad20d41985890b648badd4f0a858ffcbd9afdfc23134ede18
+k = 1f875bbf882cd6dd034a87916c7b3ba54b41b2ea2ce84ebaf4e393fcf7291fee09dec2b5bb8b6490997c9e62f077c34f0947fe14cec99b906dd6bf0b5d301e75ca1
+R = 07aa70425697736b298233249f5d0cf25c99e640c9ff88035ef1804820e1bfe7d043755f02d7a079494f7fa6dc26740c4e6b7b430c63f29c67bbd3a5c88d2f0e8d1
+S = 0e0d42e4ff11cf5be37a9fda348514d5097a662f214687cbfb28ff42d635b13029871ca4f464bb1fbce02d5da4d5fb61b2a071844259fc863d136197bec3a61e7c7
+
+Msg = adb5f069b2b501a3ebb83d4f1808eb07710ac4a7b12532996855a20bcc54b2f76812915f632163c3654ff13d187d007152617cf859200194b59c5e81fc6cc9eb1ceb75d654050f260caa79c265254089270ccd02607fdcf3246119738c496dc3a4bd5d3be15789fc3d29a08d6d921febe2f40aef286d5d4330b07198c7f4588e
+d = 17c3522007a90357ff0bda7d3a36e66df88ca9721fb80e8f63f50255d47ee819068d018f14c6dd7c6ad176f69a4500e6f63caf5cf780531004f85009c69b9c1230c
+Qx = 13a4bea0eed80c66ea973a9d3d4a90b6abbb5dee57d8affaf93390a8783a20982eba644d2e2809f66530adeeee7f9a1da7515447e9ba118999f76f170c375f621f7
+Qy = 12f9dfaee40a75d8442b39b37a5c19ea124b464236e9b9a31bae6780cfd50f7ea4a700154b5ea0feeb64e9b35a1b0e33e46900cca1f34d13bb17e5017769841af27
+k = 18388a49caeda35859ef02702c1fd45ff26991998bd9d5e189c12c36cdae3f642ddd4a79561bd1d3e1cd9359de8f5c9e1604a312d207a27b08a6033f2741794ced5
+R = 15c6264795837dfea19f91876455f564f073c5c84a3c9d76e67872ae0447ba0d4850d8721302b25bec7ebfedd2721de140b2f3dead547042b24b0876117e7093cc1
+S = 060eb74236c189a28ed20bd0822eb22d75f7d97c9043a3c8e3f6d4c90bc8ca02ac4d37c1171c799a1c7dfd2fcbf83406b5e48c051e0fbf0fd937bfe6c3db4e18154
+
+Msg = f253484d121d1ce8a88def6a3e9e78c47f4025ead6f73285bf90647102645b0c32d4d86742a50b8b7a42d5f6156a6faf588212b7dc72c3ffd13973bdba732b554d8bffc57d04f8167aef21ee941ee6ffb6cce0f49445bd707da8deb35dca650aaf761c3aa66a5ebccddd15aee21293f63061a7f4bfc3787c2cd62c806a1a9985
+d = 0c4dad55871d3bd65b016d143ddd7a195cc868b3048c8bbcb1435622036bdb5e0dec7178ca0138c610238e0365968f6ddd191bbfacc91948088044d9966f652ff25
+Qx = 014858a3b9bd426b678fdcf93fc53d17e7a9e8fe022442aaaba65399d12fd3a6a381958fb0f07ac6088f4e490506ec0f1ab4d0dbd461126f7eb46ff69cfa8bd88af
+Qy = 18c18ce29ecc6d79d26a2de0cd31c4b32e84b5e90f6ba748f86c5afbd89618aceb9079460cbd1a8261ed5476973e61bf1d17ea78b022387443800c9247d21dde550
+k = 05577108f4187a173e5c29e927a8fc8f5ffd37e184254a6e381ff1018955aec91a35f30085e8cee6a7555c10f9efdce26d62f2b4b52dfdbaeafc3a30983e2d50d5b
+R = 0344375ae7c804cbe32ced7a20976efae5d9c19eb88b6e24514d1d0cfb728b0f4601098b18b2e98f42b5222dd5237d4d87767007bf5acb185c5526d72047e2cb1a1
+S = 02de4cfa908c73c1102d6fb7062baf54a056a9517701e036c9c51e09899d60051612d59348945f845dffebec5aa395b2fac7229929033615788777306ccad96d0a3
+
+Msg = 33bab1c369c495db1610965bc0b0546a216e8dd00cd0e602a605d40bc8812bbf1ffa67143f896c436b8f7cf0bed308054f1e1ff77f4d0a13c1e831efbd0e2fcfb3eadab9f755f070ba9aeaceb0a5110f2f8b0c1f7b1aa96a7f2d038a1b72e26400819b1f73d925ea4e34d6acaf59d0a461a34ce5d65c9c937a80e844e323a16d
+d = 03d4749fadcc2008f098de70545a669133c548ce0e32eec1276ff531bcff53533144555728ad8906d17f091cc0514571691107350b6561858e90dbe19633aaf31bf
+Qx = 10fe5986b65f6e65d13c88c4d2aed781a91026904f82129d46779bdadaf6b733c845a934e941ab4a285efdea9c96ecc9dc784d87e4d937b42c337b3a9cb111a9600
+Qy = 077853768a2a4d6f596f57414e57ec60b76d3cd5ece8351cd1f335ebcb8801a3d91fb82c65caaeb5c31eea9918367bb5906863ff3ccaf7a6cee415e0d75c15ac2e0
+k = 1fbb4de337b09e935a6dc6215ffcfcb85d236cc490585e73251a8b8bac37cfa36c5d1df5f4536d33659be1e7a442529a783452f7efda74a4f661b6a127f9248aaf7
+R = 09d8f10eeff6178594c89d6e8184f9502117384813243ddf9ccf3c8eac5dc6502c472dfc1487a5caffc569f7dedd14a8ebcb310e9bacdb79fb6655aba026cdf87f2
+S = 0f74236c7915d638708d17c9f10e39dda358faf9bbb821d8dcda0d151aac143bfb165ad0a23a65cd3de532e32cad928728f5ae1c16f58fc16577f3ca8e36f9e708b
+
+Msg = 08c8b7faaac8e1154042d162dca1df0f66e0001b3c5ecf49b6a4334ce4e8a754a1a8e4daf8ec09cf1e521c96547aed5172ef852e82c03cddd851a9f992183ac5199594f288dbcc53a9bb6128561ff3236a7b4b0dce8eaf7d45e64e782955ee1b690ce6a73ece47dc4409b690de6b7928cbe60c42fc6a5ddf1d729faf1cc3885e
+d = 096a77b591bba65023ba92f8a51029725b555caf6eff129879d28f6400e760439d6e69ce662f6f1aecf3869f7b6057b530a3c6ff8ed9e86d5944f583ee0b3fbb570
+Qx = 0fdf6aed933dba73913142ef8bdcd4b760db8500831cd11d7707ab852a6372c05d112a1e7fbc7b514c42142c7370d9f4129493cd75cc6f2daf83747078f15229db6
+Qy = 0ef91dffb3c43080a59534b95ca585ee87f6145f6a0199b2b82c89f456d8bd8e6ac71c78039c08177184484eb2ebd372f189db3a58fab961a75a18afec1ee32764a
+k = 13aa7b0471317a2a139c2f90df1c40d75e5a8a830fbaf87030fffdb2ef6f2c93d1310c9ed7fe9d7bcd4fe46537ff2495bc9c4f0aaff11461f5e4bebbfbce9a8740a
+R = 1c7a21800962c91d4651553633b18612d931bb88bff8b743ed595b4e869437e50f8e84fbf334c99061db123a1c40b73b07e203790561a37df65a660355ba2017d78
+S = 1301e1782559a38f1ca0eebe9bed0f5c7c33103d506a24f8a688f500ee1fe37f97b6685319279e82e6fe43cfd823ccbc123309974cffa76c4f8d41ec02a3cbc45f1
+
+Msg = ba74eed74282811631bd2069e862381e4e2a1e4e9a357b1c159a9ce69786f864b60fe90eeb32d8b72b099986fc594965a33285f7185b415df58fead7b8b50fc60d073680881d7435609ad1d22fd21e789b6730e232b0d2e888889fb82d6ad0337ab909308676164d4f47df44b21190eca8ba0f94995e60ad9bb02938461eee61
+d = 015152382bfd4f7932a8668026e705e9e73daa8bade21e80ea62cf91bd2448ebc4487b508ca2bdaaf072e3706ba87252d64761c6885a65dcafa64c5573c224ae9e6
+Qx = 00b8c7c0186a77dc6e9addd2018188a6a40c3e2ba396f30bbd9293dba2841d57d60866b37f587432719b544d8bf7eb06d90a8c0dc9c93b0c53d53b2f667077228ca
+Qy = 1dd2e5c73ab908ae34f701689f1cd3cf5186d3a2bc941e208bf3ef970e5e429ee9b154d73286b2e5da423e75b7c7b78c7bdf915da92279db43265a0cdefca51f86a
+k = 0d03506999f5cc9ec3304072984a20a9c64a22ad9b418495ca904f4bbddc96e76d34672cb52763339d3f3bc5b1701c00a675b972797e3a086314da1a8d338436566
+R = 085406c0ff5ec91f598bb579ad8714ad718c3e133d5dcc2e67c5d2339c146b69919cac07f3bc2bda218f4c7c8be04855e2ca6fff7fbdc4fc0fda87c8c3081cad4f5
+S = 1b45f2066e583636215ae135afc202b8bf3f301eccff2e1c0198b9aeddf695fa8179488e7b622fc307f601e2f6551815117cc836bb09ef888f8e64a45d9c84ad30c
+
+Msg = dc71f171a28bdc30968c39f08f999b88dc04c550e261ecf1124d67f05edeae7e87fe9b8135a96fe2bc3996a4f47213d9d191184a76bd6310e1ee5cb67ea7fc3ef6f641a0ba165198040fa668192b75a4754fc02c224bd4a74aade5a8c814adf151c2bfeda65165a04ef359e39847c84e312afb66d4cd1db50d41ef3fe5f31296
+d = 1750ff0ca0c166560b2034bc5760fe0b3915340bc43216e9de0c1d4a76550e8b2036e8b874230f8d29354aed43e183610f24fd4abd4b0be2f111dae942bd7a121f7
+Qx = 1b4b8947192a7c0166c0e0b2791e217370836283e805f3ee11cfb78445aba3c5bc39fe594e01916617ad59e7c8e740d8f2d07d88905d3f33bd5e51aafd4943c5dc6
+Qy = 1175d117232836c28e717ce2a55e59f4ec550effde30d18e3d99e42c6aa2283c7b3e7f2f6ff1fca605dde78c3a5bffa689347b4c93f51ba59a1787bb7d5e43861dc
+k = 023645023d6bdf20652cdce1185c4ef225c66d54f18632d99ccf743bf554d04c214c88ce52a4f71ec75c899ad1b3c07c34112ca20b55c217ff1d72c9528e2774ce8
+R = 1e933f68ce0f8403cb16822b8e0564b1d39a35f27b53e4ae0bcdff3e051759464afbc34998ba7c8a7ee34ef6c1aaa722cffe48356fd0b738058358d4c768b3186c1
+S = 0a67368a305508ce6d25d29c84f552a4a513998990fef4936244f891a2909c30d5fdc9e8a267ecbf3c597138f4a08f7e92bee57d5420eadd700fee864bf78b2614b
+
+Msg = b895788d7828aaeace4f6b61a072ffa344d8ea324962ba6dab5efda93f65bf64a0f2ac6d5721d03ee70e2aef21cdba69fd29040199160e3a293b772ffb961ed694a8dc82800dab79367a4809a864e4aff6bc837aaa868e952b771b76591c0bb82249034e3208e593d85973d3fea753a95b16e221b2561644535c0131fe834ae7
+d = 023048bc16e00e58c4a4c7cc62ee80ea57f745bda35715510ed0fc29f62359ff60b0cf85b673383b87a6e1a792d93ab8549281515850fa24d6a2d93a20a2fff3d6e
+Qx = 0ba3dc98326a15999351a2ec6c59e221d7d9e7ee7152a6f71686c9797f3f330d3150123620d547813ba9d7cc6c6d35cc9a087d07dff780e4821e74ad05f3762efd6
+Qy = 18b051af9824b5f614d23ecadd591e38edbfe910ad6cbebc3e8a6bec11ea90691c17deb3bc5f34a4a3acd90b7b10f521f6ee7b3cfbfdc03b72d5a8783a4a77c3e4c
+k = 06099d2667f06c58798757632d07d8b3efbe9c1323efb0c244be6b12b3b163ba1b7cf5246c98dcc0771665a66696d687af5f28ed664fd87d5093df6427523d4db84
+R = 10dc80ea853064a2ba5a781f108aca3785c5ec0aa45aa05ba31d4de671170797589e863d54a3a986aadf6f670277f50355713dfb27d4ec7e348f787910b3cd668cd
+S = 018572bfad4f62e3694d1f2e6ffd432faed2e2b9d7e3611a07138212f1e79e6c394839f7cfae96bc368422630016fb9346681eadc5f9699e7331c3b5fde6d65e4c6
+
+Msg = 2c5bd848c476e34b427cfe5676692e588e1957957db7b5704492bd02104a38216535607f5d092dc40020130c04a3aaf0f1c52409834926d69a05d3f3188187a71d402a10ba34eac8629b4c6359b1095f30f710219298bf06b9f19bfc299981d7e251ca232a0a85338a7e02464731d1b25d4a1f68baf97064516590644820c998
+d = 02b8b866ce4503bb40ffc2c3c990465c72473f901d6ebe6a119ca49fcec8221b3b4fa7ec4e8e9a10dbd90c739065ad6a3a0dd98d1d6f6dcb0720f25a99357a40938
+Qx = 1b8c7a169d5455f16bfe5df1ba5d6ec9c76e4bad9968d4f5f96be5878a7b6f71d74bfac0076dd278bc4630629f3294646f17d6b6c712b0087e2c4d576039cfdc8b9
+Qy = 18faffd5422dfd1b61432fa77b9a288b2b7d546656c0dcca3032179e6f45ee3cf61d6a447fc51731cb54457343a41569fcf78cef42895f4da5efcb14ea1fc065f8d
+k = 0ac89e813f94042292aa1e77c73773c85cf881a9343b3f50711f13fa17b50f4e5cb04ac5f6fc3106a6ef4c9732016c4e08e301eefac19199459129a41a7589e0628
+R = 05bc7a253a028ee8b7253979b8d689d41d8df6fae7736341f22e28b6faf0cbbdebbd2ef4d73e56d2021af2c646dc15539a7c1e1c4dc9c7674808bd7968d8a66f947
+S = 0fd71575837a43a4cf1c47d0485cfd503c2cf36ebcea0fdef946ad29acb7fb2e7c6daf6b4eb741eb211081aed6207d02569f1518988f275ad94c7fd4735cb18a92e
+
+Msg = 65a0b97048067a0c9040acbb5d7f6e2e6ac462e1e0064a8ce5b5bbf8e57059e25a3ef8c80fc9037ae08f63e63f5bdb9378c322ad9b2daf839fad7a75b1027abb6f70f110247da7e971c7c52914e5a4f7761854432fa16b2a521e7bcaee2c735a87cad20c535bf6d04a87340c229bf9af8647eedca9e2dc0b5aa90f7fea3cdc0a
+d = 0a43b32ad7327ec92c0a67279f417c8ada6f40d6282fe79d6dc23b8702147a31162e646291e8df460d39d7cdbdd7b2e7c6c89509b7ed3071b68d4a518ba48e63662
+Qx = 172fb25a3e22c2a88975d7a814f3e02d5bb74cfb0aaa082c5af580019b429fddd8c7f9e09b6938f62e8c31019b25571aaceef3c0d479079db9a9b533ee8e1670abd
+Qy = 0ff5516223b6cc7c711705f15b91db559014e96d3839249c5c849f2aced228a8998177a1e91177abbb24b57a8ea84d944e0c95da860ae0925f1b40c0e1b7c9e0a46
+k = 0383eda042e06c0297fbd279a2ad40559c5c12ad458f73458eebcc92b308d3c4fcec20a5b59f698e16fa6ea02dba8661b6955f67c052f67b0a56460869f24cfdf7d
+R = 1b9c35356b9d068f33aa22a61370dae44a6cb030497a34fb52af23c6b684677370268f06bb4433be6795a71de570088aec17ce0c9933d2f76c7edce7f406f62fedd
+S = 06f07ea453cfa20ad604ba855332f62834657b0b795684d50c1562a675456e37f4dae45f0df47d8e27e47bc9ce9c9cbba1554c5b94b0b17401b73c8d0c0902c6cc4
+
+Msg = d6e366a87808eea5d39fe77cac4b8c754e865a796062e2ec89f72165cd41fe04c48148068c570e0d29afe9011e7e7a2461f4d9897d8c1fa14b4ff88cab40059d17ab724f4039244e97fcecb07f9ffeec2fb9d6b1896700fe374104a8c44af01a10e93b268d25367bf2bef488b8abcc1ef0e14c3e6e1621b2d58753f21e28b86f
+d = 03c08fdccb089faee91dac3f56f556654a153cebb32f238488d925afd4c7027707118a372f2a2db132516e12ec25f1664953f123ac2ac8f12e0dcbbb61ff40fb721
+Qx = 193301fc0791996ca29e2350723bd9aa0991ddbb4a78348ee72bdcd9ed63ce110ba3496f2ce0331b5c00d4d674c1b70114e17ce44a73c3e16bab14ed1ee924202e4
+Qy = 0aea9b288cfb2933ec0a40efa8e2108774e09b3863b3193d0dac6cc16ccaa5bd5f9ce133aec5cd3b62cbaeec04703e4b61b19572705db38cfaa1907c3d7c785b0cd
+k = 0d0e90d5ee7b5036655ad5c8f6a112c4b21c9449ca91c5c78421e364a2160bbac4428303657bc11ea69f59fb0fe85a41b8f155a362343094456fd2a39f2a79e4804
+R = 1a8c23a2965d365a4c2ffd0802ae8b3a69c6b84a1ba77fd8a5f2f61e8ec3a1dcb336f136e2a997252eaa94caf9b5ad6c9ecff5bf33abf547ca84985bb89908a11d7
+S = 1cc42a2dd97aa42b9df5ea430e0d4cb13106dd6da6e8c9315c96ed7b052db365bbde6960c9a965954a4398c18ea7db9593bbfc3c3b6b3466ff806fccac3de6424ab
+
+Msg = f99e1d272d0f5fb9c4f986e873d070ec638422bc04b47c715595e2cf1a701cdf88bc6c4b20085b357bad12ccba67cac8a5ca07f31ba432f9154ff1fadefd487a83a9c37e49fb70a2f170e58889cab0552e0a3806ccfa2a60d96e346851d84b7de6d1a4b8cf37567dc161a84f13421e3412457d4bc27f6213453c8519a2d7daa2
+d = 0969b515f356f8bb605ee131e80e8831e340902f3c6257270f7dedb2ba9d876a2ae55b4a17f5d9acd46c1b26366c7e4e4e90a0ee5cff69ed9b278e5b1156a435f7e
+Qx = 0fc7ae62b05ed6c34077cbcbb869629528a1656e2e6d403884e79a21f5f612e91fc83c3a8ac1478d58852f0e8ba120d5855983afd1a719949afa8a21aec407516c3
+Qy = 0aa705da6459a90eaa2c057f2e6614fb72fc730d6fdebe70e968c93dbc9858534768ea2666553cd01db132331441823950a17e8d2345a3cab039c22b21bfe7bd3b9
+k = 19029260f88e19360b70c11107a92f06faa64524cfbd9f70fecf02bd5a94f390582a7f4c92c5313bb91dc881596768d86f75a0d6f452094adbe11d6643d1a0b2135
+R = 07f2158e9b9fa995199608263969498923cf918fdc736427c72ce27ce4a3540dce2e8e5e63a8fc7ba46f7fa42480efbf79c6ed39521f6e6ec056079e453e80a89d9
+S = 08e349eed6f1e28b0dbf0a8aeb1d67e59a95b54a699f083db885f50d702f3c6a4069591afaa5b80b3c75efb1674ebd32c7ead0040d115945f9a52ee3a51806cad45
+
+Msg = 91f1ca8ce6681f4e1f117b918ae787a888798a9df3afc9d0e922f51cdd6e7f7e55da996f7e3615f1d41e4292479859a44fa18a5a006662610f1aaa2884f843c2e73d441753e0ead51dffc366250616c706f07128940dd6312ff3eda6f0e2b4e441b3d74c592b97d9cd910f979d7f39767b379e7f36a7519f2a4a251ef5e8aae1
+d = 013be0bf0cb060dbba02e90e43c6ba6022f201de35160192d33574a67f3f79df969d3ae87850071aac346b5f386fc645ed1977bea2e8446e0c5890784e369124418
+Qx = 167d8b8308259c730931db828a5f69697ec0773a79bdedbaaf15114a4937011c5ae36ab0503957373fee6b1c4650f91a3b0c92c2d604a3559dd2e856a9a84f551d9
+Qy = 19d2c1346aadaa3090b5981f5353243300a4ff0ab961c4ee530f4133fe85e6aab5bad42e747eee0298c2b8051c8be7049109ad3e1b572dda1cac4a03010f99f206e
+k = 1a363a344996aac9a3ac040066a65856edfb36f10bb687d4821a2e0299b329c6b60e3547dde03bdbd1afa98b0b75d79cf5aac0ef7a3116266cadf3dfbd46f8a4bfc
+R = 1ff097485faf32ce9e0c557ee064587c12c4834e7f0988cf181d07ba9ee15ae85a8208b61850080fc4bbedbd82536181d43973459f0d696ac5e6b8f2330b179d180
+S = 0306dc3c382af13c99d44db7a84ed813c8719c6ed3bbe751ead0d487b5a4aa018129862b7d282cce0bc2059a56d7722f4b226f9deb85da12d5b40648bf6ec568128
+
+[P-521,SHA-384]
+
+Msg = dbc094402c5b559d53168c6f0c550d827499c6fb2186ae2db15b89b4e6f46220386d6f01bebde91b6ceb3ec7b4696e2cbfd14894dd0b7d656d23396ce920044f9ca514bf115cf98ecaa55b950a9e49365c2f3a05be5020e93db92c37437513044973e792af814d0ffad2c8ecc89ae4b35ccb19318f0b988a7d33ec5a4fe85dfe
+d = 095976d387d814e68aeb09abecdbf4228db7232cd3229569ade537f33e07ed0da0abdee84ab057c9a00049f45250e2719d1ecaccf91c0e6fcdd4016b75bdd98a950
+Qx = 13b4ab7bc1ddf7fd74ca6f75ac560c94169f435361e74eba1f8e759ac70ab3af138d8807aca3d8e73b5c2eb787f6dcca2718122bd94f08943a686b115d869d3f406
+Qy = 0f293c1d627b44e7954d0546270665888144a94d437679d074787959d0d944d8223b9d4b5d068b4fbbd1176a004b476810475cd2a200b83eccd226d08b444a71e71
+k = 0a8d90686bd1104627836afe698effe22c51aa3b651737a940f2b0f9cd72c594575e550adb142e467a3f631f4429514df8296d8f5144df86faa9e3a8f13939ad5b3
+R = 02128f77df66d16a604ffcd1a515e039d49bf6b91a215b814b2a1c88d32039521fbd142f717817b838450229025670d99c1fd5ab18bd965f093cae7accff0675aae
+S = 008dc65a243700a84619dce14e44ea8557e36631db1a55de15865497dbfd66e76a7471f78e510c04e613ced332aa563432a1017da8b81c146059ccc7930153103a6
+
+Msg = 114187efd1f6d6c46473fed0c1922987c79be2144439c6f61183caf2045bfb419f8cddc82267d14540624975f27232117729ccfeacccc7ecd5b71473c69d128152931865a60e6a104b67afe5ed443bdbcdc45372f1a85012bbc4614d4c0c534aacd9ab78664dda9b1f1e255878e8ac59e23c56a686f567e4b15c66f0e7c0931e
+d = 04ceb9896da32f2df630580de979515d698fbf1dd96bea889b98fc0efd0751ed35e6bcf75bc5d99172b0960ffd3d8b683fbffd4174b379fbdecd7b138bb9025574b
+Qx = 0e7a3d30d5bd443549d50e9b297aaa87bc80b5c9e94169602d9d43d6d0c490c0bed8cc2170288b106bdbf4c9f1ce53fd699af0b4c64b494b08520e57dc01ab9a8b0
+Qy = 1d81056d37aec8a75d588f6d05977416e6f24ad0117a7f4450036d695612e7bc2771caed80e580314eebc88c8fc51c453f066e752481f212b57165d67f8a44f375a
+k = 046639c5a3ec15afae5e4a7a418ac760846512d880c359bc2c751b199ce43b10887e861b14127809754dbea47f6cc0140d2817e3f5b9a80ce01abd81f81b748433a
+R = 0f913de91e19bd8f943d542ae357bacc942a0967abc9be6c06239a379db8cc733fa50013e0b0f088bce9d630262feaa33b30d84f91bcf5ce9976e4e740fcb112f84
+S = 08a73a5c9c24235e0d9cecaac653f68ce5a6fb186ce67fa058d6ddbbd4d0a8c4d194e571148e8ad6c8882b4e33d2f60fb23dd7d07a1ae60864e8277918f592b3dc6
+
+Msg = 6744b69fc2420fe00f2352399bd58719e4ecdd6d602e2c80f194d607e58b27a0854745bfd6d504de2eb30b04cee0f44af710dd77e2f816ac3ac5692fad2d1d417893bb0edba2707a4c146a486f8728ca696d35cc52e9c7187c82d4bdb92eb954794e5ad15133f6bfea1f025da32ada710a3014cf11095b3ff69a94d087f17753
+d = 00a8db566bd771a9689ea5188c63d586b9c8b576dbe74c06d618576f61365e90b843d00347fdd084fec4ba229fe671ccdd5d9a3afee821a84af9560cd455ed72e8f
+Qx = 04f5b790cbe2984b71d41af5efed6c6893d15e13f31816d55a9c2926a104eee66f1ada83115d1388551218773b8b9d1138e3e3f027bb4392c90c14fd232580b4a11
+Qy = 0660eb160e9bfc8c5619e70e948e238c6fd37739bc1bb657b8e8436e63628f91992be7e63d9a7359623a1340642777b22026feb51116a6c50c54c3589b9bd39b6cb
+k = 1e7b5e53571a24bd102dd7ad44a4b8d8a4e60e5957bc3c4e5d3c73109f55233f072e572c7892f425ba5e64d3cb7966096bb34a47e26cd5b3e3b44108b310d9f681b
+R = 1a88bcd7e2bdff6e497d943dde432fb3f855a7177c466319cb53b701230c299db030276269685857d1e3f28110e690f2f529c8d18115eb381f313bc891d92ad278e
+S = 146f1984ea879274dfd5e86ad92e564a4de081523ddbb1c397b8f9595911ef2e6501bc081584d5340f7aa47e1af036234ac6f27a5ac31f78dd3b0ff1a62693c630d
+
+Msg = 16001f4dcf9e76aa134b12b867f252735144e523e40fba9b4811b07448a24ef4ccf3e81fe9d7f8097ae1d216a51b6eefc83880885e5b14a5eeee025c4232319c4b8bce26807d1b386ad6a964deb3bdca30ee196cfdd717facfad5c77d9b1d05fdd96875e9675e85029ecbf4f94c524624746b7c42870c14a9a1454acf3354474
+d = 1a300b8bf028449344d0e736145d9dd7c4075a783cb749e1ec7988d60440a07021a25a3de74ea5e3d7bd4ab774d8ad6163adae31877ef0b2bd50e26e9e4be8a7b66
+Qx = 05055b9ad726ba8a48219b0ecbfffb89f8428de895b231f676705b7de9f2022d9ff4e0114ebb52dea342f9bf76b2fb060c020e29d92074ebb1fbfe5290a58c8bc10
+Qy = 0415af7f20a6e945315adbf757316bb486c80780a0a3a15b4b9609f126d7341053a2b726ab63cb46feee527b0bf532b32b477e5671aea23d9b3c3e604b9029954b5
+k = 05a2e92717bb4dab3ee76724d4d9c2d58a32b873e491e36127985f0c9960c610962ca1c4510dba75c98d83beebdc58b1d8678e054640951d11db1bd2d8a4ab8476b
+R = 104a78ce94f878822daaf00ee527fbdbf6cceb3cbb23a2caa485e4109466de8910252f92379ab292cac8d1eda164f880c0067696e733fc8588a27703a3e1f5b8f1f
+S = 1ffe23e8ab5a31668a81161a234ea14879771fe9866f8872eb6edb672e0fe91d2bb75c9767a2dfbac7c15c802211236b22ea41ecd055a0b8b311ffc4255f86d5c67
+
+Msg = a9824a7b810aa16690083a00d422842971baf400c3563baa789c5653fc13416111c0236c67c68e95a13cec0df50324dcc9ae780ce4232607cb57dd9b2c61b382f0fa51fd4e283e2c55ffe272597651659fbd88cd03bfa9652cd54b01a7034c83a602709879e1325c77969bebfd93932ce09a23eae607374602201614ff84b141
+d = 06a253acd79912a74270fc0703ed6507ab20a970f2bc2277f782062092cf0e60ae1ca1bb44dec003169bc25ef6e7123dd04692f77b181a6d7e692e66b09d35a540c
+Qx = 1f15c6b1df156fdd8381cd7446e039435e445f8f36f0247475058da0e371bf72753f6e39f98066bc79370b038c39687ba18e16cb118fe6538b7568c5403c251f6b7
+Qy = 12d2b4f46b854eeae75f1c63f55b76bf0c604d47f870c28a50ecdeb52bba1dd9a0ff12e680804ff864111207652da7dd10b49edf66bb86be00bc06672de91982457
+k = 165faf3727e42fd61345cfa7b93e55fb4bf583b24bdc14ce635b6c99dbd788012f14da9a210b677c44acdd851e672f1a48188d6b8946c0efeebfe8a597ba0090a2c
+R = 1ad9463d2759abd568626548578deefdcd8b2d050ce6d9c7ed05feca20167484b86e89bdcc936fd647e0f8aedd7b6add2b8cf13ff6ff013c2b5540c6c56fda97a0c
+S = 1645a7d0e11015256cfb034adca198695eea6aedd44d9fbf496850ccfed950f43fffd8dbf41e113f2d3837d8a5dd62b2ed580112ff05800b1f73196e5576810e15b
+
+Msg = 90d8bbf714fd2120d2144022bf29520842d9fbd2dc8bb734b3e892ba0285c6a342d6e1e37cc11a62083566e45b039cc65506d20a7d8b51d763d25f0d9eaf3d38601af612c5798a8a2c712d968592b6ed689b88bbab95259ad34da26af9dda80f2f8a02960370bdb7e7595c0a4fffb465d7ad0c4665b5ec0e7d50c6a8238c7f53
+d = 0d5a5d3ddfd2170f9d2653b91967efc8a5157f8720d740dd974e272aab000cc1a4e6c630348754ab923cafb5056fc584b3706628051c557fce67744ee58ba7a56d0
+Qx = 128a4da5fc995678e457ceb3929adee93c280f851abe900fa21f4f809dafad4e33b381e0cd49ce8dd50e2e281cea162bfd60a1d6a1c0ee2228e6a011e171b559ab8
+Qy = 06eb0917cd72256992c49ea527f6bb0315f13d8047794a0f1da1e93737703b1c2a74a00441ef3b47b6a2ff789c49ae32d91cabe7b29247aeec44f6c40a76597a2ca
+k = 03269983a5c2bcc98e9476f5abf82424566b1f08b17204d29e310ece88f99eb677a537f86fe2529e409cfef2c12929644100099e0de2f27c0f0ac11105a4dca935b
+R = 1a5257ae1e8187ba954f535b86ff9b8d6a181a3b95c250d090cb4e9c3bfbd03aa64696a76c569728ef67780d6338d70ce46da40b87a3e49bfe154b93930890dfa93
+S = 05b6ccdfd5c63c7db76d3a0478064a2a376e0e050cb093be795a72a549247c2e4adba9183145c63d46479dbbdcf09986a6f64c09c7e16abc4853f6376c9558b014a
+
+Msg = 09952b1e09995e95bf0022e911c6ab1a463b0a1fdd0eec69117b34af1103c720b57600217de7cd178fef92de5391e550af72a8dcf7badf25b06dd039417f9a7d0f5be88fcd4e9655931d5b605452a667c9d1bae91d3476e7d51cff4108f116a49966fb3a7cff8df1c09734ce5620faf2dccb3dc5d94e7e9ac812da31f6d07a38
+d = 1bcedf920fa148361671b43c64e3186e1937eb1bd4b28cbd84c421472394552889bc05509aa732ef69d732b21b750523fdfd811f36467690fe94e01e64c9d5cbbe9
+Qx = 0d33c151d202a5d4d831348e940b027ee32e4b0b9b48d823a05c67ff3bdaee0189fc6680565f352c062e99968afc643208b4f9c7af185b861658a88c4ad0fcc8ba2
+Qy = 0e4441ddb546468ad8ffa6074f137edfbb81e82e0e7d8f05c4c54598aa996a9cde54cb371f642bfdd4ae7eca5b769696030027129a4183da93567ad142a2dff5183
+k = 046e619b83aac868b26d0b3cbfab55e630e0b55c461985b5d00f94ff3a5ce90ff412cebf46bbd84550d2031d573ca27d924624428360708c8d8491c29eb01d30f2e
+R = 08427c0f0ac0263472cd423c0fb554bf3c851b9c775c566ab0f6878717bd57665830767b05b7789c5c0b078195bd943dc737325552d32877ecb04a7c41bd07cd80c
+S = 10bb6652d6a624c40a7dd06828f15774130d02369ceb1a7d03b553e16e17b7fa5b5401f15885d5e4fc2e55c0c7a1b97871ab02f76386b93a16aa6e7eb65debac6dd
+
+Msg = 0bb0f80cff309c65ff7729c59c517d50fc0ed5be405ef70cb910c3f62c328c90853d4473530b654dda6156e149bc2222a8a7f9be665240e2fbe9d03f78a2356af0bacd1edb84c4801adc8293a8a0bd6123d1cf6ba216aca807a7eb4dca76b493eb6e3dbb69d36f0f00f856222f24d9b93ec34c3b261be2fca0451c00571928e5
+d = 03789e04b3a2a0254ade3380172c150d2fad033885e02ea8bea5b92db3f4adbab190ae423080a1154dfedec694c25eab46ce638be3db4e4cba67bc39f62d6e7db2d
+Qx = 1dbc2cf19627bdccf02432b1761f296275230c150cdde823ce3141ec315d7d05e16b2c29e2a67491078d5316883e933d85b4b10d4f64c477d3c4e0442dc928983a2
+Qy = 07562e720807dd118d3d8b265b3abc61a71fce43e3dce0e7b5ae18b7a4cb01ecc00d39c1f22e150a9a8728997e502144f5b3f6fa9b4cb8a4136212b082ca394e3f6
+k = 0fbccd8d7804bdd1d1d721b5ec74d4ba37603bc306f9fce2ec241853d8e07334e6b4b12c4ecca0c54bd71193dd7146507933a20737c5f3e15085830fab9b30ca57b
+R = 181915a3998d8fa214f9715f4ca928d09c36de168dc15c6970a8a062b5cea2dc969b2437ca17b684f78a1fd583aad8e6c762c8f4ab0c91b86a497145e3ca440d307
+S = 15a6c18c5c77f5470b27d061eafdc26b78561941a3b2ab0f5c81d40899fc053c3d9ed12d7d61e298abbae470009c7b2157731c58d7b16a66fa5abaf5e8a1b8ed394
+
+Msg = 7efacf213382ce30804e78b7256854d759147dba9729c51b2759465715bf2c421034c23dc651c13d6cce95f71fe6a84dfbee5768163ac5789ac0474c5ddf4115684683c5f7c204b33b8bcc0c03ac58f66cef2f53b721fe2fac91ad841126101a88f512a7c2ded38549d9f050d4b7961dda48a1489f026c5d111701762418cfe3
+d = 124700aa9186353e298edefc57bec0c7d0201cca10c1d80dd408d5d71040592b0ac59facdadfa8712445f5977ef8d4854022720c3f02d60e0732dbb2f171fcf1490
+Qx = 0c80fc4cecae5d53348524ddba6a160b735c75b22fdb39af17e2a613d09246e3bb0fd3f2978577f6db5d2118e05c7898024808f8eb8e021d7969cdcf7fc981200bb
+Qy = 1a880c93943fd446d4b3923b574d2221c1bb7b645fb5534dda60e827b497666ff586b77921f7e7f605147947194cffd2fef0678880b89cc0bc7fb74fa96d4b112d7
+k = 01a05238d595ded5c61d3bf6fde257dbf13095af8a5cb3a2e579e8e4c550fe31d12b71cc2dbcb295e6c4fd0fb8c22d1b741c097cc59d826ced1a8771f09983143c4
+R = 132762bc81e9922a8d642e3a9d0218affa21fa2331cfcb9e452545c5981c64a8f7e4cc8e68056023b2aa78bead59061d19c7f646c931163a91e544b106b3be8de9e
+S = 0c3a1b0b000c3169984132add51d611e2cb7069a262a6983d2ae72b459c36e6469509bdb0f473600b8686700b08910779dee9ba83f82e755d4a4ef5f124eb09397f
+
+Msg = 28edff8b9d85f5f58499cc11f492abdfab25e8945975bbaeee910afa2b8fc1295ec61406309ce4e09f4ab4f462959fc2a2786802466eb26d3b01be6919893ae75d0fdc2dc8a82e662550f9fce9627dd364188aaba5c6faa1b2d8a2235adfa5ad0dc140f88a2b2f103f5690e877d07fe8fd30d02d2b2729bd3d8eb5b23a21f54c
+d = 1f532d01af885cb4ad5c329ca5d421c5c021883bd5404c798d617679bb8b094cbb7e15c832fb436325c5302313ce5e496f9513455e7021ffad75777a19b226acfa1
+Qx = 0c0bd76b0027b85bdd879052220da1494d503f6a4bb972105a48ae98e7dda8c2d9fd9336f5646385b961ef68e8464e3a95b00f96614b1a408ceaa2c87b077b6a8fb
+Qy = 17eb7eb5c78db7819af92e8537d110d9f05a5e24f954f4dde21c224d4040f059ec99e051702f390413d2708d18f84d82998c61847475250fb844b20082cbe651a6b
+k = 14e66853e0f7cd3300ebcae06048532e19cbb95bee140edc1c867ce7310637651445b6dfeb1d99d2e32f2ffb787ebe3fe35032277f185d3dad84f95806924550abe
+R = 0c5b3a57161098e2e8e16e0a5ae8ecf4a14df14927eea18ed4925d11dc429dda145159323ba970174b194b9b4608a8fa2373b7a825c5e8bd80574e49698285c2c82
+S = 1a0c038a51796158b42eb5b0dac37aff9ab93b903a47e06ebbdd15946e4bcc9a3b3875b18cf6294c33fc6c3693cef04ed1a43d08951e664c760e2cf3fb4e47490d2
+
+Msg = bae2a8897c742fd99fbf813351cd009d3f2e18d825ca22e115276484bce8f82f8c7c0c21dd2af208404d8ef45bb5a6c41693912b630897d5246801bf0775aa9bbac8be98cb861d172c3563dc59e78a58ed13c66dea496471b3ad0eeae8995293e4ab97373edc1837ffc95ff1cc0c1e90e64ea8680b2ca5f1e09bf86b99b343b6
+d = 11abf508bca68a85a54bc0659e77efad3c86112c9db04db2883e76144aa446918bb4bb0784b0b6a0e9aa47399fe3de5aaecfd8894a0d130bb0c366c40d9d5050745
+Qx = 05c0ea363a3a12633ea39d564587ebdd3a22a175ef32b9ebfc7311304b19cb3a62b5adc36f6afb6a6f7fabbf810ee89fdb72854fefd613e7798e9b9ff5938ea54c6
+Qy = 0bd06a85e47b885c08124b55a3fcc07ca61647cda6efbfdbd21b24d1ea7a4c7300d46cd798e76063aa979adef6f0698b15e5b7ae8a2ab39ab4f50b2d20614db6317
+k = 19cadb8c7eb10565aa4567e0709873918720f0e4b42b4817afb0b0547c70cd1100229deae97a276b9c98ea58b01d4839fee86336d749d123b03e8b1a31166acc110
+R = 0667448a8bbef1c810d40646977dc22f3dfb52a4d80928ded5e976e199cbed02fbd5a08546756ece14548d721a6eb380d0e1a71ad0660dbcac6163c776eedd3e249
+S = 0ae7f0a238daaddb7fb4a1707fe5132daf653f8e19f732347134c96f1dd798f867c479a4a4609a568a15b61afed70790adbde13ac5f68c468d0230852c1a2c22581
+
+Msg = d57a26a9593e72bfc87322524639bcaae5f2252d18b99cdaa03b14445b0b8a4dd53928f66a2e4f202fb25b19cad0eb2f1bfda2ab9b0eb668cdcd0fe72f5d9ef2e45e0218590f7ab9d2c9342202610c698bc786cce108a7d4a6730a13e9ea1b470e781f1237d3f84f44abde808516975546bd89075ef9a9732bfd7ee33b6f4399
+d = 18dbf520d58177e4b7a0627674d220137983f486dd2fd3639f19751804e80df0655db6afd829cdf75238de525e1a7a9f048049b593dd64b4b96cc013f970c05ea1f
+Qx = 18b872690c37995be324ddb5c2bd5462841bb062f8e63da248a853de79c3d6bb9a2eb1e6933afda0998ca43491cc807b08ace2d5336a43d0ab50563a2d3d98755f0
+Qy = 002ff31221aa32aa6546f35e8fe5b9361f938362a5e89e77ae130ba8bce3729e912dfac35a2fd21efe84b45b8be2a340850e4b574e1885b35c2afbe196b57c6cf4c
+k = 098faeb73054639cb2e4442cd68e7b3a13f4b3f397a7b26f303afa40789f8ddd3d918f1ce4f0be53c8cb69c380744e2297d7fc01e2b3daef4ce64dd3a2644234753
+R = 09c0e7649f814f70a8416cb78bc4601472a363fe97f5c587305778169677860dd97f87b5ab07c3a953bc4615fc34634509d6a25621bdded33ed42446d059509c190
+S = 120b90e1cfb8a1b5e530df7b17d1128bc051ca4f1a65dd9c9d9d3c59d2f00c7c1e994c52b8671d40294b4d574d2c04475d5bebeacd3a0d3870a54dc7a4805614f40
+
+Msg = 8fdcf5084b12cfc043dd3416b46274e021bbed95d341d3c500c102a5609d3a34de29f8fa9f0adb611a1f47a97ad981f8129d718fc0d6c709eab1a3490db8d550f34eb905b9e00663543afc5bc155e368e0bc919a8b8c9fa42093603537a5614927efa6be819ed42ececbf1a80a61e6e0a7f9b5bc43b9238e62d5df0571fea152
+d = 002764f5696aa813cd55d30948585f86288ae05aeb264ca157cd09e1d09a10515a849b0791b755ccc656a34707be9e52f5762d290a7d2bcd6de52c600ff862eaf4e
+Qx = 127279c88719dc614db387f102e55104ea1c704ac7f57f3bca936f728439b76556730dd7cde2ac1ad0a4c2c2f036ab6f00cf34cb87ea36113571f300713044106d2
+Qy = 134a0786c31f5f2291b83c50fb579ae4c620b95e5a8bdc0c7e1ee6b996c89d764f1b20403e7faa203f397425ada297045dd8ba0e4b155d4900da249e934faab7991
+k = 08bffb0778cbb06466cecc114b9e89ca243a2b2b5e2597db920bc73a8bbcbe3f57144ad33409ef7faaab430e13f4c42d304d11347360c84972ca20b1539cce3a288
+R = 1f8f504e64a502e51e7c129517931c3b71f0d8a63b19cfe01ff7c951c6525249608b3ef5d00061d77eb6b3d69581adeaa3732c773bbb9b919c3e7c71fdc09f44d06
+S = 058044fc64b340604ffd02a5b2918d76fd6fb59ea895feab7aa218e6f1e8c8f226eb9ee345ef8140183a69272582005077b008006aab11597e808d7ff1e8382c924
+
+Msg = 00669f433934992257bed55861df679804107d7fa491672574a7624949c60049b0533383c88d6896c8de860704c3e6a6aefce83efa57c4d57e9ab253da5d15e1f53ab6dce218b592772ab0bc01fee8e63368e85c0639301456fe2d44cd5396a7f2b22761cd03b80eba7883eede8249a2f5db2183bf00550c5c002f45a5e4fb31
+d = 1b0c9acd3eeb618b4b0de4db402206f0f29adc69d7ad324b6db6601b351f723ac8fe949eeacd34228649bf0126276e5aceb0137d00c30dd858aef2d6b6449de2e89
+Qx = 1811c8884486aaa083ddee1c51cb6e861cb830bd5eaa929f72efadbbd1286566ae7e7ba7fde7e02529900d35ee64591652d28798bfc1bed0d192602a9cf5a7d22e3
+Qy = 06d7fc9dd494816cfd29613d4689af67f7d0a2e6fbad5d4d6e0130189172a1ab601c5ca71deaa8bfcb5a190d49da191672ff6fc048e146cb902acec5eae6d87e60a
+k = 1fdc4f108070af3c66c9ba7b6c1f2603a19ceb4760399df81228cfc7eafde1082b5a0716a3ff82fbe84726f14dd0db3376ca184a78c3c60679bab6cd45f77f9b9ce
+R = 1ec310339ff056faeb341c4499c43782078b04be1725ae9a6cdcb6011c46d1a4eb3d75c358225e4ec142fd1cd344186f5eb597f7ba559ddfa954824365d5b6edaec
+S = 005b679a33fdb7e04834f071cd0ac514c04add9f2614ab9bbd9b407b1420fed3f3e02a108e7e279899e43dcf64ae4083c289a87cd7d2103bdc036a95d36800ac7c6
+
+Msg = 4be81dcfab39a64d6f00c0d7fff94dabdf3473dc49f0e12900df328d6584b854fbaebaf3194c433e9e21743342e2dd056b445c8aa7d30a38504b366a8fa889dc8ecec35b3130070787e7bf0f22fab5bea54a07d3a75368605397ba74dbf2923ef20c37a0d9c64caebcc93157456b57b98d4becb13fecb7cc7f3740a6057af287
+d = 181e1037bbec7ca2f271343e5f6e9125162c8a8a46ae8baa7ca7296602ae9d56c994b3b94d359f2b3b3a01deb7a123f07d9e0c2e729d37cc5abdec0f5281931308a
+Qx = 0cfa5a8a3f15eb8c419095673f1d0bd63b396ff9813c18dfe5aa31f40b50b82481f9ed2edd47ae5ea6a48ea01f7e0ad0000edf7b66f8909ee94f141d5a07efe315c
+Qy = 18af728f7318b96d57f19c1104415c8d5989565465e429bc30cf65ced12a1c5856ac86fca02388bc151cf89959a4f048597a9e728f3034aa39259b59870946187bf
+k = 09078beaba465ba7a8b3624e644ac1e97c654533a58ac755e90bd606e2214f11a48cb51f9007865a0f569d967ea0370801421846a89f3d09eb0a481289270919f14
+R = 19cf91a38cc20b9269e7467857b1fc7eabb8cea915a3135f727d471e5bfcfb66d321fabe283a2cf38d4c5a6ecb6e8cbee1030474373bb87fcdfcc95cf857a8d25d0
+S = 1cf9acd9449c57589c950f287842f9e2487c5610955b2b5035f6aacfd2402f511998a1a942b39c307fc2bcab2c8d0dae94b5547ddccfb1012ca985b3edf42bbba8b
+
+[P-521,SHA-512]
+
+Msg = 9ecd500c60e701404922e58ab20cc002651fdee7cbc9336adda33e4c1088fab1964ecb7904dc6856865d6c8e15041ccf2d5ac302e99d346ff2f686531d25521678d4fd3f76bbf2c893d246cb4d7693792fe18172108146853103a51f824acc621cb7311d2463c3361ea707254f2b052bc22cb8012873dcbb95bf1a5cc53ab89f
+d = 0f749d32704bc533ca82cef0acf103d8f4fba67f08d2678e515ed7db886267ffaf02fab0080dca2359b72f574ccc29a0f218c8655c0cccf9fee6c5e567aa14cb926
+Qx = 061387fd6b95914e885f912edfbb5fb274655027f216c4091ca83e19336740fd81aedfe047f51b42bdf68161121013e0d55b117a14e4303f926c8debb77a7fdaad1
+Qy = 0e7d0c75c38626e895ca21526b9f9fdf84dcecb93f2b233390550d2b1463b7ee3f58df7346435ff0434199583c97c665a97f12f706f2357da4b40288def888e59e6
+k = 03af5ab6caa29a6de86a5bab9aa83c3b16a17ffcd52b5c60c769be3053cdddeac60812d12fecf46cfe1f3db9ac9dcf881fcec3f0aa733d4ecbb83c7593e864c6df1
+R = 04de826ea704ad10bc0f7538af8a3843f284f55c8b946af9235af5af74f2b76e099e4bc72fd79d28a380f8d4b4c919ac290d248c37983ba05aea42e2dd79fdd33e8
+S = 087488c859a96fea266ea13bf6d114c429b163be97a57559086edb64aed4a18594b46fb9efc7fd25d8b2de8f09ca0587f54bd287299f47b2ff124aac566e8ee3b43
+
+Msg = b3c63e5f5a21c4bfe3dbc644354d9a949186d6a9e1dd873828782aa6a0f1df2f64114a430b1c13fe8a2e09099e1ed05ef70de698161039ded73bcb50b312673bb073f8a792ac140a78a8b7f3586dffb1fc8be4f54516d57418ccc9945025ce3acf1eb84f69ceee5e9bd10c18c251dbc481562cd3aae54b54ab618cb1eeda33cf
+d = 1a4d2623a7d59c55f408331ba8d1523b94d6bf8ac83375ceb57a2b395a5bcf977cfc16234d4a97d6f6ee25a99aa5bff15ff535891bcb7ae849a583e01ac49e0e9b6
+Qx = 04d5c8afee038984d2ea96681ec0dccb6b52dfa4ee2e2a77a23c8cf43ef19905a34d6f5d8c5cf0981ed804d89d175b17d1a63522ceb1e785c0f5a1d2f3d15e51352
+Qy = 014368b8e746807b2b68f3615cd78d761a464ddd7918fc8df51d225962fdf1e3dc243e265100ff0ec133359e332e44dd49afd8e5f38fe86133573432d33c02fa0a3
+k = 0bc2c0f37155859303de6fa539a39714e195c37c6ea826e224c8218584ae09cd0d1cc14d94d93f2d83c96e4ef68517fdb3f383da5404e5a426bfc5d424e253c181b
+R = 1a3c4a6386c4fb614fba2cb9e74201e1aaa0001aa931a2a939c92e04b8344535a20f53c6e3c69c75c2e5d2fe3549ed27e6713cb0f4a9a94f6189eb33bff7d453fce
+S = 16a997f81aa0bea2e1469c8c1dab7df02a8b2086ba482c43af04f2174831f2b1761658795adfbdd44190a9b06fe10e578987369f3a2eced147cff89d8c2818f7471
+
+Msg = 6e0f96d56505ffd2d005d5677dbf926345f0ff0a5da456bbcbcfdc2d33c8d878b0bc8511401c73168d161c23a88b04d7a9629a7a6fbcff241071b0d212248fcc2c94fa5c086909adb8f4b9772b4293b4acf5215ea2fc72f8cec57b5a13792d7859b6d40348fc3ba3f5e7062a19075a9edb713ddcd391aefc90f46bbd81e2557b
+d = 14787f95fb1057a2f3867b8407e54abb91740c097dac5024be92d5d65666bb16e4879f3d3904d6eab269cf5e7b632ab3c5f342108d1d4230c30165fba3a1bf1c66f
+Qx = 0c2d540a7557f4530de35bbd94da8a6defbff783f54a65292f8f76341c996cea38795805a1b97174a9147a8644282e0d7040a6f83423ef2a0453248156393a1782e
+Qy = 119f746c5df8cec24e4849ac1870d0d8594c799d2ceb6c3bdf891dfbd2242e7ea24d6aec3166214734acc4cbf4da8f71e2429c5c187b2b3a048527c861f58a9b97f
+k = 186cd803e6e0c9925022e41cb68671adba3ead5548c2b1cd09348ab19612b7af3820fd14da5fe1d7b550ed1a3c8d2f30592cd7745a3c09ee7b5dcfa9ed31bdd0f1f
+R = 10ed3ab6d07a15dc3376494501c27ce5f78c8a2b30cc809d3f9c3bf1aef437e590ef66abae4e49065ead1af5f752ec145acfa98329f17bca9991a199579c41f9229
+S = 08c3457fe1f93d635bb52df9218bf3b49a7a345b8a8a988ac0a254340546752cddf02e6ce47eee58ea398fdc9130e55a4c09f5ae548c715f5bcd539f07a34034d78
+
+Msg = 3f12ab17af3c3680aad22196337cedb0a9dba22387a7c555b46e84176a6f8418004552386ada4deec59fdabb0d25e1c6668a96f100b352f8dabd24b2262bd2a3d0f825602d54150bdc4bcbd5b8e0ca52bc8d2c70ff2af9b03e20730d6bd9ec1d091a3e5c877259bcff4fd2c17a12bfc4b08117ec39fe4762be128d0883a37e9d
+d = 15807c101099c8d1d3f24b212af2c0ce525432d7779262eed0709275de9a1d8a8eeeadf2f909cf08b4720815bc1205a23ad1f825618cb78bde747acad8049ca9742
+Qx = 160d7ea2e128ab3fabd1a3ad5455cb45e2f977c2354a1345d4ae0c7ce4e492fb9ff958eddc2aa61735e5c1971fa6c99beda0f424a20c3ce969380aaa52ef5f5daa8
+Qy = 14e4c83f90d196945fb4fe1e41913488aa53e24c1d2142d35a1eed69fed784c0ef44d71bc21afe0a0065b3b87069217a5abab4355cf8f4ceae5657cd4b9c8008f1f
+k = 096731f8c52e72ffcc095dd2ee4eec3da13c628f570dba169b4a7460ab471149abdede0b63e4f96faf57eab809c7d2f203fd5ab406c7bd79869b7fae9c62f97c794
+R = 1e2bf98d1186d7bd3509f517c220de51c9200981e9b344b9fb0d36f34d969026c80311e7e73bb13789a99e0d59e82ebe0e9595d9747204c5f5550c30d934aa30c05
+S = 12fed45cc874dc3ed3a11dd70f7d5c61451fbea497dd63e226e10364e0718d3722c27c7b4e5027051d54b8f2a57fc58bc070a55b1a5877b0f388d768837ef2e9cec
+
+Msg = a1eed24b3b7c33296c2491d6ee092ec6124f85cf566bb5bc35bffb5c734e34547242e57593e962fb76aee9e800eed2d702cc301499060b76406b347f3d1c86456978950737703c8159001e6778f69c734a56e5ce5938bd0e0de0877d55adeee48b0d8dfa4ac65fd2d3ce3e12878bac5c7014f9284d161b2a3e7d5c88569a45f6
+d = 18692def0b516edcdd362f42669999cf27a65482f9358fcab312c6869e22ac469b82ca9036fe123935b8b9ed064acb347227a6e377fb156ec833dab9f170c2ac697
+Qx = 1ceee0be3293d8c0fc3e38a78df55e85e6b4bbce0b9995251f0ac55234140f82ae0a434b2bb41dc0aa5ecf950d4628f82c7f4f67651b804d55d844a02c1da6606f7
+Qy = 1f775eb6b3c5e43fc754052d1f7fc5b99137afc15d231a0199a702fc065c917e628a54e038cbfebe05c90988b65183b368a2061e5b5c1b025bbf2b748fae00ba297
+k = 161cf5d37953e09e12dc0091dc35d5fb3754c5c874e474d2b4a4f1a90b870dff6d99fb156498516e25b9a6a0763170702bb8507fdba4a6131c7258f6ffc3add81fd
+R = 14dfa43046302b81fd9a34a454dea25ccb594ace8df4f9d98556ca5076bcd44b2a9775dfaca50282b2c8988868e5a31d9eb08e794016996942088d43ad3379eb9a1
+S = 120be63bd97691f6258b5e78817f2dd6bf5a7bf79d01b8b1c3382860c4b00f89894c72f93a69f3119cb74c90b03e9ede27bd298b357b9616a7282d176f3899aaa24
+
+Msg = 9aace26837695e6596007a54e4bccdd5ffb16dc6844140e2eeeb584b15acb2bbffd203c74440b6ee8db676fd200b4186a8c3e957c19e74d4d865ada83f80655323dfa3570907ed3ce853b6e8cc375ed2d758a2f5ad265dd3b47650517a49b3d02df9e0c60c21576378c2b3a08481eec129b2a75608e13e6420127a3a63c8a3f1
+d = 0a63f9cdefbccdd0d5c9630b309027fa139c31e39ca26686d76c22d4093a2a5e5ec4e2308ce43eb8e563187b5bd811cc6b626eace4063047ac0420c3fdcff5bdc04
+Qx = 14cab9759d4487987b8a00afd16d7199585b730fb0bfe63796272dde9135e7cb9e27cec51207c876d9214214b8c76f82e7363f5086902a577e1c50b4fbf35ce9966
+Qy = 1a83f0caa01ca2166e1206292342f47f358009e8b891d3cb817aec290e0cf2f47e7fc637e39dca03949391839684f76b94d34e5abc7bb750cb44486cce525eb0093
+k = 01e51fd877dbbcd2ab138fd215d508879298d10c7fcbdcc918802407088eb6ca0f18976a13f2c0a57867b0298512fc85515b209c4435e9ef30ab01ba649838bc7a0
+R = 11a1323f6132d85482d9b0f73be838d8f9e78647934f2570fededca7c234cc46aa1b97da5ac1b27b714f7a171dc4209cbb0d90e4f793c4c192dc039c31310d6d99b
+S = 0386a5a0fc55d36ca7231a9537fee6b9e51c2255363d9c9e7cb7185669b302660e23133eb21eb56d305d36e69a79f5b6fa25b46ec61b7f699e1e9e927fb0bceca06
+
+Msg = ac2175940545d4fbab6e2e651c6830aba562e0c11c919e797c43eff9f187a68a9e5a128e3e2a330b955a3f4577d3f826529ad1b03d7b60f7ad678f005053b41dc0f8d267f3685c6abe1a0e9a733c44b2f3ca48b90806f935141c842e3a6c06a58f5343d75e3585971a734f4ae1074ce5b54f74bd9342f4bbca738d260393f43e
+d = 024f7d67dfc0d43a26cc7c19cb511d30a097a1e27e5efe29e9e76e43849af170fd9ad57d5b22b1c8840b59ebf562371871e12d2c1baefc1abaedc872ed5d2666ad6
+Qx = 09da1536154b46e3169265ccba2b4da9b4b06a7462a067c6909f6c0dd8e19a7bc2ac1a47763ec4be06c1bec57d28c55ee936cb19588cc1398fe4ea3bd07e6676b7f
+Qy = 14150cdf25da0925926422e1fd4dcfcffb05bdf8682c54d67a9bd438d21de5af43a15d979b320a847683b6d12ac1383a7183095e9da491c3b4a7c28874625e70f87
+k = 1c1308f31716d85294b3b5f1dc87d616093b7654907f55289499b419f38ceeb906d2c9fe4cc3d80c5a38c53f9739311b0b198111fede72ebde3b0d2bc4c2ef090d2
+R = 00dbf787ce07c453c6c6a67b0bf6850c8d6ca693a3e9818d7453487844c9048a7a2e48ff982b64eb9712461b26b5127c4dc57f9a6ad1e15d8cd56d4fd6da7186429
+S = 0c6f1c7774caf198fc189beb7e21ca92ceccc3f9875f0e2d07dc1d15bcc8f210b6dd376bf65bb6a454bf563d7f563c1041d62d6078828a57538b25ba54723170665
+
+Msg = 6266f09710e2434cb3da3b15396556765db2ddcd221dce257eab7399c7c490135925112932716af1434053b8b9fe340563e57a0b9776f9ac92cbb5fba18b05c0a2fafbed7240b3f93cd1780c980ff5fe92610e36c0177cabe82367c84cee9020cf26c1d74ae3eb9b9b512cb8b3cb3d81b17cf20dc76591b2b394ef1c62ac12ee
+d = 0349471460c205d836aa37dcd6c7322809e4e8ef81501e5da87284b267d843897746b33016f50a7b702964910361ed51d0afd9d8559a47f0b7c25b2bc952ce8ed9e
+Qx = 00bbd4e8a016b0c254e754f68f0f4ed081320d529ecdc7899cfb5a67dd04bc85b3aa6891a3ed2c9861ae76c3847d81780c23ad84153ea2042d7fd5d517a26ff3ce4
+Qy = 0645953afc3c1b3b74fdf503e7d3f982d7ee17611d60f8eb42a4bddbec2b67db1f09b54440c30b44e8071d404658285cb571462001218fc8c5e5b98b9fae28272e6
+k = 00eb2bd8bb56b9d2e97c51247baf734cc655c39e0bfda35375f0ac2fe82fad699bf1989577e24afb33c3868f91111e24fefe7dec802f3323ac013bec6c048fe5568
+R = 14bf63bdbc014aa352544bd1e83ede484807ed760619fa6bc38c4f8640840195e1f2f149b29903ca4b6934404fb1f7de5e39b1ea04dba42819c75dbef6a93ebe269
+S = 05d1bcf2295240ce4415042306abd494b4bda7cf36f2ee2931518d2454faa01c606be120b057062f2f3a174cb09c14f57ab6ef41cb3802140da22074d0e46f908d4
+
+Msg = 3de9e617a6868dca1a1432d503f923535da3f9b34426b2a4822174399c73b1c1ee67311410a58c17202ac767844b2024d8aa21a205707d93865693ac25a24fc87034fa3a7a7e27c3344cb03b87602c15180a5fe6a9dd90cd11af4a0f150207bf2d83f55b12c088adae99aa8cfa659311b3a25beb99056643760d6a282126b9b2
+d = 07788d34758b20efc330c67483be3999d1d1a16fd0da81ed28895ebb35ee21093d37ea1ac808946c275c44454a216195eb3eb3aea1b53a329eca4eb82dd48c784f5
+Qx = 0157d80bd426f6c3cee903c24b73faa02e758607c3e102d6e643b7269c299684fdaba1acddb83ee686a60acca53cddb2fe976149205c8b8ab6ad1458bc00993cc43
+Qy = 16e33cbed05721b284dacc8c8fbe2d118c347fc2e2670e691d5d53daf6ef2dfec464a5fbf46f8efce81ac226915e11d43c11c8229fca2327815e1f8da5fe95021fc
+k = 0a73477264a9cc69d359464abb1ac098a18c0fb3ea35e4f2e6e1b060dab05bef1255d9f9c9b9fbb89712e5afe13745ae6fd5917a9aedb0f2860d03a0d8f113ea10c
+R = 07e315d8d958b8ce27eaf4f3782294341d2a46fb1457a60eb9fe93a9ae86f3764716c4f5f124bd6b114781ed59c3f24e18aa35c903211b2f2039d85862932987d68
+S = 1bcc1d211ebc120a97d465b603a1bb1e470109e0a55d2f1b5c597803931bd6d7718f010d7d289b31533e9fcef3d141974e5955bc7f0ee342b9cad05e29a3dded30e
+
+Msg = aa48851af7ef17abe233163b7185130f4646203c205e22bcc2a5a3697bcab998c73a9ffe1d3ea0b7978ce7df937a72586eb5ca60b0d939a7d1c115c820171c89c8116b7e2c7b98cf0f14e4c4df3cb2f319ad3ab0ea25ff14526ddc037469f000bf82100acd4cdf94feb4eba4ea1726f0569336604a473aee67d71afebb569209
+d = 1f98696772221e6cccd5569ed8aed3c435ee86a04689c7a64d20c30f6fe1c59cc10c6d2910261d30c3b96117a669e19cfe5b696b68feeacf61f6a3dea55e6e5837a
+Qx = 07002872c200e16d57e8e53f7bce6e9a7832c387f6f9c29c6b75526262c57bc2b56d63e9558c5761c1d62708357f586d3aab41c6a7ca3bf6c32d9c3ca40f9a2796a
+Qy = 1fe3e52472ef224fb38d5a0a14875b52c2f50b82b99eea98d826c77e6a9ccf798de5ffa92a0d65965f740c702a3027be66b9c844f1b2e96c134eb3fdf3edddcf11c
+k = 1a277cf0414c6adb621d1cc0311ec908401ce040c6687ed45a0cdf2910c42c9f1954a4572d8e659733d5e26cbd35e3260be40017b2f5d38ec42315f5c0b056c596d
+R = 0d732ba8b3e9c9e0a495249e152e5bee69d94e9ff012d001b140d4b5d082aa9df77e10b65f115a594a50114722db42fa5fbe457c5bd05e7ac7ee510aa68fe7b1e7f
+S = 134ac5e1ee339727df80c35ff5b2891596dd14d6cfd137bafd50ab98e2c1ab4008a0bd03552618d217912a9ec502a902f2353e757c3b5776309f7f2cfebf913e9cd
+
+Msg = b0d5d52259af364eb2d1a5027e5f7d0afe4b999cc5dd2268cfe76f51d2f17b541bdd7867e23a1bb897705153d9432a24012108979c6a2c9e2567c9531d012f9e4be764419491a52eae2e127430b0ab58cb8e216515a821b3db206447c235bf44ee304201b483b2a88844abaa18bca0147dfff7e502397dd62e15524f67eb2df2
+d = 13c3852a6bc8825b45fd7da1754078913d77f4e586216a6eb08b6f03adce7464f5dbc2bea0eb7b12d103870ef045f53d67e3600d7eba07aac5db03f71b64db1cceb
+Qx = 0c97a4ebcbbe701c9f7be127e87079edf479b76d3c14bfbee693e1638e5bff8d4705ac0c14597529dbe13356ca85eb03a418edfe144ce6cbf3533016d4efc29dbd4
+Qy = 11c75b7a8894ef64109ac2dea972e7fd5f79b75dab1bf9441a5b8b86f1dc1324426fa6cf4e7b973b44e3d0576c52e5c9edf8ce2fc18cb3c28742d44419f044667f8
+k = 1e25b86db041f21c2503d547e2b1b655f0b99d5b6c0e1cf2bdbd8a8c6a053f5d79d78c55b4ef75bff764a74edc920b35536e3c470b6f6b8fd53898f3bbc467539ef
+R = 1dce45ea592b34d016497882c48dc0c7afb1c8e0f81a051800d7ab8da9d237efd892207bc9401f1d30650f66af8d5349fc5b19727756270722d5a8adb0a49b72d0a
+S = 0b79ffcdc33e028b1ab894cb751ec792a69e3011b201a76f3b878655bc31efd1c0bf3b98aea2b14f262c19d142e008b98e890ebbf464d3b025764dd2f73c4251b1a
+
+Msg = 9599788344976779383a7a0812a096943a1f771ee484d586af1a06207478e4c0be9c200d42460fe837e24b266c8852d80d3c53cc52ffb1913fc3261145fc6da575611efd16c026059a2e64f802517ffd1b6b34de10ad2909c65c2155e8d939b8115400c1d793d23955b15f5d1c13c962ff92b4a815cee0e10f8e14e1f6e6cd38
+d = 1654eaa1f6eec7159ee2d36fb24d15d6d33a128f36c52e2437f7d1b5a44ea4fa965c0a26d0066f92c8b82bd136491e929686c8bde61b7c704daab54ed1e1bdf6b77
+Qx = 1f269692c47a55242bb08731ff920f4915bfcecf4d4431a8b487c90d08565272c52ca90c47397f7604bc643982e34d05178e979c2cff7ea1b9eaec18d69ca7382de
+Qy = 0750bdd866fba3e92c29599c002ac6f9e2bf39af8521b7b133f70510e9918a94d3c279edec97ab75ecda95e3dd7861af84c543371c055dc74eeeff7061726818327
+k = 1b7519becd00d750459d63a72f13318b6ac61b8c8e7077cf9415c9b4b924f35514c9c28a0fae43d06e31c670a873716156aa7bc744577d62476e038b116576a9e53
+R = 183bddb46c249e868ef231a1ebd85d0773bf8105a092ab7d884d677a1e9b7d6014d6358c09538a99d9dca8f36f163ac1827df420c3f9360cc66900a9737a7f756f3
+S = 0d05ee3e64bac4e56d9d8bd511c8a43941e953cba4e5d83c0553acb87091ff54f3aad4d69d9f15e520a2551cc14f2c86bb45513fef0295e381a7635486bd3917b50
+
+Msg = fdde51acfd04eb0ad892ce9d6c0f90eb91ce765cbe3ce9d3f2defe8f691324d26b968b8b90e77706b068585f2a3ee7bf3e910528f7403c5af745a6f9d7ba6c53abd885c3b1be583415b128f4d3f224daf8563476bd9aa61e9c8518c144335f8f879c03696bddbe3ac37a8fbede29861611feaa87e325e2f60278b4893ed57fb0
+d = 1cba5d561bf18656991eba9a1dde8bde547885ea1f0abe7f2837e569ca52f53df5e64e4a547c4f26458b5d9626ed6d702e5ab1dd585cf36a0c84f768fac946cfd4c
+Qx = 12857c2244fa04db3b73db4847927db63cce2fa6cb22724466d3e20bc950a9250a15eafd99f236a801e5271e8f90d9e8a97f37c12f7da65bce8a2c93bcd25526205
+Qy = 0f394e37c17d5b8e35b488fa05a607dbc74264965043a1fb60e92edc212296ae72d7d6fe2e3457e67be853664e1da64f57e44bd259076b3bb2b06a2c604fea1be9d
+k = 0e790238796fee7b5885dc0784c7041a4cc7ca4ba757d9f7906ad1fcbab5667e3734bc2309a48047442535ff89144b518f730ff55c0c67eeb4c880c2dfd2fb60d69
+R = 1d7ce382295a2a109064ea03f0ad8761dd60eefb9c207a20e3c5551e82ac6d2ee5922b3e9655a65ba6c359dcbf8fa843fbe87239a5c3e3eaecec0407d2fcdb687c2
+S = 161963a6237b8955a8a756d8df5dbd303140bb90143b1da5f07b32f9cb64733dc6316080924733f1e2c81ade9d0be71b5b95b55666026a035a93ab3004d0bc0b19f
+
+Msg = beb34c997f905c77451ac392f7957a0ab8b23325bd5c63ca31c109ac8f655a1e3094240cb8a99284f8091de2ab9a7db2504d16251980b86be89ec3a3f41162698bab51848880633e0b71a38f8896335853d8e836a2454ecab2acdcc052c8f659be1d703b13ae1b090334ac50ab0137ddb5e8b924c0e3d2e5789daaef2fdd4a1e
+d = 0972e7ff25adf8a032535e5b19463cfe306b90803bf27fabc6046ae0807d2312fbab85d1da61b80b2d5d48f4e5886f27fca050b84563aee1926ae6b2564cd756d63
+Qx = 1d7f1e9e610619daa9d2efa563610a371677fe8b58048fdc55a98a49970f6afa6649c516f9c72085ca3722aa595f45f2803402b01c832d28aac63d9941f1a25dfea
+Qy = 1571facce3fcfe733a8eef4e8305dfe99103a370f82b3f8d75085414f2592ad44969a2ef8196c8b9809f0eca2f7ddc71c47879e3f37a40b9fecf97992b97af29721
+k = 0517f6e4002479dc89e8cbb55b7c426d128776ca82cf81be8c1da9557178783f40e3d047db7e77867f1af030a51de470ee3128c22e9c2d642d71e4904ab5a76edfa
+R = 1c3262a3a3fb74fa5124b71a6c7f7b7e6d56738eabaf7666b372b299b0c99ee8a16be3df88dd955de093fc8c049f76ee83a4138cee41e5fe94755d27a52ee44032f
+S = 072fd88bb1684c4ca9531748dfce4c161037fcd6ae5c2803b7117fb60d3db5df7df380591aaf3073a3031306b76f062dcc547ded23f6690293c34a710e7e9a226c3
+
+Msg = 543c374af90c34f50ee195006d5f9d8dd986d09ad182fcbefa085567275eee1e742bfe0af3d058675adeb5b9f87f248b00a9fbd2aa779129123a5b983f2f26fc3caf2ea34277550c22fe8c814c739b46972d50232993cddd63a3c99e20f5c5067d9b57e2d5db94317a5a16b5c12b5c4cafbc79cbc2f9940f074bbc7d0dc71e90
+d = 1f0ec8da29295394f2f072672db014861be33bfd9f91349dad5566ff396bea055e53b1d61c8c4e5c9f6e129ed75a49f91cce1d5530ad4e78c2b793a63195eb9f0da
+Qx = 09ec1a3761fe3958073b9647f34202c5e8ca2428d056facc4f3fedc7077fa87f1d1eb30cc74f6e3ff3d3f82df2641cea1eb3ff1529e8a3866ae2055aacec0bf68c4
+Qy = 0bed0261b91f664c3ff53e337d8321cb988c3edc03b46754680097e5a8585245d80d0b7045c75a9c5be7f599d3b5eea08d828acb6294ae515a3df57a37f903ef62e
+k = 0ac3b6d61ebda99e23301fa198d686a13c0832af594b289c9a55669ce6d62011384769013748b68465527a597ed6858a06a99d50493562b3a7dbcee975ad34657d8
+R = 0cef3f4babe6f9875e5db28c27d6a197d607c3641a90f10c2cc2cb302ba658aa151dc76c507488b99f4b3c8bb404fb5c852f959273f412cbdd5e713c5e3f0e67f94
+S = 0097ed9e005416fc944e26bcc3661a09b35c128fcccdc2742739c8a301a338dd77d9d13571612a3b9524a6164b09fe73643bbc31447ee31ef44a490843e4e7db23f
+
+
+[K-233,SHA-224]
+
+Msg = f23f784fe136c9fc0d169503d361e9c6148b0f1fbdcae0a97fae1af7033ddef25cb7489c9963cfcb009a8cbfe44a8510a64a073eb1deae4c324ceb9302008c92c69b2dafcc9077fd3cc3c7c119edc3ced36d176ceaa55ac036bf7f07f6fa215e8bb8196e59a5e1c9af4f98b90ab4970885bd7015fa26a09e03c7cf6b4b23d929
+d = 04c1d414696cc3657dd9df73ace56eda2636769ce7082e064c260be45a5
+Qx = 1f228c0a75b057eb07fe7ce8223ed4163148c1fdab61e0f787271f836a9
+Qy = 0cdfa5655d96ffd5ffb6027bfaa04da7b5d8fbdbb6202c8bb79f056ce43
+k = 058f8511089fcd59324469f6736b92693afe26bd4719e198f1f2287dc5f
+R = 016bafefb4933ffd00bd1db6d6c4fac8a06375603adc0aa2a5664083ff4
+S = 03bcb84b8f1990cfc7b88f2b8cc817105cd8e150808e7c87b310cdc47e3
+
+Msg = 400bcb297552bb37f2f8135a9314a35f5126788bb6fa4dc74152731ff64c5dab4b902103d85443dec20e16b1d6629930cdc2bd183d4099f0e96295a63c2fe266f5e9d050c401a8681b4a438efe53cbd8f2f43e2a31e9f88926a9c82917d873f6e8cd5ff5eb8c1ca36126b0bfc8c2b0e85a7c9e7a45f1875ca9c82019ebedb729
+d = 027cb1d84865a16992476c9e353283d5d6a40c349a8e9179d1b1f403531
+Qx = 1191227d064176f4ab020faea61330df5eb59163ecb4ea59c23e6f1f6c8
+Qy = 12dbfbf85b3624b9f56446f840602f9b839bab1368295b3ae919cb07c07
+k = 01a41af270269be052a62a9879638e3432a1479b05776ce61f45c0c361b
+R = 041a5f1d28b70bfa2925b9428ab8bac9fa174d88ae27d754824c7d16ead
+S = 044d359065672b3d3dfe8389fbc6fc751ca6a46820626c466174fb9b922
+
+Msg = 5f74d4b35c49fa454c97c05fdb6b9f6822cf1a2295f15bd766dbcb413d77c910bd8f4147e8f317fac2300fa21cb80134d1b6f8ae8e50518c1f648a28506e419f5a6e8f05abffdb3dd2587606c7e9c223ecff4f46b121216730ea13202b59128a7616bb2fd23a7e4a5aa08641cc07b669641313febfc88d64d99447353dae3f06
+d = 031b443f46c4b5224237fac1022ee1570173f664aba0c84dbaa4246bdc1
+Qx = 05f57b0e5f2e175006f4058cbb4ca9a0cac912c551ef1b94e97498fcc5a
+Qy = 0f3a554d077b751478f8a2b7c2a9cf15effed958e0ac1a9e3db1e023c5f
+k = 07ff6ef3026c5a960e632beeb7313b3bca0baec76cea1fd9b82cedc3245
+R = 0099741698549c32a4e86aab6194527cea703ff869849c538a938585a83
+S = 02ad706c6f5dcff512498d84f1877eb997dfbe9b3d13b339917632d3cb1
+
+Msg = 8f92096876d9f81bcd992369d42d0b5877ac969004d17c8627c58d8b8b7bbf7a37e8cb6afa962b9b043bbbaa5bef4a5ee38d8bd31cb5866b828265a2f4102a616f87009cd346fcb8af5519fb577c60d8792472232f33dc615655e53d2b715b15a2697b492f108b7906e1e3597c6911f8cc30c7121ae338a6b747ec368f8e4a36
+d = 048f6ca29f35f253a4962734357c995920967b9eeff1ba5fd2080bfede5
+Qx = 12b7ca7c21292f8795b2fbfd63a28c5a4ec8c850d6240f973c903bc8170
+Qy = 1be9855e5c5a5064c27d1862010b2fd0d7be5a0180c861a288ceac89d6d
+k = 07dcb9725323fd7668991ce9a907b7129d53fae9016e253c53d057d195d
+R = 0498c4fca6ed7c2998347b464d3e562a74b0e4f3a6c1dc453aaa61bb710
+S = 03a77a13f011404d5c5341dcd2ca44dc2b08f21f09f524045c281fb221e
+
+Msg = 3d275dbde44494c45fc15fe89e2ae32aa26426a17e923e895c7941a5582fb95df4d49873ab1bde358017f336b911b886b626b744806ab8113418473c441f1964159ded1b12122d53ac56573167588e4b55f36b8bca8c67823883a51fb6e7f204d1c6b07ea49b577bfab9ca6b8d51f72268b022e3a4db6f9d265ee8382f9b7b66
+d = 019b940eabbe682f961d9f3d90432e347fef3910e641656825d775705b1
+Qx = 1efcc9f4576047c43eab1c13e0547b1c5ec1cd2afd2345fda72b5e1b50f
+Qy = 0c7b5968af47e58f4ec15c0cd82ccd0b9f5bfde06c7f86fe5cd0105d693
+k = 03f783a94d1de73e4593f5d6d02238cfa0486e3ddf2bc0b95a528038e3c
+R = 013c467531f3f6508534ad072edb210e4182ce5a798d8a46674e92a0b4d
+S = 0685982aa8e2f3e46ecc03e00e7323f3b891da437235cfe9800139ee8d7
+
+Msg = d2fa68e1f7dad02916b12fa38f1849d6d409dbad0344438520b4dd9b77d62d39ac9ae3cdeab03ccbcfd4de703c6e798873671731c108f322b9f2a68145e3e210c9b15b879798e5c53c5022742e9819b99edabb2f44d89ae221f7a99dc84421a6905695ff91928db608f861745f17584d56e34b75c47281435b1b0b34e490692d
+d = 07a884b22e29fa9fe945e9ba13c0df8d786dc87cef0f77f069e182dd56c
+Qx = 11e831647d0ffd53d75e44abceda753ab470b3cc93b457590617d925a19
+Qy = 03db5bd0aecd6504d904bcf9dcce131abd239aeadb9a64a9811eac823cc
+k = 00241b763c6245b83afe61762b161c41467ef35b7f27a9c1066f02babd3
+R = 0514adca3481ac5f99287e6e966a5c223296b07a9456eb582ec5568688c
+S = 07ff6a2f7cb1d2594a11d8d0adb6fe50b4e740f025e7b4333ee26163d92
+
+Msg = 3830f75cf9df4eb2998c7c1b5fe11c1476bcf849c3a8fa7d3d0b5bc2292e5d07465ab8cc9381c575d909e509c5dac49c78817c04e4bef18bd51bb09aa5897f21634633a5ce6d20bb4638cb6c3927351eaec7b62cf4a33956916045c392f325adafb10a88a5f86d7e41dd77908fa7284210071c22aa40ef40da6339c02da05392
+d = 05da61f881d5a0dc085bb93764f584352882923cd237d878220ec624c1a
+Qx = 18d740441eff1f785a14d04da4ba69540cbb469780ffd36e1dfae4f1de2
+Qy = 18072ab30e999ae26b872ef46a9a0604296d02c08fba9477d9e03f0f75d
+k = 000f95c5678fd08dda790cc60bfa578118f8687228a2ef5f31e71a6884b
+R = 074a6599b8cab75e0cf752e3f41288fbc673d52074950edb14f76524949
+S = 03523804351e3224e816cd4fb7191f332585f68053ddb32a85cc0fadc03
+
+Msg = 65b9fe15e6c35d453caa6bad39ee78a720a04b60d8a0a0f049186d2f777e48ae2d657e174df53edb7beb9f7d8f21904ed674add0cda5b62a7308de76c324a144021e8c6d387daaba4ce48bf7dfe9c8aeee2c64e434ece1fa5ddcafcf3e5d0013a1eeec1742a00d384cc2ec0d7eda83bb4dccfb0e57045ebfc27a4f404d03da37
+d = 03fe9f04647f6d82b13ec1ae5a8c2e49bc66b05649ad778eb16149ad83a
+Qx = 158eecc6b8918e7813ef990217c603b28ed1774c740382a8af5c9af6133
+Qy = 1bbffeccd41107c7e6f83e24c822d634a7ec064fae125dc8a3ecc4fc9b3
+k = 07731edfb3ef523a165a1b5817ab2805a5cf88043c98ea2393898e19551
+R = 01fa44fa18ebafee6f419fdb9de0e8365520617558b57e9ee89f2c8fc88
+S = 053f1b2da4cabad04fea1111d525f341417587823fce71e5bfd2353c2f1
+
+Msg = d26521fd41eb5d46ece6836e188bf9cb1b461d011c41e002a935d256654d01725378e845920ec4a7fd3f379df54772493df50d312c7c6aa4e909e7b83f2442c3a5e85c37d68aa015098ecfb0a5e077370f4576f4bc63bf37e1dee06d780a3b6949af5e21c2a0960fcd20821ef5f17bebf5fd5b3bdda260842cbbfad45667287a
+d = 05ebce648ace4cd555413de6a456fc487d14bf4b0b9a72311ef480d2f26
+Qx = 020b46ecbdc36b4dc01111932090ba185eab2cdc4fa89775f2a6177c592
+Qy = 104cac1c800103c79642321a216bcfae497b037b29888cf9f70c507114e
+k = 027733120626e564b06ba71c4946c9c8bfae43f88511ec6352d2a52f407
+R = 0592de5184510e6ecb7be8a011f862470b918354a1ad82458cf716137fe
+S = 010a9c5fb6e4b70571a35c56744b57baf0108728bea2bf639af1960d1dc
+
+Msg = b778c021b1a92c41dbd09963da07018075d73e54d62df5c2b7bf8abe137151650d1c1c6abce7eebd8f32e8c3e6d1433773f257bb3ba4a4fb6a02c0db1e47d03c27d3a90898ebd1927c21df24c4c5443ca5b81f8ef2cc0f5e8b3d08f472bf07085df737adaedec63d99acd77b87ba98225f198b791124ac2d9b191cb9251b4b00
+d = 056653c2f85593f789a926ba49fa3da9d7f946d8f1020508c5a527ce813
+Qx = 10d65f6f5415dd86a83bb10118abfc1b1670a1664eb6dae99fb68b85019
+Qy = 12c1e673e575086ec1e76b90d59c2cbd2727f726f88298552b678ba7e60
+k = 021e26c098c9f9da9c782857fe640ff6abb21caf20a093f2277845bd10d
+R = 01d67cbc8209494dca1a74cee5d9894f98f03728214f7bbdac29b0c0e78
+S = 02215f758fcf0d8dd603e79658a8061ab45bfe6d854e52ea7074fd5654e
+
+Msg = ec14e07f615960015a489ef999e308b42a4c571473b9bd64b433dabd9a1b1ad02e33eee9100064405175928a94543a80f440040afa2965b4e5f95f768e7fab6d3c0a5f5e1bf1df7822f78384e80f2955ea85f044ac60537d895747979f935bb0cd3673193c4a32dd7803e48d7daf70a71bc2aa97236615b6411e28fc9a652145
+d = 049a91d320783cc70a5952c32036cfc75d41f1aa84127db2dc759fb291c
+Qx = 190528df8fc3ae4db6e12930f176ec9c833d1668ac5808f1046366445a4
+Qy = 1f647d55ce80b18a9add47fd1a8e4aa725297d9da03246f5c1ce503dd56
+k = 01eb80e2596d6c01431e7a4fd9e22903ea85547a31d675ff157a789a137
+R = 04523776d88199ebac2f96f9faa434bd81bde770ad4458ef126fde9198a
+S = 054665f31f92f8897482d34fcb63141a7539577037c84496167e9d3389f
+
+Msg = 89c645339ad0eb850e4e2fe583cee175b35feb02ed7541d7e9aace24cdd3939584f73ad39526de6399c86b36de77a018e2c70b532bd0f032f9137d10480acc30c49f9baaa86f9df0033b77e98b485bf7a69cb5c281e527d3ccd1fce2415f0dda4a268ce68a0a34b16afda54ed922cd6810ac8dc766df2a3a6c5e55972e9786fc
+d = 016a20016602fc7088a60469843e1d29ad67e3c3cb9500b1e2a00d4050a
+Qx = 04f157541dc3a8bc8a2ad4dfb3933039b67e331b7353a2fa9ede322f4ad
+Qy = 1348a7b8c9495bcbecd556870715faf3d543cb8f2368805473bca17b82e
+k = 01df1ee39217d7f0d838e8b2d30a1159d8003b06e50a00d637edf08d6d1
+R = 045d16826bbc425637e7a05b826bc907f7453c70141d1bbd2cda63dd490
+S = 01ae1703cf179dfd1d5407ba2b7324cc7cac15235ee9c3756177444e122
+
+Msg = ace14c4b101d2d8453c2bc22b756af016b5de537df9c3e639d208ad04ae0bf6232dc90b90c33228dc85de956db771ffde05fb4d0b15e4f218ed2771d703ae5bf981252a5bcd60c16f14483131a481cbe04dc0adb1fb8aa32cb48bb5008e8a8e5c7b7465be2fd7afbc811cf5ea6293b1a464669b49f55f57b93a8707e6042fda6
+d = 00ba922149bada2551b7be1c3df076f3f97ce93c13c50c285fef3f42363
+Qx = 12daff2cfab994b9d1d1ba73bd2f8e7883b2d92f760b0d16351ec125fd4
+Qy = 115666f7c65b95ec2d713c5ab1a3eeaaf0f931b1859733416c3c778aa2a
+k = 07fc7c9503fabba0972e0e8892ec6331e0812c6452d211c5561fde79048
+R = 06477ec9d8d8d45418b9efe7ae47c0863ff94c43d8f392c079b870a7cf4
+S = 06b5a5d020b3d980b9d7880130802435ddb4e7362e36a70d193f18a7fe6
+
+Msg = cec2ba0d1772c87e87d5bbbd67220692bea4301aa1a66e8dbdd7e651d45c26dc2a0d45cfc32c34d76ae3e1c61db7b0fe1863457b93937d929e6ece7462ebd16adfd708353d6f7c27aafe06593c76da7149b0cc574a4290b0d8fe219f3eada7082aca38dba3f78ed0d5942d095fa5556fc8bcef331ff0a6d5d1f4e6c51d4ff5af
+d = 02d635e12a58cc6dea44e71e87c37f91e8d08659f0b7955d24f65ab55ba
+Qx = 1dd33d8224ffe63a32f2de5d4fcb0e5f1fca7ca2ade5b35ffbe75cdc658
+Qy = 0bfbe9dfe13f99258c787af82631ce2133dc73207c579b29869c7463943
+k = 04ef333049c575d6688aa04f87a6162185e4a57bb752a7f903e3aff86ff
+R = 01ade04af08ea1c1877779fbf6335156b1a1437f3e449f07458d700c67e
+S = 010fa82467d39e5ad51cda8fcedc72ee6a78dccd0c90544814e53ba9cb4
+
+Msg = ffa13cd0f51ae2643d5d4edecb493ddd653e9faddcffc370e7e958abf726a5d67a2ab36cef42ea8ebe22a6f01b9c31f6ffad01e6894487d979acb5e618f765ac0ec3550ac5dbbcede8f9fdbe52fbaba5c087ff382b6d7a09b2b5084227d324d98ff98793040884799b96d2ca593201f4414f18c43b51c53c5e5059e0641aca02
+d = 0073883e5064e06814fc4de32e15f7a6cf825d2daf6eb1df8c83e25d80a
+Qx = 00d3c79d627ee0d2d88f2de2dd082112c20dbc5ed66089454f7b8fd9f81
+Qy = 1a2580e779753bcb023acba1b0852492b989c767f664c7047de8e6689fb
+k = 020231e05166271f47a91dd883c580ee313e9a07195ae511f0ee62173ec
+R = 0303eb4a0df97577c4cff531b3f54aa282e76669c0c5ebf4c9779c9bb82
+S = 0692432a7dfde09db7743f08130b3d3327dd98cbdc323627603518f70d7
+
+[K-233,SHA-256]
+
+Msg = c73e3dbac9513d0361dabe94071faf03a11cba18c06d131a172d5f0125b01a5eeb6055bf72c7106fe3f4be3bd2b1771cbe7f85366dccfbc3bac20538510c3f51179cc540ddafb2f3b05a0d276899674ab1d7d8fb4f6838f04e4f9e26b8c6af31540f63f4953c85840af4c57dfa78c704f637dfc8dd750fe45e2c1e149986d127
+d = 01532271bfae8d4dfe60f69b88d3006d58e28aacfa701861cde8d624db6
+Qx = 041c1ca965338976b4c45c28b1cb64836b3b4d3e7ba2b1323ea26fbcca2
+Qy = 1a177d042fba7903007db122eabc459e37c2c7fe82e42752b267fafe4b0
+k = 06a54894825644901baf2ec3681ce5aaf93a18757d93ec9cbce7ccd9d65
+R = 03edb77fc7686b520493604db18fc69edb4cad8195a958e27ef289c4bac
+S = 004337ecfac57abb9271909aa43ff4e32851df7818dcd87216d051189c0
+
+Msg = d00dcd0f3212a3167403abed91c20e76f5e7a7678a4fd970f944d11e6a8cd149d0aa6fd3164c5a74c0f55193a4fa3d8ba6f99cabed10544625a7bd92b3e0b46edbd4a269bbc10518c5268c3910a2aea567ccd32d4c7a0cbef09ea42c20b636d1f711d220e23dacdb9d1146e0494401349749e5ed88e38295232a7effbae3aed6
+d = 0550406c0db882c6aee6cf3b6baf377375208c3e90cc44a067cee43efcf
+Qx = 073348eaa8f2885fca3baf31830a2b28bfe983e3046418561f62ac5d247
+Qy = 0033de5aee6d0bd4de286f1de1e80bf72e5e17083032bd4dc24577b6d2d
+k = 05c0e7ad0f9bbd522c862326a5734a766423fff7efbe57c51c315fa574c
+R = 02103f1a0200883850b6476c7d7e7d2b3e2f60923d028ee6f8227b1ec48
+S = 007cbbc3c6295ceafb3d9cf8411f85a045b11ef8472c5ed45346d26192a
+
+Msg = 3d36221f87157ca4db84884b8666660c4e2b6af330480c516cded9f3bfe132543626a39bb6aed1964eb5c33ea0b95b9841665417679fceb95d199d55accfce35dd3f2283c1a7ced57d0c4b9ebe3da6e1ff2f979b6440db27caf9f6a4bbfa47e20d29ae304f4d0551fce9cc4097eb2fbedb9b24680bb17d207bdccdbe799d5b0d
+d = 0257dc63752920b6854d6c2d1cca68589a38418c3d036e73760a12214ab
+Qx = 11a42e9f66ecf030d0446cfb751136347d4df0ee4e031058ebdcc04df80
+Qy = 0fb7161fac8cc5ad7bc4477a39350e419776f76f184e28abce886ae9cc5
+k = 00391d36c4044896ddcd68604d5f677d1df298f46abc00eb12f1165e8a1
+R = 04e19bdc6755a603085b66355256bce98d5fdd49b4f06b628e3e185574a
+S = 07697b29ce5546de969c9c4bbb5ea65f712d6cda3410f3dbfa0cd5b1a8c
+
+Msg = 033d82a42d0eddf58fbe3e91ddff7190e3f9fc2b1e2eede977d2c0473b358b5fce1f981ca6f88fd61ce2f79e453e3a2b77d1baab2b970ed28d5dcff58873a620e195085e61c4b8480d829525a1a944e8a4b63352f0291f0311f1f98ceb262804beec1c74947618f8e3b067866255878c2502966cefcdda4f5fa2b13d92ce7840
+d = 029025352297a7be850f8852411c09259b83219135e0e8949c1bd5b94c1
+Qx = 184345e37f07077cc8df5947c1b1fcd8404b3c31586d6ebd91b240cf42b
+Qy = 19dbc9091a5d282fd6e62c34676a06a425e098567b990c47e61ef14d77e
+k = 02b2663a449ead3f8cce2459e04cf84333376624d994fd9312401ae57f1
+R = 03af223fd3a6b6b240e59dca83ce2477a577494438ddee3fd09632ea67f
+S = 0606576d89f2094572f0bbcb58a15d9a4bf10ae3667d4e35cdd8da32102
+
+Msg = 671a7c81b64b2919722d7b258bdbd90165bb757b53106e0af03d0eef27452942f40cf52bc95cc7f6567df2613cce795f8bcfc723b2735efc35375c001d37c58480d89343697146b524835df3dbd333f7c06c98e36d3c4592ecd1f34ab57c341bb0f4c785f5b8372775f74b4bce60763fad1788e77ea158d735a64861320b36c6
+d = 02dc82d0e69e498528925c0e62a13fda9af8cefd047c10c3ffc2e41da3e
+Qx = 0e5463926235ce53a85b489c3c278320ed986003962a5fc7ad4cbab0d9f
+Qy = 1453e6edde95670a4653186ebd8246c28a94dd84f5a669bd3293176f1f0
+k = 034a8dfbbdc98bb1d9b175600bffd866306dffadcc4bbb6f24e7f918da5
+R = 03cf1407445cf1a619a280e139242056c23c58979f0b3f0aa7e1fc074e2
+S = 02e55f27593f2c76fafccb71493f14daf50073b35cc85f002528cc6d691
+
+Msg = 0ef677f4799298f4aab73b7393598041f56e902ced1726af49657b6601a06186212e3ee8cd4bd33b760dfa2ea3c38884f94358d51dd479f2ccc8b0b352fa4e44fcfdcfbb24919d04e6ee1108527b8e8d60e8d1b467c30c18c5455e5835d483161d3fc26b4a67d6df9e3ddd9331247cb18450188752a1ca219f3396a872cb13d8
+d = 041535fff5d279bcd744b04e643458ce20b81df8a9e01b1181d52bb14e4
+Qx = 021e1227457be78e49db22335139a136ba290d34871f90ab5e6a8db6ac1
+Qy = 0df43b381a4d757864c39ce8d0b64d6a32e9e8be30f92a10a252d46a2e2
+k = 03019bd459b34133dc7331caa8976bee67f76db3a45b1793cb545e26c68
+R = 0025611bd4e3473aaea85228b2bf37eb1b4458d8166012aa098d9c1cab8
+S = 07acd38506e984fb7f1607b50837018f9b4246623dcfc9d7aceb486e76d
+
+Msg = 9290df0cc50c3cab6655f3a6de1f4cf613d9bc06ea7c99f38038369ff2fadefa57a3c7ae7940c1b98bb1d03503cc271f7a891bf38eec93c31dcec7892dfd2e1ab337bedde3e5325ed8d9cb7fa3096f6fafc3beb3a66cba66ba826d1032debfb4908cc9dded8c0099c85072daac4373fbc428fcaa9a6da02181ebc33f0cf926fb
+d = 000ecfe580a624df66c25e87e7689fc3b471d205970ff9ab51a64aa12ed
+Qx = 02ca7b9c98bb8106ae14a87d5f9f7ae1f99a5524992116e68af89da6daa
+Qy = 0a2fbee769eec313cf3c8519d3f96167477f0f06dcc470408e3f637b6c2
+k = 044f065c49bb7ff0772d628104bc2e222f1fde42aaa8b9345d324d7f936
+R = 046301f3f07922d338d5b7d82104597fc50941e4bc0a15ab5e0408f9fa1
+S = 03495e335905b4842b97f00b344313ca7d6a4ff60cfeaa5d589e0a31782
+
+Msg = 855c7be75fda372f062709827f333630acf28954a62a5193ff675f0dfeb63f32bca418f7cbdb346bf388d62315b19a592267ca407120db93d4e3d7125b867c4c4670b7a57a76f61734cead2caf2425eb9ff0a63293e8cd6defc9648257b401463f4533a2425e0024f1ea93365eeee3c6da20d25928602ec8b426f9b39f97f3fe
+d = 013c72c73358ffa168423149ecdd897f0a5f75a641de008649f00134944
+Qx = 1c70e1b6c01477f95e718f193e13c093b101e9f16024082ac699ed6ebb6
+Qy = 1f8013a88264266cb5cc5bd38e477fe0a1aa49ae4a5ff94cb58439a7c1b
+k = 07ad8a117f34bf2fcf7d689b8124e08118e28ebd172f8c220d57d3f0b88
+R = 012bc7d380192f2efe55625e39927ef799993af9451c662b562a239dfe7
+S = 035961b27e88d6731220f70e96d555f63853d14149df7bf6d24fc29441d
+
+Msg = 9c896f800281812ed57d31623d563377a5c725cec84313472b90e73f77d400f5d4fb236255741b73d46f7e5254d04099bec274db8a9af5fc7cc220d42cc172cbd3c3595c49ff74bfaab7b5e46c90855b611f74753ccdbbabf92e011d52e9ba753b83ed2a251a632e1bd5c6d346e38e743950c8ce0f394a837028575fa44bcc26
+d = 00ac60e2e70b7c4cda64071c7738f68773c94df9456a8ec3bbb468fa7f8
+Qx = 00109614a2ca27b7a749e53777e0f3ee2f57013ee83ea539ada6d98d8a9
+Qy = 05668f4b27213a8a024455b398de2cd7635cb620d7401f5deb4fa9ab2f4
+k = 00098489f0966e27555268a94378b7b8685ac610fb0964694aae9aa716d
+R = 06d151437a0aac232a472af038b0fac095d224ce0e5487510e30c31d605
+S = 0563dbfd021c1b77f980530d0120e93c9ee4f1f092a268bd8aba7d3110e
+
+Msg = 139a14ead998d1a962fa47c47ef2953aa136bd912fe940709b8c560bc2a0c4bf8f3aab30a8e21b7d5f487d30b0097e3da723f11b5cb4e8c5724f5a2fe0d68ee4bacbb85e5eacf18094d2a8ec4506cf8497836a4a905059a998ea750adc54c27c69cbd0b0c1f9743a62f3d988f3fa0a9865a73fc071f526623085a2ef12838888
+d = 060bf720052e8b9508a801340c213cf53bbecf4975faee63d4b44fc647a
+Qx = 196e37671def44b35c9e8c719130389b40c7ebc0ed5ae354dc73e0c40c7
+Qy = 0d3fa0a45a3cc5dfb61085290f6d18d710ad5d0d3ab31ce65b0e6915a72
+k = 0729c7e1de10e92634857a65a2ed75103df6bd4bf63b1ad6383c37a0435
+R = 06808491ffebf088476de7daf541bca3fd943d4c2089b848a130abdc0d3
+S = 02c0dcfff06a07e928c15a1fc2aceaa4b4dd6fe8eb67ccd4d01240f249f
+
+Msg = cf4a8e754b23d0fffc1c5c80b0cb11deeaba3064b315bc2cee96db5b9881baf90d30af4b69066f757b3020706def77a5fc1632d96bafba22a9c8cd3b52d535d941b3c7cc02b7fe6b51639d5e2084478ab3a29d2f5e0e16639fc2833a47b58e2c3fb5b2ea1830fe2ff68e571a8f281617a23d9a28db1c64ddfb1083d055030e5a
+d = 07cf3c216592febd8630a478b5b3e3a605084020322adb13ac0a626bc7b
+Qx = 08eee2ea13a08d4e4d71ecd2547f6d80b8f88879c9edfab5a675831fef2
+Qy = 05117c0d8a0442ad7b95cac1a984dfb9efbb7eb3c3866955da60e6cea8a
+k = 038de0be25c23cbde9ed9fb259cd9a06b69bf15dafed723970dfcb91307
+R = 051c9c5fe50eb81a11c8e7b2db145c6b5dbff2c51def56f4981774c357c
+S = 053887c6cc2f21bff461c9182c17f634ee2b301c3cc4af0bb1d3075f74e
+
+Msg = ae64030d4af9b36c8d3a6af0aff34e5ab201df04274691fb420b7d5c40c401ed7f3ade96065d34f2490d17943e27156e7bed83cd7222d0d5a73d167855fbe7ff6c3ed87f20986ad8bbbd80fed5f9705c6c783b423f641d40ff1f367f9648af5a79ea3cea0236997558bd9dcb011ea4dc64d61ea1e1f85b4f696ed586bc7705be
+d = 061eda5999e5a9ed4485d2a0ac5510549b76ca37df858ea5d95aeed571b
+Qx = 1642d56359cc0a5f261fdc405030d45b0d6f9c08a182d354bf2687dd9d5
+Qy = 11bf0dcbf62749a99e4b02b284aa7a6479b59b363d25319a5315423a589
+k = 03094fac5381a1b31e53f43a537d9e22ebe6bd2c149f2f69d792bd56f53
+R = 053c8c4f9a30e0500e01100bb97c00ce98f5cc6578686daa1bdbd679373
+S = 047086a88ea014f06d6345608bd0a6010e650b9f6f984b6efea9a4fb277
+
+Msg = 94a9d9cd9efa3e4ccf2a37f904dd9cab5624ec9393cf8816ea591c5e70cccd2f105388ae133708fb974998ae61d218c71785f9eb808d1c28d953cc7eed00dd9854b6b4568c5ed5ee3df3b58a1e04c64f1c87fee4365ec9aa41b08a6bae234dc43a0bf2f61420acdb891a40f17f246972afee75a4c0b249dee0fc8f9b9c8a243d
+d = 07e7e73171e4d2f2989dc024757c186485435b82544a448f5cfca05f281
+Qx = 181c8cf579d9259020461184979757b097d5a94245a2b9a1f8a6931ee0a
+Qy = 14baf1b761a0af3dd9c0521c6489f9a778da824283c94087698daa7cf78
+k = 02b57fabe6b866fd25ad8802c6b02b680c137ea9b623457b35a24d5a5f3
+R = 07421dbfa83859354345b9c3f1ce6242605094d924a4d38c7bd952e3910
+S = 05ee48a3a5119bb3433b53a625101492216421ce67fc04dacf947ec600e
+
+Msg = 4db998df7b90678b8aa4ec6233c9b4629800ad1f3e2cf8f7afcac62fc6982dcb290e44587015eca8dfe77dbb4a80f9bffe75b11e961e70deed14555db6dae47d49e73004f000eb8677c18f7e8234bf0a5a104266167a05ef07152e7acc2f0368b37efe69c0c2feb51eedf7338cf9ed398f066cf1f66bacd89ab9376d41da35a2
+d = 05f7270764a0444c7159d2db867930fdb0fb9fa6b8fc80ca02e11753095
+Qx = 06806c7164a09e11629e16608b7312d9d988acefa626fe8e34e03203d11
+Qy = 19c4200c9522618dab8a16e217beb3011599ed6cc09291fe9d451f0cf02
+k = 04a8958c80481a18c6e0893da9ab2d48fa6ae30a0f1d0512196e658eba0
+R = 01d301da51eccd15e09ce0bc2d0bdcb215a43ed13792084e2969260d46f
+S = 031f96a2f322d27d0bef23ba7c457fdc45a6e612f7d13e9277d36c8def3
+
+Msg = dbf9b8a4ae316bd2df0c80db1cb5d7038364a2634925ff957d7c03511b57d486274b2ecf191746827c325a14dc94daacd66ad86d369e3f598f176c4f0eadec7e9edd13e34043efbe0a801b75b8186b4a6d89ceae4fb250ab570d65b6dd7c04382738fe3f6f6c867a7d84b35b20720cb0036a5d81a87126f236833831d9ff00b1
+d = 0179b924afa4acf30ecbe2b3c12de533a1f9675687876a7e5e5ddc8e03b
+Qx = 175bf95ac8e768727d3b4a74c2b8a04b221247a3b8386ddf35fc39976ad
+Qy = 122f32f941066150c151b9db92b86f86a10cab0828a77e4f0d5c4026540
+k = 0210c75a63699b424585f65497c6e46988c28eff3e0977e3ade599581dc
+R = 06087e46c0677e3ca64a0cf030236583935d0dc03c896685dc6e446d9e2
+S = 0252e42b8f03b085f38c6849bd420837d985c9fe14750a654b584c4cc5d
+
+[K-233,SHA-384]
+
+Msg = 986d9e5d636526f4deb7545c037fe81b09c74496ddb8e42e61650c74b6fe348593f0cf8f8eca5e839baf62f17bf6ad96ec0c71dc44fdf11259dbfe7499157e402f6bd5076972354150723afb632799a990c44cd0a4fa9609ec4db133e3b4700be3ea4a338e8ba1873d345e80163ed60d0de274d7617a8382980bc2138b0a2a01
+d = 02c9eb4d392d7f2eef606e1861183acb1fc753d666225f0f154d9eda147
+Qx = 0d58fd7b5aa570b1c4b2190ec413fbcc9ef44d33ef191b6e23abcb38690
+Qy = 173e85377bdd8dac58222cd1d0f7ed98d73d6fb6c2eaf34819b08ececa9
+k = 064f9fb13784c99185f334700ccfcc4ff60b7f4d613c3de6dc5d1b8dd5a
+R = 03bff54e3610ade656bbe002867168db1b521c49225eb9662950b01955c
+S = 01da3fd8c08d8e17692059c669da3c7c4c146df6d3cbeaf34598d28eaae
+
+Msg = 68d0be2883598bfb1433886aff118349157708690380c42b8919859d96db069c7fde6e117a3669f2cff94a0f1b66b27b09e3f1b24d26299e11552a084be428446f3174da2e0414655bdceb38e58fcb065b6661190862db39c6545dead34a03584632e988d0459659dc7c7c78d4d00fc2aa10465cf24b2410f14e2a62173c9962
+d = 024661c89b77b2c743cc175a6130904461138ddc4ef771ffb9fc2c8679a
+Qx = 090383de7ca48f1e71a43845565a9f0c53d2c9f8c2e0f6c4ec7eb6437fc
+Qy = 1676582272e7ebc9fd56e1010a570d744ae4fa70eed3e6eeaeb0e0eda7c
+k = 05cc5b36c7300a1cc3f624e9e663861b4e296f7e7a27e8f8f0a2d54eecd
+R = 039c6f5b484411c434ee161ebeda7aa21b7bb26bde0301d9ff92921337e
+S = 02aaae737aedecfd5d53af56ef154ac6430a45ff03a3495a34a5fe0e97e
+
+Msg = f0ba0407485fecd7337f4b22236533a926cc744a5f06dd08276750196f1bf7ea7984278f789f92dd07e36895a8bfe297ea43d4a1177c0368900e3b969d3083cbe626f0e27e7ab38e185c923dff46d9ba187b2acb9cf4b23ec8eedbb8044b96b5263d956e50cd6240c66d5d96517130c743752404ed09473f05d0004dc5971ff5
+d = 0065e20e5ce534576d7c17616cd4ede3bf4f500894850723bcc9f895f4b
+Qx = 01413f6dd5349e94311f1d25e400b69c0f0ea446294eba4bbeb10278b85
+Qy = 066a05055d856621161d4f0e33dac82e5c0cd91ed8aa56e9abba9ec80cb
+k = 07377147b59dba008ed0e6b366e511f94c7f7c9088615c6d46f46736b97
+R = 05515a6bdfde3b4b78489194d39f4bb439f58a6b3c3f9e16c8a71590b14
+S = 00778f79083d11efc8ff959f607c4cee7cc8f38b855028ea248fe291adc
+
+Msg = 3827276694e413c886129c452c9a66e7d09dee84f5f09bf34e4baa308b4627e096c7d45cf6ef45ba1d9a4019a60399feec10fa80e333e2aff1251c85ca48574d9b9e1affb9666828dff5afcef3edaf5e8cae823505a0c73afe76c1bf130399fb06b092ba34ab0ae15ac6c682f9ee8479b065ce75b57213b8aae0f55e4e386de5
+d = 014c85f66fbbd653f1e4e590cffe62c343ba6062df4b271fbd02e5d42f7
+Qx = 18930b4a59a1c0e92febe650347c49e29a4e83cb8c507e30ad835dbc94b
+Qy = 0a237bcd130235e34b4439293f15e7a3913d659089e38e5619fa52e3c0c
+k = 03c1f8d076fb4fbea91a97800607b2db3fb5a45149c0d30dce79f07e963
+R = 04b9d2c66d8cc55b64f3f62dc629ce8e50ae0bad8a4d14e8b6567fc87e4
+S = 00b9dfdbeecb061a455dd052258f3828d4b7174af972c65bd0043a9776f
+
+Msg = d1afb8965b48d66b9acb1ece674d9548f83395275f2d8135554cfcc7ceb96450d850dd874529433883709483d0743798db5e0dee955a4f30ba328c7934b8dd9207f3c336cf89141a175ebe23d2faed629eb4236a8aea8300604c3eb7704512f240fda66acedf1494a85058dc6a31bf9531958c332b93cfe5545046876c6b99e0
+d = 030ac7a78593b570b29f6d3d267abb6ba7e5870ee1c8ee4f1ab2f141051
+Qx = 0a409e90eb4314f95967607ea3de9817a0fdb439cf406135262624e7fac
+Qy = 04b1dd719434e8dfa5861887736f32ecd635878ed4b9e290c423da09059
+k = 027c4987ff872fe499039b4432dc889960ea8e3f07be42e36a5827b3964
+R = 06829b5e02b5849689d152ceacdddbfa8f68d782b3ae8da23ea48b1acbd
+S = 03dba0d2b4400495ee098325ae4450b32b83689349e82a69b799dac2cbc
+
+Msg = 4f95b71669fdfe5dc46d4b951b085e099de349fc740535175337127910acf24e9a0e4b2f23196ad23880da47b740d77d74fe9bcfdcc44dd7d8d1a181ac290de5cf4da22d5034cda3d8020bcc776dde8cef1786c9ce4d2c2cfb035da61406af745efb7ef1a55f2eccc5000319cf1d6380963025dcea641cfd15a3106751fec286
+d = 06d7516aa040f7d559cae248e485834e8d9bb608279ed4d4f7e1dbcd2b3
+Qx = 127a92888fdac8d4ba9c0243c9aca516bcb431911254bc2cf51883623a1
+Qy = 0606c30fbb9958fb1140643f32c5dd582c2319f71bff197d58ba3e598bb
+k = 01104b6ad82327b0445e75cff0efa1281d266a9dfe4019ba2ed22dd6976
+R = 01f247b2850463e362ff8879054d3459b2cbae84b9d4bc005a2ccf4736b
+S = 05b3dbdf04758d546e54c43ca5973bd8ceba646a4dd5d17ae5d2f8ec516
+
+Msg = 2ad9e17780c824c4f2d1e1cbf19ab85638f2f71cb4fa3518f08085b8b358f54d4f08394a5ac29cbb3cab828c5f07f41eec51e6cd61a5f2cf44dbfa46834370cebdeb328fd3bf681e61011b5c2ebc8945ac7a2a8467606051008b15c89390e111999255bfe28634ce9bc2850a2b55a4af1c4c2f94403c78aba1ebc87386ab7b32
+d = 0137050d7b455f43a8dc2516cfff5a91062c1a2727b27df41488f3dcf18
+Qx = 15ccc90a5f3906469e3ecf7a70c429f5b50fd0ce74065d41f1bd6dccc1f
+Qy = 0fe5611b8b1b35a907bc188ad2b1fb7507d1043d148283911af3ad782e9
+k = 04881e879d7c76eb2ee61fe1844567316d7efaef047b96979e6dceb7858
+R = 03799e90bc64cfd7d0246a7fc89a4d8ed0399277cab2af40fa2ec8196d8
+S = 067e8728f4d8398e4e1c25775620865bcc2d4cfe635a1f4c6b7306f6d9f
+
+Msg = 958773c37d3eba003aa5c489f72118b3022c52b93399e9d8001695664918b86893f4922c7b6e55b1855ed0fd1d8de5dc61af403ad660fec60d7c44bd0102c069957ed804d0d416facdc1a95355ef58554606579ef89b1842f1055cfa2ae118abbc485356824cc09dddb77d0671cb3011b33bc86cac526e3f6bb3293c7bdca1ff
+d = 001fd447b33a2ee3595b9f885c290d241422afdd74c3dc4981955a7e9ad
+Qx = 0e706408803188263cb149428c60de57ac757f0776e5b27a2d5a859f58c
+Qy = 153b5e13f17f0178cd90427f7d608a5659b9e03effebc89da65d59698d5
+k = 0339300c00cf7e8c6195ffb71e509613018e6a417782e4f52704026a510
+R = 0227c80e36e3571e1c783358c9ffed237b251332e8ed05a8d3b454c53b5
+S = 0679a32cee8ae001a18d9a9d0ed7e99e5ae67ffcd54de7b48c62e76ac8c
+
+Msg = 9cb2c496b1bc7f040228571e005e7e936e48e8f469e295edf914f5648701249a20bff6b98b5e862603dd9f12bb71c160aafe9df02e2e383e9b8a9a9d700f4425ce408feabbf754be543f52204c849fed6c9d3e36e03dfbd9e35c18d7bb2295f1c484a66e73440a0a5aece5fe80b9ade9321ef18cde3eb2db15e4b18e788b0441
+d = 06a061e10b4a6e7001d95411cb31bdea9c84670a59ed61b14fbbb05c8e7
+Qx = 00ad2b726b805919cabc90d058c78896d2dd8a78484c1fec5bd5fb0e07b
+Qy = 07e048ddb487f667633d6d030338ded21a2ac5f65373ddcfe1e4a3424ae
+k = 013b4a86b70f0e4de6efdafd7ecc993f0d6f231b3d743ee5adf82db1515
+R = 0541c2d3b2c6f0655dd415e327f0ef07b03356f8047117c41e704169698
+S = 00300f45026200b8cc84fd564778281bd1d7e03727c242a249d9ad33338
+
+Msg = 9a4bc0a029e97742ed3bca207d5912cb568e4403cda106b00247520ea02008b14c041b8c9b976294252da835f4ff27456039d79d90315abcb0b9b6958a22352672e229665457ec79571ca80447c8ff2a86e6af3dabe7427c8bdcae65e3c6746a56079ce2cf8d22235180f46646a21cd9e86032cfad874cb9c67f882fb037a13f
+d = 027ec31ca31acb4d2fbacb49fc085f1261b0042cc755cc97f9b199e7a37
+Qx = 1d521f7abc2fd3b0a10732ed641cc1b7fdd7b49cf61909b215220c5253e
+Qy = 019e9095c67af1b89ae6c486c4f9889c3f2994743eafe55bd9eafe438d9
+k = 0151aa44fd97be14578d68f87dbb884c960ab59d950c392e607ecae6bac
+R = 07be427f46958538004186d52aa50a0f83d184a9d2f4da2974163854eec
+S = 029d4ea73ab5b336ed44556f6944e734e531a5c71dc6c929e7253323906
+
+Msg = 8d89e22cf802dc68ff22d43c436c79311e705ff6fd845e77c880f399f403e6d5e9e2b35511553c978171189e288cb2200fd95f84ec5ee9865c0eb9190aff6dacf783ef200e82027fa992741876456472bdf27f2bd8ee55db15408c957a120eb64cd24d299818726a73fbb0697eba726a326719765735b37a2dcff0c853c906bd
+d = 04c6f4d88e5a4f4f83196f2dda9dcf2a66eaf94d50c851f59bfcea1d876
+Qx = 1e2677c1305f545472e373615d195d1f7a315f592e26fbbf44c42558050
+Qy = 1638140f48bad525625a87d0e537db5500f034e71e60e8a8c48eea04108
+k = 02185d8ec6f35d5c3f965cd00597d93caf45bbe186d4128bf877ec304eb
+R = 075199f4d8af090e4666754a7dac0c1599c207735c0f54c9f11e305727c
+S = 008cadf59a224f812d64c2f492e7ad4a923f3463b878dffc75eca5f8fb2
+
+Msg = aa1bf5a79e5339fb9ef6c2817bd95725551d064bc5064d6586c5a879901adf808dc2ef7c78ec3b434b84569988db58b5e8e9782b1cbc2cc7c9b68e66f32d4ac4ebe7e75b345f654c7b8a5e650acc9f170f75b7aaa3957cce248cc69cf93faf8d72abc6fc1cfa9ae2d18a7b31ce720147e88e84f6563b2197882fe302449ac5ce
+d = 01aa169ea84365c22981bb766bfdad27e373440850569957544b0f9332a
+Qx = 1f97d91302c70798e2278348e36bbe01587e0031ac3c422141e3d4c1504
+Qy = 0a95108f6b7ff41546c98f4ea4d1b587a3280e49c6cd0d33abdebf9a1e7
+k = 03c9efc0f72d88168c2b1f7fa1c6e275839303c2bddca136dd19ef446c9
+R = 0639d1a1066465b4b2f443cd9677cfe3bf5bb33e3e9b14cab2d37f4a859
+S = 04582792ba78f782f112711ceaf36f5f0774b92a6fcaee327d687658835
+
+Msg = 475664d5e22cbe0da0d0289ca9a666a37270dc71c81cffac91f6229fa39315c1d55f7e0a89b6a7a07df7d391dbdf8fb7af63d2da46ecc3b60110dbcd842da97f98d2b67f562b0364ef8e1c589519024177c8ea079794f271f6d35554c0e9d0a39062383c95721b72f4e74eaafb6fbfbda02cb670a7c4c94f67b8ebc6442e84e3
+d = 04a665b92c0c33a3f8b9eb4b0ec061d40b603de36c87096455102ffe57b
+Qx = 0f0ac5238553f0cd74e6f34f7f82563cb01138e5c9bac6d5e7b8b7ad4fe
+Qy = 1903e9fd8a5a2aa32913b18bddef20667061f919f8d61a5b3c814ba4aab
+k = 070ef25950a795b5e22fe4cf5402f49029c5d97cf9f57f0806c0bbb5855
+R = 01248dcf1993ac2eeacd062f853ebb4b2072357e728f0589258399ea95a
+S = 069800eb2e2b3a9162196dbaaf67cab4ae123ea817f223acb6e889f6d7b
+
+Msg = 9e5397d94465390a82a3c07e3ebf21b515776d18b4463aa5810e6b2f96ca61e92d13e034fa853c3fa45411f51f79df6f799a2c6906e6a5b7896a4576a4464f9e0be2b529a43e1f503fb640d79db6b68f3a3a7deac1b5832fbe86673784ff6db1f8438f7dd332cdd1e7ad9df8b6731aad1b6a72bde52e6bc62d80b8da57822c48
+d = 00531540d94823e19ab2b95cbc6e7492e1effcbabce875de6ba96f53aa9
+Qx = 031ba225249916a5380235220b9657162eef43d59ccab507639e19bcd6c
+Qy = 062e85d61366a73b62255c741a065708701c8fa024a15401a4cd58640b0
+k = 05375df0a23646e8033ec9e3ad269e7167a663b97b4f52cf18fbb5f50f4
+R = 05bdf7d643ffde5ea191553a9c99eb42fba9a8b6e2013dcc520298d224d
+S = 06cdd9e0d58bd4c5cfe66589ed7c7d15331f3e164dff562b6971af1a41d
+
+Msg = 3cc4c4192f317e52df6f8cefba6d4cd823c942aaee11b9a0ef5de5c2d181073b7085a55805e9554def8dc13eb978e7396044d4f4a14be2c7605998c062095c929b9c23b2b1b2fa73dd19a0c0af44ca4789f9841fa62dee8a5f91b3cc4b3264f5f67334c3f0772b30bd7431c3fbbf1f34318ce1889b6e8a76ce6d42079a451e56
+d = 022a89addd8b85809e87e0aa2c038593ec277054842854de1197833a51c
+Qx = 08e760b282d0ae4eeb2fcbbfdec851468fd8e04c4dec71fc2d5d3a98a13
+Qy = 0849a56b9b0b0a1ede6b9f9522685e7ace3baa57f72709aba705814d138
+k = 05515b025d6196ffdc8bf275479d72b29a752eb3e70ebf07d4c4e7bf74d
+R = 041902f9b7bc81d3a88066b03e4111ad8ff4d99dd868d5608d1f43eead4
+S = 059adb96af9f404d2f04d89fb39cf38ba5689f47bda749ae9aa1ecb097a
+
+[K-233,SHA-512]
+
+Msg = 72cdef5bdf710978e0aa334b86b8ff4a58630da314eabe98b4d611aab56f55c526983d54d19bbbf9ddba30a84b18aa0bae9f9503e9b222f842f084db83aa39625403213ca321cc0d9c8a136c826e6ea4ec108b913dd0a9ce9d5b8c7e3af53c3876e56a2037ebd6d99f037a097111c837647bedfe4c494e4288ed6427c15969e3
+d = 01df252a11ff97b4421b3a2361db94e908e8243cd50d9179f9e03e331f1
+Qx = 129f011fd5fedf3526f0437ae800a110435db907af60e16912d58523202
+Qy = 08026ed86afa7ec80277f322dfc8cf693089968ed9ceb8c95c930415a23
+k = 04fce14bc83be6f862f06680a32e9a51d1a569fdf1d9b10a89eb9fef4bf
+R = 04d7b8d19dd9cabc3c2245a9d2c8431c3151eeb6f49676a865e78c26c2f
+S = 0373e69da1fe35ce41ff344447fa7ffe6fc71e28dc68244372745739fc2
+
+Msg = 8e4eb88c0b2d525b2c58b8e00f32def90e6dd382301de49e0ac053dbc6b61afe926d85193e2c4948f7402a3d7c614cb2c58e060362b0516a1ba4a7425f1b3d09aa20d4c3c8993a387a3248aeec51e6efa8f558dbdcfcaa13ee08413227c8351e3107e9a3e3ac124224aaea91bfe50c11c1c8ae582e718f50bc5d5c06076517d6
+d = 01d7125c299ebd0dbcc050f07de931c7ad0450af590d0a2d0228a66ac5d
+Qx = 13ebde8790a113bdde87c11ccdcbc39e354b193d772921b86657f53f74a
+Qy = 0aae910b0e22f1a2505f55fef2eae47ab6d47db6e49190a5469b4b6dce5
+k = 0113d1737bee59f9f477f71f77a0ac1aea86aa67002c34a1b31c421cd7c
+R = 066f9871da9a22f07c9b2a44fb6c01ac74ba17649cecc33b729afcb488b
+S = 037fad90c288510d0cd8e99e5d930f4fe197df779dfd6088da48986c601
+
+Msg = 370fdd80f330311dbb3959666001bba61cdacf20f72f78953d946fa6cba02d24b5003f5452d535609e489b9434f192011f99f918defe877d51349870e7e75502f61145f7c261dbd2a0840926d824ebe9be3c5a77a3a84340aea930378367ed3615a47e3f792c7773f83f91ebea718a05fc62e9ed1d78629b2c27ae44fe8f8d4e
+d = 021238e66119844b146d40e48341f522f6ac2f9c8a0b33aaf95a3099a41
+Qx = 1dc3ac1ecb670f867337b752cdbf48bed9f32589366f7c6ba7424af1d66
+Qy = 1e3a38ded8148bf45484ab6b77e0beff759812493347e32d2d54a322a2a
+k = 03626adf8e70506e74ea27ce740f7eed1c8b37d50415be6a2681c67ad2b
+R = 07a9c9056b51f1fe3e7733c6f54ed96662aa7f5a08a961f91fd6d0276df
+S = 05e7600e9fda45bb966fbbb5a9404af961058a128824b6d84d9d47ebdbf
+
+Msg = f86c4433787c3ec3cb1663389ccf53d62f9425274ccef05fd14b1b8fef676208867764eb98d16d006ee6ebdc27b8d9a8ddd303d941fdd82b630694cdc698bbe6bd524411907834286c94b24ee199fe6d646064277f244b7df3ea2d9d52a9dc6a33d7c8d6dbc919da0fa987a67621ef0829e48310e0ea2bb86fedcf4effc0b94b
+d = 015e1bdfdacd87c42ed439f3e243abf27fd42e54f3ebdfb47f60dbae5fe
+Qx = 0fb7fa51c1a96baab65fc85c3b769ac84ca7b63a1fe9f507a2ee0c49395
+Qy = 05d450aed449f8f1aeaa9df0131f696c2bcd4528808d2f52b6a73f72811
+k = 070ca3f5dc30c70e576e2d2b30935b05b6e68598eeaafa1bfcb9e156e05
+R = 07e3cdc4207456773aa52b44156801b316a7ac850b3a9e717a9ae7fcdb0
+S = 07ad6de3ba8730ac887f045cae80fe2fb5237a8594e7125c4792d478594
+
+Msg = 4117d593aa92e3eae1124ec7482737cd3573fe5f0f2a5051a7ce86946a2abb9e47a0c6ea75b262689b0b486476d2ab09a20efc2fb921419b1811b51a2e15891ae9e45a17ab4b96c665c6c423fc00e2d66df5804a164f0f3c958df6f25d7da6829b1fe162a0a8cf130858c83f3555d6ad627db70cb41303cc6380f7b3fed2563e
+d = 00e09410548c17bbbf28a68c3963a52d39743a4f1ac28e6dfe7a6ede281
+Qx = 1f5f36a21a3b7fc5ea37528566da695922d7d9b7e6800af9c1a00f68242
+Qy = 03df4e2ba0c8648cb1fa19663f31786b850e6b80068b8c007f41de08608
+k = 03c0a2a4bea270eaf66adfb297c0e3213254cd87b11edcd90cfcd6f3104
+R = 07b684e337d6778f84bdb7a6835e91877b41d6af4b76311258fbb8339d8
+S = 064a0c22057a858b153ecdf4d275cf5523dacafdfcb46423b5613c85691
+
+Msg = 882ecaff3ec8f4023df5397167f238869f78a5c499be19aea85c7486e73f66f0e08e71cf85f3f1b6f6a70796bf46a18e6b555a0a87c2088640ca73051b3dd59ebfef922be0372208fce602d8001681297b285701dbbe24ccb42541b5db4aac1a1c7f407e11c83db15b38cdbc25e930fdc6558f64d9503e214571a435d890169b
+d = 049f5bea6e72d98579b78cb07d89f64503f8759dd7a73cd73713c120428
+Qx = 0974dcd68cd85117f363812a0473e972c89551e31c74c8d99f1073eaafc
+Qy = 0f306c9051cf3b84803307beb3dc0d34a9758a4f535100e846462a49053
+k = 022a5564b468e706762e3ff934aa22d9aea0bf2b116b61182c9f7be19fe
+R = 02e050afb84e1b0591fb64d46dd7d4a939552d68bdb4213f16c5d7ec5ec
+S = 063225df0057d5368b2e103eb2181ff5760e6b2a9c13c83da042722c3e4
+
+Msg = 99b3b8f876f8359bd6369ce84f9261581c52d744b90261a1427ab9e447e6d833b6b3e89af8dc770f1dd55692d01c8bbc4277a729fddfa7cbdb2ec99133201dde44ac691a77904ca816feb0a1aaacbb9fba85048bc63d73506eb908ecd697caf582747051a3a38ac8930c9a4365f407ed94ca7f2d26913c53f4c010c7ed9d7ca4
+d = 005eaa818690d1ca4838f0bc667be5721d178c3869884260fb230277c3b
+Qx = 1f7b3b50167cb2ff7482240bade95f2850a02805742e6e29eabf7f9ad34
+Qy = 0f8038a8cffa0f798a01e333251996662bc3c0ee56d94c392269b63edb7
+k = 064d518f7b8c87325d8edfd42a52793d87ef8db283606dd676be8584562
+R = 07128123004a515e277dd5b571e31bbc877cc966e27ed5b2ab2c16e881b
+S = 051d70485148996ec30f92097e4a12b5edf804e03e312072336bd912268
+
+Msg = 8c1a83023930a85c5b2f9930521b8b8963d5523a3323d87f862a17d3505ccee01246ee1029b8b8c2b608772c4096d1e914cb398f027d91184a8e94e4feeae121eabb504a2a35c8bc9294edd15ddd979946c14c792ad787dc2d4deffa284830fc90b3f8c0ced6a99fc6de7c41b9ed261402a6b3d702ff86a9392731ecc37430c0
+d = 0603d89cd2f741d734587e77554fe6bbb1e5739d5ff73084d4de8ed69c4
+Qx = 122f2b7802917e4164ac2f54033621c78cbc7040217e5ded6b9217f95bb
+Qy = 1f867df743e73806957066c2ab45c04bf1af158e146a9d1eda9e974e0d4
+k = 076850b8ca9e454bdb320da624c0dc63e14ad279185e4f8c9e49905666c
+R = 04bc63bafd5bad022fe5db246680a0a0ccd0b50ff50482d3849c92eec7e
+S = 07b6d8a8446ddfc64392af0aa1763d45877023c0be9ec78db47efd3c366
+
+Msg = f3c9dedd7115339dd3ede7d8d06a44de66bf80b4888ab7bc386cd40a92789042440a13d2cc90dbcacca5feeec1e0e3c51724146e2c4904ed6b05c7b4e9b49d7f458ada695c5d2fc36f1193329b87c1268aa38eda9151430aa0bc004e5d2a61b9390accfc699f2efabfec785eb34f52b1beff1e4c5492e922acc348667d2a3986
+d = 07977b3aba53616dac27b4d74930da23966a88ad98f1769674789c0be3d
+Qx = 0aa61b4bd2fa9c61914ae306d69d3ade7d6cf621399e5791dda8a054dcd
+Qy = 12e8d9274d5593f5074c49ca34a7e2d64f9d9ccdf42df6087134b811762
+k = 03b8ee56bebb59207e107bb0c16938cab707e425f38b70f0bc918fc1b8a
+R = 068502a3e5e51f5481aad31eb6614152f4957eef1becfe3a297b023a94c
+S = 07b6b43be63aa79c10876179703b69caf9b03c5401b999a3c5be4737999
+
+Msg = d878c4ee0bd6c84652d7f9e68df7b90cc78776d8d1b60f3e4d7465032bf401f1527ca7bfd4a3dd916e13e93fadaa5e5f20c9f47d12f8fc922a9a3aaeeeef294c221ca1adf7df85b888faec8002f17ff202da1be837827619904121167bee2d2cd694a263d9a99062cada3399dcbfcb283597a96ebec129c65e0850ec4cb4e2d7
+d = 050cd20e7eabd29008cc977d0a17e1195d79587b8f15ac2447e15daafc0
+Qx = 01ff23ff4ea1f30663b17d8f1c67ea37b8c5df7009d0c0301db483803a4
+Qy = 0ec6bde92921b83d4d84be8a67a23e1718e575101b93d9a800550a20e7d
+k = 041ba36d2e810e47c3de583772e9b5908c257b2aec232d855669d4dae2e
+R = 079e96ed1dfc4e31774159ef311805b5f8001203cf37a72921efaf5cbe5
+S = 00b8abcd623b17357f65ac365301a8823365ab948ae3f7fc6a4a0b8ab5d
+
+Msg = ac3c118cc9cbc8eb3b74d8ccc9ecbd81d1996fb25ca43c8a43bffeb244f722b93c9e969241d45d5b81fda0b399f1e3623687190e428dae077e54cad1eff75ec2f7fbb9434bf716833421bc2634885677579c237340f76787b2eb19b446d56c0f2206099b81493349f4db0ecad0e2dbe85dbff7d7070abb3d3b12ef0cec828af4
+d = 02dbb24fcaf9f3cd5d50d209937f0e2d134fa20ee3c9c2f1fff3dfbf302
+Qx = 0a07240c52e385ecf75525201f9810859123bfd8ce04a5e8f4dc4ec88b2
+Qy = 09bd811196ca9ac45b28031b9f65f9a5c4ec497d995f7dec6eb06dd2874
+k = 05785beb1ff70c7bea89b1fa14be09332ef94b09eebcc9fb1150bfe0d55
+R = 05279bb1b1ad8174e88bec4c723d65eda768c1d08d1c64c332a240a284f
+S = 015a90383c2c40ddcf721067b3435915a843f9c4708cc133fd1ee53f442
+
+Msg = 700313698cdfdcf0044ca07bf9e5f0702ece7cc66e35decb28d5f8cb7e7e5367a95cc1728a90cc9a53a2b5fcd4702028b742538e9b386f5d8b4a2411579ed9553021a95bd00a73f03c4184a6145aaa367e3af76659d677fe7a2e98f9ddf4aa20eb8d1a1db72c3f5590598801be7ebf44255fd7376d89d998b7068bd1296fdc38
+d = 0047142197d3d43fa46545b547968680ec81688589d1ec8d7c7e90eb969
+Qx = 179450d83cd6dd1609830ec78011143eb64d2d1509ed1adfa085a58d786
+Qy = 03ee40673ac564c6b5732868d0f8a57727150a23c484228890d768dae54
+k = 064f8892245a198c9c819152edc168e69dc7b562ef1f54dcc1960cc7db1
+R = 0293f2f989fb6b6e7cf304faf3f63eef61ab89a626cf8152e15f38bf93b
+S = 04948643075cea6413b1c88a9bf11aa176611f56d027f2b165d00d46e87
+
+Msg = 0374673e1a685bdee55504ce3cd333f70084dd4ae685464a16924eccea34531663fda60229166478b30193459a3113253cd6494dc26154156252dc6e822552c7c04d790eb9f8fcef2ea8dd79e72f881f7f20fff93cd73ad303c0918ec27c6486c4da61f82bcd55422d16650cc68bfd4b0132c1e7075bbf17dad919095860d445
+d = 031352b49ecde5434aac05f898e6ce4337304845d748f114c14319fe97f
+Qx = 187ae6bc9167d9c69ce5544ad650055cb9a4e69c1772322d5722e68e7e0
+Qy = 0042187e9d11a921adafc694b5cc8da9226ddad1b65f764274954b17333
+k = 0761189e63fc0c3b5db92b281e5a4bc0d6fdb30bd14f8e69ca85a211bc7
+R = 0453560e6e725a2bfe0383884ba3b3dd0816d8522d9e0762f781f6b6340
+S = 01aaec4bd98c765e4830de6593280779d1222918d4acf08c8fc3d0aa351
+
+Msg = 8b237085f135d6e94592f8d855ca397c8c1028236a3b412adefdac888245874f586d06950ee18118f751bfe26f4c31465ec34b578caa44cf1b7109ac4f6eab7f97ff9699b34271df035d3bf58a2ed4bcbf7577cf8e5792b1945ebb9389b680baeb8518c8fdc5540e192aa4fde0eed0d7c82be2e362b286f582d65752c8db7038
+d = 0176f124c24e4420f6e726a6ca25f09dfa0c5a37e5bf879e7bdd36c3b65
+Qx = 098c37cbd44aac5d5c749524b840fd849652349fb3e02cc8f8fd0a23790
+Qy = 151a9a88da407ae41e52b3dad1ea6031c7a36bd834007c0cb1e2c2f2f0f
+k = 022e299985cf289f2fbe2b1b270fbf12ba818cd2b506f642e659cd541bf
+R = 0686ac0c09f90a077cb446c910e07fdf23e845487d0333efc65b9b84147
+S = 01688b18cb42082bea69f18511b0fd9fa35da83d738763cf13ef92a119b
+
+Msg = e3a086ec15574f7017b3cd5f5a47ab7a73980f11074333490dfe9f8ad8926f9ea7c82271aaa74e77133b1025b0b22a6900fbb71251bb6549341a23d194e79d03462cdad52ee0d1b6f5d0d14e1136026961fa3467ccf0864bf7ae3fcc3b68cb35df7324bd9bbe58fc8aa9f63c19feedf19d935b71bf5981c74fb2a487f84e453c
+d = 0755c48c3dbaf71042c58cb137f3632e3cf9d90b7b9a58fd378feef3d19
+Qx = 0bd9a720553afbfc5349e4a65a21fed0444c30304f7018ec1ff6fc8d1f9
+Qy = 109a1d6b9cc4fbd0e888d0a2b6883fd06a5da347c0d4f7882fd29eabcf0
+k = 04fedf8785c6648798748504b1c9b6a066ab6606bc9a69534f93e908f4f
+R = 001e71744a1b683858444da0d270f43b0d5644424f2b38ef48a639685b3
+S = 07ff8199ffe723abacf1947a828e8596dc49ce655319087e4aca6ca34ee
+
+
+[K-283,SHA-224]
+
+Msg = ef90f85fbda05e693006e4c64e1dac56223becaf0890f73b5274e6e289a5a1de2c141b825c24d595b3fd18ca855b5c1aa60dac6b5356275b11be670692cdbe5f282f93ac7b2e410a96cb9e9f80defcde98f3449f99e192bfd62040421a0ab8f99acb85369f25e5efbf81439efa8a5e1d9cf781355a0f47b037b09fe4086389a0
+d = 1e846c830a8ec04e8572d1a9d2df044ab47352fb346f67403a3bf87243871b164511c53
+Qx = 12e43e20941f2641154bb66a56f2e0428a7ad22d607fb8af658df0b382bedc7d5ae22cc
+Qy = 22f226cd65052071066963b112aa302973fe2b5fdd7bb827d13da7634dd2fb9e3852ddb
+k = 03a76f87ede2b5d40a0f10e15e90e29198fc3a03943efea39ddf7afc37ed4e18832af8b
+R = 1be2c776c707098438fbd0561de578e4b9449f955a25626f2fbea257fc578ffa1bbbb70
+S = 1aeef69983da1a535b10a47e66d890c4413c7a8cd6a2511a1a670a4c573d4808f46e23a
+
+Msg = a3ebc17c867cc9c7c28797f6364f6574b80c7ec5b2d8e1542a6f5db8568c15032f92cfbceefa3fe4ee654f690b0455ee5d38dd84bb8665ffc1ff8c849bdbc4aa0ddfdbbca4eb37972fcbcee8cecc1aae21ec736ef61781716b60247b7551ec4e552d0b59a53cec5964c67cf7988787cedf769eabcc9cd5243f58034d96f0e43d
+d = 101c5ed48231a56ca0ea85eb45de0e395e6df2efd4987a226ae36489dd8b2dfbf7c465c
+Qx = 7011260f504d809baefb54af48c890f94fa5984c8bf228baa4b6ea14d46372390d1a8ac
+Qy = 2bbfabb680659aa2611435c4058ed773467a41cdda8250f3490e4f491f1bbae452c5c36
+k = 12a3c7f0b3d64614ff97133873d75c7c1406e316e8cf60d22139dba462055baffe6c8f5
+R = 0a9933496d60716a39e1c3f3bf22a7da546eafebef80dc6f25d0c109ecbc430fdb3e80a
+S = 0be56197a0098b022a7914c10f40207da58403d6c7d04edaf7efc96de740cd71f67e0de
+
+Msg = 60269efa4d0ffafbbc655f6f00578eadce7fc0a7eb7db923dca49b6f2bf3e13f7f829cc6133e022c3c92143c075ab9ced0531a91e6e79848194ab98bb852f40c84e7aebe71fb8bc0fd1f97ed5bb6bad6783d8dc048df42738e841d978456e055e1b8a781dfecfce2218701c7af77e7894ccac5bfff360aab0b6136b978bc39c4
+d = 019679dc589440b11f82b3716e5b2a2bd42c3b1c83e88a28e304cf5148877faf760b4de
+Qx = 743ae04e4b07d154ca0749a011c97a31ac68d8e1da3491f331136873598896e5320ddcf
+Qy = 776c05891c27fd912267ac166bc9acbaecbf80ccdd887aded2d7b8c2a4a5d139833aad3
+k = 099ad7fba5284e406f6cf200a39e398aa0426448c09b95e691f653d6096a63adbd39965
+R = 0285a82340d9a6d96ed9ad0fd0916216fd20edf979df41a55835ef8fafa00d242ef6f11
+S = 0a8548b405c171d2a428507f7adda4944bade7cda6dc580b1d3f94e15d7e10f0a08e008
+
+Msg = 59d704d5b1f3a0605f1497f22f71b8f45b26138bc86371f00a4517554e7f6e7fa5d35189fc656ce68bd2cb8510fa3e3c3df815dfdd749b2b6ac997d443f3954c7a927e138b579801ffd035cea90840733e7884ccfe43d8d3a4a26b430673274aae312abe4ac1e1d7c67b73580fedf2d8de46572493c9205ebf0e8b4d75ccc88c
+d = 1703c21fb1e09f8947e12fddf166fda6f685221fbd803d75a0ae377a54a1e494e6c5e7b
+Qx = 767564e13ae544dab22c3763c5d330a5571e07ff8f2f5ba3fd729379709b1fb184f990c
+Qy = 27f9e5efbd1ff6ac53a6174670eb463b12f70a603354e25c577ea292b13b8e5f022ac9c
+k = 10d875acb4d0dc211a82e78c0249e74de16768003b53830bf5648cf911fef6a57f8f048
+R = 02af92243b9dadcf21561ce32ca0744810478f8d5be8e0f83d9632ecd8e86ff467268b6
+S = 1f6c50fb3bdea228a6b623be9e2ea2c371dcfeb0e604ef1029b6766c43b193d86c02f27
+
+Msg = 12c8fdba3bc5f68e13f7ff8e7bee876fa68a970afc6924314dae0c2482763ced8d4752cec29ea288d350acd8a06c69289ae41ad345a1b88bcccaac903f2bff39015c289a8ad608606bfd65270a7bcdb5fb10c89bbc2d16dcb91fc9735d66103f6b1f3575622cf4d8209290315b033ee1f79968939410f465a2d37add46af2d59
+d = 071de8eb14cbfb88e61b908990ce08b81e624ef4f2cd9cdf3dd7ca9097d5ffed9ae9a71
+Qx = 136d50e1aa8203a0cd2c2d545b81d00b95c6b43b74b1fba3a6402abf756d38087affd49
+Qy = 46bec77240de7bde85ca4345f27c6df341c72a4eccd2cd495e86376c183ccb34f271cd6
+k = 1d80734927505d8d4818b3bdf1aa2e5c557e5f717a5b3fb856ca9a2161bfd74a130ee38
+R = 07894bf10885a698899b118f57e7da22222e3d187a0aabfb99fac0ce0e134b6b44a5f90
+S = 07b4a87592004d6ef8345415064b4b4672db2943c7e6098a9e6d59ee3324847e753703e
+
+Msg = 26013a3ddf687bb2f37d9700923906f118d5cba5d8ed5113a0e3e84cff00918125108f74f4b243e351aa5d07fa7c6ece29f5700f23e50286447883d2a058c3258a12e4ed8770cabe627ebea7ef6e8c77811ed7d9a19c53287093e39226236587ddbc63b7ad5e7ad9895c64d1d03ee432d45a067afe27d4cca920ae88a7a68db1
+d = 1d156eb15762ed00c4021884adbfc2426e910b18a5bc474268196f4b74e593a8f38702b
+Qx = 0a99b45860615d7caab2f4e9bc01196a61f52f95c6c7fef615a4746d48553692d5fcf13
+Qy = 56f81a0088dec1382f8a3a863901d3443c8792cd13ce13a8f63b02d107b66d9d23bc492
+k = 1999524ce9525d85b562fd13634fd9ac50fb76d83b9d72d6976d6fbc47af7e1f354eee7
+R = 067748d49389c9b87a85b518f84f41b18f52569ba531985b8fe5e1f0cf9cffa958da3f0
+S = 00c44a583c704f69160c6258332f3121b022759b163c74c7c96058fa8e3a9928afee948
+
+Msg = c4dbf70b9a2165e7279122460d05ceb8e43e03fbe2ae7c314007fe2b1d8567cac727a10fba5cbead0ddb167d387da8e8f3d6bc0ad851cc32885809d07a776fd4a95a979fe3833610af89df0f454d9edfabe12495a118fe83add5eabb2acf54ba7ba7c4be20fc77478c0a0f0726c4e60317422a612a234a7567648603b63f1c12
+d = 17d6eb1219cab8577168be86b61f372b27ca70fb1f1a767947895c185344e966db17aea
+Qx = 65d8e43a290a6957230501509b95a208a6c37ddcacd1e882d97c73c38b2a256caef5e8b
+Qy = 02169cefa6ce170ce20a0b5463f5bd146224e0813acff304307da88830b0777b86cd3d2
+k = 1519e37a66b4e665b2e3e59b8e836869a886c879aa1ed47901a6c8a8f365efbc67fb410
+R = 1734a8bc9a13f51d921a297bc6b2d38610c20b32b0adfd5efdd01a4db5084f3b0697904
+S = 0f9f00b25a33b166f09e2a819dfda80d87f6a2419a7b4162e435ee02c0fc10a669df6d4
+
+Msg = b1d53b6af1face9b59af11c726b0099111d1adb3666209ba46b1744a528ed0f72be5a1b82423153b896384faebef0362343e2a4599803c08b8513708938aa8a498145fca1c63ba41aff06d1a18aa2a045fce7fcd7e5552a2b98d0df97b6876f06a9cf52a7a40fb737996adda97c3cedf7fe421235ac6951060eba9c0377e72a2
+d = 10ede9be6615b3b2a294d67da78127ffbf3a15bdba6f4fd78be7a60415b5d1a097c0cff
+Qx = 6418eac385ce94c1982c216ffeb0b26f9c061ccdfd785ded75efc6a329385898331fda3
+Qy = 7d41f9cf1248a37fb8baea7f3545bbca707a903966019ad56e4dc810b6863e243968b48
+k = 134ac4de6ed71106d11fa736960eef2873223aa87b1c5bf5c823de6c78092cba4726ec8
+R = 12a37587ddf224faaf8dab61210310792d4ccef650c98155a227bf468b7f323575115cd
+S = 10982c965331cf8529ef6adfe17dc3fde63dc2a557cab451d7c9408a089229e22b73d43
+
+Msg = e78f538b1ac21602b00a09e3db243ef4803b447329c94a1476cd91a88ff790da71421b60092c8a6e55327c7982e7655eb1fd6e40fa9b9fd2f10107dfc585994dfc5bc2143d18794a39f7f69ae679b27dd11ed22040d5e93aa83f71783525a4db0c3fd7b43e57dafd0033d5317680df19c2ecaadcb37ef896c61a758a5e455206
+d = 14f237cface123b64e8578ff33f86bfd2a8181b9c81f36b9ca31e2a446f0d91dbbe2249
+Qx = 7aa347c03d8845f1566bbc3fa1d66ecb41ed1dab0a402405d8300591a1f3078f9fa532c
+Qy = 63bd10274437c2690ed6df60ea632f3d4faefcc07a72ae8d85c2f999bafd373053265dd
+k = 0570bf3b42aa44c11603d94e14b524b8cb1363306196924082ae71021707c3138503031
+R = 10f7f4af1c1e3f9e8e0c95f991c348bce6725f60aa12ee7b398be64728242088a469a58
+S = 17145a39fa4dd237e31a98daf3974138638b9462a31b87ada3eade6bf7f597195eb28b6
+
+Msg = 8a6ca8ec436d2c706fcbec6486b5665b21c174edee7ebe108211c388b1219a8224179f7438e0bb7d6e41ac4a67337b52d4cd9a069fe6c88960ae20be29c8060efd7c62cb7a9a37136a250e68f253e7f27755df53ce7c570135641ad49b43507e5483e17b919cedffdc0d4913b1d5e0ca0629876c0a551841a0fc2090d2857cce
+d = 08dbecb26587cb2ed7df2404e680fcfa5bf8cf6a58e87a350a1600211b3c844ca86daa5
+Qx = 66610ce348821a77e8a6eb74a675ad9312b2622ad2e1e6d8dcd0be8b27d8384844a7234
+Qy = 014c15776bbd144c0c24bf419237db9401fb7f97a7c4c0ef50a9afd27c3964088f79643
+k = 0204586a9314bc14bef8ccce8b9ca3874572b375d01c6b4a41c743c16502a27e91a9fb4
+R = 0fabfeb17bb8c1a57af7af81d99cfb7b0ecbf4e5e4a6ed483aee4be8ee4c70c2ef23941
+S = 08071e162dfeb068e3cad256c3603e07ae48b35f1bafdb726cf4ce32844e1a2181f23f9
+
+Msg = 95bee02b423d2c6e60252da4632f693a2d8f6597b4f9c6e356f670c3a9e4e80063e92facb6421d0325b99dc150464ed2ec1d0bac72a042b35d56d33d2fda686a75d582d4756522218b4ddd25ed45503d90d3d185cba6cf0ac211b22aa4e1318a8316c369186f7130446dafad64f7966f5414f43af37a87127534060a23c6165f
+d = 191badec2d28cbbe62c072c6b57eb5d4644d0c0b3283951bb66096cd15edd43a1bbde53
+Qx = 020224b00428031056ed370147c51e68ffc02e7fe269ca15b22310a2974d383c6c83fcc
+Qy = 1686568fc4768158e75b4ef0427d8e262cd0638801ab158311749e0f432d5b69a667f0d
+k = 03b1b6ca5e627f00176b599b68fe54e1b5a272c323a06b55e4871875c0e729c4c79326a
+R = 1ade251b9360a6ca1b48c2fce0768a01193a415bd23956fee1e5c4c5076b3571abae082
+S = 0adff25020af4e2b4908a33ce1d75c793934921267b6c4a0542924300fce40fc0031021
+
+Msg = ccd7f7c0e04d1ef9a3c5617d77480bc624beed6582bc28e9e3a369b12144fcd96b735ee41713f4173b64b28c6102d82dcfc7876e06e76fc497d1d238bf6d85bb5feca630bbd0c0f0fa7c0c72e28e9259087698973ac66244bc6e69c04deb22eaeaee7b20da239ab6333576f01349c76f594498620933b8969450ac2bae66db8b
+d = 0ff5e3d66eb57fd35ba4472effd6e7a016ca461e39000a7125e99080f6ab6ef4380dd7a
+Qx = 19d8c1d9aca39de0e627981d21e35a628c35fd4096aaa86f61625fcd078f0400f615cd5
+Qy = 52ba2854ccd64407f6779c5e259917b251c9e34ec0d95c05488f30802b82cf4b25b5389
+k = 16c9cabed653c57676ee46c8912cbc507b246078834f1667d0708e4c666346299c1fc03
+R = 12ac0ec9501ac91a2b57220e9c00ec6e815399ede94a658c36f9e89bbf1674316d65dc4
+S = 0c9480160c4e9db4e82b4ad26cb79e083e9e2056e68a2ea554aca45802bbb188389bc4f
+
+Msg = 65e9124a2606c8784c9489add2999f4cbe6186395df20838d653b263a207ec46995d2685b55d1874e7ef05a6a3bb5b60a7be6751ad568cef1bcea2debfc494d1e2ece0dc8028c88f1b2c6e4ee26b639c5e81f6448bd25b73ec4608a8e8cf4e0155c29b6f0a62781493b03bb7384c9808529d5f87da6564ae196a365bd282f46f
+d = 1f3591eec4a8a3fe6ae6debe230d238a6b73cf3791cb735add1abee64239bb100f15166
+Qx = 483e7e2b8f7ff95b86008c3042ab83a4b6a48f15ce1cedbaf3b586b56ab606e6f23a4ef
+Qy = 287cbc8c609426f1665976e8120afb8de96b43978762ed44bea5aa1418b9af6922c6066
+k = 08165da5f5427b38c447382c8dd0940c3bddf8f048185e6cad260031f7c0a2ffb83027e
+R = 09034633dbd735cec6208bb6f4455b295b7d730c9301bbd1c0e9f101399f2b3425a13fd
+S = 0204ec149b416ca3467e92194449cf2ca0f41ca1fde79145f3af856085b298149a3253b
+
+Msg = e793c60fc725fd537d5fd38e9b4fb52e268722ae6bde5a058de8d20db301f5e8d8e1ad85532198835a04b76f27ca3c972be5617a55677cffa8219eb64fe53ced242efe1b889990979227dbaaa15ed39d3b6be8c5a3237ebe12bd96f333d947f80048463d3859e34f865d83faf03894c2243a06cc96788ed952e606c2d8948271
+d = 05af03cdb45961e7ff35fb0146904ddd6c2bfd3cce814073d3aa56eaa9f13b4f7423926
+Qx = 70bf676b9b0db558eeb8bb94a1248bcb599d1e8975ee13cd37dcb78af19307d1b7e57d5
+Qy = 6ed9bf30c627062b99ff9d05ca03441b6194c34364cbe7b73b46ec9716ad8a9970cbc99
+k = 192c7b1fa8f221edecbeaa51447818474dd9fc89e962e8e87400938ef0dff432a6c4b86
+R = 1df1a4f9578e9cae8102aab5eac70eddbabe4ced99b5bab1b1dee59c41b81e392968c14
+S = 0f2b1319335ee497fe3ebf1891a71cded59704365774e1ed9950f79100e70950783bc7c
+
+Msg = a57682d21cebb48190199e9f57493696eae3a59acd22f64d5ef4729decf6c2615b326817a6bc118bb7234bebfc7276dd998838c009a7348e46431574638dadc48538d6048d572e50d9c5974d2049ebe1837dd857bcd1447b1514b62808a4e7a88162ae1bb08a0f6d3db6f25874c6cd0cd4ca6333f1bd57bd192ef67e4616d182
+d = 1ec9710ada06e6270720692a06d488ae2ba863b905dd2fc323e7ce68dedacb35fc8c7d8
+Qx = 5cda72b5b068f70b3c431def41b8ca1d4381e8c2fdf0821cfc17eceadf5e3eabf7987b7
+Qy = 79ae508354fe31899cda71e01cbc80e5192d24f1f13c954208d2ab8412802407ae3763f
+k = 04f7b9372a8fed536396f0b87d4b20494786bdb8db77200c1aac1896486a05d3c940cb5
+R = 072ecde2a8f506f0fef273c8915a9edc29e440d48fc6cefb50e7117492fb4a13e123bed
+S = 0010dbd6229d770c468f5d8bd20edd6928bd8824b7fc2b10dc45fbd3242191e7557b984
+
+[K-283,SHA-256]
+
+Msg = f646e7334e191c2bf0056d3bfd23f03ef7f0777b923f962519a8399d311b8f68414c689ca34b96871fae99eb7ea534fcd83e788e56eeef817cbfe33677283c736b99bf6a626f9515291e842bf99f694e4e8aa7c9911c591a87d5f112b3d96b064594e2b368e6d1bf1a1cd343d54916a66da22c26355266aa2884120fffb8b94d
+d = 0668de088c6913640fbefbe6d2c44ab26e481802dbf957044a4957c3c5d0a0fde331501
+Qx = 0d3a50cb9d347cfe45d2a313813fec8b928a9b1defca6ff4b89c4787717f275c6b7337f
+Qy = 762e47b0669f625c39c74d50e2b46875ef366b7c3b005c16ede69a2fba161faf6b3d0db
+k = 0b24bf54795fa02eb9527f21ead5497a6db2bcc7849a16d206239f830df313dfb7a2716
+R = 0852d8b6fe93b0b36af5d99530eed08669eb9a25972fbea59f32dafe88b722bada98ab5
+S = 0e5b08d410f2252f724dfcecaedb37b92a6c09cde646ff6237007f4199068f945ebebe2
+
+Msg = a2d7e69ea381d3edfde4664c56c4cb140d01cc4425df757975cedc995b89640dc016ab419b137ff25a6a6d64a309b23890439d2ba157262393cf93d15ca1b1ffd19373ef12367f8898aaf56d5544c2f019a4854f69b3d8d320e03135bb7b675e588a5c3fe4b703938fa0f964916501297cee2fd04af767155c7739419f9dbb7b
+d = 0e6af57cf47de1e6f07041eb5e1a413fb7ddd82f8c7f7ce957eb28a118004930bec4dbd
+Qx = 21e31c4e4d412a261e40483b9106bbc1b0d7e7414e53d7b9fd84175229c8cefbbf6defc
+Qy = 46ff2dc601dd407883af7dc71a6ef4286cd3b1b6ccee4fd861865bff8fb38ad51b63d49
+k = 08f9e2113d0b223c04e678e8ebdd3aab4816681a9ef08b18a38afecc57d79c971421469
+R = 0d2c9113a18bd51008fd327a55c214c9584b6f1b816cf3b95e7346080da2cb07dcef8aa
+S = 19167051872759c36ba9eeb5d620cafd3289e8b7660fc847ff385b5143b3aca38780639
+
+Msg = 7088f60e9375ec6a42f705f851fc76cc833c4dcbb3352adcce9f59197c1b7121e7aa661c4f8ad9f4ef280af3a2981e90c01291f7d1cf7d3ae2d96b37fe6975e11b7c6c02b8ef044d1470b1a26b9c72e8c4e7b1dd83c8acc9542e2fc7d211b87841dcceea2ab8128d0ff7bb622b60faa4a89ea7008f7d55f8f9de675bc4596fd8
+d = 19f9b63fde8c6aa6177f2a38981505d04f8ac62bcc21007b05615d028cfe851ab9cbbc6
+Qx = 5a3e567b227869f948180547c2713703c90698dc04864140d22b24bdf81b3996829aca5
+Qy = 5b2ba535040afed0bf6f9d850713e54013729bc6dcbaa336ebbfb9c461f7ac61af48001
+k = 051e20545a0a98dc3fec59e4ebdf101c6aa2768f344c1e19424c1eaae4aaf7ffeb5205f
+R = 05fb3329f63587e8febcdec49f92de88366a9f75d0b9a0f374dadc6e7a62b833753e990
+S = 12edfabf1ce434c850b58804f1f31f8afb20fbb36ee69b68668e231e4c04fa75e658478
+
+Msg = ffd6044ab991849939e8a29184b4d0ac3e07acb63c7e6b886df9e8254073fa800d5910b9fe34fceb547565a2344eed4de394ce2251ed51ec882ee9207eb7340464c742d9d140fa0964f6bcb1efcc2d13919af4f727953de41b20728ab975c1ae0ce784865f23ed1325c68daa95ed5c932893610179be94f13b9a4149f09833b3
+d = 17704c1f436beb52f7ec97192e23e206ec09f9e8986e06bef71467c192bad6f0066b3c2
+Qx = 329294a36ceae2b2c56bb6e21e52ec32af11aca9ab7785be9c2d79652e7960c0cf7a8ae
+Qy = 658a89a48fb95cb7028252fa9792d91b989d7cef3fda8ba9c8e4ffaf19269f2a69f0a24
+k = 0aa8d2e210ae40ba1f9f051ad85d37f7cdea43aad890ef802519cc5773e9a0984fe5d6b
+R = 1908e3a2740fa04ec0b23c964c4c3cca51c4603e7553461dd02f8319a7ca2ca09d0aef5
+S = 12d7860d7b438df4653fe40fb9e986cb035b1384464e061bc4ee3bb29aec74d16b0a694
+
+Msg = c9f81c9ff7d80011fd41f2de97a6c1e6a22cc2da7b2b9e4c50e1354c3e139b44529ac786ce795fc501dcbf11a935d4728a7bba44b4e86b5e5990fed4d3e24fa5ab6f303e1842918f156e00dccebed6897c852207ae5941c630014a41696882066c2b296d39cd8658cb5830eee78e29a00335a99a0ba90722ceca5a2e9a99a2c6
+d = 0c7d1ac8faa689698f5c6325a3b3f35e7730bdbddabd0693f2bfdc5c838bd62f84508d4
+Qx = 095a930071ce56f28a79a66b751283c756c4f2566ebc2a10770ca60cced6914bc9a0d77
+Qy = 46f70021e7a949c7f55b059d4c8e81ee23b13809a35932d83b8398fc8684c5a90f3ec71
+k = 038ae832c25dcd30c1ee3f5fbe84bd8779c876c0641907695aa598132b0e581ea528332
+R = 0eb27c86d3ca86ef53aef0465d257e6b681f891a6357cfbf51260dc6e35a82799de0e97
+S = 0e8207959e8be94e7407543df80d38d9e662106ed68e1456dd1826602c5b73f27ddc901
+
+Msg = a60de761eb32490184dc1d29e21fa33889295ca587b994746874c7289eb9c83e9c7bacbb4066c761a06b65ecd78d701bd41f305cd7eb258c630f3febfbb0a367ad16737b146fd793dab23562e8001cd113135b1c981d1ca23eb3be0fe3e24fe3fe1089caf9fd8f4f0d1f90dcc7dbea4a9e2357793b65daf342b8e6d109c6dd10
+d = 1a173d158866db0ec665ee632b5fc397893f6a44ee17c348e7452800aadd8ce676e7fdc
+Qx = 6a9369a93e0b5165ac6e692db035495c5cdd6df243d9756098385ad616374ac1e1efee2
+Qy = 32f72a02c36954cd8221126e4eaec02668f454214e4508cf72b6d945e14d9b7c5d404c8
+k = 0200713a78f58c755db4897f9b7e52057a087816a07fc388d66d34ea9e0bcf2f47e182a
+R = 11a26ee24610e705a42329f86aaa80d78934b4bbf19314f06eec46067d85c8377e04d91
+S = 077e35add124574e98e0056bbb106cd28ba8c3bc0c47063ceebbbf2684983a2a0061950
+
+Msg = 2cd0320cc73120ef13e83c8144b270c9a1f2049a9250ef7ee83ccc7584025140a51e2227a5ebb824deff55b3affcda63ecb1fd3f337c67c08054dc82fdace0c4bb9cef1bea9dd792635f655363d05903cd6b5ed50ee669bcd8157509366cd85aa40d19593265da26e5641590ccf04672a6df52badd4b99964a8643d9687b499d
+d = 05523cfacf4ed3b74ebc30f608292e45173001d80cc801f729c5f71fc213b243f041ad5
+Qx = 410751ae7d8bb2295f584ba3d55eda41a80b8520b02bb4e5ca669a1003d6f2829e0a01e
+Qy = 5fe16244f76f0c8b24bd3ca3b53c697097e3ab0e2b44962ea534a655d6c7d80b857c21e
+k = 0a634f4cef0ba37c9ab211c57fe6574c67933280c91c8b175fa4164755bcde867fe1772
+R = 0b9f6946a578ee38433e98478a4c31b67e838939cbf128f023090c4848471482fd1dec7
+S = 157159e15a2d16da2e913c5ef00833a8e5513ee4e7d6cdc849fd822c59886d0ca3695ec
+
+Msg = a743d8337bdefc4753f937e869a36439da1f8c75e1278c3f6a4a969d93787dac93293818b1cbef5b8636e1a6cb3acaac1e15dbe0841c8001512b689292f3f4805997ae26ff52f7fe1842512a020c448ed01af2a061f3638689446ed5f6bed9fc70726ce4104bc11142de63873fa7039830223e8f152996388417c48e0c1fa81b
+d = 09f6bd008c04b8823ccc3ee7d5aca535c211f35e9d9e7cfaec518b98647fbe6d28283de
+Qx = 70019957dac0e9be0fce6abdfc00ca737096ba2d2bea9ba570acab6d73eae2132d7eb06
+Qy = 559545f82741ddd1cbb9dab0cd06454fda8abbd9d1eca752e57ec05498b14e4189f1b9e
+k = 0fe407c226fb15bc63d37cc9840a1a1fb0ac4fc2939fbbcb6e1236831379d367669ffd9
+R = 0e96e301bf1193dfdd2815597e016e0a282d6e8f9d1d67a7f7e7d05288594f1ea92584e
+S = 07488687f13c3a2b9ae90536db7868f2bde1529ccdc0c84eb85c53ea979228d1fda7c94
+
+Msg = 6a7a3ad614a3a09d2dc5a80204815d0c6471057acc0fa73f3cbbf1801902c3e1cba3c1134a79a8ce61994a94a5afa85ae1a44b2cdcf5153f8625713c872da36aba0afcc5c2f26636dc3f60e04c256a5b023e20e2e7a3f7305bd5b3033fcf05368589f19021f8c9096a88679904b657bbe5b9bee67d6e53d176fce1de9e54c64b
+d = 150d2812505c82584201e93f6e0cb875d29dc7bd99d9c0f98e0ed20128886e67e1f1071
+Qx = 12c7750172bea15487a05580891aed51bf81548f4b65c51c6c54b990bae8857a20115b0
+Qy = 3db9e7a17dc8b24ff080d80842f0488f17f7d43a40ce6ffad52c65f5a875b4b33efe3fd
+k = 0c5c52dfb50b210ae13c2f664d958b2491bfa91ced638f925941234bcc4d66de1eeeb73
+R = 03887a270eeb515a59a7387d8acbb4e72dcdf13f317a6a93ace5cc98d69a79c64a9e7ea
+S = 0e922b2d021cd71e213bdb36ce3ebf56a34617d4dcca30fc05f238a1c097e38d7cbcf91
+
+Msg = 65bcd77a3ab345cc99b9c1300755288102a6ccf140bc7d1ad25df246ef01fd57a8614b352033b88cc6ffffe5b38b99ecf03baa365ab5529d6751a3c020d0198561969aade09091434d84ffe13b46df043d0a61e20a08e9c32b646771fea1b29e202d40aae1c7079873c3af494ecf6ef5eda855736c9338b4a5c29a086a8266fa
+d = 1b3fb9e1ff70f94bc9d7742ea535ca982215af3df381b5ebdf1db40c7c849a7978ceb98
+Qx = 769a897a443c41ae7a8c1e45290ef39c40887ab8f4aa3f9ee8f3096921222ed7de45739
+Qy = 72621bfa30973da61fb6d363d66db25daf818ce79dd3268ac0520fc99ca7917fa3a2360
+k = 03fa84ee38587f9c848b65b07c47551e27f15e7a87ed0ab705c99c8b7a4ee9e86a8e4ea
+R = 11b214ebe67eda2bd6e84c33be05c4373d2536e2cccf152e56b1569cc96d261e50910cd
+S = 0e100646cbffa016664bb57c1a67108645238573867c0b595c46e6053f844e5482a993a
+
+Msg = ed1acc360d02ee6c36bbc223d91bc1d2009a3e8f8dfc4c3796cd8555b0d2b46716f4c8058bf34c2d4954e098274ab9c2cbacff46a0578a14e77fe104196cbc6d2753e3bb5422b8b79fd004ac0aa920eea94925c016ece16ed4dea916fd92563ec65692a61b28ee84bef0007120bb1e31bb75b8ecf68406a71af9a18b4edf5320
+d = 147fa46fccf0805d14c1b84ea59bb8b8283d54ca0ceefb29b5585e7141340c55b7232f7
+Qx = 4ace4c65ce07fe5ec22c560bc553bd791434a691c2d865c52b5e38d541ef191ef419067
+Qy = 76250c829de137b6549d22a12f196629d9d34cdd83758e5daf45fae41872c9b15190ce5
+k = 18c4f89cc022236a0da6105f19c6661a8325d36fa285e3ca71c1a4af3dccb016cac186a
+R = 0271b421fd572de8a71d1b18ad2325bc0fb58cabaabacc1f015ee6b14bec49762f1f8ce
+S = 12e679010ccb143b7de0c3f6c82cf99a961a4f154be6c87abb111cde2d721d864d7a1bf
+
+Msg = 2debdb95a21d72b69c545988727366a42b819ca6398a82129c5e3772aea93fac0aae9a27b11969ff0ffb9dc0301132ca2452cd863316cf24ae7696422d4dc68e37316161abc146e86f04b72d9a27a350d8545cca245b2be43c33bb822dd813d13e08a718f784845df8a4ef49b02529871ec76bb3fc1ba31089359f2ede73e767
+d = 0fae097ea56b35a517be5480802f450eb832b244558d0cc922cd4a5b40b84d02ef11216
+Qx = 4f6bda2dcb9560174ffa54f13fa5edf17bebd41399a1dce1fe13e82a2b487eddfe25a19
+Qy = 76dd375f2c5f24c342a8e2491271cebf5b97ac666aacecc8d693a85ebd2a93eaccd4059
+k = 05e3a67091b9e10c7fd20fd70d51162e5d78555059802d0c3b133f49b89f37be6a119ad
+R = 0ddf93ef8797571af3cc9a66660c569445a2b5384f95a12d680c570694bce49bf2264cf
+S = 02f50d68bda006b88798d87c232f5ed1796c841074f063da03a471e0c00f08b10f410b3
+
+Msg = e4e0c6c8fc01244abf81e139c961b6a6e2d95de5dff1083e8a48b40e3e5b9ed909152c92b1cf2263179629cdf76ae553b58bb2e9223ce4f9ffb5f170f5f0c5ec97294c34a7529a897e9397f71198cbcd68bb4055cb8cd6b690290761b3b73303f82788379df145358afe28f2997d191d968929b7a4b9a0f6228797dfaa17c613
+d = 026cd72e6ae19b3f4c53493fba1e8082a8df1fb7da6dc111b47a41f713f49b33f618d0c
+Qx = 1c411f5e298c9b61023fb26765cf4132cc78ed77c07c3e815fd43032cdf0ae8b8920f96
+Qy = 35647b4c0807b287014043560d70c9b14651cddff4bdf6d44ead5e87720294ff8954406
+k = 10e9bc449e8480474afffd20b8acd6dd08344981c4a6cc789c5338ad7e486c526d6c4fa
+R = 0e81594f1064e018aa3504bac75946d77f9e745673043417a47c0c82488e224cc4104d7
+S = 111bf8635b1bc3f6cb7f9b685077b38d67160d143ede2bd8b6ae93327d7f55c5317f00f
+
+Msg = 04710947b7c90855ba4e59107b919d4a1df22b503c5c4c33b286b6b08e451e6fbef8ba40852f9f0ee62c9217abe6156bed46ad6f0e25f70f528f3a73d099338c578bebd6879d810e6e173c2b0af1f7caacb3531ff0e6a7856e4c84db355d110febdb21c683223eb5990ef2038d462ddb7962bc0feea5f850954943d53041f66a
+d = 198e13c7d95bbbb6e226688719639bda988867764ffa9b029018b5547850daecf58fe1f
+Qx = 30b511d719217c485866273ffe2996a19e0a670b7a3fb077944a21f63ca2f22fe5a524a
+Qy = 3a4d9a808e8d77c9dfcec6d033139fc33e67d7c8dfd7329c895bfb77f565391c37c8d8f
+k = 1721f1ad4adf3c32614feb7f8df3374e24f76a32e27854a57dcafcbaaa3082b13e461ce
+R = 14b2622432adcfed7c2ecd2b52e43be7f611680ceb4bedbfa9dd9af54532911a07440de
+S = 0ece991128b10399188b18933c0d185e85d111ad401baee5ac376b84c523f130f70fee2
+
+Msg = c62d07bb1ef756b6b2fad355c66b5be086b6dc387b37cbc4a63c841dba3fce65b09d3de8f239e3649382d172f065b78f8a53e0283cf345de06b4ee0b4b7d8611bfce92a7d993b1938419afe817611bc6df3ef74191e7e39ca2339fcb5b5cfee3166d09cd52a1a7d3779722aec328d326a11bbafb6aa417920225ac453146b9b7
+d = 19098a39956747de24ded56435fa1e6c30cc2b8088fe9a75f5d07b2f5939c7a60db64ad
+Qx = 68cf5a2023753717d89d12d6861c8411e6081c3158339573dc5598b1700148d00b39dc5
+Qy = 76a22dcd4ff4f062eeff83a58d2ce6a1808af8733ae254f5157efa8ea35a85cc744692b
+k = 142e4907ce239cdaba562d1fa7305bacff05a75e2927800c7b7ea322b47c9ea47846e12
+R = 104620d752b73379e1e5d35e5b24a793d7a309685c00f8bdb97bba9876999ed9c763d0b
+S = 059cab3abb0738d8af4ea6dcbfca6d0ef11b6e591ca109b040347d7d4736724953cd9fa
+
+[K-283,SHA-384]
+
+Msg = e4d8d49c9bc566261d9134d5e237d9cbd6b67d2619a9bd06b7c9c139e091aa10682cbede114e1d4777d9cd67a16b7d64278e99eed62bbf25ec5a5a8fabcb0a3468b0e73fd02ac6533e04b1110d29da3e34f33eaa228b78341b357a5d892a61beb2168c3bd5e66bffe3f2080a1e246f55a41ebf9d579e188d16991aa060460d6a
+d = 1636bd2be121e07ee83ac5e880cfdfca6a56f2b9d0badff003e872348368c7c2cd96b6c
+Qx = 007acf46ab68744a9baaa33ebf6be20c1c093242b0056bb9885d93a4a9bb4640f17b2ef
+Qy = 15415c1b671e98f00c1fa364bd69cf998c0ae140485159b0a341994a4e27000e108f4fb
+k = 0d0d4886c3500bff68455c41f5840d0313f33ac0155a693d27c66fbdb12791c2b5f8552
+R = 0256b8ff7d37fff7dcc8cc4461984a9bd9661643fd3a68d07fd30d426d10b8c7f4dfa34
+S = 1f516f8ed4372780380a798d2da04d691aec379483bc0d10560ca79edaab453d3e77585
+
+Msg = 2d1358fdffc14630fbc421b443d3c22ba10ef34f15c6c5bb3c73a9b8714e4c411de69b9cd6628fe2eba5efc4862af66ff916505023e0514f564164b389ea422d0f1beb92adcd65baf43556614eba25e43852ba65af78f62d64b36696519ef8284ef7316ea52c365b99f63a39e6701f81ad520d7445cfc0113c38ecdad4bf5b7a
+d = 15e5f555119c19b055b15b0c0d2813068bfc184f864e250b202384f5728bbbda1cb0f5a
+Qx = 13cae2f0c3ba04d039c42cae27de4cf5842a3e24be35d7a3cc7f05083f02951cbeaa63b
+Qy = 5d69ad5b7d64d6b19772a1794562b1fa5c2fea03909bc509e7d47b0e8144acb3c26fddd
+k = 1b881d95b7de9aed9fb5ff0085ca4da2fbd413b9b947066c98aa0257142c9000bbb30e2
+R = 176f9e3c9e9f98b2f5f352ca74310badf9f598f4d42cd2b26e5ea0999ae31e3c678fad2
+S = 1f2dba4e17470cdf7e1815d30771f352807b38080d44465f86044f5969b017c9059daf3
+
+Msg = d6336faa5c3e838f4fa58626eb353d4cff9ba8f0aa0e6c3d0d850e8b22f5b0f047afc97767f1afe2040b85d4e401ba688a4da7a0caca7fac450899092c4fea789231ba9b07782010720f45d16d353798867dd7fef4a324520014ad5cb32684ec50cab742b750e05db040ff51140e8d740f6774a059feeb493b10d8ac722f23fa
+d = 190c8f17bdd38669e345440d2c7631d67cee9c6548c4e7b9452377adb9303430efeda0e
+Qx = 3235a8b7981b3ff376b6b0959a42cb56631fbb9f82f1694b9e273e6b7131e758fa0d370
+Qy = 444e5747420d7f5ffd6119ef43b998d4ea4a58da13ff6fe7f241ccdfd4b6fd33aa93e3d
+k = 0b2a690793107257d7bdc37c492eca48c4c9650ba0d657e6eb62042b16169fbe27f8984
+R = 168a83fcc67e0c155f1fa2329363729872e254f2e0c3ef85f3b3c84fa3406de4191b6e8
+S = 18c0f8e6b486e6d7d16b4103506d74bb2021232c0b1638858295a63ca35e0d6d26a6266
+
+Msg = 07384a3f650bd270b14ca388a441af201b7767a2d47e9033f50cefd3af8257ecb38f5267e141cbbb2ab7327d8fc78cf27198ca3543d39553e178390bf1b921618432ad895e4f8153783a7ac22f4ca3cad4560e64f1ee4a7bcad05df98ea49a3847dc2143b27c243e48be59c869a547988e2205358e8db98b635ca21b745df4d2
+d = 0dbbc2a0409ca58a9e39e33b95fdd15080443c1dbdb5874bee991bd1b127047f08ec9f3
+Qx = 5a687605e54e49e3c40fc5ee8fc014a62d72e8595280a66ce7d367aac2df4d16b98deb3
+Qy = 30abd03dfc224f459dccd1606287cc30016be317c6207532a0725c957ca5fde692a9c43
+k = 16bc5aa29cea64ce3297172f36fe4ce820c943908c21c9967697db0cd93bb8a12e42348
+R = 1b1fdf26a6eb2d736b8c1ab165af2ac31a4c206c5410f61ac7805a68992dbd62b457708
+S = 14e9a22ce703d942a4fe2e84a4c1c1b44538a33fbfe904bfbb17af6490d372acae4668e
+
+Msg = 824f26dcb4ce0ca020982814d5c727e629cbeeaa818c49668f8f6d743f0d0ad362b24cbac48027898f386889ca5411d7d1f9afc69493b1d9ae4d7b695c9fa0a30bb59e6be2cbff79231767e96cd8bba349fa2f97955d56f05430ab4ebd007064e3d5add94dfe255b6deff19650883ce9966e1a2affaf84d9540f65c87ab1f936
+d = 05495e6c59ca1873f36b756579632fd47f9fb95b64f52589d70f2739aa6a3bf8cf8c198
+Qx = 6df40d8259be64c8ac64a28359290bd52e843f330a68c2b605ba4f777d7bd7a798e9344
+Qy = 458667cd7021b291c3415d64f9b054db71d3fe20f232f2a2286aede89ddaf1ee8c68aa0
+k = 138f05303ea63bad47c4c9a9d43c52c264725a668db5b631d9892daa1b71f62656cbf73
+R = 05e35c1f3b30b43cc9d60bf8779f3b31e053de0a390da50ea676dc9722a17ef00d68aec
+S = 1691ecfb826fef1ea0895242129cc3e9a14e1f84fac49d62ffc0a3455ad9c97becd5980
+
+Msg = 07de1e4bb9be15a710a74806d4447b093bc08ed04392d1bd5abb414f5f4b4d9d43520d0e46fc81c2a97e71086b28e53242449ed37fd7ed1c5772dbabc430fcf82ad20437b38eac15820421e51912325c872894452c3f8a10ddb040b35308e583c155c3707b52df467c4945f4e1071126ed46611a3253c297f5cbca9e27f58448
+d = 1724987c9b698519b6c225cf1261b77d0300045e5fd774dcbf13f285e6bd74512cb7edf
+Qx = 46adc9bd5f0cc0d8bc64f4ba491eae3b7f6fb4229bf94b804807c6137787adc0fed4b2f
+Qy = 41375e2c89da41af84529811ce7aef26b983ea8add6e37c32f2b00bd47f23f25e5fe194
+k = 02ea4ed0e87687a50dc3acc7f4c089040ddd367d1a3f470a711501ccaad63c201b87ea6
+R = 1be198a1b6e91453018513902f0a8a085c76a2798a2a0538ede30dab65afb6b9b0496d7
+S = 16342f87a813780aec006ee218a615c4e1c78c0c759d48d4094639b5b4c32a9658c4d9a
+
+Msg = 1edbbbe71057bf7d0bfda922be21a3a4dff57b017ebf6fa99651246cd173bdc9b11eefd048ea599c1f98e907932aa04f64ed0a007831f30daf186c88807400970904d6090b2cf181e0f65f03b4234aceeb420867812562e47f452152bb1ddaaa48487170d06e47c5e9a7c0faa4fe494663d2fec22f7665ceffffc214b21c6b8f
+d = 1a5489091cfd51a0970508ee3e8449081ed175928ff8386592c83043a7911bbc2f8778b
+Qx = 0aa1562c94bd16a3f8a1d6c465908ce3b83ba6711e7d8b0b9353d3c55d13dee213aba70
+Qy = 103a789854f63a139e31348f1b2608f1e71c88b5d42809f2460642ff46a470ad8573543
+k = 18435a6d3bc02b3019e1b156ddd6f3e1bb9c5af70d1a2cd2089e677cbacc21624ec8947
+R = 031f561b668aeeb4df43a3a34716c4e67232f56959104b7237b26e3c95dd40e15eb076b
+S = 0f2ddb6e6d18a7393425c16b3e5a5aa232cc48198d63e46a601cd3ed221a8427178a0bb
+
+Msg = db5cf1de38a5187af11c1f0f19a36db52f8417de997229e83072fb51a3b7152a3b383e9919c1b8427582e53d4e7e25433d46cdf01492021c237ea0a87d38c71634743115a6b2aba66d3faa8003158340a5078171e0bd55a6e5d8c7fb2631a31c1204e1479bbfe79ac70d5e5823af502922a900576f0088a33e42ec3e26c0089e
+d = 1a45ecda0788fbd7cb7a716dcf4c6e83d4148bf63ed58078690ebd238c00329c462590a
+Qx = 7a1e2fb4e8e79e3946086fa65042362418db0dce51541121c73972a435aecb99f634023
+Qy = 06bb02df9899ac3f207732fa7cdbc36a60c17592af7ce06b8df4255110e26a02b231800
+k = 1c986f88ba3d5109c0afa2c213dda8df462282f024cc8efc758a5342a0de91c40452443
+R = 1efbd9e0d912e170c9c55bfbdfa6106fea4a4e013e7dc26628a1aea4f6b806a51866003
+S = 0b1347f4f85adef612f5c3a436cfa59eaced5c7cfdbb69444936d71812a2ab2461bbb5b
+
+Msg = 4adaa850eec8272d25d76600aacf2cf66e754f6c5efa65c55a2a31b7bc69437d9a7e47c6f51c5da93895a45221f5f92c2e20ee6a95eed3cc7249688261a35d82872284900eb54dd1df6024ec48963ce43e8ed8b8cca8ed22beee8f0aadeae53726cca05443316537840ab824cd1b595f36064e9a19333748d4f4972178e7f5ae
+d = 11461776c33f20b176dc8f2b0cb2446a9b69e55b6c7bc7457a7fb4639116b452b79661a
+Qx = 043ba7157559659954ac58b44f19262bef9e3a00829c70af66d07cef08ad899d7f8ec23
+Qy = 1e8dd9c947b5a6decd1a26fc5d0eecc9605d22abda747fca038571bb37036d9034e8061
+k = 18b231de7fc499b461afed9b80f4405bc005011865cdfeb25570b7c0ff79b6ae94b6ce9
+R = 0fb203f47a4e2e9365ce070ee7fd4540f3f7e9ecf69b4400eeded0f5a7bf6e5a5c6d004
+S = 0e635dc65233f27b8350db22b90a3b8611e6fd1b3e0f515e42fe8788b1376079816308e
+
+Msg = 11d212a99c39fb5e4ca0096bbe6c81ae1490e1b8e07374b4e773bee4fdd24a3c13d653919db663d2c32aa4db140c4ae2d472d4f878946e527ad33b3dc93012d97458f96cb622ddb56f1ce7c2474ad0d5291dc35545de47b7053d137a8e79dabe06757ab53e26eaf751111bd27690e57ffdab5337eb6f81889e9d1b1ac729012f
+d = 025a65f627db2b4d6cf83c5b0c00265b9b63f7656c5e3382139e4992bcdf3cab502844a
+Qx = 5a35e7e0b914a3e01ce3a885192d2ecd27418e09898631de122db0c48e8b58658720fcc
+Qy = 009eab47197d5f56927848855b6ff96db7c36f810ee7c89b305ef780ba8c993d65537ab
+k = 18516ceafb61cf2c7e7c511a8918bfe394c7fb2fbc40fb3052e156cd4020fc674684f84
+R = 1892ac13b86ad00e38ce2427c8c78c93b08605a75ca22b3658132dcf9d9df7c4b5540a0
+S = 0437b33615c16a85ccb8c4769ee7c5f94122d31e2b5fe66291b401fd90257ebefe33818
+
+Msg = 9e4ec74c09528fdf3153a0f6955f20c70915ff524b2e19c991ec4c5b41ea9185e3e876a02ed6f27c9b3479dba951bee8680c4c99be1a626808114408856994be7444ccbd5ef9859fa479b1050bb836034e20c531b4d618f5843fe1d4b613a731895b489a2363f3f5397d5ff964cf037e9b11e3ff5e1c3d403e5a46b8387c1241
+d = 173b28fc29f10245221a907778708b3ee62e0480aa9051d4c3eb4e8d552e6aad5509943
+Qx = 24bb9bdef975af892ddc1bbd31314926a9c81f8f1864829edafdfe2744e793c100c0483
+Qy = 28ddde61b4361ced9c391c86c28ece9b902c48d14c61684962007dfd69d0468dfd65e7f
+k = 199af64f79ebbc5b789d4676a07c224e4f6fd33285e5a555ac90cf65d0b669bc58ced4f
+R = 137d746d515b90890a413685bd9b26a1c05efee4c11a4b40bb621c9fa2580c46c20a687
+S = 1647f70ab7c68a0f522420893a466940ccf79067b323d940369f8b8694ccc3fc0daccad
+
+Msg = 5fe8253d2134c434cb0866796013722e82184638b024a5a30938039929ccd8415c71f71f239c5c5a81f7a9cb493dde209f189bcf766c17c6d9589cd0c7de7f07ff9f24d2320669b589d084f8a8ea71127b9760b7355b162616afb34bcdcd416f1a062035102e29b70069b2b4dbf70179b8d60bc2ee5a455efd40194533bf560a
+d = 0624616adcd45e1fdc6cfeab2b17230d73d91fe0b39f4664f3c6891554f9b8e238257f7
+Qx = 10917ef84bd5c0b36c97cb5586d3057a34f2827f239cab2af2e6081c5bdffd48dccb0b2
+Qy = 78ab47fe1bd3e28055c688c78e617ddcf6c5060123e9d65c562df2e94cac973ab3b1807
+k = 0795e229185bc1b3d6d69b08189fdd7a822cd18ac55971e4b35e51838bf12eacbc50e2e
+R = 185483378a162b8edd6a12f44e3aa4ff829630fe3a1c9ccc66e34775f69bb6a94282489
+S = 01662cde6cd497be7966a0a77b0626ba3c4b82e20bb3f2e839178a31aaf440aa0e059cd
+
+Msg = db49891838fe23f0530abd4a4fbba5ea970afa5747f6a0a10d2cf4d841581ea2178705c1203f00cafec91d0a72d25448072c9cf7d7ca5580b39f8589ec63128faa95cb0689574a6bebd515049a1eb9699922cde0366b5cd58aa8f3d3e847706896f7e1cac667fbfe94b2eca9e7be79a810806ca4bf53f219bb30532ca2254c11
+d = 199757ffaa2c59e198d66824eaad37cc42d49b2e241b6a60382d05e425e800eaaf32470
+Qx = 6ad18bdb3e51cc053f56b9f9c35e2d6eaecbc9749f41a9ffbf54634838d7745ca064890
+Qy = 5dd77c42b31aebbbb46277176df08d81919ee0d9ddf14c3e4c0cccb207bf649c48fc8b9
+k = 109d6332ceec5ea211f642a746a6ce055986b4a2feeed7e847904f7f411bf8361318d92
+R = 1a49fe690a34151056d290790a6bfa7b70958e69e9baeb30c55efc61dc5dc4934f2fc95
+S = 1710a4ba5b404d65f66a8fca2751a920224db0cc0266f7b0bc054069ea4cc51b1f017bb
+
+Msg = 29d385d09c1142a7c181fe4b6e6132e414c15aa8605b44208c0399464613b966edcc2d46cf203a3f85d943d8eae658695dac74366224a0d0348083bec0106f5eb8809ae8d07f792fdd7c48fb1a25d5ef3bb9acd40b20c61c821024a9acb2ede321bd2d0dda849c22d76f421cbd8d51565d3c4266f666455ca1c0c3777aa44107
+d = 06e51381dcf21050aef2e9b97e35303cf3bd91956854ecf9b6b9827871d2efbe8201c5e
+Qx = 52fee805d7938b8b97459b9fcb4b80cbe29f20a9aaebc07ac019539a4a966c5ee41751d
+Qy = 78aaae02974de6530f285b4bbe87fd5d0c9a2ecfde5fdc9a3303e4b988f673c778004bc
+k = 0b426ebda6628125d73efd84e6bbab6c4c8fcf7fa29ffb3c8d6b0a861dbf81cd18d088f
+R = 1270045e963b59e4a4f1237c2240a5b26a7ba8e28ea01326fbec00e5d95d40e859d88b3
+S = 1d721477ee1df1388e1b7f92c048e5759c060ce1291098a2fa647974a62a258a189b4cd
+
+Msg = 774c1cb8fb4f69ecfb5c7857d46415568d88f1f9f05a4bf64a1e1ff6d64aec16e1d09292010d1f067c68dddbcde06ea49be2ad3838053f0b9c0c2383edc451ef0188565118e7b3c66a4fa372b96633dc8a753106283b02d0322df273d58cc9bd061ec219f1e1a9c8ca1400e5e39c1b2c254273377dc98a1a2c44e5c2a5b89167
+d = 018adcc22cb9a2db64bad3d60f1608c353e091637b948914115ebd43679904f955c8732
+Qx = 0630bdd8937e961d5396f9ea5310123a340ba316fbb7d79bf8573f27a0065c6fd6f8890
+Qy = 737a0ac1116e0e2979f973cd705588a71cec5e2a9f22e7e81fc61a4375624f55a6182bc
+k = 10a0c04762d02f9d3014bbff287864743426cee14daa43b22149ce73d1ba609c0ba6be6
+R = 0ac29b041a6b95f9ab685470f50445d416df5f7ee06313185794f2b542fcc00606bed69
+S = 00a4241b97b6ccf0dcd533a15867f5889349ec353395d47e31c9eb6b8785736b3e285cf
+
+[K-283,SHA-512]
+
+Msg = c406aa4295f85c854b4db2de5a7a2defae53a319866921a3673af5b48c85ef22f6eb4cef892c790d8e64530fc20c729b2821b5f5e515560b1ac764106560c3a6a05657e34cd6deadfe2884bd288cef4ca92e1f25adde7d68a30fb0a1b3678156ced62e466718e68e9d67099ad82613b8d06bdda1a7b867c2455422818ae9eeac
+d = 1898276f159c10d92d8d4b6ae214d68c72792a4b5f1f79936ca3c063dc8d9a88be439e2
+Qx = 394cf9bb273923c88be7a1c49412ab8599e0cc5509926102c122326bc0b34243f7d1cf3
+Qy = 72330906f47e8fe95f63d0f0aca1115e77fc702a923c32a16505bcd9021da05fd9cf63b
+k = 058772fbb30227a136de616ace4a0334be0996d60e9772ae9bf672b7c38fe3ee1b24f98
+R = 10e0cd3fccd1728e99e2294efd6dd4797b6492ad95a789aab7fbd177475a047f1e5d38f
+S = 0c5e0b2d1991718355be14bc57e2d6ff9fa63e0812b9adae69f64da610cc6cbe36fe4c5
+
+Msg = cb2809152f8258660933472c06ddcdb65f6d5221fa29d5b0efec9c2a7914dbbf9ce0a468ce146fb333d26f510a87a6bb01bf8816756a1b5df81c5f65360957cae84ba038e37e88777580e91c34e2f5aef4fb55af7b81ad28aeba05e0b1c64a15381a6719fd2c16e38a441516e1b394952d984baf9e051b1dc1bda2e12f8ba5b8
+d = 12ff37c808c3cc029a9cfbb67a5ed21f3bf362b49270d4ed0f1e38fad25ebd79f112a50
+Qx = 0cc00fb36bf62e777a9f6048761e53633b92866158200c43900db95aa1342b576029090
+Qy = 55d7e57221ad939f5639282cbfc203114ee69baab4fdf194f4d2a937d8a57b70b54a907
+k = 163d8eec726d01a1bbb19995777919f68689f7c2920f3549fef966593c4fb012a5c3a1e
+R = 0cbf5c3bf1ee58869e1d3c15a05c23217f1c252da97f79334bc79efe3f5c62164669ac9
+S = 1fd51644f471ea497b0560b65fdfa2fd0a6cef469021303f97753d22ce1993d1ae5b96f
+
+Msg = e060af96d4a7fe512bbf26be9a27bb6a8ff37547d4a7bbbfa710db24cffcfc760dac120f89f642880db2df6307f9ea5441d5932d49762d182b29d8e7fb067a61ab0df622f75cecc917e27d0326085d34581e052c85f50a37713e27518aed7c4434f86970e00a0a4b8503989e72614131b7164c1bdc82d2b6aeac0787f9838476
+d = 02b8c1fef9c6def32b5f4127273ce384b6add4aecec957c1662f52334f5ee97f49852d4
+Qx = 36a4fe1d77bc431012d25ff49fb5468f975353be70e7507d71966a0ef433df51dc32324
+Qy = 58d705cc883a690641f0ab85af4959ef4258a7ba9cde36dab77c125a1de1d395366584b
+k = 0865f59502382b324e1dbd75db150f342336fb19145fb43a733971da555ac5828a3457f
+R = 1ccb2e56c02cbe8038bf78dea256704ee6e51054668ba8c2ba11aef4ac6f9320d46ee8d
+S = 030e662c0e7d47cb3b835c63599d0c9c2e77ca47dbecd7ac834c2babeb039eb630cd0ef
+
+Msg = d235c31f0a82957a087c7597673970aa39321d4c2640685a03df8388b5eae4825d1fee29926f416d5e62a2e9ca1ea7cefffd31607e750fa9675983608e0f8dc895371b190574d065c5c0c23ffdaf49e65362914363a3fffbc2c1bb487cbd4f69ec22dda5c7dc3bbab805c81faa85787cc176bc0e5703924f395d8c9e7e7701e2
+d = 0afb1c45e9a9f02942b8e04da4b815498454dde6643de186625a98b3c1c6993abc8bba4
+Qx = 02fed49c59e9d5c09202a5dc29d8dd527a870a180feded66ea6fc94ee094122ae97656b
+Qy = 3620820bdd5910037f5877649be38db3571a9c6ac632602d2013d0d5abe1f00133f6cde
+k = 1fe749d9916f11100af525ee343b3b74a493f92339e432a482dc8e86ffb5affc4630037
+R = 120f6f13331cd4d1a5b9707483c74dc0722452062cd4534e94cf40840d22ae263244a51
+S = 0bc2e37a481478f879de612cf4a833f7e12b8df33f5b0d6ac5f5aa431678ff053e2bc1a
+
+Msg = 1a2559777a5fd8f269048feda82c4d9fceca95803f84a813789d6ed070422240e443789c5231d63d5268ddebc060dfb99c4eff2ff115d2984d8bbc5c05314562ea6864fd543e7e0a3b8572c017d8ae3563027d79bbe164d40a5bab354720e45094b9b26391ceb55339592fc2f10b97dc9c2649f7227648f5cd2fc46d78d31c0e
+d = 0ff537d73a4da0ae3a4894016b71dccef3bc886f3d24a5abb7dd96cf8fdcbdf0fdc5e51
+Qx = 01bd0537dfb29f727f91fb469c31164e1bb0ee192a5b89b880f3fa40e3e5437f0d2f9e1
+Qy = 6df9bab2f9198494094a63f2ea091f60108449f0741806400694a93702f61fb0351a81e
+k = 0bbc511c6e1772ca6cd1cd308126c18c5db498055a4b3f1cb0dba3285f6d38b083e647f
+R = 1ba756f3c89b732398b90bfa2f92b2a77159c530a8020b75cdb9697c6d75c18d36040b4
+S = 18207cf326bfe97d657ac4197ee5c20c75431ee552681a92a5815db0d984fe597700bbf
+
+Msg = 658c0d3f764bbc952fa55a258bac16a5bb5184bfa76cee06baf9ee6b9ac3f116e08bb2406b1dd4be487b057f3b29c2043ebc33019b2017c4deccb86f50ff15fc9248ea5fb64261120b1960525aec3cc18827c23291722c5add8a3761ff8516c61956c62b8cbb13f3d92bf3eb45a70704c01bb3625d21c38ffa83a6db086ee968
+d = 16000d2e879906d1040b32eb6ba3caff700e5565871ac75f10c5c15b509964bbe5e14c7
+Qx = 2ba89255d1c89e42518662611e2efe3b5e3b8043926ae9c43974ee2986185269246a433
+Qy = 2b87762b9ada81bde958d1f9b81246f49098695391ba3b4b3b9ac5727f19fe42fd07946
+k = 14e837476e628007b2df21b5035a39c24cd4869bb52dbbe13c9666ddd8a7e3eeae29f65
+R = 1b5091fc755c0f908ee13ef9bee40dd16a5710befd1e265a312e595842d52cc135fd722
+S = 0fa25f43c3c074d702e45d216e3704d942e9d67b3c0728645ac6c53b9be7300061e5fe5
+
+Msg = 4f10001e3517c2c1f973b555f4827681e096d860c4db08f1f4aef8000c9c24bebe59f8bf3d7d3cac959a1a5477bb0ea43f2e746b5d14ed48a58ef35484b0ac786d2fec669f945e846ad73e6b77a9e47012a951b398941566330d89125eb3c1fbb2f06adb951ff5f047d102fdf28b5cadb4a3e1a10412eb3474d2ed5c3fce78f5
+d = 019528d505bf0584628d0214bc857150a929d3f59619bf8f3acab545fff0977c9bcdc97
+Qx = 0cc8863e1443e61fedc61abaff87d80450345489728d78c333b36fa28d8754a29cf3ba1
+Qy = 0205ae70c35396c07f9f96aa7c59cf8a28aa2a365b4a1b68e7414d8c4ae5220c8bae9ae
+k = 13d555426101fa3c239b7830fe0b6cf08a1c01f9a991f806c84baae20daddf5dec8f868
+R = 0af8bd9856dfd783217cf81b09b464614aa824b0298f35308e6427c679607853eb66c7d
+S = 0e6c1933d6ce25d0a00effbaf1db2cb2542cbe7521330c34286cf3bdffc20c001cd7722
+
+Msg = c43ec3c3232cae59bdea7cfaf18a4672035dbd2b8b6b1b44ede376b36cc2d8baeb921e416aa177f5977da8bf1d713509e5251278b6622790056271715cd5feac58bee5baf50b216e8eb886279c5a384cdb696470275b7487fe9ac4c506706f6b0f9809d1ccb102546a4297d2017c2a8df9f02f30d3d1bd9aebf6a92a02e0d202
+d = 067795ce117bc0a389397fc22a01cfd9422cfbfb5aa44131938a8c45e48e1d5a718539c
+Qx = 07924de08acfae6260009cc2f02daa2fc2a809e6ab4cd8858a9e9c2c15b17e29f1bc5ee
+Qy = 04f36cc2d36df63474a579b96f6e59b890782ad8fa865efd80abd798ca2938bacbf8212
+k = 1bf3242e75f8331fe70113ec8e14ad0814850bb8cb262c7d0a44ca69de52d32dfcabd0c
+R = 145148d59c5be2b6d39dfa33e904c161456822ec0ad64b9dc52befbd6496c9303fc062f
+S = 0b75c3c404d694e086c0f5aafd534e7d8596601f675b2fac9384fca6084711e35149f9c
+
+Msg = 9b7d675a3d2cdeb280ea28289b5fc2a3ef6b535ebee8ad242fb031e2e1f364e8ee806568b2f8627c5a5b4f51f4f65c71acdc1152c08b9211b81907b551e0ff47f5a6aca45dcfa06f09bf195d19d7b165b52111b601fbd97b192f62465f8ba20773b1599c8041e91448eac7a5763ca0628f40768324c5304e1119ca6a1fdb0778
+d = 19269dbfe4184249952a651a507584746c5b62c64cb3b17e0158aaf4d086a4afb0330c1
+Qx = 6c60a475f2a3635fa523e1b138edc36f51e94a34e75989c2cacdf8949115d96f11ae752
+Qy = 494d5e23ba9071b3e52c58b1d0740cf90cee7b084b9ef7a4a7be8aa47ce7b3d97c8c51d
+k = 111f4dc771b6ce5cc2f42172d3d70fe77c73683bdd2ea331ff711b7e9d8c3e4f2d7d6cb
+R = 027f224c01847c52ebc180ae81009923ae3453be1e0d94b5c2934603577f36653ecfccb
+S = 1e7b771631e5e72b7ddfb9c73f684b93270269ba4216cf3926e43b2ceb49756e7e7e0e6
+
+Msg = f4a08daf8f66ce57a986f14b918099bcadcc4308bcde7c169ce8536a40d94a928cfc0968180a2c2a242c59df73ff79a03687998c421cf9a0e661630378779a4744ae2a6cd24ff61d7fcd6c11a4c8bcaf358075e96f864df0998ee98ee393b37bb38747b70bb7a208740959b45174a60153ee566e0f62528e9a5e4466186fa650
+d = 03835814de0d6441cd80a44e40350cc8bd62ffcc81e939a4410bb9c9259e30463c453b5
+Qx = 5ce9f6c979bc1d6bc41f41095b7677cc184da8918265a7f0e5b9dbece2ca9e0667cfbad
+Qy = 39a395aeaa04f5168de809164285974d306e474a610d89fd401c375c9b73f0d23dbbcf0
+k = 0b714d734d063aa81a389be69c56dcc23bcced3517e330572f79c769645e7dd2fd55c20
+R = 0e4d4494f91e79f2b1d1c0e22ebf744ef448f57c951f1b5f4da3592fe60008ab00f5f7e
+S = 02edaa4d8731b598c24b993dc5bb4888ea3c2dfe2807daf88170982667e69b76a8ecfe0
+
+Msg = 864647405c70939fdb4c026bcad53218ba1d438d82c9138f0f0ecac815dbfb242307cca52c84826cf6556c51082a23f14252dfaea43ba229f7493db2bf8ae9cdb0228dab9e25cf385b504b92cca94f813acceaa1f18de851b8936c4dfe9e4e17002f02dded6b4c231ea5e614ab46fcdd637b8c6193e8d0c2df1b3d883b97e1e8
+d = 0aee83dbed3b703cb6e60d51e373eb20e298ac005fa6a572d02fa1e6da0345558ad2a46
+Qx = 0dc25760af992a8ecc108373281bd0d246f95933ec943f6346c1b2b941a03b33951f622
+Qy = 6e35f02d225ba11d2ed7ea392898f78ca0deb2a47871eba6cd2be7440a410d910097de2
+k = 1df142187f8b27f4888075a3784aebe0fb7d80b0b6d3497a7adbb88cb6bd26cb82109c4
+R = 05a530bf1135ea6d599928cb0383f5d391d19be333b1577ee4eb6f2a78b54e4aac0e09b
+S = 06f3033cf392f698d1a1141cabf138c411f4e20687920f2915e17e805e8657a887c7953
+
+Msg = c87c8f3ad5c28a027b28ae5021dbe8d425f74181d519451f1fead7a1f9dd102fa6785b147b610610cb59bfa91fa363bb79ea602a7d7e1439f874c5dce748e5c320560c2d9676f3a948754c72b6db249478b7e19c9829ab4de2e344535d3e0b7c20c272f82556a280ef491524b255c4fafb9c8ecb87b0149ddd9d7bf6159e3337
+d = 17b65c66514019ff935e9d571a4e68e9ee4463b7b9a754b93f4f7741693f4399879fa8a
+Qx = 5bfb704629596ed05096783e49864a11874f319b4020917f1ba700ddb0606e6e72c1793
+Qy = 69194592be64c33c2f63771af0e4100d060e9750031048002680541815b311ba8f7ffa9
+k = 171b5c698175300b95dfd5ed8d3fd7cf4e19105ed7193b6013103555808743501ee8c46
+R = 13f001f287dd5c7ad9af8d0105b47caed66ede41dc1e121a602610ce20e41af91cbe586
+S = 1433d5263d5233c40c0ca526b3657fcce8cb88ee65105b5f5ec82b26e12bfff11c8812a
+
+Msg = ac7da7611e2ade20aad64b418a16e02e79ab4894d758550210eb10013a9b5533132be701f8843c840807c4167c38d21dff168d3baa65d5bcf285b73dcbb75819f8d7a20a849de335e19bae2aab2ca560b93d340731f291599a5b28afd7737460d291105cbba6d0290e836f6f6c1113d1b2faf90ac5de7c64e25206d79380a4ed
+d = 17d2071f39ba35515a8ec977ddd36ca15983e15bcda626f15af61d87d58114f4c80a8be
+Qx = 6f09c255fdaf78d7d341fde4586526fcdec34a28448c7fe65685a67b6c33564ce9249a3
+Qy = 24ae4483fcbe3f823a7ce53db96ef2f6c68670e107e68cee4f358dfa844112d6b2144e1
+k = 1403078da10f55724fe7b56dfc55990507307386ba82ca8f6340d33769ab1f6ca894bdd
+R = 0a54a35767a1cc77b2332b04694404fe5a31ed8851ccc2abfa5542b0f5acd9be9b1f02e
+S = 0577e0a1937172a6d45177c2b328d72f75a08a8a774a31151b89fd451d531348695d870
+
+Msg = 5757c472fa2f81430dd920f39b61066a28c870b80e6c96f822f8f19b398c3574d159cc22120454dcd7e97be8211916e4bc8db365b2dbb99a6e597d06e6645046a0abdccbd06741e9c0eedf33cb78d78a540c2a390719acc498331e694e6b0118cf4f787b51c7b7237458a6149d6dbd0a08bae8097e919f970fde920485e9a0ac
+d = 11504659e12235855fe55220287a101e511d39a627f8a0d414446385d4a88f31507fe74
+Qx = 192fb9bcd157c7ef385d48470c3173ccf1ef9650da7d680d8473d45ab2064a073232ac3
+Qy = 14ddf872b711157d121b0a61b88a7eeb7cd260f1f82ec5f62fa2681e28c7f2640e305e7
+k = 17e10962721f041946bb5ffcce724c9f284b1c8970f974a069c36dd4391adb8cecb8bde
+R = 1546450d25e2536aa14b8751e3b3e7eeec8a6c1cd967ba0f03e6bfe64c0a59072280636
+S = 0159c8d6499fcfe8ac7b2e84990a714d7888d883c16c016c4b165f36d62c3493afa67f1
+
+Msg = e350383d04af0f4081bf09b95d1d53040e7acc64e56b13b653df31dd119617b800e0cdfeb935dfa5d94f1d7814688d8ce41021810958759cec76560e1e5c0581456acd1a020165849b2203f1c11d318d816697f36a86b59f160faeac7dba71682d3c031d0d547725ef69cbaa28345512e38b75ab011911d8924b2d17a857a96b
+d = 16e4cbabb03215767249ba2a608708b78d7387be9e77f5efd2462467fa05e8dcde2c036
+Qx = 112b7ea5d21df8ce52772a1b76a52ef6f0da62cb7718a467a034618b7ce701a05cd2467
+Qy = 649e0ad181437b4eeec87e202d8fab1c240f9dd9b31311284c24d89160b1895be541319
+k = 120e4bce412311d3e7adb36dc11d4cc1da8a4b9d6cd5219e772b3dc2b2b8ce08833748f
+R = 1ff2d53a8e6c1c23807eee681156a146e8f2cc1a8c262850dc69dece31860bf094e7f73
+S = 1e8906c0bf2a5f922ca271def90d704a1425e5cacc64bc5761b000c7df0f8f9fab51f2c
+
+
+[K-409,SHA-224]
+
+Msg = f153cc61981a46d8a47d17d29ec157fa93fcf644beb84558db7c99c57fb131dcbc5b65581ced5ff0b29bfdc66ff703ecdd4290f7c353c02a3e6d6867f33f3dccd1a0b6752b8a35fa143f8921a5078af9c85b212564c5b795da9858c7955095938fcd10c21e35e1abe905e84c8b4bc05f2a06091ce876d9519b96951d08c7ac9e
+d = 011c6528939672bed3e8c905b7ba594c3ce95f37fb28044f210cccd01dfdb42c10e8e1a0b5d6fc757834ca7f08e98cbc52b0edd
+Qx = 00b570ec1fd09d7b4d102f83cf37129d94c9cf2f982b702c5d1172bae2df558008518493c08dac6f76a6646156f123c4f33e798
+Qy = 0e3cfe1aafbf25a5a4536d6c0cfe13a540b4a3c97d4e7bc6c0346addb4b0c32dce089a7a5385e8a3e67606b45e2062c642bbbad
+k = 027cecbe83853037cf46aa98e1e1e552a96af0bb24e57756d8239fea5d769b51b83f195b7801b562259ee644ab4047764d130a0
+R = 06a1601e07dfdff9d3b4ffdbff124b717403490853099fb4a00ea98f84ddd64e908f99b40a2ba6ab88b2491a8d948fcc2f207db
+S = 0741d27c0dddca3641b56ba1e9bacb0da1fcee46b9e33ecc6990b98cf0db74668ef1009a50e5d55f80e6642ea48689a529c8a08
+
+Msg = 258c91524423b5c876432b1930c7b07b56eb5e3945f1e2296a4e5bfb9b9123f800ad195d6104641b1f1970bca553c2032f83d17252e52403a9381c1fc18eaffdf026f7537aa27d84c5e3d6e39e651a92a41139cec5181fe794457f556b390943093be719acd23fa1ddf7ff0aaf0479484a381a309b4f681af74bf97caef08c22
+d = 07e3b714496dd118d8f3f597961eec5c43d0265bf85723b0b9b0616977e0acc2cf686cb6afa6cdc19114e27ab000e762dfe467b
+Qx = 07dea0ceb73b9bfaff7147a36436cfa7955eab02ce7fe9b60dcff3e088c5c9281be5907de3e06ebb2e21dce8bf3ff85feeed500
+Qy = 1cfa9b30af20612666e5df798f91eb4647d8f5e1747c1b18adc6b73a848d987434c56d13ad78b775c4096e9f20d4878bbd9572c
+k = 028a8353c05129dcaa7caf0343130bf2e2186b9cb5ed0a27a565e1c24eb882617cc299d486be76fe0f8f3c52678b6992288d7c8
+R = 034299ca2aaaad51f12c90e8205da305523713516ba6e7d245eed8ef94a1b2409b98ae93476aed6c9b9aef50406860b4e490db6
+S = 01a1adc76c65d77ea686d769dcd007c0101b4cdd0934402fa47dac22f8ecac28fc05c2f6763a6781655ed5e7d84c41157255a4c
+
+Msg = a16a0d6fd57240fe88c7c36b9f7f9040cfcaa9afc4beeb8300818c5f90cce73b819a12c31d42af33146399cdfa4ed4954d068dbb0f1f342269dd29f1fe357e7224304b67b0f924b794780fe7e6aa9dfa3380252fe7177b43e7b1789718949b9ec1b943c83ed4399491482f0f59d2cb8050ab6f8b5854d76c50651428cd29c40a
+d = 0182d1e937b037bf7f84144f7d4c94c935269c9aae7d500aa459a7a0ec113b232dcf282908eee4c84b8106cd38cdc41db3f89e1
+Qx = 0bd4f1ee6a967123d70d488dbf0fb43aa5e93dee5794b4492277fe559776f740754850477e275cee9f1c375403a4933dc986920
+Qy = 191a544b98ba954cc6e060ba26a52fecbd1f0dc7c15381004cccb799a9f7960a3cedd02d36fcaeb0ceb844bb4683998d776dc5b
+k = 07904af733742716366f8ba07086f924697ac8a01bb4895bdb5715081ee89eaeafbff4cec44eb0ce14e774dba71bb9b091d2594
+R = 0723b2068957c4f2ac1df69378fc013797a3b071de30b514c3e610002dc8bfced32bd2f9e8f692b653e736696cf818b0ecc1e10
+S = 058455b8f9abd5fcc28a4ef839ac0245c3feda1fdcbc3c171b6928c6abc931e8b0ec34382d63e414657e9319d2965fdc9eb74cc
+
+Msg = d02ff569828fd1add21f6bd1c50cbdcd09222e458ee79fd5dfdba3cbb84e9d926fcf196cccedece77d5aa17f8c8cbf3a9facf0f02c71d5c1c8aeda9d75f6fd7b6f2c5c70dff992ef6e02c438fb3c66da5a503b3c39acbe2a069da457595b542190d818015d462670b0807c401e36b1bfe05baff3a8ccf8d1f5f8de7840e87993
+d = 07ed09428f460724c8a5225a31151e031d9949493fff5703369c401762345d002c4ce424294baab22d9e71edc4f854510cf0e6a
+Qx = 07fcd003a8cde5503f5582a42738738ac7efc6cdb3813a00c072fc114006be9881c0a881ca35988dcfb8088f3d07a03943cf230
+Qy = 0e7041e666c1bed3b80a691ecff60ad4afe3a544ce58030bbbcc130045e2c611d65f322ec78aff6757cb5df8ad54ee8a09616ea
+k = 02828c8c4bb1722b0f03262de32ca8a605c4046badb20d8eb9f19aecc5c69f199aa48d09b61f285254425cb4bb5e0763dd471bb
+R = 06c99d796c5d4fa21c5cb7cee0b7570edc9d7e9d7c3604f5ca3766b17e44bc71d8a74ac268b8713cc2ea0adc3dc1971c062b4a1
+S = 075962e0ccbda2280e502559f48c8d37704964f67f8cd3b443b89be740976f1bd929c175560fc8cfb282661c0fa792a5b200401
+
+Msg = 57befce973b225cfce7f996fa5a1a43acd160681b88a87b7de04544eb7b6a719718f1ca7f559b6531bfc18fca3836d2be7f7a6e48387b7579a6845796d30e46f0dda9d82680f8c96c5f0989741adef9762c3db763cae2699cb6c112543635e20ed5cfb4b55ca2ccb32d2d13936085a8ff95ed658a54be73f80c912ccfe5f0ca0
+d = 0390f05b9619c27b800e99aeaf61ef7f6249367d5cfaeae3c7b523a8b29153eb8a77132f6c4412545a842d6deb7b7aea7e2bda5
+Qx = 1cbcfc492a2a6bb8a7341df67ef2bcdcd706afabad5e7ed1d63387ad9b0dbc47ed17b82de6de936752632e43c393a93fc5cec0e
+Qy = 111768994b2dfe9677d9dbc45d4b55fbbafdaaa2b2638ba1605c35301fa557d628a87d0a7febcad9f8eb4b51fc9c807652579f6
+k = 00b8d236a9f8edba7b5207b4c7848807b933b214fa25cfc5a0e73f750d30051264bb9f6702837b0f65a451d4ef24f047ec4e9dd
+R = 076bd4755427fda22a0f177624477c59de12a12621aac274b980b5e1ce5dc700591eec13dc5bb48c5c8643de287a07a48a6a7fd
+S = 065a5b0a00548bcd7f59518f122d79c7552ca6097f3867604b462201add5f326807f0e8779f2177f277e5ed25253885ca81220b
+
+Msg = 4277ba40cb462860ca722cb4ee71c61836d2ceba18bc91f3fad7dea478972c6da0ebc02815eaaada1d1a5e93d7ab353855ccfdfc94a5742fe18daee2328871e06c1ab0a9a989d1239df2d2d27f96c415e7ef9a941f06c6790675361173cc229aac7045f49eaca207f59c497619ba32e932b5c1c6576812ee5b146e2cc7de5e62
+d = 007d18652732596add3db31f7a0ce6020d03f3df58131b0c7c633faf619b8210cd309d6c0c4083aef1a1b6d2a756adad0bfe344
+Qx = 15ad0682962b4dfc8901a0dc77d548ed616286733cd9b3ede937cdf4401ab8b3e3516d466ba43b6ab5356c4e72845767d55d27c
+Qy = 17e4de3288ed44b48e7c47b16e2afb513c9763d5bf4cbf9a357c128c94a758e3ff946957df461531def2b8d8411b81f45f0c2dd
+k = 01a896c30fcfdbe583d6b0119f467f47758ee01d4d601eb698f444ed0f76515c2b8053b11ae7abd0eef7aa61145a53d12d560d7
+R = 053b1cd57dfdd8d1802f3e295e450a155c366bdc2bd222d18a4d08369c25e53f1f633958b22d80755ecaf8362d548b28dff1ba8
+S = 069339fc6058762a99576a96e76f75275f848102bcbc281e59fda26c98fc48a3f1061755e80740a233e03287f510f4549bb1874
+
+Msg = 57ff6792ed4b12220d179bc0ea57ff217f322c85bd3676a681d32d7e4a3e0c8e891fd267df17caba5992f68c35ff670b60b4bbdfff82404f6ed996c30539bc395120f97d4d7a652eaee82bd8f9360bf8bb73748b8bbda9f9480eb54f7eaf2609d4259329e8a5ea020521e7dbd3ec56f23c849932cbdf2875f5d5c774a9d6b0c9
+d = 02a91244ea4623b63403dba807d60b914ca3b901a2523244c322f2f11251446d3f15e869d086ebecfa1a39ce304e8b5c8de23e2
+Qx = 0b7ad8f0a52ec21e54e28ef603d76652dbfecc7dd2427cfaaff3d280f0d1f62187d77effcb433b5bd44c3d0c0d26c38d3f5930e
+Qy = 080641bb0163130be4444f79c500ceb8d6a9b2cac42d21d31b2fb29da075bd41c6613f278944adfe92d3c99d494be9d4714e9b6
+k = 070125c89a1262a88f22e874c55ed149de6d961d6abaab2d13db9174e3cecb8f497529957058a0afe5361ddf9d3a5a3b923c7ef
+R = 01a28cfad13969c6449e5a0f879e01ef7dc1cdcd0bc77d20f3989c588a9cad12a4b52743c12f4f6e2154ad963bf234ec96263f5
+S = 066d7f0b364a640c6c620e3d030448d155cffc9ffd46a6adfa1c13e1b01892463a4724465aba3eb07009fa604f3af18109cb72b
+
+Msg = f85113eda64478f460b60f8084220134933de049200a5f37884da7901471542e26690a5fabc3cbf9e679ade71b6e54d869bc136c3d34cc4a9efcafb777abf046b5ae5429136112a9a36a475121eb1f33f1f43481286fc1ada98a41064a1fa38c89e99a93065bb2a119348a9e452497fd5a0d2b83a66b09da9f47a0583732adf4
+d = 0068c56c6b5d50d1d4e13d3837d8c5e8ba2f825e121b63e97603fdfe78bb6899600ff0dc87b6b3b6868ad0d2f62b7b7a31603ff
+Qx = 0d9a4f5992308013573f97864c23b98d276975d80cd6455e9f0d8a62d6674f3aee3d27dec15903da4e9d5908cebeb765ee02c80
+Qy = 01f61189caacb05dfb982bcccd603a769d0e1be8f9223288b5426e7f88854356fe825f11a88918085692f33b0f4c61ab09a861f
+k = 02ea7f0d81fbe3d4c865ff5315d1cc38f9e9a8653fc91dbdf445b62fe09b30ccddf508783ad87c8a48a6ccd5c9e817fe2977f90
+R = 02d7847479c16c4cba834ce5962724f185be06cc04a9a8d710cc72e6063a7b64fbf2694f5b62de65d3d347d34c0dbfd5a4d93b7
+S = 069e32bb19d20e873d0e62b306db4d5663576e4b2fe75e8ec79b7a63f38c8f1007a817ce30612e8578d48c63b04b1d34904010f
+
+Msg = 42811e9ee6dc509572e1cddbe5baf00afeb0c5c13e3755b922eee9e210001676082bc9edc3d78db2b5bebea7a2c0cd2b369226c2b8f83b28f33fb513407ab9d287d14b112d6c3be2493805ace5cf6fd366d03cfb28f4ce3f0f060880db64d6962e997463ba7c05b6fcd1e66babe4b94afc5c2d38c7050c69571d27b66ef0090b
+d = 03c88084f8b78446db431bd6e240a0c050813d2a763675b0ea869cbe183df697146cf29c03479af3d34587a95cd257027fbeed8
+Qx = 15a09436de00d8d129e297ea60e04b704c0a8183d64a77d1c527189e25e21d6bb62be8ef5eb2dbd833e5f9c7d5c3e69c9c01882
+Qy = 001c32ba376d2e9de28fca644b0d567ce1f4ef0aaddb2adec6213d03bc8cc99f9140005bed3cb6c3c0f5533275734aaec47404c
+k = 0132f4763959863a32919eb591799ffb8613797bd0b617c73654ec9eb32e2fb86631b66e28e1b4cc4aeba65ba8c75aa1cfacd73
+R = 05fe0ccbd430d9459e0093cfe2c1d1d3edff8c1ae7111299d2e04f414c46ed2cc88ce9cc9e23e187e87ef551de993f52214d609
+S = 0557acfe6347baafe031dc16032c45559693e2793d9b6d372670b09757c6f4a3e5ae5e55264137d1859c8d9f8f03c25de409bf9
+
+Msg = b38f76ede7441ae0887e689d556f43155b38dab7cde487ce9ef9a46f2957c830d4d28006873fe2368197a6931f6fcaad755102686a457a7edccc8d344e2d2a9162e3d71d41c09a022539ae6d404955a6ad748231aee1f974d4f159940532fb3b1fa0254bfc5805d2fc68696856fadea386c542d3cefd1be3af04ca595e54be25
+d = 051af7b63bf3297ae20517faaa1552f4fde65819dbbff6a52721611e5b7dc1242ed6e69768cdc37ea8cdfd1a5971f06b84b5803
+Qx = 09cd1280a2a79b182ddbd1712dbfd12cee3345a89636d7673a5fc3e1e51400603176e27d538e90005625aacf5cadcc8a8c25532
+Qy = 08b5aabedce498476b4c65ab3cdc81f819c2db670a7236c0357a86f9087b83e7568cc6e5139fb92f81975756d7dc4f48be87df2
+k = 00bba308a3eee9e3ab6d2482bb728bf44cde9eedde15af7300c57c2c1e6fed2ee4e404aeee3923e7871a2ff4ba6df64f9d01a87
+R = 07a9e69664b7b81edc5d47c014696d194b2ca4705b2e79af692b285ec476169d041dd9eef20f7d496fc49b8597574d2602757ca
+S = 01521d7cf6aeaf1c8dd54a7776cfac02967983083770346d9768a2629d606be90d58ea82377413a0fcc3e4e66f05a0d05d933ef
+
+Msg = 356dc86cef7979148e995fc5abe2b14a7d5e4e42c9b3509b4363bb80c581a66f4e7e4aa53a4bfd37f9a7eccf75fdd726f348f6a3f779e6599f61bd1d668517f40453b39bcf35db0852a6a6218198f52b7ceda2ec55fca5abe8e5d93af9a42b9ae4de9530c5870211bacc27c39aa094013db703de2fd3121f08d7e97dbd4e8946
+d = 03d65bdec48972d03811b78150a06956eb22d337dbec5416bbd8185a6322cd8c0ff8000210dbd1326422289071cab65175f5d10
+Qx = 00c9c1bb0a80c4b4863d78003e21ee60fc553ff72968c165f6eb6940250a6cb7d545c6aed3760e42370df79b0d37c2d1433c486
+Qy = 01a9d994828ac09a86c18b9758b3f6b91a5775931a7a6e4d8b052204c972b993a3b420eb8ff7e91df77253a9f5847c5968b5636
+k = 0156d12708324cd30037753c78225d183723d3f15930f23bae854f121094bfffb5d7dece1fca93bbe7457a2237760aef3db8e3f
+R = 071466e80e2a7cd8e6cb6dfde259a08619f880a71899c58bd4cd33c29f7b321d269533720101f2ef70f5b8e8f05c9cbe1ebc303
+S = 077330e08712ad709f855d92355cfb7d565efd806c6a853712916f7c943bfc79e496366deba79ef7491abad23086db341f339e5
+
+Msg = 06fd39a50bf25e89f1071ff81fec5d1e35b6dd68990414ee403dfdebb792627b6a4ae3d2236c159e4441ff90b61ec87b1592c538515f0486b19e58583394a05e6411e69b4285d6d6589982ac0eeb2c912c4948789cad741183663fc070943389d4e9a1150b8f6088fc50605915e9e24b2d98a1f539024770e4820e14ae42ea8e
+d = 01f1a8b5f35dbbf82c102df550c72216a243f986f0325920f6186a16d1da74228cc02be6024c7411160c183c923c743354f9438
+Qx = 157ae8d90fe2416f70a7ce0669acdc0b5064ba650cb5416e59e6672e45b591774ebb2f793c3a58e953da1ac08272d0b949e7b50
+Qy = 06d49b9784f8423812967b857e25dc3af1312a6ff29579f6acb6e155b6848ffac6fbce51bd2d41a22ef955f690e2487a4bbff00
+k = 04cc45e00847818397c6abb3d176cb8bd77814abfc253e3b0d799dff2c3e09a5195ed5e6232873f2783c8e670b52a839e06bc30
+R = 067b418a5395216b83ab00d5568eeb62ae0693af2b0e4d052c6feb70562dcc06ef852002687099dda114477871b924775e8460a
+S = 061d1e4d713689b2036272ad41571759b52a78e0f8a84d1f3a277aaa33ad558f0b71f3c5a99d403e49df1afab66059db20f9f32
+
+Msg = 6daaa41150ea252a3e966a338377307d909b95080e006f13027f2be5059d9208930c5a329994c0b794ef50eb059bc6c215f68cf42260bd410f9bd86d2ad5ab7179c7c92de4a93a5f6aa17de5aefea815e7c0b78a8cc53c21dc4dee037b29c9df4e12343109283ffd5d8a3b81fba1b5e95506c7e01ac056c86dd0ee23bc21af0a
+d = 031dc621200cd174193d95e9092ffb86189c52cdbb9ed937593f2cde7c4a0264b9100e1b8407336c8dfb5520d28a18dc4e39a89
+Qx = 0904bb904d50bff09bae5dd21f425c808b41001ac917b022f7e1cda6e46504781a69baab4a6f0f100c4fff9ced26f871159cd30
+Qy = 15cc300b0efbac707635c72bf855de4290f1b8b70c16f9bd0cb771ed5c760ada04d0ff648f118d64e0aff6a6de16def15cf7437
+k = 07e32b1fc1cebeec3d84f56a67c8ea2b78723e7010a725ca4745e849e573e8e4a4ce11d1af4ee508b80fb5336de3cb53161bf44
+R = 071cd81dfbacbb67be5903cbcbe402c0420adfa9d14148bea600b178fd06278572d34eb46d857085a2a4f48cd4ee9109d607dae
+S = 0347b1029e67a6ea2a45af1f7410dc951db813eabfd3c7f3e2c294b81e1c54fa8c98569efc580b68007bfa316424ac6eb353ac2
+
+Msg = 6378dd1c12c5197b57d47dc46a67949bdd1e0809004e94d49b0234126a08ad5bf8723ebfd132145813136d8b7dd096f56c34248f09a65c34f60c2f80f9a51b3795f3d2518b11aaeaf6dd45a323794080b78f85d629e5fa719b6ab0b14c78cd908befeaef0dbfaa08cec9318bbcb376d48b11b68735c9554a45293db5e9239ae1
+d = 016e6750245a88340b0f0665b890459f8038e9b1366f2fc1326245a88d4c523ec94429f21869ce3dbf75126e58f77241c99efaa
+Qx = 10184fd47e8e1e4d534ca1cf67f15bc8a80921b07e251c22eb88f25395e08d7a9283774aed204fb5c14aa13c63a94ee691b4ff4
+Qy = 1252ad972bb8c0b286c222f42f7d42ca6561bac5e517921bda53e51043f13e711da8a813bb6880678e4d6a16820bab819d62e59
+k = 07f18539d00152f5b9a75d4f114812b87024e8a8f9c9a8d12139d0a74d87986f4305bde60375918ff2dfdb88b6deda640e17364
+R = 0735a15e7bd1f69f4e90739d42ae239a8e9238ad28b63ce291b57cb5b99922fbd5dbb7f74fcc23117243efbd036eded6ee0f28b
+S = 07bb3dc77cdd4138a02e2d5fd4f6ff8516b4c95b8255c629132ea8705c399fc60f8fb660ed3aae52db283aabc3626a5559dfe85
+
+Msg = b898d0f9bd80e083fa541f457d14d853bba55b120424a95e1d9511c8833f48444329e0349d68204c4b4581ef1c4dee23ed0a4445727a72e1e6cde422f7c10ae132a3fe681f9d741fda263e73f7cdf10759467c9d76164086abf6780ad474772771eee22d195339bb8f6235e0d992bbe282b13ce4fe01417f507a2c4fa155e108
+d = 0788fabdafeebb72f6385301e30024b56639e629a400f9c50d402cfc9b5817844f06a451fbda29c7ece41dc9ffcfc625fe0ff0a
+Qx = 09b2c36d221d18189e1617cb2f2ddcd64cdf8a42ba6acc55f04e9722b11588f7fa861a3940820d9dabbab631d7fd4106c60f37e
+Qy = 0da099cdb10dfe2d7c0a16ed332b459e7be31f44b0b2d595dc948f0b073ac4e439f24f215fba5ed50aef3702731d6561eee1986
+k = 00581369aca680beb705f52b6bef075de83ad29034c3d6b2949b551a0bbd100897a079b49d41d5030e1a6950fdb14d70dbbdb41
+R = 04f62415c99c8e6750f9c41c31cf050eb58f61f62eb0b0023d61dfc30e7879d4f5a87e88faf55522631a29fb69d16e15c354323
+S = 06df238f34b5ae664860b43ea11defe3120591cfa371367096006c03e83d372bfb70da6f789665136b7dd1c59894a2fc5038c4b
+
+[K-409,SHA-256]
+
+Msg = dbe04561ea8579672a2b3afa94426a3cbc274b55263989d41a778bcb082da797d84d930ca847a481789524940701cd5f1d11b460bdac0bffb0b3a3abe1ab689c519700de85a0a571494ba0cfc3c865450eba7a9e916b7fa9df55e8a1c246c992e6a0b44b78274e008472bed8d8411633e6520e1a906c5d0c8aafd572fe6f1f64
+d = 01b8dfd64563dc219d6eeb53f2e3ad1d771140d0960b211dc1f757af5e297dc7548d6133ddb574711d466688f80dbd65a7bbcdc
+Qx = 1ec530638ea0663cd3a9b237dd66402adf50d3094391f2343d7d6c52c1d14145c245464a3b771e4b1894462fbfaf440e53eef7e
+Qy = 18349e244b24c8353811c29a60d8e02caf195a424aeafdfd0361846d5ce5eb83da1901700f00fcb85a0c2543b49a8a3ccbac157
+k = 026a26cd09c9329cd45ceb4c798846dd81af67759794f5cadab84de19a835f8a0ae49b12853b1e92822477a73891f85acce4216
+R = 04d83a5f9dad246717135bec6e386ec6b73be9ea6d1a17334ea2003a723d510914167d136254d6cb64b16ef7eec5044b8f2ba28
+S = 03e81601d0c66b507a491c530075edc5b09d770633a4c2355b3b1c7df9b200ebc7dcb706be1696aab70d4c6e1c4a7e532284670
+
+Msg = 48a8300820fea2ad83c83f7d6b24192715329c3f159d56644e11ed25efcbd3d31600a813b909812987b97d1087e74a63b4494cc031c63492b6615e9d6e5b36f62cb2ef88b9f736595800de465789f43811165a5fc093ee6d776008739de8de2a84e878748641be8bd52e5b891c4145f52bbd46644852a43108e93d86352b2a3c
+d = 0422131829608ff730c24ddf7e8b4a2600eaa9681eaf45432daa7d41fe2fb488fd0199d431a1ed823801ce21f4f01a4dd4248ca
+Qx = 06ff24eb0ab812303bdc9a23719caa789eb75775e686b9511bf6e07d60447d1601a48ae7f3041cef5aaf3ed2adb6feb422fbc54
+Qy = 09a351fdc9422a81ebef5407d0d74b52a348caf3cf6e1c6c2af722c408941de154619a1d54bc23a9dfc0c4964f3936d62daa6a4
+k = 0313ec63c34ed325d770664aed3bfd1a16eb636516eb686e806b0acf6f0d117998b30fd52068a36f03d0db3ec13e6989c6f196a
+R = 0088167f96d807bdd61e65fadaf0c56b623db42b831909d12641e4d00e7bca6077b36cfa759fcbbf087c31f294f20a09e0bdc96
+S = 01cbd06232b4c73cdd13208dd254ebf9351745ee6196e3a94b9213e931f141e4cc71f3d318a67e7b8060e11e88783fca0be41cb
+
+Msg = 276e3a986ce33256014aaa3e55cc1f4c75fe831746b342eadb017676b0cba7c353b3a2b554522c12e6aeaf1364cd2eb765a404b3d0aa61258194a30219d76d2bfa98ad20e7e91756cf65e50d7914157f283f2ba3930c0ad3a97532cc747b1cb9c806fff497f0322025a3d02ff407fc7b5808585b91d95523c9d5864efdf7d983
+d = 0095ae8e4c7e55eb5da01acc05ecfe72a4dcd8ec152f1c8dc165014f70eb4e4a7861aeb2b96c418b2d4db58659e76184e013a49
+Qx = 0a3987d7262dc30e8ec11458ff7091ca993bc61f142ee535d544a2c88a47f9601107619617a5e65cdd6d5e1a034aaa223044342
+Qy = 1fc8af29d5134ca9baf92041b6d6aefabccaca4013c55c1581ac05db6141290235ea09650a289907785d282cef1b9efb381ae66
+k = 066015a77c99015ed6983bb379772bd90e03b9c010e695853ebf8e461a20fc12b20bdda47eef856f162dfbd9fd4fc1ec49105d3
+R = 067c49b96e5bfb6a6d625346c3ecff13b8c8b7e59c764b73b256ac970aa4056460000e599a8195f2d235a75cee8e5634acfa7ed
+S = 03ce25ef1af0784645f0579da381542f5b8aef377e5b79193314f84853e2a07a4f1aaa4d8210f3a3c249a879cfa3ea8af43a929
+
+Msg = 6a4fc1827c3a7256faa8ec6a0f3d23559d6949f8cc20e7f76111dc4ebd59213951cbf0eadacaeb8862d6baa0cb298645e4314b1c303bd0d5e9893304d4b7fbd36ab05fb6a5edc3fef763e3a4124d61539eb616b359c5cb55b5e2bec50c91dd95fc39ddf521aa854216eb5a707819fa6f067b316a17a3b146e7cc2dd517f7d63f
+d = 006f2075bd730f34df111ebda919167b1d3358ada32cd6747cb3353bcfb814a77ac70cd51b31a0e538539453bf9eaf9d8b384c9
+Qx = 0bbc153deaec0bcc36c03d24afd20dacd9e78d104d94c279278d04b597ccccae43cd3e64c9e1e58fb5408f376dd7827ede9dc3a
+Qy = 15ae0d803acf12d9d3fd41f74357b1c93cec0480f2e586d0e18f15e569d27d3d106e192ee0c1c570351eff1f463dc07d3bea933
+k = 0314330098250e38145d11a48f5043190c6b44f8572ae57cf83b1f3c4c03ce38b90ed5e157464c2613c82943d78c938fcde89d7
+R = 0160b20c370ef4b9cca3f7dd3c23f70efe6bd80751ca021731bdfb0f45ae07e5f2144c77795aafdb0c3a92ebbef75fb2d334dee
+S = 045188dd2402ad36ae4278a9910648ed5e71d64737651c133aa89850e3bef2207d58ba4169e471a4737962f5fafd50a37a28e1b
+
+Msg = 4b088199bd8c94775d8ee508377d672dbf50f6d2c7370e99821ec8f9387492fb2eebdbea473ea18465565f79e2af418555f10c4a527e05a9e20c9c00b807dc8b350cd4ccc2d87e91f66addf02ce4f43597aa258ac6fbe9365cc2c8e8bbe5c884abc929710e8423cd6722a8f473bb55804159a92a3d8b6661a536b4fb9293bb0a
+d = 03887d284e9ad17d38bc6da9d83c192a434c509340a7f233cebb032b09ab7c4c6e8730b4a80844898616c9abcd16b753c6bb4c5
+Qx = 12a6d5c5690ebf14ecfa54ac97b73e88e16e757c34c6bbfdc9a3a119f298860d330af295756dec41eedeadc5257b202451faa06
+Qy = 19f40ff28bb72af659d5319286fe21f01819952d471ce2433ade745042a47c2dae798199c364ceb99029c2dd5cf57ef5daa2b00
+k = 035945b45221300f83c5fafbaf0645a7386e209d025b3e1dc367819728f630663fb732b251a019e08dde0f64dd3f60a10065c50
+R = 00c323c86e8cc548123d1337936d4be948bd4bce4631a2194c2bf04e1fd714df2c90e3681e41a21d58d9567a5df9fc478dca8e8
+S = 0493d3f4d22cf8517c301f15bde52cef17c05fed2482f3ef15cdbe32c5f0975e054d45b13faf906896201942f29e5693bfbb229
+
+Msg = 848a13465ddcfb2dc14f7bc0db0756832c22dde1e31e4d8b3ae0dd1aafbdf15e954889e95d3bdfd6e5ebb6171fad62592c23277a89e8ba53978c9b1afedfef7e1c3f6d9f31077530460b47834b30bbd84a4da601be988738aa815d3d7e72043243a5288751ee08b4815a017fb5d9bd55833698a0d526b1ed79da35ef0fac93da
+d = 02ea5430610864257c9dc393c3addcd0d8d5bc8aab1067643b08857210464428aa85cf1ae6c743fd2682255d4c8eaa46ca21e73
+Qx = 1e502d3f47823ac7207861855fe6f6aad1fa4f2149bff2643b079da23fb270599f744669b3c8ceb4cb0989aabd43d26d93c8146
+Qy = 0cdcfc138451bb59f34dc82b8128088b5ae0cb8a77dce1895d5ffdfc8b4be24a206b9856954508b82b80d0163b276683489074a
+k = 0426b90275d720d19c6ef5c8c74c568a636257740530e3ad10de0d518c4eaad8bc58cf4506cf5cdf7f2b03edd1caadb28fa3787
+R = 0123ad87c094c4ccfe4346dadad54a6b1ee1bffaa1b7b9094fe2e6ae785a2b77ce3f5e568e43e8b7fa997206262645f56078657
+S = 00d56cd5cc64736ff7ea0d9840916b1e1c94e11611f93b1b11c2ee98c79d92a8af1a560c9938dc4bdd0b84252e259ae5669d1c3
+
+Msg = d1850545c04ea65528849973c220205c35eae98826d169348970d1420b4d872ce233af1daa9e62f6a562544ae3a0633a954a493e9766dd5d87e47486559fdf86229a7c9e1726de21895abdcf2422d438f4ad98d88b45c56742694ad5e11894253270997c049f0f419842482f21c792fbe5613e2defecd485585f1835b6f4c578
+d = 062c757c92eaef41f5d81169ec4968145b5aa2bc1d2a3a5fd000634777748ecb93677b3da12e3be33272a8f0a52300f4a5a37c4
+Qx = 139660fb8bbba59e8f4e95e5ee5b97227220f0e1b293901fedcc6dab86e7c5a9d20c1a097ee2e926a934cce679fb8dcd8d2ed6c
+Qy = 08ac510ddf735184e8fa9693da264194fb78da5d1cdc0bf5faadb33950ca191fe233eb8dac8adcbfe15b4f7c09d5ddeef6bcd1a
+k = 026868bf1764993d650aaebf117521cd146ea20067cc14a5843f726a3d68e41c3fba82a83d406b2275b3459748b3bd1a8d32f1a
+R = 05b17d13ae4d9535d062a2653bae4d15b9b859a87c33e175adc3ef04781bced888f3e93e9804b2251a40b9344c0f8c6bd5be0ba
+S = 01ec3322c5beba4423b13a0528c71739a6b39f7b0e0e58a8274a8386167cadef51e5560a3e9d97447e3d3c06288459fe6569345
+
+Msg = 421c9784d6fd507c82904e1054edf9bdd1efb58a0b211340086069ad38b7b0dd15c2345fa8767ef71254ed1bd5c35f742b1d3f4765ff9007a5477ba9e5d3d5a5cb5fab4efc1cad73701d4776c6c4343f42b5d94a9eb78ae428dfe5fbdd8e6ece09d5b75cf4346cf27db856352225ab04e6ea56661554fbc39916accebecb3935
+d = 048a313c0c11489939fc0cffc6ccb9f179093c4e13141b92dbbaac441b7ae878c9d412066e95615174a24692555cbbe904a14cf
+Qx = 0677c2d364fa86b8b0c79af754e675ea3e806d5583e62087e01590b824d2730e31326591167f02bdd29f8178787c4e1ba9d2496
+Qy = 0e7f78c423baeebf6defe9feb8ada8874cecab083ca2e71d9d8a3fbe846eda69262a1f5b4a3baccaaa4f2cc87220edb1fa6b6bf
+k = 012b8df87dd935775b80c62ed6c76974fa5772939a9e7372cb74e033fbae4f78d75b8bfbb82240cf91009b5bef4d63ded04cbc9
+R = 000590a9e8de60b5cb181a1c11c2f6115c66b05e71e0c558ae203ee18e54de68016f4c7ed2f01cb0cbaf1bdc45218c0fe2b1552
+S = 0521844eee9168a501e235de5fd19c84f052445fb0e68bba687ace45d8630070ddd3b73034d1d65788a51acf91273fd187a24ed
+
+Msg = 7910bab15b6429947655e33a67f41b76f1d7b71534f8904d6a0472c2faded038565272d0b5f51aa915e0d624e9ff48d50ebfa2f09324864f26c29ab73eb39b436c5c459c7cff4d2b62992e3489cb4ddfc05d7366b161a463aa1b782641d93507de43c8cd0a0a0a9d1c644f4554e3edaf7fd794248110ca9387e73ae5d00d299e
+d = 046e2adfe5d3549e1e6fa1fe69a7cbb4ac9b111c8903d544268f8318b0b47d4b78fe3e56eb5e639ad5382e7cd5bd4b2c3e70ef6
+Qx = 12902439be50c97aae7b40328984934d6c843415f76f3821c8e8323aba96ee41359e2ce5ad3179063ea5e2c7deeda4d728d5852
+Qy = 1eb59fe96b269cc973b1fe1f3720aa9aa6ec4cf303c5cccbaaebe6ef7c9f5356ec5e76b26b09479d9831d9f5aa41ae1d61f4c47
+k = 031893aef1baee0e21b50cff7002435b058d73dc4d8301ffdcf1e0c315d18c2b16f282e5b294dc88369b25e2a1a19abffb578ab
+R = 039281ef10b9a2664b755a2db67b3c410276a424edf7681a5c97244eaac5826368a8095f1b9b76f8e490e2783694d5bcf3565ea
+S = 039edd50721dd35d1704167e8cb609f309b9ed73d3c1eece181f9582aabc647c5ec8bd258e5802fb0647372e4c3929cf59ae2d5
+
+Msg = e6fc96e060b956c25d50ad25443f3c30a12d199a47451a49ce88307201dfb15ed816982e8888a28daa92eaf3c5584ca6ab2ca9e14577f84396de2e0ac214b24a2279f5e7b344fb7387e9afc8f0a2b77a4d024a20ce6183499b17096947444bbb753d9b39e5c694239d28f9c454bb05468d17ab564ee6cea3741747ccb7f108af
+d = 0480103fd6180a431c837643566706e2b9597de0a1346a224d176a5b2c54aa4d064418ed654a5d39f4773fb509f86473ebb373f
+Qx = 1d39e2772ff3d26c5936ab347bd5a2940ece42b1964f030c59ab453acd7f44716ba9d88f0828de1a4e730ab27fe1859915818c6
+Qy = 140b1b66b0a87de29ba2cfa799d944b3b898fe7ac43de68b01fb41464506e2f014e0d11bbc0c24996428c93bc1a5ecee5956bb2
+k = 06e9bd0290548d35168f7db7fc292bc161a7710b78ac49ec6a42c9423afea1310597e5978b22b4dfa192489323b2317e4714d37
+R = 055dbf88b6221dff098345226d59d396b6773611ca6e747d26d5d758760d830693df0f5c602859f9caffd0dc3790dfa08c527c2
+S = 03e679447b622c4b06871f2337f5a24150e76efcef9698c6fd463867508e9d7b803667c32989a881c98a90998944c070aa58b17
+
+Msg = c8a8a0d41f35537e6fd523ee099eb45e1ad6ab54bed4d3e315e20227db03292e39dc1a91bab439c0d20e36e7fea6ef08983f390a6b5551ac3b4f1895220b2867fab95552cef9bd8702962839bd9b2c72772640e7d3be3c5889d226acbefdcb448432bc503e5a5fe7ae9ae7696c720a799f9882c64ae0385f656074dd8a6821f5
+d = 013c489e8311c6bef02c8f58903b2ba2a98a27cb935d75a30d320af9a14fa3cbc6adcce09235a9eaf333dd05f4b2f1694985dc4
+Qx = 046a1c0e7753cb499d19b2805df770ba54f1c6e03611c302c73c72902867c51c1cf9ed154b8f30f72002421029de7ba2d8fad22
+Qy = 02aef9c34c7c8216a805a58dd88185f40493086213cb4c85e4d226bb5e892aa37be353d9123e9900f8b0790a43d55a19d78c48a
+k = 0491dcc881731112ad5e9e1df459c27381a7bf8270f97743466e178bf5ca903971b362b73fdbef8a75d4292e63e225396c7b32f
+R = 048425b76147427b8b1969bba3809dd70f0fda24cfb0e92509a7824f027b61cd38441a691efe213f3c331da8c82f94bbde511d9
+S = 00df36683f22e9e86c88097d75409ea297d391550440e4327f67b7af1b09141a0e7a1db40c4b0bf4d60376a6636dbeeff0b6b91
+
+Msg = 3407cd6d2845197cd7414a30fc3df7184da204222ffd65c4d16a12cadabf603de8043ea14f5e6ddcc22d3572dc06dec1a23cd924e1847ae285ecf01754e2d1247876431eb98e897e47412a2330bb32990f9714122109e94b38f82cfdbbf2eeb4c6f88f5dbf9f0ccb47939df8be321dcd9bfd9bb99cac9f94885fee7d443fbd87
+d = 02419bd2200f8e1d87db848b0379741685e680d9affe693eed49d82931030b6cb05d21a4965f4e1df2045c8513a8f574ca9f2e7
+Qx = 0641a6ac72455ceb142e00d6854acc5f8b86db7bb239a5054c1ed48dffb6d050458ffea8adb68613ad3cf5977ea7330268abaa2
+Qy = 1a954ab7d62796e5aed370285d3bf91ddd34eff3b995d04967db41c2171cb2157d85032c998795ed476c891702d63ff0108f45a
+k = 02e9928f427a86c4491a47b31454ea7d497435af81c07bc96fa61f4507494fbe4ffc1fffa8faadc2a44c7e69c4f976661750f8b
+R = 01e8ff4cb8c58fa48aaf61488cc4118df90e8c06cbd88234cc920e5795597ffdc0ab967fa7461082a49de56f02f84cd9d564316
+S = 06e77ac43fc7af3c126f997fe15011fa87a27479fbd5af48e28ccc2c1bedb6c0695291dd67beeec3f17cbfecefbea46b6325fdd
+
+Msg = ad43f8440071285d01fd79244907803601aff4bc5d14c77483a87cd742144d41c68269d76c9a83c09d2178bbcbdf99f927b378497ffdc907a75a3b0ad019e69758dfffa480871eb6e1e17c8539373de611a557fad120d0bd147f8debe5f09a02e56fb607e9c1253ed592071f042e42fee39775b407225a2b86a950d81bb7d7ef
+d = 0722951879a65bfcb414e11712ee9431eeb32319e0ff28601112f89276ffc2b96eb65c7fd77d023f09914a53e2aae2c84652bad
+Qx = 0a0304caec1b68b34c822a2a031145677fe515dda977f6932ea2a3291c6bb4fe8f297b7d3c632f9b3806a8cd26e32403c27fc7a
+Qy = 0012d4c3231898a4202f3f251802c690353ae9cc28ae5089e259149bce444d31a38927dcb42ed613d4818e235884749057ebd02
+k = 0331611e81d3e6e3a24cc829c1cb9087a8c6f64c286e5f1acfb1ba764eea5ca55be544d3cb95fb98407fb6c8f9eb1b3f7ae7386
+R = 056901f11ec69f91b31f7f41f7856752568b7d34ff3af1a2259fe15ae0b01391eeaffb629976525fce5d182663b7b23a8001bb3
+S = 04e89c3155afda2e64c749536392554cc299b70020362e6701e3a649f0a63ae5a5da4efed5c73b5e8098c0cf47d6f4c45c6fab9
+
+Msg = d61a3765229dcd0b4fa6c57280f851ec2bd54d3ee2436935cd6d94e0120d0844adda163995fbc4cd9d7275da859ad8ebf30af9efbdcfc31c7c9ef42bce9011d37cf9d15fb018e117bbc102f7d05750e5072f73d02c2f45509a55627a78cbd9082cbf36807759d1fe2ecbb92ab30cf28434941712d38bdd100955d611987b5968
+d = 03f5b5a772d24bd5454bf26759dbd433fcc7bae4f5c593664c4d75da0cdf9430d7d9162bce3d7f6e13a344259da5a7d6a1635bb
+Qx = 1ca1441b1f6e13138880196e69743206ce09c439a507a11c0fed069d4ed23676b27a3a337c976c276809ae725229c9001708742
+Qy = 13c47b14e3069af070869c12f0f39e35a6f334d98210d33c9da01ac80057911f5a392fb5c8cafeea01c1953e97d47e744160243
+k = 01484461d02c0337e8113e51aa7d46330f57d423b79b580a544d372524a853db9dac0c0d16f733b273bf888271135a5162e70f2
+R = 0256d7ab133904a792987f8cea69e8e3cc674cd3c577f40ef6f12b31f52ac6366a2a3ea2b2272c7bab8be00ca0d17989b6801a5
+S = 020d82cb9b3b1f25d993fc18b7303db4cfab91c03a97b249176f9bb2aa5ae7f589c74060d25058c7acb6de1e888ff44481185b1
+
+Msg = 1f3c23636414ced48fab6763eed5b22537968e6bf08c178b3d31fb1f6ea773c6979759701d94bc1bee7c354272811edec58eff50c93331b22723d460e56dbee90466b894354777b23b13a37d15a84c762caca70c01518bf34d0c2f072145d274b3b6c932b48bd815fe81161d8507ffbc2f783bd212c29b2887af6d2ffa9d2b4d
+d = 046bb4a141c9099d531dd23ac440eff1f5b10f7cf34920b6b702311d490d25344c665ed5211d401def24986c8094165d10f8934
+Qx = 13db47ac0e33af0cc7d74f6ce647fd80cdc1849b15c349bf501c95893be5a440f85b9b029713339fb888d7a93632ea4e0bd8136
+Qy = 1f26f7009cede02e054d6499c9280794184e212e3e1091032fe0e3c189de26d04aa8a5909569017cf06ac2a20acf579ca81f3fd
+k = 046e55a908f13441bab63e5327ac346781399d5a9035a72aa21df708b814b67e420b455e1410014cb53e6ab00f526ceb396bcf6
+R = 06db7a7b03d6a85069a943fcc332cb8c54ac978810374b12eaed4a5fa5342c8eabaec238bfc6107fd03d75dc2c6d258c218a186
+S = 010a4115161765dd0c22a0915a0d8cc01905de91d3f08c6d2d85a6a92e1dc00904f3be67fef000ce19f57157deb9afba7582b59
+
+[K-409,SHA-384]
+
+Msg = ec69f2937ec793aaa3486d59d0c960ee50f640a9ce98a3becffc12d6a6c1c6c2f255d37d29f9b4d068373a96beadac98fd5203a9f229bfc70bcd449640165ae5128e3f8d057769e28356e73e35d8e9af7876f608390090892c67391ddfcc1c332aa61efbf72d54bc615998b3be8ab0a9d372784bea48c9fab244482c75cb2de3
+d = 06f2c6e9ea8109223d9a349fce14927618fc4fa95e05ecf9aba1546619eaeaca7b5815cc07e97ae8cd1e9973ac603f84d838393
+Qx = 1f5a9824584cbb0d5ed57f677caf62df77933ce19495d2df86855fb16456a50f157d18f35ff79b8a841a44ee821b36ea93b4f40
+Qy = 1a88299000c07a9ad0e57c22fa8f15218cd90ea1de5b8c56d69506ad0fd12b513ffbd224cb6ad590b79c7677a8eda47a8bdc484
+k = 042325aded3f71fc3ff0c84106f80a10af08d76d5e710a35d462e880e015a36d063599573ce2044537b9f62b51ed4fd2ed8b860
+R = 0667c74ee2d632aed13cad47e0b46a5176940652d7da613e4965876e7e22d89994bdeadd6b5d9361c516fd51a4fb6b60b537e9c
+S = 026a01220a1166a4d0172428753e98caf0aaac5b0a09c5a3f11b2645d243991d141f59d6cc502ac44b70e7c48d6b0d7b6ec4869
+
+Msg = 70e11efc78d7f079ae41ac3c31c96d3220f4abfe23814a2a4a78d9b1a25e838c3408bd416062e4b0a5cdadf0c6e16a11e00f59711b417751f5e4b43ecad99efbdb2a81c91a034e89edc94eb552c3eba62808563cdf64453a1db07daff8742aea4a9fa738e1322da316b26dbca2954b2bc0de6da7518d28e6677dec6ba8af4285
+d = 004212b7fd913d794fc6bb33e0276e349c052c969ecbf6afc89b28f75a599a9242acf74dec9f374361ba296ba42a38407f9b7d6
+Qx = 19220ebacedc60762877881262c0c3dc0c8a709fe2ea16cdaad3b680d7cc8aae8617f0acc9b5c9861ede651481f39927a24ecb2
+Qy = 18afd77bc7fe54266275fcadc0fe8d4c0dba7a1264c79bc31479f4bcd02245cde991791a7b7e65fbfa907457fb6d450c0985ae4
+k = 04c01ff477786304b24cb9c95ed70ba376ed6e4f6b3ab2f99ac575c92d3801e7f43bab072268705d61d3e2fd881f754b9c84235
+R = 00987cf8ef2b382fb25a6a542e688aa96c098f5d16be0c7d46e961b4a4152c372cc0683993843bf5a04f81e6068843582fca48c
+S = 036fba32f80cd2e66bf31baf87616027c5b107f72f11fc766b42e2774e29e10e860577c0d3a27a3b49754e6a189680b7a638408
+
+Msg = d922fa515e3bed60b517a2d37cafe4c041e5ab4b5c8d8d4011bf9fc4013dd8abf7add71fcfde5e71d6abe76bd0f749e960cbed55711c87b5629a2c39cff48ed7d0feaf5cc4765e576a4959521f9a45fcba0dc65ae618826447e02ce6e1cab5ce8d6c96c3211adbb0660de7df7453f3aa726016941d00d8ee536cc106a603d126
+d = 06baeebb5ffc89c94c3e8b37b9b0904e7c4b251d204894655bf3b1235710215c29820b9d401c9ca7df1404d2d62d708aafe208a
+Qx = 0a0b2a185ad7ddcaa0d8d21b643a14948d3552e25875506d64e236a90d274ad1ca678e628acc208bfe6b56c02df9f5a36aa94ec
+Qy = 0fef210c7137237da8ecfc2f069cb9390c132d1c6ce961f2bb3ca925ee727c967f8a46727c8811c94ef66f20836c661a5cd1c59
+k = 02185be104ad16abfe4fb83de5db067d37ca58510b786b109514debef56cceb4dd6ebe53b25127b85faf9c28b56d6586c26d60e
+R = 0404831192b4bd453c0a7e850815ac3fad88c7a2da27d29e83ca6f22213635a366018ac0038b1fb1e4c512cac15b614fb69b3e2
+S = 06f677c361547c91428d0e200dd00777262a138afcd828238d132c56b2c232e2b446cc693fdc4013f05ce7021aea5b5b2f1b34f
+
+Msg = 4f64d0f6bfc542a0d4347576935bd68ca88524ead03b8d2c494061d0658e6c3e14576b5bcea5f2f992f54cfb52b5c7cf1dfc517205e0454510eef1b7054a8cd06ab53ed2468193f98ff0dd62faf076549ab2a270f259276d5729996c120792c6f466a74ab65035bf38ff2c055b43e2a8b8e2449a2375ddbfc18242157bd905f8
+d = 008e5f66ba53e7caad1feda122a80c32c82d2c32a7237b8ee8ead44ea8f2f01d77c7056b9dd60b92d051f060da8532c1fd0e8f4
+Qx = 1a3d020a0c7e3f3fe5b3d9fa6b6148cd0c481b4f9e14dc85aeffff35e62545654fc313f930ca2e33dced28ec28d0fce6ceaeaa2
+Qy = 13c1ac166c3c088e8a4a9d44556e3344e52e8741ed1a8b526a45268086e2fe54c24d398553d509439ad4957454eb68af594e683
+k = 0095caaf063abba5073aa7123b2c0e1666d29bfdfdfb0c484e18931d756ed0845ea15dee1e9abcbbe4576113a8806aab9476b16
+R = 04d6e33001933221e9eaa78da5874f639749c7396dae90f2da4ccfca15b50ee9e50521cd84d78a098e0c383fab0186b3dfe1b3e
+S = 001e17cc7baa3e9ff4d882da970caf7d55b4e0fb7f0cdaaaa8290fe2fc9cc31d51b34b5dcc825bf6799ce22fc95382d46f3f98c
+
+Msg = 7047d478ec5282d55db8c19c97af10951982d908c759ff590f27d57e2664f08d526cbb2bfde39bdbb1aa3dca5a8d3feb50b868be6651f197abccc9d8040b623de367e2ea1d20ecd302afb9e273f4be9f3f64f2c2eb3f92d5e0e375db6549da2a589f0604bc7146562ccefd15995a7c4208f640e7a17afbca69cda4e173380523
+d = 04ecb22b44e809f89b16abb10be062c89b41ee34e110403e42a20ce59a99afdc22f6f6dda56e1d9d1b8ce1d057f390db111def3
+Qx = 0dbb4a6ed11f36eb78417269c1b1e9725eba1666591afaffb5582c8b4d5bee1d73922b0164a05bf21a12052171abbdd31305552
+Qy = 1eb385afe8588ceaac9f39a5cb4455e02bca48f3d2242730e0f9e06ff1db24344379f96356531676cd5af234a120f4b61f7e041
+k = 01cc97a718ebeffed4ca7a9a4389d6b0fafb73ab000463b68b5580267aec203b6231cfb5afbf7ad8192f0947c7f40d9e060ab32
+R = 021a29f56c31227daf0dc5dc919434978943b80f4b18748bb5f7d6702153b966a0a4af6f209ecfa3aae0e4f32a1b7c6ae58a55f
+S = 06921b2e2ab81517a0785c4ac3be3d7d4b4c917d7a1e4313b123ae96056a2a4a66d9e00819d8c1cca5bc0d75e4e05477c1fcbff
+
+Msg = 1a8384b4771a410663e56eb36c5d9ede8d161a8fb0e31d3f74bcb017b9e31232bb2e2f4c65a2d85bcd1cedd93ef08d4bb4af0095731574ab3f2762788a1ba3bf0ee46684da8d9dd384432fee99ed3c69213d790a5d81b351063eaf2bda71ca4868ac36be1b571024a8bf09039b347fa996d5d161078314e24b7d073e05cb3d48
+d = 051f9500c15ae73d6d479b9f3d2caccc2039d8d03820befc2aae3bbaf65d59bd9cb3c4e3aa8bed5b3acb70a5566047ffad80729
+Qx = 0ee8ca7f55225760c515bae053ebbf4ab23567f95c7091fee2acfff079eda297ec6a7e9d526e12e5976431f9d7e52a2318ddcd8
+Qy = 185e2c17705a2555fbb8afbe8e41ced8ace95c83e198be3c7dcdeac8c2c5bdd988800f1194e553bd0348ebe6c29c16f35d50895
+k = 073f96451cab2d3ca9810e265b3461e0fbe7f32fd6702f06891b97969b133eafd68e53b526b5e32b0d06ab61ecd75e1bbb21b7c
+R = 067d55e709f6966cb2082d8021a313850c53305a3bcc926b6f9a122181665328fdc8e05a88de812357be85d22c61c919876fec3
+S = 063d5ee4a63b1fae39f266a9f826754f5bca4d7bd414dedd16858b5c6ac2d4162e28ab57215c6713320d3d6960f6b55e3f1897b
+
+Msg = 43513d6dd8bb0af7a6f5a2b35f99957d335a48d54f2c4019ce9518b35441d4935518976ab1df37110b5b53532cd9e2c66d9f87ae7f683d7efdbe1775a6c15eecee84c6f879999d0706f6779dc158c111fe8d7201983883bc8334f51dec60004eb1087347bfdab20f8f2f260556681e05fdbb8a6139857fd3bb2df5bc1f2dc143
+d = 00cf01dc4462cca764f4f8cbef48c51980737b9b98d1384b8de9f4c733829db7718a9b5eaa46a8475c2144fe4454cb8eeb0a443
+Qx = 0806457fbb7fc577497c937600c5a9c4df2c20cf7dad4510e5ad617fb2849bfe6956c3efeab6b805cb7b63bf5d1c94e5ddb456e
+Qy = 0915071cee2094efdcc155f893da8d83d9a5c234d0f04f738b7af5b8fddaf1d3aa152fc11894a13caee0009bc106a64323e9dda
+k = 024968902b50febf13be11821d0d316f2daaa07737af45ce2e855aea6ed58f226d2279ebe4295c5d7674104bff75b899609561a
+R = 0549f18f1d654f26ca134df4707694e5d9b3693bb34ab5123ce4d9e4c2b2d9756ddad957a4169fc9bcea29944903080f6f5d01b
+S = 021887355c6360bc4ee59f1badb5325763e9428e60b31a7abed06ef03bff0b1265662d604dd2e0140c355c70fce1b56ab143201
+
+Msg = 752300bc5066d0efaf807183a41725e349907b7339d77c79921ead3c685b616b0eb97e708f3880fce0136c510c8cb53b22cb424af6f1c34633600939a0647c02d8f9601f9416f1d24a51657241fb559c25dfba91402cea43bca1a13718b3945b048725f3df560e6717cfc6ebd894e29bff1e0c7763f15b8ea93e67385f059598
+d = 063a9a565497974c6dd459bea0d1196d74f263f333c31b7e8591499960e1cd79e2ef4cc8709f6d54713f873b16e7b0be42f71c8
+Qx = 18872e9d9410dbde671fc050ab88101f01d146a72d62b630b29790b20fc02cb62cd0ebb5b453a46c60ec2d2c66de8715c320578
+Qy = 1b6af51db1c42b743b89be0900d23f7da80b15f2e7a2a965c7bc13800bf58589560af4697f873b6155194badf5a19a653e63da3
+k = 01d3278e6e78386146fc15006258d7a62a1345db3c2e44fb8d3bf8101727bef254a9fbff157072326a85b5ef4e17c5b0212bedd
+R = 07bd5b54d9c6d6f9c87f4a66472be2c4bb7f521ae56c1dd71781d95440b0a151d206ddf627e5ed3f9c7df2fc914a78454e97616
+S = 075e39ff66ab0e0d1b46f9679b95d10b692874d45fd6898c569aac28a53569646bb29f8556e529ef83a15c574ad5e1c82878154
+
+Msg = f620603489944769c02e2f902c2299dd5f32b5fb463c841b7e1fc0249a85d2c31684bd3daacd97de8291c5d39e84d6e59d3dde1b30c181bfe8d31b8d8e080bd191690a67fa00024ac8c1b10981b40d4f88789ecc58fc69b15417fff34834e23453bb9933a43d08afab74d056f366b40ad167b51ee5f008db151a12b467d3eaa2
+d = 041074dc186193d30aac7cc6d269b938ab40b257d095e54ba79967a377a91b8f73671470cd07f0a3d1db7cf0a31ba9070625e43
+Qx = 18fe9848dc599a759d90530480a6f11d052d2ce21a7275769ba02a61658c3b69ecc546aa6599e6699353ee1d65ce533c69fb218
+Qy = 192b9c41bfeb2af4f29dcd1c43d3fe72a070b5d085d070acdb8c02f0dba00c9471df1dcca1006709676bc08b8ddad97310e25bc
+k = 036447681292dc781f7f4ed60126945354ad1df5987266038c5049d698b2ae12965b6fc58f3e944c4751406087859973d8afcd2
+R = 0541c22a6cb984cafddb3269ba3ee56af64cb36d03b7cd1693b112a7df20f0422219f85c6820130ad53ef69fb66f3326bb863a9
+S = 00fa66b163ec3582760b048ba9a0fba9443d7e908b67d749d732ac9b6e89c1fcbc6d3ff4e02a43ee41414b15ead0cb83749e0a9
+
+Msg = 5575f610762b42ce4e98d7bcf45a7a6a0d66ec7f27d6b8b17f1961249d905bc7e58e2ce0806d467f106b16285dce4544c72666d08b5e2276cd0c4e13187cbda8aecf57b1855afedf8fad39ee4fe009f204e60bdbec79b123456ec2d85631d382b8a2f2c7634af3992e4707f7b4215e2c9d3b0aa8fb08267953883a4213669d33
+d = 010820db54ccf0226161aeaee79cfd2797f87702b4ee91adf8543b3c9e79579d0df8a889e366ec1e0718e039b87a37c24d620e9
+Qx = 02eb4e313f158ba7497130e2d64804ac45a7db207c55d41f39979e0303dd2641c81050fb7f24f2fd2485b90f60985cbb15d56be
+Qy = 0a190fb6c81c104164578da6bd4f2b193cd11935e1f87f14e824c2bf8c82c39f0be1a6de3dfc6dd68af8cb14f6a78f38773a7ca
+k = 0118e911f676f004fe581d1855e5795e5f4ddb33fb8d409d557aeea87895b7c23a513ca0010f98b3a63f2c65da5e3b6c37cf5f0
+R = 060c7f7c47c16b294867cee3e65eac8fc828229a5d3adf8e68e14dee620e9d4e7b78c8b902b5042b5f19c94e621c52836c95ba8
+S = 008d036087b23319553faf835b793c73204cdbe2c1c2463e74de8f404e66ff15ce9384d26149e7300ed1a109afd1f915edef912
+
+Msg = 81cf067411dde2d0ab04fe5fa1e28e6975cdcc571588de60a35bd956a535fbbda4affd0803d244f3f7e6902a2c9a7ef2488691b6bef7f8ffb33be09ccae4c5285265e4957f7928ea5cbabd6823297f59a7cfc9939a49f26bde74c4c69e2d38c1efbacbcfdef011213843158072be84ed3c1781f67a0e2d4e9ba76a585c17fc0a
+d = 059d2a06e8bfd5e14a9bc8777958b85be5e97af892d2cdeb0ecbd2d5017952b5042349db5fedba2e26e7b85bbb31ad313d99434
+Qx = 0af276952a1216ac88ca7a194f5b27b7c98c78c42f852dfc1a2cd4c1a477ed16eebfdc90f613b6e264576a35c45f49aef8a564c
+Qy = 0639625074b69346dc6c617d624d63ce415a36154a817f4e18c59a3b09e01589407077b19bbbdd57b04ef8fc2cc23c673d52910
+k = 002728f7e9b4772ab790af0be9ed5b3eab697c4710249169d2a5782ab3797b8fa21bf8c1de659e3060af5a286353402ab982320
+R = 02a7027c6f94cc236dc8cbae35f9c38102a663b84f66143e2fbf9a152b1a6478bd803bf3171f933f63509d539a54dd348002ef5
+S = 0549ecf85ca1bae6d9f0038dcef90c93121a654552780f5583a7d44a73a9360c6799e76a632bc8907ce4626c0439f1518e3a250
+
+Msg = 8ea18387940035cff2f37278d321b344231075db43c7fa7fee9bd3fdefe5e8f03e7af9deafa1022eb108e19ec11fae34536a4fbac2e8c8139a081a997c080cbe8f3e2d2a72ff26edcc5338b21372fa1498e439e4d9bb12d51cc539f859047957b1b1f1fc30b90231eb06b365a4d404a1fd5a0e5cef171fc95b04d0b557d78ebf
+d = 0405590893cbbe18f4ad99df28b5f9d17f8f1882269aff0b7eee9392859d68927a99c942a3075269ddec6d69c0df2d76ab9d801
+Qx = 06ce67ace45a9cfa0cb45e8e1d0eeb44e94bd7527fed6b563f1069140a3f36e010f85e1ae5ef14d626c78465cae43230090baa6
+Qy = 1a66a58d87621b63ca662130ea342db029acc2d99bf76cf6ec4e53ba71bde4b00e508d332081055a65fc6f44a96f4e947d729dd
+k = 0035f09e0c15b41c958596ad3f5c4bd4a3685ac94f19fb97503fb5fa29115cb18fdff4bd104535847ff36650b7461550dacf2a3
+R = 051775fe1503ce80b3d581ea3e5ba761665568ce0eb7d6a7163d8d025d76002ca7bcf6d688b6477ae85d09c0d4017aba5ea8019
+S = 035cbe69edfb6fb99c9e45240b7a587c3805ab2ed6b0399c7dd8dd76187363b2ba1def66b2c3dae4bc2e40d164bf0f4837798d8
+
+Msg = 6a253c1aa17b2b1e6624afc8e7456d366ef5b1bd78e740538260f395481148a64da0b6a58cd53d7e06c691beae1a616547cd95c4d259a371e51c2c0e334c8a5311ae31e4c7af325686ff9f7a36f731010ee1a9b8a29169ceac36a060dd23611dc9713c615424888bb574ad5f5755d7311bd169336ae986c977a394bf16487c4e
+d = 062bbb4f565aa0f23b88ab9029d33b995729d10fcfc33ba7c4051e2fbc72f15636a834e3ebfe604b927cdfc89f53c57f36890db
+Qx = 125242acf14c7e08e9f2f0194f734841758b1eea1e37ba80b9855a14100a5f0b57bc52a0200cb640121d96769e9cabc45362f56
+Qy = 0dcf52cb899470943a37d260aa85fe83c3869c862001021660ad09b4d73f7739ad331b3566bffad590534207c6db9acf98399b5
+k = 06095b4ed8d51e37f6c723648af4cd4585d9d250d7519139f58a93c75f197c4bbd1142da59769a5fe178415c677caed1c3da667
+R = 041b212a54d4396ddea2898dadc363ac3ec5385c9b3b8ef1ea17c3d2f751d4f79137238548ad759b5e1700d7d78072df3bf84e3
+S = 0149242afc524b0c3583037da153f539aad85aa0c19c6c70852e3c3923df8c3abd0189a2abba872932eee2e6f45e02f98e810bf
+
+Msg = 0f91d0f0139faf3b90a3d4bebd7e96ff6bb6f90f6c68321fb392637d8ab2a60d649a7b7364ee6e4e274e1a8d342caee36cc11c56c54247fb0a8e8ef81ac4322b454dc9a195dc54567bf47ec8d4fa4cd32e76d78ea2d08bcbce3edbb68fd8597e56d5a9f2df4e47b2701046df89615961db601bd8204584a6a6cfbb627e2a1190
+d = 03fad7031cf8810544a3e4bd1382c0a2e22c5a9fe4804ce67b27591fc516ee81dbac841d399327168aa6abd79e2b5ef85df1528
+Qx = 1ef0f918c683be57eeab95d5d1850bd492ace7f4b37785863647774a028e963ee2c0eea801838aa8217fad75c5780f1c36e8d4c
+Qy = 1d5dfc69bcad46bde5539c58ebc89e1db2a3f65069ed963280cc2cf228b2568bd53c6e0e164d6b63a5d3c2b8e3be9d5139a62ef
+k = 00eb16d784e2aed724cf1e4b72fe76b00dc80948c07f9c7524eb0e83bc59c12a8ed16fa7ff21dffb8bbaa82925848a19c93884b
+R = 04a07e79b4f771363ad4c46cde0aadf3df4a233740a89168c97b54559029c51dc2c79b7cc94a0e4e3d2f94e376fe47993da28bb
+S = 0360f559d37a777119b2aeebf00cc17e2edf04a2cbdf74366f5d34368d2eb2c92958e4dc2b7453d5a509407a4d4643cc0235f57
+
+Msg = 50c17c1fe4dc84648e5c3c3ab8f7c971d4c58d8d56d2b5ddd92e35e6792111ed8dac7644ac8a07ca8bb4e38e071aa47b22ffe495e9083f9bf781ac1b5fba571862c909c7aaa7b8d05ddfb7ef61c99700de734d5658f44ae9fc908c85a2dac8e7f854d6d24be805fcd7f873a91252985c5c73129c60177ba8fd99daa87b25a073
+d = 03db41b4f637fe7977c90e4f1a21799baaddd1826c667102414877138436cfae1b9959842b8097b5276f15f2b982ee59df263c8
+Qx = 18eb25bbdeb41c5d14edc675fcac8a523acbfadd6456632bd593ab5f694a7734b163aceb6e6b3d8ed83fa1cf7b5adb9871a6626
+Qy = 14975abca1cb769a243936e65123167e535279197a37d8c92c7b138f31cad4e95c5f62b06f438f94c1a61634b34be7b96f09fbb
+k = 055fce73c9c385f007256253281c6b9d0930d127939026495d0a30f25f77fdb6b334043c39fad4223852f7101fce72746ea205c
+R = 01d7c26e0236afeac032fc5f3dbffc8c03b04417b514adc26d6a4f697b4e87a008d5ae97544a274c25ff66b98111d7c651c9381
+S = 07954191fad321e7f2de95a87d5a9c4527e658ef85faa6622d5f34f8bc2b84c881ededbe0281456e9b70eaf7a207e253d216533
+
+[K-409,SHA-512]
+
+Msg = 3583a3226e2dc463a462fefa97024e6e969c1b13bdc1d228e2d7823d9f7c09012390c2535baf086588000e908309090daac6e6d2b06d2ede6fae838ed47f30b5b481185f607a3586f6dea47c8f84e9d3b96d5b0ebae2462fde1e49d84d36658e87dccf5e30c0937feefd8862dcdb1a1ca373f6ae41641502ac54df6633a8cec1
+d = 065b76c6093d9c49591293471286df1a4444e60d9d06cfa114e175afb5f119d2abeb273b0596019a0ec5db5b5869f2cc827b364
+Qx = 0266321fd15bf6b1af862496f467069819e3860f74a07825e68f3d023985bfbb838a49b6a41b6515cacf404ebf12ce0bd3d6d70
+Qy = 01593c7a8e629599e63d3282cbea78023518277e6731fe8d88cbe525ded554b51a7f8803ab9e330f210619dd07df8f67e1066a4
+k = 035682af873829e16b72bb86f3ee99b5d9f052e4a631b07f87d3b361c8d8260a877231dbcb3f4d461b4a1d4467824a26a5a6414
+R = 00a483dc2dc6408c256fdf63b04d71d3c58a08db7167da217f466cbbfb2d68444c10e87a9a1bb04efd71135c00226e58414d407
+S = 078acfad2f2492f74b0281d53e4224c7544588ca9ceaeb16bf759b20c2f3d3ed69c64615c247213d51800569dc8b00078de68ef
+
+Msg = 60ca58462d53d074b370127132f4e59f5eb8d15594dc721a94286afd082a8934e52462c9c1c3910f8b50d7aa3671dafa5972958d876d7992467b2fee3795a6f9d8a7bd3003a8582ea8c003aa1e02c08ab6804d85bcfa13a815d75c938671f0af0706c68bc70a6155708ca755cac2fbb68b2952208d63e0e2e3d816f04c61bc03
+d = 07e9993f3fc1fdc4c376ef77ecded96006ac1159740bd1b2dc6ae3d97e15a67383f1fc931e460b9af3fe14a54e47919667ed06c
+Qx = 189b82003b546f94c066963239c7a590e064b88bb4548678853545920e413f2be32125e40efb82d2c9582d2d8269c1d408a7ff0
+Qy = 11583b267727ba6c1e17a244ba7acdcd836986089860ee312b6dc2d88a984b1fa232eb0419730db8fb94a5e077009c1d55979bf
+k = 07574dbe04e1ac2bb34e40f32d6f6db364a95cc5770b79888d72b74bd4dbce9fd91136e9e1152424d76688dc995bbf2bea34175
+R = 009e42a63b41877e200829356a2191fbb6f2a9a234be58c76b0852e4f348ca61e7492f90a37feb8b95a6dd6df9d1a2e61c63b4b
+S = 01499fdcc804fee8193de080b085b7513eb8022503de5f64dc12c04c0ba24af30e30f63f0e3eac2c82eb20c6672336f8732ec5a
+
+Msg = c749f9bb92ca9957ca6d0124206ebf65e860ff38a225e241950bf4526cef3f4fa9184ec83f71f813fe852dc08eca6b45b14fc7f2c6a19296529bfda007efe9d0d26492de2a902b45ed39603e22f0a763dfa5deadd97ef6feb859d860baa2cfd1d066c0be0f9f4e0e2fafa69cc51b12e814ad2e33b0acc0bcbe1df8cf018dcd4f
+d = 00c11e2979498695c660a2bdfd105b115bc4ff8664ea15cfb40c725406c6fc9a13027bd1d72ffff6258f29e4e19b845243444a7
+Qx = 0904a9bfebc23607c7c89b7aa89315343852cb894f54fe42ba4225285e58c6bc318b55691aa6a6ef22eb11f44cbda89f157d7a8
+Qy = 19cc1826280e54832b455f0ce0cf89bdb62e973a8e819fb776b1a202b4f207b8baf9072929c9e3f6a8ff996d6d529de899b024e
+k = 070fe023c9341df9348f08882bef47bd8dd7f13db7215d1cd52cdbe7919031a62455ca969a8cc6db0a05a0b4befb47c142c4f34
+R = 035e7130d59d92ff8c4f264fb2c346e052bc305c7f57549a0fe43cc7cdac6aadf2ce1939222decef4e1f900e3c2fb2c52bf53f5
+S = 0008d5ec1ed2091309ac11eb88157ba5122bb9b5c858a46769a130f7a941818445664ac78325e0b6d2a11bc89d08fe0e87a5bcf
+
+Msg = 4de8414780ea20f7943b1f1adae5e3962d96e828fee43bdbf2831bd71bd25df2976a3be37a7a667c7fbe1200de578920090d131a750c9bc09bd95b261234ea8cc25423c4ddfff5656d6b32da6e2f6f530e6673a8660aeca31273bb9a3a21bbd7031a2fa71ba37c004d3d1c64b2c0798783e47b2efe1a208959ac16e35d444245
+d = 068dfc23c6635bd1fa1076dcbd456ad6e8df7ce7c1370fe275803befc4ffad007fd062a61cf1d50b93aeb9afe1aab47a65af82a
+Qx = 05591f8cb59ccea17bfbcb74e69f05218d16175f0547ab95f507ef8d7426c077b52b82dcd06baf6eae7a66bc72422236e589e42
+Qy = 126a01d5c2331a2d00949e07ea9242ebb50d830b0aaa74bce841d4e43bbaa9e9aaa01ba25db7a8a2f4d72977c0f016f625cdebb
+k = 070682c9659089a703dd9fcdf2f3fa0c1d1ef5fae3f8f1b3dda55d9b611770244f8926898c904f6952c1847d287bca21db4dd59
+R = 02734111e3b736ae795929f835701bf290dd50c0fd625738ab2769242c1403197a3f4dc29ca618c2e292c6bec6dccff71adb698
+S = 0755292cc5363fa74e0193a806879d3a275b4beebc97250fb230efbb8364b2a30098c0488bcc6e20449622d6a5fd2ae24d7abe0
+
+Msg = a081d54232f84bb19dbd52ec3812748e2e6486f6cf1b177b27929504ca878036547eb43531bb5b3edc81bfe105370427e92831d2239cca0106d031d9fa8da9cf89c6fb6401377d5936b6329ccad854e5567181b8f16a37c35f333eaa0ffe91d727d183fbab935fdac2d5670dafb3fba59e4fa2df1746c58dd8360fa08af7f4e6
+d = 040807fb888e1d9fd33604546656a493629d94d4a0a9de2608962225ed158167f9e2438abe2d12a11e2adb6c2b66ed78215b0b1
+Qx = 1787c0e6c55acd69bde9b0a84d6022796d5b5c60fe5357bc0fa4386c16f61b38bfeadb6cfebee7e7701bde24418b8b5642afefa
+Qy = 0d9579d271ba3d5e2327eb863cfdca397070055b97714e385ffc2fc23528f696dac1a4d0e535641f6c876f1819f2672a8c31cdb
+k = 010b8f5356d8a029659492c444876f1d274b82681d4f600cdb5fb2afde13598ddb71676d9ed86e83351c70678886e8237a865d1
+R = 0304f43f9705d189f47ee09a079494030b0756993a93e4c6ee6b5e664f63431f99e505747c24377e5930f13492483e6cd06ebdc
+S = 0580d4707c97f0330f908042a6cb2a2b313f07bab34774ee03bbee63a4ff881b68def47cd300fb49deb49829bf486d1efad39b8
+
+Msg = ea60266f1538565b3ff42fa4bbfe319be070329059c52c8bc04a7da2824f209c1145a05e551ea59ded8ca8439c328f6907da4e81d658937df614be98c7b8648818ea80ef40e49aaa4431f4a211d62acf2611f5d60c446b2b25745078c643859be1b12b3141a09ab765dd63ea1f2a2df015eca0840087a5db378c4c4cce76cba7
+d = 033bda0a02badae08fe40c239b9d59e5bfe1c4d4b9b7a5acda6790bfd77ad08dde5e93a2da80ec54a7f88146d72218bbb88aa10
+Qx = 02dec536832c8acf007daa66a47e4eeecfb6991a359f8c412299ef56c6ca2faaf18c4db708493e84786a7837ab74c5fe0644cee
+Qy = 0906c8f603b579cc2384e0803d31d577f7c91c55406db3b2db91bbca323fdf3cb6d010617ad1aae7bf414c4d974f22e6f05af53
+k = 051e8d027e62db2397e4a807d98a24455a76eff6dc259ada89e794dec1484b44724894eeba842f60b73287642570460896dbe77
+R = 031769e6777444095d934d05dcdf82405c43ae91ad5fa9201568ae2aba25712717f1af2b8f49f6eef373237bd70c34889d0d271
+S = 0023498aa50ee095f33a4081bfd70a9484089c85fc7a4569f560ed67243745c823cc0217d29e2938f06ba9c8790650d10fa5b1e
+
+Msg = 82f38c9405ef0d26bcdd5b3fce4fb0060c3095f61403418e17c337933f0563c03691fabd32ab5e896c593439e7492a9970ae325c67196d9e83fe0f9780409a930326f7e6efae035ef8c321cb9ad12461edd5cde66c04739fe079db65406b3c2d22f2d04b1a4335285513d4ceb901d2ca2ad10c508302266c2cd6079ff14eff4b
+d = 04ff431769d26b8837d3e1295f5464fe82be29edefba76323e92078a6483ea0daa96221549102509a1bdcfd46a5a2e5de10c39f
+Qx = 1beb74d427d849705cf26e26312446f27a7c5ff26ea9dc1aadca763254fe53a622de29cba4fa81ee2f9e0319e752f72be46cc7e
+Qy = 08dfcda35a00ab77c3c47dbc05b0678cf561f575369507097833e86e523dec879e0ae9583b4261f7a73c9dbd417accd4ae6688f
+k = 005aff3ad332af23e0dc38c16853252825076d602ed4c6d947be751af5dff3f59611e6166c31740b5e5a167260adf2a5466289f
+R = 035c4e8e1858b9694cfef3e864ed959638ba309ba2066a28fb9d0e02a66cd4c187dc6fd8ca5fabe68acbc2074168157b685aa6c
+S = 04ec2db89645018f9845b7ae31b8418a767e3570d401f41db18e424fe861bf09114d78606a056617613447d125a283be5bdb6ae
+
+Msg = d8506fab4f681ba4ae86066aed447571eba4fe04e6585fe3be6af2ab1000a3da68c5b0c711a85ddf3a40cb7c8944eef81f2094650459e14f5b848e6add7e580b0198070f873eb3ed5d0728eabd92bc1398764b94cbb4cdd7cc2027b9762dd10782658cd9e8a5022ac062fec535d892198c8a387b3d2b6f7c92b1af6ab7dd9e4a
+d = 03f85ca1169ca7e9df44cbc6bc7d2868c9d94e8f8b699a42ca492dca0914eb5789a9032218dcef7f95f959c9554a1cd83360439
+Qx = 0aa3c77dd4324258bebe7da5338c772d3496e3fd0e57f455459542f1a1c5b47692f51c3815c9549d0c23fdc1ff610fff6847ea8
+Qy = 05e626d6aeb86dc51f3b359b10862cd33ac9927e38127f7f17426f2369d62132a2a62fb6b8354c5ca0b3e5c7c87117b4f777a0e
+k = 0495099cc73c9930333ae3f9d0b7057d7c70e2bc7c805c0c6a44404739b3fb68f9fafa53033b54b7ad7bfaf4bbf7baba0dd5a0f
+R = 005612fe87c6a3a164d269da902aa43c5a4e0333770ea6334f05750be3f31ee758d169291e15b1540d40b60d1bda279599f254e
+S = 011a633bbc058550a597585bbc9f33099eb517795600b019255f649493d4a6dd533be8b0965d9f9d9698677491bf929198ff34a
+
+Msg = b3f30d34f252a4c26f396079e773142bf61c0981d912333ade3de4e27cbc72cd8a16b31807f0c46116f87accb854487d83ec8c6a61565e6fca145eab70048245db08616779d7047db63aabd90dd15acbb05eaa510072c151c0518f1b34582b95f43ec7b9484b2993c176de79e84566764467f72392ef31619426d159c91816d4
+d = 03a97deb36d68f81f50c8829d412ee5de7f9d775633cb69c09dac558182039e275fc258240517a7c4aa592e364765321f27cb12
+Qx = 13f0f4c16a47ec3a46e7a088c1b6a63ef61eaea46aa9b2c532d8df84dbf64991bdc2c81ced3635e562d1403dbcf6aab2f8aa9da
+Qy = 03aaded3b99a454b820fed989dbf6430ddcda67db58e356397d06aa137fbdb365ec43994abd9c0a9fadd2887da9539bb4ab3c44
+k = 06620ad14a5835b9e9e104607c317cc599416683a60ed8865acf78ae1e861246567cf9d91f759c2d4c82cec835a4784d3c231f4
+R = 068faabcb7c716fd73f129ebc6625f5b4660a88e47dc7dbcebab321051a61e46b74409e2b0af420e1671ef4efe04973c43471ff
+S = 06851e5da033da0f28a89dbbdabe93ef11331c55cc03d5b096c0522370be681241fbe71d1349f219ce57761c85fbe208ac36a36
+
+Msg = 0fb13b7c09467ad203852738eda5ddd25b17d330e82c279630b0e1f0c86681f67f6e537fb00da9419114973c8559306de58b0387d86e52d821d982a60769d2f15fd5ac2ee6dc55d8ac04ee247282cb2866b8cb8b4d7b4b6cfb33bfefdff09a73d727193e5fb939ff66ac5fcb644a44f9083a790888cc538c5eb435243c6a34a8
+d = 03b1da0ffed24e1a3b5ba22bd684337f6b08053591620541bdad50c761d66201a2cf21a4cc636426456525b598e96baf97d9851
+Qx = 0116a1790e621272b56cb4579ffe6ab629a2d077b779b73e039d74f58c476283c110bb18b9c9ed63de7288dd678064de68b7df6
+Qy = 122b43afccb88982f2e07ff35468178572bd72b644322d9e1ee68f78880169a83a5bb88c6c994762a7e8d80e09333487ac30fa4
+k = 06d7a24f0fcad549e9c36dbc70ce264a75eb37b74db98b1f6a824ad1e5635be9818f45c7544927807dc0fb3bb5fd38556e8656e
+R = 0232339b50bdb772d15f2cb8973f6dd9397af45cebb69adfc089bb802e9c4029dfb2078a8a26d7197de10638ce512e5904ccc5d
+S = 056add03244174966d53105c570e8fa660ae8c5d53316a24cd26f24e29e4b7459f4c9daef07442247b63665f97a3c07d91a8706
+
+Msg = f9b8124281628cf4e1da0cb4f021c8d19d815644cd80c7c8de4cc62722904ec4cddd26cc4891f30b15098a25ba6923c6abf4774deb6e1883fbb409862f94467e75a725e7154be860fd58347577c83adbf18535c54b102220197afa062cc1c84f6094490ce488af4a08d2c5b808a2572e18a59de96c87162f88413795351cedc1
+d = 040bac7e0d3b54c7753c79d43469e310d876015d948fac4e3a9765444754476af72330e88d79ee6119697aafac8435ab5690754
+Qx = 0bd4fe8daffe47bfdfc43deca20b15da7c999084bee8983c62e3dd33740143c38d8f432cbacea51e6f53994265b2d8f4c393f6e
+Qy = 06d88c33c31f4e143b13bedd5738bc1191fe6815a099fb7b44617fdeb08daa0cb74edab7f9a8c67ac1e9c0f0fb21a9f02ef4b6b
+k = 020f2f6fcb3e471d47f21fb15301784f7cf3632dad3627a9ebfce587c0097871eca580bda051b100f991aa6de5edd3a7684e839
+R = 014f8884b5107e9ee5cf6f5d137ec9d59a85a6fa0431053d58a1400fbf0d518e8910179da1160de2c6cc8ea8ba8f3af8e0e1f6a
+S = 019aa8d55c8d876989f9b9559db0576f91c4610dc9187c74aae2d4f212cd94d90dd81ee4483d88d866aec1ed469c5e3eed7d90c
+
+Msg = 4e3cd6100520db050af0daa69fe3cfe6603a223d4f2a6318fc5836db8640d4c7fb80bb781302036d2d6fb8e552b4eaef3133b98ba2d36b9ef0b86243b0391413c73d48ecbf1d19170f1b3b781b35ffd316afb1d55d1dda8e91eed5553780cb2714a93e7ece698b832e853e2589c5ba2b8a997bbbbf625071ded66762af8cad42
+d = 025b7eb3bdefba3c5134438caf968f615b315204f348006f82e8d61057a8a8a853230cf0500f9d0b8c1551a59b9184862dd2ed9
+Qx = 17d2029cb711e52df416c54b63a95a66602a1d15c3761d91071964e0128c91ea766b3d409f72d9fbb5161a459c3fd7990f87d88
+Qy = 1e71a9c66a4d4dcf199aa329e44b99f80640fc760fa7326f29c273aa13b153df5277feb3c049e407630173fdc9f735d7aee4e10
+k = 0575aade2692534b5a1a17d36c36973d24dc501c75c3b0b497a3d2fec80c67be7107988e47199d4863044fe9176762497b5aff3
+R = 024c6004fa92cad446b8339917f517f04d22db47b3f9bdb83d863dadb5431866ce21b13e780495bd66152ab33eeff8830cf8538
+S = 034aa568aca7be851d276d2235e42b6624df1cce2b97f6413dd3fc506f0f18483f95f911feb0eb220415ac593f2c93dca0808fb
+
+Msg = 5411708381a65bef4381c9e13a04cdd5ba0c15829f7f25ccadf695f635384d8e4704cb562741747831b33852567f42fedbd190d2980f1bc921ce01c17d659d4bdd7eb787b3927fcee659dd3b65132496c687f2249272a473d46326e66b3cb78dafbb522390162c168f73bdec88adb145e6afecd561979846ea4c8cee38dc1686
+d = 0673b3a2985c95904732632e5d988d8d437a60db13215bb6aa880b348f011c609a1e860461427a8cf0d622abc47f910f5c97ffa
+Qx = 0c4f1c0cdc44d867ed38d093eb967bfe285df897868c83ffcc0c53463e3852a1b2039506d9508bf01d0d79ae537e42fa2070a5e
+Qy = 0c2bd9343041c2c4100c5d795ef355c796a6ea7954cd729e11063b14a27fc2c3a9ffdb3647613b44238eee17d9cc49e8c5dfbe0
+k = 019a9509f5f6d947532638a3c80782b556c553edaee9ade91e457f7b5d2c9055572fb116f52cf4d3a2a0eca72fcb32b2f58e952
+R = 02def440e968d17d9904c5640619af2f447f74b7c067537db4a15be87df4fe68f44897047fa8af146462ceed4beae36d54e1aaa
+S = 013d5b00fef639c556d66420090c2cab1edc57b7257dc35addd62a5337300e94ea7ee116e06b744da1b575d90da81e8ae2cd424
+
+Msg = 23757fa60fcabf543e603d8b31ef0cc99b3ed16b4816a84e01dbfc858872fcb79fd03d2f8a1d4f28c25dc42a39e20c34f81ebccda1682ee9bd22fe323e7f8ea90cf4a2a6ebb634cd1153cdc35f7306f28a2efd822bf23131baa1543d0ed5ab4c8168d3199983fbee117085f90550ec3ffa2b06070d3add1d707fc2593285ff58
+d = 00db7dcac414010b816236cad584dabeaec1da76c97182d1b62f87bb7fe2946a64d10430571b2b29ccf2ef72c969a9f045f1f3b
+Qx = 1f2a6cbb9c1fabc8db2848c74d918312267888d822b7dfd1634a543dcca4be7c997239f6281d1d8b5da9adc694706b7b19cfb0c
+Qy = 1bde57a2ac15f4e6b26a373a624588a3379c8eec758f3c68695e2eb1856075d90085f43283d982526c5e57913cca5e2b4169f8f
+k = 05a3d856ad1d6164993cc59e70f8551e2408da92c7e6cd52df51b37dc22e9ebc42fbe6b83c332eedffd4086a382056175ad7009
+R = 0489b0344ae4278a0376dcc64ef9ba8595bc2fd62ad22d42fb431d2863d8ca353cd9e59de4ac10108fc247d6ee9ef643f6bdb3f
+S = 06aa27335e15dc910515385764387798cd4a9b4cd6d99d7c42e07fc04e2bfedf8dfaa7bda396f88253357d3e2545e895d9aa3b8
+
+Msg = b976314d2f066f8893307a726f450dcf2cf865c170e90e6908ce9787eec48e1e2119a731b2bec3c12fd4e6282a393774251bcaef91af6ce57c63a8b45bedd72ab862cd169b7c84b8f6a72084ff823a96f2f8eff3483a7ebfabdabf0998377c5a6836d88135cf61c65a0ca7ca57727da68047dc635c17ad13731035fe9a6402af
+d = 04717efef16e1ae267e155aa1daabafc68515aa391dfeb73c13d01f3132bd22c984228dddc4dff4c39979e7585acd3f730cfcfa
+Qx = 1526c58a3de46c95cb0527869f7d637f9441cb5504e6a01f339907c6df3d079361a41571cf0a0f11996028a41682dab5decf786
+Qy = 1581903be8a19bf8bde1d89bee0d436f061ca1a3ddded4b7793fbc32ff852671103f34e16d469eacdbfa457643d1b18dd1c4107
+k = 05c846bf61c068b421efc472469ab1ff8d9f34847ae0065ba6f4a000be53727b3fcf97a780362566e13ebab84b9ed5f0cbbc225
+R = 00aa138e742ae81eafa820632f31e87bdcfce6b909d85805e46d87d1cdb8b968907470c7ef5806accbf6245628c70d264fdd95d
+S = 04df507115384327f7b8311dfd1227c19a6124cb9bb5901bed45d8d5ca45db0903f53e7bbf136350e66bf2b4f3d978f8bc546a5
+
+
+[K-571,SHA-224]
+
+Msg = 964ad0b5acc1c4db6674e86035139f179a9d5ec711b5bae57d2988456bb136d3aade7ac9ef10813e651ae4b9602308b071d75a934a6c012eb90c5eb9b2947b50fc97b1d36c5bf9eb13a7b06c94212c3dcdab402a563262298defff62b836ead1f78f9d20713710fb48115cc5045ba15140fbb4bdf516e4150d830d02cf30963d
+d = 19cf4f4d06825499949f9e0b442586fe1bfe3459813a2b92cd8de0f775a4735e02655702ead8e60824180761808d9e816d60bdb0238e1e8039ca7bb63c92e1cf8433ef447e64ead
+Qx = 07b9cb1728cba80367b62872a986e4fc7f90f269453634d9946f79b1fedf42ca67af93e97ee0601bb3166e85357e8b044e39dcc19e608eaaa8a0066ffc48aa480c0e1e8d5569cbf
+Qy = 580858ab9223c2b2ea58df506d703d64b387a78ef43846894e7a2e47c02252bd2c1e3d21ada7c21d50a08cef0f9a189c4e850c058cc57c37918251b5aaaff2321d7355b6b555644
+k = 0726d5e317f888dddc94c73acb14b320ff509908052868f8c6b14e531ca467c1f7c8287476674efd0d636ca94c24a69d15210bb43a368a11d3453d69ca80430cbfb8b6e45d8f21a
+R = 04ec6205bdd8f7eab414110ed620dd3fbbda4cb3ad9e5559a114ca9344782847621961a3577cbbe43d94eff6ffc8dd7dd09c049239f026a928301ffcddcc910bf196853edc86d31
+S = 16535b1af98a75b9bc0f122ca3ce23a01800fa33b43584a94fd8a8d6f40077eb739f07c9f0e179a157a28023735fc8da2e2ebbee5f7308925900e657fae7c3b321f14fc45346f89
+
+Msg = baddec4794effa668cde267016dda67bc70b847919a9aa595f93ba9dc27354399ef7a607fbead31e57a8ce698beabb10f313d393980425e67cf95be45d512f00e950c0c5409573ddc3d556f23daf056259ee8914e860562a674311452fed780b3e0317a7fe93baa81fb98df3ae4328b28ad0ac8f8ea33efe24faee658ad026f6
+d = 098521a732e72ed945a549afc92318fef7156ed1d1ed9bab93b581478cb2339eb32bcef705c9bf61cf2873ddbadff8ff3806740a2e30ce67d1807a8179dfd5d952e6f8a583baf81
+Qx = 1e09410bf4f84d53a2abf8d106fc64e643edefaea263dc98c308aea16ec75f083b3e6b442ab261226c59ca5fa622db68f5cb5f2d1d465b01d0048554b0ccbf67c0aaf934d2365f6
+Qy = 361e5b43d313a62c7b3897c7db8a42116127138a1009f0bf9892981fb4fd6ae231b8940e7509f96e2a49285143010dfb4516ff810a91a4d9d2974c522ff343e93e8aad00aaa78b9
+k = 128056de96666acd09b93c5db7ba1b8fabf57251ec480d42b702940b5847d2a59b04eb5101bb3990c3ae2a41181f19a2afcf08424f8b922a95df6b292b1856dc4a9dbb1c717ba5d
+R = 163483a7e0d1012695ce0c113ec8fae3694bccd40fc038d4038f81bd39e71c969cc7f0af8313a9fdd3d028ab24a43279569dcba73fd78ad74897964ae715928b1cf7fcb779b12af
+S = 10aac6929432a6bc7e12ffa86e4d2421e0535fc44a1160fcfbee477c29a987e783a7f753eb2278ce08954c7e90284d2ce7c42de103a9c59d8e4c459b457688ad515cf156cfc56f8
+
+Msg = 7ef7138fc657492d229054f8a50dcafcfcd1dc06f1c16640af3f658907e2969248b54416066eb119adbfa23b8dc578aef18bba79610b9cc109394b900a25e55a779230bb858b2ddd9499a7775d392328db9177aa9571c2f61dd52010b48502154e914a0c55a54edcc04a6713cf7bda8744a893926118b09df877d1a4f3d95e8c
+d = 0336fb21549e397a190beac38a1ee10f0551952da15f71e11dfda415e5ee08da2356f114d450c661f52b2b32cfc7b9be61732672691a079f0927989b7e9f4efe6095a242155b641
+Qx = 316800fa2d8f8f3f9aa87ffb628dd7b2f63d4d8389ee86ed41bd4c3eecd3f3836ba92e2ff7ee5626213f9ddb41b43561c5dc0bcc3df0a872e4b8026c09c7b52b89b4975a43f60b0
+Qy = 207f956df58f75286232967dc1d3e6507634f45c0014c48b42868fecce5b9434463abfcd2b3722a7f5ed25607270148466f6ffad6a8c86e538640ece80e84f7368d33c68807fed6
+k = 1517b3524b6d43dcf3964f7c35c89bf14dd1542c37606452e2035ff0bd0cd1edd6d7b801ecb1f573e957131c0b3f30d5006f6e4748a11b9db10fad41961f4ae53e848c6dc6e1a52
+R = 1ffd4865dae7387ed797c5ffe58a929cffeab521e48284bd7d4427d5856e9d2582b91363f1d353a0ab1aabfc132a778a516d4033c64cbc991d724115d72ff8e94ab4f95a9514843
+S = 10f010aaf1bb714042fb8cf06a9501dfd1ffa598d6b3e68e7addefe00e18f3a5db8414d625e374d9ae70bea43b57c6be4a590c28e50a548cdb2e30dd9d6e3ed1d9cdada9f8b0049
+
+Msg = d58e1ff1d49a471d0567ecf8f29173dab5fe5f6184ab4cdd095c231fa7b82551f99a482994a46c3d8ebc07297fc9e952a5dee7d5f199b119f6f8b250f8fba45701ac252db725e75c4da27ad77d59a4eac448e54a277986740dfee6596811e59afc9755e53d24b826c09e497e29e69a22bbc85be11763064e9ecad7ae66458ca0
+d = 0e287ebfd9ba294128cbd484fc5121d271cd33e685bb1804f09b40aaacf64b5a9f2cde9b30a4a02d3a9bda97d92f46bb8787b3c61f280b1e1a0680f1f0679d3bb34d53725d62e52
+Qx = 52903a7afc17cce078b4b658766a67f2f75ac04e296757fd762fc05d6a7b4e4151598a872eb4618efcd06c43cdc3e54f437c0ef1b091ab5e4927d3ab4227fb24d4413e0327abb84
+Qy = 385e808bee8dad1a1b84d644aa29fec324dac2242709421479fa7a712d18b54db59778724ccaf4e51a27da090c6dd0b7967024db0a8684944b77295c9624ce3aba24ff48c86ac85
+k = 15e8cb22e371965801d99407d96200015ba58fd7eaea52c03269d8a374fc7aef17fbfd4480d29b781292e179936a68ed175802f34043018ed1d6b5a4df667d859cd2ae53ed3cfcf
+R = 0d3a57af73b7504ef18c03ed2c52aefe1d1a3f0e27f78c11d45e9825647d5ff6e97af51a5e366e52e01e5e832e4264a1d5b6967cd9debda59c955568e4c8bf804d843a49a0c5401
+S = 064fd7ecf4470f07b4df3b3046041e49f310a463210571606f00a1915c5220a27bb7a28cd0bcdbe374651aac06d4d9e017e31879b7819301eabfe3a7afe4b53f75ccc465815b4cb
+
+Msg = 4949ba765c14c31f68ee0ca26bb42ba2edee63537de4a6f5c42bbd862c21288d6ff48145260365193c6fd2b56dfb014da26b8a483776b717c6874f627c9a622154b824565b23e178240f53ee9748c45759ba5c035b584df0f09504e95eb9bce0301653aadb860bb25e6ea6b9606e0ec3bdb8089e6aa0d5763d331757490715f9
+d = 149de496fa8f88b2741864d0c35b3df666b87179b7bd06cd426a45f13bc87ea9f50dea85e1fd02a532630e0e3a231cc3e7fbb7c7ba85b40cff1124e72c677c6a3ea6aa40ffc64b7
+Qx = 0bb610e4308e229e4b4ddddff5c4633ef2ab40bf74514433bd068c7d59a6260ac79366dcdc039d5585e660a4cbee990a2cb55a99ea3d26dd9df856b0f3ee5b968bcc349240a9a2d
+Qy = 3e3ef4be63fde6ca09f12f8220e1d9b5016f267ca5aa09a2dca8a0e0feda9647fe0e1f7ecae7147a10ff893f69a4f74172c6e9a62f0c5bd96d49b47379c9c84f5ef8e59dea104bb
+k = 1cffdb963c2c8b8609809e998075299776b44d2808df509773f310124b5f318d7431f1ef8b38fac5cd5580348abc41e6e6396767f4780656361dc9a71dcc8e7c9239d6eec5cdb94
+R = 0982b9989c92e1a5d25dce832bd8a3f602f0eaea69abcfda285cb3841fe3f019503e6faf8a693712380a48a6af8844b6bd718f0edf3b57662a4fe82ee28d036ecc4cfc7310871c0
+S = 1678bec58d69def3fe35a64810b27fd06bc29d165593990f6f42c4c7676fd5d4a965fc92cf20ab8616c7ac7b4b308ce6290c5e8b4edf6859fd6f6f01878f2601e22acaeb5ce1f36
+
+Msg = 5bc63e5c50b1650f0ed4a599960f1e4e11f6c151b2123fd71d9e3c44662312a74b6854290628e20b30eaba81555acb2fb49b640bdab2528619c7fcad0f2a2880c7ea232d427d7c935fba2313370fda8863a7e7e203d63ea15d0cfa083e716ce6068c63fa616ddc225c9e413e694cdf6b355cb1293af5d6cdea51168f5634e878
+d = 17605d7c5873d870462375d741b4bc6375f3d47f7f5e9d998917adf2137a81e63b66917b3dda8968930c4b850f2270eb3187fc756e2beeaa67fe0d73053e6cc0ff0004a21250551
+Qx = 0d8ac3e76c25cdf4902426569763f4ae0638ebb1fbcee6e12a4e0b89d6d451cf420d10441a0a9984710dcac13bfd7ba70370afdfb58e2d982ac367e178f6834b4cd2d232e7f246e
+Qy = 12b5fd5b686e58df08b695fc333937eafad6006be5a7bfb1426206102a79bc32fd9ef46e19869448fed0e917fe059b76c8b5a9c403c3921ad07e6c19ca7bbfeff5491b22f8bb961
+k = 09179b3ea906137dcdbb97b27f3690bbe3bc4f1f57c46ed60b8503cae97602717a0724e055a5c52199ae3f08f1586b87fbbe514667d2eef2fe44092f3c916976c7b71eed67e8fb5
+R = 05b28342703c83ec2df898458fea6f71030e4e9c567d140ab09cc95df29ccfe199837cd58ed00d07241988bf3c863504d065ebbeb8ed11cdcb02da0a945ff38ca58d629f76832f1
+S = 01442a5606791569749b5a9f20ba8eaaedd1a2ceaab2ef55d5d41271ba23f6a5b6a33c76763fc99b291b07283122596a3331fcc9ac038447f3e0cb54872c140300fea65d7809191
+
+Msg = 610f6633718e49d232b3798654095e2efa0de11f41258b27aa01956480c870d901efa77e109d5f95f1f5101d3c90fc51312d9b3019d2e42e0067eed7b457dc7fbe5466923b62c83d7347e4dada571b57813bb9c21d5e308519b8eedb7a7706508ad04aa69698e03636eb30fd9fb363ef3a185756494ee01175b16847f5b68076
+d = 09214dc2da0967912c31995cb8f5bcf4bfa832c5a2d3610f3a9857e5eee7c77100d599d9ed003b4106013155dffd6c48859b846e45e0ddbc5fe24f4891c9b2df51407e9cddbd974
+Qx = 64376a92c1227c1c479260c7497147760c103bfa5be95ca1593f29a851daf2e5c3a5c73c1fe3e6e2506fcea710254ab5eb2daf8aaefc19cbce7b1c4afbaa2fcda1ef85750fc0a3e
+Qy = 70638482e5c7c17a82980b863cde11294c0df717bfa4b9f884cbbbbf80a64dd2cc7c7d89ed21e10561260d372da2fb726de71863f0f60e8ad0fa5e74fb5d29bae0cbe8ad6b32f6b
+k = 0621176102c6ebc2c810eabab9f60feb71083c07751c66f719370713ec2de9ee3957bba8d768b076885db1f226a9d37588abf1b141d81b70f0af711c52edd30e92e34a1d3ed214f
+R = 1a21d460ae85d0703b4b10a2f77547e45135048ffea590ce86e0a1c049f8a4aa7b395f723b7480cc84e33f4772df8f181f3919f3c0b0b4f276b0f855174103a2f7bd757584425cf
+S = 0b56bbdf6e2be1b9e754f9b48b3ba9a13403c17c5cfcc4910112704aceea9a34209df406ee40e0a10cbc26d03839f95e775e80ec5e29b156fa277a5ac68abd99c7005ea6ba2695b
+
+Msg = c548f0546cee0c0400401cd540a0aa9377f27ac64492e6baaf38e794db4df83e64ca3d83b67bbb46a6c269c04c2725287cce0dee984a0d468c9ce495a7e554a6835d72c7493bfe88dbd5a044a148c89001b8087fb03e57c2b7212d0b175d616333a9affd8a1802dd49ba9be3ab6c6d9f99a5578d26cc4707a5860c6c804d69ce
+d = 042f2682e9ac8b76f3c0880e12c292524601dce9ea6982dcf68bfdb0d3fbfb50dc9229e54149ef09b95bbf624eb04ce1427077f30d8536be9f69970ddb449ca22ab8368d2689ed4
+Qx = 116135b273ef876453b9c4c39e4be5a815874857f4a72602f0d03b4ecd9a4ad73b90600c71111e317df0782fc92e6ce2b194c204340bc11e68cc22ced38e99f90dbaf0f917e970d
+Qy = 36dfa65a6e9d0ba521ade7daa2f6b01e1d14fbe7b5abd29ae71c4eff66c390914bf46f09f4ab8a06dc0fad6fa257a85f993d6829b5e0add5086b8fe2ecb8027d08eec1bea981cc4
+k = 0bf116711b31ca347d41a6cee5aa13a74e042ffbf79d2ae9448598e6950d721b3773ae6f25d7b49ca9dbcd62feb011d5d556bb9f8a55a7acc9a3a166a4169351bc31a293db68eed
+R = 11dcb7f4103e814439df22764f776a74aa86ce9717585712b224803f0ff193d5f541d94142812c726b75e8c2c37f2a4c33db6af118af73d3ec4fda49cfc911fef1eda9a470ff200
+S = 15fa4ada3a6e95164aa8972f14ab7572a3b898feb6cde160b8f25094f67343d35e6efdfab18793f77e09e5a42f56bae747b2b66fa9fe1e4a97e5e05ca743c058b1024cc848393b8
+
+Msg = 9431c6c5237f6b4b35682a0c32f68752035c8b295a1763c5dbdfd73466cea64a00ecc11356d02d2a9211dc54548f5db1651e4471898402c887fbf45005a3bda271df0158c98319d4d6751b8ca6b07100182957d5fe0d97c4e2294406f83e9afcae4850bb089f2252490417b5afd8f07f4c795fa84c9c7cdcce26bd97273c0072
+d = 17ed9a9c75cf66528428e85b0f019e3488af8b893b12023ff1b4ca9c3691b74e594539afa0f4d7c3863d15399b862f15e27bb077392d6bbd546ddfd46728c75177338466eb2f4ff
+Qx = 760779389124c702686d8d7c25dccfa74fb333317bdb414965d2c271ca5e687c4cca57e6f6149e1714551761abd4d651e7b04451d8be8e58c0c9e361fe0c6771e3d547d6ac3e8cd
+Qy = 52d5725d14b9aef93b83d638377f5a19e3cd6e3584121fdfc2c3ba1a588491d7e9892be081c9e7585a15b37a9cd4c204054dadf06a9f4ebe98f95f6554941982faf109c2af98c65
+k = 104ba3049a642d9b49c4302e9173a9efaf215b67e060c5e9673521641c9c2a5b14bad25a448e46faf73810979a3a50104ec8c5230a909ae588213161fbc10381d7c75b35c84046e
+R = 1bf3e89fb0beb1ab854a5513278dbd8b9c6b05c94ab67145ceb1ffcd93d1a2aa374db46ef327043518a7f272b957dbbf9d6cbd6708f4c89f05865932b7e816b12a59647d972f6e5
+S = 13a8c121c9c170b244ae3a55aa2d53f4ae5af91b1f72c066207e3f52e44723bd4ae419d24821b83648cd64fa70536605912a5a9319dc446a6b2b639cb99ed2485271acafc2bc988
+
+Msg = 417cd5f60416f17081d2c70e9a510114e08be83573bf9deae75fbc3095dffc8a7f7325f61f9d6565381710eda871388cb17619e4448836076338ee309a2bba5f737319002e259b4a875cce1bb97996101c9a7abe0278dcac203a712f0809eb3c4b85a9c380550ab0bbc5067a8edfa78abf03c09b5c08f21714e1022ebfcada4a
+d = 1bcc09b3f2f1d26ab9955bff7e8c0f85c8a61293511a196b53d7963f4a4503849c96fb4daa68c9852ad9185e01a35f0bf298e34a09ec352cb6da34f89a1f23e8ea27712a8f43aa7
+Qx = 1326341764a4aea222e7413a4a6f7bdc0c35ba246e3c68728ce06bdb19f2e1b9102add88a8511130ff48c0cbe4012ab52de93329670a319f6b1e7e7dbf177667d4a98d3891ec147
+Qy = 7a4aaa73713bf8fb3907d49e5653cf82a9587518c2f8269cd1e556a3be3589dad4c238e4c80681e141be93c318f0efddee3e378cd46512d778b9033dc8706bb843a3c3546e76e4a
+k = 13412a98a2c14a9672ecd42db9c079a689b147ad91869c3d45a7046aa9dfd3f31edb43ce6b84e9edcd7e3ac6b96d89f13878cf5befb052a6f8a4e5577bdf916adb10d908d5e99b0
+R = 11c8a92044a30be397007a71d9af3e4222556a10f3a07a1521c1bcef73b4ddb94fefdebba5944d5bd91313560718a8f520bb5cd5666539756a5e9b66a1b2d18fde5ae72e61d584c
+S = 1ea510e23ccc7596db529dfbea78c99fc78ae53da32ad7c7bdb1df01039310988ea601828fdfc59a0cd237110cfee9de8711c073be44dd4d04bca4b1cbec278b1a9ef175d93f70e
+
+Msg = eced8c412a153a643ccd69596389f83b6a36880286f8aeede503452bef8305942d95734fb5733f37ffeceb1c2dae7b1396c3323de11089082745c28a1756f784423fa7ad68bbfbf0d93ff8b7ad62220500df6d6895788402c1f5c69c06dd9ef55e2401cf297184e411be87c1bba657f847208c0e750f94a3df92f253b377b4da
+d = 0ec52fc3d9c272ca80623e06b15c35f349b13548ef7ee400bbfa04196850b3b8cc7b239238c827f9b0a3160cd97969ce21d66752791f5896e0385b0527d4d77e4b9fc70f04d73b2
+Qx = 5cd2e63dcd48fc793c18776d030398dfe3f8b6978eec6d23f49240581fe1e141f667498421f4c40a9430587fa282441a78bb641894cb79d929c299f1aede218a0078c247f740252
+Qy = 0cd2843ca87d98f6336c0adb97bbb9c5293a03e5b86d5534e2849ebbd73dff837ffa488fad7d134908234d0d7fdac8c7fafb4729ecf0516c42995fc9337f60db2f36eeac69a4e42
+k = 1c40a15fca0c959852afcb4ca6cbcc99fb680950c64ba18ae5388bf783052b6ef3730b1fb1487189ad983b6a68bcfbb707466092da52ea8893d8bc4898eb133fd771e78379b9c13
+R = 14485cb1caf1527350587d6695ee3df2b21c13084df0c093ca5109d7c192e7e5df2232ede11dbe5ff2f46b13dc2dedb709a0fc1641c1f32857040147599d8f179fea6b2f2417646
+S = 1a16ebf12c11d2d0a64b7ea124623ffdfe2650fc9603ded571e76dbd7e3b27cd32fcb709e2ba04aee0e8e1b942a4e829cd0c9683aee67eec27d4244a2cefc36f84f7de209e22a62
+
+Msg = 30e83ea39a92036e22b7bed7639eab5e5be1d00c20b4a9b9afa9a0d1653369cbef363c119cc6f921c8f84663949c8b8dc9b743ac2b1861a480476e9b64c8f333f34b6fa0e1ddf09d49618ee4f3c1f46751b5595f0aea413d4ca46f3c26b974b112cbe99c813a96a4423764c069454946f213c5f066ec38108f947abeeeb02fb8
+d = 06403de7627de22d1dcf6b8da5af62f9ec59ec065cc1ca1311bb98aa439a6d5985619b17c17a70f59e17cf180ea6828ef57f5f1f8ef05680a9fc12ab7faad5af61e4e11fb45d341
+Qx = 5575c329d73f261ab6897153d7261f87e9730eb5dad49c05d782cb02e483fac4a9ddff31d2fb695a62cdc44edef6398be8f4f84aea1d63d0b3a771fe91889dfac4780063d258325
+Qy = 183e63ee783abbd00547567bb99e9b578ad8ce63d229db41c6877534487568c423d4c389154af9627708d8d8f863597bc668e88f9412b21a6696d07bba06fe7aef93b26950c69ed
+k = 0e751a4918643ba3e68bd9406a4386e876d0d66342aefb4ef75bc4dcb8cb2e2d9f8378bd02c388c776535ba85d24b206f5bef4b2f23a1c99fe2f2e8ea201009ca468e5b2e21dcda
+R = 0ad6792fdff4c621219549834cf03808645171d944088f5a6d3cf1bd826b5588544a32f231e8428a03ec02d6c1c1243fb6b79b1cc6d732be5be8f2cedf03c1e5588822eec559b7c
+S = 178b64bc5f9fcedab17822e831fa52d49ed10afef1c5912893df4bd8dc960b474ed25883ddc343341b696fdebd06e177f234ea45553cc83920a8c799ada2deccf1ddf1dd9aed863
+
+Msg = 3ed244dc16a5cb292db4b1433b0ca3226913f07377faa20c6c1402cb4d026de808ca74a6d4ecdd7c4e662105bff6edb9fae0117c50aa053aef677c0750c7a446edbb879110030758912e8fa666489d702d8fceb719963b24a256429bbcc869a1f4ab9de9db89263e3684d4daa1df2ed94bb59dde2abba63793e5f82aa2e4db83
+d = 01fb980aef64254aeb9bb613ff2fc6967503db4bc1f337882f1566cbeb57489cf32e34f310549f41cba1b951f487453c29753a184e33330e90d4b973d2e406c99a239a5c3f96233
+Qx = 36ea761ccc71ba55aeab229aaf874a7c2d1ec15d821401e2988dccf02798c4e7bea80d9fb8d30be213fc80475a17f45d60c53249b66858d29c73e73117162934dd71096d746742e
+Qy = 49bc28f4d45d29c3560915698d03271028f56c29f0ead0608cb72dd0b62490f95bbd67145a6c0adff0d6ef396b4deea6a5e2a33f242bf17e907b136c039c127d6012c88b76aab3d
+k = 0ed404ee6b59ffc445b16f11b9b1471249443f8a7309ad8a662b7cb44c94866828c906fd64784c699cd29d3d972e5db3d42157452630f14536eca23cbbdd1d37e199e5a586fc352
+R = 1056938496df511d745f2cb88acad279ec2d58bb36498fcd8139d426d596de6d145b765a5b3e8366845fceae91d14075356a32515134e577937ce2af7e732b4e89a9164d083adaa
+S = 0d5156c776f2184babd69c1f200b8bd94289d45a2f8b7cd8e8afb1455e8901d8c3ed14b7a23b0976b85a22b86f3ccff4ae91e286f696f39646188b675895684f33f0368098fa7ca
+
+Msg = 40343935d9423ad30f3fb1832bb08a5d20ddb3a55b59057cd275320db4a5835471c96cfb7d67f41ef860cf5879897b8dcf307bd1a52a6226847b768ea38ff1858f59e64cd635b51e6863773cc6c64b363ec47ca39266422406264668415c189e2f92447ac4c63ee5d74e95d1e6af05016917ad237f482ea0b02aecadd370a8bb
+d = 1d96dc09dfaf602789c1dffa5c9ba130832badcf180429660daadf4cf1be5cca92fe9713173861670eebfe3a0ba25bcc76aecac60a756f07b69687e05c7e25984a39556469f62b4
+Qx = 452b1cd70e3c88bec1fd0e4b8f8e9bd5f844ffc12f3d6769eeb1c9ea90e599619908682eb5e43b1d6eea63ba9353fb64b59d6549d19cd95f2f54156c81fba53aa0dc91244e7ab8b
+Qy = 20926ca366dc657d133f0ff9149738738ce68f3cc2f61dad590e2502e8fea714b89543f43d97b46b7075c58375efa379cde208ce769a16be9a377a111a8ac51459840a223f34695
+k = 1dfd064dbe64c25a832faea1819cd836d22583fc40b2ecbc19b1f5173c25f33ca8cb7f30bcd619ef73a4c14c46e610c8996059612728f508bf7db7ab3191ad61955e8b1ba409692
+R = 03cbb0ae5f7c0978ad8c10c4ff099767465ed6fefb7358f3eb58a79366707107cc88b305661526f2972bd16923375dd898ae72e81f290b86cf9a4dec086d7ef04d7a7bba5087f8e
+S = 09f77a86f0da4e35c395978603cbb9c4dcccf126b7cc924cf62732593bb1aff0dabb6d58321debad4410dbfa1fb8fe249bfc336db7669e4ee13485ccf8dbde01ca4cdb9acfe5e74
+
+Msg = 274567f8841183e68c4f6c6b36c5a52fb0e88492e4076b9cd768bf571facf39dad6affeb68941ee326ee461ce1f33c26e4bfb3c9e0cae8241fbcc14cc69c1af68701fd0be3def1e87b7d52b682ebbe1cc225c1bd177b0886e3698a06d0e410a1f92c9bdf7239189f6acde0d0653815a72987671b415d1e8a70e685d6e5b14c33
+d = 09d98b32c8eacd135ffb8e13223690ef02c0c1f29ea8b4da193502c8cb3f39f9eed608c02fd457f2fb685ec4595e8fc8f388d26778d225d2b18c9bc8b199d8b65c0d1a6af33854a
+Qx = 775560724ab7d98407e20af12b03634a757037f8b3854957e11900d58460ca20d93ef06436921f8d4481ff9123a9eff3973e17d441511df3cd88d0d6dfc8016d2cbfb8963378463
+Qy = 3082aa4a81d4e6f0ffc94511327202f2baed72c08026e05a288eaaeaa36a1a4961f400b4712ce68778ff38be43adc2222a986ef0fecde62f861575842429816c8fc77797af018c6
+k = 1f4acd3430931ecba5e9d986c6712467526ed94a0bfff36135da3ba7dd9870ceb38fa0b658dd391ce658774c6725360dc20e5ef41daa9cf52fa863840ca91053e7287ed29ac69f5
+R = 0502abe544fc3262663524cf88a5bc256b20829b7bed3e2779f559506adce3c4f3a89e18bfd31819f78ae3809d9d0710c6591b2fc90039328678aed9df2fae38a74b66f69295d82
+S = 0b2f055248d9633cafa4db3b3cef0b76ee02f6bda3d508e19c68870e76a02c69dd1013a03fd741e854cb34f815432bf48138203177141be7209e957f4db1a958fcd45421a213c98
+
+[K-571,SHA-256]
+
+Msg = d9c99b8da92d3c2e40dea3c4025dc37770e867c4d2746c4d726b6de24250591a586c166c88acb8ed340e161d4c81b9d14c919a1b06f1feb22c5ce5fca2693bdaf4994ac72c8983c87f331473fd094eccb3d5f3528e69d487562fb5a65c150a8217192f8aabfa7adcfd0b6916d5000248fbbddf1ca2f38e3d9ed2b388998b7cfc
+d = 04d873ac744c4f68bb044783ad69e1a733cb8b8f483f2695bbd90c4211282036ad7914a53b25c3e890c6824643cffbdc4138d7ff457e3fbb99387494eb5cf2bdf1ad243a3a1e644
+Qx = 4644456a4e5c543af7a086640fa9ff6627c2d9f17066d255c3e805db31fb1ba895682e94f6ab96d6ca449b0c3f76bfd6593d182f422689b31d9dc3bc0b70df210a96d19af9ec2ac
+Qy = 1d38f8572a06ce22c1586a8329f9421414b334352f1e8b961f7e0732ee01e838eb975bfb2f62132bbfd9acc6ef8899b4fd388c2b59e564fc3670da7a008ca016de678d6dded137c
+k = 0b050aa7266201a42dbee063ae2a21398ee1d2a190de9fbbce2468836e416b3ec18d7340c81fd2a5283713f9aba33e8cbb105eaa2abbf0b687fe2713921bcbc02a4b77df21f762f
+R = 08351115714bc8f29b84a6e3f0a23bdc219d4271a9ee18bdab54c3acc9cb3468beb1f89b0f981da5aa7d7ec7ad451bc5e91bc98440fe20f5877a4e73614820b9ab6f2bad3e2e609
+S = 0c64baaeed68178f5a1d8f095b0932fb73f9a02462df5e8378746ecf17d05971a0a287d5a8e0317db055b02d4f4b5864597d0f9a9cb1ae68577dcaf7db09c55bf3d3575197295c9
+
+Msg = d2b88a01fa17703c99e5b867c645e98feec0d6d1afaa20a97b5fce9c23f0594460142af4e36a5739b8d26d3ba35a0263caa5429b4abba157f359fce701c43372500fd2ae1bc2ed80bfcaf8cab7016ff93d4a27f565b7e67fe7dde22bf02c48be12114fbff2421517c825019c0ccc72d927bef156140d7f0e9b6ee37af78c3efa
+d = 18d2eb947297a054f8a789771dd875b12b26ef057fb91235dff3b062916f85aab3365609bd2a38a861439c8514e33f174c198139354e63766942f605107cb1b9709b782622b295a
+Qx = 3f6454f1dd032a925c6bc3e1c62892c1dfaa700d3badf83f07c1185c31ea817641865a129572f3351340fec331f5ed466db7bea3ffa9723c951b518ce6f3c9263a7bd6866c8b0b4
+Qy = 188877b68c10cd6ee543cc5638bf0f82db25b9327b2d81269dc61250eecb976d6568a9df29277836b97973e3615e0a4345e610b33909c2340a23c61dcc6e2baf2bc363a33381802
+k = 0ec6af799d92ab52c51cebda61ab642d4876f374edb17253a1de3e880048355e58367096d3bc0402e4b93fa6a6c8d55c529b9fd68a27962c19274393ebe1bd0b1197a28125275bf
+R = 095c42b3ef01c0f9ab96693526e903ef3ccf0d843776089d15e77093fa9d010872d65cee1801f821bcce747ddc5875eaa462b00424e6cdf0995b87c6cf33c37d4463848a6ad7fee
+S = 0c4f0edd4b2dff4f9fd1fea5addef6d483bb51c27bf5c7aa13f9482243e5ed5571bbe0a658543c69b731de56b6b34de27795095b3676375cb4686b45d48010fe8c941208cffded3
+
+Msg = a704a1428cc894f958774368979fe075353b56790555386e3b043dc6a2919b94a11c7f85883f46b4d47b324d349c28c667bf9a000daaca1d7191f2a0fd97a4867aa9f72422134a690625408a9ea4b723704690b69152655f9e9dd5fa3dd94814d97dd4f13e85c3f9bca769491c2461fbd17e28afac00bfa81371d5039013da8c
+d = 0594fc0b7a5cc0216d2e78eeeb6394c8225de795f4b73bec48b2f4ede185ba622b59a16dd3eedf8cf2c94f2ccd6dcd205f64c97cf1b7f1e34129e94b5129502909f43940dba0746
+Qx = 271cbd3e0d73ac19b975559450d686ed67eeaab4175435b2801e8989966d7c5ba81ee7d749e43dffa12efba820462bdb274a57d04cd7e92c180cdf555686c78aad58444d5f17129
+Qy = 7c407b46e93d4c2b12c967cd3e41320ea8535a2ff24372a5791fac9e95865e14d545dd3627dcb4aad2350db248ef49469ff4d59a879a84a19d1c0e5d7ad3db432af927c88aa5d48
+k = 1e730d50a9747c7c1ce2918fda7575bb81a74757cf9625d0f0619aab7f1eb6954dbaab749e573290406e599eddd7d3376dcb3fb98c116ed7b65729dd04ece3eab1d7b4bed52326c
+R = 00d59ebcfb30d7b27c87d56ec2fc9286b04b39e68dc49b395f374e19647bcc58f2fdce1c0dc815cb2aad55cf863a4786efd6c3a0ce56c1d92aa20a19245e74550c17fdaf7a08340
+S = 134e80d63c9b328e02ebafb75eabf0fafba886f48b25206cca9086e03658ce2047c94a5222a206c6c5a57ddb8f59c5ba1408fc56668066fef4557124c430cbd1267455e0b31a8bb
+
+Msg = f8a87c4acadee27a908718461e3b45060ae4ebb009b10a15926460bf219cb7e75dc3a993fb9a741b94e2fd71615c50f6df958568f452b2cc284f0516816bc0d2e2d45f663155660a26326f63f4aa42a6e1cc8462a2ec620a365257ec042f55e4047b62af689592a1a072553ff174dd629a4f51837780ca232cf479a68c1ebdda
+d = 0f000631106c5851e8ae0802b01e7a8a8540b427a8a3956a1d36f0600be89318032320cc420931d825cc964e823745c60aad3437ebc1c91d32004472e9677605fb708e5a71a0d83
+Qx = 34136cc7b8e2dcade5cbb9b3d0e0857c485ee791f862273749b5d3757d072bbeccdd8eb81c67fa6927c1aa54d823193c370fc596d0d903214d7967b905292f4b96549b3dbc9b47d
+Qy = 56f69b42b29ea82b9f2fc377e874b58ee785010bb7f5814907fb5531789606810b71613a36035cd257864e414fe0e6ea353f398745df87ccf25b3a25cce1c78f61f5039d66241e6
+k = 009781f5d960870a289cc20f6b1af56602e5e12d9a7353e81b89a90b0a9675686f15511157d9fb70b82e8b2e25534f8ad22e14ed518e62a88f1ae21c56d4ab7763808851762d3ec
+R = 0f3eba5ddbb8c127419fe5e8cc1aae2239bfbcd2ab43a006020b96c9e7db832fb09e0bc887aaf24848491d4de935b78141f426875f7dcf2937748afb303ec5eebd01b6a82a8c4df
+S = 17acc35bd81cf24f983072585ee1e096459b408da909fd82b5ea86b77154ecfbffa7fe97271f50b67ca3c29ce704b28186b831300db0aa0dd6147d2d160e4aff14348ba76e6f711
+
+Msg = 10b5438294a77c7e517ecfe8f8cd58d75297b14116aa93e574996ec4acb21837e6297cc0e7e7b5861e862062f192f2206a01b1caf42c6d7181d02c7d62b76c2881f8479449b02d32c6f792714d8f70f0c75e81c7d9abb996be87f5ad9a01fe42b75855558d5f00df392b62ae0d258f3f67dbeaf07208952e679a2c573aca941b
+d = 1023997206341c6147c536d034a9c38b4012035dc2c9b7ef0bb9cfe65e7d788296f055d508a1fd957b2dc7f9eb10c27790f15f30d81670945e54a508c57b70b46b4a09f4c769289
+Qx = 66bd3f503cf42a20cea4a55cab75940907f38fac7fb024c55245f02d72d80336574a72fb248b1b61e3205b31489ed789ee78d88e487db3f5a1cd48efa1487916b8707e72e4be7e6
+Qy = 10b6e4330af0270abeccf0901dad2f8f64f4993ca93a7c5281dfd71c6ec405f9a9bd78008fd22fef76fb79e20a571df16c4d97244c7356e3ad16cc489d3a9b2e3fdcd5f23b48e26
+k = 09137bd8436dd126924943e8599c87f64564297117766580e6344aa3c02056c811fb996f264ac4f8f0cb33eaed5ef8f120d43a1d2b3e5e34697765ff9db4b4683ce5c1596d74723
+R = 03b684a66e92d352847f63196181160db3de7a304b6e43679340eaa9fc828322b5b9c16a1772c981ff0febb474488daf998d4acd867e78019b61804bb675a98cef24fdad088afcb
+S = 02649a94d2bc243e997bdf27be7d6364459c38845c3bc8d1c8b549ad4689c8a4b4fd55193ac769b1da607dc96458e2f6abc602bb4048cf6b0933da6785795d04d10f22e439748a8
+
+Msg = d83a52d43216fdb16b1b40469863ca8eff4df9fa358deccb5ffd18b3e22a9d654aedc98f3dbdc4f5b4e56b4299e25d8a5a38d01b34eb93de382df1ae4d1c7f966e84b84c393d167aecc6f1192c4b42cae83748b1ee3d9147ce7de74cebd122695b455e8082f86e3e488fb0f51b3b7edcd579940d1cb9d045296e5e38f201b7ef
+d = 11ebf320ecf6a908ea5b868afb8e22246ce84e743e1076d6185ec65dd79043380708bf8da4ba802c3b93b8d15509bb7d7de9dc29f1e9fb0f0f2cb97a26698f955b1f7ef668122be
+Qx = 38b2760315b0999f9629922bcdff65cfdee4938d4aab8cc3d200aa9c1db843fcbfeb9da10afbf10280110c49f0c18f15c2aac4f39af35a79557c68eb6cf6afaab973538b98b0a6c
+Qy = 7da55796396e919f9b5967608af06bd01e8870354317e76bcb8597a379129e35bcb69bbf6b38911a03c3076f7fbbe9b179e078b442c604519e330282f6f6c21aba515d6d73c0257
+k = 1c219274e54a4c5e1e1aee3bf805a7002bbfe1c030cd4c8a1617dcea2a14b1d537a64cb07c5a1385edd76f3e4ea9a38e38b458d2c7bf8eb56a57fd33166bf59a8af2e9639106929
+R = 08677167a7ea1aec4de76d1c5effdb5a1655965850bd6498aaa4fb3fa50f213fa4d99caf4145b4ba87e34797babfe614dce6ac21d9c13dd0fcd9802b1414aa92dfa18318c7e57eb
+S = 048d6161a3739fbb3ee1c223bc82a46255d10a86a605f6c8e1934b13f1a8662f30f8e95f53848119c61f08037ee5a2440c8faa11a6b1800078ed476b2a3f4cfdb25367c8dc2989f
+
+Msg = eddf5553ed4db6e8ce72cbcb59fb1eb80671c884ebd68e24bd7abe98bb1f40806de646f4d509be50a3fabfa85c5630905ce81abfad8a55f4cd80208afffb9056bc67d9dd7f4660a5f924af2a3745eec2daec39a3fe36131fe9eea444b92d31f6a125f12125159ba095f89968a7028549466f41ad45668a861f671050d2a6f343
+d = 0746d5c824d78f42a1fd63d8fcca61f154ba3e75788b7a0b87f53e5420e23a935b02eaf67bace8dd8a8e7c1caee30154c2428e0a437cf12e235f41c416f92fb54528865fd4766d1
+Qx = 63645fd3810e2458d15b43287f329c354b07324c0707f19847c544f129e4de1799996f805fab7dd356567970e10eb21d875e8ee7bbce56c666511f9b4a4cca986683e937d6f0b3e
+Qy = 595485c9a7f2a97fa7f8453df13b75682931fae10f3441042199fedba91a58c105df57b83d2a3911a2d34a2d41e451d0d2549b0a0a65b42aca40aaa618c252baec171da7937d812
+k = 0674788e75eb9d5ceaadad9fae036f129178fde1a584d73cf284acae3b4cbcc208ae7a5d35aa473f4e1201c19ee5bbe685ff9218a8e2188f3428ab45bf09b6b600fcf81fadd8d69
+R = 060d6dc42329687012a93ffc5b846b4dce3df46ad12eb61437832f81f4fcdea7392582fd75e701e106e5b83521759da6a22a21addb63b73783592d3f29347f3d484e05c19db148e
+S = 197f3b2d4f3e10425f4cb60dd1ae84fd8c87f62a2cc822342d5f0be4f0841623227c5cb0f8bf83fef483a061e30ecac86cea0210036083a99fa1247b49e19a7f401a815cb68ab3b
+
+Msg = 3db94335f6d1a125309622c0a9d71bde1da09371f0285a93bd0aac255fa8f10a56074e0f6057f1b1aecf2d86a2319590ead96a2ad1336fe844e09339b456be32374ba2e659fbe9d0f2cdd83444d117d2ce3204ce4b4294dd05405634b84747ffb4227160c4e5c2c9da9815b0c6d20f55705f16cdbaa13d107ae666d707ccbe6c
+d = 00670e72ac2de50dd2cdd975a6cdab10ac45e37ef7a28c685d77447051496b5e161f8b1b93f6c7f32fce8ea05e94ed35fd7cb28c44bf51ea29cbaf5aaa31d6abca30a89430323dc
+Qx = 54db4acd0815aa7ebec4f7661d80465c64f1fd4147507549352bc07dfcc6041ad309bfb1434b60f73b3d61ebde91f849004d55257e98b6ebbbeeabe960f9429a55a36ff75c1124e
+Qy = 5b6f36f76b3b3c780b6a70bb8ea150e9cd6895ff6a6765a3516acbb4f5efa91434def52dd0ab81f618ff28db10fcf39264be8e7ea76e06516335ac5ae33ba5393080f114189110c
+k = 0f74a0ec1a7496043d78891e308c82b4660606642ea669e4406683d44b79dd6e6a1b810292bcd6a9f59bcc2e590518bdf2e9224755654026d85cf2a3d9768d909278448f0d63fe3
+R = 047d808febc1065646e6a5608d62d1445d922084487a64e9ced5fafff2977eb3a7e29984230946e3fc77a766820747122fdbbb9100c591ad7c9dd29d07efa2e8a43357e3c47762d
+S = 04dd6c8ce75bf2792ef227cd5a3102d30a9a31690ff5c21354f8dac9f826c86ebfaa04653f0ead103b1c8ea59f0a78f5d4e8eab597ec6c028ebcc57f4ce4103ac14579bd6e15166
+
+Msg = 69166ba40768d0a3930325405edfd85f3272f7b8e600b0b319f070274c91f9f03d0e6ec4bfc7b4445e91b87cecabfecf5e77c7301ee3c6b0affca2fa02c92216698705eb75443eecc25438db2d2fb4b24f4195d6b9c05c53e0868d3e58477100607ffdc31b18c40b4ad7202bb034e58653daec0f6b33c024d42a3fc84bd8f86b
+d = 0369a3bb96f884983c23281bcd04e24a3e5f6359f81e3c8e46f3f6b865eb6bdf98a630e90646275c587e41b546d3ca7688cc207afda15cf9b25cf83bd6ad27908647f3f9de59de7
+Qx = 0eb02f6e741b3f83a9dc50853828b8a6e0861ffc644162515a264730c662ba388ac0d705f8b36f5388894df5c1bbc3582c85de141abb7712caadd2d616da589bdffdd9258808a41
+Qy = 5dbf831f450da6f8e503c19a7788c1317ebe556a458e2bfbf3137f986c9c966a14ca90344be1b76457159c9d70f13af7fe0013cf605010a8a3b84bc0fe187c7d93e4cfb2639de57
+k = 0ce22f7f2f01355280ba2d2cda06a55771e66f598bf79c65171e08a98f1d954e4beb3ec77ab06ee60c5fd156a7098023558e3d630641579cc179739bda6d860f8ba1d5ef717ebb2
+R = 0ae86b40d10ca45c20bdb3db55a6dc12e9b75754679eccb44c40fa57351c23c062282e1da9e1703176e4b8f7f224982f2474494772a20269c43a18a7a03fd12d8ebb975b83ade0f
+S = 15ff7b34c3316d9e7ee3d7b48ebf97d98453ca32f3fc67fd08761d93cf34cfa5a2314fd0752d263c3eb7cf842aeac395d41ad3c04c1a9d3808b4fb7489e880d130c35a26b702952
+
+Msg = f64cb668b72f1e6dd026a478505c0eb33446ae9a2993bc7648aaed02e172fa9a0e05eeec61e756ba246c1dad7e85d3f01baf734b1905c5bbd1b08d833c2cf1e079eca75b866d705c407eea8618d23ebbaf269c7185984b3bd4117ecfb295ee6b47eecc8d3a78bb96552f6be314656f91caff793838226662c75cd7804b6bef79
+d = 026717b039df834855511815d5665ff9b654facab469390ae257b7f0eb4dfe66ea0dc037242ed0c13bf229b8f7ff26da9b55fe4750d3451c62804aad493c179ae45d08ece5af085
+Qx = 191a6d1ab9cdda2d593d5598a966efff829c04c421804c2297e658adc5c9a6092e146b25c730ff7ee65cb9812ac9ea0c18dc6b60deda948b4b7568e8b8e14411a6969d7764652ae
+Qy = 3744af98387421d958b26971d21928b73bbf5b0f0ef183e9f606d0348fa715f153a60b6c7991dcefead2ebb875d0c1dbd3665dc42a241c565ea0fb0e6349b4319c3de633883a516
+k = 0dcd28cdfe9028a4a6df1d41019bc58e4a1540ca94b717d258f2afe8bec560f3028e15ec1e8bfd422415961516659fa2b006256745e85e488c359e8cbc94cd2592bbb892a19c45e
+R = 07ba5911415a3d21a3d98b400f61eb63ddda689bfff0c8c3ab83668b1e4bf8a703c853d3585b8bdc29aa2fdc41d5e7534850f4656ec949f0a13fd18295b662c9829723e5a7fe3a1
+S = 1b027e38283d74c962fe0e7b58dfbf5e21ce1d9c91651bc98284008f44fddfe4cec9441994e690d72a8ff3ba2b538718aa678e7de046b653403f3b7c064ee07c9c3c6d23e1b068f
+
+Msg = 51ee0b98eb6a3e3c1afcb35a33697c048dbf61374629ac5702a57801fafbea4d6fa5a26c9d1b79d1c58257ac0106387fab2d4a1b7f8c0dadcbe7c830613531b3c209bc17f792bdba1c1fae1b7528aac53dc86c2094b40194577325c05d2258303a2d17c854e7449489c43991b6877a50692a6340a528a6b188440ac0cddd4c4b
+d = 1d642f2d393ed4abea37173e4a79534af87adf534ead4a0a1c46fb047619221e3577e6b8bcc776114d01159c736ab78af3e53feac339d7afe58be8e7a8ed290f1dad960f1b5de94
+Qx = 23d1ea50229b70b46578df6904fd528e9930985426eb2f1ce10eecbc0c1658395948380c4047d67bc4072be2a2624d62a301da41a5265f040642d1937fbbb7cbd205e1db85b8685
+Qy = 625c82ccff6047b1ef4b08f1913f7366c4f6c0312c21e5ab01b598d1a9618cf5c22cddc64a4732b477dd5c06e332b846c8015a2e5a195326bca46c29cedcc2f24d37ebdb7c2eaee
+k = 0c9066831d61a4192ad9de23efcaf578a5d5774960a2b3e3e292e0decaef62d1701b86ec6183d8e17a699d418ef9d084b982c97a55bd76c8b038ac5c639451096ca4d331f070ad8
+R = 005778acb38b1961195d38463abd9c19d9e07dcd997f19676633fa3c44caa44ad1a9bd63435f3138ad8f22a731e749a81161c5448eb462fcbcd69ec2255cc2923ac697ed319316c
+S = 1a1aa90113952608dd17dbf391ed56231ecfa7d649f3274774ed2b6034a2207c05c6d8b6cec480ae27b58495a50b1e5b74a17ce6cf2e43aa273c2b813c0e6c79976882b7e4b1c93
+
+Msg = feee50aeacaccb6b1c3d95c6524044edb78322ee836d8159c4a4c2cc6982480567c4c6cc4806a564876622266e1ebd45f2f4be851b79da025bd57d0e6acce1ec1c8c255eb89713a1e4897d4ee0f7a248b9d4bd3ad5dc0e57f60ebfb65691e164bc908956a019083e923cfd33dcf37c735af3462768a1e14a8051d7aee74d5228
+d = 08cb70be29e83f697a3e2f67d86f1c1ec9a163b5335cb4a06004b6634948bf60b8ad9df9b27d2bedc4975265ce44a7884e57082d521320ca4372d38fc77b18d3fa05ad8aa5c43d6
+Qx = 4c042bde9e90b38b48e60551d832a7c80377a81e8c5b010d0e491cf765c432b5edb0771aaa5f672edf3ba108dc71459d245ad60f3884b8cf33f8cf797f36b20e4be39c8389e66b4
+Qy = 75f2454c41c0323ee1a640755077d36a65be7c2a014db36719ec217e21a9c004bae5befb499bf6be67e82d3da70475abf9dfb751c84c409fe838cf1c6ae109d27f24d75c02cc5b3
+k = 186f16dfdd7a71f20a5e634ffc465356914bb52286d3d5ac00f3ebc02497112fcd592e1ecb2ebbc819e07ea092e465e66f3e58da7a2ddd41c8787f57c135ba4c168539b4743c3a5
+R = 1c2140d294fafe3d9effb33ce73bb7e5485c93c7aa9d33b7535c7053831a1dbe79075713794c87e52bc887ded969d2dfa6a1e2630cff96760310e04cd2a75be6fa020a12fc84d3b
+S = 110aa165707b7de1b3a8e05e4502701abb5ade0a27deb04fd93c6eb24ed2b67ade6c49d78e874d25247e948f704d3c5b925f84c5b07c9b289c4f8507e75d0f8927c6dad6dbce885
+
+Msg = b115f7370d6a93a90fd9dfdfb292956be34b61992ce1fa5627c5e928d74bcdeea66d4040c473306a0070fa8363c4303bea32f73ea3639b5c6676fa5a1d68a2cc1f91f00580d7453a23ae70af4cb1f1657aa82c5b305374effe5d67d559e46a6cee6360503d21070506f1af30bb000d2f2f85caa6465810f89968f33abae81cb3
+d = 1eef463771f9c6285f3257691dea0844687606d4dd00b6020517f190891cc1be97cfad21d147ed8881b5a6e19b22ceeae30e1132476325f2de0e9af2e14c80b8c780a9d2d6c96de
+Qx = 24de3ebe03d2d91b88794a77635aae6743e597410ae10c356a51e3af88fa7f9c4d648c7d1fdb887c8313914ed554eede282b24a2e66aeafcc0cc96907bb2f3877eeb97df491bef3
+Qy = 1ce1f9fd4d7d3870997f34f54f2ba8f08ac94ea94f74a766f2dbc02e4d5149802e3135a2d762e3b8abb01461968f1e88cfc8c7fda49c099e392e80d57f0c14de9c4fa1eea25732b
+k = 026b545702baa340fb6d1bc2bb96f7fb1a77a2428cc122ea380a258c747d4e0625bbf4e3dbc2ca2f15bcfea92f2417cd5d22f2bb5f38a9ba313b3bded506d3e570dcbcb86c2debd
+R = 091c162d040a12f08a416296a43501d92e2ecd6be302b5e1754b9ec119fb8a572626c509855c7c868a07b263f66070ac986f95e4c83150a5a492d5ea8a7f8ebf556c17ad2bcc996
+S = 00c217fee7bb202d6399f6b1ae4e5811d9361573ed4fe1b3fe5d474cf06d0236d59dd3580145dc0bc7632c721b6463c69490a67d1be1fae99e34318af6df939f9f7f36a9bb8d5e9
+
+Msg = 726782eb0d9720daa64e4a77b5d8dd67a1a193f15eb6b5162e3d89c925ba63b7c7e1c4bfc8d6f11915b0e14d16ab53ab015317bd5958b0beb6074199e05181915496575768d026c23e92e06016598de008c3718aaabcda8b68bebca0a73ecfc7327e8d3646106b7d114dabc46cfe56265c326ee56fd2ca87abb5bed8f997c735
+d = 13bd452b0880b101df1aa65724fb60d5d85b37ed5419027481661a3617e0fb37bda1151b9b5b41f908ba832011f7850b75a07b678e5b8cb35c5fc8b94a625e4398cd5ada2b04cc9
+Qx = 31d88b62d2edd5f6ed29258c143bbcb3d29413afd8f86873698a9efb8d2021186415d301599232989a0df5ea91ca222c5781314f200c708de30751feadc277d50e64842dd355ba5
+Qy = 1c76f19ceb1be48f5540265b8b018da62fc225cc0d2d1675bf7df71456cc8e35b002a220e2e80691600a2c1ae31e980d0cd22b4741c25bfbd413f10b375a4d8adf70a65c48ff006
+k = 1b9235221a6df49e39b4cde6650e994f624fcb5084daaa62aef54bc154949f4da9074636c44f50ea40da1a3f01bf67e9b62a725ac0537a4e37ba33fdea8ba8b2286bf82901a933b
+R = 01dffcb5b5eb23694da4978419110ed2bc7961c571a2e68daebe21e598c8b483b34f3178978708db6d78455cc1fb4f73c5ab7607cbb4f05d4d008c7bbeac88562fdaf7a370ba394
+S = 057018fc97d7b16d69af2b7dd4a859f09dc178a6025e1bd6839ec7c75c0383c59eee7079fe61aa6bfb3e2c780d4ac0ee074e6b13223c239aa60ea1187ca4937864f89e2c65056b9
+
+Msg = 1c2418243fcd89c6382b7c3b2a8c341f26d08174a9e9296c4a5c98c5793a0fa48dce51e30811a96b515aa22bf9af89a43de06d696be1e531c5dece1f69fa6ecb7f20be063c602a16454ddafb14385ae3f8246c3f989d0566e06e7ed1864502896ea19df8393259c4dab3b3380a4a80b4103cbef4f38cb69198b7cf74ce94883b
+d = 1288141ec2244e4bb3f62daf4ee588aed09ce22be55e3d42e9085a947c1f8cd16533635d170bd64ae0b417346fa4670c25d41387acb2a8e14407a1931d9f7c5358a14eca40974bb
+Qx = 7ccb7b12a7d6997ed2a11eead3278a3f45ea284dfda8e17f6d926ddd6881a44d02a0f7504dadbbcb0cbd6b85c113aa0d3b4efef1ca151cc38cab1aa8360a6d22e3d6fbc0ed980d3
+Qy = 31b85dc2d2096bbba6c465629ea09ae3421cacc5581770ce3479070f23b3aa938333c7c691d9cb93a4533b2ce389ae34dbebe8f333cef530abe17cd21448f701608febd42d9bdc0
+k = 1e411ab53c48cfc1ef9eda97002dc9181a78352de13fbee3bed86cb00c10e7406033fa0ea97b50764b0eb2dc6eb8ea83e47bb3150ecb9437179c124f15fac6ac19b0c8bc324f171
+R = 14420d78f2f9f1010018848b0442ff6e6203c1dc06a4d523802190f462ed3c11c7aa7678bd03ba27df01cacf4121309551877d3a2bbcfee116c59926daafce55a4e0a7d69c5c938
+S = 16de0b369c28ffa0bd6ed8802a503929cebb5c0a4bf0c0e99b14659b48aabfd08bcb64bc2e39855d7d514d7525b3c4dfd2244f37019b5f86254cdda599bb144c8fdbaad5525cfad
+
+[K-571,SHA-384]
+
+Msg = 1de4b642ec7220c64b91561caed7832044d6e811ac909f3b199cceb0d8a7db91bcdc801412044f5c34b355b95a2c6170fe497f6d5259bc20715a38cb0341c88e93029137e94d895bab464bca6568b852340a5c5d6a225475f6eefe2fc71ffa42f857d9bab768ccaf4793c80c4751a5583269ddcfccf8283c46a1b34d84463e61
+d = 01fe06b94a27d551d409b0eb9db0b163fadcf0486e2a6074bafe167f9a3b4ce8ac11f42cf72f9a1833a126b9473163d29bca2ad139dd1a5e7fedf54798bf56507326fae73a3e9a2
+Qx = 38d4dce42bf8fffc39a5b6583a1a1864de288ef8479449d599115bfa35b37954ab288ffbe81e69d58693e2c8c81639df12e4b36f62b2ab042e92a0715b518c63d0ec630051d4be1
+Qy = 59c72c0bfb0ea1ac5e2fdd4fc380d08037a3d0eeed4990ff02e6cf5a16817ea598085e28f8269da86c547e7b34e16a06724ee73776529c5b5dea4ce3321fb168827ca1cbdf8856d
+k = 0a3b18c8c9f17badd123c674869ff428d533d2ecb8c74f9784220be7a90dda591003df5259c5dfb612ac7398aa04cc9e82863eb0cbe66b6e7f45dd15dad252f74a538d5f4354c96
+R = 09c368c80f697c1718c55482b2c6c5c0edd7257a3a53f7193515629aa40a9716cc889d41c120516b54f3a106a171082364886e5d3a1e9482a103f072988f61de68f034d658bd976
+S = 0e782ef47b250f40c56e3ac4de112347174bd59fd4cc991a2b538ca90cdb222d048fec62e2773492a1d327152d1d6591740706fe2f8e1d65de888d47fdf173b2645813ac0fc3078
+
+Msg = 70279be7d7ac72a32606642ecd81b5d4d0f95fbc3c0b07d85c16adf2788601e44dedb8e55e0f9e0b4ca3ca35f5be7511b0e69224a05204af67aae11ce154af6d594d47f6e3142ad183969544aa95cae1edf42bc699137f60178c12b10a67698e37ab9f3edbfb3acdf1b3513d62fe3db33b16cbb4e1f9dfe732c107f9d0c953f6
+d = 09cdc7e4945c485a41728f83d5188f539e372ff4fe38fffcaacbcb4522428e4f93ef4972556f4398fe17bdd885768f0fb5590df495badc794d4d274e22f2f4a2535555922fa43f9
+Qx = 3c6f046aa3007ba7f883bc1e0bb43a9a0a1daecdea3e2b6c10b2481d11a834af241d60cad7cab27b677c9ac11f2e5b5226c0a3de13029229af00e5a092340af9b230e0ed992acf4
+Qy = 6326ffcd62e1a68b63ac680a743130b1440bbcd3966207dbc8a8f4336eb6a7986aa53cfa4fd7bf363b30706b4fae01568020b41caa70ee3d51db982de66b0ee39777da3fecf5b01
+k = 0c717523a308418eeb2aeb816346b74149d56b9620774cab582f01681bec73adb779bcc7462fff35685a4e1e114c8fba474c68fe2650344fc9cf610908966a9dd1779f76bce0cdd
+R = 0061067f377bff6a9be30c9c79d8abb7f54cc8f09eaacdc190beb27b1e6d297cd32b043b31feb49958745b78e42ac074b8722e1a7653bf03611d87c44fd3891ae410b23a2140b83
+S = 00edbe756a5dc78c8a29baac9e2059154294e3adac9a5adeb7b27ac6e4d4086821cbd55467266946ed8f6f03abff35b59434afe84067c1daa1e0bb62ee7c56b85e7f831eea99047
+
+Msg = 4d7e0ad520445b6a5cb46b7c77fbd367614044ae6004494c2b3a89089287e2836c73b799cd8c90139eac427ebe335804c3788f3728ffb8edd7f49a4bcc76a9e24ce3c2299cea88c04645b82033115380f81b0c1d823e470631008d350cf0c0dba1915519985b8a389ccd8c809dbd5bb5051a79e631916e0d052d9b6cca18e0ef
+d = 02bc753d007c4491cfb8ce0a6c96455acd16d37e02c982db216b8cc1afd6d10c6be4e15a3988b8b8b86b2b5b59a5c1939889024849317f27ee08a06bd8e7524d4ad83a1de208564
+Qx = 0ea922b09e902ce3847f14d3b3afc5562dddf15811cb2e7b9e06e1b919d795f8451a3dffcb92b418d30bbbd1a7ccf827ea0f1f6554387fa2fc51755799040133d7a655c7800b713
+Qy = 1f12439a0c0df9f6ef08e89eb1a62e2cedafc0460030810b2483ad9427c48dc061e4640ebbd9b4a398841c863a6e3d510e5c66934d66b317b1640bd05018a35677c6ac2c7839706
+k = 0385f9caee4731627276875dd8d725fe79626c18841562e8a13fa7531c7be9adca565c22459d519d643ea22478d7c51b4c286920b050bfa54ab7d42966e389c485b52cdb4fa1a0e
+R = 02ac84262fd121bbec43e81021c0f0610fd2fc0b26d66581ddaa78714ce58be46965283851241d792ad6bc79af39f09d2d4bda83996ab41f1fd206b8293cdb6c4eb9d96f39efa25
+S = 1d9c9bc330adeee8f58ebfe8c1ba401d4433efa04a44185b0e8e20b634691bfe058770d074289e636af3e96c118edf31d72b5766c30f6fe84ade42f284fc7f2707bf27b3a309638
+
+Msg = d49903f38b5c9b17542310425e59377f61f5b4f4740cd97371ee2116083f7758e69e7e2c1b0950ec6b76f96e3c91c721d6f2843afde8c7505a559c8a64bca2e665aa1131b75bdf86fb5b90581c7d3b61c2cff88f3fccf356ddf5ed282e27727be061b6925c51ea7f1a495f471dc8a5ca1a88bbe29e92338d3c9361460398965a
+d = 02082c6e61d0d72f040905d8c1c20d47b029f41ec68d6cbf43ce97c3b2a0a770557a33cb803c432cfbd3958fda30ec1bba77a6613c318597a85ad02b26c44bb77ca96d9cc1194ea
+Qx = 59ff339d505b307e05adb45aa314d47f2450e1b1aad840b5550a67c11940d0e78654755a8e28fb651e12e48c66cc1ce0338114bc1ffb00965b342ef3a3caf495f1d73a69c3f3d17
+Qy = 724e9474e6de57b9f8cbf6f6bb4f73f5769e6cb0e006a34c2510b379995c9e054cc4981c709ca85a3aebdf29090ca07dce5bd3c313c6153b551012d72a8f84600350e8754bc4abd
+k = 18d65ca6c2ef1fb32dddfb9ad4603e03c7cb1791a9ec7b41266cb68b6048aa111f5971f3cbef3f0dbb9ce409b59c31cc59bd6f100ee5247f8c36f26ca77cb252331fc3be7346b5b
+R = 12853f9d695b8ac4431c1ccc8498f3fc4916eb6a5e66b3795a3693f3f5a29ad13e58dcdaca5774f1f295e2d2d3c63c69abbcd9f388a3383371028fdcc8bd77f7554d6aa3f0431e8
+S = 0d1c324afdf01ea19e9453d2b7397584d773716d6a08b6e38f9a9fb104122ecfcc9de7bf1e5a6cfd52a08b7cecb002ebc21798d474f035fe7d4554bf632f237bce14aad88b47d4d
+
+Msg = 0e3f4afc3e7b25c1bf2d98098a5a87db1224d9bb45adc6e434732b8722a708ab80a1f3f6ef3c5aa70d2e1dad3e4416b12cc59171f05736c4b58bd084602c344f2f0bf3cfdcfe04c64e87597a99de23ded64b33607f7c273ec321f6462518715b11e91361e89ce5415bfc2ef520bfec378244a3bd2a4b9b6b3d68815f2f75baf6
+d = 0e298c93351323e2c5304015a4878997ae4e79d1c32f1dc64262e534d4f2c4b3e222356ffce746763373fdfb936fd330d3214a18c07f1205b20c9a941331cd676040ba1fe3dbce7
+Qx = 6ee4952a83477d89ea05ae63d5169cb0f7c7ff22f15728c6d69dfb30d1f28158e2667f9342cfd9b32f2fd537dad47c190d82f72c03043f2a9c5d97cd09d07ed4c35b96104042554
+Qy = 26d5935dcebc0ed5a07b7ffa50de3c8aac309dddb61b8c560230379696d81d72bda3c819c46387e7f026b384bb0f7b2ca90c402bb67b5e37d343cc21a8d1a0f822dbb2766030d73
+k = 12d23969d230e0e2712f96b11e196202dd3e6ac755c824f92b9c765e3fc808d4e7236c8a3c06ca2c8272c7ac953fdb936db30d892246cbdcb7f98c43177e1c30afcc162af511364
+R = 022f6dff5bc1eac1ef568588e2e512103cf56ebcb610e124a125fb004064a28291c19e83ea08171bd1b14ac729392c7c46354e795d63e3bb087fd100642465efd817b79924408a1
+S = 1785e1fd773446e3b90b8704cc2723b8da2f99d1d699e817c3c4622015d178b0cebc19b3a6dd972f75eb3828a386973c0a5e67ca192d69f1a84c825d1253f1062a990c3f1a947c7
+
+Msg = 8fe32671f6927272fd3cd8dd4e34d44d27fac8c88b41bf9a48039e914990bf06d1633b38b9200ce1c2a275b9c55498e5da2d0707322c3ea0a0fd7aff598fb801628264e13047c8008153e8595a0dc95d54e70b882ac2ac9314d2b78e7b93922da818d7075215e354708994af66958954c92c074d132dbb2488e5a531c755a8e2
+d = 104f4ad56594c5cec2a988c5596d73adaa5a81802b40110dbae698ddb1f0b271fd1479c38abcdb9b234e69cd0da8a0328d2135c287d5b130a09fa0b899058e7800eb2dfcee95c1a
+Qx = 4e8151aaf2aa6a6159622baad134be41c404982bb0101e820eac8f0a52166546c53927d9b419604e9b025757eaffac526d4fbebde5fba0841c6812dff2e9bab5054d4074a125ffa
+Qy = 4413639ad72d6eba870e1760c71966544f3f881f88880fdef1edeff47cf6c235e8dfef1eb1d8df51f9c48b985912f1f70b61fd3d4b859e052887560872fe6e95db0f435778d5c4c
+k = 0cccd1bf3424d8bb0513fda3db93e81bd34175d84aefafd26b37eda9e767618247bdc94ed2b1882bcae4c83eafc30a7a4a80806fda10a5e70b8827287eed8eac2721939a63c2175
+R = 05b1460e856548287683dfbb93efc869e80333a9ddcf292e2fa3b3c8d430563a01340685c6db1059aaa8b298c8db9e8281f36e3a9664faa17f413cb439ef24cbdc1a4d58872ff6b
+S = 0c6faac191c95738f7c6ad0eceb035e5d22ae85e4bd0e27f2e65ab293717c0491be3d1b5ace80f4cb4bac7e33258706010c2aa48d84c9e39c95e30805fa7669c42bad84386f7754
+
+Msg = a8fa01136a0a78313a5d160c32fe5d1805eeb3730c18ca0c47818e82c48eb4c9e5b2dfe3ee5facef9ec59b68f4e6f3213f77fba9f8ba06dcde546ae348d343233883894f4423331b536f62373a495852977a51cb192cfbec04b5582b4ece69f345979e234de32da7a120138a057a7119735c4cb19099bf48bb202e7ffac04def
+d = 0c4989bf33b3136bcb4ba67906eaff2bcbc6567635aa4b057acb7353ee87ba3cb4cb9838f8f679729d5c6ed98e6c4199cf58605f009c6873a1b8321f83cd3c0973b7a3cfd9dbaa5
+Qx = 3871c7781f2b4f653f0d49a224576bd1e5363d5171bd21da89f590f49fc212d8a57ac8a140d923c2949ca287bea803afd763f15f909c099a07297e8ba1b37c70e1e8f0fd1fe9d1c
+Qy = 5806bd5b4858ba0814da2167d232d55bb5c41ea0a36fb28a0a151c1b79b22cb16613ccd9dbf92174e42578ef88f4da6eb44918acf427fb7e4022da3376243e75410ba6ae012ddfe
+k = 0a9eb767077886c48bc54503a0d2d62f0192d3581bd9ec253107092c22f68a15293d7c3e7aff56282f0cd35e86a2b3c55c9eec079201d99b5f49946780ce6aa18b225c2dfd72cf8
+R = 03eec6ffb390ecb2af4f5ca17fa8a7fd6938667b319f0f61e5c7523efb77afccddddb5114ca8c461b1c28dfe7eb85ab156e24e891cc6f9511d703e8b3c8443d04fd8de80f5d65f9
+S = 10cf3156cf71dafea6a0d6abbd503d72b13e6a684076ac900f390059cf3fc325966b3548b58e14a82bf291d9689783b899db7d4baba524b0b63d31f9900a84fbabc2ccad95742f3
+
+Msg = ba2d83b21c783d6ef2f3b7b10e910a418a9b9f49ae0fd37990335b3a3d15627846c9a12a1f31a3d0e062ad1bec5650606ed4dd06c30e50c1e8761a29f4ea1a20f74635d5dac22e5b787ac10f4ee82b338a641484f91771c128c84d31cdab0a6b9616078c898665655ee9dd4ae73d33b94bf091b064928b959623aa71ff73b4db
+d = 1a96f2ad56e31397e236cafc108087479c9823589a5fbc3dc7488d0e5d1199cf245d7f21f524cc0e8b47feca14c93fb760e631434a91188b32965053942f3bd39b3714f9d6f1a11
+Qx = 0195bfb66e20ae295cd22d59b27b3880a890fc44ef5c720b568bf7f72266293841dcf0572063a96c62736d9d4a9cce31b10c03016305a409858a79070477d3e989481ec555c8146
+Qy = 491122a199176e2492e07fae4ddbf02d2a40a21bbd99b8f742b546db2018cac27fb4b1c03cff55f61b7caf13b0f3b097ffc8e1549eacab89225e0cf1e96b268eab7f9a1a69258f1
+k = 097e28225aee5bc9a970a150502dd14bee900d3b040b0da9cb52f5824e66af46a991bbf6423fe1e089cba47593af555b07b45e47b0f4141b0412ddf6e91153213c5b8645ae7bab2
+R = 1439928b55917e93d59341532cd1f9d09de1f6e0d9a04514bd4b692603f2cfb75a579301b39b8cd92fbfc8832839691c23e0ad3efd3b4c7c3e9a366c1554c6dd13c50dd087b3055
+S = 1fb432e72be6fc524a7106b21d03fa71852c18c67edcb8b265db3b144214e7e6d10caad91f81616e03ae7913fea1e8d11e90d54b17705e8d04c8c20f0f4f46f117cc423ca178ff5
+
+Msg = ea2d5f4e9797bfc2f33f0fccaf530db2bdf8abcec00f09a0338eefdba318221ec0e050cad1a85c3f76b784c6e8c18da2b062f333eeff18b7b781e67d6d0a4368b8231a892e0f4103012348e5df53ac745e4d34e2cd1ee9369f97d4801ff485fc144b2007008036bbc07cb1c302a00054b54f3713919191e1d5052978c9c2895e
+d = 0c08ed8e0e0f8b0d0714b46a2164b933f8147692f18da97e5a108c44d5a5cf221cb50536e41832b83bff4026c6df156386235cf5e3e9a67b7cf9b2fa7707c5e0ff33a91601b8e34
+Qx = 2d516bdd1914c83aec1cb242710ed79efa61cbb31dcf8d238d8f5e089158b2ee2bab407e01996a1621b1a869a98227c12296cc2a71c1ef2d0f26bd6614f2ac77008048abeedafcf
+Qy = 151474bef5965c455eb95ca2ffe1d589107dc251d22635f4a9fc7270358b64e4d2b81666b60c4a5c49902b0fa9963197b22f90a09cab97007842816f64fc49e351710db84980032
+k = 01125bde6086753b3bcf29b7d5a4fb0a8abffa6503b4f0b39960eba226062bdade57e4d73e8c1621792626203e83fd5c231a53b0ce10890881460802788d481f233466060f73359
+R = 199a1e40229786b966592ae6e275874ace23d5605d0c3371a4f9eca7ce4858927958bc1c2780e9f2f79767c1c72117c79c408f972006841cb621837ac002cc6510e0432d99a1f64
+S = 17f4e5e23e494ef149e4abce2d8a1ab10e3e6c2cc93998fc63baed6565ed350b220b282855e2824f398ae76b8679201b43450f62237f6fec643ea659e6c86abc24a63d82d9bf219
+
+Msg = b2293b0a09f41decd9d8e637b1b08c2efe612f33c9c0beebb6e05033c6103b958f8aacd125d7c810b4c287349f5f922d2c6ed554be597fb8b3ba0e5a8c385ed8ae70d5ae19685298f20e8d844fb5ad98db12ba7e5f45baed9045c3e86b3cac9bd55b614b82fd075954fc59bfc6124cbd68edae988596575f379d8921b594c75d
+d = 144090a0ee38cfa21fabcc24d35139a99656911ad4f6dbffb77dbe74e7993edfa9fd63d2c4f6bbdbc8ec21ba13c9f4a3576b5d6e3abeab5af5ac81b1f2bb6d4c42dde645d854d9c
+Qx = 208729b3c7abadfc221cfad8be642588d5d1c20989fea731cfccef25886905e4b1e61cf9548d89c24f5706f5243dc8aa7d5b2675c2c6d2755ce6a12e5b12c28a2cd9c597b7dacb3
+Qy = 3db73ee445ffc0f6c77467f3add3b1e97061117e221687f5589a030f5248bb959bc2ed98c9fb66da8679dea3949b77652dcf83ab9c50a00f6a9c22bd8d16e093b2deca4b0c7596a
+k = 0adcadb26626eb9f8db9ae98c6808840b65d6f886a3f0c45f0b993a8bc62bb5c08dcd87940dfef4f220f5e50234fba3a55e7127fcbb967ff78ce4fd6938a9bb653747116541cb85
+R = 18f7fb6ee028c3dd754d6e7b687560fa269b5a5fabb1d98529e0a27dc66bdb1ed79b7b5c64fb71e767d9497b9255f26b8150b9903caedb25f51594f5b7ec2870515f701bd68faf5
+S = 09ca9519388402d5d96dd9ef2d4ebfd0ebcfa58bf8c1970d04851b2409671c9d5e4aa833555df374469a4d277aab93b8df8d553399908c930f81c2d9769f1b30a13f61c02b16852
+
+Msg = acce54270252e7d9e983c08c993cd6b7e3caf482a9149036afe4665bd3d0662a6818047187872862d5718b8ac063477f693caf1a9baa8bdf2f36d411a796f2b46ab56f66bc94924229f8264016d6769c85d9bbb7d6bb042fefdb8fde1be026b86af2017aacfe38c97309b4689b23fff94f1de880064f1d3ad9d74dc804c41f41
+d = 1df26b672b2e3617b6b6c631d3c6be0cb49c0a690de49643e0f416215bcdaefc03fa9c708471f1d87476d58c8f147517ec8a14aa945ef001fa01984d5c3d81f7083ea500558fef4
+Qx = 767ca8fe8f3a7addf01b230b99499b33c83db95db05e1956fb1891fed60406865291d79b0daca0c307a3ec8b1bf2ac2cbab728c6ec65c013e01775ee21a29305e9403f72883a138
+Qy = 0acfb786b09e5185dbd8abf831d12967107dc57a040d7c800d904b530eed1e19a8e52e653fe8bb824cc424d7254532d0fee62e8ee7ce8e871cbf6e4ca3bc040444585b9a4e397cc
+k = 13e5e47048122c8301258c638bc0f00f8f9646cba927335535f68f4f4f51f23ac5398ecc21eb0bfe8fa6a2084e11fe67587bfa791cfbe2527797a4d98046f9df37662cb7e86a5a7
+R = 164b3500ad14063101b6c5ebabba53dc5acb4d6771d3b05a505e6a67727ca8ff73d996e1329c0f6d8f738237ee0f0be415003e2db515ef93931e09bdd853b9497826929eac9e9a8
+S = 06b65511990c061a6d2a97fe2a5053c775ce2bc5471865abb7261d0436a04b79baf41a0a852a57600cd4c6a114b3a8466f721a684aac2592640bc149980545daa271fa9b146f2fd
+
+Msg = e25274ded4840df0d71d3369007118f002b83e2d375c78f7e29ade067db15cce21842611f3f015db2efec57da77cb9d16eb1e00a8c1444d48dfda569e29fca1ebf40a22fc646a9fd44460f0e473bde487634bfbdac2c312f66a1c2982c6fe76c54ac72b6c8cc9345e47cb319a974b3cc4bb40634df74b4ad7e18adfa9a71ddd5
+d = 189918b832e9fa30161fdd927bfc267f6405335df3d66d225e17173af52a671138883bcb94c4403ca3e001fcf09ef4c6488934d6775af2b1da30a8f331579af2d0fbb530298d8f9
+Qx = 53e6b43c0551f32b7b34467d188985600c5c0ed12448f2e763609f40039f92002bc8e70d8dd3e337c3507fc996a1557d5f2fb3132507e49ce653482cdc86f6ca5903b77fa1619d9
+Qy = 4a9ac78a2c23be0841b96cdb1d55862e4854b530f1fa3f469ba9f7185e3f91c28d03c27d9666345bdbc7a44764595b303f49cc43bc2d0e944862913d280273cfd00e15b6b55f85b
+k = 0b47a185140b583c330c64a10d50748e019134bacf153cb4a23753f140a4d607d5771a8f0f535f9c35baae5ab6c37a55f38acd12f15be18d5bd9662383b30e4d0ce487e8cb553e9
+R = 1a2ae62cc9560590177aa544945377ff6ab1b34e7e32a25140f99996c130e170015636647756a5e8522c936eb1389c206ac74c012941269165f3772373047521f69510c7f3e6acf
+S = 1d86f4a6ab2bba7f6305c2df754652bad40d7c273ba2aadfbbe65c07ede4ac0e65fc0a37a0139a6ecab296f58c6c2532701bb008bd9e1ecac2771d9384aca094537fcab47f3ef06
+
+Msg = d8a4aed87c316012482819b03a1d91691f2ad11a2f46082497ea8f64880d686891f7da550b2ac17199c657d4eb9d04d5cb8eaa180f743b87d23b1c86103f9e9bb60f4e19f0ff9d160f180aed7735130c03adb62502e69be5c624ed7bda2301f30580ae0921b02e103a638f5623c02c186e3bfe6ff134c762a2bcac1f879a9353
+d = 0bdcc175eca3a399b944eb0334ff33c4fd130999c8ac0e7b52ac5b774fbad53ccc3a31024f5262b2eecfeb2104b14bb244307effe3dbe8ed25686dbf46a42c4b6f8e34010ad826a
+Qx = 7ab1a9279a8408828c2bd21ae6c643ad82633d636d36fd91498cfee49c8a635313f56993d02cc46da3f5b78fd243516cd23c14a4c8d79cf27dfcb05f52f0cee59cad5646a9389b8
+Qy = 799beb1ada93a48819ab70b74c36d2dcc3c5cca1f7a57ec58e643924c3ceb7a90c9cd9bf7ec762a2c428d16ef431a45cd5d069cd828601f903cb0a28182af2392b5ad12ac3a24c6
+k = 04ad8d2759df82dd70ebe9f3402d3d533a1b4635dfd0024deeee52b32373550f550b9fd4126aaa6c3a9b1f352c40c86e13f78e259abb17f85f0041e0cca9e2ae59f4ee3ba2fbc83
+R = 1cf9ce41dd5dbc3bee9f46f82e4bef10cefe79a87e8e00d002097045b9acd46364560e0fd27b0be6655e73b5cff272c8764b4c80ce0e1c91a94b8d05209a28b553f589ee2fa1b11
+S = 149fe587b144c37df2c48c2b7749c509421cfebab734003e51383cfb773c3ef5a24fbac0255cb807f5b95607121c5848d3f9656227b61d5a14042351de084d9b88745be242b6158
+
+Msg = acbaa5ffc4eee0850075c0e502a70cc7a897a919f5e7bca4e798385601a26f411fdae5466ba9f6b6d8d7f819a749b799fbf4a3bda9105063e74914e8583ed8b31ea4d22164bee6f14bf53afca269b901c80cb3265be32ffd4ca4bc4ddb83e11eff82ead6d75dc4aec8e5c67f35d58a8a156cd1c0351abdccc0c5396c8fbe6920
+d = 007ab5a55a1d8ecb7f5dca2afdf9ef465569a4b0374716f604ad42a6e0271e934b09655e8e2529784b69b2894bb399b02aeeae30e9e7ae70a2a8e56b9e775bd978a04c728e3951e
+Qx = 2df88e368c8162c1dcea5ceee3a4c52cfc8d6121eb81c31236ba26dfd1874c61586d2daacd96cb5ebc7053be57641bf53bf2651cfacf370cf470db86e1470bf285c7166c197e094
+Qy = 30067763f9fa6a9082ea16dcbf53c2b6f11c9ba1817198e5a4e189dd98141ab682ba4de0b3f873ae54efc080a2a03f755efeba3c0ade8ea67228b1a5a11d730302f1eb7c6bc3737
+k = 0d3dd75ec61e0f87737812fe1ac86ba336b1512bb9f7ceac2c7d1a5b4d5dbafca57a5209028cef9468ebdacb2a35988531baa094a1c901d9650f2c5d8e03a1621fb33ea85e2b506
+R = 184a98dec91b9afe52d4dd6b2d9f2d7e3c42e8e614332080aafd2621136ac7965beb4e8f97b222c1b2e5448b79534db4e710331a2f877f8fc2a9259129f0b24d24289495da22542
+S = 0fa384a04c4b0b0745abea373aabc09404a6037f302e234e7a2840ff39c2b86ae37c814e8bf3f3f7cf743748f2b88d02d66a3adef2028de94013c07075fb73f00555aa900337149
+
+Msg = 9a57b63a4f418404e8f5dcf3052b9bc04a4f6d2c33bde8651506d9cbc5542ffb9023292dea463111fb78913ccdcd182faabbff9164219b8900c7f9fb394f7d9678f77b18f8d58526ec64d7c1328953b983a7c416583e05a069cd76aefe26e5f5687b70abfbf9f58f052dc0863b4fc3bef805cc3bb05bf76a83235af9d6adfe66
+d = 1e7d4da72b1d82e17a066fe387f2a0a7fa4c60ab993ee09710531789186077f2f32b42ddda497d5fb57356383e1f96973df043307f0b6519430c3f0d40d62954032872fceb7dce9
+Qx = 37c59e95132f0027f661511d1bedc3018bffa62aad7f44d7370f5b169d683882fca3dd0c4260fa8f72a47a44fb0fdcf0d7776ff0632378022bdd223753c66f98dc04904344ac741
+Qy = 2d7f19468b8e4f32eeeaabd6e402a35f38dbb9f2476cf07881d8bcff170b0a6e1ff8cb1bfdcaff734a32ae9bf34a909ae7fee689e3f1ae777812a45dd46ce13fe648016353c6bb7
+k = 18ad70fb9c5673e5a39b3a1655ff76eb84519555a6cd88e86a26f9448a54f04516c2449bab3f75e74a8d15c69926ac43fe01ebbe7e1c97e73870e3cc4c0ca431cf614f35659e3eb
+R = 12abdbfb2eb08e326289fdf5615057d912749db4f17848c1ac73bf6a51fbe3e1b2732d4eb656715a6c459c6c3065b67b577f21b8eaca7d657c3b3171e8a4849f55024c69487e50d
+S = 09609da5049092e0aa8ebcf10c204de54c968b09b9bfb3eff90b80bc675d557967b35f52e459f37fd198a83a858e5d7f9f5aff8b2ef7272b236dba5857e88515ed471a60bf6da49
+
+[K-571,SHA-512]
+
+Msg = 97b79c76d9c637f51294369e0bb52c4189f2fd3bd0607f91834aa71b3555605a89ff68e84fb5bda603f502f620e14e8b0c7affefafa2f0b303009ee99653ae4550a05315e551dd12a4d8328279b8150d030b03c5650ed4f8d3ba7c3a5361f472f436b200b321e7863c771e20ddd7bdf739c51de3676f953a5501e4477aed1bd8
+d = 15b7271d4319db5743119c8103a7d4c6d57e9c62f3eb93762156d2ebd159980aa57cea948e416717d715a2e458851f1b2e9ad4172bbcc53861db29c3ee0ba8e82617a5866170847
+Qx = 03a5b9559b2058299161770166766aa65e151ac6a22a90205afd27de5eb99c5b1db369ad52f09141d3bf08884b96414c283b2669ec2a2a60c960a2f03d425dc4c229c0bb369d90f
+Qy = 024f3a9cf3dd257043dceefe6617a98e222e1cc820f3e19e63c64fdcf7ce8d9c7af7323c9aaaef4df02e498597581082fa3767c8a38f508f4ca2c1eed6f298dc8142668a0027490
+k = 0c585e425ae4a34f9b7b9205f095ea07599716f1eab1a8bbd934219ad760c4606ebbeb06cbfd3952e045a040b8ce20603aea4f965d1b6e87eac7a61672823fb2de7767e3466c730
+R = 129162cce6fb05e1fc8630ec6c3a16d108bcd251719d89631497177e6fe6d1373f114ad9dde6e04a4ee0b4747f91c78703012e5a058c132d54f2ccccfc0f9326b27d60322b497e4
+S = 140163edb5f3c4b49228e4614bfc6da9f73674eab82678ad9947b2a635f733dbce99ce3209f613e2a75e62ed84db4d7d13de6d789b7cfedc0cb6a028d8316db8831db66c91791c5
+
+Msg = 564ad0e37c9c37a60872a4780a723d08d1159ddc77bd834d74c1025cdf3cbd5338c3fc07a904fcad9b979b2a2ceb1a0139af35e5112305fd662a57af6312624b9bdd3a64849f95f59a46ca8feb2ed56f87f258518947474c1729275c4d89b7dd286ed65f286cbac76002cc63b92a73ab6bd13c4adef282f32297e441bdd8fd36
+d = 07219ea7917d174a5386df985d0dca798ac9f8e215ab2f0003aee929a2dbd91e37fedead0ed95b1e8aabcf516bdf54337b4aff7ace4c6b3179f2e919a49db50a41c9d4d58d4f636
+Qx = 2fd7f6ea770e0a6f1eeb3318b6b609c0e76ffeaa34e75f56910e8f658b70940cd7a5918328473b279f882816955b2e3702c22e0b3e03863f8d99c64f3a2c9d1c68f59a28eaf25ad
+Qy = 6c2cca84218aa019326cadae9639069dd27df4d1e95a4c8e7d7cb426e70e2d38650b382e325dc3835afa719145d16a29e4ff67de37ac8949641f0d140072f59718450a669973206
+k = 03413376b32f18385cced4549e231e514eadfe05fffa0b252732f5c88d13d9c6e0c35be3dbf72029be5e4573b8f8829f6efbf58a12b5c161bb7055d1944eecc93f82c12c5c56d9e
+R = 1c45c25f3e8eef9b92142f12e4119842122ed7672fdd82c14b3c34ade3243a4c50495c06b5984d0260376c4fa44c60b2e34b0084066d693943071bb663a44884927352668efcc62
+S = 08cdac0f4498173bf4e59de98ac9a26fc2c752cfea7a5b75141d4e1d019e25d70a717ac3ebb82884436ebe1007b0488c4ff29fa31fdf02f77fd99535c99b69c9d4e5f432516da77
+
+Msg = 072ed5b14754fddaf54e20da42432df49bef38f4a3b1841b2db457ff86c44880727aca945770adb41269df41fc17f6a687bcaffaa45a3e59070526ed53b8dc3b78cf9a80a85461eaf4b477e44d5ec4c2bab9c05aa747a5a520b35fd09e8b44539d060ba1c3470267e0dda111b15dbb587614a46e1e477127f963a16cf3a43ee5
+d = 0bc623152253da24bf8d752bd78aedf7d5f6a2f889453ccdec14e10753335ea8bea83fd181a1f3680ed50f2324fbeaadae160cc85831750e021f3e44121ea1b1efc29a7d0069479
+Qx = 003f3a6cc6964ab2f6da95c0a2a7b75afe4f77faff16fa28aa67809afd9495cde1f5dce079ec4e15ec8c1a2095a12e8adc409fe8729d865f50ff31ee75d7d807afd2c15cb142be9
+Qy = 76b15c1ce931ba06dd56dd8e4f544425fba4f37f951a188c8e7eb13a2850c93b8ce60f10b3783647a2d053e2764a957656a184a385e95c2013685d4954a2b2aa20e4a15dbc43b78
+k = 1e091f4febd694879f78e83842572280daa48db65c463e66d9a7ea57b82fda531f116800530a03cef2cf7e5be5eeb6e420213ff757c27b8e8a94513e417f4acc62adc02a76a4fdd
+R = 0264c499f7daa6ccaaf191d3502e86458ef088c9bf2ad989851c221364b24a1a3f4404fbd0eb44a41938ac6ab67002faba0bdde7f44ffe6bc10def8317c4e2807c3ca711cb6cd33
+S = 1b91c18fc55635c5e3cff70503e7a49572ba52b11bac193230c88d6eb65eff6b2d9a01f53ab0eb34f5e208538136811157f872a8255b4d249b6ffe021b0c0763cde4d7a7e72b0b3
+
+Msg = e660dbdf3e61af39b83b95d3f1970f66d616f03273f7dddb98f768452b21cd39604a31cf80590d4a5e4b0d4917519e10fd325dd4ab7a52d70d154506329baefe0d5816f514ae109483122b4fa8fa1ebd7fdf1fc4e21e8d278a50c05d81c8f489596633d949c6c8fea96fe91430c01522a5afbd5042be8aa47da04581b2bd21cc
+d = 0645947d981d258f2954558c31022a3b6ba5fa7b675312f794cb61bfff1d9ce87267e4a1dacb7c8fc58624d31c85ebe22f80d26a620fed5df5bf38515e0903f0b69a606048197d8
+Qx = 2d03e05c4b555943fd69a299249e7148e99633b286da69bbcda64e7b06ce9321d62bead7b8d095a68d9a3ab9e9cf1aeb1d8c4904a073c21806830451a79fe7a907b32df15ea4567
+Qy = 23cba4f6f1815cbe1934734a901206596c6f482011f6cb6d452329f9412d2ef4566429e7d35f2d247eaa7849ee141bb16914b64920fffe6b7923cfb19759fed6e1f80d6c40a0ae5
+k = 18955bb752f0af7d7aaccd0628dcf1f52d836fb91dc78b0fecf21ff5992d9c1f891f0eb3c139803b88736ce10ba4733a523854c4ae9ac35421beff9b20e0c8daf90bece46737579
+R = 110a428aa96277c9a13d4529f58ecc57cd7209a7340b4a78694dd9ec800f36c9c306221fa110e0b3fd65b9dcb67307b7d7678997a3143c04ba96d72be83a1cd6b01ef22acd0f82c
+S = 0b7ae2da5cd36006a92a5b2e6369afc2728a93edc845ccb1500e551be361f8658819f7d3eb82ad41d7f2beea1a1cab6f103238a6025acbf03a2b08339841694022c17db8c6c6886
+
+Msg = 8c9acbdc431565feae60e08bc7da113e12372ed373f1e1fdd581f98c8a7b0c79ac4aa42c7ffbc963fb4970fe26c5b5dd314b7051fe971c1186ebcb5650f7f7011a924de893f06961b8c75da7bff331847feead4abd2e8b9d6ecbedac18f4eac207b948e6e4215e4d5cb483e5c66ce7ad788cb89604d3a3e051539094079e7bdb
+d = 14cf93ca69d94ee8fbea0c8da9d76aea092b73073d8f5385b65c6dd4d567fe86bc2cfb8e8be890c3c6cd9abf7dc3a17eaecee3d7a9455887863e496c48dc3e47821bd3d825b6bed
+Qx = 3dfd1fac02ac4bd3e3017a3d94f29575238937824f80ba0b2eec185ce8c641e9fc72194323c779dde8c4fd6e748e09d66e82c82add75106a0e1739f2b977d40ecd3cb15a1eca420
+Qy = 6a73dd31226adba7ed8d08476b5af10a806fe8de72251400a83f6c9f6edf5e0cd6bd1fa8f3595c3ab32b4c4548729c455e4eaf83230e1335cf181cfea6b6bfa6cd4ad75ac3278cf
+k = 176972d9402d5d6c9753532e5ea907f256a872c100f87bd390c4d610bc00c408a97bd55dff2de1ef2fa8b9716e33a5a39bb6ed2ab541848685040656ad0468b360f42c3742c1fd0
+R = 00be28427524a3b0979cd82fea407463647a77ac45c489744a9998b545a13516abb9213ab0d89a2f5f872d927ad48dfa502de95524f94f34b174933f3faa7b554a1c2c3a688a0ed
+S = 1d49594454516c1876f23f2ba0b1fa4dd8bee028bed5524b7635a2df5b8459f4832b3db5f6074cf07c169cbfd9099a85ec2f5c42043c5b851c81a71c87affba34b11eda67e0ab69
+
+Msg = 53ef87d6ac7b9698f40b3ea9f3442e7b64207b140b7f66f73fb7d5f8f98452d30a4e493b6c0e3268371e88e612b818d4d847f032ed4983817d020411a52d81fd2a17b58ebdec199d817c2a8ba77042bbd747a6fd4bcc7e844ea829fd8461b389aa0b5957d92962b6d4e86385a8fbca90b8fac40944607117e9a4ef6dccb8fc1e
+d = 033feeaaaa28f16bfaf5ea9c7319cf4561ba4fc55327a8477b6cd58ef6ccad3962ee1f3edb243f3a04e7e49c8e23509fa2d63252adb186b8bc7e9255cd61fa9bc45242d42da3a68
+Qx = 6fc62c39bdd41ef7083ae10dad59e38dad217c55864a55a6a80bffe2f5e7da977d79db9ed8c9ac22d6f096129a0c680ac93fd77da4ad96e292a19b48454f91c93a3132559fecf07
+Qy = 66f1f737ad3af3df674637aa5efbb844bbc441966bae73973481628e5c2c67cb74553a7c8f2c5fc478edd8265bd6c99d6ce122a245e46fbfc21992b950f04cbda5eb220261316c5
+k = 0a5b86b76f98310a25111cc3d1b0b70fd0c20208cd0bfd8007cb569a187c3a97edd8e716aac938900c3ad8ed3a0d091a18555ab532b50f25184454d84af2beafadf754862b8ec74
+R = 0de2eade32f537727eeb82dce610b48106b277d15d8fbdb77cd312ab9983ab21bed05f05186a5cb2b530ba72c8c68b768c26d942f9224c6e6b9e7827c48e129833cb679c70aeb29
+S = 15e4fb92190bbf8dcf7548057d1bd5e5ec54a6edf54f6b88f50e96ac87ed7a7b7c0fe1e1174ba3e822fb7e7c083948296cdcdcfbdc4bde036a07f84d210001ded91c554ace71efe
+
+Msg = dca1b7a9a313ead11c2d54739d9017ae27f9d08b3544e418aee862bb57e427636cb6aedda28e10f12aa15d2355f4f8ef112a86fec5dc46e6acef693cb8fc37c3e4885f3be3d3ab31ea4d73a0de904e95c7135a149f77b621d642f9bd8ba192d39cfc58b6f19a797c4f3b4f3a87054298e3ce5eda0ff7f44f8134c9a108285dfa
+d = 05613dfb53149bf5fdc4e08ccc1c752b0b66ab43aef2d008ed40f3df40fcbb2938d2c41e3ea2dd4428aeba9059a97efe5593119673866a19d27a2ee37dd357e22b6bc849e7e22cc
+Qx = 7ef12ccf6b64c7ca64b5da45937281ec770ede572b9a8eb685f3614bc358ce550195e74666af9bb54379c1fe1304b76430d1e51a9976bba02e5781154c9bc187a31201ad99cb48e
+Qy = 43d4ca20f06b26d75be1454e96f0568bd740165a2bc6e5b8429d557a79666bb7b9cfa597d392cc5b8ecd180c37f9fe2088d7908e59ff644ab05568d974ab42ec9e01676e1b24169
+k = 10b4b67007af35942216e9aab1d6561bf7684f334a80c7d909a6154cfde8ef06a148af104d534d7dda59b5cec7949de4086ae669edcc4d68b88347d2445edd3037525c97564ce78
+R = 15bfb47a27c6970fbb3256410d5c2f6c04eb308569a966790636899fdb3122f9e3015455c4b50a6bd8cf519afc22ea845794f51e6994214feacf48322af48590d02cc9812960917
+S = 090c61f6c64381845491dac81d5273d58c59d9cfeed214527a52c8f23b0146431692a25cbfd77abba22d4bc61ef24093c593c827ef645853bc8deef7c3b07bae919152b90c17f4d
+
+Msg = aff61d62c8f5c31bbb7d0a64a6ac589e918bbf2f13e7ad13abb9ac26405e267249a7c9922139bc28140833e10976b87e91cf28285274b2b48b63d24ac94c85c70fafa78f8ad05955c0ce6c02b841ee196dab12306e3e3d6138371217e2b474f7e67a80bbb78a47e374ffe2c9f86292e471c551da50d46e7b5c8331029f369767
+d = 11b92c8b72b86c51903387a65aa206988d443d1988253329ad3a89c902ff1ef8cf73b7f2e4aaa352443bcb833712d94c3e637ec12cbe4c2d4606878576b17fae1512fc77785b737
+Qx = 22440b63bb4557996b63faf19d9f391c5085cdc2cda3755622a6cedc676222ceb5a56ec36e220e507973c0f07e4b2e2d565a69967804ad311f0658a9854b1eddfb5270f4a86b769
+Qy = 50199c9e443555123f153249cf7256dc3e82c5d8cb611adca0cd4fbb0a9a90296bfa770c1b0c0b43e4363b0227273a9ec9f00ecf83afc605b0dd2e5e24f739dd0b4ef6bb11950a0
+k = 0e5ebd85f5fd9a9a81067fdf51b1906023e68672d160ddcedeb35787688dcdc314359ff5347907b685a718ce38a69be17de292eaef189fb9ee8c63271bd6818904cd246503dd227
+R = 051387b0d057985dce86cb962bbca7d9a047f70d96c20539ae7d6b7cb8bffff606f03b8315f15a53049c6c1c227f86d395c2217d32aec32bbd406c790a6cd2706775ed8a0ba1ebe
+S = 0c7f3b7e4a8b65a58c1280110f6c2486cd2d2df7d48b49074e98accdfca4a72fa7d43bc25c6576279f4a70f22c98135ba79158bcc3452940963b556304da8e1ae88973d827bee32
+
+Msg = 721017294f17ef351e41256b57a64a79f3636628c4bcbe676ac9a2d96076b913dc4b246c9945183ec9bd2d251441b5101eac44e2fa1bef59dec03ccd7fa5accf3b7d094d68dcf78c8de4e2f19f56bf0dcb3b66b9421ec3f8b353b9fd74feb2e9affe0bf9aa421b6f03eeba3ffd58fba56b3ebd094880e50de01ee62a108a24cf
+d = 0c3c90d5ce4375a08b85575faa78ee6bbd9e5571ce5a90582042617b807339c282cdc3b003d82006264b1c08c20af4ad4549fbde53d262facb98d923d81b8eb6093374b6a1e84cb
+Qx = 1d900b4f64c07cb959049f2bfa18012f9bc2dccec5a73e9a48a9d5d65499e31ec4a1615c4c50177c032d388263eba1a90e07ea68f081e10272e88a41389bd2626961b646c76ed8e
+Qy = 5c094fedfb5b118accd64d5d46ca2ed92b3123a62042a556ffee9e3bf709092fff88231a26917d368db51d1959ad3285c7faac16ca57677651b070aa0abad96f07d35c5fb8a0ee0
+k = 14d4070307cd269cc1a3c048ec0847edbff46f64c1ba5b734d8a800e50a0a02af57cf24750d292e2c247ef1b860a9d7b5069a32f5b0546fe9e019e04af62316eb79507281fbef6d
+R = 1cda7f743c47ae93a9fa533145feab4c46252afabe3d54990663b5891b4979c645ccaa05c744420ed6fa235952f370f5aa187250d7b069aea1123f19f0f18da18fde98100ff6ff0
+S = 180b4163f2eba6e3769d8345dd8cb003ea120164442efa885eda5bacd75f8d705b7f1bae2976f67cdfe984430e36f93455ee7528fa6febfe92e42a002da165c63dba8fc589e7851
+
+Msg = e2d1f33681759adb7954bb5248b0db3c3885fea0d4c1c0c226eb1e6d2d3ef1b9ac281a0f1c2fe5175b67114b6a501e2426d1454bd5790dcbc4c232cf06b017de8a9bb39e6033f1edb5003e8de3b44cc3d6150c3c952afb442952483cc688908337b7c1a8b5c9da70937ccfa98b2b0098c530ff848010b8e8ee0a8d65283481a8
+d = 10f184c16228d9034271332178ed485d10b6aa76003efc160d63fea26fbbdf5552205ac7df0d8c852a1210cf0ba512f20b798827b36ad56b12a826fa7dc1db45aed264ca6822659
+Qx = 2637543ed8a11271bbbabb2cf72999f65df0104758c2fd6fbf3e1c5132ff1c1111fa5504ee86bed8f219d5025f8ae07055a7849314d2d439408ea2b2ddc40320c57f5d41255d0a6
+Qy = 14e360137ae33ce6930b844d42bcda4050b25f349e9e19fc4fe82f5e4f73cf9bb50212ea875a5735faaa1d5494f1685d6c8177448dbf356b408ffc2ba0726c9befb9de9f0cebe32
+k = 1146574a96394c82972eed1ab7ec98bd08f27653c565f0626fecb431ee4fc6f830554df35fa62b5f82eaad49524d3d4b0598cc7a2181ce9860e271812373d21be9536fc181c3f12
+R = 0dbf465de2c5242fb527f6e4a4188adb96a2030ed8417cd9431365173f569bfdd3e420f86947da10a703370d7f38dc43e2249a2476690829545992645c9c83d82af8adae893780d
+S = 1499782e0163f80de68e3a580ed08fdec8d6552ec69f186a74be89480be28a0df6acdf7c65a72f115f8a59fbc28bb94af64cb3bb3cab20bd25265237a010370d9a5c781c1e26f3c
+
+Msg = 414fc5d2bd56b30040e105cb891788792da595583b11b8fcc7320f40dbf64d9263532dc57344dd17573c95eedf851668b5d552e8796af205f3a0043af1a829fabc2e93d9af9091fdd9e0fcbcc9d6d9ec960aa60e4e2964c29a2f375400366480e513f63d124db7745847310e69a38c8455e4e602056a6a4a14a8694155e0a9bf
+d = 181baf9d497159f837cba58a11ca435c442e5ca792ea559bff9f6a1f562c05bf6bb5914afbd1bcaea75b35f88bdd832314b249a5298622c89462344d3f28a44ba3d059df432fc71
+Qx = 6f3915f884e250034db97327470197d13f0716d1d810e43055757460dc252f5281717b3ef3fdd51085e65a0e073e78b697a21bc33137213981fc05d9b34caf7dca7a4f99be78596
+Qy = 47a96ab5ebec6201b7c65ce7a6e70effeaeea1c095a0172e9e2c7bfc88f7b05ea575076caeab189f810258373cff2484f4fb9c8167989f61aa61ae27113b5140c95f7faa505d2d0
+k = 10e9e6047651362accc816389b26ea6befb0e34fe7363126f8c4ff9333266f46d63c4d45075480da9ebdd0f8da7224b470d914ea1d68cd821f563b574bdeffdd0b3ed73ecb9133a
+R = 00e36644cf0861f45b333092d44fdd99f56e89bf3607f75a06920dfab0ccb1831208296aa2431bdb75c5d50f15bbea2e13d185db6d7175c221858fd2b22afbeca7431c290b15d3f
+S = 023ee3b9ce817eb0a6733c85062cc3bc5f1ae62bdf3a74e3ec704baab05784dbb5ed01a6a2a73c80a3e754c013ba886108d9eed2bc210f29a4774bfe5508ecd876ab47a8527c530
+
+Msg = 3b592cc8972a4782870e079b82a50f84b4c2d8ca90bd500d1ce5678982e266c391c556d8162ac3aab967154d072dbc0ba1dab5545cf2651753dee2881eca5abd412fe624bf3f9d17d33692d21ce23ad15ccffdfd250cb1949e73c9e40a64ebebb03852e92692dad1d7baef97fe109f35b7a492b343d4b643a4a7b1723eaecb64
+d = 083fae86ab96bce99a53e50b7eecff38e4e25b21c4b0f6a4986915de245eae24f16b6a00a4db159ebc27f5a6a072da94ab6be5bf75f5eb3f75c4452bf4ea7014392eb1e02706fb4
+Qx = 78003779e0287bee54df31f64c58951df7999b48b647a6bac416f844485a4cd7a53a64170f9d2d31fdef0194a0c262b90e5bd33a1782d2ad56c210cf80abb5fb118cffd71ad79c1
+Qy = 73f89ebdf0e255205a7525cc12b7e1c58303ac3b3417183179c216ab8e47f33d0af3238e3ae64d418ee89ef3a2cb4bc67a1d2fb1923947b9dbf3f4fa39ff82327d0ce3db24d2324
+k = 13d126fc4033f537b00a81372031026f6a7a2062863a68e36c6909c548833d1a8f5fb5fe25c7d9f2c65b1dfa974630204f71e96d657095b93cb54b00cb88f32adc08eeff4036654
+R = 09be9f4bcd7b8ef111337fb665379509b8b17a2212a80d5fecc685f1f362c45f930acaef9df47c33c6028cf7aae424264575b4635a11edd6b005ad26cf2021051501fdd1b77d2dd
+S = 0dd196343ef76bec527c5929e02fbd5d02d5b0a4b5f2c8561978e600856de56d42943f1d74cb81b67010bae98de0efddfcddea5d354c60c1fa76138801f6cdc5bc932c136309b6c
+
+Msg = 0079a02cbab3dc02601fcb5c8607d555beef7cd71a66911ab6514a4ae21c5a9c0e166f8cf5fb198ec5a49a96e17cf041f35f00406b79270ebfe56dc6b8417d2529fd625686ffbc8f69685aefa2fd30a937c02f25b48be4679e6fde821de928b33b12470867def874bb8c7c8038ab6594346a2c44b39210d3610994ba60a05e06
+d = 1a663efa7bf4d8479bc535fad71e9b5e4f4281aec55967baa008ba17ac2f89cc3398d30573edef29d590fddce8cb157f655e92779f59e7a18d0327d02e7daf4c1216143b3688fed
+Qx = 6b4bb31856dc516be60a0d2d9f42508738edd4f925eca9c72a13cf136720867babb38622fe97df70a1edb35735365f34c74baef9aca539aa1dfdead3324f41a16ca69bdf86b43f7
+Qy = 6c4a91d3fac9e7647a6aec6e4369158bdcca2275866bcdc5a09b2f0f1eba10551da9613eeb1e8d3233316b62a5f4641d6aaf669b975dfc511f2437d43c9eebe53c5115fb4741b80
+k = 0a843d0cf776878fa9ceb163d7aaebd29ba3aea0808c3459036b258b99ccae4e2444bc3211b5898c0769b7d7e036c07803497e13803132b3c6301412af3be8eb4a853e939a247a7
+R = 00356e282c096fe1690fdac4c0c66eda155ec42356dfc4783cff0160e1d76b33a99442d4ee0e3f6e1c5bde4a16c8e18bd18f98a178c3fa4a560d8fb8b4b1d72663576f8baf8672f
+S = 0c5018c1383fc3847819726e1e940028892e1abd164b413293fe50f219f2059105218e4e3b952b912a3258c4ae52dcc03ac5f027fdfa448a8d58e3aa5c21e790b3b47bdfbf21175
+
+Msg = 88573bd94ef50459814806efa868ebf92b066fbc2f7a4be9d2fa06b9dc1a72f72d783a6bcbc107b18a6314511bff217037a2252e7a5cd34cf9d5b2fe9c7846931f0133b2e95876cb800dc4ed7c4a4e4cc4f1195acf99fb0ec224b1f8fa8af71f72d390eca9d6be3879032a318734a63fec336c79035a43f70271def10c4955d3
+d = 0088d1a2c0219696a94337cd56516252b74139ea0733b17fdcbf7692c3e5f6c3989e5da2aaed7468e65a5d578571928ca273ec3b6aa72cd196f560f05095cdc8346e5d31c4c2e0c
+Qx = 357801cec0888461ffde22d83afa9ca008ac88518f4b09074d29a846f5900e024a8e5947bc25ed0e5c980a58fd5e9aadfbfab31db8bec575fe886deda80134d91b3de9625465302
+Qy = 710806c7ed33f6879374c59ea144326f5948980c8013144345c5070122c0ddb7e18e9f752eadf2a9b0854dfb7d9b2f0d80ff0ba46197ce6017885939e9f59b642a8fa41639ea75e
+k = 16940f69013026bafb6f400c037272176b04e35e9f1563d382dc9982968a186e3e1525775d27150b34b8ce5e70b537f0149ce1a521d056b52e75da7e39ee8a529ed987c70b8234d
+R = 199058e36449ee1a3388d7357c9c1020b2e4c02144aea14b041bc584a752c94fb6e474959b24bd2c0c104f5ecfe223ebdede672298c29195033aaad5db1852ce4dc3185ba2409a6
+S = 11f3defd9b442378c461e2c68b239d2e4afaed691238c5ac4e0be46ebd461639a60176f9884133900f988e2d730d34df5e2bd8a14681014c0a213f8d233b3c50ae3064fc38d1a19
+
+Msg = d0e02045ece6e338cc8ab41d4a064c982ccb1748c48fc2fe0a6f10bdc876094358a6a90a45facec798a83cc95c6795cf0f0d7c66b77e22cb114c1432bfdaa1485ff35b6a58107cac3b7e58cb4f6c87c68db60b751e78f1fdfa54b8923b98caad0a4f31226956d065c083ace5f1e9e91944dcca51879d782e40358d58ca758750
+d = 16cc8a0fd59455ed8d4de561fd518df2e008f7dfaa5f7f29ac2489a411e233917b43eb3ebe2596fc824be58871949545e667dbcf240dfb5e0c615ade0179d9ea2a1b1ebb8ab9384
+Qx = 2477e678793593e2abe837961895c7ecef71af1feb882ff27cfbabfa0ba3ed771b79223e7b2d2388efd371d5c325854cd60e48484f818e1a8146fbb780cd6ce06ba63c0db67df8a
+Qy = 01b696114838bb972ec6d536abd809d3a436650191c43b2bfeefab2b400d5921a7eb78e307266acc190e05f3869017f0a66f886bd6556c58aafb1042478cc768a4f86758e9f4c32
+k = 1e1b851bb95d2913d6d35b756d49fba6f4c127dbed80fe4068260cab89c1d42f7a6843f731e83b379ccd8a4915d2e29550f3f6ccde607cd0b066dd5fa41ac2bf37bdcfc26cd4d04
+R = 10d4291346685fe070b267edad91154df83664dc115f058ea036c712929634d53662586bb50cb6473c2170db5d4ee43be0c50532015937202e193d15d5189870691ba65aead7f3e
+S = 0b2a15f1ef00204bcfb5108d8f1da96ac3297aa041074b68989ff5b6b276380de7887753fe3d416ba691ba0b2ad7fc065ace02815b2323fe17f6445b0fa66dba5d99d8e7d557cd5
+
+
+
+[B-233,SHA-224]
+
+Msg = f1b67fde01e60e4bb7904d906e9436a330c5cb5721fd4e0a3c75b83dade868736bb1d21cfb1b5c6407c373e386ee68ec2239b700e763728eb675a153b8ac44cf2a87be85fe8ed6683430cf4b7d718891cbf8d583d0a37cc952cc25fe803a7aa4fda80f05541a2f1f2601cdd0c095f7110f2a84f7d641b8531572269b21cbe77b
+d = 056673197bfeea9bd7a8b820b4ae51a50411bf118a692bb9ed3d304da53
+Qx = 03489be62e53910c20cb508de019c3e326f65051f26749944b4454f156a
+Qy = 0f775ac38baf19499675725e8190aeea16f52346b1c890d9583b38c7521
+k = 0a6c9914a55ef763913273b062475fd0188eb2d5af9c8c1dd97cb3cefc3
+R = 08601a42d7f7eb047e8ed9820ddce665c7277f8ef38c880b57109b7160d
+S = 026d6f50f0508953657df5d753c595ffb8e1c19f8d092f8ce8db54f76d0
+
+Msg = 1d496d96b533c632ed6a91f6e3653cdffaa5b8cc0008b35e49b2dd52fe261105c2ec7ee71a4ad5d51fdc3d36d688a3b7ccb3b3b0c3a65be17b8d8aa172e3005cfbf37a2d1b1a6e268c090c6f318e7e96f9ec9b9f5a8fbcc7558d89e840f7e76e44bed91c26ca48e6f5cbc253ca2fe8cb81c484cabd24070e488f9c00cd96ad4f
+d = 0468f01d483144e514ec257f2e5fdee28a927f2adb19714c1f3524dd0d3
+Qx = 16b3cad89cc42b80bb730431963526e26ae3b415b421575dfb6ed973e17
+Qy = 1acaf7de06e20262efae01fc80969cdc1a281f68e8c8bc0d2d4fbba3a3d
+k = 04d261304678301985f5bb3f6ae465f11c9fe0e5031b31f194969252703
+R = 0878a87b2867c03f55726ea2a6db822788f4aa4e9ef609997940ee8c8b6
+S = 03545153f0554a8f55301d4b948043de3057cace62c8032c8ef8a11dbf8
+
+Msg = 723400655027f474446843645757f7e2cd466bf97275067b4bc4c9d79bb3b19b2421835d69db916f24b77c381fa771fc1e7a19d2b4d09411ae55acccc615b16fd24705762b441ab67083a921fd4ae569ce0de69449aa96f5b977ac7dc022fdc8335656853796f54b3fbd118577f98920624eb0a00204f1ef83827245c06646cc
+d = 074052d027f05465a8083a59cdbf32600224e1f563f653b34314651517f
+Qx = 06999290db440eb5b3291bd4bb4a1af6386654fc4d275ef136c0e03dbca
+Qy = 1fed0b1f9284e488c7fa2a010766c340bc25dc132c7679c2598e423c3c6
+k = 06e38460379ac3fb13f64d4de654d4fa30bd8178da0bfc29fab2a1e2e39
+R = 01b18bafe55e5c24fa2df4c09112b44d24e78dd09557349ceb1b916d280
+S = 0ad7cfa003267a6b7a99894f75720cedc9cbf820d355a6b840709f42f62
+
+Msg = 155860cb31a142082bcc0bad828d747e916392d21f1873b3a3c1d28ca3ff9d45ddb66a712e3856b6afd07c8d2b2a7badab296a9775b03f6fec0befa2d8d6d00fe3938df244ab46e836a3e686c8b4f918da49f0bb3940bba34a9aa22c7caf02df7758b0de01d9f47af6146344b9be3842d9c055eaf0fb399cd8db95c544a62d8a
+d = 01856e7544223f55f80de72a6ef3822fa8fbd68eb397d06e2d76ddd35e0
+Qx = 1a117e52f09080625f85fbaad8ebe0d3ad410f034242bf48365e88ff735
+Qy = 008b8bb7958d191265901a3f15b2919142505efeea13df6e42da8b0dc1d
+k = 0aa106ad1461353865706bee9aa092b00fcf1b0108ecc1266ad5d8b6579
+R = 0bd6fcf49029df32fe0fa47f39cb9428d95d00a84a5afb392d7b4b365e0
+S = 0b17734befefebf03d1c79e59c12ed3c57e7d120dfd993bf276de559588
+
+Msg = cbd6e305cc9f0dc90caee6e65a74582e9357bd25c78e33a7b14e1ac7e9397ff4466f192fb432143e6df6d61a0ab808ec0a361a6d95a357a38cd3e241fe03ed883ccc364b248ee2a08702110745c2688bdcefa33c1a45b9c8b200e45cddf3e3f66b8d37eff07fbb3366ea1558ef304085613c56707095724b3e134c7a7d3f8dbf
+d = 0860aa2b589f2defc617be73e191502e5d9952bf60547fef19eeccbca26
+Qx = 06abc5619422b7d548c612e54df0385c293632d4d97c21e2e15ad98d0c5
+Qy = 06c36c072603681c1b03f6a023c8e987f39d931bc2a200eff82239ee38f
+k = 084fb252dae9a96a44212d18e15cc52d179cd5e3392ab9da57d04cd5a9d
+R = 037cd554e7815699f033ca9187ddb116777ef847b92353f613152c4216b
+S = 05f806dd062043420dd056998bdb9822b3177406a536d766c4aacdeee81
+
+Msg = 812a218ff1ee1472c189f63386e5b8ab341671c3a4dad27a8c6249d1c0f9a29338b471b6179f17a078b6504e804ac55ca3b13e68a623041bc1a092ea2adf3fa1124bbfeb161e6d7c483433f1548763b84da00352a6386e1339f674d45dab13898147ede468e0e01d2c4e0ed66b395a16cc3ded3e952ac739205f35a83376cbce
+d = 0d0dec052a00ccebd0c0c5d9a08272f75744a2582cec7ddd924a2b022b2
+Qx = 16bb8c3d319b93731f1055756e57bd56d50b6b9ffbe42735925cf6f7675
+Qy = 09dad7b87a749df130b45d9cac8011101c15abb7e64bd4fbdd94107fa31
+k = 04098547601430c723ebcb04b23e0f1ce8b1f79ff7ed3d05ba130922b01
+R = 070ea6221c0d62930b019faaa856ad2c84c3989ec54040bffc42d8dadb8
+S = 0aa20fc58beae8ccc880e7fcb48a471faa5baeb36bbe5aee71ed9f8adb9
+
+Msg = 0204b1fca831919e89e108cf140b3770f531a696b1d9a4d1fb68809eb10afccc257cc90cd36717c02b2f3d6d3d1d8a93cc5c48aa7ab9f9fddfe121ce9143376535a0c65e247c6558eac49fd1d6d1bf431ba918c471cb3d536ad485ec51f6471a340ac75f160c4c54cd3ffb9dcc123124b42df1fd2eaa005e3377c5d2d55938c6
+d = 08a017d717d6d1213f2b74c53281b07258738c0c7db649ea1ac46b9a3b6
+Qx = 1eb379e27de6c04c5320cbc18e79ed9e8993710ac70ce823f1ab5762b67
+Qy = 0f552192645d350361762aae79ffba39c33c2c5c0df208219f1b339016a
+k = 00e4822b2cffa327a8396301b21554da6fa52f418d67114bd58e850d935
+R = 0d64dbdadb4ada2d3a8892049f7fda3c733030522b44cd72ab850b77bd0
+S = 06fbae2d8e4fc04abd8a6e9cb011974ac851ec108e38f9c72603f7a04fc
+
+Msg = 2033eb48756638cb56e2cc39a3e775cfa11fce86cf71f04487dcdbc7f262bc8350a30ced54d1fcb697b28a6e96f88f782947c997872307ed963e1d68985f756435af77f57755cacbb4c6b50ed419deec9f39f0a549a13e54254fa0a5832dba2d943ad4aed8688889a2dd29dcb4ea12abd6a6c50eabcb3981c3a0c1ca5f0b9629
+d = 01b56c14442b084cfd22aeef0f8028ec57c8b571c9fc1e43de05c45e47f
+Qx = 0d450c533b13b211b8c91dad0738402a5c811460426ee2f35ae068f2c12
+Qy = 15e1c9f9d398925c619f8aa0bac746eb7907d3d510814cea185a7efe771
+k = 0dca09773730a2758b7f4d9257a8e6bd942c141e46bde5ca54a79468c4f
+R = 0379773ebb7a2860f3422d8f8f714b234e5abd8860defb19c659c9c6179
+S = 0cb9272a27661604425ab84632f586048483b9f9cb80b9697898e745117
+
+Msg = 2986ab1cfe8873009e932dc68d4727d77ccbbf378e43fe4aa7c54416346b036b89c0aad1b82977c9fbc39a00f1dc916c0561d8dd70298c02b6cbfe572e0ef2058641e841c6875e8515f3c1082765e046c90c956d984b76e0e8e6eb433ce26c1757ac5b13422479141971c20102e9621d18f51096ae3173c2753facee2862d66e
+d = 05afce37c5594586ac46a34ae291f591eacb9880a7de92701977f447fbf
+Qx = 02a069ef14f2989d2b715c5006642ba966cc84df88bbc27e713e15c47bd
+Qy = 0f001f60b8a8102a971faa2c42d3ea9cec37b49c7e6ec0cae9f7fb35713
+k = 09756db630ed9b708bf1ab8aae6a7559bc235c4e9f4002ed26e2f019aa1
+R = 06b9b2c1d214373647d9a2d24ba69741218064004614368915d5cfaacaf
+S = 090dd607329c27483fe43b7be137c3f51c23217c939baae40b53e65af2f
+
+Msg = aabf5aa90ceef91c2155f90660adbcb0eedb996f5242cee15468ae217058ebeaad8cd4ff8cdc754a8ab85ba43c59fbab6386686fad5e27ad3848fe52191c7e4b203720841501792a625aef2acb6e36493b792fa55f253effca682946ad8c77e01f44e92ec3c258d0dd98d3183f4dc4a0bd3eca183794abd6232a6f9e4add8f57
+d = 00696df05dc7a54a9908a73eb18416a155cc8df4ab26032539d86eae537
+Qx = 08f9f494ddf8d0030746a8c0b8d215dda6cc2724f411a7ea407629294c3
+Qy = 1ea2e9f85f06412d29c677aecf624a83c2fbd86482dc0d564906a91d97d
+k = 0d62b06628d3884f0a329a7b6b4f832fabea4ebc85ee03e63f2967e7810
+R = 02e39824f272d4b74810594810957963c777207217e53a672010605b9de
+S = 0e64bc44af64b6f879f0d32f814acfbb98795ef7b2f246b3f91cacb55cc
+
+Msg = 29ff209eabbde02b10b3fd559671fa53e418750c32c4a18d31cc0186d1077581bbefb8770ed079f536e866414a07431ae6633955bf42a2389b6f8a565d6e4ffb4444336e0030093876a26d4e3106e9ac697788e41f8a21c755eeb86a7c60f18e5e1069f16408a4c375a6a68d42959f2fab7ac09736c7b37c80c05897d8566ce8
+d = 05ca31e88c5b2e96e433af2023a66095161710628e7bfa428944d6676b8
+Qx = 08232d4bbe25536ea7f83c145a8d2b1cd72c383eefc2adaa1ce72c7dd9a
+Qy = 100b738c6f1551b3240293ee8e8ec29fad0cc485ffc2cfded96b68162bb
+k = 0df9e1b418ca1d41d749ee998446ba1cc54bc8bf72eac6f30929b40b5c9
+R = 0d4248e0bb60fe46abf7bdb2effe804b9d394d8a5514a5791e149d435d3
+S = 0b89a459fb99cccebda754c4b2ae264c9aef7b5b610427f42c35dbe7d3a
+
+Msg = 97765d876c80819f4004a36d09ccba78e600efc71eb7e869d3a00f658d2ace6769c7ab1ef590f41fb070aa8e08615e138df45ffbb6473d4a86ba5fdf17dd6dc9ea9ee19c0332563c99e6a3451c211d286d69102b47bfa6e07d468d9bde82e5c2063fb1ebbbed6086f542cf68ba46d4f214634afb1146dd5a6f3d50912ef5b824
+d = 0ef8fe84727a2ad8bf4e646ef28a492adfaf785a3a2ba6e6f985c649a8c
+Qx = 03435eb25ce9891a78c120098992c666940103eefd80d9bd64f1d4ba37b
+Qy = 0ddd6a4a01e443c92afbc247f634b85f1c858a2aaad35a26f57ad4c9126
+k = 09753a236759eb32e13f19b9d2ad06f7b4db4ac7b1df96813463d0cd557
+R = 08408fc46149dcce0753d7cae0f50c8c5fcc97acf7a1a02a9f68c0b80c7
+S = 0b5ffba104acc6d0cba87523382ff928859718122c4d0d2298e74985d89
+
+Msg = 21cf768d087d1e4eaa8a05e2008020e243116206d675c09be42ef2bc93617ecbb0575c873c6510ede9979215531b62126552738862fc4323d487992754e39d8f0d7e111e165ff254200e05082f59a57ef649bccaef6f980094fad3b7ef93bceb161760e200f0a2e396fbb6b6142dc84d872311bf932b84616b22231747937d58
+d = 03edb94b8c62f9af30c14a790c0f5d65e362a21cd8569b9725916d534c0
+Qx = 065133691b888cd2513964b5a905ed9334cff6367e25c09db1743045d58
+Qy = 1408e1ac721bfe2198086c1834d484b6e5692c037e09928cff87f4b5a88
+k = 01d8f800ba05d8173b0f1bb3aac0aff68c6b24cf98c28f5a69b0b5a52cf
+R = 097c07d4352e39e1878c42fe97ebd4c3ba5098706879fad9be4bb2dc2f7
+S = 0bc669db3a488e613665cd26da7927c6b6a073ba6b0951c00d22ab1ffd1
+
+Msg = 7b8e58eecdab3e40212bba6bf284f9379265b3d2baec3e4625aa08d0ced851da193c292ec793dab42732c07b4e94d8b19c83aed796a7e3a6c2b954a7a9a1ff9b2bd4ca62592c8b68f709f1ad38a5c8033ebb3f33d176945bfc68e9ef2b0cee2d45a13ce89d238a33c09ce2c0c63c4233aba5717b85c4c161dd7648a41a5e39d8
+d = 00a7519be62562318da1b67d22cf8e720353d22641e0cee11c7a352bb93
+Qx = 13b63dd8ca9044a3e518a67999a781a5b62994b6e20454003a9bdb8715c
+Qy = 1a2f9bfaf528b7f5bc8c3b02eccb71666c83e4a598b4077de999d90fe27
+k = 0992ba1a8331bc4d88be7dee06f96098bc2ea56668f345e187f32f38171
+R = 0c55b45bc7bc3092ffa82234b06ad45525b45f8904011f1bd6cd356f0cc
+S = 0e6163e70ab56d43fa27211b98b48f1cade127237bec1c6556020d39990
+
+Msg = f8f268d2b04fe47e5052c8d0d653787384b9654f0bd2138a6f52b80713feeed452b976a90eea4edcfbb62d04f3eafe172ddebd7cdc3701ecd6008e3d82e8eb217b13b5228839f61075159f3bd1e1409c08903874b6dfee2789dd72c208ae769ec8c7d52552a2b1fd73dad24de8b571f88e2184d0ee7d063a121187f97e746f2f
+d = 0264022fd7dc2328a6436b522793ad9406d7a586667a0daaf1bce927338
+Qx = 12d7e7f8519a7e357510adfca2f50182dc5fa12fb2a77409fb781ed500d
+Qy = 0ceaa9a22b7ef9febd8a9962ce21d83fd2a2a938b9d7a78d669dd233974
+k = 026fb8fa6e746106500dd29ee32bbd03b94302ec3a123356b23b3055e51
+R = 0f416418f7aa4d437e7606afedf961b968a67d9a1524d60fe3f6df4d3d0
+S = 08d3afc975a8147fa8230fef4b16e3024180a9768702038f955357ce8df
+
+[B-233,SHA-256]
+
+Msg = d288768cbd066fad4bb2500b5683fa9e4eaedfb3dbb519b083f6b802efda0a022355565c5fc6babeccb22f3adbbda450ce5d633193d1431e40c0fe631a295cf85965cd3f5937b31866bd6a5300eaef9941daf54d49832acfceed90e572ef34ccc94eacd0fd6b903fee3c572b963d21e2881656a214d2a4c125778dbe3bbeebca
+d = 0da43214e2efb7892cc1ccde6723946d2a8248a6b4d6c8872fad525ec3b
+Qx = 0db09738bf0a0dd777f67e82be50dc8c2d8e91598bc0b8d4486f67c04a5
+Qy = 08ef463e2f37ac7c3d276676cbedf17ae11e767ec577da7ccd90cde3b74
+k = 0249cbd55e307a0fd10a0c70b1c0d5e2416f4d7f144779ddc11911f4a08
+R = 04d1c99f9d486fb92b132d68c0173df891ca757572f7acc03cb41d46bbf
+S = 07de2deeb58d55d65fb37f600d916cfa49f889f02ef53dcce412703d1c9
+
+Msg = bf0ab46e0a756c11229b0ea961f8d57218be5b00ab8b0e91d7664cdf5e0341c412c0e992d26ab12115197db39df2d1a6e18ed26a91be461432a2dfc21d98cb16003e339b0b0b1f100e4e6f4824ddac5442f22a1fac26326ed8a89cc91343d7223986d485cc8c64424e84d56be536c57e4dc5faee459b1958efd79e07e90a9811
+d = 0aeafa49d776b61f6a30d66ff64bd40dd8d79891dd5293c1b5cd3b46a7c
+Qx = 1ba1b87b16122e6939da5dcadb8902177a9f9ef09194c8695008b80b588
+Qy = 08f51ee5cea1f4fc9c44c70df57326ff121268bf4e02cd9b2626fe7c1ed
+k = 09d640ede5bb60b9aa78e393ed453b1643f6dade4aa20e994db53e81fac
+R = 0277bbfb7479077d5fb6813670fbc7f46055718199550130b122a7cb8b3
+S = 0f8dd350bc0bd2d84cdd374c56ff2341de4102269a1e80df7e35969d4cf
+
+Msg = c7b1eeb7c19eb16e7f42b61d79e421b71de797a6cab4e0baee522fee7acdb533f7bbf5855316544e1b82b4f2a18ad0a2311e7622549332122171f32fc62a90e408207e0fb90d1b052821dede9c41b15b6e07d84d5d7b9e31e6396a8ed229fb6232b3051298dc5321aa589f4e289d27169f14c8cc93644916d9b72dbc92c43488
+d = 0e95db309f4305b621f51f93588a2678cb19aad0932f365fa0aaa3a3895
+Qx = 1177eefc44b6070e2c41537e75c91e2f08908c0d950bc90cd2f4720b335
+Qy = 0f751312dde55b1bcabf31665deb6c12d043d5ccc89800622a557a7ed37
+k = 00015798ef57a771d62d194389817c93de1b225398fcc0d2b81d94054a0
+R = 0eef7161a167f69a6c89b0f173db2c4a7033b5d801c0d89642ce65e377b
+S = 04043f8985bbe0221fd595f9355c33e1930b5e10a1452e81c31259e1e3d
+
+Msg = a738eb074e1f277dc665118ca055e6328059ab26da188c16f56384c566e43df8cff3d2a10d2d15c3c1406de8f734b20be5dd1ce937a4289f0ddfd7bddabd03586556eb8233b8feefedaa1f49bdec6d45fd562c2a83fa9fcfc2013bdd77900857199e51fa9c7cbeab925ba8f6c3c5fae46bf8e9c574b302f1e5f9c44400152a78
+d = 0d4319cc8e409b8755880827f3200d3f0f1c64d6356fe74eb1f5aa42499
+Qx = 0bf65953f2d08477f7fd0428c31125184e3bad4d5da00c91991949e0562
+Qy = 0f1669d0d116817d625128ae764b3fde956432552d24d98f08a12925afc
+k = 05e8704febc38bb8ea76f3c6433c1f0421dc5e5af959723a5a2f0e9a970
+R = 0307c0b838c65d1a47792cb367253bf7c9f627435f1c7ed74494b318446
+S = 00031a9b35e935be6620243f4878a38d4e617fb25f7a4883893366f39cd
+
+Msg = b28103d77e5457c42e026e713ea6ff03722a36512da17197140117442a976f9e2139c54a759fc26af5811b455e5a0d3a95362d9939c1e738045be9237b469ae2106ceed7e7842b44cc0a475d5af6d781e32ff1dd1f4e1833dbc7f82b27dc7e1562d0e29213fd8911105104a7a16f665b926aa137f70d868c90e72f8ee2c95b64
+d = 09e556c945052e5954915c773b2d47970c521fcc99139269c3ef46093b7
+Qx = 0db68c16ffe64bede4a849812df0b8e202f74500cb7d5349aacf7f3f026
+Qy = 084b5892ea74835e96e9dfb1bb201a4dcaf32da25dc00dca019d806f5c9
+k = 0d0c9e0b6d4526d5f6494d2c72f812fb8d26e17c7a44f6b5e3f9e684cad
+R = 0a379ac253f3aaf94cc49e91fe3f2908107a9e1a4d102e02395eb18cf08
+S = 0854c2f6ecbfe95cfd14045faf71ad47561e365c1dd5f515d8817c3198e
+
+Msg = 463d04c84521ae671bb35c0a7acb3ae509b1b0470f39b8fe7ae5f3c9fbadbeb2bcc3a87e284cbdff07407a351f7ba743aeac50c4a1fef7375b90eb4af8ea2df040776bbf3e4389e7a80bea40530842642b9895ab9ef5ac8ed6c9ce7917d7b3ebcf80b801da845943313988c1970e7748cc306f914c37414f8247d648b580000f
+d = 0becc76f8a77615c4f92ae1f91645bf5bb908e75ef22fd544aae63a3c8e
+Qx = 18cd93bfe8fc8ceef2b9be14fa947b60fb122f5099cb5bcfad0cdc601e8
+Qy = 16de11e673011e30f6fd92025a60d7938412ac63b19d23e45bbf53c6c4a
+k = 04e75a7b92c42ba0581eb1201fa5b3fb2ac82460e953c26ce6bc60e145f
+R = 067bad23ecac0883d218b1368d822b3bf9b82453c0e5f3e336777c6a507
+S = 03788a331249463533384a61c47232aee6f057634c37560ee25895b2a03
+
+Msg = 8b2379b5553ae7db6023cb010e26ae91322bc3f94dbaa369481936f90a886e5d3827d995ccf03ca59f46805fbac0337d31a8f117cc7044218a934d5bf507090e7e21178a7162c8fcb39111e6967803dbf9d752f3ae737ba024d0f4f7627e08be58efbe997a164106bfe37f67d2f19c0fcc7a6c7eebd96a72582a9c7bdf881896
+d = 020572c2a3dc3ea430cd8cde9d642081c21658e8bda165550cd9a5d37d9
+Qx = 16117486794f14d171dfc3ccffef0396cc9fe5aa45d6d39ce0f252c4168
+Qy = 1b6a12fe2adb279dbbefa4eafa273a2ddbafb2c6401067a5ef5e859fdcc
+k = 0edc8d0b64496da309b10630e9e5917c9a807ccd7cc7bab14360873eeab
+R = 0e1fdd3b7849806fe587ad93aef737ba0472409b7239981f0d325785fa2
+S = 0829449a0c39071a832664e8148e762efc36fda9e030e0d062458728273
+
+Msg = 3090bf7373731cc44c00372c1ac59280b0f36e627ccf763fa68a7be37bb0ac8cbd4f70db54fc652566c78ad268f78f015e4bb1e41516fa56ac303a3bb4a52e1fe897d8338db5a6e37cad685e704b994504bd231c7dec0002dbd907a7ebfa809833e32eb23fffdb44fe4a18e11fa19d67356cfd703cf39a75b1a290b8a7c73afb
+d = 0769cfbf2dd8248ea1e0ac9b275c9d6ddcf923fe762079b9ed62ccbaa89
+Qx = 1aadeee0e31ba9505da3e195d883643d260dac9fe5e86102c8ed7f88eef
+Qy = 0d925bd5fd700fcdec60cef9c9fdd304faa102d9d721b4f21291f8c96a4
+k = 0f2e203410107c075e25c4adc2f55dcc277883d679ea307df7d52060fa3
+R = 02fc0975c2e70328da4a0ad2b8bd344a8171c2c500c55b1c92270230c27
+S = 08871b6791f7d03796a3aa537fa820f0eac8f2463c9f918468e7588b784
+
+Msg = c37389cbe3f46eeebdda343e354ccd543e96b0c2a87e057aa6b9c4895a403de706d658bbc9066c140e50fef4b56af2db1f42efb70b8021254649983f1e11d04d6b10169d5a1c2093b6ab89227b88a30537c776bb7575749c3ed87bcb29effd8e4f17915b4d5dff6cab9678d88f33abead1e73dbdc5c3307ff3d3b2d5fd7bfa83
+d = 040ea4a37b388f0cc464f7e2bf92173107b268ff77a8acf5f517b4ec0e4
+Qx = 08acee84d29638a7285654d20f8e0653c7386140aba0bd2fc157d517643
+Qy = 1482ba5ebb82ba46654aa1eaa6a5f01e030177318921a0c99fa3f6eee9f
+k = 0a6fbf938e9cdd009c838196ffeb61f7f545f7e7e9a6cb18d1f595a87b1
+R = 096a80172a7b3b65c0a8acfa8b89cedf9cb19f6eaa5d38436c300b7c0f4
+S = 0b7bb96ddfc9d1324bea96836c557cf88d6ede9a93ada8fbfdfcfe56244
+
+Msg = 8884def8c3b9c5f856b9c2352c85ea71aae3c8d0e84ca74e70e404a21467159fc9826548d16dd1ec5a75dc2c23ca37b30312f25e1194e0f9385a0499db34c855412bbf58979ffce7fc3afeb7b8dbf9898df44023200d809f520db99eae315b5cf85674fab008a20340fae8f6974034fd3e55bf08c5522a460680218f9757e368
+d = 037fc7898df9b37b5390537352f5c0b8de22659166c19d7d4df31c3938d
+Qx = 198674b40d2a68ed94d5b2c51102393d1332404f75187130669b9de0df9
+Qy = 13ee77d854a60f1aa74041ef1fb58727c09f13039bb4b33a818dfe9af2a
+k = 0cf92eebec59605b1d45848f5d06e93ff2767dfa282929208ba801a9fec
+R = 0f7bd93dd4df06219fb974a4e85030840c7d4877f131adccbd98cbd25de
+S = 0c2c4a864459488eb5498a06b0b56ce7fc98fb29b1eb9b6238da8cc8f52
+
+Msg = f1fc154d469433f56c2bd42aa52237a4a4bfc08fb6d2f3f0da70a62f54e94e3f29c629c837e7adf0474fa8f23251b9b349a16848942c0d9cf5db1d0fd99527020dbe21cf0b94a9aa21f376bf74da72d36f87b306b0696771efa7250c6182b426a4500ac14de4a1804b38db8d4f3beefb8c9bb619ac82cb63fb37c2e1d22951f7
+d = 05d5069425e7a9925d2cfc6360a708147b2c1b55ede243591885147ef3b
+Qx = 1f35f161ce0963dca70066b3a6de2a74ea1941a27cdfabd9e433d8084c7
+Qy = 1d5d9cca5b741b2321d8511a777fcc2515c99ff8d13ff20266a163c94b9
+k = 01b9c83d36ada7e9367790ee850163ef4420104e0dd3299ef6d65191d7c
+R = 0dca4e804bf74aa496c15025acb4232c637c9b81e9e26d6f2065d6be21d
+S = 012014f77a4ddb7b266abf2c65a653988ee6f913e700f3f83f3e78c88ab
+
+Msg = 885cd348f7983a0721f96c0e866821223d3e5a95178b16d18652b4062b1b2278aed6f54ab06f7e37ae6ce1020aa3eb812d215194bcd212302da5b971fd86aee1dcb23057dbedb569bd0bbef80df538da69ae2358cb03bb77c64d3ead475c8c5ae5bfbdd75684b421a26f1a7b0c37548fa32d805acdc91230dd70a48232a12846
+d = 0ffe3e7b82ca62b96e057ee072a4718ca20a6cc9a3e51e4fe8ed7b4b9f9
+Qx = 10f774adc83c1893894855366f1db1962bc697b8e1d047a01a08b12da4a
+Qy = 078c6ff634d5dc8ffc4d8b1a53bbf94046023095a8c2b41618c4330a4de
+k = 005a4a50de4e97280d6ed1324214d91b271deb649a2dae18d21a0182022
+R = 04bc8ba9ffbca81b5f19f0d8b1306900ee642bc5cd9a9dc9867a4531b04
+S = 0353567acc062b83459017c70cff4f3b8ef0925032b51d7300261408549
+
+Msg = ca3b0e2f1c7db4e73c699f06e432bb0f63705ba66954bec4a259bf31c161bb4861476e2f2f7dde9d841d1ea6bd0990cc793cd7a10432e38735c3eeda7a0d786e8821239bdd6c4972c96c2cf68ec5b935391f963a50fe16af2719c9029943b539ff0f1f5645962a6ac46c75d2037fa0c7cd46deadcdfc66e1ddcaada3a376acbf
+d = 007a9cb5ce27c763646de414ca2a4dcdb774d69ed2bde7a817baddbc9de
+Qx = 086d4ac1e3d54f7c154c5370f5c9a2d22cbe8f794df68974706bdc9172c
+Qy = 17770a2ccac923423137731a14e97f6ca65a8cb3642eceb4e70c78ee929
+k = 0538b86e0a899281ab56d28f40bf3b7435f9a57e334a3269233766049a6
+R = 007ceaac3aa0e260c371843104f5cb91a057741b38889ee796e69f920e9
+S = 035eedd44b036b843deadb8e8df9d96b16e719ba350a634553457ae71a1
+
+Msg = 4b0a31b746763beee77cecd318b90acf50fac4172cf4bfb354e5a440f651cb89d7a515e09ab19e9850803ab9167c2aee3b395a5da10dc9aff799d73756dfb0a9961d93bc32f15a96bf13962a03d5bd42ddc8b5928def7fc48fb063f42866fc5f96cf88fe0eb125b7c01906ad6a7fdade28ccb0a421ceff50ae03a974671b2c27
+d = 0c03fa9e38dc1c697f70bc6381f2bacaf860bb5632fc837f728da959ac9
+Qx = 195f386c7efe108fd1d580f0a77031e180e45a23911ba983217207a904b
+Qy = 1a6837095a64f71ec53ab1c0d9a3a39d69a514065d83f1af26870e41741
+k = 0d4f48085b367787a614b57c06ee8018b2e95e989c2e8cf355e71db1091
+R = 0391710f815babf07b6287b7aab8b9d2ce04bee2a144f4d4a46fd17cf77
+S = 0ef29cbd771b8a6f414ecb73b7937ffe0a108593ffc6899f28d4030a9eb
+
+Msg = 3011d42792b21c0f1719faf6f744d576f72c5fdfd22b1a520d0e8d47e8c2b06823d853b13c9fa039fa30a6f2e3e27bb2100c6a35f55703806bbf0f79b09d0f629f8042ec63fa04062f15f2edb92b19237980005566f02bb12a40b4ec66e4ba6c599d928b33f72d7437c0e399a8e6a9068d1fef24917fc4f9ab5464ea6684dde9
+d = 087dba00e3fe4802e01718017510094924496bd2785d4ac1a352c530473
+Qx = 1198518db2d1255aef955b9b80471aba60cf6d8fd1feae6d8e048ab1403
+Qy = 1833332a116214e4d9fb37c8e0ab7552b87348434a67a0c41f73972dc9c
+k = 0378578acdfa572b1de4e032158b28bcf00ab7dbaf07b0e772c39603216
+R = 0be2cb45d527a7685139290f1098de975b69957fff2c5c29059ce417950
+S = 06abf4afdcd2990121723b94ab8145d01cc4917cd70416620ef100c67bd
+
+[B-233,SHA-384]
+
+Msg = 05a5d3a3b79f4e51b722e513620c88092a9bb02408f5f52a32e782fd4923f4fd3094fc5536caf4b645d830260eba91b5173f3833dd65600fb9e246aec968b1f6ebdfddb4059fb2de7e636ed60bb7affdb74aefd158e54485d5f26be373cf944c6570daf8fd7e4b77fad57300667d6decf5c65db99ab8763bb4ecbb09fdf47e3a
+d = 05a387e7affc54a8fbb9157b5ebd400c98e2d7bd5c3e095538987d4f8d9
+Qx = 1a97224cafc063967b25cd1a43283daa5411f3eabe9386b8b14c9768c29
+Qy = 02cefaec5141bcb084cbc9aebf28fc59780897ad1424fd439eb43eb911e
+k = 0fb7ec3804654b9c3675f7b3c427f6d01f83872e96de2742e59c93151fd
+R = 0808d829d78e65eea47122c92f8c2cbf5a8d6717a057ef1659fb6f8cd3c
+S = 0ef338e09dac0b12fa6109d15924efb694a0b672afb4ef05f4e6f2f7b88
+
+Msg = 247a101c8196eb93a440280650ad463795690bc620e46e8118db6900a71eb493d03fbcf2f73a79bb47aa8e2d8c87ef70e4cfae36fae5c45fe247d8cd0f7d0718dad106526945014b4f3bec324897d8e1fa2f457b8a68e61873b7fa0350fde3b87b7b001c13953c2050a24f71fb77eb455053e49200ebcbba7299485c0f1a40db
+d = 0adae709a930d6f5a5c0e3d8ef4aab004d741d23f0ffb8287f7059890c0
+Qx = 1541eaf3dca942957c48d693d2eaf2a456646d2fb3eb8df1779b917a9b0
+Qy = 09737958276dc31852e57063119f1d2d061616b6a2fd35b4a1a3f046954
+k = 0390d5ed395f8ee3478c2765525c235587dbf5bb2316df3a1e8c664185b
+R = 0ebcc4f84bf2deb9b3d669158998fc96d7516580675e24348ca58d70d2c
+S = 0b99462b85e6ce6b46e5aca221250ac9de7ccf3e63b38919b61700be866
+
+Msg = a16678c71976a3ce3362ca379b3272b92e8ca7085b43752473db34e4d6b61eeed3875f49f3328366fc9d0644824e0104817de458e4c1036636b18b83dbaf063f2f99818959224906571c7b28873d9c702360888df151e9ad1a7003e6130033203acf8a69889be6ebd90816f2abf0764f10be68653b1e56766ecc3150bef8b042
+d = 035d391411e6d679751092c4ea5a079c591e77ebdcb57c1d9006ae70d90
+Qx = 01298e6f1612f90dbd2eedadfa8ecce22dff1da2d1cf057c41bd37d4b06
+Qy = 073136a1caf7dae2aaaac571a900135a51ef031643e9d5f01934333b864
+k = 09e343003670f61db85aedc0249db21953d232bc45488c3d6ceaa6072bb
+R = 04ac435e88f8e487b9b217e7d68fbba9bdea0b9685769878818f25e661c
+S = 074d8f4dd58c922d7e79f30950bd54c10c1cc52ae3b8d00b675c8e501a4
+
+Msg = bc2f080a7f0b69a6b142b8f3fb481a43bd71d07418df4f3b802568073c1a8d35729ad197f34a4e941a6dd511c63f201d1f6c34a1b66545bd5f43508c10bda1d6ef60ee5bdd25dde975e50c61f76cd36d50ee3bd8dfa2dff59524db9ef12f1e28d109b552cb42f021963f559c843476b5c889fc567b7840297c5a480e18c221dc
+d = 084e79093f1947d6ab9cf399782436e36ef87c59a4c090930c9a74ddb10
+Qx = 08e756774def210e2d6f76d6e4b0b43d86adca0880f017abfc911bafb5a
+Qy = 147e6a20c1aad897829339630c5edd327ef9a7e40795630504318cb71d6
+k = 0ce780ea99a344d67de7921feba6ae062817101068266d5d1a140d2b49e
+R = 0fb2474b854b8e5d6920ed90e69b5b386a1b26a947b1cf28a13f7c5d3ac
+S = 072722017a67ea6754873f833fc51318d41d6ef598d3ec2d3e0eb5bf41d
+
+Msg = ea71cede8b63ddc5648eb244184bae265cd65d50f77a9e25ff93f02b132487c08732544cb88936d4fff7c0fedb39685822dd1c9be1158f647c605c9bb5f6a1ae34722fa08882c14b36b6c93cab33c9a269c7c10f755b6453ed045ea3e56f29e95a9404ba189a0b48848120392b4dcac43148b706c3d9e4c03db410cbe5dca3da
+d = 079b6be015b8006f86fd81c2792bec6b42c08bee2d295cf9dc214c326ab
+Qx = 0e24338d5e33ad12d41eb623ad0905f64d5b75835fec4e693eebf9bba10
+Qy = 101b4297b5b62fcca7c61637a2a57365e911d3bc7eb0fc7adb0a9dc7bad
+k = 0f06b001e5f874d16632e3c8d49f13d70f48ed4eecaff9d3b741f9d02e6
+R = 0de16d8fd7bb1783a2cc4b9ac1563eff3f87e4e6d75e6a32a4aed1ecb02
+S = 040bdb1197ee8ee51e4ecccb8d42dd985913809c131aa9224049425a052
+
+Msg = 319b41d16e18059a1324c37161c937e882192cd949c420ce9c59208a0ac208ebb06f894a7fd78df2a3c5f23f25dee6595d3dacb25a699f115dd482ccd36fc54ba29dda279335424c86b07a1b1fa76a5411bcecaf4d37065b229cdce0bac75b666c6626ec37a716e9841be93c907f87453ad91d36846561f284421a89013b88c3
+d = 0ca9d751a060fde64336cdc88122819f4b3cd1b4e7df42d495197787894
+Qx = 09549785f4f9c71f20133f5a1d409b244df55445beec404cf8cd4d2cadb
+Qy = 1b246647d7570f052840d4cc01182d1dc3bf357b25e5966434e1c3c2a30
+k = 09e99fe741cb23f7eb039f5df8414d069b5c2e3c144dcd6cbc6da56ef43
+R = 0cf00f519c18e7a0fcc84c1e338158399f16929ad89842ba97a4afb5bf2
+S = 05854ee1a6aa5a6a74bec0b4696e80aa275210183c86f45dde7002d7ae3
+
+Msg = aebeee215e7b3d4c3b82db243a47506ffbf2263f6fe9de5b69286e8649d9218367c36ba95f55e48eebcbc99de3e652b0fecc4099714ee147d71b393de14a13e5044b1251e40c6791f533b310df9e70a746f4c68c604b41752eca9ce5ce67cdc574a742c694ada8f20b34d0eb467dce5566023f8533abfa9688d782646420c77b
+d = 01dde4b2d49338a10c8ebf475b3697e8480227b39bc04253a0055839e9e
+Qx = 0504bd3a97baf9852d6d46ef3db78ee7555db752120d020cd056b1b4e50
+Qy = 18dd305f6a15e91fa46d2a6d30f2ec8fbe2baec491e26d9a2ac81155c85
+k = 03b78d2772b8ce01a00ffe2e6be2f9e2ca2c89ea3b29bec6d6cf31afe33
+R = 0c0c51fba155f98900eaa2d2935acd615e917f9dd979dc8d92f1d6e00c9
+S = 08c8354f95e24ed13d8ff3755e1122dbb4117c76b21b3bdc7f4dd856f8d
+
+Msg = 8d353a6b6f35590baef59b638914d3e934d0145b045d221d846517ceddc8ff5e3d28826d3459f8ce1260f705e80923f39abc73d5949aa7aa8ad1734be0e992bff0c9a8f4cc9bdfa430d4cf52e29d3737b0cd3231b72b16e15e1a9040b832e4a920b4a1d94c4964ac6c8abb75bbbdb10825f882ae44c534c7154c446421a04d87
+d = 02c8bea2803fd746c874fa110a716538c179c82712f38d33d0f6d037e7a
+Qx = 0a034560353561cde19db89dbcad5c9dcb74e239efc604e86ff38a0577e
+Qy = 185e0b02c48be2e90c916a7c8ef2b41a57ea8d4f21d8cd3a0878a03875b
+k = 02e39f851c57643bd799c4f3b2fcc5eec8ff7f9e9e279efa647f969cc6a
+R = 09b2ad7efc7ed60d9cd3dedbd4159b1e05f05ce5ec2d2cdf7a0e0657482
+S = 03fcbd4ace6a140c8bfebe36ff30848966bb0d3eec323cc8ddda55faf00
+
+Msg = 847f134b90f10ba3636ec24f36a94111f26d58428fda5bba4501e58c7bb55809f52320cbe9e0df55af1e40bbac9f3eaa26a55d78b60621d4356d090d98363662f406367601eaa9eb9568b1a1b319730bad7bf6a7ddf1b45eb6922faf8d065c540b671c50df758ebf8c4aca6f01878e5e0012dd038c58833e2b13ebdb9a9f3fc3
+d = 0b9119b3b4b30cbfb98ddf0a4f6953417e515fcf0e5a94e83ebc1d1d14d
+Qx = 1be65d340f7e99067bbbf961c2b357e1fd47a74393cae5f93a40c5dc280
+Qy = 0c04cd8ca3ee253b99e44ee6bc0e52d2f016b16f59c738b9f2bd8c1b9d8
+k = 02c851ba0123ff0543808931ab3857b5c15d7c10c343f232913f6e0c92e
+R = 0ba2b33550878e223cacb80e45e382dae84e76bca5a2ef8371b84d08572
+S = 08c370f82506e97cc15837f59e9779448decbd87bde0a463bc14b18edca
+
+Msg = 99d23950493bdd931915e9f9b65e4cd1329866c0071a19d4f7d6fd190689275b7b10fc07503dd1c27a4da274dbeb3aa5cb0e71e9b7b03fc2697729b7be913756e6760098951d7015df181cf14b1e0b954e6260276af553e3e59907794b863e941950718ef154669c5c262946ba120892e0239e05910c2194f712db46e37e53b7
+d = 0f4ab2a573f3771d1e4222e251faf14e06cefed544e804c299c9a8395f5
+Qx = 0b1f973d6495d277e24320622b9b99fccef8eb5c1c6952f35b82d4479ef
+Qy = 161dceea4d3c9caa4f640f51b37fcbd5b8932642a94c8e7aaed5db17fdd
+k = 034ff28a5ed6958514c603b3af5a991e2e9b4cc2c0a7aa73ab2d70bd05d
+R = 01abe4a7b27395a37089f91eab27ccf29001ced1bb3348a6f919d466477
+S = 057449e55d3f2a4004d647ad6e8fbbd516adbb4de40b1a872ad8ecf67e2
+
+Msg = 7bef2487bc2bbbcbcc1570bbd4ed437c0dbcbbf63f666a3355aec49ea6ef593da25aefe9ae0d94db50692475425dee3c88cdea975794ac69142c25732f3541457d68d9101c8be069f2b515aadadea2019dc7abefa6c12cb3f76d9f4b5e46546f77eaf636aa8f2329130922111151a4df913d18b7cf9d0308f01ad84d878adde7
+d = 0f4649cf30d4a5269296a45977de2652cb06d3ca2aff4475bb24517b927
+Qx = 100ddcc8e09ba2122a6535c6a0a2dae83abf9e17687b5f6aae7ec6a2df1
+Qy = 048f5587360ee251925b7ed02de82307ba219a707705623727f98346a26
+k = 0a38b2bd0e9a5044db19d4312ec88d19ce1a9bf0eede8c357f898b0bc67
+R = 0d0ebabc8761ea215808a2c3035b14b614f64be0c2741b3d7789a8659ff
+S = 0f9e742bdca44c11bcab196f910c0d887e90f250817ee7027f6df8207a0
+
+Msg = 87c717eef6dd3c7434b2c91de05723783bef603d170f654b49a04b067b077c405d2d757ce780101b930196ca4261efcfbd3fc1ebb762cc0eecf101072988aca508c41581936526d3f337053000dcf77b16172492c5d654c6612bbd2523a6ad5966d7091697a29ce882fe331f79a7eb59e5a3fe536263083cc59b8133bfd33c1d
+d = 0cca24ad914c24c011f41f80d27ea41caf41fcc8dc9dc6dff5248b2b474
+Qx = 0175b73db13324a678b8afe086944a7ad257cd33fe9538c59b9177d1064
+Qy = 16a98ac9e0ff59de1ad94b50f8c709ccf4342f983c7530be64c3f1548fc
+k = 029c83def3a5c386b0bc3cf2663b8f4b02f26c6e3e14fcb17e9460087f3
+R = 061df783609ceb355aba3b1753d38f42434bd75c8354029966e7a788be0
+S = 01e8a093f53a1d73d5a994b97f2b2f210125ecd3dcdf77c68ea3199856c
+
+Msg = 9bf48c2aebf473b3a4a928b3b6a4d2fb7e9193c9e60bc2067f9f03083a8cc7b892bdbf05601118bcc34dd283e7be996bf19b0bd36727eb9d65276b6517bf0c77ae0a9091e7a9e46182a2586eb22324939801034e5ba94ba30d1bde7d8fed51eb71036fab6224f8ff30a008422efcff7ea239ff23b9f462777e62b41b396c5dc5
+d = 0f5e12d536ef327e3b0ba65ac5fc3f7f4880f5968f3340eb8868c1d47da
+Qx = 0b2910f5de9475486b3975ce91c02187e8803e68586f3a1df14df67648e
+Qy = 0f28af5363ed851c42daaa810afa1fd0d2e001da7764671fd44fb6737c5
+k = 02a018753965bdfda98512c7f9da3e9235a4a77aab9804437b652182347
+R = 0b6fd02b2d84b7baf1a5eb592cde667ed6d4c2c821ca336027a72d9abdf
+S = 02253faa5935885945121a374010b2257123cd5db4c54a2aa0e08c8197b
+
+Msg = 716d25519ae8f3717da269902be4a7566d6f62b68cd0faae94bce98c8a4ac6f66215ebac5407d6f64adf9d53f79f02e50921b6f0e8c805926a839443d30d9294eaa802faa7c5471d81fd1db148cdc621a8dd0c096e06fb0b71943337d5325e1bca77062684873fe904ed9012474ceae5b138e079f941a665a995026d13d7eed9
+d = 08c30d93536b8cb132277645021775d86c2ba8f199816c7539d560ac6de
+Qx = 0d69332763cf533d48e56065e1b5255790f8c0eb23471fac9b945e62195
+Qy = 0292df8c77d9a6803f60bf0722ed57ae2aa3bc816403b000fe2940e02dd
+k = 050967928d6089da5b16c88b7927de210325c8d8f5e727fa1ba3bd95b5e
+R = 02434697cb5c2ad95721943154bc81e2ae16332fa6629788f505bbc1522
+S = 09a5a6792b1b9c2e200ace5a3d50c04f69084dd9222c021ef5fce14d4b6
+
+Msg = 01e76755007b2ee5ac9e1d4c8adabad6d0f9c1c08ac6e2622b7c1ead89bd3ad0921b9525b49a780a262fe8fc0904a80391717ad7cac9607de55f7c744af8a132ec45ce79723f4a4a8c8b9ef658b360bd3890df164c9f1cd74eafb74feea251a34514ff2a57ae7a6d4bec2067cbf6ee4fdaabf13721bf9ae178b9034ac5e9665b
+d = 0fa3f15a506ccf7b50bbbad0a54d3223f5a95eb54f0d1f4e5d0cc21469b
+Qx = 0e797527d57fb3a18c71d1e82e7935e37e719439952d4b972f0c1e0c835
+Qy = 0a345bef4c5015e97a148b8991bed4b7ef48947b12f316b5621e94d49d5
+k = 075afdc12d4d50a7495f5a7d309696dca23e9356a0cab11c3b3d7b8c54d
+R = 0960ef460000fe8c761038bab7e29d665100494d0874b6556862c2808aa
+S = 08d3c004426dde6c18b1c9ae00a44ac947e36755d8c40eecf47bfa963fe
+
+[B-233,SHA-512]
+
+Msg = e95abeeb2c51a8cb75ab74253dbe130b5560cd52e2a63d501d26e1458aa568aca6694be91eee5fdfcf582c47c1c727084ee2b2c810281cf9b095808bf7e7c668eff00a6e48b06df3fe6a445e092c24d5687d7d89acc8063275caac186c441bc697b2f67aa71b03294e1adeb7e557c296dd91304ba0587cda3c984619f1eb4f2b
+d = 06400a4830889115aa88b860b3fb65905b01fd126c4aec2785518c2543a
+Qx = 1a2051662c1681bbbf6bccbd33c44c7c7fc80b81a1bce14caa36a73f7a8
+Qy = 11583d3ba8f22080488471d8103f868100a97af94809b58bff1435b16a9
+k = 0ceac6e5d10c55888b9ecab8d3f6ada7f4d0bde2f109699157d194efa42
+R = 0c148f2337008ccc3e61501dc5df3ec95d3596d97eae96a7ab085a915d8
+S = 036d1debebaaef50243005e25c791b9674cd6fa986dc3d32e089fbfb2ec
+
+Msg = bb8d8515365d240b2071daef0d80558fd3d0e059be9f6abb7b7a0a5f47e2ddca7d1b3b5101d5c583143258520ce8db0a87f877a395615c9bf879ef46f2f20f68bbc9706f82781fad69019396b27f292cdc70fff1772e90205a2225f80889f9daece1d03914d8776ac5bad24d8fb190ba10a2ca17768b918c2e079d83734eb372
+d = 0c7b73c324250f14fac0edc941f79bdbc6933ee8f64bf94b847bee5eef6
+Qx = 1af7266ee56bf0518f2875d4f4d9ec508a01769d9c1fd0a885a48bbd80c
+Qy = 084167ada99502475478465315bf8163870a9ec1b43f15d68f0304ab03c
+k = 03badc9b8098c3b4d7e943a2365093028b579519031a8643b50c0f81eec
+R = 07ad4fc96c21963395f56eb63e1b0b4d2c93d827626e7bd4448697ded97
+S = 0e7504e6a9f662472e3e6f18a40f7645922fad2ef7313d600a5a6ee314d
+
+Msg = cd8b2403435fac9caeffa21b55eaba52d7efee0f89df7142340cdffeb89556303ca01a800429397e2ff6c746743b6bc60a87133274282d4cac02e4ca90ad95d80c93b84163b96296f67d40b2a1124b2b6534ab6b60fdee312fbcdf468d0e84eb85fce4ff360136bb31ced3998d29cfaa3ae685e638ee272058f123c4f35f8b6b
+d = 03db7f28e161abf52ab0adc8c4c8544fc989af081303b8688f22b7b2eb7
+Qx = 0ab94312e53832265b929f3d529bec33dbcc5c17b969e0afbe2d559ec39
+Qy = 1d53b2c1be229e2c224e6e9fcb8bb0f044f3f9f5677c60bc9454f36eb06
+k = 034a8f980896284fe6d28b0b49703f1384d799e3f11a04b1e62da12965c
+R = 0e374fb355f30d7e427bc5db99ed76a914d6e286099c72f28c07302c741
+S = 08d5ffd41f8a1fd3de6c433635fddcfc2b21809d91496ac17571afbb856
+
+Msg = 4bb08eeb202564efb5bda40777d71f1bcc4c7c10b611e803e5c570876f3e319e9e2bc2d32031c56a32fc0d1fcf620d4e4377d881e9e1695bcdb78acba370b849115b86c1c4b83edfa03299da8e7fd14c7cadb81a8e4911c8e427e32c8c9b67e317575331967cf58085cff0c0d48ee0b8e7dc0b49687bb1c70c703a5dad08ec81
+d = 07e9d2fdd017d6da6029e88f78927d9ac9437f542db1f1fa99e32bfcf1a
+Qx = 18429bf08752aa470a8f0801170a7ab96adfb168ee8212d76ab0b994e46
+Qy = 072a5071ce308d7daefb3e8f4da4681842ffe0f35dd8b071f0775c83f82
+k = 0a0f330e011d34714875500b70c881ff6b1c9e96da930eef75ec78ac120
+R = 0439bcdb86d40e8f64db5dbead95d85d6a771d811480c5765ffcbf75422
+S = 06c01f64e2812d18b0946ea4e6599e8cfca0a2b606c3c35c803ef2cfed3
+
+Msg = 0bce683d835fe64e6484328aa13e18b0956f6887b5e4442fce36ff09aed015889794e79da8aa60b4be565c78685674c51e1e7ac60db6a763c777198a56e382a03aff8b40862f961ae23e8b8683b76a5577769422418972ab0049119382edde9e752b42e8b93f403c1ef8665d7ce8530ce4ed9ebf6d397827cba6b7645e177231
+d = 0c94052760fc74c2b405ee4dd5dd2a7d38ebc16df9cc32df706075450b5
+Qx = 1d2a5ee02d97f82ea9c8833b825cc57b0cb51d3f2a2cfa7577eba676eca
+Qy = 149c68d98d0e9cb242962326a26164f3e3cb6d81b51f281474b0f8d333b
+k = 0fdd3ade90da682676d40008cebeadb9b2378d8a821e9e9428018cdc768
+R = 0f6d244daea95002daff2ff6513da694eee58f8b6c2d47ad121be87559a
+S = 0b04788fbb5655a053d0fb7a38c39e1fef68ff17860442ec8b8ad049842
+
+Msg = a6defc770426daad4dafba3bbd2a69881334f7c31269b297e440926db54cdad3fd7ad200f5ada2b72ad221ad99a06ecac9c2563a8deed89f0d0896991d1a652f6fa282affefbdb1c1985652300d1792725071631d75a182b683a48448063c7d2563ec3d430e0fd3acea33a35cd38ec0b5b07af96af71d0bfcd879d9864ededf3
+d = 04076b93487c2da8aeaeb4725fb53b7b41b465315335c18c6ca041175b4
+Qx = 158755fd290910498f6c8eed83bcebcd1fcafef4878c860da118efa250c
+Qy = 1781fdae501c2c147eca2c6c809d9428fff2f853b57c7d6add70fcfaa0e
+k = 07debe933553ba3420aa06e1bc52a1653f8a19b59c0bc9c47212389442e
+R = 09e09c6d96e33c845535468ec7f5b79cf30123538011d0b5ffd935d168f
+S = 0963bbae921317666f5852759e9ebf05cd026a5d9f026942835ff0daeb2
+
+Msg = 7803cdf4758c199962b62943f475c6c31356f5d9b997a12e21146a2399cd0dd3b97a860b2ce639e2801571599136d4a8cdbfb12fd1a5ce22374991e090533ff42823a2c58d2076b772814eea7fd7a1fde68263ef912681c72c7aa3e5a7cc44ee8c65e72228b7631e600121ea35bfbbc783b6ae3c0c8f80198ada218be533760b
+d = 076ddd73ee4fc1f5e6766e229cc7236cdfce312417ea291f7c3328d5ab1
+Qx = 15185e029c0d4eb5102e0fe900ef3c921acc744feb44570a288015d0908
+Qy = 0ed56bf93394a434cd84b521040d40452bb39755da5e273a05e8c0ba792
+k = 084e9e4a9c84a602c18bbb6b183d06969c8b8538e2ff901f1c2794d5eb5
+R = 0fde8e9b1959477ddb3423661df1e7182e4b583849d6d17fafd7dc5406c
+S = 01a12bd30e9c8b74912c670c0845ff5ecc77f29797160bd4992efa61f4c
+
+Msg = e789461e1dad0b6e21abeb6ae2e96385549d1bae39415188c8f833233da6a3328144c97ddb36e0ff4d9e19d84f869e79e609c51b32de59892fb0446dd28cc164a3e53534c950d26f87fb74e682db2038cde778bde06c3ee2eca2a077d8fcc2b0332e352e0e7e6487444a8ad60e78ff213b16fda9faf374dc6d27b7a3c4c6d196
+d = 07e1f8988ad804aae7d09a99be19384cc599e7652c02c391542be74b17b
+Qx = 1fa4751e507740a7345e06a8964022fc6caa901cf0c2077a2c0fb86be8a
+Qy = 0683c593a0bcd123d958deb6b430d49d5a2386d44706f4149dc526ad896
+k = 01d288de55b90dbe72cd8f1f86a3ffbc2902f4b5f0cf4e641d32aec6f20
+R = 0048d16d87dbf4fb8e994dd874c10d5d16846b9ce2cbd43d09df62ca970
+S = 0e2ee47f422095d629c188df97e2839fc6239b9e2dc26baf8161b037236
+
+Msg = 9b58c145d1b6c887f2b25fb672cd49c3a1117224be697c15182d4048be92968a6500f8bcf747fcf33145c13a8d72e891a6e0c4c7310c2b62f3181bf586fe32f1ecf4feee8c2c8bf6c2bfdf9d5f88981ce080095c93e49a772d8e7b59f9cffccec3ca2f212ef4c6748f64e224f4f098334d83108bf6f8c7b43c5eb549f1526897
+d = 09b2292b0244c2aabe8b43d95039984d504ebe05eaff318760e4dee739f
+Qx = 12618d89f50b7f83ac470705dbe9ed81beb03929732a3f2aa7a636eaf59
+Qy = 15f0f70c808e053b112a8c32ee422aac2b926c5b6a279a787fddf819990
+k = 0fb38174a83ceb9236fec8ea39be2b3c77c3dd2cf42d140e27838202d08
+R = 084941856a387a56022727f81a939d77d12b01dab603ea0cdef6d9cd6c0
+S = 0bb9fc30595f94d664a590ed4f163e4526809819baf96bbee629ff86bd9
+
+Msg = 52310a901fe9681a23dd6e02f12974d57f2c4f653322d9a0ff8b338cc6c2bd9f4765c90c6b3c9fb17df3f492e67d204e39d81a8fdeb92c852a1dcc6151ed6c63049037235c6751c9a902748163a567b714725b4d3995e0edbde03215c645b1a1da3147f7406245432800c50f823a1f991c863427ff4c68e4e16d1b106ee40dd9
+d = 07ca463b50fdd92d9163f1c2bdfce2ee45ba1437b79162e3e959b814cab
+Qx = 08eeeb146216c73ccff0096e1100008f8b1f3f0c5754c0abc4ed39f7f63
+Qy = 18c9228b11888edd66b2e661284f583a0e8d3c3e922932cd9fc1568f959
+k = 0025291ec0dc2b0c709c5e69695980564552545c2497636b814aa049ccd
+R = 098dc98457ce6e69f77123d5d2460ff569786dd60fe07e847ed5bc14da9
+S = 0cd320afad2a4247fea5b74d78dc3df8967ab3159b4c8b191814d368dc2
+
+Msg = ff419c011601cfaf833067cf28dbe6e935ebeddf8b5111a97f6eebf3bb28376334f329cd877a134b074790a073db766efe018fce666a34650cbac285ae856fb6b3b8b96877282bc11cd9f9c8e510ed1f69bc2725a44a1d2b35de1edfd8bc9d20c7525ab0bbc27662a7cfc1bbd1e0f4fce5b88411521e3893e027cc8c73acdabd
+d = 0c3844750f63fe0c2e930bc38fe88522f4e72a2fd0db9778ade20e939b3
+Qx = 075acb00b5999f8b272a15a2cbdf8cb630dc3eeb1e78e58f58e467396f2
+Qy = 16711aca424ca335878d273eca75d804d3f009a1f3628568530ef265eaa
+k = 0a63e7a20d100f14b8b709f0a6c383166c2151a36dc471f061b0f20dac6
+R = 04063be9d8e4f0f9afe0c79374c69b36910b5d2b1010e0f4db2e4cd23da
+S = 06a6eb90659aa79e4a2360ea9ffb99a415175dac6c3efef104bef6fd57e
+
+Msg = 05a89c4824c5de66587875011e704bc6e06e991ba8f3aed331cfffe55aa266a08c729f77b8d082dca4d286b2d451ea838d726cc2cf298fddf2d7376714c5e37b64506f353917caec525a1209391449c078c5197a371feade74f8fc8a1a1d67576edfda13c14ad324342fc0b09277941dc072ec0d39434ff1cb91fc59478fcde7
+d = 0a3bea235dea86506be4476eb7999dcb8e584a34238c4a894ad6823b93f
+Qx = 14093a072c21c44d1c4beddc5c8dd9a2845db0935bbb4e1c4edb0aee032
+Qy = 13286ed584deb744c9c35d7ae7eb9cad1c7ba2b670642de0399b230716d
+k = 078eda19f0cced2f84c1a7b354e5a79bec035b8bb279473f32d60f5d17f
+R = 0964e817f0cdc251eede4157a9bd830c476627c3f27d2931b4f593b0178
+S = 08dbf34e597ae06ad92b13900a4944e54a5bf0f16f586baad157da6dc96
+
+Msg = 13e6b5241365d9d0ef9e8b05cabb3248afd221ec02eab92284b98bda3d9272184bfe5251d35705defba5085381430e99b33a3ab77d7870e5102757d065862372df2434a25556b76e54ebc39d4e6c3aba5cd6acf0c335756f7d9385c1068d4cfa37526a9a58c0ccc7f87a8189176c5d4f201499236058ec061357dcdb5acdba40
+d = 09a367cd1cffd8dfcca179e167ea437ee48e9b6f42559dda9224701d3f6
+Qx = 1052d751901f6f8e61858d3b15eb59dedd21e4e997531ef65622d575029
+Qy = 112737be67ec621509d73cd613d7b448035397fa66eb881f90a6d531ea4
+k = 0d8dd8f1cab623ba6a4e840962fb31de97a4d14aa6dd34dd21154105030
+R = 0a8276d0f069f34c60b26a55d47df69e4c9ae2981afc59e14b5bfcaa498
+S = 09351c4b3a06b839eb2e9f450d9c3d15efa45509886ea3f2610ee1dd156
+
+Msg = 139a1a5090b97afb8fecfff8745efacf7dcf91a4393a7b629564e598d58d5be39c05c5830d4c8ca85d29e9e2c31ad0447864e867d0ef4788ac734f8d871daebceda98d449308c2afbe97724c3af8a468f1925065f39e52ba4b7d15728a744b1252a20476dcfff7bcb82aa72c209e72abb3c24419bc26191390ffed340c1b9c6f
+d = 046f4ad2522e78b9b35297d28f361fb0ce82306322aedc119251d8241be
+Qx = 0b976c53a966e0834d5f6bc3af10a5f12cb6d16cb2303a3c6cee7d35f22
+Qy = 1a1097cb56662265f4f2f52df375d70af086264752477c34c6af522f1ec
+k = 06a0d21e5aadcb0c9e3f9fedd2d896b0236dc90e33778fb114e970122bc
+R = 068063fe0a31b7e7925cf8959c3486985d98f58224d5f67cd0218af192b
+S = 0f11a22ced98173040062ff9e69d1b2a1b5a939eda0a6944e96fc62fa4a
+
+Msg = 3315e5cda5f252e3291b61e493ab919c20a8af1286d9660cfa2f5ca38b6defe19ebecf820787fe692d04eae8a5f5d37abfb593309569cedf45efd0cecef6951b718924c8380ba52e8ab8c9bfb2261ed5f01cc5a5f9fc5fcdd269a0f122c597afdd9a836cf8f96838c3e8962c1788c3ce4128719b3ef4fc88569643dcad6da16f
+d = 0ac82137e9c7a5ecfb8b1a7df9ab50732934566a392a6c8915ee8ca8144
+Qx = 00f7f835f8223fa6c49eaf6650e33dc9d09e1d2bb098925d908606570b2
+Qy = 06e659ce8623767e8214b076d7588746bfdcbbed59b75bb19477366cc78
+k = 080655784e3e31c6a498a63d4d84f7e5a353a66641ca17d4e223441bb1d
+R = 07faf31d1d31ef4edac1c63072350536df84c417e0ef808c6be39617e74
+S = 089023aeb53ddd3e475d11c53479863739e62dd64348646581012784689
+
+
+[B-283,SHA-224]
+
+Msg = 067f27bbcecbad85277fa3629da11a24b2f19ba1e65a69d827fad430346c9d102e1b4452d04147c8133acc1e268490cd342a54065a1bd6470aabbad42fbddc54a9a76c68aceba397cb350327c5e6f5a6df0b5b5560f04700d536b384dd4b412e74fd1b8f782611e9426bf8ca77b2448d9a9f415bcfee30dda1ccb49737994f2d
+d = 299ff06e019b5f78a1aec39706b22213abb601bd62b9979bf9bc89fb702e724e3ada994
+Qx = 405030ce5c073702cffd2d273a3799a91ef916fcd35dfadcdcd7111c2315eba8ca4c5e3
+Qy = 75988c6602a132fa0541c5fda62617c65cfa17062a1c72b17c975199ca05ab72e5fe9c6
+k = 2af633ac1aee8993fc951712866d629b43ed4d568afa70287f971e8320fe17b69b34b5d
+R = 165ce308157f6ed7b5de4e2ffcaf5f7eff6cc2264f9234c61950ad7ac9e9d53b32f5b40
+S = 06e30c3406781f63d0fc5596331d476da0c038904a0aa181208052dc2ffbdb298568565
+
+Msg = 44adcb7e2462247b44c59608cbe228ada574ecb9f6f38baf30e42b589fb9b157bb0560e5a2aa5523b71cc0d7f583b502bec45d9b8352f29ee1842f42a17a5b16136feaa2efa4a0ae306402940ecd6b71e57d1467c98e7960de2a97f88b43487e4f4016af1292381d70c18c7e6eed99a14cdeb5b3caf73688658e4c5b54c81e08
+d = 09c2804f8cab768248fb3fff8a055b3f4585c00de5c1615a19f9425b9432ea09afba8f2
+Qx = 2570ff62b03a5124f08f752aa71ddc57944cd94197fd286d5a2a107b116d7b8ff1b0421
+Qy = 37714d9abe9aa0a9668fce89a3fcd5cf2e4548102a181a777c9b3f1008ac6e8d3a31a2f
+k = 0dab5ef658ae3e2ce2bc5c88a8b8022a0ca5eb8524815ffae414327e3afaea5fcb8a7cf
+R = 2d99f82d92c9554722bb793988af0fd0bea776c5608f5939db7c8634eeb24ffd381dbef
+S = 27ceb1d01ec9a3ec0e74d79e08024359e117488020de6458fbbcad28b173918fc7d129c
+
+Msg = cffee6252c7eb6d91d8fe100a1e62f0ad9f862d78ca2b747a6c17b8c9ea8980dc239b3b673310e6e7483582399163e39d889abc1a613fe77849ebc09b4f7f4fe0688b8a9869ae918a88294c7ee199be50ee9460db14725ae70b449d0cb48f30e7d817ec02c0cd586119341dba0b74f0279330807cfccc99c8c340b72c1764a45
+d = 2e625a6bc6d0ce7c06231de827068bdb0abc8ffb57c82b35ee3a0f873b9473905974d34
+Qx = 0458bf39974812a4e0964c31f40083300454104c0d65f22c5688bfff3c256b7ea958900
+Qy = 738dd33e32b9af93ade2dddf4147187a9270543afdfd66a0f2a53d6d3d815ef59795f60
+k = 0a9388815c528fdadcc5d3b125c7a38db57fa8c163ba795ee00e8e307bf760619e705c9
+R = 2481571400ecf9dd31dbd9c905fa1006cd5bc7afae759da3312ead8d5a7dd0c25a37ab9
+S = 13952fa427d348b6347b9e93d4cb2c4cae3429dbea6aafd1e58d5a34805098722b3b8da
+
+Msg = d058ab5dc07228253707ef224897ea0fcd09c3d5cc91fdce9e03c1c59c53fb4596be2ed929c7455e67ac7f4891aed3eb06ad88f2c4aaaabff045b959f900d1019d706b60526375851bb891494e99995928e4cd51c9616aa651ec77bd7e398916bb9ed3156391bf7fb1e29181e2b011dae2edaf803607def2ac6b194929a57f45
+d = 376ac24e1b86f8a55c052d92a0bdc6472fa03acdcdbccbf7c321ec0ccd97aa0a66b4181
+Qx = 7247c755b23bddf944e29348da82495b4f61d02a482c6111d8698cc77e8dda4c341f20b
+Qy = 0f8c199138e1f4f8344facd90ac62d55f3c9a15ba7a672ce40241aa26419af790cf7dd6
+k = 25d07c7afc5a335c2bd7863c1965a48c12f2687b2a365a7c2700b008ee8a0e8e35a68a1
+R = 23fc2837a879b79e470305088acf596eb0159edc2008478cc4c3841a1bd66fab34bbb5e
+S = 0a909b83bf77e74511063366ea1d1308a8a544864783459a60fb2669785ab1af8f4cb06
+
+Msg = c86f2cc7ab5df5cf1a236fd83792769474cef464032800ffe98a44cf29dbfb6f24088160eb31a11a382ff2a49f3e05e983462f5304272f96c0a002b69af3d233aebe867ee63fa46666760a6889d022c18645b491f8d71b6a3b6b4ef058e280cf625198715b64b025bf0449445d3dd7e1f27153926e617bd2c96638345431d1ed
+d = 2b50a6395fc02b9ac1841323de4520292f913519bc0d6a471aa28021322fc4dbcd7b802
+Qx = 696d5ac4bc40e679524e246210b7bb0f93ccfe7dc506ba87be3fd018f829c93e62ad1d8
+Qy = 65953e01d9db8fc5d64516d864a33aa14af023e601d69875ac0f7af92a1e78aff0e475d
+k = 0aa25b43329de4e7739fd9134e4f4b3d68a64e55af47a2f6ccf71f518f19059b68d34cc
+R = 1338a5dda5fa09667604a6a7666b0e54e6b688b98b31c25d037ddf55ee6bee7565dad09
+S = 00aec025232c16e778f90785ded5348f3d5345b8344b2a762480383777328e0a0b11cb3
+
+Msg = c1328d8d2e5b6ffc850a9600bd6482518ddd9cee3fc9140febb72bcd444b0cd7e8074587d51b62cce4b3d4f34ad3355353fabe363369cf790db2df9fdac3a0ec4757e2dfb3b683eaa3e26531691ce765742e1c0bdc0e1028d347b6085fc459df0989c6a144271454eaffe413cae2ad7c8b2371fd2df1afffe56df727009765a2
+d = 24e5889722f6c35e18ca47effa9e415b1ba790066a91fb3c9f7b001ce28fc732b09bc23
+Qx = 7d4a57e6aaec6b51dce5408f6a7fbe9ba9d55f5abe2da55fcf015ca25dd74eb61c1556c
+Qy = 2123390178b2992059151afb51ac652b364f562c65451eccc65d968e9e7210921c93c9c
+k = 320d2a7f48cf3583e8d7e712b330d40ddbe4b6c128be5a43d72bf57d4227603762de7f0
+R = 09806a8e70742c6c4a9ee6f77fe7a36489e1fe8c442ddf9cdcfa61f019ab9b41241d949
+S = 061fda247ba7c198aa532906bc01d509088d6c2ba0f14ca3ecc5ba36f3595db1df3e64c
+
+Msg = 7176b7013ea27e94281977eacb976bb31c753bf80fa09680a29128a6fc15234f79f0e9900aff3217ce9be72c378042c6c34fced0158740073d1a985fa25987fb218002e425868fda5a47de51abfd04de34e2b8634cebfbdc98e80f93d94096193eaa82dc8778fc23f3765c7acdad94fdaa272df0ff0f28190c10a462ee78ac92
+d = 056d15b81f40b6378588a5efe43e21b95e18120d514bfdda0e7759a1d0766a8a35ce5ac
+Qx = 306cb78fa576bdd2f43cf7b71d7e66a98b850d87ac087dd2e1ff62596a2e8d4cfff1344
+Qy = 3b1e3b12db842e00c2faef04d3e39cdb71546e4e3ecf21eacb6131c3501fa30edcc0b70
+k = 1e8969d6cad41a40d8306d2a8db3290d547106eb59f661e0d0eeb163044a92aee4483fc
+R = 06786637c3bd5a95eba5ce015f151d99845255175ebb9e593d912c75cc45723612c4ed5
+S = 384471c17c45ddcf62b588993835bb913be88f7a8e46e52e211972ffb3b7768410bcb7a
+
+Msg = 4c3642ba040a9955b9d50dcd1c936688c17c363854358afa8ca49c6abd906dfdc4d89bb4cab0bbc363fb5b74e1f004d4b09ec9dfeed4c0bfb482a9061a1f487a3d79195ff7b65a0504bced3a28db0ebe8fcf8ab1ee4a3ae91324d15d890ac4c479144dd5538d2e36d3a587769ee9cd2d5c6f85a03362a022fe0efc4a3902b71a
+d = 12fb2fb5bf5f7e42a500154823a174ba2d05af71e3b0cf47fab46e673ea1822f1563def
+Qx = 2414d172d74a6281169835d18bfaae91f1f1cdfa9ed451884466e63160ecdd4a2c7906f
+Qy = 2d892bb19b47a4fd9d851d3b101ba99acf6d11345596635cedd5d7557427a2896a913c9
+k = 20786f42d77195bea5761f86dbed8b452f858b447d2f3775ba2a4865d738122363b50e3
+R = 334507412368f08bd0992a5d56581ea7139e8adc88abe4bd80dfeefdc7a37a481b18609
+S = 0fd8404df06a02618cdbf6c28610d5dfac9907635d9e5f2887f11a7f18cb8b7ac95b5d5
+
+Msg = e471f39c18b081362adc7da47dec254dab8d765f005ac574640d78c14222639245563912d942f3be212ee3cef134407334c8fe3602fa0e1629de5331643d76715dc1b0ffcebd484d86c5211be4b285a31688b205fa988e6c15b36daf396ccdcc209c7dde2a732f5c31c84c7ea041408ebf15e56632583af0131bd7f531b5fc45
+d = 30096c54fd480647e017f8cdbbdef292e799f054e3279d228b09816a757566a744a8266
+Qx = 2d4b28fec18cd888017fd5a27a375131bec3aa7195c0a4f255eeb3616437079e356a6cc
+Qy = 27c607dcf0b068418eaa7de8da6f9707650e8d95aec571f7ec794415fc175061b451519
+k = 36880905a376faa594978713c2de1a90c8e27baee65bc60b1fa6508fab5abf843f66ecf
+R = 295193f1c64181bdf749987bbc8ff2a188126131f8f932bb8ca952ffa201f109762e18a
+S = 381c496b4035bba880225dcfe74fcf101103e38f9518d9427c74a5ec86ebf8f7183694e
+
+Msg = 8a93fe53e83075c4025228540af7e96a588520da34e3eadeb99a4ab2f3dbbb8f85fe63a3b86c1f4ec912e665ca05b43e869985eae3791b91205afb1380e16c25b74e6793fa63e4a55dcf25dc22d03f09deddeb9042b620434111afe08c5657c7d754af66ad91a1b5423301b1e8e6389a1404060d1b6a99fe0f89598482979e42
+d = 0a1b7e9c8c2dc25b494b5ef3195b294e41cd3c2c35235ab42542bd3e2a52d5826662bf9
+Qx = 6232063dbb66a56e2a92dbdfd9b3c136eade9c214d831691d9b49c56a3962d20f14b8a9
+Qy = 1b47b85bc223fde1918abf6308b74dff7f3e686af9c9d7a1855a1b77984d258c1f9aeda
+k = 29b4221eebe151fe758218138535d81182c991c3b7fed93f9a6117e98c1c2f97e546937
+R = 1f8040fad671e2f32a1094413ee955ea5426bc906b8e034d87d7408e63db173b05afbfa
+S = 22a353c431a9e9315ff69facfa4e15f6e6ee1be2750472823db31b49b17fc759e6b94db
+
+Msg = e193a8ef6f454ca1aed38bb67aca6d08280d421b196d89938c0582b7cde74dafd71716f3818940af412d4a7ff3960a8517aee108ae03576b68ee7557d35e6f1ab823d124de7243dd02b542591f62c80d822608572889573e4c9dc62f99d68e07800da6f83cb6f5e03d1f2ac15f90e38b4f25e0a75e354e4b60cc81c0bbe81d39
+d = 059b1a8fb84530bba7a607ee88310e31bc6ea6a6881603567a1081a05a3a9ff87e719ef
+Qx = 0b9a71aa3cb4cff37586b1e522b0e332ad5962eec3dfeffcef3851976baadf611ae5226
+Qy = 6b1bf0b43b406b5edc6782fd391d9fb070fa3570d3cd5b2b66d7a95dbc45ccb1626172c
+k = 00a77307da9845ec4572a24c9e74a17b76b6393da87a9d7b1b8456235473ff39d243ec7
+R = 36721835be490b5ffc4a42bee3c6d231417f7038c367efd9ecaf7fb3618ae8492906de0
+S = 237833bcc3e4a721e2079e579d1aaf2519c01cc238056fe0c0990dac7fe50e75eaf6f96
+
+Msg = 8a99b9db191f6cabc88b430bc2293e6774d5180f019d871839289e25aec29379f14606e742190b7aa062e3b29fe0254146d9614856c5140c7315015abb98ac00da2c7e33cbcc82c24b797366f12767322c4381454d9d1eeaedb616b0ea5c66d1422da459f18081f4f966d05ce279c6ee69b1bf94b8388d38d4b770d9ed69025f
+d = 30ddc2c7a4ce300cc2b75f0f977033f16c1f8bb13aae3d494c381f9a6dc8622499ae4df
+Qx = 47bdfd7c77ae0c53e327c15c30d90ab1c9b670fe2241dc0ffa939fec3cf6d3c1f493f3a
+Qy = 6a286aa2310a4d0468b62f3144a9da2e66d15bf86f60045824278e8986ff87a27611920
+k = 38afc3d11c66eba3441a5ea298fa593eec57b84ea29973c306ac9d46bb8d8e2f4c8b049
+R = 06c830f6c0be99fea4712f1c75f5a4e439800dcf062a16d93135c3255d3cd04bef5bc7b
+S = 1eddfda0d0e02d382ae243e604f76939dc21f3ce106243b2d20aa562b78e620fb456428
+
+Msg = 5c437b331831530aa94623b1736f00b986172699f0a02a5e5df0008bf25341787e2e66046f2c929dfe0058c3cb89fc5bebbe1025bb1edd1ee31522ed568e7b5b4ca3991afdc76a68cbc2c4f81863e27fdaf6a564fab2c6354e5c657de81390f8a4132669fd24a48580c716b5b7961a9c091f614d11cf45dfdaec8946a54a11d8
+d = 07899928922fbfdb5407517725edf231d15a8b62d90b7fb6d8c8d20424850dc44f797ed
+Qx = 614257f54514cf37df2cd78850658a85ee362764ab8186423aa0f9a1ff486557f8f167f
+Qy = 3ceae9d1370df045d20f576931ca63bdba8885f463d5c82e5edca5116ed3d2c2b0c4861
+k = 3395493478e69e6e1088166f622a4f9ec7feb998aa552b54bcf0fc67c06079f45a14993
+R = 3f31ad171dd59c9deb21851e631f223584b17f72a6807d5239ae31373512def954d5ebe
+S = 28f095ae43ba5bdd899573ce6823eccd8e127c6c03cb59dff43c087ca24e1ce5504d1ed
+
+Msg = 91aa08567d8da4c90684dc06068f69deae240212842ff1786f04ec41b40d9187aa92c76401f9fcedced62876a34df82ad7c1e63b68bb2a972257ea8542bda6a7f1a020c9b122943b6d651abda8b8d322a8fb762eee376daa2d3637a71ed6c4f5cf96f61c0da2d6e1dda3370d80e51da2cbd8aef3267168c67359523faf910dfb
+d = 2a2af63d1171930758bd3e5bfdac62cca1a83a3b55a49b3f80cf0d9ee4b2082757beac0
+Qx = 7dd6fd0868ec478e7e5c08965fa4f1efe8db4d0c04f0b6c63b5dfa397607a0d9d5ce909
+Qy = 54ff4fba9058179a2c61951fb4955cb637b01267f8f08b3aad614738c562f602d498f04
+k = 179482dddd033e8849abfd4991304137044d7433d7bf858a794340ea1cd66e736b821fb
+R = 071f4cb000ca1c51c698c867a78961e6d7defbd60109f79d1d165ed045a653ddebabd10
+S = 1e2975f4a1fce0b3b0e13c3f50005fa664ee9319cf774d2e107c406d36158bcecb0e5bc
+
+Msg = eb5297bf408c1a55e400a20a3c10acbc5c2bc6d6ccfcc0941fb7a6fd4d2834415a6df86c3a6c4b867d1215aeb8222153da8cbbb1576c92c07ca2c36d8f243fd911f9a057e39ee25832454e28d7ed52a8d04169b9b9677a16b32d5d211b8573a8986e9bf36d7206417ad2771daa11bc21fd7ee1029b65ff7c9b2705a6dc9cf9cb
+d = 35994e89e13916ad82608f74a639e6aceb756ff913aec440519946d6434af9a60a6af49
+Qx = 1f7805dfc9f90d4f8a1b241dc9d68aa41cb77b63d530cb3733cede23bb87ee5118e5bbe
+Qy = 1c3f1aa3a1218de78a94ee8f88d3f787fdc68674e31792d919dbca681a6db1dabe89b61
+k = 2116684a4307c67a3d8c1014b33b928a962a8daf86c4031b0c1d47315d74bad7dab2aad
+R = 33cab952e9382dc074d666f1f2ab2bd72ba394a404ce2fd02a6f7a4dc096d713827c94b
+S = 33b2886738d882146c0cd715701fe4e8b94b0d28c73a6b79d2899391119ba910bcbe3be
+
+[B-283,SHA-256]
+
+Msg = f415d0adcd533dd8318b94560f86732c262ad2c6dff9dc83e2435543f429a2158cd2fbab0d96c027f71008c4895ecc644c2ceaefa80937f6cc6338d15d36e459a16bd9387a361a6d800acfd834ad5aecf442e30b70f5bfa164747cf9f89325b80976052a83a5e896c00c54f81472b14329cf23bec10a8e693005de2a506ba83d
+d = 29639da33f48e4fb0d9efdf50bba550e739f0d2476385cba09d926e789191b6fb0a73ff
+Qx = 770f9693777e261db9c700eb1af0b9e9d837ce5eabd8ed7864580bfb7672ced8ffca598
+Qy = 68aef01c8126889204aaca8f3ccb089596f85e2aca773634bc5775ee4d27c77f2af83e7
+k = 32a930fdb1ba2338554a252d1bf7f0169d18750a4ec4878d2968c5e735f98b9d0c25edb
+R = 30cd65f1097d3fa0d05e1d6072675f1377a883b683c54b8a1f4960f90d68f3ee8c7bd98
+S = 15c61ddf43386a2b8cf557760200ac06a480797e21c92e45e6a311e1a508b03c4d9632e
+
+Msg = b178d86c9335b85e02178fc4551769db589ab91d823fac219c7e14e2f029753b203962389476723832f8d9631dd7764e6dd35da290afa42a794476f5c7727b3688aced848dabc9954201578cc7b25801710931f45cba1199d3788d64dc0188412e70723fb25b8ecb6718358150c4037b5b81466dac1686cb5270bb1c72d34bb1
+d = 0583a7ecbf2a975a32d07428d27ac82e5dc13d1466c4fdfc1e6a05a8d9a289f1010617d
+Qx = 3775ec793ee4bff15027c70d9bb5dedfb7d2e41af8895faddddd4589cc5a00bd222b3bb
+Qy = 300f7cd572d82f2f0a2d99a83977ed2034e03fdd76a0267455a524bd8199424ae5b81ca
+k = 1e58b1f66c927f4ae16143856d67193d889debdac8eb03936f1b36d550c2f2639e13f8f
+R = 0f897dbc8ea12f4370fcd08e8700e5e4c68dff97495f401d01b782f2ebbe259bc0dcf25
+S = 3c32424fdcca39f411663284658b8f0c1f950f0cea4354f02f4b359f18e3fefac0976e1
+
+Msg = c8bfe9fa7c848531aa2762d48c153cd091100858aa0d79f994fd0e31b495ec662209a9c8761cd1d40c3d8c4262cf4dc83c4a2549a5cd477726ab6268b4b94a78b1c4a7e700812872d7f41912a723dd9abc305420ea1e1fb1fee41bf643f3a24abd6e8fbf6fde2475e290527724a6f99fd75374bf7cb01b34d3e60d8db33c4de1
+d = 0f817ab1b49131fb9bbe8c112c25a36f064efa85de7506fb9cd29d81b326bf276277f7f
+Qx = 2b3a06e07fce1848494d3227ff77d1c43f4ec3c037ad73ffebfebeeae87d3bff7f7e59a
+Qy = 75df52e6a34229266ff28b1c217538ae23b3912e4bae8de5cad9b57b7c1c9ca8aabb2e8
+k = 0ac57fbb899193b88fbf4ff2c502af72943b133e8d40459a833275212f6644f566f5c58
+R = 3e13307d5fc2b7ad24e9422355150578c78e1c99a6f9a24f9ca2e8bc6856936c5c4af2d
+S = 05e8b77b580cdacc2660e6f8a1877d93c5983d135d63ca0e0b06aa8daedf855c9f661fa
+
+Msg = 9a5f563d0f9fd1f31f3a822de628ae970954f4e71292492d727109036491c29e66b9b0f2c90c26abe94c08502f5e923a9ddaf6a7d91e9541ce90d0a49f03ce4e4769753d5b7d922e1ceaac4b4cfa4262732a09550aa076b8ff9d46a50fa17de17e3b6bd606698464d116fcd5f1ae11bf45b0c48d3b738427cb47b0d1272b03cc
+d = 2782af76ffebf3e2bfc0576b70e4f4bb87c762e2bb230d278ce776310a14f5b678f29af
+Qx = 00dc21b3be7efaba5c7f9f22591327f0f97083d4d844415d3148d227931256d026ec9d4
+Qy = 1276f1d9e131f13bb129a1192fa24602fb508c9679ad2124e49c70a891777cd601955fe
+k = 0255972b5329863f380de945574793beb0430dc416a8f2543330a125ce8d69f72dbdddf
+R = 25bcb54e188aef6e362a62fd88daaacc8e697dceadc8a6b6f804ce4a36856c8da6de97b
+S = 1e12e18e1e281606c16ed1f49804f8cfb33c29b0ae92c072d5c41ee3e6836cf1813d722
+
+Msg = 3d6b065721da9de82cb33ec2c27107eb399b1e69ac8fa51145ed4147e20d72e27434104e76af988a3bc94f55e36677a05182fe2376dbe38195fc6a30673a4dca87336c7304f3f31d49216fbdfea00fd1e105d8b0c13ab11f8892e0045e915c17dfaab07b24ed21b06af5a8cad4f45fbee5a25bb6e87466a7bc422c0bb896440b
+d = 31b827b88f14d3822244809096157df3c0aa99da90c00cd9f0b18dfe306f6881834e6b6
+Qx = 7b3ed076a2901ab2625bf05fa6db10a8c156412fd2d26741738f5eeb6a9189157526946
+Qy = 6a8cc2061352c36f264d23dc2857fbe02af34397ae5130c582e885f50f2c112f141c07f
+k = 0b36f5d6da409c4a27f38ff9686cbf5f4714f4e17234fbee6e6deec97c9f0d4c585d42d
+R = 356911114c9ff9ae4f3a4fcc5379c987b9d298554cdd39ce124f04707e7fd1ea25231e9
+S = 13c0a321c4c5a1e89dacddae38a9b3dda32a20627e53dcdf28ee26a550797c255eefe6c
+
+Msg = d125f0e2e6135567adec9e77da2afc6862e28d618416632ced829d14ee8b61116da59dfb44098a40a0b927731125617e3d2f32cfbd1546a6e758c1ab6597e75db07add52ecb61d37da2e9ed04df95b36ac249f4cbd794cb561655cbbe4b34834c497b3d392d78ed0db8db683aff0076fb6e43acba3fa2b91210cc6cf3fa594b0
+d = 27da4916f1c471cff80bfa14d12aa10270fc3b26caed010c0111f6e5a40d914a3927763
+Qx = 7d8202c88fb915446c521884fb756375a2b8d178f6a87306c1c8b67b926e830c8285c15
+Qy = 224dcebb8a7c46902532870ff855c780b2884dbce2956cd34dd6ffef8dc365b96753449
+k = 3fcb1e759418e4539f9be76354cc1914ccf9a111338890eef723431925fa132ebad8695
+R = 0d4d4f23408db58a72495aaec6dc335ce85309fedccb6ade053c23347abdc9e77a81aa1
+S = 129b6b322573dcc79704d08921cb54f31c571573da78cb09d0aab40c4036ee8f195d88a
+
+Msg = b380f97687ba24d617a42df1b14e5506edc4b62dfec35ed9fd886bb769832cec7f9adae10c21b7cd9152588797b4efc6b2b30a873d3f25e683ea9be070dd69731949a51121e534fabfa3a2eae0ee90a454182248bedf2595cd47ad08614177d58f7a773f5023b538f5f568682c83fb60e3fb1aa859948d01bf7b214e7f2dc719
+d = 10608eb51dc0ee97d6e488a23c582ecf0ea1df9a24db77094d87b3fb6ca98507280a934
+Qx = 399b3e571caecdfa1efb243323159a45618702600b870954cd614e494bccd70e381f68a
+Qy = 2e2fc57721a500611badf48fb435a6e399cea356d281e853f55ef2cf9fc5f70dc8b3da2
+k = 0a8045b4f55115dedd8d742545f9f2bd6e5ab81cdbd318747aebfe9f74b0cbc964b6040
+R = 2d022631bb7e05d316a1b130faaca5af5eac67dd25ad609e6e2a067ff74fd4ba534db2b
+S = 04595f184068433962d250394680701fbd2e2bd613a47e5de68fa1eb83cb08fb425571f
+
+Msg = 3f9ec57e4228e1a6ec49df02c58d756515305e48763ba1dc67298be9a1548576c28c82b4e9b3f62357d9b3c522b16d5c496a39effbdc8290edd2cadc0019e6b9fae1e61238b13b6265ad2ff413a5a0684babdb0013e7632051455e6fd943815213c555dba96cba8911e006bfddec6c3353065004538f37e48df9e339498d85c6
+d = 123f9eb8babed548df08cc3afc1d3b3bbed52b538d4654f2088fe76062fbea75b85a560
+Qx = 3b2e980ae7a847394720a9cb982fc1e41f9381b0f2e08b87fdff1bf891b9637cb22485e
+Qy = 4a367d593edfaa4e17113b6b1ea3ad185b3155b1bcbd9f00f4482e509b43bf7eb67a448
+k = 2adaba166d703d4d2d431a26200acea7fb47216fd04882f91c5730a55c349770d58a452
+R = 2c83e6a7b4fd48e1ba4fda8ed7891425213764078926d8862d0eb64765ee2900b3deccd
+S = 3561a949d583b7de9263d07ac427bc175b75dc52f43f3ebedf996218c94e51684ed5f9f
+
+Msg = bdbd7b7bf3337bd9d21a3c6db379f95408c17e49dd394e94737ceae889f45dc0ff5d48cadc53703a16b5589939506b548f8dfd34c577c084f372166cbea320c8fd07c809b211e0749ea639e68f890affa1569b66bd763c7c710989e491011371eb1d93ed9479ff0216b7f79c901a2023e2cf80b565d1c0517e73117190cd2f02
+d = 06a18e626452111922e02e31d662f4301319946a204ae8a34f06b91dd1b5b96456365e3
+Qx = 77c1fbe6a645b85fa0316ae412e8dc558c7c066d9aba900650749eb7b14a149ee57a259
+Qy = 1b2f3002ff4936653412c8ccb8a67dcae18d78dcf6dcaaa75061013d2134af2c3fa0e69
+k = 21bf4ca10d03a93d4675baa26285aaa554836bd0bab6e7fe42600ffe9137d5e304847e1
+R = 20702aa5b5cb45cbe8025b4ddda0a42a1ab746117d45382d018b2055b62791ad91abf54
+S = 12c31f9bdc096236d3ec46c4e6cdbcea47e4fba0e28d4df0fbc19e8740ce6dc0577b242
+
+Msg = 436b288512ea57bc24f84fdd117da9dc1858bae8c11637f99295d88fa9d05e3c053a2584a6fe200ad190b3077d9a1608f660349dda405066c1562f6897ef69b6b674d6bc11fa470d0b96a7cf8f6e098c9ac03b0ef415aa045867ac7c11d16cee78ecf08850ccabf70f761682b561d0d0e4a889d840dc74932648ca2fb58259f7
+d = 3307fd717015b12a2dc76ada21442ac1d97519f66898b214c2ea317ab0f0905e819e4e9
+Qx = 4ff9b8d60ed177df635a3953c0f5f5c0254224bc48d34329136706d6e8fa1b16ba0916a
+Qy = 2e50ef73f43ea9a5ad07c6bd68a82b7239534e195ee929aae7788c073dbe9e968c2828b
+k = 14d8339f610b348f4639ac20dfe2b525517218f0c71b1908d407603b25f19971a1b5b4d
+R = 2acf3dc4e3569e5038fe97920de626ddb36bf213afa0f939785dec8319eb8321234c574
+S = 01db40fa416527266a3949211fd9fec158412c447c392ed6a7c7f159a1129da864d33be
+
+Msg = 672faa156dc188bf16bf8933d65e091c633f294486049ce96a4a403dca28a149f4f840e8bef47412285363e9e89006614b013a41baad9885f1d9980cc897ffbd5f8a7d0e63feaeb42c07776efb307ed680ba1cebf470dd9bd8a2a9efc2b1daa569524394f9a50398add1a5bd2f7c263f9e63c2d49461acf98444fd23341ce78d
+d = 14f9f412e3c7d770626e800d43cfcbba3ae6aec8563af748e8a97b67d244334b6e6d2b3
+Qx = 2293b37c84e7514564635e517bbdb9bda0b4a41217ca64c38e94a4bd00753255b4cc389
+Qy = 088c10bd909964ecfe10c373214544c6f60ab85b8f5545afb0fd2ac03d036db7ea9e67a
+k = 19b21a4d73012dd2a2ec3ee280a9b855b89e6ad53438431cdb5d2cec0e5ba21300e9bd6
+R = 3baaac69d182bf1a12a024dbc9a52ba244a654716e2756c36ddf8ca634129cf9d2b23b2
+S = 13ed92730d0a6d75f2a4a56b39f82d063e1be988dc58f0ba5f553fa88b6510116005727
+
+Msg = 4321334cc8ee44f1cb392a4b280a95561809dd3639ddf43b6e11cb73067597988d95b8643d86c76c3c6b932d9262b9b8b55a04fba0666dd8b8ff1e8fdf799ae3945b6e30d3af3966f1a6d634d5e012710d66cb447fc3375130968a2e1e647780aada2609d87247c90338dd71c3bcc3902311caba27d5d4ea4d73ccea960d4bfa
+d = 3091a6a8bdac1e43542dce752694972e734dca31c061c7d1000754296d0748055db3f09
+Qx = 5c0761d01020a30c478617313c67008a1332a0e6f295c5a9f01b3411eef585a9dafc693
+Qy = 0eadfc6f7bb9986b0dd221b77b54287042ae8d1ae5788706b79a354fe785c66145bfe81
+k = 0afb2e2e29b26a686368b127e38c2f5726fd55a13e9f87cf00e831d3fe19d9511d07e81
+R = 2685f634a8c16ee79acf62b7a1fb3acaec0db47c6ff5f2c97a804e9550494b128b2287b
+S = 12b545bd76b8d2cdfc5452291d5e4748a5e981c400daeb65c20812a65bbe936bc613219
+
+Msg = 2087e22094570d39fa937f15a3ef0601709a66666344186a33b487d041793fbb9709a95af250b1df0762ea98e911aeb3ff1fa19f0aca53fd4179e454e0e91636e55cc5b17cad9e1575c82ad265dc34c4a66b7a31ecb9ef9dc756f2ac1d9dab35369a6bad4a0f47e629daab91addc6d297d1e5d81477b3966d8c3b607ed194d88
+d = 1195921b91353db9bcd00510efffe009c94f6bd8d790f5fb3e5a0101c9ca5d21c6ef2eb
+Qx = 5dd8aa95e24c054d508bc5081546677b9a8e8dad40d3f8a184af7cf07cdb09ffa2e0498
+Qy = 5032f208dc3bbad6aaab63211e13e17656c750c6c2a6e3caaf55a7c30ae5ba241d8641b
+k = 3223c6439db7255e89c28aeb046e906ba79f4e9b8222ba5ec201b964d3666301f74967b
+R = 0fb7e194dae6420ac447e7d4f882da3c4859f53a948833a0a08f918acbe03c2e915d1eb
+S = 2336f1206b46b3166b28918bdc1c817b22ab16b355030cfd635ab3dade20d2dbde08b6a
+
+Msg = 15c7bca449a73b03bbfa783f5a91ca0b7916889a5d99d541e2e8593c3b176a5b634ba20b34407fbd94ae1c1398f5313cab7402f3bcd7ad277a8c66d09a6df5dd086b20a0a3823fbbb80980cd86bd13e527eee15656cc977103e80113539e26695addd9eef6a1f56986168d9a53f8b5de833f8962c3826cca106ae9e8c00208d2
+d = 29dc20446e9abacb43823e12a83737b46e6e577466b5a3925e0f9d496824dadb4d4b50c
+Qx = 4b3c1d41d8172ba15fc92d9586f29716821ea82274ac8e4fb3452ccca3e34925f1e736c
+Qy = 23e22cec962d759bc659841f259de954911aa289e9994bd76a30149a73711bc41b29904
+k = 0931ef56f08c379d1ddce0649f45ec21eccf3dcfa178616f45b200a06f82172b91bffe1
+R = 178348d533217543af694c8d3cee8177e22740b657bc6ce6df9e57f0c1f14fc9407c440
+S = 3eb25dc4ed42495b54679653ab1cd4d61c854207994a7318026afdfd44c89cda9247388
+
+Msg = d12fbb82ee7a57eaf76b63fd6bc6c0a65c85f135f019d43ff7bc295cad15d53729d904fed63d69d3ffe8b82c0ebaf0399e2717ece40e011f710b5db46aa457c23b85545953398b814816a1e7a8ab5b0b14c4a0451b0bda9d0d2ec4a374bcaae208b7fe8056bfa17d6b7ffd4ba2e9179f49b9cd781b0c06f6ce3eec26cd428cb6
+d = 3b9b77d19a42e9a555da8ab70aa5638890b2ed21daefa28ca6323fc658662dabcbfaf52
+Qx = 632fdf8ebbb755c960ebf8fa5d6b679416e488faeeb021c0782352279a7ae00eed33094
+Qy = 41aa517eff6854ba04e2de6794848823e53ca580353f2b25e45fd4efd3a369cf80fbe57
+k = 2450beeca6f1ebac3e82e3aa3239a5031f54ffe65fa6a45e2bf2ccbda448a2cf6988141
+R = 28664212774e23b6513f73a9b2da97f5eeafd10efe742e314f6913a6d0c0e3e581cc6cb
+S = 025bc733edffbc1330689e7aee0dc121b64a72dff19e1d7c5990206d6daae5bae75d0b9
+
+[B-283,SHA-384]
+
+Msg = eab0a37915c6b43b0d1e3ef92e6317b3afc8b8301b22f6059da8271fc5fe0e419ca6097daba213915855631af64e10d8382d70599d903d1535e25cbf74da3a12ba2f13c33a8562e0db03edce791f1d39af8850fd1feff0eb25f9ad0a86dfab627b96e65831bffc5f6d9693d20493bc9dd6eb3e9325dea50b055768e8aa30d49c
+d = 0b9f8f3e89e9c1ef835390612bfe26d714e878c1c864f0a50190e5d2281081c5083923b
+Qx = 542ea231974c079be966cf320073b0c045a2181698ae0d36a90f206ce37fa10fb905186
+Qy = 7e6eccfe1303e218b26a9f008b8b7d0c755b3c6e0892a5f572cdc16897dcf18433f9a10
+k = 31789e96e2ae53de7a7dbc3e46e9252015306d88af6bd62508554f89bb390a78fdbaf6b
+R = 0fba3bd1953a9c4cf7ce37b0cd32c0f4da0396c9f347ee2dba18d636f5c3ab058907e3e
+S = 15d1c9f7302731f8fcdc363ed2285be492cc03dd642335139ba71fbf962991bc7e45369
+
+Msg = fdb93afd5dd1e3eaf72c7ea9a6cddb07fc2054499ffe152cb2870163eee71ace5bd420b898cb4fa80ea53fbbaece2a1eef6427b632320e9c97e38acb16b62fdbf6585b54fabf0a703307ca50f86387bed1815a05b0c8991e0743d10cdf49c8facfd7ddeb8d4a7b706b5a29e1d00ac88b0ee88b3153185495ac8388cc70104154
+d = 3a30a1c15b9ed71e102341f97c223a9b5ea3e6a335861c3cf407ef691a18cc639dbe74c
+Qx = 40937b263c87461eb5d409008255d4e14c54d7a86d6e3eaf2ad9c559f7a6b9d2582542b
+Qy = 7562e3a04f22ad37a1df0250215c163b45a6bd04a4b96c30fe2e2b7ded5486b172ef09d
+k = 13e745c76b33e6e91f47f8423653b0056014841f4df890121655ac2044f3a6d58b9e213
+R = 22467497bf1b5d29476f24aaf5f88d905be7900406c64033913fc88601c62063a924456
+S = 19cb024c7d6be51d15337a207e66fb0e473956932faf6d755393dd5a899bf63610ff887
+
+Msg = c78e35d1a5b1bbb0ec21e7ba7b7c74c859d88f3e100e40ae34128cf093885dae4e87cd09f3239dd8e79e25305220880dd352a650225d9bd193b9b84e488c458b0b5fde1af941c0c9fdf952d2fa41f665918dccae27ab7923da4710f8c27ac8ed424992568dd6f0a6c3ecead21650ed162e0292104eef3c2d8551be866a88d279
+d = 083330123cc64c11888c1fd388629d0b329a50ef31a476b909a182c930ff02d0c389b93
+Qx = 2e3a3e712676bede22893a8911ad6a683306e86487d24585bd6fe4f2657281f0bae2dc8
+Qy = 773889a95e9bd579be379fbf84dc8d26d47335253356e5b01c09eb8ed57474d6c0b0491
+k = 0d630f20623e93c274239200393cc552d03da6bb9e74f4a44a518e2642e84e761dff7a9
+R = 27b8997fb98ad04488f5dc8ae5dc88b2a3231fca76d7320550c74cc540110c0cee5d8fc
+S = 1824f1050e85d527847faff236b7195965e7b93343ebac889b23425dc27226d50a5266c
+
+Msg = e05435f695997229cce314e50065f3c5f71981988dddccaae6efb81f936b22cb48813f506d1edf5ebd69b0be34f278592c5935f0f6db0cca1ef9d62834fbf3c4c03f4da0596cb4d67b7b767e85dde7b7c6fbef7d89babe6f97b876b33594a9e36ab87079861ee556fb03274ad4af527342a4794192b8933f28c6220f954c77de
+d = 1dc2b656c207eabc9e0d6272099babca8d149c9c4258b779c2f06de75f76d77505271c0
+Qx = 2b03407b65809825a32ab50f1b556a65c3bbbd65cfcec898514637ce606182517fa1a4d
+Qy = 21c97e293ec74dee17c89b962356b7bd50c7b23fcc30ec7fdd0a629d11373e28380a8c8
+k = 2d0dc9317a2af5a7d0a23c00d126b7fae4c06bda0a5c50462ba26bddf575adb091d0e50
+R = 211c396875b5dc71ba87ff2483b0ffbff60cc3656132fda7422a81964f1bfbcb5ecca23
+S = 0a0ed7bf1ca853b9b19924c706eff373b97585b692b4b535ad71cc4362073caf8f61a3f
+
+Msg = 0f9f36477076c4b5a7d1ceb314a397fb14646695b0803e36e98908c8a978770269f165a1fed8f4b655d4efd6ad283d7f5d51b6e1e302d360e8ebf4e887c7523a757ffd55384e114bbfc6b7a0ec8511079507b919065ca018573418f9e394854c5704227772161707b4d0246ebceb91192f0eb2ea994ce61fd98a6d14cc8246c5
+d = 0081772348ff2d7a3fd57fe703555ab2e14f5d203c4cf0292f944e827e884d95f3b1d83
+Qx = 3f7174e88ffa8bc0a770fffa4bc30a436fce331dbe7154f6e2fc0cdd09e76840f089b3f
+Qy = 561e6aa3feffb2033ea716ae94b9a7402bccfed1fc4a137cb96fcdfe4685314f73a8bb5
+k = 3a8c40754ef7ddd0e289b2cdac5e06c72dc3d6ae9d0351d9295aedfd6f0e88809674bae
+R = 1443b46c0e6bce31642dcf3037e25b6ba2b42daa9a83f5c0bbfb2487ce717c37b91f46b
+S = 3f59d5a925fe19c795b4992c265a3c61b2452237eb34efb9aba30208ce07d1ad47e2279
+
+Msg = 1d38b1c342b6611dbaf412a66c1c0b8397692755f576df33b31c2bd12b7f0707cc423376391f7b00aa4e7b7fe54532e2b39c3c5284b9c8ccce48eaf9308ed338992f1d4ecde6cbe352e46339d7d602942158387881d9b493fd40cc59d4f9b53ee4191d42352c6f7bf32c331f0c5afbd44a92901a4b713c7cf6ccddf7de4cc6e4
+d = 1eb6bf2ca1b5ffe6f6a795733eaeed12de6e87c53571e702635b9dbd0d96b47df4a005b
+Qx = 0e64dbc1a08acf6ff0e820593cad79a46e3bd818ddef5ca0960fde799abacc7b840eddb
+Qy = 6115d3de2bdd011ad053550471368581a5f125eb0d32090646fe4407980a42988e551aa
+k = 3b28fc6d0e4a7fc449b811b78900fb9f89885f4d4f70cb5a2b3d4f8ab87bd5448f4bfd2
+R = 2601923909c8c953087b0c0acda57d8c01f814dc9722171d8409d0acd2fa4d9c1314693
+S = 3eb316cacba93bd473a4b4acae4f2b5a5b2ac9856519032e63a0c718698956e8f35673b
+
+Msg = 3353ad05ef90e9762bcfedd6ef44a1e8ea0392ebef30cffd48ae620f3e567e1cd44882d514e7c6759200d4bcab18afd3038c3d3f8c50f7bba32a04eee5a4b1cfb8c349939e4efe0a46fd047d02ed000d8fa1b98b0af5586f120d9ad174b3aea33905b979ece1eb3660b1e070c8821b32df41904ad68bbd8ed247aabd94066f16
+d = 3b2a3e65e5a306bf8e3955b60e856dfa9bf68c1275a678ca056207a0ec67c96eb3f8309
+Qx = 2c542cef892b06372af7d9c321ed5309995c1cbbf1a466e70bd30f3856ab7c5d18f4e3d
+Qy = 2a8acdc12a7cc0b54f4dec9cf61c484a5cf86c4cf6cb5ed615479123ef1c6ecbb6c7ae4
+k = 09bb5e49188621466440a0841b007525000c2203d9821f4c6afab63ac2b97cb5e2e3dcf
+R = 00a09da1c4bedff47945898f4f4ee9a0857bb56be535544aff9d729ae44e23d678fc71f
+S = 2390be08ba0861b32ca35ba27a0c8dd1a4e96d28cb007133a096b52afa0126bf2a2abee
+
+Msg = e7ec162185fe9a5803c6b03d98041422315ccdac67e48fbd07a1ef3c5661158710abc6791bd0a75d56791b4ac0e7695d53c5989d9fa6a3b037583b2a80d2b154b024f1c36b63548be9afe1d51f2f68b2ba94d4ca1e69a35ac10e15ba72242aac20f7526b12ff9d3cde9a9bfd70d55adf9bd92c66d092d7d08e9764c84bf7f329
+d = 1fd4d1af0bb7c79ed5fea7bb45574e46534387bd916649485ef15207352d7302e81dc01
+Qx = 77057d3f93011440a78718a3cfded73e4196e7fde96e794465c51be8b679f912c10edcf
+Qy = 59873441c590c43e0f00f80afad5b0166f94b62214ea45da29174874e44356b29eda6b9
+k = 3f224b35737e78ec5bc9b081a601d8fe19e33b4787449d3353d2ad225358211cf9f7f0c
+R = 1a7bfe92c30ed1af478282786bdf7b5b89cd0fdba5e534bdf13899dab5af108803d73f6
+S = 2ba14810de4f5cf48b56e94bd6c439d230dfced3cb698c77627f59faff0ac5a42c43067
+
+Msg = 87c8f2e3f4fdebce0ca9300fc1ebcaa934f51a12b6b8f2cb6bb6eb77965468663044afeb2a1334cb5a81e74b8427267f8b34b5e9ff0cf157a9f18be2b1942e32ca61dc23ea13c3f9fcfa16df8fe05e067938b6994982676463fb12842d4ec532cb904cf222aa805dd0d86ab9a33a83e294c6d81e8dfa273835e62e9041dc8ff6
+d = 20380b1136b5283e9b7f54b7535ebda33b129ceb177bf5d3d07b1daed5edd9fb3862530
+Qx = 5e7d0931db006c6abe04671d1aede760f2b1ac5c866570f8e5a24ed356fdab49cc5cdea
+Qy = 7004920fdb0a744cc545068bf82bc5d7a46edf9265fd7c5979b9559f5421c9a98f6db89
+k = 3cfbb1204caf6011fceb8d4be987d9a41b81bcdd95b94919b220647d0e7a18feef4cd01
+R = 07096beda28c20d2e62d9b0750142d3d21b54c38c7fad1ed65e4f9b386f3dcfcc43a3c2
+S = 3d0af02aa39e329e4c39f2a1d6797f0e3d14554dedbcab9abbd158273a3c7116225abab
+
+Msg = 2ac53e8a50c4afe3b38904255b7cbf150c5f79dc15932dc0ac9aa631521f68a0d4b6bc5a04d55c99a36531fd4886a23a8d99f262ecd2a9feea925d7a96ebe9b6979a207b7f9378afbe404fc8e959b0333572a2c911f8743c0ba64eebc7ef12fe5435d2cb0e5091ae518b6e4233489efe3c16c6f21abf4e2c6808b733914e5a7d
+d = 19f815b98836948e0a0dc9c30828c31b13e175f1e79f23d084ae1bbe64823f4866214b5
+Qx = 5109d8ce934972f5520101730d0a14b99213ea17772e3e7637d622a5de13fd2ffe3bffa
+Qy = 502927e0c7baedc4bb3ed2bd1b15fd2d06dd43424393b246dd530d5d8598b56dfcb3cb7
+k = 10359d5cd8a9b7532c9902bbf1cb83d0d34bf37e73e7c0f5729b62a10bd4d8faa0f53a3
+R = 3503410a6feec71fde2feb14375d50f99ff9a2c8bef47e676bcc6c3045efa9948891ab4
+S = 159b1f65fd566ecfdc08b87e4ecf99ceea3088a750e2c3c9d868bb432de6a61f289d06f
+
+Msg = 0b201469cac4c078f587edecdcdb6efd5752cb4a3f43ab540463c4d908c27527aa3592f2f9acad85dd94a3c056bd28618317ebdf2e7dd6c5ad26fa3c31dd8e5c50c60418d91c93bcbb59ec1adb1db791f485ded78a5cdcddd23dd1cfa4f13443468d8a5f2d648059b9c4470d0f4fe7733d56a28a2c24456b6923703ef32cf0b8
+d = 01854e954654e726cf4bebc0e5a840e8809fd716059211c6ffeaed36829808363164684
+Qx = 7a6e7c542860e815d3fa24fbaf99989e8b9c812b08399056ae4f9a850a6711a7385b622
+Qy = 0dde6bff33891a64744dce6456600f5a6a11049906608e77f8afc38b922972c805af258
+k = 2c9cfd376903122625c7fdca50e93d4c216f0c7d07f33b3b51e54e666e13b67dc89d290
+R = 18321f9ee35d47648060213df1275ae89c2ec7d17abe8093d8a431ced23aa61d3f8df4f
+S = 09e5a05a62b006a7787c97be38df6fb9fbc1433aa2241b5a788fa727229a18e07d7a8aa
+
+Msg = fc5e4dddf4c4a328b685035ee79069770fbebcc56c14e31afb4bbcdd5220e025f31eba794fd6c05e64f19678dab33ce4f084bc32790392f14bf35669d75b6466b4214ec30d58ca90ae285c9058f5804a1fc9d7a995958f2a0e84ee52e8a78b601bec04ab607ffc2091749cc548c6754ed14e2e5f92315bdacaa7a12823ef76bf
+d = 3548f8020819588b3202f4c1ac62eaec6a47c2a19b2900c5a3cf5b4ba5804231141c647
+Qx = 38563f2482a399bf1c13f42f8b85ef64a3599c22da9688b97530718bfefdabca3ae8637
+Qy = 5c4aabf6d8a90af345008d5a244d0671cbe1afd08000c4eb37702a9bcba6dbc058ba6da
+k = 32649876d776117003305f0ec9cdab5cd84bbdc747d3dad5d8d54a8fdc84d519d50df45
+R = 1f5160851981772c502088eef209f7f89a7c8ab35e630d16330bec7723e398fb37c84b1
+S = 073a7333a7037e1257d4d70be87c30bef770f9d728dd7e2615d47b399ec650aedc867c4
+
+Msg = 284cad790e6207e451a6a469cee3befc3ec43e047cf91b9dff1485718aa29de36a43f7c51eacd8589f0c3a96ec18e8ccfa92941b50b2132e3612d5b45e16f60d411d1c53e373e1ba451352e28970ada9dcb9802102518a385dc571dcf6900971b00346098a58042e0d1d129bd6801fa640a895a458a45b31318fe63ebb30c6e3
+d = 3cc4505005c41142308f1489226b7b542e2e7f24f1d3089ff6b92a4b0013f490ad52e60
+Qx = 280b77ddc6648d9cc3f5557d406ea2a089c8179d4320781b2eb76ab07fcafd2535b91de
+Qy = 05f23bf4171aabbf0fd50049aa017c0dae70b065964c685bc03b958cee2fc3249149d31
+k = 2ef488215648524f6caf85233736eddcd9d1d838c6a2799c3a68580492d40f9800bd119
+R = 3e8e13db22c97281307edd4037f0a75d2c70a070614e94e02c860f36a53aa738fa0db2f
+S = 356f2651b51a6be0c697300a8c2641bfaa1795397eac208385c3729248e36baefc173ae
+
+Msg = 6d46e57abea9d115deda48b69fe8e0b36144df2f6a659509ce1b514c8cc4769d46e5f71df2a084f1db4a22fdd3ef0c2f90394f2898ce291b9f279c0664aa01419f5f6bee1fc1299871b27ecd57a5ac548f99d01871b8c238a6b46044c953b2e78e22346a0c7663af4db62799038ffb5c21ee512e26d01e70a4ed967377ab8405
+d = 144a2fc8e0aa63506e14e4307df36416f963dd9da78655832f5b991af8c3eb97df78efc
+Qx = 3fe8867b560bfb21dda517b8f4d50578a11e1d0ab7ed4ab3796580d31bdf710e8e22284
+Qy = 5a302baa3795e2d132c55d90858d14d4b17aea0ab70632b135f94bb23112d163357f8ca
+k = 0b5225132f19419715170f5a3f26919b4127a05b4f0406f895af1e4bba95786daf95259
+R = 0651d17b00ed9a06bfc6a913883b5cdf51bd5f2dd22307cc5ad3bb545f623516232bb6e
+S = 01128d4784fc0fc050af0b97f859616d764b22f40734ba65aa15e2cf80e7bba3d15f42f
+
+Msg = dd750b39bd8753f4e473c4484e2b36ce2da7576813ebe05861c339ffae1d029bc793173ed394091c00685ad82f0550cb21ed1c68f0c27cb7396922239cfb886647af204e88a9101b7453a8ab662e270b87a8a13f2fe61d695597382cabeb781933bebfd7d0dcd33f77266e43e32d937f2dc89f67525e522977ce73e9ad36c8e1
+d = 24ffeaf139043ff25a395e4c560c7680c1c2155191378917eb25194136b4a69597dc277
+Qx = 0402bf61c0e36385e5fa8371a553ed8652466fdc3ed9d4a3ce1bcc567d1f451f6703dd1
+Qy = 4dbea6f67e1117116f30fe42e84383768b0da770f8a2b4cd8a4fec330a0034554a13808
+k = 3e4e78f012eaf1778c086a3bbd9e996da0ddde651236ebdb6348062f56b36f63a901561
+R = 1e2312720f6fbf44d7a6449a7f30019c38e69f2e6424d4bd1054f40798e9fe58d080b86
+S = 379d1b610a976730dfdf3300280f1c61109ad13c788e8f8f9a8d5e0130ca9482ee417da
+
+[B-283,SHA-512]
+
+Msg = 4736e59fe5812f63737eed57a570182c065538abd9fb0a1c9c2059199e7052ba57d84b5fa1cda2ad9f216610361ce1dfb9334816b6bea509283756a03aaae2e5b0597f492d078b6b015a40c9785dcc5d2ae266176980db04f5cffef40e16661a50ef871c5f531d73fd5d114fa19bae9dd2da4267a131fc31849da38c2b78d1af
+d = 1d1f2e0f044a416e1087d645f60c53cb67be2efe7944b29ac832142f13d39b08ac52931
+Qx = 10b2d7b00182ee9666a6a2bf039c4358683f234ae41a9e5485fd6594e3daa880c0dfe0f
+Qy = 0a419b2f40e573dc2dae4b22e6f56e842e50d631b6126153178585bd05a8b9e6e87e4c8
+k = 3e4d36b479773e7a01e57c88306404a46b6e62bf494b0966b4ed57e8a16169b9a1bbfe3
+R = 30513169c8874141cdf05a51f20273ac6b55fe12fa345609a2fede6acbeb110f98471af
+S = 33fd50b214f402deed1e20bd22eba71b156305e4f5a41ab9374b481ee344ab3f27f4bcd
+
+Msg = e573fa7d4bf5a5601e320130de91f4ad87eb7ca6b8998488afcef69c215b0cccd221b8b66eb0af9d699af9ad6c4b4a580e82941f31e4c0a9bd83995dd076c5ac9bebb34481061e7cb1b26f6e8c6b26ee4bdf9887f7ae2eb9fad3115a21dcc96acce85d23a040c0ebbe0a56e75714dbfa803d6e279b2f4280bcb993f96ba321e1
+d = 1337362609df74d25f7adee382225e6a04dd6ee4c6b45fa31499ce9edb0ec046325caf9
+Qx = 287b288ce6f65fed9f95c99fa4b8c1aaf6de65ca563df30ac67c1066d2ba2f5a554e09c
+Qy = 25567fe183dd400d256c333da92dda2e364afe84492ede9fa0e913ca7f12069b5a44b48
+k = 31b84ec438302155f2e84dd118c0d8479267f8d19c8c5d96d21177e20b23e0180dd6d33
+R = 08133e49644044bf9ba3b4c8bdc3973647d650c58fae4a7ea5a5fffabafed56e759010a
+S = 1d8cc410cd04b188418b20cebc8f66ab0dc29a42f9067aa2926dbadee39abce79deb396
+
+Msg = 7862864d0d78b44e2a28af44a0a16d8e9b1b8c4b794db0410c0a863ba011018ef43e1e11f2fcda2f56fdb2a69cc817df425c9cb3b458922ba00d710190cae16d61af3c304a42fbb3d0c4a74a297253fccd70aca414865b41f68b01c561be281265fa89f63f975d3101334886e85929a5a47fa8dc459b663548faf8ed7484958d
+d = 1be00aa0afdfe92e24a2536594d4b41701ad4dfb223aab35ff49310bdba7566057fe8ac
+Qx = 13583d8cd163fdef7c11e91f36c1d3eb2f7957d219244db883708a7c5777611b0066812
+Qy = 7a1f4df45073b838277d8da7daa7147b0f10aa98b5ec02fbbf97c89ee17f3a7ab4f3f27
+k = 26b42f369ff9b2740147914a2698cf1ec9bab44caa3b5f05957ceb9a32073729aef0fc3
+R = 37640dcfa11483b3754ea027f5f239500894dda4f4c8308f0623db256eba2113c41ae61
+S = 2096767a1f8210b175334fad61b4c7fb4e2d6c7811b5d22521af7750f101077e2fd4e44
+
+Msg = e73c96d1a84cf7cc96065b3c6a45db9531cd86a397e434072a38d5eeb9a90f62bf5d20bae22b926cfe967647d2bbb5dd1f59d6d58183f2cf8d06f4ac002ead026409ca6a1f868b406c84ff8887d737f65f9664f94801b2cd1f11aec336c0dbd4ec236d1cc4fc257489dc9709dfa64eae3653ac66ab32344936c03eeb06d5852d
+d = 12ad0aa248db4fbc649f503e93f86104cb705d88c58e01d3ae0099590a69aa006aa7efb
+Qx = 08d262f57f9528d55cc03c10bd63ded536bee9ecc617221d9892ae1a75b7cdee175cb33
+Qy = 754e40e8823e89fe23dd2748fb74e9e93c3b33f188f80377a32bc66f6a92da1804c04cd
+k = 2405a351a3bf9a6dd548e8477452c4d9d719e32762754cd807a90abddd3ad380e197137
+R = 28c5d807ea1c3ddb7f2c90f3af644c5d6a2757336ae46c2c148752a2fc150e8183cfd83
+S = 397c8c52fd67b99792229194a787518db5be8e8c291b1a30e105b00f108ce41f8ec8fa9
+
+Msg = a73fb0aaec838d011110d49c5e94395ce07408917bacf7689d2cfe0948c582214b263c6b80e0a55f1e159086817605723740569eeaa1bae96b979679165c5c35ef2142525e943e595e6b4b160acd7ebe41de19775346363f779b1f80b6d5f0785b92a648028e456af8496102d19dc6526247a654bdae3368f075fa9ee92b2f4a
+d = 2cfbb8f340cae8e2e2322829148981cd9e509b0c65497fd8d9da5dee9dcfd39b0f7556c
+Qx = 260bb17da74429f049f3a7eb73fea9cbeb5b14ce553d7772a365376d0114ed2ef3087d0
+Qy = 5889e41bca54c09be20dd406a6e1f11f9d31d720e0c4e2e88f381ba89a97f12fa9faff0
+k = 3fd7cb455cd97f7f9cb888444f39569114589612b108657ac59178ffe31a33569c9f0bb
+R = 048a10915fd3bf9ffab1cb13632359466ccc539128cd98c6273d5d8d26c64d57520394a
+S = 2d0f67f9baffbb34094c5fce36f47cb73a537ff984c89e38d073678c21148056bdd6893
+
+Msg = eda775984c7c9f7db47af30dab314d070fb77e9b623baa6b73e2cbda800f167b20fdc2e7219391efacf908f4ceed9b9b6bd3541b52ea087177e18c97391214758cf6455311fad336ab56cfdce57a18add8cf85b0a0bd6fa7297dbaa34bfc8585b0f06a0aae055186658c227e19cddb65de88d260f09f805c2e8854dcc524189d
+d = 070e82a1f3fa6158d15b7346dd56150faee5c98c9d07c996e01a06dc9b211b12ff62d60
+Qx = 3d3ca5fe316a0820e84a8bb5d231bb14c810a87c7392d7f960e7cecacc56c337f88b0ea
+Qy = 27ac0ded5633a98ec5734db9de1399c83a181d522037266d856c83e5c8047c4eff2c4e3
+k = 311b23487750c3c4b23b28424c33328c39d6f594d2a9b459a883508b985d8aca039a2b5
+R = 1465736c3c9e30e895b1544690e05108ca221cf2352ee4af1b5ee4130029a82b277b076
+S = 2819b94dca3a58cc5a96790871640fe0fae38883de6fb4712126c1c1cbfcb0c005c5af0
+
+Msg = a4a13e0bfa761b9bf37fade6570d41c161e20558874911ff3bee38e5649849b159beccf321c6bc7243f99c01a2fadbab9e157e9952ca65d8ea676c74fdc976d00501c626b8465c6cf0e4fd1a7d1260aea987161b821528b0b423e62ecc5193a0a49442b0c3e4ec9c4786a3a86b199c07dd3a17033d430d2c83c100f54e0a7c31
+d = 0b471bbc5f7a07996e370da4a09e71e2119ab3a562a273f079401951fbe4df39a4493da
+Qx = 333e9d5e077bc64d022e49d5d207385a19282aff1b73b307523b0f861b4ce4219308c82
+Qy = 5414e431f3b90a2d4a454d073cdd81f8b224180ac4139104166ec33ab33d079dd147ebf
+k = 3e431c39ef6f4b7674a1bf414460b58998ed7aa5b1af7ddab746cbcd2ed9f42ae3827d8
+R = 151df78c0f453d396d71528032933566e176eb7f6910fa9df2e9b2f5ebb6038777ef209
+S = 08a1c4a1e21cc63fc15a78f0a11a1bc7a59a5a31f57091a12896fa670dfdc05c04053b7
+
+Msg = 7ceda7a7248640f7055309ae712c19d741375d6a7e0608e07f0135bb830dc3e8863ee9e7a75331a5e1bd38c42cdd484d4f45a26c2c1d4e05ce0d0ca941f4e94ecc6b371102f31633629e9861de558bcb6407d66eb91f1062ac0e0409db68b9f2855296a7f42fc92359a7dae16c73fd2dddea52bd866a4d501aedd8fe3b3ea733
+d = 3c65cf80bfb507dff52f9bf2f93df0642020d41619b3990009409e7210fd7130ac44ffe
+Qx = 3beb5b9b8785c5601093086b709c0a05955be42eca3d217e625349e5a875efa82d75ed4
+Qy = 07cd4e64475d628e6f562f0ac9c3f91075626063a52c2b621796e557799ab2f1ebf8dbb
+k = 16212ce91eed7153fef806d2561912be1d988410641d5eb72d586cd4e6782deae4538a0
+R = 26ea04dded2cbeca81e75503932982c7fb5cc7d38a45a3fff8c4ed7f844dc759d8da302
+S = 061d3756e3da1c7816f0d72a8c84dd1f3b93624b631f5051c801af4e472fcf82d896c18
+
+Msg = 609815edfd58c0e26a4b06dded831d2f33466a130754b96d8d7c3b4d99fd4b0789ec719bc25338d0ae8c5880560c02687d352d77c291e406eae865c3b26d00f2e63dc644ce7e01d6e96ceeac8bc1eeb257d36cbb25d89b5fff6e30b6051506a0ae54cfaf6214f30985d54cab78f708029c1fc0175bc58e888db89dea8d300abc
+d = 0f4d33a9c7e6744ab3c441828bf0f1866ae1c042cc54abc754e3801263a96cbb3955dfc
+Qx = 4b925b97bbe67adbb6e918acbcae0ced8dcf11d012e1a97875b750bbb7d01945bd64df3
+Qy = 4591cc9caabc0db8fe9047e6b1f8d850ac4389fe67bb84f6846b631dc3524c8dbe6a06d
+k = 0483aefcad5e382351125b333dcede8ef50914b1d1f1843b075f242acba18c290c742cb
+R = 1fb791c288e2cd52d3837c56b02fc99f53a6ee27ad6dd9c0a31ca08d8fa64eefccc5c87
+S = 0a041ca35422d8985c1c706dcb0b8ece64b65285bd0a934cdb41fc08223885147281869
+
+Msg = 82d8ebba707b72655497320200ce719520c1ae7f46f38122958fd99322c25c9f4d4344bcb77a6658df0eece5df163412ecdca58475d56b0c2d14a0361e4cef458df146925d473a43692b15e9bbec550f1bde3444f2a5b2ecb55d2abd273ae999f16a32333529d94455e485ca4585e6b07bedbfc2bd1eb766abf0d28bdb1ae6ec
+d = 3a4824bdcea6a144d85f1b194431724cc49849b6cb949b4766d641ae95477d1ec3d1464
+Qx = 2c9eb36eca01dc2fe921933f4cebe8046b3679abed80d2f8fbcf8f254bf17be3d551a56
+Qy = 34c836aa4e946425fc9f49f3f62e33d8a0afd320292a34d0ef8bde8ad79a10e3f95f2f1
+k = 23d8725af57d835018e8737fb4e8b2eed3ec5a83fda137c710fc1df875416ff82fba90a
+R = 0d9f57ba8b6a9a1cbba67adfbb938211ed2d267468f79ad39ea1eca7271d135bb67c18c
+S = 0f09a600d97c69ab521bd1ed6bcf0c0f69255c334e0aea06c68bba81d53e810cc553c9d
+
+Msg = 9c6fce18a6a96349b10c9f2f5f1505c8ab727a650b44bc0782a5f39fcb48b45fc7c1b82180d5f229b8abfc807071f931d333d265fc940c93fae7520d8d40ef59d7c6e3678c6a2ecde52b6a8827b1ffc6ed269cb9832feb20e593a7e3d4708309342875199eb2ffceba7ecd707b122516c815e83e27872eda812e3ea52ee3c4a8
+d = 27ba543ea785df1d53d4ae4c1bd0a3a994cddf0c25d2b4e8ff17ea7aa00619e858da1a5
+Qx = 7d375a9e78ccee85fd795e3fe6bc07f50af3456edda1ab00303f6de6b5b02fe09859c63
+Qy = 08d0d54ab9a239b5ff955452b32bfd2372fe095751bea4b56d52f79b4fda0fa635f57f9
+k = 00ee7010af4a517502cc5d5433d98916f6750e8a9009ea04b8132268673d4a02a3e2031
+R = 3c147b66efa47a842eb90371eeae907f0c813ca0937e488da95ff8ee16d389f3ab902ff
+S = 01469d005eacd9ac84a140c93ed0aee09083a4822730a28df35058cad29267eacf03968
+
+Msg = 5eac15a64c7653d125605869012b8f036804817aedacbb5a5248a595ee0c12329f91e8179c187192d3ed0d4ca2e202d8d4d9c93ad3f3ed931121c193af5b47a8a5dc39775b6c2d702708e5134f77a31bd62eaf87e39e6fd3f2b9f782c3057e162dd53b3addf92bf0ab99835c7f6649abd1c5322a1ebb2ba313df9464a74c14d3
+d = 0708d0907d14dcd5f40e2903e1e90e48a0ffaa6d4d9b84ca14df4e985c294f74eb9f2d2
+Qx = 6fb0fe1c3d5bfee5399c98518bc3ff135e0c351243fa0540717a9b1f7990eb8cf43597f
+Qy = 5212fd4d6a50c08cd99ee5988103fa639b1123c878d416cc553639bdcee1f8e927bdc8f
+k = 151465f40204d76f3bfc2e4052549869c19da82c678c332f536ef24567ea034358866c8
+R = 0803d3e8c876d46a9198f2f769faa76c4f66bc5ff4298b9640ccb8e67ff8d10f86342c4
+S = 00da3344354114d163d14d4c288785adbf9a8b31371c6e4420383c80ba0a430019c6acf
+
+Msg = df735a7e60bc267b18f313ad56bff830be5ef119baf43ce27c6368ff1dd89f010afd4f48740b11c12101c5903bfa71d6cb3d6462cf875bbd55a570ffedf3564088dfe8c8d3148231b78b5adaa6c53696737d4704daa59eab8d986fc6e519e81540f201e77b923a6a4af65d7173635b3b19b2023022186a7b8e869e1ed51717ab
+d = 21fb0a6b94080da8b8299b87457dc09d21bc430ba5f3359d92aacc1151be9941739567e
+Qx = 179831c55ead3d11844fea2e18d25cd4d658822e626550aef1afe37d88aadbcc9bfd666
+Qy = 75f8087d759ede340157667c1bb12be272b8318aedf2e8f8b487f4bcd12a50ca66f9281
+k = 37833e9aab843a6b967264fdb705b419ed63fbb09c12170491019acc7c21b9ee28a00ba
+R = 1c9601440d109a3f4eb69a1a669bdaab9f4222a34a04ace8ae313b10bbb66811bea7d5b
+S = 3d2f9ad7595dcff69b65f035ce600f2667f8499d3bd25f789d3f3c1bf83d2855f68eafc
+
+Msg = bb107b0eeaf175a786a61db923bc6d51dad5e922e85e57536118e032167b197b1a1f62d9bbcde04922fde781665c1094181c16ac914cf6fbbfb27bb8346b2134f05c55a8c6b9b481273758e380666d6e22c28577c29446cecc5c3df9ed9f1be060ca55ab2b7fda36a147aeb46df0275bb923e0876b703452fab42f6b7ad2ceb0
+d = 2c80151f91301fb6b0c7685bd172f20515b46bf94dbc4160d0720fbaedd40ec00084447
+Qx = 4a62b0c9749ae9ff00dc1d50d2b4a4941741abfdf13c8e416549ea27fc26b14f191f243
+Qy = 2c9cdab7c6512c322bd200167eb9657f8e8c84864b57480a80a3c6efbaa289ab8cbe4d8
+k = 3df951f8c4490fc7c2d50a72a93e0e82c5a20be8d91afd890d6846bfd146169ab58b382
+R = 1f2accc7f7c4b5f877e12cc17b227e1ba110577c9f4e1785e6dacd8491bc6017129d798
+S = 27a167e6f2b43ce9663b810ed4f8ef15029fb6f2be2ddf25c014d844953f501d1dcf6d6
+
+Msg = f47e49ae30b09b7666600b7a95e81b0afa1553da5e01fd917e4ce1b58dfaddb8dc8c03c0f5591f533610deb6a7bb5faf5dd1ec4103a587a1a4c58a110a706b0f301a5c408b3d984c210d5b4a0b347d2b5447271f25b527b3c7864f7cdfa735dfded47c63b723fa0f0413c57a24ffde9a95c35f743f892ab1ed1df704cde82d9c
+d = 1538abd7ce8a6028d01604b1b87db3aaf720e04220edf4d1d28c2d731aa25f509e58f2f
+Qx = 3076b5c3a12b8a2e1368c7e3458458dd7ba6c5a6dda8c82cc6b30d1ef767d36e015207f
+Qy = 369c7a80cf01e9f32c08f9924db08a7d0dfa5e9a8e0e29b57f5eea8506841e6e3da04f0
+k = 3f0052ba6ae6bd7a7aeb077a764d21caced6b241f63616ae4e4f0d98d2bfc0e44dca592
+R = 01281bc0bd36ba1f3e1c262d98ddf4e9bf1d80dbf97db02089fdf1d2e625abb5733ec3d
+S = 076db2215d9f33054efb397c449f05db198d38a24749f046ee20032f5899dc142052e37
+
+
+
+[B-409,SHA-224]
+
+Msg = f2380acb0d869d1cf2e25a6bd46ebe49d1c9270624c5507be4299fe773749596d07d10f7c2be1c0b27e86f27b4a6f8dff68cfe5c0b4c58dad1b4ebec7bd00ab195fdd635d9fa8a15acf81816868d737b8922379648ed70022b98c388ede5355e4d50e6bc9ec57737d8843fabda78054e92777c4b90466a5af35dd79e5d7a81ce
+d = 0beb0df3b0e05a4b5cf67abef2b1827f5f3ada4a0e6c3f23d698f15a3176cb40e85bf741c9fbc78c9e207fa7302657527fd92fb
+Qx = 1da1761981a65cb5c77ec50ebf7acc11eaf44bdd2f70242340ec26ffada7a4b5f661e13d6e7ad341cd7dd1ca491cb7a0b580be3
+Qy = 19ba11e4c4f2f5507d6bd2aa2f96b03510a03d5f8c38bcc8acd08080d9effd1f8ae5a5586603b2e112964514c831bf786b2fcb2
+k = 091e575fc79444fd2d9021bc267a1a076438d73464726bd0fe4ac2884a374e71bd462b1516b3e97c3202854bd0a286214b9e92c
+R = 057ab9d5cf4d18f05eaf17d3b5a4af96c3eda8ee48acf5e02eefdfe2f542cde32a37c04f285794ddccbb14383a645db040bda81
+S = 05275de4157b32723366a0d63831e6512241e3e4416f3af02e22da8faeabbddd761160304927a71cfff4d6e8937347c9b78cd3b
+
+Msg = 22a97fc0a9694dabc6f274ab52eb592dbbe8beeb646ebe6cef60eff341a13017eef980aba6d24ab3afd976e2f6a84cf652654d4a54a36b2f2f62fab8858f8b0479a48fe9f47f8fd5a4a1f3141a91cbca186507b2bbfef5e4c4d2df525f04ef7c4720fb443ccad540f03a2be468d88c9545d1dad579fd7cbcd103bbebc9e9f961
+d = 0504865a30984a9b273d1bc289d734d10e0aa56e93ab14720f1a42a27d8cc932cb8804b963175de6fe57d8eafa8ab7ea0592dfa
+Qx = 02de5872c40a79d5238722fcb94d5158009e28fb41ea012e92028dc3c87855fba71f50e6d0dff709867de185f9a9671e7a91e2f
+Qy = 0fbf607f69609ae96982bda3f0317fe46ad1e0207030fdca702cd97fb5d5732f3abab24b10669875a64bd2a74c8603897c78d22
+k = 032d0f950d10d028db6e9115e9944e7c768e2da731df49dc9128bf145a747662de08cbe0517fca6fa185abdfcc4e3ab604e196f
+R = 0e7d16daa689ddeb08074285f5293bd9f1c051ca5589e69e4b62c32af110b6f3981d9624df15c7cac0ddd62aee9c41c7b6d690b
+S = 02f6bdcc551aef0e4e8da2df38288dcc29fe600de2f8b6cd8149f88146150790915148f069372151c3bdc4d719526eff252e610
+
+Msg = af36c04af0e3fd64bf52dedf52fb788d2d1bd67fe05d98880cc7ad3c20436abf02f637fcec209fbf888903fdec8682717299f8a4386768153b7faeb6581db57fb9aaf4615b4ea8d924198fdd158363a1f40312527d6bd14c13d19985b668c6b88a7548104b1ff057d07082eea421f50062a315bc3866378f2d2d634f03fbc0cf
+d = 0cc08a4ea5ebe32027885a8c212870e7c45b6c610117994d6a42a284c05199414a3a0e8e6645ac5c2ebf21c505a601f69c62b85
+Qx = 09d2beb607f2bab64451327e1dc67f04f7569ffc0c67b410c6db06dc04edddb1362ce8d8b8220be77c447640e7d0c676e5ad1d5
+Qy = 0ab813e800e75b6012faea43be56fe9d5a22cd46fb1f4f1ba65eab19f75f2ce9d8187e4940fddc485c42cd18d40d47415a80b02
+k = 0cfcc307f847eb696f16af32502690711ffbaa2e60e75f80cbcf7704152d5eeb9ddeb701952dd58fefb159926a83245fefa6196
+R = 068d1c646dca56393caf3239d9fb30d1dc56f991a8dfdbc0a7b69d273aec69a53056d9553e105c7917e522ffe446cbea23227c8
+S = 01db30aceed2b126cf45163b9d878a6590e9ac8284a31ccb0faeba2202679f181eaebb664b5537f408b693800f24da590082dfe
+
+Msg = 6bd6f52a6204b60f37929aeff28c87ef61ddeecc231e52a7772275f9329add899c130956f8c50ac2698aad3654fdb49b74a6427a62a11eca0a8ee8b719b8c0df7b9f0bb0af5fef4918a8c83367d29fddd04b6a1ecad904471e5b59c8fe3cdb06b4f8f96419518dda960845d83c49a49f1b1f2fd1d2682a9d60c25fe3ce982cf7
+d = 07156ef0a74ee1119532a2a7e8c02be1559c3c21897af9d5b34553c3d0feca4a8d5929d1945df824478e0c0b92a6fac8c84f639
+Qx = 01df419310cf133408e9bdb32fd85f8f0950263e1886f2e2e108a596e7e76153ec47bf9b33f69c1128dfbf52557f3c382de85f1
+Qy = 16a15517a811c77cc67ec4fe2bcba1290e4981880c071318aee28e30854692ed2d6bfb71e6e74fa97af750889ae8d010189733c
+k = 063f127c38160e85acdd4d5dee1db1c32cd9da6075b2d2f46b010636e374e0262a0453394aaa8bbb5fe7b2dbcbcd62ad601cf51
+R = 0250cf50d52a5950999b9c0ddef219218f76dd9f22a2213def9ba98d258c2f8359d08d0efc208e23ea3614c9e27b2e4576b9c12
+S = 063479550873dea8a3ec0306ffa9252739c34c87bbac56d3d9138764347d5220bea9c27d6a308dc2ec53724d6d3ac4862d1735a
+
+Msg = 0eb8de25f63abc9cba16823270e9b6f3fdedf0fb90f6652a34688970932e3ae98f6d3bf0fefc5f247f72960a6975bff1f1acc2188a1775fe8974b2bb2b4c8d226ceb735113a14009e8ce66d58808fada4e6f697fd016829913352c0f659b6be354a067df00cf74919580750aa6064f21264d89dcb28b3b2d4d699115c36d1310
+d = 0a95c7abffa92e2c637611ccba66ff9d2ab121b40a85c5b71454cb0dca1f098ce1be8d9ea4933d1a91bcd270c5a33687835d6e4
+Qx = 048e6b8614c0c7156dc41884e17e36ef528a493c28c9e6275c3454d83beb939ccc74952732c18424ba21b8ea9c528966c692141
+Qy = 00ef9efe1145029d8d60d14dcf079d43e3cea0e18010f680bddc2729ffbff9a981cef2cb595a69142b25a0a39863a929adb635a
+k = 0f43af45b0dd631bfe38d85979ff1612140b9cf80b4504857df17279d9d8ea12d5bcd2920fcec81326f15832df6774b9c4bf5b9
+R = 099f403ced566fde4d9755258445b6d6c2a4e234f99425aaa78ef118321f8579fb513ccbb71cc2732e31668a6a6bb0fdc7f4018
+S = 0d8568971a4f219d6d3d8bea6aecb4bf7de53886d2e6bbb0f71d054c63768c34d4d1883000019c59168fbb32f4317330084f979
+
+Msg = cad58ca7a3b9967dc0ab62a43037764f8074ef9177d60bd98f623d693333971c24a575ed03cb61f4dc2e3d6285fb1204502a540f3c0bbbf23f5bbbd1544f322ce35d949d8b1d8edeb82e90927ac67ad49c91007056bf5096bd690d15ac00e1874fe33293d8003a4a2b094078cf09af799dde384143350c54a99e1f99cc31f2d1
+d = 02c438b07c6e0685d1f94a4bbafc013f8f21265d893f54e54c3ac2071606ad1ffacace0b8367aad724b1d9508c65ce52282e397
+Qx = 1fca66bdddefcc3c2072ea32f026c975a2c392dd7ed7e93e94a810e1125ec161bed698d8305830eb66fca5eeb71934ab3fd79b1
+Qy = 189c22a2c9f1fd7624f805fdf4faeeb931709d745a3feaa3cf04824f5fa58bbda144d4e96d83ce1e3282bd5fc9c50bcd68f5408
+k = 09230aa7b58505e2dc2f205b70a09cb9f4d8272f465b7380195ede0f7770af2a33f7623c310a0520e7436835cfcaf32467f154e
+R = 013d0e70d8f4b1563efbd3c46feee15b88358562f769046f39df6d00477815e6b8763c023807eda87a86338c7b64214784fa2cb
+S = 0662f43fabd03a0c05ebba700203fa2188e16504f8655bfd0fd090b109e68220122dff7a6cbb8bae08612e0d516e9f95ac15368
+
+Msg = 281ce2643799bbfacc7d5993683a4fa656040517854f3c2dc7c4f8848dc305382e34e894d433caf12d8b493020a6a08d1fa05b08bf6c53127ad5f33bbe75b9db0615e3dd94408d028dcf3cb7598f6e7cb4c787681dabac7cba2cc06fccb7506fece6c7c1c1bf622d525ae9737085ab4ac578905950002024f30159cf0d99f50c
+d = 09e8658f8f9e6cd98c0f4f0fd20d64d725653aeba339504def17f3ad12a63dc6157d80804e5f43f4ff48fc5573fde2c615ed31b
+Qx = 15088531d914113a25f1598ba1d3cc611e27ea92ce8dc807fe8d446db14ef62ae2f06c293bcdd739f916cfedfc481fd941b4feb
+Qy = 0a9135dc1b0384e7169fb4648973559e508319235a3f41ba174d5f58307448671cf22a3649168495c36b0bced09ac6df98f14db
+k = 0d398fbed52228fe16d32a6ef539e4ee3858a1df327bec999ca25cdbc357de5a75903909973bbb0a5d0269862a74623a38da515
+R = 0e38910abb3d84b2b26ed17d2124f4787dc5612942e98521d9f94baac3d14159eeef9e09b9b20c807b479ba84640730a4ced4c8
+S = 0e370e575302ab0d8d08d5270fe89ba524b5bf21e43e70c4d335ec1525ff5696ced37f0de17e109fd833e5d179bcd4df42d7882
+
+Msg = 0c061da1a16f2be130ae3b20b89745e840bee09633fb49671db28ec9a051545f57ee07e2410ae7ebc61c9af79868d3047705bfc64ac0c04ef0b286e579b650c7165443631e49e6a53c84cefa5625b1e1035a6ed89b8e839540040151132a937666524265e099272c1849f806db0fdf2be64960d5b5853965099459968e5beb32
+d = 0c4c13f65eacce85a51881caa6f82d9e48ec2ac574947d2751823a7f072d38bd9da0cdf30b6f19084a6d291052e7bbc2e1349e1
+Qx = 0af93430dd77e6016d1b076a52126a729f77e34bb3db11328d9edd56e29a7a09a7b6a54f72076fcba886ea78ab6ad81de43a821
+Qy = 1419e1bc339c03a8b4413ff009d76f9a19e201876ebbfbb3dc771b7df07bc19eb893ce23e40c679d7909c33af2bcd7d6306c0bc
+k = 0889be0918e7ef34d3ed226f967301a10fc30111b3559e37f5fa5a57dd5c73ff672c5279d096c5b04c68b71d55e549d019281a5
+R = 0a4bddba9b7a402b584ceb82a54baab61e81973b7347e6dc9e3ce0f1e50dc21c9569d8ecf8a7da97c38e92e52636eb13d3b4c02
+S = 063c7291656466f7bd647073a50f410a2cd9e8c938aa1fd3b28ddc1cbdd7b78b757689dd661f5173f79896780ac3fdd4f3171ac
+
+Msg = 74ac2e1303297efc3ed8e624722df505df55b7f33964cc0d270604cc48b58205d8a11952232a8feb0079baa30d7d33660268b56a5a3dd90105f0703abef8f6636a99bc63bd47d9df100351bee32d8205dab0dbd2af36fd173409ff8d1fb7b24570f3c1e968458f58aea5aa2f46731ee91ffd6d3a060af6b3d5020daf1362af3e
+d = 0da591461791ae7847e6d8dd8df46a63d3021644abe9520e158406c96540d8fd82ecfb1c3f6f5cfd7688c7656cc3e3dc94e586e
+Qx = 1f48c95301956c62e2fd931df49953519b88ec3915c8de495dcb4ccba97bee023b1a6cd9a66dca29aeef8f4f1117eb954e47cdb
+Qy = 10db6bf78cfeb92d29a922c4b05daa3cdff3917ba6978fe738296956ed141c749a938ca9f8f13f711aec930e0f1948ce7daf9f6
+k = 00576a91862cd63acc067563626977fee6f074d5726cf4f68e80d25029d4b8efe5ea845745c45e4cd42879e52854c3f385a10b1
+R = 0806435400248ec38a6d362e8b2cafc3f3bd46ba5baf538cd97683f76a733ba2b4ca85fa7d13b99f4076e7616e68d66f05ebd8b
+S = 00ecae395fb324b4366f238f0df22d011bde5db6b0cf4189e3ad47101067ba87336ca47d637f09f7a40a1bc64de8c4aef7f497c
+
+Msg = 2afd17344552ccc577b0118caeb7dd56a0766e25f84df17c0505f9798931374b48df89a48c64e199108c36e00c0bf00a97ccde55787bb97c6765601765ab5417f3e75e35a9fe5e0f85a721d9f08440ed617afcdc200b318940a1e496040a6ad9090476b0fb4fcceee77b3fea11de09e7fb14853d1fff8ab12d66c101257e2d4f
+d = 0b5eb943f0dd390b737510e2bb703a67f2dd89dc9f6dca6790bc7a260cb2d0fb8e1a81ad6009ed51010e7686d5b48233c6c1686
+Qx = 01ac00da454bc329f7c13950c848392cb4f31594fb7837f0986f61601fe244eca3db6c4f92accc2fbd1a4b8597b70e72d88b103
+Qy = 09a364065a9f67a0aa7518b75a0b4a9140787a67f852fa31342d6275c14713d484dec3116b9dbbb8af1d4945639997ded09cbc7
+k = 049176093dcde8549f95a8f1d1c87230046fd4b18a73243c3599815d4df8387a843bc8fe1fd67f3c6bbe394547e11866f41acaf
+R = 09d7c4ddee55f61c5c4c2ac6efbba6164900344004976381c7b18c1de541a97cb58e14d14b6e433c4eb6d4bfe6d3e0a4e457469
+S = 0a9acf355bad544b3b120522365bcaa1e1dc6f1d3df1e30d3beb94f639e26147a81d154a684bbafac965bc39974c505fd0f811d
+
+Msg = 174b2b083541f8284645a810801e72631a11bd7bb805f684a7159e055afc44357f2c80df2b7853678d34a04144e0ede2327d03db6df23769ec41194a8d9d86af74d51c5bc11ea878c6a80689af71d3fdaf1c651003385332a512e03dd040c33d9c328ca89ec7ee9026bbacf30a7f3a68e0d894fb9f7100ffbc64bf17679dedd1
+d = 09cc63f32152284fca27ab2837bf1343144336a1fdf15b9727c47e877ac69ac9cf4c97b4bf42f1ab10d73de8597a554ed099efa
+Qx = 044e655ad66ca9af330c33bc6d00ccbe4533a4c6a44a3f23c921b62eeec8cc1918e19956f3ed848fed93a7fd7ddea57096d1f23
+Qy = 03a71b221c85607821cd864af6f533f216b641ceae104b8e16dbfdfe7edcb2cf9ee0dc1679b696149ff42a051c51c861a3c7530
+k = 0db9bfe4c2e659006d31a7b44eb7bcd6dd23810f27c74dd587ab9af23aa5962dd18aef1e95da4ebf4aabfd558cbf72d2951bd44
+R = 0c3b91bf0794eca7faf227c4ee4085eac6d6918803242bff4da9c5dbac2e23fc32a4d4a192d7737be22810812558f820b0a2c13
+S = 03120a558c0edb58ae7ba36e886084801e7604558238c85a199af6c9e7506ea4e748791b04f3a92354a4f1407837d87faab66ad
+
+Msg = 758df71a952cdcffdc417b9fffdfb57582ab5c5473a8bdf0c2101953b023b77824263353dea0e2ede1f800a5757ec6ac0e1e4e3ab5a4cd85567d2d19acc6b7069a6e7368401cba2b6e642373654bec0ddd19fbf032794c15b7ef7e714e13e36875262c01e77766ed53cbcf735936dc9b33eaf2152a396349c82ca0297dbae4a5
+d = 09950355e8667bea8bbe3a2c4988436ab5394551b375e27fdc0c1a1d1b07ae957932f428f1aca0a486e54cd0b5bb0a5c5650641
+Qx = 02f623f81fb9a299b71ea8c58d5bd7d89e7be66ed8cfd7370de515eaceac90364438338a3fcf9981f1b6f0b30bc61c4b7c15791
+Qy = 16130b7c4061422d70b21251fa9c3d4e9636f5a08cea794a0fddf74ff5ab1b750cce0f2768d54fb2fb75e2851c2296b39c0ddd2
+k = 038e8c70cd35591012f45f27980095c4bcbb3bd36bec594927968d3747618c7f5810ea9e0a126e4d3e1e08185b031dbe0b37e5c
+R = 0cf957d59b03aed0e48189d2b9256b5472c8a48b4911f9cec14adce5c6b4aa22d093a116364bcae01c1a739a4023da12a29c058
+S = 04cc2c22b243064758f52264ed84e757ff67c4f6596edcfe956b70f777d865d01e529f0a8a9a6e1895168780ab60950a62d2d2c
+
+Msg = b96d9f66b2000e9408d602096f032b112f0e05ea874229ab9daf6e05bee49b4722e4f2d8bf2eeaab9dad94438c76b7cc64dcbb59cb4e03f9ac70487a1d24d8d6b72d7462fe738a17edf381d52179b3acc0c0177c113eb4d10e8e78041deac1d56abda0ddf892edb8be956d285e7236bc6794168f8a180f622dd5f2b9e690c275
+d = 0a995493d6971c2d7e8fac3da9f8c0b5afd877cfb94924cfecc167f9d87002136ab253e3a4f9ddf5c9c99bb1dc1af0c6a3a3c4c
+Qx = 0ac0e558dbca0fa6f013b7282e02717e91eb73304b4f7ac5e04f12f55824c441faebe5bb5af82189044827007bffb1e26557941
+Qy = 1178bb726242c718b416b21cdc9fd90b31ba6a8350f9b4ce3a188b1b5dffd0e8894ae6a417c4d74c920fda585624eed4c1d3f99
+k = 0d581293ab1e509baa50852bd3f21f6493cc524a2c16206e461e320c7f2c1c201b9d2a1dd4207227592a6457670a67cb72eeb58
+R = 022624cbbae5214d2c29e273c334b9ea78e10c7efff3611574d5fdf6f67a81472b606e0236aa47106097b9147fc1b56d062966e
+S = 08895d107ba789d88a17c30a537402591ed788206487697a72f69285ee5eb4f03cdad6c2604e174ef4b9bb919d8b39bee6231c7
+
+Msg = e7ae60ac55e6ba62a75d5328bbc15269d4638764169de0bf0df043d15f9152bed909b1fb8c7a8d8e88ac4f552c1092b62db00958a3a827f64896f6de4bbd8fa5258d6c36e3904d82d3eacf6eedba50b0242eb6b01212288448c3a9821c4fa493869c01149ff1850e8115cf9de1618cb8744626b1951d1de305745507c8b21045
+d = 070daf435cdc26ad66c3186267ad12d10f28d32d863f950cbfcf042fe9dfce553750ad098f82f7f1650c1126b3e4451bee6e11f
+Qx = 19b41af3b557c274cf117d501ce7ccd04d8bff2dfc737d7efcd7888f2dda24737a6788f16b3b6cd589d3f65bd95194799d65659
+Qy = 11983077a2c371fcadbf47b10494f6ffc7ca8873b3d812c45a87c48e1b49edacc0ac37e5038cf1aba20360b74c0903c23a62331
+k = 043fb8cb87591747d12f4897dfbbc79644b87907bdefdbd7ff0f6f2e7970c7d40bb2fc08c17443d029a92487869f640607af460
+R = 05ea3493a8c04723de9de2cbd523481e3a8593ae8f010ecbd5add6db5a82d9b13ee7d24ecb417419639d0e9f4e68d14f6799829
+S = 0a9bbaded0a2894e384184e166bc06e1b2fabdc70536caeb3d0cd46b955743cfa8ac6edd03760d1b613fb445367734fa4270139
+
+Msg = 666b0dc2ddffaa7ffd57ea3b2768f02d4b77c16fa007c6d1918400d195f068cae2dcaa69817e6e4c70d5b29c5598efe2d957bd12d0fafdcf5ac52dee80a2d46e77fc18cce2a49bfd787ff77b942c753974d22434742bdb494590d17c42af725b1309e54566276af3bcfbf5e174d3cf191b85903faafa1583282c97e66c5da6c4
+d = 0f8121980dfbe9ad0bf92383c7cab95fb72d5caba96e1de7772c6a179e85414802fbb86d725401451329287305570ec7fdd873a
+Qx = 0c62f4e7eaf3f1bbae71734c86b8a40ed1297b9ba1151729f9363824425193e8605c2bcd6094aecc9d7ef2a41aa6b12877291cd
+Qy = 1882a45555b68596dbc8bb093dbf1aab9900cf46653c58f5656f3688fbc72c5236297be2f0586a4031279b9014f2d3655adef41
+k = 0b4b5b19922bf6a34a00454374589f9c89745eb194b0352061a79401e23c0c0e1fecd7597b5a7cc1c463b76cce7ab921867de00
+R = 0f1fcb80a4fb49348fb326e808d8ed8c21c376f0713429a22bfe16d68cab0295b21d44029083769761c4fb853662d440eba4cfa
+S = 0252a94a40008cc2c1a69113d8e14e989e7fe13918a2852de6930973a91784eb35e20d8ae150a88c459167f8ece998cbf6c5eb7
+
+[B-409,SHA-256]
+
+Msg = 3e967cbc2bd936e0b6125dc5cf885735bdcd2d95b2f764de6931c4578ac8e0e87abdf96375481df67dbe1b6c43537e84ec62bfca6672cc5f3ea4125abd4a4119edffe04e42411d338e8b10abb1f1f818c50a9631a3f89feb5be5367bdcb0a8a82c96a427ba6ce99f9631d4411a2b7f5b14d32cb3901dc9d285e4cf5508940942
+d = 047682b2e3bcb5800a531858e8137692a9b1ee98ea74e929ce4c919c26ae3b3f1d4122d07fd9a70d8315fab727ccb67004187a3
+Qx = 17ffffc1d2009e844f8e625a3bf11749a8b4ea0b0fe3532d124112edddf72d518ef577f160962b88ee38b11445fdd356a26bcc5
+Qy = 0ca356fa8e90325aafb1826a694a55a80b2af52e70ad8d507d48946392da8b9fa27b8ff6927fe5130c69809d9a2c4b1d7eff309
+k = 058edc8f3665ff9166af55e69aab9d468f576bcc8f652e950082a48224b4923cb9396ed4ae06f05bcf7797352035484fdc501fe
+R = 09b46600fb3b8204d4cb63ddfaad1482dd8cf8652f63c926895b8b8ebfe27295c052b3bb81dddd8687f4864f258a433010c89d0
+S = 0832f7674eea791b5f17db7cf9e2ab13253d870c6ab46ad01cdda30e78db8b8f51fd377dd55ec7786ccc92b17364a3c17ad5be4
+
+Msg = ca1c90012eba4e7c5f01d8cb3814c58f48c03a16be6ed86934014365eee547070b870d1d26a872cfd28b60d9ee0a66dea223e9eaa90ee28076188d6091f26f665684f4b486af70669555db9058d485c677b2a34d4a98aa8d6f43bf6f44aff2a23c5d765e98f0438ab81be0585a5be29daece5d4116f44ce6062753a3ddc505f3
+d = 040cd1a06233ac27f3ddd108de7c6c0982793ee620d71982697713be9fd5143658929924cc88747a680779bb00da8a44e1e7d3f
+Qx = 164e518a6719b1ad61a38a214ebb06dfb0553bc760799e668b1d0d098ae3f06dffd9b84c16de90db19043d72bed2601fda14b1d
+Qy = 18e022ceb850eb1db59e6cf63c4a7c73bea0b70448a7dea77d5ee8a2e1a36cbc46454bacd5954792de82f3ec21ca6a509b0c7aa
+k = 04a936fccec003bd9e8eb45d27c0eaedbd452e6fe99abaa62cbd0739bcf259cfb6884d1e60b82522c6146f081663f6f863576c9
+R = 0dec1635f2698d4666df2c217fbe3e644d27592c5607a5549c877257cba7bee29a8cac75a044e72d039747d0d18de1c34acf072
+S = 0138493216ffc3b8aa2e0c26f4fafaccd6609e6b15f767da7c907db64b5181bfdb447d73ede786144c70ddce7df7eff46dee4f2
+
+Msg = a54c4351ebdb075d6a42a787647390f864b2bbfd8bb3d0e0ea9d767200fa344d1a9ff091bddb186acd69bcaecd767068efe4d752d185bfe63f6674279d0e7192d2077c400bbc0d5599ee28507c1253f05eae0687b965a015e1f3a292b4650106765266f5c95b77ad2d82a6a6e012f233169eb6b8d83576901cfd4a927c54d7f4
+d = 01ca6f752aae4eb7fc9c73a08d6fbd96bfde5030d759a2507bd45b6e1d1487e53abbe98fad4f41976364e0a1d830910ccf97abc
+Qx = 0f6b7220bd24652572b37a0ff25e75f72d583c71c159857482ca9944b956a117a6b2ff96614898757b8a587e3c2b78d9943003d
+Qy = 118fe425768bbf3a4acade281c41c745c9ac946c2f8b95d65787fb6b64deb71e6b38fd8c721e01c87efc7c2a6d8066fe3b35a0c
+k = 04963aa161b5ffbe5d7e5058f0b1457ca1b9cd61d731a0470beefe5f8998904cf4594f98dcb41283f66e2b07c5c5d6a6c587826
+R = 0abf824d43d993107b552d7ded13f49ea0ae7bb845e56ad7e53cc5f9d64f99f9f250e4305ccd9f6594c92defa7f6860fab1c349
+S = 090a541f1844357f618e5ea34c0398ccbdab0cb363e266980ad304dfd675bc81c0345a4d723fbcc76ab5ed4cb0ba0af1b71bcd9
+
+Msg = 6723dbddc8720feeb75e2a061b7fc49079f999fbc79ec8a8e01ab8d35b438b7049da5a23c49a58101742791f84f45d5f5cf551cd7de6926a0e2c4ffa1e378f038da597368c62df8cd8349bf046de46d02183dc05b3a3575f5f232dd2970057200e2c9cb60eaa6b4d72f8b73d4d40b98d1cc801d1a69cb5ed780a75a4064623b2
+d = 0fb9b1a9597d216028902abf743d25944258b48c9762d4589fe660396130b75f6006cacfde60f6204463cb8c18b032de1dd68d2
+Qx = 19b07f7f4ba100aa9e749bcf93a2c9955c442730c5e1f6f72c1b1d132b780d92f414a533282f7b66677c8cc8a3d5ba8b3cd3cf7
+Qy = 06ec6e9c495ccf600f8c19597e9cfdb639406b04f57a29dcd1a7a843c2c44e8321bb8508953e9c0503f77d36bdef24d5d39f85b
+k = 0757f6acf74eb02b7ff3161b476dfd8349854154186c959179f11b9a15da3dface40ae6ed771096e053976866433382e640283a
+R = 08fe276e7f63ce5f85fce19d1739a8a9986cd3c3fbe26fd59324efd98826f9db3b228321b3ad1d96145ca23cc02616d9e9d7aa6
+S = 016e06de8e3e0abf4a4f52bd2f827ca4c57412adcce3271fb4014069713f3723a038bf560788d8dd48430d3b30faf15ad9c0d69
+
+Msg = ed53cec5e5500d62d38c829002916c657674ede4439c6f405ba672327ec677490e656bdd698f114c2ab5e6a1fc94a1a8d64466cfe9eaabd23a8b5c37f76a3c0decdef73b3e7b751cbf3b0817f4079560b5ea34cead88ba374201236bffc48eaf289bbaa4e828afa7d732473c228ad00588c9b443d65b998f21c3d7a9e9196c08
+d = 032109202d754da290c266f74f47805a06e6b5c3f721a72fc97a3bffeb8887e0c642d49a6bd034847d0a5ba09239c5dfdf0772d
+Qx = 0f4dc8b94dfe0a27d4d41399005b242c3e5b14bc7cec55ff3a1561c894d73f365fa8fa2ccde1fd7bf3760b96ab2db78d2d50b03
+Qy = 13ac66e95c335b71fd1a98f101a392dd4696a806239fbdd0708acc69333febb48d4b649f14f42841d66ce03f1fb557a361c12c1
+k = 0b010ef786c13ece3a10eaff79b93ef3899aa385dcc1914e16abba90de0ca6389d664082fa727fa7c7907dc4c88bd621e6124c1
+R = 0488b8956c5999c317830206fc8b9f6760845c31bc4ba77584925dfe25c05a1e7d298a62e9748c7278eba622713df59accdd78c
+S = 082701053ddfaa376c99cc42ad4587d84a358d9d8a9533888cc382623114aef51170de77ecf64af02e09bee203851abb22f5d11
+
+Msg = 13829401bd41e9fe01329e9f5a002f90f1a6ecbf25fc63e7c1345f265ff02e496230f706c6ab377ea52d8707b54f8fc5c7f089044e2bec1dfc66a07da76ee12fb9ea0697d87706b0ebf677600bd2fe117f6cdefb8bd636a1b6b97549ee78f992c24acdf3a946053f06fd012a9c703efb8bd929a66aa74b05d61bff0395232b00
+d = 080536e820fac59b3203aea928475043b2576446619001647e35693a9e65d15236c3cbc12e1bbe0eb305973535c882b70197a92
+Qx = 16d7448c0afe992f8c59b19d6cec64d8fc5b10026a806760bbdbbf0012063f46d31e521a34771f826669c4d1ddd58d3aa13ebc9
+Qy = 1a3742a6f231546f0704345b9b83c72d5036522449cf60c1b3bdfa4c8d36e499d4ce62e6e7bb05c6132bed1ae44eed17414d2da
+k = 042753a515e607cf9992dd1f249820dafe53993b59b1e57d8f2f9100f609cc15713d27f5dff4007e078d6da1061ddd36c169c21
+R = 07eeb1cc19ac45f52c0b63ff8ecf4f4f35958e86cc3e3a071a35446d490a426b48b6c287027b003488573a4834a06dad48520c3
+S = 01410d85f3f2adf065b60a126170c43e34e0883338118cd33b0b3eafea1d142480b236ce49d35fefd1ce4ad3d25e0cc9268b1d2
+
+Msg = e696acdfcc96a6c088069b7595ea9516a36d8fe04dedeb789fbd965db0cc64b7017a821015f6210b6989e515def5a9605fec0d337e4ac59f3101a505168bf72ab6d98ec62a71d2f94071fc05b95e98d4efc59fedc138e3e49c5d0b44d1f48f7b1e7c1944ee189b242950d2bc804d31c7eeb45283c84638f043ab9533976433a4
+d = 0b05e5f0dad9583ea18fb8fc4d8c75fd2e3cf9e92cdd9b737485c953620d345006c31c288b380258b6500b84f729ce6730e5303
+Qx = 157c083ad9789966905c212dcfd7c049a8ba3863fd4886e4b118b3f06445fb0d4745c2a8a1193dc68915722089d0d382253b675
+Qy = 0867e8efb575800f834c978ee2ecf0f84f72e75dbbac86926b73fab8b47f38eee17a63baa02e3edb9d4f6b2fd2afc88b6de36bb
+k = 0c72eb08acb1d422999ee8d51f9ddef9f897dccfafd886998edd3ddf30a638dbd0ed59d68885ce242fb838f022bccd4f3b5f854
+R = 01f4dddcacb088f6e24d331e8b111e390735a41e1fc29da8f5ffdbf7342f4b9056786f2a67159d1e57570bd69d69235ec562416
+S = 0809840df1ef8fce9b2edf8f970c07bdb5fb755e9d5bacd7996275c4f890173142c39299ce9eeb51d21a32acfc7761d5a2cd7ef
+
+Msg = 4058b9a8cc15ac148909eb97fa32aafbb6077b168dde91a411dbc973df7db056dc57ff78f0abcb70f70f800bd752197d681f44df4a7817c0e7f60f8f65489ecb6167c14b525e91fd2cc5d8b80ba380a83d031d5827c8b1262c687c90ef0e62723d9b565557f9f6fed0db48f3799274c2cd60a14303406c35802cba6261121296
+d = 0be1d277813e79051ca1611c783d66003ef759b9e104f32298017fb97667b94dcee1ce807dc6b4d62416e65d4120523bf6a4edc
+Qx = 1fed0171b5b3c6d9092a6592944680a08a0d4f99f08a3ad1c22b5bbf11c0e4ab3cdae9526b0ca2b1bbd961362faccd5caeb1d37
+Qy = 1ae7d57db848e5c86c31f542f1995c76e916dea9aba882865febca630bc6a10ceb6732bd5f07f51bf2f37ecae7b7fbbca618ae0
+k = 09e3585213c6d6706524e3c8e753a2eb0edced626498eacd842d44a73c602d801a079f94b781ae1ac5d44209e8e3c729ed4e820
+R = 01098d98cf83c705515494cdef8c3f50ea8316d95b3ca5f9a1296f09021de57930184ee4b9f563aebf5fd0d5abc0885cd24c0f2
+S = 0d9706f4474a8fb0c701505516699025fde546a21a3fe519a173a3ac01f683d40b4db2642330bcdfe188693b15a476cd9339ae7
+
+Msg = e793237d46e265ab84ba9929b196405faa3b0e4686e8693567e53f68e6991e57677974677682a2510c4c35b1968a90b32c4941af7813775c061c008a60f9f671cf7419c94253d6106b61e65034497f2d273a5058379bd986e3d917f708f0a2bebdba150f6d78a3af9c722a2430ab0f4bad602e91e18aaf258e3785fee78e4502
+d = 073c807bd7e07379782ab790720de4ae5106f16d34e80ed70da5b1594e660c9b775db94066b93e74f855f57d88b6ecc6228aace
+Qx = 0301526b630ac3fca5085f633deadec27af353233e6f241772c7fdbfa42e47a04b0d3ae38c04eef2109390a71fa9fda652343cf
+Qy = 137eacd97a8449ce83f19a13a248af52e512cfab3e2ce1ceb789874cb08757dd9e47ac21b5c0846498d8d7cd90122c437602d52
+k = 09245ba1873114ee2a3e642c5b15049a3566a2f003cb3d25250028655fba98203feef5f307a9f4c77f232976d83723f2621eaa6
+R = 0c8136d4b998ca0544ca1430abf55601f259aac7756c75d1371de63d1471053c789833c5cc257e323a71f80e21783df4efa169a
+S = 0e2ecc6f0a418bee5de7c2418c4ad85d981b18048f94865821de696488ee19291912ae7da1cf5fe9708e2beb18e6cad4e3f7849
+
+Msg = ffb8bc80e7619a562d8506eba7658bef0c25ace3dc1d01bdc2ef00933d4fa07b80364e5e5826074edd46a707dbc3b0ab19eec7ea8990839d7fc0a80b70661204c52bcbef57c1a7bdc861c10766033a82dafbead283d911a9502d5f9ef0a39d35ef26f3616212d4bafcd413ffd18b424fe09b48ba02ca5d97ec996205cd49d22e
+d = 0a68379b2296a6c944ad5dacb593b302d8ef0b05873ce12bbc371d705f308c739d21f343349524aa72f05341e64f7435daef112
+Qx = 07fa0f698535b011833dac1ac96f3739ecf0c29f7fc1f8bd635f4f98daa70a39310611ef51b2fdc8b37eee3573dc34cd2528d39
+Qy = 0be1a9dc30dabee3403da4f2dac6622e6fb8496e72f3f17c169e7b554efd84ac655e727ae9520feaecc752601d5391270cf0cfc
+k = 0630547017103c3f97de48ab6b942db94b2db9ed7dab0391ea9e71c1b788c547abc90088de5b3e36c9ee4280bb454c7c3710999
+R = 0916aac91ad329d6f330cb051941c781b9e59bfbfe45c4d4f6ce0d1aca982e1c612952bcea06784c57c121b14cc0dcca783d0c2
+S = 06a83d93f9bb81c61ac290906d74e2d3b964c39b4e96370f19cfb4a55a3f7901bca3deef4bb79ca6a798fb9b3a9b0137c5a9324
+
+Msg = 946bde90a5b903dd281a51d7fa93d80f3fed07eaf50c18fe9fac5acf67326bb18effa3144e25c151efc006a50a274ec6c6a5d573051c4e2d117ceb0fa125acad07a10fb6534a8e5f5b3da2a1136779c51377bf76c3a4a93c0c6158f729f2293e414fcb952c9509f228c804f0adc1daa327a8991d48ccf4f3957c5f8ccbe3ad4a
+d = 026046bbb269ddb1ec14ade56175482343a21b7c265026cef3c7d6a1ae0f6a68166b9e6c49a6e733ad2ad64df7137ef230038fb
+Qx = 0d09d8118519f9d00df7514d2ff99483473f680b750604580b61017513870a3cf1c403495cba488309e2c084079d53139a36953
+Qy = 0d25e41038c18e4ba6f4e9d14f210b71f27b8ef2c1d4cdd5f63edf8fe11d548d070177e9ddae382fed2b163ff2b58546f10a99a
+k = 0d6b0e5d83155a035248ccea95feb0b4d1af818e5ac6d5f41f1a255dd8b482a94de0f4e037b10339d1805dbb6b22af6ba834219
+R = 08059524790304a37f2a0d57bb2b93cec79a827b1fdc9ce2d7dfd4d277e0f71844d335314a30bbec5598a399e197a852b5528dd
+S = 0e7870e2a0ed16cf340a04fed4d2048e4e231cb8918345e1852bcd3e30413a2219864851121a34fc98dd99976e2b20cf1d1bf2e
+
+Msg = 07f3fe1369ebfcbcacd66675bd4ab22edbbff72e68709cb57d4f590e49440f01691f490c58b5117bd24aa2fe2101b59c61c417c918ea08ea34bbb9b8aa17491ae5d9329affe894f42d7586017877fae3ce35bb80c97f92a004380374ec91e151995166e14ac00505fd1fa810cf02981bacbcebf5f81b2e633d3a3db6737890f4
+d = 0bbcda66978ea526f7bd867c3303b625f11b94dd9ee6e2c2f8688ff07f2bba83c662949d47ad47fa882cb7d203a7f0ef5dbc52a
+Qx = 04cf5bc624553e833ffbee05ab863e5def062e0d57c28e71d758d6ffd3839504d7ed9d3b1a040bdce8e187ae0b4ca23aa565b01
+Qy = 0fc1a15b4f273737eb92a56928395f6518e05bf946afb65ebca3787f7f8bb3d946dfd26c4831cfd171b4c66c2237409ebf224d9
+k = 0a2cd205d957a20c79699e91684cd22746c476a79245f11e7cdf7e6b74f07cf2fd9eea65eda97e8994aaf51942e15695545abc3
+R = 0aa1da120fc19523e8162e6018e4ee053eb680ebc7e31d00db34f7b177c74c5e6ea344bba3c39ab7ebcd92996a1c156180b7dc9
+S = 071aa4588741208344b323642fe03f1cea73865ba645169df9c84bdbf7488829b83b8da172f1927de1c8cc318ede545c748c782
+
+Msg = 3a1cb13438e3bac9ad4ab1d319e90e2c9f118dcf1eb54d6333c674a665d41451f93cd4a9334cd057a44c010edb668254517a63700a31eb0ca474c84873e486f2f8e158a1a7735362ea0cff8ef17d959ffd851b21a91412709b3c729474d2cb40f6ca0e397030eb2611b402916e4b656f0fd868247d80be3ce33d52054b7661f0
+d = 09be3dd3442e0330750f0a6252bf9cb317f32f942ae516a4038dea2c40ca6484fb33611bef016cc64baf166c122e87c15466fd8
+Qx = 0f05a6fdbe6f80c0f5ef3322d8accda4b9ae28c91b6198b888be713afa5e652e907e5ca9aff5fe77b6546115b4c732bbd4010fd
+Qy = 00923d07aeb8c947688e7d3dcb16ca69440e2a89539a41b8fbb797523d3b766b46d257b87472f5084992422cebdc4e45556f5e4
+k = 094fe051a13ea8dbc89c4cc5511881a48ef5554de265f0badf8741ae5027eef25c617bb6a3f454a992fc68f5a548903809de09f
+R = 0162687730f0ab2f57e348476d1fa4eaf13199ee44f44dad5807bbea4e5ba79e92556f287cacbbf1fdec9a8b78f37e78e52dc1c
+S = 01acc734e2d0c81a56ee8c0465661c365edae56228ca43184ea1d7503da3d38e7607b1590f59f5190e5c7264cd0d7a39be71069
+
+Msg = e58e7b881a563d54772125b2863718690a5276c93d9e1c5feabbdb5d6f7c7293ff0f89805b53663bb417fdd46874b8e6a466e7e3ff6737930a0662af1d5879b071b0dc4d014778dff26a2eca5992e763bf4c4698c382ac947215aa116515876008a56e5bf547857049c38a2d3737ed3393705fd346897c3beb80caab88e5b8cf
+d = 0ed321fa283c662e87eaab99b7715e6cdc9b42e14fa5bbe2c56fdfb381369191a42da7e574839f90a85577485f19446fccaf6cd
+Qx = 1bbb34e6bfb1c1335c48e8b44cddd8a46486fad4313581df216002b382db1d58adcae74af0d38445cac2f6cd9e2b439d106f595
+Qy = 084473a5da9f910b4807ec5ff450be353a187af6ace821b18e096c47752b6336dbedfc4b481e356e689fd9c03ffcdbf3e4ea39f
+k = 06ae69e55ac1f7b0f844f5ee0b583e652e0e5bbfa4eae85c59eea1485148e34f4d33c9ddd7ac071a28ac0a6191d5ed03e88bb86
+R = 0c3509b6c0356e4a30a82fa7411d1fe17ed190b7eebf9310c44fd568494c894a4f4a1a09e58a4d030d47227e54f7220f3f79f4d
+S = 0d44ccff47d9fe82627393c03f882d4b98633961a897381ce8b2cd18f38d69742802d18e6c988a23eb425b294f2c1b84cf42cd1
+
+Msg = 8889ea1da1cbed98963941f6ac24f47253ff6af52de920765214f2024aeb04f7ad46936830a8eb04d95aba64ed7cda6ef242f454b67bc2de38a46b6524bd5c96739c4b580e89829a61a8249ec8dc27a50f43b8554cfb6f4fa4ca6875983d4b60a1c6b49f32ddff6fac0cafb64d55c6f594b195c207a9bd920dcf20e0080920bf
+d = 0396b805073f3c3b552b1024dcf35559ac44f255b688871a3c6657f727a4b09f3806cbb75d26a00ae1728be632387e804775a8c
+Qx = 09957f897a17241eec5b8415ed7ec1bde5df11583255e0a8136d076d72ef377ab3f553d6f56c054332a24098aed6d12878abbd3
+Qy = 1f58eee295765e8a55e388e235e833bc5cdc5d51a1d98e13429bcb7891b25487b7fd8ed804b1856cb6071cc28756bf00924bf1e
+k = 021959970a6ad070d1ac518493e309289f3d9d6e2a8933bca715f53cee4ab9000ba2d0147282495e15e63f258dca87a5db7eaca
+R = 0d1ca34413341c115f780e647519547602e0361ed4d70402f42d735353696eac6e4024ed2eacf9577252d40c27297e9389d1f7e
+S = 08cd5bd43794b32d5bd2ccf7ae4deafffa0e0deb92b1eef9d3ef807d456e459f92e9f10627b7e7574ebe3c2faa858bd3e62e187
+
+[B-409,SHA-384]
+
+Msg = 55053af9370901e38622734a5bc5589f6a20e258627f381fb0c366f3dbe58394e5997e978eb7ebbc530f6e6186f48294149b8594fb551c31c50521a8c4d67e5862921695604afb23977b6a69b21abe75966fdd11bfbdb6b51ab0a474c5fa07c4de7872a3bd81acc417655090558dfcd5af449b3347e61fa9e839bb9457de64c1
+d = 0a8fe323f6736bcabe971c7d964e75dece70cb54561da48a11c40027ebddb23e41c7b48600f569500fe8ea2abebdf480171dde4
+Qx = 020f2dfee967949643b6cb8a3810524044a4b873a4984e9795e4dd7976536a2d748b8cc636ef5c8fc92aba5677c4a0951a33327
+Qy = 0956ec5433d73162c9683558f0dfe8870cfe66575f2c34c765372c7c3bc3b291e95c4e3665e4ec5e72131975f0b1f5f30b0c844
+k = 013f26e13d43ba05e01f92457374fe2ad1ccf94ebf22334447f9360f7f9748bf3665ec3058ff6184fbfdbf7de9e1e2131cd3991
+R = 013c4c290cf89789bd6dc523deffa20c94e92e88a76eebe88457e30cddb066c7a43aadeb0493b264cdae67532db7dadf879d991
+S = 043bb7a8db3d79938beedcd6ce02f375e26ce807a2afd4fc446f372fb09a69fb34734df5dc8f6393f86577a8d29014494379624
+
+Msg = c4264330534a6c2bbd8a3b757e0912558302ce302f835ad8c5474993832fd30036fdef40b10ee37293e871db5b0b149654f9e543e22111f9709ef45732125f713c031ccfbc9a2f3aba160c241d27be4dab87ab2fa9a795752ab2daf20f9d06a98d90d01c07133adfe83cb11d5176525e1bba6a9ba70ea48b224d46ddd8103f65
+d = 0105938ba9f25034da3e032dee121bdb192ac2128b50a2ed4bca042e96cfaf4660c9d35f3e67bafd4c99f9447e6dc408e0c4471
+Qx = 0f1a9243920d7cc26741eb828bb55e34c140b0e52837792ed6274a9aa6b5534cdc5c596a1141a746dee380c0d9c2f77094c36ef
+Qy = 1393ed8c609751550ffd077347712f3b27a869cfb1b532c5b19c381365ae5dc8fbffcb2182777a17690616d71c66524017d861b
+k = 0fc52aa8c590aa28c5353568c9dc69734adfae840f1e0642b57863dc7f4faa37bf3ca789a3d7afb32c57f66a61780e253f50af4
+R = 0c45b1629bbf3273c0e785a28cb8187ef387502ac4438a3372a5c72206a15d7c5ecf9203ecfd7e0ac910b6ceee3be50c6664f81
+S = 0a0c2d31a47ad5f9dc2d42dc36714cdce47666f6e2f05ce0e7136f166647540d1e5fbdc7c9fa0def8962f44f2f8bc9addc10057
+
+Msg = 3236f1ad164e1b25d828f5202e3513c80c72a577aa9af56f041fd96cf5a3363f4b827723b1511a2f16360e32eac90ac55f4ee1146791420ef9e2af333c17d157b00e43992ef6f2be2d2f211361e468413dd93fb69232f0a0d110bc5fff361c0410344aa0636bf809062c73a7ac7c142063912b6ad7e1626fd2a384f35faffaad
+d = 0ce11677ca818537dbaeb880fc967dc8bead203a2538a55e756679c4a9e7975b9b3e6aba4e6c6eab4152d0c0939027e9b0bd92a
+Qx = 023c78eda396efa28c92b120c4ca1e19dc6c467234f9f73701d8966bd0826c20122af5f7c9ad5a5b855b6dc517c22131fb0b5af
+Qy = 1ea47619f91ed4a010dd49ece7ec78c5e98297220b4c239ff4a8c29aaec008011acbf7e4f985c02311ca703bf4ce4ba43412ecd
+k = 0dae763fced0e498e3efa1c6c412a25774c9bd6cd4bce25ab0a7266705cdd54040ec55bd7e6708e71b09ffe9c19af9a1ed9c878
+R = 0a70694fe5da7646184b23b4b434bca1b754257b8e7fa9994dce4a7a92b7ec8c7f8cc69f18d17915c6bbca24f6621f9563f7c35
+S = 009e6ba97ac2be8537afe7f8f8b9cde8841323b5cc63cf2ed46a7913096ff8d96040296a1bf9aad691b60e1f18233964a421fe1
+
+Msg = 6c400ed098d8369dab6fde3553afbbd4d47836d0d12dd16015f15cb8d067a39391c85ca4e78c62b8b72c1592349ff8dc52db8ccb7fd80c085fae456dba6f4a2378e184dd59238c92cf04e40d43a66b342d2a1325a0bab12b1ac857f0564c27b35e6abed02ff5bbbdc3770ddbb2ee0513df48bcba925da6d61583076cd3129603
+d = 05a239ae0f40d76d8d3589f1662b5ca12176a4b2784faa8339b54e96a1e1294433a4d83bf904196f939bd8b33bdb4be340ec703
+Qx = 09d03b7985647027a17c06b30ce9fa1b43d0484195f584fc347f7003802613b524cb5641db3425ab4b3839e12c012853ea83843
+Qy = 0818f5e270baf5a771627b098a6f9ad8a8262e331c299fa0722a0df6ca09bdb9c92d22d72a73567cd5497d06639aa47349df207
+k = 0c22251c73998a3a49b3fc65acf01438941a8885d1c5072a5d41d779af70c044153fed4080151b524af402a4e8ede4448b717d4
+R = 02d3a7ebe5de23e0e601c6e41616bf2a9a7fb6193fef8e3f0a7fb8128a925f7bec3833669d1a304652b7bb1af5186b2f612da1e
+S = 0b7bb17155068a8d9b3412d04d407556ee133e1a704ec5da87ed19dfde60517501af345e2e744d35d844f8ac8ad08b13b17c498
+
+Msg = 039a149eaef2de30b0ae457b376ce6fbf88afd4cfdec02d3c5e00400d3b0484c1cd6ba74db5de65d6f2fe39871349b30fdf1ef29bcbb9e182eb3ec5629d07d98354a5dfa82d7f0db3dd10d1510c0dce086848a198893ca5ad24a663494f0596b4eee86199ea85e7e8f2f76e7a6bd4a052c54287f61b391f1e52f96b606151c34
+d = 0077390c62ac41aca995640fde0c79c76f4ea8a8dbb22323ed812bee837ab8798c5d0ba976c7aa634d4b1c2c155de2709e7352c
+Qx = 1a9357770270c528f2af991c447bed86194d458f693a871ca38f271a9e6a566f5b9ba3ef3d2f9bde959e42934c95867b280e9d1
+Qy = 01f3a0516fed36d3622fae3f44d87c4bc67cee0a995cea242e530451d43781f2ebd163f6f521497fd7a1a6c7b93d33b77083a5c
+k = 02555cc113c8516d741b47ca41f53ed07d509845f140dfe7dffbd01a3f751ea9f22e12c939a2ecb1827c0e56b1b1c5459b66aa2
+R = 0e88333875a507520d0b62b35146e37e7ce4e2f2478a61adfcbc6e1aa9fd0195a4960c633d9d6aa9a79323b7ee00ab802768436
+S = 094595255e8862d14980893c095608113737f42b05b561771f56ac1d54eb521bcefeb3928917c07c1bae74cb9aa80dbd34962d0
+
+Msg = 08617d04fffd6644c40f7dd57919f7dcf3c888f4147535d12ca658302305bb8e220bb17ccdc480254004b9035b357120580882ef86aa5a061b2850100285b7d61588a664dd4f5394f5478e68a80f610c9204d056009c1c9e902161eda33ef61aa902e96b6f094a9f053135692182943d38b9763055a38739a2a2d133c5dbee89
+d = 08bf23b09fbbed1b55769907aafb97f4759cec98649b2c9da5157517d4f85bb70157076b5e4aaa7a940af042302f8be06a84ab6
+Qx = 0883c31c474333f74ab2b86f3eac865c4b2b54975ce19c5cfd23682d041ef3deaa43c9f9e2c194ccd3add6677de31fc9e07dfad
+Qy = 0a5a36b54f4eea6b300491ca22054280b3f09b202b2a6b55df9e3271c763b6d8360a330c16f936d69fa463bc0c4071707c9cf95
+k = 0812c83aa9dc4139f8c3f7c55509f9e10e6cceed30e16afc028b1904b4d260ed0e77acc26e711a7a8e24c75fd780ed893c0bbca
+R = 0fce07c6f791a05de29609b59d55b7062e82fb554341b2b2a8187baecb9c95b01ca5dbf8ac88c60babe10af2edf5985b35e10db
+S = 02bd026a3e45ac439647a483261107829411c1b4a9ab603c080b92f605cf742754b654981460cf7aa72b5186b59d224dd015314
+
+Msg = 34c959f549a307f21b850ae105f41299b8bc94fc292aefc61aefbe0a1bf57576ba8d9b80caac635e4edeb22530163fa9629665fcd43959f68eee32482f1845a78ed7278e6e43d09ed6fedf465001afc0d61f1d2e1d747623e82a762576b879c7024e34f43104593cdd691d53bccaeb8f212dc29bec6bc94cf69d0a8491db124a
+d = 0082ad05d19b8e16f80e53a4cccf6869ab5128c5e622ed146fa8555985ccd2aa3b9957dd374586115d4d75b1c01cf98ecfc3646
+Qx = 04428d05366b0a46e6578fc7528d185a3f85da06c4179e9c9055dc0a7fb4afbc53c94954f268e36d2ba8731882bdd27d9684c81
+Qy = 136ba6048ec672601987e9b7402fea24f88c1a94717ed5a83794add0f31680592d6cafdec147dfbc400e73a6ba1d23d4cb0d707
+k = 0c00c897edea7bbfe1913e3da303d64d0d657a83c1eac9c111722b17c65391f2cf67b78219e748ceb269d6c65f01e92e6952979
+R = 0624c5bcfd8e0ef22ee6b34a8b26bc051912cabac102cbf56c364a743e8150195fc55a3fec90a8fabed5eacc1799b565745bfd1
+S = 0cddd4937da8176ddf0de7f52a4babb1f6fccf861533f796a487f35d060ad9ed4435e5a67166782b53c20bc06fd1b36c265c1b0
+
+Msg = 514f4de08a6f49edbb6797c9dad6d33bfa367cc1a1b58a5becfe646c7f3352d5c5d95f7456e7112c4ddc746b9076b9756ae3916c07bbe6d3823895774a42d25d44b3309d18bfe7e3ccb1f85dacfec1654778c19e2981a853c1f40a7eafd16d331093110698c957fe9f1d86582706a6885543248b944bb70cdf9d2ea89190cb02
+d = 0af7e581aa4f9be5815f0c447e39de00da9194eee5e5f609668b9b69930b5b48a948614c2250260d1917f0ebcb00ebda4bb52f8
+Qx = 044703e0b49437315a64e397085ea2ba3f2e2c383b168f31a922e5916d590344906bd2a911074b7481aae7f3f8f4807b110f2e1
+Qy = 05a13607a3bb89a2a88e27d5eb5cac4eb498d34e6ea861c80271ed0c73e1fa893adce0c1982b8a8af6a0249796e5276d369c3f7
+k = 08e7fcadc844456f14ce9354b218d519d86c0c5211d62904c937d6fbe8cb16264d7d41d98a15e9f73a636ac3739770738d6b46d
+R = 07aebfd1681bd5a2f995ad4a709e8681da742649c0530684fac251494263e98d67247e1e4fc174b409e7e24a7b055500920cc82
+S = 07b83b9b5133aec165316021472307b8b481e6381754a9d0b4f9d683c2ee7cac94ed4d8a72cef61fa1f6349b6c4a54ec38975cf
+
+Msg = 4e5d16cb1dcaa1abab1e371e1de02f31ef4e0944dfe1fdec45ab64326435b2af9aaf1a6ed8fdf1a6ab1182bb53a844c7cfd66da30aec0d41757f5988ada0017c4ca752597a9fd3637668bc1a92bb1556553f28d66805bb47f1ef91908ce098d452872da9800e77e1fbd43ffb0ed6fe6a62185d4be73ae96c9241b82cefb2da22
+d = 06d14107b08354e6a41d7d7d50c004419db8bdc50db43428df5e86084551237223c498bce71a17e25695bc438c5c09e009c60e2
+Qx = 088c1517355cd417a698b648508fd07a457ac13a49d1bad17dbfbc9735ee58343316e3eca570bca130c753e17a69fe5bd7baff3
+Qy = 1397a697d2113d94daefe6be491ed3edce9449c707a57af3a164d172cafece564d686fe0d25725c2919c60889af4d0354b05117
+k = 0f3bb2dd9eece25c56159f501af8b619a8c279d7ecbc08ee2af6b82ead80375e9c07227b73a10918d8c89d1a2b12cb76427a7b4
+R = 0407b224d8d9c0f11a8e09ac8d654dc6e1119e2c2804510a84ec61f9017899f9613e37d8166e0fcaae16c3cc11e9f739968c687
+S = 08c2bd7d02c4c537a308fa40db786ec64fbc2dd4c142b18cf9bcad66199afd4f44cbf221adb3837e84173d174e9c0d534720ad3
+
+Msg = e29e75269754ec1194270f5c9e8267dfdd8c696008b5ebc92bb840981fd065672f07f6a0f1b19841adfc51b478371e1a0db9c3346a9f0a4ccbdecb7040191a00ddfd0a8faa0e69fcf544319c0155d02797eeef99fabbc55078f9d852927c23fd931685424249b87ed0c70a4a3e2d3b9a2f92830e7d8f7650c0bffa8f8986b7d5
+d = 099d96d2dc9c79549f031bd5346cf6a8544c312a3fbfc560dc8e378efdfe025b0e6e61e09c04c8bf4133396f993b0906c33dd30
+Qx = 0883e00d72c60f22ab085a90901ba3e8a510f19c3d62dcb3ee5066e0be094cceb30bfbed7068d0bfdf634a53e2fd002dc9e454d
+Qy = 194baa5d7ae2399965fc4009ea83273676e66a56fd35a5939c26ccaf85633adf78b33dbed6da305979077418c625354c7fb6283
+k = 0c213540a452c4f2ef275dd844402dd5ea590f7df41ad35523edff09b7fbb096f8ae8a4baee95428fee03a9e6f6a14ceb90e289
+R = 071779b477245007ba1ef5f05446c4a08d1c2eab550db9c053e4588c9935f07ba87764f0fce14d4a7b982ebba89cb056aad8cec
+S = 08174bb56cc85ebe7bca1de1f44cf93cf478d7fe59001c5947c66b837bd3a6d116f99dc4f9acb4f378b0321228518e1ba0057e2
+
+Msg = 1a538eb447c18494ad5a5ad27be67fa60eb2c5cb2404eec1dbd7244cd802b17ca5497e779d5f779b981b165dab53ad19fd7bf2ea7dbb9b4baea782a43d758202f147e59d6b6b8ed54f4ea084bc18519943f6894d603e253ba3e8e339a6933bc3a0a47126087038e1c813c3f2997aae321b7c95a802b4b73fc7db95897b7c91e3
+d = 049f347dfd361a65910e97fcefbf60013a54837f2ae657d65e02397f59dc6bca27704fed3affdc3d833fdc621cc5e5f99b92a63
+Qx = 17942b58d42da750a366d7e4cf4cf465c856cd911e5352b50bc8a12704c1ac6ad54f9465e4fc5402b373d8bd4e4f8519341f133
+Qy = 10abcea49c66730ddad7734eb1311b2626b75ebbb299a28c9d60937e6833a9b3dda052379fbcf7875f18680924274fa1764158c
+k = 0134c70f031648bf470ccca4ec19c837051bf700c851df564ef3ceb99d7d41439293bcea0c656c0e5361db92a03def51d7e4f26
+R = 06c0f9935abc5034a8b0a05e8d04de699b5916cb367e834f13642f0003510bfb68714be75c9e35b5e593eba45fe151d1df56d40
+S = 0930baf426b33eb4afbed64869a22712591db11acee7c4d3a221a1e98048f05900fe14816006854cb90631de5797f91176fdcd7
+
+Msg = 7502c755bbd385079a4001b8cd653287dc3054f3b57de19d0ff8f63c0308c64c56f035117a8971d43654f89b52e923947e4760ac72be073136da70c5ad7ca1658cc0a2d2a880d3a0c0fe636fdb27b77ff260c4c1ef8a18da8e9fd777d732a37ae9906e6c4f381f0a3d941048d5a1f6f2cb8593873fa4bb1621a44bc2bebfbcd1
+d = 0dd226de602af4e9f8e25784bd1bbd4cadb0a8aef525d5e2d57b9f3555feb698765672c5099a7d6dd5faaded69d8d68b4804f26
+Qx = 07ee34cc7a24e2e693f9409f52796427ed86fa71bf88c923db305ebd5a83bf3b6f7612847f16d00f4a25614299a2df92bb693c3
+Qy = 1f63f177b54f8dd5c907ff318b66c2bfc1cee09348c035a4413fa3cf5acde0db1c8af4fb8deaaf8a3a6f8f06b0acfd20c6f0049
+k = 0e19c21b05c82dd8c873e5f30c1e3aa9348327f959a4dbd9c741e233c649a426cf7bd9d8e93232e496d0b93ce835f80fbcfdb2d
+R = 042a3907a480329a6169b439a6945cdbe8e4572779c43fa6cd1f15062559dae9eda2712402ccbdf03d88a8a68b691f1f16f8f52
+S = 0d09fa4966d171a662a9ba6827fda830b5404f96f635edd8482ee009ec5c7b64a2a6c17793993610ae8297efa9fe4c35ceb5001
+
+Msg = 95eca932d03f1df2e8bc90a27b9a1846963437cdafc49116ccf52e71e5a434cdb0aad5eccb2b692ca76e94f43a9f11fa2bdf94fe74af5c40e6bfd067a719523eea6b4e65730365ee498ac84c46e1588b9b954f1c218920cbf71b167fc977ee2a89429590f43bf637eecd91b0ce3be2d66bac5847205f76c06b914a970f543e59
+d = 0b6fdbc9c8c76cb2b822a940d8675889ca6f5132429da795462381ce29313a23bc132976fbeb346ed4c691e651028f873ce7971
+Qx = 147647d267afb4bdadf54baa3f5131e79dae8103f5b2ddf70e4652f9fc5495123be97215b811554241c53023a247936053288bd
+Qy = 15205cd5bf0c5154b2dad8367e1b487689b898acbbf44f9ed67a37babbec739804dfe737b324ad663cd2cad79274344397099e7
+k = 07321d12d616dd2ee5f843d6ed7e92d18968b3a76c0e4ccc167790afabad1b7c0dd53d82aacac93d98679b203bad88d5ef0cd75
+R = 0672c5607acc646c67456ee77f2c02117cabd241f728ace5117626bdf91662323e7565438f46a3e25c048a8e2130e27fa1fa2d3
+S = 064aaebf9f2fcbc843ae1128eb6c7e7d1fce2b9901dae0f60afbcb08c7f2ea1b550e159947deb87dd8959921846e2923880db6c
+
+Msg = 8ff68cb00d03e730dddb05fe0b2344689529096c3da6eeecaf097f22c7fa340593106b1f6726f06b7ce7358edbcf801ead959438a42f94cdb467b3cd5b17fbbcf75739805f9eadc869c33c604cc58f81591b0b8bf4d42bd53a801f0f829a31af6c129fb4f20f1250f959754eff8c629b85a716b6a18465b6495798c0c5166c8c
+d = 0203d77fac64591eb9a18de20a9d5eacaa1c3ec58a5ecdb3008c2d642e197141d16b3a9fdffe61429264f5b420f5e9926659a4c
+Qx = 00f66ca09d15d0991b48ce7afde9a148565b73807e435ae0f16c14cd439454745f8ae153786d7c40cce3f43a8aa4f0564cdcbc3
+Qy = 00f4c919b7a97beba2559a8ad0f85dee40e8df28e23732d7de655262209a5170f94791e255e77e8c8cd64c8c9900092e0ff9d5c
+k = 0859bc752300d4ba5014e302aa4cd2a979b3097dcfde5c59f4bafc5bc8a99411174d2ef3f7377df5a09269e3d9461be61801942
+R = 0691ea76acbd5e8137924bee13326ceac8231688af8595718e210bb857d6619c152e1fb46e03fa83bd6b5d81e2463f9260407eb
+S = 054df52eb86c679d8f8514a09f5a3062d2424cdc19fbf6927f744aaa8c444223f1c28ddc84b1d135a886eb7ac7eab3c7b0a42e7
+
+Msg = 01451c4f09720cd53377a5ed04c907a735477378ed960235a833049d6bad6e6e89958b4c4249bf0f6d4f043530c9e5426deb0ec3a12b7feb4860757b41bf602ca95655155356ec35a2db8e2657998f56529be4b714364f83a140846308a2973907ed7b08e935173ebbce5e29afe1444cd51c92824ede960056439555e7e74450
+d = 057a2e6a59d4871c3d547690237dd9846d6d5dc4ec0678aafc9c8669af8a641eed67bfea4b05fd6b3b5357ec4d0caf352691ea4
+Qx = 0351aaee4207bdac826ba17e3b08dd7f94c0c8ba0d9829d7bf0eeee7e6375458b5457bd787f0ff38564734b3a0412bbddd7c371
+Qy = 0e09c4dfbc33d61d69b5a8517baf5e4e1614920cbdd89bb05f0420be757253fb92308dfe1de8db822f57b67b393d8a70d989b26
+k = 0fbe560003dc220e4c966b21c874b828874a33a93bb69c49909376df67e5df1652fd91a1d73c7733f26c121e7a3b2d1246c9a61
+R = 08b85cf3a14fdfc69cd42750baf362286940994479f6ed7ce1d87af12c5ae075b311754f1d37d8ed10bea092bd3d9f7afd2f1e2
+S = 02360bc1f7a98cc87ee2a4feadb98554cce59aa0fbfc087747c7253e54c38815cf91c8517f5692f95bc7c3a713fb6ac43a34f7d
+
+[B-409,SHA-512]
+
+Msg = ccd494ca005ad706db03a3df6d5c6e876ef859ec77a54de11fe20d104377df1900b6b192126c598944d19a2364b2ae87ad7fd32265d59e1f22be5833f20767793677b628f18e9619f8ca32f3af3b41c31e87a98d1527e5e781bff33c1a8be3a82ea503e76afec5768d7f7dd1f17dc98a9e7f92fd8c96fca0db518bd143d82e6d
+d = 00a3da7a6633608fcee9ce4253bbcec08d41ee6b00178ceb017de74e24d48fd89107c9f2db3556063abe3cb011938f4b4871795
+Qx = 0a6123b122d7d0d766897b15ba6b18b3a975d3d8058c9d359c6c6594cc0dc07d9ef6033224b4aed63d319cc2747c0660e38897b
+Qy = 1ab5fad5e78f380aeffca8d15e60731720184ed456800967b2ca47d482957d38409ca07ea798bd892b529774e44080eb8510e6a
+k = 0da042642b3117f30ea5f4b354047b164bd128696b8c00cc6fcc767246daf7483284e411009e05218246830940178cb4ebabf1b
+R = 0e4ce613e6976e9e1c30c0c93214a0a37f0632de85eaa25464b69a251d592560b2039fc59b15ed7045c29c268693d7c9e06d8ce
+S = 0ff3ad5ca70aac94facd842fecdf6a28afbceab80b549507954b7dea6da06d1facd11e0a88e9c2a549e6971a08d1af75aba8363
+
+Msg = 5719e50d939a8d74efb444eb5a77cda48cbb59e7f976cdb2ea2848bfc558718b39ce27b893c229db94bf77992222d1746f8f52f858f85124a28193ae0da039c53d484681785f3367f6516fbb8a86560aea9e3428551facc98cdb1e9df8e2f37db823a7abc589f667b5c93c4c47061400220a2014197d514217fc252cef5a2433
+d = 0384723c8b4a316b450d1fce0b2645912b8acaeb3cad50860cca43bdc0206ed5b3b60ebdc29b3eda305d0d60eeaec261edc24d5
+Qx = 0fb89d87ca4282ccd048606e4d321e7ca73244b4d0c9d3df87d54e038a14939138bff33c81a9ddd64abdfd698bf103e45c96f97
+Qy = 04ff7e1706688a53a5544f4ed0f3f5e1f0fbd6f21174166d25a690f260766646cc6fb39020de9327199225e44f3d95c5984fda9
+k = 03a9f5f26eac81dc8ca0a17acc44322d43bfd18edcbafe24113f5e5fad0ef0a3db75ad1b2422c7321593e41e76eb2a767a14268
+R = 0c311000c27539247059e4a8d789ed4db93fbaea021272a90045bf6fdd70f4f32cd1e195b99ee6f03f4fb57c3a115ffeb459af1
+S = 00db8bb46fe0f99b4e6e1394a5db283e310b24d6006319986dd2c4cc169c775c89d4ad98d0fdbc3c0bef6b7fb6b43ef21049bd8
+
+Msg = c84e5702a339259a61b5ba8ec1957f23ffc4f1eeef3a58f383d3731bbaabfcf49ce2ebb597960ac5115a2af1c62b193d4ab6c24433d5f168a1752e40145f19aeb6dee889a53a4fadd13eef60e28fcc7ed6a9b8b0ca286c1b3d66a4b2c327a629d15c148049e3a0ccdccf05cf22c31956014595e417060627c8125bd7c00f8850
+d = 0bd3136647572fef3de51b12e64b36460bd3a27dc660c164fc705417339cab21f9e1f9be0f3da926df459c5ba58b701d306e67a
+Qx = 0f45e18834d1933a2a26e95467b6db85d8c3da372e607907798745cd9847bb8f8b51f996c7293b51550144f227933ba26722685
+Qy = 05d8b108eb3591b164745d116c80afdd4870187061c75af9b0c3e87dc8262586af14f4d6b1504d274c07c8e89247196d8ce8166
+k = 047a494645b99a3469369b72cc918708ebf453957b49ac4e209f2edd7a4861d014543754e37e1d1a0f477951a0ac2b5826a470a
+R = 09de9e0147e1a268f80836d7db43779ce12e7947caa851d109273ba7e7dc7fc52c601f5bf69cffd5adf0695cd7db8de2a64781f
+S = 0561aa76e1e9f2c1d4aaf6e2da143f67166f09199e1705b631d650528e94d643768cd611467284a9f543e50520e3e738e5d56b9
+
+Msg = c90bf11d04a708e64b6f94d4cca64b92463eae878c377b188c82c1c5f05a038be20eca2e18034d46f00d9a6fc73c4084981748ee9d2915d87aee4e2321f4f9e11c176f01281913e324700d9cb474b7134fcc408fb4a7006acd9e63d4578ed4c2729d8e0d01b1e6174a43a024ad261eb644ae98979c3cdab75af357f6dbdf5db1
+d = 0495be0b0a9d357f6155fac008cec90442200bb842d89292fde38b7256e4117284a60249b3101b3f19f778b680c0d1d7422b84a
+Qx = 11119cd910d4e962f54c9776c9180e7eac2f71cb9748ace4b7dfd2d2b3caef4964c7a55caa9763e008de600b727068eda9b9865
+Qy = 000b48246cfb7c86e9dff4ba77a3a53dbb1cefa168026b8929c42c3b0251fee5746897916e50f07dfe8b57baab7964447a2fea9
+k = 0ad4ab5ecb84118c33a4b06d1a9f5d2c4f1f3dd1cf71af596eea771f851d0371d2d72593c926d7b69b39cdf72931f6bb11d10cb
+R = 0e959201622673d81ca16ed94e9e5be3f38bb8db48f9c09a585aa31ff39f14128d79d604a5f93c80aa961c85bbf99e276937f4d
+S = 083099697856c780936ac01aea5e3a4d9b6e183639cd200464a5cc05232df30ff5220dce4e2af714c580d561b72dc4969166a6a
+
+Msg = e9b2a33906a1079280100039787377c2971c378b92e70a38ab41dc23979d6fb0c41e53a21b37632407adac6f212341cf6af8605b4978c85c9c16960e1674247f1795cd73b99ff28cdca024f5078490513c77114c2f52288f5376872c331151d7b2c08f7794f2c1f9e0d849d32d73636f0aa899988ca561a76f74543b37cbf3a3
+d = 079626354dfc4eeeb51fcf232ee9e6b0130c9bd40f15ed45606bb7faeca8f359e0c3e18bf12769254522fd4077eb24bd5454871
+Qx = 07ad047bb38bde6ae2593e1e41c36b7efbce1e0ad08def9b23d25b7ea9aa336eaf10217df16d32ada4af03dc193d44e6c77e677
+Qy = 0d2b9466ecf321605b9f4f9528124108007203ac32cfdc7cb87e1790ebf4bae497fb87011e0a81068e66a840d29583bb970e24c
+k = 0074548d1a3df580e45babda6096f4c78cd70945ff190d9da463fbb03a511c45d45dd1c46dc0b9521579fb506bf015f8b835680
+R = 09e04e9ffc2cafdefb600cf61e803eb78cb416304210165fa7c93c1bfefb02cd4a255512622d524141de02c2cbd193991dcef67
+S = 01a7960232455f27768acd825b8ef91d4efacc38684d05a900a8512682ce19787033cd08c1f2412b481b88ad02dacc0ddaa0ec2
+
+Msg = 672db3fb8cc8e5f831be700498d3ab3aef14b7548e8011b21351215fb6dfa09460d18f52c02c8815baf396d856a429bb9afd602a10c213af34db80447f4c06ab4bd28873c88eb9639b199042d4b2cb13cc364f734fd4ab7bebede7dd4da63decc0cc1f84e34d760013f66d71641073f16c08078880b67230f2d6c6bfe17d206b
+d = 0ab42bc7d0e3c23f8bcf928e25f9f027b56f270398a1d37bea0ee5426b944a9c9ba6d0d7796899543feedb470f70b2ab148234f
+Qx = 1415fe81100f208ec8afd5e882e5773a0c1d46e44627732900c7e1722cd77b3ae24438a8463bf571fd6bb422d7c583439c07cff
+Qy = 19c3ef3688ed397640e873dcb20cee9755437d0023646d05612e8c360717a2e80e80f2b85860d71f9876f3a68548da7099f601d
+k = 08b44ec25214602de46046b2c94a45f64e9d0903f6148dfedb76a80b8e6314e87bf7dce8e73b14bb274a88fa39136a00537779b
+R = 00ec4c5bc88a959a1234413026700bf5d4287a0263fe75daa16693bf74cb5071a64eb18778da0a31210347aaa33130602f6b597
+S = 0b6c29b9177e89880f3eee3aff204b866020b3bf77d7c31204af383d9770804660711a8579a3f1ffe325f225fc7e7894ecc601f
+
+Msg = d7fd06b89226cfd66671ce5b4b656228c52d986afa7f6f30161680eb0c9cca177992a8a8c40167a64165c518c55f678702125709361b536bd928567c97737bd750d0e2e6e0c00296a6ca565f7c05cc8c54ae7a4e0c334c6a968fc18a959c18ebbd924457701316a4e999fb11084520dac68dc2d69187134c40891af0355ba89b
+d = 07f7aa2216164ba689459ee5d5ca29e70ef75a5b2a4416ab588df1dcb9164330c0b405a9d80c3acc41c19f58e24e17ecbc0fa7b
+Qx = 1decae837c7258ea9d90314ac87c57aa6d49828787054cc068edc1955245271acae72dce5c9cba422bee54f22e11810721c1ed5
+Qy = 024cdc9e1b27e5d4bd024654df000bc9a0181f7c0f4a90572c75e16b679f4362446993f9920e2244527801e8f6b1e9398bd8382
+k = 0463202dff25e6b9c633b60a3edcffc1a22031cff44dc1b0a5769214693ba02038fe5dcfb4a48db7ec49b33068061616daf2fa9
+R = 08c06b72b73dc2655645892447fc0c0f8055838b194e8fad99fc6bd50774e1ed08313eba4141018af33af95a3faa20b69bcc0bb
+S = 0958f104326df6008135bfbaf5c2980cba2833af1b4f04b5918bb51ab0a0df637d6a4af902a5e07db3022c134c72315f25972c2
+
+Msg = 83b7e9d3ec638fef51d2885fff5490c94e2509c126608f82660e5fc523032f3e85d69d9b76af145f6bd916dda35775abbb6d1902bf38880f8b9259822055c5b1bc726c51029972cf7474cf2a812f3251aa71813476bff55598d079f075a40c6c41498bd865ce960c518bef75a873b9d010965f342dc4b35ef5c5972efe6fdd18
+d = 021d84f070c6823a70f1a74225a472118c93ce9dc509aa6064051ca4574939dcfa96be862069424bdf1a23f62f2868326422e64
+Qx = 0f568f018b0dc4400bca3e9e4b0e5bd5245f15dc7acbcf4360b0be2ea5abbb87a3cd76aa653d32858438051cbefbcc4feee6f6b
+Qy = 1fdf1e1bd7a2d3825df14f8bf8d5de825095663c3014f2eeedb9bed3c3416d56f805b623f40b847090d6b4b3bd5abc98ea55e48
+k = 03344dc1cd950a9c3d039b6fb6af8c5745395d2a3343d86dc6670580e331d59f6c0034367a6df52423a625d70292893961ceddc
+R = 0fb010ba41d651fcc854762fa1437262eadfcabb95b9502a40b50f20cb34fa19ec570dad2e0521809ecdb2bff3f4e7055c02bec
+S = 05a9c2dc0c1f946ce33f2f434c156c236b09098365a7f31e238b4685e7cd8c86a0b2455e5c83907167c1324bbb37e66e0b2768d
+
+Msg = c62c7bcc860f0e175128e1127dacf935ce62ae794cc4a0ce7966bceb023ac0498641d7281fbc86f9ef470bbc77f608f83f8d0dd6299cf08f2cdacc7a9642e4246df131820220e5c05d0dbfceda7f16b86add4793e9b6244d96b5c07cfa23574ceb43e8e8b5483192a92b301aa3b37702b8f94f0129d8af1617896b34990c9b02
+d = 0b6645344d17528968c719091b6e2072388881dc10bdb4c7fbf41906cadf3699b30f9c1dbfb4796d009480664e6276c0359e5db
+Qx = 0b164b075b80fc8b8ec785d5c2ef84d49f2f4d276546c9cf2e17ea4d367828e9aaab985c5cd0882204e293dba0359d47d9bdc05
+Qy = 0a0c61f181d5d06ff20d0c41cf6d6cf7fea860075cdcbbab2efa0950e2276dafd4258a39c0fe4c45f3c04f76efa7d41392b4d34
+k = 0c497c621c5cd230fb1e4a4cb3af1cc9d8edf4af5c4af7f15c4ad0a8835b54de52d83bdb3433808a67628912a85c5d00aa222c9
+R = 00b22e5773aca4d97d2da846c3947bf9cf2474101a6f0d39d31629a6aa2a4c3a77076a671e37aeb4cee0a94e82e914c8c553e04
+S = 06ccd79ab93e344e6f112c1e4a39e8505a2aaf5cf85595cadc6ddd1afb0b1583d9334cf1c48f26e5baa38e05b6b52f9f12c141f
+
+Msg = b5bf38fd9e822925254418475a1ce762a94e336f12b156b1625a4574fee11ee472d537ef94b4a4b1c0a73b0140d0b818cd06636653e6c07f0f100118242a7703756f1cb1119b3477c4ced99cf45e07e83b7f2749c1a5f8d8c9272d221fe17f7c6a5fb0f8a16af46f232ce406aaf565c6b2766a2f6528c82e74fa1c0a7fcfd49e
+d = 0f8c2f770cf5f8e1f900e996ecdcd84fcff5cd959777fd005d721a419123221a3237e39834b270d37752470deaa6cea023c5058
+Qx = 1f861984fa06f15b801216a1c33672cff43740f0f736b4f4abed5656a1bee33a2aec431680942f2b0b0dce9a9196b49263fe183
+Qy = 18633f4e057bb6d70a434f919b9ce4b7d9e61fbf46c1d9638100d77881755fe9829a69d696d555b1a26e25ac1a1c27b40f909a2
+k = 0bdd99022dd964306955c57b226aef036527eca481622618fa7395f53e60aa95a275f1f2d6e7354d8b55d3e83c85819e818199d
+R = 02f1330f41a86c09205004215c24f42fe582da189906fb23fbcc52136fcb4970a33b896113eeabcec8151cf3b150eaf1ec2dd88
+S = 0439507edbd36ebe4fa5df34d220c1441e1a4175c9b0373fc85669facebb5bda7a4b415c269a7add207b461525c6cc94b7f7b22
+
+Msg = 6d3474770933ec01b76be789304b6fda423b12a0ae8c87a5ea8d7ee9f71300f39440e1c7f5aa4b47c1a8628cfc3a490b15ef292a741344f40a8fcdd02cf3863bf3e32d53031f503703deab17fc52b3d4032f4e237dcc27231b85d3fd60b49ed7ee40c3344948d87c3f47564d20a11d50e4e520bd16c8701694fc70901a5da625
+d = 0144adae951fe897d5812ee4a16c0be4c86c5e57e615c398f5768a1223a9be20fa82ceccf8a16a31432bbfd17e594a4cd8a6a07
+Qx = 0bce072255f7cbaf565f82db122e9c582ffcfbefadab6d79680b2506792028b200ca7732a98322c290916c66c8a8ef77df6a2e5
+Qy = 1b4b6f65e678223bdbe5f8ecb68573ae3d7f111dac37d4fe3c0eb768c461187fc5859b13452381fe676257aa445bc7f38b4919d
+k = 0128c12479b7f0630374880b214aa26e4e8626deca57148a6c6a0e37a97e89da8acbadbbfe7db28a0c5bd17303e1342af711f25
+R = 0a95124ec95e35747fb568e6659ff31867a4cb7c00985b36584201d1bac0775653e0a8b54cd9a9067ab3de434bc2cdf29ae287b
+S = 0257e5410a6f0bd94fb3b5b10500fb45b501a3734f0c718035a9a1516d2f88e10d1e38b70c791028e262e0c3128cb84e6064ea3
+
+Msg = 92ba7aaf71f625f7a2e024058dc8739da3567c306da4a812ed9e1542b7d1e982c16082166a59720203f4524c3bd463a662c26a82ec7b4376545206e650eed0d3dd7909dfe3810981393070d15c45dc4a75a8c5bdeba533cad1ec34fd20466a61e4cde3b25af9a80a9a54afdd7de1cf2a74ba32d4ea0082a037775413c61a8d1f
+d = 0a51f065fb32c55bf4ff6f18ba9d488d35d9f8da593adb0ab1632533284e0adc43ccdbda9d9507b9862ac63b5ae7b0f78b479bb
+Qx = 080e2f7ef17a11ae66172cf1c18eab12aca4c2ae06b8106aa1066677a93538e3dca0626e836249eb884a382c3b726736565c3c3
+Qy = 1e98d37a17ea736ae58eab093fa7dce3f10791ee9ef5ec00bfb27bf3c705dd633badc94642c385dcc276f9b1fd5e01dd76ce944
+k = 0d5cf7b3d28459db8dd69c314f6464f770c31f239a12656368c84c64693f23733661081d20dca9bec9c9659a8124b57a71ffd55
+R = 072ba8c1b4bfeca62e96a5649e851e9a311d7685603a11c1c299f5ed8605adaf27cae656cd31335a7ae363cbae5dc7a39512c1b
+S = 01bb9819d25a211548461de4ff973ffbf475230baa161558d9cb7ee6f2e682dad21a465fc2ae058121224f8680296d30e3692cc
+
+Msg = b3fb9e48c333201324755a81f3ae5d4f0e2ae7cd24238fcc66d858e3aeb1ee03328660d6399676eb1b7d8285ba571e214d935bb45516fccfab57b8eb4c3d5f1d7357c768eb7b5e7b5710f599614bd4e92706eaba31f8a5e7e57af7ed13066af50b4540ccdc126b677789920cef8543907f0ba9dc92aae343d3425bd784ef483d
+d = 095351c0bc07acfabe6477fe85f97eab520dc96bdd58b44b036328ceadaa56a1904d2217c5fd25155ff2aaf9005a3e2687fec81
+Qx = 1c1311230cfdf5824323448c68ead5e5885ba540a21ff90b951f85d84d78e26da035bfd99341b5901e1ebb18648a8dbb996fc9d
+Qy = 017a037929496e560cd1c936d9eb15f79fbff737201dd880a69dfec31209faf5bd2846e3e664c668ad3d6500c5ed620f1bcc970
+k = 02234bafb54cad0d0d51f4b8508dbc8d014c303d90d21bc3f749ed7acc42f0335c5ab6d60002d3bb57cf07018e9c13b92c0a39f
+R = 04d0609f06320d69870a3e66f19cd46a2e0e3e13fb8b7785163a7b567bf2c0f437b4e30cc67da288a3b34ce3110f6d87affe0f5
+S = 06c46d0248f7c309c1e5b80ac4b1459bf897e42f8f037031f5bbce0fde50af50cfdc4f60d5ad3d1af152298cfe77dcab287874d
+
+Msg = 9ec5f7d65082264b8a50be772c44277a73ed19199eb275fe5976f9799d8629fcb4a59a8d55074cd2eb2a0e02062d3f7cdeb05e62931a24fd1aaf14c257944d1b42eebd52726d6fe281211b39038e52baae077ea4df89675d860d6ba5a0f998d049614201b872e134367acc90066ac602e478ac3e43c3ddf4b0ca0aac1a68591a
+d = 050245c1682344fef23bd549ac8d1e8e44b2840c43eec1cecd33daa4e9ef6b53f496104d7432e14248682cfd6f5b4853b65adac
+Qx = 0d2f8fe524b2108e375c9603598b555d6c4c7724c7d11039178037b3a4dc82b66c3aeffcccd89cc34dc2b2f6695892323bdd805
+Qy = 1f98df95fc1837ec4d5239cf55e97d6b489b0a8d7bf12c1ccf95f689ad23e46dcf20dbb531f5179e754f0c29c8757a1dc67493b
+k = 0c683f98253406c6587d87c57991fe5caa3f43b451875859feeb81176b732f1c1eed0ee44d1905d41922878617e03dac53562a7
+R = 00cdc9bc7d670a1b6794fd7da82d2ad1a0e92b82ae32656ddec3aca4de75f407f20fe782daa0004317fa3f12cefc48518298d5d
+S = 03ee7c75810c2c05946b53e2f24feaa697af35174402c069b9fb03d89d73964c997eca4a5d6f9482cb23c8ce337a374ffc3e186
+
+Msg = 61d657bf472676301503f6784b7286fb39fb4186bb88abf1edacb4a2693d0a1e2b77bbf2758c84f2cbfd1753e20841b1cd4b456400d53f4d686e666943f9b6ffcdb77f510be97536e9698fc84ae347d483bc8984548d1cf86b9b40d360f9c0dc5bd1c55868e26fce1460ba94ef5e94eb63c9f0776a0f446c0cfd4106d9f36352
+d = 08d3b0277f0e9fe54581d3a9499ccd7f015c08339591326859af969d2a26284e3b3beac4a0b74d324ce5cb5f38c7995e4e3a41f
+Qx = 0ae18564ac04b54769e17df84aa54903df58decb870591dad73dbd712693d901f3f9ad43a71f23b77705de2b4ec1c3bc616356f
+Qy = 19810f92e80560979ac6e72bee505dcdef15b4146185d2f8f5a955a4555523d982c34bbfc1326024410dbad3349e4c4e01c242d
+k = 0e52dea77fc59298cb06fb1401d11c662a04500f0470965c4cfaded13b339bde52f4fa04c76a955faac16784f443b1ad9dfa0bc
+R = 00c917d487d2aae1651d76147de2a706a01c8b3d223afde7d20c9dd77cc2329bd3e0e4fc01255b7c4ed1baae7d26667bc2e9ec6
+S = 0058c766fd514a405de91a4b9e99fc0b0146d954dc2e2decc2f3f066d0fe192832ad37a940949ca4e9abae0602248b3b56100ce
+
+
+[B-571,SHA-224]
+
+Msg = 8e14f713a2c427b1f79491033994f76acbead614d12e73ac6f3f518f2052a10c1273aabe628ab38e0d3d5f8ff254802e9f44a51367bf80325b6fc39d907a37f731372864747b10749ea5cb3d3a83da39c21a7b02885a8c1770e4397cedc958e4baa21d5007569dc9dd1e45d2181709d900a394454090badbd0cd9c2cd2369aad
+d = 0f42afce7f7b3d45f3f925ab29fc3882a89c9f585177887584703cf8bd8fc572e677adfa55b402446fe1e90dc855358d92c3267c35be9674b40c2ad5ce8dbe6a533c44b0ad8d2b2
+Qx = 63dbcfc2d9171a7cc1835c1f56ecadcb59aa6d5852fde264ab25603f06817a20f2787446445be8b2ba05c70fa25d9b9e34d5374febffeb536facd3da52d43d69fa7af4d4792c792
+Qy = 7686e0629de47916af19f9013f65fa3b5f9d196916cab2f765aff31adb5a959515e83fe3e00e91843c532041ba15f047e978bf2fc69627bb5cd7f3ecd74cdf1a8d623c1efd23fc0
+k = 3fae665eb7a54f51c522ad5721d9e2648f13f3d84e3d64c8148d59c662872b5cb7d911c27bf45884f2ef717d72bd0569d9901f2308d9a68d128c042effea148cc963a8252f1426e
+R = 1df705ef13ce900ed61babed02e121dacd55a881ae32bd4f834fa8e362d059223b29ff3db835fa2b2db8fdb98c21dda5ef744cf24d0a798f501afa3a720a238ebd4fe3976a179b8
+S = 1b1e98db422fd48f1dfa049f38865f8bf9ec5618fdbfb50f21cc838051a1493e4b1e4f9ea81156481e5fd84124fbab740421173862c63920e3a833aebf0762e7b5b39a1591d27c8
+
+Msg = 38b60d27ff08fb191811036dbfd5b39e1cc3427ff70efb67c851e9cb407f9fac6f348d289df98d055eec73299fcac068bd0fd9ffa3c5d244659e4f714a58d79f6727f323a7ee26369000e90e34e106f99f5ae2ae1b64ee89e5a1d304ef20c071a7773e9b977ed3d49f467d300a881c8371041394910f9c366942449045568f01
+d = 2f36613043cbf53ad36e2b38998bb867503359ae082d07d040e5a10a43e06ba9c91e7c73308e41e2391b65e634f83b162cbdf4e7a44ad818fb93a978af00f06be06731d8c5886c6
+Qx = 0fe1afd356670e1dc6bc195f9513f1dc6b03017416b5252c7b56153da538422e557d9918298ba6c78283efa0288c0ac61298846a6f8adf74df21747cbe7c18a2b825a330e843cd8
+Qy = 18b7659f0a7e8e7ae5d636ea4d1d5f3a1f846d4bf3dfbd96c6ae874354db6faedf02f75c4d1d8bd6a3b61e70ce58e38ea5de8cc16828f87a0667614f6640a3023b7f4aa93fba577
+k = 3fe351ff6ddf50752f7dfd8e5a72c9faad77dbea303fd97dc939eaad3aa7fed466fc8939a7a6bb7abee63455284a5338e59dc067236dd699bdeeae1424d993a9c76fb2fe9595423
+R = 04a0e13a9fde9f2fef417199f8584d0f60b2f04aa6b7524cd2a2826d63043b2188ca977c9567fc1ff292ed480dabc01589db8734c15aadb4ff54a552a7d9e66829fec1dc919dae6
+S = 01bc7d2c4ca9300d7a3001755ef25231d2852a7b9a3e91baf21f2a2bd2ff305be8a9de1d1bcd7bd9eac4ce12ecf8a91c0a409726085382fb8d2428adf1b42b37b50c9e8e0535d7e
+
+Msg = 21709eeaf9e1953822294a478dfacfb205fc25f447a73a76a32601c00784cbf2f9ebd41c22721d70cdb3842dcaff4a4f208d41c0816990e421cc4b8538ac2f347cdd0aa2a39f1aa26ace8cb6a606b23f6244894d4594a0f6a5b8f6a695fd66e1a41e2eb6a377017177fec56bb58c837e311cd04c5b50575faee32606b9636ec1
+d = 2e74948c46930cbcd9dbe2325539c7dfdd910f309fd610e6599d425aad9ae230a8d4681970a14f2a71fd08030d0a40ff40dade7de1b06a80441bbf7e2fcf1809cff39c7ef88bf9f
+Qx = 1b75f2d281592c288fe6d5479a4e21ef626471819850cbbdf814593bae7e6ce2a35a978aea354649d979f161543fd4c12dae0efcdc2d95e82ae5874b9c04a2143535097b8a17c68
+Qy = 0c7160c2efa3aea1d18afc1a00b47209dfc750a5317ddebff04bc4d181f238d339a7690c24e55be2cb0c01719d34ec986a07727f2e412aa72434efef4d64ecf7c16e2e75ebd7ad8
+k = 0d3ae3d8e5e01ad838a7cc9a4d9b3e41eaf9894aed1d1ba597458391d4a2ae38c5d6efdb4d91761a415812d77fd9ceaebbf1ad49c282e693d71d89f0e2d1bbd94698a47f1f30890
+R = 1e2e9e2633885c85f70208de30ae9b7f72950e2de980607f6d0e73fc1fb2a4a8afc6388206c11b081540bb528a94e5386ce77a2d5c7830fca19223d57c1efe7ac488e69ae07e660
+S = 1250d1b920324919ef81865513db461409f6f8ad82f658dbfccfae4425906da306ba10cac84cf5379b6c1d8b252f3c6f86439413c617deadfad38a234bf2b0050fdabf7719bcc9e
+
+Msg = 3a131fabf3dc97334f212fce41c44300440d16de1d6060450875f7276f53c026e2a511681b5a8d75fc0d578546339542833145f7ee13c708df33e584445a75a5538829286480d339be7c777c03c998a6d3f037b25799ab2d541021502a0b02a9b9c337a8b176c4f30e5b186485a6103b1d1563ad4ae73ca806a5e4daa92e9100
+d = 1b5fab1d36f6f6d559f65d8b01edba610620fc3a38307b1fb1c5bd63e7ffbd4a9098cb8bdf50975a873f5d047ee2b627b090897a7fb5f56d3f4a0f3528179e7c969926fc0d3b0e5
+Qx = 5eb8c5a2bfc86aa9a82830d665296f74aeffa9c5b38750d0ff51d01c2dd0fb6f2209f8ba89ff07297ab9b1b06168757f48cb6eee618a7b44f1b3902187c33208288f35a06665920
+Qy = 5334c203f4ee44fdfd5f99686b18696b3433f203dd148324dcfaa03a0a250cf606486ef11ebcc1ed1839a76ad70909d835a4b30a014104a6ecbb284b33f50bfec33d8b5ede85ac5
+k = 243889e7ad32076a3ea436356eb572c1b4ae402d0218d3ee43927eca0b4fc21a19926eea35c37f09de4766f54e6079c34fb3c174afb953be1aac46d675bd300e717dfc2d0c3fae7
+R = 1d87b52dde9f502f02a502e7a331ca6dfc6204922fb94886efbe3013446d08240f6dba1210a76eaf804562aa92a14d220d59b6310d6caea0274a5e1e8aa3c6b57f239191a71fe3d
+S = 2a5342df6908841b719f80ff905cee0ec3fd8be46396922c3f2f142393714b97128e083907a3a2343f0cf9aac73313279ed29eb44017e2a1cdd0fc86e4b7c536e9f7eb1bbd192a7
+
+Msg = 679d85a762f2574b0b31b516270b7d33d5e166c83e91a0f48e0f3db20b52f42f9e6ee9648cf58267ffe3b713723cf3df52b5fab5c14db1e7189f7cb7170bc6ec7cc71946745e152b39180f828688a5b6c0b2957ab94283b90052a3c6e36843c391aa8810f9253b639a8d5a69aec10070603ad7a99dcedb544858d057a1d66b89
+d = 383e70c71b431eedd4574f65d01fb0304f7744d668408c847f7899eae44770a7f3243109740f177d7146a27748886b7b77ecf3792b512e8d8e37c3bf4ecef2b1253df7066498f01
+Qx = 769dd91fad550980225877d98f7c86963c88be141f91f7a3f1607e0cc6dab767aaa6ceabaf46b65a7c80b6a494b0dac1da5d2fc8c5b07ef7085ed1bbdf4273da3665a6517ea1e5a
+Qy = 282fb94b4726472248f01ee43607f7ef969446313e849998fbf0058c8ad5e24457006b84fc0460b74d86ca281caa174e69fbb68673e1d28ccba17eae045eabc1839870831246a14
+k = 336909099a1540e6f69172d55e0c88a1afa99808005bf09cc803ae1e4e4fbeac2f77f984bddb482f1f13e4430e25e36962b1a4cae00f1fcd7f2c7a17372c91673d8286f9829bbdc
+R = 290055d578012a5b7d88fe2f70581a0fff976756b4581875cf5db07e01f09c0bdf6ab70ffb5839567583d53c68e31a27c3fde12bd4f1e1315af2f742746277b1fb1349141ed3043
+S = 1480c63c8b90c7b51e092597fd8391a237b07f0ff7dbf615e6bdddd5aa880db29c9b9add5bde7e0e81d9a37f852c26f21d750cd2f95520d16da7404c2c3feee1489aff09f298d7f
+
+Msg = 236152ad31ce2ffc0dead3c142cf6c770672cd2e75af4a82fda1a72e1c775cec9b481c6f3e411644df7e7ee901c501405620af4b6e9667dfd46091788daa95ef2c6c9f5c240c06b15cb0df51f5f058d8a7934bd7845f007a35f99fa97200b20f3b5b14fbf1e372507f3b2f377e8d07d30fd3e222f398f26d8f428e320327f901
+d = 02261d4ead21f02fab19bbb0da8c272286704c8f0c6842ba47ded121e5cddef79fb34e6b9694f725ca502949faecfb21e3cc062a2b4c654bd542d9a1fe8d97bdd0905c510aa0999
+Qx = 3ef03980ea9b754b655948da63469fe526ff0ba2c0f572981d02f5693bff620b55b8e9e9f9d553a78a0138072369775c7976f028631e65887cbed62fb447c9f41da86022f4b41ef
+Qy = 4446eed90f2716a7aedefa1385db9f5f803434517fcd80571adc9b7f086c9787b76306380a375668b05fbed30922746fecc0cc16f189dddab676516ed1fe4d02855a34a90975389
+k = 0b309f6c53dee8a8956358df45e72126ec76266d38babff185d4db1d449c8fa9baa4b0651af5f5b0aa70dee3dd55623060097e2f94ed12636961a7c0744b38f2f137bca239f974b
+R = 2b42395206ae79bd9df1c729856101ec3c4a719616701f836c9d69b542b59ce973d91951853f89a0717abd4b929bc69e59cc379c941349dfb4f98d49f9dff572c614242fd370e56
+S = 1ecad482a8eadec6800a9d876a382125eafaa7bbd950fe5f0588126764126eb1b384424015c52ed6a335668506f25124aa78d98ec5739fe282af0c143c07da0fca53b9733e159b8
+
+Msg = ba3f02c4847fae035d747db246fe4e82fb9224ff9cf568a6ae548f5dc2befb2079541d2cf9aaa6b18c281a05e7ddfcdbcefb25f41dd91cb3092b3343e16985e91c912215cd99ae4a099baf628e33a7b277e3c36a13aaef85418fca99f64d73b789f23ecbb76c3095ade0a5f7f34836a98c5be933b44a94a2eaa3f99b1d8e7937
+d = 316c78f289e1860bb623082be9d9238b88e38c5e978a868bb90f776235bdff4eff591877b7f350cf14c40356922b2b6aa51d64990360b2b0e44d6941b5dd9492b4f4e1f42ca163a
+Qx = 6f4137a2c63b6b79138027464135021b034f97bcb2493943df6be844f1657a97632ac80541a3b43ccc828789517efdd9f86ba171c1262a07a6b337bdb0c8d5f018302a8046a1a8c
+Qy = 425cf553554d18f6cc97f0caca2a7eebbf266d57030014273f701562d5b1444240b9d22060ac9bebb37deec393cebdad21ec7f13fe5c7f1752b4261cc2feddeb737284a6eec3663
+k = 1e0321344bf364f1ede39a49c8051f36875ad78e4b080ece9088111739041b121f3f334c6e923777fd716a52be669d6e45f381da11262fb4d09ad66dea74ca115838e19fe94b7f9
+R = 04f24ec978c52ffc7675a09334a895e044eb8eaf04d26c094d7607b77ac4168a02a972f577880a0d0c73f218815e3a7a70c91c50734c08d374a15fb42fd13367dbbe08fe9c2d4b5
+S = 060740270df0e1fdfb8e829c9601b9901223b19d07e9d7d422b9bade88a50fd6d4ec96842afc45900a0107ce85ea6d083d66ae202dba3a32e50c7c3af951cac7acdc6f4c406740b
+
+Msg = 6d0372b40559e075af56af853cbe18ba2d471b0fc8917764abcc69102b03d5bbe1fc12458215be66409c26c89f67c72a8933677a07f88993af6918acb074fa915fe883b24bc3d191ff1b08852f07eda98977e70eba072d8bf189cd545230f59559ac05f1fa3f4e65886d0bc274a6e02e2399812b2bf91abae81e21279c5de996
+d = 2c1bc13f8320d97a82f3d9354e195481902214e16a4fd89332a0499208e91d50e5cabeb4927ba030cb42f5bc53b10f500fa646a8c88508cb0d63ebfce5c4bd574c527d686c735ce
+Qx = 2210791ca48aafed20de84ef9896a9c7584081f850b75884908c7b3dccc94e221401a6ffd982f292a9d5f9c1d066ed493da948ac7e93977dabd7b820bfc0fd21cd8d99c072bb69c
+Qy = 33574c6ce7da749ceb480b4e00bb1a58203bbbca5c16923992cc9767aba5483e4d46ed39e71000a1fe920a4c1c211a14e63ace03635a2d77e72808e0664334890b819b3caff64a3
+k = 2e3db2d82c4b9de2bc0dd0a93c1c5b385f75ad03d0da527a034da2876b42e43cd88dc64833efef54af902d85c568bb8e71684bb16b28c32d80bb3e9911cb1b74be6ec520d99b381
+R = 065f4715e87ca3541ea695878ed5ccb7d2ea6eed5d6fc5ec29f9aa8deb4001cc7c06185d6ab2dde4347344d44f8300a1e92513af4690d713762336d2e6a94d3324a224f06eeadeb
+S = 20104e0767530ce2f4351af4977b52339f34d13e458de0482bcd58ab38ee041c9adc7b05650260d919b2648e2f820407fd60a8d6b4b991b86eaf29c2c4d12d3b0b45cac2ab22c5a
+
+Msg = bbfe66c82bc060bd14fd0e40769d9b3a026eb447550dd9f118c30d8448f725f8366edef042447962ba7f7f833b9e9094d0ff600714697e632626e7d12a592e040bdcee166dcda93952323191021bd12f3b1647d0f25a41739994659dcbb19333ca30f46f539c6f0a5c354cda8969a1eda572a309950c84c7607eb8ac20163912
+d = 13bd80eafa67663e75d7ae139bf285d2b9f1e03d8e32153c73e26d06e86d7acad22bde9f121a3f1ea674dcc1fe67bc7f5398d5e92555056bc046a02b0ba86c2a0dfe32e91add5b6
+Qx = 4c01fef7f2fd8ee61726af1a2d046c7ac67716403b99e021082e96d733368c6c64d046986fb01a6b55cc930517762387eb2fa4a8eda23c700d88065bced8595188760170881a329
+Qy = 189bfdc8e7a710522ab5416182c9579ca255c5009e6ee6604ab033c1388639c0f7aad84642290954db9f4f7fbffd17481eabed38151160457d68ebdfd8695b5035e4e6e06532c0d
+k = 3c5868345c5314aad5ed3a74488a85b2f049396022cdd1de855a0b33c2877f72e871805af3ed8fd7e7a392c4ff63acac6a6f0c431ce7af680984e8c81d0350abe491a01f0f9268f
+R = 0c7e96b9e9a5935ccd51b901aadab6e01ebde44f57e6f0b84e7b58ab4f62ffc0f3f3f980665c581ee3de233ee49d11599529348f1ad3d362837c041cf98192bb324f577e973e1c7
+S = 2226922271fe8307bf597742618ea9c1c271c22c25b49aaa7c9292a81ecce2a55250415ea2ec8ffec54bf0508e64426cb9cd7177265fecc40e056e96cab661485e789f0c435b72b
+
+Msg = b35e9bf686717ce3b16a59963a32a2116130453b161a4e7ceb27b755856add836d779696edcaee3b5c986523891c8836109d431e55c23afbca022437ad19e6777efabb6da3bba1f5f44f905395b4cc7c9210590fd38da621582d059598e5e4569e904358e0dfc0dbfda4ce75538aa97480912852bccd433a9b96c9c66e9597d2
+d = 30834b0a4284097cdda2ada6947c6c281f7290a49b56becefea1e2788ea3ef78fb96807633c47c25138341768b241164ce0d42f7301728b928be2c047f2eb60fc2f844ab77306d2
+Qx = 03a21f0d8e01a64b235cc455c291e3fec8de12682f05544de207d910c7c24c4cd56f3354500d994380ebaa0b49a7604c6233a9aa24934c550c0e609f65fd4073cd6c1ee4170d77e
+Qy = 67c83513e4acbdeb8343b3add40261edbf7c8fe0af7417264830edabfc40200283b92484630741378b997c3f8bed7285decc6ef8633aa804b3846d3b4517e5ad836dbb1df475818
+k = 0031afb24fbc52b01480754837cd84a5165d5f2ad1a1d572b92ab546c049413806f0f5239a77c751af4d57a84786ed1c11bc76123a82e7db3c0495b2fdc5fb9c8720eb7afb640c1
+R = 07a222cddfaea617f1190a0bd88af4d1983d2543dfba25c5036fe24529bbe2e382de89dc1e36c1f6df59c8291d1c4277198084902e5619b64128c265bcf03b7d8cd6b663c225f11
+S = 1ca84c146ebbd16300b813621d503d8c754e4b11446d5ee31cbebc71f4b85ed09c5c94bbdfc3570e8882ef790393234c5ee9e52f7d5b74ff4171d930af817eafc40ef203a1ce613
+
+Msg = 57b5ae7e95c638b258d1e09b3fcb4341e203f5706862e199b103c8fdac72cbc5155e5cf8b300a0b3fb0ce1f897c45f7aefcc528182f73dd450cd84d5fe9eadff3f704dc2a01b4e847c22df430efd1c66b0199f3e5b59348af5386962a5ef25204fd230b54d58d7fae801c086f8f405d3d0aa7a9a9da15c22b868817cd897d853
+d = 0c81a79ced1eaaafc31b69a40d9939f4e484d625db6364a8e589b6b4d336d458b44287ea6c6aa7661113fc07806b147ff98216fa0c08708dc9d651821b922741deda522b4e436ad
+Qx = 25f9b767b8796466c1cc8a1fe6286d591c04a0d115133fc7910640032b898a5c86547f57794e5aac0148996151d3ecbe0d5939dbff5722679ecff378e3f21bbf1354b1eb294d1a3
+Qy = 074c2b91ef3472e60426d2fe182ccc678aa0abb8dda15a428e4f6f1ac401b015b2b7d83535a0a92770cff7666659e1cd33941bea1168cffde82db0ea83668c2d387e6f4bdf28cc5
+k = 27b407a29553203b829a87eb25d6d140e41184634ae1c64c6ec38e9012d0b06a1f4ad9877d7ac4236a22145095990233e6c102a0052ba18cf6e47e289cce4f2ca21514d8868bd68
+R = 02416e11fe2f8e4738ecff1710dc827f4e03c8e7f04a4f52e755f0c1676abbd122eb9751ec1fdf6c7ba04b4e29f8dee52bff7e9e726e28cb3de6f9abf2dbf58c0519ccc7d70f076
+S = 0b96f107a26097a468c1d410bf90e223cd72c5ec98d4ee4ec2e32259d7670d7e7689e62d36549086139f6111884530e20f908d7be1edab75180c81a70ece341f7eda6e4a43a5ad3
+
+Msg = daebfef74b452f039c999ba0528be3bd9e16deb5f46f6eae87b63db8b89952c949fd7db08311871eb2596865eed107aa065f030226ea675ee3256c31a3f85ddf4c21760582144e07af208f33c5f47cc026db5403186a65a47940691ea2d74ffb1245676260ef5717dd879d8b5b72d96f87fef5f762d4fd17454cb5ed83d8a11f
+d = 2f24670c0f77d2ca0266a743023d2c7413d56d0b5ec77b454ac59087efc4ea4d46179e10278e4ba416ffd8c3f9786ed202faf8251c0ef5a9ea5371fbb35b7afe3d15a9cb4bad975
+Qx = 2da72b8ae64c5ee717c33758ec26153a342936f9d41dcbb136590e1303b0e220ee84c8a06b83d4d9fc924b8808de94dbd780cc8243bc4448efd27dfaa1572aae6abe574be664939
+Qy = 3b3a95d962c48a81c48713247801e4ee630ec7956c9989023ba16f02f5bd1ef2edcdd1c8d314be933225c64b7f8a80542b209b944e1f3fab95795ffa134e7e28e82307dc62c2962
+k = 2bbb9abd2732994011c8d294c5342e8b1f7f3c1f5718187e9f75832604b43bf75abad5ddc85e8d92cdc42656cc9f3349afad3f9022ccbb4937d9ffa9cf48314b604e82bda13475e
+R = 3986059f2e096a3675215698e23b53f471c578891f6d721a34a0d231d16348d5bf9853c79c4f4aa94642ad06cb7bfd11f724800cb5477636b6fc0586fb6efb8eb9bbef62329a884
+S = 2beda064eb3ffa1c3b5336613704b3bc3d4ff7b0e977df16477c7e33d480d678804bbdc08088186fbc4764be398a26c13f88bdd23e844be0d7ce598bb87c1b3430da02ae96b3767
+
+Msg = 62af0493ae79d71b552c4647d1fb7ab2f282a91cd44aebd8ef344dfd77b521b0c0a3f72e4513c8ecc0e4b84efef3df9482a07ccc1b740c571c5e69cb913740a792aa231b9dc87edfb72bac188293c6c6e788cb3dff32e8f483f8f34e21ee7efec71302cc3bdbfa47908a135f6ef3ff179dcef26d1a3987f7be967a6c0f799b0c
+d = 20985f2c6fe3ea04bdbab66a8b6167e5969c073b9d53cf3c77cebbf73f4dbf75e601620ec9c3107bf3fbfc6c79f8f063409bf8fe1d14b19e323d857e23dc05157d270c7514137e4
+Qx = 010712d50ba7752962b140cfb943d9e8dc3bfa497bfe81c42606f4da5157656fe2ba5cfd33ddffa0f27fabef8e267688943514df45e642ee0454e05b49f7c00f5785777897d225b
+Qy = 1a2c7db6595c6d4c55110210c564cf102739760e7f5a29706fcb2515d99ca00949d5b4f291716d0aa1e3a47efb9632410f60e2fee1ada47171f902f632bee85da75c7f3c895c24e
+k = 2f26eaba6452e687af452d5e1208fa011e4c84ada92a38f0a204a254641c23ffe1c184fa8bfaff047db590ab40accda408717e4f30811b75cf3a5877ef99279476ab924d92565bf
+R = 1280adcac1c79352635f4165f9c5c1b6e1e6e33bd74d781773f483f637462f80340f8d22cb24c9db5e49ace95a676df3dde53c8721f672006382ff806410bfcdbceda50e53285e6
+S = 07dd52973ef30dbd480047732622fb1b695fe3cfd080264d2aa30a6ff3dab4ab362518c4f3de4fae042fce78c0c8fa0e763eb187eae2ff8f2e79b3f38cc3c1aea897e1f28b71a19
+
+Msg = 566f17851951777ebea3f8285610cd8ee5f882a68e7a4205e6fc9e2d66d210ee2505ee73d6503169f7b903012d43e7e99efa493a8e6ef926b16b9ad8f52156840ab561fc6b680120a88714fd66d1d0742189bf06c155e1138ee5314707173f7352e2cea0fc26e1553643f2490428718e44afd8372cbb7bf5b88234318ebf4355
+d = 2b3d641607b8a141f876f6d285ee46aea543880e772dadd5dd83d595b9643191d9597218e1d6adb081df133304037bcd2c05c24a54e6c4cca64fb2cc4569d6882315360059496d8
+Qx = 42f2bffe25142ac6c1af26643b0f1c317b34950a8a0f112a0cd4ea4131303674328e0bed5d9bc7ffcbb9712387cf67129365b4fa8a9e785b787c170463b24f6a7962c1e003c8732
+Qy = 070962ac4d3220f367f18caa7ceaadcb82fdba45cd2c034a97aab71f7f7546c09736cb080c10d9a95a5f984aa4a3ed32d22636a7b3d5ab29c86d85db59f6f17ba29eb220bb141b5
+k = 23d7021f5376e7b11be07288a0e47b4326c026df80d7e08c9a0fff11deccdadd479dad503ef2d4fa3f0ab2aada604b57fa7e09dbf5c8d493070b5faebb27cf68ad0b78bb6f3a9aa
+R = 3059720e7a2dfff03789e7a514f75f2af5ed18cf1568fa2a5354dcddc9d3c7a90605e9b9a3d0d6fbfebddd615cdd52845ff922873079e06c4f349f7798410ee18e0c69045193668
+S = 1cc40209692cf5f8ed8b82372c95033e4199d378a28b9edcba516820ba21af1bcf5c5df2ef4146b91fd37dff89ec8f9962eecce5c5e285d76a5f03eaf99fa132e98cc40ad66c296
+
+Msg = 25155825fc4f9a1c4dd1db837008e7e2594a879052431f5bfc76d0d2565b8fa726008befaeddceef73f3c60fa2cdf6d9a70e56d27210bd013034b38861ae49640ef208d3fe294ac4362f8eea44f58af3af8a9167a36b5acafb7ec95652d5885a0e08067ce1dfbb45a0c89ad1acb53eb404bf88fa5c3c463a0f912b5a2522a0d9
+d = 1afeb5ca87c81025ddf09c2b2c5ee22ba0105c0e619b67a324467485bd839030d149fee44d8bac6f5902a1245a50c3437046b7c89a84116b2147cddc645b6d2fd24d68e8d53bf5b
+Qx = 119c46988a79e3ae8833ef096b0a1e2886c4b114ccfe881886859abc031df2b1e75818c82be8c5abafcbc5d7b3b8344e98e3f413d737938845e6eab5aec7e507f7baf0d339a362f
+Qy = 3190912dfb5a1a31fbbbb50784b18051489a3cc0f44c42c71d3a54886ecf40507c3240395e8ced37b5253b915fdedd38f75bb26df2a0a8edba865f898a15f2d96f632f7f0638864
+k = 1facccc127c856db1994c4d9e9c76de6bffff81a88d7aa0ca1645e250e07674fba73447911c5b47a1aae815d5e96164854636d3168d0344b2d2d913127011b6434d5a5e545d3bcd
+R = 21da49326f39577ee9f65cee64006525de88a834365a00f4f8cfb9a01dcfd6349a3d06bf95990a2c17b7e95cc0589714b7a795c7016b29bc844ae9031488ca354548976eed68415
+S = 3364def38a8ee3116cbd971794c859776107154234d8b198efb19655647bb9228c7c6be2e703672f795ed37481e994b6764d0b7c1bbeb2bd1db90b34f460278a54bd480bf4e9adf
+
+[B-571,SHA-256]
+
+Msg = 29acb0fca27e2a10d7b9e7e84a79af73e420abdb0f80dd2665696638951b52dd39ca028166b47a3b6a2eaeceb1a11c152383f0bec64e862db1c249672b3770909f775b794e0b9b28a5ec8635a996d912d837a5f22471b40ec2e84701a8804127a9f1a0b3c96ff654700bad3167240c2518fb5dedcc1be9f56a807083e587bc56
+d = 32c97639b69c7cdbf419286d0a1b406d9b1f2886521a8b979a36118d2a368aace5b02dd8c515f2041e6fb9f026d1e82e789dc826a56d2ef732b1bb0f49be2b696ab5d3d5694a2de
+Qx = 0087ff1d8a4644edebd43c2d43d49e140940d215f272676fdfb72ccf58a12021de3d668f2766848044ac404fb45cf6e18fc6700f87aa53b4fac1e35e1731814f8a9d0233e2942d7
+Qy = 29fad3638177541d8392111064837bfa77b4455c21c5f7652e3fb302f4bff4a35b74de8aff3806538ef9ac86964cff755a81cb3002b6fb241ffcae8ac9621b8e034967d650836ee
+k = 16a06e3d25873f6dae16bb2e569720ee9c6ae7b5ba36854c321a80be8b4be502b895e1a3d161b001f6cbcf53d164b5485d8a5efa0476f581f9c79b3a291025be01a435e2fc5ded3
+R = 347138a43f3ed1a1a26f5f11549eb8a41f64aad302b6383879886216ebb6d08a4ce270d07a5bec6018eb313430ff017c1bbf78556436d9255e97aba1481f0f16b85e7320df79d69
+S = 28f35e1aeae288122b043deff9ac87d39478607da60cc33d999b6add6209f452f631c6ce896afd92ab871387f5ea0eae5f6d5cf532e7a6ab44dcf44acb1fd1daafaf1ad5423d8e8
+
+Msg = c92d67cf6536f5046e15b02158da698bcbba4ff1e4e9e9c882cda67f817210402ef917ae93682c9c3dd817b21b73c6c00b7bf92ea80ecbbef2e67f4f4379d078a2b0f297742b2bb9c3fa3297a7e8079f488555bd37715eec92b4b1cbf897640ae8a1d2a0fbcee5423ab31a37629f98630275e35094a896cc574be0a449bb1bc3
+d = 0f93672159276c5a293582b9f49607bbdb970112f6c63b2b3b5d32ad3c8240c86b1af13a8dff6502c6b6a17712cfd988f8cd23a60693d64104143b3f91adb37f852e9e11a0ef110
+Qx = 19dda59a839aa2ed28f69a62a3e3a753c6fc789fe0d8551bf59095f009d0327386e6df5437846c6803df2442e0359a367d04f117e3965397576d4287398b4b8c92ad278df4a447f
+Qy = 4159ced60503f7cfcfcd587bb3608699f54693068101a838d575715de02fff81058d025dbdda430e176f60e423e6fcbba889914f6409ce51d51e89e4cd7bbde6d24404e5b043e79
+k = 10dd216d4b3da2fa6a75de60f722f1f128776741cba002c055d1445581242a175318291fae313eea11fd905b20d26cec845f57a3d5bf23ae4dc93d886c0594f1cf7be4f59f3e3eb
+R = 128d5c00a48c7352eb980d9c80781f8abcfdc1ddae415b7ac94b4d85c3d7d4f7316e2b3344ca50c6ae82938bc728e640e59e2d733f0c7f7025e66c15c81e98a845c1ed4843b589d
+S = 1ab59ce5e54bffc68fda96c920b839fe03d1976ab36978bedd973715ed631bfc8e3edd100043ac527aeb5ca121da848bce4ec9799f55b22454e9af32848943058b257e815b04056
+
+Msg = 15413f614c4551e3b138b64f66d15f8964c40326a42b0afce820778eee4a88edb127fbf575da5263e5a2627b5461d311813ea868e6417615e7c4938313675009caac28bc7a2f4c0bc37572d9bf36a3b1794294e09c0121ceecaa4b916df45b0dd31225415e6c87cfeeb092a008fce2c543cd62365779ae28f29fa02a15d9dcd5
+d = 3db080bc99c5fe7e06d5032167af56783cb423fae59fb5b3c6bce5fbedf56b7b39b17810e48ea9a172881aa1f42f5e267349b60294d4a208b4437666b44abcfee5a1829e9467908
+Qx = 59d1b3f680da784b49dde3b361eee819d67339447d7bdf7965550264eb63bcc7674b0921f02e15d45466dee52b4c0a50c2bbbdf226af1662086476a9eb1236e3d4c2b6219af1bdb
+Qy = 4e3466200dd6ecbc268cdc1937ac5123cbe33f32110cfdb8b7536987ddf5c9ef2464d2334f315b9b489cf227a6300b6e054fe40d36c057a692f2fd3e762624069e2adefb65d24d7
+k = 37fb32a902eae0c5d7cc9f9018a5d1a906a3d1b9adf5bfb696ff63f105cb2e736d9bc1961677fc897fd3a9e9bedd370be6f25a03fad425b5a293c66180df78db33aec4a188d3db6
+R = 3aa8ab9fc9073429e52469088aea91f00cfba271b9dbb84818460883effa0c51d6a48c1905d6f58d1312af073dc8735c29957f30324b467797acf86e028410de016338b972013ab
+S = 198a746411333172daef76359e7ad23035a0f5d14c283cb268828bd876b96b5f767e0c1e2796def7a51429f39ab2332ac25d8e4f263f8dfb9c4c98da2ccc398fb3bb9a6b28ca28b
+
+Msg = 9f901557451ae2f8ec79b6d4adc794cbfd9b2e6d28f19409532d91682820205308b41498a4e1ca247a2baa8da93de95e3c0f7afd6ca46bafdbdcc6d3374a12684676a50988b86a960a82180648c8c1e38f8fd9af604c7be3be4b24799f4544ac96d6360cdb83d1d0847fda21642934fd6cf65385b50d86d4656987901fb88d0c
+d = 06ee767f6f36bb8f364f324d8346455c899a49237d759003dd52cfa13b9baa4c71347b134b24ecaee32d247c34e3787a0c64bc5d299b55c86f64b47521d22f2c09db225b0c84cc6
+Qx = 3f971125860f4598fa310eb7a8c6b4e0c31bb721fdc17ce6df9af557beded6006b8eab10ebe7f3c4f3d759d4a87dcfc1fb767ef87beb1f5c845e3f41503a33b28b2b5aa1644dd1a
+Qy = 3296062514d4e89d2105dda5bd65a315b9770c45afe4050d8c3d15001405b1e32be5867ee90cafbe4e239dd44d030b4fda855182f1fcf80963c1300cb842459aaa8c2827371876c
+k = 2b247e2dd0024f534ed2797110df6ea4ba166c34d91c94e43b045c0ff80f124bfec1cf3be3da7c58389d352c8c5c1bc2a2e876a7e56301b1e688a085ea0222697fc63141564365c
+R = 2858eadd14373aeca65ee5a2cbbaceae4b54a50e0941a696406dd86d05c07c5599379c066b2288d01b2a43c9ae34bcb8c36f59d490aa8d066fd3d7e539ebc620a7176507ccfb232
+S = 33c20d26dca20af2c56982fcfa6f085bc5c317d01f3b1dfe0ade1ef6e3e960b18b626d17d6696c936f04090ecd9606c2a6ecea1cd1883bbbca8b3dce3b0acb2688fb2834aaf922a
+
+Msg = 959fe5a19d7aea2ba611c7203e19f8e3f3cc101e03a98f91adfef602c424c580d5a868659368a930f9883d699fc633bd07f6cf8de474937db0bea86fa7cd140ec2f202663813033a757b93bd72afba15be5e47a4eb93e8a666aa1c72c241ca3922547d63fa3732fec54afea7ade84302e2f044275bb67433fb6b125b7913143c
+d = 38e2571d9f22309a636586d62863ed67a70538287f3ef88b88c3c2fa1a2900d48c342b6f15c26b8e7fb4875cda4093b7de7ceda48fe1e2cc2975afe958040881de61f309931e48d
+Qx = 5a221634ca85059543e2caf8bdf79c43bb78deb35e9c89e07d553bafb6b31750a1d85ffa7689e528c11d8a3dae442b4fb2a4a21238d636eb04ccc04c8b5d794b0a213fe0480b1d2
+Qy = 225ff457b6cbc12d152b08025cdb7e1e921ee553add9cbf83228d678d5a9f5d3d1fb4327a74c1dcb5d69a5b98f3ed1aebef0af09bd49d253a903636ef5a66844c500fa221470f2f
+k = 3b4de49d57040141f3584ff596eda457e2835085d350b75391d90abe728723e1d1ac6413979d4fc3eba98d72a01248e6510c722df15df876da881ad50539e4248facafcf311b464
+R = 00f259038b4d3d036bde101aab29f4558e88e604c62f967bc7a35eeacc6a56294268f8ab00a34f9a0319b07754f502c98718e8b5c91093cdbff2c8496fd63d6fc2c50a35f87f423
+S = 2350d5406922e8822a91f7c95cfe8524f017a14cf7174ce534c60aeb351510d06ac20dc1249129247b21c72c14b02b710c26c10899bcf995143aee632e294176e903645b660e998
+
+Msg = 97b9688d9ed5101b8cfb19e84b89cd644262ca1c7ee18944e29ddd3b4cca78e06338b270385b00a5e8b91ca5e628de3bba50e36ecc695b3ea737a9cf8b36871c473a54ba17819f49e730c0f253b0c769aefa6c16366fd2dd612f330e95fb119fcf3bf7f3e254438c0ab635ec04a8b2424a05b483ecf65b74a93636fbab7bf1d8
+d = 0c8f5736f1ae65592f3ca850f43d06441aaad8c03820f3b08d8a6db46488dcfb828459f8b3f34af73cce8dc7a5e3834e085a64523d890028e194214cef4003210e6eb530005b01a
+Qx = 667ce3db45b8772f717ce20755ffaba968aa1314d75c84073042436823fb54bf8dda34a6bb45a61d610745b1fc10eb0eef71c4f55b26acceb442d822d6e2a27761c73b740f47289
+Qy = 56035da1adaae894e361f5283b3ea07b7d9f64a298be11de9fb487c2479b120381f1c60cefe5d32d37e4644ac86a170f82b1c4443eb71b940b21c7a016b559c6c79835532c276fd
+k = 190468668989a607a3aa966cad071ca8e8eb152b0dfca9205bc9417a3d612ca1105c7b90340b04acd96a5223658adda16bf6b598ea9f32a2f8d1b61c2c2bdc08d6a49de246240b3
+R = 291e1fb18edb7a93badd6fab6f56ee0d390f3b6d298e97312d5277358511fc7621534ac035f3518cb140fa4ad5ef7d889c0d5f3f52a4e4d06bc9f647f99695531f85a4b76cb1184
+S = 2d916734e02b0a98406bb5a9723486a7ed40bdd0b39c4cb802af4bafd519803d23c6bed59a80c256a14eb878229942f67e0b8159d5cbf24b719043171b3958fd669adfc72eb7289
+
+Msg = f08b250bf4a3980cb455338b3f4173723b3f44c97bacc9cf550149794a71426e398cb4a74bde141d8b7b4a72942f1c069676a9918e27792cb8f085ee037c78e3c468adea5123c4c64d8ca6a39f2f90140c5d2d80b669cbf0d1ccb466b18ded83a1d5f042c36188a04111c34ff769abba9aedda40a87be1e24b700225e2078056
+d = 1ee68c3994adaaa9e0d61bfcd3bc1cdf198d3fbfe28a44e5dd518867ea04b20e795eadacc48bfcf8e8216dceeaa069b756e8e99ed87b6b1d31154cc9310bc3b4555162a890b0c6c
+Qx = 3efc83ad15d9bf889c9afbd769bdd1dc8925b0462c93868d85ca7554b540d8c3ef7b9a63becc85981972eee8a70b7f948098ac050ad594ef2ec249cc3b557844bae9cb2cacbf397
+Qy = 42a012b3a1d9e46cece4fc3460a2bedc9af4ce0289e95f69550eb3544f7c105b5769fa52234ac88f9045ea5cdd4937664846d26deecf511ba6996ce4072e763e8ebdfe709660888
+k = 031df03a6cec2346b92d9ae7d3d983edf577d9a1bb88098f886f38536d8d8cf25def57726790604e674d036cbcb864bdedf8475ba9c850d510ef93b844c037e04348d5f48098c20
+R = 112dcafb63bb125d9610e59883df481bfde43589e46656b5952cdd72238cfbcfee79e9165e3c9b89c9ffed12d303225ba2af19e00048e20e4edd3968807e4885003d148403321ef
+S = 2ded1456df54a24214d8c1d3fb314db52b046ca31458bed69bb3aeb6a9ece509ee521fb8046ed43accc7e605440a09fd96db659c98a7dd606758c0c47e47acfa326b9ed73ba4b28
+
+Msg = 1cabd16fc29d7d919622810dc8b23c770b790b98b119eeab1b20900fa94fc2ebaf76be4f5eea91fc5276c5621c8677d4d117c4a5a782ee2ca1d5b0db997fdc8a05b6b3fbb833d7a7b81c3c615c2a662929760a96feefcf89e46b563314c9b77c86bf34438458b43b694ceba741b97dfcdacc0ed57652ae62856ce10ed2690770
+d = 3a6fbf66ebc1365ea7699c72cdac2dd85907ec59cd26e2d18713354b619ccb83b7fc0db9193aa8493c1855f1a83fd987cbbb65de17c59fbe79256aa5392f4eba045346e9ba26592
+Qx = 559dd556241f9b11d0f91c5458ef6adb783f9f5051bc12cac9f0b214f836f7b149d00ba8218e873410a50445da9fbf68673f3282d783988981fb221d0579341892ba6824e0cf4a5
+Qy = 05dd0e594ce41122882538e51e9bf29d159fcbb8b29b97c5546582390ad5c59c975271c58ba1e75d70c3898fea929ef7316ee830eeefbdc69bd80d7b0e8133b977cd573a3b422ee
+k = 1c5a193179ab859ec1166575007c3cacb30d31f341a0e82ed6d4ddb32da909dce08acfa10fb14183258caa743010fac6f7d0fb1f8c8f55c246e49a97f2bf571129144c23de8d68c
+R = 2625d0bdf37396585d22811a12ae7e0c3f512ffdd0bf4d048379434af46c03c6067dbe7c271c417ac5307123bf58a9f2064bd2b3a2d4b4efa3027959bfe63e13a851f46a21da6e6
+S = 13f16b211b314a7e9918f3254da2f1aceb5340713985610f03ec1d0a33ecf9217d61076eb153d8f27aa31aed3c9b165be52f8d857de362b2c88db5dccfd708a996a46b76b4ebd09
+
+Msg = 7bc8bbf5ebeacf40b3c82eb6eba5d994dcc6a3f2e12ef741f90f90e176d20c21e006ecdaf14cb5beef35bff46b2c374d9ee224516679b1a9e9255cd8ad8e60ed234f8ee7e0fc53c9021488158217d4b4369cc597d6053746efa1e73340bdd73c1bd2eed57b92426fd4d278d6a86e8be0f0a66ab3dfadefca8831b2f488636251
+d = 145748871a0b5c1cee628de04a12fd68ff2b154fda96e47afaa96389d66d22802968584f6753d36618d49ed205260f09d3f5ccc2b27a34390ce58179b9834ff92a86d66ea0a97ca
+Qx = 6cc7ce2782dd67cf1fc16f1b24ae46fd085b969d936fefc409a9bde354cfd33a154a3113e837cfb88284d75a96f5fbe85274fdd0990af4a033a6c40b904a5e0f666e4d8b8bc3532
+Qy = 7adfea166087502657bf9e2c437beb2f62dab041553a06411f6c9dae83a2a2749a4e5a2a36fbe23d40816b1b8d206b9f5cea20ef200b9150061ca22fee2076e31c88d60a006ef4c
+k = 26c820dc92f97dbf545f51db7d5ba649333dde38eaa47d8a7edad9a3cf3e6780442db234632458ff17e1d7b70019916708c128601ff547ac84dfb0173cf0a3c5d69ac96c3d7d395
+R = 338c88d1bbd0b93f3f1fe1ccfcbda65fa1667ec471730a40eda87f57b3eb63d979d8d6d819b974619799c90b09f33c051b8b522c3a1acede101857265ce1b58cc7eb5698049f494
+S = 3637bf89f9b66c7ebd8f91a8324eb70a510284b39f0f2e45578f26f5f1e4504ad70a389427f4d58960cbd918c2f8279de52096e25a1b0b0c3929fd5ef56bab6cde7c0d8e9d2fb30
+
+Msg = 0cd2a45392871c0c262e7e6f036946354bb41f9c2187b8c4d399231280682f3e0a09731fbfd52c76ee63b9828c2d731f4cefee0a8c46419c398205b2ff80c67d7756db300a0a8385fa287dd37d9126f75998ae1cbab5136560592118db52fbf102b7ff0a1ed45b8a91a7d99d13a0f7fd4366392264aa1248d7324901467457ca
+d = 3c71911d24ad19c20fc1d8a044d63c9bb417abc3778d7e6234c6af79b898cbfc2f2787244708d2fe203be786edbdc4c9b12b413156b7b0bab0be8af895d191d853cd58aafe1ccce
+Qx = 6cc47aa586a73acddbc91398ff5782457e6da2b10e265153c678789d3d7fcfc485b03b089eb67e6d6955d5c8c7ed5f933d84853576e76fc60332e5f0a62c3ab23690317bf1b423e
+Qy = 15604d94ab9f2ae1d74fe46b1a070160513709de2ba8e74fbf9922e9bbe7f6e743b25701a13f73eae0db0c98dc80c5f8528e16610fcf18f60eda3357ad5878add2554a6befc9d39
+k = 3681fcc5fc1f0d7d413abf2e44cb5cce9a4a252ec449ec4f550df4a172305eecc072454efe2040aabaf4fee58ed19c9090061d3c4835c5fec38996f013e5512c0147cb14a4f0fe7
+R = 0d3c26796bb86b1a20ed4935bc3824bcb9742513ce91a66dd523a3c0d8a5abe63488aabb806b5b113e90d3f3c80e3ffa01ad051e6b0d4edfc641689953ed65fafbaf3e554be31ff
+S = 2e3129ff95b06c274f7ac08882dc1da6660269f3dbd21a3e48377a628f6d81326084bbb8d32b794fcbde8e574f853636fbbaba480fb36960b0994210bea319a99a46e29b79217b3
+
+Msg = e97092625b09c9ae6e152e1cbee207d83361f34cb9b0e727c816a5ed851f12f91fbf88ad9d4c8f9d07350f5d828fd8574eafc768bc72a2b18aaf4d2b48fb10f7c3431137b51850154de9706487d69a40a8f4cb2c799f48c5d8f518aff752500de93cbb94ab04ae1e0c7183a32d79a27291dd07b5fb6e6a4fab76e85c3a8607e2
+d = 18bd74698bac36ef11add6b3e3fad227ecd868f370ec04569462565d2f0af2340bf793486953a7b79ab04f0ab1f0e4fd16bf6b576cce677d543e73aa8edb0e50372f24ddfbff966
+Qx = 231f891e63bc1c43377faa56c5799eb1c877954ca2cafdeb4883ae40bd78816ca5634f48f5ef5c22dc7d3d0df208bab4149815274d7b134cadb700d166a5e3fc73e9be1bab72522
+Qy = 469ea29ef860adf24afdd386347763008ef6fe2488d902c4d513bc0183fc52742782a6fe500d6b581902ccd4f9bf077f975bd5fa89bf240723b99f726c9fab4f953380745ff9e17
+k = 1590570de563ea96eddd900e4a0a7efa2e4a0b389854e96af32bb7555f098a8cb52d160abcfbde65998c34f91338a40d40cc03e4a9a241d3b16b0e893d3f7ffdbf8912f35c7f538
+R = 32402fbee4831b16d762ea2cb218279f4db5e20bc8b6e2e53e89a2ef3646cfb0abbac36116c8c708a1342db2fa0abd39d149e09db57aef65ad8092f37f7962f98c28331f0f20b64
+S = 2d1e38f40965e2697abc7df5896cf051ce5646f135d1ea0bb470a43250af8df0abf2a04ca1e0f1f31013025b4136a8a6bdaa474bf50752c571f883829bc3a5482ec20e2b4a72c90
+
+Msg = ae6723b8df5d6ab5fcfaa22d32fdf106d211514cb1892c7c43ca6cd85c2532f85929c8a259ed251215063cf92e1502528d1e22d5cf67efa0b8ef21e8eb2f5dff881ba1433e8bcf2b6af8742ecb2bccde081e534615a305562cc22d3398f61f277d8ca785842bda85d8a40438d9bf1aceaedcfc22c85533794a69cfc320931d3f
+d = 335699bfd058ee2e6163f55d1816bf3669acea8b73be9c4ddfe775230925e6093cff7a66813adf22222c8376faa106d85ac9f3c67929bc58d8986795b6d35d5b9fa546dceabbedc
+Qx = 7995e02dd3d40f9bc2e6f4cb1c0d29923c9022169e64532d1b357f36264d18059c44a8617a6f1136e72648c9051a27714a0dc833428762275a1b5635a3ad91e65d2713236c20f50
+Qy = 6167d5839cd4476a638c50db218979a93da44dbf97281d90daa8b9b530960c689279fff6c342af97880db1e9c5ae57b91d7be727fd1c6210ec59416d1b675f4dd666e0b121d144b
+k = 3f037ebe0e4c3910953e123becc09c0862490e7f590245c4cdf9ea5fce930a7d7ca5d17f5689edae1ce706b90efdf84cd82e06e4ab95e9e2368db91d50110eb91cf44e50cdce2cc
+R = 2baaf025290897a5d68c5e63543256523fb086a6f1166ddfd3d50fb307e0f0cf78b5fa895f8b71944a7b67b8afe5f3e10f2d248aedf573860c42cd7aff258055ee7cce472e8efb1
+S = 0f4d239f5af023ff6c94ad7f66d43201c7e40262cd92467c4ab54be8d2b8e6577d14375064fbd00a6327da62f03f75262392add0ec119d820205065aa6238433fadc8d1734b8481
+
+Msg = ee20c6b61886e02ed94359dff3559522ff550ca126fed4b2240ea7d999a182b7bb618c50528fcbd261d5e497a991fbac0cf4c105c0f664d6a00a9001c1ed522962fb44dd4159677ce8f1531019f86457c055c9cea6247086cdfe0442485cbbc4386ad002b4bd39a1a187752437f04569705cb7adc0c68f0fd059d946deb63f0b
+d = 2c3eaf801330b3f1b0504f2399f1d24455db29911f750c246ba0a134c3b59da8b3562911197764699a92ea1d95a2aac587e24f743df1dad3e1cf7edf955203e24a0225717f8d2df
+Qx = 703d69e2dfb13fb6e695b0b30b31d89c8789e8523a7eea15673aeb4f1909192c06c27558eb55f0315f395b1f3ce84d9c304905cfda1d119bec33af9ade4420de2edbe75cc5460e3
+Qy = 75e35b2d6a8550969d49ac5d656afacf68d3a1dc6d17666f46ce3413c855b627f0891912e373af2ba91211c20f067d66056e6bbc0814ff3921d944008b25d8772cc8d696bfe1d09
+k = 0a9ebaea478893aa0e3bbfd5d007bcec5ad787d9bb5a8e9b8b79865c584966f0bf040d36f62a8e97c123d2adb7f38eb49a86e9c2ce1294d04fef1b6fec7908c4ca1a70bd1699a9e
+R = 2d495eb5f6fb187a0ee1fa772ccefbb969e854abb445ec19ac3860f40ee65f53b92f6a797003574bccf0b9de8014ad4e5745ed264eb3ae88040ef6518809b4c66f691d496a85d51
+S = 1840b2977ff137f2a8f2f7c25e347cf1262fd128e008e30e4752315deb5231098c65e9a585496a9d6b5b56cd0b6d7dcb7150a077fd199be2d2de0262aa84dad414e100ac6162346
+
+Msg = 734a9eb8288e32f5a67cc1d88704523ca2c68b798d90e188d871d9f50d2da2063baf1ee6685c45832a1818aabc9afc0bc935e97969dc983a484f16d2bedb3c7c0b8221408be2480a5562d5d1e5d8763d1e474bf2826aa93a68c3b870e3bf34f4941cf590d88e1f5a8cd782a33992213f3f6b4b4f6dbfb3c3c8f21f5eaf4ef609
+d = 1c3ff067497e5d387f31f0ecc9c67b3c0dd6ec8c81318c492aad83c9dec6c99e4fa47447f6f7082d636c2591d0df940b947d0a4ae3778e2b7cc8fb92214638399def894ada276b8
+Qx = 2e56655e37b3e753f35eedca95f8ec07b7a3d3e14e365ec041cd9003bdb78a7a8b8ad277a67da5d63dcdeb0ee8d8efb68fe61aad9b1fbef4373ab13c44efacf68cc499faf5b5dbe
+Qy = 47bbec643d74874b77f0fdbbd2df3f3ff0d35f4b3e1534b2c4d5c76b8cc51693a70e17d1d4cd64713c5c05966c826458fb5411ac840ab5998bf3cd64a0769c3e075259a70aaf94d
+k = 149848f4534eeeb45fc38ddeace59e8f83f0bfb4cfcd2b8b7acd0bf19303051a6a8fe75d4cdec1be036645beb075c772aef4a58785c16d984eb43b9b0317446bc3b3abfe7ec2cb7
+R = 17eb68556224f995733077501ed295088cc1184fa3872f5f11e97cf67c7bc1febebd31206a406c4479b60246a517cada5859d4f1aeb98dfc108e96e9898c6e71e59e39b6284895e
+S = 22904497dc7a98fbe117e4427d74f4ecfc4e14d4467c99227427e3abb8d3dcc406f3704a7783d822ec1118a1d91d5945d5b902a2ad325bcc9c17c68ddf8b5323df9c2bde392710d
+
+Msg = 68e27cc72fec8f3f1f3882c6efa08efdf21d74d13be5171da35ef2855666ad2ea6919d21dbc1cb6d296663dcbceeba2fe47a2c6507d3d4a67a61b55b0f81c93412d7e1fbe15a590e342a05f55daa55f8591171303154e615e81189a523b855829a5c96621ad118f522e397e2eea05c2603eeae6e3591215e29b2289bc384d8d4
+d = 04b4e04281b210fe78d516a5b69f878b7fa058941ee9ae8cc63b061d1eb9e12c3e0ecb8717ff4623ff5bbbcdb53c48adbd9c69636506ab929c5507d7ebafae5654aad65a263e48d
+Qx = 538049d071158c62f0102fb664a47431afe320474a173463819d5f83f6737b43880ed378470d774d32ad59cd9d75e5bb06b118f1297af3f6fa910f40aaffe11e46cd56cbd29aa51
+Qy = 0a4a843af9841e2427357bdf26817656637bf4650e443ef303dd458ed092dca3cacf2857d10aa190c256467ff834bc804f8557f6c3bdde89927a5f2bd55bb9d9f1f08a044cbc208
+k = 1191110485f56335f0e65fe04b9ad8fac1c3573cb4690db3e9f62086312d394b0e354890c0f74e3df7c43e718ecf18caf6904e03bd6c0912f906de1d2bb4c49823bc6c0dbfe37f4
+R = 0dff371ac365cb7de248ddb2b2fdee624c527c6c1908dd287a294bb43a4be94c130bfa83710b0655f21695dd91703acca64fe2e7927eaf9c2b9b230de8002798224f9505379bf34
+S = 2f30f31c863bdd68fae16f97fba756e033eada18cb0a23d7d4b2c9ea3c832e61b52185fcd654d9eb281b92a9b102c3b17ebf02422a0e4a7a56a73974208371ef65434c38f4d7d1d
+
+[B-571,SHA-384]
+
+Msg = e67cecedf35058b80787589514a9c81c6b9f4bced4260411d2af75bc46b8b2c962dc9d260dc99ebbf8ee64950766efc0e394184bdc8e2891d66bd3300ecc880e9d6a3d0eb615322378afc3dba89938704e9a8d0c949d4bae9838805c00377e3fe5ec6a1a98ad7eaaba6b500973dac48b26b7fb2e1b9889f8c387de535d4b2363
+d = 30f2849a713aeac95fde5ce3af853e9d070ee60709eccf35a076567be2c43f0fa34420b0fc097ff577221275a3a56e759efc32183be2d76058a7d20e5dd59f00415114d73a15b8f
+Qx = 6d4ed3cf180e0e307745faa49247f269c3fa0a69042b3b78ad645f43eaa50d479622e27429a6b6b1889944f85975fec8018d3321ed38f6c7d91f2efc98467a027ba4a02c7f231b4
+Qy = 5f2ebf6abf7d53fa32865a9b6ada9bee51c1fe26cad74dd6ef78f13872f340d64170031becb5073001fbca373be4e32ac3425d705ee942e6c4e639bf72379e34776680a387a0c6d
+k = 0da9d8647d0950f558a3831b47858168b3379656e603f2bd44046ac7546892d1a7318c5a9873c6ff85683edd3881a0f1af5501d17939f0825ed37bfc9a2d95faf43d3be92b237ef
+R = 0fc7eaeef74806606fe51882c6928a06bf552d18dcc4d326d44a540abb728146657048b20e5fe2868beb5f04f32d43e9ac23a7f22c6bf325bca24f5e3161c868911ee61baa8a3c6
+S = 33d63693268f3762635373fc901fd72e525965ac17e2cc009177f03bd3524107b30e4c6d80bbc4f87fb1f288ed56812994541fe063f1d91afa7213bed8be5693dc6c17ec9a0714f
+
+Msg = 2baa1ac3f07e34b67b6af087400f261e138b070c8475378063286c16fa73578303380236a4af2484ea01ba56c1c619f6ae4e5e6ac2594c8e5aae7e7f196f96fc5d0f507bebedd4d818e77b9120e5b4bc01c7ab6339e88b71d0886631cc7fd89659bf513faf149c61eb14d55060c8dfc7e6e4c2b4ec8edaaa6bc36eca50a6feef
+d = 2ebb73d04e6e5361e20629e3ad119b33db5163ed91fd9a8aec4b774898784b6822a08992118a8fe6013094bad0be1e9bf01b27c069e4335bff7e0abd28a10443818f6b825e9cef1
+Qx = 01710eb0167e8c948d381e3a75aa1e036b70c414f69260aab434ee20b6724dd7393fc487b5b3822e5e8065b06d0785a4a7be7193352d5b9eee66755ba106ba6e40f98a08c730a0c
+Qy = 6006f98fc25a641a7c6e67fedd37aaad77a9102be3e1e7d32dcb4c68029e623a42f4ca7d1ea725bfd475756b80e18904107c460fc03b9bd68aa46f9dfbd60618670c4d9a68a3287
+k = 1861e2a356a6fa8096418cde7fa17f1b893a7b63810f3fd807a82bf4c745aafdc4963eb7a0ad0488a776e915b64d2b684e46d244703eb63b77835167908f2d6b06a2ed7b53f0717
+R = 046688e12d26cd96bb05d3f418d8ec34f4426f594acd2bfd8e9abd79405e612d60737007440424bc4f546c54b7402d11880f68edd996f49277b729450f7dda5d05986b014b5244f
+S = 341a80e74f3a69b966ef81ae95dbdd60ed5a0446416653c4df431ff7c4b4272665a523379d76725e9fbe196018f0e747100084c823b95d7c7b1785d3623e52e9adbe773b81b49d3
+
+Msg = 0e640581f573068d8ebd2899a6aaeed0bf987ee11e22b05d25e88e9a1c3451f45ee3800d976f4603c18a041febef07a01086832a6f7ecd5d498d52e796a9d90758c87c36f4a5b704a39c456aaee2d5278183d5815d619c193da9fbc427d701bab0874bded848cb4bb066f56e119b637c78aeb6eaa387c41bec6cdd4bf7b2061a
+d = 1bfab717d6f6e16d9bc6e89d2ffac7cbe0f808cc8ca2eb515af7ecce5f3b230303775710a21bd25c2cc4566bb53c78c78e3774a9f306c751cc6e149929e45eef60f56c1d2388c6d
+Qx = 6935c3e8b58f7bacd045e745054c227687800ddd86d6e0c8b1e426f4df0e4b71feedefa9172c43becebbeee8ee382a75396fc5f29ef3d2cc55f8afa9232038609b5034513b222cf
+Qy = 138463efe3b32259dd90b759062f848deda84f2bcc0d687c410f1ad2dd745517c96c3451432b1e490902208cabb68bb872ec493eabdf1f3b07595d23a54c53e512777abffb7fc65
+k = 00025bd48e2dbbf1ed8bd9c1514303dc503dd0799c7815870b902249cd1d7368380853d36f7fdefad973700ded1e0d66950181b0aeac73eb622c880571315f09504ed26e28e85a1
+R = 1b9d6ccb19b208022d3a579a66957429682517e84a71be42fd571fbbd0247609d0b5b33808189efb52d21e6421d3b08821d82900577791b1c54e239b0d908bfbcdc060cfedaefb2
+S = 3356320389ffde577496c5b46a0de6d53005f5ae3489c0d292c5f460a3b7adc5bd204bc50a3bcc8538e0f8319c79b9024b065223b7ed9b0f211c5c224d363f5bdfe04db97f99e19
+
+Msg = 51a2a560ba226d629127ce1ea7e812219ceaddd23561256331458c9f11fe73990f21d0dcd974a3773040090cfdc8e0f01692d951a0cbb60f8448a016c67abf46a9c150466ac77e656ea827b0ea7d1e77ea32071ba8314fc8a2edf69008f498bd1c18061d7d00f3340a7e2cd73e9766862378d8702e804a1870b442beb2d0aa14
+d = 00cc53bf7f1cad5e3dede4b4f4b082831604c92dd2b147869cdf1107259305b1d50359647f9f3d7d4e1e608865c65dc7c9ea46bc324dcb8423b554dc369d621743cbfb592b70eb5
+Qx = 20187d7de90652caf1210703ef65cada3b88f978e14ce6055847be7127602ba7a5391cef0fc9b009134105da7b09b49beb7ba2f961b84e6d66bd818ea99ec106c6e8428b17394a6
+Qy = 197aef36e47b571ccc0b41f948392d6061060063137d8c3b999ae507b76132fea1563775be555616cb5816b9b19e42b34f9673aab833f4beb9d1a0848a4bbf2f6f44cd03982748c
+k = 08acd0f8f9660d21d62f391112908be73a4342767328d3375a8806dffd2598b6d77fcb4793e69f2390389a78c2b11866cf0f03666a60ad088d2c77bbc49fff6efc5b7283d02bf36
+R = 1004bfb78dc0e4fc0f2624bec6893d717a476fc76bb5c1d94c1dbf157aab5d1dc80f98a3aeabaac94d9cf9e26e1dd172f5d8fcd5b2d48cb3b7f0a4863813357b5cf8eae84478e44
+S = 30b1c8857977181d12c53cc2efc53a427801cde2890cf2ea2c99c6958b6869d0ac78ee2c846c241362c885835af49c47d20c30f3cbfab27d9cfeaa6d858694bab059229e30bf845
+
+Msg = 90eeecff0a2e37df318c441df220dfea013ef29774ee92a56b213e13a798858f31e52b6ccb7599e7314f12b48a89884b113c1ba0526a54f3e9a33c940944319e084bff320cf5f391c02c731c4c4f8b05afa273374a1705d6c85337782ba7d36b9c00767180cad6422c11c581672ff631fa4c49d41b02481568ec87ea97220400
+d = 2b009530cb9d586e35dd8951ccb686833afb7a37ec253e547e85b253ba999f0f186b6d4ba41091615fe57678e9801b4dc94fa683511da25637b2acc9fe60936be15af16234c4ee7
+Qx = 5913ab6a2287d946b5b6d1e6c3d64117e085da7cf6388e333cf58d22494f4b067c684dca770ddbcea5db73f048b296e9c17284a8912b3cb722d9eaa17b6b1209311fb8e8757cbf5
+Qy = 007124ac6c48ac56746563db247bcfe6b20215ccc5cfb1d43c923daa07d429c8f0513bd1ff1180ef0f7927fa23fda1af25d20b22c935c426f9ccb402c358b57b812516c43111779
+k = 27a80a19e9c320b57146845fcf97d6debcffbcae877c33c62aec62a3351ef40bd90ef4c2ca39f9e51086931d82eec4ee7870365cb14e9c54ae735069801ef12c571bf1c7c1cf6e6
+R = 1de22c8984c593a0948164e6cc8631489133972482f6a7fb1c3c13f97e4584604930d369224850a1d24f267f41bc6fca04ad79326aef61f0d429e0e1b9e9d9686ee10f2bc52b104
+S = 085c6b34687081e280a180cd0c4ffe95cebbb0ad6d3b20a7341e467812f88c23973701cbf3cd2bcd2811415d0bf0cd9df229a88754f4cb0c225a2d11f57369a29edfd7b04639055
+
+Msg = d3740cad41e2e365d80ae81da97fdf06d8b6c278b505e34cb683fb55ddc5189da543540914c0accd405dbf0063f6222885fda4b316dad4a83fd03e8d7b7e936f87fc0a5b095defc8a4b22fa97f00b394e672d5efd3e0a230c7e44dfeebda88641143502a400ed62e2a51f9561e5d652a43d616f16699e875deb9610c77de8e1c
+d = 2cc2d0d7189cc8fb3565a039aee7633ddc00ff427cafad32fd2010b10fe249c9724d91785e7080203626038109158e3a61a3970aa3e51688aa7f5184b22f63af63f80d3540ec023
+Qx = 5fe95a030efac2e5d9522680da58606e3e7544a317a3f24d726b69238367d30fa586864d8c143c3695126ce8dffbc7e7fb789f956dbf53aabbc38af988ce50f1fb30294ea3e2d48
+Qy = 193d1e745d82781ae5c3b3d2233e502959d6862fa7987c6416584504f65639ca765578378b75d3844df179cefdeccff3c4c43aeb8865063e176fd43a27c93e329f8d4f6fd5bad21
+k = 02df3920fe4d328315353ff11b0264045248b32f48e860dc59d931ad65f39e97e3a683c7b5c64b21c3fa50a9685fa11f49df9b14ddaae03eb02754b01e03f60fc6aef1e5d6d7d3c
+R = 1b91c4217b1580cfab56812c16bb5aefc1534ee8d049aa2e1d52a5bfc11519ff89f0d36ea2bfdfce8b5d3cf1527dcf700c0208a70595e9ebe4feafd0eb597e05df54212fd6eca3e
+S = 21ce52440267fb16e713eabb8bf2d502c81939799f9d09cf48a50dce5da999f3b457dcd73c212d5d070056b1f373b07ad06e90d96febb7f8cdb4c423ef946f0799c038a3ee68ff4
+
+Msg = 5eb53b5f92121396c5ff30e0c92da48db4fbbdbf27297f9bc82614ab78f7fd863e34096c615a02e349d8bc7ae4b0700130704bedf32756b5ee6af10da1cd717d624fadc57a9aa6db4a6c5d6254c0e8f8c3c0d4d03c264eeeafd52cac2c1968d9d85b106167a49d0ccdbefb20bdc10a2555f8149203af52853169a02db94e5e2a
+d = 3d8936c00c131e38c6566d2464c4e207c878070bbf681695a6cd98cab2c6e80fe98cda80c66a5cf584e90a071144dda59c07b8fc7bb42464dbee5b6f739b0f2ee5fdff7e5a4e7cf
+Qx = 0fc3a8a320e816305772bd5116cec2795d58633a9f490be8a1a360f21d2aebed6038ca4a5081288b6bdb1066307c26897ce38c24f8ccc98a63e371ff6b54f6016917b430c267af7
+Qy = 69719c868d8fd25a38a7338811904e3330a7b2289a8384bf24f6dad5312160f0093bf556fa061ca5e52d6676a8f1a3e4656740c82d3cddf0ac4f903ea885d42610bf1b45d9e57a1
+k = 050da632cd7aa58340adeb20389a2cb9897b8ec944c47e7177da65d9386a9dec5d63be7bb2d0f5b4943932e1fd7d87d5d7a80bc50a63dfd101a6a28005c894c6a6fa4c652dc519c
+R = 0e6152b9050127bf306662f6beee81d024492b91efe87a56e70596a4a72cd02dd2f10b970c9a69909f85bf4783dcd3c32505d7c148166ab43b503ab098b6d95ef09a7932359f60e
+S = 1f7d68d53ba161b61eeb17139eeae1587a6bd148e288c1f73a6bfb3a0d1f6dd8f9cdc27fa9e8c7a681410500c097ad01f320303421f1239b4a9c4d5446562b5b3cb2fc45a6fe239
+
+Msg = 5aced64f702a57ed7fabd045a40c967a485d2a70b0a5e82561d5141ef329469b2da5964a34df203a980111a77adca376c643b9030aa74516f054648c1534d912ea66582adf3c655dbd71ca55e47412315df5e2893e43b2e2dfe6e4dedf426f11846ebef34a99f5615460ce0475f7bc54b4a4fd99e83c982097c3136ac6188a5c
+d = 3dc7de970bce28a943d7599f2a9010fc99435b93bc4ba884d42503ac2941aa63fd07db34bcbb1127d56d6a4e277d6ca32051ea3467e376f74f98c3999d2f276b282ef8a28cf0cbc
+Qx = 2066a50b9f961a58620f473fcf7d5eb635da47f4ce362f428669ea578d50d1c1513c145adcc03ba98f3d67bb422141c73e2f94ef9559ccfdc0be20eb206d3d114a5db302bd0751f
+Qy = 4437e655bd255e7f013d197210bed70c5c1a6cc1daccb96145c9c438c8a44b4074629830d8df9914166c9378b33040d71918cdd0f47fa64b7c69f43eee0f34414b8f64882f90ac3
+k = 3b2e20f4e258b7f0cf69a460fece9b4794a12a37c0f8e7aa6f4f51dbfaf508f6f1e0160ab4388891efb09f0ca1f73178f0e8598750c9debd3ff856cb3a2872762ef9e16487a9513
+R = 2f265aa99ff806ffeacbf9ef7be575ce5300d3cfd4225b1835774ee075d7e530c9fdcd681584223f84a497119b4eb1fe34cd31d654c2fa262d7549acc251cece9530b26cfa3ab35
+S = 2c05ce4b35544bd1f20a68eae7f3483e0a0628dbb53f0466166257f69a7a110d2838a76d204e7a955a8977508e65f2ef6d7deee13e4e2ec0f2b9a8b4bedc26b3502813b0334a1b0
+
+Msg = 43c24aea343d4e088bea25be69a332c631275c36677093e057de69cc83a4c5e70ab270e5a8930f55846f1a22ec10e03007dcf0942c6761e89c65c6a4f032eed97dc3a2c7f7ed1e82552fe48828a132ba16c41f6bd82a49335428a24fa1679522000e6a1d12c646e0e4b4c584398577ea9493bb334fa3cee8bfdb6c2e66f46436
+d = 2de6ee12eefa7a4a736484b19b42a513dfc059a060976edc3b0aa4b50e98d72df6506fed0499ff8480986748e938289e54a5e86c0c29733a9bcf5985aa63d8a2b57933a04a8e8e0
+Qx = 073fa1b62d469f2991d54f1472b60da87ba51be0a9dea361d417b91a4a75373695e9f27b3c672322315d7b566b1f22b96c54adce3e958080fa8a02836955f6264dad3a87fd11f06
+Qy = 452c0a07ff65fff741c96851657a5afc7eeca239622e1260414ed736a04e487157c52da98a7845bcf6f311e0f2e59bb92248b6d47dcb93da6f7e0af644b7aec7603a01950293d8c
+k = 1c87653066057636f9a98a7c69a84e103df480a92739abc4d5ba53891591e3aaaef6ef3ef5e89213abbf71af9c84d3b30898580e782f557a03694446492afb05ab801d7dd631c8c
+R = 086d539546c61e82d74319f0180411172acaf08b5296dc6435d4ed7bd50cf23d3a071deb3be01f74408e64ad244f069cd41227ba127145df5a357489f944b61606ec75e8377db81
+S = 0a34d9975fbd601614d04aa41506b03fc15189ee8102c0431272d691a322f3e77bcfd19d8bddd19b307012b6c6349f5ecf88b5a69e83588b0e18096117f207304b38c16a9a8592b
+
+Msg = e89210565959d93b483659e62cf41f0a0147ea23890c2f1a694c377a826165e363860e4b084016cda878a43eb68465f81f397ecd50087a25215ce7c4ededa3552218071fa3acd7ae380655fc8fa884998209ffc8a2c26f1ca19dfcfee455dad35a4e72caecd8da47eb9ee21b889162f5d3032724abfd1a31e68612e18bfa9006
+d = 05468f0df2c9854f5f655743e79c750fd8812db28b096d97207bae7f5aafc6b6090c9c636ead9e0fde32a1ff8d539b53813733ca812b41b58ff85a941abe4f128d59fdf9847baa4
+Qx = 6591750fbc104f82c213fe88aa620e8a960fd6140598e2e6282e0d5c5ecffd09d22ed94166109561a7f4f694e171189056d8b300b54c8134485500effc7123aaa23862e89791242
+Qy = 05bf8ec10a9ac6a92c54e7fb2135e2aa4f84da571d33227bde0aa2e6c1532074882235f3103d9a51e80b7a9a19067f35047ddc52462db7c634c291e8fc5eb2154f6913bd0846b88
+k = 242308c430de514be1b9084a7e6c96894cd5615a7c71ea22316e539986e9702080ff6ceef2980144c55d9749830c20c9ea90b93dfcdd28fd862b6a15748dbb3d982e4a275129c75
+R = 361e1b7a0f981bcc65480b370c5e09b1c2e2a67cf41646f6a3d829f663c09115892237400317601fcee78a04269411d267dad3e8fc6f069529fbdf0bcf9b5f13c9c6de1681e8b0a
+S = 2620c29f86cbf698cca5f79de364ae131345a802c0cccfaefdd7375dcc9ba6ccac91f70943eb606506e51e2ced50491eb8f48769810b6dc178d56702838f1c2f0930f2a9e4f1db6
+
+Msg = 48629ec97f56273599cd9903f8a84ac2ba74275b40e1e42fa47649568babe05cf63c8417d828251acc2eec525b56dc9082b68d51b0c2bbaa7389fbee15d058cf482993b2bedc5a9101f1afdc79989a812478245d191550109fc17215679553c508c84e3d4cfdea377088d09eb214e6f92410facee4790beeecafe72b2e3ed192
+d = 3d3c6a7ab9450c94aa3b8a1ffb678e5b647af24cbfd66ee3944e6f264f406295b803767471fc67936fdfed1714b4b8761a07eec86543b7c4da6bd2fcb33fa8cda4077737f398e18
+Qx = 42d536f1b15a22f4ba80066798d8d1c2704988eeb9423319c1850a1ae6bba4097307b515640ed3112e93f1f6ae67c60a4b0d2b6634aa7038a60b52b2b447fd1651857b71711c975
+Qy = 79eb18cc7493a1c7f2f9b621969b9ce9ee37fc0701f6cf56f5d5dc6efb13a384517a387f253aae1e93bb0a919b0c22e4d6cbc79b449b268a068b7eb2853324b96715d75b8c26f27
+k = 23ce112d60a2f7c29d77d64acd9f587e0eb75ef8e739b8548e154681efc24243594eef5e33d845b1e4e89bac56f2e9586e042e0fff38bcf79c73fc9aa5fc908261df5cd2c6cb821
+R = 3a770df8a2bc35e122c1bd551c38400be47f2499ff57618ccd01e14a2e35e87a67b0e40f9a10eee7efcc3d37b474f2840fb8c24a9adf93734680ae6b25818369c8608a2f8f338f1
+S = 0728a4eae5f5638a51579e224a24ecd4c997001bb8681e23a7476fbf78b4fab84497000f20c1e67e8a4e4116498bcee49ff00026009af31c1037172188aacd264fde8db15c97167
+
+Msg = aa3a9fe467b1ca638dd0622c9ea235a418b39b2e15ad81fee01b6892b240783d8db3c72e16c13df8016dac6addbfb85232158325bd7432fca3b8bf5db3abd0b4c5ccd0999609dc42199ca4680692a0805cdd68108bcb493a558ab507cec0a2782a9e976928985352edb2abc0c07078b59d2fd86fda7fc76cfe573181d934c46c
+d = 01ce010ea8e6e1a0c26ab22eb90f0700dc73b232c429d36371e68e429792afb7223f10327708bcff779ea55fb5f22ad87aa054e84d10f5450f1bc9a89279062ea2173f55ab0f76c
+Qx = 4b2b5acef5921e691f10ade81b91ba8e68e73b33a2494cf4ca6617707861f334eb07ca96dfd681dd63f78102f8d792d66102117b739d477e431d9a3efd79bfcc18cea156db58a0e
+Qy = 7e421337d4cb7a98cf9c9c6fdf9fa242904d9906d8a6759ef64a82cbf923b2a57073ea0eabd14aa4295bec84d50a1722fecad3e5f064bd3171facdfff45b170e49f185a3c193f2a
+k = 326b62065b7c779dc398ee03a8332cfb940b0f24a7d3de4a90323d9e390ad3fb1f0036abf6f525d8d88ab6641302d10db447b78780d366f32ce36ae571e323124b21984c48aea7d
+R = 3d2b207b428829ed5100a92f7276e16978e374c734834b0d627cddf6aff5cab72dafefc6c038a91426e35ee0f2c1acc11c55a34a89874100b89588aba7b02e19490e66eb49ef6ed
+S = 3259fef5c2a0779ae408b26e6c7d581fa973156cdb07c329dde0c12b6c498e7a94577719865b7fcc0db078ba72a27bf338ec6b8aa41c15963538c329c55dee67833faebe3b643ad
+
+Msg = 6c3937014361799f1461f652841b5137eb0dcaf01dd293298d002f27e9a770b9e1a30367e35c04603881f0c814cf8ecfbe1619cc49cd516b1d60d27de37ed52a5e1cc300e2face4669f308ebe6747255a3d386f16778e494a7cdd10b45171b2bfcdabd91b805bf24857708c1b75e368edb2874321324f83a19154d3a1578c767
+d = 1e7410d012aeef02b3723346d24ebafd684c99087ecccaea1cf3735d52c4c81dda41812c09f1e874dc964d858ca240a19963d5dc89451f5dd6764426ae41cb23f19cbfdca0fc562
+Qx = 400a3bb3ff07a339ff98f7c45fe032cf42c0e25de8dee2934ce42dfb0c9894f4fce27fef299b41beb8579270efc7b01c0663c3f72d7bdd9f6ff5186eca9c42d15faaef8784211a5
+Qy = 06fe998f7a0db06efed050d178865a2b7de6ca7c789cedff7f2158a5e07ac1d335ec0dbd213fc9465399028fad8b7f4d2cd16fb8ceae4d3d53abefd2b4037efd7f7245296bfdf9d
+k = 2bb0fb9c428e42482d5dbdb35157ad0fa713fe732dac8604c0194e3f9738fac5cf3874bd863718712a3da45b7c4612c8685465ecaec0930d9fec32ab25818d2f25fad580009b698
+R = 1062386d3e77043298eb88be46bd4e6f33c83a7358926b30ca06a6b7139815f6e1630f73d352a2cb9bc0619d08a89d4bde1636c74b6580543ed743073eec2ae0037bea2b3c9228e
+S = 1ceef759d804ff7de526559636d0bc7930c096c7b959f04f8fec5d7e96129fba14c8341b0ed84a64c6cce7cd5b058fab7f44dcf3e714544c9b6f9c1d46ce512870deb51856e9dec
+
+Msg = 12fea55ffda15db902aa6a4388b9807c89c193cbf75b5d2a4c95206fa43dedc45974c80079933451bdc5b3ea015ed3ca2c54156dc61afb1bc82adefed1491302a48b9d3d2f474ab45343c611677d360515b93fb36da7a1c1b2341c9cce185c881c0beef33d43967134a190c09034ae3261f3295b79aebd3fe123616f73cf2089
+d = 2139839ce38eb879d266065dde5e5ea227244323b330e3ad5a0bc690f3c210f794cf18f0d730693887548bfbc434f48ee10ed34cb41d52172b06e448df938170a5e17311cab8e88
+Qx = 2ecf46b90616b534ea25cc9993942fd7576a1c4f2f443d3b1f56d4490bf0af669c9eb9d110fe2a65609875e1a924bc4b9ed2ed2315047bbaeadaa1029b38a7a87dd8751d4128e80
+Qy = 2aec3a2f2557c7152a4907af68aa39485274f20927b2da70823440fbd09cbc308d46e30bd6b705f615b7074fe5421ca36b4aa53861983eceae9a69649495952e75b0f060b5d26e4
+k = 2e3412b61eb23d33ca2910dc25dd14c04d2c8b403d8077a72b9511d71ee9da6d7e1db093b92287f8fb00aea0576f6712c56d80cc4e3554e0faa9c7d911e3d17682de831bf649bd9
+R = 06a3075efec81a86175cd1dc2bfe82e83aff1db640184a6a3ed7a0dcdef51aa0be0005c54ac05f9b65af265af7f2ec3d1d7c137184b0d695d701ff1aed194faf2efa98ce6c5e502
+S = 237d7ff92480fa7d6d1f5a0564a2608afe5e95ce2c29dd88853d1ad9d4d2beb8d1f0423edb883faadd592394f52048bf2dc26d2dc19279477ed86621c7a5960ee3c3e2d345fda29
+
+Msg = c8395546842ddb545d8ea3db4efe970453dcb06025ac3b7a25aa5ef62070f3021b9a1fea91ff7055b6c398073e7886a6f71afe53c82c47b71377dfe291972503bbeb25bd477bf0e7adc8a5d3f8b34ccd0080d61e121214e1b29802b711cdd8a6bb2275a2395c467ec2c1571952992e448d736d8bd70ee629c75b5e32b8323a00
+d = 274f70fe69e4dbb55c5d404e39f5196335047113087f8711f2f67f2be4964e4fbcb865680758df1c401cd677b0971654b7a6aeb7bee0d6d80ac0de14d4f46f356b2d5545c185aa6
+Qx = 2b2321e0a1df083919628dd8b4c318b9ded8a3e660ce5585b21e46843228b4d32da765a3776c181654aad0ce90724bf85b01b051d236342b48d41a1dbda1e9904d659c98a039a97
+Qy = 20227182fcf099d46d9882c0b0f26b0595a2a3166248898df2f3fd27c78e7c0b8b59ef0ed6745660c0dea1acb567f9d943928864dd1e94f8eb6b5b8473c0c91485643189cf679d2
+k = 2f234066c936625fca10dd080cbbb1228c4d2054cbdeafc8a0a248c0d22807fc92c661b4f69586ecf9469bc4c22895cc73ecf492fb2165a12b027194d409677e7185de24f6870a3
+R = 3a48daa8e379b3b2f377049a4d462530c9ea67019752f4af4b4192b02d6e028386dcb9ef95c8019e90e09dfc8dff5e6f6812df491906ced39befedf16caef614d8c174e7ea95fc1
+S = 33f18738cb26d88c8c048c58a210c7be70c71636dc62c022df1bd7747d8c67bfcf5ff2fb3990ed35becf6c77755ac62aed480df55efea578671bd8d50536a10e2c0192bd42d78e2
+
+[B-571,SHA-512]
+
+Msg = 10d2e00ae57176c79cdfc746c0c887abe799ee445b151b008e3d9f81eb69be40298ddf37b5c45a9b6e5ff83785d8c140cf11e6a4c3879a2845796872363da24b10f1f8d9cc48f8af20681dceb60dd62095d6d3b1779a4a805de3d74e38983b24c0748618e2f92ef7cac257ff4bd1f41113f2891eb13c47930e69ddbe91f270fb
+d = 03e1b03ffca4399d5b439fac8f87a5cb06930f00d304193d7daf83d5947d0c1e293f74aef8e56849f16147133c37a6b3d1b1883e5d61d6b871ea036c5291d9a74541f28878cb986
+Qx = 3b236fc135d849d50140fdaae1045e6ae35ef61091e98f5059b30eb16acdd0deb2bc0d3544bc3a666e0014e50030134fe5466a9e4d3911ed580e28851f3747c0010888e819d3d1f
+Qy = 3a8b6627a587d289032bd76374d16771188d7ff281c39542c8977f6872fa932e5daa14e13792dea9ffe8e9f68d6b525ec99b81a5a60cfb0590cc6f297cfff8d7ba1a8bb81fe2e16
+k = 2e56a94cfbbcd293e242f0c2a2e9df289a9480e6ba52e0f00fa19bcf2a7769bd155e6b79ddbd6a8646b0e69c8baea27f8034a18796e8eb4fe6e0e2358c383521d9375d2b6b437f9
+R = 2eb1c5c1fc93cf3c8babed12c031cf1504e094174fd335104cbe4a2abd210b5a14b1c3a455579f1ed0517c31822340e4dd3c1f967e1b4b9d071a1072afc1a199f8c548cd449a634
+S = 22f97bb48641235826cf4e597fa8de849402d6bd6114ad2d7fbcf53a08247e5ee921f1bd5994dffee36eedff5592bb93b8bb148214da3b7baebffbd96b4f86c55b3f6bbac142442
+
+Msg = b61a0849a28672cb536fcf61ea2eb389d02ff7a09aa391744cae6597bd56703c40c50ca2dee5f7ee796acfd47322f03d8dbe4d99dc8eec588b4e5467f123075b2d74b2a0b0bbfd3ac5487a905fad6d6ac1421c2e564c0cf15e1f0f10bc31c249b7b46edd2462a55f85560d99bde9d5b06b97817d1dbe0a67c701d6e6e7878272
+d = 2e09ffd8b434bb7f67d1d3ccf482164f1653c6e4ec64dec2517aa21b7a93b2b21ea1eebb54734882f29303e489f02e3b741a87287e2dcdf3858eb6d2ec668f8b5b26f442ce513a2
+Qx = 36f1be8738dd7dae4486b86a08fe90424f3673e76b10e739442e15f3bfafaf841842ac98e490521b7e7bb94c127529f6ec6a42cc6f06fc80606f1210fe020ff508148f93301c9d3
+Qy = 4d39666ebe99fe214336ad440d776c88eb916f2f4a3433548b87d2aebed840b424d15c8341b4a0a657bf6a234d4fe78631c8e07ac1f4dc7474cd6b4545d536b7b17c160db4562d9
+k = 378e7801566d7b77db7a474717ab2195b02957cc264a9449d4126a7cc574728ed5a4769abd5dde987ca66cfe3d45b5fc52ffd266acb8a8bb3fcb4b60f7febbf48aebe33bd3efbdd
+R = 3d8105f87fe3166046c08e80a28acc98a80b8b7a729623053c2a9e80afd06756edfe09bdcf3035f6829ede041b745955d219dc5d30ddd8b37f6ba0f6d2857504cdc68a1ed812a10
+S = 34db9998dc53527114518a7ce3783d674ca8cced823fa05e2942e7a0a20b3cc583dcd930c43f9b93079c5ee18a1f5a66e7c3527c18610f9b47a4da7e245ef803e0662e4d2ad721c
+
+Msg = ba6be551bc60653192401ed8ff9e1acd9013d8811a7a1389528bf07438366f5772cd7aedad010c19c47622cec03a4d35b8003b39ed901b720629ab59de55a03c1ca50a62987f8da159e356245df58d5ae1936e65f3cd3acbe03ad1d0fcab4aaf2a7a947549ae776772201efbc6fab1aebfa1d99994d4f43dc28f39c0f279b992
+d = 2a69bc1df069c6e89722521a63675f318252be629e7558f3716917998e660ac960b0b750562846fe6c12ef492951e51e224754bab84a6eacd4147a5f26ae85ee4381bb14ec2a8c7
+Qx = 4685c0358ca31883cdfd7d609afa8b1e47540a97f473e0ebe98b0aaaab9418877aeead3a26fb01a4725fda20e7223a4fe7de0df6891c0812555b8b146918d3b80edd11615d95b77
+Qy = 67c92736447946c7577965b613e18950d813a4df049a6000895f9dac34d73ea46a83c6a4e7c83831af0d33026825664c44090953521175b9da2a7ac563a0fc5e13c85d34aaf49f2
+k = 1700d9ac00a987ff3a1d0be4290979317fe60f4f8ce1e0e72a026fc89e28c0070b76ada14f7a1a66ac2e8aef17eec18b568ada4fd59c05414e55356fc17d9e5079e6cabfc1f220d
+R = 23a279662efec48f6cf8c7334862525b52ac37a9b03da6a063da2849f87801563242783434fca02fa23e32249666ddc6f596e07750ed21de303f4f10de56f1d37101cb0826bb8bf
+S = 3b449467b150cba0d7c2b44280c5ac452f1217384ce121c979625d313394f6cef501b81980a02567ca55da2bc313dc0754b5256b08d8e3b63ea033253b205cc5dcb014574b8e9a0
+
+Msg = 295720a79ac8201f40a66b06ae5d970afb15f36582897eed25cd92edcd00f70ac8e31c556eed4375ea044c2e8b227a8e02c0a3e996c9272d52ac7b3ad43b80f217295dddc84b177cf1e800ad08bf7fdd021fb2f49b54162092f8d628679c4ee335abbc90c027264c8b288c6e16eca3172eaa297ba50626b00fe0a0ad3a9dbeeb
+d = 0d11ed1b78b22b3420df4ddc4acc7c2286d9569dd6dd88e0fa3ecae69bcced68bb81bbb4ca6e9b54e67856e7fdf39155aa27aecb9cc827ccb9cdcf9ac633561b27d8eebfc261aee
+Qx = 1868a1335058a69e3ce24ea4e6e8dc25851777bb28d3a5da67b741ec9c46e26f2d2ae70a48c3e4feabb3b15b3c3ebd561f667ef3b95a587621de6073b9c8a904755566c5f7a3b42
+Qy = 6365a03c3f3066eca1af17bbbd08cd52e89f8095075b415cd4b82f3364cbff008fe3642fe71e8a8c634ad0e5d9979251e6cedd42cb97c2203f743210051f5ee1b70c861d2a72c00
+k = 075e49d2ff6f2aa8b44fad90446474ee0e72323a3c39e731b6c2b075cce0cb9d193bc3356f8fdae0e0143603a57028836ee6451cab101a6eb550042cb41b5c4233d3ad3e87034d1
+R = 207a8eed0b87efe65ec558a0ccbecb13b9215e176abd93c1a4803fcae713927ece70ec6c41c621357d78a13a950958871a52621f1de7ab74befd964a0e8f4820b84af3e0811bc67
+S = 2f02017714f54089652e02af36ac5165e44ac4a83747c805a9e003fde4bdb29561dcead2c76b02c195074396a2dcc1b93a256c721716f8eeda8dae443c3eea446118fec3cebc4dc
+
+Msg = a9cff41c6dfdc4a12f31dc375a5455950077ae323d0b7a3d9a8dde73b76e9d7b94ddf9c88ae8e6c262d704052ac47681fc35adfc56c904baaa6e146eb653984369d76a85596cb744941aa7b558c945ff2e81bd5ef7f00ecb4f43af23b4cea3bd4ba7b1899f1868a0c0ecfc62ccb1d588955597ffbbaf34cab2838efc2b866669
+d = 2c36ef754b5bd065e9eadde684750acc52795be80f54dd3d7a7d743d968a18f7e404bd71f8a76eb0395f396df5a7c2ff7e0ab6de35df34282fda6ee01fe5b9b68ecb4e378dbe32e
+Qx = 4805e1a23b6eadcf91647b40903bc1fd3b9921861c942fc24d2c03d0544e7c01f004caeed04b5c4ebbce366a098a878c322cbebe7910bfb0f91b284ac1aef344152fc5831669b79
+Qy = 4f589ddb4da482ba1e9a59241b1dfbc7e9b9b69e8f69f8e90460ad58fdecc48a56842ea6aa0537abec0a605ebfb713e588685a98f62e05a7d52082bfd57e3d68fb7851b37ec5567
+k = 2f2002bdde0c0b0fd92e96abe76c0858e42fd7d94a181c711fc6753572539e18effa8155cde7b1e9ceab2394f9eba874b7ea257d7c308c8ac08500f4944af5f33057650608db8fe
+R = 27f9109799bced42730faecdeea68259383a45033c6d5dc8d87adf994b46beb34177e013700b13f1253cf756a8866218e9c8adc180f3c242c56b3de28405b36940d53c2aab24f1a
+S = 20a762ffb2f5a88b0e1356964fb558b555c424946109d16c7548f41a33cfe41da1f483276a27b188faf948a56670716ddf3b187570c9f514869c4492d7773d6ce453a075f9bc64f
+
+Msg = efa6c582d7fcf5e431aa89b3b00180c0e78efd7ccb0384d90b80e59a115a13e55001d951528c42860132531c9b8ab29dda7a657c53c2ce96fd85549f6f1810e121eb89961295335eaa0e40532d85814a4206e6fffdf9bff76599da9b2e71a22ed572910b0e3bae38ad72c7042579f106739a8628dea5a745168bd918736e488a
+d = 19ffee50be5496507e3ef5c40ee88a49625e46d1dd1686a52b09ad4a8e3ee9ef364f953bfcd97c52104eecb6138067192997cd4ebadaccb73c7b2560879289a46353a756b73cc43
+Qx = 77dca410e722009ef11b37742c2c003ab3015d0ca0328a70d9d41aae04cb64f7746f1c348b08458eb3bb1788f9ffe7d0570a9b689a9b7aca43e05400bace7630d598f5b484d13c4
+Qy = 7291f74cddd9ff69470cf0d92afaaddcc4c8c274d4a7a64fd94292ddc8bf080606795376bb725ab4d32c72ef77dff34cfedd34aff2f463d635bfcd7e1fd002d84383dc5bf8d5d23
+k = 2ea37750fc3bbdeec100694068d55f92fdf35bff9ed49251c4b8bbfb2dec2dd4446999af8848e05c7b819aeb1864430ab4e8c1d684e1cf78947a71b04d5ab8ad61cc7e3e4e24205
+R = 12ff1852eaff37fee997531039adb1fb2f9b4f4199670c022e8534625fff1fa93390ee9bc7204ad2ba3efc2233260943f1d2381a3cc025b78c6d1f660a7bd6f42e5ed3c123055a9
+S = 1b4d8abb28ef1a9d77066921ed50eba64b8433cf00c66b8467269a4a914f568cdb86c766a7a6a52437c5d98cfc9a2130dfaba20f3c2001f31bba7071647d51fb9fbd5fc67ee120f
+
+Msg = 211acebfaf13bba33a9dd16722ec53baab92a140127d61372cbf1850f2fc894e942e25d780778235f880743953d04eca7a9205602e388172aec2abf35412b483490751f93b51239b6701cb0aab14e5179b0d7f55d8586358381dd83e3e436bf69a6820317d1701750cb1fea1293467ba589eec5f5779c2dbf2a9b8f28c4dc239
+d = 3129e96fd28c4198cc5242c1e3531a3979fae643d527044e98d7721aa56b5b4b45dfddfa17a4115e10a2b4f46d92f81cbdd7e86e588a4c6d8c2b3a83f54cebcee1d1dd33e85d81a
+Qx = 73a92abcc991e3f89d82c47fa0fec48e3e7c4d97e2525f8dc2d24da39f616af4a5a804d2603703f6db7cc9324c5b56a21009373f6605f561c8503394e7746e51273b5722ffbc23d
+Qy = 0684c842f03a53a60cce087f4fcdbf23b7a28c48b6b6544f583342a65d97dd87037c6fef176a1f00513713468273494a5be683b68c5e75bc08995fde763bb6f965da1acb7e894f1
+k = 0165e52640fcaf8cbdbfe73cb8058c53045e7670aafb2def28d2c9eceb5ed1634b5339cc47ba981eb6eb03ba714c7717e9ed5acc15c8f304702a0409bd4508015d4626cfc5484b1
+R = 27dcdf16b7156a7a05a752da28b5bd6b233e8a7c16eb7f9030f29c4352e6508f8424d1b5ba789dac4152ac4812ff7975cce69908371a81a4d7d9dd70a8dabebdc4e3af27234f0d0
+S = 32a654a31f09a9803e502a1440c2bcf122780f4f47aa37e15991d9a548583fdca48800804712816b212cd3c657e6bd4cb7443a0288592541473c5086e1277250612c21346538374
+
+Msg = ee592e20e0a45c18089c2e41460e65a7d22ed9714379f095d43a308bdd383128aaa6fb24e9d35fd28fc95c5b792ad75c980d2cdf0f460ac60b12c5919d3cb28dac4d488196be6c2dfe462b1b0ce59f8501692255840f5215c0fd8b74b1996a267a5e3b22d2841cf0a0b6315ef4ec7180f1c8494f4c07d5869c01fa2711739efc
+d = 3d723d2697cd07dd8444f992f2ab4a063db334034c25ea9be99fd7a1f495e3a644e5ea033a41264e0d24a911e55741d0cab80a0bd678eaec2bd1e60424d4491eb86d664900d907e
+Qx = 0c7a229b5fb9fc774c1b6250f3bba2f0972d1aada7080641c014d012db0637a0656a43024ec0ea25ff70012646dc19eeb1033aebcc96a001ba876b2f5def6e198b8d4a53f7c7f4a
+Qy = 09228a68eafaac214fdfa19923a0c19629de31ac0967c9d02c53dbf221f9affb735d3bad732f381f1ca414d70920231a78f742254d895a33ffab492f8e6094a542e77962a324ba4
+k = 3b3724a5933353bb9ff5f742f59385e780caa517a963590b7fc89882bed95cf90ca6365ce8b882f2d96e56bd866a5c437733b681308c570c51ec893ea95fede66c7aaf4561173f7
+R = 2a487c1fc29426e8e85f0a35c177cd168a444959b2f5cd4519b9edd52af3ea829cfe964ac2b59198af8e2d3859ebdf9885ebf57bdf5767da1611d3958de286f91ef397230d65599
+S = 10fc01efcb22b982f992efb71887bc79c3f32a9088bc2011c269924cee0f47c36452399d499f2933587081b872e9fd2191c20cd5cd94927839228ebcf22cf7acdf4608a2fa66310
+
+Msg = fffca41927debbd53455821441d9115db99fb31bfc69752a382f57bc7abe021f148346ee29e17512c64b4918ab2391d12d6e5643bee6b5682885dc28177b292e23a37ff99b359b9cf7578432af56e0ad1028a6cce7428980654c145af8daf09addbb3be11228d3c742defca9d3b1667f48c63091fe3307ecf72667b02e008f24
+d = 1999ab45d66cd1d3a0fe6aa43bf5ef1e2a67637d53674f6fbbfb9b582be91fc42a12cdcad94b50b0fc7ac55030de24a0b99fbc4314fa743ef4b5198bcc5f54d8b669fbed78e2e91
+Qx = 0cbf3b0bb4a2e6c225aa922bea3b233da4661df5da7e0a1cd343a9b6655ee87fc60cd763dee21eaa2b81c4dd5af6f4fadc3ceea643b37a6b17a6501e1b9b689fb0c4716911c1f10
+Qy = 14b5a9ae025f09066fffa6797ddf95f27eeade06b8ca5be5738f770362d5213c46ecfca58e3c60cb2bae1f8ab1bf0577c80b4fdad02819fc174cafb33df64fc0ec79713f7b25209
+k = 253b533d3ad1c7095363e3fc80cb32471061e44dab3f9ae0ea6252f6ef169cee8badd3eccb77096ae9224f89baeee7e183058579680661655fb689419e36a61e8573de5ecb4cd09
+R = 3ba94f7682fb61de725a35caf1d4d799c4b05a1d1c44eb1c251dd8efab6b7d713c3fb917776902a1bb202f9226558f4c1e75964349717e6dff938d0befea07a9ca1bbd429dd6318
+S = 226f43be8e24062180c726b5cb721cc04ffd3acd82183925523ff9e8631aecbec2c224d5a291bb225f0da726d256aa822ee7cc2c7d69df3f2a5beb21132d91bea22e4c5db900cec
+
+Msg = a2f71619ea04f7057e6943c2cece8594b341ec3b96c3915d924f94ba13fd7aaeed41ffa0e842ade414784f1ef825fcf2dbcf7bd8263b802def45f94de596aec0c121fc06558c7bb06b9f27a9bf56c42090b5dc344e82b69c4f528d33be166764a593483f6fda0cf56e6000ff363ba220f5ea0ea2c3191615c7ae3bb4fa575324
+d = 2ce1cae0716205330d730e6bc6dbfb6b951dc83ee3b4a7dae75d057e32e8a46e22be75b5f09135452b29c34dfe81a9be2e8dcd243fbd946a0ed14a832a7802e20cfe1abfd3d6e4b
+Qx = 75971399fa621ce535144ec1d57f544d798a0a59207166c3d657e5a80ac00e8f5b643448e3546064d68ae624aaabf36face3016561a248256ff9131950ab8b04710551e12222d0c
+Qy = 224a50f321647f47de3db4fbe1bf1e3a3dce8a834312779f66037315e3326721e3fd63d4d6ef92b7ba1fa9aeb70f92e2a6701458ac8da49ac386491f2306adcd8dd781fe75e99e1
+k = 0ad95aa69cf9f40e13f8a72ed6d93388168abc8001670ee4d95fb4b726b1f958205ab2f458df8bb9ccf2405680d0e6951abbb922cc11d47cfded93c0efdb70caf0c54e7ae96d7e5
+R = 09ce019161bf29eeaf323933045f59d2efc372904ba50c4a6602b8305234a851d95f06a5b56193ad5d28488102ec25e3f421a5f5c4626b435b423d612e6ab60e0a4fe5d4952e2c5
+S = 04f7b7ac787b361c2bdfa767da9c22152e402184a7ac133f651fdcd928239215dc917401122a6d41e78299b4235e085399e594465b7f8dbfaae9bf302d83470b4295ea06bb9bd1e
+
+Msg = b60415a831eca2cf60c79a334ef2f327a76d290846ee588d5d33d0a826bb0c7ec3e11dbb384a7f89c8d180425dfae7463e0ea6497d2eec1dde112f1c1efccb532a2e2b66a28e2d36d4252a4c3b12850d465fe21bddc441b92e6a7b0f67744f7f6e7812a0603211a26518b311a5b190ed890ad852bed4f6ed13377cab3eebedf4
+d = 2c9d0fcfcee7e75c3245ba955ae04188b1033c55ec9c821d8de7685276bda3e9a93c3ae1b003e5ea722913e7b169d67b1aa2dc8cd42adbd9368672a3f81a6817bf3e5529dcb0c8b
+Qx = 19cba4c8ddadb596d7303331f2a22461849ebfbc78ea69277f72dcfe23d08397025ff6691c61ed9958d68a9c5dd8a32048a89a2553afb9077ec43358763756b1473ab2cd8f25b53
+Qy = 319eeaa78444b7cc5d8cff4e9199ddd2c6dc7bd935a1be1d8b1c657dd5ac49bc92b0cd91304ef44ddb7ecac05518301bfa0e533402043533f99549621e31dcc282a52186478df2b
+k = 385e12170ed0b23c9c65ff7edd413145fd343dd841e85c498fae5f36e57764168899902817d4dc39127010faa1da68000a511ac69f80708be5afe1631432f3bab7aaec2bdeb11b4
+R = 231ef400c6a3a0c7b26ba1b92341b72e138ca62d04ea2172854631c40c48081a18a57e9f055748245d3e83d10d21af39935b0e50c9c86956ac46c1ea03ac4ae023d84b24f830973
+S = 24d37d67afafb0676cd7b5da2960cabfc804b0b3244b5e6739f8fe43d0841693d28c61b8e76181f8aa24940d76fc5ea8ef3a95f72f67303e1ed85ad6e83cd2c44fd0e0f3f2f44f4
+
+Msg = 5d15a08226cc74cf495be681b795d0bde26b19f29aca1a8c6ef77d50271ebdcb4e5fa2df23961fe11620b1c6580183f6ebdceb2c09516c8127be576496fb71449bbbf0a9d3d1c48a25024619b97c3e0d8b165897db96ae9758d13ac28441d7cbfb75b23cb423e0002046358bb6d64779974a5995dfe54b398f95f7d64fc52d96
+d = 10c057bbaa44ef0f565edc288bfe66d4f6acd8686899359bca418ba89fb690429489a37bd3c6c9f3a8714b2ca225868c6a45fee360e378a676f7ea39321790f32a4b005b81dce43
+Qx = 43b1e7d7b2aee3563813a6692f0b4b61ba82b801697c3e23724a2fbab2af80a2c56be55af41def0a90cbfce7a45ec61629906055a8b2a5013740e96859e580c444ae9f0ddf73afe
+Qy = 6742f13244f1bf156d321eab2c3095ca548c3182c405187c3de2fbcb01d0e16e1fef246012c87d4d32378629a75b694572ec8583ae0cc813ac64f10bb05a9e52e4805590482f289
+k = 2b8076102a6448bd4c4e192e93cdb96ea9a6c7f6753818267ee9e67644df1a4a6c9ff64bbe9f64904648cc640fb7f0cce69f9e02878ee950b91ad559a9ec0ae15b676d933f1620f
+R = 1ad97f4997037adfe306f3859d550f9fd89bce8b566e657d5742feb17466b6b8d507d5810a8cbba44d671b043ddb557df084bf5d1de74ef8bbd6a93690459fc16a17b80dd6c0f28
+S = 3262ef6e4175e7afe095d18157f67b3d12564d54954e9964e991c31bcfe1dee7e86b35491ce818400cc0f83b819f478f2f2c2d21c6c7a6be43938841559e09bce70b0d61fe51245
+
+Msg = 9eca4bd88200baf61b901fca53dc1f1e7e3f83b94d58a6cc6a2adbc9b1a35fe3f8ec61787c76ed9a0d696167cd4fe46e1a0883fda564666131753c576a720125e0b712db1da0278067cb899bdb14eec08737e864544663abb1d62f34a2114be07e8e3cf56e2d17099299ce6b6d83b1a34e6153d7c6a32a72c7b1bf4583fcbcf7
+d = 2c182df7976ea93d996f3ba5d2221f3cb755cc7847bc3fe9e022fa4285046f5bfb426bafa3580beea206de36f87593ae561b4b74a03fcd61fbd0e8d6fd5668f2148819a88a650aa
+Qx = 6004b26a184ed710a5fb67e9d042f7fb9c8f5584b1f70a91b0b3be41c3fd2cd1a537e962fdac8756df33f80fce2bb1bc7241d325bfc36dbaef7cf625918d589b6352fa744718910
+Qy = 36a29b04a494abfe809d956c3cd6f84ea51a7fa28cb39a52f16137a13f72f0726a84f6ae53ae24f5b468733f4cbfa0ce5bbbc1cc7b348fb996d33a45ff656a6a7557619f598a6b7
+k = 2ab349232bcb4f4816b26bd0049e130fffc90ca0b9308edd50fb9055358a87fe798d00140b0ae01ed8b1f6bb9bfb726b253c3d4949ce9eecaa6c7fa84d1ef812669fa929f26be0f
+R = 0bbf2f9765b12742224ba7d064358c0305fb63e9b54a831e302a4546aa02cace798d82a188d2f536d78544c1571f481289d6ec69d117648026490e781f1eb9fca59bee05234ba7e
+S = 27e07ee0a1a99c90753cdc8c0291da25a82c116e62ec58b93f91086ac1cc039b35ce7d8b53cdaa92a5ade65a7684b6e7ab79873dce33dcd467c39d0c764ee390b7fb25ca18912c3
+
+Msg = 707450bd84141f3b61beb12ffa5ae89d812dd11badcdf6a88a2d50fc70e23f6d822ff4477047abc58cdfa28f97ad7f4911ae0773c04ebed1f51bb2308cf6e5712c4aaed461edd6987fdd1796aab70198276b601241f6a14225dce575830ff60f935fd9f567d1d210652e4710922fa793da78c8fdc30c273cb08365c9fc887f50
+d = 2d3a65bbe133cc98cf0eb56ee1362195968b4eab960a1d55d8b762f1361fc21348d6f275d4bea1de7158fb97c995e20b92a9c887a3e332d154667ad167acc632eb88a0ead6113a2
+Qx = 34355b54d00c3df7c2762ee2982cb777491aaf78e550c4d2ff5d5a893416eb3517671dbe522b8c553fd71edfe0306cd7628324f4f748091fc5d84ad8af33b896985674649a6f4e5
+Qy = 7e322a04eb600a3faf3e045959f1e9f798e1c965ced40fd4c0383c0d4e79a96bf693a91d7662780990d0c9dfca77a9bc0e13551d2ab35af8a153fa34ea903961fe66996ca053b64
+k = 0a59ac1240bcefc52456486ce23b780cc92c8b89314b8442a6898c373bd0adc3725e3ebac580546d1ec82ebfb2e04c608441d962d759ab5f5af1596c6623487e1347537a3c35bf4
+R = 0c47ef55d93ac36cee537160bbe39c3d4504184188533edfe589a5ab6e5a3e06ef413aa48710d304f0b2bc380fd69a34aa0b8e2e9466fd8a131cb056dffe4b809a59fd83e594483
+S = 2d8de1e8e2a52dd1be08435cda69e673b328573edeb1767849536e6f2d5fc8f18f7bfde936d8c32ecbfa97bf976133d65641320ca1c41e81c388fd6088884bbd89274b1976470fc
+
+Msg = d5ce9d59391cdc47ef942dd2a818d024ae3917deea8a5a4214e4db6a0c5e6b0936f3e632fdb68a3f0006e05c44b7232013e1da5f877cd197f44fd6f60c1fd2378995e9a47534948c5a09e33750f07a7165072ab38095373b07a50bc1391eb6b650ee13acd63d0352e7d9c31695ea1ec6323f9b5f57b426ace56aa7fdbf419be0
+d = 2a920e8dc928acdd56e3655b2340d4371c793e66f67405fb7a90f31e9c4ef466cc44331d1d2fe3ff7391d2576dc6640772166ef8c154a5ff1808f5dab2f03061070ec8b3f786c36
+Qx = 5edc0fb974314e21ad40d73524d5620b7279084e3ecb9e58b06340ae53d2383efd206b8b1eb3dd60c38f593efc05e2ba5fb8989472bac7db60fcada2d18d4108ab36e8c20cc710d
+Qy = 0444cf65175f6bbaf647739cfd8407e7036fc6cc6208ccb9d776eb13e13b377136c683e108775d85b6bc5638926432a17344de965d45e042a0a8e0b63c7fc3a36fc15cf718f3baf
+k = 35a0215892d0c52ece29559ebfa061011da8d597af6b3d1ee988ea4819be194c79a42681476140738b1b5dc191485bd20c96c282ab38ddbc3987343155366b6a5d1ce7053efcd83
+R = 1a69a9a51f6b0dc196b2a8db2e8bf61764d4c65b038f43b5ed6b5dc2673971c32928606f92b7caafb4dab3cd61ee724bba71a0d5c788cde4b96ef6b453f2a69126dafc20dbc7c82
+S = 13b5463636b8462cd9f479de8d114e29e7011489bcb9735ffe9ca0707a07df3c0aba05043eab387bfedd9fe982fbf04968f2be200e9e052cb4b02223b8579913d713acf94e7dc80
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/main.c
new file mode 100644
index 000000000..dbad06477
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/main.c
@@ -0,0 +1,439 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/PKA/PKA_ECDSA_Sign/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to use PKA peripheral to generate an
+  *          ECDSA signature using the STM32WBxx PKA LL API.
+  *          Peripheral initialization done using LL unitary services functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+__IO uint32_t endOfProcess = 0;
+uint8_t RBuffer[32] = {0};
+uint8_t SBuffer[32] = {0};
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_PKA_Init(void);
+/* USER CODE BEGIN PFP */
+
+void     LED_On(void);
+void     LED_Blinking(uint32_t Period);
+static uint32_t Buffercmp(const uint8_t* pBuffer1,const uint8_t* pBuffer2, uint32_t BufferLength);
+__IO uint32_t *PKA_Memcpy_u8_to_u32(__IO uint32_t dst[], const uint8_t src[], uint32_t n);
+uint8_t *PKA_Memcpy_u32_to_u8(uint8_t dst[], __IO const uint32_t src[], uint32_t n);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  uint32_t result = 0;
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_PKA_Init();
+  /* USER CODE BEGIN 2 */
+  
+  /* Set mode to ECDSA signature generation in interrupt mode */
+  LL_PKA_SetMode(PKA, LL_PKA_MODE_ECDSA_SIGNATURE);
+  LL_PKA_EnableIT_ADDRERR(PKA);
+  LL_PKA_EnableIT_RAMERR(PKA);
+  LL_PKA_EnableIT_PROCEND(PKA);
+  
+  /* Loads the input buffers to PKA RAM */
+  PKA->RAM[PKA_ECDSA_SIGN_IN_ORDER_NB_BITS] = prime256v1_Order_len * 8;
+  PKA->RAM[PKA_ECDSA_SIGN_IN_MOD_NB_BITS] = prime256v1_Prime_len * 8;
+  PKA->RAM[PKA_ECDSA_SIGN_IN_A_COEFF_SIGN] =  prime256v1_A_sign;
+
+  /* Move the input parameters coefficient |a| to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_A_COEFF], prime256v1_absA, prime256v1_Prime_len);
+  PKA->RAM[PKA_ECDSA_SIGN_IN_A_COEFF + prime256v1_Prime_len / 4] = 0;
+
+  /* Move the input parameters modulus value p to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_MOD_GF], prime256v1_Prime, prime256v1_Prime_len);
+  PKA->RAM[PKA_ECDSA_SIGN_IN_MOD_GF + prime256v1_Prime_len / 4] = 0;
+
+  /* Move the input parameters integer k to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_K], SigGen_k, prime256v1_Prime_len);
+  PKA->RAM[PKA_ECDSA_SIGN_IN_K + prime256v1_Prime_len / 4] = 0;
+
+  /* Move the input parameters base point G coordinate x to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_X], prime256v1_GeneratorX, prime256v1_Prime_len);
+  PKA->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_X + prime256v1_Prime_len / 4] = 0;
+
+  /* Move the input parameters base point G coordinate y to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y], prime256v1_GeneratorY, prime256v1_Prime_len);
+  PKA->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y + prime256v1_Prime_len / 4] = 0;
+
+  /* Move the input parameters hash of message z to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_HASH_E], SigGen_Hash_Msg, prime256v1_Prime_len);
+  PKA->RAM[PKA_ECDSA_SIGN_IN_HASH_E + prime256v1_Prime_len / 4] = 0;
+
+  /* Move the input parameters private key d to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D], SigGen_d, prime256v1_Prime_len);
+  PKA->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + prime256v1_Prime_len / 4] = 0;
+
+  /* Move the input parameters prime order n to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_ORDER_N], prime256v1_Order, prime256v1_Prime_len);
+  PKA->RAM[PKA_ECDSA_SIGN_IN_ORDER_N + prime256v1_Prime_len / 4] = 0;
+  
+  /* Launch the computation in interrupt mode */
+  LL_PKA_Start(PKA);
+  
+  /* Wait for the interrupt callback */
+  while(endOfProcess != 1);
+  
+  /* Retreive the result and output buffer */
+  result = PKA->RAM[PKA_ECDSA_SIGN_OUT_ERROR];
+  PKA_Memcpy_u32_to_u8(RBuffer, &PKA->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], prime256v1_Prime_len / 4);
+  PKA_Memcpy_u32_to_u8(SBuffer, &PKA->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], prime256v1_Prime_len / 4);
+  
+  /* Compare to expected results */
+  if (result != 0)
+  {
+    LED_Blinking(LED_BLINK_ERROR);
+  } 
+  
+  result = Buffercmp(RBuffer, SigGen_R, SigGen_R_len);
+  if (result != 0)
+  {
+    LED_Blinking(LED_BLINK_ERROR);
+  }  
+  
+  result = Buffercmp(SBuffer, SigGen_S, SigGen_S_len);
+  if (result != 0)
+  {
+    LED_Blinking(LED_BLINK_ERROR);
+  }  
+  
+  LED_On();
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  /* HSI configuration and activation */
+  LL_RCC_HSI_Enable();
+  while(LL_RCC_HSI_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the HSI */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(16000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(16000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief PKA Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_PKA_Init(void)
+{
+
+  /* USER CODE BEGIN PKA_Init 0 */
+
+  /* USER CODE END PKA_Init 0 */
+
+  /* Peripheral clock enable */
+  LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PKA);
+
+  /* USER CODE BEGIN PKA_Init 1 */
+
+  /* USER CODE END PKA_Init 1 */
+  LL_PKA_Enable(PKA);
+  /* USER CODE BEGIN PKA_Init 2 */
+
+    /* Configure NVIC for PKA interrupts */
+    /*   Set priority for PKA_IRQn */
+    /*   Enable PKA_IRQn */
+    NVIC_SetPriority(PKA_IRQn, 0);  
+    NVIC_EnableIRQ(PKA_IRQn);  
+
+  /* USER CODE END PKA_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+void PKA_ERROR_callback(void)
+{
+  LED_Blinking(LED_BLINK_ERROR);
+}
+
+void PKA_PROCEND_callback(void)
+{
+  endOfProcess = 1;
+}
+/**
+  * @brief  Compares two buffers.
+  * @param  pBuffer1, pBuffer2: buffers to be compared.
+  * @param  BufferLength: buffer's length
+  * @retval 0  : pBuffer1 identical to pBuffer2
+  *         >0 : pBuffer1 differs from pBuffer2
+  */
+static uint32_t Buffercmp(const uint8_t* pBuffer1,const uint8_t* pBuffer2, uint32_t BufferLength)
+{
+  while (BufferLength--)
+  {
+    if ((*pBuffer1) != *pBuffer2)
+    {
+      return BufferLength;
+    }
+    pBuffer1++;
+    pBuffer2++;
+  }
+
+  return 0;
+}
+
+/**
+  * @brief  Copy uint8_t array to uint32_t array to fit PKA number representation.
+  * @param  dst Pointer to destination
+  * @param  src Pointer to source
+  * @param  n Number of u32 to be handled
+  * @retval dst
+  */
+__IO uint32_t *PKA_Memcpy_u8_to_u32(__IO uint32_t dst[], const uint8_t src[], uint32_t n)
+{
+  const uint32_t *ptrSrc = (const uint32_t *) src;
+
+  if (dst != 0)
+  {
+    for (uint32_t index = 0; index < n / 4; index++)
+    {
+      dst[index] = __REV(ptrSrc[n / 4 - index - 1]);
+    }
+  }
+  return dst;
+}
+
+/**
+  * @brief  Copy uint32_t array to uint8_t array to fit PKA number representation.
+  * @param  dst Pointer to destination
+  * @param  src Pointer to source
+  * @param  n Number of u8 to be handled (must be multiple of 4)
+  * @retval dst
+  */
+uint8_t *PKA_Memcpy_u32_to_u8(uint8_t dst[], __IO const uint32_t src[], uint32_t n)
+{
+  uint32_t *ptrDst = (uint32_t *) dst;
+  if (dst != 0)
+  {
+    for (uint32_t index = 0; index < n; index++)
+    {
+      ptrDst[n - index - 1] = __REV(src[index]);
+    }
+  }
+  return dst;
+}
+
+/**
+  * @brief  Turn-on LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_On(void)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin); 
+}
+
+/**
+  * @brief  Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
+  * @param  Period : Period of time (in ms) between each toggling of LED
+  *   This parameter can be user defined values. Pre-defined values used in that example are :
+  *     @arg LED_BLINK_FAST : Fast Blinking
+  *     @arg LED_BLINK_SLOW : Slow Blinking
+  *     @arg LED_BLINK_ERROR : Error specific Blinking
+  * @retval None
+  */
+void LED_Blinking(uint32_t Period)
+{
+  /* Toggle LED2 in an infinite loop */
+  while (1)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin); 
+    LL_mDelay(Period);
+  }
+}
+
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/prime256v1.c b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/prime256v1.c
new file mode 100644
index 000000000..ce2dc5e3c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/prime256v1.c
@@ -0,0 +1,96 @@
+/**
+  ******************************************************************************
+  * @file    PKA/PKA_ECDSA_Sign/Src/prime256v1.c
+  * @author  MCD Application Team
+  * @brief   This file contains reference buffers containing the description of
+  *          nist P-256 (ECDSA-256) published by NIST in Federal Information 
+  *          Processing Standards Publication FIPS PUB 186-4.
+  *          Additionnal buffer are provided to be used with PKA like abs(A)
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+  
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+const uint8_t prime256v1_Prime[] = {
+/*0x00,*/ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff
+};
+const uint32_t prime256v1_Prime_len = 32;
+
+const uint8_t prime256v1_A[] = {
+/*0x00,*/ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xfc
+};
+/* PKA operation need abs(a) */
+const uint8_t prime256v1_absA[] = {
+/*0x00,*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x03
+};
+const uint32_t prime256v1_A_len = 32;
+
+/* PKA operation need the sign of A */
+const uint32_t prime256v1_A_sign = 1;
+
+const uint8_t prime256v1_B[] = {
+    0x5a, 0xc6, 0x35, 0xd8, 0xaa, 0x3a, 0x93, 0xe7, 0xb3, 0xeb, 0xbd, 0x55, 0x76, 0x98, 0x86,
+    0xbc, 0x65, 0x1d, 0x06, 0xb0, 0xcc, 0x53, 0xb0, 0xf6, 0x3b, 0xce, 0x3c, 0x3e, 0x27, 0xd2,
+    0x60, 0x4b
+};
+const uint32_t prime256v1_B_len = 32;
+
+const uint8_t prime256v1_Generator[] = {
+    0x04, 0x6b, 0x17, 0xd1, 0xf2, 0xe1, 0x2c, 0x42, 0x47, 0xf8, 0xbc, 0xe6, 0xe5, 0x63, 0xa4,
+    0x40, 0xf2, 0x77, 0x03, 0x7d, 0x81, 0x2d, 0xeb, 0x33, 0xa0, 0xf4, 0xa1, 0x39, 0x45, 0xd8,
+    0x98, 0xc2, 0x96, 0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a,
+    0x7c, 0x0f, 0x9e, 0x16, 0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40,
+    0x68, 0x37, 0xbf, 0x51, 0xf5
+};
+const uint32_t prime256v1_Generator_len = 65;
+
+/* This buffer is extracted from prime256v1_Generator as its first part */
+const uint8_t prime256v1_GeneratorX[] = {
+    0x6b, 0x17, 0xd1, 0xf2, 0xe1, 0x2c, 0x42, 0x47, 0xf8, 0xbc, 0xe6, 0xe5, 0x63, 0xa4, 0x40, 
+    0xf2, 0x77, 0x03, 0x7d, 0x81, 0x2d, 0xeb, 0x33, 0xa0, 0xf4, 0xa1, 0x39, 0x45, 0xd8, 0x98, 
+    0xc2, 0x96
+};
+const uint32_t prime256v1_GeneratorX_len = 32;
+
+/* This buffer is extracted from prime256v1_Generator as its second part */    
+const uint8_t prime256v1_GeneratorY[] = {
+    0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a, 0x7c, 0x0f, 0x9e, 
+    0x16, 0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40, 0x68, 0x37, 0xbf, 
+    0x51, 0xf5
+};
+const uint32_t prime256v1_GeneratorY_len = 32;
+
+const uint8_t prime256v1_Order[] = {
+/*0x00,*/ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xbc, 0xe6, 0xfa, 0xad, 0xa7, 0x17, 0x9e, 0x84, 0xf3, 0xb9, 0xca, 0xc2, 0xfc,
+    0x63, 0x25, 0x51
+};
+const uint32_t prime256v1_Order_len = 32;
+
+const uint32_t prime256v1_Cofactor = 1; /* (0x1) */
+
+const uint8_t prime256v1_Seed[] = {
+    0xc4, 0x9d, 0x36, 0x08, 0x86, 0xe7, 0x04, 0x93, 0x6a, 0x66, 0x78, 0xe1, 0x13, 0x9d, 0x26,
+    0xb7, 0x81, 0x9f, 0x7e, 0x90
+};
+const uint32_t prime256v1_Seed_len = 20;
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..586304697
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/stm32wbxx_it.c
@@ -0,0 +1,235 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/PKA/PKA_ECDSA_Sign/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * Brief   This function handles PKA Instance interrupt request.
+  * Param   None
+  * Retval  None
+  */
+void PKA_IRQHandler(void)
+{
+  /* Manage the PKA RAM error flag */
+  if(LL_PKA_IsActiveFlag_RAMERR(PKA) == 1)
+  {
+    LL_PKA_ClearFlag_RAMERR(PKA);
+    PKA_ERROR_callback();
+  }
+  
+  /* Manage the Address error flag */
+  if(LL_PKA_IsActiveFlag_ADDRERR(PKA) == 1)
+  {
+    LL_PKA_ClearFlag_ADDERR(PKA);
+    PKA_ERROR_callback();
+  }
+  
+  /* Manage the PKA End of Operation flag */
+  if(LL_PKA_IsActiveFlag_PROCEND(PKA) == 1)
+  {
+    LL_PKA_ClearFlag_PROCEND(PKA);
+    PKA_PROCEND_callback();
+  }
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/readme.txt
new file mode 100644
index 000000000..38d9c97ac
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PKA/PKA_ECDSA_Sign/readme.txt
@@ -0,0 +1,79 @@
+/**
+  @page PKA_ECDSA_Sign PKA : Public Key Accelerator
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/PKA/PKA_ECDSA_Sign/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the PKA_ECDSA_Sign example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to use the low-layer PKA API to generate an ECDSA signature.
+
+Example execution:
+After startup from reset and system configuration, PKA configuration is performed.
+
+To demonstrate the generation of an ECDSA signature, input and output buffers of this
+example are extracted from National Institute of Standards and Technology (NIST)
+Cryptographic Algorithm Validation Program (CAVP) (http://csrc.nist.gov/groups/STM/cavp/).
+
+One test vector has been extracted from section [P-256,SHA-256] of 
+http://csrc.nist.gov/groups/STM/cavp/documents/dss/186-3ecdsatestvectors.zip
+and adapted to C buffers in SigGen.c and SigGen.h.
+
+The example:
+  Loads the input buffers to PKA RAM.
+  Launch the computation in interrupt mode.
+  Wait for the interrupt callback.
+  Retreive the output buffer.
+  Compare to expected results.
+
+After successful sequence, LED2 is turned On. 
+In case of errors, LED2 is slowly blinking (1sec period).
+
+@par Keywords
+
+PKA, interrupt, ECDSA, signature, NIST, CAVP
+
+@par Directory contents 
+
+  - PKA/PKA_ECDSA_Sign/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - PKA/PKA_ECDSA_Sign/Inc/main.h                  Header for main.c module
+  - PKA/PKA_ECDSA_Sign/Inc/stm32_assert.h          Template file to include assert_failed function
+  - PKA/PKA_ECDSA_Sign/Src/stm32wbxx_it.c          Interrupt handlers
+  - PKA/PKA_ECDSA_Sign/Src/main.c                  Main program
+  - PKA/PKA_ECDSA_Sign/Src/system_stm32wbxx.c      STM32WBxx system source file
+  - PKA/PKA_ECDSA_Sign/Src/prime256v1.c            Description of P-256 (ECDSA-256)
+  - PKA/PKA_ECDSA_Sign/Inc/prime256v1.h            Header for prime256v1.c
+  - PKA/PKA_ECDSA_Sign/Src/SigGen.c                Reflect the content of the test vector from SigGen.txt
+  - PKA/PKA_ECDSA_Sign/Src/SigGen.txt              Extract from NIST CAVP
+  - PKA/PKA_ECDSA_Sign/Inc/SigGen.h                Header of SigGen.c
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example and observe the LED status
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/PWR_EnterStandbyMode.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/PWR_EnterStandbyMode.ewd
new file mode 100644
index 000000000..396b4fd7e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/PWR_EnterStandbyMode.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		PWR_EnterStandbyMode
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/PWR_EnterStandbyMode.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/PWR_EnterStandbyMode.ewp
new file mode 100644
index 000000000..180ea315c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/PWR_EnterStandbyMode.ewp
@@ -0,0 +1,1083 @@
+
+
+  3
+  
+    PWR_EnterStandbyMode
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/Project.eww
new file mode 100644
index 000000000..17d2774c3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\PWR_EnterStandbyMode.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Inc/main.h
new file mode 100644
index 000000000..ad999b884
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Inc/main.h
@@ -0,0 +1,124 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/PWR/PWR_EnterStandbyMode/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+
+/**
+  * @brief Toggle periods for various blinking modes
+  */
+
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW  500
+#define LED_BLINK_ERROR 1000
+
+
+/**
+  * @brief Key push-button
+  */
+#define USER_BUTTON_PIN                         LL_GPIO_PIN_0
+#define USER_BUTTON_GPIO_PORT                   GPIOA
+#define USER_BUTTON_GPIO_CLK_ENABLE()           LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);   
+#define USER_BUTTON_EXTI_LINE                   LL_EXTI_LINE_0
+#define USER_BUTTON_EXTI_IRQn                   EXTI0_IRQn
+#define USER_BUTTON_EXTI_LINE_ENABLE()          LL_EXTI_EnableIT_0_31(USER_BUTTON_EXTI_LINE)   
+#define USER_BUTTON_EXTI_FALLING_TRIG_ENABLE()  LL_EXTI_EnableFallingTrig_0_31(USER_BUTTON_EXTI_LINE)
+#define USER_BUTTON_EXTI_RISING_TRIG_ENABLE()   LL_EXTI_EnableRisingTrig_0_31(USER_BUTTON_EXTI_LINE)   
+#define USER_BUTTON_SYSCFG_SET_EXTI()           LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTA, LL_SYSCFG_EXTI_LINE0);
+#define USER_BUTTON_IRQHANDLER                  EXTI0_IRQHandler
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+/* IRQ Handler treatment. User BUTTON handler treatment */
+void UserButton_Callback(void); 
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..c82c91f14
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/PWR/PWR_EnterStandbyMode/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void USER_BUTTON_IRQHANDLER(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/MDK-ARM/PWR_EnterStandbyMode.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/MDK-ARM/PWR_EnterStandbyMode.uvoptx
new file mode 100644
index 000000000..6f050f0de
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/MDK-ARM/PWR_EnterStandbyMode.uvoptx
@@ -0,0 +1,333 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    PWR_EnterStandbyMode
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/MDK-ARM/PWR_EnterStandbyMode.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/MDK-ARM/PWR_EnterStandbyMode.uvprojx
new file mode 100644
index 000000000..51d19db5e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/MDK-ARM/PWR_EnterStandbyMode.uvprojx
@@ -0,0 +1,471 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      PWR_EnterStandbyMode
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          PWR_EnterStandbyMode\
+          PWR_EnterStandbyMode
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/PWR_EnterStandbyMode.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/PWR_EnterStandbyMode.ioc
new file mode 100644
index 000000000..8a0e48f22
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/PWR_EnterStandbyMode.ioc
@@ -0,0 +1,111 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB0
+Mcu.Pin1=VP_SYS_VS_Systick
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=PWR_EnterStandbyMode.ioc
+ProjectManager.ProjectName=PWR_EnterStandbyMode
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..ab6b726a8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/.project
new file mode 100644
index 000000000..4357a70cf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/.project
@@ -0,0 +1,80 @@
+
+
+	PWR_EnterStandbyMode
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			PWR_EnterStandbyMode.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/PWR_EnterStandbyMode.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Src/main.c
new file mode 100644
index 000000000..123d242ae
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Src/main.c
@@ -0,0 +1,437 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/PWR/PWR_EnterStandbyMode/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to enter and exit the Standby mode with
+  *          a wakeup pin or external reset through the STM32WBxx PWR LL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define BUTTON_MODE_GPIO  0
+#define BUTTON_MODE_EXTI  1
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+/* USER CODE BEGIN PFP */
+
+void     Configure_PWR(void);
+void     LED_Blinking(uint32_t Period);
+void     UserButton_Init(uint32_t Button_Mode);
+uint32_t UserButton_GetState(void);
+void     EnterStandbyMode(void);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* Initialize User push-button (SW1) in GPIO mode */
+  UserButton_Init(BUTTON_MODE_GPIO);
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Initialize User push-button (SW1) in EXTI mode */
+  UserButton_Init(BUTTON_MODE_EXTI);
+  
+  /* Configure Power IP */
+  Configure_PWR();
+  /* Led blinking in Run mode */
+  LED_Blinking(LED_BLINK_FAST);
+  
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* MSI configuration and activation */
+  LL_RCC_MSI_Enable();
+  while(LL_RCC_MSI_IsReady() != 1)
+  {
+  };
+
+  /* Main PLL configuration and activation */
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 32, LL_RCC_PLLR_DIV_2);
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the main PLL */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(64000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(64000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
+  * @param  Period : Period of time (in ms) between each toggling of LED
+  *   This parameter can be user defined values. Pre-defined values used in that example are :
+  *     @arg LED_BLINK_FAST : Fast Blinking
+  *     @arg LED_BLINK_SLOW : Slow Blinking
+  *     @arg LED_BLINK_ERROR : Error specific Blinking
+  * @retval None
+  */
+void LED_Blinking(uint32_t Period)
+{
+  /* Toggle IO in an infinite loop */
+  while (1)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+    LL_mDelay(Period);
+  }
+}
+
+/**
+  * @brief  Configures User push-button (SW1) in GPIO or EXTI Line Mode.
+  * @param  ButtonMode: Specifies Button mode.
+  *   This parameter can be one of following parameters:   
+  *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO
+  *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
+  *                            generation capability  
+  * @retval None
+  */
+void UserButton_Init(uint32_t Button_Mode)
+{
+  /* Enable the BUTTON Clock */
+  USER_BUTTON_GPIO_CLK_ENABLE();
+  
+  /* Configure GPIO for BUTTON */
+  LL_GPIO_SetPinMode(USER_BUTTON_GPIO_PORT, USER_BUTTON_PIN, LL_GPIO_MODE_INPUT);
+  LL_GPIO_SetPinPull(USER_BUTTON_GPIO_PORT, USER_BUTTON_PIN, LL_GPIO_PULL_UP);
+
+  if(Button_Mode == BUTTON_MODE_EXTI)
+  {
+    /* Connect External Line to the GPIO */
+    USER_BUTTON_SYSCFG_SET_EXTI();
+    
+    /* Enable a falling trigger EXTI line 13 Interrupt */
+    USER_BUTTON_EXTI_LINE_ENABLE();
+    USER_BUTTON_EXTI_FALLING_TRIG_ENABLE();
+    
+    /* Configure NVIC for USER_BUTTON_EXTI_IRQn */
+    NVIC_EnableIRQ(USER_BUTTON_EXTI_IRQn); 
+    NVIC_SetPriority(USER_BUTTON_EXTI_IRQn,0x03);  
+  }
+}
+
+/**
+  * @brief  Returns the selected Button state.
+  * @param  None
+  * @retval The Button GPIO pin value.
+  */
+uint32_t UserButton_GetState(void)
+{
+  return LL_GPIO_IsInputPinSet(USER_BUTTON_GPIO_PORT, USER_BUTTON_PIN);
+}
+
+/**
+  * @brief  Function to configure and initialize PWR IP.
+  * @param  None
+  * @retval None
+  */
+void Configure_PWR(void)
+{
+  /* Check if the system was resumed from Standby mode */
+  /* Note: On STM32WB, both CPU1 and CPU2 must be in Standby mode to set the entire system in Standby mode */
+  if(   (LL_PWR_IsActiveFlag_C1SB() != 0)
+     && (LL_PWR_IsActiveFlag_C2SB() != 0)
+    )
+  {
+    /* Clear Standby flag */
+    LL_PWR_ClearFlag_C1STOP_C1STB();
+    LL_PWR_ClearFlag_C2STOP_C2STB();
+    
+    /* Change LED speed to SLOW to indicate exit from Standby mode */
+    LED_Blinking(LED_BLINK_SLOW);
+    
+    /* Wait that user release the User push-button (SW1) */
+    while(UserButton_GetState() == 0){}
+  }
+  
+  /* Specific procedure on STM32WB, in case of initial power-up and RF stack no started */
+  /* Note: This procedure is required when user application wants to request  */
+  /*       a low-power mode in the particular case:                           */
+  /*       - RF stack not started: On STM32WB, system low-power mode is fixed */
+  /*         by the deepest low-power modes of each sub-system (CPU1,         */
+  /*         CPU2, RF).                                                       */
+  /*         Standard case is RF stack started and managing low-power modes   */
+  /*         of CPU2 and RF.                                                  */
+  /*         In case of RF stack not started, CPU2 low-power mode must be     */
+  /*         forced to the lowest level. This allows to require all system    */
+  /*         low-power modes using only PWR for CPU1.                         */
+  /*         low-power mode.                                                  */
+  /*       - Initial power-up: In case of power-on reset, CPU2 low-power mode */
+  /*         has its reset value and must be set.                             */
+  /*         In case of system is resumed from low-power mode standby         */
+  /*         or shutdown, configuration of PWR parameters related to CPU2 are */
+  /*         retained and must not modified (This check is required in case   */
+  /*         of RF stack started afterwards and to not overwritte its         */
+  /*         low-power configuration).                                        */
+  if(   (LL_PWR_IsActiveFlag_C1SB() == 0)
+     || (LL_PWR_IsActiveFlag_C2SB() == 0)
+    )
+  {
+    /* Set the lowest low-power mode for CPU2: shutdown mode */
+    LL_C2_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN);
+  }
+
+  /* Check and Clear the Wakeup flag */
+  if (LL_PWR_IsActiveFlag_WU1() != 0)
+  {
+    LL_PWR_ClearFlag_WU1();
+  }
+}
+
+/**
+  * @brief  Function to configure and enter in Standby Mode.
+  * @param  None
+  * @retval None
+  */
+void EnterStandbyMode(void)
+{
+  /* Wait that user release the User push-button (SW1) */
+  while(UserButton_GetState() == 0){}
+  
+  /* Turn-off LED */
+  /* Note: LED state at this step depends on blinking state at the instant of user button is pressed. */
+  LL_GPIO_ResetOutputPin(GPIOB, LL_GPIO_PIN_0);
+  
+  /* Disable all used wakeup sources */
+  LL_PWR_DisableWakeUpPin(LL_PWR_WAKEUP_PIN1);
+  
+  /* Clear all wake up Flag */
+  LL_PWR_ClearFlag_WU();
+  
+  /* Enable pull up on wakeup pin */
+  /* Note: Setting not mandatory but recommended since there is no external pulling resistor on pin PA0 on STM32WB Nucleo board */
+  LL_PWR_EnableGPIOPullUp(LL_PWR_GPIO_A, LL_PWR_GPIO_BIT_0);
+  
+  /* Enable pull-up and pull-down configuration for CPU1 */
+  LL_PWR_EnablePUPDCfg();
+  
+  /* Set wakeup pin polarity */
+  LL_PWR_SetWakeUpPinPolarityLow(LL_PWR_WAKEUP_PIN1);
+
+  /* Enable wakeup pin */
+  LL_PWR_EnableWakeUpPin(LL_PWR_WAKEUP_PIN1);
+  
+  /* As default User push-button (SW1) state is high level, need to clear all wake up Flag again */
+  LL_PWR_ClearFlag_WU();
+
+  /** Request to enter Standby mode
+    * Following procedure describe in STM32WBxx Reference Manual
+    * See PWR part, section Low-power modes, Standby mode
+    */
+  /* Set Standby mode when CPU enters deepsleep */
+  LL_PWR_SetPowerMode(LL_PWR_MODE_STANDBY);
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  LL_LPM_EnableDeepSleep();
+  
+  /* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT                                               */
+/******************************************************************************/
+/**
+  * @brief  Function to manage BUTTON IRQ Handler
+  * @param  None
+  * @retval None
+  */
+void UserButton_Callback(void)
+{
+  /* Configure and enter in Standby Mode */
+  EnterStandbyMode();
+  
+  /* Here Device is in Standby mode */
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..36016bb95
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Src/stm32wbxx_it.c
@@ -0,0 +1,222 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/PWR/PWR_EnterStandbyMode/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles external line 0 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void USER_BUTTON_IRQHANDLER(void)
+{
+  /* Manage Flags */
+  if(LL_EXTI_IsActiveFlag_0_31(USER_BUTTON_EXTI_LINE) != RESET)
+  {
+    LL_EXTI_ClearFlag_0_31(USER_BUTTON_EXTI_LINE);
+
+    /* Manage code in main.c.*/
+    UserButton_Callback();
+  }
+}
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/readme.txt
new file mode 100644
index 000000000..44b70d79a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStandbyMode/readme.txt
@@ -0,0 +1,104 @@
+/**
+  @page PWR_EnterStandbyMode PWR standby example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/PWR/PWR_EnterStandbyMode/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the PWR STANDBY mode example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to enter the Standby mode and wake up from this mode by using an external 
+reset or a wakeup interrupt.
+
+In the associated software, the system clock is set to 64 MHz.
+An EXTI line is connected to the User push-button (SW1) through PA.00 and configured to generate an 
+interrupt on falling edge upon key press.
+LED2 toggles in order to indicate that MCU is in RUN mode:
+- quickly (each 200ms) if program starts from reset
+- slowly (each 500ms) if program wakes up from Standby mode
+
+When a falling edge is detected on the EXTI line, an interrupt is generated. 
+In the EXTI handler routine, the wake-up pin LL_PWR_WAKEUP_PIN1 is enabled and the 
+corresponding wake-up flag cleared. Then, the system enters Standby mode causing 
+LED2 to stop toggling. 
+
+Next, the user can wake-up the system in pressing the User push-button (SW1) which is 
+connected to the wake-up pin LL_PWR_WAKEUP_PIN1.
+A falling edge on WKUP pin will wake-up the system from Standby.
+Wake-up pin connection: On board STM32WB Nucleo64, pin PA0 
+Alternatively, an external RESET of the board will lead to a system wake-up as well.
+
+After wake-up from Standby mode, program execution restarts in the same way as 
+after a RESET and LED2 restarts toggling.
+
+LED2 is used to monitor the system state as follows:
+ - LED2 fast toggling: system in Run mode
+ - LED2 slow toggling: system in Run mode after exiting from Standby mode
+ - LED2 off : system in Standby mode
+
+These steps are repeated in an infinite loop.
+
+@note System in Standby mode : LED state at this step depends on blinking state at the instant of user button is pressed.
+
+@note To measure MCU current consumption on board STM32WB Nucleo,
+      board configuration must be applied:
+      - remove all jumpers on connector JP5 to avoid leakages between ST-Link circuitry and STM32WB device.
+      - remove jumper JP2 and connect an amperemeter to measure current between the 2 connectors of JP2.
+
+@note On STM32WB, both CPU1 and CPU2 must be in Standby mode to set the entire system in Standby mode.
+      In this example, RF stack is not started-up, therefore CPU2 is not started-up and CPU1 configures the CPU2 low-power mode.
+      If this example would be ported to another application, user should start RF stack or manage CPU2 low-power mode.
+
+@note This example can not be used in DEBUG mode due to the fact 
+      that the Cortex-M4 core is no longer clocked during low power mode 
+      so debugging features are disabled.
+
+
+@par Keywords
+
+Power, PWR, Standby mode, Interrupt, EXTI, Wakeup, Low Power, External reset,
+
+@par Directory contents 
+
+  - PWR/PWR_EnterStandbyMode/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - PWR/PWR_EnterStandbyMode/Inc/main.h                  Header for main.c module
+  - PWR/PWR_EnterStandbyMode/Inc/stm32_assert.h          Template file to include assert_failed function
+  - PWR/PWR_EnterStandbyMode/Src/stm32wbxx_it.c          Interrupt handlers
+  - PWR/PWR_EnterStandbyMode/Src/main.c                  Main program
+  - PWR/PWR_EnterStandbyMode/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE
+    board and can be easily tailored to any other supported device
+    and development board.
+
+  - NUCLEO-WB35CE Set-up
+    - LED2 connected to PB.00 pin
+    - User push-button connected to pin PC.13 (External line 15 to 10)
+    - WakeUp Pin LL_PWR_WAKEUP_PIN1 connected to PA.0
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/PWR_EnterStopMode.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/PWR_EnterStopMode.ewd
new file mode 100644
index 000000000..c4ec5d178
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/PWR_EnterStopMode.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		PWR_EnterStopMode
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/PWR_EnterStopMode.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/PWR_EnterStopMode.ewp
new file mode 100644
index 000000000..9d34db369
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/PWR_EnterStopMode.ewp
@@ -0,0 +1,1083 @@
+
+
+  3
+  
+    PWR_EnterStopMode
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/Project.eww
new file mode 100644
index 000000000..8dbd2d47d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\PWR_EnterStopMode.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Inc/main.h
new file mode 100644
index 000000000..4729ed29a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Inc/main.h
@@ -0,0 +1,99 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/PWR/PWR_EnterStopMode/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..5221a955e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Inc/stm32wbxx_it.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/PWR/PWR_EnterStopMode/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+void USER_BUTTON_IRQHANDLER(void);
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/MDK-ARM/PWR_EnterStopMode.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/MDK-ARM/PWR_EnterStopMode.uvoptx
new file mode 100644
index 000000000..96b984dd6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/MDK-ARM/PWR_EnterStopMode.uvoptx
@@ -0,0 +1,333 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    PWR_EnterStopMode
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/MDK-ARM/PWR_EnterStopMode.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/MDK-ARM/PWR_EnterStopMode.uvprojx
new file mode 100644
index 000000000..323b79f6c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/MDK-ARM/PWR_EnterStopMode.uvprojx
@@ -0,0 +1,471 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      PWR_EnterStopMode
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          PWR_EnterStopMode\
+          PWR_EnterStopMode
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4101
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          "" ()
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/PWR_EnterStopMode.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/PWR_EnterStopMode.ioc
new file mode 100644
index 000000000..7fa8d2b88
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/PWR_EnterStopMode.ioc
@@ -0,0 +1,111 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB0
+Mcu.Pin1=VP_SYS_VS_Systick
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=PWR_EnterStopMode.ioc
+ProjectManager.ProjectName=PWR_EnterStopMode
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..2ae485f56
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/.project
new file mode 100644
index 000000000..bad46f38c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/.project
@@ -0,0 +1,80 @@
+
+
+	PWR_EnterStopMode
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			PWR_EnterStopMode.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/PWR_EnterStopMode.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Src/main.c
new file mode 100644
index 000000000..cdae7a8c6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Src/main.c
@@ -0,0 +1,341 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/PWR/PWR_EnterStopMode/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to enter and exit the Stop 2 mode
+  *          through the STM32WBxx PWR LL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+/* USER CODE BEGIN PFP */
+
+void     Configure_PWR(void);
+void     LED_Off(void);
+void     LED_Blinking_5s(void);
+void     EnterStop2Mode(void);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  /* USER CODE BEGIN 2 */
+
+
+  /* Configure Power IP */
+  Configure_PWR();
+
+  /* Led blinking during 5s in RUN mode */
+  LED_Blinking_5s();
+
+  /* Switch OFF LED2 */
+  LED_Off();
+
+  /* Enter Stop 2 mode */
+  EnterStop2Mode();
+
+  /* Here Device is in Stop 2 mode */
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* MSI configuration and activation */
+  LL_RCC_MSI_Enable();
+  while(LL_RCC_MSI_IsReady() != 1)
+  {
+  };
+
+  /* Main PLL configuration and activation */
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 32, LL_RCC_PLLR_DIV_2);
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the main PLL */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(64000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(64000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  Turn-off LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_Off(void)
+{
+  /* Turn LED2 off */
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Set LED2 to Blinking mode during 5s.
+  * @param  None
+
+  * @retval None
+  */
+void LED_Blinking_5s(void)
+{
+  uint32_t i = 0;
+
+  /* Toggle IO in during 5s (25*200ms) */
+  for(i = 0; i < 25; i++)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);  
+    LL_mDelay(200);
+  }
+}
+
+/**
+  * @brief  Function to configure and initialize PWR IP.
+  * @param  None
+  * @retval None
+  */
+void Configure_PWR(void)
+{
+  /* Ensure that MSI is wake-up system clock */ 
+  LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_MSI);
+}
+
+/**
+  * @brief  Function to configure and enter in Stop 2 Mode.
+  * @param  None
+  * @retval None
+  */
+void EnterStop2Mode(void)
+{
+  LL_GPIO_InitTypeDef gpio_initstruct = {LL_GPIO_PIN_ALL, LL_GPIO_MODE_ANALOG, 
+                                         LL_GPIO_SPEED_FREQ_HIGH, LL_GPIO_OUTPUT_PUSHPULL, 
+                                         LL_GPIO_PULL_NO, LL_GPIO_AF_0};
+
+  /* Set all GPIO in analog state to reduce power consumption,                */
+  /* Note: Debug using ST-Link is not possible during the execution of this   */
+  /*       example because communication between ST-link and the device       */
+  /*       under test is done through UART. All GPIO pins are disabled (set   */
+  /*       to analog input mode) including  UART I/O pins.                    */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA |
+                            LL_AHB2_GRP1_PERIPH_GPIOB |
+                            LL_AHB2_GRP1_PERIPH_GPIOC |
+                            LL_AHB2_GRP1_PERIPH_GPIOE |
+                            LL_AHB2_GRP1_PERIPH_GPIOH);
+
+  LL_GPIO_Init(GPIOA, &gpio_initstruct);
+  LL_GPIO_Init(GPIOB, &gpio_initstruct);
+  LL_GPIO_Init(GPIOC, &gpio_initstruct);
+  LL_GPIO_Init(GPIOE, &gpio_initstruct);
+  LL_GPIO_Init(GPIOH, &gpio_initstruct);
+	
+
+  LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOA |
+                            LL_AHB2_GRP1_PERIPH_GPIOB |
+                            LL_AHB2_GRP1_PERIPH_GPIOC |
+                            LL_AHB2_GRP1_PERIPH_GPIOE |
+                            LL_AHB2_GRP1_PERIPH_GPIOH);
+
+  /** Request to enter Stop 2 mode
+    * Following procedure describe in STM32WBxx Reference Manual
+    * See PWR part, section Low-power modes, Stop 2 mode
+    */
+  /* Set Stop 2 mode when CPU enters deepsleep */
+  LL_PWR_SetPowerMode(LL_PWR_MODE_STOP2);
+  
+  /* Set Stop 2 mode of CPU2 */
+  /* Note: On STM32WB, both CPU1 and CPU2 must be in Stop mode to set the entire system in Stop mode */
+  LL_C2_PWR_SetPowerMode(LL_PWR_MODE_STOP2);
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  LL_LPM_EnableDeepSleep();
+
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..ffc44fa70
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Src/stm32wbxx_it.c
@@ -0,0 +1,207 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/PWR/PWR_EnterStopMode/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/readme.txt
new file mode 100644
index 000000000..562f67fba
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_EnterStopMode/readme.txt
@@ -0,0 +1,80 @@
+/**
+  @page PWR_EnterStopMode PWR standby example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/PWR/PWR_EnterStopMode/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the PWR Stop 2 mode example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to enter the Stop 2 mode.
+
+After start-up LED2 is toggling during 5 seconds, then the system automatically 
+enter in Stop 2 mode (Final state).
+
+LED2 is used to monitor the system state as follows:
+ - LED2 toggling : system in Run mode
+ - LED2 off : system in Stop 2 mode
+
+This example does not implement a wake-up source from any peripheral: to wake-up the device,
+press on Reset button.
+
+@note To measure MCU current consumption on board STM32WB Nucleo,
+      board configuration must be applied:
+      - remove all jumpers on connector JP5 to avoid leakages between ST-Link circuitry and STM32WB device.
+      - remove jumper JP2 and connect an amperemeter to measure current between the 2 connectors of JP2.
+
+@note This example can not be used in DEBUG mode due to the fact 
+      that the Cortex-M4 core is no longer clocked during low power mode 
+      so debugging features are disabled.
+
+@note On STM32WB, both CPU1 and CPU2 must be in Stop mode to set the entire system in Stop mode.
+      In this example, CPU2 is not started-up and CPU1 configures the CPU2 Stop mode.
+      If this example would be ported to another application, user must manage CPU2 entering Stop mode.
+
+@par Keywords
+
+Power, PWR, Stop mode, Interrupt, Low Power
+
+@par Directory contents 
+
+  - PWR/PWR_EnterStopMode/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - PWR/PWR_EnterStopMode/Inc/main.h                  Header for main.c module
+  - PWR/PWR_EnterStopMode/Inc/stm32_assert.h          Template file to include assert_failed function
+  - PWR/PWR_EnterStopMode/Src/stm32wbxx_it.c          Interrupt handlers
+  - PWR/PWR_EnterStopMode/Src/main.c                  Main program
+  - PWR/PWR_EnterStopMode/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE
+    board and can be easily tailored to any other supported device
+    and development board.
+
+  - NUCLEO-WB35CE Set-up
+    - LED2 connected to PB.00 pin
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/.extSettings
new file mode 100644
index 000000000..ea01585ca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Application/User=../Src/main.c;../Src/stm32wbxx_it.c;
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/PWR_OptimizedRunMode.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/PWR_OptimizedRunMode.ewd
new file mode 100644
index 000000000..fbce87faa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/PWR_OptimizedRunMode.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		PWR_OptimizedRunMode
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/PWR_OptimizedRunMode.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/PWR_OptimizedRunMode.ewp
new file mode 100644
index 000000000..14235adb3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/PWR_OptimizedRunMode.ewp
@@ -0,0 +1,1083 @@
+
+
+  3
+  
+    PWR_OptimizedRunMode
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/Project.eww
new file mode 100644
index 000000000..9fd92c099
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\PWR_OptimizedRunMode.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Inc/main.h
new file mode 100644
index 000000000..791a05829
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Inc/main.h
@@ -0,0 +1,133 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/PWR/PWR_OptimizedRunMode/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/**
+  * @brief LED2 
+  */
+
+#define LED2_PIN                           LL_GPIO_PIN_0
+#define LED2_GPIO_PORT                     GPIOB
+#define LED2_GPIO_CLK_ENABLE()             LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB)
+
+/**
+  * @brief Toggle periods for various blinking modes
+  */
+
+#define LED_BLINK_FAST    100
+#define LED_BLINK_MEDIUM  200
+#define LED_BLINK_SLOW    400
+
+/**
+  * @brief Key push-button
+  */
+#define USER_BUTTON_PIN                         LL_GPIO_PIN_0
+#define USER_BUTTON_GPIO_PORT                   GPIOA
+#define USER_BUTTON_GPIO_CLK_ENABLE()           LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);   
+#define USER_BUTTON_EXTI_LINE                   LL_EXTI_LINE_0
+#define USER_BUTTON_EXTI_IRQn                   EXTI0_IRQn
+#define USER_BUTTON_EXTI_LINE_ENABLE()          LL_EXTI_EnableIT_0_31(USER_BUTTON_EXTI_LINE)   
+#define USER_BUTTON_EXTI_LINE_DISABLE()         LL_EXTI_DisableIT_0_31(USER_BUTTON_EXTI_LINE)
+#define USER_BUTTON_EXTI_FALLING_TRIG_ENABLE()  LL_EXTI_EnableFallingTrig_0_31(USER_BUTTON_EXTI_LINE)
+#define USER_BUTTON_EXTI_RISING_TRIG_ENABLE()   LL_EXTI_EnableRisingTrig_0_31(USER_BUTTON_EXTI_LINE)   
+#define USER_BUTTON_SYSCFG_SET_EXTI()           LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTA, LL_SYSCFG_EXTI_LINE0);
+#define USER_BUTTON_IRQHANDLER                  EXTI0_IRQHandler
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* IRQ Handler treatment functions */
+void UserButton_Callback(void); 
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define USER_BUTTON_Pin LL_GPIO_PIN_0
+#define USER_BUTTON_GPIO_Port GPIOA
+#define USER_BUTTON_EXTI_IRQn EXTI0_IRQn
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..499625efc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Inc/stm32wbxx_it.h
@@ -0,0 +1,73 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/PWR/PWR_OptimizedRunMode/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void EXTI0_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+void USER_BUTTON_IRQHANDLER(void);
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/MDK-ARM/PWR_OptimizedRunMode.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/MDK-ARM/PWR_OptimizedRunMode.uvoptx
new file mode 100644
index 000000000..999ff1d6c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/MDK-ARM/PWR_OptimizedRunMode.uvoptx
@@ -0,0 +1,333 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    PWR_OptimizedRunMode
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066CFF303337554E43183920 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    1
+    0
+    0
+    0
+    
+      4
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/MDK-ARM/PWR_OptimizedRunMode.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/MDK-ARM/PWR_OptimizedRunMode.uvprojx
new file mode 100644
index 000000000..5cc964244
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/MDK-ARM/PWR_OptimizedRunMode.uvprojx
@@ -0,0 +1,472 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      PWR_OptimizedRunMode
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          PWR_OptimizedRunMode\
+          PWR_OptimizedRunMode
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/PWR_OptimizedRunMode.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/PWR_OptimizedRunMode.ioc
new file mode 100644
index 000000000..d5f2fd7f8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/PWR_OptimizedRunMode.ioc
@@ -0,0 +1,115 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA0
+Mcu.Pin1=VP_SYS_VS_Systick
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.EXTI0_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA0.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
+PA0.GPIO_Label=USER BUTTON
+PA0.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
+PA0.GPIO_PuPd=GPIO_PULLUP
+PA0.Locked=true
+PA0.Signal=GPXTI0
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=PWR_OptimizedRunMode.ioc
+ProjectManager.ProjectName=PWR_OptimizedRunMode
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SH.GPXTI0.0=GPIO_EXTI0
+SH.GPXTI0.ConfNb=1
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..0b660bb61
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/.cproject
@@ -0,0 +1,189 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/.project
new file mode 100644
index 000000000..aa563caad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/.project
@@ -0,0 +1,80 @@
+
+
+	PWR_OptimizedRunMode
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			PWR_OptimizedRunMode.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/PWR_OptimizedRunMode.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Src/main.c
new file mode 100644
index 000000000..41b65e891
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Src/main.c
@@ -0,0 +1,542 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/PWR/PWR_OptimizedRunMode/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to enter or exit Low Power Run mode and update
+  *          the core frequency on the fly through the STM32WBxx PWR LL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+#define USE_LED
+
+typedef enum {
+  RUN_MODE_DOWN_TO_16MHZ = 0,
+  RUN_MODE_DOWN_TO_100KHZ  = 1,
+  RUN_MODE_UP_TO_16MHZ   = 2,
+  RUN_MODE_UP_TO_64MHZ   = 3
+}RunMode_Typedef;
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+RunMode_Typedef RunMode = RUN_MODE_DOWN_TO_16MHZ;
+__IO uint8_t ubExecuteRunMode = 1;
+#ifdef USE_LED  
+__IO uint16_t uhLedBlinkSpeed = LED_BLINK_FAST;
+#endif
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+/* USER CODE BEGIN PFP */
+
+void     Configure_PWR(void);
+#ifdef USE_LED
+void     LED_Init(void);
+void     LED_Blinking(void);
+#endif
+void     EnterRunMode_DownTo16MHz(void);
+void     EnterRunMode_LowPower_DownTo100KHz(void);
+void     EnterRunMode_UpTo16MHz(void);
+void     EnterRunMode_UpTo64MHz(void);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  /* USER CODE BEGIN 2 */
+
+#ifdef USE_LED
+  /* Initialize LED2 */
+  LED_Init();
+#endif
+
+  /* Configure Power IP */
+  Configure_PWR();
+
+  while(ubExecuteRunMode)
+  {
+#ifdef USE_LED   
+    /* Led blinking until User push-button action */
+    LED_Blinking();
+#endif
+  }
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+#ifdef USE_LED   
+    /* Led blinking in infinite loop*/
+    LED_Blinking();
+#endif
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* MSI configuration and activation */
+  LL_RCC_MSI_Enable();
+  while(LL_RCC_MSI_IsReady() != 1)
+  {
+  };
+
+  /* Main PLL configuration and activation */
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 32, LL_RCC_PLLR_DIV_2);
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the main PLL */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(64000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(64000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_EXTI_InitTypeDef EXTI_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+
+  /**/
+  LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTA, LL_SYSCFG_EXTI_LINE0);
+
+  /**/
+  EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_0;
+  EXTI_InitStruct.Line_32_63 = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct.LineCommand = ENABLE;
+  EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;
+  EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_FALLING;
+  LL_EXTI_Init(&EXTI_InitStruct);
+
+  /**/
+  LL_GPIO_SetPinPull(USER_BUTTON_GPIO_Port, USER_BUTTON_Pin, LL_GPIO_PULL_UP);
+
+  /**/
+  LL_GPIO_SetPinMode(USER_BUTTON_GPIO_Port, USER_BUTTON_Pin, LL_GPIO_MODE_INPUT);
+
+  /* EXTI interrupt init*/
+  NVIC_SetPriority(EXTI0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(EXTI0_IRQn);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+#ifdef USE_LED
+/**
+  * @brief  Initialize LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_Init(void)
+{
+  /* Enable the LED2 Clock */
+  LED2_GPIO_CLK_ENABLE();
+
+  /* Configure IO in output push-pull mode to drive external LED2 */
+  LL_GPIO_SetPinMode(LED2_GPIO_PORT, LED2_PIN, LL_GPIO_MODE_OUTPUT);
+  /* Reset value is LL_GPIO_OUTPUT_PUSHPULL */
+  //LL_GPIO_SetPinOutputType(LED2_GPIO_PORT, LED2_PIN, LL_GPIO_OUTPUT_PUSHPULL);
+  /* Reset value is LL_GPIO_SPEED_FREQ_LOW */
+  //LL_GPIO_SetPinSpeed(LED2_GPIO_PORT, LED2_PIN, LL_GPIO_SPEED_FREQ_LOW);
+  /* Reset value is LL_GPIO_PULL_NO */
+  //LL_GPIO_SetPinPull(LED2_GPIO_PORT, LED2_PIN, LL_GPIO_PULL_NO);
+}
+
+/**
+  * @brief  Set LED2 to Blinking mode (Shall be call in a Loop).
+  * @param  None
+  * @retval None
+  */
+void LED_Blinking(void)
+{
+  /* Toggle IO. Shall be call in a loop to toggle */
+  LL_GPIO_TogglePin(LED2_GPIO_PORT, LED2_PIN);
+  LL_mDelay(uhLedBlinkSpeed);
+}
+#endif
+
+/**
+  * @brief  Function to configure and initialize PWR IP.
+  * @param  None
+  * @retval None
+  */
+void Configure_PWR(void)
+{
+  
+
+
+  /* Ensure that MSI is wake-up system clock */ 
+  /* MSI is the default value. Not mandatory to call function in this case */
+  //LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_MSI);
+}
+
+/**
+  * @brief  Function to decrease Frequency at 16MHz in Run Mode.
+  * @param  None
+  * @retval None
+  */
+void EnterRunMode_DownTo16MHz(void)
+{
+  /* 1 - Switch clock source on MSI */
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_MSI);    
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSI) 
+  {
+  };
+  
+  /* Set MSI to 16MHz */
+  LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_8);
+  
+  /* Disable PLL to decrease power consumption */
+  LL_RCC_PLL_Disable();
+  while(LL_RCC_PLL_IsReady() != 0) 
+  {
+  };
+  LL_RCC_PLL_DisableDomain_SYS();
+
+  /* Set systick to 1ms in using frequency set to 16MHz */
+  LL_Init1msTick(16 * 1000000);
+  /* Update CMSIS variable */
+  LL_SetSystemCoreClock(16 * 1000000);
+
+  /* 2 - Adjust Flash Wait state after decrease Clock Frequency */
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);
+
+  /* 3 - Set Voltage scaling (decrease Vcore) */
+  LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2);
+}
+
+/**
+  * @brief  Function to decrease Frequency at 100KHZ in Low Power Run Mode.
+  * @param  None
+  * @retval None
+  */
+void EnterRunMode_LowPower_DownTo100KHz(void)
+{
+  /* 1 - Set Frequency to 100KHz to activate Low Power Run Mode: 100KHz */
+  /* Range Selection already enabled. Need to change Range only */
+  LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_0);
+  /* Set systick to 1ms in using frequency set to 100KHz */
+  LL_Init1msTick(100 * 1000);
+  /* Update CMSIS variable */
+  LL_SetSystemCoreClock(100 * 1000);
+
+  /* 2 - Adjust Flash Wait state after decrease Clock Frequency */
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_0);
+
+  /* Voltage Scaling already set to LL_PWR_REGU_VOLTAGE_SCALE2. VCore already decreased */
+
+  /* 3 - Activate Low Power Run Mode */
+  LL_PWR_EnterLowPowerRunMode();
+}
+
+/**
+  * @brief  Function to increase Frequency at 16MHz in Run Mode.
+  * @param  None
+  * @retval None
+  */
+void EnterRunMode_UpTo16MHz(void)
+{
+  /* 1 - Deactivate Low Power Run Mode to increase Frequency up to 16MHz */
+  LL_PWR_ExitLowPowerRunMode();
+
+  /* Voltage Scaling already set to LL_PWR_REGU_VOLTAGE_SCALE2. VCore already decreased */
+
+  /* 2 - Adjust Flash Wait state before increase Clock Frequency */
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);
+  
+  /* Wait for flash latency setting effective before increase clock frequency */
+  while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_1)
+  {
+  };
+  
+  /* 3 - Set Frequency to 16MHz (MSI) */
+  LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_8);
+  /* Set systick to 1ms in using frequency set to 16MHz */
+  LL_Init1msTick(16 * 1000000);
+  /* Update CMSIS variable */
+  LL_SetSystemCoreClock(16 * 1000000);
+}
+
+/**
+  * @brief  Function to increase Frequency at 64MHz in Run Mode.
+  * @param  None
+  * @retval None
+  */
+void EnterRunMode_UpTo64MHz(void)
+{
+  /* 1 - Set Voltage scaling (increase Vcore before increasing Clock Frequency) */
+  LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
+
+  /* 2 - Wait Voltage Scaling 1 before increase frequency */
+  while(LL_PWR_IsActiveFlag_VOS() !=  0)
+  {
+  };
+
+  /* 3 - Adjust Flash Wait state before increase Clock Frequency */
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* Wait for flash latency setting effective before increase clock frequency */
+  while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_3)
+  {
+  };
+  
+  /* 4 - Set Frequency to 64MHz (PLL) */
+  LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
+
+  /* Enable PLL and wait for activation */
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Switch on PLL. Previous configuration done by SystemClock_Config is used */
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) 
+  {
+  };
+
+  /* Set systick to 1ms in using frequency set to 64MHz */
+  LL_Init1msTick(64 * 1000000);
+
+  /* Update CMSIS variable */
+  LL_SetSystemCoreClock(64 * 1000000);
+}
+
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT                                               */
+/******************************************************************************/
+/**
+  * @brief  Function to manage BUTTON IRQ Handler
+  * @param  None
+  * @retval None
+  */
+void UserButton_Callback(void)
+{
+  switch(RunMode)
+  {
+  case RUN_MODE_DOWN_TO_16MHZ:
+    {
+      /* Decrease core frequency and voltage
+       * Frequency: 64MHz -> 16MHz
+       * Voltage Scaling Range 2
+       */
+      EnterRunMode_DownTo16MHz();
+#ifdef USE_LED
+      uhLedBlinkSpeed = LED_BLINK_MEDIUM;
+#endif
+      /* Set Next RunMode to execute */
+      RunMode = RUN_MODE_DOWN_TO_100KHZ;
+      break;
+    }
+  case RUN_MODE_DOWN_TO_100KHZ:
+    {
+      /* Decrease core frequency and enter Low Power Run mode
+       * Frequency: 100KHz
+       * Voltage Scaling Range 2
+       * LowPowerRunMode activated
+       */
+      EnterRunMode_LowPower_DownTo100KHz();
+#ifdef USE_LED
+      uhLedBlinkSpeed = LED_BLINK_SLOW;
+#endif
+      /* Set Next RunMode to execute */
+      RunMode = RUN_MODE_UP_TO_16MHZ;
+      break;
+    }
+  case RUN_MODE_UP_TO_16MHZ:
+    {
+      /* Increase core frequency and exit Low Power Run mode 
+       * Frequency: 100KHz -> 16MHz
+       * Voltage Scaling Range 2
+       * LowPowerRunMode deactivated
+       */
+      EnterRunMode_UpTo16MHz();
+#ifdef USE_LED
+      uhLedBlinkSpeed = LED_BLINK_MEDIUM;
+#endif
+      /* Set Next RunMode to execute */
+      RunMode = RUN_MODE_UP_TO_64MHZ;
+      break;
+    }
+  case RUN_MODE_UP_TO_64MHZ:
+    {
+      /* Increase core frequency and voltage:
+       * Frequency: 16MHz -> 64MHz
+       * Voltage Scaling Range 1
+       */
+      EnterRunMode_UpTo64MHz();
+#ifdef USE_LED
+      uhLedBlinkSpeed = LED_BLINK_FAST;
+#endif
+      /* Exit Test */
+      NVIC_DisableIRQ(USER_BUTTON_EXTI_IRQn); 
+      USER_BUTTON_EXTI_LINE_DISABLE();
+      
+      ubExecuteRunMode = 0;
+      break;
+    }
+  }
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..1a2db78ae
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Src/stm32wbxx_it.c
@@ -0,0 +1,231 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/PWR/PWR_OptimizedRunMode/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles EXTI line0 interrupt.
+  */
+void EXTI0_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI0_IRQn 0 */
+
+  /* USER CODE END EXTI0_IRQn 0 */
+  if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
+  {
+    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
+    /* USER CODE BEGIN LL_EXTI_LINE_0 */
+    
+    /* Handle user button press in dedicated function */
+    UserButton_Callback(); 
+
+    /* USER CODE END LL_EXTI_LINE_0 */
+  }
+  /* USER CODE BEGIN EXTI0_IRQn 1 */
+
+  /* USER CODE END EXTI0_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/readme.txt
new file mode 100644
index 000000000..17667db62
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/PWR/PWR_OptimizedRunMode/readme.txt
@@ -0,0 +1,105 @@
+/**
+  @page PWR_OptimizedRunMode PWR standby example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/PWR/PWR_OptimizedRunMode/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the PWR Optimized Run Mode example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to increase/decrease frequency and VCORE and how to enter/exit the
+Low-power run mode.
+
+In the associated software, the system clock is set to 64 MHz, an EXTI line
+is connected to the User push-button (SW1) through PA.00 and configured to generate an 
+interrupt on falling edge upon key press.
+
+After start-up LED2 is toggling FAST(100-ms blinking period), indicates that device 
+is running at 64MHz.
+
+LED2 toggling speed is controlled by variable "uhLedBlinkSpeed".
+
+The User push-button (SW1) can be pressed at any time to change Frequency, VCore(VOS) 
+and Low Power Run mode. 
+
+Initial STATE: 
+--> Freq: 64MHz, VCore 1.2V, Core in Run Mode
+--> LED2 toggling FAST (100ms)   - wait User push-button (SW1) action
+
+STATE 2: 
+User push-button (SW1) pressed:
+--> Freq: 16MHz, VCore 1.0V, Core in Run Mode
+--> LED2 toggling MEDIUM (200ms) - wait User push-button (SW1) action
+
+STATE 3: 
+User push-button (SW1) pressed:
+--> Freq:  100KHz, VCore 1.0V, Core in Low Power Run Mode
+--> LED2 toggling SLOW (400ms)   - wait User push-button (SW1) action
+
+STATE 4: 
+User push-button (SW1) pressed:
+--> Freq: 16MHz, VCore 1.0V, Core in Run Mode
+--> LED2 toggling MEDIUM (200ms) - wait User push-button (SW1) action
+
+Final STATE: 
+User push-button (SW1) pressed:
+--> Freq: 64MHz, VCore 1.2V, Core in Run Mode
+--> LED2 toggling FAST (100ms) in infinite loop
+
+
+@note To measure MCU current consumption on board STM32WB Nucleo,
+      board configuration must be applied:
+      - remove all jumpers on connector JP5 to avoid leakages between ST-Link circuitry and STM32WB device.
+      - remove jumper JP2 and connect an amperemeter to measure current between the 2 connectors of JP2.
+      NB: LED2 has an impact on power consumption. 
+          Remove LED2 blinking to have a stable power consumption, 
+          comment line  "#define USE_LED" in main.c file  
+
+@par Keywords
+
+Power, PWR, Low-power run mode, Interrupt, VCORE, Low Power
+
+@par Directory contents 
+
+  - PWR/PWR_OptimizedRunMode/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - PWR/PWR_OptimizedRunMode/Inc/main.h                  Header for main.c module
+  - PWR/PWR_OptimizedRunMode/Inc/stm32_assert.h          Template file to include assert_failed function
+  - PWR/PWR_OptimizedRunMode/Src/stm32wbxx_it.c          Interrupt handlers
+  - PWR/PWR_OptimizedRunMode/Src/main.c                  Main program
+  - PWR/PWR_OptimizedRunMode/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE
+    board and can be easily tailored to any other supported device
+    and development board.
+
+  - NUCLEO-WB35CE Set-up
+    - LED2 connected to PB.00 pin
+    - User push-button connected to pin PA.00 (External line 0)
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/Project.eww
new file mode 100644
index 000000000..06a8cbc4d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\RCC_UseHSI_PLLasSystemClock.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/RCC_UseHSI_PLLasSystemClock.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/RCC_UseHSI_PLLasSystemClock.ewd
new file mode 100644
index 000000000..b8c2789f3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/RCC_UseHSI_PLLasSystemClock.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		RCC_UseHSI_PLLasSystemClock
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/RCC_UseHSI_PLLasSystemClock.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/RCC_UseHSI_PLLasSystemClock.ewp
new file mode 100644
index 000000000..8c8ef586e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/RCC_UseHSI_PLLasSystemClock.ewp
@@ -0,0 +1,1083 @@
+
+
+  3
+  
+    RCC_UseHSI_PLLasSystemClock
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Inc/main.h
new file mode 100644
index 000000000..e816c3c6f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Inc/main.h
@@ -0,0 +1,134 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+#define RCC_ERROR_NONE    0
+#define RCC_ERROR_TIMEOUT 1
+
+/* Define used to enable time-out management*/
+#define USE_TIMEOUT       0
+
+/**
+  * @brief LED2
+  */
+
+#define LED2_PIN                           LL_GPIO_PIN_0
+#define LED2_GPIO_PORT                     GPIOB
+#define LED2_GPIO_CLK_ENABLE()             LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB)
+
+/**
+  * @brief Toggle periods for various blinking modes
+  */
+
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW  500
+#define LED_BLINK_ERROR 1000
+
+/**
+  * @brief Key push-button
+  */
+#define USER_BUTTON_PIN                         LL_GPIO_PIN_0
+#define USER_BUTTON_GPIO_PORT                   GPIOA
+#define USER_BUTTON_GPIO_CLK_ENABLE()           LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC)
+#define USER_BUTTON_EXTI_LINE                   LL_EXTI_LINE_0
+#define USER_BUTTON_EXTI_IRQn                   EXTI0_IRQn
+#define USER_BUTTON_EXTI_LINE_ENABLE()          LL_EXTI_EnableIT_0_31(USER_BUTTON_EXTI_LINE)
+#define USER_BUTTON_EXTI_FALLING_TRIG_ENABLE()  LL_EXTI_EnableFallingTrig_0_31(USER_BUTTON_EXTI_LINE)
+#define USER_BUTTON_SYSCFG_SET_EXTI()           LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTC, LL_SYSCFG_EXTI_LINE0);
+#define USER_BUTTON_IRQHANDLER                  EXTI0_IRQHandler
+#define USER_BUTTON_PULL_MODE                   LL_GPIO_PULL_UP
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+/* USER button IRQ Handler treatment. */
+void UserButton_Callback(void);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..e2f8dfd6c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Inc/stm32wbxx_it.h
@@ -0,0 +1,73 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void EXTI0_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+void USER_BUTTON_IRQHANDLER(void);
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/MDK-ARM/RCC_UseHSI_PLLasSystemClock.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/MDK-ARM/RCC_UseHSI_PLLasSystemClock.uvoptx
new file mode 100644
index 000000000..776c32f05
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/MDK-ARM/RCC_UseHSI_PLLasSystemClock.uvoptx
@@ -0,0 +1,333 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    RCC_UseHSI_PLLasSystemClock
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      4
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      4
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/MDK-ARM/RCC_UseHSI_PLLasSystemClock.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/MDK-ARM/RCC_UseHSI_PLLasSystemClock.uvprojx
new file mode 100644
index 000000000..021abecff
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/MDK-ARM/RCC_UseHSI_PLLasSystemClock.uvprojx
@@ -0,0 +1,471 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      RCC_UseHSI_PLLasSystemClock
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          RCC_UseHSI_PLLasSystemClock\
+          RCC_UseHSI_PLLasSystemClock
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/RCC_UseHSI_PLLasSystemClock.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/RCC_UseHSI_PLLasSystemClock.ioc
new file mode 100644
index 000000000..da4823794
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/RCC_UseHSI_PLLasSystemClock.ioc
@@ -0,0 +1,120 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA0
+Mcu.Pin1=PB0
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.EXTI0_IRQn=true\:3\:0\:true\:false\:true\:true\:true
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA0.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultEXTI
+PA0.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
+PA0.GPIO_PuPd=GPIO_PULLUP
+PA0.Locked=true
+PA0.Signal=GPXTI0
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=false
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=RCC_UseHSI_PLLasSystemClock.ioc
+ProjectManager.ProjectName=RCC_UseHSI_PLLasSystemClock
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SH.GPXTI0.0=GPIO_EXTI0
+SH.GPXTI0.ConfNb=1
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..0444de24b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/.project
new file mode 100644
index 000000000..3d4a793db
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/.project
@@ -0,0 +1,80 @@
+
+
+	RCC_UseHSI_PLLasSystemClock
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			RCC_UseHSI_PLLasSystemClock.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/RCC_UseHSI_PLLasSystemClock.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Src/main.c
new file mode 100644
index 000000000..983912ef5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Src/main.c
@@ -0,0 +1,567 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to change dynamically SYSCLK through
+  *          the STM32WBxx RCC LL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* Structure based on parameters used for PLL config */
+typedef struct
+{
+  uint32_t Frequency;   /*!< SYSCLK frequency requested */
+  uint32_t PLLM;        /*!< PLLM factor used for PLL */
+  uint32_t PLLN;        /*!< PLLN factor used for PLL */
+  uint32_t PLLR;        /*!< PLLN factor used for PLL */
+  uint32_t Latency;     /*!< Latency to be used with SYSCLK frequency */
+} RCC_PLL_ConfigTypeDef;
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* Number of PLL Config */
+#define RCC_PLL_CONFIG_NB   2
+#define RCC_FREQUENCY_LOW          ((uint32_t)40000000) /* Low Frequency set to 40MHz*/
+#define RCC_FREQUENCY_HIGH         ((uint32_t)64000000) /* High Frequency set to 64MHz*/
+
+/* Oscillator time-out values */
+#define HSE_TIMEOUT_VALUE          ((uint32_t)5000) /* Time out for HSE start up, in ms */
+#define HSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
+#define MSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
+#define PLL_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
+#define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000) /* 5 s    */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* Variable to set different PLL config with HSI as PLL source clock */
+static RCC_PLL_ConfigTypeDef aPLL_ConfigHSI[RCC_PLL_CONFIG_NB] =
+{
+  {RCC_FREQUENCY_LOW, LL_RCC_PLLM_DIV_4, 20, LL_RCC_PLLR_DIV_2, LL_FLASH_LATENCY_2},
+  {RCC_FREQUENCY_HIGH, LL_RCC_PLLM_DIV_2, 40, LL_RCC_PLLR_DIV_4, LL_FLASH_LATENCY_3},
+};
+
+/* PLL Config index */
+__IO uint8_t bPLLIndex = 0;
+
+/* Variable to save the current configuration to apply */
+static uint32_t uwFrequency = RCC_FREQUENCY_HIGH, uwPLLN = 0, uwPLLM = 0, uwPLLR  = 0, uwLatency = 0;
+
+/* Variable to indicate a change of PLL config after a button press */
+__IO uint8_t bButtonPress = 0;
+
+uint32_t Timeout = 0; /* Variable used for Timeout management */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+/* USER CODE BEGIN PFP */
+
+uint32_t RCC_StartHSIAndWaitForHSIReady(void);
+uint32_t ChangePLL_HSI_Config(void);
+void     LED_Blinking(uint32_t Period);
+uint32_t ChangePLLConfiguration(uint32_t PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Enable HSI to be able to select it as sysclk source */
+  /* Start HSI and wait for ready */
+  if (RCC_StartHSIAndWaitForHSIReady() != RCC_ERROR_NONE)
+  {
+    /* Problem to enable HSI, blink LED2 */
+    LED_Blinking(LED_BLINK_ERROR);
+  }
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    /* Toggle LED accordingly to the frequency */
+    if (uwFrequency == RCC_FREQUENCY_LOW)
+    {
+      /* Slow toggle */
+      LED_Blinking(LED_BLINK_SLOW);
+    }
+    else
+    {
+      /* Fast toggle */
+      LED_Blinking(LED_BLINK_FAST);
+    }
+
+    /* PLL config change has been requested */
+    if (ChangePLL_HSI_Config() != RCC_ERROR_NONE)
+    {
+      /* Problem to switch to HSI, blink LED2 */
+      LED_Blinking(LED_BLINK_ERROR);
+    }
+
+    /* Reset button press */
+    bButtonPress = 0;
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* MSI configuration and activation */
+  LL_RCC_MSI_Enable();
+  while(LL_RCC_MSI_IsReady() != 1)
+  {
+  };
+
+  /* Main PLL configuration and activation */
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 32, LL_RCC_PLLR_DIV_2);
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the main PLL */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(64000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(64000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_EXTI_InitTypeDef EXTI_InitStruct = {0};
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTA, LL_SYSCFG_EXTI_LINE0);
+
+  /**/
+  EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_0;
+  EXTI_InitStruct.Line_32_63 = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct.LineCommand = ENABLE;
+  EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;
+  EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_FALLING;
+  LL_EXTI_Init(&EXTI_InitStruct);
+
+  /**/
+  LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_0, LL_GPIO_PULL_UP);
+
+  /**/
+  LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_0, LL_GPIO_MODE_INPUT);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+  /* EXTI interrupt init*/
+  NVIC_SetPriority(EXTI0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),3, 0));
+  NVIC_EnableIRQ(EXTI0_IRQn);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  Enable HSI and Wait for HSI ready
+  * @param  None
+  * @retval RCC_ERROR_NONE if no error
+  */
+uint32_t RCC_StartHSIAndWaitForHSIReady()
+{
+  /* Enable HSI and wait for HSI ready*/
+  LL_RCC_HSI_Enable();
+
+#if (USE_TIMEOUT == 1)
+  Timeout = HSI_TIMEOUT_VALUE;
+#endif /* USE_TIMEOUT */
+  while (LL_RCC_HSI_IsReady() != 1)
+  {
+#if (USE_TIMEOUT == 1)
+    /* Check Systick counter flag to decrement the Time-out value */
+    if (LL_SYSTICK_IsActiveCounterFlag())
+    {
+      if (Timeout-- == 0)
+      {
+        /* Time-out occurred. Return an error */
+        return RCC_ERROR_TIMEOUT;
+      }
+    }
+#endif /* USE_TIMEOUT */
+  };
+
+  return RCC_ERROR_NONE;
+}
+
+/**
+  * @brief  Switch the PLL source to HSI, and select the PLL as SYSCLK
+  *         source to reach new requested frequency.
+  * @param  None
+  * @retval RCC_ERROR_NONE if no error
+  */
+uint32_t ChangePLL_HSI_Config(void)
+{
+  /* Select HSI as system clock */
+  /* Wait for HSI switched */
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+#if (USE_TIMEOUT == 1)
+  Timeout = CLOCKSWITCH_TIMEOUT_VALUE;
+#endif /* USE_TIMEOUT */
+  while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+#if (USE_TIMEOUT == 1)
+    /* Check Systick counter flag to decrement the time-out value */
+    if (LL_SYSTICK_IsActiveCounterFlag())
+    {
+      if (Timeout-- == 0)
+      {
+        /* Time-out occurred. Return an error */
+        return RCC_ERROR_TIMEOUT;
+      }
+    }
+#endif /* USE_TIMEOUT */
+  }
+
+  /* Configure PLL with new configuration */
+  if (ChangePLLConfiguration(LL_RCC_PLLSOURCE_HSI, uwPLLM, uwPLLN, uwPLLR) != RCC_ERROR_NONE)
+  {
+    return RCC_ERROR_TIMEOUT;
+  }
+
+  /* Latency must be managed differently if increase or decrease the frequency */
+  if (uwFrequency == RCC_FREQUENCY_LOW)
+  {
+    /* Decrease Frequency - latency should be set after setting PLL as clock source */
+    /* Select PLL as system clock */
+    /* Wait until the PLL is switched on */
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+#if (USE_TIMEOUT == 1)
+    Timeout = CLOCKSWITCH_TIMEOUT_VALUE;
+#endif /* USE_TIMEOUT */
+    while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+    {
+#if (USE_TIMEOUT == 1)
+      /* Check Systick counter flag to decrement the time-out value */
+      if (LL_SYSTICK_IsActiveCounterFlag())
+      {
+        if (Timeout-- == 0)
+        {
+          /* Time-out occurred. Return an error */
+          return RCC_ERROR_TIMEOUT;
+        }
+      }
+#endif /* USE_TIMEOUT */
+    }
+
+    /* Set new latency */
+    LL_FLASH_SetLatency(uwLatency);
+  }
+  else
+  {
+    /* Increase Frequency - latency should be set before setting PLL as clock source */
+    /* Set new latency */
+    LL_FLASH_SetLatency(uwLatency);
+
+    /* Select PLL as system clock */
+    /* Wait until the PLL is switched on */
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+#if (USE_TIMEOUT == 1)
+    Timeout = CLOCKSWITCH_TIMEOUT_VALUE;
+#endif /* USE_TIMEOUT */
+    while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+    {
+#if (USE_TIMEOUT == 1)
+      /* Check Systick counter flag to decrement the time-out value */
+      if (LL_SYSTICK_IsActiveCounterFlag())
+      {
+        if (Timeout-- == 0)
+        {
+          /* Time-out occurred. Return an error */
+          return RCC_ERROR_TIMEOUT;
+        }
+      }
+#endif /* USE_TIMEOUT */
+    }
+  }
+
+  /* Set systick to 1ms */
+  LL_Init1msTick(uwFrequency);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  SystemCoreClock = uwFrequency;
+
+  return RCC_ERROR_NONE;
+}
+
+/**
+  * @brief  Fonction to change Main PLL configuration
+ #error
+  * @retval RCC_ERROR_NONE if no error
+  */
+uint32_t ChangePLLConfiguration(uint32_t PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+  /* Disable the PLL */
+  /* Wait until PLLRDY is cleared */
+  LL_RCC_PLL_Disable();
+#if (USE_TIMEOUT == 1)
+  Timeout = PLL_TIMEOUT_VALUE;
+#endif /* USE_TIMEOUT */
+  while (LL_RCC_PLL_IsReady() != 0)
+  {
+#if (USE_TIMEOUT == 1)
+    /* Check Systick counter flag to decrement the time-out value */
+    if (LL_SYSTICK_IsActiveCounterFlag())
+    {
+      if (Timeout-- == 0)
+      {
+        /* Time-out occurred. Return an error */
+        return RCC_ERROR_TIMEOUT;
+      }
+    }
+#endif /* USE_TIMEOUT */
+  }
+
+  /* Configure PLL */
+  LL_RCC_PLL_ConfigDomain_SYS(PLLSource, PLLM, PLLN, PLLR);
+  /* Enable the PLL */
+  LL_RCC_PLL_Enable();
+  /* Wait until PLLRDY is set */
+#if (USE_TIMEOUT == 1)
+  Timeout = PLL_TIMEOUT_VALUE;
+#endif /* USE_TIMEOUT */
+  while (LL_RCC_PLL_IsReady() != 1)
+  {
+#if (USE_TIMEOUT == 1)
+    /* Check Systick counter flag to decrement the time-out value */
+    if (LL_SYSTICK_IsActiveCounterFlag())
+    {
+      if (Timeout-- == 0)
+      {
+        /* Time-out occurred. Return an error */
+        return RCC_ERROR_TIMEOUT;
+      }
+    }
+#endif /* USE_TIMEOUT */
+  }
+
+  return RCC_ERROR_NONE;
+}
+
+/**
+  * @brief  Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
+  *         Exit of this function when a press button is detected
+  * @param  Period : Period of time (in ms) between each toggling of LED
+  *   This parameter can be user defined values. Pre-defined values used in that example are :
+  *     @arg LED_BLINK_FAST : Fast Blinking
+  *     @arg LED_BLINK_SLOW : Slow Blinking
+  *     @arg LED_BLINK_ERROR : Error specific Blinking
+  * @retval None
+  */
+void LED_Blinking(uint32_t Period)
+{
+  if (Period != LED_BLINK_ERROR)
+  {
+    /* Toggle IO in an infinite loop up to a detection of press button */
+    while (bButtonPress != 1)
+    {
+      /* LED2 is blinking at Period ms */
+      LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+      LL_mDelay(Period);
+    }
+  }
+  else
+  {
+    /* Toggle IO in an infinite loop due to an error */
+    while (1)
+    {
+      /* Error if LED2 is slowly blinking (1 sec. period) */
+      LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+      LL_mDelay(Period);
+    }
+  }
+}
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT                                               */
+/******************************************************************************/
+/**
+  * @brief  Function to manage User button press
+  * @param  None
+  * @retval None
+  */
+void UserButton_Callback(void)
+{
+  /* Get the PLL config to apply */
+  uwFrequency = aPLL_ConfigHSI[bPLLIndex].Frequency;
+  uwPLLM      = aPLL_ConfigHSI[bPLLIndex].PLLM;
+  uwPLLN      = aPLL_ConfigHSI[bPLLIndex].PLLN;
+  uwPLLR      = aPLL_ConfigHSI[bPLLIndex].PLLR;
+  uwLatency   = aPLL_ConfigHSI[bPLLIndex].Latency;
+
+  /* Set new PLL config Index */
+  bPLLIndex = (bPLLIndex + 1) % RCC_PLL_CONFIG_NB;
+
+  /* Set variable to request of PLL config change */
+  bButtonPress = 1;
+}
+
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..045a5402c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Src/stm32wbxx_it.c
@@ -0,0 +1,231 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles EXTI line0 interrupt.
+  */
+void EXTI0_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI0_IRQn 0 */
+
+  /* USER CODE END EXTI0_IRQn 0 */
+  if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
+  {
+    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
+    /* USER CODE BEGIN LL_EXTI_LINE_0 */
+
+    /* Manage code in main.c. */
+    UserButton_Callback();
+
+    /* USER CODE END LL_EXTI_LINE_0 */
+  }
+  /* USER CODE BEGIN EXTI0_IRQn 1 */
+
+  /* USER CODE END EXTI0_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/readme.txt
new file mode 100644
index 000000000..22060467e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/readme.txt
@@ -0,0 +1,70 @@
+/**
+  @page RCC_UseHSI_PLLasSystemClock RCC example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/RCC/RCC_UseHSI_PLLasSystemClock/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the RCC_UseHSI_PLLasSystemClock example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+Modification of the PLL parameters in run time.
+
+In this example, the toggling frequency of the green LED2 depends on the system clock 
+frequency and, each time the User push-button (SW1) is pressed, the PLL switches between two configurations.
+This make the LED2 blinking speed to highlight the system clock frequency changes.
+
+In this example, after start-up, SYSCLK is configured to the max frequency using the PLL with
+MSI as clock source.
+Then, when pressing User push-button (SW1), an automatic switch is done between PLL with HSI as clock source (SYSCLK
+set to 40MHz) and PLL with HSI as clock source (SYSCLK set to 64MHz). 
+LED2 will toggle differently between the 2 configurations (quick toggle with SYSCLK configuration at 64MHz).
+
+To detect a problem with PLL configuration, switch USE_TIMEOUT can be enabled. Then in case of issues, 
+LED2 will toggle every 1 second.
+Note: "uwFrequency" variable can be added in LiveWatch to monitor the system clock frequency.
+
+@par Keywords
+
+System, RCC, PLL, PLLCLK, SYSCLK, HSE, Clock, Oscillator, HSI
+
+
+@par Directory contents 
+
+  - RCC/RCC_UseHSI_PLLasSystemClock/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - RCC/RCC_UseHSI_PLLasSystemClock/Inc/main.h                  Header for main.c module
+  - RCC/RCC_UseHSI_PLLasSystemClock/Inc/stm32_assert.h          Template file to include assert_failed function
+  - RCC/RCC_UseHSI_PLLasSystemClock/Src/stm32wbxx_it.c          Interrupt handlers
+  - RCC/RCC_UseHSI_PLLasSystemClock/Src/main.c                  Main program
+  - RCC/RCC_UseHSI_PLLasSystemClock/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/Project.eww
new file mode 100644
index 000000000..650f33435
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\RNG_GenerateRandomNumbers_IT.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/RNG_GenerateRandomNumbers_IT.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/RNG_GenerateRandomNumbers_IT.ewd
new file mode 100644
index 000000000..886eb8861
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/RNG_GenerateRandomNumbers_IT.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		RNG_GenerateRandomNumbers_IT
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/RNG_GenerateRandomNumbers_IT.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/RNG_GenerateRandomNumbers_IT.ewp
new file mode 100644
index 000000000..70dc51375
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/RNG_GenerateRandomNumbers_IT.ewp
@@ -0,0 +1,1086 @@
+
+
+  3
+  
+    RNG_GenerateRandomNumbers_IT
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rng.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Inc/main.h
new file mode 100644
index 000000000..e23946b76
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Inc/main.h
@@ -0,0 +1,121 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_rng.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* Define used to enable time-out management*/
+#define USE_TIMEOUT       0
+
+
+
+/**
+  * @brief Toggle periods for various blinking modes
+  */
+
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW  500
+#define LED_BLINK_ERROR 1000
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+/* IRQ Handler treatment functions */
+void RNG_DataReady_Callback(void); 
+void Error_Callback(void); 
+void UserButton_Callback(void); 
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define USER_BUTTON_Pin LL_GPIO_PIN_0
+#define USER_BUTTON_GPIO_Port GPIOA
+#define USER_BUTTON_EXTI_IRQn EXTI0_IRQn
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..f46d5ff52
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Inc/stm32wbxx_it.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void EXTI0_IRQHandler(void);
+void RNG_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/MDK-ARM/RNG_GenerateRandomNumbers_IT.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/MDK-ARM/RNG_GenerateRandomNumbers_IT.uvoptx
new file mode 100644
index 000000000..c7df3f7b1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/MDK-ARM/RNG_GenerateRandomNumbers_IT.uvoptx
@@ -0,0 +1,345 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    RNG_GenerateRandomNumbers_IT
+    0x4
+    ARM-ADS
+    
+      16000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rng.c
+      stm32wbxx_ll_rng.c
+      0
+      0
+    
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/MDK-ARM/RNG_GenerateRandomNumbers_IT.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/MDK-ARM/RNG_GenerateRandomNumbers_IT.uvprojx
new file mode 100644
index 000000000..dbf36e699
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/MDK-ARM/RNG_GenerateRandomNumbers_IT.uvprojx
@@ -0,0 +1,477 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      RNG_GenerateRandomNumbers_IT
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          RNG_GenerateRandomNumbers_IT\
+          RNG_GenerateRandomNumbers_IT
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_rng.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rng.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/RNG_GenerateRandomNumbers_IT.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/RNG_GenerateRandomNumbers_IT.ioc
new file mode 100644
index 000000000..b2584efc7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/RNG_GenerateRandomNumbers_IT.ioc
@@ -0,0 +1,129 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=Group By Peripherals
+KeepUserPlacement=false
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=RNG
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA0
+Mcu.Pin1=PB0
+Mcu.Pin2=VP_RNG_VS_RNG
+Mcu.Pin3=VP_SYS_VS_Systick
+Mcu.PinsNb=4
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.EXTI0_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.RNG_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA0.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
+PA0.GPIO_Label=USER_BUTTON
+PA0.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
+PA0.GPIO_PuPd=GPIO_PULLUP
+PA0.Locked=true
+PA0.Signal=GPXTI0
+PB0.GPIOParameters=GPIO_Speed,PinState,GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PB0.Locked=true
+PB0.PinState=GPIO_PIN_RESET
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=RNG_GenerateRandomNumbers_IT.ioc
+ProjectManager.ProjectName=RNG_GenerateRandomNumbers_IT
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false,3-MX_RNG_Init-RNG-false-LL-true
+RCC.AHBFreq_Value=16000000
+RCC.APB1Freq_Value=16000000
+RCC.APB1TimFreq_Value=16000000
+RCC.APB2Freq_Value=16000000
+RCC.APB2TimFreq_Value=16000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=16000000
+RCC.CortexFreq_Value=16000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=16000000
+RCC.FCLKCortexFreq_Value=16000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=16000000
+RCC.HCLK3Freq_Value=16000000
+RCC.HCLKFreq_Value=16000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=16000000
+RCC.I2C3Freq_Value=16000000
+RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=16000000
+RCC.LPTIM2Freq_Value=16000000
+RCC.LPUART1Freq_Value=16000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=16000000
+RCC.PLLM=RCC_PLLM_DIV4
+RCC.PLLN=24
+RCC.PLLPoutputFreq_Value=48000000
+RCC.PLLQoutputFreq_Value=48000000
+RCC.PLLRCLKFreq_Value=48000000
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSI
+RCC.PWRFreq_Value=16000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=16000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_HSI
+RCC.USART1Freq_Value=16000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=96000000
+SH.GPXTI0.0=GPIO_EXTI0
+SH.GPXTI0.ConfNb=1
+VP_RNG_VS_RNG.Mode=RNG_Activate
+VP_RNG_VS_RNG.Signal=RNG_VS_RNG
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..9eaab34a7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/.project
new file mode 100644
index 000000000..cf7747d6b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/.project
@@ -0,0 +1,85 @@
+
+
+	RNG_GenerateRandomNumbers_IT
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			RNG_GenerateRandomNumbers_IT.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/RNG_GenerateRandomNumbers_IT.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_rng.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rng.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..eea98ff9c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb35xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB35xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..4ec95844d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,159 @@
+/**
+ ******************************************************************************
+ * @file      syscalls.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..4665417ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,58 @@
+/**
+ ******************************************************************************
+ * @file      sysmem.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System Memory calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Src/main.c
new file mode 100644
index 000000000..6e0ee576e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Src/main.c
@@ -0,0 +1,465 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to use RNG peripheral for generating random
+  *          numbers using the STM32WBxx RNG LL API.
+  *          Peripheral initialization done using LL unitary services functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+#if (USE_TIMEOUT == 1)
+#define RNG_GENERATION_TIMEOUT   20
+#endif /* USE_TIMEOUT */
+
+#define    NB_OF_GENERATED_RANDOM_NUMBERS      8       /* Nb of Random numbers generated after eash User button press */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+#if (USE_TIMEOUT == 1)
+uint32_t Timeout = 0; /* Variable used for Timeout management */
+#endif /* USE_TIMEOUT */
+__IO uint8_t ubButtonPress = 0;
+__IO uint8_t ubIndex = 0;
+__IO uint8_t ubIsNbGenerated = 0;
+
+/* Array used for storing generated Random 32bit Numbers */
+__IO uint32_t aRandom32bit[NB_OF_GENERATED_RANDOM_NUMBERS];
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_RNG_Init(void);
+/* USER CODE BEGIN PFP */
+
+void     RandomNumbersGenerationIT(void);
+void     LED_On(void);
+void     LED_Blinking(uint32_t Period);
+void     WaitForUserButtonPress(void);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_RNG_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Wait for User push-button (SW1) press to trigger random numbers generation */
+  WaitForUserButtonPress();
+
+  /* Generate Random Numbers series */
+  RandomNumbersGenerationIT();
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  /* HSI configuration and activation */
+  LL_RCC_HSI_Enable();
+  while(LL_RCC_HSI_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the HSI */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(16000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(16000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief RNG Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RNG_Init(void)
+{
+
+  /* USER CODE BEGIN RNG_Init 0 */
+
+  /* USER CODE END RNG_Init 0 */
+
+  /* Peripheral clock enable */
+  LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RNG);
+
+  /* RNG interrupt Init */
+  NVIC_SetPriority(RNG_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(RNG_IRQn);
+
+  /* USER CODE BEGIN RNG_Init 1 */
+  
+  /* Configure PLL to enable 48M domain 
+    - Keep same PLL source (HSI) and PLLM factor (DIV1) used for main PLL
+    - Select PLL_N & PLL_Q to have a frequency of 48MHz
+        * PLL_Q output = (((HSI Freq / PLLM) * PLL_N) / PLL_Q)
+        *              = (((16000000  /  4 ) *  24  ) /  2   ) */
+  LL_RCC_PLL_ConfigDomain_48M(LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLM_DIV_4, 24, LL_RCC_PLLQ_DIV_2);
+  
+  /* Enable PLL*/
+  LL_RCC_PLL_Enable();
+  /*  Enable PLL output mapped on 48MHz domain clock */
+  LL_RCC_PLL_EnableDomain_48M();
+  /* Wait for PLL ready flag */
+  while(LL_RCC_PLL_IsReady() != 1) 
+  {
+  };
+
+  /*  Write the peripherals independent clock configuration register :
+      choose PLL source as the 48 MHz clock is needed for the RNG 
+      Linear Feedback Shift Register */
+  LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLL);
+  LL_RCC_SetRNGClockSource(LL_RCC_RNG_CLKSOURCE_CLK48);
+
+  /* USER CODE END RNG_Init 1 */
+  LL_RNG_Enable(RNG);
+  /* USER CODE BEGIN RNG_Init 2 */
+
+  /* USER CODE END RNG_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_EXTI_InitTypeDef EXTI_InitStruct = {0};
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTA, LL_SYSCFG_EXTI_LINE0);
+
+  /**/
+  EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_0;
+  EXTI_InitStruct.Line_32_63 = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct.LineCommand = ENABLE;
+  EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;
+  EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_FALLING;
+  LL_EXTI_Init(&EXTI_InitStruct);
+
+  /**/
+  LL_GPIO_SetPinPull(USER_BUTTON_GPIO_Port, USER_BUTTON_Pin, LL_GPIO_PULL_UP);
+
+  /**/
+  LL_GPIO_SetPinMode(USER_BUTTON_GPIO_Port, USER_BUTTON_Pin, LL_GPIO_MODE_INPUT);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+  /* EXTI interrupt init*/
+  NVIC_SetPriority(EXTI0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(EXTI0_IRQn);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  This function performs several random numbers generation.
+  * @note   Generated random numbers are stored in global variable array, so that
+  *         generated values could be observed by user by watching variable content
+  *         in specific debugger window
+  * @param  None
+  * @retval None
+  */
+void RandomNumbersGenerationIT(void)
+{
+  /* Initialize random numbers generation */
+  LL_RNG_Enable(RNG);
+
+  /* Generate Random 32bit Numbers */
+  for(ubIndex = 0; ubIndex < NB_OF_GENERATED_RANDOM_NUMBERS; ubIndex++)
+  {
+#if (USE_TIMEOUT == 1)
+    Timeout = RNG_GENERATION_TIMEOUT;
+#endif /* USE_TIMEOUT */
+
+    ubIsNbGenerated = 0;
+
+    /* Enable RNG generation interrupt */
+    LL_RNG_EnableIT(RNG);
+
+    /* Wait for Random Number generation completion */
+    while (ubIsNbGenerated == 0)
+    {
+#if (USE_TIMEOUT == 1)
+      /* Check Systick counter flag to decrement the time-out value */
+      if (LL_SYSTICK_IsActiveCounterFlag()) 
+      { 
+        if(Timeout-- == 0)
+        {
+          /* Time-out occurred. Set LED to blinking mode */
+          LED_Blinking(LED_BLINK_SLOW);
+        }
+      } 
+#endif /* USE_TIMEOUT */
+    }
+  }
+
+  /* Stop random numbers generation */
+  LL_RNG_Disable(RNG);
+
+  /* Values of Generated Random numbers are now available in aRandom32bit array.
+     LED2 is turned on */
+  LED_On();
+}
+
+/**
+  * @brief  Turn-on LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_On(void)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
+  * @param  Period : Period of time (in ms) between each toggling of LED
+  *   This parameter can be user defined values. Pre-defined values used in that example are :
+  *     @arg LED_BLINK_FAST : Fast Blinking
+  *     @arg LED_BLINK_SLOW : Slow Blinking
+  *     @arg LED_BLINK_ERROR : Error specific Blinking
+  * @retval None
+  */
+void LED_Blinking(uint32_t Period)
+{
+  /* Toggle LED2 in an infinite loop */
+  while (1)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);  
+    LL_mDelay(Period);
+  }
+}
+
+/**
+  * @brief  Wait for User push-button (SW1) press to start transfer.
+  * @param  None 
+  * @retval None
+  */
+  /*  */
+void WaitForUserButtonPress(void)
+{
+  while (ubButtonPress == 0)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+    LL_mDelay(LED_BLINK_FAST);
+  }
+  
+  /* Turn LED2 off */
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/******************************************************************************/
+/*   IRQ HANDLER TREATMENT Functions                                          */
+/******************************************************************************/
+
+/**
+  * @brief  Function called when RNG IT is triggered with DRDY flag set
+  * @param  None
+  * @retval None
+  */
+void RNG_DataReady_Callback(void)
+{
+  /* Disable RNG IT generation */
+  LL_RNG_DisableIT(RNG);
+
+  /* Value of generated random number could be retrieved and stored in dedicated array */
+  aRandom32bit[ubIndex] = LL_RNG_ReadRandData32(RNG);
+
+  /* Set Flag indicated random Number generation is completed */
+  ubIsNbGenerated = 1;
+}
+
+/**
+  * @brief  Function called in case of error detected in RNG IT Handler
+  * @param  None
+  * @retval None
+  */
+void Error_Callback(void)
+{
+  /* Disable RNG_IRQn */
+  NVIC_DisableIRQ(RNG_IRQn);
+  
+  /* Clock or Seed Error detected. Set LED to blinking mode (Error type)*/
+  LED_Blinking(LED_BLINK_ERROR);
+}
+
+/**
+  * @brief  Function to manage User push-button (SW1)
+  * @param  None
+  * @retval None
+  */
+void UserButton_Callback(void)
+{
+  /* Update User push-button (SW1) variable : to be checked in waiting loop in main program */
+  ubButtonPress = 1;
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..27dc1624a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Src/stm32wbxx_it.c
@@ -0,0 +1,257 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles EXTI line0 interrupt.
+  */
+void EXTI0_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI0_IRQn 0 */
+
+  /* USER CODE END EXTI0_IRQn 0 */
+  if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
+  {
+    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
+    /* USER CODE BEGIN LL_EXTI_LINE_0 */
+
+    /* Handle user button press in dedicated function */
+    UserButton_Callback();
+    /* USER CODE END LL_EXTI_LINE_0 */
+  }
+  /* USER CODE BEGIN EXTI0_IRQn 1 */
+
+
+  /* USER CODE END EXTI0_IRQn 1 */
+}
+
+/**
+  * @brief This function handles RNG global interrupt.
+  */
+void RNG_IRQHandler(void)
+{
+  /* USER CODE BEGIN RNG_IRQn 0 */
+ if (   (LL_RNG_IsActiveFlag_CECS(RNG))
+       || (LL_RNG_IsActiveFlag_SECS(RNG))  )
+   { 
+     /* Call Error function */
+     Error_Callback();
+   }
+
+  /* USER CODE END RNG_IRQn 0 */
+  /* USER CODE BEGIN RNG_IRQn 1 */
+   if(LL_RNG_IsActiveFlag_DRDY(RNG))
+   {
+     /* DRDY flag will be automatically cleared when reading 
+        newly generated random number in DR register */
+
+     /* Call function in charge of handling DR reading */
+     RNG_DataReady_Callback();
+  }
+
+  /* USER CODE END RNG_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..4cb9e0e42
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx) || defined(STM32WB5Mxx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/readme.txt
new file mode 100644
index 000000000..f05e99765
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/readme.txt
@@ -0,0 +1,71 @@
+/**
+  @page RNG_GenerateRandomNumbers_IT RNG : Random Number Generation using IT
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the RNG_GenerateRandomNumbers_IT example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+Configuration of the RNG to generate 32-bit long random numbers using interrupts. The peripheral initialization uses LL unitary service
+functions for optimization purposes (performance and size).
+
+Example execution:
+After startup from reset and system configuration, RNG configuration is performed.
+(Configure Main PLL to enable 48M domain, then enable PLLQ output mapped on 48MHz domain clock).
+
+User is then asked to press User push-button (SW1) (LED2 blinking fast).
+On User push-button (SW1) press, several (8) Random 32bit numbers are generated
+(On each raised RNG interrupt, a random number is generated and retrieved from DR register).
+Corresponding generated values are available and stored in a u32 array (aRandom32bit), 
+whose content could be displayed using debugger (Watch or LiveWatch features).
+After successful Random numbers generation, LED2 is turned On. 
+In case of errors, LED2 is slowly blinking (1sec period).
+
+
+@par Keywords
+
+Analog, RNG, Random, FIPS PUB 140-2, Analog Random number generator, Entropy, Period, Interrupt
+
+
+@par Directory contents 
+
+  - RNG/RNG_GenerateRandomNumbers_IT/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - RNG/RNG_GenerateRandomNumbers_IT/Inc/main.h                  Header for main.c module
+  - RNG/RNG_GenerateRandomNumbers_IT/Inc/stm32_assert.h          Template file to include assert_failed function
+  - RNG/RNG_GenerateRandomNumbers_IT/Src/stm32wbxx_it.c          Interrupt handlers
+  - RNG/RNG_GenerateRandomNumbers_IT/Src/main.c                  Main program
+  - RNG/RNG_GenerateRandomNumbers_IT/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+ - Push User push-button (SW1) and use Variable watch window from debugger to access to values of generated numbers.
+   (A break point could be set on LED_On() call, at end of RandomNumbersGeneration_IT() function).
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/Project.eww
new file mode 100644
index 000000000..8c53cac85
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\RTC_ExitStandbyWithWakeUpTimer_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/RTC_ExitStandbyWithWakeUpTimer_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/RTC_ExitStandbyWithWakeUpTimer_Init.ewd
new file mode 100644
index 000000000..166cba1bb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/RTC_ExitStandbyWithWakeUpTimer_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		RTC_ExitStandbyWithWakeUpTimer_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/RTC_ExitStandbyWithWakeUpTimer_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/RTC_ExitStandbyWithWakeUpTimer_Init.ewp
new file mode 100644
index 000000000..765f4d43e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/RTC_ExitStandbyWithWakeUpTimer_Init.ewp
@@ -0,0 +1,1083 @@
+
+
+  3
+  
+    RTC_ExitStandbyWithWakeUpTimer_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Inc/main.h
new file mode 100644
index 000000000..f94fe290c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Inc/main.h
@@ -0,0 +1,111 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "stm32wbxx_ll_rtc.h"
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+/* Define used to enable time-out management*/
+#define USE_TIMEOUT       0
+/**
+  * @brief Toggle periods for various blinking modes
+  */
+
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW 500
+#define LED_BLINK_ERROR 1000
+
+
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+/* IRQ Handler treatment. */
+void UserButton_Callback(void);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..31ac73759
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,73 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void EXTI0_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+void USER_BUTTON_IRQHANDLER(void);
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/MDK-ARM/RTC_ExitStandbyWithWakeUpTimer_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/MDK-ARM/RTC_ExitStandbyWithWakeUpTimer_Init.uvoptx
new file mode 100644
index 000000000..e0858360a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/MDK-ARM/RTC_ExitStandbyWithWakeUpTimer_Init.uvoptx
@@ -0,0 +1,333 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    RTC_ExitStandbyWithWakeUpTimer_Init
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      4
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      4
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/MDK-ARM/RTC_ExitStandbyWithWakeUpTimer_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/MDK-ARM/RTC_ExitStandbyWithWakeUpTimer_Init.uvprojx
new file mode 100644
index 000000000..ca47b5c5a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/MDK-ARM/RTC_ExitStandbyWithWakeUpTimer_Init.uvprojx
@@ -0,0 +1,472 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      RTC_ExitStandbyWithWakeUpTimer_Init
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          RTC_ExitStandbyWithWakeUpTimer_Init\
+          RTC_ExitStandbyWithWakeUpTimer_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/RTC_ExitStandbyWithWakeUpTimer_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/RTC_ExitStandbyWithWakeUpTimer_Init.ioc
new file mode 100644
index 000000000..8cf726c17
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/RTC_ExitStandbyWithWakeUpTimer_Init.ioc
@@ -0,0 +1,120 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA0
+Mcu.Pin1=PB0
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.EXTI0_IRQn=true\:3\:0\:true\:false\:true\:true\:true
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA0.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultEXTI
+PA0.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
+PA0.GPIO_PuPd=GPIO_PULLUP
+PA0.Locked=true
+PA0.Signal=GPXTI0
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=RTC_ExitStandbyWithWakeUpTimer_Init.ioc
+ProjectManager.ProjectName=RTC_ExitStandbyWithWakeUpTimer_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SH.GPXTI0.0=GPIO_EXTI0
+SH.GPXTI0.ConfNb=1
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..cecd74c7a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..347d37b07
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/.project
@@ -0,0 +1,80 @@
+
+
+	RTC_ExitStandbyWithWakeUpTimer_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			RTC_ExitStandbyWithWakeUpTimer_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/RTC_ExitStandbyWithWakeUpTimer_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Src/main.c
new file mode 100644
index 000000000..4dc739308
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Src/main.c
@@ -0,0 +1,538 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This code example shows how to configure the RTC in order to work
+  *          with the WUT through the STM32WBxx RTC LL API.
+  *          Peripheral initialization done using LL unitary services functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* Value defined for WUT */
+#define RTC_WUT_TIME               ((uint32_t)5)     /* 5 s */
+
+/* Oscillator time-out values */
+#define LSI_TIMEOUT_VALUE          ((uint32_t)100)   /* 100 ms */
+#define LSE_TIMEOUT_VALUE          ((uint32_t)5000)  /* 5 s */
+#define RTC_TIMEOUT_VALUE          ((uint32_t)1000)  /* 1 s */
+
+/* Defines related to Clock configuration */
+/* Uncomment to enable the adequate Clock Source */
+#define RTC_CLOCK_SOURCE_LSE
+/*#define RTC_CLOCK_SOURCE_LSI*/
+
+#ifdef RTC_CLOCK_SOURCE_LSI
+/* ck_apre=LSIFreq/(ASYNC prediv + 1) = 256Hz with LSIFreq=32 kHz RC */
+#define RTC_ASYNCH_PREDIV          ((uint32_t)0x7F)
+/* ck_spre=ck_apre/(SYNC prediv + 1) = 1 Hz */
+#define RTC_SYNCH_PREDIV           ((uint32_t)0x00F9)
+#endif
+
+#ifdef RTC_CLOCK_SOURCE_LSE
+/* ck_apre=LSEFreq/(ASYNC prediv + 1) = 256Hz with LSEFreq=32768Hz */
+#define RTC_ASYNCH_PREDIV          ((uint32_t)0x7F)
+/* ck_spre=ck_apre/(SYNC prediv + 1) = 1 Hz */
+#define RTC_SYNCH_PREDIV           ((uint32_t)0x00FF)
+#endif
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+__IO uint8_t ubButtonPress = 0;
+
+#if (USE_TIMEOUT == 1)
+uint32_t Timeout = 0; /* Variable used for Timeout management */
+#endif /* USE_TIMEOUT */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+/* USER CODE BEGIN PFP */
+void     Configure_RTC(void);
+void     EnterStandbyMode(void);
+void     LED_Blinking(uint32_t Period);
+void     WaitForUserButtonPress(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Configure RTC to use WUT */
+  Configure_RTC();
+  /* Note: On STM32WB, both CPU1 and CPU2 must be in standby mode to set the entire system in standby mode */
+  if ((LL_PWR_IsActiveFlag_C1SB() != 0)
+      && (LL_PWR_IsActiveFlag_C2SB() != 0)
+     )
+  {
+    /* ##### Run after standby mode ##### */
+    /* Clear Standby flag */
+    LL_PWR_ClearFlag_C1STOP_C1STB();
+    LL_PWR_ClearFlag_C1STOP_C1STB();
+
+    /* Reset RTC Internal Wake up flag */
+    LL_RTC_ClearFlag_WUT(RTC);
+
+    /* Slow Toggle LED */
+    LED_Blinking(LED_BLINK_SLOW);
+  }
+  else
+  {
+    /* ##### Run after normal reset ##### */
+    /* Fast Toggle LED in waiting for user-button press */
+    WaitForUserButtonPress();
+
+    /* Enable wake-up timer and enter in standby mode */
+    EnterStandbyMode();
+  }
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* MSI configuration and activation */
+  LL_RCC_MSI_Enable();
+  while(LL_RCC_MSI_IsReady() != 1)
+  {
+  };
+
+  /* Main PLL configuration and activation */
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 32, LL_RCC_PLLR_DIV_2);
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the main PLL */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(64000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(64000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_EXTI_InitTypeDef EXTI_InitStruct = {0};
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTA, LL_SYSCFG_EXTI_LINE0);
+
+  /**/
+  EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_0;
+  EXTI_InitStruct.Line_32_63 = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct.LineCommand = ENABLE;
+  EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;
+  EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_FALLING;
+  LL_EXTI_Init(&EXTI_InitStruct);
+
+  /**/
+  LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_0, LL_GPIO_PULL_UP);
+
+  /**/
+  LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_0, LL_GPIO_MODE_INPUT);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+  /* EXTI interrupt init*/
+  NVIC_SetPriority(EXTI0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),3, 0));
+  NVIC_EnableIRQ(EXTI0_IRQn);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * Brief   This function configures RTC.
+  * Param   None
+  * Retval  None
+  */
+void Configure_RTC(void)
+{
+  /*##-1- Enables the PWR Clock and Enables access to the backup domain #######*/
+  /* To change the source clock of the RTC feature (LSE, LSI), you have to:
+     - Enable the power clock
+     - Enable write access to configure the RTC clock source (to be done once after reset).
+     - Reset the Back up Domain
+     - Configure the needed RTC clock source */
+  LL_PWR_EnableBkUpAccess();
+
+  /*##-2- Configure LSE/LSI as RTC clock source ###############################*/
+#ifdef RTC_CLOCK_SOURCE_LSE
+  /* Enable LSE only if disabled.*/
+  if (LL_RCC_LSE_IsReady() == 0)
+  {
+    LL_RCC_ForceBackupDomainReset();
+    LL_RCC_ReleaseBackupDomainReset();
+    LL_RCC_LSE_Enable();
+#if (USE_TIMEOUT == 1)
+    Timeout = LSE_TIMEOUT_VALUE;
+#endif /* USE_TIMEOUT */
+    while (LL_RCC_LSE_IsReady() != 1)
+    {
+#if (USE_TIMEOUT == 1)
+      if (LL_SYSTICK_IsActiveCounterFlag())
+      {
+        Timeout --;
+      }
+      if (Timeout == 0)
+      {
+        /* LSE activation error */
+        LED_Blinking(LED_BLINK_ERROR);
+      }
+#endif /* USE_TIMEOUT */
+    }
+    LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSE);
+
+    /*##-3- Enable RTC peripheral Clocks #######################################*/
+    /* Enable RTC Clock */
+    LL_RCC_EnableRTC();
+  }
+#elif defined(RTC_CLOCK_SOURCE_LSI)
+  if (LL_RCC_LSI1_IsReady() == 0)
+  {
+    LL_RCC_ForceBackupDomainReset();
+    LL_RCC_ReleaseBackupDomainReset();
+    LL_RCC_LSI1_Enable();
+#if (USE_TIMEOUT == 1)
+    Timeout = LSI_TIMEOUT_VALUE;
+#endif /* USE_TIMEOUT */
+    while (LL_RCC_LSI1_IsReady() != 1)
+    {
+#if (USE_TIMEOUT == 1)
+      if (LL_SYSTICK_IsActiveCounterFlag())
+      {
+        Timeout --;
+      }
+      if (Timeout == 0)
+      {
+        /* LSI1 activation error */
+        LED_Blinking(LED_BLINK_ERROR);
+      }
+#endif /* USE_TIMEOUT */
+    }
+    LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSI);
+
+    /*##-3- Enable RTC peripheral Clocks #######################################*/
+    /* Enable RTC Clock */
+    LL_RCC_EnableRTC();
+  }
+
+#else
+#error "configure clock for RTC"
+#endif
+
+  /*##-4- Configure RTC ######################################################*/
+  /* Disable RTC registers write protection */
+  LL_RTC_DisableWriteProtection(RTC);
+
+  /* Set prescaler according to source clock */
+  LL_RTC_SetAsynchPrescaler(RTC, RTC_ASYNCH_PREDIV);
+  LL_RTC_SetSynchPrescaler(RTC, RTC_SYNCH_PREDIV);
+
+  /* Disable wake up timer to modify it */
+  LL_RTC_WAKEUP_Disable(RTC);
+
+  /* Wait until it is allow to modify wake up reload value */
+#if (USE_TIMEOUT == 1)
+  Timeout = RTC_TIMEOUT_VALUE;
+#endif /* USE_TIMEOUT */
+
+  while (LL_RTC_IsActiveFlag_WUTW(RTC) != 1)
+  {
+#if (USE_TIMEOUT == 1)
+    if (LL_SYSTICK_IsActiveCounterFlag())
+    {
+      Timeout --;
+    }
+    if (Timeout == 0)
+    {
+      /* LSI activation error */
+      LED_Blinking(LED_BLINK_ERROR);
+    }
+#endif /* USE_TIMEOUT */
+  }
+
+  /* Setting the Wakeup time to RTC_WUT_TIME s
+       If LL_RTC_WAKEUPCLOCK_CKSPRE is selected, the frequency is 1Hz,
+       this allows to get a wakeup time equal to RTC_WUT_TIME s
+       if the counter is RTC_WUT_TIME */
+  LL_RTC_WAKEUP_SetAutoReload(RTC, RTC_WUT_TIME);
+  LL_RTC_WAKEUP_SetClock(RTC, LL_RTC_WAKEUPCLOCK_CKSPRE);
+
+  /* Enable RTC registers write protection */
+  LL_RTC_EnableWriteProtection(RTC);
+
+}
+/**
+  * @brief  Function to configure and enter in STANDBY Mode.
+  * @param  None
+  * @retval None
+  */
+void EnterStandbyMode(void)
+{
+  /* ######## ENABLE WUT #################################################*/
+  /* Disable RTC registers write protection */
+  LL_RTC_DisableWriteProtection(RTC);
+
+  /* Enable wake up counter and wake up interrupt */
+  /* Note: Periodic wakeup interrupt should be enabled to exit the device
+     from low-power modes.*/
+  LL_RTC_EnableIT_WUT(RTC);
+  LL_RTC_WAKEUP_Enable(RTC);
+
+  /* Enable RTC registers write protection */
+  LL_RTC_EnableWriteProtection(RTC);
+
+  /* ######## ENTER IN STANDBY MODE ######################################*/
+  /** Request to enter STANDBY mode
+    * Following procedure describe in STM32WBxx Reference Manual
+    * See PWR part, section Low-power modes, Standby mode
+    */
+  /* Reset Internal Wake up flag */
+  LL_RTC_ClearFlag_WUT(RTC);
+
+  /* Check that PWR Internal Wake-up is enabled */
+  if (LL_PWR_IsEnabledInternWU() == 0)
+  {
+    /* Need to enable the Internal Wake-up line */
+    LL_PWR_EnableInternWU();
+  }
+
+  /* Set Standby mode */
+  LL_PWR_SetPowerMode(LL_PWR_MODE_STANDBY);
+
+  /* Set Standby mode of CPU2 */
+  /* Note: On STM32WB, both CPU1 and CPU2 must be in Standby mode to set the entire system in Standby mode */
+  LL_C2_PWR_SetPowerMode(LL_PWR_MODE_STANDBY);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  LL_LPM_EnableDeepSleep();
+
+  /* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/**
+  * @brief  Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
+  * @param  Period : Period of time (in ms) between each toggling of LED
+  *   This parameter can be user defined values. Pre-defined values used in that example are :
+  *     @arg LED_BLINK_FAST : Fast Blinking
+  *     @arg LED_BLINK_SLOW : Slow Blinking
+  *     @arg LED_BLINK_ERROR : Error specific Blinking
+  * @retval None
+  */
+void LED_Blinking(uint32_t Period)
+{
+  /* Toggle IO in an infinite loop */
+  while (1)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+    LL_mDelay(Period);
+  }
+}
+
+/**
+  * @brief  Wait for User push-button (SW1) press to start transfer.
+  * @param  None
+  * @retval None
+  */
+/*  */
+void WaitForUserButtonPress(void)
+{
+  while (ubButtonPress == 0)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+    LL_mDelay(LED_BLINK_FAST);
+  }
+}
+
+
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT                                               */
+/******************************************************************************/
+/**
+  * @brief  Function to manage User button
+  * @param  None
+  * @retval None
+  */
+void UserButton_Callback(void)
+{
+  /* Update User push-button (SW1) variable : to be checked in waiting loop in main function */
+  ubButtonPress = 1;
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..59508005a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,227 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles EXTI line0 interrupt.
+  */
+void EXTI0_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI0_IRQn 0 */
+
+  /* USER CODE END EXTI0_IRQn 0 */
+  if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
+  {
+    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
+    /* USER CODE BEGIN LL_EXTI_LINE_0 */
+    UserButton_Callback();
+    /* USER CODE END LL_EXTI_LINE_0 */
+  }
+  /* USER CODE BEGIN EXTI0_IRQn 1 */
+
+  /* USER CODE END EXTI0_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/readme.txt
new file mode 100644
index 000000000..0a743beb1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/readme.txt
@@ -0,0 +1,83 @@
+/**
+  @page RTC_ExitStandbyWithWakeUpTimer_Init RTC example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/RTC/RTC_ExitStandbyWithWakeUpTimer_Init/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the RTC example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+Configuration of the RTC to wake up from Standby mode 
+using the RTC Wakeup timer. The peripheral initialization uses LL unitary service 
+functions for optimization purposes (performance and size).
+  
+In this example, after start-up, SYSCLK is configured to the max frequency using
+the PLL with MSI as clock source.
+
+   @note LSE oscillator clock is used as RTC clock source by default.
+      The user can use also LSI as RTC clock source. The user uncomment the adequate 
+      line on the main.c file.
+      @code
+        #define RTC_CLOCK_SOURCE_LSE  
+        /* #define RTC_CLOCK_SOURCE_LSI */
+      @endcode
+      LSI oscillator clock is delivered by a 32 kHz RC.
+      LSE (when available on board) is delivered by a 32.768 kHz crystal.
+
+   @note RTC wake up timer is one-second resolution based due to 1Hz internal frequency configuration.
+
+Example execution:
+   - 1st execution of the system, LED2 is quickly blinking (every 200ms).
+   - RTC wakup timer is configured to 5 seconds
+   - Press the User push-button (SW1):
+     * System enters in standby mode (LED2 is switched off)
+   - After 5 seconds, system resumes from standby mode, then LED2 is slowly blinking (every 500ms).
+
+   - LED2 is toggling every 1 second: This indicates that the system generates an error.
+
+
+
+@par Keywords
+
+System, RTC, RTC Wakeup timer, Standby mode, LSI, LSE, Interrupt,
+
+@par Directory contents 
+
+  - RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Inc/main.h                  Header for main.c module
+  - RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Inc/stm32_assert.h          Template file to include assert_failed function
+  - RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Src/main.c                  Main program
+  - RTC/RTC_ExitStandbyWithWakeUpTimer_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/.extSettings
new file mode 100644
index 000000000..d9196e942
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/.extSettings
@@ -0,0 +1,9 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Application/User=../Src/main.c;../Src/stm32wbxx_it.c;
+Doc=../readme.txt;
+Drivers/STM32WBxx_HAL_Driver=../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/Project.eww
new file mode 100644
index 000000000..cd6af3855
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\SPI_TwoBoards_FullDuplex_DMA_Master_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/SPI_TwoBoards_FullDuplex_DMA_Master_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/SPI_TwoBoards_FullDuplex_DMA_Master_Init.ewd
new file mode 100644
index 000000000..f301249b6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/SPI_TwoBoards_FullDuplex_DMA_Master_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		SPI_TwoBoards_FullDuplex_DMA_Master_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/SPI_TwoBoards_FullDuplex_DMA_Master_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/SPI_TwoBoards_FullDuplex_DMA_Master_Init.ewp
new file mode 100644
index 000000000..135aaff91
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/SPI_TwoBoards_FullDuplex_DMA_Master_Init.ewp
@@ -0,0 +1,1092 @@
+
+
+  3
+  
+    SPI_TwoBoards_FullDuplex_DMA_Master_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Inc/main.h
new file mode 100644
index 000000000..ab68bd974
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Inc/main.h
@@ -0,0 +1,129 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_spi.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/**
+  * @brief LED2
+  */
+#define LED2_PIN                           LL_GPIO_PIN_0
+#define LED2_GPIO_PORT                     GPIOB
+
+/**
+  * @brief Toggle periods for various blinking modes
+  */
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW  500
+#define LED_BLINK_ERROR 1000
+
+/**
+  * @brief Key push-button
+  */
+#define USER_BUTTON_PIN                         LL_GPIO_PIN_0
+#define USER_BUTTON_GPIO_PORT                   GPIOA
+#define USER_BUTTON_GPIO_CLK_ENABLE()           LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA)
+#define USER_BUTTON_EXTI_LINE                   LL_EXTI_LINE_0
+#define USER_BUTTON_EXTI_IRQn                   EXTI0_IRQn
+#define USER_BUTTON_EXTI_LINE_ENABLE()          LL_EXTI_EnableIT_0_31(USER_BUTTON_EXTI_LINE)
+#define USER_BUTTON_EXTI_FALLING_TRIG_ENABLE()  LL_EXTI_EnableFallingTrig_0_31(USER_BUTTON_EXTI_LINE)
+#define USER_BUTTON_SYSCFG_SET_EXTI()           do {                                                                     \
+                                                  LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTA, LL_SYSCFG_EXTI_LINE0);  \
+                                                } while(0)
+#define USER_BUTTON_IRQHANDLER                  EXTI0_IRQHandler
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+void DMA1_ReceiveComplete_Callback(void);
+void DMA1_TransmitComplete_Callback(void);
+void SPI1_TransferError_Callback(void);
+void UserButton_Callback(void);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..57fe99180
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void USER_BUTTON_IRQHANDLER(void);
+void DMA1_Channel3_IRQHandler(void);
+void DMA1_Channel1_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/MDK-ARM/SPI_TwoBoards_FullDuplex_DMA_Master_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/MDK-ARM/SPI_TwoBoards_FullDuplex_DMA_Master_Init.uvoptx
new file mode 100644
index 000000000..e75e0699c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/MDK-ARM/SPI_TwoBoards_FullDuplex_DMA_Master_Init.uvoptx
@@ -0,0 +1,369 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    SPI_TwoBoards_FullDuplex_DMA_Master_Init
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066CFF303337554E43183920 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      4
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      4
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      stm32wbxx_ll_dma.c
+      0
+      0
+    
+    
+      4
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c
+      stm32wbxx_ll_spi.c
+      0
+      0
+    
+    
+      4
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+    
+      4
+      11
+      1
+      0
+      0
+      0
+      ..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_ll_rcc.c
+      stm32wbxx_ll_rcc.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      5
+      12
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/MDK-ARM/SPI_TwoBoards_FullDuplex_DMA_Master_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/MDK-ARM/SPI_TwoBoards_FullDuplex_DMA_Master_Init.uvprojx
new file mode 100644
index 000000000..0141e6455
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/MDK-ARM/SPI_TwoBoards_FullDuplex_DMA_Master_Init.uvprojx
@@ -0,0 +1,487 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      SPI_TwoBoards_FullDuplex_DMA_Master_Init
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          SPI_TwoBoards_FullDuplex_DMA_Master_Init\
+          SPI_TwoBoards_FullDuplex_DMA_Master_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x40000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000004
+                0x8000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+            
+            
+              stm32wbxx_ll_spi.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+            
+              stm32wbxx_ll_rcc.c
+              1
+              ..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_ll_rcc.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/SPI_TwoBoards_FullDuplex_DMA_Master_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/SPI_TwoBoards_FullDuplex_DMA_Master_Init.ioc
new file mode 100644
index 000000000..19f6daddc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/SPI_TwoBoards_FullDuplex_DMA_Master_Init.ioc
@@ -0,0 +1,183 @@
+#MicroXplorer Configuration settings - do not modify
+Dma.Request0=SPI1_TX
+Dma.Request1=SPI1_RX
+Dma.RequestsNb=2
+Dma.SPI1_RX.1.Direction=DMA_PERIPH_TO_MEMORY
+Dma.SPI1_RX.1.EventEnable=DISABLE
+Dma.SPI1_RX.1.Instance=DMA1_Channel1
+Dma.SPI1_RX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.SPI1_RX.1.MemInc=DMA_MINC_ENABLE
+Dma.SPI1_RX.1.Mode=DMA_NORMAL
+Dma.SPI1_RX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.SPI1_RX.1.PeriphInc=DMA_PINC_DISABLE
+Dma.SPI1_RX.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.SPI1_RX.1.Priority=DMA_PRIORITY_LOW
+Dma.SPI1_RX.1.RequestNumber=1
+Dma.SPI1_RX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.SPI1_RX.1.SignalID=HAL_DMAMUX1_REQ_GEN_EXTI4
+Dma.SPI1_RX.1.SyncEnable=DISABLE
+Dma.SPI1_RX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.SPI1_RX.1.SyncRequestNumber=1
+Dma.SPI1_RX.1.SyncSignalID=HAL_DMAMUX1_SYNC_EXTI4
+Dma.SPI1_TX.0.Direction=DMA_MEMORY_TO_PERIPH
+Dma.SPI1_TX.0.EventEnable=DISABLE
+Dma.SPI1_TX.0.Instance=DMA1_Channel3
+Dma.SPI1_TX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.SPI1_TX.0.MemInc=DMA_MINC_ENABLE
+Dma.SPI1_TX.0.Mode=DMA_NORMAL
+Dma.SPI1_TX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.SPI1_TX.0.PeriphInc=DMA_PINC_DISABLE
+Dma.SPI1_TX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.SPI1_TX.0.Priority=DMA_PRIORITY_LOW
+Dma.SPI1_TX.0.RequestNumber=1
+Dma.SPI1_TX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.SPI1_TX.0.SignalID=HAL_DMAMUX1_REQ_GEN_EXTI4
+Dma.SPI1_TX.0.SyncEnable=DISABLE
+Dma.SPI1_TX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.SPI1_TX.0.SyncRequestNumber=1
+Dma.SPI1_TX.0.SyncSignalID=HAL_DMAMUX1_SYNC_EXTI4
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=DMA
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SPI1
+Mcu.IP4=SYS
+Mcu.IPNb=5
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA5
+Mcu.Pin1=PA6
+Mcu.Pin2=PA7
+Mcu.Pin3=PB0
+Mcu.Pin4=VP_SYS_VS_Systick
+Mcu.PinsNb=5
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:false\:false\:false
+NVIC.DMA1_Channel3_IRQn=true\:0\:0\:false\:false\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA5.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA5.GPIO_PuPd=GPIO_PULLDOWN
+PA5.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PA5.Locked=true
+PA5.Mode=Full_Duplex_Master
+PA5.Signal=SPI1_SCK
+PA6.GPIOParameters=GPIO_Speed
+PA6.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PA6.Mode=Full_Duplex_Master
+PA6.Signal=SPI1_MISO
+PA7.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA7.GPIO_PuPd=GPIO_PULLDOWN
+PA7.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PA7.Mode=Full_Duplex_Master
+PA7.Signal=SPI1_MOSI
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=false
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=SPI_TwoBoards_FullDuplex_DMA_Master_Init.ioc
+ProjectManager.ProjectName=SPI_TwoBoards_FullDuplex_DMA_Master_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-MX_DMA_Init-DMA-false-LL-true,3-SystemClock_Config-RCC-false-LL-true,4-MX_SPI1_Init-SPI1-false-LL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_256
+SPI1.CLKPhase=SPI_PHASE_2EDGE
+SPI1.CLKPolarity=SPI_POLARITY_HIGH
+SPI1.CRCCalculation=SPI_CRCCALCULATION_DISABLE
+SPI1.CalculateBaudRate=250.0 KBits/s
+SPI1.DataSize=SPI_DATASIZE_8BIT
+SPI1.Direction=SPI_DIRECTION_2LINES
+SPI1.FirstBit=SPI_FIRSTBIT_MSB
+SPI1.IPParameters=TIMode,DataSize,FirstBit,BaudRatePrescaler,CLKPolarity,CLKPhase,CRCCalculation,NSS,VirtualType,Mode,Direction,CalculateBaudRate
+SPI1.Mode=SPI_MODE_MASTER
+SPI1.NSS=SPI_NSS_SOFT
+SPI1.TIMode=SPI_TIMODE_DISABLE
+SPI1.VirtualType=VM_MASTER
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..449b23f86
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..4adc57366
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/.project
@@ -0,0 +1,90 @@
+
+
+	SPI_TwoBoards_FullDuplex_DMA_Master_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			SPI_TwoBoards_FullDuplex_DMA_Master_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/SPI_TwoBoards_FullDuplex_DMA_Master_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_spi.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..eea98ff9c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb35xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB35xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..4ec95844d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,159 @@
+/**
+ ******************************************************************************
+ * @file      syscalls.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..4665417ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,58 @@
+/**
+ ******************************************************************************
+ * @file      sysmem.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System Memory calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Src/main.c
new file mode 100644
index 000000000..7cc1c3dba
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Src/main.c
@@ -0,0 +1,634 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to send/receive bytes over SPI IP using
+  *          the STM32WBxx SPI LL API.
+  *          Peripheral initialization done using LL unitary services functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+__IO uint8_t ubButtonPress = 0;
+
+/* Buffer used for transmission */
+uint8_t aTxBuffer[] = "**** SPI_TwoBoards_FullDuplex_DMA communication **** SPI_TwoBoards_FullDuplex_DMA communication **** SPI_TwoBoards_FullDuplex_DMA communication ****";
+uint8_t ubNbDataToTransmit = sizeof(aTxBuffer);
+__IO uint8_t ubTransmissionComplete = 0;
+
+/* Buffer used for reception */
+uint8_t aRxBuffer[sizeof(aTxBuffer)];
+uint8_t ubNbDataToReceive  = sizeof(aTxBuffer);
+__IO uint8_t ubReceptionComplete = 0;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+static void MX_SPI1_Init(void);
+/* USER CODE BEGIN PFP */
+
+void     SystemClock_Config(void);
+void     Activate_SPI(void);
+void     LED_On(void);
+void     LED_Blinking(uint32_t Period);
+void     LED_Off(void);
+void     UserButton_Init(void);
+void     WaitForUserButtonPress(void);
+void     WaitAndCheckEndOfTransfer(void);
+uint8_t  Buffercmp8(uint8_t *pBuffer1, uint8_t *pBuffer2, uint8_t BufferLength);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_SPI1_Init();
+  /* USER CODE BEGIN 2 */
+  UserButton_Init();
+  /* Configure the DMA1_Channel3 functional parameters */
+  LL_DMA_ConfigTransfer(DMA1,
+                        LL_DMA_CHANNEL_3,
+                        LL_DMA_DIRECTION_MEMORY_TO_PERIPH | LL_DMA_PRIORITY_HIGH | LL_DMA_MODE_NORMAL |
+                        LL_DMA_PERIPH_NOINCREMENT | LL_DMA_MEMORY_INCREMENT |
+                        LL_DMA_PDATAALIGN_BYTE | LL_DMA_MDATAALIGN_BYTE);
+  LL_DMA_ConfigAddresses(DMA1,
+                         LL_DMA_CHANNEL_3,
+                         (uint32_t)aTxBuffer, LL_SPI_DMA_GetRegAddr(SPI1),
+                         LL_DMA_GetDataTransferDirection(DMA1, LL_DMA_CHANNEL_3));
+  LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_3, ubNbDataToReceive);
+
+  LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_3, LL_DMAMUX_REQ_SPI1_TX);
+
+
+  /* Configure the DMA1_Channel1 functional parameters */
+  LL_DMA_ConfigTransfer(DMA1,
+                        LL_DMA_CHANNEL_1,
+                        LL_DMA_DIRECTION_PERIPH_TO_MEMORY | LL_DMA_PRIORITY_HIGH | LL_DMA_MODE_NORMAL |
+                        LL_DMA_PERIPH_NOINCREMENT | LL_DMA_MEMORY_INCREMENT |
+                        LL_DMA_PDATAALIGN_BYTE | LL_DMA_MDATAALIGN_BYTE);
+  LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_1, LL_SPI_DMA_GetRegAddr(SPI1), (uint32_t)aRxBuffer,
+                         LL_DMA_GetDataTransferDirection(DMA1, LL_DMA_CHANNEL_1));
+  LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_1, ubNbDataToTransmit);
+  LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_SPI1_RX);
+
+
+  /* Enable DMA interrupts complete/error */
+  LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_3);
+  LL_DMA_EnableIT_TE(DMA1, LL_DMA_CHANNEL_3);
+  LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_1);
+  LL_DMA_EnableIT_TE(DMA1, LL_DMA_CHANNEL_1);
+
+  /* Initialize FFIFO Threshold */
+  LL_SPI_SetRxFIFOThreshold(SPI1, LL_SPI_RX_FIFO_TH_QUARTER);
+
+  /* Configure SPI1 DMA transfer interrupts */
+  /* Enable DMA TX Interrupt */
+  LL_SPI_EnableDMAReq_TX(SPI1);
+
+  /* Configure SPI1 DMA transfer interrupts */
+  /* Enable DMA RX Interrupt */
+  LL_SPI_EnableDMAReq_RX(SPI1);
+
+  /* Wait for User push-button (SW1) press to start transfer */
+  WaitForUserButtonPress();
+
+  /* Enable the SPI1 peripheral */
+  Activate_SPI();
+
+  /* Wait for the end of the transfer and check received data */
+  /* LED blinking FAST during waiting time */
+  WaitAndCheckEndOfTransfer();
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* MSI configuration and activation */
+  LL_RCC_MSI_Enable();
+  while(LL_RCC_MSI_IsReady() != 1)
+  {
+  };
+
+  /* Main PLL configuration and activation */
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 32, LL_RCC_PLLR_DIV_2);
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the main PLL */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(64000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(64000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief SPI1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SPI1_Init(void)
+{
+
+  /* USER CODE BEGIN SPI1_Init 0 */
+
+  /* USER CODE END SPI1_Init 0 */
+
+  LL_SPI_InitTypeDef SPI_InitStruct = {0};
+
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* Peripheral clock enable */
+  LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1);
+  
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  /**SPI1 GPIO Configuration  
+  PA5   ------> SPI1_SCK
+  PA6   ------> SPI1_MISO
+  PA7   ------> SPI1_MOSI 
+  */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_5|LL_GPIO_PIN_7;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_DOWN;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+  LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_6;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+  LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* SPI1 DMA Init */
+  
+  /* SPI1_TX Init */
+  LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_3, LL_DMAMUX_REQ_SPI1_TX);
+
+  LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_3, LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
+
+  LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PRIORITY_LOW);
+
+  LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MODE_NORMAL);
+
+  LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PERIPH_NOINCREMENT);
+
+  LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MEMORY_INCREMENT);
+
+  LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PDATAALIGN_BYTE);
+
+  LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MDATAALIGN_BYTE);
+
+  /* SPI1_RX Init */
+  LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_SPI1_RX);
+
+  LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_1, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+
+  LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PRIORITY_LOW);
+
+  LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MODE_NORMAL);
+
+  LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PERIPH_NOINCREMENT);
+
+  LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MEMORY_INCREMENT);
+
+  LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PDATAALIGN_BYTE);
+
+  LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MDATAALIGN_BYTE);
+
+  /* USER CODE BEGIN SPI1_Init 1 */
+
+  /* USER CODE END SPI1_Init 1 */
+  /* SPI1 parameter configuration*/
+  SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX;
+  SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+  SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_8BIT;
+  SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH;
+  SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE;
+  SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+  SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV256;
+  SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+  SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+  SPI_InitStruct.CRCPoly = 7;
+  LL_SPI_Init(SPI1, &SPI_InitStruct);
+  LL_SPI_SetStandard(SPI1, LL_SPI_PROTOCOL_MOTOROLA);
+  LL_SPI_DisableNSSPulseMgt(SPI1);
+  /* USER CODE BEGIN SPI1_Init 2 */
+
+  /* USER CODE END SPI1_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* Init with LL driver */
+  /* DMA controller clock enable */
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1);
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
+
+  /* DMA interrupt init */
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  NVIC_SetPriority(DMA1_Channel1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+  /* DMA1_Channel3_IRQn interrupt configuration */
+  NVIC_SetPriority(DMA1_Channel3_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(DMA1_Channel3_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  This function Activate SPI1
+  * @param  None
+  * @retval None
+  */
+void Activate_SPI(void)
+{
+  /* Enable SPI1 */
+  LL_SPI_Enable(SPI1);
+
+  /* Enable DMA Channels */
+  LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_3);
+  LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
+}
+
+/**
+  * @brief  Turn-on LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_On(void)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_PORT, LED2_PIN);
+}
+
+
+/**
+  * @brief  Turn-off LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_Off(void)
+{
+  /* Turn LED2 off */
+  LL_GPIO_ResetOutputPin(LED2_GPIO_PORT, LED2_PIN);
+}
+
+
+/**
+  * @brief  Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
+  * @param  Period : Period of time (in ms) between each toggling of LED
+  *   This parameter can be user defined values. Pre-defined values used in that example are :
+  *     @arg LED_BLINK_FAST : Fast Blinking
+  *     @arg LED_BLINK_SLOW : Slow Blinking
+  *     @arg LED_BLINK_ERROR : Error specific Blinking
+  * @retval None
+  */
+void LED_Blinking(uint32_t Period)
+{
+  /* Toggle LED2 in an infinite loop */
+  while (1)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_PORT, LED2_PIN);
+    LL_mDelay(Period);
+  }
+}
+
+/**
+  * @brief  Configures User push-button (SW1) in GPIO or EXTI Line Mode.
+  * @param  None
+  * @retval None
+  */
+void UserButton_Init(void)
+{
+  /* Enable the BUTTON Clock */
+  USER_BUTTON_GPIO_CLK_ENABLE();
+
+  /* Configure GPIO for BUTTON */
+  LL_GPIO_SetPinMode(USER_BUTTON_GPIO_PORT, USER_BUTTON_PIN, LL_GPIO_MODE_INPUT);
+  LL_GPIO_SetPinPull(USER_BUTTON_GPIO_PORT, USER_BUTTON_PIN, LL_GPIO_PULL_UP);
+
+  /* Connect External Line to the GPIO*/
+  USER_BUTTON_SYSCFG_SET_EXTI();
+
+  /* Enable a rising trigger External line 0 Interrupt */
+  USER_BUTTON_EXTI_LINE_ENABLE();
+  USER_BUTTON_EXTI_FALLING_TRIG_ENABLE();
+
+  /* Configure NVIC for USER_BUTTON_EXTI_IRQn */
+  NVIC_SetPriority(USER_BUTTON_EXTI_IRQn, 3);
+  NVIC_EnableIRQ(USER_BUTTON_EXTI_IRQn);
+}
+
+/**
+  * @brief  Wait for User push-button (SW1) press to start transfer.
+  * @param  None
+  * @retval None
+  */
+/*  */
+void WaitForUserButtonPress(void)
+{
+  while (ubButtonPress == 0)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_PORT, LED2_PIN);
+    LL_mDelay(LED_BLINK_FAST);
+  }
+  /* Ensure that LED2 is turned Off */
+  LED_Off();
+}
+
+
+/**
+  * @brief  Wait end of transfer and check if received Data are well.
+  * @param  None
+  * @retval None
+  */
+void WaitAndCheckEndOfTransfer(void)
+{
+  /* 1 - Wait end of transmission */
+  while (ubTransmissionComplete != 1)
+  {
+  }
+  /* Disable DMA1 Tx Channel */
+  LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_1);
+  /* 2 - Wait end of reception */
+  while (ubReceptionComplete != 1)
+  {
+  }
+  /* Disable DMA1 Rx Channel */
+  LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_3);
+  /* 3 - Compare Transmit data to receive data */
+  if (Buffercmp8((uint8_t *)aTxBuffer, (uint8_t *)aRxBuffer, ubNbDataToTransmit))
+  {
+    /* Processing Error */
+    LED_Blinking(LED_BLINK_ERROR);
+  }
+  else
+  {
+    /* Turn On Led if data are well received */
+    LED_On();
+  }
+}
+
+/**
+* @brief Compares two 8-bit buffers and returns the comparison result.
+* @param pBuffer1: pointer to the source buffer to be compared to.
+* @param pBuffer2: pointer to the second source buffer to be compared to the first.
+* @param BufferLength: buffer's length.
+* @retval   0: Comparison is OK (the two Buffers are identical)
+*           Value different from 0: Comparison is NOK (Buffers are different)
+*/
+uint8_t Buffercmp8(uint8_t *pBuffer1, uint8_t *pBuffer2, uint8_t BufferLength)
+{
+  while (BufferLength--)
+  {
+    if (*pBuffer1 != *pBuffer2)
+    {
+      return 1;
+    }
+
+    pBuffer1++;
+    pBuffer2++;
+  }
+
+  return 0;
+}
+
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT Functions                                     */
+/******************************************************************************/
+/**
+  * @brief  Function to manage User push-button (SW1)
+  * @param  None
+  * @retval None
+  */
+void UserButton_Callback(void)
+{
+  /* Update User push-button (SW1) variable : to be checked in waiting loop in main program */
+  ubButtonPress = 1;
+}
+
+/**
+  * @brief  Function called from DMA1 IRQ Handler when Rx transfer is completed
+  * @param  None
+  * @retval None
+  */
+void DMA1_ReceiveComplete_Callback(void)
+{
+  /* DMA Rx transfer completed */
+  ubReceptionComplete = 1;
+}
+
+/**
+  * @brief  Function called from DMA1 IRQ Handler when Tx transfer is completed
+  * @param  None
+  * @retval None
+  */
+void DMA1_TransmitComplete_Callback(void)
+{
+  /* DMA Tx transfer completed */
+  ubTransmissionComplete = 1;
+}
+
+/**
+  * @brief  Function called in case of error detected in SPI IT Handler
+  * @param  None
+  * @retval None
+  */
+void SPI1_TransferError_Callback(void)
+{
+  /* Disable DMA1 Rx Channel */
+  LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_3);
+
+  /* Disable DMA1 Tx Channel */
+  LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_1);
+  /* Set LED2 to Blinking mode to indicate error occurs */
+  LED_Blinking(LED_BLINK_ERROR);
+}
+
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..c532baf54
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,263 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles DMA1 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void DMA1_Channel3_IRQHandler(void)
+{
+
+  if (LL_DMA_IsActiveFlag_TC3(DMA1))
+  {
+    LL_DMA_ClearFlag_GI3(DMA1);
+    /* Call function Reception complete Callback */
+    DMA1_ReceiveComplete_Callback();
+  }
+  else if (LL_DMA_IsActiveFlag_TE3(DMA1))
+  {
+    /* Call Error function */
+    SPI1_TransferError_Callback();
+  }
+
+}
+
+/**
+  * @brief  This function handles DMA1 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void DMA1_Channel1_IRQHandler(void)
+{
+  if (LL_DMA_IsActiveFlag_TC1(DMA1))
+  {
+    LL_DMA_ClearFlag_GI1(DMA1);
+    /* Call function Transmission complete Callback */
+    DMA1_TransmitComplete_Callback();
+  }
+  else if (LL_DMA_IsActiveFlag_TE1(DMA1))
+  {
+    /* Call Error function */
+    SPI1_TransferError_Callback();
+  }
+}
+/**
+  * @brief  This function handles external line 0 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void USER_BUTTON_IRQHANDLER(void)
+{
+  /* Manage Flags */
+  if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
+  {
+    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
+
+    /* Handle User push-button (SW1) press in dedicated function */
+    UserButton_Callback();
+  }
+}
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/readme.txt
new file mode 100644
index 000000000..54487b149
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/readme.txt
@@ -0,0 +1,108 @@
+/**
+  @page SPI_TwoBoards_FullDuplex_DMA_Master_Init SPI example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the SPI_TwoBoards_FullDuplex_DMA_Master_Init example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+Data buffer transmission and receptionvia SPI using DMA mode. This example is 
+based on the STM32WBxx SPI LL API. The peripheral initialization uses 
+LL unitary service functions for optimization purposes (performance and size).
+
+The communication is done with 2 boards through SPI.
+   _________________________                        _________________________
+  |       ___________ ______|                      |__________________       |
+  |      |SPI1              |                      |             SPI1 |      |
+  |      |                  |                      |                  |      |
+  |      |         CLK(PA5) |______________________|(PA5)CLK          |      |
+  |      |                  |                      |                  |      |
+  |      |         MISO(PA6)|______________________|(PA6)MISO         |      |
+  |      |                  |                      |                  |      |
+  |      |         MOSI(PA7)|______________________|(PA7)MOSI         |      |
+  |      |                  |                      |                  |      |
+  |      |__________________|                      |__________________|      |
+  |      __                 |                      |                         |
+  |     |__|                |                      |                         |
+  |     USER                |                      |                         |
+  |                      GND|______________________|GND                      |
+  |                         |                      |                         |
+  |_STM32WBxx Master _______|                      |_STM32WBxx Slave ________|
+
+This example shows how to configure GPIO and SPI peripherals
+to use a Full-Duplex communication using DMA Transfer mode through the STM32WBxx SPI LL API.
+
+This example is splitted in two projects, Master board and Slave board:
+
+- Master Board
+  SPI1 Peripheral is configured in Master mode.
+  DMA1_Channel3 and DMA1_Channel1 configured to transfer Data via SPI peripheral
+  GPIO associated to User push-button (SW1) is linked with EXTI. 
+  
+- Slave Board
+  SPI1 Peripheral is configured in Slave mode.
+  DMA1_Channel3 and DMA1_Channel1 configured to transfer Data via SPI peripheral
+
+
+Example execution:
+On BOARD MASTER, LED2 is blinking Fast (200ms) and wait User push-button (SW1) action.
+Press User push-button (SW1) on BOARD MASTER start a Full-Duplex communication through DMA.
+On MASTER side, Clock will be generated on SCK line, Transmission(MOSI Line) and reception (MISO Line) 
+will be done at the same time. 
+SLAVE SPI will received  the Clock (SCK Line), so Transmission(MISO Line) and reception (MOSI Line) will be done also.
+
+LED2 is On on both boards if data is well received.
+
+In case of errors, LED2 is blinking Slowly (1s).
+
+@note You need to perform a reset on Master board, then perform it on Slave board
+      to have the correct behaviour of this example.
+
+
+@par Directory contents 
+
+  - SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Inc/main.h                  Header for main.c module
+  - SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Inc/stm32_assert.h          Template file to include assert_failed function
+  - SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Src/main.c                  Main program
+  - SPI/SPI_TwoBoards_FullDuplex_DMA_Master_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+@par Hardware and Software environment
+
+  - This example runs on NUCLEO-WB35CE devices.
+
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+  - NUCLEO-WB35CE Set-up
+    - Connect Master board PA5 to Slave Board PA5 (connected to pin 11 of CN10 connector)
+    - Connect Master board PA6 to Slave Board PA6 (connected to pin 27 of CN10 connector)
+    - Connect Master board PA7 to Slave Board PA7 (connected to pin 15 of CN10 connector)
+    - Connect Master board GND to Slave Board GND
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+    o Load the Master project in Master Board
+    o Load the Slave project in Slave Board
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/.extSettings
new file mode 100644
index 000000000..d9196e942
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/.extSettings
@@ -0,0 +1,9 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Application/User=../Src/main.c;../Src/stm32wbxx_it.c;
+Doc=../readme.txt;
+Drivers/STM32WBxx_HAL_Driver=../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/Project.eww
new file mode 100644
index 000000000..b4417192b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ewd
new file mode 100644
index 000000000..019ed5351
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		SPI_TwoBoards_FullDuplex_DMA_Slave_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ewp
new file mode 100644
index 000000000..56e48380b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ewp
@@ -0,0 +1,1092 @@
+
+
+  3
+  
+    SPI_TwoBoards_FullDuplex_DMA_Slave_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Inc/main.h
new file mode 100644
index 000000000..b4b3bbaac
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Inc/main.h
@@ -0,0 +1,115 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_spi.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/**
+  * @brief LED2
+  */
+#define LED2_PIN                           LL_GPIO_PIN_0
+#define LED2_GPIO_PORT                     GPIOB
+
+/**
+  * @brief Toggle periods for various blinking modes
+  */
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW  500
+#define LED_BLINK_ERROR 1000
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+void DMA1_ReceiveComplete_Callback(void);
+void DMA1_TransmitComplete_Callback(void);
+void SPI1_TransferError_Callback(void);
+void UserButton_Callback(void);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..4d040a918
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void DMA1_Channel3_IRQHandler(void);
+void DMA1_Channel1_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/MDK-ARM/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/MDK-ARM/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.uvoptx
new file mode 100644
index 000000000..8f7f0f115
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/MDK-ARM/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.uvoptx
@@ -0,0 +1,396 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    SPI_TwoBoards_FullDuplex_DMA_Slave_Init
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          ARMRTXEVENTFLAGS
+          -L70 -Z18 -C0 -M0 -T1
+        
+        
+          0
+          DLGTARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          
+        
+        
+          0
+          DLGUARM
+          (105=-1,-1,-1,-1,0)
+        
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066CFF303337554E43183920 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        
+          0
+          1
+          aRxBuffer
+        
+      
+      
+        0
+      
+      
+        0
+        1
+        1
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      4
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      4
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      stm32wbxx_ll_dma.c
+      0
+      0
+    
+    
+      4
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c
+      stm32wbxx_ll_spi.c
+      0
+      0
+    
+    
+      4
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+    
+      4
+      11
+      1
+      0
+      0
+      0
+      ..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_ll_rcc.c
+      stm32wbxx_ll_rcc.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      5
+      12
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/MDK-ARM/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/MDK-ARM/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.uvprojx
new file mode 100644
index 000000000..dfd89ca7b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/MDK-ARM/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.uvprojx
@@ -0,0 +1,487 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      SPI_TwoBoards_FullDuplex_DMA_Slave_Init
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          SPI_TwoBoards_FullDuplex_DMA_Slave_Init\
+          SPI_TwoBoards_FullDuplex_DMA_Slave_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x40000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000004
+                0x8000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+            
+            
+              stm32wbxx_ll_spi.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+            
+              stm32wbxx_ll_rcc.c
+              1
+              ..\..\..\..\..\..\Drivers\STM32WBxx_HAL_Driver\Src\stm32wbxx_ll_rcc.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ioc
new file mode 100644
index 000000000..4d5c22216
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ioc
@@ -0,0 +1,181 @@
+#MicroXplorer Configuration settings - do not modify
+Dma.Request0=SPI1_TX
+Dma.Request1=SPI1_RX
+Dma.RequestsNb=2
+Dma.SPI1_RX.1.Direction=DMA_PERIPH_TO_MEMORY
+Dma.SPI1_RX.1.EventEnable=DISABLE
+Dma.SPI1_RX.1.Instance=DMA1_Channel1
+Dma.SPI1_RX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.SPI1_RX.1.MemInc=DMA_MINC_ENABLE
+Dma.SPI1_RX.1.Mode=DMA_NORMAL
+Dma.SPI1_RX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.SPI1_RX.1.PeriphInc=DMA_PINC_DISABLE
+Dma.SPI1_RX.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.SPI1_RX.1.Priority=DMA_PRIORITY_LOW
+Dma.SPI1_RX.1.RequestNumber=1
+Dma.SPI1_RX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.SPI1_RX.1.SignalID=HAL_DMAMUX1_REQ_GEN_EXTI4
+Dma.SPI1_RX.1.SyncEnable=DISABLE
+Dma.SPI1_RX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.SPI1_RX.1.SyncRequestNumber=1
+Dma.SPI1_RX.1.SyncSignalID=HAL_DMAMUX1_SYNC_EXTI4
+Dma.SPI1_TX.0.Direction=DMA_MEMORY_TO_PERIPH
+Dma.SPI1_TX.0.EventEnable=DISABLE
+Dma.SPI1_TX.0.Instance=DMA1_Channel3
+Dma.SPI1_TX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.SPI1_TX.0.MemInc=DMA_MINC_ENABLE
+Dma.SPI1_TX.0.Mode=DMA_NORMAL
+Dma.SPI1_TX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.SPI1_TX.0.PeriphInc=DMA_PINC_DISABLE
+Dma.SPI1_TX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.SPI1_TX.0.Priority=DMA_PRIORITY_LOW
+Dma.SPI1_TX.0.RequestNumber=1
+Dma.SPI1_TX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.SPI1_TX.0.SignalID=HAL_DMAMUX1_REQ_GEN_EXTI4
+Dma.SPI1_TX.0.SyncEnable=DISABLE
+Dma.SPI1_TX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.SPI1_TX.0.SyncRequestNumber=1
+Dma.SPI1_TX.0.SyncSignalID=HAL_DMAMUX1_SYNC_EXTI4
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=DMA
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SPI1
+Mcu.IP4=SYS
+Mcu.IPNb=5
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA5
+Mcu.Pin1=PA6
+Mcu.Pin2=PA7
+Mcu.Pin3=PB0
+Mcu.Pin4=VP_SYS_VS_Systick
+Mcu.PinsNb=5
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:false\:false\:false
+NVIC.DMA1_Channel3_IRQn=true\:0\:0\:false\:false\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA5.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA5.GPIO_PuPd=GPIO_PULLDOWN
+PA5.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PA5.Locked=true
+PA5.Mode=Full_Duplex_Slave
+PA5.Signal=SPI1_SCK
+PA6.GPIOParameters=GPIO_Speed
+PA6.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PA6.Mode=Full_Duplex_Slave
+PA6.Signal=SPI1_MISO
+PA7.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA7.GPIO_PuPd=GPIO_PULLDOWN
+PA7.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PA7.Mode=Full_Duplex_Slave
+PA7.Signal=SPI1_MOSI
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=false
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ioc
+ProjectManager.ProjectName=SPI_TwoBoards_FullDuplex_DMA_Slave_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-MX_DMA_Init-DMA-false-LL-true,3-SystemClock_Config-RCC-false-LL-true,4-MX_SPI1_Init-SPI1-false-LL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SPI1.CLKPhase=SPI_PHASE_2EDGE
+SPI1.CLKPolarity=SPI_POLARITY_HIGH
+SPI1.CRCCalculation=SPI_CRCCALCULATION_DISABLE
+SPI1.DataSize=SPI_DATASIZE_8BIT
+SPI1.Direction=SPI_DIRECTION_2LINES
+SPI1.FirstBit=SPI_FIRSTBIT_MSB
+SPI1.IPParameters=TIMode,DataSize,FirstBit,CLKPolarity,CLKPhase,CRCCalculation,NSS,VirtualType,Mode,Direction
+SPI1.Mode=SPI_MODE_SLAVE
+SPI1.NSS=SPI_NSS_SOFT
+SPI1.TIMode=SPI_TIMODE_DISABLE
+SPI1.VirtualType=VM_SLAVE
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..2438c48fb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,188 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..d7fe2066a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/.project
@@ -0,0 +1,90 @@
+
+
+	SPI_TwoBoards_FullDuplex_DMA_Slave_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/SPI_TwoBoards_FullDuplex_DMA_Slave_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_spi.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..eea98ff9c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb35xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB35xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..4ec95844d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,159 @@
+/**
+ ******************************************************************************
+ * @file      syscalls.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..4665417ed
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,58 @@
+/**
+ ******************************************************************************
+ * @file      sysmem.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System Memory calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Src/main.c
new file mode 100644
index 000000000..0a3de9762
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Src/main.c
@@ -0,0 +1,572 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to send/receive bytes over SPI IP using
+  *          the STM32WBxx SPI LL API.
+  *          Peripheral initialization done using LL unitary services functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+__IO uint8_t ubButtonPress = 0;
+
+/* Buffer used for transmission */
+uint8_t aTxBuffer[] = "**** SPI_TwoBoards_FullDuplex_DMA communication **** SPI_TwoBoards_FullDuplex_DMA communication **** SPI_TwoBoards_FullDuplex_DMA communication ****";
+uint8_t ubNbDataToTransmit = sizeof(aTxBuffer);
+__IO uint8_t ubTransmissionComplete = 0;
+
+/* Buffer used for reception */
+uint8_t aRxBuffer[sizeof(aTxBuffer)];
+uint8_t ubNbDataToReceive  = sizeof(aTxBuffer);
+__IO uint8_t ubReceptionComplete = 0;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+static void MX_SPI1_Init(void);
+/* USER CODE BEGIN PFP */
+
+void     SystemClock_Config(void);
+void     Activate_SPI(void);
+void     LED_On(void);
+void     LED_Blinking(uint32_t Period);
+void     WaitAndCheckEndOfTransfer(void);
+uint8_t  Buffercmp8(uint8_t *pBuffer1, uint8_t *pBuffer2, uint8_t BufferLength);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_SPI1_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Configure the DMA1_Channel3 functional parameters */
+  LL_DMA_ConfigTransfer(DMA1,
+                        LL_DMA_CHANNEL_3,
+                        LL_DMA_DIRECTION_MEMORY_TO_PERIPH | LL_DMA_PRIORITY_HIGH | LL_DMA_MODE_NORMAL |
+                        LL_DMA_PERIPH_NOINCREMENT | LL_DMA_MEMORY_INCREMENT |
+                        LL_DMA_PDATAALIGN_BYTE | LL_DMA_MDATAALIGN_BYTE);
+  LL_DMA_ConfigAddresses(DMA1,
+                         LL_DMA_CHANNEL_3,
+                         (uint32_t)aTxBuffer, LL_SPI_DMA_GetRegAddr(SPI1),
+                         LL_DMA_GetDataTransferDirection(DMA1, LL_DMA_CHANNEL_3));
+  LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_3, ubNbDataToReceive);
+
+  LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_3, LL_DMAMUX_REQ_SPI1_TX);
+
+
+  /* Configure the DMA1_Channel1 functional parameters */
+  LL_DMA_ConfigTransfer(DMA1,
+                        LL_DMA_CHANNEL_1,
+                        LL_DMA_DIRECTION_PERIPH_TO_MEMORY | LL_DMA_PRIORITY_HIGH | LL_DMA_MODE_NORMAL |
+                        LL_DMA_PERIPH_NOINCREMENT | LL_DMA_MEMORY_INCREMENT |
+                        LL_DMA_PDATAALIGN_BYTE | LL_DMA_MDATAALIGN_BYTE);
+  LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_1, LL_SPI_DMA_GetRegAddr(SPI1), (uint32_t)aRxBuffer,
+                         LL_DMA_GetDataTransferDirection(DMA1, LL_DMA_CHANNEL_1));
+  LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_1, ubNbDataToTransmit);
+  LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_SPI1_RX);
+
+
+  /* Enable DMA interrupts complete/error */
+  LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_3);
+  LL_DMA_EnableIT_TE(DMA1, LL_DMA_CHANNEL_3);
+  LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_1);
+  LL_DMA_EnableIT_TE(DMA1, LL_DMA_CHANNEL_1);
+
+  /* Initialize FFIFO Threshold */
+  LL_SPI_SetRxFIFOThreshold(SPI1, LL_SPI_RX_FIFO_TH_QUARTER);
+
+  /* Configure SPI1 DMA transfer interrupts */
+  /* Enable DMA TX Interrupt */
+  LL_SPI_EnableDMAReq_TX(SPI1);
+
+  /* Configure SPI1 DMA transfer interrupts */
+  /* Enable DMA RX Interrupt */
+  LL_SPI_EnableDMAReq_RX(SPI1);
+
+  /* Enable the SPI1 peripheral */
+  Activate_SPI();
+
+  /* Wait for the end of the transfer and check received data */
+  /* LED blinking FAST during waiting time */
+  WaitAndCheckEndOfTransfer();
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* MSI configuration and activation */
+  LL_RCC_MSI_Enable();
+  while(LL_RCC_MSI_IsReady() != 1)
+  {
+  };
+
+  /* Main PLL configuration and activation */
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 32, LL_RCC_PLLR_DIV_2);
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the main PLL */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(64000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(64000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief SPI1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SPI1_Init(void)
+{
+
+  /* USER CODE BEGIN SPI1_Init 0 */
+
+  /* USER CODE END SPI1_Init 0 */
+
+  LL_SPI_InitTypeDef SPI_InitStruct = {0};
+
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* Peripheral clock enable */
+  LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1);
+  
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  /**SPI1 GPIO Configuration  
+  PA5   ------> SPI1_SCK
+  PA6   ------> SPI1_MISO
+  PA7   ------> SPI1_MOSI 
+  */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_5|LL_GPIO_PIN_7;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_DOWN;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+  LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_6;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+  LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* SPI1 DMA Init */
+  
+  /* SPI1_TX Init */
+  LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_3, LL_DMAMUX_REQ_SPI1_TX);
+
+  LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_3, LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
+
+  LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PRIORITY_LOW);
+
+  LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MODE_NORMAL);
+
+  LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PERIPH_NOINCREMENT);
+
+  LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MEMORY_INCREMENT);
+
+  LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PDATAALIGN_BYTE);
+
+  LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MDATAALIGN_BYTE);
+
+  /* SPI1_RX Init */
+  LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_SPI1_RX);
+
+  LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_1, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+
+  LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PRIORITY_LOW);
+
+  LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MODE_NORMAL);
+
+  LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PERIPH_NOINCREMENT);
+
+  LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MEMORY_INCREMENT);
+
+  LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PDATAALIGN_BYTE);
+
+  LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MDATAALIGN_BYTE);
+
+  /* USER CODE BEGIN SPI1_Init 1 */
+
+  /* USER CODE END SPI1_Init 1 */
+  /* SPI1 parameter configuration*/
+  SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX;
+  SPI_InitStruct.Mode = LL_SPI_MODE_SLAVE;
+  SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_8BIT;
+  SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH;
+  SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE;
+  SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+  SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+  SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+  SPI_InitStruct.CRCPoly = 7;
+  LL_SPI_Init(SPI1, &SPI_InitStruct);
+  LL_SPI_SetStandard(SPI1, LL_SPI_PROTOCOL_MOTOROLA);
+  LL_SPI_DisableNSSPulseMgt(SPI1);
+  /* USER CODE BEGIN SPI1_Init 2 */
+
+  /* USER CODE END SPI1_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* Init with LL driver */
+  /* DMA controller clock enable */
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1);
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
+
+  /* DMA interrupt init */
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  NVIC_SetPriority(DMA1_Channel1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+  /* DMA1_Channel3_IRQn interrupt configuration */
+  NVIC_SetPriority(DMA1_Channel3_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(DMA1_Channel3_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  This function Activate SPI1
+  * @param  None
+  * @retval None
+  */
+void Activate_SPI(void)
+{
+  /* Enable SPI1 */
+  LL_SPI_Enable(SPI1);
+
+  /* Enable DMA Channels */
+  LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_3);
+  LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
+}
+
+/**
+  * @brief  Turn-on LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_On(void)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_PORT, LED2_PIN);
+}
+
+
+/**
+  * @brief  Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
+  * @param  Period : Period of time (in ms) between each toggling of LED
+  *   This parameter can be user defined values. Pre-defined values used in that example are :
+  *     @arg LED_BLINK_FAST : Fast Blinking
+  *     @arg LED_BLINK_SLOW : Slow Blinking
+  *     @arg LED_BLINK_ERROR : Error specific Blinking
+  * @retval None
+  */
+void LED_Blinking(uint32_t Period)
+{
+  /* Toggle LED2 in an infinite loop */
+  while (1)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_PORT, LED2_PIN);
+    LL_mDelay(Period);
+  }
+}
+
+
+/**
+  * @brief  Wait end of transfer and check if received Data are well.
+  * @param  None
+  * @retval None
+  */
+void WaitAndCheckEndOfTransfer(void)
+{
+  /* 1 - Wait end of transmission */
+  while (ubTransmissionComplete != 1)
+  {
+  }
+  /* Disable DMA1 Tx Channel */
+  LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_1);
+  /* 2 - Wait end of reception */
+  while (ubReceptionComplete != 1)
+  {
+  }
+  /* Disable DMA1 Rx Channel */
+  LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_3);
+  /* 3 - Compare Transmit data to receive data */
+  if (Buffercmp8((uint8_t *)aTxBuffer, (uint8_t *)aRxBuffer, ubNbDataToTransmit))
+  {
+    /* Processing Error */
+    LED_Blinking(LED_BLINK_ERROR);
+  }
+  else
+  {
+    /* Turn On Led if data are well received */
+    LED_On();
+  }
+}
+
+/**
+* @brief Compares two 8-bit buffers and returns the comparison result.
+* @param pBuffer1: pointer to the source buffer to be compared to.
+* @param pBuffer2: pointer to the second source buffer to be compared to the first.
+* @param BufferLength: buffer's length.
+* @retval   0: Comparison is OK (the two Buffers are identical)
+*           Value different from 0: Comparison is NOK (Buffers are different)
+*/
+uint8_t Buffercmp8(uint8_t *pBuffer1, uint8_t *pBuffer2, uint8_t BufferLength)
+{
+  while (BufferLength--)
+  {
+    if (*pBuffer1 != *pBuffer2)
+    {
+      return 1;
+    }
+
+    pBuffer1++;
+    pBuffer2++;
+  }
+
+  return 0;
+}
+
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT Functions                                     */
+/******************************************************************************/
+/**
+  * @brief  Function to manage User push-button (SW1)
+  * @param  None
+  * @retval None
+  */
+void UserButton_Callback(void)
+{
+  /* Update User push-button (SW1) variable : to be checked in waiting loop in main program */
+  ubButtonPress = 1;
+}
+
+/**
+  * @brief  Function called from DMA1 IRQ Handler when Rx transfer is completed
+  * @param  None
+  * @retval None
+  */
+void DMA1_ReceiveComplete_Callback(void)
+{
+  /* DMA Rx transfer completed */
+  ubReceptionComplete = 1;
+}
+
+/**
+  * @brief  Function called from DMA1 IRQ Handler when Tx transfer is completed
+  * @param  None
+  * @retval None
+  */
+void DMA1_TransmitComplete_Callback(void)
+{
+  /* DMA Tx transfer completed */
+  ubTransmissionComplete = 1;
+}
+
+/**
+  * @brief  Function called in case of error detected in SPI IT Handler
+  * @param  None
+  * @retval None
+  */
+void SPI1_TransferError_Callback(void)
+{
+  /* Disable DMA1 Rx Channel */
+  LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_3);
+
+  /* Disable DMA1 Tx Channel */
+  LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_1);
+  /* Set LED2 to Blinking mode to indicate error occurs */
+  LED_Blinking(LED_BLINK_ERROR);
+}
+
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..0e98494f6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,248 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles DMA1 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void DMA1_Channel3_IRQHandler(void)
+{
+
+  if (LL_DMA_IsActiveFlag_TC3(DMA1))
+  {
+    LL_DMA_ClearFlag_GI3(DMA1);
+    /* Call function Reception complete Callback */
+    DMA1_ReceiveComplete_Callback();
+  }
+  else if (LL_DMA_IsActiveFlag_TE3(DMA1))
+  {
+    /* Call Error function */
+    SPI1_TransferError_Callback();
+  }
+
+}
+
+/**
+  * @brief  This function handles DMA1 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void DMA1_Channel1_IRQHandler(void)
+{
+  if (LL_DMA_IsActiveFlag_TC1(DMA1))
+  {
+    LL_DMA_ClearFlag_GI1(DMA1);
+    /* Call function Transmission complete Callback */
+    DMA1_TransmitComplete_Callback();
+  }
+  else if (LL_DMA_IsActiveFlag_TE1(DMA1))
+  {
+    /* Call Error function */
+    SPI1_TransferError_Callback();
+  }
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/readme.txt
new file mode 100644
index 000000000..b6811655f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/readme.txt
@@ -0,0 +1,108 @@
+/**
+  @page SPI_TwoBoards_FullDuplex_DMA_Slave_Init SPI example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the SPI_TwoBoards_FullDuplex_DMA_Slave_Init example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+Data buffer transmission and receptionvia SPI using DMA mode. This example is 
+based on the STM32WBxx SPI LL API. The peripheral initialization uses 
+LL unitary service functions for optimization purposes (performance and size).
+
+The communication is done with 2 boards through SPI.
+   _________________________                        _________________________
+  |       ___________ ______|                      |__________________       |
+  |      |SPI1              |                      |             SPI1 |      |
+  |      |                  |                      |                  |      |
+  |      |         CLK(PA5) |______________________|(PA5)CLK          |      |
+  |      |                  |                      |                  |      |
+  |      |         MISO(PA6)|______________________|(PA6)MISO         |      |
+  |      |                  |                      |                  |      |
+  |      |         MOSI(PA7)|______________________|(PA7)MOSI         |      |
+  |      |                  |                      |                  |      |
+  |      |__________________|                      |__________________|      |
+  |      __                 |                      |                         |
+  |     |__|                |                      |                         |
+  |     USER                |                      |                         |
+  |                      GND|______________________|GND                      |
+  |                         |                      |                         |
+  |_STM32WBxx Master _______|                      |_STM32WBxx Slave ________|
+
+This example shows how to configure GPIO and SPI peripherals
+to use a Full-Duplex communication using DMA Transfer mode through the STM32WBxx SPI LL API.
+
+This example is splitted in two projects, Master board and Slave board:
+
+- Master Board
+  SPI1 Peripheral is configured in Master mode.
+  DMA1_Channel3 and DMA1_Channel1 configured to transfer Data via SPI peripheral
+  GPIO associated to User push-button (SW1) is linked with EXTI. 
+  
+- Slave Board
+  SPI1 Peripheral is configured in Slave mode.
+  DMA1_Channel3 and DMA1_Channel1 configured to transfer Data via SPI peripheral
+
+
+Example execution:
+On BOARD MASTER, LED2 is blinking Fast (200ms) and wait User push-button (SW1) action.
+Press User push-button (SW1) on BOARD MASTER start a Full-Duplex communication through DMA.
+On MASTER side, Clock will be generated on SCK line, Transmission(MOSI Line) and reception (MISO Line) 
+will be done at the same time. 
+SLAVE SPI will received  the Clock (SCK Line), so Transmission(MISO Line) and reception (MOSI Line) will be done also.
+
+LED2 is On on both boards if data is well received.
+
+In case of errors, LED2 is blinking Slowly (1s).
+
+@note You need to perform a reset on Master board, then perform it on Slave board
+      to have the correct behaviour of this example.
+
+
+@par Directory contents 
+
+  - SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Inc/main.h                  Header for main.c module
+  - SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Inc/stm32_assert.h          Template file to include assert_failed function
+  - SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Src/main.c                  Main program
+  - SPI/SPI_TwoBoards_FullDuplex_DMA_Slave_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+@par Hardware and Software environment
+
+  - This example runs on NUCLEO-WB35CE devices.
+
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+  - NUCLEO-WB35CE Set-up
+    - Connect Master board PA5 to Slave Board PA5 (connected to pin 11 of CN10 connector)
+    - Connect Master board PA6 to Slave Board PA6 (connected to pin 27 of CN10 connector)
+    - Connect Master board PA7 to Slave Board PA7 (connected to pin 15 of CN10 connector)
+    - Connect Master board GND to Slave Board GND
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+    o Load the Master project in Master Board
+    o Load the Slave project in Slave Board
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/Project.eww
new file mode 100644
index 000000000..058c547cb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\TIM_TimeBase_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/TIM_TimeBase_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/TIM_TimeBase_Init.ewd
new file mode 100644
index 000000000..e276df4c3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/TIM_TimeBase_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		TIM_TimeBase_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/TIM_TimeBase_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/TIM_TimeBase_Init.ewp
new file mode 100644
index 000000000..3096216e3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/TIM_TimeBase_Init.ewp
@@ -0,0 +1,1089 @@
+
+
+  3
+  
+    TIM_TimeBase_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Inc/main.h
new file mode 100644
index 000000000..0d6f31d45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Inc/main.h
@@ -0,0 +1,102 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/TIM/TIM_TimeBase_Init/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_tim.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+/* IRQ Handler treatment.*/
+void UserButton_Callback(void);
+
+/* TIM1 update interrupt processing */
+void TimerUpdate_Callback(void);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..05ac25632
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,73 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/TIM/TIM_TimeBase_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void EXTI0_IRQHandler(void);
+void TIM1_BRK_IRQHandler(void);
+void TIM1_UP_TIM16_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/MDK-ARM/TIM_TimeBase_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/MDK-ARM/TIM_TimeBase_Init.uvoptx
new file mode 100644
index 000000000..b4c7062b5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/MDK-ARM/TIM_TimeBase_Init.uvoptx
@@ -0,0 +1,357 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    TIM_TimeBase_Init
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      4
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      4
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+    
+      4
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c
+      stm32wbxx_ll_tim.c
+      0
+      0
+    
+    
+      4
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      stm32wbxx_ll_dma.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/MDK-ARM/TIM_TimeBase_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/MDK-ARM/TIM_TimeBase_Init.uvprojx
new file mode 100644
index 000000000..2815a44c8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/MDK-ARM/TIM_TimeBase_Init.uvprojx
@@ -0,0 +1,481 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      TIM_TimeBase_Init
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          TIM_TimeBase_Init\
+          TIM_TimeBase_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4101
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          "" ()
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+            
+              stm32wbxx_ll_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c
+            
+            
+              stm32wbxx_ll_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..3c2ce8621
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..8e645d7be
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/.project
@@ -0,0 +1,90 @@
+
+
+	TIM_TimeBase_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			TIM_TimeBase_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/TIM_TimeBase_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Src/main.c
new file mode 100644
index 000000000..9dc96fb48
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Src/main.c
@@ -0,0 +1,351 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/TIM/TIM_TimeBase_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to use a timer instance to generate a 
+  *          time base using the STM32WBxx TIM LL API.
+  *          Peripheral initialization done using LL unitary services functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* Number of time base frequencies */
+#define TIM_BASE_FREQ_NB 10
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+static uint32_t tim_prescaler = 0;
+static uint32_t tim_period = 0;
+static uint32_t TimOutClock = 1;
+
+/* Actual autoreload value multiplication factor */
+static uint8_t AutoreloadMult = 1;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_TIM1_Init(void);
+/* USER CODE BEGIN PFP */
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* Set the pre-scaler value to have TIM1 counter clock equal to 10 kHz      */
+  /*
+   In this example TIM1 input clock TIM1CLK is set to APB2 clock (PCLK2),   
+   since APB2 pre-scaler is equal to 1.
+      TIM1CLK = PCLK2
+      PCLK2 = HCLK
+      => TIM1CLK = SystemCoreClock (64 MHz)
+  */
+  tim_prescaler = __LL_TIM_CALC_PSC(SystemCoreClock, 10000);
+
+  /* TIM1CLK = SystemCoreClock / (APB prescaler & multiplier)              */
+  TimOutClock = SystemCoreClock/1;
+  tim_period = __LL_TIM_CALC_ARR(TimOutClock, tim_prescaler, 10);
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_TIM1_Init();
+  /* USER CODE BEGIN 2 */
+  /* Clear the update flag */
+  LL_TIM_ClearFlag_UPDATE(TIM1);
+
+  /* Enable the update interrupt */
+  LL_TIM_EnableIT_UPDATE(TIM1);
+
+  /* Enable counter */
+  LL_TIM_EnableCounter(TIM1);
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* MSI configuration and activation */
+  LL_RCC_MSI_Enable();
+  while(LL_RCC_MSI_IsReady() != 1)
+  {
+  };
+
+  /* Main PLL configuration and activation */
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 32, LL_RCC_PLLR_DIV_2);
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the main PLL */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(64000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(64000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief TIM1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM1_Init(void)
+{
+
+  /* USER CODE BEGIN TIM1_Init 0 */
+
+  /* USER CODE END TIM1_Init 0 */
+
+  LL_TIM_InitTypeDef TIM_InitStruct = {0};
+
+  /* Peripheral clock enable */
+  LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1);
+
+  /* TIM1 interrupt Init */
+  NVIC_SetPriority(TIM1_BRK_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(TIM1_BRK_IRQn);
+  NVIC_SetPriority(TIM1_UP_TIM16_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);
+
+  /* USER CODE BEGIN TIM1_Init 1 */
+
+  /* USER CODE END TIM1_Init 1 */
+  TIM_InitStruct.Prescaler = tim_prescaler;
+  TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
+  TIM_InitStruct.Autoreload = tim_period;
+  TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
+  TIM_InitStruct.RepetitionCounter = 0;
+  LL_TIM_Init(TIM1, &TIM_InitStruct);
+  LL_TIM_SetClockSource(TIM1, LL_TIM_CLOCKSOURCE_INTERNAL);
+  LL_TIM_SetTriggerOutput(TIM1, LL_TIM_TRGO_RESET);
+  LL_TIM_SetTriggerOutput2(TIM1, LL_TIM_TRGO2_RESET);
+  LL_TIM_DisableMasterSlaveMode(TIM1);
+  /* USER CODE BEGIN TIM1_Init 2 */
+
+  /* USER CODE END TIM1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_EXTI_InitTypeDef EXTI_InitStruct = {0};
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTA, LL_SYSCFG_EXTI_LINE0);
+
+  /**/
+  EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_0;
+  EXTI_InitStruct.Line_32_63 = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct.LineCommand = ENABLE;
+  EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;
+  EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_FALLING;
+  LL_EXTI_Init(&EXTI_InitStruct);
+
+  /**/
+  LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_0, LL_GPIO_PULL_UP);
+
+  /**/
+  LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_0, LL_GPIO_MODE_INPUT);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+  /* EXTI interrupt init*/
+  NVIC_SetPriority(EXTI0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),3, 0));
+  NVIC_EnableIRQ(EXTI0_IRQn);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT                                               */
+/******************************************************************************/
+/**
+  * @brief  Update the timer update event period
+  * @param  None
+  * @retval None
+  */
+void UserButton_Callback(void)
+{
+  /* Change the update event period by modifying the autoreload value.        */
+  /* In up-counting update event is generated at each counter overflow (when  */
+  /* the counter reaches the auto-reload value).                              */
+  /* Update event period is calculated as follows:                            */
+  /*   Update_event = TIM1CLK /((PSC + 1)*(ARR + 1)*(RCR + 1))                */
+  /*   where TIM1CLK is 64 MHz                                                */
+  AutoreloadMult = AutoreloadMult % TIM_BASE_FREQ_NB;
+  LL_TIM_SetAutoReload(TIM1, tim_period * (AutoreloadMult +1));
+
+  /* Force update generation */
+  LL_TIM_GenerateEvent_UPDATE(TIM1);
+
+  AutoreloadMult++;
+}
+
+/**
+  * @brief  Timer update interrupt processing
+  * @param  None
+  * @retval None
+  */
+void TimerUpdate_Callback(void)
+{
+  LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);  
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* Infinite loop */
+  while (1)
+  {
+  }
+
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..04f27a17c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,265 @@
+/* USER CODE BEGIN Header */
+/** 
+  ******************************************************************************
+  * @file    Examples_LL/TIM/TIM_TimeBase_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles EXTI line0 interrupt.
+  */
+void EXTI0_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI0_IRQn 0 */
+
+  /* USER CODE END EXTI0_IRQn 0 */
+  if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
+  {
+    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
+    /* USER CODE BEGIN LL_EXTI_LINE_0 */
+
+    /* User button interrupt processing(function defined in main.c) */
+    UserButton_Callback();
+
+    /* USER CODE END LL_EXTI_LINE_0 */
+  }
+  /* USER CODE BEGIN EXTI0_IRQn 1 */
+
+  /* USER CODE END EXTI0_IRQn 1 */
+}
+
+/**
+  * @brief This function handles TIM1 break interrupt.
+  */
+void TIM1_BRK_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM1_BRK_IRQn 0 */
+
+  /* USER CODE END TIM1_BRK_IRQn 0 */
+  /* USER CODE BEGIN TIM1_BRK_IRQn 1 */
+
+  /* USER CODE END TIM1_BRK_IRQn 1 */
+}
+
+/**
+  * @brief This function handles TIM1 update interrupt and TIM16 global interrupt.
+  */
+void TIM1_UP_TIM16_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 0 */
+  /* Check whether update interrupt is pending */
+  if(LL_TIM_IsActiveFlag_UPDATE(TIM1) == 1)
+  {
+    /* Clear the update interrupt flag */
+    LL_TIM_ClearFlag_UPDATE(TIM1);
+  }
+  
+  /* TIM1 update interrupt processing */
+  TimerUpdate_Callback();
+  /* USER CODE END TIM1_UP_TIM16_IRQn 0 */
+  
+  /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 1 */
+
+  /* USER CODE END TIM1_UP_TIM16_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/TIM_TimeBase_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/TIM_TimeBase_Init.ioc
new file mode 100644
index 000000000..aab9887bf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/TIM_TimeBase_Init.ioc
@@ -0,0 +1,137 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=TIM1
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA0
+Mcu.Pin1=PB0
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.Pin3=VP_TIM1_VS_ClockSourceINT
+Mcu.PinsNb=4
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.EXTI0_IRQn=true\:3\:0\:true\:false\:true\:true\:true
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.TIM1_BRK_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.TIM1_UP_TIM16_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA0.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultEXTI
+PA0.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
+PA0.GPIO_PuPd=GPIO_PULLUP
+PA0.Locked=true
+PA0.Signal=GPXTI0
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=false
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=TIM_TimeBase_Init.ioc
+ProjectManager.ProjectName=TIM_TimeBase_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false,3-MX_TIM1_Init-TIM1-false-LL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SH.GPXTI0.0=GPIO_EXTI0
+SH.GPXTI0.ConfNb=1
+TIM1.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_DISABLE
+TIM1.ClockDivision=TIM_CLOCKDIVISION_DIV1
+TIM1.CounterMode=TIM_COUNTERMODE_UP
+TIM1.IPParameters=Prescaler,CounterMode,Period,ClockDivision,RepetitionCounter,AutoReloadPreload,TIM_MasterSlaveMode,TIM_MasterOutputTrigger,TIM_MasterOutputTrigger2
+TIM1.IPParametersWithoutCheck=Prescaler,Period
+TIM1.Period=tim_period
+TIM1.Prescaler=tim_prescaler
+TIM1.RepetitionCounter=0
+TIM1.TIM_MasterOutputTrigger=TIM_TRGO_RESET
+TIM1.TIM_MasterOutputTrigger2=TIM_TRGO2_RESET
+TIM1.TIM_MasterSlaveMode=TIM_MASTERSLAVEMODE_DISABLE
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+VP_TIM1_VS_ClockSourceINT.Mode=Internal
+VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/readme.txt
new file mode 100644
index 000000000..392b48bdd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/TIM/TIM_TimeBase_Init/readme.txt
@@ -0,0 +1,81 @@
+/**
+  @page TIM_TimeBase_Init TIM example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/TIM/TIM_TimeBase_Init/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the TIM_TimeBase_Init example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+Configuration of the TIM peripheral to generate a timebase. This 
+example is based on the STM32WBxx TIM LL API. The peripheral initialization 
+uses LL unitary service functions for optimization purposes (performance and size). 
+
+   In this example TIM1 input clock TIM1CLK is set to APB2 clock (PCLK2),   
+   since APB2 pre-scaler is equal to 1.
+      TIM1CLK = PCLK2
+      PCLK2 = HCLK
+      => TIM1CLK = SystemCoreClock (64 MHz)
+
+To set the TIM1 counter clock frequency to 10 KHz, the pre-scaler (PSC) is calculated as follows:
+PSC = (TIM1CLK / TIM1 counter clock) - 1
+PSC = (SystemCoreClock /10 KHz) - 1
+
+SystemCoreClock is set to 64 MHz for STM32WBxx Devices.
+
+The auto-reload (ARR) is calculated to get a timebase period of 100ms,
+meaning that initial timebase frequency is 10 Hz.
+ARR = (TIM1 counter clock / timebase frequency) - 1
+ARR = (TIM1 counter clock / 10) - 1
+
+Update interrupts are enabled. Within the update interrupt service routine, pin PB0
+(connected to LED2 on board NUCLEO-WB35CE) is toggled. So the period of
+blinking of LED2 = 2 * timebase period.
+
+User push-button (SW1) can be used to modify the timebase period from 100 ms
+to 1 s in 100 ms steps. To do so, every time User push-button (SW1) is pressed, the
+autoreload register (ARR) is updated. In up-counting update event is generated 
+at each counter overflow (when the counter reaches the auto-reload value). 
+
+Finally the timebase frequency is calculated as follows:
+timebase frequency = TIM1 counter clock /((PSC + 1)*(ARR + 1)*(RCR + 1))
+
+@par Directory contents 
+
+  - TIM/TIM_TimeBase_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - TIM/TIM_TimeBase_Init/Inc/main.h                  Header for main.c module
+  - TIM/TIM_TimeBase_Init/Inc/stm32_assert.h          Template file to include assert_failed function
+  - TIM/TIM_TimeBase_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - TIM/TIM_TimeBase_Init/Src/main.c                  Main program
+  - TIM/TIM_TimeBase_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/Project.eww
new file mode 100644
index 000000000..2e94c38a7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\USART_Communication_Rx_IT_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/USART_Communication_Rx_IT_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/USART_Communication_Rx_IT_Init.ewd
new file mode 100644
index 000000000..942344bfb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/USART_Communication_Rx_IT_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		USART_Communication_Rx_IT_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/USART_Communication_Rx_IT_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/USART_Communication_Rx_IT_Init.ewp
new file mode 100644
index 000000000..ae56429a8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/USART_Communication_Rx_IT_Init.ewp
@@ -0,0 +1,1092 @@
+
+
+  3
+  
+    USART_Communication_Rx_IT_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usart.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Inc/main.h
new file mode 100644
index 000000000..e1fa07e4f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Inc/main.h
@@ -0,0 +1,109 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/USART/USART_Communication_Rx_IT_Init/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_usart.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+void UserButton_Callback(void);
+void USART_CharReception_Callback(void);
+void Error_Callback(void);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/**
+  * @brief Toggle periods for various blinking modes
+  */
+
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW  500
+#define LED_BLINK_ERROR 1000
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..f3bb459e5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/USART/USART_Communication_Rx_IT_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void EXTI0_IRQHandler(void);
+void USART1_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/MDK-ARM/USART_Communication_Rx_IT_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/MDK-ARM/USART_Communication_Rx_IT_Init.uvoptx
new file mode 100644
index 000000000..01fc5d2c1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/MDK-ARM/USART_Communication_Rx_IT_Init.uvoptx
@@ -0,0 +1,369 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    USART_Communication_Rx_IT_Init
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usart.c
+      stm32wbxx_ll_usart.c
+      0
+      0
+    
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+      stm32wbxx_ll_rcc.c
+      0
+      0
+    
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      stm32wbxx_ll_dma.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/MDK-ARM/USART_Communication_Rx_IT_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/MDK-ARM/USART_Communication_Rx_IT_Init.uvprojx
new file mode 100644
index 000000000..9c901e40a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/MDK-ARM/USART_Communication_Rx_IT_Init.uvprojx
@@ -0,0 +1,486 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      USART_Communication_Rx_IT_Init
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          USART_Communication_Rx_IT_Init\
+          USART_Communication_Rx_IT_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+            
+              stm32wbxx_ll_usart.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usart.c
+            
+            
+              stm32wbxx_ll_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+            
+            
+              stm32wbxx_ll_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..a957ce5f6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..f8c840011
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/.project
@@ -0,0 +1,95 @@
+
+
+	USART_Communication_Rx_IT_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			USART_Communication_Rx_IT_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/USART_Communication_Rx_IT_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_usart.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usart.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Src/main.c
new file mode 100644
index 000000000..559ea640d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Src/main.c
@@ -0,0 +1,439 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/USART/USART_Communication_Rx_IT_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to send bytes over USART IP using
+  *          the STM32WBxx USART LL API.
+  *          Peripheral initialization done using LL initialization function.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_USART1_UART_Init(void);
+/* USER CODE BEGIN PFP */
+void     LED_On(void);
+void     LED_Off(void);
+void     LED_Blinking(uint32_t Period);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_USART1_UART_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Polling USART initialisation */
+  while ((!(LL_USART_IsActiveFlag_TEACK(USART1))) || (!(LL_USART_IsActiveFlag_REACK(USART1))))
+  {
+  }
+
+  /* Enable RXNE and Error interrupts */
+  LL_USART_EnableIT_RXNE(USART1);
+  LL_USART_EnableIT_ERROR(USART1);
+
+  /* Set LED2 Off */
+  LED_Off();
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* MSI configuration and activation */
+  LL_RCC_MSI_Enable();
+  while(LL_RCC_MSI_IsReady() != 1)
+  {
+  };
+
+  /* Main PLL configuration and activation */
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 32, LL_RCC_PLLR_DIV_2);
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the main PLL */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(64000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(64000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  LL_USART_InitTypeDef USART_InitStruct = {0};
+
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* Peripheral clock enable */
+  LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1);
+  
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+  /**USART1 GPIO Configuration  
+  PB6   ------> USART1_TX
+  PB7   ------> USART1_RX 
+  */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_6|LL_GPIO_PIN_7;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_7;
+  LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* USART1 interrupt Init */
+  NVIC_SetPriority(USART1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(USART1_IRQn);
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  USART_InitStruct.PrescalerValue = LL_USART_PRESCALER_DIV1;
+  USART_InitStruct.BaudRate = 115200;
+  USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B;
+  USART_InitStruct.StopBits = LL_USART_STOPBITS_1;
+  USART_InitStruct.Parity = LL_USART_PARITY_NONE;
+  USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;
+  USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+  USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;
+  LL_USART_Init(USART1, &USART_InitStruct);
+  LL_USART_SetTXFIFOThreshold(USART1, LL_USART_FIFOTHRESHOLD_1_8);
+  LL_USART_SetRXFIFOThreshold(USART1, LL_USART_FIFOTHRESHOLD_1_8);
+  LL_USART_DisableFIFO(USART1);
+  LL_USART_ConfigAsyncMode(USART1);
+
+  /* USER CODE BEGIN WKUPType USART1 */
+
+  /* USER CODE END WKUPType USART1 */
+
+  LL_USART_Enable(USART1);
+
+  /* Polling USART1 initialisation */
+  while((!(LL_USART_IsActiveFlag_TEACK(USART1))) || (!(LL_USART_IsActiveFlag_REACK(USART1))))
+  {
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_EXTI_InitTypeDef EXTI_InitStruct = {0};
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTA, LL_SYSCFG_EXTI_LINE0);
+
+  /**/
+  EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_0;
+  EXTI_InitStruct.Line_32_63 = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct.LineCommand = ENABLE;
+  EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;
+  EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_RISING;
+  LL_EXTI_Init(&EXTI_InitStruct);
+
+  /**/
+  LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_0, LL_GPIO_PULL_NO);
+
+  /**/
+  LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_0, LL_GPIO_MODE_INPUT);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+  /* EXTI interrupt init*/
+  NVIC_SetPriority(EXTI0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),15, 0));
+  NVIC_EnableIRQ(EXTI0_IRQn);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  Turn-on LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_On(void)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Turn-off LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_Off(void)
+{
+  /* Turn LED2 off */
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
+  * @param  Period : Period of time (in ms) between each toggling of LED
+  *   This parameter can be user defined values. Pre-defined values used in that example are :
+  *     @arg LED_BLINK_FAST : Fast Blinking
+  *     @arg LED_BLINK_SLOW : Slow Blinking
+  *     @arg LED_BLINK_ERROR : Error specific Blinking
+  * @retval None
+  */
+void LED_Blinking(uint32_t Period)
+{
+  /* Toggle LED2 in an infinite loop */
+  while (1)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+    LL_mDelay(Period);
+  }
+}
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT Functions                                     */
+/******************************************************************************/
+/**
+  * @brief  Function to manage User push-button (SW1)
+  * @param  None
+  * @retval None
+  */
+void UserButton_Callback(void)
+{
+  /* Turn LED2 Off on User button press (allow to restart sequence) */
+  LED_Off();
+}
+
+/**
+  * @brief  Function called from USART IRQ Handler when RXNE flag is set
+  *         Function is in charge of reading character received on USART RX line.
+  * @param  None
+  * @retval None
+  */
+void USART_CharReception_Callback(void)
+{
+  __IO uint32_t received_char;
+
+  /* Read Received character. RXNE flag is cleared by reading of RDR register */
+  received_char = LL_USART_ReceiveData8(USART1);
+
+  /* Check if received value is corresponding to specific one : S or s */
+  if ((received_char == 'S') || (received_char == 's'))
+  {
+    /* Turn LED2 On : Expected character has been received */
+    LED_On();
+  }
+
+  /* Echo received character on TX */
+  LL_USART_TransmitData8(USART1, received_char);
+}
+
+/**
+  * @brief  Function called in case of error detected in USART IT Handler
+  * @param  None
+  * @retval None
+  */
+void Error_Callback(void)
+{
+  __IO uint32_t isr_reg;
+
+  /* Disable USARTx_IRQn */
+  NVIC_DisableIRQ(USART1_IRQn);
+
+  /* Error handling example :
+    - Read USART ISR register to identify flag that leads to IT raising
+    - Perform corresponding error handling treatment according to flag
+  */
+  isr_reg = LL_USART_ReadReg(USART1, ISR);
+  if (isr_reg & LL_USART_ISR_NE)
+  {
+    /* case Noise Error flag is raised : ... */
+    LED_Blinking(LED_BLINK_FAST);
+  }
+  else
+  {
+    /* Unexpected IT source : Set LED to Blinking mode to indicate error occurs */
+    LED_Blinking(LED_BLINK_ERROR);
+  }
+}
+
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..24f2bbc1e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,252 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/USART/USART_Communication_Rx_IT_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles EXTI line0 interrupt.
+  */
+void EXTI0_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI0_IRQn 0 */
+
+  /* USER CODE END EXTI0_IRQn 0 */
+  if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
+  {
+    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
+    /* USER CODE BEGIN LL_EXTI_LINE_0 */
+    
+    /* USER CODE END LL_EXTI_LINE_0 */
+  }
+  /* USER CODE BEGIN EXTI0_IRQn 1 */
+
+
+  /* USER CODE END EXTI0_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+  /* Check RXNE flag value in ISR register */
+  if (LL_USART_IsActiveFlag_RXNE(USART1) && LL_USART_IsEnabledIT_RXNE(USART1))
+  {
+    /* RXNE flag will be cleared by reading of RDR register (done in call) */
+    /* Call function in charge of handling Character reception */
+    USART_CharReception_Callback();
+  }
+  else
+  {
+    /* Call Error function */
+    Error_Callback();
+  }
+  /* USER CODE END USART1_IRQn 0 */
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/USART_Communication_Rx_IT_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/USART_Communication_Rx_IT_Init.ioc
new file mode 100644
index 000000000..329794645
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/USART_Communication_Rx_IT_Init.ioc
@@ -0,0 +1,153 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=USART1
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA0
+Mcu.Pin1=PB0
+Mcu.Pin2=PB6
+Mcu.Pin3=PB7
+Mcu.Pin4=VP_SYS_VS_Systick
+Mcu.PinsNb=5
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.EXTI0_IRQn=true\:15\:0\:true\:false\:true\:true\:true
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA0.Locked=true
+PA0.Signal=GPXTI0
+PB0.GPIOParameters=GPIO_PuPd,GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.GPIO_PuPd=GPIO_NOPULL
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PB6.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PB6.GPIO_PuPd=GPIO_PULLUP
+PB6.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PB6.Mode=Asynchronous
+PB6.Signal=USART1_TX
+PB7.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PB7.GPIO_PuPd=GPIO_PULLUP
+PB7.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PB7.Mode=Asynchronous
+PB7.Signal=USART1_RX
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=USART_Communication_Rx_IT_Init.ioc
+ProjectManager.ProjectName=USART_Communication_Rx_IT_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false,3-MX_USART1_UART_Init-USART1-false-LL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SH.GPXTI0.0=GPIO_EXTI0
+SH.GPXTI0.ConfNb=1
+USART1.AutoBaudRateEnableParam=UART_ADVFEATURE_AUTOBAUDRATE_DISABLE
+USART1.BaudRate=115200
+USART1.ClockPrescaler=PRESCALER_DIV1
+USART1.DMADisableonRxErrorParam=ADVFEATURE_DMA_ENABLEONRXERROR
+USART1.DataInvertParam=ADVFEATURE_DATAINV_DISABLE
+USART1.FIFOMode=FIFOMODE_DISABLE
+USART1.IPParameters=BaudRate,WordLength,Parity,StopBits,Mode,OverSampling,OneBitSampling,ClockPrescaler,FIFOMode,TXFIFOThreshold,RXFIFOThreshold,AutoBaudRateEnableParam,TxPinLevelInvertParam,RxPinLevelInvertParam,DataInvertParam,SwapParam,OverrunDisableParam,DMADisableonRxErrorParam,MSBFirstParam,VirtualMode-Asynchronous
+USART1.MSBFirstParam=ADVFEATURE_MSBFIRST_DISABLE
+USART1.Mode=MODE_TX_RX
+USART1.OneBitSampling=UART_ONE_BIT_SAMPLE_DISABLE
+USART1.OverSampling=UART_OVERSAMPLING_16
+USART1.OverrunDisableParam=ADVFEATURE_OVERRUN_ENABLE
+USART1.Parity=PARITY_NONE
+USART1.RXFIFOThreshold=RXFIFO_THRESHOLD_1EIGHTHFULL
+USART1.RxPinLevelInvertParam=ADVFEATURE_RXINV_DISABLE
+USART1.StopBits=STOPBITS_1
+USART1.SwapParam=ADVFEATURE_SWAP_DISABLE
+USART1.TXFIFOThreshold=TXFIFO_THRESHOLD_1EIGHTHFULL
+USART1.TxPinLevelInvertParam=ADVFEATURE_TXINV_DISABLE
+USART1.VirtualMode-Asynchronous=VM_ASYNC
+USART1.WordLength=WORDLENGTH_8B
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/readme.txt
new file mode 100644
index 000000000..3a24fa95e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Rx_IT_Init/readme.txt
@@ -0,0 +1,78 @@
+/**
+  @page USART_Communication_Rx_IT_Init USART Receiver example (IT Mode)
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/USART/USART_Communication_Rx_IT_Init/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the USART_Communication_Rx_IT_Init example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+This example shows how to configure GPIO and USART peripheral for receiving characters
+from HyperTerminal (PC) in Asynchronous mode using Interrupt mode. Peripheral initialization is done
+using LL initialization function to demonstrate LL init usage.
+
+USART Peripheral is configured in asynchronous mode (115200 bauds, 8 data bit, 1 start bit, 1 stop bit, no parity).
+No HW flow control is used.
+GPIO associated to User push-button is linked with EXTI. 
+USART RX Not Empty interrupt is enabled.
+
+Example execution:
+When character is received on USART Rx line, a RXNE interrupt occurs. 
+USART IRQ Handler routine is then checking received character value. 
+On a specific value ('S' or 's'), LED2 is turned On. 
+Received character is echoed on Tx line.
+On press on push button, LED2 is turned Off.
+In case of errors, LED2 is blinking.
+
+@par Directory contents 
+
+  - USART/USART_Communication_Rx_IT_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - USART/USART_Communication_Rx_IT_Init/Inc/main.h                  Header for main.c module
+  - USART/USART_Communication_Rx_IT_Init/Inc/stm32_assert.h          Template file to include assert_failed function
+  - USART/USART_Communication_Rx_IT_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - USART/USART_Communication_Rx_IT_Init/Src/main.c                  Main program
+  - USART/USART_Communication_Rx_IT_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+  - NUCLEO-WB35CE Set-up
+    Connect USART1 TX/RX to respectively RX and TX pins of PC UART (could be done through a USB to UART adapter) :
+    - Connect STM32 MCU board USART1 TX pin (GPIO PB.06 (Pin 35 in CN10))
+      to PC COM port RX signal
+    - Connect STM32 MCU board USART1 RX pin (GPIO PB.07 (Pin 37 in CN10))
+      to PC COM port TX signal
+    - Connect STM32 MCU board GND to PC COM port GND signal
+
+  - Launch serial communication SW on PC (as HyperTerminal or TeraTerm) with proper configuration 
+    (115200 bauds, 8 bits data, 1 stop bit, no parity, no HW flow control).
+
+  - Launch the program. Enter characters on PC communication SW side.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/Project.eww
new file mode 100644
index 000000000..c9e9bac15
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\USART_Communication_Tx_IT_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/USART_Communication_Tx_IT_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/USART_Communication_Tx_IT_Init.ewd
new file mode 100644
index 000000000..779d368fd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/USART_Communication_Tx_IT_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		USART_Communication_Tx_IT_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/USART_Communication_Tx_IT_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/USART_Communication_Tx_IT_Init.ewp
new file mode 100644
index 000000000..4ae0eb4a6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/USART_Communication_Tx_IT_Init.ewp
@@ -0,0 +1,1092 @@
+
+
+  3
+  
+    USART_Communication_Tx_IT_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usart.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Inc/main.h
new file mode 100644
index 000000000..73be7d763
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Inc/main.h
@@ -0,0 +1,113 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/USART/USART_Communication_Tx_IT_Init/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_usart.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+void UserButton_Callback(void);
+void USART_TXEmpty_Callback(void);
+void USART_CharTransmitComplete_Callback(void);
+void Error_Callback(void);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* Define used to enable time-out management*/
+#define USE_TIMEOUT       0
+
+/**
+  * @brief Toggle periods for various blinking modes
+  */
+
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW  500
+#define LED_BLINK_ERROR 1000
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..124f49c05
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/USART/USART_Communication_Tx_IT_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void EXTI0_IRQHandler(void);
+void USART1_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/MDK-ARM/USART_Communication_Tx_IT_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/MDK-ARM/USART_Communication_Tx_IT_Init.uvoptx
new file mode 100644
index 000000000..16931d963
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/MDK-ARM/USART_Communication_Tx_IT_Init.uvoptx
@@ -0,0 +1,369 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    USART_Communication_Tx_IT_Init
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usart.c
+      stm32wbxx_ll_usart.c
+      0
+      0
+    
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+      stm32wbxx_ll_rcc.c
+      0
+      0
+    
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+      stm32wbxx_ll_dma.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/MDK-ARM/USART_Communication_Tx_IT_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/MDK-ARM/USART_Communication_Tx_IT_Init.uvprojx
new file mode 100644
index 000000000..6f5dcf5d6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/MDK-ARM/USART_Communication_Tx_IT_Init.uvprojx
@@ -0,0 +1,486 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      USART_Communication_Tx_IT_Init
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          USART_Communication_Tx_IT_Init\
+          USART_Communication_Tx_IT_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+            
+              stm32wbxx_ll_usart.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usart.c
+            
+            
+              stm32wbxx_ll_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+            
+            
+              stm32wbxx_ll_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..106b31b32
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..49ae77e2f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/.project
@@ -0,0 +1,95 @@
+
+
+	USART_Communication_Tx_IT_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			USART_Communication_Tx_IT_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/USART_Communication_Tx_IT_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_usart.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usart.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Src/main.c
new file mode 100644
index 000000000..b83477925
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Src/main.c
@@ -0,0 +1,466 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/USART/USART_Communication_Tx_IT_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to send bytes over USART IP using
+  *          the STM32WBxx USART LL API.
+  *          Peripheral initialization done using LL unitary services functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+__IO uint8_t ubButtonPress = 0;
+__IO uint8_t ubSend = 0;
+const uint8_t aStringToSend[] = "STM32WBxx USART LL API Example : TX in IT mode\r\nConfiguration UART 115200 bps, 8 data bit/1 stop bit/No parity/No HW flow control\r\n";
+uint8_t ubSizeToSend = sizeof(aStringToSend);
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_USART1_UART_Init(void);
+/* USER CODE BEGIN PFP */
+void     LED_On(void);
+void     LED_Off(void);
+void     LED_Blinking(uint32_t Period);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_USART1_UART_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Polling USART initialisation */
+  while ((!(LL_USART_IsActiveFlag_TEACK(USART1))) || (!(LL_USART_IsActiveFlag_REACK(USART1))))
+  {
+  }
+
+  /* Enable RXNE and Error interrupts */
+  LL_USART_EnableIT_RXNE(USART1);
+  LL_USART_EnableIT_ERROR(USART1);
+
+  /* Set LED2 Off */
+  LED_Off();
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* MSI configuration and activation */
+  LL_RCC_MSI_Enable();
+  while(LL_RCC_MSI_IsReady() != 1)
+  {
+  };
+
+  /* Main PLL configuration and activation */
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 32, LL_RCC_PLLR_DIV_2);
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the main PLL */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(64000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(64000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  LL_USART_InitTypeDef USART_InitStruct = {0};
+
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* Peripheral clock enable */
+  LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1);
+  
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  /**USART1 GPIO Configuration  
+  PA9   ------> USART1_TX
+  PA10   ------> USART1_RX 
+  */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_9|LL_GPIO_PIN_10;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_7;
+  LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USART1 interrupt Init */
+  NVIC_SetPriority(USART1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(USART1_IRQn);
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  USART_InitStruct.PrescalerValue = LL_USART_PRESCALER_DIV1;
+  USART_InitStruct.BaudRate = 115200;
+  USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B;
+  USART_InitStruct.StopBits = LL_USART_STOPBITS_1;
+  USART_InitStruct.Parity = LL_USART_PARITY_NONE;
+  USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;
+  USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+  USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;
+  LL_USART_Init(USART1, &USART_InitStruct);
+  LL_USART_SetTXFIFOThreshold(USART1, LL_USART_FIFOTHRESHOLD_1_8);
+  LL_USART_SetRXFIFOThreshold(USART1, LL_USART_FIFOTHRESHOLD_1_8);
+  LL_USART_DisableFIFO(USART1);
+  LL_USART_ConfigAsyncMode(USART1);
+
+  /* USER CODE BEGIN WKUPType USART1 */
+
+  /* USER CODE END WKUPType USART1 */
+
+  LL_USART_Enable(USART1);
+
+  /* Polling USART1 initialisation */
+  while((!(LL_USART_IsActiveFlag_TEACK(USART1))) || (!(LL_USART_IsActiveFlag_REACK(USART1))))
+  {
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_EXTI_InitTypeDef EXTI_InitStruct = {0};
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTA, LL_SYSCFG_EXTI_LINE0);
+
+  /**/
+  EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_0;
+  EXTI_InitStruct.Line_32_63 = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct.LineCommand = ENABLE;
+  EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;
+  EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_FALLING;
+  LL_EXTI_Init(&EXTI_InitStruct);
+
+  /**/
+  LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_0, LL_GPIO_PULL_UP);
+
+  /**/
+  LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_0, LL_GPIO_MODE_INPUT);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+  /* EXTI interrupt init*/
+  NVIC_SetPriority(EXTI0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(EXTI0_IRQn);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  Turn-on LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_On(void)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Turn-off LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_Off(void)
+{
+  /* Turn LED2 off */
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+/**
+  * @brief  Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
+  * @param  Period : Period of time (in ms) between each toggling of LED
+  *   This parameter can be user defined values. Pre-defined values used in that example are :
+  *     @arg LED_BLINK_FAST : Fast Blinking
+  *     @arg LED_BLINK_SLOW : Slow Blinking
+  *     @arg LED_BLINK_ERROR : Error specific Blinking
+  * @retval None
+  */
+void LED_Blinking(uint32_t Period)
+{
+  /* Toggle LED2 in an infinite loop */
+  while (1)
+  {
+    LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+    LL_mDelay(Period);
+  }
+}
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT Functions                                     */
+/******************************************************************************/
+/**
+  * @brief  Function to manage User push-button (SW1)
+  * @param  None
+  * @retval None
+  */
+void UserButton_Callback(void)
+{
+  /* Start transfer only if not already ongoing */
+  if (ubSend == 0)
+  {
+    /* Start USART transmission : Will initiate TXE interrupt after TDR register is empty */
+    LL_USART_TransmitData8(USART1, aStringToSend[ubSend++]);
+
+    /* Enable TXE interrupt */
+    LL_USART_EnableIT_TXE(USART1);
+  }
+}
+
+/**
+  * @brief  Function called for achieving next TX Byte sending
+  * @param  None
+  * @retval None
+  */
+void USART_TXEmpty_Callback(void)
+{
+  if (ubSend == (ubSizeToSend - 1))
+  {
+    /* Disable TXE interrupt */
+    LL_USART_DisableIT_TXE(USART1);
+
+    /* Enable TC interrupt */
+    LL_USART_EnableIT_TC(USART1);
+  }
+
+  /* Fill TDR with a new char */
+  LL_USART_TransmitData8(USART1, aStringToSend[ubSend++]);
+}
+
+/**
+  * @brief  Function called at completion of last byte transmission
+  * @param  None
+  * @retval None
+  */
+void USART_CharTransmitComplete_Callback(void)
+{
+  if (ubSend == sizeof(aStringToSend))
+  {
+    ubSend = 0;
+
+    /* Disable TC interrupt */
+    LL_USART_DisableIT_TC(USART1);
+
+    /* Turn LED2 On at end of transfer : Tx sequence completed successfully */
+    LED_On();
+  }
+}
+
+/**
+  * @brief  Function called in case of error detected in USART IT Handler
+  * @param  None
+  * @retval None
+  */
+void Error_Callback(void)
+{
+  __IO uint32_t isr_reg;
+
+  /* Disable USARTx_IRQn */
+  NVIC_DisableIRQ(USART1_IRQn);
+
+  /* Error handling example :
+    - Read USART ISR register to identify flag that leads to IT raising
+    - Perform corresponding error handling treatment according to flag
+  */
+  isr_reg = LL_USART_ReadReg(USART1, ISR);
+  if (isr_reg & LL_USART_ISR_NE)
+  {
+    /* case Noise Error flag is raised : ... */
+    LED_Blinking(LED_BLINK_FAST);
+  }
+  else
+  {
+    /* Unexpected IT source : Set LED to Blinking mode to indicate error occurs */
+    LED_Blinking(LED_BLINK_ERROR);
+  }
+}
+
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..815e9954e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,264 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/USART/USART_Communication_Tx_IT_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles EXTI line0 interrupt.
+  */
+void EXTI0_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI0_IRQn 0 */
+
+  /* USER CODE END EXTI0_IRQn 0 */
+  if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
+  {
+    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
+    /* USER CODE BEGIN LL_EXTI_LINE_0 */
+
+    /* Handle user button press in dedicated function */
+    UserButton_Callback();
+    /* USER CODE END LL_EXTI_LINE_0 */
+  }
+  /* USER CODE BEGIN EXTI0_IRQn 1 */
+
+
+  /* USER CODE END EXTI0_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+  if (LL_USART_IsEnabledIT_TXE(USART1) && LL_USART_IsActiveFlag_TXE(USART1))
+  {
+    /* TXE flag will be automatically cleared when writing new data in TDR register */
+
+    /* Call function in charge of handling empty DR => will lead to transmission of next character */
+    USART_TXEmpty_Callback();
+  }
+
+  if (LL_USART_IsEnabledIT_TC(USART1) && LL_USART_IsActiveFlag_TC(USART1))
+  {
+    /* Clear TC flag */
+    LL_USART_ClearFlag_TC(USART1);
+    /* Call function in charge of handling end of transmission of sent character
+       and prepare next charcater transmission */
+    USART_CharTransmitComplete_Callback();
+  }
+
+  if (LL_USART_IsEnabledIT_ERROR(USART1) && LL_USART_IsActiveFlag_NE(USART1))
+  {
+    /* Call Error function */
+    Error_Callback();
+  }
+  /* USER CODE END USART1_IRQn 0 */
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/USART_Communication_Tx_IT_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/USART_Communication_Tx_IT_Init.ioc
new file mode 100644
index 000000000..3ba7e3817
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/USART_Communication_Tx_IT_Init.ioc
@@ -0,0 +1,158 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=USART1
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA0
+Mcu.Pin1=PA9
+Mcu.Pin2=PB0
+Mcu.Pin3=PA10
+Mcu.Pin4=VP_SYS_VS_Systick
+Mcu.PinsNb=5
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.EXTI0_IRQn=true\:0\:0\:true\:false\:true\:true\:true
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA0.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultEXTI
+PA0.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
+PA0.GPIO_PuPd=GPIO_PULLUP
+PA0.Locked=true
+PA0.Signal=GPXTI0
+PA10.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA10.GPIO_PuPd=GPIO_PULLUP
+PA10.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PA10.Locked=true
+PA10.Mode=Asynchronous
+PA10.Signal=USART1_RX
+PA9.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA9.GPIO_PuPd=GPIO_PULLUP
+PA9.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PA9.Locked=true
+PA9.Mode=Asynchronous
+PA9.Signal=USART1_TX
+PB0.GPIOParameters=GPIO_PuPd,GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.GPIO_PuPd=GPIO_NOPULL
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=USART_Communication_Tx_IT_Init.ioc
+ProjectManager.ProjectName=USART_Communication_Tx_IT_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false,3-MX_USART1_UART_Init-USART1-false-LL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SH.GPXTI0.0=GPIO_EXTI0
+SH.GPXTI0.ConfNb=1
+USART1.AutoBaudRateEnableParam=UART_ADVFEATURE_AUTOBAUDRATE_DISABLE
+USART1.BaudRate=115200
+USART1.ClockPrescaler=PRESCALER_DIV1
+USART1.DMADisableonRxErrorParam=ADVFEATURE_DMA_ENABLEONRXERROR
+USART1.DataInvertParam=ADVFEATURE_DATAINV_DISABLE
+USART1.FIFOMode=FIFOMODE_DISABLE
+USART1.IPParameters=BaudRate,WordLength,Parity,StopBits,Mode,OverSampling,OneBitSampling,ClockPrescaler,FIFOMode,TXFIFOThreshold,RXFIFOThreshold,AutoBaudRateEnableParam,TxPinLevelInvertParam,RxPinLevelInvertParam,DataInvertParam,SwapParam,OverrunDisableParam,DMADisableonRxErrorParam,MSBFirstParam,VirtualMode-Asynchronous
+USART1.MSBFirstParam=ADVFEATURE_MSBFIRST_DISABLE
+USART1.Mode=MODE_TX_RX
+USART1.OneBitSampling=UART_ONE_BIT_SAMPLE_DISABLE
+USART1.OverSampling=UART_OVERSAMPLING_16
+USART1.OverrunDisableParam=ADVFEATURE_OVERRUN_ENABLE
+USART1.Parity=PARITY_NONE
+USART1.RXFIFOThreshold=RXFIFO_THRESHOLD_1EIGHTHFULL
+USART1.RxPinLevelInvertParam=ADVFEATURE_RXINV_DISABLE
+USART1.StopBits=STOPBITS_1
+USART1.SwapParam=ADVFEATURE_SWAP_DISABLE
+USART1.TXFIFOThreshold=TXFIFO_THRESHOLD_1EIGHTHFULL
+USART1.TxPinLevelInvertParam=ADVFEATURE_TXINV_DISABLE
+USART1.VirtualMode-Asynchronous=VM_ASYNC
+USART1.WordLength=WORDLENGTH_8B
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/readme.txt
new file mode 100644
index 000000000..868a56a90
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/USART/USART_Communication_Tx_IT_Init/readme.txt
@@ -0,0 +1,83 @@
+/**
+  @page USART_Communication_Tx_IT_Init USART Transmitter example (IT mode)
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/USART/USART_Communication_Tx_IT_Init/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the USART_Communication_Tx_IT_Init example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+This example shows how to configure GPIO and USART peripheral to send characters
+asynchronously to HyperTerminal (PC) in Interrupt mode. This example is based on
+STM32WBxx USART LL API. Peripheral initialization is done using LL unitary services
+functions for optimization purpose (performance and size).
+
+USART Peripheral is configured in asynchronous mode (115200 bauds, 8 data bit, 1 start bit, 1 stop bit, no parity).
+No HW flow control is used.
+GPIO associated to User push-button is linked with EXTI. 
+Virtual Com port feature of STLINK could be used for UART communication between board and PC.
+
+Example execution:
+On press on push button , USART TX Empty interrupt is enabled.
+First character of buffer to be transmitted is written into USART Transmit Data Register (TDR) in order to initialise transfer procedure.
+When character is sent from TDR, a TXE interrupt occurs. 
+USART IRQ Handler routine is sending next character on USART Tx line. 
+IT will be raised until last byte is to be transmitted : Then, Transmit Complete (TC) interrupt is enabled 
+instead of TX Empty (TXE). 
+On last byte transmission complete, LED2 is turned on.
+In case of errors, LED2 is blinking (1sec period).
+
+Program is written so that, any new press on User push-button will lead to new transmission of complete buffer.
+
+@par Directory contents 
+
+  - USART/USART_Communication_Tx_IT_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - USART/USART_Communication_Tx_IT_Init/Inc/main.h                  Header for main.c module
+  - USART/USART_Communication_Tx_IT_Init/Inc/stm32_assert.h          Template file to include assert_failed function
+  - USART/USART_Communication_Tx_IT_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - USART/USART_Communication_Tx_IT_Init/Src/main.c                  Main program
+  - USART/USART_Communication_Tx_IT_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+  - NUCLEO-WB35CE Set-up
+    Connect USART1 TX/RX to respectively RX and TX pins of PC UART (could be done through a USB to UART adapter) :
+    - Connect STM32 MCU board USART1 TX pin (GPIO PA.09 connected to pin 30 in CN7)
+      to PC COM port RX signal
+    - Connect STM32 MCU board USART1 RX pin (GPIO PA.10 connected to pin 31 in CN10)
+      to PC COM port TX signal
+    - Connect STM32 MCU board GND to PC COM port GND signal
+
+  - Launch serial communication SW on PC (as HyperTerminal or TeraTerm) with proper configuration 
+    (115200 bauds, 8 bits data, 1 stop bit, no parity, no HW flow control).
+
+  - Launch the program. Press on User push button on board to initiate data transfer.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/Project.eww
new file mode 100644
index 000000000..cf9d8eaa9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\UTILS_ReadDeviceInfo.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/UTILS_ReadDeviceInfo.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/UTILS_ReadDeviceInfo.ewd
new file mode 100644
index 000000000..1dc07ea2b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/UTILS_ReadDeviceInfo.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		UTILS_ReadDeviceInfo
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/UTILS_ReadDeviceInfo.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/UTILS_ReadDeviceInfo.ewp
new file mode 100644
index 000000000..6e7a64f08
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/UTILS_ReadDeviceInfo.ewp
@@ -0,0 +1,1083 @@
+
+
+  3
+  
+    UTILS_ReadDeviceInfo
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Inc/main.h
new file mode 100644
index 000000000..a3c7b1574
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Inc/main.h
@@ -0,0 +1,97 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/UTILS/UTILS_ReadDeviceInfo/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "stm32wbxx_ll_utils.h"
+#include 
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..30768fe74
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/UTILS/UTILS_ReadDeviceInfo/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/MDK-ARM/UTILS_ReadDeviceInfo.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/MDK-ARM/UTILS_ReadDeviceInfo.uvoptx
new file mode 100644
index 000000000..7bb97a0c9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/MDK-ARM/UTILS_ReadDeviceInfo.uvoptx
@@ -0,0 +1,333 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    UTILS_ReadDeviceInfo
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/MDK-ARM/UTILS_ReadDeviceInfo.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/MDK-ARM/UTILS_ReadDeviceInfo.uvprojx
new file mode 100644
index 000000000..e941a97fb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/MDK-ARM/UTILS_ReadDeviceInfo.uvprojx
@@ -0,0 +1,471 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      UTILS_ReadDeviceInfo
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          UTILS_ReadDeviceInfo\
+          UTILS_ReadDeviceInfo
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..3dbf8b336
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/.project
new file mode 100644
index 000000000..d885e44e0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/.project
@@ -0,0 +1,80 @@
+
+
+	UTILS_ReadDeviceInfo
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			UTILS_ReadDeviceInfo.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/UTILS_ReadDeviceInfo.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Src/main.c
new file mode 100644
index 000000000..668e406cc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Src/main.c
@@ -0,0 +1,228 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/UTILS/UTILS_ReadDeviceInfo/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to read UID, Device ID and Revision ID
+  *          through the STM32WBxx UTILS LL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* Buffer used for displaying different UTILS info */
+uint8_t aShowDeviceID[30]    = {0};
+uint8_t aShowRevisionID[30]  = {0};
+uint8_t aShowCoordinate[40]  = {0};
+uint8_t aShowWaferNumber[30] = {0};
+uint8_t aShowLotNumber[30]   = {0};
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+void     GetMCUInfo(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+  /* Get different information available in the MCU */
+  GetMCUInfo();
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* MSI configuration and activation */
+  LL_RCC_MSI_Enable();
+  while(LL_RCC_MSI_IsReady() != 1)
+  {
+  };
+
+  /* Main PLL configuration and activation */
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 32, LL_RCC_PLLR_DIV_2);
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the main PLL */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(64000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(64000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  Get different information available in the MCU (Device ID, Revision ID & UID)
+  * @param  None
+  * @retval None
+  */
+void GetMCUInfo(void)
+{
+  register uint32_t size_string = 0, read_info = 0, read_info2 = 0;
+
+  /* Display Device ID in string format */
+  sprintf((char *)aShowDeviceID, "Device ID = 0x%lX", LL_DBGMCU_GetDeviceID());
+
+  /* Display Revision ID in string format */
+  sprintf((char *)aShowRevisionID, "Revision ID = 0x%lX", LL_DBGMCU_GetRevisionID());
+
+  /* Display  X and Y coordinates on the wafer expressed in BCD format */
+  sprintf((char *)aShowCoordinate, "X and Y coordinates = 0x%lX", LL_GetUID_Word0());
+
+  /* Display Waver number and lot number in string format */
+  read_info = LL_GetUID_Word1();
+  read_info2 = LL_GetUID_Word2();
+  sprintf((char *)aShowWaferNumber, "Wafer NB = 0x%X", (uint8_t)read_info);
+  size_string = sprintf((char *)aShowLotNumber, "Lot NB = 0x%lX", read_info2);
+  sprintf((char *)aShowLotNumber + size_string, "%lX", (read_info >> 8));
+}
+
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..bb52e3cb8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Src/stm32wbxx_it.c
@@ -0,0 +1,207 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/UTILS/UTILS_ReadDeviceInfo/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides temp1late for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/UTILS_ReadDeviceInfo.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/UTILS_ReadDeviceInfo.ioc
new file mode 100644
index 000000000..529e97730
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/UTILS_ReadDeviceInfo.ioc
@@ -0,0 +1,106 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=3
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=UTILS_ReadDeviceInfo.ioc
+ProjectManager.ProjectName=UTILS_ReadDeviceInfo
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-LL-false
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/readme.txt
new file mode 100644
index 000000000..d076cbb23
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/UTILS/UTILS_ReadDeviceInfo/readme.txt
@@ -0,0 +1,60 @@
+/**
+  @page UTILS_ReadDeviceInfo UTILS example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/UTILS/UTILS_ReadDeviceInfo/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the UTILS example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+This example reads the UID, Device ID and Revision ID and saves 
+them into a global information buffer.
+
+Then UID, Device ID and Revision ID will be saved in following global variables:
+- aShowDeviceID: Device identifier
+- aShowRevisionID: Revision identifier (This field indicates the revision of the device. 
+  For example, it is read as 0x1000 for Revision 1.0)
+- aShowCoordinate: X and Y coordinates on the wafer expressed in BCD format
+- aShowWaferNumber: WAF_NUM[7:0], Wafer number (8-bit unsigned number)
+- aShowLotNumber: LOT_NUM[55:0], Lot number (ASCII encoded)
+
+@par Directory contents 
+
+  - UTILS/UTILS_ReadDeviceInfo/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - UTILS/UTILS_ReadDeviceInfo/Inc/main.h                  Header for main.c module
+  - UTILS/UTILS_ReadDeviceInfo/Inc/stm32_assert.h          Template file to include assert_failed function  
+  - UTILS/UTILS_ReadDeviceInfo/Src/stm32wbxx_it.c          Interrupt handlers
+  - UTILS/UTILS_ReadDeviceInfo/Src/main.c                  Main program
+  - UTILS/UTILS_ReadDeviceInfo/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/.extSettings b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/Project.eww
new file mode 100644
index 000000000..a7f93219c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\WWDG_RefreshUntilUserEvent_Init.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/WWDG_RefreshUntilUserEvent_Init.ewd b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/WWDG_RefreshUntilUserEvent_Init.ewd
new file mode 100644
index 000000000..2c33cdec9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/WWDG_RefreshUntilUserEvent_Init.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		WWDG_RefreshUntilUserEvent_Init
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/WWDG_RefreshUntilUserEvent_Init.ewp b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/WWDG_RefreshUntilUserEvent_Init.ewp
new file mode 100644
index 000000000..ba7e1c557
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/WWDG_RefreshUntilUserEvent_Init.ewp
@@ -0,0 +1,1083 @@
+
+
+  3
+  
+    WWDG_RefreshUntilUserEvent_Init
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Inc/main.h
new file mode 100644
index 000000000..91071b5fd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Inc/main.h
@@ -0,0 +1,111 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_wwdg.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED2_Pin LL_GPIO_PIN_0
+#define LED2_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/**
+  * @brief Toggle periods for various blinking modes
+  */
+
+#define LED_BLINK_FAST  200
+#define LED_BLINK_SLOW  500
+#define LED_BLINK_ERROR 1000
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..26dd02265
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Inc/stm32wbxx_it.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void EXTI0_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+void UserButton_Callback(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/MDK-ARM/WWDG_RefreshUntilUserEvent_Init.uvoptx b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/MDK-ARM/WWDG_RefreshUntilUserEvent_Init.uvoptx
new file mode 100644
index 000000000..188694c91
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/MDK-ARM/WWDG_RefreshUntilUserEvent_Init.uvoptx
@@ -0,0 +1,333 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    WWDG_RefreshUntilUserEvent_Init
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      5
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/MDK-ARM/WWDG_RefreshUntilUserEvent_Init.uvprojx b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/MDK-ARM/WWDG_RefreshUntilUserEvent_Init.uvprojx
new file mode 100644
index 000000000..b31448977
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/MDK-ARM/WWDG_RefreshUntilUserEvent_Init.uvprojx
@@ -0,0 +1,471 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      WWDG_RefreshUntilUserEvent_Init
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          WWDG_RefreshUntilUserEvent_Init\
+          WWDG_RefreshUntilUserEvent_Init
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..27fb7b660
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/.project
new file mode 100644
index 000000000..a6fa7cdae
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/.project
@@ -0,0 +1,80 @@
+
+
+	WWDG_RefreshUntilUserEvent_Init
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			WWDG_RefreshUntilUserEvent_Init.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/WWDG_RefreshUntilUserEvent_Init.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Src/main.c
new file mode 100644
index 000000000..5497cad8f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Src/main.c
@@ -0,0 +1,346 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to configure WWDG down-counter (with Window)
+  *          using the STM32WBxx WWDG LL API.
+  *          Peripheral initialization done using LL unitary services functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+static __IO uint8_t KeyPressed = 0;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_WWDG_Init(void);
+/* USER CODE BEGIN PFP */
+void     UserButton_Callback(void);
+void     Check_WWDG_Reset(void);
+void     LED_On(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+ 
+  /* Check if the system has resumed from WWDG reset*/
+  Check_WWDG_Reset();
+  
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_WWDG_Init();
+  /* USER CODE BEGIN 2 */
+ 
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    if (1 != KeyPressed)
+    {
+      /* Refresh WWDG Downcounter to initial value ~2s*/
+      LL_WWDG_SetCounter(WWDG, 0X7E);
+      
+      LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
+      LL_mDelay(LED_BLINK_FAST);
+    }
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
+
+  /* MSI configuration and activation */
+  LL_RCC_MSI_Enable();
+  while(LL_RCC_MSI_IsReady() != 1)
+  {
+  };
+
+  /* Main PLL configuration and activation */
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 32, LL_RCC_PLLR_DIV_2);
+  LL_RCC_PLL_Enable();
+  LL_RCC_PLL_EnableDomain_SYS();
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the main PLL */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(64000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(64000000);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief WWDG Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_WWDG_Init(void)
+{
+
+  /* USER CODE BEGIN WWDG_Init 0 */
+
+  /* USER CODE END WWDG_Init 0 */
+
+  /* Peripheral clock enable */
+  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG);
+
+  /* USER CODE BEGIN WWDG_Init 1 */
+
+  /* Configure WWDG */
+
+  /* Refresh WWDG before activate it */
+  /* Activate WWDG */
+  /* set prescaler to have a rollover each about ~2s */
+  /* set window value to same value (~2s) as downcounter in order to ba able to refresh the WWDG almost immediately */
+
+  /* USER CODE END WWDG_Init 1 */
+  LL_WWDG_SetCounter(WWDG, 126);
+  LL_WWDG_Enable(WWDG);
+  LL_WWDG_SetPrescaler(WWDG, LL_WWDG_PRESCALER_64);
+  LL_WWDG_SetWindow(WWDG, 126);
+  /* USER CODE BEGIN WWDG_Init 2 */
+
+  /* USER CODE END WWDG_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  LL_EXTI_InitTypeDef EXTI_InitStruct = {0};
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
+
+  /**/
+  LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTA, LL_SYSCFG_EXTI_LINE0);
+
+  /**/
+  EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_0;
+  EXTI_InitStruct.Line_32_63 = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct.LineCommand = ENABLE;
+  EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;
+  EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_FALLING;
+  LL_EXTI_Init(&EXTI_InitStruct);
+
+  /**/
+  LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_0, LL_GPIO_PULL_UP);
+
+  /**/
+  LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_0, LL_GPIO_MODE_INPUT);
+
+  /**/
+  GPIO_InitStruct.Pin = LED2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
+
+  /* EXTI interrupt init*/
+  NVIC_SetPriority(EXTI0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(EXTI0_IRQn);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  This function check if the system has resumed from WWDG reset
+  * @param  None
+  * @retval None
+  */
+void Check_WWDG_Reset(void)
+{
+  if (LL_RCC_IsActiveFlag_WWDGRST())
+  {
+    /* clear WWDG reset flag */
+    LL_RCC_ClearResetFlags();
+    
+    /* Re-Initialize GPIO configured peripheral */
+    MX_GPIO_Init();
+
+    /* turn Led on and wait for user event to perform example again */
+    LED_On();
+    
+    while(KeyPressed != 1)
+    {
+    }
+
+    /* Reset KeyPressed value */
+    KeyPressed = 0;
+  }
+}
+
+
+/**
+  * @brief  Turn-on LED2.
+  * @param  None
+  * @retval None
+  */
+void LED_On(void)
+{
+  /* Turn LED2 on */
+  LL_GPIO_SetOutputPin(LED2_GPIO_Port, LED2_Pin);
+}
+
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT                                               */
+/******************************************************************************/
+/**
+  * @brief  Function to manage IRQ Handler
+  * @param  None
+  * @retval None
+  */
+void UserButton_Callback(void)
+{
+  KeyPressed = 1;
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..0f2ccb97d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Src/stm32wbxx_it.c
@@ -0,0 +1,230 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles EXTI line0 interrupt.
+  */
+void EXTI0_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI0_IRQn 0 */
+
+  /* USER CODE END EXTI0_IRQn 0 */
+  if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
+  {
+    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
+    /* USER CODE BEGIN LL_EXTI_LINE_0 */
+    
+    /* Manage code in main.c.*/
+    UserButton_Callback(); 
+    
+    /* USER CODE END LL_EXTI_LINE_0 */
+  }
+  /* USER CODE BEGIN EXTI0_IRQn 1 */
+
+  /* USER CODE END EXTI0_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/WWDG_RefreshUntilUserEvent_Init.ioc b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/WWDG_RefreshUntilUserEvent_Init.ioc
new file mode 100644
index 000000000..d403ada4d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/WWDG_RefreshUntilUserEvent_Init.ioc
@@ -0,0 +1,130 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=WWDG
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA0
+Mcu.Pin1=PB0
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.Pin3=VP_WWDG_VS_WWDG
+Mcu.PinsNb=4
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.EXTI0_IRQn=true\:0\:0\:true\:false\:true\:true\:true
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA0.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultEXTI
+PA0.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
+PA0.GPIO_PuPd=GPIO_PULLUP
+PA0.Locked=true
+PA0.Signal=GPXTI0
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LED2
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=3
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=WWDG_RefreshUntilUserEvent_Init.ioc
+ProjectManager.ProjectName=WWDG_RefreshUntilUserEvent_Init
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-true,3-MX_WWDG_Init-WWDG-false-LL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SH.GPXTI0.0=GPIO_EXTI0
+SH.GPXTI0.ConfNb=1
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+VP_WWDG_VS_WWDG.Mode=WWDG_Activate
+VP_WWDG_VS_WWDG.Signal=WWDG_VS_WWDG
+WWDG.Counter=126
+WWDG.EWIMode=WWDG_EWI_DISABLE
+WWDG.IPParameters=Prescaler,Window,Counter,EWIMode
+WWDG.Prescaler=WWDG_PRESCALER_64
+WWDG.Window=126
+board=custom
+boardIOC=true
diff --git a/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/readme.txt b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/readme.txt
new file mode 100644
index 000000000..a4d5340e6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/readme.txt
@@ -0,0 +1,62 @@
+/**
+  @page WWDG_RefreshUntilUserEvent_Init WWDG example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_LL/WWDG/WWDG_RefreshUntilUserEvent_Init/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the WWDG_RefreshUntilUserEvent_Init example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+Configuration of the WWDG to periodically update the counter and 
+generate an MCU WWDG reset when a user button is pressed. The peripheral initialization 
+uses the LL unitary service functions for optimization purposes (performance and size).
+
+Example Configuration:
+Configure the WWDG (Window, Prescaler & Counter) and enable it.
+Refresh the WWDG downcounter in the main loop - LED2 is blinking fastly & continuously
+
+Example Execution:
+When User push-button (SW1) is pressed, the Downcounter automatic refresh mechanism is disable and thus, reset will occur.
+After a reset when re-entering in the main, RCC WWDG Reset Flag will be checked and if we are back from a WWDG reset the LED2 will be switch ON.
+
+Waiting a new User push-button (SW1) pressed to re-activate the WWDG
+
+@par Directory contents 
+
+  - WWDG/WWDG_RefreshUntilUserEvent_Init/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - WWDG/WWDG_RefreshUntilUserEvent_Init/Inc/main.h                  Header for main.c module
+  - WWDG/WWDG_RefreshUntilUserEvent_Init/Inc/stm32_assert.h          Template file to include assert_failed function
+  - WWDG/WWDG_RefreshUntilUserEvent_Init/Src/stm32wbxx_it.c          Interrupt handlers
+  - WWDG/WWDG_RefreshUntilUserEvent_Init/Src/main.c                  Main program
+  - WWDG/WWDG_RefreshUntilUserEvent_Init/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/.extSettings b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/.extSettings
new file mode 100644
index 000000000..15b551b33
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=CORTEX;RCC;FLASH;GPIO;ADC;DMA;TIM;PWR
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/ADC_SingleConversion_TriggerSW_IT.ioc b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/ADC_SingleConversion_TriggerSW_IT.ioc
new file mode 100644
index 000000000..c45ff646b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/ADC_SingleConversion_TriggerSW_IT.ioc
@@ -0,0 +1,116 @@
+#MicroXplorer Configuration settings - do not modify
+ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_9
+ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,master
+ADC1.NbrOfConversionFlag=1
+ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
+ADC1.Rank-0\#ChannelRegularConversion=1
+ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5
+ADC1.master=1
+File.Version=6
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=ADC1
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA4
+Mcu.Pin1=VP_SYS_VS_Systick
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA4.Signal=ADCx_IN9
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=3
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=ADC_SingleConversion_TriggerSW_IT.ioc
+ProjectManager.ProjectName=ADC_SingleConversion_TriggerSW_IT
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_ADC1_Init-ADC1-false-HAL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SH.ADCx_IN9.0=ADC1_IN9,IN9-Single-Ended
+SH.ADCx_IN9.ConfNb=1
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/ADC_SingleConversion_TriggerSW_IT.ewd b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/ADC_SingleConversion_TriggerSW_IT.ewd
new file mode 100644
index 000000000..9a6d86fb3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/ADC_SingleConversion_TriggerSW_IT.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		ADC_SingleConversion_TriggerSW_IT
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/ADC_SingleConversion_TriggerSW_IT.ewp b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/ADC_SingleConversion_TriggerSW_IT.ewp
new file mode 100644
index 000000000..94b03db53
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/ADC_SingleConversion_TriggerSW_IT.ewp
@@ -0,0 +1,1128 @@
+
+
+  3
+  
+    ADC_SingleConversion_TriggerSW_IT
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/Project.eww
new file mode 100644
index 000000000..8d249907a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\ADC_SingleConversion_TriggerSW_IT.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/main.h
new file mode 100644
index 000000000..37699e44a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/main.h
@@ -0,0 +1,107 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "stm32wbxx_ll_adc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+
+
+/* User can use this section to tailor ADCx instance under use and associated
+   resources */
+
+/* ## Definition of ADC related resources ################################### */
+/* Definition of ADCx clock resources */
+#define ADCx                            ADC1
+#define ADCx_CLK_ENABLE()               __HAL_RCC_ADC_CLK_ENABLE()
+
+#define ADCx_FORCE_RESET()              __HAL_RCC_ADC_FORCE_RESET()
+#define ADCx_RELEASE_RESET()            __HAL_RCC_ADC_RELEASE_RESET()
+
+/* Definition of ADCx channels */
+#define ADCx_CHANNELa                   ADC_CHANNEL_9
+
+/* Definition of ADCx NVIC resources */
+#define ADCx_IRQn                       ADC1_IRQn
+#define ADCx_IRQHandler                 ADC1_IRQHandler
+
+/* Definition of ADCx channels pins */
+#define ADCx_CHANNELa_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
+#define ADCx_CHANNELa_GPIO_PORT         GPIOA
+#define ADCx_CHANNELa_PIN               GPIO_PIN_4
+
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* IRQ Handler treatment */
+void AdcGrpRegularUnitaryConvComplete_Callback(void);
+void AdcGrpRegularOverrunError_Callback(void);
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..f107476b0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+#define HAL_ADC_MODULE_ENABLED
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..d13bd80ca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_it.h
@@ -0,0 +1,79 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+void EXTI0_IRQHandler(void);
+
+/* Note: Lines of code commented below correspond to the example using        */
+/*       HAL driver only.                                                     */
+/*       This example demonstrating a mix of HAL and LL drivers has replaced  */
+/*       these lines using LL driver.                                         */
+// void ADCx_IRQHandler(void);
+
+void ADC1_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/ADC_SingleConversion_TriggerSW_IT.uvoptx b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/ADC_SingleConversion_TriggerSW_IT.uvoptx
new file mode 100644
index 000000000..a786e6209
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/ADC_SingleConversion_TriggerSW_IT.uvoptx
@@ -0,0 +1,533 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    ADC_SingleConversion_TriggerSW_IT
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
+      stm32wbxx_hal_adc.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c
+      stm32wbxx_hal_adc_ex.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+      stm32wbxx_ll_adc.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      24
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      25
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/ADC_SingleConversion_TriggerSW_IT.uvprojx b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/ADC_SingleConversion_TriggerSW_IT.uvprojx
new file mode 100644
index 000000000..81b4bfcef
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/ADC_SingleConversion_TriggerSW_IT.uvprojx
@@ -0,0 +1,556 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      ADC_SingleConversion_TriggerSW_IT
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          ADC_SingleConversion_TriggerSW_IT\
+          ADC_SingleConversion_TriggerSW_IT
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_adc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
+            
+            
+              stm32wbxx_hal_adc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c
+            
+            
+              stm32wbxx_ll_adc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..515f47e70
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.cproject
@@ -0,0 +1,170 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.project
new file mode 100644
index 000000000..cfc8df772
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/.project
@@ -0,0 +1,160 @@
+
+
+	ADC_SingleConversion_TriggerSW_IT
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			ADC_SingleConversion_TriggerSW_IT.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/ADC_SingleConversion_TriggerSW_IT.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_adc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_adc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_adc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/main.c
new file mode 100644
index 000000000..37dd6d776
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/main.c
@@ -0,0 +1,550 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example describes how to use a ADC peripheral to perform
+  *          a single  ADC conversion of a channel, at each software start.
+  *          Example using programming model: interrupt 
+  *          (for programming models polling or DMA transfer, refer to
+  *          other examples).
+  *          This example is based on the STM32WBxx ADC HAL & LL API
+  *          (LL API is used for performance improvement).
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+
+/* Definitions of environment analog values */
+  /* Value of analog reference voltage (Vref+), connected to analog voltage   */
+  /* supply Vdda (unit: mV).                                                  */
+  #define VDDA_APPLI                       (3300UL)
+
+/* Definitions of data related to this example */
+  /* Full-scale digital value with a resolution of 12 bits (voltage range     */
+  /* determined by analog voltage references Vref+ and Vref-,                 */
+  /* refer to reference manual).                                              */
+  #define DIGITAL_SCALE_12BITS             (__LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B))
+
+  /* Init variable out of ADC expected conversion data range */
+  #define VAR_CONVERTED_DATA_INIT_VALUE    (__LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B) + 1)
+
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+ADC_HandleTypeDef hadc1;
+
+/* USER CODE BEGIN PV */
+
+/* Peripherals handlers declaration */
+/* ADC handler declaration */
+ADC_HandleTypeDef    hadc1;
+
+
+/* Variables for ADC conversion data */
+__IO uint16_t uhADCxConvertedData = VAR_CONVERTED_DATA_INIT_VALUE; /* ADC group regular conversion data */
+
+/* Variables for ADC conversion data computation to physical values */
+__IO uint16_t uhADCxConvertedData_Voltage_mVolt = 0UL;  /* Value of voltage calculated from ADC conversion data (unit: mV) */
+
+/* Variable to report status of ADC group regular unitary conversion          */
+/*  0: ADC group regular unitary conversion is not completed                  */
+/*  1: ADC group regular unitary conversion is completed                      */
+/*  2: ADC group regular unitary conversion has not been started yet          */
+/*     (initial state)                                                        */
+__IO uint8_t ubAdcGrpRegularUnitaryConvStatus = 2; /* Variable set into ADC interruption callback */
+
+/* Variable to manage push button on board: interface between ExtLine interruption and main program */
+__IO   uint8_t ubUserButtonClickEvent = RESET;  /* Event detection: Set after User Button interrupt */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_ADC1_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+  /*## Configure peripherals #################################################*/
+  
+  /* Initialize LEDs on board */
+  BSP_LED_Init(LED3);
+  BSP_LED_Init(LED2);
+  
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_ADC1_Init();
+  /* USER CODE BEGIN 2 */
+  
+  /* Configure User push-button (SW1) in Interrupt mode */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI); 
+  
+  
+  
+  /*## Enable peripherals ####################################################*/
+  
+  /* Note: ADC is enabled afterwards when starting ADC conversion using       */
+  /*       function "HAL_ADC_Start_xxx()".                                    */
+ 
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* Note: At this step, a voltage can be supplied to ADC channel input     */
+    /*       (by connecting an external signal voltage generator to the       */
+    /*       analog input pin) to perform a ADC conversion on a determined    */
+    /*       voltage level.                                                   */
+    /*       Otherwise, ADC channel input can be let floating, in this case   */
+    /*       ADC conversion data will be undetermined.                        */
+    
+    /* Wait for event on push button to perform following actions */
+    while ((ubUserButtonClickEvent) == RESET)
+    {
+    }
+    /* Reset variable for next loop iteration */
+    ubUserButtonClickEvent = RESET;
+    
+    /* Turn LED off before performing a new ADC conversion start */
+    BSP_LED_Off(LED2);
+    
+    /* Reset status variable of ADC group regular unitary conversion before   */
+    /* performing a new ADC group regular conversion start.                   */
+    if (ubAdcGrpRegularUnitaryConvStatus != 0)
+    {
+      ubAdcGrpRegularUnitaryConvStatus = 0;
+    }
+    
+    /* Init variable containing ADC conversion data */
+    uhADCxConvertedData = VAR_CONVERTED_DATA_INIT_VALUE;
+    
+    /*## Start ADC conversions ###############################################*/
+    
+    /* Start ADC group regular conversion with IT */
+    /* Note: Perform initial ADC conversion start using driver HAL,           */
+    /*       then following ADC conversion start using driver LL.             */
+    /*       (mandatory to use driver LL after the first call of              */
+    /*       ADC IRQ handler, implemented with driver LL).                    */
+    if (LL_ADC_IsEnabled(ADCx) == 0)
+    {
+      if (HAL_ADC_Start_IT(&hadc1) != HAL_OK)
+      {
+        /* ADC conversion start error */
+        Error_Handler();
+      }
+    }
+    /* ########## Starting from this point HAL API must not be used ########## */
+    else
+    {
+      /* Start ADC group regular conversion */
+      /* Note: Hardware constraint (refer to description of the function          */
+      /*       below):                                                            */
+      /*       On this STM32 serie, setting of this feature is conditioned to     */
+      /*       ADC state:                                                         */
+      /*       ADC must be enabled without conversion on going on group regular,  */
+      /*       without conversion stop command on going on group regular.         */
+      /* Note: In this example, all these checks are not necessary but are        */
+      /*       implemented anyway to show the best practice usages                */
+      /*       corresponding to reference manual procedure.                       */
+      /*       Software can be optimized by removing some of these checks, if     */
+      /*       they are not relevant considering previous settings and actions    */
+      /*       in user application.                                               */
+      if ((LL_ADC_IsEnabled(ADCx) == 1)               &&
+          (LL_ADC_IsDisableOngoing(ADCx) == 0)        &&
+          (LL_ADC_REG_IsConversionOngoing(ADCx) == 0)   )
+      {
+        LL_ADC_REG_StartConversion(ADCx);
+      }
+      else
+      {
+        /* Error: ADC conversion start could not be performed */
+        Error_Handler();
+      }
+    }
+    
+    /* Note: Variable "ubUserButtonClickEvent" is set into push button        */
+    /*       IRQ handler, refer to function "HAL_GPIO_EXTI_Callback()".       */
+    
+    /* Note: ADC conversions data are stored into variable                    */
+    /*       "uhADCxConvertedData".                                           */
+    /*       (for debug: see variable content into watch window).             */
+    
+
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_ADC;
+  PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_HSI;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief ADC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC1_Init(void)
+{
+
+  /* USER CODE BEGIN ADC1_Init 0 */
+
+  /* USER CODE END ADC1_Init 0 */
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN ADC1_Init 1 */
+
+  /* USER CODE END ADC1_Init 1 */
+  /** Common config 
+  */
+  hadc1.Instance = ADC1;
+  hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
+  hadc1.Init.Resolution = ADC_RESOLUTION_12B;
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
+  hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+  hadc1.Init.LowPowerAutoWait = DISABLE;
+  hadc1.Init.ContinuousConvMode = DISABLE;
+  hadc1.Init.NbrOfConversion = 1;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.NbrOfDiscConversion = 1;
+  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+  hadc1.Init.DMAContinuousRequests = DISABLE;
+  hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+  hadc1.Init.OversamplingMode = DISABLE;
+  if (HAL_ADC_Init(&hadc1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_9;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
+  sConfig.SingleDiff = ADC_SINGLE_ENDED;
+  sConfig.OffsetNumber = ADC_OFFSET_NONE;
+  sConfig.Offset = 0;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN ADC1_Init 2 */
+
+  /* USER CODE END ADC1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+
+
+
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT                                               */
+/******************************************************************************/
+
+/**
+  * @brief EXTI line detection callbacks
+  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+ if (GPIO_Pin == BUTTON_SW1_PIN)
+ {
+   /* Set variable to report push button event to main program */
+   ubUserButtonClickEvent = SET;
+ }
+}
+
+/* Note: Lines of code commented below correspond to the example using        */
+/*       HAL driver only.                                                     */
+/*       This example demonstrating a mix of HAL and LL drivers has replaced  */
+/*       these lines using LL driver.                                         */
+// /**
+//   * @brief  Conversion complete callback in non blocking mode
+//   * @param  AdcHandle : ADC handle
+//   * @note   This function is executed when the ADC group regular 
+//   *         sequencer has converted one rank of the sequence.
+//   *         Therefore, this function is executed as many times as number
+//   *         of ranks in the sequence.
+//   * @note   This example shows a simple way to report end of conversion
+//   *         and get conversion result. You can add your own implementation.
+//   * @retval None
+//   */
+// void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *AdcHandle)
+// {
+//   /* Retrieve ADC conversion data */
+//   uhADCxConvertedData = HAL_ADC_GetValue(AdcHandle);
+//
+//   /* Computation of ADC conversions raw data to physical values               */
+//   /* using LL ADC driver helper macro.                                        */
+//   uhADCxConvertedData_Voltage_mVolt = __LL_ADC_CALC_DATA_TO_VOLTAGE(VDDA_APPLI, uhADCxConvertedData, LL_ADC_RESOLUTION_12B);
+//
+//   /* Update status variable of ADC unitary conversion */
+//   ubAdcGrpRegularUnitaryConvStatus = 1;
+//
+//   /* Set LED depending on ADC unitary conversion status */
+//   /* - Turn-on if ADC group regular unitary conversion is completed */
+//   /* - Turn-off if ADC group regular unitary conversion is not completed */
+//   BSP_LED_On(LED2);
+// }
+//
+// /**
+//   * @brief  ADC error callback in non blocking mode
+//   *        (ADC conversion with interruption or transfer by DMA)
+//   * @param  hadc: ADC handle
+//   * @retval None
+//   */
+// void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+// {
+//   /* In case of ADC error, call main error handler */
+//   Error_Handler();
+// }
+
+/**
+  * @brief  ADC group regular end of unitary conversion interruption callback
+  * @note   This function is executed when the ADC group regular 
+  *         sequencer has converted one rank of the sequence.
+  *         Therefore, this function is executed as many times as number
+  *         of ranks in the sequence.
+  * @retval None
+  */
+void AdcGrpRegularUnitaryConvComplete_Callback()
+{
+  /* Retrieve ADC conversion data */
+  /* (data maximum amplitude corresponds to ADC resolution: 12 bits) */
+  uhADCxConvertedData = LL_ADC_REG_ReadConversionData12(ADCx);
+  
+  /* Computation of ADC conversions raw data to physical values               */
+  /* using LL ADC driver helper macro.                                        */
+  uhADCxConvertedData_Voltage_mVolt = __LL_ADC_CALC_DATA_TO_VOLTAGE(VDDA_APPLI, uhADCxConvertedData, LL_ADC_RESOLUTION_12B);
+  
+  /* Update status variable of ADC unitary conversion */
+  ubAdcGrpRegularUnitaryConvStatus = 1;
+  
+  /* Set LED depending on ADC unitary conversion status */
+  /* - Turn-on if ADC group regular unitary conversion is completed */
+  /* - Turn-off if ADC group regular unitary conversion is not completed */
+  BSP_LED_On(LED2);
+  
+}
+
+/**
+  * @brief  ADC group regular overrun interruption callback
+  * @note   This function is executed when ADC group regular
+  *         overrun error occurs.
+  * @retval None
+  */
+void AdcGrpRegularOverrunError_Callback(void)
+{
+  /* Note: Disable ADC interruption that caused this error before entering in */
+  /*       infinite loop below.                                               */
+  
+  /* Disable ADC group regular overrun interruption */
+  LL_ADC_DisableIT_OVR(ADCx);
+  
+  /* In case of ADC error, call main error handler */
+  Error_Handler();
+}
+
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  
+  /* In case of error, LED3 is toggling at a frequency of 1Hz */
+  while(1)
+  {
+    /* Toggle LED3 */
+    BSP_LED_Toggle(LED3);
+    HAL_Delay(500);
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..ad960307e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,181 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief ADC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hadc->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspInit 0 */
+  
+  /*##-1- Enable peripherals and GPIO Clocks #################################*/
+  /* Enable clock of GPIO associated to the peripheral channels */
+  ADCx_CHANNELa_GPIO_CLK_ENABLE();
+  
+  /* Enable clock of ADCx peripheral (core clock) */
+  ADCx_CLK_ENABLE();
+  
+  /* Note: In case of usage of asynchronous clock for ADC, with ADC setting   */
+  /*       "AdcHandle.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIVx",            */
+  /*       the clock source has to be enabled at RCC top level using function */
+  /*       "HAL_RCCEx_PeriphCLKConfig()" or macro "__HAL_RCC_ADC_CONFIG()"    */
+  /*       (refer to comments in driver file header).                         */
+
+  /*##-4- Configure the NVIC #################################################*/
+  /* NVIC configuration for ADC interrupt */
+  /* Priority: high-priority */
+  HAL_NVIC_SetPriority(ADCx_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(ADCx_IRQn);
+  /* USER CODE END ADC1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_ADC_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**ADC1 GPIO Configuration    
+    PA4     ------> ADC1_IN9 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_4;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN ADC1_MspInit 1 */
+
+  /* USER CODE END ADC1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief ADC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+  if(hadc->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspDeInit 0 */
+
+  /*##-1- Reset peripherals ##################################################*/
+  ADCx_FORCE_RESET();
+  ADCx_RELEASE_RESET();
+
+  /*##-2- Disable peripherals and GPIO Clocks ################################*/
+  /* De-initialize GPIO pin of the selected ADC channel */
+  HAL_GPIO_DeInit(ADCx_CHANNELa_GPIO_PORT, ADCx_CHANNELa_PIN);
+
+  /*##-3- Disable the DMA ####################################################*/
+  /* De-Initialize the DMA associated to the peripheral */
+  if(hadc->DMA_Handle != NULL)
+  {
+    HAL_DMA_DeInit(hadc->DMA_Handle);
+  }
+
+  /*##-4- Disable the NVIC ###################################################*/
+  /* Disable the NVIC configuration for ADC interrupt */
+  HAL_NVIC_DisableIRQ(ADCx_IRQn);
+  
+  /* USER CODE END ADC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_ADC_CLK_DISABLE();
+  
+    /**ADC1 GPIO Configuration    
+    PA4     ------> ADC1_IN9 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4);
+
+  /* USER CODE BEGIN ADC1_MspDeInit 1 */
+  
+  /* USER CODE END ADC1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..9ee8c88f0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_it.c
@@ -0,0 +1,272 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+//extern ADC_HandleTypeDef    hadc1;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/**
+  * @brief  This function handles external line 0 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+
+/* Note: Lines of code commented below correspond to the example using        */
+/*       HAL driver only.                                                     */
+/*       This example demonstrating a mix of HAL and LL drivers has replaced  */
+/*       these lines using LL driver.                                         */
+// /**
+//   * @brief  This function handles ADC interrupt request.
+//   * @param  None
+//   * @retval None
+//   */
+// void ADCx_IRQHandler(void)
+// {
+//   HAL_ADC_IRQHandler(&hadc1);
+// }
+
+/**
+  * @brief  This function handles ADCx interrupt request.
+  * @param  None
+  * @retval None
+  */
+void ADC1_IRQHandler(void)
+{
+  /* Customize process using LL interface to improve the performance          */
+  /* (exhaustive feature management not handled).                             */
+  
+  /* ########## Starting from this point HAL API must not be used ########### */
+  
+  /* Check whether ADC group regular end of unitary conversion caused         */
+  /* the ADC interruption.                                                    */
+  if(LL_ADC_IsActiveFlag_EOC(ADCx) != 0)
+  {
+    /* Clear flag ADC group regular end of unitary conversion */
+    LL_ADC_ClearFlag_EOC(ADCx);
+    
+    /* Clear flag ADC group regular end of sequence conversions */
+    /* Note: Clear this flag optionaly, this flag is set with end of          */
+    /*       unitary conversion since there is only 1 rank in                 */
+    /*       group regular sequencer.                                         */
+    LL_ADC_ClearFlag_EOS(ADCx);
+    
+    /* Call interruption treatment function */
+    AdcGrpRegularUnitaryConvComplete_Callback();
+  }
+  
+  /* Check whether ADC group regular overrun caused the ADC interruption */
+  if(LL_ADC_IsActiveFlag_OVR(ADCx) != 0)
+  {
+    /* Clear flag ADC group regular overrun */
+    LL_ADC_ClearFlag_OVR(ADCx);
+    
+    /* Call interruption treatment function */
+    AdcGrpRegularOverrunError_Callback();
+  }
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/readme.txt b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/readme.txt
new file mode 100644
index 000000000..6094054ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/readme.txt
@@ -0,0 +1,86 @@
+/**
+  @page ADC_SingleConversion_TriggerSW_IT ADC example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_MIX/ADC/ADC_SingleConversion_TriggerSW_IT/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the ADC_SingleConversion_TriggerSW_IT example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to use the ADC to perform a single ADC channel conversion at each 
+software start. This example uses the interrupt programming model (for 
+polling and DMA programming models, please refer to other examples). It is 
+based on the STM32WBxx ADC HAL and LL API. The LL API is used 
+for performance improvement.
+
+Example configuration:
+ADC is configured to convert a single channel, in single conversion mode,
+from SW trigger.
+ADC interruption enabled: EOC (end of conversion of ADC group regular).
+
+Example execution:
+At each press of User push-button (SW1), the ADC performs 1 conversion of the selected channel.
+When conversion is completed, ADC interruption occurs.
+IRQ handler callback function reads conversion data from ADC data register
+and stores it into a variable, LED2 is turned on.
+
+For debug: variables to monitor with debugger watch window:
+ - "uhADCxConvertedData": ADC group regular conversion data
+ - "uhADCxConvertedData_Voltage_mVolt": ADC conversion data computation to physical values
+
+Connection needed:
+None.
+Note: Optionally, a voltage can be supplied to the analog input pin (cf pin below),
+      between 0V and Vdda=3.3V, to perform a ADC conversion on a determined
+      voltage level.
+      Otherwise, this pin can be let floating (in this case ADC conversion data
+      will be undetermined).
+
+Other peripherals used:
+  1 GPIO for push button
+  1 GPIO for LED
+  1 GPIO for analog input: PA.04 (Arduino connector CN8 pin A0, Morpho connector CN7 pin 28)
+
+@par Keywords
+
+ADC,ADC channel,DAC channel, conversion, EOC, single channel, single conversion mode, interrupt,
+
+@par Directory contents 
+
+  - ADC/ADC_SingleConversion_TriggerSW_IT/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - ADC/ADC_SingleConversion_TriggerSW_IT/Inc/main.h                  Header for main.c module
+  - ADC/ADC_SingleConversion_TriggerSW_IT/Src/stm32wbxx_it.c          Interrupt handlers
+  - ADC/ADC_SingleConversion_TriggerSW_IT/Src/main.c                  Main program
+  - ADC/ADC_SingleConversion_TriggerSW_IT/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/.extSettings b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/DMA_FLASHToRAM.ioc b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/DMA_FLASHToRAM.ioc
new file mode 100644
index 000000000..90e77d190
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/DMA_FLASHToRAM.ioc
@@ -0,0 +1,127 @@
+#MicroXplorer Configuration settings - do not modify
+Dma.MEMTOMEM.0.Direction=DMA_MEMORY_TO_MEMORY
+Dma.MEMTOMEM.0.EventEnable=DISABLE
+Dma.MEMTOMEM.0.Instance=DMA1_Channel1
+Dma.MEMTOMEM.0.MemDataAlignment=DMA_MDATAALIGN_WORD
+Dma.MEMTOMEM.0.MemInc=DMA_MINC_ENABLE
+Dma.MEMTOMEM.0.Mode=DMA_NORMAL
+Dma.MEMTOMEM.0.PeriphDataAlignment=DMA_PDATAALIGN_WORD
+Dma.MEMTOMEM.0.PeriphInc=DMA_PINC_ENABLE
+Dma.MEMTOMEM.0.Polarity=HAL_DMAMUX_REQUEST_GEN_RISING
+Dma.MEMTOMEM.0.Priority=DMA_PRIORITY_HIGH
+Dma.MEMTOMEM.0.RequestNumber=1
+Dma.MEMTOMEM.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.MEMTOMEM.0.SignalID=NONE
+Dma.MEMTOMEM.0.SyncEnable=DISABLE
+Dma.MEMTOMEM.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.MEMTOMEM.0.SyncRequestNumber=1
+Dma.MEMTOMEM.0.SyncSignalID=NONE
+Dma.Request0=MEMTOMEM
+Dma.RequestsNb=1
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=DMA
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=3
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=DMA_FLASHToRAM.ioc
+ProjectManager.ProjectName=DMA_FLASHToRAM
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_DMA_Init-DMA-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewd b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewd
new file mode 100644
index 000000000..583958c44
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		DMA_FLASHToRAM
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewp b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewp
new file mode 100644
index 000000000..246ac5e16
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/DMA_FLASHToRAM.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    DMA_FLASHToRAM
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/Project.eww
new file mode 100644
index 000000000..d6ac81382
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\DMA_FLASHToRAM.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Inc/main.h
new file mode 100644
index 000000000..eb46b33c7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Inc/main.h
@@ -0,0 +1,77 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_MIX/DMA/DMA_FLASHToRAM/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_pwr.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+#define BUFFER_SIZE                32
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+/* IRQ Handler treatment. */
+void TransferComplete(void);
+void TransferError(void);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..19d12a61f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..707b89171
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_MIX/DMA/DMA_FLASHToRAM/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void DMA1_Channel1_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvoptx b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvoptx
new file mode 100644
index 000000000..f76039f03
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    DMA_FLASHToRAM
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvprojx b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvprojx
new file mode 100644
index 000000000..b1ccf6de0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/MDK-ARM/DMA_FLASHToRAM.uvprojx
@@ -0,0 +1,541 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      DMA_FLASHToRAM
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          DMA_FLASHToRAM\
+          DMA_FLASHToRAM
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..c091d8fc6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/.project
new file mode 100644
index 000000000..894492b5a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	DMA_FLASHToRAM
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			DMA_FLASHToRAM.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/DMA_FLASHToRAM.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Src/main.c
new file mode 100644
index 000000000..134d9bf02
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Src/main.c
@@ -0,0 +1,332 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_MIX/DMA/DMA_FLASHToRAM/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example provides a description of how to use a DMA channel
+  *          to transfer a word data buffer from FLASH memory to embedded
+  *          SRAM memory through the STM32WBxx DMA HAL and LL API.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+DMA_HandleTypeDef hdma_memtomem_dma1_channel1;
+/* USER CODE BEGIN PV */
+
+/* DMA Instance and Channel declaration */
+DMA_TypeDef*  DmaInstance;
+uint32_t      DmaChannel;
+
+static const uint32_t aSRC_Const_Buffer[BUFFER_SIZE] =
+{
+  0x01020304, 0x05060708, 0x090A0B0C, 0x0D0E0F10,
+  0x11121314, 0x15161718, 0x191A1B1C, 0x1D1E1F20,
+  0x21222324, 0x25262728, 0x292A2B2C, 0x2D2E2F30,
+  0x31323334, 0x35363738, 0x393A3B3C, 0x3D3E3F40,
+  0x41424344, 0x45464748, 0x494A4B4C, 0x4D4E4F50,
+  0x51525354, 0x55565758, 0x595A5B5C, 0x5D5E5F60,
+  0x61626364, 0x65666768, 0x696A6B6C, 0x6D6E6F70,
+  0x71727374, 0x75767778, 0x797A7B7C, 0x7D7E7F80
+};
+
+static uint32_t aDST_Buffer[BUFFER_SIZE];
+
+static __IO uint32_t transferErrorDetected;    /* Set to 1 if an error transfer is detected */
+static __IO uint32_t transferCompleteDetected; /* Set to 1 if transfer is correctly completed */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_DMA_Init(void);
+/* USER CODE BEGIN PFP */
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* Initialize LEDs */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED1);
+  BSP_LED_Init(LED3);
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* Set to 1 if an transfer error is detected */
+  transferErrorDetected = 0;
+  transferCompleteDetected = 0;
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_DMA_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Configure and start the DMA transfer using the interrupt mode */
+  /* Enable All the DMA interrupts */
+
+  /* Using HAL interface, use :                                   */
+  /* - HAL_DMA_Start_IT() to Configure and start the DMA transfer */
+  /*                      using the interrupt mode.               */
+
+  /* Using LL interface, use :                                               */
+  /* - __LL_DMA_GET_INSTANCE() to convert DMA1_Channel1 into DMA1           */
+  /* - __LL_DMA_GET_CHANNEL() to convert DMA1_Channel1 into LL_DMA_CHANNEL_1 */
+  /* - LL_DMA_ConfigAddresses() to configure addresses source, destination   */
+  /* - LL_DMA_SetDataLength() to configure data length to transfer           */
+  /* - LL_DMA_EnableIT_TC() to enable Transfer Complete Interrupt            */
+  /* - LL_DMA_EnableIT_TE() to enable Transfer Error Interrupt               */
+  /* - LL_DMA_EnableChannel() to enable DMA Transfer                         */
+  /* ########## Starting from this point HAL API must not be used ########## */
+  DmaInstance        = __LL_DMA_GET_INSTANCE(hdma_memtomem_dma1_channel1.Instance);
+  DmaChannel         = __LL_DMA_GET_CHANNEL(hdma_memtomem_dma1_channel1.Instance);
+  LL_DMA_ConfigAddresses(DmaInstance, DmaChannel, 
+                               (uint32_t)&aSRC_Const_Buffer, 
+                               (uint32_t)&aDST_Buffer, 
+                               LL_DMA_DIRECTION_MEMORY_TO_MEMORY);
+
+  LL_DMA_SetDataLength(DmaInstance, DmaChannel, BUFFER_SIZE);
+
+  LL_DMA_EnableIT_TC(DmaInstance, DmaChannel);
+  LL_DMA_EnableIT_TE(DmaInstance, DmaChannel);
+  LL_DMA_EnableChannel(DmaInstance, DmaChannel);
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    if (transferErrorDetected == 1)
+    {
+      /* Turn LED1 on*/
+      BSP_LED_On(LED1);
+      transferErrorDetected = 0;
+    }
+    if (transferCompleteDetected == 1)
+    {
+      /* Turn LED2 on*/
+      BSP_LED_On(LED2);
+      transferCompleteDetected = 0;
+    }
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/** 
+  * Enable DMA controller clock
+  * Configure DMA for memory to memory transfers
+  *   hdma_memtomem_dma1_channel1
+  */
+static void MX_DMA_Init(void) 
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+  /* Configure DMA request hdma_memtomem_dma1_channel1 on DMA1_Channel1 */
+  hdma_memtomem_dma1_channel1.Instance = DMA1_Channel1;
+  hdma_memtomem_dma1_channel1.Init.Request = DMA_REQUEST_MEM2MEM;
+  hdma_memtomem_dma1_channel1.Init.Direction = DMA_MEMORY_TO_MEMORY;
+  hdma_memtomem_dma1_channel1.Init.PeriphInc = DMA_PINC_ENABLE;
+  hdma_memtomem_dma1_channel1.Init.MemInc = DMA_MINC_ENABLE;
+  hdma_memtomem_dma1_channel1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
+  hdma_memtomem_dma1_channel1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
+  hdma_memtomem_dma1_channel1.Init.Mode = DMA_NORMAL;
+  hdma_memtomem_dma1_channel1.Init.Priority = DMA_PRIORITY_HIGH;
+  if (HAL_DMA_Init(&hdma_memtomem_dma1_channel1) != HAL_OK)
+  {
+    Error_Handler( );
+  }
+
+  /* DMA interrupt init */
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+
+}
+ 
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  DMA conversion complete callback
+  * @note   This function is executed when the transfer complete interrupt
+  *         is generated
+  * @retval None
+  */
+void TransferComplete(void)
+{
+  transferCompleteDetected = 1;
+}
+
+/**
+  * @brief  DMA conversion error callback
+  * @note   This function is executed when the transfer error interrupt
+  *         is generated during DMA transfer
+  * @retval None
+  */
+void TransferError(void)
+{
+  transferErrorDetected = 1;
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  /* Turn LED3 on: Transfer Error */
+  BSP_LED_On(LED3);
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..f9463e6fe
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    DMA/DMA_FLASHToRAM/Inc/stm32wbxx_hal_msp.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..6e388db2e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Src/stm32wbxx_it.c
@@ -0,0 +1,237 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_MIX/DMA/DMA_FLASHToRAM/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_memtomem_dma1_channel1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/**
+  * @brief  This function handles DMA channel interrupt request.
+  * @param  None
+  * @retval None
+  */
+void DMA1_Channel1_IRQHandler(void)
+{
+  /* Check the interrupts and clear flags */
+
+  /* Customize process using LL interface to improve performance           */
+  /* (exhaustive feature management not handled)                           */
+  /* Using LL interface, use :                                             */
+  /* - LL_DMA_IsActiveFlag_TC1() to check complete DMA1 Interrupt */
+  /* - LL_DMA_IsActiveFlag_TE1() to check error DMA1 Interrupt    */
+  /* - LL_DMA_ClearFlag_GI1() to clear all DMA1 Interrupts        */
+  if(LL_DMA_IsActiveFlag_TC1(DMA1) == 1)
+  {
+    LL_DMA_ClearFlag_GI1(DMA1);
+    TransferComplete();
+  }
+  else if(LL_DMA_IsActiveFlag_TE1(DMA1) == 1)
+  {
+    LL_DMA_ClearFlag_GI1(DMA1);
+    TransferError();
+  }
+
+  /* Using HAL interface, use :                                             */
+  /* - HAL_DMA_IRQHandler() to handle all DMA Interrupts (complete, errors) */
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/readme.txt b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/readme.txt
new file mode 100644
index 000000000..e3349526e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/DMA/DMA_FLASHToRAM/readme.txt
@@ -0,0 +1,85 @@
+/**
+  @page DMA_FLASHToRAM DMA example
+
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_MIX/DMA/DMA_FLASHToRAM/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the DMA example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+How to use a DMA to transfer a word data buffer from Flash memory to embedded
+SRAM through the STM32WBxx DMA HAL and LL API. The LL API is used for 
+performance improvement.
+
+At the beginning of the main program the HAL_Init() function is called to reset
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz.
+
+DMA1_Channel1 is configured to transfer the contents of a 32-word data
+buffer stored in Flash memory to the reception buffer declared in RAM.
+
+The start of transfer is triggered by LL API. DMA1_Channel1 memory-to-memory
+transfer is enabled. Source and destination addresses incrementing is also enabled.
+The transfer is started by setting the channel enable bit for DMA1_Channel1.
+At the end of the transfer a Transfer Complete interrupt is generated since it
+is enabled and the callback function (customized by user) is called.
+
+Board's LEDs can be used to monitor the transfer status:
+ - LED2 is ON when the transfer is complete (into the Transfer Complete interrupt
+   routine).
+ - LED1 is ON when there is a transfer error
+ - LED3 is ON when a Error_Handler is called
+
+It is possible to select a different channel for the DMA transfer
+example by modifying defines values in the file main.h.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note This example need to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Directory contents
+
+  - DMA/DMA_FLASHToRAM/Src/system_stm32wbxx.c      STM32WBxx system clock configuration file
+  - DMA/DMA_FLASHToRAM/Src/stm32wbxx_it.c          Interrupt handlers
+  - DMA/DMA_FLASHToRAM/Src/main.c                  Main program
+  - DMA/DMA_FLASHToRAM/Src/stm32wbxx_hal_msp.c     HAL MSP module
+  - DMA/DMA_FLASHToRAM/Inc/stm32wbxx_hal_conf.h    HAL Configuration file
+  - DMA/DMA_FLASHToRAM/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - DMA/DMA_FLASHToRAM/Inc/main.h                  Main program header file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx Devices.
+
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE
+    board and can be easily tailored to any other supported device
+    and development board.
+
+@par How to use it ?
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/.extSettings b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/I2C_OneBoard_ComSlave7_10bits_IT.ewd b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/I2C_OneBoard_ComSlave7_10bits_IT.ewd
new file mode 100644
index 000000000..710eac5c1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/I2C_OneBoard_ComSlave7_10bits_IT.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		I2C_OneBoard_ComSlave7_10bits_IT
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/I2C_OneBoard_ComSlave7_10bits_IT.ewp b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/I2C_OneBoard_ComSlave7_10bits_IT.ewp
new file mode 100644
index 000000000..0fac9523b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/I2C_OneBoard_ComSlave7_10bits_IT.ewp
@@ -0,0 +1,1125 @@
+
+
+  3
+  
+    I2C_OneBoard_ComSlave7_10bits_IT
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/Project.eww
new file mode 100644
index 000000000..71dd5bc1f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\I2C_OneBoard_ComSlave7_10bits_IT.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/I2C_OneBoard_ComSlave7_10bits_IT.ioc b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/I2C_OneBoard_ComSlave7_10bits_IT.ioc
new file mode 100644
index 000000000..d63a9d511
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/I2C_OneBoard_ComSlave7_10bits_IT.ioc
@@ -0,0 +1,146 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+I2C1.AddressingMode=I2C_ADDRESSINGMODE_10BIT
+I2C1.Analog_Filter=I2C_ANALOGFILTER_ENABLE
+I2C1.CustomTiming=Enabled
+I2C1.DualAddressMode=I2C_DUALADDRESS_ENABLE
+I2C1.GeneralCallMode=I2C_GENERALCALL_DISABLE
+I2C1.I2C_Speed_Mode=I2C_Standard
+I2C1.IPParameters=CustomTiming,I2C_Speed_Mode,Speed,Analog_Filter,Timing,NoStretchMode,GeneralCallMode,AddressingMode,DualAddressMode,OwnAddress,OwnAddress2,OwnAddress2Masks
+I2C1.IPParametersWithoutCheck=OwnAddress2,OwnAddress,Timing
+I2C1.NoStretchMode=I2C_NOSTRETCH_DISABLE
+I2C1.OwnAddress=I2C_SLAVE_ADDRESS1
+I2C1.OwnAddress2=I2C_SLAVE_ADDRESS2
+I2C1.OwnAddress2Masks=I2C_OA2_NOMASK
+I2C1.Speed=100
+I2C1.Timing=I2C_TIMING
+I2C3.AddressingMode=I2C_ADDRESSINGMODE_10BIT
+I2C3.Analog_Filter=I2C_ANALOGFILTER_ENABLE
+I2C3.CustomTiming=Enabled
+I2C3.DualAddressMode=I2C_DUALADDRESS_DISABLE
+I2C3.GeneralCallMode=I2C_GENERALCALL_DISABLE
+I2C3.I2C_Speed_Mode=I2C_Standard
+I2C3.IPParameters=CustomTiming,I2C_Speed_Mode,Speed,Analog_Filter,Timing,NoStretchMode,GeneralCallMode,AddressingMode,DualAddressMode,OwnAddress
+I2C3.IPParametersWithoutCheck=Timing
+I2C3.NoStretchMode=I2C_NOSTRETCH_DISABLE
+I2C3.OwnAddress=0
+I2C3.Speed=100
+I2C3.Timing=I2C_TIMING
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=I2C1
+Mcu.IP1=I2C3
+Mcu.IP2=NVIC
+Mcu.IP3=RCC
+Mcu.IP4=SYS
+Mcu.IPNb=5
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB8
+Mcu.Pin1=PB9
+Mcu.Pin2=PA7
+Mcu.Pin3=PB4
+Mcu.Pin4=VP_SYS_VS_Systick
+Mcu.PinsNb=5
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=I2C_SLAVE_ADDRESS1,0x13E;I2C_SLAVE_ADDRESS2,0x64;I2C_TIMING,0x10B07DB7
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA7.Mode=I2C
+PA7.Signal=I2C3_SCL
+PB4.Mode=I2C
+PB4.Signal=I2C3_SDA
+PB8.Mode=I2C
+PB8.Signal=I2C1_SCL
+PB9.Mode=I2C
+PB9.Signal=I2C1_SDA
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=I2C_OneBoard_ComSlave7_10bits_IT.ioc
+ProjectManager.ProjectName=I2C_OneBoard_ComSlave7_10bits_IT
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_I2C1_Init-I2C1-false-HAL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Inc/main.h
new file mode 100644
index 000000000..971751350
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Inc/main.h
@@ -0,0 +1,96 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+#include "stm32wbxx_ll_i2c.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_utils.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+/* User can use this section to tailor I2Cx/I2Cx instance used and associated
+   resources */
+/* Definition for I2Cx_MASTER's NVIC */
+#define I2Cx_MASTER_EV_IRQn                     I2C3_EV_IRQn
+#define I2Cx_MASTER_ER_IRQn                     I2C3_ER_IRQn
+#define I2Cx_MASTER_EV_IRQHandler               I2C3_EV_IRQHandler
+#define I2Cx_MASTER_ER_IRQHandler               I2C3_ER_IRQHandler
+
+/* Definition for I2Cx_SLAVE's NVIC */
+#define I2Cx_SLAVE_EV_IRQn                      I2C1_EV_IRQn
+#define I2Cx_SLAVE_ER_IRQn                      I2C1_ER_IRQn
+#define I2Cx_SLAVE_EV_IRQHandler                I2C1_EV_IRQHandler
+#define I2Cx_SLAVE_ER_IRQHandler                I2C1_ER_IRQHandler
+
+/* Size of Transmission buffer */
+#define TXBUFFERSIZE                            (COUNTOF(aTxBuffer) - 1)
+/* Size of Reception buffer */
+#define RXBUFFERSIZE                            TXBUFFERSIZE
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+#define COUNTOF(__BUFFER__)   (sizeof(__BUFFER__) / sizeof(*(__BUFFER__)))
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define I2C_SLAVE_ADDRESS1 0x13E
+#define I2C_SLAVE_ADDRESS2 0x64
+#define I2C_TIMING 0x10B07DB7
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..ee44a80b3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+#define HAL_I2C_MODULE_ENABLED
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..05db1c956
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Inc/stm32wbxx_it.h
@@ -0,0 +1,73 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Inc/stm32wbxx_it.h 
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void I2Cx_MASTER_EV_IRQHandler(void);
+void I2Cx_MASTER_ER_IRQHandler(void);
+void I2Cx_SLAVE_EV_IRQHandler(void);
+void I2Cx_SLAVE_ER_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/MDK-ARM/I2C_OneBoard_ComSlave7_10bits_IT.uvoptx b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/MDK-ARM/I2C_OneBoard_ComSlave7_10bits_IT.uvoptx
new file mode 100644
index 000000000..71348ab03
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/MDK-ARM/I2C_OneBoard_ComSlave7_10bits_IT.uvoptx
@@ -0,0 +1,521 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    I2C_OneBoard_ComSlave7_10bits_IT
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
+      stm32wbxx_hal_i2c.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c_ex.c
+      stm32wbxx_hal_i2c_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      24
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/MDK-ARM/I2C_OneBoard_ComSlave7_10bits_IT.uvprojx b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/MDK-ARM/I2C_OneBoard_ComSlave7_10bits_IT.uvprojx
new file mode 100644
index 000000000..477ab33d3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/MDK-ARM/I2C_OneBoard_ComSlave7_10bits_IT.uvprojx
@@ -0,0 +1,551 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      I2C_OneBoard_ComSlave7_10bits_IT
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          I2C_OneBoard_ComSlave7_10bits_IT\
+          I2C_OneBoard_ComSlave7_10bits_IT
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_i2c.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
+            
+            
+              stm32wbxx_hal_i2c_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..e72a29b73
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/.project
new file mode 100644
index 000000000..b3d2781e5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/.project
@@ -0,0 +1,155 @@
+
+
+	I2C_OneBoard_ComSlave7_10bits_IT
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			I2C_OneBoard_ComSlave7_10bits_IT.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/I2C_OneBoard_ComSlave7_10bits_IT.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_i2c.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_i2c_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/main.c
new file mode 100644
index 000000000..50d2dfba8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/main.c
@@ -0,0 +1,500 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use STM32WBxx I2C HAL and LL API
+  *          to transmit and receive a data buffer with a communication process
+  *          based on IT transfer.
+  *          The communication is done using 1 Board.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+I2C_HandleTypeDef hi2c1;
+I2C_HandleTypeDef hi2c3;
+
+/* USER CODE BEGIN PV */
+/* Buffer used for transmission */
+uint8_t aTxBuffer[] = " ****I2C_OneBoard communication based on IT****  ****I2C_OneBoard communication based on IT****  ****I2C_OneBoard communication based on IT**** ";
+
+/* Buffer used for reception */
+uint8_t aRxBuffer[RXBUFFERSIZE];
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_I2C1_Init(void);
+static void MX_I2C3_Init(void);
+/* USER CODE BEGIN PFP */
+static uint16_t Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength);
+static void Flush_Buffer(uint8_t* pBuffer, uint16_t BufferLength);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* Configure LED2 and LED3 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_I2C1_Init();
+  MX_I2C3_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Enable the Analog I2C Filter */
+  HAL_I2CEx_ConfigAnalogFilter(&hi2c1,I2C_ANALOGFILTER_ENABLE);
+
+  
+  /* Enable the Analog I2C Filter */
+  HAL_I2CEx_ConfigAnalogFilter(&hi2c1,I2C_ANALOGFILTER_ENABLE);
+
+  /* Configure User push-button (SW1) button */
+  BSP_PB_Init(BUTTON_SW1,BUTTON_MODE_GPIO);
+
+  /* Wait for User push-button (SW1) press before starting the Communication */
+  while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_RESET)
+  {
+  }
+  
+  /* Wait for User push-button (SW1) release before starting the Communication */
+  while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_SET)
+  {
+  }
+
+  /*##-3- Slave1 and Slave2 Receive process from master ####################*/
+  /* Receive data through "aRxBuffer" buffer */
+  while(HAL_I2C_Slave_Receive_IT(&hi2c1, (uint8_t*)&aRxBuffer, RXBUFFERSIZE)!= HAL_OK)
+  {
+  }
+
+  /*##-4- Master Transmit process for Slave1 ###############################*/
+  /* Transmit data through "aTxBuffer" buffer */
+  while(HAL_I2C_Master_Transmit_IT(&hi2c3, (uint16_t)I2C_SLAVE_ADDRESS1, (uint8_t*)&aTxBuffer, TXBUFFERSIZE)!= HAL_OK)
+  {
+    /* Error_Handler() function is called when Timeout error occurs.
+       When Acknowledge failure occurs (Slave don't acknowledge its address)
+       Master restarts communication */
+    if (HAL_I2C_GetError(&hi2c3) != HAL_I2C_ERROR_AF)
+    {
+      Error_Handler();
+    }
+  }
+
+  /*##-5- Wait for the end of the transfer ###################################*/
+  /*  Before starting a new communication transfer, you need to check the current
+      state of the peripheral; if its busy you need to wait for the end of current
+      transfer before starting a new one.
+      For simplicity reasons, this example is just waiting till the end of the
+      transfer, but application may perform other tasks while transfer operation
+      is ongoing. */
+  while (HAL_I2C_GetState(&hi2c1) != HAL_I2C_STATE_READY)
+  {
+  }
+
+  while (HAL_I2C_GetState(&hi2c3) != HAL_I2C_STATE_READY)
+  {
+  }
+
+  /*##-6- Compare the sent and received buffers ##############################*/
+  if(Buffercmp((uint8_t*)aTxBuffer, (uint8_t*)aRxBuffer, TXBUFFERSIZE))
+  {
+    /* Processing Error */
+    Error_Handler();
+  }
+
+  /* Toggle LED2: Transfer in reception Slave1 process is correct */
+  BSP_LED_Toggle(LED2);
+
+  /* Flush Rx buffers */
+  Flush_Buffer((uint8_t*)aRxBuffer,RXBUFFERSIZE);
+
+  /* Wait for User push-button (SW1) press before starting the Communication with Slave2 */
+  while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_RESET)
+  {
+  }
+  
+  /* Wait for User push-button (SW1) release before starting the Communication with Slave2 */
+  while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_SET)
+  {
+  }
+
+  /*##-7- Slave1 and Slave2 Transmit process for master ######################*/
+  while(HAL_I2C_Slave_Transmit_IT(&hi2c1, (uint8_t*)&aTxBuffer, TXBUFFERSIZE)!= HAL_OK)
+  {
+  }
+
+  /*##-8- Configure the I2C MASTER peripheral to discuss with Slave2 (7-Bit address) #*/
+  /* Using LL interface, initializes directly the I2C MASTER peripheral in 7-Bit addressing mode*/
+  LL_I2C_SetMasterAddressingMode(hi2c3.Instance, I2C_ADDRESSINGMODE_7BIT);
+
+  /* Following code sequence is needed in order to keep I2C handle structure          */
+  /* content in line with IP configuration                                            */
+  hi2c3.Init.AddressingMode  = I2C_ADDRESSINGMODE_7BIT;
+
+  /* Using HAL interface, following interface must be used :                          */
+  /*  - HAL_I2C_DeInit() then HAL_I2C_Init() to deInitializes then Initializes        */
+  /*  the I2C MASTER peripheral to perform an update of AddressingMode Init parameter */
+  
+  /*##-9- Put I2C peripheral in Reception process from Slave 2 ###############*/
+  while(HAL_I2C_Master_Receive_IT(&hi2c3, (uint16_t)I2C_SLAVE_ADDRESS2, (uint8_t*)&aRxBuffer, TXBUFFERSIZE)!= HAL_OK)
+  {
+    /* Error_Handler() function is called when Timeout error occurs.
+       When Acknowledge failure occurs (Slave don't acknowledge its address)
+       Master restarts communication */
+    if (HAL_I2C_GetError(&hi2c3) != HAL_I2C_ERROR_AF)
+    {
+      Error_Handler();
+    }
+  }
+
+  /*##-10- Wait for the end of the transfer ##################################*/  
+  /*  Before starting a new communication transfer, you need to check the current   
+      state of the peripheral; if its busy you need to wait for the end of current
+      transfer before starting a new one.
+      For simplicity reasons, this example is just waiting till the end of the
+      transfer, but application may perform other tasks while transfer operation
+      is ongoing. */
+  while (HAL_I2C_GetState(&hi2c1) != HAL_I2C_STATE_READY)
+  {
+  }
+
+  while (HAL_I2C_GetState(&hi2c3) != HAL_I2C_STATE_READY)
+  {
+  }
+
+  /*##-11- Compare the sent and received buffers #############################*/
+  if(Buffercmp((uint8_t*)aTxBuffer, (uint8_t*)aRxBuffer, TXBUFFERSIZE))
+  {
+    /* Processing Error */
+    Error_Handler();
+  }
+
+  /* Toggle LED2: Transfer in Slave2 transmission process is correct */
+  BSP_LED_Toggle(LED2);
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief I2C1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_I2C1_Init(void)
+{
+
+  /* USER CODE BEGIN I2C1_Init 0 */
+
+  /* USER CODE END I2C1_Init 0 */
+
+  /* USER CODE BEGIN I2C1_Init 1 */
+
+  /* USER CODE END I2C1_Init 1 */
+  hi2c1.Instance = I2C1;
+  hi2c1.Init.Timing = I2C_TIMING;
+  hi2c1.Init.OwnAddress1 = I2C_SLAVE_ADDRESS1;
+  hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_10BIT;
+  hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_ENABLE;
+  hi2c1.Init.OwnAddress2 = I2C_SLAVE_ADDRESS2;
+  hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+  hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+  hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+  if (HAL_I2C_Init(&hi2c1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Analogue filter 
+  */
+  if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Digital filter 
+  */
+  if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN I2C1_Init 2 */
+
+  /* USER CODE END I2C1_Init 2 */
+
+}
+
+/**
+  * @brief I2C3 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_I2C3_Init(void)
+{
+
+  /* USER CODE BEGIN I2C3_Init 0 */
+
+  /* USER CODE END I2C3_Init 0 */
+
+  /* USER CODE BEGIN I2C3_Init 1 */
+
+  /* USER CODE END I2C3_Init 1 */
+  hi2c3.Instance = I2C3;
+  hi2c3.Init.Timing = I2C_TIMING;
+  hi2c3.Init.OwnAddress1 = 0;
+  hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_10BIT;
+  hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+  hi2c3.Init.OwnAddress2 = 0;
+  hi2c3.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+  hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+  hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+  if (HAL_I2C_Init(&hi2c3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Analogue filter 
+  */
+  if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Digital filter 
+  */
+  if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN I2C3_Init 2 */
+
+  /* USER CODE END I2C3_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  Compares two buffers.
+  * @param  pBuffer1, pBuffer2: buffers to be compared.
+  * @param  BufferLength: buffer's length
+  * @retval 0  : pBuffer1 identical to pBuffer2
+  *         >0 : pBuffer1 differs from pBuffer2
+  */
+static uint16_t Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
+{
+  while (BufferLength--)
+  {
+    if ((*pBuffer1) != *pBuffer2)
+    {
+      return BufferLength;
+    }
+    pBuffer1++;
+    pBuffer2++;
+  }
+
+  return 0;
+}
+
+/**
+  * @brief  Flushes the buffer
+  * @param  pBuffer: buffers to be flushed.
+  * @param  BufferLength: buffer's length
+  * @retval None
+  */
+static void Flush_Buffer(uint8_t* pBuffer, uint16_t BufferLength)
+{
+  while (BufferLength--)
+  {
+    *pBuffer = 0;
+
+    pBuffer++;
+  }
+}
+
+/**
+  * @brief  I2C error callbacks.
+  * @param  I2cHandle: I2C handle
+  * @note   This example shows a simple way to report transfer error, and you can
+  *         add your own implementation.
+  * @retval None
+  */
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *I2cHandle)
+{
+  /* Turn Off LED2 */
+  BSP_LED_Off(LED2);
+  /* Turn On LED3 */
+  BSP_LED_On(LED3);
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  while(1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..4194e4b3d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,211 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************  
+  */ 
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief I2C MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hi2c: I2C handle pointer
+* @retval None
+*/
+void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hi2c->Instance==I2C1)
+  {
+  /* USER CODE BEGIN I2C1_MspInit 0 */
+  
+  /* USER CODE END I2C1_MspInit 0 */
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**I2C1 GPIO Configuration    
+    PB8     ------> I2C1_SCL
+    PB9     ------> I2C1_SDA 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* Peripheral clock enable */
+    __HAL_RCC_I2C1_CLK_ENABLE();
+  /* USER CODE BEGIN I2C1_MspInit 1 */
+    /* NVIC for I2Cx_MASTER */
+    HAL_NVIC_SetPriority(I2Cx_MASTER_ER_IRQn, 1, 0);
+    HAL_NVIC_EnableIRQ(I2Cx_MASTER_ER_IRQn);
+    HAL_NVIC_SetPriority(I2Cx_MASTER_EV_IRQn, 2, 0);
+    HAL_NVIC_EnableIRQ(I2Cx_MASTER_EV_IRQn);
+  /* USER CODE END I2C1_MspInit 1 */
+  }
+  else if(hi2c->Instance==I2C3)
+  {
+  /* USER CODE BEGIN I2C3_MspInit 0 */
+  
+  /* USER CODE END I2C3_MspInit 0 */
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**I2C3 GPIO Configuration    
+    PA7     ------> I2C3_SCL
+    PB4     ------> I2C3_SDA 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_4;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* Peripheral clock enable */
+    __HAL_RCC_I2C3_CLK_ENABLE();
+  /* USER CODE BEGIN I2C3_MspInit 1 */
+
+    /* NVIC for I2Cx_SLAVE */
+    HAL_NVIC_SetPriority(I2Cx_SLAVE_ER_IRQn, 1, 0);
+    HAL_NVIC_EnableIRQ(I2Cx_SLAVE_ER_IRQn);
+    HAL_NVIC_SetPriority(I2Cx_SLAVE_EV_IRQn, 2, 0);
+    HAL_NVIC_EnableIRQ(I2Cx_SLAVE_EV_IRQn);
+  /* USER CODE END I2C3_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief I2C MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hi2c: I2C handle pointer
+* @retval None
+*/
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
+{
+  if(hi2c->Instance==I2C1)
+  {
+  /* USER CODE BEGIN I2C1_MspDeInit 0 */
+  
+  /* USER CODE END I2C1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_I2C1_CLK_DISABLE();
+  
+    /**I2C1 GPIO Configuration    
+    PB8     ------> I2C1_SCL
+    PB9     ------> I2C1_SDA 
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9);
+
+  /* USER CODE BEGIN I2C1_MspDeInit 1 */
+
+    HAL_NVIC_DisableIRQ(I2Cx_MASTER_ER_IRQn);
+    HAL_NVIC_DisableIRQ(I2Cx_MASTER_EV_IRQn);
+  /* USER CODE END I2C1_MspDeInit 1 */
+  }
+  else if(hi2c->Instance==I2C3)
+  {
+  /* USER CODE BEGIN I2C3_MspDeInit 0 */
+  
+  /* USER CODE END I2C3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_I2C3_CLK_DISABLE();
+  
+    /**I2C3 GPIO Configuration    
+    PA7     ------> I2C3_SCL
+    PB4     ------> I2C3_SDA 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_7);
+
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_4);
+
+  /* USER CODE BEGIN I2C3_MspDeInit 1 */
+
+    HAL_NVIC_DisableIRQ(I2Cx_SLAVE_ER_IRQn);
+    HAL_NVIC_DisableIRQ(I2Cx_SLAVE_EV_IRQn);
+  /* USER CODE END I2C3_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..73f5af652
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/stm32wbxx_it.c
@@ -0,0 +1,252 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/stm32wbxx_it.c 
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and 
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+/* I2C handler declared in "main.c" file */
+extern I2C_HandleTypeDef hi2c3;
+extern I2C_HandleTypeDef hi2c1;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles I2C event interrupt request.
+  * @param  None
+  * @retval None
+  * @Note   This function is redefined in "main.h" and related to I2C data transmission
+  */
+void I2Cx_MASTER_EV_IRQHandler(void)
+{
+  HAL_I2C_EV_IRQHandler(&hi2c3);
+}
+
+/**
+  * @brief  This function handles I2C error interrupt request.
+  * @param  None
+  * @retval None
+  * @Note   This function is redefined in "main.h" and related to I2C error
+  */
+void I2Cx_MASTER_ER_IRQHandler(void)
+{
+  HAL_I2C_ER_IRQHandler(&hi2c3);
+}
+
+/**
+  * @brief  This function handles I2C event interrupt request.
+  * @param  None
+  * @retval None
+  * @Note   This function is redefined in "main.h" and related to I2C data transmission
+  */
+void I2Cx_SLAVE_EV_IRQHandler(void)
+{
+  HAL_I2C_EV_IRQHandler(&hi2c1);
+}
+
+/**
+  * @brief  This function handles I2C error interrupt request.
+  * @param  None
+  * @retval None
+  * @Note   This function is redefined in "main.h" and related to I2C error
+  */
+void I2Cx_SLAVE_ER_IRQHandler(void)
+{
+  HAL_I2C_ER_IRQHandler(&hi2c1);
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/readme.txt b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/readme.txt
new file mode 100644
index 000000000..b8e16dee0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/readme.txt
@@ -0,0 +1,152 @@
+/**
+  @page I2C_OneBoard_ComSlave7_10bits_IT I2C One Board Communication Slave 10-Bit
+  then Slave 7-Bit IT example
+  
+  @verbatim
+  ******************** (C) COPYRIGHT 2019 STMicroelectronics *******************
+  * @file    Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the I2C One Board Master Communication with 
+  *          a Slave 10-Bit address then a Slave 7-Bit address example.
+  ******************************************************************************
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+How to perform I2C data buffer transmission/reception between 
+one master and two slaves with different address sizes (7-bit or 10-bit). This example 
+uses the STM32WBxx I2C HAL and LL API (LL API usage for performance improvement)
+and an interrupt.
+
+Board: NUCLEO-WB35CE (embeds a STM32WB35CE device)
+SCL MASTER Pin:PA7 (CN5, pin4)
+SDA MASTER Pin:PB4 (CN5, pin5)
+
+SCL SLAVE Pin: PB8 (CN10, pin3)
+SDA SLAVE Pin: PB9 (CN10, pin5)
+   ____________________________________________
+  |     ____________          ____________     |
+  |    | I2C3       |        |I2C1        |    |
+  |    |            |        |            |    |
+  |    |  SCL_MASTER|________|SCL_SLAVE   |    |
+  |    |            |        |            |    |
+  |    |            |        |            |    |
+  |    |  SDA_MASTER|________|SDA_SLAVE   |    |
+  |    |____________|        |____________|    |
+  |               __                           |
+  |              |__|                          |
+  |              USER                          |
+  |                                            |
+  |____________________________________________|
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz.
+
+The I2C peripheral configuration is ensured by the HAL_I2C_Init() function.
+This later is calling the HAL_I2C_MspInit()function which core is implementing
+the configuration of the needed I2C resources according to the used hardware (CLOCK, 
+GPIO and NVIC). You may update this function to change I2C configuration.
+
+The user can disable internal pull-up by opening ioc file.
+For that, user can follow the procedure :
+1- Double click on the I2C_OneBoard_ComSlave7_10bits_IT.ioc file
+2- When CUBEMX tool is opened, select System Core category
+3- Then in the configuration of GPIO/I2C3, change Pull-up to No pull-up and no pull-down for the both pins
+4- Same action in the configuration of GPIO/I2C1, change Pull-up to No pull-up and no pull-down for the both pins
+5- Last step, generate new code thanks to button "GENERATE CODE"
+The example is updated with no pull on each pin used for I2C communication
+
+
+For this example two buffers are used 
+- aTxBuffer buffer contains the data to be transmitted 
+- aRxBuffer buffer is used to save the received data
+Note that both buffers have same size
+                       
+Example execution:
+First step, press the User push-button (SW1), this action initiates a reception process (aRxBuffer) for
+I2C Slave1 or Slave2 address through HAL_I2C_Slave_Receive_IT().
+Then I2C Master starts the communication by sending aTxBuffer through HAL_I2C_Master_Transmit_IT()
+for Slave1 (10-Bit address). 
+The end of this step is monitored through the HAL_I2C_GetState() function
+result.
+Finally, aTxBuffer and aRxBuffer are compared through Buffercmp() in order to 
+check buffers correctness.
+Toggle LED2 when data is received correctly, otherwise LED3 is ON and communication is stopped (using infinite loop)
+Second step, press the User push-button (SW1), this action initiates a transmission process (aTxBuffer) for
+I2C Slave1 or Slave2 address through HAL_I2C_Slave_Transmit_IT().
+Then I2C Master starts the communication by receiving aRxBuffer through HAL_I2C_Master_Transmit_IT()
+from Slave2 (7-Bit address).
+The end of this two steps are monitored through the HAL_I2C_GetState() function
+result.
+Finally, aTxBuffer and aRxBuffer are compared through Buffercmp() in order to 
+check buffers correctness.
+Toggle LED2 when data is received correctly, otherwise LED3 is ON and communication is stopped (using infinite loop)
+
+@note In Master side, only Acknowledge failure error is handled. When this error
+       occurs Master restart the current operation until Slave acknowledges it's
+       address.
+        
+@note I2C3 and I2C1 instance used and associated resources can be updated in "main.h"
+       file depending hardware configuration used.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note The application need to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+
+@par Directory contents 
+
+  - Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Inc/stm32wbxx_it.h          I2C interrupt handlers header file
+  - Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Inc/main.h                  Header for main.c module  
+  - Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/stm32wbxx_it.c          I2C interrupt handlers
+  - Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/main.c                  Main program
+  - Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/system_stm32wbxx.c      STM32WBxx system source file
+  - Examples_MIX/I2C/I2C_OneBoard_ComSlave7_10bits_IT/Src/stm32wbxx_hal_msp.c     HAL MSP file    
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35xx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.    
+
+  -NUCLEO-WB35CE Set-up
+    - Connect GPIOs connected to I2C1 SCL/SDA (PB8 and PB9)
+    to respectively SCL and SDA pins of I2C3 (PA7 and PB4).
+      - I2C1_SCL  PB8(CN10, pin3) : connected to I2C3_SCL PA7(CN5, pin4)
+      - I2C1_SDA  PB9(CN10, pin5) : connected to I2C3_SDA PB4(CN5, pin5)
+
+  - Launch the program.
+  - Press User push-button (SW1) to initiate a write request by Master
+    then Slave1 (10-Bit address) receive a Buffer. LED2 Toggle when data is received correctly.
+  - Press again User push-button (SW1) to initiate a read request by Master
+    then Slave2 (7-Bit address) Transmit a Buffer. LED2 Toggle when data is received correctly.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/.extSettings b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/PWR_STOP1.ewd b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/PWR_STOP1.ewd
new file mode 100644
index 000000000..137b34fc5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/PWR_STOP1.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		PWR_STOP1
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/PWR_STOP1.ewp b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/PWR_STOP1.ewp
new file mode 100644
index 000000000..38a2867ae
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/PWR_STOP1.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    PWR_STOP1
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/Project.eww
new file mode 100644
index 000000000..f8c08d35f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\PWR_STOP1.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Inc/main.h
new file mode 100644
index 000000000..ce658b9c7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Inc/main.h
@@ -0,0 +1,85 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_MIX/PWR/PWR_STOP1/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+#include "stm32wbxx_hal.h"
+#include "nucleo_wb35ce.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_pwr.h"
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* Defines related to Clock configuration */
+
+#define RTC_ASYNCH_PREDIV    0x7F
+#define RTC_SYNCH_PREDIV     0xF9  /* 32Khz/128 - 1 */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..19d12a61f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..e7c86c66a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Inc/stm32wbxx_it.h
@@ -0,0 +1,72 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_MIX/PWR/PWR_STOP1/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+void EXTI0_IRQHandler(void);
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/MDK-ARM/PWR_STOP1.uvoptx b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/MDK-ARM/PWR_STOP1.uvoptx
new file mode 100644
index 000000000..a80e8411b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/MDK-ARM/PWR_STOP1.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    PWR_STOP1
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      2
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      5
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      5
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      5
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      5
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      5
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      5
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      5
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      5
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      5
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      5
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/MDK-ARM/PWR_STOP1.uvprojx b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/MDK-ARM/PWR_STOP1.uvprojx
new file mode 100644
index 000000000..95b3a76f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/MDK-ARM/PWR_STOP1.uvprojx
@@ -0,0 +1,542 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      PWR_STOP1
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          PWR_STOP1\
+          PWR_STOP1
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/PWR_STOP1.ioc b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/PWR_STOP1.ioc
new file mode 100644
index 000000000..d3893772f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/PWR_STOP1.ioc
@@ -0,0 +1,106 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=PWR_STOP1.ioc
+ProjectManager.ProjectName=PWR_STOP1
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..3c1651b6b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/.project
new file mode 100644
index 000000000..a9d15cec8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	PWR_STOP1
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			PWR_STOP1.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/PWR_STOP1.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Src/main.c
new file mode 100644
index 000000000..6ceb761a5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Src/main.c
@@ -0,0 +1,301 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_MIX/PWR/PWR_STOP1/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use STM32WBxx PWR HAL API to enter
+  *          and exit the STOP 1 mode.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define LED_TOGGLE_DELAY         100
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+static __IO uint32_t TimingDelay;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+
+
+void SYSCLKConfig_FromSTOP(void);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+  /* Configure LED2, and LED1 */
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED1);
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+  /* Enable Systick interruption for HAL */
+  LL_SYSTICK_EnableIT();
+
+  /* User push-button (SW1) (External line 0) will be used to wakeup the system from STOP mode */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+
+  /* Ensure that MSI is wake-up system clock */ 
+  __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(RCC_STOP_WAKEUPCLOCK_MSI);
+  
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+    /* Insert 5 second delay */
+    HAL_Delay(5000);
+
+    /* Turn OFF LED's */
+    BSP_LED_Off(LED2);
+    BSP_LED_Off(LED1);
+
+    /* Enter STOP 1 mode */
+    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+    
+    /* ... STOP 1 mode ... */
+
+    /* At Stop 1 mode exit, enable and select PLL as system clock source 
+       (PLL is disabled in STOP mode) */     
+
+    SYSCLKConfig_FromSTOP(); 
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Configures system clock after wake-up from STOP: enable PLL
+  *         and select PLL as system clock source.
+  * @note   RCC LL API is used in this case to allow MCU to wake-up as quick
+  *         as possible from STOP mode.
+  * @param  None
+  * @retval None
+  */
+void SYSCLKConfig_FromSTOP(void)
+{
+  /* Customize process using LL interface to improve the performance 
+     (wake-up time from STOP quicker in LL than HAL) */  
+  /* Main PLL activation */
+  LL_RCC_PLL_Enable();
+  while(LL_RCC_PLL_IsReady() != 1) 
+  {
+  };
+  
+  /* SYSCLK activation on the main PLL */
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) 
+  {
+  };
+}
+/**
+  * @brief SYSTICK callback
+  * @param None
+  * @retval None
+  */
+void HAL_SYSTICK_Callback(void)
+{
+
+  if (TimingDelay != 0)
+  {
+    TimingDelay--;
+  }
+  else
+  {
+    /* Toggle LED2 */
+    BSP_LED_Toggle(LED2);
+    TimingDelay = LED_TOGGLE_DELAY;
+  }
+}
+
+
+/**
+  * @brief EXTI line detection callbacks
+  * @param GPIO_Pin: Specifies the pins connected EXTI line
+  * @retval None
+  */
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  if (GPIO_Pin == BUTTON_SW1_PIN)
+  {
+    /* Switch on LED2 */
+    BSP_LED_On(LED2);
+  }
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  HAL_SuspendTick();
+  
+  /* Turn LED2 & LED1 */
+  BSP_LED_On(LED2);
+  BSP_LED_On(LED1);
+  while (1)
+  {
+  }
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..cdd5c716f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,81 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32wbxx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..2bb4fb5a9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Src/stm32wbxx_it.c
@@ -0,0 +1,216 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Examples_MIX/PWR/PWR_STOP1/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+  HAL_SYSTICK_IRQHandler();
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+/**
+  * @brief  This function handles external line 0 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void)
+{
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW1_PIN);
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/readme.txt b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/readme.txt
new file mode 100644
index 000000000..3d190dbe0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/PWR/PWR_STOP1/readme.txt
@@ -0,0 +1,101 @@
+/**
+  @page PWR_STOP1 PWR Example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Examples_MIX/PWR/PWR_STOP1/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the PWR_STOP1 example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+ 
+How to enter the STOP 1 mode and wake up from this mode by using external 
+reset or wakeup interrupt (all the RCC function calls use RCC LL API 
+for minimizing footprint and maximizing performance).
+
+In the associated software, the system clock is set to 64 MHz, an EXTI line
+is connected to the user button through PA.0 and configured to generate an 
+interrupt on falling edge upon key press.
+The SysTick is programmed to generate an interrupt each 1 ms and in the SysTick 
+interrupt handler, LED2 is toggled in order to indicate whether the MCU is in STOP 1 mode 
+or RUN mode.
+
+5 seconds after start-up, the system automatically enters STOP 1 mode and 
+LED2 stops toggling.
+
+The User push-button (SW1) can be pressed at any time to wake-up the system. 
+The software then comes back in RUN mode for 5 sec. before automatically entering STOP 1 mode again. 
+
+Two leds LED2 and LED1 are used to monitor the system state as following:
+ - LED2 toggling: system in RUN mode
+ - LED2 off : system in STOP 1 mode
+ - LED2 and LED1 ON: configuration failed (system will go to an infinite loop)
+
+These steps are repeated in an infinite loop.
+
+@note To measure MCU current consumption on board STM32WB Nucleo,
+      board configuration must be applied:
+      - remove all jumpers on connector JP5 to avoid leakages between ST-Link circuitry and STM32WB device.
+      - remove jumper JP2 and connect an amperemeter to measure current between the 2 connectors of JP2.
+
+@note This example can not be used in DEBUG mode due to the fact 
+      that the Cortex-M4 core is no longer clocked during low power mode 
+      so debugging features are disabled.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+  
+@par Keywords
+
+Power, PWR, stop mode, wake-up, external reset, Interrupt, low power mode    
+
+@par Directory contents 
+
+  - Examples_MIX/PWR/PWR_STOP1/Inc/stm32wbxx_conf.h         HAL Configuration file
+  - Examples_MIX/PWR/PWR_STOP1/Inc/stm32wbxx_it.h           Header for stm32wbxx_it.c
+  - Examples_MIX/PWR/PWR_STOP1/Inc/main.h                   Header file for main.c
+  - Examples_MIX/PWR/PWR_STOP1/Src/system_stm32wbxx.c       STM32WBxx system clock configuration file
+  - Examples_MIX/PWR/PWR_STOP1/Src/stm32wbxx_it.c           Interrupt handlers
+  - Examples_MIX/PWR/PWR_STOP1/Src/main.c                   Main program
+  - Examples_MIX/PWR/PWR_STOP1/Src/stm32wbxx_hal_msp.c      HAL MSP module
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WBxx devices
+    
+
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE
+    board and can be easily tailored to any other supported device 
+    and development board.
+
+  - NUCLEO-WB35CE set-up:
+    - Use LED2 and LED1 connected respectively to PB.00 and PB.05 pins
+    - User push-button (SW1) connected to pin PA.00 (External line 0)
+    
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/.extSettings b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/Project.eww
new file mode 100644
index 000000000..62e279b4a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\SPI_HalfDuplex_ComPollingIT_Master.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/SPI_HalfDuplex_ComPollingIT_Master.ewd b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/SPI_HalfDuplex_ComPollingIT_Master.ewd
new file mode 100644
index 000000000..c9e9bd8fc
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/SPI_HalfDuplex_ComPollingIT_Master.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		SPI_HalfDuplex_ComPollingIT_Master
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/SPI_HalfDuplex_ComPollingIT_Master.ewp b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/SPI_HalfDuplex_ComPollingIT_Master.ewp
new file mode 100644
index 000000000..f2a4910a4
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/SPI_HalfDuplex_ComPollingIT_Master.ewp
@@ -0,0 +1,1125 @@
+
+
+  3
+  
+    SPI_HalfDuplex_ComPollingIT_Master
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Inc/main.h
new file mode 100644
index 000000000..2bb200694
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Inc/main.h
@@ -0,0 +1,73 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_HalfDuplex_ComPollingIT_Master/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+#include "stm32wbxx_ll_spi.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+#define COUNTOF(__BUFFER__)   (sizeof(__BUFFER__) / sizeof(*(__BUFFER__)))
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+/* Size of buffer */
+#define BUFFERSIZE                       (COUNTOF(aTxBuffer) - 1)
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..afd5aac3b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+#define HAL_SPI_MODULE_ENABLED
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..bce4157e0
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_HalfDuplex_ComPollingIT_Master/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/MDK-ARM/SPI_HalfDuplex_ComPollingIT_Master.uvoptx b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/MDK-ARM/SPI_HalfDuplex_ComPollingIT_Master.uvoptx
new file mode 100644
index 000000000..5aa7b7789
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/MDK-ARM/SPI_HalfDuplex_ComPollingIT_Master.uvoptx
@@ -0,0 +1,521 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    SPI_HalfDuplex_ComPollingIT_Master
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+      stm32wbxx_hal_spi.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+      stm32wbxx_hal_spi_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      24
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/MDK-ARM/SPI_HalfDuplex_ComPollingIT_Master.uvprojx b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/MDK-ARM/SPI_HalfDuplex_ComPollingIT_Master.uvprojx
new file mode 100644
index 000000000..a278456b1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/MDK-ARM/SPI_HalfDuplex_ComPollingIT_Master.uvprojx
@@ -0,0 +1,551 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      SPI_HalfDuplex_ComPollingIT_Master
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          SPI_HalfDuplex_ComPollingIT_Master\
+          SPI_HalfDuplex_ComPollingIT_Master
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_spi.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+            
+            
+              stm32wbxx_hal_spi_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/SPI_HalfDuplex_ComPollingIT_Master.ioc b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/SPI_HalfDuplex_ComPollingIT_Master.ioc
new file mode 100644
index 000000000..4fa8dd8a9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/SPI_HalfDuplex_ComPollingIT_Master.ioc
@@ -0,0 +1,135 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SPI1
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA5
+Mcu.Pin1=PA7
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA5.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA5.GPIO_PuPd=GPIO_PULLDOWN
+PA5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA5.Locked=true
+PA5.Mode=Simplex_Bidirectional_Master
+PA5.Signal=SPI1_SCK
+PA7.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA7.GPIO_PuPd=GPIO_PULLDOWN
+PA7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA7.Mode=Simplex_Bidirectional_Master
+PA7.Signal=SPI1_MOSI
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=SPI_HalfDuplex_ComPollingIT_Master.ioc
+ProjectManager.ProjectName=SPI_HalfDuplex_ComPollingIT_Master
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_256
+SPI1.CLKPhase=SPI_PHASE_1EDGE
+SPI1.CLKPolarity=SPI_POLARITY_LOW
+SPI1.CRCCalculation=SPI_CRCCALCULATION_DISABLE
+SPI1.CalculateBaudRate=250.0 KBits/s
+SPI1.DataSize=SPI_DATASIZE_8BIT
+SPI1.Direction=SPI_DIRECTION_1LINE
+SPI1.FirstBit=SPI_FIRSTBIT_MSB
+SPI1.GPIO_SPEED=GPIO_SPEED_FREQ_HIGH
+SPI1.IPParameters=TIMode,DataSize,FirstBit,BaudRatePrescaler,CLKPolarity,CLKPhase,CRCCalculation,NSSPMode,NSS,VirtualType,Mode,Direction,CalculateBaudRate,GPIO_SPEED
+SPI1.Mode=SPI_MODE_MASTER
+SPI1.NSS=SPI_NSS_SOFT
+SPI1.NSSPMode=SPI_NSS_PULSE_DISABLE
+SPI1.TIMode=SPI_TIMODE_DISABLE
+SPI1.VirtualType=VM_MASTER
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..2d1b2f998
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/.project
new file mode 100644
index 000000000..c3560c28d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/.project
@@ -0,0 +1,155 @@
+
+
+	SPI_HalfDuplex_ComPollingIT_Master
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			SPI_HalfDuplex_ComPollingIT_Master.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/SPI_HalfDuplex_ComPollingIT_Master.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_spi.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_spi_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/main.c
new file mode 100644
index 000000000..01f9c027c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/main.c
@@ -0,0 +1,317 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use STM32WBxx SPI HAL API to transmit
+  *          and receive a data buffer with a communication process based on
+  *          Interrupt transfer.
+  *          The communication is done using 2 Boards.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+enum {
+	TRANSFER_WAIT,
+	TRANSFER_COMPLETE,
+	TRANSFER_ERROR
+};
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+SPI_HandleTypeDef hspi1;
+
+/* USER CODE BEGIN PV */
+/* Buffer used for transmission */
+uint8_t aTxBuffer[] = "**** SPI - Two Boards communication based on Polling (LL driver) for Master Board and Interrupt (HAL Driver) for Slave Board ****";
+__IO uint8_t ubNbDataToTransmit  = BUFFERSIZE;
+__IO uint8_t ubNbDataTransmitted = 0;
+
+/* Buffer used for reception */
+uint8_t aRxBuffer[BUFFERSIZE];
+
+/* transfer state */
+__IO uint32_t wTransferState = TRANSFER_WAIT;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_SPI1_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_SPI1_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Configure LED1, LED2 and LED3 */
+  BSP_LED_Init(LED1);
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+
+
+  /* Configure User push-button (SW1) */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_GPIO);
+
+  /* Wait for User push-button (SW1) press before starting the Communication */
+  while (BSP_PB_GetState(BUTTON_SW1) != GPIO_PIN_RESET)
+  {
+    BSP_LED_Toggle(LED1);
+    HAL_Delay(100);
+  }
+  BSP_LED_Off(LED1);
+
+  /*##-1- Start the Half Duplex Communication process ########################*/
+  /* Half Duplex Direction (Tx) not Done by HAL_Init. */
+  LL_SPI_SetTransferDirection(hspi1.Instance, LL_SPI_HALF_DUPLEX_TX);
+  
+  /* Enable SPI before start transmission */
+  LL_SPI_Enable(hspi1.Instance);
+  
+  while(ubNbDataToTransmit > 0)
+  {
+    /* Check TXE flag to transmit data */
+    if(LL_SPI_IsActiveFlag_TXE(hspi1.Instance))
+    {
+      /* Transmit 8bit Data */
+      LL_SPI_TransmitData8(hspi1.Instance, aTxBuffer[ubNbDataTransmitted++]);
+      ubNbDataToTransmit--;
+    }
+  }
+  
+  /* Wait End Of Transmission: TXE set and Tx Fifo empty */
+
+  while((LL_SPI_IsActiveFlag_TXE(hspi1.Instance) != 1));
+  while(LL_SPI_GetTxFIFOLevel(hspi1.Instance) != LL_SPI_TX_FIFO_EMPTY);
+  
+  /* Disable SPI after End of Transmission */
+  LL_SPI_Disable(hspi1.Instance);
+
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief SPI1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SPI1_Init(void)
+{
+
+  /* USER CODE BEGIN SPI1_Init 0 */
+
+  /* USER CODE END SPI1_Init 0 */
+
+  /* USER CODE BEGIN SPI1_Init 1 */
+
+  /* USER CODE END SPI1_Init 1 */
+  /* SPI1 parameter configuration*/
+  hspi1.Instance = SPI1;
+  hspi1.Init.Mode = SPI_MODE_MASTER;
+  hspi1.Init.Direction = SPI_DIRECTION_1LINE;
+  hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
+  hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
+  hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
+  hspi1.Init.NSS = SPI_NSS_SOFT;
+  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
+  hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
+  hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
+  hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+  hspi1.Init.CRCPolynomial = 7;
+  hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
+  hspi1.Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
+  if (HAL_SPI_Init(&hspi1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN SPI1_Init 2 */
+
+  /* USER CODE END SPI1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  while(1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..12aa955c8
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,149 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief SPI MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hspi->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspInit 0 */
+
+  /* USER CODE END SPI1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SPI1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**SPI1 GPIO Configuration    
+    PA5     ------> SPI1_SCK
+    PA7     ------> SPI1_MOSI 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SPI1_MspInit 1 */
+
+  /* USER CODE END SPI1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief SPI MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
+{
+  if(hspi->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspDeInit 0 */
+    /* Reset peripherals */
+    __HAL_RCC_SPI1_FORCE_RESET();
+    __HAL_RCC_SPI1_RELEASE_RESET();
+
+  /* USER CODE END SPI1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SPI1_CLK_DISABLE();
+  
+    /**SPI1 GPIO Configuration    
+    PA5     ------> SPI1_SCK
+    PA7     ------> SPI1_MOSI 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_7);
+
+  /* USER CODE BEGIN SPI1_MspDeInit 1 */
+
+  /* USER CODE END SPI1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..89308dc31
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/stm32wbxx_it.c
@@ -0,0 +1,205 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/readme.txt b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/readme.txt
new file mode 100644
index 000000000..b95cef262
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/readme.txt
@@ -0,0 +1,120 @@
+/**
+  @page SPI_HalfDuplex_ComPollingIT_Master SPI Half Duplex IT example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    SPI/SPI_HalfDuplex_ComPollingIT_Master/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the SPI Half Duplex IT example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+Data buffer transmission/reception between 
+two boards via SPI using Polling (LL driver) and Interrupt modes (HAL driver).
+
+   _________________________                        _________________________
+  |       ___________ ______|                      |__________________       |
+  |      |SPI1              |                      |             SPI1 |      |
+  |      |                  |                      |                  |      |
+  |      |         CLK(PA5) |______________________|(PA5)CLK          |      |
+  |      |                  |                      |                  |      |
+  |      |         MISO(PA6)|          ____________|(PA6)MISO         |      |
+  |      |                  |          |           |                  |      |
+  |      |         MOSI(PA7)|__________|           |(PA7)MOSI         |      |
+  |      |                  |                      |                  |      |
+  |      |__________________|                      |__________________|      |
+  |      __                 |                      |                         |
+  |     |__|                |                      |                         |
+  |     USER                |                      |                         |
+  |                      GND|______________________|GND                      |
+  |                         |                      |                         |
+  |_STM32WBxx Master________|                      |_STM32WBxx Slave_________|
+
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz.
+
+The SPI peripheral configuration is ensured by the HAL_SPI_Init() function.
+This later is calling the HAL_SPI_MspInit()function which core is implementing
+the configuration of the needed SPI resources according to the used hardware (CLOCK & 
+GPIO). You may update this function to change SPI configuration.
+The Half-Duplex SPI transmission (8bit) is done using LL Driver on Master board (Tx) by using function 
+LL_SPI_TransmitData8.
+The The Half-Duplex SPI reception (8bit) is done using HAL Driver on Slave board (Rx) by using function 
+HAL_SPI_Receive_IT.
+
+Example execution:
+First step, press the User push-button (SW1), this action initiates a Half-Duplex transfer 
+between Master and Slave.
+After end of transfer, aRxBuffer and aTxBuffer are compared through Buffercmp() in order to 
+check buffers correctness.
+
+STM32 board's LEDs can be used to monitor the transfer status:
+ - LED1 toggles quickly on master board waiting User push-button (SW1) to be pressed.
+ - LED2 turns ON on slave board if reception is complete and OK.
+ - LED3 turns ON when there is an error in reception process. 
+
+@note You need to perform a reset on Slave board, then perform it on Master board
+      to have the correct behaviour of this example.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note The application need to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Directory contents 
+
+  - Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Inc/stm32wbxx_it.h          SPI interrupt handlers header file
+  - Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Inc/main.h                  Header for main.c module  
+  - Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/stm32wbxx_it.c          SPI interrupt handlers
+  - Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/main.c                  Main program
+  - Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/system_stm32wbxx.c      STM32WBxx system source file
+  - Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Master/Src/stm32wbxx_hal_msp.c     HAL MSP file    
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+
+  - Take care to cable connection between Master and Slave Board:
+    Cable shall be smaller than 5 cm and rigid if possible.
+
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+  - NUCLEO-WB35CE Set-up
+    - Connect Master board PA5 (CN10, pin 11) to Slave Board PA5 (CN10, pin 11)
+    - Connect Master board PA7 (CN10, pin 15) to Slave Board PA6 (CN10, pin 27)
+    - Connect Master board GND to Slave Board GND
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following:
+ - Open your preferred toolchain 
+ - Rebuild all files (master project) and load your image into target memory
+    o Load the project in Master Board
+ - Rebuild all files (slave project) and load your image into target memory
+    o Load the project in Slave Board
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
+ 
\ No newline at end of file
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/.extSettings b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/Project.eww
new file mode 100644
index 000000000..803fdd90a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\SPI_HalfDuplex_ComPollingIT_Slave.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/SPI_HalfDuplex_ComPollingIT_Slave.ewd b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/SPI_HalfDuplex_ComPollingIT_Slave.ewd
new file mode 100644
index 000000000..779533635
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/SPI_HalfDuplex_ComPollingIT_Slave.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		SPI_HalfDuplex_ComPollingIT_Slave
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/SPI_HalfDuplex_ComPollingIT_Slave.ewp b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/SPI_HalfDuplex_ComPollingIT_Slave.ewp
new file mode 100644
index 000000000..386cef1b6
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/SPI_HalfDuplex_ComPollingIT_Slave.ewp
@@ -0,0 +1,1125 @@
+
+
+  3
+  
+    SPI_HalfDuplex_ComPollingIT_Slave
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Inc/main.h
new file mode 100644
index 000000000..269648279
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Inc/main.h
@@ -0,0 +1,73 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_HalfDuplex_ComPollingIT_Slave/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+#include "stm32wbxx_ll_spi.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+#define COUNTOF(__BUFFER__)   (sizeof(__BUFFER__) / sizeof(*(__BUFFER__)))
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+/* Size of buffer */
+#define BUFFERSIZE                       (COUNTOF(aTxBuffer) - 1)
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..afd5aac3b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+#define HAL_SPI_MODULE_ENABLED
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..1770fd33a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Inc/stm32wbxx_it.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_HalfDuplex_ComPollingIT_Slave/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void SPI1_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/MDK-ARM/SPI_HalfDuplex_ComPollingIT_Slave.uvoptx b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/MDK-ARM/SPI_HalfDuplex_ComPollingIT_Slave.uvoptx
new file mode 100644
index 000000000..14dfaa56f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/MDK-ARM/SPI_HalfDuplex_ComPollingIT_Slave.uvoptx
@@ -0,0 +1,521 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    SPI_HalfDuplex_ComPollingIT_Slave
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+      stm32wbxx_hal_spi.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+      stm32wbxx_hal_spi_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      24
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/MDK-ARM/SPI_HalfDuplex_ComPollingIT_Slave.uvprojx b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/MDK-ARM/SPI_HalfDuplex_ComPollingIT_Slave.uvprojx
new file mode 100644
index 000000000..fc7101fde
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/MDK-ARM/SPI_HalfDuplex_ComPollingIT_Slave.uvprojx
@@ -0,0 +1,551 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      SPI_HalfDuplex_ComPollingIT_Slave
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          SPI_HalfDuplex_ComPollingIT_Slave\
+          SPI_HalfDuplex_ComPollingIT_Slave
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_spi.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+            
+            
+              stm32wbxx_hal_spi_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/SPI_HalfDuplex_ComPollingIT_Slave.ioc b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/SPI_HalfDuplex_ComPollingIT_Slave.ioc
new file mode 100644
index 000000000..99fd7faaf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/SPI_HalfDuplex_ComPollingIT_Slave.ioc
@@ -0,0 +1,134 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SPI1
+Mcu.IP3=SYS
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA5
+Mcu.Pin1=PA6
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SPI1_IRQn=true\:1\:0\:false\:false\:true\:true\:true
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA5.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA5.GPIO_PuPd=GPIO_PULLDOWN
+PA5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA5.Locked=true
+PA5.Mode=Simplex_Bidirectional_Slave
+PA5.Signal=SPI1_SCK
+PA6.GPIOParameters=GPIO_ModeDefaultPP,GPIO_Speed,GPIO_PuPd
+PA6.GPIO_ModeDefaultPP=GPIO_MODE_AF_PP
+PA6.GPIO_PuPd=GPIO_PULLDOWN
+PA6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA6.Mode=Simplex_Bidirectional_Slave
+PA6.Signal=SPI1_MISO
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=SPI_HalfDuplex_ComPollingIT_Slave.ioc
+ProjectManager.ProjectName=SPI_HalfDuplex_ComPollingIT_Slave
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_SPI1_Init-SPI1-false-HAL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SPI1.CLKPhase=SPI_PHASE_1EDGE
+SPI1.CLKPolarity=SPI_POLARITY_LOW
+SPI1.CRCCalculation=SPI_CRCCALCULATION_DISABLE
+SPI1.DataSize=SPI_DATASIZE_8BIT
+SPI1.Direction=SPI_DIRECTION_1LINE
+SPI1.FirstBit=SPI_FIRSTBIT_MSB
+SPI1.GPIO_SPEED=GPIO_SPEED_FREQ_HIGH
+SPI1.IPParameters=TIMode,DataSize,FirstBit,CLKPolarity,CLKPhase,CRCCalculation,NSS,VirtualType,Mode,Direction,GPIO_SPEED
+SPI1.Mode=SPI_MODE_SLAVE
+SPI1.NSS=SPI_NSS_SOFT
+SPI1.TIMode=SPI_TIMODE_DISABLE
+SPI1.VirtualType=VM_SLAVE
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..4e3d90dbd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/.cproject
@@ -0,0 +1,170 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/.project
new file mode 100644
index 000000000..110b445c9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/.project
@@ -0,0 +1,155 @@
+
+
+	SPI_HalfDuplex_ComPollingIT_Slave
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			SPI_HalfDuplex_ComPollingIT_Slave.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/SPI_HalfDuplex_ComPollingIT_Slave.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_spi.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_spi_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/main.c
new file mode 100644
index 000000000..476d30aee
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/main.c
@@ -0,0 +1,365 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use STM32WBxx SPI HAL API to transmit
+  *          and receive a data buffer with a communication process based on
+  *          Interrupt transfer.
+  *          The communication is done using 2 Boards.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+enum {
+	TRANSFER_WAIT,
+	TRANSFER_COMPLETE,
+	TRANSFER_ERROR
+};
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+SPI_HandleTypeDef hspi1;
+
+/* USER CODE BEGIN PV */
+/* Buffer used for transmission */
+uint8_t aTxBuffer[] = "**** SPI - Two Boards communication based on Polling (LL driver) for Master Board and Interrupt (HAL Driver) for Slave Board ****";
+
+/* Buffer used for reception */
+uint8_t aRxBuffer[BUFFERSIZE];
+
+/* transfer state */
+__IO uint32_t wTransferState = TRANSFER_WAIT;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_SPI1_Init(void);
+/* USER CODE BEGIN PFP */
+static uint16_t Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_SPI1_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* Configure LED1, LED2 and LED3 */
+  BSP_LED_Init(LED1);
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+
+
+
+  /*##-1- Start the Half Duplex Communication process ########################*/  
+  /* While the SPI in Receive process, user can receive data through "aRxBuffer" */
+  if(HAL_SPI_Receive_IT(&hspi1, (uint8_t *)aRxBuffer, BUFFERSIZE) != HAL_OK)
+  {
+    /* Transfer error in transmission process */
+    Error_Handler();
+  }
+
+  /*##-2- Wait for the end of the transfer ###################################*/  
+  /*  Before starting a new communication transfer, you must wait the callback call 
+      to get the transfer complete confirmation or an error detection.
+      For simplicity reasons, this example is just waiting till the end of the 
+      transfer, but application may perform other tasks while transfer operation
+      is ongoing. */  
+  while (wTransferState == TRANSFER_WAIT)
+  {
+  }
+  
+  switch(wTransferState)
+  {
+    case TRANSFER_COMPLETE :
+      /*##-4- Compare the sent and received buffers ##############################*/
+      if(Buffercmp((uint8_t*)aTxBuffer, (uint8_t*)aRxBuffer, BUFFERSIZE))
+      {
+        /* Processing Error */
+        Error_Handler();     
+      }
+      else
+      {
+        BSP_LED_On(LED2);
+      }
+    break;
+    default : 
+      Error_Handler();
+    break;
+  }
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief SPI1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SPI1_Init(void)
+{
+
+  /* USER CODE BEGIN SPI1_Init 0 */
+
+  /* USER CODE END SPI1_Init 0 */
+
+  /* USER CODE BEGIN SPI1_Init 1 */
+
+  /* USER CODE END SPI1_Init 1 */
+  /* SPI1 parameter configuration*/
+  hspi1.Instance = SPI1;
+  hspi1.Init.Mode = SPI_MODE_SLAVE;
+  hspi1.Init.Direction = SPI_DIRECTION_1LINE;
+  hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
+  hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
+  hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
+  hspi1.Init.NSS = SPI_NSS_SOFT;
+  hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
+  hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
+  hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+  hspi1.Init.CRCPolynomial = 7;
+  hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
+  hspi1.Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
+  if (HAL_SPI_Init(&hspi1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN SPI1_Init 2 */
+
+  /* USER CODE END SPI1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+/**
+  * @brief  Compares two buffers.
+  * @param  pBuffer1, pBuffer2: buffers to be compared.
+  * @param  BufferLength: buffer's length
+  * @retval 0  : pBuffer1 identical to pBuffer2
+  *         >0 : pBuffer1 differs from pBuffer2
+  */
+static uint16_t Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
+{
+  while (BufferLength--)
+  {
+    if((*pBuffer1) != *pBuffer2)
+    {
+      return BufferLength;
+    }
+    pBuffer1++;
+    pBuffer2++;
+  }
+
+  return 0;
+}
+
+/******************************************************************************/
+/*   USER IRQ HANDLER TREATMENT                                               */
+/******************************************************************************/
+
+/**
+  * @brief  Tx Transfer completed callback.
+  * @param  hspi: SPI handle
+  * @note   This example shows a simple way to report end of Interrupt Tx transfer, and 
+  *         you can add your own implementation. 
+  * @retval None
+  */
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Transfer in reception process is complete */
+  wTransferState = TRANSFER_COMPLETE;
+}
+
+/**
+  * @brief  SPI error callbacks.
+  * @param  hspi: SPI handle
+  * @note   This example shows a simple way to report transfer error, and you can
+  *         add your own implementation.
+  * @retval None
+  */
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+{
+  wTransferState = TRANSFER_ERROR;
+}
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  while(1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..8c7bb4fee
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,154 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief SPI MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hspi->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspInit 0 */
+
+  /* USER CODE END SPI1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SPI1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**SPI1 GPIO Configuration    
+    PA5     ------> SPI1_SCK
+    PA6     ------> SPI1_MISO 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* SPI1 interrupt Init */
+    HAL_NVIC_SetPriority(SPI1_IRQn, 1, 0);
+    HAL_NVIC_EnableIRQ(SPI1_IRQn);
+  /* USER CODE BEGIN SPI1_MspInit 1 */
+
+  /* USER CODE END SPI1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief SPI MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
+{
+  if(hspi->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspDeInit 0 */
+    /* Reset peripherals */
+    __HAL_RCC_SPI1_FORCE_RESET();
+    __HAL_RCC_SPI1_RELEASE_RESET();
+
+  /* USER CODE END SPI1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SPI1_CLK_DISABLE();
+  
+    /**SPI1 GPIO Configuration    
+    PA5     ------> SPI1_SCK
+    PA6     ------> SPI1_MISO 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6);
+
+    /* SPI1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(SPI1_IRQn);
+  /* USER CODE BEGIN SPI1_MspDeInit 1 */
+
+  /* USER CODE END SPI1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..5fd099e1d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/stm32wbxx_it.c
@@ -0,0 +1,219 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern SPI_HandleTypeDef hspi1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles SPI1 global interrupt.
+  */
+void SPI1_IRQHandler(void)
+{
+  /* USER CODE BEGIN SPI1_IRQn 0 */
+
+  /* USER CODE END SPI1_IRQn 0 */
+  HAL_SPI_IRQHandler(&hspi1);
+  /* USER CODE BEGIN SPI1_IRQn 1 */
+
+  /* USER CODE END SPI1_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/readme.txt b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/readme.txt
new file mode 100644
index 000000000..d92ac5a1c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/readme.txt
@@ -0,0 +1,120 @@
+/**
+  @page SPI_HalfDuplex_ComPollingIT_Slave SPI Half Duplex IT example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    SPI/SPI_HalfDuplex_ComPollingIT_Slave/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the SPI Half Duplex IT example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+Data buffer transmission/reception between 
+two boards via SPI using Polling (LL driver) and Interrupt modes (HAL driver).
+
+   _________________________                        _________________________
+  |       ___________ ______|                      |__________________       |
+  |      |SPI1              |                      |             SPI1 |      |
+  |      |                  |                      |                  |      |
+  |      |         CLK(PA5) |______________________|(PA5)CLK          |      |
+  |      |                  |                      |                  |      |
+  |      |         MISO(PA6)|          ____________|(PA6)MISO         |      |
+  |      |                  |          |           |                  |      |
+  |      |         MOSI(PA7)|__________|           |(PA7)MOSI         |      |
+  |      |                  |                      |                  |      |
+  |      |__________________|                      |__________________|      |
+  |      __                 |                      |                         |
+  |     |__|                |                      |                         |
+  |     USER                |                      |                         |
+  |                      GND|______________________|GND                      |
+  |                         |                      |                         |
+  |_STM32WBxx Master________|                      |_STM32WBxx Slave_________|
+
+
+At the beginning of the main program the HAL_Init() function is called to reset 
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz.
+
+The SPI peripheral configuration is ensured by the HAL_SPI_Init() function.
+This later is calling the HAL_SPI_MspInit()function which core is implementing
+the configuration of the needed SPI resources according to the used hardware (CLOCK & 
+GPIO). You may update this function to change SPI configuration.
+The Half-Duplex SPI transmission (8bit) is done using LL Driver on Master board (Tx) by using function 
+LL_SPI_TransmitData8.
+The The Half-Duplex SPI reception (8bit) is done using HAL Driver on Slave board (Rx) by using function 
+HAL_SPI_Receive_IT.
+
+Example execution:
+First step, press the User push-button (SW1), this action initiates a Half-Duplex transfer 
+between Master and Slave.
+After end of transfer, aRxBuffer and aTxBuffer are compared through Buffercmp() in order to 
+check buffers correctness.
+
+STM32 board's LEDs can be used to monitor the transfer status:
+ - LED1 toggles quickly on master board waiting User push-button (SW1) to be pressed.
+ - LED2 turns ON on slave board if reception is complete and OK.
+ - LED3 turns ON when there is an error in reception process. 
+
+@note You need to perform a reset on Slave board, then perform it on Master board
+      to have the correct behaviour of this example.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note The application need to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Directory contents 
+
+  - Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Inc/stm32wbxx_it.h          SPI interrupt handlers header file
+  - Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Inc/main.h                  Header for main.c module  
+  - Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/stm32wbxx_it.c          SPI interrupt handlers
+  - Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/main.c                  Main program
+  - Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/system_stm32wbxx.c      STM32WBxx system source file
+  - Examples_MIX/SPI/SPI_HalfDuplex_ComPollingIT_Slave/Src/stm32wbxx_hal_msp.c     HAL MSP file    
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+
+  - Take care to cable connection between Master and Slave Board:
+    Cable shall be smaller than 5 cm and rigid if possible.
+
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+  - NUCLEO-WB35CE Set-up
+    - Connect Master board PA5 (CN10, pin 11) to Slave Board PA5 (CN10, pin 11)
+    - Connect Master board PA7 (CN10, pin 15) to Slave Board PA6 (CN10, pin 27)
+    - Connect Master board GND to Slave Board GND
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following:
+ - Open your preferred toolchain 
+ - Rebuild all files (master project) and load your image into target memory
+    o Load the project in Master Board
+ - Rebuild all files (slave project) and load your image into target memory
+    o Load the project in Slave Board
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
+ 
\ No newline at end of file
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/.extSettings b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/Project.eww
new file mode 100644
index 000000000..19604344f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\TIM_PWMInput.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewd b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewd
new file mode 100644
index 000000000..4ce078a32
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		TIM_PWMInput
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewp b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewp
new file mode 100644
index 000000000..1f36fc751
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/TIM_PWMInput.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    TIM_PWMInput
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Inc/main.h
new file mode 100644
index 000000000..5044e57c1
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Inc/main.h
@@ -0,0 +1,78 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    TIM/TIM_PWMInput/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_tim.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+void TimerCaptureCompare_Ch2_Callback(void);
+void UserButton_Callback(void);
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..3e4ba1426
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..d9c3f5934
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Inc/stm32wbxx_it.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    TIM/TIM_PWMInput/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+void TIM2_IRQHandler(void);
+void EXTI0_IRQHandler(void);
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvoptx b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvoptx
new file mode 100644
index 000000000..5f281db03
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    TIM_PWMInput
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvprojx b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvprojx
new file mode 100644
index 000000000..b5941a6aa
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/MDK-ARM/TIM_PWMInput.uvprojx
@@ -0,0 +1,541 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      TIM_PWMInput
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          TIM_PWMInput\
+          TIM_PWMInput
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..7d6d56e6c
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/.project
new file mode 100644
index 000000000..0d04fcea3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	TIM_PWMInput
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			TIM_PWMInput.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/TIM_PWMInput.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Src/main.c
new file mode 100644
index 000000000..3add6ad24
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Src/main.c
@@ -0,0 +1,462 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    TIM/TIM_PWMInput/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This example shows how to use the TIM peripheral to measure the
+  *          frequency and duty cycle of an external signal.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* Number of frequencies */
+#define TIM_FREQUENCIES_NB 6
+#define TIM_DUTYCYCLE_NB 2
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+TIM_HandleTypeDef htim1;
+TIM_HandleTypeDef htim2;
+
+/* USER CODE BEGIN PV */
+
+/* Captured Value */
+__IO uint32_t            uwIC2Value = 0;
+/* Duty Cycle Value */
+__IO uint32_t            uwDutyCycle = 0;
+/* Frequency Value */
+__IO uint32_t            uwFrequency = 0;
+
+/* Counter Prescaler value */
+uint32_t uhPrescalerValue = 0;
+
+static uint8_t iFrequency = 0;
+/* Frequency index *//* Frequency table */
+static uint32_t aFrequency[TIM_FREQUENCIES_NB] = {
+  2000,   /*  2 kHz */
+  2000,   /*  2 kHz */
+  3000,   /*  3 kHz */
+  3000,   /*  3 kHz */
+  4000,   /*  4 kHz */
+  4000,   /*  4 kHz */
+};
+/* Frequency index */
+
+static uint8_t iDutyCycle = 0;
+static uint32_t aDutyCycle[TIM_DUTYCYCLE_NB] = {
+  2,   /*  50% */
+  4,   /*  25% */
+};
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_TIM2_Init(void);
+static void MX_TIM1_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* Configure LED3 */
+  BSP_LED_Init(LED3);
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* Configure User push-button in Interrupt mode */
+  BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_TIM2_Init();
+  MX_TIM1_Init();
+  /* USER CODE BEGIN 2 */
+
+ /* Start Input waveform generation */
+  if (HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1) != HAL_OK)
+  {
+    /* PWM Generation Error */
+    Error_Handler();
+  }
+
+  /* Start the Input Capture in interrupt mode  */
+  if (HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_2) != HAL_OK)
+  {
+    /* Starting Error */
+    Error_Handler();
+  }
+
+  if (HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_1) != HAL_OK)
+  {
+    /* Starting Error */
+    Error_Handler();
+  }
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief TIM1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM1_Init(void)
+{
+
+  /* USER CODE BEGIN TIM1_Init 0 */
+
+  /* USER CODE END TIM1_Init 0 */
+
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+  TIM_OC_InitTypeDef sConfigOC = {0};
+  TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
+
+  /* USER CODE BEGIN TIM1_Init 1 */
+
+  /* USER CODE END TIM1_Init 1 */
+  htim1.Instance = TIM1;
+  htim1.Init.Prescaler = uhPrescalerValue;
+  htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim1.Init.Period = (SystemCoreClock/1)/aFrequency[0];
+  htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim1.Init.RepetitionCounter = 0;
+  htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigOC.OCMode = TIM_OCMODE_PWM1;
+  sConfigOC.Pulse = ((SystemCoreClock/1)/aFrequency[0])/aDutyCycle[0];
+  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+  sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
+  sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
+  sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+  if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
+  sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
+  sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
+  sBreakDeadTimeConfig.DeadTime = 0;
+  sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
+  sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
+  sBreakDeadTimeConfig.BreakFilter = 0;
+  sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
+  sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
+  sBreakDeadTimeConfig.Break2Filter = 0;
+  sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
+  if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM1_Init 2 */
+
+  /* USER CODE END TIM1_Init 2 */
+  HAL_TIM_MspPostInit(&htim1);
+
+}
+
+/**
+  * @brief TIM2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM2_Init(void)
+{
+
+  /* USER CODE BEGIN TIM2_Init 0 */
+
+  /* USER CODE END TIM2_Init 0 */
+
+  TIM_SlaveConfigTypeDef sSlaveConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+  TIM_IC_InitTypeDef sConfigIC = {0};
+
+  /* USER CODE BEGIN TIM2_Init 1 */
+
+  /* USER CODE END TIM2_Init 1 */
+  htim2.Instance = TIM2;
+  htim2.Init.Prescaler = 0x0;
+  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim2.Init.Period = 0xFFFF;
+  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_TIM_IC_Init(&htim2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sSlaveConfig.SlaveMode = TIM_SLAVEMODE_RESET;
+  sSlaveConfig.InputTrigger = TIM_TS_TI2FP2;
+  sSlaveConfig.TriggerPolarity = TIM_INPUTCHANNELPOLARITY_RISING;
+  sSlaveConfig.TriggerFilter = 0;
+  if (HAL_TIM_SlaveConfigSynchro(&htim2, &sSlaveConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_FALLING;
+  sConfigIC.ICSelection = TIM_ICSELECTION_INDIRECTTI;
+  sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;
+  sConfigIC.ICFilter = 0;
+  if (HAL_TIM_IC_ConfigChannel(&htim2, &sConfigIC, TIM_CHANNEL_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING;
+  sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;
+  if (HAL_TIM_IC_ConfigChannel(&htim2, &sConfigIC, TIM_CHANNEL_2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM2_Init 2 */
+
+  /* USER CODE END TIM2_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief EXTI line detection callbacks
+  * @param GPIO_Pin: Specifies the pins connected EXTI line
+  * @retval None
+  */
+void UserButton_Callback()
+{
+    /* Set new PWM signal frequency and duty cycle*/
+    iFrequency = (iFrequency + 1) % TIM_FREQUENCIES_NB;
+    iDutyCycle = (iDutyCycle + 1) % TIM_DUTYCYCLE_NB;
+
+    /* Set the auto-reload value to have the requested frequency */
+    /* Frequency = TIM1CLK / (ARR + 1) = SystemCoreClock / (ARR + 1)  */
+    LL_TIM_SetAutoReload(TIM1, __LL_TIM_CALC_ARR(SystemCoreClock/1, LL_TIM_GetPrescaler(TIM1), aFrequency[iFrequency]));
+ 
+    /* Set  duty cycle */
+    LL_TIM_OC_SetCompareCH1(TIM1, (LL_TIM_GetAutoReload(TIM1) / aDutyCycle[iDutyCycle]));	
+
+}
+
+/**
+  * @brief  Input Capture callback in non blocking mode 
+  * @param  htim : TIM IC handle
+  * @retval None
+  */
+void TimerCaptureCompare_Ch2_Callback()
+{
+  /* Get the Input Capture value */
+  uwIC2Value = LL_TIM_IC_GetCaptureCH2(TIM2);
+
+  if (uwIC2Value != 0)
+  {
+    /* Duty cycle computation */
+    uwDutyCycle = (LL_TIM_IC_GetCaptureCH1(TIM2) * 100) / uwIC2Value;
+
+    /* uwFrequency computation
+    TIM2 freq  = SystemCoreClock */
+    uwFrequency = SystemCoreClock  / (1*uwIC2Value);
+  }
+  else
+  {
+    uwDutyCycle = 0;
+    uwFrequency = 0;
+  }
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  /* Turn LED3 on */
+  BSP_LED_On(LED3);
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..9d0524ef5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,223 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    TIM/TIM_PWMInput/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+                        
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+                    /**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief TIM_PWM MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_pwm: TIM_PWM handle pointer
+* @retval None
+*/
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
+{
+  if(htim_pwm->Instance==TIM1)
+  {
+  /* USER CODE BEGIN TIM1_MspInit 0 */
+
+  /* USER CODE END TIM1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM1_CLK_ENABLE();
+  /* USER CODE BEGIN TIM1_MspInit 1 */
+
+  /* USER CODE END TIM1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief TIM_Base MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(htim_base->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspInit 0 */
+
+  /* USER CODE END TIM2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM2_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**TIM2 GPIO Configuration    
+    PA1     ------> TIM2_CH2 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_1;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN TIM2_MspInit 1 */
+
+    /* TIM2 interrupt Init */
+    HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(TIM2_IRQn);
+
+  /* USER CODE END TIM2_MspInit 1 */
+  }
+
+}
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(htim->Instance==TIM1)
+  {
+  /* USER CODE BEGIN TIM1_MspPostInit 0 */
+
+  /* USER CODE END TIM1_MspPostInit 0 */
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**TIM1 GPIO Configuration    
+    PA8     ------> TIM1_CH1 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_8;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN TIM1_MspPostInit 1 */
+
+  /* USER CODE END TIM1_MspPostInit 1 */
+  }
+
+}
+/**
+* @brief TIM_PWM MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_pwm: TIM_PWM handle pointer
+* @retval None
+*/
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm)
+{
+  if(htim_pwm->Instance==TIM1)
+  {
+  /* USER CODE BEGIN TIM1_MspDeInit 0 */
+
+  /* USER CODE END TIM1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM1_CLK_DISABLE();
+  /* USER CODE BEGIN TIM1_MspDeInit 1 */
+
+  /* USER CODE END TIM1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief TIM_Base MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
+{
+  if(htim_base->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspDeInit 0 */
+
+  /* USER CODE END TIM2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM2_CLK_DISABLE();
+  
+    /**TIM2 GPIO Configuration    
+    PA1     ------> TIM2_CH2 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1);
+
+  /* USER CODE BEGIN TIM2_MspDeInit 1 */
+
+    /* TIM2 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(TIM2_IRQn);
+
+  /* USER CODE END TIM2_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..217b4f031
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Src/stm32wbxx_it.c
@@ -0,0 +1,215 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    TIM/TIM_PWMInput/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/**
+* @brief  This function handles TIM2 capture/compare interrupt.
+* @param  None
+* @retval None
+*/
+void TIM2_IRQHandler(void)
+{
+  /* Check whether CC2 interrupt is pending */
+  /* It is sufficient to callback just on one front (either rising or falling) */
+  if(LL_TIM_IsActiveFlag_CC2(TIM2) == 1)
+  {
+    /* Clear the update interrupt flag*/
+    LL_TIM_ClearFlag_CC2(TIM2);
+
+    /* TIM2 capture/compare interrupt processing(function defined in main.c) */
+    TimerCaptureCompare_Ch2_Callback();
+  }
+}
+
+/**
+  * @brief  This function handles external line 0 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void)
+{
+  /* Manage Flags */
+  if(LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
+  {
+    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
+
+    /* User button interrupt processing(function defined in main.c) */
+    UserButton_Callback(); 
+  }
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/TIM_PWMInput.ioc b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/TIM_PWMInput.ioc
new file mode 100644
index 000000000..31602fea5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/TIM_PWMInput.ioc
@@ -0,0 +1,173 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=TIM1
+Mcu.IP4=TIM2
+Mcu.IPNb=5
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PA1
+Mcu.Pin1=PA8
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.Pin3=VP_TIM2_VS_ControllerModeReset
+Mcu.PinsNb=4
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA1.Signal=S_TIM2_CH2
+PA8.Signal=S_TIM1_CH1
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=3
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=TIM_PWMInput.ioc
+ProjectManager.ProjectName=TIM_PWMInput
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-true,3-MX_TIM2_Init-TIM2-false-HAL-true,4-MX_TIM1_Init-TIM1-false-HAL-true
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+SH.S_TIM1_CH1.0=TIM1_CH1,PWM Generation1 CH1
+SH.S_TIM1_CH1.ConfNb=1
+SH.S_TIM2_CH2.0=TIM2_CH2,TriggerSource_TI2FP2
+SH.S_TIM2_CH2.1=TIM2_CH2,Input_Capture2_from_TI2
+SH.S_TIM2_CH2.2=TIM2_CH2,Input_Capture1_from_TI2
+SH.S_TIM2_CH2.ConfNb=3
+TIM1.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_DISABLE
+TIM1.AutomaticOutput=TIM_AUTOMATICOUTPUT_DISABLE
+TIM1.Break2Filter=0
+TIM1.Break2Polarity=TIM_BREAK2POLARITY_HIGH
+TIM1.Break2State=TIM_BREAK2_DISABLE
+TIM1.BreakFilter=0
+TIM1.BreakPolarity=TIM_BREAKPOLARITY_HIGH
+TIM1.BreakState=TIM_BREAK_DISABLE
+TIM1.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
+TIM1.ClearInputSource=TIM_CLEARINPUTSOURCE_NONE
+TIM1.ClockDivision=TIM_CLOCKDIVISION_DIV1
+TIM1.CounterMode=TIM_COUNTERMODE_UP
+TIM1.IPParameters=Prescaler,CounterMode,Period,ClockDivision,RepetitionCounter,AutoReloadPreload,TIM_MasterSlaveMode,TIM_MasterOutputTrigger,TIM_MasterOutputTrigger2,BreakState,BreakPolarity,BreakFilter,SourceBRKDigInput,SourceBRKCOMP1,SourceBRKCOMP2,Break2State,Break2Polarity,Break2Filter,SourceBRK2DigInput,SourceBRK2COMP1,SourceBRK2COMP2,AutomaticOutput,OffStateRunMode,OffStateIDLEMode,LockLevel,ClearInputSource,OCMode_PWM-PWM Generation1 CH1,Pulse-PWM Generation1 CH1,OC1Preload_PWM,OCFastMode_PWM-PWM Generation1 CH1,OCPolarity_1,OCIdleState_1,Channel-PWM Generation1 CH1
+TIM1.IPParametersWithoutCheck=Pulse-PWM Generation1 CH1,Prescaler,Period
+TIM1.LockLevel=TIM_LOCKLEVEL_OFF
+TIM1.OC1Preload_PWM=ENABLE
+TIM1.OCFastMode_PWM-PWM\ Generation1\ CH1=TIM_OCFAST_DISABLE
+TIM1.OCIdleState_1=TIM_OCIDLESTATE_RESET
+TIM1.OCMode_PWM-PWM\ Generation1\ CH1=TIM_OCMODE_PWM1
+TIM1.OCPolarity_1=TIM_OCPOLARITY_HIGH
+TIM1.OffStateIDLEMode=TIM_OSSI_DISABLE
+TIM1.OffStateRunMode=TIM_OSSR_DISABLE
+TIM1.Period=(SystemCoreClock/1)/aFrequency[0]
+TIM1.Prescaler=uhPrescalerValue
+TIM1.Pulse-PWM\ Generation1\ CH1=((SystemCoreClock/1)/aFrequency[0])/aDutyCycle[0]
+TIM1.RepetitionCounter=0
+TIM1.SourceBRK2COMP1=TIM_BREAKINPUTSOURCE_DISABLE
+TIM1.SourceBRK2COMP2=TIM_BREAKINPUTSOURCE_DISABLE
+TIM1.SourceBRK2DigInput=TIM_BREAKINPUTSOURCE_DISABLE
+TIM1.SourceBRKCOMP1=TIM_BREAKINPUTSOURCE_DISABLE
+TIM1.SourceBRKCOMP2=TIM_BREAKINPUTSOURCE_DISABLE
+TIM1.SourceBRKDigInput=TIM_BREAKINPUTSOURCE_DISABLE
+TIM1.TIM_MasterOutputTrigger=TIM_TRGO_RESET
+TIM1.TIM_MasterOutputTrigger2=TIM_TRGO2_RESET
+TIM1.TIM_MasterSlaveMode=TIM_MASTERSLAVEMODE_DISABLE
+TIM2.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_DISABLE
+TIM2.Channel-Input_Capture1_from_TI2=TIM_CHANNEL_1
+TIM2.Channel-Input_Capture2_from_TI2=TIM_CHANNEL_2
+TIM2.ClockDivision=TIM_CLOCKDIVISION_DIV1
+TIM2.CounterMode=TIM_COUNTERMODE_UP
+TIM2.ICFilter_CH2=0
+TIM2.ICPolarity_CH1=TIM_INPUTCHANNELPOLARITY_FALLING
+TIM2.ICPolarity_CH2=TIM_INPUTCHANNELPOLARITY_RISING
+TIM2.ICPrescaler-Input_Capture1_from_TI2=TIM_ICPSC_DIV1
+TIM2.ICPrescaler-Input_Capture2_from_TI2=TIM_ICPSC_DIV1
+TIM2.ICSelection-Input_Capture1_from_TI2=TIM_ICSELECTION_INDIRECTTI
+TIM2.ICSelection-Input_Capture2_from_TI2=TIM_ICSELECTION_DIRECTTI
+TIM2.IPParameters=Prescaler,CounterMode,Period,ClockDivision,AutoReloadPreload,TIM_MasterSlaveMode,TIM_MasterOutputTrigger,TIM_SlaveMode,ICPolarity_CH1,ICSelection-Input_Capture1_from_TI2,ICPrescaler-Input_Capture1_from_TI2,ICPolarity_CH2,ICSelection-Input_Capture2_from_TI2,ICPrescaler-Input_Capture2_from_TI2,ICFilter_CH2,Channel-Input_Capture1_from_TI2,Channel-Input_Capture2_from_TI2
+TIM2.Period=0xFFFF
+TIM2.Prescaler=0x0
+TIM2.TIM_MasterOutputTrigger=TIM_TRGO_RESET
+TIM2.TIM_MasterSlaveMode=TIM_MASTERSLAVEMODE_DISABLE
+TIM2.TIM_SlaveMode=TIM_SLAVEMODE_RESET
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+VP_TIM2_VS_ControllerModeReset.Mode=Reset Mode
+VP_TIM2_VS_ControllerModeReset.Signal=TIM2_VS_ControllerModeReset
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/readme.txt b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/readme.txt
new file mode 100644
index 000000000..062b19569
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/TIM/TIM_PWMInput/readme.txt
@@ -0,0 +1,92 @@
+/**
+  @page TIM_PWMInput TIM PWM Input example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    TIM/TIM_PWMInput/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the TIM PWM_Input example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description 
+
+Use of the TIM peripheral to measure an external signal frequency and 
+duty cycle.
+
+The TIM2CLK frequency is set to SystemCoreClock/1 (Hz), the Prescaler is 0 so the 
+counter clock is SystemCoreClock/1 (Hz).
+
+TIM2 is configured in PWM Input Mode: the external signal is connected to 
+TIM2 Channel2 used as input pin.
+To measure the frequency and the duty cycle, we use the TIM2 CC2 interrupt request,
+so in the TIM2_IRQHandler routine, the frequency and the duty cycle of the external 
+signal are computed.
+
+"uwFrequency" variable contains the external signal frequency:
+TIM2 counter clock = SystemCoreClock/1,
+uwFrequency = TIM2 counter clock / TIM2_CCR2 in Hz, 
+
+"uwDutyCycle" variable contains the external signal duty cycle:
+uwDutyCycle = (TIM2_CCR1*100)/(TIM2_CCR2) in %.
+
+The minimum frequency value to measure is (TIM2 counter clock / CCR MAX)
+                                         = (64 MHz/1)/ 65535
+                                         = 915,5 Hz
+
+TIM1 can be used to generate the external signal in case a function generator 
+is not available. TIM1 is configured in PWM Output Mode to produce a square wave on PA8.
+Frequency and duty cycles can be changed by pressing the User Button (PC13).
+Six combinations are available (see tables aFrequency[] and aDutyCycle[]).
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application need to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Directory contents 
+
+  - TIM/TIM_PWMInput/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - TIM/TIM_PWMInput/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - TIM/TIM_PWMInput/Inc/main.h                  Header for main.c module  
+  - TIM/TIM_PWMInput/Src/stm32wbxx_it.c          Interrupt handlers
+  - TIM/TIM_PWMInput/Src/main.c                  Main program
+  - TIM/TIM_PWMInput/Src/stm32wbxx_hal_msp.c     HAL MSP file
+  - TIM/TIM_PWMInput/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE 
+    board and can be easily tailored to any other supported device 
+    and development board.
+
+  - NUCLEO-WB35CE Set-up
+    - You can either Connect the external signal to measure to the TIM2 CH2 pin (PA1) (pin 32 in CN7 connector).
+    - Or connect TIM1 CH1 pin PA8 (pin 25 in CN10 connector) to the TIM2 CH2 pin (PA1) instead of an external signal.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/.extSettings b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/.extSettings
new file mode 100644
index 000000000..87360f460
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/Project.eww
new file mode 100644
index 000000000..79e40fb7a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\UART_HyperTerminal_IT.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/UART_HyperTerminal_IT.ewd b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/UART_HyperTerminal_IT.ewd
new file mode 100644
index 000000000..ea06f2738
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/UART_HyperTerminal_IT.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		UART_HyperTerminal_IT
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/UART_HyperTerminal_IT.ewp b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/UART_HyperTerminal_IT.ewp
new file mode 100644
index 000000000..9630dc088
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/UART_HyperTerminal_IT.ewp
@@ -0,0 +1,1125 @@
+
+
+  3
+  
+    UART_HyperTerminal_IT
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Inc/main.h b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Inc/main.h
new file mode 100644
index 000000000..2a1648161
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Inc/main.h
@@ -0,0 +1,88 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_HyperTerminal_IT/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_gpio.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_usart.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+#define COUNTOF(__BUFFER__)   (sizeof(__BUFFER__) / sizeof(*(__BUFFER__)))
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+/* IRQ Handler treatment functions */
+void UART_CharReception_Callback(void); 
+void UART_TXEmpty_Callback(void); 
+void UART_CharTransmitComplete_Callback(void); 
+void UART_Error_Callback(void); 
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+/* Size of Transmission buffer */
+#define TXSTARTMESSAGESIZE                   (COUNTOF(aTxStartMessage) - 1)
+#define TXENDMESSAGESIZE                     (COUNTOF(aTxEndMessage) - 1)
+
+/* Size of Reception buffer */
+#define RXBUFFERSIZE                      10
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..7353fcbbb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..d81983b71
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_HyperTerminal_IT/Inc/stm32wbxx_it.c
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void USART1_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/MDK-ARM/UART_HyperTerminal_IT.uvoptx b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/MDK-ARM/UART_HyperTerminal_IT.uvoptx
new file mode 100644
index 000000000..55b50a1e3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/MDK-ARM/UART_HyperTerminal_IT.uvoptx
@@ -0,0 +1,521 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    UART_HyperTerminal_IT
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      0
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      3
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      3
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      3
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      5
+      6
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      6
+      7
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      6
+      8
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      6
+      9
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      6
+      10
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+      stm32wbxx_hal_uart.c
+      0
+      0
+    
+    
+      6
+      11
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+      stm32wbxx_hal_uart_ex.c
+      0
+      0
+    
+    
+      6
+      12
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      6
+      13
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      6
+      17
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      6
+      18
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      6
+      19
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      6
+      20
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      6
+      21
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      7
+      24
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/MDK-ARM/UART_HyperTerminal_IT.uvprojx b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/MDK-ARM/UART_HyperTerminal_IT.uvprojx
new file mode 100644
index 000000000..9c492e2f7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/MDK-ARM/UART_HyperTerminal_IT.uvprojx
@@ -0,0 +1,551 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      UART_HyperTerminal_IT
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          UART_HyperTerminal_IT\
+          UART_HyperTerminal_IT
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../../../Drivers/CMSIS/Include;../../../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          ::CMSIS
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_uart.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+            
+            
+              stm32wbxx_hal_uart_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..8eecdbc91
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/.project
new file mode 100644
index 000000000..a0859122a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/.project
@@ -0,0 +1,155 @@
+
+
+	UART_HyperTerminal_IT
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			UART_HyperTerminal_IT.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/UART_HyperTerminal_IT.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart_ex.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-6-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Src/main.c b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Src/main.c
new file mode 100644
index 000000000..890cc02c5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Src/main.c
@@ -0,0 +1,424 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_HyperTerminal_IT/Src/main.c
+  * @author  MCD Application Team
+  * @brief   This sample code shows how to use UART HAL and LL APIs to transmit
+  *          and receive a data buffer with a communication process based on IT;
+  *          The communication is done with the Hyperterminal PC application;
+  *          HAL driver is used to perform UART configuration, 
+  *          then TX/RX transfers procedures are based on LL APIs use
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef huart1;
+
+/* USER CODE BEGIN PV */
+
+/* UART handler declaration */
+UART_HandleTypeDef UartHandle;
+__IO uint8_t  ubTxComplete = 0;
+__IO uint8_t  ubRxComplete = 0;
+
+/* Buffer used for transmission */
+uint8_t aTxStartMessage[] = "\n\r ****UART-Hyperterminal communication based on IT (Mixed HAL/LL usage) ****\n\r Enter 10 characters using keyboard :\n\r";
+__IO uint32_t uwTxIndex = 0;
+uint8_t ubSizeToSend = sizeof(aTxStartMessage);
+uint8_t aTxEndMessage[] = "\n\r Example Finished\n\r";
+
+/* Buffer used for reception */
+uint8_t aRxBuffer[RXBUFFERSIZE];
+__IO uint32_t uwRxIndex = 0;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_USART1_UART_Init(void);
+/* USER CODE BEGIN PFP */
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+/* STM32WBxx HAL library initialization:
+       - Configure the Flash prefetch
+       - Systick timer is configured by default as source of time base, but user 
+         can eventually implement his proper time base source (a general purpose 
+         timer for example or other time source), keeping in mind that Time base 
+         duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+         handled in milliseconds basis.
+       - Set NVIC Group Priority to 4
+       - Low Level Initialization
+     */
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+  /* Configure leds */
+  BSP_LED_Init(LED1);
+  BSP_LED_Init(LED2);
+  BSP_LED_Init(LED3);
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_USART1_UART_Init();
+  /* USER CODE BEGIN 2 */
+
+  /*## Configure UART peripheral for reception process (using LL) ##########*/  
+  /* Any data received will be stored "aRxBuffer" buffer : the number max of 
+     data received is RXBUFFERSIZE */
+  /* Enable RXNE and Error interrupts */  
+  LL_USART_EnableIT_RXNE(USART1);
+  LL_USART_EnableIT_ERROR(USART1);
+
+  /*## Start the transmission process (using LL) *##########################*/  
+  /* While the UART in reception process, user can transmit data from 
+     "aTxStartMessage" buffer */
+  /* Start USART transmission : Will initiate TXE interrupt after TDR register is empty */
+  LL_USART_TransmitData8(USART1, aTxStartMessage[uwTxIndex++]); 
+
+  /* Enable TXE interrupt */
+  LL_USART_EnableIT_TXE(USART1); 
+
+  /*## Wait for the end of the transfer ###################################*/
+  /* USART IRQ handler is not anymore routed to HAL_UART_IRQHandler() function 
+     and is now based on LL API functions use. 
+     Therefore, use of HAL IT based services is no more possible. */
+  /*  Once TX transfer is completed, LED1 will turn On.
+      Then, when RX transfer is completed, LED2 will turn On. */
+  while (ubTxComplete == 0)
+  {
+  }
+  BSP_LED_On(LED1);
+   
+  while (ubRxComplete == 0)
+  {
+  }
+  BSP_LED_On(LED2);
+
+
+  /*## Send the received Buffer ###########################################*/
+  /* Even if use of HAL IT based services is no more possible, use of HAL Polling based services
+     (as Transmit in polling mode) is still possible. */
+  if(HAL_UART_Transmit(&huart1, (uint8_t*)aRxBuffer, RXBUFFERSIZE, 1000)!= HAL_OK)
+  {
+    /* Transfer error in transmission process */
+    Error_Handler();
+  }
+  
+  /*## Send the End Message ###############################################*/  
+  if(HAL_UART_Transmit(&huart1, (uint8_t*)aTxEndMessage, TXENDMESSAGESIZE, 1000)!= HAL_OK)
+  {
+    /* Transfer error in transmission process */
+    Error_Handler();
+  }
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 9600;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_ODD;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/**
+  * @brief  Rx Transfer completed callback
+  * @note   This example shows a simple way to report end of IT Rx transfer, and 
+  *         you can add your own implementation.
+  * @retval None
+  */
+void UART_CharReception_Callback(void)
+{
+  /* Read Received character. RXNE flag is cleared by reading of RDR register */
+  aRxBuffer[uwRxIndex++] = LL_USART_ReceiveData8(USART1);
+
+  /* Check if reception is completed (expected nb of bytes has been received) */
+  if (uwRxIndex == RXBUFFERSIZE)
+  {
+    /* Set Reception complete boolean to 1 */
+    ubRxComplete = 1;
+  }
+}
+
+/**
+  * @brief  Function called for achieving next TX Byte sending
+  * @retval None
+  */
+void UART_TXEmpty_Callback(void)
+{
+  if(uwTxIndex == (ubSizeToSend - 1))
+  {
+    /* Disable TXE interrupt */
+    LL_USART_DisableIT_TXE(USART1);
+    
+    /* Enable TC interrupt */
+    LL_USART_EnableIT_TC(USART1);
+  }
+
+  /* Fill TDR with a new char */
+  LL_USART_TransmitData8(USART1, aTxStartMessage[uwTxIndex++]);
+}
+
+/**
+  * @brief  Function called at completion of last byte transmission
+  * @retval None
+  */
+void UART_CharTransmitComplete_Callback(void)
+{
+  if(uwTxIndex == sizeof(aTxStartMessage))
+  {
+    uwTxIndex = 0;
+    
+    /* Disable TC interrupt */
+    LL_USART_DisableIT_TC(USART1);
+    
+    /* Set Tx complete boolean to 1 */
+    ubTxComplete = 1;
+  }
+}
+
+/**
+  * @brief  UART error callbacks
+  * @note   This example shows a simple way to report transfer error, and you can
+  *         add your own implementation.
+  * @retval None
+  */
+void UART_Error_Callback(void)
+{
+  __IO uint32_t isr_reg;
+
+  /* Disable USARTx_IRQn */
+  NVIC_DisableIRQ(USART1_IRQn);
+  
+  /* Error handling example :
+    - Read USART ISR register to identify flag that leads to IT raising
+    - Perform corresponding error handling treatment according to flag
+  */
+  isr_reg = LL_USART_ReadReg(USART1, ISR);
+  if (isr_reg & LL_USART_ISR_NE)
+  {
+    /* Turn LED3 on: Transfer error in reception/transmission process */
+    BSP_LED_On(LED3);
+  }
+  else
+  {
+    /* Turn LED3 on: Transfer error in reception/transmission process */
+    BSP_LED_On(LED3);
+  }
+}
+
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  /* Toggle LED3 for error */
+  while(1)
+  {
+    BSP_LED_Toggle(LED3);
+    HAL_Delay(1000);
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..fe5424e33
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,151 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_HyperTerminal_IT/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspInit 0 */
+
+  /* USER CODE END USART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**USART1 GPIO Configuration    
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* USART1 interrupt Init */
+    HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspInit 1 */
+
+  /* USER CODE END USART1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+  /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+  
+    /**USART1 GPIO Configuration    
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
+
+    /* USART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+  /* USER CODE END USART1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..d10112538
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Src/stm32wbxx_it.c
@@ -0,0 +1,253 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    UART/UART_HyperTerminal_IT/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern UART_HandleTypeDef huart1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+  /* Customize process using LL interface to improve the performance (exhaustive feature management not handled) */
+
+  /* Check RXNE flag value in ISR register */
+  if(LL_USART_IsActiveFlag_RXNE(USART1) && LL_USART_IsEnabledIT_RXNE(USART1))
+  {
+    /* RXNE flag will be cleared by reading of RDR register (done in call) */
+    /* Call function in charge of handling Character reception */
+    UART_CharReception_Callback();
+  }
+
+  if(LL_USART_IsEnabledIT_TXE(USART1) && LL_USART_IsActiveFlag_TXE(USART1))
+  {
+    /* TXE flag will be automatically cleared when writing new data in TDR register */
+
+    /* Call function in charge of handling empty DR => will lead to transmission of next character */
+    UART_TXEmpty_Callback();
+  }
+
+  if(LL_USART_IsEnabledIT_TC(USART1) && LL_USART_IsActiveFlag_TC(USART1))
+  {
+    /* Clear TC flag */
+    LL_USART_ClearFlag_TC(USART1);
+    /* Call function in charge of handling end of transmission of sent character
+       and prepare next charcater transmission */
+    UART_CharTransmitComplete_Callback();
+  }
+
+  if(LL_USART_IsEnabledIT_ERROR(USART1) && LL_USART_IsActiveFlag_NE(USART1))
+  {
+    /* Call Error function */
+    UART_Error_Callback();
+  }
+  /* USER CODE END USART1_IRQn 0 */
+  HAL_UART_IRQHandler(&huart1);
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/UART_HyperTerminal_IT.ioc b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/UART_HyperTerminal_IT.ioc
new file mode 100644
index 000000000..70473c399
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/UART_HyperTerminal_IT.ioc
@@ -0,0 +1,141 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=USART1
+Mcu.IPNb=4
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PB6
+Mcu.Pin1=PB7
+Mcu.Pin2=VP_SYS_VS_Systick
+Mcu.PinsNb=3
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PB6.GPIOParameters=GPIO_PuPd
+PB6.GPIO_PuPd=GPIO_PULLUP
+PB6.Locked=true
+PB6.Mode=Asynchronous
+PB6.Signal=USART1_TX
+PB7.GPIOParameters=GPIO_PuPd
+PB7.GPIO_PuPd=GPIO_PULLUP
+PB7.Locked=true
+PB7.Mode=Asynchronous
+PB7.Signal=USART1_RX
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=UART_HyperTerminal_IT.ioc
+ProjectManager.ProjectName=UART_HyperTerminal_IT
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.CodegenConfigPeriph=false
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CodegenConfigPeriph,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+USART1.AutoBaudRateEnableParam=UART_ADVFEATURE_AUTOBAUDRATE_DISABLE
+USART1.BaudRate=9600
+USART1.ClockPrescaler=PRESCALER_DIV1
+USART1.DMADisableonRxErrorParam=ADVFEATURE_DMA_ENABLEONRXERROR
+USART1.DataInvertParam=ADVFEATURE_DATAINV_DISABLE
+USART1.FIFOMode=FIFOMODE_DISABLE
+USART1.IPParameters=BaudRate,WordLength,Parity,StopBits,Mode,OverSampling,OneBitSampling,ClockPrescaler,FIFOMode,TXFIFOThreshold,RXFIFOThreshold,AutoBaudRateEnableParam,TxPinLevelInvertParam,RxPinLevelInvertParam,DataInvertParam,SwapParam,OverrunDisableParam,DMADisableonRxErrorParam,MSBFirstParam,VirtualMode-Asynchronous
+USART1.MSBFirstParam=ADVFEATURE_MSBFIRST_DISABLE
+USART1.Mode=MODE_TX_RX
+USART1.OneBitSampling=UART_ONE_BIT_SAMPLE_DISABLE
+USART1.OverSampling=UART_OVERSAMPLING_16
+USART1.OverrunDisableParam=ADVFEATURE_OVERRUN_ENABLE
+USART1.Parity=PARITY_ODD
+USART1.RXFIFOThreshold=RXFIFO_THRESHOLD_1EIGHTHFULL
+USART1.RxPinLevelInvertParam=ADVFEATURE_RXINV_DISABLE
+USART1.StopBits=STOPBITS_1
+USART1.SwapParam=ADVFEATURE_SWAP_DISABLE
+USART1.TXFIFOThreshold=TXFIFO_THRESHOLD_1EIGHTHFULL
+USART1.TxPinLevelInvertParam=ADVFEATURE_TXINV_DISABLE
+USART1.VirtualMode-Asynchronous=VM_ASYNC
+USART1.WordLength=WORDLENGTH_8B
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/readme.txt b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/readme.txt
new file mode 100644
index 000000000..0b9ffe331
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Examples_MIX/UART/UART_HyperTerminal_IT/readme.txt
@@ -0,0 +1,141 @@
+/**
+  @page UART_Hyperterminal_IT UART Hyperterminal IT example (HAL/LL mixed usage example)
+
+  @verbatim
+  ******************************************************************************
+  * @file    UART/UART_HyperTerminal_IT/readme.txt
+  * @author  MCD Application Team
+  * @brief   Description of the UART HAL/LL mixed Hyperterminal example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+Use of a UART to transmit data (transmit/receive)
+between a board and an HyperTerminal PC application in Interrupt mode. This example
+describes how to use the USART peripheral through the STM32WBxx UART HAL
+and LL API, the LL API being used for performance improvement.
+
+Board: NUCLEO-WB35CE
+Tx Pin: PB.06 (Pin 35 in CN10)
+Rx Pin: PB.07 (Pin 37 in CN10)
+   _________________________
+  |           ______________|                       _______________
+  |          |USART1        |                      | HyperTerminal |
+  |          |              |                      |               |
+  |          |           TX |______________________|RX             |
+  |          |              |                      |               |
+  |          |              |  Virtual Com Port    |               |
+  |          |              |                      |               |
+  |          |           RX |______________________|TX             |
+  |          |              |                      |               |
+  |          |______________|                      |_______________|
+  |                         |
+  |                         |
+  |                         |
+  |                         |
+  |_STM32_Board_____________|
+
+At the beginning of the main program the HAL_Init() function is called to reset
+all the peripherals, initialize the Flash interface and the systick.
+Then the SystemClock_Config() function is used to configure the system
+clock (SYSCLK) to run at 64 MHz for STM32WBxx Devices.
+
+The UART peripheral configuration is ensured by the HAL_UART_Init() function.
+This later is calling the HAL_UART_MspInit() function which core is implementing
+the configuration of the needed UART resources according to the used hardware.
+You may update this function to change UART configuration.
+
+The UART/Hyperterminal communication is then initiated.
+Receive and Transmit functions which allow respectively
+the reception of Data from Hyperterminal and the transmission of a predefined data
+buffer, are implemented using LL USART API.
+
+The Asynchronous communication aspect of the UART is clearly highlighted as the
+data buffers transmission/reception to/from Hyperterminal are done simultaneously.
+
+For this example the TX buffer (aTxStartMessage) is predefined and the RX buffer (aRxBuffer)
+size is limited to 10 data by the mean of the RXBUFFERSIZE define in the main.c file.
+
+In a first step the received data will be stored in the RX buffer and the
+TX buffer content will be displayed in the Hyperterminal interface.
+In a second step the received data in the RX buffer will be sent back to
+Hyperterminal and displayed.
+
+STM32 Nucleo board's LEDs can be used to monitor the transfer status:
+ - LED1 is ON when transmission/reception of 10 characters is complete.
+ - LED2 is ON when the reception process is complete.
+ - LED3 is ON when there is an error in transmission/reception process.
+ - LED3 toggles when there another error is detected.
+
+The UART is configured as follows:
+    - BaudRate = 9600 baud
+    - Word Length = 8 Bits (7 data bit + 1 parity bit)
+    - One Stop Bit
+    - Odd parity
+    - Hardware flow control disabled (RTS and CTS signals)
+    - Reception and transmission are enabled in the time
+
+@note When the parity is enabled, the computed parity is inserted at the MSB
+      position of the transmitted data.
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+
+@par Directory contents
+
+  - UART/UART_Hyperterminal_IT/Inc/stm32wbxx_hal_conf.h    HAL configuration file
+  - UART/UART_Hyperterminal_IT/Inc/stm32wbxx_it.h          IT interrupt handlers header file
+  - UART/UART_Hyperterminal_IT/Inc/main.h                  Main program header file
+  - UART/UART_Hyperterminal_IT/Src/stm32wbxx_it.c          IT interrupt handlers
+  - UART/UART_Hyperterminal_IT/Src/main.c                  Main program
+  - UART/UART_Hyperterminal_IT/Src/stm32wbxx_hal_msp.c     HAL MSP file
+  - UART/UART_Hyperterminal_IT/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+  - NUCLEO-WB35CE Set-up
+    Example is delivered for using Virtual Com port feature of STLINK for connection between NUCLEO-WB35CE and PC,
+    Please ensure that USART communication between the target MCU and ST-LINK MCU is properly enabled
+    on HW board in order to support Virtual Com Port (Default HW SB configuration allows use of VCP)
+    GPIOs connected to USART1 TX/RX (PB6 and PB7) are automatically mapped
+    on RX and TX pins of PC UART Com port selected on PC side (please ensure VCP com port is selected).
+
+  - Launch serial communication SW on PC (as HyperTerminal or TeraTerm) with proper configuration
+    - Word Length = 7 Bits
+    - One Stop Bit
+    - Odd parity
+    - BaudRate = 9600 baud
+    - Flow control: None
+
+@par How to use it ?
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Release_Notes.html b/Projects/NUCLEO-WB35CE/Release_Notes.html
new file mode 100644
index 000000000..72ec54d6d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Release_Notes.html
@@ -0,0 +1,62 @@
+
+
+
+  
+  
+  
+  Release Notes for NUCLEO-WB35CE
+  
+  
+  
+
+
+
    
+
    
+
    
+
    
+
    
+
    Release Notes for NUCLEO-WB35CE
    
+
    Copyright © 2019 STMicroelectronics
    
+
    
+
+
    
+
    
+
    
+
    License
    
+
    This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:
    
+
    https://opensource.org/licenses/BSD-3-Clause
    
+
    Purpose
    
+
    This directory contains the examples and applications to demonstrate the capabilities of the NUCLEO-WB35CE board.
    
+
    Most of those projects are generated with STM32CubeMX tool to initialize the system, peripherals and middleware stacks.
    
+
    Several applications are provided ready to use with IAR, KEIL and SW4STM32 to demonstrate the Bluetooth Low Energy capabilities of the device.
    
+
    A particular attention must be taken when using BLE as a specific binary must be loaded inside device memory for each application. You can refer to the readme.txt of each application for the detailed information and usage.
    
+
    They can be found under the following directories:
    
+
      
+
    • Projects\NUCLEO-WB35CE\Applications\BLE
      • 
+
    
+
    
+
    
+
    Update History
    
+
    
+ 
+
    
+
    Main Changes
    
+
    Introduction of NUCLEO-WB35CE
    
+
    Initial version introducing NUCLEO-WB35CE projects. - Thread - Support of a first Thread application (Thread_Cli_Cmd).
    
+
    
+
    
+
    
+
    
+
    
+
    For complete documentation on STM32WBxx, visit: [www.st.com/stm32wb]
    
+This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.
+
    
+
+
diff --git a/Projects/NUCLEO-WB35CE/Templates/.extSettings b/Projects/NUCLEO-WB35CE/Templates/.extSettings
new file mode 100644
index 000000000..f46322bc5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/.extSettings
@@ -0,0 +1,8 @@
+[ProjectFiles]
+HeaderPath=..\..\..\..\Drivers\BSP\NUCLEO-WB35CE
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
+Drivers/BSP/NUCLEO-WB35CE=../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c;
diff --git a/Projects/NUCLEO-WB35CE/Templates/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Templates/EWARM/Project.eww
new file mode 100644
index 000000000..b8b991bce
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\Templates.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Templates/EWARM/Templates.ewd b/Projects/NUCLEO-WB35CE/Templates/EWARM/Templates.ewd
new file mode 100644
index 000000000..fd11b3f47
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/EWARM/Templates.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		Templates
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Templates/EWARM/Templates.ewp b/Projects/NUCLEO-WB35CE/Templates/EWARM/Templates.ewp
new file mode 100644
index 000000000..d51c55a64
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/EWARM/Templates.ewp
@@ -0,0 +1,1119 @@
+
+
+  3
+  
+    Templates
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_hal_msp.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      BSP
+      
+        NUCLEO-WB35CE
+        
+          $PROJ_DIR$/../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+        
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      
+    
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Templates/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Templates/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Templates/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Templates/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Templates/EWARM/stm32wb35xx_sram_cm4.icf b/Projects/NUCLEO-WB35CE/Templates/EWARM/stm32wb35xx_sram_cm4.icf
new file mode 100644
index 000000000..6426355fb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/EWARM/stm32wb35xx_sram_cm4.icf
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20003FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20004000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20008000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x2000FFFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/Projects/NUCLEO-WB35CE/Templates/Inc/main.h b/Projects/NUCLEO-WB35CE/Templates/Inc/main.h
new file mode 100644
index 000000000..52fdc9e80
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Templates/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "nucleo_wb35ce.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Templates/Inc/stm32wbxx_hal_conf.h b/Projects/NUCLEO-WB35CE/Templates/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..19d12a61f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    8000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE) 
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE) 
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+  
+#define  VDD_VALUE				3300U                   /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+   
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+    
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Templates/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Templates/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..9b5bc0ddf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Templates/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Templates/MDK-ARM/Templates.uvoptx b/Projects/NUCLEO-WB35CE/Templates/MDK-ARM/Templates.uvoptx
new file mode 100644
index 000000000..dcabf4f1a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/MDK-ARM/Templates.uvoptx
@@ -0,0 +1,497 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    Templates
+    0x4
+    ARM-ADS
+    
+      64000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4.FLM -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+    
+      2
+      4
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_hal_msp.c
+      stm32wbxx_hal_msp.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      5
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/BSP/NUCLEO-WB35CE
+    0
+    0
+    0
+    0
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+      nucleo_wb35ce.c
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      5
+      7
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+      stm32wbxx_hal_gpio.c
+      0
+      0
+    
+    
+      5
+      8
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+      stm32wbxx_hal_tim.c
+      0
+      0
+    
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+      stm32wbxx_hal_tim_ex.c
+      0
+      0
+    
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+      stm32wbxx_hal_rcc.c
+      0
+      0
+    
+    
+      5
+      11
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+      stm32wbxx_hal_rcc_ex.c
+      0
+      0
+    
+    
+      5
+      12
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+      stm32wbxx_hal_flash.c
+      0
+      0
+    
+    
+      5
+      13
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+      stm32wbxx_hal_flash_ex.c
+      0
+      0
+    
+    
+      5
+      14
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+      stm32wbxx_hal_hsem.c
+      0
+      0
+    
+    
+      5
+      15
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+      stm32wbxx_hal_dma.c
+      0
+      0
+    
+    
+      5
+      16
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+      stm32wbxx_hal_dma_ex.c
+      0
+      0
+    
+    
+      5
+      17
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+      stm32wbxx_hal_pwr.c
+      0
+      0
+    
+    
+      5
+      18
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+      stm32wbxx_hal_pwr_ex.c
+      0
+      0
+    
+    
+      5
+      19
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+      stm32wbxx_hal_cortex.c
+      0
+      0
+    
+    
+      5
+      20
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+      stm32wbxx_hal.c
+      0
+      0
+    
+    
+      5
+      21
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+      stm32wbxx_hal_exti.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      6
+      22
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Templates/MDK-ARM/Templates.uvprojx b/Projects/NUCLEO-WB35CE/Templates/MDK-ARM/Templates.uvprojx
new file mode 100644
index 000000000..d44554efd
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/MDK-ARM/Templates.uvprojx
@@ -0,0 +1,541 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      Templates
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          Templates\
+          Templates
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_HAL_DRIVER,STM32WB35xx
+              
+              ../Inc;../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../Drivers/STM32WBxx_HAL_Driver/Inc/Legacy;../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../Drivers/CMSIS/Include;../../../../Drivers/BSP/NUCLEO-WB35CE
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Src/stm32wbxx_hal_msp.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/BSP/NUCLEO-WB35CE
+          
+            
+              nucleo_wb35ce.c
+              1
+              ../../../../Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_hal_gpio.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+            
+            
+              stm32wbxx_hal_tim.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+            
+            
+              stm32wbxx_hal_tim_ex.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+            
+            
+              stm32wbxx_hal_rcc.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+            
+            
+              stm32wbxx_hal_rcc_ex.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+            
+            
+              stm32wbxx_hal_flash.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+            
+            
+              stm32wbxx_hal_flash_ex.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+            
+            
+              stm32wbxx_hal_hsem.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+            
+            
+              stm32wbxx_hal_dma.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+            
+            
+              stm32wbxx_hal_dma_ex.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+            
+            
+              stm32wbxx_hal_pwr.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+            
+            
+              stm32wbxx_hal_pwr_ex.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+            
+            
+              stm32wbxx_hal_cortex.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+            
+            
+              stm32wbxx_hal.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+            
+            
+              stm32wbxx_hal_exti.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Templates/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Templates/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Templates/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Templates/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..94494e2ab
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/.cproject
@@ -0,0 +1,169 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/.project
new file mode 100644
index 000000000..d27d79eae
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/.project
@@ -0,0 +1,145 @@
+
+
+	Templates
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			Templates.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Templates.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_hal_msp.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_hal_msp.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+		
+			Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/BSP/NUCLEO-WB35CE/nucleo_wb35ce.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Templates/Src/main.c b/Projects/NUCLEO-WB35CE/Templates/Src/main.c
new file mode 100644
index 000000000..32ed9cdf3
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/Src/main.c
@@ -0,0 +1,206 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Templates/Src/main.c
+  * @author  MCD Application Team
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  while(1) 
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* Infinite loop */
+  while (1)
+  {
+  }
+
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Templates/Src/stm32wbxx_hal_msp.c b/Projects/NUCLEO-WB35CE/Templates/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..5c745f47f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,82 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Templates/Src/stm32wbxx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   This file provides code for the MSP Initialization 
+  *          and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Templates/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Templates/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..b6ff4e47a
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/Src/stm32wbxx_it.c
@@ -0,0 +1,206 @@
+/* USER CODE BEGIN Header */
+/** 
+  ******************************************************************************
+  * @file    Templates/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Templates/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Templates/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Templates/Templates.ioc b/Projects/NUCLEO-WB35CE/Templates/Templates.ioc
new file mode 100644
index 000000000..4f2eab55e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/Templates.ioc
@@ -0,0 +1,104 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+KeepUserPlacement=true
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=Templates.ioc
+ProjectManager.ProjectName=Templates
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=
+RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB1TimFreq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB2TimFreq_Value=64000000
+RCC.APB3Freq_Value=16000000
+RCC.Cortex2Freq_Value=32000000
+RCC.CortexFreq_Value=64000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=32000000
+RCC.FCLKCortexFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=32000000
+RCC.HCLK3Freq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=64000000
+RCC.I2C3Freq_Value=64000000
+RCC.IPParameters=AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=64000000
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=64000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=128000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Templates/readme.txt b/Projects/NUCLEO-WB35CE/Templates/readme.txt
new file mode 100644
index 000000000..7b5cd7aa5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates/readme.txt
@@ -0,0 +1,65 @@
+/**
+  @page Templates  Description of the Templates example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Templates/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the Templates example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+This projects provides a reference template that can be used to build any firmware application.
+
+This directory provides a reference template project that can be used to build any firmware application for
+STM32WB35CEUx devices using STM32CubeWB HAL and running on NUCLEO-WB35CE board from STMicroelectronics. 
+
+@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
+      based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
+      a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
+      than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+      To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
+      
+@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
+      to have correct HAL operation.
+
+@par Directory contents 
+
+  - Templates/Src/main.c                 Main program
+  - Templates/Src/system_stm32wbxx.c     STM32WBxx system clock configuration file
+  - Templates/Src/stm32wbxx_it.c         Interrupt handlers 
+  - Templates/Src/stm32wbxx_hal_msp.c    HAL MSP module
+  - Templates/Inc/main.h                 Main program header file  
+  - Templates/Inc/stm32wbxx_hal_conf.h   HAL Configuration file
+  - Templates/Inc/stm32wbxx_it.h         Interrupt handlers header file
+
+        
+@par Hardware and Software environment  
+
+  - This example runs on STM32WB35CE devices.
+    
+  - This example has been tested with STMicroelectronics NUCLEO-WB35CE
+    boards and can be easily tailored to any other supported device 
+    and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/.extSettings b/Projects/NUCLEO-WB35CE/Templates_LL/.extSettings
new file mode 100644
index 000000000..861dedcad
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/.extSettings
@@ -0,0 +1,7 @@
+[ProjectFiles]
+HeaderPath=
+[Others]
+Define=
+HALModule=
+[Groups]
+Doc=../readme.txt;
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/EWARM/Project.eww b/Projects/NUCLEO-WB35CE/Templates_LL/EWARM/Project.eww
new file mode 100644
index 000000000..5a9b0a765
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/EWARM/Project.eww
@@ -0,0 +1,7 @@
+
+
+  
+    $WS_DIR$\Templates_LL.ewp
+  
+  
+
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/EWARM/Templates_LL.ewd b/Projects/NUCLEO-WB35CE/Templates_LL/EWARM/Templates_LL.ewd
new file mode 100644
index 000000000..670b3d43f
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/EWARM/Templates_LL.ewd
@@ -0,0 +1,1419 @@
+
+
+	3
+	
+		Templates_LL
+		
+			ARM
+		
+		1
+		
+			C-SPY
+			2
+			
+				29
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			ARMSIM_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			CADI_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+			
+		
+		
+			CMSISDAP_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			GDBSERVER_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			IJET_ID
+			2
+			
+				8
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			JLINK_ID
+			2
+			
+				16
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			LMIFTDI_ID
+			2
+			
+				2
+				1
+				1
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			PEMICRO_ID
+			2
+			
+				3
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			STLINK_ID
+			2
+			
+				4
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			THIRDPARTY_ID
+			2
+			
+				0
+				1
+				1
+				
+				
+				
+				
+			
+		
+		
+			TIFET_ID
+			2
+			
+				1
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			XDS100_ID
+			2
+			
+				6
+				1
+				1
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+				
+			
+		
+		
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+				0
+			
+			
+				$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+				1
+			
+			
+				$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+				0
+			
+			
+				$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+				0
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/EWARM/Templates_LL.ewp b/Projects/NUCLEO-WB35CE/Templates_LL/EWARM/Templates_LL.ewp
new file mode 100644
index 000000000..3841ae479
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/EWARM/Templates_LL.ewp
@@ -0,0 +1,1083 @@
+
+
+  3
+  
+    Templates_LL
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        29
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        34
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        10
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+        0
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        20
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Application
+    
+      EWARM
+      
+        $PROJ_DIR$/startup_stm32wb35xx_cm4.s
+      
+    
+    
+      User
+      
+        $PROJ_DIR$/../Src/main.c
+      
+      
+        $PROJ_DIR$/../Src/stm32wbxx_it.c
+      
+    
+  
+  
+    Doc
+    
+      $PROJ_DIR$/../readme.txt
+    
+  
+  
+    Drivers
+    
+      CMSIS
+      
+        $PROJ_DIR$/../Src/system_stm32wbxx.c
+      
+    
+    
+      STM32WBxx_HAL_Driver
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      
+      
+        $PROJ_DIR$/../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      
+    
+  
+
+
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/EWARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Templates_LL/EWARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..919503dca
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/EWARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,507 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : M4 core vector table of the STM32WB35xx devices for the
+;*                      IAR (EWARM) toolchain.
+;*
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;******************************************************************************
+;* @attention
+;*
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_IRQHandler
+        B TAMP_STAMP_LSECSS_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK C2SEV_PWR_C2H_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+        B C2SEV_PWR_C2H_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+        B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+
+        PUBWEAK IPCC_C1_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+        B IPCC_C1_RX_IRQHandler
+
+        PUBWEAK IPCC_C1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+        B IPCC_C1_TX_IRQHandler
+
+        PUBWEAK HSEM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+        B HSEM_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK AES1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES1_IRQHandler
+        B AES1_IRQHandler
+
+        PUBWEAK AES2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES2_IRQHandler
+        B AES2_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/EWARM/stm32wb35xx_flash_cm4.icf b/Projects/NUCLEO-WB35CE/Templates_LL/EWARM/stm32wb35xx_flash_cm4.icf
new file mode 100644
index 000000000..5ab0c933b
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/EWARM/stm32wb35xx_flash_cm4.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20008000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x2000A7FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/EWARM/stm32wb35xx_sram_cm4.icf b/Projects/NUCLEO-WB35CE/Templates_LL/EWARM/stm32wb35xx_sram_cm4.icf
new file mode 100644
index 000000000..6426355fb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/EWARM/stm32wb35xx_sram_cm4.icf
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20003FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20004000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20008000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x2000FFFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/Inc/main.h b/Projects/NUCLEO-WB35CE/Templates_LL/Inc/main.h
new file mode 100644
index 000000000..2c798ed09
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/Inc/main.h
@@ -0,0 +1,96 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Templates_LL/Inc/main.h
+  * @author  MCD Application Team
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_ll_crs.h"
+#include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_system.h"
+#include "stm32wbxx_ll_exti.h"
+#include "stm32wbxx_ll_cortex.h"
+#include "stm32wbxx_ll_utils.h"
+#include "stm32wbxx_ll_pwr.h"
+#include "stm32wbxx_ll_dma.h"
+#include "stm32wbxx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/Inc/stm32_assert.h b/Projects/NUCLEO-WB35CE/Templates_LL/Inc/stm32_assert.h
new file mode 100644
index 000000000..c42df1966
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/Inc/stm32wbxx_it.h b/Projects/NUCLEO-WB35CE/Templates_LL/Inc/stm32wbxx_it.h
new file mode 100644
index 000000000..f27198f96
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Templates_LL/Inc/stm32wbxx_it.h
+  * @author  MCD Application Team
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/MDK-ARM/Templates_LL.uvoptx b/Projects/NUCLEO-WB35CE/Templates_LL/MDK-ARM/Templates_LL.uvoptx
new file mode 100644
index 000000000..b3dd005b5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/MDK-ARM/Templates_LL.uvoptx
@@ -0,0 +1,333 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    Templates_LL
+    0x4
+    ARM-ADS
+    
+      16000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U066BFF333539554E43161529 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WB3x_512_M4 -FS08000000 -FL080000 -FP0($$Device:STM32WB35CEUx$Drivers\CMSIS\Flash\STM32WB3x_512_M4.FLM)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Application/MDK-ARM
+    0
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      0
+      startup_stm32wb35xx_cm4.s
+      startup_stm32wb35xx_cm4.s
+      0
+      0
+    
+  
+
+  
+    Application/User
+    0
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      ../Src/main.c
+      main.c
+      0
+      0
+    
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      ../Src/stm32wbxx_it.c
+      stm32wbxx_it.c
+      0
+      0
+    
+  
+
+  
+    Doc
+    0
+    0
+    0
+    0
+    
+      3
+      4
+      5
+      0
+      0
+      0
+      ../readme.txt
+      readme.txt
+      0
+      0
+    
+  
+
+  
+    Drivers/STM32WBxx_HAL_Driver
+    0
+    0
+    0
+    0
+    
+      4
+      5
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+      stm32wbxx_ll_utils.c
+      0
+      0
+    
+    
+      4
+      6
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+      stm32wbxx_ll_exti.c
+      0
+      0
+    
+    
+      4
+      7
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+      stm32wbxx_ll_pwr.c
+      0
+      0
+    
+    
+      4
+      8
+      1
+      0
+      0
+      0
+      ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+      stm32wbxx_ll_gpio.c
+      0
+      0
+    
+  
+
+  
+    Drivers/CMSIS
+    0
+    0
+    0
+    0
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      ../Src/system_stm32wbxx.c
+      system_stm32wbxx.c
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/MDK-ARM/Templates_LL.uvprojx b/Projects/NUCLEO-WB35CE/Templates_LL/MDK-ARM/Templates_LL.uvprojx
new file mode 100644
index 000000000..104f8cdcf
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/MDK-ARM/Templates_LL.uvprojx
@@ -0,0 +1,471 @@
+
+
+
+  2.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      Templates_LL
+      0x4
+      ARM-ADS
+      0
+      
+        
+          STM32WB35CEUx
+          STMicroelectronics
+          Keil.STM32WB3x_DFP.1.0.2
+          http://www.keil.com/pack
+          IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32WB35CEUx$Drivers\CMSIS\SVD\STM32WB35_CM4.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          Templates_LL\
+          Templates_LL
+          1
+          0
+          1
+          1
+          1
+          
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          0
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4107
+          
+          1
+          STLink\ST-LINKIII-KEIL_SWO.dll
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            2
+            0
+            0
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x80000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x18000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              
+              USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=4800000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32WB35xx
+              
+              ../Inc;../../../../Drivers/STM32WBxx_HAL_Driver/Inc;../../../../Drivers/CMSIS/Device/ST/STM32WBxx/Include;../../../../Drivers/CMSIS/Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            stm32wb35xx_flash_cm4.sct
+            
+            
+            --diag_suppress L6314W
+            
+            
+          
+        
+      
+      
+        
+          Application/MDK-ARM
+          
+            
+              startup_stm32wb35xx_cm4.s
+              2
+              startup_stm32wb35xx_cm4.s
+            
+          
+        
+        
+          Application/User
+          
+            
+              main.c
+              1
+              ../Src/main.c
+            
+            
+              stm32wbxx_it.c
+              1
+              ../Src/stm32wbxx_it.c
+            
+          
+        
+        
+          Doc
+          
+            
+              readme.txt
+              5
+              ../readme.txt
+            
+          
+        
+        
+          Drivers/STM32WBxx_HAL_Driver
+          
+            
+              stm32wbxx_ll_utils.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+            
+            
+              stm32wbxx_ll_exti.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+            
+            
+              stm32wbxx_ll_pwr.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+            
+            
+              stm32wbxx_ll_gpio.c
+              1
+              ../../../../Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32wbxx.c
+              1
+              ../Src/system_stm32wbxx.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+    
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/MDK-ARM/startup_stm32wb35xx_cm4.s b/Projects/NUCLEO-WB35CE/Templates_LL/MDK-ARM/startup_stm32wb35xx_cm4.s
new file mode 100644
index 000000000..25a64ae45
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/MDK-ARM/startup_stm32wb35xx_cm4.s
@@ -0,0 +1,364 @@
+;******************************************************************************
+;* File Name          : startup_stm32wb35xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WB35xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+        DCD     Reset_Handler                     ; Reset Handler
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+        DCD     RCC_IRQHandler                    ; RCC Interrupt
+        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+        DCD     ADC1_IRQHandler                   ; ADC1 Interrupt
+        DCD     USB_HP_IRQHandler                 ; USB High Priority Interrupt
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority Interrupt
+        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
+        DCD     COMP_IRQHandler                   ; COMP1 and COMP2  Interrupts
+        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16 global Interrupts
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Communication and TIM17 global Interrupts
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+        DCD     PKA_IRQHandler                    ; PKA Interrupt
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+        DCD     USART1_IRQHandler                 ; USART1 Interrupt
+        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; TSC Interrupt
+        DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
+        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+        DCD     0                                 ; Reserved
+        DCD     QUADSPI_IRQHandler                ; QUADSPI Interrupt
+        DCD     AES1_IRQHandler                   ; AES1 Interrupt
+        DCD     AES2_IRQHandler                   ; AES2 Interrupt
+        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+        DCD     FPU_IRQHandler                    ; FPU Interrupt
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_IRQHandler      [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler                   [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  TSC_IRQHandler                    [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  AES1_IRQHandler                   [WEAK]
+                EXPORT  AES2_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+PKA_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+LPUART1_IRQHandler
+TSC_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CRS_IRQHandler
+PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+QUADSPI_IRQHandler
+AES1_IRQHandler
+AES2_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/MDK-ARM/stm32wb35xx_flash_cm4.sct b/Projects/NUCLEO-WB35CE/Templates_LL/MDK-ARM/stm32wb35xx_flash_cm4.sct
new file mode 100644
index 000000000..c97ed269e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/MDK-ARM/stm32wb35xx_flash_cm4.sct
@@ -0,0 +1,21 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1     0x20000004 0x7FFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
+   *(MAPPING_TABLE)
+   *(MB_MEM1)
+   *(MB_MEM2)
+  }
+  }
+
+
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/.cproject b/Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/.cproject
new file mode 100644
index 000000000..45293e141
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/.cproject
@@ -0,0 +1,187 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/.project b/Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/.project
new file mode 100644
index 000000000..224578ffb
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/.project
@@ -0,0 +1,80 @@
+
+
+	Templates_LL
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		com.st.stm32cube.ide.mcu.MCUProjectNature
+		org.eclipse.cdt.core.cnature
+		com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
+		com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature
+		com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+		com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+		com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+		com.st.stm32cube.ide.mcu.MCURootProjectNature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			Templates_LL.ioc
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Templates_LL.ioc
+		
+		
+			Doc/readme.txt
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/readme.txt
+		
+		
+			Application/User/main.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/main.c
+		
+		
+			Application/User/stm32wbxx_it.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/stm32wbxx_it.c
+		
+		
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			$%7BPARENT-1-PROJECT_LOC%7D/Src/system_stm32wbxx.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_exti.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_gpio.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+		
+		
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
+			1
+			$%7BPARENT-4-PROJECT_LOC%7D/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+		
+	
+
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s b/Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
new file mode 100644
index 000000000..5155eb5f2
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/Application/Startup/startup_stm32wb35ceux.s
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32wb55xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WB55xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
+  movs r3, #0
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
+
+.section  .text.data_initializers
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc  CopyDataInit
+  bx lr
+
+FillZerobss:
+  str  r3, [r0]
+  adds r0, r0, #4
+
+LoopFillZerobss:
+  cmp r0, r1
+  bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+	bl	main
+
+LoopForever:
+  b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+	.word	NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_PVM_IRQHandler
+  .word TAMP_STAMP_LSECSS_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word C2SEV_PWR_C2H_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_TIM16_IRQHandler
+  .word TIM1_TRG_COM_TIM17_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word PKA_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C3_EV_IRQHandler
+  .word I2C3_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word LPUART1_IRQHandler
+  .word 0
+  .word TSC_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word CRS_IRQHandler
+  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .word IPCC_C1_RX_IRQHandler
+  .word IPCC_C1_TX_IRQHandler
+  .word HSEM_IRQHandler
+  .word LPTIM1_IRQHandler
+  .word LPTIM2_IRQHandler
+  .word 0
+  .word QUADSPI_IRQHandler
+  .word AES1_IRQHandler
+  .word AES2_IRQHandler
+  .word RNG_IRQHandler
+  .word FPU_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word DMA2_Channel6_IRQHandler
+  .word DMA2_Channel7_IRQHandler
+  .word DMAMUX1_OVR_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_PVM_IRQHandler
+  .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+  .weak  TAMP_STAMP_LSECSS_IRQHandler
+  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
+
+  .weak  RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak  USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak  C2SEV_PWR_C2H_IRQHandler
+  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+  .weak  COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  PKA_IRQHandler
+  .thumb_set PKA_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C3_EV_IRQHandler
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+  .weak  I2C3_ER_IRQHandler
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+  .weak  TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak  CRS_IRQHandler
+  .thumb_set CRS_IRQHandler,Default_Handler
+
+  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
+  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_RX_IRQHandler
+  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+  .weak  IPCC_C1_TX_IRQHandler
+  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+  .weak  HSEM_IRQHandler
+  .thumb_set HSEM_IRQHandler,Default_Handler
+
+  .weak  LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak  LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak  QUADSPI_IRQHandler
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+  .weak  AES1_IRQHandler
+  .thumb_set AES1_IRQHandler,Default_Handler
+
+  .weak  AES2_IRQHandler
+  .thumb_set AES2_IRQHandler,Default_Handler
+
+  .weak  RNG_IRQHandler
+  .thumb_set RNG_IRQHandler,Default_Handler
+
+  .weak  FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel6_IRQHandler
+  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel7_IRQHandler
+  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+  .weak  DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/Application/User/syscalls.c b/Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/Application/User/syscalls.c
new file mode 100644
index 000000000..9f32dad0e
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/Application/User/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/Application/User/sysmem.c b/Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/Application/User/sysmem.c
new file mode 100644
index 000000000..e5e1bc2d9
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/Application/User/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2018 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/STM32WB35CEUX_FLASH.ld b/Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
new file mode 100644
index 000000000..f1ff0d7da
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/STM32CubeIDE/STM32WB35CEUX_FLASH.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb35xx_flash_cm4.ld
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE for MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x7FFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/Src/main.c b/Projects/NUCLEO-WB35CE/Templates_LL/Src/main.c
new file mode 100644
index 000000000..0088823ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/Src/main.c
@@ -0,0 +1,193 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Templates_LL/Src/main.c
+  * @author  MCD Application Team
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  
+
+  NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  /* HSI configuration and activation */
+  LL_RCC_HSI_Enable();
+  while(LL_RCC_HSI_IsReady() != 1)
+  {
+  };
+
+  /* Sysclk activation on the HSI */
+  /* Set CPU1 prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set CPU2 prescaler*/
+  LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+  {
+  };
+
+  /* Set AHB SHARED prescaler*/
+  LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  /* Set APB2 prescaler*/
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+  LL_Init1msTick(16000000);
+
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(16000000);
+  LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSI);
+  LL_RCC_SetSMPSPrescaler(LL_RCC_SMPS_DIV_1);
+  LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_NONE);
+  /* USER CODE BEGIN Smps */
+
+  /* USER CODE END Smps */
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  while(1) 
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* Infinite loop */
+  while (1)
+  {
+  }
+
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/Src/stm32wbxx_it.c b/Projects/NUCLEO-WB35CE/Templates_LL/Src/stm32wbxx_it.c
new file mode 100644
index 000000000..c326d0bd5
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/Src/stm32wbxx_it.c
@@ -0,0 +1,206 @@
+/* USER CODE BEGIN Header */
+/** 
+  ******************************************************************************
+  * @file    Templates/Src/stm32wbxx_it.c
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/Src/system_stm32wbxx.c b/Projects/NUCLEO-WB35CE/Templates_LL/Src/system_stm32wbxx.c
new file mode 100644
index 000000000..2e42904ec
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/Src/system_stm32wbxx.c
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_system
+  * @{
+  */
+
+/** @addtogroup stm32WBxx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32wbxx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */ 
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
+
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+#if defined(STM32WB55xx) || defined(STM32WB35xx)
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
+
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
+
+#if defined(STM32WB55xx)
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
+#endif
+  
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+
+  /*MSI frequency range in Hz*/
+  msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:   /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C: /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
+
+      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      else /* MSI used as PLL clock source */
+      {
+        pllvco = (msirange / pllm);
+      }
+      
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+      
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK1 prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock = SystemCoreClock / tmp;
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/Templates_LL.ioc b/Projects/NUCLEO-WB35CE/Templates_LL/Templates_LL.ioc
new file mode 100644
index 000000000..42171e95d
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/Templates_LL.ioc
@@ -0,0 +1,102 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+KeepUserPlacement=false
+Mcu.Family=STM32WB
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IPNb=3
+Mcu.Name=STM32WB35C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.PinsNb=1
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32WB35CEUx
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PCC.Ble.ConnectionInterval=1000.0
+PCC.Ble.DataLength=6
+PCC.Ble.Mode=NOT_SELECTED
+PCC.Ble.PowerLevel=Min
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32WB35CEUx
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=Templates_LL.ioc
+ProjectManager.ProjectName=Templates_LL
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8.32
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-LL-false
+RCC.AHBFreq_Value=16000000
+RCC.APB1Freq_Value=16000000
+RCC.APB1TimFreq_Value=16000000
+RCC.APB2Freq_Value=16000000
+RCC.APB2TimFreq_Value=16000000
+RCC.APB3Freq_Value=16000000
+RCC.Cortex2Freq_Value=16000000
+RCC.CortexFreq_Value=16000000
+RCC.EXTERNAL_CLOCK_VALUE=4800000
+RCC.FCLK2Freq_Value=16000000
+RCC.FCLKCortexFreq_Value=16000000
+RCC.FamilyName=M
+RCC.HCLK2Freq_Value=16000000
+RCC.HCLK3Freq_Value=16000000
+RCC.HCLKFreq_Value=16000000
+RCC.HCLKRFFreq_Value=16000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=16000000
+RCC.I2C3Freq_Value=16000000
+RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,Cortex2Freq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SMPS1Freq_Value,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=16000000
+RCC.LPTIM2Freq_Value=16000000
+RCC.LPUART1Freq_Value=16000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=16000000
+RCC.PLLPoutputFreq_Value=16000000
+RCC.PLLQoutputFreq_Value=16000000
+RCC.PLLRCLKFreq_Value=16000000
+RCC.PWRFreq_Value=16000000
+RCC.RNGFreq_Value=32000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=16000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_HSI
+RCC.USART1Freq_Value=16000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=32000000
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/Projects/NUCLEO-WB35CE/Templates_LL/readme.txt b/Projects/NUCLEO-WB35CE/Templates_LL/readme.txt
new file mode 100644
index 000000000..5623b79e7
--- /dev/null
+++ b/Projects/NUCLEO-WB35CE/Templates_LL/readme.txt
@@ -0,0 +1,87 @@
+/**
+  @page Templates_LL  Description of the Templates_LL example
+  
+  @verbatim
+  ******************************************************************************
+  * @file    Templates_LL/readme.txt 
+  * @author  MCD Application Team
+  * @brief   Description of the Templates_LL example.
+  ******************************************************************************
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  @endverbatim
+
+@par Example Description
+
+This projects provides a reference template through the LL API that can be used to build any firmware application.
+
+This project LL template provides:
+ - Inclusion of all LL drivers (include files in "main.h" and LL sources files in IDE environment, with option "USE_FULL_LL_DRIVER" in IDE environment)
+   Note: If optimization is needed afterwards, user can perform a cleanup by removing unused drivers.
+ - Definition of LEDs and user button (file: main.h)
+   Note: User button name printed on board may differ from naming "user button" in code: "key button", ...
+ - Clock configuration (file: main.c)
+
+This project LL template does not provide:
+ - Functions to initialize and control LED and user button
+ - Functions to manage IRQ handler of user button
+
+To port a LL example to the targeted board:
+1. Select the LL example to port.
+   To find the board on which LL examples are deployed, refer to LL examples list in "STM32CubeProjectsList.html", table section "Examples_LL"
+   or AN    : STM32Cube firmware examples for stm32wbxx Series
+
+2. Replace source files of the LL template by the ones of the LL example, except code specific to board.
+   Note: Code specific to board is specified between tags:
+         /* ==============   BOARD SPECIFIC CONFIGURATION CODE BEGIN    ============== */
+         /* ==============   BOARD SPECIFIC CONFIGURATION CODE END      ============== */
+         
+   - Replace file main.h, with updates:
+     - Keep LED and user button definition of the LL template under tags
+    
+   - Replace file main.c, with updates:
+     - Keep clock configuration of the LL template: function "SystemClock_Config()"
+     - Depending of LED availability, replace LEDx_PIN by another LEDx (number) available in file main.h
+     
+   - Replace file stm32wbxx_it.h
+   - Replace file stm32wbxx_it.c
+
+
+@par Keywords
+
+Template LL, 
+
+@par Directory contents 
+
+  - Templates_LL/Inc/stm32wbxx_it.h          Interrupt handlers header file
+  - Templates_LL/Inc/main.h                  Header for main.c module
+  - Templates_LL/Inc/stm32_assert.h     Template file to include assert_failed function
+  - Templates_LL/Src/stm32wbxx_it.c          Interrupt handlers
+  - Templates_LL/Src/main.c                  Main program
+  - Templates_LL/Src/system_stm32wbxx.c      STM32WBxx system source file
+
+
+@par Hardware and Software environment
+
+  - This example runs on STM32WB35CEUx devices.
+    
+  - This example has been tested with NUCLEO-WB35CE board and can be
+    easily tailored to any other supported device and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Open your preferred toolchain
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+ * 
    © COPYRIGHT STMicroelectronics
    
+ */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/BLE_Beacon.ioc b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/BLE_Beacon.ioc
index 646d86bf7..cd4ed5b59 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/BLE_Beacon.ioc
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/BLE_Beacon.ioc
@@ -94,8 +94,8 @@ Mcu.PinsNb=17
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32WB55RGVx
-MxCube.Version=5.5.0
-MxDb.Version=DB.5.0.50
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.DMA1_Channel4_IRQn=true\:15\:0\:true\:false\:true\:false\:true
 NVIC.DMA2_Channel4_IRQn=true\:15\:0\:true\:false\:true\:false\:true
@@ -157,14 +157,6 @@ PCC.Ble.ConnectionInterval=1000.0
 PCC.Ble.DataLength=6
 PCC.Ble.Mode=Advertising
 PCC.Ble.PowerLevel=Min
-PCC.Checker=true
-PCC.Line=STM32WBx5
-PCC.MCU=STM32WB55RGVx
-PCC.PartNumber=STM32WB55RGVx
-PCC.Seq0=0
-PCC.Series=STM32WB
-PCC.Temperature=25
-PCC.Vdd=3.0
 PinOutPanel.RotationAngle=0
 ProjectManager.AskForMigrate=true
 ProjectManager.BackupPrevious=false
@@ -284,8 +276,8 @@ STM32_WPAN.CUSTOM_TEMPLATE=Disabled
 STM32_WPAN.DBG_TRACE_UART_CFG=hw_uart1
 STM32_WPAN.IPParameters=CFG_FAST_CONN_ADV_INTERVAL_MAX_HEXA,CFG_LP_CONN_ADV_INTERVAL_MAX_HEXA,LOCAL_NAME_FORMATTED,CFG_HW_LPUART1_ENABLED,CFG_DEBUG_BLE_TRACE,CFG_DEBUG_APP_TRACE,DBG_TRACE_UART_CFG,CFG_ADV_BD_ADDRESS,CFG_LP_CONN_ADV_INTERVAL_MAX,CFG_LP_CONN_ADV_INTERVAL_MIN,CFG_HW_LPUART1_DMA_TX_SUPPORTED,LOCAL_NAME,CFG_HW_USART1_ENABLED,CFG_LPM_SUPPORTED,CUSTOM_P2P_SERVER,BLE_DBG_SVCCTL_EN,BT_SIG_HEALTH_THERMOMETER_SENSOR,BLE_CFG_DIS_MODEL_NUMBER_STRING,BLE_CFG_DIS_SYSTEM_ID,BLE_CFG_HTS_MEASUREMENT_INTERVAL,BLE_CFG_HTS_TEMPERATURE_INTERVAL_MAX_VALUE,BT_SIG_BEACON,BLE_APPLICATION_TYPE,BT_SIG_BLOOD_PRESSURE_SENSOR,BT_SIG_HEART_RATE_SENSOR,CUSTOM_TEMPLATE,CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER,CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO,CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO,CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION,CFG_HW_RESET_BY_FW,CFG_DEBUGGER_SUPPORTED,CFG_FAST_CONN_ADV_INTERVAL_MIN,CFG_FAST_CONN_ADV_INTERVAL_MAX,CFG_IO_CAPABILITY,CFG_MITM_PROTECTION,CFG_RTCCLK_DIVIDER_CONF,CFG_DEBUG_TRACE_UART,CFG_DEBUG_TRACE_LIGHT
 STM32_WPAN.IPParametersWithoutCheck=BLE_CFG_HTS_TEMPERATURE_INTERVAL_MAX_VALUE
-STM32_WPAN.LOCAL_NAME=HTSTM
-STM32_WPAN.LOCAL_NAME_FORMATTED=,'H','T','S','T','M'
+STM32_WPAN.LOCAL_NAME=BEACON
+STM32_WPAN.LOCAL_NAME_FORMATTED=,'B','E','A','C','O','N'
 USART1.AutoBaudRateEnableParam=UART_ADVFEATURE_AUTOBAUDRATE_DISABLE
 USART1.BaudRate=115200
 USART1.ClockPrescaler=PRESCALER_DIV1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/app_common.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/app_common.h
index 4defc5d7a..836f40dcf 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/app_common.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/app_common.h
@@ -1,12 +1,13 @@
+/* USER CODE BEGIN Header */
 /**
  ******************************************************************************
   * File Name          : app_common.h
   * Description        : App Common application configuration file for STM32WPAN Middleware.
   *
- ******************************************************************************
+  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
@@ -16,7 +17,7 @@
   *
   ******************************************************************************
   */
-
+/* USER CODE END Header */
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef APP_COMMON_H
 #define APP_COMMON_H
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/app_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/app_conf.h
index 175409a3d..44dcaef95 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/app_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/app_conf.h
@@ -1,12 +1,12 @@
+/* USER CODE BEGIN Header */
 /**
  ******************************************************************************
   * File Name          : app_conf.h
   * Description        : Application configuration file for STM32WPAN Middleware.
-  *
- ******************************************************************************
+  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
@@ -16,6 +16,7 @@
   *
   ******************************************************************************
   */
+/* USER CODE END Header */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef APP_CONF_H
@@ -48,11 +49,11 @@
 /**
  * Define IO Authentication
  */
-#define CFG_BONDING_MODE                  (1)
-#define CFG_FIXED_PIN                     (111111)
-#define CFG_USED_FIXED_PIN                (0)
-#define CFG_ENCRYPTION_KEY_SIZE_MAX       (16)
-#define CFG_ENCRYPTION_KEY_SIZE_MIN       (8)
+#define CFG_BONDING_MODE                 (0)
+#define CFG_FIXED_PIN                    (111111)
+#define CFG_USED_FIXED_PIN               (0)
+#define CFG_ENCRYPTION_KEY_SIZE_MAX      (16)
+#define CFG_ENCRYPTION_KEY_SIZE_MIN      (8)
 
 /**
  * Define IO capabilities
@@ -63,7 +64,7 @@
 #define CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT (0x03)
 #define CFG_IO_CAPABILITY_KEYBOARD_DISPLAY   (0x04)
 
-#define CFG_IO_CAPABILITY              CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT
+#define CFG_IO_CAPABILITY               CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT
 
 /**
  * Define MITM modes
@@ -73,6 +74,35 @@
 
 #define CFG_MITM_PROTECTION             CFG_MITM_PROTECTION_REQUIRED
 
+/**
+ * Define Secure Connections Support
+ */
+#define CFG_SECURE_NOT_SUPPORTED       (0x00)
+#define CFG_SECURE_OPTIONAL            (0x01)
+#define CFG_SECURE_MANDATORY           (0x02)
+
+#define CFG_SC_SUPPORT                 CFG_SECURE_OPTIONAL
+
+/**
+ * Define Keypress Notification Support
+ */
+#define CFG_KEYPRESS_NOT_SUPPORTED      (0x00)
+#define CFG_KEYPRESS_SUPPORTED          (0x01)
+
+#define CFG_KEYPRESS_NOTIFICATION_SUPPORT             CFG_KEYPRESS_NOT_SUPPORTED
+   
+/**
+ * Numeric Comparison Answers
+ */   
+#define YES (0x01)
+#define NO  (0x00)
+
+/**
+ * Device name configuration for Generic Access Service
+ */
+#define CFG_GAP_DEVICE_NAME             "TEMPLATE"
+#define CFG_GAP_DEVICE_NAME_LENGTH      (8)
+
 /**
 *   Identity root key used to derive LTK and CSRK
 */
@@ -252,7 +282,7 @@
  * Select UART interfaces
  */
 #define CFG_DEBUG_TRACE_UART    hw_uart1
-#define CFG_CONSOLE_MENU      
+#define CFG_CONSOLE_MENU      0
 /******************************************************************************
  * USB interface
  ******************************************************************************/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/app_debug.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/app_debug.h
new file mode 100644
index 000000000..4224edbe0
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/app_debug.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : app_debug.h
+  * Description        : Header for app_debug.c module
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/hw_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/hw_conf.h
index 6733a683f..5492cbb08 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/hw_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/hw_conf.h
@@ -27,6 +27,34 @@
  * Semaphores
  * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
  *****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
 /* Index of the semaphore used to manage the entry Stop Mode procedure */
 #define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/main.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/main.h
index 55097bac8..4b10d2beb 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/main.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/main.h
@@ -29,6 +29,7 @@ extern "C" {
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32wbxx_hal.h"
+#include "app_conf.h"
 
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/stm32wbxx_hal_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/stm32wbxx_hal_conf.h
index 7f1537260..d5db0e33f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/stm32wbxx_hal_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Inc/stm32wbxx_hal_conf.h
@@ -39,6 +39,7 @@
 /*#define HAL_CRC_MODULE_ENABLED   */
 #define HAL_HSEM_MODULE_ENABLED
 /*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
 #define HAL_IPCC_MODULE_ENABLED
 /*#define HAL_IRDA_MODULE_ENABLED   */
 /*#define HAL_IWDG_MODULE_ENABLED   */
@@ -70,6 +71,7 @@
 #define USE_HAL_COMP_REGISTER_CALLBACKS      0u
 #define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
 #define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
 #define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
 #define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
 #define USE_HAL_PCD_REGISTER_CALLBACKS       0u
@@ -243,6 +245,10 @@
  #include "stm32wbxx_hal_i2c.h"
 #endif /* HAL_I2C_MODULE_ENABLED */
 
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
 #ifdef HAL_IPCC_MODULE_ENABLED
  #include "stm32wbxx_hal_ipcc.h"
 #endif /* HAL_IPCC_MODULE_ENABLED */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/app_debug.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/app_debug.c
new file mode 100644
index 000000000..14ed65c22
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/app_debug.c
@@ -0,0 +1,399 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : app_debug.c
+  * Description        : Debug capabilities source file for STM32WPAN Middleware
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+#ifdef CFG_DEBUG_TRACE_UART
+#if(CFG_HW_LPUART1_ENABLED == 1)
+extern void MX_LPUART1_UART_Init(void);
+#endif
+#if(CFG_HW_USART1_ENABLED == 1)
+extern void MX_USART1_UART_Init(void);
+#endif
+#endif
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+/* USER CODE END PV */
+
+/* Global variables ----------------------------------------------------------*/
+/* USER CODE BEGIN GV */
+/* USER CODE END GV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+/* USER CODE BEGIN APPD_Init */
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+/* USER CODE END APPD_Init */
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+/* USER CODE BEGIN APPD_EnableCPU2 */
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+/* USER CODE END APPD_EnableCPU2 */
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+/* USER CODE BEGIN APPD_SetCPU2GpioConfig */
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+/* USER CODE END APPD_SetCPU2GpioConfig */
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+/* USER CODE BEGIN APPD_BleDtbCfg */
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+/* USER CODE END APPD_BleDtbCfg */
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+/* USER CODE BEGIN DbgOutputInit */
+#ifdef CFG_DEBUG_TRACE_UART
+if (CFG_DEBUG_TRACE_UART == hw_lpuart1)
+{
+#if(CFG_HW_LPUART1_ENABLED == 1)
+    MX_LPUART1_UART_Init();
+#endif
+}
+else if (CFG_DEBUG_TRACE_UART == hw_uart1)
+{
+#if(CFG_HW_USART1_ENABLED == 1)
+    MX_USART1_UART_Init();
+#endif
+}
+#endif
+
+/* USER CODE END DbgOutputInit */
+  return;
+}
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+/* USER CODE END DbgOutputTraces */
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+/* USER CODE END DbgOutputTraces */
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/app_entry.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/app_entry.c
index 7046354ac..4bb965090 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/app_entry.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/app_entry.c
@@ -29,7 +29,7 @@
 #include "stm32_seq.h"
 #include "shci_tl.h"
 #include "stm32_lpm.h"
-#include "dbg_trace.h"
+#include "app_debug.h"
 
 /* Private includes -----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
@@ -66,7 +66,6 @@ PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t BleSpareEvtBuffer[sizeof(TL_
 
 /* Private functions prototypes-----------------------------------------------*/
 static void SystemPower_Config( void );
-static void Init_Debug( void );
 static void appe_Tl_Init( void );
 static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status );
 static void APPE_SysUserEvtRx( void * pPayload );
@@ -91,7 +90,7 @@ void APPE_Init( void )
   HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
 
 /* USER CODE BEGIN APPE_Init_1 */
-  Init_Debug();
+  APPD_Init();
   
   /**
    * The Standby mode should not be entered before the initialization is over
@@ -124,47 +123,6 @@ void APPE_Init( void )
  * LOCAL FUNCTIONS
  *
  *************************************************************/
-static void Init_Debug( void )
-{
-#if (CFG_DEBUGGER_SUPPORTED == 1)
-  /**
-   * Keep debugger enabled while in any low power mode
-   */
-  HAL_DBGMCU_EnableDBGSleepMode();
-
-  /***************** ENABLE DEBUGGER *************************************/
-  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-  LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-
-#else
-
-  GPIO_InitTypeDef gpio_config = {0};
-
-  gpio_config.Pull = GPIO_NOPULL;
-  gpio_config.Mode = GPIO_MODE_ANALOG;
-
-  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOA, &gpio_config);
-  __HAL_RCC_GPIOA_CLK_DISABLE();
-
-  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOB, &gpio_config);
-  __HAL_RCC_GPIOB_CLK_DISABLE();
-
-  HAL_DBGMCU_DisableDBGSleepMode();
-  HAL_DBGMCU_DisableDBGStopMode();
-  HAL_DBGMCU_DisableDBGStandbyMode();
-
-#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
-
-#if(CFG_DEBUG_TRACE != 0)
-  DbgTraceInit();
-#endif
-
-  return;
-}
 
 /**
  * @brief  Configure the system for power optimization
@@ -239,7 +197,7 @@ static void APPE_SysUserEvtRx( void * pPayload )
 {
   UNUSED(pPayload);
   /* Traces channel initialization */
-  TL_TRACES_Init( );
+  APPD_EnableCPU2( );
 
   APP_BLE_Init( );
   UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE);
@@ -322,34 +280,6 @@ void shci_cmd_resp_wait(uint32_t timeout)
   return;
 }
 
-/**
-  * @brief  Initialisation of the trace mechanism
-  * @param  None
-  * @retval None
-  */
-#if(CFG_DEBUG_TRACE != 0)
-void DbgOutputInit( void )
-{
-    MX_USART1_UART_Init();
-
-  return;
-}
-
-/**
-  * @brief  Management of the traces
-  * @param  p_data : data
-  * @param  size : size
-  * @param  call-back :
-  * @retval None
-  */
-void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
-{
-  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
-
-  return;
-}
-#endif
-
 /* USER CODE BEGIN FD_WRAP_FUNCTIONS */
 void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin )
 {
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/hw_timerserver.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/hw_timerserver.c
index c842ba55e..e0e4fcb5d 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/hw_timerserver.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/hw_timerserver.c
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/hw_uart.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/hw_uart.c
index 9a553610d..ce910235c 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/hw_uart.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/hw_uart.c
@@ -6,7 +6,7 @@
   ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/main.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/main.c
index 93e6f5cb3..fffe89652 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/main.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/main.c
@@ -110,7 +110,6 @@ int main(void)
   /* USER CODE BEGIN 1 */
 
   /* USER CODE END 1 */
-  
 
   /* MCU Configuration--------------------------------------------------------*/
 
@@ -139,9 +138,8 @@ int main(void)
 
   /* USER CODE END 2 */
 
-  /* Init code for STM32_WPAN */  
+  /* Init code for STM32_WPAN */
   APPE_Init();
-
   /* Infinite loop */
   /* USER CODE BEGIN WHILE */
 	while(1)
@@ -166,6 +164,7 @@ void SystemClock_Config(void)
 
   /** Configure LSE Drive Capability 
   */
+  HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
   /** Configure the main internal regulator output voltage 
   */
@@ -210,7 +209,6 @@ void SystemClock_Config(void)
   PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
   PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
   PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
-
   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
   {
     Error_Handler();
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/stm32_lpm_if.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/stm32_lpm_if.c
index f024b61e3..1418e0a36 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/stm32_lpm_if.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/stm32_lpm_if.c
@@ -70,6 +70,13 @@ static void Switch_On_HSI( void );
 void PWR_EnterOffMode( void )
 {
 /* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
   /************************************************************************************
    * ENTER OFF MODE
    ***********************************************************************************/
@@ -106,6 +113,8 @@ void PWR_ExitOffMode( void )
 {
 /* USER CODE BEGIN PWR_ExitOffMode */
 
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitOffMode */
 }
 
@@ -118,6 +127,16 @@ void PWR_ExitOffMode( void )
 void PWR_EnterStopMode( void )
 {
 /* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
   /**
    * This function is called from CRITICAL SECTION
    */
@@ -202,6 +221,9 @@ void PWR_ExitStopMode( void )
 
   /* Release RCC semaphore */
   LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitStopMode */
 }
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/stm32wbxx_hal_msp.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/stm32wbxx_hal_msp.c
index f22ad0f38..fc4e64f31 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/stm32wbxx_hal_msp.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/Core/Src/stm32wbxx_hal_msp.c
@@ -293,6 +293,7 @@ void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
   /* USER CODE END RTC_MspInit 0 */
     /* Peripheral clock enable */
     __HAL_RCC_RTC_ENABLE();
+    __HAL_RCC_RTCAPB_CLK_ENABLE();
   /* USER CODE BEGIN RTC_MspInit 1 */
   HAL_RTCEx_EnableBypassShadow(hrtc);
   /* USER CODE END RTC_MspInit 1 */
@@ -315,6 +316,7 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
   /* USER CODE END RTC_MspDeInit 0 */
     /* Peripheral clock disable */
     __HAL_RCC_RTC_DISABLE();
+    __HAL_RCC_RTCAPB_CLK_DISABLE();
   /* USER CODE BEGIN RTC_MspDeInit 1 */
 
   /* USER CODE END RTC_MspDeInit 1 */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/EWARM/ble_beacon.ewp b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/EWARM/ble_beacon.ewp
index 2768071da..32f1426a6 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/EWARM/ble_beacon.ewp
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/EWARM/ble_beacon.ewp
@@ -1052,6 +1052,9 @@
         
           $PROJ_DIR$\..\Core\Src\main.c
         
+        
+          $PROJ_DIR$\..\Core\Src\app_debug.c
+        
         
           $PROJ_DIR$\..\Core\Src\app_entry.c
         
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/MDK-ARM/BLE_Beacon.uvprojx b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/MDK-ARM/BLE_Beacon.uvprojx
index c421b8d7d..69b46b080 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/MDK-ARM/BLE_Beacon.uvprojx
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/MDK-ARM/BLE_Beacon.uvprojx
@@ -420,6 +420,11 @@
               1
               ../Core/Src/main.c
             
+            
+              app_debug.c
+              1
+              ../Core/Src/app_debug.c
+            
             
               app_entry.c
               1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/ble_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/ble_conf.h
index f93ff7755..1174c267f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/ble_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/ble_conf.h
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/ble_dbg_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/ble_dbg_conf.h
index 960afbb00..e7839825c 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/ble_dbg_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/ble_dbg_conf.h
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_beacon.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_beacon.h
index 2f111498f..7854a19e2 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_beacon.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_beacon.h
@@ -5,7 +5,7 @@
   ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_tlm_service.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_tlm_service.c
index 7b9a5ccee..bea07028e 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_tlm_service.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_tlm_service.c
@@ -5,7 +5,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_tlm_service.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_tlm_service.h
index a4edb5986..2a4f41dbc 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_tlm_service.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_tlm_service.h
@@ -5,7 +5,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_uid_service.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_uid_service.c
index 41a385513..b651b54e5 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_uid_service.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_uid_service.c
@@ -5,7 +5,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_uid_service.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_uid_service.h
index e799cfd0d..11cfdec8d 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_uid_service.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_uid_service.h
@@ -5,7 +5,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_url_service.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_url_service.c
index d4116ff93..9fe558a7f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_url_service.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_url_service.c
@@ -5,7 +5,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_url_service.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_url_service.h
index 626a08be3..108dd52a6 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_url_service.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/App/eddystone_url_service.h
@@ -5,7 +5,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/Target/hw_ipcc.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/Target/hw_ipcc.c
index a0d8b3b5b..c6e1ca97a 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/Target/hw_ipcc.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/STM32_WPAN/Target/hw_ipcc.c
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/SW4STM32/BLE_Beacon/.project b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/SW4STM32/BLE_Beacon/.project
index 3c49a6a5e..c5ceecb9e 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/SW4STM32/BLE_Beacon/.project
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/SW4STM32/BLE_Beacon/.project
@@ -39,6 +39,11 @@
 			1
 			PARENT-2-PROJECT_LOC/Core/Src/main.c
 		
+	
+			Application/User/Core/app_debug.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/app_debug.c
+		
     
 			Application/User/Core/app_entry.c
 			1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/SW4STM32/BLE_Beacon/stm32wb55xx_flash_cm4.ld b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/SW4STM32/BLE_Beacon/stm32wb55xx_flash_cm4.ld
index a9ccd801e..7ac9a391f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/SW4STM32/BLE_Beacon/stm32wb55xx_flash_cm4.ld
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/SW4STM32/BLE_Beacon/stm32wb55xx_flash_cm4.ld
@@ -50,7 +50,7 @@ ENTRY(Reset_Handler)
 _estack = 0x20030000;    /* end of RAM */
 /* Generate a link error if heap and stack don't fit into RAM */
 _Min_Heap_Size = 0x400;      /* required amount of heap  */
-_Min_Stack_Size = 0x1000; /* required amount of stack */
+_Min_Stack_Size = 0x1000;   /* required amount of stack */
 
 /* Specify the memory areas */
 MEMORY
@@ -181,7 +181,7 @@ SECTIONS
   .ARM.attributes 0       : { *(.ARM.attributes) }
    MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
    MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
-   MB_MEM2                : { *(MB_MEM2) } >RAM_SHARED  
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
 }
 
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/SW4STM32/startup_stm32wb55xx_cm4.s b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/SW4STM32/startup_stm32wb55xx_cm4.s
index 023c1b016..f79eec117 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/SW4STM32/startup_stm32wb55xx_cm4.s
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Beacon/SW4STM32/startup_stm32wb55xx_cm4.s
@@ -44,21 +44,29 @@ defined in linker script */
 .word	_sbss
 /* end address for the .bss section. defined in linker script */
 .word	_ebss
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
   movs r3, #0
-  b	LoopCopyDataInit
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
 
+.section  .text.data_initializers
 CopyDataInit:
   ldr r4, [r2, r3]
   str r4, [r0, r3]
@@ -67,21 +75,31 @@ CopyDataInit:
 LoopCopyDataInit:
   adds r4, r0, r3
   cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
+  bcc  CopyDataInit
+  bx lr
 
 FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
+  str  r3, [r0]
+  adds r0, r0, #4
 
 LoopFillZerobss:
-  cmp r2, r4
+  cmp r0, r1
   bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/BLE_BloodPressure.ioc b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/BLE_BloodPressure.ioc
index 7e16e0dd3..52be49417 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/BLE_BloodPressure.ioc
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/BLE_BloodPressure.ioc
@@ -94,8 +94,8 @@ Mcu.PinsNb=17
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32WB55RGVx
-MxCube.Version=5.5.0
-MxDb.Version=DB.5.0.50
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.DMA1_Channel4_IRQn=true\:15\:0\:true\:false\:true\:false\:true
 NVIC.DMA2_Channel4_IRQn=true\:15\:0\:true\:false\:true\:false\:true
@@ -157,14 +157,6 @@ PCC.Ble.ConnectionInterval=1000.0
 PCC.Ble.DataLength=6
 PCC.Ble.Mode=Advertising
 PCC.Ble.PowerLevel=Min
-PCC.Checker=true
-PCC.Line=STM32WBx5
-PCC.MCU=STM32WB55RGVx
-PCC.PartNumber=STM32WB55RGVx
-PCC.Seq0=0
-PCC.Series=STM32WB
-PCC.Temperature=25
-PCC.Vdd=3.0
 PinOutPanel.RotationAngle=0
 ProjectManager.AskForMigrate=true
 ProjectManager.BackupPrevious=false
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/app_common.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/app_common.h
index 4defc5d7a..836f40dcf 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/app_common.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/app_common.h
@@ -1,12 +1,13 @@
+/* USER CODE BEGIN Header */
 /**
  ******************************************************************************
   * File Name          : app_common.h
   * Description        : App Common application configuration file for STM32WPAN Middleware.
   *
- ******************************************************************************
+  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
@@ -16,7 +17,7 @@
   *
   ******************************************************************************
   */
-
+/* USER CODE END Header */
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef APP_COMMON_H
 #define APP_COMMON_H
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/app_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/app_conf.h
index 35119e8e2..30b9e42c2 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/app_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/app_conf.h
@@ -1,12 +1,12 @@
+/* USER CODE BEGIN Header */
 /**
  ******************************************************************************
   * File Name          : app_conf.h
   * Description        : Application configuration file for STM32WPAN Middleware.
-  *
- ******************************************************************************
+  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
@@ -16,6 +16,7 @@
   *
   ******************************************************************************
   */
+/* USER CODE END Header */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef APP_CONF_H
@@ -48,11 +49,11 @@
 /**
  * Define IO Authentication
  */
-#define CFG_BONDING_MODE                  (1)
-#define CFG_FIXED_PIN                     (111111)
-#define CFG_USED_FIXED_PIN                (0)
-#define CFG_ENCRYPTION_KEY_SIZE_MAX       (16)
-#define CFG_ENCRYPTION_KEY_SIZE_MIN       (8)
+#define CFG_BONDING_MODE                 (0)
+#define CFG_FIXED_PIN                    (111111)
+#define CFG_USED_FIXED_PIN               (0)
+#define CFG_ENCRYPTION_KEY_SIZE_MAX      (16)
+#define CFG_ENCRYPTION_KEY_SIZE_MIN      (8)
 
 /**
  * Define IO capabilities
@@ -63,7 +64,7 @@
 #define CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT (0x03)
 #define CFG_IO_CAPABILITY_KEYBOARD_DISPLAY   (0x04)
 
-#define CFG_IO_CAPABILITY              CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT
+#define CFG_IO_CAPABILITY               CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT
 
 /**
  * Define MITM modes
@@ -73,6 +74,35 @@
 
 #define CFG_MITM_PROTECTION             CFG_MITM_PROTECTION_REQUIRED
 
+/**
+ * Define Secure Connections Support
+ */
+#define CFG_SECURE_NOT_SUPPORTED       (0x00)
+#define CFG_SECURE_OPTIONAL            (0x01)
+#define CFG_SECURE_MANDATORY           (0x02)
+
+#define CFG_SC_SUPPORT                 CFG_SECURE_OPTIONAL
+
+/**
+ * Define Keypress Notification Support
+ */
+#define CFG_KEYPRESS_NOT_SUPPORTED      (0x00)
+#define CFG_KEYPRESS_SUPPORTED          (0x01)
+
+#define CFG_KEYPRESS_NOTIFICATION_SUPPORT             CFG_KEYPRESS_NOT_SUPPORTED
+   
+/**
+ * Numeric Comparison Answers
+ */   
+#define YES (0x01)
+#define NO  (0x00)
+
+/**
+ * Device name configuration for Generic Access Service
+ */
+#define CFG_GAP_DEVICE_NAME             "TEMPLATE"
+#define CFG_GAP_DEVICE_NAME_LENGTH      (8)
+
 /**
  * Define PHY
  */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/app_debug.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/app_debug.h
new file mode 100644
index 000000000..4224edbe0
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/app_debug.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : app_debug.h
+  * Description        : Header for app_debug.c module
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/hw_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/hw_conf.h
index 0742a745f..dde8e773f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/hw_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/hw_conf.h
@@ -27,6 +27,34 @@
  * Semaphores
  * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
  *****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
 /* Index of the semaphore used to manage the entry Stop Mode procedure */
 #define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/main.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/main.h
index 55097bac8..4b10d2beb 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/main.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/main.h
@@ -29,6 +29,7 @@ extern "C" {
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32wbxx_hal.h"
+#include "app_conf.h"
 
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/stm32wbxx_hal_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/stm32wbxx_hal_conf.h
index 7f1537260..d5db0e33f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/stm32wbxx_hal_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Inc/stm32wbxx_hal_conf.h
@@ -39,6 +39,7 @@
 /*#define HAL_CRC_MODULE_ENABLED   */
 #define HAL_HSEM_MODULE_ENABLED
 /*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
 #define HAL_IPCC_MODULE_ENABLED
 /*#define HAL_IRDA_MODULE_ENABLED   */
 /*#define HAL_IWDG_MODULE_ENABLED   */
@@ -70,6 +71,7 @@
 #define USE_HAL_COMP_REGISTER_CALLBACKS      0u
 #define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
 #define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
 #define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
 #define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
 #define USE_HAL_PCD_REGISTER_CALLBACKS       0u
@@ -243,6 +245,10 @@
  #include "stm32wbxx_hal_i2c.h"
 #endif /* HAL_I2C_MODULE_ENABLED */
 
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
 #ifdef HAL_IPCC_MODULE_ENABLED
  #include "stm32wbxx_hal_ipcc.h"
 #endif /* HAL_IPCC_MODULE_ENABLED */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/app_debug.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/app_debug.c
new file mode 100644
index 000000000..14ed65c22
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/app_debug.c
@@ -0,0 +1,399 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : app_debug.c
+  * Description        : Debug capabilities source file for STM32WPAN Middleware
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+#ifdef CFG_DEBUG_TRACE_UART
+#if(CFG_HW_LPUART1_ENABLED == 1)
+extern void MX_LPUART1_UART_Init(void);
+#endif
+#if(CFG_HW_USART1_ENABLED == 1)
+extern void MX_USART1_UART_Init(void);
+#endif
+#endif
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+/* USER CODE END PV */
+
+/* Global variables ----------------------------------------------------------*/
+/* USER CODE BEGIN GV */
+/* USER CODE END GV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+/* USER CODE BEGIN APPD_Init */
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+/* USER CODE END APPD_Init */
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+/* USER CODE BEGIN APPD_EnableCPU2 */
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+/* USER CODE END APPD_EnableCPU2 */
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+/* USER CODE BEGIN APPD_SetCPU2GpioConfig */
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+/* USER CODE END APPD_SetCPU2GpioConfig */
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+/* USER CODE BEGIN APPD_BleDtbCfg */
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+/* USER CODE END APPD_BleDtbCfg */
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+/* USER CODE BEGIN DbgOutputInit */
+#ifdef CFG_DEBUG_TRACE_UART
+if (CFG_DEBUG_TRACE_UART == hw_lpuart1)
+{
+#if(CFG_HW_LPUART1_ENABLED == 1)
+    MX_LPUART1_UART_Init();
+#endif
+}
+else if (CFG_DEBUG_TRACE_UART == hw_uart1)
+{
+#if(CFG_HW_USART1_ENABLED == 1)
+    MX_USART1_UART_Init();
+#endif
+}
+#endif
+
+/* USER CODE END DbgOutputInit */
+  return;
+}
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+/* USER CODE END DbgOutputTraces */
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+/* USER CODE END DbgOutputTraces */
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/app_entry.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/app_entry.c
index 7046354ac..4bb965090 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/app_entry.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/app_entry.c
@@ -29,7 +29,7 @@
 #include "stm32_seq.h"
 #include "shci_tl.h"
 #include "stm32_lpm.h"
-#include "dbg_trace.h"
+#include "app_debug.h"
 
 /* Private includes -----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
@@ -66,7 +66,6 @@ PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t BleSpareEvtBuffer[sizeof(TL_
 
 /* Private functions prototypes-----------------------------------------------*/
 static void SystemPower_Config( void );
-static void Init_Debug( void );
 static void appe_Tl_Init( void );
 static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status );
 static void APPE_SysUserEvtRx( void * pPayload );
@@ -91,7 +90,7 @@ void APPE_Init( void )
   HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
 
 /* USER CODE BEGIN APPE_Init_1 */
-  Init_Debug();
+  APPD_Init();
   
   /**
    * The Standby mode should not be entered before the initialization is over
@@ -124,47 +123,6 @@ void APPE_Init( void )
  * LOCAL FUNCTIONS
  *
  *************************************************************/
-static void Init_Debug( void )
-{
-#if (CFG_DEBUGGER_SUPPORTED == 1)
-  /**
-   * Keep debugger enabled while in any low power mode
-   */
-  HAL_DBGMCU_EnableDBGSleepMode();
-
-  /***************** ENABLE DEBUGGER *************************************/
-  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-  LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-
-#else
-
-  GPIO_InitTypeDef gpio_config = {0};
-
-  gpio_config.Pull = GPIO_NOPULL;
-  gpio_config.Mode = GPIO_MODE_ANALOG;
-
-  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOA, &gpio_config);
-  __HAL_RCC_GPIOA_CLK_DISABLE();
-
-  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOB, &gpio_config);
-  __HAL_RCC_GPIOB_CLK_DISABLE();
-
-  HAL_DBGMCU_DisableDBGSleepMode();
-  HAL_DBGMCU_DisableDBGStopMode();
-  HAL_DBGMCU_DisableDBGStandbyMode();
-
-#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
-
-#if(CFG_DEBUG_TRACE != 0)
-  DbgTraceInit();
-#endif
-
-  return;
-}
 
 /**
  * @brief  Configure the system for power optimization
@@ -239,7 +197,7 @@ static void APPE_SysUserEvtRx( void * pPayload )
 {
   UNUSED(pPayload);
   /* Traces channel initialization */
-  TL_TRACES_Init( );
+  APPD_EnableCPU2( );
 
   APP_BLE_Init( );
   UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE);
@@ -322,34 +280,6 @@ void shci_cmd_resp_wait(uint32_t timeout)
   return;
 }
 
-/**
-  * @brief  Initialisation of the trace mechanism
-  * @param  None
-  * @retval None
-  */
-#if(CFG_DEBUG_TRACE != 0)
-void DbgOutputInit( void )
-{
-    MX_USART1_UART_Init();
-
-  return;
-}
-
-/**
-  * @brief  Management of the traces
-  * @param  p_data : data
-  * @param  size : size
-  * @param  call-back :
-  * @retval None
-  */
-void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
-{
-  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
-
-  return;
-}
-#endif
-
 /* USER CODE BEGIN FD_WRAP_FUNCTIONS */
 void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin )
 {
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/hw_timerserver.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/hw_timerserver.c
index c842ba55e..e0e4fcb5d 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/hw_timerserver.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/hw_timerserver.c
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/hw_uart.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/hw_uart.c
index 9a553610d..ce910235c 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/hw_uart.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/hw_uart.c
@@ -6,7 +6,7 @@
   ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/main.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/main.c
index 93e6f5cb3..fffe89652 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/main.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/main.c
@@ -110,7 +110,6 @@ int main(void)
   /* USER CODE BEGIN 1 */
 
   /* USER CODE END 1 */
-  
 
   /* MCU Configuration--------------------------------------------------------*/
 
@@ -139,9 +138,8 @@ int main(void)
 
   /* USER CODE END 2 */
 
-  /* Init code for STM32_WPAN */  
+  /* Init code for STM32_WPAN */
   APPE_Init();
-
   /* Infinite loop */
   /* USER CODE BEGIN WHILE */
 	while(1)
@@ -166,6 +164,7 @@ void SystemClock_Config(void)
 
   /** Configure LSE Drive Capability 
   */
+  HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
   /** Configure the main internal regulator output voltage 
   */
@@ -210,7 +209,6 @@ void SystemClock_Config(void)
   PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
   PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
   PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
-
   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
   {
     Error_Handler();
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/stm32_lpm_if.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/stm32_lpm_if.c
index f024b61e3..1418e0a36 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/stm32_lpm_if.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/stm32_lpm_if.c
@@ -70,6 +70,13 @@ static void Switch_On_HSI( void );
 void PWR_EnterOffMode( void )
 {
 /* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
   /************************************************************************************
    * ENTER OFF MODE
    ***********************************************************************************/
@@ -106,6 +113,8 @@ void PWR_ExitOffMode( void )
 {
 /* USER CODE BEGIN PWR_ExitOffMode */
 
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitOffMode */
 }
 
@@ -118,6 +127,16 @@ void PWR_ExitOffMode( void )
 void PWR_EnterStopMode( void )
 {
 /* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
   /**
    * This function is called from CRITICAL SECTION
    */
@@ -202,6 +221,9 @@ void PWR_ExitStopMode( void )
 
   /* Release RCC semaphore */
   LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitStopMode */
 }
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/stm32wbxx_hal_msp.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/stm32wbxx_hal_msp.c
index f22ad0f38..fc4e64f31 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/stm32wbxx_hal_msp.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/Core/Src/stm32wbxx_hal_msp.c
@@ -293,6 +293,7 @@ void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
   /* USER CODE END RTC_MspInit 0 */
     /* Peripheral clock enable */
     __HAL_RCC_RTC_ENABLE();
+    __HAL_RCC_RTCAPB_CLK_ENABLE();
   /* USER CODE BEGIN RTC_MspInit 1 */
   HAL_RTCEx_EnableBypassShadow(hrtc);
   /* USER CODE END RTC_MspInit 1 */
@@ -315,6 +316,7 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
   /* USER CODE END RTC_MspDeInit 0 */
     /* Peripheral clock disable */
     __HAL_RCC_RTC_DISABLE();
+    __HAL_RCC_RTCAPB_CLK_DISABLE();
   /* USER CODE BEGIN RTC_MspDeInit 1 */
 
   /* USER CODE END RTC_MspDeInit 1 */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/EWARM/BLE_BloodPressure.ewp b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/EWARM/BLE_BloodPressure.ewp
index cb9432ed9..ae01c321e 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/EWARM/BLE_BloodPressure.ewp
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/EWARM/BLE_BloodPressure.ewp
@@ -1052,6 +1052,9 @@
         
           $PROJ_DIR$\..\Core\Src\main.c
         
+        
+          $PROJ_DIR$\..\Core\Src\app_debug.c
+        
         
           $PROJ_DIR$\..\Core\Src\app_entry.c
         
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/MDK-ARM/BLE_BloodPressure.uvprojx b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/MDK-ARM/BLE_BloodPressure.uvprojx
index a583c2c6b..1244ad5bd 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/MDK-ARM/BLE_BloodPressure.uvprojx
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/MDK-ARM/BLE_BloodPressure.uvprojx
@@ -420,6 +420,11 @@
               1
               ../Core/Src/main.c
             
+            
+              app_debug.c
+              1
+              ../Core/Src/app_debug.c
+            
             
               app_entry.c
               1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/STM32_WPAN/App/app_ble.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/STM32_WPAN/App/app_ble.c
index 67fce5ba0..c03a38378 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/STM32_WPAN/App/app_ble.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/STM32_WPAN/App/app_ble.c
@@ -378,7 +378,7 @@ SVCCTL_UserEvtFlowStatus_t SVCCTL_App_Notification( void *pckt )
       /* USER CODE END EVT_LE_META_EVENT */
       switch (meta_evt->subevent)
       {
-        case EVT_LE_CONN_UPDATE_COMPLETE: 
+        case EVT_LE_CONN_UPDATE_COMPLETE:
           APP_DBG_MSG("\r\n\r** CONNECTION UPDATE EVENT WITH CLIENT \n");
 
           /* USER CODE BEGIN EVT_LE_CONN_UPDATE_COMPLETE */
@@ -670,11 +670,11 @@ static void Ble_Hci_Gap_Gatt_Init(void){
    */
   BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode = CFG_MITM_PROTECTION;
   BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data_Present = 0;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin = 8;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax = 16;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin = 1;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin = 111111;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode = 1;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin = CFG_ENCRYPTION_KEY_SIZE_MIN;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax = CFG_ENCRYPTION_KEY_SIZE_MAX;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin = CFG_USED_FIXED_PIN;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin = CFG_FIXED_PIN;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode = CFG_BONDING_MODE;
   for (index = 0; index < 16; index++)
   {
     BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data[index] = (uint8_t) index;
@@ -682,14 +682,14 @@ static void Ble_Hci_Gap_Gatt_Init(void){
 
   aci_gap_set_authentication_requirement(BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode,
-                                         1,
-                                         0,
+                                         CFG_SC_SUPPORT,
+                                         CFG_KEYPRESS_NOTIFICATION_SUPPORT,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin,
-                                         0
-                                        );
+                                         PUBLIC_ADDR
+                                         );
 
   /**
    * Initialize whitelist
@@ -754,6 +754,7 @@ static void Adv_Request(APP_BLE_ConnStatus_t New_Status)
         BleApplicationContext.BleApplicationContext_legacy.advtServUUID,
         0,
         0);
+
     if (ret == BLE_STATUS_SUCCESS)
     {
       if (New_Status == APP_BLE_FAST_ADV)
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/STM32_WPAN/App/ble_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/STM32_WPAN/App/ble_conf.h
index 14b543793..924d6822d 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/STM32_WPAN/App/ble_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/STM32_WPAN/App/ble_conf.h
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/STM32_WPAN/App/ble_dbg_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/STM32_WPAN/App/ble_dbg_conf.h
index db335dc11..42f015a83 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/STM32_WPAN/App/ble_dbg_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/STM32_WPAN/App/ble_dbg_conf.h
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/STM32_WPAN/Target/hw_ipcc.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/STM32_WPAN/Target/hw_ipcc.c
index a0d8b3b5b..c6e1ca97a 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/STM32_WPAN/Target/hw_ipcc.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/STM32_WPAN/Target/hw_ipcc.c
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/SW4STM32/BLE_BloodPressure/.project b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/SW4STM32/BLE_BloodPressure/.project
index 6ea49330c..068c3d2bb 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/SW4STM32/BLE_BloodPressure/.project
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/SW4STM32/BLE_BloodPressure/.project
@@ -39,6 +39,11 @@
 			1
 			PARENT-2-PROJECT_LOC/Core/Src/main.c
 		
+	
+			Application/User/Core/app_debug.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/app_debug.c
+		
     
 			Application/User/Core/app_entry.c
 			1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/SW4STM32/BLE_BloodPressure/stm32wb55xx_flash_cm4.ld b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/SW4STM32/BLE_BloodPressure/stm32wb55xx_flash_cm4.ld
index a9ccd801e..7ac9a391f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/SW4STM32/BLE_BloodPressure/stm32wb55xx_flash_cm4.ld
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/SW4STM32/BLE_BloodPressure/stm32wb55xx_flash_cm4.ld
@@ -50,7 +50,7 @@ ENTRY(Reset_Handler)
 _estack = 0x20030000;    /* end of RAM */
 /* Generate a link error if heap and stack don't fit into RAM */
 _Min_Heap_Size = 0x400;      /* required amount of heap  */
-_Min_Stack_Size = 0x1000; /* required amount of stack */
+_Min_Stack_Size = 0x1000;   /* required amount of stack */
 
 /* Specify the memory areas */
 MEMORY
@@ -181,7 +181,7 @@ SECTIONS
   .ARM.attributes 0       : { *(.ARM.attributes) }
    MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
    MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
-   MB_MEM2                : { *(MB_MEM2) } >RAM_SHARED  
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
 }
 
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/SW4STM32/startup_stm32wb55xx_cm4.s b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/SW4STM32/startup_stm32wb55xx_cm4.s
index 023c1b016..f79eec117 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/SW4STM32/startup_stm32wb55xx_cm4.s
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_BloodPressure/SW4STM32/startup_stm32wb55xx_cm4.s
@@ -44,21 +44,29 @@ defined in linker script */
 .word	_sbss
 /* end address for the .bss section. defined in linker script */
 .word	_ebss
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
   movs r3, #0
-  b	LoopCopyDataInit
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
 
+.section  .text.data_initializers
 CopyDataInit:
   ldr r4, [r2, r3]
   str r4, [r0, r3]
@@ -67,21 +75,31 @@ CopyDataInit:
 LoopCopyDataInit:
   adds r4, r0, r3
   cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
+  bcc  CopyDataInit
+  bx lr
 
 FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
+  str  r3, [r0]
+  adds r0, r0, #4
 
 LoopFillZerobss:
-  cmp r2, r4
+  cmp r0, r1
   bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Inc/app_debug.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Inc/app_debug.h
new file mode 100644
index 000000000..13485c16b
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Inc/app_debug.h
@@ -0,0 +1,45 @@
+
+/**
+  ******************************************************************************
+  * @file    app_debug.h
+  * @author  MCD Application Team
+  * @brief   Interface to support debug in the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+  /* Exported types ------------------------------------------------------------*/
+  /* Exported constants --------------------------------------------------------*/
+  /* External variables --------------------------------------------------------*/
+  /* Exported macros -----------------------------------------------------------*/
+  /* Exported functions ------------------------------------------------------- */
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Inc/hw_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Inc/hw_conf.h
index 9e679a33c..0a91cad1a 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Inc/hw_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Inc/hw_conf.h
@@ -23,9 +23,37 @@
 #define __HW_CONF_H
 
 /******************************************************************************
- * Semaphores
- * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
- *****************************************************************************/
+* Semaphores
+* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
+*****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
 /* Index of the semaphore used to manage the entry Stop Mode procedure */
 #define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Src/app_debug.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Src/app_debug.c
new file mode 100644
index 000000000..246173ae6
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Src/app_debug.c
@@ -0,0 +1,349 @@
+/**
+ ******************************************************************************
+ * @file    app_debug.c
+ * @author  MCD Application Team
+ * @brief   Debug capabilities
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+  HW_UART_Init(CFG_DEBUG_TRACE_UART);
+  return;
+}
+
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Src/app_entry.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Src/app_entry.c
index c33612b59..4392d13ff 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Src/app_entry.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Src/app_entry.c
@@ -33,7 +33,7 @@
 #include "stm32_lpm.h"
 
 
-#include "dbg_trace.h"
+#include "app_debug.h"
 
 
 /* Private typedef -----------------------------------------------------------*/
@@ -50,7 +50,6 @@ PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t	BleSpareEvtBuffer[sizeof(TL_
 /* Global variables ----------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
 static void SystemPower_Config( void );
-static void Init_Debug( void );
 static void appe_Tl_Init( void );
 static void Led_Init( void );
 static void Button_Init( void );
@@ -64,7 +63,7 @@ void APPE_Init( void )
   
   HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
 
-  Init_Debug();
+  APPD_Init();
 
   /**
    * The Standby mode should not be entered before the initialization is over
@@ -92,48 +91,6 @@ void APPE_Init( void )
  * LOCAL FUNCTIONS
  *
  *************************************************************/
-static void Init_Debug( void )
-{
-#if (CFG_DEBUGGER_SUPPORTED == 1)
-  /**
-   * Keep debugger enabled while in any low power mode
-   */
-  HAL_DBGMCU_EnableDBGSleepMode();
-
-  /***************** ENABLE DEBUGGER *************************************/
-  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-  LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-
-#else
-
-  GPIO_InitTypeDef gpio_config = {0};
-
-  gpio_config.Pull = GPIO_NOPULL;
-  gpio_config.Mode = GPIO_MODE_ANALOG;
-
-  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOA, &gpio_config);
-  __HAL_RCC_GPIOA_CLK_DISABLE();
-
-  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOB, &gpio_config);
-  __HAL_RCC_GPIOB_CLK_DISABLE();
-
-  HAL_DBGMCU_DisableDBGSleepMode();
-  HAL_DBGMCU_DisableDBGStopMode();
-  HAL_DBGMCU_DisableDBGStandbyMode();
-
-#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
-
-#if(CFG_DEBUG_TRACE != 0)
-  DbgTraceInit();
-#endif
-
-  return;
-}
-
 /**
  * @brief  Configure the system for power optimization
  *
@@ -237,7 +194,7 @@ static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status )
 static void APPE_SysUserEvtRx( void * pPayload )
 {
   /**< Traces channel initialization */
-  TL_TRACES_Init( );
+  APPD_EnableCPU2();
 
   UTIL_LPM_SetOffMode(1 << CFG_LPM_APP, UTIL_LPM_ENABLE);
 
@@ -307,22 +264,4 @@ void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin )
   return;
 }
 
-
-#if(CFG_DEBUG_TRACE != 0)
-void DbgOutputInit( void )
-{
-  HW_UART_Init(CFG_DEBUG_TRACE_UART);
-  return;
-}
-
-
-void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
-{
-  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
-
-  return;
-}
-#endif
-
-
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Src/stm32_lpm_if.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Src/stm32_lpm_if.c
index f024b61e3..1418e0a36 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Src/stm32_lpm_if.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/Core/Src/stm32_lpm_if.c
@@ -70,6 +70,13 @@ static void Switch_On_HSI( void );
 void PWR_EnterOffMode( void )
 {
 /* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
   /************************************************************************************
    * ENTER OFF MODE
    ***********************************************************************************/
@@ -106,6 +113,8 @@ void PWR_ExitOffMode( void )
 {
 /* USER CODE BEGIN PWR_ExitOffMode */
 
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitOffMode */
 }
 
@@ -118,6 +127,16 @@ void PWR_ExitOffMode( void )
 void PWR_EnterStopMode( void )
 {
 /* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
   /**
    * This function is called from CRITICAL SECTION
    */
@@ -202,6 +221,9 @@ void PWR_ExitStopMode( void )
 
   /* Release RCC semaphore */
   LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitStopMode */
 }
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/EWARM/BLE_CableReplacement.ewp b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/EWARM/BLE_CableReplacement.ewp
index 395d1caca..83c808cbc 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/EWARM/BLE_CableReplacement.ewp
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/EWARM/BLE_CableReplacement.ewp
@@ -1048,6 +1048,9 @@
             
                 $PROJ_DIR$\..\Core\Src\app_entry.c
             
+            
+                $PROJ_DIR$\..\Core\Src\app_debug.c
+            
             
                 $PROJ_DIR$\..\Core\Src\hw_timerserver.c
             
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/EWARM/startup_stm32wb55xx_cm4.s b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/EWARM/startup_stm32wb55xx_cm4.s
index 79b0e7edd..1f886ff59 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/EWARM/startup_stm32wb55xx_cm4.s
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/EWARM/startup_stm32wb55xx_cm4.s
@@ -1,4 +1,4 @@
-;/********************* COPYRIGHT(c) 2019 STMicroelectronics ********************
+;******************************************************************************
 ;* File Name          : startup_stm32wb55xx_cm4.s
 ;* Author             : MCD Application Team
 ;* Description        : M4 core vector table of the STM32WB55xx devices for the
@@ -13,31 +13,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
 ;*
-;*******************************************************************************
+;******************************************************************************
 ;
 ;
 ; The modules in this file are included in the libraries, and may be replaced
@@ -86,10 +73,10 @@ __vector_table
         DCD     PendSV_Handler                    ; PendSV Handler
         DCD     SysTick_Handler                   ; SysTick Handler
 
-         ; External Interrupts
+        ; External Interrupts
         DCD     WWDG_IRQHandler                   ; Window WatchDog
-        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
-        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
         DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
         DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
         DCD     RCC_IRQHandler                    ; RCC Interrupt
@@ -129,7 +116,7 @@ __vector_table
         DCD     TSC_IRQHandler                    ; TSC Interrupt
         DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
         DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
-        DCD     USB_FS_WKUP_CRS_IRQHandler        ; USB Full speed wakeup
+        DCD     CRS_IRQHandler                    ; CRS interrupt
         DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
         DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
         DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
@@ -156,6 +143,7 @@ __vector_table
 ;; Default interrupt handlers.
 ;;
         THUMB
+
         PUBWEAK Reset_Handler
         SECTION .text:CODE:NOROOT:REORDER(2)
 Reset_Handler
@@ -419,10 +407,10 @@ EXTI15_10_IRQHandler
 RTC_Alarm_IRQHandler
         B RTC_Alarm_IRQHandler
 
-        PUBWEAK USB_FS_WKUP_CRS_IRQHandler
+        PUBWEAK CRS_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
-USB_FS_WKUP_CRS_IRQHandler
-        B USB_FS_WKUP_CRS_IRQHandler
+CRS_IRQHandler
+        B CRS_IRQHandler
 
         PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
@@ -523,6 +511,7 @@ DMA2_Channel7_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMAMUX1_OVR_IRQHandler
         B DMAMUX1_OVR_IRQHandler
+
         END
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/MDK-ARM/BLE_CableReplacement.uvprojx b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/MDK-ARM/BLE_CableReplacement.uvprojx
index 3e92a532f..1fe1bf6af 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/MDK-ARM/BLE_CableReplacement.uvprojx
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/MDK-ARM/BLE_CableReplacement.uvprojx
@@ -406,6 +406,11 @@
               1
               ../Core/Src/main.c
             
+            
+              app_debug.c
+              1
+              ../Core/Src/app_debug.c
+            
             
               stm32wbxx_it.c
               1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/SW4STM32/BLE_CableReplacement/.project b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/SW4STM32/BLE_CableReplacement/.project
index acb5b0c70..dc14fa7f3 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/SW4STM32/BLE_CableReplacement/.project
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/SW4STM32/BLE_CableReplacement/.project
@@ -59,6 +59,11 @@
 			1
 			PARENT-2-PROJECT_LOC/Core/Src/main.c
 		
+    
+			Application/Core/app_debug.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/app_debug.c
+		
     
 			Application/Core/stm32wbxx_it.c
 			1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/SW4STM32/BLE_CableReplacement/stm32wb55xx_flash_cm4.ld b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/SW4STM32/BLE_CableReplacement/stm32wb55xx_flash_cm4.ld
index a9ccd801e..7ac9a391f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/SW4STM32/BLE_CableReplacement/stm32wb55xx_flash_cm4.ld
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/SW4STM32/BLE_CableReplacement/stm32wb55xx_flash_cm4.ld
@@ -50,7 +50,7 @@ ENTRY(Reset_Handler)
 _estack = 0x20030000;    /* end of RAM */
 /* Generate a link error if heap and stack don't fit into RAM */
 _Min_Heap_Size = 0x400;      /* required amount of heap  */
-_Min_Stack_Size = 0x1000; /* required amount of stack */
+_Min_Stack_Size = 0x1000;   /* required amount of stack */
 
 /* Specify the memory areas */
 MEMORY
@@ -181,7 +181,7 @@ SECTIONS
   .ARM.attributes 0       : { *(.ARM.attributes) }
    MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
    MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
-   MB_MEM2                : { *(MB_MEM2) } >RAM_SHARED  
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
 }
 
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/SW4STM32/startup_stm32wb55xx_cm4.s b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/SW4STM32/startup_stm32wb55xx_cm4.s
index 023c1b016..f79eec117 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/SW4STM32/startup_stm32wb55xx_cm4.s
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_CableReplacement/SW4STM32/startup_stm32wb55xx_cm4.s
@@ -44,21 +44,29 @@ defined in linker script */
 .word	_sbss
 /* end address for the .bss section. defined in linker script */
 .word	_ebss
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
   movs r3, #0
-  b	LoopCopyDataInit
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
 
+.section  .text.data_initializers
 CopyDataInit:
   ldr r4, [r2, r3]
   str r4, [r0, r3]
@@ -67,21 +75,31 @@ CopyDataInit:
 LoopCopyDataInit:
   adds r4, r0, r3
   cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
+  bcc  CopyDataInit
+  bx lr
 
 FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
+  str  r3, [r0]
+  adds r0, r0, #4
 
 LoopFillZerobss:
-  cmp r2, r4
+  cmp r0, r1
   bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/app_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/app_conf.h
index 9dbba7b71..7f3d05db4 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/app_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/app_conf.h
@@ -79,6 +79,21 @@
  */
 #define CFG_UNKNOWN_APPEARANCE                  (0)
 #define CFG_GAP_APPEARANCE                      (832)
+ 
+/**
+ * Define PHY
+ */
+#define ALL_PHYS_PREFERENCE                             0x00
+#define RX_2M_PREFERRED                                 0x02
+#define TX_2M_PREFERRED                                 0x02
+#define RX_1M_PREFERRED                                 0x01
+#define TX_1M_PREFERRED                                 0x01
+#define RX_ALL_PHY_PREFERRED                            0x03
+#define TX_ALL_PHY_PREFERRED                            0x03
+#define TX_1M                                           0x01
+#define TX_2M                                           0x02
+#define RX_1M                                           0x01
+#define RX_2M                                           0x02 
    
 /**
 *   Identity root key used to derive LTK and CSRK
@@ -113,6 +128,8 @@
  * When set to 0, the device is peripheral
  */
 #define CFG_BLE_CENTRAL     1
+
+#define CFG_SERVER_ONLY     0
 /**
  * in this specific application, the device is either central
  * or peripheral but cannot be both
@@ -127,6 +144,7 @@
 #endif
 
 #define PUSH_BUTTON_SW1_EXTI_IRQHandler     EXTI4_IRQHandler
+#define PUSH_BUTTON_SW2_EXTI_IRQHandler     EXTI0_IRQHandler
 
 #define CONN_L(x) ((int)(((float)x)/0.625f))
 #define CONN_P(x) ((int)(((float)x)/1.25f))
@@ -152,7 +170,7 @@
  * 4 if LE_CODED
  * or any combination of 1M | 2M | LE_CODED
  */
-#define CFG_TX_PHY    2
+#define CFG_TX_PHY    1
 
 /**
  * RX PHY configuration
@@ -163,13 +181,14 @@
  * 4 if LE_CODED
  * or any combination of 1M | 2M | LE_CODED
  */
-#define CFG_RX_PHY    2
+#define CFG_RX_PHY    1
 
 /**
  * ALL PHYS configuration
  */
 #define CFG_ALL_PHYS    ((!CFG_TX_PHY) + ((!CFG_RX_PHY)*2))
-
+#define L2CAP_SLAVE_LATENCY             0x0000
+#define L2CAP_TIMEOUT_MULTIPLIER        0x1F4
 /******************************************************************************
  * BLE Stack
  ******************************************************************************/
@@ -411,6 +430,7 @@
 
 /** tick timer value in us */
 #define CFG_TS_TICK_VAL           DIVR( (CFG_RTCCLK_DIV * 1000000), HSE_VALUE/32 )
+//#define CFG_TS_TICK_VAL           DIVR( (CFG_RTCCLK_DIV * 1000000), LSE_VALUE )
 typedef enum
 {
     CFG_TIM_PROC_ID_ISR,
@@ -515,8 +535,10 @@ typedef enum
 typedef enum
 {
   CFG_TASK_DATA_TRANSFER_UPDATE_ID,
+  CFG_TASK_DATA_WRITE_ID,
   CFG_TASK_CONN_DEV_1_ID,
   CFG_TASK_BUTTON_ID,
+  CFG_TASK_SW2_BUTTON_PUSHED_ID,
   CFG_TASK_START_ADV_ID,
   CFG_TASK_START_SCAN_ID,
   CFG_TASK_LINK_CONFIG_ID,
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/app_debug.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/app_debug.h
new file mode 100644
index 000000000..13485c16b
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/app_debug.h
@@ -0,0 +1,45 @@
+
+/**
+  ******************************************************************************
+  * @file    app_debug.h
+  * @author  MCD Application Team
+  * @brief   Interface to support debug in the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+  /* Exported types ------------------------------------------------------------*/
+  /* Exported constants --------------------------------------------------------*/
+  /* External variables --------------------------------------------------------*/
+  /* Exported macros -----------------------------------------------------------*/
+  /* Exported functions ------------------------------------------------------- */
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/hw_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/hw_conf.h
index 130af82bc..1e2d7a616 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/hw_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/hw_conf.h
@@ -23,9 +23,37 @@
 #define __HW_CONF_H
 
 /******************************************************************************
- * Semaphores
- * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
- *****************************************************************************/
+* Semaphores
+* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
+*****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
 /* Index of the semaphore used to manage the entry Stop Mode procedure */
 #define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/main.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/main.h
index bbe71a4da..4b98bcca3 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/main.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/main.h
@@ -24,7 +24,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32wbxx_hal.h"
-
+void Error_Handler(void);
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
 /* Exported variables --------------------------------------------------------*/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/app_debug.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/app_debug.c
new file mode 100644
index 000000000..2f6c2375e
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/app_debug.c
@@ -0,0 +1,363 @@
+/**
+ ******************************************************************************
+ * @file    app_debug.c
+ * @author  MCD Application Team
+ * @brief   Debug capabilities
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+
+typedef PACKED_STRUCT
+{
+  uint8_t thread_config;
+  uint8_t ble_config;
+  uint8_t mac_802_15_4;
+  uint8_t reserved;
+} APPD_TracesConfig_t;
+
+typedef PACKED_STRUCT
+{
+  uint8_t ble_dtb_cfg;
+  uint8_t reserved[3];
+} APPD_GeneralConfig_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static APPD_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static APPD_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOB, LL_GPIO_PIN_1, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+  HW_UART_Init(CFG_DEBUG_TRACE_UART);
+  return;
+}
+
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/app_entry.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/app_entry.c
index c33612b59..f4721f475 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/app_entry.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/app_entry.c
@@ -32,8 +32,7 @@
 #include "shci_tl.h"
 #include "stm32_lpm.h"
 
-
-#include "dbg_trace.h"
+#include "app_debug.h"
 
 
 /* Private typedef -----------------------------------------------------------*/
@@ -50,13 +49,18 @@ PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t	BleSpareEvtBuffer[sizeof(TL_
 /* Global variables ----------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
 static void SystemPower_Config( void );
-static void Init_Debug( void );
 static void appe_Tl_Init( void );
 static void Led_Init( void );
 static void Button_Init( void );
 static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status );
 static void APPE_SysUserEvtRx( void * pPayload );
 
+#if (CFG_HW_LPUART1_ENABLED == 1)
+extern void MX_LPUART1_UART_Init(void);
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+extern void MX_USART1_UART_Init(void);
+#endif
 /* Functions Definition ------------------------------------------------------*/
 void APPE_Init( void )
 {
@@ -64,7 +68,7 @@ void APPE_Init( void )
   
   HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
 
-  Init_Debug();
+  APPD_Init();
 
   /**
    * The Standby mode should not be entered before the initialization is over
@@ -80,60 +84,23 @@ void APPE_Init( void )
 
   /**
    * From now, the application is waiting for the ready event ( VS_HCI_C2_Ready )
-   * received on the system channel before starting the Stack
+   * received on the system channel before starting the BLE Stack
    * This system event is received with APPE_SysUserEvtRx()
    */
+/* USER CODE BEGIN APPE_Init_2 */
 
-  return;
+/* USER CODE END APPE_Init_2 */
+   return;
 }
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
 
 /*************************************************************
  *
  * LOCAL FUNCTIONS
  *
  *************************************************************/
-static void Init_Debug( void )
-{
-#if (CFG_DEBUGGER_SUPPORTED == 1)
-  /**
-   * Keep debugger enabled while in any low power mode
-   */
-  HAL_DBGMCU_EnableDBGSleepMode();
-
-  /***************** ENABLE DEBUGGER *************************************/
-  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-  LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-
-#else
-
-  GPIO_InitTypeDef gpio_config = {0};
-
-  gpio_config.Pull = GPIO_NOPULL;
-  gpio_config.Mode = GPIO_MODE_ANALOG;
-
-  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOA, &gpio_config);
-  __HAL_RCC_GPIOA_CLK_DISABLE();
-
-  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOB, &gpio_config);
-  __HAL_RCC_GPIOB_CLK_DISABLE();
-
-  HAL_DBGMCU_DisableDBGSleepMode();
-  HAL_DBGMCU_DisableDBGStopMode();
-  HAL_DBGMCU_DisableDBGStandbyMode();
-
-#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
-
-#if(CFG_DEBUG_TRACE != 0)
-  DbgTraceInit();
-#endif
-
-  return;
-}
-
 /**
  * @brief  Configure the system for power optimization
  *
@@ -167,7 +134,6 @@ static void appe_Tl_Init( void )
 {
   TL_MM_Config_t tl_mm_config;
   SHCI_TL_HciInitConf_t SHci_Tl_Init_Conf;
-
   /**< Reference table initialization */
   TL_Init();
 
@@ -189,6 +155,35 @@ static void appe_Tl_Init( void )
   return;
 }
 
+
+
+static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status )
+{
+  UNUSED(status);
+  return;
+}
+
+/**
+ * The type of the payload for a system user event is tSHCI_UserEvtRxParam
+ * When the system event is both :
+ *    - a ready event (subevtcode = SHCI_SUB_EVT_CODE_READY)
+ *    - reported by the FUS (sysevt_ready_rsp == RSS_FW_RUNNING)
+ * The buffer shall not be released
+ * ( eg ((tSHCI_UserEvtRxParam*)pPayload)->status shall be set to SHCI_TL_UserEventFlow_Disable )
+ * When the status is not filled, the buffer is released by default
+ */
+static void APPE_SysUserEvtRx( void * pPayload )
+{
+  UNUSED(pPayload);
+  /* Traces channel initialization */
+  APPD_EnableCPU2();
+
+  APP_BLE_Init( );
+  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP, UTIL_LPM_ENABLE);
+  return;
+}
+
+/* USER CODE BEGIN FD_LOCAL_FUNCTIONS */
 static void Led_Init( void )
 {
 #if (CFG_LED_SUPPORTED == 1)
@@ -212,39 +207,15 @@ static void Button_Init( void )
   /**
    * Button Initialization
    */
+
   BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
+  BSP_PB_Init(BUTTON_SW2, BUTTON_MODE_EXTI);
+  BSP_PB_Init(BUTTON_SW3, BUTTON_MODE_EXTI);
 #endif
 
   return;
 }
-
-
-
-static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status )
-{
-  return;
-}
-
-/**
- * The type of the payload for a system user event is tSHCI_UserEvtRxParam
- * When the system event is both :
- *    - a ready event (subevtcode = SHCI_SUB_EVT_CODE_READY)
- *    - reported by the FUS (sysevt_ready_rsp == RSS_FW_RUNNING)
- * The buffer shall not be released
- * ( eg ((tSHCI_UserEvtRxParam*)pPayload)->status shall be set to SHCI_TL_UserEventFlow_Disable )
- * When the status is not filled, the buffer is released by default
- */
-static void APPE_SysUserEvtRx( void * pPayload )
-{
-  /**< Traces channel initialization */
-  TL_TRACES_Init( );
-
-  UTIL_LPM_SetOffMode(1 << CFG_LPM_APP, UTIL_LPM_ENABLE);
-
-  APP_BLE_Init( );
-  return;
-}
-
+/* USER CODE END FD_LOCAL_FUNCTIONS */
 
 /*************************************************************
  *
@@ -260,11 +231,17 @@ void UTIL_SEQ_Idle( void )
   return;
 }
 
+
+/**
+  * @brief  This function is called by the scheduler each time an event
+  *         is pending.
+  *
+  * @param  evt_waited_bm : Event pending.
+  * @retval None
+  */
 void UTIL_SEQ_EvtIdle( UTIL_SEQ_bm_t task_id_bm, UTIL_SEQ_bm_t evt_waited_bm )
 {
   UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
-
-  return;
 }
 
 void shci_notify_asynch_evt(void* pdata)
@@ -307,22 +284,4 @@ void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin )
   return;
 }
 
-
-#if(CFG_DEBUG_TRACE != 0)
-void DbgOutputInit( void )
-{
-  HW_UART_Init(CFG_DEBUG_TRACE_UART);
-  return;
-}
-
-
-void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
-{
-  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
-
-  return;
-}
-#endif
-
-
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/hw_uart.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/hw_uart.c
index 775aa241d..f27523955 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/hw_uart.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/hw_uart.c
@@ -1,26 +1,31 @@
 /**
  ******************************************************************************
- * @file    hw_uart.c
- * @author  MCD Application Team
- * @brief   hardware access
- ******************************************************************************
- * @attention
- *
- * 
    © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
    
- *
- * This software component is licensed by ST under Ultimate Liberty license
- * SLA0044, the "License"; You may not use this file except in compliance with
- * the License. You may obtain a copy of the License at:
- *                             www.st.com/SLA0044
- *
- ******************************************************************************
- */
-
+  * File Name          : Src/hw_uart.c
+  * Description        : HW UART source file for STM32WPAN Middleware.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "app_common.h"
 #include "hw_conf.h"
+#if (CFG_HW_LPUART1_ENABLED == 1)
+extern UART_HandleTypeDef hlpuart1;
+#endif
+#if (CFG_HW_USART1_ENABLED == 1)
+extern UART_HandleTypeDef huart1;
+#endif
 
 /* Macros --------------------------------------------------------------------*/
 #define HW_UART_INIT(__HANDLE__, __USART_BASE__)                                                    \
@@ -36,7 +41,7 @@
             (__HANDLE__).AdvancedInit.AdvFeatureInit = CFG_HW_##__USART_BASE__##_ADVFEATUREINIT;    \
             HAL_UART_Init(&(__HANDLE__));                                                           \
         } while(0)
-
+          
 #define HW_UART_RX_IT(__HANDLE__, __USART_BASE__)                                                   \
         do{                                                                                         \
             HW_##__HANDLE__##RxCb = cb;                                                             \
@@ -57,82 +62,8 @@
             hal_status = HAL_UART_Transmit(&(__HANDLE__), p_data, size, timeout);                   \
         } while(0)
 
-#define HW_UART_MSP_UART_INIT(__HANDLE__, __USART_BASE__)                                           \
-        do{                                                                                         \
-                                                                                                    \
-            /* Configure Tx Pin */                                                                  \
-            CFG_HW_##__USART_BASE__##_TX_PORT_CLK_ENABLE();                                         \
-                                                                                                    \
-            GPIO_InitStruct.Pin = CFG_HW_##__USART_BASE__##_TX_PIN ;                                \
-            GPIO_InitStruct.Mode = CFG_HW_##__USART_BASE__##_TX_MODE;                               \
-            GPIO_InitStruct.Pull = CFG_HW_##__USART_BASE__##_TX_PULL;                               \
-            GPIO_InitStruct.Speed = CFG_HW_##__USART_BASE__##_TX_SPEED;                             \
-            GPIO_InitStruct.Alternate = CFG_HW_##__USART_BASE__##_TX_ALTERNATE;                     \
-            HAL_GPIO_Init(CFG_HW_##__USART_BASE__##_TX_PORT, &GPIO_InitStruct);                     \
-                                                                                                    \
-                                                                                                    \
-            /* Configure Rx Pin */                                                                  \
-            CFG_HW_##__USART_BASE__##_RX_PORT_CLK_ENABLE();                                         \
-                                                                                                    \
-            GPIO_InitStruct.Pin = CFG_HW_##__USART_BASE__##_RX_PIN;                                 \
-            GPIO_InitStruct.Mode = CFG_HW_##__USART_BASE__##_RX_MODE;                               \
-            GPIO_InitStruct.Pull = CFG_HW_##__USART_BASE__##_RX_PULL;                               \
-            GPIO_InitStruct.Speed = CFG_HW_##__USART_BASE__##_RX_SPEED;                             \
-            GPIO_InitStruct.Alternate = CFG_HW_##__USART_BASE__##_RX_ALTERNATE;                     \
-            HAL_GPIO_Init(CFG_HW_##__USART_BASE__##_RX_PORT, &GPIO_InitStruct);                     \
-                                                                                                    \
-                                                                                                    \
-            /* Configure CTS Pin */                                                                 \
-            CFG_HW_##__USART_BASE__##_CTS_PORT_CLK_ENABLE();                                        \
-                                                                                                    \
-            GPIO_InitStruct.Pin = CFG_HW_##__USART_BASE__##_CTS_PIN;                                \
-            GPIO_InitStruct.Mode = CFG_HW_##__USART_BASE__##_CTS_MODE;                              \
-            GPIO_InitStruct.Pull = CFG_HW_##__USART_BASE__##_CTS_PULL;                              \
-            GPIO_InitStruct.Speed = CFG_HW_##__USART_BASE__##_CTS_SPEED;                            \
-            GPIO_InitStruct.Alternate = CFG_HW_##__USART_BASE__##_CTS_ALTERNATE;                    \
-            HAL_GPIO_Init(CFG_HW_##__USART_BASE__##_CTS_PORT, &GPIO_InitStruct);                    \
-                                                                                                    \
-            /* Set USART source clock */                                                            \
-            __HAL_RCC_##__USART_BASE__##_CONFIG(CFG_HW_##__USART_BASE__##_SOURCE_CLOCK);            \
-                                                                                                    \
-            /* Enable USART clock */                                                                \
-            __HAL_RCC_##__USART_BASE__##_CLK_ENABLE();                                              \
-                                                                                                    \
-            HAL_NVIC_SetPriority(__USART_BASE__##_IRQn, CFG_HW_##__USART_BASE__##_PREEMPTPRIORITY, CFG_HW_##__USART_BASE__##_SUBPRIORITY); \
-            HAL_NVIC_EnableIRQ(__USART_BASE__##_IRQn);                                              \
-        } while(0)
-
-#define HW_UART_MSP_TX_DMA_INIT(__HANDLE__, __USART_BASE__)                                         \
-        do{                                                                                         \
-            /* Configure the DMA handler for Transmission process */                                \
-        /* Enable DMA clock */                                                                      \
-        CFG_HW_##__USART_BASE__##_DMA_CLK_ENABLE();                                                 \
-        /* Enable DMA MUX clock */                                                                  \
-        CFG_HW_##__USART_BASE__##_DMAMUX_CLK_ENABLE();                                              \
-                                                                                                    \
-        HW_hdma_##__HANDLE__##_tx.Instance                 = CFG_HW_##__USART_BASE__##_TX_DMA_CHANNEL; \
-        HW_hdma_##__HANDLE__##_tx.Init.Request             = CFG_HW_##__USART_BASE__##_TX_DMA_REQ;  \
-        HW_hdma_##__HANDLE__##_tx.Init.Direction           = DMA_MEMORY_TO_PERIPH;                  \
-        HW_hdma_##__HANDLE__##_tx.Init.PeriphInc           = DMA_PINC_DISABLE;                      \
-        HW_hdma_##__HANDLE__##_tx.Init.MemInc              = DMA_MINC_ENABLE;                       \
-        HW_hdma_##__HANDLE__##_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;                   \
-        HW_hdma_##__HANDLE__##_tx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;                   \
-        HW_hdma_##__HANDLE__##_tx.Init.Mode                = DMA_NORMAL;                            \
-        HW_hdma_##__HANDLE__##_tx.Init.Priority            = DMA_PRIORITY_LOW;                      \
-                                                                                                    \
-        HAL_DMA_Init(&HW_hdma_##__HANDLE__##_tx);                                                   \
-                                                                                                    \
-        /* Associate the initialized DMA handle to the UART handle */                               \
-        __HAL_LINKDMA(huart, hdmatx, HW_hdma_##__HANDLE__##_tx);                                    \
-                                                                                                    \
-        /* NVIC configuration for DMA transfer complete interrupt  */                               \
-        HAL_NVIC_SetPriority(CFG_HW_##__USART_BASE__##_TX_DMA_IRQn, CFG_HW_##__USART_BASE__##_DMA_TX_PREEMPTPRIORITY, CFG_HW_##__USART_BASE__##_DMA_TX_SUBPRIORITY); \
-        HAL_NVIC_EnableIRQ(CFG_HW_##__USART_BASE__##_TX_DMA_IRQn);                                  \
-    } while(0)
-
-/* Variables ------------------------------------------------------------------*/
+/* Variables -----------------------------------------------------------------*/
 #if (CFG_HW_USART1_ENABLED == 1)
-        UART_HandleTypeDef huart1 = {0};
 #if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
     DMA_HandleTypeDef HW_hdma_huart1_tx ={0};
 #endif
@@ -141,12 +72,11 @@
 #endif
 
 #if (CFG_HW_LPUART1_ENABLED == 1)
-    UART_HandleTypeDef lpuart1 = {0};
 #if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
-    DMA_HandleTypeDef HW_hdma_lpuart1_tx ={0};
+    DMA_HandleTypeDef HW_hdma_hlpuart1_tx ={0};
 #endif
-    void (*HW_lpuart1RxCb)(void);
-    void (*HW_lpuart1TxCb)(void);
+    void (*HW_hlpuart1RxCb)(void);
+    void (*HW_hlpuart1TxCb)(void);
 #endif
 
     void HW_UART_Init(hw_uart_id_t hw_uart_id)
@@ -171,301 +101,255 @@
 
         return;
     }
-
-    void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+    
+void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+{
+    switch (hw_uart_id)
     {
-        switch (hw_uart_id)
-        {
 #if (CFG_HW_USART1_ENABLED == 1)
-            case hw_uart1:
-                HW_UART_RX_IT(huart1, USART1);
-                break;
+        case hw_uart1:
+            HW_UART_RX_IT(huart1, USART1);
+            break;
 #endif
 
 #if (CFG_HW_LPUART1_ENABLED == 1)
-            case hw_lpuart1:
-                HW_UART_RX_IT(lpuart1, LPUART1);
-                break;
+        case hw_lpuart1:
+            HW_UART_RX_IT(hlpuart1, LPUART1);
+            break;
 #endif
 
-            default:
-                break;
-        }
-
-        return;
+        default:
+            break;
     }
 
-    void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  void (*cb)(void))
+    return;
+}
+
+void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  void (*cb)(void))
+{
+    switch (hw_uart_id)
     {
-        switch (hw_uart_id)
-        {
 #if (CFG_HW_USART1_ENABLED == 1)
-            case hw_uart1:
-                HW_UART_TX_IT(huart1, USART1);
-                break;
+        case hw_uart1:
+            HW_UART_TX_IT(huart1, USART1);
+            break;
 #endif
 
 #if (CFG_HW_LPUART1_ENABLED == 1)
-            case hw_lpuart1:
-                HW_UART_TX_IT(lpuart1, LPUART1);
-                break;
+        case hw_lpuart1:
+            HW_UART_TX_IT(hlpuart1, LPUART1);
+            break;
 #endif
 
-            default:
-                break;
-        }
-
-        return;
+        default:
+            break;
     }
 
-    hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout)
-    {
-        HAL_StatusTypeDef hal_status = HAL_OK;
-        hw_status_t hw_status = hw_uart_ok;
+    return;
+}
 
-        switch (hw_uart_id)
-        {
+hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,  uint32_t timeout)
+{
+    HAL_StatusTypeDef hal_status = HAL_OK;
+    hw_status_t hw_status = hw_uart_ok;
+
+    switch (hw_uart_id)
+    {
 #if (CFG_HW_USART1_ENABLED == 1)
-            case hw_uart1:
-                HW_UART_TX(huart1, USART1);
-                break;
+        case hw_uart1:
+            HW_UART_TX(huart1, USART1);
+            break;
 #endif
 
 #if (CFG_HW_LPUART1_ENABLED == 1)
-            case hw_lpuart1:
-                HW_UART_TX(lpuart1, LPUART1);
-                break;
+        case hw_lpuart1:
+            HW_UART_TX(hlpuart1, LPUART1);
+            break;
 #endif
 
-            default:
-                break;
-        }
-
-        switch (hal_status)
-        {
-            case HAL_OK:
-                hw_status = hw_uart_ok;
-                break;
+        default:
+            break;
+    }
 
-            case HAL_ERROR:
-                hw_status = hw_uart_error;
-                break;
+    switch (hal_status)
+    {
+        case HAL_OK:
+            hw_status = hw_uart_ok;
+            break;
 
-            case HAL_BUSY:
-                hw_status = hw_uart_busy;
-                break;
+        case HAL_ERROR:
+            hw_status = hw_uart_error;
+            break;
 
-            case HAL_TIMEOUT:
-                hw_status = hw_uart_to;
-                break;
+        case HAL_BUSY:
+            hw_status = hw_uart_busy;
+            break;
 
-            default:
-                break;
-        }
+        case HAL_TIMEOUT:
+            hw_status = hw_uart_to;
+            break;
 
-        return hw_status;
+        default:
+            break;
     }
 
-    hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
-    {
-        HAL_StatusTypeDef hal_status = HAL_OK;
-        hw_status_t hw_status = hw_uart_ok;
+    return hw_status;
+}
 
-        switch (hw_uart_id)
-        {
-#if (CFG_HW_USART1_ENABLED == 1)
-            case hw_uart1:
-                HW_huart1TxCb = cb;
-                huart1.Instance = USART1;
-                hal_status = HAL_UART_Transmit_DMA(&huart1, p_data, size);
-                break;
-#endif
+hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
+{
+    HAL_StatusTypeDef hal_status = HAL_OK;
+    hw_status_t hw_status = hw_uart_ok;
 
-#if (CFG_HW_USART2_ENABLED == 1)
-            case hw_uart2:
-                HW_huart2TxCb = cb;
-                huart2.Instance = USART2;
-                hal_status = HAL_UART_Transmit_DMA(&huart2, p_data, size);
-                break;
+    switch (hw_uart_id)
+    {
+#if (CFG_HW_USART1_ENABLED == 1)
+        case hw_uart1:
+            HW_huart1TxCb = cb;
+            huart1.Instance = USART1;
+            hal_status = HAL_UART_Transmit_DMA(&huart1, p_data, size);
+            break;
 #endif
 
 #if (CFG_HW_LPUART1_ENABLED == 1)
-            case hw_lpuart1:
-                HW_lpuart1TxCb = cb;
-                lpuart1.Instance = LPUART1;
-                hal_status = HAL_UART_Transmit_DMA(&lpuart1, p_data, size);
-                break;
+        case hw_lpuart1:
+            HW_hlpuart1TxCb = cb;
+            hlpuart1.Instance = LPUART1;
+            hal_status = HAL_UART_Transmit_DMA(&hlpuart1, p_data, size);
+            break;
 #endif
 
-            default:
-                break;
-        }
-
-        switch (hal_status)
-        {
-            case HAL_OK:
-                hw_status = hw_uart_ok;
-                break;
+        default:
+            break;
+    }
 
-            case HAL_ERROR:
-                hw_status = hw_uart_error;
-                break;
+    switch (hal_status)
+    {
+        case HAL_OK:
+            hw_status = hw_uart_ok;
+            break;
 
-            case HAL_BUSY:
-                hw_status = hw_uart_busy;
-                break;
+        case HAL_ERROR:
+            hw_status = hw_uart_error;
+            break;
 
-            case HAL_TIMEOUT:
-                hw_status = hw_uart_to;
-                break;
+        case HAL_BUSY:
+            hw_status = hw_uart_busy;
+            break;
 
-            default:
-                break;
-        }
+        case HAL_TIMEOUT:
+            hw_status = hw_uart_to;
+            break;
 
-        return hw_status;
+        default:
+            break;
     }
 
-    void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+    return hw_status;
+}
+
+void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+{
+    switch (hw_uart_id)
     {
-        switch (hw_uart_id)
-        {
 #if (CFG_HW_USART1_ENABLED == 1)
-            case hw_uart1:
-                HAL_UART_IRQHandler(&huart1);
-                break;
+        case hw_uart1:
+            HAL_UART_IRQHandler(&huart1);
+            break;
 #endif
 
 #if (CFG_HW_LPUART1_ENABLED == 1)
-            case hw_lpuart1:
-                HAL_UART_IRQHandler(&lpuart1);
-                break;
+        case hw_lpuart1:
+            HAL_UART_IRQHandler(&hlpuart1);
+            break;
 #endif
 
-            default:
-                break;
-        }
-
-        return;
+        default:
+            break;
     }
 
-    void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id)
-    {
-        switch (hw_uart_id)
-        {
-#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
-            case hw_uart1:
-                HAL_DMA_IRQHandler(huart1.hdmatx);
-                break;
-#endif
-
-#if (CFG_HW_USART2_DMA_TX_SUPPORTED == 1)
-            case hw_uart2:
-                HAL_DMA_IRQHandler(huart2.hdmatx);
-                break;
-#endif
-
-#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
-            case hw_lpuart1:
-                HAL_DMA_IRQHandler(lpuart1.hdmatx);
-                break;
-#endif
-
-            default:
-                break;
-        }
+    return;
+}
 
-        return;
-    }
-
-    void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id)
+{
+    switch (hw_uart_id)
     {
-#if ( (CFG_HW_USART1_ENABLED == 1) || (CFG_HW_LPUART1_ENABLED == 1) )
-        GPIO_InitTypeDef  GPIO_InitStruct = {0};
-#endif
-        switch ((uint32_t)huart->Instance)
-        {
-#if (CFG_HW_USART1_ENABLED == 1)
-            case (uint32_t)USART1:
-      HW_UART_MSP_UART_INIT( huart1, USART1 );
 #if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
-            HW_UART_MSP_TX_DMA_INIT( huart1, USART1 );
-#endif
+        case hw_uart1:
+            HAL_DMA_IRQHandler(huart1.hdmatx);
             break;
 #endif
 
-#if (CFG_HW_LPUART1_ENABLED == 1)
-            case (uint32_t)LPUART1:
-      HW_UART_MSP_UART_INIT( lpuart1, LPUART1 );
 #if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
-            HW_UART_MSP_TX_DMA_INIT( lpuart1, LPUART1 );
-#endif
+        case hw_lpuart1:
+            HAL_DMA_IRQHandler(hlpuart1.hdmatx);
             break;
 #endif
 
-            default:
-                break;
-        }
-
-        return;
+        default:
+            break;
     }
 
-    void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+    return;
+}
+
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+    switch ((uint32_t)huart->Instance)
     {
-        switch ((uint32_t)huart->Instance)
-        {
 #if (CFG_HW_USART1_ENABLED == 1)
-            case (uint32_t)USART1:
-                    if(HW_huart1RxCb)
-                    {
-                        HW_huart1RxCb();
-                    }
+        case (uint32_t)USART1:
+            if(HW_huart1RxCb)
+            {
+                HW_huart1RxCb();
+            }
             break;
 #endif
 
 #if (CFG_HW_LPUART1_ENABLED == 1)
-            case (uint32_t)LPUART1:
-                    if(HW_lpuart1RxCb)
-                    {
-                        HW_lpuart1RxCb();
-                    }
+        case (uint32_t)LPUART1:
+            if(HW_hlpuart1RxCb)
+            {
+                HW_hlpuart1RxCb();
+            }
             break;
 #endif
 
-            default:
-                break;
-        }
-
-        return;
+        default:
+            break;
     }
 
-    void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+    return;
+}
+
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+    switch ((uint32_t)huart->Instance)
     {
-        switch ((uint32_t)huart->Instance)
-        {
 #if (CFG_HW_USART1_ENABLED == 1)
-            case (uint32_t)USART1:
-                    if(HW_huart1TxCb)
-                    {
-                        HW_huart1TxCb();
-                    }
+        case (uint32_t)USART1:
+            if(HW_huart1TxCb)
+            {
+                HW_huart1TxCb();
+            }
             break;
 #endif
 
 #if (CFG_HW_LPUART1_ENABLED == 1)
-            case (uint32_t)LPUART1:
-                    if(HW_lpuart1TxCb)
-                    {
-                        HW_lpuart1TxCb();
-                    }
+        case (uint32_t)LPUART1:
+            if(HW_hlpuart1TxCb)
+            {
+                HW_hlpuart1TxCb();
+            }
             break;
 #endif
 
-            default:
-                break;
-        }
-
-        return;
+        default:
+            break;
     }
 
-    /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+    return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/main.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/main.c
index 53f38a463..0022c15aa 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/main.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/main.c
@@ -35,166 +35,331 @@
  *
  ******************************************************************************
  */
-
+/* USER CODE END Header */
 
 /* Includes ------------------------------------------------------------------*/
-#include "app_common.h"
-
+#include "main.h"
 #include "app_entry.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "app_common.h"
 #include "stm32_lpm.h"
 #include "stm32_seq.h"
 #include "dbg_trace.h"
+#include "hw_conf.h"
+#include "otp.h"
+/* USER CODE END Includes */
 
 /* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Global variables ---------------------------------------------------------*/
-RTC_HandleTypeDef hrtc = { 0 }; /**< RTC handler declaration */
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
 
 /* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef hlpuart1;
+UART_HandleTypeDef huart1;
+DMA_HandleTypeDef hdma_lpuart1_tx;
+DMA_HandleTypeDef hdma_usart1_tx;
+
+RTC_HandleTypeDef hrtc;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
 /* Private function prototypes -----------------------------------------------*/
-static void Reset_BackupDomain( void );
-static void Init_RTC( void );
-static void SystemClock_Config( void );
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+void MX_LPUART1_UART_Init(void);
+void MX_USART1_UART_Init(void);
+static void MX_RF_Init(void);
+static void MX_RTC_Init(void);
+/* USER CODE BEGIN PFP */
+void PeriphClock_Config(void);
 static void Reset_Device( void );
 static void Reset_IPCC( void );
+static void Reset_BackupDomain( void );
 static void Init_Exti( void );
+static void Config_HSE(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
 
-/* Functions Definition ------------------------------------------------------*/
+/* USER CODE END 0 */
 
 /**
- * @brief  Main program
- * @param  None
- * @retval None
- */
-int main( void )
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
 {
-  HAL_Init();
+  /* USER CODE BEGIN 1 */
 
-  Reset_Device();
+  /* USER CODE END 1 */
 
-  /**
-   * When the application is expected to run at higher speed, it should be better to set the correct system clock
-   * in system_stm32yyxx.c so that the initialization phase is running at max speed.
-   */
-  SystemClock_Config(); /**< Configure the system clock */
+  /* MCU Configuration--------------------------------------------------------*/
 
-  Init_Exti( );
-
-  Init_RTC();
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
 
-  APPE_Init( );
+  /* USER CODE BEGIN Init */
+  Reset_Device();
+  Config_HSE();
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  PeriphClock_Config();
+  Init_Exti(); /**< Configure the system Power Mode */
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_RF_Init();
+  MX_RTC_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+  APPE_Init();
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+	while(1)
+	{
+		UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
 
-  while(1)
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure LSE Drive Capability 
+  */
+  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE
+                              |RCC_OSCILLATORTYPE_LSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
   {
-    UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RFWAKEUP
+                              |RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1
+                              |RCC_PERIPHCLK_LPUART1;
+  PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+  //PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32;
+  PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
   }
 }
 
-/*************************************************************
- *
- * LOCAL FUNCTIONS
- *
- *************************************************************/
-static void Init_Exti( void )
+/**
+  * @brief LPUART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+void MX_LPUART1_UART_Init(void)
 {
-  /**< Disable all wakeup interrupt on CPU1  except IPCC(36), HSEM(38) */
-  LL_EXTI_DisableIT_0_31(~0);
-  LL_EXTI_DisableIT_32_63( (~0) & (~(LL_EXTI_LINE_36 | LL_EXTI_LINE_38)) );
 
-  return;
+  /* USER CODE BEGIN LPUART1_Init 0 */
+
+  /* USER CODE END LPUART1_Init 0 */
+
+  /* USER CODE BEGIN LPUART1_Init 1 */
+
+  /* USER CODE END LPUART1_Init 1 */
+  hlpuart1.Instance = LPUART1;
+  hlpuart1.Init.BaudRate = 115200;
+  hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
+  hlpuart1.Init.StopBits = UART_STOPBITS_1;
+  hlpuart1.Init.Parity = UART_PARITY_NONE;
+  hlpuart1.Init.Mode = UART_MODE_TX_RX;
+  hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  hlpuart1.FifoMode = UART_FIFOMODE_DISABLE;
+  if (HAL_UART_Init(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN LPUART1_Init 2 */
+
+  /* USER CODE END LPUART1_Init 2 */
+
 }
 
-static void Reset_Device( void )
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+void MX_USART1_UART_Init(void)
 {
-#if ( CFG_HW_RESET_BY_FW == 1 )
-  Reset_BackupDomain();
 
-  Reset_IPCC();
-#endif
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_8;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
 
-  return;
 }
 
-static void Reset_IPCC( void )
+/**
+  * @brief RF Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RF_Init(void)
 {
-  LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
-
-  LL_C1_IPCC_ClearFlag_CHx(
-      IPCC,
-      LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
-      | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
-
-  LL_C2_IPCC_ClearFlag_CHx(
-      IPCC,
-      LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
-      | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
-
-  LL_C1_IPCC_DisableTransmitChannel(
-      IPCC,
-      LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
-      | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
-
-  LL_C2_IPCC_DisableTransmitChannel(
-      IPCC,
-      LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
-      | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
-
-  LL_C1_IPCC_DisableReceiveChannel(
-      IPCC,
-      LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
-      | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
-
-  LL_C2_IPCC_DisableReceiveChannel(
-      IPCC,
-      LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
-      | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
 
-  return;
-}
+  /* USER CODE BEGIN RF_Init 0 */
 
-static void Reset_BackupDomain( void )
-{
-  if ((LL_RCC_IsActiveFlag_PINRST() != FALSE) && (LL_RCC_IsActiveFlag_SFTRST() == FALSE))
-  {
-    HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+  /* USER CODE END RF_Init 0 */
 
-    /**
-     *  Write twice the value to flush the APB-AHB bridge
-     *  This bit shall be written in the register before writing the next one
-     */
-    HAL_PWR_EnableBkUpAccess();
+  /* USER CODE BEGIN RF_Init 1 */
 
-    __HAL_RCC_BACKUPRESET_FORCE();
-    __HAL_RCC_BACKUPRESET_RELEASE();
-  }
+  /* USER CODE END RF_Init 1 */
+  /* USER CODE BEGIN RF_Init 2 */
+
+  /* USER CODE END RF_Init 2 */
 
-  return;
 }
 
-static void Init_RTC( void )
+/**
+  * @brief RTC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RTC_Init(void)
 {
-  HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
 
-  /**
-   *  Write twice the value to flush the APB-AHB bridge
-   *  This bit shall be written in the register before writing the next one
-   */
-  HAL_PWR_EnableBkUpAccess();
+  /* USER CODE BEGIN RTC_Init 0 */
 
-  __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_HSE_DIV32); /**< Select HSE as RTC Input */
+  /* USER CODE END RTC_Init 0 */
 
-  __HAL_RCC_RTC_ENABLE(); /**< Enable RTC */
+  /* USER CODE BEGIN RTC_Init 1 */
 
-  hrtc.Instance = RTC; /**< Define instance */
-
-  /**
-   * Set the Asynchronous prescaler
-   */
+  /* USER CODE END RTC_Init 1 */
+  /** Initialize RTC Only 
+  */
+  hrtc.Instance = RTC;
+  hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
   hrtc.Init.AsynchPrediv = CFG_RTC_ASYNCH_PRESCALER;
   hrtc.Init.SynchPrediv = CFG_RTC_SYNCH_PRESCALER;
-  HAL_RTC_Init(&hrtc);
-
+  hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
+  hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+  hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+  if (HAL_RTC_Init(&hrtc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN RTC_Init 2 */
   /* Disable RTC registers write protection */
   LL_RTC_DisableWriteProtection(RTC);
 
@@ -202,29 +367,53 @@ static void Init_RTC( void )
 
   /* Enable RTC registers write protection */
   LL_RTC_EnableWriteProtection(RTC);
+  /* USER CODE END RTC_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+  /* DMA controller clock enable */
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
+  __HAL_RCC_DMA2_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
+  /* DMA2_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA2_Channel4_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(DMA2_Channel4_IRQn);
 
-  return;
 }
 
 /**
- * @brief  Configure the system clock
- *
- * @note   This API configures
- *         - The system clock source
- *           - The AHBCLK, APBCLK dividers
- *           - The flash latency
- *           - The PLL settings (when required)
- *
- * @param  None
- * @retval None
- */
-void SystemClock_Config( void )
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
 {
-#if (CFG_USB_INTERFACE_ENABLE != 0)
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
-  RCC_CRSInitTypeDef RCC_CRSInitStruct = { 0 };
 
-  /**
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+void PeriphClock_Config(void)
+{
+  #if (CFG_USB_INTERFACE_ENABLE != 0)
+	RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
+	RCC_CRSInitTypeDef RCC_CRSInitStruct = { 0 };
+
+	/**
    * This prevents the CPU2 to disable the HSI48 oscillator when
    * it does not use anymore the RNG IP
    */
@@ -232,53 +421,134 @@ void SystemClock_Config( void )
 
   LL_RCC_HSI48_Enable();
 
-  while(!LL_RCC_HSI48_IsReady());
+	while(!LL_RCC_HSI48_IsReady());
 
-  /* Select HSI48 as USB clock source */
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+	/* Select HSI48 as USB clock source */
+	PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+	PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+	HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 
-  /*Configure the clock recovery system (CRS)**********************************/
+	/*Configure the clock recovery system (CRS)**********************************/
 
-  /* Enable CRS Clock */
-  __HAL_RCC_CRS_CLK_ENABLE();
+	/* Enable CRS Clock */
+	__HAL_RCC_CRS_CLK_ENABLE();
 
-  /* Default Synchro Signal division factor (not divided) */
-  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+	/* Default Synchro Signal division factor (not divided) */
+	RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
 
-  /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
-  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+	/* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+	RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
 
-  /* HSI48 is synchronized with USB SOF at 1KHz rate */
-  RCC_CRSInitStruct.ReloadValue = RCC_CRS_RELOADVALUE_DEFAULT;
-  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+	/* HSI48 is synchronized with USB SOF at 1KHz rate */
+	RCC_CRSInitStruct.ReloadValue = RCC_CRS_RELOADVALUE_DEFAULT;
+	RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
 
-  RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+	RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
 
-  /* Set the TRIM[5:0] to the default value*/
-  RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+	/* Set the TRIM[5:0] to the default value*/
+	RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
 
-  /* Start automatic synchronization */
-  HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+	/* Start automatic synchronization */
+	HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
 #endif
 
-        /**
-         *  Write twice the value to flush the APB-AHB bridge to ensure the  bit is written
-         */
-        HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
-        HAL_PWR_EnableBkUpAccess();
+	return;
+}
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
 
-  /**
-   * Select LSE clock
-   */
-  LL_RCC_LSE_Enable();
-  while(!LL_RCC_LSE_IsReady());
+static void Config_HSE(void)
+{
+    OTP_ID0_t * p_otp;
 
   /**
-   * Select wakeup source of BLE RF
+   * Read HSE_Tuning from OTP
    */
-  LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_LSE);
+  p_otp = (OTP_ID0_t *) OTP_Read(0);
+  if (p_otp)
+  {
+    LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
+  }
+
+  return;
+}  
+
+
+static void Reset_Device( void )
+{
+#if ( CFG_HW_RESET_BY_FW == 1 )
+	Reset_BackupDomain();
+
+	Reset_IPCC();
+#endif
+
+	return;
+}
+
+static void Reset_IPCC( void )
+{
+	LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
+
+	LL_C1_IPCC_ClearFlag_CHx(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_ClearFlag_CHx(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C1_IPCC_DisableTransmitChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_DisableTransmitChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C1_IPCC_DisableReceiveChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	LL_C2_IPCC_DisableReceiveChannel(
+			IPCC,
+			LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+			| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+	return;
+}
+
+static void Reset_BackupDomain( void )
+{
+	if ((LL_RCC_IsActiveFlag_PINRST() != FALSE) && (LL_RCC_IsActiveFlag_SFTRST() == FALSE))
+	{
+		HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+		/**
+		 *  Write twice the value to flush the APB-AHB bridge
+		 *  This bit shall be written in the register before writing the next one
+		 */
+		HAL_PWR_EnableBkUpAccess();
+
+		__HAL_RCC_BACKUPRESET_FORCE();
+		__HAL_RCC_BACKUPRESET_RELEASE();
+	}
+
+	return;
+}
+
+static void Init_Exti( void )
+{
+  /**< Disable all wakeup interrupt on CPU1  except IPCC(36), HSEM(38) */
+  LL_EXTI_DisableIT_0_31(~0);
+  LL_EXTI_DisableIT_32_63( (~0) & (~(LL_EXTI_LINE_36 | LL_EXTI_LINE_38)) );
 
   return;
 }
@@ -316,5 +586,35 @@ void HAL_Delay(uint32_t Delay)
     __WFI( );
   }
 }
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
 
-/******************* (C) COPYRIGHT 2019 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/stm32_lpm_if.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/stm32_lpm_if.c
index f024b61e3..1418e0a36 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/stm32_lpm_if.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/stm32_lpm_if.c
@@ -70,6 +70,13 @@ static void Switch_On_HSI( void );
 void PWR_EnterOffMode( void )
 {
 /* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
   /************************************************************************************
    * ENTER OFF MODE
    ***********************************************************************************/
@@ -106,6 +113,8 @@ void PWR_ExitOffMode( void )
 {
 /* USER CODE BEGIN PWR_ExitOffMode */
 
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitOffMode */
 }
 
@@ -118,6 +127,16 @@ void PWR_ExitOffMode( void )
 void PWR_EnterStopMode( void )
 {
 /* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
   /**
    * This function is called from CRITICAL SECTION
    */
@@ -202,6 +221,9 @@ void PWR_ExitStopMode( void )
 
   /* Release RCC semaphore */
   LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitStopMode */
 }
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/stm32wbxx_hal_msp.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/stm32wbxx_hal_msp.c
new file mode 100644
index 000000000..91fb787ab
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/stm32wbxx_hal_msp.c
@@ -0,0 +1,348 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32wbxx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * This notice applies to any and all portions of this file
+  * that are not between comment pairs USER CODE BEGIN and
+  * USER CODE END. Other portions of this file, whether 
+  * inserted by the user or by software development tools
+  * are owned by their respective copyright owners.
+  *
+  * Copyright (c) 2019 STMicroelectronics International N.V. 
+  * All rights reserved.
+  *
+  * Redistribution and use in source and binary forms, with or without 
+  * modification, are permitted, provided that the following conditions are met:
+  *
+  * 1. Redistribution of source code must retain the above copyright notice, 
+  *    this list of conditions and the following disclaimer.
+  * 2. Redistributions in binary form must reproduce the above copyright notice,
+  *    this list of conditions and the following disclaimer in the documentation
+  *    and/or other materials provided with the distribution.
+  * 3. Neither the name of STMicroelectronics nor the names of other 
+  *    contributors to this software may be used to endorse or promote products 
+  *    derived from this software without specific written permission.
+  * 4. This software, including modifications and/or derivative works of this 
+  *    software, must execute solely and exclusively on microcontroller or
+  *    microprocessor devices manufactured by or for STMicroelectronics.
+  * 5. Redistribution and use of this software other than as permitted under 
+  *    this license is void and will automatically terminate your rights under 
+  *    this license. 
+  *
+  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" 
+  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT 
+  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 
+  * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
+  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT 
+  * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 
+  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 
+  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 
+  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_lpuart1_tx;
+
+extern DMA_HandleTypeDef hdma_usart1_tx;
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_HSEM_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(huart->Instance==LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspInit 0 */
+
+  /* USER CODE END LPUART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_LPUART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**LPUART1 GPIO Configuration    
+    PA2     ------> LPUART1_TX
+    PA3     ------> LPUART1_RX
+    PA6     ------> LPUART1_CTS 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* LPUART1 DMA Init */
+    /* LPUART1_TX Init */
+    hdma_lpuart1_tx.Instance = DMA1_Channel4;
+    hdma_lpuart1_tx.Init.Request = DMA_REQUEST_LPUART1_TX;
+    hdma_lpuart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_lpuart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_lpuart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_lpuart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_lpuart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_lpuart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_lpuart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_lpuart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmatx,hdma_lpuart1_tx);
+
+    /* LPUART1 interrupt Init */
+    HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(LPUART1_IRQn);
+  /* USER CODE BEGIN LPUART1_MspInit 1 */
+
+  /* USER CODE END LPUART1_MspInit 1 */
+  }
+  else if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspInit 0 */
+
+  /* USER CODE END USART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**USART1 GPIO Configuration    
+    PA11     ------> USART1_CTS
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_11;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* USART1 DMA Init */
+    /* USART1_TX Init */
+    hdma_usart1_tx.Instance = DMA2_Channel4;
+    hdma_usart1_tx.Init.Request = DMA_REQUEST_USART1_TX;
+    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_usart1_tx.Init.Mode = DMA_NORMAL;
+    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx);
+
+    /* USART1 interrupt Init */
+    HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspInit 1 */
+
+  /* USER CODE END USART1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspDeInit 0 */
+
+  /* USER CODE END LPUART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_LPUART1_CLK_DISABLE();
+  
+    /**LPUART1 GPIO Configuration    
+    PA2     ------> LPUART1_TX
+    PA3     ------> LPUART1_RX
+    PA6     ------> LPUART1_CTS 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_6);
+
+    /* LPUART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmatx);
+
+    /* LPUART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(LPUART1_IRQn);
+  /* USER CODE BEGIN LPUART1_MspDeInit 1 */
+
+  /* USER CODE END LPUART1_MspDeInit 1 */
+  }
+  else if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+  /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+  
+    /**USART1 GPIO Configuration    
+    PA11     ------> USART1_CTS
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11);
+
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
+
+    /* USART1 DMA DeInit */
+    HAL_DMA_DeInit(huart->hdmatx);
+
+    /* USART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+  /* USER CODE END USART1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspInit 0 */
+  HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+  /**
+  *  Write twice the value to flush the APB-AHB bridge
+  *  This bit shall be written in the register before writing the next one
+  */
+  HAL_PWR_EnableBkUpAccess();
+
+  __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_HSE_DIV32);
+  /* USER CODE END RTC_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_RTC_ENABLE();
+  /* USER CODE BEGIN RTC_MspInit 1 */
+  HAL_RTCEx_EnableBypassShadow(hrtc);
+  /* USER CODE END RTC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspDeInit 0 */
+
+  /* USER CODE END RTC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RTC_DISABLE();
+  /* USER CODE BEGIN RTC_MspDeInit 1 */
+
+  /* USER CODE END RTC_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/stm32wbxx_it.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/stm32wbxx_it.c
index 92d934b6f..b37e5a9ab 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/stm32wbxx_it.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/stm32wbxx_it.c
@@ -23,84 +23,254 @@
 /* Includes ------------------------------------------------------------------*/
 #include "app_common.h"
 #include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
 
 /* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
 /* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
 /* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
 /* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
 /* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+ 
+    
+      
+extern DMA_HandleTypeDef hdma_lpuart1_tx;
+  
+      
+extern DMA_HandleTypeDef hdma_usart1_tx;
+  
+      
+extern UART_HandleTypeDef hlpuart1;
+  
+      
+extern UART_HandleTypeDef huart1;
+  
+      
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
 
 /******************************************************************************/
-/*            Cortex-M4 Processor Exceptions Handlers                         */
+/*           Cortex Processor Interruption and Exception Handlers          */ 
 /******************************************************************************/
-
 /**
- * @brief  This function handles NMI exception.
- * @param  None
- * @retval None
- */
+  * @brief This function handles Non maskable interrupt.
+  */
 void NMI_Handler(void)
 {
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
 }
 
 /**
- * @brief  This function handles Hard Fault exception.
- * @param  None
- * @retval None
- */
+  * @brief This function handles Hard fault interrupt.
+  */
 void HardFault_Handler(void)
 {
-  /* Go to infinite loop when Hard Fault exception occurs */
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
   while (1)
   {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
   }
 }
 
 /**
- * @brief  This function handles SVCall exception.
- * @param  None
- * @retval None
- */
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
 void SVC_Handler(void)
 {
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
 }
 
 /**
- * @brief  This function handles Debug Monitor exception.
- * @param  None
- * @retval None
- */
+  * @brief This function handles Debug monitor.
+  */
 void DebugMon_Handler(void)
 {
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
 }
 
 /**
- * @brief  This function handles PendSVC exception.
- * @param  None
- * @retval None
- */
+  * @brief This function handles Pendable request for system service.
+  */
 void PendSV_Handler(void)
 {
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
 }
 
 /**
- * @brief  This function handles SysTick Handler.
- * @param  None
- * @retval None
- */
+  * @brief This function handles System tick timer.
+  */
 void SysTick_Handler(void)
 {
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
   HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32wbxx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles DMA1 channel4 global interrupt.
+  */
+void DMA1_Channel4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_lpuart1_tx);
+  /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel4_IRQn 1 */
 }
 
-/********************************************************************************/
-/*                 STM32WBxx Peripherals Interrupt Handlers                     */
-/*  Add here the Interrupt Handler for the used peripheral(s), for the          */
-/*  available peripheral interrupt handler's name please refer to the startup   */
-/*  file (startup_stm32wb55xx_cm4.s).                                           */
-/********************************************************************************/
+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+
+  /* USER CODE END USART1_IRQn 0 */
+  HAL_UART_IRQHandler(&huart1);
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
 
+/**
+  * @brief This function handles LPUART1 global interrupt.
+  */
+void LPUART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN LPUART1_IRQn 0 */
+
+  /* USER CODE END LPUART1_IRQn 0 */
+  HAL_UART_IRQHandler(&hlpuart1);
+  /* USER CODE BEGIN LPUART1_IRQn 1 */
+
+  /* USER CODE END LPUART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA2 channel4 global interrupt.
+  */
+void DMA2_Channel4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2_Channel4_IRQn 0 */
+
+  /* USER CODE END DMA2_Channel4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart1_tx);
+  /* USER CODE BEGIN DMA2_Channel4_IRQn 1 */
+
+  /* USER CODE END DMA2_Channel4_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
 /**
  * @brief  This function handles External line
  *         interrupt request.
@@ -120,6 +290,7 @@ void PUSH_BUTTON_SW1_EXTI_IRQHandler(void)
  */
 void PUSH_BUTTON_SW2_EXTI_IRQHandler(void)
 {
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW2_PIN);
 }
 
 /**
@@ -130,35 +301,9 @@ void PUSH_BUTTON_SW2_EXTI_IRQHandler(void)
  */
 void PUSH_BUTTON_SW3_EXTI_IRQHandler(void)
 {
+  HAL_GPIO_EXTI_IRQHandler(BUTTON_SW3_PIN);
 }
 
-#if(CFG_HW_USART1_ENABLED == 1)
-void USART1_IRQHandler(void)
-{
-  HW_UART_Interrupt_Handler(hw_uart1);
-}
-#endif
-
-#if(CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
-void CFG_HW_USART1_DMA_TX_IRQHandler( void )
-{
-  HW_UART_DMA_Interrupt_Handler(hw_uart1);
-}
-#endif
-
-#if(CFG_HW_LPUART1_ENABLED == 1)
-void LPUART1_IRQHandler(void)
-{
-  HW_UART_Interrupt_Handler(hw_lpuart1);
-}
-#endif
-
-#if(CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
-void CFG_HW_LPUART1_DMA_TX_IRQHandler( void )
-{
-  HW_UART_DMA_Interrupt_Handler(hw_lpuart1);
-}
-#endif
 
 void RTC_WKUP_IRQHandler(void)
 {
@@ -177,7 +322,5 @@ void IPCC_C1_RX_IRQHandler(void)
   HW_IPCC_Rx_Handler();
   return;
 }
-
-
-
+/* USER CODE END 1 */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/system_stm32wbxx.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/system_stm32wbxx.c
index e3025c7f9..b0a058b8a 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/system_stm32wbxx.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Src/system_stm32wbxx.c
@@ -122,6 +122,14 @@
  * @{
  */
 
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
 /**
  * @}
  */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/EWARM/BLE_DataThroughput.ewp b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/EWARM/BLE_DataThroughput.ewp
index d3661660e..1adb22fe2 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/EWARM/BLE_DataThroughput.ewp
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/EWARM/BLE_DataThroughput.ewp
@@ -49,20 +49,20 @@
                 
                 
                 
                 
                 
                 
                 
                 
                 
                 
                 
                 
                 
                 
                 
                 
                     
+            
+              stm32wbxx_hal_msp.c
+              1
+              ../Core/Src/stm32wbxx_hal_msp.c
+            
+            
+              app_debug.c
+              1
+              ../Core/Src/app_debug.c
+            
             
               stm32wbxx_it.c
               1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/app_ble.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/app_ble.c
index 169e70a72..69c6c71db 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/app_ble.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/app_ble.c
@@ -44,12 +44,12 @@
 #define FAST_CONN_ADV_INTERVAL_MAX  (0x30)  /**< 30ms */
 
 #define FORCE_REBOND                      0x01
-#define CONN_P1_7_5                        (CONN_P(7.5))
-#define CONN_P2_7_5                        (CONN_P(7.5))
+#define CONN_P1_7_5                     (CONN_P(7.5))
+#define CONN_P2_7_5                     (CONN_P(7.5))
 #define CONN_P1_50                        (CONN_P(50))
 #define CONN_P2_50                        (CONN_P(50))
-#define CONN_P1_400                        (CONN_P(400))
-#define CONN_P2_400                        (CONN_P(400))
+#define CONN_P1_400                       (CONN_P(400))
+#define CONN_P2_400                       (CONN_P(400))
 
 #define BD_ADDR_SIZE_LOCAL    6
 /* Private typedef -----------------------------------------------------------*/
@@ -218,6 +218,8 @@ static const uint8_t BLE_CFG_ER_VALUE[16] = CFG_BLE_ERK;
 static const char local_name[] = { AD_TYPE_COMPLETE_LOCAL_NAME, 'D', 'T', '_', 'S', 'E', 'R', 'V', 'E', 'R' };
 #endif
 
+uint8_t index_con_int, mutex; 
+
 uint8_t const manuf_data[22] = { 2, AD_TYPE_TX_POWER_LEVEL, 0x00 /* 0 dBm */, /* Trasmission Power */
     10, AD_TYPE_COMPLETE_LOCAL_NAME, 'D', 'T', '_', 'S', 'E', 'R', 'V', 'E', 'R', /* Complete Name */
     7, AD_TYPE_MANUFACTURER_SPECIFIC_DATA, 0x01/*SKD version */,
@@ -237,6 +239,7 @@ static void Ble_Tl_Init(void);
 static void Ble_Hci_Gap_Gatt_Init(void);
 static const uint8_t* BleGetBdAddress(void);
 static void LinkConfiguration(void);
+uint8_t TimerDataThroughputWrite_Id;
 
 #if (CFG_BLE_CENTRAL != 0)
 static void GapProcReq(GapProcId_t GapProcId);
@@ -247,6 +250,7 @@ static void Connection_Update(void);
 
 #if (CFG_BLE_PERIPHERAL != 0)
 static void Adv_Request(void);
+static void DataThroughput_proc(void);
 #endif
 
 
@@ -306,12 +310,16 @@ void APP_BLE_Init( void )
    * Initialization of the BLE Services
    */
   SVCCTL_Init();
-
+  mutex = 1; 
   /**
    * From here, all initialization are BLE application specific
    */
 #if(CFG_BLE_PERIPHERAL != 0)
   UTIL_SEQ_RegTask( 1<data;
       switch (blue_evt->ecode)
       {
-        case EVT_BLUE_ATT_EXCHANGE_MTU_RESP:
-          APP_DBG_MSG("EVT_BLUE_ATT_EXCHANGE_MTU_RESP \n");
-          exchange_mtu_resp = (aci_att_exchange_mtu_resp_event_rp0 *)blue_evt->data;
-          APP_DBG_MSG("MTU_size = %d \n",exchange_mtu_resp->Server_RX_MTU );
-          APP_DBG_MSG("MTU_handle = 0x%x \n",exchange_mtu_resp->Connection_Handle );
-          break;
 
         case EVT_BLUE_ATT_READ_BY_GROUP_TYPE_RESP:
         {
@@ -326,7 +326,7 @@ static SVCCTL_EvtAckStatus_t DTC_Event_Handler( void *Event )
               && (pr->Attribute_Value_Length > (2)))
           {
             NotificationData.DataTransfered.Length = pr->Attribute_Value_Length;
-            NotificationData.DataTransfered.pPayload =  pr->Attribute_Value;
+            NotificationData.DataTransfered.pPayload = (pr->Attribute_Value);
             NotificationData.DataTransfered.pPayload_n = *((uint32_t*) &(pr->Attribute_Value[0]));
             __disable_irq();
             if (NotificationData.DataTransfered.pPayload_n >= (NotificationData.DataTransfered.pPayload_n_1 + 2))
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/dt_server_app.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/dt_server_app.c
index 47afafcee..5ebaed219 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/dt_server_app.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/dt_server_app.c
@@ -57,15 +57,23 @@ typedef struct
 /* Private defines -----------------------------------------------------------*/
 /* Private macros ------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-static DTS_App_Context_t DataTransferServerContext;
+DTS_App_Context_t DataTransferServerContext;
 static uint8_t Notification_Data_Buffer[DATA_NOTIFICATION_MAX_PACKET_SIZE]; /* DATA_NOTIFICATION_MAX_PACKET_SIZE data + CRC */
+uint32_t DataReceived;
 
 /* Global variables ----------------------------------------------------------*/
 /* Functions Definition ------------------------------------------------------*/
 /* Private functions ----------------------------------------------------------*/
 static void ButtonTriggerReceived(void);
+static void DT_App_Button2_Trigger_Received( void );
 static void SendData(void);
+static void BLE_App_Delay_DataThroughput( void );
+extern uint16_t Att_Mtu_Exchanged;
+extern uint8_t TimerDataThroughputWrite_Id;
 
+#define DEFAULT_TS_MEASUREMENT_INTERVAL   (1000000/CFG_TS_TICK_VAL)  /**< 1s */
+#define DELAY_1s  (1*DEFAULT_TS_MEASUREMENT_INTERVAL)
+#define TIMEUNIT  1
 /*************************************************************
  *
  * PUBLIC FUNCTIONS
@@ -76,7 +84,9 @@ void DTS_App_Init(void)
   uint8_t i;
 
   UTIL_SEQ_RegTask( 1<DataTransfered.Length;
+        HW_TS_Start(TimerDataThroughputWrite_Id, DELAY_1s);
+      }
+      else
+      {
+        DataReceived += pNotification->DataTransfered.Length;
+      }
+      break;
 
     case DTS_STM_GATT_TX_POOL_AVAILABLE:
       DataTransferServerContext.DtFlowStatus = DTS_APP_FLOW_ON;
@@ -155,7 +193,8 @@ static void SendData( void )
     Notification_Data_Buffer[DATA_NOTIFICATION_MAX_PACKET_SIZE - 1] = crc_result;
 
     DataTransferServerContext.TxData.pPayload = Notification_Data_Buffer;
-    DataTransferServerContext.TxData.Length = DATA_NOTIFICATION_MAX_PACKET_SIZE; /* DATA_NOTIFICATION_MAX_PACKET_SIZE */
+    //DataTransferServerContext.TxData.Length = DATA_NOTIFICATION_MAX_PACKET_SIZE; /* DATA_NOTIFICATION_MAX_PACKET_SIZE */
+    DataTransferServerContext.TxData.Length = Att_Mtu_Exchanged-10;
 
     status = DTS_STM_UpdateChar(DATA_TRANSFER_TX_CHAR_UUID, (uint8_t *) &DataTransferServerContext.TxData);
     if (status == BLE_STATUS_INSUFFICIENT_RESOURCES)
@@ -170,7 +209,10 @@ static void SendData( void )
   }
   return;
 }
-
+void Resume_Notification(void)
+{
+  DataTransferServerContext.DtFlowStatus = DTS_APP_FLOW_ON;
+}
 static void ButtonTriggerReceived( void )
 {
   if(DataTransferServerContext.ButtonTransferReq != DTS_APP_TRANSFER_REQ_OFF)
@@ -188,4 +230,25 @@ static void ButtonTriggerReceived( void )
   return;
 }
 
+static void DT_App_Button2_Trigger_Received( void )
+{
+  APP_DBG_MSG("change PHY \n");
+  BLE_SVC_GAP_Change_PHY();
+  return;
+}
+
+static void BLE_App_Delay_DataThroughput(void)
+{
+  uint32_t DataThroughput;
+  DTS_STM_Payload_t ThroughputToSend; 
+  
+  DataThroughput = (uint32_t)(DataReceived/TIMEUNIT);
+  APP_DBG_MSG("DataThroughput = %ld  bytes/s\n", DataThroughput);
+  
+  ThroughputToSend.Length = 4;
+  ThroughputToSend.pPayload = (uint8_t*)&DataThroughput;
+  
+  DTS_STM_UpdateCharThroughput( (DTS_STM_Payload_t*) &ThroughputToSend);  
+  DataReceived = 0;
+}
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/dt_server_app.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/dt_server_app.h
index a7da93a02..555bb8f72 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/dt_server_app.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/dt_server_app.h
@@ -35,6 +35,7 @@ extern "C" {
   /* Exported functions ------------------------------------------------------- */
   void DTS_App_Init(void);
   void DTS_App_KeyButtonAction(void);
+  void DTS_App_KeyButton2Action( void );
   void DTS_App_TxPoolAvailableNotification(void);
 
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/dts.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/dts.c
index 09861152d..60daa3acb 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/dts.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/dts.c
@@ -42,6 +42,26 @@ const uint8_t DT_REQ_CHAR_UUID[16] =
 const uint8_t DT_REQ_CHAR_UUID[2] = { 0x81, 0xFE };
 #endif
 
+#if (UUID_128_SUPPORTED == 1)
+const uint8_t DT_REQ_CHAR2_UUID[16] =
+{ 0x19, 0xed, 0x82, 0xae,
+  0xed, 0x21, 0x4c, 0x9d,
+  0x41, 0x45, 0x22, 0x8e,
+  0x82, 0xFE, 0x00, 0x00};
+#else
+const uint8_t DT_REQ_CHAR2_UUID[2] = { 0x82, 0xFE };
+#endif
+
+#if (UUID_128_SUPPORTED == 1)
+const uint8_t DT_REQ_CHAR3_UUID[16] =
+{ 0x19, 0xed, 0x82, 0xae,
+  0xed, 0x21, 0x4c, 0x9d,
+  0x41, 0x45, 0x22, 0x8e,
+  0x83, 0xFE, 0x00, 0x00};
+#else
+const uint8_t DT_REQ_CHAR3_UUID[2] = { 0x83, 0xFE };
+#endif
+
 #if (UUID_128_SUPPORTED == 1)
 const uint8_t DT_REQ_SERV_UUID[16] =
 { 0x19, 0xed, 0x82, 0xae,
@@ -63,6 +83,8 @@ typedef struct
 {
 uint16_t DataTransferSvcHdle; /**< Service handle */
 uint16_t DataTransferTxCharHdle; /**< Characteristic handle */
+uint16_t DataTransferRxCharHdle; /**< Characteristic handle */
+uint16_t DataTransferTxChar3Hdle; /**< Characteristic handle */
 } DataTransferSvcContext_t;
 
 /* Private defines -----------------------------------------------------------*/
@@ -74,6 +96,7 @@ uint16_t DataTransferTxCharHdle; /**< Characteristic handle */
 static tBleStatus TX_Update_Char( DTS_STM_Payload_t *pDataValue );
 static SVCCTL_EvtAckStatus_t DTS_Event_Handler( void *pckt );
 static DataTransferSvcContext_t aDataTransferContext;
+extern uint16_t Att_Mtu_Exchanged;
 
 /* Functions Definition ------------------------------------------------------*/
 /* Private functions ----------------------------------------------------------*/
@@ -89,6 +112,7 @@ static SVCCTL_EvtAckStatus_t DTS_Event_Handler( void *Event )
   hci_event_pckt * event_pckt;
   evt_blue_aci * blue_evt;
   aci_gatt_attribute_modified_event_rp0 * attribute_modified;
+  aci_att_exchange_mtu_resp_event_rp0 * exchange_mtu_resp;
 
   DTS_STM_App_Notification_evt_t Notification;
 
@@ -103,6 +127,12 @@ static SVCCTL_EvtAckStatus_t DTS_Event_Handler( void *Event )
 
       switch (blue_evt->ecode)
       {
+        case EVT_BLUE_ATT_EXCHANGE_MTU_RESP:
+          APP_DBG_MSG("EVT_BLUE_ATT_EXCHANGE_MTU_RESP \n");					
+          exchange_mtu_resp = (aci_att_exchange_mtu_resp_event_rp0 *)blue_evt->data;
+          APP_DBG_MSG("MTU_size = %d \n",exchange_mtu_resp->Server_RX_MTU );
+          Att_Mtu_Exchanged = exchange_mtu_resp->Server_RX_MTU;
+          break;
         /* server */
         case EVT_BLUE_GATT_ATTRIBUTE_MODIFIED:
         {
@@ -125,8 +155,38 @@ static SVCCTL_EvtAckStatus_t DTS_Event_Handler( void *Event )
               DTS_Notification(&Notification);
             }
           }
-        }
+          if (attribute_modified->Attr_Handle == (aDataTransferContext.DataTransferTxChar3Hdle + 2))
+          {
+            /**
+            * Notify to application to start measurement
+            */
+            if (attribute_modified->Attr_Data[0] & DTS_STM_NOTIFICATION_MASK)
+            {
+              APP_DBG_MSG("notification enabled\n");
+              Notification.Evt_Opcode = DTC_NOTIFICATION_ENABLED;
+              DTS_Notification(&Notification);
+            }
+            else
+            {
+              APP_DBG_MSG("notification disabled\n");
+              Notification.Evt_Opcode = DTC_NOTIFICATION_DISABLED;
+              DTS_Notification(&Notification);
+            }
+          }
+          if(attribute_modified->Attr_Handle == (aDataTransferContext.DataTransferRxCharHdle + 1))
+          {
+            return_value = SVCCTL_EvtAckFlowEnable;
+            
+            APP_DBG_MSG("length = %x, offset = %x\r\n", attribute_modified->Attr_Data_Length,attribute_modified->Offset);
+            Notification.Evt_Opcode = DTS_STM_DATA_RECEIVED;
+            Notification.DataTransfered.Length=attribute_modified->Attr_Data_Length;
+            DTS_Notification(&Notification); 
+          }
+          }
           break;
+        case EVT_BLUE_GATT_TX_POOL_AVAILABLE:
+          Resume_Notification();
+          break; 
 
         default:
           break;
@@ -207,6 +267,42 @@ void DTS_STM_Init( void )
     APP_DBG_MSG("error add char Tx 0x%x\n", hciCmdResult);
   }
 
+  /**
+   *  Add Data Transfer RX Characteristic
+   */
+  hciCmdResult = aci_gatt_add_char(aDataTransferContext.DataTransferSvcHdle,
+  DT_UUID_LENGTH,
+                    (Char_UUID_t *) DT_REQ_CHAR2_UUID,
+                    255, /* DATA_TRANSFER_NOTIFICATION_LEN_MAX, */
+                    CHAR_PROP_WRITE,
+                    ATTR_PERMISSION_NONE,
+                    GATT_NOTIFY_ATTRIBUTE_WRITE, /* gattEvtMask */
+                    10, /* encryKeySize */
+                    1, /* isVariable */
+                    &(aDataTransferContext.DataTransferRxCharHdle));
+  if (hciCmdResult != 0)
+  {
+    APP_DBG_MSG("error add char Tx\n");
+  }
+  
+  /**
+   *  Add Data Transfer TX Characteristic
+   */
+  hciCmdResult = aci_gatt_add_char(aDataTransferContext.DataTransferSvcHdle,
+  DT_UUID_LENGTH,
+                    (Char_UUID_t *) DT_REQ_CHAR3_UUID,
+                    255, /* DATA_TRANSFER_NOTIFICATION_LEN_MAX, */
+                    CHAR_PROP_NOTIFY,
+                    ATTR_PERMISSION_NONE,
+                    GATT_DONT_NOTIFY_EVENTS, /* gattEvtMask */
+                    10, /* encryKeySize */
+                    1, /* isVariable */
+                    &(aDataTransferContext.DataTransferTxChar3Hdle));
+  if (hciCmdResult != 0)
+  {
+    APP_DBG_MSG("error add char Tx\n");
+  }
+  
   return;
 }
 
@@ -231,4 +327,19 @@ tBleStatus DTS_STM_UpdateChar( uint16_t UUID , uint8_t *pPayload )
   return result;
 }/* end DTS_STM_UpdateChar() */
 
+tBleStatus DTS_STM_UpdateCharThroughput(DTS_STM_Payload_t *pDataValue )
+{
+  tBleStatus result = BLE_STATUS_INVALID_PARAMS;
+  /**
+   *  Notification Data Transfer Packet
+   */
+  result = aci_gatt_update_char_value(
+                                   aDataTransferContext.DataTransferSvcHdle,
+                                   aDataTransferContext.DataTransferTxChar3Hdle,
+                                   0, /* charValOffset */
+                                   pDataValue->Length, /* charValueLen */
+                                   (uint8_t *) pDataValue->pPayload);
+  return result;
+}/* end DTS_STM_UpdateChar() */
+
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/dts.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/dts.h
index bd6ec4fbe..283664c45 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/dts.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/STM32_WPAN/App/dts.h
@@ -36,6 +36,7 @@ extern "C"
 typedef struct
 {
   uint8_t *pPayload;
+//  uint32_t *pPayload;
   uint32_t pPayload_n_1;
   uint32_t pPayload_n;
   uint32_t Length;
@@ -46,10 +47,15 @@ typedef enum
   DTS_STM__NOTIFICATION_ENABLED,
   DTS_STM_NOTIFICATION_DISABLED,
   DTS_STM_GATT_TX_POOL_AVAILABLE,
+  DTC_NOTIFICATION_ENABLED,
+  DTC_NOTIFICATION_DISABLED,
+  DTS_STM_DATA_RECEIVED,
+  DTS_MTU_EXCHANGED,
 } DTS_STM_NotCode_t;
 
 typedef struct
 {
+  uint8_t ATT_MTU_exchanged;
   DTS_STM_NotCode_t Evt_Opcode;
   DTS_STM_Payload_t DataTransfered;
 } DTS_STM_App_Notification_evt_t;
@@ -62,6 +68,9 @@ typedef struct
 void DTS_STM_Init( void );
 tBleStatus DTS_STM_UpdateChar( uint16_t UUID , uint8_t *pPayload );
 void DTS_Notification( DTS_STM_App_Notification_evt_t *pNotification );
+void BLE_SVC_GAP_Change_PHY(void);
+void Resume_Notification(void);
+tBleStatus DTS_STM_UpdateCharThroughput(DTS_STM_Payload_t *pDataValue );
 
 #ifdef __cplusplus
 }
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/SW4STM32/BLE_DataThroughput/.project b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/SW4STM32/BLE_DataThroughput/.project
index a7ecde6df..d1bc8283e 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/SW4STM32/BLE_DataThroughput/.project
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/SW4STM32/BLE_DataThroughput/.project
@@ -59,6 +59,16 @@
 			1
 			PARENT-2-PROJECT_LOC/Core/Src/main.c
 		
+    
+			Application/Core/stm32wbxx_hal_msp.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/stm32wbxx_hal_msp.c
+		
+    
+			Application/Core/app_debug.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/app_debug.c
+		
     
 			Application/Core/stm32wbxx_it.c
 			1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/SW4STM32/BLE_DataThroughput/stm32wb55xx_flash_cm4.ld b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/SW4STM32/BLE_DataThroughput/stm32wb55xx_flash_cm4.ld
index a9ccd801e..7ac9a391f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/SW4STM32/BLE_DataThroughput/stm32wb55xx_flash_cm4.ld
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/SW4STM32/BLE_DataThroughput/stm32wb55xx_flash_cm4.ld
@@ -50,7 +50,7 @@ ENTRY(Reset_Handler)
 _estack = 0x20030000;    /* end of RAM */
 /* Generate a link error if heap and stack don't fit into RAM */
 _Min_Heap_Size = 0x400;      /* required amount of heap  */
-_Min_Stack_Size = 0x1000; /* required amount of stack */
+_Min_Stack_Size = 0x1000;   /* required amount of stack */
 
 /* Specify the memory areas */
 MEMORY
@@ -181,7 +181,7 @@ SECTIONS
   .ARM.attributes 0       : { *(.ARM.attributes) }
    MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
    MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
-   MB_MEM2                : { *(MB_MEM2) } >RAM_SHARED  
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
 }
 
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/SW4STM32/startup_stm32wb55xx_cm4.s b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/SW4STM32/startup_stm32wb55xx_cm4.s
index 023c1b016..f79eec117 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/SW4STM32/startup_stm32wb55xx_cm4.s
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/SW4STM32/startup_stm32wb55xx_cm4.s
@@ -44,21 +44,29 @@ defined in linker script */
 .word	_sbss
 /* end address for the .bss section. defined in linker script */
 .word	_ebss
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
   movs r3, #0
-  b	LoopCopyDataInit
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
 
+.section  .text.data_initializers
 CopyDataInit:
   ldr r4, [r2, r3]
   str r4, [r0, r3]
@@ -67,21 +75,31 @@ CopyDataInit:
 LoopCopyDataInit:
   adds r4, r0, r3
   cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
+  bcc  CopyDataInit
+  bx lr
 
 FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
+  str  r3, [r0]
+  adds r0, r0, #4
 
 LoopFillZerobss:
-  cmp r2, r4
+  cmp r0, r1
   bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/readme.txt b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/readme.txt
index 3d46c3da9..fb2c9dac4 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/readme.txt
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/readme.txt
@@ -86,12 +86,12 @@ Two STM32WB55xx boards are used, one central and one peripheral.
 They are both configured as GATT client and GATT server.
 They both support a Data transfer service with a transmission characteristic that supports notification.
 Both boards need to be compiled by changing the definition in app_conf.h
-Use #define CFG_BLE_CENTRAL 0 or 1
+Use #define CFG_BLE_CENTRAL 0 or 1 and CFG_SERVER_ONLY 0
 One board is defined as GAP peripheral, the other board is defined as GAP central.
 Open a VT100 terminal on Central and Peripheral side (ST Link Com Port, @115200 bauds).
 At startup the connection is established and encryption started(if #define ENCRYPTION_ON 1 uncomment in app_conf.h).
  - The peripheral device starts advertising.
- - The central device scans and automatically connects to the peripheral. 
+ - The central device scans and automatically connects to the peripheral (use of CFG_DEV_ID_PERIPH_SERVER). 
  - After pairing and authentication (if enabled),  
    the client on each device starts to search the data transfer service and characteristic.
  - Each client enables the notification of the transmission characteristic.
@@ -100,6 +100,13 @@ it stops when SW1 is pushed again (blue led is OFF).
 The notification can be started and stopped from both sides.
 On the client terminal receiving the current notification, the number of bytes per second is displayed.
 
+One STM32WB55xx board is used as peripheral and server only.
+Use #define CFG_BLE_CENTRAL 0 and CFG_SERVER_ONLY 1 (in app_conf.h)
+This board can be connected with a smartphone supporting ST BLE SENSOR application.
+Start a scan and choose DT_SERVER board to connect.
+SW1 starts the notification data.
+SW2 changes the PHY (1M or 2M). 
+
 In app_conf.h 
 if #define CFG_TX_PHY    2 and #define CFG_RX_PHY    2, link is set to 2M
 if #define CFG_TX_PHY    1 and #define CFG_RX_PHY    1, link stays at 1M
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/BLE_HealthThermometer.ioc b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/BLE_HealthThermometer.ioc
index 0ccc1c98c..d8d5929cd 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/BLE_HealthThermometer.ioc
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/BLE_HealthThermometer.ioc
@@ -94,8 +94,8 @@ Mcu.PinsNb=17
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32WB55RGVx
-MxCube.Version=5.5.0
-MxDb.Version=DB.5.0.50
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.DMA1_Channel4_IRQn=true\:15\:0\:true\:false\:true\:false\:true
 NVIC.DMA2_Channel4_IRQn=true\:15\:0\:true\:false\:true\:false\:true
@@ -157,14 +157,6 @@ PCC.Ble.ConnectionInterval=1000.0
 PCC.Ble.DataLength=6
 PCC.Ble.Mode=Advertising
 PCC.Ble.PowerLevel=Min
-PCC.Checker=true
-PCC.Line=STM32WBx5
-PCC.MCU=STM32WB55RGVx
-PCC.PartNumber=STM32WB55RGVx
-PCC.Seq0=0
-PCC.Series=STM32WB
-PCC.Temperature=25
-PCC.Vdd=3.0
 PinOutPanel.RotationAngle=0
 ProjectManager.AskForMigrate=true
 ProjectManager.BackupPrevious=false
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/app_common.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/app_common.h
index 4defc5d7a..836f40dcf 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/app_common.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/app_common.h
@@ -1,12 +1,13 @@
+/* USER CODE BEGIN Header */
 /**
  ******************************************************************************
   * File Name          : app_common.h
   * Description        : App Common application configuration file for STM32WPAN Middleware.
   *
- ******************************************************************************
+  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
@@ -16,7 +17,7 @@
   *
   ******************************************************************************
   */
-
+/* USER CODE END Header */
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef APP_COMMON_H
 #define APP_COMMON_H
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/app_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/app_conf.h
index 179a47916..a70ba80e4 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/app_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/app_conf.h
@@ -1,12 +1,12 @@
+/* USER CODE BEGIN Header */
 /**
  ******************************************************************************
   * File Name          : app_conf.h
   * Description        : Application configuration file for STM32WPAN Middleware.
-  *
- ******************************************************************************
+  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
@@ -16,6 +16,7 @@
   *
   ******************************************************************************
   */
+/* USER CODE END Header */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef APP_CONF_H
@@ -48,11 +49,11 @@
 /**
  * Define IO Authentication
  */
-#define CFG_BONDING_MODE                  (1)
-#define CFG_FIXED_PIN                     (111111)
-#define CFG_USED_FIXED_PIN                (0)
-#define CFG_ENCRYPTION_KEY_SIZE_MAX       (16)
-#define CFG_ENCRYPTION_KEY_SIZE_MIN       (8)
+#define CFG_BONDING_MODE                 (0)
+#define CFG_FIXED_PIN                    (111111)
+#define CFG_USED_FIXED_PIN               (0)
+#define CFG_ENCRYPTION_KEY_SIZE_MAX      (16)
+#define CFG_ENCRYPTION_KEY_SIZE_MIN      (8)
 
 /**
  * Define IO capabilities
@@ -63,7 +64,7 @@
 #define CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT (0x03)
 #define CFG_IO_CAPABILITY_KEYBOARD_DISPLAY   (0x04)
 
-#define CFG_IO_CAPABILITY              CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT
+#define CFG_IO_CAPABILITY               CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT
 
 /**
  * Define MITM modes
@@ -73,6 +74,35 @@
 
 #define CFG_MITM_PROTECTION             CFG_MITM_PROTECTION_REQUIRED
 
+/**
+ * Define Secure Connections Support
+ */
+#define CFG_SECURE_NOT_SUPPORTED       (0x00)
+#define CFG_SECURE_OPTIONAL            (0x01)
+#define CFG_SECURE_MANDATORY           (0x02)
+
+#define CFG_SC_SUPPORT                 CFG_SECURE_OPTIONAL
+
+/**
+ * Define Keypress Notification Support
+ */
+#define CFG_KEYPRESS_NOT_SUPPORTED      (0x00)
+#define CFG_KEYPRESS_SUPPORTED          (0x01)
+
+#define CFG_KEYPRESS_NOTIFICATION_SUPPORT             CFG_KEYPRESS_NOT_SUPPORTED
+   
+/**
+ * Numeric Comparison Answers
+ */   
+#define YES (0x01)
+#define NO  (0x00)
+
+/**
+ * Device name configuration for Generic Access Service
+ */
+#define CFG_GAP_DEVICE_NAME             "TEMPLATE"
+#define CFG_GAP_DEVICE_NAME_LENGTH      (8)
+
 /**
  * Define PHY
  */
@@ -248,7 +278,7 @@
  * Select UART interfaces
  */
 #define CFG_DEBUG_TRACE_UART    hw_uart1
-#define CFG_CONSOLE_MENU      
+#define CFG_CONSOLE_MENU      0
 /******************************************************************************
  * USB interface
  ******************************************************************************/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/app_debug.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/app_debug.h
new file mode 100644
index 000000000..4224edbe0
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/app_debug.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : app_debug.h
+  * Description        : Header for app_debug.c module
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/hw_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/hw_conf.h
index 6733a683f..5492cbb08 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/hw_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/hw_conf.h
@@ -27,6 +27,34 @@
  * Semaphores
  * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
  *****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
 /* Index of the semaphore used to manage the entry Stop Mode procedure */
 #define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/main.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/main.h
index 55097bac8..4b10d2beb 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/main.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/main.h
@@ -29,6 +29,7 @@ extern "C" {
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32wbxx_hal.h"
+#include "app_conf.h"
 
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/stm32wbxx_hal_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/stm32wbxx_hal_conf.h
index 7f1537260..d5db0e33f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/stm32wbxx_hal_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Inc/stm32wbxx_hal_conf.h
@@ -39,6 +39,7 @@
 /*#define HAL_CRC_MODULE_ENABLED   */
 #define HAL_HSEM_MODULE_ENABLED
 /*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
 #define HAL_IPCC_MODULE_ENABLED
 /*#define HAL_IRDA_MODULE_ENABLED   */
 /*#define HAL_IWDG_MODULE_ENABLED   */
@@ -70,6 +71,7 @@
 #define USE_HAL_COMP_REGISTER_CALLBACKS      0u
 #define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
 #define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
 #define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
 #define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
 #define USE_HAL_PCD_REGISTER_CALLBACKS       0u
@@ -243,6 +245,10 @@
  #include "stm32wbxx_hal_i2c.h"
 #endif /* HAL_I2C_MODULE_ENABLED */
 
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
 #ifdef HAL_IPCC_MODULE_ENABLED
  #include "stm32wbxx_hal_ipcc.h"
 #endif /* HAL_IPCC_MODULE_ENABLED */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/app_debug.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/app_debug.c
new file mode 100644
index 000000000..14ed65c22
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/app_debug.c
@@ -0,0 +1,399 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : app_debug.c
+  * Description        : Debug capabilities source file for STM32WPAN Middleware
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+#ifdef CFG_DEBUG_TRACE_UART
+#if(CFG_HW_LPUART1_ENABLED == 1)
+extern void MX_LPUART1_UART_Init(void);
+#endif
+#if(CFG_HW_USART1_ENABLED == 1)
+extern void MX_USART1_UART_Init(void);
+#endif
+#endif
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+/* USER CODE END PV */
+
+/* Global variables ----------------------------------------------------------*/
+/* USER CODE BEGIN GV */
+/* USER CODE END GV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+/* USER CODE BEGIN APPD_Init */
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+/* USER CODE END APPD_Init */
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+/* USER CODE BEGIN APPD_EnableCPU2 */
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+/* USER CODE END APPD_EnableCPU2 */
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+/* USER CODE BEGIN APPD_SetCPU2GpioConfig */
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+/* USER CODE END APPD_SetCPU2GpioConfig */
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+/* USER CODE BEGIN APPD_BleDtbCfg */
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+/* USER CODE END APPD_BleDtbCfg */
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+/* USER CODE BEGIN DbgOutputInit */
+#ifdef CFG_DEBUG_TRACE_UART
+if (CFG_DEBUG_TRACE_UART == hw_lpuart1)
+{
+#if(CFG_HW_LPUART1_ENABLED == 1)
+    MX_LPUART1_UART_Init();
+#endif
+}
+else if (CFG_DEBUG_TRACE_UART == hw_uart1)
+{
+#if(CFG_HW_USART1_ENABLED == 1)
+    MX_USART1_UART_Init();
+#endif
+}
+#endif
+
+/* USER CODE END DbgOutputInit */
+  return;
+}
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+/* USER CODE END DbgOutputTraces */
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+/* USER CODE END DbgOutputTraces */
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/app_entry.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/app_entry.c
index 7046354ac..4bb965090 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/app_entry.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/app_entry.c
@@ -29,7 +29,7 @@
 #include "stm32_seq.h"
 #include "shci_tl.h"
 #include "stm32_lpm.h"
-#include "dbg_trace.h"
+#include "app_debug.h"
 
 /* Private includes -----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
@@ -66,7 +66,6 @@ PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t BleSpareEvtBuffer[sizeof(TL_
 
 /* Private functions prototypes-----------------------------------------------*/
 static void SystemPower_Config( void );
-static void Init_Debug( void );
 static void appe_Tl_Init( void );
 static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status );
 static void APPE_SysUserEvtRx( void * pPayload );
@@ -91,7 +90,7 @@ void APPE_Init( void )
   HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
 
 /* USER CODE BEGIN APPE_Init_1 */
-  Init_Debug();
+  APPD_Init();
   
   /**
    * The Standby mode should not be entered before the initialization is over
@@ -124,47 +123,6 @@ void APPE_Init( void )
  * LOCAL FUNCTIONS
  *
  *************************************************************/
-static void Init_Debug( void )
-{
-#if (CFG_DEBUGGER_SUPPORTED == 1)
-  /**
-   * Keep debugger enabled while in any low power mode
-   */
-  HAL_DBGMCU_EnableDBGSleepMode();
-
-  /***************** ENABLE DEBUGGER *************************************/
-  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-  LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-
-#else
-
-  GPIO_InitTypeDef gpio_config = {0};
-
-  gpio_config.Pull = GPIO_NOPULL;
-  gpio_config.Mode = GPIO_MODE_ANALOG;
-
-  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOA, &gpio_config);
-  __HAL_RCC_GPIOA_CLK_DISABLE();
-
-  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOB, &gpio_config);
-  __HAL_RCC_GPIOB_CLK_DISABLE();
-
-  HAL_DBGMCU_DisableDBGSleepMode();
-  HAL_DBGMCU_DisableDBGStopMode();
-  HAL_DBGMCU_DisableDBGStandbyMode();
-
-#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
-
-#if(CFG_DEBUG_TRACE != 0)
-  DbgTraceInit();
-#endif
-
-  return;
-}
 
 /**
  * @brief  Configure the system for power optimization
@@ -239,7 +197,7 @@ static void APPE_SysUserEvtRx( void * pPayload )
 {
   UNUSED(pPayload);
   /* Traces channel initialization */
-  TL_TRACES_Init( );
+  APPD_EnableCPU2( );
 
   APP_BLE_Init( );
   UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE);
@@ -322,34 +280,6 @@ void shci_cmd_resp_wait(uint32_t timeout)
   return;
 }
 
-/**
-  * @brief  Initialisation of the trace mechanism
-  * @param  None
-  * @retval None
-  */
-#if(CFG_DEBUG_TRACE != 0)
-void DbgOutputInit( void )
-{
-    MX_USART1_UART_Init();
-
-  return;
-}
-
-/**
-  * @brief  Management of the traces
-  * @param  p_data : data
-  * @param  size : size
-  * @param  call-back :
-  * @retval None
-  */
-void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
-{
-  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
-
-  return;
-}
-#endif
-
 /* USER CODE BEGIN FD_WRAP_FUNCTIONS */
 void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin )
 {
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/hw_timerserver.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/hw_timerserver.c
index c842ba55e..e0e4fcb5d 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/hw_timerserver.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/hw_timerserver.c
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/hw_uart.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/hw_uart.c
index 9a553610d..ce910235c 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/hw_uart.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/hw_uart.c
@@ -6,7 +6,7 @@
   ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/main.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/main.c
index 7920b2d20..7cebe8df3 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/main.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/main.c
@@ -110,7 +110,6 @@ int main(void)
   /* USER CODE BEGIN 1 */
 
   /* USER CODE END 1 */
-  
 
   /* MCU Configuration--------------------------------------------------------*/
 
@@ -139,9 +138,8 @@ int main(void)
 
   /* USER CODE END 2 */
 
-  /* Init code for STM32_WPAN */  
+  /* Init code for STM32_WPAN */
   APPE_Init();
-
   /* Infinite loop */
   /* USER CODE BEGIN WHILE */
 	while(1)
@@ -166,6 +164,7 @@ void SystemClock_Config(void)
 
   /** Configure LSE Drive Capability 
   */
+  HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
   /** Configure the main internal regulator output voltage 
   */
@@ -210,7 +209,6 @@ void SystemClock_Config(void)
   PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
   PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
   PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
-
   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
   {
     Error_Handler();
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/stm32_lpm_if.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/stm32_lpm_if.c
index f024b61e3..1418e0a36 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/stm32_lpm_if.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/stm32_lpm_if.c
@@ -70,6 +70,13 @@ static void Switch_On_HSI( void );
 void PWR_EnterOffMode( void )
 {
 /* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
   /************************************************************************************
    * ENTER OFF MODE
    ***********************************************************************************/
@@ -106,6 +113,8 @@ void PWR_ExitOffMode( void )
 {
 /* USER CODE BEGIN PWR_ExitOffMode */
 
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitOffMode */
 }
 
@@ -118,6 +127,16 @@ void PWR_ExitOffMode( void )
 void PWR_EnterStopMode( void )
 {
 /* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
   /**
    * This function is called from CRITICAL SECTION
    */
@@ -202,6 +221,9 @@ void PWR_ExitStopMode( void )
 
   /* Release RCC semaphore */
   LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitStopMode */
 }
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/stm32wbxx_hal_msp.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/stm32wbxx_hal_msp.c
index f22ad0f38..fc4e64f31 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/stm32wbxx_hal_msp.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/Core/Src/stm32wbxx_hal_msp.c
@@ -293,6 +293,7 @@ void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
   /* USER CODE END RTC_MspInit 0 */
     /* Peripheral clock enable */
     __HAL_RCC_RTC_ENABLE();
+    __HAL_RCC_RTCAPB_CLK_ENABLE();
   /* USER CODE BEGIN RTC_MspInit 1 */
   HAL_RTCEx_EnableBypassShadow(hrtc);
   /* USER CODE END RTC_MspInit 1 */
@@ -315,6 +316,7 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
   /* USER CODE END RTC_MspDeInit 0 */
     /* Peripheral clock disable */
     __HAL_RCC_RTC_DISABLE();
+    __HAL_RCC_RTCAPB_CLK_DISABLE();
   /* USER CODE BEGIN RTC_MspDeInit 1 */
 
   /* USER CODE END RTC_MspDeInit 1 */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/EWARM/BLE_HealthThermometer.ewp b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/EWARM/BLE_HealthThermometer.ewp
index 00c1fa270..b7eae7d16 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/EWARM/BLE_HealthThermometer.ewp
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/EWARM/BLE_HealthThermometer.ewp
@@ -1052,6 +1052,9 @@
         
           $PROJ_DIR$\..\Core\Src\main.c
         
+        
+          $PROJ_DIR$\..\Core\Src\app_debug.c
+        
         
           $PROJ_DIR$\..\Core\Src\app_entry.c
         
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/MDK-ARM/BLE_HealthThermometer.uvprojx b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/MDK-ARM/BLE_HealthThermometer.uvprojx
index 1bb54013c..425a8d05a 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/MDK-ARM/BLE_HealthThermometer.uvprojx
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/MDK-ARM/BLE_HealthThermometer.uvprojx
@@ -420,6 +420,11 @@
               1
               ../Core/Src/main.c
             
+            
+              app_debug.c
+              1
+              ../Core/Src/app_debug.c
+            
             
               app_entry.c
               1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/STM32_WPAN/App/app_ble.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/STM32_WPAN/App/app_ble.c
index 6a21d2ac7..a2aa75436 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/STM32_WPAN/App/app_ble.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/STM32_WPAN/App/app_ble.c
@@ -387,7 +387,7 @@ SVCCTL_UserEvtFlowStatus_t SVCCTL_App_Notification( void *pckt )
       /* USER CODE END EVT_LE_META_EVENT */
       switch (meta_evt->subevent)
       {
-        case EVT_LE_CONN_UPDATE_COMPLETE: 
+        case EVT_LE_CONN_UPDATE_COMPLETE:
           APP_DBG_MSG("\r\n\r** CONNECTION UPDATE EVENT WITH CLIENT \n");
 
           /* USER CODE BEGIN EVT_LE_CONN_UPDATE_COMPLETE */
@@ -682,11 +682,11 @@ static void Ble_Hci_Gap_Gatt_Init(void){
    */
   BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode = CFG_MITM_PROTECTION;
   BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data_Present = 0;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin = 8;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax = 16;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin = 1;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin = 111111;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode = 1;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin = CFG_ENCRYPTION_KEY_SIZE_MIN;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax = CFG_ENCRYPTION_KEY_SIZE_MAX;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin = CFG_USED_FIXED_PIN;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin = CFG_FIXED_PIN;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode = CFG_BONDING_MODE;
   for (index = 0; index < 16; index++)
   {
     BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data[index] = (uint8_t) index;
@@ -694,14 +694,14 @@ static void Ble_Hci_Gap_Gatt_Init(void){
 
   aci_gap_set_authentication_requirement(BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode,
-                                         1,
-                                         0,
+                                         CFG_SC_SUPPORT,
+                                         CFG_KEYPRESS_NOTIFICATION_SUPPORT,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin,
-                                         0
-                                        );
+                                         PUBLIC_ADDR
+                                         );
 
   /**
    * Initialize whitelist
@@ -766,6 +766,7 @@ static void Adv_Request(APP_BLE_ConnStatus_t New_Status)
         BleApplicationContext.BleApplicationContext_legacy.advtServUUID,
         0,
         0);
+
     if (ret == BLE_STATUS_SUCCESS)
     {
       if (New_Status == APP_BLE_FAST_ADV)
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/STM32_WPAN/App/ble_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/STM32_WPAN/App/ble_conf.h
index d36d2104d..9e211d8f6 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/STM32_WPAN/App/ble_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/STM32_WPAN/App/ble_conf.h
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/STM32_WPAN/App/ble_dbg_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/STM32_WPAN/App/ble_dbg_conf.h
index 6a6aa1ae9..46ade119f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/STM32_WPAN/App/ble_dbg_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/STM32_WPAN/App/ble_dbg_conf.h
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/STM32_WPAN/Target/hw_ipcc.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/STM32_WPAN/Target/hw_ipcc.c
index a0d8b3b5b..c6e1ca97a 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/STM32_WPAN/Target/hw_ipcc.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/STM32_WPAN/Target/hw_ipcc.c
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/SW4STM32/BLE_HealthThermometer/.project b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/SW4STM32/BLE_HealthThermometer/.project
index 99b5a3d79..5b62181ce 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/SW4STM32/BLE_HealthThermometer/.project
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/SW4STM32/BLE_HealthThermometer/.project
@@ -39,6 +39,11 @@
 			1
 			PARENT-2-PROJECT_LOC/Core/Src/main.c
 		
+	
+			Application/User/Core/app_debug.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/app_debug.c
+		
     
 			Application/User/Core/app_entry.c
 			1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/SW4STM32/BLE_HealthThermometer/stm32wb55xx_flash_cm4.ld b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/SW4STM32/BLE_HealthThermometer/stm32wb55xx_flash_cm4.ld
index a9ccd801e..7ac9a391f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/SW4STM32/BLE_HealthThermometer/stm32wb55xx_flash_cm4.ld
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/SW4STM32/BLE_HealthThermometer/stm32wb55xx_flash_cm4.ld
@@ -50,7 +50,7 @@ ENTRY(Reset_Handler)
 _estack = 0x20030000;    /* end of RAM */
 /* Generate a link error if heap and stack don't fit into RAM */
 _Min_Heap_Size = 0x400;      /* required amount of heap  */
-_Min_Stack_Size = 0x1000; /* required amount of stack */
+_Min_Stack_Size = 0x1000;   /* required amount of stack */
 
 /* Specify the memory areas */
 MEMORY
@@ -181,7 +181,7 @@ SECTIONS
   .ARM.attributes 0       : { *(.ARM.attributes) }
    MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
    MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
-   MB_MEM2                : { *(MB_MEM2) } >RAM_SHARED  
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
 }
 
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/SW4STM32/startup_stm32wb55xx_cm4.s b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/SW4STM32/startup_stm32wb55xx_cm4.s
index 023c1b016..f79eec117 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/SW4STM32/startup_stm32wb55xx_cm4.s
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HealthThermometer/SW4STM32/startup_stm32wb55xx_cm4.s
@@ -44,21 +44,29 @@ defined in linker script */
 .word	_sbss
 /* end address for the .bss section. defined in linker script */
 .word	_ebss
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
   movs r3, #0
-  b	LoopCopyDataInit
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
 
+.section  .text.data_initializers
 CopyDataInit:
   ldr r4, [r2, r3]
   str r4, [r0, r3]
@@ -67,21 +75,31 @@ CopyDataInit:
 LoopCopyDataInit:
   adds r4, r0, r3
   cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
+  bcc  CopyDataInit
+  bx lr
 
 FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
+  str  r3, [r0]
+  adds r0, r0, #4
 
 LoopFillZerobss:
-  cmp r2, r4
+  cmp r0, r1
   bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/BLE_HeartRate.ioc b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/BLE_HeartRate.ioc
index 2dae347ef..fe9b0fb92 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/BLE_HeartRate.ioc
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/BLE_HeartRate.ioc
@@ -94,8 +94,8 @@ Mcu.PinsNb=17
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32WB55RGVx
-MxCube.Version=5.5.0
-MxDb.Version=DB.5.0.50
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.DMA1_Channel4_IRQn=true\:15\:0\:true\:false\:true\:false\:true
 NVIC.DMA2_Channel4_IRQn=true\:15\:0\:true\:false\:true\:false\:true
@@ -157,14 +157,6 @@ PCC.Ble.ConnectionInterval=1000.0
 PCC.Ble.DataLength=6
 PCC.Ble.Mode=Advertising
 PCC.Ble.PowerLevel=Min
-PCC.Checker=true
-PCC.Line=STM32WBx5
-PCC.MCU=STM32WB55RGVx
-PCC.PartNumber=STM32WB55RGVx
-PCC.Seq0=0
-PCC.Series=STM32WB
-PCC.Temperature=25
-PCC.Vdd=3.0
 PinOutPanel.RotationAngle=0
 ProjectManager.AskForMigrate=true
 ProjectManager.BackupPrevious=false
@@ -295,8 +287,9 @@ STM32_WPAN.CFG_RTCCLK_DIVIDER_CONF=0
 STM32_WPAN.CUSTOM_P2P_SERVER=Disabled
 STM32_WPAN.CUSTOM_TEMPLATE=Disabled
 STM32_WPAN.DBG_TRACE_UART_CFG=hw_uart1
-STM32_WPAN.IPParameters=P2P_SERVER_NUMBER,CFG_FAST_CONN_ADV_INTERVAL_MAX_HEXA,CFG_LP_CONN_ADV_INTERVAL_MAX_HEXA,LOCAL_NAME_FORMATTED,CFG_HW_LPUART1_ENABLED,CFG_DEBUG_BLE_TRACE,CFG_DEBUG_APP_TRACE,DBG_TRACE_UART_CFG,CFG_ADV_BD_ADDRESS,CFG_LP_CONN_ADV_INTERVAL_MAX,CFG_LP_CONN_ADV_INTERVAL_MIN,CFG_HW_LPUART1_DMA_TX_SUPPORTED,CFG_HW_USART1_ENABLED,CFG_LPM_SUPPORTED,L2CAP_REQUEST_NEW_CONN_PARAM,CUSTOM_P2P_SERVER,BT_SIG_HEART_RATE_SENSOR,CFG_DEBUGGER_SUPPORTED,BLE_DBG_DIS_EN,BLE_DBG_HRS_EN,BLE_DBG_SVCCTL_EN,BLE_APPLICATION_TYPE,BT_SIG_BEACON,BT_SIG_BLOOD_PRESSURE_SENSOR,BT_SIG_HEALTH_THERMOMETER_SENSOR,CUSTOM_TEMPLATE,BLE_CFG_DIS_MANUFACTURER_NAME_STRING,BLE_CFG_DIS_MODEL_NUMBER_STRING,BLE_CFG_DIS_SERIAL_NUMBER_STRING,BLE_CFG_DIS_HARDWARE_REVISION_STRING,BLE_CFG_DIS_FIRMWARE_REVISION_STRING,BLE_CFG_DIS_SOFTWARE_REVISION_STRING,BLE_CFG_DIS_SYSTEM_ID,BLE_CFG_DIS_IEEE_CERTIFICATION,BLE_CFG_DIS_PNP_ID,BLE_CFG_HRS_BODY_SENSOR_LOCATION_CHAR,BLE_CFG_HRS_ENERGY_EXPENDED_INFO_FLAG,BLE_CFG_HRS_ENERGY_RR_INTERVAL_FLAG,CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER,CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO,CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO,CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION,CFG_HW_RESET_BY_FW,CFG_FAST_CONN_ADV_INTERVAL_MIN,CFG_FAST_CONN_ADV_INTERVAL_MAX,CFG_IO_CAPABILITY,CFG_MITM_PROTECTION,CFG_RTCCLK_DIVIDER_CONF,CFG_DEBUG_TRACE_UART,BLE_DBG_APP_EN,CFG_DEBUG_TRACE_LIGHT
+STM32_WPAN.IPParameters=P2P_SERVER_NUMBER,CFG_FAST_CONN_ADV_INTERVAL_MAX_HEXA,CFG_LP_CONN_ADV_INTERVAL_MAX_HEXA,LOCAL_NAME_FORMATTED,CFG_HW_LPUART1_ENABLED,CFG_DEBUG_BLE_TRACE,CFG_DEBUG_APP_TRACE,DBG_TRACE_UART_CFG,CFG_ADV_BD_ADDRESS,CFG_LP_CONN_ADV_INTERVAL_MAX,CFG_LP_CONN_ADV_INTERVAL_MIN,CFG_HW_LPUART1_DMA_TX_SUPPORTED,CFG_HW_USART1_ENABLED,CFG_LPM_SUPPORTED,L2CAP_REQUEST_NEW_CONN_PARAM,CUSTOM_P2P_SERVER,BT_SIG_HEART_RATE_SENSOR,CFG_DEBUGGER_SUPPORTED,BLE_DBG_DIS_EN,BLE_DBG_HRS_EN,BLE_DBG_SVCCTL_EN,BLE_APPLICATION_TYPE,BT_SIG_BEACON,BT_SIG_BLOOD_PRESSURE_SENSOR,BT_SIG_HEALTH_THERMOMETER_SENSOR,CUSTOM_TEMPLATE,BLE_CFG_DIS_MANUFACTURER_NAME_STRING,BLE_CFG_DIS_MODEL_NUMBER_STRING,BLE_CFG_DIS_SERIAL_NUMBER_STRING,BLE_CFG_DIS_HARDWARE_REVISION_STRING,BLE_CFG_DIS_FIRMWARE_REVISION_STRING,BLE_CFG_DIS_SOFTWARE_REVISION_STRING,BLE_CFG_DIS_SYSTEM_ID,BLE_CFG_DIS_IEEE_CERTIFICATION,BLE_CFG_DIS_PNP_ID,BLE_CFG_HRS_BODY_SENSOR_LOCATION_CHAR,BLE_CFG_HRS_ENERGY_EXPENDED_INFO_FLAG,BLE_CFG_HRS_ENERGY_RR_INTERVAL_FLAG,CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER,CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO,CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO,CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION,CFG_HW_RESET_BY_FW,CFG_FAST_CONN_ADV_INTERVAL_MIN,CFG_FAST_CONN_ADV_INTERVAL_MAX,CFG_IO_CAPABILITY,CFG_MITM_PROTECTION,CFG_RTCCLK_DIVIDER_CONF,CFG_DEBUG_TRACE_UART,BLE_DBG_APP_EN,CFG_DEBUG_TRACE_LIGHT,LOCAL_NAME
 STM32_WPAN.L2CAP_REQUEST_NEW_CONN_PARAM=1
+STM32_WPAN.LOCAL_NAME=HRSTM
 STM32_WPAN.LOCAL_NAME_FORMATTED=,'H','R','S','T','M'
 STM32_WPAN.P2P_SERVER_NUMBER=P2P_SERVER1
 USART1.AutoBaudRateEnableParam=UART_ADVFEATURE_AUTOBAUDRATE_DISABLE
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Binary/BLE_HeartRate_reference.hex b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Binary/BLE_HeartRate_reference.hex
index feea2aefa..814dd6188 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Binary/BLE_HeartRate_reference.hex
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Binary/BLE_HeartRate_reference.hex
@@ -1,1049 +1,1093 @@
 :020000040800F2
-:10000000F81400204D4000085D3E00085F3E0008E7
-:10001000613E0008633E0008653E000800000000E5
-:10002000000000000000000000000000673E000823
-:10003000693E0008000000006B3E00086D3E0008AD
-:10004000694000086D40000871400008AB3E0008A0
-:1000500075400008794000089F3E0008A53E000852
-:100060007D40000881400008993E00088540000856
-:10007000894000088D400008713E0008914000084A
-:1000800095400008994000089D400008A1400008E4
-:10009000A5400008A9400008AD400008B140000894
-:1000A000B5400008B9400008BD400008C140000844
-:1000B000C5400008C9400008CD400008D1400008F4
-:1000C000D5400008D9400008DD400008E1400008A4
-:1000D000773E00087D3E0008E5400008E940000842
-:1000E000ED400008F1400008F5400008F940000824
-:1000F000B33E0008AF3E0008FD4000080141000883
-:1001000005410008094100080D410008114100089F
-:1001100015410008194100081D410008214100084F
-:100120002541000829410008833E00082D410008B0
-:100130003141000835410008394100084FF0B04016
+:10000000F814002009430008094100080B410008CA
+:100010000D4100080F4100081141000800000000D8
+:100020000000000000000000000000001341000874
+:1000300015410008000000001741000819410008A0
+:1000400025430008294300082D43000857410008B4
+:1000500031430008354300084B4100085141000876
+:10006000394300083D43000845410008414300086A
+:1000700045430008494300081D4100084D4300085E
+:100080005143000855430008594300085D430008E8
+:100090006143000865430008694300086D43000898
+:1000A0007143000875430008794300087D43000848
+:1000B0008143000885430008894300088D430008F8
+:1000C0009143000895430008994300089D430008A8
+:1000D0002341000829410008A1430008A543000866
+:1000E000A9430008AD430008B1430008B543000828
+:1000F0005F4100085B410008B9430008BD430008A8
+:10010000C1430008C5430008C9430008CD430008A7
+:10011000D1430008D5430008D9430008DD43000857
+:10012000E1430008E54300082F410008E9430008C7
+:10013000ED430008F1430008F54300084FF0B040DC
 :10014000006800F0F000B02888BFB02070472DE9AB
-:10015000F041040068D0207881064FF0B04539D5D1
-:10016000A868E96810F00C0001F0030104D00C2825
-:1001700008BF012940F083802868800702D5E06924
-:10018000002851D0FFF7DAFF616A884207D208469B
-:1001900000F0A4FB00281BD100F05AFA10E02868F8
-:1001A00020F0F000014329606968206A21F47F4152
-:1001B00041EA00216960606A00F090FB002807D1E5
-:1001C00000F02EFCDFF8AC07006800F0B7FC002858
-:1001D00040F088812078C10711D5A868E96800F04F
-:1001E0000C00082801F0030103D00C2808BF0329E4
-:1001F00067D12868800302D56068002814D0217870
-:1002000088071AD5A868E96800F00C00042801F0F6
-:10021000030104D00C2808BF022940F08780286819
-:10022000400503D5E068002800F05C81696820691A
-:1002300021F0FE4141EA006169602168DFF838671A
-:1002400011F0180F00F078816069002800F0A88094
-:10025000C906706840F19580800707D4706840F047
-:10026000010000F00EFA07467068800700F13C813B
-:1002700000F086FCC01B0328F6D30320E1E1E0690F
-:1002800078B1296841F0010100F0D4FA06462868E7
-:10029000800700F1388100F073FC801B0328F6D33F
-:1002A000EBE728684008400000F0E5F906462868BA
-:1002B00000F0CAF98ED000F063FC801B0328F6D34F
-:1002C000DBE76068B0F5803F06D0B0F5A02F296865
-:1002D00007D141F480212960286840F480302860EB
-:1002E00006E021F4803129602A6822F480222A6005
-:1002F000606860B100F044FC0646286880033FF562
-:100300007EAF00F03DFC801B6528F6D3B5E700F01A
-:1003100037FC06462868400C10F001003FF46FAF30
-:1003200000F02EFC801B6528F4D3A6E7E06878B1C6
-:10033000296841F4807100F07DFA0646286840057E
-:1003400000F1E48000F01CFC801B0328F6D394E746
-:10035000286820F4807000F08EF906462868800A2C
-:1003600010F001003FF469AF00F00AFC801B032885
-:10037000F4D382E700F004FCC01B0328C0F0D8804F
-:100380007BE740F0010000F07CF9074670688007C9
-:1003900000F1E98000F0F4FBC01B0328F6D36CE702
-:1003A000706820F0040000F06CF907467068C0081F
-:1003B00010F0010000F0E68000F0E2FBC01B042812
-:1003C000F4D35AE70528306806D140F004003060C5
-:1003D000316841F0010105E04008400030603168BB
-:1003E00021F004013160A06841F2893768B100F062
-:1003F000C7FB80463068800700F1D98000F0C0FB61
-:10040000A0EB0800B842F5D337E700F0B9FB80460F
-:10041000306800F019F900F0CA8000F0B1FBA0EBE1
-:100420000800B842F4D328E700F0AAFBC01B032859
-:10043000C0F0CB8021E7B06840084000B06000F019
-:100440009FFB0746B06800F0FFF800F0C28000F0A4
-:1004500097FBC01B0328F5D30FE700F091FB801B2F
-:100460000328C0F0C88008E700F08AFB001B0328BF
-:10047000C0F0E28001E7E968DFF80005890889003B
-:10048000E960E9680140E96000F07AFB044600F0A9
-:10049000EDF825D000F074FB001B0328F7D3ECE641
-:1004A00001281FD0E868226B00F00301914202BFCF
-:1004B00000F07001626B914214D1A26BC0F306216F
-:1004C000914202BF00F47811E26B91420AD1226C92
-:1004D00000F06061914202BF00F06040616C8842B0
-:1004E00000F0AE800120ACE0706840F0040000F045
-:1004F000C8F807467068000710D400F041FBC01B25
-:100500000428F7D3B9E600F0A3F863E66868216928
-:1005100020F0FE4040EA016068608EE67068A169E4
-:1005200020F4706040EA0120706000F0A7F80746F0
-:1005300000F089F87FF41EAF2078410737D5DFF847
-:1005400040743868C10529D400F020FB00F018FB86
-:1005500080463868C10521D400F012FBA0EB0800EA
-:100560000328F6D389E6706820F004007060706894
-:10057000C00810F00100DFD000F002FBC01B04280F
-:10058000F5D37AE600F07AF8074600F05CF8D3D0AD
-:1005900000F0F6FAC01B0328F7D36EE6A068012826
-:1005A0007FF410AF306840F0010030601BE7217825
-:1005B00048060ED5A06A00283FF43DAFB16841F06F
-:1005C0000101B16000F0DCFA0746B06880077FF5F2
-:1005D0002BAFE06AA0B3A96801F00C010C293FF42D
-:1005E0005FAF0228286820F0807028607FF443AF56
-:1005F00000F0C6FA064600F039F87FF42EAFE9683D
-:10060000DFF88003A26B0140206B0143606B014364
-:10061000E06B41EA02210143206C0143606C01431D
-:10062000E960286840F080702860E96841F08051F6
-:10063000E96000F0A5FA0446286880017FF514AF50
-:100640000020BDE8F0817068400810F0010070479C
-:100650002968606A21F0F001014329606868216A15
-:1006600020F47F4040EA0120686070472868400E0F
-:1006700010F001007047286000F082BA70684008EE
-:100680004000706000F07CBA2DE9F8430400884611
-:1006900044D0DFF8F46200F0C8F847D200F0CDF89B
-:1006A000074600F0C2F841D000F06AFAC01B0228E9
-:1006B000F7D90320B7E000F063FA401B022843D9C2
-:1006C000F7E700F05DFAA0EB090002284CD9F0E74B
-:1006D00000F056FAA0EB0900022854D9E9E700F02F
-:1006E0004FFA401B02285DD9E3E700F049FA401BAE
-:1006F000022867D9DDE700F043FA401B484577D36D
-:10070000D7E7032802D13968890103E00028396856
-:1007100002D1890762D401E049055FD4012082E05B
-:1007200000F02EFAC01B022872D9C2E72078810798
-:100730004FF0B0470BD5B968A06821F0F001014334
-:10074000B96000F01DFA0546B868C003B3D520783B
-:10075000DFF81C5281060AD52968606921F0F00192
-:10076000014300F067F8814628688003A9D5207806
-:1007700041060BD52968A0690909090141EA101150
-:1007800000F058F881462868C003A1D520784107B9
-:100790000BD5B968E06821F4E0610143B96000F06D
-:1007A000EFF90546B868800399D5207801070CD584
-:1007B000B868216920F4605040EAC100B86000F0D8
-:1007C000DFF90546B86840038FD52078C10717D5F3
-:1007D0006068022895D1396889039FD5B96889086E
-:1007E00040EA8100B86041F2893900F0C9F9054654
-:1007F000B868616800F00C00B0EB810F7FF47BAF4C
-:10080000306800F00700804505D200F016F8074672
-:1008100000F00BF884D100F003F900F0D3F9BDE843
-:10082000F24300F08BB9BDE8F283306800F00700B6
-:1008300040457047296000F0A3B93168C90848EA0B
-:10084000C101316000F09CB938B54FF0B044504D53
-:10085000A16811F00C0106D1FFF770FCC0F3031082
-:1008600055F8200032BD04294A4A05D008294A48D3
-:1008700004D12168C90222D5104632BDE16801F0D9
-:100880000301022904D0032904D12168C90207D534
-:10089000104605E0FFF752FCC0F3031055F82000A6
-:1008A000E168E268E368C1F306214843C2F302113C
-:1008B000491C5B0FB0FBF1F05B1CB0FBF3F032BDE9
-:1008C00080B5FFF7C1FF3149FFE7344A0968C1F33A
-:1008D000031152F82110B0FBF1F002BD70B52C49A4
-:1008E000B1282EBFCC6AC0F3031051F82040204835
-:1008F000056800F087F92949294A05F00F0551F8E4
-:100900002510B4FBF1F10024B1FBF2F1B0F5007F4A
-:100910000FF2AC02204609D10FF2880353F82050A1
-:100920008D4214D2401C0328F8D912E00FF2840340
-:1009300053F820508D420AD2401C0328F8D308E017
-:1009400000F01EF9801B03280BD3032070BD52F862
-:1009500020400D4D2868C00844EAC000FFF78BFE18
-:100960000646296801F00701A142E9D1002070BDC7
-:10097000080100584800002090000058FFFFFEEEDC
-:10098000000400588C80C111004000580800005835
-:10099000FC0A00080024F4000048E801BC0A000832
-:1009A00040420F001200000024000000360000004A
-:1009B00040000000060000000C00000010000000D5
-:1009C0000000000001000000020000000300000021
-:1009D0003249002008604FF4E0223148016841F4B8
-:1009E000700101604FF0B041086840F001000860FC
-:1009F0008A602C480A6802402B480A60036823F08A
-:100A000005030360426852085200426000222748F2
-:100A1000C8600861086820F4802008608A61704717
-:100A20004FF0B0410FF2D4000A68C2F3031250F83D
-:100A300022008A6802F00C02042A04D0082A04D09A
-:100A40000C2A04D01CE01A481AE01A4818E0CA68B8
-:100A5000CB68C3F3021302F003025B1C022A08BF37
-:100A6000134802D0032A08BF1248B0FBF3F2C8684B
-:100A7000CB68C0F306205B0F42435B1CB2FBF3F074
-:100A80000D4A0FF23803106088681168C0F3031034
-:100A900053F82000B1FBF0F01060704708ED00E063
-:100AA00088ED00E0FBFEF6FA9400005800100422E6
-:100AB0000024F4000048E8015C0000200100000070
-:100AC000030000000500000001000000010000001C
-:100AD000060000000A0000002000000002000000E4
-:100AE00004000000080000001000000040000000AA
-:100AF000800000000001000000020000A08601004C
-:100B0000400D0300801A060000350C0040420F0023
-:100B100080841E0000093D0000127A000024F400C9
-:100B200000366E010048E801006CDC0200000000A5
-:100B300000000000000000000000000070B50F4E33
-:100B40000446B0680025A8B1FFF7BAFEB2684FF4BA
-:100B50007A71B1FBF2F1B0FBF1F000F0AEF848B9F8
-:100B6000102C07D2002221464FF0FF3000F06EF823
-:100B7000746000E00125284670BD00BF44000020DD
-:100B800001480068704700BF440000200248016827
-:100B900041F480710160704700040058164810B598
-:100BA000016841F480710160032000F042F80020E8
-:100BB000FFF7C4FF0024002814BF012400F0BAF896
-:100BC000204610BD0D48406870470C48806870474B
-:100BD0000B480BE00A48016821F0020101607047F0
-:100BE0000748016821F00401016070470168490865
-:100BF0004900016070470000004000584400002098
-:100C0000042004E0DFF80800006800F4C0607047CA
-:100C1000000400580901020081B002D43C4881540C
-:100C200005E03C4802F00F02104400F8041C01B03B
-:100C30007047394A13684FF6FF0100020B4000F479
-:100C4000E0601843354908431060704738B5324BAF
-:100C50001C68C4F30223C3F10704052C28BF042435
-:100C60001D1D072D34BF0023DB1E012505FA04F4EA
-:100C7000641E2140994005FA03F35B1E1A4011439C
-:100C8000BDE83440C6E7010007D4012200F01F018F
-:100C9000234B8A40400943F82020704701000BD4C1
-:100CA000012200F01F011F4B8A40400943F8202019
-:100CB000BFF34F8FBFF36F8F704710B5401EB0F179
-:100CC000807F01D3012010BD174C60600F214FF0D1
-:100CD000FF30FFF79FFF0022A26007202060002066
-:100CE00010BD010007D4012200F01F010F4B8A4004
-:100CF000400943F820207047010007D4012200F08A
-:100D00001F010B4B8A40400943F820207047000028
-:100D100000E400E018ED00E00CED00E00000FA0552
-:100D200000E100E080E100E010E000E000E200E02F
-:100D300080E200E0134881B0016841F400210160C5
-:100D4000006800F400200090009801B0704710B5D2
-:100D500004460D492068884213D1FFF717FFFFF7BB
-:100D600015FF0A48016821F4407141F48071016067
-:100D7000026842F4004202602046BDE8104000F0E4
-:100D800013B810BD500000580028004090000058D3
-:100D90008A60FF2102685162012180F82110002140
-:100DA00080F820100020704790F82010012901D110
-:100DB00002207047012280F82020022180F82110B3
-:100DC000CA210268516253210368596201688A6826
-:100DD00042F02002FFF7DCBFDFF83C150A6892B250
-:100DE00000E00246086880B28242FAD170472DE9DD
-:100DF000FC4104461825DFF82485DFF824656843A4
-:100E000008EB00073078062808D13178717034700B
-:100E100078754FF0FF307060002039E000F077F80F
-:100E2000B9680918B96008F10803B96832786A43EB
-:100E30009A589142327813D308F1150315FB02FC3E
-:100E400013F80C30062B25D008F108066B43F35835
-:100E5000994222BF08F115036A439A5CEED219E069
-:100E60001146337869439A420BD008F1140308F114
-:100E7000150C5B5C15FB03F50CF805407A753B75AA
-:100E800000E07A7508F114025454317871703470AE
-:100E9000BDE8F6811146694308F115035B5C062B3A
-:100EA00004D008F1140615FB03F574557B753A75EB
-:100EB00008F115025454EBE7F8B5DFF86434DFF8B5
-:100EC0005C541E78182402466243B0422A4404D17E
-:100ED00018785870507D18700FE0167D507D92F88C
-:100EE00015C005F115076643062807F806C004D0AB
-:100EF000167D143514FB00F42E550120107318785C
-:100F0000062802BF00294FF0FF315960F1BD10B52E
-:100F1000DFF80C44606810F1010F0FD0FFF75CFFA1
-:100F20006168DFF80024814261683CBF5388C918BA
-:100F3000081A517848431178C84000E0002080B278
-:100F400010BD2DE9F84FDFF8DC53DFF8DCB3D5F83E
-:100F50000880D8F80000DBF800104A0500F090F98E
-:100F6000DFF8BC63DFF8B4A321F4806181604FF047
-:100F7000180934780AF1080019FB04F14758FFF703
-:100F8000C6FF874217D200270121B170062C3DD041
-:100F900019FB04F40AF108010AF108020959814217
-:100FA00023BF0AF108010959091A002111510AEB5E
-:100FB00004014C7DEAE7A9884118B94202D2AF8802
-:100FC0000021E2E73F1ADFE7022802DA2878012849
-:100FD00000D07F1ED8F80000C1684A07FAD500F09B
-:100FE00055F9DBF80C00000CBFB247EA0047CBF81C
-:100FF0000C70FFF7F1FE7060A8680068816841F42A
-:1010000080618160AFF30080BDE8F18FB8B2002845
-:10101000DAD1FFF7E1FE70600320BDE8F24FFFF781
-:1010200060BE2DE9F843EFF3108872B6BD4DBB4B9F
-:10103000A8680168CA224A6253204862B84A886890
-:1010400020F48060886018201678374647431F4494
-:10105000387B022826D13C68D7F810909078F0B100
-:101060007A7B012A0AD101213046FFF725FF88F358
-:1010700010887968304600F016F904E088F310888B
-:10108000304600F0C1F8A8680068CA2141622246D3
-:10109000532141624846314600F050F90BE0FFF71A
-:1010A00050FF06E0C8684207FCD500F07EF89F4973
-:1010B000086088F31088FF21A86802685162BDE8C3
-:1010C000F183F8B5974CA160CA2209684A6253229D
-:1010D0004A62954A136843F020031360136803F0D3
-:1010E0000703C3F10403237095682D0C05F07F05F9
-:1010F0006D1C6570EDB29268C2F30E02521C6280E4
-:1011000092B2521E6A43A2F5A072DA404FF6FF7304
-:101110009A422CBFA380A280854A136843F400231F
-:101120001360844B1D6845F400251D6048BB7C4856
-:101130007A4E0123837018254FF0FF33436000235C
-:101140005FFA83FC06F10C0715FB0CFC4FF0000E58
-:1011500007F80CE05B1CDFB2062FF1DB06230370FF
-:10116000886820F48060886000F01FF8D060032059
-:10117000FFF7C2FDA1680868826842F4804282607D
-:1011800005E0C868410544BF0320FFF7AAFDA16838
-:101190000A68FF205062002203210320FFF756FD5A
-:1011A000BDE8F2400320FFF76EBDC86800F0800084
-:1011B00060F49060C8604FF400207047F0B50446BA
-:1011C0000025EFF3108672B61827DFF850C10CF136
-:1011D0000C0007FB05FE10F80E0010B16D1C062D6B
-:1011E000F5DB062D0CD06F430CEB070001270773CE
-:1011F00086F310880461427303600D700020F0BD17
-:1012000086F310880120F0BDF8B50746EFF310848F
-:1012100072B60320FFF742FD424DAE683068CA2126
-:1012200041623A4653214162182043494243895C56
-:1012300002291BD100213846FFF73EFE38480178CD
-:1012400006290ED1306838490A68530500F018F8AD
-:1012500021F480618160C1684A07FCD500F016F86E
-:1012600004E04078884218BFFFF76BFEA9680A685F
-:10127000FF2050620320FFF706FD84F31088F1BDC4
-:1012800002D5C1684A07FCD481687047C16801F083
-:10129000800161F49061C1604FF40020234908602F
-:1012A0000320FFF729BD2DE9F04180460F46424655
-:1012B00018201A4942438C18207B022804BF40465C
-:1012C000FFF7A2FFEFF3108572B60320FFF7E6FCED
-:1012D000144EB0680068CA21416253214162022065
-:1012E0002073A76067604046FFF781FD0C490A78CC
-:1012F0004978914202D0FFF724FE02E0A168081A63
-:10130000A060FF20B1680A6850620320FFF7BBFCB1
-:1013100085F31088BDE8F08128280040FC000020FB
-:10132000DC040020A8040020082800400C08005815
-:1013300000080058800800580801002010470000ED
-:1013400038B58EB002A80FF21C41DFF86C43DFF80D
-:101350006C53302200F02EFA0FF2B9300190009455
-:1013600069460FF2993000F069FA0121022000F07D
-:101370004EFBD34A0021042000F0DFFB02A800F05E
-:101380005BFC00F0A0F800F05FFC002085F8900006
-:1013900005F126044FF6FF70208000210FF2453240
-:1013A000012000F0CAFB00F0B1FC00F0D8FC0FF205
-:1013B0002D33002205F191010020FFF7FFFE0220EE
-:1013C000E07080210120A0700D2020710220A0700B
-:1013D000182060710320A070BA480180A0214180CC
-:1013E000012000F024F90FB030BD7CB50646B34DA6
-:1013F0007078052805F1900404D03E280DD0FF2810
-:1014000024D03AE0B088E98C884202D10020E884F8
-:101410002070012000F00BF92FE0F178012908D0AD
-:101420000C292AD1E88C6A460DF1010100F013FD68
-:1014300023E06078FFF7E8FE207804280CBF062040
-:1014400005202070B6F80500E88416E0B6F8030021
-:1014500040F20241401A08D0C01E0BD0001F02BF4C
-:101460000121E88C00F031FF07E0E88C964900F09C
-:101470001CFE02E0E88C00F0D0FE012076BD00F0FA
-:10148000BABE8E48C08C00F05DBE1CB58B4CE08CA3
-:1014900001AA0DF1050100F0DEFC98B99DF80500E8
-:1014A000022804BF9DF80410022903D100200090F7
-:1014B000012302E0002000900223E08C1A46002164
-:1014C00000F024FD13BD78B50FF25C207F4D00883D
-:1014D0007F4E89B0ADF81A0000F088FC286810F142
-:1014E000010F0ED069683074090A020A000CB0744A
-:1014F000727406F1100468683175F074090A717528
-:1015000006E0002000F0FCFE040008BF0FF22424D7
-:1015100022460621002000F005FF6079307210217C
-:1015200020797072E078B072A078F07260783073D1
-:1015300020780FF2082470732246182000F0F2FE83
-:101540000FF2082600F06EF84EF66E50089007AACB
-:101550002868079006212E2000F0E4FE2246102184
-:10156000182000F0DFFE00F05DF81821012000F0E7
-:1015700000FF00F029FF0DF1160006A9019000916F
-:1015800005AB07220021012000F0ACFD0FF29C10FA
-:10159000BDF81810494C00900523BDF81400002236
-:1015A00000F0D2FF0DF11A0000900223BDF81610D2
-:1015B000BDF81400002200F0C7FF02220221002023
-:1015C00000F07CFC0120207000F023FD0120607001
-:1015D0000020E070082060751020A07501202075A3
-:1015E0003C48A0610120A0700020C1B221440871D4
-:1015F000401CC1B21029F8DB002004900023A06930
-:10160000617803900122207D0290A07D0190607D91
-:101610000090A07800F016FDA07808B100F0D0FD91
-:101620000AB070BD32461021082000F07BBE2DE9C3
-:10163000F8420746012F87B003D122480588468823
-:1016400003E04FF4C8654FF47A66DFF8709009F153
-:1016500090046078FFF7D8FD022F05D1207801288B
-:1016600014BF022800F07AFC277000200690059035
-:1016700009F129010491062299F828000FF2DC01F2
-:1016800003900291019200230093324629460020E4
-:1016900000F076FC0E490E2000F06AFD002808BF1D
-:1016A000012F06D160780C4908B0BDE8F042FFF781
-:1016B000FABD08B0BDE8F082A4080320680000204D
-:1016C0007B180008EC04002040E201008075FF1F39
-:1016D0000400002007B2010046E0010000210120C3
-:1016E00000F038BA0220A2E70021042000F032BA4C
-:1016F000012000F051BA012000F056BA10B504469E
-:10170000616801F1080000F0AFFA00B1012020701B
-:1017100010BD000010B1012803D07047072000F071
-:1017200029BA072000F02EBA400300004852535453
-:101730004D0000006C7AD8AC577200001234567815
-:101740009ABCDEF0123456789ABCDEF0FEDCBA09A0
-:1017500087654321FEDCBA09876543210948525356
-:10176000544D0000000000000000000000000000D8
-:1017700000000000000000004400080040050801CF
-:101780003A799C00F4010000FFFFFFFF48010100CF
-:101790000000000062B38B0708D0521E11F8013B15
-:1017A00000F8013B00F024808B07F6D1830740F05E
-:1017B000208000BF103A07D330B4B1E83810103A97
-:1017C000A0E83810F9D230BC530724BFB1E80810A4
-:1017D000A0E8081044BF51F8043B40F8043BD2078E
-:1017E00024BF31F8022B20F8022B44BF0B78037082
-:1017F0007047121F17D35B0009D151F8043B20F842
-:10180000023B1B0C121F20F8023BF6D20BE051F8F2
-:10181000043B00F8013B1B0A20F8023B1B0C121F83
-:1018200000F8013BF3D238BF121D521E24BF11F83D
-:10183000013B00F8013BF8D8704700007FB50C462B
-:101840006D4D61686D4EE8612962284600F0E8FE42
-:10185000246805F1240000F0EDFE746006F1080034
-:1018600000F0E8FE01203070296829B10FF2551010
-:1018700000900294684688477FBD1FB55F4C04F115
-:10188000080000F0DAFE00BB2178F1B1694604F1EE
-:10189000080000F0FBFE5848C16949B10098029069
-:1018A00001228DF8042001A888479DF8040000E07B
-:1018B00001202070207818B1009800F09AFF04E011
-:1018C000009904F1080000F0C1FE04F1080000F0E6
-:1018D000B4FE28B9207818B104F10800FFF704FF1E
-:1018E0001FBD2DE9F8430646002000F05FF874881C
-:1018F0003088B268DFF80081C4F3090444EA802428
-:10190000F068A4B2C1B2204600F03CF8002748F2CB
-:10191000E8094846FFF7EFFE08E06888A04202D1D8
-:10192000316928780870687800B1012708F124002F
-:1019300000F083FEF0B9694608F1240000F0A6FE2D
-:10194000009800F10B05407A0F28E6D0B5F8011099
-:10195000A1420DD10098817AC81E7169C0B2884237
-:10196000C8BF0846706102463069E91CFFF712FFE4
-:101970002878D9E73800CCD0012000F017F80020F3
-:10198000BDE8F28310B513461C4A5468A4F8090058
-:10199000E1720A46194604F10C00FFF7FBFE164AF5
-:1019A0001369BDE810400021002018471249096A58
-:1019B00082B008B921B101E011B1012002B008479D
-:1019C00002B0704710B50146487A0F2818BF0E289C
-:1019D00007D10B4800F044FEBDE810400020FFF79F
-:1019E00087BE064C04F1080000F03AFE04F108003E
-:1019F000BDE81040FFF778BEE40300208804002013
-:101A0000080400201948002101604160704710B5AA
-:101A100000F00CF85C6819B1012904D1204301E001
-:101A200024EA0000586082F3108810BDEFF31082A2
-:101A300072B60E4B704738B5EFF3108472B60B498F
-:101A40000B4D086820B129688847686880470AE01C
-:101A5000486820B1A9688847E868804703E028699A
-:101A600080476869804784F3108831BDB404002042
-:101A7000344000082DE9FC47594CDFF86891A5690E
-:101A80002840A0614FF0010A4FF0FF3830E0491CB8
-:101A900054F831000642FAD004EBC10718407968C7
-:101AA0001040014208BFC7F804807E68304000F053
-:101AB0009BF860620AFA00F086437E60EFF31081C3
-:101AC00072B6626A20690AFA02F2D24310402061BB
-:101AD000022004EBC00353F8086C1640401E43F884
-:101AE000086CF6D181F31088606A59F82010884795
-:101AF00063692069A2691840104207D0E069216A31
-:101B0000084203D1002103EA0206C1E700F0BFFE4C
-:101B1000EFF3108972B6216960690140A069014242
-:101B200001BFE169206A014200F041FF89F310889A
-:101B300000F05AFFA561BDE8F38738B51446EFF30E
-:101B4000108572B600F050F8264941F8204085F320
-:101B5000108831BD10B5EFF3108272B6204B1C69AE
-:101B600004431C6153F83140204343F8310082F3B1
-:101B7000108810BDEFF3108172B6194A536923EA39
-:101B8000000005E0EFF3108172B6154A536918435F
-:101B9000506181F310887047EFF3108172B6104ADC
-:101BA000D3691843D061F4E72DE9F0410C4C626A27
-:101BB000266A2062012101FA02F803E03946404614
-:101BC00000F0F7FE276AE5693D42F7D0404600F095
-:101BD0000BF825EA0707E76126626062BDE8F0813D
-:101BE0001C000020A402002002460020110C090461
-:101BF00004BF1020120412F07F4F04BF08301202FD
-:101C00000FF2180112F0704F04BF001D1201120FE5
-:101C1000C0F11F00895C401A7047000004030202F3
-:101C200001010101000000000000000000F033FF8E
-:101C30009DF80E0005B000BDF8B500F10C026B4632
-:101C400021214FF66640F1E71C4900200877002269
-:101C50001B48027000F036B818490A7F41F822008C
-:101C6000087F401C0877704770B504466078FF28ED
-:101C700002BFB4F8031001F47F41B1F5406F12D1F7
-:101C800000260E4D00E0761C297FF0B288420AD271
-:101C9000F1B255F82110204688470100F3D002D058
-:101CA000022805D006E02046BDE87040FFF79DBB46
-:101CB000002070BD012070BD00000000580400200D
-:101CC000F404002080B500F035FF00F034FF00F090
-:101CD00033FF00F06BFF00F06AFF00F0E7FF01F058
-:101CE0004BF801F04AF801F049F801F048F801F02A
-:101CF00047F801F046F801F045F801F044F801F02A
-:101D000043F8BDE8014001F040B80000E0B505A08F
-:101D1000042100908DF8041042F62920694600F055
-:101D200032FF07BD53544D0010B500782B4C18B14D
-:101D300002280FD004D310BDA0800120207310BD55
-:101D4000607BFFF761FA607BBDE8104040F601015F
-:101D5000FFF7A9BA607BBDE81040FFF755BA10B590
-:101D60000FF2450200210220FFF7E7FE1B4C002185
-:101D7000042021732070214642F6382000F0E1FF54
-:101D80001F20E07204F10D010A20A0800120A07242
-:101D90004FF48060E0800122BDE810400FF245035F
-:101DA0000020FFF70BBA00000D480C490068CA7A02
-:101DB00000F00700413048801307087B04D518B9AC
-:101DC0008888401D888003E0012804BF0020087334
-:101DD000891C42F6372000F0B4BF000078040020D0
-:101DE0002828004000210220FFF7B4BE00B587B0CC
-:101DF00000F010F8012003220690ADF80420ADF8A1
-:101E0000062000F0A5F800284CBFFF209DF8000038
-:101E100007B000BD00208DF800001822002101A8A5
-:101E200000F0BABFADF80600049107A8012108220E
-:101E300003900691ADF804207047092200216846FE
-:101E400000F0AABF1822002102A800F0A5BF1822A6
-:101E500001A800F0A1BF70B5C8B006460C461546F3
-:101E60000522FFF7EBFFADF82060FFF7EBFF302115
-:101E700000F014F80521049000F019F8002848BF7C
-:101E8000FF2009D49DF8000030B99DF803002070B0
-:101E90009DF804002870002048B070BDADF80A100D
-:101EA00008200221ADF80800059108A870470791A5
-:101EB000CDF818D0002102A8FFF713BD00B5C7B0B8
-:101EC00000F00EF8FFF7C3FF312000F013F800F028
-:101ED0003FF800284CBFFF209DF8000047B000BD30
-:101EE00000238DF81C008DF8003007A84170827027
-:101EF00000217047ADF8060007A9032004900822CE
-:101F0000012003910690ADF80420704730B5C7B0AA
-:101F10000025ADF81C008DF81F2007A84A9C817091
-:101F200003718DF80050ADF82140FFF776FF0F21C7
-:101F3000029132200721FFF775FF00F009F8002811
-:101F40004CBFFF209DF8000047B030BD03900691C4
-:101F5000CDF814D0002101A8FFF7C3BC00B587B0AD
-:101F600000F045F900F073F9812000F03BF900F032
-:101F700085F900284CBFFF209DF8000007B000BD88
-:101F80002DE9F84DC7B09446DDF840E1519A559DD2
-:101F9000569EDDF84CA1ADF81D108DF81C004FF0D9
-:101FA000000BADF81FC08DF821308DF822E000F055
-:101FB00024F800F017F824F8095F668000F047F96C
-:101FC0003F20832100F075F9574406910D3704979F
-:101FD00000F057F900284CBFFF209DF8000048B0E2
-:101FE000BDE8F08D88F800A007AC5499E41952467A
-:101FF00008F10100544400F0C9BE8DF823201746B3
-:1020000052998DF800B00DF1240809A8B84400F0E9
-:10201000BDBE00B5C7B000F00CF8852000F0C3F8D5
-:1020200000F02CF900284CBFFF209DF8000047B0BD
-:1020300000BD00218DF81C008DF80010182201A8A9
-:1020400000F0AABE2DE9F841C7B04FF0000800F03B
-:1020500026F80DF12300DDF844E14E9F4F9E509D80
-:10206000529C8DF81F30C0F800E08DF800808DF88C
-:1020700020708DF821608DF822508DF8274000F0F7
-:10208000E6F88620ADF8060007A90C2000F0F2F86B
-:1020900000284CBFFF209DF8000000F024B98DF807
-:1020A0001C0007A841708270704700B5C7B00022BD
-:1020B000ADF81C008DF800200DF11E001822016003
-:1020C00001A8002100F068FE8820ADF8060007A9ED
-:1020D000062000F0CFF800284CBFFF209DF800003C
-:1020E00047B000BDF8B5C8B005460E4617461C46B9
-:1020F00000F023F808A8467087708DF8205000F093
-:10210000D3F88A21ADF80A103F20032100F0BFF870
-:10211000002848BFFF200ED49DF8000058B94F9901
-:102120004E98BDF801202280BDF803200280BDF842
-:1021300005000880002049B0F0BD07220021684654
-:1021400000F02ABE00B5C7B00021ADF81C00FFF7B3
-:1021500073FF0F2102918D20022100F07EF800F024
-:102160008EF800284CBFFF209DF8000047B000BD4E
-:1021700018B5C7B0044600F03AF88DF81C40224666
-:1021800000F09FF800F063F83F208E2100F0AEF8D9
-:10219000641C049400F075F800284CBFFF209DF8E3
-:1021A000000048B010BDADF8060007A901203F228D
-:1021B000039104907047ADF8060007A9022070470C
-:1021C00000B587B000F013F800F041F8922000F05D
-:1021D00009F800F053F800284CBFFF209DF80000DC
-:1021E00007B000BDADF806003F2201207047002077
-:1021F0008DF80000704700B587B0FFF7F8FF00F0DA
-:1022000026F89420FFF7EEFF00F038F800284CBFC6
-:10221000FF209DF8000007B000BD00B5C7B0002149
-:10222000ADF81C00FFF708FF9520FFF7C4FF00F092
-:1022300021F800284CBFFF209DF8000047B000BDEA
-:1022400000228DF80020ADF81C008DF81E10182219
-:10225000002101A800F0A0BD0321ADF80600049103
-:1022600007A801213F22039006917047ADF80600B0
-:1022700007A9032004903F22012003910690ADF8A6
-:102280000420CDF814D0002101A8FFF72ABBADF837
-:102290000800059108A8072104900791CDF818D0EF
-:1022A000002102A8FFF71DBB1822002102A800F0A0
-:1022B00073BDADF80400ADF8061007A80121039026
-:1022C00070470DF11D0000F061BD00B5C7B0FFF70C
-:1022D000B7FFA520FFF7CAFF00284CBFFF209DF8DD
-:1022E000000047B000BD48B0BDE8F081ADF8040083
-:1022F000ADF8061007A80121039006917047000071
-:1023000001460648064AC3798B4218BF904218BF5F
-:102310000838F8D18B4218BF00207047F873FF1FB0
-:102320000070FF1F18B50C46C7B0114600228DF88B
-:1023300000208DF81C008DF81D4022460DF11E0076
-:1023400000F024FD00F02AF83F200C21ADF8040035
-:10235000ADF8061007A8012103900691A41C04946F
-:1023600000F02CF800284CBFFF209DF8000048B07A
-:1023700010BD00B5C7B000F00AF80F2000F013F848
-:1023800000284CBFFF209DF8000047B000BD002290
-:102390008DF800208DF81C008DF81D1018220021EA
-:1023A00001A800F0F9BCADF8060007A902200490CE
-:1023B0003F22012003910690ADF80420CDF814D0FF
-:1023C000002101A8FFF78DBA00B587B000208DF875
-:1023D000000000F0E0F840F20110ADF806003F22E6
-:1023E0000120069000F013F900284CBFFF209DF853
-:1023F000000007B000BD2DE9F84107460128C7B02D
-:10240000884615461E4608BF022003D002280CBF8E
-:10241000102000200DF11D010C1800F036F8012FDE
-:102420008DF81C7002D0022F18D019E002273A460E
-:1024300041460DF11D0000F0A9FC2570667000F00A
-:10244000AAF83F204FF4817100F016F8FF1C0497A2
-:1024500000F0DFF8002805D5FF2009E01027E6E7A7
-:10246000472005E09DF8000010B94E9800F067F88D
-:10247000FFE748B0BDE8F081ADF80400ADF8061004
-:1024800007A80321039006917047032200216846A4
-:1024900000F082BC2DE9F64F0C460546012CC7B072
-:1024A0009B4608BF022003D0022C0CBF1020002046
-:1024B0000DF11F010E18FFF7E8FF012CADF81C50BD
-:1024C0008DF81E4002D0022C2CD02DE00227569C05
-:1024D000559DDDF85091DDF84CA1DDF84881489913
-:1024E0003A4600F054F8A6F800B086F8028086F864
-:1024F00003A086F804907571B47100F04CF83F2089
-:10250000ADF804004FF4827107A8ADF806100390EF
-:1025100003210A370497069100F07BF8002805D5BF
-:10252000FF2009E01027D2E7472005E09DF80000D2
-:1025300010B9579800F003F849B0BDE8F08FBDF826
-:10254000011001800020704730B5C7B01C464A9B7F
-:1025500000F049F800258DF800508DF82140224602
-:1025600019460DF1220000F011FC00F014F83F2094
-:102570004FF4837100F042F8A41D049400F049F870
-:1025800000284CBFFF209DF8000047B030BD0DF182
-:102590001F0000F0FBBB1822002101A800F0FCBBCB
-:1025A00078B5C7B04C9C4D9D00F01DF800268DF805
-:1025B00021308DF800608DF822402246294600F037
-:1025C00019F8FFF7E8FF3F204FF4937100F016F879
-:1025D000E41D049400F01DF800284CBFFF209DF876
-:1025E000000048B070BDADF81C00ADF81E108DF8AD
-:1025F000202070470DF1230000F0C8BBADF80400A7
-:10260000ADF8061007A80121039006917047ADF8B8
-:102610000420CDF814D0002101A8FFF762B9000012
-:102620000249016002490161704700BFED260008C0
-:1026300017270008006040607047EFF3108172B602
-:10264000026882420CBF012000201CE0EFF31082E0
-:1026500072B603680B60486001600868416023E05F
-:10266000EFF3108272B6086043684B6041604868BF
-:10267000016019E0EFF3108172B6436802681A60D6
-:1026800042680068426081F31088704710B5EFF32C
-:10269000108472B602680A600068FFE7FFF7EAFF7D
-:1026A00084F3108810BD086082F310887047000022
-:1026B00000F0F0BB6C486D49016001F120024260FE
-:1026C00001F13002826001F13C02026201F1440238
-:1026D000C26001F14C02026101F16802426101F144
-:1026E0006C0282617831C16100F0E6BB38B5044606
-:1026F0005F4D05F11000FFF79DFF5B494868A16839
-:102700000160E168C160456005F11001816000F081
-:10271000EFFB58482DE080B553494A681368012003
-:10272000187200F0EBFB002002BD38B5514C504D43
-:1027300007E0694605F11000FFF7A8FF009821683F
-:10274000884705F11000FFF778FF0028F1D031BD70
-:1027500048484168084738B50446474D2846FFF7C2
-:1027600069FF4148C068A1680160456000F0CBFB8B
-:1027700042482168016061684160002032BD80B537
-:102780003949CA6813681020187200F0C2FB002093
-:1027900002BD3549CA68394910680B68184738B511
-:1027A000364C354D06E069462846FFF76FFF009826
-:1027B000616888472846FFF740FF0028F3D031BD05
-:1027C00038B504462E4D2846FFF734FF2D48FFF755
-:1027D00031FF25480069A1688160E168C160056139
-:1027E00021680160616841602169416161698161BD
-:1027F00031BD80B501462348FFF732FFBDE80240F6
-:102800000FF2050000F095BB38B5174C1D4D08E0E0
-:1028100069462846FFF73AFF009920690069FFF7EB
-:102820001FFF2846FFF709FF0028F1D031BD10B582
-:10283000154C2046FFF7FEFE0B4841690C60BDE8D1
-:10284000104000F08ABB1CB50F4C06E069462046DC
-:10285000FFF71CFF009800F019F82046FFF7EDFE87
-:102860000028F3D013BD000000000320B0090320AE
-:1028700084080320C40400209C080320CC0400200A
-:10288000340A0320BC0400203C0A03207047704730
-:102890003A4981B00A6802430A600968084000901A
-:1028A000009801B0704710B5354C88B0206840F4EE
-:1028B00000402060FFF7A6F832490020FEF701FC37
-:1028C0006846142100F060FB0020029003214FF4C1
-:1028D0006040009001910120FFF7DAFF69464FF058
-:1028E000904000F055FB606C400840006064182187
-:1028F00000910220FFF7CCFF6946234800F048FB17
-:10290000606C20F002006064FEF762F9FEF762F985
-:10291000FEF766F901210120FFF779F80121002077
-:1029200000F01FFC0121012000F01BFC012102200E
-:1029300000F017FCFFF7BEFE144A00210820FFF745
-:10294000FCF8134C0FF24D01019104F23C50009041
-:1029500069460FF2450000F049F804F25470029005
-:1029600004F5C96140F23C5005900391049402A81B
-:10297000FFF726FFFFF79CFE08B010BD4C00005883
-:102980000800005810040020000400482F2A000806
-:10299000240003207047000080B5FFF748FFFEF7D2
-:1029A000CFFCBDE8044000210120FFF730B8FFF75D
-:1029B00042B84FF0FF30FFF75DB800210820FFF765
-:1029C000C9B80220FFF7E8B80220FFF7EDB80128E8
-:1029D00005D0022805D0102805D1FEF750BDFEF71E
-:1029E00050BDFEF752BD7047704700007FB50C46E2
-:1029F0004D4D61684D4EE8612962284600F000FCAB
-:102A00002468746006F10800FFF714FE012000F04E
-:102A100068F801203070296841B10FF2E9000FF227
-:102A2000ED02009001920294684688477FBD1FB571
-:102A30003E4C04F10800FFF700FE00BB2178F1B125
-:102A4000694604F10800FFF721FE3748C16949B122
-:102A50000098029001228DF8042001A888479DF873
-:102A6000040000E001202070207818B10098FFF7E2
-:102A7000C0FE04E0009904F10800FFF7E7FD04F14F
-:102A80000800FFF7DAFD28B9207818B104F1080032
-:102A9000FFF793FF1FBD2DE9F04105460E46904616
-:102AA0001C46002000F01DF8204F7868A0F809505F
-:102AB000C672324641460C30FEF76CFE1A4A136964
-:102AC00000210020984748F2E800FFF77DFF796871
-:102AD0008A78D21C04F10800FEF75CFEBDE8F041E4
-:102AE00001201CB51049124C096A20B901B1884770
-:102AF0000020207013BD0120207011B1BDE81C40E2
-:102B0000084713BD0020FFF75CBF000010B5014669
-:102B1000064C04F10800FFF7A3FD04F10800BDE82E
-:102B20001040FFF74ABF0000340400209804002042
-:102B3000F50400207047704718B51B4C002020603A
-:102B400087B041F60A00ADF8180000940323012273
-:102B500006A90120FFF74FFC42F629220121ADF81A
-:102B600018200491A01C05900A2200230221039240
-:102B70000293019300912023208806AA0121FFF7E8
-:102B800089FC08B010BD80B542F62922904209D1D7
-:102B90000A680548009200220B7941880088FFF7F7
-:102BA000D3FC02BD002002BDF00400207047704736
-:102BB00038B5024686B050780024FF2839D1B2F8E3
-:102BC00003106B4840F60143C91A1FD0123901BFE8
-:102BD000B2F80710C088401C81422AD1957AB2F819
-:102BE0000500537A0124012D08D10A320192009385
-:102BF00000220023FFF7D4FC002015E00A320192E6
-:102C0000009301228023FFF7CBFC12E04088B2F84A
-:102C10000710801C81420CD1507B0124C10748BFA2
-:102C20008DF8084002D402208DF8080002A8FFF7B2
-:102C30007BF8204607B030BDFEB5014601AA487AB0
-:102C40008DF804004B7A08885070DC0704D508889A
-:102C5000000A9070032300E00223487A040707D596
-:102C60004888D0545B1C4888DCB2000A10555B1CB5
-:102C70004C7AE00610D50D7A00200BE001EB400401
-:102C8000DFB2A688D6555B1CA488DEB2240A945510
-:102C90005B1C401CA842F1DB01A935480091DBB266
-:102CA000418800880022FFF74FFCFEBD18B587B0B1
-:102CB00030482F4CFEF7D0FF41F60D01ADF818104B
-:102CC00000940823012206A90120FFF794FB42F695
-:102CD0003720ADF81800012204920A20A11C0390AD
-:102CE000002310220591029301930092072300F024
-:102CF00023F842F63820ADF8180000220492029220
-:102D000001920A20211D03900222059100F012F881
-:102D100042F63920ADF818000022049201920A20F0
-:102D2000A11D0390022308220591029300F002F8EE
-:102D300008B010BD00920123208806AA0121FFF7E8
-:102D4000A9BB80B5002242F63723C01A09D0401E25
-:102D50000BD107480091012381880088FFF7F4FB1D
-:102D600002E00846FFF768FF0246104602BD000079
-:102D7000D4040020B12B000870477047704770479B
-:102D800070477047704770477047704710B50446EA
-:102D9000FEF700FD204610BD10B5044610460A4659
-:102DA0000146204600F036FA204610BDC0680840B3
-:102DB000884201D10120704700207047C069084057
-:102DC000884201D1012070470020704710B5664C41
-:102DD00002212046FFF7F2FF38B16068C043810747
-:102DE00003D5FFF7DCFC022018E001212046FFF7A5
-:102DF000E5FF38B16068C043C10703D5FFF795FC14
-:102E000001200BE008212046FFF7D8FF38B16068A9
-:102E1000C043010703D5FFF716FD0820A06010BDD1
-:102E200010B5514C00F033F818B96068C043810305
-:102E300006D400F02CF830B96068C043810302D595
-:102E4000BDE810406EE0082100F022F870B960681B
-:102E5000C04301030AD56068444940F40020606023
-:102E6000086880474FF40020A06010BD202100F0CA
-:102E70000FF858B96068C043810207D5606840F414
-:102E800000106060BDE81040FFF762BC10BD022179
-:102E900020468BE73648016841F4007101603548EF
-:102EA000026842F40072026040BF20BF32480168ED
-:102EB00041F400410160704780B53048016841F439
-:102EC00080110160006800F480100090009826488E
-:102ED000016841F001010160026842F48032026041
-:102EE0002C20FDF7D0FEBDE802402D20FDF7CBBE23
-:102EF00023480168490849000160704721494FF49F
-:102F00008030086070471E48016821F002010160AE
-:102F100070471B484FF400314160016821F40031D3
-:102F2000016070471648016841F400310160FFF705
-:102F300030BC38B504460C4D08212846FFF736FF53
-:102F400030B10A480460686820F40020686031BD30
-:102F5000A0474FF40021A96031BD0948016821F064
-:102F60000801016070470000000C0058E4040020D4
-:102F7000D4080058200800580C040058500000588D
-:102F8000040C0058080C0058002200F077B900002B
-:102F90002DE9F84F4FF0000C644A654BDFF894813F
-:102FA0004FF00F0982460F4633E0634DAA4514BF28
-:102FB000072504258D40254348F82E50C1431C6841
-:102FC00001EA040E7C68E50348BF40EA0E0EC3F830
-:102FD00000E05C6801EA040E7C68A50348BF40EA93
-:102FE0000E0EC3F804E0146801EA040E7C68E502E2
-:102FF00048BF40EA0E0EC2F800E0546801EA040E31
-:1030000079688C0248BF40EA0E0EC2F804E00CF169
-:10301000010C396831FA0CF000F07C80012000FAD4
-:103020000CFE1EEA0100F2D07C68022C18BF122CA4
-:103030004FEA8C0110D14FEADC040AEB840401F062
-:103040001C05266A09FA05FB26EA0B06D7F810B01C
-:103050000BFA05F5354325624FEA4C040325DAF8EF
-:10306000006097F804B0A540ED430BF0030B2E4031
-:103070000BFA04FB4BEA0606CAF800607E68012ED4
-:1030800018BF022E03D0112E18BF122E17D1DAF856
-:103090000860D7F80CB02E400BFA04FB4BEA06068A
-:1030A000CAF80860DAF8046026EA0E0E7E68C6F3F5
-:1030B000001606FA0CF646EA0E06CAF80460DAF8BC
-:1030C0000C603540BE6806FA04F42C43CAF80C4084
-:1030D0007C68E4009BD54FEA9C0E58F82E5001F016
-:1030E0000C0109FA01F425EA0404BAF1904F08BF73
-:1030F00000250ED0114DAA4508BF012509D0104D5D
-:10310000AA4508BF022504D00E4DAA457FF44DAF55
-:1031100003254FE7BDE8F18F0B4A136803421CBF3C
-:103120001060FFF754BC7047000000000008005812
-:1031300080080058080001400010004800040048C2
-:1031400000080048000C00480C080058264981B0CF
-:103150000A6802430A60096808400090009801B0BC
-:103160007047F0B585B005460C4668461421FFF758
-:103170000BFF0DB9042004E0012D18BF022D02D170
-:103180000820FFF7E3FF2000184E0FF268070DD16B
-:1031900037F81500009000210191012002900221D2
-:1031A000039100F01BF8012000F08EF9012C13D1DF
-:1031B00037F81500009001210D480190029100F0B0
-:1031C0000DF80FF23800445D00220F2160B2FDF7C8
-:1031D0003DFD60B2FDF757FD05B0F0BD694656F8FC
-:1031E0002500FFF7D5BE00004C000058500000201D
-:1031F0000000211010000100020000000A06070074
-:103200000249016002490161704700BF5727000869
-:103210007F27000862F30F2262F31F42401810F06C
-:10322000030308D0C91A1FD3DB0748BF00F8012DDC
-:1032300028BF20F8022D130030B41446154610396B
-:1032400028BF20E93C00FAD8490728BF20E90C0034
-:1032500048BF40F8042D890028BF20F8022D48BF40
-:1032600000F8012D30BC7047C91818BF00F8012DB7
-:10327000CB0728BF00F8012D7047000000B500BF44
-:10328000130096469446103928BFA0E80C50FAD88F
-:103290005FEA417C28BF0CC048BF40F8042BC90737
-:1032A00028BF20F8022B48BF00F8012B00BD00000A
-:1032B000914900E0914981B00A6802430A600968B7
-:1032C00008400090009801B0704710B5FDF766FC0B
-:1032D0008B4C606840010ED56068C0000BD4FDF7D0
-:1032E00055FCFDF753FC206840F4803020602168D5
-:1032F00021F48031216000F0C6F80020FFF700F8CB
-:1033000040B180797F49E160E16821F47C5141EA74
-:103310000021E16000F047F87B487C4C0168002206
-:103320000260026902F0500202610420FFF7C2FF4E
-:103330000120FFF7BFFF0220FFF7BCFF0420FFF7CB
-:10334000B7FF0120FFF7B4FF0220FFF7B1FF002213
-:103350000F210E20FDF77AFC0E20FDF794FC0022D1
-:103360000F213A20FDF772FC3A20FDF78CFC00217A
-:10337000674841600F218160046047F6FF71C160BA
-:1033800000F0D2F8CA206062FF2153206062A0687A
-:10339000C008C000A0606162FFF785FA4FF0FF30FF
-:1033A000FEF768FBFAE738B5AEB01CA84821FFF776
-:1033B000EBFD01A81C21FFF7E7FD08A85021FFF74E
-:1033C000E3FD4F48534C016821F0180101604FF4B0
-:1033D0008032206820F4C06040F4007020604FF418
-:1033E0008075216801F4C0610091072100981C914B
-:1033F00001201E900021402020901D9227911F95B2
-:103400001CA8FCF7A4FE6F2001900221002002916D
-:1034100003900490059006900790012101A8FDF704
-:1034200033F943F60300089000214FF480401990CF
-:103430000E910F91102002211B901A91189508A847
-:1034400000F02CF9E06920F07000E061324801687A
-:10345000C1F303200090009830B9E169090909011E
-:1034600041F00401E16108E00098E169801E80F309
-:103470000400090940EA0110E061E06940F40040FD
-:10348000E0612FB030BD254881B0016841F4801162
-:1034900001603F21006800F48010009000982048EF
-:1034A00041604161016841F47C110160026942F4AC
-:1034B0007C120261016841F03F010160026942F043
-:1034C0003F02026101B0704738B50446FDF758FB72
-:1034D00014F1010F054609D0FDF777FB041905E04B
-:1034E0001048016821F00401016030BFFDF748FB7E
-:1034F000401BA042F4D331BD480000584C00005896
-:1035000090000058FECAFECA8008005800280040FB
-:1035100010040020000400585875FF1F5000005888
-:10352000040C005810ED00E038B5040044D094F8C5
-:10353000210028B9002184F820102046FDF707FC5F
-:1035400000F049F8FF2510B100F03FF834E02168A1
-:10355000DFF8B0008A6802408A6021688A68636880
-:1035600020690343A06903431A438A602168E06825
-:10357000086120680169A26841EA0241016120688E
-:10358000C16821F08001C1602068C16C8908890090
-:10359000C1642168CA6CE369606903431A43CA6461
-:1035A00020688168880609D400F020F830B12068CE
-:1035B0004562042100F01FF8012032BD20684562F9
-:1035C000012184F82110002032BD206845620421C9
-:1035D00084F821107047022084F82100CA20216855
-:1035E0004862532022685062204626E020460BE0C5
-:1035F0002068C0F8248084F82110002084F820007E
-:1036000070470000BFFF8FFF70B5044640F2E936F7
-:103610002068C16821F0A001C160FDF7B1FA05463C
-:103620002068C168880606D4FDF7AAFA401BB0429C
-:10363000F6D3032070BD002070BD70B5044620682D
-:10364000C1684A0612D44FF0FF32C26040F2E93638
-:10365000FDF796FA05462068C168480606D4FDF7CE
-:103660008FFA401BB042F6D3032070BD002070BD1E
-:10367000DFF820130A68030903F47F2300019A434B
-:1036800000F47F2000F082B9DFF808231368010CF2
-:1036900023EA014343EA0043136070472DE9F843EE
-:1036A000054600242878DFF8EC624106A0464FF07A
-:1036B000B0472DD5286B70B1B0F5800F06D0B0F5AE
-:1036C000000F18BFB0F5400F17D01FE0F86840F4A6
-:1036D0008030F860EDE0386820F080603860FDF7F9
-:1036E0004FFA81463868000140F1D080FDF748FA72
-:1036F000A0EB09000228F5D90324D7E0FDF740FA32
-:10370000A0EB0900022840F2C980F5E70124A04699
-:103710002868010531D5B06800F44078286C8045F0
-:103720002AD0FDF733FAB8F1000FB16805D1286C43
-:1037300021F440710143B1601EE0B06840F4803074
-:10374000B06021F44071B06820F48030B060286C23
-:103750000143B160B068C0070ED5FDF711FA80468D
-:1037600041F28939B068800706D4FDF709FAA0EB69
-:1037700008004845F6D30324A0462878C10705D59C
-:103780003168A869890840EA810131602878810799
-:1037900005D53168E86921F440610143316028783A
-:1037A000C10644BFA86AFFF76FFF2878810644BFAF
-:1037B000E86AFFF769FF2878410744BF286AFFF7E6
-:1037C00057FF2878010744BF686AFFF751FF286850
-:1037D000C1051BD53168686B21F040610143316040
-:1037E000686BB0F1006F00F0BDF8686BB0F1806FEE
-:1037F00075D100F0BDF804463868000160D5FDF7CA
-:10380000BFF9001B0228F7D94FF0030867E0FDF766
-:10381000B7F9001B02285BD9F6E7316821F0404177
-:10382000316020F08050326822F0406210433060F6
-:10383000A86BB0F1C05F00F095F8286841056DD520
-:103840003168E86B21F0405101433160E86BB0F121
-:10385000005F03D1F96841F48031F960E86BB0F1A1
-:10386000805F5BD100F084F804463868000146D5DB
-:10387000FDF786F9001B0228F7D94FF003084DE049
-:10388000FDF77EF9001B022841D9F6E700F061F848
-:10389000A86821F4781100F071F8814638680001B9
-:1038A0007FF52CAF3969686901433961002C7FF4D9
-:1038B0002EAF3168286B21F440010143316027E7C6
-:1038C00000F047F8E86821F0606100F057F804461E
-:1038D000386800019BD539696869014339612868F6
-:1038E0008105AAD5A86BB0F1804F1CBFB0F1004F85
-:1038F000002892D1316821F04041084397E700F059
-:1039000028F8286921F0604100F038F8044638684A
-:103910000001B5D539696869014339612868C10476
-:1039200005D5F168686C21F440410143F1602868D5
-:1039300081040BD5796AE86C21F03001014379628A
-:10394000796AA86C890840EA810179624046BDE83D
-:10395000F2833869696820F4FE4040EA012038614A
-:103960003969704703D1F96841F08071F960704797
-:10397000396821F080613960FDF702B9014339618E
-:10398000386840F080603860FDF7FAB8104308608E
-:103990007047000088000058206881684A06704718
-:1039A000F8B5044640F60F002568E9692A68AB6857
-:1039B00008400DD1880602D5900602D4D80040F107
-:1039C0008980E16E00294FD02046BDE8F4400847C9
-:1039D0006248034204BF624E32427BD0CF0709D512
-:1039E000D60507D501262E62D4F8885045F001058A
-:1039F000C4F888508D070AD5DD0708D5266802254A
-:103A00003562D4F8885045F00405C4F888504D0755
-:103A10000AD5DD0708D5266804253562D4F8885014
-:103A200045F00205C4F888500D070CD5950601D461
-:103A3000034208D0256808202862D4F8880040F0A6
-:103A40000800C4F8880008050BD5500109D5256881
-:103A50004FF400602862D4F8880040F02000C4F8D9
-:103A60008800D4F88800002870D0890607D5900611
-:103A700001D4D80003D5E16E09B120468847D4F8B7
-:103A8000880021688A68510602D410F0280F1AD0E5
-:103A9000204600F069F8FFF77FFF0FD500F057F8D8
-:103AA00060B1DFF8C0108163A06F00F079F80028E2
-:103AB0004CD0A06F816BBDE8F44008472046BDE8BC
-:103AC000F24000F004B9204600F001F90020C4F8EB
-:103AD0008800F1BDC80209D5580207D54FF48010FF
-:103AE00028622046BDE8F24000F0F2B8080609D589
-:103AF000100601D4180205D5216F39B32046BDE860
-:103B0000F440084748060FD550060DD5286820F028
-:103B1000400028602021C4F8801000202067204643
-:103B2000BDE8F24000F0D6B8080206D5500004D532
-:103B30002046BDE8F24000F0DBB8C80148BF002ACB
-:103B400004D52046BDE8F24000F0D3B8F1BD81684D
-:103B500021F040018160A06F70470000010000105B
-:103B6000200100048D3B000801680A6822F490726D
-:103B70000A60DFF82810026893680B4093602021E8
-:103B8000C0F884100021C16670470000806A00F10F
-:103B9000560100220A810A8000F099B8FEFFFFEF6B
-:103BA00038B500F1240200245178022903D0042002
-:103BB0009061012428E001680B6823F00E030B607C
-:103BC00001680D686D086D000D60516A0B6823F483
-:103BD00080730B60012192F82030D56903F01C033B
-:103BE00099406960936AD16A5960116B31B10B6871
-:103BF00023F480730B60536B916B596001215170FA
-:103C00001470516901B18847204632BDF8B500F102
-:103C100024010423CA6914680268156891F82060B9
-:103C200006F01C0603FA06F73C4210D06F070ED5CB
-:103C30001468A50603D4156825F00405156000F086
-:103C40003DF8C968002938D0BDE8F4400847022390
-:103C500003FA06F73C4213D0AF0711D51468A50646
-:103C600005D4156825F00A05156001224A7000F098
-:103C700025F800220A708968F9B1BDE8F4400847C8
-:103C8000082303FA06F6344217D02B0715D513681C
-:103C900023F00E031360012291F82030CC6903F069
-:103CA0001C039A40626001228A614A7000220A70F5
-:103CB000096911B1BDE8F4400847F1BD91F8202031
-:103CC000CC6902F01C0293406360704700007047AB
-:103CD0007047000000680449884204D1034908681D
-:103CE000002818BF0047704700380140E804002052
-:103CF0007047704700EB81003D4AD0F88010914238
-:103D000001D0012070470020704742F4806240F8E3
-:103D10002120704737481F2181610168C908C90007
-:103D200041F0030101603448016841F00401016081
-:103D300030BF7047704710B5304C00F048F800288D
-:103D4000FBD1042100F044F828B92D480068010493
-:103D500003D500F03FF800F057F800220321204679
-:103D6000FFF7D3FF23480168C908C90041F00201E9
-:103D700001602148016841F00401016030BF10BDBD
-:103D800010B51E4C00F026F800F021F80028FBD1F9
-:103D90004FF0B040816801F00C01042911D1016895
-:103DA00041F48031016001688903FCD5816889088C
-:103DB000890041F002018160816801F00C0108294D
-:103DC000FAD12046BDE81040002203219DE70321DF
-:103DD00020468FE700220421204696E780B500F0B8
-:103DE0002DF80548016821F00401016030BF01BDD4
-:103DF000000400800004005810ED00E0001400589A
-:103E00008804005800F022B84FF0B040016841F437
-:103E10008071016001684905FCD5816889088900C5
-:103E200041F001018160416A89088900416281682D
-:103E300001F00C010429FAD1704700000248016822
-:103E400021F002010160704710E000E002480168C3
-:103E500041F002010160704710E000E07047FEE7AA
-:103E6000FEE7FEE7FEE770477047704700F024B8B2
-:103E70000548FFF7CBBE0548FFF792BD0448FFF7A2
-:103E80008FBD0448FFF7C2BE2403002018020020A3
-:103E90008C010020840300201020FFF73DB9012091
-:103EA000FFF73AB90220FFF737B9FDF7BAB8FEF7C6
-:103EB000B7BFFEF78BBF000002490A688868821806
-:103EC0000A6070474400002019E050F8042BD30723
-:103ED00044BFA9F101039A18091F0023042942F8DD
-:103EE000043BF9D25FEA817C134604D54FF0000C05
-:103EF000A2F800C09B1CC90744BF0021197050F8EC
-:103F0000041B0029E1D1704730B50168846842186C
-:103F1000416802EB5103C9070BD54C4409E012F983
-:103F2000011B12F8015B002904F8015B05D5491C4F
-:103F3000F9D19A42F3D10C3030BD491EF1D5F8E7E2
-:103F400010B500F013F802000023DB4300241068D2
-:103F5000984203D011000220ABBE14605068984212
-:103F600003D0111D0220ABBE546010BD0148704744
-:103F7000000000006000002010B5074979441831A6
-:103F8000064C7C44163404E00A68081D1144884736
-:103F90000146A142F8D110BD2C00000050000000E5
-:103FA0004EF68851CEF20001086840F470000860B7
-:103FB000BFF34F8FBFF36F8F4FF00070E1EE100A29
-:103FC0007047000005FFFFFF90040000680000201C
-:103FD0008008000024000320000000002DFFFFFFE8
-:103FE0005C010000480000000400002000F00DF813
-:103FF000002801D0FFF7C0FFAFF300800020AFF32F
-:104000000080FFF762F900F002F80120704700F02D
-:1040100001B800000746384600F002F8FBE7000050
-:1040200080B5FFF78DFF024A11001820ABBEFBE7F9
-:1040300026000200DD3D0008053E0008373D00086F
-:10404000813D0008153D0008353D000801488047C6
-:1040500001480047D10900085D400008AFF3008027
-:10406000FFF79EFFFFF7C2FFFFF7FEBFFFF7FEBFA0
-:10407000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF74
-:10408000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF64
-:10409000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF54
-:1040A000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF44
-:1040B000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF34
-:1040C000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF24
-:1040D000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF14
-:1040E000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF04
-:1040F000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFF4
-:10410000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFE3
-:10411000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFD3
-:10412000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFC3
-:10413000FFF7FEBFFFF7FEBFFFF7FEBF020DFF0157
-:10414000D700F8FFF0000010FD000001FC000E0891
-:104150000048000C0048000C004800093D00F8FF32
-:040000050800405D52
+:10015000F041040051D0207881064FF0B04535D5EC
+:10016000A868E96810F00C0001F0030103D00C2826
+:1001700008BF012943D12868800702D5E06900281B
+:100180003BD0FFF7DBFF616A884207D2084600F0E8
+:10019000BFFB002831D100F07AFA0FE0286820F088
+:1001A000F000014329606968206A21F47F4141EA37
+:1001B00000216960606A00F0ABFBF0B900F04AFC16
+:1001C000DFF8E407006800F0D3FCB0B92078C1077D
+:1001D0000DD5A868E96800F00C00082801F00301BB
+:1001E00003D00C2808BF03292CD12868800340F1D4
+:1001F00041816068002840F03D81012040E2E069D3
+:1002000080B1296841F0010100F02EFB0646286804
+:10021000800700F12C8100F0CDFC801B0328F6D371
+:1002200003202DE228684008400000F03EFA064610
+:10023000286800F028FAC9D000F0BCFC801B032815
+:10024000F6D3EDE76068B0F5803F06D0B0F5A02F9B
+:10025000296807D141F480212960286840F4803062
+:10026000286006E021F4803129602A6822F4802287
+:100270002A60606860B100F09DFC06462868800333
+:1002800000F1F88000F096FC801B6528F6D3C7E7E4
+:1002900000F090FC06462868400C10F0010000F0C9
+:1002A000E98000F087FC801B6528F4D3B8E700F0F4
+:1002B00081FCC01B0328C0F01181B1E7E06878B170
+:1002C000296841F4807100F0CFFA0646286840059D
+:1002D00000F1178100F06EFC801B0328F6D39FE726
+:1002E000286820F4807000F0E0F906462868800A4B
+:1002F00010F0010000F0DC8000F05CFC801B0328A3
+:10030000F4D38DE700F056FCC01B0328C0F00B812E
+:1003100086E740F0010000F0CEF9074670688007DC
+:1003200000F11C8100F046FCC01B0328F6D377E7E0
+:10033000706820F0040000F0BEF907467068C0083D
+:1003400010F0010000F0198100F034FCC01B0428FB
+:10035000F4D365E70528306806D140F0040030602A
+:10036000316841F0010105E040084000306031682B
+:1003700021F004013160A06841F2893768B100F0D2
+:1003800019FC80463068800700F10C8100F012FCF7
+:10039000A0EB0800B842F5D342E700F00BFC804622
+:1003A000306800F070F900F0FD8000F003FCA0EB75
+:1003B0000800B842F4D333E700F0FCFBC01B03286D
+:1003C000C0F0FE802CE7B06840084000B06000F04C
+:1003D000F1FB0746B06800F056F900F0F58000F038
+:1003E000E9FBC01B0328F5D31AE700F0E3FB801BF1
+:1003F0000328C0F01F8113E700F0DCFB001B03287B
+:10040000C0F039810CE7286881010CD4296841F0DB
+:1004100080712960E86840F08050E86000F0CAFB15
+:1004200004462868810100F12A8100F0C3FB001B0B
+:100430000328F6D3F4E60C2931D0286820F0807028
+:100440002860E968DFF8640589088900E960E968DF
+:100450000140E96000F0AEFB04462868810140F1EC
+:100460000E8100F0A7FB001B0328F6D3D8E600F0AE
+:100470000EF9ABE6207881071AD5A868E96800F084
+:100480000C00042801F0030104D00C2808BF022945
+:100490007FF414AF2868400503D5E06800283FF4D6
+:1004A000ACAE6968206921F0FE4141EA00616960F3
+:1004B0002168DFF8FC6411F0180F38D0606900285B
+:1004C0003FF436AFC90670687FF523AF800709D4C3
+:1004D000706840F0010000F0EEF807467068800791
+:1004E0007FF5E5AE706840F0040000F0E4F80746E0
+:1004F000706800070DD400F05DFBC01B0428F7D323
+:100500008EE66868216920F0FE4040EA016068607C
+:10051000CEE77068A16920F4706040EA0120706045
+:1005200000F0C6F8074600F0ADF87FF4EBAE207897
+:10053000410737D5DFF87C743868C10529D400F04D
+:100540003FFB00F037FB80463868C10521D400F03E
+:1005500031FBA0EB08000328F6D361E6706820F0B9
+:10056000040070607068C00810F00100DFD000F077
+:1005700021FBC01B0428F5D352E600F099F807468A
+:1005800000F080F8D3D000F015FBC01B0328F7D390
+:1005900046E6A06801287FF4DDAE306840F0010037
+:1005A0003060E8E6217848060ED5A06A00283FF4BE
+:1005B0000AAFB16841F00101B16000F0FBFA0746F3
+:1005C000B06880077FF5F8AEE06A002857D0A968C8
+:1005D000EA68022801F00C017FF42DAF236B02F0D2
+:1005E0000300984202BF02F07000636B984214D17E
+:1005F000A36BC2F30620984202BF02F47810E36BAB
+:1006000098420AD1236C02F06060984202BF02F067
+:100610006042606C82423FF4F6AE0C293FF4EDADCF
+:10062000286841013FF5E9AD296821F0807100F0AB
+:100630001BF90646286881013FF5D7AEE968DFF867
+:100640007803A26B0140206B0143606B0143E06BB8
+:1006500041EA02210143206C0143606C0143E960DF
+:10066000286840F080702860E96841F08051E960B6
+:1006700000F0A0FA0446286881017FF5BDAE002095
+:10068000BDE8F0817068400810F0010070472968EB
+:10069000606A21F0F001014329606868216A20F452
+:1006A0007F4040EA012068607047286000F082BA0D
+:1006B000706840084000706000F07CBA2DE9F84393
+:1006C0000400884644D0DFF8F46200F0C8F847D24E
+:1006D00000F0CDF8074600F0C2F841D000F06AFA09
+:1006E000C01B0228F7D90320B7E000F063FA401BD3
+:1006F000022843D9F7E700F05DFAA0EB09000228D1
+:100700004CD9F0E700F056FAA0EB0900022854D9C2
+:10071000E9E700F04FFA401B02285DD9E3E700F05B
+:1007200049FA401B022867D9DDE700F043FA401B75
+:10073000484577D3D7E7032802D13968890103E018
+:100740000028396802D1890762D401E049055FD4E5
+:10075000012082E000F02EFAC01B022872D9C2E705
+:10076000207881074FF0B0470BD5B968A06821F019
+:10077000F0010143B96000F01DFA0546B868C003F6
+:10078000B3D52078DFF81C5281060AD52968606944
+:1007900021F0F001014300F067F8814628688003EA
+:1007A000A9D5207841060BD52968A0690909090156
+:1007B00041EA101100F058F881462868C003A1D51D
+:1007C000207841070BD5B968E06821F4E061014366
+:1007D000B96000F0EFF90546B868800399D5207834
+:1007E00001070CD5B868216920F4605040EAC100C7
+:1007F000B86000F0DFF90546B86840038FD520786F
+:10080000C10717D56068022895D1396889039FD53B
+:10081000B968890840EA8100B86041F2893900F07E
+:10082000C9F90546B868616800F00C00B0EB810FAB
+:100830007FF47BAF306800F00700804505D200F000
+:1008400016F8074600F00BF884D100F003F900F029
+:10085000D3F9BDE8F24300F08BB9BDE8F28330680C
+:1008600000F0070040457047296000F0A3B93168E7
+:10087000C90848EAC101316000F09CB938B54FF0B1
+:10088000B044504DA16811F00C0106D1FFF756FCA1
+:10089000C0F3031055F8200032BD04294A4A05D0A0
+:1008A00008294A4804D12168C90222D5104632BD20
+:1008B000E16801F00301022904D0032904D1216871
+:1008C000C90207D5104605E0FFF738FCC0F3031056
+:1008D00055F82000E168E268E368C1F30621484367
+:1008E000C2F30211491C5B0FB0FBF1F05B1CB0FBC3
+:1008F000F3F032BD80B5FFF7C1FF3149FFE7344A5D
+:100900000968C1F3031152F82110B0FBF1F002BDE8
+:1009100070B52C49B1282EBFCC6AC0F3031051F832
+:1009200020402048056800F087F92949294A05F048
+:100930000F0551F82510B4FBF1F10024B1FBF2F1E1
+:10094000B0F5007F0FF2AC02204609D10FF2880308
+:1009500053F820508D4214D2401C0328F8D912E0DD
+:100960000FF2840353F820508D420AD2401C032812
+:10097000F8D308E000F01EF9801B03280BD30320F6
+:1009800070BD52F820400D4D2868C00844EAC000F0
+:10099000FFF78BFE0646296801F00701A142E9D165
+:1009A000002070BD0801005848000020FFFFFEEE47
+:1009B00090000058000400588C80C111004000587D
+:1009C00008000058300B00080024F4000048E8013B
+:1009D000F00A000840420F0012000000240000004E
+:1009E0003600000040000000060000000C0000007F
+:1009F00010000000000000000100000002000000E4
+:100A0000030000003249002008604FF4E022314822
+:100A1000016841F4700101604FF0B041086840F096
+:100A2000010008608A602C480A6802402B480A606E
+:100A3000036823F0050303604268520852004260D5
+:100A400000222748C8600861086820F480200860F8
+:100A50008A6170474FF0B0410FF2D4000A68C2F3C8
+:100A6000031250F822008A6802F00C02042A04D013
+:100A7000082A04D00C2A04D01CE01A481AE01A48AC
+:100A800018E0CA68CB68C3F3021302F003025B1CD0
+:100A9000022A08BF134802D0032A08BF1248B0FB3D
+:100AA000F3F2C868CB68C0F306205B0F42435B1CBF
+:100AB000B2FBF3F00D4A0FF238031060886811683A
+:100AC000C0F3031053F82000B1FBF0F01060704742
+:100AD00008ED00E088ED00E0FBFEF6FA9400005817
+:100AE000001004220024F4000048E8015C0000200B
+:100AF00001000000030000000500000001000000EC
+:100B000001000000060000000A00000020000000B4
+:100B100002000000040000000800000010000000B7
+:100B20004000000080000000000100000002000002
+:100B3000A0860100400D0300801A060000350C005D
+:100B400040420F0080841E0000093D0000127A0020
+:100B50000024F40000366E010048E801006CDC025D
+:100B60000000000000000000000000000000000085
+:100B700070B50F4E0446B0680025A8B1FFF7BAFE65
+:100B8000B2684FF47A71B1FBF2F1B0FBF1F000F012
+:100B9000AEF848B9102C07D2002221464FF0FF30A2
+:100BA00000F06EF8746000E00125284670BD00BFBB
+:100BB0004400002001480068704700BF4400002046
+:100BC0000248016841F480710160704700040058D8
+:100BD000164810B5016841F480710160032000F0EF
+:100BE00042F80020FFF7C4FF0024002814BF0124AE
+:100BF00000F0BAF8204610BD0D48406870470C4818
+:100C0000806870470B480BE00A48016821F0020138
+:100C1000016070470748016821F0040101607047D6
+:100C20000168490849000160704700000040005811
+:100C300044000020042004E0DFF80800006800F40D
+:100C4000C0607047000400580901020081B002D45E
+:100C50003C48815405E03C4802F00F02104400F883
+:100C6000041C01B07047394A13684FF6FF010002B7
+:100C70000B4000F4E06018433549084310607047AA
+:100C800038B5324B1C68C4F30223C3F10704052CAA
+:100C900028BF04241D1D072D34BF0023DB1E0125A2
+:100CA00005FA04F4641E2140994005FA03F35B1E23
+:100CB0001A401143BDE83440C6E7010007D40122C1
+:100CC00000F01F01234B8A40400943F82020704761
+:100CD00001000BD4012200F01F011F4B8A40400984
+:100CE00043F82020BFF34F8FBFF36F8F704710B5CD
+:100CF000401EB0F1807F01D3012010BD174C606011
+:100D00000F214FF0FF30FFF79FFF0022A260072066
+:100D10002060002010BD010007D4012200F01F0157
+:100D20000F4B8A40400943F820207047010007D448
+:100D3000012200F01F010B4B8A40400943F820209C
+:100D40007047000000E400E018ED00E00CED00E06A
+:100D50000000FA0500E100E080E100E010E000E0C2
+:100D600000E200E080E200E0184881B0016841F450
+:100D700000210160006800F400200090009801B09C
+:100D800070471CB504461249206888421CD1FFF701
+:100D900017FFFFF715FF0F48816B21F4407141F4F5
+:100DA00080718163816B41F400418163026842F488
+:100DB00080620260006800F4806000900098204625
+:100DC000BDE8164000F014B813BD000050000058F4
+:100DD00000280040580000588A60FF2102685162D4
+:100DE000012180F82110002180F820100020704798
+:100DF00090F82010012901D102207047012280F8CB
+:100E00002020022180F82110CA210268516253215A
+:100E10000368596201688A6842F02002FFF7DCBF6C
+:100E2000DFF83C150A6892B200E00246086880B21A
+:100E30008242FAD170472DE9FC4104461825DFF8BB
+:100E40002485DFF82465684308EB0007307806281E
+:100E500008D131787170347078754FF0FF30706060
+:100E6000002039E000F077F8B9680918B96008F196
+:100E70000803B96832786A439A589142327813D39A
+:100E800008F1150315FB02FC13F80C30062B25D0D6
+:100E900008F108066B43F358994222BF08F1150385
+:100EA0006A439A5CEED219E01146337869439A425C
+:100EB0000BD008F1140308F1150C5B5C15FB03F56E
+:100EC0000CF805407A753B7500E07A7508F114025C
+:100ED0005454317871703470BDE8F681114669431D
+:100EE00008F115035B5C062B04D008F1140615FB12
+:100EF00003F574557B753A7508F115025454EBE708
+:100F0000F8B5DFF86434DFF85C541E781824024624
+:100F10006243B0422A4404D118785870507D18704A
+:100F20000FE0167D507D92F815C005F11507664358
+:100F3000062807F806C004D0167D143514FB00F40B
+:100F40002E55012010731878062802BF00294FF093
+:100F5000FF315960F1BD10B5DFF80C44606810F145
+:100F6000010F0FD0FFF75CFF6168DFF800248142BA
+:100F700061683CBF5388C918081A517848431178F2
+:100F8000C84000E0002080B210BD2DE9F84FDFF826
+:100F9000DC53DFF8DCB3D5F80880D8F80000DBF8C4
+:100FA00000104A0500F090F9DFF8BC63DFF8B4A345
+:100FB00021F4806181604FF0180934780AF108004B
+:100FC00019FB04F14758FFF7C6FF874217D20027E5
+:100FD0000121B170062C3DD019FB04F40AF108017F
+:100FE0000AF108020959814223BF0AF1080109598F
+:100FF000091A002111510AEB04014C7DEAE7A98886
+:101000004118B94202D2AF880021E2E73F1ADFE778
+:10101000022802DA2878012800D07F1ED8F80000C4
+:10102000C1684A07FAD500F055F9DBF80C00000C4E
+:10103000BFB247EA0047CBF80C70FFF7F1FE7060D3
+:10104000A8680068816841F480618160AFF3008026
+:10105000BDE8F18FB8B20028DAD1FFF7E1FE706089
+:101060000320BDE8F24FFFF756BE2DE9F843EFF33A
+:10107000108872B6BD4DBB4BA8680168CA224A628F
+:1010800053204862B84A886820F48060886018203D
+:101090001678374647431F44387B022826D13C68E0
+:1010A000D7F810909078F0B17A7B012A0AD101210B
+:1010B0003046FFF725FF88F310887968304600F046
+:1010C00016F904E088F31088304600F0C1F8A868EB
+:1010D0000068CA2141622246532141624846314696
+:1010E00000F050F90BE0FFF750FF06E0C868420738
+:1010F000FCD500F07EF89F49086088F31088FF2136
+:10110000A86802685162BDE8F183F8B5974CA16008
+:10111000CA2209684A6253224A62954A136843F018
+:1011200020031360136803F00703C3F10403237063
+:1011300095682D0C05F07F056D1C6570EDB2926809
+:10114000C2F30E02521C628092B2521E6A43A2F592
+:10115000A072DA404FF6FF739A422CBFA380A280A0
+:10116000854A136843F400231360844B1D6845F4DB
+:1011700000251D6048BB7C487A4E012383701825EA
+:101180004FF0FF33436000235FFA83FC06F10C0746
+:1011900015FB0CFC4FF0000E07F80CE05B1CDFB2F7
+:1011A000062FF1DB06230370886820F480608860D6
+:1011B00000F01FF8D0600320FFF7B8FDA1680868B1
+:1011C000826842F48042826005E0C868410544BFFD
+:1011D0000320FFF7A0FDA1680A68FF2050620022EB
+:1011E00003210320FFF74CFDBDE8F2400320FFF789
+:1011F00064BDC86800F0800060F49060C8604FF47F
+:1012000000207047F0B504460025EFF3108672B653
+:101210001827DFF850C10CF10C0007FB05FE10F891
+:101220000E0010B16D1C062DF5DB062D0CD06F43A2
+:101230000CEB07000127077386F3108804614273E3
+:1012400003600D700020F0BD86F310880120F0BD12
+:10125000F8B50746EFF3108472B60320FFF738FDA8
+:10126000424DAE683068CA2141623A46532141621C
+:10127000182043494243895C02291BD1002138468A
+:10128000FFF73EFE3848017806290ED1306838490C
+:101290000A68530500F018F821F480618160C16884
+:1012A0004A07FCD500F016F804E04078884218BFE1
+:1012B000FFF76BFEA9680A68FF2050620320FFF762
+:1012C000FCFC84F31088F1BD02D5C1684A07FCD448
+:1012D00081687047C16801F0800161F49061C1606C
+:1012E0004FF40020234908600320FFF71FBD2DE9BC
+:1012F000F04180460F46424618201A4942438C1856
+:10130000207B022804BF4046FFF7A2FFEFF31085C1
+:1013100072B60320FFF7DCFC144EB0680068CA21E7
+:1013200041625321416202202073A76067604046FA
+:10133000FFF781FD0C490A784978914202D0FFF706
+:1013400024FE02E0A168081AA060FF20B1680A68C4
+:1013500050620320FFF7B1FC85F31088BDE8F081EF
+:1013600028280040FC000020DC040020A804002005
+:10137000082800400C080058000800588008005851
+:10138000080100201047000038B58EB002A80FF207
+:101390001C41DFF86C43DFF86C53302200F02EFA6A
+:1013A0000FF2B9300190009469460FF2993000F0C5
+:1013B00069FA0121022000F04EFBD34A00210420EB
+:1013C00000F0DFFB02A800F05BFC00F0A0F800F0EA
+:1013D00067FC002085F8900005F126044FF6FF70A9
+:1013E000208000210FF24532012000F0CAFB00F0FE
+:1013F000B9FC00F0E0FC0FF22D33002205F1910161
+:101400000020FFF7FFFE0220E07080210120A07085
+:101410000D2020710220A070182060710320A070A0
+:10142000BA480180A0214180012000F023F90FB0CB
+:1014300030BD7CB50646B34D7078052805F19004A3
+:1014400004D03E280DD0FF2824D03AE0B088E98CA3
+:10145000884202D10020E8842070012000F00AF9BF
+:101460002FE0F178012908D00C292AD1E88C6A46AE
+:101470000DF1010100F01BFD23E06078FFF7E8FEAD
+:10148000207804280CBF062005202070B6F805003F
+:10149000E88416E0B6F8030040F20241401A08D092
+:1014A000C01E0BD0001F02BF0121E88C00F039FFE5
+:1014B00007E0E88C964900F024FE02E0E88C00F09A
+:1014C000D8FE012076BD00F0C2BE8E48C08C00F070
+:1014D00065BE1CB58B4CE08C01AA0DF1050100F036
+:1014E000E6FC98B99DF80500022804BF9DF8041099
+:1014F000022903D100200090012302E00020009087
+:101500000223E08C1A46002100F02CFD13BD78B5B3
+:101510000FF25C207F4D00887F4E89B0ADF81A0035
+:1015200000F090FC286810F1010F0ED0696830744B
+:10153000090A020A000CB074727406F1100468689B
+:101540003175F074090A717506E0002000F004FF9F
+:10155000040008BF0FF2242422460621002000F0D8
+:101560000DFF60793072102120797072E078B072CE
+:10157000A078F0726078307320780FF208247073CE
+:101580002246182000F0FAFE0FF2082600F06DF84F
+:101590004EF66E50089007AA2868079006212E2064
+:1015A00000F0ECFE22461021182000F0E7FE00F0CB
+:1015B0005CF81821012000F008FF00F031FF0DF168
+:1015C000160006A90190009105AB07220021012019
+:1015D00000F0B4FD0FF29C10BDF81810494C0090BB
+:1015E0000523BDF81400002200F0DAFF0DF11A0007
+:1015F00000900223BDF81610BDF81400002200F080
+:10160000CFFF02220221002000F084FC0120207084
+:1016100000F02BFD012060700020E0700820607554
+:101620001020A075002020753C48A0610020A0700B
+:10163000C1B221440871401CC1B21029F8DB00205E
+:1016400004900023A069617803900122207D02901C
+:10165000A07D0190607D0090A07800F01FFDA07833
+:1016600008B100F0D9FD0AB070BD32461021082043
+:1016700000F084BE2DE9F8420746012F87B003D160
+:1016800022480588468803E04FF4C8654FF47A661F
+:10169000DFF8709009F190046078FFF7D9FD022F10
+:1016A00005D12078012814BF022800F083FC2770A0
+:1016B00000200690059009F129010491062299F86D
+:1016C00028000FF2E00103900291019200230093A1
+:1016D00032462946002000F07FFC0F490E2000F022
+:1016E00073FD002808BF012F06D160780C4908B0AF
+:1016F000BDE8F042FFF7FBBD08B0BDE8F082000096
+:10170000AC08032068000020C3180008EC04002087
+:1017100040E201008075FF1F0400002007B20100B5
+:1017200046E001000021012000F038BA0220A1E7C4
+:101730000021042000F032BA012000F051BA01204B
+:1017400000F056BA10B50446616801F1080000F0D7
+:10175000B7FA00B10120207010BD000010B10128BF
+:1017600003D07047072000F029BA072000F02EBAF6
+:1017700040030000485253544D0000006C7AD8AC2E
+:1017800057720000123456789ABCDEF01234567844
+:101790009ABCDEF0FEDCBA0987654321FEDCBA099B
+:1017A0008765432109485253544D00000000000052
+:1017B0000000000000000000000000000000000029
+:1017C00044000800400508013A799C00F40100003B
+:1017D000FFFFFFFF480101000000000062B38B071C
+:1017E00008D0521E11F8013B00F8013B00F02480A4
+:1017F0008B07F6D1830740F0208000BF103A07D353
+:1018000030B4B1E83810103AA0E83810F9D230BC42
+:10181000530724BFB1E80810A0E8081044BF51F8EE
+:10182000043B40F8043BD20724BF31F8022B20F8D8
+:10183000022B44BF0B7803707047121F17D35B0055
+:1018400009D151F8043B20F8023B1B0C121F20F871
+:10185000023BF6D20BE051F8043B00F8013B1B0AB7
+:1018600020F8023B1B0C121F00F8013BF3D238BFDB
+:10187000121D521E24BF11F8013B00F8013BF8D89D
+:10188000704700007FB50C466D4D61686D4EE86194
+:101890002962284600F0F0FE246805F1240000F0DB
+:1018A000F5FE746006F1080000F0F0FE01203070D3
+:1018B000296829B10FF255100090029468468847B4
+:1018C0007FBD1FB55F4C04F1080000F0E2FE00BBD5
+:1018D0002178F1B1694604F1080000F003FF58488F
+:1018E000C16949B10098029001228DF8042001A835
+:1018F00088479DF8040000E001202070207818B18E
+:10190000009800F0A2FF04E0009904F1080000F044
+:10191000C9FE04F1080000F0BCFE28B9207818B117
+:1019200004F10800FFF704FF1FBD2DE9F843064648
+:10193000002000F05FF874883088B268DFF800811A
+:10194000C4F3090444EA8024F068A4B2C1B220467A
+:1019500000F03CF8002748F2E8094846FFF7EFFEA0
+:1019600008E06888A04202D1316928780870687858
+:1019700000B1012708F1240000F08BFEF0B96946A0
+:1019800008F1240000F0AEFE009800F10B05407A4B
+:101990000F28E6D0B5F80110A1420DD10098817A48
+:1019A000C81E7169C0B28842C8BF0846706102464D
+:1019B0003069E91CFFF712FF2878D9E73800CCD04E
+:1019C000012000F017F80020BDE8F28310B513469F
+:1019D0001C4A5468A4F80900E1720A46194604F149
+:1019E0000C00FFF7FBFE164A1369BDE8104000210A
+:1019F000002018471249096A82B008B921B101E0F4
+:101A000011B1012002B0084702B0704710B501467D
+:101A1000487A0F2818BF0E2807D10B4800F04CFE5B
+:101A2000BDE810400020FFF787BE064C04F1080017
+:101A300000F042FE04F10800BDE81040FFF778BE58
+:101A4000E403002088040020080400201948002135
+:101A500001604160704710B500F00CF85C6819B186
+:101A6000012904D1204301E024EA0000586082F3F8
+:101A7000108810BDEFF3108272B60E4B704738B568
+:101A8000EFF3108472B60B490B4D086820B129683A
+:101A90008847686880470AE0486820B1A968884795
+:101AA000E868804703E0286980476869804784F3D5
+:101AB000108831BDB4040020F04200082DE9FC4735
+:101AC000594CDFF86891A5692840A0614FF0010AE0
+:101AD0004FF0FF3830E0491C54F831000642FAD08C
+:101AE00004EBC107184079681040014208BFC7F8ED
+:101AF00004807E68304000F09BF860620AFA00F0D3
+:101B000086437E60EFF3108172B6626A20690AFA3A
+:101B100002F2D24310402061022004EBC00353F8CC
+:101B2000086C1640401E43F8086CF6D181F310880B
+:101B3000606A59F82010884763692069A2691840D3
+:101B4000104207D0E069216A084203D1002103EA6C
+:101B50000206C1E700F0C7FEEFF3108972B62169F3
+:101B600060690140A069014201BFE169206A014248
+:101B700000F013FF89F3108800F02CFFA561BDE889
+:101B8000F38738B51446EFF3108572B600F050F8BD
+:101B9000264941F8204085F3108831BD10B5EFF398
+:101BA000108272B6204B1C6904431C6153F831400B
+:101BB000204343F8310082F3108810BDEFF3108109
+:101BC00072B6194A536923EA000005E0EFF3108169
+:101BD00072B6154A53691843506181F310887047F3
+:101BE000EFF3108172B6104AD3691843D061F4E75D
+:101BF0002DE9F0410C4C626A266A2062012101FA4B
+:101C000002F803E03946404600F0C9FE276AE5695C
+:101C10003D42F7D0404600F00BF825EA0707E761A0
+:101C200026626062BDE8F0811C000020A402002052
+:101C300002460020110C090404BF1020120412F007
+:101C40007F4F04BF083012020FF2180112F0704FDC
+:101C500004BF001D1201120FC0F11F00895C401A61
+:101C600070470000040302020101010100000000AE
+:101C70000000000000F005FF9DF80E0005B000BD5B
+:101C8000F8B500F10C026B4621214FF66640F1E7F2
+:101C9000F8B500F10C026B460F214FF66840E9E7FA
+:101CA0001C490020087700221B48027000F036B85B
+:101CB00018490A7F41F82200087F401C08777047C6
+:101CC00070B504466078FF2802BFB4F8031001F431
+:101CD0007F41B1F5406F12D100260E4D00E0761C19
+:101CE000297FF0B288420AD2F1B255F8211020467D
+:101CF00088470100F3D002D0022805D006E0204634
+:101D0000BDE87040FFF795BB002070BD012070BD9D
+:101D10000000000058040020F404002080B500F00A
+:101D2000FFFE00F0FEFE00F0FDFE00F035FF00F0CB
+:101D300034FF00F0B1FF01F015F801F014F801F0E4
+:101D400013F801F012F801F011F801F010F801F0A9
+:101D50000FF801F00EF801F00DF8BDE8014001F0B8
+:101D60000AB80000E0B505A0042100908DF8041029
+:101D700042F62920694600F0FCFE07BD53544D0091
+:101D800010B500782B4C18B102280FD004D310BD29
+:101D9000A0800120207310BD607BFFF759FA607BA3
+:101DA000BDE8104040F60101FFF7A1BA607BBDE835
+:101DB0001040FFF74DBA10B50FF245020021022086
+:101DC000FFF7DFFE1B4C0021042021732070214609
+:101DD00042F6382000F0ABFF1F20E07204F10D0145
+:101DE0000A20A0800120A0724FF48060E0800122D0
+:101DF000BDE810400FF245030020FFF703BA0000D2
+:101E00000D480C490068CA7A00F00700413048804C
+:101E10001307087B04D518B98888401D888003E023
+:101E2000012804BF00200873891C42F6372000F007
+:101E30007EBF0000780400202828004000210220F6
+:101E4000FFF7ACBE00B587B000F010F80120032208
+:101E50000690ADF80420ADF8062000F0A5F80028A3
+:101E60004CBFFF209DF8000007B000BD00208DF89A
+:101E700000001822002101A800F084BFADF8060080
+:101E8000049107A80121082203900691ADF80420CF
+:101E9000704709220021684600F074BF1822002113
+:101EA00002A800F06FBF182201A800F06BBF70B548
+:101EB000C8B006460C4615460522FFF7EBFFADF805
+:101EC0002060FFF7EBFF302100F014F805210490AB
+:101ED00000F019F8002848BFFF2009D49DF8000041
+:101EE00030B99DF8030020709DF804002870002090
+:101EF00048B070BDADF80A1008200221ADF8080006
+:101F0000059108A870470791CDF818D0002102A8C4
+:101F1000FFF70BBD00B5C7B000F00EF8FFF7C3FF29
+:101F2000312000F013F800F03FF800284CBFFF20EC
+:101F30009DF8000047B000BD00238DF81C008DF80F
+:101F4000003007A84170827000217047ADF806008C
+:101F500007A9032004900822012003910690ADF800
+:101F60000420704730B5C7B00025ADF81C008DF8CF
+:101F70001F2007A84A9C817003718DF80050ADF8AE
+:101F80002140FFF776FF0F21029132200721FFF752
+:101F900075FF00F009F800284CBFFF209DF80000F5
+:101FA00047B030BD03900691CDF814D0002101A8B0
+:101FB000FFF7BBBC00B587B000F045F900F073F93E
+:101FC000812000F03BF900F085F900284CBFFF208C
+:101FD0009DF8000007B000BD2DE9F84DC7B094464C
+:101FE000DDF840E1519A559D569EDDF84CA1ADF8C3
+:101FF0001D108DF81C004FF0000BADF81FC08DF8C0
+:1020000021308DF822E000F024F800F017F824F8D1
+:10201000095F668000F047F93F20832100F075F9E1
+:10202000574406910D37049700F057F900284CBF2C
+:10203000FF209DF8000048B0BDE8F08D88F800A0B2
+:1020400007AC5499E419524608F10100544400F0D9
+:1020500093BE8DF82320174652998DF800B00DF1EC
+:10206000240809A8B84400F087BE00B5C7B000F046
+:102070000CF8852000F0C3F800F02CF900284CBFC4
+:10208000FF209DF8000047B000BD00218DF81C0026
+:102090008DF80010182201A800F074BE2DE9F84157
+:1020A000C7B04FF0000800F026F80DF12300DDF86E
+:1020B00044E14E9F4F9E509D529C8DF81F30C0F8BA
+:1020C00000E08DF800808DF820708DF821608DF88B
+:1020D00022508DF8274000F0E6F88620ADF8060083
+:1020E00007A90C2000F0F2F800284CBFFF209DF853
+:1020F000000000F024B98DF81C0007A84170827020
+:10210000704700B5C7B00022ADF81C008DF8002064
+:102110000DF11E001822016001A8002100F032FE1E
+:102120008820ADF8060007A9062000F0CFF80028A7
+:102130004CBFFF209DF8000047B000BDF8B5C8B007
+:1021400005460E4617461C4600F023F808A84670C0
+:1021500087708DF8205000F0D3F88A21ADF80A106E
+:102160003F20032100F0BFF8002848BFFF200ED415
+:102170009DF8000058B94F994E98BDF80120228073
+:10218000BDF803200280BDF805000880002049B09A
+:10219000F0BD07220021684600F0F4BD00B5C7B0CD
+:1021A0000021ADF81C00FFF773FF0F2102918D2075
+:1021B000022100F07EF800F08EF800284CBFFF20CE
+:1021C0009DF8000047B000BD18B5C7B0044600F048
+:1021D0003AF88DF81C40224600F09FF800F063F8B2
+:1021E0003F208E2100F0AEF8641C049400F075F8D6
+:1021F00000284CBFFF209DF8000048B010BDADF88E
+:10220000060007A901203F22039104907047ADF812
+:10221000060007A90220704700B587B000F013F848
+:1022200000F041F8922000F009F800F053F800287F
+:102230004CBFFF209DF8000007B000BDADF80600C0
+:102240003F220120704700208DF80000704700B544
+:1022500087B0FFF7F8FF00F026F89420FFF7EEFFB5
+:1022600000F038F800284CBFFF209DF8000007B0B0
+:1022700000BD00B5C7B00021ADF81C00FFF708FF96
+:102280009520FFF7C4FF00F021F800284CBFFF2085
+:102290009DF8000047B000BD00228DF80020ADF889
+:1022A0001C008DF81E101822002101A800F06ABD44
+:1022B0000321ADF80600049107A801213F220390F5
+:1022C00006917047ADF8060007A9032004903F224D
+:1022D000012003910690ADF80420CDF814D0002120
+:1022E00001A8FFF722BBADF80800059108A8072157
+:1022F00004900791CDF818D0002102A8FFF715BB74
+:102300001822002102A800F03DBDADF80400ADF890
+:10231000061007A80121039070470DF11D0000F081
+:102320002BBD00B5C7B0FFF7B7FFA520FFF7CAFF69
+:1023300000284CBFFF209DF8000047B000BD48B00A
+:10234000BDE8F081ADF80400ADF8061007A8012142
+:10235000039006917047000001460648064AC3797B
+:102360008B4218BF904218BF0838F8D18B4218BF73
+:1023700000207047F873FF1F0070FF1F18B50C4650
+:10238000C7B0114600228DF800208DF81C008DF892
+:102390001D4022460DF11E0000F0EEFC00F02AF870
+:1023A0003F200C21ADF80400ADF8061007A801216C
+:1023B00003900691A41C049400F02CF800284CBF54
+:1023C000FF209DF8000048B010BD00B5C7B000F078
+:1023D0000AF80F2000F013F800284CBFFF209DF8EA
+:1023E000000047B000BD00228DF800208DF81C00D1
+:1023F0008DF81D101822002101A800F0C3BCADF813
+:10240000060007A9022004903F22012003910690B4
+:10241000ADF80420CDF814D0002101A8FFF785BA4B
+:1024200000B587B000208DF8000000F0E0F840F221
+:102430000110ADF806003F220120069000F013F9CC
+:1024400000284CBFFF209DF8000007B000BD2DE91B
+:10245000F84107460128C7B0884615461E4608BF02
+:10246000022003D002280CBF102000200DF11D0116
+:102470000C1800F036F8012F8DF81C7002D0022FD6
+:1024800018D019E002273A4641460DF11D0000F030
+:1024900073FC2570667000F0AAF83F204FF481713C
+:1024A00000F016F8FF1C049700F0DFF8002805D5AF
+:1024B000FF2009E01027E6E7472005E09DF800002F
+:1024C00010B94E9800F067F8FFE748B0BDE8F0811A
+:1024D000ADF80400ADF8061007A80321039006919B
+:1024E000704703220021684600F04CBC2DE9F64FEE
+:1024F0000C460546012CC7B09B4608BF022003D0FE
+:10250000022C0CBF102000200DF11F010E18FFF748
+:10251000E8FF012CADF81C508DF81E4002D0022CB3
+:102520002CD02DE00227569C559DDDF85091DDF80A
+:102530004CA1DDF8488148993A4600F054F8A6F8D5
+:1025400000B086F8028086F803A086F804907571C2
+:10255000B47100F04CF83F20ADF804004FF48271E4
+:1025600007A8ADF80610039003210A3704970691D7
+:1025700000F07BF8002805D5FF2009E01027D2E7FE
+:10258000472005E09DF8000010B9579800F003F8C7
+:1025900049B0BDE8F08FBDF8011001800020704700
+:1025A00030B5C7B01C464A9B00F049F800258DF8AD
+:1025B00000508DF82140224619460DF1220000F00E
+:1025C000DBFB00F014F83F204FF4837100F042F879
+:1025D000A41D049400F049F800284CBFFF209DF88A
+:1025E000000047B030BD0DF11F0000F0C5BB182240
+:1025F000002101A800F0C6BB78B5C7B04C9C4D9D2A
+:1026000000F01DF800268DF821308DF800608DF85F
+:1026100022402246294600F019F8FFF7E8FF3F2044
+:102620004FF4937100F016F8E41D049400F01DF8C7
+:1026300000284CBFFF209DF8000048B070BDADF8E9
+:102640001C00ADF81E108DF8202070470DF12300FE
+:1026500000F092BBADF80400ADF8061007A8012108
+:10266000039006917047ADF80420CDF814D00021F6
+:1026700001A8FFF75AB9000002490160024901614F
+:10268000704700BF452700086F27000800604060C2
+:102690007047EFF3108172B6026882420CBF0120CE
+:1026A00000201CE0EFF3108272B603680B604860F4
+:1026B00001600868416023E0EFF3108272B60860A1
+:1026C00043684B6041604868016019E0EFF3108196
+:1026D00072B6436802681A6042680068426081F31B
+:1026E0001088704710B5EFF3108472B602680A6064
+:1026F0000068FFE7FFF7EAFF84F3108810BD086069
+:1027000082F310887047000000F0BABB6C486D4936
+:10271000016001F12002426001F13002826001F1AA
+:102720003C02026201F14402C26001F14C0202610A
+:1027300001F16802426101F16C0282617831C1618C
+:1027400000F0B0BB38B504465F4D05F11000FFF74F
+:102750009DFF5B494868A1680160E168C160456010
+:1027600005F11001816000F0B9FB58482DE080B5FB
+:1027700053494A6813680120187200F0B5FB002025
+:1027800002BD38B5514C504D07E0694605F11000C7
+:10279000FFF7A8FF00982168884705F11000FFF7B0
+:1027A00078FF0028F1D031BD48484168084738B566
+:1027B0000446474D2846FFF769FF4148C068A168B5
+:1027C0000160456000F095FB424821680160616846
+:1027D0004160002032BD80B53949CA6813681020B5
+:1027E000187200F08CFB002002BD3549CA683949D7
+:1027F00010680B68184738B5364C354D06E0694609
+:102800002846FFF76FFF0098616888472846FFF762
+:1028100040FF0028F3D031BD38B504462E4D284680
+:10282000FFF734FF2D48FFF731FF25480069A16805
+:102830008160E168C1600561216801606168416093
+:10284000216941616169816131BD80B501462348DB
+:10285000FFF732FFBDE802400FF2050000F05FBB5A
+:1028600038B5174C1D4D08E069462846FFF73AFF7A
+:10287000009920690069FFF71FFF2846FFF709FF4D
+:102880000028F1D031BD10B5154C2046FFF7FEFEF3
+:102890000B4841690C60BDE8104000F054BB1CB50A
+:1028A0000F4C06E069462046FFF71CFF009800F039
+:1028B00019F82046FFF7EDFE0028F3D013BD000005
+:1028C00000000320B80903208C080320C404002062
+:1028D000A4080320CC0400203C0A0320BC040020F0
+:1028E000440A03207047704710B52148214C88B036
+:1028F000016841F400410160FFF7A8F81E4900207B
+:10290000FEF703FC00F043FB01210120FFF7A3F8D1
+:102910000121002000F08BFC0121012000F087FC48
+:102920000121022000F083FCFFF7F0FE134A002192
+:102930000820FFF726F904F23C500FF24501009001
+:10294000019169460FF23D0000F046F804F2547020
+:10295000029004F5C96140F23C5005900391049443
+:1029600002A8FFF759FFFFF7CFFE08B010BD000027
+:10297000080000582C000320100400201B2A000827
+:102980007047000080B500F030FBFEF7FDFCBDE8AD
+:10299000044000210120FFF75EB8FFF770B84FF048
+:1029A000FF30FFF78BB800210820FFF7F7B80220AF
+:1029B000FFF716B90220FFF71BB9012805D002283E
+:1029C00005D0102805D1FEF77EBDFEF77EBDFEF7CF
+:1029D00080BD7047704700007FB50C464D4D616863
+:1029E0004D4EE8612962284600F070FC246874604E
+:1029F00006F10800FFF74AFE012000F068F8012008
+:102A00003070296841B10FF2E9000FF2ED02009039
+:102A100001920294684688477FBD1FB53E4C04F181
+:102A20000800FFF736FE00BB2178F1B1694604F1DA
+:102A30000800FFF757FE3748C16949B10098029076
+:102A400001228DF8042001A888479DF8040000E0C9
+:102A500001202070207818B10098FFF7F6FE04E0FE
+:102A6000009904F10800FFF71DFE04F10800FFF7CC
+:102A700010FE28B9207818B104F10800FFF793FF81
+:102A80001FBD2DE9F04105460E4690461C4600202C
+:102A900000F01DF8204F7868A0F80950C672324641
+:102AA00041460C30FEF79AFE1A4A136900210020B5
+:102AB000984748F2E800FFF77DFF79688A78D21CD2
+:102AC00004F10800FEF78AFEBDE8F04101201CB5C4
+:102AD0001049124C096A20B901B1884700202070C2
+:102AE00013BD0120207011B1BDE81C40084713BD83
+:102AF0000020FFF75CBF000010B50146064C04F152
+:102B00000800FFF7D9FD04F10800BDE81040FFF709
+:102B10004ABF00003404002098040020F50400207F
+:102B20007047704718B51B4C0020206087B041F6F5
+:102B30000A00ADF8180000940323012206A9012021
+:102B4000FFF785FC42F629220121ADF818200491F7
+:102B5000A01C05900A2200230221039202930193F4
+:102B600000912023208806AA0121FFF7BFFC08B0AE
+:102B700010BD80B542F62922904209D10A68054865
+:102B8000009200220B7941880088FFF709FD02BD01
+:102B9000002002BDF00400207047704738B502469F
+:102BA00086B050780024FF2839D1B2F803106B4862
+:102BB00040F60143C91A1FD0123901BFB2F80710FD
+:102BC000C088401C81422AD1957AB2F80500537A18
+:102BD0000124012D08D10A32019200930022002322
+:102BE000FFF70AFD002015E00A320192009301224E
+:102BF0008023FFF701FD12E04088B2F80710801C27
+:102C000081420CD1507B0124C10748BF8DF8084098
+:102C100002D402208DF8080002A8FFF7B1F8204680
+:102C200007B030BDFEB5014601AA487A8DF8040010
+:102C30004B7A08885070DC0704D50888000A907029
+:102C4000032300E00223487A040707D54888D054BC
+:102C50005B1C4888DCB2000A10555B1C4C7AE0060D
+:102C600010D50D7A00200BE001EB4004DFB2A688FE
+:102C7000D6555B1CA488DEB2240A94555B1C401C0C
+:102C8000A842F1DB01A935480091DBB241880088F8
+:102C90000022FFF785FCFEBD18B587B030482F4CE9
+:102CA000FFF706F841F60D01ADF81810009408235F
+:102CB000012206A90120FFF7CAFB42F63720ADF832
+:102CC0001800012204920A20A11C03900023102264
+:102CD0000591029301930092072300F023F842F636
+:102CE0003820ADF8180000220492029201920A20C6
+:102CF000211D03900222059100F012F842F63920BE
+:102D0000ADF818000022049201920A20A11D039040
+:102D1000022308220591029300F002F808B010BDCA
+:102D200000920123208806AA0121FFF7DFBB80B5AE
+:102D3000002242F63723C01A09D0401E0BD10748A3
+:102D40000091012381880088FFF72AFC02E00846F1
+:102D5000FFF768FF0246104602BD0000D4040020C1
+:102D60009D2B000870477047704770477047704749
+:102D7000704770477047704710B50446FEF72EFD48
+:102D8000204610BD10B5044610460A4601462046AE
+:102D900000F0A6FA204610BDC0680840884201D164
+:102DA0000120704700207047C0690840884201D167
+:102DB000012070470020704710B5664C0221204664
+:102DC000FFF7F2FF38B16068C043810703D5FFF712
+:102DD00012FD022018E001212046FFF7E5FF38B17F
+:102DE0006068C043C10703D5FFF7CBFC01200BE0AF
+:102DF00008212046FFF7D8FF38B16068C0430107BB
+:102E000003D5FFF74CFD0820A06010BD10B5514C54
+:102E100000F033F818B96068C043810306D400F0AD
+:102E20002CF830B96068C043810302D5BDE810407A
+:102E30006EE0082100F022F870B96068C043010319
+:102E40000AD56068444940F4002060600868804703
+:102E50004FF40020A06010BD202100F00FF858B9F9
+:102E60006068C043810207D5606840F4001060606C
+:102E7000BDE81040FFF798BC10BD022120468BE74B
+:102E80003648016841F4007101603548026842F437
+:102E90000072026040BF20BF3248016841F4004127
+:102EA0000160704780B53048016841F480110160CD
+:102EB000006800F48010009000982648016841F0F6
+:102EC00001010160026842F4803202602C20FDF7AB
+:102ED000F4FEBDE802402D20FDF7EFBE2348016857
+:102EE000490849000160704721494FF4803008606B
+:102EF00070471E48016821F00201016070471B48BD
+:102F00004FF400314160016821F4003101607047E5
+:102F10001648016841F400310160FFF766BC38B51E
+:102F200004460C4D08212846FFF736FF30B10A4809
+:102F30000460686820F40020686031BDA0474FF449
+:102F40000021A96031BD0948016821F00801016034
+:102F500070470000000C0058E4040020D40800581A
+:102F6000200800580C04005850000058040C005869
+:102F7000080C0058564900E0564981B00A680243DF
+:102F80000A60096808400090009801B0704718B5C1
+:102F900085B06846142100F0D7F9032001904FF462
+:102FA00060410024009102940120FFF7E3FF00F04C
+:102FB00097F8474C20684008400020601821009195
+:102FC0000220FFF7D7FF6946434800F0C1F92068A7
+:102FD00020F002002060FDF715FEFDF715FEFDF75D
+:102FE00019FE00F011F806B010BD00B587B06846B4
+:102FF0000FF208211C22FEF701FCFFF744FC684693
+:10300000FEF746FE07B000BDF0B585B06846142156
+:1030100000F09AF900260025002400210FF2CC00D0
+:1030200000EBC102907988B11368B3F1904F08D0DA
+:10303000294FBB4208D0294FBB4204BF90880443AC
+:1030400004E09088064301E090880543491C22294A
+:10305000E4DB002002900121032003900191B0B233
+:1030600070B100900120FFF785FF0120FFF784FF7A
+:1030700000F036F80022B1B24FF0904000F02CFA88
+:10308000A8B280B100900220FFF774FF0220FFF782
+:1030900073FF114E6946304600F05AF90022A9B27A
+:1030A000304600F019FAA0B280B100900420FFF77A
+:1030B00061FF0420FFF760FF084D6946284600F0D5
+:1030C00047F90022A1B2284600F006FA05B0F0BD8B
+:1030D0004C0000584C01005800040048000800480B
+:1030E00069464FF0904000F033B9000000000048FE
+:1030F000010000000000004801000000000000483E
+:10310000010000000000004801000000000000482D
+:10311000010000000000004801000000000000481D
+:10312000010000000000004801000000000000480D
+:1031300001000000000000480100000000000048FD
+:1031400001000000000000480100000000000048ED
+:1031500001000000000000480100000000000048DD
+:1031600001000000000000480100000000000048CD
+:1031700001000000000000480100000000000048BD
+:1031800001000000000000480100000000000048AD
+:10319000010000000000004801000000000000489D
+:1031A000010000000000004801000000000000488D
+:1031B000010000000000004801000000000000487D
+:1031C000010000000000004801000000000000486D
+:1031D000010000000000004801000000000000485D
+:1031E000010000000000004801000000000000484D
+:1031F0000100000000000048010000000000000085
+:103200000000000000000000EC3000082400032053
+:103210002800032022040400264981B00A680243E2
+:103220000A60096808400090009801B07047F0B546
+:1032300085B005460C466846142100F085F80DB9A6
+:10324000042004E0012D18BF022D02D10820FFF751
+:10325000E3FF2000184E0FF268070DD137F8150074
+:10326000009000210191012002900221039100F0C1
+:103270001BF8012000F05EFA012C13D137F815007D
+:10328000009001210D480190029100F00DF80FF21D
+:103290003800445D00220F2160B2FDF7F1FC60B2FE
+:1032A000FDF70BFD05B0F0BD694656F8250000F0AE
+:1032B0004FB800004C0000585000002000002110C2
+:1032C00010000100020000000A0607000249016028
+:1032D00002490161704700BFAF270008D7270008E7
+:1032E00062F30F2262F31F42401810F0030308D06C
+:1032F000C91A1FD3DB0748BF00F8012D28BF20F8EB
+:10330000022D130030B414461546103928BF20E9A9
+:103310003C00FAD8490728BF20E90C0048BF40F814
+:10332000042D890028BF20F8022D48BF00F8012D88
+:1033300030BC7047C91818BF00F8012DCB0728BF53
+:1033400000F8012D70470000002200F023BA0000B1
+:103350002DE9F84F4FF0000C674A684BDFF8A08169
+:103360004FF00F0982460F4633E0664DAA4514BF61
+:10337000072504258D40254348F82E50C1431C687D
+:1033800001EA040E7C68E50348BF40EA0E0EC3F86C
+:1033900000E05C6801EA040E7C68A50348BF40EACF
+:1033A0000E0EC3F804E0146801EA040E7C68E5021E
+:1033B00048BF40EA0E0EC2F800E0546801EA040E6D
+:1033C00079688C0248BF40EA0E0EC2F804E00CF1A6
+:1033D000010C396831FA0CF000F07C80012000FA11
+:1033E0000CFE1EEA0100F2D07C68022C18BF122CE1
+:1033F0004FEA8C0110D14FEADC040AEB840401F09F
+:103400001C05266A09FA05FB26EA0B06D7F810B058
+:103410000BFA05F5354325624FEA4C040325DAF82B
+:10342000006097F804B0A540ED430BF0030B2E406D
+:103430000BFA04FB4BEA0606CAF800607E68012E10
+:1034400018BF022E03D0112E18BF122E17D1DAF892
+:103450000860D7F80CB02E400BFA04FB4BEA0606C6
+:10346000CAF80860DAF8046026EA0E0E7E68C6F331
+:10347000001606FA0CF646EA0E06CAF80460DAF8F8
+:103480000C603540BE6806FA04F42C43CAF80C40C0
+:103490007C68E4009BD54FEA9C0E58F82E5001F052
+:1034A0000C0109FA01F425EA0404BAF1904F08BFAF
+:1034B00000250ED0144DAA4508BF012509D0134D93
+:1034C000AA4508BF022504D0114DAA457FF44DAF8F
+:1034D00003254FE7BDE8F18F81B0002A14BF816159
+:1034E000816201B070470B4A136803421CBF106031
+:1034F000FFF763BA704700000008005880080058C2
+:10350000080001400010004800040048000800487E
+:10351000000C00480C080058924900E0924981B024
+:103520000A6802430A60096808400090009801B0E8
+:10353000704710B5FDF74CFB8C4C606840010ED510
+:103540006068C0000BD4FDF73BFBFDF739FB20683A
+:1035500040F480302060216821F48031216000F047
+:10356000C8F80020FEF7F8FE40B180798049E1609C
+:10357000E16821F47C5141EA0021E16000F047F864
+:103580007C487D4C016800220260026902F0500212
+:1035900002610420FFF7C2FF0120FFF7BFFF0220F6
+:1035A000FFF7BCFF0420FFF7B7FF0120FFF7B4FFD0
+:1035B0000220FFF7B1FF00220F210E20FDF760FB74
+:1035C0000E20FDF77AFB00220F213A20FDF758FB71
+:1035D0003A20FDF772FB0021684841600F218160AD
+:1035E000046047F6FF71C16000F0EEF8CA20606227
+:1035F000FF2153206062A068C008C000A060616223
+:10360000FFF772F94FF0FF30FEF758FAFAE738B5D6
+:10361000AEB01CA84821FFF797FE01A81C21FFF7B8
+:1036200093FE08A85021FFF78FFEFDF7C9FA4F4817
+:10363000534C016821F0180101604FF4803220687A
+:1036400020F4C06040F4007020604FF48075216861
+:1036500001F4C0610091072100981C9101201E9087
+:103660000021402020901D9227911F951CA8FCF757
+:103670006EFD6F20019002210020029103900490C2
+:10368000059006900790012101A8FDF717F843F671
+:103690000300089000214FF4804019900E910F9183
+:1036A000102002211B901A91189508A800F046F9E5
+:1036B000E06920F07000E06132480168C1F3032046
+:1036C0000090009830B9E1690909090141F004014D
+:1036D000E16108E00098E169801E80F304000909B7
+:1036E00040EA0110E061E06940F40040E0612FB081
+:1036F00030BD254881B0016841F4801101603F214F
+:10370000006800F4801000900098204841604161FA
+:10371000016841F47C110160026942F47C1202618B
+:10372000016841F03F010160026942F03F0202611D
+:1037300001B0704738B50446FDF73CFA14F1010FAB
+:10374000054609D0FDF75BFA041905E01048016849
+:1037500021F00401016030BFFDF72CFA401BA042AC
+:10376000F4D331BD480000584C0000589000005878
+:10377000FECAFECA8008005800280040100400203D
+:10378000000400585875FF1F50000058040C0058E2
+:1037900010ED00E000B500BF1300964694461039C6
+:1037A00028BFA0E80C50FAD85FEA417C28BF0CC0C3
+:1037B00048BF40F8042BC90728BF20F8022B48BF98
+:1037C00000F8012B00BD000038B5040044D094F887
+:1037D000210028B9002184F820102046FDF7D1FAF5
+:1037E00000F049F8FF2510B100F03FF834E02168FF
+:1037F000DFF8B0008A6802408A6021688A686368DE
+:1038000020690343A06903431A438A602168E06882
+:10381000086120680169A26841EA024101612068EB
+:10382000C16821F08001C1602068C16C89088900ED
+:10383000C1642168CA6CE369606903431A43CA64BE
+:1038400020688168880609D400F020F830B120682B
+:103850004562042100F01FF8012032BD2068456256
+:10386000012184F82110002032BD20684562042126
+:1038700084F821107047022084F82100CA202168B2
+:103880004862532022685062204626E020460BE022
+:103890002068C0F8248084F82110002084F82000DB
+:1038A00070470000BFFF8FFF70B5044640F2E93655
+:1038B0002068C16821F0A001C160FDF77BF90546D1
+:1038C0002068C168880606D4FDF774F9401BB04231
+:1038D000F6D3032070BD002070BD70B5044620688B
+:1038E000C1684A0612D44FF0FF32C26040F2E93696
+:1038F000FDF760F905462068C168480606D4FDF763
+:1039000059F9401BB042F6D3032070BD002070BDB2
+:10391000DFF820130A68030903F47F2300019A43A8
+:1039200000F47F2000F082B9DFF808231368010C4F
+:1039300023EA014343EA0043136070472DE9F8434B
+:10394000054600242878DFF8EC624106A0464FF0D7
+:10395000B0472DD5286B70B1B0F5800F06D0B0F50B
+:10396000000F18BFB0F5400F17D01FE0F86840F403
+:103970008030F860EDE0386820F080603860FDF756
+:1039800019F981463868000140F1D080FDF712F93D
+:10399000A0EB09000228F5D90324D7E0FDF70AF9C6
+:1039A000A0EB0900022840F2C980F5E70124A046F7
+:1039B0002868010531D5B06800F44078286C80454E
+:1039C0002AD0FDF7FDF8B8F1000FB16805D1286CD9
+:1039D00021F440710143B1601EE0B06840F48030D2
+:1039E000B06021F44071B06820F48030B060286C81
+:1039F0000143B160B068C0070ED5FDF7DBF8804623
+:103A000041F28939B068800706D4FDF7D3F8A0EBFE
+:103A100008004845F6D30324A0462878C10705D5F9
+:103A20003168A869890840EA8101316028788107F6
+:103A300005D53168E86921F4406101433160287897
+:103A4000C10644BFA86AFFF76FFF2878810644BF0C
+:103A5000E86AFFF769FF2878410744BF286AFFF743
+:103A600057FF2878010744BF686AFFF751FF2868AD
+:103A7000C1051BD53168686B21F04061014331609D
+:103A8000686BB0F1006F00F0BDF8686BB0F1806F4B
+:103A900075D100F0BDF804463868000160D5FDF727
+:103AA00089F8001B0228F7D94FF0030867E0FDF7FB
+:103AB00081F8001B02285BD9F6E7316821F040410C
+:103AC000316020F08050326822F040621043306054
+:103AD000A86BB0F1C05F00F095F8286841056DD57E
+:103AE0003168E86B21F0405101433160E86BB0F17F
+:103AF000005F03D1F96841F48031F960E86BB0F1FF
+:103B0000805F5BD100F084F804463868000146D538
+:103B1000FDF750F8001B0228F7D94FF003084DE0DD
+:103B2000FDF748F8001B022841D9F6E700F061F8DC
+:103B3000A86821F4781100F071F881463868000116
+:103B40007FF52CAF3969686901433961002C7FF436
+:103B50002EAF3168286B21F440010143316027E723
+:103B600000F047F8E86821F0606100F057F804467B
+:103B7000386800019BD53969686901433961286853
+:103B80008105AAD5A86BB0F1804F1CBFB0F1004FE2
+:103B9000002892D1316821F04041084397E700F0B6
+:103BA00028F8286921F0604100F038F804463868A8
+:103BB0000001B5D539696869014339612868C104D4
+:103BC00005D5F168686C21F440410143F160286833
+:103BD00081040BD5796AE86C21F0300101437962E8
+:103BE000796AA86C890840EA810179624046BDE89B
+:103BF000F2833869696820F4FE4040EA01203861A8
+:103C00003969704703D1F96841F08071F9607047F4
+:103C1000396821F080613960FCF7CCBF014339611C
+:103C2000386840F080603860FCF7C4BF104308601B
+:103C30007047000088000058206881684A06704775
+:103C4000F8B5044640F60F002568E9692A68AB68B4
+:103C500008400DD1880602D5900602D4D80040F164
+:103C60008980E16E00294FD02046BDE8F440084726
+:103C70006248034204BF624E32427BD0CF0709D56F
+:103C8000D60507D501262E62D4F8885045F00105E7
+:103C9000C4F888508D070AD5DD0708D526680225A7
+:103CA0003562D4F8885045F00405C4F888504D07B3
+:103CB0000AD5DD0708D5266804253562D4F8885072
+:103CC00045F00205C4F888500D070CD5950601D4BF
+:103CD000034208D0256808202862D4F8880040F004
+:103CE0000800C4F8880008050BD5500109D52568DF
+:103CF0004FF400602862D4F8880040F02000C4F837
+:103D00008800D4F88800002870D0890607D590066E
+:103D100001D4D80003D5E16E09B120468847D4F814
+:103D2000880021688A68510602D410F0280F1AD042
+:103D3000204600F069F8FFF77FFF0FD500F057F835
+:103D400060B1DFF8C0108163A06F00F079F800283F
+:103D50004CD0A06F816BBDE8F44008472046BDE819
+:103D6000F24000F004B9204600F001F90020C4F848
+:103D70008800F1BDC80209D5580207D54FF480105C
+:103D800028622046BDE8F24000F0F2B8080609D5E6
+:103D9000100601D4180205D5216F39B32046BDE8BD
+:103DA000F440084748060FD550060DD5286820F086
+:103DB000400028602021C4F88010002020672046A1
+:103DC000BDE8F24000F0D6B8080206D5500004D590
+:103DD0002046BDE8F24000F0DBB8C80148BF002A29
+:103DE00004D52046BDE8F24000F0D3B8F1BD8168AB
+:103DF00021F040018160A06F7047000001000010B9
+:103E0000200100042D3E000801680A6822F4907227
+:103E10000A60DFF82810026893680B409360202145
+:103E2000C0F884100021C16670470000806A00F16C
+:103E3000560100220A810A8000F099B8FEFFFFEFC8
+:103E400038B500F1240200245178022903D004205F
+:103E50009061012428E001680B6823F00E030B60D9
+:103E600001680D686D086D000D60516A0B6823F4E0
+:103E700080730B60012192F82030D56903F01C0398
+:103E800099406960936AD16A5960116B31B10B68CE
+:103E900023F480730B60536B916B59600121517057
+:103EA0001470516901B18847204632BDF8B500F160
+:103EB00024010423CA6914680268156891F8206017
+:103EC00006F01C0603FA06F73C4210D06F070ED529
+:103ED0001468A50603D4156825F00405156000F0E4
+:103EE0003DF8C968002938D0BDE8F44008470223EE
+:103EF00003FA06F73C4213D0AF0711D51468A506A4
+:103F000005D4156825F00A05156001224A7000F0F5
+:103F100025F800220A708968F9B1BDE8F440084725
+:103F2000082303FA06F6344217D02B0715D5136879
+:103F300023F00E031360012291F82030CC6903F0C6
+:103F40001C039A40626001228A614A7000220A7052
+:103F5000096911B1BDE8F4400847F1BD91F820208E
+:103F6000CC6902F01C029340636070470000704708
+:103F70007047000000680449884204D1034908687A
+:103F8000002818BF0047704700380140E8040020AF
+:103F90007047704700EB8100404AD0F88010914292
+:103FA00001D0012070470020704742F4806240F841
+:103FB0002120704780B500F097F839481F218161B2
+:103FC0000168C908C90041F0030100F026F861E06A
+:103FD00000F092B810B500F087F8324C00F04CF8C1
+:103FE0000028FBD1042100F048F828B92E480068C9
+:103FF000010403D500F043F800F05CF8002203212F
+:1040000000F03FF826480168C908C90041F00201E4
+:1040100000F003F8016030BF10BD01602348016863
+:1040200041F00401704710B51E4C00F028F800F074
+:1040300023F80028FBD14FF0B040816801F00C015B
+:10404000042911D1016841F48031016001688903BC
+:10405000FCD581688908890041F00201816081688E
+:1040600001F00C010829FAD10022032100F009F81F
+:10407000BDE8104000F040B8032120468AE7002246
+:104080000421204691E780B500F02EF8074801682A
+:1040900021F00401016030BF01BD00000004008078
+:1040A00000040058001400588804005810ED00E087
+:1040B00000F022B84FF0B040016841F48071016017
+:1040C00001684905FCD581688908890041F0010132
+:1040D0008160416A890889004162816801F00C01B0
+:1040E0000429FAD1704700000248016821F002015A
+:1040F0000160704710E000E00248016841F00201F1
+:104100000160704710E000E07047FEE7FEE7FEE761
+:10411000FEE770477047704700F024B80548FFF786
+:10412000C5BE0548FFF78CBD0448FFF789BD0448AC
+:10413000FFF7BCBE24030020180200208C010020E1
+:10414000840300201020FFF7CEB90120FFF7CBB980
+:104150000220FFF7C8B9FCF788BFFEF757BEFEF78D
+:104160002BBE000002490A68886882180A607047FE
+:104170004400002019E050F8042BD30744BFA9F1F4
+:1041800001039A18091F0023042942F8043BF9D2BD
+:104190005FEA817C134604D54FF0000CA2F800C002
+:1041A0009B1CC90744BF0021197050F8041B00294B
+:1041B000E1D1704730B5016884684218416802EB6C
+:1041C0005103C9070BD54C4409E012F9011B12F841
+:1041D000015B002904F8015B05D5491CF9D19A421D
+:1041E000F3D10C3030BD491EF1D5F8E710B500F021
+:1041F00013F802000023DB4300241068984203D028
+:1042000011000220ABBE14605068984203D0111D0B
+:104210000220ABBE546010BD014870470000000092
+:104220006000002010B5074979441831064C7C44E1
+:10423000163404E00A68081D114488470146A1426B
+:10424000F8D110BD2C000000600000004EF688512F
+:10425000CEF20001086840F470000860BFF34F8F91
+:10426000BFF36F8F4FF00070E1EE100A704700004F
+:1042700005FFFFFF90040000680000208008000098
+:104280002C000320000000002DFFFFFF6C01000048
+:1042900048000000040000201DFFFFFF8001000017
+:1042A000040000002400032000F00DF8002801D0D5
+:1042B000FFF7B8FFAFF300800020AFF30080FFF7F7
+:1042C00038F900F002F80120704700F001B8000052
+:1042D0000746384600F002F8FBE7000080B5FFF71C
+:1042E00085FF024A11001820ABBEFBE72600020042
+:1042F00087400008B1400008D53F0008274000086B
+:10430000B53F0008D13F00080148804701480047F9
+:10431000050A000819430008AFF30080FFF796FF75
+:10432000FFF7C2FFFFF7FEBFFFF7FEBFFFF7FEBFBD
+:10433000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFB1
+:10434000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFA1
+:10435000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF91
+:10436000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF81
+:10437000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF71
+:10438000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF61
+:10439000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF51
+:1043A000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF41
+:1043B000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF31
+:1043C000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF21
+:1043D000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF11
+:1043E000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF01
+:1043F000FFF7FEBFFFF7FEBF020DFF01D700F8FF7A
+:10440000F0000010FD000001FC000E080048000C48
+:0E4410000048000C004800093D00F8FFF800CD
+:040000050800431993
 :00000001FF
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/app_common.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/app_common.h
index 4defc5d7a..836f40dcf 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/app_common.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/app_common.h
@@ -1,12 +1,13 @@
+/* USER CODE BEGIN Header */
 /**
  ******************************************************************************
   * File Name          : app_common.h
   * Description        : App Common application configuration file for STM32WPAN Middleware.
   *
- ******************************************************************************
+  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
@@ -16,7 +17,7 @@
   *
   ******************************************************************************
   */
-
+/* USER CODE END Header */
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef APP_COMMON_H
 #define APP_COMMON_H
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/app_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/app_conf.h
index 5a91eccae..fb847cd88 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/app_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/app_conf.h
@@ -1,12 +1,12 @@
+/* USER CODE BEGIN Header */
 /**
  ******************************************************************************
   * File Name          : app_conf.h
   * Description        : Application configuration file for STM32WPAN Middleware.
-  *
- ******************************************************************************
+  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
@@ -16,6 +16,7 @@
   *
   ******************************************************************************
   */
+/* USER CODE END Header */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef APP_CONF_H
@@ -48,11 +49,11 @@
 /**
  * Define IO Authentication
  */
-#define CFG_BONDING_MODE                  (1)
-#define CFG_FIXED_PIN                     (111111)
-#define CFG_USED_FIXED_PIN                (0)
-#define CFG_ENCRYPTION_KEY_SIZE_MAX       (16)
-#define CFG_ENCRYPTION_KEY_SIZE_MIN       (8)
+#define CFG_BONDING_MODE                 (0)
+#define CFG_FIXED_PIN                    (111111)
+#define CFG_USED_FIXED_PIN               (0)
+#define CFG_ENCRYPTION_KEY_SIZE_MAX      (16)
+#define CFG_ENCRYPTION_KEY_SIZE_MIN      (8)
 
 /**
  * Define IO capabilities
@@ -63,7 +64,7 @@
 #define CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT (0x03)
 #define CFG_IO_CAPABILITY_KEYBOARD_DISPLAY   (0x04)
 
-#define CFG_IO_CAPABILITY             CFG_IO_CAPABILITY_DISPLAY_YES_NO
+#define CFG_IO_CAPABILITY              CFG_IO_CAPABILITY_DISPLAY_YES_NO
 
 /**
  * Define MITM modes
@@ -73,6 +74,35 @@
 
 #define CFG_MITM_PROTECTION             CFG_MITM_PROTECTION_REQUIRED
 
+/**
+ * Define Secure Connections Support
+ */
+#define CFG_SECURE_NOT_SUPPORTED       (0x00)
+#define CFG_SECURE_OPTIONAL            (0x01)
+#define CFG_SECURE_MANDATORY           (0x02)
+
+#define CFG_SC_SUPPORT                 CFG_SECURE_OPTIONAL
+
+/**
+ * Define Keypress Notification Support
+ */
+#define CFG_KEYPRESS_NOT_SUPPORTED      (0x00)
+#define CFG_KEYPRESS_SUPPORTED          (0x01)
+
+#define CFG_KEYPRESS_NOTIFICATION_SUPPORT             CFG_KEYPRESS_NOT_SUPPORTED
+   
+/**
+ * Numeric Comparison Answers
+ */   
+#define YES (0x01)
+#define NO  (0x00)
+
+/**
+ * Device name configuration for Generic Access Service
+ */
+#define CFG_GAP_DEVICE_NAME             "TEMPLATE"
+#define CFG_GAP_DEVICE_NAME_LENGTH      (8)
+
 /**
  * Define PHY
  */
@@ -254,7 +284,7 @@
  * Select UART interfaces
  */
 #define CFG_DEBUG_TRACE_UART    hw_uart1
-#define CFG_CONSOLE_MENU      
+#define CFG_CONSOLE_MENU      0
 /******************************************************************************
  * USB interface
  ******************************************************************************/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/app_debug.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/app_debug.h
new file mode 100644
index 000000000..4224edbe0
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/app_debug.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : app_debug.h
+  * Description        : Header for app_debug.c module
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/hw_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/hw_conf.h
index 6733a683f..5492cbb08 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/hw_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/hw_conf.h
@@ -27,6 +27,34 @@
  * Semaphores
  * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
  *****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
 /* Index of the semaphore used to manage the entry Stop Mode procedure */
 #define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/main.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/main.h
index 55097bac8..4b10d2beb 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/main.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/main.h
@@ -29,6 +29,7 @@ extern "C" {
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32wbxx_hal.h"
+#include "app_conf.h"
 
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/stm32wbxx_hal_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/stm32wbxx_hal_conf.h
index 7f1537260..d5db0e33f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/stm32wbxx_hal_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Inc/stm32wbxx_hal_conf.h
@@ -39,6 +39,7 @@
 /*#define HAL_CRC_MODULE_ENABLED   */
 #define HAL_HSEM_MODULE_ENABLED
 /*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
 #define HAL_IPCC_MODULE_ENABLED
 /*#define HAL_IRDA_MODULE_ENABLED   */
 /*#define HAL_IWDG_MODULE_ENABLED   */
@@ -70,6 +71,7 @@
 #define USE_HAL_COMP_REGISTER_CALLBACKS      0u
 #define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
 #define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
 #define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
 #define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
 #define USE_HAL_PCD_REGISTER_CALLBACKS       0u
@@ -243,6 +245,10 @@
  #include "stm32wbxx_hal_i2c.h"
 #endif /* HAL_I2C_MODULE_ENABLED */
 
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
 #ifdef HAL_IPCC_MODULE_ENABLED
  #include "stm32wbxx_hal_ipcc.h"
 #endif /* HAL_IPCC_MODULE_ENABLED */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/app_debug.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/app_debug.c
new file mode 100644
index 000000000..14ed65c22
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/app_debug.c
@@ -0,0 +1,399 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : app_debug.c
+  * Description        : Debug capabilities source file for STM32WPAN Middleware
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+#ifdef CFG_DEBUG_TRACE_UART
+#if(CFG_HW_LPUART1_ENABLED == 1)
+extern void MX_LPUART1_UART_Init(void);
+#endif
+#if(CFG_HW_USART1_ENABLED == 1)
+extern void MX_USART1_UART_Init(void);
+#endif
+#endif
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+/* USER CODE END PV */
+
+/* Global variables ----------------------------------------------------------*/
+/* USER CODE BEGIN GV */
+/* USER CODE END GV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+/* USER CODE BEGIN APPD_Init */
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+/* USER CODE END APPD_Init */
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+/* USER CODE BEGIN APPD_EnableCPU2 */
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+/* USER CODE END APPD_EnableCPU2 */
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+/* USER CODE BEGIN APPD_SetCPU2GpioConfig */
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+/* USER CODE END APPD_SetCPU2GpioConfig */
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+/* USER CODE BEGIN APPD_BleDtbCfg */
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+/* USER CODE END APPD_BleDtbCfg */
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+/* USER CODE BEGIN DbgOutputInit */
+#ifdef CFG_DEBUG_TRACE_UART
+if (CFG_DEBUG_TRACE_UART == hw_lpuart1)
+{
+#if(CFG_HW_LPUART1_ENABLED == 1)
+    MX_LPUART1_UART_Init();
+#endif
+}
+else if (CFG_DEBUG_TRACE_UART == hw_uart1)
+{
+#if(CFG_HW_USART1_ENABLED == 1)
+    MX_USART1_UART_Init();
+#endif
+}
+#endif
+
+/* USER CODE END DbgOutputInit */
+  return;
+}
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+/* USER CODE END DbgOutputTraces */
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+/* USER CODE END DbgOutputTraces */
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/app_entry.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/app_entry.c
index 9d38af323..a70641314 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/app_entry.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/app_entry.c
@@ -29,7 +29,7 @@
 #include "stm32_seq.h"
 #include "shci_tl.h"
 #include "stm32_lpm.h"
-#include "dbg_trace.h"
+#include "app_debug.h"
 
 /* Private includes -----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
@@ -66,7 +66,6 @@ PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t BleSpareEvtBuffer[sizeof(TL_
 
 /* Private functions prototypes-----------------------------------------------*/
 static void SystemPower_Config( void );
-static void Init_Debug( void );
 static void appe_Tl_Init( void );
 static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status );
 static void APPE_SysUserEvtRx( void * pPayload );
@@ -91,7 +90,7 @@ void APPE_Init( void )
   HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
 
 /* USER CODE BEGIN APPE_Init_1 */
-  Init_Debug();
+  APPD_Init();
   
   /**
    * The Standby mode should not be entered before the initialization is over
@@ -124,47 +123,6 @@ void APPE_Init( void )
  * LOCAL FUNCTIONS
  *
  *************************************************************/
-static void Init_Debug( void )
-{
-#if (CFG_DEBUGGER_SUPPORTED == 1)
-  /**
-   * Keep debugger enabled while in any low power mode
-   */
-  HAL_DBGMCU_EnableDBGSleepMode();
-
-  /***************** ENABLE DEBUGGER *************************************/
-  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-  LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-
-#else
-
-  GPIO_InitTypeDef gpio_config = {0};
-
-  gpio_config.Pull = GPIO_NOPULL;
-  gpio_config.Mode = GPIO_MODE_ANALOG;
-
-  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOA, &gpio_config);
-  __HAL_RCC_GPIOA_CLK_DISABLE();
-
-  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOB, &gpio_config);
-  __HAL_RCC_GPIOB_CLK_DISABLE();
-
-  HAL_DBGMCU_DisableDBGSleepMode();
-  HAL_DBGMCU_DisableDBGStopMode();
-  HAL_DBGMCU_DisableDBGStandbyMode();
-
-#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
-
-#if(CFG_DEBUG_TRACE != 0)
-  DbgTraceInit();
-#endif
-
-  return;
-}
 
 /**
  * @brief  Configure the system for power optimization
@@ -239,7 +197,7 @@ static void APPE_SysUserEvtRx( void * pPayload )
 {
   UNUSED(pPayload);
   /* Traces channel initialization */
-  TL_TRACES_Init( );
+  APPD_EnableCPU2( );
 
   APP_BLE_Init( );
   UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE);
@@ -324,34 +282,6 @@ void shci_cmd_resp_wait(uint32_t timeout)
   return;
 }
 
-/**
-  * @brief  Initialisation of the trace mechanism
-  * @param  None
-  * @retval None
-  */
-#if(CFG_DEBUG_TRACE != 0)
-void DbgOutputInit( void )
-{
-    MX_USART1_UART_Init();
-
-  return;
-}
-
-/**
-  * @brief  Management of the traces
-  * @param  p_data : data
-  * @param  size : size
-  * @param  call-back :
-  * @retval None
-  */
-void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
-{
-  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
-
-  return;
-}
-#endif
-
 /* USER CODE BEGIN FD_WRAP_FUNCTIONS */
 void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin )
 {
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/hw_timerserver.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/hw_timerserver.c
index c842ba55e..e0e4fcb5d 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/hw_timerserver.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/hw_timerserver.c
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/hw_uart.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/hw_uart.c
index 9a553610d..ce910235c 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/hw_uart.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/hw_uart.c
@@ -6,7 +6,7 @@
   ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/main.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/main.c
index febf1f268..cea2fdfb2 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/main.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/main.c
@@ -110,7 +110,6 @@ int main(void)
   /* USER CODE BEGIN 1 */
 
   /* USER CODE END 1 */
-  
 
   /* MCU Configuration--------------------------------------------------------*/
 
@@ -139,9 +138,8 @@ int main(void)
 
   /* USER CODE END 2 */
 
-  /* Init code for STM32_WPAN */  
+  /* Init code for STM32_WPAN */
   APPE_Init();
-
   /* Infinite loop */
   /* USER CODE BEGIN WHILE */
 	while(1)
@@ -166,6 +164,7 @@ void SystemClock_Config(void)
 
   /** Configure LSE Drive Capability 
   */
+  HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
   /** Configure the main internal regulator output voltage 
   */
@@ -210,7 +209,6 @@ void SystemClock_Config(void)
   PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
   PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
   PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
-
   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
   {
     Error_Handler();
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/stm32_lpm_if.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/stm32_lpm_if.c
index f024b61e3..1418e0a36 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/stm32_lpm_if.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/stm32_lpm_if.c
@@ -70,6 +70,13 @@ static void Switch_On_HSI( void );
 void PWR_EnterOffMode( void )
 {
 /* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
   /************************************************************************************
    * ENTER OFF MODE
    ***********************************************************************************/
@@ -106,6 +113,8 @@ void PWR_ExitOffMode( void )
 {
 /* USER CODE BEGIN PWR_ExitOffMode */
 
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitOffMode */
 }
 
@@ -118,6 +127,16 @@ void PWR_ExitOffMode( void )
 void PWR_EnterStopMode( void )
 {
 /* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
   /**
    * This function is called from CRITICAL SECTION
    */
@@ -202,6 +221,9 @@ void PWR_ExitStopMode( void )
 
   /* Release RCC semaphore */
   LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitStopMode */
 }
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/stm32wbxx_hal_msp.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/stm32wbxx_hal_msp.c
index f22ad0f38..fc4e64f31 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/stm32wbxx_hal_msp.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/Core/Src/stm32wbxx_hal_msp.c
@@ -293,6 +293,7 @@ void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
   /* USER CODE END RTC_MspInit 0 */
     /* Peripheral clock enable */
     __HAL_RCC_RTC_ENABLE();
+    __HAL_RCC_RTCAPB_CLK_ENABLE();
   /* USER CODE BEGIN RTC_MspInit 1 */
   HAL_RTCEx_EnableBypassShadow(hrtc);
   /* USER CODE END RTC_MspInit 1 */
@@ -315,6 +316,7 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
   /* USER CODE END RTC_MspDeInit 0 */
     /* Peripheral clock disable */
     __HAL_RCC_RTC_DISABLE();
+    __HAL_RCC_RTCAPB_CLK_DISABLE();
   /* USER CODE BEGIN RTC_MspDeInit 1 */
 
   /* USER CODE END RTC_MspDeInit 1 */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/EWARM/BLE_HeartRate.ewp b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/EWARM/BLE_HeartRate.ewp
index 1d5566776..82e43f228 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/EWARM/BLE_HeartRate.ewp
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/EWARM/BLE_HeartRate.ewp
@@ -1052,6 +1052,9 @@
         
           $PROJ_DIR$\..\Core\Src\main.c
         
+        
+          $PROJ_DIR$\..\Core\Src\app_debug.c
+        
         
           $PROJ_DIR$\..\Core\Src\app_entry.c
         
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/EWARM/stm32wb55xx_flash_cm4.icf b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/EWARM/stm32wb55xx_flash_cm4.icf
index 46f07d1f3..5f36da686 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/EWARM/stm32wb55xx_flash_cm4.icf
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/EWARM/stm32wb55xx_flash_cm4.icf
@@ -11,7 +11,7 @@ define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
 define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
 /*-Sizes-*/
 define symbol __ICFEDIT_size_cstack__ = 0x1000;
-define symbol __ICFEDIT_size_heap__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x400;
 /**** End of ICF editor section. ###ICF###*/
 
 define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000;
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/MDK-ARM/BLE_HeartRate.uvprojx b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/MDK-ARM/BLE_HeartRate.uvprojx
index fe7c428c7..e66e8c4a1 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/MDK-ARM/BLE_HeartRate.uvprojx
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/MDK-ARM/BLE_HeartRate.uvprojx
@@ -420,6 +420,11 @@
               1
               ../Core/Src/main.c
             
+            
+              app_debug.c
+              1
+              ../Core/Src/app_debug.c
+            
             
               app_entry.c
               1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/app_ble.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/app_ble.c
index 64baa2f22..f54d69a22 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/app_ble.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/app_ble.c
@@ -331,10 +331,11 @@ void APP_BLE_Init( void )
    * From here, all initialization are BLE application specific
    */
   UTIL_SEQ_RegTask( 1<subevent)
       {
-        case EVT_LE_CONN_UPDATE_COMPLETE: 
+        case EVT_LE_CONN_UPDATE_COMPLETE:
           APP_DBG_MSG("\r\n\r** CONNECTION UPDATE EVENT WITH CLIENT \n");
 
           /* USER CODE BEGIN EVT_LE_CONN_UPDATE_COMPLETE */
@@ -709,7 +710,7 @@ static void Ble_Hci_Gap_Gatt_Init(void){
   manuf_data[ sizeof(manuf_data)-3] = bd_addr[2];
   manuf_data[ sizeof(manuf_data)-2] = bd_addr[1];
   manuf_data[ sizeof(manuf_data)-1] = bd_addr[0];
-  
+
   /**
    * Write Identity root key used to derive LTK and CSRK 
    */
@@ -813,11 +814,11 @@ static void Ble_Hci_Gap_Gatt_Init(void){
    */
   BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode = CFG_MITM_PROTECTION;
   BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data_Present = 0;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin = 8;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax = 16;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin = 1;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin = 111111;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode = 1;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin = CFG_ENCRYPTION_KEY_SIZE_MIN;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax = CFG_ENCRYPTION_KEY_SIZE_MAX;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin = CFG_USED_FIXED_PIN;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin = CFG_FIXED_PIN;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode = CFG_BONDING_MODE;
   for (index = 0; index < 16; index++)
   {
     BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data[index] = (uint8_t) index;
@@ -825,14 +826,14 @@ static void Ble_Hci_Gap_Gatt_Init(void){
 
   aci_gap_set_authentication_requirement(BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode,
-                                         1,
-                                         0,
+                                         CFG_SC_SUPPORT,
+                                         CFG_KEYPRESS_NOTIFICATION_SUPPORT,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin,
-                                         0
-                                        );
+                                         PUBLIC_ADDR
+                                         );
 
   /**
    * Initialize whitelist
@@ -897,9 +898,9 @@ static void Adv_Request(APP_BLE_ConnStatus_t New_Status)
         BleApplicationContext.BleApplicationContext_legacy.advtServUUID,
         0,
         0);
+
     /* Update Advertising data */
     ret = aci_gap_update_adv_data(sizeof(manuf_data), (uint8_t*) manuf_data);
-
     if (ret == BLE_STATUS_SUCCESS)
     {
       if (New_Status == APP_BLE_FAST_ADV)
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/ble_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/ble_conf.h
index 2e0c37951..faf09232f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/ble_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/ble_conf.h
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/ble_dbg_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/ble_dbg_conf.h
index a24660c50..803855d69 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/ble_dbg_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/STM32_WPAN/App/ble_dbg_conf.h
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/STM32_WPAN/Target/hw_ipcc.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/STM32_WPAN/Target/hw_ipcc.c
index a0d8b3b5b..c6e1ca97a 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/STM32_WPAN/Target/hw_ipcc.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/STM32_WPAN/Target/hw_ipcc.c
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/SW4STM32/BLE_HeartRate/.project b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/SW4STM32/BLE_HeartRate/.project
index 936839758..0b2ab3b40 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/SW4STM32/BLE_HeartRate/.project
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/SW4STM32/BLE_HeartRate/.project
@@ -39,6 +39,11 @@
 			1
 			PARENT-2-PROJECT_LOC/Core/Src/main.c
 		
+	
+			Application/User/Core/app_debug.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/app_debug.c
+		
     
 			Application/User/Core/app_entry.c
 			1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/SW4STM32/BLE_HeartRate/stm32wb55xx_flash_cm4.ld b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/SW4STM32/BLE_HeartRate/stm32wb55xx_flash_cm4.ld
index a9ccd801e..7ac9a391f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/SW4STM32/BLE_HeartRate/stm32wb55xx_flash_cm4.ld
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/SW4STM32/BLE_HeartRate/stm32wb55xx_flash_cm4.ld
@@ -50,7 +50,7 @@ ENTRY(Reset_Handler)
 _estack = 0x20030000;    /* end of RAM */
 /* Generate a link error if heap and stack don't fit into RAM */
 _Min_Heap_Size = 0x400;      /* required amount of heap  */
-_Min_Stack_Size = 0x1000; /* required amount of stack */
+_Min_Stack_Size = 0x1000;   /* required amount of stack */
 
 /* Specify the memory areas */
 MEMORY
@@ -181,7 +181,7 @@ SECTIONS
   .ARM.attributes 0       : { *(.ARM.attributes) }
    MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
    MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
-   MB_MEM2                : { *(MB_MEM2) } >RAM_SHARED  
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
 }
 
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/SW4STM32/startup_stm32wb55xx_cm4.s b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/SW4STM32/startup_stm32wb55xx_cm4.s
index 023c1b016..f79eec117 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/SW4STM32/startup_stm32wb55xx_cm4.s
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate/SW4STM32/startup_stm32wb55xx_cm4.s
@@ -44,21 +44,29 @@ defined in linker script */
 .word	_sbss
 /* end address for the .bss section. defined in linker script */
 .word	_ebss
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
   movs r3, #0
-  b	LoopCopyDataInit
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
 
+.section  .text.data_initializers
 CopyDataInit:
   ldr r4, [r2, r3]
   str r4, [r0, r3]
@@ -67,21 +75,31 @@ CopyDataInit:
 LoopCopyDataInit:
   adds r4, r0, r3
   cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
+  bcc  CopyDataInit
+  bx lr
 
 FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
+  str  r3, [r0]
+  adds r0, r0, #4
 
 LoopFillZerobss:
-  cmp r2, r4
+  cmp r0, r1
   bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/BLE_HeartRateFreeRTOS.ioc b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/BLE_HeartRateFreeRTOS.ioc
index 33dcea120..29de92d15 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/BLE_HeartRateFreeRTOS.ioc
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/BLE_HeartRateFreeRTOS.ioc
@@ -100,8 +100,8 @@ Mcu.PinsNb=17
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32WB55RGVx
-MxCube.Version=5.5.0
-MxDb.Version=DB.5.0.50
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.DMA1_Channel4_IRQn=true\:15\:0\:true\:false\:true\:true\:false\:true
 NVIC.DMA2_Channel4_IRQn=true\:15\:0\:true\:false\:true\:true\:false\:true
@@ -166,14 +166,6 @@ PCC.Ble.ConnectionInterval=1000.0
 PCC.Ble.DataLength=6
 PCC.Ble.Mode=Advertising
 PCC.Ble.PowerLevel=Min
-PCC.Checker=true
-PCC.Line=STM32WBx5
-PCC.MCU=STM32WB55RGVx
-PCC.PartNumber=STM32WB55RGVx
-PCC.Seq0=0
-PCC.Series=STM32WB
-PCC.Temperature=25
-PCC.Vdd=3.0
 PinOutPanel.RotationAngle=0
 ProjectManager.AskForMigrate=true
 ProjectManager.BackupPrevious=false
@@ -295,8 +287,9 @@ STM32_WPAN.CFG_LP_CONN_ADV_INTERVAL_MIN=1000
 STM32_WPAN.CFG_MITM_PROTECTION=CFG_MITM_PROTECTION_REQUIRED
 STM32_WPAN.CFG_RTCCLK_DIVIDER_CONF=0
 STM32_WPAN.DBG_TRACE_UART_CFG=hw_uart1
-STM32_WPAN.IPParameters=P2P_SERVER_NUMBER,CFG_FAST_CONN_ADV_INTERVAL_MAX_HEXA,CFG_LP_CONN_ADV_INTERVAL_MAX_HEXA,LOCAL_NAME_FORMATTED,CFG_HW_LPUART1_ENABLED,CFG_DEBUG_BLE_TRACE,CFG_DEBUG_APP_TRACE,DBG_TRACE_UART_CFG,CFG_ADV_BD_ADDRESS,CFG_LP_CONN_ADV_INTERVAL_MAX,CFG_LP_CONN_ADV_INTERVAL_MIN,CFG_HW_LPUART1_DMA_TX_SUPPORTED,CFG_HW_USART1_ENABLED,CFG_LPM_SUPPORTED,L2CAP_REQUEST_NEW_CONN_PARAM,BT_SIG_HEART_RATE_SENSOR,CFG_DEBUGGER_SUPPORTED,BLE_DBG_DIS_EN,BLE_DBG_HRS_EN,BLE_DBG_SVCCTL_EN,BLE_APPLICATION_TYPE,BLE_CFG_DIS_MANUFACTURER_NAME_STRING,BLE_CFG_DIS_MODEL_NUMBER_STRING,BLE_CFG_DIS_SERIAL_NUMBER_STRING,BLE_CFG_DIS_HARDWARE_REVISION_STRING,BLE_CFG_DIS_FIRMWARE_REVISION_STRING,BLE_CFG_DIS_SOFTWARE_REVISION_STRING,BLE_CFG_DIS_SYSTEM_ID,BLE_CFG_DIS_IEEE_CERTIFICATION,BLE_CFG_DIS_PNP_ID,BLE_CFG_HRS_BODY_SENSOR_LOCATION_CHAR,BLE_CFG_HRS_ENERGY_EXPENDED_INFO_FLAG,BLE_CFG_HRS_ENERGY_RR_INTERVAL_FLAG,CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER,CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO,CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO,CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION,CFG_HW_RESET_BY_FW,CFG_FAST_CONN_ADV_INTERVAL_MIN,CFG_FAST_CONN_ADV_INTERVAL_MAX,CFG_IO_CAPABILITY,CFG_MITM_PROTECTION,CFG_RTCCLK_DIVIDER_CONF,CFG_DEBUG_TRACE_UART
+STM32_WPAN.IPParameters=P2P_SERVER_NUMBER,CFG_FAST_CONN_ADV_INTERVAL_MAX_HEXA,CFG_LP_CONN_ADV_INTERVAL_MAX_HEXA,LOCAL_NAME_FORMATTED,CFG_HW_LPUART1_ENABLED,CFG_DEBUG_BLE_TRACE,CFG_DEBUG_APP_TRACE,DBG_TRACE_UART_CFG,CFG_ADV_BD_ADDRESS,CFG_LP_CONN_ADV_INTERVAL_MAX,CFG_LP_CONN_ADV_INTERVAL_MIN,CFG_HW_LPUART1_DMA_TX_SUPPORTED,CFG_HW_USART1_ENABLED,CFG_LPM_SUPPORTED,L2CAP_REQUEST_NEW_CONN_PARAM,BT_SIG_HEART_RATE_SENSOR,CFG_DEBUGGER_SUPPORTED,BLE_DBG_DIS_EN,BLE_DBG_HRS_EN,BLE_DBG_SVCCTL_EN,BLE_APPLICATION_TYPE,BLE_CFG_DIS_MANUFACTURER_NAME_STRING,BLE_CFG_DIS_MODEL_NUMBER_STRING,BLE_CFG_DIS_SERIAL_NUMBER_STRING,BLE_CFG_DIS_HARDWARE_REVISION_STRING,BLE_CFG_DIS_FIRMWARE_REVISION_STRING,BLE_CFG_DIS_SOFTWARE_REVISION_STRING,BLE_CFG_DIS_SYSTEM_ID,BLE_CFG_DIS_IEEE_CERTIFICATION,BLE_CFG_DIS_PNP_ID,BLE_CFG_HRS_BODY_SENSOR_LOCATION_CHAR,BLE_CFG_HRS_ENERGY_EXPENDED_INFO_FLAG,BLE_CFG_HRS_ENERGY_RR_INTERVAL_FLAG,CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER,CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO,CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO,CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION,CFG_HW_RESET_BY_FW,CFG_FAST_CONN_ADV_INTERVAL_MIN,CFG_FAST_CONN_ADV_INTERVAL_MAX,CFG_IO_CAPABILITY,CFG_MITM_PROTECTION,CFG_RTCCLK_DIVIDER_CONF,CFG_DEBUG_TRACE_UART,LOCAL_NAME
 STM32_WPAN.L2CAP_REQUEST_NEW_CONN_PARAM=1
+STM32_WPAN.LOCAL_NAME=HRSTM
 STM32_WPAN.LOCAL_NAME_FORMATTED=,'H','R','S','T','M'
 STM32_WPAN.P2P_SERVER_NUMBER=P2P_SERVER1
 USART1.AutoBaudRateEnableParam=UART_ADVFEATURE_AUTOBAUDRATE_DISABLE
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/FreeRTOSConfig.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/FreeRTOSConfig.h
index 9c3a79b89..bc31a094a 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/FreeRTOSConfig.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/FreeRTOSConfig.h
@@ -36,10 +36,10 @@
  * These definitions should be adjusted for your particular hardware and
  * application requirements.
  *
- * These parameters and more are described within the 'configuration' section of the
- * FreeRTOS API documentation available on the FreeRTOS.org web site.
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
  *
- * See http://www.freertos.org/a00110.html
+ * See http://www.freertos.org/a00110.html.
  *----------------------------------------------------------*/
 
 /* USER CODE BEGIN Includes */   	      
@@ -51,6 +51,9 @@
   #include 
   extern uint32_t SystemCoreClock;
 #endif
+#define configENABLE_FPU                         0
+#define configENABLE_MPU                         0
+
 #define configUSE_PREEMPTION                     1
 #define configSUPPORT_STATIC_ALLOCATION          1
 #define configSUPPORT_DYNAMIC_ALLOCATION         1
@@ -70,6 +73,11 @@
 #define configUSE_COUNTING_SEMAPHORES            1
 #define configUSE_PORT_OPTIMISED_TASK_SELECTION  0
 #define configUSE_TICKLESS_IDLE                  2
+/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */
+/* Defaults to size_t for backward compatibility, but can be changed
+   if lengths will always be less than the number of bytes in a size_t. */
+#define configMESSAGE_BUFFER_LENGTH_TYPE         size_t
+/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */ 
 
 /* Co-routine definitions. */
 #define configUSE_CO_ROUTINES                    0
@@ -83,18 +91,18 @@
 
 /* Set the following definitions to 1 to include the API function, or zero
 to exclude the API function. */
-#define INCLUDE_vTaskPrioritySet            1
-#define INCLUDE_uxTaskPriorityGet           1
-#define INCLUDE_vTaskDelete                 1
-#define INCLUDE_vTaskCleanUpResources       0
-#define INCLUDE_vTaskSuspend                1
-#define INCLUDE_vTaskDelayUntil             1
-#define INCLUDE_vTaskDelay                  1
-#define INCLUDE_xTaskGetSchedulerState      1
-#define INCLUDE_xTimerPendFunctionCall      1
-#define INCLUDE_xQueueGetMutexHolder        1
-#define INCLUDE_uxTaskGetStackHighWaterMark 1
-#define INCLUDE_eTaskGetState               1
+#define INCLUDE_vTaskPrioritySet             1
+#define INCLUDE_uxTaskPriorityGet            1
+#define INCLUDE_vTaskDelete                  1
+#define INCLUDE_vTaskCleanUpResources        0
+#define INCLUDE_vTaskSuspend                 1
+#define INCLUDE_vTaskDelayUntil              1
+#define INCLUDE_vTaskDelay                   1
+#define INCLUDE_xTaskGetSchedulerState       1
+#define INCLUDE_xTimerPendFunctionCall       1
+#define INCLUDE_xQueueGetMutexHolder         1
+#define INCLUDE_uxTaskGetStackHighWaterMark  1
+#define INCLUDE_eTaskGetState                1
 
 /* 
  * The CMSIS-RTOS V2 FreeRTOS wrapper is dependent on the heap implementation used
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_common.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_common.h
index 4defc5d7a..836f40dcf 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_common.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_common.h
@@ -1,12 +1,13 @@
+/* USER CODE BEGIN Header */
 /**
  ******************************************************************************
   * File Name          : app_common.h
   * Description        : App Common application configuration file for STM32WPAN Middleware.
   *
- ******************************************************************************
+  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
@@ -16,7 +17,7 @@
   *
   ******************************************************************************
   */
-
+/* USER CODE END Header */
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef APP_COMMON_H
 #define APP_COMMON_H
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_conf.h
index 809017802..1e285ae58 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_conf.h
@@ -1,12 +1,12 @@
+/* USER CODE BEGIN Header */
 /**
  ******************************************************************************
   * File Name          : app_conf.h
   * Description        : Application configuration file for STM32WPAN Middleware.
-  *
- ******************************************************************************
+  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
@@ -16,6 +16,7 @@
   *
   ******************************************************************************
   */
+/* USER CODE END Header */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef APP_CONF_H
@@ -48,11 +49,11 @@
 /**
  * Define IO Authentication
  */
-#define CFG_BONDING_MODE                  (1)
-#define CFG_FIXED_PIN                     (111111)
-#define CFG_USED_FIXED_PIN                (0)
-#define CFG_ENCRYPTION_KEY_SIZE_MAX       (16)
-#define CFG_ENCRYPTION_KEY_SIZE_MIN       (8)
+#define CFG_BONDING_MODE                 (0)
+#define CFG_FIXED_PIN                    (111111)
+#define CFG_USED_FIXED_PIN               (0)
+#define CFG_ENCRYPTION_KEY_SIZE_MAX      (16)
+#define CFG_ENCRYPTION_KEY_SIZE_MIN      (8)
 
 /**
  * Define IO capabilities
@@ -63,7 +64,7 @@
 #define CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT (0x03)
 #define CFG_IO_CAPABILITY_KEYBOARD_DISPLAY   (0x04)
 
-#define CFG_IO_CAPABILITY             CFG_IO_CAPABILITY_DISPLAY_YES_NO
+#define CFG_IO_CAPABILITY              CFG_IO_CAPABILITY_DISPLAY_YES_NO
 
 /**
  * Define MITM modes
@@ -73,6 +74,35 @@
 
 #define CFG_MITM_PROTECTION             CFG_MITM_PROTECTION_REQUIRED
 
+/**
+ * Define Secure Connections Support
+ */
+#define CFG_SECURE_NOT_SUPPORTED       (0x00)
+#define CFG_SECURE_OPTIONAL            (0x01)
+#define CFG_SECURE_MANDATORY           (0x02)
+
+#define CFG_SC_SUPPORT                 CFG_SECURE_OPTIONAL
+
+/**
+ * Define Keypress Notification Support
+ */
+#define CFG_KEYPRESS_NOT_SUPPORTED      (0x00)
+#define CFG_KEYPRESS_SUPPORTED          (0x01)
+
+#define CFG_KEYPRESS_NOTIFICATION_SUPPORT             CFG_KEYPRESS_NOT_SUPPORTED
+   
+/**
+ * Numeric Comparison Answers
+ */   
+#define YES (0x01)
+#define NO  (0x00)
+
+/**
+ * Device name configuration for Generic Access Service
+ */
+#define CFG_GAP_DEVICE_NAME             "TEMPLATE"
+#define CFG_GAP_DEVICE_NAME_LENGTH      (8)
+
 /**
  * Define PHY
  */
@@ -254,7 +284,7 @@
  * Select UART interfaces
  */
 #define CFG_DEBUG_TRACE_UART    hw_uart1
-#define CFG_CONSOLE_MENU      
+#define CFG_CONSOLE_MENU      0
 /******************************************************************************
  * USB interface
  ******************************************************************************/
@@ -448,7 +478,7 @@ typedef enum
 #define CFG_SHCI_USER_EVT_PROCESS_CB_SIZE     (0)
 #define CFG_SHCI_USER_EVT_PROCESS_STACK_MEM   (0)
 #define CFG_SHCI_USER_EVT_PROCESS_PRIORITY    osPriorityNone
-#define CFG_SHCI_USER_EVT_PROCESS_STACk_SIZE  (128 * 7)
+#define CFG_SHCI_USER_EVT_PROCESS_STACK_SIZE  (128 * 7)
 
 #define CFG_HCI_USER_EVT_PROCESS_NAME         "HCI_USER_EVT_PROCESS"
 #define CFG_HCI_USER_EVT_PROCESS_ATTR_BITS    (0)
@@ -456,7 +486,7 @@ typedef enum
 #define CFG_HCI_USER_EVT_PROCESS_CB_SIZE      (0)
 #define CFG_HCI_USER_EVT_PROCESS_STACK_MEM    (0)
 #define CFG_HCI_USER_EVT_PROCESS_PRIORITY     osPriorityNone
-#define CFG_HCI_USER_EVT_PROCESS_STACk_SIZE   (128 * 8)
+#define CFG_HCI_USER_EVT_PROCESS_STACK_SIZE   (128 * 8)
 
 #define CFG_ADV_UPDATE_PROCESS_NAME           "ADV_UPDATE_PROCESS"
 #define CFG_ADV_UPDATE_PROCESS_ATTR_BITS      (0)
@@ -464,7 +494,7 @@ typedef enum
 #define CFG_ADV_UPDATE_PROCESS_CB_SIZE        (0)
 #define CFG_ADV_UPDATE_PROCESS_STACK_MEM      (0)
 #define CFG_ADV_UPDATE_PROCESS_PRIORITY       osPriorityNone
-#define CFG_ADV_UPDATE_PROCESS_STACk_SIZE     (128 * 6)
+#define CFG_ADV_UPDATE_PROCESS_STACK_SIZE     (128 * 6)
 
 #define CFG_HRS_PROCESS_NAME                  "HRS_PROCESS"
 #define CFG_HRS_PROCESS_ATTR_BITS             (0)
@@ -472,7 +502,7 @@ typedef enum
 #define CFG_HRS_PROCESS_CB_SIZE               (0)
 #define CFG_HRS_PROCESS_STACK_MEM             (0)
 #define CFG_HRS_PROCESS_PRIORITY              osPriorityNone
-#define CFG_HRS_PROCESS_STACk_SIZE            (128 * 5)
+#define CFG_HRS_PROCESS_STACK_SIZE            (128 * 5)
 
 /* USER CODE BEGIN FreeRTOS_Defines */
 #define PUSH_BUTTON_SW1_EXTI_IRQHandler     EXTI4_IRQHandler
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_debug.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_debug.h
new file mode 100644
index 000000000..4224edbe0
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/app_debug.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : app_debug.h
+  * Description        : Header for app_debug.c module
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/hw_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/hw_conf.h
index ac7d196f7..097cedfd8 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/hw_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/hw_conf.h
@@ -29,6 +29,34 @@
  * Semaphores
  * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
  *****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
 /* Index of the semaphore used to manage the entry Stop Mode procedure */
 #define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/main.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/main.h
index 55097bac8..4b10d2beb 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/main.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/main.h
@@ -29,6 +29,7 @@ extern "C" {
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32wbxx_hal.h"
+#include "app_conf.h"
 
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/stm32wbxx_hal_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/stm32wbxx_hal_conf.h
index 8a056226f..b5b04b135 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/stm32wbxx_hal_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Inc/stm32wbxx_hal_conf.h
@@ -39,6 +39,7 @@
 /*#define HAL_CRC_MODULE_ENABLED   */
 #define HAL_HSEM_MODULE_ENABLED
 /*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
 /*#define HAL_IPCC_MODULE_ENABLED   */
 /*#define HAL_IRDA_MODULE_ENABLED   */
 /*#define HAL_IWDG_MODULE_ENABLED   */
@@ -70,6 +71,7 @@
 #define USE_HAL_COMP_REGISTER_CALLBACKS      0u
 #define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
 #define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
 #define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
 #define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
 #define USE_HAL_PCD_REGISTER_CALLBACKS       0u
@@ -243,6 +245,10 @@
  #include "stm32wbxx_hal_i2c.h"
 #endif /* HAL_I2C_MODULE_ENABLED */
 
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
 #ifdef HAL_IPCC_MODULE_ENABLED
  #include "stm32wbxx_hal_ipcc.h"
 #endif /* HAL_IPCC_MODULE_ENABLED */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/app_debug.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/app_debug.c
new file mode 100644
index 000000000..14ed65c22
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/app_debug.c
@@ -0,0 +1,399 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : app_debug.c
+  * Description        : Debug capabilities source file for STM32WPAN Middleware
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+#ifdef CFG_DEBUG_TRACE_UART
+#if(CFG_HW_LPUART1_ENABLED == 1)
+extern void MX_LPUART1_UART_Init(void);
+#endif
+#if(CFG_HW_USART1_ENABLED == 1)
+extern void MX_USART1_UART_Init(void);
+#endif
+#endif
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+/* USER CODE END PV */
+
+/* Global variables ----------------------------------------------------------*/
+/* USER CODE BEGIN GV */
+/* USER CODE END GV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+/* USER CODE BEGIN APPD_Init */
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+/* USER CODE END APPD_Init */
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+/* USER CODE BEGIN APPD_EnableCPU2 */
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+/* USER CODE END APPD_EnableCPU2 */
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+/* USER CODE BEGIN APPD_SetCPU2GpioConfig */
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+/* USER CODE END APPD_SetCPU2GpioConfig */
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+/* USER CODE BEGIN APPD_BleDtbCfg */
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+/* USER CODE END APPD_BleDtbCfg */
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+/* USER CODE BEGIN DbgOutputInit */
+#ifdef CFG_DEBUG_TRACE_UART
+if (CFG_DEBUG_TRACE_UART == hw_lpuart1)
+{
+#if(CFG_HW_LPUART1_ENABLED == 1)
+    MX_LPUART1_UART_Init();
+#endif
+}
+else if (CFG_DEBUG_TRACE_UART == hw_uart1)
+{
+#if(CFG_HW_USART1_ENABLED == 1)
+    MX_USART1_UART_Init();
+#endif
+}
+#endif
+
+/* USER CODE END DbgOutputInit */
+  return;
+}
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+/* USER CODE END DbgOutputTraces */
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+/* USER CODE END DbgOutputTraces */
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/app_entry.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/app_entry.c
index ee65df527..f0f9946bb 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/app_entry.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/app_entry.c
@@ -28,7 +28,7 @@
 #include "cmsis_os.h"
 #include "shci_tl.h"
 #include "stm32_lpm.h"
-#include "dbg_trace.h"
+#include "app_debug.h"
 
 /* Private includes -----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
@@ -75,13 +75,12 @@ const osThreadAttr_t ShciUserEvtProcess_attr = {
     .cb_size = CFG_SHCI_USER_EVT_PROCESS_CB_SIZE,
     .stack_mem = CFG_SHCI_USER_EVT_PROCESS_STACK_MEM,
     .priority = CFG_SHCI_USER_EVT_PROCESS_PRIORITY,
-    .stack_size = CFG_SHCI_USER_EVT_PROCESS_STACk_SIZE
+    .stack_size = CFG_SHCI_USER_EVT_PROCESS_STACK_SIZE
 };
 
 /* Private functions prototypes-----------------------------------------------*/
 static void ShciUserEvtProcess(void *argument);
 static void SystemPower_Config( void );
-static void Init_Debug( void );
 static void appe_Tl_Init( void );
 static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status );
 static void APPE_SysUserEvtRx( void * pPayload );
@@ -106,7 +105,7 @@ void APPE_Init( void )
   HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
 
 /* USER CODE BEGIN APPE_Init_1 */
-  Init_Debug();
+  APPD_Init();
 
   /**
    * The Standby mode should not be entered before the initialization is over
@@ -139,47 +138,6 @@ void APPE_Init( void )
  * LOCAL FUNCTIONS
  *
  *************************************************************/
-static void Init_Debug( void )
-{
-#if (CFG_DEBUGGER_SUPPORTED == 1)
-  /**
-   * Keep debugger enabled while in any low power mode
-   */
-  HAL_DBGMCU_EnableDBGSleepMode();
-
-  /***************** ENABLE DEBUGGER *************************************/
-  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-  LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-
-#else
-
-  GPIO_InitTypeDef gpio_config = {0};
-
-  gpio_config.Pull = GPIO_NOPULL;
-  gpio_config.Mode = GPIO_MODE_ANALOG;
-
-  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOA, &gpio_config);
-  __HAL_RCC_GPIOA_CLK_DISABLE();
-
-  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOB, &gpio_config);
-  __HAL_RCC_GPIOB_CLK_DISABLE();
-
-  HAL_DBGMCU_DisableDBGSleepMode();
-  HAL_DBGMCU_DisableDBGStopMode();
-  HAL_DBGMCU_DisableDBGStandbyMode();
-
-#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
-
-#if(CFG_DEBUG_TRACE != 0)
-  DbgTraceInit();
-#endif
-
-  return;
-}
 
 /**
  * @brief  Configure the system for power optimization
@@ -271,7 +229,7 @@ static void APPE_SysUserEvtRx( void * pPayload )
 {
   UNUSED(pPayload);
   /* Traces channel initialization */
-  TL_TRACES_Init( );
+  APPD_EnableCPU2( );
 
   APP_BLE_Init( );
   UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE);
@@ -361,34 +319,6 @@ void shci_cmd_resp_wait(uint32_t timeout)
   return;
 }
 
-/**
-  * @brief  Initialisation of the trace mechanism
-  * @param  None
-  * @retval None
-  */
-#if(CFG_DEBUG_TRACE != 0)
-void DbgOutputInit( void )
-{
-    MX_USART1_UART_Init();
-
-  return;
-}
-
-/**
-  * @brief  Management of the traces
-  * @param  p_data : data
-  * @param  size : size
-  * @param  call-back :
-  * @retval None
-  */
-void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
-{
-  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
-
-  return;
-}
-#endif
-
 /* USER CODE BEGIN FD_WRAP_FUNCTIONS */
 void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin )
 {
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/freertos_port.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/freertos_port.c
index 1348d0ffa..58883cb71 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/freertos_port.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/freertos_port.c
@@ -1,21 +1,23 @@
+/* USER CODE BEGIN Header */
 /**
  ******************************************************************************
  * File Name          : freertos_port.c
- * Description        : Custom porting of FreeRTIS functionalities
+ * Description        : Custom porting of FreeRTOS functionalities
  *
  ******************************************************************************
- * @attention
- *
- * 
    © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
    
- *
- * This software component is licensed by ST under Ultimate Liberty license
- * SLA0044, the "License"; You may not use this file except in compliance with
- * the License. You may obtain a copy of the License at:
- *                             www.st.com/SLA0044
- *
- ******************************************************************************
- */
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
 
 /* Includes ------------------------------------------------------------------*/
 #include "app_common.h"
@@ -81,6 +83,8 @@ void vPortSetupTimerInterrupt( void );
  */
 void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
 {
+  /* If low power is not used, do not stop the SysTick and continue execution */
+#if ( CFG_LPM_SUPPORTED != 0)
   /**
    * Although this is not documented as such, when xExpectedIdleTime = 0xFFFFFFFF = (~0),
    * it likely means the system may enter low power for ever ( from a FreeRTOS point of view ).
@@ -119,6 +123,8 @@ void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
   {
     if (xExpectedIdleTime != (~0))
     {
+      /* Remove one tick to wake up before the event occurs */
+      xExpectedIdleTime--;
       /* Start the low power timer */
       LpTimerStart( xExpectedIdleTime );
     }
@@ -145,6 +151,7 @@ void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     /* Exit with interrUpts enabled. */
     __enable_irq();
   }
+#endif
 }
 
 /*
@@ -293,10 +300,18 @@ static void LpEnter( void )
  */
 static uint32_t LpGetElapsedTime( void )
 {
-  uint64_t return_value;
-
-  return_value = (configTICK_RATE_HZ) * (CFG_TS_TICK_VAL) * (uint64_t)(LpTimerContext.LpTimeLeftOnEntry - HW_TS_RTC_ReadLeftTicksToCount( ));
-  return_value = return_value / (1000 * 1000);
+  uint64_t val_ticks, time_us;
+
+  time_us = (CFG_TS_TICK_VAL) * (uint64_t)(LpTimerContext.LpTimeLeftOnEntry - HW_TS_RTC_ReadLeftTicksToCount( ));
+  
+  val_ticks = time_us * configTICK_RATE_HZ;
+  val_ticks = val_ticks / (1000 * 1000);
+  
+  /* add a tick if the time elapsed is above 50 % of a tick */
+  if( (time_us % (portTICK_PERIOD_MS * 1000) > (portTICK_PERIOD_MS * 1000 / 2)) )
+  {
+    val_ticks++;
+  }
 
   /**
    * The system may have been out from another reason than the timer
@@ -306,7 +321,7 @@ static uint32_t LpGetElapsedTime( void )
    */
   HW_TS_Stop(LpTimerContext.LpTimerFreeRTOS_Id);
 
-  return (uint32_t)return_value;
+  return (uint32_t)val_ticks;
 }
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_timerserver.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_timerserver.c
index c842ba55e..e0e4fcb5d 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_timerserver.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_timerserver.c
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_uart.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_uart.c
index 9a553610d..ce910235c 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_uart.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/hw_uart.c
@@ -6,7 +6,7 @@
   ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/main.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/main.c
index 0e07fbfcb..1c06069e0 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/main.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/main.c
@@ -75,7 +75,13 @@ DMA_HandleTypeDef hdma_usart1_tx;
 
 RTC_HandleTypeDef hrtc;
 
+/* Definitions for defaultTask */
 osThreadId_t defaultTaskHandle;
+const osThreadAttr_t defaultTask_attributes = {
+  .name = "defaultTask",
+  .priority = (osPriority_t) osPriorityNormal,
+  .stack_size = 256 * sizeof(StackType_t)
+};
 /* USER CODE BEGIN PV */
 
 /* USER CODE END PV */
@@ -113,7 +119,6 @@ int main(void)
   /* USER CODE BEGIN 1 */
 
   /* USER CODE END 1 */
-  
 
   /* MCU Configuration--------------------------------------------------------*/
 
@@ -142,6 +147,7 @@ int main(void)
 
   /* USER CODE END 2 */
 
+  /* Init scheduler */
   osKernelInitialize();
 
   /* USER CODE BEGIN RTOS_MUTEX */
@@ -161,12 +167,7 @@ int main(void)
   /* USER CODE END RTOS_QUEUES */
 
   /* Create the thread(s) */
-  /* definition and creation of defaultTask */
-  const osThreadAttr_t defaultTask_attributes = {
-    .name = "defaultTask",
-    .priority = (osPriority_t) osPriorityNormal,
-    .stack_size = 256
-  };
+  /* creation of defaultTask */
   defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);
 
   /* USER CODE BEGIN RTOS_THREADS */
@@ -175,12 +176,10 @@ int main(void)
 
   /* Init code for STM32_WPAN */
   APPE_Init();
-
   /* Start scheduler */
   osKernelStart();
-  
+ 
   /* We should never get here as control is now taken by the scheduler */
-
   /* Infinite loop */
   /* USER CODE BEGIN WHILE */
   while (1)
@@ -204,6 +203,7 @@ void SystemClock_Config(void)
 
   /** Configure LSE Drive Capability 
   */
+  HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
   /** Configure the main internal regulator output voltage 
   */
@@ -248,7 +248,6 @@ void SystemClock_Config(void)
   PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
   PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
   PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
-
   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
   {
     Error_Handler();
@@ -661,7 +660,7 @@ void StartDefaultTask(void *argument)
   /* USER CODE END 5 */ 
 }
 
-/**
+ /**
   * @brief  Period elapsed callback in non blocking mode
   * @note   This function is called  when TIM17 interrupt took place, inside
   * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32wbxx_hal_msp.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32wbxx_hal_msp.c
index 207c26eb8..702eb8fdd 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32wbxx_hal_msp.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/Core/Src/stm32wbxx_hal_msp.c
@@ -298,6 +298,7 @@ void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
   /* USER CODE END RTC_MspInit 0 */
     /* Peripheral clock enable */
     __HAL_RCC_RTC_ENABLE();
+    __HAL_RCC_RTCAPB_CLK_ENABLE();
   /* USER CODE BEGIN RTC_MspInit 1 */
   HAL_RTCEx_EnableBypassShadow(hrtc);
   /* USER CODE END RTC_MspInit 1 */
@@ -320,6 +321,7 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
   /* USER CODE END RTC_MspDeInit 0 */
     /* Peripheral clock disable */
     __HAL_RCC_RTC_DISABLE();
+    __HAL_RCC_RTCAPB_CLK_DISABLE();
   /* USER CODE BEGIN RTC_MspDeInit 1 */
 
   /* USER CODE END RTC_MspDeInit 1 */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/BLE_HeartRateFreeRTOS.ewp b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/BLE_HeartRateFreeRTOS.ewp
index 21e228906..a9078e35d 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/BLE_HeartRateFreeRTOS.ewp
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/BLE_HeartRateFreeRTOS.ewp
@@ -1049,6 +1049,9 @@
             
                 $PROJ_DIR$\..\Core\Src\app_entry.c
             
+            
+                $PROJ_DIR$\..\Core\Src\app_debug.c
+            
             
                 $PROJ_DIR$\..\Core\Src\freertos_port.c
             
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/startup_stm32wb55xx_cm4.s b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/startup_stm32wb55xx_cm4.s
index 79b0e7edd..1f886ff59 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/startup_stm32wb55xx_cm4.s
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/EWARM/startup_stm32wb55xx_cm4.s
@@ -1,4 +1,4 @@
-;/********************* COPYRIGHT(c) 2019 STMicroelectronics ********************
+;******************************************************************************
 ;* File Name          : startup_stm32wb55xx_cm4.s
 ;* Author             : MCD Application Team
 ;* Description        : M4 core vector table of the STM32WB55xx devices for the
@@ -13,31 +13,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
 ;*
-;*******************************************************************************
+;******************************************************************************
 ;
 ;
 ; The modules in this file are included in the libraries, and may be replaced
@@ -86,10 +73,10 @@ __vector_table
         DCD     PendSV_Handler                    ; PendSV Handler
         DCD     SysTick_Handler                   ; SysTick Handler
 
-         ; External Interrupts
+        ; External Interrupts
         DCD     WWDG_IRQHandler                   ; Window WatchDog
-        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
-        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
         DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
         DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
         DCD     RCC_IRQHandler                    ; RCC Interrupt
@@ -129,7 +116,7 @@ __vector_table
         DCD     TSC_IRQHandler                    ; TSC Interrupt
         DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
         DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
-        DCD     USB_FS_WKUP_CRS_IRQHandler        ; USB Full speed wakeup
+        DCD     CRS_IRQHandler                    ; CRS interrupt
         DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
         DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
         DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
@@ -156,6 +143,7 @@ __vector_table
 ;; Default interrupt handlers.
 ;;
         THUMB
+
         PUBWEAK Reset_Handler
         SECTION .text:CODE:NOROOT:REORDER(2)
 Reset_Handler
@@ -419,10 +407,10 @@ EXTI15_10_IRQHandler
 RTC_Alarm_IRQHandler
         B RTC_Alarm_IRQHandler
 
-        PUBWEAK USB_FS_WKUP_CRS_IRQHandler
+        PUBWEAK CRS_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
-USB_FS_WKUP_CRS_IRQHandler
-        B USB_FS_WKUP_CRS_IRQHandler
+CRS_IRQHandler
+        B CRS_IRQHandler
 
         PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
@@ -523,6 +511,7 @@ DMA2_Channel7_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMAMUX1_OVR_IRQHandler
         B DMAMUX1_OVR_IRQHandler
+
         END
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/MDK-ARM/BLE_HeartRateFreeRTOS.uvprojx b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/MDK-ARM/BLE_HeartRateFreeRTOS.uvprojx
index c1c37ab2a..b4e5d864a 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/MDK-ARM/BLE_HeartRateFreeRTOS.uvprojx
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/MDK-ARM/BLE_HeartRateFreeRTOS.uvprojx
@@ -411,6 +411,11 @@
               1
               ../Core/Src/main.c
             
+            
+              app_debug.c
+              1
+              ../Core/Src/app_debug.c
+            
             
               stm32wbxx_hal_msp.c
               1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/app_ble.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/app_ble.c
index 3f153428c..498760f26 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/app_ble.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/app_ble.c
@@ -261,7 +261,7 @@ const osThreadAttr_t AdvUpdateProcess_attr = {
     .cb_size = CFG_ADV_UPDATE_PROCESS_CB_SIZE,
     .stack_mem = CFG_ADV_UPDATE_PROCESS_STACK_MEM,
     .priority = CFG_ADV_UPDATE_PROCESS_PRIORITY,
-    .stack_size = CFG_ADV_UPDATE_PROCESS_STACk_SIZE
+    .stack_size = CFG_ADV_UPDATE_PROCESS_STACK_SIZE
 };
 
 const osThreadAttr_t HciUserEvtProcess_attr = {
@@ -271,7 +271,7 @@ const osThreadAttr_t HciUserEvtProcess_attr = {
     .cb_size = CFG_HCI_USER_EVT_PROCESS_CB_SIZE,
     .stack_mem = CFG_HCI_USER_EVT_PROCESS_STACK_MEM,
     .priority = CFG_HCI_USER_EVT_PROCESS_PRIORITY,
-    .stack_size = CFG_HCI_USER_EVT_PROCESS_STACk_SIZE
+    .stack_size = CFG_HCI_USER_EVT_PROCESS_STACK_SIZE
 };
 
 /* Private function prototypes -----------------------------------------------*/
@@ -359,10 +359,11 @@ void APP_BLE_Init( void )
    * From here, all initialization are BLE application specific
    */
   AdvUpdateProcessId = osThreadNew(AdvUpdateProcess, NULL, &AdvUpdateProcess_attr);
+
   /**
    * Initialization of ADV - Ad Manufacturer Element - Support OTA Bit Mask
    */
-#if(BLE_CFG_OTA_REBOOT_CHAR != 0)  
+#if(BLE_CFG_OTA_REBOOT_CHAR != 0)
   manuf_data[sizeof(manuf_data)-8] = CFG_FEATURE_OTA_REBOOT;
 #endif
   /**
@@ -445,7 +446,7 @@ SVCCTL_UserEvtFlowStatus_t SVCCTL_App_Notification( void *pckt )
       /* USER CODE END EVT_LE_META_EVENT */
       switch (meta_evt->subevent)
       {
-        case EVT_LE_CONN_UPDATE_COMPLETE: 
+        case EVT_LE_CONN_UPDATE_COMPLETE:
           APP_DBG_MSG("\r\n\r** CONNECTION UPDATE EVENT WITH CLIENT \n");
 
           /* USER CODE BEGIN EVT_LE_CONN_UPDATE_COMPLETE */
@@ -740,7 +741,7 @@ static void Ble_Hci_Gap_Gatt_Init(void){
   manuf_data[ sizeof(manuf_data)-3] = bd_addr[2];
   manuf_data[ sizeof(manuf_data)-2] = bd_addr[1];
   manuf_data[ sizeof(manuf_data)-1] = bd_addr[0];
-  
+
   /**
    * Write Identity root key used to derive LTK and CSRK 
    */
@@ -844,11 +845,11 @@ static void Ble_Hci_Gap_Gatt_Init(void){
    */
   BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode = CFG_MITM_PROTECTION;
   BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data_Present = 0;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin = 8;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax = 16;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin = 1;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin = 111111;
-  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode = 1;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin = CFG_ENCRYPTION_KEY_SIZE_MIN;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax = CFG_ENCRYPTION_KEY_SIZE_MAX;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin = CFG_USED_FIXED_PIN;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin = CFG_FIXED_PIN;
+  BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode = CFG_BONDING_MODE;
   for (index = 0; index < 16; index++)
   {
     BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.OOB_Data[index] = (uint8_t) index;
@@ -856,14 +857,14 @@ static void Ble_Hci_Gap_Gatt_Init(void){
 
   aci_gap_set_authentication_requirement(BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode,
-                                         1,
-                                         0,
+                                         CFG_SC_SUPPORT,
+                                         CFG_KEYPRESS_NOTIFICATION_SUPPORT,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin,
                                          BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin,
-                                         0
-                                        );
+                                         PUBLIC_ADDR
+                                         );
 
   /**
    * Initialize whitelist
@@ -928,9 +929,9 @@ static void Adv_Request(APP_BLE_ConnStatus_t New_Status)
         BleApplicationContext.BleApplicationContext_legacy.advtServUUID,
         0,
         0);
+
     /* Update Advertising data */
     ret = aci_gap_update_adv_data(sizeof(manuf_data), (uint8_t*) manuf_data);
-
     if (ret == BLE_STATUS_SUCCESS)
     {
       if (New_Status == APP_BLE_FAST_ADV)
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/ble_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/ble_conf.h
index 2e0c37951..faf09232f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/ble_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/ble_conf.h
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/ble_dbg_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/ble_dbg_conf.h
index a24660c50..803855d69 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/ble_dbg_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/ble_dbg_conf.h
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/hrs_app.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/hrs_app.c
index e3f77ee03..b4aca3c3c 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/hrs_app.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/App/hrs_app.c
@@ -75,7 +75,7 @@ const osThreadAttr_t HrsProcess_attr = {
     .cb_size = CFG_HRS_PROCESS_CB_SIZE,
     .stack_mem = CFG_HRS_PROCESS_STACK_MEM,
     .priority = CFG_HRS_PROCESS_PRIORITY,
-    .stack_size = CFG_HRS_PROCESS_STACk_SIZE
+    .stack_size = CFG_HRS_PROCESS_STACK_SIZE
 };
 
 /* USER CODE BEGIN PV */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/Target/hw_ipcc.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/Target/hw_ipcc.c
index a0d8b3b5b..c6e1ca97a 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/Target/hw_ipcc.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/STM32_WPAN/Target/hw_ipcc.c
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/SW4STM32/BLE_HeartRateFreeRTOS/.project b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/SW4STM32/BLE_HeartRateFreeRTOS/.project
index 454bf5c4b..cef35ffbb 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/SW4STM32/BLE_HeartRateFreeRTOS/.project
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/SW4STM32/BLE_HeartRateFreeRTOS/.project
@@ -65,6 +65,11 @@
 			1
 			PARENT-2-PROJECT_LOC/Core/Src/main.c
 		
+		
+			Application/Core/app_debug.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/app_debug.c
+		
 		
 			Application/Core/stm32_lpm_if.c
 			1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/SW4STM32/BLE_HeartRateFreeRTOS/stm32wb55xx_flash_cm4.ld b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/SW4STM32/BLE_HeartRateFreeRTOS/stm32wb55xx_flash_cm4.ld
index a9ccd801e..7ac9a391f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/SW4STM32/BLE_HeartRateFreeRTOS/stm32wb55xx_flash_cm4.ld
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/SW4STM32/BLE_HeartRateFreeRTOS/stm32wb55xx_flash_cm4.ld
@@ -50,7 +50,7 @@ ENTRY(Reset_Handler)
 _estack = 0x20030000;    /* end of RAM */
 /* Generate a link error if heap and stack don't fit into RAM */
 _Min_Heap_Size = 0x400;      /* required amount of heap  */
-_Min_Stack_Size = 0x1000; /* required amount of stack */
+_Min_Stack_Size = 0x1000;   /* required amount of stack */
 
 /* Specify the memory areas */
 MEMORY
@@ -181,7 +181,7 @@ SECTIONS
   .ARM.attributes 0       : { *(.ARM.attributes) }
    MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
    MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
-   MB_MEM2                : { *(MB_MEM2) } >RAM_SHARED  
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
 }
 
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/SW4STM32/startup_stm32wb55xx_cm4.s b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/SW4STM32/startup_stm32wb55xx_cm4.s
index 023c1b016..f79eec117 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/SW4STM32/startup_stm32wb55xx_cm4.s
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRateFreeRTOS/SW4STM32/startup_stm32wb55xx_cm4.s
@@ -44,21 +44,29 @@ defined in linker script */
 .word	_sbss
 /* end address for the .bss section. defined in linker script */
 .word	_ebss
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
   movs r3, #0
-  b	LoopCopyDataInit
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
 
+.section  .text.data_initializers
 CopyDataInit:
   ldr r4, [r2, r3]
   str r4, [r0, r3]
@@ -67,21 +75,31 @@ CopyDataInit:
 LoopCopyDataInit:
   adds r4, r0, r3
   cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
+  bcc  CopyDataInit
+  bx lr
 
 FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
+  str  r3, [r0]
+  adds r0, r0, #4
 
 LoopFillZerobss:
-  cmp r2, r4
+  cmp r0, r1
   bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Binary/BLE_HeartRate_ota_reference.bin b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Binary/BLE_HeartRate_ota_reference.bin
index 73c65bcdf..e892b7207 100644
Binary files a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Binary/BLE_HeartRate_ota_reference.bin and b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Binary/BLE_HeartRate_ota_reference.bin differ
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_debug.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_debug.h
new file mode 100644
index 000000000..13485c16b
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Inc/app_debug.h
@@ -0,0 +1,45 @@
+
+/**
+  ******************************************************************************
+  * @file    app_debug.h
+  * @author  MCD Application Team
+  * @brief   Interface to support debug in the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+  /* Exported types ------------------------------------------------------------*/
+  /* Exported constants --------------------------------------------------------*/
+  /* External variables --------------------------------------------------------*/
+  /* Exported macros -----------------------------------------------------------*/
+  /* Exported functions ------------------------------------------------------- */
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Inc/hw_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Inc/hw_conf.h
index 6733a683f..f4f55affa 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Inc/hw_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Inc/hw_conf.h
@@ -24,9 +24,37 @@
 #define HW_CONF_H
 
 /******************************************************************************
- * Semaphores
- * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
- *****************************************************************************/
+* Semaphores
+* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
+*****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
 /* Index of the semaphore used to manage the entry Stop Mode procedure */
 #define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Src/app_debug.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Src/app_debug.c
new file mode 100644
index 000000000..246173ae6
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Src/app_debug.c
@@ -0,0 +1,349 @@
+/**
+ ******************************************************************************
+ * @file    app_debug.c
+ * @author  MCD Application Team
+ * @brief   Debug capabilities
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+  HW_UART_Init(CFG_DEBUG_TRACE_UART);
+  return;
+}
+
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Src/app_entry.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Src/app_entry.c
index 9d38af323..eab85057d 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Src/app_entry.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Src/app_entry.c
@@ -29,7 +29,7 @@
 #include "stm32_seq.h"
 #include "shci_tl.h"
 #include "stm32_lpm.h"
-#include "dbg_trace.h"
+#include "app_debug.h"
 
 /* Private includes -----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
@@ -66,7 +66,6 @@ PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t BleSpareEvtBuffer[sizeof(TL_
 
 /* Private functions prototypes-----------------------------------------------*/
 static void SystemPower_Config( void );
-static void Init_Debug( void );
 static void appe_Tl_Init( void );
 static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status );
 static void APPE_SysUserEvtRx( void * pPayload );
@@ -91,7 +90,7 @@ void APPE_Init( void )
   HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
 
 /* USER CODE BEGIN APPE_Init_1 */
-  Init_Debug();
+  APPD_Init();
   
   /**
    * The Standby mode should not be entered before the initialization is over
@@ -124,48 +123,6 @@ void APPE_Init( void )
  * LOCAL FUNCTIONS
  *
  *************************************************************/
-static void Init_Debug( void )
-{
-#if (CFG_DEBUGGER_SUPPORTED == 1)
-  /**
-   * Keep debugger enabled while in any low power mode
-   */
-  HAL_DBGMCU_EnableDBGSleepMode();
-
-  /***************** ENABLE DEBUGGER *************************************/
-  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-  LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-
-#else
-
-  GPIO_InitTypeDef gpio_config = {0};
-
-  gpio_config.Pull = GPIO_NOPULL;
-  gpio_config.Mode = GPIO_MODE_ANALOG;
-
-  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOA, &gpio_config);
-  __HAL_RCC_GPIOA_CLK_DISABLE();
-
-  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOB, &gpio_config);
-  __HAL_RCC_GPIOB_CLK_DISABLE();
-
-  HAL_DBGMCU_DisableDBGSleepMode();
-  HAL_DBGMCU_DisableDBGStopMode();
-  HAL_DBGMCU_DisableDBGStandbyMode();
-
-#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
-
-#if(CFG_DEBUG_TRACE != 0)
-  DbgTraceInit();
-#endif
-
-  return;
-}
-
 /**
  * @brief  Configure the system for power optimization
  *
@@ -239,7 +196,7 @@ static void APPE_SysUserEvtRx( void * pPayload )
 {
   UNUSED(pPayload);
   /* Traces channel initialization */
-  TL_TRACES_Init( );
+  APPD_EnableCPU2();
 
   APP_BLE_Init( );
   UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE);
@@ -324,34 +281,6 @@ void shci_cmd_resp_wait(uint32_t timeout)
   return;
 }
 
-/**
-  * @brief  Initialisation of the trace mechanism
-  * @param  None
-  * @retval None
-  */
-#if(CFG_DEBUG_TRACE != 0)
-void DbgOutputInit( void )
-{
-    MX_USART1_UART_Init();
-
-  return;
-}
-
-/**
-  * @brief  Management of the traces
-  * @param  p_data : data
-  * @param  size : size
-  * @param  call-back :
-  * @retval None
-  */
-void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
-{
-  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
-
-  return;
-}
-#endif
-
 /* USER CODE BEGIN FD_WRAP_FUNCTIONS */
 void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin )
 {
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Src/stm32_lpm_if.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Src/stm32_lpm_if.c
index f024b61e3..1418e0a36 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Src/stm32_lpm_if.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/Core/Src/stm32_lpm_if.c
@@ -70,6 +70,13 @@ static void Switch_On_HSI( void );
 void PWR_EnterOffMode( void )
 {
 /* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
   /************************************************************************************
    * ENTER OFF MODE
    ***********************************************************************************/
@@ -106,6 +113,8 @@ void PWR_ExitOffMode( void )
 {
 /* USER CODE BEGIN PWR_ExitOffMode */
 
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitOffMode */
 }
 
@@ -118,6 +127,16 @@ void PWR_ExitOffMode( void )
 void PWR_EnterStopMode( void )
 {
 /* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
   /**
    * This function is called from CRITICAL SECTION
    */
@@ -202,6 +221,9 @@ void PWR_ExitStopMode( void )
 
   /* Release RCC semaphore */
   LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitStopMode */
 }
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/EWARM/BLE_HeartRate_ota.ewp b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/EWARM/BLE_HeartRate_ota.ewp
index 1be214d13..7cf02ef38 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/EWARM/BLE_HeartRate_ota.ewp
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/EWARM/BLE_HeartRate_ota.ewp
@@ -1052,6 +1052,9 @@
                 
                     $PROJ_DIR$\..\Core\Src\app_entry.c
                 
+                
+                    $PROJ_DIR$\..\Core\Src\app_debug.c
+                
                 
                     $PROJ_DIR$\..\Core\Src\stm32_lpm_if.c
                 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/MDK-ARM/BLE_HeartRate_ota.uvprojx b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/MDK-ARM/BLE_HeartRate_ota.uvprojx
index 5dbe65ca4..762286837 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/MDK-ARM/BLE_HeartRate_ota.uvprojx
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/MDK-ARM/BLE_HeartRate_ota.uvprojx
@@ -417,6 +417,11 @@
               1
               ../Core/Src/main.c
             
+            
+              app_debug.c
+              1
+              ../Core/Src/app_debug.c
+            
             
               stm32wbxx_hal_msp.c
               1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/MDK-ARM/startup_stm32wb55xx_cm4.s b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/MDK-ARM/startup_stm32wb55xx_cm4.s
index c0ebe4bbd..c92be083e 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/MDK-ARM/startup_stm32wb55xx_cm4.s
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/MDK-ARM/startup_stm32wb55xx_cm4.s
@@ -14,8 +14,7 @@
 ;******************************************************************************
 ;* @attention
 ;*
-;* Copyright (c) 2019 STMicroelectronics. All rights reserved. 
-
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
 ;*
 ;* This software component is licensed by ST under BSD 3-Clause license,
 ;* the "License"; You may not use this file except in compliance with the 
@@ -51,11 +50,12 @@ __heap_limit
                 PRESERVE8
                 THUMB
 
+
 ; Vector Table Mapped to Address 0 at Reset
                 AREA    RESET, DATA, READONLY
-               ; EXPORT  __Vectors
-               ; EXPORT  __Vectors_End
-                ;EXPORT  __Vectors_Size
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
 
 __Vectors       DCD     __initial_sp              ; Top of Stack
         DCD     Reset_Handler                     ; Reset Handler
@@ -138,14 +138,10 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
         DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
         DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
         DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
-		DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
 
 __Vectors_End
 
- AREA    INFO, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
 __Vectors_Size  EQU  __Vectors_End - __Vectors
 
                 AREA    |.text|, CODE, READONLY
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/SW4STM32/BLE_HeartRate_ota/.project b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/SW4STM32/BLE_HeartRate_ota/.project
index 97b15e5a1..4048cd373 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/SW4STM32/BLE_HeartRate_ota/.project
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/SW4STM32/BLE_HeartRate_ota/.project
@@ -59,6 +59,11 @@
 			1
 			PARENT-2-PROJECT_LOC/Core/Src/main.c
 		
+    
+			Application/User/Core/app_debug.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/app_debug.c
+		
     
 			Application/User/Core/stm32wbxx_hal_msp.c
 			1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/SW4STM32/BLE_HeartRate_ota/stm32wb55xx_flash_cm4.ld b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/SW4STM32/BLE_HeartRate_ota/stm32wb55xx_flash_cm4.ld
index 931a91b27..79aadcf6d 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/SW4STM32/BLE_HeartRate_ota/stm32wb55xx_flash_cm4.ld
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/SW4STM32/BLE_HeartRate_ota/stm32wb55xx_flash_cm4.ld
@@ -11,7 +11,7 @@
 **
 **  Environment : System Workbench for MCU
 **
-**  Distribution: The file is distributed as is, without any warranty
+**  Distribution: The file is distributed “as is,” without any warranty
 **                of any kind.
 **
 *****************************************************************************
@@ -50,7 +50,7 @@ ENTRY(Reset_Handler)
 _estack = 0x20030000;    /* end of RAM */
 /* Generate a link error if heap and stack don't fit into RAM */
 _Min_Heap_Size = 0x400;      /* required amount of heap  */
-_Min_Stack_Size = 0x1000; /* required amount of stack */
+_Min_Stack_Size = 0x1000;   /* required amount of stack */
 
 /* Specify the memory areas */
 MEMORY
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/readme.txt b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/readme.txt
index aa78bc95d..29c0d71e6 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/readme.txt
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_HeartRate_ota/readme.txt
@@ -89,6 +89,8 @@ Wireless Coprocessor binary.
 In order to make the program work, you must do the following:
  - Open your toolchain 
  - Rebuild all files and flash the board with the executable file
+   [Warning: not use CMSIS startup_stm32wb55xx_cm4.s to compile under Keil toolchain as specific 
+    DCD offset added for OTA application]
  - OR use the BLE_HeartRate_ota_reference.bin from Binary directory
    - to be flashed at 0x0800 7000
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Inc/app_debug.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Inc/app_debug.h
new file mode 100644
index 000000000..13485c16b
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Inc/app_debug.h
@@ -0,0 +1,45 @@
+
+/**
+  ******************************************************************************
+  * @file    app_debug.h
+  * @author  MCD Application Team
+  * @brief   Interface to support debug in the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+  /* Exported types ------------------------------------------------------------*/
+  /* Exported constants --------------------------------------------------------*/
+  /* External variables --------------------------------------------------------*/
+  /* Exported macros -----------------------------------------------------------*/
+  /* Exported functions ------------------------------------------------------- */
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Inc/hw_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Inc/hw_conf.h
index 91bc7cd83..18d8e28f8 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Inc/hw_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Inc/hw_conf.h
@@ -23,9 +23,37 @@
 #define __HW_CONF_H
 
 /******************************************************************************
- * Semaphores
- * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
- *****************************************************************************/
+* Semaphores
+* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
+*****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
 /* Index of the semaphore used to manage the entry Stop Mode procedure */
 #define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Src/app_debug.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Src/app_debug.c
new file mode 100644
index 000000000..246173ae6
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Src/app_debug.c
@@ -0,0 +1,349 @@
+/**
+ ******************************************************************************
+ * @file    app_debug.c
+ * @author  MCD Application Team
+ * @brief   Debug capabilities
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+  HW_UART_Init(CFG_DEBUG_TRACE_UART);
+  return;
+}
+
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Src/app_entry.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Src/app_entry.c
index 62da533ad..34a9acb6d 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Src/app_entry.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Src/app_entry.c
@@ -33,7 +33,7 @@
 #include "stm32_lpm.h"
 
 
-#include "dbg_trace.h"
+#include "app_debug.h"
 
 
 /* Private typedef -----------------------------------------------------------*/
@@ -50,7 +50,6 @@ PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t	BleSpareEvtBuffer[sizeof(TL_
 /* Global variables ----------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
 static void SystemPower_Config( void );
-static void Init_Debug( void );
 static void appe_Tl_Init( void );
 static void Led_Init( void );
 static void Button_Init( void );
@@ -64,7 +63,7 @@ void APPE_Init( void )
   
   HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
 
-  Init_Debug();
+  APPD_Init();
 
   /**
    * The Standby mode should not be entered before the initialization is over
@@ -92,48 +91,6 @@ void APPE_Init( void )
  * LOCAL FUNCTIONS
  *
  *************************************************************/
-static void Init_Debug( void )
-{
-#if (CFG_DEBUGGER_SUPPORTED == 1)
-  /**
-   * Keep debugger enabled while in any low power mode
-   */
-  HAL_DBGMCU_EnableDBGSleepMode();
-
-  /***************** ENABLE DEBUGGER *************************************/
-  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-  LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-
-#else
-
-  GPIO_InitTypeDef gpio_config = {0};
-
-  gpio_config.Pull = GPIO_NOPULL;
-  gpio_config.Mode = GPIO_MODE_ANALOG;
-
-  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOA, &gpio_config);
-  __HAL_RCC_GPIOA_CLK_DISABLE();
-
-  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOB, &gpio_config);
-  __HAL_RCC_GPIOB_CLK_DISABLE();
-
-  HAL_DBGMCU_DisableDBGSleepMode();
-  HAL_DBGMCU_DisableDBGStopMode();
-  HAL_DBGMCU_DisableDBGStandbyMode();
-
-#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
-
-#if(CFG_DEBUG_TRACE != 0)
-  DbgTraceInit();
-#endif
-
-  return;
-}
-
 /**
  * @brief  Configure the system for power optimization
  *
@@ -239,7 +196,7 @@ static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status )
 static void APPE_SysUserEvtRx( void * pPayload )
 {
   /**< Traces channel initialization */
-  TL_TRACES_Init( );
+  APPD_EnableCPU2();
 
   UTIL_LPM_SetOffMode(1 << CFG_LPM_APP, UTIL_LPM_ENABLE);
 
@@ -309,22 +266,4 @@ void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin )
   return;
 }
 
-
-#if(CFG_DEBUG_TRACE != 0)
-void DbgOutputInit( void )
-{
-  HW_UART_Init(CFG_DEBUG_TRACE_UART);
-  return;
-}
-
-
-void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
-{
-  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
-
-  return;
-}
-#endif
-
-
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Src/stm32_lpm_if.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Src/stm32_lpm_if.c
index f024b61e3..1418e0a36 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Src/stm32_lpm_if.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/Core/Src/stm32_lpm_if.c
@@ -70,6 +70,13 @@ static void Switch_On_HSI( void );
 void PWR_EnterOffMode( void )
 {
 /* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
   /************************************************************************************
    * ENTER OFF MODE
    ***********************************************************************************/
@@ -106,6 +113,8 @@ void PWR_ExitOffMode( void )
 {
 /* USER CODE BEGIN PWR_ExitOffMode */
 
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitOffMode */
 }
 
@@ -118,6 +127,16 @@ void PWR_ExitOffMode( void )
 void PWR_EnterStopMode( void )
 {
 /* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
   /**
    * This function is called from CRITICAL SECTION
    */
@@ -202,6 +221,9 @@ void PWR_ExitStopMode( void )
 
   /* Release RCC semaphore */
   LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitStopMode */
 }
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/EWARM/BLE_Hid.ewp b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/EWARM/BLE_Hid.ewp
index 6e224ab07..27f7559ca 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/EWARM/BLE_Hid.ewp
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/EWARM/BLE_Hid.ewp
@@ -1053,6 +1053,9 @@
             
                 $PROJ_DIR$\..\Core\Src\app_entry.c
             
+            
+                $PROJ_DIR$\..\Core\Src\app_debug.c
+            
             
                 $PROJ_DIR$\..\Core\Src\hw_timerserver.c
             
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/EWARM/startup_stm32wb55xx_cm4.s b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/EWARM/startup_stm32wb55xx_cm4.s
index 79b0e7edd..1f886ff59 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/EWARM/startup_stm32wb55xx_cm4.s
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/EWARM/startup_stm32wb55xx_cm4.s
@@ -1,4 +1,4 @@
-;/********************* COPYRIGHT(c) 2019 STMicroelectronics ********************
+;******************************************************************************
 ;* File Name          : startup_stm32wb55xx_cm4.s
 ;* Author             : MCD Application Team
 ;* Description        : M4 core vector table of the STM32WB55xx devices for the
@@ -13,31 +13,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
 ;*
-;*******************************************************************************
+;******************************************************************************
 ;
 ;
 ; The modules in this file are included in the libraries, and may be replaced
@@ -86,10 +73,10 @@ __vector_table
         DCD     PendSV_Handler                    ; PendSV Handler
         DCD     SysTick_Handler                   ; SysTick Handler
 
-         ; External Interrupts
+        ; External Interrupts
         DCD     WWDG_IRQHandler                   ; Window WatchDog
-        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
-        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
         DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
         DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
         DCD     RCC_IRQHandler                    ; RCC Interrupt
@@ -129,7 +116,7 @@ __vector_table
         DCD     TSC_IRQHandler                    ; TSC Interrupt
         DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
         DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
-        DCD     USB_FS_WKUP_CRS_IRQHandler        ; USB Full speed wakeup
+        DCD     CRS_IRQHandler                    ; CRS interrupt
         DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
         DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
         DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
@@ -156,6 +143,7 @@ __vector_table
 ;; Default interrupt handlers.
 ;;
         THUMB
+
         PUBWEAK Reset_Handler
         SECTION .text:CODE:NOROOT:REORDER(2)
 Reset_Handler
@@ -419,10 +407,10 @@ EXTI15_10_IRQHandler
 RTC_Alarm_IRQHandler
         B RTC_Alarm_IRQHandler
 
-        PUBWEAK USB_FS_WKUP_CRS_IRQHandler
+        PUBWEAK CRS_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
-USB_FS_WKUP_CRS_IRQHandler
-        B USB_FS_WKUP_CRS_IRQHandler
+CRS_IRQHandler
+        B CRS_IRQHandler
 
         PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
@@ -523,6 +511,7 @@ DMA2_Channel7_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMAMUX1_OVR_IRQHandler
         B DMAMUX1_OVR_IRQHandler
+
         END
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/MDK-ARM/BLE_Hid.uvprojx b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/MDK-ARM/BLE_Hid.uvprojx
index 5b02b78c4..dc814e282 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/MDK-ARM/BLE_Hid.uvprojx
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/MDK-ARM/BLE_Hid.uvprojx
@@ -406,6 +406,11 @@
               1
               ../Core/Src/main.c
                 
+            
+              app_debug.c
+              1
+              ../Core/Src/app_debug.c
+            
             
               stm32wbxx_it.c
               1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/SW4STM32/BLE_Hid/.project b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/SW4STM32/BLE_Hid/.project
index 95116fc82..3bb9c39c1 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/SW4STM32/BLE_Hid/.project
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/SW4STM32/BLE_Hid/.project
@@ -59,6 +59,11 @@
 			1
 			PARENT-2-PROJECT_LOC/Core/Src/main.c
 		
+    
+			Application/Core/app_debug.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/app_debug.c
+		
     
 			Application/Core/stm32wbxx_it.c
 			1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/SW4STM32/BLE_Hid/stm32wb55xx_flash_cm4.ld b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/SW4STM32/BLE_Hid/stm32wb55xx_flash_cm4.ld
index a9ccd801e..7ac9a391f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/SW4STM32/BLE_Hid/stm32wb55xx_flash_cm4.ld
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/SW4STM32/BLE_Hid/stm32wb55xx_flash_cm4.ld
@@ -50,7 +50,7 @@ ENTRY(Reset_Handler)
 _estack = 0x20030000;    /* end of RAM */
 /* Generate a link error if heap and stack don't fit into RAM */
 _Min_Heap_Size = 0x400;      /* required amount of heap  */
-_Min_Stack_Size = 0x1000; /* required amount of stack */
+_Min_Stack_Size = 0x1000;   /* required amount of stack */
 
 /* Specify the memory areas */
 MEMORY
@@ -181,7 +181,7 @@ SECTIONS
   .ARM.attributes 0       : { *(.ARM.attributes) }
    MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
    MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
-   MB_MEM2                : { *(MB_MEM2) } >RAM_SHARED  
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
 }
 
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/SW4STM32/startup_stm32wb55xx_cm4.s b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/SW4STM32/startup_stm32wb55xx_cm4.s
index 023c1b016..f79eec117 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/SW4STM32/startup_stm32wb55xx_cm4.s
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Hid/SW4STM32/startup_stm32wb55xx_cm4.s
@@ -44,21 +44,29 @@ defined in linker script */
 .word	_sbss
 /* end address for the .bss section. defined in linker script */
 .word	_ebss
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
   movs r3, #0
-  b	LoopCopyDataInit
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
 
+.section  .text.data_initializers
 CopyDataInit:
   ldr r4, [r2, r3]
   str r4, [r0, r3]
@@ -67,21 +75,31 @@ CopyDataInit:
 LoopCopyDataInit:
   adds r4, r0, r3
   cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
+  bcc  CopyDataInit
+  bx lr
 
 FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
+  str  r3, [r0]
+  adds r0, r0, #4
 
 LoopFillZerobss:
-  cmp r2, r4
+  cmp r0, r1
   bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Inc/app_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Inc/app_conf.h
index cf9898afa..4b654f07b 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Inc/app_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Inc/app_conf.h
@@ -35,7 +35,7 @@
 /**
  * Define Tx Power
  */   
-#define CFG_TX_POWER                      (0x1D) /**< +4 dBm */
+#define CFG_TX_POWER                      (0x18) /**< +0 dBm */
    
 /**
  * Define Advertising parameters
@@ -120,7 +120,7 @@
 
 #define CFG_MAX_CONNECTION      1
 
-#define  RADIO_ACTIVITY_EVENT   0
+#define  RADIO_ACTIVITY_EVENT   1
    
 
 #define CONN_L(x) ((int)((x)/0.625f))
@@ -280,8 +280,8 @@
 /**
  * Select UART interfaces
  */
-#define CFG_DEBUG_TRACE_UART              hw_uart1
-#define CFG_CONSOLE_MENU		hw_lpuart1
+#define CFG_DEBUG_TRACE_UART                                            hw_uart1
+#define CFG_CONSOLE_MENU                                              hw_lpuart1
 
 /******************************************************************************
  * USB interface
@@ -299,7 +299,7 @@
  *  When set to 1, the low power mode is enable
  *  When set to 0, the device stays in RUN mode
  */
-#define CFG_LPM_SUPPORTED   1
+#define CFG_LPM_SUPPORTED   0
 
 /******************************************************************************
  * Timer Server
@@ -400,17 +400,17 @@ typedef enum
  * keep debugger enabled while in any low power mode when set to 1
  * should be set to 0 in production
  */
-#define CFG_DEBUGGER_SUPPORTED    1
+#define CFG_DEBUGGER_SUPPORTED    0
 
 /**
  * When set to 1, the traces are enabled in the BLE services
  */
-#define CFG_DEBUG_BLE_TRACE     1
+#define CFG_DEBUG_BLE_TRACE     0
 
 /**
  * Enable or Disable traces in application
  */
-#define CFG_DEBUG_APP_TRACE     1
+#define CFG_DEBUG_APP_TRACE     0
 
 #if (CFG_DEBUG_APP_TRACE != 0)
 #define APP_DBG_MSG                 PRINT_MESG_DBG
@@ -423,12 +423,14 @@ typedef enum
 #define CFG_DEBUG_TRACE             1
 #endif
 
+#if 1
 #if (CFG_DEBUG_TRACE != 0)
 #undef CFG_LPM_SUPPORTED
 #undef CFG_DEBUGGER_SUPPORTED
 #define CFG_LPM_SUPPORTED         0
 #define CFG_DEBUGGER_SUPPORTED      1
 #endif
+#endif
 
 /**
  * When CFG_DEBUG_TRACE_FULL is set to 1, the trace are output with the API name, the file name and the line number
@@ -485,6 +487,9 @@ typedef enum
   CFG_TASK_MESH_REQ_ID,
   CFG_TASK_MESH_BEACON_REQ_ID,
   CFG_TASK_MESH_UART_RX_REQ_ID,
+  CFG_TASK_APPLI_REQ_ID,
+  CFG_TASK_MESH_SW1_REQ_ID,
+  CFG_TASK_MESH_LPN_REQ_ID,
   
   CFG_LAST_TASK_ID_WITH_HCICMD, /**< Shall be LAST in the list */
 } CFG_Task_Id_With_HCI_Cmd_t;
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Inc/hw_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Inc/hw_conf.h
index 130af82bc..1e2d7a616 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Inc/hw_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Inc/hw_conf.h
@@ -23,9 +23,37 @@
 #define __HW_CONF_H
 
 /******************************************************************************
- * Semaphores
- * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
- *****************************************************************************/
+* Semaphores
+* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
+*****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
 /* Index of the semaphore used to manage the entry Stop Mode procedure */
 #define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Inc/hw_flash.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Inc/hw_flash.h
new file mode 100644
index 000000000..18c088d3e
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Inc/hw_flash.h
@@ -0,0 +1,87 @@
+/**
+******************************************************************************
+* @file    hw_flash.h
+* @brief   Header for hw_flash.c module
+******************************************************************************
+* @attention
+*
+* 
    © Copyright (c) 2019 STMicroelectronics. 
+* All rights reserved.
    
+*
+* This software component is licensed by ST under BSD 3-Clause license,
+* the "License"; You may not use this file except in compliance with the 
+* License. You may obtain a copy of the License at:
+*                        opensource.org/licenses/BSD-3-Clause
+*
+******************************************************************************
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HW_FLASH_H
+#define __HW_FLASH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Write 64 bits double word in FLASH
+ *
+ * @param  FLASH destination address 
+ * @param  64 bits double word data 
+ * @retval result
+ */
+MOBLE_RESULT HW_FLASH_Write(uint32_t address, uint64_t data);
+
+/**
+ * @brief Erase FLASH page
+ *
+ * @param  address of FLASH page 
+ * @param  number of page 
+ * @param  interrupt not used 
+ * @retval result
+ */
+MOBLE_RESULT HW_FLASH_Erase(uint32_t page, uint16_t n, int interrupt);
+
+#if 0
+/**
+ * @brief Get Option Byte IPCC buffer address
+ *
+ * @param  None 
+ * @retval Option Byte IPCC buffer address
+ */
+uint32_t HW_FLASH_OB_GetIPCCBufferAddr(void);
+
+/**
+ * @brief Get Option Byte SFSA
+ *
+ * @param  None 
+ * @retval Option Byte SFSA
+ */
+uint32_t HW_FLASH_OB_GetSFSA(void);
+
+/**
+ * @brief Get Option Byte SBSRA
+ *
+ * @param  None 
+ * @retval Option Byte SBSRA
+ */
+uint32_t HW_FLASH_OB_GetSBRSA(void);
+
+/**
+ * @brief Get Option Byte SNBRSA
+ *
+ * @param  None 
+ * @retval Option Byte SNBRSA
+ */
+uint32_t HW_FLASH_OB_GetSNBRSA(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__HW_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Inc/lp_timer.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Inc/lp_timer.h
new file mode 100644
index 000000000..41f226faf
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Inc/lp_timer.h
@@ -0,0 +1,60 @@
+/**
+******************************************************************************
+* @file    lp_timer.h
+* @brief   Header for lp_timer.c module
+******************************************************************************
+* @attention
+*
+* 
    © Copyright (c) 2019 STMicroelectronics. 
+* All rights reserved.
    
+*
+* This software component is licensed by ST under BSD 3-Clause license,
+* the "License"; You may not use this file except in compliance with the 
+* License. You may obtain a copy of the License at:
+*                        opensource.org/licenses/BSD-3-Clause
+*
+******************************************************************************
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __LP_TIMER_H
+#define __LP_TIMER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+  /**
+   * @brief Initialize the low power timer
+   *
+   * @param  None
+   * @retval None
+   */
+  void LpTimerInit(void);
+
+  /**
+   * @brief  Request to start a low power timer ( running is stop mode )
+   *
+   * @param  time_to_sleep : in ms
+   * @retval None
+   */
+  void LpTimerStart(uint32_t time_to_sleep);
+
+  /**
+   * @brief  Read how long the timer has run
+   *
+   * @param  None
+   * @retval The time elapsed in ms
+   */
+  uint32_t LpGetElapsedTime(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__LP_TIMER_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/app_debug.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/app_debug.c
index 9a5d338a0..246173ae6 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/app_debug.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/app_debug.c
@@ -36,23 +36,9 @@ typedef PACKED_STRUCT
   uint8_t reserved;
 } APPD_GpioConfig_t;
 
-typedef PACKED_STRUCT
-{
-  uint8_t thread_config;
-  uint8_t ble_config;
-  uint8_t mac_802_15_4;
-  uint8_t reserved;
-} APPD_TracesConfig_t;
-
-typedef PACKED_STRUCT
-{
-  uint8_t ble_dtb_cfg;
-  uint8_t reserved[3];
-} APPD_GeneralConfig_t;
-
 /* Private defines -----------------------------------------------------------*/
 #define GPIO_NBR_OF_RF_SIGNALS                  9
-#define GPIO_CFG_NBR_OF_FEATURES                32
+#define GPIO_CFG_NBR_OF_FEATURES                34
 #define NBR_OF_TRACES_CONFIG_PARAMETERS         4
 #define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
 
@@ -63,8 +49,8 @@ typedef PACKED_STRUCT
 
 /* Private macros ------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static APPD_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
-PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static APPD_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
 
 /**
  * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
@@ -74,39 +60,44 @@ PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static APPD_GeneralConfig_t APPD_GeneralCon
  */
 static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
 {
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-/* USER DEFINED IN M0 */
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
-    { GPIOA, LL_GPIO_PIN_0, 0, 0},
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
 };
 
 /**
@@ -119,15 +110,15 @@ static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
 #if( BLE_DTB_CFG == 7)
 static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
 {
-    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 */
-    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 */
-    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 */
-    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 */
-    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 */
-    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 */
-    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 */
-    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 */
-    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 */
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
 };
 #endif
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/app_entry.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/app_entry.c
index 7655d360c..db8838a8f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/app_entry.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/app_entry.c
@@ -29,12 +29,16 @@
 #include "stm32_seq.h"
 #include "shci_tl.h"
 #include "stm32_lpm.h"
-#include "dbg_trace.h"
+#include "app_debug.h"
 
 #include "app_debug.h"
 
 #include "appli_mesh.h"
-   
+#include "appli_nvm.h"
+#include "pal_nvm.h"
+#include "lp_timer.h"
+#include "mesh_cfg.h"
+
 /* Private includes -----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
 
@@ -48,6 +52,18 @@ extern MOBLEUINT8 PowerOnOff_flag;
 #ifdef ENABLE_OCCUPANCY_SENSOR           
 extern MOBLEUINT8 Occupancy_Flag;
 #endif
+extern const void *mobleNvmBase; 
+extern const void *appNvmBase;
+extern const void *prvsnr_data;
+#if (LOW_POWER_FEATURE == 1)
+extern __IO uint32_t uwTick;
+extern HAL_TickFreqTypeDef uwTickFreq;
+#if ( CFG_LPM_SUPPORTED == 1)
+static uint32_t BleMesh_sleepTime;
+#endif
+extern volatile uint8_t BleProcessInit;
+#endif
+
 /* USER CODE BEGIN PTD */
 
 /* USER CODE END PTD */
@@ -92,9 +108,13 @@ static void Led_Init( void );
 static void Button_Init( void );
 /* USER CODE END PFP */
 
+uint8_t Mesh_Stop_Mode;
+
 /* Functions Definition ------------------------------------------------------*/
 void APPE_Init( void )
 {
+  MOBLEUINT32 last_user_flash_address = ((READ_BIT(FLASH->SFR, FLASH_SFR_SFSA) >> FLASH_SFR_SFSA_Pos) << 12) + FLASH_BASE;
+  
   SystemPower_Config(); /**< Configure the system Power Mode */
   
   HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
@@ -112,6 +132,16 @@ void APPE_Init( void )
 
   Button_Init();
   
+  mobleNvmBase = (const void *)(last_user_flash_address - NVM_SIZE);
+  appNvmBase   = (const void *)(last_user_flash_address - NVM_SIZE - APP_NVM_SIZE);
+  prvsnr_data  = (const void *)(last_user_flash_address - NVM_SIZE - APP_NVM_SIZE - PRVN_NVM_PAGE_SIZE);    
+  
+#if (LOW_POWER_FEATURE == 1)
+  /**
+   * Initialize the lp timer to be used when the systick is stopped in low power mode
+   */
+  LpTimerInit();
+#endif
   
 /* USER CODE END APPE_Init_1 */
   appe_Tl_Init();	/*  Initialize all transport layers */
@@ -197,6 +227,15 @@ static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status )
   return;
 }
 
+/**
+ * The type of the payload for a system user event is tSHCI_UserEvtRxParam
+ * When the system event is both :
+ *    - a ready event (subevtcode = SHCI_SUB_EVT_CODE_READY)
+ *    - reported by the FUS (sysevt_ready_rsp == RSS_FW_RUNNING)
+ * The buffer shall not be released
+ * ( eg ((tSHCI_UserEvtRxParam*)pPayload)->status shall be set to SHCI_TL_UserEventFlow_Disable )
+ * When the status is not filled, the buffer is released by default
+ */
 static void APPE_SysUserEvtRx( void * pPayload )
 {
   UNUSED(pPayload);
@@ -234,6 +273,7 @@ static void Button_Init( void )
 
   BSP_PB_Init(BUTTON_SW1, BUTTON_MODE_EXTI);
   BSP_PB_Init(BUTTON_SW2, BUTTON_MODE_EXTI);
+  BSP_PB_Init(BUTTON_SW3, BUTTON_MODE_EXTI);
 #endif
 
   return;
@@ -249,7 +289,31 @@ static void Button_Init( void )
 void UTIL_SEQ_Idle( void )
 {
 #if ( CFG_LPM_SUPPORTED == 1)
+#if (LOW_POWER_FEATURE == 1)
+  if(BleProcessInit != 0)
+  {
+    BleMesh_sleepTime = (uint32_t)BLEMesh_GetSleepDuration();
+
+    if (BleMesh_sleepTime > 0)
+    {
+      LpTimerStart(BleMesh_sleepTime);
+
+      UTIL_LPM_EnterLowPower( );
+
+      uwTick += (uwTickFreq*LpGetElapsedTime());
+    }
+    UTIL_SEQ_SetTask( 1<
    © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ *****************************************************************************
+ */
+
+#include "common.h"
+#include "stm32_seq.h"
+//#include "dbg_gpio.h"
+#include "hw_flash.h"
+#include "stm32wbxx_hal.h"
+
+static void HW_FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
+static void HW_FLASH_PageErase(uint32_t Page);
+//static void HW_FLASH_WaitEndOfOperation(void);
+
+/*****************************************************************************/
+
+MOBLE_RESULT HW_FLASH_Write(uint32_t address, uint64_t data)
+{
+  /* Enable EOP interrupt */
+ // __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
+
+ // __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+
+  HW_FLASH_Program_DoubleWord(address, data);
+
+ // HW_FLASH_WaitEndOfOperation();
+
+  /* Disable EOP interrupt */
+//  __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
+
+  /* Clear the PG bit once data has been written */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+
+  return (MOBLE_RESULT_SUCCESS);
+}
+
+/*****************************************************************************/
+
+MOBLE_RESULT HW_FLASH_Erase(uint32_t page, uint16_t n, int interrupt)
+{
+  UNUSED(interrupt);
+
+  uint32_t loop;
+
+  /* Enable EOP interrupt */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
+
+  for( loop = 0;  loop < n ; loop++)
+  {
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+
+    HW_FLASH_PageErase(page+loop);
+
+//    HW_FLASH_WaitEndOfOperation();
+  }
+
+  /* Disable EOP interrupt */
+  __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
+
+  /* Clear the page erase bit */
+  CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
+
+  return (MOBLE_RESULT_SUCCESS);
+}
+
+#if 0
+/*****************************************************************************/
+
+uint32_t HW_FLASH_OB_GetIPCCBufferAddr(void)
+{
+  return READ_BIT(FLASH->IPCCBR, FLASH_IPCCBR_IPCCDBA);
+}
+
+/*****************************************************************************/
+
+uint32_t HW_FLASH_OB_GetSFSA(void)
+{
+  return (READ_BIT(FLASH->SFR, FLASH_SFR_SFSA) >> FLASH_SFR_SFSA_Pos);
+}
+
+/*****************************************************************************/
+
+uint32_t HW_FLASH_OB_GetSBRSA(void)
+{
+  return (READ_BIT(FLASH->SRRVR, FLASH_SRRVR_SBRSA) >> FLASH_SRRVR_SBRSA_Pos);
+}
+
+/*****************************************************************************/
+
+uint32_t HW_FLASH_OB_GetSNBRSA(void)
+{
+  return (READ_BIT(FLASH->SRRVR, FLASH_SRRVR_SNBRSA) >> FLASH_SRRVR_SNBRSA_Pos);
+}
+#endif
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+
+/**
+ * This is a copy of FLASH_Program_DoubleWord() from the HAL
+ */
+static void HW_FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
+{
+//  DBG_GPIO_Gr2Set(DBG_GPIO_GR2_FLASH_WRITE);
+
+  /* Set PG bit */
+  SET_BIT(FLASH->CR, FLASH_CR_PG);
+
+  /* Program first word */
+  *(uint32_t *)Address = (uint32_t)Data;
+
+  /* Barrier to ensure programming is performed in 2 steps, in right order
+    (independently of compiler optimization behavior) */
+  __ISB();
+
+  /* Program second word */
+  *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U);
+
+//  DBG_GPIO_Gr2Reset(DBG_GPIO_GR2_FLASH_WRITE);
+}
+
+/**
+ * This is a copy of LASH_PageErase() from the HAL
+ */
+static void HW_FLASH_PageErase(uint32_t Page)
+{
+//  DBG_GPIO_Gr2Set(DBG_GPIO_GR2_FLASH_ERASE);
+
+  /* Proceed to erase the page */
+  MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page << FLASH_CR_PNB_Pos) | FLASH_CR_PER | FLASH_CR_STRT));
+
+//  DBG_GPIO_Gr2Set(DBG_GPIO_GR2_FLASH_ERASE);
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/hw_uart.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/hw_uart.c
index 8210fd7f3..cb97bd718 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/hw_uart.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/hw_uart.c
@@ -143,10 +143,10 @@ void (*HW_huart1TxCb)(void);
 #if (CFG_HW_LPUART1_ENABLED == 1)
     UART_HandleTypeDef hlpuart1 = {0};
 #if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
-DMA_HandleTypeDef HW_hdma_lpuart1_tx ={0};
+DMA_HandleTypeDef HW_hdma_hlpuart1_tx ={0};
 #endif
-void (*HW_lpuart1RxCb)(void);
-void (*HW_lpuart1TxCb)(void);
+void (*HW_hlpuart1RxCb)(void);
+void (*HW_hlpuart1TxCb)(void);
 #endif
 
 void HW_UART_Init(hw_uart_id_t hw_uart_id)
@@ -184,7 +184,7 @@ void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size,
     
 #if (CFG_HW_LPUART1_ENABLED == 1)
     case hw_lpuart1:
-                HW_UART_RX_IT(hlpuart1, LPUART1);
+      HW_UART_RX_IT(hlpuart1, LPUART1);
       break;
 #endif
     
@@ -207,7 +207,7 @@ void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size
     
 #if (CFG_HW_LPUART1_ENABLED == 1)
     case hw_lpuart1:
-                HW_UART_TX_IT(hlpuart1, LPUART1);
+      HW_UART_TX_IT(hlpuart1, LPUART1);
       break;
 #endif
     
@@ -291,7 +291,7 @@ hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint1
     
 #if (CFG_HW_LPUART1_ENABLED == 1)
     case hw_lpuart1:
-      HW_lpuart1TxCb = cb;
+      HW_hlpuart1TxCb = cb;
                 hlpuart1.Instance = LPUART1;
                 hal_status = HAL_UART_Transmit_DMA(&hlpuart1, p_data, size);
       break;
@@ -425,9 +425,9 @@ void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
     
 #if (CFG_HW_LPUART1_ENABLED == 1)
     case (uint32_t)LPUART1:
-      if(HW_lpuart1RxCb)
+      if(HW_hlpuart1RxCb)
       {
-        HW_lpuart1RxCb();
+        HW_hlpuart1RxCb();
       }
       break;
 #endif
@@ -454,9 +454,9 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
     
 #if (CFG_HW_LPUART1_ENABLED == 1)
     case (uint32_t)LPUART1:
-      if(HW_lpuart1TxCb)
+      if(HW_hlpuart1TxCb)
       {
-        HW_lpuart1TxCb();
+        HW_hlpuart1TxCb();
       }
       break;
 #endif
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/lp_timer.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/lp_timer.c
new file mode 100644
index 000000000..404bb2e3b
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/lp_timer.c
@@ -0,0 +1,134 @@
+/**
+ ***************************************************************************************
+  * File Name          : lp_timer.c
+  * Description        : Low power timer to be used within Mesh Application.
+ ***************************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/  
+#include "app_common.h"
+
+#include "lp_timer.h"
+
+/* Exported variables --------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void LpTimerCb(void);
+
+/* Private typedef -----------------------------------------------------------*/
+typedef struct
+{
+  uint32_t LpTimeLeftOnEntry;
+  uint8_t LpTimer_Id;
+} LpTimerContext_t;
+
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static LpTimerContext_t LpTimerContext;
+
+/* Functions Definition ------------------------------------------------------*/
+
+/**
+ * @brief Initialize the low power timer
+ *
+ * @param  None
+ * @retval None
+ */
+void LpTimerInit(void)
+{
+  (void) HW_TS_Create(CFG_TIM_PROC_ID_ISR, &(LpTimerContext.LpTimer_Id), hw_ts_SingleShot, LpTimerCb);
+
+  return;
+}
+
+/**
+ * @brief  Request to start a low power timer ( running is stop mode )
+ *
+ * @param  time_to_sleep : in ms
+ * @retval None
+ */
+void LpTimerStart(uint32_t time_to_sleep)
+{
+  /* Converts the number of ms into hw timer tick */
+  if(time_to_sleep > 0x400000)
+  {
+    time_to_sleep = time_to_sleep / (CFG_TS_TICK_VAL);
+    time_to_sleep *= 1000;
+  }
+  else
+  {
+    time_to_sleep *= 1000;
+    time_to_sleep = time_to_sleep / (CFG_TS_TICK_VAL);
+  }
+
+  HW_TS_Start(LpTimerContext.LpTimer_Id, time_to_sleep);
+
+  /**
+   * There might be other timers already running in the timer server that may elapse
+   * before this one.
+   * Store how long before the next event so that on wakeup, it will be possible to calculate
+   * how long the tick has been suppressed
+   */
+  LpTimerContext.LpTimeLeftOnEntry = HW_TS_RTC_ReadLeftTicksToCount();
+
+  return;
+}
+
+/**
+ * @brief  Read how long the timer has run
+ *
+ * @param  None
+ * @retval The time elapsed in ms
+ */
+uint32_t LpGetElapsedTime(void)
+{
+  uint32_t return_value;
+
+  return_value = (CFG_TS_TICK_VAL) * (uint32_t)(LpTimerContext.LpTimeLeftOnEntry - HW_TS_RTC_ReadLeftTicksToCount());
+  return_value = return_value / 1000;
+
+  /**
+   * The system may have been out from another reason than the timer
+   * Stop the timer after the elapsed time is calculated other wise, HW_TS_RTC_ReadLeftTicksToCount()
+   * may return 0xFFFF ( TIMER LIST EMPTY )
+   * It does not hurt stopping a timer that exists but is not running.
+   */
+  HW_TS_Stop(LpTimerContext.LpTimer_Id);
+
+  return return_value;
+}
+
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+/**
+ * @brief Low power timer callback
+ *
+ * @param  None
+ * @retval None
+ */
+static void LpTimerCb( void )
+{
+  /**
+   * Nothing to be done
+   */
+
+  return;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/main.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/main.c
index ec1faf587..95537ac98 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/main.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/main.c
@@ -50,9 +50,17 @@
 #include "appli_mesh.h"
 #include "models_if.h"
 #include "mesh_cfg.h"
+#include "otp.h"
+#include "stm32wbxx_hal_rcc.h"
 
 
+/** @addtogroup ST_BLE_Mesh
+ *  @{
+ */
 
+/** @addtogroup Application
+*  @{
+*/
 /* Private typedef -----------------------------------------------------------*/
 /* Private defines -----------------------------------------------------------*/
 /* Private macros ------------------------------------------------------------*/
@@ -69,6 +77,9 @@ static void SystemClock_Config( void );
 static void Reset_Device( void );
 static void Reset_IPCC( void );
 static void Init_Exti( void );
+void Error_Handler(void);
+void PeriphClock_Config(void);
+static void Config_HSE(void);
 
 /* Functions Definition ------------------------------------------------------*/
 
@@ -82,6 +93,7 @@ int main( void )
   HAL_Init();
 
   Reset_Device();
+  Config_HSE();
 
   /**
    * When the application is expected to run at higher speed, it should be better to set the correct system clock
@@ -89,6 +101,10 @@ int main( void )
    */
   SystemClock_Config(); /**< Configure the system clock */
 
+  PeriphClock_Config();
+  
+//  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_16);
+    
   Init_Exti( );
 
   Init_RTC();
@@ -98,6 +114,10 @@ int main( void )
 
   APPE_Init( );
   
+#if ( CFG_LPM_SUPPORTED == 1)
+//  BSP_LED_On(LED_GREEN);
+#endif
+  
   while(1)
   {
     UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
@@ -199,14 +219,17 @@ static void Init_RTC( void )
 
   __HAL_RCC_RTC_ENABLE(); /**< Enable RTC */
 
-  hrtc.Instance = RTC; /**< Define instance */
-
-  /**
-   * Set the Asynchronous prescaler
-   */
+  hrtc.Instance = RTC;
+  hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
   hrtc.Init.AsynchPrediv = CFG_RTC_ASYNCH_PRESCALER;
   hrtc.Init.SynchPrediv = CFG_RTC_SYNCH_PRESCALER;
-  HAL_RTC_Init(&hrtc);
+  hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
+  hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+  hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+  if (HAL_RTC_Init(&hrtc) != HAL_OK)
+  {
+    Error_Handler();
+  }
 
   /* Disable RTC registers write protection */
   LL_RTC_DisableWriteProtection(RTC);
@@ -219,19 +242,7 @@ static void Init_RTC( void )
   return;
 }
 
-/**
- * @brief  Configure the system clock
- *
- * @note   This API configures
- *         - The system clock source
- *           - The AHBCLK, APBCLK dividers
- *           - The flash latency
- *           - The PLL settings (when required)
- *
- * @param  None
- * @retval None
- */
-void SystemClock_Config( void )
+void PeriphClock_Config(void)
 {
 #if (CFG_USB_INTERFACE_ENABLE != 0)
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
@@ -276,26 +287,114 @@ void SystemClock_Config( void )
   HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
 #endif
 
+  return;
+}
+
+static void Config_HSE(void)
+{
+    OTP_ID0_t * p_otp;
+
   /**
-   *  Write twice the value to flush the APB-AHB bridge to ensure the  bit is written
+   * Read HSE_Tuning from OTP
    */
-  HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
-  HAL_PWR_EnableBkUpAccess();
+  p_otp = (OTP_ID0_t *) OTP_Read(0);
+  if (p_otp)
+  {
+    LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
+  }
+
+  return;
+}  
 
   /**
-   * Select LSE clock
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
    */
-  LL_RCC_LSE_Enable();
-  while(!LL_RCC_LSE_IsReady());
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+ 
+  /* USER CODE END Error_Handler_Debug */
+}
 
-  /**
-   * Select wakeup source of BLE RF
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure LSE Drive Capability 
+  */
+  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE
+                              |RCC_OSCILLATORTYPE_LSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
+#if ( CFG_LPM_SUPPORTED == 1)
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
+#else
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+#endif
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the peripherals clocks 
    */
-  LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_LSE);
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RFWAKEUP
+                              |RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1
+                              |RCC_PERIPHCLK_LPUART1;
+  PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+  PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN Smps */
 
-  return;
+#if (CFG_USE_SMPS != 0)
+  /**
+   *  Configure and enable SMPS
+   *
+   *  The SMPS configuration is not yet supported by CubeMx
+   */
+  LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
+  LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
+  LL_PWR_SMPS_Enable();
+#endif
+  /* USER CODE END Smps */
 }
 
+
 /*************************************************************
  *
  * WRAP FUNCTIONS
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/stm32_lpm_if.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/stm32_lpm_if.c
index f024b61e3..1418e0a36 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/stm32_lpm_if.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/stm32_lpm_if.c
@@ -70,6 +70,13 @@ static void Switch_On_HSI( void );
 void PWR_EnterOffMode( void )
 {
 /* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
   /************************************************************************************
    * ENTER OFF MODE
    ***********************************************************************************/
@@ -106,6 +113,8 @@ void PWR_ExitOffMode( void )
 {
 /* USER CODE BEGIN PWR_ExitOffMode */
 
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitOffMode */
 }
 
@@ -118,6 +127,16 @@ void PWR_ExitOffMode( void )
 void PWR_EnterStopMode( void )
 {
 /* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
   /**
    * This function is called from CRITICAL SECTION
    */
@@ -202,6 +221,9 @@ void PWR_ExitStopMode( void )
 
   /* Release RCC semaphore */
   LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitStopMode */
 }
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/EWARM/BLE_MeshLightingDemo.ewd b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/EWARM/BLE_MeshLightingDemo.ewd
index 2c34928be..da150faa3 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/EWARM/BLE_MeshLightingDemo.ewd
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/EWARM/BLE_MeshLightingDemo.ewd
@@ -2,7 +2,7 @@
 
     3
     
-        BLE_MeshLightingDemo
+        Lighting_Node
         
             ARM
         
@@ -44,7 +44,7 @@
                 
                 
                 
                 
                 
             
         
+        
+            NULINK_ID
+            2
+            
+        
         
             
                 $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/EWARM/BLE_MeshLightingDemo.ewp b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/EWARM/BLE_MeshLightingDemo.ewp
index 794c7c007..b5e9a83f0 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/EWARM/BLE_MeshLightingDemo.ewp
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/EWARM/BLE_MeshLightingDemo.ewp
@@ -2,7 +2,7 @@
 
     3
     
-        BLE_MeshLightingDemo
+        Lighting_Node
         
             ARM
         
@@ -16,15 +16,15 @@
                 0
                 
                 
                 
                 
                 
                 
                 
                 
                 
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ *
+ ******************************************************************************
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "hal_common.h"
+#include "types.h"
+#include "appli_generic.h"
+#include "appli_light.h"
+#include "common.h"
+#include "mesh_cfg_usr.h"
+#include "appli_nvm.h"
+#include "config_client.h"
+#include "appli_config_client.h"
+#include "appli_mesh.h"
+#include "sensors.h"
+#include "light_lc.h"
+#include "vendor.h"
+
+/** @addtogroup ST_BLE_Mesh
+*  @{
+*/
+
+/** @addtogroup Application_Mesh_Models
+*  @{
+*/
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define DEFAULT_GROUP_ADDR   0xC000
+#define DEFAULT_PUBLISH_ADDR 0xC000
+#define DEFAULT_NETKEY_INDEX 0x0000
+#define DEFAULT_APPKEY_INDEX 0x0000
+#define DEFAULT_CREDENTIAL_FLAG 0x00
+#define DEFAULT_PUBLISH_TTL   0x08
+#define DEFAULT_PUBLISH_PERIOD   0x00
+#define DEFAULT_PUBLISH_RETRANSMIT_COUNT 0x00   
+#define DEFAULT_PUBLISH_RETRANSMIT_INTERVAL_STEPS 0x00
+
+#define NUM_VENDOR_MODELS_TO_SUBSCRIBE 0
+#define NUM_VENDOR_MODELS_TO_PUBLISH 0
+#define NUM_VENDOR_MODELS_TO_BIND_APP 0
+
+const MOBLEUINT8 aConfigAppKeyDefault[19]= 
+                { /* NetKeyIndexAndAppKeyIndex : 3B
+                Index of the NetKey and index of the AppKey*/
+                (MOBLEUINT8)(DEFAULT_NETKEY_INDEX & 0x00ff), 
+                (MOBLEUINT8)((DEFAULT_NETKEY_INDEX & 0x0f00) >> 8) | (MOBLEUINT8) ((DEFAULT_APPKEY_INDEX & 0x000f) << 4), 
+                (MOBLEUINT8) ((DEFAULT_APPKEY_INDEX >>4) & 0xff), 
+                /* AppKey is initialised as below = 16B */
+                 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 
+                 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 };
+
+
+const MOBLEUINT8 aConfigAppKeyDeleteDefault[3]= 
+                { /* NetKeyIndexAndAppKeyIndex : 3B
+                Index of the NetKey and index of the AppKey*/
+                (MOBLEUINT8)(DEFAULT_NETKEY_INDEX & 0x00ff), 
+                (MOBLEUINT8)((DEFAULT_NETKEY_INDEX & 0x0f00) >> 8) | (MOBLEUINT8) ((DEFAULT_APPKEY_INDEX & 0x000f) << 4), 
+                (MOBLEUINT8) ((DEFAULT_APPKEY_INDEX >>4) & 0xff)};
+
+const MOBLEUINT8 aConfigAppKeyGetDefault[2]= 
+                { /* NetKeyIndex : 2B
+                Index of the NetKey */
+                (MOBLEUINT8)(DEFAULT_NETKEY_INDEX & 0x00ff), 
+                (MOBLEUINT8)((DEFAULT_NETKEY_INDEX & 0x0f00) >> 8) };
+
+const MOBLEUINT8 aNoParamDefaultConfig;
+
+#define MAX_CONFIG_PARAM_SIZE 22
+const MOBLEUINT8 aNoInitParamDefault[MAX_CONFIG_PARAM_SIZE]= {0};
+
+/* Private macro -------------------------------------------------------------*/
+MOBLEUINT16 aSigModelsToBind[] = 
+{
+  GENERIC_MODEL_SERVER_ONOFF_MODEL_ID, 
+  GENERIC_MODEL_SERVER_LEVEL_MODEL_ID,
+  //                  GENERIC_MODEL_SERVER_DEFAULT_TRANSITION_TIME_MODEL_ID, 
+  //                  SENSOR_SERVER_MODEL_ID,
+  //                  LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID,
+  //                  LIGHT_MODEL_SERVER_LC_MODEL_ID
+};
+
+MOBLEUINT16 aPublishModels[] = 
+{
+                  GENERIC_MODEL_SERVER_ONOFF_MODEL_ID,
+                  GENERIC_MODEL_SERVER_LEVEL_MODEL_ID,
+//                  GENERIC_MODEL_SERVER_DEFAULT_TRANSITION_TIME_MODEL_ID, 
+//                  SENSOR_SERVER_MODEL_ID,
+//                  LIGHT_MODEL_SERVER_LIGHTNESS_MODEL_ID,
+//                  LIGHT_MODEL_SERVER_LC_MODEL_ID
+};
+
+MOBLEUINT16 aSubscribeModels[] = 
+{
+                  GENERIC_MODEL_SERVER_ONOFF_MODEL_ID, 
+                  GENERIC_MODEL_SERVER_LEVEL_MODEL_ID,
+//                  GENERIC_MODEL_SERVER_DEFAULT_TRANSITION_TIME_MODEL_ID, 
+//                  LIGHT_MODEL_SERVER_LC_MODEL_ID
+};        
+
+const MODEL_CONFIG_CLIENT_OpcodeTableParam_t ConfigClient_MessageOpcodes_Table[] = {
+  /*    MOBLEUINT16 opcode, 
+        MOBLEUINT8 min_payload_size, 
+        MOBLEUINT8 max_payload_size;
+  Here in this array, Handler is not defined; */
+
+  /* 4.3.2.37 Config AppKey Add, Opcode = 0x00
+     The Config AppKey Add is an acknowledged message used to add an AppKey 
+       to the AppKey List on a node and bind it to the NetKey identified by 
+       NetKeyIndex. The added AppKey can be used by the node only as a pair with 
+       the specified NetKey. 
+    The AppKey is used to authenticate and decrypt messages it receives, as well 
+      as authenticate and encrypt messages it sends.
+    The response to a Config AppKey Add message is a Config AppKey Status message.
+
+    message parameters:
+    -------------------
+    NetKeyIndexAndAppKeyIndex: 3B : Index of the NetKey and index of the AppKey
+    AppKey 16B : AppKey value */
+  { OPCODE_CONFIG_APPKEY_ADD,    19, 19, aConfigAppKeyDefault },  
+
+  /* 4.3.2.39 Config AppKey Delete, Opcode = 0x80 0x00
+     The Config AppKey Delete is an acknowledged message used to delete an 
+       AppKey from the AppKey List on a node. 
+     The response to a Config AppKey Delete message is a 
+       Config AppKey Status message.
+
+    message parameters:
+    -------------------
+    NetKeyIndexAndAppKeyIndex : 3B : Index of the NetKey and index of the AppKey
+   */
+  { OPCODE_CONFIG_APPKEY_DELETE,  3,  3, aConfigAppKeyDeleteDefault },
+  
+  /* 4.3.2.41 Config AppKey Get, Opcode = 0x80 0x01
+     The AppKey Get is an acknowledged message used to report all AppKeys bound 
+       to the NetKey.
+     The response to a Config AppKey Get message is a Config AppKey List message */
+  { OPCODE_CONFIG_APPKEY_GET,     2,  2, aConfigAppKeyGetDefault }, 
+  
+  /* 4.3.2.38 Config AppKey Update, Opcode = 0x01
+     The Config AppKey Update is an acknowledged message used to update an 
+     AppKey value on the AppKey List on a node. The updated AppKey is used by 
+     the node to authenticate and decrypt messages it receives, as well as 
+     authenticate and encrypt messages it sends, as defined by the Key Refresh procedure (see Section 3.10.4).
+     The response to an Config AppKey Update message is an Config AppKey Status message. 
+
+    message parameters:
+    -------------------
+    NetKeyIndexAndAppKeyIndex: 3B : Index of the NetKey and index of the AppKey
+    AppKey 16B : AppKey value */
+  { OPCODE_CONFIG_APPKEY_UPDATE, 19, 19, aConfigAppKeyDefault },
+
+    /* 4.3.2.1 Config Beacon Get, Opcode = 0x80 0x09
+     The Config Beacon Get is an acknowledged message used to get the current 
+     Secure Network Beacon state of a node (see Section 4.2.10).
+     The response to a Config Beacon Get message is a Config Beacon Status message.
+     There are no Parameters for this message. */
+  { OPCODE_CONFIG_BEACON_GET, 0, 0, aNoInitParamDefault }, 
+
+  /* 4.3.2.2 Config Beacon Set, Opcode = 0x80 0x0A
+    The Config Beacon Set is an acknowledged message used to set the 
+    Secure Network Beacon state of a node (see Section 4.2.10).
+    The response to a Config Beacon Set message is a Config Beacon Status message.
+    Beacon : 1B: New Secure Network Beacon state*/
+  { OPCODE_CONFIG_BEACON_SET, 1, 1, aNoInitParamDefault }, 
+
+  /* 4.3.2.4 Config Composition Data Get, Opcode = 0x80 0x08
+     The Config Composition Data Get is an acknowledged message used to read 
+       one page of the Composition Data (see Section 4.2.1).
+     The response to a Config Composition Data Get message is a 
+        Config Composition Data Status message. 
+     Page : 1B : Page number of the Composition Data   */
+  { OPCODE_CONFIG_COMPOSITION_DATA_GET, 1, 1, aNoInitParamDefault },
+  
+  /* 4.3.2.16 Config Model Publication Set, Opcode = 0x03
+     The Config Model Publication Set is an acknowledged message used to set the
+     Model Publication state (see Section 4.2.2) of an outgoing message that 
+     originates from a model.
+     The response to a Config Model Publication Set message is a 
+        Config Model Publication Status message.
+     The Config Model Publication Set message uses a single octet opcode to 
+         maximize the size of a payload.
+
+      ElementAddress : 16b : Address of the element
+      PublishAddress : 16b : Value of the publish address
+      AppKeyIndex : 12b : Index of the application key
+      CredentialFlag : 1b : Value of the Friendship Credential Flag
+      RFU : 3b : Reserved for Future Use
+      PublishTTL : 8b : Default TTL value for the outgoing messages
+      PublishPeriod : 8b : Period for periodic status publishing
+      PublishRetransmitCount : 3b : Number of retransmissions for each published message
+      PublishRetransmitIntervalSteps : 5b: Number of 50-millisecond steps between retransmissions
+      ModelIdentifier: 16 or 32b: SIG Model ID or Vendor Model ID
+   */
+  
+  { OPCODE_CONFIG_CONFIG_MODEL_PUBLICATION_SET, 11, 13, }, 
+
+  /* 4.3.2.6 Config Default TTL Get, Opcode = 0x80 0x0C
+    The Config Default TTL Get is an acknowledged message used to get the 
+    current Default TTL state of a node.
+    The response to a Config Default TTL Get message is a Config Default TTL Status message.
+    There are no Parameters for this message.
+  */
+  { OPCODE_CONFIG_DEFAULT_TTL_GET, 0, 0, aNoInitParamDefault },          
+  
+  /* 4.3.2.7 Config Default TTL Set, Opcode = 0x80 0x0D
+     The Config Default TTL Set is an acknowledged message used to set the 
+     Default TTL state of a node (see Section 4.2.7).
+     The response to a Config Default TTL Set message is a 
+       Config Default TTL Status message. 
+     TTL : 1B : New Default TTL value*/
+  { OPCODE_CONFIG_DEFAULT_TTL_SET, 1, 1, aNoInitParamDefault }, 
+
+  /* 4.3.2.55 Config Friend Get, Opcode = 0x80 0x0F
+     The Config Friend Get is an acknowledged message used to get the current 
+       Friend state of a node (see Section 4.2.13).
+     The response to a Config Friend Get message is a Config Friend Status message.
+     There are no Parameters for this message. */
+  { OPCODE_CONFIG_FRIEND_GET, 0, 0, aNoInitParamDefault }, 
+  
+  /* 4.3.2.56 Config Friend Set, Opcode = 0x80 0x10
+     The Config Friend Set is an acknowledged message used to set the 
+      Friend state of a node (see Section 4.2.13).
+     The response to a Config Friend Set message is a Config Friend Status message. 
+      Friend : 1B : New Friend state    */
+  { OPCODE_CONFIG_FRIEND_SET, 1, 1, aNoInitParamDefault },
+
+  /* 4.3.2.9 Config GATT Proxy Get, Opcode = 0x80 0x12
+     The Config GATT Proxy Get is an acknowledged message used to get the 
+     current GATT Proxy state of a node (see Section 4.2.11).
+     The response to a Config GATT Proxy Get message is a 
+        Config GATT Proxy Status message.
+     There are no Parameters for this message. */
+  { OPCODE_CONFIG_GATT_PROXY_GET, 0, 0, aNoInitParamDefault },          
+
+  /* 4.3.2.10 Config GATT Proxy Set, Opcode = 0x80 0x12
+     The Config GATT Proxy Set is an acknowledged message used to set the 
+        GATT Proxy state of a node (see Section 4.2.11).
+     The response to a Config GATT Proxy Set message is a Config GATT Proxy 
+        Status message
+     GATTProxy : 1B  : New GATT Proxy state */
+  { OPCODE_CONFIG_GATT_PROXY_SET, 1, 1, aNoInitParamDefault },
+
+    /* 4.3.2.61 Config Heartbeat Publication Get, Opcode = 0x80 0x38
+    The Config Heartbeat Publication Get is an acknowledged message used to get 
+    the current Heartbeat Publication state of an element (see Section 4.2.17).
+    The response to a Config Heartbeat Publication Get message is a 
+    Config Heartbeat Publication Status message.
+    The message has no parameters.*/
+  { OPCODE_CONFIG_HEARTBEAT_PUBLICATION_GET, 0, 0, aNoInitParamDefault },
+  
+  /* 4.3.2.62 Config Heartbeat Publication Set, Opcode = 0x80 0x39
+    The Config Heartbeat Publication Set is an acknowledged message used to set 
+    the current Heartbeat Publication state of an element (see Section 4.2.17).
+    The response to a Config Heartbeat Publication Set message is a 
+    Config Heartbeat Publication Status message. 
+
+   Destination : 2B : Destination address for Heartbeat messages
+   CountLog    : 1B : Number of Heartbeat messages to be sent
+   PeriodLog   : 1B : Period for sending Heartbeat messages
+   TTL         : 1B : TTL to be used when sending Heartbeat messages
+   Features    : 2B : Bit field indicating features that trigger Heartbeat messages when changed
+   NetKeyIndex : 2B : NetKey Index
+  */
+  { OPCODE_CONFIG_HEARTBEAT_PUBLICATION_SET, 9, 9, aNoInitParamDefault },
+  
+  /* 4.3.2.64 Config Heartbeat Subscription Get, Opcode = 0x80 0x3A
+     The Config Heartbeat Subscription Get is an acknowledged message used to get  
+     the current Heartbeat Subscription state of an element (see Section 4.2.18).
+     The response to a Config Heartbeat Subscription Get message is a 
+     Config Heartbeat Subscription Status message.
+   The message has no parameters. */
+  { OPCODE_CONFIG_HEARTBEAT_SUBSCRIPTION_GET, 0, 0, aNoInitParamDefault },
+  
+  /* 4.3.2.65 Config Heartbeat Subscription Set, Opcode = 0x80 0x3B
+     The Config Heartbeat Subscription Set is an acknowledged message used to 
+     set the current Heartbeat Subscription state of an element (see Section 4.2.18).
+      The response to a Config Heartbeat Subscription Set message is a 
+      Config Heartbeat Subscription Status message.
+
+      Source : 2B : Source address for Heartbeat messages
+      Destination : 2B : Destination address for Heartbeat messages
+      PeriodLog : 1B : Period for receiving Heartbeat messages */
+  { OPCODE_CONFIG_HEARTBEAT_SUBSCRIPTION_SET, 5, 5, aNoInitParamDefault },
+
+  /* 4.3.2.58 Config Key Refresh Phase Get, Opcode = 0x80 0x15
+     The Config Key Refresh Phase Get is an acknowledged message used to get the
+       current Key Refresh Phase state of the identified network key.
+     The response to a Config Key Refresh Phase Get message is a 
+       Config Key Refresh Phase Status message. 
+     NetKeyIndex : 2B : NetKey Index*/
+  { OPCODE_CONFIG_KEY_REFRESH_PHASE_GET, 2, 2, aNoInitParamDefault },
+  
+  /* 4.3.2.59 Config Key Refresh Phase Set, Opcode = 0x80 0x16
+    The Config Key Refresh Phase Set is an acknowledged message used to set the 
+    Key Refresh Phase state of the identified network key (see Section 4.2.14).
+   The response to a Config Key Refresh Phase Set message is a 
+      Config Key Refresh Phase Status message. 
+   
+   NetKeyIndex : 2B : NetKey Index 
+   Transition  : 1B : New Key Refresh Phase Transition */
+  { OPCODE_CONFIG_KEY_REFRESH_PHASE_SET, 3, 3, aNoInitParamDefault },
+
+  /* 4.3.2.67 Config Low Power Node PollTimeout Get, Opcode = 0x80 0x2D
+     The Config Low Power Node PollTimeout Get is an acknowledged message used 
+     to get the current value of PollTimeout timer of the Low Power node within 
+     a Friend node (see Section 3.6.6.1). The message is sent to a Friend node 
+    that has claimed to be handling messages by sending ACKs On Behalf Of (OBO) 
+    the indicated Low Power node. This message should only be sent to a node 
+    that has the Friend feature supported and enabled.
+    The response to a Config Low Power Node PollTimeout Get message is a 
+    Config Low Power Node PollTimeout Status message. 
+
+    LPNAddress : 2B : The unicast address of the Low Power node */
+  { OPCODE_CONFIG_LOW_POWER_NODE_POLLTIMEOUT_GET, 2, 2, aNoInitParamDefault },
+
+  
+  /* 4.3.3.12 Health Attention Get
+     The Health Attention Get is an acknowledged message used to get the current
+     Attention Timer state of an element (see Section 4.2.9).
+     The response to a Health Attention Get message is an Attention Status message.
+     There are no Parameters for this message.*/
+  { OPCODE_HEALTH_ATTENTION_GET, 0, 0, aNoInitParamDefault }, 
+  
+  /* 4.3.3.13 Health Attention Set
+     The Health Attention Set is an acknowledged message used to set the 
+     Attention Timer state of an element (see Section 4.2.9).
+     The response to a Health Attention Set message is a 
+     Health Attention Status message 
+    Attention: 1B: Value of the Attention Timer state*/
+  { OPCODE_HEALTH_ATTENTION_SET, 1, 1, aNoInitParamDefault }, 
+  
+  /* 4.3.3.14 Health Attention Set Unacknowledged
+     The Health Attention Set Unacknowledged is an unacknowledged message used 
+     to set the Attention Timer state of an element (see Section 4.2.9). */
+  { OPCODE_HEALTH_ATTENTION_SET_UNACKNOWLEDGED, 1, 1, aNoInitParamDefault }, 
+  
+  
+
+  
+
+
+  /* 4.3.2.15 Config Model Publication Get
+     The Config Model Publication Get is an acknowledged message used to get the
+     publish address and parameters of an outgoing message that originates 
+     from a model.
+     The response to a Config Model Publication Get message is a 
+     Config Model Publication Status message.
+
+     ElementAddress : 2B : Address of the element
+     ModelIdentifier : 2 or 4B : SIG Model ID or Vendor Model ID
+  */
+  { OPCODE_CONFIG_MODEL_PUBLICATION_GET, 4, 6, aNoInitParamDefault },
+  
+  /* 4.3.2.17 Config Model Publication Virtual Address Set
+     The Config Model Publication Virtual Address Set is an acknowledged message 
+     used to set the model Publication state (see Section 4.2.2) of an 
+     outgoing message that originates from a model.
+     The response to a Config Model Publication Virtual Address Set message is 
+        a Config Model Publication Status message.
+
+      ElementAddress : 16b : Address of the element
+      PublishAddress : 128b : Value of the Label UUID publish address
+      AppKeyIndex : 12b : Index of the application key
+      CredentialFlag : 1b : Value of the Friendship Credential Flag
+      RFU : 3b : Reserved for Future Use
+      PublishTTL : 8b : Default TTL value for the outgoing messages
+      PublishPeriod : 8b : Period for periodic status publishing
+      PublishRetransmitCount : 3b : Number of retransmissions for each published message
+      PublishRetransmitIntervalSteps : 5b: Number of 50-millisecond steps between retransmissions
+      ModelIdentifier: 16 or 32b: SIG Model ID or Vendor Model ID
+  */
+  { OPCODE_CONFIG_MODEL_PUBLICATION_VIRTUAL_ADDRESS_SET, 25, 27, aNoInitParamDefault },
+  
+  /* 4.3.2.19 Config Model Subscription Add
+     The Config Model Subscription Add is an acknowledged message used to add an 
+     address to a Subscription List of a model (see Section 4.2.3).
+
+      The response to a Config Model Subscription Add message is a 
+      Config Model Subscription Status message.
+
+    ElementAddress  : 2B       : Address of the element
+    address     : 2B           : Value of the address
+    ModelIdentifier : 2B or 4B : SIG Model ID or Vendor Model ID
+*/
+  { OPCODE_CONFIG_MODEL_SUBSCRIPTION_ADD, 6, 8, aNoInitParamDefault },
+  
+  /* 4.3.2.21 Config Model Subscription Delete
+     The Config Model Subscription Delete is an acknowledged message used to 
+     delete a subscription address from the Subscription List of a model (see Section 4.2.3).
+      The response to a Config Model Subscription Delete message is a 
+      Config Model Subscription Status message.
+
+    ElementAddress  : 2B       : Address of the element
+    address     : 2B           : Value of the address
+    ModelIdentifier : 2B or 4B : SIG Model ID or Vendor Model ID
+  */
+  { OPCODE_CONFIG_MODEL_SUBSCRIPTION_DELETE, 6, 8, aNoInitParamDefault },
+  
+  /* 4.3.2.25 Config Model Subscription Delete All
+     The Config Model Subscription Delete All is an acknowledged message used to 
+        discard the Subscription List of a model (see Section 4.2.3).
+     The response to a Config Model Subscription Delete All message is a 
+        Config Model Subscription Status message. 
+    ElementAddress  : 2B       : Address of the element
+    ModelIdentifier : 2B or 4B : SIG Model ID or Vendor Model ID */
+  { OPCODE_CONFIG_MODEL_SUBSCRIPTION_DELETE_ALL, 4, 6, aNoInitParamDefault },
+
+  /* 4.3.2.23 Config Model Subscription Overwrite
+     The Config Model Subscription Overwrite is an acknowledged message used to 
+     discard the Subscription List and add an address to the 
+     cleared Subscription List of a model (see Section 4.2.3).
+     
+     The response to a Config Model Subscription Overwrite message is a 
+     Config Model Subscription Status message. 
+
+    ElementAddress  : 2B       : Address of the element
+    address     : 2B           : Value of the address
+    ModelIdentifier : 2B or 4B : SIG Model ID or Vendor Model ID */
+  { OPCODE_CONFIG_MODEL_SUBSCRIPTION_OVERWRITE, 6, 8, aNoInitParamDefault },
+
+  /* 4.3.2.20 Config Model Subscription Virtual Address Add
+     The Config Model Subscription Virtual Address Add is an acknowledged message 
+    used to add an address to a Subscription List of a model (see Section 4.2.3).
+    The response to a Config Model Subscription Virtual Address Add message is a 
+    Config Model Subscription Status message. 
+
+    ElementAddress  : 2B       : Address of the element
+    Label           : 16B      : Value of the Label UUID
+    ModelIdentifier : 2B or 4B : SIG Model ID or Vendor Model ID */
+  { OPCODE_CONFIG_MODEL_SUBSCRIPTION_VIRTUAL_ADDRESS_ADD, 20, 22, aNoInitParamDefault },
+  
+  /* 4.3.2.22 Config Model Subscription Virtual Address Delete
+     The Config Model Subscription Virtual Address Delete is an acknowledged 
+       message used to delete a subscription address from the 
+       Subscription List of a model (see Section 4.2.3).
+     The response to a Config Model Subscription Virtual Address Delete message 
+     is a Config Model Subscription Status message. 
+    ElementAddress  : 2B       : Address of the element
+    Address         : 16B      : Value of the Label UUID
+    ModelIdentifier : 2B or 4B : SIG Model ID or Vendor Model ID */
+  { OPCODE_CONFIG_MODEL_SUBSCRIPTION_VIRTUAL_ADDRESS_DELETE, 20, 22, aNoInitParamDefault },
+  
+    /* 4.3.2.24 Config Model Subscription Virtual Address Overwrite
+       The Config Model Subscription Virtual Address Overwrite is an acknowledged 
+       message used to discard the Subscription List and add an address to the 
+       cleared Subscription List of a model (see Section 4.2.3).
+       The response to a Config Model Subscription Virtual Address Overwrite 
+       message is a Config Model Subscription Status message. 
+       Element Address  : 2B       : Address of the element
+       Address          : 16B      : Value of the Label UUID
+       ModelIdentifier  : 2B or 4B : SIG Model ID or Vendor Model ID */
+
+  { OPCODE_CONFIG_MODEL_SUBSCRIPTION_VIRTUAL_ADDRESS_OVERWRITE, 20, 22, aNoInitParamDefault },
+  
+  /* 4.3.2.69 Config Network Transmit Get
+     The Config Network Transmit Get is an acknowledged message used to get the 
+     current Network Transmit state of a node (see Section 4.2.19).
+     The response to a Config Network Transmit Get message is a Config Network 
+        Transmit Status message.
+    There are no Parameters for this message. */
+  { OPCODE_CONFIG_NETWORK_TRANSMIT_GET, 0, 0, aNoInitParamDefault },     
+  
+  /* 4.3.2.70 Config Network Transmit Set
+     The Config Network Transmit Set is an acknowledged message used to set the 
+        Network Transmit state of a node (see Section 4.2.19).
+     The response to a Config Network Transmit Set message is a Config Network 
+        Transmit Status message.
+     
+     NetworkTransmitCount : 3b : Number of transmissions for each Network PDU originating from the node
+     NetworkTransmitIntervalSteps : 5b : Number of 10-millisecond steps between transmissions 
+  */
+  { OPCODE_CONFIG_NETWORK_TRANSMIT_SET, 1, 1, aNoInitParamDefault }, 
+
+  /* 4.3.2.12 Config Relay Get
+     The Config Relay Get is an acknowledged message used to get the 
+       current Relay (see Section 4.2.8) and Relay Retransmit (see Section 4.2.20) 
+       states of a node.
+     The response to a Config Relay Get message is a Config Relay Status message.
+     There are no Parameters for this message.*/
+  { OPCODE_CONFIG_RELAY_GET, 0, 0, aNoInitParamDefault },      
+  
+  /* 4.3.2.13 Config Relay Set
+     The Config Relay Set is an acknowledged message used to set the Relay 
+    (see Section 4.2.8) and Relay Retransmit (see Section 4.2.20) states of a node.
+    The response to a Config Relay Set message is a Config Relay Status message. 
+    Relay : 8 bits : Relay
+    RelayRetransmitCount  : 3b : Number of retransmissions on advertising bearer for each Network PDU relayed by the node
+    RelayRetransmitIntervalSteps : 5b : Number of 10-millisecond steps between retransmissions
+  */
+  { OPCODE_CONFIG_RELAY_SET, 2, 2, aNoInitParamDefault },      
+
+  /* 4.3.2.27 Config SIG Model Subscription Get
+     The Config SIG Model Subscription Get is an acknowledged message used to 
+     get the list of subscription addresses of a model within the element. 
+     This message is only for SIG Models.
+     The response to a Config SIG Model Subscription Get message is a Config SIG 
+     Model Subscription List message.
+       Element Address  : 2B       : Address of the element
+       ModelIdentifier  : 2B       : SIG Model ID  */
+
+  { OPCODE_CONFIG_SIG_MODEL_SUBSCRIPTION_GET, 4, 4, aNoInitParamDefault },
+  
+  /* 4.3.2.29 Config Vendor Model Subscription Get
+     The Config Vendor Model Subscription Get is an acknowledged message used to
+     get the list of subscription addresses of a model within the element. 
+     This message is only for Vendor Models.
+     The response to a Config Vendor Model Subscription Get message is a 
+     Config Vendor Model Subscription List message.
+       Element Address  : 2B       : Address of the element
+       ModelIdentifier  : 4B       : Vendor Model ID */
+
+  { OPCODE_CONFIG_VENDOR_MODEL_SUBSCRIPTION_GET, 6, 6, aNoInitParamDefault },
+  
+
+  /* 4.3.3.4 Health Fault Clear
+     The Health Fault Clear is an acknowledged message used to clear the current
+       Registered Fault state identified by Company ID of an element 
+       (see Section 4.2.15.2).
+     The response to a Health Fault Clear message is a Health Fault Status message */
+  { OPCODE_HEALTH_FAULT_CLEAR, 2, 2, aNoInitParamDefault },
+
+       /* 4.3.3.3 Health Fault Clear Unacknowledged
+      The Health Fault Clear Unacknowledged is an unacknowledged message used to
+      clear the current Registered Fault state identified by Company ID of an 
+      element (see Section 4.2.15.2).
+      Company ID : 2B : 16-bit Bluetooth assigned Company Identifier */
+
+   { OPCODE_HEALTH_FAULT_CLEAR_UNACKNOWLEDGED, 2, 2, aNoInitParamDefault },
+  
+  /* 4.3.3.2 Health Fault Get
+     The Health Fault Get is an acknowledged message used to get the current 
+     Registered Fault state identified by Company ID of an element 
+     (see Section 4.2.15.2).
+     The response to a Health Fault Get message is a Health Fault Status message
+     Company ID : 2B : 16-bit Bluetooth assigned Company Identifier */
+   { OPCODE_HEALTH_FAULT_GET, 2, 2, aNoInitParamDefault },
+   
+   /* 4.3.3.5 Health Fault Test
+      The Health Fault Test is an acknowledged message used to invoke a 
+      self-test procedure of an element. 
+      The procedure is implementation specific and may result in changing the 
+       Health Fault state of an element (see Section 4.2.15).
+     The response to a Health Fault Test message is a Health Fault Status message.
+
+     Test ID : 1B : Identifier of a specific test to be performed 
+    Company ID : 2B : 16-bit Bluetooth assigned Company Identifier */
+  { OPCODE_HEALTH_FAULT_TEST, 3, 3, aNoInitParamDefault },
+   
+  /* 4.3.3.6 Health Fault Test Unacknowledged
+     The Health Fault Test Unacknowledged is an unacknowledged message used to 
+     invoke a self-test procedure of an element. The procedure is implementation
+     specific and may result in changing the Health Fault state of an element 
+    (see Section 4.2.15). 
+
+    Test ID : 1B : Identifier of a specific test to be performed 
+    Company ID : 2B : 16-bit Bluetooth assigned Company Identifier */
+  { OPCODE_HEALTH_FAULT_TEST_UNACKNOWLEDGED, 3, 3, aNoInitParamDefault },
+  
+  /* 4.3.3.8 Health Period Get
+    The Health Period Get is an acknowledged message used to get the 
+    current Health Fast Period Divisor state of an element (see Section 4.2.16).
+    The response to a Health Period Get message is a Health Period Status message.
+    There are no parameters for this message. */
+  { OPCODE_HEALTH_PERIOD_GET, 0, 0, aNoInitParamDefault },
+  
+  /* 4.3.3.10 Health Period Set
+    The Health Period Set is an acknowledged message used to set the current 
+    Health Fast Period Divisor state of an element (see Section 4.2.16).
+    The response to a Health Period Set message is a Health Period Status message
+   
+    FastPeriodDivisor : 1B: Divider for the Publish Period. 
+               Modified Publish Period is used for sending Current */
+  { OPCODE_HEALTH_PERIOD_SET, 1, 1, aNoInitParamDefault },
+  
+  /* 4.3.3.9 Health Period Set Unacknowledged
+     The Health Period Set Unacknowledged is an unacknowledged message used to 
+     set the current Health Fast Period Divisor state of an element 
+    (see Section 4.2.16). 
+
+   FastPeriodDivisor : 1B: Divider for the Publish Period. 
+               Modified Publish Period is used for sending Current 
+           Health Status messages when there are active faults to communicate */
+  { OPCODE_HEALTH_PERIOD_SET_UNACKNOWLEDGED, 1, 1, aNoInitParamDefault },
+////  { OPCODE_HEALTH_PERIOD_STATUS              0x8037
+
+
+
+  /* 4.3.2.46 Config Model App Bind
+     The Config Model App Bind is an acknowledged message used to bind an 
+      AppKey to a model.
+    The response to a Config Model App Bind message is a 
+      Config Model App Status message.
+
+  ElementAddress : 2B : Address of the element
+  AppKeyIndex : 2B : Index of the AppKey
+  ModelIdentifier : 2 or 4: SIG Model ID or Vendor Model ID */
+
+  { OPCODE_CONFIG_MODEL_APP_BIND, 6, 8, aNoInitParamDefault },
+  
+  /* 4.3.2.47 Config Model App Unbind
+     The Config Model App Unbind is an acknowledged message used to remove the 
+         binding between an AppKey and a model.
+     The response to a Config Model App Unbind message is a Config Model App Status message. 
+
+
+  ElementAddress : 2B : Address of the element
+  AppKeyIndex : 2B : Index of the AppKey
+  ModelIdentifier : 2 or 4: SIG Model ID or Vendor Model ID */
+  { OPCODE_CONFIG_MODEL_APP_UNBIND, 6, 8, aNoInitParamDefault },
+  
+  /* 4.3.2.31 Config NetKey Add
+    The Config NetKey Add is an acknowledged message used to add a NetKey 
+       to a NetKey List (see Section 4.2.4) on a node. 
+    The added NetKey is then used by the node to authenticate and decrypt messages it receives, as well as authenticate and encrypt messages it sends.
+    The response to a Config NetKey Add message is a Config NetKey Status message.
+    NetKeyIndex  : 2B
+    NetKey       : 16B NetKey  */
+  { OPCODE_CONFIG_NETKEY_ADD, 18, 18, aNoInitParamDefault },
+  
+  /* 4.3.2.33 Config NetKey Delete
+     The Config NetKey Delete is an acknowledged message used to delete a NetKey 
+     on a NetKey List from a node.
+     The response to a Config NetKey Delete message is a 
+        Config NetKey Status message. 
+    NetKeyIndex  : 2B  */
+  { OPCODE_CONFIG_NETKEY_DELETE, 2, 2, aNoInitParamDefault },
+
+  /* 4.3.2.35 Config NetKey Get
+     The Config NetKey Get is an acknowledged message used to report all NetKeys
+     known to the node.
+    The response to a Config NetKey Get message is a Config NetKey List message.
+    There are no Parameters for this message. */
+  { OPCODE_CONFIG_NETKEY_GET, 0, 0, aNoInitParamDefault },
+
+  /* 4.3.2.32 Config NetKey Update
+     The Config NetKey Update is an acknowledged message used to update a NetKey 
+     on a node. The updated NetKey is then used by the node to authenticate and 
+     decrypt messages it receives, as well as authenticate and encrypt messages 
+     it sends, as defined by the Key Refresh procedure (see Section 3.10.4).
+     The response to a Config NetKey Update message is a Config NetKey Status message. 
+    NetKeyIndex  : 2B  : Index of the NetKey
+    NetKey       : 16B : NetKey  */
+  { OPCODE_CONFIG_NETKEY_UPDATE, 18, 18, aNoInitParamDefault},
+  
+  /* 4.3.2.43 Config Node Identity Get
+     The Config Node Identity Get is an acknowledged message used to get the 
+           current Node Identity state for a subnet (see Section 4.2.12).
+       The response to a Config Node Identity Get message is a 
+            Config Node Identity Status message. 
+
+    NetKeyIndex  : 2B : Index of the NetKey */
+  { OPCODE_CONFIG_NODE_IDENTITY_GET, 2, 2, aNoInitParamDefault},
+  
+  /* 4.3.2.44 Config Node Identity Set
+    The Config Node Identity Set is an acknowledged message used to set the 
+        current Node Identity state for a subnet (see Section 4.2.12).
+     The response to a Config Node Identity Set message is a 
+         Config Node Identity Status message. 
+
+    NetKeyIndex : 2B : Index of the NetKey
+    Identity    : 1B : New Node Identity state */
+  { OPCODE_CONFIG_NODE_IDENTITY_SET, 3, 3, aNoInitParamDefault},
+
+  /* 4.3.2.53 Config Node Reset
+     The Config Node Reset is an acknowledged message used to reset a node 
+       (other than a Provisioner) and remove it from the network.
+     The response to a Config Node Reset message is a Config Node Reset 
+          Status message.
+     There are no Parameters for this message.  */
+  { OPCODE_CONFIG_NODE_RESET, 0, 0, aNoInitParamDefault },
+  
+  /* 4.3.2.49 Config SIG Model App Get
+     The Config SIG Model App Get is an acknowledged message used to request 
+       report of all AppKeys bound to the SIG Model.
+     The response to a Config SIG Model App Get message is a Config SIG Model 
+     App List message. 
+
+     ElementAddress  : 2B : Address of the element
+     ModelIdentifier : 2B : SIG Model ID */
+  { OPCODE_CONFIG_SIG_MODEL_APP_GET, 4, 4, aNoInitParamDefault },
+
+  /* 4.3.2.51 Config Vendor Model App Get
+     The Config Vendor Model App Get is an acknowledged message used to request 
+     report of all AppKeys bound to the model. This message is only for Vendor Models.
+     The response to a Config Vendor Model App Get message is a Config Vendor Model App List message 
+
+     ElementAddress  : 2B : Address of the element
+     ModelIdentifier : 4B : Vendor Model ID */ 
+  { OPCODE_CONFIG_VENDOR_MODEL_APP_GET, 6, 6, aNoInitParamDefault },
+
+};
+/* Private variables ---------------------------------------------------------*/
+
+eClientSendMsgState_t eClientSendMsgState; /* Keeps the state of Sent Message */
+eServerRespRecdState_t eServerRespRecdState; /* Keeps the state of Received Message */
+
+/* Private function prototypes -----------------------------------------------*/
+MOBLEUINT8 AppliConfigClient_SendMessageDefault(MOBLEUINT8 elementIdx);
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+* @brief  This function is callback from library after the Provisioning is 
+          completed by embedded Provisioner. 
+* @param  prvState: Provisioning State of the Node. Expecting "1" when the
+                   provisioning is completed
+* @retval None
+*/ 
+void Appli_ConfigClientStartNodeConfiguration(MOBLEUINT8 prvState)
+{
+  if (prvState==1 )
+  {
+    Appli_ConfigClient_Init();
+    eClientSendMsgState = ProvisioningDone_State;
+    NodeInfo.nodePrimaryAddress = GetAddressToConfigure();
+  }
+}
+
+/**
+* @brief  This function is Init function for the state machine of the 
+          Configuration Client. The Function shall be called everytime a new 
+          node is provisioned 
+* @param  None
+* @retval None
+*/ 
+MOBLE_RESULT Appli_ConfigClient_Init(void) 
+{
+  eClientSendMsgState = ClientIdle_State; /* Init the value of state machine  */ 
+  eServerRespRecdState = NodeIdle_State;  /* Init the value of state machine  */
+  ConfigClient_ResetTrials();
+  
+  return MOBLE_RESULT_SUCCESS;
+}
+
+/**
+* @brief  Appli_ConfigClient_Process: This function is Process function and 
+          shall be called from while(1) loop 
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT Appli_ConfigClient_Process(void) 
+{
+    
+  Appli_ConfigClient_ConfigureNode();
+  
+  return MOBLE_RESULT_SUCCESS;
+}
+
+
+/**
+* @brief  This function is used to configure the Node after provisioning
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT Appli_ConfigClient_ConfigureNode(void) 
+{
+  MOBLE_RESULT result = MOBLE_RESULT_SUCCESS;
+  MOBLEUINT32 nowClockTime;
+    
+    /* 
+    State                  response                   called function
+    --------------------------------------------------------------------------------
+    ClientIdle_State       X                               None
+    ProvisioningDone_State X                               Start the configuration
+    CompositionGet_State   ConfigRespInit_State       GetComposition
+    CompositionGet_State   CompositionRecd_State      ChangeThe State to next 
+    AppKeyAdd_State        X                          Issue AppKey
+    AppKeyAdd_State        AppkeyAck_State            ChangeThe State to next 
+    AppBindModel_State     X                          Issue AppKetBind
+    AppBindModel_State     AppBindModelAck_State      ChangeThe State to next 
+    AddSubscription_State  X                          Issue the Subscription 
+    AddSubscription_State  SubscriptionAck_State      ChangeThe State to next 
+    SetPublication_State   PublicationStatus_State    Issue the Subscription 
+    SetPublication_State   PublicationStatus_State    ChangeThe State to next 
+
+  */
+
+  /* If the Node is already configured, return from here  */
+  if (eClientSendMsgState == ConfigurationDone_State) 
+    return result;
+  
+  if (eClientSendMsgState == ClientIdle_State) 
+  {
+    /* Waiting for the Provisioning to be done before to Start the 
+       node configuration procedure */
+      return result;
+  }
+  
+  if (eServerRespRecdState == NodeNoResponse_State) 
+  {
+    /* No Response received from Node under Provisioning for some config 
+       messages. So, no need to do the trials  */
+      return MOBLE_RESULT_FAIL;
+  }
+  
+  if (eClientSendMsgState == ProvisioningDone_State) 
+  {
+    /* Start the node configuration procedure */
+    eClientSendMsgState = CompositionGet_State;
+    ConfigClient_SaveMsgSendingTime();
+  }
+  
+  else if (eClientSendMsgState == CompositionGet_State)
+  {
+
+     nowClockTime = Clock_Time();
+     if( (nowClockTime - NodeInfo.Initial_time) < CONFIGURATION_START_DELAY)
+     {
+       return result;
+     }
+     /*------------- Add the delay before to start the configuration messages */
+    
+    if (eServerRespRecdState == CompositionRecdCompleted_State)
+    {
+      eClientSendMsgState = AppKeyAdd_State;  /* Change the state to Next */
+      eServerRespRecdState = NodeIdle_State;
+    
+    }
+    else 
+    {
+      /* Continue the GetComposition servicing */
+      Appli_ConfigClient_GetCompositionData();
+    }
+  }
+  
+  else if (eClientSendMsgState == AppKeyAdd_State)
+  {
+    if (eServerRespRecdState == AppkeyAckCompleted_State)
+    {
+      eClientSendMsgState = AppBindModel_State;  /* Change the send state */
+      eServerRespRecdState = NodeIdle_State;
+    }
+    else
+    {
+      /* Continue the AppKeyAdd servicing */
+    Appli_ConfigClient_DefaultAppKeyAdd();
+  }
+  }  
+  
+  else if (eClientSendMsgState == AppBindModel_State)
+  {
+    if (eServerRespRecdState == AppBindModelAckCompleted_State)
+    {
+      eClientSendMsgState = AddSubscription_State;  /* Change the send state */
+      eServerRespRecdState = NodeIdle_State;
+    }
+    else
+    {
+       /* Continue the AppKeyBIND servicing */
+    Appli_ConfigClient_DefaultAppKeyBind();
+  }
+  }
+  
+  else if (eClientSendMsgState == AddSubscription_State)
+  {
+    if (eServerRespRecdState == SubscriptionAckCompleted_State)
+    {
+      eClientSendMsgState = SetPublication_State;  /* Change the send state */
+      eServerRespRecdState = NodeIdle_State;
+    }
+    else 
+    {
+      /* Continue the Subscription add servicing */
+    AppliConfigClient_SubscriptionAddDefault();
+    }    
+  }
+
+  else if (eClientSendMsgState == SetPublication_State)
+  {
+    if (eServerRespRecdState == PublicationStatusCompleted_State)
+    {
+      eClientSendMsgState = ConfigurationDone_State;  /* Change the send state */
+      eServerRespRecdState = NodeIdle_State;
+      TRACE_M(TF_CONFIG_CLIENT,"**Node is configured** \r\n");  
+    }
+    else 
+    {
+      /* Continue the Publication add servicing */
+    AppliConfigClient_PublicationSetDefault();
+    }
+  }
+  
+  return result;
+}
+
+
+
+
+/**
+* @brief  This function is called to Get The Composition data from the 
+*         a node under configuration
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT Appli_ConfigClient_GetCompositionData (void)
+{
+    MOBLE_RESULT result = MOBLE_RESULT_SUCCESS;
+    MOBLEUINT8 retry;
+    
+    switch(eServerRespRecdState)
+    {
+    case NodeIdle_State:
+
+      ConfigClient_SaveMsgSendingTime();
+      /* Start the Get Composition Message */
+      ConfigClient_CompositionDataGet();
+      
+      /* Switch to InProgress_State */
+      eServerRespRecdState = InProgress_State;
+      break;
+
+    case CompositionRecd_State:
+      /* Switch the state to next state AddAppKey_State */
+      ConfigClient_ResetTrials();
+      eServerRespRecdState = CompositionRecdCompleted_State;
+      break;
+      
+    case InProgress_State:
+      /* Just wait and let the messages be completed 
+         or look for timeout */
+
+      retry = ConfigClient_ChkRetries();
+      
+      if (retry == CLIENT_TX_RETRY_ENDS)
+      {
+        eServerRespRecdState = NodeNoResponse_State;
+      }
+      else if (retry == CLIENT_TX_TIMEOUT)
+      {
+        eServerRespRecdState = NodeIdle_State;    /* Run next re-trial cycle again */;
+      }
+      
+      break;
+      
+    default:
+      /* Error State */
+      break;
+    }
+    
+  return result;
+}
+
+
+/**
+* @brief  Appli_ConfigClient_DefaultAppKeyAdd: This function is called to 
+          add the default AppKeys and net keys to a node under configuration
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT Appli_ConfigClient_DefaultAppKeyAdd (void)
+{
+   MOBLE_RESULT result = MOBLE_RESULT_SUCCESS;
+  MOBLEUINT8 retry; 
+   MOBLEUINT8 *pAppKey;  
+   MOBLEUINT16 netKeyIndex = DEFAULT_NETKEY_INDEX;
+   MOBLEUINT16 appKeyIndex = DEFAULT_APPKEY_INDEX;
+
+   pAppKey = GetNewProvNodeAppKey();
+   
+    switch(eServerRespRecdState)
+    {
+    case NodeIdle_State:
+      ConfigClient_SaveMsgSendingTime();
+      /* Start the Set Appkey message  */
+      ConfigClient_AppKeyAdd (netKeyIndex, 
+                                  appKeyIndex,
+                                  pAppKey);
+      /* Switch to InProgress_State */
+      eServerRespRecdState = InProgress_State; 
+      break;
+
+    case AppkeyAck_State:
+      ConfigClient_ResetTrials();
+      eServerRespRecdState = AppkeyAckCompleted_State;
+      break;
+      
+    case InProgress_State:
+      /* Just wait and let the messages be completed 
+         or look for timeout */
+
+      retry = ConfigClient_ChkRetries();
+      
+      if (retry == CLIENT_TX_RETRY_ENDS)
+      {
+        eServerRespRecdState = NodeNoResponse_State;
+      }
+      else if (retry == CLIENT_TX_TIMEOUT)
+      {
+        eServerRespRecdState = NodeIdle_State;    /* Run next re-trial cycle again */;
+      }
+
+      break;
+
+    default:
+      /* Error State */
+      break;
+}
+
+  return result;
+}
+
+/**
+* @brief  Appli_ConfigClient_DefaultAppKeyBind: This function is application used for 
+          function to Bind the element(node) with AppKeyIndex and Models
+* @param  pGeneric_OnOffParam: Pointer to the parameters received for message
+* @param  OptionalValid: Flag to inform about the validity of optional parameters 
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT Appli_ConfigClient_DefaultAppKeyBind (void)
+{
+
+    /* 
+    ElementAddress : 2B : Address of the element
+    AppKeyIndex : 2B : Index of the AppKey
+    ModelIdentifier : 2 or 4: SIG Model ID or Vendor Model ID
+    */   
+   static MOBLEUINT32 modelIdentifier;
+   static MOBLEUINT8 elementIndex;
+   static MOBLEUINT8  indexSIGmodels;
+   static MOBLEUINT8  indexVendormodels;
+   MOBLEUINT16 elementAddress;
+   MOBLEUINT16 appKeyIndex = DEFAULT_APPKEY_INDEX;
+
+   MOBLEUINT8  numSIGmodels;
+   MOBLEUINT8  numVendorModels;
+   MOBLEUINT8  numofElements;        
+   MOBLE_RESULT result = MOBLE_RESULT_SUCCESS;
+   MOBLEUINT8 retry;  
+  
+    switch(eServerRespRecdState)
+    {
+    case NodeIdle_State:
+      /* Start the AppBindModel_State message  */
+        elementIndex = 0; /* Initialize it for the complete loop */
+        indexSIGmodels = 0; /* Initialize it for the complete loop */
+        indexVendormodels = 0;
+        modelIdentifier = GetSIGModelToBindApp(elementIndex,indexSIGmodels );
+        /* Switch to NodeSendMessage_State */
+        eServerRespRecdState = NodeSendMessage_State;
+      break;
+
+     case NodeSendMessage_State:
+      /* Start the AppBindModel_State message  */
+        elementAddress = GetServerElementAddress(elementIndex);
+        ConfigClient_SaveMsgSendingTime();
+
+        /* Switch to InProgress_State */
+        eServerRespRecdState = InProgress_State;
+        /* Send the Message to the server */
+        ConfigClient_ModelAppBind (elementAddress, appKeyIndex, modelIdentifier);
+      break;
+
+    case AppBindModelAck_State:
+       /* Need to check if all SIG Models are binded ? */
+
+      ConfigClient_ResetTrials();
+            
+      numSIGmodels = GetCountSIGModelToBindApp(elementIndex);
+      numVendorModels = GetCountVendorModelToBindApp(elementIndex);
+      
+      if (indexSIGmodels < numSIGmodels )
+      { /* Even when all SIG Models are serviced, we need to start for Vendor Models */
+        indexSIGmodels++; 
+        indexVendormodels =0;  /* Reset back, bcoz, we are still process the SIG Models */
+      }
+      else if (indexVendormodels < numVendorModels)
+      {
+        indexVendormodels++; /* When SIG Models and Vendor Models are processed
+                                the loop condition will become true */
+      }
+      
+      if (indexSIGmodels < numSIGmodels )
+      {/* if index is still less, then we have scope of reading 1 more index */
+       
+        /* Get the Next Model and Bind it again till all SIG Models are binded */
+        modelIdentifier = GetSIGModelToBindApp(elementIndex,indexSIGmodels );
+        eServerRespRecdState = NodeSendMessage_State;
+        /* Switch to InProgress_State */
+      }
+      else if (indexVendormodels < numVendorModels)
+      {
+        /*Now, do binding for Vendor Model */
+        modelIdentifier = GetVendorModelToBindApp(elementIndex,indexVendormodels );
+        eServerRespRecdState = NodeSendMessage_State;
+      }
+      else
+      {
+        /* Now, the element index is handled, change the element index */
+        elementIndex++;
+        numofElements = ConfigClient_GetNodeElements();  
+        if (elementIndex >=  numofElements)
+        {/* we are comparing Index whose counting started from 0, becomes equal, 
+            then exit the loop */
+          
+           eServerRespRecdState = AppBindModelAckCompleted_State; 
+        }
+        else if (elementIndex < numofElements)
+        { /* When the Element Index is still less than the total number of 
+             elements in the Node: So, Restart the cycle */
+        
+          eServerRespRecdState = NodeIdle_State; 
+      }
+      }
+      break;
+      
+    case InProgress_State:
+      /* Just wait and let the messages be completed 
+         or look for timeout */
+      retry = ConfigClient_ChkRetries();
+      
+      if (retry == CLIENT_TX_RETRY_ENDS)
+      {
+        eServerRespRecdState = NodeNoResponse_State;
+      }
+      else if (retry == CLIENT_TX_TIMEOUT)
+      {
+        eServerRespRecdState = NodeSendMessage_State; /* Run next re-trial cycle again */;
+      }
+      break;
+     
+    default:
+      /* Error State */
+      break;
+    }
+    
+  return result;
+}
+
+
+/**
+* @brief  AppliConfigClient_SubscriptionAddDefault: This function is application
+          used for adding subscription to the element(node) for default settings
+* @param  pGeneric_OnOffParam: Pointer to the parameters received for message
+* @param  OptionalValid: Flag to inform about the validity of optional parameters 
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT AppliConfigClient_SubscriptionAddDefault (void) 
+{
+   static MOBLEUINT32 modelIdentifier;
+   static MOBLEUINT16 elementAddress;
+   static MOBLEUINT8 elementIndex;
+   static MOBLEUINT8  indexSIGmodels;
+   static MOBLEUINT8  indexVendormodels;
+   MOBLEUINT8  numSIGmodels;
+   MOBLEUINT8  numVendorModels;
+   MOBLEUINT8  numofElements;        
+   MOBLEUINT16 address = DEFAULT_GROUP_ADDR;
+   MOBLE_RESULT result = MOBLE_RESULT_SUCCESS;
+   MOBLEUINT8 retry; 
+      
+    switch(eServerRespRecdState)
+    {
+    case NodeIdle_State:
+      /* Start the SubscriptionAdd message  */
+
+        elementIndex = 0; /* Initialize it for the complete loop */
+        indexSIGmodels = 0; /* Initialize it for the complete loop */
+        indexVendormodels = 0;
+        modelIdentifier = GetSIGModelToSubscribe(elementIndex,indexSIGmodels );
+        /* Switch to NodeSendMessage_State */
+        eServerRespRecdState = NodeSendMessage_State;
+      break;
+
+    case NodeSendMessage_State:
+        elementAddress = GetServerElementAddress(elementIndex);
+        ConfigClient_SaveMsgSendingTime();
+
+         /* Switch to InProgress_State */
+        eServerRespRecdState = InProgress_State;        
+        ConfigClient_SubscriptionAdd (elementAddress, address, modelIdentifier);
+      
+      break;
+
+       
+    case SubscriptionAck_State:
+       /* Need to check if all SIG Models are subscribed ? */
+      ConfigClient_ResetTrials();
+
+      numSIGmodels = GetCountSIGModelToSubscribe(elementIndex);
+      numVendorModels = GetCountVendorModelToSubscribe(elementIndex);
+      elementAddress = GetServerElementAddress(elementIndex);
+      
+      if (indexSIGmodels < numSIGmodels )
+      { /* Even when all SIG Models are serviced, we need to start for Vendor Models */
+        indexSIGmodels++; 
+        indexVendormodels =0;  /* Reset back, bcoz, we are still process the SIG Models */
+      }
+      else if (indexVendormodels < numVendorModels)
+      {
+        indexVendormodels++; /* When SIG Models and Vendor Models are processed
+                                the loop condition will become true */
+      }
+      
+      if (indexSIGmodels < numSIGmodels )
+      {/* if index is still less, then we have scope of reading 1 more index */
+       
+        /* Get the Next Model and Bind it again till all SIG Models are binded */
+        modelIdentifier = GetSIGModelToSubscribe(elementIndex,indexSIGmodels);
+        eServerRespRecdState = NodeSendMessage_State;
+        
+      }
+      else if (indexVendormodels < numVendorModels)
+{
+        modelIdentifier = GetVendorModelToSubscribe(elementIndex,indexVendormodels );
+        eServerRespRecdState = NodeSendMessage_State;
+        
+      }
+      else
+      {
+        /* Now, the element index is handled, change the element index */
+        elementIndex++;
+        numofElements = ConfigClient_GetNodeElements();  
+        if (elementIndex ==  numofElements)
+        {/* we are comparing Index whose counting started from 0, becomes equal, 
+            then exit the loop */
+           eServerRespRecdState = SubscriptionAckCompleted_State; 
+        }
+        else if (elementIndex < numofElements)
+        { /* When the Element Index is still less than the total number of 
+             elements in the Node: So, Restart the cycle */
+        
+          eServerRespRecdState = NodeIdle_State; 
+          indexSIGmodels =0; /* Reset the variable again for the next element */
+        indexVendormodels = 0;
+      }
+      }
+      break;
+      
+    case InProgress_State:
+      /* Just wait and let the messages be completed 
+         or look for timeout */
+      retry = ConfigClient_ChkRetries();
+      
+      if (retry == CLIENT_TX_RETRY_ENDS)
+      {
+        eServerRespRecdState = NodeNoResponse_State;
+      }
+      else if (retry == CLIENT_TX_TIMEOUT)
+      {
+        eServerRespRecdState = NodeSendMessage_State; /* Run next re-trial cycle again */;
+      }
+      break;
+      
+    default:
+      /* Error State */
+      break;
+    }
+    
+  return result;
+}
+
+/**
+* @brief  AppliConfigClient_PublicationSetDefault: This function is application
+          used for adding publication settings to the element(node) 
+          for default settings
+* @param  pGeneric_OnOffParam: Pointer to the parameters received for message
+* @param  OptionalValid: Flag to inform about the validity of optional parameters 
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT AppliConfigClient_PublicationSetDefault (void) 
+{
+  MOBLEUINT16 publishAddress = DEFAULT_PUBLISH_ADDR;
+  MOBLEUINT16 appKeyIndex = DEFAULT_APPKEY_INDEX;
+  MOBLEUINT8 credentialFlag = DEFAULT_CREDENTIAL_FLAG;
+  MOBLEUINT8 publishTTL = DEFAULT_PUBLISH_TTL;
+  MOBLEUINT8 publishPeriod = DEFAULT_PUBLISH_PERIOD;
+  MOBLEUINT8 publishRetransmitCount = DEFAULT_PUBLISH_RETRANSMIT_COUNT;
+  MOBLEUINT8 publishRetransmitIntervalSteps= DEFAULT_PUBLISH_RETRANSMIT_INTERVAL_STEPS;
+  
+   static MOBLEUINT16 elementAddress;
+   static MOBLEUINT32 modelIdentifier;
+   static MOBLEUINT8 elementIndex;
+   static MOBLEUINT8  indexSIGmodels;
+   static MOBLEUINT8  indexVendormodels;
+   MOBLEUINT8  numSIGmodels;
+   MOBLEUINT8  numVendorModels;
+   MOBLEUINT8  numofElements;        
+   MOBLE_RESULT result = MOBLE_RESULT_SUCCESS;
+   MOBLEUINT8 retry; 
+      
+    switch(eServerRespRecdState)
+    {
+    case NodeIdle_State:
+      /* Start the Publication Add message  */
+
+        elementIndex = 0; /* Initialize it for the complete loop */
+        indexSIGmodels = 0; /* Initialize it for the complete loop */
+        indexVendormodels = 0;
+        modelIdentifier = GetSIGModelToPublish(elementIndex,indexSIGmodels );
+         /* Switch to NodeSendMessage_State */
+        eServerRespRecdState = NodeSendMessage_State;        
+        
+      break;
+
+    case NodeSendMessage_State:
+        elementAddress = GetServerElementAddress(elementIndex);
+
+        ConfigClient_SaveMsgSendingTime();
+
+         /* Switch to InProgress_State */
+        eServerRespRecdState = InProgress_State;        
+        ConfigClient_PublicationSet(elementAddress,
+                              publishAddress,
+                              appKeyIndex,
+                              credentialFlag,
+                              publishTTL,
+                              publishPeriod,
+                              publishRetransmitCount,
+                              publishRetransmitIntervalSteps,
+                              modelIdentifier);
+
+      break;
+
+      
+    case PublicationStatus_State:
+       /* Need to check if all SIG Models are subscribed ? */
+      ConfigClient_ResetTrials();
+
+      numSIGmodels = GetCountSIGModelToPublish(elementIndex);
+      numVendorModels = GetCountVendorModelToPublish(elementIndex);
+      elementAddress = GetServerElementAddress(elementIndex);
+      
+      if (indexSIGmodels < numSIGmodels )
+      { /* Even when all SIG Models are serviced, we need to start for Vendor Models */
+        indexSIGmodels++; 
+        indexVendormodels =0;  /* Reset back, bcoz, we are still process the SIG Models */
+      }
+      else if (indexVendormodels < numVendorModels)
+      {
+        indexVendormodels++; /* When SIG Models and Vendor Models are processed
+                                the loop condition will become true */
+      }
+
+      
+      if (indexSIGmodels < numSIGmodels )
+      {/* if index is still less, then we have scope of reading 1 more index */
+       
+        /* Get the Next Model and Bind it again till all SIG Models are binded */
+        modelIdentifier = GetSIGModelToPublish(elementIndex,indexSIGmodels);
+        eServerRespRecdState = NodeSendMessage_State;        
+        
+      }
+      else if (indexVendormodels < numVendorModels)
+      {
+        modelIdentifier = GetVendorModelToPublish(elementIndex,indexVendormodels );
+        eServerRespRecdState = NodeSendMessage_State;        
+
+      }
+      else
+      {
+        /* Now, the element index is handled, change the element index */
+        elementIndex++;
+        numofElements = ConfigClient_GetNodeElements();  
+        if (elementIndex ==  numofElements)
+        {/* we are comparing Index whose counting started from 0, becomes equal, 
+            then exit the loop */
+           eServerRespRecdState = PublicationStatusCompleted_State; 
+        }
+        else if (elementIndex < numofElements)
+        { /* When the Element Index is still less than the total number of 
+             elements in the Node: So, Restart the cycle */
+        
+          eServerRespRecdState = NodeIdle_State; 
+          indexSIGmodels =0; /* Reset the variable again for the next element */
+        indexVendormodels = 0;
+      }
+      }
+      break;
+      
+    case InProgress_State:
+      /* Just wait and let the messages be completed 
+         or look for timeout */
+      retry = ConfigClient_ChkRetries();
+      
+      if (retry == CLIENT_TX_RETRY_ENDS)
+      {
+        eServerRespRecdState = NodeNoResponse_State;
+      }
+      else if (retry == CLIENT_TX_TIMEOUT)
+      {
+        eServerRespRecdState = NodeSendMessage_State; /* Run next re-trial cycle again */;
+      }
+      break;
+      
+    default:
+      /* Error State */
+      break;
+    }
+
+  return result;
+}
+
+/**
+* @brief  AppliConfigClient_PublicationSetDefault: This function is application
+          used for adding publication settings to the element(node) 
+          for default settings
+* @param  pGeneric_OnOffParam: Pointer to the parameters received for message
+* @param  OptionalValid: Flag to inform about the validity of optional parameters 
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT AppliConfigClient_SelfPublicationSetDefault (void) 
+{
+  MOBLEUINT16 publishAddress = DEFAULT_PUBLISH_ADDR;
+  MOBLEUINT16 appKeyIndex = DEFAULT_APPKEY_INDEX;
+  MOBLEUINT8 credentialFlag = DEFAULT_CREDENTIAL_FLAG;
+  MOBLEUINT8 publishTTL = DEFAULT_PUBLISH_TTL;
+  MOBLEUINT8 publishPeriod = DEFAULT_PUBLISH_PERIOD;
+  MOBLEUINT8 publishRetransmitCount = DEFAULT_PUBLISH_RETRANSMIT_COUNT;
+  MOBLEUINT8 publishRetransmitIntervalSteps= DEFAULT_PUBLISH_RETRANSMIT_INTERVAL_STEPS;
+ 
+  MOBLEUINT16 elementAddress;
+  MOBLEUINT32 modelIdentifier;
+  MOBLEUINT8  numSIGmodels;
+  MOBLE_RESULT result = MOBLE_RESULT_SUCCESS;
+  
+  numSIGmodels = sizeof(aPublishModels)/sizeof(MOBLEUINT16);
+  
+  for (MOBLEUINT8 index=0; index < numSIGmodels;  index++)
+  {
+    /* Start the Publication Add message  */
+    elementAddress = BLEMesh_GetAddress();
+    modelIdentifier = 0;
+    modelIdentifier = (MOBLEUINT16) aPublishModels[index];
+    
+    /* Switch to InProgress_State */
+    ConfigClient_PublicationSet(elementAddress,
+                                publishAddress,
+                                appKeyIndex,
+                                credentialFlag,
+                                publishTTL,
+                                publishPeriod,
+                                publishRetransmitCount,
+                                publishRetransmitIntervalSteps,
+                                modelIdentifier);
+  }
+  
+  return result;
+}
+
+
+/**
+* @brief  AppliConfigClient_PublicationSetDefault: This function is application
+          used for adding publication settings to the element(node) 
+          for default settings
+* @param  pGeneric_OnOffParam: Pointer to the parameters received for message
+* @param  OptionalValid: Flag to inform about the validity of optional parameters 
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT AppliConfigClient_SelfSubscriptionSetDefault (void) 
+{
+  MOBLEUINT32 modelIdentifier;
+  MOBLEUINT16 elementAddress;
+  MOBLEUINT8  numSIGmodels;
+  MOBLEUINT16 address = DEFAULT_GROUP_ADDR;
+  MOBLE_RESULT result = MOBLE_RESULT_SUCCESS;
+  
+  numSIGmodels = sizeof(aSubscribeModels)/sizeof(MOBLEUINT16);
+  
+  for (MOBLEUINT8 index=0; index < numSIGmodels;  index++)
+  {
+    /* Start the Publication Add message  */
+    elementAddress = BLEMesh_GetAddress();
+    modelIdentifier = 0;
+    modelIdentifier = (MOBLEUINT16) aSubscribeModels[index];
+    
+    ConfigClient_SubscriptionAdd (elementAddress, address, modelIdentifier);
+  }
+  
+  return result; 
+}
+
+/**
+* @brief  Appli_ConfigClient_DefaultAppKeyBind: This function is application used for 
+          function to Bind the element(node) with AppKeyIndex and Models
+* @param  pGeneric_OnOffParam: Pointer to the parameters received for message
+* @param  OptionalValid: Flag to inform about the validity of optional parameters 
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT Appli_ConfigClient_SelfDefaultAppKeyBind (void)
+{
+  
+  /* 
+  ElementAddress : 2B : Address of the element
+  AppKeyIndex : 2B : Index of the AppKey
+  ModelIdentifier : 2 or 4: SIG Model ID or Vendor Model ID
+  */  
+  MOBLEUINT32 modelIdentifier;
+  MOBLEUINT16 appKeyIndex = DEFAULT_APPKEY_INDEX;
+  MOBLEUINT16 elementAddress;
+  MOBLEUINT8  numSIGmodels;
+  MOBLE_RESULT result = MOBLE_RESULT_SUCCESS;
+  appKeyIndex = DEFAULT_APPKEY_INDEX;
+  
+  numSIGmodels = sizeof(aSigModelsToBind)/sizeof(MOBLEUINT16);
+  
+  for (MOBLEUINT8 index=0; index < numSIGmodels;  index++)
+  {
+    elementAddress = BLEMesh_GetAddress();
+    modelIdentifier = 0;
+    modelIdentifier = (MOBLEUINT16) aSigModelsToBind[index];
+    ConfigClient_ModelAppBind (elementAddress, appKeyIndex, modelIdentifier);
+  }      
+  
+  return result;
+}
+
+/**
+* @brief  Appli_CompositionDataStatusCb: This function is callback from config 
+         client middleware on reception of the response
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+void Appli_CompositionDataStatusCb(MOBLE_RESULT status)
+{
+   eServerRespRecdState = CompositionRecd_State;
+}
+
+/**
+* @brief  Appli_AppKeyStatusCb: This function is callback from config 
+         client middleware on reception of the response
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+void Appli_AppKeyStatusCb(MOBLEUINT8 status)
+{
+   /* Change the received state for application  */
+   eServerRespRecdState = AppkeyAck_State;
+}
+
+/**
+* @brief  Appli_AppBindModelStatusCb: This function is callback from config 
+         client middleware on reception of the response
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+void Appli_AppBindModelStatusCb(MOBLEUINT8 status)
+{
+   /* Change the received state for application  */
+   eServerRespRecdState = AppBindModelAck_State;
+}
+
+/**
+* @brief  Appli_SubscriptionAddStatusCb: This function is callback from config 
+         client middleware on reception of the response
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+void Appli_SubscriptionAddStatusCb(MOBLEUINT8 status)
+{
+   /* Change the received state for application  */
+   eServerRespRecdState = SubscriptionAck_State;
+}
+
+/**
+* @brief  Appli_PublicationStatusCb: This function is callback from config 
+         client middleware on reception of the response
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+void Appli_PublicationStatusCb(MOBLEUINT8 status)
+{
+   /* Change the received state for application  */
+   eServerRespRecdState = PublicationStatus_State;
+}
+
+/**
+* @brief  Appli_NodeResetStatusCb: This function is callback from config 
+         client middleware on reception of the Node Reset response
+* @param  None
+* @retval None
+*/ 
+void Appli_NodeResetStatusCb(void)
+{
+   /* Change the received state for application  */
+   eServerRespRecdState = NodeResetStatus_State;
+}
+
+/**
+* @brief  GetSIGModelToBindApp: This function gets the SIG Model to Bind 
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+MOBLEUINT16 GetSIGModelToBindApp(MOBLEUINT8 elementIdx, MOBLEUINT8 idxSIG)
+{
+#ifdef CONFIGURE_AS_PER_COMPOSITION_DATA
+#else  
+  return aSigModelsToBind[idxSIG] ; 
+#endif  
+}
+
+/**
+* @brief  GetVendorModelToBindApp: This function gets the Vendor Model to Bind 
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+MOBLEUINT32 GetVendorModelToBindApp(MOBLEUINT8 elementIdx, MOBLEUINT8 idxSIG)
+{
+#ifdef CONFIGURE_AS_PER_COMPOSITION_DATA
+#else 
+  return VENDORMODEL_STMICRO_ID1 ; 
+#endif
+}
+/**
+* @brief  GetSIGModelToBindApp: This function gets the SIG Model to Bind 
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+MOBLEUINT8 GetCountSIGModelToBindApp(MOBLEUINT8 elementIdx)
+{
+#ifdef CONFIGURE_AS_PER_COMPOSITION_DATA
+#else   
+  return sizeof(aSigModelsToBind)/sizeof(MOBLEUINT16); 
+#endif  
+}
+
+/**
+* @brief  GetSIGModelToBindApp: This function gets the SIG Model to Bind 
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+MOBLEUINT8 GetCountVendorModelToBindApp(MOBLEUINT8 elementIdx)
+{
+#ifdef CONFIGURE_AS_PER_COMPOSITION_DATA
+#else  
+  return NUM_VENDOR_MODELS_TO_BIND_APP; 
+#endif
+}
+
+
+/**
+* @brief  GetSIGModelToBindApp: This function gets the SIG Model to Bind 
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+MOBLEUINT16 GetSIGModelToPublish(MOBLEUINT8 elementIdx, MOBLEUINT8 idxSIG)
+{
+#ifdef CONFIGURE_AS_PER_COMPOSITION_DATA
+#else  
+  return aPublishModels[idxSIG] ; 
+#endif  
+}
+
+/**
+* @brief  GetVendorModelToPublish: This function gets the SIG Model to Bind 
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+MOBLEUINT32 GetVendorModelToPublish(MOBLEUINT8 elementIdx, MOBLEUINT8 idxSIG)
+{
+#ifdef CONFIGURE_AS_PER_COMPOSITION_DATA
+#else   
+  return VENDORMODEL_STMICRO_ID1 ; 
+#endif  
+}
+
+/**
+* @brief  GetCountSIGModelToPublish: This function gets the SIG Model to Bind 
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+MOBLEUINT8 GetCountSIGModelToPublish(MOBLEUINT8 elementIdx)
+{
+#ifdef CONFIGURE_AS_PER_COMPOSITION_DATA
+#else   
+  return sizeof(aPublishModels)/sizeof(MOBLEUINT16); 
+#endif  
+}
+
+/**
+* @brief  GetCountVendorModelToPublish: This function gets the SIG Model to Bind 
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+MOBLEUINT8 GetCountVendorModelToPublish(MOBLEUINT8 elementIdx)
+{
+#ifdef CONFIGURE_AS_PER_COMPOSITION_DATA
+#else   
+  return NUM_VENDOR_MODELS_TO_PUBLISH; 
+#endif    
+}
+
+/**
+* @brief  GetSIGModelToBindApp: This function gets the SIG Model to Bind 
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+MOBLEUINT16 GetSIGModelToSubscribe(MOBLEUINT8 elementIdx, MOBLEUINT8 idxSIG)
+{
+#ifdef CONFIGURE_AS_PER_COMPOSITION_DATA
+#else    
+  return aSubscribeModels[idxSIG] ; 
+#endif  
+}
+
+/**
+* @brief  GetSIGModelToBindApp: This function gets the SIG Model to Bind 
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+MOBLEUINT32 GetVendorModelToSubscribe(MOBLEUINT8 elementIdx, MOBLEUINT8 idxSIG)
+{
+#ifdef CONFIGURE_AS_PER_COMPOSITION_DATA
+#else   
+  return VENDORMODEL_STMICRO_ID1 ; 
+#endif  
+}
+
+/**
+* @brief  GetCountSIGModelToPublish: This function gets the SIG Model to Bind 
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+MOBLEUINT8 GetCountSIGModelToSubscribe(MOBLEUINT8 elementIdx)
+{
+#ifdef CONFIGURE_AS_PER_COMPOSITION_DATA
+#else   
+  return sizeof(aSubscribeModels)/sizeof(MOBLEUINT16); 
+#endif  
+}
+
+/**
+* @brief  GetCountVendorModelToPublish: This function gets the SIG Model to Bind 
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+MOBLEUINT8 GetCountVendorModelToSubscribe(MOBLEUINT8 elementIdx)
+{
+#ifdef CONFIGURE_AS_PER_COMPOSITION_DATA
+#else  
+  return NUM_VENDOR_MODELS_TO_SUBSCRIBE; 
+#endif    
+}
+
+/**
+* @brief  AppliConfigClient_SendMessageDefault: This function gets the SIG Model to Bind 
+* @param  None
+* @retval MOBLE_RESULT
+*/ 
+MOBLEUINT8 AppliConfigClient_SendMessageDefault(MOBLEUINT8 elementIdx)
+{
+  return NUM_VENDOR_MODELS_TO_SUBSCRIBE; 
+}
+
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/******************* (C) COPYRIGHT 2017 STMicroelectronics *****END OF FILE****/
+
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_config_client.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_config_client.h
new file mode 100644
index 000000000..d9465958b
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_config_client.h
@@ -0,0 +1,75 @@
+/**
+******************************************************************************
+* @file    appli_config_client.h
+* @author  BLE Mesh Team
+* @brief   Application interface for Generic Mesh Models  
+******************************************************************************
+* @attention
+*
+* 
    © Copyright (c) 2019 STMicroelectronics.
+* All rights reserved.
    
+*
+* This software component is licensed by ST under Ultimate Liberty license
+* SLA0044, the "License"; You may not use this file except in compliance with
+* the License. You may obtain a copy of the License at:
+*                             www.st.com/SLA0044
+*
+******************************************************************************
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APPLI_CONFIG_CLIENT_H
+#define __APPLI_CONFIG_CLIENT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "types.h"
+#include "generic.h"
+#include "mesh_cfg.h"
+#include "config_client.h"
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported variables  ------------------------------------------------------- */
+/* Application Variable-------------------------------------------------------*/
+/* Exported Functions Prototypes ---------------------------------------------*/
+MOBLE_RESULT Appli_ConfigClient_Init(void);
+MOBLE_RESULT Appli_ConfigClient_Process(void);
+MOBLE_RESULT Appli_ConfigClient_ConfigureNode(void);
+void Appli_CompositionDataStatusCb(MOBLE_RESULT); 
+void Appli_AppKeyStatusCb(MOBLEUINT8 status);
+void Appli_AppBindModelStatusCb(MOBLEUINT8 status);
+void Appli_PublicationStatusCb(MOBLEUINT8 status);
+void Appli_SubscriptionAddStatusCb(MOBLEUINT8 status);
+void Appli_NodeResetStatusCb(void);
+
+void Appli_ConfigClientStartNodeConfiguration(MOBLEUINT8 prvState);
+MOBLE_RESULT Appli_ConfigClient_GetCompositionData (void);
+MOBLE_RESULT Appli_ConfigClient_DefaultAppKeyAdd (void);
+MOBLE_RESULT Appli_ConfigClient_DefaultAppKeyBind (void);
+MOBLE_RESULT AppliConfigClient_SubscriptionAddDefault (void);
+MOBLE_RESULT AppliConfigClient_PublicationSetDefault (void);
+MOBLE_RESULT AppliConfigClient_SelfPublicationSetDefault (void); 
+MOBLE_RESULT AppliConfigClient_SelfSubscriptionSetDefault (void);
+MOBLE_RESULT Appli_ConfigClient_SelfDefaultAppKeyBind (void);
+Composition_Data_Page0_t* Appli_GetNodeCompositionBuff (void);
+
+MOBLEUINT16 GetSIGModelToBindApp(MOBLEUINT8 elementIdx, MOBLEUINT8 idxSIG);
+MOBLEUINT32 GetVendorModelToBindApp(MOBLEUINT8 elementIdx, MOBLEUINT8 idxSIG);
+MOBLEUINT8 GetCountSIGModelToBindApp(MOBLEUINT8 elementIdx);
+MOBLEUINT8 GetCountVendorModelToBindApp(MOBLEUINT8 elementIdx);
+
+MOBLEUINT16 GetSIGModelToSubscribe(MOBLEUINT8 elementIdx, MOBLEUINT8 idxSIG);
+MOBLEUINT32 GetVendorModelToSubscribe(MOBLEUINT8 elementIdx, MOBLEUINT8 idxSIG);
+MOBLEUINT8 GetCountSIGModelToSubscribe(MOBLEUINT8);
+MOBLEUINT8 GetCountVendorModelToSubscribe(MOBLEUINT8);
+
+MOBLEUINT16 GetSIGModelToPublish(MOBLEUINT8 elementIdx, MOBLEUINT8 idxSIG);
+MOBLEUINT32 GetVendorModelToPublish(MOBLEUINT8 elementIdx, MOBLEUINT8 idxSIG);
+MOBLEUINT8 GetCountSIGModelToPublish(MOBLEUINT8 elementIdx);
+MOBLEUINT8 GetCountVendorModelToPublish(MOBLEUINT8 elementIdx);
+
+
+#endif /* __APPLI_CONFIG_CLIENT_H */
+
+/******************* (C) COPYRIGHT 2017 STMicroelectronics *****END OF FILE****/
+
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_generic.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_generic.c
index 7afb360a4..082e7d11f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_generic.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_generic.c
@@ -31,11 +31,12 @@
 #include "common.h"
 #include "mesh_cfg_usr.h"
 #include "appli_nvm.h"
-/** @addtogroup BLE_Mesh
+
+/** @addtogroup ST_BLE_Mesh
  *  @{
  */
 
-/** @addtogroup models_BLE
+/** @addtogroup Application_Mesh_Models
  *  @{
  */
 
@@ -44,12 +45,11 @@
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
    
-MOBLEUINT8 RestoreFlag;
+extern MOBLEUINT8 RestoreFlag;
 extern MOBLEUINT16 IntensityValue;
 extern MOBLEUINT8 IntensityFlag;
 extern MOBLEUINT8 PowerOnOff_flag;
 extern Appli_LightPwmValue_t Appli_LightPwmValue;
-
 Appli_Generic_OnOffSet AppliOnOffSet;
 Appli_Generic_LevelSet AppliLevelSet;
 Appli_Generic_PowerOnOffSet AppliPowerOnSet;
@@ -105,8 +105,6 @@ MOBLE_RESULT Appli_Generic_OnOff_Set(Generic_OnOffStatus_t* pGeneric_OnOffParam,
     } 
   }
 
-  
-
   TRACE_M(TF_SERIAL_CTRL,"#8202%02hx!\n\r",AppliOnOffSet.Present_OnOff);
 
   /* set the flag value for NVM store */
@@ -116,6 +114,25 @@ MOBLE_RESULT Appli_Generic_OnOff_Set(Generic_OnOffStatus_t* pGeneric_OnOffParam,
     
   return MOBLE_RESULT_SUCCESS;
 }
+
+
+
+/**
+* @brief  Appli_Generic_OnOff_Set: This function is callback for Application
+*          when Generic OnOff message is received
+* @param  pOnOff_status: Pointer to the parameters received for message
+* @param  plength: length of the data 
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT Appli_Generic_OnOff_Status(MOBLEUINT8 const *pOnOff_status, MOBLEUINT32 plength)
+{
+  TRACE_M(TF_GENERIC,"Appli_Generic_OnOff_Status callback received \r\n");
+  
+  TRACE_M(TF_SERIAL_CTRL,"#8204! \n\r");
+  
+  return MOBLE_RESULT_SUCCESS;
+}
+
 #endif
 
 #ifdef ENABLE_GENERIC_MODEL_SERVER_LEVEL
@@ -200,6 +217,7 @@ MOBLE_RESULT Appli_Generic_LevelDelta_Set(Generic_LevelStatus_t* pdeltalevelPara
     Light_UpdateLedValue(RESET_STATE , Appli_LightPwmValue);
     BSP_LED_Off(LED_BLUE);
   }
+  TRACE_M(TF_SERIAL_CTRL,"#8206!\n\r");
   return MOBLE_RESULT_SUCCESS;
 }
 
@@ -219,6 +237,24 @@ MOBLE_RESULT Appli_Generic_LevelMove_Set(Generic_LevelStatus_t* pdeltaMoveParam,
   {
     AppliLevelSet.Present_Level16= pdeltaMoveParam->Present_Level16;   
   }
+   TRACE_M(TF_SERIAL_CTRL,"#8206!\n\r");
+  
+  return MOBLE_RESULT_SUCCESS;
+  
+}
+  /**
+* @brief  Appli_Generic_Level_Status: This function is callback for Application
+*          when Generic Level Move message is received
+* @param  plevel_status: Pointer to the parameters message
+* @param  plength: length of data 
+* @retval MOBLE_RESULT
+*/
+MOBLE_RESULT Appli_Generic_Level_Status(MOBLEUINT8 const *plevel_status, MOBLEUINT32 plength)
+{
+  
+  TRACE_M(TF_GENERIC,"Generic_Level_Status callback received \r\n");
+  
+  TRACE_M(TF_SERIAL_CTRL,"#8208! \n\r");
       
   return MOBLE_RESULT_SUCCESS;
 }
@@ -238,16 +274,31 @@ MOBLE_RESULT Appli_Generic_PowerOnOff_Set(Generic_PowerOnOffParam_t* pPowerOnOff
 { 
   AppliPowerOnSet.PowerOnState = pPowerOnOffParam->PowerOnOffState;
   
-  TRACE_M(TF_SERIAL_CTRL,"Generic Power OnOff Set: State %d!\n\r",
-          pPowerOnOffParam->PowerOnOffState);
+  TRACE_M(TF_SERIAL_CTRL,"#8213!\n\r");
 
   /* set the flag value for NVM store */
-  RestoreFlag = GENERIC_ON_OFF_NVM_FLAG;
+  RestoreFlag = No_NVM_FLAG;
 
   AppliNvm_SaveMessageParam();
     
   return MOBLE_RESULT_SUCCESS;
 }
+/**
+* @brief  Appli_Generic_PowerOnOff_Set: This function is callback for Application
+*           when Generic Power on off set message is received
+* @param   powerOnOff_status: Pointer to the parameters message
+* @param  plength: length of data 
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT Appli_Generic_PowerOnOff_Status(MOBLEUINT8 const *powerOnOff_status , MOBLEUINT32 plength) 
+{  
+
+  TRACE_M(TF_GENERIC,"Generic_PowerOnOff_Status callback received \r\n"); 
+  
+  TRACE_M(TF_SERIAL_CTRL,"#8212! \n\r");
+
+  return MOBLE_RESULT_SUCCESS;
+}
 #endif  /* ENABLE_GENERIC_MODEL_SERVER_POWER_ONOFF */
 
 
@@ -267,6 +318,23 @@ MOBLE_RESULT Appli_Generic_DefaultTransitionTime_Set(Generic_DefaultTransitionPa
   
   return MOBLE_RESULT_SUCCESS;
 }
+
+/**
+* @brief  Appli_Generic_DefaultTransitionTime_Status: This function is callback for Application
+*          when Generic Power on off set message is received
+* @param  pTransition_status: Pointer to the parameters message
+* @param  plength: length of data 
+* @retval MOBLE_RESULT
+*/
+MOBLE_RESULT Appli_Generic_DefaultTransitionTime_Status(MOBLEUINT8 const *pTransition_status , MOBLEUINT32 plength) 
+{  
+
+  TRACE_M(TF_GENERIC,"Generic_DefaultTransitionTime_Status callback received \r\n");
+  
+  TRACE_M(TF_SERIAL_CTRL,"#8210! \n\r");
+  
+  return MOBLE_RESULT_SUCCESS;
+}
 #endif   /* ENABLE_GENERIC_MODEL_SERVER_DEFAULT_TRANSITION_TIME */
 
 
@@ -323,9 +391,9 @@ MOBLE_RESULT Appli_Generic_GetLevelStatus(MOBLEUINT8* pLevel_Status)
 * @param  pLevel_status: Pointer to the status message
 * @retval MOBLE_RESULT
 */ 
-MOBLE_RESULT Appli_Generic_GetPowerOnOffStatus(MOBLEUINT8* pLevel_Status) 
+MOBLE_RESULT Appli_Generic_GetPowerOnOffStatus(MOBLEUINT8* pPower_Status) 
 { 
-  *pLevel_Status = AppliPowerOnSet.PowerOnState;
+  *pPower_Status = AppliPowerOnSet.PowerOnState;
   TRACE_M(TF_SERIAL_CTRL,"Generic Get OnOff Status: Status %d!\n\r",
           AppliPowerOnSet.PowerOnState);
   
@@ -333,8 +401,8 @@ MOBLE_RESULT Appli_Generic_GetPowerOnOffStatus(MOBLEUINT8* pLevel_Status)
 }
 
 /**
-* @brief  Appli_Generic_GetDefaultTransitionStatus: This function is callback for Application
-* when Generic Level status message is to be provided
+* @brief  Appli_Generic_GetDefaultTransitionStatus: This function is callback for 
+*           Application when Generic Level status message is to be provided
 * @param  pTransition_Status: Pointer to the status message
 * @retval MOBLE_RESULT
 */ 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_generic.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_generic.h
index 465f16b5f..a68c231f3 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_generic.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_generic.h
@@ -81,22 +81,31 @@ typedef struct
 /* Exported Functions Prototypes ---------------------------------------------*/
 
 MOBLE_RESULT Appli_Generic_OnOff_Set(Generic_OnOffStatus_t*, MOBLEUINT8);
+MOBLE_RESULT Appli_Generic_OnOff_Status(MOBLEUINT8 const *pOnOff_status,
+                                               MOBLEUINT32 plength);
 MOBLE_RESULT Appli_Generic_Level_Set(Generic_LevelStatus_t*, MOBLEUINT8);
 MOBLE_RESULT Appli_Generic_LevelDelta_Set(Generic_LevelStatus_t*, MOBLEUINT8 );
 MOBLE_RESULT Appli_Generic_LevelMove_Set(Generic_LevelStatus_t* pdeltaMoveParam, 
                                               MOBLEUINT8 OptionalValid);
-MOBLE_RESULT Appli_Generic_Level_Status(MOBLEUINT8* level_status, 
-                                                MOBLEUINT32 *plength);
+MOBLE_RESULT Appli_Generic_Level_Status(MOBLEUINT8 const *plevel_status,
+                                               MOBLEUINT32 plength);
 MOBLE_RESULT Appli_Generic_PowerOnOff_Set(Generic_PowerOnOffParam_t* pPowerOnOffParam, 
                                                 MOBLEUINT8 OptionalValid);  
+MOBLE_RESULT Appli_Generic_PowerOnOff_Status(MOBLEUINT8 const *powerOnOff_status , 
+                                               MOBLEUINT32 plength); 
 MOBLE_RESULT Appli_Generic_DefaultTransitionTime_Set(Generic_DefaultTransitionParam_t* pDefaultTimeParam, 
                                                 MOBLEUINT8 OptionalValid);
+MOBLE_RESULT Appli_Generic_DefaultTransitionTime_Status(MOBLEUINT8 const *pTransition_status , 
+                                               MOBLEUINT32 plength); 
 
 MOBLE_RESULT Appli_Generic_GetOnOffStatus(MOBLEUINT8* pOnOff_Status);
 MOBLE_RESULT Appli_Generic_GetOnOffValue(MOBLEUINT8* pOnOff_Value);
 MOBLE_RESULT Appli_Generic_GetLevelStatus(MOBLEUINT8* pLevel_Status);
 MOBLE_RESULT Appli_Generic_GetPowerOnOffStatus(MOBLEUINT8* pLevel_Status);
+void Appli_Generic_Restore_PowerOn_Value(MOBLEUINT8 restoreValue);
 MOBLE_RESULT Appli_Generic_GetDefaultTransitionStatus(MOBLEUINT8* pTransition_Status) ;
+MOBLE_RESULT Appli_Generic_OnOff_Status(MOBLEUINT8 const *pOnOff_status,
+                                               MOBLEUINT32 plength);
  
 
 #endif /* __APPLI_GENERIC_H */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_generic_client.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_generic_client.c
new file mode 100644
index 000000000..0c36b2294
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_generic_client.c
@@ -0,0 +1,101 @@
+/**
+******************************************************************************
+* @file    appli_generic_client.c
+* @author  BLE Mesh Team
+* @brief   Application interface for Generic Mesh Models 
+******************************************************************************
+* @attention
+*
+* 
    © Copyright (c) 2019 STMicroelectronics.
+* All rights reserved.
    
+*
+* This software component is licensed by ST under Ultimate Liberty license
+* SLA0044, the "License"; You may not use this file except in compliance with
+* the License. You may obtain a copy of the License at:
+*                             www.st.com/SLA0044
+*
+******************************************************************************
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "hal_common.h"
+#include "types.h"
+#include "appli_generic.h"
+#include "appli_light.h"
+#include "common.h"
+#include "mesh_cfg_usr.h"
+#include "appli_nvm.h"
+#include "appli_mesh.h"
+#include "generic_client.h"
+#include "appli_generic_client.h"
+
+/** @addtogroup ST_BLE_Mesh
+*  @{
+*/
+
+/** @addtogroup Application_Mesh_Models
+*  @{
+*/
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+MOBLEUINT8 Led_Value;
+/* Private function prototypes -----------------------------------------------*/
+MOBLE_RESULT Appli_GenericClient_OnOff_Set(void);
+/* Private functions ---------------------------------------------------------*/
+
+/**
+* @brief  Appli_Generic_OnOff_Set: This function is callback for Application
+*          when Generic OnOff message is called
+* @param  void
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT Appli_GenericClient_OnOff_Set(void) 
+{ 
+  MOBLE_ADDRESS elementAddr = 0; 
+  MOBLEUINT8 pGeneric_OnOffParam[2];
+   
+  Led_Value ^= APPLI_LED_ON;
+  pGeneric_OnOffParam[0] = Led_Value;
+  GenericClient_OnOff_Set_Unack(elementAddr,
+                          (_Generic_OnOffParam*) pGeneric_OnOffParam, 
+                          sizeof(pGeneric_OnOffParam) ); 
+     
+  return MOBLE_RESULT_SUCCESS;
+}
+
+#ifdef ENABLE_GENERIC_MODEL_CLIENT_LEVEL
+/**
+* @brief  Appli_Generic_Level_Set: This function is callback for Application
+*          when Generic Level message is called
+* @param  void: 
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT Appli_GenericClient_Level_Set_Unack(void) 
+{ 
+  MOBLE_ADDRESS elementAddr = 0; 
+  MOBLEUINT8 pGeneric_LevelParam[3];
+  
+  Appli_IntensityControlPublishing(pGeneric_LevelParam);
+  GenericClient_Level_Set_Unack(elementAddr,
+                          (_Generic_LevelParam*) pGeneric_LevelParam, 
+                          sizeof(pGeneric_LevelParam));
+    
+  return MOBLE_RESULT_SUCCESS;
+}
+
+#endif
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/******************* (C) COPYRIGHT 2017 STMicroelectronics *****END OF FILE****/
+
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_generic_client.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_generic_client.h
new file mode 100644
index 000000000..8726f76e8
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_generic_client.h
@@ -0,0 +1,45 @@
+/**
+******************************************************************************
+* @file    appli_generic_client.h
+* @author  BLE Mesh Team
+* @version V1.12.000
+* @date    06-12-2019
+* @brief   Application interface for Generic Mesh Models  
+******************************************************************************
+* @attention
+*
+  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+*
+******************************************************************************
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APPLI_GENERIC_CLIENT_H
+#define __APPLI_GENERIC_CLIENT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "types.h"
+#include "generic.h"
+#include "mesh_cfg.h"
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported variables  ------------------------------------------------------- */
+/* Application Variable-------------------------------------------------------*/
+/* Exported Functions Prototypes ---------------------------------------------*/
+MOBLE_RESULT Appli_ConfigClient_Set(void); 
+MOBLE_RESULT Appli_GenericClient_OnOff_Set(void);
+MOBLE_RESULT Appli_GenericClient_Level_Set_Unack(void);
+MOBLE_RESULT Appli_GenericClient_OnOff_Set(void);
+
+
+#endif /* __APPLI_GENERIC_CLIENT_H */
+
+/******************* (C) COPYRIGHT 2017 STMicroelectronics *****END OF FILE****/
+
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light.c
index 64998ac3c..24cd49583 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light.c
@@ -33,11 +33,11 @@
 #include "appli_nvm.h"
 #include "math.h"
 
-/** @addtogroup BLE_Mesh
+/** @addtogroup ST_BLE_Mesh
 *  @{
 */
 
-/** @addtogroup models_BLE
+/** @addtogroup Application_Mesh_Models
 *  @{
 */
 
@@ -79,6 +79,7 @@ Following Variables are used for the LIGHTING HSL MODEL
 
 #ifdef ENABLE_LIGHT_MODEL_SERVER_HSL
   Appli_Light_HslSet AppliHslSet;
+  Appli_Light_HslDefaultSet Appli_HslDefaultSet = {0x7FFF,0x7FFF,0x7FFF};
   Appli_Light_RGBSet Appli_RGBParam;
   Appli_Light_HslRangeSet AppliHslRangeSet;
 
@@ -94,7 +95,8 @@ Appli_LightPwmValue_t Appli_LightPwmValue;
 
 extern MOBLEUINT8 RestoreFlag;
 extern MOBLEUINT8 PowerOnOff_flag;
-
+extern MOBLEUINT8 IntensityFlag;
+extern MOBLEUINT16 IntensityValue;
 /* Private function prototypes -----------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
 
@@ -110,13 +112,31 @@ MOBLE_RESULT Appli_Light_Lightness_Set(Light_LightnessStatus_t* pLight_Lightness
                                        MOBLEUINT8 OptionalValid)
 {
   MOBLEUINT16 duty;
-  
+  static MOBLEUINT16 previousIntensity = 0;
+  TRACE_M(TF_SERIAL_CTRL,"#824C!\n\r");
   ApplilightnessSet.PresentState16 = pLight_LightnessParam->PresentValue16;
   
+  if(((IntensityValue > previousIntensity) && (IntensityValue PresentValue16 != 0x00)
   {
     ApplilightnessSet.LastLightness16 = pLight_LightnessParam->PresentValue16;
   }
+  
+  if(pLight_LightnessParam->PresentValue16 != 0x00)
+  {
+    ApplilightnessSet.LastLightness16 = pLight_LightnessParam->PresentValue16;
+  }
+  
   duty = PwmValueMapping(ApplilightnessSet.PresentState16 , 0xfFFF ,0); 
   Appli_LightPwmValue.IntensityValue = duty;
   Light_UpdateLedValue(LOAD_STATE , Appli_LightPwmValue);
@@ -141,6 +161,22 @@ MOBLE_RESULT Appli_Light_Lightness_Set(Light_LightnessStatus_t* pLight_Lightness
   
 }
 
+/**
+* @brief  Appli_Light_Lightness_Status: This function is callback for Application
+*           when Light Lightness status message is received
+* @param  pLightness_status: Pointer to the parameters received for message
+* @param  pLength: length of data 
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT Appli_Light_Lightness_Status(MOBLEUINT8 const *pLightness_status, MOBLEUINT32 pLength)
+{
+  TRACE_M(TF_LIGHT,"Light_Lightness_Status callback received \r\n");
+  
+  TRACE_M(TF_SERIAL_CTRL,"#824E! \n\r");
+  
+  return MOBLE_RESULT_SUCCESS;
+}
+
 /******************************************************************************/
 #endif
 /******************************************************************************/
@@ -158,6 +194,24 @@ MOBLE_RESULT Appli_Light_Lightness_Linear_Set(Light_LightnessStatus_t* pLight_Li
 {
   ApplilightnessLinearSet.PresentState16 = pLight_LightnessLinearParam->PresentValue16;
   
+  TRACE_M(TF_SERIAL_CTRL,"#8250!\n\r");
+  
+  return MOBLE_RESULT_SUCCESS;
+}
+
+/**
+* @brief  Appli_Light_Lightness_Linear_Status: This function is callback for Application
+*         when Light Lightness Linear status message is received
+* @param  pLightnessLinear_status: Pointer to the parameters received for message
+* @param  pLength: length of data
+* @retval MOBLE_RESULT
+*/
+MOBLE_RESULT Appli_Light_Lightness_Linear_Status(MOBLEUINT8 const *pLightnessLinear_status, MOBLEUINT32 pLength)
+{
+  TRACE_M(TF_LIGHT,"Light_Lightness_Linear_Status callback received \r\n");
+  
+  TRACE_M(TF_SERIAL_CTRL,"#8252! \n\r");
+  
   return MOBLE_RESULT_SUCCESS;
 }
 
@@ -168,7 +222,7 @@ MOBLE_RESULT Appli_Light_Lightness_Linear_Set(Light_LightnessStatus_t* pLight_Li
 #ifdef ENABLE_LIGHT_MODEL_SERVER_LIGHTNESS_SETUP
 /**
 * @brief  Appli_Light_Lightness_Default_Set: This function is callback for Application
-* when Light Lightness Linear Set message is received
+*         when Light Lightness Default Set message is received
 * @param  pLight_LightnessDefaultParam: Pointer to the parameters received for message
 * @param  OptionalValid: Flag to inform about the validity of optional parameters 
 * @retval MOBLE_RESULT
@@ -176,7 +230,6 @@ MOBLE_RESULT Appli_Light_Lightness_Linear_Set(Light_LightnessStatus_t* pLight_Li
 MOBLE_RESULT Appli_Light_Lightness_Default_Set(Light_LightnessDefaultParam_t* pLight_LightnessDefaultParam,
                                                MOBLEUINT8 OptionalValid)
 {
-  ApplilightnessSet.LightnessDefault = pLight_LightnessDefaultParam->LightnessDefaultStatus;
   if(pLight_LightnessDefaultParam->LightnessDefaultStatus > 0)
   {
     BSP_LED_On(LED_BLUE);
@@ -185,6 +238,25 @@ MOBLE_RESULT Appli_Light_Lightness_Default_Set(Light_LightnessDefaultParam_t* pL
   {
     BSP_LED_Off(LED_BLUE);
   }
+  ApplilightnessSet.LightnessDefault = pLight_LightnessDefaultParam->LightnessDefaultStatus;
+  
+   TRACE_M(TF_SERIAL_CTRL,"#8259!\n\r");
+   
+  return MOBLE_RESULT_SUCCESS;
+}
+
+/**
+* @brief  Appli_Light_Lightness_Default_Status: This function is callback for Application
+*         when Light Lightness Default status message is received
+* @param  pLightnessDefault_status: Pointer to the parameters received for message
+* @param  pLength: length of data
+* @retval MOBLE_RESULT
+*/
+MOBLE_RESULT Appli_Light_Lightness_Default_Status(MOBLEUINT8 const *pLightnessDefault_status, MOBLEUINT32 pLength)
+{
+  TRACE_M(TF_LIGHT,"Light_Lightness_Default_Status callback received \r\n");
+  
+  TRACE_M(TF_SERIAL_CTRL,"#8256! \n\r");
   
   return MOBLE_RESULT_SUCCESS;
 }
@@ -196,7 +268,7 @@ MOBLE_RESULT Appli_Light_Lightness_Default_Set(Light_LightnessDefaultParam_t* pL
 #ifdef ENABLE_LIGHT_MODEL_SERVER_LIGHTNESS_SETUP
 /**
 * @brief  Appli_Light_Lightness_Range_Set: This function is callback for Application
-* when Light Lightness Linear Set message is received
+*         when Light Lightness Range Set message is received
 * @param  pLight_LightnessRangeParam: Pointer to the parameters received for message
 * @param  OptionalValid: Flag to inform about the validity of optional parameters 
 * @retval MOBLE_RESULT
@@ -208,6 +280,24 @@ MOBLE_RESULT Appli_Light_Lightness_Range_Set(Light_LightnessRangeParam_t* pLight
   ApplilightnessSet.RangeMin = pLight_LightnessRangeParam->MinRangeStatus; 
   ApplilightnessSet.RangeMax = pLight_LightnessRangeParam->MaxRangeStatus;
   
+  TRACE_M(TF_SERIAL_CTRL,"#825B! \n\r");
+  
+  return MOBLE_RESULT_SUCCESS;
+}
+
+/**
+* @brief  Appli_Light_Lightness_Range_Status: This function is callback for Application
+*         when Light Lightness range ststus message is received
+* @param  pLightnessRange_status: Pointer to the parameters received for message
+* @param  pLength: length of data 
+* @retval MOBLE_RESULT
+*/
+MOBLE_RESULT Appli_Light_Lightness_Range_Status(MOBLEUINT8 const *pLightnessRange_status, MOBLEUINT32 pLength)
+{
+  TRACE_M(TF_LIGHT,"Light_Lightness_Range_Status callback received \r\n");
+
+  TRACE_M(TF_SERIAL_CTRL,"#8258! \n\r");
+  
   return MOBLE_RESULT_SUCCESS;
 }
 
@@ -218,7 +308,7 @@ MOBLE_RESULT Appli_Light_Lightness_Range_Set(Light_LightnessRangeParam_t* pLight
 #ifdef ENABLE_LIGHT_MODEL_SERVER_CTL
 /**
 * @brief  Appli_Light_Ctl_Set: This function is callback for Application
-* when Light Lightness Linear Set message is received
+*         when Light Ctl Set message is received
 * @param  pLight_CtlParam: Pointer to the parameters received for message
 * @param  OptionalValid: Flag to inform about the validity of optional parameters 
 * @retval MOBLE_RESULT
@@ -228,6 +318,7 @@ MOBLE_RESULT Appli_Light_Ctl_Set(Light_CtlStatus_t* pLight_CtlParam,
 {
   float colourRatio;
   float brightRatio;
+  TRACE_M(TF_SERIAL_CTRL,"#825E! \n\r");
   
   AppliCtlSet.PresentLightness16 = pLight_CtlParam->PresentCtlLightness16;
   AppliCtlSet.PresentTemperature16 = pLight_CtlParam->PresentCtlTemperature16;
@@ -254,13 +345,30 @@ MOBLE_RESULT Appli_Light_Ctl_Set(Light_CtlStatus_t* pLight_CtlParam,
     
   return MOBLE_RESULT_SUCCESS;
 }
+
+/**
+* @brief  Appli_Light_Ctl_Status: This function is callback for Application
+*         when Light CTL status message is received
+* @param  pLightCtl_status: Pointer to the parameters received for message
+* @param  pLength: length of data
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT Appli_Light_Ctl_Status(MOBLEUINT8 const *pLightCtl_status, MOBLEUINT32 pLength)
+{
+  TRACE_M(TF_LIGHT,"Light_Ctl_Status callback received \r\n");
+  
+  TRACE_M(TF_SERIAL_CTRL,"#8260! \n\r");
+  
+  return MOBLE_RESULT_SUCCESS;
+}
+
 #endif
 
 
 #ifdef ENABLE_LIGHT_MODEL_SERVER_CTL_TEMPERATURE 
 /**
 * @brief  Appli_Light_CtlTemperature_Set: This function is callback for Application
-* when Light Lightness Linear Set message is received
+*         when Light Ctl Temperature Set message is received
 * @param  pLight_CtltempParam: Pointer to the parameters received for message
 * @param  OptionalValid: Flag to inform about the validity of optional parameters 
 * @retval MOBLE_RESULT
@@ -270,6 +378,7 @@ MOBLE_RESULT Appli_Light_CtlTemperature_Set(Light_CtlStatus_t* pLight_CtltempPar
 {
   float colourRatio;
   float brightRatio;
+  TRACE_M(TF_SERIAL_CTRL,"#8264!\n\r");
   AppliCtlSet.PresentTemperature16 = pLight_CtltempParam->PresentCtlTemperature16;
   AppliCtlSet.PresentCtlDelta16 = pLight_CtltempParam->PresentCtlDelta16;
   
@@ -291,6 +400,23 @@ MOBLE_RESULT Appli_Light_CtlTemperature_Set(Light_CtlStatus_t* pLight_CtltempPar
   return MOBLE_RESULT_SUCCESS;
 }
 
+/**                                                  
+* @brief  Appli_Light_CtlTemperature_Status: This function is callback for Application
+*         when Light CTL temperature status message is received
+* @param  pLightCtlTemp_status: Pointer to the parameters received for message
+* @param  pLength: length of data
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT Appli_Light_CtlTemperature_Status(MOBLEUINT8 const *pLightCtlTemp_status, MOBLEUINT32 pLength)
+{
+  TRACE_M(TF_LIGHT,"Light_CtlTemperature_Status callback received \r\n");
+  
+  TRACE_M(TF_SERIAL_CTRL,"#8266! \n\r");
+  
+  return MOBLE_RESULT_SUCCESS;
+}
+
+
 /******************************************************************************/
 #endif
 /******************************************************************************/
@@ -298,7 +424,7 @@ MOBLE_RESULT Appli_Light_CtlTemperature_Set(Light_CtlStatus_t* pLight_CtltempPar
 #ifdef ENABLE_LIGHT_MODEL_SERVER_CTL_SETUP
 /**
 * @brief  Appli_Light_CtlTemperature_Range_Set: This function is callback for Application
-* when Light Lightness Linear Set message is received
+*         when Light Ctl Temperature range Set message is received
 * @param  pLight_CtlTempRangeParam: Pointer to the parameters received for message
 * @param  OptionalValid: Flag to inform about the validity of optional parameters 
 * @retval MOBLE_RESULT
@@ -310,6 +436,23 @@ MOBLE_RESULT Appli_Light_CtlTemperature_Range_Set(Light_CtlTemperatureRangeParam
   AppliCtlTemperatureRangeSet.RangeMax = pLight_CtlTempRangeParam->MaxRangeStatus;
   AppliCtlTemperatureRangeSet.StatusCode = pLight_CtlTempRangeParam->StatusCode;
 
+  TRACE_M(TF_SERIAL_CTRL,"#826B!\n\r");
+  
+  return MOBLE_RESULT_SUCCESS;
+}
+/**                                                  
+* @brief  Appli_Light_CtlTemperature_Range_Set: This function is callback for Application
+*         when Light CTL temperature range status message is received
+* @param  pCtlTempRange_status: Pointer to the parameters received for message
+* @param  pLength: length of data
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT Appli_Light_CtlTemperature_Range_Status(MOBLEUINT8 const *pCtlTempRange_status, MOBLEUINT32 pLength)
+{
+  TRACE_M(TF_LIGHT,"Light_CtlTemperature_Range_Status callback received \r\n");
+  
+  TRACE_M(TF_SERIAL_CTRL,"#8263! \n\r");
+  
   return MOBLE_RESULT_SUCCESS;
 }
 
@@ -320,7 +463,7 @@ MOBLE_RESULT Appli_Light_CtlTemperature_Range_Set(Light_CtlTemperatureRangeParam
 #ifdef ENABLE_LIGHT_MODEL_SERVER_CTL_SETUP
 /**
 * @brief  Appli_Light_CtlDefault_Set: This function is callback for Application
-*         when Light Lightness Linear Set message is received
+*         when Light Ctl Default Set message is received
 * @param  pLight_CtlDefaultParam: Pointer to the parameters received for message
 * @param  OptionalValid: Flag to inform about the validity of optional parameters 
 * @retval MOBLE_RESULT
@@ -332,8 +475,27 @@ MOBLE_RESULT Appli_Light_CtlDefault_Set(Light_CtlDefaultParam_t* pLight_CtlDefau
   AppliCtlDefaultSet.CtlDefaultTemperature16 = pLight_CtlDefaultParam->CtlDefaultTemperature16;
   AppliCtlDefaultSet.CtlDefaultDeltaUv = pLight_CtlDefaultParam->CtlDefaultDeltaUv;
   
+  TRACE_M(TF_SERIAL_CTRL,"#8269!\n\r");
+  
   return MOBLE_RESULT_SUCCESS;
 } 
+
+/**                                                  
+* @brief  Appli_Light_CtlDefault_Status: This function is callback for Application
+*         when Light CTL Default status message is received
+* @param  pCtlDefault_status: Pointer to the parameters received for message
+* @param  pLength: length of data
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT Appli_Light_CtlDefault_Status(MOBLEUINT8 const *pCtlDefault_status, MOBLEUINT32 pLength)
+{
+  TRACE_M(TF_LIGHT,"Light_Ctl_DefaultStatus callback received \r\n");
+  
+  TRACE_M(TF_SERIAL_CTRL,"#8268! \n\r");
+  
+  return MOBLE_RESULT_SUCCESS;
+} 
+
 #endif
 
 
@@ -348,7 +510,7 @@ MOBLE_RESULT Appli_Light_CtlDefault_Set(Light_CtlDefaultParam_t* pLight_CtlDefau
 MOBLE_RESULT Appli_Light_Hsl_Set(Light_HslStatus_t* pLight_HslParam,
                                              MOBLEUINT8 OptionalValid)
 { 
-  
+  TRACE_M(TF_SERIAL_CTRL,"#8276!\n\r");
   AppliHslSet.HslLightness16 = pLight_HslParam->PresentHslLightness16;
   AppliHslSet.HslHueLightness16 = pLight_HslParam->PresentHslHueLightness16;
   AppliHslSet.HslSaturation16 = pLight_HslParam->PresentHslSaturation16;
@@ -371,6 +533,23 @@ MOBLE_RESULT Appli_Light_Hsl_Set(Light_HslStatus_t* pLight_HslParam,
     
   return MOBLE_RESULT_SUCCESS;
 } 
+
+/**                                                  
+* @brief  Appli_Light_Hsl_Status: This function is callback for Application
+*         when Light HSL status message is received
+* @param  pHsl_status: Pointer to the parameters received for message
+* @param  pLength: length of data
+* @retval MOBLE_RESULT
+*/
+MOBLE_RESULT Appli_Light_Hsl_Status(MOBLEUINT8 const *pHsl_status, MOBLEUINT32 pLength)
+{
+  TRACE_M(TF_LIGHT,"Light_Hsl_Status callback received \r\n");
+  
+  TRACE_M(TF_SERIAL_CTRL,"#8278! \n\r");
+  
+  return MOBLE_RESULT_SUCCESS;
+}
+
 #endif
 
 
@@ -385,6 +564,7 @@ MOBLE_RESULT Appli_Light_Hsl_Set(Light_HslStatus_t* pLight_HslParam,
 MOBLE_RESULT Appli_Light_HslHue_Set(Light_HslStatus_t* pLight_HslHueParam,
                                              MOBLEUINT8 OptionalValid)
 {
+  TRACE_M(TF_SERIAL_CTRL,"#826F! \n\r");	
   AppliHslSet.HslHueLightness16 = pLight_HslHueParam->PresentHslHueLightness16; 
   
   HSL2RGB_Conversion();
@@ -401,8 +581,26 @@ MOBLE_RESULT Appli_Light_HslHue_Set(Light_HslStatus_t* pLight_HslHueParam,
 
   AppliNvm_SaveMessageParam();
     
+  return MOBLE_RESULT_SUCCESS;
+   
+}
+
+/**                                                  
+* @brief  Appli_Light_HslHue_Status: This function is callback for Application
+*         when Light HSL HUE status message is received
+* @param  pHslHue_status: Pointer to the parameters received for message
+* @param  pLength: length of data
+* @retval MOBLE_RESULT
+*/
+MOBLE_RESULT Appli_Light_HslHue_Status(MOBLEUINT8 const *pHslHue_status, MOBLEUINT32 pLength)
+{
+  TRACE_M(TF_LIGHT,"Light_HslHue_Status callback received \r\n");
+  
+  TRACE_M(TF_SERIAL_CTRL,"#8271! \n\r");
+    
   return MOBLE_RESULT_SUCCESS;
 } 
+
 #endif
 
 
@@ -417,6 +615,7 @@ MOBLE_RESULT Appli_Light_HslHue_Set(Light_HslStatus_t* pLight_HslHueParam,
 MOBLE_RESULT Appli_Light_HslSaturation_Set(Light_HslStatus_t* pLight_HslSaturationParam,
                                              MOBLEUINT8 OptionalValid)
 {
+  TRACE_M(TF_SERIAL_CTRL,"#8273! \n\r");	
   AppliHslSet.HslSaturation16 = pLight_HslSaturationParam->PresentHslSaturation16;
   
   HSL2RGB_Conversion();
@@ -435,6 +634,24 @@ MOBLE_RESULT Appli_Light_HslSaturation_Set(Light_HslStatus_t* pLight_HslSaturati
     
   return MOBLE_RESULT_SUCCESS;
 } 
+
+/**                                                  
+* @brief  Appli_Light_HslSaturation_Status: This function is callback for Application
+*         when Light HSL Saturation status message is received
+* @param  pHslSaturation_status: Pointer to the parameters received for message
+* @param  pLength: length of data
+* @retval MOBLE_RESULT
+*/
+MOBLE_RESULT Appli_Light_HslSaturation_Status(MOBLEUINT8 const *pHslSaturation_status, MOBLEUINT32 pLength)
+{
+  TRACE_M(TF_LIGHT,"Light_HslSaturation_Status callback received \r\n");
+  
+  TRACE_M(TF_SERIAL_CTRL,"#8275! \n\r");
+    
+  return MOBLE_RESULT_SUCCESS;
+}
+
+
 #endif
               
 
@@ -449,9 +666,14 @@ MOBLE_RESULT Appli_Light_HslSaturation_Set(Light_HslStatus_t* pLight_HslSaturati
 MOBLE_RESULT Appli_Light_HslDefault_Set(Light_HslStatus_t* pLight_HslDefaultParam,
                                              MOBLEUINT8 OptionalValid)
 {
-  AppliHslSet.HslLightness16 = pLight_HslDefaultParam->PresentHslLightness16;
-  AppliHslSet.HslHueLightness16 = pLight_HslDefaultParam->PresentHslHueLightness16;
-  AppliHslSet.HslSaturation16 = pLight_HslDefaultParam->PresentHslSaturation16;
+  TRACE_M(TF_SERIAL_CTRL,"#827F! \n\r");	
+  Appli_HslDefaultSet.HslDefaultLightness16 = pLight_HslDefaultParam->PresentHslLightness16;
+  Appli_HslDefaultSet.HslDefaultHueLightness16 = pLight_HslDefaultParam->PresentHslHueLightness16;
+  Appli_HslDefaultSet.HslDefaultSaturation16 = pLight_HslDefaultParam->PresentHslSaturation16;  
+  
+  AppliHslSet.HslLightness16 = Appli_HslDefaultSet.HslDefaultLightness16;
+  AppliHslSet.HslHueLightness16 = Appli_HslDefaultSet.HslDefaultHueLightness16;
+  AppliHslSet.HslSaturation16 = Appli_HslDefaultSet.HslDefaultSaturation16;
   
   HSL2RGB_Conversion();
   
@@ -469,6 +691,23 @@ MOBLE_RESULT Appli_Light_HslDefault_Set(Light_HslStatus_t* pLight_HslDefaultPara
     
   return MOBLE_RESULT_SUCCESS;
 } 
+
+/**                                                  
+* @brief  Appli_Light_HslDefault_Status: This function is callback for Application
+*          when Light HSL Default status  message is received
+* @param  pHslDefault_status: Pointer to the parameters received for message
+* @param  pLength: length of data
+* @retval MOBLE_RESULT
+*/
+MOBLE_RESULT Appli_Light_HslDefault_Status(MOBLEUINT8 const *pHslDefault_status, MOBLEUINT32 pLength)
+{
+  TRACE_M(TF_LIGHT,"Light_HslDefault_Status callback received \r\n");
+  
+    TRACE_M(TF_SERIAL_CTRL,"#827C! \n\r");
+    
+  return MOBLE_RESULT_SUCCESS;
+}
+
 #endif 
               
 
@@ -483,6 +722,7 @@ MOBLE_RESULT Appli_Light_HslDefault_Set(Light_HslStatus_t* pLight_HslDefaultPara
 MOBLE_RESULT Appli_Light_HslRange_Set(Light_HslRangeParam_t* pLight_HslRangeParam,
                                              MOBLEUINT8 OptionalValid)
 {
+  TRACE_M(TF_SERIAL_CTRL,"#8281! \n\r"); 	
    AppliHslRangeSet.HslHueMinRange16 = pLight_HslRangeParam->HslHueMinRange16;
    AppliHslRangeSet.HslHueMaxRange16 = pLight_HslRangeParam->HslHueMaxRange16;
    AppliHslRangeSet.HslMinSaturation16 = pLight_HslRangeParam->HslMinSaturation16;
@@ -490,6 +730,24 @@ MOBLE_RESULT Appli_Light_HslRange_Set(Light_HslRangeParam_t* pLight_HslRangePara
    
    return MOBLE_RESULT_SUCCESS;
 } 
+
+/**                                                  
+* @brief  Appli_Light_HslRange_Status: This function is callback for Application
+*         when Light HSL range status message is received
+* @param  pHslRange_status: Pointer to the parameters received for message
+* @param  pLength: length of data
+* @retval MOBLE_RESULT
+*/
+MOBLE_RESULT Appli_Light_HslRange_Status(MOBLEUINT8 const *pHslRange_status, MOBLEUINT32 pLength)
+{
+  TRACE_M(TF_LIGHT,"Light_HslRange_Status callback received \r\n");
+  
+ TRACE_M(TF_SERIAL_CTRL,"#827E! \n\r");
+    
+  return MOBLE_RESULT_SUCCESS;
+}
+
+
 #endif            
 
 
@@ -509,10 +767,8 @@ MOBLE_RESULT Appli_Light_GetLightnessStatus(MOBLEUINT8* lLightnessState)
 {
   *(lLightnessState) = ApplilightnessSet.PresentState16;
   *(lLightnessState+1) = ApplilightnessSet.PresentState16 >> 8;
-//  *(lLightnessState+2) = ApplilightnessSet.LastLightness16 ;
-//  *(lLightnessState+3) = ApplilightnessSet.LastLightness16 >> 8;
-  TRACE_M(TF_SERIAL_CTRL,"Get Lighness Status: %d\n\r",
-          ApplilightnessSet.PresentState16);
+  *(lLightnessState+2) = ApplilightnessSet.LastLightness16 ;
+  *(lLightnessState+3) = ApplilightnessSet.LastLightness16 >> 8;
     
   return MOBLE_RESULT_SUCCESS;
 }
@@ -557,7 +813,7 @@ MOBLE_RESULT Appli_Light_GetLightnessDefaultStatus(MOBLEUINT8* lDefaultState)
 
 /**
 * @brief  Appli_Light_GetLightnessRangeStatus: This function is callback for Application
-to get the application values in middleware used for transition change.
+*         to get the application values in middleware used for transition change.
 * @param  lRangeState: Pointer to the status message
 * @retval MOBLE_RESULT
 */ 
@@ -719,7 +975,7 @@ MOBLE_RESULT Appli_Light_GetHslHueStatus(MOBLEUINT8* lHslHueState)
 
 /**
 * @brief  Appli_Light_GetHslSaturationStatus: This function is callback for Application
-* to get the application values in middleware used for transition change.
+*         to get the application values in middleware used for transition change
 * @param  lHslSaturationState: Pointer to the status message
 * @retval MOBLE_RESULT
 */ 
@@ -733,9 +989,27 @@ MOBLE_RESULT Appli_Light_GetHslSaturationStatus(MOBLEUINT8* lHslSaturationState)
     return MOBLE_RESULT_SUCCESS;
 }  
 
+/**
+* @brief  Appli_Light_GetHslDefaultStatus: This function is callback for Application
+*         to get the application values in middleware used for transition change.
+* @param  lHslDefaultState: Pointer to the status message
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT Appli_Light_GetHslDefaultStatus(MOBLEUINT8* lHslDefaultState)
+{
+  *(lHslDefaultState) = Appli_HslDefaultSet.HslDefaultLightness16;
+  *(lHslDefaultState+1) = Appli_HslDefaultSet.HslDefaultLightness16 >> 8;
+  *(lHslDefaultState+2) = Appli_HslDefaultSet.HslDefaultHueLightness16;
+  *(lHslDefaultState+3) = Appli_HslDefaultSet.HslDefaultHueLightness16 >>8;
+  *(lHslDefaultState+4) = Appli_HslDefaultSet.HslDefaultSaturation16;
+  *(lHslDefaultState+5) = Appli_HslDefaultSet.HslDefaultSaturation16 >>8;
+  
+  return MOBLE_RESULT_SUCCESS;
+}  
+
 /**
 * @brief  Appli_Light_GetHslSatRange: This function is callback for Application
-          to get the application values in middleware used for transition change
+*         to get the application values in middleware used for transition change
 * @param  lHslSatRange: Pointer to the status message
 * @retval MOBLE_RESULT
 */ 
@@ -782,7 +1056,12 @@ MOBLE_RESULT Appli_Light_GetHslHueRange(MOBLEUINT8* lHslHueRange)
 /* This Function used to initialise the PWM . This is used for the RGB board */
 void Appli_Light_PwmInit()
 {
-   
+   Appli_LightPwmValue.IntensityValue = PWM_VALUE_OFF;
+   Appli_LightPwmValue.PwmCoolValue = 0;
+   Appli_LightPwmValue.PwmWarmValue = 0;
+   Appli_LightPwmValue.PwmRedValue = PWM_VALUE_OFF;
+   Appli_LightPwmValue.PwmGreenValue = PWM_VALUE_OFF;
+   Appli_LightPwmValue.PwmBlueValue = PWM_VALUE_OFF;
    Light_UpdateLedValue(RESET_STATE , Appli_LightPwmValue);
 }
 
@@ -879,7 +1158,7 @@ void HSL2RGB_Conversion(void)
 
 /**
 * @brief  Rgb_LedOffState: This function is called while using CTL, makes all the RGB 
-  PWM off state for Application.        
+*         PWM off state for Application.        
 * @param  void: 
 * @retval void
 */ 
@@ -893,7 +1172,7 @@ void Rgb_LedOffState(void)
 
 /**
 * @brief  Ctl_LedOffState: This function is called while using HSL, makes all the  
-  cool Warm PWM off state for Application.        
+*         cool Warm PWM off state for Application.        
 * @param  void: 
 * @retval void
 */ 
@@ -920,7 +1199,9 @@ void Light_UpdateLedValue(MOBLEUINT8 state ,Appli_LightPwmValue_t light_state)
       light_state.PwmWarmValue = light_state.IntensityValue;
 #endif
 #ifdef  USER_BOARD_RGB_LED
-    if((light_state.PwmRedValue == 0) && (light_state.PwmGreenValue == 0) && (light_state.PwmBlueValue == 0))
+    if((light_state.PwmRedValue == PWM_VALUE_OFF) && 
+       (light_state.PwmGreenValue == PWM_VALUE_OFF) && 
+         (light_state.PwmBlueValue == PWM_VALUE_OFF))
       light_state.PwmBlueValue = light_state.IntensityValue;
 #endif
   }
@@ -933,11 +1214,13 @@ void Light_UpdateLedValue(MOBLEUINT8 state ,Appli_LightPwmValue_t light_state)
 #endif
 
 #ifdef  USER_BOARD_COOL_WHITE_LED
+
     Modify_PWM(COOL_LED, light_state.PwmCoolValue); 
     Modify_PWM(WARM_LED, light_state.PwmWarmValue); 
 #endif
 
 #ifdef USER_BOARD_RGB_LED
+
     Modify_PWM(RED_LED, light_state.PwmRedValue); 
     Modify_PWM(GREEN_LED, light_state.PwmGreenValue); 
     Modify_PWM(BLUE_LED, light_state.PwmBlueValue);  
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light.h
index 808e03ff3..f99a48f74 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light.h
@@ -80,6 +80,14 @@ typedef struct
   MOBLEUINT16 HslSaturation16; 
 }Appli_Light_HslSet;
 
+/* Light Hsl Hue set */
+typedef struct
+{
+  MOBLEUINT16 HslDefaultLightness16;
+  MOBLEUINT16 HslDefaultHueLightness16;
+  MOBLEUINT16 HslDefaultSaturation16; 
+}Appli_Light_HslDefaultSet;
+
 typedef struct
 {
   MOBLEUINT16 Red_Value;
@@ -111,30 +119,56 @@ typedef struct
 
 MOBLE_RESULT Appli_Light_Lightness_Set(Light_LightnessStatus_t*, MOBLEUINT8 OptionalValid);
 
+MOBLE_RESULT Appli_Light_Lightness_Status(MOBLEUINT8 const *pLightness_status, MOBLEUINT32 pLength);
+
 MOBLE_RESULT Appli_Light_Lightness_Linear_Set(Light_LightnessStatus_t* pLight_LightnessLinearParam,
                                      MOBLEUINT8 OptionalValid);
+MOBLE_RESULT Appli_Light_Lightness_Linear_Status(MOBLEUINT8 const *pLightnessLinear_status, MOBLEUINT32 pLength);
+
 MOBLE_RESULT Appli_Light_Lightness_Default_Set(Light_LightnessDefaultParam_t* pLight_LightnessDefaultParam,
                                      MOBLEUINT8 OptionalValid);
+MOBLE_RESULT Appli_Light_Lightness_Default_Status(MOBLEUINT8 const *pLightnessDefault_status, MOBLEUINT32 pLength);
+
 MOBLE_RESULT Appli_Light_Lightness_Range_Set(Light_LightnessRangeParam_t* pLight_LightnessRangeParam,
                                      MOBLEUINT8 OptionalValid);
+MOBLE_RESULT Appli_Light_Lightness_Range_Status(MOBLEUINT8 const *pLightnessRange_status, MOBLEUINT32 pLength);
+
 MOBLE_RESULT Appli_Light_Ctl_Set(Light_CtlStatus_t* pLight_CtlParam,
                                      MOBLEUINT8 OptionalValid);
+MOBLE_RESULT Appli_Light_Ctl_Status(MOBLEUINT8 const *pLightCtl_status, MOBLEUINT32 pLength);
+
 MOBLE_RESULT Appli_Light_CtlTemperature_Set(Light_CtlStatus_t* pLight_CtltempParam,
                                      MOBLEUINT8 OptionalValid);
+MOBLE_RESULT Appli_Light_CtlTemperature_Status(MOBLEUINT8 const *pLightCtlTemp_status, MOBLEUINT32 pLength);
+
 MOBLE_RESULT Appli_Light_CtlTemperature_Range_Set(Light_CtlTemperatureRangeParam_t* pLight_CtlTempRangeParam,
                                      MOBLEUINT8 OptionalValid);
+MOBLE_RESULT Appli_Light_CtlTemperature_Range_Status(MOBLEUINT8 const *pCtlTempRange_status, MOBLEUINT32 pLength);
+
 MOBLE_RESULT Appli_Light_CtlDefault_Set(Light_CtlDefaultParam_t* pLight_CtlDefaultParam,
                                      MOBLEUINT8 OptionalValid);
+MOBLE_RESULT Appli_Light_CtlDefault_Status(MOBLEUINT8 const *pCtlDefault_status, MOBLEUINT32 pLength);
+
 MOBLE_RESULT Appli_Light_Hsl_Set(Light_HslStatus_t* pLight_HslParam,
                                      MOBLEUINT8 OptionalValid);
+MOBLE_RESULT Appli_Light_Hsl_Status(MOBLEUINT8 const *pHsl_status, MOBLEUINT32 pLength);
+
 MOBLE_RESULT Appli_Light_HslHue_Set(Light_HslStatus_t* pLight_HslHueParam,
                                      MOBLEUINT8 OptionalValid);
+MOBLE_RESULT Appli_Light_HslHue_Status(MOBLEUINT8 const *pHslHue_status, MOBLEUINT32 pLength);
+
 MOBLE_RESULT Appli_Light_HslSaturation_Set(Light_HslStatus_t* pLight_HslSaturationParam,
                                      MOBLEUINT8 OptionalValid);
+MOBLE_RESULT Appli_Light_HslSaturation_Status(MOBLEUINT8 const *pHslSaturation_status, MOBLEUINT32 pLength);
+
 MOBLE_RESULT Appli_Light_HslDefault_Set(Light_HslStatus_t* pLight_HslDefaultParam,
                                      MOBLEUINT8 OptionalValid);
+MOBLE_RESULT Appli_Light_HslDefault_Status(MOBLEUINT8 const *pHslDefault_status, MOBLEUINT32 pLength);
+
 MOBLE_RESULT Appli_Light_HslRange_Set(Light_HslRangeParam_t* pLight_HslDefaultParam,
                                      MOBLEUINT8 OptionalValid);
+MOBLE_RESULT Appli_Light_HslRange_Status(MOBLEUINT8 const *pHslRange_status, MOBLEUINT32 pLength);
+
 MOBLE_RESULT Appli_Light_GetLightnessStatus(MOBLEUINT8* lLightnessState);
 MOBLE_RESULT Appli_Light_GetLightnessLinearStatus(MOBLEUINT8* lLightnessState);
 MOBLE_RESULT Appli_Light_GetLightnessDefaultStatus(MOBLEUINT8* lDefaultState);
@@ -148,14 +182,13 @@ MOBLE_RESULT Appli_Light_GetHslHueStatus(MOBLEUINT8* lHslHueState);
 MOBLE_RESULT Appli_Light_GetHslSaturationStatus(MOBLEUINT8* lHslSaturationState);
 MOBLE_RESULT Appli_Light_GetHslHueRange(MOBLEUINT8* lHslHueRange);
 MOBLE_RESULT Appli_Light_GetHslSatRange(MOBLEUINT8* lHslSatRange);
+MOBLE_RESULT Appli_Light_GetHslDefaultStatus(MOBLEUINT8* lHslDefaultState);
 void Appli_Light_PwmInit(void);
 void HSL2RGB_Conversion(void);
 void Ctl_LedOffState(void);
 void Rgb_LedOffState(void);
 void RgbF_Create(MOBLEUINT16 value1, MOBLEUINT16 value2, MOBLEUINT16 value3);
 void Light_UpdateLedValue(MOBLEUINT8 state , Appli_LightPwmValue_t light_state);
-
-
 #endif /* __APPLI_LIGHT_H */
 
 /******************* (C) COPYRIGHT 2019 STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light_client.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light_client.c
new file mode 100644
index 000000000..96626b19a
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light_client.c
@@ -0,0 +1,102 @@
+/**
+******************************************************************************
+* @file    appli_light_client.c
+* @author  BLE Mesh Team
+* @version V1.12.000
+* @date    06-12-2019
+* @brief   Application interface for Generic Mesh Models 
+******************************************************************************
+* @attention
+*
+* 
    © COPYRIGHT(c) 2017 STMicroelectronics
    
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*   1. Redistributions of source code must retain the above copyright notice,
+*      this list of conditions and the following disclaimer.
+*   2. Redistributions in binary form must reproduce the above copyright notice,
+*      this list of conditions and the following disclaimer in the documentation
+*      and/or other materials provided with the distribution.
+*   3. Neither the name of STMicroelectronics nor the names of its contributors
+*      may be used to endorse or promote products derived from this software
+*      without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* Initial BLE-Mesh is built over Motorolas Mesh over Bluetooth Low Energy 
+* (MoBLE) technology. The present solution is developed and maintained for both 
+* Mesh library and Applications solely by STMicroelectronics.
+*
+******************************************************************************
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "hal_common.h"
+#include "types.h"
+#include "appli_generic.h"
+#include "appli_light.h"
+#include "common.h"
+#include "mesh_cfg_usr.h"
+#include "appli_nvm.h"
+#include "appli_mesh.h"
+#include "generic_client.h"
+#include "appli_light_client.h"
+#include "light_client.h"
+
+
+/** @addtogroup ST_BLE_Mesh
+*  @{
+*/
+
+/** @addtogroup Application_Mesh_Models
+*  @{
+*/
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+extern MOBLEUINT8 Tid_Client;
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+* @brief  Appli_Light_Lightness_Set: This function is callback for Application
+*          when Lightness message is called
+* @param  void
+* @retval MOBLE_RESULT
+*/ 
+MOBLE_RESULT Appli_LightClient_Lightness_Set(void) 
+{ 
+  MOBLE_ADDRESS elementAddr = 0; 
+  MOBLEUINT8 pLightnessParam[3];
+  
+  Appli_IntensityControlPublishing(pLightnessParam);
+  LightClient_Lightness_Set_Unack(elementAddr,
+                          (_Light_LightnessParam*) pLightnessParam, 
+                          sizeof(pLightnessParam) ); 
+     
+  return MOBLE_RESULT_SUCCESS;
+} 
+
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/******************* (C) COPYRIGHT 2017 STMicroelectronics *****END OF FILE****/
+
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light_client.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light_client.h
new file mode 100644
index 000000000..f216e5175
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light_client.h
@@ -0,0 +1,62 @@
+/**
+******************************************************************************
+* @file    appli_light_client.h
+* @author  BLE Mesh Team
+* @version V1.12.000
+* @date    06-12-2019
+* @brief   Application interface for Generic Mesh Models  
+******************************************************************************
+* @attention
+*
+* 
    © COPYRIGHT(c) 2017 STMicroelectronics
    
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*   1. Redistributions of source code must retain the above copyright notice,
+*      this list of conditions and the following disclaimer.
+*   2. Redistributions in binary form must reproduce the above copyright notice,
+*      this list of conditions and the following disclaimer in the documentation
+*      and/or other materials provided with the distribution.
+*   3. Neither the name of STMicroelectronics nor the names of its contributors
+*      may be used to endorse or promote products derived from this software
+*      without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* Initial BLE-Mesh is built over Motorolas Mesh over Bluetooth Low Energy 
+* (MoBLE) technology. The present solution is developed and maintained for both 
+* Mesh library and Applications solely by STMicroelectronics.
+*
+******************************************************************************
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APPLI_LIGHT_CLIENT_H
+#define __APPLI_LIGHT_CLIENT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "types.h"
+#include "generic.h"
+#include "mesh_cfg.h"
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported variables  ------------------------------------------------------- */
+/* Application Variable-------------------------------------------------------*/
+/* Exported Functions Prototypes ---------------------------------------------*/
+MOBLE_RESULT Appli_LightClient_Lightness_Set(void);
+ 
+
+#endif /* __APPLI_LIGHT_CLIENT_H */
+
+/******************* (C) COPYRIGHT 2017 STMicroelectronics *****END OF FILE****/
+
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light_lc.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light_lc.c
index b541c256a..6cfe8bc27 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light_lc.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light_lc.c
@@ -26,11 +26,11 @@
 #include "mesh_cfg_usr.h"
 #include "appli_light_lc.h"
 
-/** @addtogroup BlueNRG_Mesh
+/** @addtogroup ST_BLE_Mesh
 *  @{
 */
 
-/** @addtogroup models_BlueNRG2
+/** @addtogroup Application_Mesh_Models
 *  @{
 */
 
@@ -48,7 +48,7 @@ MOBLEUINT16 AmbientLuxLevel;
 
 /**
 * @brief  Appli_Light_LCMode_Set: This function is callback for Application
-when Light LC mode Set message is received
+*         when Light LC mode Set message is received
 * @param  pLight_LC_Param: Pointer to the parameters received for message
 * @param  OptionalValid: Flag to inform about the validity of optional parameters 
 * @retval MOBLE_RESULT
@@ -62,7 +62,7 @@ MOBLE_RESULT Appli_LightLC_Mode_Set(Light_LC_Param_t* pLight_LC_Param,
   
 /**
 * @brief  Appli_LightLC_OM_Set: This function is callback for Application
-when Light LC mode Occupancy Model Set message is received
+*         when Light LC mode Occupancy Model Set message is received
 * @param  pLight_LC_Param: Pointer to the parameters received for message
 * @param  OptionalValid: Flag to inform about the validity of optional parameters 
 * @retval MOBLE_RESULT
@@ -76,15 +76,15 @@ MOBLE_RESULT Appli_LightLC_OM_Set(Light_LC_Param_t* pLight_LC_Param,
 
 /**
 * @brief  Appli_LightLC_OnOff_Set: This function is callback for Application
-when Light LC On Off Set message is received
+*         when Light LC On Off Set message is received
 * @param  pLight_LC_Param: Pointer to the parameters received for message
 * @param  OptionalValid: Flag to inform about the validity of optional parameters 
 * @retval MOBLE_RESULT
 */ 
-MOBLE_RESULT Appli_LightLC_OnOff_Set(Light_LC_OnOffState_t* pLight_LC_Param,
+MOBLE_RESULT Appli_LightLC_OnOff_Set(Light_LC_Param_t* pLight_LC_Param,
                                                      MOBLEUINT8 OptionalValid)
 {
-  Appli_LightLC_set.Light_OnOffState = pLight_LC_Param->Present_OnOff_State;
+  Appli_LightLC_set.Light_OnOffState = pLight_LC_Param->Light_OnOff;
   return MOBLE_RESULT_SUCCESS;
 }  
 
@@ -105,8 +105,9 @@ MOBLEUINT16 Appli_LightLC_Get_AmbientLuxLevelOutput(void)
 
 /**
 * @brief Light_LC_LuxLevelPIRegulator: This function will calculate all the parameter
-         Kid,kpu,kiu,kpd and return the value Light Lightness Linear.           
-* @param void:
+*        Kid,kpu,kiu,kpd and return the value Light Lightness Linear.           
+* @param tableLuxLevel:
+* @param ambientLuxLevel:
 * @retval MOBLEUINT16:    
 **/
 MOBLEUINT16 Appli_Light_LC_PIRegulatorOutput(MOBLEUINT16 tableLuxLevel,MOBLEUINT16 ambientLuxLevel)
@@ -120,8 +121,8 @@ MOBLEUINT16 Appli_Light_LC_PIRegulatorOutput(MOBLEUINT16 tableLuxLevel,MOBLEUINT
 
 /**
 * @brief  Appli_LightLC_Get_ModeStatus: This function is callback for Application
-to get the application values in middleware used for transition change.
-* @param  lcModeState: Pointer to the status message
+*         to get the application values in middleware used for transition change.
+* @param  plcModeState: Pointer to the status message
 * @retval MOBLE_RESULT
 */ 
 MOBLE_RESULT Appli_LightLC_Get_ModeStatus(MOBLEUINT8* plcModeState)
@@ -135,8 +136,8 @@ MOBLE_RESULT Appli_LightLC_Get_ModeStatus(MOBLEUINT8* plcModeState)
 
 /**
 * @brief  Appli_LightLC_Get_OMModeStatus: This function is callback for Application
-to get the application values in middleware used for transition change.
-* @param  lcOM_ModeState: Pointer to the status message
+*         to get the application values in middleware used for transition change.
+* @param  plcOM_ModeState: Pointer to the status message
 * @retval MOBLE_RESULT
 */ 
 MOBLE_RESULT Appli_LightLC_Get_OMModeStatus(MOBLEUINT8* plcOM_ModeState)
@@ -150,8 +151,8 @@ MOBLE_RESULT Appli_LightLC_Get_OMModeStatus(MOBLEUINT8* plcOM_ModeState)
 
 /**
 * @brief  Appli_LightLC_Get_OnOffStatus: This function is callback for Application
-to get the application values in middleware used for transition change.
-* @param  lcOnOffState: Pointer to the status message
+*         to get the application values in middleware used for transition change.
+* @param  plcOnOffState: Pointer to the status message
 * @retval MOBLE_RESULT
 */ 
 MOBLE_RESULT Appli_LightLC_Get_OnOffStatus(MOBLEUINT8* plcOnOffState)
@@ -164,17 +165,6 @@ MOBLE_RESULT Appli_LightLC_Get_OnOffStatus(MOBLEUINT8* plcOnOffState)
   return MOBLE_RESULT_SUCCESS;
 }  
 
-/**
-* @brief  Appli_LightLC_Get_PropertyStatus: This function is callback for Application
-to get the application values in middleware used for transition change.
-* @param  plcPropertyState: Pointer to the status message
-* @retval MOBLE_RESULT
-*/ 
-MOBLE_RESULT Appli_LightLC_Get_PropertyStatus(MOBLEUINT8* plcPropertyState)
-{  
-  return MOBLE_RESULT_SUCCESS;
-}  
-
 
 /**
 * @}
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light_lc.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light_lc.h
index d91a4cd5e..049d95308 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light_lc.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_light_lc.h
@@ -2,8 +2,8 @@
 ******************************************************************************
 * @file    appli_light_ctrl.h
 * @author  BLE Mesh Team
-* @version V1.10.000
-* @date    15-Jan-2019
+* @version V1.12.000
+* @date    06-12-2019
 * @brief   Application interface for Light Control Mesh Models  
 ******************************************************************************
 * @attention
@@ -32,7 +32,7 @@
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
-* Initial BlueNRG-Mesh is built over Motorolas Mesh over Bluetooth Low Energy 
+* Initial BLE-Mesh is built over Motorolas Mesh over Bluetooth Low Energy 
 * (MoBLE) technology. The present solution is developed and maintained for both 
 * Mesh library and Applications solely by STMicroelectronics.
 *
@@ -75,17 +75,14 @@ MOBLE_RESULT Appli_LightLC_Mode_Set(Light_LC_Param_t* pLight_LC_Param,
                                                      MOBLEUINT8 OptionalValid);
 MOBLE_RESULT Appli_LightLC_OM_Set(Light_LC_Param_t* pLight_LC_Param,
                                                      MOBLEUINT8 OptionalValid);
-MOBLE_RESULT Appli_LightLC_OnOff_Set(Light_LC_OnOffState_t* pLight_LC_Param,
+MOBLE_RESULT Appli_LightLC_OnOff_Set(Light_LC_Param_t* pLight_LC_Param,
                                                      MOBLEUINT8 OptionalValid);
 MOBLE_RESULT Appli_LightLC_Get_OnOffStatus(MOBLEUINT8* plcOnOffState);   
 MOBLE_RESULT Appli_LightLC_Get_ModeStatus(MOBLEUINT8* plcModeState);
 MOBLE_RESULT Appli_LightLC_Get_OMModeStatus(MOBLEUINT8* plcOM_ModeState);
-MOBLE_RESULT Appli_LightLC_Get_PropertyStatus(MOBLEUINT8* plcPropertyState);
 MOBLEUINT16 Appli_LightLC_Get_AmbientLuxLevelOutput(void);
 MOBLEUINT16 Appli_Light_LC_PIRegulatorOutput(MOBLEUINT16 tableLuxLevel,
                                                MOBLEUINT16 ambientLuxLevel);
-
-
 #endif /* __APPLI_LIGHT_LC_H */
 
 /******************* (C) COPYRIGHT 2017 STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_mesh.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_mesh.c
index 7d500a353..2402d0d7f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_mesh.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_mesh.c
@@ -29,22 +29,31 @@
 #include "models_if.h"
 #include "mesh_cfg.h"
 #include "generic.h"
+#include "common.h"
 #include "serial_if.h"
 #include "appli_nvm.h"
-//#include "gp_timer.h"
+#include "pal_nvm.h"
+#include "appli_config_client.h"
+#include "appli_generic_client.h"
+#include "appli_light_client.h"
 
 #include "stm32_seq.h"
 #include "PWM_config.h"
+#ifdef ENABLE_PROVISIONER_FEATURE
+#include "serial_prvn.h"
+#endif
+#include "mesh_cfg_usr.h"
 
-/** @addtogroup BLE_Mesh
+/** @addtogroup ST_BLE_Mesh
 *  @{
 */
 
-/** @addtogroup Application_Callbacks_BLE
+/** @addtogroup Application_Mesh_Models
 *  @{
 */
 
 /* Private define ------------------------------------------------------------*/
+#define APPLI_OPTIM                     0
 
 /*********** Macros to be modified according to the requirement *************/
 #define BOUNCE_THRESHOLD                20U
@@ -52,17 +61,28 @@
 #define MANUAL_UNPROVISION_TIMER        3000U
 #define FLASH_ERASE_TIME                100U
 //#define DISCOVER_TIMER                  10*60*1000 /* 10 minutes */
-#define DISCOVER_TIMER_INTERVAL         /*10*60**/(1000000/CFG_TS_TICK_VAL)  /* 10 minutes */
+#define DISCOVER_TIMER_INTERVAL         10*60*(1000000/CFG_TS_TICK_VAL)  /* 10 minutes */
+#if (APPLI_OPTIM == 1)
+#define APPLI_MESH_TIMER_INTERVAL       1*(1000/CFG_TS_TICK_VAL)  /* 1 ms */
+#endif
 #define DEFAULT_DELAY_PACKET_FROM         500U
 #define DEFAULT_DELAY_PACKET_RANDOM_TIME  500U
 #define USER_OUTPUT_OOB_APPLI_PROCESS           0U
 #define INPUT_OOB_TIMEOUT                       300U /* input Oob30 Sec timeout*/
 #define PBADV_UNPROV_DEV_BEACON_INTERVAL        100U /* 100 ms */
+#define DEVICE_KEY_SIZE                         16U
+#define APP_KEY_SIZE                            16U
+#if (LOW_POWER_FEATURE == 1)
+#define LPN_API_TIMER_INTERVAL           15*(1000000/CFG_TS_TICK_VAL)  /* 15 secondes */
+#endif
 /* Private macro -------------------------------------------------------------*/
 #define MAX_APPLI_BUFF_SIZE             8 
 #define MAX_PENDING_PACKETS_QUE_SIZE    2
 #define DATA_BUFFER_LENGTH              8
-#define MAX_NUMB_ELEMENTS 3
+#define MAX_NUMB_ELEMENTS               APPLICATION_NUMBER_OF_ELEMENTS
+#define CUSTOM_BEACON_AD_TYPE           0x00
+#define ENABLE_CUSTOM_BEACON            0
+#define CUSTOM_BEACON_INTERVAL          2000U
 
 /**********************Friendship callbacks macros ****************************/
 #define FN_CLEARED_REPEAT_REQUEST   1
@@ -77,9 +97,7 @@ enum ButtonState
   BS_OFF,
   BS_DEBOUNCE,
   BS_SHORT_PRESS,
-  BS_SHORT_PRESS2,
-  BS_LONG_PRESS,
-  BS_LONG_PRESS2
+  BS_LONG_PRESS
 };
 
 enum ButtonState buttonState = BS_OFF;
@@ -96,10 +114,17 @@ static MOBLEUINT8 PrvngInProcess = 0;
 static MOBLEUINT32 OutputOobData = 0;
 static MOBLEUINT32 OutputOobBlinkCount = 0;
 #endif
+
 #ifdef ENABLE_AUTH_TYPE_INPUT_OOB
 MOBLEUINT8 InputOobData[8] = {0};
 MOBLEUINT8 inputOOBDataReady = 0;
 #endif
+
+#ifdef ENABLE_PROVISIONER_FEATURE
+static MOBLEUINT8 NewProvNodeDevKey[DEVICE_KEY_SIZE] = {0};  
+static MOBLEUINT8 NewProvNodeAppKey[APP_KEY_SIZE] = {0}; 
+#endif
+MOBLEUINT16 nodeAddressOffset = 1;
 /*Number Of Elements selected per Node. Maximum Elements supported = 3*/
 MOBLEUINT8 NumberOfElements = APPLICATION_NUMBER_OF_ELEMENTS;
 
@@ -110,6 +135,7 @@ const MOBLEUINT8 StaticOobBuff[STATIC_OOB_SIZE] = {0x01, 0x00, 0x00, 0x00, 0x00,
 #else
 const MOBLEUINT8 StaticOobBuff[] = {0};
 #endif
+
 #ifdef PUB_KEY_TYPE_OOB
 /* 64 octets Public Key information to be input here. It is only required for Public Key OOB case.
 Used during provisioning by Library */
@@ -131,11 +157,14 @@ const MOBLEUINT8 PrivKeyBuff[] = NULL;
 
 
 
-/*Select Node as Sniffer, Means able to sniff all the packets*/
+/* Select Node as Sniffer, Means able to sniff all the packets 
+*  0 - Filters are enabled and packets not targeted to node are filtered
+*  1 - Filters are disabled and packets not targeted to node are not filtered
+*/
 MOBLEUINT8 DisableFilter = 0;
 
 #if LOW_POWER_FEATURE
-MOBLEINT32 BluenrgMesh_sleepTime;
+MOBLEINT32 BLEMesh_sleepTime;
 MOBLEUINT32 SysRefCount;
 #endif
 
@@ -147,30 +176,30 @@ MOBLEUINT8 provisioning_completion;
 /* Timer to control unprovisioned device beacons */
 #if PB_ADV_SUPPORTED
 MOBLEUINT8 discoverTimer_Id;
+tClockTime discoverTimerinterval = DISCOVER_TIMER_INTERVAL;
+#endif
+
+#if (APPLI_OPTIM == 1)
+MOBLEUINT8 appliTaskTimer_Id;
+#endif
+#if LOW_POWER_FEATURE
+volatile uint8_t BleProcessInit = 0;
+#endif
+#if (LOW_POWER_FEATURE == 1)
+MOBLEUINT8 lowPowerNodeApiTimer_Id;
 #endif
 
 /********************* Application configuration **************************/
 #if defined(__GNUC__) || defined(__IAR_SYSTEMS_ICC__) || defined(__CC_ARM)
 MOBLEUINT8 bdaddr[8];
-/* Mesh application data 1 sector used 125 */
-//extern const MOBLEUINT8 _bdaddr[];
-//const void *appNvmBase = _bdaddr;
-
-/* Mesh library configuration 2 sectors used: 126 and 127 */
-//extern const char* _bleNvmBase_data[];
-//const void *mobleNvmBase = _bleNvmBase_data;
 
 #ifdef INTERNAL_UNIQUE_NUMBER_MAC
 static void Appli_GetMACfromUniqueNumber(void);
 #endif /* INTERNAL_UNIQUE_NUMBER_MAC */
 
-/* NVM addresses for Nucleo 1Mb */
-const void *mobleNvmBase = (const void *)0x0807E000; /* 2 sectors used: 126 and 127 */ 
-const void *appNvmBase   = (const void *)0x0807D000; /* 1 sector  used: 125 */
-/* NVM addresses for Nucleo 512Kb */
-//const void *mobleNvmBase = (const void *)0x08056000; /* 2 sectors used: 86 and 87 */ 
-//const void *appNvmBase   = (const void *)0x08055000; /* 1 sector  used: 85 */
-
+const void *mobleNvmBase; 
+const void *appNvmBase;
+const void *prvsnr_data;
 #else
 #error "Unknown compiler"
 #endif /* __GNUC__ || defined(__IAR_SYSTEMS_ICC__) || defined(__CC_ARM) */
@@ -178,10 +207,20 @@ const void *appNvmBase   = (const void *)0x0807D000; /* 1 sector  used: 125 */
 /* Private function prototypes -----------------------------------------------*/
 //static void Appli_LongButtonPress(void);
 static void Appli_ShortButtonPress(void);
+#if USER_OUTPUT_OOB_APPLI_PROCESS
 void Appli_OobAuthenticationProcess(void);
+#endif
 void BLEMesh_UnprovisionCallback(MOBLEUINT8 reason);
 void Appli_LowPowerProcess(void);
-
+#if (PROVISIONER_FEATURE == 1)
+MOBLEUINT16 BLEMesh_PvnrDataInputCallback(MOBLEUINT8* devKey, MOBLEUINT8* appKey);
+#endif
+#if (APPLI_OPTIM == 1)
+static void AppliMeshTask(void);
+#endif
+#if (PROVISIONER_FEATURE == 1) 
+void Appli_SelfConfigurationProcess(void);
+#endif
 /* Private functions ---------------------------------------------------------*/
 
 /************************* Button Control functions ********************/
@@ -214,75 +253,21 @@ static void Appli_LongButtonPress(void)
 */ 
 static void Appli_UpdateButtonState(int isPressed)
 {
-  /* Check for button state */
-  switch (buttonState)
-  {
-    /* Case for Button State off */
-  case BS_OFF:
-    if (isPressed)
-    {
-        /* move to debounce state */
-      buttonState = BS_DEBOUNCE;
-      tBounce = Clock_Time();
-    }
-    break;
-    /* Case for Button Debounce */
-  case BS_DEBOUNCE:
-    if (isPressed)
-    {
-      /* Debouncing Delay check */
-      if (Clock_Time() - tBounce > BOUNCE_THRESHOLD)
-      {   
-        if (BSP_PB_GetState(BUTTON_SW1) == BUTTON_PRESSED)    
-          buttonState = BS_SHORT_PRESS;
-      }
-      else
-      {
-          /* continue to be in BS_DEBOUNCE */
-      }
-    }
-    else
-    {
-      buttonState = BS_OFF;
-      }
-      break;
-    /* Case if Button 1 is pressed for duration > BOUNCE_THRESHOLD */
-  case BS_SHORT_PRESS:
-      if (isPressed)
-      {
-        if ((Clock_Time() - tBounce) > LONG_PRESS_THRESHOLD)
-    {
-          /* If Button 1 is pressed for duration > LONG_PRESS_THRESHOLD  */
-      buttonState = BS_LONG_PRESS;
-    }
-    else
-    {
-          /* continue in same state */
-        }
-      }
-      else
-      {
-        /* Button 1 short press action */
-        Appli_ShortButtonPress();
+  uint32_t t0 = 0,t1 = 1;
+
+  t0 = Clock_Time(); /* SW1 press timing */
   
-        buttonState = BS_OFF;
-      }
-      break;
-    case BS_LONG_PRESS:
-      if (isPressed)
-      {
-        /* Long press action */
-        Appli_IntensityControlPublishing();
-    }
-      else
-    {
-        buttonState = BS_OFF;
-    }
-    break;
-    /* Default case */
-  default:
-    buttonState = BS_OFF;
-    break;
+  while(BSP_PB_GetState(BUTTON_SW1) == BUTTON_PRESSED);
+  t1 = Clock_Time(); /* SW1 release timing */
+  
+  if((t1 - t0) > LONG_PRESS_THRESHOLD)
+  {
+    IntensityPublish();
+  }
+  else if((t1 - t0) > BOUNCE_THRESHOLD)
+  {
+    /* Button 1 short press action */
+    Appli_ShortButtonPress();
   }
 }
 
@@ -291,14 +276,34 @@ static void Appli_UpdateButtonState(int isPressed)
 * @param  void
 * @retval void
 */ 
-static void Appli_Mesh_Process()
+static void Mesh_Task()
 {
   BLEMesh_Process();
   BLEMesh_ModelsProcess(); /* Models Processing */
-  Appli_Process();
   
+#if (APPLI_OPTIM == 0)
   /* Set the task in the scheduler for the next execution */
+#if (LOW_POWER_FEATURE == 0)
   UTIL_SEQ_SetTask( 1< MAX_NUMB_ELEMENTS)
   {
-    TRACE_M(TF_ELEMENTS,"Currently Three Elements per node are supported!\r\n"); 
+    TRACE_M(TF_ELEMENTS,"In version 1.11.00x one Element per node is supported!\r\n"); 
     return MAX_NUMB_ELEMENTS;
   }
+  
+  else if(NumberOfElements == 0)
+  {
+    TRACE_M(TF_ELEMENTS,"Number Of Elements must be 1 or greater than 1!\r\n"); 
+    return 1;
+  }
+  
   else
   {
   return NumberOfElements;
@@ -665,6 +669,12 @@ void Appli_CheckForUnprovision(void)
     if (!interrupted)
     {
       BLEMesh_Unprovision();
+      
+      MoblePalNvmErase(NVM_BASE, 0);      
+      MoblePalNvmErase(NVM_BASE, 0x1000);
+      MoblePalNvmErase(APP_NVM_BASE, 0);
+      MoblePalNvmErase(PRVN_NVM_BASE_OFFSET, 0);
+      
       AppliNvm_ClearModelState();     
       TRACE_M(TF_PROVISION,"Device is unprovisioned by application \r\n");      
       t = Clock_Time();
@@ -679,12 +689,30 @@ void Appli_CheckForUnprovision(void)
       }
     }
     BSP_LED_Off(LED_BLUE);
+    NVIC_SystemReset();
   }
   
   /* Register the task for all MESH dedicated processes */
-  UTIL_SEQ_RegTask( 1<< CFG_TASK_MESH_REQ_ID, UTIL_SEQ_RFU, Appli_Mesh_Process );
+  UTIL_SEQ_RegTask( 1<< CFG_TASK_MESH_REQ_ID, UTIL_SEQ_RFU, Mesh_Task );
   /* Set the task in the scheduler for the next scheduling */
+#if (LOW_POWER_FEATURE == 0)
   UTIL_SEQ_SetTask( 1< ", count);  
+          BLEMesh_PrintDataCb(unprovDeviceArray[count].uuid, 16);
+        }
+    }
+  return result;
+}
+/**
+* @brief  This function returns starts the provisioning of one of the devices
+* @param  unprovDeviceArray: Pointer of an array having unprovisioned device UUIDs
+* @param  index: Index of the device to be provisioned
+* @retval MOBLE_RESULT
+*/  
+MOBLE_RESULT BLEMesh_ProvisionDevice(neighbor_params_t *unprovDeviceArray, MOBLEUINT16 index)
+{
+  MOBLE_RESULT result = MOBLE_RESULT_SUCCESS;
+    
+  result = BLEMesh_ProvisionRemote((unprovDeviceArray+index)->uuid);
+
+  return result;
+}
+
+/* Customized implementation for provisioning a device from mesh node - End */
+
+/**
+* @brief  Call back function called when PB-ADV link Opened  
+* @param  none
+* @retval none
+*/ 
+void BLEMesh_PbAdvLinkOpenCb(void)
+{ 
+  ProvisionFlag = 0;
+  TRACE_M(TF_PROVISION,"PB-ADV Link opened successfully \n\r");    
+#ifdef ENABLE_PROVISIONER_FEATURE
+  SerialPrvn_ProvisioningStatusUpdateCb(MOBLE_TRUE, 0);
+#endif
+  /* Turn ON Red LED*/
+#if LOW_POWER_FEATURE
+  /* do nothing */
+#else
+  BSP_LED_On(LED_RED);
+#endif
 }
 
+/**
+* @brief  Call back function called when PB-ADV link Closed   
+* @param  none
+* @retval none
+*/ 
+void BLEMesh_PbAdvLinkCloseCb(void)
+{
+  TRACE_M(TF_PROVISION,"PB-ADV Link Closed successfully \n\r");   
+  /* Turn Off Red LED*/
+#if LOW_POWER_FEATURE
+  /* do nothing */
+#else
+  BSP_LED_Off(LED_RED);
+#ifdef ENABLE_PROVISIONER_FEATURE
+  SerialPrvn_ProvisioningStatusUpdateCb(MOBLE_FALSE, nodeAddressOffset);
+#endif
+#endif
+  #if (PROVISIONER_FEATURE == 1)
+  if (ProvisionFlag == 1)
+  {
+    SaveProvisionedNodeAddress();
+    ProvisionFlag = 0;
+  }
+#endif
+}
 /**
 * @brief  callback for friendship established by friend node
 * @param  address of corresponding low power node
@@ -854,7 +1120,7 @@ void BLEMesh_FnFriendshipEstablishedCallback(MOBLE_ADDRESS lpnAddress,
 { 
   TRACE_M(TF_LPN_FRND,"Friendship established. Low power node address 0x%.4X \r\n", lpnAddress);
   TRACE_M(TF_LPN_FRND,"Low power node receive delay %dms \r\n", lpnReceiveDelay);
-  TRACE_M(TF_LPN_FRND,"Low power node poll timeout %dms \r\n", lpnPollTimeout*100);
+  TRACE_M(TF_LPN_FRND,"Low power node poll timeout %ldms \r\n", lpnPollTimeout*100);
   TRACE_M(TF_LPN_FRND,"Low power node number of elements %d \r\n", lpnNumElements);
   if (lpnPrevFriendAddress != MOBLE_ADDRESS_UNASSIGNED)
   {
@@ -901,6 +1167,7 @@ void BLEMesh_FnFriendshipClearedCallback(MOBLEUINT8 reason, MOBLE_ADDRESS lpnAdd
 void BLEMesh_LpnFriendshipEstablishedCallback(MOBLE_ADDRESS fnAddress)
 {
   /* Friendship established */
+  TRACE_M(TF_LPN_FRND,"Friend node responding, friendship established.\r\n");
 }
 
 /**
@@ -1054,82 +1321,81 @@ void BLEMesh_NeighborRefreshedCallback(const MOBLEUINT8* bdAddr,
   TRACE_M(TF_NEIGHBOUR,"\n\r");
 }
 
-/**
-* @brief  Appli_IntensityControl:Function to increase the intensity of led by
-*          Publishing the value.
-* @param  void
+/** 
+* @brief  Beacon received callback
+*         Beacons are received only if received beacon ad type is not 
+*         Mesh Message, Mesh Beacon or PB-ADV
+* @param  MAC address
+*         data
+*         length of beacon
+*         rssi value of beacon
+* @retval void
 */
-void Appli_IntensityControlPublishing(void)
+#if (ENABLE_CUSTOM_BEACON == 1)
+/* BLEMesh_CustomBeaconReceivedCallback high frequency callback */
+void BLEMesh_CustomBeaconReceivedCallback(const MOBLEUINT8* bdAddr,
+                                              const MOBLEUINT8* data,
+                                              MOBLEUINT8 length,
+                                              MOBLEINT8 rssi)
 {
-  MOBLEUINT8 generic_Level_Buff[3];
-  MOBLE_ADDRESS publishAddress;
-  MOBLEUINT8 elementNumber;
-  MOBLEUINT8 elementIndex;
-        
-  /*Select the Element Number for which publication address is required*/
-  
-  if (NumberOfElements == 1)
-  {
-    elementNumber = 0x01; 
-  }
-  
-  else if(NumberOfElements == 2)
-  { 
-    elementNumber = 0x02; /*Element 2 is configured as switch*/
-  }
+  MOBLE_RESULT result = MOBLE_RESULT_SUCCESS;
   
-  else if(NumberOfElements == 3)
+  if (length < 2)
   {
-    elementNumber = 0x03; /*Element 3 is configured as switch*/
+    result = MOBLE_RESULT_FAIL;
+    TRACE_M(TF_BEACON, "Message is too small \r\n");
   }
   
-  else
+  if (result == MOBLE_RESULT_SUCCESS)
   {
-    elementNumber = 0x01;
+    if ((length-1) < data[0])
+    {
+      result = MOBLE_RESULT_FAIL;
+      TRACE_M(TF_BEACON, "Length field does not match with message length \r\n");
+    }    
   }
   
-  publishAddress = BLEMesh_GetPublishAddress(elementNumber);
-  elementIndex = elementNumber-1;
-  
-  TRACE_M(TF_MISC,"IntensityFlag %d\n\r", IntensityFlag);
-      
-  if(IntensityFlag == FALSE)
+  if (result == MOBLE_RESULT_SUCCESS)
   {
-      
-    IntensityValue = IntensityValue + (INTENSITY_LEVEL_FULL/5);
-    generic_Level_Buff[0] = (MOBLEUINT8)IntensityValue;
-    generic_Level_Buff[1] = (MOBLEUINT8)(IntensityValue >> 8) ;
-    
-    TRACE_M(TF_MISC,"IntensityValue %d\n\r", IntensityValue);
+    MOBLEUINT8 adType = data[1];
+    MOBLEUINT8 i;
     
-    BLEMesh_SetRemoteData(publishAddress, elementIndex, GENERIC_LEVEL_SET_UNACK , 
-                          generic_Level_Buff,3, MOBLE_FALSE, MOBLE_FALSE);
-    
-    if(IntensityValue >= INTENSITY_LEVEL_FULL)
+    if (adType == CUSTOM_BEACON_AD_TYPE)
     {
-      IntensityFlag = TRUE;
+      TRACE_M(TF_BEACON, "Message length(%d), ad type(0x%.2x), rssi(%d) \r\n", length-2, adType, rssi);        
+      TRACE_M(TF_BEACON, "Message:\r\n");        
+      for(i = 0; i < length-2; i++)
+        TRACE_M(TF_BEACON, "data[%d]= %d\r\n", i, data[2+i]);
     }
-     
-  }
-  else
-  {
-     
-    IntensityValue = IntensityValue - (INTENSITY_LEVEL_FULL/5);
-    generic_Level_Buff[0] = (MOBLEUINT8)IntensityValue;
-    generic_Level_Buff[1] = (MOBLEUINT8)(IntensityValue >> 8) ;
-    
-    TRACE_M(TF_MISC,"IntensityValue %d\n\r", IntensityValue);
-    
-    BLEMesh_SetRemoteData(publishAddress, elementIndex, GENERIC_LEVEL_SET_UNACK, 
-                              generic_Level_Buff, 3, MOBLE_FALSE, MOBLE_FALSE); 
-    
-    if(IntensityValue <= INTENSITY_LEVEL_ZERO)
+    else
     {
-      IntensityFlag = FALSE;
+      /* Discard, Ad type mismatch */
     }
-  
   }
 }
+#endif /* BLEMesh_CustomBeaconReceivedCallback high frequency callback */
+
+/** 
+* @brief  Custom beacon generator
+*         If size set to > 31 bytes, beacon is rejected
+*         BLEMesh_SetCustomBeaconInterval should be set to get this callback
+* @param  beacon data buffer. It includes length and AD type fields
+*         buffer size
+* @retval void
+*/
+void BLEMesh_CustomBeaconGeneratorCallback(void* buffer, MOBLEUINT8* size)
+{
+  MOBLEUINT8 adType = CUSTOM_BEACON_AD_TYPE;
+  MOBLEUINT8 dataLength = 5;
+  MOBLEUINT8 data[5] = {0x00,0x01,0x02,0x03,0x04};
+  MOBLEUINT8* buf = (MOBLEUINT8*)buffer;
+  
+  buf[0] = dataLength+1;
+  buf[1] = adType;
+  memcpy(buf+2, data, dataLength);
+  
+  *size = dataLength+2;  
+}
 
 /**
 * @brief  Low Power mode process 
@@ -1168,6 +1434,61 @@ void Appli_LowPowerProcess(void)
 #endif
 }
 
+/**
+* @brief  Appli_IntensityControlPublishing:Function is used to set the intensity value.
+*          Publishing the value.
+* @param  void
+* @retval void
+*/
+void Appli_IntensityControlPublishing(MOBLEUINT8* value)
+{
+      
+  if(IntensityFlag == FALSE)
+  {
+      
+    IntensityValue = IntensityValue + (INTENSITY_LEVEL_FULL/5);
+    value[0] = (MOBLEUINT8)IntensityValue;
+    value[1] = (MOBLEUINT8)(IntensityValue >> 8) ;
+    
+    if(IntensityValue >= INTENSITY_LEVEL_FULL)
+    {
+      IntensityFlag = TRUE;
+    }
+     
+  }
+  else
+  {
+     
+    IntensityValue = IntensityValue - (INTENSITY_LEVEL_FULL/5);
+    value[0] = (MOBLEUINT8)IntensityValue;
+    value[1] = (MOBLEUINT8)(IntensityValue >> 8) ;    
+    
+    if(IntensityValue <= INTENSITY_LEVEL_ZERO)
+    {
+      IntensityFlag = FALSE;
+    }
+  
+  }
+}
+
+/**
+* @brief  Publish the intensity value for generic level or light lightness 
+*         This function should be called in main loop
+* @param  void
+* @retval void
+*/
+void IntensityPublish(void)
+{  
+  
+#ifdef LIGHT_CLIENT_MODEL_PUBLISH 
+  Appli_LightClient_Lightness_Set();
+#endif
+  
+#ifdef GENERIC_CLIENT_MODEL_PUBLISH
+  Appli_GenericClient_Level_Set_Unack();
+#endif  
+}
+
 /**
 * @brief  Application processing 
 *         This function should be called in main loop
@@ -1176,10 +1497,15 @@ void Appli_LowPowerProcess(void)
 */
 void Appli_Process(void)
 {
-  Appli_UpdateButtonState(BSP_PB_GetState(BUTTON_SW1) == BUTTON_PRESSED);
-
-  Appli_LowPowerProcess();
+#ifdef ENABLE_SAVE_MODEL_STATE_NVM  
+  AppliNvm_Process();
+#endif
   
+#if (SAVE_EMBD_PROVISION_DATA == 1)  
+  AppliPrvnNvm_Process();
+#endif    
+    
+  Appli_LowPowerProcess();
 #ifdef ENABLE_AUTH_TYPE_OUTPUT_OOB
   if(PrvngInProcess)
   {
@@ -1188,10 +1514,11 @@ void Appli_Process(void)
 #endif
   }
 #endif
-#ifdef ENABLE_SAVE_MODEL_STATE_NVM  
-  AppliNvm_Process();
+
+#if PROVISIONER_FEATURE      
+  Appli_ConfigClient_Process();
+  Appli_SelfConfigurationProcess();
 #endif
-  
 }
 
 #if PB_ADV_SUPPORTED
@@ -1213,6 +1540,40 @@ static void UnprovisionedDeviceBeaconTask(void)
 }
 #endif
 
+#if (APPLI_OPTIM == 1)
+static void AppliMeshTask(void)
+{
+  /* Set the task in the scheduler for the next execution */
+  UTIL_SEQ_SetTask( 1<
 #include "hal_common.h"
 #include "ble_mesh.h"
+#include "mesh_cfg_usr.h"
 #include "appli_nvm.h"
 #include "mesh_cfg.h"
 #include "pal_nvm.h"
@@ -28,32 +29,50 @@
 #ifdef SAVE_MODEL_STATE_FOR_ALL_MESSAGES
 #include "common.h"
 #endif
+#if (LOW_POWER_FEATURE == 1)
+#include "app_conf.h"
+#include "stm32_seq.h"
+#endif
+
+/** @addtogroup ST_BLE_Mesh
+*  @{
+*/
+
+/** @addtogroup Application_Mesh_Models
+*  @{
+*/
+/* Private define ------------------------------------------------------------*/
 
 extern const MOBLEUINT8* _bdaddr[];
-//extern const void* mobleNvmBase;
+extern const MOBLEUINT8* _prvsnr_data[];
+
 #ifdef SAVE_MODEL_STATE_FOR_ALL_MESSAGES
 extern MOBLEUINT8 PowerOnOff_flag;
 #endif
+MOBLEUINT8 PrvnFlag = 0;
+
+#if defined SAVE_EMBD_PROVISION_DATA  
+MOBLEUINT8 DataCopy[2048];
+#endif
+#ifdef ENABLE_PROVISIONER_FEATURE
+extern MOBLEUINT16 nodeAddressOffset;
+#endif
+
 extern const void* appNvmBase;
+extern const void* prvsnr_data;
 
-/* Reserved for Bluenrg-Mesh library */
-//#define BLUENRGMESH_NVM_BASE               ((unsigned int)mobleNvmBase)
-//#define BLUENRGMESH_NVM_BACKUP_BASE        (BLUENRGMESH_NVM_BASE + PAGE_SIZE)
 
 /*
-*  Page of size 2k, BlueNRG-1 and BlueNRG-2, reserved for application is divided into 8 subpages of each 256 bytes
+*  Page of size 4k, STM32WB, reserved for application is divided into 16 subpages of each 256 bytes
 *  First subpage is reserved (for e.g. External MAC is present in this area)
-*  Rest 7 subpages are used on rolling basis for application states. 
+*  Rest 15 subpages are used on rolling basis for application states. 
 *    First byte of each subpage indicates if page is valid or not
 */
-//#define APP_NVM_BASE                      ((unsigned int)_bdaddr)
-#define APP_NVM_BASE                      ((unsigned int)appNvmBase)
-#define APP_NVM_SIZE                      0x00001000
 
 #define APP_NVM_RESERVED_SIZE             256U
 #define APP_NVM_SUBPAGE_SIZE              256U
 #define APP_NVM_MAX_SUBPAGE               15U
-#define APP_NVM_SUBPAGE_OFFSET(i)         (unsigned int)(APP_NVM_RESERVED_SIZE+256*(i))
+#define APP_NVM_SUBPAGE_OFFSET(i)         (unsigned int)(APP_NVM_SUBPAGE_SIZE + APP_NVM_SUBPAGE_SIZE*(i))
 
 /* offsets defined wrt start of subpage */
 #define APP_NVM_VALID_FLAG_OFFSET         0U
@@ -65,6 +84,14 @@ extern const void* appNvmBase;
 #define APP_NVM_LIGHT_MODEL_OFFSET        (unsigned int)(APP_NVM_VALID_FLAG_SIZE+APP_NVM_RESET_COUNT_SIZE+APP_NVM_GENERIC_MODEL_SIZE)
 #define APP_NVM_LIGHT_MODEL_SIZE          16U
 
+/* offset defined for the embedded provisioner node */
+#define PRVN_NVM_SUBPAGE_SIZE             16U
+#define PRVN_NVM_MAX_SUBPAGE              (unsigned int)(PRVN_NVM_PAGE_SIZE/PRVN_NVM_SUBPAGE_SIZE)
+#define PRVN_NVM_SUBPAGE_OFFSET(i)        (unsigned int)(PRVN_NVM_SUBPAGE_SIZE*(i))
+
+#define FIRST_PRVND_NODE_ADDRSS           2U
+#define LAST_PRVND_NODE_ADDRSS            (unsigned int)(PRVN_NVM_MAX_SUBPAGE+FIRST_PRVND_NODE_ADDRSS)
+
 /* Private variables ---------------------------------------------------------*/
 typedef struct
 {
@@ -73,14 +100,32 @@ typedef struct
   MOBLEBOOL writeReq;
 } APPLI_NVM_REQS;
 
-APPLI_NVM_REQS AppliNvm_Reqs;
+/* ALIGN(4) */
+__attribute__((aligned(4))) APPLI_NVM_REQS AppliNvm_Reqs;
+
+typedef struct
+{
+  MOBLEUINT8  prvnData[PRVN_NVM_SUBPAGE_SIZE];
+  MOBLEBOOL erasePageReq;
+  MOBLEBOOL writeReq;
+} PRVN_NVM_REQS;
+
+/* ALIGN(4) */
+__attribute__((aligned(4))) PRVN_NVM_REQS  PrvnNvm_Reqs;
 
 MOBLE_RESULT AppliNvm_EraseRestoreResvNvm(void);
-MOBLE_RESULT AppliNvm_FindFirstValidSubPage(MOBLEINT8* subPageIndex);
+MOBLE_RESULT AppliNvm_FindFirstEmptyPage(MOBLEINT8* subPageIndex,MOBLEUINT32 SubPageSize,
+                                          MOBLEUINT32 totalSubPage, MOBLEUINT32 nvmBaseOffset);
+//MOBLE_RESULT AppliNvm_FindFirstValidSubPage(MOBLEINT8* subPageIndex);
 MOBLE_RESULT AppliNvm_MarkSubpageInvalid(void);
 MOBLE_RESULT AppliNvm_FlashProgram(MOBLEUINT32 offset, void const *buf, MOBLEUINT32 size);
-MOBLE_RESULT AppliNvm_LoadGenericState(uint8_t state[], uint8_t* size);
-MOBLE_RESULT AppliNvm_LoadLightState(uint8_t state[], uint8_t* size);
+//MOBLE_RESULT AppliNvm_LoadGenericState(uint8_t state[], uint8_t* size);
+//MOBLE_RESULT AppliNvm_LoadLightState(uint8_t state[], uint8_t* size);
+//MOBLE_RESULT AppliNvm_PrvnFindFirstValidSubPage(MOBLEINT8* subPageIndex);
+//MOBLE_RESULT AppliNvm_PrvnMarkSubpageInvalid(void);
+//MOBLE_RESULT AppliNvm_SavePrvsnerData(uint8_t* data, uint8_t size);
+MOBLEUINT32* AppliPrvnNvm_GetSubPageData(MOBLE_ADDRESS addrss);
+MOBLE_RESULT AppliPrvnNvm_FlashProgram(MOBLEUINT32 offset, void const *buf, MOBLEUINT32 size);
 
 #if 0
 /**
@@ -118,7 +163,6 @@ MOBLE_RESULT AppliNvm_FlashErase(uint16_t PageNumber)
 *  @param  Data: word to write
 *  @retval MOBLE_RESULT_SUCCESS on success
 */
-//MOBLE_RESULT AppliNvm_FlashProgram(uint32_t TypeProgram, uint32_t Address, uint32_t Data[])
 MOBLE_RESULT AppliNvm_FlashProgram(MOBLEUINT32 offset, void const *buf, MOBLEUINT32 size)
 {
   MOBLE_RESULT result = MOBLE_RESULT_SUCCESS;
@@ -151,6 +195,46 @@ MOBLE_RESULT AppliNvm_FlashProgram(MOBLEUINT32 offset, void const *buf, MOBLEUIN
   return result;
 }
 
+/** 
+*  @brief  Program word (32-bit) at a PRVN_NVM_BASE_OFFSET
+*  @param  TypeProgram  Indicate the way to program at a specified address
+*  @param  Address: address to write
+*  @param  Data: word to write
+*  @retval MOBLE_RESULT_SUCCESS on success
+*/
+MOBLE_RESULT AppliPrvnNvm_FlashProgram(MOBLEUINT32 offset, void const *buf, MOBLEUINT32 size)
+{
+  MOBLE_RESULT result = MOBLE_RESULT_SUCCESS;
+  
+  if (offset > PRVN_NVM_PAGE_SIZE)
+  {
+    result = MOBLE_RESULT_INVALIDARG;
+  }
+  else if (size == 0)
+  {
+    result = MOBLE_RESULT_FALSE;
+  }
+  else if (offset + size > (PRVN_NVM_BASE_OFFSET + PRVN_NVM_PAGE_SIZE))
+  {
+    result = MOBLE_RESULT_INVALIDARG;
+  }
+  else if (offset & 3)
+  {
+    result = MOBLE_RESULT_INVALIDARG;
+  }
+  else if (size & 3)
+  {
+    result = MOBLE_RESULT_INVALIDARG;
+  }
+  else
+  {
+    result = MoblePalNvmWrite(PRVN_NVM_BASE_OFFSET, offset, buf, size);
+  }
+  
+  return result;
+}
+
+#if 0
 /**
 *  @brief  Find first valid subpage available. 
 *          If no valid subpage found, erase page appli nvm to reset it
@@ -180,6 +264,9 @@ MOBLE_RESULT AppliNvm_FindFirstValidSubPage(MOBLEINT8* subPageIndex)
   if (subPageIdx < 0)
   {
     AppliNvm_Reqs.erasePageReq = MOBLE_TRUE;
+#if (LOW_POWER_FEATURE == 1)
+    UTIL_SEQ_SetTask( 1< 0xFFFFFFE0)
+    /* Check for "POWER_ON_OFF_CYCLES_FOR_UNPROVISIONING" times, that many bits shall be zero */
+    if (resetCount > MASK_BITS_FOR_POWER_ON_OFF_CYCLES)
     {
+      /* MASK_BITS_FOR_POWER_ON_OFF_CYCLES = 0xFFFFFFE0 */
+      
       /* update reset count */
       result = AppliNvm_FlashProgram(APP_NVM_SUBPAGE_OFFSET(currSubPageIdx),
                                      (uint32_t*)&subPageTemp, 
@@ -301,10 +398,22 @@ MOBLE_RESULT AppliNvm_FactorySettingReset(void)
       
       /* Blink twice to indicate device startup 
          1 second to blink once and 2 seconds to blink twice */
-      for (MOBLEUINT8 i=0; i<2; i++)
+      for (MOBLEUINT8 i=0; i< ON_TIME_IN_SECONDS_FOR_POWER_CYCLING; i++)
       {
         Appli_LedBlink();
       }
+      
+      /* Load model data copy from nvm */
+      memcpy((void*)AppliNvm_Reqs.modelData, 
+             (void*)(APP_NVM_SUBPAGE_OFFSET(currSubPageIdx)+APP_NVM_GENERIC_MODEL_OFFSET), 
+             APP_NVM_GENERIC_MODEL_SIZE+APP_NVM_LIGHT_MODEL_SIZE);
+      
+      result = AppliNvm_MarkSubpageInvalid();
+      
+      if (MOBLE_FAILED(result))
+      {
+        result = MOBLE_RESULT_FAIL;
+      }
     }
     else /* Device is forced to factory reset, 5 LSBs are zero */
     {
@@ -320,7 +429,7 @@ MOBLE_RESULT AppliNvm_FactorySettingReset(void)
       BLEMesh_SetUnprovisionedDevBeaconInterval(100);
       
       /* Blink 5 times to indicate factory setting reset */
-      for (MOBLEUINT8 i=0; i<5; i++)
+      for (MOBLEUINT8 i=0; i PRVN_NVM_SUBPAGE_SIZE)
+  {
+    /* incorrect size */
+    result = MOBLE_RESULT_FAIL;
+  }
+  else
+  {
+    memcpy(PrvnNvm_Reqs.prvnData, data, size);
+    PrvnNvm_Reqs.writeReq = MOBLE_TRUE;
+#if (LOW_POWER_FEATURE == 1)
+    UTIL_SEQ_SetTask( 1<= PRVN_NVM_MAX_SUBPAGE)
+  {
+    TRACE_M(TF_PROVISION,"Invalid Address \r\n");
+    return 0;   
+  }
+  else
+  {
+    subPageAddrss = (MOBLEUINT32 *)(PRVN_NVM_BASE_OFFSET + PRVN_NVM_SUBPAGE_OFFSET(subPageIndx));
+    TRACE_M(TF_PROVISION,"Address Of SubPage =  %p \r\n", (void *)subPageAddrss);
+  }
+  return subPageAddrss;
+}
+
+/**
+* @brief  backup by Copy all the data from the page in RAM.
+* @param  model state buff
+* @param  model state buff size
+* @retval MOBLE_RESULT_SUCCESS on success
+*/
+MOBLE_RESULT AppliPrvnNvm_CopyData(uint8_t state[], uint8_t* size)
+{
+  
+#if SAVE_EMBD_PROVISION_DATA    
+  MOBLEUINT8 deviceKeysSaved[2048]; 
+  MOBLE_RESULT result = MOBLE_RESULT_SUCCESS;
+  
+  /* find valid subpage */
+    for (MOBLEUINT8 count=0; count<8; count++)
+    {    
+      memcpy((void*)deviceKeysSaved, (void*)(PRVN_NVM_BASE_OFFSET + PRVN_NVM_SUBPAGE_OFFSET(count)), PRVN_NVM_SUBPAGE_SIZE);
+    }
+    
+  *size = PRVN_NVM_SUBPAGE_SIZE;
+  
+  return result;  
+#else /* SAVE_EMBD_PROVISION_DATA */  
+  *size = 0;
+  return MOBLE_RESULT_SUCCESS;
+#endif /* SAVE_EMBD_PROVISION_DATA */
+    
+}
+
+/**
+* @brief  Process Provisioner NVM erase and write requests
+* @param  void
+* @retval void
+*/
+void AppliPrvnNvm_Process(void)
+{
+  MOBLE_RESULT result;
+  MOBLEINT8 subPageIdx;
+  
+  if ( (PrvnNvm_Reqs.erasePageReq == MOBLE_FALSE) && 
+       (PrvnNvm_Reqs.writeReq == MOBLE_TRUE) )
+  {
+    result = AppliNvm_FindFirstEmptyPage(&subPageIdx,PRVN_NVM_SUBPAGE_SIZE,
+                                          PRVN_NVM_MAX_SUBPAGE,PRVN_NVM_BASE_OFFSET);
+    
+    if (result == MOBLE_RESULT_SUCCESS)
+    {
+      TRACE_M(TF_PROVISION,"Saving in SubPage[%.8x] = \r\n", PRVN_NVM_SUBPAGE_OFFSET(subPageIdx));
+      result = AppliPrvnNvm_FlashProgram(PRVN_NVM_SUBPAGE_OFFSET(subPageIdx), 
+                                     PrvnNvm_Reqs.prvnData,
+                                     PRVN_NVM_SUBPAGE_SIZE);
+    
+      if (result == MOBLE_RESULT_SUCCESS)
+      {
+        PrvnNvm_Reqs.writeReq = MOBLE_FALSE;
+      }
+    }
+    else
+    {
+      //AppliNvm_Reqs.erasePageReq = MOBLE_TRUE;
+    }
+  }
+}
+
+/**
+* @brief  This function is to save the provisioner device key in the flash.          
+* @param  data:Pointer to the data passed.
+* @param  size:size of the data
+* @param  prvnFlag:Pointer to the flag passed.
+* @retval void
+*/
+void AppliNvm_saveProvisionerDevKey(MOBLEUINT8 *data , MOBLEUINT8 size , MOBLEUINT8 *prvnFlag)
+{
+  if(*prvnFlag == 1)
+  {
+    AppliPrvnNvm_SaveData(&data[0] ,size);
+    prvnFlag = 0;
+  }
+}
+
+/**
+* @brief  This function load the Provisioner nvm data to the buffer after reset.          
+* @param  void
+* @retval MOBLE_RESULT_SUCCESS on success
+*/
+MOBLE_RESULT AppliPrvnNvm_FactorySettingReset(MOBLEUINT8 *flag)
+{
+  MOBLEINT8 currSubPageIdx;
+  MOBLE_RESULT result = MOBLE_RESULT_SUCCESS;
+    
+  result = AppliNvm_FindFirstEmptyPage(&currSubPageIdx,PRVN_NVM_SUBPAGE_SIZE,
+                                       PRVN_NVM_MAX_SUBPAGE,PRVN_NVM_BASE_OFFSET);
+  
+  if(result == MOBLE_RESULT_OUTOFMEMORY)
+  {
+    result = MOBLE_RESULT_FAIL;
+    //AppliNvm_Reqs.erasePageReq = MOBLE_TRUE;
+  }
+  else
+  {    
+      /* After reset of provisioner , retreiving the next node address to be provisioned */
+#ifdef ENABLE_PROVISIONER_FEATURE
+    
+      if(currSubPageIdx > 0)
+      {
+        nodeAddressOffset = currSubPageIdx + 1;         
+      }
+      
+#endif           
+          
+      
+      if(currSubPageIdx > 0)
+      {
+        currSubPageIdx = currSubPageIdx-1;
+      }
+      
+      /* Load model data copy from nvm */
+      memcpy((void*)PrvnNvm_Reqs.prvnData, 
+             (void*)(PRVN_NVM_BASE_OFFSET + PRVN_NVM_SUBPAGE_OFFSET(currSubPageIdx)),PRVN_NVM_SUBPAGE_SIZE);          
+          
+      
+      TRACE_I(TF_PROVISION,"NEXT NVM ADDRESS %.8x \r\n",PRVN_NVM_SUBPAGE_OFFSET(currSubPageIdx+PRVN_NVM_SUBPAGE_SIZE));
+      
+   }
+     
+  return result;
+}
+
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_nvm.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_nvm.h
index 769dc76ad..96479cedc 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_nvm.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_nvm.h
@@ -2,8 +2,8 @@
 ******************************************************************************
 * @file    appli_nvm.h
 * @author  BLE Mesh Team
-* @version V1.10.000
-* @date    15-Jan-2019
+* @version V1.11.000
+* @date    25-07-2019
 * @brief   Header file for the user application file 
 ******************************************************************************
 * @attention
@@ -32,7 +32,7 @@
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
-* Initial BlueNRG-Mesh is built over Motorolas Mesh over Bluetooth Low Energy 
+* Initial BLE-Mesh is built over Motorolas Mesh over Bluetooth Low Energy 
 * (MoBLE) technology. The present solution is developed and maintained for both 
 * Mesh library and Applications solely by STMicroelectronics.
 *
@@ -46,6 +46,10 @@
 /* Includes ------------------------------------------------------------------*/
 /* Exported macro ------------------------------------------------------------*/
 /* Exported variables  ------------------------------------------------------- */
+#define APP_NVM_BASE                                  ((unsigned int)appNvmBase)
+#define APP_NVM_SIZE                                                       4096U
+#define PRVN_NVM_BASE_OFFSET                         ((unsigned int)prvsnr_data)
+#define PRVN_NVM_PAGE_SIZE                                                 4096U
 
 /* Exported Functions Prototypes ---------------------------------------------*/
 MOBLE_RESULT AppliNvm_FlashProgram(MOBLEUINT32 offset, void const *buf, MOBLEUINT32 size);
@@ -53,12 +57,21 @@ MOBLE_RESULT AppliNvm_FactorySettingReset(void);
 //MOBLE_RESULT AppliNvm_FlashErase(uint16_t PageNumber);
 MOBLE_RESULT AppliNvm_SaveModelState(uint8_t* state, uint8_t size);
 MOBLE_RESULT AppliNvm_ClearModelState(void);
-//MOBLE_RESULT AppliNvm_LoadGenericState(uint8_t state[], uint8_t* size);
-//MOBLE_RESULT AppliNvm_LoadLightState(uint8_t state[], uint8_t* size);
 MOBLE_RESULT AppliNvm_LoadModelState(uint8_t state[], uint8_t* size);
 void AppliNvm_Process(void);
 void AppliNvm_SaveMessageParam (void);
+MOBLE_RESULT AppliNvm_FindFirstEmptyPage(MOBLEINT8* subPageIndex,MOBLEUINT32 SubPageSize,
+                                          MOBLEUINT32 totalSubPage, MOBLEUINT32 nvmBaseOffset);
+MOBLE_RESULT AppliPrvnNvm_LoadData(uint8_t state[], uint8_t* size);
+MOBLE_RESULT AppliPrvnNvm_SaveData(uint8_t* data, uint8_t size);
+MOBLEUINT32* AppliPrvnNvm_GetNodeDevKey(MOBLE_ADDRESS addrss);
+void AppliPrvnNvm_Process(void);
 
+MOBLE_RESULT AppliPrvnNvm_FactorySettingReset(MOBLEUINT8*flag);
+
+MOBLE_RESULT AppliPrvnNvm_CopyData(uint8_t state[], uint8_t* size);
+void AppliNvm_saveProvisionerDevKey(MOBLEUINT8 *data , MOBLEUINT8 size 
+                                                     , MOBLEUINT8 *prvnFlag);
 #endif /* __APPLI_NVM_H */
 
 /******************* (C) COPYRIGHT 2017 STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_sensor.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_sensor.c
index a6634a857..77074438c 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_sensor.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_sensor.c
@@ -2,7 +2,7 @@
   ******************************************************************************
   * @file    appli_sensor.c
   * @author  BLE Mesh Team
-  * @brief   Application interface for Lighting Mesh Models 
+  * @brief   Application interface for Sensor Mesh Models 
   ******************************************************************************
   * @attention
   *
@@ -30,11 +30,11 @@
 #include "common.h"
 #include "math.h"
 
-/** @addtogroup BLE_Mesh
+/** @addtogroup ST_BLE_Mesh
  *  @{
  */
 
-/** @addtogroup models_BLE
+/** @addtogroup Application_Mesh_Models
  *  @{
  */
 
@@ -88,10 +88,10 @@ extern MOBLEUINT8 ProvisionFlag;
 
 /**
 * @brief  Appli_Sensor_Cadence_Set: This function is callback for Application
-when sensor cadence Set message is received
+*         when sensor cadence Set message is received
 * @param  pCadence_param: Pointer to the parameters received for message
 * @param  property_ID: Property is of sensor coming in data packet
-* @param  length: Length of data coming in packet.
+* @param  length: Received data length.
 * @retval MOBLE_RESULT
 */ 
 MOBLE_RESULT Appli_Sensor_Cadence_Set(Sensor_CadenceParam_t* pCadence_param, MOBLEUINT16 property_ID, MOBLEUINT32 length)                                    
@@ -129,7 +129,7 @@ MOBLE_RESULT Appli_Sensor_Cadence_Set(Sensor_CadenceParam_t* pCadence_param, MOB
 
 /**
 * @brief  Appli_Sensor_Setting_Set: This function is callback for Application
-when sensor setting Set message is received
+*         when sensor setting Set message is received
 * @param  pSensor_SettingParam: Pointer to the parameters received for message
 * @param  OptionalValid: Flag to inform about the validity of optional parameters 
 * @retval MOBLE_RESULT
@@ -147,19 +147,21 @@ MOBLE_RESULT Appli_Sensor_Setting_Set(Sensor_SettingParam_t* pSensor_SettingPara
 
 /**
 * @brief  Appli_Sensor_Data_Status: This function is callback for Application
-           when sensor get message is received
+*         when sensor get message is received
 * @param  sensor_Data: Pointer to the parameters to be send in message
 * @param  pLength: Length of the parameters to be sent in response
 * @param  prop_ID: Property is of sensor coming in data packet
+* @param  length: Received data length
 * @retval MOBLE_RESULT
 */ 
 MOBLE_RESULT Appli_Sensor_Data_Status(MOBLEUINT8* sensor_Data , MOBLEUINT32* pLength, 
                                       MOBLEUINT16 prop_ID , MOBLEUINT32 length)
 {
-  MOBLE_RESULT result;                                  
+  MOBLE_RESULT result = MOBLE_RESULT_FALSE;                                  
   MOBLEUINT32 temperatureData  = 0;
   MOBLEUINT32 pressureData = 0;
   MOBLEUINT8 data_Length = 0x03;
+  MOBLEUINT32 distance = 0x000000C8; // 200 cm;
                                      
 #if 0
   LPS25HB_GetTemperature((float*)&temperatureData);
@@ -192,6 +194,17 @@ MOBLE_RESULT Appli_Sensor_Data_Status(MOBLEUINT8* sensor_Data , MOBLEUINT32* pLe
     
     *pLength  =7;    
   }
+  else if((prop_ID == TIME_OF_FLIGHT_PID) && (length > 0))
+  {
+    /* Format B for Pressure sensor */
+    *(sensor_Data+0) = ((data_Length <<1) | 0x01); 
+    *(sensor_Data+1) = (MOBLEUINT8)TIME_OF_FLIGHT_PID ;
+    *(sensor_Data+2) = (MOBLEUINT8)(TIME_OF_FLIGHT_PID >> 8);
+    
+    memcpy(&sensor_Data[3],(void*)&distance,4);
+    
+    *pLength  =7;    
+  }
   else if((result == MOBLE_RESULT_FALSE) && (length == 0))
   {
     /*(prop_Id_Temp & 0x07) << 5) | (Len <<1) Format A 
@@ -209,7 +222,14 @@ MOBLE_RESULT Appli_Sensor_Data_Status(MOBLEUINT8* sensor_Data , MOBLEUINT32* pLe
     
     memcpy(&sensor_Data[9],(void*)&pressureData,4);
     
-    *pLength  =13;    
+    /* Format B for Pressure sensor */
+    *(sensor_Data+13) = ((data_Length <<1) | 0x01); 
+    *(sensor_Data+14) = (MOBLEUINT8)TIME_OF_FLIGHT_PID ;
+    *(sensor_Data+15) = (MOBLEUINT8)(TIME_OF_FLIGHT_PID >> 8);
+    
+    memcpy(&sensor_Data[16],(void*)&distance,4);
+    
+    *pLength  =20;    
   }  
   else
   {
@@ -225,7 +245,7 @@ MOBLE_RESULT Appli_Sensor_Data_Status(MOBLEUINT8* sensor_Data , MOBLEUINT32* pLe
                                     
 /**
 * @brief  Appli_Sensor_Descriptor_Status: This function is callback for Application
-when sensor descriptor get message is received
+*         when sensor get message is received
 * @param  sensor_Descriptor: Pointer to the parameters to be send in message
 * @param  pLength: Length of the parameters to be sent in response
 * @retval MOBLE_RESULT
@@ -233,7 +253,8 @@ when sensor descriptor get message is received
 MOBLE_RESULT Appli_Sensor_Descriptor_Status(MOBLEUINT8* sensor_Descriptor , MOBLEUINT32* pLength)
 {
   Appli_Sensor_DescriptorStatus_t Appli_Sensor_DescriptorStatus1[] = {{PRESSURE_PID,0xABC,0xDEF,0x03,0x04,0x05},
-                                                                       {TEMPERATURE_PID,0xc56,0xd78,0x06,0x07,0x08}};
+                                                                       {TEMPERATURE_PID,0xc56,0xd78,0x06,0x07,0x08},
+                                                                        {TIME_OF_FLIGHT_PID,0xD23,0xE45,0x06,0x07,0x08}};
     MOBLEUINT32 tolerance;
     tolerance = Appli_Sensor_DescriptorStatus1[0].NegativeTolerance;
     tolerance = (tolerance << 12 ) | Appli_Sensor_DescriptorStatus1[0].PositiveTolerance;
@@ -259,7 +280,19 @@ MOBLE_RESULT Appli_Sensor_Descriptor_Status(MOBLEUINT8* sensor_Descriptor , MOBL
   *(sensor_Descriptor+14) = Appli_Sensor_DescriptorStatus1[1].MeasurementPeriod;
   *(sensor_Descriptor+15) = Appli_Sensor_DescriptorStatus1[1].UpdateInterval;
   
-  *pLength = 18;
+   tolerance = Appli_Sensor_DescriptorStatus1[2].NegativeTolerance;
+   tolerance = (tolerance << 12 ) | Appli_Sensor_DescriptorStatus1[2].PositiveTolerance ;
+    
+  *(sensor_Descriptor+16) = Appli_Sensor_DescriptorStatus1[2].Prop_ID;
+  *(sensor_Descriptor+17) = Appli_Sensor_DescriptorStatus1[2].Prop_ID >> 8;
+  *(sensor_Descriptor+18) = tolerance;
+  *(sensor_Descriptor+19) = tolerance >> 8;
+  *(sensor_Descriptor+20) = tolerance >> 16;
+  *(sensor_Descriptor+21) = Appli_Sensor_DescriptorStatus1[2].SamplingFunction;
+  *(sensor_Descriptor+22) = Appli_Sensor_DescriptorStatus1[2].MeasurementPeriod;
+  *(sensor_Descriptor+23) = Appli_Sensor_DescriptorStatus1[2].UpdateInterval;
+  
+  *pLength = 24;
   
   return MOBLE_RESULT_SUCCESS;
 }
@@ -267,9 +300,9 @@ MOBLE_RESULT Appli_Sensor_Descriptor_Status(MOBLEUINT8* sensor_Descriptor , MOBL
 #endif
 
 /**
-* @brief  Sensor Process function
-* @param  Function will continuously monitor the sensors.
-Function used for the Publishing, data monitoring..
+* @brief  Sensor Process Function will continuously monitor the sensors.
+*         Function used for the Publishing, data monitoring..
+* @param  void
 * @retval void
 */ 
 void Sensor_Process(void)
@@ -284,16 +317,24 @@ void Sensor_Process(void)
   }
 #endif
   
-/* Occupancy_Flag become True when ever sensor detect occupancy and get interrupt
-   and make flag True to run this routine.
-*/ 
+  /* Occupancy_Flag become True when ever sensor detect occupancy and get interrupt
+     and make flag True to run this routine.
+  */ 
   if(Occupancy_Flag == MOBLE_TRUE) 
   {
     if(BLE_waitPeriod(CONTROLLER_WAIT_TIME))
     {
-/* publishing the command for LC Light occupancy set message in the sensor status 
-   message .
-*/     
+#ifdef ENABLE_SENSOR_PUBLICATION    
+      if(ProvisionFlag == 1)
+      {
+        Read_Sensor_Data(&sensorValue[0]);
+        Sensor_Publication_Process(&sensorValue[0], &Property_ID_Table[0]);
+      }
+#endif
+  
+      /* publishing the command for LC Light occupancy set message in the sensor status 
+         message .
+      */     
       Sensor_LC_Light_Publish();  
       Occupancy_Flag = MOBLE_FALSE;   
     }  
@@ -308,22 +349,26 @@ void Sensor_Process(void)
 */  
 void Sensor_LC_Light_Publish(void)
 {
-  MOBLE_ADDRESS publishAddress;
-  MOBLEUINT8 elementNumber;
   MOBLEUINT8 occupancyData = 0x1;
   MOBLEUINT8 sensor_Data[5];
+  MOBLE_ADDRESS srcAdd;
+  MOBLE_RESULT result = MOBLE_RESULT_SUCCESS;
   
-  sensor_Data[1] = (MOBLEUINT8)(LIGHT_CONTROL_LIGHTNESS_ON_ID << 8);
-  sensor_Data[0] = (MOBLEUINT8)LIGHT_CONTROL_LIGHTNESS_ON_ID;
+  sensor_Data[1] = (MOBLEUINT8)(PRESENCE_DETECTED_PROPERTY << 8);
+  sensor_Data[0] = (MOBLEUINT8)PRESENCE_DETECTED_PROPERTY;
   sensor_Data[2] = occupancyData;
   
-  elementNumber = BLE_GetElementNumber();
-  publishAddress = BLEMesh_GetPublishAddress(elementNumber); 
+  srcAdd = BLEMesh_GetAddress();
   
-  BLEMesh_SetRemoteData(publishAddress, 0,
-                        SENSOR_STATUS , 
-                        sensor_Data,3,
-                        MOBLE_FALSE, MOBLE_FALSE);
+  result = BLEMesh_SetRemotePublication(LIGHT_MODEL_SERVER_LC_MODEL_ID, srcAdd ,
+                                        SENSOR_STATUS , 
+                                        sensor_Data,3,
+                                        MOBLE_FALSE, MOBLE_FALSE);
+   
+  if(result)
+  {
+    TRACE_M(TF_LIGHT_LC,"Publication Error \r\n");
+  }
    
 }
 
@@ -362,80 +407,80 @@ void Sensor_Publication_Process(float* pSensorData, MODEL_Property_IDTableParam_
   static float previousDataValue[NUMBER_OF_SENSOR];
   static PublishingDataFlag_t PublishingDataFlag[NUMBER_OF_SENSOR] = {MOBLE_FALSE};
   
-      floatToInt(pSensorData[sensor_Count], &out_value, 2);
-      
-      /* Taking the timestamp for the cadence publication and making flag high */
-      if(PublishingDataFlag[sensor_Count].CadenceDurationFlag == MOBLE_FALSE)
-      {
-        cadenceDurationTick[sensor_Count] = Clock_Time();
-        PublishingDataFlag[sensor_Count].CadenceDurationFlag = MOBLE_TRUE;          
-      }
-      /* Taking the sensor value and store it for comparing present sensor value with
-      particular difference of increasing or decreasing. and making flag high.
-      */
-      if(PublishingDataFlag[sensor_Count].DeltaDataFlag == MOBLE_FALSE)
-      {
-        previousDataValue[sensor_Count] = pSensorData[sensor_Count];
-        PublishingDataFlag[sensor_Count].DeltaDataFlag = MOBLE_TRUE;
-      }
-      /*
-      This condition is checking for the difference of present sensor value 
-      with prestored sensor value with user defined difference,if this condition 
-      is true then it publish the sensor data.And making the delta flag low again.
-      */       
-      if((pSensorData[sensor_Count] >= (previousDataValue[sensor_Count] + Sensor_CadenceSet[sensor_Count].triggerDeltaUp)) ||
-         (pSensorData[sensor_Count] <= (previousDataValue[sensor_Count] - Sensor_CadenceSet[sensor_Count].triggerDeltaDown)))
-      {        
+  floatToInt(pSensorData[sensor_Count], &out_value, 2);
+  
+  /* Taking the timestamp for the cadence publication and making flag high */
+  if(PublishingDataFlag[sensor_Count].CadenceDurationFlag == MOBLE_FALSE)
+  {
+    cadenceDurationTick[sensor_Count] = Clock_Time();
+    PublishingDataFlag[sensor_Count].CadenceDurationFlag = MOBLE_TRUE;          
+  }
+  /* Taking the sensor value and store it for comparing present sensor value with
+  particular difference of increasing or decreasing. and making flag high.
+  */
+  if(PublishingDataFlag[sensor_Count].DeltaDataFlag == MOBLE_FALSE)
+  {
+    previousDataValue[sensor_Count] = pSensorData[sensor_Count];
+    PublishingDataFlag[sensor_Count].DeltaDataFlag = MOBLE_TRUE;
+  }
+  /*
+  This condition is checking for the difference of present sensor value 
+  with prestored sensor value with user defined difference,if this condition 
+  is true then it publish the sensor data.And making the delta flag low again.
+  */       
+  if((pSensorData[sensor_Count] >= (previousDataValue[sensor_Count] + Sensor_CadenceSet[sensor_Count].triggerDeltaUp)) ||
+     (pSensorData[sensor_Count] <= (previousDataValue[sensor_Count] - Sensor_CadenceSet[sensor_Count].triggerDeltaDown)))
+  {        
     MOBLEUINT16 prop_id = pProp_ID[sensor_Count].Property_ID;
     
     SensorDataPublish((MOBLEUINT32*)&pSensorData[sensor_Count] , &prop_id);
         
-        PublishingDataFlag[sensor_Count].DeltaDataFlag = MOBLE_FALSE;
-        TRACE_M(TF_SENSOR,"previous value data %.3f \r\n",previousDataValue[sensor_Count]);
-        TRACE_M(TF_SENSOR,"Delta publication of data %.3f\r\n",*((float*)&pSensorData[sensor_Count]));
-        sensor_Count++;
-      }
-      /*
-      This condition is continuously checking the sensor value range, if that 
-      value is within the user defined range then publishing duration or rate will
-      be divided by user definedcadence devisor value and rate of publishing will 
-      become high.And making the cadence flag low again.
-      */
-      if(((out_value.out_int <= Sensor_CadenceSet[sensor_Count].FastCadenceHigh) && 
-          (out_value.out_int >= Sensor_CadenceSet[sensor_Count].FastCadenceLow)) ||
-         (Sensor_CadenceSet[sensor_Count].FastCadenceHigh < Sensor_CadenceSet[sensor_Count].FastCadenceLow))
-      {
-        devisorValue = (MOBLEUINT8)pow(2 ,Sensor_CadenceSet[sensor_Count].FastCadenceDevisor);
-        publishTime = SENSOR_PUBLISH_PERIOD/devisorValue;  
-        
-        if(((Clock_Time()- cadenceDurationTick[sensor_Count]) >= publishTime))
-        {                   
-      MOBLEUINT16 prop_id = pProp_ID[sensor_Count].Property_ID;
+    PublishingDataFlag[sensor_Count].DeltaDataFlag = MOBLE_FALSE;
+    TRACE_M(TF_SENSOR,"previous value data %.3f \r\n",previousDataValue[sensor_Count]);
+    TRACE_M(TF_SENSOR,"Delta publication of data %.3f\r\n",*((float*)&pSensorData[sensor_Count]));
+    sensor_Count++;
+  }
+  /*
+  This condition is continuously checking the sensor value range, if that 
+  value is within the user defined range then publishing duration or rate will
+  be divided by user definedcadence devisor value and rate of publishing will 
+  become high.And making the cadence flag low again.
+  */
+  if(((out_value.out_int <= Sensor_CadenceSet[sensor_Count].FastCadenceHigh) && 
+      (out_value.out_int >= Sensor_CadenceSet[sensor_Count].FastCadenceLow)) ||
+     (Sensor_CadenceSet[sensor_Count].FastCadenceHigh < Sensor_CadenceSet[sensor_Count].FastCadenceLow))
+  {
+    devisorValue = (MOBLEUINT8)pow(2 ,Sensor_CadenceSet[sensor_Count].FastCadenceDevisor);
+    publishTime = SENSOR_PUBLISH_PERIOD/devisorValue;  
     
-      SensorDataPublish((MOBLEUINT32*)&pSensorData[sensor_Count] , &prop_id);                 
-          PublishingDataFlag[sensor_Count].CadenceDurationFlag = MOBLE_FALSE;           
-          TRACE_M(TF_SENSOR,"Cadence publication of data %.2f \r\n",*((float*)&pSensorData[sensor_Count])); 
-          sensor_Count++;
-        } 
-      }
-      else
-      {
-        publishTime = SENSOR_PUBLISH_PERIOD ;     
-        
-        if(((Clock_Time()- cadenceDurationTick[sensor_Count]) >= SENSOR_PUBLISH_PERIOD))
-        {            
+    if(((Clock_Time()- cadenceDurationTick[sensor_Count]) >= publishTime))
+    {                   
       MOBLEUINT16 prop_id = pProp_ID[sensor_Count].Property_ID;
+
+      SensorDataPublish((MOBLEUINT32*)&pSensorData[sensor_Count] , &prop_id);                 
+      PublishingDataFlag[sensor_Count].CadenceDurationFlag = MOBLE_FALSE;           
+      TRACE_M(TF_SENSOR,"Cadence publication of data %.2f \r\n",*((float*)&pSensorData[sensor_Count])); 
+      sensor_Count++;
+    } 
+  }
+  else
+  {
+    publishTime = SENSOR_PUBLISH_PERIOD ;     
     
+    if(((Clock_Time()- cadenceDurationTick[sensor_Count]) >= SENSOR_PUBLISH_PERIOD))
+    {            
+      MOBLEUINT16 prop_id = pProp_ID[sensor_Count].Property_ID;
+
       SensorDataPublish((MOBLEUINT32*)&pSensorData[sensor_Count] , &prop_id);
-          
-          PublishingDataFlag[sensor_Count].CadenceDurationFlag = MOBLE_FALSE;                
-          TRACE_M(TF_SENSOR,"Regular publication of data %.3f \r\n",*((float*)&pSensorData[sensor_Count]));
-        }  
-      } 
-     if(sensor_Count > 1)
-     {
-       sensor_Count = 0;
-     }
+      
+      PublishingDataFlag[sensor_Count].CadenceDurationFlag = MOBLE_FALSE;                
+      TRACE_M(TF_SENSOR,"Regular publication of data %.3f \r\n",*((float*)&pSensorData[sensor_Count]));
+    }  
+  } 
+ if(sensor_Count > 1)
+ {
+   sensor_Count = 0;
+ }
 
 }
 
@@ -448,27 +493,12 @@ void Sensor_Publication_Process(float* pSensorData, MODEL_Property_IDTableParam_
 */
 void SensorDataPublish(MOBLEUINT32 *pSensor_Value , MOBLEUINT16* pProp_ID)
 {
-  MOBLE_ADDRESS publishAddress;
-  MOBLEUINT8 elementNumber = 0;
-  MOBLEUINT32 length = 0;
+  MOBLEUINT32 length;
   MOBLEUINT8 sensor_Data[8];
+  MOBLE_ADDRESS srcAdd;
+  MOBLE_RESULT result = MOBLE_RESULT_SUCCESS;
   
-  /*Select the Element Number for which publication address is required*/
-  
-  if(NumberOfElements == 1)
-  {
-    elementNumber = 0x01; 
-  }  
-  else if(NumberOfElements == 2)
-  { 
-    elementNumber = 0x02; /*Element 2 is configured as switch*/
-  } 
-  else if(NumberOfElements == 3)
-  {
-    elementNumber = 0x03; /*Element 3 is configured as switch*/
-  }
-  
-  publishAddress = BLEMesh_GetPublishAddress(elementNumber); 
+  srcAdd = BLEMesh_GetAddress();
   
   switch(*pProp_ID)
   {
@@ -499,10 +529,15 @@ void SensorDataPublish(MOBLEUINT32 *pSensor_Value , MOBLEUINT16* pProp_ID)
     break;
   }
   
-  BLEMesh_SetRemoteData(publishAddress, 0,
-                            SENSOR_STATUS , 
-                            sensor_Data,length,
-                            MOBLE_FALSE, MOBLE_FALSE);
+  result = BLEMesh_SetRemotePublication(SENSOR_SERVER_MODEL_ID, srcAdd,
+                                        SENSOR_STATUS , 
+                                        sensor_Data,length,
+                                        MOBLE_FALSE, MOBLE_FALSE);
+  
+  if(result)
+  {
+    TRACE_M(TF_SENSOR,"Publication Error \r\n");
+  }
   
 }
 
@@ -511,7 +546,7 @@ void SensorDataPublish(MOBLEUINT32 *pSensor_Value , MOBLEUINT16* pProp_ID)
 #ifdef ENABLE_SENSOR_MODEL_SERVER
 /**
 * @brief  Appli_Sensor_GetSettingStatus: This function is callback for Application
-when sensor setting numbers status message is to be provided
+*         when sensor setting numbers status message is to be provided
 * @param  pSetting_Status: Pointer to the status message
 * @retval MOBLE_RESULT
 */ 
@@ -528,7 +563,7 @@ MOBLE_RESULT Appli_Sensor_GetSettingStatus(MOBLEUINT8* pSetting_Status)
 
 /**
 * @brief  Appli_Sensor_GetSetting_IDStatus: This function is callback for Application
-when sensor setting numbers and row value status message is to be provided
+*         when sensor setting numbers and row value status message is to be provided
 * @param  pSetting_Status: Pointer to the status message
 * @retval MOBLE_RESULT
 */ 
@@ -550,7 +585,7 @@ MOBLE_RESULT Appli_Sensor_GetSetting_IDStatus(MOBLEUINT8* pSetting_Status)
 
 /**
 * @brief  Check_Property_ID: This function is used for checking the Property id 
-of sensor available in table.
+*         of sensor available in table.
 * @param  prop_ID_Table: address of the property id table array.
 * @param  prop_ID:received property id of sensor.
 * @retval MOBLE_RESULT
@@ -558,23 +593,23 @@ of sensor available in table.
 MOBLE_RESULT Check_Property_ID(const MODEL_Property_IDTableParam_t prop_ID_Table[] 
                                , MOBLEUINT16 prop_ID)
 {
+   MOBLE_RESULT status = MOBLE_RESULT_FALSE;
   
   for(int i=0;i sizeof(ResponseBuffer))
+      {
+        length = sizeof(ResponseBuffer);
+        TRACE_M(TF_VENDOR,"Length received greater than size of response buffer \r\n");
+      }
+      memcpy (&(ResponseBuffer[1]),&(data[1]),(length-1));
       BuffLength = length;
       break;
     }
@@ -213,7 +236,7 @@ MOBLE_RESULT Appli_Vendor_Test(MOBLEUINT8 const *data, MOBLEUINT32 length)
       }                                                    
               
       TestHitCounter++;              
-      TRACE_M(TF_VENDOR,"Command received Count %.2x \r\n",TestHitCounter);
+      TRACE_M(TF_VENDOR,"Command received Count %.2lx \r\n",TestHitCounter);
       ResponseBuffer[0] = subCmd;
       ResponseBuffer[1] = Appli_LedState ;
       BuffLength = 2;
@@ -222,9 +245,14 @@ MOBLE_RESULT Appli_Vendor_Test(MOBLEUINT8 const *data, MOBLEUINT32 length)
     }
   case APPLI_MODEL_PUBLISH_SELECT:
     {
-                
-      break;
-    }
+       for (MOBLEUINT8 idx=0; idx 1))
+        if(Appli_LedState == 1)
         {
           Appli_LightPwmValue.IntensityValue = LED_OFF_VALUE;
-          Light_UpdateLedValue(LOAD_STATE , Appli_LightPwmValue);
+                                    
+#ifndef CUSTOM_BOARD_PWM_SELECTION            
+            Light_UpdateLedValue(LOAD_STATE , Appli_LightPwmValue);   /* PWM_ID = PWM4, mapped on PWM4_PIN (GPIO_14 in mapping) */
+#else
+          Light_UpdateLedValue(RESET_STATE , Appli_LightPwmValue);   /* PWM_ID = PWM4, mapped on PWM4_PIN (GPIO_14 in mapping) */
+#endif            
+          Appli_LedState = 0;
           BSP_LED_Off(LED_BLUE);
         }
         else
         {
           Appli_LightPwmValue.IntensityValue = PWM_TIME_PERIOD;
           Light_UpdateLedValue(LOAD_STATE , Appli_LightPwmValue);
+          Appli_LedState = 1;
           BSP_LED_On(LED_BLUE);
         }
               
@@ -335,7 +371,12 @@ MOBLE_RESULT Appli_Vendor_LEDControl( MOBLEUINT8 const *data, MOBLEUINT32 length
       if(elementNumber == FIRST_ELEMENT)
       {
         Appli_LightPwmValue.IntensityValue = LED_OFF_VALUE;
+            
+#ifndef CUSTOM_BOARD_PWM_SELECTION            
         Light_UpdateLedValue(LOAD_STATE , Appli_LightPwmValue);   /* PWM_ID = PWM4, mapped on PWM4_PIN (GPIO_14 in mapping) */
+#else
+            Light_UpdateLedValue(RESET_STATE , Appli_LightPwmValue);   /* PWM_ID = PWM4, mapped on PWM4_PIN (GPIO_14 in mapping) */
+#endif            
         Appli_LedState = 0;
         BSP_LED_Off(LED_BLUE);
       }
@@ -408,6 +449,42 @@ MOBLE_RESULT Appli_Vendor_LEDControl( MOBLEUINT8 const *data, MOBLEUINT32 length
   return status;
 }
 
+/**
+* @brief  Process the Vendor Data write Command 
+* @param  data: Pointer to the data received from peer_addr
+* @param  length: Length of the data
+* @retval MOBLE_RESULT status of result
+*/          
+MOBLE_RESULT Appli_Vendor_Data_write(MOBLEUINT8 const *data, MOBLEUINT32 length)
+{
+       MOBLE_RESULT status = MOBLE_RESULT_SUCCESS;  
+       MOBLEUINT8 subCmd = data[0];
+       /*First Byte is sending the Sub Command*/      
+       ResponseBuffer[0]=subCmd;
+       TRACE_M(TF_VENDOR_COMMAND,"#0E-%02hx! \n\r",data[0]);
+       switch(subCmd)
+       {     
+         case APPLI_STRING_WRITE:
+           {            
+             memcpy(&ResponseBuffer,data,length);
+             BuffLength = length;
+             break;
+           }
+         default:
+          {
+            status = MOBLE_RESULT_FALSE;
+            break;
+          }
+       }
+      return status;        
+}
+         
+/**
+* @brief  Appli_GetTestValue: This function is callback for Application
+*          when Vensor application test command received then status message is to be provided
+* @param  responseValue: Pointer to the status message
+* @retval void
+*/ 
 void Appli_GetTestValue (MOBLEUINT8 *responseValue)
 {
   *responseValue = TestHitCounter;
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_vendor.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_vendor.h
index 3efba69ed..2b9390099 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_vendor.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/appli_vendor.h
@@ -34,6 +34,7 @@ MOBLE_RESULT Appli_Vendor_LEDControl( MOBLEUINT8 const *data, MOBLEUINT32 length
                                        MOBLEUINT8 elementNumber, MOBLE_ADDRESS dst_peer);
 MOBLE_RESULT Appli_Vendor_DeviceInfo(MOBLEUINT8 const *data, MOBLEUINT32 length);
 MOBLE_RESULT Appli_Vendor_Test(MOBLEUINT8 const *data, MOBLEUINT32 length);
+MOBLE_RESULT Appli_Vendor_Data_write(MOBLEUINT8 const *data, MOBLEUINT32 length);
 void Appli_GetTestValue (MOBLEUINT8 *responseValue);
 
 #endif /* __APPLI_VENDOR_H */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/mesh_cfg.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/mesh_cfg.h
index 6c7fa7965..393ef19a1 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/mesh_cfg.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/mesh_cfg.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    mesh_cfg.h
   * @author  BLE Mesh Team
-  * @version V1.09.000
-  * @date    15-Oct-2018
+* @version V1.12.000
+* @date    06-12-2019
   * @brief   Header file for mesh_usr_cfg.c 
   ******************************************************************************
   * @attention
@@ -121,6 +121,12 @@ void TraceHeader(const char* func_name, int mode);
 #define LOW_POWER_FEATURE 0
 #endif
 
+#ifdef ENABLE_PROVISIONER_FEATURE
+#define PROVISIONER_FEATURE 1
+#else
+#define PROVISIONER_FEATURE 0
+#endif
+
 #if (LOW_POWER_FEATURE && RELAY_FEATURE)
 #error "Low power node can't be relay node"
 #elif (LOW_POWER_FEATURE && PROXY_FEATURE)
@@ -151,15 +157,6 @@ void TraceHeader(const char* func_name, int mode);
   LPN_NO_OF_RETRIES                      \
 }
 
-/*
-*  If PB-GATT and Proxy not supported, optimize related to GATT database not required
-*/
-#if  (PB_GATT_SUPPORTED == 0 && PROXY_FEATURE == 0)
-#define BLUENRG_MESH_GATT_REQ               0
-#else
-#define BLUENRG_MESH_GATT_REQ               1
-#endif
-
 #define UNPROV_NODE_INFO_PARAMS          \
 {                                        \
     PUB_KEY_TYPE_OOB,                    \
@@ -216,7 +213,7 @@ void TraceHeader(const char* func_name, int mode);
 #elif LOW_POWER_FEATURE
 #define FRIEND_BUFF_DYNAMIC_MEMORY_SIZE    112U
 #else
-#define FRIEND_BUFF_DYNAMIC_MEMORY_SIZE    1U
+#define FRIEND_BUFF_DYNAMIC_MEMORY_SIZE    4U
 #endif
 
 #define DYNAMIC_MEMORY_SIZE                4096U
@@ -235,15 +232,6 @@ void TraceHeader(const char* func_name, int mode);
 #define SdkEvalComIOUartIrqHandler         UART_Handler /* Added Interrupt handler for Uart */
 /******************** Serial Interface Handling Control **********************/
 
-/* Note: Please use Full Library configuration in project options to use the full 
-         configuration of the C/C++ runtime library for printf and scanf functionality */
-
-/* Enables the serial interface using Uart */
-#define ENABLE_SERIAL_INTERFACE            1    
-#define ENABLE_UT                          0
-#define ENABLE_SERIAL_CONTROL              1
-#define ENABLE_APPLI_TEST                  0
-
 /* Exported variables  ------------------------------------------------------- */
 extern const DynBufferParam_t DynBufferParam;
 extern const tr_params_t TrParams;
@@ -253,5 +241,6 @@ extern const prvn_params_t PrvnParams;
 extern const neighbor_table_init_params_t NeighborTableParams;
 
 /* Exported Functions Prototypes ---------------------------------------------*/
+MOBLEUINT8 ApplicationSetNodeSigModelList(void);
 
 #endif /* __MESH_CFG_H */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/mesh_cfg_usr.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/mesh_cfg_usr.h
index 4aa2505a9..c230c60e0 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/mesh_cfg_usr.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/mesh_cfg_usr.h
@@ -2,8 +2,8 @@
 ******************************************************************************
 * @file    mesh_cfg_usr.h
 * @author  BLE Mesh Team
-* @version V1.10.000
-* @date    15-Jan-2019
+* @version V1.12.000
+* @date    06-12-2019
 * @brief   Header file for mesh_usr_cfg.c 
 ******************************************************************************
 * @attention
@@ -64,39 +64,53 @@ Either use 0 to disable or 1 to enable
 @  TF_MISC is responsible for the other type traces.
 
 */
-#define TF_GENERIC                                                             1
-#define TF_LIGHT                                                               1
-#define TF_LIGHT_LC                                                            1
-#define TF_SENSOR                                                              1
+#define TF_GENERIC                                                             0
+#define TF_LIGHT                                                               0
+#define TF_LIGHT_LC                                                            0
+#define TF_SENSOR                                                              0
 #define TF_VENDOR                                                              0
+#define TF_COMMON                                                              0
+#define TF_VENDOR_COMMAND                                                      0
 #define TF_NEIGHBOUR                                                           0
 #define TF_LPN_FRND                                                            0
 #define TF_ELEMENTS                                                            0
 #define TF_ADDRESS                                                             0
 #define TF_PROVISION                                                           1
 #define TF_HANDLER                                                             0
-#define TF_INIT                                                                0
-#define TF_MISC                                                                0
+#define TF_INIT                                                                1
+#define TF_MISC                                                                1
+#define TF_MEMORY                                                              0
 #define TF_SERIAL_CTRL                                                         1
+#define TF_BEACON                                                              0
+#define TF_GENERIC_CLIENT                                                      1
+#define TF_LIGHT_CLIENT                                                        1
+#define TF_CONFIG_CLIENT                                                       1
+#define TF_LIGHT_CLIENT                                                        1
 
 /*******************************************************************************
 *** Following section helps to select right configuration of Models  ***********
 *******************************************************************************/
 /******* Define the following Macros to enable the usage of the  Models  ******/
 
+#ifdef CLIENT
+#define ENABLE_GENERIC_MODEL_SERVER_ONOFF 
+#endif
+
+#ifdef SERVER
 /* Define the following Macros to enable the usage of the Server Generic Models  */
 #define ENABLE_GENERIC_MODEL_SERVER_ONOFF 
 #define ENABLE_GENERIC_MODEL_SERVER_LEVEL
-#define ENABLE_GENERIC_MODEL_SERVER_POWER_ONOFF
-#define ENABLE_GENERIC_MODEL_SERVER_POWER_ONOFF_SETUP
+//#define ENABLE_GENERIC_MODEL_SERVER_POWER_ONOFF
+//#define ENABLE_GENERIC_MODEL_SERVER_POWER_ONOFF_SETUP
 //#define ENABLE_GENERIC_MODEL_SERVER_DEFAULT_TRANSITION_TIME
 
 /* The Following Models are not available in this version, will be developed in 
    next version.
 */
+
+//#define ENABLE_GENERIC_MODEL_SERVER_POWER_LEVEL
+//#define ENABLE_GENERIC_MODEL_SERVER_POWER_LEVEL_SETUP
 /*
-#define ENABLE_GENERIC_MODEL_SERVER_POWER_LEVEL
-#define ENABLE_GENERIC_MODEL_SERVER_POWER_LEVEL_SETUP
 #define ENABLE_GENERIC_MODEL_SERVER_BATTERY
 #define ENABLE_GENERIC_MODEL_SERVER_LOCATION
 #define ENABLE_GENERIC_MODEL_SERVER_LOCATION_SETUP
@@ -104,12 +118,7 @@ Either use 0 to disable or 1 to enable
 #define ENABLE_GENERIC_MODEL_SERVER_MANUFACTURER_PROPERTY
 #define ENABLE_GENERIC_MODEL_SERVER_USER_PROPERTY
 #define ENABLE_GENERIC_MODEL_SERVER_CLIENT_PROPERTY
-*/
 
-/* Define the following Macros to enable the usage of the Client Generic Models  */
-/*
-#define ENABLE_GENERIC_MODEL_CLIENT_ONOFF 
-#define ENABLE_GENERIC_MODEL_CLIENT_LEVEL
 */
 
 /******************************************************************************/
@@ -118,19 +127,35 @@ Either use 0 to disable or 1 to enable
 
 #define ENABLE_LIGHT_MODEL_SERVER_LIGHTNESS
 #define ENABLE_LIGHT_MODEL_SERVER_LIGHTNESS_SETUP 
-#define ENABLE_LIGHT_MODEL_SERVER_CTL
-#define ENABLE_LIGHT_MODEL_SERVER_CTL_SETUP 
-#define ENABLE_LIGHT_MODEL_SERVER_CTL_TEMPERATURE
-#define ENABLE_LIGHT_MODEL_SERVER_HSL 
-#define ENABLE_LIGHT_MODEL_SERVER_HSL_SETUP  
-#define ENABLE_LIGHT_MODEL_SERVER_HSL_HUE 
-#define ENABLE_LIGHT_MODEL_SERVER_HSL_SATURATION 
+//#define ENABLE_LIGHT_MODEL_SERVER_CTL
+//#define ENABLE_LIGHT_MODEL_SERVER_CTL_SETUP 
+//#define ENABLE_LIGHT_MODEL_SERVER_CTL_TEMPERATURE
+//#define ENABLE_LIGHT_MODEL_SERVER_HSL 
+//#define ENABLE_LIGHT_MODEL_SERVER_HSL_SETUP  
+//#define ENABLE_LIGHT_MODEL_SERVER_HSL_HUE 
+//#define ENABLE_LIGHT_MODEL_SERVER_HSL_SATURATION 
 
 /* 
    The following Models are managed in different file light_lc.c in middleware
 */
-#define ENABLE_LIGHT_MODEL_SERVER_LC 
-#define ENABLE_LIGHT_MODEL_SERVER_LC_SETUP 
+//#define ENABLE_LIGHT_MODEL_SERVER_LC 
+//#define ENABLE_LIGHT_MODEL_SERVER_LC_SETUP 
+
+/******************************************************************************/
+/* Define the following Macros to enable the usage of the Sensor Models  */
+/******************************************************************************/
+
+//#define ENABLE_SENSOR_MODEL_SERVER
+//#define ENABLE_SENSOR_MODEL_SERVER_SETUP
+
+/******************************************************************************/
+/* Define the following Macros to enable the usage of the time and scene Models */
+/******************************************************************************/
+
+//#define ENABLE_TIME_MODEL_SERVER
+//#define ENABLE_TIME_MODEL_SERVER_SETUP
+//#define ENABLE_SCENE_MODEL_SERVER
+//#define ENABLE_SCENE_MODEL_SERVER_SETUP
 
 /* 
    The Following Models are not available in this version
@@ -138,29 +163,42 @@ Either use 0 to disable or 1 to enable
 //#define ENABLE_LIGHT_MODEL_SERVER_XYL 
 //#define ENABLE_LIGHT_MODEL_SERVER_XYL_SETUP 
 
-
-/* Following Macro helps to know if the Fixed functions are needed or not 
-   DO NOT change or add any space at the end of the file */
-#if defined(ENABLE_LIGHT_MODEL_SERVER_LIGHTNESS) \
-    || defined(ENABLE_LIGHT_MODEL_SERVER_LIGHTNESS_SETUP) \
-    || defined(ENABLE_LIGHT_MODEL_SERVER_CTL) \
-    || defined(ENABLE_LIGHT_MODEL_SERVER_CTL_SETUP) \
-    || defined(ENABLE_LIGHT_MODEL_SERVER_CTL_TEMPERATURE) \
-    || defined(ENABLE_LIGHT_MODEL_SERVER_HSL) \
-    || defined(ENABLE_LIGHT_MODEL_SERVER_HSL_SETUP) \
-    || defined(ENABLE_LIGHT_MODEL_SERVER_HSL_HUE) \
-    || defined(ENABLE_LIGHT_MODEL_SERVER_HSL_SATURATION) \
-    || defined(ENABLE_LIGHT_MODEL_SERVER_LC) \
-    || defined(ENABLE_LIGHT_MODEL_SERVER_LC_SETUP) \
-    || defined(ENABLE_LIGHT_MODEL_SERVER_XYL) \
-    || defined(ENABLE_LIGHT_MODEL_SERVER_XYL_SETUP)
-  #define  ENABLE_LIGHT_MODEL_SERVER  
+/******* Define the following Macros to enable the vendor model  ******/
+//#define ENABLE_VENDOR_MODEL_SERVER  
+#define GENERIC_SERVER_MODEL_PUBLISH  
 #endif
+
+#ifdef CLIENT
+/* Define the following Macros to enable the usage of the Client Generic Models  */
+#define ENABLE_GENERIC_MODEL_CLIENT_ONOFF 
+#define ENABLE_GENERIC_MODEL_CLIENT_LEVEL
+#define ENABLE_LIGHT_MODEL_CLIENT_LIGHTNESS
+#define ENABLE_CONFIG_MODEL_CLIENT
+
+/******************************************************************************/
+/*
+Define the Macro for enabling/disabling the Publishing with Generic on off
+or by Vendor Model.
+@ define Macro for Vendor Publishing
+@ Undefine or comment Macro for Generic On Off Publishing
+*/
+//#define VENDOR_CLIENT_MODEL_PUBLISH
+#define GENERIC_CLIENT_MODEL_PUBLISH  
+//#define LIGHT_CLIENT_MODEL_PUBLISH
+ 
+#if defined (ENABLE_GENERIC_MODEL_CLIENT_ONOFF) \
+    || defined (ENABLE_GENERIC_MODEL_CLIENT_LEVEL) 
       
-#if defined(ENABLE_LIGHT_MODEL_SERVER_LC) \
-    || defined(ENABLE_LIGHT_MODEL_SERVER_LC_SETUP)
-   #define  ENABLE_LIGHT_LC_MODEL_SERVER  
+ #define ENABLE_GENERIC_MODEL_CLIENT
+#endif
+
+#if defined (ENABLE_LIGHT_MODEL_CLIENT_LIGHTNESS) 
+         
+ #define ENABLE_LIGHT_MODEL_CLIENT
 #endif      
+      
+#endif
+
 /******************************************************************************/
 /*
 Define the Macros for Enabling/disabling the binding of data between the Generic 
@@ -171,61 +209,15 @@ and Light model.
 /******************************************************************************/
 //#define ENABLE_MODEL_BINDING
 
-
-/******************************************************************************/
-/* Define the following Macros to enable the usage of the Sensor Models  */
-/******************************************************************************/
-
-#define ENABLE_SENSOR_MODEL_SERVER
-#define ENABLE_SENSOR_MODEL_SERVER_SETUP
-
 /* Define the macros for the numbers of sensor present.*/
 #define NUMBER_OF_SENSOR                   2
-#define ENABLE_OCCUPANCY_SENSOR
+//#define ENABLE_OCCUPANCY_SENSOR
 /*
 Macro is responsible for enabling and desabling the sensor publication.
 Comment this macro to disable the publication
 */
 //#define ENABLE_SENSOR_PUBLICATION
 
-/******************************************************************************/
-/* Define the following Macros to enable the usage of the time and scene Models  */
-/******************************************************************************/
-
-//#define ENABLE_TIME_MODEL_SERVER
-//#define ENABLE_TIME_MODEL_SERVER_SETUP
-//#define ENABLE_SCENE_MODEL_SERVER
-//#define ENABLE_SCENE_MODEL_SERVER_SETUP
-
-/******************************************************************************/
-/*
-Macros are defined to enable the setting for the PWM. these Macros are given for 
-eval board of BlueNRG-1 and BlueNRG-2, costom board and STEVAL-BLUEMIC-1 board
-and default transition inserted in generic on off.
-IMPORTATNT NOTE-  STEVAL_BLUENRG_1_BOARD_PWM_SELECTION
-                  STEVAL_BLUENRG_2_BOARD_PWM_SELECTION
-                  STEVAL_BLUEMIC_1_BOARD_PWM_SELECTION
-                  CUSTOM_BOARD_PWM_SELECTION
-                  GENERIC_ONOFF_DEFAULT_TRANSITION_ENABLE
-Only one macro must be enabled at one time from list of mocros provided here,
-otherwise get confliction and firmware will not work properly.
-*/
-/******************************************************************************/
-//#define STEVAL_BLUENRG_1_BOARD_PWM_SELECTION
-//#define STEVAL_BLUENRG_2_BOARD_PWM_SELECTION
-//#define STEVAL_BLUEMIC_1_BOARD_PWM_SELECTION
-//#define CUSTOM_BOARD_PWM_SELECTION
-
-
-/******************************************************************************/
-/*
-Define the Macro for enabling/disabling the Publishing with Generic on off
-or by Vendor Model.
-@ define Macro for Vendor Publishing
-@ Undefine or comment Macro for Generic On Off Publishing
-*/
-//#define VENDOR_MODEL_PUBLISH
- 
 /******************************************************************************/
 
 
@@ -256,8 +248,13 @@ This may result into excessive flash erase operations, this should be avoided to
 
 /* Only one Macro will be enable at one time */
 //#define SAVE_MODEL_STATE_FOR_ALL_MESSAGES         
-#define SAVE_MODEL_STATE_POWER_FAILURE_DETECTION
+//#define SAVE_MODEL_STATE_POWER_FAILURE_DETECTION
 
+/*      
+Define the following Macro to save the nodes data in provisioner in NVM
+This may result into excessive flash erase operations, this should be avoided to ensure flash longevity
+*/
+#define SAVE_EMBD_PROVISION_DATA     1
 /* Macros defined for the number of bytes saved, number of bytes dedicated for ganeric 
   model and light model.
 */     
@@ -281,40 +278,18 @@ This may result into excessive flash erase operations, this should be avoided to
 //#define  USER_BOARD_COOL_WHITE_LED
 //#define  USER_BOARD_RGB_LED 
 
-#if defined(STEVAL_BLUEMIC_1_BOARD_PWM_SELECTION)      
-   #define SINGLE_LED      PWM1
-#endif    
-
-/*******************************************************************************
-*** Following section helps to configure the LEDs of Application of Mesh     ***********
-*******************************************************************************/
-
-#if defined STEVAL_BLUENRG_1_BOARD_PWM_SELECTION || defined STEVAL_BLUENRG_2_BOARD_PWM_SELECTION
-  #define SINGLE_LED   PWM4
-  #define COOL_LED     PWM0
-  #define WARM_LED     PWM1
-  #define RED_LED      PWM2
-  #define GREEN_LED    PWM3
-  #define BLUE_LED     PWM4 
-#endif   
+/* Note: Please use Full Library configuration in project options to use the full 
+         configuration of the C/C++ runtime library for printf and scanf functionality */
 
-#if defined CUSTOM_BOARD_PWM_SELECTION || defined USE_STM32WBXX_NUCLEO || defined USE_STM32WBXX_USB_DONGLE
-  #define SINGLE_LED   PWM4    
-  #define COOL_LED     PWM0  
-  #define WARM_LED     PWM1
-  #define RED_LED      PWM2
-  #define GREEN_LED    PWM3
-  #define BLUE_LED     PWM4 
+/* Enables the serial interface using Uart */
+#define ENABLE_SERIAL_INTERFACE            1
+#define ENABLE_UT                          0
+#define ENABLE_SERIAL_CONTROL              1
+#define ENABLE_APPLI_TEST                  0
+#ifdef CLIENT
+#define ENABLE_SERIAL_PRVN                 1
 #endif
-
-#ifdef STEVAL_BLUEMIC_1_BOARD_PWM_SELECTION
-  #define SINGLE_LED   PWM1   
-  #define COOL_LED     PWM0  
-  #define WARM_LED     PWM1
-  #define RED_LED      PWM2
-  #define GREEN_LED    PWM3
-  #define BLUE_LED     PWM4 
-#endif      
+      
 /*******************************************************************************
 *** Following section helps to configure the Application of Mesh     ***********
 *******************************************************************************/
@@ -327,13 +302,15 @@ For STMicroelectronics : it is 0x0030 */
 #define COMPANY_ID                                                        0x0030
 
 /* Contains a 16-bit vendor-assigned product identifier */
-#define PRODUCT_ID                                                        0x0001
+#define PRODUCT_ID                                                        0x0002
 
 /* Contains a 16-bit vendor-assigned product version ID */
-#define PRODUCT_VERSION_ID                                                0x0001
+#define PRODUCT_VERSION_ID                                                0x010A   
 
 #define MAX_APPLICATION_PACKET_SIZE                                          160
 
+#define TPT_SEGMENT_COUNT                  (((MAX_APPLICATION_PACKET_SIZE)/12)+2)
+
 /*******************************************************************************
 ********** MAC Address Configuration *******************************************
 *******************************************************************************/
@@ -366,14 +343,14 @@ For STMicroelectronics : it is 0x0030 */
 
 
 /*
-*  Different provision bearer supported by BlueNRG-Mesh. Define according to application.
+*  Different provision bearer supported by BLE-Mesh. Define according to application.
 *      Atleast one of PB-ADV and PB-GATT should be defined
 */
 #define ENABLE_PB_ADV
 #define ENABLE_PB_GATT
-#define ENABLE_PUB_KEY_TYPE_OOB
-#define ENABLE_AUTH_TYPE_STATIC_OOB
-#define ENABLE_AUTH_TYPE_OUTPUT_OOB
+//#define ENABLE_PUB_KEY_TYPE_OOB
+//#define ENABLE_AUTH_TYPE_STATIC_OOB
+//#define ENABLE_AUTH_TYPE_OUTPUT_OOB
 //#define ENABLE_AUTH_TYPE_INPUT_OOB
 
 /* Static OOB Configurations */
@@ -401,16 +378,18 @@ For STMicroelectronics : it is 0x0030 */
 #endif
 
 /*
-*  Different features supported by BlueNRG-Mesh. Uncomment according to application.
+*  Different features supported by BLE-Mesh. Uncomment according to application.
 *      Low power feature enabled node do not support other features. 
 *      Do not define any other feature if Low Power feature is defined
 */
 #define ENABLE_RELAY_FEATURE
 #define ENABLE_PROXY_FEATURE
 #define ENABLE_FRIEND_FEATURE
-/* #define ENABLE_LOW_POWER_FEATURE */
-
-
+//#define ENABLE_LOW_POWER_FEATURE
+#ifdef CLIENT
+#define ENABLE_PROVISIONER_FEATURE
+#endif
+      
 /*
 * Friend node receive window size is fixed at 50 ms
 */
@@ -427,12 +406,16 @@ For STMicroelectronics : it is 0x0030 */
 *  Number of Low power nodes that can be associated with Friend node
 *  varies from 1 to 10
 */
-#define FN_NO_OF_LPNS                                                         2U
+#define FN_NO_OF_LPNS                                                         6U
 
 /* 
 *  For prioritizing friendship offer with good RSSI link
 *  varies from 0 to 3
 *  Ref @Mesh_v1.0
+*  0  ->  1
+*  1  ->  1.5
+*  2  ->  2
+*  3  ->  2.5
 */
 #define LPN_RSSI_FACTOR_LEVEL                                                 1U
 
@@ -440,13 +423,24 @@ For STMicroelectronics : it is 0x0030 */
 *  For prioritizing friendship offer with good receive window factor
 *  varies from 0 to 3
 *  Ref @Mesh_v1.0
+*  0  ->  1
+*  1  ->  1.5
+*  2  ->  2
+*  3  ->  2.5
 */
 #define LPN_RECIVE_WINDOW_FACTOR_LEVEL                                        1U
 
 /* 
-*  Minimum packets queue size required
+*  Minimum packets queue size required by Low Power node
 *  varies from 1 to 7
 *  Ref @Mesh_v1.0
+*  1  ->  2
+*  2  ->  4
+*  3  ->  8
+*  4  ->  16
+*  5  ->  32
+*  6  ->  64
+*  7  ->  128
 */
 #define LPN_MINIMUM_QUEUE_SIZE_LOG                                            2U
 
@@ -454,6 +448,8 @@ For STMicroelectronics : it is 0x0030 */
 *  (unit ms)
 *  varies from 0x0A to 0xFF
 *  Ref @Mesh_v1.0
+*  0x0A  ->  10ms
+*  0xFF  ->  255ms
 */
 #define LPN_RECEIVE_DELAY                                                   150U
 
@@ -461,15 +457,19 @@ For STMicroelectronics : it is 0x0030 */
 *  Poll timeout value after which friendship cease to exist (unit 100ms)
 *  varies from 0x00000A to 0x34BBFF
 *  Ref @Mesh_v1.0
+*  0x00000A  ->  1 second
+*  0x34BBFF  ->  96 hours
 */
 #define LPN_POLL_TIMEOUT                                                   2000U
 
 /* 
 *  Maximum receive window size acceptable to low power node (unit ms)
-*  varies from 10 to 255
+*  varies from 0x0A to 0xFF
 *  Ref @Mesh_v1.0
+*  0x0A  ->  10ms
+*  0xFF  ->  255ms
 */
-#define LPN_RECEIVE_WINDOW_SIZE                                              55U
+#define LPN_RECEIVE_WINDOW_SIZE                                              255U/*55U*/
 
 /* 
 *  Minimum friend's subscription list size capability required by lpn
@@ -481,12 +481,14 @@ For STMicroelectronics : it is 0x0030 */
 /* 
 *  Frequency at which low power node would send friend request (unit 100ms)
 *  varies from 0 to 255
+*  100  ->  10s
 */
 #define LPN_FRIEND_REQUEST_FREQUENCY                                         50U
 
 /* 
 *  Frequency at which low power node would poll friend node (unit 100ms)
 *  should be less than poll timeout
+*  100  ->  10s
 */
 #define LPN_FRIEND_POLL_FREQUENCY                                            25U
 
@@ -502,6 +504,10 @@ For STMicroelectronics : it is 0x0030 */
 */
 #define LPN_NO_OF_RETRIES                                                    10U
 
+/* 
+*  Maximum address list size buffer in Friend Subscription List Add Message is 10
+*/
+      
 
 /*
 *  Enable or disable neighbor table
@@ -533,14 +539,14 @@ For STMicroelectronics : it is 0x0030 */
 *  0: Disable neighbor table update with unprovisioned device beacon
 *  1: Enable neighbor table update with unprovisioned device beacon
 */
-#define NEIGHBOR_UNPRVND_DEV_BEACON_NTU                                       0U
+#define NEIGHBOR_UNPRVND_DEV_BEACON_NTU                                      1U
 
 /* 
 *  Enable/disable neighbor table update with secure network beacon
 *  0: Disable neighbor table update with secure network beacon
 *  1: Enable neighbor table update with secure network beacon
 */
-#define NEIGHBOR_SECURE_NET_BEACON_NTU                                        1U
+#define NEIGHBOR_SECURE_NET_BEACON_NTU                                       0U
 
 /* 
 *  Enable/disable neighbor table update with TTL 0 message
@@ -548,7 +554,68 @@ For STMicroelectronics : it is 0x0030 */
 *  1: Enable neighbor table update with messages with 0 TTL
 *  2: Enable neighbor table update with messages with any TTL
 */
-#define NEIGHBOR_MSG_TTLX_NTU                                                 1U
+#define NEIGHBOR_MSG_TTLX_NTU                                                0U
+
+/*******************************************************************************
+*** Following section helps to configure the LEDs of Application of Mesh     ***********
+*******************************************************************************/
+
+#if defined USE_STM32WBXX_NUCLEO || defined USE_STM32WBXX_USB_DONGLE
+  #define SINGLE_LED   PWM4    
+  #define COOL_LED     PWM0  
+  #define WARM_LED     PWM1
+  #define RED_LED      PWM2
+  #define GREEN_LED    PWM3
+  #define BLUE_LED     PWM4 
+#endif
+
+/* Following Macro helps to know if the Fixed functions are needed or not 
+   DO NOT change or add any space at the end of the file */
+#if defined (ENABLE_GENERIC_MODEL_SERVER_ONOFF) \
+    || defined (ENABLE_GENERIC_MODEL_SERVER_LEVEL) \
+    || defined (ENABLE_GENERIC_MODEL_SERVER_POWER_ONOFF) \
+    || defined (ENABLE_GENERIC_MODEL_SERVER_POWER_ONOFF_SETUP) \
+    || defined (ENABLE_GENERIC_MODEL_SERVER_DEFAULT_TRANSITION_TIME) \
+    || defined (ENABLE_GENERIC_MODEL_SERVER_POWER_LEVEL) \
+    || defined (ENABLE_GENERIC_MODEL_SERVER_POWER_LEVEL_SETUP) \
+    || defined (ENABLE_GENERIC_MODEL_SERVER_BATTERY) \
+    || defined (ENABLE_GENERIC_MODEL_SERVER_LOCATION) \
+    || defined (ENABLE_GENERIC_MODEL_SERVER_LOCATION_SETUP) \
+    || defined (ENABLE_GENERIC_MODEL_SERVER_ADMIN_PROPERTY) \
+    || defined (ENABLE_GENERIC_MODEL_SERVER_MANUFACTURER_PROPERTY) \
+    || defined (ENABLE_GENERIC_MODEL_SERVER_USER_PROPERTY) \
+    || defined (ENABLE_GENERIC_MODEL_SERVER_CLIENT_PROPERTY)
+ #define ENABLE_GENERIC_MODEL_SERVER
+ #define GENERIC_SERVER_MODEL_ADD_CONFIGURATION     
+      
+#endif      
+
+
+/* Following Macro helps to know if the Fixed functions are needed or not 
+   DO NOT change or add any space at the end of the file */
+#if defined(ENABLE_LIGHT_MODEL_SERVER_LIGHTNESS) \
+    || defined(ENABLE_LIGHT_MODEL_SERVER_LIGHTNESS_SETUP) \
+    || defined(ENABLE_LIGHT_MODEL_SERVER_CTL) \
+    || defined(ENABLE_LIGHT_MODEL_SERVER_CTL_SETUP) \
+    || defined(ENABLE_LIGHT_MODEL_SERVER_CTL_TEMPERATURE) \
+    || defined(ENABLE_LIGHT_MODEL_SERVER_HSL) \
+    || defined(ENABLE_LIGHT_MODEL_SERVER_HSL_SETUP) \
+    || defined(ENABLE_LIGHT_MODEL_SERVER_HSL_HUE) \
+    || defined(ENABLE_LIGHT_MODEL_SERVER_HSL_SATURATION) \
+    || defined(ENABLE_LIGHT_MODEL_SERVER_LC) \
+    || defined(ENABLE_LIGHT_MODEL_SERVER_LC_SETUP) \
+    || defined(ENABLE_LIGHT_MODEL_SERVER_XYL) \
+    || defined(ENABLE_LIGHT_MODEL_SERVER_XYL_SETUP)
+  #define  ENABLE_LIGHT_MODEL_SERVER 
+  #define LIGHT_SERVER_MODEL_ADD_CONFIGURATION    
+#endif  
+
+#if defined(ENABLE_TIME_MODEL_SERVER) \
+    || defined(ENABLE_TIME_MODEL_SERVER_SETUP)\
+    || defined(ENABLE_SCENE_MODEL_SERVER)\
+    || defined(ENABLE_SCENE_MODEL_SERVER_SETUP)
+   #define ENABLE_TIME_SCENE_MODEL_SERVER
+#endif             
 
 /* Exported variables  -------------------------------------------------------*/
 /* Exported Functions Prototypes ---------------------------------------------*/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/models_if.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/models_if.c
index 194a3ddca..09ef79884 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/models_if.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/models_if.c
@@ -33,21 +33,28 @@
 #include "appli_nvm.h"
 #include "ble_hci_le.h"
 #include "models_if.h"
-//#include "bluenrg1_api.h"
+
 #include "PWM_config.h"
 #include "PWM_handlers.h"
 #include "appli_light_lc.h"
 #include "light_lc.h"
+#ifdef ENABLE_PROVISIONER_FEATURE
+#include "appli_generic_client.h"
+#include "config_client.h"
+#endif
+#include "generic_client.h"
+#include "appli_light_client.h"
 
-/** @addtogroup BLE_Mesh
+/** @addtogroup ST_BLE_Mesh
 *  @{
 */
 
-/** @addtogroup models_BLE
+/** @addtogroup Application_Mesh_Models
 *  @{
 */
 
 /* Private typedef -----------------------------------------------------------*/
+#pragma pack(1)
 typedef struct
 {
   MOBLE_ADDRESS peer;
@@ -57,7 +64,6 @@ typedef struct
   MOBLEUINT32 length;
 } APPLI_SEND_RESPONSE_MODULE;
 
-
 typedef struct
 {
   MOBLEUINT8 packet_count;
@@ -66,6 +72,7 @@ typedef struct
   MOBLEUINT8 head_index;
   APPLI_SEND_RESPONSE_MODULE packet[MAX_PENDING_PACKETS_QUE_SIZE];
 } APPLI_PENDING_PACKETS;
+#pragma pack(4)
 
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
@@ -90,7 +97,8 @@ const Appli_Vendor_cb_t VendorAppli_cb =
   Appli_Vendor_DeviceInfo,
   Appli_Vendor_Test,
   Appli_LedCtrl,
-  Appli_GetTestValue 
+  Appli_GetTestValue, 
+  Appli_Vendor_Data_write
 };
 
 __attribute__((aligned(4)))   
@@ -98,17 +106,25 @@ const Appli_Generic_cb_t GenericAppli_cb =
 {
   /* Generic OnOff callbacks */
   Appli_Generic_OnOff_Set,
-  
+  /* Generic OnOff Status callbacks */
+  Appli_Generic_OnOff_Status,
   /* Generic Level callbacks */
   Appli_Generic_Level_Set,
   Appli_Generic_LevelDelta_Set,
   Appli_Generic_LevelMove_Set,
-  
+  /* Generic Level Status callbacks */ 
+  Appli_Generic_Level_Status,
   /* Generic Power on off callbacks */
   Appli_Generic_PowerOnOff_Set,
+  /* Generic Power on off callbacks */
+  Appli_Generic_PowerOnOff_Status,
+    
+  Appli_Generic_Restore_PowerOn_Value,
     
   /* Generic Default transition time callbacks */  
-  Appli_Generic_DefaultTransitionTime_Set
+  Appli_Generic_DefaultTransitionTime_Set,
+  /* Generic Default transition time callbacks */
+  Appli_Generic_DefaultTransitionTime_Status
 };
 
 __attribute__((aligned(4))) 
@@ -142,6 +158,7 @@ const Appli_Light_GetStatus_cb_t Appli_Light_GetStatus_cb =
   Appli_Light_GetHslSaturationStatus,
   Appli_Light_GetHslHueRange,
   Appli_Light_GetHslSatRange,
+  Appli_Light_GetHslDefaultStatus  
 };
 
 
@@ -150,20 +167,43 @@ const Appli_Light_cb_t LightAppli_cb =
 {
   /* Light Lightness callbacks */
   Appli_Light_Lightness_Set,
+  Appli_Light_Lightness_Status,
+  
   Appli_Light_Lightness_Linear_Set,
+  Appli_Light_Lightness_Linear_Status,
+  
   Appli_Light_Lightness_Default_Set,
+  Appli_Light_Lightness_Default_Status,
+  
   Appli_Light_Lightness_Range_Set,
+  Appli_Light_Lightness_Range_Status,
   
   Appli_Light_Ctl_Set,
+  Appli_Light_Ctl_Status,
+  
   Appli_Light_CtlTemperature_Set,
+  Appli_Light_CtlTemperature_Status,
+  
   Appli_Light_CtlTemperature_Range_Set,
+  Appli_Light_CtlTemperature_Range_Status,
+  
   Appli_Light_CtlDefault_Set,
+  Appli_Light_CtlDefault_Status,
   
   Appli_Light_Hsl_Set,
+  Appli_Light_Hsl_Status,
+  
   Appli_Light_HslHue_Set,
+  Appli_Light_HslHue_Status,
+  
   Appli_Light_HslSaturation_Set,
+  Appli_Light_HslSaturation_Status,
+  
   Appli_Light_HslDefault_Set,
-  Appli_Light_HslRange_Set
+  Appli_Light_HslDefault_Status,
+  
+  Appli_Light_HslRange_Set,
+  Appli_Light_HslRange_Status
 };
 
 
@@ -211,11 +251,14 @@ const Appli_Sensor_GetStatus_cb_t Appli_Sensor_GetStatus_cb =
 __attribute__((aligned(4))) 
 const MODEL_SIG_cb_t Model_SIG_cb[] = 
 {
+#ifdef ENABLE_GENERIC_MODEL_SERVER  
   {
     GenericModelServer_GetOpcodeTableCb,
     GenericModelServer_GetStatusRequestCb,
     GenericModelServer_ProcessMessageCb
   },
+#endif
+  
 #ifdef ENABLE_LIGHT_MODEL_SERVER
   {
     LightModelServer_GetOpcodeTableCb,
@@ -223,27 +266,42 @@ const MODEL_SIG_cb_t Model_SIG_cb[] =
     LightModelServer_ProcessMessageCb
   },
 #endif
-#if defined(ENABLE_SENSOR_MODEL_SERVER) || defined(ENABLE_SENSOR_MODEL_SERVER_SETUP)
+#ifdef ENABLE_SENSOR_MODEL_SERVER
 {
   SensorModelServer_GetOpcodeTableCb,
   SensorModelServer_GetStatusRequestCb,
   SensorModelServer_ProcessMessageCb
   },
 #endif
-#if defined(ENABLE_TIME_MODEL_SERVER) || defined(ENABLE_SCENE_MODEL_SERVER)
+#ifdef ENABLE_TIME_SCENE_MODEL_SERVER
   {
     Time_SceneModelServer_GetOpcodeTableCb,
     Time_SceneModelServer_GetStatusRequestCb,
     Time_SceneModelServer_ProcessMessageCb
   },
 #endif
-#if defined(ENABLE_LIGHT_MODEL_SERVER_LC) || defined(ENABLE_LIGHT_MODEL_SERVER_LC_SETUP)
+#ifdef ENABLE_LIGHT_MODEL_SERVER_LC
   {
     Light_LC_ModelServer_GetOpcodeTableCb,
     Light_LC_ModelServer_GetStatusRequestCb,
     Light_LC_ModelServer_ProcessMessageCb
   },
 #endif
+#ifdef ENABLE_GENERIC_MODEL_CLIENT
+  {
+    GenericModelClient_GetOpcodeTableCb,
+    GenericModelClient_GetStatusRequestCb,
+    GenericModelClient_ProcessMessageCb
+  },
+#endif  
+#ifdef ENABLE_CONFIG_MODEL_CLIENT
+  {
+    ConfigClientModel_GetOpcodeTableCb,
+    ConfigClientModel_GetStatusRequestCb,
+    ConfigClientModel_ProcessMessageCb
+  },
+#endif
+  
   { 0, 0,0 }
 };
 
@@ -254,11 +312,13 @@ __attribute__((aligned(4))) const APPLI_SAVE_MODEL_STATE_CB SaveModelState_cb =
 __attribute__((aligned(4))) 
 const MODEL_Vendor_cb_t Model_Vendor_cb[] = 
 {
+#ifdef ENABLE_VENDOR_MODEL_SERVER  
   {
     VendorModel_PID1_GetOpcodeTableCb,
     VendorModel_PID1_GetStatusRequestCb,
     VendorModel_PID1_ProcessMessageCb
   },
+#endif  
   { 0, 0,0 }
 };
 
@@ -284,18 +344,27 @@ void GetApplicationVendorModels(const MODEL_Vendor_cb_t** pModelsTable, MOBLEUIN
 */    
 void BLEMesh_ModelsInit(void)
 {
+  
+#ifdef ENABLE_SAVE_MODEL_STATE_NVM
+  
   MOBLEUINT8 modelStateLoad_Size;
   MOBLEUINT8 modelStateLoadBuff[APP_NVM_MODEL_SIZE];    
   
+#ifdef CLIENT
+  MOBLEUINT8 PrvnStateLoad_Size;
+  MOBLEUINT8 PrvnlStateLoadBuff[16]; 
+#endif
+  
   /* Callbacks used by BLE-Mesh Models */
   BLEMesh_SetSIGModelsCbMap(Model_SIG_cb, MODEL_SIG_COUNT);
-  
-  
-  /* Initialization of PWM value to 1 */
-  Appli_Light_PwmInit();
-  
+ 
   /* Load generic model states from nvm */
   AppliNvm_LoadModelState(modelStateLoadBuff, &modelStateLoad_Size);
+  
+#ifdef CLIENT
+  AppliPrvnNvm_LoadData(PrvnlStateLoadBuff,&PrvnStateLoad_Size);
+#endif
+  
   if (modelStateLoad_Size != 0)
   {
     /* update states of generic model */
@@ -306,6 +375,8 @@ void BLEMesh_ModelsInit(void)
   /* Initiallization of sensors */
   Appli_Sensor_Init();
 #endif  
+
+#endif  
 }
 
 /**
@@ -315,18 +386,29 @@ void BLEMesh_ModelsInit(void)
 */    
 void BLEMesh_ModelsProcess(void)
 {
+#ifdef ENABLE_GENERIC_MODEL_SERVER  
   Generic_Process();
+#endif
+
+#ifdef ENABLE_LIGHT_MODEL_SERVER  
   Lighting_Process();
+#endif
+
+#ifdef ENABLE_VENDOR_MODEL_SERVER  
   Vendor_Process();
+#endif  
 /* Define this Macro to enable the publication of sensors data.*/ 
 #if defined ENABLE_SENSOR_MODEL_SERVER 
   Sensor_Process();
 #endif  
 
-#ifdef ENABLE_APPLI_TEST  
+#if ENABLE_APPLI_TEST  
   Test_Process();
 #endif   
+
+#ifdef ENABLE_SAVE_MODEL_STATE_NVM  
   ModelSave_Process();
+#endif
   
 #ifdef ENABLE_LIGHT_MODEL_SERVER_LC   
   Light_control_Process();
@@ -340,44 +422,25 @@ void BLEMesh_ModelsProcess(void)
 */    
 void BLEMesh_ModelsCommand(void)
 {
-  MOBLE_ADDRESS publishAddress;
-  MOBLEUINT8 elementNumber = 0;
-  MOBLEUINT8 elementIndex;
-  
-  /*Select the Element Number for which publication address is required*/
-  
-  if (NumberOfElements == 1)
-  {
-    elementNumber = 0x01; 
-  }
+  MOBLE_ADDRESS srcAdd = BLEMesh_GetAddress();
   
-  else if(NumberOfElements == 2)
-  { 
-    elementNumber = 0x02; /*Element 2 is configured as switch*/
-  }
-  
-  else if(NumberOfElements == 3)
-  {
-    elementNumber = 0x03; /*Element 3 is configured as switch*/
-  }
-  
-  publishAddress = BLEMesh_GetPublishAddress(elementNumber);
-  elementIndex = elementNumber-1;
- 
-  if(publishAddress)
-  {
-    TRACE_M(TF_ADDRESS,"Published Address is= 0x%2x \n\r", publishAddress); 
-  }
-  else
-  {
-    TRACE_M(TF_ADDRESS,"Publish Address is unassigned!\r\n"); 
-  }
+#ifdef VENDOR_CLIENT_MODEL_PUBLISH     
+  Vendor_Publish(srcAdd);
+#endif
   
-#ifdef VENDOR_MODEL_PUBLISH   
-  Vendor_Publish(publishAddress, elementIndex);
-#else
-  Generic_Publish(publishAddress, elementIndex);
+#ifdef GENERIC_CLIENT_MODEL_PUBLISH  
+  Generic_Publish(srcAdd);
+//  Appli_GenericClient_OnOff_Set();
 #endif  
+
+#ifndef CLIENT
+/* if CLIENT and SERVER => Publish is already done in CLIENT */
+#ifdef GENERIC_SERVER_MODEL_PUBLISH 
+  Generic_Publish(srcAdd);
+#else
+  Vendor_Publish(srcAdd);
+#endif
+#endif
 }
 
 /**
@@ -409,8 +472,8 @@ MOBLE_RESULT BLEMesh_ModelsCheckSubscription(MOBLE_ADDRESS dst_peer, \
   MOBLE_RESULT status = MOBLE_RESULT_FAIL;
   MOBLE_ADDRESS subscriptionList[10] = {0};
   MOBLEUINT8 length;
-  
-  BLEMesh_GetSubscriptionAddress(subscriptionList,&length,elementNumber);
+  MOBLEUINT32 modelId = GENERIC_MODEL_SERVER_LEVEL_MODEL_ID;
+  BLEMesh_GetSubscriptionAddress(subscriptionList,&length,elementNumber, modelId);
   
   
   for(uint8_t list=0; list>>\r\n");
   
   if ((comparison == NULL) || (buf == NULL))
@@ -210,18 +213,17 @@ MOBLE_RESULT MoblePalNvmCompare(MOBLEUINT32 address,
   else
   {
     *comparison = MOBLE_NVM_COMPARE_EQUAL;
-    size >>= 3;
-    
-    uint64_t* src = (uint64_t*)buf;
-    uint64_t* dst = (uint64_t*)(address + offset);
+
+    uint8_t* src = (uint8_t*)buf;
+    uint8_t* dst = (uint8_t*)(address + offset);
     
     for (MOBLEUINT32 i=0; i>>\r\n");
+#ifdef ENABLE_SAVE_MODEL_STATE_NVM
+  
+  //  printf("MoblePalNvmWrite >>>\r\n");
   
   if (offset > NVM_SIZE)
   {
@@ -320,72 +317,29 @@ MOBLE_RESULT MoblePalNvmWrite(MOBLEUINT32 address,
   }
   else
   {
-#if 0
-    /* Check for repeated write request */
-    for (MOBLEUINT8 count = 0; count < BnrgmNvmReqs.no_of_write_reqs; count++)
-    {
-      if ((BnrgmNvmReqs.write_req[count].offset == (MOBLEUINT16)offset) && 
-          (BnrgmNvmReqs.write_req[count].size == (MOBLEUINT16)size) &&
-          (BnrgmNvmReqs.write_req[count].buff == buf))
-      {
-        return result;
-      }
-    }
-        
-    if (BnrgmNvmReqs.no_of_write_reqs < MAX_NVM_PENDING_WRITE_REQS)
-    {
-      BnrgmNvmReqs.write_req[BnrgmNvmReqs.no_of_write_reqs].offset = (MOBLEUINT16)offset;
-      BnrgmNvmReqs.write_req[BnrgmNvmReqs.no_of_write_reqs].size = (MOBLEUINT16)size;        
-      BnrgmNvmReqs.write_req[BnrgmNvmReqs.no_of_write_reqs].buff = buf;
-      BnrgmNvmReqs.no_of_write_reqs++;
-    }
-    /* If pending write requests already full, overwrite oldest one */
-    else
-    {
-      for (MOBLEINT8 count=0; count>= 3;
     
     uint64_t* src = (uint64_t*)buf;
-//    uint64_t* dst = (uint64_t*)(address + offset);
-    
-    HAL_StatusTypeDef status = HAL_OK;
     
     while( LL_HSEM_1StepLock( HSEM, CFG_HW_FLASH_SEMID ) );
     HAL_FLASH_Unlock();
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_OPTVERR);
-    for (size_t i = 0; (i < size) && (status == HAL_OK); i++)
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_OPTVERR | FLASH_FLAG_PGSERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGAERR);
+
+    for (size_t i = 0; i < size; i++)
+    {
+      do
       {
-//      if (src[i<<3] != dst[i<<3])
-//      {
         while(LL_FLASH_IsActiveFlag_OperationSuspended());
-        status = HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address + offset + (i <<3), src[i]);
-        if (status != HAL_OK)
-        {
-          break;
-        }
-//      }
+        HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address + offset + (i <<3), src[i]);
+        while(LL_FLASH_IsActiveFlag_OperationSuspended());
+      } while(*((uint64_t*)(address + offset + (i <<3))) != src[i]);
     }
+
     HAL_FLASH_Lock();
     LL_HSEM_ReleaseLock( HSEM, CFG_HW_FLASH_SEMID, 0 );
-    
-    if (HAL_OK != status)
-    {
-      result = MOBLE_RESULT_FAIL;
-    }
-#endif
   }
 //  printf("MoblePalNvmWrite <<<\r\n");
+#endif
   
   return result;
 }
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/user_if.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/user_if.h
index 99c990481..773b36116 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/user_if.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/STM32_WPAN/app/user_if.h
@@ -32,7 +32,7 @@
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
-* Initial BlueNRG-Mesh is built over Motorolas Mesh over Bluetooth Low Energy 
+* Initial BLE-Mesh is built over Motorolas Mesh over Bluetooth Low Energy 
 * (MoBLE) technology. The present solution is developed and maintained for both 
 * Mesh library and Applications solely by STMicroelectronics.
 *
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/BLE_MeshLightingDemo/.cproject b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/BLE_MeshLightingDemo/.cproject
deleted file mode 100644
index 3094e829a..000000000
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/BLE_MeshLightingDemo/.cproject
+++ /dev/null
@@ -1,183 +0,0 @@
-
-
-	
-		
-			
-				
-				
-					
-					
-					
-					
-					
-					
-				
-			
-			
-				
-					
-						
-							
-							
-					
-					
-						
-					
-				
-			
-			
-		
-	
-	
-		
-	
-	
-		
-		
-			
-		
-	
-	
-	
-		
-			
-		
-	
-	
-	
-
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/BLE_MeshLightingDemo/.project b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/BLE_MeshLightingDemo/.project
deleted file mode 100644
index 396d514aa..000000000
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/BLE_MeshLightingDemo/.project
+++ /dev/null
@@ -1,383 +0,0 @@
-
-	BLE_MeshLightingDemo
-	
-	
-	
-	
-		
-			org.eclipse.cdt.managedbuilder.core.genmakebuilder
-			clean,full,incremental,
-			
-			
-		
-		
-			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
-			full,incremental,
-			
-			
-		
-	
-	
-		org.eclipse.cdt.core.cnature
-		org.eclipse.cdt.managedbuilder.core.managedBuildNature
-		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
-		fr.ac6.mcu.ide.core.MCUProjectNature
-	
-	
-    
-      Application/SW4STM32/syscalls.c
-      1
-      PARENT-1-PROJECT_LOC/syscalls.c
-    
-      Application/SW4STM32/startup_stm32wb55xx_cm4.s
-      1
-      PARENT-1-PROJECT_LOC/startup_stm32wb55xx_cm4.s
-    
-		
-	
-			Application/Core/app_debug.c
-			1
-			PARENT-2-PROJECT_LOC/Core/Src/app_debug.c
-		
-    
-			Application/Core/app_entry.c
-			1
-			PARENT-2-PROJECT_LOC/Core/Src/app_entry.c
-		
-    
-			Application/Core/hw_timerserver.c
-			1
-			PARENT-2-PROJECT_LOC/Core/Src/hw_timerserver.c
-		
-    
-			Application/Core/hw_uart.c
-			1
-			PARENT-2-PROJECT_LOC/Core/Src/hw_uart.c
-		
-    
-			Application/Core/main.c
-			1
-			PARENT-2-PROJECT_LOC/Core/Src/main.c
-		
-    
-			Application/Core/stm32_lpm_if.c
-			1
-			PARENT-2-PROJECT_LOC/Core/Src/stm32_lpm_if.c
-		
-    
-			Application/Core/stm32wbxx_it.c
-			1
-			PARENT-2-PROJECT_LOC/Core/Src/stm32wbxx_it.c
-		
-    
-			Application/STM32_WPAN/app/app_ble.c
-			1
-			PARENT-2-PROJECT_LOC/STM32_WPAN/app/app_ble.c
-		
-    
-			Application/STM32_WPAN/app/appli_generic.c
-			1
-			PARENT-2-PROJECT_LOC/STM32_WPAN/app/appli_generic.c
-		
-    
-			Application/STM32_WPAN/app/appli_light.c
-			1
-			PARENT-2-PROJECT_LOC/STM32_WPAN/app/appli_light.c
-		
-    
-			Application/STM32_WPAN/app/appli_light_lc.c
-			1
-			PARENT-2-PROJECT_LOC/STM32_WPAN/app/appli_light_lc.c
-		
-    
-			Application/STM32_WPAN/app/appli_mesh.c
-			1
-			PARENT-2-PROJECT_LOC/STM32_WPAN/app/appli_mesh.c
-		
-    
-			Application/STM32_WPAN/app/appli_nvm.c
-			1
-			PARENT-2-PROJECT_LOC/STM32_WPAN/app/appli_nvm.c
-		
-    
-			Application/STM32_WPAN/app/appli_sensor.c
-			1
-			PARENT-2-PROJECT_LOC/STM32_WPAN/app/appli_sensor.c
-		
-    
-			Application/STM32_WPAN/app/appli_vendor.c
-			1
-			PARENT-2-PROJECT_LOC/STM32_WPAN/app/appli_vendor.c
-		
-    
-			Application/STM32_WPAN/app/models_if.c
-			1
-			PARENT-2-PROJECT_LOC/STM32_WPAN/app/models_if.c
-		
-    
-			Application/STM32_WPAN/app/pal_nvm.c
-			1
-			PARENT-2-PROJECT_LOC/STM32_WPAN/app/pal_nvm.c
-		
-    
-			Application/STM32_WPAN/app/PWM_config.c
-			1
-			PARENT-2-PROJECT_LOC/STM32_WPAN/app/PWM_config.c
-		
-    
-			Application/STM32_WPAN/app/PWM_handlers.c
-			1
-			PARENT-2-PROJECT_LOC/STM32_WPAN/app/PWM_handlers.c
-		
-    
-			Application/STM32_WPAN/target/hw_ipcc.c
-			1
-			PARENT-2-PROJECT_LOC/STM32_WPAN/target/hw_ipcc.c
-		
-    
-			Doc/readme.txt
-			1
-			PARENT-2-PROJECT_LOC/readme.txt
-		
-    
-			Drivers/BSP/P-NUCLEO-WB55.Nucleo/stm32wbxx_nucleo.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/BSP/P-NUCLEO-WB55.Nucleo/stm32wbxx_nucleo.c
-		
-    
-			Drivers/CMSIS/system_stm32wbxx.c
-			1
-			PARENT-2-PROJECT_LOC/Core/Src/system_stm32wbxx.c
-		
-    
-			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
-		
-    
-			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
-		
-    
-			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
-		
-    
-			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
-		
-    
-			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
-		
-    
-			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
-		
-    
-			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_i2c.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
-		
-    
-			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_i2c_ex.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c_ex.c
-		
-    
-			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
-		
-    
-			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
-		
-    
-			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
-		
-    
-			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
-		
-    
-			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
-		
-    
-			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc_ex.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
-		
-    
-			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
-		
-    
-			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
-		
-    
-			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
-		
-    
-			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart_ex.c
-			1
-			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
-		
-    
-			Middlewares/STM32_WPAN/ble/blesvc/common.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/common.c
-		
-    
-			Middlewares/STM32_WPAN/ble/blesvc/generic.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/generic.c
-		
-    
-			Middlewares/STM32_WPAN/ble/blesvc/light.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/light.c
-		
-    
-			Middlewares/STM32_WPAN/ble/blesvc/light_lc.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/light_lc.c
-		
-    
-			Middlewares/STM32_WPAN/ble/blesvc/mesh.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/svc/Src/mesh.c
-		
-    
-			Middlewares/STM32_WPAN/ble/blesvc/mesh_cfg.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/Src/mesh_cfg.c
-		
-    
-			Middlewares/STM32_WPAN/ble/blesvc/sensors.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/sensors.c
-		
-    
-			Middlewares/STM32_WPAN/ble/blesvc/svc_ctl.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/svc/Src/svc_ctl.c
-		
-    
-			Middlewares/STM32_WPAN/ble/blesvc/time_scene.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/time_scene.c
-		
-    
-			Middlewares/STM32_WPAN/ble/blesvc/vendor.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/vendor.c
-		
-    
-			Middlewares/STM32_WPAN/ble/core/ble_gap_aci.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_gap_aci.c
-		
-    
-			Middlewares/STM32_WPAN/ble/core/ble_gatt_aci.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_gatt_aci.c
-		
-    
-			Middlewares/STM32_WPAN/ble/core/ble_hal_aci.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_hal_aci.c
-		
-    
-			Middlewares/STM32_WPAN/ble/core/ble_hci_le.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_hci_le.c
-		
-    
-			Middlewares/STM32_WPAN/ble/core/ble_l2cap_aci.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_l2cap_aci.c
-		
-    
-			Middlewares/STM32_WPAN/ble/core/osal.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/core/template/osal.c
-		
-    
-			Middlewares/STM32_WPAN/interface/patterns/ble_thread/shci/shci.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/shci/shci.c
-		
-    
-			Middlewares/STM32_WPAN/interface/patterns/ble_thread/tl/hci_tl.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/hci_tl.c
-		
-    
-			Middlewares/STM32_WPAN/interface/patterns/ble_thread/tl/hci_tl_if.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/hci_tl_if.c
-		
-    
-			Middlewares/STM32_WPAN/interface/patterns/ble_thread/tl/shci_tl.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/shci_tl.c
-		
-    
-			Middlewares/STM32_WPAN/interface/patterns/ble_thread/tl/shci_tl_if.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/shci_tl_if.c
-		
-    
-			Middlewares/STM32_WPAN/interface/patterns/ble_thread/tl/tl_mbox.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl_mbox.c
-		
-    
-			Middlewares/STM32_WPAN/utilities/dbg_trace.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/utilities/dbg_trace.c
-		
-    
-			Middlewares/STM32_WPAN/utilities/otp.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/utilities/otp.c
-		
-    
-			Middlewares/STM32_WPAN/utilities/stm32_lpm.c
-			1
-			PARENT-7-PROJECT_LOC/Utilities/lpm/tiny_lpm/stm32_lpm.c
-		
-    
-			Middlewares/STM32_WPAN/utilities/stm32_seq.c
-			1
-			PARENT-7-PROJECT_LOC/Utilities/sequencer/stm32_seq.c
-		
-    
-			Middlewares/STM32_WPAN/utilities/stm_list.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/utilities/stm_list.c
-		
-    
-			Middlewares/STM32_WPAN/utilities/stm_queue.c
-			1
-			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/utilities/stm_queue.c
-		
-  
-
\ No newline at end of file
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/BLE_MeshLightingDemo/stm32wb55xx_flash_cm4.ld b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/BLE_MeshLightingDemo/stm32wb55xx_flash_cm4.ld
deleted file mode 100644
index a9ccd801e..000000000
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/BLE_MeshLightingDemo/stm32wb55xx_flash_cm4.ld
+++ /dev/null
@@ -1,187 +0,0 @@
-/**
-*****************************************************************************
-**
-**  File        : stm32wb55xx_flash_cm4.ld
-**
-**  Abstract    : System Workbench Minimal System calls file
-**
-** 		          For more information about which c-functions
-**                need which of these lowlevel functions
-**                please consult the Newlib libc-manual
-**
-**  Environment : System Workbench for MCU
-**
-**  Distribution: The file is distributed “as is,” without any warranty
-**                of any kind.
-**
-*****************************************************************************
-**
-** 
    © COPYRIGHT(c) 2019 Ac6
    
-**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of Ac6 nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20030000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x400;      /* required amount of heap  */
-_Min_Stack_Size = 0x1000; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
-RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x2FFFC
-RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM1 AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM1
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM1
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0       : { *(.ARM.attributes) }
-   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
-   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
-   MB_MEM2                : { *(MB_MEM2) } >RAM_SHARED  
-}
-
-
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/Lighting_Node/.cproject b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/Lighting_Node/.cproject
new file mode 100644
index 000000000..201ad3d83
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/Lighting_Node/.cproject
@@ -0,0 +1,181 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+							
+					
+					
+						
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+			
+		
+		
+	
+	
+	
+		
+		
+			
+		
+	
+
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/Lighting_Node/.project b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/Lighting_Node/.project
new file mode 100644
index 000000000..54ffad474
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/Lighting_Node/.project
@@ -0,0 +1,423 @@
+
+	Lighting_Node
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		org.eclipse.cdt.core.cnature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+		fr.ac6.mcu.ide.core.MCUProjectNature
+	
+	
+    
+      Application/SW4STM32/syscalls.c
+      1
+      PARENT-1-PROJECT_LOC/syscalls.c
+    
+      Application/SW4STM32/startup_stm32wb55xx_cm4.s
+      1
+      PARENT-1-PROJECT_LOC/startup_stm32wb55xx_cm4.s
+    
+		
+	
+			Application/Core/app_debug.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/app_debug.c
+		
+    
+			Application/Core/app_entry.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/app_entry.c
+		
+    
+			Application/Core/hw_flash.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/hw_flash.c
+		
+    
+			Application/Core/hw_timerserver.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/hw_timerserver.c
+		
+    
+			Application/Core/hw_uart.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/hw_uart.c
+		
+    
+			Application/Core/lp_timer.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/lp_timer.c
+		
+    
+			Application/Core/main.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/main.c
+		
+    
+			Application/Core/stm32_lpm_if.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/stm32_lpm_if.c
+		
+    
+			Application/Core/stm32wbxx_it.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/stm32wbxx_it.c
+		
+    
+			Application/STM32_WPAN/app/app_ble.c
+			1
+			PARENT-2-PROJECT_LOC/STM32_WPAN/app/app_ble.c
+		
+    
+			Application/STM32_WPAN/app/appli_config_client.c
+			1
+			PARENT-2-PROJECT_LOC/STM32_WPAN/app/appli_config_client.c
+		
+    
+			Application/STM32_WPAN/app/appli_generic.c
+			1
+			PARENT-2-PROJECT_LOC/STM32_WPAN/app/appli_generic.c
+		
+    
+			Application/STM32_WPAN/app/appli_generic_client.c
+			1
+			PARENT-2-PROJECT_LOC/STM32_WPAN/app/appli_generic_client.c
+		
+    
+			Application/STM32_WPAN/app/appli_light.c
+			1
+			PARENT-2-PROJECT_LOC/STM32_WPAN/app/appli_light.c
+		
+    
+			Application/STM32_WPAN/app/appli_light_client.c
+			1
+			PARENT-2-PROJECT_LOC/STM32_WPAN/app/appli_light_client.c
+		
+    
+			Application/STM32_WPAN/app/appli_light_lc.c
+			1
+			PARENT-2-PROJECT_LOC/STM32_WPAN/app/appli_light_lc.c
+		
+    
+			Application/STM32_WPAN/app/appli_mesh.c
+			1
+			PARENT-2-PROJECT_LOC/STM32_WPAN/app/appli_mesh.c
+		
+    
+			Application/STM32_WPAN/app/appli_nvm.c
+			1
+			PARENT-2-PROJECT_LOC/STM32_WPAN/app/appli_nvm.c
+		
+    
+			Application/STM32_WPAN/app/appli_sensor.c
+			1
+			PARENT-2-PROJECT_LOC/STM32_WPAN/app/appli_sensor.c
+		
+    
+			Application/STM32_WPAN/app/appli_vendor.c
+			1
+			PARENT-2-PROJECT_LOC/STM32_WPAN/app/appli_vendor.c
+		
+    
+			Application/STM32_WPAN/app/models_if.c
+			1
+			PARENT-2-PROJECT_LOC/STM32_WPAN/app/models_if.c
+		
+    
+			Application/STM32_WPAN/app/pal_nvm.c
+			1
+			PARENT-2-PROJECT_LOC/STM32_WPAN/app/pal_nvm.c
+		
+    
+			Application/STM32_WPAN/app/PWM_config.c
+			1
+			PARENT-2-PROJECT_LOC/STM32_WPAN/app/PWM_config.c
+		
+    
+			Application/STM32_WPAN/app/PWM_handlers.c
+			1
+			PARENT-2-PROJECT_LOC/STM32_WPAN/app/PWM_handlers.c
+		
+    
+			Application/STM32_WPAN/target/hw_ipcc.c
+			1
+			PARENT-2-PROJECT_LOC/STM32_WPAN/target/hw_ipcc.c
+		
+    
+			Doc/readme.txt
+			1
+			PARENT-2-PROJECT_LOC/readme.txt
+		
+    
+			Drivers/BSP/P-NUCLEO-WB55.Nucleo/stm32wbxx_nucleo.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/BSP/P-NUCLEO-WB55.Nucleo/stm32wbxx_nucleo.c
+		
+    
+			Drivers/CMSIS/system_stm32wbxx.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/system_stm32wbxx.c
+		
+    
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+		
+    
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
+		
+    
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
+		
+    
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c
+		
+    
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+		
+    
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+		
+    
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_i2c.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
+		
+    
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_i2c_ex.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c_ex.c
+		
+    
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+		
+    
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+		
+    
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+		
+    
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+		
+    
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c
+		
+    
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc_ex.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c
+		
+    
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+		
+    
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+		
+    
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+		
+    
+			Drivers/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart_ex.c
+			1
+			PARENT-7-PROJECT_LOC/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c
+		
+    
+			Middlewares/STM32_WPAN/ble/blesvc/common.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/common.c
+		
+    
+			Middlewares/STM32_WPAN/ble/blesvc/config_client.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/config_client.c
+		
+    
+			Middlewares/STM32_WPAN/ble/blesvc/generic.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/generic.c
+		
+    
+			Middlewares/STM32_WPAN/ble/blesvc/generic_client.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/generic_client.c
+		
+    
+			Middlewares/STM32_WPAN/ble/blesvc/light.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/light.c
+		
+    
+			Middlewares/STM32_WPAN/ble/blesvc/light_client.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/light_client.c
+		
+    
+			Middlewares/STM32_WPAN/ble/blesvc/light_lc.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/light_lc.c
+		
+    
+			Middlewares/STM32_WPAN/ble/blesvc/mesh.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/svc/Src/mesh.c
+		
+    
+			Middlewares/STM32_WPAN/ble/blesvc/mesh_cfg.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/Src/mesh_cfg.c
+		
+    
+			Middlewares/STM32_WPAN/ble/blesvc/sensors.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/sensors.c
+		
+    
+			Middlewares/STM32_WPAN/ble/blesvc/svc_ctl.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/svc/Src/svc_ctl.c
+		
+    
+			Middlewares/STM32_WPAN/ble/blesvc/time_scene.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/time_scene.c
+		
+    
+			Middlewares/STM32_WPAN/ble/blesvc/vendor.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/mesh/MeshModel/Src/vendor.c
+		
+    
+			Middlewares/STM32_WPAN/ble/core/ble_gap_aci.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_gap_aci.c
+		
+    
+			Middlewares/STM32_WPAN/ble/core/ble_gatt_aci.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_gatt_aci.c
+		
+    
+			Middlewares/STM32_WPAN/ble/core/ble_hal_aci.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_hal_aci.c
+		
+    
+			Middlewares/STM32_WPAN/ble/core/ble_hci_le.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_hci_le.c
+		
+    
+			Middlewares/STM32_WPAN/ble/core/ble_l2cap_aci.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/core/auto/ble_l2cap_aci.c
+		
+    
+			Middlewares/STM32_WPAN/ble/core/osal.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/ble/core/template/osal.c
+		
+    
+			Middlewares/STM32_WPAN/interface/patterns/ble_thread/shci/shci.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/shci/shci.c
+		
+    
+			Middlewares/STM32_WPAN/interface/patterns/ble_thread/tl/hci_tl.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/hci_tl.c
+		
+    
+			Middlewares/STM32_WPAN/interface/patterns/ble_thread/tl/hci_tl_if.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/hci_tl_if.c
+		
+    
+			Middlewares/STM32_WPAN/interface/patterns/ble_thread/tl/shci_tl.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/shci_tl.c
+		
+    
+			Middlewares/STM32_WPAN/interface/patterns/ble_thread/tl/shci_tl_if.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/shci_tl_if.c
+		
+    
+			Middlewares/STM32_WPAN/interface/patterns/ble_thread/tl/tl_mbox.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/interface/patterns/ble_thread/tl/tl_mbox.c
+		
+    
+			Middlewares/STM32_WPAN/utilities/dbg_trace.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/utilities/dbg_trace.c
+		
+    
+			Middlewares/STM32_WPAN/utilities/otp.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/utilities/otp.c
+		
+    
+			Middlewares/STM32_WPAN/utilities/stm32_lpm.c
+			1
+			PARENT-7-PROJECT_LOC/Utilities/lpm/tiny_lpm/stm32_lpm.c
+		
+    
+			Middlewares/STM32_WPAN/utilities/stm32_seq.c
+			1
+			PARENT-7-PROJECT_LOC/Utilities/sequencer/stm32_seq.c
+		
+    
+			Middlewares/STM32_WPAN/utilities/stm_list.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/utilities/stm_list.c
+		
+    
+			Middlewares/STM32_WPAN/utilities/stm_queue.c
+			1
+			PARENT-7-PROJECT_LOC/Middlewares/ST/STM32_WPAN/utilities/stm_queue.c
+		
+  
+
\ No newline at end of file
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/Lighting_Node/stm32wb55xx_flash_cm4.ld b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/Lighting_Node/stm32wb55xx_flash_cm4.ld
new file mode 100644
index 000000000..7ac9a391f
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/Lighting_Node/stm32wb55xx_flash_cm4.ld
@@ -0,0 +1,187 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb55xx_flash_cm4.ld
+**
+**  Abstract    : System Workbench Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : System Workbench for MCU
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
    © COPYRIGHT(c) 2019 Ac6
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of Ac6 nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20030000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x400;      /* required amount of heap  */
+_Min_Stack_Size = 0x1000;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x2FFFC
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/startup_stm32wb55xx_cm4.s b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/startup_stm32wb55xx_cm4.s
index 023c1b016..f79eec117 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/startup_stm32wb55xx_cm4.s
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/SW4STM32/startup_stm32wb55xx_cm4.s
@@ -44,21 +44,29 @@ defined in linker script */
 .word	_sbss
 /* end address for the .bss section. defined in linker script */
 .word	_ebss
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
   movs r3, #0
-  b	LoopCopyDataInit
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
 
+.section  .text.data_initializers
 CopyDataInit:
   ldr r4, [r2, r3]
   str r4, [r0, r3]
@@ -67,21 +75,31 @@ CopyDataInit:
 LoopCopyDataInit:
   adds r4, r0, r3
   cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
+  bcc  CopyDataInit
+  bx lr
 
 FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
+  str  r3, [r0]
+  adds r0, r0, #4
 
 LoopFillZerobss:
-  cmp r2, r4
+  cmp r0, r1
   bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/readme.txt b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/readme.txt
index b48f650ab..861e91274 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/readme.txt
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/readme.txt
@@ -32,59 +32,72 @@ This is the implementation of the BLE Mesh Lighting profile as specified by the
 
 @par Directory contents 
             mesh_lighting_demo
-  - BLE/BLE_MeshLightingDemo/Core/Inc/app_common.h            	Header for all modules with common definition
-  - BLE/BLE_MeshLightingDemo/Core/Inc/app_conf.h              	Parameters configuration file of the application
-  - BLE/BLE_MeshLightingDemo/Core/Inc/app_entry.h            	Parameters configuration file of the application
-  - BLE/BLE_MeshLightingDemo/Core/Inc/hw_conf.h           		Configuration file of the HW
-  - BLE/BLE_MeshLightingDemo/Core/Inc/main.h                  	Header for main.c module
-  - BLE/BLE_MeshLightingDemo/Core/Inc/stm32wbxx_hal_conf.h		HAL configuration file
-  - BLE/BLE_MeshLightingDemo/Core/Inc/stm32wbxx_it.h          	Interrupt handlers header file
-  - BLE/BLE_MeshLightingDemo/Core/Inc/utilities_conf.h    		Configuration file of the utilities
-  - BLE/BLE_MeshLightingDemo/Core/Inc/vcp_conf.h    		    Configuration file of Virtual Com Port Interface
-  - BLE/BLE_MeshLightingDemo/Core/Src/app_entry.c      		    Initialization of the application
-  - BLE/BLE_MeshLightingDemo/Core/Src/stm32_lpm_if.c		    Low Power Manager Interface
-  - BLE/BLE_MeshLightingDemo/Core/Src/hw_timerserver.c 		    Timer Server based on RTC
-  - BLE/BLE_MeshLightingDemo/Core/Src/hw_uart.c 			    UART Driver
-  - BLE/BLE_MeshLightingDemo/Core/Src/main.c                  	Main program
-  - BLE/BLE_MeshLightingDemo/Core/Src/stm32wbxx_it.c          	Interrupt handlers
-  - BLE/BLE_MeshLightingDemo/Core/Src/system_stm32wbxx.c      	stm32wbxx system source file
-  - BLE/BLE_MeshLightingDemo/Core/Inc/app_ble.h               	Header for app_ble.c module
-  - BLE/BLE_MeshLightingDemo/Core/Inc/tl_conf.h           		Configuration file of the Transport layer
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/app_ble.c      		BLE Profile implementation
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/app_ble.h      		Header of BLE Profile implementation 
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_generic.c     BLE Mesh Generic Profile implementation
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_generic.h     Header of BLE Mesh Generic Profile implementation 
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_light.c       BLE Mesh Light Profile implementation
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_light.h       Header of BLE Mesh Light Profile implementation 
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_light_lc.c    BLE Mesh Light Lightness Controller Profile implementation
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_light_lc.h    Header of BLE Mesh Light Lightness Controller Profile implementation 
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_mesh.c        BLE Mesh application implementation
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_mesh.h        Header of BLE Mesh application implementation 
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_nvm.c         BLE Mesh NVM application implementation
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_nvm.h         Header of BLE Mesh NVM application implementation 
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_sensor.c      BLE Mesh Sensor Profile implementation
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_sensor.h      Header of BLE Mesh Sensor Profile implementation 
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_vendor.c      BLE Mesh Vendor Profile implementation
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_vendor.h      Header of BLE Mesh Vendor Profile implementation 
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/ble_conf.h          BLE Services configuration
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/ble_dbg_conf.h      BLE Traces configuration of the BLE services
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/hal_common.h        Header for common function of HAL file
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/mesh_cfg.h         	Header for Mesh configuration
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/mesh_cfg_usr.h      Header for user Mesh configuration
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/models_if.h         Header for the BLE Mesh Models Interface file
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/models_if.c         BLE Mesh Models Interface file
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/pal_nvm.c           BLE Mesh NVM management implementation
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/pal_nvm.h           Header of BLE Mesh NVM management implementation 
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/PWM_config.c        Pulse Width Modulation configuration
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/PWM_config.h        Header of Pulse Width Modulation configuration 
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/PWM_handlers.c      Pulse Width Modulation handlers
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/PWM_handlers.h      Header of Pulse Width Modulation handlers 
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/svcctl_conf.c 		Service Controller configuration API
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/tl_conf.h           Configuration file of the Transport layer
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/tl_if.c 			Transport Layer interface
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/user_if.h 		    Header file for User interface file
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/user_if.c 		    User interface file
-  - BLE/BLE_MeshLightingDemo/STM32_WPAN/Target/hw_ipcc.c     	IPCC Driver
+  - BLE/BLE_MeshLightingDemo/Core/Inc/app_common.h                  Header for all modules with common definition
+  - BLE/BLE_MeshLightingDemo/Core/Inc/app_conf.h                    Parameters configuration file of the application
+  - BLE/BLE_MeshLightingDemo/Core/Inc/app_debug.h                   Interface to support debug in the application
+  - BLE/BLE_MeshLightingDemo/Core/Inc/app_entry.h                   Parameters configuration file of the application
+  - BLE/BLE_MeshLightingDemo/Core/Inc/hw_conf.h                     Configuration file of the HW
+  - BLE/BLE_MeshLightingDemo/Core/Inc/hw_flash.h                    Configuration file of the FLASH driver needed by EE module
+  - BLE/BLE_MeshLightingDemo/Core/Inc/hw_if.h                       Configuration file of the Hardware Iterface
+  - BLE/BLE_MeshLightingDemo/Core/Inc/lp_timer.h                    Configuration file of the Low power timer to be used within Mesh Application.
+  - BLE/BLE_MeshLightingDemo/Core/Inc/main.h                        Header for main.c module
+  - BLE/BLE_MeshLightingDemo/Core/Inc/stm32wbxx_hal_conf.h          HAL configuration file
+  - BLE/BLE_MeshLightingDemo/Core/Inc/stm32_lpm_if.h                Configuration file of the Low layer function to enter/exit low power modes (stop, sleep).
+  - BLE/BLE_MeshLightingDemo/Core/Inc/stm32wbxx_it.h                Interrupt handlers header file
+  - BLE/BLE_MeshLightingDemo/Core/Inc/utilities_conf.h              Configuration file of the utilities
+  - BLE/BLE_MeshLightingDemo/Core/Inc/vcp_conf.h                    Configuration file of Virtual Com Port Interface
+  - BLE/BLE_MeshLightingDemo/Core/Src/app_debug.c                   Interface to support debug in the application
+  - BLE/BLE_MeshLightingDemo/Core/Src/app_entry.c                   Initialization of the application
+  - BLE/BLE_MeshLightingDemo/Core/Src/hw_flash.c                    FLASH driver needed by EE module
+  - BLE/BLE_MeshLightingDemo/Core/Src/hw_timerserver.c              Timer Server based on RTC
+  - BLE/BLE_MeshLightingDemo/Core/Src/hw_uart.c                     UART Driver
+  - BLE/BLE_MeshLightingDemo/Core/Src/lp_timer.c                    Low power timer to be used within Mesh Application.
+  - BLE/BLE_MeshLightingDemo/Core/Src/main.c                        Main program
+  - BLE/BLE_MeshLightingDemo/Core/Src/stm32_lpm_if.c                Low Power Manager Interface
+  - BLE/BLE_MeshLightingDemo/Core/Src/stm32wbxx_it.c                Interrupt handlers
+  - BLE/BLE_MeshLightingDemo/Core/Src/system_stm32wbxx.c            stm32wbxx system source file
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/app_ble.c               BLE Profile implementation
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/app_ble.h               Header of BLE Profile implementation 
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_config_client.c   Application interface for Config CLient Mesh Model
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_config_client.h   Header of Application interface for Config CLient Mesh Model 
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_generic.c         Application interface for Generic Mesh Models
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_generic.h         Header of Application interface for Generic Mesh Models 
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_generic_client.c  Application interface for Client Generic Mesh Models
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_generic_client.h  Header of Application interface for Client Generic Mesh Models 
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_light.c           BLE Mesh Light Profile implementation
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_light.h           Header of BLE Mesh Light Profile implementation 
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_light_client.c    Application interface for Client Light Mesh Models
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_light_client.h    Header of Application interface for Client Light Mesh Models 
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_light_lc.c        BLE Mesh Light Lightness Controller Profile implementation
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_light_lc.h        Header of BLE Mesh Light Lightness Controller Profile implementation 
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_mesh.c            BLE Mesh application implementation
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_mesh.h            Header of BLE Mesh application implementation 
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_nvm.c             BLE Mesh NVM application implementation
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_nvm.h             Header of BLE Mesh NVM application implementation 
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_sensor.c          BLE Mesh Sensor Profile implementation
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_sensor.h          Header of BLE Mesh Sensor Profile implementation 
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_vendor.c          BLE Mesh Vendor Profile implementation
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/appli_vendor.h          Header of BLE Mesh Vendor Profile implementation 
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/ble_conf.h              BLE Services configuration
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/ble_dbg_conf.h          BLE Traces configuration of the BLE services
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/hal_common.h            Header for common function of HAL file
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/mesh_cfg.h              Header for Mesh configuration
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/mesh_cfg_usr.h          Header for user Mesh configuration
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/models_if.h             Header for the BLE Mesh Models Interface file
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/models_if.c             BLE Mesh Models Interface file
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/pal_nvm.c               BLE Mesh NVM management implementation
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/pal_nvm.h               Header of BLE Mesh NVM management implementation 
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/PWM_config.c            Pulse Width Modulation configuration
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/PWM_config.h            Header of Pulse Width Modulation configuration 
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/PWM_handlers.c          Pulse Width Modulation handlers
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/PWM_handlers.h          Header of Pulse Width Modulation handlers 
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/svcctl_conf.c           Service Controller configuration API
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/tl_conf.h               Configuration file of the Transport layer
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/tl_if.c                 Transport Layer interface
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/user_if.h               Header file for User interface file
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/user_if.c               User interface file
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/App/vcp_conf.h              Configuration of the vcp interface
+  - BLE/BLE_MeshLightingDemo/STM32_WPAN/Target/hw_ipcc.c            IPCC Driver
 
      
 @par Hardware and Software environment
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Inc/app_debug.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Inc/app_debug.h
new file mode 100644
index 000000000..13485c16b
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Inc/app_debug.h
@@ -0,0 +1,45 @@
+
+/**
+  ******************************************************************************
+  * @file    app_debug.h
+  * @author  MCD Application Team
+  * @brief   Interface to support debug in the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+  /* Exported types ------------------------------------------------------------*/
+  /* Exported constants --------------------------------------------------------*/
+  /* External variables --------------------------------------------------------*/
+  /* Exported macros -----------------------------------------------------------*/
+  /* Exported functions ------------------------------------------------------- */
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Inc/hw_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Inc/hw_conf.h
index cce3af451..bd949bad9 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Inc/hw_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Inc/hw_conf.h
@@ -24,9 +24,37 @@
 #define HW_CONF_H
 
 /******************************************************************************
- * Semaphores
- * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
- *****************************************************************************/
+* Semaphores
+* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
+*****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
 /* Index of the semaphore used to manage the entry Stop Mode procedure */
 #define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Src/app_debug.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Src/app_debug.c
new file mode 100644
index 000000000..246173ae6
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Src/app_debug.c
@@ -0,0 +1,349 @@
+/**
+ ******************************************************************************
+ * @file    app_debug.c
+ * @author  MCD Application Team
+ * @brief   Debug capabilities
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+  HW_UART_Init(CFG_DEBUG_TRACE_UART);
+  return;
+}
+
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Src/app_entry.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Src/app_entry.c
index 089e5054c..25217c36f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Src/app_entry.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Src/app_entry.c
@@ -31,7 +31,7 @@
 #include "stm32_seq.h"
 #include "shci_tl.h"
 #include "stm32_lpm.h"
-#include "dbg_trace.h"
+#include "app_debug.h"
 #include "uart_app.h"
 
 /* Private includes -----------------------------------------------------------*/
@@ -74,7 +74,6 @@ PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t BleSpareEvtBuffer[sizeof(TL_
 
 /* Private functions prototypes-----------------------------------------------*/
 static void SystemPower_Config( void );
-static void Init_Debug( void );
 static void appe_Tl_Init( void );
 static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status );
 static void APPE_SysUserEvtRx( void * pPayload );
@@ -105,7 +104,7 @@ void APPE_Init( void )
   HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
 
 /* USER CODE BEGIN APPE_Init_1 */
-  Init_Debug();
+  APPD_Init();
 
   /**
    * The Standby mode should not be entered before the initialization is over
@@ -165,48 +164,6 @@ static void Mode_Selec( void )
   }
 }
 
-static void Init_Debug( void )
-{
-#if (CFG_DEBUGGER_SUPPORTED == 1)
-  /**
-   * Keep debugger enabled while in any low power mode
-   */
-  HAL_DBGMCU_EnableDBGSleepMode();
-
-  /***************** ENABLE DEBUGGER *************************************/
-  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-  LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-
-#else
-
-  GPIO_InitTypeDef gpio_config = {0};
-
-  gpio_config.Pull = GPIO_NOPULL;
-  gpio_config.Mode = GPIO_MODE_ANALOG;
-
-  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOA, &gpio_config);
-  __HAL_RCC_GPIOA_CLK_DISABLE();
-
-  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOB, &gpio_config);
-  __HAL_RCC_GPIOB_CLK_DISABLE();
-
-  HAL_DBGMCU_DisableDBGSleepMode();
-  HAL_DBGMCU_DisableDBGStopMode();
-  HAL_DBGMCU_DisableDBGStandbyMode();
-
-#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
-
-#if(CFG_DEBUG_TRACE != 0)
-  DbgTraceInit();
-#endif
-
-  return;
-}
-
 /**
  * @brief  Configure the system for power optimization
  *
@@ -280,7 +237,7 @@ static void APPE_SysUserEvtRx( void * pPayload )
 {
   UNUSED(pPayload);
   /* Traces channel initialization */
-  TL_TRACES_Init( );
+  APPD_EnableCPU2();
   
   switch(APP_MODE)
   {
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Src/stm32_lpm_if.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Src/stm32_lpm_if.c
index f024b61e3..1418e0a36 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Src/stm32_lpm_if.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/Core/Src/stm32_lpm_if.c
@@ -70,6 +70,13 @@ static void Switch_On_HSI( void );
 void PWR_EnterOffMode( void )
 {
 /* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
   /************************************************************************************
    * ENTER OFF MODE
    ***********************************************************************************/
@@ -106,6 +113,8 @@ void PWR_ExitOffMode( void )
 {
 /* USER CODE BEGIN PWR_ExitOffMode */
 
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitOffMode */
 }
 
@@ -118,6 +127,16 @@ void PWR_ExitOffMode( void )
 void PWR_EnterStopMode( void )
 {
 /* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
   /**
    * This function is called from CRITICAL SECTION
    */
@@ -202,6 +221,9 @@ void PWR_ExitStopMode( void )
 
   /* Release RCC semaphore */
   LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitStopMode */
 }
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/EWARM/BLE_MultiAppAt.ewp b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/EWARM/BLE_MultiAppAt.ewp
index cada6268f..dd27f5eeb 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/EWARM/BLE_MultiAppAt.ewp
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/EWARM/BLE_MultiAppAt.ewp
@@ -1055,6 +1055,9 @@
                 
                     $PROJ_DIR$\..\Core\Src\app_entry.c
                 
+                
+                    $PROJ_DIR$\..\Core\Src\app_debug.c
+                
                 
                     $PROJ_DIR$\..\Core\Src\hw_timerserver.c
                 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/MDK-ARM/ble_multi_app_at.uvprojx b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/MDK-ARM/ble_multi_app_at.uvprojx
index 274472a80..ed6d96426 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/MDK-ARM/ble_multi_app_at.uvprojx
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/MDK-ARM/ble_multi_app_at.uvprojx
@@ -411,6 +411,11 @@
               1
               ../Core/Src/main.c
             
+            
+              app_debug.c
+              1
+              ../Core/Src/app_debug.c
+            
             
               stm32_lpm_if.c
               1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/SW4STM32/BLE_MultiAppAt/.project b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/SW4STM32/BLE_MultiAppAt/.project
index dc8b68ddb..2a72f61af 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/SW4STM32/BLE_MultiAppAt/.project
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/SW4STM32/BLE_MultiAppAt/.project
@@ -275,6 +275,11 @@
 			1
 			PARENT-2-PROJECT_LOC/Core/Src/main.c
 		
+		
+			Application/User/Core/app_debug.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/app_debug.c
+		
 		
 			Application/User/Core/stm32_lpm_if.c
 			1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/SW4STM32/BLE_MultiAppAt/stm32wb55xx_flash_cm4.ld b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/SW4STM32/BLE_MultiAppAt/stm32wb55xx_flash_cm4.ld
index 303201bd2..7ac9a391f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/SW4STM32/BLE_MultiAppAt/stm32wb55xx_flash_cm4.ld
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/SW4STM32/BLE_MultiAppAt/stm32wb55xx_flash_cm4.ld
@@ -50,13 +50,13 @@ ENTRY(Reset_Handler)
 _estack = 0x20030000;    /* end of RAM */
 /* Generate a link error if heap and stack don't fit into RAM */
 _Min_Heap_Size = 0x400;      /* required amount of heap  */
-_Min_Stack_Size = 0x1000; /* required amount of stack */
+_Min_Stack_Size = 0x1000;   /* required amount of stack */
 
 /* Specify the memory areas */
 MEMORY
 {
 FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
-RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 191K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x2FFFC
 RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
 }
 
@@ -181,7 +181,7 @@ SECTIONS
   .ARM.attributes 0       : { *(.ARM.attributes) }
    MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
    MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
-   MB_MEM2                : { *(MB_MEM2) } >RAM_SHARED  
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
 }
 
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/SW4STM32/startup_stm32wb55xx_cm4.s b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/SW4STM32/startup_stm32wb55xx_cm4.s
index 023c1b016..f79eec117 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/SW4STM32/startup_stm32wb55xx_cm4.s
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/SW4STM32/startup_stm32wb55xx_cm4.s
@@ -44,21 +44,29 @@ defined in linker script */
 .word	_sbss
 /* end address for the .bss section. defined in linker script */
 .word	_ebss
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
   movs r3, #0
-  b	LoopCopyDataInit
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
 
+.section  .text.data_initializers
 CopyDataInit:
   ldr r4, [r2, r3]
   str r4, [r0, r3]
@@ -67,21 +75,31 @@ CopyDataInit:
 LoopCopyDataInit:
   adds r4, r0, r3
   cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
+  bcc  CopyDataInit
+  bx lr
 
 FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
+  str  r3, [r0]
+  adds r0, r0, #4
 
 LoopFillZerobss:
-  cmp r2, r4
+  cmp r0, r1
   bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/readme.txt b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/readme.txt
index 83c61a1bb..bb742c12d 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/readme.txt
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MultiAppAt/readme.txt
@@ -104,7 +104,8 @@ On the android/ios device, enable the Bluetooth communications, and if not done
  - Type "AT+SV\r", you should receive "SV OK". You are now in AT P2P Server mode.
  - Type "AT+SV$ADV_START\r". You should receive A and see a green led blinking rapidly on the board.
  - Then, with your phone, click on the App icon, ST BLE Sensor (android device)
- - select the ATP2PSV in the device list, connect to the device and play with the App as well as the terminal, using commands described in the Application Note.
+ - select the ATP2PSV in the device list, connect to the device and play with the App as well as the terminal, using commands described in the Application Note
+   as the instruction "AT+SV$NOTIFY=XXXX\r" with XXXX input parameter being 2 bytes hex values in range [0-9]/[A-F].
 
 
 Second demonstration
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/Binary/BLE_Ota_reference.hex b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/Binary/BLE_Ota_reference.hex
index 900524111..2bb6baae7 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/Binary/BLE_Ota_reference.hex
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/Binary/BLE_Ota_reference.hex
@@ -1,24 +1,24 @@
 :020000040800F2
-:10000000F0230020454400084D4300084F430008FA
-:1000100061440008654400086944000800000000CD
-:100020000000000000000000000000005143000834
-:1000300053430008000000005543000857430008E0
-:100040006D440008714400087544000867430008C7
-:10005000794400087D440008814400088544000874
-:10006000894400088D440008914400089544000824
-:10007000994400089D440008A1440008A5440008D4
-:10008000A9440008AD440008B1440008B544000884
-:10009000B9440008BD440008C1440008C544000834
-:1000A000C9440008CD440008D1440008D5440008E4
-:1000B000D9440008DD440008E1440008E544000894
-:1000C000E9440008ED440008F1440008F544000844
-:1000D0005B430008F9440008FD440008014500089E
-:1000E00005450008094500080D45000811450008B0
-:1000F0006F4300086B4300081545000819450008C8
-:100100001D4500082145000825450008294500082F
-:100110002D450008314500083545000839450008DF
-:100120003D45000841450008614300084545000879
-:10013000494500084D4500085145000838B5040000
+:10000000F0230020354400083D4300083F4300082A
+:1000100051440008554400085944000800000000FD
+:100020000000000000000000000000004143000844
+:100030004343000800000000454300084743000810
+:100040005D44000861440008654400085743000807
+:10005000694400086D4400087144000875440008B4
+:10006000794400087D440008814400088544000864
+:10007000894400088D440008914400089544000814
+:10008000994400089D440008A1440008A5440008C4
+:10009000A9440008AD440008B1440008B544000874
+:1000A000B9440008BD440008C1440008C544000824
+:1000B000C9440008CD440008D1440008D5440008D4
+:1000C000D9440008DD440008E1440008E544000884
+:1000D0004B430008E9440008ED440008F1440008DF
+:1000E000F5440008F9440008FD44000801450008F3
+:1000F0005F4300085B430008054500080945000808
+:100100000D4500081145000815450008194500086F
+:100110001D4500082145000825450008294500081F
+:100120002D450008314500085143000835450008B9
+:10013000394500083D4500084145000838B5040030
 :1001400009D004F17C05686808B900F01EF800F0D9
 :1001500021F8012801D1012032BDA06A08B100F0C8
 :100160002AF800F00AF821F02A01FFE7816000F088
@@ -313,8 +313,8 @@
 :10137000FFF7EFFF00F010F8C1F3022106E080B59F
 :10138000FFF7E7FF00F008F8C1F3C22112F82110BF
 :1013900001F01F01C84002BD0149064A09687047B3
-:1013A000080000586C4200080024F4000048E801DE
-:1013B0002C420008E0430008B3BBD9B1B2F5803F2E
+:1013A000080000585C4200080024F4000048E801EE
+:1013B0001C420008D0430008B3BBD9B1B2F5803F4E
 :1013C0007DD2022A1ED98C46B1FBF2F102FB11C379
 :1013D0001B0443EA1043B3FBF2FC02FB1C3380B254
 :1013E00040EA0343B3FBF2F002FB103240EA0C4048
@@ -515,7 +515,7 @@
 :1020100000F031BD10B50F490A6812F1010F0DD063
 :1020200012484B6802701B0A140A120C447082702A
 :1020300049680371C1701B0A437110BD002000F094
-:10204000EDFE08B90FF2700010BD0000AC080320CF
+:10204000E5FE08B90FF2700010BD0000AC080320D7
 :10205000FF2100088075FF1F07B2010010400058E3
 :102060000CED00E00400FA0504000020B01300208D
 :102070000021012000F014BA012000F033BA012041
@@ -540,22 +540,22 @@
 :1021A0001B0C121F00F8013BF3D238BF121D521E48
 :1021B00024BF11F8013B00F8013BF8D8704700003C
 :1021C0007FB50C466D4D61686D4EE8612962284609
-:1021D00000F036FE246805F1240000604060746061
+:1021D00000F02EFE246805F1240000604060746069
 :1021E00006F108000060406001203070296829B1C4
 :1021F0000FF2551000900294684688477FBD1FB5C6
-:102200005F4C04F1080000F028FE00BB2178F1B11A
-:10221000694604F1080000F049FE5848C16949B117
+:102200005F4C04F1080000F020FE00BB2178F1B122
+:10221000694604F1080000F041FE5848C16949B11F
 :102220000098029001228DF8042001A888479DF8AB
 :10223000040000E001202070207818B1009800F020
-:10224000E8FE04E0009904F1080000F00FFE04F13C
-:10225000080000F002FE28B9207818B104F1080047
+:10224000E0FE04E0009904F1080000F007FE04F14C
+:10225000080000F0FAFD28B9207818B104F1080050
 :10226000FFF706FF1FBD2DE9F8430646002000F0EA
 :102270005FF874883088B268DFF80081C4F309041D
 :1022800044EA8024F068A4B2C1B2204600F03CF8D1
 :10229000002748F2E8094846FFF7F1FE08E06888A1
 :1022A000A04202D1316928780870687800B101270E
-:1022B00008F1240000F0D1FDF0B9694608F12400CE
-:1022C00000F0F4FD009800F10B05407A0F28E6D0ED
+:1022B00008F1240000F0C9FDF0B9694608F12400D6
+:1022C00000F0ECFD009800F10B05407A0F28E6D0F5
 :1022D000B5F80110A1420DD10098817AC81E71692C
 :1022E000C0B28842C8BF0846706102463069E91C26
 :1022F000FFF712FF2878D9E73800CCD0012000F092
@@ -564,8 +564,8 @@
 :10232000FBFE164A1369BDE8104000210020184743
 :102330001249096A82B008B921B101E011B1012046
 :1023400002B0084702B0704710B50146487A0F281E
-:1023500018BF0E2807D10B4800F092FDBDE81040D1
-:102360000020FFF789BE064C04F1080000F088FD4C
+:1023500018BF0E2807D10B4800F08AFDBDE81040D9
+:102360000020FFF789BE064C04F1080000F080FD54
 :1023700004F10800BDE81040FFF77ABEB412002057
 :1023800078130020D81200200C4800210160416021
 :10239000704710B500F00CF85C6819B1012904D140
@@ -582,7 +582,7 @@
 :10244000A2691840104207D0E069216A084203D10E
 :10245000002103EA0206C1E7C046C046EFF3108937
 :1024600072B6216960690140A069014201BFE1695A
-:10247000206A014200F0C8FE89F31088C046C046B9
+:10247000206A014200F0C0FE89F31088C046C046C1
 :10248000A561BDE8F38738B51446EFF3108572B641
 :1024900000F050F8264941F8204085F3108831BDFE
 :1024A00010B5EFF3108272B6204B1C6904431C6117
@@ -591,7 +591,7 @@
 :1024D000EFF3108172B6154A53691843506181F3C6
 :1024E00010887047EFF3108172B6104AD369184311
 :1024F000D061F4E72DE9F0410C4C626A266A206253
-:10250000012101FA02F803E03946404600F07DFE61
+:10250000012101FA02F803E03946404600F075FE69
 :10251000276AE5693D42F7D0404600F00BF825EA0E
 :102520000707E76126626062BDE8F081381000208D
 :10253000D411002002460020110C090404BF102011
@@ -599,27 +599,27 @@
 :1025500012F0704F04BF001D1201120FC0F11F00D6
 :10256000895C401A70470000040302020101010166
 :1025700000000000000000001FB5044600F030F825
-:102580004FF6524000F0A5FE14B19DF80F002070E8
+:102580004FF6524000F09DFE14B19DF80F002070F0
 :102590000EE01FB5002408B10090042409B1019198
-:1025A000241D6B466A46E1B24FF6544000F091FE9E
-:1025B0009DF80E0004B010BD00F08BFE9DF80E00DB
+:1025A000241D6B466A46E1B24FF6544000F089FEA6
+:1025B0009DF80E0004B010BD00F083FE9DF80E00E3
 :1025C00005B000BDF8B500F00BF84FF65A40F3E740
 :1025D000F8B500F10C026B4621214FF66640EBE79F
 :1025E0006B46002200217047F8B500F10C026B46E3
 :1025F0000F214FF66840DFE700B587B000F010F814
 :10260000012003220690ADF80420ADF8062000F06A
 :1026100011F800284CBFFF209DF8000007B000BD56
-:1026200000208DF800001822002101A800F0A6BEAD
+:1026200000208DF800001822002101A800F09EBEB5
 :1026300003900691CDF814D0002101A8FFF713BE36
 :1026400018B50C46C7B0114600228DF800208DF851
-:102650001C008DF81D4022460DF11E0000F088FE82
+:102650001C008DF81D4022460DF11E0000F080FE8A
 :1026600000F02AF83F200C21ADF80400ADF8061068
 :1026700007A8012103900691A41C049400F02CF8F3
 :1026800000284CBFFF209DF8000048B010BD00B5E9
 :10269000C7B000F00AF80F2000F013F800284CBF74
 :1026A000FF209DF8000047B000BD00228DF80020FB
 :1026B0008DF81C008DF81D101822002101A800F0D3
-:1026C0005DBEADF8060007A9022004903F2201205C
+:1026C00055BEADF8060007A9022004903F22012064
 :1026D00003910690ADF80420CDF814D0002101A894
 :1026E000FFF7C1BD00B587B000208DF8000000F0F5
 :1026F000E0F840F20110ADF806003F2201200690FC
@@ -628,12 +628,12 @@
 :102720001E4608BF022003D002280CBF1020002044
 :102730000DF11D010C1800F036F8012F8DF81C70FA
 :1027400002D0022F18D019E002273A4641460DF177
-:102750001D0000F00DFE2570667000F0AAF83F2005
+:102750001D0000F005FE2570667000F0AAF83F200D
 :102760004FF4817100F016F8FF1C049700F0B8F8E0
 :10277000002805D5FF2009E01027E6E7472005E0FF
 :102780009DF8000010B94E9800F067F8FFE748B0D8
 :10279000BDE8F081ADF80400ADF8061007A80321EC
-:1027A00003900691704703220021684600F0E6BDC1
+:1027A00003900691704703220021684600F0DEBDC9
 :1027B0002DE9F64F0C460546012CC7B09B4608BFD5
 :1027C000022003D0022C0CBF102000200DF11F01AD
 :1027D0000E18FFF7E8FF012CADF81C508DF81E40D5
@@ -647,10 +647,10 @@
 :1028500000F003F849B0BDE8F08FBDF80110018029
 :102860000020704730B5C7B01C464A9B00F026F8E0
 :1028700000258DF800508DF82140224619460DF1B3
-:10288000220000F075FD00F014F83F204FF4837132
+:10288000220000F06DFD00F014F83F204FF483713A
 :1028900000F01BF8A41D049400F022F800284CBF9F
 :1028A000FF209DF8000047B030BD0DF11F0000F083
-:1028B0005FBD1822002101A800F060BDADF81C002A
+:1028B00057BD1822002101A800F058BDADF81C003A
 :1028C000ADF81E108DF820207047ADF80400ADF86B
 :1028D000061007A80121039006917047ADF8042067
 :1028E000CDF814D0002101A8FFF7BDBC2DE9F84DAB
@@ -661,11 +661,11 @@
 :1029300000F0ECF8574406910D37049700F0CEF8FC
 :1029400000284CBFFF209DF8000048B0BDE8F08D86
 :1029500088F800A007AC5499E419524608F1010028
-:10296000544400F005BD8DF82320174652998DF888
-:1029700000B00DF1240809A8B84400F0F9BC00B576
+:10296000544400F0FDBC8DF82320174652998DF891
+:1029700000B00DF1240809A8B84400F0F1BC00B57E
 :10298000C7B000F00CF8852000F090F800F0A3F834
 :1029900000284CBFFF209DF8000047B000BD00217B
-:1029A0008DF81C008DF80010182201A800F0E6BC7C
+:1029A0008DF81C008DF80010182201A800F0DEBC84
 :1029B0002DE9F841C7B04FF0000800F026F80DF1FE
 :1029C0002300DDF844E14E9F4F9E509D529C8DF8B0
 :1029D0001F30C0F800E08DF800808DF820708DF871
@@ -678,18 +678,18 @@
 :102A400053F8002848BFFF200ED49DF8000058B965
 :102A50004F994E98BDF801202280BDF803200280D6
 :102A6000BDF805000880002049B0F0BD0722002114
-:102A7000684600F083BC18B5C7B0044600F01EF8E5
+:102A7000684600F07BBC18B5C7B0044600F01EF8ED
 :102A80008DF81C40224600F049F800F01BF83F206A
 :102A90008E2100F04AF8641C049400F01FF800280E
 :102AA0004CBFFF209DF8000048B010BDADF80600F7
 :102AB00007A901203F2203910490704700208DF860
-:102AC000000070471822002101A800F057BC0490B4
+:102AC000000070471822002101A800F04FBC0490BC
 :102AD0003F22012003910690ADF80420CDF814D0D8
 :102AE000002101A8FFF7BFBBADF80800059108A8B9
 :102AF000072104900791CDF818D0002102A8FFF714
-:102B0000B2BB1822002102A800F038BCADF80400C6
+:102B0000B2BB1822002102A800F030BCADF80400CE
 :102B1000ADF8061007A80121039070470DF11D00C4
-:102B200000F026BC48B0BDE8F081ADF80400ADF877
+:102B200000F01EBC48B0BDE8F081ADF80400ADF87F
 :102B3000061007A801210390069170471C49002048
 :102B4000087700221B48027000F036B818490A7F47
 :102B500041F82200087F401C0877704770B5044692
@@ -701,8 +701,8 @@
 :102BB00028130020E813002080B5C046C046C04658
 :102BC000C046C046C046C046C046C046C046C046D5
 :102BD000C046C046C046C046C046C046C046C046C5
-:102BE000C046C046C046C046C04600F00DFCC046C8
-:102BF000C046C046C046BDE8014000F07DBC0000B4
+:102BE000C046C046C046C046C04600F005FCC046D0
+:102BF000C046C046C046BDE8014000F075BC0000BC
 :102C0000DFF800F0891000202DE9F0413C4F064626
 :102C100038780128884614461D4608BF02201BD07C
 :102C2000012139700020786000F018F8010011D1FE
@@ -720,183 +720,183 @@
 :102CE000EDD4002070BD10B506490C6844F0010415
 :102CF0000C6040F8042BBFF36F8F036010BD000021
 :102D0000601300201440005810400058084000583C
-:102D100023016745AB89EFCD2DE9F04100F05CF868
-:102D2000884608BF022055D000F05BF800F05EF83E
-:102D300001004DD12968DFF8D470042908D17869E1
-:102D400040F4803040F00400786100F04FF819E062
-:102D50004FF0FF31C8F800106E6800E0761C69681B
-:102D6000AA6851188E4208D2304600F043F800F0AD
-:102D70003DF80100F2D0C8F800607A69DFF89010E1
-:102D80000A407A6139688A050FD53A6822F40072E0
-:102D90003A60396841F4006139603A6822F40062AF
-:102DA0003A60396841F4007139603A6851050FD5CD
-:102DB000396821F4806139603A6842F480523A609F
-:102DC000396821F4805139603A6842F480623A608F
-:102DD00000212170BDE8F0810F4C054620780128C4
-:102DE0007047002001216060217070474FF47A70B5
-:102DF000FFF750BF07490A6822F4FF6242EAC002A7
-:102E000042F4803242F002020A60704700400058EB
-:102E100005F8FFFF144000586013002001460648E3
-:102E2000064AC3798B4218BF904218BF0838F8D1C0
-:102E30008B4218BF00207047F873FF1F0070FF1F00
-:102E40000249016002490161704700BF0D2F00086F
-:102E5000372F0008006040607047EFF3108172B6B2
-:102E6000026882420CBF012000201CE0EFF31082B8
-:102E700072B603680B60486001600868416023E037
-:102E8000EFF3108272B6086043684B604160486897
-:102E9000016019E0EFF3108172B6436802681A60AE
-:102EA00042680068426081F31088704710B5EFF304
-:102EB000108472B602680A600068FFE7FFF7EAFF55
-:102EC00084F3108810BD086082F3108870470000FA
-:102ED00000F088BB6C486D49016001F1200242603E
-:102EE00001F13002826001F13C02026201F1440210
-:102EF000C26001F14C02026101F16802426101F11C
-:102F00006C0282617831C16100F07EBB38B5044645
-:102F10005F4D05F11000FFF79DFF5B494868A16810
-:102F20000160E168C160456005F11001816000F059
-:102F300087FB58482DE080B553494A681368012043
-:102F4000187200F083FB002002BD38B5514C504D83
-:102F500007E0694605F11000FFF7A8FF0098216817
-:102F6000884705F11000FFF778FF0028F1D031BD48
-:102F700048484168084738B50446474D2846006030
-:102F800040604148C068A1680160456000F063FB93
-:102F900042482168016061684160002032BD80B50F
-:102FA0003949CA6813681020187200F05AFB0020D3
-:102FB00002BD3549CA68394910680B68184738B5E9
-:102FC000364C354D06E069462846FFF76FFF0098FE
-:102FD000616888472846FFF740FF0028F3D031BDDD
-:102FE00038B504462E4D2846006040602D480060EC
-:102FF000406025480069A1688160E168C1600561A1
-:103000002168016061684160216941616169816194
-:1030100031BD80B501462348FFF732FFBDE80240CD
-:103020000FF2050000F02DBB38B5174C1D4D08E020
-:1030300069462846FFF73AFF009920690069FFF7C3
-:103040001FFF2846FFF709FF0028F1D031BD10B55A
-:10305000154C2046006040600B4841690C60BDE89B
-:10306000104000F022BB1CB50F4C06E0694620461C
-:10307000FFF71CFF0098C046C0462046FFF7EDFE54
-:103080000028F3D013BD000000000320B80903207E
-:103090008C080320C8130020A4080320D0130020AC
-:1030A0003C0A0320C0130020440A0320BFF34F8FC3
-:1030B000284929480A6802F4E06202430A60BFF323
-:1030C0004F8F00BFFDE710B52448254C88B001683C
-:1030D00041F400410160FFF757F922490020FEF753
-:1030E00088FD00F006FB01210120FFF752F90020C6
-:1030F00000F034FC012000F031FC022000F02EFC36
-:10310000012000F052FC0121002000F064FCFFF7D8
-:10311000E1FE154A00210220FFF7B5F904F23C5008
-:103120000FF249010090019169460FF2450000F04D
-:103130007BF804F25470029004F5C96140F23C50EF
-:1031400005900391049402A8FFF74AFFFFF7C0FE21
-:1031500008B010BD0CED00E00400FA0508000058AE
-:103160002C000320E01200206B32000870470000A2
-:1031700070B50546686800F10B063188B1F5124F4D
-:1031800015D1002000F01CFCB0784FF0005478B945
-:103190002178022908BF20702FD000F0B9FA002151
-:1031A0000120FFF7F6F8FEF73DFE0120287070BD04
-:1031B0000020FFF7E1F9FF281FD028B1002000F020
-:1031C000F4FB00F01DF8FCE72078022809D100216B
-:1031D0002170FFF7F7F9002000F0E7FB00F010F88E
-:1031E000FCE70220207000210020FFF7D2F9002028
-:1031F00000F0DBFB00F004F8FCE7FFF757FF00BF2F
-:103200000121002000F046BC70474FF0FF30FFF76F
-:10321000D7B800210220FFF743B90220FFF762B9B7
-:103220000220FFF767B900007FB50C464D4D61687D
-:103230004D4EE8612962284600F050FC2468746015
-:1032400006F1080000604060012000F068F80120ED
-:103250003070296841B10FF2E9000FF2ED020090E1
-:1032600001920294684688477FBD1FB53E4C04F129
-:103270000800FFF7F2FD00BB2178F1B1694604F1C7
-:103280000800FFF713FE3748C16949B10098029062
-:1032900001228DF8042001A888479DF8040000E071
-:1032A00001202070207818B10098FFF7B2FE04E0EA
-:1032B000009904F10800FFF7D9FD04F10800FFF7B9
-:1032C000CCFD28B9207818B104F10800FFF7A1FF60
-:1032D0001FBD2DE9F04105460E4690461C460020D4
-:1032E00000F01DF8204F7868A0F80950C6723246E9
-:1032F00041460C30FEF710FF1A4A136900210020E6
-:10330000984748F2E800FFF78BFF79688A78D21C6B
-:1033100004F10800FEF700FFBDE8F04101201CB5F4
-:103320001049124C096A20B901B188470020207069
-:1033300013BD0120207011B1BDE81C40084713BD2A
-:103340000020FFF76ABF000010B50146064C04F1EB
-:103350000800FFF795FD04F10800BDE81040FFF7F5
-:1033600058BF00000413002088130020E913002038
-:1033700010B50446FEF7D0FE204610BD10B5044639
-:1033800010460A460146204600F0B2FB204610BD1A
-:103390001CB541780024FF2934D1B0F80310444A09
-:1033A00040F60143C91A02D016391AD02AE05388D0
-:1033B000B0F807105B1C99420BD100218DF8041066
-:1033C00000F10D0200920124B0F80B108DF80510E9
-:1033D00015E0D288521C914214D101248DF804408A
-:1033E00006E0117A71B11472032101248DF80410E2
-:1033F00000F10D020092B0F80B008DF80500684650
-:1034000000F0BAFB204616BD10B586B02948284CFE
-:10341000FFF79CFB0094082301220FF29C0102207D
-:10342000FFF777F9002104910191A01C05900A2271
-:1034300001230421039202930091042320880FF2B8
-:1034400088020221FFF7B4F9002104910291019151
-:10345000201D05900A22202103920091012320883B
-:103460000FF274020221FFF7A3F9A01D05900121BC
-:103470000491029100200A220190042103920091FC
-:10348000142320880FF260020221FFF791F9002037
-:10349000207206B010BD80B50091012204488188D9
-:1034A0000272012300880022FFF7DCF902BD000050
-:1034B000A4130020913300088FE5B3D52E7F4A98DE
-:1034C0002A487ACC20FE000019ED82AEED214C9DF9
-:1034D0004145228E22FE000019ED82AEED214C9D69
-:1034E0004145228E23FE000019ED82AEED214C9D58
-:1034F0004145228E24FE000070470000C06808404D
-:10350000884201D10120704700207047C0690840FF
-:10351000884201D1012070470020704710B5664CE9
-:1035200002212046FFF7F2FF38B16068C0438107EF
-:1035300003D5FFF744FD022018E001212046FFF7E4
-:10354000E5FF38B16068C043C10703D5FFF7FDFC54
-:1035500001200BE008212046FFF7D8FF38B1606852
-:10356000C043010703D5FFF77EFD0820A06010BD12
-:1035700010B5514C00F033F818B96068C0438103AE
-:1035800006D400F02CF830B96068C043810302D53E
-:10359000BDE810406EE0082100F022F870B96068C4
-:1035A000C04301030AD56068444940F400206060CC
-:1035B000086880474FF40020A06010BD202100F073
-:1035C0000FF858B96068C043810207D5606840F4BD
-:1035D00000106060BDE81040FFF7CABC10BD0221BA
-:1035E00020468BE73648016841F400710160354898
-:1035F000026842F40072026040BF20BF3248016896
-:1036000041F400410160704780B53048016841F4E1
-:1036100080110160006800F4801000900098264836
-:10362000016841F001010160026842F480320260E9
-:103630002C20FEF7F6F8BDE802402D20FEF7F1B889
-:1036400023480168490849000160704721494FF447
-:103650008030086070471E48016821F00201016057
-:1036600070471B484FF400314160016821F400317C
-:10367000016070471648016841F400310160FFF7AE
-:1036800098BC38B504460C4D08212846FFF736FF94
-:1036900030B10A480460686820F40020686031BDD9
-:1036A000A0474FF40021A96031BD0948016821F00D
-:1036B0000801016070470000000C0058E013002072
-:1036C000D4080058200800580C0400585000005836
-:1036D000040C0058080C0058484900E0484981B0E3
-:1036E0000A6802430A60096808400090009801B027
-:1036F000704780B500F028FB00F028FB41480168C6
-:1037000041F48031016000F033FBBDE801400EE080
-:1037100000B587B068460FF210211C22FEF70CFDA1
-:10372000FFF795FC6846FEF75FFF07B000BDF0B5F8
-:1037300085B068461421FDF75DFF002600250024B2
-:1037400000210FF2D40000EBC102907988B1136818
-:10375000B3F1904F08D02C4FBB4208D02B4FBB4247
-:1037600004BF9088044304E09088064301E09088F9
-:103770000543491C2229E4DB00200290012103209B
-:1037800003900191B0B288B100900120FFF7A4FF2F
-:103790000120FFF7A3FF69464FF09040FDF72EFF91
-:1037A0000022B1B24FF09040FDF7ECFFA8B280B11B
-:1037B00000900220FFF790FF0220FFF78FFF124ECC
-:1037C00069463046FDF71AFF0022A9B23046FDF7E0
-:1037D000D9FFA0B280B100900420FFF77DFF042044
-:1037E000FFF77CFF094D69462846FDF707FF0022D9
-:1037F000A1B22846FDF7C6FF05B0F0BD4C00005849
-:103800004C01005890080058000400480008004887
-:103810000020FDF760BB0000000000480100000030
+:102D100023016745AB89EFCD2DE9F04100F053F871
+:102D2000884608BF02204CD000F052F800F055F859
+:102D3000010044D12968DFF8C470022919D14FF08D
+:102D4000FF32C8F800206E6800E0761C6968AA6847
+:102D500051188E4208D2304600F043F800F03DF89A
+:102D60000100F2D0C8F800607A69DFF894100A40D8
+:102D70007A6139688A050FD53A6822F400723A60A0
+:102D8000396841F4006139603A6822F400623A60BF
+:102D9000396841F4007139603A6851050FD53968D6
+:102DA00021F4806139603A6842F480523A603968AF
+:102DB00021F4805139603A6842F480623A6000211F
+:102DC0002170BDE8F081104C05462078012870473D
+:102DD000002001216060217070474FF47A70FFF786
+:102DE00059BF08490A6822F4FF6242EAC00242F46D
+:102DF000803242F002020A60704700000040005832
+:102E000005F8FFFF144000586013002001460648F3
+:102E1000064AC3798B4218BF904218BF0838F8D1D0
+:102E20008B4218BF00207047F873FF1F0070FF1F10
+:102E30000249016002490161704700BFFD2E000890
+:102E4000272F0008006040607047EFF3108172B6D2
+:102E5000026882420CBF012000201CE0EFF31082C8
+:102E600072B603680B60486001600868416023E047
+:102E7000EFF3108272B6086043684B6041604868A7
+:102E8000016019E0EFF3108172B6436802681A60BE
+:102E900042680068426081F31088704710B5EFF314
+:102EA000108472B602680A600068FFE7FFF7EAFF65
+:102EB00084F3108810BD086082F31088704700000A
+:102EC00000F088BB6C486D49016001F1200242604E
+:102ED00001F13002826001F13C02026201F1440220
+:102EE000C26001F14C02026101F16802426101F12C
+:102EF0006C0282617831C16100F07EBB38B5044656
+:102F00005F4D05F11000FFF79DFF5B494868A16820
+:102F10000160E168C160456005F11001816000F069
+:102F200087FB58482DE080B553494A681368012053
+:102F3000187200F083FB002002BD38B5514C504D93
+:102F400007E0694605F11000FFF7A8FF0098216827
+:102F5000884705F11000FFF778FF0028F1D031BD58
+:102F600048484168084738B50446474D2846006040
+:102F700040604148C068A1680160456000F063FBA3
+:102F800042482168016061684160002032BD80B51F
+:102F90003949CA6813681020187200F05AFB0020E3
+:102FA00002BD3549CA68394910680B68184738B5F9
+:102FB000364C354D06E069462846FFF76FFF00980E
+:102FC000616888472846FFF740FF0028F3D031BDED
+:102FD00038B504462E4D2846006040602D480060FC
+:102FE000406025480069A1688160E168C1600561B1
+:102FF00021680160616841602169416161698161A5
+:1030000031BD80B501462348FFF732FFBDE80240DD
+:103010000FF2050000F02DBB38B5174C1D4D08E030
+:1030200069462846FFF73AFF009920690069FFF7D3
+:103030001FFF2846FFF709FF0028F1D031BD10B56A
+:10304000154C2046006040600B4841690C60BDE8AB
+:10305000104000F022BB1CB50F4C06E0694620462C
+:10306000FFF71CFF0098C046C0462046FFF7EDFE64
+:103070000028F3D013BD000000000320B80903208E
+:103080008C080320C8130020A4080320D0130020BC
+:103090003C0A0320C0130020440A0320BFF34F8FD3
+:1030A000284929480A6802F4E06202430A60BFF333
+:1030B0004F8F00BFFDE710B52448254C88B001684C
+:1030C00041F400410160FFF75FF922490020FEF75B
+:1030D00090FD00F006FB01210120FFF75AF90020C6
+:1030E00000F034FC012000F031FC022000F02EFC46
+:1030F000012000F052FC0121002000F064FCFFF7E9
+:10310000E1FE154A00210220FFF7BDF904F23C5010
+:103110000FF249010090019169460FF2450000F05D
+:103120007BF804F25470029004F5C96140F23C50FF
+:1031300005900391049402A8FFF74AFFFFF7C0FE31
+:1031400008B010BD0CED00E00400FA0508000058BE
+:103150002C000320E01200205B32000870470000C2
+:1031600070B50546686800F10B063188B1F5124F5D
+:1031700015D1002000F01CFCB0784FF0005478B955
+:103180002178022908BF20702FD000F0B9FA002161
+:103190000120FFF7FEF8FEF745FE0120287070BD04
+:1031A0000020FFF7E9F9FF281FD028B1002000F028
+:1031B000F4FB00F01DF8FCE72078022809D100217B
+:1031C0002170FFF7FFF9002000F0E7FB00F010F896
+:1031D000FCE70220207000210020FFF7DAF9002030
+:1031E00000F0DBFB00F004F8FCE7FFF757FF00BF3F
+:1031F0000121002000F046BC70474FF0FF30FFF780
+:10320000DFB800210220FFF74BB90220FFF76AB9AF
+:103210000220FFF76FB900007FB50C464D4D616885
+:103220004D4EE8612962284600F050FC2468746025
+:1032300006F1080000604060012000F068F80120FD
+:103240003070296841B10FF2E9000FF2ED020090F1
+:1032500001920294684688477FBD1FB53E4C04F139
+:103260000800FFF7F2FD00BB2178F1B1694604F1D7
+:103270000800FFF713FE3748C16949B10098029072
+:1032800001228DF8042001A888479DF8040000E081
+:1032900001202070207818B10098FFF7B2FE04E0FA
+:1032A000009904F10800FFF7D9FD04F10800FFF7C9
+:1032B000CCFD28B9207818B104F10800FFF7A1FF70
+:1032C0001FBD2DE9F04105460E4690461C460020E4
+:1032D00000F01DF8204F7868A0F80950C6723246F9
+:1032E00041460C30FEF718FF1A4A136900210020EE
+:1032F000984748F2E800FFF78BFF79688A78D21C7C
+:1033000004F10800FEF708FFBDE8F04101201CB5FC
+:103310001049124C096A20B901B188470020207079
+:1033200013BD0120207011B1BDE81C40084713BD3A
+:103330000020FFF76ABF000010B50146064C04F1FB
+:103340000800FFF795FD04F10800BDE81040FFF705
+:1033500058BF00000413002088130020E913002048
+:1033600010B50446FEF7D8FE204610BD10B5044641
+:1033700010460A460146204600F0B2FB204610BD2A
+:103380001CB541780024FF2934D1B0F80310444A19
+:1033900040F60143C91A02D016391AD02AE05388E0
+:1033A000B0F807105B1C99420BD100218DF8041076
+:1033B00000F10D0200920124B0F80B108DF80510F9
+:1033C00015E0D288521C914214D101248DF804409A
+:1033D00006E0117A71B11472032101248DF80410F2
+:1033E00000F10D020092B0F80B008DF80500684660
+:1033F00000F0BAFB204616BD10B586B02948284C0F
+:10340000FFF7A4FB0094082301220FF29C01022085
+:10341000FFF77FF9002104910191A01C05900A2279
+:1034200001230421039202930091042320880FF2C8
+:1034300088020221FFF7BCF9002104910291019159
+:10344000201D05900A22202103920091012320884B
+:103450000FF274020221FFF7ABF9A01D05900121C4
+:103460000491029100200A2201900421039200910C
+:10347000142320880FF260020221FFF799F900203F
+:10348000207206B010BD80B50091012204488188E9
+:103490000272012300880022FFF7E4F902BD000058
+:1034A000A4130020813300088FE5B3D52E7F4A98FE
+:1034B0002A487ACC20FE000019ED82AEED214C9D09
+:1034C0004145228E22FE000019ED82AEED214C9D79
+:1034D0004145228E23FE000019ED82AEED214C9D68
+:1034E0004145228E24FE000070470000C06808405D
+:1034F000884201D10120704700207047C069084010
+:10350000884201D1012070470020704710B5664CF9
+:1035100002212046FFF7F2FF38B16068C0438107FF
+:1035200003D5FFF744FD022018E001212046FFF7F4
+:10353000E5FF38B16068C043C10703D5FFF7FDFC64
+:1035400001200BE008212046FFF7D8FF38B1606862
+:10355000C043010703D5FFF77EFD0820A06010BD22
+:1035600010B5514C00F033F818B96068C0438103BE
+:1035700006D400F02CF830B96068C043810302D54E
+:10358000BDE810406EE0082100F022F870B96068D4
+:10359000C04301030AD56068444940F400206060DC
+:1035A000086880474FF40020A06010BD202100F083
+:1035B0000FF858B96068C043810207D5606840F4CD
+:1035C00000106060BDE81040FFF7CABC10BD0221CA
+:1035D00020468BE73648016841F4007101603548A8
+:1035E000026842F40072026040BF20BF32480168A6
+:1035F00041F400410160704780B53048016841F4F2
+:1036000080110160006800F4801000900098264846
+:10361000016841F001010160026842F480320260F9
+:103620002C20FEF7FEF8BDE802402D20FEF7F9B889
+:1036300023480168490849000160704721494FF457
+:103640008030086070471E48016821F00201016067
+:1036500070471B484FF400314160016821F400318C
+:10366000016070471648016841F400310160FFF7BE
+:1036700098BC38B504460C4D08212846FFF736FFA4
+:1036800030B10A480460686820F40020686031BDE9
+:10369000A0474FF40021A96031BD0948016821F01D
+:1036A0000801016070470000000C0058E013002082
+:1036B000D4080058200800580C0400585000005846
+:1036C000040C0058080C0058484900E0484981B0F3
+:1036D0000A6802430A60096808400090009801B037
+:1036E000704780B500F028FB00F028FB41480168D6
+:1036F00041F48031016000F033FBBDE801400EE091
+:1037000000B587B068460FF210211C22FEF714FDA9
+:10371000FFF795FC6846FEF767FF07B000BDF0B500
+:1037200085B068461421FDF765FF002600250024BA
+:1037300000210FF2D40000EBC102907988B1136828
+:10374000B3F1904F08D02C4FBB4208D02B4FBB4257
+:1037500004BF9088044304E09088064301E0908809
+:103760000543491C2229E4DB0020029001210320AB
+:1037700003900191B0B288B100900120FFF7A4FF3F
+:103780000120FFF7A3FF69464FF09040FDF736FF99
+:103790000022B1B24FF09040FDF7F4FFA8B280B123
+:1037A00000900220FFF790FF0220FFF78FFF124EDC
+:1037B00069463046FDF722FF0022A9B23046FDF7E8
+:1037C000E1FFA0B280B100900420FFF77DFF04204C
+:1037D000FFF77CFF094D69462846FDF70FFF0022E1
+:1037E000A1B22846FDF7CEFF05B0F0BD4C00005851
+:1037F0004C01005890080058000400480008004898
+:103800000020FDF768BB0000000000480100000038
+:103810000000004801000000000000480100000016
 :103820000000004801000000000000480100000006
 :1038300000000048010000000000004801000000F6
 :1038400000000048010000000000004801000000E6
@@ -912,187 +912,187 @@
 :1038E0000000004801000000000000480100000046
 :1038F0000000004801000000000000480100000036
 :103900000000004801000000000000480100000025
-:103910000000004801000000000000480100000015
-:10392000000000480100000000000000000000004E
-:10393000000000001838000824000320280003209D
-:1039400022040400DFF81C1181B00A6802430A60F7
-:10395000096808400090009801B0704778B585B0BC
-:10396000044600F07AF80220FFF7ECFF00F010F8B0
-:1039700000950120019000210220039002916946E8
-:1039800056F82400FDF73AFE00F009F806B070BDC5
-:103990000FF2E000DFF8D06030F81450704756F8AE
-:1039A000240000222946FDF7EDBE0FF2C801DFF822
-:1039B000B83031F8101053F820000122FDF7E2BEB4
-:1039C0000FF2B001DFF8A03031F8101053F82000EA
-:1039D0000022FDF7D7BEF0B585B005460C4600F0D5
-:1039E0003CF80DB9042004E0012D18BF022D02D1CE
-:1039F0000820FFF7A7FF2000DFF870600FF27C07B8
-:103A00000DD137F81500009000210191012002909E
-:103A10000221039100F01CF8012000F03BFA012C78
-:103A200014D137F8150000900121DFF8440001900F
-:103A3000029100F00DF80FF24C00445D00220F21BE
-:103A400060B2FDF7D1FE60B2FDF7EBFE05B0F0BD50
-:103A5000694656F82500FDF7D1BD68461421FDF7EB
-:103A6000C9BD00004C0000586C10002078100020E8
-:103A700000002110200001000200000010000100E1
-:103A8000020000000A0607001148016841F4807135
-:103A90000160704710B50C460E490028086805D132
-:103AA000810507D500F022FA20B110BD810558BF6D
-:103AB00000F016FA0848016821F00401012C0160A9
-:103AC00001D130BF10BD40BF20BF20BF10BD0000DE
-:103AD000000400581404005810ED00E00249016091
-:103AE00002490161704700BF772F00089F2F00082F
-:103AF00062F30F2262F31F42401810F0030308D054
-:103B0000C91A1FD3DB0748BF00F8012D28BF20F8D2
-:103B1000022D130030B414461546103928BF20E991
-:103B20003C00FAD8490728BF20E90C0048BF40F8FC
-:103B3000042D890028BF20F8022D48BF00F8012D70
-:103B400030BC7047C91818BF00F8012DCB0728BF3B
-:103B500000F8012D7047000000EB8100604AD0F8AA
-:103B60008010914201D0012070470020704742F43C
-:103B7000806240F8212070472DE9F8430546DFF8C0
-:103B800064912879DFF86081584E20B1012825D052
-:103B9000032869D010E029680A78012A4FF00060F4
-:103BA00004D0022A0AD0072A10D005E00022306093
-:103BB000727400F0ACF83274BDE8F183012130601A
-:103BC000717400F0A4F800203074F5E701228DF83C
-:103BD000002069460220FFF75EFCEDE76C790027C4
-:103BE00002214046FFF7B8FF0028F9D1FFF739F866
-:103BF00022E0296806F1080339441844FEF78CFADC
-:103C000000F07EF8D6E9022331680120FEF7FCFFC0
-:103C1000D6F800C0D6E90201DCE900238B4208BFD8
-:103C2000824209D10CF108003060307CC0F10800FC
-:103C3000241AC71900203074307CC0F10802944265
-:103C4000D7D2FFF71CF800F057F8002CB4D0286842
-:103C5000337CC11906F1080022461844FEF75CFACD
-:103C6000307C24183474A7E7307CD0B10221404660
-:103C7000FFF772FF0028F9D1FEF7F3FF04E000F030
-:103C80003FF80120FEF7C0FF3168D6E90223D1E9F1
-:103C900000459D4208BF9442F1D1FEF7F0FF00F0CD
-:103CA0002BF8707C90B1012886D14FF00051002094
-:103CB0000870BFF34F8F0E490E480A6802F4E062A5
-:103CC00002430A60BFF34F8F00BFFDE7FEF754FCCD
-:103CD0000020FEF751FC01210020FFF7DBFEFAE790
-:103CE00000040080104000580014005848130020C1
-:103CF0000CED00E00400FA0500220221404636E700
-:103D0000D9F80000C00C10F00100F9D17047286804
-:103D1000C178317029688878707028684178B170EE
-:103D200070470000032010B5FDF751FD0F2000F093
-:103D3000FFF80024002814BF012400F017F82046E3
-:103D400010BD084880687047074805E006480168CC
-:103D500041F0020101607047016841F0010101601A
-:103D60007047000060100020042004E0704700004D
-:103D700080B5FFF74DFD022100910023044800F1BA
-:103D800024014FF48052001D00F0F4F801BD000042
-:103D90001400002010B5FFF7C5FF4A4C60684001D1
-:103DA0000ED56068C0000BD4FFF76EFEFFF76CFE07
-:103DB000206840F480302060216821F48031216047
-:103DC00000F022F8FFF760FEFFF75EFE206840F08B
-:103DD0000100206020688007FCD50022606820F484
-:103DE000404040F4804060603748016802600269EA
-:103DF00002F05002026100F028F8FFF764F94FF07A
-:103E0000FF30FEF7DDFAFAE7304881B0016841F48F
-:103E1000801101603F21006800F48010009000983C
-:103E20002B4841604161016841F47C1101600269E5
-:103E300042F47C120261016841F03F0101600269B5
-:103E400042F03F02026101B0704710B5FFF71CFE5F
-:103E5000FFF71AFE1B481F4C016821F4407141F422
-:103E6000807101600F21026842F4004202601A482A
-:103E7000816047F6FF71C160046000F08FF8CA20CE
-:103E80006062FF2153206062A068C008C000A0608B
-:103E9000616210BD38B50446FDF7A6FB14F1010FB1
-:103EA000054609D0FFF74DFF041905E00B480168EE
-:103EB00021F00401016030BFFDF796FB401BA042DA
-:103EC000F4D331BD900000588008005850000058CD
-:103ED000040C005800280040E012002010ED00E023
-:103EE0001048016841F480410160704710B50D4AE7
-:103EF0000D4B106820F48040106032211C680B4884
-:103F0000B4FBF0F0484351698B0506D5002818BF73
-:103F1000401EF8D101E0002010BD50698105FAD59E
-:103F2000032010BD000400588410002040420F0000
-:103F300070B50F4E0446B0680025A8B1FDF709FA28
-:103F4000B2684FF47A71B1FBF2F1B0FBF1F0FDF71A
-:103F500082FC48B9102C07D2002221464FF0FF30D6
-:103F6000FDF742FC746000E00125284670BD00BFEB
-:103F70006010002010B5029C016042600021C16009
-:103F80000161416181610381A107047704D5008942
-:103F900010B14FF0FF3010BD002010BD38B5040047
-:103FA00044D094F8210028B9002184F8201020463C
-:103FB000C046C04600F049F8FF2510B100F03FF8B8
-:103FC00034E02168DFF8B0008A6802408A60216826
-:103FD0008A68636820690343A06903431A438A60BF
-:103FE0002168E068086120680169A26841EA02412D
-:103FF00001612068C16821F08001C1602068C16C46
-:1040000089088900C1642168CA6CE3696069034357
-:104010001A43CA6420688168880609D400F020F831
-:1040200030B120684562042100F01FF8012032BD44
-:1040300020684562012184F82110002032BD2068EB
-:104040004562042184F821107047022084F8210081
-:10405000CA2021684862532022685062204626E028
-:1040600020460BE02068C0F8248084F8211000204E
-:1040700084F8200070470000BFFF8FFF70B5044632
-:1040800040F2E9362068C16821F0A001C160FDF767
-:10409000ABFA05462068C168880606D4FDF7A4FA85
-:1040A000401BB042F6D3032070BD002070BD70B538
-:1040B00004462068C1684A0612D44FF0FF32C2603D
-:1040C00040F2E936FDF790FA05462068C1684806D7
-:1040D00006D4FDF789FA401BB042F6D3032070BD29
-:1040E000002070BD4748484A01681268B1F1006F6E
-:1040F0000AD3120302F47F22444882188A4203D36F
-:1041000008684349884201D0002070470120704769
-:1041100080B5404940480860016881F308884068DC
-:10412000804730BF01BD10B5FFF7DCFF4FF00054F2
-:1041300020B100202070BDE81040E9E70120207088
-:1041400007206070FF20A07010BD38B5334C206888
-:10415000C00002D4206880011AD54FF0005528789D
-:1041600028B9FFF7BFFF10B1FFF7D2FF12E02878A0
-:1041700048B9FFF7B7FF30B90120287007206870F1
-:10418000FF20A87006E02878012818BF022801D077
-:10419000FFF7C9FF2248016841F470010160002067
-:1041A000FEF73CFE40B180791E49A160A16821F470
-:1041B0007C5141EA0021A1604FF0B040016841F418
-:1041C0008031016018490A68D208D20042F0010229
-:1041D0000A600A6802F00702012AFAD1016889031D
-:1041E000FCD581688908890041F0020181608168FD
-:1041F00001F00C010829FAD1016849084900016061
-:1042000031BD00004071000880400058FCFFFF07EE
-:10421000298A449408ED00E00070000894000058DA
-:1042200088ED00E0FECAFECA004000580100000010
-:104230000300000005000000010000000100000074
-:10424000060000000A00000020000000020000003C
-:104250000400000008000000100000004000000002
-:10426000800000000001000000020000A0860100A4
-:10427000400D0300801A060000350C0040420F007C
-:1042800080841E0000093D0000127A000024F40022
-:1042900000366E010048E801006CDC0200000000FE
-:1042A00000000000000000000000000019E050F8CD
-:1042B000042BD30744BFA9F101039A18091F002357
-:1042C000042942F8043BF9D25FEA817C134604D505
-:1042D0004FF0000CA2F800C09B1CC90744BF00218E
-:1042E000197050F8041B0029E1D1704730B50168FE
-:1042F00084684218416802EB5103C9070BD54C444E
-:1043000009E012F9011B12F8015B002904F8015BB6
-:1043100005D5491CF9D19A42F3D10C3030BD491E64
-:10432000F1D5F8E710B5074979441831064C7C44BB
-:10433000163404E00A68081D114488470146A1426A
-:10434000F8D110BD64000000980000007047FEE73F
-:1043500070477047704700F00DB80020FCF7D1BDE2
-:104360000020FCF7D4BDFDF7F4BBFFF701B9FFF760
-:10437000D5B8000002490A68886882180A60704748
-:10438000601000204EF68851CEF20001086840F41B
-:1043900070000860BFF34F8FBFF36F8F4FF0007056
-:1043A000E1EE100A7047000005FFFFFF3403000034
-:1043B000B8100020800800002C000320000000003E
-:1043C0002DFFFFFF900100004601000004000020C7
-:1043D0001DFFFFFF23020000040000002400032053
-:1043E00000000000000000000000000000000000CD
-:1043F00001000000020000000300000004000000B3
-:104400000120C046002801D0FFF78CFFAFF30080E9
-:104410000020AFF30080FFF7BDFC00F000F800F0D3
-:1044200001B800000746384600F002F8FBE700003C
-:1044300080B5AFF30080024A11001820ABBEFBE745
-:104440002600020001488047014800474B41000810
-:1044500055440008AFF30080FFF794FFFFF7D0FF4B
+:10391000000000480100000000000000000000005E
+:1039200000000000083800082400032028000320BD
+:1039300022040400DFF81C1181B00A6802430A6007
+:10394000096808400090009801B0704778B585B0CC
+:10395000044600F07AF80220FFF7ECFF00F010F8C0
+:1039600000950120019000210220039002916946F8
+:1039700056F82400FDF742FE00F009F806B070BDCD
+:103980000FF2E000DFF8D06030F81450704756F8BE
+:10399000240000222946FDF7F5BE0FF2C801DFF82A
+:1039A000B83031F8101053F820000122FDF7EABEBC
+:1039B0000FF2B001DFF8A03031F8101053F82000FA
+:1039C0000022FDF7DFBEF0B585B005460C4600F0DD
+:1039D0003CF80DB9042004E0012D18BF022D02D1DE
+:1039E0000820FFF7A7FF2000DFF870600FF27C07C8
+:1039F0000DD137F8150000900021019101200290AF
+:103A00000221039100F01CF8012000F03BFA012C88
+:103A100014D137F8150000900121DFF8440001901F
+:103A2000029100F00DF80FF24C00445D00220F21CE
+:103A300060B2FDF7D9FE60B2FDF7F3FE05B0F0BD50
+:103A4000694656F82500FDF7D9BD68461421FDF7F3
+:103A5000D1BD00004C0000586C10002078100020F0
+:103A600000002110200001000200000010000100F1
+:103A7000020000000A0607001148016841F4807145
+:103A80000160704710B50C460E490028086805D142
+:103A9000810507D500F022FA20B110BD810558BF7D
+:103AA00000F016FA0848016821F00401012C0160B9
+:103AB00001D130BF10BD40BF20BF20BF10BD0000EE
+:103AC000000400581404005810ED00E002490160A1
+:103AD00002490161704700BF672F00088F2F00085F
+:103AE00062F30F2262F31F42401810F0030308D064
+:103AF000C91A1FD3DB0748BF00F8012D28BF20F8E3
+:103B0000022D130030B414461546103928BF20E9A1
+:103B10003C00FAD8490728BF20E90C0048BF40F80C
+:103B2000042D890028BF20F8022D48BF00F8012D80
+:103B300030BC7047C91818BF00F8012DCB0728BF4B
+:103B400000F8012D7047000000EB8100604AD0F8BA
+:103B50008010914201D0012070470020704742F44C
+:103B6000806240F8212070472DE9F8430546DFF8D0
+:103B700064912879DFF86081584E20B1012825D062
+:103B8000032869D010E029680A78012A4FF0006004
+:103B900004D0022A0AD0072A10D005E000223060A3
+:103BA000727400F0ACF83274BDE8F183012130602A
+:103BB000717400F0A4F800203074F5E701228DF84C
+:103BC000002069460220FFF75EFCEDE76C790027D4
+:103BD00002214046FFF7B8FF0028F9D1FFF741F86E
+:103BE00022E0296806F1080339441844FEF794FAE4
+:103BF00000F07EF8D6E9022331680120FFF704F8CF
+:103C0000D6F800C0D6E90201DCE900238B4208BFE8
+:103C1000824209D10CF108003060307CC0F108000C
+:103C2000241AC71900203074307CC0F10802944275
+:103C3000D7D2FFF724F800F057F8002CB4D028684A
+:103C4000337CC11906F1080022461844FEF764FAD5
+:103C5000307C24183474A7E7307CD0B10221404670
+:103C6000FFF772FF0028F9D1FEF7FBFF04E000F038
+:103C70003FF80120FEF7C8FF3168D6E90223D1E9F9
+:103C800000459D4208BF9442F1D1FEF7F8FF00F0D5
+:103C90002BF8707C90B1012886D14FF000510020A4
+:103CA0000870BFF34F8F0E490E480A6802F4E062B5
+:103CB00002430A60BFF34F8F00BFFDE7FEF75CFCD5
+:103CC0000020FEF759FC01210020FFF7DBFEFAE798
+:103CD00000040080104000580014005848130020D1
+:103CE0000CED00E00400FA0500220221404636E710
+:103CF000D9F80000C00C10F00100F9D17047286815
+:103D0000C178317029688878707028684178B170FE
+:103D100070470000032010B5FDF759FD0F2000F09B
+:103D2000FFF80024002814BF012400F017F82046F3
+:103D300010BD084880687047074805E006480168DC
+:103D400041F0020101607047016841F0010101602A
+:103D50007047000060100020042004E0704700005D
+:103D600080B5FFF74DFD022100910023044800F1CA
+:103D700024014FF48052001D00F0F4F801BD000052
+:103D80001400002010B5FFF7C5FF4A4C60684001E1
+:103D90000ED56068C0000BD4FFF76EFEFFF76CFE17
+:103DA000206840F480302060216821F48031216057
+:103DB00000F022F8FFF760FEFFF75EFE206840F09B
+:103DC0000100206020688007FCD50022606820F494
+:103DD000404040F4804060603748016802600269FA
+:103DE00002F05002026100F028F8FFF764F94FF08A
+:103DF000FF30FEF7E5FAFAE7304881B0016841F498
+:103E0000801101603F21006800F48010009000984C
+:103E10002B4841604161016841F47C1101600269F5
+:103E200042F47C120261016841F03F0101600269C5
+:103E300042F03F02026101B0704710B5FFF71CFE6F
+:103E4000FFF71AFE1B481F4C016821F4407141F432
+:103E5000807101600F21026842F4004202601A483A
+:103E6000816047F6FF71C160046000F08FF8CA20DE
+:103E70006062FF2153206062A068C008C000A0609B
+:103E8000616210BD38B50446FDF7AEFB14F1010FB9
+:103E9000054609D0FFF74DFF041905E00B480168FE
+:103EA00021F00401016030BFFDF79EFB401BA042E2
+:103EB000F4D331BD900000588008005850000058DD
+:103EC000040C005800280040E012002010ED00E033
+:103ED0001048016841F480410160704710B50D4AF7
+:103EE0000D4B106820F48040106032211C680B4894
+:103EF000B4FBF0F0484351698B0506D5002818BF84
+:103F0000401EF8D101E0002010BD50698105FAD5AE
+:103F1000032010BD000400588410002040420F0010
+:103F200070B50F4E0446B0680025A8B1FDF711FA30
+:103F3000B2684FF47A71B1FBF2F1B0FBF1F0FDF72A
+:103F40008AFC48B9102C07D2002221464FF0FF30DE
+:103F5000FDF74AFC746000E00125284670BD00BFF3
+:103F60006010002010B5029C016042600021C16019
+:103F70000161416181610381A107047704D5008952
+:103F800010B14FF0FF3010BD002010BD38B5040057
+:103F900044D094F8210028B9002184F8201020464C
+:103FA000C046C04600F049F8FF2510B100F03FF8C8
+:103FB00034E02168DFF8B0008A6802408A60216836
+:103FC0008A68636820690343A06903431A438A60CF
+:103FD0002168E068086120680169A26841EA02413D
+:103FE00001612068C16821F08001C1602068C16C56
+:103FF00089088900C1642168CA6CE3696069034368
+:104000001A43CA6420688168880609D400F020F841
+:1040100030B120684562042100F01FF8012032BD54
+:1040200020684562012184F82110002032BD2068FB
+:104030004562042184F821107047022084F8210091
+:10404000CA2021684862532022685062204626E038
+:1040500020460BE02068C0F8248084F8211000205E
+:1040600084F8200070470000BFFF8FFF70B5044642
+:1040700040F2E9362068C16821F0A001C160FDF777
+:10408000B3FA05462068C168880606D4FDF7ACFA85
+:10409000401BB042F6D3032070BD002070BD70B548
+:1040A00004462068C1684A0612D44FF0FF32C2604D
+:1040B00040F2E936FDF798FA05462068C1684806DF
+:1040C00006D4FDF791FA401BB042F6D3032070BD31
+:1040D000002070BD4748484A01681268B1F1006F7E
+:1040E0000AD3120302F47F22444882188A4203D37F
+:1040F00008684349884201D000207047012070477A
+:1041000080B5404940480860016881F308884068EC
+:10411000804730BF01BD10B5FFF7DCFF4FF0005402
+:1041200020B100202070BDE81040E9E70120207098
+:1041300007206070FF20A07010BD38B5334C206898
+:10414000C00002D4206880011AD54FF000552878AD
+:1041500028B9FFF7BFFF10B1FFF7D2FF12E02878B0
+:1041600048B9FFF7B7FF30B9012028700720687001
+:10417000FF20A87006E02878012818BF022801D087
+:10418000FFF7C9FF2248016841F470010160002077
+:10419000FEF73CFE40B180791E49A160A16821F480
+:1041A0007C5141EA0021A1604FF0B040016841F428
+:1041B0008031016018490A68D208D20042F0010239
+:1041C0000A600A6802F00702012AFAD1016889032D
+:1041D000FCD581688908890041F00201816081680D
+:1041E00001F00C010829FAD1016849084900016071
+:1041F00031BD00004071000880400058FCFFFF07FF
+:10420000298A449408ED00E00070000894000058EA
+:1042100088ED00E0FECAFECA004000580100000020
+:104220000300000005000000010000000100000084
+:10423000060000000A00000020000000020000004C
+:104240000400000008000000100000004000000012
+:10425000800000000001000000020000A0860100B4
+:10426000400D0300801A060000350C0040420F008C
+:1042700080841E0000093D0000127A000024F40032
+:1042800000366E010048E801006CDC02000000000E
+:1042900000000000000000000000000019E050F8DD
+:1042A000042BD30744BFA9F101039A18091F002367
+:1042B000042942F8043BF9D25FEA817C134604D515
+:1042C0004FF0000CA2F800C09B1CC90744BF00219E
+:1042D000197050F8041B0029E1D1704730B501680E
+:1042E00084684218416802EB5103C9070BD54C445E
+:1042F00009E012F9011B12F8015B002904F8015BC7
+:1043000005D5491CF9D19A42F3D10C3030BD491E74
+:10431000F1D5F8E710B5074979441831064C7C44CB
+:10432000163404E00A68081D114488470146A1427A
+:10433000F8D110BD64000000980000007047FEE74F
+:1043400070477047704700F00DB80020FCF7D9BDEA
+:104350000020FCF7DCBDFDF7FCBBFFF701B9FFF760
+:10436000D5B8000002490A68886882180A60704758
+:10437000601000204EF68851CEF20001086840F42B
+:1043800070000860BFF34F8FBFF36F8F4FF0007066
+:10439000E1EE100A7047000005FFFFFF3403000044
+:1043A000B8100020800800002C000320000000004E
+:1043B0002DFFFFFF900100004601000004000020D7
+:1043C0001DFFFFFF23020000040000002400032063
+:1043D00000000000000000000000000000000000DD
+:1043E00001000000020000000300000004000000C3
+:1043F0000120C046002801D0FFF78CFFAFF30080FA
+:104400000020AFF30080FFF7BDFC00F000F800F0E3
+:1044100001B800000746384600F002F8FBE700004C
+:1044200080B5AFF30080024A11001820ABBEFBE755
+:104430002600020001488047014800473B41000830
+:1044400045440008AFF30080FFF794FFFFF7D0FF6B
+:10445000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF90
 :10446000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF80
 :10447000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF70
 :10448000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF60
@@ -1107,17 +1107,16 @@
 :10451000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFCF
 :10452000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFBF
 :10453000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFAF
-:10454000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF9F
-:10455000FFF7FEBF030DFF0186F40000018100811B
+:10454000FFF7FEBF030DFF0186F40000018100812B
+:104550000081008100810081008100810081008153
 :104560000081008100810081008100810081008143
 :104570000081008100810081008100810081008133
-:104580000081008100810081008100810081008123
-:1045900000810081008100810081008100A900F874
-:1045A000FFF0000010FD000001FC004A040048007C
-:1045B0000400480004004800080048000C004800BF
-:1045C0000C004800093D0030B50A4B5A6842F4809F
-:1045D000225A60EFF3108472B6802251F8045B40D7
-:1045E000F8045B521EF9D11868C103FCD484F3109F
-:0945F0008830BD10400058F800AD
-:040000050800445556
+:1045800000810081008100810081008100A900F884
+:10459000FFF0000010FD000001FC004A040048008C
+:1045A0000400480004004800080048000C004800CF
+:1045B0000C004800093D0030B50A4B5A6842F480AF
+:1045C000225A60EFF3108472B6802251F8045B40E7
+:1045D000F8045B521EF9D11868C103FCD484F310AF
+:0945E0008830BD10400058F800BD
+:040000050800444566
 :00000001FF
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/Core/Inc/hw_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/Core/Inc/hw_conf.h
index 82121292b..078755183 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/Core/Inc/hw_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/Core/Inc/hw_conf.h
@@ -23,9 +23,37 @@
 #define __HW_CONF_H
 
 /******************************************************************************
- * Semaphores
- * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
- *****************************************************************************/
+* Semaphores
+* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
+*****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
 /* Index of the semaphore used to manage the entry Stop Mode procedure */
 #define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/Core/Src/app_debug.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/Core/Src/app_debug.c
index 793fb3e2c..246173ae6 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/Core/Src/app_debug.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/Core/Src/app_debug.c
@@ -36,20 +36,6 @@ typedef PACKED_STRUCT
   uint8_t reserved;
 } APPD_GpioConfig_t;
 
-typedef PACKED_STRUCT
-{
-  uint8_t thread_config;
-  uint8_t ble_config;
-  uint8_t mac_802_15_4;
-  uint8_t reserved;
-} APPD_TracesConfig_t;
-
-typedef PACKED_STRUCT
-{
-  uint8_t ble_dtb_cfg;
-  uint8_t reserved[3];
-} APPD_GeneralConfig_t;
-
 /* Private defines -----------------------------------------------------------*/
 #define GPIO_NBR_OF_RF_SIGNALS                  9
 #define GPIO_CFG_NBR_OF_FEATURES                34
@@ -63,8 +49,8 @@ typedef PACKED_STRUCT
 
 /* Private macros ------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static APPD_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
-PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static APPD_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
 
 /**
  * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
@@ -124,15 +110,15 @@ static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
 #if( BLE_DTB_CFG == 7)
 static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
 {
-    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 */
-    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 */
-    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 */
-    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 */
-    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 */
-    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 */
-    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 */
-    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 */
-    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 */
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
 };
 #endif
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/Core/Src/stm32_lpm_if.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/Core/Src/stm32_lpm_if.c
index f024b61e3..1418e0a36 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/Core/Src/stm32_lpm_if.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/Core/Src/stm32_lpm_if.c
@@ -70,6 +70,13 @@ static void Switch_On_HSI( void );
 void PWR_EnterOffMode( void )
 {
 /* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
   /************************************************************************************
    * ENTER OFF MODE
    ***********************************************************************************/
@@ -106,6 +113,8 @@ void PWR_ExitOffMode( void )
 {
 /* USER CODE BEGIN PWR_ExitOffMode */
 
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitOffMode */
 }
 
@@ -118,6 +127,16 @@ void PWR_ExitOffMode( void )
 void PWR_EnterStopMode( void )
 {
 /* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
   /**
    * This function is called from CRITICAL SECTION
    */
@@ -202,6 +221,9 @@ void PWR_ExitStopMode( void )
 
   /* Release RCC semaphore */
   LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitStopMode */
 }
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/EWARM/startup_stm32wb55xx_cm4.s b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/EWARM/startup_stm32wb55xx_cm4.s
index 79b0e7edd..1f886ff59 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/EWARM/startup_stm32wb55xx_cm4.s
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/EWARM/startup_stm32wb55xx_cm4.s
@@ -1,4 +1,4 @@
-;/********************* COPYRIGHT(c) 2019 STMicroelectronics ********************
+;******************************************************************************
 ;* File Name          : startup_stm32wb55xx_cm4.s
 ;* Author             : MCD Application Team
 ;* Description        : M4 core vector table of the STM32WB55xx devices for the
@@ -13,31 +13,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
 ;*
-;*******************************************************************************
+;******************************************************************************
 ;
 ;
 ; The modules in this file are included in the libraries, and may be replaced
@@ -86,10 +73,10 @@ __vector_table
         DCD     PendSV_Handler                    ; PendSV Handler
         DCD     SysTick_Handler                   ; SysTick Handler
 
-         ; External Interrupts
+        ; External Interrupts
         DCD     WWDG_IRQHandler                   ; Window WatchDog
-        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
-        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
         DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
         DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
         DCD     RCC_IRQHandler                    ; RCC Interrupt
@@ -129,7 +116,7 @@ __vector_table
         DCD     TSC_IRQHandler                    ; TSC Interrupt
         DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
         DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
-        DCD     USB_FS_WKUP_CRS_IRQHandler        ; USB Full speed wakeup
+        DCD     CRS_IRQHandler                    ; CRS interrupt
         DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
         DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
         DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
@@ -156,6 +143,7 @@ __vector_table
 ;; Default interrupt handlers.
 ;;
         THUMB
+
         PUBWEAK Reset_Handler
         SECTION .text:CODE:NOROOT:REORDER(2)
 Reset_Handler
@@ -419,10 +407,10 @@ EXTI15_10_IRQHandler
 RTC_Alarm_IRQHandler
         B RTC_Alarm_IRQHandler
 
-        PUBWEAK USB_FS_WKUP_CRS_IRQHandler
+        PUBWEAK CRS_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
-USB_FS_WKUP_CRS_IRQHandler
-        B USB_FS_WKUP_CRS_IRQHandler
+CRS_IRQHandler
+        B CRS_IRQHandler
 
         PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
@@ -523,6 +511,7 @@ DMA2_Channel7_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMAMUX1_OVR_IRQHandler
         B DMAMUX1_OVR_IRQHandler
+
         END
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/MDK-ARM/BLE_Ota.uvprojx b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/MDK-ARM/BLE_Ota.uvprojx
index c30b22b84..45147a12b 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/MDK-ARM/BLE_Ota.uvprojx
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/MDK-ARM/BLE_Ota.uvprojx
@@ -435,6 +435,11 @@
               1
               ../Core/Src/main.c
                 
+            
+              app_debug.c
+              1
+              ../Core/Src/app_debug.c
+            
             
               stm32wbxx_it.c
               1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/SW4STM32/BLE_Ota/.project b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/SW4STM32/BLE_Ota/.project
index 59b255021..dbb0b0778 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/SW4STM32/BLE_Ota/.project
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/SW4STM32/BLE_Ota/.project
@@ -64,6 +64,11 @@
 			1
 			PARENT-2-PROJECT_LOC/Core/Src/main.c
 		
+    
+			Application/Core/app_debug.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/app_debug.c
+		
     
 			Application/Core/stm32wbxx_it.c
 			1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/SW4STM32/BLE_Ota/stm32wb55xx_flash_cm4.ld b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/SW4STM32/BLE_Ota/stm32wb55xx_flash_cm4.ld
index a9ccd801e..7ac9a391f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/SW4STM32/BLE_Ota/stm32wb55xx_flash_cm4.ld
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/SW4STM32/BLE_Ota/stm32wb55xx_flash_cm4.ld
@@ -50,7 +50,7 @@ ENTRY(Reset_Handler)
 _estack = 0x20030000;    /* end of RAM */
 /* Generate a link error if heap and stack don't fit into RAM */
 _Min_Heap_Size = 0x400;      /* required amount of heap  */
-_Min_Stack_Size = 0x1000; /* required amount of stack */
+_Min_Stack_Size = 0x1000;   /* required amount of stack */
 
 /* Specify the memory areas */
 MEMORY
@@ -181,7 +181,7 @@ SECTIONS
   .ARM.attributes 0       : { *(.ARM.attributes) }
    MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
    MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
-   MB_MEM2                : { *(MB_MEM2) } >RAM_SHARED  
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
 }
 
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/SW4STM32/startup_stm32wb55xx_cm4.s b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/SW4STM32/startup_stm32wb55xx_cm4.s
index 023c1b016..f79eec117 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/SW4STM32/startup_stm32wb55xx_cm4.s
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Ota/SW4STM32/startup_stm32wb55xx_cm4.s
@@ -44,21 +44,29 @@ defined in linker script */
 .word	_sbss
 /* end address for the .bss section. defined in linker script */
 .word	_ebss
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
   movs r3, #0
-  b	LoopCopyDataInit
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
 
+.section  .text.data_initializers
 CopyDataInit:
   ldr r4, [r2, r3]
   str r4, [r0, r3]
@@ -67,21 +75,31 @@ CopyDataInit:
 LoopCopyDataInit:
   adds r4, r0, r3
   cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
+  bcc  CopyDataInit
+  bx lr
 
 FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
+  str  r3, [r0]
+  adds r0, r0, #4
 
 LoopFillZerobss:
-  cmp r2, r4
+  cmp r0, r1
   bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/EWARM/stm32wb55xx_flash_cm4.icf b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/EWARM/stm32wb55xx_flash_cm4.icf
index 46f07d1f3..5f36da686 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/EWARM/stm32wb55xx_flash_cm4.icf
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/EWARM/stm32wb55xx_flash_cm4.icf
@@ -11,7 +11,7 @@ define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
 define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
 /*-Sizes-*/
 define symbol __ICFEDIT_size_cstack__ = 0x1000;
-define symbol __ICFEDIT_size_heap__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x400;
 /**** End of ICF editor section. ###ICF###*/
 
 define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000;
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/Inc/hw_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/Inc/hw_conf.h
index e1aa2cf3e..cee4bbae6 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/Inc/hw_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/Inc/hw_conf.h
@@ -24,9 +24,37 @@
 #define HW_CONF_H
 
 /******************************************************************************
- * Semaphores
- * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
- *****************************************************************************/
+* Semaphores
+* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
+*****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
 /* Index of the semaphore used to manage the entry Stop Mode procedure */
 #define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/MDK-ARM/stm32wb55xx_flash_cm4.sct b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/MDK-ARM/stm32wb55xx_flash_cm4.sct
index 0c8a4261d..63845c07b 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/MDK-ARM/stm32wb55xx_flash_cm4.sct
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/MDK-ARM/stm32wb55xx_flash_cm4.sct
@@ -11,10 +11,11 @@ LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
   RW_IRAM1     0x20000004 0x2FFFC  {  ; RW data
    .ANY (+RW +ZI)
   }
-
   RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
-   *(MAPPING_TABLE,First)
+   *(MAPPING_TABLE)
    *(MB_MEM1)
    *(MB_MEM2)
   }
-    }
\ No newline at end of file
+  }
+
+
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/SW4STM32/BLE_Peripheral_Lite/stm32wb55xx_flash_cm4.ld b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/SW4STM32/BLE_Peripheral_Lite/stm32wb55xx_flash_cm4.ld
index ab9923784..7ac9a391f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/SW4STM32/BLE_Peripheral_Lite/stm32wb55xx_flash_cm4.ld
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/SW4STM32/BLE_Peripheral_Lite/stm32wb55xx_flash_cm4.ld
@@ -50,13 +50,13 @@ ENTRY(Reset_Handler)
 _estack = 0x20030000;    /* end of RAM */
 /* Generate a link error if heap and stack don't fit into RAM */
 _Min_Heap_Size = 0x400;      /* required amount of heap  */
-_Min_Stack_Size = 0x1000; /* required amount of stack */
+_Min_Stack_Size = 0x1000;   /* required amount of stack */
 
 /* Specify the memory areas */
 MEMORY
 {
 FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
-RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 191K
+RAM1 (xrw)                 : ORIGIN = 0x20000004, LENGTH = 0x2FFFC
 RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
 }
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/Src/app_debug.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/Src/app_debug.c
index b5e8863a2..246173ae6 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/Src/app_debug.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/Src/app_debug.c
@@ -36,20 +36,6 @@ typedef PACKED_STRUCT
   uint8_t reserved;
 } APPD_GpioConfig_t;
 
-typedef PACKED_STRUCT
-{
-  uint8_t thread_config;
-  uint8_t ble_config;
-  uint8_t mac_802_15_4;
-  uint8_t reserved;
-} APPD_TracesConfig_t;
-
-typedef PACKED_STRUCT
-{
-  uint8_t ble_dtb_cfg;
-  uint8_t reserved[3];
-} APPD_GeneralConfig_t;
-
 /* Private defines -----------------------------------------------------------*/
 #define GPIO_NBR_OF_RF_SIGNALS                  9
 #define GPIO_CFG_NBR_OF_FEATURES                34
@@ -63,8 +49,8 @@ typedef PACKED_STRUCT
 
 /* Private macros ------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static APPD_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
-PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static APPD_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
 
 /**
  * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
@@ -124,15 +110,15 @@ static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
 #if( BLE_DTB_CFG == 7)
 static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
 {
-    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 */
-    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 */
-    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 */
-    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 */
-    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 */
-    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 */
-    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 */
-    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 */
-    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 */
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
 };
 #endif
 
@@ -150,12 +136,25 @@ void APPD_Init( void )
    */
   HAL_DBGMCU_EnableDBGSleepMode();
   HAL_DBGMCU_EnableDBGStopMode();
-  HAL_DBGMCU_EnableDBGStandbyMode();
-  
+
   /***************** ENABLE DEBUGGER *************************************/
   LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
 
 #else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
 
   HAL_DBGMCU_DisableDBGSleepMode();
   HAL_DBGMCU_DisableDBGStopMode();
@@ -331,7 +330,7 @@ static void APPD_BleDtbCfg( void )
  * WRAP FUNCTIONS
  *
 *************************************************************/
-#if (CFG_DEBUG_TRACE != 0)
+#if(CFG_DEBUG_TRACE != 0)
 void DbgOutputInit( void )
 {
   HW_UART_Init(CFG_DEBUG_TRACE_UART);
@@ -342,6 +341,7 @@ void DbgOutputInit( void )
 void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
 {
   HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
   return;
 }
 #endif
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/Src/main.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/Src/main.c
index 4679fe5ab..d144172aa 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/Src/main.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Peripheral_Lite/Src/main.c
@@ -77,8 +77,6 @@ detailed procedure to change the Wireless Coprocessor binary.
 #define APP_FLAG_BLE_INITIALIZED            3
 #define APP_FLAG_BLE_ADVERTISING            4
 #define APP_FLAG_BLE_CONNECTED              5
-#define APP_FLAG_HCI_COMMAND_SENT          16
-#define APP_FLAG_SHCI_COMMAND_SENT         17
 #define APP_FLAG_HCI_EVENT_PENDING         18
 #define APP_FLAG_SHCI_EVENT_PENDING        19
 #define APP_FLAG_GET(flag)                  VariableBit_Get_BB(((uint32_t)&APP_State), flag)
@@ -725,39 +723,6 @@ void shci_notify_asynch_evt(void* pdata)
   return;
 }
 
-/**
-* @brief  This function informs the user that the response of the pending
-*         system command has been received. It is called in the IPCC interrupt
-*         context. When moving out from this API, the application may return
-*         from the API shci_cmd_resp_wait().
-* @param  flag: Release flag, always 0 (unused)
-* @retval None
-*/
-void shci_cmd_resp_release(uint32_t flag)
-{
-  APP_FLAG_RESET(APP_FLAG_SHCI_COMMAND_SENT);
-  return;
-}
-
-/**
-* @brief  This function is called when an System HCI Command is sent and the response
-*         is waited from the CPU2.
-*         The application shall implement a mechanism to not return from this function 
-*         until the waited event is received.
-*         This is notified to the application with shci_cmd_resp_release().
-*         It is called from the same context the System HCI command has been sent.
-*
-* @param  timeout: Waiting timeout, SHCI_TL_DEFAULT_TIMEOUT passed (fixed to 33 seconds as of today)
-* @retval None
-*/
-void shci_cmd_resp_wait(uint32_t timeout)
-{
-  APP_FLAG_SET(APP_FLAG_SHCI_COMMAND_SENT);
-  while (APP_FLAG_GET(APP_FLAG_SHCI_COMMAND_SENT) == 1);
-  return;
-}
-
-
 /**
 * @brief As stated in AN5289, this is the system event user callback. It is
 *        registered and passed as argument to shci_init() function.
@@ -895,37 +860,6 @@ void hci_notify_asynch_evt(void* pdata)
   return;
 }
 
-/**
-* @brief  As stated in AN5289, this function is called when an ACI/HCI command is sent and the response is
-*         received from the BLE core.
-*
-* @param  flag: Release flag, always 0 (unused)
-* @retval None
-*/
-void hci_cmd_resp_release(uint32_t flag)
-{
-  APP_FLAG_RESET(APP_FLAG_HCI_COMMAND_SENT);
-  return;
-}
-
-/**
-* @brief  As stated in AN5289, this function is called when an ACI/HCI command is sent and the response 
-*         is waited from the BLE core.
-*         The application shall implement a mechanism to not return from this function 
-*         until the waited event is received.
-*         This is notified to the application with hci_cmd_resp_release().
-*         It is called from the same context the HCI command has been sent.
-*
-* @param  timeout: Waiting timeout, HCI_TL_DEFAULT_TIMEOUT passed (fixed to 33 seconds as of today)
-* @retval None
-*/
-void hci_cmd_resp_wait(uint32_t timeout)
-{
-  APP_FLAG_SET(APP_FLAG_HCI_COMMAND_SENT);
-  while (APP_FLAG_GET(APP_FLAG_HCI_COMMAND_SENT) == 1);
-  return;
-}
-
 /**
 * @brief As stated in AN5289, this is the BLE event user callback. It is
 *        registered and passed as argument to hci_init() function.
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Inc/app_debug.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Inc/app_debug.h
new file mode 100644
index 000000000..13485c16b
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Inc/app_debug.h
@@ -0,0 +1,45 @@
+
+/**
+  ******************************************************************************
+  * @file    app_debug.h
+  * @author  MCD Application Team
+  * @brief   Interface to support debug in the application
+  ******************************************************************************
+  * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+  /* Exported types ------------------------------------------------------------*/
+  /* Exported constants --------------------------------------------------------*/
+  /* External variables --------------------------------------------------------*/
+  /* Exported macros -----------------------------------------------------------*/
+  /* Exported functions ------------------------------------------------------- */
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Inc/hw_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Inc/hw_conf.h
index 91bc7cd83..18d8e28f8 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Inc/hw_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Inc/hw_conf.h
@@ -23,9 +23,37 @@
 #define __HW_CONF_H
 
 /******************************************************************************
- * Semaphores
- * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
- *****************************************************************************/
+* Semaphores
+* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
+*****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
 /* Index of the semaphore used to manage the entry Stop Mode procedure */
 #define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Src/app_debug.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Src/app_debug.c
new file mode 100644
index 000000000..246173ae6
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Src/app_debug.c
@@ -0,0 +1,349 @@
+/**
+ ******************************************************************************
+ * @file    app_debug.c
+ * @author  MCD Application Team
+ * @brief   Debug capabilities
+ ******************************************************************************
+ * @attention
+ *
+ * 
    © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
    
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+
+/* Private defines -----------------------------------------------------------*/
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+
+/* Global variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+  HW_UART_Init(CFG_DEBUG_TRACE_UART);
+  return;
+}
+
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Src/app_entry.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Src/app_entry.c
index 6ad579132..106f4ad6a 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Src/app_entry.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Src/app_entry.c
@@ -33,7 +33,7 @@
 #include "stm32_lpm.h"
 
 
-#include "dbg_trace.h"
+#include "app_debug.h"
 
 
 /* Private typedef -----------------------------------------------------------*/
@@ -50,7 +50,6 @@ PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t	BleSpareEvtBuffer[sizeof(TL_
 /* Global variables ----------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
 static void SystemPower_Config( void );
-static void Init_Debug( void );
 static void appe_Tl_Init( void );
 static void Led_Init( void );
 static void Button_Init( void );
@@ -64,7 +63,7 @@ void APPE_Init( void )
   
   HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
 
-  Init_Debug();
+  APPD_Init();
 
   /**
    * The Standby mode should not be entered before the initialization is over
@@ -92,48 +91,6 @@ void APPE_Init( void )
  * LOCAL FUNCTIONS
  *
  *************************************************************/
-static void Init_Debug( void )
-{
-#if (CFG_DEBUGGER_SUPPORTED == 1)
-  /**
-   * Keep debugger enabled while in any low power mode
-   */
-  HAL_DBGMCU_EnableDBGSleepMode();
-
-  /***************** ENABLE DEBUGGER *************************************/
-  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-  LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-
-#else
-
-  GPIO_InitTypeDef gpio_config = {0};
-
-  gpio_config.Pull = GPIO_NOPULL;
-  gpio_config.Mode = GPIO_MODE_ANALOG;
-
-  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOA, &gpio_config);
-  __HAL_RCC_GPIOA_CLK_DISABLE();
-
-  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOB, &gpio_config);
-  __HAL_RCC_GPIOB_CLK_DISABLE();
-
-  HAL_DBGMCU_DisableDBGSleepMode();
-  HAL_DBGMCU_DisableDBGStopMode();
-  HAL_DBGMCU_DisableDBGStandbyMode();
-
-#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
-
-#if(CFG_DEBUG_TRACE != 0)
-  DbgTraceInit();
-#endif
-
-  return;
-}
-
 /**
  * @brief  Configure the system for power optimization
  *
@@ -238,7 +195,7 @@ static void APPE_SysStatusNot( SHCI_TL_CmdStatus_t status )
 static void APPE_SysUserEvtRx( void * pPayload )
 {
   /**< Traces channel initialization */
-  TL_TRACES_Init( );
+  APPD_EnableCPU2();
 
   UTIL_LPM_SetOffMode(1 << CFG_LPM_APP, UTIL_LPM_ENABLE);
 
@@ -308,21 +265,4 @@ void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin )
   return;
 }
 
-#if(CFG_DEBUG_TRACE != 0)
-void DbgOutputInit( void )
-{
-  HW_UART_Init(CFG_DEBUG_TRACE_UART);
-  return;
-}
-
-
-void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
-{
-  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
-
-  return;
-}
-#endif
-
-
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Src/stm32_lpm_if.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Src/stm32_lpm_if.c
index f024b61e3..1418e0a36 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Src/stm32_lpm_if.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/Core/Src/stm32_lpm_if.c
@@ -70,6 +70,13 @@ static void Switch_On_HSI( void );
 void PWR_EnterOffMode( void )
 {
 /* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
   /************************************************************************************
    * ENTER OFF MODE
    ***********************************************************************************/
@@ -106,6 +113,8 @@ void PWR_ExitOffMode( void )
 {
 /* USER CODE BEGIN PWR_ExitOffMode */
 
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitOffMode */
 }
 
@@ -118,6 +127,16 @@ void PWR_ExitOffMode( void )
 void PWR_EnterStopMode( void )
 {
 /* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
   /**
    * This function is called from CRITICAL SECTION
    */
@@ -202,6 +221,9 @@ void PWR_ExitStopMode( void )
 
   /* Release RCC semaphore */
   LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitStopMode */
 }
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/EWARM/BLE_Proximity.ewp b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/EWARM/BLE_Proximity.ewp
index 8c5c5ec21..150250a54 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/EWARM/BLE_Proximity.ewp
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/EWARM/BLE_Proximity.ewp
@@ -1048,6 +1048,9 @@
             
                 $PROJ_DIR$\..\Core\Src\app_entry.c
             
+            
+                $PROJ_DIR$\..\Core\Src\app_debug.c
+            
             
                 $PROJ_DIR$\..\Core\Src\hw_timerserver.c
             
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/EWARM/startup_stm32wb55xx_cm4.s b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/EWARM/startup_stm32wb55xx_cm4.s
index 79b0e7edd..1f886ff59 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/EWARM/startup_stm32wb55xx_cm4.s
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/EWARM/startup_stm32wb55xx_cm4.s
@@ -1,4 +1,4 @@
-;/********************* COPYRIGHT(c) 2019 STMicroelectronics ********************
+;******************************************************************************
 ;* File Name          : startup_stm32wb55xx_cm4.s
 ;* Author             : MCD Application Team
 ;* Description        : M4 core vector table of the STM32WB55xx devices for the
@@ -13,31 +13,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* 
    © Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.
    
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
 ;*
-;*******************************************************************************
+;******************************************************************************
 ;
 ;
 ; The modules in this file are included in the libraries, and may be replaced
@@ -86,10 +73,10 @@ __vector_table
         DCD     PendSV_Handler                    ; PendSV Handler
         DCD     SysTick_Handler                   ; SysTick Handler
 
-         ; External Interrupts
+        ; External Interrupts
         DCD     WWDG_IRQHandler                   ; Window WatchDog
-        DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
-        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
+        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
+        DCD     TAMP_STAMP_LSECSS_IRQHandler      ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
         DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
         DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
         DCD     RCC_IRQHandler                    ; RCC Interrupt
@@ -129,7 +116,7 @@ __vector_table
         DCD     TSC_IRQHandler                    ; TSC Interrupt
         DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
         DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
-        DCD     USB_FS_WKUP_CRS_IRQHandler        ; USB Full speed wakeup
+        DCD     CRS_IRQHandler                    ; CRS interrupt
         DCD     PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
         DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
         DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
@@ -156,6 +143,7 @@ __vector_table
 ;; Default interrupt handlers.
 ;;
         THUMB
+
         PUBWEAK Reset_Handler
         SECTION .text:CODE:NOROOT:REORDER(2)
 Reset_Handler
@@ -419,10 +407,10 @@ EXTI15_10_IRQHandler
 RTC_Alarm_IRQHandler
         B RTC_Alarm_IRQHandler
 
-        PUBWEAK USB_FS_WKUP_CRS_IRQHandler
+        PUBWEAK CRS_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
-USB_FS_WKUP_CRS_IRQHandler
-        B USB_FS_WKUP_CRS_IRQHandler
+CRS_IRQHandler
+        B CRS_IRQHandler
 
         PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
@@ -523,6 +511,7 @@ DMA2_Channel7_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMAMUX1_OVR_IRQHandler
         B DMAMUX1_OVR_IRQHandler
+
         END
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/MDK-ARM/BLE_Proximity.uvprojx b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/MDK-ARM/BLE_Proximity.uvprojx
index ec4bd6ee2..02bbe7afc 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/MDK-ARM/BLE_Proximity.uvprojx
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/MDK-ARM/BLE_Proximity.uvprojx
@@ -406,6 +406,11 @@
               1
               ../Core/Src/main.c
                 
+            
+              app_debug.c
+              1
+              ../Core/Src/app_debug.c
+            
             
               stm32wbxx_it.c
               1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/SW4STM32/BLE_Proximity/.project b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/SW4STM32/BLE_Proximity/.project
index 40cca01f2..8c98b07ed 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/SW4STM32/BLE_Proximity/.project
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/SW4STM32/BLE_Proximity/.project
@@ -59,6 +59,11 @@
 			1
 			PARENT-2-PROJECT_LOC/Core/Src/main.c
 		
+    
+			Application/Core/app_debug.c
+			1
+			PARENT-2-PROJECT_LOC/Core/Src/app_debug.c
+		
     
 			Application/Core/stm32wbxx_it.c
 			1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/SW4STM32/BLE_Proximity/stm32wb55xx_flash_cm4.ld b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/SW4STM32/BLE_Proximity/stm32wb55xx_flash_cm4.ld
index a9ccd801e..7ac9a391f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/SW4STM32/BLE_Proximity/stm32wb55xx_flash_cm4.ld
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/SW4STM32/BLE_Proximity/stm32wb55xx_flash_cm4.ld
@@ -50,7 +50,7 @@ ENTRY(Reset_Handler)
 _estack = 0x20030000;    /* end of RAM */
 /* Generate a link error if heap and stack don't fit into RAM */
 _Min_Heap_Size = 0x400;      /* required amount of heap  */
-_Min_Stack_Size = 0x1000; /* required amount of stack */
+_Min_Stack_Size = 0x1000;   /* required amount of stack */
 
 /* Specify the memory areas */
 MEMORY
@@ -181,7 +181,7 @@ SECTIONS
   .ARM.attributes 0       : { *(.ARM.attributes) }
    MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
    MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
-   MB_MEM2                : { *(MB_MEM2) } >RAM_SHARED  
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
 }
 
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/SW4STM32/startup_stm32wb55xx_cm4.s b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/SW4STM32/startup_stm32wb55xx_cm4.s
index 023c1b016..f79eec117 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/SW4STM32/startup_stm32wb55xx_cm4.s
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_Proximity/SW4STM32/startup_stm32wb55xx_cm4.s
@@ -44,21 +44,29 @@ defined in linker script */
 .word	_sbss
 /* end address for the .bss section. defined in linker script */
 .word	_ebss
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
+/* start address for the .MB_MEM2 section. defined in linker script */
+.word _sMB_MEM2
+/* end address for the .MB_MEM2 section. defined in linker script */
+.word _eMB_MEM2
+
+/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
+.macro INIT_BSS start, end
+  ldr r0, =\start
+  ldr r1, =\end
   movs r3, #0
-  b	LoopCopyDataInit
+  bl LoopFillZerobss
+.endm
+
+/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
+.macro INIT_DATA start, end, src
+  ldr r0, =\start
+  ldr r1, =\end
+  ldr r2, =\src
+  movs r3, #0
+  bl LoopCopyDataInit
+.endm
 
+.section  .text.data_initializers
 CopyDataInit:
   ldr r4, [r2, r3]
   str r4, [r0, r3]
@@ -67,21 +75,31 @@ CopyDataInit:
 LoopCopyDataInit:
   adds r4, r0, r3
   cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
+  bcc  CopyDataInit
+  bx lr
 
 FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
+  str  r3, [r0]
+  adds r0, r0, #4
 
 LoopFillZerobss:
-  cmp r2, r4
+  cmp r0, r1
   bcc FillZerobss
+  bx lr
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  INIT_DATA _sdata, _edata, _sidata
+
+/* Zero fill the bss segments. */
+  INIT_BSS _sbss, _ebss
+  INIT_BSS _sMB_MEM2, _eMB_MEM2
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/BLE_TransparentMode.ioc b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/BLE_TransparentMode.ioc
index 7d3e78d9f..394b71c90 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/BLE_TransparentMode.ioc
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/BLE_TransparentMode.ioc
@@ -52,8 +52,8 @@ Mcu.PinsNb=13
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32WB55RGVx
-MxCube.Version=5.5.0
-MxDb.Version=DB.5.0.50
+MxCube.Version=5.6.0
+MxDb.Version=DB.5.0.60
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.DMA2_Channel4_IRQn=true\:15\:0\:true\:false\:true\:false\:true
 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
@@ -95,14 +95,6 @@ PCC.Ble.ConnectionInterval=1000.0
 PCC.Ble.DataLength=6
 PCC.Ble.Mode=Advertising
 PCC.Ble.PowerLevel=Min
-PCC.Checker=true
-PCC.Line=STM32WBx5
-PCC.MCU=STM32WB55RGVx
-PCC.PartNumber=STM32WB55RGVx
-PCC.Seq0=0
-PCC.Series=STM32WB
-PCC.Temperature=25
-PCC.Vdd=3.0
 PinOutPanel.RotationAngle=0
 ProjectManager.AskForMigrate=true
 ProjectManager.BackupPrevious=false
@@ -127,7 +119,7 @@ ProjectManager.StackSize=0x1000
 ProjectManager.TargetToolchain=EWARM V8
 ProjectManager.ToolChainLocation=
 ProjectManager.UnderRoot=false
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_LPUART1_UART_Init-LPUART1-true-HAL-false,5-MX_USART1_UART_Init-USART1-true-HAL-false,6-MX_RF_Init-RF-false-HAL-true,7-MX_RTC_Init-RTC-false-HAL-true,8-APPE_Init-STM32_WPAN-false-HAL-false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_USART1_UART_Init-USART1-true-HAL-false,5-MX_RF_Init-RF-false-HAL-true,6-MX_RTC_Init-RTC-false-HAL-true,7-APPE_Init-STM32_WPAN-false-HAL-false
 RCC.ADCFreq_Value=64000000
 RCC.AHBFreq_Value=32000000
 RCC.APB1Freq_Value=32000000
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Binary/BLE_TransparentMode_reference.hex b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Binary/BLE_TransparentMode_reference.hex
index 8b812a93b..fd6aa7579 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Binary/BLE_TransparentMode_reference.hex
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Binary/BLE_TransparentMode_reference.hex
@@ -1,30 +1,30 @@
 :020000040800F2
-:10000000F01300201D4700086D4500086F450008EB
-:1000100071450008734500087545000800000000A0
-:10002000000000000000000000000000774500080C
-:1000300079450008000000007B4500087D45000868
-:10004000394700083D470008414700089B45000824
-:1000500045470008494700084D4700085147000838
-:100060005547000859470008954500085D470008B6
-:100070006147000865470008694700086D470008A8
-:100080007147000875470008794700087D47000858
-:100090008147000885470008894700088D47000808
-:1000A0009147000895470008994700089D470008B8
-:1000B000A1470008A5470008A9470008AD47000868
-:1000C000B1470008B5470008B9470008BD47000818
-:1000D00081450008C1470008C5470008C947000816
-:1000E000CD470008D1470008D5470008D947000888
-:1000F000A34500089F450008DD470008E1470008C8
-:10010000E5470008E9470008ED470008F147000807
-:10011000F5470008F9470008FD47000801480008B6
-:100120000548000809480008874500080D480008F0
-:1001300011480008154800081948000838B504009F
+:10000000F0130020CD4900080D4800080F480008F3
+:1000100011480008134800081548000800000000B7
+:100020000000000000000000000000001748000869
+:1000300019480008000000001B4800081D4800087F
+:10004000E9490008ED490008F14900083B4800086B
+:10005000F5490008F9490008FD490008014A00086F
+:10006000054A0008094A0008354800080D4A0008FA
+:10007000114A0008154A0008194A00081D4A0008DC
+:10008000214A0008254A0008294A00082D4A00088C
+:10009000314A0008354A0008394A00083D4A00083C
+:1000A000414A0008454A0008494A00084D4A0008EC
+:1000B000514A0008554A0008594A00085D4A00089C
+:1000C000614A0008654A0008694A00086D4A00084C
+:1000D00021480008714A0008754A0008794A00085A
+:1000E0007D4A0008814A0008854A0008894A0008BC
+:1000F000434800083F4800088D4A0008914A00081C
+:10010000954A0008994A00089D4A0008A14A00083B
+:10011000A54A0008A94A0008AD4A0008B14A0008EB
+:10012000B54A0008B94A000827480008BD4A000837
+:10013000C14A0008C54A0008C94A000838B5040089
 :1001400009D004F17C05686808B900F01EF800F0D9
 :1001500021F8012801D1012032BDA06A08B100F0C8
 :100160002AF800F00AF821F02A01FFE7816000F088
 :100170001BF8BDE8324000F0AABE2068416821F4B7
 :1001800090414160206881687047002129702046B5
-:1001900001F0DEB824206860206801684908490041
+:1001900001F0E7B824206860206801684908490038
 :1001A0000160204600F0BCB92068016841F00101FF
 :1001B000016020467047204600F026BE30B500F1B1
 :1001C0007C035C68202C41D109B1140001D10120CD
@@ -67,17 +67,17 @@
 :10041000D80003D5E16E09B120468847D4F888009A
 :1004200021688A68510602D410F0280F1AD020469D
 :1004300000F0BAFDFFF77FFF0FD500F057F860B16D
-:10044000DFF8A4198163A06F01F047F800284CD0B1
+:10044000DFF8A4198163A06F01F051F800284CD0A7
 :10045000A06F816BBDE8F44008472046BDE8F2403C
-:1004600001F010B9204601F00DF90020C4F8880011
+:1004600001F01AB9204601F017F90020C4F88800FD
 :10047000F1BDC80209D5580207D54FF48010286293
-:100480002046BDE8F24001F085B9080609D51006FE
+:100480002046BDE8F24001F08FB9080609D51006F4
 :1004900001D4180205D5216F39B32046BDE8F440D8
 :1004A000084748060FD550060DD5286820F04000B3
 :1004B00028602021C4F88010002020672046BDE875
-:1004C000F24001F085B9080206D5500004D5204657
-:1004D000BDE8F24001F08EB9C80148BF002A04D53A
-:1004E0002046BDE8F24001F086B9F1BD816821F0F7
+:1004C000F24001F08FB9080206D5500004D520464D
+:1004D000BDE8F24001F098B9C80148BF002A04D530
+:1004E0002046BDE8F24001F090B9F1BD816821F0ED
 :1004F00040018160A06F7047B910000879100008B2
 :100500004B10000821100008FB110008A31100087F
 :10051000351100081111000801000010200100042D
@@ -93,7 +93,7 @@
 :1005B000BBF1030F3ED8DFE80BF00237343A4FF0BF
 :1005C000010AD4F81CB05746BBF5004F4FF6F07A3D
 :1005D00040F01183012F09D0022F00F05482042F24
-:1005E00000F08D82082F00F0C282F5E201F0DCFC01
+:1005E00000F08D82082F00F0C282F5E201F000FDDC
 :1005F0000146606A002840F01B8242E2DFF8ECB757
 :100600005F4517D1DAF800A01AF4406A27D0BAF58E
 :10061000806F09D0BAF5006F03D0BAF5406F06D0ED
@@ -101,7 +101,7 @@
 :10063000080A01E04FF0100ADFF8B0B75F45C0D1FB
 :10064000BAF1000F0BD0BAF1020F49D0BAF1040F82
 :1006500000F08280BAF1080F00F0B080B6E301F03C
-:100660009BFC0146606A58B3012808BF022028D0CD
+:10066000BFFC0146606A58B3012808BF022028D0A9
 :10067000022808BF042024D0032808BF062020D069
 :10068000042808BF08201CD0052808BF0A2018D05D
 :10069000062808BF0C2014D0072808BF102010D04F
@@ -116,7 +116,7 @@
 :10072000072808BFDFF8C008D0D0082808BFDFF8C6
 :10073000BC08CBD0092808BFDFF8B408C6D00A2807
 :1007400008BFDFF8B008C1D00B2808BF4FF2244023
-:10075000BCD0DFF8A408B9E701F0D4FB0146606A19
+:10075000BCD0DFF8A408B9E701F0F8FB0146606AF5
 :1007600058B3012808BF0220ABD0022808BF0420DC
 :10077000A7D0032808BF0620A3D0042808BF08205C
 :100780009FD0052808BF0A209BD0062808BF0C2050
@@ -131,7 +131,7 @@
 :100810000A2F08BF284602D00B2F00D1802055E7B1
 :10082000BAF1000F0BD0BAF1020F38D0BAF1040FB1
 :1008300000F07280BAF1080F00F0A780ECE001F040
-:10084000ABFB0146606A40B3012808BF02251ED0F9
+:10084000CFFB0146606A40B3012808BF02251ED0D5
 :10085000022808BF04251AD0032808BF062516D091
 :10086000042808BF082512D0052808BF0A250ED085
 :10087000062808BF0C250AD0072808BF102506D077
@@ -144,7 +144,7 @@
 :1008E000072808BFDFF878690DD0082808BFDFF8AF
 :1008F000746908D0092808BFDFF86C6903D00A289A
 :1009000008BFDFF868697CD00B2808BFDFF8E8660D
-:1009100077D0DFF85C6974E001F0F4FA0146606AB0
+:1009100077D0DFF85C6974E001F018FB0146606A8B
 :1009200040B3012808BF022525D0022808BF0425AE
 :1009300021D0032808BF06251DD0042808BF08259C
 :1009400019D0052808BF0A2515D0062808BF0C2590
@@ -160,7 +160,7 @@
 :1009E000092808BF4FF400360BD00A2808BF4FF47F
 :1009F000803606D00B2808BF4FF4004601D04FF4D4
 :100A00000006C246002116EB52004AEB010100230A
-:100A100001F058FB064601E04FF00108A6F54070D2
+:100A100001F07CFB064601E04FF00108A6F54070AE
 :100A2000DFF85C18884280F0D1812168CE60CFE188
 :100A3000012808BF02251AD0022808BF042516D0B5
 :100A4000032808BF062512D0042808BF08250ED0A9
@@ -175,7 +175,7 @@
 :100AD000082808BFDFF810057AD0092808BFDFF81A
 :100AE0000C0575D00A2808BFDFF8040570D00B2864
 :100AF00008BFDFF800056BD0DFF8700768E001F091
-:100B000001FA0146606A40B3012808BF022525D0DA
+:100B000025FA0146606A40B3012808BF022525D0B6
 :100B1000022808BF042521D0032808BF06251DD0C0
 :100B2000042808BF082519D0052808BF0A2515D0B4
 :100B3000062808BF0C2511D0072808BF10250DD0A6
@@ -191,7 +191,7 @@
 :100BD00000F014F9B6B201E04FF00108A6F11000E0
 :100BE000504580F0F3800AEA0601C6F34200014353
 :100BF0002068C160ECE0012F07D0022F35D0042F10
-:100C000070D0082F00F0A580D7E001F0CDF90146A3
+:100C000070D0082F00F0A580D7E001F0F1F901467F
 :100C1000606A40B3012808BF022516D0022808BF29
 :100C2000042512D0032808BF06250ED0042808BFCB
 :100C300008250AD0052808BF0A2506D0062808BFBF
@@ -205,7 +205,7 @@
 :100CB000381315D0082808BFDFF8301310D00928E2
 :100CC00008BFDFF82C130BD00A2808BFDFF8241365
 :100CD00006D00B2808BF4FF2244101D0DFF81813CB
-:100CE000606831E001F00EF90146606A40B3012806
+:100CE000606831E001F032F90146606A40B30128E2
 :100CF00008BF022525D0022808BF042521D00328DB
 :100D000008BF06251DD0042808BF082519D00528CE
 :100D100008BF0A2515D0062808BF0C2511D00728C2
@@ -237,14 +237,14 @@
 :100EB000C0030B43536090F828100A0606D501685A
 :100EC0004A68C06C22F4002202434A607047F8B5B9
 :100ED000044604F17C050020E8606FF07E4701F0D5
-:100EE00009FA0646206801680A0708D500973346C4
+:100EE0002DFA0646206801680A0708D500973346A0
 :100EF00000224FF40011204600F016F860B9206877
 :100F000001684A070AD50097334600224FF4800152
 :100F1000204600F009F808B10320F2BD20206860E7
 :100F2000A86000202870F2BD2DE9F041069C05461E
 :100F30000E4690461F462868C1693140B1420CBF39
 :100F40000120002040451CD114F1010FF3D001F025
-:100F5000D1F9C01B844200D314B900F015F80CE09D
+:100F5000F5F9C01B844200D314B900F015F80CE079
 :100F6000286801684A07E6D5C1690A05E3D54FF448
 :100F70000062026200F008F8C160002101700320E5
 :100F800000E00020BDE8F0812868016821F4D071FC
@@ -256,7 +256,7 @@
 :100FE000006A18005558140040420F0020A1070065
 :100FF00090D0030048E801000024F400136823F0B7
 :10100000800313600068016841F04001016070478F
-:10101000806A00F1560100220A810A8000F032BB8A
+:10101000806A00F1560100220A810A8000F03CBB80
 :10102000D0F8801021290FD10268B0F8561001B90C
 :10103000E4E7036D19789162016D4A1C0265B0F80E
 :1010400056104A1EA0F856207047D0F8801021296B
@@ -281,7 +281,7 @@
 :101170004B6A00F15E0461880B40816D7047016825
 :101180000B6823F490730B6001688B685B085B004D
 :101190008B602021916100211160BDE8104000F0BA
-:1011A0000DBB2DE9F84300F07DF81CD16789DFF80D
+:1011A00017BB2DE9F84300F07DF81CD16789DFF803
 :1011B000DC900AE000F08DF80870B06D411C00F082
 :1011C0006BF808B900F08BF87F1EB8B20028F1D197
 :1011D000208850B16189884207DA00F074F82C4801
@@ -302,859 +302,902 @@
 :1012C0002001016070473068816821F080518160A1
 :1012D00070473068406AB16D08EA000070473068B6
 :1012E000016821F4807101603068816809EA0101B8
-:1012F00081602020A86100202860304600F05EBA9E
-:101300003A4881B0016841F400210160006800F4AE
-:1013100000200090009801B0704710B50446344991
-:101320002068884213D100F0EBFF00F0E9FF31485C
-:10133000016821F4407141F480710160026842F457
-:10134000004202602046BDE8104000F0EDBF10BD35
-:1013500038B586B0044601A8142100F0FDFF2168CD
-:10136000254A914240D12548254D416941F48041AB
-:1013700041610222416901F48041009100990168B4
-:1013800041F002010160C021006800F002000090FD
-:1013900000980191012003900321072004910590FA
-:1013A000029201A9174800F0DBFF174828600F20C0
-:1013B00068601020A8600020E8608020286100207C
-:1013C0006861A861E8612862284600F01FF808B14A
-:1013D00001F0E2F96567AC6200220021242001F0EF
-:1013E000F9F9242001F013FA07B030BD500000587D
-:1013F0000028004090000058003801404C00005880
-:1014000004030020000400484404024038B50400EE
-:1014100001D1012032BD2168DFF84002814204F190
-:10142000240500F042F8022068700A68A0686FF393
-:101430000E120243E06802432069024360690243DE
-:10144000A0690243E0690243206A02430A60204621
-:1014500000F0DAF8A068B0F5804F04BF00216160A9
-:10146000696A207900F014F838B1052805D22046C1
-:1014700000F0E4F800F012F803E00020286368634D
-:10148000A8630020A861012068700020287032BD88
-:101490000860A96AE86A486060687047296B0020A4
-:1014A0000860696BA86B486070470AD2DFF8B0012A
-:1014B00042181423B2FBF3F292002A62DFF8A4016F
-:1014C00009E0DFF8A40142181423B2FBF3F2920002
-:1014D0002A62DFF89801E861704738B500F124020C
-:1014E00000245178022903D004209061012428E0CF
-:1014F00001680B6823F00E030B6001680D686D082E
-:101500006D000D60516A0B6823F480730B6001213C
-:1015100092F82030D56903F01C0399406960936A02
-:10152000D16A5960116B31B10B6823F480730B6081
-:10153000536B916B5960012151701470516901B165
-:101540008847204632BDF8B500F124010423CA695A
-:1015500014680268156891F8206006F01C0603FA0A
-:1015600006F73C4210D06F070ED51468A50603D4C9
-:10157000156825F00405156000F03DF8C9680029DC
-:1015800038D0BDE8F4400847022303FA06F73C428E
-:1015900013D0AF0711D51468A50605D4156825F03A
-:1015A0000A05156001224A7000F025F800220A7031
-:1015B0008968F9B1BDE8F4400847082303FA06F644
-:1015C000344217D02B0715D5136823F00E03136090
-:1015D000012291F82030CC6903F01C039A4062602C
-:1015E00001228A614A7000220A70096911B1BDE8BE
-:1015F000F4400847F1BD91F82020CC6902F01C02AC
-:101600009340636070470000416C0268134B890887
-:101610009A4234BF164B174B03EB8101816402F0F1
-:10162000FF02083A1421B2FBF1F1134AC26401F03F
-:101630001C01012202FA01F10165704701790F4A8C
-:1016400002EB81024265491E0D4A826501F00301E9
-:1016500001228A40C2657047000000000804024071
-:10166000F8FFFDBF00000240F8FBFDBF0004024090
-:10167000000802401C08024080080240FC080240AA
-:10168000400902407047000010B500F17C010A7863
-:10169000012A01D1022010BD01230B7024224A60CF
-:1016A00002681368146864086400146000224266CB
-:1016B00023F0005300680360202048600020087079
-:1016C00010BD70B500F01EF801D1022070BD00F011
-:1016D0001FF822F0604209E070B500F013F801D164
-:1016E000022070BD00F014F822F0606211438160A6
-:1016F000204600F01AF8206806602020686000206C
-:10170000287070BD044604F17C05287801287047D4
-:1017100001222A7024206860206806680268520846
-:1017200052000260206882687047FFB50FF25402D1
-:101730000FF25806D2E9003402A9C1E90034D6E913
-:101740000071CDE90071416E11B90121012213E050
-:1017500001688A688968520E02F00702490F02ACDC
-:10176000655CA45C1DF801101DF80220ED00E4008A
-:1017700095FBF1F194FBF2F2683041800280FFBDED
-:101780000000000001010103070100000804020439
-:10179000080101017047000030B912480360124887
-:1017A000124B0360FEF754BD704730B91048036018
-:1017B0000D480E4B0360FEF701BD704700680B49F2
-:1017C000884204D107490868002818BF00477047BD
-:1017D00000680649884204D105490868002818BFF6
-:1017E00000477047E8030020F8010020003801405E
-:1017F000EC030020704770474FF0B040006800F0E5
-:10180000F000B02888BFB02070472DE9F0410400F7
-:1018100068D0207881064FF0B04539D5A868E968CE
-:1018200010F00C0001F0030104D00C2808BF0129BE
-:1018300040F083802868800702D5E069002851D0F5
-:10184000FFF7DAFF616A884207D2084600F0BDFB65
-:1018500000281BD100F05AFA10E0286820F0F000B0
-:10186000014329606968206A21F47F4141EA00212F
-:101870006960606A00F0A9FB002807D101F046F812
-:10188000DFF8E007006801F0CFF8002840F0888119
-:101890002078C10711D5A868E96800F00C00082875
-:1018A00001F0030103D00C2808BF032967D1286881
-:1018B000800302D56068002814D0217888071AD5E3
-:1018C000A868E96800F00C00042801F0030104D0C6
-:1018D0000C2808BF022940F087802868400503D5FE
-:1018E000E068002800F05C816968206921F0FE4111
-:1018F00041EA006169602168DFF86C6711F0180F38
-:1019000000F078816069002800F0A880C90670683E
-:1019100040F19580800707D4706840F0010000F026
-:101920000EFA07467068800700F13C8100F0E2FC87
-:10193000C01B0328F6D30320E1E1E06978B12968F0
-:1019400041F0010100F0D4FA06462868800700F152
-:10195000388100F0CFFC801B0328F6D3EBE7286822
-:101960004008400000F0E5F90646286800F0CAF992
-:101970008ED000F0BFFC801B0328F6D3DBE7606845
-:10198000B0F5803F06D0B0F5A02F296807D141F40B
-:1019900080212960286840F48030286006E021F426
-:1019A000803129602A6822F480222A60606860B150
-:1019B00000F0A0FC0646286880033FF57EAF00F0EB
-:1019C00099FC801B6528F6D3B5E700F093FC06462A
-:1019D0002868400C10F001003FF46FAF00F08AFC63
-:1019E000801B6528F4D3A6E7E06878B1296841F444
-:1019F000807100F07DFA06462868400500F1E48019
-:101A000000F078FC801B0328F6D394E7286820F4C4
-:101A1000807000F08EF906462868800A10F00100F8
-:101A20003FF469AF00F066FC801B0328F4D382E723
-:101A300000F060FCC01B0328C0F0D8807BE740F0BA
-:101A4000010000F07CF907467068800700F1E9802A
-:101A500000F050FCC01B0328F6D36CE7706820F040
-:101A6000040000F06CF907467068C00810F001002F
-:101A700000F0E68000F03EFCC01B0428F4D35AE7D7
-:101A80000528306806D140F004003060316841F02C
-:101A9000010105E0400840003060316821F0040198
-:101AA0003160A06841F2893768B100F023FC8046BC
-:101AB0003068800700F1D98000F01CFCA0EB080022
-:101AC000B842F5D337E700F015FC8046306800F0E7
-:101AD00019F900F0CA8000F00DFCA0EB0800B84234
-:101AE000F4D328E700F006FCC01B0328C0F0CB802D
-:101AF00021E7B06840084000B06000F0FBFB0746FB
-:101B0000B06800F0FFF800F0C28000F0F3FBC01BEB
-:101B10000328F5D30FE700F0EDFB801B0328C0F08E
-:101B2000C88008E700F0E6FB001B0328C0F0E28055
-:101B300001E7E968DFF8340589088900E960E968A8
-:101B40000140E96000F0D6FB044600F0EDF825D036
-:101B500000F0D0FB001B0328F7D3ECE601281FD0D0
-:101B6000E868226B00F00301914202BF00F07001AF
-:101B7000626B914214D1A26BC0F30621914202BF65
-:101B800000F47811E26B91420AD1226C00F060619E
-:101B9000914202BF00F06040616C884200F0AE806C
-:101BA0000120ACE0706840F0040000F0C8F807467F
-:101BB0007068000710D400F09DFBC01B0428F7D309
-:101BC000B9E600F0A3F863E66868216920F0FE40FA
-:101BD00040EA016068608EE67068A16920F4706078
-:101BE00040EA0120706000F0A7F8074600F089F88D
-:101BF0007FF41EAF2078410737D5DFF8747438685A
-:101C0000C10529D400F07CFB00F074FB80463868E5
-:101C1000C10521D400F06EFBA0EB08000328F6D329
-:101C200089E6706820F0040070607068C00810F0E9
-:101C30000100DFD000F05EFBC01B0428F5D37AE67C
-:101C400000F07AF8074600F05CF8D3D000F052FBC1
-:101C5000C01B0328F7D36EE6A06801287FF410AFFD
-:101C6000306840F0010030601BE7217848060ED54F
-:101C7000A06A00283FF43DAFB16841F00101B160B6
-:101C800000F038FB0746B06880077FF52BAFE06AAD
-:101C9000A0B3A96801F00C010C293FF45FAF022842
-:101CA000286820F0807028607FF443AF00F022FBAA
-:101CB000064600F039F87FF42EAFE968DFF8B40388
-:101CC000A26B0140206B0143606B0143E06B41EA72
-:101CD00002210143206C0143606C0143E9602868E4
-:101CE00040F080702860E96841F08051E96000F0C0
-:101CF00001FB0446286880017FF514AF0020BDE891
-:101D0000F0817068400810F0010070472968606A2F
-:101D100021F0F001014329606868216A20F47F40C6
-:101D200040EA0120686070472868400E10F001000A
-:101D30007047286000F0DEBA7068400840007060AC
-:101D400000F0D8BA2DE9F8430400884644D0DFF803
-:101D5000286300F0C8F847D200F0CDF8074600F03D
-:101D6000C2F841D000F0C6FAC01B0228F7D9032000
-:101D7000B7E000F0BFFA401B022843D9F7E700F0B4
-:101D8000B9FAA0EB090002284CD9F0E700F0B2FA4A
-:101D9000A0EB0900022854D9E9E700F0ABFA401B98
-:101DA00002285DD9E3E700F0A5FA401B022867D9B5
-:101DB000DDE700F09FFA401B484577D3D7E70328BB
-:101DC00002D13968890103E00028396802D1890706
-:101DD00062D401E049055FD4012082E000F08AFA74
-:101DE000C01B022872D9C2E7207881074FF0B047A4
-:101DF0000BD5B968A06821F0F0010143B96000F08B
-:101E000079FA0546B868C003B3D52078DFF8505298
-:101E100081060AD52968606921F0F001014300F0CC
-:101E200067F8814628688003A9D5207841060BD53C
-:101E30002968A0690909090141EA101100F058F860
-:101E400081462868C003A1D5207841070BD5B96821
-:101E5000E06821F4E0610143B96000F04BFA054607
-:101E6000B868800399D5207801070CD5B868216936
-:101E700020F4605040EAC100B86000F03BFA05462B
-:101E8000B86840038FD52078C10717D5606802284D
-:101E900095D1396889039FD5B968890840EA8100DE
-:101EA000B86041F2893900F025FA0546B8686168E2
-:101EB00000F00C00B0EB810F7FF47BAF306800F0D6
-:101EC0000700804505D200F016F8074600F00BF831
-:101ED00084D100F01BFD00F0DDFDBDE8F24300F011
-:101EE000A3BDBDE8F283306800F0070040457047AD
-:101EF000296000F0FFB93168C90848EAC1013160C2
-:101F000000F0F8B938B54FF0B0445D4DA16811F05C
-:101F10000C0106D1FFF770FCC0F3031055F8200048
-:101F200032BD0429574A05D00829574804D12168F1
-:101F3000C90222D5104632BDE16801F00301022931
-:101F400004D0032904D12168C90207D5104605E051
-:101F5000FFF752FCC0F3031055F82000E168E26877
-:101F6000E368C1F306214843C2F30211491C5B0F29
-:101F7000B0FBF1F05B1CB0FBF3F032BD80B5FFF7B6
-:101F8000C1FF3E49FFE7414A0968C1F3031152F816
-:101F90002110B0FBF1F002BD80B5FFF7EFFF00F0BC
-:101FA00010F8C1F3022106E080B5FFF7E7FF00F06B
-:101FB00008F8C1F3C22112F8211001F01F01C84036
-:101FC00002BD2E49324A0968704770B52C49B128C4
-:101FD0002EBFCC6AC0F3031051F82040204805689A
-:101FE00000F078FD29492B4A05F00F0551F825101E
-:101FF000B4FBF1F10024B1FBF2F1B0F5007F0FF278
-:10200000B402204609D10FF2900353F820508D42BC
-:1020100014D2401C0328F8D912E00FF28C0353F8B5
-:1020200020508D420AD2401C0328F8D308E000F06B
-:1020300061F9801B03280BD3032070BD52F82040A8
-:102040000D4D2868C00844EAC000FFF772FE06463E
-:10205000296801F00701A142E9D1002070BD00000C
-:10206000080100583000002090000058FFFFFEEEED
-:10207000000400588C80C11100400058080000582E
-:10208000E82900080024F4000048E801A829000815
-:102090009C46000840420F0012000000240000008F
-:1020A0003600000040000000060000000C000000A8
-:1020B000100000000000000001000000020000000D
-:1020C00003000000B3BBD9B1B2F5803F7DD2022A34
-:1020D0001ED98C46B1FBF2F102FB11C31B0443EA8B
-:1020E0001043B3FBF2FC02FB1C3380B240EA034313
-:1020F000B3FBF2F002FB103240EA0C4000237047C1
-:10210000022A05D98446B0FBF2F002FB10C27047E8
-:102110004AB105D100F0010249085FEA300070477A
-:1021200000220023704700F0DDBC0B0002000021FC
-:1021300000207047904271EB030CF6D3B3F5803F5B
-:102140002FD2F0B5B3FA83F7B1FA81F4A7F10F0EED
-:102150003D1B5340CEF1200602FA0EF2F3415340EC
-:10216000B5F10F0746D80F3C2C444140C4F120067E
-:10217000A040F1414140B1FBF3F603FB1611A2FB75
-:102180000645001BA94102D2761E8018594180EAFB
-:10219000010221FA0EF362FA0EF200215A40304693
-:1021A000F0BD30B4B1FBF3FC03FB1C11A2FB0C45EA
-:1021B000001BA94103D2ACF1010C8018594130BC7D
-:1021C00002460B46604600217047B2F1807F65D31E
-:1021D000F0B5B2FA82F7B1FA81F4C7F10F063D1BF0
-:1021E00022FA06F307F1110EF24120355A40B5F1FB
-:1021F0000F07B8D94140C4F12006A040F141414049
-:10220000B1FBF3FC03FB1C11A2FB0C45001BA94115
-:1022100003D2BCF1010C801859410F2F12D30F3F8C
-:10222000C90341EA5041B1FBF3F603FB1611A2FBCF
-:102230000645D4EBC030A94102D2761E8018594120
-:1022400046EACC3C07B34140C7F12006B840F14113
-:102250004140B1FBF3F603FB1611A2FB0645001B40
-:10226000A94102D2761E8018594180EA010221FA62
-:102270000EF3C7F1200462FA0EF20CFA07F05A408E
-:102280002CFA04F13043F0BD80EA010221FA0EF38A
-:10229000002162FA0EF260465A40F0BD8C46B1FB56
-:1022A000F2F102FB11C31B0243EA1063B3FBF2FC21
-:1022B00002FB1C331B024CEA002043EA1063B3FB11
-:1022C000F2FC02FB1C331B024CEA002043EA1063C1
-:1022D000B3FBF2FC02FB1C331B024CEA002043EA76
-:1022E0001063B3FBF2FC02FB1C324CEA002000231B
-:1022F0007047000001480068704700BF2C000020B4
-:102300000248016841F48071016070470004005880
-:102310008A60FF2102685162012180F821100021AA
-:1023200080F820100020704790F82010012901D17A
-:1023300002207047012280F82020022180F821101D
-:10234000CA210268516253210368596201688A6890
-:1023500042F02002FFF7DCBF002200F0C5BB000006
-:102360002DE9F84F4FF0000C674A684BDFF8A08169
-:102370004FF00F0982460F4633E0664DAA4514BF61
-:10238000072504258D40254348F82E50C1431C687D
-:1023900001EA040E7C68E50348BF40EA0E0EC3F86C
-:1023A00000E05C6801EA040E7C68A50348BF40EACF
-:1023B0000E0EC3F804E0146801EA040E7C68E5021E
-:1023C00048BF40EA0E0EC2F800E0546801EA040E6D
-:1023D00079688C0248BF40EA0E0EC2F804E00CF1A6
-:1023E000010C396831FA0CF000F07C80012000FA11
-:1023F0000CFE1EEA0100F2D07C68022C18BF122CE1
-:102400004FEA8C0110D14FEADC040AEB840401F09E
-:102410001C05266A09FA05FB26EA0B06D7F810B058
-:102420000BFA05F5354325624FEA4C040325DAF82B
-:10243000006097F804B0A540ED430BF0030B2E406D
-:102440000BFA04FB4BEA0606CAF800607E68012E10
-:1024500018BF022E03D0112E18BF122E17D1DAF892
-:102460000860D7F80CB02E400BFA04FB4BEA0606C6
-:10247000CAF80860DAF8046026EA0E0E7E68C6F331
-:10248000001606FA0CF646EA0E06CAF80460DAF8F8
-:102490000C603540BE6806FA04F42C43CAF80C40C0
-:1024A0007C68E4009BD54FEA9C0E58F82E5001F052
-:1024B0000C0109FA01F425EA0404BAF1904F08BFAF
-:1024C00000250ED0144DAA4508BF012509D0134D93
-:1024D000AA4508BF022504D0114DAA457FF44DAF8F
-:1024E00003254FE7BDE8F18F81B0002A14BF816159
-:1024F000816201B070470B4A136803421CBF106031
-:1025000000F0BCBB7047000000080058800800586D
-:10251000080001400010004800040048000800487E
-:10252000000C00480C0800588E4900E08E4981B02C
-:102530000A6802430A60096808400090009801B0E8
-:10254000704710B500F092FA884C606840010ED5D3
-:102550006068C0000BD4FFF7D3FEFFF7D1FE206800
-:1025600040F480302060216821F48031216000F047
-:10257000BEF8002000F088FB40B180797C49E16022
-:10258000E16821F47C5141EA0021E16000F039F872
-:102590007848794C016800220260026902F050021A
-:1025A00002610420FFF7C2FF0220FFF7BFFF0420F3
-:1025B000FFF7BAFF0220FFF7B7FF00220F213A20F2
-:1025C00000F008F93A2000F022F900216B48416040
-:1025D0000F218160046047F6FF71C16000F066FB67
-:1025E000CA206062FF2153206062A068C008C0005A
-:1025F000A060616200F09DFA4FF0FF3000F0FAFB3E
-:10260000FAE710B5AEB01CA84821FFF7A5FE01A857
-:102610001C21FFF7A1FE08A85021FFF79DFE53489B
-:10262000016821F01801016007215548026822F471
-:10263000C06242F4007202604FF48032006800F41D
-:10264000C06000904FF4807400981C9101201E908F
-:102650000021402020901D9227911F941CA8FFF775
-:10266000D4F86F2001900221002002910390049081
-:10267000059006900790012101A8FFF763FB43F640
-:102680000100089000214FF4804019900E91102015
-:1026900002211B901A91189408A800F08FFC2EB00C
-:1026A00010BD10B5374C384820604FF4E130606001
-:1026B0000020A060E06020610C2060610020A0612B
-:1026C0004FF40040E061002020626062A06220467A
-:1026D000FDF734FD00212046FEF7F3FF00212046E0
-:1026E000FEF7FAFF2046BDE81040FEF7CDBF2748B1
-:1026F00081B0016841F4801101603F21006800F45D
-:10270000801000900098224841604161016841F4C6
-:102710007C110160026942F47C120261016841F09F
-:102720003F010160026942F03F02026101B070475F
-:1027300038B50446FFF7DEFD14F1010F054609D058
-:1027400000F0ABF9041905E01248016821F004011A
-:10275000016030BFFFF7CEFD401BA042F4D331BD76
-:1027600000000000480000584C000058900000583D
-:10277000FECAFECA800800580028004064030020FA
-:1027800000040058F80100200038014050000058B3
-:10279000040C005810ED00E0704700000901020031
-:1027A00081B002D43C48815405E03C4802F00F025D
-:1027B000104400F8041C01B07047394A13684FF602
-:1027C000FF0100020B4000F4E06018433549084364
-:1027D0001060704738B5324B1C68C4F30223C3F154
-:1027E0000704052C28BF04241D1D072D34BF00231A
-:1027F000DB1E012505FA04F4641E2140994005FA08
-:1028000003F35B1E1A401143BDE83440C6E70100E4
-:1028100007D4012200F01F01234B8A40400943F8EE
-:102820002020704701000BD4012200F01F011F4B34
-:102830008A40400943F82020BFF34F8FBFF36F8FCA
-:10284000704710B5401EB0F1807F01D3012010BD4C
-:10285000174C60600F214FF0FF30FFF79FFF002201
-:10286000A26007202060002010BD010007D40122D3
-:1028700000F01F010F4B8A40400943F820207047A9
-:10288000010007D4012200F01F010B4B8A404009D0
-:1028900043F820207047000000E400E018ED00E05D
-:1028A0000CED00E00000FA0500E100E080E100E04E
-:1028B00010E000E000E200E080E200E032490020A9
-:1028C00008604FF4E0223148016841F47001016072
-:1028D0004FF0B041086840F0010008608A602C4861
-:1028E0000A6802402B480A60036823F0050303606E
-:1028F000426852085200426000222748C8600861BE
-:10290000086820F4802008608A6170474FF0B04169
-:102910000FF2D4000A68C2F3031250F822008A684A
-:1029200002F00C02042A04D0082A04D00C2A04D095
-:102930001CE01A481AE01A4818E0CA68CB68C3F3CA
-:10294000021302F003025B1C022A08BF134802D0E4
-:10295000032A08BF1248B0FBF3F2C868CB68C0F383
-:1029600006205B0F42435B1CB2FBF3F00D4A0FF2F3
-:102970003803106088681168C0F3031053F8200012
-:10298000B1FBF0F01060704708ED00E088ED00E06A
-:10299000FBFEF6FA94000058001004220024F40014
-:1029A0000048E80150000020010000000300000082
-:1029B000050000000100000001000000060000000A
-:1029C0000A000000200000000200000004000000D7
-:1029D000080000001000000040000000800000001F
-:1029E0000001000000020000A0860100400D03006D
-:1029F000801A060000350C0040420F0080841E0043
-:102A000000093D0000127A000024F40000366E0137
-:102A10000048E801006CDC0200000000000000003B
-:102A2000000000000000000070B50F4E0446B068C2
-:102A30000025A8B1FFF7A2FAB2684FF47A71B1FB92
-:102A4000F2F1B0FBF1F0FFF7FCFE48B9102C07D211
-:102A5000002221464FF0FF30FFF7BCFE746000E01B
-:102A60000125284670BD00BF2C000020164810B577
-:102A7000016841F4807101600320FFF79EFE002091
-:102A8000FFF7D2FF0024002814BF0124FEF738FC12
-:102A9000204610BD0D48406870470C48806870475C
-:102AA0000B480BE00A48016821F002010160704701
-:102AB0000748016821F00401016070470168490876
-:102AC0004900016070470000004000582C000020C1
-:102AD000042004E0DFF80800006800F4C0607047DC
-:102AE000000400587047000000B500BF1300964670
-:102AF0009446103928BFA0E80C50FAD85FEA417C10
-:102B000028BF0CC048BF40F8042BC90728BF20F8D5
-:102B1000022B48BF00F8012B00BD00004D4981B0D9
-:102B20000A6802430A60096808400090009801B0F2
-:102B3000704718B5484C89B0206840F400402060C8
-:102B400000F0BAFB4549002000F071FD68461421F1
-:102B5000FFF702FC0020029003214FF46040009038
-:102B600001910120FFF7DAFF69464FF09040FFF72F
-:102B7000F7FB606C4008400060641821009102205F
-:102B8000FFF7CCFF69463648FFF7EAFB606C20F0A0
-:102B900002006064FFF784FFFFF784FFFFF788FF00
-:102BA0000121012000F09AFB002000F064FE0120CA
-:102BB00000F061FE022000F05EFE012000F083FEC6
-:102BC0000121002000F093FE00F0E8FE2548264C8D
-:102BD00000F0DBFF0FF259020021202000F06DF918
-:102BE00004F23C50029021490FF22D000190009117
-:102BF000684600F02EFF04F25470039004F5C9619A
-:102C000040F23C5006900491059403A800F056FF52
-:102C100000F0C2FE0AB010BD80B50146114800F0B8
-:102C2000C0FFBDE804400021202000F053B900009F
-:102C300080B500F07AFF0021012000F04FFB6946CB
-:102C4000084800F0C4FF009800F051FF00F0D0FFEA
-:102C500001BD00004C00005808000058640300202B
-:102C600000040048B403002024000320BB3C0008FB
-:102C700000F048BB4FF0FF3000F0BCB8102808BF90
-:102C800001F02AB87047000001460648064AC37999
-:102C90008B4218BF904218BF0838F8D18B4218BF3A
-:102CA00000207047F873FF1F0070FF1F38B5040045
-:102CB00044D094F8210028B9002184F8201020463F
-:102CC000FEF72BFB00F049F8FF2510B100F03FF8AC
-:102CD00034E02168DFF8B0008A6802408A60216829
-:102CE0008A68636820690343A06903431A438A60C2
-:102CF0002168E068086120680169A26841EA024130
-:102D000001612068C16821F08001C1602068C16C48
-:102D100089088900C1642168CA6CE369606903435A
-:102D20001A43CA6420688168880609D400F020F834
-:102D300030B120684562042100F01FF8012032BD47
-:102D400020684562012184F82110002032BD2068EE
-:102D50004562042184F821107047022084F8210084
-:102D6000CA2021684862532022685062204626E02B
-:102D700020460BE02068C0F8248084F82110002051
-:102D800084F8200070470000BFFF8FFF70B5044635
-:102D900040F2E9362068C16821F0A001C160FFF768
-:102DA000A9FA05462068C168880606D4FFF7A2FA8A
-:102DB000401BB042F6D3032070BD002070BD70B53B
-:102DC00004462068C1684A0612D44FF0FF32C26040
-:102DD00040F2E936FFF78EFA05462068C1684806DA
-:102DE00006D4FFF787FA401BB042F6D3032070BD2C
-:102DF000002070BD2DE9FC47524CDFF84C91A569CD
-:102E00002840A0614FF0010A4FF0FF3830E0491C24
-:102E100054F831000642FAD004EBC1071840796833
-:102E20001040014208BFC7F804807E68304000F0BF
-:102E30008DF860620AFA00F086437E60EFF310813D
-:102E400072B6626A20690AFA02F2D2431040206127
-:102E5000022004EBC00353F8086C1640401E43F8F0
-:102E6000086CF6D181F31088606A59F82010884701
-:102E700063692069A2691840104207D0E069216A9D
-:102E8000084203D1002103EA0206C1E701F08AF8F3
-:102E9000EFF3108972B6216960690140A0690142AF
-:102EA00001BFE169206A0142FFF7E2FE89F3108861
-:102EB00001F079F8A561BDE8F38738B51446EFF362
-:102EC000108572B600F042F81F4941F8204085F3A2
-:102ED000108831BD10B5EFF3108272B6194B1C6922
-:102EE00004431C6153F83140204343F8310082F31E
-:102EF000108810BD506181F310887047EFF3108186
-:102F000072B6104AD3691843D061F4E72DE9F04155
-:102F10000C4C626A266A2062012101FA02F803E081
-:102F200039464046FFF7A6FE276AE5693D42F7D0DD
-:102F3000404600F00BF825EA0707E7612662606269
-:102F4000BDE8F08104000020840200200246002039
-:102F5000110C090404BF1020120412F07F4F04BFAB
-:102F6000083012020FF2180112F0704F04BF001D5A
-:102F70001201120FC0F11F00895C401A7047000057
-:102F80000403020201010101000000000000000032
-:102F9000DFF820130A68030903F47F2300019A4332
-:102FA00000F47F2000F082B9DFF808231368010CD9
-:102FB00023EA014343EA0043136070472DE9F843D5
-:102FC000054600242878DFF8EC624106A0464FF061
-:102FD000B0472DD5286B70B1B0F5800F06D0B0F595
-:102FE000000F18BFB0F5400F17D01FE0F86840F48D
-:102FF0008030F860EDE0386820F080603860FFF7DE
-:1030000079F981463868000140F1D080FFF772F904
-:10301000A0EB09000228F5D90324D7E0FFF76AF9ED
-:10302000A0EB0900022840F2C980F5E70124A04680
-:103030002868010531D5B06800F44078286C8045D7
-:103040002AD0FFF75DF9B8F1000FB16805D1286CFF
-:1030500021F440710143B1601EE0B06840F480305B
-:10306000B06021F44071B06820F48030B060286C0A
-:103070000143B160B068C0070ED5FFF73BF9804649
-:1030800041F28939B068800706D4FFF733F9A0EB25
-:1030900008004845F6D30324A0462878C10705D583
-:1030A0003168A869890840EA810131602878810780
-:1030B00005D53168E86921F4406101433160287821
-:1030C000C10644BFA86AFFF76FFF2878810644BF96
-:1030D000E86AFFF769FF2878410744BF286AFFF7CD
-:1030E00057FF2878010744BF686AFFF751FF286837
-:1030F000C1051BD53168686B21F040610143316027
-:10310000686BB0F1006F00F0BDF8686BB0F1806FD4
-:1031100075D100F0BDF804463868000160D5FFF7AE
-:10312000E9F8001B0228F7D94FF0030867E0FFF722
-:10313000E1F8001B02285BD9F6E7316821F0404135
-:10314000316020F08050326822F0406210433060DD
-:10315000A86BB0F1C05F00F095F8286841056DD507
-:103160003168E86B21F0405101433160E86BB0F108
-:10317000005F03D1F96841F48031F960E86BB0F188
-:10318000805F5BD100F084F804463868000146D5C2
-:10319000FFF7B0F8001B0228F7D94FF003084DE005
-:1031A000FFF7A8F8001B022841D9F6E700F061F804
-:1031B000A86821F4781100F071F8814638680001A0
-:1031C0007FF52CAF3969686901433961002C7FF4C0
-:1031D0002EAF3168286B21F440010143316027E7AD
-:1031E00000F047F8E86821F0606100F057F8044605
-:1031F000386800019BD539696869014339612868DD
-:103200008105AAD5A86BB0F1804F1CBFB0F1004F6B
-:10321000002892D1316821F04041084397E700F03F
-:1032200028F8286921F0604100F038F80446386831
-:103230000001B5D539696869014339612868C1045D
-:1032400005D5F168686C21F440410143F1602868BC
-:1032500081040BD5796AE86C21F030010143796271
-:10326000796AA86C890840EA810179624046BDE824
-:10327000F2833869696820F4FE4040EA0120386131
-:103280003969704703D1F96841F08071F96070477E
-:10329000396821F080613960FFF72CB8014339614A
-:1032A000386840F080603860FFF724B81043086049
-:1032B00070470000880000582048002101604160EC
-:1032C000704710B500F019F81C6819B1012904D134
-:1032D000204301E024EA000018600BE010B500F084
-:1032E0000CF85C6819B1012904D1204301E024EAFB
-:1032F0000000586082F3108810BDEFF3108272B6A0
-:103300000E4B704738B5EFF3108472B60B490C4D75
-:10331000086820B129688847686880470AE04868DB
-:1033200020B1A9688847E868804703E0286980479A
-:103330006869804784F3108831BD0000BC03002019
-:1033400004470008DFF8F0140A6892B200E0024671
-:10335000086880B28242FAD170472DE9FC410446E8
-:103360001825DFF8D884DFF8D864684308EB000735
-:103370003078062808D131787170347078754FF044
-:10338000FF307060002039E000F077F8B968091864
-:10339000B96008F10803B96832786A439A589142D3
-:1033A000327813D308F1150315FB02FC13F80C3027
-:1033B000062B25D008F108066B43F358994222BF2B
-:1033C00008F115036A439A5CEED219E0114633788E
-:1033D00069439A420BD008F1140308F1150C5B5CA9
-:1033E00015FB03F50CF805407A753B7500E07A751E
-:1033F00008F114025454317871703470BDE8F681CC
-:103400001146694308F115035B5C062B04D008F1F3
-:10341000140615FB03F574557B753A7508F1150212
-:103420005454EBE7F8B5DFF81834DFF810541E7881
-:10343000182402466243B0422A4404D118785870D6
-:10344000507D18700FE0167D507D92F815C005F183
-:1034500015076643062807F806C004D0167D143504
-:1034600014FB00F42E55012010731878062802BFB3
-:1034700000294FF0FF315960F1BD10B5DFF8C043AE
-:10348000606810F1010F0FD0FFF75CFF6168DFF893
-:10349000B423814261683CBF5388C918081A517827
-:1034A00048431178C84000E0002080B210BD2DE9EB
-:1034B000F84FDFF89053DFF890B3D5F80880D8F8CC
-:1034C0000000DBF800104A0500F06AF9DFF87063CD
-:1034D000DFF868A321F4806181604FF01809347827
-:1034E0000AF1080019FB04F14758FFF7C6FF8742AD
-:1034F00017D200270121B170062C3DD019FB04F42E
-:103500000AF108010AF108020959814223BF0AF1B0
-:1035100008010959091A002111510AEB04014C7DD7
-:10352000EAE7A9884118B94202D2AF880021E2E750
-:103530003F1ADFE7022802DA2878012800D07F1E30
-:10354000D8F80000C1684A07FAD500F02FF9DBF877
-:103550000C00000CBFB247EA0047CBF80C70FFF735
-:10356000F1FE7060A8680068816841F48061816044
-:10357000AFF30080BDE8F18FB8B20028DAD1FFF7D1
-:10358000E1FE70600320BDE8F24FFFF76EB92DE950
-:10359000F843EFF3108872B6AA4DA84BA8680168EB
-:1035A000CA224A6253204862A54A886820F4806093
-:1035B000886018201678374647431F44387B022816
-:1035C00026D13C68D7F810909078F0B17A7B012A28
-:1035D0000AD101213046FFF725FF88F3108879686A
-:1035E000304600F0F0F804E088F31088304600F030
-:1035F0009BF8A8680068CA214162224653214162B3
-:103600004846314600F02AF90BE0FFF750FF06E08C
-:10361000C8684207FCD500F07EF88C49086088F342
-:103620001088FF21A86802685162BDE8F183F8B5EF
-:10363000844CA160CA2209684A6253224A62824AC3
-:10364000136843F020031360136803F00703C3F10A
-:103650000403237095682D0C05F07F056D1C6570C3
-:10366000EDB29268C2F30E02521C628092B2521EF8
-:103670006A43A2F5A072DA404FF6FF739A422CBF5C
-:10368000A380A280724A136843F400231360714B35
-:103690001D6845F400251D6048BB6948674E01233D
-:1036A000837018254FF0FF33436000235FFA83FCDB
-:1036B00006F10C0715FB0CFC4FF0000E07F80CE0B0
-:1036C0005B1CDFB2062FF1DB06230370886820F451
-:1036D0008060886000F01FF8D0600320FFF7D0F80A
-:1036E000A1680868826842F48042826005E0C86888
-:1036F000410544BF0320FFF7B8F8A1680A68FF201E
-:103700005062002203210320FFF764F8BDE8F24075
-:103710000320FFF77CB8C86800F0800060F4906078
-:10372000C8604FF400207047F8B50746EFF31084E7
-:1037300072B60320FFF776F8424DAE683068CA21B2
-:1037400041623A4653214162182043494243895C11
-:1037500002291BD100213846FFF764FE3848017862
-:1037600006290ED1306838490A68530500F018F868
-:1037700021F480618160C1684A07FCD500F016F829
-:1037800004E04078884218BFFFF791FEA9680A68F4
-:10379000FF2050620320FFF73AF884F31088F1BD50
-:1037A00002D5C1684A07FCD481687047C16801F03E
-:1037B000800161F49061C1604FF4002023490860EA
-:1037C0000320FFF75DB82DE9F04180460F464246E1
-:1037D00018201A4942438C18207B022804BF404617
-:1037E000FFF7A2FFEFF3108572B60320FFF71AF878
-:1037F000144EB0680068CA21416253214162022020
-:103800002073A76067604046FFF7A7FD0C490A7860
-:103810004978914202D0FFF74AFE02E0A168081AF7
-:10382000A060FF20B1680A6850620320FEF7EFFF36
-:1038300085F31088BDE8F081282800406801002049
-:10384000DC030020A8030020082800400C080058D2
-:10385000000800588008005874010020104700003C
-:10386000444981B00A6802430A6009680840009030
-:10387000009801B0704778B585B0044668461421B9
-:10388000FEF76AFD0220FFF7EBFF00F010F800954D
-:10389000012001900021022003900291694656F810
-:1038A0002400FEF75DFD00F008F806B070BD0FF2D1
-:1038B000D400314E30F81450704756F824000022DE
-:1038C0002946FEF711BE0FF2BC012B4B31F8101048
-:1038D00053F820000122FEF707BE0FF2A801264B85
-:1038E00031F8101053F820000022FEF7FDBDF0B5AE
-:1038F00085B005460C4668461421FEF72DFD0DB92E
-:10390000042004E0012D18BF022D02D10820FFF78A
-:10391000A7FF2000194E0FF274070DD137F81500DC
-:10392000009000210191012002900221039100F0FA
-:103930001BF80120FEF7FCFE012C13D137F815000F
-:10394000009001210E480190029100F00DF80FF255
-:103950004400445D00220F2160B2FEF73BFF60B2DD
-:10396000FEF755FF05B0F0BD694656F82500FEF795
-:10397000F7BC00004C000058380000204400002034
-:1039800000002110200001000200000010000100D2
-:10399000020000000A06070000F07ABB7148724975
-:1039A000016001F12002426001F13002826001F108
-:1039B0003C02026201F14402C26001F14C02026168
-:1039C00001F16802426101F16C0282617831C161EA
-:1039D00000F070BB38B50446644D05F1100000F0EE
-:1039E000D4F860494868A1680160E168C160456039
-:1039F00005F11001816000F079FB5D4837E080B58A
-:103A000058494A6813680120187200F075FB0020BD
-:103A100002BD38B5564C554D07E0694605F110001A
-:103A200000F0D5F800982168884705F1100000F0F3
-:103A3000AFF80028F1D031BD80B54A494A68D16855
-:103A40000220087200F05DFB002002BD484841687A
-:103A5000084738B50446474D284600F096F84148D7
-:103A6000C068A1680160456000F054FB42482168CD
-:103A7000016061684160002032BD80B53949CA6883
-:103A800013681020187200F04BFB002002BD35496E
-:103A9000CA68394910680B68184738B5364C354D37
-:103AA00006E06946284600F092F800986168884769
-:103AB000284600F06DF80028F3D031BD38B5044633
-:103AC0002E4D284600F061F82D4800F05EF825489C
-:103AD0000069A1688160E168C160056121680160D9
-:103AE00061684160216941616169816131BD80B571
-:103AF0000146234800F055F8BDE802400FF20500EA
-:103B000000F01EBB38B5174C1D4D08E0694628462D
-:103B100000F05DF800992069006900F042F828463D
-:103B200000F036F80028F1D031BD10B5154C204614
-:103B300000F02BF80B4841690C60BDE8104000F024
-:103B400013BB1CB50F4C06E06946204600F03FF859
-:103B5000009800F019F8204600F01AF80028F3D079
-:103B600013BD000000000320B80A0320980A0320B8
-:103B7000CC030020B00A0320D40300203C0B032018
-:103B8000C4030020440B032070470060406070476E
-:103B9000EFF3108172B6026882420CBF0120002050
-:103BA00012E0EFF3108272B6086043684B60416028
-:103BB0004868016019E0EFF3108172B6436802684B
-:103BC0001A6042680068426081F31088704710B53F
-:103BD000EFF3108472B602680A600068FFE7FFF72F
-:103BE000EAFF84F3108810BD086082F310887047E4
-:103BF00010B590B004A80FF27C31DFF850433022AA
-:103C000000F0D8FA2068DFF848434FF6FC7101EA6B
-:103C10008001DFF840034118DFF83C030290E160C7
-:103C200000F5867003900FF2B9210FF2CD200190BC
-:103C300000916846FFF7CEFE01210220FFF74EFB00
-:103C400001210220FFF73DFB0020E070A07004A8D6
-:103C500000F0FAFA0FF2011200210820FFF72DF907
-:103C6000BE4A00210120FFF728F90FF29902002136
-:103C70001020FFF722F9BA4A00210220FFF71DF9B0
-:103C8000B84A00210420FFF718F9012060700020D5
-:103C9000A06004F11800FFF778FFFEF702FD04F1C1
-:103CA000100060600020207001220FF2011304F167
-:103CB0001001FDF771FD10B010BD80B5A44A9178D8
-:103CC00031B1002090700120BDE80240FFF716B925
-:103CD000014602F1180007E110B59D4CE07830B9BB
-:103CE0000120FFF7FAFD0121E170002105E001202C
-:103CF000FFF7E9FD0020E0700121BDE8104002203F
-:103D0000FFF7DFBA38B5EFF31084914D68780128DA
-:103D100021D10021697005F1180005F10801FFF7B4
-:103D200056FFE878A0B9A8680FF28113017A02293A
-:103D300072B607BFB0F80B20521D827AD21C00F178
-:103D4000080192B20020FDF730FD84F3108831BDE8
-:103D5000BDE83140AAE031BD10B5834CB4F809008C
-:103D60004FF66052811A04D0491E06D0491E08D071
-:103D70000BE0204600F070FA11E0204600F0A7FAB0
-:103D80000DE0204600F0C9FA09E0A0810120A073EF
-:103D9000E072212020720E2060720420A072214661
-:103DA0007248FFF7FEFEBDE81040A1E0F8B5684D8F
-:103DB00069682A78002400201AB1022A64D013D33B
-:103DC00058E00978012905D0022907D0102918BF29
-:103DD000202907D10120287003244BE001202870FE
-:103DE000042447E0012445E00E78E868022E11D053
-:103DF000102E02D0202E03D01CE0CC78C0681BE02F
-:103E0000CC78594805F1100100F108070A6840F81C
-:103E1000082F18E04068CA780979C36802EB0124CA
-:103E200003F10807052205F11001384600F0B2F948
-:103E3000052009E0CC784068016805F1100001F127
-:103E400008070168396004206F60A1B211B1022136
-:103E500029700FE0022E25D0102E1DD0202E1ED04E
-:103E600000210120FFF736F8002005F1100128702D
-:103E700001246960A2B201B069683D4BBDE8F04021
-:103E800001440020FDF788BC087802280AD01028D9
-:103E900002D0202803D0E3E700210220E2E700213E
-:103EA0000820DFE700210420DCE700001CB5284CD7
-:103EB00001206070E0680169A0688A68904205D3BB
-:103EC000C9681144884238BFFFF711FE04F1180099
-:103ED000FFF75EFE10B9BDE81C4009E013BD00000D
-:103EE00080B50146DFF88400FFF75BFEBDE80440C3
-:103EF00000211020FEF7EEBF704770B51446134A3C
-:103F0000134E12681D460123B3704FF6FC7303EA8B
-:103F10008203104AD3180A46DE683668A6F80900FC
-:103F2000F17206F10C00214600F034F90021002066
-:103F3000FFF7A3FD0120FEF7E9FF314605F1080078
-:103F4000B278BDE87040D21C00F024B93C40005863
-:103F5000880300200000032084080320FF390008A4
-:103F60007B3A0008393A00085C000020A0030020DA
-:103F7000AD3D00080000000000000000000000004F
-:103F80000000000000000000440008004005080197
-:103F90003A799C00F4010000FFFFFFFF4801010097
-:103FA0000000000070477047C0680840884201D197
-:103FB0000120704700207047C0690840884201D145
-:103FC000012070470020704710B56A4C022120463E
-:103FD000FFF7F2FF38B16068C043810703D5FFF7F0
-:103FE0005CFD022018E001212046FFF7E5FF38B113
-:103FF0006068C043C10703D5FFF70BFD01200BE04C
-:1040000008212046FFF7D8FF38B16068C043010798
-:1040100003D5FFF796FD0820A06010BD10B5554CE4
-:1040200000F033F818B96068C043810306D400F08B
-:104030002CF830B96068C043810302D5BDE8104058
-:1040400077E0082100F022F870B96068C0430103EE
-:104050000AD56068484940F40020606008688047DD
-:104060004FF40020A06010BD202100F00FF858B9D7
-:104070006068C043810207D5606840F4001060604A
-:10408000BDE81040FFF7E2BC10BD022120468BE7DF
-:104090003A48016841F4007101603948026842F40D
-:1040A0000072026040BF20BF3648016841F4004101
-:1040B0000160704780B53448016841F480110160A7
-:1040C000006800F48010009000982A48016841F0D0
-:1040D00001010160026842F4803202602C20FEF788
-:1040E00096FBBDE802402D20FEF791BB27480168F2
-:1040F000490849000160704725494FF48030086045
-:10410000704722484FF400114160016821F400110A
-:10411000016070471D48016821F00201016070478D
-:104120001A484FF400314160016821F40031016008
-:1041300070471648016841F400310160FFF7A7BCE1
-:1041400038B504460B4D08212846FFF72DFF30B146
-:1041500009480460686820F40020686031BDA04709
-:104160004FF40021A96031BD0848016821F0080121
-:1041700001607047000C0058E4030020D408005888
-:10418000200800580C04005850000058040C005837
-:10419000080C005862B38B0708D0521E11F8013B7F
-:1041A00000F8013B00F024808B07F6D1830740F034
-:1041B000208000BF103A07D330B4B1E83810103A6D
-:1041C000A0E83810F9D230BC530724BFB1E808107A
-:1041D000A0E8081044BF51F8043B40F8043BD20764
-:1041E00024BF31F8022B20F8022B44BF0B78037058
-:1041F0007047121F17D35B0009D151F8043B20F818
-:10420000023B1B0C121F20F8023BF6D20BE051F8C8
-:10421000043B00F8013B1B0A20F8023B1B0C121F59
-:1042200000F8013BF3D238BF121D521E24BF11F813
-:10423000013B00F8013BF8D870470000FFF75DFE36
-:104240009DF80E0005B000BDF8B500F10C026B46FC
-:1042500021214FF66640F1E770B5EFF31081027B44
-:10426000012A02D0022A07D00DE000F028F81378C6
-:1042700000F01FF814700CE000F021F8138800F033
-:1042800018F8148005E000F01AF8136800F011F82F
-:10429000146081F31088212101720E2141720421E2
-:1042A00081724FF660518181002181730121C172B9
-:1042B00070BD264623EA040435402C43704772B68D
-:1042C000D0F81120D0F80D40D0F81550704781B0CB
-:1042D000017B012902D0022904D008E0D0F80D109A
-:1042E000097807E0D0F80D100A88009203E0D0F8B2
-:1042F0000D10096800910E2141722122082181725E
-:1043000002724FF6615181810121C17200218173D6
-:10431000009A40F80F2F01B0704738B504462120AD
-:1043200020720E2060724220A0724FF66250A0816F
-:104330000120E0720020A0731D4D1E480168090C89
-:10434000A4F80F100068C0F30B00A4F811001A487D
-:1043500001781A4801F01F01E17441682175416834
-:10436000090AC4F815100268C4F819200169C4F8D4
-:104370001D104169C4F8211004F129018069C4F8B5
-:104380002500286802680A600C222B68191D04F1B8
-:104390002D00FFF7FFFE286800F11001102204F144
-:1043A0003900FFF7F7FE06480168C4F8491031BD2F
-:1043B00000000320002004E00075FF1F8075FF1F30
-:1043C0001C48000800EB81003D4AD0F88010914263
-:1043D00001D0012070470020704742F4806240F80D
-:1043E0002120704737481F2181610168C908C90031
-:1043F00041F0030101603448016841F004010160AB
-:1044000030BF7047704710B5304C00F048F80028B6
-:10441000FBD1042100F044F828B92D4800680104BC
-:1044200003D500F03FF800F057F8002203212046A2
-:10443000FFF7D3FF23480168C908C90041F0020112
-:1044400001602148016841F00401016030BF10BDE6
-:1044500010B51E4C00F026F800F021F80028FBD122
-:104460004FF0B040816801F00C01042911D10168BE
-:1044700041F48031016001688903FCD581688908B5
-:10448000890041F002018160816801F00C01082976
-:10449000FAD12046BDE81040002203219DE7032108
-:1044A00020468FE700220421204696E780B500F0E1
-:1044B0002DF80548016821F00401016030BF01BDFD
-:1044C000000400800004005810ED00E000140058C3
-:1044D0008804005800F022B84FF0B040016841F461
-:1044E0008071016001684905FCD5816889088900EF
-:1044F00041F001018160416A890889004162816857
-:1045000001F00C010429FAD170470000024801684B
-:1045100021F002010160704710E000E002480168EC
-:1045200041F002010160704710E000E019E050F82E
-:10453000042BD30744BFA9F101039A18091F0023D4
-:10454000042942F8043BF9D25FEA817C134604D582
-:104550004FF0000CA2F800C09B1CC90744BF00210B
-:10456000197050F8041B0029E1D170477047FEE72D
-:10457000FEE7FEE7FEE770477047704700F014B8AB
-:104580000248FBF7DCBE0248FCF7DDBFF801002063
-:10459000040300201020FDF7AEBFFEF7F8BFFFF7C1
-:1045A0003DBDFFF711BD000002490A688868821806
-:1045B0000A6070472C00002030B5016884684218FA
-:1045C000416802EB5103C9070BD54C4409E012F9CD
-:1045D000011B12F8015B002904F8015B05D5491C99
-:1045E000F9D19A42F3D10C3030BD491EF1D5F8E72C
-:1045F00010B500F013F802000023DB43002410681C
-:10460000984203D011000220ABBE1460506898425B
-:1046100003D0111D0220ABBE546010BD014870478D
-:10462000000000005400002010B5074979441831FB
-:10463000064C7C44163404E00A68081D114488477F
-:104640000146A142F8D110BD2C000000500000002E
-:104650004EF68851CEF20001086840F47000086000
-:10466000BFF34F8FBFF36F8F4FF00070E1EE100A72
-:1046700070470000B9FEFFFF940300005C000020BB
-:10468000940A000024000320000000002DFFFFFF1B
-:10469000900100005800000004000020000000000D
-:1046A0000000000000000000000000000100000009
-:1046B00002000000030000000400000000F00DF8FC
-:1046C000002801D0FFF7B0FFAFF300800020AFF368
-:1046D0000080FDF736FF00F002F80120704700F07F
-:1046E00001B800000746384600F002F8FBE700007A
-:1046F00080B5FFF77DFF024A11001820ABBEFBE733
-:1047000026000200AD440008D54400080744000814
-:1047100051440008E543000805440008014880476B
-:1047200001480047BD2800082D470008AFF300806E
-:10473000FFF78EFFFFF7C2FFFFF7FEBFFFF7FEBFD9
-:10474000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF9D
-:10475000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF8D
-:10476000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF7D
-:10477000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF6D
-:10478000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF5D
-:10479000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF4D
-:1047A000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF3D
-:1047B000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF2D
-:1047C000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF1D
-:1047D000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF0D
-:1047E000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFFD
-:1047F000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFED
-:10480000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFDC
-:10481000FFF7FEBFFFF7FEBFFFF7FEBF000100007E
-:10482000EC00F8FFF0000010FD000001FC001A048D
-:104830000048000400480004004800080048000C3C
-:0C4840000048000C004800093D00F8FF93
-:040000050800472D7B
+:1012F00081602020A86100202860304600F068BA94
+:101300003F4881B0016841F400210160006800F4A9
+:1013100000200090009801B070471CB50446394980
+:10132000206888421CD101F00FF801F00DF8364812
+:10133000816B21F4407141F480718163816B41F4D0
+:1013400000418163026842F480620260006800F438
+:101350008060009000982046BDE8164001F008B873
+:1013600013BD38B586B0044601A8142101F018F861
+:101370002168264A914240D12548264D416941F4D1
+:10138000804141610222416901F48041009100994C
+:10139000016841F002010160C021006800F0020014
+:1013A00000900098019101200390032107200491EF
+:1013B0000590029201A9184800F0F6FF174828602E
+:1013C0000F2068601020A8600020E860802028615D
+:1013D00000206861A861E8612862284600F020F8D2
+:1013E00008B101F0FFF96567AC62002200212420FA
+:1013F00001F016FA242001F030FA07B030BD0000E9
+:1014000050000058002800405800005800380140A3
+:101410004C0000580403002000040048440402402B
+:1014200038B5040001D1012032BD2168DFF8400247
+:10143000814204F1240500F042F8022068700A6835
+:10144000A0686FF30E120243E06802432069024372
+:1014500060690243A0690243E0690243206A0243D3
+:101460000A60204600F0DAF8A068B0F5804F04BFAB
+:1014700000216160696A207900F014F838B105280C
+:1014800005D2204600F0E4F800F012F803E0002056
+:1014900028636863A8630020A861012068700020A9
+:1014A000287032BD0860A96AE86A486060687047C1
+:1014B000296B00200860696BA86B486070470AD2EE
+:1014C000DFF8B00142181423B2FBF3F292002A6253
+:1014D000DFF8A40109E0DFF8A40142181423B2FBED
+:1014E000F3F292002A62DFF89801E861704738B59C
+:1014F00000F1240200245178022903D004209061D5
+:10150000012428E001680B6823F00E030B600168DA
+:101510000D686D086D000D60516A0B6823F48073CF
+:101520000B60012192F82030D56903F01C0399402B
+:101530006960936AD16A5960116B31B10B6823F409
+:1015400080730B60536B916B596001215170147063
+:10155000516901B18847204632BDF8B500F1240138
+:101560000423CA6914680268156891F8206006F0BF
+:101570001C0603FA06F73C4210D06F070ED514681C
+:10158000A50603D4156825F00405156000F03DF8A4
+:10159000C968002938D0BDE8F4400847022303FA9F
+:1015A00006F73C4213D0AF0711D51468A50605D441
+:1015B000156825F00A05156001224A7000F025F82B
+:1015C00000220A708968F9B1BDE8F4400847082391
+:1015D00003FA06F6344217D02B0715D5136823F00B
+:1015E0000E031360012291F82030CC6903F01C0334
+:1015F0009A40626001228A614A7000220A70096979
+:1016000011B1BDE8F4400847F1BD91F82020CC6944
+:1016100002F01C029340636070470000416C026856
+:10162000134B89089A4234BF164B174B03EB8101C9
+:10163000816402F0FF02083A1421B2FBF1F1134A6F
+:10164000C26401F01C01012202FA01F10165704738
+:1016500001790F4A02EB81024265491E0D4A8265FB
+:1016600001F0030101228A40C265704700000000BA
+:1016700008040240F8FFFDBF00000240F8FBFDBF78
+:1016800000040240000802401C080240800802409A
+:10169000FC080240400902407047000010B500F10C
+:1016A0007C010A78012A01D1022010BD01230B70B0
+:1016B00024224A6002681368146864086400146095
+:1016C0000022426623F00053006803602020486037
+:1016D0000020087010BD70B500F01EF801D1022086
+:1016E00070BD00F01FF822F0604209E070B500F014
+:1016F00013F801D1022070BD00F014F822F06062EE
+:1017000011438160204600F01AF82068066020200E
+:1017100068600020287070BD044604F17C052878BC
+:101720000128704701222A7024206860206806681A
+:101730000268520852000260206882687047FFB554
+:101740000FF254020FF25806D2E9003402A9C1E99F
+:101750000034D6E90071CDE90071416E11B9012163
+:10176000012213E001688A688968520E02F00702BC
+:10177000490F02AC655CA45C1DF801101DF8022045
+:10178000ED00E40095FBF1F194FBF2F2683041804A
+:101790000280FFBD000000000101010307010000FD
+:1017A00008040204080101017047000030B9124822
+:1017B00003601248124B0360FEF74ABD704730B910
+:1017C000104803600D480E4B0360FEF7F7BC7047EE
+:1017D00000680B49884204D107490868002818BFEF
+:1017E0000047704700680649884204D105490868E7
+:1017F000002818BF00477047E8030020F8010020C8
+:1018000000380140EC030020704770474FF0B040B3
+:10181000006800F0F000B02888BFB02070472DE9C4
+:10182000F041040051D0207881064FF0B04535D505
+:10183000A868E96810F00C0001F0030103D00C283F
+:1018400008BF012943D12868800702D5E069002834
+:101850003BD0FFF7DBFF616A884207D2084600F001
+:10186000D8FB002831D100F07AFA0FE0286820F088
+:10187000F000014329606968206A21F47F4141EA50
+:1018800000216960606A00F0C4FBF0B901F064F8FF
+:10189000DFF81808006801F0EDF8B0B92078C1074A
+:1018A0000DD5A868E96800F00C00082801F00301D4
+:1018B00003D00C2808BF03292CD12868800340F1ED
+:1018C00041816068002840F03D81012040E2E069EC
+:1018D00080B1296841F0010100F02EFB064628681E
+:1018E000800700F12C8100F029FD801B0328F6D32E
+:1018F00003202DE228684008400000F03EFA06462A
+:10190000286800F028FAC9D000F018FD801B0328D1
+:10191000F6D3EDE76068B0F5803F06D0B0F5A02FB4
+:10192000296807D141F480212960286840F480307B
+:10193000286006E021F4803129602A6822F48022A0
+:101940002A60606860B100F0F9FC064628688003F0
+:1019500000F1F88000F0F2FC801B6528F6D3C7E7A1
+:1019600000F0ECFC06462868400C10F0010000F086
+:10197000E98000F0E3FC801B6528F4D3B8E700F0B1
+:10198000DDFCC01B0328C0F01181B1E7E06878B12D
+:10199000296841F4807100F0CFFA064628684005B6
+:1019A00000F1178100F0CAFC801B0328F6D39FE7E3
+:1019B000286820F4807000F0E0F906462868800A64
+:1019C00010F0010000F0DC8000F0B8FC801B032860
+:1019D000F4D38DE700F0B2FCC01B0328C0F00B81EC
+:1019E00086E740F0010000F0CEF9074670688007F6
+:1019F00000F11C8100F0A2FCC01B0328F6D377E79E
+:101A0000706820F0040000F0BEF907467068C00856
+:101A100010F0010000F0198100F090FCC01B0428B8
+:101A2000F4D365E70528306806D140F00400306043
+:101A3000316841F0010105E0400840003060316844
+:101A400021F004013160A06841F2893768B100F0EB
+:101A500075FC80463068800700F10C8100F06EFC58
+:101A6000A0EB0800B842F5D342E700F067FC8046DF
+:101A7000306800F070F900F0FD8000F05FFCA0EB32
+:101A80000800B842F4D333E700F058FCC01B032829
+:101A9000C0F0FE802CE7B06840084000B06000F065
+:101AA0004DFC0746B06800F056F900F0F58000F0F4
+:101AB00045FCC01B0328F5D31AE700F03FFC801B50
+:101AC0000328C0F01F8113E700F038FC001B032837
+:101AD000C0F039810CE7286881010CD4296841F0F5
+:101AE00080712960E86840F08050E86000F026FCD2
+:101AF00004462868810100F12A8100F01FFC001BC8
+:101B00000328F6D3F4E60C2931D0286820F0807041
+:101B10002860E968DFF8980589088900E960E968C4
+:101B20000140E96000F00AFC04462868810140F1A8
+:101B30000E8100F003FC001B0328F6D3D8E600F06A
+:101B40000EF9ABE6207881071AD5A868E96800F09D
+:101B50000C00042801F0030104D00C2808BF02295E
+:101B60007FF414AF2868400503D5E06800283FF4EF
+:101B7000ACAE6968206921F0FE4141EA006169600C
+:101B80002168DFF8306511F0180F38D0606900283F
+:101B90003FF436AFC90670687FF523AF800709D4DC
+:101BA000706840F0010000F0EEF8074670688007AA
+:101BB0007FF5E5AE706840F0040000F0E4F80746F9
+:101BC000706800070DD400F0B9FBC01B0428F7D3E0
+:101BD0008EE66868216920F0FE4040EA0160686096
+:101BE000CEE77068A16920F4706040EA012070605F
+:101BF00000F0C6F8074600F0ADF87FF4EBAE2078B1
+:101C0000410737D5DFF8B0743868C10529D400F032
+:101C10009BFB00F093FB80463868C10521D400F09F
+:101C20008DFBA0EB08000328F6D361E6706820F076
+:101C3000040070607068C00810F00100DFD000F090
+:101C40007DFBC01B0428F5D352E600F099F8074647
+:101C500000F080F8D3D000F071FBC01B0328F7D34D
+:101C600046E6A06801287FF4DDAE306840F0010050
+:101C70003060E8E6217848060ED5A06A00283FF4D7
+:101C80000AAFB16841F00101B16000F057FB0746AF
+:101C9000B06880077FF5F8AEE06A002857D0A968E1
+:101CA000EA68022801F00C017FF42DAF236B02F0EB
+:101CB0000300984202BF02F07000636B984214D197
+:101CC000A36BC2F30620984202BF02F47810E36BC4
+:101CD00098420AD1236C02F06060984202BF02F081
+:101CE0006042606C82423FF4F6AE0C293FF4EDADE9
+:101CF000286841013FF5E9AD296821F0807100F0C5
+:101D00001BF90646286881013FF5D7AEE968DFF880
+:101D1000AC03A26B0140206B0143606B0143E06B9D
+:101D200041EA02210143206C0143606C0143E960F8
+:101D3000286840F080702860E96841F08051E960CF
+:101D400000F0FCFA0446286881017FF5BDAE002052
+:101D5000BDE8F0817068400810F001007047296804
+:101D6000606A21F0F001014329606868216A20F46B
+:101D70007F4040EA012068607047286000F0DEBACA
+:101D8000706840084000706000F0D8BA2DE9F84350
+:101D90000400884644D0DFF8286300F0C8F847D232
+:101DA00000F0CDF8074600F0C2F841D000F0C6FAC6
+:101DB000C01B0228F7D90320B7E000F0BFFA401B90
+:101DC000022843D9F7E700F0B9FAA0EB090002288E
+:101DD0004CD9F0E700F0B2FAA0EB0900022854D980
+:101DE000E9E700F0ABFA401B02285DD9E3E700F019
+:101DF000A5FA401B022867D9DDE700F09FFA401BD7
+:101E0000484577D3D7E7032802D13968890103E031
+:101E10000028396802D1890762D401E049055FD4FE
+:101E2000012082E000F08AFAC01B022872D9C2E7C2
+:101E3000207881074FF0B0470BD5B968A06821F032
+:101E4000F0010143B96000F079FA0546B868C003B3
+:101E5000B3D52078DFF8505281060AD52968606929
+:101E600021F0F001014300F067F881462868800303
+:101E7000A9D5207841060BD52968A069090909016F
+:101E800041EA101100F058F881462868C003A1D536
+:101E9000207841070BD5B968E06821F4E06101437F
+:101EA000B96000F04BFA0546B868800399D52078F0
+:101EB00001070CD5B868216920F4605040EAC100E0
+:101EC000B86000F03BFA0546B86840038FD520782B
+:101ED000C10717D56068022895D1396889039FD555
+:101EE000B968890840EA8100B86041F2893900F098
+:101EF00025FA0546B868616800F00C00B0EB810F68
+:101F00007FF47BAF306800F00700804505D200F019
+:101F100016F8074600F00BF884D100F01DFD00F024
+:101F2000DFFDBDE8F24300F0A5BDBDE8F2833068F7
+:101F300000F0070040457047296000F0FFB93168A4
+:101F4000C90848EAC101316000F0F8B938B54FF06E
+:101F5000B0445D4DA16811F00C0106D1FFF756FCAD
+:101F6000C0F3031055F8200032BD0429574A05D0AC
+:101F70000829574804D12168C90222D5104632BD2C
+:101F8000E16801F00301022904D0032904D121688A
+:101F9000C90207D5104605E0FFF738FCC0F303106F
+:101FA00055F82000E168E268E368C1F30621484380
+:101FB000C2F30211491C5B0FB0FBF1F05B1CB0FBDC
+:101FC000F3F032BD80B5FFF7C1FF3E49FFE7414A5C
+:101FD0000968C1F3031152F82110B0FBF1F002BD02
+:101FE00080B5FFF7EFFF00F010F8C1F3022106E023
+:101FF00080B5FFF7E7FF00F008F8C1F3C22112F83F
+:10200000211001F01F01C84002BD2E49324A096863
+:10201000704770B52C49B1282EBFCC6AC0F30310AD
+:1020200051F820402048056800F07AFD29492B4AE4
+:1020300005F00F0551F82510B4FBF1F10024B1FBB8
+:10204000F2F1B0F5007F0FF2B402204609D10FF291
+:10205000900353F820508D4214D2401C0328F8D925
+:1020600012E00FF28C0353F820508D420AD2401C2C
+:102070000328F8D308E000F061F9801B03280BD394
+:10208000032070BD52F820400D4D2868C00844EA76
+:10209000C000FFF772FE0646296801F00701A14261
+:1020A000E9D1002070BD0000080100583000002078
+:1020B000FFFFFEEE90000058000400588C80C11114
+:1020C0000040005808000058342A00080024F4009A
+:1020D0000048E801F42900084C49000840420F007C
+:1020E0001200000024000000360000004000000044
+:1020F000060000000C0000001000000000000000BE
+:10210000010000000200000003000000B3BBD9B1D1
+:10211000B2F5803F7DD2022A1ED98C46B1FBF2F186
+:1021200002FB11C31B0443EA1043B3FBF2FC02FBA6
+:102130001C3380B240EA0343B3FBF2F002FB1032DF
+:1021400040EA0C4000237047022A05D98446B0FBC0
+:10215000F2F002FB10C270474AB105D100F0010253
+:1021600049085FEA3000704700220023704700F002
+:10217000DFBC0B000200002100207047904271EB91
+:10218000030CF6D3B3F5803F2FD2F0B5B3FA83F743
+:10219000B1FA81F4A7F10F0E3D1B5340CEF120069A
+:1021A00002FA0EF2F3415340B5F10F0746D80F3C47
+:1021B0002C444140C4F12006A040F1414140B1FB14
+:1021C000F3F603FB1611A2FB0645001BA94102D240
+:1021D000761E8018594180EA010221FA0EF362FA54
+:1021E0000EF200215A403046F0BD30B4B1FBF3FC92
+:1021F00003FB1C11A2FB0C45001BA94103D2ACF14F
+:10220000010C8018594130BC02460B466046002143
+:102210007047B2F1807F65D3F0B5B2FA82F7B1FAB8
+:1022200081F4C7F10F063D1B22FA06F307F1110EE8
+:10223000F24120355A40B5F10F07B8D94140C4F1F9
+:102240002006A040F1414140B1FBF3FC03FB1C110F
+:10225000A2FB0C45001BA94103D2BCF1010C801864
+:1022600059410F2F12D30F3FC90341EA5041B1FB2F
+:10227000F3F603FB1611A2FB0645D4EBC030A941CF
+:1022800002D2761E8018594146EACC3C07B3414041
+:10229000C7F12006B840F1414140B1FBF3F603FB22
+:1022A0001611A2FB0645001BA94102D2761E80181A
+:1022B000594180EA010221FA0EF3C7F1200462FAC3
+:1022C0000EF20CFA07F05A402CFA04F13043F0BD3C
+:1022D00080EA010221FA0EF3002162FA0EF2604652
+:1022E0005A40F0BD8C46B1FBF2F102FB11C31B0258
+:1022F00043EA1063B3FBF2FC02FB1C331B024CEA03
+:10230000002043EA1063B3FBF2FC02FB1C331B0208
+:102310004CEA002043EA1063B3FBF2FC02FB1C33DF
+:102320001B024CEA002043EA1063B3FBF2FC02FB01
+:102330001C324CEA0020002370470000014800686E
+:10234000704700BF2C0000200248016841F48071F2
+:1023500001607047000400588A60FF2102685162E2
+:10236000012180F82110002180F820100020704702
+:1023700090F82010012901D102207047012280F835
+:102380002020022180F82110CA21026851625321C5
+:102390000368596201688A6842F02002FFF7DCBFD7
+:1023A000002200F0C7BB00002DE9F84F4FF0000CF1
+:1023B000674A684BDFF8A0814FF00F0982460F464D
+:1023C00033E0664DAA4514BF072504258D402543FB
+:1023D00048F82E50C1431C6801EA040E7C68E503EE
+:1023E00048BF40EA0E0EC3F800E05C6801EA040E44
+:1023F0007C68A50348BF40EA0E0EC3F804E01468E9
+:1024000001EA040E7C68E50248BF40EA0E0EC2F8FD
+:1024100000E0546801EA040E79688C0248BF40EA83
+:102420000E0EC2F804E00CF1010C396831FA0CF020
+:1024300000F07C80012000FA0CFE1EEA0100F2D0C0
+:102440007C68022C18BF122C4FEA8C0110D14FEA85
+:10245000DC040AEB840401F01C05266A09FA05FB7A
+:1024600026EA0B06D7F810B00BFA05F535432562BE
+:102470004FEA4C040325DAF8006097F804B0A54051
+:10248000ED430BF0030B2E400BFA04FB4BEA060660
+:10249000CAF800607E68012E18BF022E03D0112EEC
+:1024A00018BF122E17D1DAF80860D7F80CB02E40FA
+:1024B0000BFA04FB4BEA0606CAF80860DAF8046077
+:1024C00026EA0E0E7E68C6F3001606FA0CF646EAF9
+:1024D0000E06CAF80460DAF80C603540BE6806FAE9
+:1024E00004F42C43CAF80C407C68E4009BD54FEA06
+:1024F0009C0E58F82E5001F00C0109FA01F425EA5F
+:102500000404BAF1904F08BF00250ED0144DAA451F
+:1025100008BF012509D0134DAA4508BF022504D0E4
+:10252000114DAA457FF44DAF03254FE7BDE8F18F6C
+:1025300081B0002A14BF8161816201B070470B4AEB
+:10254000136803421CBF106000F088BB7047000096
+:10255000000800588008005808000140001000489A
+:102560000004004800080048000C00480C0800580F
+:102570008F4900E08F4981B00A6802430A60096808
+:1025800008400090009801B0704710B500F094FA30
+:10259000894C606840010ED56068C0000BD4FFF71D
+:1025A000D3FEFFF7D1FE206840F480302060216820
+:1025B00021F48031216000F0C0F8002000F054FBCD
+:1025C00040B180797D49E160E16821F47C5141EAC4
+:1025D0000021E16000F039F879487A4C0168002266
+:1025E0000260026902F0500202610420FFF7C2FF9C
+:1025F0000220FFF7BFFF0420FFF7BAFF0220FFF71A
+:10260000B7FF00220F213A2000F00AF93A2000F02B
+:1026100024F900216C4841600F218160046047F675
+:10262000FF71C16000F032FBCA206062FF215320BD
+:102630006062A068C008C000A060616200F094FA07
+:102640004FF0FF3000F0C6FBFAE710B5AEB01CA8A3
+:102650004821FFF7A5FE01A81C21FFF7A1FE08A84D
+:102660005021FFF79DFEFFF76FFE5348016821F0F0
+:102670001801016007215548026822F4C06242F443
+:10268000007202604FF48032006800F4C060009075
+:102690004FF4807400981C9101201E90002140206E
+:1026A00020901D9227911F941CA8FFF7B8F86F2067
+:1026B0000190022100200291039004900590069061
+:1026C0000790012101A8FFF761FB43F60100089084
+:1026D00000214FF4804019900E91102002211B9090
+:1026E0001A91189408A800F059FC2EB010BD10B52E
+:1026F000374C384820604FF4E13060600020A06023
+:10270000E06020610C2060610020A0614FF4004077
+:10271000E061002020626062A0622046FDF70EFDAD
+:1027200000212046FEF7D7FF00212046FEF7DEFFFE
+:102730002046BDE81040FEF7B1BF274881B00168D0
+:1027400041F4801101603F21006800F48010009086
+:102750000098224841604161016841F47C110160A8
+:10276000026942F47C120261016841F03F0101609C
+:10277000026942F03F02026101B0704738B5044679
+:10278000FFF7DCFD14F1010F054609D000F0ABF9AD
+:10279000041905E01248016821F00401016030BF0E
+:1027A000FFF7CCFD401BA042F4D331BD0000000078
+:1027B000480000584C00005890000058FECAFECA5D
+:1027C00080080058002800406403002000040058DE
+:1027D000F80100200038014050000058040C005857
+:1027E00010ED00E0704700000901020081B002D442
+:1027F0003C48815405E03C4802F00F02104400F8C8
+:10280000041C01B07047394A13684FF6FF010002FB
+:102810000B4000F4E06018433549084310607047EE
+:1028200038B5324B1C68C4F30223C3F10704052CEE
+:1028300028BF04241D1D072D34BF0023DB1E0125E6
+:1028400005FA04F4641E2140994005FA03F35B1E67
+:102850001A401143BDE83440C6E7010007D4012205
+:1028600000F01F01234B8A40400943F820207047A5
+:1028700001000BD4012200F01F011F4B8A404009C8
+:1028800043F82020BFF34F8FBFF36F8F704710B511
+:10289000401EB0F1807F01D3012010BD174C606055
+:1028A0000F214FF0FF30FFF79FFF0022A2600720AB
+:1028B0002060002010BD010007D4012200F01F019C
+:1028C0000F4B8A40400943F820207047010007D48D
+:1028D000012200F01F010B4B8A40400943F82020E1
+:1028E0007047000000E400E018ED00E00CED00E0AF
+:1028F0000000FA0500E100E080E100E010E000E007
+:1029000000E200E080E200E03249002008604FF47D
+:10291000E0223148016841F4700101604FF0B0419C
+:10292000086840F0010008608A602C480A6802408C
+:102930002B480A60036823F00503036042685208CD
+:102940005200426000222748C8600861086820F4ED
+:10295000802008608A6170474FF0B0410FF2D400C8
+:102960000A68C2F3031250F822008A6802F00C02CF
+:10297000042A04D0082A04D00C2A04D01CE01A48E7
+:102980001AE01A4818E0CA68CB68C3F3021302F0D1
+:1029900003025B1C022A08BF134802D0032A08BFA7
+:1029A0001248B0FBF3F2C868CB68C0F306205B0F97
+:1029B00042435B1CB2FBF3F00D4A0FF23803106088
+:1029C00088681168C0F3031053F82000B1FBF0F0E1
+:1029D0001060704708ED00E088ED00E0FBFEF6FABD
+:1029E00094000058001004220024F4000048E8017C
+:1029F000500000200100000003000000050000005E
+:102A00000100000001000000060000000A000000B4
+:102A10002000000002000000040000000800000088
+:102A200010000000400000008000000000010000D5
+:102A300000020000A0860100400D0300801A06007D
+:102A400000350C0040420F0080841E0000093D004C
+:102A500000127A000024F40000366E010048E801FC
+:102A6000006CDC020000000000000000000000001C
+:102A70000000000070B50F4E0446B0680025A8B1F4
+:102A8000FFF7A0FAB2684FF47A71B1FBF2F1B0FB34
+:102A9000F1F0FFF7FCFE48B9102C07D200222146C6
+:102AA0004FF0FF30FFF7BCFE746000E001252846C0
+:102AB00070BD00BF2C000020164810B5016841F41D
+:102AC000807101600320FFF79EFE0020FFF7D2FF18
+:102AD0000024002814BF0124FEF712FC204610BD7C
+:102AE0000D48406870470C48806870470B480BE001
+:102AF0000A48016821F00201016070470748016837
+:102B000021F0040101607047016849084900016033
+:102B100070470000004000582C000020042004E012
+:102B2000DFF80800006800F4C06070470004005837
+:102B30007047000000B500BF130096469446103958
+:102B400028BFA0E80C50FAD85FEA417C28BF0CC02F
+:102B500048BF40F8042BC90728BF20F8022B48BF04
+:102B600000F8012B00BD000018B53448344C89B082
+:102B7000016841F40041016000F08EFB3149002002
+:102B800000F045FD00F069FE0121012000F096FBF8
+:102B9000002000F0B2FF012000F0AFFF022000F0A3
+:102BA000ACFF012000F0D1FF0121002000F0E1FF87
+:102BB00001F036F8244801F02AF90FF25D020021F5
+:102BC000202000F06AF904F23C5002901F490FF2F5
+:102BD000310001900091684601F07DF804F25470D4
+:102BE000039004F5C96140F23C50069004910594AD
+:102BF00003A801F0A5F801F011F80AB010BD00001B
+:102C000080B50146104801F00EF9BDE804400021EE
+:102C1000202000F04FB9000080B500F04CFE0021EC
+:102C2000012000F04BFB6946074801F012F90098BB
+:102C300001F09FF801F01EF901BD000008000058E6
+:102C40002C00032064030020B40300203F3F000851
+:102C500000F048BB4FF0FF3000F0BCB8102808BFB0
+:102C600001F07CB97047000001460648064AC37966
+:102C70008B4218BF904218BF0838F8D18B4218BF5A
+:102C800000207047F873FF1F0070FF1F38B5040065
+:102C900044D094F8210028B9002184F8201020465F
+:102CA000FEF73BFB00F049F8FF2510B100F03FF8BC
+:102CB00034E02168DFF8B0008A6802408A60216849
+:102CC0008A68636820690343A06903431A438A60E2
+:102CD0002168E068086120680169A26841EA024150
+:102CE00001612068C16821F08001C1602068C16C69
+:102CF00089088900C1642168CA6CE369606903437B
+:102D00001A43CA6420688168880609D400F020F854
+:102D100030B120684562042100F01FF8012032BD67
+:102D200020684562012184F82110002032BD20680E
+:102D30004562042184F821107047022084F82100A4
+:102D4000CA2021684862532022685062204626E04B
+:102D500020460BE02068C0F8248084F82110002071
+:102D600084F8200070470000BFFF8FFF70B5044655
+:102D700040F2E9362068C16821F0A001C160FFF788
+:102D8000DDFA05462068C168880606D4FFF7D6FA42
+:102D9000401BB042F6D3032070BD002070BD70B55B
+:102DA00004462068C1684A0612D44FF0FF32C26060
+:102DB00040F2E936FFF7C2FA05462068C1684806C6
+:102DC00006D4FFF7BBFA401BB042F6D3032070BD18
+:102DD000002070BD2DE9FC47524CDFF84C91A569ED
+:102DE0002840A0614FF0010A4FF0FF3830E0491C45
+:102DF00054F831000642FAD004EBC1071840796854
+:102E00001040014208BFC7F804807E68304000F0DF
+:102E10008DF860620AFA00F086437E60EFF310815D
+:102E200072B6626A20690AFA02F2D2431040206147
+:102E3000022004EBC00353F8086C1640401E43F810
+:102E4000086CF6D181F31088606A59F82010884721
+:102E500063692069A2691840104207D0E069216ABD
+:102E6000084203D1002103EA0206C1E701F0DCF9C0
+:102E7000EFF3108972B6216960690140A0690142CF
+:102E800001BFE169206A0142FFF7E2FE89F3108881
+:102E900001F0CBF9A561BDE8F38738B51446EFF32F
+:102EA000108572B600F042F81F4941F8204085F3C2
+:102EB000108831BD10B5EFF3108272B6194B1C6942
+:102EC00004431C6153F83140204343F8310082F33E
+:102ED000108810BD506181F310887047EFF31081A6
+:102EE00072B6104AD3691843D061F4E72DE9F04176
+:102EF0000C4C626A266A2062012101FA02F803E0A2
+:102F000039464046FFF7A6FE276AE5693D42F7D0FD
+:102F1000404600F00BF825EA0707E7612662606289
+:102F2000BDE8F08104000020840200200246002059
+:102F3000110C090404BF1020120412F07F4F04BFCB
+:102F4000083012020FF2180112F0704F04BF001D7A
+:102F50001201120FC0F11F00895C401A7047000077
+:102F60000403020201010101000000000000000052
+:102F7000DFF820130A68030903F47F2300019A4352
+:102F800000F47F2000F082B9DFF808231368010CF9
+:102F900023EA014343EA0043136070472DE9F843F5
+:102FA000054600242878DFF8EC624106A0464FF081
+:102FB000B0472DD5286B70B1B0F5800F06D0B0F5B5
+:102FC000000F18BFB0F5400F17D01FE0F86840F4AD
+:102FD0008030F860EDE0386820F080603860FFF7FE
+:102FE000ADF981463868000140F1D080FFF7A6F9BD
+:102FF000A0EB09000228F5D90324D7E0FFF79EF9DA
+:10300000A0EB0900022840F2C980F5E70124A046A0
+:103010002868010531D5B06800F44078286C8045F7
+:103020002AD0FFF791F9B8F1000FB16805D1286CEB
+:1030300021F440710143B1601EE0B06840F480307B
+:10304000B06021F44071B06820F48030B060286C2A
+:103050000143B160B068C0070ED5FFF76FF9804635
+:1030600041F28939B068800706D4FFF767F9A0EB11
+:1030700008004845F6D30324A0462878C10705D5A3
+:103080003168A869890840EA8101316028788107A0
+:1030900005D53168E86921F4406101433160287841
+:1030A000C10644BFA86AFFF76FFF2878810644BFB6
+:1030B000E86AFFF769FF2878410744BF286AFFF7ED
+:1030C00057FF2878010744BF686AFFF751FF286857
+:1030D000C1051BD53168686B21F040610143316047
+:1030E000686BB0F1006F00F0BDF8686BB0F1806FF5
+:1030F00075D100F0BDF804463868000160D5FFF7CF
+:103100001DF9001B0228F7D94FF0030867E0FFF70D
+:1031100015F9001B02285BD9F6E7316821F0404120
+:10312000316020F08050326822F0406210433060FD
+:10313000A86BB0F1C05F00F095F8286841056DD527
+:103140003168E86B21F0405101433160E86BB0F128
+:10315000005F03D1F96841F48031F960E86BB0F1A8
+:10316000805F5BD100F084F804463868000146D5E2
+:10317000FFF7E4F8001B0228F7D94FF003084DE0F1
+:10318000FFF7DCF8001B022841D9F6E700F061F8F0
+:10319000A86821F4781100F071F8814638680001C0
+:1031A0007FF52CAF3969686901433961002C7FF4E0
+:1031B0002EAF3168286B21F440010143316027E7CD
+:1031C00000F047F8E86821F0606100F057F8044625
+:1031D000386800019BD539696869014339612868FD
+:1031E0008105AAD5A86BB0F1804F1CBFB0F1004F8C
+:1031F000002892D1316821F04041084397E700F060
+:1032000028F8286921F0604100F038F80446386851
+:103210000001B5D539696869014339612868C1047D
+:1032200005D5F168686C21F440410143F1602868DC
+:1032300081040BD5796AE86C21F030010143796291
+:10324000796AA86C890840EA810179624046BDE844
+:10325000F2833869696820F4FE4040EA0120386151
+:103260003969704703D1F96841F08071F96070479E
+:10327000396821F080613960FFF760B80143396136
+:10328000386840F080603860FFF758B81043086035
+:10329000704700008800005820480021016041600C
+:1032A000704710B500F019F81C6819B1012904D154
+:1032B000204301E024EA000018600BE010B500F0A4
+:1032C0000CF85C6819B1012904D1204301E024EA1B
+:1032D0000000586082F3108810BDEFF3108272B6C0
+:1032E0000E4B704738B5EFF3108472B60B490C4D96
+:1032F000086820B129688847686880470AE04868FC
+:1033000020B1A9688847E868804703E028698047BA
+:103310006869804784F3108831BD0000BC03002039
+:10332000B4490008DFF8F0140A6892B200E00246DF
+:10333000086880B28242FAD170472DE9FC41044608
+:103340001825DFF8D884DFF8D864684308EB000755
+:103350003078062808D131787170347078754FF064
+:10336000FF307060002039E000F077F8B968091884
+:10337000B96008F10803B96832786A439A589142F3
+:10338000327813D308F1150315FB02FC13F80C3047
+:10339000062B25D008F108066B43F358994222BF4B
+:1033A00008F115036A439A5CEED219E011463378AE
+:1033B00069439A420BD008F1140308F1150C5B5CC9
+:1033C00015FB03F50CF805407A753B7500E07A753E
+:1033D00008F114025454317871703470BDE8F681EC
+:1033E0001146694308F115035B5C062B04D008F114
+:1033F000140615FB03F574557B753A7508F1150233
+:103400005454EBE7F8B5DFF81834DFF810541E78A1
+:10341000182402466243B0422A4404D118785870F6
+:10342000507D18700FE0167D507D92F815C005F1A3
+:1034300015076643062807F806C004D0167D143524
+:1034400014FB00F42E55012010731878062802BFD3
+:1034500000294FF0FF315960F1BD10B5DFF8C043CE
+:10346000606810F1010F0FD0FFF75CFF6168DFF8B3
+:10347000B423814261683CBF5388C918081A517847
+:1034800048431178C84000E0002080B210BD2DE90B
+:10349000F84FDFF89053DFF890B3D5F80880D8F8EC
+:1034A0000000DBF800104A0500F06AF9DFF87063ED
+:1034B000DFF868A321F4806181604FF01809347847
+:1034C0000AF1080019FB04F14758FFF7C6FF8742CD
+:1034D00017D200270121B170062C3DD019FB04F44E
+:1034E0000AF108010AF108020959814223BF0AF1D1
+:1034F00008010959091A002111510AEB04014C7DF8
+:10350000EAE7A9884118B94202D2AF880021E2E770
+:103510003F1ADFE7022802DA2878012800D07F1E50
+:10352000D8F80000C1684A07FAD500F02FF9DBF897
+:103530000C00000CBFB247EA0047CBF80C70FFF755
+:10354000F1FE7060A8680068816841F48061816064
+:10355000AFF30080BDE8F18FB8B20028DAD1FFF7F1
+:10356000E1FE70600320BDE8F24FFFF7A4B92DE93A
+:10357000F843EFF3108872B6AA4DA84BA86801680B
+:10358000CA224A6253204862A54A886820F48060B3
+:10359000886018201678374647431F44387B022836
+:1035A00026D13C68D7F810909078F0B17A7B012A48
+:1035B0000AD101213046FFF725FF88F3108879688A
+:1035C000304600F0F0F804E088F31088304600F050
+:1035D0009BF8A8680068CA214162224653214162D3
+:1035E0004846314600F02AF90BE0FFF750FF06E0AD
+:1035F000C8684207FCD500F07EF88C49086088F363
+:103600001088FF21A86802685162BDE8F183F8B50F
+:10361000844CA160CA2209684A6253224A62824AE3
+:10362000136843F020031360136803F00703C3F12A
+:103630000403237095682D0C05F07F056D1C6570E3
+:10364000EDB29268C2F30E02521C628092B2521E18
+:103650006A43A2F5A072DA404FF6FF739A422CBF7C
+:10366000A380A280724A136843F400231360714B55
+:103670001D6845F400251D6048BB6948674E01235D
+:10368000837018254FF0FF33436000235FFA83FCFB
+:1036900006F10C0715FB0CFC4FF0000E07F80CE0D0
+:1036A0005B1CDFB2062FF1DB06230370886820F471
+:1036B0008060886000F01FF8D0600320FFF706F9F3
+:1036C000A1680868826842F48042826005E0C868A8
+:1036D000410544BF0320FFF7EEF8A1680A68FF2008
+:1036E0005062002203210320FFF79AF8BDE8F24060
+:1036F0000320FFF7B2B8C86800F0800060F4906063
+:10370000C8604FF400207047F8B50746EFF3108407
+:1037100072B60320FFF7ACF8424DAE683068CA219C
+:1037200041623A4653214162182043494243895C31
+:1037300002291BD100213846FFF764FE3848017882
+:1037400006290ED1306838490A68530500F018F888
+:1037500021F480618160C1684A07FCD500F016F849
+:1037600004E04078884218BFFFF791FEA9680A6814
+:10377000FF2050620320FFF770F884F31088F1BD3A
+:1037800002D5C1684A07FCD481687047C16801F05E
+:10379000800161F49061C1604FF40020234908600A
+:1037A0000320FFF793B82DE9F04180460F464246CB
+:1037B00018201A4942438C18207B022804BF404637
+:1037C000FFF7A2FFEFF3108572B60320FFF750F862
+:1037D000144EB0680068CA21416253214162022040
+:1037E0002073A76067604046FFF7A7FD0C490A7881
+:1037F0004978914202D0FFF74AFE02E0A168081A18
+:10380000A060FF20B1680A6850620320FFF725F826
+:1038100085F31088BDE8F081282800406801002069
+:10382000DC030020A8030020082800400C080058F2
+:10383000000800588008005874010020104700005C
+:10384000564900E0564981B00A6802430A60096897
+:1038500008400090009801B0704718B585B06846E0
+:103860001421FEF79DFD032001904FF460410024D8
+:10387000009102940120FFF7E3FF00F097F8474C16
+:103880002068400840002060182100910220FFF7C6
+:10389000D7FF69464348FEF787FD206820F0020005
+:1038A0002060FFF723F9FFF723F9FFF727F900F06E
+:1038B00011F806B010BD00B587B068460FF20821B8
+:1038C0001C2200F0C3FC00F072FA684600F010FD04
+:1038D00007B000BDF0B585B068461421FEF760FD65
+:1038E00000260025002400210FF2CC0000EBC102CD
+:1038F000907988B11368B3F1904F08D0294FBB423B
+:1039000008D0294FBB4204BF9088044304E090884C
+:10391000064301E090880543491C2229E4DB00208E
+:1039200002900121032003900191B0B270B1009088
+:103930000120FFF785FF0120FFF784FF00F036F834
+:103940000022B1B24FF09040FEF7F2FDA8B280B174
+:1039500000900220FFF774FF0220FFF773FF114E63
+:1039600069463046FEF720FD0022A9B23046FEF738
+:10397000DFFDA0B280B100900420FFF761FF0420BA
+:10398000FFF760FF084D69462846FEF70DFD00224F
+:10399000A1B22846FEF7CCFD05B0F0BD4C000058A2
+:1039A0004C010058000400480008004869464FF0E8
+:1039B0009040FEF7F9BC0000000000480100000044
+:1039C0000000004801000000000000480100000065
+:1039D0000000004801000000000000480100000055
+:1039E0000000004801000000000000480100000045
+:1039F0000000004801000000000000480100000035
+:103A00000000004801000000000000480100000024
+:103A10000000004801000000000000480100000014
+:103A20000000004801000000000000480100000004
+:103A300000000048010000000000004801000000F4
+:103A400000000048010000000000004801000000E4
+:103A500000000048010000000000004801000000D4
+:103A600000000048010000000000004801000000C4
+:103A700000000048010000000000004801000000B4
+:103A800000000048010000000000004801000000A4
+:103A90000000004801000000000000480100000094
+:103AA0000000004801000000000000480100000084
+:103AB0000000004801000000000000480100000074
+:103AC00000000048010000000000000000000000AD
+:103AD00000000000B839000824000320280003205B
+:103AE00022040400444981B00A6802430A6009685C
+:103AF00008400090009801B0704778B585B0044642
+:103B000068461421FEF74CFC0220FFF7EBFF00F0A3
+:103B100010F80095012001900021022003900291ED
+:103B2000694656F82400FEF73FFC00F008F806B09E
+:103B300070BD0FF2D400314E30F81450704756F873
+:103B4000240000222946FEF7F3BC0FF2BC012B4BE8
+:103B500031F8101053F820000122FEF7E9BC0FF2F3
+:103B6000A801264B31F8101053F820000022FEF770
+:103B7000DFBCF0B585B005460C4668461421FEF75B
+:103B80000FFC0DB9042004E0012D18BF022D02D155
+:103B90000820FFF7A7FF2000194E0FF274070DD180
+:103BA00037F81500009000210191012002900221B8
+:103BB000039100F01BF80120FEF7E0FD012C13D16A
+:103BC00037F81500009001210E480190029100F095
+:103BD0000DF80FF24400445D00220F2160B2FEF7A1
+:103BE0001FFE60B2FEF739FE05B0F0BD694656F81B
+:103BF0002500FEF7D9BB00004C000058380000201B
+:103C000044000020000021102000010002000000FC
+:103C100010000100020000000A06070000F0E4BBEB
+:103C200071487249016001F12002426001F13002E5
+:103C3000826001F13C02026201F14402C26001F1C2
+:103C40004C02026101F16802426101F16C02826181
+:103C50007831C16100F0DABB38B50446644D05F136
+:103C6000100000F0D4F860494868A1680160E1687C
+:103C7000C160456005F11001816000F0E3FB5D4823
+:103C800037E080B558494A6813680120187200F07F
+:103C9000DFFB002002BD38B5564C554D07E06946A4
+:103CA00005F1100000F0D5F800982168884705F16B
+:103CB000100000F0AFF80028F1D031BD80B54A49BE
+:103CC0004A68D1680220087200F0C7FB002002BDDC
+:103CD00048484168084738B50446474D284600F033
+:103CE00096F84148C068A1680160456000F0BEFBDD
+:103CF00042482168016061684160002032BD80B5A2
+:103D00003949CA6813681020187200F0B5FB00200A
+:103D100002BD3549CA68394910680B68184738B57B
+:103D2000364C354D06E06946284600F092F800987A
+:103D300061688847284600F06DF80028F3D031BD4F
+:103D400038B504462E4D284600F061F82D4800F0A5
+:103D50005EF825480069A1688160E168C16005617D
+:103D60002168016061684160216941616169816127
+:103D700031BD80B50146234800F055F8BDE802404A
+:103D80000FF2050000F088BB38B5174C1D4D08E058
+:103D90006946284600F05DF800992069006900F046
+:103DA00042F8284600F036F80028F1D031BD10B5B1
+:103DB000154C204600F02BF80B4841690C60BDE81B
+:103DC000104000F07DBB1CB50F4C06E06946204654
+:103DD00000F03FF8009800F019F8204600F01AF8BB
+:103DE0000028F3D013BD000000000320C00A032008
+:103DF000A00A0320CC030020B80A0320D40300202B
+:103E0000440B0320C40300204C0B032070470060C8
+:103E100040607047EFF3108172B6026882420CBFB7
+:103E20000120002012E0EFF3108272B608604368B0
+:103E30004B6041604868016019E0EFF3108172B691
+:103E4000436802681A6042680068426081F3108823
+:103E5000704710B5EFF3108472B602680A6000680C
+:103E6000FFE7FFF7EAFF84F3108810BD086082F3D4
+:103E70001088704710B590B004A80FF27C31DFF8BD
+:103E80005043302200F0E2F92068DFF848434FF653
+:103E9000FC7101EA8001DFF840034118DFF83C03C0
+:103EA0000290E16000F5867003900FF2B9210FF2E5
+:103EB000CD20019000916846FFF7CEFE012102203F
+:103EC000FFF7FCF901210220FFF7EBF90020E07079
+:103ED000A07004A800F004FA0FF2011200210820DB
+:103EE000FEF7DBFFBE4A00210120FEF7D6FF0FF2EE
+:103EF000990200211020FEF7D0FFBA4A00210220CB
+:103F0000FEF7CBFFB84A00210420FEF7C6FF0120D0
+:103F100060700020A06004F11800FFF778FFFEF742
+:103F2000E6FB04F1100060600020207001220FF217
+:103F3000011304F11001FDF739FC10B010BD80B57C
+:103F4000A44A917831B1002090700120BDE8024070
+:103F5000FEF7C4BF014602F1180007E110B59D4C01
+:103F6000E07830B90120FFF7FAFD0121E17000216E
+:103F700005E00120FFF7E9FD0020E0700121BDE828
+:103F800010400220FFF78DB938B5EFF31084914D42
+:103F90006878012821D10021697005F1180005F128
+:103FA0000801FFF756FFE878A0B9A8680FF281135F
+:103FB000017A022972B607BFB0F80B20521D827A2F
+:103FC000D21C00F1080192B20020FDF7F8FB84F347
+:103FD000108831BDBDE83140AAE031BD10B5834C39
+:103FE000B4F809004FF66052811A04D0491E06D079
+:103FF000491E08D00BE0204600F078FA11E0204678
+:1040000000F0AFFA0DE0204600F0D1FA09E0A081FF
+:104010000120A073E072212020720E206072042023
+:10402000A07221467248FFF7FEFEBDE81040A1E0F5
+:10403000F8B5684D69682A78002400201AB1022A70
+:1040400064D013D358E00978012905D0022907D09C
+:10405000102918BF202907D10120287003244BE024
+:1040600001202870042447E0012445E00E78E86828
+:10407000022E11D0102E02D0202E03D01CE0CC78BE
+:10408000C0681BE0CC78594805F1100100F1080721
+:104090000A6840F8082F18E04068CA780979C368B0
+:1040A00002EB012403F10807052205F1100138464F
+:1040B00000F0BCF8052009E0CC784068016805F103
+:1040C000100001F108070168396004206F60A1B297
+:1040D00011B1022129700FE0022E25D0102E1DD023
+:1040E000202E1ED000210120FEF7E4FE002005F165
+:1040F0001001287001246960A2B201B069683D4BCB
+:10410000BDE8F04001440020FDF750BB08780228CC
+:104110000AD0102802D0202803D0E3E70021022093
+:10412000E2E700210820DFE700210420DCE70000AF
+:104130001CB5284C01206070E0680169A0688A689D
+:10414000904205D3C9681144884238BFFFF711FE79
+:1041500004F11800FFF75EFE10B9BDE81C4009E04D
+:1041600013BD000080B50146DFF88400FFF75BFE59
+:10417000BDE8044000211020FEF79CBE704770B5DA
+:104180001446134A134E12681D460123B3704FF6AE
+:10419000FC7303EA8203104AD3180A46DE683668C5
+:1041A000A6F80900F17206F10C00214600F03EF875
+:1041B00000210020FFF7A3FD0120FEF797FE314606
+:1041C00005F10800B278BDE87040D21C00F02EB8AE
+:1041D0003C40005888030020000003208C08032086
+:1041E000833C0008FF3C0008BD3C00085C00002048
+:1041F000A003002031400008000000000000000083
+:104200000000000000000000000000004400080062
+:10421000400508013A799C00F4010000FFFFFFFF10
+:1042200048010100000000007047704762B38B072F
+:1042300008D0521E11F8013B00F8013B00F0248029
+:104240008B07F6D1830740F0208000BF103A07D3D8
+:1042500030B4B1E83810103AA0E83810F9D230BCC8
+:10426000530724BFB1E80810A0E8081044BF51F874
+:10427000043B40F8043BD20724BF31F8022B20F85E
+:10428000022B44BF0B7803707047121F17D35B00DB
+:1042900009D151F8043B20F8023B1B0C121F20F8F7
+:1042A000023BF6D20BE051F8043B00F8013B1B0A3D
+:1042B00020F8023B1B0C121F00F8013BF3D238BF61
+:1042C000121D521E24BF11F8013B00F8013BF8D823
+:1042D00070470000FFF753FF9DF80E0005B000BDCA
+:1042E000F8B500F10C026B4621214FF66640F1E76C
+:1042F000F8B500F10C026B460F214FF66840E9E774
+:10430000C0680840884201D10120704700207047F2
+:10431000C0690840884201D10120704700207047E1
+:1043200010B56A4C02212046FFF7F2FF38B16068F1
+:10433000C043810703D5FFF7F2FC022018E00121FA
+:104340002046FFF7E5FF38B16068C043C10703D5D9
+:10435000FFF7A1FC01200BE008212046FFF7D8FF62
+:1043600038B16068C043010703D5FFF72CFD082072
+:10437000A06010BD10B5554C00F033F818B9606856
+:10438000C043810306D400F02CF830B96068C04304
+:10439000810302D5BDE8104077E0082100F022F843
+:1043A00070B96068C04301030AD56068484940F4A9
+:1043B00000206060086880474FF40020A06010BDB6
+:1043C000202100F00FF858B96068C043810207D57A
+:1043D000606840F400106060BDE81040FFF778BCF2
+:1043E00010BD022120468BE73A48016841F4007174
+:1043F00001603948026842F40072026040BF20BF89
+:104400003648016841F400410160704780B5344886
+:10441000016841F480110160006800F48010009090
+:1044200000982A48016841F001010160026842F4E5
+:10443000803202602C20FEF710FABDE802402D20E9
+:10444000FEF70BBA27480168490849000160704728
+:1044500025494FF480300860704722484FF400111E
+:104460004160016821F40011016070471D48016836
+:1044700021F00201016070471A484FF40031416099
+:10448000016821F40031016070471648016841F469
+:1044900000310160FFF73DBC38B504460B4D0821E3
+:1044A0002846FFF72DFF30B109480460686820F402
+:1044B0000020686031BDA0474FF40021A96031BDE4
+:1044C0000848016821F0080101607047000C00589D
+:1044D000E4030020D4080058200800580C040058B9
+:1044E00050000058040C0058080C005870B5EFF349
+:1044F0001081027B012A02D0022A07D00DE000F0D1
+:1045000028F8137800F01FF814700CE000F021F880
+:10451000138800F018F8148005E000F01AF813680A
+:1045200000F011F8146081F31088212101720E212E
+:104530004172042181724FF66051818100218173A3
+:104540000121C17270BD264623EA040435402C4384
+:10455000704772B6D0F81120D0F80D40D0F8155041
+:10456000704781B0017B012902D0022904D008E004
+:10457000D0F80D10097807E0D0F80D100A880092E5
+:1045800003E0D0F80D10096800910E21417221223C
+:104590000821817202724FF6615181810121C1723D
+:1045A00000218173009A40F80F2F01B0704738B591
+:1045B0000446212020720E2060724220A0724FF625
+:1045C0006250A0810120E0720020A0731D4D1E48A2
+:1045D0000168090CA4F80F100068C0F30B00A4F8E0
+:1045E00011001A4801781A4801F01F01E17441686E
+:1045F00021754168090AC4F815100268C4F8192029
+:104600000169C4F81D104169C4F8211004F12901A1
+:104610008069C4F82500286802680A600C222B68AB
+:10462000191D04F12D00FFF701FE286800F11001AB
+:10463000102204F13900FFF7F9FD06480168C4F8BB
+:10464000491031BD00000320002004E00075FF1F69
+:104650008075FF1FCC4A000800EB8100404AD0F86B
+:104660008010914201D0012070470020704742F431
+:10467000806240F82120704780B500F097F83948F3
+:104680001F2181610168C908C90041F0030100F0E0
+:1046900026F861E000F092B810B500F087F8324CCF
+:1046A00000F04CF80028FBD1042100F048F828B9AC
+:1046B0002E480068010403D500F043F800F05CF8D0
+:1046C0000022032100F03FF826480168C908C9000C
+:1046D00041F0020100F003F8016030BF10BD01603D
+:1046E0002348016841F00401704710B51E4C00F0EA
+:1046F00028F800F023F80028FBD14FF0B040816883
+:1047000001F00C01042911D1016841F480310160EC
+:1047100001688903FCD581688908890041F002019C
+:104720008160816801F00C010829FAD1002203217F
+:1047300000F009F8BDE8104000F040B80321204621
+:104740008AE700220421204691E780B500F02EF888
+:104750000748016821F00401016030BF01BD00007D
+:104760000004008000040058001400588804005819
+:1047700010ED00E000F022B84FF0B040016841F4C5
+:104780008071016001684905FCD58168890889004C
+:1047900041F001018160416A8908890041628168B4
+:1047A00001F00C010429FAD17047000002480168A9
+:1047B00021F002010160704710E000E0024801684A
+:1047C00041F002010160704710E000E019E050F88C
+:1047D000042BD30744BFA9F101039A18091F002332
+:1047E000042942F8043BF9D25FEA817C134604D5E0
+:1047F0004FF0000CA2F800C09B1CC90744BF002169
+:10480000197050F8041B0029E1D170477047FEE78A
+:10481000FEE7FEE7FEE770477047704700F014B808
+:104820000248FBF78CBD0248FCF797BEF801002058
+:10483000040300201020FDF782BEFEF798BEFFF7AC
+:1048400099BDFFF76DBD000002490A6888688218AB
+:104850000A6070472C00002030B501688468421857
+:10486000416802EB5103C9070BD54C4409E012F92A
+:10487000011B12F8015B002904F8015B05D5491CF6
+:10488000F9D19A42F3D10C3030BD491EF1D5F8E789
+:1048900010B500F013F802000023DB430024106879
+:1048A000984203D011000220ABBE146050689842B9
+:1048B00003D0111D0220ABBE546010BD01487047EB
+:1048C000000000005400002010B507497944183159
+:1048D000064C7C44163404E00A68081D11448847DD
+:1048E0000146A142F8D110BD2C000000600000007C
+:1048F0004EF68851CEF20001086840F4700008605E
+:10490000BFF34F8FBFF36F8F4FF00070E1EE100ACF
+:1049100070470000B9FEFFFF940300005C00002018
+:10492000940A00002C000320000000002DFFFFFF70
+:10493000A001000058000000040000201DFFFFFF40
+:10494000BC0100000400000024000320000000005F
+:104950000000000000000000000000000100000056
+:1049600002000000030000000400000000F00DF849
+:10497000002801D0FFF7A8FFAFF300800020AFF3BD
+:104980000080FDF702FE00F002F80120704700F001
+:1049900001B800000746384600F002F8FBE70000C7
+:1049A00080B5FFF775FF024A11001820ABBEFBE788
+:1049B000260002004B47000875470008994600088A
+:1049C000EB460008794600089546000801488047F4
+:1049D0000148004709290008DD490008AFF30080BD
+:1049E000FFF786FFFFF7C2FFFFF7FEBFFFF7FEBF2F
+:1049F000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFEB
+:104A0000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFDA
+:104A1000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFCA
+:104A2000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFBA
+:104A3000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFAA
+:104A4000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF9A
+:104A5000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF8A
+:104A6000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF7A
+:104A7000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF6A
+:104A8000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF5A
+:104A9000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF4A
+:104AA000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF3A
+:104AB000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF2A
+:104AC000FFF7FEBFFFF7FEBFFFF7FEBF00010000CC
+:104AD000EC00F8FFF0000010FD000001FC001A04DB
+:104AE0000048000400480004004800080048000C8A
+:0E4AF0000048000C004800093D00F8FFF800E7
+:04000005080049DDC9
 :00000001FF
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/app_common.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/app_common.h
index 4defc5d7a..836f40dcf 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/app_common.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/app_common.h
@@ -1,12 +1,13 @@
+/* USER CODE BEGIN Header */
 /**
  ******************************************************************************
   * File Name          : app_common.h
   * Description        : App Common application configuration file for STM32WPAN Middleware.
   *
- ******************************************************************************
+  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
@@ -16,7 +17,7 @@
   *
   ******************************************************************************
   */
-
+/* USER CODE END Header */
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef APP_COMMON_H
 #define APP_COMMON_H
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/app_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/app_conf.h
index cdc70a942..c51682da7 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/app_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/app_conf.h
@@ -1,12 +1,12 @@
+/* USER CODE BEGIN Header */
 /**
  ******************************************************************************
   * File Name          : app_conf.h
   * Description        : Application configuration file for STM32WPAN Middleware.
-  *
- ******************************************************************************
+  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
@@ -16,6 +16,7 @@
   *
   ******************************************************************************
   */
+/* USER CODE END Header */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef APP_CONF_H
@@ -29,6 +30,35 @@
  * Application Config
  ******************************************************************************/
 
+/**
+ * Define Secure Connections Support
+ */
+#define CFG_SECURE_NOT_SUPPORTED       (0x00)
+#define CFG_SECURE_OPTIONAL            (0x01)
+#define CFG_SECURE_MANDATORY           (0x02)
+
+#define CFG_SC_SUPPORT                 CFG_SECURE_OPTIONAL
+
+/**
+ * Define Keypress Notification Support
+ */
+#define CFG_KEYPRESS_NOT_SUPPORTED      (0x00)
+#define CFG_KEYPRESS_SUPPORTED          (0x01)
+
+#define CFG_KEYPRESS_NOTIFICATION_SUPPORT             CFG_KEYPRESS_NOT_SUPPORTED
+   
+/**
+ * Numeric Comparison Answers
+ */   
+#define YES (0x01)
+#define NO  (0x00)
+
+/**
+ * Device name configuration for Generic Access Service
+ */
+#define CFG_GAP_DEVICE_NAME             "TEMPLATE"
+#define CFG_GAP_DEVICE_NAME_LENGTH      (8)
+
 /**
 *   Identity root key used to derive LTK and CSRK
 */
@@ -212,7 +242,7 @@
  * Select UART interfaces
  */
 #define CFG_UART_GUI          hw_uart1
-#define CFG_DEBUG_TRACE_UART    
+#define CFG_DEBUG_TRACE_UART    0
 /******************************************************************************
  * USB interface
  ******************************************************************************/
@@ -411,11 +441,11 @@ typedef enum
 /**< Add in that list all tasks that may send a ACI/HCI command */
 typedef enum
 {
-  CFG_TASK_BLE_HCI_CMD_ID,
-  CFG_TASK_SYS_HCI_CMD_ID,
-  CFG_TASK_HCI_ACL_DATA_ID,
-  CFG_TASK_SYS_LOCAL_CMD_ID,
-  CFG_TASK_TX_TO_HOST_ID,
+    CFG_TASK_BLE_HCI_CMD_ID,
+    CFG_TASK_SYS_HCI_CMD_ID,
+    CFG_TASK_HCI_ACL_DATA_ID,
+    CFG_TASK_SYS_LOCAL_CMD_ID,
+    CFG_TASK_TX_TO_HOST_ID,
 /* USER CODE BEGIN CFG_Task_Id_With_HCI_Cmd_t */
 
 /* USER CODE END CFG_Task_Id_With_HCI_Cmd_t */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/app_debug.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/app_debug.h
new file mode 100644
index 000000000..4224edbe0
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/app_debug.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : app_debug.h
+  * Description        : Header for app_debug.c module
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __APP_DEBUG_H
+#define __APP_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+  /* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/* Exported macros ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions ---------------------------------------------*/
+  void APPD_Init( void );
+  void APPD_EnableCPU2( void );
+/* USER CODE BEGIN EF */
+
+/* USER CODE END EF */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*__APP_DEBUG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/hw_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/hw_conf.h
index 6ea3b1986..a2c69aba0 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/hw_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/hw_conf.h
@@ -27,6 +27,34 @@
  * Semaphores
  * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
  *****************************************************************************/
+/**
+*  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
+*  The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
+*  When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
+*  after writing a raw (64bits data) or erasing one sector.
+*  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
+*  By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
+*  instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7
+
+/**
+*  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
+*  In order to protect its timing, the CPU1 may get this semaphore to prevent the  CPU2 to either
+*  write or erase in flash (as this will stall both CPUs)
+*  The PES bit shall not be used as this may stall the CPU2 in some cases.
+*/
+#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6
+
+/**
+*  Index of the semaphore used to manage the CLK48 clock configuration
+*  When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
+*  and should be released after the application switch OFF the clock when the USB is not used anymore
+*  When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
+*  More details in AN5289
+*/
+#define CFG_HW_CLK48_CONFIG_SEMID                               5
+
 /* Index of the semaphore used to manage the entry Stop Mode procedure */
 #define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/main.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/main.h
index 55097bac8..4b10d2beb 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/main.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/main.h
@@ -29,6 +29,7 @@ extern "C" {
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32wbxx_hal.h"
+#include "app_conf.h"
 
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/stm32wbxx_hal_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/stm32wbxx_hal_conf.h
index 7f1537260..d5db0e33f 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/stm32wbxx_hal_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Inc/stm32wbxx_hal_conf.h
@@ -39,6 +39,7 @@
 /*#define HAL_CRC_MODULE_ENABLED   */
 #define HAL_HSEM_MODULE_ENABLED
 /*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
 #define HAL_IPCC_MODULE_ENABLED
 /*#define HAL_IRDA_MODULE_ENABLED   */
 /*#define HAL_IWDG_MODULE_ENABLED   */
@@ -70,6 +71,7 @@
 #define USE_HAL_COMP_REGISTER_CALLBACKS      0u
 #define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
 #define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS       0u
 #define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
 #define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
 #define USE_HAL_PCD_REGISTER_CALLBACKS       0u
@@ -243,6 +245,10 @@
  #include "stm32wbxx_hal_i2c.h"
 #endif /* HAL_I2C_MODULE_ENABLED */
 
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
 #ifdef HAL_IPCC_MODULE_ENABLED
  #include "stm32wbxx_hal_ipcc.h"
 #endif /* HAL_IPCC_MODULE_ENABLED */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/app_debug.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/app_debug.c
new file mode 100644
index 000000000..14ed65c22
--- /dev/null
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/app_debug.c
@@ -0,0 +1,399 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * File Name          : app_debug.c
+  * Description        : Debug capabilities source file for STM32WPAN Middleware
+ ******************************************************************************
+  * @attention
+  *
+  * 
    © Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
    
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "app_common.h"
+
+#include "app_debug.h"
+#include "utilities_common.h"
+#include "shci.h"
+#include "tl.h"
+#include "dbg_trace.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+typedef PACKED_STRUCT
+{
+  GPIO_TypeDef* port;
+  uint16_t pin;
+  uint8_t enable;
+  uint8_t reserved;
+} APPD_GpioConfig_t;
+/* USER CODE END PTD */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define GPIO_NBR_OF_RF_SIGNALS                  9
+#define GPIO_CFG_NBR_OF_FEATURES                34
+#define NBR_OF_TRACES_CONFIG_PARAMETERS         4
+#define NBR_OF_GENERAL_CONFIG_PARAMETERS        4
+
+/**
+ * THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
+ */
+#define BLE_DTB_CFG     0
+/* USER CODE END PD */
+
+/* Private macros ------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+
+#ifdef CFG_DEBUG_TRACE_UART
+#if(CFG_HW_LPUART1_ENABLED == 1)
+extern void MX_LPUART1_UART_Init(void);
+#endif
+#if(CFG_HW_USART1_ENABLED == 1)
+extern void MX_USART1_UART_Init(void);
+#endif
+#endif
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * It provides timing information on the CPU2 activity.
+ * All configuration of (port, pin) is supported for each features and can be selected by the user
+ * depending on the availability
+ */
+static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
+{
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ISR - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* RNG_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVM_PROCESS - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* NVMA_START - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_EOP - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_WRITE - Set on Entry / Reset on Exit */
+    { GPIOA, LL_GPIO_PIN_0, 0, 0},  /* FLASH_ERASE - Set on Entry / Reset on Exit */
+};
+
+/**
+ * THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
+ * This table is relevant only for BLE
+ * It provides timing information on BLE RF activity.
+ * New signals may be allocated at any location when requested by ST
+ * The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
+ */
+#if( BLE_DTB_CFG == 7)
+static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
+{
+    { GPIOB, LL_GPIO_PIN_2, 0, 0},      /* DTB10 - Tx/Rx SPI */
+    { GPIOB, LL_GPIO_PIN_7, 0, 0},      /* DTB11 - Tx/Tx SPI Clk */
+    { GPIOA, LL_GPIO_PIN_8, 0, 0},      /* DTB12 - Tx/Rx Ready & SPI Select */
+    { GPIOA, LL_GPIO_PIN_9, 0, 0},      /* DTB13 - Tx/Rx Start */
+    { GPIOA, LL_GPIO_PIN_10, 0, 0},     /* DTB14 - FSM0 */
+    { GPIOA, LL_GPIO_PIN_11, 0, 0},     /* DTB15 - FSM1 */
+    { GPIOB, LL_GPIO_PIN_8, 0, 0},      /* DTB16 - FSM2 */
+    { GPIOB, LL_GPIO_PIN_11, 0, 0},     /* DTB17 - FSM3 */
+    { GPIOB, LL_GPIO_PIN_10, 0, 0},     /* DTB18 - FSM4 */
+};
+#endif
+/* USER CODE END PV */
+
+/* Global variables ----------------------------------------------------------*/
+/* USER CODE BEGIN GV */
+/* USER CODE END GV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+static void APPD_SetCPU2GpioConfig( void );
+static void APPD_BleDtbCfg( void );
+/* USER CODE END PFP */
+
+/* Functions Definition ------------------------------------------------------*/
+void APPD_Init( void )
+{
+/* USER CODE BEGIN APPD_Init */
+#if (CFG_DEBUGGER_SUPPORTED == 1)
+  /**
+   * Keep debugger enabled while in any low power mode
+   */
+  HAL_DBGMCU_EnableDBGSleepMode();
+  HAL_DBGMCU_EnableDBGStopMode();
+
+  /***************** ENABLE DEBUGGER *************************************/
+  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
+
+#else
+  GPIO_InitTypeDef gpio_config = {0};
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_ANALOG;
+
+  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOA, &gpio_config);
+  __HAL_RCC_GPIOA_CLK_DISABLE();
+
+  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  HAL_GPIO_Init(GPIOB, &gpio_config);
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+
+  HAL_DBGMCU_DisableDBGSleepMode();
+  HAL_DBGMCU_DisableDBGStopMode();
+  HAL_DBGMCU_DisableDBGStandbyMode();
+
+#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
+
+#if(CFG_DEBUG_TRACE != 0)
+  DbgTraceInit();
+#endif
+
+  APPD_SetCPU2GpioConfig( );
+  APPD_BleDtbCfg( );
+
+/* USER CODE END APPD_Init */
+  return;
+}
+
+void APPD_EnableCPU2( void )
+{
+/* USER CODE BEGIN APPD_EnableCPU2 */
+  SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
+  {
+    {{0,0,0}},                            /**< Does not need to be initialized */
+    {(uint8_t *)aGpioConfigList,
+    (uint8_t *)&APPD_TracesConfig,
+    (uint8_t *)&APPD_GeneralConfig,
+    GPIO_CFG_NBR_OF_FEATURES,
+    NBR_OF_TRACES_CONFIG_PARAMETERS,
+    NBR_OF_GENERAL_CONFIG_PARAMETERS}
+  };
+
+  /**< Traces channel initialization */
+  TL_TRACES_Init( );
+
+  /** GPIO DEBUG Initialization */
+  SHCI_C2_DEBUG_Init( &DebugCmdPacket  );
+
+/* USER CODE END APPD_EnableCPU2 */
+  return;
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void APPD_SetCPU2GpioConfig( void )
+{
+/* USER CODE BEGIN APPD_SetCPU2GpioConfig */
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+  uint16_t gpioc_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+  gpioc_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
+  {
+    if( aGpioConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aGpioConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOC:
+            gpioc_pin_list |= aGpioConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+    HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+    HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
+  }
+
+  if(gpioc_pin_list != 0)
+  {
+    gpio_config.Pin = gpioc_pin_list;
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_C2GPIOC_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOC, &gpio_config);
+    HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
+  }
+  
+/* USER CODE END APPD_SetCPU2GpioConfig */
+  return;
+}
+
+static void APPD_BleDtbCfg( void )
+{
+/* USER CODE BEGIN APPD_BleDtbCfg */
+#if (BLE_DTB_CFG != 0)
+  GPIO_InitTypeDef gpio_config = {0};
+  uint8_t local_loop;
+  uint16_t gpioa_pin_list;
+  uint16_t gpiob_pin_list;
+
+  gpioa_pin_list = 0;
+  gpiob_pin_list = 0;
+
+  for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
+  {
+    if( aRfConfigList[local_loop].enable != 0)
+    {
+      switch((uint32_t)aRfConfigList[local_loop].port)
+      {
+        case (uint32_t)GPIOA:
+            gpioa_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        case (uint32_t)GPIOB:
+            gpiob_pin_list |= aRfConfigList[local_loop].pin;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+
+  gpio_config.Pull = GPIO_NOPULL;
+  gpio_config.Mode = GPIO_MODE_AF_PP;
+  gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_config.Alternate = GPIO_AF6_RF_DTB7;
+
+  if(gpioa_pin_list != 0)
+  {
+    gpio_config.Pin = gpioa_pin_list;
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_C2GPIOA_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOA, &gpio_config);
+  }
+
+  if(gpiob_pin_list != 0)
+  {
+    gpio_config.Pin = gpiob_pin_list;
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_C2GPIOB_CLK_ENABLE();
+    HAL_GPIO_Init(GPIOB, &gpio_config);
+  }
+#endif
+
+/* USER CODE END APPD_BleDtbCfg */
+  return;
+}
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+*************************************************************/
+#if(CFG_DEBUG_TRACE != 0)
+void DbgOutputInit( void )
+{
+/* USER CODE BEGIN DbgOutputInit */
+#ifdef CFG_DEBUG_TRACE_UART
+if (CFG_DEBUG_TRACE_UART == hw_lpuart1)
+{
+#if(CFG_HW_LPUART1_ENABLED == 1)
+    MX_LPUART1_UART_Init();
+#endif
+}
+else if (CFG_DEBUG_TRACE_UART == hw_uart1)
+{
+#if(CFG_HW_USART1_ENABLED == 1)
+    MX_USART1_UART_Init();
+#endif
+}
+#endif
+
+/* USER CODE END DbgOutputInit */
+  return;
+}
+
+void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
+{
+/* USER CODE END DbgOutputTraces */
+  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
+
+/* USER CODE END DbgOutputTraces */
+  return;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/app_entry.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/app_entry.c
index bc9ca9496..fbf2037e9 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/app_entry.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/app_entry.c
@@ -28,7 +28,7 @@
 #include "stm32_seq.h"
 #include "stm_list.h"
 #include "stm32_lpm.h"
-#include "dbg_trace.h"
+#include "app_debug.h"
 
 /* Private includes -----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
@@ -72,7 +72,6 @@ static tListNode  SysEvtQueue;
 
 /* Private functions prototypes-----------------------------------------------*/
 static void SystemPower_Config( void );
-static void Init_Debug( void );
 static void appe_Tl_Init( void );
 static void APPE_SysUserEvtRx( TL_EvtPacket_t * p_evt_rx );
 static void shci_user_evt_proc( void );
@@ -97,7 +96,7 @@ void APPE_Init( void )
   HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
 
 /* USER CODE BEGIN APPE_Init_1 */
-  Init_Debug();
+  APPD_Init();
 
   /**
    * The Standby mode should not be entered before the initialization is over
@@ -131,47 +130,6 @@ void APPE_Init( void )
  * LOCAL FUNCTIONS
  *
  *************************************************************/
-static void Init_Debug( void )
-{
-#if (CFG_DEBUGGER_SUPPORTED == 1)
-  /**
-   * Keep debugger enabled while in any low power mode
-   */
-  HAL_DBGMCU_EnableDBGSleepMode();
-
-  /***************** ENABLE DEBUGGER *************************************/
-  LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-  LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
-
-#else
-
-  GPIO_InitTypeDef gpio_config = {0};
-
-  gpio_config.Pull = GPIO_NOPULL;
-  gpio_config.Mode = GPIO_MODE_ANALOG;
-
-  gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOA, &gpio_config);
-  __HAL_RCC_GPIOA_CLK_DISABLE();
-
-  gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  HAL_GPIO_Init(GPIOB, &gpio_config);
-  __HAL_RCC_GPIOB_CLK_DISABLE();
-
-  HAL_DBGMCU_DisableDBGSleepMode();
-  HAL_DBGMCU_DisableDBGStopMode();
-  HAL_DBGMCU_DisableDBGStandbyMode();
-
-#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
-
-#if(CFG_DEBUG_TRACE != 0)
-  DbgTraceInit();
-#endif
-
-  return;
-}
 
 /**
  * @brief  Configure the system for power optimization
@@ -246,8 +204,7 @@ static void shci_user_evt_proc ( void )
    */
 
   /**< Traces channel initialization */
-  TL_TRACES_Init( );
-
+  APPD_EnableCPU2( );
   UTIL_LPM_SetOffMode(1 << CFG_LPM_APP, UTIL_LPM_ENABLE);
 
   LST_remove_head( &SysEvtQueue, (tListNode **)&p_evt_rx );
@@ -315,33 +272,6 @@ void UTIL_SEQ_EvtIdle( UTIL_SEQ_bm_t task_id_bm, UTIL_SEQ_bm_t evt_waited_bm )
   UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
 }
 
-/**
-  * @brief  Initialisation of the trace mechanism
-  * @param  None
-  * @retval None
-  */
-#if(CFG_DEBUG_TRACE != 0)
-void DbgOutputInit( void )
-{
-
-  return;
-}
-
-/**
-  * @brief  Management of the traces
-  * @param  p_data : data
-  * @param  size : size
-  * @param  call-back :
-  * @retval None
-  */
-void DbgOutputTraces(  uint8_t *p_data, uint16_t size, void (*cb)(void) )
-{
-  HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
-
-  return;
-}
-#endif
-
 /* USER CODE BEGIN FD_WRAP_FUNCTIONS */
 void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin )
 {
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/hw_timerserver.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/hw_timerserver.c
index c842ba55e..e0e4fcb5d 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/hw_timerserver.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/hw_timerserver.c
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/hw_uart.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/hw_uart.c
index 9a553610d..ce910235c 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/hw_uart.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/hw_uart.c
@@ -6,7 +6,7 @@
   ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/main.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/main.c
index 8afb0ef26..96ea11292 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/main.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/main.c
@@ -108,7 +108,6 @@ int main(void)
   /* USER CODE BEGIN 1 */
 
   /* USER CODE END 1 */
-  
 
   /* MCU Configuration--------------------------------------------------------*/
 
@@ -137,9 +136,8 @@ int main(void)
 
   /* USER CODE END 2 */
 
-  /* Init code for STM32_WPAN */  
+  /* Init code for STM32_WPAN */
   APPE_Init();
-
   /* Infinite loop */
   /* USER CODE BEGIN WHILE */
 	while(1)
@@ -164,6 +162,7 @@ void SystemClock_Config(void)
 
   /** Configure LSE Drive Capability 
   */
+  HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
   /** Configure the main internal regulator output voltage 
   */
@@ -206,7 +205,6 @@ void SystemClock_Config(void)
   PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
   PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
   PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
-
   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
   {
     Error_Handler();
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/stm32_lpm_if.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/stm32_lpm_if.c
index f024b61e3..1418e0a36 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/stm32_lpm_if.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/stm32_lpm_if.c
@@ -70,6 +70,13 @@ static void Switch_On_HSI( void );
 void PWR_EnterOffMode( void )
 {
 /* USER CODE BEGIN PWR_EnterOffMode */
+
+  /**
+   * The systick should be disabled for the same reason than when the device enters stop mode because
+   * at this time, the device may enter either OffMode or StopMode.
+   */
+  HAL_SuspendTick();
+
   /************************************************************************************
    * ENTER OFF MODE
    ***********************************************************************************/
@@ -106,6 +113,8 @@ void PWR_ExitOffMode( void )
 {
 /* USER CODE BEGIN PWR_ExitOffMode */
 
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitOffMode */
 }
 
@@ -118,6 +127,16 @@ void PWR_ExitOffMode( void )
 void PWR_EnterStopMode( void )
 {
 /* USER CODE BEGIN PWR_EnterStopMode */
+  /**
+   * When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
+   * the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
+   *
+   * When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
+   * However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
+   * stop mode ( this will abort the Stop Mode entry ).
+   */
+  HAL_SuspendTick();
+
   /**
    * This function is called from CRITICAL SECTION
    */
@@ -202,6 +221,9 @@ void PWR_ExitStopMode( void )
 
   /* Release RCC semaphore */
   LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
+
+  HAL_ResumeTick();
+
 /* USER CODE END PWR_ExitStopMode */
 }
 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/stm32wbxx_hal_msp.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/stm32wbxx_hal_msp.c
index 12c69084e..92841a891 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/stm32wbxx_hal_msp.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/Core/Src/stm32wbxx_hal_msp.c
@@ -100,6 +100,7 @@ void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
   /* USER CODE END RTC_MspInit 0 */
     /* Peripheral clock enable */
     __HAL_RCC_RTC_ENABLE();
+    __HAL_RCC_RTCAPB_CLK_ENABLE();
   /* USER CODE BEGIN RTC_MspInit 1 */
   HAL_RTCEx_EnableBypassShadow(hrtc);
   /* USER CODE END RTC_MspInit 1 */
@@ -122,6 +123,7 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
   /* USER CODE END RTC_MspDeInit 0 */
     /* Peripheral clock disable */
     __HAL_RCC_RTC_DISABLE();
+    __HAL_RCC_RTCAPB_CLK_DISABLE();
   /* USER CODE BEGIN RTC_MspDeInit 1 */
 
   /* USER CODE END RTC_MspDeInit 1 */
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/EWARM/BLE_TransparentMode.ewp b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/EWARM/BLE_TransparentMode.ewp
index 7b4d9c4b5..43c974209 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/EWARM/BLE_TransparentMode.ewp
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/EWARM/BLE_TransparentMode.ewp
@@ -1054,6 +1054,9 @@
                 
                     $PROJ_DIR$\..\Core\Src\app_entry.c
                 
+                
+                    $PROJ_DIR$\..\Core\Src\app_debug.c
+                
                 
                     $PROJ_DIR$\..\Core\Src\stm32_lpm_if.c
                 
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/MDK-ARM/BLE_TransparentMode.uvprojx b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/MDK-ARM/BLE_TransparentMode.uvprojx
index 2f7575173..378b7cc3c 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/MDK-ARM/BLE_TransparentMode.uvprojx
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/MDK-ARM/BLE_TransparentMode.uvprojx
@@ -440,6 +440,11 @@
               1
               ../Core/Src/main.c
             
+            
+              app_debug.c
+              1
+              ../Core/Src/app_debug.c
+            
             
               stm32wbxx_hal_msp.c
               1
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/ble_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/ble_conf.h
index ec2d0e166..0a2c605bb 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/ble_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/ble_conf.h
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/ble_dbg_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/ble_dbg_conf.h
index 1f9b21135..4eb0239b4 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/ble_dbg_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/ble_dbg_conf.h
@@ -6,7 +6,7 @@
  ******************************************************************************
   * @attention
   *
-  * 
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/tm.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/tm.c
index f066f8113..095e23b4d 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/tm.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/STM32_WPAN/App/tm.c
@@ -193,6 +193,7 @@ void TM_SysCmdRspCb (TL_EvtPacket_t * p_cmd_resp)
 
     UTIL_SEQ_SetTask( 1<
    © Copyright (c) 2019 STMicroelectronics.
+  * 
    © Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.
    
   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/SW4STM32/BLE_TransparentMode/.cproject b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/SW4STM32/BLE_TransparentMode/.cproject
index a518959c2..a4efb1fea 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/SW4STM32/BLE_TransparentMode/.cproject
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode/SW4STM32/BLE_TransparentMode/.cproject
@@ -34,7 +34,7 @@
 								
 							
 							
-
    + @@ -99,11 +100,13 @@ This projects provides a reference template that can be used to build any firmwa + - + + @@ -114,14 +117,16 @@ This projects provides a reference template through the LL API that can be used + - + + - + + @@ -139,6 +145,7 @@ and out-of-window interrupts enabled. + @@ -147,6 +154,7 @@ conversion data are transferred by DMA into an array, indefinitely (circular mod + @@ -154,6 +162,7 @@ conversion data are transferred by DMA into an array, indefinitely (circular mod + @@ -162,6 +171,7 @@ uses the interrupt programming model. + @@ -170,6 +180,7 @@ conversion data are transferred by DMA into an array, indefinitely (circular mod + @@ -179,6 +190,7 @@ This example describes how to use the bsp API. + @@ -189,6 +201,7 @@ voltage applied on a specific pin with the Internal Voltage Reference. + @@ -197,6 +210,17 @@ This example shows how to make an analog watchdog using the COMP peripherals in + + + + + + + + + @@ -208,6 +232,7 @@ redundancy check) calculation unit computes the CRC code of a given buffer of + @@ -218,6 +243,7 @@ buffer of 32-bit data words, based on a user-defined generating polynomial. + @@ -228,6 +254,7 @@ modes (ECB, CBC, CTR). + @@ -237,6 +264,7 @@ Algorithm with ECB chaining mode in DMA mode. + @@ -248,6 +276,7 @@ different modes. + @@ -257,6 +286,7 @@ on reset or when returning from an exception. + @@ -265,6 +295,7 @@ How to use the default SysTick configuration with a 1 ms timebase to toggle LEDs + @@ -275,6 +306,7 @@ SRAM through the HAL API. + @@ -285,6 +317,7 @@ output signal. USART1 is used in DMA synchronized mode to send a countdown from + @@ -294,6 +327,7 @@ requests upon an External line 4 rising edge signal. + @@ -304,6 +338,7 @@ Flash memory. + @@ -313,6 +348,7 @@ protection of the internal Flash memory. + @@ -322,6 +358,7 @@ How to configure external interrupt lines. + @@ -330,6 +367,7 @@ How to configure and use GPIOs through the HAL API. + @@ -340,6 +378,7 @@ instead of Systick. + @@ -349,6 +388,7 @@ instead of Systick. + @@ -358,6 +398,7 @@ instead of Systick. + @@ -367,6 +408,7 @@ instead of Systick. + @@ -376,6 +418,7 @@ How to use a HW semaphore to synchronize 2 process. + @@ -384,6 +427,7 @@ How to enable, take then release semaphore using 2 different Process. + @@ -394,6 +438,7 @@ using an interrupt. + @@ -403,6 +448,7 @@ via DMA. + @@ -412,6 +458,7 @@ using an interrupt. + @@ -421,6 +468,7 @@ in polling mode. + @@ -430,6 +478,7 @@ in interrupt mode and with restart condition. + @@ -439,6 +488,7 @@ in interrupt mode and with restart condition. + @@ -448,6 +498,7 @@ using an interrupt when the device is in Stop mode. + @@ -457,6 +508,18 @@ using an interrupt when the device is in Stop 2 mode. + + + + + + + + + @@ -467,6 +530,7 @@ an MCU IWDG reset after a preset laps of time. + @@ -476,6 +540,7 @@ an MCU IWDG reset after a preset laps of time. + @@ -485,6 +550,7 @@ How to drive a LCD Glass using STM32WBxx hal driver. + @@ -495,6 +561,7 @@ to generate a PWM signal at the lowest power consumption. + @@ -504,6 +571,7 @@ as counter clock, to generate a PWM signal, in a low-power mode. + @@ -513,6 +581,7 @@ to count pulses. + @@ -522,6 +591,7 @@ the system from a low-power mode. + @@ -532,6 +602,7 @@ allows generating a public key from a private key. + @@ -541,6 +612,7 @@ allows generating a public key from a private key in interrupt mode. + @@ -550,6 +622,7 @@ How to compute a signed message regarding the Elliptic curve digital signature a + @@ -559,6 +632,7 @@ How to compute a signed message regarding the Elliptic curve digital signature a + @@ -568,6 +642,7 @@ How to determine if a given signature is valid regarding the Elliptic curve digi + @@ -577,6 +652,7 @@ How to determine if a given signature is valid regarding the Elliptic curve digi + @@ -586,6 +662,7 @@ allows ciphering/deciphering a text. + @@ -594,6 +671,7 @@ How to compute the Chinese Remainder Theorem (CRT) optimization. + @@ -602,6 +680,7 @@ How to compute the Chinese Remainder Theorem (CRT) optimization in interrupt mod + @@ -611,6 +690,7 @@ allows ciphering/deciphering a text in interrupt mode. + @@ -620,6 +700,7 @@ allows validating an external public key. + @@ -629,6 +710,7 @@ allows validating an external public key. + @@ -638,6 +720,7 @@ How to enter and exit the Low-power run mode. + @@ -647,6 +730,7 @@ an interrupt. + @@ -655,6 +739,7 @@ line. External DC supply must be used to supply Vdd. + @@ -664,6 +749,7 @@ reset or the RTC wakeup timer. + @@ -673,6 +759,7 @@ or RTC wakeup timer. + @@ -683,6 +770,7 @@ a section is created where the function is stored. + @@ -692,6 +780,7 @@ and access to QSPI memory in memory-mapped mode to check the data in a forever l + @@ -701,6 +790,7 @@ read data in DMA mode and compare the result in a forever loop. + @@ -710,6 +800,7 @@ read data in IT mode and compare the result in a forever loop. + @@ -719,6 +810,7 @@ Configuration of the clock recovery service (CRS) in Interrupt mode, using the R + @@ -727,6 +819,7 @@ Configuration of the clock recovery service (CRS) in Polling mode, using the RCC + @@ -735,6 +828,7 @@ Configuration of the system clock (SYSCLK) and modification of the clock setting + @@ -744,6 +838,7 @@ Configuration of the RNG using the HAL API. This example uses the RNG to generat + @@ -752,6 +847,7 @@ Configuration of the RNG using the HAL API. This example uses RNG interrupts to + @@ -761,6 +857,7 @@ Configuration and generation of an RTC alarm using the RTC HAL API. + @@ -769,6 +866,7 @@ Configuration of the calendar using the RTC HAL API. + @@ -777,6 +875,7 @@ Use of the LSI clock source autocalibration to get a precise RTC clock. + @@ -785,6 +884,7 @@ Configuration of the RTC HAL API to write/read data to/from RTC Backup registers + @@ -792,6 +892,7 @@ Configuration of the RTC HAL API to write/read data to/from RTC Backup registers + @@ -801,6 +902,7 @@ Use of the SAI HAL API to play an audio file in DMA circular mode and handle the + @@ -810,6 +912,7 @@ Data buffer transmission/reception between two boards via SPI using DMA. + @@ -818,6 +921,7 @@ Data buffer transmission/reception between two boards via SPI using DMA. + @@ -826,6 +930,7 @@ Data buffer transmission/reception between two boards via SPI using Interrupt mo + @@ -834,6 +939,7 @@ Data buffer transmission/reception between two boards via SPI using Interrupt mo + @@ -842,6 +948,7 @@ Data buffer transmission/reception between two boards via SPI using Polling mode + @@ -850,6 +957,7 @@ Data buffer transmission/reception between two boards via SPI using Polling mode + @@ -860,6 +968,7 @@ to transfer data from memory to TIMER Capture Compare Register 3 (TIMx_CCR3). + @@ -868,6 +977,7 @@ How to update the TIMER channel 1 period and duty cycle using the TIMER DMA burs + @@ -876,6 +986,7 @@ How to use the TIM peripheral to measure an external signal frequency. + @@ -886,6 +997,7 @@ pin is set to its active state). + @@ -895,6 +1007,7 @@ with the corresponding Interrupt requests for each channel. + @@ -904,6 +1017,7 @@ signals at four different frequencies. + @@ -913,6 +1027,7 @@ an external signal rising edge is received on the timer input pin. + @@ -922,6 +1037,7 @@ duty cycle of an external signal. + @@ -931,6 +1047,7 @@ mode. + @@ -940,6 +1057,7 @@ one second with the corresponding Interrupt request. + @@ -949,6 +1067,7 @@ Use of the TSC HAL API to perform continuous acquisitions of one channel in Inte + @@ -959,6 +1078,7 @@ between a board and an HyperTerminal PC application. + @@ -968,6 +1088,7 @@ an HyperTerminal PC application. + @@ -976,6 +1097,7 @@ Re-routing of the C library printf function to the UART. + @@ -985,6 +1107,7 @@ between two boards. + @@ -994,6 +1117,7 @@ between two boards. + @@ -1003,6 +1127,7 @@ between two boards. + @@ -1013,11 +1138,13 @@ generates an MCU WWDG reset when a predefined time period has elapsed. + - + + @@ -1030,6 +1157,7 @@ thresholds. + @@ -1039,6 +1167,7 @@ channel, from a software start. + @@ -1048,6 +1177,7 @@ channel, from a software start. + @@ -1056,6 +1186,7 @@ How to use an ADC peripheral with ADC low-power features. + @@ -1065,6 +1196,7 @@ in their intended use cases. + @@ -1073,6 +1205,7 @@ How to use an ADC peripheral with ADC oversampling. + @@ -1083,6 +1216,7 @@ at each software start. This example uses the DMA programming model + @@ -1093,6 +1227,7 @@ at each software start. This example uses the interrupt programming model + @@ -1103,6 +1238,7 @@ interrupt or DMA programming models, please refer to other examples). + @@ -1113,6 +1249,7 @@ by DMA into a table (circular mode). + @@ -1122,6 +1259,7 @@ internal temperature sensor and calculate the temperature in degrees Celsius. + @@ -1134,6 +1272,7 @@ uses LL unitary service functions for optimization purposes (performance and siz + @@ -1145,6 +1284,7 @@ uses the LL initialization function to demonstrate LL init usage. + @@ -1155,6 +1295,7 @@ to a GPIO. This example is based on the STM32WBxx COMP LL API. + @@ -1167,6 +1308,7 @@ uses LL unitary service functions for optimization purposes (performance and siz + @@ -1178,6 +1320,7 @@ different modes. + @@ -1190,6 +1333,7 @@ optimization purposes (performance and size). + @@ -1201,6 +1345,7 @@ optimization purposes (performance and size). + @@ -1212,6 +1357,7 @@ service functions for optimization purposes (performance and size). + @@ -1222,6 +1368,7 @@ service functions for optimization purposes (performance and size). + @@ -1233,6 +1380,7 @@ LL unitary service functions for optimization purposes (performance and size). + @@ -1243,6 +1391,7 @@ initialization functions to demonstrate LL init usage. + @@ -1255,6 +1404,7 @@ functions for optimization purposes (performance and size). + @@ -1267,6 +1417,7 @@ initialization function to demonstrate LL init usage. + @@ -1279,6 +1430,7 @@ for performance and size. + @@ -1289,6 +1441,7 @@ is initialized with LL initialization function to demonstrate LL init usage. + @@ -1299,6 +1452,7 @@ semaphore in the context of two processes accessing the same resource. + @@ -1308,6 +1462,7 @@ semaphore in the context of two processes accessing the same resource. + @@ -1319,6 +1474,7 @@ functions to optimize for performance and size. + @@ -1329,6 +1485,7 @@ LL unitary service functions to optimize for performance and size. + @@ -1339,6 +1496,7 @@ with LL unitary service functions to optimize for performance and size. + @@ -1349,6 +1507,7 @@ with LL initialization function to demonstrate LL init usage. + @@ -1359,6 +1518,7 @@ with LL unitary service functions to optimize for performance and size. + @@ -1370,6 +1530,7 @@ and size. + @@ -1380,6 +1541,7 @@ with LL unitary service functions to optimize for performance and size. + @@ -1390,6 +1552,7 @@ with LL unitary service functions to optimize for performance and size. + @@ -1401,6 +1564,7 @@ performance and size. + @@ -1412,6 +1576,7 @@ performance and size. + @@ -1424,6 +1589,7 @@ for performance and size. + @@ -1436,6 +1602,7 @@ functions to optimize for performance and size. + @@ -1447,6 +1614,7 @@ function to demonstrate LL init usage. + @@ -1459,6 +1627,7 @@ initialization function to demonstrate LL init usage. + @@ -1470,6 +1639,7 @@ initialization function to demonstrate LL init usage. + @@ -1479,6 +1649,7 @@ How to use the low-layer PKA API to generate an ECDSA signature. + @@ -1487,6 +1658,7 @@ How to use the low-layer PKA API to execute RSA modular exponentiation. + @@ -1497,6 +1669,7 @@ reset or a wakeup interrupt. + @@ -1505,6 +1678,7 @@ How to enter the Stop 2 mode. + @@ -1514,6 +1688,7 @@ Low-power run mode. + @@ -1523,6 +1698,7 @@ depending on Vdd voltage and low-power mode. + @@ -1532,6 +1708,7 @@ depending on Vdd voltage and low-power mode. + @@ -1541,6 +1718,7 @@ Use of the MSI clock source hardware autocalibration and LSE clock (PLL mode) to + @@ -1549,6 +1727,7 @@ Configuration of MCO pin (PA8) to output the system clock. + @@ -1557,6 +1736,7 @@ Use of the RCC LL API to start the HSE and use it as system clock. + @@ -1565,6 +1745,7 @@ Modification of the PLL parameters in run time. + @@ -1575,6 +1756,7 @@ functions for optimization purposes (performance and size). + @@ -1584,6 +1766,7 @@ functions for optimization purposes (performance and size). + @@ -1594,6 +1777,7 @@ uses LL unitary service functions for optimization purposes (performance and siz + @@ -1603,6 +1787,7 @@ initialization uses the LL initialization function. + @@ -1612,6 +1797,7 @@ functions for optimization purposes (performance and size). + @@ -1622,6 +1808,7 @@ functions for optimization purposes (performance and size). + @@ -1631,6 +1818,7 @@ uses LL unitary service functions for optimization purposes (performance and siz + @@ -1640,6 +1828,7 @@ uses LL unitary service functions for optimization purposes (performance and siz + @@ -1652,6 +1841,7 @@ LL unitary service functions for optimization purposes (performance and size). + @@ -1663,6 +1853,7 @@ LL initialization function to demonstrate LL init usage. + @@ -1674,6 +1865,7 @@ LL unitary service functions for optimization purposes (performance and size). + @@ -1684,6 +1876,7 @@ LL unitary service functions for optimization purposes (performance and size). + @@ -1694,6 +1887,7 @@ LL unitary service functions for optimization purposes (performance and size). + @@ -1704,6 +1898,7 @@ initialization uses LL unitary service functions for optimization purposes (perf + @@ -1714,6 +1909,7 @@ initialization uses LL unitary service functions for optimization purposes (perf + @@ -1727,6 +1923,7 @@ Configuration of the TIM peripheral to + @@ -1738,6 +1935,7 @@ uses LL unitary service functions for optimization purposes (performance and siz + @@ -1750,6 +1948,7 @@ for optimization purposes (performance and size). + @@ -1761,6 +1960,7 @@ LL unitary service functions for optimization purposes (performance and size). + @@ -1772,6 +1972,7 @@ LL unitary service functions for optimization purposes (performance and size). + @@ -1783,6 +1984,7 @@ LL unitary service functions for optimization purposes (performance and size). + @@ -1794,6 +1996,7 @@ LL initialization function to demonstrate LL Init. + @@ -1804,6 +2007,7 @@ uses LL unitary service functions for optimization purposes (performance and siz + @@ -1815,6 +2019,7 @@ uses LL unitary service functions for optimization purposes (performance and siz + @@ -1825,6 +2030,7 @@ done using LL unitary services functions for optimization purpose (performance a + @@ -1835,6 +2041,7 @@ done using LL unitary services functions for optimization purpose (performance a + @@ -1845,6 +2052,7 @@ using LL initialization function to demonstrate LL init usage. + @@ -1855,6 +2063,7 @@ using LL initialization function to demonstrate LL init usage. + @@ -1867,6 +2076,7 @@ purpose (performance and size). + @@ -1878,6 +2088,7 @@ functions for optimization purpose (performance and size). + @@ -1889,6 +2100,7 @@ functions for optimization purpose (performance and size). + @@ -1902,6 +2114,7 @@ initialization is done using LL unitary services functions for optimization purp + @@ -1915,6 +2128,7 @@ initialization is done using LL unitary services functions for optimization purp + @@ -1923,6 +2137,7 @@ Configuration of GPIO and USART1 peripherals to allow the characters received on + @@ -1931,6 +2146,7 @@ Configuration of GPIO and USART1 peripherals to allow the characters received on + @@ -1940,6 +2156,7 @@ Use of UTILS LL API to configure the system clock using PLL with HSI as source c + @@ -1949,6 +2166,7 @@ them into a global information buffer. + @@ -1960,11 +2178,13 @@ uses the LL unitary service functions for optimization purposes (performance and + - + + @@ -1979,6 +2199,7 @@ for performance improvement. + @@ -1988,6 +2209,7 @@ How to use the CRC peripheral through the STM32WBxx CRC HAL and LL API. + @@ -1999,6 +2221,7 @@ performance improvement. + @@ -2011,6 +2234,7 @@ and an interrupt. + @@ -2022,6 +2246,7 @@ for minimizing footprint and maximizing performance). + @@ -2031,6 +2256,7 @@ Data buffer transmission/reception between two boards via SPI using Polling mode + @@ -2039,6 +2265,7 @@ Data buffer transmission/reception between two boards via SPI using Polling mode + @@ -2048,6 +2275,7 @@ two boards via SPI using Polling (LL driver) and Interrupt modes (HAL driver). + @@ -2057,6 +2285,7 @@ two boards via SPI using Polling (LL driver) and Interrupt modes (HAL driver). + @@ -2067,6 +2296,7 @@ duty cycle. + @@ -2079,6 +2309,7 @@ and LL API, the LL API being used for performance improvement. + @@ -2090,14 +2321,16 @@ the STM32WBxx UART HAL and LL API, the LL API being used for performance improve + - + + - + + @@ -2113,6 +2347,7 @@ How to use the Blood Pressure profile as specified by the BLE SIG. + @@ -2121,6 +2356,7 @@ How to use the Point-to-Point communication using BLE component. + @@ -2129,6 +2365,7 @@ How to use data throughput via notification from server to client using BLE comp + @@ -2137,6 +2374,7 @@ How to use the Health Thermometer profile as specified by the BLE SIG. + @@ -2145,6 +2383,7 @@ How to use the Heart Rate profile as specified by the BLE SIG. + @@ -2153,6 +2392,7 @@ How to use the Heart Rate profile as specified by the BLE SIG. + @@ -2161,6 +2401,7 @@ How to use the Heart Rate profile as specified by the BLE SIG. + @@ -2169,6 +2410,7 @@ How to use the Human Interface Device profile as specified by the BLE SIG. + @@ -2176,6 +2418,7 @@ How to use the Human Interface Device profile as specified by the BLE SIG. + @@ -2184,6 +2427,7 @@ How to use multi BLE applications using a network processor architecture. + @@ -2192,6 +2436,7 @@ OTA implementation to download a new image into the user flash. + @@ -2200,6 +2445,7 @@ How to communicate with simple BLE peripheral with minimum activated features. + @@ -2208,6 +2454,7 @@ How to use the Proximity profile as specified by the BLE SIG. + @@ -2216,6 +2463,7 @@ How to communicate with the STM32CubeMonitor-RF Tool using the transparent mode. + @@ -2224,6 +2472,7 @@ How to communicate with the STM32CubeMonitor-RF Tool using the transparent mode. + @@ -2232,6 +2481,7 @@ This example is to demonstrate Point-to-Point communication using BLE component. + @@ -2239,6 +2489,7 @@ This example is to demonstrate Point-to-Point communication using BLE component. + @@ -2247,6 +2498,7 @@ This example is to demonstrate Point-to-Point communication using BLE component. + @@ -2255,6 +2507,7 @@ This example is to demonstrate Point-to-Point communication using BLE component. + @@ -2264,6 +2517,17 @@ How to use BLE application and Thread application in static concurrent mode. + + + + + + + + + @@ -2273,6 +2537,7 @@ How to use CKS feature to store AES crypto keys in secure area. + @@ -2284,6 +2549,7 @@ features to configure a microSD drive. + @@ -2293,6 +2559,7 @@ How to use mail queues with CMSIS RTOS API. + @@ -2301,6 +2568,7 @@ How to use mutexes with CMSIS RTOS API. + @@ -2309,6 +2577,7 @@ How to use message queues with CMSIS RTOS API. + @@ -2317,6 +2586,7 @@ How to use semaphores with CMSIS RTOS API. + @@ -2325,6 +2595,7 @@ How to use semaphore from ISR with CMSIS RTOS API. + @@ -2333,6 +2604,7 @@ How to perform thread signaling using CMSIS RTOS API. + @@ -2341,6 +2613,7 @@ This application shows the usage of CMSIS-OS Signal API from ISR context. + @@ -2349,6 +2622,7 @@ How to implement thread creation using CMSIS RTOS API. + @@ -2357,15 +2631,26 @@ How to use timers of CMSIS RTOS API. + - + + + + + + + + + @@ -2374,6 +2659,7 @@ How to use MAC 802.15.4 Association and Data exchange. + @@ -2383,6 +2669,7 @@ How to control the Thread stack via Cli commands. + @@ -2391,6 +2678,7 @@ How to transfer large blocks of data through the CoAP messaging protocol. + @@ -2399,6 +2687,7 @@ How to build Thread application based on Coap messages. + @@ -2407,6 +2696,7 @@ How to build Thread application based on Coap messages. + @@ -2415,6 +2705,7 @@ How to use Coap for sending message to multiple boards. + @@ -2423,6 +2714,7 @@ How to use Thread commissioning process. + @@ -2431,6 +2723,7 @@ How to exchange multicast Coap messages. + @@ -2439,6 +2732,7 @@ How to update Over The Air (OTA) FW application and Copro Wireless binary using + @@ -2447,6 +2741,7 @@ How to update Over The Air (OTA) FW application and Copro Wireless binary using + @@ -2455,6 +2750,7 @@ How to exchange a Coap message using the Thread protocol. + @@ -2463,6 +2759,7 @@ How to exchange a Coap message using the Thread protocol. + @@ -2472,6 +2769,7 @@ Use of the STMTouch driver with 1 touchkey sensor. + @@ -2482,6 +2780,7 @@ Communication Class (CDC) following the PSTN sub-protocol on the STM32WBxx devic + @@ -2490,6 +2789,7 @@ Compliant implementation of the Device Firmware Upgrade (DFU). + @@ -2498,6 +2798,7 @@ Use of the USB device application based on the Human Interface (HID). + @@ -2506,15 +2807,53 @@ How to use the USB device application based on the Mass Storage Class (MSC) on t + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + @@ -2523,6 +2862,7 @@ How to use OnOff cluster as a client on a centralized Zigbee network. + @@ -2531,6 +2871,7 @@ How to use OnOff cluster as a server on a centralized Zigbee network. + @@ -2539,11 +2880,67 @@ How to use OnOff cluster as a server on a distributed Zigbee network. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + - @@ -2555,16 +2952,19 @@ Cortex-M devices that can be plugged on a STM32 Nucleo board. + - + + - - - + + + +
    ParameterSizeDescriptionPossible values
    Description P-NUCLEO-WB55.USBDongle P-NUCLEO-WB55.NucleoNUCLEO-WB35CE

    Templates

    		 - CubeMxCubeMx
    Total number of templates: 1Total number of templates: 2 0 11

    Templates_LL

    		 - CubeMxCubeMx
    Total number of templates_ll: 1Total number of templates_ll: 2 0 11

    Examples

    Examples

    -

    BSP

    		 @@ -129,6 +134,7 @@ How to use the bsp API of the NUCLEO-WB55.USBDongle board. X --

    ADC

    		 - CubeMx-

    ADC_MultiChannelSingleConversion

    		 - CubeMx-

    ADC_Oversampling

    		 - CubeMx-

    ADC_SingleConversion_TriggerSW_IT

    		 - CubeMxCubeMx

    ADC_SingleConversion_TriggerTimer_DMA

    		 - CubeMxCubeMx

    BSP

    		 - CubeMxCubeMx

    COMP

    		 - CubeMxCubeMx

    COMP_CompareGpioVsVrefInt_Window_IT

    		 - CubeMx-

    CORTEX

    CORTEXM_SysTick

    		 +How to use the default SysTick configuration with a 1 ms timebase to toggle LEDs. +--CubeMx

    CRC

    		 - CubeMxCubeMx

    CRC_UserDefinedPolynomial

    		 - CubeMx-

    CRYP

    		 - CubeMx-

    CRYP_DMA

    		 - CubeMxCubeMx

    Cortex

    		 - CubeMx-

    CORTEXM_ModePrivilege

    		 - CubeMx-

    CORTEXM_SysTick

    		 - CubeMx-

    DMA

    		 - CubeMxCubeMx

    DMA_MUXSYNC

    		 - CubeMxCubeMx

    DMA_MUX_RequestGen

    		 - CubeMxCubeMx

    FLASH

    		 - CubeMxCubeMx

    FLASH_WriteProtection

    		 - CubeMxCubeMx

    GPIO

    		 - CubeMxCubeMx

    GPIO_IOToggle

    		 - CubeMxCubeMx

    HAL

    		 - CubeMxCubeMx

    HAL_TimeBase_RTC_ALARM

    		 - CubeMxCubeMx

    HAL_TimeBase_RTC_WKUP

    		 - CubeMxCubeMx

    HAL_TimeBase_TIM

    		 - CubeMxCubeMx

    HSEM

    		 - CubeMx-

    HSEM_ReadLock

    		 - CubeMx-

    I2C

    		 - CubeMx-

    I2C_TwoBoards_ComDMA

    		 - CubeMxCubeMx

    I2C_TwoBoards_ComIT

    		 - CubeMxCubeMx

    I2C_TwoBoards_ComPolling

    		 - CubeMx-

    I2C_TwoBoards_RestartAdvComIT

    		 - CubeMx-

    I2C_TwoBoards_RestartComIT

    		 - CubeMx-

    I2C_WakeUpFromStop

    		 - CubeMx-

    I2C_WakeUpFromStop2

    		 - CubeMxCubeMx

    I2S

    I2S_Audio

    		 +How to play an audio file through the I2S peripheral and DMA-based transfer +and using an external codec. +--X

    IWDG

    		 - CubeMx-

    IWDG_WindowMode

    		 - CubeMxCubeMx

    LCD

    		 - CubeMx-

    LPTIM

    		 - CubeMxCubeMx

    LPTIM_PWM_LSE

    		 - CubeMx-

    LPTIM_PulseCounter

    		 - CubeMxCubeMx

    LPTIM_Timeout

    		 - CubeMx-

    PKA

    		 - CubeMx-

    PKA_ECCscalarMultiplication_IT

    		 - CubeMx-

    PKA_ECDSA_Sign

    		 - CubeMxCubeMx

    PKA_ECDSA_Sign_IT

    		 - CubeMx-

    PKA_ECDSA_Verify

    		 - CubeMx-

    PKA_ECDSA_Verify_IT

    		 - CubeMxCubeMx

    PKA_ModularExponentiation

    		 - CubeMx-

    PKA_ModularExponentiationCRT

    		 - CubeMx-

    PKA_ModularExponentiationCRT_IT

    		 - CubeMx-

    PKA_ModularExponentiation_IT

    		 - CubeMx-

    PKA_PointCheck

    		 - CubeMx-

    PKA_PointCheck_IT

    		 - CubeMx-

    PWR

    		 - CubeMxCubeMx

    PWR_LPSLEEP

    		 - CubeMxCubeMx

    PWR_PVD

    		 - CubeMxCubeMx

    PWR_STANDBY_RTC

    		 - CubeMxCubeMx

    PWR_STOP2_RTC

    		 - CubeMxCubeMx

    QSPI

    		 - CubeMx-

    QSPI_MemoryMapped

    		 - CubeMx-

    QSPI_ReadWrite_DMA

    		 - CubeMxCubeMx

    QSPI_ReadWrite_IT

    		 - CubeMx-

    RCC

    		 - CubeMx-

    RCC_CRS_Synchronization_Polling

    		 - CubeMx-

    RCC_ClockConfig

    		 - CubeMxCubeMx

    RNG

    		 - CubeMxCubeMx

    RNG_MultiRNG_IT

    		 - CubeMx-

    RTC

    		 - CubeMxCubeMx

    RTC_Calendar

    		 - CubeMx-

    RTC_LSI

    		 - CubeMx-

    RTC_Tamper

    		 - CubeMxCubeMx

    RTC_TimeStamp

    		 - CubeMx-

    SAI

    		 - X-

    SPI

    		 - CubeMxCubeMx

    SPI_FullDuplex_ComDMA_Slave

    		 - CubeMxCubeMx

    SPI_FullDuplex_ComIT_Master

    		 - CubeMx-

    SPI_FullDuplex_ComIT_Slave

    		 - CubeMx-

    SPI_FullDuplex_ComPolling_Master

    		 - CubeMx-

    SPI_FullDuplex_ComPolling_Slave

    		 - CubeMx-

    TIM

    		 - CubeMx-

    TIM_DMABurst

    		 - CubeMx-

    TIM_InputCapture

    		 - CubeMx-

    TIM_OCActive

    		 - CubeMxCubeMx

    TIM_OCInactive

    		 - CubeMx-

    TIM_OCToggle

    		 - CubeMx-

    TIM_OnePulse

    		 - X-

    TIM_PWMInput

    		 - CubeMxCubeMx

    TIM_PWMOutput

    		 - CubeMxCubeMx

    TIM_TimeBase

    		 - CubeMx-

    TSC

    		 - XX

    UART

    		 - CubeMxCubeMx

    UART_HyperTerminal_IT

    		 - CubeMxCubeMx

    UART_Printf

    		 - CubeMxCubeMx

    UART_TwoBoards_ComDMA

    		 - CubeMx-

    UART_TwoBoards_ComIT

    		 - CubeMx-

    UART_TwoBoards_ComPolling

    		 - CubeMx-

    WWDG

    		 - CubeMxCubeMx
    Total number of examples: 100Total number of examples: 147 1 9947

    Examples_LL

    		 - CubeMxCubeMx

    ADC_ContinuousConversion_TriggerSW

    		 - X-

    ADC_ContinuousConversion_TriggerSW_Init

    		 - CubeMx-

    ADC_ContinuousConversion_TriggerSW_LowPower_Init

    		 - CubeMx-

    ADC_GroupsRegularInjected_Init

    		 - CubeMx-

    ADC_Oversampling_Init

    		 - CubeMxCubeMx

    ADC_SingleConversion_TriggerSW_DMA_Init

    		 - CubeMx-

    ADC_SingleConversion_TriggerSW_IT_Init

    		 - CubeMx-

    ADC_SingleConversion_TriggerSW_Init

    		 - CubeMxCubeMx

    ADC_SingleConversion_TriggerTimer_DMA_Init

    		 - CubeMx-

    ADC_TemperatureSensor

    		 - X-

    COMP

    		 - X-

    COMP_CompareGpioVsVrefInt_IT_Init

    		 - CubeMx-

    COMP_CompareGpioVsVrefInt_OutputGpio_Init

    		 - CubeMx-

    COMP_CompareGpioVsVrefInt_Window_IT_Init

    		 - CubeMxCubeMx

    CORTEX

    		 - CubeMx-

    CRC

    		 - CubeMxCubeMx

    CRC_UserDefinedPolynomial

    		 - CubeMx-

    CRS

    		 - CubeMx-

    CRS_Synchronization_Polling

    		 - CubeMx-

    DMA

    		 - X-

    DMA_CopyFromFlashToMemory_Init

    		 - CubeMxCubeMx

    EXTI

    		 - X-

    EXTI_ToggleLedOnIT_Init

    		 - CubeMxCubeMx

    GPIO

    		 - X-

    GPIO_InfiniteLedToggling_Init

    		 - CubeMxCubeMx

    HSEM

    		 - CubeMx-

    HSEM_DualProcess_IT

    		 - CubeMxCubeMx

    I2C

    		 - CubeMx-

    I2C_OneBoard_Communication_DMAAndIT_Init

    		 - CubeMx-

    I2C_OneBoard_Communication_IT

    		 - X-

    I2C_OneBoard_Communication_IT_Init

    		 - CubeMx-

    I2C_OneBoard_Communication_PollingAndIT_Init

    		 - CubeMx-

    I2C_TwoBoards_MasterRx_SlaveTx_IT_Init

    		 - CubeMxCubeMx

    I2C_TwoBoards_MasterTx_SlaveRx_DMA_Init

    		 - CubeMxCubeMx

    I2C_TwoBoards_MasterTx_SlaveRx_Init

    		 - CubeMx-

    I2C_TwoBoards_WakeUpFromStop2_IT_Init

    		 - CubeMx-

    I2C_TwoBoards_WakeUpFromStop_IT_Init

    		 - CubeMx-

    IWDG

    		 - CubeMxCubeMx

    LPTIM

    		 - X-

    LPTIM_PulseCounter_Init

    		 - CubeMxCubeMx

    LPUART

    		 - CubeMxCubeMx

    LPUART_WakeUpFromStop_Init

    		 - CubeMx-

    PKA

    		 - CubeMxCubeMx

    PKA_ModularExponentiation

    		 - CubeMx-

    PWR

    		 - CubeMxCubeMx

    PWR_EnterStopMode

    		 - CubeMxCubeMx

    PWR_OptimizedRunMode

    		 - CubeMxCubeMx

    PWR_SMPS_16MHZ_HSI

    		 - CubeMx-

    PWR_SMPS_64MHZ_MSI_PLL

    		 - CubeMx-

    RCC

    		 - CubeMx-

    RCC_OutputSystemClockOnMCO

    		 - CubeMx-

    RCC_UseHSEasSystemClock

    		 - CubeMx-

    RCC_UseHSI_PLLasSystemClock

    		 - CubeMxCubeMx

    RNG

    		 - CubeMx-

    RNG_GenerateRandomNumbers_IT

    		 - CubeMxCubeMx

    RTC

    		 - X-

    RTC_Alarm_Init

    		 - CubeMx-

    RTC_Calendar_Init

    		 - CubeMx-

    RTC_ExitStandbyWithWakeUpTimer_Init

    		 - CubeMxCubeMx

    RTC_Tamper_Init

    		 - CubeMx-

    RTC_TimeStamp_Init

    		 - CubeMx-

    SPI

    		 - X-

    SPI_OneBoard_HalfDuplex_DMA_Init

    		 - CubeMx-

    SPI_OneBoard_HalfDuplex_IT_Init

    		 - CubeMx-

    SPI_TwoBoards_FullDuplex_DMA_Master_Init

    		 - CubeMxCubeMx

    SPI_TwoBoards_FullDuplex_DMA_Slave_Init

    		 - CubeMxCubeMx

    SPI_TwoBoards_FullDuplex_IT_Master_Init

    		 - CubeMx-

    SPI_TwoBoards_FullDuplex_IT_Slave_Init

    		 - CubeMx-

    TIM

    		 - X-

    TIM_DMA_Init

    		 - CubeMx-

    TIM_InputCapture_Init

    		 - CubeMx-

    TIM_OnePulse

    		 - X-

    TIM_OutputCompare_Init

    		 - CubeMx-

    TIM_PWMOutput

    		 - X-

    TIM_PWMOutput_Init

    		 - CubeMx-

    TIM_TimeBase_Init

    		 - CubeMxCubeMx

    USART

    		 - X-

    USART_Communication_Rx_IT_Continuous_Init

    		 - CubeMx-

    USART_Communication_Rx_IT_Continuous_VCP_Init

    		 - CubeMx-

    USART_Communication_Rx_IT_Init

    		 - CubeMxCubeMx

    USART_Communication_Rx_IT_VCP_Init

    		 - CubeMx-

    USART_Communication_TxRx_DMA_Init

    		 - CubeMx-

    USART_Communication_Tx_IT_Init

    		 - CubeMxCubeMx

    USART_Communication_Tx_IT_VCP_Init

    		 - CubeMx-

    USART_Communication_Tx_Init

    		 - CubeMx-

    USART_Communication_Tx_VCP_Init

    		 - CubeMx-

    USART_WakeUpFromStop1_Init

    		 - CubeMx-

    USART_WakeUpFromStop_Init

    		 - CubeMx-

    UTILS

    		 - CubeMx-

    UTILS_ReadDeviceInfo

    		 - CubeMxCubeMx

    WWDG

    		 - CubeMxCubeMx
    Total number of examples_ll: 92Total number of examples_ll: 120 0 9228

    Examples_MIX

    		 - CubeMxCubeMx

    CRC

    		 - CubeMx-

    DMA

    		 - CubeMxCubeMx

    I2C

    		 - CubeMxCubeMx

    PWR

    		 - CubeMxCubeMx

    SPI

    		 - CubeMx-

    SPI_FullDuplex_ComPolling_Slave

    		 - CubeMx-

    SPI_HalfDuplex_ComPollingIT_Master

    		 - CubeMxCubeMx

    SPI_HalfDuplex_ComPollingIT_Slave

    		 - CubeMxCubeMx

    TIM

    		 - CubeMxCubeMx

    UART

    		 - CubeMxCubeMx

    UART_HyperTerminal_TxPolling_RxIT

    		 - CubeMx-
    Total number of examples_mix: 12Total number of examples_mix: 20 0 128

    Applications

    Applications

    BLE

    BLE_Beacon

    		 @@ -2105,6 +2338,7 @@ How to advertize 3 types of beacon ( tlm, uuid, url ). - CubeMx-

    BLE_BloodPressure

    		 - CubeMx-

    BLE_CableReplacement

    		 - X-

    BLE_DataThroughput

    		 - X-

    BLE_HealthThermometer

    		 - CubeMx-

    BLE_HeartRate

    		 X CubeMxX

    BLE_HeartRateFreeRTOS

    		 - CubeMxX

    BLE_HeartRate_ota

    		 - XX

    BLE_Hid

    		 - X-

    BLE_MeshLightingDemo

    		 X X-

    BLE_MultiAppAt

    		 - X-

    BLE_Ota

    		 - XX

    BLE_Peripheral_Lite

    		 - X-

    BLE_Proximity

    		 - X-

    BLE_TransparentMode

    		 - CubeMxX

    BLE_TransparentModeVCP

    		 X --

    BLE_p2pClient

    		 X CubeMxX

    BLE_p2pRouteur

    		 X CubeMx-

    BLE_p2pServer

    		 X CubeMxX

    BLE_p2pServer_ota

    		 - XX

    BLE_Thread

    		 - X-

    BLE_Zigbee

    BLE_Zigbee_Static

    		 +How to use BLE application and Zigbee application in static concurrent mode. +-X-

    CKS

    		 - X-

    FatFs

    		 - CubeMxX

    FreeRTOS

    		 - CubeMx-

    FreeRTOS_Mutexes

    		 - CubeMxCubeMx

    FreeRTOS_Queues

    		 - CubeMxCubeMx

    FreeRTOS_Semaphore

    		 - CubeMxCubeMx

    FreeRTOS_SemaphoreFromISR

    		 - CubeMx-

    FreeRTOS_Signal

    		 - CubeMx-

    FreeRTOS_SignalFromISR

    		 - CubeMx-

    FreeRTOS_ThreadCreation

    		 - CubeMx-

    FreeRTOS_Timers

    		 - CubeMx-

    Mac_802_15_4

    Mac_802_15_4

    Mac_802_15_4_FFD

    		 How to use MAC 802.15.4 Association and Data exchange. - X-

    Mac_802_15_4_LPM_Periodic_Transmit

    		 +How to use MAC 802.15.4 data transmission with STOP1 low power mode enabled. +-X-

    Mac_802_15_4_RFD

    		 - X-

    Thread

    		 X CubeMxX

    Thread_Coap_DataTransfer

    		 X CubeMx-

    Thread_Coap_Generic

    		 X CubeMx-

    Thread_Coap_Generic_Ota

    		 - X-

    Thread_Coap_MultiBoard

    		 - CubeMx-

    Thread_Commissioning

    		 - CubeMx-

    Thread_FTD_Coap_Multicast

    		 X CubeMx-

    Thread_Ota

    		 - X-

    Thread_Ota_Server

    		 - X-

    Thread_SED_Coap_FreeRTOS

    		 - CubeMx-

    Thread_SED_Coap_Multicast

    		 X CubeMx-

    TouchSensing

    		 - X-

    USB_Device

    		 - CubeMx-

    DFU_Standalone

    		 CubeMx CubeMx-

    HID_Standalone

    		 CubeMx CubeMxCubeMx

    MSC_Standalone

    		 - CubeMxCubeMx

    Zigbee

    Zigbee_DevTemp_Client_Router

    		 +How to use DevTemp cluster on a Centralized Zigbee network with device acting as router. +-X-

    Zigbee_DevTemp_Server_Coord

    		 +How to use DevTemp cluster on a Centralized Zigbee network with device acting as server. +-X-

    Zigbee_MeterId_Client_Router

    		 +How to use Meter Identification cluster as a client on a centralized Zigbee network. +-X-

    Zigbee_MeterId_Server_Coord

    		 +How to use Meter Identification cluster as a server on a centralized Zigbee network. +XX-

    Zigbee

    Zigbee_OnOff_Client_Distrib

    		 How to use OnOff cluster as a client on a distributed Zigbee network. - X-

    Zigbee_OnOff_Client_Router

    		 X X-

    Zigbee_OnOff_Server_Coord

    		 X X-

    Zigbee_OnOff_Server_Distrib

    		 - X-

    Zigbee_PowerProfile_Client_Coord

    		 +How to use Power Profile cluster as a client on a centralized Zigbee network. +-X-

    Zigbee_PowerProfile_Server_Router

    		 +How to use Power Profile cluster as a server on a centralized Zigbee network. +XX-

    Zigbee_PressMeas_Client_Router

    		 +How to use PressMeas cluster on a Centralized Zigbee network with device acting as router. +-X-

    Zigbee_PressMeas_Server_Coord

    		 +How to use Pressure Measurement cluster on a Centralized Zigbee network with device acting as server. +-X-

    Zigbee_SE_Msg_Client_Coord

    		 +How to use SE Messaging cluster on a Centralized Zigbee network with device acting as coordinator (Client). +-X-

    Zigbee_SE_Msg_Server_Router

    		 +How to use SE Messaging cluster on a Centralized Zigbee network with device acting as router (Server). +-X-
    Total number of applications: 68Total number of applications: 971765 1553

    Demonstrations

    		 - CubeMxCubeMx
    Total number of demonstrations: 1Total number of demonstrations: 2 0 11
    Total number of projects: 27516259Total number of projects: 39018271101
    diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/Release_Notes.html b/Projects/STM32WB_Copro_Wireless_Binaries/Release_Notes.html deleted file mode 100644 index 48e5a5e1b..000000000 --- a/Projects/STM32WB_Copro_Wireless_Binaries/Release_Notes.html +++ /dev/null @@ -1,819 +0,0 @@ - - - - - - - Release Notes for STM32WB Copro Wireless Binaries - - - - - -
    -
    -
    -
    -
    -

    Release Notes for STM32WB Copro Wireless Binaries

    -

    Copyright © 2019 STMicroelectronics
    -

    - -
    -
    -
    -

    License

    -

    This software component is licensed by ST under Ultimate Liberty license SLA0044, the “License”;

    -

    You may not use this file except in compliance with the License.

    -

    You may obtain a copy of the License at: SLA0044

    -

    Purpose

    -

    This release covers the delivery of STM32WB Coprocessor binaries.

    -

    Here is the list of the supported binaries:

    -
      -
    • stm32wb5x_BLE_Stack_fw.bin -
        -
      • Full BLE Stack 5.0 certified : Link Layer, HCI, L2CAP, ATT, SM, GAP and GATT database
        • -
      • BT SIG Certification listing : Declaration ID D042164
        • -
      • -
    • stm32wb5x_BLE_HCILayer_fw.bin -
        -
      • HCI Layer only mode 5.0 certified : Link Layer, HCI
        • -
      • BT SIG Certification listing : Declaration ID D042213
        • -
      • -
    • stm32wb5x_Thread_FTD_fw.bin -
        -
      • Full Thread Device certified v1.1
        • -
      • To be used for Leader / Router / End Device Thread role (full features excepting Border Router)
        • -
      • -
    • stm32wb5x_Thread_MTD_fw.bin -
        -
      • Minimal Thread Device certified v1.1
        • -
      • To be used for End Device and Sleepy End Device Thread role
        • -
      • -
    • stm32wb5x_BLE_Thread_fw.bin -
        -
      • Static Concurrent Mode BLE Thread
        • -
      • Supports Full BLE Stack 5.0 certified and Full Thread Device certified v1.1
        • -
      • -
    • stm32wb5x_Mac_802_15_4_fw.bin -
      • -
    • stm32wb5x_rfmonitor_phy802_15_4_fw.bin -
        -
      • Dedicated firmware binary to be used with STM32CubeMonitor-RF application.
        • -
      • Refer to STM32CubeMonitor-RF User Manual (UM2288) to get application details.
        • -
      • -
    • stm32wb5x_Zigbee_FFD_Full_fw.bin -
        -
      • Zigbee Compliant Platform certified
        • -
      • Supports Full Function Device (FFD)
        • -
      • -
    • stm32wb5x_FUS_fw.bin -
        -
      • Firmware Upgrade Services (FUS)
        • -
      • This binary is the utility to flash the Wireless Coprocessor Binaries.
        • -
      • -
    -

    How to flash the Wireless Coprocessor Binary

    -
      -

    • STEP 1: Use STM32CubeProgrammer

      -
        -

      • Version 2.0 or higher.

        • -

      • It gives access to Firmware Upgrade Service (FUS) (AN5185 : ST firmware upgrade services for STM32WB Series.) through Bootloader.

        • -

      • It is currently available as Command Line Interface (CLI) mode.

        • -
      • -

    • STEP 2: Access to Bootloader USB Interface (system flash)

      -
        -
      • Boot mode selected by Boot0 pin set to VDD -
          -
        • For P-NUCLEO-WB55.Nucleo : -
            -
          • Jumper between CN7.5(VDD) and CN7.7(Boot0)
            • -
          • Power ON via USB_USER and Jumper JP1(USB_MCU)
            • -
          • -
        • For P-NUCLEO-WB55.USBDongle : -
            -
          • Move switch SW2 to Boot0
            • -
          • Connect P-NUCLEO-WB55.USBDongle
            • -
          • -
        • -
      • -

    • STEP 3 : Delete current wireless stack :

      -
        -
      • STM32_Programmer_CLI.exe -c port=usb1 -fwdelete
        • -
      • -
    • STEP 4 : Read and upgrade FUS Version -
        -
      • STM32_Programmer_CLI.exe -c port=usb1 -r32 0x20030030 1 -
          -
        • 0x20030030 : 00050300 : FUSv0.5.3 => Must be updated using STEP 5.
          • -
        • 0x20030030 : 01000100 or 01000200 : FUSv1.0.x => Up to date, you can download the new wireless stack using STEP6.
          • -
        • -
      • -

    • STEP 5 : Download new FUS :

      -
        -
      • STM32_Programmer_CLI.exe -c port=usb1 -fwupgrade [FUS_Binary] [Install@] firstinstall=0
        • -
      -

      Please check Firmware Upgrade Services Binary Table for Install@ parameter depending of the binary.

      • -

    • STEP 6 : Download new wireless stack :

      -
        -
      • STM32_Programmer_CLI.exe -c port=usb1 -fwupgrade [Wireless_Coprocessor_Binary] [Install@] firstinstall=1
        • -
      -

      Please check Wireless Coprocessor Binary Table for Install@ parameter depending of the binary.

      • -

    • STEP 7 : Revert STEP 2 procedure to put back device in normal mode.

      • -
    -
    -
    -

    Update History

    -
    - -
    -

    Main Changes

    -

    Associated changes in Wireless Coprocessor Binary:

    -
      -
    • ZIGBEE : -
        -
      • Use Hardware Acceleration for AES processing
        • -
      • Improved trace mechanism
        • -
      • -
    • BLE : -
        -
      • Add GAP appearance definitions in ble_defs.h
        • -
      • Fix issue with ACI_GATT_[SIGNED_]WRITE_WITHOUT_RESP when ATT packet with a size between 61 and 63 bytes
        • -
      • Improvement of the NVM management
        • -
      • Support of External PA
        • -
      • -
    • MAC 802.15.4 : -
        -
      • MAC Promiscuous mode enablement
        • -
      • New MAC/PHY PIB attribute support (TxPower)
        • -
      • -
    -

    Firmware Upgrade Services Binary Table: Provides Install address for the targeted binary to be used in “STEP 5” of flash procedure.

    - -------- - - - - - - - - - - - - - - - - - - - - -
    Wireless Coprocessor BinarySTM32WB5xG(1M)STM32WB5xE(512K)STM32WB5xC(256K)VersionDate
    stm32wb5x_FUS_fw.bin0x080EC0000x0807A0000x0803A000v1.0.204/10/2019
    -

    Wireless Coprocessor Binary Table: Provides Install address for the targeted binary to be used in “STEP 6” of flash procedure.

    - -------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Wireless Coprocessor BinarySTM32WB5xG(1M)STM32WB5xE(512K)STM32WB5xC(256K)VersionDate
    stm32wb5x_BLE_HCILayer_fw.bin0x080DC0000x080680000x08028000v1.4.011/22/2019
    stm32wb5x_BLE_Stack_fw.bin0x080CB0000x080570000x08017000v1.4.011/22/2019
    stm32wb5x_BLE_Thread_fw.bin0x08078000NANAv1.4.011/22/2019
    stm32wb5x_Mac_802_15_4_fw.bin0x080E50000x080710000x08031000v1.4.011/22/2019
    stm32wb5x_rfmonitor_phy802_15_4_fw.bin0x080EC0000x080780000x08038000v1.1.004/05/2019
    stm32wb5x_Thread_FTD_fw.bin0x0809F0000x0802B000NAv1.4.011/22/2019
    stm32wb5x_Thread_MTD_fw.bin0x080B50000x08041000NAv1.4.011/22/2019
    stm32wb5x_Zigbee_FFD_Full_fw.bin0x080A3000 0x0802F000NAv1.4.011/22/2019
    -
    -
    -
    - -
    -

    Main Changes

    -

    Associated changes in Wireless Coprocessor Binary:

    -
      -
    • ZIGBEE : -
        -
      • Introducing support of Zigbee FFD (Full Function Device)
        • -
      • -
    • BLE : -
        -
      • Erase Flash while RF activity
        • -
      • BLE Initialization execution time reduced
        • -
      • -
    • THREAD / MAC 802.15.4 : -
        -
      • New version of 802.15.4 Low Level Driver
        • -
      • -
    -

    Firmware Upgrade Services Binary Table: Provides Install address for the targeted binary to be used in “STEP 5” of flash procedure.

    - -------- - - - - - - - - - - - - - - - - - - - - -
    Wireless Coprocessor BinarySTM32WB5xG(1M)STM32WB5xE(512K)STM32WB5xC(256K)VersionDate
    stm32wb5x_FUS_fw.bin0x080EC0000x0807A0000x0803A000v1.0.204/10/2019
    -

    Wireless Coprocessor Binary Table: Provides Install address for the targeted binary to be used in “STEP 6” of flash procedure.

    - -------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Wireless Coprocessor BinarySTM32WB5xG(1M)STM32WB5xE(512K)STM32WB5xC(256K)VersionDate
    stm32wb5x_BLE_HCILayer_fw.bin0x080DC0000x080680000x08028000v1.3.009/09/2019
    stm32wb5x_BLE_Stack_fw.bin0x080CB0000x080570000x08017000v1.3.109/24/2019
    stm32wb5x_BLE_Thread_fw.bin0x08078000NANAv1.3.109/24/2019
    stm32wb5x_Mac_802_15_4_fw.bin0x080E50000x080710000x08031000v1.3.009/09/2019
    stm32wb5x_rfmonitor_phy802_15_4_fw.bin0x080EC0000x080780000x08038000v1.1.004/05/2019
    stm32wb5x_Thread_FTD_fw.bin0x0809F0000x0802B000NAv1.3.109/24/2019
    stm32wb5x_Thread_MTD_fw.bin0x080B50000x08041000NAv1.3.109/24/2019
    stm32wb5x_zigbee_full_fw.bin0x0808D000 0x08019000 NAv1.3.009/09/2019
    -
    -
    -
    - -
    -

    Main Changes

    -

    Associated changes in Wireless Coprocessor Binary:

    -
      -
    • BLE Link layer : fix issues with pairing
      • -
    • Reception of 2 pairing complete events after failing numeric comparison
      • -
    • Slave_security_req collision with connection update made unstable security
      • -
    • No timeout event after slave req pairing if link key was deleted @ slave side
      • -

    • Blackout time should be back to 5sec after bonding OK

      • -
    • BLE GATT : improvement of GATT Read event management for certain values of attribute length and ATT_MTU
      • -
    • BLE GATT : Add ACI_GATT_INDICATION_EXT_EVENT
      • -
    • THREAD / MAC 802.15.4 : -
        -
      • New version of 802.15.4 Low Level Driver (Tx Power management improvement + API alignment)
        • -
      • -
    • MAC 802.15.4: -
        -
      • Updates on robustness and test coverage
        • -
      • -
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Firmware Upgrade Services BinaryDeviceInstall addressVersionDate
    stm32wb5x_FUS_fw.binSTM32WB5xC(256K)0x0803E000v1.0.204/10/2019
    stm32wb5x_FUS_fw.binSTM32WB5xE(512K)0x0807E000v1.0.204/10/2019
    stm32wb5x_FUS_fw.binSTM32WB5xG(1M)0x080EC000v1.0.204/10/2019
    -

    Binary Install Address and version : Provides Install address for the targeted binary to be used in “STEP 5 and STEP 6” of flash procedure.

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Wireless Coprocessor BinaryInstall addressVersionDate
    stm32wb5x_BLE_Stack_fw.bin0x080CC000v1.2.007/03/2019
    stm32wb5x_BLE_HCILayer_fw.bin0x080DC000v1.2.007/03/2019
    stm32wb5x_Thread_FTD_fw.bin0x0809F000v1.2.006/25/2019
    stm32wb5x_Thread_MTD_fw.bin0x080B5000v1.2.006/25/2019
    stm32wb5x_BLE_Thread_fw.bin0x08079000v1.2.007/03/2019
    stm32wb5x_Mac_802_15_4_fw.bin0x080E4000v1.2.006/25/2019
    stm32wb5x_rfmonitor_phy802_15_4_fw.bin0x080EC000v1.1.004/05/2019
    -
    -
    -
    - -
    -

    Main Changes

    -

    Associated changes in Firmware Upgrade Services (FUS):

    -
      -
    • Add support for STM32WB5xE(512K) and STM32WB5xC(256K) devices.
      • -
    • On STM32WB5xC and STM32WB5xE, it is mandatory to install FUS V1.0.2 before any other operation. Otherwise, the device might be locked in an unrecoverable state.
      • -
    -

    The following table provide the address to use in correspondence with the flash procedure of Wireless Coprocessor Binaries and the device to be used.

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Firmware Upgrade Services BinaryDeviceInstall addressVersionDate
    stm32wb5x_FUS_fw.binSTM32WB5xC(256K)0x0803E000v1.0.204/10/2019
    stm32wb5x_FUS_fw.binSTM32WB5xE(512K)0x0807E000v1.0.204/10/2019
    stm32wb5x_FUS_fw.binSTM32WB5xG(1M)0x080EC000v1.0.204/10/2019
    -

    Associated changes in Wireless Coprocessor Binary:

    -
      -
    • BLE System : fix stopMode2 race condition
      • -
    • BLE Security : fix pairing issue with numeric comparison
      • -
    -

    Binary Install Address and version : Provides Install address for the targeted binary to be used in “STEP 5 and STEP 6” of flash procedure.

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Wireless Coprocessor BinaryInstall addressVersionDate
    stm32wb5x_BLE_Stack_fw.bin0x080CC000v1.1.105/10/2019
    stm32wb5x_BLE_HCILayer_fw.bin0x080DC000v1.1.105/10/2019
    stm32wb5x_Thread_FTD_fw.bin0x0809F000v1.1.004/05/2019
    stm32wb5x_Thread_MTD_fw.bin0x080B5000v1.1.004/05/2019
    stm32wb5x_BLE_Thread_fw.bin0x08079000v1.1.004/05/2019
    stm32wb5x_Mac_802_15_4_fw.bin0x080E6000v1.1.004/05/2019
    stm32wb5x_rfmonitor_phy802_15_4_fw.bin0x080EC000v1.1.004/05/2019
    -
    -
    -
    - -
    -

    Main Changes

    -

    Introduction of the Firmware Upgrade Services (FUS):

    -
      -
    • This feature is embedded inside stm32wb5x_FUS_fw.bin.
      • -
    • This stm32wb5x_FUS_fw.bin v1.0.1 MUST be installed to use Wireless Coprocessor Binaries v1.1.0.
      • -
    • This stm32wb5x_FUS_fw.bin v1.0.1 CANNOT BE USED with the previous version of Wireless Coprocessor Binary.
      • -
    • All existing Cortex®-M4 user application are compatible without any update.
      • -
    -

    The following table provide the address to use in correspondence with the flash procedure of Wireless Coprocessor Binaries.

    - - - - - - - - - - - - - - - - - -
    Firmware Upgrade Services BinaryInstall addressVersionDate
    stm32wb5x_FUS_fw.bin0x080EC000 (On top of FUS v0.5.3)v1.0.104/05/2019
    -

    Introduction of the Customer Key Storage (CKS):

    -
      -
    • All Wireless Coprocessor Binaries embeds this new feature.
      • -
    • The FUS allows customer keys to be stored in the dedicated FUS Flash memory area and then to load the stored key to the AES1 in secure mode (AES1 key register accessed only by Cortex®-M0+ and data registers accessible by Cortex®-M4 user application).
      • -
    • You can refer to AN5185 : ST firmware upgrade services for STM32WB Series.
      • -
    -

    Associated changes in Wireless Coprocessor Binary:

    -
      -
    • BLE NVM : change behavior when NVM is full -
        -
      • Inform application before latest record
        • -
      • Erase and keep latest record when it is full
        • -
      • -
    • BLE Link layer : fix issue when pairing fails with SMP_SC_NUMCOMPARISON_FAILED, no response from the slave if the master sends again pairing_req.
      • -
    • BLE Link layer : fix issue Disconnection with error code 0x3D MIC Failure.
      • -
    • Thread 802_15_4 radio driver robustness improvement with additional error checks. The application is now notified in case of radio error detected inside the wireless binary.
      • -
    • Thread TxPower management improvement -
        -
      • New APIs provided on application side in order to control the Tx power :otPlatRadioGetTransmitPower() and otPlatRadioSetTransmitPower()
        • -
      • The default Tx power is now set to 0dBm
        • -
      • -
    -

    Binary Install Address and version : Provides Install address for the targeted binary to be used in “STEP 5 and STEP 6” of flash procedure.

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Wireless Coprocessor BinaryInstall addressVersionDate
    stm32wb5x_BLE_Stack_fw.bin0x080CC000v1.1.004/05/2019
    stm32wb5x_BLE_HCILayer_fw.bin0x080DC000v1.1.004/05/2019
    stm32wb5x_Thread_FTD_fw.bin0x0809F000v1.1.004/05/2019
    stm32wb5x_Thread_MTD_fw.bin0x080B5000v1.1.004/05/2019
    stm32wb5x_BLE_Thread_fw.bin0x08079000v1.1.004/05/2019
    stm32wb5x_Mac_802_15_4_fw.bin0x080E6000v1.1.004/05/2019
    stm32wb5x_rfmonitor_phy802_15_4_fw.bin0x080EC000v1.1.004/05/2019
    -
    -
    -
    - -
    -

    Main Changes

    -

    First release

    -

    First official release.

    -

    Binary Install Address and version : Provides Install address for the targeted binary to be used in “STEP 6” of flash procedure.

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Wireless Processor BinaryInstall addressVersionDate
    stm32wb5x_BLE_Stack_fw.bin0x080CB000v1.0.002/06/2019
    stm32wb5x_BLE_HCILayer_fw.bin0x080CD000v1.0.002/06/2019
    stm32wb5x_Thread_FTD_fw.bin0x0809F000v1.0.002/06/2019
    stm32wb5x_Thread_MTD_fw.bin0x080B5000v1.0.002/06/2019
    stm32wb5x_BLE_Thread_fw.bin0x08079000v1.0.002/06/2019
    stm32wb5x_Mac_802_15_4_fw.bin0x080E5000v1.0.002/06/2019
    stm32wb5x_rfmonitor_phy802_15_4_fw.bin0x080EA000v1.0.002/06/2019
    -
    -
    -
    -
    -
    -

    For complete documentation on STM32WBxx, visit: [www.st.com/stm32wb]

    -This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge. -
    - - diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/Release_Notes.html b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/Release_Notes.html new file mode 100644 index 000000000..f534603ed --- /dev/null +++ b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/Release_Notes.html @@ -0,0 +1,244 @@ + + + + + + + Release Notes for STM32WB Copro Wireless Binaries + + + + + +
    +
    +
    +
    +
    +

    Release Notes for STM32WB Copro Wireless Binaries

    +

    Copyright © 2019 STMicroelectronics
    +

    + +
    +
    +
    +

    License

    +

    This software component is licensed by ST under Ultimate Liberty license SLA0044, the “License”;

    +

    You may not use this file except in compliance with the License.

    +

    You may obtain a copy of the License at: SLA0044

    +

    Purpose

    +

    This release covers the delivery of STM32WB Coprocessor binaries.

    +

    Here is the list of the supported binaries:

    +
      +
    • stm32wb3x_BLE_Stack_full_fw.bin +
        +
      • Full BLE Stack 5.0 certified : Link Layer, HCI, L2CAP, ATT, SM, GAP and GATT database
        • +
      • BT SIG Certification listing : Declaration ID D042164
        • +
      • +
    • stm32wb3x_BLE_Stack_light_fw.bin +
        +
      • Erase/Write Flash of Wireless Stack Non Volatile Memory while BLE link is active (Min Interval 28ms)
        • +
      • Fix IFS (Inter Frame Spacing) sometimes longer than 152us
        • +
      • Wireless Ble stack Light configuration – Slave Only +
          +
        • Following features are kept: +
            +
          • GAP peripheral / LL slave
            • +
          • GATT server
            • +
          • Data length extension
            • +
          • Double LL slave
            • +
          • +
        • Following Feature are removed +
            +
          • GAP central / LL master
            • +
          • GATT client
            • +
          • Privacy / White list
            • +
          • Secure connections
            • +
          • 2 MB / PHY update
            • +
          • HCI interface (useless functions are removed)
            • +
          • +
        • +
      • +
    • stm32wb3x_BLE_HCILayer_fw.bin +
        +
      • HCI Layer only mode 5.0 certified : Link Layer, HCI
        • +
      • BT SIG Certification listing : Declaration ID D042213
        • +
      • +
    • stm32wb3x_Thread_FTD_fw.bin +
        +
      • Full Thread Device certified v1.1
        • +
      • To be used for Leader / Router / End Device Thread role (full features excepting Border Router)
        • +
      • +
    • stm32wb3x_Thread_MTD_fw.bin +
        +
      • Minimal Thread Device certified v1.1
        • +
      • To be used for End Device and Sleepy End Device Thread role
        • +
      • +
    • stm32wb3x_Mac_802_15_4_fw.bin +
      • +
    +

    How to flash the Wireless Coprocessor Binary via USB

    +
      +

    • Inside the below procedure, the references to binaries name and install address are provided in the section Main Changes of this file.

      • +

    • STEP 1: Use STM32CubeProgrammer

      +
        +

      • Version 2.0 or higher.

        • +

      • It gives access to Firmware Upgrade Service (FUS) (AN5185 : ST firmware upgrade services for STM32WB Series.) through Bootloader.

        • +

      • It is currently available as Command Line Interface (CLI) mode.

        • +
      • +

    • STEP 2: Access to Bootloader USB Interface (system flash)

      +
        +
      • Boot mode selected by Boot0 pin set to VDD +
          +
        • For NUCLEO-WB35CE : +
            +
          • Jumper between CN7.5(VDD) and CN7.7(Boot0)
            • +
          • Power ON via USB_USER and Jumper JP1(USB_MCU)
            • +
          • +
        • +
      • +

    • STEP 3 : Delete current wireless stack :

      +
        +
      • STM32_Programmer_CLI.exe -c port=usb1 -fwdelete
        • +
      • +
    • STEP 4 : Read and upgrade FUS Version +
        +
      • STM32_Programmer_CLI.exe -c port=usb1 -r32 0x20008030 1 +
          +
        • *0x20008030 : 01000000 : FUSv1.0.x => Up to date, you can download the new wireless stack using STEP6.
          • +
        • +
      • +
    • STEP 5 : Download new FUS : Not Applicable +
        +
      • STM32_Programmer_CLI.exe -c port=usb1 -fwupgrade [FUS_Binary] [Install@] firstinstall=0 Please check Firmware Upgrade Services Binary Table for Install@ parameter depending of the binary.
        • +
      • +

    • STEP 6 : Download new wireless stack :

      +
        +
      • STM32_Programmer_CLI.exe -c port=usb1 -fwupgrade [Wireless_Coprocessor_Binary] [Install@] firstinstall=1
        • +
      +

      Please check Wireless Coprocessor Binary Table for Install@ parameter depending of the binary.

      • +

    • STEP 7 : Revert STEP 2 procedure to put back device in normal mode.

      • +
    +

    How to flash the Wireless Coprocessor Binary via SWD/JTAG

    +
      +

    • Inside the below procedure, the references to binaries name and install address are provided in the section Main Changes of this file.

      • +

    • STEP 1: Use STM32CubeProgrammer

      +
        +

      • Version 2.2.0 or higher.

        • +

      • It gives access to Firmware Upgrade Service (FUS) (AN5185 : ST firmware upgrade services for STM32WB Series.) through Bootloader.

        • +

      • It is currently available as Command Line Interface (CLI) mode.

        • +
      • +
    • STEP 2 : Read and upgrade FUS Version +
        +
      • STM32_Programmer_CLI.exe -c port=usb1 -r32 0x20030030 1 +
          +
        • *0x20030030 : 01000000 : FUSv1.0.x => Up to date, you can download the new wireless stack using STEP 4.
          • +
        • +
      • +
    • STEP 3 :Download new FUS : Not Applicable +
        +
      • STM32_Programmer_CLI.exe -c port=swd mode=UR -ob nSWboot0=0 nboot1=1 nboot0=1 -fwupgrade [FUS_Binary] [Install@] firstinstall=0 Please check Firmware Upgrade Services Binary Table for Install@ parameter depending of the binary.
        • +
      • +

    • STEP 4 : Download new wireless stack :

      +
        +
      • STM32_Programmer_CLI.exe -c port=swd mode=UR -ob nSWboot0=0 nboot1=1 nboot0=1 -fwupgrade [Wireless_Coprocessor_Binary] [Install@] firstinstall=1
        • +
      +

      Please check Wireless Coprocessor Binary Table for Install@ parameter depending of the binary.

      • +
    +

    How to compute available flash size

    +
      +

    • The default linker file provided in [\Drivers\CMSIS\Device\ST32WBxx\Source\Templates] allows the application to use a fixed amount of flash.

      +

      The maximum flash memory that can be used by the application is up to the Secure Flash Start Address (SFSA) that can be read from the option byte.

      +

      The ICFEDIT_region_ROM_end in the linker can be modified with a value up to : (0x08000000 + (SFSA << 12)) - 1.

      • +

    • Example: When the SFSA option byte is set to 0x32, the maximum value to be used for __ICFEDIT_region_ROM_end is 0x08031FFF – which is 200KB of flash

      • +

    • Note: The SFSA option byte can only be set by the CPU2. The user cannot modify that value.

      • +
    +
    +
    +

    Update History

    +
    + +
    +

    Main Changes

    +

    Associated changes in Wireless Coprocessor Binary:

    +
      +
    • Initial version of Wireless Coprocessor Binary compatible with STM32WB3x.
      • +
    • Thread +
        +
      • Support of Thread stack on STM32WB35 in FFD and RFD configurations (two separate binaries)
        +
        • +
      • +
    • MAC +
        +
      • Support of 802_15_4 MAC stack on STM32WB35
        • +
      • +
    +

    Binary Install Address and version : Provides Install address for the targeted binary to be used in flash procedure “STEP 6” via USB or “STEP 4” via SWD/JTAG.

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Wireless Coprocessor BinarySTM32WB3x(512K)VersionDate
    stm32wb3x_BLE_HCILayer_fw.bin0x805C000v1.5.002/10/2020
    stm32wb3x_BLE_Stack_full_fw.bin0x804B000v1.5.002/10/2020
    stm32wb3x_BLE_Stack_light_fw.bin0x8059000v1.5.002/10/2020
    stm32wb3x_Mac_802_15_4_fw.bin0x8064000v1.5.002/10/2020
    stm32wb3x_Thread_FTD_fw.bin0x801F000v1.5.002/10/2020
    stm32wb3x_Thread_MTD_fw.bin0x8034000v1.5.002/10/2020
    +
    +
    +
    +
    +
    +

    For complete documentation on STM32WBxx, visit: [www.st.com/stm32wb]

    +This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge. +
    + + diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_BLE_HCILayer_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_BLE_HCILayer_fw.bin new file mode 100644 index 000000000..54953f222 Binary files /dev/null and b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_BLE_HCILayer_fw.bin differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_BLE_Stack_full_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_BLE_Stack_full_fw.bin new file mode 100644 index 000000000..67c618f17 Binary files /dev/null and b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_BLE_Stack_full_fw.bin differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_BLE_Stack_light_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_BLE_Stack_light_fw.bin new file mode 100644 index 000000000..96e0e61ef Binary files /dev/null and b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_BLE_Stack_light_fw.bin differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_Mac_802_15_4_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_Mac_802_15_4_fw.bin new file mode 100644 index 000000000..5148ea7a0 Binary files /dev/null and b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_Mac_802_15_4_fw.bin differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_Thread_FTD_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_Thread_FTD_fw.bin new file mode 100644 index 000000000..89965c8cd Binary files /dev/null and b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_Thread_FTD_fw.bin differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_Thread_MTD_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_Thread_MTD_fw.bin new file mode 100644 index 000000000..7d024e7c5 Binary files /dev/null and b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB3x/stm32wb3x_Thread_MTD_fw.bin differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/Release_Notes.html b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/Release_Notes.html new file mode 100644 index 000000000..1afb58839 --- /dev/null +++ b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/Release_Notes.html @@ -0,0 +1,1095 @@ + + + + + + + Release Notes for STM32WB Copro Wireless Binaries + + + + + +
    +
    +
    +
    +
    +

    Release Notes for STM32WB Copro Wireless Binaries

    +

    Copyright © 2019 STMicroelectronics
    +

    + +
    +
    +
    +

    License

    +

    This software component is licensed by ST under Ultimate Liberty license SLA0044, the “License”;

    +

    You may not use this file except in compliance with the License.

    +

    You may obtain a copy of the License at: SLA0044

    +

    Purpose

    +

    This release covers the delivery of STM32WB Coprocessor binaries.

    +

    Here is the list of the supported binaries:

    +
      +
    • stm32wb5x_BLE_Stack_full_fw.bin +
        +
      • Full BLE Stack 5.0 certified : Link Layer, HCI, L2CAP, ATT, SM, GAP and GATT database
        • +
      • BT SIG Certification listing : Declaration ID D042164
        • +
      • +
    • stm32wb5x_BLE_Stack_light_fw.bin +
        +
      • Erase/Write Flash of Wireless Stack Non Volatile Memory while BLE link is active (Min Interval 28ms)
        • +
      • Fix IFS (Inter Frame Spacing) sometimes longer than 152us
        • +
      • Wireless Ble stack Light configuration – Slave Only +
          +
        • Following features are kept: +
            +
          • GAP peripheral / LL slave
            • +
          • GATT server
            • +
          • Data length extension
            • +
          • Double LL slave
            • +
          • +
        • Following Feature are removed +
            +
          • GAP central / LL master
            • +
          • GATT client
            • +
          • Privacy / White list
            • +
          • Secure connections
            • +
          • 2 MB / PHY update
            • +
          • HCI interface (useless functions are removed)
            • +
          • +
        • +
      • +
    • stm32wb5x_BLE_HCILayer_fw.bin +
        +
      • HCI Layer only mode 5.0 certified : Link Layer, HCI
        • +
      • BT SIG Certification listing : Declaration ID D042213
        • +
      • +
    • stm32wb5x_Thread_FTD_fw.bin +
        +
      • Full Thread Device certified v1.1
        • +
      • To be used for Leader / Router / End Device Thread role (full features excepting Border Router)
        • +
      • +
    • stm32wb5x_Thread_MTD_fw.bin +
        +
      • Minimal Thread Device certified v1.1
        • +
      • To be used for End Device and Sleepy End Device Thread role
        • +
      • +
    • stm32wb5x_BLE_Thread_fw.bin +
        +
      • Static Concurrent Mode BLE Thread
        • +
      • Supports Full BLE Stack 5.0 certified and Full Thread Device certified v1.1
        • +
      • +
    • stm32wb5x_Mac_802_15_4_fw.bin +
      • +
    • stm32wb5x_rfmonitor_phy802_15_4_fw.bin +
        +
      • Dedicated firmware binary to be used with STM32CubeMonitor-RF application.
        • +
      • Refer to STM32CubeMonitor-RF User Manual (UM2288) to get application details.
        • +
      • +
    • stm32wb5x_Zigbee_FFD_Full_fw.bin +
        +
      • Zigbee Compliant Platform certified
        • +
      • Supports Full Function Device (FFD)
        • +
      • +
    • stm32wb5x_BLE_Zigbee_FFD_static_fw.bin +
        +
      • Static Concurrent Mode BLE Zigbee
        • +
      • Supports Full BLE Stack 5.0 certified and Zigbee FFD(Full Function Device) Compliant Platform certified
        • +
      • +
    • stm32wb5x_FUS_fw_1_0_2.bin +
        +
      • Firmware Upgrade Services (FUS)
        • +
      • This binary is the utility to flash the Wireless Coprocessor Binaries.
        • +
      • FUS version v1.0.2
        • +
      • +
    • stm32wb5x_FUS_fw.bin +
        +
      • Firmware Upgrade Services (FUS)
        • +
      • This binary is the utility to flash the Wireless Coprocessor Binaries.
        • +
      • Latest version of the FUS
        • +
      • +
    +

    How to flash the Wireless Coprocessor Binary via USB

    +
      +

    • Inside the below procedure, the references to binaries name and install address are provided in the section Main Changes of this file.

      • +

    • STEP 1: Use STM32CubeProgrammer

      +
        +

      • Version 2.0 or higher.

        • +

      • It gives access to Firmware Upgrade Service (FUS) (AN5185 : ST firmware upgrade services for STM32WB Series.) through Bootloader.

        • +

      • It is currently available as Command Line Interface (CLI) mode.

        • +
      • +

    • STEP 2: Access to Bootloader USB Interface (system flash)

      +
        +
      • Boot mode selected by Boot0 pin set to VDD +
          +
        • For P-NUCLEO-WB55.Nucleo : +
            +
          • Jumper between CN7.5(VDD) and CN7.7(Boot0)
            • +
          • Power ON via USB_USER and Jumper JP1(USB_MCU)
            • +
          • +
        • For P-NUCLEO-WB55.USBDongle : +
            +
          • Move switch SW2 to Boot0
            • +
          • Connect P-NUCLEO-WB55.USBDongle
            • +
          • +
        • +
      • +

    • STEP 3 : Delete current wireless stack :

      +
        +
      • STM32_Programmer_CLI.exe -c port=usb1 -fwdelete
        • +
      • +
    • STEP 4 : Read and upgrade FUS Version +
        +
      • STM32_Programmer_CLI.exe -c port=usb1 -r32 0x20030030 1 +
          +
        • 0x20030030 : 00050300 : FUSv0.5.3 => Must be updated using STEP 5.
          • +
        • 0x20030030 : 01000100 or 01000200 : FUSv1.0.x => Must be updated using STEP 6.
          • +
        • 0x20030030 : 0x10100000 : FUSv1.1.0 => Up to date, you can download the new wireless stack using STEP 7.
          • +
        • +
      • +

    • STEP 5 : Download FUS 1.0.2 (stm32wb5x_FUS_fw_1_0_2.bin):

      +
        +
      • STM32_Programmer_CLI.exe -c port=usb1 -fwupgrade stm32wb5x_FUS_fw_1_0_2.bin [Install@] firstinstall=0
        • +
      +

      Please check Firmware Upgrade Services Binary Table for Install@ parameter depending of the binary.

      • +

    • STEP 6 : Download latest FUS :

      +
        +
      • STM32_Programmer_CLI.exe -c port=usb1 -fwupgrade [FUS_Binary] [Install@] firstinstall=0
        • +
      +

      Please check Firmware Upgrade Services Binary Table for Install@ parameter depending of the binary.

      • +

    • STEP 7 : Download new wireless stack :

      +
        +
      • STM32_Programmer_CLI.exe -c port=usb1 -fwupgrade [Wireless_Coprocessor_Binary] [Install@] firstinstall=1
        • +
      +

      Please check Wireless Coprocessor Binary Table for Install@ parameter depending of the binary.

      • +

    • STEP 8 : Revert STEP 2 procedure to put back device in normal mode.

      • +
    +

    How to flash the Wireless Coprocessor Binary via SWD/JTAG

    +
      +

    • Inside the below procedure, the references to binaries name and install address are provided in the section Main Changes of this file.

      • +

    • STEP 1: Use STM32CubeProgrammer

      +
        +

      • Version 2.2.0 or higher.

        • +

      • It gives access to Firmware Upgrade Service (FUS) (AN5185 : ST firmware upgrade services for STM32WB Series.) through Bootloader.

        • +

      • It is currently available as Command Line Interface (CLI) mode.

        • +
      • +
    • STEP 2 : Read and upgrade FUS Version +
        +
      • STM32_Programmer_CLI.exe -c port=usb1 -r32 0x20030030 1 +
          +
        • 0x20030030 : 00050300 : FUSv0.5.3 => Must be updated using STEP 3.
          • +
        • 0x20030030 : 01000100 or 01000200 : FUSv1.0.x => Must be updated using using STEP 4.
          • +
        • 0x20030030 : 0x10100000 : FUSv1.1.0 => Up to date, you can download the new wireless stack using STEP 5.
          • +
        • +
      • +

    • STEP 3 : Download FUS 1.0.2 (stm32wb5x_FUS_fw_1_0_2.bin) :

      +
        +
      • STM32_Programmer_CLI.exe -c port=swd mode=UR -ob nSWboot0=0 nboot1=1 nboot0=1 -fwupgrade stm32wb5x_FUS_fw_1_0_2.bin [Install@] firstinstall=0
        • +
      +

      Please check Firmware Upgrade Services Binary Table for Install@ parameter depending of the binary.

      • +

    • STEP 4 :Download latest FUS :

      +
        +
      • STM32_Programmer_CLI.exe -c port=swd mode=UR -ob nSWboot0=0 nboot1=1 nboot0=1 -fwupgrade [FUS_Binary] [Install@] firstinstall=0
        • +
      +

      Please check Firmware Upgrade Services Binary Table for Install@ parameter depending of the binary.

      • +

    • STEP 5 : Download new wireless stack :

      +
        +
      • STM32_Programmer_CLI.exe -c port=swd mode=UR -ob nSWboot0=0 nboot1=1 nboot0=1 -fwupgrade [Wireless_Coprocessor_Binary] [Install@] firstinstall=1
        • +
      +

      Please check Wireless Coprocessor Binary Table for Install@ parameter depending of the binary.

      • +
    +

    How to compute available flash size

    +
      +

    • The default linker file is provided in [\Drivers\CMSIS\Device\ST32WBxx\Source\Templates].

      +

      The maximum flash memory that can be used by the application is up to the Secure Flash Start Address (SFSA) that can be read from the option byte.

      +

      The ICFEDIT_region_ROM_end in the linker can be modified with a value up to : (0x08000000 + (SFSA << 12)) - 1.

      • +

    • Example: When the SFSA option byte is set to 0xA0, the maximum value to be used for __ICFEDIT_region_ROM_end is 0x0809FFFF – which is 640KB of flash

      • +

    • Note: The SFSA option byte can only be set by the CPU2. The user cannot modify that value.

      • +
    +
    +
    +

    Update History

    +
    + +
    +

    Main Changes

    +

    Associated changes in Wireless Coprocessor Binary:

    +
      +
    • FUS: +
        +
      • New revision
        • +
      • Add Antirollback mechanism: when this option is activated it cannot be reverted and it prevents installation of any older version of firmware (refer to AN5185 for more details)
        • +
      • Add ECC error management (factory reset).
        • +
      • Add Flash corruption error management (factory reset).
        • +
      • Replace the safeboot complete device lock by factory reset.
        • +
      • +
    • Introducing new binary stm32wb5x_BLE_Zigbee_FFD_static_fw.bin: +
        +
      • Supporting BLE and Zigbee in static mode
        • +
      • +
    • THREAD: +
        +
      • Correct the way the OpenThread API parameters are shared between M4 and M0. M4 is no more accessing parameters stored in secure SRAM.
        • +
      • LLD enhancement
        • +
      • Support of External PA
        • +
      • +
    • ZIGBEE: +
        +
      • Reducing memory footprint
        • +
      • Fix memory allocation issue
        • +
      • Zigbee stack enhancement (Fix basic cluster string initialization and Fix zb_ipc_m0_zdo_match_desc callback issue)
        • +
      • LLD enhancement
        • +
      • Support of External PA
        • +
      • +
    • MAC 802.15.4: +
        +
      • Support of Low Power mode
        • +
      • Fix issue on silent start as device was not able to emit data on such start, SyncLossIndication now provides the right PANID
        • +
      • LLD enhancement
        • +
      • Support of External PA
        • +
      • +
    • BLE: +
        +
      • Introduction of new binary stm32wb5x_BLE_Stack_light_fw.bin for supporting Slave only (cf previous detailed description).
        • +
      • WARNING: when using the stm32wb5x_BLE_Stack_light_fw.bin binary, the maximum number of simultaneous connections that the device will support is 2
        +then #define CFG_BLE_NUM_LINK in app_conf.h shall be updated accordingly.
        • +
      • +
    +

    Firmware Upgrade Services Binary Table: Provides Install address for the targeted binary to be used in flash procedure “STEP 5” via USB or “STEP 3” via SWD/JTAG.

    + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Wireless Coprocessor BinarySTM32WB5xG(1M)STM32WB5xE(512K)STM32WB5xC(256K)VersionDate
    stm32wb5x_FUS_fw_1_0_2.bin0x080EC0000x0807A0000x0803A000v1.0.204/10/2019
    stm32wb5x_FUS_fw.bin0x080EC0000x0807A0000x0803A000v1.1.002/10/2020
    +

    Wireless Coprocessor Binary Table: Provides Install address for the targeted binary to be used in flash procedure “STEP 6” via USB or “STEP 4” via SWD/JTAG.

    + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Wireless Coprocessor BinarySTM32WB5xG(1M)STM32WB5xE(512K)STM32WB5xC(256K)VersionDate
    stm32wb5x_BLE_HCILayer_fw.bin0x080DC0000x080680000x08028000v1.5.002/10/2020
    stm32wb5x_BLE_Stack_full_fw.bin0x080CB0000x080570000x08017000v1.5.002/10/2020
    stm32wb5x_BLE_Stack_light_fw.bin0x80D90000x80650000x8025000v1.5.002/10/2020
    stm32wb5x_BLE_Thread_fw.bin0x08078000NANAv1.5.002/10/2020
    stm32wb5x_BLE_Zigbee_FFD_static_fw.bin0x0807C000NANAv1.5.002/10/2020
    stm32wb5x_Mac_802_15_4_fw.bin0x080E40000x080700000x08030000v1.5.002/10/2020
    stm32wb5x_rfmonitor_phy802_15_4_fw.bin0x080EC0000x080780000x08038000v1.1.004/05/2019
    stm32wb5x_Thread_FTD_fw.bin0x0809F0000x0802B000NAv1.5.002/10/2020
    stm32wb5x_Thread_MTD_fw.bin0x080B40000x08040000NAv1.5.002/10/2020
    stm32wb5x_Zigbee_FFD_Full_fw.bin0x080A9000 0x08035000NAv1.5.002/10/2020
    +
    +
    +
    + +
    +

    Main Changes

    +

    Associated changes in Wireless Coprocessor Binary:

    +
      +
    • ZIGBEE : +
        +
      • Reducing memory footprint
        • +
      • Use Hardware Acceleration for AES processing
        • +
      • Improved trace mechanism
        • +
      • +
    • BLE : +
        +
      • Add GAP appearance definitions in ble_defs.h
        • +
      • Fix issue with ACI_GATT_[SIGNED_]WRITE_WITHOUT_RESP when ATT packet with a size between 61 and 63 bytes
        • +
      • Improvement of the NVM management
        • +
      • Support of External PA
        • +
      • +
    • MAC 802.15.4 : +
        +
      • MAC Promiscuous mode enablement
        • +
      • New MAC/PHY PIB attribute support (TxPower)
        • +
      • +
    +

    Firmware Upgrade Services Binary Table: Provides Install address for the targeted binary to be used in “STEP 5” of flash procedure.

    + ++++++++ + + + + + + + + + + + + + + + + + + + + +
    Wireless Coprocessor BinarySTM32WB5xG(1M)STM32WB5xE(512K)STM32WB5xC(256K)VersionDate
    stm32wb5x_FUS_fw.bin0x080EC0000x0807A0000x0803A000v1.0.204/10/2019
    +

    Wireless Coprocessor Binary Table: Provides Install address for the targeted binary to be used in “STEP 6” of flash procedure.

    + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Wireless Coprocessor BinarySTM32WB5xG(1M)STM32WB5xE(512K)STM32WB5xC(256K)VersionDate
    stm32wb5x_BLE_HCILayer_fw.bin0x080DC0000x080680000x08028000v1.4.011/22/2019
    stm32wb5x_BLE_Stack_fw.bin0x080CB0000x080570000x08017000v1.4.011/22/2019
    stm32wb5x_BLE_Thread_fw.bin0x08078000NANAv1.4.011/22/2019
    stm32wb5x_Mac_802_15_4_fw.bin0x080E50000x080710000x08031000v1.4.011/22/2019
    stm32wb5x_rfmonitor_phy802_15_4_fw.bin0x080EC0000x080780000x08038000v1.1.004/05/2019
    stm32wb5x_Thread_FTD_fw.bin0x0809F0000x0802B000NAv1.4.011/22/2019
    stm32wb5x_Thread_MTD_fw.bin0x080B50000x08041000NAv1.4.011/22/2019
    stm32wb5x_Zigbee_FFD_Full_fw.bin0x080A3000 0x0802F000NAv1.4.011/22/2019
    +
    +
    +
    + +
    +

    Main Changes

    +

    Associated changes in Wireless Coprocessor Binary:

    +
      +
    • ZIGBEE : +
        +
      • Introducing support of Zigbee FFD (Full Function Device)
        • +
      • +
    • BLE : +
        +
      • Erase Flash while RF activity
        • +
      • BLE Initialization execution time reduced
        • +
      • +
    • THREAD / MAC 802.15.4 : +
        +
      • New version of 802.15.4 Low Level Driver
        • +
      • +
    +

    Firmware Upgrade Services Binary Table: Provides Install address for the targeted binary to be used in “STEP 5” of flash procedure.

    + ++++++++ + + + + + + + + + + + + + + + + + + + + +
    Wireless Coprocessor BinarySTM32WB5xG(1M)STM32WB5xE(512K)STM32WB5xC(256K)VersionDate
    stm32wb5x_FUS_fw.bin0x080EC0000x0807A0000x0803A000v1.0.204/10/2019
    +

    Wireless Coprocessor Binary Table: Provides Install address for the targeted binary to be used in “STEP 6” of flash procedure.

    + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Wireless Coprocessor BinarySTM32WB5xG(1M)STM32WB5xE(512K)STM32WB5xC(256K)VersionDate
    stm32wb5x_BLE_HCILayer_fw.bin0x080DC0000x080680000x08028000v1.3.009/09/2019
    stm32wb5x_BLE_Stack_fw.bin0x080CB0000x080570000x08017000v1.3.109/24/2019
    stm32wb5x_BLE_Thread_fw.bin0x08078000NANAv1.3.109/24/2019
    stm32wb5x_Mac_802_15_4_fw.bin0x080E50000x080710000x08031000v1.3.009/09/2019
    stm32wb5x_rfmonitor_phy802_15_4_fw.bin0x080EC0000x080780000x08038000v1.1.004/05/2019
    stm32wb5x_Thread_FTD_fw.bin0x0809F0000x0802B000NAv1.3.109/24/2019
    stm32wb5x_Thread_MTD_fw.bin0x080B50000x08041000NAv1.3.109/24/2019
    stm32wb5x_zigbee_full_fw.bin0x0808D000 0x08019000 NAv1.3.009/09/2019
    +
    +
    +
    + +
    +

    Main Changes

    +

    Associated changes in Wireless Coprocessor Binary:

    +
      +
    • BLE Link layer : fix issues with pairing
      • +
    • Reception of 2 pairing complete events after failing numeric comparison
      • +
    • Slave_security_req collision with connection update made unstable security
      • +
    • No timeout event after slave req pairing if link key was deleted @ slave side
      • +

    • Blackout time should be back to 5sec after bonding OK

      • +
    • BLE GATT : improvement of GATT Read event management for certain values of attribute length and ATT_MTU
      • +
    • BLE GATT : Add ACI_GATT_INDICATION_EXT_EVENT
      • +
    • THREAD / MAC 802.15.4 : +
        +
      • New version of 802.15.4 Low Level Driver (Tx Power management improvement + API alignment)
        • +
      • +
    • MAC 802.15.4: +
        +
      • Updates on robustness and test coverage
        • +
      • +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Firmware Upgrade Services BinaryDeviceInstall addressVersionDate
    stm32wb5x_FUS_fw.binSTM32WB5xC(256K)0x0803E000v1.0.204/10/2019
    stm32wb5x_FUS_fw.binSTM32WB5xE(512K)0x0807E000v1.0.204/10/2019
    stm32wb5x_FUS_fw.binSTM32WB5xG(1M)0x080EC000v1.0.204/10/2019
    +

    Binary Install Address and version : Provides Install address for the targeted binary to be used in “STEP 5 and STEP 6” of flash procedure.

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Wireless Coprocessor BinaryInstall addressVersionDate
    stm32wb5x_BLE_Stack_fw.bin0x080CC000v1.2.007/03/2019
    stm32wb5x_BLE_HCILayer_fw.bin0x080DC000v1.2.007/03/2019
    stm32wb5x_Thread_FTD_fw.bin0x0809F000v1.2.006/25/2019
    stm32wb5x_Thread_MTD_fw.bin0x080B5000v1.2.006/25/2019
    stm32wb5x_BLE_Thread_fw.bin0x08079000v1.2.007/03/2019
    stm32wb5x_Mac_802_15_4_fw.bin0x080E4000v1.2.006/25/2019
    stm32wb5x_rfmonitor_phy802_15_4_fw.bin0x080EC000v1.1.004/05/2019
    +
    +
    +
    + +
    +

    Main Changes

    +

    Associated changes in Firmware Upgrade Services (FUS):

    +
      +
    • Add support for STM32WB5xE(512K) and STM32WB5xC(256K) devices.
      • +
    • On STM32WB5xC and STM32WB5xE, it is mandatory to install FUS V1.0.2 before any other operation. Otherwise, the device might be locked in an unrecoverable state.
      • +
    +

    The following table provide the address to use in correspondence with the flash procedure of Wireless Coprocessor Binaries and the device to be used.

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Firmware Upgrade Services BinaryDeviceInstall addressVersionDate
    stm32wb5x_FUS_fw.binSTM32WB5xC(256K)0x0803E000v1.0.204/10/2019
    stm32wb5x_FUS_fw.binSTM32WB5xE(512K)0x0807E000v1.0.204/10/2019
    stm32wb5x_FUS_fw.binSTM32WB5xG(1M)0x080EC000v1.0.204/10/2019
    +

    Associated changes in Wireless Coprocessor Binary:

    +
      +
    • BLE System : fix stopMode2 race condition
      • +
    • BLE Security : fix pairing issue with numeric comparison
      • +
    +

    Binary Install Address and version : Provides Install address for the targeted binary to be used in “STEP 5 and STEP 6” of flash procedure.

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Wireless Coprocessor BinaryInstall addressVersionDate
    stm32wb5x_BLE_Stack_fw.bin0x080CC000v1.1.105/10/2019
    stm32wb5x_BLE_HCILayer_fw.bin0x080DC000v1.1.105/10/2019
    stm32wb5x_Thread_FTD_fw.bin0x0809F000v1.1.004/05/2019
    stm32wb5x_Thread_MTD_fw.bin0x080B5000v1.1.004/05/2019
    stm32wb5x_BLE_Thread_fw.bin0x08079000v1.1.004/05/2019
    stm32wb5x_Mac_802_15_4_fw.bin0x080E6000v1.1.004/05/2019
    stm32wb5x_rfmonitor_phy802_15_4_fw.bin0x080EC000v1.1.004/05/2019
    +
    +
    +
    + +
    +

    Main Changes

    +

    Introduction of the Firmware Upgrade Services (FUS):

    +
      +
    • This feature is embedded inside stm32wb5x_FUS_fw.bin.
      • +
    • This stm32wb5x_FUS_fw.bin v1.0.1 MUST be installed to use Wireless Coprocessor Binaries v1.1.0.
      • +
    • This stm32wb5x_FUS_fw.bin v1.0.1 CANNOT BE USED with the previous version of Wireless Coprocessor Binary.
      • +
    • All existing Cortex®-M4 user application are compatible without any update.
      • +
    +

    The following table provide the address to use in correspondence with the flash procedure of Wireless Coprocessor Binaries.

    + + + + + + + + + + + + + + + + + +
    Firmware Upgrade Services BinaryInstall addressVersionDate
    stm32wb5x_FUS_fw.bin0x080EC000 (On top of FUS v0.5.3)v1.0.104/05/2019
    +

    Introduction of the Customer Key Storage (CKS):

    +
      +
    • All Wireless Coprocessor Binaries embeds this new feature.
      • +
    • The FUS allows customer keys to be stored in the dedicated FUS Flash memory area and then to load the stored key to the AES1 in secure mode (AES1 key register accessed only by Cortex®-M0+ and data registers accessible by Cortex®-M4 user application).
      • +
    • You can refer to AN5185 : ST firmware upgrade services for STM32WB Series.
      • +
    +

    Associated changes in Wireless Coprocessor Binary:

    +
      +
    • BLE NVM : change behavior when NVM is full +
        +
      • Inform application before latest record
        • +
      • Erase and keep latest record when it is full
        • +
      • +
    • BLE Link layer : fix issue when pairing fails with SMP_SC_NUMCOMPARISON_FAILED, no response from the slave if the master sends again pairing_req.
      • +
    • BLE Link layer : fix issue Disconnection with error code 0x3D MIC Failure.
      • +
    • Thread 802_15_4 radio driver robustness improvement with additional error checks. The application is now notified in case of radio error detected inside the wireless binary.
      • +
    • Thread TxPower management improvement +
        +
      • New APIs provided on application side in order to control the Tx power :otPlatRadioGetTransmitPower() and otPlatRadioSetTransmitPower()
        • +
      • The default Tx power is now set to 0dBm
        • +
      • +
    +

    Binary Install Address and version : Provides Install address for the targeted binary to be used in “STEP 5 and STEP 6” of flash procedure.

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Wireless Coprocessor BinaryInstall addressVersionDate
    stm32wb5x_BLE_Stack_fw.bin0x080CC000v1.1.004/05/2019
    stm32wb5x_BLE_HCILayer_fw.bin0x080DC000v1.1.004/05/2019
    stm32wb5x_Thread_FTD_fw.bin0x0809F000v1.1.004/05/2019
    stm32wb5x_Thread_MTD_fw.bin0x080B5000v1.1.004/05/2019
    stm32wb5x_BLE_Thread_fw.bin0x08079000v1.1.004/05/2019
    stm32wb5x_Mac_802_15_4_fw.bin0x080E6000v1.1.004/05/2019
    stm32wb5x_rfmonitor_phy802_15_4_fw.bin0x080EC000v1.1.004/05/2019
    +
    +
    +
    + +
    +

    Main Changes

    +

    First release

    +

    First official release.

    +

    Binary Install Address and version : Provides Install address for the targeted binary to be used in “STEP 6” of flash procedure.

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Wireless Processor BinaryInstall addressVersionDate
    stm32wb5x_BLE_Stack_fw.bin0x080CB000v1.0.002/06/2019
    stm32wb5x_BLE_HCILayer_fw.bin0x080CD000v1.0.002/06/2019
    stm32wb5x_Thread_FTD_fw.bin0x0809F000v1.0.002/06/2019
    stm32wb5x_Thread_MTD_fw.bin0x080B5000v1.0.002/06/2019
    stm32wb5x_BLE_Thread_fw.bin0x08079000v1.0.002/06/2019
    stm32wb5x_Mac_802_15_4_fw.bin0x080E5000v1.0.002/06/2019
    stm32wb5x_rfmonitor_phy802_15_4_fw.bin0x080EA000v1.0.002/06/2019
    +
    +
    +
    +
    +
    +

    For complete documentation on STM32WBxx, visit: [www.st.com/stm32wb]

    +This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge. +
    + + diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_HCILayer_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_HCILayer_fw.bin new file mode 100644 index 000000000..88fc5932c Binary files /dev/null and b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_HCILayer_fw.bin differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_Stack_full_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_Stack_full_fw.bin new file mode 100644 index 000000000..9d50edf02 Binary files /dev/null and b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_Stack_full_fw.bin differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_Stack_light_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_Stack_light_fw.bin new file mode 100644 index 000000000..2e90ea558 Binary files /dev/null and b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_Stack_light_fw.bin differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_Thread_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_Thread_fw.bin new file mode 100644 index 000000000..4f2825f7d Binary files /dev/null and b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_Thread_fw.bin differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_Zigbee_FFD_static_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_Zigbee_FFD_static_fw.bin new file mode 100644 index 000000000..823320190 Binary files /dev/null and b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_Zigbee_FFD_static_fw.bin differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_FUS_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_FUS_fw.bin new file mode 100644 index 000000000..7d7bb6394 Binary files /dev/null and b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_FUS_fw.bin differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_FUS_fw_1_0_2.bin b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_FUS_fw_1_0_2.bin new file mode 100644 index 000000000..f75d7aff7 Binary files /dev/null and b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_FUS_fw_1_0_2.bin differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_Mac_802_15_4_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_Mac_802_15_4_fw.bin new file mode 100644 index 000000000..8a060c08b Binary files /dev/null and b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_Mac_802_15_4_fw.bin differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_Thread_FTD_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_Thread_FTD_fw.bin new file mode 100644 index 000000000..8846045b3 Binary files /dev/null and b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_Thread_FTD_fw.bin differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_Thread_MTD_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_Thread_MTD_fw.bin new file mode 100644 index 000000000..7d88e9777 Binary files /dev/null and b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_Thread_MTD_fw.bin differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_Zigbee_FFD_Full_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_Zigbee_FFD_Full_fw.bin new file mode 100644 index 000000000..9c69798d5 Binary files /dev/null and b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_Zigbee_FFD_Full_fw.bin differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_rfmonitor_phy802_15_4_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_rfmonitor_phy802_15_4_fw.bin new file mode 100644 index 000000000..85e2dc726 Binary files /dev/null and b/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_rfmonitor_phy802_15_4_fw.bin differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_BLE_HCILayer_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_BLE_HCILayer_fw.bin deleted file mode 100644 index 2b4efc711..000000000 Binary files a/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_BLE_HCILayer_fw.bin and /dev/null differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_BLE_Stack_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_BLE_Stack_fw.bin deleted file mode 100644 index 396c67c59..000000000 Binary files a/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_BLE_Stack_fw.bin and /dev/null differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_BLE_Thread_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_BLE_Thread_fw.bin deleted file mode 100644 index f4150ce70..000000000 Binary files a/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_BLE_Thread_fw.bin and /dev/null differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_FUS_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_FUS_fw.bin deleted file mode 100644 index f75d7aff7..000000000 Binary files a/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_FUS_fw.bin and /dev/null differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_Mac_802_15_4_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_Mac_802_15_4_fw.bin deleted file mode 100644 index 3c7429d82..000000000 Binary files a/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_Mac_802_15_4_fw.bin and /dev/null differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_Thread_FTD_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_Thread_FTD_fw.bin deleted file mode 100644 index 2438139ff..000000000 Binary files a/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_Thread_FTD_fw.bin and /dev/null differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_Thread_MTD_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_Thread_MTD_fw.bin deleted file mode 100644 index 96b07a62c..000000000 Binary files a/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_Thread_MTD_fw.bin and /dev/null differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_Zigbee_FFD_Full_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_Zigbee_FFD_Full_fw.bin deleted file mode 100644 index 508d2cdd3..000000000 Binary files a/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_Zigbee_FFD_Full_fw.bin and /dev/null differ diff --git a/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_rfmonitor_phy802_15_4_fw.bin b/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_rfmonitor_phy802_15_4_fw.bin deleted file mode 100644 index 85e2dc726..000000000 Binary files a/Projects/STM32WB_Copro_Wireless_Binaries/stm32wb5x_rfmonitor_phy802_15_4_fw.bin and /dev/null differ diff --git a/README.md b/README.md index 6676adfa4..3c13eb47e 100644 --- a/README.md +++ b/README.md @@ -11,7 +11,12 @@ The **STM32CubeWB MCU Package** projects are directly running on the STM32WB series boards. You can find in each Projects/*Board name* directories a set of software projects (Applications/Demonstration/Examples) +## Release note + +Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeWB/blob/master/Release_Notes.html). + ## Boards available + * STM32WB55 * [P-NUCLEO-WB55.Nucleo](https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html) * [P-NUCLEO-WB55.USBDongle](https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html) diff --git a/Release_Notes.html b/Release_Notes.html index 6461cd331..a8e0d2e98 100644 --- a/Release_Notes.html +++ b/Release_Notes.html @@ -52,6 +52,9 @@

    The HAL (Hardware Abstraction Layer) & LL (Low Layers) drivers provided within this package supports the following STM32WBxx product:

    • STM32WB55xx
      • +
    • STM32WB50xx
      • +
    • STM32WB35xx
      • +
    • STM32WB30xx

    The HAL and LL drivers provided within this package are compliant with MISRA-C®:2012 guidelines, and have been reviewed with a static analysis tool to eliminate possible run-time errors. Reports are available on demand.

    For quick getting started with the STM32CubeWB firmware package, refer to UM2550 and you can download firmware updates and all the latest documentation from www.st.com/stm32cubefw

    @@ -59,8 +62,9 @@
    • UM2550 : Getting started with STM32CubeWB for STM32WBxx Series.
    • UM2442 : Description of STM32WB HAL and low-layer drivers.
      • -
    • AN5292 : How to build a Bluetooth® Low Energy mesh application for STM32WBx5 microcontrollers
      • -
    • AN5155 : STM32Cube MCU Package examples for STM32WB Series
      • +
    • AN5289 : Building wireless applications with STM32WB Series microcontrollers
      • +
    • AN5292 : How to build a Bluetooth® Low Energy mesh application for STM32WBx5 microcontrollers
      • +
    • AN5155 : STM32Cube MCU Package examples for STM32WB Series
    • UM1721 : Developing Applications on STM32Cube with FatFs.
    • UM1722 : Developing Applications on STM32Cube with RTOS.
    @@ -68,9 +72,488 @@

    Update History

    - +

    Main Changes

    +

    Introduction of STM32WB5Mxx, STM32WB35xx, STM32WB30xx product and BLE/Zigbee static concurrent mode

    +
      +
    • STM32WB35xx: +
        +
      • Introduction of the STM32WB35xx and STM32WB30xx product
        • +
      • Add support inside CMSIS device under stm32wb35xx.h and stm32wb30xx.h.
        • +
      • This product can be used by enabling inside your project the define STM32WB35xx.
        • +
      • Add BLE wireless stack +
          +
        • The detailed usage is provided under release note
          • +
        • stm32wb3x_BLE_Stack_full_fw.bin +
            +
          • Full BLE Stack 5.0 certified : Link Layer, HCI, L2CAP, ATT, SM, GAP and GATT database
            • +
          • +
        • stm32wb3x_BLE_Stack_light_fw.bin +
            +
          • BLE Stack witch reduced features
            • +
          • Refer to release note for the details.
            • +
          • +
        • stm32wb3x_BLE_HCILayer_fw.bin +
            +
          • HCI Layer only mode 5.0 certified : Link Layer, HCI
            • +
          • +
        • +
      • Add HAL and LL support of STM32WB35xx. +
          +
        • The new I2S peripheral is introduced and provided inside stm32wbxx_hal_i2s.c.
          • +
        • +
      • Several applications are provided under Projects\NUCLEO-WB35CE to demonstrate the capabilities of the product. +
          +
        • Examples to demonstrate the capabilities of the peripherals, both in HAL, LL and a mix usage of HAL and LL.
          • +
        • Applications to demonstrate the integration of FreeRTOS and FatFs.
          • +
        • Applications to demonstrate the usage of the USB device.
          • +
        • BLE applications: +
            +
          • BLE_HeartRate
            • +
          • BLE_HeartRate_ota
            • +
          • BLE_HeartRateFreeRTOS
            • +
          • BLE_Ota
            • +
          • BLE_p2pClient
            • +
          • BLE_p2pServer
            • +
          • BLE_p2pServer_ota
            • +
          • BLE_TransparentMode
            • +
          • +
        • +
      • Support of Thread stack on STM32WB35 in FFD and RFD configurations +
          +
        • stm32wb3x_Thread_FTD_fw.bin +
            +
          • Full Thread Device
            • +
          • +
        • stm32wb3x_Thread_MTD_fw.bin +
            +
          • Minimal Thread Device
            • +
          • +
        • +
      • Support of the standalone MAC_802_15_4 protocol on STM32WB35 +
          +
        • stm32wb3x_Mac_802_15_4_fw.bin +
            +
          • MAC API is based on latest official IEEE Std 802.15.4-2011
            • +
          • Support of low power on MAC_802_15_4 standalone protocol
            • +
          • +
        • Support of External PA on all 802_15_4 supported protocol stacks
          • +
        • +
      • Introduction of STM32CubeIDE, an all-in-one multi-OS development tool, which is part of the STM32Cube software ecosystem. +
          +
        • The STM32CubeIDE file for all STM32WB35xx examples are provided ready to use.
          • +
        • +
      • +
    • STM32WB55xx: +
        +
      • Zigbee +
          +
        • This new release supports the following clusters: +
            +
          • Basic
            • +
          • Device Temperature Configuration,
            • +
          • Identify,
            • +
          • On/Off,
            • +
          • Power Profile,
            • +
          • Thermostat-UI-Config,
            • +
          • Ballast-Configuration,
            • +
          • Illuminance-Measurement,
            • +
          • Temperature Measurement,
            • +
          • Pressure Measurement,
            • +
          • Occupancy-Sensing,
            • +
          • Messaging
            • +
          • Meter Identification
            • +
          • +
        • Several applications are provided under Projects\P-NUCLEO-WB55.Nucleo\Applications\Zigbee to ilustrate the use of those clusters: +
            +
          • Zigbee_DevTemp_Server_Coord
            • +
          • Zigbee_DevTemp_Client_Router
            • +
          • Zigbee_PressMeas_Server_Coord
            • +
          • Zigbee_PressMeas_Client_Router
            • +
          • Zigbee_SE_Msg_Client_Coord
            • +
          • Zigbee_SE_Msg_Server_Router
            • +
          • +
        • Those application requires the usage of the stm32wb5x_Zigbee_FFD_Full_fw.bin (refer to release note)
          • +
        • +
      • Add BLE/Zigbee static concurrent mode support +
          +
        • A new application BLE_Zigbee_Static is provided under Projects\P-NUCLEO-WB55.Nucleo\Applications\BLE_Zigbee\BLE_Zigbee_Static.
          • +
        • This application requires the usage of the stm32wb5x_BLE_Zigbee_FFD_static_fw.bin (refer to release note)
          • +
        • +
      • +
    • STM32WB5Mxx: +
        +
      • Introduce the support od STM32WB5Mxx inside the cmsis device, the HAL and the LL library.
        • +
      • +
    +

    Contents

    +

    Projects

    +

    The STM32CubeWB Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains.

    +

    The exhaustive list of projects and their short description is provided in this table (STM32CubeProjectsList.html).

    + +

    Components

    + + + + + + + + + + + + + + + + + + +
    STM32WB5x Firmware Upgrade Services Binary
    NameVersionLicenseRelease note
    stm32wb5x_FUS_fw.binV1.0.2SLA0044 (binary release)release note
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    STM32WB5x Coprocessor Wireless Binaries
    NameVersionLicenseRelease note
    stm32wb5x_BLE_HCILayer_fw.binv1.5.0SLA0044 (binary release)release note
    stm32wb5x_BLE_Stack_full_fw.binv1.5.0SLA0044 (binary release)release note
    stm32wb5x_BLE_Stack_light_fw.binv1.5.0SLA0044 (binary release)release note
    stm32wb5x_BLE_Thread_fw.binv1.5.0SLA0044 (binary release)release note
    stm32wb5x_BLE_Zigbee_FFD_static_fw.binv1.5.0SLA0044 (binary release)release note
    stm32wb5x_Mac_802_15_4_fw.binv1.5.0SLA0044 (binary release)release note
    stm32wb5x_rfmonitor_phy802_15_4_fw.binv1.5.0SLA0044 (binary release)release note
    stm32wb5x_Thread_FTD_fw.binv1.5.0SLA0044 (binary release)release note
    stm32wb5x_Thread_MTD_fw.binv1.5.0SLA0044 (binary release)release note
    stm32wb5x_Zigbee_FFD_Full_fw.binv1.5.0SLA0044 (binary release)release note
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    STM32WB3x Coprocessor Wireless Binaries
    NameVersionLicenseRelease note
    stm32wb3x_BLE_HCILayer_fw.binv1.5.0SLA0044 (binary release)release note
    stm32wb3x_BLE_Stack_full_fw.binv1.5.0SLA0044 (binary release)release note
    stm32wb3x_BLE_Stack_light_fw.binv1.5.0SLA0044 (binary release)release note
    stm32wb3x_Mac_802_15_4_fw.binv1.5.0SLA0044 (binary release)release note
    stm32wb3x_Thread_FTD_fw.binv1.5.0SLA0044 (binary release)release note
    stm32wb3x_Thread_MTD_fw.binv1.5.0SLA0044 (binary release)release note
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Drivers
    NameVersionLicenseRelease note
    Cortex-M CMSISV5.4.0Apache License 2.0release notes
    STM32WB CMSISV1.4.0Apache License 2.0release notes
    STM32WBxx_HAL_DriverV1.5.0BSD 3-Clauserelease notes
    P-NUCLEO-WB55.USBDongleV1.0.1BSD 3-Clauserelease notes
    P-NUCLEO-WB55.NucleoV1.0.1BSD 3-Clauserelease notes
    NUCLEO-WB35CEV1.0.0BSD 3-Clauserelease notes
    BSP Adafruit ShieldV3.0.3BSD 3-Clauserelease notes
    BSP CommonV5.0.0BSD 3-Clauserelease notes
    BSP st7735V1.1.2BSD 3-Clauserelease notes
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Middleware
    NameVersionLicenseRelease note
    STM32 USB Device LibraryV2.5.3SLA0044release notes
    STM32 WPANV1.5.0SLA0044release notes
    FatFSR0.12cFatFs Licenserelease notes
    ST modified 20191011SLA0044release notes ST
    FreeRTOSV10.2.1MITrelease notes
    ST modified 20191213SLA0044release notes ST
    STM32_TouchSensing_LibraryV2.2.4SLA0044release notes
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Utilities
    NameVersionLicenseRelease note
    CPUV1.1.0BSD 3-Clauserelease notes
    FontsV1.0.0BSD 3-Clauserelease notes
    LogV1.0.0BSD 3-Clauserelease notes
    confV1.3.1BSD 3-Clauserelease notes
    lpmV1.1.0BSD 3-Clauserelease notes
    sequencerV1.2.1BSD 3-Clauserelease notes
    +

    Known Limitations

    +
      +
    • With the ability to change the Coprocessor Wireless Binaries Over The Air (OTA), it is possible to switch from one binary to another. Only, the following case is not possible due to available memory size: +
        +
      • Moving from stm32wb5x_BLE_Stack_fw.bin to stm32wb5x_BLE_Thread_fw.bin
        • +
      • +
    • The example RCC/RCC_ClockConfig encounter a hard fault after few keypressed. This will be corrected inside the next release.
      • +
    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2 + ST-Link
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25 + ST-Link
      • +
    • System Workbench for STM32 (SW4STM32) toolchain V2.7 + ST-Link
      • +
    • STM32CubeIDE toolchain V1.2.0 + ST-Link
      • +
    +

    Supported Devices and boards

    +
      +
    • STM32WB55xx, STM32WB50xx, STM32WB35xx and STM32WB30xx devices.
      • +
    • P-NUCLEO-WB55 kit composed of P-NUCLEO-WB55.Nucleo and P-NUCLEO-WB55.USBDongle
      • +
    • NUCLEO-WB35CE board.
      • +
    +

    Dependencies

    +

    This software release is compatible with:

    +
      +
    • STM32WB_Copro_Wireless_Binaries available under Projects/STM32WB_Copro_Wireless_Binaries
      • +
    +

    Several applications (BLE (Bluetooth low energy), Thread or Mac 802-15-4) are available under:

    +
      +
    • Projects/P-NUCLEO-WB55.Nucleo/Applications
      • +
    • Projects/P-NUCLEO-WB55.USBDongle/Applications
      • +
    +

    All of them are provided in source code and some of them are also available in binary format directly for ready to use usage:

    +
      +
    • Projects/P-NUCLEO-WB55.Nucleo/Applications/xxx/Binary/.hex
      • +
    • Projects/P-NUCLEO-WB55.USBDongle/Applications/xxx/Binary/.hex
      • +
    • Projects/NUCLEO-WB35CE/Applications/xxx/Binary/.hex
      • +
    +

    Each of them require a different coprocessor binary in order to behave correctly. This is documented inside each readme.txt of those applications.

    +

    You can refer to the release note for STM32WB5x or release note for STM32WB3x of the binaries for a detailed explanation on how to use and how to flash them.

    +
    +
    +
    + +
    +

    Main Changes

    Maintenance Release

    • BLE: @@ -95,15 +578,15 @@
  • Maintenance release for HAL and LL drivers.
    • -

    Contents

    -

    Projects

    +

    Contents

    +

    Projects

    The STM32CubeWB Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains.

    The exhaustive list of projects and their short description is provided in this table (STM32CubeProjectsList.html).

    -

    Components

    +

    Components

    @@ -349,7 +832,7 @@
    Firmware Upgrade Services Binary
    -

    Known Limitations

    +

    Known Limitations

    • With the ability to change the Coprocessor Wireless Binaries Over The Air (OTA), it is possible to switch from one binary to another. Only, the following case is not possible due to available memory size:
        @@ -357,18 +840,18 @@
    • BLE_MeshLightingDemo application is not functionnal under Linux platform.
    -

    Development Toolchains and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2 + ST-Link
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25 + ST-Link
    • System Workbench for STM32 (SW4STM32) toolchain V2.7 + ST-Link
    -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx and STM32WB50xx devices
    • P-NUCLEO-WB55 kit composed of P-NUCLEO-WB55.Nucleo and P-NUCLEO-WB55.USBDongle
    -

    Dependencies

    +

    Dependencies

    This software release is compatible with:

    • STM32WB_Copro_Wireless_Binaries available under Projects/STM32WB_Copro_Wireless_Binaries
      • @@ -390,7 +873,7 @@
      -

      Main Changes

      +

      Main Changes

      Introduction of ZIGBEE support

      STM32WB ecosystem keeps growing, now with the introduction of ZigBee protocol support as certified compliant platform, running on certified 802.15.4 2015 LLD MAC and PHY.

      The wireless stack is based on ZigBee pro 2017, R22 release version in order to propose a ZigBee 3.0 solution. First ON/OFF cluster is coming in this STM32CubeWB Firmware Package delivery release.

      @@ -419,15 +902,15 @@
    • Integration of BLE Mesh library v1.10.004
    • Maintenance release for CMSIS, HAL and LL drivers.
    -

    Contents

    -

    Projects

    +

    Contents

    +

    Projects

    The STM32CubeWB Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains.

    The exhaustive list of projects and their short description is provided in this table (STM32CubeProjectsList.html).

    -

    Components

    +

    Components

    @@ -667,7 +1150,7 @@
    Firmware Upgrade Services Binary
    -

    Known Limitations

    +

    Known Limitations

    • With the ability to change the Coprocessor Wireless Binaries Over The Air (OTA), it is possible to switch from one binary to another. Only, the following case is not possible due to available memory size:
        @@ -676,18 +1159,18 @@
      • Mac 802-15-4 applications are provided with EWARM IDE. MDK-ARM and SW4STM32 IDE are planned for a future release.
      • BLE_MeshLightingDemo application is not functionnal under Linux platform.
      -

      Development Toolchains and Compilers

      +

      Development Toolchains and Compilers

      • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2 + ST-Link
      • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25 + ST-Link
      • System Workbench for STM32 (SW4STM32) toolchain V2.7 + ST-Link
      -

      Supported Devices and boards

      +

      Supported Devices and boards

      • STM32WB55xx and STM32WB50xx devices
      • P-NUCLEO-WB55 kit composed of P-NUCLEO-WB55.Nucleo and P-NUCLEO-WB55.USBDongle
      -

      Dependencies

      +

      Dependencies

      This software release is compatible with:

      • STM32WB_Copro_Wireless_Binaries available under Projects/STM32WB_Copro_Wireless_Binaries
        • @@ -709,7 +1192,7 @@
        -

        Main Changes

        +

        Main Changes

        STM32WB50xx introduction and new features addition

        This release introduces the following feature:

          @@ -736,15 +1219,15 @@
        • Mesh Library V1.10.000
      -

      Contents

      -

      Projects

      +

      Contents

      +

      Projects

      The STM32CubeWB Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains.

      The exhaustive list of projects and their short description is provided in this table (STM32CubeProjectsList.html).

      -

      Components

      +

      Components

      @@ -984,7 +1467,7 @@
      Firmware Upgrade Services Binary
      -

      Known Limitations

      +

      Known Limitations

      • With the ability to change the Coprocessor Wireless Binaries Over The Air (OTA), it is possible to switch from one binary to another. Only, the following case is not possible due to available memory size:
          @@ -994,18 +1477,18 @@
        • BLE_MeshLightingDemo application is not functionnal under Linux platform.
        • Zigbee supports only OnOff cluster.
        -

        Development Toolchains and Compilers

        +

        Development Toolchains and Compilers

        • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2 + ST-Link
        • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25 + ST-Link
        • System Workbench for STM32 (SW4STM32) toolchain V2.7 + ST-Link
        -

        Supported Devices and boards

        +

        Supported Devices and boards

        • STM32WB55xx and STM32WB50xx devices
        • P-NUCLEO-WB55 kit composed of P-NUCLEO-WB55.Nucleo and P-NUCLEO-WB55.USBDongle
        -

        Dependencies

        +

        Dependencies

        This software release is compatible with:

        • STM32WB_Copro_Wireless_Binaries available under Projects/STM32WB_Copro_Wireless_Binaries
          • @@ -1027,7 +1510,7 @@
          -

          Main Changes

          +

          Main Changes

          Patch release for FUS V1.0.2,Wireless Coprocessor Binary bug fix and BLE Mesh Library improvements

          This release introduces the following feature:

            @@ -1053,8 +1536,8 @@
      -

      Contents

      -

      Projects

      +

      Contents

      +

      Projects

      The STM32CubeWB Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains.

      The exhaustive list of projects and their short description is provided in this table (STM32CubeProjectsList.html).

      Please note that the path of the example projects have been change to P-NUCLEO-WB55.Nucleo and P-NUCLEO-WB55.USBDongle.

      -

      Components

      +

      Components

      @@ -1284,7 +1767,7 @@
      Firmware Upgrade Services Binary
      -

      Known Limitations

      +

      Known Limitations

      • With the ability to change the Coprocessor Wireless Binaries Over The Air (OTA), it is possible to switch from one binary to another. Only, the following case is not possible due to available memory size:
          @@ -1302,18 +1785,18 @@
        • SW4STM32 project is compiled without optimisation. (With optimised size compilation, the virtual com port required for the application is not functionnal)
      -

      Development Toolchains and Compilers

      +

      Development Toolchains and Compilers

      • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2 + ST-Link
      • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25 + ST-Link
      • System Workbench for STM32 (SW4STM32) toolchain V2.7 + ST-Link
      -

      Supported Devices and boards

      +

      Supported Devices and boards

      • STM32WB55xx devices
      • P-NUCLEO-WB55 kit composed of P-NUCLEO-WB55.Nucleo and P-NUCLEO-WB55.USBDongle
      -

      Dependencies

      +

      Dependencies

      This software release is compatible with:

      • STM32WB_Copro_Wireless_Binaries available under Projects/STM32WB_Copro_Wireless_Binaries
        • @@ -1335,7 +1818,7 @@
        -

        Main Changes

        +

        Main Changes

        New features introduction and maintenance release

        This release introduces the following feature:

          @@ -1397,8 +1880,8 @@
        • Projects\P-NUCLEO-WB55.USBDongle\Applications\BLE
        • Projects\P-NUCLEO-WB55.USBDongle\Applications\Thread
        -

        Contents

        -

        Projects

        +

        Contents

        +

        Projects

        The STM32CubeWB Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains.

        The exhaustive list of projects and their short description is provided in this table (STM32CubeProjectsList.html).

        Please note that the path of the example projects have been change to P-NUCLEO-WB55.Nucleo and P-NUCLEO-WB55.USBDongle.

        -

        Components

        +

        Components

        @@ -1628,7 +2111,7 @@
        Firmware Upgrade Services Binary
        -

        Known Limitations

        +

        Known Limitations

        • With the ability to change the Coprocessor Wireless Binaries Over The Air (OTA), it is possible to switch from one binary to another. Only, the following case is not possible due to available memory size:
            @@ -1646,18 +2129,18 @@
          • SW4STM32 project is compiled without optimisation. (With optimised size compilation, the virtual com port required for the application is not functionnal)
        -

        Development Toolchains and Compilers

        +

        Development Toolchains and Compilers

        • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2 + ST-Link
        • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25 + ST-Link
        • System Workbench for STM32 (SW4STM32) toolchain V2.7 + ST-Link
        -

        Supported Devices and boards

        +

        Supported Devices and boards

        • STM32WB55xx devices
        • P-NUCLEO-WB55 kit composed of P-NUCLEO-WB55.Nucleo and P-NUCLEO-WB55.USBDongle
        -

        Dependencies

        +

        Dependencies

        This software release is compatible with:

        • STM32WB_Copro_Wireless_Binaries available under Projects/STM32WB_Copro_Wireless_Binaries
          • @@ -1679,7 +2162,7 @@
          -

          Main Changes

          +

          Main Changes

          First release

          First release of STM32CubeWB (STM32Cube for STM32WB Series) supporting STM32WB55xx devices.

          In the STM32CubeWB MCU Package, most of the examples and applications projects are generated with the STM32CubeMX tool to initialize the system, peripherals and middleware stacks.

          @@ -1695,15 +2178,15 @@
        • Projects\P-NUCLEO-WB55.USBDongle\Applications\BLE
        • Projects\P-NUCLEO-WB55.USBDongle\Applications\Thread
        -

        Contents

        -

        Projects

        +

        Contents

        +

        Projects

        The STM32CubeWB Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains.

        The exhaustive list of projects and their short description is provided in this table (STM32CubeProjectsList.html).

        -

        Components

        +

        Components

        @@ -1894,7 +2377,7 @@
        Coprocessor Wireless Binaries
        -

        Known Limitations

        +

        Known Limitations

        • BLE\BLE_p2pClient is provided with EWARM and MDK-ARM IDE. A connection issue with BLE_p2pServer is encounter with SW4STM32.
        • BLE\BLE_p2pRouter is provided with EWARM and MDK-ARM IDE. A connection issue with BLE_p2pServer is encounter with SW4STM32.
          • @@ -1924,18 +2407,18 @@
    -

    Development Toolchains and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2 + ST-Link
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25 + ST-Link
    • System Workbench for STM32 (SW4STM32) toolchain V2.7 + ST-Link
    -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx devices
    • P-NUCLEO-WB55 kit composed of P-NUCLEO-WB55.Nucleo and P-NUCLEO-WB55.USBDongle
    -

    Dependencies

    +

    Dependencies

    This software release is compatible with:

    • STM32WB_Copro_Wireless_Binaries available under Projects/STM32WB_Copro_Wireless_Binaries
      • diff --git a/Utilities/PC_Software/EWARMv8_STM32WB5MMG_Support_V0.1.zip b/Utilities/PC_Software/EWARMv8_STM32WB5MMG_Support_V0.1.zip new file mode 100644 index 000000000..f7e07d671 Binary files /dev/null and b/Utilities/PC_Software/EWARMv8_STM32WB5MMG_Support_V0.1.zip differ diff --git a/Utilities/PC_Software/Keil.STM32WB5MMG_DFP.0.0.1.zip b/Utilities/PC_Software/Keil.STM32WB5MMG_DFP.0.0.1.zip new file mode 100644 index 000000000..41f6f1aae Binary files /dev/null and b/Utilities/PC_Software/Keil.STM32WB5MMG_DFP.0.0.1.zip differ diff --git a/Utilities/conf/Release_Notes.html b/Utilities/conf/Release_Notes.html index 0ff4e9eb5..89c292514 100644 --- a/Utilities/conf/Release_Notes.html +++ b/Utilities/conf/Release_Notes.html @@ -4,7 +4,7 @@ - Release Notes for utilties configuration file + Release Notes for utilities configuration file